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Having inherited the concept of PALMiCE series, it realizes
comfortable operation by speedup, and ease-of-use by
compactification and provision for connection that requires
no power supply.
Furthermore, it is implemented with advanced multi-core
support and the debugging features that have been
enhanced
from CPU trace by own exertions.
 Attains speed up
In consideration for realization of better debugging
features and augmentation of trace memory, communication
between PALMiCE3 and the host computer has been made faster.
Because of which transfer of internal resource such as
traced data is faster and thereby makes debugging more
comfortable.
Inherited
Vbus support that requires no power supply
Having inherited Vbus support concept of PALMiCE series,
which requires no power supply, it realizes Vbus support
that requires no power supply even for AUD model with
enlarged trace memory capacity.
Even more compact body design
Although performance has been improved, it has been
materialized to even lighter and smaller body than the
former product.
Allows to add debugging environment at low cost
By additionally purchasing optional CSIDE that can be
used with the same product unit as that of the debugger
software "CSIDE" in standard set, debugging environment for
newly added CPU can be installed at low cost.
Improves the functionality for AUD tracing with distinct
features *2
Having been prepared
with triggers for AUD tracing and by added trace modes for
tracing before and after the trigger or between triggers,
now it allows precise tracing of the problem points. In
addition, it also implements branch address display by
sampling, CPU clock indication, and AUD trace fillup break
feature.
Advanced multi-core support
By making the internal resource of PALMiCE3 more powerful,
multi-core debugging, which requires more complicated debug
control, has been made possible.
Improves the functionality for AUD tracing with distinct
features
In AUD model, considering effective utilization of AUD
tracing, the following features have been enhanced.
- Augmented information allowance for AUD tracing
With AUD trace information allowance increased to 64-fold of
the existing products,
more branch information and
access data
can be acquired at a time.
- Trigger feature for precise identification of the
whereabouts of the problem *2
Having been prepared with 2 points of triggers, which were
not available in AUD tracing with the existing products, it
allows precise identification of the problem points. As
trigger, program address, access address,
or data
can be specified.
- Efficient analysis with various trace modes
*2
Besides Free mode, which
captures trace data till
break or trace stop, with Normal mode, which
captures before
and after the trigger points, and Start/End mode, which
captures from
Start trigger to End trigger, it now allows efficient trace
analysis.
CPU
tracing feature for efficient analysis of the program
behaviour
*2
Efficiently analyzes and presents the information captured
in CPU tracing (built in CPU, AUD, etc.).
Traceback feature which debugs based on the results of
CPU tracing
*2
Analyzes the contents of CPU trace memory to restore the
register and memory values, and thereby allows
implementation of pseudo execution and back step execution.
C0,C1 coverage feature implemented on the basis of AUD
tracing
*2
- Coverage display in Code Window
- Module coverage
display which shows the rate of coverage by
function unit
- Area coverage
display which shows the executed area of the
specified area
Status bar indication which allows to check the state
of the CPU easily
*2
- Indicates the CPU clock by sampling
Calculates the CPU clock and presents it in the
status bar.
- Indicates the address being executed by sampling
Samples branch addresses during the program execution and
presents them in the status bar.
Undo Trace into feature for undoing Trace into execution that went too far *1
Restores the results of execution back to original state by
putting virtual memory and virtual register back to the
values before change if Trace into execution (by single step
execution) went too far. It allows easy reviewing of simple
operations such as re-execution with the values changed and
checking of the state before branched.
Simulated I/O feature which implements printf
debugging through JTAG
*2
The debugger processes standard input/output of the user
program through JTAG. For example, when C library functions
such as printf() and scanf() are executed, they will be
output to Terminal Window of the debugger and keyboard input
will be forwarded to the user program.
This feature processes communication between the user
program and the debugger in real time without causing break
to CPU. Thus, it is perfect for debugging that pursues
realtimeliness.
Advanced multi-core support
Having been prepared with multi-core debugging specific
features such as synchronous execution, synchronous break,
and status indication which monitors the state of execution
by core, the program in which multiple cores work in
coordination can be debugged smoothly.
- Supported MCU: SH7265 Provided with integrated development environment "CSIDE" Version 5 as standard
Provided with integrated development environment as standard
for seamless implementation of development phases from
creation of the program to debugging.
CPU break feature *1
Allows after-execution break of the program and access break upon read/write of data.
Flash memory support
Supports debugging features such as software breakpoint
setting and normal memory rewriting, besides downloading to
NOR-type flash memory. Also, new devices can be added easily
by using definition file format.
Real-time stealing feature
*2 *3
Allows referencing/editing of the memory and I/O during user
program execution, and it is perfect for the target
debugging that pursues realtimeliness.
Performance feature
*4
Allows attempt for improvement in performance and
measurement of the program performance by measuring number
of various cycles, number of accesses, times of execution,
etc. during execution with measurement functionality of the
CPU.
Easy
update
By unique internet key issuing system, real-time support for
newly added CPU, update to the latest version, range of
optionally purchased software, etc. has been made feasible.
To assist debugging of the target program using OS, optional
debug library softwares have been prepared for each OS. Use
of the debug library will add features for OS state
indication, program operation check, etc.
µITRON support
By additionally purchasing optional RTOS Debug Library
besides debugger software, task tracing feature and status
display feature for real-time OS will be added.
(Specifications vary by µITRON.)
Operating environment
| Supported host: |
IBM PC/AT compatibles (DOS/V machines) |
| Host I/F: |
USB 2.0 |
| Supported OS: |
Windows Vista 32bit/7 32bit,64bit/8 32bit,64bit |
Connection illustration
- AUD model
- H-UDI model
SuperH family
| Supported CPUs |
Product summary |
Technical information |
SH7047F,SH7083F,SH7084F,SH7085F,SH7086F,
SH7144F,SH7145F,SH7146F,SH7149F,
SH7201,SH7203,SH7205,SH7206,SH7211F,SH7243F,
SH7261,SH7262,SH7263,SH7264,SH7265,
SH7285F,SH7286F,
SH7606,SH7615,SH7616,SH7618,SH7618A,SH7619,
SH7670,SH7671,SH7672,SH7673,
SH7705,SH7706,SH7709A,SH7709S,
SH7710,SH7712,SH7713,
SH7720,SH7721,SH7727,SH7729,SH7729R,SH7730,
SH7750,SH7750R,SH7750S,SH7751,SH7751R,
SH7760,SH7763,SH7764,SH7770,SH7774,
SH7780,SH7781,SH7785,
SH-Mobile1(SH7290),SH-Mobile3AS(SH7343),
SH-MobileJ(SH7294),SH-MobileL3V(SH7354),
SH-MobileR(SH7722),SH-MobileR2(SH7723),
SH-MobileV(SH7300)
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For details of specifications, check them in Product summary and Technical information.
*1: Specifications vary by CPU.
*2: Supported CPUs are SH-4A,
SH4AL-DSP, SH-2A, and SH2A-FPU.
*3: Supported CPUs are some of
SH-2.
*4: Supported CPUs are
some of SH-2, SH-2A, SH3-DSP, and SH-4 respectively.
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