diff -crN buildroot-2013.08.1-ckb-20150123-1/board/ckb/ckb-3352/patches/linux-3.2.1-004-ksz9021-timing.patch buildroot-2013.08.1-ckb-20150123-1_n/board/ckb/ckb-3352/patches/linux-3.2.1-004-ksz9021-timing.patch
*** buildroot-2013.08.1-ckb-20150123-1/board/ckb/ckb-3352/patches/linux-3.2.1-004-ksz9021-timing.patch	1970-01-01 09:00:00.000000000 +0900
--- buildroot-2013.08.1-ckb-20150123-1_n/board/ckb/ckb-3352/patches/linux-3.2.1-004-ksz9021-timing.patch	2015-09-18 20:48:43.160819788 +0900
***************
*** 0 ****
--- 1,79 ----
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/board-ckb-3352.c	2015-09-18 19:54:29.488881698 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/board-ckb-3352.c	2015-09-18 19:50:55.900885764 +0900
+ ***************
+ *** 1173,1210 ****
+   }
+   
+   #ifdef CONFIG_PHYLIB
+ ! volatile int reg_104 = 0x9090;
+ ! volatile int reg_105 = 0x0000;
+   
+   static int am33xx_evm_tx_clk_dly_phy_fixup(struct phy_device *phydev)
+   {
+   	int val;
+   
+   	/* min rx data delay */
+   	phy_write(phydev, 0x0b, 0x8105);
+ - 	//phy_write(phydev, 0x0c, 0xFFFFa);
+   	phy_write(phydev, 0x0c, reg_105);
+   	
+   	/* max rx/tx clock delay, min rx/tx control delay */
+ - 
+   	phy_write(phydev, 0x0b, 0x8104);
+   	phy_write(phydev, 0x0c, reg_104);	//163~182/ 207~222
+   
+ ! 	//phy_write(phydev, 0x0c, 0xf0f0);	//163~182/ 207~222
+ ! 	//phy_write(phydev, 0x0c, 0x70f0);   // 151~188/ 219~234
+ ! 	//phy_write(phydev, 0x0c, 0x7777); - NG
+ ! 	//phy_write(phydev, 0x0c, 007x70);  - Ping OK, iperf NG
+ ! 	//phy_write(phydev, 0x0c, 0x70A0);	//170~     226
+ ! 	//phy_write(phydev, 0x0c, 0x8080);	//170~     226
+ ! 	//phy_write(phydev, 0x0c, 0x8080);	//163~182/ 207~222
+ ! 	//phy_write(phydev, 0x0c, 0x9950);	//163~182/ 207~222
+ ! 	
+   	phy_write(phydev, 0x0b, 0x104);
+   	val =  phy_read(phydev, 0x0d);
+   	
+   	phy_write(phydev, 0x0b, 0x0105);
+   	val =  phy_read(phydev, 0x0d);
+   	
+   	return 0;
+   }
+   #endif
+ --- 1173,1208 ----
+   }
+   
+   #ifdef CONFIG_PHYLIB
+ ! volatile int reg_104 = 0x90f0;	/* Register 260 (104h) – RGMII Clock and Control Pad Skew */
+ ! volatile int reg_105 = 0x0000;	/* Register 261 (105h) – RGMII RX Data Pad Skew */
+ ! volatile int reg_106 = 0x4117;	/* Register 262 (106h) – RGMII TX Data Pad Skew */
+   
+   static int am33xx_evm_tx_clk_dly_phy_fixup(struct phy_device *phydev)
+   {
+   	int val;
+   
+ + 	/* min tx data delay */
+ + 	phy_write(phydev, 0x0b, 0x8106);
+ + 	phy_write(phydev, 0x0c, reg_106);
+ + 
+   	/* min rx data delay */
+   	phy_write(phydev, 0x0b, 0x8105);
+   	phy_write(phydev, 0x0c, reg_105);
+   	
+   	/* max rx/tx clock delay, min rx/tx control delay */
+   	phy_write(phydev, 0x0b, 0x8104);
+   	phy_write(phydev, 0x0c, reg_104);	//163~182/ 207~222
+   
+ ! 	/* Phy read test */
+   	phy_write(phydev, 0x0b, 0x104);
+   	val =  phy_read(phydev, 0x0d);
+   	
+   	phy_write(phydev, 0x0b, 0x0105);
+   	val =  phy_read(phydev, 0x0d);
+   	
+ + 	phy_write(phydev, 0x0b, 0x0106);
+ + 	val =  phy_read(phydev, 0x0d);
+ + 	
+   	return 0;
+   }
+   #endif
