diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/Config.in buildroot-2013.08.1-ckb-20141129-1/board/ckb/Config.in
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/Config.in	2014-07-08 19:25:34.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/Config.in	2014-11-26 09:12:54.000000000 +0900
***************
*** 231,236 ****
--- 231,242 ----
  	default y
  	help
  		This will build the sample application for EXT_CN CS1.
+ 
+ config BR2_CKB_WDT_SAMPLE
+ 	bool "WDT sample"
+ 	default y
+ 	help
+ 		This will build the sample application for Watchdog timer.
  endif
  
  if BR2_BOARD_CKB_RZ
diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/Config.in.bak buildroot-2013.08.1-ckb-20141129-1/board/ckb/Config.in.bak
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/Config.in.bak	2014-05-26 14:19:57.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/Config.in.bak	1970-01-01 09:00:00.000000000 +0900
***************
*** 1,234 ****
- if BR2_arm && BR2_arm926t
- config BR2_BOARD_CKB_1808
- 	bool "CKB-1808 support" 
- 	select BR2_BOARD_CKB
- 	help
-          Select this option for building for CKB-1808 board.
- endif
- 
- if BR2_arm && BR2_cortex_a8
- config BR2_BOARD_CKB_3352
- 	bool "CKB-3352 support"
- 	select BR2_BOARD_CKB
- 	help
-          Select this option for building for CKB-3352 board.
- endif
- 
- if BR2_arm && BR2_cortex_a9
- config BR2_BOARD_CKB_RZ
- 	bool "CKB-RZ/A1H support" 
- 	help
-          Select this option for building for CKB-RZ/A1H board.
- endif
- 
- if BR2_BOARD_CKB_1808
- 
- choice
- 	prompt "RAM memory size"
- 	default BR2_CKB_1808_128MB
- 	help
- 	  Select the DDR RAM memory size on the target
- 
- config BR2_CKB_1808_32MB
- 	bool "32MB"
- 	
- config BR2_CKB_1808_128MB
- 	bool "128MB"
- 	
- endchoice
- 
- endif
- 
- if BR2_BOARD_CKB_1808 || BR2_BOARD_CKB_3352 || BR2_BOARD_CKB_RZ
- 
- config BR2_CKB_LCD_SUPPORT
- 	bool "Support LCD"
- 	help
- 	 Select this option to add LCD support.
- 
- choice
- 	prompt "Select LCD board"
- 	depends on BR2_CKB_LCD_SUPPORT
- 	help
- 	 Select the LCD board.
- 
- if BR2_BOARD_CKB_1808 || BR2_BOARD_CKB_3352
- config BR2_CKB_LCD_01
- 	bool "CKB LCD-01"
- 	help
- 	 Support for Computex CKB LCD_01 LCD board (Visionx KTM050AL02).
- endif
- 	
- config BR2_CKB_LCD_02
- 	bool "CKB LCD-02"
- 	help
- 	 Support for Computex CKB LCD_02 LCD board (Kyocera TCG070WVLPAAFA_AA00).
- 
- if BR2_BOARD_CKB_RZ
- config BR2_VISIONX_KTM050AL02
- 	bool "Visionx KTM050AL02"
- 	help
- 	 Support for Visionx KTM050AL02 LCD panel.
- endif
- 
- endchoice
- endif
- 
- if BR2_BOARD_CKB_1808
- config  BR2_CKB_VPIF_SUPPORT
- 	bool "Support VPIF"
- 	help
- 	  Select this option to add VPIF support (camera).
- endif
- 
- if BR2_BOARD_CKB_3352
- 
- config BR2_CKB_DVI_SUPPORT
- 	bool "Support DVI"
- 	help
- 	Select this option to add DVI support.
- 
- endif
- 
- if BR2_BOARD_CKB_RZ
- config BR2_CKB_LVDS_SUPPORT
- 	bool "Support LVDS"
- 	help
- 	Select this option to add LVDS support.
- 
- endif
- 
- config BR2_CKB_DISPLAY_DVI_RESOLUTIONS
- 	bool "Display DVI resolutions when a device is connected"
- 	depends on BR2_CKB_DVI_SUPPORT
- 	help
- 	Select this option to display the DVI resolution read from the
- 	device on the terminal. Some resolutions may not be supported.
- 	The file /etc/fb.modes will have a list of resolutions that are
- 	be supported.
- 
- config  BR2_CKB_DISPLAY_UNSUPPORTED_DVI_RESOLUTIONS
- 	bool "Display DVI unsupported resolutions"
- 	depends on BR2_CKB_DVI_SUPPORT
- 	help
- 	Select this option to display the DVI resolution that have been
- 	ignored because of incompatibility.
- 
- if BR2_BOARD_CKB_3352
- config BR2_CKB_LCD_CLOCK_CLOSEST_MATCH
- 	bool "Compute best match for LCD/DVI output clock"
- 	depends on BR2_CKB_LCD_SUPPORT || BR2_CKB_DVI_SUPPORT
- 	help
- 	This option finds the best matching output clock for LCD/DVI
- 	and uses it.
- endif
- 
- config BR2_CKB_DISPLAY_EASY_SWITCH_MODE
- 	bool "Use numbers instead of names in /etc/fb.modes"
- 	depends on BR2_CKB_LCD_SUPPORT || BR2_CKB_DVI_SUPPORT || BR2_CKB_LVDS_SUPPORT
- 	help
- 	  This option makes it easier to switch the LCD configuration bootloader.
- 	  Instead of "fbset <mode_name>", "fbset <number>" can be used.
- 	  <number> will be shorter than <mode_name>.
- 
- 
- if BR2_BOARD_CKB_1808 || BR2_BOARD_CKB_3352 || BR2_BOARD_CKB_RZ
- 
- if BR2_CKB_LCD_SUPPORT || BR2_CKB_DVI_SUPPORT || BR2_CKB_LVDS_SUPPORT
- config BR2_TITLE_IMAGE_FILE_NAME
- 	string "Title BMP file"
- 	default "dl/pics/title_400x240.bmp"
- 	help
- 	  Complete path to the title logo BMP file
- 	  that will be displayed when the target
- 	  boots.
- endif
- 
- config BR2_CMJ100_MODULE
- 	bool "Compile CMJ100 driver"
- 	select BR2_CMJ100_FW_IN_KERNEL if BR2_BOARD_CKB_3352
- 	default y
- 	help
- 		This will build the CMJ100 driver module for Linux 3.2.x or 3.8.x
- 		depending on the Kernel version that has been selected.
- 
- config BR2_CMJ100_FW_IN_KERNEL
- 	bool "Include CMJ100 firmware in Kernel"
- 	depends on BR2_BOARD_CKB_3352 && BR2_CMJ100_MODULE
- 	default y
- 	help
- 		This will include the CMJ100 firmware binary in the Kernel
- 		image (Needed for Linux 3.2.x and below)
- 
- config BR2_PACKAGE_CSIDED
- 	bool "Compile CSIDED"
- 	default y
- 	help
- 	  CSIDED is the target daemon for "CSIDE for C-Shark" by COMPUTEX.
- 	  http://http://www.computex.co.jp/ftproot/pub/ckb/linux
- 
- config BR2_PACKAGE_LIBCDBMEM
- 	bool "Compile Libcdcmem"
- 	default y
- 	help
- 	  LIBCDBMEM is memory profile for "CSIDE for PALMiCE3 Linux-APD library" by COMPUTEX.
- 
- config BR2_CKB_LISTUP_APP
- 	bool "listup"
- 	default y
- 	help
- 		This will build the listup application.
- 
- 
- comment "Sample applications"
- 
- config BR2_ENABLE_AP_DEBUG
- 	bool "Enable sample application debugging"
- 	default n
- 	
- 
- if BR2_BOARD_CKB_1808
- 
- config BR2_CKB_VPIF_SAMPLES
- 	bool "VPIF camera applications"
- 	default y
- 	help
- 		This will build vpif_cam_app, vpif_cam_streamer and vpif_tcp_cam_streamer applications.
- 
- endif
- 		
- source "board/ckb/common/samples/Config-usbcam.in"		
- source "board/ckb/common/samples/Config-samples.in"
- 
- if BR2_BOARD_CKB_1808
- config BR2_CKB_EXT_CN5_MEM_SAMPLE
- 	bool "External connector memory sample"
- 	default y
- 	help
- 		This will build the sample application for EXT_CN CS5.
- endif
- 
- if BR2_BOARD_CKB_3352
- config BR2_CKB_EXT_CN1_MEM_SAMPLE
- 	bool "External connector memory sample"
- 	default y
- 	help
- 		This will build the sample application for EXT_CN CS1.
- endif
- 
- if BR2_BOARD_CKB_RZ
- config BR2_CKB_EX1_CN_CS2_MEM_SAMPLE
- 	bool "EX1_CN CS2 memory sample"
- 	default y
- 	help
- 		This will build the sample application for the External connector EX1_CN CS2.
- 	
- config BR2_CKB_EX1_CN_CS2_MEM_16_SAMPLE
- 	bool "EX1_CN 16 bit CS2 memory sample"
- 	default y
- 	help
- 		This will build the 16 bit sample application for the External connector EX1_CN CS2.
- endif
- 
- endif
- 
--- 0 ----
diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/Makefile.in buildroot-2013.08.1-ckb-20141129-1/board/ckb/Makefile.in
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/Makefile.in	2014-07-28 11:26:12.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/Makefile.in	2014-11-27 16:37:58.000000000 +0900
***************
*** 108,127 ****
  spidev_test-clean:
  	make clean -C $(BOARD_COMMON_DIR)/samples/spidev_test
  
- yuv:
- 	@$(call MESSAGE, "**************************************************************")
- 		@$(call MESSAGE, "Building YUV Camera application \(yuv_usb_cam_app\)")
- 	@$(call MESSAGE, "**************************************************************")
- 	make CROSS_COMPILE="$(TARGET_CROSS)" \
- 		CFLAGS="$(TARGET_CFLAGS)" \
- 		LDFLAGS="$(TARGET_LDFLAGS)" \
- 		KERNEL_HEADERS="$(STAGING_DIR)/usr" \
- 		OUTPUT_DIR="$(O)" \
- 		APP_DEBUG=$(APP_DEBUG) \
- 		-C $(BOARD_COMMON_DIR)/samples/yuv_usb_cam_app
- 	 cp $(BOARD_COMMON_DIR)/samples/yuv_usb_cam_app/yuv_usb_cam_app $(TARGET_DIR)/bin/
- #	 cp $(BOARD_COMMON_DIR)/samples/usb_cam_app/usb_cam_app $(TARGET_DIR)/../target_without_usr/bin/
- 
  usb_cam_app:
  	@$(call MESSAGE, "**************************************************************")
  		@$(call MESSAGE, "Building USB Camera application \(usb_cam_app\)")
--- 108,113 ----
***************
*** 494,498 ****
  
  POST_LINUX_TARGETS += legal-info
  
- # POST_LINUX_TARGETS += yuv
- 
--- 480,482 ----
diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-1808/before_packing_fs.sh buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-1808/before_packing_fs.sh
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-1808/before_packing_fs.sh	1970-01-01 09:00:00.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-1808/before_packing_fs.sh	2014-02-13 09:03:05.000000000 +0900
***************
*** 0 ****
--- 1,14 ----
+ #!/bin/sh
+ #Environment variables; $TARGET_DIR is passed as the argument by buildroot
+ export TARGET_FS_FOLDER=$1
+ 
+ # legal-info licenses.txt
+ mkdir -p $TARGET_FS_FOLDER/etc/legal-info
+ cp $TARGET_FS_FOLDER/../legal-info/licenses.txt $TARGET_FS_FOLDER/etc/legal-info/licenses.txt
+ 
+ #Change permissions
+ chmod +x $TARGET_FS_FOLDER/etc/udhcpc.scripts 
+ chmod +x $TARGET_FS_FOLDER/etc/init.d/*
+ chmod +x $TARGET_FS_FOLDER/etc/network/wlan-scripts/*
+ #chmod +x $TARGET_FS_FOLDER/bin/*
+ sync
diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-1808/custom_fs.sh buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-1808/custom_fs.sh
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-1808/custom_fs.sh	2014-02-13 09:03:05.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-1808/custom_fs.sh	1970-01-01 09:00:00.000000000 +0900
***************
*** 1,14 ****
- #!/bin/sh
- #Environment variables; $TARGET_DIR is passed as the argument by buildroot
- export TARGET_FS_FOLDER=$1
- 
- # legal-info licenses.txt
- mkdir -p $TARGET_FS_FOLDER/etc/legal-info
- cp $TARGET_FS_FOLDER/../legal-info/licenses.txt $TARGET_FS_FOLDER/etc/legal-info/licenses.txt
- 
- #Change permissions
- chmod +x $TARGET_FS_FOLDER/etc/udhcpc.scripts 
- chmod +x $TARGET_FS_FOLDER/etc/init.d/*
- chmod +x $TARGET_FS_FOLDER/etc/network/wlan-scripts/*
- #chmod +x $TARGET_FS_FOLDER/bin/*
- sync
--- 0 ----
diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-1808/extern_fs.sh buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-1808/extern_fs.sh
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-1808/extern_fs.sh	2014-06-23 15:15:57.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-1808/extern_fs.sh	1970-01-01 09:00:00.000000000 +0900
***************
*** 1,65 ****
- #!/bin/sh
- #Environment variables passed as the arguments by buildroot
- # $1 : Root FS folder
- # $2 : Folder to which /usr has been moved
- 
- export ROOT_FS_FOLDER=$1
- export USR_FOLDER=$2
- 
- #copy important libs/bins from sdcard directory to the root folder directory
- 	mkdir -p $ROOT_FS_FOLDER/usr/bin
- 	mkdir -p $ROOT_FS_FOLDER/usr/sbin
- 	mkdir -p $ROOT_FS_FOLDER/usr/lib
- 	mkdir -p $ROOT_FS_FOLDER/usr/local/bin
- 	cp -rpd $USR_FOLDER/local/bin/* $ROOT_FS_FOLDER/usr/local/bin/
- 	cp -rpd $USR_FOLDER/bin/iperf $ROOT_FS_FOLDER/usr/bin/
- 	cp -rpd $USR_FOLDER/bin/ts_test $ROOT_FS_FOLDER/usr/bin/
- 	cp -rpd $USR_FOLDER/bin/ntpdate $ROOT_FS_FOLDER/usr/bin/
- 	cp -rpd $USR_FOLDER/bin/inotify* $ROOT_FS_FOLDER/usr/bin/
- 	cp -rpd $USR_FOLDER/bin/i2c* $ROOT_FS_FOLDER/usr/bin/
- 	cp -rpd $USR_FOLDER/lib/ts* $ROOT_FS_FOLDER/usr/lib/
- 	cp -rpd $USR_FOLDER/lib/libts* $ROOT_FS_FOLDER/usr/lib
- 	cp -rpd $USR_FOLDER/lib/libintl.* $ROOT_FS_FOLDER/usr/lib
- 	cp -rpd $USR_FOLDER/lib/libnl* $ROOT_FS_FOLDER/usr/lib
- 	cp -rpd $USR_FOLDER/lib/libssl* $ROOT_FS_FOLDER/usr/lib/
- 	cp -rpd $USR_FOLDER/lib/libcrypto* $ROOT_FS_FOLDER/usr/lib/
- 	cp -rpd $USR_FOLDER/lib/libgpg-error* $ROOT_FS_FOLDER/usr/lib/
- 	cp -rpd $USR_FOLDER/lib/libdbus* $ROOT_FS_FOLDER/usr/lib/
- 	cp -rpd $USR_FOLDER/lib/libstdc++.so* $ROOT_FS_FOLDER/usr/lib/
- 	cp -rpd $USR_FOLDER/lib/crda $ROOT_FS_FOLDER/usr/lib/
- 	cp -rpd $USR_FOLDER/lib/avahi $ROOT_FS_FOLDER/usr/lib/
- 	cp -rpd $USR_FOLDER/lib/libavahi-* $ROOT_FS_FOLDER/usr/lib/
- 	cp -rpd $USR_FOLDER/lib/libdaemon.* $ROOT_FS_FOLDER/usr/lib/
- 	cp -rpd $USR_FOLDER/lib/libexpat.* $ROOT_FS_FOLDER/usr/lib/
- 	cp -rpd $USR_FOLDER/lib/libgcrypt.* $ROOT_FS_FOLDER/usr/lib/
- 	cp -rpd $USR_FOLDER/sbin/iw $ROOT_FS_FOLDER/usr/sbin/
- 	cp -rpd $USR_FOLDER/sbin/wpa_* $ROOT_FS_FOLDER/usr/sbin/
- 	cp -rpd $USR_FOLDER/sbin/hostapd $ROOT_FS_FOLDER/usr/sbin/
- 	cp -rpd $USR_FOLDER/sbin/mtd* $ROOT_FS_FOLDER/usr/sbin/
- 	cp -rpd $USR_FOLDER/sbin/rtc* $ROOT_FS_FOLDER/usr/sbin/
- 	cp -rpd $USR_FOLDER/sbin/fbset* $ROOT_FS_FOLDER/usr/sbin/
- 	cp -rpd $USR_FOLDER/sbin/avahi-* $ROOT_FS_FOLDER/usr/sbin/
- 	cp -rpd $USR_FOLDER/share/avahi $ROOT_FS_FOLDER/usr/share/
- 	cp -rpd $USR_FOLDER/sbin/fbset* $ROOT_FS_FOLDER/usr/sbin/
- 	cp -rpd $USR_FOLDER/share/udhcpc $ROOT_FS_FOLDER/usr/share/
- 	cp -rpd $USR_FOLDER/bin/_cside* $ROOT_FS_FOLDER/usr/bin/
- 	cp -rpd $USR_FOLDER/bin/cside* $ROOT_FS_FOLDER/usr/bin/
- 	cp -rpd $USR_FOLDER/bin/libcsidemprof.so $ROOT_FS_FOLDER/usr/bin/
- 	cp -rpd $USR_FOLDER/lib/libcdbmem.so $ROOT_FS_FOLDER/lib/
- # - IPTABLES
- #	cp -rpd $USR_FOLDER/sbin/iptables* $ROOT_FS_FOLDER/usr/sbin/
- #	cp -rpd $USR_FOLDER/sbin/xtables* $ROOT_FS_FOLDER/usr/sbin/
- # - SDL
- #	cp -rpd $USR_FOLDER/lib/libSDL* $ROOT_FS_FOLDER/usr/lib/
- 	cp -rpd $USR_FOLDER/lib/libjpeg.so* $ROOT_FS_FOLDER/usr/lib/
- #	cp -rpd $USR_FOLDER/lib/libtiff.so* $ROOT_FS_FOLDER/usr/lib/
- #	cp -rpd $USR_FOLDER/lib/libz.so* $ROOT_FS_FOLDER/usr/lib/
- #	cp -rpd $USR_FOLDER/lib/libfreetype.so* $ROOT_FS_FOLDER/usr/lib/
- 
- #End
- 
- #Change permissions
- chmod +x $ROOT_FS_FOLDER/etc/udhcpc.scripts 
- chmod +x $ROOT_FS_FOLDER/etc/init.d/*
- chmod +x $ROOT_FS_FOLDER/etc/network/wlan-scripts/*
- sync
--- 0 ----
diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-1808/usr_to_rootfs.sh buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-1808/usr_to_rootfs.sh
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-1808/usr_to_rootfs.sh	1970-01-01 09:00:00.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-1808/usr_to_rootfs.sh	2014-11-28 08:58:16.000000000 +0900
***************
*** 0 ****
--- 1,65 ----
+ #!/bin/sh
+ #Environment variables passed as the arguments by buildroot
+ # $1 : Root FS folder
+ # $2 : Folder to which /usr has been moved
+ 
+ export ROOT_FS_FOLDER=$1
+ export USR_FOLDER=$2
+ 
+ #copy important libs and bins from /usr directory to the root folder directory
+ 	mkdir -p $ROOT_FS_FOLDER/usr/bin
+ 	mkdir -p $ROOT_FS_FOLDER/usr/sbin
+ 	mkdir -p $ROOT_FS_FOLDER/usr/lib
+ 	mkdir -p $ROOT_FS_FOLDER/usr/local/bin
+ 	cp -rpd $USR_FOLDER/local/bin/* $ROOT_FS_FOLDER/usr/local/bin/
+ 	cp -rpd $USR_FOLDER/bin/iperf $ROOT_FS_FOLDER/usr/bin/
+ 	cp -rpd $USR_FOLDER/bin/ts_test $ROOT_FS_FOLDER/usr/bin/
+ 	cp -rpd $USR_FOLDER/bin/ntpdate $ROOT_FS_FOLDER/usr/bin/
+ 	cp -rpd $USR_FOLDER/bin/inotify* $ROOT_FS_FOLDER/usr/bin/
+ 	cp -rpd $USR_FOLDER/bin/i2c* $ROOT_FS_FOLDER/usr/bin/
+ 	cp -rpd $USR_FOLDER/lib/ts* $ROOT_FS_FOLDER/usr/lib/
+ 	cp -rpd $USR_FOLDER/lib/libts* $ROOT_FS_FOLDER/usr/lib
+ 	cp -rpd $USR_FOLDER/lib/libintl.* $ROOT_FS_FOLDER/usr/lib
+ 	cp -rpd $USR_FOLDER/lib/libnl* $ROOT_FS_FOLDER/usr/lib
+ 	cp -rpd $USR_FOLDER/lib/libssl* $ROOT_FS_FOLDER/usr/lib/
+ 	cp -rpd $USR_FOLDER/lib/libcrypto* $ROOT_FS_FOLDER/usr/lib/
+ 	cp -rpd $USR_FOLDER/lib/libgpg-error* $ROOT_FS_FOLDER/usr/lib/
+ 	cp -rpd $USR_FOLDER/lib/libdbus* $ROOT_FS_FOLDER/usr/lib/
+ 	cp -rpd $USR_FOLDER/lib/libstdc++.so* $ROOT_FS_FOLDER/usr/lib/
+ 	cp -rpd $USR_FOLDER/lib/crda $ROOT_FS_FOLDER/usr/lib/
+ 	cp -rpd $USR_FOLDER/lib/avahi $ROOT_FS_FOLDER/usr/lib/
+ 	cp -rpd $USR_FOLDER/lib/libavahi-* $ROOT_FS_FOLDER/usr/lib/
+ 	cp -rpd $USR_FOLDER/lib/libdaemon.* $ROOT_FS_FOLDER/usr/lib/
+ 	cp -rpd $USR_FOLDER/lib/libexpat.* $ROOT_FS_FOLDER/usr/lib/
+ 	cp -rpd $USR_FOLDER/lib/libgcrypt.* $ROOT_FS_FOLDER/usr/lib/
+ 	cp -rpd $USR_FOLDER/sbin/iw $ROOT_FS_FOLDER/usr/sbin/
+ 	cp -rpd $USR_FOLDER/sbin/wpa_* $ROOT_FS_FOLDER/usr/sbin/
+ 	cp -rpd $USR_FOLDER/sbin/hostapd $ROOT_FS_FOLDER/usr/sbin/
+ 	cp -rpd $USR_FOLDER/sbin/mtd* $ROOT_FS_FOLDER/usr/sbin/
+ 	cp -rpd $USR_FOLDER/sbin/rtc* $ROOT_FS_FOLDER/usr/sbin/
+ 	cp -rpd $USR_FOLDER/sbin/fbset* $ROOT_FS_FOLDER/usr/sbin/
+ 	cp -rpd $USR_FOLDER/sbin/avahi-* $ROOT_FS_FOLDER/usr/sbin/
+ 	cp -rpd $USR_FOLDER/share/avahi $ROOT_FS_FOLDER/usr/share/
+ 	cp -rpd $USR_FOLDER/sbin/fbset* $ROOT_FS_FOLDER/usr/sbin/
+ 	cp -rpd $USR_FOLDER/share/udhcpc $ROOT_FS_FOLDER/usr/share/
+ 	cp -rpd $USR_FOLDER/bin/_cside* $ROOT_FS_FOLDER/usr/bin/
+ 	cp -rpd $USR_FOLDER/bin/cside* $ROOT_FS_FOLDER/usr/bin/
+ 	cp -rpd $USR_FOLDER/bin/libcsidemprof.so $ROOT_FS_FOLDER/usr/bin/
+ 	cp -rpd $USR_FOLDER/lib/libcdbmem.so $ROOT_FS_FOLDER/lib/
+ # - IPTABLES
+ #	cp -rpd $USR_FOLDER/sbin/iptables* $ROOT_FS_FOLDER/usr/sbin/
+ #	cp -rpd $USR_FOLDER/sbin/xtables* $ROOT_FS_FOLDER/usr/sbin/
+ # - SDL
+ #	cp -rpd $USR_FOLDER/lib/libSDL* $ROOT_FS_FOLDER/usr/lib/
+ 	cp -rpd $USR_FOLDER/lib/libjpeg.so* $ROOT_FS_FOLDER/usr/lib/
+ #	cp -rpd $USR_FOLDER/lib/libtiff.so* $ROOT_FS_FOLDER/usr/lib/
+ #	cp -rpd $USR_FOLDER/lib/libz.so* $ROOT_FS_FOLDER/usr/lib/
+ #	cp -rpd $USR_FOLDER/lib/libfreetype.so* $ROOT_FS_FOLDER/usr/lib/
+ 
+ #End
+ 
+ #Change permissions
+ chmod +x $ROOT_FS_FOLDER/etc/udhcpc.scripts 
+ chmod +x $ROOT_FS_FOLDER/etc/init.d/*
+ chmod +x $ROOT_FS_FOLDER/etc/network/wlan-scripts/*
+ sync
diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-3352/Makefile.in buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-3352/Makefile.in
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-3352/Makefile.in	2014-06-19 09:06:38.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-3352/Makefile.in	2014-11-26 09:13:07.000000000 +0900
***************
*** 9,15 ****
  			gui1_app-clean kensa_app-clean launcher_app-clean \
  			led_sample-clean ts_led-clean ts_test2-clean gpio_int-clean \
  			spidev_test-clean \
! 			ext_cn1_mem-clean \
  			ckb_3352_uart_flasher-clean
  
  clean_message:
--- 9,15 ----
  			gui1_app-clean kensa_app-clean launcher_app-clean \
  			led_sample-clean ts_led-clean ts_test2-clean gpio_int-clean \
  			spidev_test-clean \
! 			ext_cn1_mem-clean wdt_sample-clean \
  			ckb_3352_uart_flasher-clean
  
  clean_message:
***************
*** 52,57 ****
--- 52,73 ----
  ext_cn1_mem-clean:
  	make clean -C $(BOARD_DIR)/samples/ext_cn_mem
  
+ wdt_sample:
+ 	@$(call MESSAGE, "**************************************************************")
+ 	@$(call MESSAGE, "Building WDT sample application \(saWatchdog\)")
+ 	@$(call MESSAGE, "**************************************************************")
+ 	make CROSS_COMPILE="$(TARGET_CROSS)" \
+ 		CFLAGS="$(TARGET_CFLAGS)" \
+ 		LDFLAGS="$(TARGET_LDFLAGS)" \
+ 		KERNEL_HEADERS="$(STAGING_DIR)/usr" \
+ 		OUTPUT_DIR="$(O)" \
+ 		APP_DEBUG=$(APP_DEBUG) \
+ 		-C $(BOARD_DIR)/samples/wdt
+ 	cp $(BOARD_DIR)/samples/wdt/saWatchdog $(TARGET_DIR)/bin/
+ 
+ wdt_sample-clean:
+ 	make clean -C $(BOARD_DIR)/samples/wdt
+ 	
  copy_headers:
  #Copy the headers that are needed manually 
  	cp $(LINUX_DIR)/include/mtd/ckb_gpmc_cs1_ioctl.h $(STAGING_DIR)/usr/include/mtd/
***************
*** 65,68 ****
--- 81,88 ----
  POST_LINUX_TARGETS += ext_cn1_mem
  endif
  
+ ifeq ($(BR2_CKB_WDT_SAMPLE),y)
+ TARGETS += wdt_sample
+ endif
+ 
  endif
diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-3352/before_packing_fs.sh buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-3352/before_packing_fs.sh
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-3352/before_packing_fs.sh	1970-01-01 09:00:00.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-3352/before_packing_fs.sh	2014-02-12 17:58:35.000000000 +0900
***************
*** 0 ****
--- 1,14 ----
+ #!/bin/sh
+ #Environment variables; $TARGET_DIR is passed as the argument by buildroot
+ export TARGET_FS_FOLDER=$1
+ 
+ # legal-info licenses.txt
+ mkdir -p $TARGET_FS_FOLDER/etc/legal-info
+ cp $TARGET_FS_FOLDER/../legal-info/licenses.txt $TARGET_FS_FOLDER/etc/legal-info/licenses.txt
+ 
+ #Change permissions
+ chmod +x $TARGET_FS_FOLDER/etc/udhcpc.scripts 
+ chmod +x $TARGET_FS_FOLDER/etc/init.d/*
+ chmod +x $TARGET_FS_FOLDER/etc/network/wlan-scripts/*
+ #chmod +x $TARGET_FS_FOLDER/bin/*
+ sync
diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-3352/bootloader/device.c buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-3352/bootloader/device.c
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-3352/bootloader/device.c	2014-06-16 14:45:09.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-3352/bootloader/device.c	2014-11-28 08:51:37.000000000 +0900
***************
*** 20,25 ****
--- 20,35 ----
  
  #include <defines.h>
  
+ int wait_for_bb(void);
+ int wait_for_pin(void);
+ void flush_fifo(void);
+ void enable_ddr3_clocks(void);
+ void config_vtp(void);
+ void phy_config_cmd(void);
+ void phy_config_data(void);
+ void config_emif_ddr3(void);
+ 
+ 
  #define Outport(a, addr, val)		((*(volatile unsigned long *)addr) = val)
  #define Inport(a, addr)				(*(volatile unsigned long *)addr)
  
***************
*** 201,209 ****
--- 211,221 ----
  
  /* MAIN PLL Fdll = 1 GHZ, */
  #define MPUPLL_M_275	 275	/* 125 * n */
+ #define MPUPLL_M_300	 300	/* 125 * n */
  #define MPUPLL_M_500	 500	/* 125 * n */
  #define MPUPLL_M_600	 600	/* 125 * n */
  #define MPUPLL_M_720	 720	/* 125 * n */
+ #define MPUPLL_M_800	 800	/* 125 * n */
  
  #define MPUPLL_N		 23	/* (n -1 ) */
  #define MPUPLL_M2		 1
***************
*** 253,258 ****
--- 265,271 ----
  #define DEFDCDC3			0x10
  #define DEFSLEW				0x11
  #define DCDC_GO				0x80
+ #define V0950				0x02
  #define V1100				0x08
  #define V1200				0x0C
  #define V1275				0x0F
***************
*** 570,575 ****
--- 583,591 ----
  #define vrefp			(PAD_CTRL_BASE + 0x330)
  #define vrefn			(PAD_CTRL_BASE + 0x334)
  
+ /* TI81XX spefic control submodules */
+ #define DEVICE_ID_REG_OFFSET		0x600
+ #define DEVICE_ID_REG	(CTRL_BASE + DEVICE_ID_REG_OFFSET)
  
  /* I2C */
  #define I2C_BASE1		0x44E0B000
***************
*** 664,671 ****
  	int clkmode;
  	int clksel;
  	int div_m2;
! 	int idlest_dpll_mpu;
! 
  	clkmode = Inport(3,CM_CLKMODE_DPLL_MPU) & ~0x7;			// 0x44E00488
  
  	/* Set the PLL to bypass Mode */
--- 680,686 ----
  	int clkmode;
  	int clksel;
  	int div_m2;
! 	
  	clkmode = Inport(3,CM_CLKMODE_DPLL_MPU) & ~0x7;			// 0x44E00488
  
  	/* Set the PLL to bypass Mode */
***************
*** 1134,1147 ****
  }
  
  
! gpio1_config()
  {
  	/* NOR bank config */ 
  	Outport(3,GPIO1_SYSCONFIG,	IDLEMODE | SOFTRESET | AUTOIDLE );						// 0x4804C010
  	Outport(3,GPIO1_OE, Inport(3,GPIO1_OE) & (~(0x7f<<20)));								// 0x4804C134
  }
  
! config_am335x_ddr3(void)
  {
  
  	int DDR3_IOCTRL_VALUE		= 0x18B;
--- 1149,1162 ----
  }
  
  
! void gpio1_config()
  {
  	/* NOR bank config */ 
  	Outport(3,GPIO1_SYSCONFIG,	IDLEMODE | SOFTRESET | AUTOIDLE );						// 0x4804C010
  	Outport(3,GPIO1_OE, Inport(3,GPIO1_OE) & (~(0x7f<<20)));								// 0x4804C134
  }
  
! void config_am335x_ddr3(void)
  {
  
  	int DDR3_IOCTRL_VALUE		= 0x18B;
***************
*** 1172,1178 ****
  	config_emif_ddr3();
  }
  
! enable_ddr3_clocks(void)
  {
  	/* Enable the  EMIF_FW Functional clock */
  	Outport(3, CM_PER_EMIF_FW_CLKCTRL,PRCM_MOD_EN);
--- 1187,1193 ----
  	config_emif_ddr3();
  }
  
! void enable_ddr3_clocks(void)
  {
  	/* Enable the  EMIF_FW Functional clock */
  	Outport(3, CM_PER_EMIF_FW_CLKCTRL,PRCM_MOD_EN);
***************
*** 1182,1188 ****
  	while ((Inport(3,CM_PER_EMIF_CLKCTRL)) != PRCM_MOD_EN);
  }
  
! phy_config_cmd(void)
  {
  	int DDR3_RATIO				= 0x40;
  	int DDR3_INVERT_CLKOUT		= 0x1;
--- 1197,1203 ----
  	while ((Inport(3,CM_PER_EMIF_CLKCTRL)) != PRCM_MOD_EN);
  }
  
! void phy_config_cmd(void)
  {
  	int DDR3_RATIO				= 0x40;
  	int DDR3_INVERT_CLKOUT		= 0x1;
***************
*** 1195,1201 ****
  	Outport(3, CMD2_INVERT_CLKOUT_0,	DDR3_INVERT_CLKOUT);
  }
  
! phy_config_data(void)
  {
  	int DDR3_RD_DQS				= 0x3B;
  	int DDR3_WR_DQS				= 0x85;
--- 1210,1216 ----
  	Outport(3, CMD2_INVERT_CLKOUT_0,	DDR3_INVERT_CLKOUT);
  }
  
! void phy_config_data(void)
  {
  	int DDR3_RD_DQS				= 0x3B;
  	int DDR3_WR_DQS				= 0x85;
***************
*** 1213,1219 ****
  	Outport(3, DATA1_WR_DATA_SLAVE_RATIO_0,	DDR3_PHY_WR_DATA);
  }
  
! config_emif_ddr3(void)
  {
  
  	int DDR3_EMIF_READ_LATENCY		= 0x06;				// RD_Latency = (CL + 2) - 1
--- 1228,1234 ----
  	Outport(3, DATA1_WR_DATA_SLAVE_RATIO_0,	DDR3_PHY_WR_DATA);
  }
  
! void config_emif_ddr3(void)
  {
  
  	int DDR3_EMIF_READ_LATENCY		= 0x06;				// RD_Latency = (CL + 2) - 1
***************
*** 1222,1229 ****
  	int DDR3_EMIF_TIM3				= 0x501F830F;		// by calc_tool
  	int DDR3_EMIF_SDREF				= 0x0000093B;		// 303MHz * 7.8us
  	int DDR3_ZQ_CFG					= 0x50074BE4;
! 	int DDR3_EMIF_SDCFG				= 0x61C04AB2;
! 
  	int reg_sdram_type;
  	int reg_ibank_pos;
  	int reg_ddr_term;
--- 1237,1243 ----
  	int DDR3_EMIF_TIM3				= 0x501F830F;		// by calc_tool
  	int DDR3_EMIF_SDREF				= 0x0000093B;		// 303MHz * 7.8us
  	int DDR3_ZQ_CFG					= 0x50074BE4;
! 	
  	int reg_sdram_type;
  	int reg_ibank_pos;
  	int reg_ddr_term;
***************
*** 1271,1277 ****
  	reg_ebank				= (0<<3);
  	reg_pagesize			= (2);			/* 10 1k */
  
- //	Outport(3, EMIF4_0_SDRAM_CONFIG,			DDR3_EMIF_SDCFG);
  	Outport(3, EMIF4_0_SDRAM_CONFIG,	reg_sdram_type		|
                                          reg_ibank_pos		|
                                          reg_ddr_term		|
--- 1285,1290 ----
***************
*** 1290,1298 ****
  }
  
  
! void pll_init()
  {
! 	mpu_pll_config(MPUPLL_M_500);
  	core_pll_config();
  	per_pll_config();
  	ddr_pll_config();
--- 1303,1314 ----
  }
  
  
! void pll_init(int revision)
  {
! 	if(revision >= AM335X_REV_ES2_0)
! 		mpu_pll_config(MPUPLL_M_600);
! 	else
! 		mpu_pll_config(MPUPLL_M_500);
  	core_pll_config();
  	per_pll_config();
  	ddr_pll_config();
***************
*** 1301,1307 ****
  	per_clocks_enable();						/* Enable the required peripherals */
  }
  
! config_vtp(void)
  {
  	int VTP0_CTRL_REG;
  	int vtp_ctrl	= 0xE0C;
--- 1317,1323 ----
  	per_clocks_enable();						/* Enable the required peripherals */
  }
  
! void config_vtp(void)
  {
  	int VTP0_CTRL_REG;
  	int vtp_ctrl	= 0xE0C;
***************
*** 1329,1335 ****
   ***  I2C
   ******************************************************************************** */
  
! i2c_init(int speed, int slaveadd)
  {
  	int psc;
  	int fsscll;
--- 1345,1351 ----
   ***  I2C
   ******************************************************************************** */
  
! void i2c_init(int speed, int slaveadd)
  {
  	int psc;
  	int fsscll;
***************
*** 1340,1346 ****
  	int sclh;
  	int timeout;
  
! 	int I2C_PSC_MAX		= 0x0f;
  	int I2C_PSC_MIN		= 0x00;
  
  	int I2C_IP_CLK		= 48000000;
--- 1356,1362 ----
  	int sclh;
  	int timeout;
  
! 	//int I2C_PSC_MAX		= 0x0f;
  	int I2C_PSC_MIN		= 0x00;
  
  	int I2C_IP_CLK		= 48000000;
***************
*** 1529,1535 ****
  	return i2c_error;
  }
  
! flush_fifo(void)
  {	int stat;
  
  	/* note: if you try and read data when its not there or ready
--- 1545,1551 ----
  	return i2c_error;
  }
  
! void flush_fifo(void)
  {	int stat;
  
  	/* note: if you try and read data when its not there or ready
***************
*** 1742,1749 ****
--- 1758,1767 ----
  	}
  
  	if (timeout <= 0) {
+ 		return 1;
  	}
  	Outport(3,I2C_STAT,0xFFFF);	 /* clear delayed stuff*/
+ 	return 0;
  }
  
  /**************************************************************************************/
***************
*** 1769,1775 ****
  	return status;
  }
  
! udelay(int dly)
  {
  	int i;
  	for(i=0;i<10000;i++);
--- 1787,1793 ----
  	return status;
  }
  
! void udelay(int dly)
  {
  	int i;
  	for(i=0;i<10000;i++);
***************
*** 1792,1830 ****
  int tps65217_reg_write(int prot_level, int dest_reg, int dest_val, int mask)
  {
  
! 		int read_val;
! 		int xor_reg;
! 
! 		/* if we are affecting only a bit field, read dest_reg and apply the mask */
! 		if (mask != MASK_ALL_BITS) {
! 			if (i2c_read_byte(TPS65217_CHIP_PM, dest_reg, &read_val))
! 				return 1;
! 			read_val &= (~mask);
! 			read_val |= (dest_val & mask);
! 			dest_val = read_val;
! 		}
  
! 		if (prot_level > 0) {
! 			xor_reg = dest_reg ^ PASSWORD_UNLOCK;
! 			if (i2c_write_byte(TPS65217_CHIP_PM, PASSWORD, xor_reg))
! 				return 1;
! 		}
  
! 		if (i2c_write_byte(TPS65217_CHIP_PM, dest_reg, dest_val))
  			return 1;
  
! 		if (prot_level == PROT_LEVEL_2) {
! 			if (i2c_write_byte(TPS65217_CHIP_PM, PASSWORD, xor_reg))
! 				return 1;
  
! 			if (i2c_write_byte(TPS65217_CHIP_PM, dest_reg, dest_val))
! 				return 1;
! 		}
  
! 		return 0;
  }
  
! arm_275m()
  {
  	int mask1	= 0x3F;
  	int mask2	= 0x80;;
--- 1810,1848 ----
  int tps65217_reg_write(int prot_level, int dest_reg, int dest_val, int mask)
  {
  
! 	int read_val;
! 	int xor_reg;
  
! 	/* if we are affecting only a bit field, read dest_reg and apply the mask */
! 	if (mask != MASK_ALL_BITS) {
! 		if (i2c_read_byte(TPS65217_CHIP_PM, dest_reg, &read_val))
! 			return 1;
! 		read_val &= (~mask);
! 		read_val |= (dest_val & mask);
! 		dest_val = read_val;
! 	}
  
! 	if (prot_level > 0) {
! 		xor_reg = dest_reg ^ PASSWORD_UNLOCK;
! 		if (i2c_write_byte(TPS65217_CHIP_PM, PASSWORD, xor_reg))
  			return 1;
+ 	}
  
! 	if (i2c_write_byte(TPS65217_CHIP_PM, dest_reg, dest_val))
! 		return 1;
  
! 	if (prot_level == PROT_LEVEL_2) {
! 		if (i2c_write_byte(TPS65217_CHIP_PM, PASSWORD, xor_reg))
! 			return 1;
  
! 		if (i2c_write_byte(TPS65217_CHIP_PM, dest_reg, dest_val))
! 			return 1;
! 	}
! 	return 0;
  }
  
! // Rev ES1
! void arm_275m()
  {
  	int mask1	= 0x3F;
  	int mask2	= 0x80;;
***************
*** 1836,1842 ****
  	mpu_pll_config(MPUPLL_M_275);
  
  }
! arm_500m()
  {
  	int mask1	= 0x3F;
  	int mask2	= 0x80;;
--- 1854,1877 ----
  	mpu_pll_config(MPUPLL_M_275);
  
  }
! 
! // Rev >= ES2_0
! void arm_300m()
! {
! 	int mask1	= 0x3F;
! 	int mask2	= 0x80;;
! 
! 	i2c_init(100000,1);
! 	//tps65217_reg_write(PROT_LEVEL_2,DEFDCDC2,V1100,mask1);
! 	tps65217_reg_write(PROT_LEVEL_2,DEFDCDC2,V0950,mask1);
! 	tps65217_reg_write(PROT_LEVEL_2,DEFSLEW,DCDC_GO,mask2);
! 	udelay(1);
! 	mpu_pll_config(MPUPLL_M_300);
! 
! }
! 
! // Rev ES1
! void arm_500m()
  {
  	int mask1	= 0x3F;
  	int mask2	= 0x80;;
***************
*** 1849,1886 ****
  
  }
  
! arm_600m()
  {
  	int mask1	= 0x3F;
  	int mask2	= 0x80;;
  
  	i2c_init(100000,1);
! 	tps65217_reg_write(PROT_LEVEL_2,DEFDCDC2,V1200,mask1);
  	tps65217_reg_write(PROT_LEVEL_2,DEFSLEW,DCDC_GO,mask2);
  	udelay(1);
  	mpu_pll_config(MPUPLL_M_600);
  
  }
  
! arm_720m()
  {
  	int mask1	= 0x3F;
  	int mask2	= 0x80;;
  
  	i2c_init(100000,1);
! 	tps65217_reg_write(PROT_LEVEL_2,DEFDCDC2,V1275,mask1);
  	tps65217_reg_write(PROT_LEVEL_2,DEFSLEW,DCDC_GO,mask2);
  	udelay(1);
  	mpu_pll_config(MPUPLL_M_720);
  
  }
  
  
  
! void init_DEVICE()
  {
  	watchdog_init();
! 	pll_init();
  	
  	pin_config();
  	gpmc_config();
--- 1884,1965 ----
  
  }
  
! void arm_600m(int revision)
  {
  	int mask1	= 0x3F;
  	int mask2	= 0x80;;
  
  	i2c_init(100000,1);
! 	if(revision >= AM335X_REV_ES2_0)
! 		tps65217_reg_write(PROT_LEVEL_2,DEFDCDC2,V1100,mask1);
! 	else
! 		tps65217_reg_write(PROT_LEVEL_2,DEFDCDC2,V1200,mask1);
  	tps65217_reg_write(PROT_LEVEL_2,DEFSLEW,DCDC_GO,mask2);
  	udelay(1);
  	mpu_pll_config(MPUPLL_M_600);
  
  }
  
! void arm_720m(int revision)
  {
  	int mask1	= 0x3F;
  	int mask2	= 0x80;;
  
  	i2c_init(100000,1);
! 	if(revision >= AM335X_REV_ES2_0)
! 		tps65217_reg_write(PROT_LEVEL_2,DEFDCDC2,V1200,mask1);
! 	else
! 		tps65217_reg_write(PROT_LEVEL_2,DEFDCDC2,V1275,mask1);
  	tps65217_reg_write(PROT_LEVEL_2,DEFSLEW,DCDC_GO,mask2);
  	udelay(1);
  	mpu_pll_config(MPUPLL_M_720);
  
  }
+ // Rev >= ES2_0
+ void arm_800m()
+ {
+ 	int mask1	= 0x3F;
+ 	int mask2	= 0x80;;
+ 
+ 	i2c_init(100000,1);
+ 	tps65217_reg_write(PROT_LEVEL_2,DEFDCDC2,V1275,mask1);
+ 	tps65217_reg_write(PROT_LEVEL_2,DEFSLEW,DCDC_GO,mask2);
+ 	udelay(1);
+ 	mpu_pll_config(MPUPLL_M_800);
  
+ }
  
+ unsigned long get_dev_id()
+ {
+ 	return Inport(3, DEVICE_ID_REG);
+ }
  
! int init_DEVICE()
  {
+ 	int revision;
+ 	unsigned long idcode;
+ 	unsigned char rev;
+ 
  	watchdog_init();
! 	/* get the CPU revision */
! 	idcode = get_dev_id();
! 	rev = (idcode >> 28) & 0xff;
! 	switch(rev)
! 	{
! 	case 0:
! 		revision = AM335X_REV_ES1_0;
! 		break;
! 	case 1:
! 		revision = AM335X_REV_ES2_0;
! 		break;
! 	case 2:
! 		revision = AM335X_REV_ES2_1;
! 		break;
! 	default:
! 		revision = AM335X_REV_UNKNOWN;
! 		break;
! 	}
! 	pll_init(revision);
  	
  	pin_config();
  	gpmc_config();
***************
*** 1888,1894 ****
  	config_am335x_ddr3();
  	/* some problem with CS1 mode, use GPIO mode */
  	gpmc_cs1_ext_cn_config(1);			/* 1 -> GPIO mode, 0->CS1 mode */
! 
  }
  
  void set_flash_bank(int bank)
--- 1967,1977 ----
  	config_am335x_ddr3();
  	/* some problem with CS1 mode, use GPIO mode */
  	gpmc_cs1_ext_cn_config(1);			/* 1 -> GPIO mode, 0->CS1 mode */
! 	if(revision >= AM335X_REV_ES2_0)
! 		arm_800m();
! 	else
! 		arm_720m(revision);
! 	return revision;
  }
  
  void set_flash_bank(int bank)
diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-3352/bootloader/include/device.h buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-3352/bootloader/include/device.h
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-3352/bootloader/include/device.h	2014-06-16 14:43:24.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-3352/bootloader/include/device.h	2014-11-28 08:50:39.000000000 +0900
***************
*** 25,30 ****
--- 25,37 ----
  #endif
  
  #define TARGET_NAME	"CKB-3352 (COMPUTEX Kumikomi Board)"
+ // CPU Revision
+ enum {
+ 	AM335X_REV_ES1_0,
+ 	AM335X_REV_ES2_0,
+ 	AM335X_REV_ES2_1,
+ 	AM335X_REV_UNKNOWN
+ };
  
  // System Control Module register structure
  typedef struct _DEVICE_SYS_MODULE_REGS_
***************
*** 495,600 ****
  #define dlm ier
  #define LSR lsr
  
! /* useful defaults for LCR */
  #define UART_LCR_8N1	0x03
! 
  #define UART_RESET		(0x1 << 1)
  #define UART_CLK_RUNNING_MASK	0x1
! #define UART_SMART_IDLE_EN	(0x1 << 0x3)
! 
! /*
!  * These are the definitions for the FIFO Control Register
!  */
! #define UART_FCR_FIFO_EN	0x01 /* Fifo enable */
! #define UART_FCR_CLEAR_RCVR	0x02 /* Clear the RCVR FIFO */
! #define UART_FCR_CLEAR_XMIT	0x04 /* Clear the XMIT FIFO */
! #define UART_FCR_DMA_SELECT	0x08 /* For DMA applications */
! #define UART_FCR_TRIGGER_MASK	0xC0 /* Mask for the FIFO trigger range */
! #define UART_FCR_TRIGGER_1	0x00 /* Mask for trigger set at 1 */
! #define UART_FCR_TRIGGER_4	0x40 /* Mask for trigger set at 4 */
! #define UART_FCR_TRIGGER_8	0x80 /* Mask for trigger set at 8 */
! #define UART_FCR_TRIGGER_14	0xC0 /* Mask for trigger set at 14 */
! 
! #define UART_FCR_RXSR		0x02 /* Receiver soft reset */
! #define UART_FCR_TXSR		0x04 /* Transmitter soft reset */
! 
! /*
!  * These are the definitions for the Modem Control Register
!  */
! #define UART_MCR_DTR	0x01		/* DTR   */
! #define UART_MCR_RTS	0x02		/* RTS   */
! #define UART_MCR_OUT1	0x04		/* Out 1 */
! #define UART_MCR_OUT2	0x08		/* Out 2 */
! #define UART_MCR_LOOP	0x10		/* Enable loopback test mode */
! 
! #define UART_MCR_DMA_EN	0x04
! #define UART_MCR_TX_DFR	0x08
! 
! /*
!  * These are the definitions for the Line Control Register
!  *
!  * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
!  * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
!  */
! #define UART_LCR_WLS_MSK 0x03		/* character length select mask */
! #define UART_LCR_WLS_5	0x00		/* 5 bit character length */
! #define UART_LCR_WLS_6	0x01		/* 6 bit character length */
! #define UART_LCR_WLS_7	0x02		/* 7 bit character length */
! #define UART_LCR_WLS_8	0x03		/* 8 bit character length */
! #define UART_LCR_STB	0x04		/* # stop Bits, off=1, on=1.5 or 2) */
! #define UART_LCR_PEN	0x08		/* Parity eneble */
! #define UART_LCR_EPS	0x10		/* Even Parity Select */
! #define UART_LCR_STKP	0x20		/* Stick Parity */
! #define UART_LCR_SBRK	0x40		/* Set Break */
! #define UART_LCR_BKSE	0x80		/* Bank select enable */
! #define UART_LCR_DLAB	0x80		/* Divisor latch access bit */
! 
! /*
!  * These are the definitions for the Line Status Register
!  */
! #define UART_LSR_DR	0x01		/* Data ready */
! #define UART_LSR_OE	0x02		/* Overrun */
! #define UART_LSR_PE	0x04		/* Parity error */
! #define UART_LSR_FE	0x08		/* Framing error */
! #define UART_LSR_BI	0x10		/* Break */
! #define UART_LSR_THRE	0x20		/* Xmit holding register empty */
! #define UART_LSR_TEMT	0x40		/* Xmitter empty */
! #define UART_LSR_ERR	0x80		/* Error */
! 
! #define UART_MSR_DCD	0x80		/* Data Carrier Detect */
! #define UART_MSR_RI	0x40		/* Ring Indicator */
! #define UART_MSR_DSR	0x20		/* Data Set Ready */
! #define UART_MSR_CTS	0x10		/* Clear to Send */
! #define UART_MSR_DDCD	0x08		/* Delta DCD */
! #define UART_MSR_TERI	0x04		/* Trailing edge ring indicator */
! #define UART_MSR_DDSR	0x02		/* Delta DSR */
! #define UART_MSR_DCTS	0x01		/* Delta CTS */
! 
! /*
!  * These are the definitions for the Interrupt Identification Register
!  */
! #define UART_IIR_NO_INT	0x01	/* No interrupts pending */
! #define UART_IIR_ID	0x06	/* Mask for the interrupt ID */
! 
! #define UART_IIR_MSI	0x00	/* Modem status interrupt */
! #define UART_IIR_THRI	0x02	/* Transmitter holding register empty */
! #define UART_IIR_RDI	0x04	/* Receiver data interrupt */
! #define UART_IIR_RLSI	0x06	/* Receiver line status interrupt */
! 
! /*
!  * These are the definitions for the Interrupt Enable Register
!  */
! #define UART_IER_MSI	0x08	/* Enable Modem status interrupt */
! #define UART_IER_RLSI	0x04	/* Enable receiver line status interrupt */
! #define UART_IER_THRI	0x02	/* Enable Transmitter holding register int. */
! #define UART_IER_RDI	0x01	/* Enable receiver data interrupt */
! 
! #define UART_LCRVAL UART_LCR_8N1		/* 8 data, 1 stop, no parity */
! #define UART_MCRVAL (UART_MCR_DTR | \
! 		     UART_MCR_RTS)		/* RTS/DTR */
! #define UART_FCRVAL (UART_FCR_FIFO_EN |	\
! 		     UART_FCR_RXSR |	\
! 		     UART_FCR_TXSR)		/* Clear & enable FIFOs */
  
  
  // GPIO Register structures
--- 502,607 ----
  #define dlm ier
  #define LSR lsr
  
! /* useful defaults for LCR */
  #define UART_LCR_8N1	0x03
! 
  #define UART_RESET		(0x1 << 1)
  #define UART_CLK_RUNNING_MASK	0x1
! #define UART_SMART_IDLE_EN	(0x1 << 0x3)
! 
! /*
!  * These are the definitions for the FIFO Control Register
!  */
! #define UART_FCR_FIFO_EN	0x01 /* Fifo enable */
! #define UART_FCR_CLEAR_RCVR	0x02 /* Clear the RCVR FIFO */
! #define UART_FCR_CLEAR_XMIT	0x04 /* Clear the XMIT FIFO */
! #define UART_FCR_DMA_SELECT	0x08 /* For DMA applications */
! #define UART_FCR_TRIGGER_MASK	0xC0 /* Mask for the FIFO trigger range */
! #define UART_FCR_TRIGGER_1	0x00 /* Mask for trigger set at 1 */
! #define UART_FCR_TRIGGER_4	0x40 /* Mask for trigger set at 4 */
! #define UART_FCR_TRIGGER_8	0x80 /* Mask for trigger set at 8 */
! #define UART_FCR_TRIGGER_14	0xC0 /* Mask for trigger set at 14 */
! 
! #define UART_FCR_RXSR		0x02 /* Receiver soft reset */
! #define UART_FCR_TXSR		0x04 /* Transmitter soft reset */
! 
! /*
!  * These are the definitions for the Modem Control Register
!  */
! #define UART_MCR_DTR	0x01		/* DTR   */
! #define UART_MCR_RTS	0x02		/* RTS   */
! #define UART_MCR_OUT1	0x04		/* Out 1 */
! #define UART_MCR_OUT2	0x08		/* Out 2 */
! #define UART_MCR_LOOP	0x10		/* Enable loopback test mode */
! 
! #define UART_MCR_DMA_EN	0x04
! #define UART_MCR_TX_DFR	0x08
! 
! /*
!  * These are the definitions for the Line Control Register
!  *
!  * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
!  * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
!  */
! #define UART_LCR_WLS_MSK 0x03		/* character length select mask */
! #define UART_LCR_WLS_5	0x00		/* 5 bit character length */
! #define UART_LCR_WLS_6	0x01		/* 6 bit character length */
! #define UART_LCR_WLS_7	0x02		/* 7 bit character length */
! #define UART_LCR_WLS_8	0x03		/* 8 bit character length */
! #define UART_LCR_STB	0x04		/* # stop Bits, off=1, on=1.5 or 2) */
! #define UART_LCR_PEN	0x08		/* Parity eneble */
! #define UART_LCR_EPS	0x10		/* Even Parity Select */
! #define UART_LCR_STKP	0x20		/* Stick Parity */
! #define UART_LCR_SBRK	0x40		/* Set Break */
! #define UART_LCR_BKSE	0x80		/* Bank select enable */
! #define UART_LCR_DLAB	0x80		/* Divisor latch access bit */
! 
! /*
!  * These are the definitions for the Line Status Register
!  */
! #define UART_LSR_DR	0x01		/* Data ready */
! #define UART_LSR_OE	0x02		/* Overrun */
! #define UART_LSR_PE	0x04		/* Parity error */
! #define UART_LSR_FE	0x08		/* Framing error */
! #define UART_LSR_BI	0x10		/* Break */
! #define UART_LSR_THRE	0x20		/* Xmit holding register empty */
! #define UART_LSR_TEMT	0x40		/* Xmitter empty */
! #define UART_LSR_ERR	0x80		/* Error */
! 
! #define UART_MSR_DCD	0x80		/* Data Carrier Detect */
! #define UART_MSR_RI	0x40		/* Ring Indicator */
! #define UART_MSR_DSR	0x20		/* Data Set Ready */
! #define UART_MSR_CTS	0x10		/* Clear to Send */
! #define UART_MSR_DDCD	0x08		/* Delta DCD */
! #define UART_MSR_TERI	0x04		/* Trailing edge ring indicator */
! #define UART_MSR_DDSR	0x02		/* Delta DSR */
! #define UART_MSR_DCTS	0x01		/* Delta CTS */
! 
! /*
!  * These are the definitions for the Interrupt Identification Register
!  */
! #define UART_IIR_NO_INT	0x01	/* No interrupts pending */
! #define UART_IIR_ID	0x06	/* Mask for the interrupt ID */
! 
! #define UART_IIR_MSI	0x00	/* Modem status interrupt */
! #define UART_IIR_THRI	0x02	/* Transmitter holding register empty */
! #define UART_IIR_RDI	0x04	/* Receiver data interrupt */
! #define UART_IIR_RLSI	0x06	/* Receiver line status interrupt */
! 
! /*
!  * These are the definitions for the Interrupt Enable Register
!  */
! #define UART_IER_MSI	0x08	/* Enable Modem status interrupt */
! #define UART_IER_RLSI	0x04	/* Enable receiver line status interrupt */
! #define UART_IER_THRI	0x02	/* Enable Transmitter holding register int. */
! #define UART_IER_RDI	0x01	/* Enable receiver data interrupt */
! 
! #define UART_LCRVAL UART_LCR_8N1		/* 8 data, 1 stop, no parity */
! #define UART_MCRVAL (UART_MCR_DTR | \
! 		     UART_MCR_RTS)		/* RTS/DTR */
! #define UART_FCRVAL (UART_FCR_FIFO_EN |	\
! 		     UART_FCR_RXSR |	\
! 		     UART_FCR_TXSR)		/* Clear & enable FIFOs */
  
  
  // GPIO Register structures
***************
*** 630,636 ****
  * Global Function Declarations                             *
  ***********************************************************/
  // System Initialization prototypes
! extern void  init_DEVICE(void);
  
  // Peripheral Initialization prototypes
  extern Uint32  DEVICE_UARTInit(int baudrate);
--- 637,643 ----
  * Global Function Declarations                             *
  ***********************************************************/
  // System Initialization prototypes
! extern int init_DEVICE(void);
  
  // Peripheral Initialization prototypes
  extern Uint32  DEVICE_UARTInit(int baudrate);
diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-3352/bootloader/main.c buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-3352/bootloader/main.c
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-3352/bootloader/main.c	2014-06-16 14:45:59.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-3352/bootloader/main.c	2014-11-28 08:52:04.000000000 +0900
***************
*** 26,31 ****
--- 26,35 ----
  extern unsigned char __bss_start;
  extern unsigned char __bss_end;
  
+ void set_flash_bank(int bank);
+ void hprintf(const char *format, ...);
+ void putstr(char *str);
+ 
  /****************************************************************************
   * entry routine
   ****************************************************************************/
***************
*** 40,67 ****
  }
  
  int g_ckb_cur_flash_bank=-1;
! unsigned long set_ckb_flash_bank(unsigned long addr)
! {
! 	/* The flash bank is a shadow mapping of 128KB changable by the GPIOs GP1[20]~GP1[26] */
  	int ckb_flash_bank = (addr - CONFIG_SYS_FLASH_BASE)/CONFIG_FLASH_CKB_BANK_SIZE;
! 	if(ckb_flash_bank != g_ckb_cur_flash_bank)
! 	{
! 		/* select map using GPIOs */
! 		set_flash_bank(ckb_flash_bank);
! 		g_ckb_cur_flash_bank = ckb_flash_bank;
  	}
  }
  
! void main(void)
  {
  	unsigned long uboot_len;
  	unsigned long *src, *dst;
  	unsigned long src_end;
  	int copied_len = 0;
  	int copy_len;
  
  	/* initialize */
! 	init_DEVICE();
  	
  	DEVICE_UARTInit(115200);
  
--- 44,74 ----
  }
  
  int g_ckb_cur_flash_bank=-1;
! void set_ckb_flash_bank(unsigned long addr)
! {
! 	/* The flash bank is a shadow mapping of 128KB changable by the GPIOs GP1[20]~GP1[26] */
  	int ckb_flash_bank = (addr - CONFIG_SYS_FLASH_BASE)/CONFIG_FLASH_CKB_BANK_SIZE;
! 	if(ckb_flash_bank != g_ckb_cur_flash_bank)
! 	{
! 		/* select map using GPIOs */
! 		set_flash_bank(ckb_flash_bank);
! 		g_ckb_cur_flash_bank = ckb_flash_bank;
  	}
  }
  
! int main(void)
  {
  	unsigned long uboot_len;
  	unsigned long *src, *dst;
  	unsigned long src_end;
  	int copied_len = 0;
  	int copy_len;
+ 	unsigned long idcode;
+ 	int omap_revision;
+ 	unsigned char rev;
  
  	/* initialize */
! 	omap_revision = init_DEVICE();
  	
  	DEVICE_UARTInit(115200);
  
***************
*** 69,74 ****
--- 76,104 ----
  	hprintf("\n\n%s V1.00.00 (%s)-%s\n",
                  TARGET_NAME, __DATE__, __TIME__);
  	
+ 	hprintf("AM335x ES");
+ 	switch(rev)
+ 	{
+ 	case 0:
+ 		omap_revision = AM335X_REV_ES1_0;
+ 		hprintf("1.0");
+ 		break;
+ 	case 1:
+ 		omap_revision = AM335X_REV_ES2_0;
+ 		hprintf("2.0");
+ 		break;
+ 	case 2:
+ 		omap_revision = AM335X_REV_ES2_1;
+ 		hprintf("2.1");
+ 		break;
+ 	default:
+ 		omap_revision = AM335X_REV_UNKNOWN;
+ 		hprintf("-unknown");
+ 		break;
+ 	}
+ 	
+ 	hprintf("\n");
+ 	
  	/* check if U-Boot is present */
  	set_ckb_flash_bank(UBOOT_NOR_BASE_ADDR);
  	if((*((unsigned long*)(UBOOT_NOR_BASE_ADDR+UBOOT_HEADER_OFFSET))) != CONFIG_SYS_TEXT_BASE)
***************
*** 79,90 ****
  	if(uboot_len > MAX_UBOOT_SIZE)
  		goto _not_found;
  	
! 	puts("Loading U-Boot...");
  
  #ifdef _CKB_PRINT_ADDRESS
  	hprintf("0x%x=>0x%x, %d bytes\n", UBOOT_NOR_BASE_ADDR, CONFIG_SYS_TEXT_BASE, uboot_len);
  #else
! 	puts("\n");
  #endif
  
  	dst = CONFIG_SYS_TEXT_BASE;
--- 109,120 ----
  	if(uboot_len > MAX_UBOOT_SIZE)
  		goto _not_found;
  	
! 	putstr("Loading U-Boot...");
  
  #ifdef _CKB_PRINT_ADDRESS
  	hprintf("0x%x=>0x%x, %d bytes\n", UBOOT_NOR_BASE_ADDR, CONFIG_SYS_TEXT_BASE, uboot_len);
  #else
! 	putstr("\n");
  #endif
  
  	dst = CONFIG_SYS_TEXT_BASE;
***************
*** 157,167 ****
  	jump_to_addr(CONFIG_SYS_TEXT_BASE);
  
  _not_found:
! 	puts("U-Boot not found");
  #ifdef _CKB_PRINT_ADDRESS
  	hprintf(" at 0x%x\n", UBOOT_NOR_BASE_ADDR);
  #else
! 	puts("\n");
  #endif
  	while(1);
  }
--- 187,198 ----
  	jump_to_addr(CONFIG_SYS_TEXT_BASE);
  
  _not_found:
! 	putstr("U-Boot not found");
  #ifdef _CKB_PRINT_ADDRESS
  	hprintf(" at 0x%x\n", UBOOT_NOR_BASE_ADDR);
  #else
! 	putstr("\n");
  #endif
  	while(1);
+ 	return 0;
  }
diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-3352/bootloader/uart.c buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-3352/bootloader/uart.c
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-3352/bootloader/uart.c	2013-03-27 09:34:59.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-3352/bootloader/uart.c	2014-11-25 16:19:33.000000000 +0900
***************
*** 22,28 ****
  Uint32 DEVICE_UARTInit(int baudrate)
  {
  	
! 	int baud_divisor =(CONFIG_SYS_NS16550_CLK + (baudrate * (MODE_X_DIV / 2))) /
          (MODE_X_DIV * baudrate);
  	
  	/* set the global UART pointer */
--- 22,28 ----
  Uint32 DEVICE_UARTInit(int baudrate)
  {
  	
! 	int baud_divisor =(CONFIG_SYS_NS16550_CLK + (baudrate * (MODE_X_DIV / 2))) /
          (MODE_X_DIV * baudrate);
  	
  	/* set the global UART pointer */
***************
*** 37,55 ****
  	UART->uartsyscfg |= UART_SMART_IDLE_EN;
  	
  	UART->ier = 0;
! 	UART->mdr1 = 0x7;	/* mode select reset TL16C750*/
! 	UART->lcr = UART_LCR_BKSE | UART_LCRVAL;
! 	UART->dll = 0;
! 	UART->dlm = 0;
! 	UART->lcr = UART_LCRVAL;
! 	UART->mcr = UART_MCRVAL;
! 	UART->fcr = UART_FCRVAL;
! 	UART->lcr = UART_LCR_BKSE | UART_LCRVAL;
! 	UART->dll = baud_divisor & 0xff;
! 	UART->dlm = (baud_divisor >> 8) & 0xff;
! 	UART->lcr = UART_LCRVAL;
! 	/* /16 is proper to hit 115200 with 48MHz */
! 	UART->mdr1 = 0;
   
     return 0;
  }
--- 37,55 ----
  	UART->uartsyscfg |= UART_SMART_IDLE_EN;
  	
  	UART->ier = 0;
! 	UART->mdr1 = 0x7;	/* mode select reset TL16C750*/
! 	UART->lcr = UART_LCR_BKSE | UART_LCRVAL;
! 	UART->dll = 0;
! 	UART->dlm = 0;
! 	UART->lcr = UART_LCRVAL;
! 	UART->mcr = UART_MCRVAL;
! 	UART->fcr = UART_FCRVAL;
! 	UART->lcr = UART_LCR_BKSE | UART_LCRVAL;
! 	UART->dll = baud_divisor & 0xff;
! 	UART->dlm = (baud_divisor >> 8) & 0xff;
! 	UART->lcr = UART_LCRVAL;
! 	/* /16 is proper to hit 115200 with 48MHz */
! 	UART->mdr1 = 0;
   
     return 0;
  }
***************
*** 128,134 ****
  	}
  }
  
! void puts(char *str)
  {
  	while(*str)
  		hputchar(*str++);
--- 128,134 ----
  	}
  }
  
! void putstr(char *str)
  {
  	while(*str)
  		hputchar(*str++);
***************
*** 207,212 ****
  //extern void __aeabi_idiv(void);
  void __div0(void)
  {
! 	puts("Error: Division by zero.\n");
  	while(1);
  }
--- 207,212 ----
  //extern void __aeabi_idiv(void);
  void __div0(void)
  {
! 	putstr("Error: Division by zero.\n");
  	while(1);
  }
diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-3352/configs/linux-3.2.1.config buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-3352/configs/linux-3.2.1.config
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-3352/configs/linux-3.2.1.config	2014-07-28 11:24:33.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-3352/configs/linux-3.2.1.config	2014-11-25 16:29:08.000000000 +0900
***************
*** 311,318 ****
  CONFIG_CKB_EXTCN_CAN1=y
  
  #
! # Disable LCD support to enable spidev on Pins 6,31,36,38
  #
  CONFIG_CKB_EXTCN_ADC=y
  
  #
--- 311,320 ----
  CONFIG_CKB_EXTCN_CAN1=y
  
  #
! # Disable LCD support to enable devices on Pins 6,31,36,38 (spidev1, eHRPWM0)
  #
+ # CONFIG_CKB_EXTCN_SPIDEV_SPI1 is not set
+ # CONFIG_CKB_EHRPWM0 is not set
  CONFIG_CKB_EXTCN_ADC=y
  
  #
***************
*** 322,339 ****
  #
  # Disable LCD support to enable Pin2 multiplex options
  #
  
  #
  # Disable LCD support to enable Pin4 multiplex options
  #
! 
! #
! # Disable LCD support to enable Pin6 multiplex options
! #
  
  #
  # Disable LCD support to enable Pin10 multiplex options
  #
  
  #
  # Disable Support GPMC CS1 mem to enable Pin21 multiplex options
--- 324,377 ----
  #
  # Disable LCD support to enable Pin2 multiplex options
  #
+ # CONFIG_CKB_EX_CN_PIN2_LCD_DATA12 is not set
+ # CONFIG_CKB_EX_CN_PIN2_A16 is not set
+ # CONFIG_CKB_EX_CN_PIN2_EQEP1A_IN is not set
+ # CONFIG_CKB_EX_CN_PIN2_MCASP0_ACLKR is not set
+ # CONFIG_CKB_EX_CN_PIN2_MCAP0_AXR2 is not set
+ # CONFIG_CKB_EX_CN_PIN2_PR1_MII0_RXLINK is not set
+ # CONFIG_CKB_EX_CN_PIN2_UART4_CTS is not set
+ # CONFIG_CKB_EX_CN_PIN2_OGPIO is not set
+ # CONFIG_CKB_EX_CN_PIN2_IGPIO is not set
  
  #
  # Disable LCD support to enable Pin4 multiplex options
  #
! # CONFIG_CKB_EX_CN_PIN4_LCD_DATA13 is not set
! # CONFIG_CKB_EX_CN_PIN4_A17 is not set
! # CONFIG_CKB_EX_CN_PIN4_EQEP1B_IN is not set
! # CONFIG_CKB_EX_CN_PIN4_MCASP0_FSR is not set
! # CONFIG_CKB_EX_CN_PIN4_MCAP0_AXR3 is not set
! # CONFIG_CKB_EX_CN_PIN2_PR1_MII0_RXER is not set
! # CONFIG_CKB_EX_CN_PIN4_UART4_RTS is not set
! # CONFIG_CKB_EX_CN_PIN4_OGPIO is not set
! # CONFIG_CKB_EX_CN_PIN4_IGPIO is not set
! 
! #
! # Disable LCD support and spidev1 to enable Pin6 multiplex options
! #
! # CONFIG_CKB_EX_CN_PIN6_MCASP0_AHCLKR is not set
! # CONFIG_CKB_EX_CN_PIN6_EHRPWM0_SYNCI is not set
! # CONFIG_CKB_EX_CN_PIN6_MCASP0_AXR2 is not set
! # CONFIG_CKB_EX_CN_PIN6_SPI1_CS0 is not set
! # CONFIG_CKB_EX_CN_PIN6_ECAP2_IN_PWM2_OUT is not set
! # CONFIG_CKB_EX_CN_PIN6_PR1_PRU0_PRU_R30_3 is not set
! # CONFIG_CKB_EX_CN_PIN6_PR1_PRU0_PRU_R31_3 is not set
! # CONFIG_CKB_EX_CN_PIN6_OGPIO is not set
! # CONFIG_CKB_EX_CN_PIN6_IGPIO is not set
  
  #
  # Disable LCD support to enable Pin10 multiplex options
  #
+ # CONFIG_CKB_EX_CN_PIN10_MCASP0_FSR is not set
+ # CONFIG_CKB_EX_CN_PIN10_EQEP0B_IN is not set
+ # CONFIG_CKB_EX_CN_PIN10_MCASP0_AXR3 is not set
+ # CONFIG_CKB_EX_CN_PIN10_MCASP1_FSX is not set
+ # CONFIG_CKB_EX_CN_PIN10_EMU2 is not set
+ # CONFIG_CKB_EX_CN_PIN10_PR1_PRU0_PRU_R30_5 is not set
+ # CONFIG_CKB_EX_CN_PIN10_PR1_PRU0_PRU_R31_5 is not set
+ # CONFIG_CKB_EX_CN_PIN10_OGPIO is not set
+ # CONFIG_CKB_EX_CN_PIN10_IGPIO is not set
  
  #
  # Disable Support GPMC CS1 mem to enable Pin21 multiplex options
***************
*** 371,380 ****
  # CONFIG_CKB_EX_CN_PIN30_XDMA_EVENT_INTR2 is not set
  CONFIG_CKB_EX_CN_PIN30_OGPIO=y
  # CONFIG_CKB_EX_CN_PIN30_IGPIO is not set
! 
! #
! # Disable LCD support to enable Pin31 multiplex options
! #
  # CONFIG_CKB_EX_CN_PIN33_MCASP0_AXR1 is not set
  # CONFIG_CKB_EX_CN_PIN33_EQEP0_INDEX is not set
  # CONFIG_CKB_EX_CN_PIN33_MCASP1_AXR0 is not set
--- 409,422 ----
  # CONFIG_CKB_EX_CN_PIN30_XDMA_EVENT_INTR2 is not set
  CONFIG_CKB_EX_CN_PIN30_OGPIO=y
  # CONFIG_CKB_EX_CN_PIN30_IGPIO is not set
! # CONFIG_CKB_EX_CN_PIN31_MCASP0_AXR0 is not set
! # CONFIG_CKB_EX_CN_PIN31_EHRPWM0_TRIPZONE_INPUT is not set
! # CONFIG_CKB_EX_CN_PIN31_SPI1_D1 is not set
! # CONFIG_CKB_EX_CN_PIN31_MMC2_SDCD is not set
! # CONFIG_CKB_EX_CN_PIN31_PR1_PRU0_PRU_R30_2 is not set
! # CONFIG_CKB_EX_CN_PIN31_PR1_PRU0_PRU_R31_2 is not set
! # CONFIG_CKB_EX_CN_PIN31_OGPIO is not set
! # CONFIG_CKB_EX_CN_PIN31_IGPIO is not set
  # CONFIG_CKB_EX_CN_PIN33_MCASP0_AXR1 is not set
  # CONFIG_CKB_EX_CN_PIN33_EQEP0_INDEX is not set
  # CONFIG_CKB_EX_CN_PIN33_MCASP1_AXR0 is not set
***************
*** 394,404 ****
  # CONFIG_CKB_EX_CN_PIN34_IGPIO is not set
  
  #
! # Disable LCD support to enable Pin36 multiplex options
  #
  
  #
! # Disable LCD support to enable Pin38 multiplex options
  #
  
  #
--- 436,446 ----
  # CONFIG_CKB_EX_CN_PIN34_IGPIO is not set
  
  #
! # Disable LCD support, spidev1 and eHRPWM0 to enable Pin36 multiplex options
  #
  
  #
! # Disable LCD support, spidev and eHRPWM0 to enable Pin38 multiplex options
  #
  
  #
***************
*** 1335,1342 ****
  # MODULbus GPIO expanders:
  #
  CONFIG_GENERIC_PWM=y
! # CONFIG_DAVINCI_EHRPWM is not set
! # CONFIG_ECAP_PWM is not set
  # CONFIG_W1 is not set
  # CONFIG_POWER_SUPPLY is not set
  # CONFIG_HWMON is not set
--- 1377,1384 ----
  # MODULbus GPIO expanders:
  #
  CONFIG_GENERIC_PWM=y
! CONFIG_DAVINCI_EHRPWM=y
! CONFIG_ECAP_PWM=y
  # CONFIG_W1 is not set
  # CONFIG_POWER_SUPPLY is not set
  # CONFIG_HWMON is not set
***************
*** 1350,1355 ****
--- 1392,1398 ----
  #
  # CONFIG_SOFT_WATCHDOG is not set
  # CONFIG_DW_WATCHDOG is not set
+ CONFIG_OMAP_WATCHDOG=y
  # CONFIG_MAX63XX_WATCHDOG is not set
  
  #
diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-3352/custom_fs.sh buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-3352/custom_fs.sh
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-3352/custom_fs.sh	2014-02-12 17:58:35.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-3352/custom_fs.sh	1970-01-01 09:00:00.000000000 +0900
***************
*** 1,14 ****
- #!/bin/sh
- #Environment variables; $TARGET_DIR is passed as the argument by buildroot
- export TARGET_FS_FOLDER=$1
- 
- # legal-info licenses.txt
- mkdir -p $TARGET_FS_FOLDER/etc/legal-info
- cp $TARGET_FS_FOLDER/../legal-info/licenses.txt $TARGET_FS_FOLDER/etc/legal-info/licenses.txt
- 
- #Change permissions
- chmod +x $TARGET_FS_FOLDER/etc/udhcpc.scripts 
- chmod +x $TARGET_FS_FOLDER/etc/init.d/*
- chmod +x $TARGET_FS_FOLDER/etc/network/wlan-scripts/*
- #chmod +x $TARGET_FS_FOLDER/bin/*
- sync
--- 0 ----
diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-3352/extern_fs.sh buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-3352/extern_fs.sh
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-3352/extern_fs.sh	2014-06-23 15:15:58.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-3352/extern_fs.sh	1970-01-01 09:00:00.000000000 +0900
***************
*** 1,65 ****
- #!/bin/sh
- #Environment variables passed as the arguments by buildroot
- # $1 : Root FS folder
- # $2 : Folder to which /usr has been moved
- 
- export ROOT_FS_FOLDER=$1
- export USR_FOLDER=$2
- 
- #copy important libs/bins from sdcard directory to the root folder directory
- 	mkdir -p $ROOT_FS_FOLDER/usr/bin
- 	mkdir -p $ROOT_FS_FOLDER/usr/sbin
- 	mkdir -p $ROOT_FS_FOLDER/usr/lib
- 	mkdir -p $ROOT_FS_FOLDER/usr/local/bin
- 	cp -rpd $USR_FOLDER/local/bin/* $ROOT_FS_FOLDER/usr/local/bin/
- 	cp -rpd $USR_FOLDER/bin/iperf $ROOT_FS_FOLDER/usr/bin/
- 	cp -rpd $USR_FOLDER/bin/ts_test $ROOT_FS_FOLDER/usr/bin/
- 	cp -rpd $USR_FOLDER/bin/ntpdate $ROOT_FS_FOLDER/usr/bin/
- 	cp -rpd $USR_FOLDER/bin/inotify* $ROOT_FS_FOLDER/usr/bin/
- 	cp -rpd $USR_FOLDER/bin/i2c* $ROOT_FS_FOLDER/usr/bin/
- 	cp -rpd $USR_FOLDER/lib/ts* $ROOT_FS_FOLDER/usr/lib/
- 	cp -rpd $USR_FOLDER/lib/libts* $ROOT_FS_FOLDER/usr/lib
- 	cp -rpd $USR_FOLDER/lib/libintl.* $ROOT_FS_FOLDER/usr/lib
- 	cp -rpd $USR_FOLDER/lib/libnl* $ROOT_FS_FOLDER/usr/lib
- 	cp -rpd $USR_FOLDER/lib/libssl* $ROOT_FS_FOLDER/usr/lib/
- 	cp -rpd $USR_FOLDER/lib/libcrypto* $ROOT_FS_FOLDER/usr/lib/
- 	cp -rpd $USR_FOLDER/lib/libgpg-error* $ROOT_FS_FOLDER/usr/lib/
- 	cp -rpd $USR_FOLDER/lib/libdbus* $ROOT_FS_FOLDER/usr/lib/
- 	cp -rpd $USR_FOLDER/lib/libstdc++.so* $ROOT_FS_FOLDER/usr/lib/
- 	cp -rpd $USR_FOLDER/lib/crda $ROOT_FS_FOLDER/usr/lib/
- 	cp -rpd $USR_FOLDER/lib/avahi $ROOT_FS_FOLDER/usr/lib/
- 	cp -rpd $USR_FOLDER/lib/libavahi-* $ROOT_FS_FOLDER/usr/lib/
- 	cp -rpd $USR_FOLDER/lib/libdaemon.* $ROOT_FS_FOLDER/usr/lib/
- 	cp -rpd $USR_FOLDER/lib/libexpat.* $ROOT_FS_FOLDER/usr/lib/
- 	cp -rpd $USR_FOLDER/lib/libgcrypt.* $ROOT_FS_FOLDER/usr/lib/
- 	cp -rpd $USR_FOLDER/sbin/iw $ROOT_FS_FOLDER/usr/sbin/
- 	cp -rpd $USR_FOLDER/sbin/wpa_* $ROOT_FS_FOLDER/usr/sbin/
- 	cp -rpd $USR_FOLDER/sbin/hostapd $ROOT_FS_FOLDER/usr/sbin/
- 	cp -rpd $USR_FOLDER/sbin/mtd* $ROOT_FS_FOLDER/usr/sbin/
- 	cp -rpd $USR_FOLDER/sbin/rtc* $ROOT_FS_FOLDER/usr/sbin/
- 	cp -rpd $USR_FOLDER/sbin/fbset* $ROOT_FS_FOLDER/usr/sbin/
- 	cp -rpd $USR_FOLDER/sbin/avahi-* $ROOT_FS_FOLDER/usr/sbin/
- 	cp -rpd $USR_FOLDER/share/avahi $ROOT_FS_FOLDER/usr/share/
- 	cp -rpd $USR_FOLDER/sbin/fbset* $ROOT_FS_FOLDER/usr/sbin/
- 	cp -rpd $USR_FOLDER/share/udhcpc $ROOT_FS_FOLDER/usr/share/
- 	cp -rpd $USR_FOLDER/bin/_cside* $ROOT_FS_FOLDER/usr/bin/
- 	cp -rpd $USR_FOLDER/bin/cside* $ROOT_FS_FOLDER/usr/bin/
- 	cp -rpd $USR_FOLDER/bin/libcsidemprof.so $ROOT_FS_FOLDER/usr/bin/
- 	cp -rpd $USR_FOLDER/lib/libcdbmem.so $ROOT_FS_FOLDER/lib/
- # - IPTABLES
- #	cp -rpd $USR_FOLDER/sbin/iptables* $ROOT_FS_FOLDER/usr/sbin/
- #	cp -rpd $USR_FOLDER/sbin/xtables* $ROOT_FS_FOLDER/usr/sbin/
- # - SDL
- #	cp -rpd $USR_FOLDER/lib/libSDL* $ROOT_FS_FOLDER/usr/lib/
- 	cp -rpd $USR_FOLDER/lib/libjpeg.so* $ROOT_FS_FOLDER/usr/lib/
- #	cp -rpd $USR_FOLDER/lib/libtiff.so* $ROOT_FS_FOLDER/usr/lib/
- #	cp -rpd $USR_FOLDER/lib/libz.so* $ROOT_FS_FOLDER/usr/lib/
- #	cp -rpd $USR_FOLDER/lib/libfreetype.so* $ROOT_FS_FOLDER/usr/lib/
- 
- #End
- 
- #Change permissions
- chmod +x $ROOT_FS_FOLDER/etc/udhcpc.scripts 
- chmod +x $ROOT_FS_FOLDER/etc/init.d/*
- chmod +x $ROOT_FS_FOLDER/etc/network/wlan-scripts/*
- sync
--- 0 ----
diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-3352/patches/linux-3.2.1-000-ctexdbg_arm_generic_v014_6.patch buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-3352/patches/linux-3.2.1-000-ctexdbg_arm_generic_v014_6.patch
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-3352/patches/linux-3.2.1-000-ctexdbg_arm_generic_v014_6.patch	2013-06-05 14:04:25.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-3352/patches/linux-3.2.1-000-ctexdbg_arm_generic_v014_6.patch	1970-01-01 09:00:00.000000000 +0900
***************
*** 1,5589 ****
- diff -crN linux-3.2.1_o/arch/arm/include/asm/ctexdbg_arch.h linux-3.2.1_ctex/arch/arm/include/asm/ctexdbg_arch.h
- *** linux-3.2.1_o/arch/arm/include/asm/ctexdbg_arch.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1_ctex/arch/arm/include/asm/ctexdbg_arch.h	2013-05-24 10:30:30.649277000 +0900
- ***************
- *** 0 ****
- --- 1,225 ----
- + /*
- +  *  linux/arch/arm/ctexdbg_arch.h
- +  */
- + 
- + #ifndef _LINUX_CTEXDBG_ARCH_H
- + #define _LINUX_CTEXDBG_ARCH_H
- +  
- + #include <linux/kernel.h>
- + #include <linux/sched.h>
- + #include <linux/mm.h>
- + #include <linux/user.h>
- + 
- + #include <asm/uaccess.h>
- + #include <asm/pgtable.h>
- + #include <asm/system.h>
- + 
- + #include <linux/ctexdbg.h>
- + 
- + #ifdef CONFIG_CTEX_DBGLIB
- + 
- + /* scheduler change */
- + #if defined(CONFIG_CTEXDBG_ETM_CP15_PID_NAME)
- + /* set CP15.c3 pid and process name*/
- + inline void ctexdbg_arch_schedchange_event(unsigned long prevpid,unsigned long nextpid,unsigned char *next_comm)
- + {
- + 	register unsigned long cp;
- + 	register unsigned long temp;
- + 	barrier();
- + 	
- + 	if((ctexdbg_enabled == 0)&&(ctexdbg_hardware_trace_enabled == 0)) return;	
- + #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V7)
- + 	/* v6 only...*/
- + 	/* init. */
- + 	cp = 0;
- + 	__asm__ volatile(
- + 	"	mrc		p15,0,%0,c13,c0,1\n"
- + 	: "=r" (cp) : "0" (0) : "memory"
- + 	);
- + 	cp &= 0xff;
- + 	// process name 
- + 	temp = 0xff000000l |  (next_comm[0] << 16) | (next_comm[1] << 8) | cp;
- + 	__asm__ volatile(
- + 	"	mcr		p15,0,%0,c13,c0,1\n"
- + #if defined(CONFIG_CPU_V7)			
- + 	"	isb	\n"
- + #endif /* V7 */			
- + 	: : "r" (temp) : "memory"
- + 	);
- + 
- + 	temp = (next_comm[2] << 24)|  (next_comm[3] << 16) | (next_comm[4] << 8) | cp;
- + 	__asm__ volatile(
- + 	"	mcr		p15,0,%0,c13,c0,1\n"
- + #if defined(CONFIG_CPU_V7)			
- + 	"	isb	\n"
- + #endif /* V7 */			
- + 	: : "r" (temp) : "memory"
- + 	);
- + 	
- + 	temp = (next_comm[5] << 24)|  (next_comm[6] << 16) | (next_comm[7] << 8) | cp;
- + 	__asm__ volatile(
- + 	"	mcr		p15,0,%0,c13,c0,1\n"
- + #if defined(CONFIG_CPU_V7)			
- + 	"	isb	\n"
- + #endif /* V7 */	
- + 	: : "r" (temp) : "memory"
- + 	);
- + 
- + 	temp = (next_comm[8] << 24)|  (next_comm[9] << 16) | (next_comm[10] << 8) | cp;
- + 	__asm__ volatile(
- + 	"	mcr		p15,0,%0,c13,c0,1\n"
- + #if defined(CONFIG_CPU_V7)			
- + 	"	isb	\n"
- + #endif /* V7 */	
- + 	: : "r" (temp) : "memory"
- + 	);
- + 
- + 	temp = (next_comm[11] << 24)|  (next_comm[12] << 16) | (next_comm[13] << 8) | cp;
- + 	__asm__ volatile(
- + 	"	mcr		p15,0,%0,c13,c0,1\n"
- + #if defined(CONFIG_CPU_V7)			
- + 	"	isb	\n"
- + #endif /* V7 */	
- + 	: : "r" (temp) : "memory"
- + 	);
- + 
- + 	temp = (next_comm[14] << 24)|  (next_comm[15] << 16) | (0xfel << 8) | cp;
- + 	__asm__ volatile(
- + 	"	mcr		p15,0,%0,c13,c0,1\n"
- + #if defined(CONFIG_CPU_V7)			
- + 	"	isb	\n"
- + #endif /* V7 */	
- + 	: : "r" (temp) : "memory"
- + 	);
- + 
- + 	// process id
- + 	__asm__ volatile(
- + 	"	and		%1,%1,#0x000000FF\n"
- + 	"	mov		%0,%0,lsl #8\n"
- + 	"	orr		%1,%0,%1\n"
- + 	"	mcr		p15,0,%1,c13,c0,1\n"
- + #if defined(CONFIG_CPU_V7)			
- + 	"	isb	\n"
- + #endif /* V7 */	
- + 	: : "r" ((unsigned long)(nextpid)) , "r" ((unsigned long)(cp)) : "memory"
- + 	);
- + #endif /* V6 */
- + 
- + 	return;
- + }
- + 
- + #elif defined(CONFIG_CTEXDBG_ETM_CP15_PID_ONLY) || defined(CONFIG_CTEXDBG_ETM_CP15_PID_ONLY_V6)
- + /* set CP15.c3 pid */
- + inline void ctexdbg_arch_schedchange_event(unsigned long prevpid,unsigned long nextpid,unsigned char *next_comm)
- + {
- + 	register unsigned long unused;
- + 	barrier();
- + 	if((ctexdbg_enabled == 0)&&(ctexdbg_hardware_trace_enabled == 0)) return;	
- + 
- + #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V7)
- + 	__asm__ volatile(
- + 	"	mrc		p15,0,%0,c13,c0,1\n"
- + 	: "=r" (unused) : "0" (0) : "memory"
- + 	);
- + 	__asm__ volatile(
- + 	"	and		%1,%1,#0x000000FF\n"
- + 	"	mov		%0,%0,lsl #8\n"
- + 	"	orr		%1,%0,%1\n"
- + 	"	mcr		p15,0,%1,c13,c0,1\n"
- + #if defined(CONFIG_CPU_V7)			
- + 	"	isb	\n"
- + #endif /* V7 */
- + 	: : "r" ((unsigned long)(nextpid)), "r" ((unsigned long)(unused)) : "memory"
- + 	);
- + #else
- + 	/* not v6 no shift bit */
- + 	__asm__ volatile(
- + 	"	mcr		p15,0,%0,c13,c0,1\n"
- + 	: : "r" ((unsigned long)(nextpid)) : "memory"
- + 	);	
- + #endif /* V6 */
- + }
- + 
- + #else
- + inline void ctexdbg_arch_schedchange_event(unsigned long prevpid,unsigned long nextpid,unsigned char *next_comm)
- + {
- + 	/* V6 must be this */
- + #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V7)
- + 	register unsigned long unused;
- + 	barrier();
- + 	if((ctexdbg_enabled == 0)&&(ctexdbg_hardware_trace_enabled == 0)) return;	
- + 	
- + 	__asm__ volatile(
- + 	"	mrc		p15,0,%0,c13,c0,1\n"
- + 	: "=r" (unused) : "0" (0) : "memory"
- + 	);
- + 	__asm__ volatile(
- + 	"	and		%1,%1,#0x000000FF\n"
- + 	"	mov		%0,%0,lsl #8\n"
- + 	"	orr		%1,%0,%1\n"
- + 	"	mcr		p15,0,%1,c13,c0,1\n"
- + #if defined(CONFIG_CPU_V7)			
- + 	"	isb	\n"
- + #endif /* V7 */
- + 	: : "r" ((unsigned long)(nextpid)), "r" ((unsigned long)(unused)) : "memory"
- + 	);
- + #else
- + 	/* no v6 ... set pid external data to mem */
- + /*
- + 	ctexdbg_prevpid = prevpid; 
- + 	ctexdbg_nextpid = nextpid;
- + */
- + 	register unsigned long unused=0;
- + 	register unsigned long a = (unsigned long)&ctexdbg_prevpid;
- + 	register unsigned long b = (unsigned long)&ctexdbg_nextpid;
- + 	register unsigned long c = prevpid;
- + 	register unsigned long d = nextpid;
- + 
- + 	barrier();
- + 	if((ctexdbg_enabled == 0)&&(ctexdbg_hardware_trace_enabled == 0)) return;	
- + 
- + 	__asm__ volatile(
- + 	"	mcr		p15,0,%4,c7,c10,1\n"
- + 	"	mcr		p15,0,%0,c7,c10,4\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	str		%2,[%4,#0]\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	str		%1,[%3,#0]\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	:
- + 	: "r" ((unsigned long)(unused)),"r" ((unsigned long)(c)),"r" ((unsigned long)(d)),"r" ((unsigned long)(a)),"r" ((unsigned long)(b))
- + 	:  "memory"
- + 	);
- + 	
- + #endif /* V6 */
- + 	
- + }
- + 
- + #endif
- + 
- + 
- + #endif /* CONFIG_CTEX_DBGLIB */
- + 
- + #endif /* _LINUX_CTEXDBG_ARCH_H */
- + 
- diff -crN linux-3.2.1_o/arch/arm/include/asm/unistd.h linux-3.2.1_ctex/arch/arm/include/asm/unistd.h
- *** linux-3.2.1_o/arch/arm/include/asm/unistd.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1_ctex/arch/arm/include/asm/unistd.h	2013-05-24 10:28:31.930236842 +0900
- ***************
- *** 414,419 ****
- --- 414,422 ----
-   #define __ARM_NR_usr26			(__ARM_NR_BASE+3)
-   #define __ARM_NR_usr32			(__ARM_NR_BASE+4)
-   #define __ARM_NR_set_tls		(__ARM_NR_BASE+5)
- + #ifdef CONFIG_CTEX_DBGLIB
- + #define __ARM_NR_ctexnotify		(__ARM_NR_BASE+6)
- + #endif /* CONFIG_CTEX_DBGLIB */
-   
-   /*
-    * *NOTE*: This is a ghost syscall private to the kernel.  Only the
- diff -crN linux-3.2.1_o/arch/arm/Kconfig linux-3.2.1_ctex/arch/arm/Kconfig
- *** linux-3.2.1_o/arch/arm/Kconfig	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1_ctex/arch/arm/Kconfig	2013-05-24 10:28:32.338309049 +0900
- ***************
- *** 2244,2249 ****
- --- 2244,2251 ----
-   
-   source "security/Kconfig"
-   
- + source "arch/arm/Kconfig.ctex"
- + 
-   source "crypto/Kconfig"
-   
-   source "lib/Kconfig"
- diff -crN linux-3.2.1_o/arch/arm/Kconfig.ctex linux-3.2.1_ctex/arch/arm/Kconfig.ctex
- *** linux-3.2.1_o/arch/arm/Kconfig.ctex	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1_ctex/arch/arm/Kconfig.ctex	2013-05-24 10:28:32.621567975 +0900
- ***************
- *** 0 ****
- --- 1,62 ----
- + menu "Computex Linux dbglib"
- + 
- + config CTEX_DBGLIB
- + 	bool "Computex linux debug library support"
- + 	default n
- + 	help
- + 	  support computex linux debug library.
- + 	  Start the 'Computex Linux library' daemon just before stating the init process.
- + 	  and computex ICE support patch
- + 
- + if ((CPU_V6 || CPU_V7) && CTEX_DBGLIB)	  
- + choice
- + 	prompt "ETM Tracing mode (CPUV6 CPUV7)"
- + 	default CTEXDBG_ETM_CP15_PID_ONLY
- + 
- + config CTEXDBG_ETM_CP15_PID_NAME
- + 	bool "PID with ProcessName"
- + 
- + config CTEXDBG_ETM_CP15_PID_ONLY_V6
- + 	bool "PID Only"
- + 	
- + endchoice
- + 
- + endif
- + 
- + if (! (CPU_V6 || CPU_V7) && CTEX_DBGLIB)	  
- + choice
- + 	prompt "ETM Tracing mode"
- + 	default CTEXDBG_ETM_CP15_PID_NML
- + 
- + config CTEXDBG_ETM_CP15_PID_ONLY
- + 	bool "PID in CP15"
- + 
- + config CTEXDBG_ETM_CP15_PID_NML
- + 	bool "Not Use CP15"
- + 	
- + endchoice
- + 
- + endif
- + 
- + config CTEX_TRACE
- + 	bool "Enable process trace"
- + 	depends on CTEX_DBGLIB
- + 	default y
- + 	help
- + 	  say Y, Support process trace from ICE.
- + 
- + config CTEX_DBGLIB_MOD_NOINITEXIT
- + 	bool "disable _init _exit define (loadable module only)"
- + 	depends on CTEX_DBGLIB
- + 	default y
- + 	help
- + 	  say Y, disable __init and __exit defines.
- + 	  and support for loadable module debugging.
- + 
- + config CTEX_DBGLIB_ANDROID
- + 	bool "Enable google android support"
- + 	depends on CTEX_DBGLIB
- + 	default n
- + 	help
- + 	  say Y, Support google android system.
- + endmenu
- diff -crN linux-3.2.1_o/arch/arm/kernel/ctexdbg_arch.c linux-3.2.1_ctex/arch/arm/kernel/ctexdbg_arch.c
- *** linux-3.2.1_o/arch/arm/kernel/ctexdbg_arch.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1_ctex/arch/arm/kernel/ctexdbg_arch.c	2013-05-24 10:28:32.686599976 +0900
- ***************
- *** 0 ****
- --- 1,232 ----
- + /*
- +  *  linux/arch/arm/ctexdbg_arch.c
- +  *
- +  * (C) Copyright 2004 - Computex co.,ltd.
- +  *
- +  * Computex dbglib support kernel thread (arch depend)
- +  *
- +  */
- + 
- + #include <linux/kernel.h>
- + #include <linux/sched.h>
- + #include <linux/mm.h>
- + #include <linux/user.h>
- + 
- + #include <asm/uaccess.h>
- + #include <asm/pgtable.h>
- + #include <asm/system.h>
- + 
- + #include <linux/ctexdbg.h>
- + 
- + 
- + #include "../vfp/vfpinstr.h"
- + #include "../vfp/vfp.h"
- + 
- + #if defined(CONFIG_CTEX_DBGLIB)
- + 
- + extern spinlock_t ctexdbg_kernel_spinlock;		/* kernel lock */
- + 
- + #if defined(CONFIG_VFP)
- + extern union vfp_state *vfp_current_hw_state[NR_CPUS];	/* current vfp state */
- + #endif /* CONFIG_VFP */
- + 
- + /* ctexdbg fixeddata */
- + typedef struct __tag_ctexdbg_configdata
- + {
- + 	uint8_t trace_into_pname;	/* trace into process name 0: no 1:yes */
- + 	uint8_t trace_pid_in_mode;	/* trace pid in tracer 0: no use 1: memory in 2:CP15 (v6mode) 3:CP15 (v4mode)*/
- + 	
- + }ctexdbg_pri_config;
- + 
- + ctexdbg_pri_config ctexdbg_configdata;
- + 
- + /* private monitor */
- + uint32_t ctexdbg_monitor[64];
- + 
- + /* ------------------------------- event break area -------------------------------- */
- + #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V7)
- + /* arm 11xx */
- + void ctexdbg_event_core(void)
- + {
- + 	barrier();
- + 	/* ice breakcode (BKPT 0) */
- + 	__asm__ volatile(
- + 	".long	 0xE1200070\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	:::"lr"
- + 	);
- + }
- + #elif defined(CONFIG_ARCH_OMAP) || defined(CONFIG_CPU_ARM710) || defined(CONFIG_CPU_ARM720T) || defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T)
- + /* other (arm 920T omap15xx 16xx) */
- + void ctexdbg_event_core(void)
- + {
- + 	barrier();
- + 	/* ice breakcode */
- + 	/* LDR lr,[sp,#-4]! */
- + 	/* swi FFDFFF */
- + 	/* STR lr,[sp,#4] */
- + 	__asm__ volatile(
- + 	".long	 0xDFFFDFFF\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	:::"lr"
- + 	);
- + }
- + #else
- + void ctexdbg_event_core(void)
- + {
- + 	barrier();
- + 	/* ice breakcode (BKPT 0) */
- + 	__asm__ volatile(
- + 	".long	 0xE1200070\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	"	nop\n"
- + 	:::"lr"
- + 	);	
- + }
- + 
- + #endif /* V6 */
- + 
- + /* -------------------------------------------------------------------------------- */
- + /* ICE connection check */
- + int ctexdbg_arch_checkice(void)
- + {
- + 	barrier();
- + 	return 0;
- + }
- + 
- + /* ------------------------lock and unlock K ---------------------------------------- */
- + /* FORCE Interrupt disable and kernel locking (return OLD irqflasg)*/
- + unsigned long ctexdbg_arch_lock_kernel(void)
- + {
- + 	unsigned long flags;
- + 	barrier();
- + 	spin_lock_irqsave(&ctexdbg_kernel_spinlock, flags);	
- + 	return flags;
- + }
- +                                                                                 
- + /* unlock kernel and MSR restore (arg:oldval ... irqflag)*/
- + void ctexdbg_arch_unlock_kernel(unsigned long oldval)
- + {
- + 	barrier();
- + 	spin_unlock_irqrestore(&ctexdbg_kernel_spinlock, oldval);	
- + }
- + /* -------------------------------------------------------------------------------- */
- + 
- + 
- + /* ------------------------------- debugging func -------------------------------- */
- + /* [debug] print context registers */
- + void ctexdbg_print_context_reg(struct pt_regs *regs)
- + {
- + 	show_regs(regs);
- + }
- + 
- + /* why=r2 ptreg=r1 scno or sysreturn =r0 */
- + asmlinkage int ctexdbg_trace_syscall(int scno,struct pt_regs *regs,int why)
- + {
- + 	if(ctexdbg_traceuse == 0) return scno;
- + 	if(!why){
- + 		ctx_ev_syscall_entry(scno,instruction_pointer(regs));
- + 	}else{
- + 		ctx_ev_syscall_exit();
- + 	}
- + 	return scno;
- + }
- + 
- + /* save vfp to user context */
- + void ctexdbg_arch_vfpsave(struct thread_info *thread,u32 fpexc)
- + {
- + #if defined(CONFIG_VFP)
- + 	union vfp_state *vfp;
- + 	__u32 cpu;
- + 	/* debug process only */
- + 	if (ctexdbg_enabled == 0) return;
- + 	if (ctexdbg_find_debugpid(current->pid) == NULL) return;
- + 	
- + 	/* save current thread vfp  */
- + 	vfp = &(current_thread_info()->vfpstate);
- + 	vfp_save_state(vfp, fpexc);
- + 	cpu = thread->cpu;
- + 	/* reload context vfp to next vfp exception. */
- + 	vfp_current_hw_state[cpu] = NULL;		
- + #endif
- + }
- + 
- + int ctexdbg_arch_init(void)
- + {
- + 	barrier();
- + 	ctexdbg_configdata.trace_into_pname = 0;
- + 	ctexdbg_configdata.trace_pid_in_mode = 0;
- + 	
- + #if defined(CONFIG_CTEXDBG_ETM_CP15_PID_NAME)
- + #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V7)
- + 	ctexdbg_configdata.trace_into_pname = 1;		/* use name */
- + 	ctexdbg_configdata.trace_pid_in_mode = 2;		/* PID in CP15 V6 or V7 */
- + #endif
- + 
- + #elif defined(CONFIG_CTEXDBG_ETM_CP15_PID_ONLY) || defined(CONFIG_CTEXDBG_ETM_CP15_PID_ONLY_V6)
- + #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V7)
- + 	ctexdbg_configdata.trace_pid_in_mode = 2;		/* PID in CP15 V6 or V7 */
- + #else
- + 	ctexdbg_configdata.trace_pid_in_mode = 3;		/* PID in CP15 V4 */
- + #endif
- + #else
- + #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V7)
- + 	ctexdbg_configdata.trace_pid_in_mode = 2;		/* PID in CP15 V6 or V7 */
- + #else
- + 	ctexdbg_configdata.trace_pid_in_mode = 1;		/* PID in memory */
- + #endif
- + 
- + #endif
- + 	return 0;
- + }
- + 
- + 
- + #endif /* CONFIG_CTEX_DBGLIB */
- diff -crN linux-3.2.1_o/arch/arm/kernel/entry-common.S linux-3.2.1_ctex/arch/arm/kernel/entry-common.S
- *** linux-3.2.1_o/arch/arm/kernel/entry-common.S	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1_ctex/arch/arm/kernel/entry-common.S	2013-05-24 10:28:32.769559504 +0900
- ***************
- *** 85,94 ****
- --- 85,104 ----
-   ENTRY(ret_from_fork)
-   	bl	schedule_tail
-   	get_thread_info tsk
- + #if defined(CONFIG_CTEX_TRACE)
- + 	mov	why, #1
- + 	ldr	r1 ,=ctexdbg_traceuse
- + 	ldr	r1,[r1]
- + 	cmp	r1 ,#1
- + 	beq	__ctrace_ret
- + #endif			
-   	ldr	r1, [tsk, #TI_FLAGS]		@ check for syscall tracing
-   	mov	why, #1
-   	tst	r1, #_TIF_SYSCALL_TRACE		@ are we tracing syscalls?
-   	beq	ret_slow_syscall
- + #if defined(CONFIG_CTEX_TRACE)
- + __ctrace_ret:
- + #endif	
-   	mov	r1, sp
-   	mov	r0, #1				@ trace exit [IP = 1]
-   	bl	syscall_trace
- ***************
- *** 432,437 ****
- --- 442,454 ----
-   
-   	ldr	r10, [tsk, #TI_FLAGS]		@ check for syscall tracing
-   	stmdb	sp!, {r4, r5}			@ push fifth and sixth args
- + #if defined(CONFIG_CTEX_TRACE)
- + 	ldr	ip,=ctexdbg_traceuse
- + 	ldr	ip,[ip]
- + 	cmp	ip, #1
- + 	ldr	ip, [tsk, #TI_FLAGS]		@ check for syscall tracing	
- + 	beq	__sys_trace
- + #endif
-   
-   #ifdef CONFIG_SECCOMP
-   	tst	r10, #_TIF_SECCOMP
- diff -crN linux-3.2.1_o/arch/arm/kernel/Makefile linux-3.2.1_ctex/arch/arm/kernel/Makefile
- *** linux-3.2.1_o/arch/arm/kernel/Makefile	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1_ctex/arch/arm/kernel/Makefile	2013-05-24 10:28:32.769559504 +0900
- ***************
- *** 62,67 ****
- --- 62,69 ----
-   CFLAGS_swp_emulate.o		:= -Wa,-march=armv7-a
-   obj-$(CONFIG_HAVE_HW_BREAKPOINT)	+= hw_breakpoint.o
-   
- + obj-$(CONFIG_CTEX_DBGLIB)	+= ctexdbg_arch.o
- + 
-   obj-$(CONFIG_CRUNCH)		+= crunch.o crunch-bits.o
-   AFLAGS_crunch-bits.o		:= -Wa,-mcpu=ep9312
-   
- diff -crN linux-3.2.1_o/arch/arm/kernel/process.c linux-3.2.1_ctex/arch/arm/kernel/process.c
- *** linux-3.2.1_o/arch/arm/kernel/process.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1_ctex/arch/arm/kernel/process.c	2013-05-24 10:28:32.802326944 +0900
- ***************
- *** 31,36 ****
- --- 31,37 ----
-   #include <linux/random.h>
-   #include <linux/hw_breakpoint.h>
-   #include <linux/cpuidle.h>
- + #include <linux/ctexdbg.h>
-   
-   #include <asm/cacheflush.h>
-   #include <asm/leds.h>
- ***************
- *** 449,455 ****
-   pid_t kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
-   {
-   	struct pt_regs regs;
- ! 
-   	memset(&regs, 0, sizeof(regs));
-   
-   	regs.ARM_r4 = (unsigned long)arg;
- --- 450,458 ----
-   pid_t kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
-   {
-   	struct pt_regs regs;
- ! #ifdef CONFIG_CTEX_TRACE
- ! 	long pid;
- ! #endif
-   	memset(&regs, 0, sizeof(regs));
-   
-   	regs.ARM_r4 = (unsigned long)arg;
- ***************
- *** 459,465 ****
- --- 462,474 ----
-   	regs.ARM_pc = (unsigned long)kernel_thread_helper;
-   	regs.ARM_cpsr = regs.ARM_r7 | PSR_I_BIT;
-   
- + #ifdef CONFIG_CTEX_TRACE
- + 	pid = do_fork(flags|CLONE_VM|CLONE_UNTRACED, 0, &regs, 0, NULL, NULL);
- + 	ctx_ev_process(CTX_EV_PROCESS_KTHREAD,(u32)pid,(ulong)fn);
- + 	return pid;
- + #else
-   	return do_fork(flags|CLONE_VM|CLONE_UNTRACED, 0, &regs, 0, NULL, NULL);
- + #endif
-   }
-   EXPORT_SYMBOL(kernel_thread);
-   
- diff -crN linux-3.2.1_o/arch/arm/kernel/ptrace.c linux-3.2.1_ctex/arch/arm/kernel/ptrace.c
- *** linux-3.2.1_o/arch/arm/kernel/ptrace.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1_ctex/arch/arm/kernel/ptrace.c	2013-05-24 10:28:32.807261850 +0900
- ***************
- *** 23,28 ****
- --- 23,29 ----
-   #include <linux/perf_event.h>
-   #include <linux/hw_breakpoint.h>
-   #include <linux/regset.h>
- + #include <linux/ctexdbg.h>
-   
-   #include <asm/pgtable.h>
-   #include <asm/system.h>
- ***************
- *** 902,911 ****
- --- 903,920 ----
-   	return ret;
-   }
-   
- + #ifdef CONFIG_CTEX_DBGLIB
- + extern void ctexdbg_trace_syscall(int why, struct pt_regs *regs, int scno);
- + #endif
- + 
-   asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno)
-   {
-   	unsigned long ip;
-   
- + #ifdef CONFIG_CTEX_DBGLIB
- + 	ctexdbg_trace_syscall(scno,regs,why);
- + #endif
- + 
-   	if (!test_thread_flag(TIF_SYSCALL_TRACE))
-   		return scno;
-   	if (!(current->ptrace & PT_PTRACED))
- ***************
- *** 937,939 ****
- --- 946,963 ----
-   
-   	return current_thread_info()->syscall;
-   }
- + 
- + #ifdef CONFIG_CTEX_DBGLIB
- + /*
- +  * calc context user register base addr.
- +  */
- + void ctexdbg_arch_userregaddr(void)
- + {
- + 	/*
- + 	return (struct pt_regs *)
- + 		((unsigned long)task->thread_info + THREAD_SIZE -
- + 				 8 - sizeof(struct pt_regs));	
- + 	*/
- + 	ctexdbg_fixdata.userregaddr = THREAD_SIZE -  8 - sizeof(struct pt_regs);
- + }
- + #endif /* CONFIG_CTEX_DBGLIB */
- diff -crN linux-3.2.1_o/arch/arm/kernel/sys_oabi-compat.c linux-3.2.1_ctex/arch/arm/kernel/sys_oabi-compat.c
- *** linux-3.2.1_o/arch/arm/kernel/sys_oabi-compat.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1_ctex/arch/arm/kernel/sys_oabi-compat.c	2013-05-24 10:30:53.161565000 +0900
- ***************
- *** 84,89 ****
- --- 84,90 ----
-   #include <linux/ipc.h>
-   #include <linux/uaccess.h>
-   #include <linux/slab.h>
- + #include <linux/ctexdbg.h>
-   
-   struct oldabi_stat64 {
-   	unsigned long long st_dev;
- ***************
- *** 349,354 ****
- --- 350,358 ----
-   asmlinkage int sys_oabi_ipc(uint call, int first, int second, int third,
-   			    void __user *ptr, long fifth)
-   {
- + #ifdef CONFIG_CTEX_TRACE
- + 	ctx_ev_ipc(CTX_EV_IPC_CALL,call,first);
- + #endif
-   	switch (call & 0xffff) {
-   	case SEMOP:
-   		return  sys_oabi_semtimedop(first,
- diff -crN linux-3.2.1_o/arch/arm/kernel/traps.c linux-3.2.1_ctex/arch/arm/kernel/traps.c
- *** linux-3.2.1_o/arch/arm/kernel/traps.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1_ctex/arch/arm/kernel/traps.c	2013-05-24 10:28:32.823315475 +0900
- ***************
- *** 25,30 ****
- --- 25,31 ----
-   #include <linux/delay.h>
-   #include <linux/init.h>
-   #include <linux/sched.h>
- + #include <linux/ctexdbg.h>
-   
-   #include <linux/atomic.h>
-   #include <asm/cacheflush.h>
- ***************
- *** 298,305 ****
-   	if (user_mode(regs)) {
-   		current->thread.error_code = err;
-   		current->thread.trap_no = trap;
- ! 
-   		force_sig_info(info->si_signo, info, current);
-   	} else {
-   		die(str, regs, err);
-   	}
- --- 299,311 ----
-   	if (user_mode(regs)) {
-   		current->thread.error_code = err;
-   		current->thread.trap_no = trap;
- ! #if defined(CONFIG_CTEX_TRACE)
- ! 		ctx_ev_trap_entry(current->thread.trap_no,instruction_pointer(regs));
- ! #endif
-   		force_sig_info(info->si_signo, info, current);
- + #if defined(CONFIG_CTEX_TRACE)
- + 		ctx_ev_trap_exit();
- + #endif
-   	} else {
-   		die(str, regs, err);
-   	}
- ***************
- *** 503,508 ****
- --- 509,521 ----
-   	struct thread_info *thread = current_thread_info();
-   	siginfo_t info;
-   
- + #ifdef CONFIG_CTEX_DBGLIB	
- + 	if(no == 0xFFDFFF){
- + 		/* ICE breakcode */
- + 		return 0;
- + 	}
- + #endif /* CONFIG_CTEX_DBGLIB */
- + 	
-   	if ((no >> 16) != (__ARM_NR_BASE>> 16))
-   		return bad_syscall(no, regs);
-   
- ***************
- *** 539,544 ****
- --- 552,563 ----
-   		do_cache_op(regs->ARM_r0, regs->ARM_r1, regs->ARM_r2);
-   		return 0;
-   
- + #ifdef CONFIG_CTEX_DBGLIB	
- + 	case NR(ctexnotify): /* SWI ctexnotify */
- + 		ctexdbg_external_notify((size_t)regs->ARM_r0,(void*)regs->ARM_r1);
- + 		return 0;
- + #endif /* CONFIG_CTEX_DBGLIB */
- + 		
-   	case NR(usr26):
-   		if (!(elf_hwcap & HWCAP_26BIT))
-   			break;
- diff -crN linux-3.2.1_o/arch/arm/mm/mmu.c linux-3.2.1_ctex/arch/arm/mm/mmu.c
- *** linux-3.2.1_o/arch/arm/mm/mmu.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1_ctex/arch/arm/mm/mmu.c	2013-05-24 10:28:32.951096061 +0900
- ***************
- *** 30,35 ****
- --- 30,36 ----
-   #include <asm/mach/map.h>
-   
-   #include "mm.h"
- + #include <linux/ctexdbg.h>
-   
-   /*
-    * empty_zero_page is a special page that is used for
- ***************
- *** 704,709 ****
- --- 705,714 ----
-   	addr = md->virtual & PAGE_MASK;
-   	phys = __pfn_to_phys(md->pfn);
-   	length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
- + 	
- + #ifdef CONFIG_CTEX_DBGLIB
- + 	ctexdbg_add_memmap(md->virtual,__pfn_to_phys(md->pfn),md->length);
- + #endif /* CONFIG_CTEX_DBGLIB */	
-   
-   	if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
-   		printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not "
- diff -crN linux-3.2.1_o/arch/arm/vfp/vfpmodule.c linux-3.2.1_ctex/arch/arm/vfp/vfpmodule.c
- *** linux-3.2.1_o/arch/arm/vfp/vfpmodule.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1_ctex/arch/arm/vfp/vfpmodule.c	2013-05-24 10:39:25.649877000 +0900
- ***************
- *** 21,30 ****
- --- 21,35 ----
-   #include <asm/cputype.h>
-   #include <asm/thread_notify.h>
-   #include <asm/vfp.h>
- + #include <linux/ctexdbg.h>
-   
-   #include "vfpinstr.h"
-   #include "vfp.h"
-   
- + #ifdef CONFIG_CTEX_DBGLIB
- + extern void ctexdbg_arch_vfpsave(struct thread_info *thread,u32 fpexc);
- + #endif /* CONFIG_CTEX_DBGLIB */
- + 
-   /*
-    * Our undef handlers (in entry.S)
-    */
- ***************
- *** 505,510 ****
- --- 510,521 ----
-   	if (vfp_state_in_hw(cpu, thread)) {
-   		u32 fpexc = fmrx(FPEXC);
-   
- + #ifdef CONFIG_CTEX_DBGLIB
- + 		if((fpexc & FPEXC_EN)){
- + 			ctexdbg_arch_vfpsave(thread,fpexc);
- + 		}
- + #endif /* CONFIG_CTEX_DBGLIB */	
- + 		
-   		/*
-   		 * Save the last VFP state on this CPU.
-   		 */
- diff -crN linux-3.2.1_o/fs/binfmt_elf.c linux-3.2.1_ctex/fs/binfmt_elf.c
- *** linux-3.2.1_o/fs/binfmt_elf.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1_ctex/fs/binfmt_elf.c	2013-05-24 10:28:33.046366491 +0900
- ***************
- *** 35,40 ****
- --- 35,41 ----
-   #include <asm/uaccess.h>
-   #include <asm/param.h>
-   #include <asm/page.h>
- + #include <linux/ctexdbg.h>
-   
-   static int load_elf_binary(struct linux_binprm *bprm, struct pt_regs *regs);
-   static int load_elf_library(struct file *);
- ***************
- *** 984,989 ****
- --- 985,996 ----
-   #endif
-   
-   	start_thread(regs, elf_entry, bprm->p);
- + 
- + #if defined(CONFIG_CTEX_DBGLIB)
- + 	if(current->mm != NULL){
- + 		ctexdbg_main_pre_brk(current,elf_entry,(unsigned long)current->mm->pgd);
- + 	}
- + #endif
-   	retval = 0;
-   out:
-   	kfree(loc);
- diff -crN linux-3.2.1_o/fs/buffer.c linux-3.2.1_ctex/fs/buffer.c
- *** linux-3.2.1_o/fs/buffer.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1_ctex/fs/buffer.c	2013-05-24 10:28:33.177549688 +0900
- ***************
- *** 42,47 ****
- --- 42,48 ----
-   #include <linux/mpage.h>
-   #include <linux/bit_spinlock.h>
-   #include <linux/cleancache.h>
- + #include <linux/ctexdbg.h>
-   
-   static int fsync_buffers_list(spinlock_t *lock, struct list_head *list);
-   
- ***************
- *** 83,89 ****
- --- 84,96 ----
-    */
-   void __wait_on_buffer(struct buffer_head * bh)
-   {
- + #ifdef CONFIG_CTEX_TRACE
- + 	ctx_ev_file_system(CTX_EV_FILE_SYSTEM_BUF_WAIT_START,0,0,NULL);	
- + #endif
-   	wait_on_bit(&bh->b_state, BH_Lock, sleep_on_buffer, TASK_UNINTERRUPTIBLE);
- + #ifdef CONFIG_CTEX_TRACE
- + 	ctx_ev_file_system(CTX_EV_FILE_SYSTEM_BUF_WAIT_END, 0, 0, NULL);	
- + #endif
-   }
-   EXPORT_SYMBOL(__wait_on_buffer);
-   
- diff -crN linux-3.2.1_o/fs/exec.c linux-3.2.1_ctex/fs/exec.c
- *** linux-3.2.1_o/fs/exec.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1_ctex/fs/exec.c	2013-05-24 10:28:33.231278936 +0900
- ***************
- *** 55,60 ****
- --- 55,61 ----
-   #include <linux/pipe_fs_i.h>
-   #include <linux/oom.h>
-   #include <linux/compat.h>
- + #include <linux/ctexdbg.h>
-   
-   #include <asm/uaccess.h>
-   #include <asm/mmu_context.h>
- ***************
- *** 1515,1520 ****
- --- 1516,1528 ----
-   	if ((retval = bprm->envc) < 0)
-   		goto out;
-   
- + #if defined(CONFIG_CTEX_DBGLIB)		
- + 	ctexdbg_file_event(
- + 		current,
- + 		file,
- + 		(uint32_t)bprm->mm->pgd
- + 	);	
- + #endif		
-   	retval = prepare_binprm(bprm);
-   	if (retval < 0)
-   		goto out;
- ***************
- *** 1528,1533 ****
- --- 1536,1548 ----
-   	if (retval < 0)
-   		goto out;
-   
- + #if defined(CONFIG_CTEX_DBGLIB)
- + 	/* add special envp */
- + 	retval = ctexdbg_get_subenvp((char*)file->f_dentry->d_name.name, bprm);
- + 	if (retval < 0) 
- + 		goto out; 
- + #endif /* CONFIG_CTEX_DBGLIB */
- + 
-   	retval = copy_strings(bprm->argc, argv, bprm);
-   	if (retval < 0)
-   		goto out;
- ***************
- *** 1536,1541 ****
- --- 1551,1560 ----
-   	if (retval < 0)
-   		goto out;
-   
- + #ifdef CONFIG_CTEX_TRACE
- + 	ctx_ev_file_system(CTX_EV_FILE_SYSTEM_EXEC,0,strlen(filename),filename);	
- + #endif
- + 
-   	/* execve succeeded */
-   	current->fs->in_exec = 0;
-   	current->in_execve = 0;
- diff -crN linux-3.2.1_o/fs/ioctl.c linux-3.2.1_ctex/fs/ioctl.c
- *** linux-3.2.1_o/fs/ioctl.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1_ctex/fs/ioctl.c	2013-05-24 10:28:33.306350556 +0900
- ***************
- *** 15,20 ****
- --- 15,21 ----
-   #include <linux/writeback.h>
-   #include <linux/buffer_head.h>
-   #include <linux/falloc.h>
- + #include <linux/ctexdbg.h>
-   
-   #include <asm/ioctls.h>
-   
- ***************
- *** 611,616 ****
- --- 612,621 ----
-   	if (!filp)
-   		goto out;
-   
- + #ifdef CONFIG_CTEX_TRACE
- + 	ctx_ev_file_system(CTX_EV_FILE_SYSTEM_IOCTL,fd,cmd,NULL);
- + #endif
- + 
-   	error = security_file_ioctl(filp, cmd, arg);
-   	if (error)
-   		goto out_fput;
- diff -crN linux-3.2.1_o/fs/open.c linux-3.2.1_ctex/fs/open.c
- *** linux-3.2.1_o/fs/open.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1_ctex/fs/open.c	2013-05-24 10:28:33.366365696 +0900
- ***************
- *** 30,35 ****
- --- 30,36 ----
-   #include <linux/fs_struct.h>
-   #include <linux/ima.h>
-   #include <linux/dnotify.h>
- + #include <linux/ctexdbg.h>
-   
-   #include "internal.h"
-   
- ***************
- *** 988,993 ****
- --- 989,997 ----
-   				fsnotify_open(f);
-   				fd_install(fd, f);
-   			}
- + #ifdef CONFIG_CTEX_TRACE
- + 		ctx_ev_file_system(CTX_EV_FILE_SYSTEM_OPEN,0,strlen(tmp),tmp);
- + #endif
-   		}
-   		putname(tmp);
-   	}
- ***************
- *** 1079,1084 ****
- --- 1083,1093 ----
-   	filp = fdt->fd[fd];
-   	if (!filp)
-   		goto out_unlock;
- + 
- + #ifdef CONFIG_CTEX_TRACE
- + 	ctx_ev_file_system(CTX_EV_FILE_SYSTEM_CLOSE,fd,0,NULL);
- + #endif
- + 
-   	rcu_assign_pointer(fdt->fd[fd], NULL);
-   	FD_CLR(fd, fdt->close_on_exec);
-   	__put_unused_fd(files, fd);
- diff -crN linux-3.2.1_o/fs/read_write.c linux-3.2.1_ctex/fs/read_write.c
- *** linux-3.2.1_o/fs/read_write.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1_ctex/fs/read_write.c	2013-05-24 10:28:33.369655090 +0900
- ***************
- *** 15,20 ****
- --- 15,21 ----
-   #include <linux/syscalls.h>
-   #include <linux/pagemap.h>
-   #include <linux/splice.h>
- + #include <linux/ctexdbg.h>
-   #include "read_write.h"
-   
-   #include <asm/uaccess.h>
- ***************
- *** 245,250 ****
- --- 246,254 ----
-   		if (res != (loff_t)retval)
-   			retval = -EOVERFLOW;	/* LFS: should only happen on 32 bit platforms */
-   	}
- + #ifdef CONFIG_CTEX_TRACE
- + 	ctx_ev_file_system(CTX_EV_FILE_SYSTEM_SEEK,fd,offset,NULL);
- + #endif
-   	fput_light(file, fput_needed);
-   bad:
-   	return retval;
- ***************
- *** 466,471 ****
- --- 470,478 ----
-   	file = fget_light(fd, &fput_needed);
-   	if (file) {
-   		loff_t pos = file_pos_read(file);
- + #ifdef CONFIG_CTEX_TRACE
- + 		ctx_ev_file_system(CTX_EV_FILE_SYSTEM_READ,fd,count,NULL);
- + #endif
-   		ret = vfs_read(file, buf, count, &pos);
-   		file_pos_write(file, pos);
-   		fput_light(file, fput_needed);
- ***************
- *** 485,490 ****
- --- 492,500 ----
-   	if (file) {
-   		loff_t pos = file_pos_read(file);
-   		ret = vfs_write(file, buf, count, &pos);
- + #ifdef CONFIG_CTEX_TRACE
- + 		ctx_ev_file_system(CTX_EV_FILE_SYSTEM_WRITE,fd,count,NULL);
- + #endif
-   		file_pos_write(file, pos);
-   		fput_light(file, fput_needed);
-   	}
- diff -crN linux-3.2.1_o/fs/select.c linux-3.2.1_ctex/fs/select.c
- *** linux-3.2.1_o/fs/select.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1_ctex/fs/select.c	2013-05-24 10:37:23.556894000 +0900
- ***************
- *** 26,31 ****
- --- 26,32 ----
-   #include <linux/fs.h>
-   #include <linux/rcupdate.h>
-   #include <linux/hrtimer.h>
- + #include <linux/ctexdbg.h>
-   
-   #include <asm/uaccess.h>
-   
- ***************
- *** 450,455 ****
- --- 451,459 ----
-   				file = fget_light(i, &fput_needed);
-   				if (file) {
-   					f_op = file->f_op;
- + #ifdef CONFIG_CTEX_TRACE
- + 					ctx_ev_file_system(CTX_EV_FILE_SYSTEM_SELECT,i,(u32)timed_out,NULL);
- + #endif
-   					mask = DEFAULT_POLLMASK;
-   					if (f_op && f_op->poll) {
-   						wait_key_set(wait, in, out, bit);
- ***************
- *** 737,742 ****
- --- 741,749 ----
-   		mask = POLLNVAL;
-   		if (file != NULL) {
-   			mask = DEFAULT_POLLMASK;
- + #ifdef CONFIG_CTEX_TRACE
- + 			ctx_ev_file_system(CTX_EV_FILE_SYSTEM_POLL,fd,0,NULL);
- + #endif
-   			if (file->f_op && file->f_op->poll) {
-   				if (pwait)
-   					pwait->key = pollfd->events |
- diff -crN linux-3.2.1_o/include/linux/ctexdbg.h linux-3.2.1_ctex/include/linux/ctexdbg.h
- *** linux-3.2.1_o/include/linux/ctexdbg.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1_ctex/include/linux/ctexdbg.h	2013-05-24 10:28:33.486344022 +0900
- ***************
- *** 0 ****
- --- 1,299 ----
- + /*
- +  * linux/include/linux/ctexdbg.h
- +  *
- +  * (C) Copyright 2004 - Computex co.,ltd.
- +  *
- +  * Computex dbglib support kernel thread
- +  *
- +  * -- version info --------------------------------------------------
- +  *
- +  * version 014   - 2008/07/18	 update patch version
- +  *                               + change process trace
- +  *                               + cleanup code
- +  *                               + support Linux 2.6.22.1
- +  *
- +  * version 013   - 2008/04/10	 update patch version
- +  *                               + fix loadable module install
- +  *
- +  * version 012   - 2007/07/26	 update patch version
- +  *                               + add selective user-mode fake xip (cramfs)
- +  *				 + support Linux 2.6.21
- +  *
- +  * version 011   - 2007/06/30	update patch version
- +  *								 + support SMP Kern
- +  *                               + add file operation buffer
- +  *                               + add monitor buffer
- +  *                               + fix: sleep_on -> wait_event
- +  *
- +  * version 009_6 - 2007/01/17	update patch version
- +  *								 + addandfix: ctexdbg_do_check_page
- +  *								 + support Linux 2.6.14 and 16 
- +  *
- +  * version 009_5 - 2007/01/13	update patch version
- +  * 								 + support user-mode fake XIP (cramfs)
- +  * 								 + fix: strict findfile
- +  * 								 + fix: a lot of warning
- +  *
- +  * version 009 - 2006/04/xx		update patch version
- +  * 								 + support PALMiCE 2H mode
- +  *                                 + add ctexdbg_hardware_trace_enabled
- +  *                                 + change ctexdbg_schedchange_event
- +  *
- +  * version 008 - 2005/12/xx		update patch version
- +  * 								support file rename chmod chown
- +  *								add CTEXDBG_EV_PREMAIN event
- +  *								support linux 2.6.x
- +  *
- +  * version 007 - 2005/11/xx		update patch version
- +  *
- +  * version 006 - 2005/05/xx		update patch version
- +  *								 + change ctexdbg_event
- +  *								 + Add process exit throw mode
- +  *								 + Add check load module debug file list
- +  *
- +  * version 005 - 2005/02/23		first release version
- +  *								 + Add version 
- +  *								 + CONFIG_TRACE_MODULE option support
- +  *
- +  * version 004 - 2005/02/1x		pre version
- +  *
- +  * -------------------------------------------------------------------
- +  *
- +  */
- + 
- + #ifndef _LINUX_CTEXDBG_H
- + #define _LINUX_CTEXDBG_H
- + 
- + #include <linux/types.h>
- + 
- + /* Is defined me ? */
- + #if defined(CONFIG_CTEX_DBGLIB)
- + 
- + /* Patch Version */
- + #define CTEXDBG_PATCH_VERSION	"014"
- + 
- + 
- + /* process breakpoint max */
- + #define CTEXDBG_PBP_MAX	256
- + #define CTEXDBG_PGOFF_MAX	256
- + #define CTEXDBG_MODULE_MAX 256
- + 
- + /* internal buffer size */
- + #define CTEXDBG_WORKBUF_START 20
- + #define CTEXDBG_WORKBUF_SIZE 1024
- + #define CTEXDBG_WORKBUF_END (CTEXDBG_WORKBUF_SIZE - CTEXDBG_WORKBUF_START - 1)
- + 
- + /* event buffer size */
- + #define CTEXDBG_EVENTBUF_SIZE	50000
- + 
- + /* num of Debug process */
- + #define CTEXDBG_PIDSIZE_MAX		512
- + 
- + #define CTEXDBG_DBG_FNAMESIZE	2000
- + #define CTEXDBG_MMAPDATA_SIZE	256
- + #define CTEXDBG_EVENT_FNAMESIZE	2000
- + #define CTEXTRC_MASK_SIZE 80
- + 
- + 
- + enum CTEXDBG_ICEFunction
- + {
- + 	CTEXDBG_NONE	= 0,		/* Noop */
- + 	CTEXDBG_DBGPUT,				/* printk a ctexdbg_combuf (internal-debugging) */
- + 	CTEXDBG_SENDSIG,			/* signal send to process */
- + 	CTEXDBG_CONTINUE,			/* continue a braek process */
- + 	CTEXDBG_FORCEBREAK,			/* force braek process */
- + 	CTEXDBG_LTTRACE_START,		/* start LTTrace */
- + 	CTEXDBG_LTTRACE_STOP,		/* stop LTTrace */
- + 	CTEXDBG_EVENT_SETBUFSIZE,	/* Event buffersize reset */
- + 	CTEXDBG_FILE_LS,			/* Enum Directory list */
- + 	CTEXDBG_FILE_RMDIR,			/* rmdir */
- + 	CTEXDBG_FILE_MKDIR,			/* mkdir */
- + 	CTEXDBG_FILE_DELETE,		/* delete target fs data */
- + 	CTEXDBG_FILE_READ,			/* read target fs data to HOST */
- + 	CTEXDBG_FILE_WRITE,			/* write host file data to target fs */
- + 	CTEXDBG_TEST,				/* funciton test */
- + 	CTEXDBG_FILE_RENAME,		/* Rename file/Dir */
- + 	CTEXDBG_FILE_CHMOD,			/* Change attributes of file/Dir */
- + 	CTEXDBG_FILE_CHOWN,			/* Change Owner */	
- + };
- + 
- + enum CTEXDBG_EVENTINFO
- + {
- + 	CTEXDBG_EV_NONE	= 0,		/* Noop */
- + 	CTEXDBG_EV_FORK,			/* forking */
- + 	CTEXDBG_EV_SIGNAL,			/* signal recv */
- + 	CTEXDBG_EV_EXECVP,			/* execute process */
- + 	CTEXDBG_EV_PBREAK_WAKEUP,	/* processbreak wakeup */
- + 	CTEXDBG_EV_PBREAK_FBREAK,	/* force break */
- + 	CTEXDBG_EV_NOPAGE,			/* no page */
- + 	CTEXDBG_EV_PBREAK_FBREAK_WAKEUP,	/* force break wakeup */
- + 	CTEXDBG_EV_SIGNAL_WAKEUP,		/* signal braek wakeup */
- + 	CTEXDBG_EV_LTTFULL,		/* ltt buffre full */
- + 	CTEXDBG_EV_FILEMAP,		/* file mapping */
- + 	CTEXDBG_EV_WAITDATA,	/* data wait */
- + 	CTEXDBG_EV_EXIT,		/* exit program */
- + 	CTEXDBG_EV_MODULE_INIT,  /* modukle preload */
- + 	CTEXDBG_EV_EVENTFULL,	/* event buffre full */
- + 	CTEXDBG_EV_EXIT_WAIT,	/* exit() wait */
- + 	CTEXDBG_EV_EXIT_WAKEUP,	/* exit() wait wakeup */
- + 	CTEXDBG_EV_FILE_LSFULL,	/* file lsdata full*/
- + 	CTEXDBG_EV_FILE_READ,	/* target file read. send to host */
- + 	CTEXDBG_EV_FILE_WRITE,	/* file recv from target. file writing */
- + 	CTEXDBG_EV_FILE_END,	/* end of file operate */
- + 	CTEXDBG_EV_EVENTSET_END,	/* end of ctexdbg event setting */		
- + 	CTEXDBG_EV_LTTRACE_STARTACK,	/* ltt start ack */		
- + 	CTEXDBG_EV_FORK_S,			/* forkint(nochkmode) */
- + 	CTEXDBG_EV_ICECONNECT,		/* ICE Connection OK */
- + 	CTEXDBG_EV_PREMAIN,		/* main() func pre break */
- + 	CTEXDBG_EV_EXT_TRAP,	/* External trap break */
- + 	CTEXDBG_EV_MIGRATION,	/* migration CPU break */
- + };
- + 
- + 
- + /* ctexdbg fixeddata */
- + typedef struct __tag_ctexdbg_fixdata
- + {
- + 	uint32_t maxsigno;			/* max signal number */
- + 	uint32_t userregaddr;		/* user register base addr */
- + 	/* v006 max size define*/
- + 	uint32_t maxdbgfilelen;		/* max ctexdbgdgbfile length */
- + 	uint32_t maxmapdatalen;		/* max mapdata length */
- + 	uint32_t maxevtasklen;		/* max ctexdbg_eventtskname length */
- + 	uint32_t maxtrcmasklen;		/* max cdbtrc_mask_table length */
- + 	
- + }ctexdbg_fix;
- + 
- + 
- + /* check page in area */
- + typedef struct __tag_ctexdbg_checkarea
- + {
- + 	uint32_t address;			/* address (virtual) */
- + 	uint32_t pid;				/* process id */
- + 	uint32_t pgd;				/* process pgd */
- + }ctexdbg_checkarea;
- + 
- + typedef struct __tag_cdbtrc_bufpos
- + {
- + 	char* sEventBuf;                  /* Event Buffer */
- + 	char* sEventWritPos;              /* Current position for writting */
- + 	char* sEventReadPos;              /* Current position for reading */
- + 	char* sEventWritLimit;            /* Limit at which write should stop */	
- + 	uint32_t  sEventBufDir;			  /* Buffer dir */
- + }cdbtrc_bufpos;
- + 
- + typedef struct __tag_ctexdbg_mmap
- + {
- + 	uint32_t virtaddr;
- + 	uint32_t physaddr;
- + 	uint32_t length;
- + }ctexdbg_mmap;
- + 
- + /* module symbol information */
- + typedef struct __tag_ctexdbg_modsyms
- + {
- + 	struct module *mod;			/* ptr of module */
- + 	uint32_t start_addr;			/* start text address */
- + 	uint32_t symtab_addr;			/* symbol table address */
- + 	uint32_t numsym;			/* number of symbol */
- + 	uint32_t strtab_addr;			/* string table address */
- + 	uint32_t rodata_addr;			/* rodata section address */
- + 	uint32_t data_addr;			/* data section address */
- + 	uint32_t bss_addr;			/* bss section address */
- + }ctexdbg_modsyms;
- + 
- + /* debug process information */
- + typedef struct __tag_ctexdbg_debugproc
- + {
- + 	uint32_t pid;					/* process pid */
- + 	uint32_t migration;				/* migrationcheck flag */
- + }ctexdbg_debugproc;
- + 
- + 
- + /* global */
- + extern ctexdbg_fix ctexdbg_fixdata; /* kctexdbgd control data */
- + extern uint32_t ctexdbg_EventBufSize;
- + extern uint32_t ctexdbg_EventUse;
- + extern uint32_t ctexdbg_enabled;
- + extern uint32_t ctexdbg_hardware_trace_enabled;
- + 
- + /* pidchange data */
- + extern uint32_t ctexdbg_prevpid;
- + extern uint32_t ctexdbg_nextpid;
- + 
- + /* arch depend */
- + extern void ctexdbg_event_core(void);
- + extern void ctexdbg_arch_userregaddr(void);
- + extern int ctexdbg_arch_checkice(void);
- + extern void ctexdbg_print_context_reg(struct pt_regs *regs);
- + extern int ctexdbg_arch_init(void);
- + extern unsigned long ctexdbg_arch_lock_kernel(void);
- + extern void ctexdbg_arch_unlock_kernel(unsigned long oldval);
- + 
- + extern void ctexdbg_add_memmap(unsigned long virt,unsigned long phys,unsigned long length);
- + 
- + extern void ctexdbg_filemap(struct vm_area_struct * vma);
- + extern ctexdbg_debugproc* ctexdbg_find_debugpid(uint32_t pid);
- + extern int ctexdbg_find_file(char *fname,char* finder,int findersize);
- + extern int ctexdbg_find_file_xip(char *fname,char* finder,int findersize);
- + extern int ctexdbg_varid_dname(struct mm_struct *mm);
- + 
- + 
- + /* module event */
- + extern int ctexdbg_module_init(struct module *mod);
- + extern int ctexdbg_module_install(struct module *mod,void *ehdrs,void *sechdrs,const char* secstrings,uint32_t symindex,uint32_t strindex);
- + extern int ctexdbg_module_remove(struct module *mod);
- + 
- + /* Library injection */
- + //char **ctexdbg_get_subenvp(int *envc,char *filename);
- + int ctexdbg_get_subenvp(char *filename, void *bprm);
- + 
- + /* event notify */
- + void ctexdbg_external_notify(size_t size,void *ptr);
- + void ctexdbg_eventfull_bp(void);
- + void ctexdbg_event_init(void);
- + extern int ctexdbg_event_set_buffer_size(int pmSize);
- + 
- + /* LTT tracer hook */
- + #if defined(CONFIG_CTEX_TRACE)
- + extern void ctexdbg_tracer(uint8_t pmEventID,void* pmEventStruct);
- + extern int  ctexdbg_tracer_start(uint32_t nbuffersize,uint32_t oneshot);
- + extern void ctexdbg_tracer_stop(void);
- + extern void ctexdbg_tracer_init(void);
- + #else
- + #define ctexdbg_tracer(a,b)
- + #define ctexdbg_tracer_start(a,b)
- + #define ctexdbg_tracer_stop()
- + #define ctexdbg_tracer_init()
- + #endif /* defined(CONFIG_CTEX_TRACE) */
- + 
- + extern void ctexdbg_lttfull_bp(void);
- + 
- + /* LTT data */
- + extern int ctexdbg_traceuse; 		/* LTT trace enable */
- + 
- + /* prototype */
- + extern int ctexdbg_forcebreak(struct task_struct *tsk);
- + extern int ctexdbg_checkwakeup(void);
- + extern void ctexdbg_do_no_page(struct vm_area_struct * vma,unsigned long address);
- + 
- + extern int ctexdbg_forking(struct task_struct *tsk,unsigned long clone_flags,unsigned long stack_start);
- + extern int ctexdbg_signals(uint32_t signa,uint32_t pid,struct pt_regs *regs);
- + extern int ctexdbg_main_pre_brk(struct task_struct *tsk,unsigned long entryaddr,unsigned long ppgd);
- + 
- + /* ------------------------ events -------------------------------------*/
- + extern void ctexdbg_process_exit(void);
- + extern void ctexdbg_file_event(struct task_struct *tsk,struct file *file,uint32_t pgd);
- + extern void ctexdbg_migration_check(struct task_struct *tsk ,int src_cpu,int dest_cpu);
- + 
- + /* debug print macro */
- + #define ctexdbg_prn(who, format, arg...)		\
- + do{							\
- + 	if(ctexdbg_ddebugevent == 1)			\
- + 		printk("%s: "format,who, ## arg);	\
- + }while(0)
- + 
- + #endif /* CONFIG_CTEX_DBGLIB */
- + 
- + #include <linux/ctextrc.h>
- + 
- + #endif /* _LINUX_CTEXDBG_H */
- diff -crN linux-3.2.1_o/include/linux/ctextrc.h linux-3.2.1_ctex/include/linux/ctextrc.h
- *** linux-3.2.1_o/include/linux/ctextrc.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1_ctex/include/linux/ctextrc.h	2013-05-24 10:28:33.494834631 +0900
- ***************
- *** 0 ****
- --- 1,355 ----
- + /*
- +  * linux/include/linux/ctextrc.h
- +  *
- +  * (C) Copyright 2006 - Computex co.,ltd.
- +  *
- +  * Computex dbglib support ltt-ng
- +  *  LTT-ng to ctextrc style transfer
- +  * -- version info --------------------------------------------------
- +  *
- +  * version 0014 - 2008/05/xx	reborn
- +  *
- +  * -------------------------------------------------------------------
- +  *
- +  */
- + 
- + #ifndef _LINUX_CTEXTRC_H_
- + #define _LINUX_CTEXTRC_H_
- + 
- + #include <linux/types.h>
- + 
- + /* Is defined me ? */
- + #if defined(CONFIG_CTEX_TRACE)
- + 
- + #define CTX_PACKED_STRUCT __attribute__ ((packed))
- + 
- + /* Traced events */
- + enum {
- + 	CTX_EV_START = 0,	/* This is to mark the trace's start */
- + 	CTX_EV_SYSCALL_ENTRY,	/* Entry in a given system call */
- + 	CTX_EV_SYSCALL_EXIT,	/* Exit from a given system call */
- + 	CTX_EV_TRAP_ENTRY,	/* Entry in a trap */
- + 	CTX_EV_TRAP_EXIT,	/* Exit from a trap */
- + 	CTX_EV_IRQ_ENTRY,	/* Entry in an irq */
- + 	CTX_EV_IRQ_EXIT,	/* Exit from an irq */
- + 	CTX_EV_SCHEDCHANGE,	/* Scheduling change */
- + 	CTX_EV_KERNEL_TIMER,	/* The kernel timer routine has been called */
- + 	CTX_EV_SOFT_IRQ,	/* Hit key part of soft-irq management */
- + 	CTX_EV_PROCESS,		/* Hit key part of process management */
- + 	CTX_EV_FILE_SYSTEM,	/* Hit key part of file system */
- + 	CTX_EV_TIMER,		/* Hit key part of timer management */
- + 	CTX_EV_MEMORY,		/* Hit key part of memory management */
- + 	CTX_EV_SOCKET,		/* Hit key part of socket communication */
- + 	CTX_EV_IPC,		/* Hit key part of System V IPC */
- + 	CTX_EV_NETWORK,		/* Hit key part of network communication */
- + 	CTX_EV_BUFFER_START,	/* Mark the begining of a trace buffer */
- + 	CTX_EV_BUFFER_END,	/* Mark the ending of a trace buffer */
- + };
- + 
- + /* Number of traced events */
- + #define CTX_EV_MAX		CTX_EV_BUFFER_END
- + 
- + /*  LTT_SYSCALL_ENTRY */
- + typedef struct _ctx_syscall_entry {
- + 	u16   syscall_id;		/* Syscall entry number in entry.S */
- + 	ulong address;		/* Address from which call was made */
- + } CTX_PACKED_STRUCT ctx_syscall_entry;
- + #define ctx_ev_syscall_entry(ID,DATA) \
- + do{ \
- + 	if(ctexdbg_traceuse != 0){ \
- + 		ctx_syscall_entry si; \
- + 		si.syscall_id = (u16)ID; \
- + 		si.address = (ulong)DATA; \
- + 		ctexdbg_tracer((uint8_t)CTX_EV_SYSCALL_ENTRY, (void*)&si); \
- + } \
- + }while(0);
- + 
- + #define ctx_ev_syscall_exit()\
- + do{ \
- + 	ctexdbg_tracer((uint8_t)CTX_EV_SYSCALL_EXIT, NULL); \
- + }while(0);
- + 
- + 
- + /*  LTT_TRAP_ENTRY */
- + typedef struct _ctx_trap_entry {
- + 	u16   trap_id;		/* Trap number */
- + 	ulong address;		/* Address where trap occured */
- + } CTX_PACKED_STRUCT ctx_trap_entry;
- + #define ctx_ev_trap_entry(ID,DATA) \
- + do{ \
- + 	if(ctexdbg_traceuse != 0){ \
- + 		ctx_trap_entry trap_event; \
- + 		trap_event.trap_id = ID; \
- + 		trap_event.address = DATA; \
- + 		ctexdbg_tracer((uint8_t)CTX_EV_TRAP_ENTRY, (void*)&trap_event); \
- + 	}\
- + }while(0);
- + 
- + /*  LTT_TRAP_EXIT */
- + #define ctx_ev_trap_exit() \
- + do{ \
- + 	if(ctexdbg_traceuse != 0){ \
- + 		ctexdbg_tracer((uint8_t)CTX_EV_TRAP_EXIT, NULL); \
- + 	} \
- + }while(0);
- + 
- + /*  LTT_IRQ_ENTRY */
- + typedef struct _ctx_irq_entry {
- + 	u16 irq_id;		/* IRQ number */
- + 	u8  kernel;		/* Are we executing kernel code */
- + } CTX_PACKED_STRUCT ctx_irq_entry;
- + #define ctx_ev_irq_entry(ID,DATA) \
- + do{ \
- + 	if(ctexdbg_traceuse != 0){ \
- + 		ctx_irq_entry irq_entry; \
- + 		irq_entry.irq_id = ID; \
- + 		irq_entry.kernel = DATA; \
- + 		ctexdbg_tracer((uint8_t)CTX_EV_IRQ_ENTRY, (void*)&irq_entry); \
- + 	} \
- + }while(0);
- + 
- + /*  LTT_IRQ_EXIT */
- + #define ctx_ev_irq_exit() \
- + do{ \
- + 	if(ctexdbg_traceuse != 0){ \
- + 		ctexdbg_tracer((uint8_t)CTX_EV_IRQ_EXIT, NULL); \
- + 	} \
- + }while(0); 
- + 
- + /*  LTT_SCHEDCHANGE */
- + typedef struct _ctx_schedchange {
- + 	u32 out;		/* Outgoing process */
- + 	u32 in;			/* Incoming process */
- + 	u32 out_state;		/* Outgoing process' state */
- + } CTX_PACKED_STRUCT ctx_schedchange;
- + #define ctx_ev_schedchange(OUT,IN,DATA) \
- + do{ \
- + 	if(ctexdbg_traceuse != 0){ \
- + 		ctx_schedchange sched_event; \
- + 		sched_event.out = OUT; \
- + 		sched_event.in  = IN; \
- + 		sched_event.out_state = DATA; \
- + 		ctexdbg_tracer((uint8_t)CTX_EV_SCHEDCHANGE, (void*)&sched_event); \
- + 	} \
- + }while(0); 
- + 
- + /*  LTT_SOFT_IRQ */
- + enum {
- + 	CTX_EV_SOFT_IRQ_BOTTOM_HALF = 1,	/* Conventional bottom-half */
- + 	CTX_EV_SOFT_IRQ_SOFT_IRQ,		/* Real soft-irq */
- + 	CTX_EV_SOFT_IRQ_TASKLET_ACTION,		/* Tasklet action */
- + 	CTX_EV_SOFT_IRQ_TASKLET_HI_ACTION	/* Tasklet hi-action */
- + };
- + typedef struct _ctx_soft_irq {
- + 	u8    event_sub_id;	/* Soft-irq event Id */
- + 	ulong event_data;
- + } CTX_PACKED_STRUCT ctx_soft_irq;
- + #define ctx_ctx_ev_soft_irq(ID,DATA) \
- + do{ \
- + 	if(ctexdbg_traceuse != 0){ \
- + 		ctx_soft_irq soft_irq_event; \
- + 		soft_irq_event.event_sub_id = ID; \
- + 		soft_irq_event.event_data = DATA; \
- + 		ctexdbg_tracer((uint8_t)CTX_EV_SOFT_IRQ, (void*)&soft_irq_event); \
- + 	} \
- + }while(0); 
- + 
- + /*  LTT_PROCESS */
- + enum {
- + 	CTX_EV_PROCESS_KTHREAD = 1,	/* Creation of a kernel thread */
- + 	CTX_EV_PROCESS_FORK,		/* A fork or clone occured */
- + 	CTX_EV_PROCESS_EXIT,		/* An exit occured */
- + 	CTX_EV_PROCESS_WAIT,		/* A wait occured */
- + 	CTX_EV_PROCESS_SIGNAL,		/* A signal has been sent */
- + 	CTX_EV_PROCESS_WAKEUP		/* Wake up a process */
- + };
- + typedef struct _ctx_process {
- + 	u8    event_sub_id;	/* Process event ID */
- + 	u32   event_data1;
- + 	ulong event_data2;
- + } CTX_PACKED_STRUCT ctx_process;
- + #define ctx_ev_process(ID,DATA,DATA2) \
- + do{ \
- + 	if(ctexdbg_traceuse != 0){	\
- + 		ctx_process proc_event; \
- + 		proc_event.event_sub_id = ID; \
- + 		proc_event.event_data1 = DATA; \
- + 		proc_event.event_data2 = DATA2; \
- + 		ctexdbg_tracer((uint8_t)CTX_EV_PROCESS, (void*)&proc_event); \
- + 	} \
- + }while(0); 
- + 
- + #define ctx_ev_process_exit() \
- + do{ \
- + 	if(ctexdbg_traceuse != 0){	\
- + 		ctx_process proc_event;	\
- + 		proc_event.event_sub_id = CTX_EV_PROCESS_EXIT; \
- + 		ctexdbg_tracer((uint8_t)CTX_EV_PROCESS, (void*)&proc_event); \
- + 	} \
- + }while(0);
- + 
- + /*  LTT_FILE_SYSTEM */
- + enum {
- + 	CTX_EV_FILE_SYSTEM_BUF_WAIT_START = 1,	/* Starting to wait for a data buffer */
- + 	CTX_EV_FILE_SYSTEM_BUF_WAIT_END,	/* End to wait for a data buffer */
- + 	CTX_EV_FILE_SYSTEM_EXEC,		/* An exec occured */
- + 	CTX_EV_FILE_SYSTEM_OPEN,		/* An open occured */
- + 	CTX_EV_FILE_SYSTEM_CLOSE,		/* A close occured */
- + 	CTX_EV_FILE_SYSTEM_READ,		/* A read occured */
- + 	CTX_EV_FILE_SYSTEM_WRITE,		/* A write occured */
- + 	CTX_EV_FILE_SYSTEM_SEEK,		/* A seek occured */
- + 	CTX_EV_FILE_SYSTEM_IOCTL,		/* An ioctl occured */
- + 	CTX_EV_FILE_SYSTEM_SELECT,		/* A select occured */
- + 	CTX_EV_FILE_SYSTEM_POLL			/* A poll occured */
- + };
- + typedef struct _ctx_file_system {
- + 	u8 event_sub_id;	/* File system event ID */
- + 	u32 event_data1;
- + 	u32 event_data2;
- + 	char *file_name;	/* Name of file operated on */
- + } CTX_PACKED_STRUCT ctx_file_system;
- + #define ctx_ev_file_system(ID,DATA,DATA2,FNAME) \
- + do{ \
- + 	if(ctexdbg_traceuse != 0){	\
- + 		ctx_file_system fs_event; \
- + 		fs_event.event_sub_id = ID; \
- + 		fs_event.event_data1 = DATA; \
- + 		fs_event.event_data2 = DATA2; \
- + 		fs_event.file_name = (char*) FNAME; \
- + 		ctexdbg_tracer((uint8_t)CTX_EV_FILE_SYSTEM, (void*)&fs_event); \
- + 	} \
- + }while(0);
- + 
- + /*  LTT_TIMER */
- + enum {
- + 	CTX_EV_TIMER_EXPIRED = 1,	/* Timer expired */
- + 	CTX_EV_TIMER_SETITIMER,		/* Setting itimer occurred */
- + 	CTX_EV_TIMER_SETTIMEOUT		/* Setting sched timeout occurred */
- + };
- + typedef struct _ctx_timer {
- + 	u8 event_sub_id;	/* Timer event ID */
- + 	u8 event_sdata;		/* Short data */
- + 	ulong event_data1;
- + 	ulong event_data2;
- + } CTX_PACKED_STRUCT ctx_timer;
- + #define ctx_ev_timer(ID,SDATA,DATA,DATA2) \
- + do{ \
- + 	if(ctexdbg_traceuse != 0){ \
- + 		ctx_timer timer_event; \
- + 		timer_event.event_sub_id = ID; \
- + 		timer_event.event_sdata = SDATA; \
- + 		timer_event.event_data1 = DATA; \
- + 		timer_event.event_data2 = DATA2; \
- + 		ctexdbg_tracer((uint8_t)CTX_EV_TIMER, (void*)&timer_event); \
- + 	} \
- + }while(0);
- + 
- + /*  LTT_MEMORY */
- + enum {
- + 	CTX_EV_MEMORY_PAGE_ALLOC = 1,	/* Allocating pages */
- + 	CTX_EV_MEMORY_PAGE_FREE,	/* Freing pages */
- + 	CTX_EV_MEMORY_SWAP_IN,		/* Swaping pages in */
- + 	CTX_EV_MEMORY_SWAP_OUT,		/* Swaping pages out */
- + 	CTX_EV_MEMORY_PAGE_WAIT_START,	/* Start to wait for page */
- + 	CTX_EV_MEMORY_PAGE_WAIT_END	/* End to wait for page */
- + };
- + typedef struct _ctx_memory {
- + 	u8 event_sub_id;	/* Memory event ID */
- + 	ulong event_data;
- + } CTX_PACKED_STRUCT ctx_memory;
- + #define ctx_ev_memory(ID,DATA) \
- + do{ \
- + 	if(ctexdbg_traceuse != 0){	\
- + 		ctx_memory memory_event; \
- + 		memory_event.event_sub_id = ID; \
- + 		memory_event.event_data = DATA; \
- + 		ctexdbg_tracer((uint8_t)CTX_EV_MEMORY, (void*)&memory_event); \
- + 	} \
- + }while(0);
- + 
- + /*  LTT_SOCKET */
- + enum {
- + 	CTX_EV_SOCKET_CALL = 1,	/* A socket call occured */
- + 	CTX_EV_SOCKET_CREATE,	/* A socket has been created */
- + 	CTX_EV_SOCKET_SEND,	/* Data was sent to a socket */
- + 	CTX_EV_SOCKET_RECEIVE	/* Data was read from a socket */
- + };
- + typedef struct _ctx_socket {
- + 	u8 event_sub_id;	/* Socket event ID */
- + 	u32 event_data1;
- + 	ulong  event_data2;
- + } CTX_PACKED_STRUCT ctx_socket;
- + #define ctx_ev_socket(ID,DATA,DATA2) \
- + do{ \
- + 	if(ctexdbg_traceuse != 0){ \
- + 		ctx_socket socket_event; \
- + 		socket_event.event_sub_id = ID; \
- + 		socket_event.event_data1 = DATA; \
- + 		socket_event.event_data2 = DATA2; \
- + 		ctexdbg_tracer((uint8_t)CTX_EV_SOCKET, (void*)&socket_event); \
- + 	} \
- + }while(0);
- + 
- + /*  LTT_IPC */
- + enum {
- + 	CTX_EV_IPC_CALL = 1,	/* A System V IPC call occured */
- + 	CTX_EV_IPC_MSG_CREATE,	/* A message queue has been created */
- + 	CTX_EV_IPC_SEM_CREATE,	/* A semaphore was created */
- + 	CTX_EV_IPC_SHM_CREATE	/* A shared memory segment has been created */
- + };
- + typedef struct _ctx_ipc {
- + 	u8 event_sub_id;	/* IPC event ID */
- + 	u32 event_data1;
- + 	u32 event_data2;
- + } CTX_PACKED_STRUCT ctx_ipc;
- + #define ctx_ev_ipc(ID,DATA,DATA2) \
- + do{ \
- + 	if(ctexdbg_traceuse != 0){	\
- + 		ctx_ipc ipc_event; \
- + 		ipc_event.event_sub_id = ID; \
- + 		ipc_event.event_data1 = DATA; \
- + 		ipc_event.event_data2 = DATA2; \
- + 		ctexdbg_tracer((uint8_t)CTX_EV_IPC, (void*)&ipc_event); \
- + 	} \
- + }while(0);
- + 
- + /*  LTT_NETWORK */
- + enum {
- + 	CTX_EV_NETWORK_PACKET_IN = 1,	/* A packet came in */
- + 	CTX_EV_NETWORK_PACKET_OUT	/* A packet was sent */
- + };
- + typedef struct _ctx_network {
- + 	u8 event_sub_id;	/* Network event ID */
- + 	u32 event_data;
- + } CTX_PACKED_STRUCT ctx_network;
- + #define ctx_ev_network(ID,DATA) \
- + do{ \
- + 	if(ctexdbg_traceuse != 0){ \
- + 		ctx_network net_event; \
- + 		net_event.event_sub_id = ID; \
- + 		net_event.event_data = DATA; \
- + 		ctexdbg_tracer((uint8_t)CTX_EV_NETWORK, (void*)&net_event); \
- + 	} \
- + }while(0);
- + 
- + #else /* defined(CONFIG_CTEX_TRACE) */
- + 
- + #define ctx_ev_syscall_entry(ID,DATA)
- + #define ctx_ev_syscall_exit()
- + #define ctx_ev_trap_entry(ID, EIP)
- + #define ctx_ev_trap_exit()
- + #define ctx_ev_irq_entry(ID, KERNEL)
- + #define ctx_ev_irq_exit()
- + #define ctx_ev_schedchange(OUT, IN, DATA)
- + #define ctx_ev_soft_irq(ID, DATA)
- + #define ctx_ev_process(ID, DATA1, DATA2)
- + #define ctx_ev_process_exit()
- + #define ctx_ev_file_system(ID, DATA1, DATA2, FILE_NAME)
- + #define ctx_ev_timer(ID, SDATA, DATA1, DATA2)
- + #define ctx_ev_memory(ID, DATA)
- + #define ctx_ev_socket(ID, DATA1, DATA2)
- + #define ctx_ev_ipc(ID, DATA1, DATA2)
- + #define ctx_ev_network(ID, DATA)
- + #endif /* defined(CONFIG_CTEX_TRACE) */
- + 
- + #endif /* _LINUX_CTEXTRC_H_ */
- diff -crN linux-3.2.1_o/include/linux/init.h linux-3.2.1_ctex/include/linux/init.h
- *** linux-3.2.1_o/include/linux/init.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1_ctex/include/linux/init.h	2013-05-24 10:28:33.507336860 +0900
- ***************
- *** 40,46 ****
- --- 40,50 ----
-   
-   /* These are for everybody (although not all archs will actually
-      discard it in modules) */
- + #if defined (MODULE) && defined(CONFIG_CTEX_DBGLIB_MOD_NOINITEXIT)
- + #define __init
- + #else
-   #define __init		__section(.init.text) __cold notrace
- + #endif
-   #define __initdata	__section(.init.data)
-   #define __initconst	__section(.init.rodata)
-   #define __exitdata	__section(.exit.data)
- ***************
- *** 79,86 ****
-   #define __exitused  __used
-   #endif
-   
-   #define __exit          __section(.exit.text) __exitused __cold notrace
- ! 
-   /* Used for HOTPLUG */
-   #define __devinit        __section(.devinit.text) __cold notrace
-   #define __devinitdata    __section(.devinit.data)
- --- 83,93 ----
-   #define __exitused  __used
-   #endif
-   
- + #if defined (MODULE) && defined(CONFIG_CTEX_DBGLIB_MOD_NOINITEXIT)
- + #define __exit
- + #else
-   #define __exit          __section(.exit.text) __exitused __cold notrace
- ! #endif
-   /* Used for HOTPLUG */
-   #define __devinit        __section(.devinit.text) __cold notrace
-   #define __devinitdata    __section(.devinit.data)
- diff -crN linux-3.2.1_o/ipc/msg.c linux-3.2.1_ctex/ipc/msg.c
- *** linux-3.2.1_o/ipc/msg.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1_ctex/ipc/msg.c	2013-05-24 10:36:26.866652000 +0900
- ***************
- *** 37,42 ****
- --- 37,43 ----
-   #include <linux/rwsem.h>
-   #include <linux/nsproxy.h>
-   #include <linux/ipc_namespace.h>
- +  #include <linux/ctexdbg.h>
-   
-   #include <asm/current.h>
-   #include <asm/uaccess.h>
- ***************
- *** 314,320 ****
-   	struct ipc_namespace *ns;
-   	struct ipc_ops msg_ops;
-   	struct ipc_params msg_params;
- ! 
-   	ns = current->nsproxy->ipc_ns;
-   
-   	msg_ops.getnew = newque;
- --- 315,323 ----
-   	struct ipc_namespace *ns;
-   	struct ipc_ops msg_ops;
-   	struct ipc_params msg_params;
- ! #ifdef CONFIG_CTEX_TRACE
- ! 	int ret = -EPERM;
- ! #endif
-   	ns = current->nsproxy->ipc_ns;
-   
-   	msg_ops.getnew = newque;
- ***************
- *** 323,330 ****
-   
-   	msg_params.key = key;
-   	msg_params.flg = msgflg;
- ! 
-   	return ipcget(ns, &msg_ids(ns), &msg_ops, &msg_params);
-   }
-   
-   static inline unsigned long
- --- 326,338 ----
-   
-   	msg_params.key = key;
-   	msg_params.flg = msgflg;
- ! #ifdef CONFIG_CTEX_TRACE
- ! 	ret = ipcget(ns, &msg_ids(ns), &msg_ops, &msg_params);
- ! 	ctx_ev_ipc(CTX_EV_IPC_MSG_CREATE,ret,msgflg);
- ! 	return ret;
- ! #else
-   	return ipcget(ns, &msg_ids(ns), &msg_ops, &msg_params);
- + #endif
-   }
-   
-   static inline unsigned long
- diff -crN linux-3.2.1_o/ipc/sem.c linux-3.2.1_ctex/ipc/sem.c
- *** linux-3.2.1_o/ipc/sem.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1_ctex/ipc/sem.c	2013-05-24 10:28:33.862380679 +0900
- ***************
- *** 86,91 ****
- --- 86,92 ----
-   #include <linux/rwsem.h>
-   #include <linux/nsproxy.h>
-   #include <linux/ipc_namespace.h>
- + #include <linux/ctexdbg.h>
-   
-   #include <asm/uaccess.h>
-   #include "util.h"
- ***************
- *** 369,375 ****
-   	struct ipc_namespace *ns;
-   	struct ipc_ops sem_ops;
-   	struct ipc_params sem_params;
- ! 
-   	ns = current->nsproxy->ipc_ns;
-   
-   	if (nsems < 0 || nsems > ns->sc_semmsl)
- --- 370,378 ----
-   	struct ipc_namespace *ns;
-   	struct ipc_ops sem_ops;
-   	struct ipc_params sem_params;
- ! #ifdef CONFIG_CTEX_TRACE
- ! 	int err = -EINVAL;
- ! #endif
-   	ns = current->nsproxy->ipc_ns;
-   
-   	if (nsems < 0 || nsems > ns->sc_semmsl)
- ***************
- *** 383,389 ****
- --- 386,398 ----
-   	sem_params.flg = semflg;
-   	sem_params.u.nsems = nsems;
-   
- + #ifdef CONFIG_CTEX_TRACE
- + 	err = ipcget(ns, &sem_ids(ns), &sem_ops, &sem_params);
- + 	ctx_ev_ipc(CTX_EV_IPC_SEM_CREATE,err,semflg);
- + 	return err;
- + #else
-   	return ipcget(ns, &sem_ids(ns), &sem_ops, &sem_params);
- + #endif
-   }
-   
-   /*
- diff -crN linux-3.2.1_o/ipc/shm.c linux-3.2.1_ctex/ipc/shm.c
- *** linux-3.2.1_o/ipc/shm.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1_ctex/ipc/shm.c	2013-05-24 10:28:33.894307682 +0900
- ***************
- *** 39,44 ****
- --- 39,45 ----
-   #include <linux/nsproxy.h>
-   #include <linux/mount.h>
-   #include <linux/ipc_namespace.h>
- + #include <linux/ctexdbg.h>
-   
-   #include <asm/uaccess.h>
-   
- ***************
- *** 564,570 ****
-   	struct ipc_namespace *ns;
-   	struct ipc_ops shm_ops;
-   	struct ipc_params shm_params;
- ! 
-   	ns = current->nsproxy->ipc_ns;
-   
-   	shm_ops.getnew = newseg;
- --- 565,573 ----
-   	struct ipc_namespace *ns;
-   	struct ipc_ops shm_ops;
-   	struct ipc_params shm_params;
- ! #ifdef CONFIG_CTEX_TRACE
- ! 	int err = -EINVAL;
- ! #endif
-   	ns = current->nsproxy->ipc_ns;
-   
-   	shm_ops.getnew = newseg;
- ***************
- *** 575,581 ****
- --- 578,590 ----
-   	shm_params.flg = shmflg;
-   	shm_params.u.size = size;
-   
- + #ifdef CONFIG_CTEX_TRACE
- + 	err = ipcget(ns, &shm_ids(ns), &shm_ops, &shm_params);
- + 	ctx_ev_ipc(CTX_EV_IPC_SHM_CREATE,err,shmflg);
- + 	return err;
- + #else
-   	return ipcget(ns, &shm_ids(ns), &shm_ops, &shm_params);
- + #endif
-   }
-   
-   static inline unsigned long copy_shmid_to_user(void __user *buf, struct shmid64_ds *in, int version)
- diff -crN linux-3.2.1_o/ipc/syscall.c linux-3.2.1_ctex/ipc/syscall.c
- *** linux-3.2.1_o/ipc/syscall.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1_ctex/ipc/syscall.c	2013-05-24 10:35:33.400594000 +0900
- ***************
- *** 20,26 ****
-   
-   	version = call >> 16; /* hack for backward compatibility */
-   	call &= 0xffff;
- ! 
-   	switch (call) {
-   	case SEMOP:
-   		return sys_semtimedop(first, (struct sembuf __user *)ptr,
- --- 20,26 ----
-   
-   	version = call >> 16; /* hack for backward compatibility */
-   	call &= 0xffff;
- ! 	
-   	switch (call) {
-   	case SEMOP:
-   		return sys_semtimedop(first, (struct sembuf __user *)ptr,
- diff -crN linux-3.2.1_o/kernel/ctexdbg.c linux-3.2.1_ctex/kernel/ctexdbg.c
- *** linux-3.2.1_o/kernel/ctexdbg.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1_ctex/kernel/ctexdbg.c	2013-05-24 10:34:39.724523000 +0900
- ***************
- *** 0 ****
- --- 1,1560 ----
- + /*
- +  * linux/kernel/ctexdbg.c
- +  *
- +  * (C) Copyright 2004 - Computex co.,ltd.
- +  *
- +  * Computex dbglib support kernel thread (debug mon)
- +  *
- +  * -- version info --------------------------------------------------
- +  *
- +  * version 014_6 - 2009/09/04	 update patch version
- +  *                               + support Linux 2.6.29
- +  *                               + support Androld
- +  *
- +  * version 014_5 - 2009/07/14	 update patch version
- +  *                               + support Linux 2.6.27
- +  *
- +  * version 014_2 - 2008/12/08	 update patch version
- +  *                               + change ctexdbgd realtime kernel-thread
- +  * 
- +  * version 014   - 2008/07/18	 update patch version
- +  *                               + change process trace
- +  *                               + cleanup code
- +  *                               + support Linux 2.6.22.1
- +  *
- +  * version 013   - 2008/04/10	 update patch version
- +  *                               + fix loadable module install
- +  *
- +  * version 012   - 2007/07/26	 update patch version
- +  *                               + add selective user-mode fake xip (cramfs)
- +  *				 + support Linux 2.6.21
- +  *
- +  * version 011   - 2007/06/30	update patch version
- +  *								 + support SMP Kern
- +  *                               + add file operation buffer
- +  *                               + add monitor buffer
- +  *                               + fix: sleep_on -> wait_event
- +  *
- +  * version 009_6 - 2007/01/17	update patch version
- +  *								 + addandfix: ctexdbg_do_check_page
- +  *								 + support Linux 2.6.14 and 16 
- +  *
- +  * version 009_5 - 2007/01/13	update patch version
- +  * 								 + support user-mode fake XIP (cramfs)
- +  * 								 + fix: strict findfile
- +  * 								 + fix: a lot of warning
- +  *
- +  * version 009 - 2006/04/xx		update patch version
- +  * 								 + support PALMiCE 2H mode
- +  *                                 + add ctexdbg_hardware_trace_enabled
- +  *                                 + change ctexdbg_schedchange_event 
- +  *
- +  * version 008 - 2005/12/xx		update patch version
- +  * 								 + support file rename chmod chown
- +  *								 + add ctexdbg_premain_debug
- +  *								 + add CTEXDBG_EV_PREMAIN event 
- +  *								 + suopprt Linux 2.6.10 (mvl4.0 style)
- +  *
- +  * version 007 - 2005/11/xx		update patch version
- +  * 								 + remove fork_s
- +  * 								 + unuse pexit_no_chk
- +  *								 + change arg ctexdbg_event()
- +  *									(by fork event)
- +  *								 + add ctexdbg_noattach_debug
- +  *								 + change ctexdbg_filemap
- +  *
- +  * version 006 - 2005/08/xx		update patch version
- +  *								 + change ctexdbg_event
- +  *								 + Add process exit throw mode
- +  *								 + Add check load module debug file list
- +  *								 + change ctextrc
- +  *								 + change debug process size 128->512
- +  *								 + change ctexdbg_do_no_page args (addr->vma)
- +  *								 + remove unuse event
- +  *
- +  * version 005 - 2005/02/23		first release version
- +  *								 + Add version 
- +  *								 + CONFIG_TRACE_MODULE option support
- +  *								  + Move LTT buffer init code ctexdbg.c
- +  *								 + modified arch/xxx/kernel/signal.c
- +  *								 + add debug process file mode
- +  *
- +  * version 004 - 2005/02/1x		pre version
- +  *
- +  * -------------------------------------------------------------------
- +  */
- + #include <linux/kernel.h>
- + #include <linux/init.h>     /* For __init */
- + #include <linux/proc_fs.h>
- + #include <linux/unistd.h>
- + #include <linux/version.h>
- + 
- + #include <linux/ctexdbg.h>  /* definitions */
- + #include <linux/errno.h>    /* Miscellaneous error codes */
- + #include <linux/module.h>   /* EXPORT_SYMBOL */
- + #include <linux/mm.h>
- + #include <linux/sched.h>
- + #include <linux/completion.h>
- + #include <linux/file.h>
- + 
- + #include <linux/pagemap.h>
- + #include <linux/cpu.h>
- + 
- + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) 
- + #include <linux/locks.h>
- + #endif 
- + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) 
- + #include <linux/devfs_fs_kernel.h>
- + #endif 
- + #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,20)
- + #include <linux/freezer.h>
- + #endif
- + 
- + /* ---- global data */
- + 
- + /* wait queue */
- + DECLARE_WAIT_QUEUE_HEAD(kctexdbgd_wait);
- + DECLARE_WAIT_QUEUE_HEAD(kctexdbgd_process_wait);
- + DECLARE_WAIT_QUEUE_HEAD(kctexdbgd_force_wait);
- + DECLARE_WAIT_QUEUE_HEAD(kctexdbgd_signal_wait);
- + DECLARE_WAIT_QUEUE_HEAD(kctexdbgd_exit_wait);
- + 
- + /* lock */
- + spinlock_t ctexdbg_kernel_spinlock;				/* kernel spinlock */
- + spinlock_t ctexdbg_continue_spinlock;
- + 
- + /* sMP */
- + uint32_t ctexdbg_daemon_cpuid = 0;				/* daemon cpuid */
- + uint32_t ctexdbg_nrcpus;						/* max cpus */
- + 
- + 
- + /* ctexdbg_contdata ctexdbg_data; */	 		/* kctexdbgd control data */
- + ctexdbg_fix ctexdbg_fixdata; 			/* kctexdbgd init fix data */
- + 
- + /* pid changing data */
- + uint32_t ctexdbg_prevpid;
- + uint32_t ctexdbg_nextpid;
- + 
- + /*
- +    com buffer formats: 
- +    byte: 
- +     0       : wakeup flag (0:sleep   nonZero: wakeup
- + 	1       : function ID  (see CTEXDBG_ICEFunction)
- + 	2       : reserved (now unuse)
- + 	3       : end of data flag (0 is end ; 1 is continue)
- + 	4-511  : data...
- + */
- + unsigned char ctexdbg_combuf[512];		/* communication buffer */
- + unsigned char ctexdbg_workbuf[CTEXDBG_WORKBUF_SIZE+1];			/* working buffer */
- + unsigned char ctexdbg_filebuf[CTEXDBG_WORKBUF_SIZE+1];			/* file op working buffer (1kb) */
- + 
- + unsigned char *ctexdbg_evdata;				/* event data */
- + 
- + /* ICE ack flag */
- + unsigned char ctexdbg_ack = 0;					/* event ack */
- + unsigned char ctexdbg_lop = 0;					/* event in loop */
- + 
- + unsigned long ctexdbg_wakeuppid;
- + 
- + unsigned long ctexdbg_debugpidmax = 0;		/* Number of debug process */
- + int ctexdbg_traceuse = 0;					/* TRACE enable */
- + 
- + ctexdbg_checkarea ctexdbg_areatable[CTEXDBG_PGOFF_MAX];	/* area check table*/
- + uint32_t ctexdbg_breaksig[_NSIG+1];						/* handle catch signal */
- + //uint32_t ctexdbg_debugpid[CTEXDBG_PIDSIZE_MAX];			/* debug pid table */
- + ctexdbg_debugproc ctexdbg_debugpid[CTEXDBG_PIDSIZE_MAX];
- + uint32_t ctexdbg_forcebreaksig_pid;
- + uint32_t ctexdbg_tempcur;
- + uint32_t ctexdbg_enabled;			/* enable disable ctexdbg */
- + uint32_t ctexdbg_allbreak;			/* enable disable all breakmode */
- + uint32_t ctexdbg_pexitnochk;		/* enable disable outsize debug process exit check */
- + 											/* 0: disable (check all exec/exit process) */
- + 											/* 1: enable  (check debug only fork/exec/exit process) */
- + 
- + uint32_t ctexdbg_noclone_debug;	/* enable disable catch clone(pthread/thread)debug */									
- + 											/* 0: enable (clone() catch)*/
- + 											/* 1: disable (clone() not catch)*/
- + 									
- + uint32_t ctexdbg_noattach_debug;	/* enable disable attach process debug */									
- + 											/* 0: enable (all attach:default) */
- + 											/* 1: disable (do not attach) */
- + 									
- + uint32_t ctexdbg_premain_debug;	/* enable disable before main() debug */									
- + 											/* 0: disable (dont stop:default) */
- + 											/* 1: enable (stop) */
- + 
- + 																		
- + uint32_t ctexdbg_mapcount=0;		/* mapping counter */									
- + 
- + uint32_t ctexdbg_xipinram;		/* CRAMFS Xip apps RAM mode */
- + 
- + uint32_t ctexdbg_hardware_trace_enabled;	/* [v9]setting for hardware trace by ice */
- + 
- + char*  ctexdbg_envpdata[10];		/* special envp */
- + char   ctexdbg_envpstr[100];
- + char   ctexdbg_preloadlib[100];
- + 
- + char   ctexdbg_dbgfile[CTEXDBG_DBG_FNAMESIZE];	/* debug file list */
- + 
- + ctexdbg_mmap	ctexdbg_mmapdata[CTEXDBG_MMAPDATA_SIZE];	/* VP map data */
- + 
- + ctexdbg_modsyms ctexdbg_moddata[CTEXDBG_MODULE_MAX];	/* module table */
- + 
- + /* LTT */
- + cdbtrc_bufpos	ctexdbg_tracebufpos;				/* buffer position */
- + 
- + /* Debug symbol */
- + uint32_t ctexdbg_ddebugevent = 0;
- + uint32_t ctexdbg_ddebugrecv = 0;
- + 
- + #ifdef CONFIG_CTEX_DBGLIB_ANDROID
- + char ctexdbg_android = 0;				/* android flag */
- + #endif
- + 
- + /* Version info and check */
- + char ctexdbg_patchver_char[8];
- + 
- + /* proto-type */
- + void ctexdbg_signalbreak(uint32_t pid,uint32_t sig);
- + 
- + extern int ctexdbg_file_ls(char *path);
- + extern int ctexdbg_file_rmdir(char *path);
- + extern int ctexdbg_file_mkdir(char *path);
- + extern int ctexdbg_file_delfile(char *path);
- + extern int ctexdbg_file_read(char *path);
- + extern int ctexdbg_file_write(char *path);
- + extern int ctexdbg_file_rename(char *path);
- + extern int ctexdbg_file_chmod(char *path);
- + extern int ctexdbg_file_chown(char *path);
- + 
- + /* event handler */
- + void ctexdbg_event(struct task_struct *tasks,uint32_t eventno)
- + {
- + 	barrier();		/* compiler optmize barrier */
- + 	if(ctexdbg_enabled == 0) return;
- + 	/*
- + 	 * set process info
- + 	 * [eventno] [context] [PID] [...]
- + 	 */
- + 	ctexdbg_tempcur = (uint32_t)tasks;
- + 	memcpy(ctexdbg_workbuf,&eventno,sizeof(uint32_t));
- + 	memcpy(ctexdbg_workbuf + 4,&ctexdbg_tempcur,sizeof(uint32_t));
- + 	memcpy(ctexdbg_workbuf + 8,&(tasks->pid),sizeof(uint32_t));
- + 	ctexdbg_prn("ctexdbg","event# %08x context %08x PID %08x cpuid %08x\n",
- + 			(uint32_t)(*ctexdbg_workbuf),
- + 			(uint32_t)(*(ctexdbg_workbuf+4)),
- + 			(uint32_t)(*(ctexdbg_workbuf+8)),
- + 			(uint32_t)(smp_processor_id())
- + 	);
- + 	/* send ice and loop ack */
- + 	while(ctexdbg_ack == 0){
- + 		ctexdbg_lop = 1;
- + 		ctexdbg_event_core();
- + 	}
- + 	ctexdbg_ack = 0;
- + 	ctexdbg_lop = 0;
- + }
- + 
- + /* --------------- event bp ---------------------------------------------------- */
- + 
- + /* LTTbuffer full event */
- + void ctexdbg_lttfull_bp(void)
- + {
- + 	unsigned long clk_irq;
- + 	clk_irq = ctexdbg_arch_lock_kernel();
- + 	ctexdbg_event(current,CTEXDBG_EV_LTTFULL);
- + 	ctexdbg_arch_unlock_kernel(clk_irq);
- + 	return;
- + }
- + 
- + 
- + /* Eventbuffer full event */
- + void ctexdbg_eventfull_bp(void)
- + {
- + 	unsigned long clk_irq;
- + 	clk_irq = ctexdbg_arch_lock_kernel();
- + 	ctexdbg_event(current,CTEXDBG_EV_EVENTFULL);
- + 	ctexdbg_arch_unlock_kernel(clk_irq);	
- + 	return;
- + }
- + 
- + /* File LS buffer full event */
- + void ctexdbg_filelsfull_bp(void)
- + {
- + 	unsigned long clk_irq;
- + 	clk_irq = ctexdbg_arch_lock_kernel();
- + 	memcpy(ctexdbg_workbuf,ctexdbg_filebuf,CTEXDBG_WORKBUF_SIZE);	
- + 	ctexdbg_event(current,CTEXDBG_EV_FILE_LSFULL);
- + 	ctexdbg_arch_unlock_kernel(clk_irq);
- + 	return;
- + }
- + 
- + /* File read transfer event */
- + unsigned long ctexdbg_fileread_bp(void)
- + {
- + 	unsigned long clk_irq;
- + 	unsigned long stopflag;
- + 	clk_irq = ctexdbg_arch_lock_kernel();
- + 	memcpy(ctexdbg_workbuf,ctexdbg_filebuf,CTEXDBG_WORKBUF_SIZE);
- + 	ctexdbg_event(current,CTEXDBG_EV_FILE_READ);
- + 	memcpy(&stopflag,ctexdbg_workbuf,sizeof(unsigned long));
- + 	ctexdbg_arch_unlock_kernel(clk_irq);	
- + 	return stopflag;
- + }
- + 
- + /* File write transfer event */
- + unsigned long ctexdbg_filewrite_bp(void)
- + {
- + 	unsigned long clk_irq;
- + 	unsigned long stopflag;	
- + 	clk_irq = ctexdbg_arch_lock_kernel();
- + 	memcpy(ctexdbg_workbuf,ctexdbg_filebuf,CTEXDBG_WORKBUF_SIZE);
- + 	ctexdbg_event(current,CTEXDBG_EV_FILE_WRITE);
- + 	memcpy(&stopflag,ctexdbg_workbuf,sizeof(unsigned long));	
- + 	memcpy(ctexdbg_filebuf,ctexdbg_workbuf,CTEXDBG_WORKBUF_SIZE);	
- + 	ctexdbg_arch_unlock_kernel(clk_irq);
- + 	return stopflag;
- + }
- + 
- + /* File op end event */
- + void ctexdbg_fileend_bp(void)
- + {
- + 	unsigned long clk_irq;
- + 	clk_irq = ctexdbg_arch_lock_kernel();
- + 	memcpy(ctexdbg_workbuf,ctexdbg_filebuf,CTEXDBG_WORKBUF_SIZE);
- + 	ctexdbg_event(current,CTEXDBG_EV_FILE_END);
- + 	ctexdbg_arch_unlock_kernel(clk_irq);
- + 	return;
- + }
- + 
- + 
- + /* --------------- misc ---------------------------------------------------- */
- + 
- + /* Find any file in finder. ret=0 not found fname ret=1 found fname */
- + int ctexdbg_find_file(char *fname,char* finder,int findersize)
- + {
- + 	int i = 0;
- + 	int ldot = 0;
- + 	int flen = 0;
- + 	int slen = 0;
- + 	
- + 	char findname[NAME_MAX];
- + 	
- + 	if(fname == NULL) return 0;
- + 	strncpy(findname,fname,NAME_MAX);
- + 	slen = strlen(findname);
- + 	
- + 	/* find last dot */
- + 	for(ldot=slen-1;ldot >= 0;ldot--){
- + 		if(findname[ldot] == '.'){
- + 			findname[ldot] = '\0';
- + 			break;
- + 		}
- + 	}
- + 	slen = strlen(findname);
- + 	
- + 	/* fix :null is set default */
- + 	if(finder == NULL){
- + 		finder = (char *)ctexdbg_dbgfile;
- + 		findersize = CTEXDBG_DBG_FNAMESIZE;
- + 	}
- + 	
- + 	while(i < findersize){
- + 		if(finder[i] == '\0'){
- + 			break;
- + 		}
- + 		flen = strlen(&(finder[i]));
- + 		/* fix: filename equal finder strict compare */
- + 		if(slen == flen){
- + 			if(strnicmp(&(finder[i]),findname,slen) == 0){
- + 				return 1;
- + 			}
- + 		}
- + 		i += (flen+1);
- + 	}
- + 
- + 	return 0;
- + }
- + 
- + /* Find any file in finder(from CRAMFS-XIP code). ret=0 not found or not ram mode fname ret=1 found fname */
- + int ctexdbg_find_file_xip(char *fname,char* finder,int findersize)
- + {
- + 	if(ctexdbg_xipinram == 1) return 0;
- + 	return ctexdbg_find_file(fname,finder,findersize);
- + }
- + 
- + /* isvarid d_name.name */
- + int ctexdbg_varid_dname(struct mm_struct *mm)
- + {
- + 	if(mm == NULL) return 1;
- + 	if(mm->mmap == NULL) return 1;
- + 	if(mm->mmap->vm_file == NULL) return 1;
- + 	if(mm->mmap->vm_file->f_dentry == NULL) return 1;
- + 	return 0;
- + }
- + 
- + int ctexdbg_varid_vma(struct vm_area_struct * vma)
- + {
- + 	if(vma == NULL) return 1;
- + 	if(vma->vm_file == NULL) return 1;
- + 	if(vma->vm_file->f_dentry == NULL) return 1;
- + 	return 0;
- + }
- + 
- + /* Add debug process ID */
- + void ctexdbg_add_debugpid(uint32_t pid)
- + {
- + 	int i;
- + 	for(i=0; i < CTEXDBG_PIDSIZE_MAX ;i++){
- + 		if(ctexdbg_debugpid[i].pid == 0){
- + 			ctexdbg_debugpid[i].pid = pid;
- + 			ctexdbg_debugpid[i].migration = 0;
- + 			break;
- + 		}
- + 	}
- + }
- + 
- + /* Remove debug process ID */
- + void ctexdbg_remove_debugpid(uint32_t pid)
- + {
- + 	int i;
- + 	for(i=0; i < CTEXDBG_PIDSIZE_MAX ;i++){
- + 		if(ctexdbg_debugpid[i].pid == pid){
- + 			ctexdbg_debugpid[i].pid = 0;
- + 			ctexdbg_debugpid[i].migration = 0;
- + 			break;
- + 		}
- + 	}
- + }
- + 
- + /* Find debug process ID */
- + ctexdbg_debugproc* ctexdbg_find_debugpid(uint32_t pid)
- + {
- + 	int i;
- + 	for(i=0; i < CTEXDBG_PIDSIZE_MAX ;i++){
- + 		if(ctexdbg_debugpid[i].pid == pid){
- + 			return &(ctexdbg_debugpid[i]);
- + 		}
- + 	}
- + 	return NULL;
- + }
- + 
- + /* Debug dump console */
- + void do_ctexdump(void)
- + {
- + 	int i;
- + 	char *cb = ctexdbg_combuf;
- + 	
- + 	ctexdbg_prn("kctexdbg","Dump communitation buffer\n");
- + 	for(i=0;i<127;i+=16){
- + 		ctexdbg_prn("kctexdbg","%05X : %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
- + 				i,
- + 				cb[i],cb[i+1],cb[i+2],cb[i+3],cb[i+4],cb[i+5],cb[i+6],cb[i+7],cb[i+8],
- + 				cb[i+9],cb[i+10],cb[i+11],cb[i+12],cb[i+13],cb[i+14],cb[i+15]
- + 		);
- + 	}
- + 	ctexdbg_prn("kctexdbg","Dump end\n");
- + 	
- + }
- + 
- + /* sending signal */
- + void do_ctex_sendsig(unsigned long pid,unsigned long sigid)
- + {
- + 	struct task_struct *t;
- + #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,26)
- + 	t = find_task_by_pid_ns(pid, &init_pid_ns);
- + #else
- + 	t = find_task_by_pid(pid);
- + #endif	
- + 	if(t != NULL){
- + 		force_sig(sigid,t);
- + 	}
- + }
- + 
- + /* ----------------- kctexdbg sMP function ----------------------------------------- */
- + /* limit runnable cpuS forked process */
- + void ctexdbg_fork_limit_cpu_mask(struct task_struct *tsk)
- + {
- + 	cpumask_t c_mask;
- + 	cpus_clear(c_mask);
- + 	cpu_set(ctexdbg_daemon_cpuid,c_mask);
- + 	tsk->cpus_allowed = c_mask;
- + 	set_task_cpu(tsk, ctexdbg_daemon_cpuid);
- + }
- + 
- + /* limit runnable cpuS execed process */
- + void ctexdbg_exec_limit_cpu_mask(struct task_struct *tsk)
- + {
- + 	cpumask_t c_mask;
- + 	cpus_clear(c_mask);
- + 	cpu_set(ctexdbg_daemon_cpuid,c_mask);
- + 	set_cpus_allowed(tsk,c_mask);
- + }
- + 
- + /* unlimit runnable cpuS execed process */
- + void ctexdbg_exec_setall_cpu_mask(struct task_struct *tsk)
- + {
- + 	cpumask_t c_mask;
- + 	cpus_clear(c_mask);
- + 	cpus_setall(c_mask);
- + 	set_cpus_allowed(tsk,c_mask);
- + }
- + 
- + void ctexdbg_up_migration(ctexdbg_debugproc *findtask)
- + {
- + 	findtask->migration = 0;
- + }
- + 
- + /* migration check */
- + void ctexdbg_migration_check(struct task_struct *tsk ,int src_cpu,int dest_cpu)
- + {
- + 	char *p;
- + 	unsigned long clk_irq;
- + 	ctexdbg_debugproc *findtask;
- + 
- + 	if(ctexdbg_enabled == 0) return;
- + 
- + 	barrier();		/* compiler optmize barrier */
- + 	clk_irq = ctexdbg_arch_lock_kernel();
- + 
- + 	findtask = ctexdbg_find_debugpid(tsk->pid);
- + 	if (findtask == NULL) goto migration_check_exit;
- + 	if (findtask->migration == 0) goto migration_check_exit;
- + 
- + 	/* fmt:[tskaddr] [pid] [src_cpu] [dest_cpu] */
- + 	p = ctexdbg_evdata;
- + 	ctexdbg_tempcur = (uint32_t)tsk;
- + 	memcpy(p ,&ctexdbg_tempcur,sizeof(uint32_t));
- + 	p += sizeof(uint32_t);
- + 	memcpy(p,&tsk->pid,sizeof(uint32_t));
- + 	p += sizeof(uint32_t);
- + 	memcpy(p,&(src_cpu),sizeof(uint32_t));
- + 	p += sizeof(uint32_t);
- + 	memcpy(p,&(dest_cpu),sizeof(uint32_t));
- + 
- + 	ctexdbg_event(current,CTEXDBG_EV_MIGRATION);
- + 
- + 	ctexdbg_up_migration(findtask);
- + 
- + migration_check_exit:
- + 	ctexdbg_arch_unlock_kernel(clk_irq);	
- + 	return;
- + }
- + 
- + /* ----------------------------------------------------------------------------- */
- + /* adding PV mapping from arch */
- + void ctexdbg_add_memmap(unsigned long virt,unsigned long phys,unsigned long length)
- + {
- + 	ctexdbg_prn("ctexdbg","mapping v=0x%08lx p=0x%08lx len=0x%08lx\n",virt,phys,length);
- + 
- + 	if(CTEXDBG_MMAPDATA_SIZE <= (ctexdbg_mapcount + 1)) return;
- + 	
- + 	ctexdbg_mmapdata[ctexdbg_mapcount].virtaddr = virt;
- + 	ctexdbg_mmapdata[ctexdbg_mapcount].physaddr = phys;
- + 	ctexdbg_mmapdata[ctexdbg_mapcount].length = length;
- + 
- + 	ctexdbg_mmapdata[ctexdbg_mapcount+1].virtaddr = 0;
- + 	ctexdbg_mmapdata[ctexdbg_mapcount+1].physaddr = 0;
- + 	ctexdbg_mmapdata[ctexdbg_mapcount+1].length = 0;
- + 	ctexdbg_mapcount ++;
- + }
- + 
- + 
- + /* --------------- event ---------------------------------------------------- */
- + 
- + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) 
- + /* Find a module section: 0 means not found. */
- + static unsigned int ctexdbg_find_elf_section(Elf_Ehdr *hdr,Elf_Shdr *sechdrs,const char *secstrings,const char *name)
- + {
- + 	unsigned int i;
- + 	if(secstrings == NULL) return 0;
- + 	for (i = 1; i < hdr->e_shnum; i++){
- + 		if(sechdrs[i].sh_name == 0) continue;
- + 		if(strcmp(secstrings+sechdrs[i].sh_name, name) == 0) return i;
- + 	}
- + 	return 0;
- + }
- + static uint32_t ctexdbg_get_elf_addr(Elf_Ehdr *hdr,Elf_Shdr *sechdrs,const char *secstrings,const char *name)
- + {
- + 	unsigned int i;
- + 	i = ctexdbg_find_elf_section(hdr,sechdrs,secstrings,name);
- + 	if(i == 0) return 0;
- + 	return sechdrs[i].sh_addr;
- + }
- + 
- + #endif
- + 
- + /* module init helper (2.6 later) */
- + int ctexdbg_module_install(struct module *mod,void *ehdrs,void *sechdrs,const char* secstrings,uint32_t symindex,uint32_t strindex)
- + {
- + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) 
- + 	int i,n;
- +  	Elf_Shdr *elf_sechdrs = (Elf_Shdr *)sechdrs;
- + 	Elf_Ehdr *elf_edrs = (Elf_Ehdr *)ehdrs;
- + 
- + 	if(ctexdbg_ddebugevent == 1){
- + 		for (n = 1; n < elf_edrs->e_shnum; n++){
- + 			ctexdbg_prn("ctexdbg","elf info %d\n",n);
- + 			if(elf_sechdrs[n].sh_name != 0){
- + 				ctexdbg_prn("ctexdbg","name %-15s \n",secstrings+elf_sechdrs[n].sh_name);
- + 			}
- + 			ctexdbg_prn("ctexdbg","sadr %08X \n",elf_sechdrs[n].sh_addr);
- + 			ctexdbg_prn("ctexdbg","offs %08X \n",elf_sechdrs[n].sh_offset);
- + 			ctexdbg_prn("ctexdbg","type %08X \n",elf_sechdrs[n].sh_type);
- + 			ctexdbg_prn("ctexdbg","flag %08X \n",elf_sechdrs[n].sh_flags);
- + 		}
- + 	}
- + 
- + 	if(ctexdbg_enabled == 0) return 0;
- + 
- + 	for(i=0;i<CTEXDBG_MODULE_MAX;i++){
- + 		if(ctexdbg_moddata[i].mod == NULL) break;
- + 	}
- + 	if(i>=CTEXDBG_MODULE_MAX) i=0;
- + 	ctexdbg_moddata[i].mod = mod;
- + 	ctexdbg_moddata[i].start_addr = ctexdbg_get_elf_addr(elf_edrs,elf_sechdrs,secstrings,".text");
- + 	ctexdbg_moddata[i].rodata_addr = ctexdbg_get_elf_addr(elf_edrs,elf_sechdrs,secstrings,".rodata");
- + 	ctexdbg_moddata[i].data_addr = ctexdbg_get_elf_addr(elf_edrs,elf_sechdrs,secstrings,".data");
- + 	ctexdbg_moddata[i].bss_addr = ctexdbg_get_elf_addr(elf_edrs,elf_sechdrs,secstrings,".bss");
- + 
- + 	ctexdbg_moddata[i].symtab_addr = elf_sechdrs[symindex].sh_addr;
- + 	ctexdbg_moddata[i].numsym = elf_sechdrs[symindex].sh_size / sizeof(Elf_Sym);
- + 	ctexdbg_moddata[i].strtab_addr = elf_sechdrs[strindex].sh_addr;	
- + 
- + #endif /* Lver */
- + 	return 0;
- + }
- + 
- + int ctexdbg_module_remove(struct module *mod)
- + {
- + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
- + 	int i;
- + 	for(i=0;i<CTEXDBG_MODULE_MAX;i++){
- + 		if(ctexdbg_moddata[i].mod == mod){
- + 			ctexdbg_moddata[i].mod = NULL;
- + 			break;
- + 		}
- + 	}
- + #endif /* Lver */
- + 	return 0;
- + }
- + 
- + 
- + /* module init event (sys_init_module()) */
- + int ctexdbg_module_init(struct module *mod)
- + {
- + 	char *p;
- + 	uint32_t nlen;
- + 	uint32_t offset;
- + 	int i;
- + 	unsigned long clk_irq;
- + 	
- + 	if(ctexdbg_enabled == 0)
- + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26) 		
- + 		return 0;
- + #else
- + 		return mod->init();
- + #endif
- + 		
- + 	if(mod->name == NULL)
- + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26) 		
- + 		return 0;
- + #else
- + 		return mod->init();
- + #endif
- + 	
- + 	clk_irq = ctexdbg_arch_lock_kernel();	
- + 	
- + 	nlen = strlen(mod->name);
- + 	
- + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) 
- + 	offset = (unsigned long)mod->module_init;
- + #else
- + 	offset = (unsigned long)mod + mod->size_of_struct;
- + #endif /* Lver */
- + 
- + 	/* check debug filelist */
- + 	if(ctexdbg_find_file((char*)mod->name,NULL,0) != 1){
- + 		ctexdbg_arch_unlock_kernel(clk_irq);	
- + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26) 		
- + 		return 0;
- + #else
- + 		return mod->init();
- + #endif
- + 	}
- + 	for(i=0;i<CTEXDBG_MODULE_MAX;i++){
- + 		if(ctexdbg_moddata[i].mod == mod)	break;
- + 	}
- + 	if(i>=CTEXDBG_MODULE_MAX)	i=0;
- + 
- + 	/* fmt: [offset] [initaddr] [name length] [name...] [startaddr] [symtab] [nsyms] [strtab] */
- + 	p = ctexdbg_evdata;
- + 	memcpy(p,&(offset),sizeof(uint32_t));
- + 	p += sizeof(uint32_t);
- + 	memcpy(p,&(mod->init),sizeof(uint32_t));
- + 	p += sizeof(uint32_t);
- + 
- + 	/* ver009 send type*/		
- + 	memcpy(p,&(ctexdbg_moddata[i].start_addr),sizeof(uint32_t));
- + 	p += sizeof(uint32_t);
- + 	memcpy(p,&(ctexdbg_moddata[i].symtab_addr),sizeof(uint32_t));
- + 	p += sizeof(uint32_t);
- + 	memcpy(p,&(ctexdbg_moddata[i].numsym),sizeof(uint32_t));
- + 	p += sizeof(uint32_t);
- + 	memcpy(p,&(ctexdbg_moddata[i].strtab_addr),sizeof(uint32_t));
- + 	p += sizeof(uint32_t);
- + 	memcpy(p,&(ctexdbg_moddata[i].rodata_addr),sizeof(uint32_t));
- + 	p += sizeof(uint32_t);
- + 	memcpy(p,&(ctexdbg_moddata[i].data_addr),sizeof(uint32_t));
- + 	p += sizeof(uint32_t);
- + 	memcpy(p,&(ctexdbg_moddata[i].bss_addr),sizeof(uint32_t));
- + 	p += sizeof(uint32_t);
- + 			
- + 	memcpy(p,&(nlen),sizeof(uint32_t));
- + 	p += sizeof(uint32_t);
- + 	strcpy(p,mod->name);
- + 	
- + 	ctexdbg_event(current,CTEXDBG_EV_MODULE_INIT);
- + 	
- + 	ctexdbg_arch_unlock_kernel(clk_irq);	
- + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26) 		
- + 	return 0;
- + #else
- + 	return mod->init();
- + #endif
- + }
- + 
- + /* signal event and force break operation */
- + int ctexdbg_signals(uint32_t signa,uint32_t pid,struct pt_regs *regs)
- + {
- + 	unsigned long clk_irq;
- + 	/* check a signal */
- + 	if(_NSIG < signa)	return 0;		/* unknown signal */
- + 		
- + 	if( (ctexdbg_forcebreaksig_pid == pid) &&
- + 		(signa == SIGSTOP) ){
- + 		
- + 		if(ctexdbg_ddebugevent == 1)	ctexdbg_print_context_reg(regs);
- + 		/* Force break hook */
- + 		clk_irq = ctexdbg_arch_lock_kernel();
- + 		ctexdbg_event(current,CTEXDBG_EV_PBREAK_FBREAK);
- + 		ctexdbg_arch_unlock_kernel(clk_irq);
- + 		if(ctexdbg_allbreak != 0){
- + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
- + 			spin_unlock_irq(&current->sighand->siglock);
- + #endif
- + 			return 1;
- + 		}
- + 	}else if(ctexdbg_breaksig[signa] == 1){
- + 		if(ctexdbg_ddebugevent == 1)	ctexdbg_print_context_reg(regs);
- + 		ctexdbg_signalbreak(pid,signa);
- + 	}
- + 	
- + 	return 0;
- + }
- + 
- + /* signal break handler */
- + void ctexdbg_signalbreak(uint32_t pid,uint32_t sig)
- + {
- + 	char *p;
- + 	unsigned long clk_irq;
- + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
- + 	/* irq_lock must be canceled before locking kern */
- + 	spin_unlock_irq(&current->sighand->siglock);
- + #endif
- + 	clk_irq = ctexdbg_arch_lock_kernel();
- + 	
- + 	p = ctexdbg_evdata;
- + 	memcpy(p,&pid,sizeof(uint32_t));
- + 	p += sizeof(uint32_t);
- + 	memcpy(p,&sig,sizeof(uint32_t));
- + 	
- + 	ctexdbg_event(current,CTEXDBG_EV_SIGNAL);
- + 	
- + 	if(ctexdbg_allbreak != 0)	goto signalbreak_exit;
- + 	if(ctexdbg_workbuf[0] != 1)		goto signalbreak_exit;
- + 	
- + 	ctexdbg_arch_unlock_kernel(clk_irq);
- + 	
- + 	/* waiting. for ctexdbg event */
- + 	wait_event(kctexdbgd_signal_wait,ctexdbg_wakeuppid == current->pid);
- + 	/* wake up */
- + 	clk_irq = ctexdbg_arch_lock_kernel();
- + 	spin_lock(&ctexdbg_continue_spinlock);	
- + 	ctexdbg_wakeuppid = 0;
- + 	ctexdbg_event(current,CTEXDBG_EV_SIGNAL_WAKEUP);
- + 	spin_unlock(&ctexdbg_continue_spinlock);	
- + 	
- + signalbreak_exit:	
- + 	ctexdbg_arch_unlock_kernel(clk_irq);	
- + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
- + 	spin_lock_irq(&current->sighand->siglock);
- + #endif
- + }
- + 
- + /* process break handler */
- + #ifdef CONFIG_ARM
- + void ctexdbg_pbreak(void)
- + #else
- + void ctexdbg_pbreak_cmn(void)
- + #endif /* CONFIG_ARM */
- + {
- + 	/* waiting. for ctexdbg event */
- + 	wait_event(kctexdbgd_process_wait,ctexdbg_wakeuppid == current->pid);
- + 	spin_lock(&ctexdbg_continue_spinlock);
- + 	ctexdbg_wakeuppid = 0;
- + 	spin_unlock(&ctexdbg_continue_spinlock);
- + 	ctexdbg_exec_setall_cpu_mask(current);
- + 	ctexdbg_event(current,CTEXDBG_EV_PBREAK_WAKEUP);
- + 	/* Do not return */
- + }
- + 
- + 
- + /* process FORCE break handler */
- + int ctexdbg_forcebreak(struct task_struct *tsk)
- + {
- + 	unsigned long clk_irq;
- + 	
- + 	/* isnot CTEX forcebreak... */
- + 	if(ctexdbg_forcebreaksig_pid != tsk->pid)	return 0;
- + 	
- + 	ctexdbg_forcebreaksig_pid = 0;
- + 	
- + 	/* irq_lock must be canceled before locking kern */
- + 	spin_unlock_irq(&current->sighand->siglock);
- + 	
- + 	/* waiting. for ctexdbg event */
- + 	wait_event(kctexdbgd_force_wait,ctexdbg_wakeuppid == current->pid);
- + 	/* I can wake up ? */
- + 	clk_irq = ctexdbg_arch_lock_kernel();
- + 	spin_lock(&ctexdbg_continue_spinlock);
- + 	ctexdbg_wakeuppid = 0;
- + 	
- + 	ctexdbg_event(current,CTEXDBG_EV_PBREAK_FBREAK_WAKEUP);
- + 	
- + 	spin_unlock(&ctexdbg_continue_spinlock);	
- + 	ctexdbg_arch_unlock_kernel(clk_irq);
- + 	return 1;
- + }
- + 
- + 
- + /*
- +  * check page from vm_arae
- +  */
- + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) 
- + int ctexdbg_do_check_page(struct vm_area_struct * vma,unsigned long address)
- + {
- + 	unsigned long check_addr_offset;
- + 	int i;
- + 	int check_present = 0;
- + 	struct address_space * checkaddr_space;
- + 	struct page * check_page;
- + 
- + 	if(vma == NULL) return -1;
- + 	if(vma->vm_file == NULL) return -1;
- + 	if(vma->vm_file->f_mapping == NULL) return -1;
- + 	checkaddr_space = vma->vm_file->f_mapping;
- + 	
- + 	for(i = 0;i < CTEXDBG_PGOFF_MAX;i++){
- + 		if(ctexdbg_areatable[i].pid == 0){
- + 			/* end of table */
- + 			return -1;
- + 		}
- + 		ctexdbg_prn("ctexdbg","do_no_page pid %d tgid %d vma_s=0x%08lx vma_e=0x%08lx addr=0x%08lx\n",
- + 						current->pid,current->tgid,vma->vm_start,vma->vm_end,address);
- + 		if((current->pid == ctexdbg_areatable[i].pid) ||
- + 		   (current->tgid == ctexdbg_areatable[i].pid)
- + 		){
- + 			if(unlikely(address == ctexdbg_areatable[i].address)){
- + 				/* hit */
- + 				return i;
- + 			}else
- + 			if((vma->vm_start <= ctexdbg_areatable[i].address) &&
- + 				(vma->vm_end >= ctexdbg_areatable[i].address)
- + 			){
- + 				check_addr_offset = 
- + 					((ctexdbg_areatable[i].address - vma->vm_start) >> PAGE_SHIFT) + vma->vm_pgoff;
- + 				
- + 				check_page = find_get_page(checkaddr_space, check_addr_offset);				
- + 				if(unlikely(check_page == NULL)){
- + 					/* page not found */
- + 					continue;
- + 				}
- + 				check_present = PageUptodate(check_page);
- + 				page_cache_release(check_page);
- + 				if(check_present != 0){
- + 					/* hit. this activate page address */
- + 					return i;
- + 				}
- + 			}
- + 		}
- + 	}		
- + 	return -1;
- + }
- + #else
- + int ctexdbg_do_check_page(struct vm_area_struct * vma,unsigned long address)
- + {
- + 	int i,same=0;
- + 
- + 	if(vma == NULL) return -1;
- + 
- + 	for(i = 0;i < CTEXDBG_PGOFF_MAX;i++){
- + 		if(ctexdbg_areatable[i].pid == 0){
- + 			/* end of table */
- + 			return -1;
- + 		}
- + 
- + 		ctexdbg_prn("ctexdbg","do_no_page pid %d vma_s=0x%08lx vma_e=0x%08lx\n",
- + 						current->pid,vma->vm_start,vma->vm_end);
- + 		if(current->mm != NULL){
- + 			ctexdbg_prn("ctexdbg","mm = 0x%08x pgd=0x%08x pgdp=0x%08x\n",
- + 						(uint32_t)current->mm,(uint32_t)current->mm->pgd);
- + 		}
- + 
- + 		if((current->pid == ctexdbg_areatable[i].pid) &&
- + 			(vma->vm_start <= ctexdbg_areatable[i].address) &&
- + 			(vma->vm_end >= ctexdbg_areatable[i].address)
- + 		){
- + 			same = 1;
- + 		}
- + 
- + 		/* 2.4 FIX use pgd */
- + 		if(current->mm != NULL){
- + 			if( ((uint32_t)current->mm->pgd == ctexdbg_areatable[i].pgd) &&
- + 				(vma->vm_start <= ctexdbg_areatable[i].address) &&
- + 				(vma->vm_end >= ctexdbg_areatable[i].address)
- + 			){
- + 				same = 1;
- + 			}
- + 		}
- + 
- + 		if(same == 1){
- + 			return i;
- + 		}
- + 	}
- + 	return -1;
- + }
- + #endif	/* 2.6 */
- + 
- + /*
- +  * do_no_page()  page non -> load end handler.
- +  */
- + void ctexdbg_do_no_page(struct vm_area_struct * vma,unsigned long address)
- + {
- + 	uint32_t i;
- + 	char *p;
- + 	int checkret;
- + 	unsigned long clk_irq;
- + 	
- + 	if(ctexdbg_enabled == 0) return;
- + 	
- + 	checkret = ctexdbg_do_check_page(vma,address);
- + 	if(checkret < 0) return;
- + 	
- + 	clk_irq = ctexdbg_arch_lock_kernel();	
- + 	
- + 	p = ctexdbg_evdata;
- + 	i = (uint32_t)checkret;
- + 	memcpy(p,&i,sizeof(uint32_t));
- + 		
- + 	ctexdbg_event(current,CTEXDBG_EV_NOPAGE);			
- + 	
- + 	ctexdbg_arch_unlock_kernel(clk_irq);
- + }
- + 
- + 
- + /*
- +  * file mapped handler (from do_mmap_pgoff)
- +  */
- + void ctexdbg_filemap(struct vm_area_struct * vma)
- + {
- + 	char *p;
- + 	unsigned long clk_irq;	
- + 	
- + 	if(ctexdbg_enabled == 0) return;
- + 
- + 	if(vma == NULL) return;
- + 	if((vma->vm_flags & VM_EXEC) == 0) return;
- + 	
- + 	clk_irq = ctexdbg_arch_lock_kernel();	
- + 	
- + 	if(ctexdbg_find_debugpid(current->pid) == NULL) goto filemap_exit;
- + 	if(ctexdbg_varid_vma(vma) == 1)		goto filemap_exit;
- + 	
- + 	ctexdbg_prn("ctexdbg","ctexdbg_filemap %s\n",
- + 				vma->vm_file->f_dentry->d_name.name);
- + 
- + 	if(ctexdbg_find_file((char*)vma->vm_file->f_dentry->d_name.name,NULL,0) == 0){
- + 		goto filemap_exit;
- + 	}
- + 	p = ctexdbg_evdata;
- + 	memcpy(p,&(current->pid),sizeof(uint32_t));
- + 	p += sizeof(uint32_t);
- + 	memcpy(p,&(vma->vm_start),sizeof(uint32_t));
- + 	p += sizeof(uint32_t);
- + 	memcpy(p,&(vma->vm_end),sizeof(uint32_t));
- + 	p += sizeof(uint32_t);
- + 	memcpy(p,&(vma->vm_file->f_dentry->d_name.len),sizeof(uint32_t));
- + 	p += sizeof(uint32_t);
- + 	memcpy(p,vma->vm_file->f_dentry->d_name.name,vma->vm_file->f_dentry->d_name.len);
- + 		
- + 	ctexdbg_event(current,CTEXDBG_EV_FILEMAP);
- + 	
- + filemap_exit:
- + 	ctexdbg_arch_unlock_kernel(clk_irq);	
- + }
- + 
- + /* happened fork and clone  */
- + int ctexdbg_forking(struct task_struct *tsk,unsigned long clone_flags,unsigned long stack_start)
- + {
- + 	char *p;
- + 	struct mm_struct *mm;
- + 	struct vm_area_struct * map;
- + 	unsigned long clk_irq;
- + 
- + 	if ((clone_flags & (CLONE_FS | CLONE_FILES | CLONE_VM | CLONE_SIGHAND)
- + 		) != (CLONE_FS | CLONE_FILES | CLONE_VM | CLONE_SIGHAND) ) {
- + 		return 0;
- + 	}
- + 	
- + 	clk_irq = ctexdbg_arch_lock_kernel();
- + 
- + 	/* parent was debug process ? */
- + 	if (ctexdbg_find_debugpid(current->pid) == NULL) goto forking_exit;
- + 		
- + 	/* no clone check mode */		
- + 	if(ctexdbg_noclone_debug == 1)	goto forking_exit;
- + 	
- + 	/* find pthred lib */
- + 	mm = tsk->mm;
- + 	if(mm == NULL)		goto forking_exit;
- + 	
- + 	map = mm->mmap;
- + 	while (map) {
- + 		if(map->vm_file != NULL){
- + 			if(strstr(map->vm_file->f_dentry->d_name.name,"libpthread") != NULL){
- + 				break;
- + 			}
- + #ifdef CONFIG_CTEX_DBGLIB_ANDROID
- + 			if(strstr(map->vm_file->f_dentry->d_name.name,"libc.so") != NULL){
- + 				break;
- + 			}
- + #endif
- + 		}
- + 		map = map->vm_next;
- + 	}
- + 	if(map == NULL)	goto forking_exit;	
- + 	
- + 	/* stop a pthread clone only */
- + 	p = ctexdbg_evdata;
- + 	memcpy(p,&tsk->pid,sizeof(uint32_t));		/* create pid */
- + 	p += sizeof(uint32_t);
- + 	memcpy(p,&clone_flags,sizeof(uint32_t));	/* flags */
- + 	p += sizeof(uint32_t);
- + 	memcpy(p,&stack_start,sizeof(uint32_t));	/* start stack */
- + 	p += sizeof(uint32_t);
- + 	memcpy(p,&current->pid,sizeof(uint32_t));	/* paernt pid */
- + 	p += sizeof(uint32_t);
- + 	memcpy(p,&mm->pgd,sizeof(uint32_t));		/* pgd */
- + 	p += sizeof(uint32_t);
- + 
- + 	ctexdbg_event(tsk,CTEXDBG_EV_FORK);		
- + 		
- + 	ctexdbg_add_debugpid(tsk->pid);
- + 		
- + 	ctexdbg_arch_unlock_kernel(clk_irq);
- + 		
- + 	return 0;
- + 
- + forking_exit:
- + 	ctexdbg_arch_unlock_kernel(clk_irq);
- + 	return 0;
- + }
- + 
- + /* pre MAIN() break handler */
- + int ctexdbg_main_pre_brk(struct task_struct *tsk,unsigned long entryaddr,unsigned long ppgd)
- + {
- + 	unsigned long clk_irq;
- + 	char *p;
- + 	if(ctexdbg_enabled == 0) return 0;
- + 
- + 	if(ctexdbg_premain_debug == 0)	return 0;
- + 	
- + 	clk_irq = ctexdbg_arch_lock_kernel();
- + 		
- + 	if (ctexdbg_find_debugpid(tsk->pid) == NULL) goto prebrk_exit;
- + 	
- + 	ctexdbg_prn("ctexdbg","ctexdbg_main_pre_brk pid %d entry %08X\n",tsk->pid,(unsigned int)entryaddr);
- + 
- + 	/* send data... [pid][entry] */
- + 	p = ctexdbg_evdata;
- + 	memcpy(p,&tsk->pid,sizeof(uint32_t));	/* pid */
- + 	p += sizeof(uint32_t);
- + 	memcpy(p,&entryaddr,sizeof(uint32_t));	/* entries address */
- + 	p += sizeof(uint32_t);
- + 	memcpy(p,&ppgd,sizeof(uint32_t));		/* pgd */
- + 	p += sizeof(uint32_t);
- + 
- + 	ctexdbg_event(tsk,CTEXDBG_EV_PREMAIN);
- + 	
- + prebrk_exit:
- + 	ctexdbg_arch_unlock_kernel(clk_irq);
- + 	return 0;
- + }
- + 
- + 
- + /* ------------------------------- event handlers ---------------------------------- */
- + 
- + 
- + void ctexdbg_process_exit(void)
- + {
- + 	char *p;
- + 	unsigned long clk_irq;
- + 	if(ctexdbg_enabled == 0) return;
- + 	
- + 	clk_irq = ctexdbg_arch_lock_kernel();
- + 	
- + 	if(ctexdbg_find_debugpid(current->pid) == NULL){
- + 		goto process_exit_exit;
- + 	}
- + 	
- + 	p = ctexdbg_evdata;
- + 	memcpy(p,&current->pid,sizeof(uint32_t));		
- + 	ctexdbg_event(current,CTEXDBG_EV_EXIT_WAIT);
- + 	
- + 	/* wait mode check (sup. v006 later) */
- + 	if(ctexdbg_workbuf[0] != 1)	goto process_exit_removepid;
- + 	
- + 	if(ctexdbg_allbreak == 0){
- + 		ctexdbg_arch_unlock_kernel(clk_irq);		
- + 		/* waiting. for ctexdbg event */
- + 		wait_event(kctexdbgd_exit_wait,ctexdbg_wakeuppid == current->pid);			
- + 		clk_irq = ctexdbg_arch_lock_kernel();
- + 		spin_lock(&ctexdbg_continue_spinlock);
- + 		ctexdbg_wakeuppid = 0;
- + 		spin_unlock(&ctexdbg_continue_spinlock);
- + 	}
- + 	ctexdbg_event(current,CTEXDBG_EV_EXIT_WAKEUP);
- + 	
- + process_exit_removepid:	
- + 	ctexdbg_remove_debugpid(current->pid);
- + process_exit_exit:	
- + 	ctexdbg_arch_unlock_kernel(clk_irq);
- + }
- + 
- + void ctexdbg_file_event(struct task_struct *tsk, struct file *file,uint32_t pgd)
- + {
- + 	char *p;
- + 	unsigned long clk_irq;	
- + 
- + 	if(ctexdbg_enabled == 0) return;
- + 	if(ctexdbg_noattach_debug == 1) return;
- + 	if(file == NULL) return;
- + 	
- + 	ctexdbg_exec_limit_cpu_mask(tsk);
- + 
- + 	clk_irq = ctexdbg_arch_lock_kernel();
- + 	
- + 	if(ctexdbg_find_file((char*)file->f_dentry->d_name.name,NULL,0) == 0){
- + 		ctexdbg_arch_unlock_kernel(clk_irq);
- + 		ctexdbg_exec_setall_cpu_mask(tsk);
- + 		return;
- + 	}
- + 
- + 	p = ctexdbg_evdata;
- + 	memcpy(p,&(tsk->pid),sizeof(uint32_t));
- + 	p += sizeof(uint32_t);
- + 	memcpy(p,&(file->f_dentry->d_name.len),sizeof(uint32_t));
- + 	p += sizeof(uint32_t);
- + 	memcpy(p,file->f_dentry->d_name.name,sizeof(char) * file->f_dentry->d_name.len);
- + 	p += sizeof(char) * file->f_dentry->d_name.len;
- + 	memcpy(p,&pgd,sizeof(uint32_t));
- + 	p += sizeof(uint32_t);
- + 
- + 	ctexdbg_event(current,CTEXDBG_EV_EXECVP);								
- + 	/* is this debug? */
- + 	if(ctexdbg_workbuf[0] == 1){
- + 		ctexdbg_add_debugpid(tsk->pid);
- + 	}
- + 	ctexdbg_arch_unlock_kernel(clk_irq);
- + 	
- + }
- + 
- + /*
- +  * find wait queue and wakeup task ...
- +  * r:
- +  *  !0: not found
- +  *  0: found and wakeup task
- +  */  
- + static int ctexdbg_wakeup_process(wait_queue_head_t *q,int mpid)
- + {
- + 	unsigned long flags;
- + 	struct list_head *tmp;
- + 	wait_queue_t *curr;
- + 	struct task_struct *p;
- + 	int ret = 1;
- + 	
- + 	spin_lock_irqsave(&q->lock, flags);
- + 	
- + 	list_for_each(tmp, &q->task_list) {
- + 		curr = list_entry(tmp, wait_queue_t, task_list);
- + #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13) 
- + 		p = curr->private;
- + #else
- + 		p = curr->task;
- + #endif
- + 		if(p->pid == mpid){
- + 			ret = 0;
- + 			spin_lock(&ctexdbg_continue_spinlock);
- + 			ctexdbg_wakeuppid = mpid;
- + 			wake_up_process(p);
- + 			spin_unlock(&ctexdbg_continue_spinlock);
- + 			break;
- + 		}
- + 	}	
- + 	spin_unlock_irqrestore(&q->lock, flags);
- + 	return ret;
- + }
- + 
- + /* ----------------- kctexdbg kernel thread part ----------------------------------------- */
- + /*
- +  * kctexdbg kernel thread monitor todo...
- +  */
- + int do_ctexdbg(void)
- + {
- + 	unsigned long lvar,kvar,nvar;
- + 	unsigned long retvar;
- + 
- + 	while(1){
- + 		if(ctexdbg_ddebugrecv == 1)		do_ctexdump();
- + 	
- + 		switch(ctexdbg_combuf[1]){
- + 		case CTEXDBG_NONE:											/* 0 */
- + 			/* No operation */
- + 			break;
- + 		case CTEXDBG_DBGPUT:										/* 1 */
- + 			/* put combuf */
- + 			do_ctexdump();
- + 			break;
- + 		case CTEXDBG_SENDSIG:										/* 2 */
- + 			/* send pid */
- + 			/*buf 4 5 6 7 ... pid */
- + 			/*buf 8 9 10 11 ... sig */
- + 			memcpy(&lvar,&ctexdbg_combuf[4],4);
- + 			memcpy(&kvar,&ctexdbg_combuf[8],4);
- + 			do_ctex_sendsig(lvar,kvar);
- + 			break;
- + 		case CTEXDBG_CONTINUE:										/* 3 */
- + 			/* continue stopped pid */
- + 			/*buf 4 5 6 7 ... pid */
- + 			memcpy(&lvar,&ctexdbg_combuf[4],4);
- + 			/* wait queue check and run task */
- + 			if(ctexdbg_wakeup_process(&kctexdbgd_process_wait,lvar) == 0) break;
- + 			if(ctexdbg_wakeup_process(&kctexdbgd_force_wait,lvar) == 0) break;
- + 			if(ctexdbg_wakeup_process(&kctexdbgd_signal_wait,lvar) == 0) break;
- + 			if(ctexdbg_wakeup_process(&kctexdbgd_exit_wait,lvar) == 0) break;
- + 			/* not found... send SIGCONT signal...*/
- + 			kvar = SIGCONT;
- + 			do_ctex_sendsig(lvar,kvar);
- + 			break;
- + 		case CTEXDBG_FORCEBREAK:									/* 4 */
- + 			/* force break process */
- + 			/* send SIGSTOP signal */
- + 			/*buf 4 5 6 7 ... pid */
- + 			memcpy(&lvar,&ctexdbg_combuf[4],4);
- + 			ctexdbg_forcebreaksig_pid = lvar;
- + 			do_ctex_sendsig(lvar,SIGSTOP);
- + 			break;
- + 		
- + 		/* ------------------ LTT and event ------------------------------- */
- + 			
- + 		case CTEXDBG_LTTRACE_START:									/* 5 */
- + 			retvar = 0;
- + #if defined(CONFIG_CTEX_TRACE)
- + 			/*buf 4 5 6 7 ... size */
- + 			/*buf 8 9 10 11 ... address */
- + 			/*buf 12 13 14 15 ... stopmode */
- + 			memcpy(&lvar,&ctexdbg_combuf[4],4);
- + 			memcpy(&kvar,&ctexdbg_combuf[8],4);		
- + 			memcpy(&nvar,&ctexdbg_combuf[12],4);		
- + 			if(ctexdbg_tracer_start(lvar,nvar) != 0){
- + 				retvar = 1;
- + 			}
- + #endif /* CONFIG_CTEX_TRACE */
- + 			memcpy(ctexdbg_evdata		,&retvar	,sizeof(unsigned long));
- + 			ctexdbg_event(current,CTEXDBG_EV_LTTRACE_STARTACK);
- + 			break;
- + 		case CTEXDBG_LTTRACE_STOP:									/* 6 */
- + #if defined(CONFIG_CTEX_TRACE)
- + 			ctexdbg_tracer_stop();
- + #endif /* CONFIG_CTEX_TRACE */
- + 			break;
- + 		case CTEXDBG_EVENT_SETBUFSIZE:								/* 7 */
- + 			/*buf 4 5 6 7 ... size */
- + 			/*buf 8 9 10 11 ... address */
- + 			/*buf 12 13 14 15 ... eventuse */
- + 			retvar = 0;
- + 			memcpy(&lvar,&ctexdbg_combuf[4],4);
- + 			memcpy(&kvar,&ctexdbg_combuf[8],4);
- + 			memcpy(&nvar,&ctexdbg_combuf[12],4);
- + 			ctexdbg_EventUse = nvar;
- + 			if(ctexdbg_EventUse == 1){
- + 				ctexdbg_EventBufSize = lvar;
- + 				if(ctexdbg_event_set_buffer_size(ctexdbg_EventBufSize) != 0){
- + 					retvar = 1; /* buffer error */
- + 				}
- + 			}
- + 			memcpy(ctexdbg_evdata		,&retvar	,sizeof(unsigned long));
- + 			ctexdbg_event(current,CTEXDBG_EV_EVENTSET_END);
- + 			break;
- + 			
- + 		/* ------------------ file opelation ------------------------------- */
- + 			
- + 		case CTEXDBG_FILE_LS:										/* 8 */
- + 			/* buf 4 ... dirname */
- + 			ctexdbg_file_ls(&ctexdbg_combuf[4]);
- + 			break;
- + 			
- + 		case CTEXDBG_FILE_RMDIR:									/* 9 */
- + 			/* buf 4 ... dirname */
- + 			ctexdbg_file_rmdir(&ctexdbg_combuf[4]);
- + 			break;
- + 			
- + 		case CTEXDBG_FILE_MKDIR:									/* 10 */
- + 			/* buf 4 ... dirname */
- + 			ctexdbg_file_mkdir(&ctexdbg_combuf[4]);
- + 			break;			
- + 
- + 		case CTEXDBG_FILE_DELETE:									/* 11 */
- + 			/* buf 4 ... dirname */
- + 			ctexdbg_file_delfile(&ctexdbg_combuf[4]);
- + 			break;
- + 			
- + 		case CTEXDBG_FILE_READ:										/* 12 */
- + 			/* buf 4 ... dirname */
- + 			ctexdbg_file_read(&ctexdbg_combuf[4]);
- + 			break;
- + 			
- + 		case CTEXDBG_FILE_WRITE:									/* 13 */
- + 			/* buf 4 ... dirname */
- + 			ctexdbg_file_write(&ctexdbg_combuf[4]);
- + 			break;					
- + 			
- + 		case CTEXDBG_FILE_RENAME:									/* 15 */
- + 			/* buf 4 ... old+new path */
- + 			ctexdbg_file_rename(&ctexdbg_combuf[4]);
- + 			break;					
- + 		
- + 		case CTEXDBG_FILE_CHMOD:									/* 16 */
- + 			/* buf 4 ... filename+attr */
- + 			ctexdbg_file_chmod(&ctexdbg_combuf[4]);
- + 			break;					
- + 		
- + 		case CTEXDBG_FILE_CHOWN:									/* 17 */
- + 			/* buf 4 ... filename+attr */
- + 			ctexdbg_file_chown(&ctexdbg_combuf[4]);
- + 			break;					
- + 			
- + 		/* ------------------ misc ------------------------------- */
- + 			
- + 		case CTEXDBG_TEST:
- + 			break;
- + 		}
- + 		
- + 		if(ctexdbg_combuf[3] == 0)	break;
- + 		
- + 		/* waiting data from ICE .... */
- + 		ctexdbg_event(current,CTEXDBG_EV_WAITDATA);
- + 	}
- + 	/* stops me ... */
- + 	ctexdbg_combuf[0] = 0;
- + 	
- + 	return 0;
- + }
- + 
- + 
- + /*
- +  * ctexdbgd wakeup check
- +  * r:
- +  *  0: sleeping or runnung
- +  *  1: now wakeup
- +  */
- + int ctexdbg_checkwakeup(void)
- + {
- + 	if(ctexdbg_combuf[0] == 0) return 0;
- + 	
- + 	wake_up(& kctexdbgd_wait);
- + 	return 1;
- + }
- + 
- + 
- + /*
- +  * ctexdbg kernel thread (monitor)
- +  */
- + int ctexdbg(void *startup)
- + {
- + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) 
- + 	int waitsig;
- + 	struct sched_param param = { .sched_priority = MAX_RT_PRIO-1 };
- + 	
- + 	/* ctexdbg must be cpuid zero */
- + 	set_cpus_allowed(current, CPU_MASK_CPU0);
- + 	ctexdbg_daemon_cpuid = smp_processor_id();
- + 	daemonize("kctexdbgd/%d",ctexdbg_daemon_cpuid);
- + #else
- + 	struct task_struct * tsk = current;
- + 	
- + 	tsk->session = 1;
- + 	tsk->pgrp = 1;
- + 	strcpy(tsk->comm, "kctexdbgd");
- + 
- + 	/* avoid getting signals */
- + 	spin_lock_irq(&tsk->sigmask_lock);
- + 	flush_signals(tsk);
- + 	sigfillset(&tsk->blocked);
- + 	recalc_sigpending(tsk);
- + 	spin_unlock_irq(&tsk->sigmask_lock);
- + 	
- + #endif /* LinuxVer */
- + 
- + 	ctexdbg_nrcpus = (uint32_t)num_online_cpus();
- + 	
- + 	memcpy(ctexdbg_patchver_char,CTEXDBG_PATCH_VERSION,4);
- + 	memcpy(&(ctexdbg_patchver_char[4]),CTEXDBG_PATCH_VERSION,4);
- + 
- + 	complete((struct completion *)startup);
- + 	
- + 	printk("ctexdbg enabled by computex.patch vers=%s online cpu=%d \n",ctexdbg_patchver_char,ctexdbg_nrcpus);
- + 	
- + 	sched_setscheduler(current, SCHED_FIFO, &param);
- + 	
- + 	/* checking ICE connect */
- + 	ctexdbg_arch_checkice();	
- + 	
- + 	for (;;) {
- + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) 
- + 		waitsig = wait_event_interruptible(kctexdbgd_wait,ctexdbg_combuf[0] != 0);
- + 		if(waitsig == -ERESTARTSYS)	continue;	/* was signal happened */
- + 		if(ctexdbg_combuf[0] == 0)	continue;
- + 		ctexdbg_combuf[0] = 0;		/* iam wakeup */
- + 		do_ctexdbg();
- + #else
- + 		if(!freezing(current)){
- + 			waitsig = wait_event_interruptible(kctexdbgd_wait,ctexdbg_combuf[0] != 0);
- + 			if(waitsig == -ERESTARTSYS)	continue;	/* was signal happened */
- + 			if(ctexdbg_combuf[0] == 0)	continue;
- + 		}
- + 		if(!try_to_freeze()){
- + 			ctexdbg_combuf[0] = 0;		/* iam wakeup */
- + 			do_ctexdbg();
- + 		}
- + #endif
- + 	}
- + 	return 0;
- + } 
- + 
- + /*
- +  * Initialize a ctexdbg thread
- +  */
- + static int __init ctexdbg_init(void)
- + {
- + 	static struct completion startup __initdata = COMPLETION_INITIALIZER(startup);
- + 	int i;
- + 	spin_lock_init(&ctexdbg_kernel_spinlock);
- + 	spin_lock_init(&ctexdbg_continue_spinlock);	
- + 	ctexdbg_daemon_cpuid = 0;
- + 	/* initialize internal data */
- + 	ctexdbg_traceuse = 0;
- + 	ctexdbg_wakeuppid = 0;
- + 	ctexdbg_forcebreaksig_pid = 0;
- + 	ctexdbg_enabled = 0;
- + 	ctexdbg_hardware_trace_enabled = 0;
- + 	ctexdbg_xipinram = 0;
- + 	
- + 	for(i=0;i<=_NSIG;i++){
- + 		/* set stop signal... */
- + 		ctexdbg_breaksig[i] = 1;
- + 	}
- + 	/* ignoreos signal */
- + 	ctexdbg_breaksig[SIGSTOP] = 0;
- + 	ctexdbg_breaksig[SIGCONT] = 0;
- + 	ctexdbg_breaksig[SIGPROF] = 0;
- + 	ctexdbg_breaksig[SIGALRM] = 0;
- + 	ctexdbg_breaksig[SIGCHLD] = 0;
- + 	ctexdbg_breaksig[SIGUSR1] = 0;
- + 	ctexdbg_breaksig[SIGUSR2] = 0;
- + 	ctexdbg_breaksig[SIGVTALRM] = 0;
- + 	ctexdbg_breaksig[SIGIO] = 0;
- + 	ctexdbg_breaksig[SIGPOLL] = 0;
- + 	ctexdbg_breaksig[SIGWINCH] = 0;
- + 	ctexdbg_breaksig[SIGTSTP] = 0;
- + 	ctexdbg_breaksig[SIGTTIN] = 0;
- + 	ctexdbg_breaksig[SIGTTOU] = 0;
- + 	
- + 	ctexdbg_forcebreaksig_pid = 0;
- + 	ctexdbg_allbreak = 0;
- + 	ctexdbg_pexitnochk = 0;
- + 	ctexdbg_noclone_debug = 0;
- + 	ctexdbg_noattach_debug = 0;
- + 	ctexdbg_premain_debug = 0;
- + 	
- + 	ctexdbg_arch_userregaddr();
- + 	ctexdbg_arch_init();
- + 	
- + 	memset(ctexdbg_combuf,0,512);
- + 	
- + 	for(i=0;i<10;i++){
- + 		ctexdbg_envpdata[i] = 0;
- + 	}
- + 	ctexdbg_envpstr[0] = '\0';
- + 	ctexdbg_preloadlib[0] = '\0';
- + 
- + 	for(i=0; i < CTEXDBG_PGOFF_MAX ;i++){
- + 		ctexdbg_areatable[i].pid = 0;
- + 		ctexdbg_areatable[i].pgd = 0;
- + 	}
- + 	
- + 	for(i=0; i < CTEXDBG_PIDSIZE_MAX ;i++){
- + 		ctexdbg_debugpid[i].pid = 0;
- + 		ctexdbg_debugpid[i].migration = 0;
- + 	}
- + 
- + 	for(i=0; i < CTEXDBG_MODULE_MAX ;i++){
- + 		ctexdbg_moddata[i].mod = NULL;
- + 	}
- + 			
- + 	memset((void*)ctexdbg_dbgfile,0,CTEXDBG_DBG_FNAMESIZE);
- + #ifdef CONFIG_CTEX_DBGLIB_ANDROID
- + 	ctexdbg_android = 1;				/* android flag */
- + #endif	
- + 	ctexdbg_event_init();
- + #if defined(CONFIG_CTEX_TRACE)
- + 	ctexdbg_tracer_init();
- + #endif /* CONFIG_CTEX_TRACE */
- + 	
- + 	/* enable something events ... */
- + 	ctexdbg_tracebufpos.sEventBuf = NULL;
- + 	ctexdbg_tracebufpos.sEventWritPos = NULL;
- + 	ctexdbg_tracebufpos.sEventReadPos = NULL;
- + 	ctexdbg_tracebufpos.sEventWritLimit = NULL;
- + 	ctexdbg_tracebufpos.sEventBufDir = 0;
- + 	
- + 	ctexdbg_evdata = (unsigned char*)(ctexdbg_workbuf + CTEXDBG_WORKBUF_START);
- + 	ctexdbg_debugpidmax = CTEXDBG_PIDSIZE_MAX;
- + 	
- + 	ctexdbg_fixdata.maxdbgfilelen = CTEXDBG_DBG_FNAMESIZE;
- + 	ctexdbg_fixdata.maxmapdatalen = CTEXDBG_MMAPDATA_SIZE;
- + 	ctexdbg_fixdata.maxevtasklen = CTEXDBG_EVENT_FNAMESIZE;
- + 	ctexdbg_fixdata.maxtrcmasklen = CTEXTRC_MASK_SIZE;
- + 
- + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
- + 	kernel_thread(ctexdbg, &startup, CLONE_KERNEL);
- + #else
- + 	kernel_thread(ctexdbg, &startup, CLONE_FS | CLONE_FILES | CLONE_SIGNAL);
- + #endif /* Linuxver */
- + 	wait_for_completion(&startup);
- +   
- + 	return 0;
- + }
- + 
- + module_init(ctexdbg_init)
- diff -crN linux-3.2.1_o/kernel/ctexevt.c linux-3.2.1_ctex/kernel/ctexevt.c
- *** linux-3.2.1_o/kernel/ctexevt.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1_ctex/kernel/ctexevt.c	2013-05-24 10:34:00.042254000 +0900
- ***************
- *** 0 ****
- --- 1,357 ----
- + /*
- +  * linux/kernel/ctexevt.c
- +  *
- +  * (C) Copyright 2004 - Computex co.,ltd.
- +  *
- +  * Computex dbglib support library event notifyer
- +  *
- +  * -- version info --------------------------------------------------
- +  *
- +  * version 008 - 2005/12/EE		add ctexdbg_EventJackEnv
- +  *                               (e/d LD_PRELOAD)
- +  *
- +  * version 005 - 2005/02/23		first release version
- +  *
- +  * version 004 - 2005/02/1x		pre version
- +  *
- +  * -------------------------------------------------------------------
- +  *
- +  */
- + 
- + #include <linux/kernel.h>
- + #include <linux/init.h>     /* For __init */
- + #include <linux/errno.h>    /* Miscellaneous error codes */
- + #include <linux/module.h>   /* EXPORT_SYMBOL */
- + #include <linux/proc_fs.h>
- + #include <linux/unistd.h>
- + #include <linux/version.h>
- + #include <linux/ctexdbg.h>  /* definitions */
- + #include <linux/sched.h>
- + #include <linux/completion.h>
- + #include <linux/vmalloc.h>
- + #include <linux/interrupt.h>
- + 
- + #include <linux/slab.h>
- + #include <linux/ctype.h>
- + #include <linux/pagemap.h>
- + 
- + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) 
- + #include <asm/semaphore.h>
- + #include <asm/processor.h>
- + #endif 
- + #include <linux/mm.h>
- + 
- + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) 
- + #include <linux/wrapper.h>
- + #include <linux/locks.h>
- + #else
- + #include <linux/namei.h>
- + #endif 
- + 
- + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) 
- + #include <linux/devfs_fs_kernel.h>
- + #endif
- + 
- + #include <asm/uaccess.h>
- + #include <linux/binfmts.h>
- + 
- + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36) 
- + extern int copy_strings_kernel(int argc,char ** argv, struct linux_binprm *bprm);
- + #endif
- + 
- + typedef struct __tag_cdbevt_bufpos
- + {
- + 	char* sEventBuf;                  /* Event Buffer */
- + 	char* sEventWritPos;              /* Current position for writting */
- + 	char* sEventReadPos;              /* Current position for reading */
- + 	char* sEventWritLimit;            /* Limit at which write should stop */	
- + 	uint32_t  sEventBufDir;			  /* Buffer dir */
- + }cdbevt_bufpos;
- + 
- + typedef struct __tag_cdbevt_common_data
- + {
- +   unsigned long eid;      /* event id */
- +   unsigned long pid;      /* process id */
- +   unsigned long size;     /* after private data size */
- + }cdbevt_common_data;
- + 
- + extern char*  ctexdbg_envpdata[10];		/* special envp */
- + extern char   ctexdbg_envpstr[100];
- + extern char   ctexdbg_preloadlib[100];
- + extern uint32_t ctexdbg_enabled;		/* enable disable ctexdbg */
- + 
- + static uint32_t               sBufSize;              /* Buffer sizes */
- + static uint32_t               sAllocSize;            /* Size of buffers allocated */
- + 
- + cdbevt_bufpos	ctexdbg_eventbufpos;				/* buffer position */
- + 
- + 
- + char* ctexdbg_EventBuf = NULL;							/* pointer of Event buffer */
- + uint32_t ctexdbg_EventBufSize = CTEXDBG_EVENTBUF_SIZE;	/* event buffer size */
- + uint32_t ctexdbg_EventUse = 0;							/* enable event */
- + uint32_t ctexdbg_EventAll = 0;							/* v008: 0: event use debug process only */
- +  														/*       1: event use all process */
- + 														/*       2: Mask event name */
- + uint32_t ctexdbg_EventJackEnv = 0;						/* v008: 0: use envp jack */
- + 														/*       1: unuse envp jack */
- + 
- + //#ifndef CONFIG_ARM
- + #define CTEXDBG_TRACER_BUFSTATIC
- + //#endif /* NOTARM */
- + 
- + #ifdef CTEXDBG_TRACER_BUFSTATIC
- + static char ctexdbg_sEventBuffer[CTEXDBG_EVENTBUF_SIZE];
- + #endif /* CTEXDBG_TRACER_BUFSTATIC */
- + 
- + uint32_t ctexdbg_EventMaskName = 0;						/* v006: 0: no event mask  */
- + 														/*       1: event mask proc name */
- + char ctexdbg_eventtskname[CTEXDBG_EVENT_FNAMESIZE];	/* debug file list (need ctexdbg_pexitnochk = 1) */
- + 
- + static spinlock_t             sSpinLock;             /* Spinlock in order to lock kernel */
- + 
- + 
- + /* ------------------------ memry allocate --------------------------------------------- */
- + #define FIX_SIZE(x) (((x) - 1) & PAGE_MASK) + PAGE_SIZE /* This inspired by rtai/shmem */
- + 
- + /* --- kernel execvp hook --- */
- + 
- + /* check preload library */
- + int ctexdbg_set_envp_ldpreload(void)
- + {
- + 	int paerror = 0;
- + 	struct path xpath;
- + 	if(ctexdbg_preloadlib[0] == '\0') return 1;
- + 	paerror = kern_path(ctexdbg_preloadlib, LOOKUP_FOLLOW, &xpath);
- + 	if (paerror) return 1;
- + 	path_put(&xpath);
- + 	
- + 	strcpy(ctexdbg_envpstr,"LD_PRELOAD=");
- + 	strcat(ctexdbg_envpstr,ctexdbg_preloadlib);
- + 	
- + 	return 0;
- + }
- + 
- + /* returned special enviroment envp */
- + int ctexdbg_get_subenvp(char *filename, void *bprm)
- + {
- + 	struct linux_binprm *l_bprm = (struct linux_binprm *)bprm;
- + 	int retval=0;
- + 	if(ctexdbg_enabled == 0) return 0;
- + 	if(ctexdbg_EventUse == 0) return 0;
- + 	
- + 	if(ctexdbg_EventAll == 0){
- + 		if(ctexdbg_find_debugpid(current->pid) == NULL) return 0;
- + 	}
- + 	
- + 	if(ctexdbg_EventAll == 2){
- + 		if(ctexdbg_find_file (filename,ctexdbg_eventtskname,CTEXDBG_EVENT_FNAMESIZE) == 0){
- + 			return 0;
- + 		}	
- + 	}	
- + 	
- + 	if(ctexdbg_eventbufpos.sEventBuf == NULL){
- + 		ctexdbg_event_set_buffer_size(ctexdbg_EventBufSize);
- + 	}
- + 	
- + 	if(ctexdbg_EventJackEnv == 1){
- + 		/* do not jacking */
- + 		return 0;
- + 	}
- + 	/* Jacking... injection preload library */
- + 	if(ctexdbg_set_envp_ldpreload() == 1) return 0;
- + 	
- + 	ctexdbg_envpdata[0] = (char *) &ctexdbg_envpstr;
- + 	
- + 	retval = copy_strings_kernel(1,(const char* const*)ctexdbg_envpdata , l_bprm);
- + 	if(retval < 0) return -1;
- + 	
- + 	l_bprm->envc += 1;
- + 	return 0;
- + }
- + /* ---------------------------------- */
- + 
- + 
- + #define BKK(x) ((x) << PAGE_SHIFT)
- + 
- + static void ctexdbg_event_cleanbuf(void)
- + {
- + 	memset(ctexdbg_eventbufpos.sEventBuf,0xFE,sBufSize);
- + }
- + 
- + int ctexdbg_event_set_buffer_size(int pmSize)
- + {
- + #ifdef CTEXDBG_TRACER_BUFSTATIC
- +  /* clean */
- + 	ctexdbg_eventbufpos.sEventBuf = NULL;
- + 	ctexdbg_eventbufpos.sEventWritPos = NULL;
- + 	ctexdbg_eventbufpos.sEventReadPos = NULL;
- + 	ctexdbg_eventbufpos.sEventWritLimit = NULL;
- + 	ctexdbg_eventbufpos.sEventBufDir = 0;	
- + 	
- + 	ctexdbg_eventbufpos.sEventBuf = ctexdbg_sEventBuffer;
- + 	
- + 	sBufSize = CTEXDBG_EVENTBUF_SIZE;
- + 	sAllocSize = CTEXDBG_EVENTBUF_SIZE;  
- + 
- + #else /* CTEXDBG_TRACER_BUFSTATIC */
- + 	int	lSizeAlloc;     	/* Size to be allocated */
- + 	int	lSizeMax;		/* Max alloc size */
- + 	struct sysinfo i;		/* memory size */
- + 	
- + 	/* Set size to allocate (= pmSize) and fix it's size to be on a page boundary */
- + 	lSizeAlloc = FIX_SIZE(pmSize);
- + 	
- + 	/* Free the current buffers, if any */
- + 	if(ctexdbg_eventbufpos.sEventBuf !=  NULL)
- + 		kfree(ctexdbg_eventbufpos.sEventBuf);
- + 	/* clean */
- + 	ctexdbg_eventbufpos.sEventBuf = NULL;
- + 	ctexdbg_eventbufpos.sEventWritPos = NULL;
- + 	ctexdbg_eventbufpos.sEventReadPos = NULL;
- + 	ctexdbg_eventbufpos.sEventWritLimit = NULL;
- + 	ctexdbg_eventbufpos.sEventBufDir = 0;	
- + 		
- + 	/* calclation sizeing...*/
- + 	si_meminfo(&i);
- + 	lSizeMax = BKK(i.freeram) - 100000;
- + 	if(lSizeAlloc >= lSizeMax){
- + 		/* Over memory ... return ERROR */
- + 		ctexdbg_EventUse = 0;
- + 		return 1;
- + 	}
- + 	
- + 	/* Allocate space for the tracing buffers */
- + 	if((ctexdbg_eventbufpos.sEventBuf = (char*) kmalloc(lSizeAlloc,GFP_KERNEL|__GFP_NORETRY)) == NULL){
- + 		ctexdbg_EventUse = 0;
- + 		return 1;
- + 	}
- + 		
- + 	/* Remember the size set */
- + 	sBufSize = pmSize;
- + 	sAllocSize = lSizeAlloc;
- + 
- + #endif /* CTEXDBG_TRACER_BUFSTATIC */
- +   
- + 	/* Set the read and write buffers */
- + 	ctexdbg_eventbufpos.sEventWritPos = ctexdbg_eventbufpos.sEventBuf;
- + 	
- + 	/* Set write limit */
- + 	ctexdbg_eventbufpos.sEventWritLimit = ctexdbg_eventbufpos.sEventWritPos + sBufSize;
- + 	
- + 	/* Set write position */
- + 	ctexdbg_eventbufpos.sEventReadPos = ctexdbg_eventbufpos.sEventBuf;
- + 	
- + 	ctexdbg_event_cleanbuf();
- + 	
- + 	/* All is OK */
- + 	return 0;
- + }
- + 
- + 
- + void ctexdbg_event_switch_buffers(void)
- + {
- + 	if(ctexdbg_eventbufpos.sEventReadPos == ctexdbg_eventbufpos.sEventBuf){
- + 		/* STOP! this read point ... */
- + 		ctexdbg_eventfull_bp();
- + 		ctexdbg_eventbufpos.sEventBufDir = 0;
- + 		ctexdbg_eventbufpos.sEventReadPos = ctexdbg_eventbufpos.sEventBuf;
- + 	}else if(ctexdbg_eventbufpos.sEventBufDir == 0){
- + 		ctexdbg_eventbufpos.sEventBufDir = 1;
- + 	}else{
- + 		/* STOP! this read point ... */
- + 		ctexdbg_eventfull_bp();
- + 		ctexdbg_eventbufpos.sEventBufDir = 0;
- + 		ctexdbg_eventbufpos.sEventReadPos = ctexdbg_eventbufpos.sEventBuf;
- + 	}
- + 	ctexdbg_eventbufpos.sEventWritPos = ctexdbg_eventbufpos.sEventBuf;
- + }
- + 
- + void ctexdbg_event_read_buffers(void)
- + {
- + 	/* read stop */
- + 	ctexdbg_eventfull_bp();
- + 	
- + 	ctexdbg_eventbufpos.sEventWritPos = ctexdbg_eventbufpos.sEventBuf;
- + 	ctexdbg_eventbufpos.sEventReadPos = ctexdbg_eventbufpos.sEventBuf;
- + 	ctexdbg_eventbufpos.sEventBufDir = 0;
- + }
- + 
- + int ctexdbg_event_filter(void *ptr)
- + {
- + 	cdbevt_common_data *pdata = (cdbevt_common_data *)ptr;
- + 	struct task_struct *tsk;
- + 	struct mm_struct *mm;
- + 		
- + 	if(ctexdbg_EventAll == 1) return 0;
- + 	
- + 	if(ctexdbg_EventAll == 0){
- + 		if(ctexdbg_EventJackEnv == 0){
- + 			return 0;
- + 		}
- + 		if(ctexdbg_find_debugpid(current->pid) != NULL) return 0;
- + 		
- + 		return 1;
- + 	}
- + 	
- + #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,26)
- + 	tsk = find_task_by_pid_ns(pdata->pid, &init_pid_ns);
- + #else
- + 	tsk = find_task_by_pid(pdata->pid);
- + #endif	
- + 	
- + 	if(tsk == NULL) return 1;
- + 	
- + 	mm = tsk->mm;
- + 	if(ctexdbg_varid_dname(mm) == 1){
- + 		return 1;
- + 	}
- + 	if(ctexdbg_find_file ((char *) mm->mmap->vm_file->f_dentry->d_name.name,ctexdbg_eventtskname,CTEXDBG_EVENT_FNAMESIZE) == 0){
- + 		return 1;
- + 	}
- + 	return 0;
- + }
- + 
- + 
- + /*
- +  * event notify from user program
- +  */
- + void ctexdbg_external_notify(size_t size,void *ptr)
- + {
- + 	unsigned long int   lFlags;                   /* CPU flags for lock */
- + 	
- + 	if( ctexdbg_enabled == 0 ) return;
- + 	if( ctexdbg_EventUse == 0 ) return;
- + 	
- + 	/* Lock the kernel */
- + 	spin_lock_irqsave(&sSpinLock, lFlags);	
- + 	
- + 	if( ctexdbg_event_filter(ptr) == 1) goto notify_exit;
- + 	if( (ctexdbg_eventbufpos.sEventWritPos + size) >= ctexdbg_eventbufpos.sEventWritLimit){
- + 		/* Switch buffers */
- + 		ctexdbg_event_switch_buffers();
- + 	}
- + 	if((ctexdbg_eventbufpos.sEventBufDir == 1) && 
- + 		( (ctexdbg_eventbufpos.sEventWritPos + size) >= ctexdbg_eventbufpos.sEventReadPos) ){
- + 		ctexdbg_event_read_buffers();
- + 	}
- + 	
- + 	if(copy_from_user(ctexdbg_eventbufpos.sEventWritPos, (void*) ptr, size)){
- + 		printk("ctexdbg: read miss event\n");
- + 		goto notify_exit;
- + 	}
- + 	ctexdbg_eventbufpos.sEventWritPos += size;
- + 
- + notify_exit:
- + 	spin_unlock_irqrestore(&sSpinLock, lFlags);	
- + }
- + 
- + void ctexdbg_event_init()
- + {
- + 	spin_lock_init(&sSpinLock);
- + 	ctexdbg_eventbufpos.sEventBuf = NULL;
- + 	ctexdbg_eventbufpos.sEventWritPos = NULL;
- + 	ctexdbg_eventbufpos.sEventReadPos = NULL;
- + 	ctexdbg_eventbufpos.sEventWritLimit = NULL;
- + 	ctexdbg_eventbufpos.sEventBufDir = 0;
- + 	memset(ctexdbg_eventtskname,0,CTEXDBG_EVENT_FNAMESIZE);
- + }
- diff -crN linux-3.2.1_o/kernel/ctexfile.c linux-3.2.1_ctex/kernel/ctexfile.c
- *** linux-3.2.1_o/kernel/ctexfile.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1_ctex/kernel/ctexfile.c	2013-05-24 10:28:33.990561270 +0900
- ***************
- *** 0 ****
- --- 1,534 ----
- + /*
- +  * linux/kernel/ctexfile.c
- +  *
- +  * (C) Copyright 2004 - Computex co.,ltd.
- +  *
- +  * Computex dbglib support kernel thread (file operation)
- +  *
- +  * -- version info --------------------------------------------------
- +  *
- +  * version 012   - 2007/07/EE	update patch version
- +  *                               + support SMP
- +  *                               + add file operation buffer
- +  *                               + fixed file sync
- +  *
- +  * version 008 - 2005/12/EE		support file rename chmod chown
- +  *
- +  * version 005 - 2005/02/23		first release version
- +  *
- +  * version 004 - 2005/02/1x		pre version
- +  *
- +  * ------------------------------------------------------------------- 
- +  */
- + #define __KERNEL_SYSCALLS__
- + 
- + #include <linux/kernel.h>
- + #include <linux/init.h>     /* For __init */
- + #include <linux/proc_fs.h>
- + #include <linux/unistd.h>
- + #include <linux/dirent.h>
- + #include <linux/version.h>
- + 
- + 
- + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) 
- + #include <linux/locks.h>
- + #endif 
- + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) 
- + #include <linux/devfs_fs_kernel.h>
- + #endif
- + #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,20) 
- + #include <linux/syscalls.h>
- + #endif
- + 
- + 
- + #include <linux/ctexdbg.h>  /* definitions */
- + #include <linux/errno.h>    /* Miscellaneous error codes */
- + #include <linux/file.h>
- + #include <linux/delay.h>
- + 
- + #define CTEXDBG_FILEOP_SYNC_DUMMY_NAME ".ctexdbg_fop_temp"
- + 
- + enum CTEXDBG_FILE_MARKER
- + {
- + 	CTEXDBG_FILE_M_LS = 0,
- + 	CTEXDBG_FILE_M_READ,
- + 	CTEXDBG_FILE_M_WRITE,
- + 	CTEXDBG_FILE_M_RMDIR,
- + 	CTEXDBG_FILE_M_MKDIR,
- + 	CTEXDBG_FILE_M_DELFILE,
- + };
- + 
- + enum CTEXDBG_FILE_SMARKER
- + {
- + 	CTEXDBG_FILE_S_OK = 0,
- + 	CTEXDBG_FILE_S_ERR,
- + 	CTEXDBG_FILE_S_ERR_OPEN,
- + 	CTEXDBG_FILE_S_ERR_STAT,
- + };
- + 
- + extern unsigned char ctexdbg_filebuf[CTEXDBG_WORKBUF_SIZE+1];	/* file op working buffer (1kb) */
- + 
- + extern void ctexdbg_filelsfull_bp(void);
- + extern unsigned long ctexdbg_fileread_bp(void);
- + extern unsigned long ctexdbg_filewrite_bp(void);
- + extern void ctexdbg_fileend_bp(void);
- + 
- + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) 
- + extern long sys_getdents(unsigned int fd, void * dirent, unsigned int count);
- + extern long sys_newlstat(char * filename, struct stat * statbuf);
- + extern long sys_rmdir(const char * pathname);
- + extern long sys_mkdir(const char * pathname);
- + extern int sys_rename(const char * oldname, const char * newname);
- + extern int sys_chmod(const char * filename, mode_t mode);
- + extern long sys_chown(const char * filename, uid_t user, gid_t group);
- + extern long sys_unlink(const char * pathname);
- + #endif	
- + 
- + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21) 
- + extern asmlinkage long sys_getdents(unsigned int fd, struct linux_dirent __user *dirent,unsigned int count);	
- + extern asmlinkage long sys_newlstat(char __user *filename,struct stat __user *statbuf);	
- + extern asmlinkage long sys_rmdir(const char __user *pathname);
- + extern asmlinkage long sys_mkdir(const char __user *pathname, int mode);
- + extern asmlinkage long sys_rename(const char __user * oldname, const char __user * newname);
- + extern asmlinkage long sys_chmod(const char __user *filename, mode_t mode);
- + extern asmlinkage long sys_chown(const char __user *filename,uid_t user, gid_t group);
- + extern asmlinkage long sys_unlink(const char __user *pathname);
- + #endif	
- + 
- + int ctexdbg_sprit_path(char *path)
- + {
- + 	int len,i;
- + 	len = strlen(path);
- + 	for(i=len-1;i>=0;i--){
- + 		if(path[i] == '/'){
- + 			return i;
- + 		}
- + 	}
- + 	return -1;
- + }
- + 
- + /* tempolaly file write and syncing inode... */
- + void ctexdbg_temp_sync(char *path)
- + {
- + 	int fdds;
- + 	int pathsprit;
- + 	char readdata[10];
- + 	char tmppathname[NAME_MAX];
- + 
- + 	pathsprit = ctexdbg_sprit_path(path);
- + 	if(pathsprit == -1){
- + 		return;
- + 	}
- + 	strncpy(tmppathname,path,NAME_MAX);
- + 	tmppathname[pathsprit+1] = '\0';
- + 	strncat(tmppathname,CTEXDBG_FILEOP_SYNC_DUMMY_NAME,NAME_MAX);
- + 
- + 	fdds = sys_open(tmppathname, O_WRONLY|O_CREAT|O_TRUNC, S_IRWXU | S_IRWXG | S_IRWXO);		
- + 	if(fdds < 0){
- + 		return;
- + 	}
- + 	
- + 	sys_write(fdds,readdata,10);
- + 	sys_fsync(fdds);
- + 	sys_close(fdds);
- + 	sys_sync();
- + 
- + 	sys_unlink(tmppathname);
- + 	sys_sync();
- + 
- + 	return;
- + }
- + 
- + inline unsigned char* ctexdbg_file_writemarker(unsigned char *buf,unsigned long marker,unsigned long submarker,unsigned long er)
- + {
- + 	memcpy(buf  ,&marker,sizeof(unsigned long));
- + 	memcpy(buf+4,&submarker,sizeof(unsigned long));
- + 	memcpy(buf+8,&er,sizeof(unsigned long));
- + 	buf += 12;
- + 	return buf;
- + }
- + 
- + int ctexdbg_file_ls(char *path)
- + {
- + 	int fdds;
- + 	int readbyte;
- + 	int namelen;
- + 	unsigned long ssize;
- + 	char buff[512];
- + 	char files[512];
- + 	char *writesrc;
- + 	char *writedata;
- + 	char *writeend;
- + 	struct stat fstats;
- + 	
- + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) 
- + 	struct dirent *dirp;
- + #else
- + 	struct linux_dirent64 *dirp;
- + #endif
- + 	unsigned short t_shorts;
- + 	
- + 	writesrc = (unsigned char*)(ctexdbg_filebuf + CTEXDBG_WORKBUF_START);
- + 	
- + 	writedata = writesrc;
- + 	writeend = writesrc + CTEXDBG_WORKBUF_END;
- + 	sys_sync();
- + 	fdds = sys_open(path, O_RDONLY, 0);
- + 	if(fdds < 0){
- + 		writedata = writesrc;
- + 		ctexdbg_file_writemarker(writedata,CTEXDBG_FILE_M_LS,CTEXDBG_FILE_S_ERR_OPEN,-fdds);
- + 		ctexdbg_fileend_bp();
- + 		return 1;
- + 	}
- + 	sys_fsync(fdds);
- + 	sys_sync();
- + 	sys_close(fdds);
- + 	fdds = sys_open(path, O_RDONLY, 0);
- + 	if(fdds < 0){
- + 		writedata = writesrc;
- + 		ctexdbg_file_writemarker(writedata,CTEXDBG_FILE_M_LS,CTEXDBG_FILE_S_ERR_OPEN,-fdds);
- + 		ctexdbg_fileend_bp();
- + 		return 1;
- + 	}
- + 
- + 	memset(ctexdbg_filebuf,0,CTEXDBG_WORKBUF_SIZE);
- + 	while(1){
- + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) 
- + 		readbyte = sys_getdents(fdds,(struct dirent *)buff,512);
- + #elif LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) 
- + 		readbyte = sys_getdents(fdds,(struct linux_dirent *)buff,512);
- + #else
- + 		readbyte = sys_getdents64(fdds,(struct linux_dirent64 *)buff,512);
- + #endif
- + 		if(readbyte <= 0){
- + 			ctexdbg_filelsfull_bp();
- + 			break;
- + 		}
- + 		
- + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) 
- + 		for(dirp = (struct dirent*)&buff ; (char *)dirp < &buff[readbyte];
- + 		  dirp = (struct dirent *) ( (int)dirp + (dirp->d_reclen) ) ){
- + #else
- + 		for(dirp = (struct linux_dirent64*)&buff ; (char *)dirp < &buff[readbyte];
- + 		  dirp = (struct linux_dirent64 *) ( (int)dirp + (dirp->d_reclen) ) ){
- + #endif			  
- + 			strncpy(files,path,511); 
- + 			strncat(files,"/",1); 
- + 			strncat(files,dirp->d_name,511); 
- + 		
- + 			if(sys_newlstat(files,&fstats) == -1){
- + 				continue;
- + 			}
- + 			namelen = strlen(dirp->d_name) + 1;
- + 			ssize = namelen + 20;
- + 			if((writedata + ssize) >= writeend){
- + 				ctexdbg_filelsfull_bp();
- + 				writedata = writesrc;
- + 				memset(ctexdbg_filebuf,0,CTEXDBG_WORKBUF_SIZE);
- + 			}
- + 			memcpy(writedata,&ssize,sizeof(unsigned long));
- + 			t_shorts = (unsigned short)fstats.st_mode; memcpy(writedata+4,&t_shorts,sizeof(unsigned short));
- + 			t_shorts = (unsigned short)fstats.st_nlink; memcpy(writedata+6,&t_shorts,sizeof(unsigned short));
- + 			t_shorts = (unsigned short)fstats.st_uid; memcpy(writedata+8,&t_shorts,sizeof(unsigned short));
- + 			t_shorts = (unsigned short)fstats.st_gid; memcpy(writedata+10,&t_shorts,sizeof(unsigned short));
- + 			memcpy(writedata+12,&fstats.st_size,sizeof(unsigned long));
- + 			memcpy(writedata+16,&fstats.st_mtime,sizeof(unsigned long));
- + 			memcpy(writedata+20,dirp->d_name,namelen);
- + 			writedata += ssize;
- + 		}
- + 	}
- + 	writedata = writesrc;
- + 	ctexdbg_file_writemarker(writedata,CTEXDBG_FILE_M_LS,CTEXDBG_FILE_S_OK,0);
- + 	ctexdbg_fileend_bp();	
- + 	sys_close(fdds);
- + 	return 0;
- + }
- + 
- + /* read target fs send HOST */
- + int ctexdbg_file_read(char *path)
- + {
- + 	int fdds;
- + 	char *writesrc;	
- + 	char *writedata;
- + 	char *writeend;
- + 	unsigned long stopflag = 0;
- + 	ssize_t readfsize;
- + 	struct stat fstats;
- + 
- + 	writesrc = (unsigned char*)(ctexdbg_filebuf + CTEXDBG_WORKBUF_START);		
- + 	writedata = writesrc;
- + 	writeend = writesrc + CTEXDBG_WORKBUF_END + 1;
- + 	
- + 	fdds = sys_open(path, O_RDONLY, 0);
- + 	if(fdds < 0){
- + 		writedata = writesrc;
- + 		ctexdbg_file_writemarker(writedata,CTEXDBG_FILE_M_READ,CTEXDBG_FILE_S_ERR_OPEN,-fdds);
- + 		ctexdbg_fileend_bp();
- + 		return 1;
- + 	}
- + 
- + 	sys_fsync(fdds);
- + 	sys_sync();
- + 	
- + 	if(sys_newstat(path,&fstats) == -1){
- + 		ctexdbg_file_writemarker(writedata,CTEXDBG_FILE_M_READ,CTEXDBG_FILE_S_ERR_STAT,1);
- + 		ctexdbg_fileend_bp();
- + 		return 1;
- + 	}
- + 	/* first. send file size... */
- + 	memcpy(writedata,&(fstats.st_size),sizeof(unsigned long));	
- + 	writedata += sizeof(unsigned long);
- + 	
- + 	/* send file */
- + 	while(1){
- + 		readfsize = sys_read(fdds,writedata,writeend - writedata);
- + 		if(readfsize <= 0){
- + 			break;
- + 		}
- + 		stopflag = ctexdbg_fileread_bp();
- + 		if(stopflag != CTEXDBG_EV_FILE_READ){
- + 			/* Stopped */
- + 			break;
- + 		}
- + 		writedata = writesrc;
- + 	}
- + 	
- + 	writedata = writesrc;
- + 	if(readfsize < 0){
- + 		ctexdbg_file_writemarker(writedata,CTEXDBG_FILE_M_READ,CTEXDBG_FILE_S_ERR,-readfsize);
- + 	}else{
- + 		ctexdbg_file_writemarker(writedata,CTEXDBG_FILE_M_READ,CTEXDBG_FILE_S_OK,0);	
- + 	}
- + 	/* send end */	
- + 	ctexdbg_fileend_bp();	
- + 
- + 	sys_close(fdds);
- + 
- + 	return 0;
- + }
- + 
- + /* read HOST filedata to write target fs */
- + int ctexdbg_file_write(char *path)
- + {
- + 	int fdds;
- + 	int eot;
- + 	char *readsrc;	
- + 	char *readdata;
- + 	char *readend;
- + 	unsigned long stopflag = 0;
- + 
- + 	ssize_t writefsize;
- + 	ssize_t writersize;
- + 	ssize_t wrsize;
- + 	ssize_t wrsum;
- + 	
- + 	readsrc = (unsigned char*)(ctexdbg_filebuf + CTEXDBG_WORKBUF_START);	
- + 	readdata = readsrc;
- + 	readend = readsrc + CTEXDBG_WORKBUF_END + 1;
- + 
- + 	fdds = sys_open(path, O_WRONLY|O_CREAT|O_TRUNC, S_IRWXU | S_IRWXG | S_IRWXO);		
- + 	if(fdds < 0){
- + 		ctexdbg_file_writemarker(readdata,CTEXDBG_FILE_M_WRITE,CTEXDBG_FILE_S_ERR_OPEN,-fdds);
- + 		ctexdbg_fileend_bp();		
- + 		return 1;
- + 	}
- + 	
- + 	/* read from HOST */
- + 	stopflag = ctexdbg_filewrite_bp();
- + 	if(stopflag != CTEXDBG_EV_FILE_WRITE){
- + 		/* Stopped */
- + 		return 1;
- + 	}
- + 	readdata = readsrc;	
- + 	
- + 	wrsum = 0; eot = 0; writefsize = 0;
- + 	/* first. recv file size.... */
- + 	memcpy(&writefsize,readdata,sizeof(unsigned long));	
- + 	readdata += sizeof(unsigned long);
- + 	/* recv file */
- + 	while(1){
- + 		wrsize = readend - readdata;
- + 		if( (wrsize + wrsum) > writefsize){
- + 			wrsize = writefsize - wrsum;
- + 			eot = 1; 
- + 		}
- + 		writersize = sys_write(fdds,readdata,wrsize);
- + 		if(writersize < 0){
- + 			break;
- + 		}else if(eot == 1){
- + 			break;
- + 		}
- + 		wrsum += wrsize;
- + 		/* read from HOST */
- + 		stopflag = ctexdbg_filewrite_bp();
- + 		if(stopflag != CTEXDBG_EV_FILE_WRITE){
- + 			/* Stopped */
- + 			break;
- + 		}		
- + 		readdata = readsrc;
- + 	}
- + 	
- + 	readdata = readsrc;
- + 	if(writersize < 0){
- + 		ctexdbg_file_writemarker(readdata,CTEXDBG_FILE_M_WRITE,CTEXDBG_FILE_S_ERR,-writersize);
- + 	}else{
- + 		ctexdbg_file_writemarker(readdata,CTEXDBG_FILE_M_WRITE,CTEXDBG_FILE_S_OK,0);	
- + 	}
- + 
- + 	sys_fsync(fdds);
- + 	sys_close(fdds);
- + 	sys_sync();
- + 	ctexdbg_temp_sync(path);
- + 
- + 	/* send end */	
- + 	ctexdbg_fileend_bp();	
- + 
- + 	return 0;
- + }
- + 
- + int ctexdbg_file_rmdir(char *path)
- + {
- + 	char *writesrc;
- + 	char *writedata;
- + 	int ret;
- + 	
- + 	writesrc = (unsigned char*)(ctexdbg_filebuf + CTEXDBG_WORKBUF_START);	
- + 	writedata = writesrc;
- + 	if((ret = sys_rmdir(path)) < 0){
- + 		ctexdbg_file_writemarker(writedata,CTEXDBG_FILE_M_RMDIR,CTEXDBG_FILE_S_ERR,-ret);
- + 	}else{
- + 		ctexdbg_file_writemarker(writedata,CTEXDBG_FILE_M_RMDIR,CTEXDBG_FILE_S_OK,0);
- + 	}
- + 
- + 	sys_sync();
- + 
- + 	ctexdbg_fileend_bp();	
- + 	return 0;
- + }
- + 
- + int ctexdbg_file_mkdir(char *path)
- + {
- + 	char *writesrc;
- + 	char *writedata;
- + 	int ret;
- + 
- + 	writesrc = (unsigned char*)(ctexdbg_filebuf + CTEXDBG_WORKBUF_START);	
- + 	writedata = writesrc;	
- + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) 
- + 	if((ret = sys_mkdir(path)) < 0){
- + #else
- + 	if((ret = sys_mkdir(path,0777)) < 0){
- + #endif	
- + 		ctexdbg_file_writemarker(writedata,CTEXDBG_FILE_M_MKDIR,CTEXDBG_FILE_S_ERR,-ret);
- + 	}else{
- + 		ctexdbg_file_writemarker(writedata,CTEXDBG_FILE_M_MKDIR,CTEXDBG_FILE_S_OK,0);
- + 	}
- + 	sys_sync();
- + 	ctexdbg_temp_sync(path);
- + 	ctexdbg_fileend_bp();	
- + 	sys_sync();
- + 
- + 	return 0;
- + }
- + 
- + int ctexdbg_file_rename(char *path)
- + {
- + 	char *writesrc;
- + 	char *writedata;
- + 	int ret;
- + 
- + 	/* new path follows the old path in the pointer */
- + 	/* get a pointer to the new name */
- + 	char *new_name = path + strlen(path) + 1;
- + 
- + 	writesrc = (unsigned char*)(ctexdbg_filebuf + CTEXDBG_WORKBUF_START);	
- + 	writedata = writesrc;
- + 	if((ret = sys_rename(path,new_name)) < 0){
- + 		ctexdbg_file_writemarker(writedata,CTEXDBG_FILE_M_MKDIR,CTEXDBG_FILE_S_ERR,-ret);
- + 	}else{
- + 		ctexdbg_file_writemarker(writedata,CTEXDBG_FILE_M_MKDIR,CTEXDBG_FILE_S_OK,0);
- + 	}
- + 	sys_sync();
- + 
- + 	ctexdbg_fileend_bp();	
- + 	return 0;
- + }
- + 
- + int ctexdbg_file_chmod(char *path)
- + {
- + 	char *writesrc;
- + 	char *writedata;
- + 	char *filepath;
- + 	int ret;
- + 
- + 	/* copy attribute */
- + 	mode_t attr;
- + 	memcpy(&attr,path,4);
- + 	
- + 	/* get a pointer to the filename */
- + 	filepath = path + 4;
- + 		
- + 	writesrc = (unsigned char*)(ctexdbg_filebuf + CTEXDBG_WORKBUF_START);	
- + 	writedata = writesrc;	
- + 	if((ret = sys_chmod(filepath,attr)) < 0){
- + 		ctexdbg_file_writemarker(writedata,CTEXDBG_FILE_M_MKDIR,CTEXDBG_FILE_S_ERR,-ret);
- + 	}else{
- + 		ctexdbg_file_writemarker(writedata,CTEXDBG_FILE_M_MKDIR,CTEXDBG_FILE_S_OK,0);
- + 	}
- + 	sys_sync();
- + 
- + 	ctexdbg_fileend_bp();	
- + 	return 0;
- + }
- + 
- + int ctexdbg_file_chown(char *path)
- + {
- + 	char *writesrc;
- + 	char *writedata;
- + 	char *filepath;
- + 	int ret;
- + 	uid_t grp_id;
- + 	
- + 	/* copy owner ID */
- + 	uid_t own_id;
- + 	memcpy(&own_id,path,4);
- + 	
- + 	/* copy group ID */
- + 	/* copy owner ID */
- + 	memcpy(&grp_id,path+4,4);
- + 	
- + 	/* get a pointer to the filename */
- + 	filepath = path + 8;
- + 
- + 	writesrc = (unsigned char*)(ctexdbg_filebuf + CTEXDBG_WORKBUF_START);	
- + 	writedata = writesrc;			
- + 	if((ret = sys_chown(filepath, own_id, grp_id)) < 0){
- + 		ctexdbg_file_writemarker(writedata,CTEXDBG_FILE_M_MKDIR,CTEXDBG_FILE_S_ERR,-ret);
- + 	}else{
- + 		ctexdbg_file_writemarker(writedata,CTEXDBG_FILE_M_MKDIR,CTEXDBG_FILE_S_OK,0);
- + 	}
- + 	sys_sync();
- + 
- + 	ctexdbg_fileend_bp();	
- + 	return 0;
- + }
- + 
- + int ctexdbg_file_delfile(char *path)
- + {
- + 	char *writesrc;
- + 	char *writedata;
- + 	int ret;
- + 	
- + 	writesrc = (unsigned char*)(ctexdbg_filebuf + CTEXDBG_WORKBUF_START);	
- + 	writedata = writesrc;
- + 	if((ret = sys_unlink(path)) < 0){
- + 		ctexdbg_file_writemarker(writedata,CTEXDBG_FILE_M_DELFILE,CTEXDBG_FILE_S_ERR,-ret);
- + 	}else{
- + 		ctexdbg_file_writemarker(writedata,CTEXDBG_FILE_M_DELFILE,CTEXDBG_FILE_S_OK,0);
- + 	}	
- + 	sys_sync();
- + 
- + 	ctexdbg_fileend_bp();
- + 	return 0;
- + }
- + 
- diff -crN linux-3.2.1_o/kernel/ctextrc.c linux-3.2.1_ctex/kernel/ctextrc.c
- *** linux-3.2.1_o/kernel/ctextrc.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1_ctex/kernel/ctextrc.c	2013-05-24 10:28:33.990561270 +0900
- ***************
- *** 0 ****
- --- 1,444 ----
- + /*
- +  * linux/kernel/ctextrc.c
- +  *
- +  * (C) Copyright 2004 - Computex co.,ltd.
- +  *
- +  * Linux trace toolkit support
- +  *
- +  * -- version info --------------------------------------------------
- +  * 
- +  * version 0013- 2008/05/xx		reborn
- +  *
- +  * -------------------------------------------------------------------
- +  *
- +  */
- + 
- +  /* Necessary includes */
- + #include <linux/kernel.h>
- + #include <linux/version.h>
- + 
- + #include <linux/fs.h>
- + #include <linux/sched.h>
- + #include <linux/slab.h>
- + #include <linux/ctype.h>
- + #include <linux/pagemap.h>
- + #include <linux/string.h>
- + #include <linux/time.h>
- + #include <linux/vmalloc.h>
- + #include <linux/mm.h>
- + 
- + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) 
- + #include <linux/wrapper.h>
- + #else
- + #include <linux/namei.h>
- + #endif
- + 
- + #include <linux/vmalloc.h>
- + #include <linux/interrupt.h>
- + #ifdef CONFIG_ARM
- + #include <asm/irq.h>
- + #include <asm/mach/irq.h>
- + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) 
- + #include <asm/arch/irq.h>
- + #endif
- + #else
- + #include <linux/irq.h>
- + #endif
- + 
- + #include <linux/ctexdbg.h>  /* definitions */
- + 
- + #include <asm/io.h>
- + #include <asm/current.h>
- + #include <asm/uaccess.h>
- + #include <asm/bitops.h>
- + 
- + #include <linux/ctextrc.h>
- + 
- + #define CTEXTRC_DEFAULT_BUF_SIZE 50000				/* buffer size*/
- + 
- + extern cdbtrc_bufpos	ctexdbg_tracebufpos;		/* buffer position */
- + 
- + static spinlock_t             sSpinLock;             /* Spinlock in order to lock kernel */
- + static uint32_t               sBufSize;              /* Buffer sizes */
- + static uint32_t               sAllocSize;            /* Size of buffers allocated */
- + 
- + uint32_t		ctexdbg_TracerSize = CTEXTRC_DEFAULT_BUF_SIZE;	/* trace buffer size */
- + int			ctexdbg_traceend = 0; 							/* TRACE end flag */
- + int			ctexdbg_tracestop = 1;	 						/* buffer full stop enable */
- + 												/* 0 : stop    (default) */
- + 												/* 1 : nonstop (one shot) */
- + //#ifndef CONFIG_ARM
- + #define CTEXDBG_TRACER_BUFSTATIC
- + //#endif /* NOTARM */
- + 
- + #ifdef CTEXDBG_TRACER_BUFSTATIC
- + static char ctexdbg_sTraceBuffer[CTEXTRC_DEFAULT_BUF_SIZE+2];
- + #endif /* CTEXDBG_TRACER_BUFSTATIC */
- + 
- + /* Size of statically defined events */
- + static int sEventStructSize[CTX_EV_MAX + 1] =
- + {
- + 	0,
- + 	sizeof(ctx_syscall_entry),
- + 	0,				/* SYSCALL_EXIT */
- + 	sizeof(ctx_trap_entry),
- + 	0,				/* TRAP_EXIT */
- + 	sizeof(ctx_irq_entry),
- + 	0,				/* IRQ_EXIT */
- + 	sizeof(ctx_schedchange),
- + 	0,				/* KERNEL_TIMER */
- + 	sizeof(ctx_soft_irq),
- + 	sizeof(ctx_process),
- + 	sizeof(ctx_file_system),
- + 	sizeof(ctx_timer),
- + 	sizeof(ctx_memory),
- + 	sizeof(ctx_socket),
- + 	sizeof(ctx_ipc),
- + 	sizeof(ctx_network),
- + 	0,
- +  	0
- + };
- + 
- + typedef struct _tag_cdbtrc_mask_type
- + {
- + 	uint32_t event_num;				/* mask event ID : 0 = end */
- + 	uint32_t event_denyall;			/* 0 :subevent not 1:subevent use */
- + 	uint32_t subevent_num;			/* syscallnum or mask*/
- + }cdbtrc_mask_type;
- + 
- + cdbtrc_mask_type cdbtrc_mask_table[CTEXTRC_MASK_SIZE];
- + 
- + 
- + 
- + /* ------------------------ memry allocate --------------------------------------------- */
- + 
- + #ifndef FIX_SIZE
- + #define FIX_SIZE(x) (((x) - 1) & PAGE_MASK) + PAGE_SIZE /* This inspired by rtai/shmem */
- + #endif
- + 
- + #define BKK(x) ((x) << PAGE_SHIFT)
- + 
- + static void ctexdbg_tracer_cleanbuf(void)
- + {
- + 	memset(ctexdbg_tracebufpos.sEventBuf,CTX_EV_BUFFER_END,sBufSize);
- + }
- + 
- + int ctexdbg_tracer_set_buffer_size(int pmSize)
- + {
- + #ifdef CTEXDBG_TRACER_BUFSTATIC
- +   /* clean */
- +   
- +   ctexdbg_tracebufpos.sEventBuf = NULL;
- +   ctexdbg_tracebufpos.sEventWritPos = NULL;
- +   ctexdbg_tracebufpos.sEventReadPos = NULL;
- +   ctexdbg_tracebufpos.sEventWritLimit = NULL;
- +   ctexdbg_tracebufpos.sEventBufDir = 0;
- +   
- +   ctexdbg_tracebufpos.sEventBuf = ctexdbg_sTraceBuffer;
- +  
- +   sBufSize = CTEXTRC_DEFAULT_BUF_SIZE;
- +   sAllocSize = CTEXTRC_DEFAULT_BUF_SIZE;
- + 
- + #else /* CTEXDBG_TRACER_BUFSTATIC */
- +   int	lSizeAlloc;     /* Size to be allocated */
- +   int	lSizeMax;	/* Max alloc size */
- +   struct sysinfo i;	/* memory size */
- + 
- +   /* Set size to allocate (= pmSize) and fix it's size to be on a page boundary */
- +   lSizeAlloc = FIX_SIZE(pmSize);
- + 
- +   /* Free the current buffers, if any */
- +   if(ctexdbg_tracebufpos.sEventBuf != NULL)
- +     kfree(ctexdbg_tracebufpos.sEventBuf);
- + 
- +   /* clean */
- +   ctexdbg_tracebufpos.sEventBuf = NULL;
- +   ctexdbg_tracebufpos.sEventWritPos = NULL;
- +   ctexdbg_tracebufpos.sEventReadPos = NULL;
- +   ctexdbg_tracebufpos.sEventWritLimit = NULL;
- +   ctexdbg_tracebufpos.sEventBufDir = 0;
- + 			
- +   /* calclation sizeing...*/
- +   si_meminfo(&i);
- +   lSizeMax = BKK(i.freeram) - 100000;
- +   if(lSizeAlloc >= lSizeMax){
- +   	/* Over memory ... return ERROR */
- +     return 1;
- +   }
- + 
- +   /* Allocate space for the tracing buffers */
- +   if((ctexdbg_tracebufpos.sEventBuf = (char*) kmalloc(lSizeAlloc,GFP_KERNEL|__GFP_NORETRY)) == NULL){
- +     ctexdbg_tracebufpos.sEventBuf = NULL;	  
- +     return 1;
- +   }
- + 	
- +   /* Remember the size set */
- +   sBufSize = pmSize;
- +   sAllocSize = lSizeAlloc;
- + 
- + #endif /* CTEXDBG_TRACER_BUFSTATIC */ 
- + 
- +   /* Set the read and write buffers */
- +   ctexdbg_tracebufpos.sEventWritPos = ctexdbg_tracebufpos.sEventBuf;
- +    
- +   /* Set write limit */
- +   ctexdbg_tracebufpos.sEventWritLimit = ctexdbg_tracebufpos.sEventWritPos + sBufSize;
- + 
- +   /* Set write position */
- +   ctexdbg_tracebufpos.sEventReadPos = ctexdbg_tracebufpos.sEventBuf;
- +   
- +   /* All is OK */
- +   return 0;
- + }
- + 
- + 
- + #define write_to_buffer(DEST, SRC, SIZE) \
- + do{ \
- + 	memcpy(DEST, SRC, SIZE); \
- + 	DEST += SIZE; \
- + } while(0);
- + 
- + int ctexdbg_tracer_start(uint32_t nbuffersize,uint32_t oneshot)
- + {
- + 	unsigned long int   lFlags;                   /* CPU flags for lock */
- + 	
- + 	if(ctexdbg_traceuse == 1) return 0;
- + 	
- + 	/* Lock the kernel */
- + 	spin_lock_irqsave(&sSpinLock, lFlags);
- + 	
- + 	ctexdbg_tracestop = oneshot;
- + 
- + #ifdef CTEXDBG_TRACER_BUFSTATIC
- + 	nbuffersize = CTEXTRC_DEFAULT_BUF_SIZE;
- + #endif /* CTEXDBG_TRACER_BUFSTATIC */
- + 
- + 	if(ctexdbg_tracebufpos.sEventBuf == NULL){
- + 		ctexdbg_TracerSize = nbuffersize;	
- + 		if(ctexdbg_tracer_set_buffer_size(ctexdbg_TracerSize) != 0){
- + 			ctexdbg_traceend = 1;
- + 			ctexdbg_traceuse = 0;
- + 			spin_unlock_irqrestore(&sSpinLock, lFlags);
- + 			return 1;
- + 		}
- + 	}else if(ctexdbg_TracerSize != nbuffersize){
- + 		ctexdbg_TracerSize = nbuffersize;
- + 		if(ctexdbg_tracer_set_buffer_size(ctexdbg_TracerSize) != 0){
- + 			ctexdbg_traceend = 1;
- + 			ctexdbg_traceuse = 0;
- + 			spin_unlock_irqrestore(&sSpinLock, lFlags);
- + 			return 1;
- + 		}
- + 	}else{
- + 		ctexdbg_tracebufpos.sEventWritPos = ctexdbg_tracebufpos.sEventBuf;	
- + 		ctexdbg_tracebufpos.sEventReadPos = ctexdbg_tracebufpos.sEventBuf;
- + 		ctexdbg_tracebufpos.sEventBufDir = 0;
- + 	}
- + 	/* clean buf */
- + 	ctexdbg_tracer_cleanbuf();
- + 	/* enable something events ... */
- + 	spin_unlock_irqrestore(&sSpinLock, lFlags);
- + 	
- + 	/* We can start tracing */
- + 	ctexdbg_traceuse = 1;
- + 	ctexdbg_traceend = 0;	
- + 	return 0;
- + }
- + 
- + 
- + void ctexdbg_tracer_stop(void)
- + {
- + 	if(ctexdbg_traceuse == 0) return;
- + 	ctexdbg_traceend = 1;
- + 	ctexdbg_traceuse = 0;
- + }
- + 
- + static void ctexdbg_trace_switch_buffers(void)
- + {
- + 	if(ctexdbg_tracestop == 0){
- + 		/* stop */
- + 		ctexdbg_lttfull_bp();
- + 		ctexdbg_tracebufpos.sEventBufDir = 0;
- + 		ctexdbg_tracebufpos.sEventReadPos = ctexdbg_tracebufpos.sEventBuf;
- + 		ctexdbg_tracebufpos.sEventWritPos = ctexdbg_tracebufpos.sEventBuf;
- + 		return;
- + 	}
- + 	
- + 	/* this no stop mode set dir 1 */
- + 	if(ctexdbg_tracebufpos.sEventBufDir == 0){
- + 		ctexdbg_tracebufpos.sEventBufDir = 1;
- + 	}
- + 	
- + 	memset(ctexdbg_tracebufpos.sEventWritPos,0xFF,
- + 			ctexdbg_tracebufpos.sEventWritLimit - ctexdbg_tracebufpos.sEventWritPos);		
- + 	
- + 	ctexdbg_tracebufpos.sEventWritPos = ctexdbg_tracebufpos.sEventBuf;	
- + 	return;
- + }
- + 
- + /* Check event mask (v006 later)*/
- + int ctexdbg_tracer_hitmask(uint8_t pmEventID,void* pmEventStruct)
- + {
- + 	int i;
- + 	int ret = 0;
- + 	
- + 	for(i=0;i < CTEXTRC_MASK_SIZE;i++){
- + 		if(cdbtrc_mask_table[i].event_num == 0) break;
- + 		if(cdbtrc_mask_table[i].event_num != pmEventID) continue;
- + 		
- + 		if(cdbtrc_mask_table[i].event_denyall == 0){
- + 			/* subevent not use ... HIT mask! */
- + 			return 1;
- + 		}
- + 		switch(pmEventID){
- + 		case CTX_EV_SYSCALL_ENTRY:
- + 			if(cdbtrc_mask_table[i].subevent_num == ((ctx_syscall_entry*) pmEventStruct)->syscall_id){
- + 				return 1;
- + 			}
- + 			break;
- + 		case CTX_EV_TRAP_ENTRY:
- + 			if(cdbtrc_mask_table[i].subevent_num == ((ctx_trap_entry*) pmEventStruct)->trap_id){
- + 				return 1;
- + 			}
- + 			break;
- + 		case CTX_EV_IRQ_ENTRY:
- + 			if(cdbtrc_mask_table[i].subevent_num == ((ctx_irq_entry*) pmEventStruct)->irq_id){
- + 				return 1;
- + 			}
- + 			break;
- + 		case CTX_EV_SOFT_IRQ: 
- + 			if(cdbtrc_mask_table[i].subevent_num == ((ctx_soft_irq*) pmEventStruct)->event_sub_id){
- + 				return 1;
- + 			}
- + 			break;
- + 		case CTX_EV_PROCESS: 
- + 			if(cdbtrc_mask_table[i].subevent_num == ((ctx_process*) pmEventStruct)->event_sub_id){
- + 				return 1;
- + 			}
- + 			break;
- + 		case CTX_EV_FILE_SYSTEM: 
- + 			if(cdbtrc_mask_table[i].subevent_num == ((ctx_file_system*) pmEventStruct)->event_sub_id){
- + 				return 1;
- + 			}
- + 			break;
- + 		case CTX_EV_TIMER: 
- + 			if(cdbtrc_mask_table[i].subevent_num == ((ctx_timer*) pmEventStruct)->event_sub_id){
- + 				return 1;
- + 			}
- + 			break;
- + 		case CTX_EV_MEMORY: 
- + 			if(cdbtrc_mask_table[i].subevent_num == ((ctx_memory*) pmEventStruct)->event_sub_id){
- + 				return 1;
- + 			}
- + 			break;
- + 		case CTX_EV_SOCKET: 
- + 			if(cdbtrc_mask_table[i].subevent_num == ((ctx_socket*) pmEventStruct)->event_sub_id){
- + 				return 1;
- + 			}
- + 			break;
- + 		case CTX_EV_IPC: 
- + 			if(cdbtrc_mask_table[i].subevent_num == ((ctx_ipc*) pmEventStruct)->event_sub_id){
- + 				return 1;
- + 			}
- + 			break;
- + 		case CTX_EV_NETWORK: 
- + 			if(cdbtrc_mask_table[i].subevent_num == ((ctx_network*) pmEventStruct)->event_sub_id){
- + 				return 1;
- + 			}
- + 			break;
- + 		}
- + 	}
- + 
- + 	return ret;
- + }
- + 
- + 
- + 
- + /* ------------------------------ tracer ------------------------------------------ */
- + void ctexdbg_tracer(uint8_t pmEventID,void* pmEventStruct)
- + {
- + 	int                 lVarDataLen = 0;          /* Length of variable length data to be copied, if any */
- + 	void*               lVarDataBeg = NULL;       /* Begining of variable length data to be copied */
- + 	uint16_t            lCPUID;                   /* CPUID of currently runing process */
- + 	uint16_t            lDataSize;                /* Size of tracing data */
- + 	struct timeval      lTime;                    /* Event time */
- + 	unsigned long int   lFlags;                   /* CPU flags for lock */
- + 	char*               lWritPos;
- + 	
- + 	if(ctexdbg_traceuse == 0) return;
- + 	
- + 	switch(pmEventID){
- + 	case CTX_EV_START:
- + 	case CTX_EV_BUFFER_START:
- + 	case CTX_EV_BUFFER_END:
- + 		return;
- + 		break;
- + 	}
- + 	
- + 	/* check mask */
- + 	if(ctexdbg_tracer_hitmask(pmEventID, pmEventStruct) != 0){
- + 		return;
- + 	}
- + 
- + 	/* Compute size of tracing data */
- + 	lDataSize = sizeof(pmEventID) + sizeof(lCPUID) + sizeof(lTime) + sEventStructSize[pmEventID] +sizeof(lDataSize);
- + 	
- + 	/* Some events have variable length */
- + 	if(pmEventID == CTX_EV_FILE_SYSTEM){
- + 	/* Is there a file name in this */
- + 		if((((ctx_file_system*) pmEventStruct)->event_sub_id == CTX_EV_FILE_SYSTEM_EXEC)
- + 		|| (((ctx_file_system*) pmEventStruct)->event_sub_id == CTX_EV_FILE_SYSTEM_OPEN)){
- + 			/* Remember the string's begining and update size variables */
- + 			lVarDataBeg = ((ctx_file_system*) pmEventStruct)->file_name;
- + 			lVarDataLen = ((ctx_file_system*) pmEventStruct)->event_data2 + 1;
- + 			lDataSize += (uint16_t) lVarDataLen;
- + 		}
- + 	}
- + 	lCPUID = smp_processor_id();
- + 	/* Get the time of the event */
- + 	do_gettimeofday(&lTime);
- + 
- + 	/* The following time calculations have to be done within the spinlock because
- + 		otherwise the event order could be inverted. */
- + 	
- + 	/* Lock the kernel */
- + 	spin_lock_irqsave(&sSpinLock, lFlags);
- + 	
- + 	/* Is there enough space left in the write buffer */
- + 	if( (ctexdbg_tracebufpos.sEventWritPos + lDataSize) >= ctexdbg_tracebufpos.sEventWritLimit){
- + 		/* Switch buffers */
- + 		ctexdbg_trace_switch_buffers();
- + 	}
- + 
- + 	lWritPos = ctexdbg_tracebufpos.sEventWritPos;
- + 	/* Write event type to tracing buffer */
- + 	write_to_buffer(lWritPos,&pmEventID,sizeof(pmEventID));
- + 
- + 	/* Write the CPUID */
- + 	write_to_buffer(lWritPos,&lCPUID,sizeof(lCPUID));
- + 		
- + 	/* Write event time to tracing buffer */
- + 	write_to_buffer(lWritPos,&lTime,sizeof(lTime));
- + 
- + 	/* Write event structure */
- + 	write_to_buffer(lWritPos,pmEventStruct,sEventStructSize[pmEventID]);
- + 		
- + 	/* Write string if any */
- + 	if(lVarDataBeg != NULL){
- + 		write_to_buffer(lWritPos,lVarDataBeg,lVarDataLen);
- + 	}
- + 			
- + 	/* Write the length of the event description */
- + 	write_to_buffer(lWritPos,&lDataSize,sizeof(lDataSize));
- + 
- + 	ctexdbg_tracebufpos.sEventWritPos = lWritPos;
- + 	
- + 	spin_unlock_irqrestore(&sSpinLock, lFlags);
- + }
- + 
- + 
- + void ctexdbg_tracer_init(void)
- + {
- + 	spin_lock_init(& sSpinLock);	
- + 	memset(cdbtrc_mask_table,0,sizeof(cdbtrc_mask_table));
- + }
- diff -crN linux-3.2.1_o/kernel/exit.c linux-3.2.1_ctex/kernel/exit.c
- *** linux-3.2.1_o/kernel/exit.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1_ctex/kernel/exit.c	2013-05-24 10:28:34.061534497 +0900
- ***************
- *** 51,56 ****
- --- 51,57 ----
-   #include <trace/events/sched.h>
-   #include <linux/hw_breakpoint.h>
-   #include <linux/oom.h>
- + #include <linux/ctexdbg.h>
-   
-   #include <asm/uaccess.h>
-   #include <asm/unistd.h>
- ***************
- *** 971,982 ****
- --- 972,989 ----
-   	tsk->exit_code = code;
-   	taskstats_exit(tsk, group_dead);
-   
- + #if defined(CONFIG_CTEX_DBGLIB)		
- + 	ctexdbg_process_exit();
- + #endif	
-   	exit_mm(tsk);
-   
-   	if (group_dead)
-   		acct_process();
-   	trace_sched_process_exit(tsk);
-   
- + #ifdef CONFIG_CTEX_TRACE
- + 	ctx_ev_process_exit();
- + #endif
-   	exit_sem(tsk);
-   	exit_shm(tsk);
-   	exit_files(tsk);
- ***************
- *** 1690,1695 ****
- --- 1697,1705 ----
-   
-   	trace_sched_process_wait(wo->wo_pid);
-   
- + #ifdef CONFIG_CTEX_TRACE
- + 	ctx_ev_process(CTX_EV_PROCESS_WAIT, pid_nr(wo->wo_pid), 0);
- + #endif
-   	init_waitqueue_func_entry(&wo->child_wait, child_wait_callback);
-   	wo->child_wait.private = current;
-   	add_wait_queue(&current->signal->wait_chldexit, &wo->child_wait);
- diff -crN linux-3.2.1_o/kernel/fork.c linux-3.2.1_ctex/kernel/fork.c
- *** linux-3.2.1_o/kernel/fork.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1_ctex/kernel/fork.c	2013-05-24 10:28:34.082498202 +0900
- ***************
- *** 66,71 ****
- --- 66,72 ----
-   #include <linux/user-return-notifier.h>
-   #include <linux/oom.h>
-   #include <linux/khugepaged.h>
- + #include <linux/ctexdbg.h>
-   
-   #include <asm/pgtable.h>
-   #include <asm/pgalloc.h>
- ***************
- *** 1512,1517 ****
- --- 1513,1521 ----
-   		struct completion vfork;
-   
-   		trace_sched_process_fork(current, p);
- + #ifdef CONFIG_CTEX_TRACE
- + 		ctx_ev_process(CTX_EV_PROCESS_FORK,p->pid,0);
- + #endif
-   
-   		nr = task_pid_vnr(p);
-   
- ***************
- *** 1533,1538 ****
- --- 1537,1546 ----
-   		 */
-   		p->flags &= ~PF_STARTING;
-   
- + #ifdef CONFIG_CTEX_DBGLIB
- + 		ctexdbg_forking(p,clone_flags,stack_start);
- + #endif /* CONFIG_CTEX_DBGLIB */	
- + 
-   		wake_up_new_task(p);
-   
-   		/* forking complete and child started to run, tell ptracer */
- diff -crN linux-3.2.1_o/kernel/itimer.c linux-3.2.1_ctex/kernel/itimer.c
- *** linux-3.2.1_o/kernel/itimer.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1_ctex/kernel/itimer.c	2013-05-24 10:28:34.090556769 +0900
- ***************
- *** 13,18 ****
- --- 13,19 ----
-   #include <linux/posix-timers.h>
-   #include <linux/hrtimer.h>
-   #include <trace/events/timer.h>
- + #include <linux/ctexdbg.h>
-   
-   #include <asm/uaccess.h>
-   
- ***************
- *** 122,128 ****
-   {
-   	struct signal_struct *sig =
-   		container_of(timer, struct signal_struct, real_timer);
- ! 
-   	trace_itimer_expire(ITIMER_REAL, sig->leader_pid, 0);
-   	kill_pid_info(SIGALRM, SEND_SIG_PRIV, sig->leader_pid);
-   
- --- 123,131 ----
-   {
-   	struct signal_struct *sig =
-   		container_of(timer, struct signal_struct, real_timer);
- ! #ifdef CONFIG_CTEX_TRACE
- ! 	ctx_ev_timer(CTX_EV_TIMER_EXPIRED,0,0,0);
- ! #endif
-   	trace_itimer_expire(ITIMER_REAL, sig->leader_pid, 0);
-   	kill_pid_info(SIGALRM, SEND_SIG_PRIV, sig->leader_pid);
-   
- ***************
- *** 200,206 ****
-   	if (!timeval_valid(&value->it_value) ||
-   	    !timeval_valid(&value->it_interval))
-   		return -EINVAL;
- ! 
-   	switch (which) {
-   	case ITIMER_REAL:
-   again:
- --- 203,211 ----
-   	if (!timeval_valid(&value->it_value) ||
-   	    !timeval_valid(&value->it_interval))
-   		return -EINVAL;
- ! #ifdef CONFIG_CTEX_TRACE
- ! 	ctx_ev_timer(CTX_EV_TIMER_SETITIMER,which,(ulong)&value->it_interval,(ulong)&value->it_value);
- ! #endif
-   	switch (which) {
-   	case ITIMER_REAL:
-   again:
- diff -crN linux-3.2.1_o/kernel/Makefile linux-3.2.1_ctex/kernel/Makefile
- *** linux-3.2.1_o/kernel/Makefile	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1_ctex/kernel/Makefile	2013-05-24 10:28:34.118522940 +0900
- ***************
- *** 109,114 ****
- --- 109,118 ----
-   obj-$(CONFIG_PADATA) += padata.o
-   obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
-   obj-$(CONFIG_JUMP_LABEL) += jump_label.o
- + obj-$(CONFIG_CTEX_DBGLIB) += ctexdbg.o
- + obj-$(CONFIG_CTEX_DBGLIB) += ctexevt.o
- + obj-$(CONFIG_CTEX_DBGLIB) += ctexfile.o
- + obj-$(CONFIG_CTEX_TRACE) += ctextrc.o
-   
-   ifneq ($(CONFIG_SCHED_OMIT_FRAME_POINTER),y)
-   # According to Alan Modra <alan@linuxcare.com.au>, the -fno-omit-frame-pointer is
- diff -crN linux-3.2.1_o/kernel/module.c linux-3.2.1_ctex/kernel/module.c
- *** linux-3.2.1_o/kernel/module.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1_ctex/kernel/module.c	2013-05-24 10:28:34.126609134 +0900
- ***************
- *** 58,63 ****
- --- 58,64 ----
-   #include <linux/jump_label.h>
-   #include <linux/pfn.h>
-   #include <linux/bsearch.h>
- + #include <linux/ctexdbg.h>
-   
-   #define CREATE_TRACE_POINTS
-   #include <trace/events/module.h>
- ***************
- *** 661,666 ****
- --- 662,670 ----
-   	struct module_use *use, *tmp;
-   
-   	mutex_lock(&module_mutex);
- + #ifdef CONFIG_CTEX_DBGLIB
- + 	ctexdbg_module_remove(mod);
- + #endif
-   	list_for_each_entry_safe(use, tmp, &mod->target_list, target_list) {
-   		struct module *i = use->target;
-   		DEBUGP("%s unusing %s\n", mod->name, i->name);
- ***************
- *** 2794,2799 ****
- --- 2798,2807 ----
-   	percpu_modcopy(mod, (void *)info->sechdrs[info->index.pcpu].sh_addr,
-   		       info->sechdrs[info->index.pcpu].sh_size);
-   
- + #ifdef CONFIG_CTEX_DBGLIB
- + 	ctexdbg_module_install(mod, info->hdr, info->sechdrs, info->secstrings, info->index.sym, info->index.str);
- + #endif
- + 
-   	/* Setup kallsyms-specific fields. */
-   	add_kallsyms(mod, info);
-   
- ***************
- *** 2980,2986 ****
- --- 2988,3001 ----
-   	do_mod_ctors(mod);
-   	/* Start the module */
-   	if (mod->init != NULL)
- + #ifdef CONFIG_CTEX_DBGLIB
- + 	{
- + 		ctexdbg_module_init(mod);
- + 		ret = do_one_initcall(mod->init);
- + 	}
- + #else
-   		ret = do_one_initcall(mod->init);
- + #endif /* CONFIG_CTEX_DBGLIB */		
-   	if (ret < 0) {
-   		/* Init routine failed: abort.  Try to protect us from
-                      buggy refcounters. */
- diff -crN linux-3.2.1_o/kernel/sched.c linux-3.2.1_ctex/kernel/sched.c
- *** linux-3.2.1_o/kernel/sched.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1_ctex/kernel/sched.c	2013-05-24 10:33:23.736177000 +0900
- ***************
- *** 72,77 ****
- --- 72,79 ----
-   #include <linux/ftrace.h>
-   #include <linux/slab.h>
-   #include <linux/init_task.h>
- + #include <linux/ctexdbg.h>
- + #include <asm/ctexdbg_arch.h>
-   
-   #include <asm/tlb.h>
-   #include <asm/irq_regs.h>
- ***************
- *** 2456,2461 ****
- --- 2458,2466 ----
-   		 */
-   		rq = task_rq_lock(p, &flags);
-   		trace_sched_wait_task(p);
- + #ifdef CONFIG_CTEX_TRACE
- + 		ctx_ev_process(CTX_EV_PROCESS_WAIT, p->pid, 0);
- + #endif
-   		running = task_running(rq, p);
-   		on_rq = p->on_rq;
-   		ncsw = 0;
- ***************
- *** 2659,2664 ****
- --- 2664,2672 ----
-   	trace_sched_wakeup(p, true);
-   	check_preempt_curr(rq, p, wake_flags);
-   
- + #ifdef CONFIG_CTEX_TRACE
- + 	ctx_ev_process(CTX_EV_PROCESS_WAKEUP, p->pid, p->state);
- + #endif
-   	p->state = TASK_RUNNING;
-   #ifdef CONFIG_SMP
-   	if (p->sched_class->task_woken)
- ***************
- *** 3290,3296 ****
-   	struct mm_struct *mm, *oldmm;
-   
-   	prepare_task_switch(rq, prev, next);
- ! 
-   	mm = next->mm;
-   	oldmm = prev->active_mm;
-   	/*
- --- 3298,3306 ----
-   	struct mm_struct *mm, *oldmm;
-   
-   	prepare_task_switch(rq, prev, next);
- ! #ifdef CONFIG_CTEX_TRACE
- ! 	ctx_ev_schedchange(prev->pid,next->pid,prev->state);
- ! #endif
-   	mm = next->mm;
-   	oldmm = prev->active_mm;
-   	/*
- ***************
- *** 3320,3325 ****
- --- 3330,3338 ----
-   #ifndef __ARCH_WANT_UNLOCKED_CTXSW
-   	spin_release(&rq->lock.dep_map, 1, _THIS_IP_);
-   #endif
- + #ifdef CONFIG_CTEX_DBGLIB
- + 	ctexdbg_arch_schedchange_event(prev->pid,next->pid, next->comm);
- + #endif /* CONFIG_CTEX_DBGLIB */	
-   
-   	/* Here we just switch the register state and the stack. */
-   	switch_to(prev, next, prev);
- ***************
- *** 6273,6278 ****
- --- 6286,6295 ----
-   	if (!cpumask_test_cpu(dest_cpu, tsk_cpus_allowed(p)))
-   		goto fail;
-   
- + #ifdef CONFIG_CTEX_DBGLIB
- + 	ctexdbg_migration_check(p,src_cpu,dest_cpu);
- + #endif /* CONFIG_CTEX_DBGLIB */
- + 
-   	/*
-   	 * If we're not on a rq, the next wake-up will ensure we're
-   	 * placed properly.
- diff -crN linux-3.2.1_o/kernel/signal.c linux-3.2.1_ctex/kernel/signal.c
- *** linux-3.2.1_o/kernel/signal.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1_ctex/kernel/signal.c	2013-05-24 10:28:34.538897176 +0900
- ***************
- *** 30,35 ****
- --- 30,36 ----
-   #include <linux/nsproxy.h>
-   #define CREATE_TRACE_POINTS
-   #include <trace/events/signal.h>
- + #include <linux/ctexdbg.h>
-   
-   #include <asm/param.h>
-   #include <asm/uaccess.h>
- ***************
- *** 1168,1173 ****
- --- 1169,1177 ----
-   static int
-   specific_send_sig_info(int sig, struct siginfo *info, struct task_struct *t)
-   {
- + #ifdef CONFIG_CTEX_TRACE
- + 	ctx_ev_process(CTX_EV_PROCESS_SIGNAL, (uint32_t)sig,t->pid);
- + #endif
-   	return send_signal(sig, info, t, 0);
-   }
-   
- ***************
- *** 2241,2246 ****
- --- 2245,2262 ----
-   		if (sig_kernel_ignore(signr)) /* Default is nothing. */
-   			continue;
-   
- + #if defined(CONFIG_CTEX_DBGLIB)
- + 		if(ctexdbg_signals(signr,current->pid,regs) != 0){
- + 			goto relock;
- + 		}else{
- + 			if ( (current->pid == 1) && (signr == SIGSTOP) ){
- + 				if (ctexdbg_forcebreak(current) != 0){
- + 					goto relock;
- + 				}					
- + 			}
- + 		}
- + #endif /* CONFIG_CTEX_DBGLIB */
- + 
-   		/*
-   		 * Global init gets no signals it doesn't want.
-   		 * Container-init gets no signals it doesn't want from same
- ***************
- *** 2276,2282 ****
-   
-   				spin_lock_irq(&sighand->siglock);
-   			}
- ! 
-   			if (likely(do_signal_stop(info->si_signo))) {
-   				/* It released the siglock.  */
-   				goto relock;
- --- 2292,2302 ----
-   
-   				spin_lock_irq(&sighand->siglock);
-   			}
- ! #ifdef CONFIG_CTEX_DBGLIB
- ! 			if (ctexdbg_forcebreak(current) != 0){
- ! 				goto relock;
- ! 			}
- ! #endif /* CONFIG_CTEX_DBGLIB */
-   			if (likely(do_signal_stop(info->si_signo))) {
-   				/* It released the siglock.  */
-   				goto relock;
- diff -crN linux-3.2.1_o/kernel/softirq.c linux-3.2.1_ctex/kernel/softirq.c
- *** linux-3.2.1_o/kernel/softirq.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1_ctex/kernel/softirq.c	2013-05-24 10:32:58.290722000 +0900
- ***************
- *** 24,29 ****
- --- 24,30 ----
-   #include <linux/ftrace.h>
-   #include <linux/smp.h>
-   #include <linux/tick.h>
- + #include <linux/ctexdbg.h>
-   
-   #define CREATE_TRACE_POINTS
-   #include <trace/events/irq.h>
- ***************
- *** 297,302 ****
- --- 298,307 ----
-   	int cpu = smp_processor_id();
-   
-   	rcu_irq_enter();
- + #ifdef CONFIG_CTEX_DBGLIB
- + 	ctexdbg_checkwakeup();
- + #endif /* CONFIG_CTEX_DBGLIB */
- + 
-   	if (idle_cpu(cpu) && !in_interrupt()) {
-   		/*
-   		 * Prevent raise_softirq from needlessly waking up ksoftirqd
- diff -crN linux-3.2.1_o/Makefile linux-3.2.1_ctex/Makefile
- *** linux-3.2.1_o/Makefile	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1_ctex/Makefile	2013-05-24 10:28:34.610286839 +0900
- ***************
- *** 593,599 ****
- --- 593,603 ----
-   endif
-   
-   ifdef CONFIG_DEBUG_INFO
- + #ifdef CONFIG_CTEX_DBGLIB
- + KBUILD_CFLAGS	+= -gdwarf-2
- + #else
-   KBUILD_CFLAGS	+= -g
- + #endif
-   KBUILD_AFLAGS	+= -gdwarf-2
-   endif
-   
- diff -crN linux-3.2.1_o/mm/filemap.c linux-3.2.1_ctex/mm/filemap.c
- *** linux-3.2.1_o/mm/filemap.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1_ctex/mm/filemap.c	2013-05-24 10:28:34.649978405 +0900
- ***************
- *** 35,40 ****
- --- 35,41 ----
-   #include <linux/memcontrol.h>
-   #include <linux/cleancache.h>
-   #include "internal.h"
- + #include <linux/ctexdbg.h>
-   
-   /*
-    * FIXME: remove all knowledge of the buffer layer from the core VM
- ***************
- *** 551,559 ****
- --- 552,566 ----
-   {
-   	DEFINE_WAIT_BIT(wait, &page->flags, bit_nr);
-   
- + #ifdef CONFIG_CTEX_TRACE	
- + 	ctx_ev_memory(CTX_EV_MEMORY_PAGE_WAIT_START,0);
- + #endif
-   	if (test_bit(bit_nr, &page->flags))
-   		__wait_on_bit(page_waitqueue(page), &wait, sleep_on_page,
-   							TASK_UNINTERRUPTIBLE);
- + #ifdef CONFIG_CTEX_TRACE
- + 	ctx_ev_memory(CTX_EV_MEMORY_PAGE_WAIT_END,0);
- + #endif
-   }
-   EXPORT_SYMBOL(wait_on_page_bit);
-   
- diff -crN linux-3.2.1_o/mm/memory.c linux-3.2.1_ctex/mm/memory.c
- *** linux-3.2.1_o/mm/memory.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1_ctex/mm/memory.c	2013-05-24 10:28:34.682371232 +0900
- ***************
- *** 57,62 ****
- --- 57,63 ----
-   #include <linux/swapops.h>
-   #include <linux/elf.h>
-   #include <linux/gfp.h>
- + #include <linux/ctexdbg.h>
-   
-   #include <asm/io.h>
-   #include <asm/pgalloc.h>
- ***************
- *** 2899,2904 ****
- --- 2900,2908 ----
-   		ret = VM_FAULT_MAJOR;
-   		count_vm_event(PGMAJFAULT);
-   		mem_cgroup_count_vm_event(mm, PGMAJFAULT);
- + #ifdef CONFIG_CTEX_TRACE
- + 		ctx_ev_memory(CTX_EV_MEMORY_SWAP_IN,(uint32_t)address);
- + #endif
-   	} else if (PageHWPoison(page)) {
-   		/*
-   		 * hwpoisoned dirty swapcache pages are kept for killing
- ***************
- *** 3009,3014 ****
- --- 3013,3021 ----
-   
-   	/* No need to invalidate - it was non-present before */
-   	update_mmu_cache(vma, address, page_table);
- + #if defined(CONFIG_CTEX_DBGLIB)
- + 	ctexdbg_do_no_page(vma,address);
- + #endif /* CONFIG_CTEX_DBGLIB */
-   unlock:
-   	pte_unmap_unlock(page_table, ptl);
-   out:
- ***************
- *** 3286,3291 ****
- --- 3293,3301 ----
-   		else
-   			anon = 1; /* no anon but release faulted_page */
-   	}
- + #if defined(CONFIG_CTEX_DBGLIB)
- + 	ctexdbg_do_no_page(vma,address);
- + #endif /* CONFIG_CTEX_DBGLIB */
-   
-   	pte_unmap_unlock(page_table, ptl);
-   
- diff -crN linux-3.2.1_o/mm/mmap.c linux-3.2.1_ctex/mm/mmap.c
- *** linux-3.2.1_o/mm/mmap.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1_ctex/mm/mmap.c	2013-05-24 10:28:34.750405723 +0900
- ***************
- *** 30,35 ****
- --- 30,36 ----
-   #include <linux/perf_event.h>
-   #include <linux/audit.h>
-   #include <linux/khugepaged.h>
- + #include <linux/ctexdbg.h>
-   
-   #include <asm/uaccess.h>
-   #include <asm/cacheflush.h>
- ***************
- *** 1281,1286 ****
- --- 1282,1292 ----
-   		error = file->f_op->mmap(file, vma);
-   		if (error)
-   			goto unmap_and_free_vma;
- + 
- + #if defined(CONFIG_CTEX_DBGLIB)
- + 		ctexdbg_filemap(vma);
- + #endif /* CONFIG_CTEX_DBGLIB */
- + 
-   		if (vm_flags & VM_EXECUTABLE)
-   			added_exe_file_vma(mm);
-   
- diff -crN linux-3.2.1_o/mm/page_alloc.c linux-3.2.1_ctex/mm/page_alloc.c
- *** linux-3.2.1_o/mm/page_alloc.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1_ctex/mm/page_alloc.c	2013-05-24 10:32:28.673028000 +0900
- ***************
- *** 57,62 ****
- --- 57,63 ----
-   #include <linux/ftrace_event.h>
-   #include <linux/memcontrol.h>
-   #include <linux/prefetch.h>
- + #include <linux/ctexdbg.h>
-   
-   #include <asm/tlbflush.h>
-   #include <asm/div64.h>
- ***************
- *** 689,694 ****
- --- 690,700 ----
-   	__count_vm_events(PGFREE, 1 << order);
-   	free_one_page(page_zone(page), page, order,
-   					get_pageblock_migratetype(page));
- + 
- + #ifdef CONFIG_CTEX_TRACE
- + 	ctx_ev_memory(CTX_EV_MEMORY_PAGE_FREE,order);
- + #endif
- + 
-   	local_irq_restore(flags);
-   }
-   
- ***************
- *** 2318,2323 ****
- --- 2324,2332 ----
-   	page = alloc_pages(gfp_mask, order);
-   	if (!page)
-   		return 0;
- + #ifdef CONFIG_CTEX_TRACE
- + 	ctx_ev_memory(CTX_EV_MEMORY_PAGE_ALLOC,order);
- + #endif
-   	return (unsigned long) page_address(page);
-   }
-   EXPORT_SYMBOL(__get_free_pages);
- diff -crN linux-3.2.1_o/mm/page_io.c linux-3.2.1_ctex/mm/page_io.c
- *** linux-3.2.1_o/mm/page_io.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1_ctex/mm/page_io.c	2013-05-24 10:28:34.838389436 +0900
- ***************
- *** 18,23 ****
- --- 18,25 ----
-   #include <linux/bio.h>
-   #include <linux/swapops.h>
-   #include <linux/writeback.h>
- + #include <linux/ctexdbg.h>
- + 
-   #include <asm/pgtable.h>
-   
-   static struct bio *get_swap_bio(gfp_t gfp_flags,
- ***************
- *** 109,114 ****
- --- 111,119 ----
-   		rw |= REQ_SYNC;
-   	count_vm_event(PSWPOUT);
-   	set_page_writeback(page);
- + #ifdef CONFIG_CTEX_TRACE
- + 	ctx_ev_memory(CTX_EV_MEMORY_SWAP_OUT,(uint32_t)page_address(page));
- + #endif
-   	unlock_page(page);
-   	submit_bio(rw, bio);
-   out:
- diff -crN linux-3.2.1_o/net/socket.c linux-3.2.1_ctex/net/socket.c
- *** linux-3.2.1_o/net/socket.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1_ctex/net/socket.c	2013-05-24 10:32:00.000388000 +0900
- ***************
- *** 88,93 ****
- --- 88,94 ----
-   #include <linux/nsproxy.h>
-   #include <linux/magic.h>
-   #include <linux/slab.h>
- + #include <linux/ctexdbg.h>
-   
-   #include <asm/uaccess.h>
-   #include <asm/unistd.h>
- ***************
- *** 570,576 ****
-   	struct kiocb iocb;
-   	struct sock_iocb siocb;
-   	int ret;
- ! 
-   	init_sync_kiocb(&iocb, NULL);
-   	iocb.private = &siocb;
-   	ret = __sock_sendmsg(&iocb, sock, msg, size);
- --- 571,579 ----
-   	struct kiocb iocb;
-   	struct sock_iocb siocb;
-   	int ret;
- ! #ifdef CONFIG_CTEX_TRACE
- ! 	ctx_ev_socket(CTX_EV_SOCKET_SEND,sock->sk->sk_type,size);
- ! #endif
-   	init_sync_kiocb(&iocb, NULL);
-   	iocb.private = &siocb;
-   	ret = __sock_sendmsg(&iocb, sock, msg, size);
- ***************
- *** 697,702 ****
- --- 700,709 ----
-   
-   	sock_update_classid(sock->sk);
-   
- + #ifdef CONFIG_CTEX_TRACE
- + 	ctx_ev_socket(CTX_EV_SOCKET_RECEIVE,sock->sk->sk_type,size);
- + #endif
- + 
-   	si->sock = sock;
-   	si->scm = NULL;
-   	si->msg = msg;
- ***************
- *** 1327,1332 ****
- --- 1334,1343 ----
-   	if (retval < 0)
-   		goto out_release;
-   
- + #ifdef CONFIG_CTEX_TRACE
- + 	ctx_ev_socket(CTX_EV_SOCKET_CREATE,retval,sock->sk->sk_type);
- + #endif
- + 
-   out:
-   	/* It may be already another descriptor 8) Not kernel problem. */
-   	return retval;
- ***************
- *** 2365,2371 ****
-   
-   	a0 = a[0];
-   	a1 = a[1];
- ! 
-   	switch (call) {
-   	case SYS_SOCKET:
-   		err = sys_socket(a0, a1, a[2]);
- --- 2376,2384 ----
-   
-   	a0 = a[0];
-   	a1 = a[1];
- ! #ifdef CONFIG_CTEX_TRACE
- ! 	ctx_ev_socket(CTX_EV_SOCKET_CALL,call,a0);
- ! #endif
-   	switch (call) {
-   	case SYS_SOCKET:
-   		err = sys_socket(a0, a1, a[2]);
--- 0 ----
diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-3352/patches/linux-3.2.1-000-ctexdbg_arm_generic_v015.patch buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-3352/patches/linux-3.2.1-000-ctexdbg_arm_generic_v015.patch
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-3352/patches/linux-3.2.1-000-ctexdbg_arm_generic_v015.patch	1970-01-01 09:00:00.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-3352/patches/linux-3.2.1-000-ctexdbg_arm_generic_v015.patch	2014-11-17 14:11:17.000000000 +0900
***************
*** 0 ****
--- 1,5702 ----
+ diff -crN linux-3.2.1_o/Makefile linux-3.2.1/Makefile
+ *** linux-3.2.1_o/Makefile	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/Makefile	2014-11-14 21:03:15.494351678 +0900
+ ***************
+ *** 593,599 ****
+   endif
+   
+   ifdef CONFIG_DEBUG_INFO
+ ! KBUILD_CFLAGS	+= -g
+   KBUILD_AFLAGS	+= -gdwarf-2
+   endif
+   
+ --- 593,599 ----
+   endif
+   
+   ifdef CONFIG_DEBUG_INFO
+ ! KBUILD_CFLAGS	+= -gdwarf-2
+   KBUILD_AFLAGS	+= -gdwarf-2
+   endif
+   
+ diff -crN linux-3.2.1_o/arch/arm/Kconfig linux-3.2.1/arch/arm/Kconfig
+ *** linux-3.2.1_o/arch/arm/Kconfig	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/arch/arm/Kconfig	2014-11-14 21:03:15.518351678 +0900
+ ***************
+ *** 2244,2249 ****
+ --- 2244,2251 ----
+   
+   source "security/Kconfig"
+   
+ + source "arch/arm/Kconfig.ctex"
+ + 
+   source "crypto/Kconfig"
+   
+   source "lib/Kconfig"
+ diff -crN linux-3.2.1_o/arch/arm/Kconfig.ctex linux-3.2.1/arch/arm/Kconfig.ctex
+ *** linux-3.2.1_o/arch/arm/Kconfig.ctex	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/Kconfig.ctex	2014-11-14 21:03:15.518351678 +0900
+ ***************
+ *** 0 ****
+ --- 1,62 ----
+ + menu "Computex Linux dbglib"
+ + 
+ + config CTEX_DBGLIB
+ + 	bool "Computex linux debug library support"
+ + 	default n
+ + 	help
+ + 	  support computex linux debug library.
+ + 	  Start the 'Computex Linux library' daemon just before stating the init process.
+ + 	  and computex ICE support patch
+ + 
+ + if ((CPU_V6 || CPU_V7) && CTEX_DBGLIB)	  
+ + choice
+ + 	prompt "ETM Tracing mode (CPUV6 CPUV7)"
+ + 	default CTEXDBG_ETM_CP15_PID_ONLY
+ + 
+ + config CTEXDBG_ETM_CP15_PID_NAME
+ + 	bool "PID with ProcessName"
+ + 
+ + config CTEXDBG_ETM_CP15_PID_ONLY_V6
+ + 	bool "PID Only"
+ + 	
+ + endchoice
+ + 
+ + endif
+ + 
+ + if (! (CPU_V6 || CPU_V7) && CTEX_DBGLIB)	  
+ + choice
+ + 	prompt "ETM Tracing mode"
+ + 	default CTEXDBG_ETM_CP15_PID_NML
+ + 
+ + config CTEXDBG_ETM_CP15_PID_ONLY
+ + 	bool "PID in CP15"
+ + 
+ + config CTEXDBG_ETM_CP15_PID_NML
+ + 	bool "Not Use CP15"
+ + 	
+ + endchoice
+ + 
+ + endif
+ + 
+ + config CTEX_TRACE
+ + 	bool "Enable process trace"
+ + 	depends on CTEX_DBGLIB
+ + 	default y
+ + 	help
+ + 	  say Y, Support process trace from ICE.
+ + 
+ + config CTEX_DBGLIB_MOD_NOINITEXIT
+ + 	bool "disable _init _exit define (loadable module only)"
+ + 	depends on CTEX_DBGLIB
+ + 	default n
+ + 	help
+ + 	  say Y, disable __init and __exit defines.
+ + 	  and support for loadable module debugging.
+ + 
+ + config CTEX_DBGLIB_ANDROID
+ + 	bool "Enable google android support"
+ + 	depends on CTEX_DBGLIB
+ + 	default n
+ + 	help
+ + 	  say Y, Support google android system.
+ + endmenu
+ diff -crN linux-3.2.1_o/arch/arm/include/asm/ctexdbg_arch.h linux-3.2.1/arch/arm/include/asm/ctexdbg_arch.h
+ *** linux-3.2.1_o/arch/arm/include/asm/ctexdbg_arch.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/include/asm/ctexdbg_arch.h	2014-11-14 21:03:15.518351678 +0900
+ ***************
+ *** 0 ****
+ --- 1,198 ----
+ + /*
+ +  *  linux/arch/arm/ctexdbg_arch.h
+ +  */
+ + 
+ + #ifndef _LINUX_CTEXDBG_ARCH_H
+ + #define _LINUX_CTEXDBG_ARCH_H
+ +  
+ + #include <linux/kernel.h>
+ + #include <linux/sched.h>
+ + #include <linux/mm.h>
+ + #include <linux/user.h>
+ + 
+ + #include <asm/uaccess.h>
+ + #include <asm/pgtable.h>
+ + #include <asm/system.h>
+ + 
+ + #include <linux/ctexdbg.h>
+ + 
+ + #ifdef CONFIG_CTEX_DBGLIB
+ + 
+ + /* scheduler change */
+ + #if defined(CONFIG_CTEXDBG_ETM_CP15_PID_NAME)
+ + /* set CP15.c3 pid and process name*/
+ + inline void ctexdbg_arch_schedchange_event(unsigned long prevpid,unsigned long nextpid,unsigned char *next_comm)
+ + {
+ + 	register unsigned long cp;
+ + 	register unsigned long temp;
+ + 	barrier();
+ + 	
+ + 	if((ctexdbg_enabled == 0)&&(ctexdbg_hardware_trace_enabled == 0)) return;	
+ + #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V7)
+ + 	/* v6 only...*/
+ + 	/* init. */
+ + 	cp = 0;
+ + 	__asm__ volatile(
+ + 	"	mrc		p15,0,%0,c13,c0,1\n"
+ + 	: "=r" (cp) : "0" (0) : "memory"
+ + 	);
+ + 	cp &= 0xff;
+ + 	// process name 
+ + 	temp = 0xff000000l |  (next_comm[0] << 16) | (next_comm[1] << 8) | cp;
+ + 	__asm__ volatile(
+ + 	"	mcr		p15,0,%0,c13,c0,1\n"
+ + 	: : "r" (temp) : "memory"
+ + 	);
+ + 
+ + 	temp = (next_comm[2] << 24)|  (next_comm[3] << 16) | (next_comm[4] << 8) | cp;
+ + 	__asm__ volatile(
+ + 	"	mcr		p15,0,%0,c13,c0,1\n"
+ + 	: : "r" (temp) : "memory"
+ + 	);
+ + 	
+ + 	temp = (next_comm[5] << 24)|  (next_comm[6] << 16) | (next_comm[7] << 8) | cp;
+ + 	__asm__ volatile(
+ + 	"	mcr		p15,0,%0,c13,c0,1\n"
+ + 	: : "r" (temp) : "memory"
+ + 	);
+ + 
+ + 	temp = (next_comm[8] << 24)|  (next_comm[9] << 16) | (next_comm[10] << 8) | cp;
+ + 	__asm__ volatile(
+ + 	"	mcr		p15,0,%0,c13,c0,1\n"
+ + 	: : "r" (temp) : "memory"
+ + 	);
+ + 
+ + 	temp = (next_comm[11] << 24)|  (next_comm[12] << 16) | (next_comm[13] << 8) | cp;
+ + 	__asm__ volatile(
+ + 	"	mcr		p15,0,%0,c13,c0,1\n"
+ + 	: : "r" (temp) : "memory"
+ + 	);
+ + 
+ + 	temp = (next_comm[14] << 24)|  (next_comm[15] << 16) | (0xfel << 8) | cp;
+ + 	__asm__ volatile(
+ + 	"	mcr		p15,0,%0,c13,c0,1\n"
+ + 	: : "r" (temp) : "memory"
+ + 	);
+ + 
+ + 	// process id
+ + 	__asm__ volatile(
+ + 	"	and		%1,%1,#0x000000FF\n"
+ + 	"	mov		%0,%0,lsl #8\n"
+ + 	"	orr		%1,%0,%1\n"
+ + 	"	mcr		p15,0,%1,c13,c0,1\n"
+ + 	: : "r" ((unsigned long)(nextpid)) , "r" ((unsigned long)(cp)) : "memory"
+ + 	);
+ + #endif /* V6 */
+ + 
+ + 	return;
+ + }
+ + 
+ + #elif defined(CONFIG_CTEXDBG_ETM_CP15_PID_ONLY) || defined(CONFIG_CTEXDBG_ETM_CP15_PID_ONLY_V6)
+ + /* set CP15.c3 pid */
+ + inline void ctexdbg_arch_schedchange_event(unsigned long prevpid,unsigned long nextpid,unsigned char *next_comm)
+ + {
+ + 	register unsigned long unused;
+ + 	barrier();
+ + 	if((ctexdbg_enabled == 0)&&(ctexdbg_hardware_trace_enabled == 0)) return;	
+ + 
+ + #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V7)
+ + 	__asm__ volatile(
+ + 	"	mrc		p15,0,%0,c13,c0,1\n"
+ + 	: "=r" (unused) : "0" (0) : "memory"
+ + 	);
+ + 	__asm__ volatile(
+ + 	"	and		%1,%1,#0x000000FF\n"
+ + 	"	mov		%0,%0,lsl #8\n"
+ + 	"	orr		%1,%0,%1\n"
+ + 	"	mcr		p15,0,%1,c13,c0,1\n"
+ + 	: : "r" ((unsigned long)(nextpid)), "r" ((unsigned long)(unused)) : "memory"
+ + 	);
+ + #else
+ + 	/* not v6 no shift bit */
+ + 	__asm__ volatile(
+ + 	"	mcr		p15,0,%0,c13,c0,1\n"
+ + 	: : "r" ((unsigned long)(nextpid)) : "memory"
+ + 	);	
+ + #endif /* V6 */
+ + }
+ + 
+ + #else
+ + inline void ctexdbg_arch_schedchange_event(unsigned long prevpid,unsigned long nextpid,unsigned char *next_comm)
+ + {
+ + 	/* V6 must be this */
+ + #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V7)
+ + 	register unsigned long unused;
+ + 	barrier();
+ + 	if((ctexdbg_enabled == 0)&&(ctexdbg_hardware_trace_enabled == 0)) return;	
+ + 	
+ + 	__asm__ volatile(
+ + 	"	mrc		p15,0,%0,c13,c0,1\n"
+ + 	: "=r" (unused) : "0" (0) : "memory"
+ + 	);
+ + 	__asm__ volatile(
+ + 	"	and		%1,%1,#0x000000FF\n"
+ + 	"	mov		%0,%0,lsl #8\n"
+ + 	"	orr		%1,%0,%1\n"
+ + 	"	mcr		p15,0,%1,c13,c0,1\n"
+ + 	: : "r" ((unsigned long)(nextpid)), "r" ((unsigned long)(unused)) : "memory"
+ + 	);
+ + #else
+ + 	/* no v6 ... set pid external data to mem */
+ + /*
+ + 	ctexdbg_prevpid = prevpid; 
+ + 	ctexdbg_nextpid = nextpid;
+ + */
+ + 	register unsigned long unused=0;
+ + 	register unsigned long a = (unsigned long)&ctexdbg_prevpid;
+ + 	register unsigned long b = (unsigned long)&ctexdbg_nextpid;
+ + 	register unsigned long c = prevpid;
+ + 	register unsigned long d = nextpid;
+ + 
+ + 	barrier();
+ + 	if((ctexdbg_enabled == 0)&&(ctexdbg_hardware_trace_enabled == 0)) return;	
+ + 
+ + 	__asm__ volatile(
+ + 	"	mcr		p15,0,%4,c7,c10,1\n"
+ + 	"	mcr		p15,0,%0,c7,c10,4\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	str		%2,[%4,#0]\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	str		%1,[%3,#0]\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	:
+ + 	: "r" ((unsigned long)(unused)),"r" ((unsigned long)(c)),"r" ((unsigned long)(d)),"r" ((unsigned long)(a)),"r" ((unsigned long)(b))
+ + 	:  "memory"
+ + 	);
+ + 	
+ + #endif /* V6 */
+ + 	
+ + }
+ + 
+ + #endif
+ + 
+ + 
+ + #endif /* CONFIG_CTEX_DBGLIB */
+ + 
+ + #endif /* _LINUX_CTEXDBG_ARCH_H */
+ + 
+ diff -crN linux-3.2.1_o/arch/arm/include/asm/unistd.h linux-3.2.1/arch/arm/include/asm/unistd.h
+ *** linux-3.2.1_o/arch/arm/include/asm/unistd.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/arch/arm/include/asm/unistd.h	2014-11-14 21:03:15.542351677 +0900
+ ***************
+ *** 414,419 ****
+ --- 414,422 ----
+   #define __ARM_NR_usr26			(__ARM_NR_BASE+3)
+   #define __ARM_NR_usr32			(__ARM_NR_BASE+4)
+   #define __ARM_NR_set_tls		(__ARM_NR_BASE+5)
+ + #ifdef CONFIG_CTEX_DBGLIB
+ + #define __ARM_NR_ctexnotify		(__ARM_NR_BASE+6)
+ + #endif /* CONFIG_CTEX_DBGLIB */
+   
+   /*
+    * *NOTE*: This is a ghost syscall private to the kernel.  Only the
+ diff -crN linux-3.2.1_o/arch/arm/kernel/Makefile linux-3.2.1/arch/arm/kernel/Makefile
+ *** linux-3.2.1_o/arch/arm/kernel/Makefile	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/arch/arm/kernel/Makefile	2014-11-14 21:03:15.542351677 +0900
+ ***************
+ *** 58,63 ****
+ --- 58,64 ----
+   obj-$(CONFIG_HAVE_TCM)		+= tcm.o
+   obj-$(CONFIG_OF)		+= devtree.o
+   obj-$(CONFIG_CRASH_DUMP)	+= crash_dump.o
+ + obj-$(CONFIG_CTEX_DBGLIB)	+= ctexdbg_arch.o
+   obj-$(CONFIG_SWP_EMULATE)	+= swp_emulate.o
+   CFLAGS_swp_emulate.o		:= -Wa,-march=armv7-a
+   obj-$(CONFIG_HAVE_HW_BREAKPOINT)	+= hw_breakpoint.o
+ diff -crN linux-3.2.1_o/arch/arm/kernel/ctexdbg_arch.c linux-3.2.1/arch/arm/kernel/ctexdbg_arch.c
+ *** linux-3.2.1_o/arch/arm/kernel/ctexdbg_arch.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/kernel/ctexdbg_arch.c	2014-11-14 21:03:15.542351677 +0900
+ ***************
+ *** 0 ****
+ --- 1,308 ----
+ + /*
+ +  *  linux/arch/arm/ctexdbg_arch.c
+ +  *
+ +  * (C) Copyright 2004 - Computex co.,ltd.
+ +  *
+ +  * Computex dbglib support kernel thread (arch depend)
+ +  *
+ +  */
+ + 
+ + #include <linux/kernel.h>
+ + #include <linux/sched.h>
+ + #include <linux/mm.h>
+ + #include <linux/user.h>
+ + #include <linux/highmem.h>
+ + 
+ + #include <asm/uaccess.h>
+ + #include <asm/pgtable.h>
+ + #include <asm/system.h>
+ + 
+ + #include <linux/ctexdbg.h>
+ + 
+ + 
+ + #include "../vfp/vfpinstr.h"
+ + #include "../vfp/vfp.h"
+ + 
+ + #if defined(CONFIG_CTEX_DBGLIB)
+ + 
+ + extern spinlock_t ctexdbg_kernel_spinlock;		/* kernel lock */
+ + 
+ + #if defined(CONFIG_VFP)
+ + extern union vfp_state *vfp_current_hw_state[NR_CPUS];	/* last vfp state */
+ + #endif /* CONFIG_VFP */
+ + 
+ + /* ctexdbg fixeddata */
+ + typedef struct __tag_ctexdbg_configdata
+ + {
+ + 	uint8_t trace_into_pname;	/* trace into process name 0: no 1:yes */
+ + 	uint8_t trace_pid_in_mode;	/* trace pid in tracer 0: no use 1: memory in 2:CP15 (v6mode) 3:CP15 (v4mode)*/
+ + 	
+ + }ctexdbg_pri_config;
+ + 
+ + ctexdbg_pri_config ctexdbg_configdata;
+ + 
+ + /* private monitor */
+ + uint32_t ctexdbg_monitor[64];
+ + 
+ + /* cache flush code */
+ + extern void ctexdbg_cache_flush_all(void);
+ + uint32_t ctexdbg_cache_flush_addr;
+ + 
+ + unsigned int ctexdbg_cpuid[NR_CPUS];
+ + 
+ + /* ------------------------------- event break area -------------------------------- */
+ + #if defined(CONFIG_THUMB2_KERNEL)
+ + /* thumb2 kernel */
+ + void ctexdbg_event_core(void)
+ + {
+ + 	barrier();
+ + 	/* ice breakcode (BKPT 0) */
+ + 	__asm__ volatile(
+ + 	".word	 0xBE00\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	:::"lr"
+ + 	);
+ + }
+ + 
+ + #elif defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V7)
+ + /* arm 11xx */
+ + void ctexdbg_event_core(void)
+ + {
+ + 	barrier();
+ + 	/* ice breakcode (BKPT 0) */
+ + 	__asm__ volatile(
+ + 	".long	 0xE1200070\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	:::"lr"
+ + 	);
+ + }
+ + #elif defined(CONFIG_ARCH_OMAP) || defined(CONFIG_CPU_ARM710) || defined(CONFIG_CPU_ARM720T) || defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T)
+ + /* other (arm 920T omap15xx 16xx) */
+ + void ctexdbg_event_core(void)
+ + {
+ + 	barrier();
+ + 	/* ice breakcode */
+ + 	/* LDR lr,[sp,#-4]! */
+ + 	/* swi FFDFFF */
+ + 	/* STR lr,[sp,#4] */
+ + 	__asm__ volatile(
+ + 	".long	 0xDFFFDFFF\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	:::"lr"
+ + 	);
+ + }
+ + #else
+ + void ctexdbg_event_core(void)
+ + {
+ + 	barrier();
+ + 	/* ice breakcode (BKPT 0) */
+ + 	__asm__ volatile(
+ + 	".long	 0xE1200070\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	"	nop\n"
+ + 	:::"lr"
+ + 	);	
+ + }
+ + 
+ + #endif /* V6 */
+ + 
+ + /* -------------------------------------------------------------------------------- */
+ + /* ICE connection check */
+ + int ctexdbg_arch_checkice(void)
+ + {
+ + 	barrier();
+ + 	return 0;
+ + }
+ + 
+ + /* ------------------------lock and unlock K ---------------------------------------- */
+ + /* FORCE Interrupt disable and kernel locking (return OLD irqflasg)*/
+ + unsigned long ctexdbg_arch_lock_kernel(void)
+ + {
+ + 	unsigned long flags;
+ + 	barrier();
+ + 	spin_lock_irqsave(&ctexdbg_kernel_spinlock, flags);	
+ + 	return flags;
+ + }
+ +                                                                                 
+ + /* unlock kernel and MSR restore (arg:oldval ... irqflag)*/
+ + void ctexdbg_arch_unlock_kernel(unsigned long oldval)
+ + {
+ + 	barrier();
+ + 	spin_unlock_irqrestore(&ctexdbg_kernel_spinlock, oldval);	
+ + }
+ + /* -------------------------------------------------------------------------------- */
+ + 
+ + 
+ + /* ------------------------------- debugging func -------------------------------- */
+ + /* [debug] print context registers */
+ + void ctexdbg_print_context_reg(struct pt_regs *regs)
+ + {
+ + 	show_regs(regs);
+ + }
+ + 
+ + /* why=r2 ptreg=r1 scno or sysreturn =r0 */
+ + asmlinkage int ctexdbg_trace_syscall(int scno,struct pt_regs *regs,int why)
+ + {
+ + 	if(ctexdbg_traceuse == 0) return scno;
+ + 	if(!why){
+ + 		ctx_ev_syscall_entry(scno,instruction_pointer(regs));
+ + 	}else{
+ + 		ctx_ev_syscall_exit();
+ + 	}
+ + 	return scno;
+ + }
+ + 
+ + /* save vfp to user context */
+ + void ctexdbg_arch_vfpsave(struct thread_info *thread,u32 fpexc)
+ + {
+ + #if defined(CONFIG_VFP)
+ + 	union vfp_state *vfp;
+ + 	__u32 cpu;
+ + 	/* debug process only */
+ + 	if (ctexdbg_enabled == 0) return;
+ + 	if (ctexdbg_find_debugpid(current->pid) == NULL) return;
+ + 	
+ + 	/* save current thread vfp  */
+ + 	vfp = &(current_thread_info()->vfpstate);
+ + 	vfp_save_state(vfp, fpexc);
+ + 	cpu = thread->cpu;
+ + 	/* reload context vfp to next vfp exception. */
+ + 	vfp_current_hw_state[cpu] = NULL;		
+ + #endif
+ + }
+ + 
+ + int ctexdbg_arch_init(void)
+ + {
+ + 	barrier();
+ + 	ctexdbg_configdata.trace_into_pname = 0;
+ + 	ctexdbg_configdata.trace_pid_in_mode = 0;
+ + 	
+ + #if defined(CONFIG_CTEXDBG_ETM_CP15_PID_NAME)
+ + #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V7)
+ + 	ctexdbg_configdata.trace_into_pname = 1;		/* use name */
+ + 	ctexdbg_configdata.trace_pid_in_mode = 2;		/* PID in CP15 V6 or V7 */
+ + #endif
+ + 
+ + #elif defined(CONFIG_CTEXDBG_ETM_CP15_PID_ONLY) || defined(CONFIG_CTEXDBG_ETM_CP15_PID_ONLY_V6)
+ + #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V7)
+ + 	ctexdbg_configdata.trace_pid_in_mode = 2;		/* PID in CP15 V6 or V7 */
+ + #else
+ + 	ctexdbg_configdata.trace_pid_in_mode = 3;		/* PID in CP15 V4 */
+ + #endif
+ + #else
+ + #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V7)
+ + 	ctexdbg_configdata.trace_pid_in_mode = 2;		/* PID in CP15 V6 or V7 */
+ + #else
+ + 	ctexdbg_configdata.trace_pid_in_mode = 1;		/* PID in memory */
+ + #endif
+ + 
+ + #endif
+ + 	ctexdbg_fixdata.mem_page_offset = PAGE_OFFSET;
+ + 	ctexdbg_fixdata.mem_phys_offset = PHYS_OFFSET;
+ + 	ctexdbg_fixdata.mem_lowmem_start = PAGE_OFFSET;
+ + 	ctexdbg_fixdata.mem_lowmem_end = (uint32_t)high_memory;
+ + 	ctexdbg_fixdata.mem_vmalloc_start = VMALLOC_START;
+ + 	ctexdbg_fixdata.mem_vmalloc_end = VMALLOC_END;
+ + #ifdef CONFIG_MODULES	
+ + 	ctexdbg_fixdata.mem_modules_start = MODULES_VADDR;
+ + 	ctexdbg_fixdata.mem_modules_end = MODULES_END;
+ + #endif
+ + #ifdef CONFIG_HIGHMEM
+ + 	ctexdbg_fixdata.mem_is_highmem = 1;
+ + 	ctexdbg_fixdata.mem_highmem_start = PKMAP_BASE;
+ + 	ctexdbg_fixdata.mem_highmem_end = ((PKMAP_BASE)+(LAST_PKMAP) * (PAGE_SIZE));	
+ + #ifdef CONFIG_HIGHPTE
+ + 	ctexdbg_fixdata.mem_is_highpte = 1;
+ + #endif	
+ + #endif
+ + #ifdef CONFIG_ARM_LPAE
+ + 	ctexdbg_fixdata.mem_is_lpae = 1;
+ + #endif
+ + 
+ + #ifdef CONFIG_CPU_V7
+ + 	ctexdbg_cache_flush_addr = (uint32_t)ctexdbg_cache_flush_all & 0xFFFFFFFE;
+ + #else
+ + 	ctexdbg_cache_flush_addr = 0;
+ + #endif
+ + 
+ + #ifndef CONFIG_SMP
+ + 	ctexdbg_cpuid[0] = 0;
+ + #endif	
+ + 	return 0;
+ + }
+ + 
+ + void ctexdbg_arch_store_cpuid(unsigned int cpuid)
+ + {
+ + #ifdef CONFIG_SMP
+ + 	ctexdbg_cpuid[cpuid] = read_cpuid_mpidr();
+ + 	printk("ctexdbg: store mpidr info (cpu %d mpidr %08X)\n",cpuid,ctexdbg_cpuid[cpuid]);
+ + #endif
+ + }
+ + 
+ + 
+ + 
+ + #endif /* CONFIG_CTEX_DBGLIB */
+ diff -crN linux-3.2.1_o/arch/arm/kernel/entry-common.S linux-3.2.1/arch/arm/kernel/entry-common.S
+ *** linux-3.2.1_o/arch/arm/kernel/entry-common.S	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/arch/arm/kernel/entry-common.S	2014-11-14 21:11:48.738346767 +0900
+ ***************
+ *** 85,94 ****
+ --- 85,104 ----
+   ENTRY(ret_from_fork)
+   	bl	schedule_tail
+   	get_thread_info tsk
+ + #if defined(CONFIG_CTEX_TRACE)
+ + 	mov	why, #1
+ + 	ldr	r1 ,=ctexdbg_traceuse
+ + 	ldr	r1,[r1]
+ + 	cmp	r1 ,#1
+ + 	beq	__ctrace_ret
+ + #endif		
+   	ldr	r1, [tsk, #TI_FLAGS]		@ check for syscall tracing
+   	mov	why, #1
+   	tst	r1, #_TIF_SYSCALL_TRACE		@ are we tracing syscalls?
+   	beq	ret_slow_syscall
+ + #if defined(CONFIG_CTEX_TRACE)
+ + __ctrace_ret:
+ + #endif
+   	mov	r1, sp
+   	mov	r0, #1				@ trace exit [IP = 1]
+   	bl	syscall_trace
+ ***************
+ *** 443,448 ****
+ --- 453,466 ----
+   1:
+   #endif
+   
+ + #if defined(CONFIG_CTEX_TRACE)
+ + 	ldr	ip,=ctexdbg_traceuse
+ + 	ldr	ip,[ip]
+ + 	cmp	ip, #1
+ + 	ldr	ip, [tsk, #TI_FLAGS]		@ check for syscall tracing	
+ + 	beq	__sys_trace
+ + #endif
+ + 
+   	tst	r10, #_TIF_SYSCALL_TRACE		@ are we tracing syscalls?
+   	bne	__sys_trace
+   
+ diff -crN linux-3.2.1_o/arch/arm/kernel/process.c linux-3.2.1/arch/arm/kernel/process.c
+ *** linux-3.2.1_o/arch/arm/kernel/process.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/arch/arm/kernel/process.c	2014-11-14 21:03:15.574351677 +0900
+ ***************
+ *** 29,34 ****
+ --- 29,35 ----
+   #include <linux/utsname.h>
+   #include <linux/uaccess.h>
+   #include <linux/random.h>
+ + #include <linux/ctexdbg.h>
+   #include <linux/hw_breakpoint.h>
+   #include <linux/cpuidle.h>
+   
+ ***************
+ *** 449,455 ****
+   pid_t kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
+   {
+   	struct pt_regs regs;
+ ! 
+   	memset(&regs, 0, sizeof(regs));
+   
+   	regs.ARM_r4 = (unsigned long)arg;
+ --- 450,456 ----
+   pid_t kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
+   {
+   	struct pt_regs regs;
+ ! 	pid_t pid;
+   	memset(&regs, 0, sizeof(regs));
+   
+   	regs.ARM_r4 = (unsigned long)arg;
+ ***************
+ *** 459,465 ****
+   	regs.ARM_pc = (unsigned long)kernel_thread_helper;
+   	regs.ARM_cpsr = regs.ARM_r7 | PSR_I_BIT;
+   
+ ! 	return do_fork(flags|CLONE_VM|CLONE_UNTRACED, 0, &regs, 0, NULL, NULL);
+   }
+   EXPORT_SYMBOL(kernel_thread);
+   
+ --- 460,468 ----
+   	regs.ARM_pc = (unsigned long)kernel_thread_helper;
+   	regs.ARM_cpsr = regs.ARM_r7 | PSR_I_BIT;
+   
+ ! 	pid =  do_fork(flags|CLONE_VM|CLONE_UNTRACED, 0, &regs, 0, NULL, NULL);
+ ! 	ctx_ev_process(CTX_EV_PROCESS_KTHREAD,(u32)pid,(ulong)fn);
+ ! 	return pid;	
+   }
+   EXPORT_SYMBOL(kernel_thread);
+   
+ diff -crN linux-3.2.1_o/arch/arm/kernel/ptrace.c linux-3.2.1/arch/arm/kernel/ptrace.c
+ *** linux-3.2.1_o/arch/arm/kernel/ptrace.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/arch/arm/kernel/ptrace.c	2014-11-14 21:08:02.146348935 +0900
+ ***************
+ *** 21,26 ****
+ --- 21,27 ----
+   #include <linux/signal.h>
+   #include <linux/uaccess.h>
+   #include <linux/perf_event.h>
+ + #include <linux/ctexdbg.h>
+   #include <linux/hw_breakpoint.h>
+   #include <linux/regset.h>
+   
+ ***************
+ *** 902,911 ****
+ --- 903,920 ----
+   	return ret;
+   }
+   
+ + #ifdef CONFIG_CTEX_DBGLIB
+ + extern void ctexdbg_trace_syscall(int why, struct pt_regs *regs, int scno);
+ + #endif
+ + 
+   asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno)
+   {
+   	unsigned long ip;
+   
+ + #ifdef CONFIG_CTEX_DBGLIB
+ + 	ctexdbg_trace_syscall(scno,regs,why);
+ + #endif		
+ + 
+   	if (!test_thread_flag(TIF_SYSCALL_TRACE))
+   		return scno;
+   	if (!(current->ptrace & PT_PTRACED))
+ ***************
+ *** 937,939 ****
+ --- 946,963 ----
+   
+   	return current_thread_info()->syscall;
+   }
+ + 
+ + #ifdef CONFIG_CTEX_DBGLIB
+ + /*
+ +  * calc context user register base addr.
+ +  */
+ + void ctexdbg_arch_userregaddr(void)
+ + {
+ + 	/*
+ + 	return (struct pt_regs *)
+ + 		((unsigned long)task->thread_info + THREAD_SIZE -
+ + 				 8 - sizeof(struct pt_regs));	
+ + 	*/
+ + 	ctexdbg_fixdata.userregaddr = THREAD_SIZE -  8 - sizeof(struct pt_regs);
+ + }
+ + #endif /* CONFIG_CTEX_DBGLIB */
+ diff -crN linux-3.2.1_o/arch/arm/kernel/sys_oabi-compat.c linux-3.2.1/arch/arm/kernel/sys_oabi-compat.c
+ *** linux-3.2.1_o/arch/arm/kernel/sys_oabi-compat.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/arch/arm/kernel/sys_oabi-compat.c	2014-11-14 21:03:15.578351677 +0900
+ ***************
+ *** 84,89 ****
+ --- 84,90 ----
+   #include <linux/ipc.h>
+   #include <linux/uaccess.h>
+   #include <linux/slab.h>
+ + #include <linux/ctexdbg.h>
+   
+   struct oldabi_stat64 {
+   	unsigned long long st_dev;
+ ***************
+ *** 349,354 ****
+ --- 350,357 ----
+   asmlinkage int sys_oabi_ipc(uint call, int first, int second, int third,
+   			    void __user *ptr, long fifth)
+   {
+ + 	ctx_ev_ipc(CTX_EV_IPC_CALL,call,first);
+ + 	
+   	switch (call & 0xffff) {
+   	case SEMOP:
+   		return  sys_oabi_semtimedop(first,
+ diff -crN linux-3.2.1_o/arch/arm/kernel/traps.c linux-3.2.1/arch/arm/kernel/traps.c
+ *** linux-3.2.1_o/arch/arm/kernel/traps.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/arch/arm/kernel/traps.c	2014-11-14 21:03:15.582351677 +0900
+ ***************
+ *** 25,30 ****
+ --- 25,31 ----
+   #include <linux/delay.h>
+   #include <linux/init.h>
+   #include <linux/sched.h>
+ + #include <linux/ctexdbg.h>
+   
+   #include <linux/atomic.h>
+   #include <asm/cacheflush.h>
+ ***************
+ *** 298,305 ****
+   	if (user_mode(regs)) {
+   		current->thread.error_code = err;
+   		current->thread.trap_no = trap;
+ ! 
+   		force_sig_info(info->si_signo, info, current);
+   	} else {
+   		die(str, regs, err);
+   	}
+ --- 299,307 ----
+   	if (user_mode(regs)) {
+   		current->thread.error_code = err;
+   		current->thread.trap_no = trap;
+ ! 		ctx_ev_trap_entry(current->thread.trap_no,instruction_pointer(regs));	
+   		force_sig_info(info->si_signo, info, current);
+ + 		ctx_ev_trap_exit();
+   	} else {
+   		die(str, regs, err);
+   	}
+ ***************
+ *** 503,508 ****
+ --- 505,517 ----
+   	struct thread_info *thread = current_thread_info();
+   	siginfo_t info;
+   
+ + #ifdef CONFIG_CTEX_DBGLIB	
+ + 	if(no == 0xFFDFFF){
+ + 		/* ICE breakcode */
+ + 		return 0;
+ + 	}
+ + #endif /* CONFIG_CTEX_DBGLIB */
+ + 	
+   	if ((no >> 16) != (__ARM_NR_BASE>> 16))
+   		return bad_syscall(no, regs);
+   
+ ***************
+ *** 539,544 ****
+ --- 548,559 ----
+   		do_cache_op(regs->ARM_r0, regs->ARM_r1, regs->ARM_r2);
+   		return 0;
+   
+ + #ifdef CONFIG_CTEX_DBGLIB	
+ + 	case NR(ctexnotify): /* SWI ctexnotify */
+ + 		ctexdbg_external_notify((size_t)regs->ARM_r0,(void*)regs->ARM_r1);
+ + 		return 0;
+ + #endif /* CONFIG_CTEX_DBGLIB */
+ + 		
+   	case NR(usr26):
+   		if (!(elf_hwcap & HWCAP_26BIT))
+   			break;
+ diff -crN linux-3.2.1_o/arch/arm/mm/Makefile linux-3.2.1/arch/arm/mm/Makefile
+ *** linux-3.2.1_o/arch/arm/mm/Makefile	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/arch/arm/mm/Makefile	2014-11-14 21:03:15.598351677 +0900
+ ***************
+ *** 92,101 ****
+ --- 92,106 ----
+   obj-$(CONFIG_CPU_V6)		+= proc-v6.o
+   obj-$(CONFIG_CPU_V6K)		+= proc-v6.o
+   obj-$(CONFIG_CPU_V7)		+= proc-v7.o
+ + ifeq ($(CONFIG_CPU_V7),y)
+ + obj-$(CONFIG_CTEX_DBGLIB)	+= ctexdbg_asm_v7.o
+ + endif
+   
+   AFLAGS_proc-v6.o	:=-Wa,-march=armv6
+   AFLAGS_proc-v7.o	:=-Wa,-march=armv7-a
+   
+ + AFLAGS_ctexdbg_asm_v7.o	:=-Wa,-march=armv7-a
+ + 
+   obj-$(CONFIG_CACHE_FEROCEON_L2)	+= cache-feroceon-l2.o
+   obj-$(CONFIG_CACHE_L2X0)	+= cache-l2x0.o
+   obj-$(CONFIG_CACHE_XSC3L2)	+= cache-xsc3l2.o
+ diff -crN linux-3.2.1_o/arch/arm/mm/ctexdbg_asm_v7.S linux-3.2.1/arch/arm/mm/ctexdbg_asm_v7.S
+ *** linux-3.2.1_o/arch/arm/mm/ctexdbg_asm_v7.S	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mm/ctexdbg_asm_v7.S	2014-11-14 21:03:15.598351677 +0900
+ ***************
+ *** 0 ****
+ --- 1,71 ----
+ + /*
+ +  *  linux/arch/arm/mm/ctexdbg_asm_v7.c
+ +  *
+ +  * (C) Copyright 2004 - Computex co.,ltd.
+ +  *
+ +  * Computex dbglib support (arch depend)
+ +  *
+ +  */
+ + #include <linux/linkage.h>
+ + #include <linux/init.h>
+ + #include <asm/assembler.h>
+ + #include <asm/errno.h>
+ + #include <asm/unwind.h>
+ + 
+ + #include "proc-macros.S"
+ + 
+ + ENTRY(ctexdbg_cache_flush_all)
+ + 	dmb					@ ensure ordering with previous memory accesses
+ + 	mrc	p15, 1, r0, c0, c0, 1		@ read clidr
+ + 	ands	r3, r0, #0x7000000		@ extract loc from clidr
+ + 	mov	r3, r3, lsr #23			@ left align loc bit field
+ + 	beq	finished			@ if loc is 0, then no need to clean
+ + 	mov	r10, #0				@ start clean at cache level 0
+ + flush_levels:
+ + 	add	r2, r10, r10, lsr #1		@ work out 3x current cache level
+ + 	mov	r1, r0, lsr r2			@ extract cache type bits from clidr
+ + 	and	r1, r1, #7			@ mask of the bits for current cache only
+ + 	cmp	r1, #2				@ see what cache we have at this level
+ + 	blt	skip				@ skip if no cache, or just i-cache
+ + 	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
+ + 	isb					@ isb to sych the new cssr&csidr
+ + 	mrc	p15, 1, r1, c0, c0, 0		@ read the new csidr
+ + 	and	r2, r1, #7			@ extract the length of the cache lines
+ + 	add	r2, r2, #4			@ add 4 (line length offset)
+ + 	ldr	r4, =0x3ff
+ + 	ands	r4, r4, r1, lsr #3		@ find maximum number on the way size
+ + 	clz	r5, r4				@ find bit position of way size increment
+ + 	ldr	r7, =0x7fff
+ + 	ands	r7, r7, r1, lsr #13		@ extract max number of the index size
+ + loop1:
+ + 	mov	r9, r4				@ create working copy of max way size
+ + loop2:
+ +  ARM(	orr	r11, r10, r9, lsl r5	)	@ factor way and cache number into r11
+ +  THUMB(	lsl	r6, r9, r5		)
+ +  THUMB(	orr	r11, r10, r6		)	@ factor way and cache number into r11
+ +  ARM(	orr	r11, r11, r7, lsl r2	)	@ factor index number into r11
+ +  THUMB(	lsl	r6, r7, r2		)
+ +  THUMB(	orr	r11, r11, r6		)	@ factor index number into r11
+ + 	mcr	p15, 0, r11, c7, c14, 2		@ clean & invalidate by set/way
+ + 	subs	r9, r9, #1			@ decrement the way
+ + 	bge	loop2
+ + 	subs	r7, r7, #1			@ decrement the index
+ + 	bge	loop1
+ + skip:
+ + 	add	r10, r10, #2			@ increment cache number
+ + 	cmp	r3, r10
+ + 	bgt	flush_levels
+ + finished:
+ + 	mov	r10, #0				@ swith back to cache level 0
+ + 	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
+ + 	dsb
+ + 	isb
+ + 	mov	r0, #0
+ + 	ALT_SMP(mcr	p15, 0, r0, c7, c1, 0)	@ invalidate I-cache inner shareable
+ + 	ALT_UP(mcr	p15, 0, r0, c7, c5, 0)	@ I+BTB cache invalidate
+ +  ARM(	.long	0xE1200070	)			@ bkpt arm code
+ +  THUMB(	.word	0xBE00		)			@ bkpt thumb code
+ + 	nop
+ + ENDPROC(ctexdbg_cache_flush_all)
+ + 
+ + 
+ diff -crN linux-3.2.1_o/arch/arm/mm/mmu.c linux-3.2.1/arch/arm/mm/mmu.c
+ *** linux-3.2.1_o/arch/arm/mm/mmu.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/arch/arm/mm/mmu.c	2014-11-14 21:12:43.490346243 +0900
+ ***************
+ *** 15,20 ****
+ --- 15,21 ----
+   #include <linux/nodemask.h>
+   #include <linux/memblock.h>
+   #include <linux/fs.h>
+ + #include <linux/ctexdbg.h>
+   
+   #include <asm/cputype.h>
+   #include <asm/sections.h>
+ ***************
+ *** 704,709 ****
+ --- 705,714 ----
+   	addr = md->virtual & PAGE_MASK;
+   	phys = __pfn_to_phys(md->pfn);
+   	length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
+ + 	
+ + #ifdef CONFIG_CTEX_DBGLIB
+ + 	ctexdbg_add_memmap(md->virtual,__pfn_to_phys(md->pfn),md->length);
+ + #endif /* CONFIG_CTEX_DBGLIB */	
+   
+   	if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
+   		printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not "
+ diff -crN linux-3.2.1_o/arch/arm/vfp/vfpmodule.c linux-3.2.1/arch/arm/vfp/vfpmodule.c
+ *** linux-3.2.1_o/arch/arm/vfp/vfpmodule.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/arch/arm/vfp/vfpmodule.c	2014-11-14 21:03:15.646351676 +0900
+ ***************
+ *** 21,30 ****
+ --- 21,35 ----
+   #include <asm/cputype.h>
+   #include <asm/thread_notify.h>
+   #include <asm/vfp.h>
+ + #include <linux/ctexdbg.h>
+   
+   #include "vfpinstr.h"
+   #include "vfp.h"
+   
+ + #ifdef CONFIG_CTEX_DBGLIB
+ + extern void ctexdbg_arch_vfpsave(struct thread_info *thread,u32 fpexc);
+ + #endif /* CONFIG_CTEX_DBGLIB */
+ + 
+   /*
+    * Our undef handlers (in entry.S)
+    */
+ ***************
+ *** 504,509 ****
+ --- 509,519 ----
+   
+   	if (vfp_state_in_hw(cpu, thread)) {
+   		u32 fpexc = fmrx(FPEXC);
+ + #ifdef CONFIG_CTEX_DBGLIB
+ + 		if((fpexc & FPEXC_EN)){
+ + 			ctexdbg_arch_vfpsave(thread,fpexc);
+ + 		}
+ + #endif /* CONFIG_CTEX_DBGLIB */		
+   
+   		/*
+   		 * Save the last VFP state on this CPU.
+ diff -crN linux-3.2.1_o/fs/binfmt_elf.c linux-3.2.1/fs/binfmt_elf.c
+ *** linux-3.2.1_o/fs/binfmt_elf.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/fs/binfmt_elf.c	2014-11-14 21:03:15.646351676 +0900
+ ***************
+ *** 32,37 ****
+ --- 32,39 ----
+   #include <linux/elf.h>
+   #include <linux/utsname.h>
+   #include <linux/coredump.h>
+ + #include <linux/ctexdbg.h>
+ + 
+   #include <asm/uaccess.h>
+   #include <asm/param.h>
+   #include <asm/page.h>
+ ***************
+ *** 984,989 ****
+ --- 986,996 ----
+   #endif
+   
+   	start_thread(regs, elf_entry, bprm->p);
+ + #if defined(CONFIG_CTEX_DBGLIB)
+ + 	if(current->mm != NULL){
+ + 		ctexdbg_main_pre_brk(current,elf_entry,(unsigned long)current->mm->pgd);
+ + 	}
+ + #endif		
+   	retval = 0;
+   out:
+   	kfree(loc);
+ diff -crN linux-3.2.1_o/fs/buffer.c linux-3.2.1/fs/buffer.c
+ *** linux-3.2.1_o/fs/buffer.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/fs/buffer.c	2014-11-14 21:06:43.506349687 +0900
+ ***************
+ *** 42,47 ****
+ --- 42,48 ----
+   #include <linux/mpage.h>
+   #include <linux/bit_spinlock.h>
+   #include <linux/cleancache.h>
+ + #include <linux/ctexdbg.h>
+   
+   static int fsync_buffers_list(spinlock_t *lock, struct list_head *list);
+   
+ ***************
+ *** 83,89 ****
+ --- 84,92 ----
+    */
+   void __wait_on_buffer(struct buffer_head * bh)
+   {
+ + 	ctx_ev_file_system(CTX_EV_FILE_SYSTEM_BUF_WAIT_START,0,0,NULL);
+   	wait_on_bit(&bh->b_state, BH_Lock, sleep_on_buffer, TASK_UNINTERRUPTIBLE);
+ + 	ctx_ev_file_system(CTX_EV_FILE_SYSTEM_BUF_WAIT_END, 0, 0, NULL);
+   }
+   EXPORT_SYMBOL(__wait_on_buffer);
+   
+ diff -crN linux-3.2.1_o/fs/exec.c linux-3.2.1/fs/exec.c
+ *** linux-3.2.1_o/fs/exec.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/fs/exec.c	2014-11-14 21:03:15.650351676 +0900
+ ***************
+ *** 55,60 ****
+ --- 55,61 ----
+   #include <linux/pipe_fs_i.h>
+   #include <linux/oom.h>
+   #include <linux/compat.h>
+ + #include <linux/ctexdbg.h>
+   
+   #include <asm/uaccess.h>
+   #include <asm/mmu_context.h>
+ ***************
+ *** 1515,1520 ****
+ --- 1516,1528 ----
+   	if ((retval = bprm->envc) < 0)
+   		goto out;
+   
+ + #if defined(CONFIG_CTEX_DBGLIB)		
+ + 	ctexdbg_file_event(
+ + 		current,
+ + 		file,
+ + 		(uint32_t)bprm->mm->pgd
+ + 	);	
+ + #endif		
+   	retval = prepare_binprm(bprm);
+   	if (retval < 0)
+   		goto out;
+ ***************
+ *** 1527,1533 ****
+   	retval = copy_strings(bprm->envc, envp, bprm);
+   	if (retval < 0)
+   		goto out;
+ ! 
+   	retval = copy_strings(bprm->argc, argv, bprm);
+   	if (retval < 0)
+   		goto out;
+ --- 1535,1546 ----
+   	retval = copy_strings(bprm->envc, envp, bprm);
+   	if (retval < 0)
+   		goto out;
+ ! #if defined(CONFIG_CTEX_DBGLIB)
+ ! 	/* add special envp */
+ ! 	retval = ctexdbg_get_subenvp((char*)file->f_dentry->d_name.name, bprm);
+ ! 	if (retval < 0) 
+ ! 		goto out; 
+ ! #endif /* CONFIG_CTEX_DBGLIB */	
+   	retval = copy_strings(bprm->argc, argv, bprm);
+   	if (retval < 0)
+   		goto out;
+ ***************
+ *** 1536,1541 ****
+ --- 1549,1556 ----
+   	if (retval < 0)
+   		goto out;
+   
+ + 	ctx_ev_file_system(CTX_EV_FILE_SYSTEM_EXEC,0,strlen(filename),filename);	
+ + 	
+   	/* execve succeeded */
+   	current->fs->in_exec = 0;
+   	current->in_execve = 0;
+ diff -crN linux-3.2.1_o/fs/ioctl.c linux-3.2.1/fs/ioctl.c
+ *** linux-3.2.1_o/fs/ioctl.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/fs/ioctl.c	2014-11-14 21:03:15.650351676 +0900
+ ***************
+ *** 15,20 ****
+ --- 15,21 ----
+   #include <linux/writeback.h>
+   #include <linux/buffer_head.h>
+   #include <linux/falloc.h>
+ + #include <linux/ctexdbg.h>
+   
+   #include <asm/ioctls.h>
+   
+ ***************
+ *** 610,616 ****
+   	filp = fget_light(fd, &fput_needed);
+   	if (!filp)
+   		goto out;
+ ! 
+   	error = security_file_ioctl(filp, cmd, arg);
+   	if (error)
+   		goto out_fput;
+ --- 611,617 ----
+   	filp = fget_light(fd, &fput_needed);
+   	if (!filp)
+   		goto out;
+ ! 	ctx_ev_file_system(CTX_EV_FILE_SYSTEM_IOCTL,fd,cmd,NULL);
+   	error = security_file_ioctl(filp, cmd, arg);
+   	if (error)
+   		goto out_fput;
+ diff -crN linux-3.2.1_o/fs/open.c linux-3.2.1/fs/open.c
+ *** linux-3.2.1_o/fs/open.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/fs/open.c	2014-11-14 21:03:15.650351676 +0900
+ ***************
+ *** 30,35 ****
+ --- 30,36 ----
+   #include <linux/fs_struct.h>
+   #include <linux/ima.h>
+   #include <linux/dnotify.h>
+ + #include <linux/ctexdbg.h>
+   
+   #include "internal.h"
+   
+ ***************
+ *** 988,993 ****
+ --- 989,995 ----
+   				fsnotify_open(f);
+   				fd_install(fd, f);
+   			}
+ + 		ctx_ev_file_system(CTX_EV_FILE_SYSTEM_OPEN,0,strlen(tmp),tmp);	
+   		}
+   		putname(tmp);
+   	}
+ ***************
+ *** 1079,1084 ****
+ --- 1081,1087 ----
+   	filp = fdt->fd[fd];
+   	if (!filp)
+   		goto out_unlock;
+ + 	ctx_ev_file_system(CTX_EV_FILE_SYSTEM_CLOSE,fd,0,NULL);
+   	rcu_assign_pointer(fdt->fd[fd], NULL);
+   	FD_CLR(fd, fdt->close_on_exec);
+   	__put_unused_fd(files, fd);
+ diff -crN linux-3.2.1_o/fs/read_write.c linux-3.2.1/fs/read_write.c
+ *** linux-3.2.1_o/fs/read_write.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/fs/read_write.c	2014-11-14 21:03:15.650351676 +0900
+ ***************
+ *** 15,20 ****
+ --- 15,21 ----
+   #include <linux/syscalls.h>
+   #include <linux/pagemap.h>
+   #include <linux/splice.h>
+ + #include <linux/ctexdbg.h>
+   #include "read_write.h"
+   
+   #include <asm/uaccess.h>
+ ***************
+ *** 245,250 ****
+ --- 246,252 ----
+   		if (res != (loff_t)retval)
+   			retval = -EOVERFLOW;	/* LFS: should only happen on 32 bit platforms */
+   	}
+ + 	ctx_ev_file_system(CTX_EV_FILE_SYSTEM_SEEK,fd,offset,NULL);
+   	fput_light(file, fput_needed);
+   bad:
+   	return retval;
+ ***************
+ *** 466,471 ****
+ --- 468,474 ----
+   	file = fget_light(fd, &fput_needed);
+   	if (file) {
+   		loff_t pos = file_pos_read(file);
+ + 		ctx_ev_file_system(CTX_EV_FILE_SYSTEM_READ,fd,count,NULL);
+   		ret = vfs_read(file, buf, count, &pos);
+   		file_pos_write(file, pos);
+   		fput_light(file, fput_needed);
+ ***************
+ *** 485,490 ****
+ --- 488,494 ----
+   	if (file) {
+   		loff_t pos = file_pos_read(file);
+   		ret = vfs_write(file, buf, count, &pos);
+ + 		ctx_ev_file_system(CTX_EV_FILE_SYSTEM_WRITE,fd,count,NULL);		
+   		file_pos_write(file, pos);
+   		fput_light(file, fput_needed);
+   	}
+ diff -crN linux-3.2.1_o/fs/select.c linux-3.2.1/fs/select.c
+ *** linux-3.2.1_o/fs/select.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/fs/select.c	2014-11-14 21:03:15.650351676 +0900
+ ***************
+ *** 26,31 ****
+ --- 26,32 ----
+   #include <linux/fs.h>
+   #include <linux/rcupdate.h>
+   #include <linux/hrtimer.h>
+ + #include <linux/ctexdbg.h>
+   
+   #include <asm/uaccess.h>
+   
+ ***************
+ *** 450,455 ****
+ --- 451,457 ----
+   				file = fget_light(i, &fput_needed);
+   				if (file) {
+   					f_op = file->f_op;
+ + 					ctx_ev_file_system(CTX_EV_FILE_SYSTEM_SELECT,i,(u32)timed_out,NULL);	
+   					mask = DEFAULT_POLLMASK;
+   					if (f_op && f_op->poll) {
+   						wait_key_set(wait, in, out, bit);
+ ***************
+ *** 737,742 ****
+ --- 739,745 ----
+   		mask = POLLNVAL;
+   		if (file != NULL) {
+   			mask = DEFAULT_POLLMASK;
+ + 			ctx_ev_file_system(CTX_EV_FILE_SYSTEM_POLL,fd,0,NULL);
+   			if (file->f_op && file->f_op->poll) {
+   				if (pwait)
+   					pwait->key = pollfd->events |
+ diff -crN linux-3.2.1_o/include/linux/ctexdbg.h linux-3.2.1/include/linux/ctexdbg.h
+ *** linux-3.2.1_o/include/linux/ctexdbg.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/include/linux/ctexdbg.h	2014-11-14 21:03:15.650351676 +0900
+ ***************
+ *** 0 ****
+ --- 1,316 ----
+ + /*
+ +  * linux/include/linux/ctexdbg.h
+ +  *
+ +  * (C) Copyright 2004 - Computex co.,ltd.
+ +  *
+ +  * Computex dbglib support kernel thread
+ +  *
+ +  * -- version info --------------------------------------------------
+ +  *
+ +  * version 015   - 2014/01/20	 update patch version
+ +  *                               + support Linux 3.11.xx
+ +  *                               + fix process break
+ +  *
+ +  * version 014   - 2008/07/18	 update patch version
+ +  *                               + change process trace
+ +  *                               + cleanup code
+ +  *                               + support Linux 2.6.22.1
+ +  *
+ +  * version 013   - 2008/04/10	 update patch version
+ +  *                               + fix loadable module install
+ +  *
+ +  * version 012   - 2007/07/26	 update patch version
+ +  *                               + add selective user-mode fake xip (cramfs)
+ +  *				 + support Linux 2.6.21
+ +  *
+ +  * version 011   - 2007/06/30	update patch version
+ +  *								 + support SMP Kern
+ +  *                               + add file operation buffer
+ +  *                               + add monitor buffer
+ +  *                               + fix: sleep_on -> wait_event
+ +  *
+ +  * version 009_6 - 2007/01/17	update patch version
+ +  *								 + addandfix: ctexdbg_do_check_page
+ +  *								 + support Linux 2.6.14 and 16 
+ +  *
+ +  * version 009_5 - 2007/01/13	update patch version
+ +  * 								 + support user-mode fake XIP (cramfs)
+ +  * 								 + fix: strict findfile
+ +  * 								 + fix: a lot of warning
+ +  *
+ +  * version 009 - 2006/04/xx		update patch version
+ +  * 								 + support PALMiCE 2H mode
+ +  *                                 + add ctexdbg_hardware_trace_enabled
+ +  *                                 + change ctexdbg_schedchange_event
+ +  *
+ +  * version 008 - 2005/12/xx		update patch version
+ +  * 								support file rename chmod chown
+ +  *								add CTEXDBG_EV_PREMAIN event
+ +  *								support linux 2.6.x
+ +  *
+ +  * version 007 - 2005/11/xx		update patch version
+ +  *
+ +  * version 006 - 2005/05/xx		update patch version
+ +  *								 + change ctexdbg_event
+ +  *								 + Add process exit throw mode
+ +  *								 + Add check load module debug file list
+ +  *
+ +  * version 005 - 2005/02/23		first release version
+ +  *								 + Add version 
+ +  *								 + CONFIG_TRACE_MODULE option support
+ +  *
+ +  * version 004 - 2005/02/1x		pre version
+ +  *
+ +  * -------------------------------------------------------------------
+ +  *
+ +  */
+ + 
+ + #ifndef _LINUX_CTEXDBG_H
+ + #define _LINUX_CTEXDBG_H
+ + 
+ + #include <linux/types.h>
+ + 
+ + /* Is defined me ? */
+ + #if defined(CONFIG_CTEX_DBGLIB)
+ + 
+ + /* Patch Version */
+ + #define CTEXDBG_PATCH_VERSION	"015"
+ + 
+ + 
+ + /* process breakpoint max */
+ + #define CTEXDBG_PBP_MAX	256
+ + #define CTEXDBG_PGOFF_MAX	256
+ + #define CTEXDBG_MODULE_MAX 256
+ + 
+ + /* internal buffer size */
+ + #define CTEXDBG_WORKBUF_START 20
+ + #define CTEXDBG_WORKBUF_SIZE 1024
+ + #define CTEXDBG_WORKBUF_END (CTEXDBG_WORKBUF_SIZE - CTEXDBG_WORKBUF_START - 1)
+ + 
+ + /* event buffer size */
+ + #define CTEXDBG_EVENTBUF_SIZE	50000
+ + 
+ + /* num of Debug process */
+ + #define CTEXDBG_PIDSIZE_MAX		512
+ + 
+ + #define CTEXDBG_DBG_FNAMESIZE	2000
+ + #define CTEXDBG_MMAPDATA_SIZE	256
+ + #define CTEXDBG_EVENT_FNAMESIZE	2000
+ + #define CTEXTRC_MASK_SIZE 80
+ + 
+ + 
+ + enum CTEXDBG_ICEFunction
+ + {
+ + 	CTEXDBG_NONE	= 0,		/* Noop */
+ + 	CTEXDBG_DBGPUT,				/* printk a ctexdbg_combuf (internal-debugging) */
+ + 	CTEXDBG_SENDSIG,			/* signal send to process */
+ + 	CTEXDBG_CONTINUE,			/* continue a braek process */
+ + 	CTEXDBG_FORCEBREAK,			/* force braek process */
+ + 	CTEXDBG_LTTRACE_START,		/* start LTTrace */
+ + 	CTEXDBG_LTTRACE_STOP,		/* stop LTTrace */
+ + 	CTEXDBG_EVENT_SETBUFSIZE,	/* Event buffersize reset */
+ + 	CTEXDBG_FILE_LS,			/* Enum Directory list */
+ + 	CTEXDBG_FILE_RMDIR,			/* rmdir */
+ + 	CTEXDBG_FILE_MKDIR,			/* mkdir */
+ + 	CTEXDBG_FILE_DELETE,		/* delete target fs data */
+ + 	CTEXDBG_FILE_READ,			/* read target fs data to HOST */
+ + 	CTEXDBG_FILE_WRITE,			/* write host file data to target fs */
+ + 	CTEXDBG_TEST,				/* funciton test */
+ + 	CTEXDBG_FILE_RENAME,		/* Rename file/Dir */
+ + 	CTEXDBG_FILE_CHMOD,			/* Change attributes of file/Dir */
+ + 	CTEXDBG_FILE_CHOWN,			/* Change Owner */	
+ + };
+ + 
+ + enum CTEXDBG_EVENTINFO
+ + {
+ + 	CTEXDBG_EV_NONE	= 0,		/* Noop */
+ + 	CTEXDBG_EV_FORK,			/* forking */
+ + 	CTEXDBG_EV_SIGNAL,			/* signal recv */
+ + 	CTEXDBG_EV_EXECVP,			/* execute process */
+ + 	CTEXDBG_EV_PBREAK_WAKEUP,	/* processbreak wakeup */
+ + 	CTEXDBG_EV_PBREAK_FBREAK,	/* force break */
+ + 	CTEXDBG_EV_NOPAGE,			/* no page */
+ + 	CTEXDBG_EV_PBREAK_FBREAK_WAKEUP,	/* force break wakeup */
+ + 	CTEXDBG_EV_SIGNAL_WAKEUP,		/* signal braek wakeup */
+ + 	CTEXDBG_EV_LTTFULL,		/* ltt buffre full */
+ + 	CTEXDBG_EV_FILEMAP,		/* file mapping */
+ + 	CTEXDBG_EV_WAITDATA,	/* data wait */
+ + 	CTEXDBG_EV_EXIT,		/* exit program */
+ + 	CTEXDBG_EV_MODULE_INIT,  /* modukle preload */
+ + 	CTEXDBG_EV_EVENTFULL,	/* event buffre full */
+ + 	CTEXDBG_EV_EXIT_WAIT,	/* exit() wait */
+ + 	CTEXDBG_EV_EXIT_WAKEUP,	/* exit() wait wakeup */
+ + 	CTEXDBG_EV_FILE_LSFULL,	/* file lsdata full*/
+ + 	CTEXDBG_EV_FILE_READ,	/* target file read. send to host */
+ + 	CTEXDBG_EV_FILE_WRITE,	/* file recv from target. file writing */
+ + 	CTEXDBG_EV_FILE_END,	/* end of file operate */
+ + 	CTEXDBG_EV_EVENTSET_END,	/* end of ctexdbg event setting */		
+ + 	CTEXDBG_EV_LTTRACE_STARTACK,	/* ltt start ack */		
+ + 	CTEXDBG_EV_FORK_S,			/* forkint(nochkmode) */
+ + 	CTEXDBG_EV_ICECONNECT,		/* ICE Connection OK */
+ + 	CTEXDBG_EV_PREMAIN,		/* main() func pre break */
+ + 	CTEXDBG_EV_EXT_TRAP,	/* External trap break */
+ + 	CTEXDBG_EV_MIGRATION,	/* migration CPU break */
+ + };
+ + 
+ + 
+ + /* ctexdbg fixeddata */
+ + typedef struct __tag_ctexdbg_fixdata
+ + {
+ + 	uint32_t maxsigno;			/* max signal number */
+ + 	uint32_t userregaddr;		/* user register base addr */
+ + 	/* v006 max size define*/
+ + 	uint32_t maxdbgfilelen;		/* max ctexdbgdgbfile length */
+ + 	uint32_t maxmapdatalen;		/* max mapdata length */
+ + 	uint32_t maxevtasklen;		/* max ctexdbg_eventtskname length */
+ + 	uint32_t maxtrcmasklen;		/* max cdbtrc_mask_table length */
+ + 	/* v015 memory map data */
+ + 	uint32_t mem_is_highmem;	/* use highmem=1 */
+ + 	uint32_t mem_is_highpte;	/* use highpte=1 */
+ + 	uint32_t mem_is_lpae;		/* use LPAE=1 */
+ + 	uint32_t mem_lowmem_start;	/* low memory start */
+ + 	uint32_t mem_lowmem_end;	/* low memory end */
+ + 	uint32_t mem_highmem_start;	/* higm memory start */
+ + 	uint32_t mem_highmem_end;	/* higm memory end */
+ + 	uint32_t mem_vmalloc_start;	/* vmalloc start */
+ + 	uint32_t mem_vmalloc_end;	/* vmalloc end */
+ + 	uint32_t mem_modules_start;	/* module start */
+ + 	uint32_t mem_modules_end;	/* module end */
+ + 	uint32_t mem_page_offset;	/* page_offset */
+ + 	uint32_t mem_phys_offset;	/* phys_offset */
+ + }ctexdbg_fix;
+ + 
+ + 
+ + /* check page in area */
+ + typedef struct __tag_ctexdbg_checkarea
+ + {
+ + 	uint32_t address;			/* address (virtual) */
+ + 	uint32_t pid;				/* process id */
+ + 	uint32_t pgd;				/* process pgd */
+ + }ctexdbg_checkarea;
+ + 
+ + typedef struct __tag_cdbtrc_bufpos
+ + {
+ + 	char* sEventBuf;                  /* Event Buffer */
+ + 	char* sEventWritPos;              /* Current position for writting */
+ + 	char* sEventReadPos;              /* Current position for reading */
+ + 	char* sEventWritLimit;            /* Limit at which write should stop */	
+ + 	uint32_t  sEventBufDir;			  /* Buffer dir */
+ + }cdbtrc_bufpos;
+ + 
+ + typedef struct __tag_ctexdbg_mmap
+ + {
+ + 	uint32_t virtaddr;
+ + 	uint32_t physaddr;
+ + 	uint32_t length;
+ + }ctexdbg_mmap;
+ + 
+ + /* module symbol information */
+ + typedef struct __tag_ctexdbg_modsyms
+ + {
+ + 	struct module *mod;			/* ptr of module */
+ + 	uint32_t start_addr;			/* start text address */
+ + 	uint32_t symtab_addr;			/* symbol table address */
+ + 	uint32_t numsym;			/* number of symbol */
+ + 	uint32_t strtab_addr;			/* string table address */
+ + 	uint32_t rodata_addr;			/* rodata section address */
+ + 	uint32_t data_addr;			/* data section address */
+ + 	uint32_t bss_addr;			/* bss section address */
+ + }ctexdbg_modsyms;
+ + 
+ + /* debug process information */
+ + typedef struct __tag_ctexdbg_debugproc
+ + {
+ + 	uint32_t pid;					/* process pid */
+ + 	uint32_t migration;				/* migrationcheck flag */
+ + }ctexdbg_debugproc;
+ + 
+ + 
+ + /* global */
+ + extern ctexdbg_fix ctexdbg_fixdata; /* kctexdbgd control data */
+ + extern uint32_t ctexdbg_EventBufSize;
+ + extern uint32_t ctexdbg_EventUse;
+ + extern uint32_t ctexdbg_enabled;
+ + extern uint32_t ctexdbg_hardware_trace_enabled;
+ + 
+ + /* pidchange data */
+ + extern uint32_t ctexdbg_prevpid;
+ + extern uint32_t ctexdbg_nextpid;
+ + 
+ + /* arch depend */
+ + extern void ctexdbg_event_core(void);
+ + extern void ctexdbg_arch_userregaddr(void);
+ + extern int ctexdbg_arch_checkice(void);
+ + extern void ctexdbg_print_context_reg(struct pt_regs *regs);
+ + extern int ctexdbg_arch_init(void);
+ + extern unsigned long ctexdbg_arch_lock_kernel(void);
+ + extern void ctexdbg_arch_unlock_kernel(unsigned long oldval);
+ + 
+ + extern void ctexdbg_add_memmap(unsigned long virt,unsigned long phys,unsigned long length);
+ + 
+ + extern void ctexdbg_filemap(struct vm_area_struct * vma);
+ + extern ctexdbg_debugproc* ctexdbg_find_debugpid(uint32_t pid);
+ + extern int ctexdbg_find_file(char *fname,char* finder,int findersize);
+ + extern int ctexdbg_find_file_xip(char *fname,char* finder,int findersize);
+ + extern int ctexdbg_varid_dname(struct mm_struct *mm);
+ + 
+ + 
+ + /* module event */
+ + extern int ctexdbg_module_init(struct module *mod);
+ + extern int ctexdbg_module_install(struct module *mod,void *ehdrs,void *sechdrs,const char* secstrings,uint32_t symindex,uint32_t strindex);
+ + extern int ctexdbg_module_remove(struct module *mod);
+ + 
+ + /* Library injection */
+ + //char **ctexdbg_get_subenvp(int *envc,char *filename);
+ + int ctexdbg_get_subenvp(char *filename, void *bprm);
+ + 
+ + /* event notify */
+ + void ctexdbg_external_notify(size_t size,void *ptr);
+ + void ctexdbg_eventfull_bp(void);
+ + void ctexdbg_event_init(void);
+ + extern int ctexdbg_event_set_buffer_size(int pmSize);
+ + 
+ + /* LTT tracer hook */
+ + #if defined(CONFIG_CTEX_TRACE)
+ + extern void ctexdbg_tracer(uint8_t pmEventID,void* pmEventStruct);
+ + extern int  ctexdbg_tracer_start(uint32_t nbuffersize,uint32_t oneshot);
+ + extern void ctexdbg_tracer_stop(void);
+ + extern void ctexdbg_tracer_init(void);
+ + #else
+ + #define ctexdbg_tracer(a,b)
+ + #define ctexdbg_tracer_start(a,b)
+ + #define ctexdbg_tracer_stop()
+ + #define ctexdbg_tracer_init()
+ + #endif /* defined(CONFIG_CTEX_TRACE) */
+ + 
+ + extern void ctexdbg_lttfull_bp(void);
+ + 
+ + /* LTT data */
+ + extern int ctexdbg_traceuse; 		/* LTT trace enable */
+ + 
+ + /* prototype */
+ + extern int ctexdbg_forcebreak(struct task_struct *tsk);
+ + extern int ctexdbg_checkwakeup(void);
+ + extern void ctexdbg_do_no_page(struct vm_area_struct * vma,unsigned long address);
+ + 
+ + extern int ctexdbg_forking(struct task_struct *tsk,unsigned long clone_flags,unsigned long stack_start);
+ + extern int ctexdbg_signals(uint32_t signa,uint32_t pid,struct pt_regs *regs);
+ + extern int ctexdbg_main_pre_brk(struct task_struct *tsk,unsigned long entryaddr,unsigned long ppgd);
+ + 
+ + /* ------------------------ events -------------------------------------*/
+ + extern void ctexdbg_process_exit(void);
+ + extern void ctexdbg_file_event(struct task_struct *tsk,struct file *file,uint32_t pgd);
+ + extern void ctexdbg_migration_check(struct task_struct *tsk ,int src_cpu,int dest_cpu);
+ + 
+ + /* debug print macro */
+ + #define ctexdbg_prn(who, format, arg...)		\
+ + do{							\
+ + 	if(ctexdbg_ddebugevent == 1)			\
+ + 		printk("%s: "format,who, ## arg);	\
+ + }while(0)
+ + 
+ + #endif /* CONFIG_CTEX_DBGLIB */
+ + 
+ + #include <linux/ctextrc.h>
+ + 
+ + #endif /* _LINUX_CTEXDBG_H */
+ diff -crN linux-3.2.1_o/include/linux/ctextrc.h linux-3.2.1/include/linux/ctextrc.h
+ *** linux-3.2.1_o/include/linux/ctextrc.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/include/linux/ctextrc.h	2014-11-14 21:03:15.654351676 +0900
+ ***************
+ *** 0 ****
+ --- 1,355 ----
+ + /*
+ +  * linux/include/linux/ctextrc.h
+ +  *
+ +  * (C) Copyright 2006 - Computex co.,ltd.
+ +  *
+ +  * Computex dbglib support ltt-ng
+ +  *  LTT-ng to ctextrc style transfer
+ +  * -- version info --------------------------------------------------
+ +  *
+ +  * version 0014 - 2008/05/xx	reborn
+ +  *
+ +  * -------------------------------------------------------------------
+ +  *
+ +  */
+ + 
+ + #ifndef _LINUX_CTEXTRC_H_
+ + #define _LINUX_CTEXTRC_H_
+ + 
+ + #include <linux/types.h>
+ + 
+ + /* Is defined me ? */
+ + #if defined(CONFIG_CTEX_TRACE)
+ + 
+ + #define CTX_PACKED_STRUCT __attribute__ ((packed))
+ + 
+ + /* Traced events */
+ + enum {
+ + 	CTX_EV_START = 0,	/* This is to mark the trace's start */
+ + 	CTX_EV_SYSCALL_ENTRY,	/* Entry in a given system call */
+ + 	CTX_EV_SYSCALL_EXIT,	/* Exit from a given system call */
+ + 	CTX_EV_TRAP_ENTRY,	/* Entry in a trap */
+ + 	CTX_EV_TRAP_EXIT,	/* Exit from a trap */
+ + 	CTX_EV_IRQ_ENTRY,	/* Entry in an irq */
+ + 	CTX_EV_IRQ_EXIT,	/* Exit from an irq */
+ + 	CTX_EV_SCHEDCHANGE,	/* Scheduling change */
+ + 	CTX_EV_KERNEL_TIMER,	/* The kernel timer routine has been called */
+ + 	CTX_EV_SOFT_IRQ,	/* Hit key part of soft-irq management */
+ + 	CTX_EV_PROCESS,		/* Hit key part of process management */
+ + 	CTX_EV_FILE_SYSTEM,	/* Hit key part of file system */
+ + 	CTX_EV_TIMER,		/* Hit key part of timer management */
+ + 	CTX_EV_MEMORY,		/* Hit key part of memory management */
+ + 	CTX_EV_SOCKET,		/* Hit key part of socket communication */
+ + 	CTX_EV_IPC,		/* Hit key part of System V IPC */
+ + 	CTX_EV_NETWORK,		/* Hit key part of network communication */
+ + 	CTX_EV_BUFFER_START,	/* Mark the begining of a trace buffer */
+ + 	CTX_EV_BUFFER_END,	/* Mark the ending of a trace buffer */
+ + };
+ + 
+ + /* Number of traced events */
+ + #define CTX_EV_MAX		CTX_EV_BUFFER_END
+ + 
+ + /*  LTT_SYSCALL_ENTRY */
+ + typedef struct _ctx_syscall_entry {
+ + 	u16   syscall_id;		/* Syscall entry number in entry.S */
+ + 	ulong address;		/* Address from which call was made */
+ + } CTX_PACKED_STRUCT ctx_syscall_entry;
+ + #define ctx_ev_syscall_entry(ID,DATA) \
+ + do{ \
+ + 	if(ctexdbg_traceuse != 0){ \
+ + 		ctx_syscall_entry si; \
+ + 		si.syscall_id = (u16)ID; \
+ + 		si.address = (ulong)DATA; \
+ + 		ctexdbg_tracer((uint8_t)CTX_EV_SYSCALL_ENTRY, (void*)&si); \
+ + } \
+ + }while(0);
+ + 
+ + #define ctx_ev_syscall_exit()\
+ + do{ \
+ + 	ctexdbg_tracer((uint8_t)CTX_EV_SYSCALL_EXIT, NULL); \
+ + }while(0);
+ + 
+ + 
+ + /*  LTT_TRAP_ENTRY */
+ + typedef struct _ctx_trap_entry {
+ + 	u16   trap_id;		/* Trap number */
+ + 	ulong address;		/* Address where trap occured */
+ + } CTX_PACKED_STRUCT ctx_trap_entry;
+ + #define ctx_ev_trap_entry(ID,DATA) \
+ + do{ \
+ + 	if(ctexdbg_traceuse != 0){ \
+ + 		ctx_trap_entry trap_event; \
+ + 		trap_event.trap_id = ID; \
+ + 		trap_event.address = DATA; \
+ + 		ctexdbg_tracer((uint8_t)CTX_EV_TRAP_ENTRY, (void*)&trap_event); \
+ + 	}\
+ + }while(0);
+ + 
+ + /*  LTT_TRAP_EXIT */
+ + #define ctx_ev_trap_exit() \
+ + do{ \
+ + 	if(ctexdbg_traceuse != 0){ \
+ + 		ctexdbg_tracer((uint8_t)CTX_EV_TRAP_EXIT, NULL); \
+ + 	} \
+ + }while(0);
+ + 
+ + /*  LTT_IRQ_ENTRY */
+ + typedef struct _ctx_irq_entry {
+ + 	u16 irq_id;		/* IRQ number */
+ + 	u8  kernel;		/* Are we executing kernel code */
+ + } CTX_PACKED_STRUCT ctx_irq_entry;
+ + #define ctx_ev_irq_entry(ID,DATA) \
+ + do{ \
+ + 	if(ctexdbg_traceuse != 0){ \
+ + 		ctx_irq_entry irq_entry; \
+ + 		irq_entry.irq_id = ID; \
+ + 		irq_entry.kernel = DATA; \
+ + 		ctexdbg_tracer((uint8_t)CTX_EV_IRQ_ENTRY, (void*)&irq_entry); \
+ + 	} \
+ + }while(0);
+ + 
+ + /*  LTT_IRQ_EXIT */
+ + #define ctx_ev_irq_exit() \
+ + do{ \
+ + 	if(ctexdbg_traceuse != 0){ \
+ + 		ctexdbg_tracer((uint8_t)CTX_EV_IRQ_EXIT, NULL); \
+ + 	} \
+ + }while(0); 
+ + 
+ + /*  LTT_SCHEDCHANGE */
+ + typedef struct _ctx_schedchange {
+ + 	u32 out;		/* Outgoing process */
+ + 	u32 in;			/* Incoming process */
+ + 	u32 out_state;		/* Outgoing process' state */
+ + } CTX_PACKED_STRUCT ctx_schedchange;
+ + #define ctx_ev_schedchange(OUT,IN,DATA) \
+ + do{ \
+ + 	if(ctexdbg_traceuse != 0){ \
+ + 		ctx_schedchange sched_event; \
+ + 		sched_event.out = OUT; \
+ + 		sched_event.in  = IN; \
+ + 		sched_event.out_state = DATA; \
+ + 		ctexdbg_tracer((uint8_t)CTX_EV_SCHEDCHANGE, (void*)&sched_event); \
+ + 	} \
+ + }while(0); 
+ + 
+ + /*  LTT_SOFT_IRQ */
+ + enum {
+ + 	CTX_EV_SOFT_IRQ_BOTTOM_HALF = 1,	/* Conventional bottom-half */
+ + 	CTX_EV_SOFT_IRQ_SOFT_IRQ,		/* Real soft-irq */
+ + 	CTX_EV_SOFT_IRQ_TASKLET_ACTION,		/* Tasklet action */
+ + 	CTX_EV_SOFT_IRQ_TASKLET_HI_ACTION	/* Tasklet hi-action */
+ + };
+ + typedef struct _ctx_soft_irq {
+ + 	u8    event_sub_id;	/* Soft-irq event Id */
+ + 	ulong event_data;
+ + } CTX_PACKED_STRUCT ctx_soft_irq;
+ + #define ctx_ctx_ev_soft_irq(ID,DATA) \
+ + do{ \
+ + 	if(ctexdbg_traceuse != 0){ \
+ + 		ctx_soft_irq soft_irq_event; \
+ + 		soft_irq_event.event_sub_id = ID; \
+ + 		soft_irq_event.event_data = DATA; \
+ + 		ctexdbg_tracer((uint8_t)CTX_EV_SOFT_IRQ, (void*)&soft_irq_event); \
+ + 	} \
+ + }while(0); 
+ + 
+ + /*  LTT_PROCESS */
+ + enum {
+ + 	CTX_EV_PROCESS_KTHREAD = 1,	/* Creation of a kernel thread */
+ + 	CTX_EV_PROCESS_FORK,		/* A fork or clone occured */
+ + 	CTX_EV_PROCESS_EXIT,		/* An exit occured */
+ + 	CTX_EV_PROCESS_WAIT,		/* A wait occured */
+ + 	CTX_EV_PROCESS_SIGNAL,		/* A signal has been sent */
+ + 	CTX_EV_PROCESS_WAKEUP		/* Wake up a process */
+ + };
+ + typedef struct _ctx_process {
+ + 	u8    event_sub_id;	/* Process event ID */
+ + 	u32   event_data1;
+ + 	ulong event_data2;
+ + } CTX_PACKED_STRUCT ctx_process;
+ + #define ctx_ev_process(ID,DATA,DATA2) \
+ + do{ \
+ + 	if(ctexdbg_traceuse != 0){	\
+ + 		ctx_process proc_event; \
+ + 		proc_event.event_sub_id = ID; \
+ + 		proc_event.event_data1 = DATA; \
+ + 		proc_event.event_data2 = DATA2; \
+ + 		ctexdbg_tracer((uint8_t)CTX_EV_PROCESS, (void*)&proc_event); \
+ + 	} \
+ + }while(0); 
+ + 
+ + #define ctx_ev_process_exit() \
+ + do{ \
+ + 	if(ctexdbg_traceuse != 0){	\
+ + 		ctx_process proc_event;	\
+ + 		proc_event.event_sub_id = CTX_EV_PROCESS_EXIT; \
+ + 		ctexdbg_tracer((uint8_t)CTX_EV_PROCESS, (void*)&proc_event); \
+ + 	} \
+ + }while(0);
+ + 
+ + /*  LTT_FILE_SYSTEM */
+ + enum {
+ + 	CTX_EV_FILE_SYSTEM_BUF_WAIT_START = 1,	/* Starting to wait for a data buffer */
+ + 	CTX_EV_FILE_SYSTEM_BUF_WAIT_END,	/* End to wait for a data buffer */
+ + 	CTX_EV_FILE_SYSTEM_EXEC,		/* An exec occured */
+ + 	CTX_EV_FILE_SYSTEM_OPEN,		/* An open occured */
+ + 	CTX_EV_FILE_SYSTEM_CLOSE,		/* A close occured */
+ + 	CTX_EV_FILE_SYSTEM_READ,		/* A read occured */
+ + 	CTX_EV_FILE_SYSTEM_WRITE,		/* A write occured */
+ + 	CTX_EV_FILE_SYSTEM_SEEK,		/* A seek occured */
+ + 	CTX_EV_FILE_SYSTEM_IOCTL,		/* An ioctl occured */
+ + 	CTX_EV_FILE_SYSTEM_SELECT,		/* A select occured */
+ + 	CTX_EV_FILE_SYSTEM_POLL			/* A poll occured */
+ + };
+ + typedef struct _ctx_file_system {
+ + 	u8 event_sub_id;	/* File system event ID */
+ + 	u32 event_data1;
+ + 	u32 event_data2;
+ + 	char *file_name;	/* Name of file operated on */
+ + } CTX_PACKED_STRUCT ctx_file_system;
+ + #define ctx_ev_file_system(ID,DATA,DATA2,FNAME) \
+ + do{ \
+ + 	if(ctexdbg_traceuse != 0){	\
+ + 		ctx_file_system fs_event; \
+ + 		fs_event.event_sub_id = ID; \
+ + 		fs_event.event_data1 = DATA; \
+ + 		fs_event.event_data2 = DATA2; \
+ + 		fs_event.file_name = (char*) FNAME; \
+ + 		ctexdbg_tracer((uint8_t)CTX_EV_FILE_SYSTEM, (void*)&fs_event); \
+ + 	} \
+ + }while(0);
+ + 
+ + /*  LTT_TIMER */
+ + enum {
+ + 	CTX_EV_TIMER_EXPIRED = 1,	/* Timer expired */
+ + 	CTX_EV_TIMER_SETITIMER,		/* Setting itimer occurred */
+ + 	CTX_EV_TIMER_SETTIMEOUT		/* Setting sched timeout occurred */
+ + };
+ + typedef struct _ctx_timer {
+ + 	u8 event_sub_id;	/* Timer event ID */
+ + 	u8 event_sdata;		/* Short data */
+ + 	ulong event_data1;
+ + 	ulong event_data2;
+ + } CTX_PACKED_STRUCT ctx_timer;
+ + #define ctx_ev_timer(ID,SDATA,DATA,DATA2) \
+ + do{ \
+ + 	if(ctexdbg_traceuse != 0){ \
+ + 		ctx_timer timer_event; \
+ + 		timer_event.event_sub_id = ID; \
+ + 		timer_event.event_sdata = SDATA; \
+ + 		timer_event.event_data1 = DATA; \
+ + 		timer_event.event_data2 = DATA2; \
+ + 		ctexdbg_tracer((uint8_t)CTX_EV_TIMER, (void*)&timer_event); \
+ + 	} \
+ + }while(0);
+ + 
+ + /*  LTT_MEMORY */
+ + enum {
+ + 	CTX_EV_MEMORY_PAGE_ALLOC = 1,	/* Allocating pages */
+ + 	CTX_EV_MEMORY_PAGE_FREE,	/* Freing pages */
+ + 	CTX_EV_MEMORY_SWAP_IN,		/* Swaping pages in */
+ + 	CTX_EV_MEMORY_SWAP_OUT,		/* Swaping pages out */
+ + 	CTX_EV_MEMORY_PAGE_WAIT_START,	/* Start to wait for page */
+ + 	CTX_EV_MEMORY_PAGE_WAIT_END	/* End to wait for page */
+ + };
+ + typedef struct _ctx_memory {
+ + 	u8 event_sub_id;	/* Memory event ID */
+ + 	ulong event_data;
+ + } CTX_PACKED_STRUCT ctx_memory;
+ + #define ctx_ev_memory(ID,DATA) \
+ + do{ \
+ + 	if(ctexdbg_traceuse != 0){	\
+ + 		ctx_memory memory_event; \
+ + 		memory_event.event_sub_id = ID; \
+ + 		memory_event.event_data = DATA; \
+ + 		ctexdbg_tracer((uint8_t)CTX_EV_MEMORY, (void*)&memory_event); \
+ + 	} \
+ + }while(0);
+ + 
+ + /*  LTT_SOCKET */
+ + enum {
+ + 	CTX_EV_SOCKET_CALL = 1,	/* A socket call occured */
+ + 	CTX_EV_SOCKET_CREATE,	/* A socket has been created */
+ + 	CTX_EV_SOCKET_SEND,	/* Data was sent to a socket */
+ + 	CTX_EV_SOCKET_RECEIVE	/* Data was read from a socket */
+ + };
+ + typedef struct _ctx_socket {
+ + 	u8 event_sub_id;	/* Socket event ID */
+ + 	u32 event_data1;
+ + 	ulong  event_data2;
+ + } CTX_PACKED_STRUCT ctx_socket;
+ + #define ctx_ev_socket(ID,DATA,DATA2) \
+ + do{ \
+ + 	if(ctexdbg_traceuse != 0){ \
+ + 		ctx_socket socket_event; \
+ + 		socket_event.event_sub_id = ID; \
+ + 		socket_event.event_data1 = DATA; \
+ + 		socket_event.event_data2 = DATA2; \
+ + 		ctexdbg_tracer((uint8_t)CTX_EV_SOCKET, (void*)&socket_event); \
+ + 	} \
+ + }while(0);
+ + 
+ + /*  LTT_IPC */
+ + enum {
+ + 	CTX_EV_IPC_CALL = 1,	/* A System V IPC call occured */
+ + 	CTX_EV_IPC_MSG_CREATE,	/* A message queue has been created */
+ + 	CTX_EV_IPC_SEM_CREATE,	/* A semaphore was created */
+ + 	CTX_EV_IPC_SHM_CREATE	/* A shared memory segment has been created */
+ + };
+ + typedef struct _ctx_ipc {
+ + 	u8 event_sub_id;	/* IPC event ID */
+ + 	u32 event_data1;
+ + 	u32 event_data2;
+ + } CTX_PACKED_STRUCT ctx_ipc;
+ + #define ctx_ev_ipc(ID,DATA,DATA2) \
+ + do{ \
+ + 	if(ctexdbg_traceuse != 0){	\
+ + 		ctx_ipc ipc_event; \
+ + 		ipc_event.event_sub_id = ID; \
+ + 		ipc_event.event_data1 = DATA; \
+ + 		ipc_event.event_data2 = DATA2; \
+ + 		ctexdbg_tracer((uint8_t)CTX_EV_IPC, (void*)&ipc_event); \
+ + 	} \
+ + }while(0);
+ + 
+ + /*  LTT_NETWORK */
+ + enum {
+ + 	CTX_EV_NETWORK_PACKET_IN = 1,	/* A packet came in */
+ + 	CTX_EV_NETWORK_PACKET_OUT	/* A packet was sent */
+ + };
+ + typedef struct _ctx_network {
+ + 	u8 event_sub_id;	/* Network event ID */
+ + 	u32 event_data;
+ + } CTX_PACKED_STRUCT ctx_network;
+ + #define ctx_ev_network(ID,DATA) \
+ + do{ \
+ + 	if(ctexdbg_traceuse != 0){ \
+ + 		ctx_network net_event; \
+ + 		net_event.event_sub_id = ID; \
+ + 		net_event.event_data = DATA; \
+ + 		ctexdbg_tracer((uint8_t)CTX_EV_NETWORK, (void*)&net_event); \
+ + 	} \
+ + }while(0);
+ + 
+ + #else /* defined(CONFIG_CTEX_TRACE) */
+ + 
+ + #define ctx_ev_syscall_entry(ID,DATA)
+ + #define ctx_ev_syscall_exit()
+ + #define ctx_ev_trap_entry(ID, EIP)
+ + #define ctx_ev_trap_exit()
+ + #define ctx_ev_irq_entry(ID, KERNEL)
+ + #define ctx_ev_irq_exit()
+ + #define ctx_ev_schedchange(OUT, IN, DATA)
+ + #define ctx_ev_soft_irq(ID, DATA)
+ + #define ctx_ev_process(ID, DATA1, DATA2)
+ + #define ctx_ev_process_exit()
+ + #define ctx_ev_file_system(ID, DATA1, DATA2, FILE_NAME)
+ + #define ctx_ev_timer(ID, SDATA, DATA1, DATA2)
+ + #define ctx_ev_memory(ID, DATA)
+ + #define ctx_ev_socket(ID, DATA1, DATA2)
+ + #define ctx_ev_ipc(ID, DATA1, DATA2)
+ + #define ctx_ev_network(ID, DATA)
+ + #endif /* defined(CONFIG_CTEX_TRACE) */
+ + 
+ + #endif /* _LINUX_CTEXTRC_H_ */
+ diff -crN linux-3.2.1_o/include/linux/init.h linux-3.2.1/include/linux/init.h
+ *** linux-3.2.1_o/include/linux/init.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/include/linux/init.h	2014-11-14 21:03:15.654351676 +0900
+ ***************
+ *** 40,46 ****
+ --- 40,50 ----
+   
+   /* These are for everybody (although not all archs will actually
+      discard it in modules) */
+ + #if defined (MODULE) && defined(CONFIG_CTEX_DBGLIB_MOD_NOINITEXIT)
+ + #define __init
+ + #else
+   #define __init		__section(.init.text) __cold notrace
+ + #endif
+   #define __initdata	__section(.init.data)
+   #define __initconst	__section(.init.rodata)
+   #define __exitdata	__section(.exit.data)
+ ***************
+ *** 79,85 ****
+ --- 83,93 ----
+   #define __exitused  __used
+   #endif
+   
+ + #if defined (MODULE) && defined(CONFIG_CTEX_DBGLIB_MOD_NOINITEXIT)
+ + #define __exit
+ + #else
+   #define __exit          __section(.exit.text) __exitused __cold notrace
+ + #endif
+   
+   /* Used for HOTPLUG */
+   #define __devinit        __section(.devinit.text) __cold notrace
+ diff -crN linux-3.2.1_o/ipc/msg.c linux-3.2.1/ipc/msg.c
+ *** linux-3.2.1_o/ipc/msg.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/ipc/msg.c	2014-11-14 21:03:15.654351676 +0900
+ ***************
+ *** 37,42 ****
+ --- 37,43 ----
+   #include <linux/rwsem.h>
+   #include <linux/nsproxy.h>
+   #include <linux/ipc_namespace.h>
+ +  #include <linux/ctexdbg.h>
+   
+   #include <asm/current.h>
+   #include <asm/uaccess.h>
+ ***************
+ *** 314,320 ****
+   	struct ipc_namespace *ns;
+   	struct ipc_ops msg_ops;
+   	struct ipc_params msg_params;
+ ! 
+   	ns = current->nsproxy->ipc_ns;
+   
+   	msg_ops.getnew = newque;
+ --- 315,321 ----
+   	struct ipc_namespace *ns;
+   	struct ipc_ops msg_ops;
+   	struct ipc_params msg_params;
+ ! 	int ret = -EPERM;
+   	ns = current->nsproxy->ipc_ns;
+   
+   	msg_ops.getnew = newque;
+ ***************
+ *** 323,330 ****
+   
+   	msg_params.key = key;
+   	msg_params.flg = msgflg;
+ ! 
+ ! 	return ipcget(ns, &msg_ids(ns), &msg_ops, &msg_params);
+   }
+   
+   static inline unsigned long
+ --- 324,332 ----
+   
+   	msg_params.key = key;
+   	msg_params.flg = msgflg;
+ !  	ret = ipcget(ns, &msg_ids(ns), &msg_ops, &msg_params);
+ ! 	ctx_ev_ipc(CTX_EV_IPC_MSG_CREATE,ret,msgflg);
+ ! 	return ret;
+   }
+   
+   static inline unsigned long
+ diff -crN linux-3.2.1_o/ipc/sem.c linux-3.2.1/ipc/sem.c
+ *** linux-3.2.1_o/ipc/sem.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/ipc/sem.c	2014-11-14 21:03:15.654351676 +0900
+ ***************
+ *** 86,91 ****
+ --- 86,92 ----
+   #include <linux/rwsem.h>
+   #include <linux/nsproxy.h>
+   #include <linux/ipc_namespace.h>
+ + #include <linux/ctexdbg.h>
+   
+   #include <asm/uaccess.h>
+   #include "util.h"
+ ***************
+ *** 369,375 ****
+   	struct ipc_namespace *ns;
+   	struct ipc_ops sem_ops;
+   	struct ipc_params sem_params;
+ ! 
+   	ns = current->nsproxy->ipc_ns;
+   
+   	if (nsems < 0 || nsems > ns->sc_semmsl)
+ --- 370,376 ----
+   	struct ipc_namespace *ns;
+   	struct ipc_ops sem_ops;
+   	struct ipc_params sem_params;
+ ! 	int err = -EINVAL;
+   	ns = current->nsproxy->ipc_ns;
+   
+   	if (nsems < 0 || nsems > ns->sc_semmsl)
+ ***************
+ *** 384,389 ****
+ --- 385,393 ----
+   	sem_params.u.nsems = nsems;
+   
+   	return ipcget(ns, &sem_ids(ns), &sem_ops, &sem_params);
+ + 	 err = ipcget(ns, &sem_ids(ns), &sem_ops, &sem_params);
+ + 	ctx_ev_ipc(CTX_EV_IPC_SEM_CREATE,err,semflg);
+ + 	return err;
+   }
+   
+   /*
+ diff -crN linux-3.2.1_o/ipc/shm.c linux-3.2.1/ipc/shm.c
+ *** linux-3.2.1_o/ipc/shm.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/ipc/shm.c	2014-11-14 21:03:15.654351676 +0900
+ ***************
+ *** 39,45 ****
+   #include <linux/nsproxy.h>
+   #include <linux/mount.h>
+   #include <linux/ipc_namespace.h>
+ ! 
+   #include <asm/uaccess.h>
+   
+   #include "util.h"
+ --- 39,45 ----
+   #include <linux/nsproxy.h>
+   #include <linux/mount.h>
+   #include <linux/ipc_namespace.h>
+ ! #include <linux/ctexdbg.h>
+   #include <asm/uaccess.h>
+   
+   #include "util.h"
+ ***************
+ *** 564,570 ****
+   	struct ipc_namespace *ns;
+   	struct ipc_ops shm_ops;
+   	struct ipc_params shm_params;
+ ! 
+   	ns = current->nsproxy->ipc_ns;
+   
+   	shm_ops.getnew = newseg;
+ --- 564,571 ----
+   	struct ipc_namespace *ns;
+   	struct ipc_ops shm_ops;
+   	struct ipc_params shm_params;
+ ! 	int err = -EINVAL;
+ ! 	
+   	ns = current->nsproxy->ipc_ns;
+   
+   	shm_ops.getnew = newseg;
+ ***************
+ *** 575,581 ****
+   	shm_params.flg = shmflg;
+   	shm_params.u.size = size;
+   
+ ! 	return ipcget(ns, &shm_ids(ns), &shm_ops, &shm_params);
+   }
+   
+   static inline unsigned long copy_shmid_to_user(void __user *buf, struct shmid64_ds *in, int version)
+ --- 576,584 ----
+   	shm_params.flg = shmflg;
+   	shm_params.u.size = size;
+   
+ !  	err = ipcget(ns, &shm_ids(ns), &shm_ops, &shm_params);
+ ! 	ctx_ev_ipc(CTX_EV_IPC_SHM_CREATE,err,shmflg);
+ ! 	return err;
+   }
+   
+   static inline unsigned long copy_shmid_to_user(void __user *buf, struct shmid64_ds *in, int version)
+ diff -crN linux-3.2.1_o/kernel/Makefile linux-3.2.1/kernel/Makefile
+ *** linux-3.2.1_o/kernel/Makefile	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/kernel/Makefile	2014-11-14 21:03:15.658351676 +0900
+ ***************
+ *** 109,114 ****
+ --- 109,118 ----
+   obj-$(CONFIG_PADATA) += padata.o
+   obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
+   obj-$(CONFIG_JUMP_LABEL) += jump_label.o
+ + obj-$(CONFIG_CTEX_DBGLIB) += ctexdbg.o
+ + obj-$(CONFIG_CTEX_DBGLIB) += ctexevt.o
+ + obj-$(CONFIG_CTEX_DBGLIB) += ctexfile.o
+ + obj-$(CONFIG_CTEX_TRACE) += ctextrc.o
+   
+   ifneq ($(CONFIG_SCHED_OMIT_FRAME_POINTER),y)
+   # According to Alan Modra <alan@linuxcare.com.au>, the -fno-omit-frame-pointer is
+ diff -crN linux-3.2.1_o/kernel/ctexdbg.c linux-3.2.1/kernel/ctexdbg.c
+ *** linux-3.2.1_o/kernel/ctexdbg.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/kernel/ctexdbg.c	2014-11-14 21:03:15.658351676 +0900
+ ***************
+ *** 0 ****
+ --- 1,1587 ----
+ + /*
+ +  * linux/kernel/ctexdbg.c
+ +  *
+ +  * (C) Copyright 2004 - Computex co.,ltd.
+ +  *
+ +  * Computex dbglib support kernel thread (debug mon)
+ +  *
+ +  * -- version info --------------------------------------------------
+ +  *
+ +  * version 015   - 2014/01/20	 update patch version
+ +  *                               + support Linux 3.11.xx
+ +  *                               + fix process break
+ +  *
+ +  * version 014_6 - 2009/09/04	 update patch version
+ +  *                               + support Linux 2.6.29
+ +  *                               + support Androld
+ +  *
+ +  * version 014_5 - 2009/07/14	 update patch version
+ +  *                               + support Linux 2.6.27
+ +  *
+ +  * version 014_2 - 2008/12/08	 update patch version
+ +  *                               + change ctexdbgd realtime kernel-thread
+ +  * 
+ +  * version 014   - 2008/07/18	 update patch version
+ +  *                               + change process trace
+ +  *                               + cleanup code
+ +  *                               + support Linux 2.6.22.1
+ +  *
+ +  * version 013   - 2008/04/10	 update patch version
+ +  *                               + fix loadable module install
+ +  *
+ +  * version 012   - 2007/07/26	 update patch version
+ +  *                               + add selective user-mode fake xip (cramfs)
+ +  *				 + support Linux 2.6.21
+ +  *
+ +  * version 011   - 2007/06/30	update patch version
+ +  *								 + support SMP Kern
+ +  *                               + add file operation buffer
+ +  *                               + add monitor buffer
+ +  *                               + fix: sleep_on -> wait_event
+ +  *
+ +  * version 009_6 - 2007/01/17	update patch version
+ +  *								 + addandfix: ctexdbg_do_check_page
+ +  *								 + support Linux 2.6.14 and 16 
+ +  *
+ +  * version 009_5 - 2007/01/13	update patch version
+ +  * 								 + support user-mode fake XIP (cramfs)
+ +  * 								 + fix: strict findfile
+ +  * 								 + fix: a lot of warning
+ +  *
+ +  * version 009 - 2006/04/xx		update patch version
+ +  * 								 + support PALMiCE 2H mode
+ +  *                                 + add ctexdbg_hardware_trace_enabled
+ +  *                                 + change ctexdbg_schedchange_event 
+ +  *
+ +  * version 008 - 2005/12/xx		update patch version
+ +  * 								 + support file rename chmod chown
+ +  *								 + add ctexdbg_premain_debug
+ +  *								 + add CTEXDBG_EV_PREMAIN event 
+ +  *								 + suopprt Linux 2.6.10 (mvl4.0 style)
+ +  *
+ +  * version 007 - 2005/11/xx		update patch version
+ +  * 								 + remove fork_s
+ +  * 								 + unuse pexit_no_chk
+ +  *								 + change arg ctexdbg_event()
+ +  *									(by fork event)
+ +  *								 + add ctexdbg_noattach_debug
+ +  *								 + change ctexdbg_filemap
+ +  *
+ +  * version 006 - 2005/08/xx		update patch version
+ +  *								 + change ctexdbg_event
+ +  *								 + Add process exit throw mode
+ +  *								 + Add check load module debug file list
+ +  *								 + change ctextrc
+ +  *								 + change debug process size 128->512
+ +  *								 + change ctexdbg_do_no_page args (addr->vma)
+ +  *								 + remove unuse event
+ +  *
+ +  * version 005 - 2005/02/23		first release version
+ +  *								 + Add version 
+ +  *								 + CONFIG_TRACE_MODULE option support
+ +  *								  + Move LTT buffer init code ctexdbg.c
+ +  *								 + modified arch/xxx/kernel/signal.c
+ +  *								 + add debug process file mode
+ +  *
+ +  * version 004 - 2005/02/1x		pre version
+ +  *
+ +  * -------------------------------------------------------------------
+ +  */
+ + #include <linux/kernel.h>
+ + #include <linux/init.h>     /* For __init */
+ + #include <linux/proc_fs.h>
+ + #include <linux/unistd.h>
+ + #include <linux/version.h>
+ + 
+ + #include <linux/ctexdbg.h>  /* definitions */
+ + #include <linux/errno.h>    /* Miscellaneous error codes */
+ + #include <linux/module.h>   /* EXPORT_SYMBOL */
+ + #include <linux/mm.h>
+ + #include <linux/sched.h>
+ + #include <linux/completion.h>
+ + #include <linux/file.h>
+ + #include <linux/pagemap.h>
+ + #include <linux/cpu.h>
+ + #include <linux/init_task.h>
+ + #include <linux/kthread.h>
+ + #include <linux/delay.h>
+ + 
+ + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) 
+ + #include <linux/locks.h>
+ + #endif 
+ + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) 
+ + #include <linux/devfs_fs_kernel.h>
+ + #endif 
+ + #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,20)
+ + #include <linux/freezer.h>
+ + #endif
+ + 
+ + /* ---- global data */
+ + 
+ + /* wait queue */
+ + DECLARE_WAIT_QUEUE_HEAD(kctexdbgd_wait);
+ + DECLARE_WAIT_QUEUE_HEAD(kctexdbgd_process_wait);
+ + DECLARE_WAIT_QUEUE_HEAD(kctexdbgd_force_wait);
+ + DECLARE_WAIT_QUEUE_HEAD(kctexdbgd_signal_wait);
+ + DECLARE_WAIT_QUEUE_HEAD(kctexdbgd_exit_wait);
+ + 
+ + /* lock */
+ + spinlock_t ctexdbg_kernel_spinlock;				/* kernel spinlock */
+ + spinlock_t ctexdbg_continue_spinlock;
+ + 
+ + /* sMP */
+ + uint32_t ctexdbg_daemon_cpuid = 0;				/* daemon cpuid */
+ + uint32_t ctexdbg_nrcpus;						/* max cpus */
+ + 
+ + 
+ + /* ctexdbg_contdata ctexdbg_data; */	 		/* kctexdbgd control data */
+ + ctexdbg_fix ctexdbg_fixdata; 			/* kctexdbgd init fix data */
+ + 
+ + /* pid changing data */
+ + uint32_t ctexdbg_prevpid;
+ + uint32_t ctexdbg_nextpid;
+ + 
+ + /*
+ +    com buffer formats: 
+ +    byte: 
+ +     0       : wakeup flag (0:sleep   nonZero: wakeup
+ + 	1       : function ID  (see CTEXDBG_ICEFunction)
+ + 	2       : reserved (now unuse)
+ + 	3       : end of data flag (0 is end ; 1 is continue)
+ + 	4-511  : data...
+ + */
+ + unsigned char ctexdbg_combuf[512];		/* communication buffer */
+ + unsigned char ctexdbg_workbuf[CTEXDBG_WORKBUF_SIZE+1];			/* working buffer */
+ + unsigned char ctexdbg_filebuf[CTEXDBG_WORKBUF_SIZE+1];			/* file op working buffer (1kb) */
+ + 
+ + unsigned char *ctexdbg_evdata;				/* event data */
+ + 
+ + /* ICE ack flag */
+ + unsigned char ctexdbg_ack = 0;					/* event ack */
+ + unsigned char ctexdbg_lop = 0;					/* event in loop */
+ + 
+ + unsigned long ctexdbg_wakeuppid;
+ + 
+ + unsigned long ctexdbg_debugpidmax = 0;		/* Number of debug process */
+ + int ctexdbg_traceuse = 0;					/* TRACE enable */
+ + 
+ + ctexdbg_checkarea ctexdbg_areatable[CTEXDBG_PGOFF_MAX];	/* area check table*/
+ + uint32_t ctexdbg_breaksig[_NSIG+1];						/* handle catch signal */
+ + //uint32_t ctexdbg_debugpid[CTEXDBG_PIDSIZE_MAX];			/* debug pid table */
+ + ctexdbg_debugproc ctexdbg_debugpid[CTEXDBG_PIDSIZE_MAX];
+ + uint32_t ctexdbg_forcebreaksig_pid;
+ + uint32_t ctexdbg_tempcur;
+ + uint32_t ctexdbg_enabled;			/* enable disable ctexdbg */
+ + uint32_t ctexdbg_allbreak;			/* enable disable all breakmode */
+ + uint32_t ctexdbg_pexitnochk;		/* enable disable outsize debug process exit check */
+ + 											/* 0: disable (check all exec/exit process) */
+ + 											/* 1: enable  (check debug only fork/exec/exit process) */
+ + 
+ + uint32_t ctexdbg_noclone_debug;	/* enable disable catch clone(pthread/thread)debug */									
+ + 											/* 0: enable (clone() catch)*/
+ + 											/* 1: disable (clone() not catch)*/
+ + 									
+ + uint32_t ctexdbg_noattach_debug;	/* enable disable attach process debug */									
+ + 											/* 0: enable (all attach:default) */
+ + 											/* 1: disable (do not attach) */
+ + 									
+ + uint32_t ctexdbg_premain_debug;	/* enable disable before main() debug */									
+ + 											/* 0: disable (dont stop:default) */
+ + 											/* 1: enable (stop) */
+ + 
+ + 																		
+ + uint32_t ctexdbg_mapcount=0;		/* mapping counter */									
+ + 
+ + uint32_t ctexdbg_xipinram;		/* CRAMFS Xip apps RAM mode */
+ + 
+ + uint32_t ctexdbg_hardware_trace_enabled;	/* [v9]setting for hardware trace by ice */
+ + 
+ + char*  ctexdbg_envpdata[10];		/* special envp */
+ + char   ctexdbg_envpstr[100];
+ + char   ctexdbg_preloadlib[100];
+ + 
+ + char   ctexdbg_dbgfile[CTEXDBG_DBG_FNAMESIZE];	/* debug file list */
+ + 
+ + ctexdbg_mmap	ctexdbg_mmapdata[CTEXDBG_MMAPDATA_SIZE];	/* VP map data */
+ + 
+ + ctexdbg_modsyms ctexdbg_moddata[CTEXDBG_MODULE_MAX];	/* module table */
+ + 
+ + /* LTT */
+ + cdbtrc_bufpos	ctexdbg_tracebufpos;				/* buffer position */
+ + 
+ + /* Debug symbol */
+ + uint32_t ctexdbg_ddebugevent = 0;
+ + uint32_t ctexdbg_ddebugrecv = 0;
+ + uint32_t ctexdbgd_wake = 0;
+ + 
+ + #ifdef CONFIG_CTEX_DBGLIB_ANDROID
+ + char ctexdbg_android = 0;				/* android flag */
+ + #endif
+ + 
+ + /* Version info and check */
+ + char ctexdbg_patchver_char[8];
+ + 
+ + /* proto-type */
+ + void ctexdbg_signalbreak(uint32_t pid,uint32_t sig);
+ + 
+ + extern int ctexdbg_file_ls(char *path);
+ + extern int ctexdbg_file_rmdir(char *path);
+ + extern int ctexdbg_file_mkdir(char *path);
+ + extern int ctexdbg_file_delfile(char *path);
+ + extern int ctexdbg_file_read(char *path);
+ + extern int ctexdbg_file_write(char *path);
+ + extern int ctexdbg_file_rename(char *path);
+ + extern int ctexdbg_file_chmod(char *path);
+ + extern int ctexdbg_file_chown(char *path);
+ + 
+ + /* event handler */
+ + void ctexdbg_event(struct task_struct *tasks,uint32_t eventno)
+ + {
+ + 	barrier();		/* compiler optmize barrier */
+ + 	if(ctexdbg_enabled == 0) return;
+ + 	/*
+ + 	 * set process info
+ + 	 * [eventno] [context] [PID] [...]
+ + 	 */
+ + 	ctexdbg_tempcur = (uint32_t)tasks;
+ + 	memcpy(ctexdbg_workbuf,&eventno,sizeof(uint32_t));
+ + 	memcpy(ctexdbg_workbuf + 4,&ctexdbg_tempcur,sizeof(uint32_t));
+ + 	memcpy(ctexdbg_workbuf + 8,&(tasks->pid),sizeof(uint32_t));
+ + 	ctexdbg_prn("ctexdbg","event# %08x context %08x PID %08x cpuid %08x\n",
+ + 			(uint32_t)(*ctexdbg_workbuf),
+ + 			(uint32_t)(*(ctexdbg_workbuf+4)),
+ + 			(uint32_t)(*(ctexdbg_workbuf+8)),
+ + 			(uint32_t)(smp_processor_id())
+ + 	);
+ + 	/* send ice and loop ack */
+ + 	while(ctexdbg_ack == 0){
+ + 		ctexdbg_lop = 1;
+ + 		ctexdbg_event_core();
+ + 	}
+ + 	ctexdbg_ack = 0;
+ + 	ctexdbg_lop = 0;
+ + }
+ + 
+ + /* --------------- event bp ---------------------------------------------------- */
+ + 
+ + /* LTTbuffer full event */
+ + void ctexdbg_lttfull_bp(void)
+ + {
+ + 	unsigned long clk_irq;
+ + 	clk_irq = ctexdbg_arch_lock_kernel();
+ + 	ctexdbg_event(current,CTEXDBG_EV_LTTFULL);
+ + 	ctexdbg_arch_unlock_kernel(clk_irq);
+ + 	return;
+ + }
+ + 
+ + 
+ + /* Eventbuffer full event */
+ + void ctexdbg_eventfull_bp(void)
+ + {
+ + 	unsigned long clk_irq;
+ + 	clk_irq = ctexdbg_arch_lock_kernel();
+ + 	ctexdbg_event(current,CTEXDBG_EV_EVENTFULL);
+ + 	ctexdbg_arch_unlock_kernel(clk_irq);	
+ + 	return;
+ + }
+ + 
+ + /* File LS buffer full event */
+ + void ctexdbg_filelsfull_bp(void)
+ + {
+ + 	unsigned long clk_irq;
+ + 	clk_irq = ctexdbg_arch_lock_kernel();
+ + 	memcpy(ctexdbg_workbuf,ctexdbg_filebuf,CTEXDBG_WORKBUF_SIZE);	
+ + 	ctexdbg_event(current,CTEXDBG_EV_FILE_LSFULL);
+ + 	ctexdbg_arch_unlock_kernel(clk_irq);
+ + 	return;
+ + }
+ + 
+ + /* File read transfer event */
+ + unsigned long ctexdbg_fileread_bp(void)
+ + {
+ + 	unsigned long clk_irq;
+ + 	unsigned long stopflag;
+ + 	clk_irq = ctexdbg_arch_lock_kernel();
+ + 	memcpy(ctexdbg_workbuf,ctexdbg_filebuf,CTEXDBG_WORKBUF_SIZE);
+ + 	ctexdbg_event(current,CTEXDBG_EV_FILE_READ);
+ + 	memcpy(&stopflag,ctexdbg_workbuf,sizeof(unsigned long));
+ + 	ctexdbg_arch_unlock_kernel(clk_irq);	
+ + 	return stopflag;
+ + }
+ + 
+ + /* File write transfer event */
+ + unsigned long ctexdbg_filewrite_bp(void)
+ + {
+ + 	unsigned long clk_irq;
+ + 	unsigned long stopflag;	
+ + 	clk_irq = ctexdbg_arch_lock_kernel();
+ + 	memcpy(ctexdbg_workbuf,ctexdbg_filebuf,CTEXDBG_WORKBUF_SIZE);
+ + 	ctexdbg_event(current,CTEXDBG_EV_FILE_WRITE);
+ + 	memcpy(&stopflag,ctexdbg_workbuf,sizeof(unsigned long));	
+ + 	memcpy(ctexdbg_filebuf,ctexdbg_workbuf,CTEXDBG_WORKBUF_SIZE);	
+ + 	ctexdbg_arch_unlock_kernel(clk_irq);
+ + 	return stopflag;
+ + }
+ + 
+ + /* File op end event */
+ + void ctexdbg_fileend_bp(void)
+ + {
+ + 	unsigned long clk_irq;
+ + 	clk_irq = ctexdbg_arch_lock_kernel();
+ + 	memcpy(ctexdbg_workbuf,ctexdbg_filebuf,CTEXDBG_WORKBUF_SIZE);
+ + 	ctexdbg_event(current,CTEXDBG_EV_FILE_END);
+ + 	ctexdbg_arch_unlock_kernel(clk_irq);
+ + 	return;
+ + }
+ + 
+ + 
+ + /* --------------- misc ---------------------------------------------------- */
+ + 
+ + /* Find any file in finder. ret=0 not found fname ret=1 found fname */
+ + int ctexdbg_find_file(char *fname,char* finder,int findersize)
+ + {
+ + 	int i = 0;
+ + 	int ldot = 0;
+ + 	int flen = 0;
+ + 	int slen = 0;
+ + 	
+ + 	char findname[NAME_MAX];
+ + 	
+ + 	if(fname == NULL) return 0;
+ + 	strncpy(findname,fname,NAME_MAX);
+ + 	slen = strlen(findname);
+ + 	
+ + 	/* find last dot */
+ + 	for(ldot=slen-1;ldot >= 0;ldot--){
+ + 		if(findname[ldot] == '.'){
+ + 			findname[ldot] = '\0';
+ + 			break;
+ + 		}
+ + 	}
+ + 	slen = strlen(findname);
+ + 	
+ + 	/* fix :null is set default */
+ + 	if(finder == NULL){
+ + 		finder = (char *)ctexdbg_dbgfile;
+ + 		findersize = CTEXDBG_DBG_FNAMESIZE;
+ + 	}
+ + 	
+ + 	while(i < findersize){
+ + 		if(finder[i] == '\0'){
+ + 			break;
+ + 		}
+ + 		flen = strlen(&(finder[i]));
+ + 		/* fix: filename equal finder strict compare */
+ + 		if(slen == flen){
+ + 			if(strnicmp(&(finder[i]),findname,slen) == 0){
+ + 				return 1;
+ + 			}
+ + 		}
+ + 		i += (flen+1);
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /* Find any file in finder(from CRAMFS-XIP code). ret=0 not found or not ram mode fname ret=1 found fname */
+ + int ctexdbg_find_file_xip(char *fname,char* finder,int findersize)
+ + {
+ + 	if(ctexdbg_xipinram == 1) return 0;
+ + 	return ctexdbg_find_file(fname,finder,findersize);
+ + }
+ + 
+ + /* isvarid d_name.name */
+ + int ctexdbg_varid_dname(struct mm_struct *mm)
+ + {
+ + 	if(mm == NULL) return 1;
+ + 	if(mm->mmap == NULL) return 1;
+ + 	if(mm->mmap->vm_file == NULL) return 1;
+ + 	if(mm->mmap->vm_file->f_dentry == NULL) return 1;
+ + 	return 0;
+ + }
+ + 
+ + int ctexdbg_varid_vma(struct vm_area_struct * vma)
+ + {
+ + 	if(vma == NULL) return 1;
+ + 	if(vma->vm_file == NULL) return 1;
+ + 	if(vma->vm_file->f_dentry == NULL) return 1;
+ + 	return 0;
+ + }
+ + 
+ + /* Add debug process ID */
+ + void ctexdbg_add_debugpid(uint32_t pid)
+ + {
+ + 	int i;
+ + 	for(i=0; i < CTEXDBG_PIDSIZE_MAX ;i++){
+ + 		if(ctexdbg_debugpid[i].pid == 0){
+ + 			ctexdbg_debugpid[i].pid = pid;
+ + 			ctexdbg_debugpid[i].migration = 0;
+ + 			break;
+ + 		}
+ + 	}
+ + }
+ + 
+ + /* Remove debug process ID */
+ + void ctexdbg_remove_debugpid(uint32_t pid)
+ + {
+ + 	int i;
+ + 	for(i=0; i < CTEXDBG_PIDSIZE_MAX ;i++){
+ + 		if(ctexdbg_debugpid[i].pid == pid){
+ + 			ctexdbg_debugpid[i].pid = 0;
+ + 			ctexdbg_debugpid[i].migration = 0;
+ + 			break;
+ + 		}
+ + 	}
+ + }
+ + 
+ + /* Find debug process ID */
+ + ctexdbg_debugproc* ctexdbg_find_debugpid(uint32_t pid)
+ + {
+ + 	int i;
+ + 	for(i=0; i < CTEXDBG_PIDSIZE_MAX ;i++){
+ + 		if(ctexdbg_debugpid[i].pid == pid){
+ + 			return &(ctexdbg_debugpid[i]);
+ + 		}
+ + 	}
+ + 	return NULL;
+ + }
+ + 
+ + /* Debug dump console */
+ + void do_ctexdump(void)
+ + {
+ + 	int i;
+ + 	char *cb = ctexdbg_combuf;
+ + 	
+ + 	ctexdbg_prn("kctexdbg","Dump communitation buffer\n");
+ + 	for(i=0;i<127;i+=16){
+ + 		ctexdbg_prn("kctexdbg","%05X : %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
+ + 				i,
+ + 				cb[i],cb[i+1],cb[i+2],cb[i+3],cb[i+4],cb[i+5],cb[i+6],cb[i+7],cb[i+8],
+ + 				cb[i+9],cb[i+10],cb[i+11],cb[i+12],cb[i+13],cb[i+14],cb[i+15]
+ + 		);
+ + 	}
+ + 	ctexdbg_prn("kctexdbg","Dump end\n");
+ + 	
+ + }
+ + 
+ + /* sending signal */
+ + void do_ctex_sendsig(unsigned long pid,unsigned long sigid)
+ + {
+ + 	struct task_struct *t;
+ + #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,26)
+ + //	t = find_task_by_pid_type_ns(PIDTYPE_PID, pid, &init_pid_ns);
+ + 	t = find_task_by_pid_ns(pid, &init_pid_ns);
+ + #else
+ + 	t = find_task_by_pid(pid);
+ + #endif	
+ + 	if(t != NULL){
+ + 		force_sig(sigid,t);
+ + 	}
+ + }
+ + 
+ + /* ----------------- kctexdbg sMP function ----------------------------------------- */
+ + /* limit runnable cpuS forked process */
+ + void ctexdbg_fork_limit_cpu_mask(struct task_struct *tsk)
+ + {
+ + 	cpumask_t c_mask;
+ + 	cpus_clear(c_mask);
+ + 	cpu_set(ctexdbg_daemon_cpuid,c_mask);
+ + 	tsk->cpus_allowed = c_mask;
+ + 	set_task_cpu(tsk, ctexdbg_daemon_cpuid);
+ + }
+ + 
+ + /* limit runnable cpuS execed process */
+ + void ctexdbg_exec_limit_cpu_mask(struct task_struct *tsk)
+ + {
+ + 	cpumask_t c_mask;
+ + 	cpus_clear(c_mask);
+ + 	cpu_set(ctexdbg_daemon_cpuid,c_mask);
+ + 	set_cpus_allowed(tsk,c_mask);
+ + }
+ + 
+ + /* unlimit runnable cpuS execed process */
+ + void ctexdbg_exec_setall_cpu_mask(struct task_struct *tsk)
+ + {
+ + 	cpumask_t c_mask;
+ + 	cpus_clear(c_mask);
+ + 	cpus_setall(c_mask);
+ + 	set_cpus_allowed(tsk,c_mask);
+ + }
+ + 
+ + void ctexdbg_up_migration(ctexdbg_debugproc *findtask)
+ + {
+ + 	findtask->migration = 0;
+ + }
+ + 
+ + /* migration check */
+ + void ctexdbg_migration_check(struct task_struct *tsk ,int src_cpu,int dest_cpu)
+ + {
+ + 	char *p;
+ + 	unsigned long clk_irq;
+ + 	ctexdbg_debugproc *findtask;
+ + 
+ + 	if(ctexdbg_enabled == 0) return;
+ + 
+ + 	barrier();		/* compiler optmize barrier */
+ + 	clk_irq = ctexdbg_arch_lock_kernel();
+ + 
+ + 	findtask = ctexdbg_find_debugpid(tsk->pid);
+ + 	if (findtask == NULL) goto migration_check_exit;
+ + 	if (findtask->migration == 0) goto migration_check_exit;
+ + 
+ + 	/* fmt:[tskaddr] [pid] [src_cpu] [dest_cpu] */
+ + 	p = ctexdbg_evdata;
+ + 	ctexdbg_tempcur = (uint32_t)tsk;
+ + 	memcpy(p ,&ctexdbg_tempcur,sizeof(uint32_t));
+ + 	p += sizeof(uint32_t);
+ + 	memcpy(p,&tsk->pid,sizeof(uint32_t));
+ + 	p += sizeof(uint32_t);
+ + 	memcpy(p,&(src_cpu),sizeof(uint32_t));
+ + 	p += sizeof(uint32_t);
+ + 	memcpy(p,&(dest_cpu),sizeof(uint32_t));
+ + 
+ + 	ctexdbg_event(current,CTEXDBG_EV_MIGRATION);
+ + 
+ + 	ctexdbg_up_migration(findtask);
+ + 
+ + migration_check_exit:
+ + 	ctexdbg_arch_unlock_kernel(clk_irq);	
+ + 	return;
+ + }
+ + 
+ + /* ----------------------------------------------------------------------------- */
+ + /* adding PV mapping from arch */
+ + void ctexdbg_add_memmap(unsigned long virt,unsigned long phys,unsigned long length)
+ + {
+ + 	ctexdbg_prn("ctexdbg","mapping v=0x%08lx p=0x%08lx len=0x%08lx\n",virt,phys,length);
+ + 
+ + 	if(CTEXDBG_MMAPDATA_SIZE <= (ctexdbg_mapcount + 1)) return;
+ + 	
+ + 	ctexdbg_mmapdata[ctexdbg_mapcount].virtaddr = virt;
+ + 	ctexdbg_mmapdata[ctexdbg_mapcount].physaddr = phys;
+ + 	ctexdbg_mmapdata[ctexdbg_mapcount].length = length;
+ + 
+ + 	ctexdbg_mmapdata[ctexdbg_mapcount+1].virtaddr = 0;
+ + 	ctexdbg_mmapdata[ctexdbg_mapcount+1].physaddr = 0;
+ + 	ctexdbg_mmapdata[ctexdbg_mapcount+1].length = 0;
+ + 	ctexdbg_mapcount ++;
+ + }
+ + 
+ + 
+ + /* --------------- event ---------------------------------------------------- */
+ + 
+ + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) 
+ + /* Find a module section: 0 means not found. */
+ + static unsigned int ctexdbg_find_elf_section(Elf_Ehdr *hdr,Elf_Shdr *sechdrs,const char *secstrings,const char *name)
+ + {
+ + 	unsigned int i;
+ + 	if(secstrings == NULL) return 0;
+ + 	for (i = 1; i < hdr->e_shnum; i++){
+ + 		if(sechdrs[i].sh_name == 0) continue;
+ + 		if(strcmp(secstrings+sechdrs[i].sh_name, name) == 0) return i;
+ + 	}
+ + 	return 0;
+ + }
+ + static uint32_t ctexdbg_get_elf_addr(Elf_Ehdr *hdr,Elf_Shdr *sechdrs,const char *secstrings,const char *name)
+ + {
+ + 	unsigned int i;
+ + 	i = ctexdbg_find_elf_section(hdr,sechdrs,secstrings,name);
+ + 	if(i == 0) return 0;
+ + 	return sechdrs[i].sh_addr;
+ + }
+ + 
+ + #endif
+ + 
+ + /* module init helper (2.6 later) */
+ + int ctexdbg_module_install(struct module *mod,void *ehdrs,void *sechdrs,const char* secstrings,uint32_t symindex,uint32_t strindex)
+ + {
+ + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) 
+ + 	int i,n;
+ +  	Elf_Shdr *elf_sechdrs = (Elf_Shdr *)sechdrs;
+ + 	Elf_Ehdr *elf_edrs = (Elf_Ehdr *)ehdrs;
+ + 
+ + 	if(ctexdbg_ddebugevent == 1){
+ + 		for (n = 1; n < elf_edrs->e_shnum; n++){
+ + 			ctexdbg_prn("ctexdbg","elf info %d\n",n);
+ + 			if(elf_sechdrs[n].sh_name != 0){
+ + 				ctexdbg_prn("ctexdbg","name %-15s \n",secstrings+elf_sechdrs[n].sh_name);
+ + 			}
+ + 			ctexdbg_prn("ctexdbg","sadr %08X \n",elf_sechdrs[n].sh_addr);
+ + 			ctexdbg_prn("ctexdbg","offs %08X \n",elf_sechdrs[n].sh_offset);
+ + 			ctexdbg_prn("ctexdbg","type %08X \n",elf_sechdrs[n].sh_type);
+ + 			ctexdbg_prn("ctexdbg","flag %08X \n",elf_sechdrs[n].sh_flags);
+ + 		}
+ + 	}
+ + 
+ + 	if(ctexdbg_enabled == 0) return 0;
+ + 
+ + 	for(i=0;i<CTEXDBG_MODULE_MAX;i++){
+ + 		if(ctexdbg_moddata[i].mod == NULL) break;
+ + 	}
+ + 	if(i>=CTEXDBG_MODULE_MAX) i=0;
+ + 	ctexdbg_moddata[i].mod = mod;
+ + 	ctexdbg_moddata[i].start_addr = ctexdbg_get_elf_addr(elf_edrs,elf_sechdrs,secstrings,".text");
+ + 	ctexdbg_moddata[i].rodata_addr = ctexdbg_get_elf_addr(elf_edrs,elf_sechdrs,secstrings,".rodata");
+ + 	ctexdbg_moddata[i].data_addr = ctexdbg_get_elf_addr(elf_edrs,elf_sechdrs,secstrings,".data");
+ + 	ctexdbg_moddata[i].bss_addr = ctexdbg_get_elf_addr(elf_edrs,elf_sechdrs,secstrings,".bss");
+ + 
+ + 	ctexdbg_moddata[i].symtab_addr = elf_sechdrs[symindex].sh_addr;
+ + 	ctexdbg_moddata[i].numsym = elf_sechdrs[symindex].sh_size / sizeof(Elf_Sym);
+ + 	ctexdbg_moddata[i].strtab_addr = elf_sechdrs[strindex].sh_addr;	
+ + 
+ + #endif /* Lver */
+ + 	return 0;
+ + }
+ + 
+ + int ctexdbg_module_remove(struct module *mod)
+ + {
+ + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+ + 	int i;
+ + 	for(i=0;i<CTEXDBG_MODULE_MAX;i++){
+ + 		if(ctexdbg_moddata[i].mod == mod){
+ + 			ctexdbg_moddata[i].mod = NULL;
+ + 			break;
+ + 		}
+ + 	}
+ + #endif /* Lver */
+ + 	return 0;
+ + }
+ + 
+ + 
+ + /* module init event (sys_init_module()) */
+ + int ctexdbg_module_init(struct module *mod)
+ + {
+ + 	char *p;
+ + 	uint32_t nlen;
+ + 	uint32_t offset;
+ + 	int i;
+ + 	unsigned long clk_irq;
+ + 	
+ + 	if(ctexdbg_enabled == 0)
+ + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26) 		
+ + 		return 0;
+ + #else
+ + 		return mod->init();
+ + #endif
+ + 		
+ + 	if(mod->name == NULL)
+ + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26) 		
+ + 		return 0;
+ + #else
+ + 		return mod->init();
+ + #endif
+ + 	
+ + 	clk_irq = ctexdbg_arch_lock_kernel();	
+ + 	
+ + 	nlen = strlen(mod->name);
+ + 	
+ + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) 
+ + 	offset = (unsigned long)mod->module_init;
+ + #else
+ + 	offset = (unsigned long)mod + mod->size_of_struct;
+ + #endif /* Lver */
+ + 
+ + 	/* check debug filelist */
+ + 	if(ctexdbg_find_file((char*)mod->name,NULL,0) != 1){
+ + 		ctexdbg_arch_unlock_kernel(clk_irq);	
+ + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26) 		
+ + 		return 0;
+ + #else
+ + 		return mod->init();
+ + #endif
+ + 	}
+ + 	for(i=0;i<CTEXDBG_MODULE_MAX;i++){
+ + 		if(ctexdbg_moddata[i].mod == mod)	break;
+ + 	}
+ + 	if(i>=CTEXDBG_MODULE_MAX)	i=0;
+ + 
+ + 	/* fmt: [offset] [initaddr] [name length] [name...] [startaddr] [symtab] [nsyms] [strtab] */
+ + 	p = ctexdbg_evdata;
+ + 	memcpy(p,&(offset),sizeof(uint32_t));
+ + 	p += sizeof(uint32_t);
+ + 	memcpy(p,&(mod->init),sizeof(uint32_t));
+ + 	p += sizeof(uint32_t);
+ + 
+ + 	/* ver009 send type*/		
+ + 	memcpy(p,&(ctexdbg_moddata[i].start_addr),sizeof(uint32_t));
+ + 	p += sizeof(uint32_t);
+ + 	memcpy(p,&(ctexdbg_moddata[i].symtab_addr),sizeof(uint32_t));
+ + 	p += sizeof(uint32_t);
+ + 	memcpy(p,&(ctexdbg_moddata[i].numsym),sizeof(uint32_t));
+ + 	p += sizeof(uint32_t);
+ + 	memcpy(p,&(ctexdbg_moddata[i].strtab_addr),sizeof(uint32_t));
+ + 	p += sizeof(uint32_t);
+ + 	memcpy(p,&(ctexdbg_moddata[i].rodata_addr),sizeof(uint32_t));
+ + 	p += sizeof(uint32_t);
+ + 	memcpy(p,&(ctexdbg_moddata[i].data_addr),sizeof(uint32_t));
+ + 	p += sizeof(uint32_t);
+ + 	memcpy(p,&(ctexdbg_moddata[i].bss_addr),sizeof(uint32_t));
+ + 	p += sizeof(uint32_t);
+ + 			
+ + 	memcpy(p,&(nlen),sizeof(uint32_t));
+ + 	p += sizeof(uint32_t);
+ + 	strcpy(p,mod->name);
+ + 	
+ + 	ctexdbg_event(current,CTEXDBG_EV_MODULE_INIT);
+ + 	
+ + 	ctexdbg_arch_unlock_kernel(clk_irq);	
+ + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26) 		
+ + 	return 0;
+ + #else
+ + 	return mod->init();
+ + #endif
+ + }
+ + 
+ + /* signal event and force break operation */
+ + int ctexdbg_signals(uint32_t signa,uint32_t pid,struct pt_regs *regs)
+ + {
+ + 	unsigned long clk_irq;
+ + 	/* check a signal */
+ + 	if(_NSIG < signa)	return 0;		/* unknown signal */
+ + 		
+ + 	if( (ctexdbg_forcebreaksig_pid == pid) &&
+ + 		(signa == SIGSTOP) ){
+ + 		
+ + 		if(ctexdbg_ddebugevent == 1)	ctexdbg_print_context_reg(regs);
+ + 		/* Force break hook */
+ + 		clk_irq = ctexdbg_arch_lock_kernel();
+ + 		ctexdbg_event(current,CTEXDBG_EV_PBREAK_FBREAK);
+ + 		ctexdbg_arch_unlock_kernel(clk_irq);
+ + 		if(ctexdbg_allbreak != 0){
+ + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+ + 			spin_unlock_irq(&current->sighand->siglock);
+ + #endif
+ + 			return 1;
+ + 		}
+ + 	}else if(ctexdbg_breaksig[signa] == 1){
+ + 		if(ctexdbg_ddebugevent == 1)	ctexdbg_print_context_reg(regs);
+ + 		ctexdbg_signalbreak(pid,signa);
+ + 	}
+ + 	
+ + 	return 0;
+ + }
+ + 
+ + /* signal break handler */
+ + void ctexdbg_signalbreak(uint32_t pid,uint32_t sig)
+ + {
+ + 	char *p;
+ + 	unsigned long clk_irq;
+ + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+ + 	/* irq_lock must be canceled before locking kern */
+ + 	spin_unlock_irq(&current->sighand->siglock);
+ + #endif
+ + 	clk_irq = ctexdbg_arch_lock_kernel();
+ + 	
+ + 	p = ctexdbg_evdata;
+ + 	memcpy(p,&pid,sizeof(uint32_t));
+ + 	p += sizeof(uint32_t);
+ + 	memcpy(p,&sig,sizeof(uint32_t));
+ + 	
+ + 	ctexdbg_event(current,CTEXDBG_EV_SIGNAL);
+ + 	
+ + 	if(ctexdbg_allbreak != 0)	goto signalbreak_exit;
+ + 	if(ctexdbg_workbuf[0] != 1)		goto signalbreak_exit;
+ + 	
+ + 	ctexdbg_arch_unlock_kernel(clk_irq);
+ + 	
+ + 	/* waiting. for ctexdbg event */
+ + 	wait_event(kctexdbgd_signal_wait,ctexdbg_wakeuppid == current->pid);
+ + 	/* wake up */
+ + 	clk_irq = ctexdbg_arch_lock_kernel();
+ + 	spin_lock(&ctexdbg_continue_spinlock);	
+ + 	ctexdbg_wakeuppid = 0;
+ + 	ctexdbg_event(current,CTEXDBG_EV_SIGNAL_WAKEUP);
+ + 	spin_unlock(&ctexdbg_continue_spinlock);	
+ + 	
+ + signalbreak_exit:	
+ + 	ctexdbg_arch_unlock_kernel(clk_irq);	
+ + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+ + 	spin_lock_irq(&current->sighand->siglock);
+ + #endif
+ + }
+ + 
+ + /* process break handler */
+ + #ifdef CONFIG_ARM
+ + void ctexdbg_pbreak(void)
+ + #else
+ + void ctexdbg_pbreak_cmn(void)
+ + #endif /* CONFIG_ARM */
+ + {
+ + 	/* waiting. for ctexdbg event */
+ + 	wait_event(kctexdbgd_process_wait,ctexdbg_wakeuppid == current->pid);
+ + 	spin_lock(&ctexdbg_continue_spinlock);
+ + 	ctexdbg_wakeuppid = 0;
+ + 	spin_unlock(&ctexdbg_continue_spinlock);
+ + 	ctexdbg_exec_setall_cpu_mask(current);
+ + 	ctexdbg_event(current,CTEXDBG_EV_PBREAK_WAKEUP);
+ + 	/* Do not return */
+ + }
+ + 
+ + 
+ + /* process FORCE break handler */
+ + int ctexdbg_forcebreak(struct task_struct *tsk)
+ + {
+ + 	unsigned long clk_irq;
+ + 	
+ + 	/* isnot CTEX forcebreak... */
+ + 	if(ctexdbg_forcebreaksig_pid != tsk->pid)	return 0;
+ + 	
+ + 	ctexdbg_forcebreaksig_pid = 0;
+ + 	
+ + 	/* irq_lock must be canceled before locking kern */
+ + 	spin_unlock_irq(&current->sighand->siglock);
+ + 	
+ + 	/* waiting. for ctexdbg event */
+ + 	wait_event(kctexdbgd_force_wait,ctexdbg_wakeuppid == current->pid);
+ + 	/* I can wake up ? */
+ + 	clk_irq = ctexdbg_arch_lock_kernel();
+ + 	spin_lock(&ctexdbg_continue_spinlock);
+ + 	ctexdbg_wakeuppid = 0;
+ + 	
+ + 	ctexdbg_event(current,CTEXDBG_EV_PBREAK_FBREAK_WAKEUP);
+ + 	
+ + 	spin_unlock(&ctexdbg_continue_spinlock);	
+ + 	ctexdbg_arch_unlock_kernel(clk_irq);
+ + 	return 1;
+ + }
+ + 
+ + 
+ + /*
+ +  * check page from vm_arae
+ +  */
+ + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) 
+ + int ctexdbg_do_check_page(struct vm_area_struct * vma,unsigned long address)
+ + {
+ + 	unsigned long check_addr_offset;
+ + 	int i;
+ + 	int check_present = 0;
+ + 	struct address_space * checkaddr_space;
+ + 	struct page * check_page;
+ + 
+ + 	if(vma == NULL) return -1;
+ + 	if(vma->vm_file == NULL) return -1;
+ + 	if(vma->vm_file->f_mapping == NULL) return -1;
+ + 	checkaddr_space = vma->vm_file->f_mapping;
+ + 	
+ + 	for(i = 0;i < CTEXDBG_PGOFF_MAX;i++){
+ + 		if(ctexdbg_areatable[i].pid == 0){
+ + 			/* end of table */
+ + 			return -1;
+ + 		}
+ + 		ctexdbg_prn("ctexdbg","do_no_page pid %d tgid %d vma_s=0x%08lx vma_e=0x%08lx addr=0x%08lx\n",
+ + 						current->pid,current->tgid,vma->vm_start,vma->vm_end,address);
+ + 		if((current->pid == ctexdbg_areatable[i].pid) ||
+ + 		   (current->tgid == ctexdbg_areatable[i].pid)
+ + 		){
+ + 			if(unlikely(address == ctexdbg_areatable[i].address)){
+ + 				/* hit */
+ + 				return i;
+ + 			}else
+ + 			if((vma->vm_start <= ctexdbg_areatable[i].address) &&
+ + 				(vma->vm_end >= ctexdbg_areatable[i].address)
+ + 			){
+ + 				check_addr_offset = 
+ + 					((ctexdbg_areatable[i].address - vma->vm_start) >> PAGE_SHIFT) + vma->vm_pgoff;
+ + 				
+ + 				check_page = find_get_page(checkaddr_space, check_addr_offset);				
+ + 				if(unlikely(check_page == NULL)){
+ + 					/* page not found */
+ + 					continue;
+ + 				}
+ + 				check_present = PageUptodate(check_page);
+ + 				page_cache_release(check_page);
+ + 				if(check_present != 0){
+ + 					/* hit. this activate page address */
+ + 					return i;
+ + 				}
+ + 			}
+ + 		}
+ + 	}		
+ + 	return -1;
+ + }
+ + #else
+ + int ctexdbg_do_check_page(struct vm_area_struct * vma,unsigned long address)
+ + {
+ + 	int i,same=0;
+ + 
+ + 	if(vma == NULL) return -1;
+ + 
+ + 	for(i = 0;i < CTEXDBG_PGOFF_MAX;i++){
+ + 		if(ctexdbg_areatable[i].pid == 0){
+ + 			/* end of table */
+ + 			return -1;
+ + 		}
+ + 
+ + 		ctexdbg_prn("ctexdbg","do_no_page pid %d vma_s=0x%08lx vma_e=0x%08lx\n",
+ + 						current->pid,vma->vm_start,vma->vm_end);
+ + 		if(current->mm != NULL){
+ + 			ctexdbg_prn("ctexdbg","mm = 0x%08x pgd=0x%08x pgdp=0x%08x\n",
+ + 						(uint32_t)current->mm,(uint32_t)current->mm->pgd);
+ + 		}
+ + 
+ + 		if((current->pid == ctexdbg_areatable[i].pid) &&
+ + 			(vma->vm_start <= ctexdbg_areatable[i].address) &&
+ + 			(vma->vm_end >= ctexdbg_areatable[i].address)
+ + 		){
+ + 			same = 1;
+ + 		}
+ + 
+ + 		/* 2.4 FIX use pgd */
+ + 		if(current->mm != NULL){
+ + 			if( ((uint32_t)current->mm->pgd == ctexdbg_areatable[i].pgd) &&
+ + 				(vma->vm_start <= ctexdbg_areatable[i].address) &&
+ + 				(vma->vm_end >= ctexdbg_areatable[i].address)
+ + 			){
+ + 				same = 1;
+ + 			}
+ + 		}
+ + 
+ + 		if(same == 1){
+ + 			return i;
+ + 		}
+ + 	}
+ + 	return -1;
+ + }
+ + #endif	/* 2.6 */
+ + 
+ + /*
+ +  * do_no_page()  page non -> load end handler.
+ +  */
+ + void ctexdbg_do_no_page(struct vm_area_struct * vma,unsigned long address)
+ + {
+ + 	uint32_t i;
+ + 	char *p;
+ + 	int checkret;
+ + 	unsigned long clk_irq;
+ + 	
+ + 	if(ctexdbg_enabled == 0) return;
+ + 	
+ + 	checkret = ctexdbg_do_check_page(vma,address);
+ + 	if(checkret < 0) return;
+ + 	
+ + 	clk_irq = ctexdbg_arch_lock_kernel();	
+ + 	
+ + 	p = ctexdbg_evdata;
+ + 	i = (uint32_t)checkret;
+ + 	memcpy(p,&i,sizeof(uint32_t));
+ + 		
+ + 	ctexdbg_event(current,CTEXDBG_EV_NOPAGE);			
+ + 	
+ + 	ctexdbg_arch_unlock_kernel(clk_irq);
+ + }
+ + 
+ + 
+ + /*
+ +  * file mapped handler (from do_mmap_pgoff)
+ +  */
+ + void ctexdbg_filemap(struct vm_area_struct * vma)
+ + {
+ + 	char *p;
+ + 	unsigned long clk_irq;	
+ + 	
+ + 	if(ctexdbg_enabled == 0) return;
+ + 
+ + 	if(vma == NULL) return;
+ + 	if((vma->vm_flags & VM_EXEC) == 0) return;
+ + 	
+ + 	clk_irq = ctexdbg_arch_lock_kernel();	
+ + 	
+ + 	if(ctexdbg_find_debugpid(current->pid) == NULL) goto filemap_exit;
+ + 	if(ctexdbg_varid_vma(vma) == 1)		goto filemap_exit;
+ + 	
+ + 	ctexdbg_prn("ctexdbg","ctexdbg_filemap %s\n",
+ + 				vma->vm_file->f_dentry->d_name.name);
+ + 
+ + 	if(ctexdbg_find_file((char*)vma->vm_file->f_dentry->d_name.name,NULL,0) == 0){
+ + 		goto filemap_exit;
+ + 	}
+ + 	p = ctexdbg_evdata;
+ + 	memcpy(p,&(current->pid),sizeof(uint32_t));
+ + 	p += sizeof(uint32_t);
+ + 	memcpy(p,&(vma->vm_start),sizeof(uint32_t));
+ + 	p += sizeof(uint32_t);
+ + 	memcpy(p,&(vma->vm_end),sizeof(uint32_t));
+ + 	p += sizeof(uint32_t);
+ + 	memcpy(p,&(vma->vm_file->f_dentry->d_name.len),sizeof(uint32_t));
+ + 	p += sizeof(uint32_t);
+ + 	memcpy(p,vma->vm_file->f_dentry->d_name.name,vma->vm_file->f_dentry->d_name.len);
+ + 		
+ + 	ctexdbg_event(current,CTEXDBG_EV_FILEMAP);
+ + 	
+ + filemap_exit:
+ + 	ctexdbg_arch_unlock_kernel(clk_irq);	
+ + }
+ + 
+ + /* happened fork and clone  */
+ + int ctexdbg_forking(struct task_struct *tsk,unsigned long clone_flags,unsigned long stack_start)
+ + {
+ + 	char *p;
+ + 	struct mm_struct *mm;
+ + 	struct vm_area_struct * map;
+ + 	unsigned long clk_irq;
+ + 
+ + 	if ((clone_flags & (CLONE_FS | CLONE_FILES | CLONE_VM | CLONE_SIGHAND)
+ + 		) != (CLONE_FS | CLONE_FILES | CLONE_VM | CLONE_SIGHAND) ) {
+ + 		return 0;
+ + 	}
+ + 	
+ + 	clk_irq = ctexdbg_arch_lock_kernel();
+ + 
+ + 	/* parent was debug process ? */
+ + 	if (ctexdbg_find_debugpid(current->pid) == NULL) goto forking_exit;
+ + 		
+ + 	/* no clone check mode */		
+ + 	if(ctexdbg_noclone_debug == 1)	goto forking_exit;
+ + 	
+ + 	/* find pthred lib */
+ + 	mm = tsk->mm;
+ + 	if(mm == NULL)		goto forking_exit;
+ + 	
+ + 	map = mm->mmap;
+ + 	while (map) {
+ + 		if(map->vm_file != NULL){
+ + 			if(strstr(map->vm_file->f_dentry->d_name.name,"libpthread") != NULL){
+ + 				break;
+ + 			}
+ + #ifdef CONFIG_CTEX_DBGLIB_ANDROID
+ + 			if(strstr(map->vm_file->f_dentry->d_name.name,"libc.so") != NULL){
+ + 				break;
+ + 			}
+ + #endif
+ + 		}
+ + 		map = map->vm_next;
+ + 	}
+ + 	if(map == NULL)	goto forking_exit;	
+ + 	
+ + 	/* stop a pthread clone only */
+ + 	p = ctexdbg_evdata;
+ + 	memcpy(p,&tsk->pid,sizeof(uint32_t));		/* create pid */
+ + 	p += sizeof(uint32_t);
+ + 	memcpy(p,&clone_flags,sizeof(uint32_t));	/* flags */
+ + 	p += sizeof(uint32_t);
+ + 	memcpy(p,&stack_start,sizeof(uint32_t));	/* start stack */
+ + 	p += sizeof(uint32_t);
+ + 	memcpy(p,&current->pid,sizeof(uint32_t));	/* paernt pid */
+ + 	p += sizeof(uint32_t);
+ + 	memcpy(p,&mm->pgd,sizeof(uint32_t));		/* pgd */
+ + 	p += sizeof(uint32_t);
+ + 
+ + 	ctexdbg_event(tsk,CTEXDBG_EV_FORK);		
+ + 		
+ + 	ctexdbg_add_debugpid(tsk->pid);
+ + 		
+ + 	ctexdbg_arch_unlock_kernel(clk_irq);
+ + 		
+ + 	return 0;
+ + 
+ + forking_exit:
+ + 	ctexdbg_arch_unlock_kernel(clk_irq);
+ + 	return 0;
+ + }
+ + 
+ + /* pre MAIN() break handler */
+ + int ctexdbg_main_pre_brk(struct task_struct *tsk,unsigned long entryaddr,unsigned long ppgd)
+ + {
+ + 	unsigned long clk_irq;
+ + 	char *p;
+ + 	if(ctexdbg_enabled == 0) return 0;
+ + 
+ + 	if(ctexdbg_premain_debug == 0)	return 0;
+ + 	
+ + 	clk_irq = ctexdbg_arch_lock_kernel();
+ + 		
+ + 	if (ctexdbg_find_debugpid(tsk->pid) == NULL) goto prebrk_exit;
+ + 	
+ + 	ctexdbg_prn("ctexdbg","ctexdbg_main_pre_brk pid %d entry %08X\n",tsk->pid,(unsigned int)entryaddr);
+ + 
+ + 	/* send data... [pid][entry] */
+ + 	p = ctexdbg_evdata;
+ + 	memcpy(p,&tsk->pid,sizeof(uint32_t));	/* pid */
+ + 	p += sizeof(uint32_t);
+ + 	memcpy(p,&entryaddr,sizeof(uint32_t));	/* entries address */
+ + 	p += sizeof(uint32_t);
+ + 	memcpy(p,&ppgd,sizeof(uint32_t));		/* pgd */
+ + 	p += sizeof(uint32_t);
+ + 
+ + 	ctexdbg_event(tsk,CTEXDBG_EV_PREMAIN);
+ + 	
+ + prebrk_exit:
+ + 	ctexdbg_arch_unlock_kernel(clk_irq);
+ + 	return 0;
+ + }
+ + 
+ + 
+ + /* ------------------------------- event handlers ---------------------------------- */
+ + 
+ + 
+ + void ctexdbg_process_exit(void)
+ + {
+ + 	char *p;
+ + 	unsigned long clk_irq;
+ + 	if(ctexdbg_enabled == 0) return;
+ + 	
+ + 	clk_irq = ctexdbg_arch_lock_kernel();
+ + 	
+ + 	if(ctexdbg_find_debugpid(current->pid) == NULL){
+ + 		goto process_exit_exit;
+ + 	}
+ + 	
+ + 	p = ctexdbg_evdata;
+ + 	memcpy(p,&current->pid,sizeof(uint32_t));		
+ + 	ctexdbg_event(current,CTEXDBG_EV_EXIT_WAIT);
+ + 	
+ + 	/* wait mode check (sup. v006 later) */
+ + 	if(ctexdbg_workbuf[0] != 1)	goto process_exit_removepid;
+ + 	
+ + 	if(ctexdbg_allbreak == 0){
+ + 		ctexdbg_arch_unlock_kernel(clk_irq);		
+ + 		/* waiting. for ctexdbg event */
+ + 		wait_event(kctexdbgd_exit_wait,ctexdbg_wakeuppid == current->pid);			
+ + 		clk_irq = ctexdbg_arch_lock_kernel();
+ + 		spin_lock(&ctexdbg_continue_spinlock);
+ + 		ctexdbg_wakeuppid = 0;
+ + 		spin_unlock(&ctexdbg_continue_spinlock);
+ + 	}
+ + 	ctexdbg_event(current,CTEXDBG_EV_EXIT_WAKEUP);
+ + 	
+ + process_exit_removepid:	
+ + 	ctexdbg_remove_debugpid(current->pid);
+ + process_exit_exit:	
+ + 	ctexdbg_arch_unlock_kernel(clk_irq);
+ + }
+ + 
+ + void ctexdbg_file_event(struct task_struct *tsk, struct file *file,uint32_t pgd)
+ + {
+ + 	char *p;
+ + 	unsigned long clk_irq;	
+ + 
+ + 	if(ctexdbg_enabled == 0) return;
+ + 	if(ctexdbg_noattach_debug == 1) return;
+ + 	if(file == NULL) return;
+ + 	
+ + 	ctexdbg_exec_limit_cpu_mask(tsk);
+ + 
+ + 	clk_irq = ctexdbg_arch_lock_kernel();
+ + 	
+ + 	if(ctexdbg_find_file((char*)file->f_dentry->d_name.name,NULL,0) == 0){
+ + 		ctexdbg_arch_unlock_kernel(clk_irq);
+ + 		ctexdbg_exec_setall_cpu_mask(tsk);
+ + 		return;
+ + 	}
+ + 
+ + 	p = ctexdbg_evdata;
+ + 	memcpy(p,&(tsk->pid),sizeof(uint32_t));
+ + 	p += sizeof(uint32_t);
+ + 	memcpy(p,&(file->f_dentry->d_name.len),sizeof(uint32_t));
+ + 	p += sizeof(uint32_t);
+ + 	memcpy(p,file->f_dentry->d_name.name,sizeof(char) * file->f_dentry->d_name.len);
+ + 	p += sizeof(char) * file->f_dentry->d_name.len;
+ + 	memcpy(p,&pgd,sizeof(uint32_t));
+ + 	p += sizeof(uint32_t);
+ + 
+ + 	ctexdbg_event(current,CTEXDBG_EV_EXECVP);								
+ + 	/* is this debug? */
+ + 	if(ctexdbg_workbuf[0] == 1){
+ + 		ctexdbg_add_debugpid(tsk->pid);
+ + 	}
+ + 	ctexdbg_arch_unlock_kernel(clk_irq);
+ + 	
+ + }
+ + 
+ + /*
+ +  * find wait queue and wakeup task ...
+ +  * r:
+ +  *  !0: not found
+ +  *  0: found and wakeup task
+ +  */  
+ + static int ctexdbg_wakeup_process(wait_queue_head_t *q,int mpid)
+ + {
+ + 	unsigned long flags;
+ + 	struct list_head *tmp;
+ + 	wait_queue_t *curr;
+ + 	struct task_struct *p;
+ + 	int ret = 1;
+ + 	int wret = 0;
+ + 	
+ + 	spin_lock_irqsave(&q->lock, flags);
+ + 	
+ + 	list_for_each(tmp, &q->task_list) {
+ + 		curr = list_entry(tmp, wait_queue_t, task_list);
+ + #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13) 
+ + 		p = curr->private;
+ + #else
+ + 		p = curr->task;
+ + #endif
+ + 		if(p->pid == mpid){
+ + 			ret = 0;
+ + 			spin_lock(&ctexdbg_continue_spinlock);
+ + 			ctexdbg_wakeuppid = mpid;
+ + 			wret = wake_up_process(p);
+ + 			spin_unlock(&ctexdbg_continue_spinlock);
+ + 			break;
+ + 		}
+ + 	}	
+ + 	spin_unlock_irqrestore(&q->lock, flags);
+ + 	return ret;
+ + }
+ + 
+ + /* ----------------- kctexdbg kernel thread part ----------------------------------------- */
+ + /*
+ +  * kctexdbg kernel thread monitor todo...
+ +  */
+ + int do_ctexdbg(void)
+ + {
+ + 	unsigned long lvar,kvar,nvar;
+ + 	unsigned long retvar;
+ + 	int i;
+ + 	int found=0;
+ + 
+ + 	while(1){
+ + 		if(ctexdbg_ddebugrecv == 1)		do_ctexdump();
+ + 	
+ + 		switch(ctexdbg_combuf[1]){
+ + 		case CTEXDBG_NONE:											/* 0 */
+ + 			/* No operation */
+ + 			break;
+ + 		case CTEXDBG_DBGPUT:										/* 1 */
+ + 			/* put combuf */
+ + 			do_ctexdump();
+ + 			break;
+ + 		case CTEXDBG_SENDSIG:										/* 2 */
+ + 			/* send pid */
+ + 			/*buf 4 5 6 7 ... pid */
+ + 			/*buf 8 9 10 11 ... sig */
+ + 			memcpy(&lvar,&ctexdbg_combuf[4],4);
+ + 			memcpy(&kvar,&ctexdbg_combuf[8],4);
+ + 			do_ctex_sendsig(lvar,kvar);
+ + 			break;
+ + 		case CTEXDBG_CONTINUE:										/* 3 */
+ + 			/* continue stopped pid */
+ + 			/*buf 4 5 6 7 ... pid */
+ + 			memcpy(&lvar,&ctexdbg_combuf[4],4);
+ + 			for(i=0;i<10;i++){
+ + 				/* wait queue check and run task */
+ + 				if(ctexdbg_wakeup_process(&kctexdbgd_process_wait,lvar) == 0)	{found=1; break;}
+ + 				if(ctexdbg_wakeup_process(&kctexdbgd_force_wait,lvar) == 0)		{found=1; break;}
+ + 				if(ctexdbg_wakeup_process(&kctexdbgd_signal_wait,lvar) == 0)	{found=1; break;}
+ + 				if(ctexdbg_wakeup_process(&kctexdbgd_exit_wait,lvar) == 0)		{found=1; break;}
+ + 				msleep(10);
+ + 			}
+ + 			if(found == 1) break;
+ + 			/* not found... send SIGCONT signal...*/
+ + 			ctexdbg_prn("ctexdbg","warn; CTEXDBG_CONTINUE not found waitprocess %d \n",(int)lvar);
+ + 			kvar = SIGCONT;
+ + 			do_ctex_sendsig(lvar,kvar);
+ + 			break;
+ + 		case CTEXDBG_FORCEBREAK:									/* 4 */
+ + 			/* force break process */
+ + 			/* send SIGSTOP signal */
+ + 			/*buf 4 5 6 7 ... pid */
+ + 			memcpy(&lvar,&ctexdbg_combuf[4],4);
+ + 			ctexdbg_forcebreaksig_pid = lvar;
+ + 			do_ctex_sendsig(lvar,SIGSTOP);
+ + 			break;
+ + 		
+ + 		/* ------------------ LTT and event ------------------------------- */
+ + 			
+ + 		case CTEXDBG_LTTRACE_START:									/* 5 */
+ + 			retvar = 0;
+ + #if defined(CONFIG_CTEX_TRACE)
+ + 			/*buf 4 5 6 7 ... size */
+ + 			/*buf 8 9 10 11 ... address */
+ + 			/*buf 12 13 14 15 ... stopmode */
+ + 			memcpy(&lvar,&ctexdbg_combuf[4],4);
+ + 			memcpy(&kvar,&ctexdbg_combuf[8],4);		
+ + 			memcpy(&nvar,&ctexdbg_combuf[12],4);		
+ + 			if(ctexdbg_tracer_start(lvar,nvar) != 0){
+ + 				retvar = 1;
+ + 			}
+ + #endif /* CONFIG_CTEX_TRACE */
+ + 			memcpy(ctexdbg_evdata		,&retvar	,sizeof(unsigned long));
+ + 			ctexdbg_event(current,CTEXDBG_EV_LTTRACE_STARTACK);
+ + 			break;
+ + 		case CTEXDBG_LTTRACE_STOP:									/* 6 */
+ + #if defined(CONFIG_CTEX_TRACE)
+ + 			ctexdbg_tracer_stop();
+ + #endif /* CONFIG_CTEX_TRACE */
+ + 			break;
+ + 		case CTEXDBG_EVENT_SETBUFSIZE:								/* 7 */
+ + 			/*buf 4 5 6 7 ... size */
+ + 			/*buf 8 9 10 11 ... address */
+ + 			/*buf 12 13 14 15 ... eventuse */
+ + 			retvar = 0;
+ + 			memcpy(&lvar,&ctexdbg_combuf[4],4);
+ + 			memcpy(&kvar,&ctexdbg_combuf[8],4);
+ + 			memcpy(&nvar,&ctexdbg_combuf[12],4);
+ + 			ctexdbg_EventUse = nvar;
+ + 			if(ctexdbg_EventUse == 1){
+ + 				ctexdbg_EventBufSize = lvar;
+ + 				if(ctexdbg_event_set_buffer_size(ctexdbg_EventBufSize) != 0){
+ + 					retvar = 1; /* buffer error */
+ + 				}
+ + 			}
+ + 			memcpy(ctexdbg_evdata		,&retvar	,sizeof(unsigned long));
+ + 			ctexdbg_event(current,CTEXDBG_EV_EVENTSET_END);
+ + 			break;
+ + 			
+ + 		/* ------------------ file opelation ------------------------------- */
+ + 			
+ + 		case CTEXDBG_FILE_LS:										/* 8 */
+ + 			/* buf 4 ... dirname */
+ + 			ctexdbg_file_ls(&ctexdbg_combuf[4]);
+ + 			break;
+ + 			
+ + 		case CTEXDBG_FILE_RMDIR:									/* 9 */
+ + 			/* buf 4 ... dirname */
+ + 			ctexdbg_file_rmdir(&ctexdbg_combuf[4]);
+ + 			break;
+ + 			
+ + 		case CTEXDBG_FILE_MKDIR:									/* 10 */
+ + 			/* buf 4 ... dirname */
+ + 			ctexdbg_file_mkdir(&ctexdbg_combuf[4]);
+ + 			break;			
+ + 
+ + 		case CTEXDBG_FILE_DELETE:									/* 11 */
+ + 			/* buf 4 ... dirname */
+ + 			ctexdbg_file_delfile(&ctexdbg_combuf[4]);
+ + 			break;
+ + 			
+ + 		case CTEXDBG_FILE_READ:										/* 12 */
+ + 			/* buf 4 ... dirname */
+ + 			ctexdbg_file_read(&ctexdbg_combuf[4]);
+ + 			break;
+ + 			
+ + 		case CTEXDBG_FILE_WRITE:									/* 13 */
+ + 			/* buf 4 ... dirname */
+ + 			ctexdbg_file_write(&ctexdbg_combuf[4]);
+ + 			break;					
+ + 			
+ + 		case CTEXDBG_FILE_RENAME:									/* 15 */
+ + 			/* buf 4 ... old+new path */
+ + 			ctexdbg_file_rename(&ctexdbg_combuf[4]);
+ + 			break;					
+ + 		
+ + 		case CTEXDBG_FILE_CHMOD:									/* 16 */
+ + 			/* buf 4 ... filename+attr */
+ + 			ctexdbg_file_chmod(&ctexdbg_combuf[4]);
+ + 			break;					
+ + 		
+ + 		case CTEXDBG_FILE_CHOWN:									/* 17 */
+ + 			/* buf 4 ... filename+attr */
+ + 			ctexdbg_file_chown(&ctexdbg_combuf[4]);
+ + 			break;					
+ + 			
+ + 		/* ------------------ misc ------------------------------- */
+ + 			
+ + 		case CTEXDBG_TEST:
+ + 			break;
+ + 		}
+ + 		
+ + 		if(ctexdbg_combuf[3] == 0)	break;
+ + 		
+ + 		/* waiting data from ICE .... */
+ + 		ctexdbg_event(current,CTEXDBG_EV_WAITDATA);
+ + 	}
+ + 	
+ + 	return 0;
+ + }
+ + 
+ + 
+ + /*
+ +  * ctexdbgd wakeup check
+ +  * r:
+ +  *  0: sleeping or runnung
+ +  *  1: now wakeup
+ +  */
+ + int ctexdbg_checkwakeup(void)
+ + {
+ + 	if(ctexdbg_combuf[0] == 0) return 0;
+ + 	ctexdbg_combuf[0] = 0;
+ + 	ctexdbgd_wake=1;
+ + 	wake_up(& kctexdbgd_wait);
+ + 	return 1;
+ + }
+ + 
+ + 
+ + /*
+ +  * ctexdbg kernel thread (monitor)
+ +  */
+ + int ctexdbg(void *startup)
+ + {
+ + #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,8,0)
+ + 	int waitsig;
+ + 	struct sched_param param = { .sched_priority = MAX_RT_PRIO-1 };
+ + 	
+ + 	/* ctexdbg must be cpuid zero */
+ + 	set_cpus_allowed(current, CPU_MASK_CPU0);
+ + 	ctexdbg_daemon_cpuid = smp_processor_id();
+ + 	
+ + #elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) 
+ + 	int waitsig;
+ + 	struct sched_param param = { .sched_priority = MAX_RT_PRIO-1 };
+ + 	
+ + 	/* ctexdbg must be cpuid zero */
+ + 	set_cpus_allowed(current, CPU_MASK_CPU0);
+ + 	ctexdbg_daemon_cpuid = smp_processor_id();
+ + 	daemonize("kctexdbgd/%d",ctexdbg_daemon_cpuid);	
+ + #else
+ + 	struct task_struct * tsk = current;
+ + 	
+ + 	tsk->session = 1;
+ + 	tsk->pgrp = 1;
+ + 	strcpy(tsk->comm, "kctexdbgd");
+ + 
+ + 	/* avoid getting signals */
+ + 	spin_lock_irq(&tsk->sigmask_lock);
+ + 	flush_signals(tsk);
+ + 	sigfillset(&tsk->blocked);
+ + 	recalc_sigpending(tsk);
+ + 	spin_unlock_irq(&tsk->sigmask_lock);
+ + #endif /* LinuxVer */
+ + 
+ + 	ctexdbg_nrcpus = (uint32_t)num_online_cpus();
+ + 	
+ + 	memcpy(ctexdbg_patchver_char,CTEXDBG_PATCH_VERSION,4);
+ + 	memcpy(&(ctexdbg_patchver_char[4]),CTEXDBG_PATCH_VERSION,4);
+ + 
+ + 	complete((struct completion *)startup);
+ + 	
+ + 	printk("ctexdbg enabled by computex.patch vers=%s online cpu=%d \n",ctexdbg_patchver_char,ctexdbg_nrcpus);
+ + 	
+ + 	sched_setscheduler(current, SCHED_FIFO, &param);
+ + 	
+ + 	/* checking ICE connect */
+ + 	ctexdbg_arch_checkice();	
+ + 	
+ + 	for (;;) {
+ + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) 
+ + 		waitsig = wait_event_interruptible(kctexdbgd_wait,ctexdbgd_wake != 0);
+ + 		if(waitsig == -ERESTARTSYS)	continue;	/* was signal happened */
+ + 		if(ctexdbgd_wake == 0)	continue;
+ + 		ctexdbgd_wake = 0;		/* iam wakeup */
+ + 		do_ctexdbg();
+ + #else
+ + 		if(!freezing(current)){
+ + 			waitsig = wait_event_interruptible(kctexdbgd_wait,ctexdbgd_wake != 0);
+ + 			if(waitsig == -ERESTARTSYS)	continue;	/* was signal happened */
+ + 			if(ctexdbgd_wake == 0)	continue;
+ + 		}
+ + 		if(!try_to_freeze()){
+ + 			ctexdbgd_wake = 0;		/* iam wakeup */
+ + 			do_ctexdbg();
+ + 		}
+ + #endif
+ + 	}
+ + 	return 0;
+ + } 
+ + 
+ + /*
+ +  * Initialize a ctexdbg thread
+ +  */
+ + static int __init ctexdbg_init(void)
+ + {
+ + 	static struct completion startup __initdata = COMPLETION_INITIALIZER(startup);
+ + 	int i;
+ + 	spin_lock_init(&ctexdbg_kernel_spinlock);
+ + 	spin_lock_init(&ctexdbg_continue_spinlock);	
+ + 	ctexdbg_daemon_cpuid = 0;
+ + 	/* initialize internal data */
+ + 	ctexdbg_traceuse = 0;
+ + 	ctexdbg_wakeuppid = 0;
+ + 	ctexdbg_forcebreaksig_pid = 0;
+ + 	ctexdbg_enabled = 0;
+ + 	ctexdbg_hardware_trace_enabled = 0;
+ + 	ctexdbg_xipinram = 0;
+ + 	ctexdbgd_wake = 0;
+ + 	
+ + 	for(i=0;i<=_NSIG;i++){
+ + 		/* set stop signal... */
+ + 		ctexdbg_breaksig[i] = 1;
+ + 	}
+ + 	/* ignoreos signal */
+ + 	ctexdbg_breaksig[SIGSTOP] = 0;
+ + 	ctexdbg_breaksig[SIGCONT] = 0;
+ + 	ctexdbg_breaksig[SIGPROF] = 0;
+ + 	ctexdbg_breaksig[SIGALRM] = 0;
+ + 	ctexdbg_breaksig[SIGCHLD] = 0;
+ + 	ctexdbg_breaksig[SIGUSR1] = 0;
+ + 	ctexdbg_breaksig[SIGUSR2] = 0;
+ + 	ctexdbg_breaksig[SIGVTALRM] = 0;
+ + 	ctexdbg_breaksig[SIGIO] = 0;
+ + 	ctexdbg_breaksig[SIGPOLL] = 0;
+ + 	ctexdbg_breaksig[SIGWINCH] = 0;
+ + 	ctexdbg_breaksig[SIGTSTP] = 0;
+ + 	ctexdbg_breaksig[SIGTTIN] = 0;
+ + 	ctexdbg_breaksig[SIGTTOU] = 0;
+ + 	
+ + 	ctexdbg_forcebreaksig_pid = 0;
+ + 	ctexdbg_allbreak = 0;
+ + 	ctexdbg_pexitnochk = 0;
+ + 	ctexdbg_noclone_debug = 0;
+ + 	ctexdbg_noattach_debug = 0;
+ + 	ctexdbg_premain_debug = 0;
+ + 
+ + 	memset((void*)&ctexdbg_fixdata,0,sizeof(ctexdbg_fix));
+ + 	
+ + 	ctexdbg_arch_userregaddr();
+ + 	ctexdbg_arch_init();
+ + 	
+ + 	memset(ctexdbg_combuf,0,512);
+ + 	
+ + 	for(i=0;i<10;i++){
+ + 		ctexdbg_envpdata[i] = 0;
+ + 	}
+ + 	ctexdbg_envpstr[0] = '\0';
+ + 	ctexdbg_preloadlib[0] = '\0';
+ + 
+ + 	for(i=0; i < CTEXDBG_PGOFF_MAX ;i++){
+ + 		ctexdbg_areatable[i].pid = 0;
+ + 		ctexdbg_areatable[i].pgd = 0;
+ + 	}
+ + 	
+ + 	for(i=0; i < CTEXDBG_PIDSIZE_MAX ;i++){
+ + 		ctexdbg_debugpid[i].pid = 0;
+ + 		ctexdbg_debugpid[i].migration = 0;
+ + 	}
+ + 
+ + 	for(i=0; i < CTEXDBG_MODULE_MAX ;i++){
+ + 		ctexdbg_moddata[i].mod = NULL;
+ + 	}
+ + 			
+ + 	memset((void*)ctexdbg_dbgfile,0,CTEXDBG_DBG_FNAMESIZE);
+ + #ifdef CONFIG_CTEX_DBGLIB_ANDROID
+ + 	ctexdbg_android = 1;				/* android flag */
+ + #endif	
+ + 	ctexdbg_event_init();
+ + #if defined(CONFIG_CTEX_TRACE)
+ + 	ctexdbg_tracer_init();
+ + #endif /* CONFIG_CTEX_TRACE */
+ + 	
+ + 	/* enable something events ... */
+ + 	ctexdbg_tracebufpos.sEventBuf = NULL;
+ + 	ctexdbg_tracebufpos.sEventWritPos = NULL;
+ + 	ctexdbg_tracebufpos.sEventReadPos = NULL;
+ + 	ctexdbg_tracebufpos.sEventWritLimit = NULL;
+ + 	ctexdbg_tracebufpos.sEventBufDir = 0;
+ + 	
+ + 	ctexdbg_evdata = (unsigned char*)(ctexdbg_workbuf + CTEXDBG_WORKBUF_START);
+ + 	ctexdbg_debugpidmax = CTEXDBG_PIDSIZE_MAX;
+ + 	
+ + 	ctexdbg_fixdata.maxdbgfilelen = CTEXDBG_DBG_FNAMESIZE;
+ + 	ctexdbg_fixdata.maxmapdatalen = CTEXDBG_MMAPDATA_SIZE;
+ + 	ctexdbg_fixdata.maxevtasklen = CTEXDBG_EVENT_FNAMESIZE;
+ + 	ctexdbg_fixdata.maxtrcmasklen = CTEXTRC_MASK_SIZE;
+ + 
+ + #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,8,0)
+ + 	kthread_run(ctexdbg, &startup,"kctexdbgd/%d",0);
+ + #elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+ + 	kernel_thread(ctexdbg, &startup, CLONE_KERNEL);
+ + #else
+ + 	kernel_thread(ctexdbg, &startup, CLONE_FS | CLONE_FILES | CLONE_SIGNAL);
+ + #endif /* Linuxver */
+ + 	wait_for_completion(&startup);
+ +   
+ + 	return 0;
+ + }
+ + 
+ + module_init(ctexdbg_init)
+ diff -crN linux-3.2.1_o/kernel/ctexevt.c linux-3.2.1/kernel/ctexevt.c
+ *** linux-3.2.1_o/kernel/ctexevt.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/kernel/ctexevt.c	2014-11-14 21:03:15.658351676 +0900
+ ***************
+ *** 0 ****
+ --- 1,358 ----
+ + /*
+ +  * linux/kernel/ctexevt.c
+ +  *
+ +  * (C) Copyright 2004 - Computex co.,ltd.
+ +  *
+ +  * Computex dbglib support library event notifyer
+ +  *
+ +  * -- version info --------------------------------------------------
+ +  *
+ +  * version 008 - 2005/12/EE		add ctexdbg_EventJackEnv
+ +  *                               (e/d LD_PRELOAD)
+ +  *
+ +  * version 005 - 2005/02/23		first release version
+ +  *
+ +  * version 004 - 2005/02/1x		pre version
+ +  *
+ +  * -------------------------------------------------------------------
+ +  *
+ +  */
+ + 
+ + #include <linux/kernel.h>
+ + #include <linux/init.h>     /* For __init */
+ + #include <linux/errno.h>    /* Miscellaneous error codes */
+ + #include <linux/module.h>   /* EXPORT_SYMBOL */
+ + #include <linux/proc_fs.h>
+ + #include <linux/unistd.h>
+ + #include <linux/version.h>
+ + #include <linux/ctexdbg.h>  /* definitions */
+ + #include <linux/sched.h>
+ + #include <linux/completion.h>
+ + #include <linux/vmalloc.h>
+ + #include <linux/interrupt.h>
+ + 
+ + #include <linux/slab.h>
+ + #include <linux/ctype.h>
+ + #include <linux/pagemap.h>
+ + 
+ + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) 
+ + #include <asm/semaphore.h>
+ + #include <asm/processor.h>
+ + #endif 
+ + #include <linux/mm.h>
+ + 
+ + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) 
+ + #include <linux/wrapper.h>
+ + #include <linux/locks.h>
+ + #else
+ + #include <linux/namei.h>
+ + #endif 
+ + 
+ + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) 
+ + #include <linux/devfs_fs_kernel.h>
+ + #endif
+ + 
+ + #include <asm/uaccess.h>
+ + #include <linux/binfmts.h>
+ + 
+ + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36) 
+ + extern int copy_strings_kernel(int argc,char ** argv, struct linux_binprm *bprm);
+ + #endif
+ + 
+ + typedef struct __tag_cdbevt_bufpos
+ + {
+ + 	char* sEventBuf;                  /* Event Buffer */
+ + 	char* sEventWritPos;              /* Current position for writting */
+ + 	char* sEventReadPos;              /* Current position for reading */
+ + 	char* sEventWritLimit;            /* Limit at which write should stop */	
+ + 	uint32_t  sEventBufDir;			  /* Buffer dir */
+ + }cdbevt_bufpos;
+ + 
+ + typedef struct __tag_cdbevt_common_data
+ + {
+ +   unsigned long eid;      /* event id */
+ +   unsigned long pid;      /* process id */
+ +   unsigned long size;     /* after private data size */
+ + }cdbevt_common_data;
+ + 
+ + extern char*  ctexdbg_envpdata[10];		/* special envp */
+ + extern char   ctexdbg_envpstr[100];
+ + extern char   ctexdbg_preloadlib[100];
+ + extern uint32_t ctexdbg_enabled;		/* enable disable ctexdbg */
+ + 
+ + static uint32_t               sBufSize;              /* Buffer sizes */
+ + static uint32_t               sAllocSize;            /* Size of buffers allocated */
+ + 
+ + cdbevt_bufpos	ctexdbg_eventbufpos;				/* buffer position */
+ + 
+ + 
+ + char* ctexdbg_EventBuf = NULL;							/* pointer of Event buffer */
+ + uint32_t ctexdbg_EventBufSize = CTEXDBG_EVENTBUF_SIZE;	/* event buffer size */
+ + uint32_t ctexdbg_EventUse = 0;							/* enable event */
+ + uint32_t ctexdbg_EventAll = 0;							/* v008: 0: event use debug process only */
+ +  														/*       1: event use all process */
+ + 														/*       2: Mask event name */
+ + uint32_t ctexdbg_EventJackEnv = 0;						/* v008: 0: use envp jack */
+ + 														/*       1: unuse envp jack */
+ + 
+ + //#ifndef CONFIG_ARM
+ + #define CTEXDBG_TRACER_BUFSTATIC
+ + //#endif /* NOTARM */
+ + 
+ + #ifdef CTEXDBG_TRACER_BUFSTATIC
+ + static char ctexdbg_sEventBuffer[CTEXDBG_EVENTBUF_SIZE];
+ + #endif /* CTEXDBG_TRACER_BUFSTATIC */
+ + 
+ + uint32_t ctexdbg_EventMaskName = 0;						/* v006: 0: no event mask  */
+ + 														/*       1: event mask proc name */
+ + char ctexdbg_eventtskname[CTEXDBG_EVENT_FNAMESIZE];	/* debug file list (need ctexdbg_pexitnochk = 1) */
+ + 
+ + static spinlock_t             sSpinLock;             /* Spinlock in order to lock kernel */
+ + 
+ + 
+ + /* ------------------------ memry allocate --------------------------------------------- */
+ + #define FIX_SIZE(x) (((x) - 1) & PAGE_MASK) + PAGE_SIZE /* This inspired by rtai/shmem */
+ + 
+ + /* --- kernel execvp hook --- */
+ + 
+ + /* check preload library */
+ + int ctexdbg_set_envp_ldpreload(void)
+ + {
+ + 	int paerror = 0;
+ + 	struct path xpath;
+ + 	if(ctexdbg_preloadlib[0] == '\0') return 1;
+ + 	paerror = kern_path(ctexdbg_preloadlib, LOOKUP_FOLLOW, &xpath);
+ + 	if (paerror) return 1;
+ + 	path_put(&xpath);
+ + 	
+ + 	strcpy(ctexdbg_envpstr,"LD_PRELOAD=");
+ + 	strcat(ctexdbg_envpstr,ctexdbg_preloadlib);
+ + 	
+ + 	return 0;
+ + }
+ + 
+ + /* returned special enviroment envp */
+ + int ctexdbg_get_subenvp(char *filename, void *bprm)
+ + {
+ + 	struct linux_binprm *l_bprm = (struct linux_binprm *)bprm;
+ + 	int retval=0;
+ + 	if(ctexdbg_enabled == 0) return 0;
+ + 	if(ctexdbg_EventUse == 0) return 0;
+ + 	
+ + 	if(ctexdbg_EventAll == 0){
+ + 		if(ctexdbg_find_debugpid(current->pid) == NULL) return 0;
+ + 	}
+ + 	
+ + 	if(ctexdbg_EventAll == 2){
+ + 		if(ctexdbg_find_file (filename,ctexdbg_eventtskname,CTEXDBG_EVENT_FNAMESIZE) == 0){
+ + 			return 0;
+ + 		}	
+ + 	}	
+ + 	
+ + 	if(ctexdbg_eventbufpos.sEventBuf == NULL){
+ + 		ctexdbg_event_set_buffer_size(ctexdbg_EventBufSize);
+ + 	}
+ + 	
+ + 	if(ctexdbg_EventJackEnv == 1){
+ + 		/* do not jacking */
+ + 		return 0;
+ + 	}
+ + 	/* Jacking... injection preload library */
+ + 	if(ctexdbg_set_envp_ldpreload() == 1) return 0;
+ + 	
+ + 	ctexdbg_envpdata[0] = (char *) &ctexdbg_envpstr;
+ + 	
+ + 	retval = copy_strings_kernel(1,(const char* const*)ctexdbg_envpdata , l_bprm);
+ + 	if(retval < 0) return -1;
+ + 	
+ + 	l_bprm->envc += 1;
+ + 	return 0;
+ + }
+ + /* ---------------------------------- */
+ + 
+ + 
+ + #define BKK(x) ((x) << PAGE_SHIFT)
+ + 
+ + static void ctexdbg_event_cleanbuf(void)
+ + {
+ + 	memset(ctexdbg_eventbufpos.sEventBuf,0xFE,sBufSize);
+ + }
+ + 
+ + int ctexdbg_event_set_buffer_size(int pmSize)
+ + {
+ + #ifdef CTEXDBG_TRACER_BUFSTATIC
+ +  /* clean */
+ + 	ctexdbg_eventbufpos.sEventBuf = NULL;
+ + 	ctexdbg_eventbufpos.sEventWritPos = NULL;
+ + 	ctexdbg_eventbufpos.sEventReadPos = NULL;
+ + 	ctexdbg_eventbufpos.sEventWritLimit = NULL;
+ + 	ctexdbg_eventbufpos.sEventBufDir = 0;	
+ + 	
+ + 	ctexdbg_eventbufpos.sEventBuf = ctexdbg_sEventBuffer;
+ + 	
+ + 	sBufSize = CTEXDBG_EVENTBUF_SIZE;
+ + 	sAllocSize = CTEXDBG_EVENTBUF_SIZE;  
+ + 
+ + #else /* CTEXDBG_TRACER_BUFSTATIC */
+ + 	int	lSizeAlloc;     	/* Size to be allocated */
+ + 	int	lSizeMax;		/* Max alloc size */
+ + 	struct sysinfo i;		/* memory size */
+ + 	
+ + 	/* Set size to allocate (= pmSize) and fix it's size to be on a page boundary */
+ + 	lSizeAlloc = FIX_SIZE(pmSize);
+ + 	
+ + 	/* Free the current buffers, if any */
+ + 	if(ctexdbg_eventbufpos.sEventBuf !=  NULL)
+ + 		kfree(ctexdbg_eventbufpos.sEventBuf);
+ + 	/* clean */
+ + 	ctexdbg_eventbufpos.sEventBuf = NULL;
+ + 	ctexdbg_eventbufpos.sEventWritPos = NULL;
+ + 	ctexdbg_eventbufpos.sEventReadPos = NULL;
+ + 	ctexdbg_eventbufpos.sEventWritLimit = NULL;
+ + 	ctexdbg_eventbufpos.sEventBufDir = 0;	
+ + 		
+ + 	/* calclation sizeing...*/
+ + 	si_meminfo(&i);
+ + 	lSizeMax = BKK(i.freeram) - 100000;
+ + 	if(lSizeAlloc >= lSizeMax){
+ + 		/* Over memory ... return ERROR */
+ + 		ctexdbg_EventUse = 0;
+ + 		return 1;
+ + 	}
+ + 	
+ + 	/* Allocate space for the tracing buffers */
+ + 	if((ctexdbg_eventbufpos.sEventBuf = (char*) kmalloc(lSizeAlloc,GFP_KERNEL|__GFP_NORETRY)) == NULL){
+ + 		ctexdbg_EventUse = 0;
+ + 		return 1;
+ + 	}
+ + 		
+ + 	/* Remember the size set */
+ + 	sBufSize = pmSize;
+ + 	sAllocSize = lSizeAlloc;
+ + 
+ + #endif /* CTEXDBG_TRACER_BUFSTATIC */
+ +   
+ + 	/* Set the read and write buffers */
+ + 	ctexdbg_eventbufpos.sEventWritPos = ctexdbg_eventbufpos.sEventBuf;
+ + 	
+ + 	/* Set write limit */
+ + 	ctexdbg_eventbufpos.sEventWritLimit = ctexdbg_eventbufpos.sEventWritPos + sBufSize;
+ + 	
+ + 	/* Set write position */
+ + 	ctexdbg_eventbufpos.sEventReadPos = ctexdbg_eventbufpos.sEventBuf;
+ + 	
+ + 	ctexdbg_event_cleanbuf();
+ + 	
+ + 	/* All is OK */
+ + 	return 0;
+ + }
+ + 
+ + 
+ + void ctexdbg_event_switch_buffers(void)
+ + {
+ + 	if(ctexdbg_eventbufpos.sEventReadPos == ctexdbg_eventbufpos.sEventBuf){
+ + 		/* STOP! this read point ... */
+ + 		ctexdbg_eventfull_bp();
+ + 		ctexdbg_eventbufpos.sEventBufDir = 0;
+ + 		ctexdbg_eventbufpos.sEventReadPos = ctexdbg_eventbufpos.sEventBuf;
+ + 	}else if(ctexdbg_eventbufpos.sEventBufDir == 0){
+ + 		ctexdbg_eventbufpos.sEventBufDir = 1;
+ + 	}else{
+ + 		/* STOP! this read point ... */
+ + 		ctexdbg_eventfull_bp();
+ + 		ctexdbg_eventbufpos.sEventBufDir = 0;
+ + 		ctexdbg_eventbufpos.sEventReadPos = ctexdbg_eventbufpos.sEventBuf;
+ + 	}
+ + 	ctexdbg_eventbufpos.sEventWritPos = ctexdbg_eventbufpos.sEventBuf;
+ + }
+ + 
+ + void ctexdbg_event_read_buffers(void)
+ + {
+ + 	/* read stop */
+ + 	ctexdbg_eventfull_bp();
+ + 	
+ + 	ctexdbg_eventbufpos.sEventWritPos = ctexdbg_eventbufpos.sEventBuf;
+ + 	ctexdbg_eventbufpos.sEventReadPos = ctexdbg_eventbufpos.sEventBuf;
+ + 	ctexdbg_eventbufpos.sEventBufDir = 0;
+ + }
+ + 
+ + int ctexdbg_event_filter(void *ptr)
+ + {
+ + 	cdbevt_common_data *pdata = (cdbevt_common_data *)ptr;
+ + 	struct task_struct *tsk;
+ + 	struct mm_struct *mm;
+ + 		
+ + 	if(ctexdbg_EventAll == 1) return 0;
+ + 	
+ + 	if(ctexdbg_EventAll == 0){
+ + 		if(ctexdbg_EventJackEnv == 0){
+ + 			return 0;
+ + 		}
+ + 		if(ctexdbg_find_debugpid(current->pid) != NULL) return 0;
+ + 		
+ + 		return 1;
+ + 	}
+ + 	
+ + #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,26)
+ + //	tsk = find_task_by_pid_type_ns(PIDTYPE_PID, pdata->pid, &init_pid_ns);
+ + 	tsk = find_task_by_pid_ns(pdata->pid, &init_pid_ns);
+ + #else
+ + 	tsk = find_task_by_pid(pdata->pid);
+ + #endif	
+ + 	
+ + 	if(tsk == NULL) return 1;
+ + 	
+ + 	mm = tsk->mm;
+ + 	if(ctexdbg_varid_dname(mm) == 1){
+ + 		return 1;
+ + 	}
+ + 	if(ctexdbg_find_file ((char *) mm->mmap->vm_file->f_dentry->d_name.name,ctexdbg_eventtskname,CTEXDBG_EVENT_FNAMESIZE) == 0){
+ + 		return 1;
+ + 	}
+ + 	return 0;
+ + }
+ + 
+ + 
+ + /*
+ +  * event notify from user program
+ +  */
+ + void ctexdbg_external_notify(size_t size,void *ptr)
+ + {
+ + 	unsigned long int   lFlags;                   /* CPU flags for lock */
+ + 	
+ + 	if( ctexdbg_enabled == 0 ) return;
+ + 	if( ctexdbg_EventUse == 0 ) return;
+ + 	
+ + 	/* Lock the kernel */
+ + 	spin_lock_irqsave(&sSpinLock, lFlags);	
+ + 	
+ + 	if( ctexdbg_event_filter(ptr) == 1) goto notify_exit;
+ + 	if( (ctexdbg_eventbufpos.sEventWritPos + size) >= ctexdbg_eventbufpos.sEventWritLimit){
+ + 		/* Switch buffers */
+ + 		ctexdbg_event_switch_buffers();
+ + 	}
+ + 	if((ctexdbg_eventbufpos.sEventBufDir == 1) && 
+ + 		( (ctexdbg_eventbufpos.sEventWritPos + size) >= ctexdbg_eventbufpos.sEventReadPos) ){
+ + 		ctexdbg_event_read_buffers();
+ + 	}
+ + 	
+ + 	if(copy_from_user(ctexdbg_eventbufpos.sEventWritPos, (void*) ptr, size)){
+ + 		printk("ctexdbg: read miss event\n");
+ + 		goto notify_exit;
+ + 	}
+ + 	ctexdbg_eventbufpos.sEventWritPos += size;
+ + 
+ + notify_exit:
+ + 	spin_unlock_irqrestore(&sSpinLock, lFlags);	
+ + }
+ + 
+ + void ctexdbg_event_init()
+ + {
+ + 	spin_lock_init(&sSpinLock);
+ + 	ctexdbg_eventbufpos.sEventBuf = NULL;
+ + 	ctexdbg_eventbufpos.sEventWritPos = NULL;
+ + 	ctexdbg_eventbufpos.sEventReadPos = NULL;
+ + 	ctexdbg_eventbufpos.sEventWritLimit = NULL;
+ + 	ctexdbg_eventbufpos.sEventBufDir = 0;
+ + 	memset(ctexdbg_eventtskname,0,CTEXDBG_EVENT_FNAMESIZE);
+ + }
+ diff -crN linux-3.2.1_o/kernel/ctexfile.c linux-3.2.1/kernel/ctexfile.c
+ *** linux-3.2.1_o/kernel/ctexfile.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/kernel/ctexfile.c	2014-11-14 21:03:15.658351676 +0900
+ ***************
+ *** 0 ****
+ --- 1,534 ----
+ + /*
+ +  * linux/kernel/ctexfile.c
+ +  *
+ +  * (C) Copyright 2004 - Computex co.,ltd.
+ +  *
+ +  * Computex dbglib support kernel thread (file operation)
+ +  *
+ +  * -- version info --------------------------------------------------
+ +  *
+ +  * version 012   - 2007/07/EE	update patch version
+ +  *                               + support SMP
+ +  *                               + add file operation buffer
+ +  *                               + fixed file sync
+ +  *
+ +  * version 008 - 2005/12/EE		support file rename chmod chown
+ +  *
+ +  * version 005 - 2005/02/23		first release version
+ +  *
+ +  * version 004 - 2005/02/1x		pre version
+ +  *
+ +  * ------------------------------------------------------------------- 
+ +  */
+ + #define __KERNEL_SYSCALLS__
+ + 
+ + #include <linux/kernel.h>
+ + #include <linux/init.h>     /* For __init */
+ + #include <linux/proc_fs.h>
+ + #include <linux/unistd.h>
+ + #include <linux/dirent.h>
+ + #include <linux/version.h>
+ + 
+ + 
+ + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) 
+ + #include <linux/locks.h>
+ + #endif 
+ + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) 
+ + #include <linux/devfs_fs_kernel.h>
+ + #endif
+ + #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,20) 
+ + #include <linux/syscalls.h>
+ + #endif
+ + 
+ + 
+ + #include <linux/ctexdbg.h>  /* definitions */
+ + #include <linux/errno.h>    /* Miscellaneous error codes */
+ + #include <linux/file.h>
+ + #include <linux/delay.h>
+ + 
+ + #define CTEXDBG_FILEOP_SYNC_DUMMY_NAME ".ctexdbg_fop_temp"
+ + 
+ + enum CTEXDBG_FILE_MARKER
+ + {
+ + 	CTEXDBG_FILE_M_LS = 0,
+ + 	CTEXDBG_FILE_M_READ,
+ + 	CTEXDBG_FILE_M_WRITE,
+ + 	CTEXDBG_FILE_M_RMDIR,
+ + 	CTEXDBG_FILE_M_MKDIR,
+ + 	CTEXDBG_FILE_M_DELFILE,
+ + };
+ + 
+ + enum CTEXDBG_FILE_SMARKER
+ + {
+ + 	CTEXDBG_FILE_S_OK = 0,
+ + 	CTEXDBG_FILE_S_ERR,
+ + 	CTEXDBG_FILE_S_ERR_OPEN,
+ + 	CTEXDBG_FILE_S_ERR_STAT,
+ + };
+ + 
+ + extern unsigned char ctexdbg_filebuf[CTEXDBG_WORKBUF_SIZE+1];	/* file op working buffer (1kb) */
+ + 
+ + extern void ctexdbg_filelsfull_bp(void);
+ + extern unsigned long ctexdbg_fileread_bp(void);
+ + extern unsigned long ctexdbg_filewrite_bp(void);
+ + extern void ctexdbg_fileend_bp(void);
+ + 
+ + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) 
+ + extern long sys_getdents(unsigned int fd, void * dirent, unsigned int count);
+ + extern long sys_newlstat(char * filename, struct stat * statbuf);
+ + extern long sys_rmdir(const char * pathname);
+ + extern long sys_mkdir(const char * pathname);
+ + extern int sys_rename(const char * oldname, const char * newname);
+ + extern int sys_chmod(const char * filename, mode_t mode);
+ + extern long sys_chown(const char * filename, uid_t user, gid_t group);
+ + extern long sys_unlink(const char * pathname);
+ + #endif	
+ + 
+ + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21) 
+ + extern asmlinkage long sys_getdents(unsigned int fd, struct linux_dirent __user *dirent,unsigned int count);	
+ + extern asmlinkage long sys_newlstat(char __user *filename,struct stat __user *statbuf);	
+ + extern asmlinkage long sys_rmdir(const char __user *pathname);
+ + extern asmlinkage long sys_mkdir(const char __user *pathname, int mode);
+ + extern asmlinkage long sys_rename(const char __user * oldname, const char __user * newname);
+ + extern asmlinkage long sys_chmod(const char __user *filename, mode_t mode);
+ + extern asmlinkage long sys_chown(const char __user *filename,uid_t user, gid_t group);
+ + extern asmlinkage long sys_unlink(const char __user *pathname);
+ + #endif	
+ + 
+ + int ctexdbg_sprit_path(char *path)
+ + {
+ + 	int len,i;
+ + 	len = strlen(path);
+ + 	for(i=len-1;i>=0;i--){
+ + 		if(path[i] == '/'){
+ + 			return i;
+ + 		}
+ + 	}
+ + 	return -1;
+ + }
+ + 
+ + /* tempolaly file write and syncing inode... */
+ + void ctexdbg_temp_sync(char *path)
+ + {
+ + 	int fdds;
+ + 	int pathsprit;
+ + 	char readdata[10];
+ + 	char tmppathname[NAME_MAX];
+ + 
+ + 	pathsprit = ctexdbg_sprit_path(path);
+ + 	if(pathsprit == -1){
+ + 		return;
+ + 	}
+ + 	strncpy(tmppathname,path,NAME_MAX);
+ + 	tmppathname[pathsprit+1] = '\0';
+ + 	strncat(tmppathname,CTEXDBG_FILEOP_SYNC_DUMMY_NAME,NAME_MAX);
+ + 
+ + 	fdds = sys_open(tmppathname, O_WRONLY|O_CREAT|O_TRUNC, S_IRWXU | S_IRWXG | S_IRWXO);		
+ + 	if(fdds < 0){
+ + 		return;
+ + 	}
+ + 	
+ + 	sys_write(fdds,readdata,10);
+ + 	sys_fsync(fdds);
+ + 	sys_close(fdds);
+ + 	sys_sync();
+ + 
+ + 	sys_unlink(tmppathname);
+ + 	sys_sync();
+ + 
+ + 	return;
+ + }
+ + 
+ + inline unsigned char* ctexdbg_file_writemarker(unsigned char *buf,unsigned long marker,unsigned long submarker,unsigned long er)
+ + {
+ + 	memcpy(buf  ,&marker,sizeof(unsigned long));
+ + 	memcpy(buf+4,&submarker,sizeof(unsigned long));
+ + 	memcpy(buf+8,&er,sizeof(unsigned long));
+ + 	buf += 12;
+ + 	return buf;
+ + }
+ + 
+ + int ctexdbg_file_ls(char *path)
+ + {
+ + 	int fdds;
+ + 	int readbyte;
+ + 	int namelen;
+ + 	unsigned long ssize;
+ + 	char buff[512];
+ + 	char files[512];
+ + 	char *writesrc;
+ + 	char *writedata;
+ + 	char *writeend;
+ + 	struct stat fstats;
+ + 	
+ + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) 
+ + 	struct dirent *dirp;
+ + #else
+ + 	struct linux_dirent64 *dirp;
+ + #endif
+ + 	unsigned short t_shorts;
+ + 	
+ + 	writesrc = (unsigned char*)(ctexdbg_filebuf + CTEXDBG_WORKBUF_START);
+ + 	
+ + 	writedata = writesrc;
+ + 	writeend = writesrc + CTEXDBG_WORKBUF_END;
+ + 	sys_sync();
+ + 	fdds = sys_open(path, O_RDONLY, 0);
+ + 	if(fdds < 0){
+ + 		writedata = writesrc;
+ + 		ctexdbg_file_writemarker(writedata,CTEXDBG_FILE_M_LS,CTEXDBG_FILE_S_ERR_OPEN,-fdds);
+ + 		ctexdbg_fileend_bp();
+ + 		return 1;
+ + 	}
+ + 	sys_fsync(fdds);
+ + 	sys_sync();
+ + 	sys_close(fdds);
+ + 	fdds = sys_open(path, O_RDONLY, 0);
+ + 	if(fdds < 0){
+ + 		writedata = writesrc;
+ + 		ctexdbg_file_writemarker(writedata,CTEXDBG_FILE_M_LS,CTEXDBG_FILE_S_ERR_OPEN,-fdds);
+ + 		ctexdbg_fileend_bp();
+ + 		return 1;
+ + 	}
+ + 
+ + 	memset(ctexdbg_filebuf,0,CTEXDBG_WORKBUF_SIZE);
+ + 	while(1){
+ + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) 
+ + 		readbyte = sys_getdents(fdds,(struct dirent *)buff,512);
+ + #elif LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) 
+ + 		readbyte = sys_getdents(fdds,(struct linux_dirent *)buff,512);
+ + #else
+ + 		readbyte = sys_getdents64(fdds,(struct linux_dirent64 *)buff,512);
+ + #endif
+ + 		if(readbyte <= 0){
+ + 			ctexdbg_filelsfull_bp();
+ + 			break;
+ + 		}
+ + 		
+ + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) 
+ + 		for(dirp = (struct dirent*)&buff ; (char *)dirp < &buff[readbyte];
+ + 		  dirp = (struct dirent *) ( (int)dirp + (dirp->d_reclen) ) ){
+ + #else
+ + 		for(dirp = (struct linux_dirent64*)&buff ; (char *)dirp < &buff[readbyte];
+ + 		  dirp = (struct linux_dirent64 *) ( (int)dirp + (dirp->d_reclen) ) ){
+ + #endif			  
+ + 			strncpy(files,path,511); 
+ + 			strncat(files,"/",1); 
+ + 			strncat(files,dirp->d_name,511); 
+ + 		
+ + 			if(sys_newlstat(files,&fstats) == -1){
+ + 				continue;
+ + 			}
+ + 			namelen = strlen(dirp->d_name) + 1;
+ + 			ssize = namelen + 20;
+ + 			if((writedata + ssize) >= writeend){
+ + 				ctexdbg_filelsfull_bp();
+ + 				writedata = writesrc;
+ + 				memset(ctexdbg_filebuf,0,CTEXDBG_WORKBUF_SIZE);
+ + 			}
+ + 			memcpy(writedata,&ssize,sizeof(unsigned long));
+ + 			t_shorts = (unsigned short)fstats.st_mode; memcpy(writedata+4,&t_shorts,sizeof(unsigned short));
+ + 			t_shorts = (unsigned short)fstats.st_nlink; memcpy(writedata+6,&t_shorts,sizeof(unsigned short));
+ + 			t_shorts = (unsigned short)fstats.st_uid; memcpy(writedata+8,&t_shorts,sizeof(unsigned short));
+ + 			t_shorts = (unsigned short)fstats.st_gid; memcpy(writedata+10,&t_shorts,sizeof(unsigned short));
+ + 			memcpy(writedata+12,&fstats.st_size,sizeof(unsigned long));
+ + 			memcpy(writedata+16,&fstats.st_mtime,sizeof(unsigned long));
+ + 			memcpy(writedata+20,dirp->d_name,namelen);
+ + 			writedata += ssize;
+ + 		}
+ + 	}
+ + 	writedata = writesrc;
+ + 	ctexdbg_file_writemarker(writedata,CTEXDBG_FILE_M_LS,CTEXDBG_FILE_S_OK,0);
+ + 	ctexdbg_fileend_bp();	
+ + 	sys_close(fdds);
+ + 	return 0;
+ + }
+ + 
+ + /* read target fs send HOST */
+ + int ctexdbg_file_read(char *path)
+ + {
+ + 	int fdds;
+ + 	char *writesrc;	
+ + 	char *writedata;
+ + 	char *writeend;
+ + 	unsigned long stopflag = 0;
+ + 	ssize_t readfsize;
+ + 	struct stat fstats;
+ + 
+ + 	writesrc = (unsigned char*)(ctexdbg_filebuf + CTEXDBG_WORKBUF_START);		
+ + 	writedata = writesrc;
+ + 	writeend = writesrc + CTEXDBG_WORKBUF_END + 1;
+ + 	
+ + 	fdds = sys_open(path, O_RDONLY, 0);
+ + 	if(fdds < 0){
+ + 		writedata = writesrc;
+ + 		ctexdbg_file_writemarker(writedata,CTEXDBG_FILE_M_READ,CTEXDBG_FILE_S_ERR_OPEN,-fdds);
+ + 		ctexdbg_fileend_bp();
+ + 		return 1;
+ + 	}
+ + 
+ + 	sys_fsync(fdds);
+ + 	sys_sync();
+ + 	
+ + 	if(sys_newstat(path,&fstats) == -1){
+ + 		ctexdbg_file_writemarker(writedata,CTEXDBG_FILE_M_READ,CTEXDBG_FILE_S_ERR_STAT,1);
+ + 		ctexdbg_fileend_bp();
+ + 		return 1;
+ + 	}
+ + 	/* first. send file size... */
+ + 	memcpy(writedata,&(fstats.st_size),sizeof(unsigned long));	
+ + 	writedata += sizeof(unsigned long);
+ + 	
+ + 	/* send file */
+ + 	while(1){
+ + 		readfsize = sys_read(fdds,writedata,writeend - writedata);
+ + 		if(readfsize <= 0){
+ + 			break;
+ + 		}
+ + 		stopflag = ctexdbg_fileread_bp();
+ + 		if(stopflag != CTEXDBG_EV_FILE_READ){
+ + 			/* Stopped */
+ + 			break;
+ + 		}
+ + 		writedata = writesrc;
+ + 	}
+ + 	
+ + 	writedata = writesrc;
+ + 	if(readfsize < 0){
+ + 		ctexdbg_file_writemarker(writedata,CTEXDBG_FILE_M_READ,CTEXDBG_FILE_S_ERR,-readfsize);
+ + 	}else{
+ + 		ctexdbg_file_writemarker(writedata,CTEXDBG_FILE_M_READ,CTEXDBG_FILE_S_OK,0);	
+ + 	}
+ + 	/* send end */	
+ + 	ctexdbg_fileend_bp();	
+ + 
+ + 	sys_close(fdds);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /* read HOST filedata to write target fs */
+ + int ctexdbg_file_write(char *path)
+ + {
+ + 	int fdds;
+ + 	int eot;
+ + 	char *readsrc;	
+ + 	char *readdata;
+ + 	char *readend;
+ + 	unsigned long stopflag = 0;
+ + 
+ + 	ssize_t writefsize;
+ + 	ssize_t writersize;
+ + 	ssize_t wrsize;
+ + 	ssize_t wrsum;
+ + 	
+ + 	readsrc = (unsigned char*)(ctexdbg_filebuf + CTEXDBG_WORKBUF_START);	
+ + 	readdata = readsrc;
+ + 	readend = readsrc + CTEXDBG_WORKBUF_END + 1;
+ + 
+ + 	fdds = sys_open(path, O_WRONLY|O_CREAT|O_TRUNC, S_IRWXU | S_IRWXG | S_IRWXO);		
+ + 	if(fdds < 0){
+ + 		ctexdbg_file_writemarker(readdata,CTEXDBG_FILE_M_WRITE,CTEXDBG_FILE_S_ERR_OPEN,-fdds);
+ + 		ctexdbg_fileend_bp();		
+ + 		return 1;
+ + 	}
+ + 	
+ + 	/* read from HOST */
+ + 	stopflag = ctexdbg_filewrite_bp();
+ + 	if(stopflag != CTEXDBG_EV_FILE_WRITE){
+ + 		/* Stopped */
+ + 		return 1;
+ + 	}
+ + 	readdata = readsrc;	
+ + 	
+ + 	wrsum = 0; eot = 0; writefsize = 0;
+ + 	/* first. recv file size.... */
+ + 	memcpy(&writefsize,readdata,sizeof(unsigned long));	
+ + 	readdata += sizeof(unsigned long);
+ + 	/* recv file */
+ + 	while(1){
+ + 		wrsize = readend - readdata;
+ + 		if( (wrsize + wrsum) > writefsize){
+ + 			wrsize = writefsize - wrsum;
+ + 			eot = 1; 
+ + 		}
+ + 		writersize = sys_write(fdds,readdata,wrsize);
+ + 		if(writersize < 0){
+ + 			break;
+ + 		}else if(eot == 1){
+ + 			break;
+ + 		}
+ + 		wrsum += wrsize;
+ + 		/* read from HOST */
+ + 		stopflag = ctexdbg_filewrite_bp();
+ + 		if(stopflag != CTEXDBG_EV_FILE_WRITE){
+ + 			/* Stopped */
+ + 			break;
+ + 		}		
+ + 		readdata = readsrc;
+ + 	}
+ + 	
+ + 	readdata = readsrc;
+ + 	if(writersize < 0){
+ + 		ctexdbg_file_writemarker(readdata,CTEXDBG_FILE_M_WRITE,CTEXDBG_FILE_S_ERR,-writersize);
+ + 	}else{
+ + 		ctexdbg_file_writemarker(readdata,CTEXDBG_FILE_M_WRITE,CTEXDBG_FILE_S_OK,0);	
+ + 	}
+ + 
+ + 	sys_fsync(fdds);
+ + 	sys_close(fdds);
+ + 	sys_sync();
+ + 	ctexdbg_temp_sync(path);
+ + 
+ + 	/* send end */	
+ + 	ctexdbg_fileend_bp();	
+ + 
+ + 	return 0;
+ + }
+ + 
+ + int ctexdbg_file_rmdir(char *path)
+ + {
+ + 	char *writesrc;
+ + 	char *writedata;
+ + 	int ret;
+ + 	
+ + 	writesrc = (unsigned char*)(ctexdbg_filebuf + CTEXDBG_WORKBUF_START);	
+ + 	writedata = writesrc;
+ + 	if((ret = sys_rmdir(path)) < 0){
+ + 		ctexdbg_file_writemarker(writedata,CTEXDBG_FILE_M_RMDIR,CTEXDBG_FILE_S_ERR,-ret);
+ + 	}else{
+ + 		ctexdbg_file_writemarker(writedata,CTEXDBG_FILE_M_RMDIR,CTEXDBG_FILE_S_OK,0);
+ + 	}
+ + 
+ + 	sys_sync();
+ + 
+ + 	ctexdbg_fileend_bp();	
+ + 	return 0;
+ + }
+ + 
+ + int ctexdbg_file_mkdir(char *path)
+ + {
+ + 	char *writesrc;
+ + 	char *writedata;
+ + 	int ret;
+ + 
+ + 	writesrc = (unsigned char*)(ctexdbg_filebuf + CTEXDBG_WORKBUF_START);	
+ + 	writedata = writesrc;	
+ + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) 
+ + 	if((ret = sys_mkdir(path)) < 0){
+ + #else
+ + 	if((ret = sys_mkdir(path,0777)) < 0){
+ + #endif	
+ + 		ctexdbg_file_writemarker(writedata,CTEXDBG_FILE_M_MKDIR,CTEXDBG_FILE_S_ERR,-ret);
+ + 	}else{
+ + 		ctexdbg_file_writemarker(writedata,CTEXDBG_FILE_M_MKDIR,CTEXDBG_FILE_S_OK,0);
+ + 	}
+ + 	sys_sync();
+ + 	ctexdbg_temp_sync(path);
+ + 	ctexdbg_fileend_bp();	
+ + 	sys_sync();
+ + 
+ + 	return 0;
+ + }
+ + 
+ + int ctexdbg_file_rename(char *path)
+ + {
+ + 	char *writesrc;
+ + 	char *writedata;
+ + 	int ret;
+ + 
+ + 	/* new path follows the old path in the pointer */
+ + 	/* get a pointer to the new name */
+ + 	char *new_name = path + strlen(path) + 1;
+ + 
+ + 	writesrc = (unsigned char*)(ctexdbg_filebuf + CTEXDBG_WORKBUF_START);	
+ + 	writedata = writesrc;
+ + 	if((ret = sys_rename(path,new_name)) < 0){
+ + 		ctexdbg_file_writemarker(writedata,CTEXDBG_FILE_M_MKDIR,CTEXDBG_FILE_S_ERR,-ret);
+ + 	}else{
+ + 		ctexdbg_file_writemarker(writedata,CTEXDBG_FILE_M_MKDIR,CTEXDBG_FILE_S_OK,0);
+ + 	}
+ + 	sys_sync();
+ + 
+ + 	ctexdbg_fileend_bp();	
+ + 	return 0;
+ + }
+ + 
+ + int ctexdbg_file_chmod(char *path)
+ + {
+ + 	char *writesrc;
+ + 	char *writedata;
+ + 	char *filepath;
+ + 	int ret;
+ + 
+ + 	/* copy attribute */
+ + 	mode_t attr;
+ + 	memcpy(&attr,path,4);
+ + 	
+ + 	/* get a pointer to the filename */
+ + 	filepath = path + 4;
+ + 		
+ + 	writesrc = (unsigned char*)(ctexdbg_filebuf + CTEXDBG_WORKBUF_START);	
+ + 	writedata = writesrc;	
+ + 	if((ret = sys_chmod(filepath,attr)) < 0){
+ + 		ctexdbg_file_writemarker(writedata,CTEXDBG_FILE_M_MKDIR,CTEXDBG_FILE_S_ERR,-ret);
+ + 	}else{
+ + 		ctexdbg_file_writemarker(writedata,CTEXDBG_FILE_M_MKDIR,CTEXDBG_FILE_S_OK,0);
+ + 	}
+ + 	sys_sync();
+ + 
+ + 	ctexdbg_fileend_bp();	
+ + 	return 0;
+ + }
+ + 
+ + int ctexdbg_file_chown(char *path)
+ + {
+ + 	char *writesrc;
+ + 	char *writedata;
+ + 	char *filepath;
+ + 	int ret;
+ + 	uid_t grp_id;
+ + 	
+ + 	/* copy owner ID */
+ + 	uid_t own_id;
+ + 	memcpy(&own_id,path,4);
+ + 	
+ + 	/* copy group ID */
+ + 	/* copy owner ID */
+ + 	memcpy(&grp_id,path+4,4);
+ + 	
+ + 	/* get a pointer to the filename */
+ + 	filepath = path + 8;
+ + 
+ + 	writesrc = (unsigned char*)(ctexdbg_filebuf + CTEXDBG_WORKBUF_START);	
+ + 	writedata = writesrc;			
+ + 	if((ret = sys_chown(filepath, own_id, grp_id)) < 0){
+ + 		ctexdbg_file_writemarker(writedata,CTEXDBG_FILE_M_MKDIR,CTEXDBG_FILE_S_ERR,-ret);
+ + 	}else{
+ + 		ctexdbg_file_writemarker(writedata,CTEXDBG_FILE_M_MKDIR,CTEXDBG_FILE_S_OK,0);
+ + 	}
+ + 	sys_sync();
+ + 
+ + 	ctexdbg_fileend_bp();	
+ + 	return 0;
+ + }
+ + 
+ + int ctexdbg_file_delfile(char *path)
+ + {
+ + 	char *writesrc;
+ + 	char *writedata;
+ + 	int ret;
+ + 	
+ + 	writesrc = (unsigned char*)(ctexdbg_filebuf + CTEXDBG_WORKBUF_START);	
+ + 	writedata = writesrc;
+ + 	if((ret = sys_unlink(path)) < 0){
+ + 		ctexdbg_file_writemarker(writedata,CTEXDBG_FILE_M_DELFILE,CTEXDBG_FILE_S_ERR,-ret);
+ + 	}else{
+ + 		ctexdbg_file_writemarker(writedata,CTEXDBG_FILE_M_DELFILE,CTEXDBG_FILE_S_OK,0);
+ + 	}	
+ + 	sys_sync();
+ + 
+ + 	ctexdbg_fileend_bp();
+ + 	return 0;
+ + }
+ + 
+ diff -crN linux-3.2.1_o/kernel/ctextrc.c linux-3.2.1/kernel/ctextrc.c
+ *** linux-3.2.1_o/kernel/ctextrc.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/kernel/ctextrc.c	2014-11-14 21:03:15.658351676 +0900
+ ***************
+ *** 0 ****
+ --- 1,444 ----
+ + /*
+ +  * linux/kernel/ctextrc.c
+ +  *
+ +  * (C) Copyright 2004 - Computex co.,ltd.
+ +  *
+ +  * Linux trace toolkit support
+ +  *
+ +  * -- version info --------------------------------------------------
+ +  * 
+ +  * version 0013- 2008/05/xx		reborn
+ +  *
+ +  * -------------------------------------------------------------------
+ +  *
+ +  */
+ + 
+ +  /* Necessary includes */
+ + #include <linux/kernel.h>
+ + #include <linux/version.h>
+ + 
+ + #include <linux/fs.h>
+ + #include <linux/sched.h>
+ + #include <linux/slab.h>
+ + #include <linux/ctype.h>
+ + #include <linux/pagemap.h>
+ + #include <linux/string.h>
+ + #include <linux/time.h>
+ + #include <linux/vmalloc.h>
+ + #include <linux/mm.h>
+ + 
+ + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) 
+ + #include <linux/wrapper.h>
+ + #else
+ + #include <linux/namei.h>
+ + #endif
+ + 
+ + #include <linux/vmalloc.h>
+ + #include <linux/interrupt.h>
+ + #ifdef CONFIG_ARM
+ + #include <asm/irq.h>
+ + #include <asm/mach/irq.h>
+ + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) 
+ + #include <asm/arch/irq.h>
+ + #endif
+ + #else
+ + #include <linux/irq.h>
+ + #endif
+ + 
+ + #include <linux/ctexdbg.h>  /* definitions */
+ + 
+ + #include <asm/io.h>
+ + #include <asm/current.h>
+ + #include <asm/uaccess.h>
+ + #include <asm/bitops.h>
+ + 
+ + #include <linux/ctextrc.h>
+ + 
+ + #define CTEXTRC_DEFAULT_BUF_SIZE 50000				/* buffer size*/
+ + 
+ + extern cdbtrc_bufpos	ctexdbg_tracebufpos;		/* buffer position */
+ + 
+ + static spinlock_t             sSpinLock;             /* Spinlock in order to lock kernel */
+ + static uint32_t               sBufSize;              /* Buffer sizes */
+ + static uint32_t               sAllocSize;            /* Size of buffers allocated */
+ + 
+ + uint32_t		ctexdbg_TracerSize = CTEXTRC_DEFAULT_BUF_SIZE;	/* trace buffer size */
+ + int			ctexdbg_traceend = 0; 							/* TRACE end flag */
+ + int			ctexdbg_tracestop = 1;	 						/* buffer full stop enable */
+ + 												/* 0 : stop    (default) */
+ + 												/* 1 : nonstop (one shot) */
+ + //#ifndef CONFIG_ARM
+ + #define CTEXDBG_TRACER_BUFSTATIC
+ + //#endif /* NOTARM */
+ + 
+ + #ifdef CTEXDBG_TRACER_BUFSTATIC
+ + static char ctexdbg_sTraceBuffer[CTEXTRC_DEFAULT_BUF_SIZE+2];
+ + #endif /* CTEXDBG_TRACER_BUFSTATIC */
+ + 
+ + /* Size of statically defined events */
+ + static int sEventStructSize[CTX_EV_MAX + 1] =
+ + {
+ + 	0,
+ + 	sizeof(ctx_syscall_entry),
+ + 	0,				/* SYSCALL_EXIT */
+ + 	sizeof(ctx_trap_entry),
+ + 	0,				/* TRAP_EXIT */
+ + 	sizeof(ctx_irq_entry),
+ + 	0,				/* IRQ_EXIT */
+ + 	sizeof(ctx_schedchange),
+ + 	0,				/* KERNEL_TIMER */
+ + 	sizeof(ctx_soft_irq),
+ + 	sizeof(ctx_process),
+ + 	sizeof(ctx_file_system),
+ + 	sizeof(ctx_timer),
+ + 	sizeof(ctx_memory),
+ + 	sizeof(ctx_socket),
+ + 	sizeof(ctx_ipc),
+ + 	sizeof(ctx_network),
+ + 	0,
+ +  	0
+ + };
+ + 
+ + typedef struct _tag_cdbtrc_mask_type
+ + {
+ + 	uint32_t event_num;				/* mask event ID : 0 = end */
+ + 	uint32_t event_denyall;			/* 0 :subevent not 1:subevent use */
+ + 	uint32_t subevent_num;			/* syscallnum or mask*/
+ + }cdbtrc_mask_type;
+ + 
+ + cdbtrc_mask_type cdbtrc_mask_table[CTEXTRC_MASK_SIZE];
+ + 
+ + 
+ + 
+ + /* ------------------------ memry allocate --------------------------------------------- */
+ + 
+ + #ifndef FIX_SIZE
+ + #define FIX_SIZE(x) (((x) - 1) & PAGE_MASK) + PAGE_SIZE /* This inspired by rtai/shmem */
+ + #endif
+ + 
+ + #define BKK(x) ((x) << PAGE_SHIFT)
+ + 
+ + static void ctexdbg_tracer_cleanbuf(void)
+ + {
+ + 	memset(ctexdbg_tracebufpos.sEventBuf,CTX_EV_BUFFER_END,sBufSize);
+ + }
+ + 
+ + int ctexdbg_tracer_set_buffer_size(int pmSize)
+ + {
+ + #ifdef CTEXDBG_TRACER_BUFSTATIC
+ +   /* clean */
+ +   
+ +   ctexdbg_tracebufpos.sEventBuf = NULL;
+ +   ctexdbg_tracebufpos.sEventWritPos = NULL;
+ +   ctexdbg_tracebufpos.sEventReadPos = NULL;
+ +   ctexdbg_tracebufpos.sEventWritLimit = NULL;
+ +   ctexdbg_tracebufpos.sEventBufDir = 0;
+ +   
+ +   ctexdbg_tracebufpos.sEventBuf = ctexdbg_sTraceBuffer;
+ +  
+ +   sBufSize = CTEXTRC_DEFAULT_BUF_SIZE;
+ +   sAllocSize = CTEXTRC_DEFAULT_BUF_SIZE;
+ + 
+ + #else /* CTEXDBG_TRACER_BUFSTATIC */
+ +   int	lSizeAlloc;     /* Size to be allocated */
+ +   int	lSizeMax;	/* Max alloc size */
+ +   struct sysinfo i;	/* memory size */
+ + 
+ +   /* Set size to allocate (= pmSize) and fix it's size to be on a page boundary */
+ +   lSizeAlloc = FIX_SIZE(pmSize);
+ + 
+ +   /* Free the current buffers, if any */
+ +   if(ctexdbg_tracebufpos.sEventBuf != NULL)
+ +     kfree(ctexdbg_tracebufpos.sEventBuf);
+ + 
+ +   /* clean */
+ +   ctexdbg_tracebufpos.sEventBuf = NULL;
+ +   ctexdbg_tracebufpos.sEventWritPos = NULL;
+ +   ctexdbg_tracebufpos.sEventReadPos = NULL;
+ +   ctexdbg_tracebufpos.sEventWritLimit = NULL;
+ +   ctexdbg_tracebufpos.sEventBufDir = 0;
+ + 			
+ +   /* calclation sizeing...*/
+ +   si_meminfo(&i);
+ +   lSizeMax = BKK(i.freeram) - 100000;
+ +   if(lSizeAlloc >= lSizeMax){
+ +   	/* Over memory ... return ERROR */
+ +     return 1;
+ +   }
+ + 
+ +   /* Allocate space for the tracing buffers */
+ +   if((ctexdbg_tracebufpos.sEventBuf = (char*) kmalloc(lSizeAlloc,GFP_KERNEL|__GFP_NORETRY)) == NULL){
+ +     ctexdbg_tracebufpos.sEventBuf = NULL;	  
+ +     return 1;
+ +   }
+ + 	
+ +   /* Remember the size set */
+ +   sBufSize = pmSize;
+ +   sAllocSize = lSizeAlloc;
+ + 
+ + #endif /* CTEXDBG_TRACER_BUFSTATIC */ 
+ + 
+ +   /* Set the read and write buffers */
+ +   ctexdbg_tracebufpos.sEventWritPos = ctexdbg_tracebufpos.sEventBuf;
+ +    
+ +   /* Set write limit */
+ +   ctexdbg_tracebufpos.sEventWritLimit = ctexdbg_tracebufpos.sEventWritPos + sBufSize;
+ + 
+ +   /* Set write position */
+ +   ctexdbg_tracebufpos.sEventReadPos = ctexdbg_tracebufpos.sEventBuf;
+ +   
+ +   /* All is OK */
+ +   return 0;
+ + }
+ + 
+ + 
+ + #define write_to_buffer(DEST, SRC, SIZE) \
+ + do{ \
+ + 	memcpy(DEST, SRC, SIZE); \
+ + 	DEST += SIZE; \
+ + } while(0);
+ + 
+ + int ctexdbg_tracer_start(uint32_t nbuffersize,uint32_t oneshot)
+ + {
+ + 	unsigned long int   lFlags;                   /* CPU flags for lock */
+ + 	
+ + 	if(ctexdbg_traceuse == 1) return 0;
+ + 	
+ + 	/* Lock the kernel */
+ + 	spin_lock_irqsave(&sSpinLock, lFlags);
+ + 	
+ + 	ctexdbg_tracestop = oneshot;
+ + 
+ + #ifdef CTEXDBG_TRACER_BUFSTATIC
+ + 	nbuffersize = CTEXTRC_DEFAULT_BUF_SIZE;
+ + #endif /* CTEXDBG_TRACER_BUFSTATIC */
+ + 
+ + 	if(ctexdbg_tracebufpos.sEventBuf == NULL){
+ + 		ctexdbg_TracerSize = nbuffersize;	
+ + 		if(ctexdbg_tracer_set_buffer_size(ctexdbg_TracerSize) != 0){
+ + 			ctexdbg_traceend = 1;
+ + 			ctexdbg_traceuse = 0;
+ + 			spin_unlock_irqrestore(&sSpinLock, lFlags);
+ + 			return 1;
+ + 		}
+ + 	}else if(ctexdbg_TracerSize != nbuffersize){
+ + 		ctexdbg_TracerSize = nbuffersize;
+ + 		if(ctexdbg_tracer_set_buffer_size(ctexdbg_TracerSize) != 0){
+ + 			ctexdbg_traceend = 1;
+ + 			ctexdbg_traceuse = 0;
+ + 			spin_unlock_irqrestore(&sSpinLock, lFlags);
+ + 			return 1;
+ + 		}
+ + 	}else{
+ + 		ctexdbg_tracebufpos.sEventWritPos = ctexdbg_tracebufpos.sEventBuf;	
+ + 		ctexdbg_tracebufpos.sEventReadPos = ctexdbg_tracebufpos.sEventBuf;
+ + 		ctexdbg_tracebufpos.sEventBufDir = 0;
+ + 	}
+ + 	/* clean buf */
+ + 	ctexdbg_tracer_cleanbuf();
+ + 	/* enable something events ... */
+ + 	spin_unlock_irqrestore(&sSpinLock, lFlags);
+ + 	
+ + 	/* We can start tracing */
+ + 	ctexdbg_traceuse = 1;
+ + 	ctexdbg_traceend = 0;	
+ + 	return 0;
+ + }
+ + 
+ + 
+ + void ctexdbg_tracer_stop(void)
+ + {
+ + 	if(ctexdbg_traceuse == 0) return;
+ + 	ctexdbg_traceend = 1;
+ + 	ctexdbg_traceuse = 0;
+ + }
+ + 
+ + static void ctexdbg_trace_switch_buffers(void)
+ + {
+ + 	if(ctexdbg_tracestop == 0){
+ + 		/* stop */
+ + 		ctexdbg_lttfull_bp();
+ + 		ctexdbg_tracebufpos.sEventBufDir = 0;
+ + 		ctexdbg_tracebufpos.sEventReadPos = ctexdbg_tracebufpos.sEventBuf;
+ + 		ctexdbg_tracebufpos.sEventWritPos = ctexdbg_tracebufpos.sEventBuf;
+ + 		return;
+ + 	}
+ + 	
+ + 	/* this no stop mode set dir 1 */
+ + 	if(ctexdbg_tracebufpos.sEventBufDir == 0){
+ + 		ctexdbg_tracebufpos.sEventBufDir = 1;
+ + 	}
+ + 	
+ + 	memset(ctexdbg_tracebufpos.sEventWritPos,0xFF,
+ + 			ctexdbg_tracebufpos.sEventWritLimit - ctexdbg_tracebufpos.sEventWritPos);		
+ + 	
+ + 	ctexdbg_tracebufpos.sEventWritPos = ctexdbg_tracebufpos.sEventBuf;	
+ + 	return;
+ + }
+ + 
+ + /* Check event mask (v006 later)*/
+ + int ctexdbg_tracer_hitmask(uint8_t pmEventID,void* pmEventStruct)
+ + {
+ + 	int i;
+ + 	int ret = 0;
+ + 	
+ + 	for(i=0;i < CTEXTRC_MASK_SIZE;i++){
+ + 		if(cdbtrc_mask_table[i].event_num == 0) break;
+ + 		if(cdbtrc_mask_table[i].event_num != pmEventID) continue;
+ + 		
+ + 		if(cdbtrc_mask_table[i].event_denyall == 0){
+ + 			/* subevent not use ... HIT mask! */
+ + 			return 1;
+ + 		}
+ + 		switch(pmEventID){
+ + 		case CTX_EV_SYSCALL_ENTRY:
+ + 			if(cdbtrc_mask_table[i].subevent_num == ((ctx_syscall_entry*) pmEventStruct)->syscall_id){
+ + 				return 1;
+ + 			}
+ + 			break;
+ + 		case CTX_EV_TRAP_ENTRY:
+ + 			if(cdbtrc_mask_table[i].subevent_num == ((ctx_trap_entry*) pmEventStruct)->trap_id){
+ + 				return 1;
+ + 			}
+ + 			break;
+ + 		case CTX_EV_IRQ_ENTRY:
+ + 			if(cdbtrc_mask_table[i].subevent_num == ((ctx_irq_entry*) pmEventStruct)->irq_id){
+ + 				return 1;
+ + 			}
+ + 			break;
+ + 		case CTX_EV_SOFT_IRQ: 
+ + 			if(cdbtrc_mask_table[i].subevent_num == ((ctx_soft_irq*) pmEventStruct)->event_sub_id){
+ + 				return 1;
+ + 			}
+ + 			break;
+ + 		case CTX_EV_PROCESS: 
+ + 			if(cdbtrc_mask_table[i].subevent_num == ((ctx_process*) pmEventStruct)->event_sub_id){
+ + 				return 1;
+ + 			}
+ + 			break;
+ + 		case CTX_EV_FILE_SYSTEM: 
+ + 			if(cdbtrc_mask_table[i].subevent_num == ((ctx_file_system*) pmEventStruct)->event_sub_id){
+ + 				return 1;
+ + 			}
+ + 			break;
+ + 		case CTX_EV_TIMER: 
+ + 			if(cdbtrc_mask_table[i].subevent_num == ((ctx_timer*) pmEventStruct)->event_sub_id){
+ + 				return 1;
+ + 			}
+ + 			break;
+ + 		case CTX_EV_MEMORY: 
+ + 			if(cdbtrc_mask_table[i].subevent_num == ((ctx_memory*) pmEventStruct)->event_sub_id){
+ + 				return 1;
+ + 			}
+ + 			break;
+ + 		case CTX_EV_SOCKET: 
+ + 			if(cdbtrc_mask_table[i].subevent_num == ((ctx_socket*) pmEventStruct)->event_sub_id){
+ + 				return 1;
+ + 			}
+ + 			break;
+ + 		case CTX_EV_IPC: 
+ + 			if(cdbtrc_mask_table[i].subevent_num == ((ctx_ipc*) pmEventStruct)->event_sub_id){
+ + 				return 1;
+ + 			}
+ + 			break;
+ + 		case CTX_EV_NETWORK: 
+ + 			if(cdbtrc_mask_table[i].subevent_num == ((ctx_network*) pmEventStruct)->event_sub_id){
+ + 				return 1;
+ + 			}
+ + 			break;
+ + 		}
+ + 	}
+ + 
+ + 	return ret;
+ + }
+ + 
+ + 
+ + 
+ + /* ------------------------------ tracer ------------------------------------------ */
+ + void ctexdbg_tracer(uint8_t pmEventID,void* pmEventStruct)
+ + {
+ + 	int                 lVarDataLen = 0;          /* Length of variable length data to be copied, if any */
+ + 	void*               lVarDataBeg = NULL;       /* Begining of variable length data to be copied */
+ + 	uint16_t            lCPUID;                   /* CPUID of currently runing process */
+ + 	uint16_t            lDataSize;                /* Size of tracing data */
+ + 	struct timeval      lTime;                    /* Event time */
+ + 	unsigned long int   lFlags;                   /* CPU flags for lock */
+ + 	char*               lWritPos;
+ + 	
+ + 	if(ctexdbg_traceuse == 0) return;
+ + 	
+ + 	switch(pmEventID){
+ + 	case CTX_EV_START:
+ + 	case CTX_EV_BUFFER_START:
+ + 	case CTX_EV_BUFFER_END:
+ + 		return;
+ + 		break;
+ + 	}
+ + 	
+ + 	/* check mask */
+ + 	if(ctexdbg_tracer_hitmask(pmEventID, pmEventStruct) != 0){
+ + 		return;
+ + 	}
+ + 
+ + 	/* Compute size of tracing data */
+ + 	lDataSize = sizeof(pmEventID) + sizeof(lCPUID) + sizeof(lTime) + sEventStructSize[pmEventID] +sizeof(lDataSize);
+ + 	
+ + 	/* Some events have variable length */
+ + 	if(pmEventID == CTX_EV_FILE_SYSTEM){
+ + 	/* Is there a file name in this */
+ + 		if((((ctx_file_system*) pmEventStruct)->event_sub_id == CTX_EV_FILE_SYSTEM_EXEC)
+ + 		|| (((ctx_file_system*) pmEventStruct)->event_sub_id == CTX_EV_FILE_SYSTEM_OPEN)){
+ + 			/* Remember the string's begining and update size variables */
+ + 			lVarDataBeg = ((ctx_file_system*) pmEventStruct)->file_name;
+ + 			lVarDataLen = ((ctx_file_system*) pmEventStruct)->event_data2 + 1;
+ + 			lDataSize += (uint16_t) lVarDataLen;
+ + 		}
+ + 	}
+ + 	lCPUID = smp_processor_id();
+ + 	/* Get the time of the event */
+ + 	do_gettimeofday(&lTime);
+ + 
+ + 	/* The following time calculations have to be done within the spinlock because
+ + 		otherwise the event order could be inverted. */
+ + 	
+ + 	/* Lock the kernel */
+ + 	spin_lock_irqsave(&sSpinLock, lFlags);
+ + 	
+ + 	/* Is there enough space left in the write buffer */
+ + 	if( (ctexdbg_tracebufpos.sEventWritPos + lDataSize) >= ctexdbg_tracebufpos.sEventWritLimit){
+ + 		/* Switch buffers */
+ + 		ctexdbg_trace_switch_buffers();
+ + 	}
+ + 
+ + 	lWritPos = ctexdbg_tracebufpos.sEventWritPos;
+ + 	/* Write event type to tracing buffer */
+ + 	write_to_buffer(lWritPos,&pmEventID,sizeof(pmEventID));
+ + 
+ + 	/* Write the CPUID */
+ + 	write_to_buffer(lWritPos,&lCPUID,sizeof(lCPUID));
+ + 		
+ + 	/* Write event time to tracing buffer */
+ + 	write_to_buffer(lWritPos,&lTime,sizeof(lTime));
+ + 
+ + 	/* Write event structure */
+ + 	write_to_buffer(lWritPos,pmEventStruct,sEventStructSize[pmEventID]);
+ + 		
+ + 	/* Write string if any */
+ + 	if(lVarDataBeg != NULL){
+ + 		write_to_buffer(lWritPos,lVarDataBeg,lVarDataLen);
+ + 	}
+ + 			
+ + 	/* Write the length of the event description */
+ + 	write_to_buffer(lWritPos,&lDataSize,sizeof(lDataSize));
+ + 
+ + 	ctexdbg_tracebufpos.sEventWritPos = lWritPos;
+ + 	
+ + 	spin_unlock_irqrestore(&sSpinLock, lFlags);
+ + }
+ + 
+ + 
+ + void ctexdbg_tracer_init(void)
+ + {
+ + 	spin_lock_init(& sSpinLock);	
+ + 	memset(cdbtrc_mask_table,0,sizeof(cdbtrc_mask_table));
+ + }
+ diff -crN linux-3.2.1_o/kernel/exit.c linux-3.2.1/kernel/exit.c
+ *** linux-3.2.1_o/kernel/exit.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/kernel/exit.c	2014-11-14 21:05:16.454350520 +0900
+ ***************
+ *** 51,56 ****
+ --- 51,57 ----
+   #include <trace/events/sched.h>
+   #include <linux/hw_breakpoint.h>
+   #include <linux/oom.h>
+ + #include <linux/ctexdbg.h>
+   
+   #include <asm/uaccess.h>
+   #include <asm/unistd.h>
+ ***************
+ *** 971,982 ****
+ --- 972,988 ----
+   	tsk->exit_code = code;
+   	taskstats_exit(tsk, group_dead);
+   
+ + #if defined(CONFIG_CTEX_DBGLIB)		
+ + 	ctexdbg_process_exit();
+ + #endif	
+   	exit_mm(tsk);
+   
+   	if (group_dead)
+   		acct_process();
+   	trace_sched_process_exit(tsk);
+   
+ + 	ctx_ev_process_exit();
+ + 	
+   	exit_sem(tsk);
+   	exit_shm(tsk);
+   	exit_files(tsk);
+ ***************
+ *** 1689,1695 ****
+   	int retval;
+   
+   	trace_sched_process_wait(wo->wo_pid);
+ ! 
+   	init_waitqueue_func_entry(&wo->child_wait, child_wait_callback);
+   	wo->child_wait.private = current;
+   	add_wait_queue(&current->signal->wait_chldexit, &wo->child_wait);
+ --- 1695,1703 ----
+   	int retval;
+   
+   	trace_sched_process_wait(wo->wo_pid);
+ ! 	
+ ! 	ctx_ev_process(CTX_EV_PROCESS_WAIT, pid_nr(wo->wo_pid), 0);
+ ! 	
+   	init_waitqueue_func_entry(&wo->child_wait, child_wait_callback);
+   	wo->child_wait.private = current;
+   	add_wait_queue(&current->signal->wait_chldexit, &wo->child_wait);
+ diff -crN linux-3.2.1_o/kernel/fork.c linux-3.2.1/kernel/fork.c
+ *** linux-3.2.1_o/kernel/fork.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/kernel/fork.c	2014-11-14 21:04:15.922351100 +0900
+ ***************
+ *** 66,71 ****
+ --- 66,72 ----
+   #include <linux/user-return-notifier.h>
+   #include <linux/oom.h>
+   #include <linux/khugepaged.h>
+ + #include <linux/ctexdbg.h>
+   
+   #include <asm/pgtable.h>
+   #include <asm/pgalloc.h>
+ ***************
+ *** 1512,1517 ****
+ --- 1513,1519 ----
+   		struct completion vfork;
+   
+   		trace_sched_process_fork(current, p);
+ + 		ctx_ev_process(CTX_EV_PROCESS_FORK,p->pid,0);
+   
+   		nr = task_pid_vnr(p);
+   
+ ***************
+ *** 1533,1538 ****
+ --- 1535,1544 ----
+   		 */
+   		p->flags &= ~PF_STARTING;
+   
+ + #ifdef CONFIG_CTEX_DBGLIB
+ + 		ctexdbg_forking(p,clone_flags,stack_start);
+ + #endif /* CONFIG_CTEX_DBGLIB */
+ + 
+   		wake_up_new_task(p);
+   
+   		/* forking complete and child started to run, tell ptracer */
+ diff -crN linux-3.2.1_o/kernel/itimer.c linux-3.2.1/kernel/itimer.c
+ *** linux-3.2.1_o/kernel/itimer.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/kernel/itimer.c	2014-11-14 21:03:15.662351676 +0900
+ ***************
+ *** 13,18 ****
+ --- 13,19 ----
+   #include <linux/posix-timers.h>
+   #include <linux/hrtimer.h>
+   #include <trace/events/timer.h>
+ + #include <linux/ctexdbg.h>
+   
+   #include <asm/uaccess.h>
+   
+ ***************
+ *** 123,128 ****
+ --- 124,130 ----
+   	struct signal_struct *sig =
+   		container_of(timer, struct signal_struct, real_timer);
+   
+ + 	ctx_ev_timer(CTX_EV_TIMER_EXPIRED,0,0,0);
+   	trace_itimer_expire(ITIMER_REAL, sig->leader_pid, 0);
+   	kill_pid_info(SIGALRM, SEND_SIG_PRIV, sig->leader_pid);
+   
+ ***************
+ *** 200,206 ****
+   	if (!timeval_valid(&value->it_value) ||
+   	    !timeval_valid(&value->it_interval))
+   		return -EINVAL;
+ ! 
+   	switch (which) {
+   	case ITIMER_REAL:
+   again:
+ --- 202,208 ----
+   	if (!timeval_valid(&value->it_value) ||
+   	    !timeval_valid(&value->it_interval))
+   		return -EINVAL;
+ ! 	ctx_ev_timer(CTX_EV_TIMER_SETITIMER,which,(ulong)&value->it_interval,(ulong)&value->it_value);
+   	switch (which) {
+   	case ITIMER_REAL:
+   again:
+ diff -crN linux-3.2.1_o/kernel/module.c linux-3.2.1/kernel/module.c
+ *** linux-3.2.1_o/kernel/module.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/kernel/module.c	2014-11-14 21:03:15.662351676 +0900
+ ***************
+ *** 58,63 ****
+ --- 58,64 ----
+   #include <linux/jump_label.h>
+   #include <linux/pfn.h>
+   #include <linux/bsearch.h>
+ + #include <linux/ctexdbg.h>
+   
+   #define CREATE_TRACE_POINTS
+   #include <trace/events/module.h>
+ ***************
+ *** 661,666 ****
+ --- 662,670 ----
+   	struct module_use *use, *tmp;
+   
+   	mutex_lock(&module_mutex);
+ + #ifdef CONFIG_CTEX_DBGLIB
+ + 	ctexdbg_module_remove(mod);
+ + #endif		
+   	list_for_each_entry_safe(use, tmp, &mod->target_list, target_list) {
+   		struct module *i = use->target;
+   		DEBUGP("%s unusing %s\n", mod->name, i->name);
+ ***************
+ *** 2797,2802 ****
+ --- 2801,2809 ----
+   	/* Setup kallsyms-specific fields. */
+   	add_kallsyms(mod, info);
+   
+ + #ifdef CONFIG_CTEX_DBGLIB
+ + 	ctexdbg_module_install(mod, info->hdr, info->sechdrs, info->secstrings, info->index.sym, info->index.str);
+ + #endif	
+   	/* Arch-specific module finalizing. */
+   	return module_finalize(info->hdr, info->sechdrs, mod);
+   }
+ ***************
+ *** 2980,2986 ****
+ --- 2987,3000 ----
+   	do_mod_ctors(mod);
+   	/* Start the module */
+   	if (mod->init != NULL)
+ + #ifdef CONFIG_CTEX_DBGLIB
+ + 	{
+ + 		ctexdbg_module_init(mod);
+   		ret = do_one_initcall(mod->init);
+ + 	}
+ + #else
+ + 		ret = do_one_initcall(mod->init);
+ + #endif /* CONFIG_CTEX_DBGLIB */		
+   	if (ret < 0) {
+   		/* Init routine failed: abort.  Try to protect us from
+                      buggy refcounters. */
+ diff -crN linux-3.2.1_o/kernel/sched.c linux-3.2.1/kernel/sched.c
+ *** linux-3.2.1_o/kernel/sched.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/kernel/sched.c	2014-11-14 21:22:22.310340704 +0900
+ ***************
+ *** 72,77 ****
+ --- 72,79 ----
+   #include <linux/ftrace.h>
+   #include <linux/slab.h>
+   #include <linux/init_task.h>
+ + #include <linux/ctexdbg.h>
+ + #include <asm/ctexdbg_arch.h>
+   
+   #include <asm/tlb.h>
+   #include <asm/irq_regs.h>
+ ***************
+ *** 2456,2461 ****
+ --- 2458,2466 ----
+   		 */
+   		rq = task_rq_lock(p, &flags);
+   		trace_sched_wait_task(p);
+ + #ifdef CONFIG_CTEX_DBGLIB
+ + 		ctx_ev_process(CTX_EV_PROCESS_WAIT, p->pid, 0);
+ + #endif
+   		running = task_running(rq, p);
+   		on_rq = p->on_rq;
+   		ncsw = 0;
+ ***************
+ *** 2659,2664 ****
+ --- 2664,2673 ----
+   	trace_sched_wakeup(p, true);
+   	check_preempt_curr(rq, p, wake_flags);
+   
+ + #ifdef CONFIG_CTEX_DBGLIB
+ + 	ctx_ev_process(CTX_EV_PROCESS_WAKEUP, p->pid, p->state);
+ + #endif
+ + 	
+   	p->state = TASK_RUNNING;
+   #ifdef CONFIG_SMP
+   	if (p->sched_class->task_woken)
+ ***************
+ *** 3291,3296 ****
+ --- 3300,3309 ----
+   
+   	prepare_task_switch(rq, prev, next);
+   
+ + #ifdef CONFIG_CTEX_DBGLIB
+ + 	ctx_ev_schedchange(prev->pid,next->pid,prev->state);
+ + #endif
+ + 
+   	mm = next->mm;
+   	oldmm = prev->active_mm;
+   	/*
+ ***************
+ *** 3321,3326 ****
+ --- 3334,3343 ----
+   	spin_release(&rq->lock.dep_map, 1, _THIS_IP_);
+   #endif
+   
+ + #ifdef CONFIG_CTEX_DBGLIB
+ + 	ctexdbg_arch_schedchange_event(prev->pid,next->pid, next->comm);
+ + #endif /* CONFIG_CTEX_DBGLIB */	
+ + 
+   	/* Here we just switch the register state and the stack. */
+   	switch_to(prev, next, prev);
+   
+ ***************
+ *** 6273,6278 ****
+ --- 6290,6299 ----
+   	if (!cpumask_test_cpu(dest_cpu, tsk_cpus_allowed(p)))
+   		goto fail;
+   
+ + #ifdef CONFIG_CTEX_DBGLIB
+ + 	ctexdbg_migration_check(p,src_cpu,dest_cpu);
+ + #endif /* CONFIG_CTEX_DBGLIB */		
+ + 
+   	/*
+   	 * If we're not on a rq, the next wake-up will ensure we're
+   	 * placed properly.
+ diff -crN linux-3.2.1_o/kernel/signal.c linux-3.2.1/kernel/signal.c
+ *** linux-3.2.1_o/kernel/signal.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/kernel/signal.c	2014-11-14 21:04:48.158350791 +0900
+ ***************
+ *** 28,33 ****
+ --- 28,34 ----
+   #include <linux/freezer.h>
+   #include <linux/pid_namespace.h>
+   #include <linux/nsproxy.h>
+ + #include <linux/ctexdbg.h>
+   #define CREATE_TRACE_POINTS
+   #include <trace/events/signal.h>
+   
+ ***************
+ *** 1168,1173 ****
+ --- 1169,1175 ----
+   static int
+   specific_send_sig_info(int sig, struct siginfo *info, struct task_struct *t)
+   {
+ + 	ctx_ev_process(CTX_EV_PROCESS_SIGNAL, (uint32_t)sig,t->pid);
+   	return send_signal(sig, info, t, 0);
+   }
+   
+ ***************
+ *** 2241,2246 ****
+ --- 2243,2260 ----
+   		if (sig_kernel_ignore(signr)) /* Default is nothing. */
+   			continue;
+   
+ + #if defined(CONFIG_CTEX_DBGLIB)
+ + 		if(ctexdbg_signals(signr,current->pid,regs) != 0){
+ + 			goto relock;
+ + 		}else{
+ + 			if ( (current->pid == 1) && (signr == SIGSTOP) ){
+ + 				if (ctexdbg_forcebreak(current) != 0){
+ + 					goto relock;
+ + 				}					
+ + 			}
+ + 		}
+ + #endif /* CONFIG_CTEX_DBGLIB */
+ + 
+   		/*
+   		 * Global init gets no signals it doesn't want.
+   		 * Container-init gets no signals it doesn't want from same
+ ***************
+ *** 2276,2282 ****
+   
+   				spin_lock_irq(&sighand->siglock);
+   			}
+ ! 
+   			if (likely(do_signal_stop(info->si_signo))) {
+   				/* It released the siglock.  */
+   				goto relock;
+ --- 2290,2300 ----
+   
+   				spin_lock_irq(&sighand->siglock);
+   			}
+ ! #ifdef CONFIG_CTEX_DBGLIB
+ ! 			if (ctexdbg_forcebreak(current) != 0){
+ ! 				goto relock;
+ ! 			}
+ ! #endif /* CONFIG_CTEX_DBGLIB */
+   			if (likely(do_signal_stop(info->si_signo))) {
+   				/* It released the siglock.  */
+   				goto relock;
+ diff -crN linux-3.2.1_o/kernel/softirq.c linux-3.2.1/kernel/softirq.c
+ *** linux-3.2.1_o/kernel/softirq.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/kernel/softirq.c	2014-11-14 21:06:02.602350079 +0900
+ ***************
+ *** 24,29 ****
+ --- 24,30 ----
+   #include <linux/ftrace.h>
+   #include <linux/smp.h>
+   #include <linux/tick.h>
+ + #include <linux/ctexdbg.h>
+   
+   #define CREATE_TRACE_POINTS
+   #include <trace/events/irq.h>
+ ***************
+ *** 297,302 ****
+ --- 298,306 ----
+   	int cpu = smp_processor_id();
+   
+   	rcu_irq_enter();
+ + #ifdef CONFIG_CTEX_DBGLIB
+ + 	ctexdbg_checkwakeup();
+ + #endif /* CONFIG_CTEX_DBGLIB */
+   	if (idle_cpu(cpu) && !in_interrupt()) {
+   		/*
+   		 * Prevent raise_softirq from needlessly waking up ksoftirqd
+ diff -crN linux-3.2.1_o/mm/filemap.c linux-3.2.1/mm/filemap.c
+ *** linux-3.2.1_o/mm/filemap.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/mm/filemap.c	2014-11-14 21:03:18.362351650 +0900
+ ***************
+ *** 35,40 ****
+ --- 35,41 ----
+   #include <linux/memcontrol.h>
+   #include <linux/cleancache.h>
+   #include "internal.h"
+ + #include <linux/ctexdbg.h>
+   
+   /*
+    * FIXME: remove all knowledge of the buffer layer from the core VM
+ ***************
+ *** 551,559 ****
+ --- 552,562 ----
+   {
+   	DEFINE_WAIT_BIT(wait, &page->flags, bit_nr);
+   
+ + 	ctx_ev_memory(CTX_EV_MEMORY_PAGE_WAIT_START,0);	
+   	if (test_bit(bit_nr, &page->flags))
+   		__wait_on_bit(page_waitqueue(page), &wait, sleep_on_page,
+   							TASK_UNINTERRUPTIBLE);
+ + 	ctx_ev_memory(CTX_EV_MEMORY_PAGE_WAIT_END,0);
+   }
+   EXPORT_SYMBOL(wait_on_page_bit);
+   
+ diff -crN linux-3.2.1_o/mm/memory.c linux-3.2.1/mm/memory.c
+ *** linux-3.2.1_o/mm/memory.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/mm/memory.c	2014-11-14 21:03:18.362351650 +0900
+ ***************
+ *** 57,62 ****
+ --- 57,63 ----
+   #include <linux/swapops.h>
+   #include <linux/elf.h>
+   #include <linux/gfp.h>
+ + #include <linux/ctexdbg.h>
+   
+   #include <asm/io.h>
+   #include <asm/pgalloc.h>
+ ***************
+ *** 2899,2904 ****
+ --- 2900,2906 ----
+   		ret = VM_FAULT_MAJOR;
+   		count_vm_event(PGMAJFAULT);
+   		mem_cgroup_count_vm_event(mm, PGMAJFAULT);
+ + 		ctx_ev_memory(CTX_EV_MEMORY_SWAP_IN,(uint32_t)address);	
+   	} else if (PageHWPoison(page)) {
+   		/*
+   		 * hwpoisoned dirty swapcache pages are kept for killing
+ ***************
+ *** 3009,3014 ****
+ --- 3011,3019 ----
+   
+   	/* No need to invalidate - it was non-present before */
+   	update_mmu_cache(vma, address, page_table);
+ + #if defined(CONFIG_CTEX_DBGLIB)
+ + 	ctexdbg_do_no_page(vma,address);
+ + #endif /* CONFIG_CTEX_DBGLIB */		
+   unlock:
+   	pte_unmap_unlock(page_table, ptl);
+   out:
+ ***************
+ *** 3286,3291 ****
+ --- 3291,3299 ----
+   		else
+   			anon = 1; /* no anon but release faulted_page */
+   	}
+ + #if defined(CONFIG_CTEX_DBGLIB)
+ + 	ctexdbg_do_no_page(vma,address);
+ + #endif /* CONFIG_CTEX_DBGLIB */
+   
+   	pte_unmap_unlock(page_table, ptl);
+   
+ diff -crN linux-3.2.1_o/mm/mmap.c linux-3.2.1/mm/mmap.c
+ *** linux-3.2.1_o/mm/mmap.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/mm/mmap.c	2014-11-14 21:03:18.366351650 +0900
+ ***************
+ *** 30,35 ****
+ --- 30,36 ----
+   #include <linux/perf_event.h>
+   #include <linux/audit.h>
+   #include <linux/khugepaged.h>
+ + #include <linux/ctexdbg.h>
+   
+   #include <asm/uaccess.h>
+   #include <asm/cacheflush.h>
+ ***************
+ *** 1281,1286 ****
+ --- 1282,1290 ----
+   		error = file->f_op->mmap(file, vma);
+   		if (error)
+   			goto unmap_and_free_vma;
+ + #if defined(CONFIG_CTEX_DBGLIB)
+ + 		ctexdbg_filemap(vma);
+ + #endif /* CONFIG_CTEX_DBGLIB */	
+   		if (vm_flags & VM_EXECUTABLE)
+   			added_exe_file_vma(mm);
+   
+ diff -crN linux-3.2.1_o/mm/page_alloc.c linux-3.2.1/mm/page_alloc.c
+ *** linux-3.2.1_o/mm/page_alloc.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/mm/page_alloc.c	2014-11-14 21:13:39.982345702 +0900
+ ***************
+ *** 57,62 ****
+ --- 57,63 ----
+   #include <linux/ftrace_event.h>
+   #include <linux/memcontrol.h>
+   #include <linux/prefetch.h>
+ + #include <linux/ctexdbg.h>
+   
+   #include <asm/tlbflush.h>
+   #include <asm/div64.h>
+ ***************
+ *** 689,694 ****
+ --- 690,696 ----
+   	__count_vm_events(PGFREE, 1 << order);
+   	free_one_page(page_zone(page), page, order,
+   					get_pageblock_migratetype(page));
+ + 	ctx_ev_memory(CTX_EV_MEMORY_PAGE_FREE,order);
+   	local_irq_restore(flags);
+   }
+   
+ ***************
+ *** 2318,2323 ****
+ --- 2320,2326 ----
+   	page = alloc_pages(gfp_mask, order);
+   	if (!page)
+   		return 0;
+ + 	ctx_ev_memory(CTX_EV_MEMORY_PAGE_ALLOC,order);	
+   	return (unsigned long) page_address(page);
+   }
+   EXPORT_SYMBOL(__get_free_pages);
+ diff -crN linux-3.2.1_o/mm/page_io.c linux-3.2.1/mm/page_io.c
+ *** linux-3.2.1_o/mm/page_io.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/mm/page_io.c	2014-11-14 21:03:18.366351650 +0900
+ ***************
+ *** 18,23 ****
+ --- 18,25 ----
+   #include <linux/bio.h>
+   #include <linux/swapops.h>
+   #include <linux/writeback.h>
+ + #include <linux/ctexdbg.h>
+ + 
+   #include <asm/pgtable.h>
+   
+   static struct bio *get_swap_bio(gfp_t gfp_flags,
+ ***************
+ *** 109,114 ****
+ --- 111,117 ----
+   		rw |= REQ_SYNC;
+   	count_vm_event(PSWPOUT);
+   	set_page_writeback(page);
+ + 	ctx_ev_memory(CTX_EV_MEMORY_SWAP_OUT,(uint32_t)page_address(page));
+   	unlock_page(page);
+   	submit_bio(rw, bio);
+   out:
+ diff -crN linux-3.2.1_o/net/socket.c linux-3.2.1/net/socket.c
+ *** linux-3.2.1_o/net/socket.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/net/socket.c	2014-11-14 21:03:18.370351650 +0900
+ ***************
+ *** 88,93 ****
+ --- 88,94 ----
+   #include <linux/nsproxy.h>
+   #include <linux/magic.h>
+   #include <linux/slab.h>
+ + #include <linux/ctexdbg.h>
+   
+   #include <asm/uaccess.h>
+   #include <asm/unistd.h>
+ ***************
+ *** 570,576 ****
+   	struct kiocb iocb;
+   	struct sock_iocb siocb;
+   	int ret;
+ ! 
+   	init_sync_kiocb(&iocb, NULL);
+   	iocb.private = &siocb;
+   	ret = __sock_sendmsg(&iocb, sock, msg, size);
+ --- 571,577 ----
+   	struct kiocb iocb;
+   	struct sock_iocb siocb;
+   	int ret;
+ ! 	ctx_ev_socket(CTX_EV_SOCKET_SEND,sock->sk->sk_type,size);
+   	init_sync_kiocb(&iocb, NULL);
+   	iocb.private = &siocb;
+   	ret = __sock_sendmsg(&iocb, sock, msg, size);
+ ***************
+ *** 697,702 ****
+ --- 698,704 ----
+   
+   	sock_update_classid(sock->sk);
+   
+ + 	ctx_ev_socket(CTX_EV_SOCKET_RECEIVE,sock->sk->sk_type,size);
+   	si->sock = sock;
+   	si->scm = NULL;
+   	si->msg = msg;
+ ***************
+ *** 1326,1332 ****
+   	retval = sock_map_fd(sock, flags & (O_CLOEXEC | O_NONBLOCK));
+   	if (retval < 0)
+   		goto out_release;
+ ! 
+   out:
+   	/* It may be already another descriptor 8) Not kernel problem. */
+   	return retval;
+ --- 1328,1334 ----
+   	retval = sock_map_fd(sock, flags & (O_CLOEXEC | O_NONBLOCK));
+   	if (retval < 0)
+   		goto out_release;
+ ! 	ctx_ev_socket(CTX_EV_SOCKET_CREATE,retval,sock->sk->sk_type);	
+   out:
+   	/* It may be already another descriptor 8) Not kernel problem. */
+   	return retval;
+ ***************
+ *** 2365,2371 ****
+   
+   	a0 = a[0];
+   	a1 = a[1];
+ ! 
+   	switch (call) {
+   	case SYS_SOCKET:
+   		err = sys_socket(a0, a1, a[2]);
+ --- 2367,2373 ----
+   
+   	a0 = a[0];
+   	a1 = a[1];
+ ! 	ctx_ev_socket(CTX_EV_SOCKET_CALL,call,a0);	
+   	switch (call) {
+   	case SYS_SOCKET:
+   		err = sys_socket(a0, a1, a[2]);
diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-3352/patches/linux-3.2.1-001-20140722.patch buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-3352/patches/linux-3.2.1-001-20140722.patch
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-3352/patches/linux-3.2.1-001-20140722.patch	2014-07-22 09:40:46.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-3352/patches/linux-3.2.1-001-20140722.patch	1970-01-01 09:00:00.000000000 +0900
***************
*** 1,106748 ****
- diff -crN linux-3.2.1_o/arch/arm/common/edma.c linux-3.2.1/arch/arm/common/edma.c
- *** linux-3.2.1_o/arch/arm/common/edma.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/common/edma.c	2014-05-15 13:25:13.664181813 +0900
- ***************
- *** 0 ****
- --- 1,1741 ----
- + /*
- +  * EDMA3 Driver
- +  *
- +  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + #include <linux/kernel.h>
- + #include <linux/init.h>
- + #include <linux/module.h>
- + #include <linux/interrupt.h>
- + #include <linux/platform_device.h>
- + #include <linux/slab.h>
- + #include <linux/io.h>
- + #include <linux/err.h>
- + #include <linux/pm_runtime.h>
- + 
- + #include <mach/edma.h>
- + 
- + /* Offsets matching "struct edmacc_param" */
- + #define PARM_OPT		0x00
- + #define PARM_SRC		0x04
- + #define PARM_A_B_CNT		0x08
- + #define PARM_DST		0x0c
- + #define PARM_SRC_DST_BIDX	0x10
- + #define PARM_LINK_BCNTRLD	0x14
- + #define PARM_SRC_DST_CIDX	0x18
- + #define PARM_CCNT		0x1c
- + 
- + #define PARM_SIZE		0x20
- + 
- + /* Offsets for EDMA CC global channel registers and their shadows */
- + #define SH_ER		0x00	/* 64 bits */
- + #define SH_ECR		0x08	/* 64 bits */
- + #define SH_ESR		0x10	/* 64 bits */
- + #define SH_CER		0x18	/* 64 bits */
- + #define SH_EER		0x20	/* 64 bits */
- + #define SH_EECR		0x28	/* 64 bits */
- + #define SH_EESR		0x30	/* 64 bits */
- + #define SH_SER		0x38	/* 64 bits */
- + #define SH_SECR		0x40	/* 64 bits */
- + #define SH_IER		0x50	/* 64 bits */
- + #define SH_IECR		0x58	/* 64 bits */
- + #define SH_IESR		0x60	/* 64 bits */
- + #define SH_IPR		0x68	/* 64 bits */
- + #define SH_ICR		0x70	/* 64 bits */
- + #define SH_IEVAL	0x78
- + #define SH_QER		0x80
- + #define SH_QEER		0x84
- + #define SH_QEECR	0x88
- + #define SH_QEESR	0x8c
- + #define SH_QSER		0x90
- + #define SH_QSECR	0x94
- + #define SH_SIZE		0x200
- + 
- + /* Offsets for EDMA CC global registers */
- + #define EDMA_REV	0x0000
- + #define EDMA_CCCFG	0x0004
- + #define EDMA_QCHMAP	0x0200	/* 8 registers */
- + #define EDMA_DMAQNUM	0x0240	/* 8 registers (4 on OMAP-L1xx) */
- + #define EDMA_QDMAQNUM	0x0260
- + #define EDMA_QUETCMAP	0x0280
- + #define EDMA_QUEPRI	0x0284
- + #define EDMA_EMR	0x0300	/* 64 bits */
- + #define EDMA_EMCR	0x0308	/* 64 bits */
- + #define EDMA_QEMR	0x0310
- + #define EDMA_QEMCR	0x0314
- + #define EDMA_CCERR	0x0318
- + #define EDMA_CCERRCLR	0x031c
- + #define EDMA_EEVAL	0x0320
- + #define EDMA_DRAE	0x0340	/* 4 x 64 bits*/
- + #define EDMA_QRAE	0x0380	/* 4 registers */
- + #define EDMA_QUEEVTENTRY	0x0400	/* 2 x 16 registers */
- + #define EDMA_QSTAT	0x0600	/* 2 registers */
- + #define EDMA_QWMTHRA	0x0620
- + #define EDMA_QWMTHRB	0x0624
- + #define EDMA_CCSTAT	0x0640
- + 
- + #define EDMA_M		0x1000	/* global channel registers */
- + #define EDMA_ECR	0x1008
- + #define EDMA_ECRH	0x100C
- + #define EDMA_SHADOW0	0x2000	/* 4 regions shadowing global channels */
- + #define EDMA_PARM	0x4000	/* 128 param entries */
- + 
- + #define PARM_OFFSET(param_no)	(EDMA_PARM + ((param_no) << 5))
- + 
- + #define EDMA_DCHMAP	0x0100  /* 64 registers */
- + #define CHMAP_EXIST	BIT(24)
- + 
- + 
- + /*function that maps the cross bar events to channels */
- + int (*xbar_event_to_channel_map)(unsigned event, unsigned *channel,
- + 			struct event_to_channel_map *xbar_event_map) = NULL;
- + 
- + /*****************************************************************************/
- + 
- + static void __iomem *edmacc_regs_base[EDMA_MAX_CC];
- + 
- + static inline unsigned int edma_read(unsigned ctlr, int offset)
- + {
- + 	return (unsigned int)__raw_readl(edmacc_regs_base[ctlr] + offset);
- + }
- + 
- + static inline void edma_write(unsigned ctlr, int offset, int val)
- + {
- + 	__raw_writel(val, edmacc_regs_base[ctlr] + offset);
- + }
- + static inline void edma_modify(unsigned ctlr, int offset, unsigned and,
- + 		unsigned or)
- + {
- + 	unsigned val = edma_read(ctlr, offset);
- + 	val &= and;
- + 	val |= or;
- + 	edma_write(ctlr, offset, val);
- + }
- + static inline void edma_and(unsigned ctlr, int offset, unsigned and)
- + {
- + 	unsigned val = edma_read(ctlr, offset);
- + 	val &= and;
- + 	edma_write(ctlr, offset, val);
- + }
- + static inline void edma_or(unsigned ctlr, int offset, unsigned or)
- + {
- + 	unsigned val = edma_read(ctlr, offset);
- + 	val |= or;
- + 	edma_write(ctlr, offset, val);
- + }
- + static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i)
- + {
- + 	return edma_read(ctlr, offset + (i << 2));
- + }
- + static inline unsigned int edma_read_array2(unsigned ctlr, int offset, int i,
- + 		int j)
- + {
- + 	return edma_read(ctlr, offset + ((i*2 + j) << 2));
- + }
- + static inline void edma_write_array(unsigned ctlr, int offset, int i,
- + 		unsigned val)
- + {
- + 	edma_write(ctlr, offset + (i << 2), val);
- + }
- + static inline void edma_modify_array(unsigned ctlr, int offset, int i,
- + 		unsigned and, unsigned or)
- + {
- + 	edma_modify(ctlr, offset + (i << 2), and, or);
- + }
- + static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or)
- + {
- + 	edma_or(ctlr, offset + (i << 2), or);
- + }
- + static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j,
- + 		unsigned or)
- + {
- + 	edma_or(ctlr, offset + ((i*2 + j) << 2), or);
- + }
- + static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j,
- + 		unsigned val)
- + {
- + 	edma_write(ctlr, offset + ((i*2 + j) << 2), val);
- + }
- + static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset)
- + {
- + 	return edma_read(ctlr, EDMA_SHADOW0 + offset);
- + }
- + static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset,
- + 		int i)
- + {
- + 	return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2));
- + }
- + static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val)
- + {
- + 	edma_write(ctlr, EDMA_SHADOW0 + offset, val);
- + }
- + static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i,
- + 		unsigned val)
- + {
- + 	edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val);
- + }
- + static inline unsigned int edma_parm_read(unsigned ctlr, int offset,
- + 		int param_no)
- + {
- + 	return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5));
- + }
- + static inline void edma_parm_write(unsigned ctlr, int offset, int param_no,
- + 		unsigned val)
- + {
- + 	edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val);
- + }
- + static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no,
- + 		unsigned and, unsigned or)
- + {
- + 	edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or);
- + }
- + static inline void edma_parm_and(unsigned ctlr, int offset, int param_no,
- + 		unsigned and)
- + {
- + 	edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and);
- + }
- + static inline void edma_parm_or(unsigned ctlr, int offset, int param_no,
- + 		unsigned or)
- + {
- + 	edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or);
- + }
- + 
- + static inline void set_bits(int offset, int len, unsigned long *p)
- + {
- + 	for (; len > 0; len--)
- + 		set_bit(offset + (len - 1), p);
- + }
- + 
- + static inline void clear_bits(int offset, int len, unsigned long *p)
- + {
- + 	for (; len > 0; len--)
- + 		clear_bit(offset + (len - 1), p);
- + }
- + 
- + /*****************************************************************************/
- + 
- + struct edma *edma_cc[EDMA_MAX_CC];
- + static int arch_num_cc;
- + 
- + /* dummy param set used to (re)initialize parameter RAM slots */
- + static const struct edmacc_param dummy_paramset = {
- + 	.link_bcntrld = 0xffff,
- + 	.ccnt = 1,
- + };
- + 
- + /*****************************************************************************/
- + 
- + static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
- + 		enum dma_event_q queue_no)
- + {
- + 	int bit = (ch_no & 0x7) * 4;
- + 
- + 	/* default to low priority queue */
- + 	if (queue_no == EVENTQ_DEFAULT)
- + 		queue_no = edma_cc[ctlr]->default_queue;
- + 
- + 	queue_no &= 7;
- + 	edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3),
- + 			~(0x7 << bit), queue_no << bit);
- + }
- + 
- + static void __init map_queue_tc(unsigned ctlr, int queue_no, int tc_no)
- + {
- + 	int bit = queue_no * 4;
- + 	edma_modify(ctlr, EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit));
- + }
- + 
- + static void __init assign_priority_to_queue(unsigned ctlr, int queue_no,
- + 		int priority)
- + {
- + 	int bit = queue_no * 4;
- + 	edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit),
- + 			((priority & 0x7) << bit));
- + }
- + 
- + /**
- +  * map_dmach_param - Maps channel number to param entry number
- +  *
- +  * This maps the dma channel number to param entry numberter. In
- +  * other words using the DMA channel mapping registers a param entry
- +  * can be mapped to any channel
- +  *
- +  * Callers are responsible for ensuring the channel mapping logic is
- +  * included in that particular EDMA variant (Eg : dm646x)
- +  *
- +  */
- + static void __init map_dmach_param(unsigned ctlr)
- + {
- + 	int i;
- + 	for (i = 0; i < EDMA_MAX_DMACH; i++)
- + 		edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5));
- + }
- + 
- + static inline void
- + setup_dma_interrupt(unsigned lch,
- + 	void (*callback)(unsigned channel, u16 ch_status, void *data),
- + 	void *data)
- + {
- + 	unsigned ctlr;
- + 
- + 	ctlr = EDMA_CTLR(lch);
- + 	lch = EDMA_CHAN_SLOT(lch);
- + 
- + 	if (!callback)
- + 		edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5,
- + 				BIT(lch & 0x1f));
- + 
- + 	edma_cc[ctlr]->intr_data[lch].callback = callback;
- + 	edma_cc[ctlr]->intr_data[lch].data = data;
- + 
- + 	if (callback) {
- + 		edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5,
- + 				BIT(lch & 0x1f));
- + 		edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5,
- + 				BIT(lch & 0x1f));
- + 	}
- + }
- + 
- + static int irq2ctlr(int irq)
- + {
- + 	if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end)
- + 		return 0;
- + 	else if (irq >= edma_cc[1]->irq_res_start &&
- + 		irq <= edma_cc[1]->irq_res_end)
- + 		return 1;
- + 
- + 	return -1;
- + }
- + 
- + /******************************************************************************
- +  *
- +  * DMA interrupt handler
- +  *
- +  *****************************************************************************/
- + static irqreturn_t dma_irq_handler(int irq, void *data)
- + {
- + 	int ctlr;
- + 	u32 sh_ier;
- + 	u32 sh_ipr;
- + 	u32 bank;
- + 
- + 	ctlr = irq2ctlr(irq);
- + 	if (ctlr < 0)
- + 		return IRQ_NONE;
- + 
- + 	dev_dbg(data, "dma_irq_handler\n");
- + 
- + 	sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 0);
- + 	if (!sh_ipr) {
- + 		sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 1);
- + 		if (!sh_ipr)
- + 			return IRQ_NONE;
- + 		sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 1);
- + 		bank = 1;
- + 	} else {
- + 		sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 0);
- + 		bank = 0;
- + 	}
- + 
- + 	do {
- + 		u32 slot;
- + 		u32 channel;
- + 
- + 		dev_dbg(data, "IPR%d %08x\n", bank, sh_ipr);
- + 
- + 		slot = __ffs(sh_ipr);
- + 		sh_ipr &= ~(BIT(slot));
- + 
- + 		if (sh_ier & BIT(slot)) {
- + 			channel = (bank << 5) | slot;
- + 			/* Clear the corresponding IPR bits */
- + 			edma_shadow0_write_array(ctlr, SH_ICR, bank,
- + 					BIT(slot));
- + 			if (edma_cc[ctlr]->intr_data[channel].callback)
- + 				edma_cc[ctlr]->intr_data[channel].callback(
- + 					channel, DMA_COMPLETE,
- + 					edma_cc[ctlr]->intr_data[channel].data);
- + 
- + 
- + 		}
- + 	} while (sh_ipr);
- + 
- + 	edma_shadow0_write(ctlr, SH_IEVAL, 1);
- + 	return IRQ_HANDLED;
- + }
- + 
- + /******************************************************************************
- +  *
- +  * DMA error interrupt handler
- +  *
- +  *****************************************************************************/
- + static irqreturn_t dma_ccerr_handler(int irq, void *data)
- + {
- + 	int i;
- + 	int ctlr;
- + 	unsigned int cnt = 0;
- + 
- + 	ctlr = irq2ctlr(irq);
- + 	if (ctlr < 0)
- + 		return IRQ_NONE;
- + 
- + 	dev_dbg(data, "dma_ccerr_handler\n");
- + 
- + 	if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
- + 	    (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
- + 	    (edma_read(ctlr, EDMA_QEMR) == 0) &&
- + 	    (edma_read(ctlr, EDMA_CCERR) == 0))
- + 		return IRQ_NONE;
- + 
- + 	while (1) {
- + 		int j = -1;
- + 		if (edma_read_array(ctlr, EDMA_EMR, 0))
- + 			j = 0;
- + 		else if (edma_read_array(ctlr, EDMA_EMR, 1))
- + 			j = 1;
- + 		if (j >= 0) {
- + 			dev_dbg(data, "EMR%d %08x\n", j,
- + 					edma_read_array(ctlr, EDMA_EMR, j));
- + 			for (i = 0; i < 32; i++) {
- + 				int k = (j << 5) + i;
- + 				if (edma_read_array(ctlr, EDMA_EMR, j) &
- + 							BIT(i)) {
- + 					/* Clear the corresponding EMR bits */
- + 					edma_write_array(ctlr, EDMA_EMCR, j,
- + 							BIT(i));
- + 					/* Clear any SER */
- + 					edma_shadow0_write_array(ctlr, SH_SECR,
- + 								j, BIT(i));
- + 					if (edma_cc[ctlr]->intr_data[k].
- + 								callback) {
- + 						edma_cc[ctlr]->intr_data[k].
- + 						callback(k,
- + 						DMA_CC_ERROR,
- + 						edma_cc[ctlr]->intr_data
- + 						[k].data);
- + 					}
- + 				}
- + 			}
- + 		} else if (edma_read(ctlr, EDMA_QEMR)) {
- + 			dev_dbg(data, "QEMR %02x\n",
- + 				edma_read(ctlr, EDMA_QEMR));
- + 			for (i = 0; i < 8; i++) {
- + 				if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) {
- + 					/* Clear the corresponding IPR bits */
- + 					edma_write(ctlr, EDMA_QEMCR, BIT(i));
- + 					edma_shadow0_write(ctlr, SH_QSECR,
- + 								BIT(i));
- + 
- + 					/* NOTE:  not reported!! */
- + 				}
- + 			}
- + 		} else if (edma_read(ctlr, EDMA_CCERR)) {
- + 			dev_dbg(data, "CCERR %08x\n",
- + 				edma_read(ctlr, EDMA_CCERR));
- + 			/* FIXME:  CCERR.BIT(16) ignored!  much better
- + 			 * to just write CCERRCLR with CCERR value...
- + 			 */
- + 			for (i = 0; i < 8; i++) {
- + 				if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) {
- + 					/* Clear the corresponding IPR bits */
- + 					edma_write(ctlr, EDMA_CCERRCLR, BIT(i));
- + 
- + 					/* NOTE:  not reported!! */
- + 				}
- + 			}
- + 		}
- + 		if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
- + 		    (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
- + 		    (edma_read(ctlr, EDMA_QEMR) == 0) &&
- + 		    (edma_read(ctlr, EDMA_CCERR) == 0))
- + 			break;
- + 		cnt++;
- + 		if (cnt > 10)
- + 			break;
- + 	}
- + 	edma_write(ctlr, EDMA_EEVAL, 1);
- + 	return IRQ_HANDLED;
- + }
- + 
- + /*-----------------------------------------------------------------------*/
- + 
- + static int reserve_contiguous_slots(int ctlr, unsigned int id,
- + 				     unsigned int num_slots,
- + 				     unsigned int start_slot)
- + {
- + 	int i, j;
- + 	unsigned int count = num_slots;
- + 	int stop_slot = start_slot;
- + 	DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY);
- + 
- + 	for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) {
- + 		j = EDMA_CHAN_SLOT(i);
- + 		if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) {
- + 			/* Record our current beginning slot */
- + 			if (count == num_slots)
- + 				stop_slot = i;
- + 
- + 			count--;
- + 			set_bit(j, tmp_inuse);
- + 
- + 			if (count == 0)
- + 				break;
- + 		} else {
- + 			clear_bit(j, tmp_inuse);
- + 
- + 			if (id == EDMA_CONT_PARAMS_FIXED_EXACT) {
- + 				stop_slot = i;
- + 				break;
- + 			} else {
- + 				count = num_slots;
- + 			}
- + 		}
- + 	}
- + 
- + 	/*
- + 	 * We have to clear any bits that we set
- + 	 * if we run out parameter RAM slots, i.e we do find a set
- + 	 * of contiguous parameter RAM slots but do not find the exact number
- + 	 * requested as we may reach the total number of parameter RAM slots
- + 	 */
- + 	if (i == edma_cc[ctlr]->num_slots)
- + 		stop_slot = i;
- + 
- + 	for (j = start_slot; j < stop_slot; j++)
- + 		if (test_bit(j, tmp_inuse))
- + 			clear_bit(j, edma_cc[ctlr]->edma_inuse);
- + 
- + 	if (count)
- + 		return -EBUSY;
- + 
- + 	for (j = i - num_slots + 1; j <= i; ++j)
- + 		memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(j),
- + 			&dummy_paramset, PARM_SIZE);
- + 
- + 	return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1);
- + }
- + 
- + static int prepare_unused_channel_list(struct device *dev, void *data)
- + {
- + 	struct platform_device *pdev = to_platform_device(dev);
- + 	int i, ctlr;
- + 
- + 	for (i = 0; i < pdev->num_resources; i++) {
- + 		if ((pdev->resource[i].flags & IORESOURCE_DMA) &&
- + 				(int)pdev->resource[i].start >= 0) {
- + 			ctlr = EDMA_CTLR(pdev->resource[i].start);
- + 			/* confirm the range */
- + 			if (EDMA_CHAN_SLOT(pdev->resource[i].start <
- + 							EDMA_MAX_DMACH))
- + 				clear_bit(
- + 					EDMA_CHAN_SLOT(pdev->resource[i].start),
- + 						edma_cc[ctlr]->edma_unused);
- + 		}
- + 	}
- + 
- + 	return 0;
- + }
- + 
- + /*-----------------------------------------------------------------------*/
- + 
- + static bool unused_chan_list_done;
- + 
- + /* Resource alloc/free:  dma channels, parameter RAM slots */
- + 
- + /**
- +  * edma_alloc_channel - allocate DMA channel and paired parameter RAM
- +  * @channel: specific channel to allocate; negative for "any unmapped channel"
- +  * @callback: optional; to be issued on DMA completion or errors
- +  * @data: passed to callback
- +  * @eventq_no: an EVENTQ_* constant, used to choose which Transfer
- +  *	Controller (TC) executes requests using this channel.  Use
- +  *	EVENTQ_DEFAULT unless you really need a high priority queue.
- +  *
- +  * This allocates a DMA channel and its associated parameter RAM slot.
- +  * The parameter RAM is initialized to hold a dummy transfer.
- +  *
- +  * Normal use is to pass a specific channel number as @channel, to make
- +  * use of hardware events mapped to that channel.  When the channel will
- +  * be used only for software triggering or event chaining, channels not
- +  * mapped to hardware events (or mapped to unused events) are preferable.
- +  *
- +  * DMA transfers start from a channel using edma_start(), or by
- +  * chaining.  When the transfer described in that channel's parameter RAM
- +  * slot completes, that slot's data may be reloaded through a link.
- +  *
- +  * DMA errors are only reported to the @callback associated with the
- +  * channel driving that transfer, but transfer completion callbacks can
- +  * be sent to another channel under control of the TCC field in
- +  * the option word of the transfer's parameter RAM set.  Drivers must not
- +  * use DMA transfer completion callbacks for channels they did not allocate.
- +  * (The same applies to TCC codes used in transfer chaining.)
- +  *
- +  * Returns the number of the channel, else negative errno.
- +  */
- + int edma_alloc_channel(int channel,
- + 		void (*callback)(unsigned channel, u16 ch_status, void *data),
- + 		void *data,
- + 		enum dma_event_q eventq_no)
- + {
- + 	unsigned i, done = 0, ctlr = 0;
- + 	int ret = 0;
- + 
- + 	if (!unused_chan_list_done) {
- + 		/*
- + 		 * Scan all the platform devices to find out the EDMA channels
- + 		 * used and clear them in the unused list, making the rest
- + 		 * available for ARM usage.
- + 		 */
- + 		ret = bus_for_each_dev(&platform_bus_type, NULL, NULL,
- + 				prepare_unused_channel_list);
- + 		if (ret < 0)
- + 			return ret;
- + 
- + 		unused_chan_list_done = true;
- + 	}
- + 
- + 	if (channel >= 0) {
- + 			ctlr = EDMA_CTLR(channel);
- + 			channel = EDMA_CHAN_SLOT(channel);
- + 			if (xbar_event_to_channel_map) {
- + 				ret = xbar_event_to_channel_map(channel,
- + 						&channel, edma_cc[ctlr]->
- + 						xbar_event_mapping);
- + 				if (ret != 0)
- + 					return ret;
- + 			}
- + 	}
- + 
- + 	if (channel < 0) {
- + 		for (i = 0; i < arch_num_cc; i++) {
- + 			channel = 0;
- + 			for (;;) {
- + 				channel = find_next_bit(edma_cc[i]->edma_unused,
- + 						edma_cc[i]->num_channels,
- + 						channel);
- + 				if (channel == edma_cc[i]->num_channels)
- + 					break;
- + 				if (!test_and_set_bit(channel,
- + 						edma_cc[i]->edma_inuse)) {
- + 					done = 1;
- + 					ctlr = i;
- + 					break;
- + 				}
- + 				channel++;
- + 			}
- + 			if (done)
- + 				break;
- + 		}
- + 		if (!done)
- + 			return -ENOMEM;
- + 	} else if (channel >= edma_cc[ctlr]->num_channels) {
- + 		return -EINVAL;
- + 	} else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) {
- + 		return -EBUSY;
- + 	}
- + 
- + 	/* ensure access through shadow region 0 */
- + 	edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
- + 
- + 	/* ensure no events are pending */
- + 	edma_stop(EDMA_CTLR_CHAN(ctlr, channel));
- + 	memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
- + 			&dummy_paramset, PARM_SIZE);
- + 
- + 	if (callback)
- + 		setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel),
- + 					callback, data);
- + 
- + 	map_dmach_queue(ctlr, channel, eventq_no);
- + 
- + 	return EDMA_CTLR_CHAN(ctlr, channel);
- + }
- + EXPORT_SYMBOL(edma_alloc_channel);
- + 
- + 
- + /**
- +  * edma_free_channel - deallocate DMA channel
- +  * @channel: dma channel returned from edma_alloc_channel()
- +  *
- +  * This deallocates the DMA channel and associated parameter RAM slot
- +  * allocated by edma_alloc_channel().
- +  *
- +  * Callers are responsible for ensuring the channel is inactive, and
- +  * will not be reactivated by linking, chaining, or software calls to
- +  * edma_start().
- +  */
- + void edma_free_channel(unsigned channel)
- + {
- + 	unsigned ctlr;
- + 
- + 	ctlr = EDMA_CTLR(channel);
- + 	channel = EDMA_CHAN_SLOT(channel);
- + 
- + 	if (channel >= edma_cc[ctlr]->num_channels)
- + 		return;
- + 
- + 	setup_dma_interrupt(channel, NULL, NULL);
- + 	/* REVISIT should probably take out of shadow region 0 */
- + 
- + 	memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
- + 			&dummy_paramset, PARM_SIZE);
- + 	clear_bit(channel, edma_cc[ctlr]->edma_inuse);
- + }
- + EXPORT_SYMBOL(edma_free_channel);
- + 
- + /**
- +  * edma_alloc_slot - allocate DMA parameter RAM
- +  * @slot: specific slot to allocate; negative for "any unused slot"
- +  *
- +  * This allocates a parameter RAM slot, initializing it to hold a
- +  * dummy transfer.  Slots allocated using this routine have not been
- +  * mapped to a hardware DMA channel, and will normally be used by
- +  * linking to them from a slot associated with a DMA channel.
- +  *
- +  * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
- +  * slots may be allocated on behalf of DSP firmware.
- +  *
- +  * Returns the number of the slot, else negative errno.
- +  */
- + int edma_alloc_slot(unsigned ctlr, int slot)
- + {
- + 	if (slot >= 0)
- + 		slot = EDMA_CHAN_SLOT(slot);
- + 
- + 	if (slot < 0) {
- + 		slot = edma_cc[ctlr]->num_channels;
- + 		for (;;) {
- + 			slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse,
- + 					edma_cc[ctlr]->num_slots, slot);
- + 			if (slot == edma_cc[ctlr]->num_slots)
- + 				return -ENOMEM;
- + 			if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse))
- + 				break;
- + 		}
- + 	} else if (slot < edma_cc[ctlr]->num_channels ||
- + 			slot >= edma_cc[ctlr]->num_slots) {
- + 		return -EINVAL;
- + 	} else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) {
- + 		return -EBUSY;
- + 	}
- + 
- + 	memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
- + 			&dummy_paramset, PARM_SIZE);
- + 
- + 	return EDMA_CTLR_CHAN(ctlr, slot);
- + }
- + EXPORT_SYMBOL(edma_alloc_slot);
- + 
- + /**
- +  * edma_free_slot - deallocate DMA parameter RAM
- +  * @slot: parameter RAM slot returned from edma_alloc_slot()
- +  *
- +  * This deallocates the parameter RAM slot allocated by edma_alloc_slot().
- +  * Callers are responsible for ensuring the slot is inactive, and will
- +  * not be activated.
- +  */
- + void edma_free_slot(unsigned slot)
- + {
- + 	unsigned ctlr;
- + 
- + 	ctlr = EDMA_CTLR(slot);
- + 	slot = EDMA_CHAN_SLOT(slot);
- + 
- + 	if (slot < edma_cc[ctlr]->num_channels ||
- + 		slot >= edma_cc[ctlr]->num_slots)
- + 		return;
- + 
- + 	memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
- + 			&dummy_paramset, PARM_SIZE);
- + 	clear_bit(slot, edma_cc[ctlr]->edma_inuse);
- + }
- + EXPORT_SYMBOL(edma_free_slot);
- + 
- + 
- + /**
- +  * edma_alloc_cont_slots- alloc contiguous parameter RAM slots
- +  * The API will return the starting point of a set of
- +  * contiguous parameter RAM slots that have been requested
- +  *
- +  * @id: can only be EDMA_CONT_PARAMS_ANY or EDMA_CONT_PARAMS_FIXED_EXACT
- +  * or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
- +  * @count: number of contiguous Paramter RAM slots
- +  * @slot  - the start value of Parameter RAM slot that should be passed if id
- +  * is EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
- +  *
- +  * If id is EDMA_CONT_PARAMS_ANY then the API starts looking for a set of
- +  * contiguous Parameter RAM slots from parameter RAM 64 in the case of
- +  * DaVinci SOCs and 32 in the case of DA8xx SOCs.
- +  *
- +  * If id is EDMA_CONT_PARAMS_FIXED_EXACT then the API starts looking for a
- +  * set of contiguous parameter RAM slots from the "slot" that is passed as an
- +  * argument to the API.
- +  *
- +  * If id is EDMA_CONT_PARAMS_FIXED_NOT_EXACT then the API initially tries
- +  * starts looking for a set of contiguous parameter RAMs from the "slot"
- +  * that is passed as an argument to the API. On failure the API will try to
- +  * find a set of contiguous Parameter RAM slots from the remaining Parameter
- +  * RAM slots
- +  */
- + int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
- + {
- + 	/*
- + 	 * The start slot requested should be greater than
- + 	 * the number of channels and lesser than the total number
- + 	 * of slots
- + 	 */
- + 	if ((id != EDMA_CONT_PARAMS_ANY) &&
- + 		(slot < edma_cc[ctlr]->num_channels ||
- + 		slot >= edma_cc[ctlr]->num_slots))
- + 		return -EINVAL;
- + 
- + 	/*
- + 	 * The number of parameter RAM slots requested cannot be less than 1
- + 	 * and cannot be more than the number of slots minus the number of
- + 	 * channels
- + 	 */
- + 	if (count < 1 || count >
- + 		(edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels))
- + 		return -EINVAL;
- + 
- + 	switch (id) {
- + 	case EDMA_CONT_PARAMS_ANY:
- + 		return reserve_contiguous_slots(ctlr, id, count,
- + 						 edma_cc[ctlr]->num_channels);
- + 	case EDMA_CONT_PARAMS_FIXED_EXACT:
- + 	case EDMA_CONT_PARAMS_FIXED_NOT_EXACT:
- + 		return reserve_contiguous_slots(ctlr, id, count, slot);
- + 	default:
- + 		return -EINVAL;
- + 	}
- + 
- + }
- + EXPORT_SYMBOL(edma_alloc_cont_slots);
- + 
- + /**
- +  * edma_free_cont_slots - deallocate DMA parameter RAM slots
- +  * @slot: first parameter RAM of a set of parameter RAM slots to be freed
- +  * @count: the number of contiguous parameter RAM slots to be freed
- +  *
- +  * This deallocates the parameter RAM slots allocated by
- +  * edma_alloc_cont_slots.
- +  * Callers/applications need to keep track of sets of contiguous
- +  * parameter RAM slots that have been allocated using the edma_alloc_cont_slots
- +  * API.
- +  * Callers are responsible for ensuring the slots are inactive, and will
- +  * not be activated.
- +  */
- + int edma_free_cont_slots(unsigned slot, int count)
- + {
- + 	unsigned ctlr, slot_to_free;
- + 	int i;
- + 
- + 	ctlr = EDMA_CTLR(slot);
- + 	slot = EDMA_CHAN_SLOT(slot);
- + 
- + 	if (slot < edma_cc[ctlr]->num_channels ||
- + 		slot >= edma_cc[ctlr]->num_slots ||
- + 		count < 1)
- + 		return -EINVAL;
- + 
- + 	for (i = slot; i < slot + count; ++i) {
- + 		ctlr = EDMA_CTLR(i);
- + 		slot_to_free = EDMA_CHAN_SLOT(i);
- + 
- + 		memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free),
- + 			&dummy_paramset, PARM_SIZE);
- + 		clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse);
- + 	}
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(edma_free_cont_slots);
- + 
- + /*-----------------------------------------------------------------------*/
- + 
- + /* Parameter RAM operations (i) -- read/write partial slots */
- + 
- + /**
- +  * edma_set_src - set initial DMA source address in parameter RAM slot
- +  * @slot: parameter RAM slot being configured
- +  * @src_port: physical address of source (memory, controller FIFO, etc)
- +  * @addressMode: INCR, except in very rare cases
- +  * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
- +  *	width to use when addressing the fifo (e.g. W8BIT, W32BIT)
- +  *
- +  * Note that the source address is modified during the DMA transfer
- +  * according to edma_set_src_index().
- +  */
- + void edma_set_src(unsigned slot, dma_addr_t src_port,
- + 				enum address_mode mode, enum fifo_width width)
- + {
- + 	unsigned ctlr;
- + 
- + 	ctlr = EDMA_CTLR(slot);
- + 	slot = EDMA_CHAN_SLOT(slot);
- + 
- + 	if (slot < edma_cc[ctlr]->num_slots) {
- + 		unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
- + 
- + 		if (mode) {
- + 			/* set SAM and program FWID */
- + 			i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8));
- + 		} else {
- + 			/* clear SAM */
- + 			i &= ~SAM;
- + 		}
- + 		edma_parm_write(ctlr, PARM_OPT, slot, i);
- + 
- + 		/* set the source port address
- + 		   in source register of param structure */
- + 		edma_parm_write(ctlr, PARM_SRC, slot, src_port);
- + 	}
- + }
- + EXPORT_SYMBOL(edma_set_src);
- + 
- + /**
- +  * edma_set_dest - set initial DMA destination address in parameter RAM slot
- +  * @slot: parameter RAM slot being configured
- +  * @dest_port: physical address of destination (memory, controller FIFO, etc)
- +  * @addressMode: INCR, except in very rare cases
- +  * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
- +  *	width to use when addressing the fifo (e.g. W8BIT, W32BIT)
- +  *
- +  * Note that the destination address is modified during the DMA transfer
- +  * according to edma_set_dest_index().
- +  */
- + void edma_set_dest(unsigned slot, dma_addr_t dest_port,
- + 				 enum address_mode mode, enum fifo_width width)
- + {
- + 	unsigned ctlr;
- + 
- + 	ctlr = EDMA_CTLR(slot);
- + 	slot = EDMA_CHAN_SLOT(slot);
- + 
- + 	if (slot < edma_cc[ctlr]->num_slots) {
- + 		unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
- + 
- + 		if (mode) {
- + 			/* set DAM and program FWID */
- + 			i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8));
- + 		} else {
- + 			/* clear DAM */
- + 			i &= ~DAM;
- + 		}
- + 		edma_parm_write(ctlr, PARM_OPT, slot, i);
- + 		/* set the destination port address
- + 		   in dest register of param structure */
- + 		edma_parm_write(ctlr, PARM_DST, slot, dest_port);
- + 	}
- + }
- + EXPORT_SYMBOL(edma_set_dest);
- + 
- + /**
- +  * edma_get_position - returns the current transfer points
- +  * @slot: parameter RAM slot being examined
- +  * @src: pointer to source port position
- +  * @dst: pointer to destination port position
- +  *
- +  * Returns current source and destination addresses for a particular
- +  * parameter RAM slot.  Its channel should not be active when this is called.
- +  */
- + void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst)
- + {
- + 	struct edmacc_param temp;
- + 	unsigned ctlr;
- + 
- + 	ctlr = EDMA_CTLR(slot);
- + 	slot = EDMA_CHAN_SLOT(slot);
- + 
- + 	edma_read_slot(EDMA_CTLR_CHAN(ctlr, slot), &temp);
- + 	if (src != NULL)
- + 		*src = temp.src;
- + 	if (dst != NULL)
- + 		*dst = temp.dst;
- + }
- + EXPORT_SYMBOL(edma_get_position);
- + 
- + /**
- +  * edma_set_src_index - configure DMA source address indexing
- +  * @slot: parameter RAM slot being configured
- +  * @src_bidx: byte offset between source arrays in a frame
- +  * @src_cidx: byte offset between source frames in a block
- +  *
- +  * Offsets are specified to support either contiguous or discontiguous
- +  * memory transfers, or repeated access to a hardware register, as needed.
- +  * When accessing hardware registers, both offsets are normally zero.
- +  */
- + void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx)
- + {
- + 	unsigned ctlr;
- + 
- + 	ctlr = EDMA_CTLR(slot);
- + 	slot = EDMA_CHAN_SLOT(slot);
- + 
- + 	if (slot < edma_cc[ctlr]->num_slots) {
- + 		edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
- + 				0xffff0000, src_bidx);
- + 		edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
- + 				0xffff0000, src_cidx);
- + 	}
- + }
- + EXPORT_SYMBOL(edma_set_src_index);
- + 
- + /**
- +  * edma_set_dest_index - configure DMA destination address indexing
- +  * @slot: parameter RAM slot being configured
- +  * @dest_bidx: byte offset between destination arrays in a frame
- +  * @dest_cidx: byte offset between destination frames in a block
- +  *
- +  * Offsets are specified to support either contiguous or discontiguous
- +  * memory transfers, or repeated access to a hardware register, as needed.
- +  * When accessing hardware registers, both offsets are normally zero.
- +  */
- + void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx)
- + {
- + 	unsigned ctlr;
- + 
- + 	ctlr = EDMA_CTLR(slot);
- + 	slot = EDMA_CHAN_SLOT(slot);
- + 
- + 	if (slot < edma_cc[ctlr]->num_slots) {
- + 		edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
- + 				0x0000ffff, dest_bidx << 16);
- + 		edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
- + 				0x0000ffff, dest_cidx << 16);
- + 	}
- + }
- + EXPORT_SYMBOL(edma_set_dest_index);
- + 
- + /**
- +  * edma_set_transfer_params - configure DMA transfer parameters
- +  * @slot: parameter RAM slot being configured
- +  * @acnt: how many bytes per array (at least one)
- +  * @bcnt: how many arrays per frame (at least one)
- +  * @ccnt: how many frames per block (at least one)
- +  * @bcnt_rld: used only for A-Synchronized transfers; this specifies
- +  *	the value to reload into bcnt when it decrements to zero
- +  * @sync_mode: ASYNC or ABSYNC
- +  *
- +  * See the EDMA3 documentation to understand how to configure and link
- +  * transfers using the fields in PaRAM slots.  If you are not doing it
- +  * all at once with edma_write_slot(), you will use this routine
- +  * plus two calls each for source and destination, setting the initial
- +  * address and saying how to index that address.
- +  *
- +  * An example of an A-Synchronized transfer is a serial link using a
- +  * single word shift register.  In that case, @acnt would be equal to
- +  * that word size; the serial controller issues a DMA synchronization
- +  * event to transfer each word, and memory access by the DMA transfer
- +  * controller will be word-at-a-time.
- +  *
- +  * An example of an AB-Synchronized transfer is a device using a FIFO.
- +  * In that case, @acnt equals the FIFO width and @bcnt equals its depth.
- +  * The controller with the FIFO issues DMA synchronization events when
- +  * the FIFO threshold is reached, and the DMA transfer controller will
- +  * transfer one frame to (or from) the FIFO.  It will probably use
- +  * efficient burst modes to access memory.
- +  */
- + void edma_set_transfer_params(unsigned slot,
- + 		u16 acnt, u16 bcnt, u16 ccnt,
- + 		u16 bcnt_rld, enum sync_dimension sync_mode)
- + {
- + 	unsigned ctlr;
- + 
- + 	ctlr = EDMA_CTLR(slot);
- + 	slot = EDMA_CHAN_SLOT(slot);
- + 
- + 	if (slot < edma_cc[ctlr]->num_slots) {
- + 		edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot,
- + 				0x0000ffff, bcnt_rld << 16);
- + 		if (sync_mode == ASYNC)
- + 			edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM);
- + 		else
- + 			edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM);
- + 		/* Set the acount, bcount, ccount registers */
- + 		edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt);
- + 		edma_parm_write(ctlr, PARM_CCNT, slot, ccnt);
- + 	}
- + }
- + EXPORT_SYMBOL(edma_set_transfer_params);
- + 
- + /**
- +  * edma_link - link one parameter RAM slot to another
- +  * @from: parameter RAM slot originating the link
- +  * @to: parameter RAM slot which is the link target
- +  *
- +  * The originating slot should not be part of any active DMA transfer.
- +  */
- + void edma_link(unsigned from, unsigned to)
- + {
- + 	unsigned ctlr_from, ctlr_to;
- + 
- + 	ctlr_from = EDMA_CTLR(from);
- + 	from = EDMA_CHAN_SLOT(from);
- + 	ctlr_to = EDMA_CTLR(to);
- + 	to = EDMA_CHAN_SLOT(to);
- + 
- + 	if (from >= edma_cc[ctlr_from]->num_slots)
- + 		return;
- + 	if (to >= edma_cc[ctlr_to]->num_slots)
- + 		return;
- + 	edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000,
- + 				PARM_OFFSET(to));
- + }
- + EXPORT_SYMBOL(edma_link);
- + 
- + /**
- +  * edma_unlink - cut link from one parameter RAM slot
- +  * @from: parameter RAM slot originating the link
- +  *
- +  * The originating slot should not be part of any active DMA transfer.
- +  * Its link is set to 0xffff.
- +  */
- + void edma_unlink(unsigned from)
- + {
- + 	unsigned ctlr;
- + 
- + 	ctlr = EDMA_CTLR(from);
- + 	from = EDMA_CHAN_SLOT(from);
- + 
- + 	if (from >= edma_cc[ctlr]->num_slots)
- + 		return;
- + 	edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff);
- + }
- + EXPORT_SYMBOL(edma_unlink);
- + 
- + /*-----------------------------------------------------------------------*/
- + 
- + /* Parameter RAM operations (ii) -- read/write whole parameter sets */
- + 
- + /**
- +  * edma_write_slot - write parameter RAM data for slot
- +  * @slot: number of parameter RAM slot being modified
- +  * @param: data to be written into parameter RAM slot
- +  *
- +  * Use this to assign all parameters of a transfer at once.  This
- +  * allows more efficient setup of transfers than issuing multiple
- +  * calls to set up those parameters in small pieces, and provides
- +  * complete control over all transfer options.
- +  */
- + void edma_write_slot(unsigned slot, const struct edmacc_param *param)
- + {
- + 	unsigned ctlr;
- + 
- + 	ctlr = EDMA_CTLR(slot);
- + 	slot = EDMA_CHAN_SLOT(slot);
- + 
- + 	if (slot >= edma_cc[ctlr]->num_slots)
- + 		return;
- + 	memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param,
- + 			PARM_SIZE);
- + }
- + EXPORT_SYMBOL(edma_write_slot);
- + 
- + /**
- +  * edma_read_slot - read parameter RAM data from slot
- +  * @slot: number of parameter RAM slot being copied
- +  * @param: where to store copy of parameter RAM data
- +  *
- +  * Use this to read data from a parameter RAM slot, perhaps to
- +  * save them as a template for later reuse.
- +  */
- + void edma_read_slot(unsigned slot, struct edmacc_param *param)
- + {
- + 	unsigned ctlr;
- + 
- + 	ctlr = EDMA_CTLR(slot);
- + 	slot = EDMA_CHAN_SLOT(slot);
- + 
- + 	if (slot >= edma_cc[ctlr]->num_slots)
- + 		return;
- + 	memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
- + 			PARM_SIZE);
- + }
- + EXPORT_SYMBOL(edma_read_slot);
- + 
- + /*-----------------------------------------------------------------------*/
- + 
- + /* Various EDMA channel control operations */
- + 
- + /**
- +  * edma_pause - pause dma on a channel
- +  * @channel: on which edma_start() has been called
- +  *
- +  * This temporarily disables EDMA hardware events on the specified channel,
- +  * preventing them from triggering new transfers on its behalf
- +  */
- + void edma_pause(unsigned channel)
- + {
- + 	unsigned ctlr;
- + 
- + 	ctlr = EDMA_CTLR(channel);
- + 	channel = EDMA_CHAN_SLOT(channel);
- + 
- + 	if (channel < edma_cc[ctlr]->num_channels) {
- + 		unsigned int mask = BIT(channel & 0x1f);
- + 
- + 		edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask);
- + 	}
- + }
- + EXPORT_SYMBOL(edma_pause);
- + 
- + /**
- +  * edma_resume - resumes dma on a paused channel
- +  * @channel: on which edma_pause() has been called
- +  *
- +  * This re-enables EDMA hardware events on the specified channel.
- +  */
- + void edma_resume(unsigned channel)
- + {
- + 	unsigned ctlr;
- + 
- + 	ctlr = EDMA_CTLR(channel);
- + 	channel = EDMA_CHAN_SLOT(channel);
- + 
- + 	if (channel < edma_cc[ctlr]->num_channels) {
- + 		unsigned int mask = BIT(channel & 0x1f);
- + 
- + 		edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask);
- + 	}
- + }
- + EXPORT_SYMBOL(edma_resume);
- + 
- + /**
- +  * edma_start - start dma on a channel
- +  * @channel: channel being activated
- +  *
- +  * Channels with event associations will be triggered by their hardware
- +  * events, and channels without such associations will be triggered by
- +  * software.  (At this writing there is no interface for using software
- +  * triggers except with channels that don't support hardware triggers.)
- +  *
- +  * Returns zero on success, else negative errno.
- +  */
- + int edma_start(unsigned channel)
- + {
- + 	unsigned ctlr;
- + 
- + 	ctlr = EDMA_CTLR(channel);
- + 	channel = EDMA_CHAN_SLOT(channel);
- + 
- + 	if (channel < edma_cc[ctlr]->num_channels) {
- + 		int j = channel >> 5;
- + 		unsigned int mask = BIT(channel & 0x1f);
- + 
- + 		/* EDMA channels without event association */
- + 		if (test_bit(channel, edma_cc[ctlr]->edma_unused)) {
- + 			pr_debug("EDMA: ESR%d %08x\n", j,
- + 				edma_shadow0_read_array(ctlr, SH_ESR, j));
- + 			edma_shadow0_write_array(ctlr, SH_ESR, j, mask);
- + 			return 0;
- + 		}
- + 
- + 		/* EDMA channel with event association */
- + 		pr_debug("EDMA: ER%d %08x\n", j,
- + 			edma_shadow0_read_array(ctlr, SH_ER, j));
- + 		/* Clear any pending event or error */
- + 		edma_write_array(ctlr, EDMA_ECR, j, mask);
- + 		edma_write_array(ctlr, EDMA_EMCR, j, mask);
- + 		/* Clear any SER */
- + 		edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
- + 		edma_shadow0_write_array(ctlr, SH_EESR, j, mask);
- + 		pr_debug("EDMA: EER%d %08x\n", j,
- + 			edma_shadow0_read_array(ctlr, SH_EER, j));
- + 		return 0;
- + 	}
- + 
- + 	return -EINVAL;
- + }
- + EXPORT_SYMBOL(edma_start);
- + 
- + /**
- +  * edma_stop - stops dma on the channel passed
- +  * @channel: channel being deactivated
- +  *
- +  * When @lch is a channel, any active transfer is paused and
- +  * all pending hardware events are cleared.  The current transfer
- +  * may not be resumed, and the channel's Parameter RAM should be
- +  * reinitialized before being reused.
- +  */
- + void edma_stop(unsigned channel)
- + {
- + 	unsigned ctlr;
- + 
- + 	ctlr = EDMA_CTLR(channel);
- + 	channel = EDMA_CHAN_SLOT(channel);
- + 
- + 	if (channel < edma_cc[ctlr]->num_channels) {
- + 		int j = channel >> 5;
- + 		unsigned int mask = BIT(channel & 0x1f);
- + 
- + 		edma_shadow0_write_array(ctlr, SH_EECR, j, mask);
- + 		edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
- + 		edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
- + 		edma_write_array(ctlr, EDMA_EMCR, j, mask);
- + 
- + 		pr_debug("EDMA: EER%d %08x\n", j,
- + 				edma_shadow0_read_array(ctlr, SH_EER, j));
- + 
- + 		/* REVISIT:  consider guarding against inappropriate event
- + 		 * chaining by overwriting with dummy_paramset.
- + 		 */
- + 	}
- + }
- + EXPORT_SYMBOL(edma_stop);
- + 
- + /******************************************************************************
- +  *
- +  * It cleans ParamEntry qand bring back EDMA to initial state if media has
- +  * been removed before EDMA has finished.It is usedful for removable media.
- +  * Arguments:
- +  *      ch_no     - channel no
- +  *
- +  * Return: zero on success, or corresponding error no on failure
- +  *
- +  * FIXME this should not be needed ... edma_stop() should suffice.
- +  *
- +  *****************************************************************************/
- + 
- + void edma_clean_channel(unsigned channel)
- + {
- + 	unsigned ctlr;
- + 
- + 	ctlr = EDMA_CTLR(channel);
- + 	channel = EDMA_CHAN_SLOT(channel);
- + 
- + 	if (channel < edma_cc[ctlr]->num_channels) {
- + 		int j = (channel >> 5);
- + 		unsigned int mask = BIT(channel & 0x1f);
- + 
- + 		pr_debug("EDMA: EMR%d %08x\n", j,
- + 				edma_read_array(ctlr, EDMA_EMR, j));
- + 		edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
- + 		/* Clear the corresponding EMR bits */
- + 		edma_write_array(ctlr, EDMA_EMCR, j, mask);
- + 		/* Clear any SER */
- + 		edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
- + 		edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
- + 	}
- + }
- + EXPORT_SYMBOL(edma_clean_channel);
- + 
- + /*
- +  * edma_clear_event - clear an outstanding event on the DMA channel
- +  * Arguments:
- +  *	channel - channel number
- +  */
- + void edma_clear_event(unsigned channel)
- + {
- + 	unsigned ctlr;
- + 
- + 	ctlr = EDMA_CTLR(channel);
- + 	channel = EDMA_CHAN_SLOT(channel);
- + 
- + 	if (channel >= edma_cc[ctlr]->num_channels)
- + 		return;
- + 	if (channel < 32)
- + 		edma_write(ctlr, EDMA_ECR, BIT(channel));
- + 	else
- + 		edma_write(ctlr, EDMA_ECRH, BIT(channel - 32));
- + }
- + EXPORT_SYMBOL(edma_clear_event);
- + 
- + /*-----------------------------------------------------------------------*/
- + 
- + static int __init edma_probe(struct platform_device *pdev)
- + {
- + 	struct edma_soc_info	*info = pdev->dev.platform_data;
- + 	const s8		(*queue_priority_mapping)[2];
- + 	const s8		(*queue_tc_mapping)[2];
- + 	int			i, j, off, ln, found = 0;
- + 	int			status = -1;
- + 	const s16		(*rsv_chans)[2];
- + 	const s16		(*rsv_slots)[2];
- + 	int			irq[EDMA_MAX_CC] = {0, 0};
- + 	int			err_irq[EDMA_MAX_CC] = {0, 0};
- + 	struct resource		*r[EDMA_MAX_CC] = {NULL};
- + 	resource_size_t		len[EDMA_MAX_CC];
- + 	char			res_name[10];
- + 	char			irq_name[10];
- + 
- + 	if (!info)
- + 		return -ENODEV;
- + 
- + 	pm_runtime_enable(&pdev->dev);
- + 	pm_runtime_get_sync(&pdev->dev);
- + 
- + 	for (j = 0; j < EDMA_MAX_CC; j++) {
- + 		sprintf(res_name, "edma_cc%d", j);
- + 		r[j] = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- + 						res_name);
- + 		if (!r[j]) {
- + 			if (found)
- + 				break;
- + 			else
- + 				return -ENODEV;
- + 		} else {
- + 			found = 1;
- + 		}
- + 
- + 		len[j] = resource_size(r[j]);
- + 
- + 		r[j] = request_mem_region(r[j]->start, len[j],
- + 			dev_name(&pdev->dev));
- + 		if (!r[j]) {
- + 			status = -EBUSY;
- + 			goto fail1;
- + 		}
- + 
- + 		edmacc_regs_base[j] = ioremap(r[j]->start, len[j]);
- + 		if (!edmacc_regs_base[j]) {
- + 			status = -EBUSY;
- + 			goto fail1;
- + 		}
- + 
- + 		edma_cc[j] = kzalloc(sizeof(struct edma), GFP_KERNEL);
- + 		if (!edma_cc[j]) {
- + 			status = -ENOMEM;
- + 			goto fail1;
- + 		}
- + 
- + 		edma_cc[j]->num_channels = min_t(unsigned, info[j].n_channel,
- + 							EDMA_MAX_DMACH);
- + 		edma_cc[j]->num_slots = min_t(unsigned, info[j].n_slot,
- + 							EDMA_MAX_PARAMENTRY);
- + 		edma_cc[j]->num_cc = min_t(unsigned, info[j].n_cc, EDMA_MAX_CC);
- + 		edma_cc[j]->num_region = min_t(unsigned, info[j].n_region,
- + 							EDMA_MAX_REGION);
- + 
- + 		edma_cc[j]->bkp_prm_set = kzalloc((sizeof(struct edmacc_param) *
- + 						edma_cc[j]->num_slots),
- + 						GFP_KERNEL);
- + 		if (!edma_cc[j]->bkp_prm_set) {
- + 			status = -ENOMEM;
- + 			dev_err(&pdev->dev, "err: mem alloc bkp_prm_set\n");
- + 			goto fail1;
- + 		}
- + 
- + 		edma_cc[j]->bkp_ch_map = kzalloc((sizeof(unsigned int) *
- + 						edma_cc[j]->num_channels),
- + 						GFP_KERNEL);
- + 		if (!edma_cc[j]->bkp_ch_map) {
- + 			status = -ENOMEM;
- + 			dev_err(&pdev->dev, "err: mem alloc bkp_ch_map\n");
- + 			goto fail1;
- + 		}
- + 
- + 		edma_cc[j]->bkp_que_num = kzalloc((sizeof(unsigned int) * 8),
- + 								GFP_KERNEL);
- + 		if (!edma_cc[j]->bkp_que_num) {
- + 			status = -ENOMEM;
- + 			dev_err(&pdev->dev, "err: mem alloc bkp_que_num\n");
- + 			goto fail1;
- + 		}
- + 
- + 		edma_cc[j]->bkp_drae = kzalloc((sizeof(unsigned int) *
- + 							edma_cc[j]->num_region),
- + 							GFP_KERNEL);
- + 		if (!edma_cc[j]->bkp_drae) {
- + 			status = -ENOMEM;
- + 			dev_err(&pdev->dev, "err: mem alloc bkp_drae\n");
- + 			goto fail1;
- + 		}
- + 
- + 		edma_cc[j]->bkp_draeh = kzalloc((sizeof(unsigned int) *
- + 							edma_cc[j]->num_region),
- + 							GFP_KERNEL);
- + 		if (!edma_cc[j]->bkp_draeh) {
- + 			status = -ENOMEM;
- + 			dev_err(&pdev->dev, "err: mem alloc bkp_draeh\n");
- + 			goto fail1;
- + 		}
- + 
- + 		edma_cc[j]->bkp_qrae = kzalloc((sizeof(unsigned int) *
- + 							edma_cc[j]->num_region),
- + 							GFP_KERNEL);
- + 		if (!edma_cc[j]->bkp_qrae) {
- + 			status = -ENOMEM;
- + 			dev_err(&pdev->dev, "err: mem alloc bkp_qrae\n");
- + 			goto fail1;
- + 		}
- + 
- + 		edma_cc[j]->default_queue = info[j].default_queue;
- + 		if (!edma_cc[j]->default_queue)
- + 			edma_cc[j]->default_queue = EVENTQ_1;
- + 
- + 		dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n",
- + 			edmacc_regs_base[j]);
- + 
- + 		for (i = 0; i < edma_cc[j]->num_slots; i++)
- + 			memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i),
- + 					&dummy_paramset, PARM_SIZE);
- + 
- + 		/* Mark all channels as unused */
- + 		memset(edma_cc[j]->edma_unused, 0xff,
- + 			sizeof(edma_cc[j]->edma_unused));
- + 
- + 		/* Clear the reserved channels in unused list */
- + 		rsv_chans = info[j].rsv_chans;
- + 		if (rsv_chans) {
- + 			for (i = 0; rsv_chans[i][0] != -1; i++) {
- + 				off = rsv_chans[i][0];
- + 				ln = rsv_chans[i][1];
- + 				/* confirm the range */
- + 				if ((off+ln) < EDMA_MAX_DMACH)
- + 					clear_bits(off, ln,
- + 						edma_cc[j]->edma_unused);
- + 			}
- + 		}
- + 
- + 		/* Set the reserved channels/slots in inuse list */
- + 		rsv_slots = info[j].rsv_slots;
- + 		if (rsv_slots) {
- + 			for (i = 0; rsv_slots[i][0] != -1; i++) {
- + 				off = rsv_slots[i][0];
- + 				ln = rsv_slots[i][1];
- + 				set_bits(off, ln, edma_cc[j]->edma_inuse);
- + 			}
- + 		}
- + 
- + 		sprintf(irq_name, "edma%d", j);
- + 		irq[j] = platform_get_irq_byname(pdev, irq_name);
- + 		edma_cc[j]->irq_res_start = irq[j];
- + 		status = request_irq(irq[j], dma_irq_handler, 0, "edma",
- + 					&pdev->dev);
- + 		if (status < 0) {
- + 			dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
- + 				irq[j], status);
- + 			goto fail;
- + 		}
- + 
- + 		sprintf(irq_name, "edma%d_err", j);
- + 		err_irq[j] = platform_get_irq_byname(pdev, irq_name);
- + 		edma_cc[j]->irq_res_end = err_irq[j];
- + 		status = request_irq(err_irq[j], dma_ccerr_handler, 0,
- + 					"edma_error", &pdev->dev);
- + 		if (status < 0) {
- + 			dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
- + 				err_irq[j], status);
- + 			goto fail;
- + 		}
- + 
- + 		/* Everything lives on transfer controller 1 until otherwise
- + 		 * specified. This way, long transfers on the low priority queue
- + 		 * started by the codec engine will not cause audio defects.
- + 		 */
- + 		for (i = 0; i < edma_cc[j]->num_channels; i++)
- + 			map_dmach_queue(j, i, EVENTQ_1);
- + 
- + 		queue_tc_mapping = info[j].queue_tc_mapping;
- + 		queue_priority_mapping = info[j].queue_priority_mapping;
- + 
- + 		/* Event queue to TC mapping */
- + 		for (i = 0; queue_tc_mapping[i][0] != -1; i++)
- + 			map_queue_tc(j, queue_tc_mapping[i][0],
- + 					queue_tc_mapping[i][1]);
- + 
- + 		/* Event queue priority mapping */
- + 		for (i = 0; queue_priority_mapping[i][0] != -1; i++)
- + 			assign_priority_to_queue(j,
- + 						queue_priority_mapping[i][0],
- + 						queue_priority_mapping[i][1]);
- + 
- + 		/* Map the channel to param entry if channel mapping logic
- + 		 * exist
- + 		 */
- + 		if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST)
- + 			map_dmach_param(j);
- + 
- + 		for (i = 0; i < info[j].n_region; i++) {
- + 			edma_write_array2(j, EDMA_DRAE, i, 0, 0x0);
- + 			edma_write_array2(j, EDMA_DRAE, i, 1, 0x0);
- + 			edma_write_array(j, EDMA_QRAE, i, 0x0);
- + 		}
- + 
- + 		edma_cc[j]->is_xbar = info[j].is_xbar;
- + 
- + 		if (edma_cc[j]->is_xbar) {
- + 			edma_cc[j]->num_events = info[j].n_events;
- + 			edma_cc[j]->xbar_event_mapping =
- + 						info[j].xbar_event_mapping;
- + 			xbar_event_to_channel_map = info[j].map_xbar_channel;
- + 		}
- + 
- + 		arch_num_cc++;
- + 	}
- + 
- + 	return 0;
- + 
- + fail:
- + 	for (i = 0; i < EDMA_MAX_CC; i++) {
- + 		if (err_irq[i])
- + 			free_irq(err_irq[i], &pdev->dev);
- + 		if (irq[i])
- + 			free_irq(irq[i], &pdev->dev);
- + 	}
- + fail1:
- + 	for (i = 0; i < EDMA_MAX_CC; i++) {
- + 		if (r[i])
- + 			release_mem_region(r[i]->start, len[i]);
- + 		if (edmacc_regs_base[i])
- + 			iounmap(edmacc_regs_base[i]);
- + 		kfree(edma_cc[i]);
- + 	}
- + 	pm_runtime_put_sync(&pdev->dev);
- + 	pm_runtime_disable(&pdev->dev);
- + 	return status;
- + }
- + 
- + #ifdef CONFIG_PM
- + static int edma3_suspend(struct platform_device *pdev, pm_message_t state)
- + {
- + 	int i, j;
- + 
- + 	for (i = 0; i < arch_num_cc; i++) {
- + 		/* backup channel data */
- + 		for (j = 0; j < edma_cc[i]->num_channels; j++) {
- + 			edma_cc[i]->bkp_ch_map[j] = edma_read_array(i,
- + 							EDMA_DCHMAP, j);
- + 		}
- + 
- + 		/* backup DMA Queue Number */
- + 		for (j = 0; j < 8; j++) {
- + 			edma_cc[i]->bkp_que_num[j] = edma_read_array(i,
- + 							EDMA_DMAQNUM, j);
- + 		}
- + 
- + 		for (j = 0; j < edma_cc[i]->num_region; j++) {
- + 			/* backup DMA DMA Region Access Enable data */
- + 			edma_cc[i]->bkp_drae[j] = edma_read_array2(i,
- + 							EDMA_DRAE, j, 0);
- + 			edma_cc[i]->bkp_draeh[j] = edma_read_array2(i,
- + 							EDMA_DRAE, j, 1);
- + 
- + 			/* backup DMA QDMA Region Access Enable data */
- + 			edma_cc[i]->bkp_qrae[j] = edma_read_array(i,
- + 							EDMA_QRAE, j);
- + 		}
- + 
- + 		/* backup DMA shadow Event Set data */
- + 		edma_cc[i]->bkp_sh_esr = edma_shadow0_read_array(i, SH_ESR, 0);
- + 		edma_cc[i]->bkp_sh_esrh = edma_shadow0_read_array(i, SH_ESR, 1);
- + 
- + 		/* backup DMA Shadow Event Enable Set data */
- + 		edma_cc[i]->bkp_sh_eesr = edma_shadow0_read_array(i,
- + 							SH_EER, 0);
- + 		edma_cc[i]->bkp_sh_eesrh = edma_shadow0_read_array(i,
- + 							SH_EER, 1);
- + 
- + 		/* backup DMA Shadow Interrupt Enable Set data */
- + 		edma_cc[i]->bkp_sh_iesr = edma_shadow0_read_array(i,
- + 							SH_IER, 0);
- + 		edma_cc[i]->bkp_sh_iesrh = edma_shadow0_read_array(i,
- + 							SH_IER, 1);
- + 
- + 		edma_cc[i]->bkp_que_tc_map = edma_read(i, EDMA_QUETCMAP);
- + 
- + 		/* backup DMA Queue Priority data */
- + 		edma_cc[i]->bkp_que_pri = edma_read(i, EDMA_QUEPRI);
- + 
- + 		/* backup paramset */
- + 		for (j = 0; j < edma_cc[i]->num_slots; j++) {
- + 			memcpy_fromio(&edma_cc[i]->bkp_prm_set[j],
- + 				edmacc_regs_base[i] + PARM_OFFSET(j),
- + 				PARM_SIZE);
- + 		}
- + 	}
- + 
- + 	pm_runtime_put_sync(&pdev->dev);
- + 
- + 	return 0;
- + }
- + 
- + static int edma3_resume(struct platform_device *pdev)
- + {
- + 	int i, j;
- + 
- + 	pm_runtime_get_sync(&pdev->dev);
- + 
- + 	for (i = 0; i < arch_num_cc; i++) {
- + 
- + 		/* restore channel data */
- + 		for (j = 0; j < edma_cc[i]->num_channels; j++) {
- + 			edma_write_array(i, EDMA_DCHMAP, j,
- + 						edma_cc[i]->bkp_ch_map[j]);
- + 		}
- + 
- + 		/* restore DMA Queue Number */
- + 		for (j = 0; j < 8; j++) {
- + 			edma_write_array(i, EDMA_DMAQNUM, j,
- + 						edma_cc[i]->bkp_que_num[j]);
- + 		}
- + 
- + 		for (j = 0; j < edma_cc[i]->num_region; j++) {
- + 			/* restore DMA DMA Region Access Enable data */
- + 			edma_write_array2(i, EDMA_DRAE, j, 0,
- + 						edma_cc[i]->bkp_drae[j]);
- + 			edma_write_array2(i, EDMA_DRAE, j, 1,
- + 						edma_cc[i]->bkp_draeh[j]);
- + 
- + 			/* restore DMA QDMA Region Access Enable data */
- + 			edma_write_array(i, EDMA_QRAE, j,
- + 						edma_cc[i]->bkp_qrae[j]);
- + 		}
- + 
- + 		/* restore DMA shadow Event Set data */
- + 		edma_shadow0_write_array(i, SH_ESR, 0, edma_cc[i]->bkp_sh_esr);
- + 		edma_shadow0_write_array(i, SH_ESR, 1, edma_cc[i]->bkp_sh_esrh);
- + 
- + 		/* restore DMA Shadow Event Enable Set data */
- + 		edma_shadow0_write_array(i, SH_EESR, 0,
- + 						edma_cc[i]->bkp_sh_eesr);
- + 		edma_shadow0_write_array(i, SH_EESR, 1,
- + 						edma_cc[i]->bkp_sh_eesrh);
- + 
- + 		/* restore DMA Shadow Interrupt Enable Set data */
- + 		edma_shadow0_write_array(i, SH_IESR, 0,
- + 						edma_cc[i]->bkp_sh_iesr);
- + 		edma_shadow0_write_array(i, SH_IESR, 1,
- + 						edma_cc[i]->bkp_sh_iesrh);
- + 
- + 		edma_write(i, EDMA_QUETCMAP, edma_cc[i]->bkp_que_tc_map);
- + 
- + 		/* restore DMA Queue Priority data */
- + 		edma_write(i, EDMA_QUEPRI, edma_cc[i]->bkp_que_pri);
- + 
- + 		/* restore paramset */
- + 		for (j = 0; j < edma_cc[i]->num_slots; j++) {
- + 			memcpy_toio(edmacc_regs_base[i] + PARM_OFFSET(j),
- + 				&edma_cc[i]->bkp_prm_set[j], PARM_SIZE);
- + 		}
- + 	}
- + 
- + 	return 0;
- + }
- + 
- + #else
- + #define edma3_suspend	NULL
- + #define edma3_resume		NULL
- + #endif
- + 
- + static struct platform_driver edma_driver = {
- + 	.driver.name	= "edma",
- + 	.suspend	= edma3_suspend,
- + 	.resume		= edma3_resume,
- + };
- + 
- + static int __init edma_init(void)
- + {
- + 	return platform_driver_probe(&edma_driver, edma_probe);
- + }
- + subsys_initcall(edma_init);
- diff -crN linux-3.2.1_o/arch/arm/common/Makefile linux-3.2.1/arch/arm/common/Makefile
- *** linux-3.2.1_o/arch/arm/common/Makefile	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/arch/arm/common/Makefile	2014-05-15 13:25:13.672206508 +0900
- ***************
- *** 17,19 ****
- --- 17,20 ----
-   obj-$(CONFIG_ARCH_IXP23XX)	+= uengine.o
-   obj-$(CONFIG_PCI_HOST_ITE8152)  += it8152.o
-   obj-$(CONFIG_ARM_TIMER_SP804)	+= timer-sp.o
- + obj-$(CONFIG_OMAP3_EDMA)	+= edma.o
- diff -crN linux-3.2.1_o/arch/arm/include/asm/device.h linux-3.2.1/arch/arm/include/asm/device.h
- *** linux-3.2.1_o/arch/arm/include/asm/device.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/arch/arm/include/asm/device.h	2014-05-15 13:25:13.696197092 +0900
- ***************
- *** 18,24 ****
-   struct omap_device;
-   
-   struct pdev_archdata {
- ! #ifdef CONFIG_ARCH_OMAP
-   	struct omap_device *od;
-   #endif
-   };
- --- 18,24 ----
-   struct omap_device;
-   
-   struct pdev_archdata {
- ! #if defined(CONFIG_ARCH_OMAP) || defined(CONFIG_ARCH_CKB)
-   	struct omap_device *od;
-   #endif
-   };
- diff -crN linux-3.2.1_o/arch/arm/include/asm/pmu.h linux-3.2.1/arch/arm/include/asm/pmu.h
- *** linux-3.2.1_o/arch/arm/include/asm/pmu.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/arch/arm/include/asm/pmu.h	2014-05-15 13:25:13.703357958 +0900
- ***************
- *** 27,39 ****
-   /*
-    * struct arm_pmu_platdata - ARM PMU platform data
-    *
- !  * @handle_irq: an optional handler which will be called from the interrupt and
- !  * passed the address of the low level handler, and can be used to implement
- !  * any platform specific handling before or after calling it.
-    */
-   struct arm_pmu_platdata {
-   	irqreturn_t (*handle_irq)(int irq, void *dev,
-   				  irq_handler_t pmu_handler);
-   };
-   
-   #ifdef CONFIG_CPU_HAS_PMU
- --- 27,48 ----
-   /*
-    * struct arm_pmu_platdata - ARM PMU platform data
-    *
- !  * @handle_irq: an optional handler which will be called from the
- !  *	interrupt and passed the address of the low level handler,
- !  *	and can be used to implement any platform specific handling
- !  *	before or after calling it.
- !  * @enable_irq: an optional handler which will be called after
- !  *	request_irq and be used to handle some platform specific
- !  *	irq enablement
- !  * @disable_irq: an optional handler which will be called before
- !  *	free_irq and be used to handle some platform specific
- !  *	irq disablement
-    */
-   struct arm_pmu_platdata {
-   	irqreturn_t (*handle_irq)(int irq, void *dev,
-   				  irq_handler_t pmu_handler);
- + 	void (*enable_irq)(int irq);
- + 	void (*disable_irq)(int irq);
-   };
-   
-   #ifdef CONFIG_CPU_HAS_PMU
- diff -crN linux-3.2.1_o/arch/arm/include/asm/setup.h linux-3.2.1/arch/arm/include/asm/setup.h
- *** linux-3.2.1_o/arch/arm/include/asm/setup.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/arch/arm/include/asm/setup.h	2014-05-15 13:25:13.779252687 +0900
- ***************
- *** 43,48 ****
- --- 43,52 ----
-   	__u32	start;	/* physical start address */
-   };
-   
- + 
- + /* FB TAG */
- + #define ATAG_FB		0x54411002
- + 
-   /* VGA text type displays */
-   #define ATAG_VIDEOTEXT	0x54410003
-   
- ***************
- *** 225,230 ****
- --- 229,239 ----
-   extern void early_print(const char *str, ...);
-   extern void dump_machine_table(void);
-   
- + #ifdef CONFIG_MACH_CKB_3352
- + extern int ckb_add_fbaddr(phys_addr_t start, phys_addr_t size);
- + extern int ckb_add_vpifaddr(phys_addr_t start, phys_addr_t size);
- + #endif
- + 
-   #endif  /*  __KERNEL__  */
-   
-   #endif
- diff -crN linux-3.2.1_o/arch/arm/include/asm/unistd.h linux-3.2.1/arch/arm/include/asm/unistd.h
- *** linux-3.2.1_o/arch/arm/include/asm/unistd.h	2014-05-15 09:39:09.171917393 +0900
- --- linux-3.2.1/arch/arm/include/asm/unistd.h	2014-05-15 13:25:13.784249542 +0900
- ***************
- *** 404,409 ****
- --- 404,410 ----
-   #define __NR_setns			(__NR_SYSCALL_BASE+375)
-   #define __NR_process_vm_readv		(__NR_SYSCALL_BASE+376)
-   #define __NR_process_vm_writev		(__NR_SYSCALL_BASE+377)
- + #define __NR_ckb3352_change_mux		(__NR_SYSCALL_BASE+378)
-   
-   /*
-    * The following SWIs are ARM private.
- diff -crN linux-3.2.1_o/arch/arm/Kconfig linux-3.2.1/arch/arm/Kconfig
- *** linux-3.2.1_o/arch/arm/Kconfig	2014-05-15 09:39:09.191917472 +0900
- --- linux-3.2.1/arch/arm/Kconfig	2014-05-15 13:25:13.791316948 +0900
- ***************
- *** 938,949 ****
- --- 938,963 ----
-   	select ARCH_REQUIRE_GPIOLIB
-   	select ARCH_HAS_CPUFREQ
-   	select CLKSRC_MMIO
- + 	select GENERIC_ALLOCATOR
-   	select GENERIC_CLOCKEVENTS
-   	select HAVE_SCHED_CLOCK
-   	select ARCH_HAS_HOLES_MEMORYMODEL
-   	help
-   	  Support for TI's OMAP platform (OMAP1/2/3/4).
-   
- + config ARCH_CKB
- + 	bool "CKB (Computex Kumikomi Board)"
- + 	select HAVE_CLK
- + 	select ARCH_REQUIRE_GPIOLIB
- + 	select ARCH_HAS_CPUFREQ
- + 	select CLKSRC_MMIO
- + 	select GENERIC_ALLOCATOR
- + 	select GENERIC_CLOCKEVENTS
- + 	select HAVE_SCHED_CLOCK
- + 	select ARCH_HAS_HOLES_MEMORYMODEL
- + 	help
- + 	  Support for Computex Kumikomi Board.
- + 
-   config PLAT_SPEAR
-   	bool "ST SPEAr"
-   	select ARM_AMBA
- ***************
- *** 988,993 ****
- --- 1002,1009 ----
-   
-   source "arch/arm/mach-bcmring/Kconfig"
-   
- + source "arch/arm/mach-ckb_3352/Kconfig"
- + 
-   source "arch/arm/mach-clps711x/Kconfig"
-   
-   source "arch/arm/mach-cns3xxx/Kconfig"
- ***************
- *** 1035,1040 ****
- --- 1051,1057 ----
-   source "arch/arm/mach-netx/Kconfig"
-   
-   source "arch/arm/mach-nomadik/Kconfig"
- + 
-   source "arch/arm/plat-nomadik/Kconfig"
-   
-   source "arch/arm/plat-omap/Kconfig"
- diff -crN linux-3.2.1_o/arch/arm/Kconfig.debug linux-3.2.1/arch/arm/Kconfig.debug
- *** linux-3.2.1_o/arch/arm/Kconfig.debug	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/arch/arm/Kconfig.debug	2014-05-15 13:25:13.808288002 +0900
- ***************
- *** 271,274 ****
- --- 271,280 ----
-   	help
-   	  Perform tests of kprobes API and instruction set simulation.
-   
- + config DEBUG_JTAG_ENABLE
- + 	bool "Enable JTAG clock for debugger connectivity"
- + 	help
- + 	 Say Y here if you want to enable the JTAG clock to enable
- + 	 connectivity to a debugger
- + 
-   endmenu
- diff -crN linux-3.2.1_o/arch/arm/kernel/calls.S linux-3.2.1/arch/arm/kernel/calls.S
- *** linux-3.2.1_o/arch/arm/kernel/calls.S	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/arch/arm/kernel/calls.S	2014-05-15 13:25:13.823535245 +0900
- ***************
- *** 387,392 ****
- --- 387,393 ----
-   /* 375 */	CALL(sys_setns)
-   		CALL(sys_process_vm_readv)
-   		CALL(sys_process_vm_writev)
- + 		CALL(sys_ckb3352_change_mux)
-   #ifndef syscalls_counted
-   .equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls
-   #define syscalls_counted
- diff -crN linux-3.2.1_o/arch/arm/kernel/setup.c linux-3.2.1/arch/arm/kernel/setup.c
- *** linux-3.2.1_o/arch/arm/kernel/setup.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/arch/arm/kernel/setup.c	2014-05-15 13:25:13.843242062 +0900
- ***************
- *** 640,645 ****
- --- 640,654 ----
-   
-   __tagtable(ATAG_MEM, parse_tag_mem32);
-   
- + #ifdef CONFIG_MACH_CKB_3352
- + static int __init parse_tag_fb(const struct tag *tag)
- + {
- + 	return ckb_add_fbaddr(tag->u.mem.start, tag->u.mem.size);
- + }
- + 
- + __tagtable(ATAG_FB, parse_tag_fb);
- + #endif
- + 
-   #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
-   struct screen_info screen_info = {
-    .orig_video_lines	= 30,
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/am33xx-smartreflex-class2.c linux-3.2.1/arch/arm/mach-ckb_3352/am33xx-smartreflex-class2.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/am33xx-smartreflex-class2.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/am33xx-smartreflex-class2.c	2014-05-15 13:25:13.851764814 +0900
- ***************
- *** 0 ****
- --- 1,1061 ----
- + /*
- +  * SmartReflex Voltage Control driver
- +  *
- +  * Copyright (C) 2012 Texas Instruments, Inc. - http://www.ti.com/
- +  * Author: Greg Guyotte <gguyotte@ti.com> (modified for AM33xx)
- +  *
- +  * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
- +  * Author: AnilKumar Ch <anilkumar@ti.com>
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #include <linux/kernel.h>
- + #include <linux/init.h>
- + #include <linux/module.h>
- + #include <linux/interrupt.h>
- + #include <linux/clk.h>
- + #include <linux/io.h>
- + #include <linux/debugfs.h>
- + #include <linux/slab.h>
- + #include <linux/regulator/consumer.h>
- + #include <linux/cpufreq.h>
- + #include <linux/opp.h>
- + 
- + #include <plat/common.h>
- + #include <plat/smartreflex.h>
- + 
- + #include "control.h"
- + #include "voltage.h"
- + 
- + #define CLK_NAME_LEN		40
- + 
- + static inline void sr_write_reg(struct am33xx_sr *sr, int offset, u32 value,
- + 					u32 srid)
- + {
- + 	writel(value, sr->sen[srid].base + offset);
- + }
- + 
- + static inline void sr_modify_reg(struct am33xx_sr *sr, int offset, u32 mask,
- + 				u32 value, u32 srid)
- + {
- + 	u32 reg_val;
- + 
- + 	reg_val = readl(sr->sen[srid].base + offset);
- + 	reg_val &= ~mask;
- + 	reg_val |= (value&mask);
- + 
- + 	writel(reg_val, sr->sen[srid].base + offset);
- + }
- + 
- + static inline u32 sr_read_reg(struct am33xx_sr *sr, int offset, u32 srid)
- + {
- + 	return readl(sr->sen[srid].base + offset);
- + }
- + 
- + static void cal_reciprocal(u32 sensor, u32 *sengain, u32 *rnsen) {
- +          u32 gn, rn, mul;
- + 
- +          for (gn = 0; gn < GAIN_MAXLIMIT; gn++) {
- +                  mul = 1 << (gn + 8);
- +                  rn = mul / sensor;
- +                  if (rn < R_MAXLIMIT) {
- +                          *sengain = gn;
- +                          *rnsen = rn;
- +                  }
- +          }
- + }
- + 
- + static u32 cal_test_nvalue(u32 sennval, u32 senpval) {
- +          u32 senpgain=0, senngain=0;
- +          u32 rnsenp=0, rnsenn=0;
- + 
- +          /* Calculating the gain and reciprocal of the SenN and SenP values */
- +          cal_reciprocal(senpval, &senpgain, &rnsenp);
- +          cal_reciprocal(sennval, &senngain, &rnsenn);
- + 
- +          return (senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
- +                  (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
- +                  (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
- +                  (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT);
- + }
- + 
- + static unsigned int sr_adjust_efuse_nvalue(unsigned int opp_no,
- +                                                  unsigned int orig_opp_nvalue,
- +                                                  unsigned int mv_delta) {
- +          unsigned int new_opp_nvalue;
- +          unsigned int senp_gain, senn_gain, rnsenp, rnsenn, pnt_delta, nnt_delta;
- +          unsigned int new_senn, new_senp, senn, senp;
- + 
- +          /* calculate SenN and SenP from the efuse value */
- +          senp_gain = ((orig_opp_nvalue >> 20) & 0xf);
- +          senn_gain = ((orig_opp_nvalue >> 16) & 0xf);
- +          rnsenp = ((orig_opp_nvalue >> 8) & 0xff);
- +          rnsenn = (orig_opp_nvalue & 0xff);
- + 
- +          senp = ((1<<(senp_gain+8))/(rnsenp));
- +          senn = ((1<<(senn_gain+8))/(rnsenn));
- + 
- +          /* calculate the voltage delta */
- +          pnt_delta = (26 * mv_delta)/10;
- +          nnt_delta = (3 * mv_delta);
- + 
- +          /* now lets add the voltage delta to the sensor values */
- +          new_senn = senn + nnt_delta;
- +          new_senp = senp + pnt_delta;
- + 
- +          new_opp_nvalue = cal_test_nvalue(new_senn, new_senp);
- + 
- +          printk("Compensating OPP%d for %dmV Orig nvalue:0x%x New nvalue:0x%x \n",
- +                          opp_no, mv_delta, orig_opp_nvalue, new_opp_nvalue);
- + 
- +          return new_opp_nvalue;
- + }
- + 
- + /* irq_sr_reenable - Re-enable SR interrupts (triggered by delayed work queue)
- +  * @work:	pointer to work_struct embedded in am33xx_sr_sensor struct
- +  *
- +  * While servicing the IRQ, this function is added to the delayed work queue.
- +  * This gives time for the voltage change to settle before we re-enable
- +  * the interrupt.
- +  */
- + static void irq_sr_reenable(struct work_struct *work)
- + {
- +         u32 srid;
- + 	struct am33xx_sr_sensor *sens;
- +         struct am33xx_sr *sr;
- + 
- +         sens = container_of((void *)work, struct am33xx_sr_sensor,
- +                 work_reenable);
- + 
- +         srid = sens->sr_id;
- + 
- +         sr = container_of((void *)sens, struct am33xx_sr, sen[srid]);
- + 
- +         dev_dbg(&sr->pdev->dev, "%s: SR %d\n", __func__, srid);
- + 
- +         /* Must clear IRQ status */
- +         sens->irq_status = 0;
- + 
- +         /* Re-enable the interrupt */
- + 	sr_modify_reg(sr, IRQENABLE_SET, IRQENABLE_MCUBOUNDSINT,
- + 		IRQENABLE_MCUBOUNDSINT, srid);
- + 
- + 	/* Restart the module after voltage set */
- + 	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE,
- + 		SRCONFIG_SRENABLE, srid);
- + }
- + 
- + /* get_errvolt - get error voltage from SR error register
- +  * @sr:		contains SR driver data
- +  * @srid:	contains the srid, indicates which SR moduel lswe are using
- +  *
- +  * Read the error from SENSOR error register and then convert
- +  * to voltage delta, return value is the voltage delta in micro
- +  * volt.
- +  */
- + static int get_errvolt(struct am33xx_sr *sr, s32 srid)
- + {
- +         struct am33xx_sr_sensor *sens;
- + 	int senerror_reg;
- + 	s32 uvoltage;
- + 	s8 terror;
- + 
- +         sens = &sr->sen[srid];
- + 
- + 	senerror_reg = sr_read_reg(sr, SENERROR_V2, srid);
- + 	senerror_reg = (senerror_reg & 0x0000FF00);
- + 	terror = (s8)(senerror_reg >> 8);
- + 
- +         /* math defined in SR functional spec */
- + 	uvoltage = ((terror) * sr->uvoltage_step_size) >> 7;
- + 	uvoltage = uvoltage * sens->opp_data[sens->curr_opp].e2v_gain;
- + 
- + 	return uvoltage;
- + }
- + 
- + /* set_voltage - Schedule task for setting the voltage
- +  * @work:	pointer to the work structure
- +  *
- +  * Voltage is set based on previous voltage and calculated
- +  * voltage error.
- +  *
- +  * Generic voltage regulator set voltage is used for changing
- +  * the voltage to new value.  Could potentially use voltdm_scale
- +  * but at time of testing voltdm was not populated with volt_data.
- +  *
- +  * Disabling the module before changing the voltage, this is
- +  * needed for not generating interrupt during voltage change,
- +  * enabling after voltage change. This will also take care of
- +  * resetting the SR registers.
- +  */
- + static void set_voltage(struct work_struct *work)
- + {
- + 	struct am33xx_sr *sr;
- + 	int prev_volt, new_volt, i, ret;
- + 	s32 delta_v;
- + 
- + 	sr = container_of((void *)work, struct am33xx_sr, work);
- + 
- +         for (i = 0; i < sr->no_of_sens; i++) {
- +                 if (sr->sen[i].irq_status != 1)
- +                         continue;
- + 
- +                 /* Get the current voltage from PMIC */
- +                 prev_volt = regulator_get_voltage(sr->sen[i].reg);
- + 
- +                 if (prev_volt < 0) {
- +                         dev_err(&sr->pdev->dev,
- +                                 "%s: SR %d: regulator_get_voltage error %d\n",
- +                                 __func__, i, prev_volt);
- + 
- +                         goto reenable;
- +                 }
- + 
- +         	delta_v = get_errvolt(sr, i);
- +                 new_volt = prev_volt + delta_v;
- + 
- +                 /* this is the primary output for debugging SR activity */
- +                 dev_dbg(&sr->pdev->dev,
- +                         "%s: SR %d: prev volt=%d, delta_v=%d, req_volt=%d\n",
- +                          __func__, i, prev_volt, delta_v, new_volt);
- + 
- + 	        /* Clear the counter, SR module disable */
- + 	        sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE,
- + 			~SRCONFIG_SRENABLE, i);
- + 
- +                 if (delta_v != 0) {
- + 	                ret = regulator_set_voltage(sr->sen[i].reg, new_volt,
- +                                 new_volt + sr->uvoltage_step_size);
- + 
- +                         if (ret < 0)
- +                                 dev_err(&sr->pdev->dev,
- +                                 "%s: regulator_set_voltage failed! (err %d)\n",
- +                                 __func__, ret);
- +                 }
- + reenable:
- +                 /* allow time for voltage to settle before re-enabling SR
- +                    module and interrupt */
- +                 schedule_delayed_work(&sr->sen[i].work_reenable,
- +                         msecs_to_jiffies(sr->irq_delay));
- +         }
- + }
- + 
- + /* sr_class2_irq - sr irq handling
- +  * @irq:	Number of the irq serviced
- +  * @data:	data contains the SR driver structure
- +  *
- +  * Smartreflex IRQ handling for class2 IP, once the IRQ handler
- +  * is here then disable the interrupt and re-enable after some
- +  * time. This is the work around for handling both interrupts,
- +  * while one got satisfied with the voltage change but not the
- +  * other. The same logic helps the case where PMIC cannot set
- +  * the exact voltage requested by SR IP
- +  *
- +  * Schedule work only if both interrupts are serviced
- +  *
- +  * Note that same irq handler is used for both the interrupts,
- +  * needed for decision making for voltage change
- +  */
- + static irqreturn_t sr_class2_irq(int irq, void *data)
- + {
- + 	u32 srid;
- +         struct am33xx_sr *sr;
- +         struct am33xx_sr_sensor *sr_sensor = (struct am33xx_sr_sensor *)data;
- + 
- +         srid = sr_sensor->sr_id;
- + 
- +         sr = container_of(data, struct am33xx_sr, sen[srid]);
- + 
- + 	sr->sen[srid].irq_status = 1;
- + 
- + 	/* Clear MCUBounds Interrupt */
- + 	sr_modify_reg(sr, IRQSTATUS, IRQSTATUS_MCBOUNDSINT,
- + 			IRQSTATUS_MCBOUNDSINT, srid);
- + 
- + 	/* Disable the interrupt and re-enable in set_voltage() */
- + 	sr_modify_reg(sr, IRQENABLE_CLR, IRQENABLE_MCUBOUNDSINT,
- + 			IRQENABLE_MCUBOUNDSINT, srid);
- + 
- +         /* Causes set_voltage() to get called at a later time.  Set_voltage()
- +            will check the irq_status flags to determine which SR needs to
- +            be serviced.  This was previously done with schedule_work, but
- +            I observed a crash in set_voltage() when changing OPPs on weak
- +            silicon, which may have been related to insufficient voltage
- +            settling time for OPP change.  This additional delay avoids the
- +            crash. */
- +         schedule_delayed_work(&sr->work,
- +                         msecs_to_jiffies(250));
- + 
- + 	return IRQ_HANDLED;
- + }
- + 
- + static int sr_clk_enable(struct am33xx_sr *sr, u32 srid)
- + {
- + 	if (clk_enable(sr->sen[srid].fck) != 0) {
- + 		dev_err(&sr->pdev->dev, "%s: Could not enable sr_fck\n",
- + 					__func__);
- + 		return -EINVAL;
- + 	}
- + 
- + 	return 0;
- + }
- + 
- + static int sr_clk_disable(struct am33xx_sr *sr, u32 srid)
- + {
- + 	clk_disable(sr->sen[srid].fck);
- + 
- + 	return 0;
- + }
- + 
- + static inline int sr_set_nvalues(struct am33xx_sr *sr, u32 srid)
- + {
- +         int i;
- +         struct am33xx_sr_sensor *sens = &sr->sen[srid];
- + 
- +         for (i = 0; i < sens->no_of_opps; i++) {
- +         	/* Read nTarget value form EFUSE register*/
- + 	        sens->opp_data[i].nvalue = readl(AM33XX_CTRL_REGADDR
- + 			(sens->opp_data[i].efuse_offs)) & 0xFFFFFF;
- + 
- +                 /* validate nTarget value */
- +                 if (sens->opp_data[i].nvalue == 0)
- +                         return -EINVAL;
- + 
- +                 /* adjust nTarget based on margin in mv */
- +                 sens->opp_data[i].adj_nvalue = sr_adjust_efuse_nvalue(i,
- +                         sens->opp_data[i].nvalue,
- +                         sens->opp_data[i].margin);
- + 
- +                 dev_dbg(&sr->pdev->dev,
- +                         "NValueReciprocal value (from efuse) = %08x\n",
- +                         sens->opp_data[i].nvalue);
- + 
- +                 dev_dbg(&sr->pdev->dev,
- +                         "Adjusted NValueReciprocal value = %08x\n",
- +                         sens->opp_data[i].adj_nvalue);
- +         }
- + 	return 0;
- + }
- + 
- + /* sr_configure - Configure SR module to work in Error generator mode
- +  * @sr:		contains SR driver data
- +  * @srid:	contains the srid, specify whether it is CORE or MPU
- +  *
- +  * Configure the corresponding values to SR module registers for
- +  * operating SR module in Error Generator mode.
- +  */
- + static void sr_configure(struct am33xx_sr *sr, u32 srid)
- + {
- +         struct am33xx_sr_sensor *sens = &sr->sen[srid];
- + 
- + 	/* Configuring the SR module with clock length, enabling the
- + 	 * error generator, enable SR module, enable individual N and P
- + 	 * sensors
- + 	 */
- + 	sr_write_reg(sr, SRCONFIG, (SRCLKLENGTH_125MHZ_SYSCLK |
- + 		SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN |
- + 		(sens->senn_en << SRCONFIG_SENNENABLE_V2_SHIFT) |
- + 		(sens->senp_en << SRCONFIG_SENPENABLE_V2_SHIFT)),
- + 		srid);
- + 
- + 	/* Configuring the Error Generator */
- + 	sr_modify_reg(sr, ERRCONFIG_V2, (SR_ERRWEIGHT_MASK |
- + 		SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
- + 		((sens->opp_data[sens->curr_opp].err_weight <<
- +                         ERRCONFIG_ERRWEIGHT_SHIFT) |
- + 		(sens->opp_data[sens->curr_opp].err_maxlimit <<
- +                         ERRCONFIG_ERRMAXLIMIT_SHIFT) |
- + 		(sens->opp_data[sens->curr_opp].err_minlimit <<
- +                         ERRCONFIG_ERRMINLIMIT_SHIFT)),
- + 		srid);
- + }
- + 
- + /* sr_enable - Enable SR module
- +  * @sr:		contains SR driver data
- +  * @srid:	contains the srid, specify whether it is CORE or MPU
- +  *
- +  * Enable SR module by writing nTarget values to corresponding SR
- +  * NVALUERECIPROCAL register, enable the interrupt and enable SR
- +  */
- + static void sr_enable(struct am33xx_sr *sr, u32 srid)
- + {
- +         struct am33xx_sr_sensor *sens;
- + 
- +         sens = &sr->sen[srid];
- + 
- + 	/* Check if SR is already enabled. If yes do nothing */
- + 	if (sr_read_reg(sr, SRCONFIG, srid) & SRCONFIG_SRENABLE)
- + 		return;
- + 
- + 	if (sens->opp_data[sens->curr_opp].nvalue == 0)
- + 		dev_err(&sr->pdev->dev,
- +                         "%s: OPP doesn't support SmartReflex\n", __func__);
- + 
- + 	/* Writing the nReciprocal value to the register */
- + 	sr_write_reg(sr, NVALUERECIPROCAL,
- +                 sens->opp_data[sens->curr_opp].adj_nvalue, srid);
- + 
- + 	/* Enable the interrupt */
- + 	sr_modify_reg(sr, IRQENABLE_SET, IRQENABLE_MCUBOUNDSINT,
- + 				IRQENABLE_MCUBOUNDSINT, srid);
- + 
- + 	/* SRCONFIG - enable SR */
- + 	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE,
- + 				SRCONFIG_SRENABLE, srid);
- + }
- + 
- + /* sr_disable - Disable SR module
- +  * @sr:		contains SR driver data
- +  * @srid:	contains the srid, specify whether it is CORE or MPU
- +  *
- +  * Disable SR module by disabling the interrupt and Smartreflex module
- +  */
- + static void sr_disable(struct am33xx_sr *sr, u32 srid)
- + {
- + 	/* Disable the interrupt */
- + 	sr_modify_reg(sr, IRQENABLE_CLR, IRQENABLE_MCUBOUNDSINT,
- + 				IRQENABLE_MCUBOUNDSINT, srid);
- + 
- + 	/* SRCONFIG - disable SR */
- + 	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE,
- + 				~SRCONFIG_SRENABLE, srid);
- + }
- + 
- + /* sr_start_vddautocomp - Start VDD auto compensation
- +  * @sr:		contains SR driver data
- +  *
- +  * This is the starting point for AVS enable from user space.
- +  * Also used to re-enable SR after OPP change.
- +  */
- + static void sr_start_vddautocomp(struct am33xx_sr *sr)
- + {
- + 	int i;
- + 
- + 	if ((sr->sen[SR_CORE].opp_data[0].nvalue == 0) ||
- +                 (sr->sen[SR_MPU].opp_data[0].nvalue == 0)) {
- + 		dev_err(&sr->pdev->dev, "SR module not enabled, nTarget"
- + 					" values are not found\n");
- + 		return;
- + 	}
- + 
- + 	if (sr->autocomp_active == 1) {
- + 		dev_warn(&sr->pdev->dev, "SR VDD autocomp already active\n");
- + 		return;
- + 	}
- + 
- + 	for (i = 0; i < sr->no_of_sens; i++) {
- +                	/* Read current regulator value and voltage */
- + 	        sr->sen[i].init_volt_mv = regulator_get_voltage(sr->sen[i].reg);
- + 
- +                 dev_dbg(&sr->pdev->dev, "%s: regulator %d, init_volt = %d\n",
- +                         __func__, i, sr->sen[i].init_volt_mv);
- + 
- + 		if (sr_clk_enable(sr, i))
- +                         return;
- + 		sr_configure(sr, i);
- + 		sr_enable(sr, i);
- + 	}
- + 
- + 	sr->autocomp_active = 1;
- + }
- + 
- + /* sr_stop_vddautocomp - Stop VDD auto compensation
- +  * @sr:		contains SR driver data
- +  *
- +  * This is the ending point during SR disable from user space.
- +  * Also used to disable SR after OPP change.
- +  */
- + static void sr_stop_vddautocomp(struct am33xx_sr *sr)
- + {
- + 	int i;
- + 
- + 	if (sr->autocomp_active == 0) {
- + 		dev_warn(&sr->pdev->dev, "SR VDD autocomp is not active\n");
- + 		return;
- + 	}
- + 
- +         /* cancel bottom half interrupt handlers that haven't run yet */
- + 	cancel_delayed_work_sync(&sr->work);
- + 
- + 	for (i = 0; i < sr->no_of_sens; i++) {
- +                 /* cancel any outstanding SR IRQ re-enables on work queue */
- +                 cancel_delayed_work_sync(&sr->sen[i].work_reenable);
- + 		sr_disable(sr, i);
- + 		sr_clk_disable(sr, i);
- + 	}
- + 
- + 	sr->autocomp_active = 0;
- + }
- + 
- + /* am33xx_sr_autocomp_show - Store user input value and stop SR
- +  * @data:		contains SR driver data
- +  * @val:		pointer to store autocomp_active status
- +  *
- +  * This is the Debug Fs enteries to show whether SR is enabled
- +  * or disabled
- +  */
- + static int am33xx_sr_autocomp_show(void *data, u64 *val)
- + {
- + 	struct am33xx_sr *sr_info = (struct am33xx_sr *) data;
- + 
- + 	*val = (u64) sr_info->autocomp_active;
- + 
- + 	return 0;
- + }
- + 
- + static int am33xx_sr_margin_show(void *data, u64 *val)
- + {
- +         struct am33xx_sr_opp_data *sr_opp_data = (struct am33xx_sr_opp_data *)data;
- + 
- + 	*val = (u64) sr_opp_data->margin;
- + 
- + 	return 0;
- + }
- + 
- + static int am33xx_sr_margin_update(void *data, u64 val)
- + {
- +         struct am33xx_sr_opp_data *sr_opp_data =
- +                 (struct am33xx_sr_opp_data *)data;
- +         struct am33xx_sr_sensor *sr_sensor;
- +         struct am33xx_sr *sr_info;
- + 
- +         /* work back to the sr_info pointer */
- +         sr_sensor = container_of((void *)sr_opp_data, struct am33xx_sr_sensor,
- +                 opp_data[sr_opp_data->opp_id]);
- + 
- +         sr_info = container_of((void *)sr_sensor, struct am33xx_sr,
- +                 sen[sr_sensor->sr_id]);
- + 
- +         /* store the value of margin */
- +         sr_opp_data->margin = (s32)val;
- + 
- +         dev_warn(&sr_info->pdev->dev, "%s: new margin=%d, srid=%d, opp=%d\n",
- +                 __func__, sr_opp_data->margin, sr_sensor->sr_id,
- +                 sr_opp_data->opp_id);
- + 
- +         /* updata ntarget values based upon new margin */
- +         if (sr_set_nvalues(sr_info, sr_sensor->sr_id) == -EINVAL)
- +                 dev_err(&sr_info->pdev->dev,
- +                         "%s: Zero NValue read from EFUSE\n", __func__);
- + 
- +         /* restart SmartReflex to adapt to new values */
- +         sr_stop_vddautocomp(sr_info);
- +         sr_start_vddautocomp(sr_info);
- + 
- +         return 0;
- + }
- + 
- + /* am33xx_sr_autocomp_store - Store user input and start SR
- +  * @data:		contains SR driver data
- +  * @val:		contains the value pased by user
- +  *
- +  * This is the Debug Fs enteries to store user input and
- +  * enable smartreflex.
- +  */
- + static int am33xx_sr_autocomp_store(void *data, u64 val)
- + {
- + 	struct am33xx_sr *sr_info = (struct am33xx_sr *) data;
- + 
- + 	/* Sanity check */
- + 	if (val && (val != 1)) {
- + 		dev_warn(&sr_info->pdev->dev, "%s: Invalid argument %llu\n",
- + 		        __func__, val);
- + 		return -EINVAL;
- + 	}
- + 
- + 	if (!val) {
- +                 sr_info->disabled_by_user = 1;
- + 		sr_stop_vddautocomp(sr_info);
- +         }
- + 	else {
- +                 sr_info->disabled_by_user = 0;
- + 		sr_start_vddautocomp(sr_info);
- +         }
- + 
- + 	return 0;
- + }
- + 
- + DEFINE_SIMPLE_ATTRIBUTE(sr_fops, am33xx_sr_autocomp_show,
- + 		am33xx_sr_autocomp_store, "%llu\n");
- + 
- + /* sr_curr_volt_show - Show current voltage value
- +  * @data:		contains SR driver data
- +  * @val:		pointer to store current voltage value
- +  *
- +  * Read the current voltage value and display the same on console
- +  * This is used in debugfs entries
- +  */
- + static int am33xx_sr_curr_volt_show(void *data, u64 *val)
- + {
- + 	struct am33xx_sr_sensor *sr_sensor = (struct am33xx_sr_sensor *) data;
- + 
- + 	*val = (u64) regulator_get_voltage(sr_sensor->reg);
- + 
- + 	return 0;
- + }
- + 
- + DEFINE_SIMPLE_ATTRIBUTE(curr_volt_fops, am33xx_sr_curr_volt_show,
- + 		NULL, "%llu\n");
- + 
- + DEFINE_SIMPLE_ATTRIBUTE(margin_fops, am33xx_sr_margin_show,
- + 		am33xx_sr_margin_update, "%llu\n");
- + 
- + #ifdef CONFIG_DEBUG_FS
- + /* sr_debugfs_entries - Create debugfs entries
- +  * @sr_info:		contains SR driver data
- +  *
- +  * Create debugfs entries, which is exposed to user for knowing
- +  * the current status. Some of the parameters can change during
- +  * run time
- +  */
- + static int sr_debugfs_entries(struct am33xx_sr *sr_info)
- + {
- +         struct am33xx_sr_sensor *sens;
- + 	struct dentry *dbg_dir, *sen_dir, *opp_dir;
- + 	int i, j;
- + 
- + 	dbg_dir = debugfs_create_dir("smartreflex", NULL);
- + 	if (IS_ERR(dbg_dir)) {
- + 		dev_err(&sr_info->pdev->dev, "%s: Unable to create debugfs"
- + 				" directory\n", __func__);
- + 		return PTR_ERR(dbg_dir);
- + 	}
- + 
- + 	(void) debugfs_create_file("autocomp", S_IRUGO | S_IWUGO, dbg_dir,
- + 				(void *)sr_info, &sr_fops);
- +         (void) debugfs_create_u32("interrupt_delay", S_IRUGO | S_IWUGO,
- + 				dbg_dir, &sr_info->irq_delay);
- + 
- + 	for (i = 0; i < sr_info->no_of_sens; i++) {
- +                 sens = &sr_info->sen[i];
- + 		sen_dir = debugfs_create_dir(sens->name, dbg_dir);
- + 		if (IS_ERR(sen_dir)) {
- + 			dev_err(&sr_info->pdev->dev, "%s: Unable to create"
- + 				" debugfs directory\n", __func__);
- + 			return PTR_ERR(sen_dir);
- + 		}
- + 
- +                 (void)debugfs_create_u32("initial_voltage", S_IRUGO, sen_dir,
- + 				&sens->init_volt_mv);
- + 	        (void)debugfs_create_file("current_voltage", S_IRUGO, sen_dir,
- + 				(void *)sens, &curr_volt_fops);
- + 
- +                 for (j = 0; j < sr_info->sen[i].no_of_opps; j++) {
- +                         char tmp[20];
- + 
- +                         sprintf(&tmp[0], "opp%d", j);
- +                         opp_dir = debugfs_create_dir(tmp, sen_dir);
- +                         if (IS_ERR(opp_dir)) {
- +         			dev_err(&sr_info->pdev->dev,
- +                                         "%s: Unable to create debugfs directory\n",
- +                                         __func__);
- +         			return PTR_ERR(opp_dir);
- +         		}
- + 
- +                         (void)debugfs_create_file("margin", S_IRUGO | S_IWUGO,
- + 	        	       opp_dir, (void *)&sens->opp_data[j],
- +                                &margin_fops);
- +                         (void)debugfs_create_x32("err2voltgain",
- +                                S_IRUGO | S_IWUGO,
- +         		       opp_dir,
- +                                &sens->opp_data[j].e2v_gain);
- +         		(void)debugfs_create_x32("nvalue", S_IRUGO,
- +         		       opp_dir,
- +                                &sens->opp_data[j].nvalue);
- +                         (void)debugfs_create_x32("adj_nvalue", S_IRUGO,
- +         		       opp_dir,
- +                                &sens->opp_data[j].adj_nvalue);
- +                 }
- + 	}
- + 	return 0;
- + }
- + #else
- + static int sr_debugfs_entries(struct am33xx_sr *sr_info)
- + {
- + 	return 0;
- + }
- + #endif
- + 
- + #ifdef CONFIG_CPU_FREQ
- + 
- + /* Find and return current OPP.  This should change to use system APIs,
- +    but voltdm is not currently populated, and opp APIs are also not working. */
- + static int get_current_opp(struct am33xx_sr *sr, u32 srid, u32 freq)  {
- +         int i;
- + 
- +         for (i = 0; i < sr->sen[srid].no_of_opps; i++) {
- +                 if (sr->sen[srid].opp_data[i].frequency == freq)
- +                         return i;
- +         }
- + 
- +         return -EINVAL;
- + }
- + 
- + static int am33xx_sr_cpufreq_transition(struct notifier_block *nb,
- + 					  unsigned long val, void *data)
- + {
- +         struct am33xx_sr *sr;
- +         struct cpufreq_freqs *cpu;
- + 
- + 	sr = container_of(nb, struct am33xx_sr, freq_transition);
- + 
- +         /* We are required to disable SR while OPP change is occurring */
- + 	if (val == CPUFREQ_PRECHANGE) {
- +                 dev_dbg(&sr->pdev->dev, "%s: prechange\n", __func__);
- +                 sr_stop_vddautocomp(sr);
- + 	} else if (val == CPUFREQ_POSTCHANGE) {
- +                 cpu = (struct cpufreq_freqs *)data;
- +                 dev_dbg(&sr->pdev->dev,
- +                         "%s: postchange, cpu=%d, old=%d, new=%d\n",
- +                         __func__, cpu->cpu, cpu->old, cpu->new);
- + 
- +                 /* update current OPP */
- +                 sr->sen[SR_MPU].curr_opp = get_current_opp(sr, SR_MPU,
- +                         cpu->new*1000);
- +                 if (sr->sen[SR_MPU].curr_opp == -EINVAL) {
- +                         dev_err(&sr->pdev->dev, "%s: cannot determine opp\n",
- +                                 __func__);
- +                         return -EINVAL;
- +                 }
- + 
- +                 dev_dbg(&sr->pdev->dev, "%s: postchange, new opp=%d\n",
- +                         __func__, sr->sen[SR_MPU].curr_opp);
- + 
- +                 /* this handles the case when the user has disabled SR via
- +                    debugfs, therefore we do not want to enable SR */
- +                 if (sr->disabled_by_user == 0)
- +                         sr_start_vddautocomp(sr);
- + 	}
- + 
- + 	return 0;
- + }
- + 
- + static inline int am33xx_sr_cpufreq_register(struct am33xx_sr *sr)
- + {
- +         sr->freq_transition.notifier_call = am33xx_sr_cpufreq_transition;
- + 
- + 	return cpufreq_register_notifier(&sr->freq_transition,
- + 					 CPUFREQ_TRANSITION_NOTIFIER);
- + }
- + 
- + static inline void am33xx_sr_cpufreq_deregister(struct am33xx_sr *sr)
- + {
- + 	cpufreq_unregister_notifier(&sr->freq_transition,
- + 				    CPUFREQ_TRANSITION_NOTIFIER);
- + }
- + 
- + #endif
- + 
- + static int __init am33xx_sr_probe(struct platform_device *pdev)
- + {
- + 	struct am33xx_sr *sr_info;
- + 	struct am33xx_sr_platform_data *pdata;
- + 	struct resource *res[MAX_SENSORS];
- + 	int irq;
- + 	int ret;
- + 	int i,j;
- + 
- + 	if (omap_rev() != AM335X_REV_ES1_0) {
- + 		dev_err(&pdev->dev, "%s: Smartreflex requires ES 1.0\n",
- + 		       	__func__);
- + 		return -EINVAL;
- + 	}
- + 
- + 	sr_info = kzalloc(sizeof(struct am33xx_sr), GFP_KERNEL);
- + 	if (!sr_info) {
- + 		dev_err(&pdev->dev, "%s: unable to allocate sr_info\n",
- + 					__func__);
- + 		return -ENOMEM;
- + 	}
- + 
- + 	pdata = pdev->dev.platform_data;
- + 	if (!pdata) {
- + 		dev_err(&pdev->dev, "%s: platform data missing\n", __func__);
- + 		ret = -EINVAL;
- + 		goto err_free_sr_info;
- + 	}
- + 
- + 	sr_info->pdev = pdev;
- + 	sr_info->sen[SR_CORE].name = "smartreflex0";
- + 	sr_info->sen[SR_MPU].name = "smartreflex1";
- + 	sr_info->ip_type = pdata->ip_type;
- +         sr_info->irq_delay = pdata->irq_delay;
- +         sr_info->no_of_sens = pdata->no_of_sens;
- +         sr_info->no_of_vds = pdata->no_of_vds;
- + 	sr_info->uvoltage_step_size = pdata->vstep_size_uv;
- + 	sr_info->autocomp_active = false;
- +         sr_info->disabled_by_user = false;
- + 
- + 	for (i = 0; i < sr_info->no_of_sens; i++) {
- +                 u32 curr_freq=0;
- + 
- +                 sr_info->sen[i].reg_name = pdata->vd_name[i];
- + 
- +                 /* this should be determined from voltdm or opp layer, but
- +                    those approaches are not working */
- +                 sr_info->sen[i].no_of_opps = pdata->sr_sdata[i].no_of_opps;
- +                 sr_info->sen[i].sr_id = i;
- + 
- +                 /* Reading per OPP Values */
- +                 for (j = 0; j < sr_info->sen[i].no_of_opps; j++) {
- +         		sr_info->sen[i].opp_data[j].efuse_offs =
- +                                 pdata->sr_sdata[i].sr_opp_data[j].efuse_offs;
- +                         sr_info->sen[i].opp_data[j].e2v_gain =
- +                                 pdata->sr_sdata[i].sr_opp_data[j].e2v_gain;
- +         		sr_info->sen[i].opp_data[j].err_weight =
- +                                 pdata->sr_sdata[i].sr_opp_data[j].err_weight;
- +         		sr_info->sen[i].opp_data[j].err_minlimit =
- +                                 pdata->sr_sdata[i].sr_opp_data[j].err_minlimit;
- +         		sr_info->sen[i].opp_data[j].err_maxlimit =
- +                                 pdata->sr_sdata[i].sr_opp_data[j].err_maxlimit;
- +                         sr_info->sen[i].opp_data[j].margin =
- +                                 pdata->sr_sdata[i].sr_opp_data[j].margin;
- +                         sr_info->sen[i].opp_data[j].nominal_volt =
- +                                 pdata->sr_sdata[i].sr_opp_data[j].nominal_volt;
- +                         sr_info->sen[i].opp_data[j].frequency =
- +                                 pdata->sr_sdata[i].sr_opp_data[j].frequency;
- +                         sr_info->sen[i].opp_data[j].opp_id = j;
- +                 }
- + 
- +                 if (i == SR_MPU) {
- +                         /* hardcoded CPU NR */
- +                         curr_freq = cpufreq_get(0);
- + 
- +                         /* update current OPP */
- +                         sr_info->sen[i].curr_opp = get_current_opp(sr_info, i,
- +                                         curr_freq*1000);
- +                         if (sr_info->sen[i].curr_opp == -EINVAL) {
- +                                 dev_err(&sr_info->pdev->dev,
- +                                         "%s: cannot determine opp\n",__func__);
- +                                 ret = -EINVAL;
- +                                 goto err_free_sr_info;
- +                         }
- +                 } else {
- +                         sr_info->sen[i].curr_opp =
- +                                 pdata->sr_sdata[i].default_opp;
- +                 }
- + 
- +                 dev_dbg(&pdev->dev,
- +                         "%s: SR%d, curr_opp=%d, no_of_opps=%d, step_size=%d\n",
- +                         __func__, i, sr_info->sen[i].curr_opp,
- +                         sr_info->sen[i].no_of_opps,
- +                         sr_info->uvoltage_step_size);
- + 
- +                 ret = sr_set_nvalues(sr_info, i);
- +                 if (ret == -EINVAL) {
- +                         dev_err(&sr_info->pdev->dev,
- +                                 "%s: Zero NValue read from EFUSE\n", __func__);
- +                         goto err_free_sr_info;
- +                 }
- + 
- +                 INIT_DELAYED_WORK(&sr_info->sen[i].work_reenable,
- +                         irq_sr_reenable);
- + 
- + 		sr_info->res_name[i] = kzalloc(CLK_NAME_LEN + 1, GFP_KERNEL);
- + 
- + 		/* resources */
- + 		res[i] = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- + 					sr_info->sen[i].name);
- + 		if (!res[i]) {
- + 			dev_err(&pdev->dev, "%s: no mem resource\n", __func__);
- + 			ret = -ENOENT;
- + 			goto err_free_mem;
- + 		}
- + 
- + 		irq = platform_get_irq_byname(pdev, sr_info->sen[i].name);
- + 		if (irq < 0) {
- + 			dev_err(&pdev->dev, "Can't get interrupt resource\n");
- + 			ret = irq;
- + 			goto err_free_mem;
- + 		}
- + 		sr_info->sen[i].irq = irq;
- + 
- + 		res[i] = request_mem_region(res[i]->start,
- + 				resource_size(res[i]), pdev->name);
- + 		if (!res[i]) {
- + 			dev_err(&pdev->dev, "can't request mem region\n");
- + 			ret = -EBUSY;
- + 			goto err_free_mem;
- + 		}
- + 
- + 		sr_info->sen[i].base = ioremap(res[i]->start,
- + 				resource_size(res[i]));
- + 		if (!sr_info->sen[i].base) {
- + 			dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
- + 			ret = -ENOMEM;
- + 			goto err_release_mem;
- + 		}
- + 
- + 		strcat(sr_info->res_name[i], sr_info->sen[i].name);
- + 		strcat(sr_info->res_name[i], "_fck");
- + 
- + 		sr_info->sen[i].fck = clk_get(NULL, sr_info->res_name[i]);
- + 		if (IS_ERR(sr_info->sen[i].fck)) {
- + 			dev_err(&pdev->dev, "%s: Could not get sr fck\n",
- + 						__func__);
- + 			ret = PTR_ERR(sr_info->sen[i].fck);
- + 			goto err_unmap;
- + 		}
- + 
- + 		ret = request_irq(sr_info->sen[i].irq, sr_class2_irq,
- + 			IRQF_DISABLED, sr_info->sen[i].name,
- +                         (void *)&sr_info->sen[i]);
- + 		if (ret) {
- + 			dev_err(&pdev->dev, "%s: Could not install SR ISR\n",
- + 						__func__);
- + 			goto err_put_clock;
- + 		}
- + 
- + 		sr_info->sen[i].senn_en = pdata->sr_sdata[i].senn_mod;
- + 		sr_info->sen[i].senp_en = pdata->sr_sdata[i].senp_mod;
- + 
- +                 sr_info->sen[i].reg =
- +                         regulator_get(NULL, sr_info->sen[i].reg_name);
- +                	if (IS_ERR(sr_info->sen[i].reg)) {
- +                         ret = -EINVAL;
- + 	                goto err_free_irq;
- +                 }
- + 
- +                	/* Read current regulator value and voltage */
- + 	        sr_info->sen[i].init_volt_mv =
- +                         regulator_get_voltage(sr_info->sen[i].reg);
- + 
- +                 dev_dbg(&pdev->dev, "%s: regulator %d, init_volt = %d\n",
- +                         __func__, i, sr_info->sen[i].init_volt_mv);
- + 	} /* for() */
- + 
- +         /* set_voltage() will be used as the bottom half IRQ handler */
- + 	INIT_DELAYED_WORK(&sr_info->work, set_voltage);
- + 
- + #ifdef CONFIG_CPU_FREQ
- + 	ret = am33xx_sr_cpufreq_register(sr_info);
- + 	if (ret) {
- + 		dev_err(&pdev->dev, "failed to register cpufreq\n");
- + 		goto err_reg_put;
- + 	}
- + #endif
- + 
- + 	/* debugfs entries */
- + 	ret = sr_debugfs_entries(sr_info);
- + 	if (ret)
- + 		dev_warn(&pdev->dev, "%s: Debugfs entries are not created\n",
- + 						__func__);
- + 
- + 	platform_set_drvdata(pdev, sr_info);
- + 
- + 	dev_info(&pdev->dev, "%s: Driver initialized\n", __func__);
- + 
- +         /* disabled_by_user used to ensure SR doesn't come on via CPUFREQ
- +            scaling if user has disabled SR via debugfs on enable_on_init */
- + 	if (pdata->enable_on_init)
- + 		sr_start_vddautocomp(sr_info);
- +         else
- +                 sr_info->disabled_by_user = 1;
- + 
- + 	return ret;
- + 
- + #ifdef CONFIG_CPU_FREQ
- + 	am33xx_sr_cpufreq_deregister(sr_info);
- + #endif
- + 
- + err_reg_put:
- +         i--; /* back up i by one to walk back through the for loop */
- +         regulator_put(sr_info->sen[i].reg);
- + err_free_irq:
- + 	free_irq(sr_info->sen[i].irq, (void *)sr_info);
- + err_put_clock:
- + 	clk_put(sr_info->sen[i].fck);
- + err_unmap:
- + 	iounmap(sr_info->sen[i].base);
- + err_release_mem:
- + 	release_mem_region(res[i]->start, resource_size(res[i]));
- + err_free_mem:
- +         kfree(sr_info->res_name[i]);
- +         /* unwind back through the for loop */
- +         if (i != 0) {
- +                 goto err_reg_put;
- +         }
- + 
- + err_free_sr_info:
- + 	kfree(sr_info);
- + 	return ret;
- + }
- + 
- + static int __devexit am33xx_sr_remove(struct platform_device *pdev)
- + {
- + 	struct am33xx_sr *sr_info;
- + 	struct resource *res[MAX_SENSORS];
- + 	int irq;
- + 	int i;
- + 
- + 	sr_info = dev_get_drvdata(&pdev->dev);
- + 	if (!sr_info) {
- + 		dev_err(&pdev->dev, "%s: sr_info missing\n", __func__);
- + 		return -EINVAL;
- + 	}
- + 
- + 	if (sr_info->autocomp_active)
- + 		sr_stop_vddautocomp(sr_info);
- + 
- + #ifdef CONFIG_CPU_FREQ
- + 	am33xx_sr_cpufreq_deregister(sr_info);
- + #endif
- + 
- + 	for (i = 0; i < sr_info->no_of_sens; i++) {
- +                 regulator_put(sr_info->sen[i].reg);
- +                 irq = platform_get_irq_byname(pdev, sr_info->sen[i].name);
- + 		free_irq(irq, (void *)sr_info);
- + 		clk_put(sr_info->sen[i].fck);
- + 		iounmap(sr_info->sen[i].base);
- + 		res[i] = platform_get_resource_byname(pdev,
- + 				IORESOURCE_MEM, sr_info->sen[i].name);
- + 		release_mem_region(res[i]->start, resource_size(res[i]));
- +                 kfree(sr_info->res_name[i]);
- + 	}
- + 
- + 	kfree(sr_info);
- + 
- +         dev_info(&pdev->dev, "%s: SR has been removed\n", __func__);
- + 	return 0;
- + }
- + 
- + static struct platform_driver smartreflex_driver = {
- + 	.driver		= {
- + 		.name	= "smartreflex",
- + 		.owner	= THIS_MODULE,
- + 	},
- + 	.remove		= am33xx_sr_remove,
- + };
- + 
- + static int __init sr_init(void)
- + {
- + 	int ret;
- + 
- + 	ret = platform_driver_probe(&smartreflex_driver, am33xx_sr_probe);
- + 	if (ret) {
- + 		pr_err("%s: platform driver register failed\n", __func__);
- + 		return ret;
- + 	}
- + 
- + 	return 0;
- + }
- + 
- + static void __exit sr_exit(void)
- + {
- + 	platform_driver_unregister(&smartreflex_driver);
- + }
- + late_initcall(sr_init);
- + module_exit(sr_exit);
- + 
- + MODULE_DESCRIPTION("AM33XX Smartreflex Class2 Driver");
- + MODULE_LICENSE("GPL");
- + MODULE_ALIAS("platform:" DRIVER_NAME);
- + MODULE_AUTHOR("Texas Instruments Inc");
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/board-ckb-3352.c linux-3.2.1/arch/arm/mach-ckb_3352/board-ckb-3352.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/board-ckb-3352.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/board-ckb-3352.c	2014-06-06 15:08:40.108505000 +0900
- ***************
- *** 0 ****
- --- 1,2539 ----
- + /*
- +  * Code for AM335X EVM.
- +  *
- +  * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + #include <linux/kernel.h>
- + #include <linux/init.h>
- + #include <linux/i2c.h>
- + #include <linux/module.h>
- + #include <linux/i2c/at24.h>
- + #include <linux/phy.h>
- + #include <linux/gpio.h>
- + #include <linux/gpio_keys.h>
- + #include <linux/input.h>
- + #include <linux/mtd/mtd.h>
- + #include <linux/mtd/nand.h>
- + #include <linux/mtd/partitions.h>
- + #include <linux/mtd/physmap.h>
- + #include <linux/platform_device.h>
- + #include <linux/clk.h>
- + #include <linux/err.h>
- + #include <linux/export.h>
- + #include <linux/ethtool.h>
- + #include <linux/mfd/tps65217.h>
- + #include <linux/reboot.h>
- + #include <linux/pwm/pwm.h>
- + #include <linux/rtc/rtc-omap.h>
- + #include <linux/opp.h>
- + #include <linux/i2c/tsc2007.h>
- + #include <linux/irq.h>
- + #include <video/omapdss.h>
- + #include <linux/rtc/rtc-omap.h>
- + #ifdef CONFIG_SUPPORT_GPMC_CS1_MEM
- + #include <mtd/ckb_gpmc_cs1.h>
- + #endif
- + #include <mach/ckb_3352.h>
- + 
- + /* LCD controller is similar to DA8xx */
- + #if defined(CONFIG_CKB_LCD_SUPPORT) || defined(CONFIG_CKB_DVI_SUPPORT)
- + #include <video/da8xx-fb.h>
- + #endif
- + 
- + #include <mach/hardware.h>
- + 
- + #include <asm/mach-types.h>
- + #include <asm/mach/arch.h>
- + #include <asm/mach/map.h>
- + 
- + #include <plat/omap_device.h>
- + #include <plat/irqs.h>
- + #include <plat/board.h>
- + #include <plat/common.h>
- + #include <plat/lcdc.h>
- + #include <plat/usb.h>
- + #include <plat/mmc.h>
- + //#include <plat/emif.h>
- + #include <plat/gpmc.h>
- + 
- + #include "cpuidle33xx.h"
- + #include "mux.h"
- + #include "devices.h"
- + #include "hsmmc.h"
- + #include <mach/devices.h>
- + 
- + #ifdef CONFIG_CKB_DVI_SUPPORT
- + #include <video/ckb_dvi.h>
- + #endif
- + #ifdef CONFIG_CKB_EXTCN_SPIDEV_SPI1
- + #include <linux/spi/spi.h>
- + #endif
- + #ifdef CONFIG_CKB_EXTCN_ADC
- + #include <linux/platform_data/ti_adc.h>
- + #include <linux/mfd/ti_tscadc.h>
- + #endif
- + 
- + #ifdef CONFIG_SUPPORT_CMJ100
- + #include <linux/cm-j100.h>
- + #endif
- + 
- + #define DISP_PLL_CLK		300000000
- + 
- + /* Convert GPIO signal to GPIO pin number */
- + #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
- + 
- + /* AM335X EVM Phy ID and Debug Registers */
- + #define AM335X_EVM_PHY_ID		0x221611
- + #define AM335X_EVM_PHY_MASK		0xfffffffe
- + 
- + #define CKB_LAN_RST_PIN			GPIO_TO_PIN(3, 1)
- + #define CKB_LCD_PWR_PIN		GPIO_TO_PIN(3, 7)
- + #define CKB_LCD_BL_PIN		GPIO_TO_PIN(3, 8)
- + #define CKB_BL_TPS_PIN			GPIO_TO_PIN(3, 19)
- + #define DA8xx_TS_PENIRQ_GPIO	GPIO_TO_PIN(3, 17)
- + #define DA8xx_RTCIRQ_GPIO		GPIO_TO_PIN(3, 18)
- + 
- + /* various memory sizes */
- + #define FLASH_SIZE_16M		SZ_16M	/* NOR flash (16 Meg aligned) */
- + #define FLASH_SIZE_SDPV1	SZ_64M	/* NOR flash (64 Meg aligned) */
- + #define FLASH_SIZE_SDPV2	SZ_128M	/* NOR flash (256 Meg aligned) */
- + 
- + /* LCD backlight platform Data */
- + #define AM335X_BACKLIGHT_MAX_BRIGHTNESS        100
- + #define AM335X_BACKLIGHT_DEFAULT_BRIGHTNESS    100
- + #define AM335X_PWM_PERIOD_NANO_SECONDS        (5000 * 10)
- + 
- + #define AM335XEVM_WLAN_PMENA_GPIO	GPIO_TO_PIN(1, 30)
- + #define AM335XEVM_WLAN_IRQ_GPIO		GPIO_TO_PIN(3, 17)
- + 
- + #ifdef CONFIG_SUPPORT_CMJ100
- + #define CKB_WLAN_EN				GPIO_TO_PIN(0, 30)
- + #define CKB_WLAN_IRQ			GPIO_TO_PIN(0, 31)
- + #endif
- + 
- + #define CKB_LED1_PIN			GPIO_TO_PIN(0, 19)
- + #define CKB_LED2_PIN			GPIO_TO_PIN(0, 20)
- + 
- + 
- + #define SET_GPIO_TO_OUTPUT(p, val)	\
- + 	if (gpio_request(p, "gpio_x") || gpio_direction_output(p, val)) { \
- + 		pr_warning("Error initializing the GPIO %d\n", p); \
- + 	}\
- + 	gpio_free(p);
- + 
- + #define SET_GPIO_TO_INPUT(p)	\
- + 	if (gpio_request(p, "gpio_x") || gpio_direction_input(p)) { \
- + 		pr_warning("Error initializing the GPIO %d\n", p); \
- + 	}\
- + 	gpio_free(p);
- + 
- + unsigned long FB_DATA_ADDRESS = 0;
- + unsigned long FB_DATA_VADDRESS = 0;
- + unsigned long FB_MAP_SIZE = 0;
- + 
- + /* module pin mux structure */
- + struct pinmux_config {
- + 	const char *string_name; /* signal name format */
- + 	int val; /* Options for the mux register value */
- + };
- + 
- + #if defined(CONFIG_CKB_TSC2007_TOUCH_PANEL) || defined(CONFIG_CKB_RTC)
- + /* I2C device index */
- + enum {
- + #ifdef CONFIG_CKB_TSC2007_TOUCH_PANEL
- + 	CKB_TSC_DEV_INDEX,
- + #endif
- + #ifdef CONFIG_CKB_RTC
- + 	CKB_RTC_DEV_INDEX,
- + #endif
- + };
- + #endif
- + 
- + 
- + typedef enum {
- + 	CKB_EMAC_MAC_OFFSET,
- + //	CKB_SDIO_MAC_OFFSET,
- + 	TOTAL_EMAC_NUMS
- + }CKB_MAC_OFFSET;
- + 
- + /*
- + * @pin_mux - single module pin-mux structure which defines pin-mux
- + *			details for all its pins.
- + */
- + static void setup_pin_mux(struct pinmux_config *pin_mux)
- + {
- + 	int i;
- + 
- + 	for (i = 0; pin_mux->string_name != NULL; pin_mux++)
- + 		omap_mux_init_signal(pin_mux->string_name, pin_mux->val);
- + 
- + }
- + 
- + static struct mtd_partition ckb_norflash_partition[] = {
- + 	{
- + 		.name           = "loader.bin",
- + 		.offset         = 0,
- + 		.size           = SZ_128K,
- + 		.mask_flags     = MTD_WRITEABLE,
- + 	},
- + 	{
- + 		.name           = "U-Boot",
- + 		.offset         = MTDPART_OFS_APPEND,
- + 		.size           = SZ_256K+SZ_128K,
- + 		.mask_flags     = 0,
- + 	},
- + 	{
- + 		.name           = "LCD Logo image",
- + 		.offset         = MTDPART_OFS_APPEND,
- + 		.size           = SZ_256K+SZ_128K,
- + 		.mask_flags     = 0,
- + 	},
- + 	{
- + 		.name           = "U-Boot environment",
- + 		.offset         = MTDPART_OFS_APPEND,
- + 		.size           = SZ_128K,
- + 		.mask_flags     = 0,
- + 	},
- + 	{
- + 		.name           = "Kernel",
- + 		.offset         = MTDPART_OFS_APPEND,
- + 		.size           = SZ_1M*14,
- + 		.mask_flags     = 0,
- + 	},
- + 	{
- + 		.name           = "Settings",
- + 		.offset         = MTDPART_OFS_APPEND,
- + 		.size           = MTDPART_SIZ_FULL,
- + 		.mask_flags     = 0,
- + 	},
- + };
- + 
- + 
- + static struct physmap_flash_data ckb_norflash_data = {
- + 	.width		= 2,
- + 	.parts		= ckb_norflash_partition,
- + 	.nr_parts	= ARRAY_SIZE(ckb_norflash_partition),
- + };
- + 
- + 
- + static struct pinmux_config ckb_nor_pins[] = {
- + 	{"gpmc_ad0.gpmc_ad0",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
- + 	{"gpmc_ad1.gpmc_ad1",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
- + 	{"gpmc_ad2.gpmc_ad2",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
- + 	{"gpmc_ad3.gpmc_ad3",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
- + 	{"gpmc_ad4.gpmc_ad4",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
- + 	{"gpmc_ad5.gpmc_ad5",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
- + 	{"gpmc_ad6.gpmc_ad6",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
- + 	{"gpmc_ad7.gpmc_ad7",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
- + 	{"gpmc_ad8.gpmc_ad8",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
- + 	{"gpmc_ad9.gpmc_ad9",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
- + 	{"gpmc_ad10.gpmc_ad10",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
- + 	{"gpmc_ad11.gpmc_ad11",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
- + 	{"gpmc_ad12.gpmc_ad12",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
- + 	{"gpmc_ad13.gpmc_ad13",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
- + 	{"gpmc_ad14.gpmc_ad14",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
- + 	{"gpmc_ad15.gpmc_ad15",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
- + 	/* for GPIO port */
- + 	{"gpmc_a4.gpio1_20", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
- + 	{"gpmc_a5.gpio1_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
- + 	{"gpmc_a6.gpio1_22", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
- + 	{"gpmc_a7.gpio1_23", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
- + 	{"gpmc_a8.gpio1_24", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
- + 	{"gpmc_a9.gpio1_25", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
- + 	{"gpmc_a10.gpio1_26", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
- + 	{NULL, 0},
- + };
- + 
- + 
- + 
- + #include "common.h"
- + 
- + 
- + static struct omap2_hsmmc_info mmc_sdcard __initdata = {
- + 	.mmc            = 1,
- + 	.caps           = MMC_CAP_4_BIT_DATA,
- + 	.gpio_cd        = GPIO_TO_PIN(0, 6),
- + 	.gpio_wp        = -EINVAL,
- + 	.ocr_mask       = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3V3 */
- + };
- + 
- + #ifdef CONFIG_SUPPORT_CMJ100
- + 
- + static struct omap2_hsmmc_info mmc_cmj100 __initdata = {
- + 	.mmc            = 3,
- + 	.name			= "cm-j100",
- + 	.caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE,
- + 	.nonremovable	= true,
- + 	.gpio_cd        = -EINVAL,
- + 	.gpio_wp        = -EINVAL,
- + 	.ocr_mask       = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3V3 */
- + };
- + 
- + static int cmj100_sdio_set_power(struct device *dev, int slot, int power_on, int vdd)
- + {
- + 	return cmj100_set_power(power_on);
- + }
- + 
- + static struct pinmux_config cmj100_wl_pins[] = {
- + 	{"gpmc_a1.mmc2_dat0", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
- + 	{"gpmc_a2.mmc2_dat1", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
- + 	{"gpmc_a3.mmc2_dat2", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
- + 	{"gpmc_ben1.mmc2_dat3", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
- + 	{"gpmc_csn3.mmc2_cmd", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
- + 	{"gpmc_clk.mmc2_clk", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
- + 	{"gpmc_wait0.gpio0_30", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
- + 	{"gpmc_wpn.gpio0_31", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
- + 	{NULL, 0},
- + };
- + 
- + static struct cmj100_platform_data wlan_data __initdata = {
- + 	.wlan_en_gpio = CKB_WLAN_EN,
- + 	.wlan_irq_gpio = CKB_WLAN_IRQ,
- + 	.board_ref_clock = CMJ100_REFCLOCK_38_XTAL,
- + 	.irq = -1,
- + 	.trigger_rising = 1, /* rising edge */
- + };
- + 
- + 
- + static void ckb_cmj100_init(void)
- + {
- + 	struct device *dev;
- + 	struct omap_mmc_platform_data *pdata;
- + 
- + 	setup_pin_mux(cmj100_wl_pins);
- + 	
- + 	if (gpio_request(CKB_WLAN_EN, "wl_en") ||
- + 			gpio_direction_output(CKB_WLAN_EN, 0))
- + 		pr_warning("Error initializing the wl_en GPIO %d\n",
- + 					CKB_WLAN_EN);
- + 		
- + 	if (gpio_request(CKB_WLAN_IRQ, "wl_irq") ||
- + 			gpio_direction_input(CKB_WLAN_IRQ))
- + 		pr_warning("Error initializing the wl_irq GPIO %d\n",
- + 					CKB_WLAN_IRQ);
- + 	
- + 	omap_init_hsmmc(&mmc_cmj100);
- + 		
- + 	if (cmj100_set_platform_data(&wlan_data))
- + 		pr_err("Error setting cmj100 data\n");
- + 
- + 	dev = mmc_cmj100.dev;
- + 	if (!dev) {
- + 		pr_err("cm-j100 initialization failed\n");
- + 		goto out;
- + 	}
- + 
- + 	pdata = dev->platform_data;
- + 	if (!pdata) {
- + 		pr_err("Platform data of cm-j100 not set\n");
- + 		goto out;
- + 	}
- + 
- + 	pdata->slots[0].set_power = cmj100_sdio_set_power;
- + 
- + out:
- + 	return;
- + }
- + #endif
- + 
- + 
- + #if defined(CONFIG_CKB_LCD_SUPPORT) || defined(CONFIG_CKB_DVI_SUPPORT)
- + /* Module pin mux for LCDC */
- + static struct pinmux_config lcdc_pin_mux[] = {
- + 	{"lcd_data0.lcd_data0",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
- + 						       | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW},
- + 	{"lcd_data1.lcd_data1",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
- + 						       | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW},
- + 	{"lcd_data2.lcd_data2",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
- + 						       | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW},
- + 	{"lcd_data3.lcd_data3",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
- + 						       | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW},
- + 	{"lcd_data4.lcd_data4",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
- + 						       | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW},
- + 	{"lcd_data5.lcd_data5",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
- + 						       | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW},
- + 	{"lcd_data6.lcd_data6",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
- + 						       | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW},
- + 	{"lcd_data7.lcd_data7",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
- + 						       | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW},
- + 	{"lcd_data8.lcd_data8",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
- + 						       | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW},
- + 	{"lcd_data9.lcd_data9",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
- + 						       | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW},
- + 	{"lcd_data10.lcd_data10",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
- + 						       | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW},
- + 	{"lcd_data11.lcd_data11",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
- + 						       | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW},
- + 	{"lcd_data12.lcd_data12",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
- + 						       | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW},
- + 	{"lcd_data13.lcd_data13",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
- + 						       | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW},
- + 	{"lcd_data14.lcd_data14",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
- + 						       | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW},
- + 	{"lcd_data15.lcd_data15",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
- + 						       | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW},
- + 	{"lcd_vsync.lcd_vsync",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_SLEWCTRL_SLOW},
- + 	{"lcd_hsync.lcd_hsync",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_SLEWCTRL_SLOW},
- + 	{"lcd_pclk.lcd_pclk",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_SLEWCTRL_SLOW},
- + 	{"lcd_ac_bias_en.lcd_ac_bias_en", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_SLEWCTRL_SLOW},
- + 	{NULL, 0},
- + };
- + #endif
- + 
- + #if defined(CONFIG_CKB_LCD_SUPPORT)
- + static struct pinmux_config lcdpwr_pin_mux[] = {
- + 	{"emu0.gpio3_7", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT_PULLUP},		/* LCDC Pwr pin */
- + 	{"emu1.gpio3_8", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT_PULLUP},		/* Backlight pin */
- + 	{"mcasp0_fsr.gpio3_19", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT_PULLUP},	/* TPS pin */
- + 	{NULL, 0},
- + };
- + #endif
- + 
- + /* Module pin mux for rgmii1 */
- + static struct pinmux_config rgmii1_pin_mux[] = {
- + 	{"mii1_txen.rgmii1_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
- + 	{"mii1_rxdv.rgmii1_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
- + 	{"mii1_txd3.rgmii1_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
- + 	{"mii1_txd2.rgmii1_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
- + 	{"mii1_txd1.rgmii1_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
- + 	{"mii1_txd0.rgmii1_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
- + 	{"mii1_txclk.rgmii1_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
- + 	{"mii1_rxclk.rgmii1_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
- + 	{"mii1_rxd3.rgmii1_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
- + 	{"mii1_rxd2.rgmii1_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
- + 	{"mii1_rxd1.rgmii1_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
- + 	{"mii1_rxd0.rgmii1_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
- + 	{"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
- + 	{"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
- + 	//{"mii1_col.gpio3_0", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLDOWN},	/* IRQ */
- + 	{"mii1_crs.gpio3_1", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT_PULLUP},	/* reset pin */
- + 	{NULL, 0},
- + };
- + 
- + 
- + //AM33XX_SLEWCTRL_SLOW
- + static struct pinmux_config i2c0_pin_mux[] = {
- + 	{"i2c0_sda.i2c0_sda",    OMAP_MUX_MODE0 | AM33XX_INPUT_EN | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW },
- + 	{"i2c0_scl.i2c0_scl",   OMAP_MUX_MODE0 | AM33XX_INPUT_EN | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW },
- + 	{NULL, 0},
- + };
- + 
- + /* Module pin mux for mmc0 */
- + static struct pinmux_config mmc0_common_pin_mux[] = {
- + 	{"mmc0_dat3.mmc0_dat3",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
- + 	{"mmc0_dat2.mmc0_dat2",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
- + 	{"mmc0_dat1.mmc0_dat1",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
- + 	{"mmc0_dat0.mmc0_dat0",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
- + 	{"mmc0_clk.mmc0_clk",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
- + 	{"mmc0_cmd.mmc0_cmd",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
- + 	{NULL, 0},
- + };
- + 
- + static struct pinmux_config mmc0_cd_only_pin_mux[] = {
- + 	{"spi0_cs1.gpio0_6",  OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
- + 	{NULL, 0},
- + };
- + 
- + /* pinmux for usb0 drvvbus */
- + static struct pinmux_config usb0_pin_mux[] = {
- + 	{"usb0_drvvbus.usb0_drvvbus",    OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
- + 	{"mii1_rxerr.gpio3_2", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLDOWN},	/* USB fault */
- + 	{NULL, 0},
- + };
- + 
- + /* pinmux for usb1 drvvbus */
- + static struct pinmux_config usb1_pin_mux[] = {
- + 	{"usb1_drvvbus.usb1_drvvbus",    OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
- + 	{NULL, 0},
- + };
- + 
- + 
- + /* TPS65217 voltage regulator support */
- + 
- + /* 1.8V */
- + static struct regulator_consumer_supply tps65217_dcdc1_consumers[] = {
- + 	{
- + 		.supply = "vdds_osc",
- + 	},
- + 	{
- + 		.supply = "vdds_pll_ddr",
- + 	},
- + 	{
- + 		.supply = "vdds_pll_mpu",
- + 	},
- + 	{
- + 		.supply = "vdds_pll_core_lcd",
- + 	},
- + 	{
- + 		.supply = "vdds_sram_mpu_bb",
- + 	},
- + 	{
- + 		.supply = "vdds_sram_core_bg",
- + 	},
- + 	{
- + 		.supply = "vdda_usb0_1p8v",
- + 	},
- + 	{
- + 		.supply = "vdds_ddr",
- + 	},
- + 	{
- + 		.supply = "vdds",
- + 	},
- + 	{
- + 		.supply = "vdds_hvx_1p8v",
- + 	},
- + 	{
- + 		.supply = "vdda_adc",
- + 	},
- + 	{
- + 		.supply = "ddr2",
- + 	},
- + };
- + 
- + /* 1.1V */
- + static struct regulator_consumer_supply tps65217_dcdc2_consumers[] = {
- + 	{
- + 		.supply = "vdd_mpu",
- + 	},
- + };
- + 
- + /* 1.1V */
- + static struct regulator_consumer_supply tps65217_dcdc3_consumers[] = {
- + 	{
- + 		.supply = "vdd_core",
- + 	},
- + };
- + 
- + /* 1.8V LDO */
- + static struct regulator_consumer_supply tps65217_ldo1_consumers[] = {
- + 	{
- + 		.supply = "vdds_rtc",
- + 	},
- + };
- + 
- + /* 3.3V LDO */
- + static struct regulator_consumer_supply tps65217_ldo2_consumers[] = {
- + 	{
- + 		.supply = "vdds_any_pn",
- + 	},
- + };
- + 
- + /* 3.3V LDO */
- + static struct regulator_consumer_supply tps65217_ldo3_consumers[] = {
- + 	{
- + 		.supply = "vdds_hvx_ldo3_3p3v",
- + 	},
- + 	{
- + 		.supply = "vdda_usb0_3p3v",
- + 	},
- + };
- + 
- + /* 3.3V LDO */
- + static struct regulator_consumer_supply tps65217_ldo4_consumers[] = {
- + 	{
- + 		.supply = "vdds_hvx_ldo4_3p3v",
- + 	},
- + };
- + 
- + static struct tps65217_rdelay dcdc2_ramp_delay = {
- + 	.ramp_delay = 70000,
- + };
- + 
- + static struct regulator_init_data tps65217_regulator_data[] = {
- + 	/* dcdc1 */
- + 	{
- + 		.constraints = {
- + 			.min_uV = 900000,
- + 			.max_uV = 1800000,
- + 			.boot_on = 1,
- + 			.always_on = 1,
- + 		},
- + 		.num_consumer_supplies = ARRAY_SIZE(tps65217_dcdc1_consumers),
- + 		.consumer_supplies = tps65217_dcdc1_consumers,
- + 	},
- + 
- + 	/* dcdc2 */
- + 	{
- + 		.constraints = {
- + 			.min_uV = 900000,
- + 			.max_uV = 3300000,
- + 			.valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
- + 				REGULATOR_CHANGE_STATUS),
- + 			.boot_on = 1,
- + 			.always_on = 1,
- + 		},
- + 		.num_consumer_supplies = ARRAY_SIZE(tps65217_dcdc2_consumers),
- + 		.consumer_supplies = tps65217_dcdc2_consumers,
- + 		.driver_data = &dcdc2_ramp_delay,
- + 		.ignore_check_consumers = 1,
- + 	},
- + 
- + 	/* dcdc3 */
- + 	{
- + 		.constraints = {
- + 			.min_uV = 900000,
- + 			.max_uV = 1500000,
- + 			.valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
- + 				REGULATOR_CHANGE_STATUS),
- + 			.boot_on = 1,
- + 			.always_on = 1,
- + 		},
- + 		.num_consumer_supplies = ARRAY_SIZE(tps65217_dcdc3_consumers),
- + 		.consumer_supplies = tps65217_dcdc3_consumers,
- + 		.ignore_check_consumers = 1,
- + 	},
- + 
- + 	/* ldo1 */
- + 	{
- + 		.constraints = {
- + 			.min_uV = 1000000,
- + 			.max_uV = 3300000,
- + 			.valid_ops_mask = REGULATOR_CHANGE_STATUS,
- + 			.boot_on = 1,
- + 			.always_on = 1,
- + 		},
- + 		.num_consumer_supplies = ARRAY_SIZE(tps65217_ldo1_consumers),
- + 		.consumer_supplies = tps65217_ldo1_consumers,
- + 	},
- + 
- + 	/* ldo2 */
- + 	{
- + 		.constraints = {
- + 			.min_uV = 900000,
- + 			.max_uV = 3300000,
- + 			.valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
- + 				REGULATOR_CHANGE_STATUS),
- + 			.boot_on = 1,
- + 			.always_on = 1,
- + 		},
- + 		.num_consumer_supplies = ARRAY_SIZE(tps65217_ldo2_consumers),
- + 		.consumer_supplies = tps65217_ldo2_consumers,
- + 	},
- + 
- + 	/* ldo3 */
- + 	{
- + 		.constraints = {
- + 			.min_uV = 1800000,
- + 			.max_uV = 3300000,
- + 			.valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
- + 				REGULATOR_CHANGE_STATUS),
- + 			.boot_on = 1,
- + 			.always_on = 1,
- + 		},
- + 		.num_consumer_supplies = ARRAY_SIZE(tps65217_ldo3_consumers),
- + 		.consumer_supplies = tps65217_ldo3_consumers,
- + 	},
- + 
- + 	/* ldo4 */
- + 	{
- + 		.constraints = {
- + 			.min_uV = 1800000,
- + 			.max_uV = 3300000,
- + 			.valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
- + 				REGULATOR_CHANGE_STATUS),
- + 			.boot_on = 1,
- + 			.always_on = 1,
- + 		},
- + 		.num_consumer_supplies = ARRAY_SIZE(tps65217_ldo4_consumers),
- + 		.consumer_supplies = tps65217_ldo4_consumers,
- + 	},
- + };
- + 
- + static struct tps65217_board ckb_tps65217_info = {
- + 	.tps65217_init_data = &tps65217_regulator_data[0],
- + 	.status_off = true,
- + };
- + 
- + int conf_disp_pll(int rate)
- + {
- + 	struct clk *disp_pll;
- + 	int ret = -EINVAL;
- + 
- + 	disp_pll = clk_get(NULL, "dpll_disp_ck");
- + 	if (IS_ERR(disp_pll)) {
- + 		pr_err("Cannot clk_get disp_pll\n");
- + 		goto out;
- + 	}
- + 	ret = clk_set_rate(disp_pll, rate);
- + 	clk_put(disp_pll);
- + out:
- + 	return ret;
- + }
- + 
- + #ifdef CONFIG_SUPPORT_CKB_LED
- + /* pinmux for led device */
- + static struct pinmux_config ckb_led_pinmux[] = {
- + 	{"xdma_event_intr0.gpio0_19", OMAP_MUX_MODE7},
- + 	{"xdma_event_intr1.gpio0_20", OMAP_MUX_MODE7},
- + 	{NULL, 0},
- + };
- + 
- + static struct gpio_led ckb_leds[] = {
- + 	{
- + 		.name			= "led1",
- + 		//.default_trigger	= "heartbeat",
- + 		.default_trigger	= "default-on",
- + 		.gpio			= CKB_LED1_PIN,
- + 		//.active_low		= 1,
- + 	},
- + 	{
- + 		.name			= "led2",
- + 		.default_trigger	= "default-on",
- + 		.gpio			= CKB_LED2_PIN,
- + 	},
- + };
- + 
- + static struct gpio_led_platform_data ckb_leds_data = {
- + 	.num_leds	= ARRAY_SIZE(ckb_leds),
- + 	.leds		= ckb_leds,
- + };
- + 
- + static struct platform_device ckb_gpio_leds = {
- + 	.name	= "leds-gpio",
- + 	.id	= -1,
- + 	.dev	= {
- + 		.platform_data = &ckb_leds_data,
- + 	},
- + };
- + 
- + static void gpio_led_init(void)
- + {
- + 	int err;
- + 	
- + 	setup_pin_mux(ckb_led_pinmux);
- + 	err = platform_device_register(&ckb_gpio_leds);
- + 	if (err)
- + 		pr_err("failed to register gpio led device\n");
- + }
- + #endif
- + 
- + #ifdef CONFIG_CKB_TSC2007_TOUCH_PANEL
- + static struct pinmux_config ckb_touchpanel_pin_mux[] = {
- + 	{"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},		/* TP Pen IRQ */
- + 	{NULL, 0},
- + };
- + 
- + int tsc2007_get_pendown_state(void)
- + {
- + 	return !gpio_get_value(DA8xx_TS_PENIRQ_GPIO);
- + }
- + 
- + static struct tsc2007_platform_data tsc2007_info = {
- + 	.model			= 2007,
- + 	.x_plate_ohms		= 180,
- + 	.get_pendown_state = tsc2007_get_pendown_state,
- + };
- + #endif
- + 
- + #ifdef CONFIG_CKB_RTC
- + static struct pinmux_config ckb_rtc_pin_mux[] = {
- + 	{"mcasp0_aclkr.gpio3_18", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},		/* RTC IRQ */
- + 	{NULL, 0},
- + };
- + #endif
- + 
- + /* global variables to store EEPROM function call params */
- + struct memory_accessor *g_at24i2c_mem_acc = NULL;
- + void *g_g_at24i2c_context;
- + 
- + /* retrieves the mac address from EEPROM
- + 	offset : Index of the MAC address structure on EEPROM
- + 	mac_addr : MAC address (6 bytes)
- + */
- + u_char get_mac_address(CKB_MAC_OFFSET offset, char *mac_addr)
- + {
- + 	size_t len;
- + 	ckb_3352_eeprom_mac_address mac;
- + 	int addr;
- + 	if(offset>=TOTAL_EMAC_NUMS)
- + 	{
- + 		printk("Wrong offset specified for MAC address\n");
- + 		return 1;
- + 	}
- + 	if(!g_at24i2c_mem_acc)
- + 	{
- + 		printk("No EEPROM device found. Unable to read MAC address\n");
- + 		return 2;
- + 	}
- + 	len = sizeof(ckb_3352_eeprom_mac_address);
- + 	addr = ((int)g_g_at24i2c_context)+(offset*len);
- + 	
- + 	/* read data */
- + 	if((!g_at24i2c_mem_acc->read) || g_at24i2c_mem_acc->read(g_at24i2c_mem_acc, (char*)&mac, addr, len) != len)
- + 	{
- + 		printk("Unable to read MAC address from EEPROM\n");
- + 		return 3;
- + 	}
- + 	/* check the header */
- + 	if(mac.id!=CKB_3352_MAC_HEADER)
- + 	{
- + 		printk("MAC address header mismatch on EEPROM\n");
- + 		return 4;
- + 	}
- + 	pr_info("Read MAC addr from EEPROM: %pM\n", mac.mac);
- + 	/* copy the mac address */
- + 	memcpy(mac_addr, mac.mac, ETH_ALEN);
- + 	return 0;
- + }
- + 
- + /* writes the MAC address to NAND flash
- + 	offset : Index of the MAC address structure on EEPROM
- + 	mac_addr : MAC address (6 bytes)
- + */
- + u_char save_mac_address(CKB_MAC_OFFSET offset, char *mac_addr)
- + {
- + 	ckb_3352_eeprom_mac_address mac;
- + 	size_t len;
- + 	int addr;
- + 
- + 	if(offset>=TOTAL_EMAC_NUMS)
- + 	{
- + 		printk("Wrong offset specified for MAC address\n");
- + 		return 1;
- + 	}
- + 	if(!g_at24i2c_mem_acc)
- + 	{
- + 		printk("No EEPROM device found. Unable to read MAC address\n");
- + 		return 2;
- + 	}
- + 	len = sizeof(ckb_3352_eeprom_mac_address);
- + 	addr = ((int)g_g_at24i2c_context)+(offset*len);
- + 	/* update new mac address in the buffer */
- + 	mac.id = CKB_3352_MAC_HEADER;
- + 	memcpy(mac.mac, mac_addr, ETH_ALEN);
- + 	pr_info("Writing MAC addr to EEPROM: %pM\n", mac_addr);
- + 	/* write data */
- + 	if((!g_at24i2c_mem_acc->write) || g_at24i2c_mem_acc->write(g_at24i2c_mem_acc, (char*)&mac, addr, len) != len)
- + 	{
- + 		pr_err("Unable to Write MAC address to EEPROM\n");
- + 		return 3;
- + 	}
- + 	/* Verify */
- + 	if((!g_at24i2c_mem_acc->read) || g_at24i2c_mem_acc->read(g_at24i2c_mem_acc, (char*)&mac, addr, len) != len)
- + 	{
- + 		pr_err("Unable to read MAC address from EEPROM for verifying\n");
- + 		return 3;
- + 	}
- + 	if(mac.id!=CKB_3352_MAC_HEADER || memcmp(mac.mac, mac_addr, ETH_ALEN))
- + 	{
- + 		pr_err("MAC addr: Data mismatch during verification\n");
- + 		return 3;
- + 	}
- + 	pr_info("MAC addr written successfully\n");
- + 	return 0;
- + }
- + 
- + void save_mac_addr(char *mac_addr)
- + {
- + 	save_mac_address(CKB_EMAC_MAC_OFFSET, mac_addr);
- + }
- + 
- + /* dummy function to store EEPROM function call params */
- + void board_at24i2c_setup(struct memory_accessor *mem_acc, void *context)
- + {
- + 	/* store the pointer for later use */
- + 	g_at24i2c_mem_acc = mem_acc;
- + 	g_g_at24i2c_context = context;
- + }
- + 
- + void  board_at24i2c_unload(void)
- + {
- + 	g_at24i2c_mem_acc = NULL;
- + }
- + 
- + static struct at24_platform_data m24c01_eeprom_info = {
- + 	.byte_len	= SZ_1K / 8,
- + 	.page_size	= 16,
- + 	.flags		= 0,
- + 	.setup		= board_at24i2c_setup,
- + 	.unload		= board_at24i2c_unload,
- + };
- + 
- + static struct i2c_board_info __initdata am335x_i2c0_boardinfo[] = {
- + #ifdef CONFIG_CKB_TSC2007_TOUCH_PANEL
- + 	[CKB_TSC_DEV_INDEX]={
- + 		I2C_BOARD_INFO("tsc2007", (0x90>>1)),
- + 		.type		= "tsc2007",
- + 		.platform_data	= &tsc2007_info,
- + 		.irq = 0,
- + 	},
- + #endif
- + #ifdef CONFIG_CKB_RTC
- + 	[CKB_RTC_DEV_INDEX]={
- + 		I2C_BOARD_INFO("s35390a", 0x30),
- + 		.irq	= 0,
- + 	},
- + #endif
- + 	{
- + 		I2C_BOARD_INFO("tps65217", TPS65217_I2C_ID),
- + 		.platform_data  = &ckb_tps65217_info,
- + 	},
- + 	{
- + 		I2C_BOARD_INFO("24c01", 0x51),
- + 		.platform_data = &m24c01_eeprom_info,
- + 	},
- + #ifdef CONFIG_CKB_3352_AUDIO
- + 	{
- + 		I2C_BOARD_INFO("tlv320aic3x", 0x1b),
- + 	},
- + #endif
- + #ifdef CONFIG_CKB_DVI_SUPPORT
- + 	{
- + 		I2C_BOARD_INFO("tfp410", 0x38),
- + 	},
- + #endif
- + 
- + };
- + 
- + #ifdef CONFIG_CKB_3352_AUDIO
- + 
- + static u8 am335x_iis_serializer_direction1[] = {
- + 	INACTIVE_MODE,	INACTIVE_MODE,	TX_MODE,	RX_MODE,
- + 	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,
- + 	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,
- + 	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,
- + };
- + 
- + static struct snd_platform_data am335x_evm_snd_data1 = {
- + 	.tx_dma_offset	= 0x46400000,	/* McASP1 */
- + 	.rx_dma_offset	= 0x46400000,
- + 	.op_mode	= DAVINCI_MCASP_IIS_MODE,
- + 	.num_serializer	= ARRAY_SIZE(am335x_iis_serializer_direction1),
- + 	.tdm_slots	= 2,
- + 	.serial_dir	= am335x_iis_serializer_direction1,
- + 	.asp_chan_q	= EVENTQ_2,
- + 	.version	= MCASP_VERSION_3,
- + 	.txnumevt	= 1,
- + 	.rxnumevt	= 1,
- + };
- + #endif
- + 
- + static void __init ckb_i2c_init(void)
- + {
- + 	setup_pin_mux(i2c0_pin_mux);
- + 
- + #ifdef CONFIG_CKB_TSC2007_TOUCH_PANEL
- + 	setup_pin_mux(ckb_touchpanel_pin_mux);
- + 
- + 	if (gpio_request(DA8xx_TS_PENIRQ_GPIO, "TS Pen IRQ"))
- + 		pr_err("Error initializing TS Pen IRQ gpio\n");
- + 	gpio_direction_input(DA8xx_TS_PENIRQ_GPIO);
- + 
- + 	gpio_free(DA8xx_TS_PENIRQ_GPIO);
- + 
- + 	am335x_i2c0_boardinfo[CKB_TSC_DEV_INDEX].irq = gpio_to_irq(DA8xx_TS_PENIRQ_GPIO);
- + 	irq_set_irq_type(am335x_i2c0_boardinfo[CKB_TSC_DEV_INDEX].irq, IRQF_TRIGGER_FALLING);
- + #endif
- + 
- + #ifdef CONFIG_CKB_RTC
- + 
- + 	setup_pin_mux(ckb_rtc_pin_mux);
- + 	if (gpio_request(DA8xx_RTCIRQ_GPIO, "RTC IRQ"))
- + 		pr_err("Error initializing RTC IRQ gpio\n");
- + 	gpio_direction_input(DA8xx_RTCIRQ_GPIO);
- + 
- + 	gpio_free(DA8xx_RTCIRQ_GPIO);
- + 
- + 	am335x_i2c0_boardinfo[CKB_RTC_DEV_INDEX].irq = gpio_to_irq(DA8xx_RTCIRQ_GPIO);
- + 	irq_set_irq_type(am335x_i2c0_boardinfo[CKB_RTC_DEV_INDEX].irq, IRQF_TRIGGER_FALLING);
- + #endif
- + 
- + 	omap_register_i2c_bus(1, 48, am335x_i2c0_boardinfo,
- + 				ARRAY_SIZE(am335x_i2c0_boardinfo));
- + }
- + 
- + 
- + static struct omap_musb_board_data musb_board_data = {
- + 	.interface_type	= MUSB_INTERFACE_ULPI,
- + 	/*
- + 	 * mode[0:3] = USB0PORT's mode
- + 	 * mode[4:7] = USB1PORT's mode
- + 	 * CKB 3352 has USB0 and USB1 in host mode.
- + 	 */
- + 	.mode           = (MUSB_HOST << 4) | MUSB_HOST,
- + 	.power		= 500,
- + 	.instances	= 1,
- + };
- + 
- + static void usb0_init(void)
- + {
- + 	setup_pin_mux(usb0_pin_mux);
- + 	return;
- + }
- + 
- + static void usb1_init(void)
- + {
- + 	setup_pin_mux(usb1_pin_mux);
- + 	return;
- + }
- + 
- + #ifdef CONFIG_SUPPORT_GPMC_CS1_MEM
- + static struct pinmux_config cs1_mux_enable[] = {
- + 	{"gpmc_csn1.gpmc_csn1",    OMAP_MUX_MODE0 | AM33XX_PULL_UP},
- + 	{NULL, 0},
- + };
- + 
- + void gpmc_cs1_mux_enable(void)
- + {
- + 	/* CS1 */
- + 	printk("Setting GPMC CS1 mux\n");
- + 	setup_pin_mux(cs1_mux_enable);
- + 	/* WEn and OEn are configured while configuring NOR flash */
- + }
- + 
- + 
- + static struct resource ckb_emif_CS1_resource[] = {
- + 	{
- + 		.start	= CKB_GPMC_CS1_BASE,
- + 		.end	= CKB_GPMC_CS1_BASE + SZ_128,		/* 128 bytes are accessible */
- + 		.flags	= IORESOURCE_MEM,
- + 	},
- + };
- + 
- + struct platform_device ckb_emif_CS1_device = {
- + 	.name          = CKB_GPMC_CS1_DEV_NAME,
- + 	.num_resources = ARRAY_SIZE(ckb_emif_CS1_resource),
- + 	.resource      = ckb_emif_CS1_resource,
- + };
- + 
- + static inline void ckb_setup_ex_cn_cs1(void)
- + {
- + 	platform_device_register(&ckb_emif_CS1_device);
- + }
- + #endif
- + 
- + static struct omap_rtc_pdata am335x_rtc_info = {
- + 	.pm_off		= true,
- + #ifdef CONFIG_CKB_SUSPEND_SUPPORT
- + 	.wakeup_capable	= 1,
- + #else
- + 	.wakeup_capable	= 0,
- + #endif
- + };
- + 
- + static void am335x_rtc_init(void)
- + {
- + 	void __iomem *base;
- + 	struct clk *clk;
- + 	struct omap_hwmod *oh;
- + 	struct platform_device *pdev;
- + 	char *dev_name = "am33xx-rtc";
- + 
- + 	clk = clk_get(NULL, "rtc_fck");
- + 	if (IS_ERR(clk)) {
- + 		pr_err("rtc : Failed to get RTC clock\n");
- + 		return;
- + 	}
- + 
- + 	if (clk_enable(clk)) {
- + 		pr_err("rtc: Clock Enable Failed\n");
- + 		return;
- + 	}
- + 
- + 	base = ioremap(AM33XX_RTC_BASE, SZ_4K);
- + 
- + 	if (WARN_ON(!base))
- + 		return;
- + 
- + 	/* Unlock the rtc's registers */
- + 	writel(0x83e70b13, base + 0x6c);
- + 	writel(0x95a4f1e0, base + 0x70);
- + 
- + 	/*
- + 	 * Enable the 32K OSc
- + 	 * TODO: Need a better way to handle this
- + 	 * Since we want the clock to be running before mmc init
- + 	 * we need to do it before the rtc probe happens
- + 	 */
- + 	writel(0x48, base + 0x54);
- + 
- + 	iounmap(base);
- + 
- + 	clk_disable(clk);
- + 	clk_put(clk);
- + 
- + 	oh = omap_hwmod_lookup("rtc");
- + 	if (!oh) {
- + 		pr_err("could not look up %s\n", "rtc");
- + 		return;
- + 	}
- + 
- + 	pdev = omap_device_build(dev_name, -1, oh, &am335x_rtc_info,
- + 			sizeof(struct omap_rtc_pdata), NULL, 0, 0);
- + 	WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
- + 			dev_name, oh->name);
- + }
- + 
- + unsigned flash_gpios[] = { GPIO_TO_PIN(1,20), GPIO_TO_PIN(1,21), GPIO_TO_PIN(1,22), GPIO_TO_PIN(1,23),
- + 							GPIO_TO_PIN(1,24), GPIO_TO_PIN(1,25), GPIO_TO_PIN(1,26)};
- + static struct resource ckb_norflash_resource[] = {
- + 	{
- + 		/* other fields will be filled later */
- + 		.name  = "cfi_probe",
- + 		.flags	= IORESOURCE_MEM,
- + 	},
- + 	{
- + 		.start = (unsigned long)flash_gpios,
- +  		.end   = ARRAY_SIZE(flash_gpios),
- + 		.flags = IORESOURCE_IRQ,
- + 	}
- + };
- + 
- + struct platform_device ckb_norflash_device = {
- + 	.name          = "gpio-addr-flash",
- + 	.dev           = { .platform_data = &ckb_norflash_data, },
- + 	.num_resources = ARRAY_SIZE(ckb_norflash_resource),
- + 	.resource      = ckb_norflash_resource,
- + };
- + 
- + void board_gpmc_init(void)
- + {
- + 	struct gpmc_devices_info gpmc_device[1] = {
- + 		{ NULL, 0 },
- + 	};
- + 
- + 	gpmc_device[0].pdata = &ckb_norflash_data;
- + 	gpmc_device[0].flag = GPMC_DEVICE_NOR;
- + 
- + 	omap_init_gpmc(gpmc_device, sizeof(gpmc_device));
- + }
- + 
- + static void
- + board_nor_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs)
- + {
- + 	int err;
- + 
- + 	/* Configure start address and size of NOR device */
- + 	err = gpmc_cs_request(cs, FLASH_SIZE_16M - 1,
- + 			(unsigned long *)&ckb_norflash_resource[0].start);
- + 	ckb_norflash_resource[0].end = ckb_norflash_resource[0].start
- + 				+ SZ_128K - 1;
- + 	if (err < 0) {
- + 		pr_err("NOR: Can't request GPMC CS\n");
- + 		return;
- + 	}
- + 	if (platform_device_register(&ckb_norflash_device) < 0)
- + 		pr_err("Unable to register NOR device\n");
- + 	
- + }
- + 
- + void ckb_setup_nor(void)
- + {
- + 	setup_pin_mux(ckb_nor_pins);
- + 	board_gpmc_init();
- + }
- + 
- + 
- + static void rgmii1_init(void)
- + {
- + 	setup_pin_mux(rgmii1_pin_mux);
- + 
- + 	gpio_set_value_cansleep(CKB_LAN_RST_PIN, 0);
- + 	/* issue a reset */
- + 	if (gpio_request(CKB_LAN_RST_PIN, "LAN reset")) {
- + 		pr_warning("Cannot open GPIO %d\n",
- + 					CKB_LAN_RST_PIN);
- + 	}
- + 	else {
- + 		/* reset the LAN chip */
- + 		gpio_direction_output(CKB_LAN_RST_PIN, 0);
- + 		mdelay(15);
- + 		gpio_set_value(CKB_LAN_RST_PIN, 1);
- + 		mdelay(1);
- + 	}
- + 	return;
- + }
- + 
- + static void mmc0_init(void)
- + {
- + 	setup_pin_mux(mmc0_common_pin_mux);
- + 	setup_pin_mux(mmc0_cd_only_pin_mux);
- + 	omap_init_hsmmc(&mmc_sdcard);
- + }
- + 
- + #ifdef CONFIG_PHYLIB
- + volatile int reg_104 = 0x9090;
- + volatile int reg_105 = 0x0000;
- + 
- + static int am33xx_evm_tx_clk_dly_phy_fixup(struct phy_device *phydev)
- + {
- + 	int val;
- + 
- + 	/* min rx data delay */
- + 	phy_write(phydev, 0x0b, 0x8105);
- + 	//phy_write(phydev, 0x0c, 0xFFFFa);
- + 	phy_write(phydev, 0x0c, reg_105);
- + 	
- + 	/* max rx/tx clock delay, min rx/tx control delay */
- + 
- + 	phy_write(phydev, 0x0b, 0x8104);
- + 	phy_write(phydev, 0x0c, reg_104);	//163~182/ 207~222
- + 
- + 	//phy_write(phydev, 0x0c, 0xf0f0);	//163~182/ 207~222
- + 	//phy_write(phydev, 0x0c, 0x70f0);   // 151~188/ 219~234
- + 	//phy_write(phydev, 0x0c, 0x7777); - NG
- + 	//phy_write(phydev, 0x0c, 007x70);  - Ping OK, iperf NG
- + 	//phy_write(phydev, 0x0c, 0x70A0);	//170~     226
- + 	//phy_write(phydev, 0x0c, 0x8080);	//170~     226
- + 	//phy_write(phydev, 0x0c, 0x8080);	//163~182/ 207~222
- + 	//phy_write(phydev, 0x0c, 0x9950);	//163~182/ 207~222
- + 	
- + 	phy_write(phydev, 0x0b, 0x104);
- + 	val =  phy_read(phydev, 0x0d);
- + 	
- + 	phy_write(phydev, 0x0b, 0x0105);
- + 	val =  phy_read(phydev, 0x0d);
- + 	
- + 	return 0;
- + }
- + #endif
- + 
- + #if defined(CONFIG_CKB_LCD_SUPPORT) || defined(CONFIG_CKB_DVI_SUPPORT)
- + static const struct display_panel ckb_disp_panel = {
- + 	QVGA,
- + 	16,
- + 	16,
- + 	COLOR_ACTIVE,
- + };
- + 
- + static struct lcd_ctrl_config lcd_cfg = {
- + 	&ckb_disp_panel,
- + 	.ac_bias		= 255,
- + 	.ac_bias_intrpt		= 0,
- + 	.dma_burst_sz		= 16,
- + 	.bpp			= 16,
- + 	.fdd			= 255,
- + 	.tft_alt_mode		= 0,
- + 	.stn_565_mode		= 0,
- + 	.mono_8bit_mode		= 0,
- + 	.sync_edge		= 0,
- + 	.sync_ctrl		= 1,
- + 	.raster_order		= 0,
- + 	.fifo_th		= 6,
- + };
- + #endif
- + 
- + #ifdef CONFIG_CKB_LCD_SUPPORT
- + /* val: 0 - Backlight and LCD display off
- + 		1 - Backlight and LCD display on
- + 		2 - Backlight off
- + */
- + static void ckb_panel_power_ctrl(int val)
- + {
- + 	/* backlight */
- + 	if(val==0 || val==2)
- + 	{
- + 		/* turn off */
- + 		gpio_set_value(CKB_LCD_BL_PIN, 0);
- + 		gpio_set_value(CKB_BL_TPS_PIN, 0);
- + 	}
- + 	else if(val==1)
- + 	{
- + 		/* turn on */
- + 		gpio_set_value(CKB_LCD_BL_PIN, 1);
- + 		gpio_set_value(CKB_BL_TPS_PIN, 1);
- + 	}
- + 	/* lcd power */
- + 	if(val==0 || val==1)
- + 		gpio_set_value(CKB_LCD_PWR_PIN, val);
- + }
- + #endif
- + 
- + #if defined(CONFIG_CKB_LCD_SUPPORT) || defined(CONFIG_CKB_DVI_SUPPORT)
- + struct da8xx_lcdc_platform_data da8xx_pdata = {
- + #ifdef CONFIG_CKB_LCD_01
- + 	.manu_name		= "Visionx",
- + 	.type			= "Visionx_KTM050AL02",
- + #endif
- + #ifdef CONFIG_CKB_LCD_02
- + 	.manu_name		= "Kyocera",
- + 	.type			= "KyoceraTCG070WVLPAAFA_AA00",
- + #endif
- + 	
- + #ifdef CONFIG_CKB_LCD_SUPPORT
- + 	.panel_power_ctrl = ckb_panel_power_ctrl,
- + #endif
- + #if !defined(CONFIG_CKB_LCD_SUPPORT) && defined(CONFIG_CKB_DVI_SUPPORT)
- + 	.manu_name		= "NONE",
- + 	.type			= "Generic DVI panel",
- + #endif
- + 	.controller_data	= &lcd_cfg,
- + };
- + 
- + static void lcdc_init(void)
- + {
- + #ifdef CONFIG_CKB_LCD_SUPPORT
- + 	int status;
- + #endif
- + 	setup_pin_mux(lcdc_pin_mux);
- + 
- + 	if (conf_disp_pll(DISP_PLL_CLK)) {
- + 		pr_info("Failed configure display PLL, not attempting to"
- + 				"register LCDC\n");
- + 		return;
- + 	}
- + 
- + #ifdef CONFIG_CKB_LCD_SUPPORT
- + 	setup_pin_mux(lcdpwr_pin_mux);
- + 	
- + 	status = gpio_request(CKB_LCD_BL_PIN, "lcd bl\n");
- + 	if (status < 0)
- + 		return;
- + 
- + 	status = gpio_request(CKB_BL_TPS_PIN, "BL TPS\n");
- + 	if (status < 0)
- + 	{
- + 		gpio_free(CKB_LCD_BL_PIN);
- + 		return;
- + 	}
- + 
- + 	status = gpio_request(CKB_LCD_PWR_PIN, "lcd pwr\n");
- + 	if (status < 0) {
- + 		gpio_free(CKB_LCD_BL_PIN);
- + 		gpio_free(CKB_BL_TPS_PIN);
- + 		return;
- + 	}
- + 
- + 	/* set backlight and LCD to output and turn them on */
- + 	gpio_direction_output(CKB_LCD_BL_PIN, 1);
- + 	gpio_direction_output(CKB_BL_TPS_PIN, 1);
- + 	gpio_direction_output(CKB_LCD_PWR_PIN, 1);
- + #endif
- + 
- + 	da8xx_pdata.fb_mapped_physaddr = FB_DATA_ADDRESS;
- + 	da8xx_pdata.fb_mapped_len = FB_MAP_SIZE;
- + 	if (am33xx_register_lcdc(&da8xx_pdata))
- + 		pr_info("Failed to register LCDC device\n");
- + 
- + 	return;
- + }
- + #endif
- + 
- + #ifdef CONFIG_CKB_DVI_SUPPORT
- + struct ckb_dvi_platform_data dvi_data = {
- + 	/* 3352 LCD controller supports upto WXGA (1366x768) */
- + 	.max_xres = 1366,
- + 	.max_yres = 768,
- + 	.connect_poll_interval = 500,					/* 500 ms */
- + 	.i2c_port = 1,
- + };
- + 
- + struct platform_device ckb_dvi_device = {
- + 	.name          = CKB_DVI_NAME,
- + 	.dev = {
- + 		.platform_data	= &dvi_data,
- + 	},
- + };
- + #endif
- + 
- + #ifdef CONFIG_CKB_3352_AUDIO
- + 
- + static u8 am335x_iis_serializer_direction1[] = {
- + 	INACTIVE_MODE,	INACTIVE_MODE,	TX_MODE,	RX_MODE,
- + 	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,
- + 	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,
- + 	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,
- + };
- + 
- + static struct snd_platform_data am335x_evm_snd_data1 = {
- + 	.tx_dma_offset	= 0x46400000,	/* McASP1 */
- + 	.rx_dma_offset	= 0x46400000,
- + 	.op_mode	= DAVINCI_MCASP_IIS_MODE,
- + 	.num_serializer	= ARRAY_SIZE(am335x_iis_serializer_direction1),
- + 	.tdm_slots	= 2,
- + 	.serial_dir	= am335x_iis_serializer_direction1,
- + 	.asp_chan_q	= EVENTQ_2,
- + 	.version	= MCASP_VERSION_3,
- + 	.txnumevt	= 1,
- + 	.rxnumevt	= 1,
- + };
- + #endif
- + 
- + #ifdef CONFIG_CKB_EXTCN_I2C1
- + static struct pinmux_config extcn_i2c1_pin_mux[] = {
- + 	{"uart0_ctsn.i2c1_sda", OMAP_MUX_MODE3 | AM33XX_INPUT_EN | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW },
- + 	{"uart0_rtsn.i2c1_scl", OMAP_MUX_MODE3 | AM33XX_INPUT_EN | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW },
- + 	{NULL, 0},
- + };
- + 
- + static struct i2c_board_info __initdata am335x_i2c1_boardinfo[] = {
- + };
- + #endif
- + 
- + #ifdef CONFIG_CKB_EXTCN_UART4
- + static struct pinmux_config extcn_uart4_pin_mux[] = {
- + 	{"uart0_ctsn.uart4_rxd", OMAP_MUX_MODE1 | AM33XX_INPUT_EN | AM33XX_PULL_DISA },
- + 	{"uart0_rtsn.uart4_txd", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT
- + 						       | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW },
- + 	{NULL, 0},
- + };
- + #endif
- + 
- + 
- + #ifdef CONFIG_CKB_EXTCN_CAN1
- + static struct pinmux_config d_can_gp_pin_mux[] = {
- + 	{"uart0_ctsn.d_can1_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
- + 	{"uart0_rtsn.d_can1_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
- + 	{NULL, 0},
- + };
- + 
- + static void d_can_init(void)
- + {
- + 	setup_pin_mux(d_can_gp_pin_mux);
- + 	am33xx_d_can_init(1);
- + }
- + #endif
- + 
- + #ifdef CONFIG_CKB_EXTCN_SPIDEV_SPI1
- + static struct pinmux_config extcn_spi1_pin_mux[] = {
- + 	{"mcasp0_aclkx.spi1_sclk", OMAP_MUX_MODE3 |  AM33XX_PULL_ENBL
- + 							| AM33XX_INPUT_EN },
- + 	{"mcasp0_fsx.spi1_d0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
- + 							| AM33XX_PULL_UP | AM33XX_INPUT_EN},
- + 	{"mcasp0_axr0.spi1_d1", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
- + 							| AM33XX_INPUT_EN },
- + 	{"mcasp0_ahclkr.spi1_cs0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
- + 							| AM33XX_PULL_UP | AM33XX_INPUT_EN},
- + 	{NULL, 0},
- + };
- + 
- + static struct spi_board_info am335x_spi1_slave_info[] = {
- + 	{
- + 		.modalias      = "spidev",
- + 		.irq           = -1,
- + 		.max_speed_hz  = 12000000,
- + 		.bus_num       = 2,
- + 		.chip_select   = 0,
- + 	},
- + };
- + #endif
- + 
- + static struct pinmux_config extcn_pin_mux[] = {
- + #ifdef CONFIG_CKB_EX_CN_PIN2_LCD_DATA12
- + 	{"lcd_data12.lcd_data12",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN2_A16
- + 	{"lcd_data12.gpmc_a16",	OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN2_EQEP1A_IN
- + 	{"lcd_data12.eQEP1A_in", OMAP_MUX_MODE2 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN2_MCASP0_ACLKR
- + 	{"lcd_data12.mcasp0_aclkr",	OMAP_MUX_MODE3 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN2_MCAP0_AXR2
- + 	{"lcd_data12.mcasp0_axr2",	OMAP_MUX_MODE4 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN2_PR1_MII0_RXLINK
- + 	{"lcd_data12.pr1_mii0_rxlink",	OMAP_MUX_MODE5 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN2_UART4_CTS
- + 	{"lcd_data12.uart4_ctsn",	OMAP_MUX_MODE6 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN2_OGPIO
- + 	{"lcd_data12.gpio0_8",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN2_IGPIO
- + 	{"lcd_data12.gpio0_8",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + 
- + #ifdef CONFIG_CKB_EX_CN_PIN4_LCD_DATA13
- + 	{"lcd_data13.lcd_data13",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN4_A17
- + 	{"lcd_data13.gpmc_a17",	OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN4_EQEP1B_IN
- + 	{"lcd_data13.eQEP1B_in", OMAP_MUX_MODE2 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN4_MCASP0_FSR
- + 	{"lcd_data13.mcasp0_fsr",	OMAP_MUX_MODE3 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN4_MCAP0_AXR3
- + 	{"lcd_data13.mcasp0_axr3",	OMAP_MUX_MODE4 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN2_PR1_MII0_RXER
- + 	{"lcd_data13.pr1_mii0_rxer",	OMAP_MUX_MODE5 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN4_UART4_RTS
- + 	{"lcd_data13.uart4_rtsn",	OMAP_MUX_MODE6 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN4_OGPIO
- + 	{"lcd_data13.gpio0_9",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN4_IGPIO
- + 	{"lcd_data13.gpio0_9",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + 
- + #ifdef CONFIG_CKB_EX_CN_PIN6_MCASP0_AHCLKR
- + 	{"mcasp0_ahclkr.mcasp0_ahclkr",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN6_EHRPWM0_SYNCI
- + 	{"mcasp0_ahclkr.ehrpwm0_synci", OMAP_MUX_MODE1 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN6_MCASP0_AXR2
- + 	{"mcasp0_ahclkr.mcasp0_axr2", OMAP_MUX_MODE2 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN6_SPI1_CS0
- + 	{"mcasp0_ahclkr.spi1_cs0",	OMAP_MUX_MODE3 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN6_ECAP2_IN_PWM2_OUT
- + 	{"mcasp0_ahclkr.ecap2_in_pwm2_out",	OMAP_MUX_MODE4 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN6_PR1_PRU0_PRU_R30_3
- + 	{"mcasp0_ahclkr.pr1_pru0_pru_r30_3",	OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN6_PR1_PRU0_PRU_R31_3
- + 	{"mcasp0_ahclkr.pr1_pru0_pru_r31_3",	OMAP_MUX_MODE6 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN6_OGPIO
- + 	{"mcasp0_ahclkr.gpio3_17",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN6_IGPIO
- + 	{"mcasp0_ahclkr.gpio3_17",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + 
- + #ifdef CONFIG_CKB_EX_CN_PIN10_MCASP0_FSR
- + 	{"mcasp0_fsr.mcasp0_fsr",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN10_EQEP0B_IN
- + 	{"mcasp0_fsr.eQEP0B_in", OMAP_MUX_MODE1 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN10_MCASP0_AXR3
- + 	{"mcasp0_fsr.mcasp0_axr3",	OMAP_MUX_MODE2 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN10_MCASP1_FSX
- + 	{"mcasp0_fsr.mcasp1_fsx",	OMAP_MUX_MODE3 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN10_EMU2
- + 	{"mcasp0_fsr.EMU2",	OMAP_MUX_MODE4 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN10_PR1_PRU0_PRU_R30_5
- + 	{"mcasp0_fsr.pr1_pru0_pru_r30_5",	OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN10_PR1_PRU0_PRU_R31_5
- + 	{"mcasp0_fsr.pr1_pru0_pru_r31_5",	OMAP_MUX_MODE6 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN10_OGPIO
- + 	{"mcasp0_fsr.gpio3_19",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN10_IGPIO
- + 	{"mcasp0_fsr.gpio3_19",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + 	
- + #ifdef CONFIG_CKB_EX_CN_PIN13_AD1
- + 	{"gpmc_ad1.gpmc_ad1",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN13_MMC1_DAT1
- + 	{"gpmc_ad1.mmc1_dat1", OMAP_MUX_MODE1 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN13_OGPIO
- + 	{"gpmc_ad1.gpio1_1",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN13_IGPIO
- + 	{"gpmc_ad1.gpio1_1",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + 	
- + #ifdef CONFIG_CKB_EX_CN_PIN14_AD0
- + 	{"gpmc_ad0.gpmc_ad0",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN14_MMC1_DAT0
- + 	{"gpmc_ad0.mmc1_dat0", OMAP_MUX_MODE1 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN14_OGPIO
- + 	{"gpmc_ad0.gpio1_0",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN14_IGPIO
- + 	{"gpmc_ad0.gpio1_0",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + 	
- + #ifdef CONFIG_CKB_EX_CN_PIN15_AD3
- + 	{"gpmc_ad3.gpmc_ad3",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN15_MMC1_DAT3
- + 	{"gpmc_ad3.mmc1_dat3", OMAP_MUX_MODE1 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN15_OGPIO
- + 	{"gpmc_ad3.gpio1_3",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN15_IGPIO
- + 	{"gpmc_ad3.gpio1_3",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + 
- + #ifdef CONFIG_CKB_EX_CN_PIN16_AD2
- + 	{"gpmc_ad2.gpmc_ad2",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN16_MMC1_DAT2
- + 	{"gpmc_ad2.mmc1_dat2", OMAP_MUX_MODE1 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN16_OGPIO
- + 	{"gpmc_ad2.gpio1_2",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN16_IGPIO
- + 	{"gpmc_ad2.gpio1_2",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + 
- + #ifdef CONFIG_CKB_EX_CN_PIN17_AD5
- + 	{"gpmc_ad5.gpmc_ad5",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN17_MMC1_DAT5
- + 	{"gpmc_ad5.mmc1_dat5", OMAP_MUX_MODE1 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN17_OGPIO
- + 	{"gpmc_ad5.gpio1_5",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN17_IGPIO
- + 	{"gpmc_ad5.gpio1_5",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + 
- + #ifdef CONFIG_CKB_EX_CN_PIN18_AD4
- + 	{"gpmc_ad4.gpmc_ad4",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN18_MMC1_DAT4
- + 	{"gpmc_ad4.mmc1_dat4", OMAP_MUX_MODE1 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN18_OGPIO
- + 	{"gpmc_ad4.gpio1_4",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN18_IGPIO
- + 	{"gpmc_ad4.gpio1_4",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + 
- + #ifdef CONFIG_CKB_EX_CN_PIN19_AD7
- + 	{"gpmc_ad7.gpmc_ad7",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN19_MMC1_DAT7
- + 	{"gpmc_ad7.mmc1_dat7", OMAP_MUX_MODE1 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN19_OGPIO
- + 	{"gpmc_ad7.gpio1_7",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN19_IGPIO
- + 	{"gpmc_ad7.gpio1_7",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + 
- + #ifdef CONFIG_CKB_EX_CN_PIN20_AD6
- + 	{"gpmc_ad6.gpmc_ad6",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN20_MMC1_DAT6
- + 	{"gpmc_ad6.mmc1_dat6", OMAP_MUX_MODE1 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN20_OGPIO
- + 	{"gpmc_ad6.gpio1_6",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN20_IGPIO
- + 	{"gpmc_ad6.gpio1_6",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + 
- + #ifdef CONFIG_CKB_EX_CN_PIN21_GPMC_CSN1
- + 	{"gpmc_csn1.gpmc_csn1",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN21_GPMC_CLK
- + 	{"gpmc_csn1.gpmc_clk",	OMAP_MUX_MODE1 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN21_MMC1_CLK
- + 	{"gpmc_csn1.mmc1_clk", OMAP_MUX_MODE2 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN21_PR1_EDIO_DATA_IN6
- + 	{"mcasp0_fsr.pr1_edio_data_in6",	OMAP_MUX_MODE3 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN21_PR1_EDIO_DATA_OUT6
- + 	{"mcasp0_fsr.pr1_edio_data_out6",	OMAP_MUX_MODE4 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN21_PR1_PRU1_PRU_R30_12
- + 	{"mcasp0_fsr.pr1_pru1_pru_r30_12",	OMAP_MUX_MODE4 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN21_PR1_PRU1_PRU_R31_12
- + 	{"mcasp0_fsr.pr1_pru1_pru_r31_12",	OMAP_MUX_MODE4 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN21_OGPIO
- + 	{"gpmc_csn1.gpio1_30",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN21_IGPIO
- + 	{"gpmc_csn1.gpio1_30",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + 
- + #ifdef CONFIG_CKB_EX_CN_PIN22_XDMA_EVENT_INTR0
- + 	{"xdma_event_intr0.xdma_event_intr0",	OMAP_MUX_MODE0 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN22_TIM4
- + 	{"xdma_event_intr0.timer4", OMAP_MUX_MODE2 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN22_CLKOUT1
- + 	{"xdma_event_intr0.clkout1",	OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN22_SPI1_CS1
- + 	{"xdma_event_intr0.spi1_cs1",	OMAP_MUX_MODE4 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN22_PR1_PRU1_PRU_R31_16
- + 	{"xdma_event_intr0.pr1_pru1_pru_r31_16",	OMAP_MUX_MODE5 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN22_EMU2
- + 	{"xdma_event_intr0.EMU2",	OMAP_MUX_MODE6 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN22_OGPIO
- + 	{"xdma_event_intr0.gpio0_19",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN22_IGPIO
- + 	{"xdma_event_intr0.gpio0_19",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + 
- + #ifdef CONFIG_CKB_EX_CN_PIN23_GPMC_WEN
- + 	{"gpmc_wen.gpmc_wen", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN23_TIM6
- + 	{"gpmc_wen.timer6", OMAP_MUX_MODE2 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN23_OGPIO
- + 	{"gpmc_wen.gpio2_4",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN23_IGPIO
- + 	{"gpmc_wen.gpio2_4",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + 
- + #ifdef CONFIG_CKB_EX_CN_PIN24_XDMA_EVENT_INTR1
- + 	{"xdma_event_intr1.xdma_event_intr1",	OMAP_MUX_MODE0 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN24_TCLKIN
- + 	{"xdma_event_intr1.tclkin", OMAP_MUX_MODE2 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN24_CLKOUT2
- + 	{"xdma_event_intr1.clkout2",	OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN24_TIM7
- + 	{"xdma_event_intr1.timer7",	OMAP_MUX_MODE4 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN24_PR1_PRU0_PRU_R31_16
- + 	{"xdma_event_intr1.pr1_pru0_pru_r31_16",	OMAP_MUX_MODE5 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN24_EMU3
- + 	{"xdma_event_intr1.EMU3",	OMAP_MUX_MODE6 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN24_OGPIO
- + 	{"xdma_event_intr1.gpio0_20",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN24_IGPIO
- + 	{"xdma_event_intr1.gpio0_20",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + 
- + #ifdef CONFIG_CKB_EX_CN_PIN25_GPMC_OEN_REN
- + 	{"gpmc_oen_ren.gpmc_oen_ren",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN25_TIM7
- + 	{"gpmc_oen_ren.timer7",	OMAP_MUX_MODE2 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN25_OGPIO
- + 	{"gpmc_oen_ren.gpio2_3",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN25_IGPIO
- + 	{"gpmc_oen_ren.gpio2_3",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + 
- + #ifdef CONFIG_CKB_EX_CN_PIN26_UART0_CTSN
- + 	{"uart0_ctsn.uart0_ctsn",	OMAP_MUX_MODE0 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN26_UART4_RXD
- + 	{"uart0_ctsn.uart4_rxd", OMAP_MUX_MODE1 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN26_DCAN1_TX
- + 	{"uart0_ctsn.d_can1_tx",	OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN26_I2C1_SDA
- + 	{"uart0_ctsn.i2c1_sda",	OMAP_MUX_MODE3 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN26_SPI1_D0
- + 	{"uart0_ctsn.spi1_d0",	OMAP_MUX_MODE4 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN26_TIM7
- + 	{"uart0_ctsn.timer7",	OMAP_MUX_MODE5 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN26_PR1_EDC_SYNC0_OUT
- + 	{"uart0_ctsn.pr1_edc_sync0_out",	OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN26_OGPIO
- + 	{"uart0_ctsn.gpio1_8",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN26_IGPIO
- + 	{"uart0_ctsn.gpio1_8",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + 
- + #ifdef CONFIG_CKB_EX_CN_PIN27_GPMC_ADVN_ALE
- + 	{"gpmc_advn_ale.gpmc_advn_ale",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN27_TIM4
- + 	{"gpmc_advn_ale.timer4",	OMAP_MUX_MODE2 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN27_OGPIO
- + 	{"gpmc_advn_ale.gpio2_2",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN27_IGPIO
- + 	{"gpmc_advn_ale.gpio2_2",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + 
- + #ifdef CONFIG_CKB_EX_CN_PIN28_UART0_RTSN
- + 	{"uart0_rtsn.uart0_rtsn",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN28_UART4_TXD
- + 	{"uart0_rtsn.uart4_txd", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN28_DCAN1_RX
- + 	{"uart0_rtsn.d_can1_rx",	OMAP_MUX_MODE2 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN28_I2C1_SCL
- + 	{"uart0_rtsn.i2c1_scl",	OMAP_MUX_MODE3 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN28_SPI1_D1
- + 	{"uart0_rtsn.spi1_d1",	OMAP_MUX_MODE4 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN28_SPI1_CS0
- + 	{"uart0_rtsn.spi1_cs0",	OMAP_MUX_MODE5 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN28_PR1_EDC_SYNC1_OUT
- + 	{"uart0_rtsn.pr1_edc_sync1_out",	OMAP_MUX_MODE6 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN28_OGPIO
- + 	{"uart0_rtsn.gpio1_9",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN28_IGPIO
- + 	{"uart0_rtsn.gpio1_9",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + 
- + #ifdef CONFIG_CKB_EX_CN_PIN29_GPMC_A1
- + 	{"gpmc_a1.gpmc_a1",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN29_MII2_RXDV
- + 	{"gpmc_a1.mii2_rxdv", OMAP_MUX_MODE1 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN29_RGMII2_RCTL
- + 	{"gpmc_a1.rgmii2_rctl",	OMAP_MUX_MODE2 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN29_MMC2_D0
- + 	{"gpmc_a1.mmc2_dat0",	OMAP_MUX_MODE3 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN29_GPMC_A17
- + 	{"gpmc_a1.gpmc_a17",	OMAP_MUX_MODE4 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN29_PR1_MII1_TXD3
- + 	{"gpmc_a1.pr1_mii1_txd3",	OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN29_EHRPWM0_SYNCO
- + 	{"gpmc_a1.ehrpwm0_synco",	OMAP_MUX_MODE6 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN29_OGPIO
- + 	{"gpmc_a1.gpio1_17",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN29_IGPIO
- + 	{"gpmc_a1.gpio1_17",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + 
- + #ifdef CONFIG_CKB_EX_CN_PIN30_ECAP0_IN_PWM0_OUT
- + 	{"ecap0_in_pwm0_out.ecap0_in_pwm0_out",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN30_UART3_TXD
- + 	{"ecap0_in_pwm0_out.uart3_txd", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN30_SPI1_CS1
- + 	{"ecap0_in_pwm0_out.spi1_cs1",	OMAP_MUX_MODE2 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN30_PR1_ECAP0_ECAP_CAPIN_APWM_O
- + 	{"ecap0_in_pwm0_out.pr1_ecap0_ecap_capin_apwm_o",	OMAP_MUX_MODE3 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN30_SPI1_SCK
- + 	{"ecap0_in_pwm0_out.spi1_sclk",	OMAP_MUX_MODE4 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN30_MMC0_SDWP
- + 	{"ecap0_in_pwm0_out.mmc0_sdwp",	OMAP_MUX_MODE5 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN30_XDMA_EVENT_INTR2
- + 	{"ecap0_in_pwm0_out.xdma_event_intr2",	OMAP_MUX_MODE6 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN30_OGPIO
- + 	{"ecap0_in_pwm0_out.gpio0_7",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN30_IGPIO
- + 	{"ecap0_in_pwm0_out.gpio0_7",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + 
- + #ifdef CONFIG_CKB_EX_CN_PIN31_MCASP0_AXR0
- + 	{"mcasp0_axr0.mcasp0_axr0",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN31_EHRPWM0_TRIPZONE_INPUT
- + 	{"mcasp0_axr0.ehrpwm0_tripzone_input", OMAP_MUX_MODE1 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN31_SPI1_D1
- + 	{"mcasp0_axr0.spi1_d1", OMAP_MUX_MODE3 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN31_MMC2_SDCD
- + 	{"mcasp0_axr0.mmc2_sdcd",	OMAP_MUX_MODE4 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN31_PR1_PRU0_PRU_R30_2
- + 	{"mcasp0_axr0.pr1_pru0_pru_r30_2",	OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN31_PR1_PRU0_PRU_R31_2
- + 	{"mcasp0_axr0.pr1_pru0_pru_r31_2",	OMAP_MUX_MODE6 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN31_OGPIO
- + 	{"mcasp0_axr0.gpio3_16",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN31_IGPIO
- + 	{"mcasp0_axr0.gpio3_16",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + 
- + #ifdef CONFIG_CKB_EX_CN_PIN33_MCASP0_AXR1
- + 	{"mcasp0_axr1.mcasp0_axr1",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN33_EQEP0_INDEX
- + 	{"mcasp0_axr1.eQEP0_index", OMAP_MUX_MODE1 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN33_MCASP1_AXR0
- + 	{"mcasp0_axr1.mcasp1_axr0",	OMAP_MUX_MODE3 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN33_EMU3
- + 	{"mcasp0_axr1.EMU3",	OMAP_MUX_MODE4 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN33_PR1_PRU0_PRU_R30_6
- + 	{"mcasp0_axr1.pr1_pru0_pru_r30_6",	OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN33_PR1_PRU0_PRU_R31_6
- + 	{"mcasp0_axr1.pr1_pru0_pru_r31_6",	OMAP_MUX_MODE6 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN33_OGPIO
- + 	{"mcasp0_axr1.gpio3_20",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN33_IGPIO
- + 	{"mcasp0_axr1.gpio3_20",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + 
- + #ifdef CONFIG_CKB_EX_CN_PIN34_MCASP0_AHCLKX
- + 	{"mcasp0_ahclkx.mcasp0_ahclkx",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN34_EQEP0_STROBE
- + 	{"mcasp0_ahclkx.eQEP0_strobe", OMAP_MUX_MODE1 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN34_MCASP0_AXR3
- + 	{"mcasp0_ahclkx.mcasp0_axr3",	OMAP_MUX_MODE2 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN34_MCASP1_AXR1
- + 	{"mcasp0_ahclkx.mcasp1_axr1",	OMAP_MUX_MODE3 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN34_EMU4
- + 	{"mcasp0_ahclkx.EMU4",	OMAP_MUX_MODE4 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN34_PR1_PRU0_PRU_R30_7
- + 	{"mcasp0_ahclkx.pr1_pru0_pru_r30_7",	OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN34_PR1_PRU0_PRU_R31_7
- + 	{"mcasp0_ahclkx.pr1_pru0_pru_r31_7",	OMAP_MUX_MODE6 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN34_OGPIO
- + 	{"mcasp0_ahclkx.gpio3_21",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN34_IGPIO
- + 	{"mcasp0_ahclkx.gpio3_21",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + 	
- + #ifdef CONFIG_CKB_EX_CN_PIN36_MCASP0_ACLKX
- + 	{"mcasp0_aclkx.mcasp0_aclkx",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN36_EHRPWM0A
- + 	{"mcasp0_aclkx.ehrpwm0A", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN36_SPI1_SCLK
- + 	{"mcasp0_aclkx.spi1_sclk",	OMAP_MUX_MODE3 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN36_MMC0_SDCD
- + 	{"mcasp0_aclkx.mmc0_sdcd",	OMAP_MUX_MODE4 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN36_PR1_PRU0_PRU_R30_0
- + 	{"mcasp0_aclkx.pr1_pru0_pru_r30_0",	OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN36_PR1_PRU0_PRU_R31_0
- + 	{"mcasp0_aclkx.pr1_pru0_pru_r31_0",	OMAP_MUX_MODE6 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN36_OGPIO
- + 	{"mcasp0_aclkx.gpio3_14",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN36_IGPIO
- + 	{"mcasp0_aclkx.gpio3_14",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + 
- + #ifdef CONFIG_CKB_EX_CN_PIN38_MCASP0_FSX
- + 	{"mcasp0_fsx.mcasp0_fsx",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN38_EHRPWM0B
- + 	{"mcasp0_fsx.ehrpwm0B", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN38_SPI1_D0
- + 	{"mcasp0_fsx.spi1_d0",	OMAP_MUX_MODE3 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN38_MMC1_SDCD
- + 	{"mcasp0_fsx.mmc1_sdcd",	OMAP_MUX_MODE4 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN38_PR1_PRU0_PRU_R30_1
- + 	{"mcasp0_fsx.pr1_pru0_pru_r30_1",	OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN38_PR1_PRU0_PRU_R31_1
- + 	{"mcasp0_fsx.pr1_pru0_pru_r31_1",	OMAP_MUX_MODE6 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN38_OGPIO
- + 	{"mcasp0_fsx.gpio3_15",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN38_IGPIO
- + 	{"mcasp0_fsx.gpio3_15",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + 	{NULL, 0},
- + };
- + 
- + static struct pinmux_config wlan_cn_pin_mux[] = {
- + #ifdef CONFIG_CKB_WLAN_CN_PIN24_UART1_TXD
- + 	{"uart1_txd.uart1_txd",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_WLAN_CN_PIN24_MMC2_SDWP
- + 	{"uart1_txd.mmc2_sdwp",	OMAP_MUX_MODE1 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_WLAN_CN_PIN24_DCAN1_TX
- + 	{"uart1_txd.dcan1_rx",	OMAP_MUX_MODE2 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_WLAN_CN_PIN24_I2C1_SCL
- + 	{"uart1_txd.i2c1_scl",	OMAP_MUX_MODE3 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_WLAN_CN_PIN24_PR1_UART0_TXD
- + 	{"uart1_txd.pr1_uart0_txd",	OMAP_MUX_MODE5 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_WLAN_CN_PIN24_PR1_PRU0_PRU_R31_16
- + 	{"uart1_txd.pr1_pru0_pru_r31_16", OMAP_MUX_MODE6 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_WLAN_CN_PIN24_OGPIO
- + 	{"uart1_txd.gpio0_15", OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_WLAN_CN_PIN24_IGPIO
- + 	{"uart1_txd.gpio0_15", OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + 
- + #ifdef CONFIG_CKB_WLAN_CN_PIN26_UART1_RXD
- + 	{"uart1_rxd.uart1_rxd",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_WLAN_CN_PIN26_MMC1_SDWP
- + 	{"uart1_rxd.mmc1_sdwp",	OMAP_MUX_MODE1 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_WLAN_CN_PIN26_DCAN0_TX
- + 	{"uart1_rxd.dcan1_tx",	OMAP_MUX_MODE2 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_WLAN_CN_PIN26_I2C1_SDA
- + 	{"uart1_rxd.i2c1_sda",	OMAP_MUX_MODE3 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_WLAN_CN_PIN26_PR1_UART0_RXD
- + 	{"uart1_rxd.pr1_uart0_rxd",	OMAP_MUX_MODE5 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_WLAN_CN_PIN26_PR1_PRU1_PRU_R31_16
- + 	{"uart1_rxd.pr1_pru1_pru_r31_16", OMAP_MUX_MODE6 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_WLAN_CN_PIN26_OGPIO
- + 	{"uart1_rxd.gpio0_14", OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_WLAN_CN_PIN26_IGPIO
- + 	{"uart1_rxd.gpio0_14", OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + 
- + #ifdef CONFIG_CKB_WLAN_CN_PIN28_UART1_CTSN
- + 	{"uart1_ctsn.uart1_ctsn",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_WLAN_CN_PIN28_TIMER6
- + 	{"uart1_ctsn.timer6",	OMAP_MUX_MODE1 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_WLAN_CN_PIN28_DCAN0_TX
- + 	{"uart1_ctsn.dcan0_tx",	OMAP_MUX_MODE2 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_WLAN_CN_PIN28_I2C2_SDA
- + 	{"uart1_ctsn.i2c2_sda",	OMAP_MUX_MODE3 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_WLAN_CN_PIN28_SPI1_CS0
- + 	{"uart1_ctsn.spi1_cs0",	OMAP_MUX_MODE4 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_WLAN_CN_PIN28_PR1_UART0_CTS_N
- + 	{"uart1_ctsn.pr1_uart0_cts_n",	OMAP_MUX_MODE5 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_WLAN_CN_PIN28_PR1_EDC_LATCH0_IN
- + 	{"uart1_ctsn.pr1_edc_latch0_in", OMAP_MUX_MODE6 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_WLAN_CN_PIN28_OGPIO
- + 	{"uart1_ctsn.gpio0_12", OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_WLAN_CN_PIN28_IGPIO
- + 	{"uart1_ctsn.gpio0_12", OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + 	
- + #ifdef CONFIG_CKB_WLAN_CN_PIN30_UART1_RTSN
- + 	{"uart1_rtsn.uart1_rtsn",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_WLAN_CN_PIN30_TIMER5
- + 	{"uart1_rtsn.timer5",	OMAP_MUX_MODE1 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_WLAN_CN_PIN30_DCAN0_RX
- + 	{"uart1_rtsn.dcan0_rx",	OMAP_MUX_MODE2 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_WLAN_CN_PIN30_I2C2_SCL
- + 	{"uart1_rtsn.i2c2_scl",	OMAP_MUX_MODE3 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_WLAN_CN_PIN30_SPI1_CS1
- + 	{"uart1_rtsn.spi1_cs1",	OMAP_MUX_MODE4 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_WLAN_CN_PIN30_PR1_UART0_RTS_N
- + 	{"uart1_rtsn.pr1_uart0_rts_n",	OMAP_MUX_MODE5 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_WLAN_CN_PIN30_PR1_EDC_LATCH1_IN
- + 	{"uart1_rtsn.pr1_edc_latch1_in", OMAP_MUX_MODE6 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_WLAN_CN_PIN30_OGPIO
- + 	{"uart1_rtsn.gpio0_13", OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
- + #endif
- + #ifdef CONFIG_CKB_WLAN_CN_PIN30_IGPIO
- + 	{"uart1_rtsn.gpio0_13", OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
- + #endif
- + 
- + 	{NULL, 0},
- + };
- + 
- + 
- + void configure_extcn_gpio_mode(void)
- + {
- + #ifdef CONFIG_CKB_EX_CN_PIN2_OGPIO
- + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(0, 8), 0);
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN2_IGPIO
- + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(0, 8);
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN4_OGPIO
- + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(0, 9), 0);
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN4_IGPIO
- + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(0, 9);
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN6_OGPIO
- + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(3, 17), 0);
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN6_IGPIO
- + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(3, 17));
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN10_OGPIO
- + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(3, 19), 0);
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN10_IGPIO
- + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(3, 19));
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN13_OGPIO
- + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(1, 1), 0);
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN13_IGPIO
- + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(1, 1));
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN14_OGPIO
- + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(1, 0), 0);
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN14_IGPIO
- + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(1, 0));
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN15_OGPIO
- + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(1, 3), 0);
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN15_IGPIO
- + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(1, 3));
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN16_OGPIO
- + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(1, 2), 0);
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN16_IGPIO
- + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(1, 2));
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN17_OGPIO
- + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(1, 5), 0);
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN17_IGPIO
- + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(1, 5));
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN18_OGPIO
- + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(1, 4), 0);
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN18_IGPIO
- + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(1, 4));
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN19_OGPIO
- + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(1, 7), 0);
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN19_IGPIO
- + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(1, 7));
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN20_OGPIO
- + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(1, 6), 0);
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN20_IGPIO
- + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(1, 6));
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN21_OGPIO
- + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(1, 30), 0);
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN21_IGPIO
- + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(1, 30));
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN22_OGPIO
- + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(0, 19), 0);
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN22_IGPIO
- + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(0, 19));
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN23_OGPIO
- + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(2, 4), 0);
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN23_IGPIO
- + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(2, 4));
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN24_OGPIO
- + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(0, 20), 0);
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN24_IGPIO
- + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(0, 20));
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN25_OGPIO
- + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(2, 3), 0);
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN25_IGPIO
- + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(2, 3));
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN26_OGPIO
- + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(1, 8), 0);
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN26_IGPIO
- + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(1, 8));
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN27_OGPIO
- + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(2, 2), 0);
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN27_IGPIO
- + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(2, 2));
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN28_OGPIO
- + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(1, 9), 0);
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN28_IGPIO
- + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(1, 9));
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN29_OGPIO
- + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(1, 17), 0);
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN29_IGPIO
- + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(1, 17));
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN30_OGPIO
- + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(0, 7), 0);
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN30_IGPIO
- + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(0, 7));
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN31_OGPIO
- + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(3, 16), 0);
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN31_IGPIO
- + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(3, 16));
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN33_OGPIO
- + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(3, 20), 0);
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN33_IGPIO
- + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(3, 20));
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN34_OGPIO
- + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(3, 21), 0);
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN34_IGPIO
- + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(3, 21));
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN36_OGPIO
- + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(3, 14), 0);
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN36_IGPIO
- + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(3, 14));
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN38_OGPIO
- + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(3, 15), 0);
- + #endif
- + #ifdef CONFIG_CKB_EX_CN_PIN38_IGPIO
- + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(3, 15));
- + #endif
- + }
- + 
- + void configure_wlan_cn_gpio_mode(void)
- + {
- + #ifdef CONFIG_CKB_WLAN_CN_PIN24_OGPIO
- + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(0, 15), 0);
- + #endif
- + #ifdef CONFIG_CKB_WLAN_CN_PIN24_IGPIO
- + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(0, 15));
- + #endif
- + #ifdef CONFIG_CKB_WLAN_CN_PIN26_OGPIO
- + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(0, 14), 0);
- + #endif
- + #ifdef CONFIG_CKB_WLAN_CN_PIN26_IGPIO
- + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(0, 14));
- + #endif
- + #ifdef CONFIG_CKB_WLAN_CN_PIN28_OGPIO
- + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(0, 12), 0);
- + #endif
- + #ifdef CONFIG_CKB_WLAN_CN_PIN28_IGPIO
- + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(0, 12));
- + #endif
- + #ifdef CONFIG_CKB_WLAN_CN_PIN30_OGPIO
- + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(0, 13), 0);
- + #endif
- + #ifdef CONFIG_CKB_WLAN_CN_PIN30_IGPIO
- + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(0, 13));
- + #endif
- + }
- + 
- + 
- + #ifdef CONFIG_CKB_EXTCN_ADC
- + int am33xx_register_mfd_tscadc(struct mfd_tscadc_board *pdata);
- + 
- + static struct adc_data am335x_adc_data = {
- + 	.adc_channels = 8,
- + };
- + 
- + static struct mfd_tscadc_board tscadc = {
- +     .adc_init = &am335x_adc_data,
- + };
- + #endif
- + 
- + void __iomem *am33xx_emif_base;
- + 
- + void __iomem * __init am33xx_get_mem_ctlr(void)
- + {
- + 
- + 	am33xx_emif_base = ioremap(AM33XX_EMIF0_BASE, SZ_32K);
- + 
- + 	if (!am33xx_emif_base)
- + 		pr_warning("%s: Unable to map DDR2 controller",	__func__);
- + 
- + 	return am33xx_emif_base;
- + }
- + 
- + void __iomem *am33xx_get_ram_base(void)
- + {
- + 	return am33xx_emif_base;
- + }
- + 
- + void __iomem *am33xx_gpio0_base;
- + 
- + void __iomem *am33xx_get_gpio0_base(void)
- + {
- + 	am33xx_gpio0_base = ioremap(AM33XX_GPIO0_BASE, SZ_4K);
- + 
- + 	return am33xx_gpio0_base;
- + }
- + 
- + static struct resource am33xx_cpuidle_resources[] = {
- + 	{
- + 		.start		= AM33XX_EMIF0_BASE,
- + 		.end		= AM33XX_EMIF0_BASE + SZ_32K - 1,
- + 		.flags		= IORESOURCE_MEM,
- + 	},
- + };
- + 
- + /* AM33XX devices support DDR2 power down */
- + static struct am33xx_cpuidle_config am33xx_cpuidle_pdata = {
- + 	.ddr2_pdown	= 1,
- + };
- + 
- + static struct platform_device am33xx_cpuidle_device = {
- + 	.name			= "cpuidle-am33xx",
- + 	.num_resources		= ARRAY_SIZE(am33xx_cpuidle_resources),
- + 	.resource		= am33xx_cpuidle_resources,
- + 	.dev = {
- + 		.platform_data	= &am33xx_cpuidle_pdata,
- + 	},
- + };
- + 
- + static void __init ckb_cpuidle_init(void)
- + {
- + 	int ret;
- + 
- + 	am33xx_cpuidle_pdata.emif_base = am33xx_get_mem_ctlr();
- + 
- + 	ret = platform_device_register(&am33xx_cpuidle_device);
- + 
- + 	if (ret)
- + 		pr_warning("AM33XX cpuidle registration failed\n");
- + 
- + }
- + 
- + void ckb_setup_lan(void)
- + {
- + 	char macaddr[ETH_ALEN];
- + 
- + 	/* 1st get the MAC address from EEPROM */
- + 	if (get_mac_address(CKB_EMAC_MAC_OFFSET, macaddr) != 0) {
- + 		pr_warning("Couldn't get MAC address from EEPROM\n");
- + 	}
- + 	am33xx_cpsw_init(AM33XX_CPSW_MODE_RGMII, macaddr, &save_mac_addr);
- + }
- + 
- + static void __init ckb3352_init(void)
- + {
- + 	pr_info("The board is CKB 3352 with DDR3");
- + 
- + 	ckb_cpuidle_init();
- + 	am33xx_mux_init(NULL);
- + 	omap_serial_init();
- + 
- + 	ckb_i2c_init();
- + 	omap_sdrc_init(NULL, NULL);
- + 	usb_musb_init(&musb_board_data);
- + 			 
- + 	usb0_init();
- + 	usb1_init();
- + 	
- + 	/* init mmc controller */
- + 	omap2_hsmmc_init();
- + 	mmc0_init();
- + #ifdef CONFIG_SUPPORT_CMJ100
- + 	ckb_cmj100_init();
- + #endif
- + 	rgmii1_init();
- + #if defined(CONFIG_CKB_LCD_SUPPORT) || defined(CONFIG_CKB_DVI_SUPPORT)
- + 	lcdc_init();
- + #endif
- + #ifdef CONFIG_CKB_DVI_SUPPORT
- + 	if (platform_device_register(&ckb_dvi_device))
- + 		pr_warning("CKB DVI device registration failed\n");
- + #endif
- + #ifdef CONFIG_SUPPORT_CKB_LED
- + 	gpio_led_init();
- + #endif
- + 	/* TPS65217 regulator has full constraints */
- + 	regulator_has_full_constraints();
- + 
- + #ifdef CONFIG_PHYLIB
- + 	/* Atheros Tx Clk delay Phy fixup */
- + 	phy_register_fixup_for_uid(AM335X_EVM_PHY_ID, AM335X_EVM_PHY_MASK,
- + 				   am33xx_evm_tx_clk_dly_phy_fixup);
- + #endif
- + 	/* SmartReflex also requires board information. */
- + 	am33xx_sr_init();
- + #ifdef CONFIG_SUPPORT_GPMC_CS1_MEM
- + 	gpmc_cs1_mux_enable();
- + 	ckb_setup_ex_cn_cs1();
- + #endif	
- + 	ckb_setup_nor();
- + 	am335x_rtc_init();
- + 	
- + #ifdef CONFIG_CKB_EXTCN_I2C1
- + 	setup_pin_mux(extcn_i2c1_pin_mux);
- + 	omap_register_i2c_bus(2, 48, am335x_i2c1_boardinfo,
- + 				ARRAY_SIZE(am335x_i2c1_boardinfo));
- + #endif
- + #ifdef CONFIG_CKB_EXTCN_UART4
- + 	setup_pin_mux(extcn_uart4_pin_mux);
- + #endif
- + #ifdef CONFIG_CKB_EXTCN_CAN1
- + 	d_can_init();
- + #endif
- + #ifdef CONFIG_CKB_EXTCN_GPIO_2628
- + 	setup_pin_mux(extcn_gp1_8_9_pin_mux);
- + #endif
- + #ifdef CONFIG_CKB_EXTCN_SPIDEV_SPI1
- + 	setup_pin_mux(extcn_spi1_pin_mux);
- + 	spi_register_board_info(am335x_spi1_slave_info,
- + 			ARRAY_SIZE(am335x_spi1_slave_info));
- + #endif
- + #ifdef CONFIG_CKB_EXTCN_ADC
- + 	if (am33xx_register_mfd_tscadc(&tscadc))
- + 		pr_err("failed to register touchscreen device\n");
- + #endif
- + 	setup_pin_mux(extcn_pin_mux);
- + 	configure_extcn_gpio_mode();
- + 	setup_pin_mux(wlan_cn_pin_mux);
- + 	configure_wlan_cn_gpio_mode();
- + 
- + 	/* Create an alias for icss clock */
- + 	if (clk_add_alias("pruss", NULL, "pruss_uart_gclk", NULL))
- + 		pr_warn("failed to create an alias: icss_uart_gclk --> pruss\n");
- + 	/* Create an alias for gfx/sgx clock */
- + 	if (clk_add_alias("sgx_ck", NULL, "gfx_fclk", NULL))
- + 		pr_warn("failed to create an alias: gfx_fclk --> sgx_ck\n");
- + }
- + 
- + static int ckb_late_init(void)
- + {
- + 	board_nor_init(ckb_norflash_partition, ARRAY_SIZE(ckb_norflash_partition), 0);
- + 	ckb_setup_lan();
- + 	return 0;
- + }
- + late_initcall(ckb_late_init);
- + 
- + 
- + int ckb_add_fbaddr(phys_addr_t start, phys_addr_t size)
- + {
- + 	FB_DATA_ADDRESS = start;
- + 	FB_MAP_SIZE = size;
- + 	return 0;
- + }
- + 
- + static void __init ckb3352_map_io(void)
- + {
- + 	omap2_set_globals_am33xx();
- + 	omapam33xx_map_common_io();
- + 	if(FB_MAP_SIZE != 0)
- + 	{
- + 		/* map FB */
- + 		struct map_desc io_desc;
- + 		
- + 		io_desc.pfn = __phys_to_pfn(FB_DATA_ADDRESS);
- + 		io_desc.virtual = (unsigned long)__va(FB_DATA_ADDRESS);
- + 		io_desc.length = FB_MAP_SIZE;
- + 		io_desc.type = MT_DEVICE;
- + 	
- + 		iotable_init(&io_desc,	1);
- + #if 0
- + 		FB_DATA_VADDRESS = (unsigned long)ioremap(FB_DATA_ADDRESS, FB_MAP_SIZE);
- + 		if(!FB_DATA_VADDRESS)
- + 		{
- + 			printk("Error: FB adress couldn't be mapped\n");
- + 			FB_DATA_ADDRESS = 0;
- + 		}
- + #else
- + 		FB_DATA_VADDRESS = io_desc.virtual;
- + #endif
- + 	}
- + }
- + 
- + asmlinkage long sys_ckb3352_change_mux(const char __user *pin_name, unsigned int mux_mode,
- + 				  unsigned int flags)
- + {
- + 	if(mux_mode < 0 || mux_mode > 7 || flags <= 7)
- + 		return -1;
- + 	
- + 	if(omap_mux_init_signal(pin_name, mux_mode | flags) != 0)
- + 	{
- + 		printk("Error: Setting mux %s filed\n", pin_name);
- + 		return -2;
- + 	}
- + 	return 0;
- + }
- + 
- + MACHINE_START(CKB_3352, "Computex Kumikomi Board CKB-3352")
- + 	/* Maintainer: Computex Co., Ltd. www.computex.co.jp */
- + 	.atag_offset	= 0x100,
- + 	.map_io		= ckb3352_map_io,
- + 	.init_early	= am33xx_init_early,
- + 	.init_irq	= ti81xx_init_irq,
- + 	.handle_irq     = omap3_intc_handle_irq,
- + 	.timer		= &omap3_am33xx_timer,
- + 	.init_machine	= ckb3352_init,
- + MACHINE_END
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/clkt_clksel.c linux-3.2.1/arch/arm/mach-ckb_3352/clkt_clksel.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/clkt_clksel.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/clkt_clksel.c	2014-05-15 13:25:13.859874528 +0900
- ***************
- *** 0 ****
- --- 1,509 ----
- + /*
- +  * clkt_clksel.c - OMAP2/3/4 clksel clock functions
- +  *
- +  * Copyright (C) 2005-2008 Texas Instruments, Inc.
- +  * Copyright (C) 2004-2010 Nokia Corporation
- +  *
- +  * Contacts:
- +  * Richard Woodruff <r-woodruff2@ti.com>
- +  * Paul Walmsley
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  *
- +  *
- +  * clksel clocks are clocks that do not have a fixed parent, or that
- +  * can divide their parent's rate, or possibly both at the same time, based
- +  * on the contents of a hardware register bitfield.
- +  *
- +  * All of the various mux and divider settings can be encoded into
- +  * struct clksel* data structures, and then these can be autogenerated
- +  * from some hardware database for each new chip generation.  This
- +  * should avoid the need to write, review, and validate a lot of new
- +  * clock code for each new chip, since it can be exported from the SoC
- +  * design flow.  This is now done on OMAP4.
- +  *
- +  * The fusion of mux and divider clocks is a software creation.  In
- +  * hardware reality, the multiplexer (parent selection) and the
- +  * divider exist separately.  XXX At some point these clksel clocks
- +  * should be split into "divider" clocks and "mux" clocks to better
- +  * match the hardware.
- +  *
- +  * (The name "clksel" comes from the name of the corresponding
- +  * register field in the OMAP2/3 family of SoCs.)
- +  *
- +  * XXX Currently these clocks are only used in the OMAP2/3/4 code, but
- +  * many of the OMAP1 clocks should be convertible to use this
- +  * mechanism.
- +  */
- + #undef DEBUG
- + 
- + #include <linux/kernel.h>
- + #include <linux/errno.h>
- + #include <linux/clk.h>
- + #include <linux/io.h>
- + 
- + #include <plat/clock.h>
- + 
- + #include "clock.h"
- + 
- + /* Private functions */
- + 
- + /**
- +  * _get_clksel_by_parent() - return clksel struct for a given clk & parent
- +  * @clk: OMAP struct clk ptr to inspect
- +  * @src_clk: OMAP struct clk ptr of the parent clk to search for
- +  *
- +  * Scan the struct clksel array associated with the clock to find
- +  * the element associated with the supplied parent clock address.
- +  * Returns a pointer to the struct clksel on success or NULL on error.
- +  */
- + static const struct clksel *_get_clksel_by_parent(struct clk *clk,
- + 						  struct clk *src_clk)
- + {
- + 	const struct clksel *clks;
- + 
- + 	for (clks = clk->clksel; clks->parent; clks++)
- + 		if (clks->parent == src_clk)
- + 			break; /* Found the requested parent */
- + 
- + 	if (!clks->parent) {
- + 		/* This indicates a data problem */
- + 		WARN(1, "clock: Could not find parent clock %s in clksel array "
- + 		     "of clock %s\n", src_clk->name, clk->name);
- + 		return NULL;
- + 	}
- + 
- + 	return clks;
- + }
- + 
- + /**
- +  * _get_div_and_fieldval() - find the new clksel divisor and field value to use
- +  * @src_clk: planned new parent struct clk *
- +  * @clk: struct clk * that is being reparented
- +  * @field_val: pointer to a u32 to contain the register data for the divisor
- +  *
- +  * Given an intended new parent struct clk * @src_clk, and the struct
- +  * clk * @clk to the clock that is being reparented, find the
- +  * appropriate rate divisor for the new clock (returned as the return
- +  * value), and the corresponding register bitfield data to program to
- +  * reach that divisor (returned in the u32 pointed to by @field_val).
- +  * Returns 0 on error, or returns the newly-selected divisor upon
- +  * success (in this latter case, the corresponding register bitfield
- +  * value is passed back in the variable pointed to by @field_val)
- +  */
- + static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
- + 				u32 *field_val)
- + {
- + 	const struct clksel *clks;
- + 	const struct clksel_rate *clkr, *max_clkr = NULL;
- + 	u8 max_div = 0;
- + 
- + 	clks = _get_clksel_by_parent(clk, src_clk);
- + 	if (!clks)
- + 		return 0;
- + 
- + 	/*
- + 	 * Find the highest divisor (e.g., the one resulting in the
- + 	 * lowest rate) to use as the default.  This should avoid
- + 	 * clock rates that are too high for the device.  XXX A better
- + 	 * solution here would be to try to determine if there is a
- + 	 * divisor matching the original clock rate before the parent
- + 	 * switch, and if it cannot be found, to fall back to the
- + 	 * highest divisor.
- + 	 */
- + 	for (clkr = clks->rates; clkr->div; clkr++) {
- + 		if (!(clkr->flags & cpu_mask))
- + 			continue;
- + 
- + 		if (clkr->div > max_div) {
- + 			max_div = clkr->div;
- + 			max_clkr = clkr;
- + 		}
- + 	}
- + 
- + 	if (max_div == 0) {
- + 		/* This indicates an error in the clksel data */
- + 		WARN(1, "clock: Could not find divisor for clock %s parent %s"
- + 		     "\n", clk->name, src_clk->parent->name);
- + 		return 0;
- + 	}
- + 
- + 	*field_val = max_clkr->val;
- + 
- + 	return max_div;
- + }
- + 
- + /**
- +  * _write_clksel_reg() - program a clock's clksel register in hardware
- +  * @clk: struct clk * to program
- +  * @v: clksel bitfield value to program (with LSB at bit 0)
- +  *
- +  * Shift the clksel register bitfield value @v to its appropriate
- +  * location in the clksel register and write it in.  This function
- +  * will ensure that the write to the clksel_reg reaches its
- +  * destination before returning -- important since PRM and CM register
- +  * accesses can be quite slow compared to ARM cycles -- but does not
- +  * take into account any time the hardware might take to switch the
- +  * clock source.
- +  */
- + static void _write_clksel_reg(struct clk *clk, u32 field_val)
- + {
- + 	u32 v;
- + 
- + 	v = __raw_readl(clk->clksel_reg);
- + 	v &= ~clk->clksel_mask;
- + 	v |= field_val << __ffs(clk->clksel_mask);
- + 	__raw_writel(v, clk->clksel_reg);
- + 
- + 	v = __raw_readl(clk->clksel_reg); /* OCP barrier */
- + }
- + 
- + /**
- +  * _clksel_to_divisor() - turn clksel field value into integer divider
- +  * @clk: OMAP struct clk to use
- +  * @field_val: register field value to find
- +  *
- +  * Given a struct clk of a rate-selectable clksel clock, and a register field
- +  * value to search for, find the corresponding clock divisor.  The register
- +  * field value should be pre-masked and shifted down so the LSB is at bit 0
- +  * before calling.  Returns 0 on error or returns the actual integer divisor
- +  * upon success.
- +  */
- + static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
- + {
- + 	const struct clksel *clks;
- + 	const struct clksel_rate *clkr;
- + 
- + 	clks = _get_clksel_by_parent(clk, clk->parent);
- + 	if (!clks)
- + 		return 0;
- + 
- + 	for (clkr = clks->rates; clkr->div; clkr++) {
- + 		if (!(clkr->flags & cpu_mask))
- + 			continue;
- + 
- + 		if (clkr->val == field_val)
- + 			break;
- + 	}
- + 
- + 	if (!clkr->div) {
- + 		/* This indicates a data error */
- + 		WARN(1, "clock: Could not find fieldval %d for clock %s parent "
- + 		     "%s\n", field_val, clk->name, clk->parent->name);
- + 		return 0;
- + 	}
- + 
- + 	return clkr->div;
- + }
- + 
- + /**
- +  * _divisor_to_clksel() - turn clksel integer divisor into a field value
- +  * @clk: OMAP struct clk to use
- +  * @div: integer divisor to search for
- +  *
- +  * Given a struct clk of a rate-selectable clksel clock, and a clock
- +  * divisor, find the corresponding register field value.  Returns the
- +  * register field value _before_ left-shifting (i.e., LSB is at bit
- +  * 0); or returns 0xFFFFFFFF (~0) upon error.
- +  */
- + static u32 _divisor_to_clksel(struct clk *clk, u32 div)
- + {
- + 	const struct clksel *clks;
- + 	const struct clksel_rate *clkr;
- + 
- + 	/* should never happen */
- + 	WARN_ON(div == 0);
- + 
- + 	clks = _get_clksel_by_parent(clk, clk->parent);
- + 	if (!clks)
- + 		return ~0;
- + 
- + 	for (clkr = clks->rates; clkr->div; clkr++) {
- + 		if (!(clkr->flags & cpu_mask))
- + 			continue;
- + 
- + 		if (clkr->div == div)
- + 			break;
- + 	}
- + 
- + 	if (!clkr->div) {
- + 		pr_err("clock: Could not find divisor %d for clock %s parent "
- + 		       "%s\n", div, clk->name, clk->parent->name);
- + 		return ~0;
- + 	}
- + 
- + 	return clkr->val;
- + }
- + 
- + /**
- +  * _read_divisor() - get current divisor applied to parent clock (from hdwr)
- +  * @clk: OMAP struct clk to use.
- +  *
- +  * Read the current divisor register value for @clk that is programmed
- +  * into the hardware, convert it into the actual divisor value, and
- +  * return it; or return 0 on error.
- +  */
- + static u32 _read_divisor(struct clk *clk)
- + {
- + 	u32 v;
- + 
- + 	if (!clk->clksel || !clk->clksel_mask)
- + 		return 0;
- + 
- + 	v = __raw_readl(clk->clksel_reg);
- + 	v &= clk->clksel_mask;
- + 	v >>= __ffs(clk->clksel_mask);
- + 
- + 	return _clksel_to_divisor(clk, v);
- + }
- + 
- + /* Public functions */
- + 
- + /**
- +  * omap2_clksel_round_rate_div() - find divisor for the given clock and rate
- +  * @clk: OMAP struct clk to use
- +  * @target_rate: desired clock rate
- +  * @new_div: ptr to where we should store the divisor
- +  *
- +  * Finds 'best' divider value in an array based on the source and target
- +  * rates.  The divider array must be sorted with smallest divider first.
- +  * This function is also used by the DPLL3 M2 divider code.
- +  *
- +  * Returns the rounded clock rate or returns 0xffffffff on error.
- +  */
- + u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
- + 				u32 *new_div)
- + {
- + 	unsigned long test_rate;
- + 	const struct clksel *clks;
- + 	const struct clksel_rate *clkr;
- + 	u32 last_div = 0;
- + 
- + 	if (!clk->clksel || !clk->clksel_mask)
- + 		return ~0;
- + 
- + 	pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
- + 		 clk->name, target_rate);
- + 
- + 	*new_div = 1;
- + 
- + 	clks = _get_clksel_by_parent(clk, clk->parent);
- + 	if (!clks)
- + 		return ~0;
- + 
- + 	for (clkr = clks->rates; clkr->div; clkr++) {
- + 		if (!(clkr->flags & cpu_mask))
- + 			continue;
- + 
- + 		/* Sanity check */
- + 		if (clkr->div <= last_div)
- + 			pr_err("clock: clksel_rate table not sorted "
- + 			       "for clock %s", clk->name);
- + 
- + 		last_div = clkr->div;
- + 
- + 		test_rate = clk->parent->rate / clkr->div;
- + 
- + 		if (test_rate <= target_rate)
- + 			break; /* found it */
- + 	}
- + 
- + 	if (!clkr->div) {
- + 		pr_err("clock: Could not find divisor for target "
- + 		       "rate %ld for clock %s parent %s\n", target_rate,
- + 		       clk->name, clk->parent->name);
- + 		return ~0;
- + 	}
- + 
- + 	*new_div = clkr->div;
- + 
- + 	pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div,
- + 		 (clk->parent->rate / clkr->div));
- + 
- + 	return clk->parent->rate / clkr->div;
- + }
- + 
- + /*
- +  * Clocktype interface functions to the OMAP clock code
- +  * (i.e., those used in struct clk field function pointers, etc.)
- +  */
- + 
- + /**
- +  * omap2_init_clksel_parent() - set a clksel clk's parent field from the hdwr
- +  * @clk: OMAP clock struct ptr to use
- +  *
- +  * Given a pointer @clk to a source-selectable struct clk, read the
- +  * hardware register and determine what its parent is currently set
- +  * to.  Update @clk's .parent field with the appropriate clk ptr.  No
- +  * return value.
- +  */
- + void omap2_init_clksel_parent(struct clk *clk)
- + {
- + 	const struct clksel *clks;
- + 	const struct clksel_rate *clkr;
- + 	u32 r, found = 0;
- + 
- + 	if (!clk->clksel || !clk->clksel_mask)
- + 		return;
- + 
- + 	r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
- + 	r >>= __ffs(clk->clksel_mask);
- + 
- + 	for (clks = clk->clksel; clks->parent && !found; clks++) {
- + 		for (clkr = clks->rates; clkr->div && !found; clkr++) {
- + 			if (!(clkr->flags & cpu_mask))
- + 				continue;
- + 
- + 			if (clkr->val == r) {
- + 				if (clk->parent != clks->parent) {
- + 					pr_debug("clock: inited %s parent "
- + 						 "to %s (was %s)\n",
- + 						 clk->name, clks->parent->name,
- + 						 ((clk->parent) ?
- + 						  clk->parent->name : "NULL"));
- + 					clk_reparent(clk, clks->parent);
- + 				};
- + 				found = 1;
- + 			}
- + 		}
- + 	}
- + 
- + 	/* This indicates a data error */
- + 	WARN(!found, "clock: %s: init parent: could not find regval %0x\n",
- + 	     clk->name, r);
- + 
- + 	return;
- + }
- + 
- + /**
- +  * omap2_clksel_recalc() - function ptr to pass via struct clk .recalc field
- +  * @clk: struct clk *
- +  *
- +  * This function is intended to be called only by the clock framework.
- +  * Each clksel clock should have its struct clk .recalc field set to this
- +  * function.  Returns the clock's current rate, based on its parent's rate
- +  * and its current divisor setting in the hardware.
- +  */
- + unsigned long omap2_clksel_recalc(struct clk *clk)
- + {
- + 	unsigned long rate;
- + 	u32 div = 0;
- + 
- + 	div = _read_divisor(clk);
- + 	if (div == 0)
- + 		return clk->rate;
- + 
- + 	rate = clk->parent->rate / div;
- + 
- + 	pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n", clk->name,
- + 		 rate, div);
- + 
- + 	return rate;
- + }
- + 
- + /**
- +  * omap2_clksel_round_rate() - find rounded rate for the given clock and rate
- +  * @clk: OMAP struct clk to use
- +  * @target_rate: desired clock rate
- +  *
- +  * This function is intended to be called only by the clock framework.
- +  * Finds best target rate based on the source clock and possible dividers.
- +  * rates. The divider array must be sorted with smallest divider first.
- +  *
- +  * Returns the rounded clock rate or returns 0xffffffff on error.
- +  */
- + long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
- + {
- + 	u32 new_div;
- + 
- + 	return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
- + }
- + 
- + /**
- +  * omap2_clksel_set_rate() - program clock rate in hardware
- +  * @clk: struct clk * to program rate
- +  * @rate: target rate to program
- +  *
- +  * This function is intended to be called only by the clock framework.
- +  * Program @clk's rate to @rate in the hardware.  The clock can be
- +  * either enabled or disabled when this happens, although if the clock
- +  * is enabled, some downstream devices may glitch or behave
- +  * unpredictably when the clock rate is changed - this depends on the
- +  * hardware. This function does not currently check the usecount of
- +  * the clock, so if multiple drivers are using the clock, and the rate
- +  * is changed, they will all be affected without any notification.
- +  * Returns -EINVAL upon error, or 0 upon success.
- +  */
- + int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
- + {
- + 	u32 field_val, validrate, new_div = 0;
- + 
- + 	if (!clk->clksel || !clk->clksel_mask)
- + 		return -EINVAL;
- + 
- + 	validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
- + 	if (validrate != rate)
- + 		return -EINVAL;
- + 
- + 	field_val = _divisor_to_clksel(clk, new_div);
- + 	if (field_val == ~0)
- + 		return -EINVAL;
- + 
- + 	_write_clksel_reg(clk, field_val);
- + 
- + 	clk->rate = clk->parent->rate / new_div;
- + 
- + 	pr_debug("clock: %s: set rate to %ld\n", clk->name, clk->rate);
- + 
- + 	return 0;
- + }
- + 
- + /*
- +  * Clksel parent setting function - not passed in struct clk function
- +  * pointer - instead, the OMAP clock code currently assumes that any
- +  * parent-setting clock is a clksel clock, and calls
- +  * omap2_clksel_set_parent() by default
- +  */
- + 
- + /**
- +  * omap2_clksel_set_parent() - change a clock's parent clock
- +  * @clk: struct clk * of the child clock
- +  * @new_parent: struct clk * of the new parent clock
- +  *
- +  * This function is intended to be called only by the clock framework.
- +  * Change the parent clock of clock @clk to @new_parent.  This is
- +  * intended to be used while @clk is disabled.  This function does not
- +  * currently check the usecount of the clock, so if multiple drivers
- +  * are using the clock, and the parent is changed, they will all be
- +  * affected without any notification.  Returns -EINVAL upon error, or
- +  * 0 upon success.
- +  */
- + int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent)
- + {
- + 	u32 field_val = 0;
- + 	u32 parent_div;
- + 
- + 	if (!clk->clksel || !clk->clksel_mask)
- + 		return -EINVAL;
- + 
- + 	parent_div = _get_div_and_fieldval(new_parent, clk, &field_val);
- + 	if (!parent_div)
- + 		return -EINVAL;
- + 
- + 	_write_clksel_reg(clk, field_val);
- + 
- + 	clk_reparent(clk, new_parent);
- + 
- + 	/* CLKSEL clocks follow their parents' rates, divided by a divisor */
- + 	clk->rate = new_parent->rate;
- + 
- + 	if (parent_div > 0)
- + 		clk->rate /= parent_div;
- + 
- + 	pr_debug("clock: %s: set parent to %s (new rate %ld)\n",
- + 		 clk->name, clk->parent->name, clk->rate);
- + 
- + 	return 0;
- + }
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/clkt_dpll.c linux-3.2.1/arch/arm/mach-ckb_3352/clkt_dpll.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/clkt_dpll.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/clkt_dpll.c	2014-05-15 13:25:13.859874528 +0900
- ***************
- *** 0 ****
- --- 1,328 ----
- + /*
- +  * OMAP2/3/4 DPLL clock functions
- +  *
- +  * Copyright (C) 2005-2008 Texas Instruments, Inc.
- +  * Copyright (C) 2004-2010 Nokia Corporation
- +  *
- +  * Contacts:
- +  * Richard Woodruff <r-woodruff2@ti.com>
- +  * Paul Walmsley
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + #undef DEBUG
- + 
- + #include <linux/kernel.h>
- + #include <linux/errno.h>
- + #include <linux/clk.h>
- + #include <linux/io.h>
- + 
- + #include <asm/div64.h>
- + 
- + #include <plat/clock.h>
- + 
- + #include "clock.h"
- + #include "cm-regbits-34xx.h"
- + 
- + /* DPLL rate rounding: minimum DPLL multiplier, divider values */
- + #define DPLL_MIN_MULTIPLIER		2
- + #define DPLL_MIN_DIVIDER		1
- + 
- + /* Possible error results from _dpll_test_mult */
- + #define DPLL_MULT_UNDERFLOW		-1
- + 
- + /*
- +  * Scale factor to mitigate roundoff errors in DPLL rate rounding.
- +  * The higher the scale factor, the greater the risk of arithmetic overflow,
- +  * but the closer the rounded rate to the target rate.  DPLL_SCALE_FACTOR
- +  * must be a power of DPLL_SCALE_BASE.
- +  */
- + #define DPLL_SCALE_FACTOR		64
- + #define DPLL_SCALE_BASE			2
- + #define DPLL_ROUNDING_VAL		((DPLL_SCALE_BASE / 2) * \
- + 					 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
- + 
- + /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
- + #define OMAP3430_DPLL_FINT_BAND1_MIN	750000
- + #define OMAP3430_DPLL_FINT_BAND1_MAX	2100000
- + #define OMAP3430_DPLL_FINT_BAND2_MIN	7500000
- + #define OMAP3430_DPLL_FINT_BAND2_MAX	21000000
- + 
- + /*
- +  * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
- +  * From device data manual section 4.3 "DPLL and DLL Specifications".
- +  */
- + #define OMAP3PLUS_DPLL_FINT_JTYPE_MIN	500000
- + #define OMAP3PLUS_DPLL_FINT_JTYPE_MAX	2500000
- + #define OMAP3PLUS_DPLL_FINT_MIN		32000
- + #define OMAP3PLUS_DPLL_FINT_MAX		52000000
- + 
- + /* _dpll_test_fint() return codes */
- + #define DPLL_FINT_UNDERFLOW		-1
- + #define DPLL_FINT_INVALID		-2
- + 
- + /* Private functions */
- + 
- + /*
- +  * _dpll_test_fint - test whether an Fint value is valid for the DPLL
- +  * @clk: DPLL struct clk to test
- +  * @n: divider value (N) to test
- +  *
- +  * Tests whether a particular divider @n will result in a valid DPLL
- +  * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
- +  * Correction".  Returns 0 if OK, -1 if the enclosing loop can terminate
- +  * (assuming that it is counting N upwards), or -2 if the enclosing loop
- +  * should skip to the next iteration (again assuming N is increasing).
- +  */
- + static int _dpll_test_fint(struct clk *clk, u8 n)
- + {
- + 	struct dpll_data *dd;
- + 	long fint, fint_min, fint_max;
- + 	int ret = 0;
- + 
- + 	dd = clk->dpll_data;
- + 
- + 	/* DPLL divider must result in a valid jitter correction val */
- + 	fint = clk->parent->rate / n;
- + 
- + 	if (dd->flags & DPLL_J_TYPE) {
- + 		fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN;
- + 		fint_max = OMAP3PLUS_DPLL_FINT_JTYPE_MAX;
- + 	} else {
- + 		fint_min = OMAP3PLUS_DPLL_FINT_MIN;
- + 		fint_max = OMAP3PLUS_DPLL_FINT_MAX;
- + 	}
- + 
- + 	if (fint < fint_min) {
- + 		pr_debug("rejecting n=%d due to Fint failure, "
- + 			 "lowering max_divider\n", n);
- + 		dd->max_divider = n;
- + 		ret = DPLL_FINT_UNDERFLOW;
- + 	} else if (fint > fint_max) {
- + 		pr_debug("rejecting n=%d due to Fint failure, "
- + 			 "boosting min_divider\n", n);
- + 		dd->min_divider = n;
- + 		ret = DPLL_FINT_INVALID;
- + 	}
- + 
- + 	return ret;
- + }
- + 
- + static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
- + 					    unsigned int m, unsigned int n)
- + {
- + 	unsigned long long num;
- + 
- + 	num = (unsigned long long)parent_rate * m;
- + 	do_div(num, n);
- + 	return num;
- + }
- + 
- + /*
- +  * _dpll_test_mult - test a DPLL multiplier value
- +  * @m: pointer to the DPLL m (multiplier) value under test
- +  * @n: current DPLL n (divider) value under test
- +  * @new_rate: pointer to storage for the resulting rounded rate
- +  * @target_rate: the desired DPLL rate
- +  * @parent_rate: the DPLL's parent clock rate
- +  *
- +  * This code tests a DPLL multiplier value, ensuring that the
- +  * resulting rate will not be higher than the target_rate, and that
- +  * the multiplier value itself is valid for the DPLL.  Initially, the
- +  * integer pointed to by the m argument should be prescaled by
- +  * multiplying by DPLL_SCALE_FACTOR.  The code will replace this with
- +  * a non-scaled m upon return.  This non-scaled m will result in a
- +  * new_rate as close as possible to target_rate (but not greater than
- +  * target_rate) given the current (parent_rate, n, prescaled m)
- +  * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
- +  * non-scaled m attempted to underflow, which can allow the calling
- +  * function to bail out early; or 0 upon success.
- +  */
- + static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
- + 			   unsigned long target_rate,
- + 			   unsigned long parent_rate)
- + {
- + 	int r = 0, carry = 0;
- + 
- + 	/* Unscale m and round if necessary */
- + 	if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
- + 		carry = 1;
- + 	*m = (*m / DPLL_SCALE_FACTOR) + carry;
- + 
- + 	/*
- + 	 * The new rate must be <= the target rate to avoid programming
- + 	 * a rate that is impossible for the hardware to handle
- + 	 */
- + 	*new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
- + 	if (*new_rate > target_rate) {
- + 		(*m)--;
- + 		*new_rate = 0;
- + 	}
- + 
- + 	/* Guard against m underflow */
- + 	if (*m < DPLL_MIN_MULTIPLIER) {
- + 		*m = DPLL_MIN_MULTIPLIER;
- + 		*new_rate = 0;
- + 		r = DPLL_MULT_UNDERFLOW;
- + 	}
- + 
- + 	if (*new_rate == 0)
- + 		*new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
- + 
- + 	return r;
- + }
- + 
- + /* Public functions */
- + 
- + void omap2_init_dpll_parent(struct clk *clk)
- + {
- + 	u32 v;
- + 	struct dpll_data *dd;
- + 
- + 	dd = clk->dpll_data;
- + 	if (!dd)
- + 		return;
- + 
- + 	v = __raw_readl(dd->control_reg);
- + 	v &= dd->enable_mask;
- + 	v >>= __ffs(dd->enable_mask);
- + 
- + 	/* Reparent the struct clk in case the dpll is in bypass */
- + 	if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
- + 	    v == OMAP3XXX_EN_DPLL_FRBYPASS ||
- + 	    v == OMAP4XXX_EN_DPLL_MNBYPASS)
- + 		clk_reparent(clk, dd->clk_bypass);
- + 	
- + 	return;
- + }
- + 
- + /**
- +  * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
- +  * @clk: struct clk * of a DPLL
- +  *
- +  * DPLLs can be locked or bypassed - basically, enabled or disabled.
- +  * When locked, the DPLL output depends on the M and N values.  When
- +  * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock
- +  * or sys_clk.  Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
- +  * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively
- +  * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
- +  * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is
- +  * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
- +  * if the clock @clk is not a DPLL.
- +  */
- + u32 omap2_get_dpll_rate(struct clk *clk)
- + {
- + 	long long dpll_clk;
- + 	u32 dpll_mult, dpll_div, v;
- + 	struct dpll_data *dd;
- + 
- + 	dd = clk->dpll_data;
- + 	if (!dd)
- + 		return 0;
- + 
- + 	/* Return bypass rate if DPLL is bypassed */
- + 	v = __raw_readl(dd->control_reg);
- + 	v &= dd->enable_mask;
- + 	v >>= __ffs(dd->enable_mask);
- + 
- + 	if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
- + 	    v == OMAP3XXX_EN_DPLL_FRBYPASS ||
- + 	    v == OMAP4XXX_EN_DPLL_MNBYPASS)
- + 		return dd->clk_bypass->rate;
- + 	
- + 	v = __raw_readl(dd->mult_div1_reg);
- + 	dpll_mult = v & dd->mult_mask;
- + 	dpll_mult >>= __ffs(dd->mult_mask);
- + 	dpll_div = v & dd->div1_mask;
- + 	dpll_div >>= __ffs(dd->div1_mask);
- + 
- + 	dpll_clk = (long long)dd->clk_ref->rate * dpll_mult;
- + 	do_div(dpll_clk, dpll_div + 1);
- + 
- + 	return dpll_clk;
- + }
- + 
- + /* DPLL rate rounding code */
- + 
- + /**
- +  * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
- +  * @clk: struct clk * for a DPLL
- +  * @target_rate: desired DPLL clock rate
- +  *
- +  * Given a DPLL and a desired target rate, round the target rate to a
- +  * possible, programmable rate for this DPLL.  Attempts to select the
- +  * minimum possible n.  Stores the computed (m, n) in the DPLL's
- +  * dpll_data structure so set_rate() will not need to call this
- +  * (expensive) function again.  Returns ~0 if the target rate cannot
- +  * be rounded, or the rounded rate upon success.
- +  */
- + long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
- + {
- + 	int m, n, r, scaled_max_m;
- + 	unsigned long scaled_rt_rp;
- + 	unsigned long new_rate = 0;
- + 	struct dpll_data *dd;
- + 
- + 	if (!clk || !clk->dpll_data)
- + 		return ~0;
- + 
- + 	dd = clk->dpll_data;
- + 
- + 	pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n",
- + 		 clk->name, target_rate);
- + 
- + 	scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR);
- + 	scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
- + 
- + 	dd->last_rounded_rate = 0;
- + 
- + 	for (n = dd->min_divider; n <= dd->max_divider; n++) {
- + 
- + 		/* Is the (input clk, divider) pair valid for the DPLL? */
- + 		r = _dpll_test_fint(clk, n);
- + 		if (r == DPLL_FINT_UNDERFLOW)
- + 			break;
- + 		else if (r == DPLL_FINT_INVALID)
- + 			continue;
- + 
- + 		/* Compute the scaled DPLL multiplier, based on the divider */
- + 		m = scaled_rt_rp * n;
- + 
- + 		/*
- + 		 * Since we're counting n up, a m overflow means we
- + 		 * can bail out completely (since as n increases in
- + 		 * the next iteration, there's no way that m can
- + 		 * increase beyond the current m)
- + 		 */
- + 		if (m > scaled_max_m)
- + 			break;
- + 
- + 		r = _dpll_test_mult(&m, n, &new_rate, target_rate,
- + 				    dd->clk_ref->rate);
- + 
- + 		/* m can't be set low enough for this n - try with a larger n */
- + 		if (r == DPLL_MULT_UNDERFLOW)
- + 			continue;
- + 
- + 		pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n",
- + 			 clk->name, m, n, new_rate);
- + 
- + 		if (target_rate == new_rate) {
- + 			dd->last_rounded_m = m;
- + 			dd->last_rounded_n = n;
- + 			dd->last_rounded_rate = target_rate;
- + 			break;
- + 		}
- + 	}
- + 
- + 	if (target_rate != new_rate) {
- + 		pr_debug("clock: %s: cannot round to rate %ld\n", clk->name,
- + 			 target_rate);
- + 		return ~0;
- + 	}
- + 
- + 	return target_rate;
- + }
- + 
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/clock33xx_data.c linux-3.2.1/arch/arm/mach-ckb_3352/clock33xx_data.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/clock33xx_data.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/clock33xx_data.c	2014-05-15 13:25:13.867221735 +0900
- ***************
- *** 0 ****
- --- 1,2254 ----
- + /*
- +  * AM33XX Clock data
- +  *
- +  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #include <linux/kernel.h>
- + #include <linux/list.h>
- + #include <linux/clk.h>
- + #include <plat/clkdev_omap.h>
- + 
- + #include "control.h"
- + #include "clock.h"
- + #include "clock33xx.h"
- + #include "cm.h"
- + #include "cm33xx.h"
- + #include "cm-regbits-33xx.h"
- + #include "prm.h"
- + 
- + /* Modulemode control */
- + #define AM33XX_MODULEMODE_HWCTRL	0
- + #define AM33XX_MODULEMODE_SWCTRL	1
- + 
- + /* Root clocks */
- + static struct clk clk_32768_ck = {
- + 	.name		= "clk_32768_ck",
- + 	.rate		= 32768,
- + 	.ops		= &clkops_null,
- + };
- + 
- + /* On-Chip 32KHz RC OSC */
- + static struct clk clk_rc32k_ck = {
- + 	.name		= "clk_rc32k_ck",
- + 	.rate		= 32000,
- + 	.ops		= &clkops_null,
- + };
- + 
- + /* Crystal input clks */
- + static struct clk virt_19_2m_ck = {
- + 	.name		= "virt_19_2m_ck",
- + 	.rate		= 19200000,
- + 	.ops		= &clkops_null,
- + };
- + 
- + static struct clk virt_24m_ck = {
- + 	.name		= "virt_24m_ck",
- + 	.rate		= 24000000,
- + 	.ops		= &clkops_null,
- + };
- + 
- + static struct clk virt_25m_ck = {
- + 	.name		= "virt_25m_ck",
- + 	.rate		= 25000000,
- + 	.ops		= &clkops_null,
- + };
- + 
- + static struct clk virt_26m_ck = {
- + 	.name		= "virt_26m_ck",
- + 	.rate		= 26000000,
- + 	.ops		= &clkops_null,
- + };
- + 
- + static struct clk tclkin_ck = {
- + 	.name		= "tclkin_ck",
- + 	.rate		= 12000000,
- + 	.ops		= &clkops_null,
- + };
- + 
- + static const struct clksel_rate div_1_0_rates[] = {
- + 	{ .div = 1, .val = 0, .flags = RATE_IN_AM33XX },
- + 	{ .div = 0 },
- + };
- + 
- + static const struct clksel_rate div_1_1_rates[] = {
- + 	{ .div = 1, .val = 1, .flags = RATE_IN_AM33XX },
- + 	{ .div = 0 },
- + };
- + 
- + static const struct clksel_rate div_1_2_rates[] = {
- + 	{ .div = 1, .val = 2, .flags = RATE_IN_AM33XX },
- + 	{ .div = 0 },
- + };
- + 
- + static const struct clksel_rate div_1_3_rates[] = {
- + 	{ .div = 1, .val = 3, .flags = RATE_IN_AM33XX },
- + 	{ .div = 0 },
- + };
- + 
- + static const struct clksel_rate div_1_4_rates[] = {
- + 	{ .div = 1, .val = 4, .flags = RATE_IN_AM33XX },
- + 	{ .div = 0 },
- + };
- + 
- + static const struct clksel_rate div31_1to31_rates[] = {
- + 	{ .div = 1, .val = 1, .flags = RATE_IN_AM33XX },
- + 	{ .div = 2, .val = 2, .flags = RATE_IN_AM33XX },
- + 	{ .div = 3, .val = 3, .flags = RATE_IN_AM33XX },
- + 	{ .div = 4, .val = 4, .flags = RATE_IN_AM33XX },
- + 	{ .div = 5, .val = 5, .flags = RATE_IN_AM33XX },
- + 	{ .div = 6, .val = 6, .flags = RATE_IN_AM33XX },
- + 	{ .div = 7, .val = 7, .flags = RATE_IN_AM33XX },
- + 	{ .div = 8, .val = 8, .flags = RATE_IN_AM33XX },
- + 	{ .div = 9, .val = 9, .flags = RATE_IN_AM33XX },
- + 	{ .div = 10, .val = 10, .flags = RATE_IN_AM33XX },
- + 	{ .div = 11, .val = 11, .flags = RATE_IN_AM33XX },
- + 	{ .div = 12, .val = 12, .flags = RATE_IN_AM33XX },
- + 	{ .div = 13, .val = 13, .flags = RATE_IN_AM33XX },
- + 	{ .div = 14, .val = 14, .flags = RATE_IN_AM33XX },
- + 	{ .div = 15, .val = 15, .flags = RATE_IN_AM33XX },
- + 	{ .div = 16, .val = 16, .flags = RATE_IN_AM33XX },
- + 	{ .div = 17, .val = 17, .flags = RATE_IN_AM33XX },
- + 	{ .div = 18, .val = 18, .flags = RATE_IN_AM33XX },
- + 	{ .div = 19, .val = 19, .flags = RATE_IN_AM33XX },
- + 	{ .div = 20, .val = 20, .flags = RATE_IN_AM33XX },
- + 	{ .div = 21, .val = 21, .flags = RATE_IN_AM33XX },
- + 	{ .div = 22, .val = 22, .flags = RATE_IN_AM33XX },
- + 	{ .div = 23, .val = 23, .flags = RATE_IN_AM33XX },
- + 	{ .div = 24, .val = 24, .flags = RATE_IN_AM33XX },
- + 	{ .div = 25, .val = 25, .flags = RATE_IN_AM33XX },
- + 	{ .div = 26, .val = 26, .flags = RATE_IN_AM33XX },
- + 	{ .div = 27, .val = 27, .flags = RATE_IN_AM33XX },
- + 	{ .div = 28, .val = 28, .flags = RATE_IN_AM33XX },
- + 	{ .div = 29, .val = 29, .flags = RATE_IN_AM33XX },
- + 	{ .div = 30, .val = 30, .flags = RATE_IN_AM33XX },
- + 	{ .div = 31, .val = 31, .flags = RATE_IN_AM33XX },
- + 	{ .div = 0 },
- + };
- + 
- + /* Oscillator clock */
- + /* 19.2, 24, 25 or 26 MHz */
- + static const struct clksel sys_clkin_sel[] = {
- + 	{ .parent = &virt_19_2m_ck, .rates = div_1_0_rates },
- + 	{ .parent = &virt_24m_ck, .rates = div_1_1_rates },
- + 	{ .parent = &virt_25m_ck, .rates = div_1_2_rates },
- + 	{ .parent = &virt_26m_ck, .rates = div_1_3_rates },
- + 	{ .parent = NULL },
- + };
- + 
- + /* sys_clk_in */
- + static struct clk sys_clkin_ck = {
- + 	.name		= "sys_clkin_ck",
- + 	.parent		= &virt_24m_ck,
- + 	.init		= &omap2_init_clksel_parent,
- + 	.clksel_reg	= AM33XX_CTRL_REGADDR(0x40),	/* CONTROL_STATUS */
- + 	.clksel_mask	= (0x3 << 22),
- + 	.clksel		= sys_clkin_sel,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &omap2_clksel_recalc,
- + };
- + 
- + /* DPLL_CORE */
- + static struct dpll_data dpll_core_dd = {
- + 	.mult_div1_reg	= AM33XX_CM_CLKSEL_DPLL_CORE,
- + 	.clk_bypass	= &sys_clkin_ck,
- + 	.clk_ref	= &sys_clkin_ck,
- + 	.control_reg	= AM33XX_CM_CLKMODE_DPLL_CORE,
- + 	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- + 	.idlest_reg	= AM33XX_CM_IDLEST_DPLL_CORE,
- + 	.mult_mask	= AM33XX_DPLL_MULT_MASK,
- + 	.div1_mask	= AM33XX_DPLL_DIV_MASK,
- + 	.enable_mask	= AM33XX_DPLL_EN_MASK,
- + 	.idlest_mask	= AM33XX_ST_DPLL_CLK_MASK,
- + 	.max_multiplier	= AM33XX_MAX_DPLL_MULT,
- + 	.max_divider	= AM33XX_MAX_DPLL_DIV,
- + 	.min_divider	= 1,
- + };
- + 
- + /* CLKDCOLDO output */
- + static struct clk dpll_core_ck = {
- + 	.name		= "dpll_core_ck",
- + 	.parent		= &sys_clkin_ck,
- + 	.dpll_data	= &dpll_core_dd,
- + 	.init		= &omap2_init_dpll_parent,
- + 	.ops		= &clkops_omap3_core_dpll_ops,
- + 	.recalc		= &omap3_dpll_recalc,
- + };
- + 
- + static struct clk dpll_core_x2_ck = {
- + 	.name		= "dpll_core_x2_ck",
- + 	.parent		= &dpll_core_ck,
- + 	.flags		= CLOCK_CLKOUTX2,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &omap3_clkoutx2_recalc,
- + };
- + 
- + 
- + static const struct clksel dpll_core_m4_div[] = {
- + 	{ .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
- + 	{ .parent = NULL },
- + };
- + 
- + static struct clk dpll_core_m4_ck = {
- + 	.name		= "dpll_core_m4_ck",
- + 	.parent		= &dpll_core_x2_ck,
- + 	.clksel		= dpll_core_m4_div,
- + 	.clksel_reg	= AM33XX_CM_DIV_M4_DPLL_CORE,
- + 	.clksel_mask	= AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &omap2_clksel_recalc,
- + 	.round_rate	= &omap2_clksel_round_rate,
- + 	.set_rate	= &omap2_clksel_set_rate,
- + };
- + 
- + static const struct clksel dpll_core_m5_div[] = {
- + 	{ .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
- + 	{ .parent = NULL },
- + };
- + 
- + static struct clk dpll_core_m5_ck = {
- + 	.name		= "dpll_core_m5_ck",
- + 	.parent		= &dpll_core_x2_ck,
- + 	.clksel		= dpll_core_m5_div,
- + 	.clksel_reg	= AM33XX_CM_DIV_M5_DPLL_CORE,
- + 	.clksel_mask	= AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &omap2_clksel_recalc,
- + 	.round_rate	= &omap2_clksel_round_rate,
- + 	.set_rate	= &omap2_clksel_set_rate,
- + };
- + 
- + static const struct clksel dpll_core_m6_div[] = {
- + 	{ .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
- + 	{ .parent = NULL },
- + };
- + 
- + static struct clk dpll_core_m6_ck = {
- + 	.name		= "dpll_core_m6_ck",
- + 	.parent		= &dpll_core_x2_ck,
- + 	.clksel		= dpll_core_m6_div,
- + 	.clksel_reg	= AM33XX_CM_DIV_M6_DPLL_CORE,
- + 	.clksel_mask	= AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &omap2_clksel_recalc,
- + 	.round_rate	= &omap2_clksel_round_rate,
- + 	.set_rate	= &omap2_clksel_set_rate,
- + };
- + 
- + static struct clk sysclk1_ck = {
- + 	.name		= "sysclk1_ck",
- + 	.parent		= &dpll_core_m4_ck,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk sysclk2_ck = {
- + 	.name		= "sysclk2_ck",
- + 	.parent		= &dpll_core_m5_ck,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk core_clk_out = {
- + 	.name		= "core_clk_out",
- + 	.parent		= &dpll_core_m4_ck,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + /* DPLL_MPU */
- + static struct dpll_data dpll_mpu_dd = {
- + 	.mult_div1_reg	= AM33XX_CM_CLKSEL_DPLL_MPU,
- + 	.clk_bypass	= &sys_clkin_ck,
- + 	.clk_ref	= &sys_clkin_ck,
- + 	.control_reg	= AM33XX_CM_CLKMODE_DPLL_MPU,
- + 	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- + 	.idlest_reg	= AM33XX_CM_IDLEST_DPLL_MPU,
- + 	.mult_mask	= AM33XX_DPLL_MULT_MASK,
- + 	.div1_mask	= AM33XX_DPLL_DIV_MASK,
- + 	.enable_mask	= AM33XX_DPLL_EN_MASK,
- + 	.idlest_mask	= AM33XX_ST_DPLL_CLK_MASK,
- + 	.max_multiplier	= AM33XX_MAX_DPLL_MULT,
- + 	.max_divider	= AM33XX_MAX_DPLL_DIV,
- + 	.min_divider	= 1,
- + };
- + 
- + /* CLKOUT: fdpll/M2 */
- + static struct clk dpll_mpu_ck = {
- + 	.name		= "dpll_mpu_ck",
- + 	.parent		= &sys_clkin_ck,
- + 	.dpll_data	= &dpll_mpu_dd,
- + 	.init		= &omap2_init_dpll_parent,
- + 	.ops		= &clkops_omap3_noncore_dpll_ops,
- + 	.recalc		= &omap3_dpll_recalc,
- + 	.round_rate	= &omap2_dpll_round_rate,
- + 	.set_rate	= &omap3_noncore_dpll_set_rate,
- + };
- + 
- + /*
- +  * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
- +  * and ALT_CLK1/2)
- +  */
- + static const struct clksel dpll_mpu_m2_div[] = {
- + 	{ .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
- + 	{ .parent = NULL },
- + };
- + 
- + static struct clk dpll_mpu_m2_ck = {
- + 	.name		= "dpll_mpu_m2_ck",
- + 	.parent		= &dpll_mpu_ck,
- + 	.clksel		= dpll_mpu_m2_div,
- + 	.clksel_reg	= AM33XX_CM_DIV_M2_DPLL_MPU,
- + 	.clksel_mask	= AM33XX_DPLL_CLKOUT_DIV_MASK,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &omap2_clksel_recalc,
- + 	.round_rate	= &omap2_clksel_round_rate,
- + 	.set_rate	= &omap2_clksel_set_rate,
- + };
- + 
- + static struct clk mpu_fck = {
- + 	.name		= "mpu_fck",
- + 	.clkdm_name	= "mpu_clkdm",
- + 	.parent		= &dpll_mpu_m2_ck,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.enable_reg	= AM33XX_CM_MPU_MPU_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.recalc		= &followparent_recalc,
- + 	.flags		= ENABLE_ON_INIT,
- + };
- + 
- + /* DPLL_DDR */
- + static struct dpll_data dpll_ddr_dd = {
- + 	.mult_div1_reg	= AM33XX_CM_CLKSEL_DPLL_DDR,
- + 	.clk_bypass	= &sys_clkin_ck,
- + 	.clk_ref	= &sys_clkin_ck,
- + 	.control_reg	= AM33XX_CM_CLKMODE_DPLL_DDR,
- + 	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- + 	.idlest_reg	= AM33XX_CM_IDLEST_DPLL_DDR,
- + 	.mult_mask	= AM33XX_DPLL_MULT_MASK,
- + 	.div1_mask	= AM33XX_DPLL_DIV_MASK,
- + 	.enable_mask	= AM33XX_DPLL_EN_MASK,
- + 	.idlest_mask	= AM33XX_ST_DPLL_CLK_MASK,
- + 	.max_multiplier	= AM33XX_MAX_DPLL_MULT,
- + 	.max_divider	= AM33XX_MAX_DPLL_DIV,
- + 	.min_divider	= 1,
- + };
- + 
- + /* CLKOUT: fdpll/M2 */
- + static struct clk dpll_ddr_ck = {
- + 	.name		= "dpll_ddr_ck",
- + 	.parent		= &sys_clkin_ck,
- + 	.dpll_data	= &dpll_ddr_dd,
- + 	.init		= &omap2_init_dpll_parent,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &omap3_dpll_recalc,
- + };
- + 
- + /*
- +  * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
- +  * and ALT_CLK1/2)
- +  */
- + static const struct clksel dpll_ddr_m2_div[] = {
- + 	{ .parent = &dpll_ddr_ck, .rates = div31_1to31_rates },
- + 	{ .parent = NULL },
- + };
- + 
- + static struct clk dpll_ddr_m2_ck = {
- + 	.name		= "dpll_ddr_m2_ck",
- + 	.parent		= &dpll_ddr_ck,
- + 	.clksel		= dpll_ddr_m2_div,
- + 	.clksel_reg	= AM33XX_CM_DIV_M2_DPLL_DDR,
- + 	.clksel_mask	= AM33XX_DPLL_CLKOUT_DIV_MASK,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &omap2_clksel_recalc,
- + 	.round_rate	= &omap2_clksel_round_rate,
- + 	.set_rate	= &omap2_clksel_set_rate,
- + };
- + 
- + static struct clk ddr_pll_clk = {
- + 	.name		= "ddr_pll_clk",
- + 	.parent		= &dpll_ddr_m2_ck,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk emif_fck = {
- + 	.name		= "emif_fck",
- + 	.clkdm_name	= "l3_clkdm",
- + 	.parent		= &ddr_pll_clk,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.enable_reg	= AM33XX_CM_PER_EMIF_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.fixed_div	= 2,
- + 	.recalc		= &omap_fixed_divisor_recalc,
- + 	.flags		= ENABLE_ON_INIT,
- + };
- + 
- + /* DPLL_DISP */
- + static struct dpll_data dpll_disp_dd = {
- + 	.mult_div1_reg	= AM33XX_CM_CLKSEL_DPLL_DISP,
- + 	.clk_bypass	= &sys_clkin_ck,
- + 	.clk_ref	= &sys_clkin_ck,
- + 	.control_reg	= AM33XX_CM_CLKMODE_DPLL_DISP,
- + 	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- + 	.idlest_reg	= AM33XX_CM_IDLEST_DPLL_DISP,
- + 	.mult_mask	= AM33XX_DPLL_MULT_MASK,
- + 	.div1_mask	= AM33XX_DPLL_DIV_MASK,
- + 	.enable_mask	= AM33XX_DPLL_EN_MASK,
- + 	.idlest_mask	= AM33XX_ST_DPLL_CLK_MASK,
- + 	.max_multiplier	= AM33XX_MAX_DPLL_MULT,
- + 	.max_divider	= AM33XX_MAX_DPLL_DIV,
- + 	.min_divider	= 1,
- + };
- + 
- + /* CLKOUT: fdpll/M2 */
- + static struct clk dpll_disp_ck = {
- + 	.name		= "dpll_disp_ck",
- + 	.parent		= &sys_clkin_ck,
- + 	.dpll_data	= &dpll_disp_dd,
- + 	.init		= &omap2_init_dpll_parent,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &omap3_dpll_recalc,
- + 	.round_rate	= &omap2_dpll_round_rate,
- + 	.set_rate	= &omap3_noncore_dpll_set_rate,
- + };
- + 
- + /*
- +  * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
- +  * and ALT_CLK1/2)
- +  */
- + static const struct clksel dpll_disp_m2_div[] = {
- + 	{ .parent = &dpll_disp_ck, .rates = div31_1to31_rates },
- + 	{ .parent = NULL },
- + };
- + 
- + static struct clk dpll_disp_m2_ck = {
- + 	.name		= "dpll_disp_m2_ck",
- + 	.parent		= &dpll_disp_ck,
- + 	.clksel		= dpll_disp_m2_div,
- + 	.clksel_reg	= AM33XX_CM_DIV_M2_DPLL_DISP,
- + 	.clksel_mask	= AM33XX_DPLL_CLKOUT_DIV_MASK,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &omap2_clksel_recalc,
- + 	.round_rate	= &omap2_clksel_round_rate,
- + 	.set_rate	= &omap2_clksel_set_rate,
- + };
- + 
- + static struct clk disp_pll_clk = {
- + 	.name		= "disp_pll_clk",
- + 	.parent		= &dpll_disp_m2_ck,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + /* DPLL_PER */
- + static struct dpll_data dpll_per_dd = {
- + 	.mult_div1_reg	= AM33XX_CM_CLKSEL_DPLL_PERIPH,
- + 	.clk_bypass	= &sys_clkin_ck,
- + 	.clk_ref	= &sys_clkin_ck,
- + 	.control_reg	= AM33XX_CM_CLKMODE_DPLL_PER,
- + 	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- + 	.idlest_reg	= AM33XX_CM_IDLEST_DPLL_PER,
- + 	.mult_mask	= AM33XX_DPLL_MULT_PERIPH_MASK,
- + 	.div1_mask	= AM33XX_DPLL_PER_DIV_MASK,
- + 	.enable_mask	= AM33XX_DPLL_EN_MASK,
- + 	.idlest_mask	= AM33XX_ST_DPLL_CLK_MASK,
- + 	.max_multiplier	= AM33XX_MAX_DPLL_MULT,
- + 	.max_divider	= AM33XX_MAX_DPLL_DIV,
- + 	.min_divider	= 1,
- + 	.flags		= DPLL_J_TYPE,
- + };
- + 
- + /* CLKDCOLDO */
- + static struct clk dpll_per_ck = {
- + 	.name		= "dpll_per_ck",
- + 	.parent		= &sys_clkin_ck,
- + 	.dpll_data	= &dpll_per_dd,
- + 	.init		= &omap2_init_dpll_parent,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &omap3_dpll_recalc,
- + 	.round_rate	= &omap2_dpll_round_rate,
- + 	.set_rate	= &omap3_noncore_dpll_set_rate,
- + };
- + 
- + /* CLKOUT: fdpll/M2 */
- + static const struct clksel dpll_per_m2_div[] = {
- + 	{ .parent = &dpll_per_ck, .rates = div31_1to31_rates },
- + 	{ .parent = NULL },
- + };
- + 
- + static struct clk dpll_per_m2_ck = {
- + 	.name		= "dpll_per_m2_ck",
- + 	.parent		= &dpll_per_ck,
- + 	.clksel		= dpll_per_m2_div,
- + 	.clksel_reg	= AM33XX_CM_DIV_M2_DPLL_PER,
- + 	.clksel_mask	= AM33XX_DPLL_CLKOUT_DIV_MASK,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &omap2_clksel_recalc,
- + 	.round_rate	= &omap2_clksel_round_rate,
- + 	.set_rate	= &omap2_clksel_set_rate,
- + };
- + 
- + static struct clk per_192mhz_clk = {
- + 	.name		= "per_192mhz_clk",
- + 	.parent		= &dpll_per_m2_ck,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk usb_pll_clk = {
- + 	.name		= "usb_pll_clk",
- + 	.parent		= &dpll_per_ck,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk core_100mhz_ck = {
- + 	.name		= "core_100mhz_ck",
- + 	.parent		= &sysclk1_ck,
- + 	.ops		= &clkops_null,
- + 	.fixed_div	= 2,
- + 	.recalc		= &omap_fixed_divisor_recalc,
- + };
- + 
- + static struct clk l3_aon_gclk = {
- + 	.name		= "l3_aon_gclk",
- + 	.parent		= &sysclk1_ck,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk l4_wkup_aon_gclk = {
- + 	.name		= "l4_wkup_aon_gclk",
- + 	.clkdm_name	= "l4_wkup_aon_clkdm",
- + 	.parent		= &sysclk1_ck,
- + 	.enable_reg	= AM33XX_CM_L4_WKUP_AON_CLKSTCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_null,
- + 	.fixed_div	= 2,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk l3_gclk = {
- + 	.name		= "l3_gclk",
- + 	.parent		= &sysclk1_ck,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk l3_ick = {
- + 	.name		= "l3_ick",
- + 	.clkdm_name	= "l3_clkdm",
- + 	.parent		= &l3_gclk,
- + 	.enable_reg	= AM33XX_CM_PER_L3_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.flags		= ENABLE_ON_INIT,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk l3_instr_ick = {
- + 	.name		= "l3_instr_ick",
- + 	.clkdm_name	= "l3_clkdm",
- + 	.parent		= &l3_gclk,
- + 	.enable_reg	= AM33XX_CM_PER_L3_INSTR_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.flags		= ENABLE_ON_INIT,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk l4_wkup_gclk = {
- + 	.name		= "l4_wkup_gclk",
- + 	.parent		= &sysclk1_ck,
- + 	.ops		= &clkops_null,
- + 	.fixed_div	= 2,
- + 	.recalc		= &omap_fixed_divisor_recalc,
- + };
- + 
- + static struct clk l4hs_gclk = {
- + 	.name		= "l4hs_gclk",
- + 	.parent		= &sysclk1_ck,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk gfx_l3_gclk = {
- + 	.name		= "gfx_l3_gclk",
- + 	.clkdm_name	= "gfx_l3_clkdm",
- + 	.parent		= &sysclk1_ck,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk debug_clka_gclk = {
- + 	.name		= "debug_clka_gclk",
- + 	.parent		= &sysclk1_ck,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk l4_rtc_gclk = {
- + 	.name		= "l4_rtc_gclk",
- + 	.parent		= &sysclk1_ck,
- + 	.ops		= &clkops_null,
- + 	.fixed_div	= 2,
- + 	.recalc		= &omap_fixed_divisor_recalc,
- + };
- + 
- + static struct clk rtc_ick = {
- + 	.name		= "rtc_ick",
- + 	.parent		= &l4_rtc_gclk,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk l3s_gclk = {
- + 	.name		= "l3s_gclk",
- + 	.parent		= &core_100mhz_ck,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk l4fw_gclk = {
- + 	.name		= "l4fw_gclk",
- + 	.parent		= &core_100mhz_ck,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk l4ls_gclk = {
- + 	.name		= "l4ls_gclk",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &core_100mhz_ck,
- + 	.enable_reg	= AM33XX_CM_PER_L4LS_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk clk_24mhz = {
- + 	.name		= "clk_24mhz",
- + 	.parent		= &per_192mhz_clk,
- + 	.fixed_div	= 8,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &omap_fixed_divisor_recalc,
- + };
- + 
- + static struct clk l4_cefuse_gclk = {
- + 	.name		= "l4_cefsue_gclk",
- + 	.parent		= &core_100mhz_ck,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk cefuse_iclk = {
- + 	.name		= "cefuse_iclk",
- + 	.clkdm_name	= "l4_cefuse_clkdm",
- + 	.parent		= &l4_cefuse_gclk,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk cefuse_fck = {
- + 	.name		= "cefuse_fck",
- + 	.clkdm_name	= "l4_cefuse_clkdm",
- + 	.parent		= &sys_clkin_ck,
- + 	.enable_reg	= AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk sysclk_div_ck = {
- + 	.name		= "sysclk_div_ck",
- + 	.parent		= &dpll_core_m4_ck,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk adc_tsc_fck = {
- + 	.name		= "adc_tsc_fck",
- + 	.clkdm_name	= "l4_wkup_clkdm",
- + 	.parent		= &sys_clkin_ck,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk adc_tsc_ick = {
- + 	.name		= "adc_tsc_ick",
- + 	.clkdm_name	= "l4_wkup_clkdm",
- + 	.parent		= &l4_wkup_gclk,
- + 	.enable_reg	= AM33XX_CM_WKUP_ADC_TSC_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk aes0_fck = {
- + 	.name		= "aes0_fck",
- + 	.clkdm_name	= "l3_clkdm",
- + 	.parent		= &l3_gclk,
- + 	.enable_reg	= AM33XX_CM_PER_AES0_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + /*
- +  * clkdiv32 is generated from fixed division of 732.4219
- +  */
- + static struct clk clkdiv32k_ick = {
- + 	.name		= "clkdiv32k_ick",
- + 	.clkdm_name	= "clk_24mhz_clkdm",
- + 	.rate		= 32768,
- + 	.parent		= &clk_24mhz,
- + 	.enable_reg	= AM33XX_CM_PER_CLKDIV32K_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + };
- + 
- + static struct clk clk_32khz_ck = {
- + 	.name		= "clk_32khz_ck",
- + 	.clkdm_name	= "clk_24mhz_clkdm",
- + 	.parent		= &clkdiv32k_ick,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk control_fck = {
- + 	.name		= "control_fck",
- + 	.clkdm_name	= "l4_wkup_clkdm",
- + 	.parent		= &l4_wkup_gclk,
- + 	.enable_reg	= AM33XX_CM_WKUP_CONTROL_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk dcan0_ick = {
- + 	.name		= "dcan0_ick",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &l4ls_gclk,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk dcan0_fck = {
- + 	.name		= "dcan0_fck",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &sys_clkin_ck,
- + 	.enable_reg	= AM33XX_CM_PER_DCAN0_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk dcan1_ick = {
- + 	.name		= "dcan1_ick",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &l4ls_gclk,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk dcan1_fck = {
- + 	.name		= "dcan1_fck",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &sys_clkin_ck,
- + 	.enable_reg	= AM33XX_CM_PER_DCAN1_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk debugss_ick = {
- + 	.name		= "debugss_ick",
- + 	.clkdm_name	= "l3_aon_clkdm",
- + 	.parent		= &l3_aon_gclk,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.enable_reg	= AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk elm_fck = {
- + 	.name		= "elm_fck",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &l4ls_gclk,
- + 	.enable_reg	= AM33XX_CM_PER_ELM_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk emif_fw_fck = {
- + 	.name		= "emif_fw_fck",
- + 	.clkdm_name	= "l4fw_clkdm",
- + 	.parent		= &l4fw_gclk,
- + 	.enable_reg	= AM33XX_CM_PER_EMIF_FW_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk epwmss0_fck = {
- + 	.name		= "epwmss0_fck",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &l4ls_gclk,
- + 	.enable_reg	= AM33XX_CM_PER_EPWMSS0_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk epwmss1_fck = {
- + 	.name		= "epwmss1_fck",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &l4ls_gclk,
- + 	.enable_reg	= AM33XX_CM_PER_EPWMSS1_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk epwmss2_fck = {
- + 	.name		= "epwmss2_fck",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &l4ls_gclk,
- + 	.enable_reg	= AM33XX_CM_PER_EPWMSS2_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk gpmc_fck = {
- + 	.name		= "gpmc_fck",
- + 	.clkdm_name	= "l3s_clkdm",
- + 	.parent		= &l3s_gclk,
- + 	.enable_reg	= AM33XX_CM_PER_GPMC_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk i2c1_ick = {
- + 	.name		= "i2c1_ick",
- + 	.clkdm_name	= "l4_wkup_clkdm",
- + 	.parent		= &l4_wkup_gclk,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk i2c1_fck = {
- + 	.name		= "i2c1_fck",
- + 	.clkdm_name	= "l4_wkup_clkdm",
- + 	.parent		= &per_192mhz_clk,
- + 	.enable_reg	= AM33XX_CM_WKUP_I2C0_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.fixed_div	= 4,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &omap_fixed_divisor_recalc,
- + };
- + 
- + static struct clk i2c2_ick = {
- + 	.name		= "i2c2_ick",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &l4ls_gclk,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk i2c2_fck = {
- + 	.name		= "i2c2_fck",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &per_192mhz_clk,
- + 	.enable_reg	= AM33XX_CM_PER_I2C1_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.fixed_div	= 4,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &omap_fixed_divisor_recalc,
- + };
- + 
- + static struct clk i2c3_ick = {
- + 	.name		= "i2c3_ick",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &l4ls_gclk,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk i2c3_fck = {
- + 	.name		= "i2c3_fck",
- + 	.parent		= &per_192mhz_clk,
- + 	.enable_reg	= AM33XX_CM_PER_I2C2_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.fixed_div	= 4,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &omap_fixed_divisor_recalc,
- + };
- + 
- + static struct clk ieee5000_fck = {
- + 	.name		= "ieee5000_fck",
- + 	.clkdm_name	= "l3s_clkdm",
- + 	.parent		= &l3s_gclk,
- + 	.enable_reg	= AM33XX_CM_PER_IEEE5000_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk l4hs_ick = {
- + 	.name		= "l4hs_ick",
- + 	.clkdm_name	= "l4hs_clkdm",
- + 	.parent		= &l4hs_gclk,
- + 	.enable_reg	= AM33XX_CM_PER_L4HS_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.flags		= ENABLE_ON_INIT,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk l4wkup_ick = {
- + 	.name		= "l4wkup_ick",
- + 	.clkdm_name	= "l4_wkup_aon_clkdm",
- + 	.parent		= &l4_wkup_aon_gclk,
- + 	.enable_reg	= AM33XX_CM_L4_WKUP_AON_CLKSTCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.flags		= ENABLE_ON_INIT,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk l4fw_ick = {
- + 	.name		= "l4fw_ick",
- + 	.clkdm_name	= "l4fw_clkdm",
- + 	.parent		= &core_100mhz_ck,
- + 	.enable_reg	= AM33XX_CM_PER_L4FW_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.flags		= ENABLE_ON_INIT,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk l4ls_ick = {
- + 	.name		= "l4ls_ick",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &l4ls_gclk,
- + 	.enable_reg	= AM33XX_CM_PER_L4LS_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.flags		= ENABLE_ON_INIT,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk mailbox0_fck = {
- + 	.name		= "mailbox0_fck",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &l4ls_gclk,
- + 	.enable_reg	= AM33XX_CM_PER_MAILBOX0_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk mcasp0_ick = {
- + 	.name		= "mcasp0_ick",
- + 	.parent		= &l3s_gclk,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk mcasp0_fck = {
- + 	.name		= "mcasp0_fck",
- + 	.clkdm_name	= "l3s_clkdm",
- + 	.parent		= &sys_clkin_ck,
- + 	.enable_reg	= AM33XX_CM_PER_MCASP0_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk mcasp1_ick = {
- + 	.name		= "mcasp1_ick",
- + 	.parent		= &l3s_gclk,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk mcasp1_fck = {
- + 	.name		= "mcasp1_fck",
- + 	.clkdm_name	= "l3s_clkdm",
- + 	.parent		= &sys_clkin_ck,
- + 	.enable_reg	= AM33XX_CM_PER_MCASP1_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk mlb_fck = {
- + 	.name		= "mlb_fck",
- + 	.ops		= &clkops_omap2_dflt,
- + 	.enable_reg	= AM33XX_CM_PER_MLB_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.clkdm_name	= "l3_clkdm",
- + 	.parent		= &sysclk_div_ck,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk mmu_fck = {
- + 	.name		= "mmu_fck",
- + 	.clkdm_name	= "gfx_l3_clkdm",
- + 	.parent		= &gfx_l3_gclk,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.enable_reg	= AM33XX_CM_GFX_MMUDATA_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk ocmcram_ick = {
- + 	.name		= "ocmcram_ick",
- + 	.clkdm_name	= "l3_clkdm",
- + 	.parent		= &l3_gclk,
- + 	.enable_reg	= AM33XX_CM_PER_OCMCRAM_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk ocpwp_fck = {
- + 	.name		= "ocpwp_fck",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &l4ls_gclk,
- + 	.enable_reg	= AM33XX_CM_PER_OCPWP_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk pka_fck = {
- + 	.name		= "pka_fck",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &l4ls_gclk,
- + 	.enable_reg	= AM33XX_CM_PER_PKA_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk rng_fck = {
- + 	.name		= "rng_fck",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &l4ls_gclk,
- + 	.enable_reg	= AM33XX_CM_PER_RNG_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk rtc_fck = {
- + 	.name		= "rtc_fck",
- + 	.clkdm_name	= "l4_rtc_clkdm",
- + 	.parent		= &clk_32768_ck,
- + 	.enable_reg	= AM33XX_CM_RTC_RTC_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk sha0_fck = {
- + 	.name		= "sha0_fck",
- + 	.clkdm_name	= "l3_clkdm",
- + 	.parent		= &l3_gclk,
- + 	.enable_reg	= AM33XX_CM_PER_SHA0_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk smartreflex0_ick = {
- + 	.name		= "smartreflex0_ick",
- + 	.parent		= &l4_wkup_gclk,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk smartreflex0_fck = {
- + 	.name		= "smartreflex0_fck",
- + 	.clkdm_name	= "l4_wkup_clkdm",
- + 	.parent		= &sys_clkin_ck,
- + 	.enable_reg	= AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk smartreflex1_ick = {
- + 	.name		= "smartreflex1_ick",
- + 	.parent		= &l4_wkup_gclk,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk smartreflex1_fck = {
- + 	.name		= "smartreflex1_fck",
- + 	.clkdm_name	= "l4_wkup_clkdm",
- + 	.parent		= &sys_clkin_ck,
- + 	.enable_reg	= AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk spi0_ick = {
- + 	.name		= "spi0_ick",
- + 	.parent		= &l4ls_gclk,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk spi0_fck = {
- + 	.name		= "spi0_fck",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &per_192mhz_clk,
- + 	.enable_reg	= AM33XX_CM_PER_SPI0_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.fixed_div	= 4,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &omap_fixed_divisor_recalc,
- + };
- + 
- + static struct clk spi1_ick = {
- + 	.name		= "spi1_ick",
- + 	.parent		= &l4ls_gclk,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk spi1_fck = {
- + 	.name		= "spi1_fck",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &per_192mhz_clk,
- + 	.enable_reg	= AM33XX_CM_PER_SPI1_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.fixed_div	= 4,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &omap_fixed_divisor_recalc,
- + };
- + 
- + static struct clk spinlock_fck = {
- + 	.name		= "spinlock_fck",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &l4ls_gclk,
- + 	.enable_reg	= AM33XX_CM_PER_SPINLOCK_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk clk_32khz_timer = {
- + 	.name		= "clk_32khz_timer",
- + 	.parent		= &clk_32khz_ck,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + /* Timers */
- + 
- + /* Secure Timer: Used only to disable the clocks and for completeness */
- + static const struct clksel timer0_clkmux_sel[] = {
- + 	{ .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
- + 	{ .parent = &clk_32khz_ck, .rates = div_1_1_rates },
- + 	{ .parent = &sys_clkin_ck, .rates = div_1_2_rates },
- + 	{ .parent = &tclkin_ck, .rates = div_1_3_rates },
- + 	{ .parent = NULL },
- + };
- + 
- + static struct clk timer0_ick = {
- + 	.name		= "timer0_ick",
- + 	.parent		= &l4_wkup_gclk,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk timer0_fck = {
- + 	.name		= "timer0_fck",
- + 	.clkdm_name	= "l4_wkup_clkdm",
- + 	.parent		= &clk_rc32k_ck,
- + 	.clksel		= timer0_clkmux_sel,
- + 	.enable_reg	= AM33XX_CM_WKUP_TIMER0_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.clksel_reg	= AM33XX_CTRL_REGADDR(0x01BC),
- + 	.clksel_mask	= (0x3 << 4),
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static const struct clksel timer1_clkmux_sel[] = {
- + 	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
- + 	{ .parent = &clk_32khz_ck, .rates = div_1_1_rates },
- + 	{ .parent = &tclkin_ck, .rates = div_1_2_rates },
- + 	{ .parent = &clk_rc32k_ck, .rates = div_1_3_rates },
- + 	{ .parent = &clk_32768_ck, .rates = div_1_4_rates },
- + 	{ .parent = NULL },
- + };
- + 
- + static struct clk timer1_ick = {
- + 	.name		= "timer1_ick",
- + 	.parent		= &l4_wkup_gclk,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk timer1_fck = {
- + 	.name		= "timer1_fck",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &sys_clkin_ck,
- + 	.init		= &omap2_init_clksel_parent,
- + 	.clksel		= timer1_clkmux_sel,
- + 	.enable_reg	= AM33XX_CM_WKUP_TIMER1_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.clksel_reg	= AM33XX_CLKSEL_TIMER1MS_CLK,
- + 	.clksel_mask	= AM33XX_CLKSEL_0_2_MASK,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &omap2_clksel_recalc,
- + };
- + 
- + static const struct clksel timer2_to_7_clk_sel[] = {
- + 	{ .parent = &tclkin_ck, .rates = div_1_0_rates },
- + 	{ .parent = &sys_clkin_ck, .rates = div_1_1_rates },
- + 	{ .parent = &clk_32khz_timer, .rates = div_1_2_rates },
- + 	{ .parent = NULL },
- + };
- + 
- + static struct clk timer2_ick = {
- + 	.name		= "timer2_ick",
- + 	.parent		= &l4ls_gclk,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk timer2_fck = {
- + 	.name		= "timer2_fck",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &sys_clkin_ck,
- + 	.init		= &omap2_init_clksel_parent,
- + 	.clksel		= timer2_to_7_clk_sel,
- + 	.enable_reg	= AM33XX_CM_PER_TIMER2_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.clksel_reg	= AM33XX_CLKSEL_TIMER2_CLK,
- + 	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &omap2_clksel_recalc,
- + };
- + 
- + static struct clk timer3_ick = {
- + 	.name		= "timer3_ick",
- + 	.parent		= &l4ls_gclk,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk timer3_fck = {
- + 	.name		= "timer3_fck",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &sys_clkin_ck,
- + 	.init		= &am33xx_init_timer_parent,
- + 	.clksel		= timer2_to_7_clk_sel,
- + 	.enable_reg	= AM33XX_CM_PER_TIMER3_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.clksel_reg	= AM33XX_CLKSEL_TIMER3_CLK,
- + 	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &omap2_clksel_recalc,
- + };
- + 
- + static struct clk timer4_ick = {
- + 	.name		= "timer4_ick",
- + 	.parent		= &l4ls_gclk,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk timer4_fck = {
- + 	.name		= "timer4_fck",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &sys_clkin_ck,
- + 	.init		= &omap2_init_clksel_parent,
- + 	.clksel		= timer2_to_7_clk_sel,
- + 	.enable_reg	= AM33XX_CM_PER_TIMER4_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.clksel_reg	= AM33XX_CLKSEL_TIMER4_CLK,
- + 	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &omap2_clksel_recalc,
- + };
- + 
- + static struct clk timer5_ick = {
- + 	.name		= "timer5_ick",
- + 	.parent		= &l4ls_gclk,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk timer5_fck = {
- + 	.name		= "timer5_fck",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &sys_clkin_ck,
- + 	.init		= &omap2_init_clksel_parent,
- + 	.clksel		= timer2_to_7_clk_sel,
- + 	.enable_reg	= AM33XX_CM_PER_TIMER5_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.clksel_reg	= AM33XX_CLKSEL_TIMER5_CLK,
- + 	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &omap2_clksel_recalc,
- + };
- + 
- + static struct clk timer6_ick = {
- + 	.name		= "timer6_ick",
- + 	.parent		= &l4ls_gclk,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk timer6_fck = {
- + 	.name		= "timer6_fck",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &sys_clkin_ck,
- + 	.init		= &am33xx_init_timer_parent,
- + 	.clksel		= timer2_to_7_clk_sel,
- + 	.enable_reg	= AM33XX_CM_PER_TIMER6_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.clksel_reg	= AM33XX_CLKSEL_TIMER6_CLK,
- + 	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &omap2_clksel_recalc,
- + };
- + 
- + static struct clk timer7_ick = {
- + 	.name		= "timer7_ick",
- + 	.parent		= &l4ls_gclk,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk timer7_fck = {
- + 	.name		= "timer7_fck",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &sys_clkin_ck,
- + 	.init		= &omap2_init_clksel_parent,
- + 	.clksel		= timer2_to_7_clk_sel,
- + 	.enable_reg	= AM33XX_CM_PER_TIMER7_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.clksel_reg	= AM33XX_CLKSEL_TIMER7_CLK,
- + 	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &omap2_clksel_recalc,
- + };
- + 
- + static struct clk tpcc_ick = {
- + 	.name		= "tpcc_ick",
- + 	.clkdm_name	= "l3_clkdm",
- + 	.parent		= &l3_gclk,
- + 	.enable_reg	= AM33XX_CM_PER_TPCC_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk tptc0_ick = {
- + 	.name		= "tptc0_ick",
- + 	.parent		= &l3_gclk,
- + 	.clkdm_name	= "l3_clkdm",
- + 	.enable_reg	= AM33XX_CM_PER_TPTC0_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk tptc1_ick = {
- + 	.name		= "tptc1_ick",
- + 	.clkdm_name	= "l3_clkdm",
- + 	.parent		= &l3_gclk,
- + 	.enable_reg	= AM33XX_CM_PER_TPTC1_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk tptc2_ick = {
- + 	.name		= "tptc2_ick",
- + 	.clkdm_name	= "l3_clkdm",
- + 	.parent		= &l3_gclk,
- + 	.enable_reg	= AM33XX_CM_PER_TPTC2_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk uart1_ick = {
- + 	.name		= "uart1_ick",
- + 	.parent		= &l4_wkup_gclk,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk uart1_fck = {
- + 	.name		= "uart1_fck",
- + 	.clkdm_name	= "l4_wkup_clkdm",
- + 	.parent		= &per_192mhz_clk,
- + 	.enable_reg	= AM33XX_CM_WKUP_UART0_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.fixed_div	= 4,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &omap_fixed_divisor_recalc,
- + };
- + 
- + static struct clk uart2_ick = {
- + 	.name		= "uart2_ick",
- + 	.parent		= &l4ls_gclk,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk uart2_fck = {
- + 	.name		= "uart2_fck",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &per_192mhz_clk,
- + 	.enable_reg	= AM33XX_CM_PER_UART1_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.fixed_div	= 4,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &omap_fixed_divisor_recalc,
- + };
- + 
- + static struct clk uart3_ick = {
- + 	.name		= "uart3_ick",
- + 	.parent		= &l4ls_gclk,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk uart3_fck = {
- + 	.name		= "uart3_fck",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &per_192mhz_clk,
- + 	.enable_reg	= AM33XX_CM_PER_UART2_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.fixed_div	= 4,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &omap_fixed_divisor_recalc,
- + };
- + 
- + static struct clk uart4_ick = {
- + 	.name		= "uart4_ick",
- + 	.parent		= &l4ls_gclk,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk uart4_fck = {
- + 	.name		= "uart4_fck",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &per_192mhz_clk,
- + 	.enable_reg	= AM33XX_CM_PER_UART3_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.fixed_div	= 4,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &omap_fixed_divisor_recalc,
- + };
- + 
- + static struct clk uart5_ick = {
- + 	.name		= "uart5_ick",
- + 	.parent		= &l4ls_gclk,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk uart5_fck = {
- + 	.name		= "uart5_fck",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &per_192mhz_clk,
- + 	.enable_reg	= AM33XX_CM_PER_UART4_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.fixed_div	= 4,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &omap_fixed_divisor_recalc,
- + };
- + 
- + static struct clk uart6_ick = {
- + 	.name		= "uart6_ick",
- + 	.parent		= &l4ls_gclk,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk uart6_fck = {
- + 	.name		= "uart6_fck",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &per_192mhz_clk,
- + 	.enable_reg	= AM33XX_CM_PER_UART5_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.fixed_div	= 4,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &omap_fixed_divisor_recalc,
- + };
- + 
- + static struct clk wkup_m3_fck = {
- + 	.name		= "wkup_m3_fck",
- + 	.clkdm_name	= "l4_wkup_aon_clkdm",
- + 	.parent		= &l4_wkup_aon_gclk,
- + 	.enable_reg	= AM33XX_CM_WKUP_WKUP_M3_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk cpsw_250mhz_clk = {
- + 	.name		= "cpsw_250mhz_clk",
- + 	.clkdm_name	= "l4hs_clkdm",
- + 	.parent		= &sysclk2_ck,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk cpsw_125mhz_gclk = {
- + 	.name		= "cpsw_125mhz_gclk",
- + 	.clkdm_name	= "cpsw_125mhz_clkdm",
- + 	.parent		= &sysclk2_ck,
- + 	.ops		= &clkops_null,
- + 	.fixed_div	= 2,
- + 	.recalc		= &omap_fixed_divisor_recalc,
- + };
- + 
- + /*
- +  * TODO: As per clock tree @OPP50 /2 is used, but there is not register
- +  * to configure this. @ normal OPP, /5 is used - 250MHz/5 = 50MHz
- +  */
- + static struct clk cpsw_50mhz_clk = {
- + 	.name		= "cpsw_50mhz_clk",
- + 	.clkdm_name	= "l4hs_clkdm",
- + 	.parent		= &sysclk2_ck,
- + 	.ops		= &clkops_null,
- + 	.fixed_div	= 5,
- + 	.recalc		= &omap_fixed_divisor_recalc,
- + };
- + 
- + static struct clk cpsw_5mhz_clk = {
- + 	.name		= "cpsw_5mhz_clk",
- + 	.clkdm_name	= "l4hs_clkdm",
- + 	.parent		= &cpsw_50mhz_clk,
- + 	.ops		= &clkops_null,
- + 	.fixed_div	= 10,
- + 	.recalc		= &omap_fixed_divisor_recalc,
- + };
- + 
- + static struct clk cpgmac0_ick = {
- + 	.name		= "cpgmac0_ick",
- + 	.clkdm_name	= "cpsw_125mhz_clkdm",
- + 	.ops		= &clkops_omap2_dflt,
- + 	.enable_reg	= AM33XX_CM_PER_CPGMAC0_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.parent		= &cpsw_125mhz_gclk,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static const struct clksel cpsw_cpts_rft_clkmux_sel[] = {
- + 	{ .parent = &sysclk2_ck, .rates = div_1_0_rates },
- + 	{ .parent = &sysclk1_ck, .rates = div_1_1_rates },
- + 	{ .parent = NULL },
- + };
- + 
- + static struct clk cpsw_cpts_rft_clk = {
- + 	.name		= "cpsw_cpts_rft_clk",
- + 	.clkdm_name	= "l3_clkdm",
- + 	.parent		= &sysclk2_ck,
- + 	.clksel		= cpsw_cpts_rft_clkmux_sel,
- + 	.clksel_reg	= AM33XX_CM_CPTS_RFT_CLKSEL,
- + 	.clksel_mask	= AM33XX_CLKSEL_0_0_MASK,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk usbotg_ick = {
- + 	.name		= "usbotg_ick",
- + 	.clkdm_name	= "l3s_clkdm",
- + 	.parent		= &l3s_gclk,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.enable_reg	= AM33XX_CM_PER_USB0_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk usbotg_fck = {
- + 	.name		= "usbotg_fck",
- + 	.clkdm_name	= "l3s_clkdm",
- + 	.parent		= &usb_pll_clk,
- + 	.enable_reg	= AM33XX_CM_CLKDCOLDO_DPLL_PER,
- + 	.enable_bit	= AM33XX_ST_DPLL_CLKDCOLDO_SHIFT,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + /* gpio */
- + static const struct clksel gpio0_dbclk_mux_sel[] = {
- + 	{ .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
- + 	{ .parent = &clk_32768_ck, .rates = div_1_1_rates },
- + 	{ .parent = &clk_32khz_timer, .rates = div_1_2_rates },
- + 	{ .parent = NULL },
- + };
- + 
- + static struct clk gpio0_dbclk_mux_ck = {
- + 	.name		= "gpio0_dbclk_mux_ck",
- + 	.clkdm_name	= "l4_wkup_clkdm",
- + 	.parent		= &clk_rc32k_ck,
- + 	.init		= &omap2_init_clksel_parent,
- + 	.clksel		= gpio0_dbclk_mux_sel,
- + 	.clksel_reg	= AM33XX_CLKSEL_GPIO0_DBCLK,
- + 	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &omap2_clksel_recalc,
- + };
- + 
- + static struct clk gpio0_dbclk = {
- + 	.name		= "gpio0_dbclk",
- + 	.clkdm_name	= "l4_wkup_clkdm",
- + 	.parent		= &gpio0_dbclk_mux_ck,
- + 	.enable_reg	= AM33XX_CM_WKUP_GPIO0_CLKCTRL,
- + 	.enable_bit	= AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk gpio0_ick = {
- + 	.name		= "gpio0_ick",
- + 	.clkdm_name	= "l4_wkup_clkdm",
- + 	.parent		= &l4_wkup_gclk,
- + 	.enable_reg	= AM33XX_CM_WKUP_GPIO0_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk gpio1_dbclk = {
- + 	.name		= "gpio1_dbclk",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &clkdiv32k_ick,
- + 	.enable_reg	= AM33XX_CM_PER_GPIO1_CLKCTRL,
- + 	.enable_bit	= AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk gpio1_ick = {
- + 	.name		= "gpio1_ick",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &l4ls_gclk,
- + 	.enable_reg	= AM33XX_CM_PER_GPIO1_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk gpio2_dbclk = {
- + 	.name		= "gpio2_dbclk",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &clkdiv32k_ick,
- + 	.enable_reg	= AM33XX_CM_PER_GPIO2_CLKCTRL,
- + 	.enable_bit	= AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk gpio2_ick = {
- + 	.name		= "gpio2_ick",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &l4ls_gclk,
- + 	.enable_reg	= AM33XX_CM_PER_GPIO2_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk gpio3_dbclk = {
- + 	.name		= "gpio3_dbclk",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &clkdiv32k_ick,
- + 	.enable_reg	= AM33XX_CM_PER_GPIO3_CLKCTRL,
- + 	.enable_bit	= AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk gpio3_ick = {
- + 	.name		= "gpio3_ick",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &l4ls_gclk,
- + 	.enable_reg	= AM33XX_CM_PER_GPIO3_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static const struct clksel pruss_ocp_clk_mux_sel[] = {
- + 	{ .parent = &l3_gclk, .rates = div_1_0_rates },
- + 	{ .parent = &disp_pll_clk, .rates = div_1_1_rates },
- + 	{ .parent = NULL },
- + };
- + 
- + static struct clk pruss_ocp_gclk = {
- + 	.name		= "pruss_ocp_gclk",
- + 	.parent		= &l3_gclk,
- + 	.init		= &omap2_init_clksel_parent,
- + 	.clksel		= pruss_ocp_clk_mux_sel,
- + 	.clksel_reg	= AM33XX_CLKSEL_PRUSS_OCP_CLK,
- + 	.clksel_mask	= AM33XX_CLKSEL_0_0_MASK,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk pruss_iep_gclk = {
- + 	.name		= "pruss_iep_gclk",
- + 	.clkdm_name	= "pruss_ocp_clkdm",
- + 	.parent		= &l3_gclk,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk pruss_uart_gclk = {
- + 	.name		= "pruss_uart_gclk",
- + 	.clkdm_name	= "pruss_ocp_clkdm",
- + 	.parent		= &per_192mhz_clk,
- + 	.enable_reg	= AM33XX_CM_PER_PRUSS_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk lcdc_ick = {
- + 	.name		= "lcdc_ick",
- + 	.clkdm_name	= "l3_clkdm",
- + 	.parent		= &sysclk1_ck,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static const struct clksel lcd_clk_mux_sel[] = {
- + 	{ .parent = &disp_pll_clk, .rates = div_1_0_rates },
- + 	{ .parent = &sysclk2_ck, .rates = div_1_1_rates },
- + 	{ .parent = &per_192mhz_clk, .rates = div_1_2_rates },
- + 	{ .parent = NULL },
- + };
- + 
- + static struct clk lcd_gclk = {
- + 	.name		= "lcd_gclk",
- + 	.parent		= &disp_pll_clk,
- + 	.init		= &omap2_init_clksel_parent,
- + 	.clksel		= lcd_clk_mux_sel,
- + 	.clksel_reg	= AM33XX_CLKSEL_LCDC_PIXEL_CLK,
- + 	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk lcdc_fck = {
- + 	.name		= "lcdc_fck",
- + 	.clkdm_name	= "lcdc_clkdm",
- + 	.parent		= &lcd_gclk,
- + 	.enable_reg	= AM33XX_CM_PER_LCDC_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk mmc_clk = {
- + 	.name		= "mmc_clk",
- + 	.parent		= &per_192mhz_clk,
- + 	.ops		= &clkops_null,
- + 	.fixed_div	= 2,
- + 	.recalc		= &omap_fixed_divisor_recalc,
- + };
- + 
- + static struct clk mmc0_ick = {
- + 	.name		= "mmc0_ick",
- + 	.parent		= &l4ls_gclk,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk mmc0_fck = {
- + 	.name		= "mmc0_fck",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &mmc_clk,
- + 	.enable_reg	= AM33XX_CM_PER_MMC0_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk mmc1_ick = {
- + 	.name		= "mmc1_ick",
- + 	.parent		= &l4ls_gclk,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk mmc1_fck = {
- + 	.name		= "mmc1_fck",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.parent		= &mmc_clk,
- + 	.enable_reg	= AM33XX_CM_PER_MMC1_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk mmc2_ick = {
- + 	.name		= "mmc2_ick",
- + 	.parent		= &l4ls_gclk,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk mmc2_fck = {
- + 	.name		= "mmc2_fck",
- + 	.clkdm_name	= "l3s_clkdm",
- + 	.parent		= &mmc_clk,
- + 	.enable_reg	= AM33XX_CM_PER_MMC2_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static const struct clksel gfx_clksel_sel[] = {
- + 	{ .parent = &sysclk1_ck, .rates = div_1_0_rates },
- + 	{ .parent = &per_192mhz_clk, .rates = div_1_1_rates },
- + 	{ .parent = NULL },
- + };
- + 
- + static struct clk gfx_fclk_clksel_ck = {
- + 	.name		= "gfx_fclk_clksel_ck",
- + 	.parent		= &sysclk1_ck,
- + 	.clksel		= gfx_clksel_sel,
- + 	.ops		= &clkops_null,
- + 	.clksel_reg	= AM33XX_CLKSEL_GFX_FCLK,
- + 	.clksel_mask	= AM33XX_CLKSEL_GFX_FCLK_MASK,
- + 	.recalc		= &omap2_clksel_recalc,
- + };
- + 
- + static const struct clksel_rate div_1_0_2_1_rates[] = {
- + 	{ .div = 1, .val = 0, .flags = RATE_IN_AM33XX },
- + 	{ .div = 2, .val = 1, .flags = RATE_IN_AM33XX },
- + 	{ .div = 0 },
- + };
- + 
- + static const struct clksel gfx_div_sel[] = {
- + 	{ .parent = &gfx_fclk_clksel_ck, .rates = div_1_0_2_1_rates },
- + 	{ .parent = NULL },
- + };
- + 
- + static struct clk gfx_ick = {
- + 	.name		= "gfx_ick",
- + 	.clkdm_name	= "gfx_l3_clkdm",
- + 	.parent		= &gfx_l3_gclk,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk gfx_fclk = {
- + 	.name		= "gfx_fclk",
- + 	.clkdm_name	= "gfx_l3_clkdm",
- + 	.parent		= &gfx_fclk_clksel_ck,
- + 	.clksel		= gfx_div_sel,
- + 	.enable_reg	= AM33XX_CM_GFX_GFX_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.clksel_reg	= AM33XX_CLKSEL_GFX_FCLK,
- + 	.clksel_mask	= AM33XX_CLKSEL_0_0_MASK,
- + 	.recalc		= &omap2_clksel_recalc,
- + 	.round_rate	= &omap2_clksel_round_rate,
- + 	.set_rate	= &omap2_clksel_set_rate,
- + 	.ops		= &clkops_omap2_dflt,
- + };
- + 
- + static const struct clksel sysclkout_pre_sel[] = {
- + 	{ .parent = &clk_32768_ck, .rates = div_1_0_rates },
- + 	{ .parent = &l3_gclk, .rates = div_1_1_rates },
- + 	{ .parent = &ddr_pll_clk, .rates = div_1_2_rates },
- + 	{ .parent = &per_192mhz_clk, .rates = div_1_3_rates },
- + 	{ .parent = &lcd_gclk, .rates = div_1_4_rates },
- + 	{ .parent = NULL },
- + };
- + 
- + static struct clk sysclkout_pre_ck = {
- + 	.name		= "sysclkout_pre_ck",
- + 	.parent		= &clk_32768_ck,
- + 	.init		= &omap2_init_clksel_parent,
- + 	.clksel		= sysclkout_pre_sel,
- + 	.clksel_reg	= AM33XX_CM_CLKOUT_CTRL,
- + 	.clksel_mask	= AM33XX_CLKOUT2SOURCE_MASK,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &omap2_clksel_recalc,
- + };
- + 
- + /* Divide by 8 clock rates with default clock is 1/1*/
- + static const struct clksel_rate div8_rates[] = {
- + 	{ .div = 1, .val = 0, .flags = RATE_IN_AM33XX },
- + 	{ .div = 2, .val = 1, .flags = RATE_IN_AM33XX },
- + 	{ .div = 3, .val = 2, .flags = RATE_IN_AM33XX },
- + 	{ .div = 4, .val = 3, .flags = RATE_IN_AM33XX },
- + 	{ .div = 5, .val = 4, .flags = RATE_IN_AM33XX },
- + 	{ .div = 6, .val = 5, .flags = RATE_IN_AM33XX },
- + 	{ .div = 7, .val = 6, .flags = RATE_IN_AM33XX },
- + 	{ .div = 8, .val = 7, .flags = RATE_IN_AM33XX },
- + 	{ .div = 0 },
- + };
- + 
- + static const struct clksel clkout2_div[] = {
- + 	{ .parent = &sysclkout_pre_ck, .rates = div8_rates },
- + 	{ .parent = NULL },
- + };
- + 
- + static struct clk clkout2_ck = {
- + 	.name		= "clkout2_ck",
- + 	.parent		= &sysclkout_pre_ck,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.clksel		= clkout2_div,
- + 	.clksel_reg	= AM33XX_CM_CLKOUT_CTRL,
- + 	.clksel_mask	= AM33XX_CLKOUT2DIV_MASK,
- + 	.enable_reg	= AM33XX_CM_CLKOUT_CTRL,
- + 	.enable_bit	= AM33XX_CLKOUT2EN_SHIFT,
- + 	.recalc		= &omap2_clksel_recalc,
- + 	.round_rate	= &omap2_clksel_round_rate,
- + 	.set_rate	= &omap2_clksel_set_rate,
- + };
- + 
- + static struct clk vtp_clk = {
- + 	.name		= "vtp_clk",
- + 	.parent		= &sys_clkin_ck,
- + 	.ops		= &clkops_null,
- + 	.fixed_div	= 2,
- + 	.recalc		= &omap_fixed_divisor_recalc,
- + };
- + 
- + static const struct clksel wdt_clkmux_sel[] = {
- + 	{ .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
- + 	{ .parent = &clk_32khz_ck, .rates = div_1_1_rates },
- + 	{ .parent = NULL },
- + };
- + 
- + static struct clk wdt0_ick = {
- + 	.name		= "wdt0_ick",
- + 	.parent		= &l4_wkup_gclk,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk wdt0_fck = {
- + 	.name		= "wdt0_fck",
- + 	.clkdm_name	= "l4_wkup_clkdm",
- + 	.parent		= &clk_rc32k_ck,
- + 	.clksel		= wdt_clkmux_sel,
- + 	.enable_reg	= AM33XX_CM_WKUP_WDT0_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk wdt1_ick = {
- + 	.name		= "wdt1_ick",
- + 	.parent		= &l4_wkup_gclk,
- + 	.ops		= &clkops_null,
- + 	.recalc		= &followparent_recalc,
- + };
- + 
- + static struct clk wdt1_fck = {
- + 	.name		= "wdt1_fck",
- + 	.clkdm_name	= "l4_wkup_clkdm",
- + 	.parent		= &clk_32khz_ck,
- + 	.init		= &am33xx_init_timer_parent,
- + 	.clksel		= wdt_clkmux_sel,
- + 	.enable_reg	= AM33XX_CM_WKUP_WDT1_CLKCTRL,
- + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
- + 	.clksel_reg	= AM33XX_CLKSEL_WDT1_CLK,
- + 	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.recalc		= &omap2_clksel_recalc,
- + };
- + 
- + /*
- +  * Provides clock definitions for enabling bits for Time base module in
- +  * PWMSS ctrl register.
- +  */
- + 
- + static struct clk ehrpwm0_tbclk = {
- + 	.name		= "ehrpwm0_tbclk",
- + 	.enable_reg	= AM33XX_CONTROL_PWMSS_CTRL,
- + 	.enable_bit	= AM33XX_PWMSS0_TBCLKEN,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.flags		= ENABLE_ON_INIT,
- + };
- + 
- + static struct clk ehrpwm1_tbclk = {
- + 	.name		= "ehrpwm1_tbclk",
- + 	.enable_reg	= AM33XX_CONTROL_PWMSS_CTRL,
- + 	.enable_bit	= AM33XX_PWMSS1_TBCLKEN,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.flags		= ENABLE_ON_INIT,
- + };
- + 
- + static struct clk ehrpwm2_tbclk = {
- + 	.name		= "ehrpwm2_tbclk",
- + 	.enable_reg	= AM33XX_CONTROL_PWMSS_CTRL,
- + 	.enable_bit	= AM33XX_PWMSS2_TBCLKEN,
- + 	.ops		= &clkops_omap2_dflt,
- + 	.flags		= ENABLE_ON_INIT,
- + };
- + 
- + 
- + /*
- +  * clkdev
- +  */
- + static struct omap_clk am33xx_clks[] = {
- + 	CLK(NULL,	"clk_32768_ck",		&clk_32768_ck,	CK_AM33XX),
- + 	CLK(NULL,	"clk_32khz_ck",		&clk_32khz_ck,	CK_AM33XX),
- + 	CLK(NULL,	"clk_rc32k_ck",		&clk_rc32k_ck,	CK_AM33XX),
- + 	CLK(NULL,	"virt_19_2m_ck",	&virt_19_2m_ck,	CK_AM33XX),
- + 	CLK(NULL,	"virt_24m_ck",		&virt_24m_ck,	CK_AM33XX),
- + 	CLK(NULL,	"virt_25m_ck",		&virt_25m_ck,	CK_AM33XX),
- + 	CLK(NULL,	"virt_26m_ck",		&virt_26m_ck,	CK_AM33XX),
- + 	CLK(NULL,	"sys_clkin_ck",		&sys_clkin_ck,	CK_AM33XX),
- + 	CLK(NULL,	"tclkin_ck",		&tclkin_ck,	CK_AM33XX),
- + 	CLK(NULL,	"dpll_core_ck",		&dpll_core_ck,		CK_AM33XX),
- + 	CLK(NULL,	"dpll_core_x2_ck",	&dpll_core_x2_ck,	CK_AM33XX),
- + 	CLK(NULL,	"dpll_core_m4_ck",	&dpll_core_m4_ck,	CK_AM33XX),
- + 	CLK(NULL,	"dpll_core_m5_ck",	&dpll_core_m5_ck,	CK_AM33XX),
- + 	CLK(NULL,	"dpll_core_m6_ck",	&dpll_core_m6_ck,	CK_AM33XX),
- + 	CLK(NULL,	"sysclk1_ck",		&sysclk1_ck,	CK_AM33XX),
- + 	CLK(NULL,	"sysclk2_ck",		&sysclk2_ck,	CK_AM33XX),
- + 	CLK(NULL,	"core_clk_out",		&core_clk_out,	CK_AM33XX),
- + 	CLK(NULL,	"clk_32khz_timer",	&clk_32khz_timer, CK_AM33XX),
- + 	CLK(NULL,	"dpll_mpu_ck",		&dpll_mpu_ck,		CK_AM33XX),
- + 	CLK(NULL,	"dpll_mpu_m2_ck",	&dpll_mpu_m2_ck,	CK_AM33XX),
- + 	CLK(NULL,	"mpu_ck",		&mpu_fck,	CK_AM33XX),
- + 	CLK(NULL,	"dpll_ddr_ck",		&dpll_ddr_ck,		CK_AM33XX),
- + 	CLK(NULL,	"dpll_ddr_m2_ck",	&dpll_ddr_m2_ck,	CK_AM33XX),
- + 	CLK(NULL,	"ddr_pll_clk",		&ddr_pll_clk,	CK_AM33XX),
- + 	CLK(NULL,	"emif_fck",		&emif_fck,	CK_AM33XX),
- + 	CLK(NULL,	"emif_fw_fck",		&emif_fw_fck,	CK_AM33XX),
- + 	CLK(NULL,	"dpll_disp_ck",		&dpll_disp_ck,		CK_AM33XX),
- + 	CLK(NULL,	"dpll_disp_m2_ck",	&dpll_disp_m2_ck,	CK_AM33XX),
- + 	CLK(NULL,	"disp_pll_clk",		&disp_pll_clk,		CK_AM33XX),
- + 	CLK(NULL,	"dpll_per_ck",		&dpll_per_ck,	CK_AM33XX),
- + 	CLK(NULL,	"dpll_per_m2_ck",	&dpll_per_m2_ck,	CK_AM33XX),
- + 	CLK(NULL,	"per_192mhz_clk",	&per_192mhz_clk,	CK_AM33XX),
- + 	CLK(NULL,	"usb_pll_clk",		&usb_pll_clk,		CK_AM33XX),
- + 	CLK(NULL,	"core_100mhz_ck",	&core_100mhz_ck,	CK_AM33XX),
- + 	CLK(NULL,	"l3_ick",		&l3_ick,	CK_AM33XX),
- + 	CLK(NULL,	"l3_instr_ick",		&l3_instr_ick,	CK_AM33XX),
- + 	CLK(NULL,	"adc_tsc_fck",		&adc_tsc_fck,	CK_AM33XX),
- + 	CLK(NULL,	"adc_tsc_ick",		&adc_tsc_ick,	CK_AM33XX),
- + 	CLK(NULL,	"aes0_fck",		&aes0_fck,	CK_AM33XX),
- + 	CLK(NULL,	"l4_cefuse_gclk",	&l4_cefuse_gclk, CK_AM33XX),
- + 	CLK(NULL,	"cefuse_fck",		&cefuse_fck,	CK_AM33XX),
- + 	CLK(NULL,	"cefuse_iclk",		&cefuse_iclk,	CK_AM33XX),
- + 	CLK(NULL,	"clkdiv32k_ick",	&clkdiv32k_ick,	CK_AM33XX),
- + 	CLK(NULL,	"control_fck",		&control_fck,	CK_AM33XX),
- + 	CLK("cpsw.0",	NULL,			&cpgmac0_ick,	CK_AM33XX),
- + 	CLK("d_can.0",	"fck",			&dcan0_fck,	CK_AM33XX),
- + 	CLK("d_can.1",	"fck",			&dcan1_fck,	CK_AM33XX),
- + 	CLK("d_can.0",	"ick",			&dcan0_ick,	CK_AM33XX),
- + 	CLK("d_can.1",	"ick",			&dcan1_ick,	CK_AM33XX),
- + 	CLK(NULL,	"debugss_ick",		&debugss_ick,	CK_AM33XX),
- + 	CLK(NULL,	"elm_fck",		&elm_fck,	CK_AM33XX),
- + 	CLK(NULL,	"epwmss0_fck",		&epwmss0_fck,	CK_AM33XX),
- + 	CLK(NULL,	"epwmss1_fck",		&epwmss1_fck,	CK_AM33XX),
- + 	CLK(NULL,	"epwmss2_fck",		&epwmss2_fck,	CK_AM33XX),
- + 	CLK(NULL,	"gpio0_ick",		&gpio0_ick,	CK_AM33XX),
- + 	CLK(NULL,	"gpio1_ick",		&gpio1_ick,	CK_AM33XX),
- + 	CLK(NULL,	"gpio2_ick",		&gpio2_ick,	CK_AM33XX),
- + 	CLK(NULL,	"gpio3_ick",		&gpio3_ick,	CK_AM33XX),
- + 	CLK(NULL,	"gpmc_fck",		&gpmc_fck,	CK_AM33XX),
- + 	CLK("omap_i2c.1",	"fck",		&i2c1_fck,	CK_AM33XX),
- + 	CLK("omap_i2c.1",	"ick",		&i2c1_ick,	CK_AM33XX),
- + 	CLK("omap_i2c.2",	"fck",		&i2c2_fck,	CK_AM33XX),
- + 	CLK("omap_i2c.2",	"ick",		&i2c2_ick,	CK_AM33XX),
- + 	CLK("omap_i2c.3",	"fck",		&i2c3_fck,	CK_AM33XX),
- + 	CLK("omap_i2c.3",	"ick",		&i2c3_ick,	CK_AM33XX),
- + 	CLK(NULL,	"pruss_ocp_gclk",	&pruss_ocp_gclk,	CK_AM33XX),
- + 	CLK(NULL,	"pruss_uart_gclk",	&pruss_uart_gclk,	CK_AM33XX),
- + 	CLK(NULL,	"pruss_iep_gclk",	&pruss_iep_gclk,	CK_AM33XX),
- + 	CLK(NULL,	"ieee5000_fck",		&ieee5000_fck,	CK_AM33XX),
- + 	CLK(NULL,	"l4hs_ick",		&l4hs_ick,	CK_AM33XX),
- + 	CLK(NULL,	"l4wkup_ick",		&l4wkup_ick,	CK_AM33XX),
- + 	CLK(NULL,	"l4fw_ick",		&l4fw_ick,	CK_AM33XX),
- + 	CLK(NULL,	"l4ls_ick",		&l4ls_ick,	CK_AM33XX),
- + 	CLK("da8xx_lcdc.0",	NULL,		&lcdc_fck,	CK_AM33XX),
- + 	CLK(NULL,	"mailbox0_fck",		&mailbox0_fck,	CK_AM33XX),
- + 	CLK(NULL,	"mcasp1_ick",		&mcasp0_ick,	CK_AM33XX),
- + 	CLK("davinci-mcasp.0",	NULL,		&mcasp0_fck,	CK_AM33XX),
- + 	CLK(NULL,	"mcasp2_ick",		&mcasp1_ick,	CK_AM33XX),
- + 	CLK("davinci-mcasp.1",	NULL,		&mcasp1_fck,	CK_AM33XX),
- + 	CLK(NULL,	"mlb_fck",		&mlb_fck,	CK_AM33XX),
- + 	CLK("omap_hsmmc.0",	"ick",		&mmc0_ick,	CK_AM33XX),
- + 	CLK("omap_hsmmc.1",	"ick",		&mmc1_ick,	CK_AM33XX),
- + 	CLK("omap_hsmmc.2",	"ick",		&mmc2_ick,	CK_AM33XX),
- + 	CLK("omap_hsmmc.0",	"fck",		&mmc0_fck,	CK_AM33XX),
- + 	CLK("omap_hsmmc.1",	"fck",		&mmc1_fck,	CK_AM33XX),
- + 	CLK("omap_hsmmc.2",	"fck",		&mmc2_fck,	CK_AM33XX),
- + 	CLK(NULL,	"mmu_fck",		&mmu_fck,	CK_AM33XX),
- + 	CLK(NULL,	"ocmcram_ick",		&ocmcram_ick,	CK_AM33XX),
- + 	CLK(NULL,	"ocpwp_fck",		&ocpwp_fck,	CK_AM33XX),
- + 	CLK(NULL,	"pka_fck",		&pka_fck,	CK_AM33XX),
- + 	CLK(NULL,	"rng_fck",		&rng_fck,	CK_AM33XX),
- + 	CLK(NULL,	"rtc_fck",		&rtc_fck,	CK_AM33XX),
- + 	CLK(NULL,	"rtc_ick",		&rtc_ick,	CK_AM33XX),
- + 	CLK(NULL,	"sha0_fck",		&sha0_fck,	CK_AM33XX),
- + 	CLK(NULL,	"smartreflex0_fck",	&smartreflex0_fck,	CK_AM33XX),
- + 	CLK(NULL,	"smartreflex0_ick",	&smartreflex0_ick,	CK_AM33XX),
- + 	CLK(NULL,	"smartreflex1_fck",	&smartreflex1_fck,	CK_AM33XX),
- + 	CLK(NULL,	"smartreflex1_ick",	&smartreflex1_ick,	CK_AM33XX),
- + 	CLK("omap2_mcspi.1",	"fck",		&spi0_fck,	CK_AM33XX),
- + 	CLK("omap2_mcspi.2",	"fck",		&spi1_fck,	CK_AM33XX),
- + 	CLK("omap2_mcspi.1",	"ick",		&spi0_ick,	CK_AM33XX),
- + 	CLK("omap2_mcspi.2",	"ick",		&spi1_ick,	CK_AM33XX),
- + 	CLK(NULL,	"spinlock_fck",		&spinlock_fck,	CK_AM33XX),
- + 	CLK(NULL,	"gpt0_fck",		&timer0_fck,	CK_AM33XX),
- + 	CLK(NULL,	"gpt1_fck",		&timer1_fck,	CK_AM33XX),
- + 	CLK(NULL,	"gpt2_fck",		&timer2_fck,	CK_AM33XX),
- + 	CLK(NULL,	"gpt3_fck",		&timer3_fck,	CK_AM33XX),
- + 	CLK(NULL,	"gpt4_fck",		&timer4_fck,	CK_AM33XX),
- + 	CLK(NULL,	"gpt5_fck",		&timer5_fck,	CK_AM33XX),
- + 	CLK(NULL,	"gpt6_fck",		&timer6_fck,	CK_AM33XX),
- + 	CLK(NULL,	"gpt7_fck",		&timer7_fck,	CK_AM33XX),
- + 	CLK("da8xx_lcdc.0",	"lcdc_ick",	&lcdc_ick,	CK_AM33XX),
- + 	CLK(NULL,	"tpcc_ick",		&tpcc_ick,	CK_AM33XX),
- + 	CLK(NULL,	"tptc0_ick",		&tptc0_ick,	CK_AM33XX),
- + 	CLK(NULL,	"tptc1_ick",		&tptc1_ick,	CK_AM33XX),
- + 	CLK(NULL,	"tptc2_ick",		&tptc2_ick,	CK_AM33XX),
- + 	CLK(NULL,	"uart1_fck",		&uart1_fck,	CK_AM33XX),
- + 	CLK(NULL,	"uart2_fck",		&uart2_fck,	CK_AM33XX),
- + 	CLK(NULL,	"uart3_fck",		&uart3_fck,	CK_AM33XX),
- + 	CLK(NULL,	"uart4_fck",		&uart4_fck,	CK_AM33XX),
- + 	CLK(NULL,	"uart5_fck",		&uart5_fck,	CK_AM33XX),
- + 	CLK(NULL,	"uart6_fck",		&uart6_fck,	CK_AM33XX),
- + 	CLK(NULL,	"uart1_ick",		&uart1_ick,	CK_AM33XX),
- + 	CLK(NULL,	"uart2_ick",		&uart2_ick,	CK_AM33XX),
- + 	CLK(NULL,	"uart3_ick",		&uart3_ick,	CK_AM33XX),
- + 	CLK(NULL,	"uart4_ick",		&uart4_ick,	CK_AM33XX),
- + 	CLK(NULL,	"uart5_ick",		&uart5_ick,	CK_AM33XX),
- + 	CLK(NULL,	"uart6_ick",		&uart6_ick,	CK_AM33XX),
- + 	CLK(NULL,	"usbotg_ick",		&usbotg_ick,	CK_AM33XX),
- + 	CLK(NULL,	"usbotg_fck",		&usbotg_fck,	CK_AM33XX),
- + 	CLK(NULL,	"wdt0_ick",		&wdt0_ick,	CK_AM33XX),
- + 	CLK(NULL,	"wdt0_fck",		&wdt0_fck,	CK_AM33XX),
- + 	CLK(NULL,	"wdt1_ick",		&wdt1_ick,	CK_AM33XX),
- + 	CLK(NULL,	"wdt1_fck",		&wdt1_fck,	CK_AM33XX),
- + 	CLK(NULL,	"wkup_m3_fck",		&wkup_m3_fck,	CK_AM33XX),
- + 	CLK(NULL,	"l3_aon_gclk",		&l3_aon_gclk,		CK_AM33XX),
- + 	CLK(NULL,	"l4_wkup_aon_gclk",	&l4_wkup_aon_gclk,	CK_AM33XX),
- + 	CLK(NULL,	"l4_rtc_gclk",		&l4_rtc_gclk,		CK_AM33XX),
- + 	CLK(NULL,	"l3_gclk",		&l3_gclk,		CK_AM33XX),
- + 	CLK(NULL,	"gfx_l3_gclk",		&gfx_l3_gclk,		CK_AM33XX),
- + 	CLK(NULL,	"l4_wkup_gclk",		&l4_wkup_gclk,		CK_AM33XX),
- + 	CLK(NULL,	"l4hs_gclk",		&l4hs_gclk,		CK_AM33XX),
- + 	CLK(NULL,	"l3s_gclk",		&l3s_gclk,		CK_AM33XX),
- + 	CLK(NULL,	"l4fw_gclk",		&l4fw_gclk,		CK_AM33XX),
- + 	CLK(NULL,	"l4ls_gclk",		&l4ls_gclk,		CK_AM33XX),
- + 	CLK(NULL,	"debug_clka_gclk",	&debug_clka_gclk,	CK_AM33XX),
- + 	CLK(NULL,	"clk_24mhz",		&clk_24mhz,		CK_AM33XX),
- + 	CLK(NULL,	"sysclk_div_ck",	&sysclk_div_ck,		CK_AM33XX),
- + 	CLK(NULL,	"cpsw_250mhz_clk",	&cpsw_250mhz_clk,	CK_AM33XX),
- + 	CLK(NULL,	"cpsw_125mhz_gclk",	&cpsw_125mhz_gclk,	CK_AM33XX),
- + 	CLK(NULL,	"cpsw_50mhz_clk",	&cpsw_50mhz_clk,	CK_AM33XX),
- + 	CLK(NULL,	"cpsw_5mhz_clk",	&cpsw_5mhz_clk,		CK_AM33XX),
- + 	CLK(NULL,	"cpsw_cpts_rft_clk",	&cpsw_cpts_rft_clk,	CK_AM33XX),
- + 	CLK(NULL,	"gpio0_dbclk_mux_ck",	&gpio0_dbclk_mux_ck,	CK_AM33XX),
- + 	CLK(NULL,	"gpio0_dbclk",		&gpio0_dbclk,		CK_AM33XX),
- + 	CLK(NULL,	"gpio1_dbclk",		&gpio1_dbclk,		CK_AM33XX),
- + 	CLK(NULL,	"gpio2_dbclk",		&gpio2_dbclk,		CK_AM33XX),
- + 	CLK(NULL,	"gpio3_dbclk",		&gpio3_dbclk,		CK_AM33XX),
- + 	CLK(NULL,	"lcd_gclk",		&lcd_gclk,		CK_AM33XX),
- + 	CLK(NULL,	"mmc_clk",		&mmc_clk,		CK_AM33XX),
- + 	CLK(NULL,	"gfx_fclk_clksel_ck",	&gfx_fclk_clksel_ck,	CK_AM33XX),
- + 	CLK(NULL,	"gfx_fclk",		&gfx_fclk,		CK_AM33XX),
- + 	CLK(NULL,	"gfx_ick",		&gfx_ick,		CK_AM33XX),
- + 	CLK(NULL,	"sysclkout_pre_ck",	&sysclkout_pre_ck,	CK_AM33XX),
- + 	CLK(NULL,	"clkout2_ck",		&clkout2_ck,		CK_AM33XX),
- + 	CLK(NULL,	"gpt0_ick",		&timer0_ick,		CK_AM33XX),
- + 	CLK(NULL,	"gpt1_ick",		&timer1_ick,		CK_AM33XX),
- + 	CLK(NULL,	"gpt2_ick",		&timer2_ick,		CK_AM33XX),
- + 	CLK(NULL,	"gpt3_ick",		&timer3_ick,		CK_AM33XX),
- + 	CLK(NULL,	"gpt4_ick",		&timer4_ick,		CK_AM33XX),
- + 	CLK(NULL,	"gpt5_ick",		&timer5_ick,		CK_AM33XX),
- + 	CLK(NULL,	"gpt6_ick",		&timer6_ick,		CK_AM33XX),
- + 	CLK(NULL,	"gpt7_ick",		&timer7_ick,		CK_AM33XX),
- + 	CLK(NULL,	"vtp_clk",		&vtp_clk,		CK_AM33XX),
- + 	CLK(NULL,	"ehrpwm0_tbclk",	&ehrpwm0_tbclk,	CK_AM33XX),
- + 	CLK(NULL,	"ehrpwm1_tbclk",	&ehrpwm1_tbclk,	CK_AM33XX),
- + 	CLK(NULL,	"ehrpwm2_tbclk",	&ehrpwm2_tbclk,	CK_AM33XX),
- + };
- + 
- + int __init am33xx_clk_init(void)
- + {
- + 	struct omap_clk *c;
- + 	u32 cpu_clkflg;
- + 
- + 	cpu_mask = RATE_IN_AM33XX;
- + 	cpu_clkflg = CK_AM33XX;
- + 	
- + 	clk_init(&omap2_clk_functions);
- + 
- + 	for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++)
- + 		clk_preinit(c->lk.clk);
- + 
- + 	for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++)
- + 		if (c->cpu & cpu_clkflg) {
- + 			clkdev_add(&c->lk);
- + 			clk_register(c->lk.clk);
- + 			omap2_init_clk_clkdm(c->lk.clk);
- + 		}
- + 
- + 	recalculate_root_clocks();
- + 
- + 	/*
- + 	 * Only enable those clocks we will need, let the drivers
- + 	 * enable other clocks as necessary
- + 	 */
- + 	clk_enable_init_clocks();
- + 
- + 	return 0;
- + }
- + 
- + 
- + 
- + /* Common clock code */
- + 
- + /*
- +  * Switch the MPU rate if specified on cmdline.  We cannot do this
- +  * early until cmdline is parsed.  XXX This should be removed from the
- +  * clock code and handled by the OPP layer code in the near future.
- +  */
- + static int __init omap3xxx_clk_arch_init(void)
- + {
- + 	int ret;
- + 
- + 	ret = omap2_clk_switch_mpurate_at_boot("dpll1_ck");
- + 	if (!ret)
- + 		omap2_clk_print_new_rates("osc_sys_ck", "core_ck", "arm_fck");
- + 
- + 	return ret;
- + }
- + 
- + arch_initcall(omap3xxx_clk_arch_init);
- + 
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/clock33xx.h linux-3.2.1/arch/arm/mach-ckb_3352/clock33xx.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/clock33xx.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/clock33xx.h	2014-05-15 13:25:13.867221735 +0900
- ***************
- *** 0 ****
- --- 1,42 ----
- + /*
- +  * AM33XX clock function prototypes and macros.
- +  *
- +  * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK33XX_H
- + #define __ARCH_ARM_MACH_OMAP2_CLOCK33XX_H
- + 
- + #define AM33XX_MAX_DPLL_MULT  2047
- + #define AM33XX_MAX_DPLL_DIV   128
- + 
- + 
- + int am33xx_clk_init(void);
- + 
- + /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
- +      physically present, in such a case HWMOD enabling of
- +      clock would be failure with default parent. And timer
- +      probe thinks clock is already enabled, this leads to
- +      crash upon accessing timer 3 & 6 registers in probe.
- +      Fix by setting parent of both these timers to master
- +      oscillator clock.
- +    WDT1: On reset, RC Osc 32K clock is sourced to WDT1 module,
- +      which is non-accurate clock-source and results into inaccuracy
- +      with timer ticking.
- +      The solution is to switch the input functional clock-source to
- +      per_32k clock.
- +  */
- + static inline void am33xx_init_timer_parent(struct clk *clk)
- + {
- + 	omap2_clksel_set_parent(clk, clk->parent);
- + }
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/clock.c linux-3.2.1/arch/arm/mach-ckb_3352/clock.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/clock.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/clock.c	2014-05-15 13:25:13.871407170 +0900
- ***************
- *** 0 ****
- --- 1,492 ----
- + /*
- +  *  linux/arch/arm/mach-omap2/clock.c
- +  *
- +  *  Copyright (C) 2005-2008 Texas Instruments, Inc.
- +  *  Copyright (C) 2004-2010 Nokia Corporation
- +  *
- +  *  Contacts:
- +  *  Richard Woodruff <r-woodruff2@ti.com>
- +  *  Paul Walmsley
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + #undef DEBUG
- + 
- + #include <linux/kernel.h>
- + #include <linux/list.h>
- + #include <linux/errno.h>
- + #include <linux/err.h>
- + #include <linux/delay.h>
- + #include <linux/clk.h>
- + #include <linux/io.h>
- + #include <linux/bitops.h>
- + #include <trace/events/power.h>
- + 
- + #include <asm/cpu.h>
- + #include <plat/clock.h>
- + #include "clockdomain.h"
- + #include <plat/cpu.h>
- + #include <plat/prcm.h>
- + 
- + #include "clock.h"
- + #include "cm2xxx_3xxx.h"
- + #include "cm-regbits-34xx.h"
- + 
- + u16 cpu_mask;
- + 
- + /*
- +  * clkdm_control: if true, then when a clock is enabled in the
- +  * hardware, its clockdomain will first be enabled; and when a clock
- +  * is disabled in the hardware, its clockdomain will be disabled
- +  * afterwards.
- +  */
- + static bool clkdm_control = true;
- + 
- + /*
- +  * OMAP2+ specific clock functions
- +  */
- + 
- + /* Private functions */
- + 
- + /**
- +  * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE
- +  * @clk: struct clk * belonging to the module
- +  *
- +  * If the necessary clocks for the OMAP hardware IP block that
- +  * corresponds to clock @clk are enabled, then wait for the module to
- +  * indicate readiness (i.e., to leave IDLE).  This code does not
- +  * belong in the clock code and will be moved in the medium term to
- +  * module-dependent code.  No return value.
- +  */
- + static void _omap2_module_wait_ready(struct clk *clk)
- + {
- + 	void __iomem *companion_reg, *idlest_reg;
- + 	u8 other_bit, idlest_bit, idlest_val;
- + 
- + 	/* Not all modules have multiple clocks that their IDLEST depends on */
- + 	if (clk->ops->find_companion) {
- + 		clk->ops->find_companion(clk, &companion_reg, &other_bit);
- + 		if (!(__raw_readl(companion_reg) & (1 << other_bit)))
- + 			return;
- + 	}
- + 
- + 	clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val);
- + 
- + 	omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), idlest_val,
- + 			     clk->name);
- + }
- + 
- + /* Public functions */
- + 
- + /**
- +  * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
- +  * @clk: OMAP clock struct ptr to use
- +  *
- +  * Convert a clockdomain name stored in a struct clk 'clk' into a
- +  * clockdomain pointer, and save it into the struct clk.  Intended to be
- +  * called during clk_register().  No return value.
- +  */
- + void omap2_init_clk_clkdm(struct clk *clk)
- + {
- + 	struct clockdomain *clkdm;
- + 
- + 	if (!clk->clkdm_name)
- + 		return;
- + 
- + 	clkdm = clkdm_lookup(clk->clkdm_name);
- + 	if (clkdm) {
- + 		pr_debug("clock: associated clk %s to clkdm %s\n",
- + 			 clk->name, clk->clkdm_name);
- + 		clk->clkdm = clkdm;
- + 	} else {
- + 		pr_debug("clock: could not associate clk %s to "
- + 			 "clkdm %s\n", clk->name, clk->clkdm_name);
- + 	}
- + }
- + 
- + /**
- +  * omap2_clk_disable_clkdm_control - disable clkdm control on clk enable/disable
- +  *
- +  * Prevent the OMAP clock code from calling into the clockdomain code
- +  * when a hardware clock in that clockdomain is enabled or disabled.
- +  * Intended to be called at init time from omap*_clk_init().  No
- +  * return value.
- +  */
- + void __init omap2_clk_disable_clkdm_control(void)
- + {
- + 	clkdm_control = false;
- + }
- + 
- + /**
- +  * omap2_clk_dflt_find_companion - find companion clock to @clk
- +  * @clk: struct clk * to find the companion clock of
- +  * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in
- +  * @other_bit: u8 ** to return the companion clock bit shift in
- +  *
- +  * Note: We don't need special code here for INVERT_ENABLE for the
- +  * time being since INVERT_ENABLE only applies to clocks enabled by
- +  * CM_CLKEN_PLL
- +  *
- +  * Convert CM_ICLKEN* <-> CM_FCLKEN*.  This conversion assumes it's
- +  * just a matter of XORing the bits.
- +  *
- +  * Some clocks don't have companion clocks.  For example, modules with
- +  * only an interface clock (such as MAILBOXES) don't have a companion
- +  * clock.  Right now, this code relies on the hardware exporting a bit
- +  * in the correct companion register that indicates that the
- +  * nonexistent 'companion clock' is active.  Future patches will
- +  * associate this type of code with per-module data structures to
- +  * avoid this issue, and remove the casts.  No return value.
- +  */
- + void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
- + 				   u8 *other_bit)
- + {
- + 	u32 r;
- + 
- + 	/*
- + 	 * Convert CM_ICLKEN* <-> CM_FCLKEN*.  This conversion assumes
- + 	 * it's just a matter of XORing the bits.
- + 	 */
- + 	r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN));
- + 
- + 	*other_reg = (__force void __iomem *)r;
- + 	*other_bit = clk->enable_bit;
- + }
- + 
- + int omap2_dflt_clk_enable(struct clk *clk)
- + {
- + 	u32 v;
- + 
- + 	if (unlikely(clk->enable_reg == NULL)) {
- + 		pr_err("clock.c: Enable for %s without enable code\n",
- + 		       clk->name);
- + 		return 0; /* REVISIT: -EINVAL */
- + 	}
- + 
- + 	v = __raw_readl(clk->enable_reg);
- + 	if (clk->flags & INVERT_ENABLE)
- + 		v &= ~(1 << clk->enable_bit);
- + 	else
- + 		v |= (1 << clk->enable_bit);
- + 	__raw_writel(v, clk->enable_reg);
- + 	v = __raw_readl(clk->enable_reg); /* OCP barrier */
- + 
- + 	if (clk->ops->find_idlest)
- + 		_omap2_module_wait_ready(clk);
- + 
- + 	return 0;
- + }
- + 
- + void omap2_dflt_clk_disable(struct clk *clk)
- + {
- + 	u32 v;
- + 
- + 	if (!clk->enable_reg) {
- + 		/*
- + 		 * 'Independent' here refers to a clock which is not
- + 		 * controlled by its parent.
- + 		 */
- + 		printk(KERN_ERR "clock: clk_disable called on independent "
- + 		       "clock %s which has no enable_reg\n", clk->name);
- + 		return;
- + 	}
- + 
- + 	v = __raw_readl(clk->enable_reg);
- + 	if (clk->flags & INVERT_ENABLE)
- + 		v |= (1 << clk->enable_bit);
- + 	else
- + 		v &= ~(1 << clk->enable_bit);
- + 	__raw_writel(v, clk->enable_reg);
- + 	/* No OCP barrier needed here since it is a disable operation */
- + }
- + 
- + const struct clkops clkops_omap2_dflt = {
- + 	.enable		= omap2_dflt_clk_enable,
- + 	.disable	= omap2_dflt_clk_disable,
- + };
- + 
- + /**
- +  * omap2_clk_disable - disable a clock, if the system is not using it
- +  * @clk: struct clk * to disable
- +  *
- +  * Decrements the usecount on struct clk @clk.  If there are no users
- +  * left, call the clkops-specific clock disable function to disable it
- +  * in hardware.  If the clock is part of a clockdomain (which they all
- +  * should be), request that the clockdomain be disabled.  (It too has
- +  * a usecount, and so will not be disabled in the hardware until it no
- +  * longer has any users.)  If the clock has a parent clock (most of
- +  * them do), then call ourselves, recursing on the parent clock.  This
- +  * can cause an entire branch of the clock tree to be powered off by
- +  * simply disabling one clock.  Intended to be called with the clockfw_lock
- +  * spinlock held.  No return value.
- +  */
- + void omap2_clk_disable(struct clk *clk)
- + {
- + 	if (clk->usecount == 0) {
- + 		WARN(1, "clock: %s: omap2_clk_disable() called, but usecount "
- + 		     "already 0?", clk->name);
- + 		return;
- + 	}
- + 
- + 	pr_debug("clock: %s: decrementing usecount\n", clk->name);
- + 
- + 	clk->usecount--;
- + 
- + 	if (clk->usecount > 0)
- + 		return;
- + 
- + 	pr_debug("clock: %s: disabling in hardware\n", clk->name);
- + 
- + 	if (clk->ops && clk->ops->disable) {
- + 		trace_clock_disable(clk->name, 0, smp_processor_id());
- + 		clk->ops->disable(clk);
- + 	}
- + 
- + 	if (clkdm_control && clk->clkdm)
- + 		clkdm_clk_disable(clk->clkdm, clk);
- + 
- + 	if (clk->parent)
- + 		omap2_clk_disable(clk->parent);
- + }
- + 
- + /**
- +  * omap2_clk_enable - request that the system enable a clock
- +  * @clk: struct clk * to enable
- +  *
- +  * Increments the usecount on struct clk @clk.  If there were no users
- +  * previously, then recurse up the clock tree, enabling all of the
- +  * clock's parents and all of the parent clockdomains, and finally,
- +  * enabling @clk's clockdomain, and @clk itself.  Intended to be
- +  * called with the clockfw_lock spinlock held.  Returns 0 upon success
- +  * or a negative error code upon failure.
- +  */
- + int omap2_clk_enable(struct clk *clk)
- + {
- + 	int ret;
- + 
- + 	pr_debug("clock: %s: incrementing usecount\n", clk->name);
- + 
- + 	clk->usecount++;
- + 
- + 	if (clk->usecount > 1)
- + 		return 0;
- + 
- + 	pr_debug("clock: %s: enabling in hardware\n", clk->name);
- + 
- + 	if (clk->parent) {
- + 		ret = omap2_clk_enable(clk->parent);
- + 		if (ret) {
- + 			WARN(1, "clock: %s: could not enable parent %s: %d\n",
- + 			     clk->name, clk->parent->name, ret);
- + 			goto oce_err1;
- + 		}
- + 	}
- + 
- + 	if (clkdm_control && clk->clkdm) {
- + 		ret = clkdm_clk_enable(clk->clkdm, clk);
- + 		if (ret) {
- + 			WARN(1, "clock: %s: could not enable clockdomain %s: "
- + 			     "%d\n", clk->name, clk->clkdm->name, ret);
- + 			goto oce_err2;
- + 		}
- + 	}
- + 
- + 	if (clk->ops && clk->ops->enable) {
- + 		trace_clock_enable(clk->name, 1, smp_processor_id());
- + 		ret = clk->ops->enable(clk);
- + 		if (ret) {
- + 			WARN(1, "clock: %s: could not enable: %d\n",
- + 			     clk->name, ret);
- + 			goto oce_err3;
- + 		}
- + 	}
- + 
- + 	return 0;
- + 
- + oce_err3:
- + 	if (clkdm_control && clk->clkdm)
- + 		clkdm_clk_disable(clk->clkdm, clk);
- + oce_err2:
- + 	if (clk->parent)
- + 		omap2_clk_disable(clk->parent);
- + oce_err1:
- + 	clk->usecount--;
- + 
- + 	return ret;
- + }
- + 
- + /* Given a clock and a rate apply a clock specific rounding function */
- + long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
- + {
- + 	if (clk->round_rate)
- + 		return clk->round_rate(clk, rate);
- + 
- + 	return clk->rate;
- + }
- + 
- + /* Set the clock rate for a clock source */
- + int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
- + {
- + 	int ret = -EINVAL;
- + 
- + 	pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
- + 
- + 	/* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
- + 	if (clk->set_rate) {
- + 		trace_clock_set_rate(clk->name, rate, smp_processor_id());
- + 		ret = clk->set_rate(clk, rate);
- + 	}
- + 
- + 	return ret;
- + }
- + 
- + int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
- + {
- + 	if (!clk->clksel)
- + 		return -EINVAL;
- + 
- + 	if (clk->parent == new_parent)
- + 		return 0;
- + 
- + 	return omap2_clksel_set_parent(clk, new_parent);
- + }
- + 
- + /* OMAP3/4 non-CORE DPLL clkops */
- + 
- + const struct clkops clkops_omap3_noncore_dpll_ops = {
- + 	.enable		= omap3_noncore_dpll_enable,
- + 	.disable	= omap3_noncore_dpll_disable,
- + 	.allow_idle	= omap3_dpll_allow_idle,
- + 	.deny_idle	= omap3_dpll_deny_idle,
- + };
- + 
- + const struct clkops clkops_omap3_core_dpll_ops = {
- + 	.allow_idle	= omap3_dpll_allow_idle,
- + 	.deny_idle	= omap3_dpll_deny_idle,
- + };
- + 
- + /*
- +  * OMAP2+ clock reset and init functions
- +  */
- + 
- + #ifdef CONFIG_OMAP_RESET_CLOCKS
- + void omap2_clk_disable_unused(struct clk *clk)
- + {
- + 	u32 regval32, v;
- + 
- + 	v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
- + 
- + 	regval32 = __raw_readl(clk->enable_reg);
- + 	if ((regval32 & (1 << clk->enable_bit)) == v)
- + 		return;
- + 
- + 	pr_debug("Disabling unused clock \"%s\"\n", clk->name);
- + 	clk->ops->disable(clk);
- + 	
- + 	if (clk->clkdm != NULL)
- + 		pwrdm_clkdm_state_switch(clk->clkdm);
- + }
- + #endif
- + 
- + /**
- +  * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument
- +  * @mpurate_ck_name: clk name of the clock to change rate
- +  *
- +  * Change the ARM MPU clock rate to the rate specified on the command
- +  * line, if one was specified.  @mpurate_ck_name should be
- +  * "virt_prcm_set" on OMAP2xxx and "dpll1_ck" on OMAP34xx/OMAP36xx.
- +  * XXX Does not handle voltage scaling - on OMAP2xxx this is currently
- +  * handled by the virt_prcm_set clock, but this should be handled by
- +  * the OPP layer.  XXX This is intended to be handled by the OPP layer
- +  * code in the near future and should be removed from the clock code.
- +  * Returns -EINVAL if 'mpurate' is zero or if clk_set_rate() rejects
- +  * the rate, -ENOENT if the struct clk referred to by @mpurate_ck_name
- +  * cannot be found, or 0 upon success.
- +  */
- + int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name)
- + {
- + 	struct clk *mpurate_ck;
- + 	int r;
- + 
- + 	if (!mpurate)
- + 		return -EINVAL;
- + 
- + 	mpurate_ck = clk_get(NULL, mpurate_ck_name);
- + 	if (WARN(IS_ERR(mpurate_ck), "Failed to get %s.\n", mpurate_ck_name))
- + 		return -ENOENT;
- + 
- + 	r = clk_set_rate(mpurate_ck, mpurate);
- + 	if (IS_ERR_VALUE(r)) {
- + 		WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n",
- + 		     mpurate_ck->name, mpurate, r);
- + 		clk_put(mpurate_ck);
- + 		return -EINVAL;
- + 	}
- + 
- + 	calibrate_delay();
- + 	recalculate_root_clocks();
- + 
- + 	clk_put(mpurate_ck);
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * omap2_clk_print_new_rates - print summary of current clock tree rates
- +  * @hfclkin_ck_name: clk name for the off-chip HF oscillator
- +  * @core_ck_name: clk name for the on-chip CORE_CLK
- +  * @mpu_ck_name: clk name for the ARM MPU clock
- +  *
- +  * Prints a short message to the console with the HFCLKIN oscillator
- +  * rate, the rate of the CORE clock, and the rate of the ARM MPU clock.
- +  * Called by the boot-time MPU rate switching code.   XXX This is intended
- +  * to be handled by the OPP layer code in the near future and should be
- +  * removed from the clock code.  No return value.
- +  */
- + void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name,
- + 				      const char *core_ck_name,
- + 				      const char *mpu_ck_name)
- + {
- + 	struct clk *hfclkin_ck, *core_ck, *mpu_ck;
- + 	unsigned long hfclkin_rate;
- + 
- + 	mpu_ck = clk_get(NULL, mpu_ck_name);
- + 	if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name))
- + 		return;
- + 
- + 	core_ck = clk_get(NULL, core_ck_name);
- + 	if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name))
- + 		return;
- + 
- + 	hfclkin_ck = clk_get(NULL, hfclkin_ck_name);
- + 	if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name))
- + 		return;
- + 
- + 	hfclkin_rate = clk_get_rate(hfclkin_ck);
- + 
- + 	pr_info("Switched to new clocking rate (Crystal/Core/MPU): "
- + 		"%ld.%01ld/%ld/%ld MHz\n",
- + 		(hfclkin_rate / 1000000),
- + 		((hfclkin_rate / 100000) % 10),
- + 		(clk_get_rate(core_ck) / 1000000),
- + 		(clk_get_rate(mpu_ck) / 1000000));
- + }
- + 
- + /* Common data */
- + 
- + struct clk_functions omap2_clk_functions = {
- + 	.clk_enable		= omap2_clk_enable,
- + 	.clk_disable		= omap2_clk_disable,
- + 	.clk_round_rate		= omap2_clk_round_rate,
- + 	.clk_set_rate		= omap2_clk_set_rate,
- + 	.clk_set_parent		= omap2_clk_set_parent,
- + 	.clk_disable_unused	= omap2_clk_disable_unused,
- + #ifdef CONFIG_CPU_FREQ
- + 	/* These will be removed when the OPP code is integrated */
- + 	.clk_init_cpufreq_table	= omap2_clk_init_cpufreq_table,
- + 	.clk_exit_cpufreq_table	= omap2_clk_exit_cpufreq_table,
- + #endif
- + };
- + 
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/clock_common_data.c linux-3.2.1/arch/arm/mach-ckb_3352/clock_common_data.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/clock_common_data.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/clock_common_data.c	2014-05-15 13:25:13.871407170 +0900
- ***************
- *** 0 ****
- --- 1,45 ----
- + /*
- +  *  linux/arch/arm/mach-omap2/clock_common_data.c
- +  *
- +  *  Copyright (C) 2005-2009 Texas Instruments, Inc.
- +  *  Copyright (C) 2004-2009 Nokia Corporation
- +  *
- +  *  Contacts:
- +  *  Richard Woodruff <r-woodruff2@ti.com>
- +  *  Paul Walmsley
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  *
- +  * This file contains clock data that is common to both the OMAP2xxx and
- +  * OMAP3xxx clock definition files.
- +  */
- + 
- + #include "clock.h"
- + 
- + /* clksel_rate data common to 24xx/343x */
- + const struct clksel_rate gpt_32k_rates[] = {
- + 	 { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_3XXX },
- + 	 { .div = 0 }
- + };
- + 
- + const struct clksel_rate gpt_sys_rates[] = {
- + 	 { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_3XXX },
- + 	 { .div = 0 }
- + };
- + 
- + const struct clksel_rate gfx_l3_rates[] = {
- + 	{ .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_3XXX },
- + 	{ .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_3XXX },
- + 	{ .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_3XXX },
- + 	{ .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_3XXX },
- + 	{ .div = 0 }
- + };
- + 
- + const struct clksel_rate dsp_ick_rates[] = {
- + 	{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
- + 	{ .div = 2, .val = 2, .flags = RATE_IN_24XX },
- + 	{ .div = 3, .val = 3, .flags = RATE_IN_243X },
- + 	{ .div = 0 },
- + };
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/clockdomain44xx.c linux-3.2.1/arch/arm/mach-ckb_3352/clockdomain44xx.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/clockdomain44xx.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/clockdomain44xx.c	2014-05-15 13:25:13.871407170 +0900
- ***************
- *** 0 ****
- --- 1,61 ----
- + /*
- +  * OMAP4 clockdomain control
- +  *
- +  * Copyright (C) 2008-2010 Texas Instruments, Inc.
- +  * Copyright (C) 2008-2010 Nokia Corporation
- +  *
- +  * Derived from mach-omap2/clockdomain.c written by Paul Walmsley
- +  * Rajendra Nayak <rnayak@ti.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #include <linux/kernel.h>
- + #include "clockdomain.h"
- + #include "cminst44xx.h"
- + #include "cm44xx.h"
- + 
- + static int omap4_clkdm_sleep(struct clockdomain *clkdm)
- + {
- + 	omap4_cminst_clkdm_force_sleep(clkdm->prcm_partition,
- + 					clkdm->cm_inst, clkdm->clkdm_offs);
- + 	return 0;
- + }
- + 
- + static int omap4_clkdm_wakeup(struct clockdomain *clkdm)
- + {
- + 	omap4_cminst_clkdm_force_wakeup(clkdm->prcm_partition,
- + 					clkdm->cm_inst, clkdm->clkdm_offs);
- + 	return 0;
- + }
- + 
- + 
- + static int omap4_clkdm_clk_enable(struct clockdomain *clkdm)
- + {
- + 	if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
- + 		return omap4_clkdm_wakeup(clkdm);
- + 
- + 	return 0;
- + }
- + 
- + static int omap4_clkdm_clk_disable(struct clockdomain *clkdm)
- + {
- + 	bool hwsup = false;
- + 
- + 	hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
- + 					clkdm->cm_inst, clkdm->clkdm_offs);
- + 
- + 	if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP))
- + 		omap4_clkdm_sleep(clkdm);
- + 
- + 	return 0;
- + }
- + 
- + struct clkdm_ops am33xx_clkdm_operations = {
- + 	.clkdm_sleep		= omap4_clkdm_sleep,
- + 	.clkdm_wakeup		= omap4_clkdm_wakeup,
- + 	.clkdm_clk_enable	= omap4_clkdm_clk_enable,
- + 	.clkdm_clk_disable	= omap4_clkdm_clk_disable,
- + };
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/clockdomain.c linux-3.2.1/arch/arm/mach-ckb_3352/clockdomain.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/clockdomain.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/clockdomain.c	2014-05-15 13:25:13.874974076 +0900
- ***************
- *** 0 ****
- --- 1,1012 ----
- + /*
- +  * OMAP2/3/4 clockdomain framework functions
- +  *
- +  * Copyright (C) 2008-2011 Texas Instruments, Inc.
- +  * Copyright (C) 2008-2011 Nokia Corporation
- +  *
- +  * Written by Paul Walmsley and Jouni Högander
- +  * Added OMAP4 specific support by Abhijit Pagare <abhijitpagare@ti.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + #undef DEBUG
- + 
- + #include <linux/kernel.h>
- + #include <linux/device.h>
- + #include <linux/list.h>
- + #include <linux/errno.h>
- + #include <linux/string.h>
- + #include <linux/delay.h>
- + #include <linux/clk.h>
- + #include <linux/limits.h>
- + #include <linux/err.h>
- + 
- + #include <linux/io.h>
- + 
- + #include <linux/bitops.h>
- + 
- + #include <plat/clock.h>
- + #include "clockdomain.h"
- + 
- + /* clkdm_list contains all registered struct clockdomains */
- + static LIST_HEAD(clkdm_list);
- + 
- + /* array of clockdomain deps to be added/removed when clkdm in hwsup mode */
- + static struct clkdm_autodep *autodeps;
- + 
- + static struct clkdm_ops *arch_clkdm;
- + 
- + /* Private functions */
- + 
- + static struct clockdomain *_clkdm_lookup(const char *name)
- + {
- + 	struct clockdomain *clkdm, *temp_clkdm;
- + 
- + 	if (!name)
- + 		return NULL;
- + 
- + 	clkdm = NULL;
- + 
- + 	list_for_each_entry(temp_clkdm, &clkdm_list, node) {
- + 		if (!strcmp(name, temp_clkdm->name)) {
- + 			clkdm = temp_clkdm;
- + 			break;
- + 		}
- + 	}
- + 
- + 	return clkdm;
- + }
- + 
- + /**
- +  * _clkdm_register - register a clockdomain
- +  * @clkdm: struct clockdomain * to register
- +  *
- +  * Adds a clockdomain to the internal clockdomain list.
- +  * Returns -EINVAL if given a null pointer, -EEXIST if a clockdomain is
- +  * already registered by the provided name, or 0 upon success.
- +  */
- + static int _clkdm_register(struct clockdomain *clkdm)
- + {
- + 	struct powerdomain *pwrdm;
- + 
- + 	if (!clkdm || !clkdm->name)
- + 		return -EINVAL;
- + 
- + 	pwrdm = pwrdm_lookup(clkdm->pwrdm.name);
- + 	if (!pwrdm) {
- + 		pr_err("clockdomain: %s: powerdomain %s does not exist\n",
- + 			clkdm->name, clkdm->pwrdm.name);
- + 		return -EINVAL;
- + 	}
- + 	clkdm->pwrdm.ptr = pwrdm;
- + 
- + 	/* Verify that the clockdomain is not already registered */
- + 	if (_clkdm_lookup(clkdm->name))
- + 		return -EEXIST;
- + 
- + 	list_add(&clkdm->node, &clkdm_list);
- + 
- + 	pwrdm_add_clkdm(pwrdm, clkdm);
- + 
- + 	spin_lock_init(&clkdm->lock);
- + 
- + 	pr_debug("clockdomain: registered %s\n", clkdm->name);
- + 
- + 	return 0;
- + }
- + 
- + /* _clkdm_deps_lookup - look up the specified clockdomain in a clkdm list */
- + static struct clkdm_dep *_clkdm_deps_lookup(struct clockdomain *clkdm,
- + 					    struct clkdm_dep *deps)
- + {
- + 	struct clkdm_dep *cd;
- + 
- + 	if (!clkdm || !deps)
- + 		return ERR_PTR(-EINVAL);
- + 
- + 	for (cd = deps; cd->clkdm_name; cd++) {
- + 		if (!cd->clkdm && cd->clkdm_name)
- + 			cd->clkdm = _clkdm_lookup(cd->clkdm_name);
- + 
- + 		if (cd->clkdm == clkdm)
- + 			break;
- + 	}
- + 
- + 	if (!cd->clkdm_name)
- + 		return ERR_PTR(-ENOENT);
- + 
- + 	return cd;
- + }
- + 
- + /*
- +  * _autodep_lookup - resolve autodep clkdm names to clkdm pointers; store
- +  * @autodep: struct clkdm_autodep * to resolve
- +  *
- +  * Resolve autodep clockdomain names to clockdomain pointers via
- +  * clkdm_lookup() and store the pointers in the autodep structure.  An
- +  * "autodep" is a clockdomain sleep/wakeup dependency that is
- +  * automatically added and removed whenever clocks in the associated
- +  * clockdomain are enabled or disabled (respectively) when the
- +  * clockdomain is in hardware-supervised mode.	Meant to be called
- +  * once at clockdomain layer initialization, since these should remain
- +  * fixed for a particular architecture.  No return value.
- +  *
- +  * XXX autodeps are deprecated and should be removed at the earliest
- +  * opportunity
- +  */
- + static void _autodep_lookup(struct clkdm_autodep *autodep)
- + {
- + 	struct clockdomain *clkdm;
- + 
- + 	if (!autodep)
- + 		return;
- + 
- + 	clkdm = clkdm_lookup(autodep->clkdm.name);
- + 	if (!clkdm) {
- + 		pr_err("clockdomain: autodeps: clockdomain %s does not exist\n",
- + 			 autodep->clkdm.name);
- + 		clkdm = ERR_PTR(-ENOENT);
- + 	}
- + 	autodep->clkdm.ptr = clkdm;
- + }
- + 
- + /*
- +  * _clkdm_add_autodeps - add auto sleepdeps/wkdeps to clkdm upon clock enable
- +  * @clkdm: struct clockdomain *
- +  *
- +  * Add the "autodep" sleep & wakeup dependencies to clockdomain 'clkdm'
- +  * in hardware-supervised mode.  Meant to be called from clock framework
- +  * when a clock inside clockdomain 'clkdm' is enabled.	No return value.
- +  *
- +  * XXX autodeps are deprecated and should be removed at the earliest
- +  * opportunity
- +  */
- + void _clkdm_add_autodeps(struct clockdomain *clkdm)
- + {
- + 	struct clkdm_autodep *autodep;
- + 
- + 	if (!autodeps || clkdm->flags & CLKDM_NO_AUTODEPS)
- + 		return;
- + 
- + 	for (autodep = autodeps; autodep->clkdm.ptr; autodep++) {
- + 		if (IS_ERR(autodep->clkdm.ptr))
- + 			continue;
- + 
- + 		pr_debug("clockdomain: adding %s sleepdep/wkdep for "
- + 			 "clkdm %s\n", autodep->clkdm.ptr->name,
- + 			 clkdm->name);
- + 
- + 		clkdm_add_sleepdep(clkdm, autodep->clkdm.ptr);
- + 		clkdm_add_wkdep(clkdm, autodep->clkdm.ptr);
- + 	}
- + }
- + 
- + /*
- +  * _clkdm_add_autodeps - remove auto sleepdeps/wkdeps from clkdm
- +  * @clkdm: struct clockdomain *
- +  *
- +  * Remove the "autodep" sleep & wakeup dependencies from clockdomain 'clkdm'
- +  * in hardware-supervised mode.  Meant to be called from clock framework
- +  * when a clock inside clockdomain 'clkdm' is disabled.  No return value.
- +  *
- +  * XXX autodeps are deprecated and should be removed at the earliest
- +  * opportunity
- +  */
- + void _clkdm_del_autodeps(struct clockdomain *clkdm)
- + {
- + 	struct clkdm_autodep *autodep;
- + 
- + 	if (!autodeps || clkdm->flags & CLKDM_NO_AUTODEPS)
- + 		return;
- + 
- + 	for (autodep = autodeps; autodep->clkdm.ptr; autodep++) {
- + 		if (IS_ERR(autodep->clkdm.ptr))
- + 			continue;
- + 
- + 		pr_debug("clockdomain: removing %s sleepdep/wkdep for "
- + 			 "clkdm %s\n", autodep->clkdm.ptr->name,
- + 			 clkdm->name);
- + 
- + 		clkdm_del_sleepdep(clkdm, autodep->clkdm.ptr);
- + 		clkdm_del_wkdep(clkdm, autodep->clkdm.ptr);
- + 	}
- + }
- + 
- + /**
- +  * _resolve_clkdm_deps() - resolve clkdm_names in @clkdm_deps to clkdms
- +  * @clkdm: clockdomain that we are resolving dependencies for
- +  * @clkdm_deps: ptr to array of struct clkdm_deps to resolve
- +  *
- +  * Iterates through @clkdm_deps, looking up the struct clockdomain named by
- +  * clkdm_name and storing the clockdomain pointer in the struct clkdm_dep.
- +  * No return value.
- +  */
- + static void _resolve_clkdm_deps(struct clockdomain *clkdm,
- + 				struct clkdm_dep *clkdm_deps)
- + {
- + 	struct clkdm_dep *cd;
- + 
- + 	for (cd = clkdm_deps; cd && cd->clkdm_name; cd++) {
- + 		if (cd->clkdm)
- + 			continue;
- + 		cd->clkdm = _clkdm_lookup(cd->clkdm_name);
- + 
- + 		WARN(!cd->clkdm, "clockdomain: %s: could not find clkdm %s while resolving dependencies - should never happen",
- + 		     clkdm->name, cd->clkdm_name);
- + 	}
- + }
- + 
- + /* Public functions */
- + 
- + /**
- +  * clkdm_register_platform_funcs - register clockdomain implementation fns
- +  * @co: func pointers for arch specific implementations
- +  *
- +  * Register the list of function pointers used to implement the
- +  * clockdomain functions on different OMAP SoCs.  Should be called
- +  * before any other clkdm_register*() function.  Returns -EINVAL if
- +  * @co is null, -EEXIST if platform functions have already been
- +  * registered, or 0 upon success.
- +  */
- + int clkdm_register_platform_funcs(struct clkdm_ops *co)
- + {
- + 	if (!co)
- + 		return -EINVAL;
- + 
- + 	if (arch_clkdm)
- + 		return -EEXIST;
- + 
- + 	arch_clkdm = co;
- + 
- + 	return 0;
- + };
- + 
- + /**
- +  * clkdm_register_clkdms - register SoC clockdomains
- +  * @cs: pointer to an array of struct clockdomain to register
- +  *
- +  * Register the clockdomains available on a particular OMAP SoC.  Must
- +  * be called after clkdm_register_platform_funcs().  May be called
- +  * multiple times.  Returns -EACCES if called before
- +  * clkdm_register_platform_funcs(); -EINVAL if the argument @cs is
- +  * null; or 0 upon success.
- +  */
- + int clkdm_register_clkdms(struct clockdomain **cs)
- + {
- + 	struct clockdomain **c = NULL;
- + 
- + 	if (!arch_clkdm)
- + 		return -EACCES;
- + 
- + 	if (!cs)
- + 		return -EINVAL;
- + 
- + 	for (c = cs; *c; c++)
- + 		_clkdm_register(*c);
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * clkdm_register_autodeps - register autodeps (if required)
- +  * @ia: pointer to a static array of struct clkdm_autodep to register
- +  *
- +  * Register clockdomain "automatic dependencies."  These are
- +  * clockdomain wakeup and sleep dependencies that are automatically
- +  * added whenever the first clock inside a clockdomain is enabled, and
- +  * removed whenever the last clock inside a clockdomain is disabled.
- +  * These are currently only used on OMAP3 devices, and are deprecated,
- +  * since they waste energy.  However, until the OMAP2/3 IP block
- +  * enable/disable sequence can be converted to match the OMAP4
- +  * sequence, they are needed.
- +  *
- +  * Must be called only after all of the SoC clockdomains are
- +  * registered, since the function will resolve autodep clockdomain
- +  * names into clockdomain pointers.
- +  *
- +  * The struct clkdm_autodep @ia array must be static, as this function
- +  * does not copy the array elements.
- +  *
- +  * Returns -EACCES if called before any clockdomains have been
- +  * registered, -EINVAL if called with a null @ia argument, -EEXIST if
- +  * autodeps have already been registered, or 0 upon success.
- +  */
- + int clkdm_register_autodeps(struct clkdm_autodep *ia)
- + {
- + 	struct clkdm_autodep *a = NULL;
- + 
- + 	if (list_empty(&clkdm_list))
- + 		return -EACCES;
- + 
- + 	if (!ia)
- + 		return -EINVAL;
- + 
- + 	if (autodeps)
- + 		return -EEXIST;
- + 
- + 	autodeps = ia;
- + 	for (a = autodeps; a->clkdm.ptr; a++)
- + 		_autodep_lookup(a);
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * clkdm_complete_init - set up the clockdomain layer
- +  *
- +  * Put all clockdomains into software-supervised mode; PM code should
- +  * later enable hardware-supervised mode as appropriate.  Must be
- +  * called after clkdm_register_clkdms().  Returns -EACCES if called
- +  * before clkdm_register_clkdms(), or 0 upon success.
- +  */
- + int clkdm_complete_init(void)
- + {
- + 	struct clockdomain *clkdm;
- + 
- + 	if (list_empty(&clkdm_list))
- + 		return -EACCES;
- + 
- + 	list_for_each_entry(clkdm, &clkdm_list, node) {
- + 		if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
- + 			clkdm_wakeup(clkdm);
- + 		else if (clkdm->flags & CLKDM_CAN_DISABLE_AUTO)
- + 			clkdm_deny_idle(clkdm);
- + 
- + 		_resolve_clkdm_deps(clkdm, clkdm->wkdep_srcs);
- + 		clkdm_clear_all_wkdeps(clkdm);
- + 
- + 		_resolve_clkdm_deps(clkdm, clkdm->sleepdep_srcs);
- + 		clkdm_clear_all_sleepdeps(clkdm);
- + 	}
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * clkdm_lookup - look up a clockdomain by name, return a pointer
- +  * @name: name of clockdomain
- +  *
- +  * Find a registered clockdomain by its name @name.  Returns a pointer
- +  * to the struct clockdomain if found, or NULL otherwise.
- +  */
- + struct clockdomain *clkdm_lookup(const char *name)
- + {
- + 	struct clockdomain *clkdm, *temp_clkdm;
- + 
- + 	if (!name)
- + 		return NULL;
- + 
- + 	clkdm = NULL;
- + 
- + 	list_for_each_entry(temp_clkdm, &clkdm_list, node) {
- + 		if (!strcmp(name, temp_clkdm->name)) {
- + 			clkdm = temp_clkdm;
- + 			break;
- + 		}
- + 	}
- + 
- + 	return clkdm;
- + }
- + 
- + /**
- +  * clkdm_for_each - call function on each registered clockdomain
- +  * @fn: callback function *
- +  *
- +  * Call the supplied function @fn for each registered clockdomain.
- +  * The callback function @fn can return anything but 0 to bail
- +  * out early from the iterator.  The callback function is called with
- +  * the clkdm_mutex held, so no clockdomain structure manipulation
- +  * functions should be called from the callback, although hardware
- +  * clockdomain control functions are fine.  Returns the last return
- +  * value of the callback function, which should be 0 for success or
- +  * anything else to indicate failure; or -EINVAL if the function pointer
- +  * is null.
- +  */
- + int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user),
- + 			void *user)
- + {
- + 	struct clockdomain *clkdm;
- + 	int ret = 0;
- + 
- + 	if (!fn)
- + 		return -EINVAL;
- + 
- + 	list_for_each_entry(clkdm, &clkdm_list, node) {
- + 		ret = (*fn)(clkdm, user);
- + 		if (ret)
- + 			break;
- + 	}
- + 
- + 	return ret;
- + }
- + 
- + 
- + /**
- +  * clkdm_get_pwrdm - return a ptr to the pwrdm that this clkdm resides in
- +  * @clkdm: struct clockdomain *
- +  *
- +  * Return a pointer to the struct powerdomain that the specified clockdomain
- +  * @clkdm exists in, or returns NULL if @clkdm is NULL.
- +  */
- + struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm)
- + {
- + 	if (!clkdm)
- + 		return NULL;
- + 
- + 	return clkdm->pwrdm.ptr;
- + }
- + 
- + 
- + /* Hardware clockdomain control */
- + 
- + /**
- +  * clkdm_add_wkdep - add a wakeup dependency from clkdm2 to clkdm1
- +  * @clkdm1: wake this struct clockdomain * up (dependent)
- +  * @clkdm2: when this struct clockdomain * wakes up (source)
- +  *
- +  * When the clockdomain represented by @clkdm2 wakes up, wake up
- +  * @clkdm1. Implemented in hardware on the OMAP, this feature is
- +  * designed to reduce wakeup latency of the dependent clockdomain @clkdm1.
- +  * Returns -EINVAL if presented with invalid clockdomain pointers,
- +  * -ENOENT if @clkdm2 cannot wake up clkdm1 in hardware, or 0 upon
- +  * success.
- +  */
- + int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
- + {
- + 	struct clkdm_dep *cd;
- + 	int ret = 0;
- + 
- + 	if (!clkdm1 || !clkdm2)
- + 		return -EINVAL;
- + 
- + 	cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
- + 	if (IS_ERR(cd))
- + 		ret = PTR_ERR(cd);
- + 
- + 	if (!arch_clkdm || !arch_clkdm->clkdm_add_wkdep)
- + 		ret = -EINVAL;
- + 
- + 	if (ret) {
- + 		pr_debug("clockdomain: hardware cannot set/clear wake up of "
- + 			 "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
- + 		return ret;
- + 	}
- + 
- + 	if (atomic_inc_return(&cd->wkdep_usecount) == 1) {
- + 		pr_debug("clockdomain: hardware will wake up %s when %s wakes "
- + 			 "up\n", clkdm1->name, clkdm2->name);
- + 
- + 		ret = arch_clkdm->clkdm_add_wkdep(clkdm1, clkdm2);
- + 	}
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * clkdm_del_wkdep - remove a wakeup dependency from clkdm2 to clkdm1
- +  * @clkdm1: wake this struct clockdomain * up (dependent)
- +  * @clkdm2: when this struct clockdomain * wakes up (source)
- +  *
- +  * Remove a wakeup dependency causing @clkdm1 to wake up when @clkdm2
- +  * wakes up.  Returns -EINVAL if presented with invalid clockdomain
- +  * pointers, -ENOENT if @clkdm2 cannot wake up clkdm1 in hardware, or
- +  * 0 upon success.
- +  */
- + int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
- + {
- + 	struct clkdm_dep *cd;
- + 	int ret = 0;
- + 
- + 	if (!clkdm1 || !clkdm2)
- + 		return -EINVAL;
- + 
- + 	cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
- + 	if (IS_ERR(cd))
- + 		ret = PTR_ERR(cd);
- + 
- + 	if (!arch_clkdm || !arch_clkdm->clkdm_del_wkdep)
- + 		ret = -EINVAL;
- + 
- + 	if (ret) {
- + 		pr_debug("clockdomain: hardware cannot set/clear wake up of "
- + 			 "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
- + 		return ret;
- + 	}
- + 
- + 	if (atomic_dec_return(&cd->wkdep_usecount) == 0) {
- + 		pr_debug("clockdomain: hardware will no longer wake up %s "
- + 			 "after %s wakes up\n", clkdm1->name, clkdm2->name);
- + 
- + 		ret = arch_clkdm->clkdm_del_wkdep(clkdm1, clkdm2);
- + 	}
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * clkdm_read_wkdep - read wakeup dependency state from clkdm2 to clkdm1
- +  * @clkdm1: wake this struct clockdomain * up (dependent)
- +  * @clkdm2: when this struct clockdomain * wakes up (source)
- +  *
- +  * Return 1 if a hardware wakeup dependency exists wherein @clkdm1 will be
- +  * awoken when @clkdm2 wakes up; 0 if dependency is not set; -EINVAL
- +  * if either clockdomain pointer is invalid; or -ENOENT if the hardware
- +  * is incapable.
- +  *
- +  * REVISIT: Currently this function only represents software-controllable
- +  * wakeup dependencies.  Wakeup dependencies fixed in hardware are not
- +  * yet handled here.
- +  */
- + int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
- + {
- + 	struct clkdm_dep *cd;
- + 	int ret = 0;
- + 
- + 	if (!clkdm1 || !clkdm2)
- + 		return -EINVAL;
- + 
- + 	cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
- + 	if (IS_ERR(cd))
- + 		ret = PTR_ERR(cd);
- + 
- + 	if (!arch_clkdm || !arch_clkdm->clkdm_read_wkdep)
- + 		ret = -EINVAL;
- + 
- + 	if (ret) {
- + 		pr_debug("clockdomain: hardware cannot set/clear wake up of "
- + 			 "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
- + 		return ret;
- + 	}
- + 
- + 	/* XXX It's faster to return the atomic wkdep_usecount */
- + 	return arch_clkdm->clkdm_read_wkdep(clkdm1, clkdm2);
- + }
- + 
- + /**
- +  * clkdm_clear_all_wkdeps - remove all wakeup dependencies from target clkdm
- +  * @clkdm: struct clockdomain * to remove all wakeup dependencies from
- +  *
- +  * Remove all inter-clockdomain wakeup dependencies that could cause
- +  * @clkdm to wake.  Intended to be used during boot to initialize the
- +  * PRCM to a known state, after all clockdomains are put into swsup idle
- +  * and woken up.  Returns -EINVAL if @clkdm pointer is invalid, or
- +  * 0 upon success.
- +  */
- + int clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
- + {
- + 	if (!clkdm)
- + 		return -EINVAL;
- + 
- + 	if (!arch_clkdm || !arch_clkdm->clkdm_clear_all_wkdeps)
- + 		return -EINVAL;
- + 
- + 	return arch_clkdm->clkdm_clear_all_wkdeps(clkdm);
- + }
- + 
- + /**
- +  * clkdm_add_sleepdep - add a sleep dependency from clkdm2 to clkdm1
- +  * @clkdm1: prevent this struct clockdomain * from sleeping (dependent)
- +  * @clkdm2: when this struct clockdomain * is active (source)
- +  *
- +  * Prevent @clkdm1 from automatically going inactive (and then to
- +  * retention or off) if @clkdm2 is active.  Returns -EINVAL if
- +  * presented with invalid clockdomain pointers or called on a machine
- +  * that does not support software-configurable hardware sleep
- +  * dependencies, -ENOENT if the specified dependency cannot be set in
- +  * hardware, or 0 upon success.
- +  */
- + int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
- + {
- + 	struct clkdm_dep *cd;
- + 	int ret = 0;
- + 
- + 	if (!clkdm1 || !clkdm2)
- + 		return -EINVAL;
- + 
- + 	cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs);
- + 	if (IS_ERR(cd))
- + 		ret = PTR_ERR(cd);
- + 
- + 	if (!arch_clkdm || !arch_clkdm->clkdm_add_sleepdep)
- + 		ret = -EINVAL;
- + 
- + 	if (ret) {
- + 		pr_debug("clockdomain: hardware cannot set/clear sleep "
- + 			 "dependency affecting %s from %s\n", clkdm1->name,
- + 			 clkdm2->name);
- + 		return ret;
- + 	}
- + 
- + 	if (atomic_inc_return(&cd->sleepdep_usecount) == 1) {
- + 		pr_debug("clockdomain: will prevent %s from sleeping if %s "
- + 			 "is active\n", clkdm1->name, clkdm2->name);
- + 
- + 		ret = arch_clkdm->clkdm_add_sleepdep(clkdm1, clkdm2);
- + 	}
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * clkdm_del_sleepdep - remove a sleep dependency from clkdm2 to clkdm1
- +  * @clkdm1: prevent this struct clockdomain * from sleeping (dependent)
- +  * @clkdm2: when this struct clockdomain * is active (source)
- +  *
- +  * Allow @clkdm1 to automatically go inactive (and then to retention or
- +  * off), independent of the activity state of @clkdm2.  Returns -EINVAL
- +  * if presented with invalid clockdomain pointers or called on a machine
- +  * that does not support software-configurable hardware sleep dependencies,
- +  * -ENOENT if the specified dependency cannot be cleared in hardware, or
- +  * 0 upon success.
- +  */
- + int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
- + {
- + 	struct clkdm_dep *cd;
- + 	int ret = 0;
- + 
- + 	if (!clkdm1 || !clkdm2)
- + 		return -EINVAL;
- + 
- + 	cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs);
- + 	if (IS_ERR(cd))
- + 		ret = PTR_ERR(cd);
- + 
- + 	if (!arch_clkdm || !arch_clkdm->clkdm_del_sleepdep)
- + 		ret = -EINVAL;
- + 
- + 	if (ret) {
- + 		pr_debug("clockdomain: hardware cannot set/clear sleep "
- + 			 "dependency affecting %s from %s\n", clkdm1->name,
- + 			 clkdm2->name);
- + 		return ret;
- + 	}
- + 
- + 	if (atomic_dec_return(&cd->sleepdep_usecount) == 0) {
- + 		pr_debug("clockdomain: will no longer prevent %s from "
- + 			 "sleeping if %s is active\n", clkdm1->name,
- + 			 clkdm2->name);
- + 
- + 		ret = arch_clkdm->clkdm_del_sleepdep(clkdm1, clkdm2);
- + 	}
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * clkdm_read_sleepdep - read sleep dependency state from clkdm2 to clkdm1
- +  * @clkdm1: prevent this struct clockdomain * from sleeping (dependent)
- +  * @clkdm2: when this struct clockdomain * is active (source)
- +  *
- +  * Return 1 if a hardware sleep dependency exists wherein @clkdm1 will
- +  * not be allowed to automatically go inactive if @clkdm2 is active;
- +  * 0 if @clkdm1's automatic power state inactivity transition is independent
- +  * of @clkdm2's; -EINVAL if either clockdomain pointer is invalid or called
- +  * on a machine that does not support software-configurable hardware sleep
- +  * dependencies; or -ENOENT if the hardware is incapable.
- +  *
- +  * REVISIT: Currently this function only represents software-controllable
- +  * sleep dependencies.	Sleep dependencies fixed in hardware are not
- +  * yet handled here.
- +  */
- + int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
- + {
- + 	struct clkdm_dep *cd;
- + 	int ret = 0;
- + 
- + 	if (!clkdm1 || !clkdm2)
- + 		return -EINVAL;
- + 
- + 	cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs);
- + 	if (IS_ERR(cd))
- + 		ret = PTR_ERR(cd);
- + 
- + 	if (!arch_clkdm || !arch_clkdm->clkdm_read_sleepdep)
- + 		ret = -EINVAL;
- + 
- + 	if (ret) {
- + 		pr_debug("clockdomain: hardware cannot set/clear sleep "
- + 			 "dependency affecting %s from %s\n", clkdm1->name,
- + 			 clkdm2->name);
- + 		return ret;
- + 	}
- + 
- + 	/* XXX It's faster to return the atomic sleepdep_usecount */
- + 	return arch_clkdm->clkdm_read_sleepdep(clkdm1, clkdm2);
- + }
- + 
- + /**
- +  * clkdm_clear_all_sleepdeps - remove all sleep dependencies from target clkdm
- +  * @clkdm: struct clockdomain * to remove all sleep dependencies from
- +  *
- +  * Remove all inter-clockdomain sleep dependencies that could prevent
- +  * @clkdm from idling.  Intended to be used during boot to initialize the
- +  * PRCM to a known state, after all clockdomains are put into swsup idle
- +  * and woken up.  Returns -EINVAL if @clkdm pointer is invalid, or
- +  * 0 upon success.
- +  */
- + int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
- + {
- + 	if (!clkdm)
- + 		return -EINVAL;
- + 
- + 	if (!arch_clkdm || !arch_clkdm->clkdm_clear_all_sleepdeps)
- + 		return -EINVAL;
- + 
- + 	return arch_clkdm->clkdm_clear_all_sleepdeps(clkdm);
- + }
- + 
- + /**
- +  * clkdm_sleep - force clockdomain sleep transition
- +  * @clkdm: struct clockdomain *
- +  *
- +  * Instruct the CM to force a sleep transition on the specified
- +  * clockdomain @clkdm.  Returns -EINVAL if @clkdm is NULL or if
- +  * clockdomain does not support software-initiated sleep; 0 upon
- +  * success.
- +  */
- + int clkdm_sleep(struct clockdomain *clkdm)
- + {
- + 	int ret;
- + 	unsigned long flags;
- + 
- + 	if (!clkdm)
- + 		return -EINVAL;
- + 
- + 	if (!(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
- + 		pr_debug("clockdomain: %s does not support forcing "
- + 			 "sleep via software\n", clkdm->name);
- + 		return -EINVAL;
- + 	}
- + 
- + 	if (!arch_clkdm || !arch_clkdm->clkdm_sleep)
- + 		return -EINVAL;
- + 
- + 	pr_debug("clockdomain: forcing sleep on %s\n", clkdm->name);
- + 
- + 	spin_lock_irqsave(&clkdm->lock, flags);
- + 	clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
- + 	ret = arch_clkdm->clkdm_sleep(clkdm);
- + 	spin_unlock_irqrestore(&clkdm->lock, flags);
- + 	return ret;
- + }
- + 
- + /**
- +  * clkdm_wakeup - force clockdomain wakeup transition
- +  * @clkdm: struct clockdomain *
- +  *
- +  * Instruct the CM to force a wakeup transition on the specified
- +  * clockdomain @clkdm.  Returns -EINVAL if @clkdm is NULL or if the
- +  * clockdomain does not support software-controlled wakeup; 0 upon
- +  * success.
- +  */
- + int clkdm_wakeup(struct clockdomain *clkdm)
- + {
- + 	int ret;
- + 	unsigned long flags;
- + 
- + 	if (!clkdm)
- + 		return -EINVAL;
- + 
- + 	if (!(clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) {
- + 		pr_debug("clockdomain: %s does not support forcing "
- + 			 "wakeup via software\n", clkdm->name);
- + 		return -EINVAL;
- + 	}
- + 
- + 	if (!arch_clkdm || !arch_clkdm->clkdm_wakeup)
- + 		return -EINVAL;
- + 
- + 	pr_debug("clockdomain: forcing wakeup on %s\n", clkdm->name);
- + 
- + 	spin_lock_irqsave(&clkdm->lock, flags);
- + 	clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
- + 	ret = arch_clkdm->clkdm_wakeup(clkdm);
- + 	ret |= pwrdm_state_switch(clkdm->pwrdm.ptr);
- + 	spin_unlock_irqrestore(&clkdm->lock, flags);
- + 	return ret;
- + }
- + 
- + /**
- +  * clkdm_allow_idle - enable hwsup idle transitions for clkdm
- +  * @clkdm: struct clockdomain *
- +  *
- +  * Allow the hardware to automatically switch the clockdomain @clkdm into
- +  * active or idle states, as needed by downstream clocks.  If the
- +  * clockdomain has any downstream clocks enabled in the clock
- +  * framework, wkdep/sleepdep autodependencies are added; this is so
- +  * device drivers can read and write to the device.  No return value.
- +  */
- + void clkdm_allow_idle(struct clockdomain *clkdm)
- + {
- + 	unsigned long flags;
- + 
- + 	if (!clkdm)
- + 		return;
- + 
- + 	if (!(clkdm->flags & CLKDM_CAN_ENABLE_AUTO)) {
- + 		pr_debug("clock: automatic idle transitions cannot be enabled "
- + 			 "on clockdomain %s\n", clkdm->name);
- + 		return;
- + 	}
- + 
- + 	if (!arch_clkdm || !arch_clkdm->clkdm_allow_idle)
- + 		return;
- + 
- + 	pr_debug("clockdomain: enabling automatic idle transitions for %s\n",
- + 		 clkdm->name);
- + 
- + 	spin_lock_irqsave(&clkdm->lock, flags);
- + 	clkdm->_flags |= _CLKDM_FLAG_HWSUP_ENABLED;
- + 	arch_clkdm->clkdm_allow_idle(clkdm);
- + 	pwrdm_clkdm_state_switch(clkdm);
- + 	spin_unlock_irqrestore(&clkdm->lock, flags);
- + }
- + 
- + /**
- +  * clkdm_deny_idle - disable hwsup idle transitions for clkdm
- +  * @clkdm: struct clockdomain *
- +  *
- +  * Prevent the hardware from automatically switching the clockdomain
- +  * @clkdm into inactive or idle states.  If the clockdomain has
- +  * downstream clocks enabled in the clock framework, wkdep/sleepdep
- +  * autodependencies are removed.  No return value.
- +  */
- + void clkdm_deny_idle(struct clockdomain *clkdm)
- + {
- + 	unsigned long flags;
- + 
- + 	if (!clkdm)
- + 		return;
- + 
- + 	if (!(clkdm->flags & CLKDM_CAN_DISABLE_AUTO)) {
- + 		pr_debug("clockdomain: automatic idle transitions cannot be "
- + 			 "disabled on %s\n", clkdm->name);
- + 		return;
- + 	}
- + 
- + 	if (!arch_clkdm || !arch_clkdm->clkdm_deny_idle)
- + 		return;
- + 
- + 	pr_debug("clockdomain: disabling automatic idle transitions for %s\n",
- + 		 clkdm->name);
- + 
- + 	spin_lock_irqsave(&clkdm->lock, flags);
- + 	clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
- + 	arch_clkdm->clkdm_deny_idle(clkdm);
- + 	pwrdm_state_switch(clkdm->pwrdm.ptr);
- + 	spin_unlock_irqrestore(&clkdm->lock, flags);
- + }
- + 
- + /**
- +  * clkdm_in_hwsup - is clockdomain @clkdm have hardware-supervised idle enabled?
- +  * @clkdm: struct clockdomain *
- +  *
- +  * Returns true if clockdomain @clkdm currently has
- +  * hardware-supervised idle enabled, or false if it does not or if
- +  * @clkdm is NULL.  It is only valid to call this function after
- +  * clkdm_init() has been called.  This function does not actually read
- +  * bits from the hardware; it instead tests an in-memory flag that is
- +  * changed whenever the clockdomain code changes the auto-idle mode.
- +  */
- + bool clkdm_in_hwsup(struct clockdomain *clkdm)
- + {
- + 	bool ret;
- + 	unsigned long flags;
- + 
- + 	if (!clkdm)
- + 		return false;
- + 
- + 	spin_lock_irqsave(&clkdm->lock, flags);
- + 	ret = (clkdm->_flags & _CLKDM_FLAG_HWSUP_ENABLED) ? true : false;
- + 	spin_unlock_irqrestore(&clkdm->lock, flags);
- + 
- + 	return ret;
- + }
- + 
- + /* Clockdomain-to-clock/hwmod framework interface code */
- + 
- + static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
- + {
- + 	unsigned long flags;
- + 
- + 	if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_enable)
- + 		return -EINVAL;
- + 
- + 	/*
- + 	 * For arch's with no autodeps, clkcm_clk_enable
- + 	 * should be called for every clock instance or hwmod that is
- + 	 * enabled, so the clkdm can be force woken up.
- + 	 */
- + 	if ((atomic_inc_return(&clkdm->usecount) > 1) && autodeps)
- + 		return 0;
- + 
- + 	spin_lock_irqsave(&clkdm->lock, flags);
- + 	arch_clkdm->clkdm_clk_enable(clkdm);
- + 	pwrdm_wait_transition(clkdm->pwrdm.ptr);
- + 	pwrdm_clkdm_state_switch(clkdm);
- + 	spin_unlock_irqrestore(&clkdm->lock, flags);
- + 
- + 	pr_debug("clockdomain: clkdm %s: enabled\n", clkdm->name);
- + 
- + 	return 0;
- + }
- + 
- + static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm)
- + {
- + 	unsigned long flags;
- + 
- + 	if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
- + 		return -EINVAL;
- + 
- + 	if (atomic_read(&clkdm->usecount) == 0) {
- + 		WARN_ON(1); /* underflow */
- + 		return -ERANGE;
- + 	}
- + 
- + 	if (atomic_dec_return(&clkdm->usecount) > 0)
- + 		return 0;
- + 
- + 	spin_lock_irqsave(&clkdm->lock, flags);
- + 	arch_clkdm->clkdm_clk_disable(clkdm);
- + 	pwrdm_clkdm_state_switch(clkdm);
- + 	spin_unlock_irqrestore(&clkdm->lock, flags);
- + 
- + 	pr_debug("clockdomain: clkdm %s: disabled\n", clkdm->name);
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * clkdm_clk_enable - add an enabled downstream clock to this clkdm
- +  * @clkdm: struct clockdomain *
- +  * @clk: struct clk * of the enabled downstream clock
- +  *
- +  * Increment the usecount of the clockdomain @clkdm and ensure that it
- +  * is awake before @clk is enabled.  Intended to be called by
- +  * clk_enable() code.  If the clockdomain is in software-supervised
- +  * idle mode, force the clockdomain to wake.  If the clockdomain is in
- +  * hardware-supervised idle mode, add clkdm-pwrdm autodependencies, to
- +  * ensure that devices in the clockdomain can be read from/written to
- +  * by on-chip processors.  Returns -EINVAL if passed null pointers;
- +  * returns 0 upon success or if the clockdomain is in hwsup idle mode.
- +  */
- + int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
- + {
- + 	/*
- + 	 * XXX Rewrite this code to maintain a list of enabled
- + 	 * downstream clocks for debugging purposes?
- + 	 */
- + 
- + 	if (!clk)
- + 		return -EINVAL;
- + 
- + 	return _clkdm_clk_hwmod_enable(clkdm);
- + }
- + 
- + /**
- +  * clkdm_clk_disable - remove an enabled downstream clock from this clkdm
- +  * @clkdm: struct clockdomain *
- +  * @clk: struct clk * of the disabled downstream clock
- +  *
- +  * Decrement the usecount of this clockdomain @clkdm when @clk is
- +  * disabled.  Intended to be called by clk_disable() code.  If the
- +  * clockdomain usecount goes to 0, put the clockdomain to sleep
- +  * (software-supervised mode) or remove the clkdm autodependencies
- +  * (hardware-supervised mode).  Returns -EINVAL if passed null
- +  * pointers; -ERANGE if the @clkdm usecount underflows; or returns 0
- +  * upon success or if the clockdomain is in hwsup idle mode.
- +  */
- + int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
- + {
- + 	/*
- + 	 * XXX Rewrite this code to maintain a list of enabled
- + 	 * downstream clocks for debugging purposes?
- + 	 */
- + 
- + 	if (!clk)
- + 		return -EINVAL;
- + 
- + 	return _clkdm_clk_hwmod_disable(clkdm);
- + }
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/clockdomain.h linux-3.2.1/arch/arm/mach-ckb_3352/clockdomain.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/clockdomain.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/clockdomain.h	2014-05-15 13:25:13.874974076 +0900
- ***************
- *** 0 ****
- --- 1,210 ----
- + /*
- +  * arch/arm/plat-omap/include/mach/clockdomain.h
- +  *
- +  * OMAP2/3 clockdomain framework functions
- +  *
- +  * Copyright (C) 2008 Texas Instruments, Inc.
- +  * Copyright (C) 2008-2011 Nokia Corporation
- +  *
- +  * Paul Walmsley
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAIN_H
- + #define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAIN_H
- + 
- + #include <linux/init.h>
- + #include <linux/spinlock.h>
- + 
- + #include "powerdomain.h"
- + #include <plat/clock.h>
- + #include <plat/omap_hwmod.h>
- + #include <plat/cpu.h>
- + 
- + /*
- +  * Clockdomain flags
- +  *
- +  * XXX Document CLKDM_CAN_* flags
- +  *
- +  * CLKDM_NO_AUTODEPS: Prevent "autodeps" from being added/removed from this
- +  *     clockdomain.  (Currently, this applies to OMAP3 clockdomains only.)
- +  */
- + #define CLKDM_CAN_FORCE_SLEEP			(1 << 0)
- + #define CLKDM_CAN_FORCE_WAKEUP			(1 << 1)
- + #define CLKDM_CAN_ENABLE_AUTO			(1 << 2)
- + #define CLKDM_CAN_DISABLE_AUTO			(1 << 3)
- + #define CLKDM_NO_AUTODEPS			(1 << 4)
- + 
- + #define CLKDM_CAN_HWSUP		(CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO)
- + #define CLKDM_CAN_SWSUP		(CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP)
- + #define CLKDM_CAN_HWSUP_SWSUP	(CLKDM_CAN_SWSUP | CLKDM_CAN_HWSUP)
- + 
- + /**
- +  * struct clkdm_autodep - clkdm deps to add when entering/exiting hwsup mode
- +  * @clkdm: clockdomain to add wkdep+sleepdep on - set name member only
- +  *
- +  * A clockdomain that should have wkdeps and sleepdeps added when a
- +  * clockdomain should stay active in hwsup mode; and conversely,
- +  * removed when the clockdomain should be allowed to go inactive in
- +  * hwsup mode.
- +  *
- +  * Autodeps are deprecated and should be removed after
- +  * omap_hwmod-based fine-grained module idle control is added.
- +  */
- + struct clkdm_autodep {
- + 	union {
- + 		const char *name;
- + 		struct clockdomain *ptr;
- + 	} clkdm;
- + };
- + 
- + /**
- +  * struct clkdm_dep - encode dependencies between clockdomains
- +  * @clkdm_name: clockdomain name
- +  * @clkdm: pointer to the struct clockdomain of @clkdm_name
- +  * @wkdep_usecount: Number of wakeup dependencies causing this clkdm to wake
- +  * @sleepdep_usecount: Number of sleep deps that could prevent clkdm from idle
- +  *
- +  * Statically defined.  @clkdm is resolved from @clkdm_name at runtime and
- +  * should not be pre-initialized.
- +  *
- +  * XXX Should also include hardware (fixed) dependencies.
- +  */
- + struct clkdm_dep {
- + 	const char *clkdm_name;
- + 	struct clockdomain *clkdm;
- + 	atomic_t wkdep_usecount;
- + 	atomic_t sleepdep_usecount;
- + };
- + 
- + /* Possible flags for struct clockdomain._flags */
- + #define _CLKDM_FLAG_HWSUP_ENABLED		BIT(0)
- + 
- + /**
- +  * struct clockdomain - OMAP clockdomain
- +  * @name: clockdomain name
- +  * @pwrdm: powerdomain containing this clockdomain
- +  * @clktrctrl_reg: CLKSTCTRL reg for the given clock domain
- +  * @clktrctrl_mask: CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg
- +  * @flags: Clockdomain capability flags
- +  * @_flags: Flags for use only by internal clockdomain code
- +  * @dep_bit: Bit shift of this clockdomain's PM_WKDEP/CM_SLEEPDEP bit
- +  * @prcm_partition: (OMAP4 only) PRCM partition ID for this clkdm's registers
- +  * @cm_inst: (OMAP4 only) CM instance register offset
- +  * @clkdm_offs: (OMAP4 only) CM clockdomain register offset
- +  * @wkdep_srcs: Clockdomains that can be told to wake this powerdomain up
- +  * @sleepdep_srcs: Clockdomains that can be told to keep this clkdm from inact
- +  * @usecount: Usecount tracking
- +  * @node: list_head to link all clockdomains together
- +  *
- +  * @prcm_partition should be a macro from mach-omap2/prcm44xx.h (OMAP4 only)
- +  * @cm_inst should be a macro ending in _INST from the OMAP4 CM instance
- +  *     definitions (OMAP4 only)
- +  * @clkdm_offs should be a macro ending in _CDOFFS from the OMAP4 CM instance
- +  *     definitions (OMAP4 only)
- +  */
- + struct clockdomain {
- + 	const char *name;
- + 	union {
- + 		const char *name;
- + 		struct powerdomain *ptr;
- + 	} pwrdm;
- + 	const u16 clktrctrl_mask;
- + 	const u8 flags;
- + 	u8 _flags;
- + 	const u8 dep_bit;
- + 	const u8 prcm_partition;
- + 	const s16 cm_inst;
- + 	const u16 clkdm_offs;
- + 	struct clkdm_dep *wkdep_srcs;
- + 	struct clkdm_dep *sleepdep_srcs;
- + 	atomic_t usecount;
- + 	struct list_head node;
- + 	spinlock_t lock;
- + };
- + 
- + /**
- +  * struct clkdm_ops - Arch specific function implementations
- +  * @clkdm_add_wkdep: Add a wakeup dependency between clk domains
- +  * @clkdm_del_wkdep: Delete a wakeup dependency between clk domains
- +  * @clkdm_read_wkdep: Read wakeup dependency state between clk domains
- +  * @clkdm_clear_all_wkdeps: Remove all wakeup dependencies from the clk domain
- +  * @clkdm_add_sleepdep: Add a sleep dependency between clk domains
- +  * @clkdm_del_sleepdep: Delete a sleep dependency between clk domains
- +  * @clkdm_read_sleepdep: Read sleep dependency state between clk domains
- +  * @clkdm_clear_all_sleepdeps: Remove all sleep dependencies from the clk domain
- +  * @clkdm_sleep: Force a clockdomain to sleep
- +  * @clkdm_wakeup: Force a clockdomain to wakeup
- +  * @clkdm_allow_idle: Enable hw supervised idle transitions for clock domain
- +  * @clkdm_deny_idle: Disable hw supervised idle transitions for clock domain
- +  * @clkdm_clk_enable: Put the clkdm in right state for a clock enable
- +  * @clkdm_clk_disable: Put the clkdm in right state for a clock disable
- +  */
- + struct clkdm_ops {
- + 	int	(*clkdm_add_wkdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
- + 	int	(*clkdm_del_wkdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
- + 	int	(*clkdm_read_wkdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
- + 	int	(*clkdm_clear_all_wkdeps)(struct clockdomain *clkdm);
- + 	int	(*clkdm_add_sleepdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
- + 	int	(*clkdm_del_sleepdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
- + 	int	(*clkdm_read_sleepdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
- + 	int	(*clkdm_clear_all_sleepdeps)(struct clockdomain *clkdm);
- + 	int	(*clkdm_sleep)(struct clockdomain *clkdm);
- + 	int	(*clkdm_wakeup)(struct clockdomain *clkdm);
- + 	void	(*clkdm_allow_idle)(struct clockdomain *clkdm);
- + 	void	(*clkdm_deny_idle)(struct clockdomain *clkdm);
- + 	int	(*clkdm_clk_enable)(struct clockdomain *clkdm);
- + 	int	(*clkdm_clk_disable)(struct clockdomain *clkdm);
- + };
- + 
- + int clkdm_register_platform_funcs(struct clkdm_ops *co);
- + int clkdm_register_autodeps(struct clkdm_autodep *ia);
- + int clkdm_register_clkdms(struct clockdomain **c);
- + int clkdm_complete_init(void);
- + 
- + struct clockdomain *clkdm_lookup(const char *name);
- + 
- + int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user),
- + 			void *user);
- + struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm);
- + 
- + int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
- + int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
- + int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
- + int clkdm_clear_all_wkdeps(struct clockdomain *clkdm);
- + int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
- + int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
- + int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
- + int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm);
- + 
- + void clkdm_allow_idle(struct clockdomain *clkdm);
- + void clkdm_deny_idle(struct clockdomain *clkdm);
- + bool clkdm_in_hwsup(struct clockdomain *clkdm);
- + 
- + int clkdm_wakeup(struct clockdomain *clkdm);
- + int clkdm_sleep(struct clockdomain *clkdm);
- + 
- + int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
- + int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
- + 
- + extern void __init omap242x_clockdomains_init(void);
- + extern void __init omap243x_clockdomains_init(void);
- + extern void __init am33xx_clockdomains_init(void);
- + extern void __init omap44xx_clockdomains_init(void);
- + extern void _clkdm_add_autodeps(struct clockdomain *clkdm);
- + extern void _clkdm_del_autodeps(struct clockdomain *clkdm);
- + 
- + extern struct clkdm_ops omap3_clkdm_operations;
- + extern struct clkdm_ops omap4_clkdm_operations;
- + extern struct clkdm_ops am33xx_clkdm_operations;
- + 
- + extern struct clkdm_dep gfx_24xx_wkdeps[];
- + extern struct clkdm_dep dsp_24xx_wkdeps[];
- + extern struct clockdomain wkup_common_clkdm;
- + extern struct clockdomain prm_common_clkdm;
- + extern struct clockdomain cm_common_clkdm;
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/clockdomains33xx_data.c linux-3.2.1/arch/arm/mach-ckb_3352/clockdomains33xx_data.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/clockdomains33xx_data.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/clockdomains33xx_data.c	2014-05-15 13:25:13.874974076 +0900
- ***************
- *** 0 ****
- --- 1,232 ----
- + /*
- +  * AM33XX Clock Domain data.
- +  *
- +  * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #include <linux/kernel.h>
- + #include <linux/io.h>
- + 
- + #include "prcm44xx.h"
- + #include "clockdomain.h"
- + #include "cm.h"
- + #include "cm33xx.h"
- + #include "cm-regbits-33xx.h"
- + 
- + static struct clockdomain l4ls_am33xx_clkdm = {
- + 	.name		= "l4ls_clkdm",
- + 	.pwrdm		= { .name = "per_pwrdm" },
- + 	.cm_inst	= AM33XX_CM_PER_MOD,
- + 	.prcm_partition	= AM33XX_PRM_PARTITION,
- + 	.clkdm_offs	= AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET,
- + 	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
- + 	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
- + };
- + 
- + static struct clockdomain l3s_am33xx_clkdm = {
- + 	.name		= "l3s_clkdm",
- + 	.pwrdm		= { .name = "per_pwrdm" },
- + 	.cm_inst	= AM33XX_CM_PER_MOD,
- + 	.prcm_partition	= AM33XX_PRM_PARTITION,
- + 	.clkdm_offs	= AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET,
- + 	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
- + 	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
- + };
- + 
- + static struct clockdomain l4fw_am33xx_clkdm = {
- + 	.name		= "l4fw_clkdm",
- + 	.pwrdm		= { .name = "per_pwrdm" },
- + 	.cm_inst	= AM33XX_CM_PER_MOD,
- + 	.prcm_partition	= AM33XX_PRM_PARTITION,
- + 	.clkdm_offs	= AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET,
- + 	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
- + 	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
- + };
- + 
- + static struct clockdomain l3_am33xx_clkdm = {
- + 	.name		= "l3_clkdm",
- + 	.pwrdm		= { .name = "per_pwrdm" },
- + 	.cm_inst	= AM33XX_CM_PER_MOD,
- + 	.prcm_partition	= AM33XX_PRM_PARTITION,
- + 	.clkdm_offs	= AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET,
- + 	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
- + 	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
- + };
- + 
- + static struct clockdomain l4hs_am33xx_clkdm = {
- + 	.name		= "l4hs_clkdm",
- + 	.pwrdm		= { .name = "per_pwrdm" },
- + 	.cm_inst	= AM33XX_CM_PER_MOD,
- + 	.prcm_partition	= AM33XX_PRM_PARTITION,
- + 	.clkdm_offs	= AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET,
- + 	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
- + 	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
- + };
- + 
- + static struct clockdomain ocpwp_l3_am33xx_clkdm = {
- + 	.name		= "ocpwp_l3_clkdm",
- + 	.pwrdm		= { .name = "per_pwrdm" },
- + 	.cm_inst	= AM33XX_CM_PER_MOD,
- + 	.prcm_partition	= AM33XX_PRM_PARTITION,
- + 	.clkdm_offs	= AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET,
- + 	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
- + 	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
- + };
- + 
- + static struct clockdomain pruss_ocp_am33xx_clkdm = {
- + 	.name		= "pruss_ocp_clkdm",
- + 	.pwrdm		= { .name = "per_pwrdm" },
- + 	.cm_inst	= AM33XX_CM_PER_MOD,
- + 	.prcm_partition	= AM33XX_PRM_PARTITION,
- + 	.clkdm_offs	= AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET,
- + 	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
- + 	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
- + };
- + 
- + static struct clockdomain cpsw_125mhz_am33xx_clkdm = {
- + 	.name		= "cpsw_125mhz_clkdm",
- + 	.pwrdm		= { .name = "per_pwrdm" },
- + 	.cm_inst	= AM33XX_CM_PER_MOD,
- + 	.prcm_partition	= AM33XX_PRM_PARTITION,
- + 	.clkdm_offs	= AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET,
- + 	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
- + 	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
- + };
- + 
- + static struct clockdomain lcdc_am33xx_clkdm = {
- + 	.name		= "lcdc_clkdm",
- + 	.pwrdm		= { .name = "per_pwrdm" },
- + 	.cm_inst	= AM33XX_CM_PER_MOD,
- + 	.prcm_partition	= AM33XX_PRM_PARTITION,
- + 	.clkdm_offs	= AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET,
- + 	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
- + 	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
- + };
- + 
- + static struct clockdomain clk_24mhz_am33xx_clkdm = {
- + 	.name		= "clk_24mhz_clkdm",
- + 	.pwrdm		= { .name = "per_pwrdm" },
- + 	.cm_inst	= AM33XX_CM_PER_MOD,
- + 	.prcm_partition	= AM33XX_PRM_PARTITION,
- + 	.clkdm_offs	= AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET,
- + 	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
- + 	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
- + };
- + 
- + static struct clockdomain l4_wkup_am33xx_clkdm = {
- + 	.name		= "l4_wkup_clkdm",
- + 	.pwrdm		= { .name = "wkup_pwrdm" },
- + 	.cm_inst	= AM33XX_CM_WKUP_MOD,
- + 	.prcm_partition	= AM33XX_PRM_PARTITION,
- + 	.clkdm_offs	= AM33XX_CM_WKUP_CLKSTCTRL_OFFSET,
- + 	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
- + 	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
- + };
- + 
- + static struct clockdomain l3_aon_am33xx_clkdm = {
- + 	.name		= "l3_aon_clkdm",
- + 	.pwrdm		= { .name = "wkup_pwrdm" },
- + 	.cm_inst	= AM33XX_CM_WKUP_MOD,
- + 	.prcm_partition	= AM33XX_PRM_PARTITION,
- + 	.clkdm_offs	= AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET,
- + 	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
- + 	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
- + };
- + 
- + static struct clockdomain l4_wkup_aon_am33xx_clkdm = {
- + 	.name		= "l4_wkup_aon_clkdm",
- + 	.pwrdm		= { .name = "wkup_pwrdm" },
- + 	.cm_inst	= AM33XX_CM_WKUP_MOD,
- + 	.prcm_partition	= AM33XX_PRM_PARTITION,
- + 	.clkdm_offs	= AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET,
- + 	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
- + 	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
- + };
- + 
- + static struct clockdomain mpu_am33xx_clkdm = {
- + 	.name		= "mpu_clkdm",
- + 	.pwrdm		= { .name = "mpu_pwrdm" },
- + 	.cm_inst	= AM33XX_CM_MPU_MOD,
- + 	.prcm_partition	= AM33XX_PRM_PARTITION,
- + 	.clkdm_offs	= AM33XX_CM_MPU_CLKSTCTRL_OFFSET,
- + 	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
- + 	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
- + };
- + 
- + static struct clockdomain l4_rtc_am33xx_clkdm = {
- + 	.name		= "l4_rtc_clkdm",
- + 	.pwrdm		= { .name = "rtc_pwrdm" },
- + 	.cm_inst	= AM33XX_CM_RTC_MOD,
- + 	.prcm_partition	= AM33XX_PRM_PARTITION,
- + 	.clkdm_offs	= AM33XX_CM_RTC_CLKSTCTRL_OFFSET,
- + 	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
- + 	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
- + };
- + 
- + static struct clockdomain gfx_l3_am33xx_clkdm = {
- + 	.name		= "gfx_l3_clkdm",
- + 	.pwrdm		= { .name = "gfx_pwrdm" },
- + 	.cm_inst	= AM33XX_CM_GFX_MOD,
- + 	.prcm_partition	= AM33XX_PRM_PARTITION,
- + 	.clkdm_offs	= AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET,
- + 	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
- + 	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
- + };
- + 
- + static struct clockdomain gfx_l4ls_gfx_am33xx_clkdm = {
- + 	.name		= "gfx_l4ls_gfx_clkdm",
- + 	.pwrdm		= { .name = "gfx_pwrdm" },
- + 	.cm_inst	= AM33XX_CM_GFX_MOD,
- + 	.prcm_partition	= AM33XX_PRM_PARTITION,
- + 	.clkdm_offs	= AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET,
- + 	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
- + 	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
- + };
- + 
- + static struct clockdomain l4_cefuse_am33xx_clkdm = {
- + 	.name		= "l4_cefuse_clkdm",
- + 	.pwrdm		= { .name = "cefuse_pwrdm" },
- + 	.cm_inst	= AM33XX_CM_CEFUSE_MOD,
- + 	.prcm_partition	= AM33XX_PRM_PARTITION,
- + 	.clkdm_offs	= AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET,
- + 	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
- + 	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
- + };
- + 
- + static struct clockdomain *clockdomains_am33xx[] __initdata = {
- + 	&l4ls_am33xx_clkdm,
- + 	&l3s_am33xx_clkdm,
- + 	&l4fw_am33xx_clkdm,
- + 	&l3_am33xx_clkdm,
- + 	&l4hs_am33xx_clkdm,
- + 	&ocpwp_l3_am33xx_clkdm,
- + 	&pruss_ocp_am33xx_clkdm,
- + 	&cpsw_125mhz_am33xx_clkdm,
- + 	&lcdc_am33xx_clkdm,
- + 	&clk_24mhz_am33xx_clkdm,
- + 	&l4_wkup_am33xx_clkdm,
- + 	&l3_aon_am33xx_clkdm,
- + 	&l4_wkup_aon_am33xx_clkdm,
- + 	&mpu_am33xx_clkdm,
- + 	&l4_rtc_am33xx_clkdm,
- + 	&gfx_l3_am33xx_clkdm,
- + 	&gfx_l4ls_gfx_am33xx_clkdm,
- + 	&l4_cefuse_am33xx_clkdm,
- + 	NULL,
- + };
- + 
- + void __init am33xx_clockdomains_init(void)
- + {
- + 	clkdm_register_platform_funcs(&am33xx_clkdm_operations);
- + 	clkdm_register_clkdms(clockdomains_am33xx);
- + 	clkdm_complete_init();
- + }
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/clock.h linux-3.2.1/arch/arm/mach-ckb_3352/clock.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/clock.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/clock.h	2014-05-15 13:25:13.878817899 +0900
- ***************
- *** 0 ****
- --- 1,125 ----
- + /*
- +  *  linux/arch/arm/mach-omap2/clock.h
- +  *
- +  *  Copyright (C) 2005-2009 Texas Instruments, Inc.
- +  *  Copyright (C) 2004-2011 Nokia Corporation
- +  *
- +  *  Contacts:
- +  *  Richard Woodruff <r-woodruff2@ti.com>
- +  *  Paul Walmsley
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
- + #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
- + 
- + #include <linux/kernel.h>
- + 
- + #include <plat/clock.h>
- + 
- + /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
- + #define CORE_CLK_SRC_32K		0x0
- + #define CORE_CLK_SRC_DPLL		0x1
- + #define CORE_CLK_SRC_DPLL_X2		0x2
- + 
- + /* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */
- + #define OMAP2XXX_EN_DPLL_LPBYPASS		0x1
- + #define OMAP2XXX_EN_DPLL_FRBYPASS		0x2
- + #define OMAP2XXX_EN_DPLL_LOCKED			0x3
- + 
- + /* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
- + #define OMAP3XXX_EN_DPLL_LPBYPASS		0x5
- + #define OMAP3XXX_EN_DPLL_FRBYPASS		0x6
- + #define OMAP3XXX_EN_DPLL_LOCKED			0x7
- + 
- + /* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
- + #define OMAP4XXX_EN_DPLL_MNBYPASS		0x4
- + 
- + /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
- + #define DPLL_LOW_POWER_STOP	0x1
- + #define DPLL_LOW_POWER_BYPASS	0x5
- + #define DPLL_LOCKED		0x7
- + 
- + /* DPLL Type and DCO Selection Flags */
- + #define DPLL_J_TYPE		0x1
- + 
- + int omap2_clk_enable(struct clk *clk);
- + void omap2_clk_disable(struct clk *clk);
- + long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
- + int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
- + int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
- + long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
- + unsigned long omap3_dpll_recalc(struct clk *clk);
- + unsigned long omap3_clkoutx2_recalc(struct clk *clk);
- + void omap3_dpll_allow_idle(struct clk *clk);
- + void omap3_dpll_deny_idle(struct clk *clk);
- + u32 omap3_dpll_autoidle_read(struct clk *clk);
- + int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
- + int omap3_noncore_dpll_enable(struct clk *clk);
- + void omap3_noncore_dpll_disable(struct clk *clk);
- + int omap4_dpllmx_gatectrl_read(struct clk *clk);
- + void omap4_dpllmx_allow_gatectrl(struct clk *clk);
- + void omap4_dpllmx_deny_gatectrl(struct clk *clk);
- + long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate);
- + unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk);
- + 
- + #ifdef CONFIG_OMAP_RESET_CLOCKS
- + void omap2_clk_disable_unused(struct clk *clk);
- + #else
- + #define omap2_clk_disable_unused	NULL
- + #endif
- + 
- + void omap2_init_clk_clkdm(struct clk *clk);
- + void __init omap2_clk_disable_clkdm_control(void);
- + 
- + /* clkt_clksel.c public functions */
- + u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
- + 				u32 *new_div);
- + void omap2_init_clksel_parent(struct clk *clk);
- + unsigned long omap2_clksel_recalc(struct clk *clk);
- + long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
- + int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
- + int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent);
- + 
- + u32 omap2_get_dpll_rate(struct clk *clk);
- + void omap2_init_dpll_parent(struct clk *clk);
- + 
- + int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
- + 
- + 
- + 
- + void omap3_clk_prepare_for_reboot(void);
- + 
- + int omap2_dflt_clk_enable(struct clk *clk);
- + void omap2_dflt_clk_disable(struct clk *clk);
- + void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
- + 				   u8 *other_bit);
- + int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
- + void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
- + 			       const char *core_ck_name,
- + 			       const char *mpu_ck_name);
- + 
- + extern u16 cpu_mask;
- + 
- + extern const struct clkops clkops_dummy;
- + extern const struct clkops clkops_omap2_dflt;
- + 
- + extern struct clk_functions omap2_clk_functions;
- + extern struct clk *vclk, *sclk;
- + 
- + extern const struct clksel_rate gpt_32k_rates[];
- + extern const struct clksel_rate gpt_sys_rates[];
- + extern const struct clksel_rate gfx_l3_rates[];
- + extern const struct clksel_rate dsp_ick_rates[];
- + 
- + #define omap2_clk_init_cpufreq_table	0
- + #define omap2_clk_exit_cpufreq_table	0
- + 
- + extern const struct clkops clkops_omap3_noncore_dpll_ops;
- + extern const struct clkops clkops_omap3_core_dpll_ops;
- + extern const struct clkops clkops_omap4_dpllmx_ops;
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/cm2xxx_3xxx.h linux-3.2.1/arch/arm/mach-ckb_3352/cm2xxx_3xxx.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/cm2xxx_3xxx.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/cm2xxx_3xxx.h	2014-05-15 13:25:13.878817899 +0900
- ***************
- *** 0 ****
- --- 1,147 ----
- + /*
- +  * OMAP2/3 Clock Management (CM) register definitions
- +  *
- +  * Copyright (C) 2007-2009 Texas Instruments, Inc.
- +  * Copyright (C) 2007-2010 Nokia Corporation
- +  * Paul Walmsley
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  *
- +  * The CM hardware modules on the OMAP2/3 are quite similar to each
- +  * other.  The CM modules/instances on OMAP4 are quite different, so
- +  * they are handled in a separate file.
- +  */
- + #ifndef __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H
- + #define __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H
- + 
- + #include "prcm-common.h"
- + 
- + #define OMAP34XX_CM_REGADDR(module, reg)				\
- + 			OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
- + 
- + 
- + /*
- +  * OMAP3-specific global CM registers
- +  * Use cm_{read,write}_reg() with these registers.
- +  * These registers appear once per CM module.
- +  */
- + 
- + #define OMAP3430_CM_REVISION		OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000)
- + #define OMAP3430_CM_SYSCONFIG		OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
- + #define OMAP3430_CM_POLCTRL		OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
- + 
- + #define OMAP3_CM_CLKOUT_CTRL_OFFSET	0x0070
- + #define OMAP3430_CM_CLKOUT_CTRL		OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
- + 
- + /*
- +  * Module specific CM register offsets from CM_BASE + domain offset
- +  * Use cm_{read,write}_mod_reg() with these registers.
- +  * These register offsets generally appear in more than one PRCM submodule.
- +  */
- + 
- + /* Common between OMAP2 and OMAP3 */
- + 
- + #define CM_FCLKEN					0x0000
- + #define CM_FCLKEN1					CM_FCLKEN
- + #define CM_CLKEN					CM_FCLKEN
- + #define CM_ICLKEN					0x0010
- + #define CM_ICLKEN1					CM_ICLKEN
- + #define CM_ICLKEN2					0x0014
- + #define CM_ICLKEN3					0x0018
- + #define CM_IDLEST					0x0020
- + #define CM_IDLEST1					CM_IDLEST
- + #define CM_IDLEST2					0x0024
- + #define CM_AUTOIDLE					0x0030
- + #define CM_AUTOIDLE1					CM_AUTOIDLE
- + #define CM_AUTOIDLE2					0x0034
- + #define CM_AUTOIDLE3					0x0038
- + #define CM_CLKSEL					0x0040
- + #define CM_CLKSEL1					CM_CLKSEL
- + #define CM_CLKSEL2					0x0044
- + #define OMAP2_CM_CLKSTCTRL				0x0048
- + 
- + /* OMAP2-specific register offsets */
- + 
- + #define OMAP24XX_CM_FCLKEN2				0x0004
- + #define OMAP24XX_CM_ICLKEN4				0x001c
- + #define OMAP24XX_CM_AUTOIDLE4				0x003c
- + 
- + #define OMAP2430_CM_IDLEST3				0x0028
- + 
- + /* OMAP3-specific register offsets */
- + 
- + #define OMAP3430_CM_CLKEN_PLL				0x0004
- + #define OMAP3430ES2_CM_CLKEN2				0x0004
- + #define OMAP3430ES2_CM_FCLKEN3				0x0008
- + #define OMAP3430_CM_IDLEST_PLL				CM_IDLEST2
- + #define OMAP3430_CM_AUTOIDLE_PLL			CM_AUTOIDLE2
- + #define OMAP3430ES2_CM_AUTOIDLE2_PLL			CM_AUTOIDLE2
- + #define OMAP3430_CM_CLKSEL1				CM_CLKSEL
- + #define OMAP3430_CM_CLKSEL1_PLL				CM_CLKSEL
- + #define OMAP3430_CM_CLKSEL2_PLL				CM_CLKSEL2
- + #define OMAP3430_CM_SLEEPDEP				CM_CLKSEL2
- + #define OMAP3430_CM_CLKSEL3				OMAP2_CM_CLKSTCTRL
- + #define OMAP3430_CM_CLKSTST				0x004c
- + #define OMAP3430ES2_CM_CLKSEL4				0x004c
- + #define OMAP3430ES2_CM_CLKSEL5				0x0050
- + #define OMAP3430_CM_CLKSEL2_EMU				0x0050
- + #define OMAP3430_CM_CLKSEL3_EMU				0x0054
- + 
- + 
- + /* CM_IDLEST bit field values to indicate deasserted IdleReq */
- + 
- + #define OMAP24XX_CM_IDLEST_VAL				0
- + #define OMAP34XX_CM_IDLEST_VAL				1
- + 
- + 
- + /* Clock management domain register get/set */
- + 
- + #ifndef __ASSEMBLER__
- + 
- + extern u32 omap2_cm_read_mod_reg(s16 module, u16 idx);
- + extern void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx);
- + extern u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
- + 
- + extern u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx);
- + extern u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx);
- + 
- + extern bool omap2_cm_is_clkdm_in_hwsup(s16 module, u32 mask);
- + extern void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask);
- + extern void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
- + 
- + extern void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask);
- + extern void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
- + extern void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask);
- + extern void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask);
- + 
- + extern int am33xx_cm_wait_module_ready(u16 inst, u16 clkctrl_reg);
- + extern void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 clkdm, u32 mask);
- + extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 clkdm, u32 mask);
- + extern void am33xx_cm_clkdm_force_sleep(s16 inst, u16 clkdm, u32 mask);
- + extern void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 clkdm, u32 mask);
- + 
- + #endif
- + 
- + /* CM register bits shared between 24XX and 3430 */
- + 
- + /* CM_CLKSEL_GFX */
- + #define OMAP_CLKSEL_GFX_SHIFT				0
- + #define OMAP_CLKSEL_GFX_MASK				(0x7 << 0)
- + 
- + /* CM_ICLKEN_GFX */
- + #define OMAP_EN_GFX_SHIFT				0
- + #define OMAP_EN_GFX_MASK				(1 << 0)
- + 
- + /* CM_IDLEST_GFX */
- + #define OMAP_ST_GFX_MASK				(1 << 0)
- + 
- + 
- + /* Function prototypes */
- + # ifndef __ASSEMBLER__
- + extern void omap3_cm_save_context(void);
- + extern void omap3_cm_restore_context(void);
- + # endif
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/cm33xx.h linux-3.2.1/arch/arm/mach-ckb_3352/cm33xx.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/cm33xx.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/cm33xx.h	2014-05-15 13:25:13.878817899 +0900
- ***************
- *** 0 ****
- --- 1,377 ----
- + /*
- +  * AM33XX CM instance offset macros
- +  *
- +  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H
- + #define __ARCH_ARM_MACH_OMAP2_CM_33XX_H
- + 
- + #include "common.h"
- + 
- + #include "cm.h"
- + #include "cm-regbits-33xx.h"
- + #include "cm33xx.h"
- + 
- + /* CM base address */
- + #define AM33XX_CM_BASE		0x44e00000
- + 
- + #define AM33XX_CM_REGADDR(inst, reg)				\
- + 	AM33XX_L4_WK_IO_ADDRESS(AM33XX_CM_BASE + (inst) + (reg))
- + 
- + /* CM instances */
- + #define AM33XX_CM_PER_MOD		0x0000
- + #define AM33XX_CM_WKUP_MOD		0x0400
- + #define AM33XX_CM_DPLL_MOD		0x0500
- + #define AM33XX_CM_MPU_MOD		0x0600
- + #define AM33XX_CM_DEVICE_MOD		0x0700
- + #define AM33XX_CM_RTC_MOD		0x0800
- + #define AM33XX_CM_GFX_MOD		0x0900
- + #define AM33XX_CM_CEFUSE_MOD		0x0A00
- + 
- + /* CM */
- + 
- + /* CM.PER_CM register offsets */
- + #define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET		0x0000
- + #define AM33XX_CM_PER_L4LS_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0000)
- + #define AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET		0x0004
- + #define AM33XX_CM_PER_L3S_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0004)
- + #define AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET		0x0008
- + #define AM33XX_CM_PER_L4FW_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0008)
- + #define AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET		0x000c
- + #define AM33XX_CM_PER_L3_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x000c)
- + #define AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET		0x0014
- + #define AM33XX_CM_PER_CPGMAC0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0014)
- + #define AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET		0x0018
- + #define AM33XX_CM_PER_LCDC_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0018)
- + #define AM33XX_CM_PER_USB0_CLKCTRL_OFFSET		0x001c
- + #define AM33XX_CM_PER_USB0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x001c)
- + #define AM33XX_CM_PER_MLB_CLKCTRL_OFFSET		0x0020
- + #define AM33XX_CM_PER_MLB_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0020)
- + #define AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET		0x0024
- + #define AM33XX_CM_PER_TPTC0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0024)
- + #define AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET		0x0028
- + #define AM33XX_CM_PER_EMIF_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0028)
- + #define AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET		0x002c
- + #define AM33XX_CM_PER_OCMCRAM_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x002c)
- + #define AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET		0x0030
- + #define AM33XX_CM_PER_GPMC_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0030)
- + #define AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET		0x0034
- + #define AM33XX_CM_PER_MCASP0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0034)
- + #define AM33XX_CM_PER_UART5_CLKCTRL_OFFSET		0x0038
- + #define AM33XX_CM_PER_UART5_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0038)
- + #define AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET		0x003c
- + #define AM33XX_CM_PER_MMC0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x003c)
- + #define AM33XX_CM_PER_ELM_CLKCTRL_OFFSET		0x0040
- + #define AM33XX_CM_PER_ELM_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0040)
- + #define AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET		0x0044
- + #define AM33XX_CM_PER_I2C2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0044)
- + #define AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET		0x0048
- + #define AM33XX_CM_PER_I2C1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0048)
- + #define AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET		0x004c
- + #define AM33XX_CM_PER_SPI0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x004c)
- + #define AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET		0x0050
- + #define AM33XX_CM_PER_SPI1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0050)
- + #define AM33XX_CM_PER_SPI2_CLKCTRL_OFFSET		0x0054
- + #define AM33XX_CM_PER_SPI2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0054)
- + #define AM33XX_CM_PER_SPI3_CLKCTRL_OFFSET		0x0058
- + #define AM33XX_CM_PER_SPI3_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0058)
- + #define AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET		0x0060
- + #define AM33XX_CM_PER_L4LS_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0060)
- + #define AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET		0x0064
- + #define AM33XX_CM_PER_L4FW_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0064)
- + #define AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET		0x0068
- + #define AM33XX_CM_PER_MCASP1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0068)
- + #define AM33XX_CM_PER_UART1_CLKCTRL_OFFSET		0x006c
- + #define AM33XX_CM_PER_UART1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x006c)
- + #define AM33XX_CM_PER_UART2_CLKCTRL_OFFSET		0x0070
- + #define AM33XX_CM_PER_UART2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0070)
- + #define AM33XX_CM_PER_UART3_CLKCTRL_OFFSET		0x0074
- + #define AM33XX_CM_PER_UART3_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0074)
- + #define AM33XX_CM_PER_UART4_CLKCTRL_OFFSET		0x0078
- + #define AM33XX_CM_PER_UART4_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0078)
- + #define AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET		0x007c
- + #define AM33XX_CM_PER_TIMER7_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x007c)
- + #define AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET		0x0080
- + #define AM33XX_CM_PER_TIMER2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0080)
- + #define AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET		0x0084
- + #define AM33XX_CM_PER_TIMER3_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0084)
- + #define AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET		0x0088
- + #define AM33XX_CM_PER_TIMER4_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0088)
- + #define AM33XX_CM_PER_MCASP2_CLKCTRL_OFFSET		0x008c
- + #define AM33XX_CM_PER_MCASP2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x008c)
- + #define AM33XX_CM_PER_RNG_CLKCTRL_OFFSET		0x0090
- + #define AM33XX_CM_PER_RNG_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0090)
- + #define AM33XX_CM_PER_AES0_CLKCTRL_OFFSET		0x0094
- + #define AM33XX_CM_PER_AES0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0094)
- + #define AM33XX_CM_PER_AES1_CLKCTRL_OFFSET		0x0098
- + #define AM33XX_CM_PER_AES1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0098)
- + #define AM33XX_CM_PER_DES_CLKCTRL_OFFSET		0x009c
- + #define AM33XX_CM_PER_DES_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x009c)
- + #define AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET		0x00a0
- + #define AM33XX_CM_PER_SHA0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a0)
- + #define AM33XX_CM_PER_PKA_CLKCTRL_OFFSET		0x00a4
- + #define AM33XX_CM_PER_PKA_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a4)
- + #define AM33XX_CM_PER_GPIO6_CLKCTRL_OFFSET		0x00a8
- + #define AM33XX_CM_PER_GPIO6_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a8)
- + #define AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET		0x00ac
- + #define AM33XX_CM_PER_GPIO1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ac)
- + #define AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET		0x00b0
- + #define AM33XX_CM_PER_GPIO2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b0)
- + #define AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET		0x00b4
- + #define AM33XX_CM_PER_GPIO3_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b4)
- + #define AM33XX_CM_PER_GPIO4_CLKCTRL_OFFSET		0x00b8
- + #define AM33XX_CM_PER_GPIO4_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b8)
- + #define AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET		0x00bc
- + #define AM33XX_CM_PER_TPCC_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00bc)
- + #define AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET		0x00c0
- + #define AM33XX_CM_PER_DCAN0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c0)
- + #define AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET		0x00c4
- + #define AM33XX_CM_PER_DCAN1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c4)
- + #define AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET		0x00cc
- + #define AM33XX_CM_PER_EPWMSS1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00cc)
- + #define AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET		0x00d0
- + #define AM33XX_CM_PER_EMIF_FW_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d0)
- + #define AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET		0x00d4
- + #define AM33XX_CM_PER_EPWMSS0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d4)
- + #define AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET		0x00d8
- + #define AM33XX_CM_PER_EPWMSS2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d8)
- + #define AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET		0x00dc
- + #define AM33XX_CM_PER_L3_INSTR_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00dc)
- + #define AM33XX_CM_PER_L3_CLKCTRL_OFFSET			0x00e0
- + #define AM33XX_CM_PER_L3_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e0)
- + #define AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET		0x00e4
- + #define AM33XX_CM_PER_IEEE5000_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e4)
- + #define AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET		0x00e8
- + #define AM33XX_CM_PER_PRUSS_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e8)
- + #define AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET		0x00ec
- + #define AM33XX_CM_PER_TIMER5_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ec)
- + #define AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET		0x00f0
- + #define AM33XX_CM_PER_TIMER6_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f0)
- + #define AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET		0x00f4
- + #define AM33XX_CM_PER_MMC1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f4)
- + #define AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET		0x00f8
- + #define AM33XX_CM_PER_MMC2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f8)
- + #define AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET		0x00fc
- + #define AM33XX_CM_PER_TPTC1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00fc)
- + #define AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET		0x0100
- + #define AM33XX_CM_PER_TPTC2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0100)
- + #define AM33XX_CM_PER_GPIO5_CLKCTRL_OFFSET		0x0104
- + #define AM33XX_CM_PER_GPIO5_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0104)
- + #define AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET		0x010c
- + #define AM33XX_CM_PER_SPINLOCK_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x010c)
- + #define AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET		0x0110
- + #define AM33XX_CM_PER_MAILBOX0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0110)
- + #define AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET		0x011c
- + #define AM33XX_CM_PER_L4HS_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x011c)
- + #define AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET		0x0120
- + #define AM33XX_CM_PER_L4HS_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0120)
- + #define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL_OFFSET		0x0124
- + #define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0124)
- + #define AM33XX_CM_PER_SLV_EXPS_CLKCTRL_OFFSET		0x0128
- + #define AM33XX_CM_PER_SLV_EXPS_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0128)
- + #define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET		0x012c
- + #define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL		AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x012c)
- + #define AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET		0x0130
- + #define AM33XX_CM_PER_OCPWP_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0130)
- + #define AM33XX_CM_PER_MAILBOX1_CLKCTRL_OFFSET		0x0134
- + #define AM33XX_CM_PER_MAILBOX1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0134)
- + #define AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET		0x0140
- + #define AM33XX_CM_PER_PRUSS_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0140)
- + #define AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET		0x0144
- + #define AM33XX_CM_PER_CPSW_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0144)
- + #define AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET		0x0148
- + #define AM33XX_CM_PER_LCDC_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0148)
- + #define AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET		0x014c
- + #define AM33XX_CM_PER_CLKDIV32K_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x014c)
- + #define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET	0x0150
- + #define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL		AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0150)
- + 
- + /* CM.WKUP_CM register offsets */
- + #define AM33XX_CM_WKUP_CLKSTCTRL_OFFSET			0x0000
- + #define AM33XX_CM_WKUP_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0000)
- + #define AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET		0x0004
- + #define AM33XX_CM_WKUP_CONTROL_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0004)
- + #define AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET		0x0008
- + #define AM33XX_CM_WKUP_GPIO0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0008)
- + #define AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET		0x000c
- + #define AM33XX_CM_WKUP_L4WKUP_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x000c)
- + #define AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET		0x0010
- + #define AM33XX_CM_WKUP_TIMER0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0010)
- + #define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET		0x0014
- + #define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0014)
- + #define AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET		0x0018
- + #define AM33XX_CM_L3_AON_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0018)
- + #define AM33XX_CM_AUTOIDLE_DPLL_MPU_OFFSET		0x001c
- + #define AM33XX_CM_AUTOIDLE_DPLL_MPU			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x001c)
- + #define AM33XX_CM_IDLEST_DPLL_MPU_OFFSET		0x0020
- + #define AM33XX_CM_IDLEST_DPLL_MPU			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0020)
- + #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET	0x0024
- + #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0024)
- + #define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET	0x0028
- + #define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0028)
- + #define AM33XX_CM_CLKSEL_DPLL_MPU_OFFSET		0x002c
- + #define AM33XX_CM_CLKSEL_DPLL_MPU			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x002c)
- + #define AM33XX_CM_AUTOIDLE_DPLL_DDR_OFFSET		0x0030
- + #define AM33XX_CM_AUTOIDLE_DPLL_DDR			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0030)
- + #define AM33XX_CM_IDLEST_DPLL_DDR_OFFSET		0x0034
- + #define AM33XX_CM_IDLEST_DPLL_DDR			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0034)
- + #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET	0x0038
- + #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0038)
- + #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET	0x003c
- + #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x003c)
- + #define AM33XX_CM_CLKSEL_DPLL_DDR_OFFSET		0x0040
- + #define AM33XX_CM_CLKSEL_DPLL_DDR			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0040)
- + #define AM33XX_CM_AUTOIDLE_DPLL_DISP_OFFSET		0x0044
- + #define AM33XX_CM_AUTOIDLE_DPLL_DISP			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0044)
- + #define AM33XX_CM_IDLEST_DPLL_DISP_OFFSET		0x0048
- + #define AM33XX_CM_IDLEST_DPLL_DISP			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0048)
- + #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP_OFFSET	0x004c
- + #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x004c)
- + #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP_OFFSET	0x0050
- + #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0050)
- + #define AM33XX_CM_CLKSEL_DPLL_DISP_OFFSET		0x0054
- + #define AM33XX_CM_CLKSEL_DPLL_DISP			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0054)
- + #define AM33XX_CM_AUTOIDLE_DPLL_CORE_OFFSET		0x0058
- + #define AM33XX_CM_AUTOIDLE_DPLL_CORE			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0058)
- + #define AM33XX_CM_IDLEST_DPLL_CORE_OFFSET		0x005c
- + #define AM33XX_CM_IDLEST_DPLL_CORE			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x005c)
- + #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET	0x0060
- + #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0060)
- + #define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET	0x0064
- + #define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0064)
- + #define AM33XX_CM_CLKSEL_DPLL_CORE_OFFSET		0x0068
- + #define AM33XX_CM_CLKSEL_DPLL_CORE			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0068)
- + #define AM33XX_CM_AUTOIDLE_DPLL_PER_OFFSET		0x006c
- + #define AM33XX_CM_AUTOIDLE_DPLL_PER			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x006c)
- + #define AM33XX_CM_IDLEST_DPLL_PER_OFFSET		0x0070
- + #define AM33XX_CM_IDLEST_DPLL_PER			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0070)
- + #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET	0x0074
- + #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0074)
- + #define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET	0x0078
- + #define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0078)
- + #define AM33XX_CM_CLKDCOLDO_DPLL_PER_OFFSET		0x007c
- + #define AM33XX_CM_CLKDCOLDO_DPLL_PER			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x007c)
- + #define AM33XX_CM_DIV_M4_DPLL_CORE_OFFSET		0x0080
- + #define AM33XX_CM_DIV_M4_DPLL_CORE			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0080)
- + #define AM33XX_CM_DIV_M5_DPLL_CORE_OFFSET		0x0084
- + #define AM33XX_CM_DIV_M5_DPLL_CORE			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0084)
- + #define AM33XX_CM_CLKMODE_DPLL_MPU_OFFSET		0x0088
- + #define AM33XX_CM_CLKMODE_DPLL_MPU			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0088)
- + #define AM33XX_CM_CLKMODE_DPLL_PER_OFFSET		0x008c
- + #define AM33XX_CM_CLKMODE_DPLL_PER			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x008c)
- + #define AM33XX_CM_CLKMODE_DPLL_CORE_OFFSET		0x0090
- + #define AM33XX_CM_CLKMODE_DPLL_CORE			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0090)
- + #define AM33XX_CM_CLKMODE_DPLL_DDR_OFFSET		0x0094
- + #define AM33XX_CM_CLKMODE_DPLL_DDR			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0094)
- + #define AM33XX_CM_CLKMODE_DPLL_DISP_OFFSET		0x0098
- + #define AM33XX_CM_CLKMODE_DPLL_DISP			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0098)
- + #define AM33XX_CM_CLKSEL_DPLL_PERIPH_OFFSET		0x009c
- + #define AM33XX_CM_CLKSEL_DPLL_PERIPH			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x009c)
- + #define AM33XX_CM_DIV_M2_DPLL_DDR_OFFSET		0x00a0
- + #define AM33XX_CM_DIV_M2_DPLL_DDR			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a0)
- + #define AM33XX_CM_DIV_M2_DPLL_DISP_OFFSET		0x00a4
- + #define AM33XX_CM_DIV_M2_DPLL_DISP			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a4)
- + #define AM33XX_CM_DIV_M2_DPLL_MPU_OFFSET		0x00a8
- + #define AM33XX_CM_DIV_M2_DPLL_MPU			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a8)
- + #define AM33XX_CM_DIV_M2_DPLL_PER_OFFSET		0x00ac
- + #define AM33XX_CM_DIV_M2_DPLL_PER			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00ac)
- + #define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET		0x00b0
- + #define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b0)
- + #define AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET		0x00b4
- + #define AM33XX_CM_WKUP_UART0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b4)
- + #define AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET		0x00b8
- + #define AM33XX_CM_WKUP_I2C0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b8)
- + #define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET		0x00bc
- + #define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00bc)
- + #define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET	0x00c0
- + #define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c0)
- + #define AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET		0x00c4
- + #define AM33XX_CM_WKUP_TIMER1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c4)
- + #define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET	0x00c8
- + #define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c8)
- + #define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET		0x00cc
- + #define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00cc)
- + #define AM33XX_CM_WKUP_WDT0_CLKCTRL_OFFSET		0x00d0
- + #define AM33XX_CM_WKUP_WDT0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d0)
- + #define AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET		0x00d4
- + #define AM33XX_CM_WKUP_WDT1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d4)
- + #define AM33XX_CM_DIV_M6_DPLL_CORE_OFFSET		0x00d8
- + #define AM33XX_CM_DIV_M6_DPLL_CORE			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d8)
- + 
- + /* CM.DPLL_CM register offsets */
- + #define AM33XX_CLKSEL_TIMER7_CLK_OFFSET			0x0004
- + #define AM33XX_CLKSEL_TIMER7_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0004)
- + #define AM33XX_CLKSEL_TIMER2_CLK_OFFSET			0x0008
- + #define AM33XX_CLKSEL_TIMER2_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0008)
- + #define AM33XX_CLKSEL_TIMER3_CLK_OFFSET			0x000c
- + #define AM33XX_CLKSEL_TIMER3_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x000c)
- + #define AM33XX_CLKSEL_TIMER4_CLK_OFFSET			0x0010
- + #define AM33XX_CLKSEL_TIMER4_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0010)
- + #define AM33XX_CM_MAC_CLKSEL_OFFSET			0x0014
- + #define AM33XX_CM_MAC_CLKSEL				AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0014)
- + #define AM33XX_CLKSEL_TIMER5_CLK_OFFSET			0x0018
- + #define AM33XX_CLKSEL_TIMER5_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0018)
- + #define AM33XX_CLKSEL_TIMER6_CLK_OFFSET			0x001c
- + #define AM33XX_CLKSEL_TIMER6_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x001c)
- + #define AM33XX_CM_CPTS_RFT_CLKSEL_OFFSET		0x0020
- + #define AM33XX_CM_CPTS_RFT_CLKSEL			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0020)
- + #define AM33XX_CLKSEL_TIMER1MS_CLK_OFFSET		0x0028
- + #define AM33XX_CLKSEL_TIMER1MS_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0028)
- + #define AM33XX_CLKSEL_GFX_FCLK_OFFSET			0x002c
- + #define AM33XX_CLKSEL_GFX_FCLK				AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x002c)
- + #define AM33XX_CLKSEL_PRUSS_OCP_CLK_OFFSET		0x0030
- + #define AM33XX_CLKSEL_PRUSS_OCP_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0030)
- + #define AM33XX_CLKSEL_LCDC_PIXEL_CLK_OFFSET		0x0034
- + #define AM33XX_CLKSEL_LCDC_PIXEL_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0034)
- + #define AM33XX_CLKSEL_WDT1_CLK_OFFSET			0x0038
- + #define AM33XX_CLKSEL_WDT1_CLK				AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0038)
- + #define AM33XX_CLKSEL_GPIO0_DBCLK_OFFSET		0x003c
- + #define AM33XX_CLKSEL_GPIO0_DBCLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x003c)
- + 
- + /* CM.MPU_CM register offsets */
- + #define AM33XX_CM_MPU_CLKSTCTRL_OFFSET			0x0000
- + #define AM33XX_CM_MPU_CLKSTCTRL				AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0000)
- + #define AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET		0x0004
- + #define AM33XX_CM_MPU_MPU_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0004)
- + 
- + /* CM.DEVICE_CM register offsets */
- + #define AM33XX_CM_CLKOUT_CTRL_OFFSET			0x0000
- + #define AM33XX_CM_CLKOUT_CTRL				AM33XX_CM_REGADDR(AM33XX_CM_DEVICE_MOD, 0x0000)
- + 
- + /* CM.RTC_CM register offsets */
- + #define AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET		0x0000
- + #define AM33XX_CM_RTC_RTC_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0000)
- + #define AM33XX_CM_RTC_CLKSTCTRL_OFFSET			0x0004
- + #define AM33XX_CM_RTC_CLKSTCTRL				AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0004)
- + 
- + /* CM.GFX_CM register offsets */
- + #define AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET		0x0000
- + #define AM33XX_CM_GFX_L3_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0000)
- + #define AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET		0x0004
- + #define AM33XX_CM_GFX_GFX_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0004)
- + #define AM33XX_CM_GFX_BITBLT_CLKCTRL_OFFSET		0x0008
- + #define AM33XX_CM_GFX_BITBLT_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0008)
- + #define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET	0x000c
- + #define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1		AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x000c)
- + #define AM33XX_CM_GFX_MMUCFG_CLKCTRL_OFFSET		0x0010
- + #define AM33XX_CM_GFX_MMUCFG_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0010)
- + #define AM33XX_CM_GFX_MMUDATA_CLKCTRL_OFFSET		0x0014
- + #define AM33XX_CM_GFX_MMUDATA_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0014)
- + 
- + /* CM.CEFUSE_CM register offsets */
- + #define AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET		0x0000
- + #define AM33XX_CM_CEFUSE_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0000)
- + #define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET		0x0020
- + #define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0020)
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/cm44xx.h linux-3.2.1/arch/arm/mach-ckb_3352/cm44xx.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/cm44xx.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/cm44xx.h	2014-05-15 13:25:13.878817899 +0900
- ***************
- *** 0 ****
- --- 1,26 ----
- + /*
- +  * OMAP4 Clock Management (CM) definitions
- +  *
- +  * Copyright (C) 2007-2011 Texas Instruments, Inc.
- +  * Copyright (C) 2007-2009 Nokia Corporation
- +  *
- +  * Written by Paul Walmsley
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  *
- +  * OMAP4 has two separate CM blocks, CM1 and CM2.  This file contains
- +  * macros and function prototypes that are applicable to both.
- +  */
- + #ifndef __ARCH_ASM_MACH_OMAP2_CM44XX_H
- + #define __ARCH_ASM_MACH_OMAP2_CM44XX_H
- + 
- + 
- + #include "prcm-common.h"
- + #include "cm.h"
- + 
- + #define OMAP4_CM_CLKSTCTRL				0x0000
- + #define OMAP4_CM_STATICDEP				0x0004
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/cm.h linux-3.2.1/arch/arm/mach-ckb_3352/cm.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/cm.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/cm.h	2014-05-15 13:25:13.882860630 +0900
- ***************
- *** 0 ****
- --- 1,25 ----
- + /*
- +  * OMAP2+ Clock Management prototypes
- +  *
- +  * Copyright (C) 2007-2009 Texas Instruments, Inc.
- +  * Copyright (C) 2007-2009 Nokia Corporation
- +  *
- +  * Written by Paul Walmsley
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + #ifndef __ARCH_ASM_MACH_OMAP2_CM_H
- + #define __ARCH_ASM_MACH_OMAP2_CM_H
- + 
- + /*
- +  * MAX_MODULE_READY_TIME: max duration in microseconds to wait for the
- +  * PRCM to request that a module exit the inactive state in the case of
- +  * OMAP2 & 3.
- +  * In the case of OMAP4 this is the max duration in microseconds for the
- +  * module to reach the functionnal state from an inactive state.
- +  */
- + #define MAX_MODULE_READY_TIME		2000
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/cminst33xx.h linux-3.2.1/arch/arm/mach-ckb_3352/cminst33xx.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/cminst33xx.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/cminst33xx.h	2014-05-15 13:25:13.882860630 +0900
- ***************
- *** 0 ****
- --- 1,63 ----
- + /*
- +  * am33xx Clock Management (CM) function prototypes
- +  *
- +  * Copyright (C) 2010 Nokia Corporation
- +  * Paul Walmsley
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + #ifndef __ARCH_ASM_MACH_OMAP2_CMINST33XX_H
- + #define __ARCH_ASM_MACH_OMAP2_CMINST33XX_H
- + 
- + extern bool am33xx_cminst_is_clkdm_in_hwsup(s16 inst, u16 cdoffs);
- + extern void am33xx_cminst_clkdm_enable_hwsup(s16 inst, u16 cdoffs);
- + extern void am33xx_cminst_clkdm_disable_hwsup(s16 inst, u16 cdoffs);
- + extern void am33xx_cminst_clkdm_force_sleep(s16 inst, u16 cdoffs);
- + extern void am33xx_cminst_clkdm_force_wakeup(s16 inst, u16 cdoffs);
- + 
- + extern int am33xx_cminst_wait_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs);
- + 
- + #ifdef CONFIG_SOC_OMAPAM33XX
- + extern int am33xx_cminst_wait_module_idle(u16 inst, s16 cdoffs,
- + 					 u16 clkctrl_offs);
- + 
- + extern void am33xx_cminst_module_enable(u8 mode, u16 inst, s16 cdoffs,
- + 				       u16 clkctrl_offs);
- + extern void am33xx_cminst_module_disable(u16 inst, s16 cdoffs,
- + 					u16 clkctrl_offs);
- + 
- + #else
- + 
- + static inline int am33xx_cminst_wait_module_idle(u16 inst, s16 cdoffs,
- + 					u16 clkctrl_offs)
- + {
- + 	return 0;
- + }
- + 
- + static inline void am33xx_cminst_module_enable(u8 mode, u16 inst,
- + 				s16 cdoffs, u16 clkctrl_offs)
- + {
- + }
- + 
- + static inline void am33xx_cminst_module_disable(u16 inst, s16 cdoffs,
- + 				 u16 clkctrl_offs)
- + {
- + }
- + 
- + #endif
- + 
- + /*
- +  * In an ideal world, we would not export these low-level functions,
- +  * but this will probably take some time to fix properly
- +  */
- + extern u32 am33xx_cminst_read_inst_reg(s16 inst, u16 idx);
- + extern void am33xx_cminst_write_inst_reg(u32 val, s16 inst, u16 idx);
- + extern u32 am33xx_cminst_rmw_inst_reg_bits(u32 mask, u32 bits,
- + 					   s16 inst, s16 idx);
- + extern u32 am33xx_cminst_set_inst_reg_bits(u32 bits, s16 inst, s16 idx);
- + extern u32 am33xx_cminst_clear_inst_reg_bits(u32 bits, s16 inst, s16 idx);
- + extern u32 am33xx_cminst_read_inst_reg_bits(u16 inst, s16 idx, u32 mask);
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/cminst44xx.c linux-3.2.1/arch/arm/mach-ckb_3352/cminst44xx.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/cminst44xx.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/cminst44xx.c	2014-05-15 13:25:13.882860630 +0900
- ***************
- *** 0 ****
- --- 1,317 ----
- + /*
- +  * OMAP4 CM instance functions
- +  *
- +  * Copyright (C) 2009 Nokia Corporation
- +  * Copyright (C) 2011 Texas Instruments, Inc.
- +  * Paul Walmsley
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  *
- +  * This is needed since CM instances can be in the PRM, PRCM_MPU, CM1,
- +  * or CM2 hardware modules.  For example, the EMU_CM CM instance is in
- +  * the PRM hardware module.  What a mess...
- +  */
- + 
- + #include <linux/kernel.h>
- + #include <linux/types.h>
- + #include <linux/errno.h>
- + #include <linux/err.h>
- + #include <linux/io.h>
- + 
- + #include "common.h"
- + 
- + #include "cm.h"
- + #include "cm44xx.h"
- + #include "cminst44xx.h"
- + #include "cm-regbits-34xx.h"
- + #include "cm-regbits-44xx.h"
- + #include "prcm44xx.h"
- + //#include "prm44xx.h"
- + #include "prm33xx.h"
- + 
- + /*
- +  * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield:
- +  *
- +  *   0x0 func:     Module is fully functional, including OCP
- +  *   0x1 trans:    Module is performing transition: wakeup, or sleep, or sleep
- +  *                 abortion
- +  *   0x2 idle:     Module is in Idle mode (only OCP part). It is functional if
- +  *                 using separate functional clock
- +  *   0x3 disabled: Module is disabled and cannot be accessed
- +  *
- +  */
- + #define CLKCTRL_IDLEST_FUNCTIONAL		0x0
- + #define CLKCTRL_IDLEST_INTRANSITION		0x1
- + #define CLKCTRL_IDLEST_INTERFACE_IDLE		0x2
- + #define CLKCTRL_IDLEST_DISABLED			0x3
- + 
- + static u32 **_cm_bases;
- + static u32 max_cm_partitions;
- + 
- + static u32 *am33xx_cm_bases[] = {
- + 	[OMAP4430_INVALID_PRCM_PARTITION]	= 0,
- + 	[AM33XX_PRM_PARTITION]			= AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRM_BASE),
- + };
- + 
- + /* Private functions */
- + 
- + /**
- +  * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield
- +  * @part: PRCM partition ID that the CM_CLKCTRL register exists in
- +  * @inst: CM instance register offset (*_INST macro)
- +  * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
- +  * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
- +  *
- +  * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to
- +  * bit 0.
- +  */
- + static u32 _clkctrl_idlest(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
- + {
- + 	u32 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
- + 	v &= OMAP4430_IDLEST_MASK;
- + 	v >>= OMAP4430_IDLEST_SHIFT;
- + 	return v;
- + }
- + 
- + /**
- +  * _is_module_ready - can module registers be accessed without causing an abort?
- +  * @part: PRCM partition ID that the CM_CLKCTRL register exists in
- +  * @inst: CM instance register offset (*_INST macro)
- +  * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
- +  * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
- +  *
- +  * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either
- +  * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise.
- +  */
- + static bool _is_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
- + {
- + 	u32 v;
- + 
- + 	v = _clkctrl_idlest(part, inst, cdoffs, clkctrl_offs);
- + 
- + 	return (v == CLKCTRL_IDLEST_FUNCTIONAL ||
- + 		v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false;
- + }
- + 
- + /* Public functions */
- + 
- + /* Read a register in a CM instance */
- + u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx)
- + {
- + 	BUG_ON(part >= max_cm_partitions ||
- + 	       part == OMAP4430_INVALID_PRCM_PARTITION ||
- + 	       !_cm_bases[part]);
- + 	return __raw_readl(_cm_bases[part] + ((inst + idx)/sizeof(u32)));
- + }
- + 
- + /* Write into a register in a CM instance */
- + void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
- + {
- + 	BUG_ON(part >= max_cm_partitions ||
- + 	       part == OMAP4430_INVALID_PRCM_PARTITION ||
- + 	       !_cm_bases[part]);
- + 	__raw_writel(val, _cm_bases[part] + ((inst + idx)/sizeof(u32)));
- + }
- + 
- + 
- + /*
- +  *
- +  */
- + 
- + /**
- +  * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield
- +  * @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted)
- +  * @part: PRCM partition ID that the CM_CLKSTCTRL register exists in
- +  * @inst: CM instance register offset (*_INST macro)
- +  * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
- +  *
- +  * @c must be the unshifted value for CLKTRCTRL - i.e., this function
- +  * will handle the shift itself.
- +  */
- + static void _clktrctrl_write(u8 c, u8 part, s16 inst, u16 cdoffs)
- + {
- + 	u32 v;
- + 
- + 	v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL);
- + 	v &= ~OMAP4430_CLKTRCTRL_MASK;
- + 	v |= c << OMAP4430_CLKTRCTRL_SHIFT;
- + 	omap4_cminst_write_inst_reg(v, part, inst, cdoffs + OMAP4_CM_CLKSTCTRL);
- + }
- + 
- + /**
- +  * omap4_cminst_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode?
- +  * @part: PRCM partition ID that the CM_CLKSTCTRL register exists in
- +  * @inst: CM instance register offset (*_INST macro)
- +  * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
- +  *
- +  * Returns true if the clockdomain referred to by (@part, @inst, @cdoffs)
- +  * is in hardware-supervised idle mode, or 0 otherwise.
- +  */
- + bool omap4_cminst_is_clkdm_in_hwsup(u8 part, s16 inst, u16 cdoffs)
- + {
- + 	u32 v;
- + 
- + 	v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL);
- + 	v &= OMAP4430_CLKTRCTRL_MASK;
- + 	v >>= OMAP4430_CLKTRCTRL_SHIFT;
- + 
- + 	return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false;
- + }
- + 
- + /**
- +  * omap4_cminst_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode
- +  * @part: PRCM partition ID that the clockdomain registers exist in
- +  * @inst: CM instance register offset (*_INST macro)
- +  * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
- +  *
- +  * Put a clockdomain referred to by (@part, @inst, @cdoffs) into
- +  * hardware-supervised idle mode.  No return value.
- +  */
- + void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs)
- + {
- + 	_clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, part, inst, cdoffs);
- + }
- + 
- + /**
- +  * omap4_cminst_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode
- +  * @part: PRCM partition ID that the clockdomain registers exist in
- +  * @inst: CM instance register offset (*_INST macro)
- +  * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
- +  *
- +  * Put a clockdomain referred to by (@part, @inst, @cdoffs) into
- +  * software-supervised idle mode, i.e., controlled manually by the
- +  * Linux OMAP clockdomain code.  No return value.
- +  */
- + void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs)
- + {
- + 	_clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, part, inst, cdoffs);
- + }
- + 
- + /**
- +  * omap4_cminst_clkdm_force_sleep - try to put a clockdomain into idle
- +  * @part: PRCM partition ID that the clockdomain registers exist in
- +  * @inst: CM instance register offset (*_INST macro)
- +  * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
- +  *
- +  * Put a clockdomain referred to by (@part, @inst, @cdoffs) into idle
- +  * No return value.
- +  */
- + void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs)
- + {
- + 	_clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, part, inst, cdoffs);
- + }
- + 
- + /**
- +  * omap4_cminst_clkdm_force_sleep - try to take a clockdomain out of idle
- +  * @part: PRCM partition ID that the clockdomain registers exist in
- +  * @inst: CM instance register offset (*_INST macro)
- +  * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
- +  *
- +  * Take a clockdomain referred to by (@part, @inst, @cdoffs) out of idle,
- +  * waking it up.  No return value.
- +  */
- + void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs)
- + {
- + 	_clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs);
- + }
- + 
- + /*
- +  *
- +  */
- + 
- + /**
- +  * omap4_cminst_wait_module_ready - wait for a module to be in 'func' state
- +  * @part: PRCM partition ID that the CM_CLKCTRL register exists in
- +  * @inst: CM instance register offset (*_INST macro)
- +  * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
- +  * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
- +  *
- +  * Wait for the module IDLEST to be functional. If the idle state is in any
- +  * the non functional state (trans, idle or disabled), module and thus the
- +  * sysconfig cannot be accessed and will probably lead to an "imprecise
- +  * external abort"
- +  */
- + int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs,
- + 				   u16 clkctrl_offs)
- + {
- + 	int i = 0;
- + 
- + 	omap_test_timeout(_is_module_ready(part, inst, cdoffs, clkctrl_offs),
- + 			  MAX_MODULE_READY_TIME, i);
- + 
- + 	return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
- + }
- + 
- + /**
- +  * omap4_cminst_wait_module_idle - wait for a module to be in 'disabled'
- +  * state
- +  * @part: PRCM partition ID that the CM_CLKCTRL register exists in
- +  * @inst: CM instance register offset (*_INST macro)
- +  * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
- +  * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
- +  *
- +  * Wait for the module IDLEST to be disabled. Some PRCM transition,
- +  * like reset assertion or parent clock de-activation must wait the
- +  * module to be fully disabled.
- +  */
- + int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
- + {
- + 	int i = 0;
- + 
- + 	if (!clkctrl_offs)
- + 		return 0;
- + 
- + 	omap_test_timeout((_clkctrl_idlest(part, inst, cdoffs, clkctrl_offs) ==
- + 			   CLKCTRL_IDLEST_DISABLED),
- + 			  MAX_MODULE_READY_TIME, i);
- + 
- + 	return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
- + }
- + 
- + /**
- +  * omap4_cminst_module_enable - Enable the modulemode inside CLKCTRL
- +  * @mode: Module mode (SW or HW)
- +  * @part: PRCM partition ID that the CM_CLKCTRL register exists in
- +  * @inst: CM instance register offset (*_INST macro)
- +  * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
- +  * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
- +  *
- +  * No return value.
- +  */
- + void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs,
- + 			    u16 clkctrl_offs)
- + {
- + 	u32 v;
- + 
- + 	v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
- + 	v &= ~OMAP4430_MODULEMODE_MASK;
- + 	v |= mode << OMAP4430_MODULEMODE_SHIFT;
- + 	omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs);
- + }
- + 
- + /**
- +  * omap4_cminst_module_disable - Disable the module inside CLKCTRL
- +  * @part: PRCM partition ID that the CM_CLKCTRL register exists in
- +  * @inst: CM instance register offset (*_INST macro)
- +  * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
- +  * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
- +  *
- +  * No return value.
- +  */
- + void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
- + 			     u16 clkctrl_offs)
- + {
- + 	u32 v;
- + 
- + 	v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
- + 	v &= ~OMAP4430_MODULEMODE_MASK;
- + 	omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs);
- + }
- + 
- + void __init omap44xx_cminst_init(void)
- + {
- + 	_cm_bases = am33xx_cm_bases;
- + 	max_cm_partitions = ARRAY_SIZE(am33xx_cm_bases);
- + }
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/cminst44xx.h linux-3.2.1/arch/arm/mach-ckb_3352/cminst44xx.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/cminst44xx.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/cminst44xx.h	2014-05-15 13:25:13.882860630 +0900
- ***************
- *** 0 ****
- --- 1,39 ----
- + /*
- +  * OMAP4 Clock Management (CM) function prototypes
- +  *
- +  * Copyright (C) 2010 Nokia Corporation
- +  * Paul Walmsley
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + #ifndef __ARCH_ASM_MACH_OMAP2_CMINST44XX_H
- + #define __ARCH_ASM_MACH_OMAP2_CMINST44XX_H
- + 
- + extern bool omap4_cminst_is_clkdm_in_hwsup(u8 part, s16 inst, u16 cdoffs);
- + extern void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs);
- + extern void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs);
- + extern void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs);
- + extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs);
- + 
- + extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
- + 
- + extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs,
- + 					 u16 clkctrl_offs);
- + 
- + extern void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs,
- + 				       u16 clkctrl_offs);
- + extern void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
- + 					u16 clkctrl_offs);
- + 
- + 
- + /*
- +  * In an ideal world, we would not export these low-level functions,
- +  * but this will probably take some time to fix properly
- +  */
- + extern u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx);
- + extern void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx);
- + 
- + extern void __init omap44xx_cminst_init(void);
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/cm-regbits-33xx.h linux-3.2.1/arch/arm/mach-ckb_3352/cm-regbits-33xx.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/cm-regbits-33xx.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/cm-regbits-33xx.h	2014-05-15 13:25:13.887063538 +0900
- ***************
- *** 0 ****
- --- 1,683 ----
- + /*
- +  * AM33XX Power Management register bits
- +  *
- +  * This file is automatically generated from the AM33XX hardware databases.
- +  *
- +  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + 
- + #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
- + #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
- + 
- + /*
- +  * Used by CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_DDR, CM_AUTOIDLE_DPLL_DISP,
- +  * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER
- +  */
- + #define AM33XX_AUTO_DPLL_MODE_SHIFT			0
- + #define AM33XX_AUTO_DPLL_MODE_MASK			(0x7 << 0)
- + 
- + /* Used by CM_WKUP_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT		14
- + #define AM33XX_CLKACTIVITY_ADC_FCLK_MASK		(1 << 16)
- + 
- + /* Used by CM_PER_L4LS_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT		11
- + #define AM33XX_CLKACTIVITY_CAN_CLK_MASK			(1 << 11)
- + 
- + /* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT		4
- + #define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK		(1 << 4)
- + 
- + /* Used by CM_PER_CPSW_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT	4
- + #define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK	(1 << 4)
- + 
- + /* Used by CM_PER_L4HS_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT	4
- + #define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK	(1 << 4)
- + 
- + /* Used by CM_PER_L4HS_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT	5
- + #define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK		(1 << 5)
- + 
- + /* Used by CM_PER_L4HS_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT		6
- + #define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK		(1 << 6)
- + 
- + /* Used by CM_PER_L3_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT		6
- + #define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK		(1 << 6)
- + 
- + /* Used by CM_CEFUSE_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT	9
- + #define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK	(1 << 9)
- + 
- + /* Used by CM_L3_AON_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT		2
- + #define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK		(1 << 2)
- + 
- + /* Used by CM_L3_AON_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT		4
- + #define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK		(1 << 4)
- + 
- + /* Used by CM_PER_L3_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT		2
- + #define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK		(1 << 2)
- + 
- + /* Used by CM_GFX_L3_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT		9
- + #define AM33XX_CLKACTIVITY_GFX_FCLK_MASK		(1 << 9)
- + 
- + /* Used by CM_GFX_L3_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT		8
- + #define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK		(1 << 8)
- + 
- + /* Used by CM_WKUP_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT		8
- + #define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK		(1 << 8)
- + 
- + /* Used by CM_PER_L4LS_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT		19
- + #define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK		(1 << 19)
- + 
- + /* Used by CM_PER_L4LS_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT		20
- + #define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK		(1 << 20)
- + 
- + /* Used by CM_PER_L4LS_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT		21
- + #define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK		(1 << 21)
- + 
- + /* Used by CM_PER_L4LS_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT		22
- + #define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK		(1 << 22)
- + 
- + /* Used by CM_PER_L4LS_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT		26
- + #define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK		(1 << 26)
- + 
- + /* Used by CM_PER_L4LS_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT		18
- + #define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK		(1 << 18)
- + 
- + /* Used by CM_WKUP_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT		11
- + #define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK		(1 << 11)
- + 
- + /* Used by CM_PER_L4LS_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT		24
- + #define AM33XX_CLKACTIVITY_I2C_FCLK_MASK		(1 << 24)
- + 
- + /* Used by CM_PER_PRUSS_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT		5
- + #define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK		(1 << 5)
- + 
- + /* Used by CM_PER_PRUSS_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT		4
- + #define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK		(1 << 4)
- + 
- + /* Used by CM_PER_PRUSS_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT	6
- + #define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK		(1 << 6)
- + 
- + /* Used by CM_PER_L3S_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT		3
- + #define AM33XX_CLKACTIVITY_L3S_GCLK_MASK		(1 << 3)
- + 
- + /* Used by CM_L3_AON_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT		3
- + #define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK		(1 << 3)
- + 
- + /* Used by CM_PER_L3_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT		4
- + #define AM33XX_CLKACTIVITY_L3_GCLK_MASK			(1 << 4)
- + 
- + /* Used by CM_PER_L4FW_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT		8
- + #define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK		(1 << 8)
- + 
- + /* Used by CM_PER_L4HS_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT		3
- + #define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK		(1 << 3)
- + 
- + /* Used by CM_PER_L4LS_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT		8
- + #define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK		(1 << 8)
- + 
- + /* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */
- + #define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT		8
- + #define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK		(1 << 8)
- + 
- + /* Used by CM_CEFUSE_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT	8
- + #define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK		(1 << 8)
- + 
- + /* Used by CM_RTC_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT		8
- + #define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK		(1 << 8)
- + 
- + /* Used by CM_L4_WKUP_AON_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT	2
- + #define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK	(1 << 2)
- + 
- + /* Used by CM_WKUP_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT		2
- + #define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK		(1 << 2)
- + 
- + /* Used by CM_PER_L4LS_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT		17
- + #define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK		(1 << 17)
- + 
- + /* Used by CM_PER_LCDC_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT	4
- + #define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK	(1 << 4)
- + 
- + /* Used by CM_PER_LCDC_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT	5
- + #define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK	(1 << 5)
- + 
- + /* Used by CM_PER_L3_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT		7
- + #define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK		(1 << 7)
- + 
- + /* Used by CM_PER_L3_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT		3
- + #define AM33XX_CLKACTIVITY_MMC_FCLK_MASK		(1 << 3)
- + 
- + /* Used by CM_MPU_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT		2
- + #define AM33XX_CLKACTIVITY_MPU_CLK_MASK			(1 << 2)
- + 
- + /* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT		4
- + #define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK		(1 << 4)
- + 
- + /* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT		5
- + #define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK		(1 << 5)
- + 
- + /* Used by CM_RTC_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT		9
- + #define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK		(1 << 9)
- + 
- + /* Used by CM_PER_L4LS_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT		25
- + #define AM33XX_CLKACTIVITY_SPI_GCLK_MASK		(1 << 25)
- + 
- + /* Used by CM_WKUP_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT		3
- + #define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK		(1 << 3)
- + 
- + /* Used by CM_WKUP_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT		10
- + #define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK		(1 << 10)
- + 
- + /* Used by CM_WKUP_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT		13
- + #define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK		(1 << 13)
- + 
- + /* Used by CM_PER_L4LS_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT		14
- + #define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK		(1 << 14)
- + 
- + /* Used by CM_PER_L4LS_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT		15
- + #define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK		(1 << 15)
- + 
- + /* Used by CM_PER_L4LS_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT		16
- + #define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK		(1 << 16)
- + 
- + /* Used by CM_PER_L4LS_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT		27
- + #define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK		(1 << 27)
- + 
- + /* Used by CM_PER_L4LS_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT		28
- + #define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK		(1 << 28)
- + 
- + /* Used by CM_PER_L4LS_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT		13
- + #define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK		(1 << 13)
- + 
- + /* Used by CM_WKUP_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT		12
- + #define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK		(1 << 12)
- + 
- + /* Used by CM_PER_L4LS_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT		10
- + #define AM33XX_CLKACTIVITY_UART_GFCLK_MASK		(1 << 10)
- + 
- + /* Used by CM_WKUP_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT		9
- + #define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK		(1 << 9)
- + 
- + /* Used by CM_WKUP_CLKSTCTRL */
- + #define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT		4
- + #define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK		(1 << 4)
- + 
- + /* Used by CLKSEL_GFX_FCLK */
- + #define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT		0
- + #define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK			(1 << 0)
- + 
- + /* Used by CM_CLKOUT_CTRL */
- + #define AM33XX_CLKOUT2DIV_SHIFT				3
- + #define AM33XX_CLKOUT2DIV_MASK				(0x05 << 3)
- + 
- + /* Used by CM_CLKOUT_CTRL */
- + #define AM33XX_CLKOUT2EN_SHIFT				7
- + #define AM33XX_CLKOUT2EN_MASK				(1 << 7)
- + 
- + /* Used by CM_CLKOUT_CTRL */
- + #define AM33XX_CLKOUT2SOURCE_SHIFT			0
- + #define AM33XX_CLKOUT2SOURCE_MASK			(0x02 << 0)
- + 
- + /*
- +  * Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK,
- +  * CLKSEL_TIMER3_CLK, CLKSEL_TIMER4_CLK, CLKSEL_TIMER5_CLK, CLKSEL_TIMER6_CLK,
- +  * CLKSEL_TIMER7_CLK
- +  */
- + #define AM33XX_CLKSEL_SHIFT				0
- + #define AM33XX_CLKSEL_MASK				(0x01 << 0)
- + 
- + /*
- +  * Renamed from CLKSEL Used by CLKSEL_PRUSS_OCP_CLK, CLKSEL_WDT1_CLK,
- +  * CM_CPTS_RFT_CLKSEL
- +  */
- + #define AM33XX_CLKSEL_0_0_SHIFT				0
- + #define AM33XX_CLKSEL_0_0_MASK				(1 << 0)
- + 
- + #define AM33XX_CLKSEL_0_1_SHIFT				0
- + #define AM33XX_CLKSEL_0_1_MASK				(3 << 0)
- + 
- + /* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */
- + #define AM33XX_CLKSEL_0_2_SHIFT				0
- + #define AM33XX_CLKSEL_0_2_MASK				(7 << 0)
- + 
- + /* Used by CLKSEL_GFX_FCLK */
- + #define AM33XX_CLKSEL_GFX_FCLK_SHIFT			1
- + #define AM33XX_CLKSEL_GFX_FCLK_MASK			(1 << 1)
- + 
- + /*
- +  * Used by CM_MPU_CLKSTCTRL, CM_RTC_CLKSTCTRL, CM_PER_CLK_24MHZ_CLKSTCTRL,
- +  * CM_PER_CPSW_CLKSTCTRL, CM_PER_PRUSS_CLKSTCTRL, CM_PER_L3S_CLKSTCTRL,
- +  * CM_PER_L3_CLKSTCTRL, CM_PER_L4FW_CLKSTCTRL, CM_PER_L4HS_CLKSTCTRL,
- +  * CM_PER_L4LS_CLKSTCTRL, CM_PER_LCDC_CLKSTCTRL, CM_PER_OCPWP_L3_CLKSTCTRL,
- +  * CM_L3_AON_CLKSTCTRL, CM_L4_WKUP_AON_CLKSTCTRL, CM_WKUP_CLKSTCTRL,
- +  * CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL
- +  */
- + #define AM33XX_CLKTRCTRL_SHIFT				0
- + #define AM33XX_CLKTRCTRL_MASK				(0x3 << 0)
- + 
- + /*
- +  * Used by CM_SSC_DELTAMSTEP_DPLL_CORE, CM_SSC_DELTAMSTEP_DPLL_DDR,
- +  * CM_SSC_DELTAMSTEP_DPLL_DISP, CM_SSC_DELTAMSTEP_DPLL_MPU,
- +  * CM_SSC_DELTAMSTEP_DPLL_PER
- +  */
- + #define AM33XX_DELTAMSTEP_SHIFT				0
- + #define AM33XX_DELTAMSTEP_MASK				(0x19 << 0)
- + 
- + /* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */
- + #define AM33XX_DPLL_BYP_CLKSEL_SHIFT			23
- + #define AM33XX_DPLL_BYP_CLKSEL_MASK			(1 << 23)
- + 
- + /* Used by CM_CLKDCOLDO_DPLL_PER */
- + #define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT		8
- + #define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK		(1 << 8)
- + 
- + /* Used by CM_CLKDCOLDO_DPLL_PER */
- + #define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT		12
- + #define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK			(1 << 12)
- + 
- + /* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
- + #define AM33XX_DPLL_CLKOUT_DIV_SHIFT			0
- + #define AM33XX_DPLL_CLKOUT_DIV_MASK			(0x1f << 0)
- + 
- + /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */
- + #define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT		0
- + #define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK			(0x06 << 0)
- + 
- + /* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
- + #define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT		5
- + #define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK		(1 << 5)
- + 
- + /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */
- + #define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT	7
- + #define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK		(1 << 7)
- + 
- + /*
- +  * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU,
- +  * CM_DIV_M2_DPLL_PER
- +  */
- + #define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT		8
- + #define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK		(1 << 8)
- + 
- + /*
- +  * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP,
- +  * CM_CLKSEL_DPLL_MPU
- +  */
- + #define AM33XX_DPLL_DIV_SHIFT				0
- + #define AM33XX_DPLL_DIV_MASK				(0x7f << 0)
- + 
- + #define AM33XX_DPLL_PER_DIV_MASK			(0xff << 0)
- + 
- + /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */
- + #define AM33XX_DPLL_DIV_0_7_SHIFT			0
- + #define AM33XX_DPLL_DIV_0_7_MASK			(0x07 << 0)
- + 
- + /*
- +  * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
- +  * CM_CLKMODE_DPLL_MPU
- +  */
- + #define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT			8
- + #define AM33XX_DPLL_DRIFTGUARD_EN_MASK			(1 << 8)
- + 
- + /*
- +  * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
- +  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
- +  */
- + #define AM33XX_DPLL_EN_SHIFT				0
- + #define AM33XX_DPLL_EN_MASK				(0x7 << 0)
- + 
- + /*
- +  * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
- +  * CM_CLKMODE_DPLL_MPU
- +  */
- + #define AM33XX_DPLL_LPMODE_EN_SHIFT			10
- + #define AM33XX_DPLL_LPMODE_EN_MASK			(1 << 10)
- + 
- + /*
- +  * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP,
- +  * CM_CLKSEL_DPLL_MPU
- +  */
- + #define AM33XX_DPLL_MULT_SHIFT				8
- + #define AM33XX_DPLL_MULT_MASK				(0x7ff << 8)
- + 
- + /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */
- + #define AM33XX_DPLL_MULT_PERIPH_SHIFT			8
- + #define AM33XX_DPLL_MULT_PERIPH_MASK			(0xfff << 8)
- + 
- + /*
- +  * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
- +  * CM_CLKMODE_DPLL_MPU
- +  */
- + #define AM33XX_DPLL_REGM4XEN_SHIFT			11
- + #define AM33XX_DPLL_REGM4XEN_MASK			(1 << 11)
- + 
- + /* Used by CM_CLKSEL_DPLL_PERIPH */
- + #define AM33XX_DPLL_SD_DIV_SHIFT			24
- + #define AM33XX_DPLL_SD_DIV_MASK				(24, 31)
- + 
- + /*
- +  * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
- +  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
- +  */
- + #define AM33XX_DPLL_SSC_ACK_SHIFT			13
- + #define AM33XX_DPLL_SSC_ACK_MASK			(1 << 13)
- + 
- + /*
- +  * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
- +  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
- +  */
- + #define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT		14
- + #define AM33XX_DPLL_SSC_DOWNSPREAD_MASK			(1 << 14)
- + 
- + /*
- +  * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
- +  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
- +  */
- + #define AM33XX_DPLL_SSC_EN_SHIFT			12
- + #define AM33XX_DPLL_SSC_EN_MASK				(1 << 12)
- + 
- + /* Used by CM_DIV_M4_DPLL_CORE */
- + #define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT		0
- + #define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK		(0x1f << 0)
- + 
- + /* Used by CM_DIV_M4_DPLL_CORE */
- + #define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT		5
- + #define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK		(1 << 5)
- + 
- + /* Used by CM_DIV_M4_DPLL_CORE */
- + #define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT	8
- + #define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK		(1 << 8)
- + 
- + /* Used by CM_DIV_M4_DPLL_CORE */
- + #define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT		12
- + #define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK		(1 << 12)
- + 
- + /* Used by CM_DIV_M5_DPLL_CORE */
- + #define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT		0
- + #define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK		(0x1f << 0)
- + 
- + /* Used by CM_DIV_M5_DPLL_CORE */
- + #define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT		5
- + #define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK		(1 << 5)
- + 
- + /* Used by CM_DIV_M5_DPLL_CORE */
- + #define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT	8
- + #define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK		(1 << 8)
- + 
- + /* Used by CM_DIV_M5_DPLL_CORE */
- + #define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT		12
- + #define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK		(1 << 12)
- + 
- + /* Used by CM_DIV_M6_DPLL_CORE */
- + #define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT		0
- + #define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK		(0x04 << 0)
- + 
- + /* Used by CM_DIV_M6_DPLL_CORE */
- + #define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT		5
- + #define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK		(1 << 5)
- + 
- + /* Used by CM_DIV_M6_DPLL_CORE */
- + #define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT	8
- + #define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK		(1 << 8)
- + 
- + /* Used by CM_DIV_M6_DPLL_CORE */
- + #define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT		12
- + #define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK		(1 << 12)
- + 
- + /*
- +  * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
- +  * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL,
- +  * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL,
- +  * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL,
- +  * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL,
- +  * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL,
- +  * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL,
- +  * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL,
- +  * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL,
- +  * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL,
- +  * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL,
- +  * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL,
- +  * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL,
- +  * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL,
- +  * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
- +  * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL,
- +  * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL,
- +  * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL,
- +  * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL,
- +  * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL,
- +  * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL,
- +  * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
- +  * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL,
- +  * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL,
- +  * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL,
- +  * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL,
- +  * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL,
- +  * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL,
- +  * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL,
- +  * CM_WKUP_WDT1_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL,
- +  * CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL
- +  */
- + #define AM33XX_IDLEST_SHIFT				16
- + #define AM33XX_IDLEST_MASK				(0x3 << 16)
- + #define AM33XX_IDLEST_VAL				0x3
- + 
- + /* Used by CM_MAC_CLKSEL */
- + #define AM33XX_MII_CLK_SEL_SHIFT			2
- + #define AM33XX_MII_CLK_SEL_MASK				(1 << 2)
- + 
- + /*
- +  * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
- +  * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU,
- +  * CM_SSC_MODFREQDIV_DPLL_PER
- +  */
- + #define AM33XX_MODFREQDIV_EXPONENT_SHIFT		8
- + #define AM33XX_MODFREQDIV_EXPONENT_MASK			(0x10 << 8)
- + 
- + /*
- +  * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
- +  * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU,
- +  * CM_SSC_MODFREQDIV_DPLL_PER
- +  */
- + #define AM33XX_MODFREQDIV_MANTISSA_SHIFT		0
- + #define AM33XX_MODFREQDIV_MANTISSA_MASK			(0x06 << 0)
- + 
- + /*
- +  * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
- +  * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL,
- +  * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL,
- +  * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL,
- +  * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL,
- +  * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL,
- +  * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL,
- +  * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL,
- +  * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL,
- +  * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL,
- +  * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL,
- +  * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL,
- +  * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL,
- +  * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL,
- +  * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
- +  * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL,
- +  * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL,
- +  * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL,
- +  * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL,
- +  * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL,
- +  * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL,
- +  * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
- +  * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL,
- +  * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL,
- +  * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL,
- +  * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL,
- +  * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL,
- +  * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL,
- +  * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL,
- +  * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL,
- +  * CM_GFX_GFX_CLKCTRL, CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL,
- +  * CM_CEFUSE_CEFUSE_CLKCTRL
- +  */
- + #define AM33XX_MODULEMODE_SHIFT				0
- + #define AM33XX_MODULEMODE_MASK				(0x3 << 0)
- + 
- + /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
- + #define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT			30
- + #define AM33XX_OPTCLK_DEBUG_CLKA_MASK			(1 << 30)
- + 
- + /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
- + #define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT		19
- + #define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK			(1 << 19)
- + 
- + /* Used by CM_WKUP_GPIO0_CLKCTRL */
- + #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT		18
- + #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK		(1 << 18)
- + 
- + /* Used by CM_PER_GPIO1_CLKCTRL */
- + #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT		18
- + #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK		(1 << 18)
- + 
- + /* Used by CM_PER_GPIO2_CLKCTRL */
- + #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT		18
- + #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK		(1 << 18)
- + 
- + /* Used by CM_PER_GPIO3_CLKCTRL */
- + #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT		18
- + #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK		(1 << 18)
- + 
- + /* Used by CM_PER_GPIO4_CLKCTRL */
- + #define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT		18
- + #define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK		(1 << 18)
- + 
- + /* Used by CM_PER_GPIO5_CLKCTRL */
- + #define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT		18
- + #define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK		(1 << 18)
- + 
- + /* Used by CM_PER_GPIO6_CLKCTRL */
- + #define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT		18
- + #define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK		(1 << 18)
- + 
- + /*
- +  * Used by CM_MPU_MPU_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, CM_PER_PRUSS_CLKCTRL,
- +  * CM_PER_IEEE5000_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MLB_CLKCTRL,
- +  * CM_PER_MSTR_EXPS_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
- +  * CM_PER_SPARE_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
- +  * CM_PER_TPTC2_CLKCTRL, CM_PER_USB0_CLKCTRL, CM_WKUP_DEBUGSS_CLKCTRL,
- +  * CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL
- +  */
- + #define AM33XX_STBYST_SHIFT				18
- + #define AM33XX_STBYST_MASK				(1 << 18)
- + 
- + /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
- + #define AM33XX_STM_PMD_CLKDIVSEL_SHIFT			27
- + #define AM33XX_STM_PMD_CLKDIVSEL_MASK			(0x29 << 27)
- + 
- + /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
- + #define AM33XX_STM_PMD_CLKSEL_SHIFT			22
- + #define AM33XX_STM_PMD_CLKSEL_MASK			(0x23 << 22)
- + 
- + /*
- +  * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
- +  * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
- +  */
- + #define AM33XX_ST_DPLL_CLK_SHIFT			0
- + #define AM33XX_ST_DPLL_CLK_MASK				(1 << 0)
- + 
- + /* Used by CM_CLKDCOLDO_DPLL_PER */
- + #define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT			8
- + #define AM33XX_ST_DPLL_CLKDCOLDO_MASK			(1 << 8)
- + 
- + /*
- +  * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU,
- +  * CM_DIV_M2_DPLL_PER
- +  */
- + #define AM33XX_ST_DPLL_CLKOUT_SHIFT			9
- + #define AM33XX_ST_DPLL_CLKOUT_MASK			(1 << 9)
- + 
- + /* Used by CM_DIV_M4_DPLL_CORE */
- + #define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT		9
- + #define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK		(1 << 9)
- + 
- + /* Used by CM_DIV_M5_DPLL_CORE */
- + #define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT		9
- + #define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK		(1 << 9)
- + 
- + /* Used by CM_DIV_M6_DPLL_CORE */
- + #define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT		9
- + #define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK		(1 << 9)
- + 
- + /*
- +  * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
- +  * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
- +  */
- + #define AM33XX_ST_MN_BYPASS_SHIFT			8
- + #define AM33XX_ST_MN_BYPASS_MASK			(1 << 8)
- + 
- + /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
- + #define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT			24
- + #define AM33XX_TRC_PMD_CLKDIVSEL_MASK			(0x26 << 24)
- + 
- + /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
- + #define AM33XX_TRC_PMD_CLKSEL_SHIFT			20
- + #define AM33XX_TRC_PMD_CLKSEL_MASK			(0x21 << 20)
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/cm-regbits-34xx.h linux-3.2.1/arch/arm/mach-ckb_3352/cm-regbits-34xx.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/cm-regbits-34xx.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/cm-regbits-34xx.h	2014-05-15 13:25:13.887063538 +0900
- ***************
- *** 0 ****
- --- 1,812 ----
- + #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
- + #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
- + 
- + /*
- +  * OMAP3430 Clock Management register bits
- +  *
- +  * Copyright (C) 2007-2008 Texas Instruments, Inc.
- +  * Copyright (C) 2007-2008 Nokia Corporation
- +  *
- +  * Written by Paul Walmsley
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + /* Bits shared between registers */
- + 
- + /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
- + #define OMAP3430ES2_EN_MMC3_MASK			(1 << 30)
- + #define OMAP3430ES2_EN_MMC3_SHIFT			30
- + #define OMAP3430_EN_MSPRO_MASK				(1 << 23)
- + #define OMAP3430_EN_MSPRO_SHIFT				23
- + #define OMAP3430_EN_HDQ_MASK				(1 << 22)
- + #define OMAP3430_EN_HDQ_SHIFT				22
- + #define OMAP3430ES1_EN_FSHOSTUSB_MASK			(1 << 5)
- + #define OMAP3430ES1_EN_FSHOSTUSB_SHIFT			5
- + #define OMAP3430ES1_EN_D2D_MASK				(1 << 3)
- + #define OMAP3430ES1_EN_D2D_SHIFT			3
- + #define OMAP3430_EN_SSI_MASK				(1 << 0)
- + #define OMAP3430_EN_SSI_SHIFT				0
- + 
- + /* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */
- + #define OMAP3430ES2_EN_USBTLL_SHIFT			2
- + #define OMAP3430ES2_EN_USBTLL_MASK			(1 << 2)
- + 
- + /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
- + #define OMAP3430_EN_WDT2_MASK				(1 << 5)
- + #define OMAP3430_EN_WDT2_SHIFT				5
- + 
- + /* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */
- + #define OMAP3430_EN_CAM_MASK				(1 << 0)
- + #define OMAP3430_EN_CAM_SHIFT				0
- + 
- + /* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */
- + #define OMAP3430_EN_WDT3_MASK				(1 << 12)
- + #define OMAP3430_EN_WDT3_SHIFT				12
- + 
- + /* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */
- + #define OMAP3430_OVERRIDE_ENABLE_MASK			(1 << 19)
- + 
- + 
- + /* Bits specific to each register */
- + 
- + /* CM_FCLKEN_IVA2 */
- + #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK		(1 << 0)
- + #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT		0
- + 
- + /* CM_CLKEN_PLL_IVA2 */
- + #define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT		8
- + #define OMAP3430_IVA2_DPLL_RAMPTIME_MASK		(0x3 << 8)
- + #define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT		4
- + #define OMAP3430_IVA2_DPLL_FREQSEL_MASK			(0xf << 4)
- + #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT		3
- + #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK		(1 << 3)
- + #define OMAP3430_EN_IVA2_DPLL_SHIFT			0
- + #define OMAP3430_EN_IVA2_DPLL_MASK			(0x7 << 0)
- + 
- + /* CM_IDLEST_IVA2 */
- + #define OMAP3430_ST_IVA2_MASK				(1 << 0)
- + 
- + /* CM_IDLEST_PLL_IVA2 */
- + #define OMAP3430_ST_IVA2_CLK_SHIFT			0
- + #define OMAP3430_ST_IVA2_CLK_MASK			(1 << 0)
- + 
- + /* CM_AUTOIDLE_PLL_IVA2 */
- + #define OMAP3430_AUTO_IVA2_DPLL_SHIFT			0
- + #define OMAP3430_AUTO_IVA2_DPLL_MASK			(0x7 << 0)
- + 
- + /* CM_CLKSEL1_PLL_IVA2 */
- + #define OMAP3430_IVA2_CLK_SRC_SHIFT			19
- + #define OMAP3430_IVA2_CLK_SRC_MASK			(0x3 << 19)
- + #define OMAP3430_IVA2_DPLL_MULT_SHIFT			8
- + #define OMAP3430_IVA2_DPLL_MULT_MASK			(0x7ff << 8)
- + #define OMAP3430_IVA2_DPLL_DIV_SHIFT			0
- + #define OMAP3430_IVA2_DPLL_DIV_MASK			(0x7f << 0)
- + 
- + /* CM_CLKSEL2_PLL_IVA2 */
- + #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT		0
- + #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK		(0x1f << 0)
- + 
- + /* CM_CLKSTCTRL_IVA2 */
- + #define OMAP3430_CLKTRCTRL_IVA2_SHIFT			0
- + #define OMAP3430_CLKTRCTRL_IVA2_MASK			(0x3 << 0)
- + 
- + /* CM_CLKSTST_IVA2 */
- + #define OMAP3430_CLKACTIVITY_IVA2_SHIFT			0
- + #define OMAP3430_CLKACTIVITY_IVA2_MASK			(1 << 0)
- + 
- + /* CM_REVISION specific bits */
- + 
- + /* CM_SYSCONFIG specific bits */
- + 
- + /* CM_CLKEN_PLL_MPU */
- + #define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT		8
- + #define OMAP3430_MPU_DPLL_RAMPTIME_MASK			(0x3 << 8)
- + #define OMAP3430_MPU_DPLL_FREQSEL_SHIFT			4
- + #define OMAP3430_MPU_DPLL_FREQSEL_MASK			(0xf << 4)
- + #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT		3
- + #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK		(1 << 3)
- + #define OMAP3430_EN_MPU_DPLL_SHIFT			0
- + #define OMAP3430_EN_MPU_DPLL_MASK			(0x7 << 0)
- + 
- + /* CM_IDLEST_MPU */
- + #define OMAP3430_ST_MPU_MASK				(1 << 0)
- + 
- + /* CM_IDLEST_PLL_MPU */
- + #define OMAP3430_ST_MPU_CLK_SHIFT			0
- + #define OMAP3430_ST_MPU_CLK_MASK			(1 << 0)
- + 
- + /* CM_AUTOIDLE_PLL_MPU */
- + #define OMAP3430_AUTO_MPU_DPLL_SHIFT			0
- + #define OMAP3430_AUTO_MPU_DPLL_MASK			(0x7 << 0)
- + 
- + /* CM_CLKSEL1_PLL_MPU */
- + #define OMAP3430_MPU_CLK_SRC_SHIFT			19
- + #define OMAP3430_MPU_CLK_SRC_MASK			(0x3 << 19)
- + #define OMAP3430_MPU_DPLL_MULT_SHIFT			8
- + #define OMAP3430_MPU_DPLL_MULT_MASK			(0x7ff << 8)
- + #define OMAP3430_MPU_DPLL_DIV_SHIFT			0
- + #define OMAP3430_MPU_DPLL_DIV_MASK			(0x7f << 0)
- + 
- + /* CM_CLKSEL2_PLL_MPU */
- + #define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT		0
- + #define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK		(0x1f << 0)
- + 
- + /* CM_CLKSTCTRL_MPU */
- + #define OMAP3430_CLKTRCTRL_MPU_SHIFT			0
- + #define OMAP3430_CLKTRCTRL_MPU_MASK			(0x3 << 0)
- + 
- + /* CM_CLKSTST_MPU */
- + #define OMAP3430_CLKACTIVITY_MPU_SHIFT			0
- + #define OMAP3430_CLKACTIVITY_MPU_MASK			(1 << 0)
- + 
- + /* CM_FCLKEN1_CORE specific bits */
- + #define OMAP3430_EN_MODEM_MASK				(1 << 31)
- + #define OMAP3430_EN_MODEM_SHIFT				31
- + 
- + /* CM_ICLKEN1_CORE specific bits */
- + #define OMAP3430_EN_ICR_MASK				(1 << 29)
- + #define OMAP3430_EN_ICR_SHIFT				29
- + #define OMAP3430_EN_AES2_MASK				(1 << 28)
- + #define OMAP3430_EN_AES2_SHIFT				28
- + #define OMAP3430_EN_SHA12_MASK				(1 << 27)
- + #define OMAP3430_EN_SHA12_SHIFT				27
- + #define OMAP3430_EN_DES2_MASK				(1 << 26)
- + #define OMAP3430_EN_DES2_SHIFT				26
- + #define OMAP3430ES1_EN_FAC_MASK				(1 << 8)
- + #define OMAP3430ES1_EN_FAC_SHIFT			8
- + #define OMAP3430_EN_MAILBOXES_MASK			(1 << 7)
- + #define OMAP3430_EN_MAILBOXES_SHIFT			7
- + #define OMAP3430_EN_OMAPCTRL_MASK			(1 << 6)
- + #define OMAP3430_EN_OMAPCTRL_SHIFT			6
- + #define OMAP3430_EN_SAD2D_MASK				(1 << 3)
- + #define OMAP3430_EN_SAD2D_SHIFT				3
- + #define OMAP3430_EN_SDRC_MASK				(1 << 1)
- + #define OMAP3430_EN_SDRC_SHIFT				1
- + 
- + /* AM35XX specific CM_ICLKEN1_CORE bits */
- + #define AM35XX_EN_IPSS_MASK				(1 << 4)
- + #define AM35XX_EN_IPSS_SHIFT				4
- + #define AM35XX_EN_UART4_MASK				(1 << 23)
- + #define AM35XX_EN_UART4_SHIFT				23
- + 
- + /* CM_ICLKEN2_CORE */
- + #define OMAP3430_EN_PKA_MASK				(1 << 4)
- + #define OMAP3430_EN_PKA_SHIFT				4
- + #define OMAP3430_EN_AES1_MASK				(1 << 3)
- + #define OMAP3430_EN_AES1_SHIFT				3
- + #define OMAP3430_EN_RNG_MASK				(1 << 2)
- + #define OMAP3430_EN_RNG_SHIFT				2
- + #define OMAP3430_EN_SHA11_MASK				(1 << 1)
- + #define OMAP3430_EN_SHA11_SHIFT				1
- + #define OMAP3430_EN_DES1_MASK				(1 << 0)
- + #define OMAP3430_EN_DES1_SHIFT				0
- + 
- + /* CM_ICLKEN3_CORE */
- + #define OMAP3430_EN_MAD2D_SHIFT				3
- + #define OMAP3430_EN_MAD2D_MASK				(1 << 3)
- + 
- + /* CM_FCLKEN3_CORE specific bits */
- + #define OMAP3430ES2_EN_TS_SHIFT				1
- + #define OMAP3430ES2_EN_TS_MASK				(1 << 1)
- + #define OMAP3430ES2_EN_CPEFUSE_SHIFT			0
- + #define OMAP3430ES2_EN_CPEFUSE_MASK			(1 << 0)
- + 
- + /* CM_IDLEST1_CORE specific bits */
- + #define OMAP3430ES2_ST_MMC3_SHIFT			30
- + #define OMAP3430ES2_ST_MMC3_MASK			(1 << 30)
- + #define OMAP3430_ST_ICR_SHIFT				29
- + #define OMAP3430_ST_ICR_MASK				(1 << 29)
- + #define OMAP3430_ST_AES2_SHIFT				28
- + #define OMAP3430_ST_AES2_MASK				(1 << 28)
- + #define OMAP3430_ST_SHA12_SHIFT				27
- + #define OMAP3430_ST_SHA12_MASK				(1 << 27)
- + #define OMAP3430_ST_DES2_SHIFT				26
- + #define OMAP3430_ST_DES2_MASK				(1 << 26)
- + #define OMAP3430_ST_MSPRO_SHIFT				23
- + #define OMAP3430_ST_MSPRO_MASK				(1 << 23)
- + #define OMAP3430_ST_HDQ_SHIFT				22
- + #define OMAP3430_ST_HDQ_MASK				(1 << 22)
- + #define OMAP3430ES1_ST_FAC_SHIFT			8
- + #define OMAP3430ES1_ST_FAC_MASK				(1 << 8)
- + #define OMAP3430ES2_ST_SSI_IDLE_SHIFT			8
- + #define OMAP3430ES2_ST_SSI_IDLE_MASK			(1 << 8)
- + #define OMAP3430_ST_MAILBOXES_SHIFT			7
- + #define OMAP3430_ST_MAILBOXES_MASK			(1 << 7)
- + #define OMAP3430_ST_OMAPCTRL_SHIFT			6
- + #define OMAP3430_ST_OMAPCTRL_MASK			(1 << 6)
- + #define OMAP3430_ST_SDMA_SHIFT				2
- + #define OMAP3430_ST_SDMA_MASK				(1 << 2)
- + #define OMAP3430_ST_SDRC_SHIFT				1
- + #define OMAP3430_ST_SDRC_MASK				(1 << 1)
- + #define OMAP3430_ST_SSI_STDBY_SHIFT			0
- + #define OMAP3430_ST_SSI_STDBY_MASK			(1 << 0)
- + 
- + /* AM35xx specific CM_IDLEST1_CORE bits */
- + #define AM35XX_ST_IPSS_SHIFT				5
- + #define AM35XX_ST_IPSS_MASK 				(1 << 5)
- + 
- + /* CM_IDLEST2_CORE */
- + #define OMAP3430_ST_PKA_SHIFT				4
- + #define OMAP3430_ST_PKA_MASK				(1 << 4)
- + #define OMAP3430_ST_AES1_SHIFT				3
- + #define OMAP3430_ST_AES1_MASK				(1 << 3)
- + #define OMAP3430_ST_RNG_SHIFT				2
- + #define OMAP3430_ST_RNG_MASK				(1 << 2)
- + #define OMAP3430_ST_SHA11_SHIFT				1
- + #define OMAP3430_ST_SHA11_MASK				(1 << 1)
- + #define OMAP3430_ST_DES1_SHIFT				0
- + #define OMAP3430_ST_DES1_MASK				(1 << 0)
- + 
- + /* CM_IDLEST3_CORE */
- + #define OMAP3430ES2_ST_USBTLL_SHIFT			2
- + #define OMAP3430ES2_ST_USBTLL_MASK			(1 << 2)
- + #define OMAP3430ES2_ST_CPEFUSE_SHIFT			0
- + #define OMAP3430ES2_ST_CPEFUSE_MASK			(1 << 0)
- + 
- + /* CM_AUTOIDLE1_CORE */
- + #define OMAP3430_AUTO_MODEM_MASK			(1 << 31)
- + #define OMAP3430_AUTO_MODEM_SHIFT			31
- + #define OMAP3430ES2_AUTO_MMC3_MASK			(1 << 30)
- + #define OMAP3430ES2_AUTO_MMC3_SHIFT			30
- + #define OMAP3430ES2_AUTO_ICR_MASK			(1 << 29)
- + #define OMAP3430ES2_AUTO_ICR_SHIFT			29
- + #define OMAP3430_AUTO_AES2_MASK				(1 << 28)
- + #define OMAP3430_AUTO_AES2_SHIFT			28
- + #define OMAP3430_AUTO_SHA12_MASK			(1 << 27)
- + #define OMAP3430_AUTO_SHA12_SHIFT			27
- + #define OMAP3430_AUTO_DES2_MASK				(1 << 26)
- + #define OMAP3430_AUTO_DES2_SHIFT			26
- + #define OMAP3430_AUTO_MMC2_MASK				(1 << 25)
- + #define OMAP3430_AUTO_MMC2_SHIFT			25
- + #define OMAP3430_AUTO_MMC1_MASK				(1 << 24)
- + #define OMAP3430_AUTO_MMC1_SHIFT			24
- + #define OMAP3430_AUTO_MSPRO_MASK			(1 << 23)
- + #define OMAP3430_AUTO_MSPRO_SHIFT			23
- + #define OMAP3430_AUTO_HDQ_MASK				(1 << 22)
- + #define OMAP3430_AUTO_HDQ_SHIFT				22
- + #define OMAP3430_AUTO_MCSPI4_MASK			(1 << 21)
- + #define OMAP3430_AUTO_MCSPI4_SHIFT			21
- + #define OMAP3430_AUTO_MCSPI3_MASK			(1 << 20)
- + #define OMAP3430_AUTO_MCSPI3_SHIFT			20
- + #define OMAP3430_AUTO_MCSPI2_MASK			(1 << 19)
- + #define OMAP3430_AUTO_MCSPI2_SHIFT			19
- + #define OMAP3430_AUTO_MCSPI1_MASK			(1 << 18)
- + #define OMAP3430_AUTO_MCSPI1_SHIFT			18
- + #define OMAP3430_AUTO_I2C3_MASK				(1 << 17)
- + #define OMAP3430_AUTO_I2C3_SHIFT			17
- + #define OMAP3430_AUTO_I2C2_MASK				(1 << 16)
- + #define OMAP3430_AUTO_I2C2_SHIFT			16
- + #define OMAP3430_AUTO_I2C1_MASK				(1 << 15)
- + #define OMAP3430_AUTO_I2C1_SHIFT			15
- + #define OMAP3430_AUTO_UART2_MASK			(1 << 14)
- + #define OMAP3430_AUTO_UART2_SHIFT			14
- + #define OMAP3430_AUTO_UART1_MASK			(1 << 13)
- + #define OMAP3430_AUTO_UART1_SHIFT			13
- + #define OMAP3430_AUTO_GPT11_MASK			(1 << 12)
- + #define OMAP3430_AUTO_GPT11_SHIFT			12
- + #define OMAP3430_AUTO_GPT10_MASK			(1 << 11)
- + #define OMAP3430_AUTO_GPT10_SHIFT			11
- + #define OMAP3430_AUTO_MCBSP5_MASK			(1 << 10)
- + #define OMAP3430_AUTO_MCBSP5_SHIFT			10
- + #define OMAP3430_AUTO_MCBSP1_MASK			(1 << 9)
- + #define OMAP3430_AUTO_MCBSP1_SHIFT			9
- + #define OMAP3430ES1_AUTO_FAC_MASK			(1 << 8)
- + #define OMAP3430ES1_AUTO_FAC_SHIFT			8
- + #define OMAP3430_AUTO_MAILBOXES_MASK			(1 << 7)
- + #define OMAP3430_AUTO_MAILBOXES_SHIFT			7
- + #define OMAP3430_AUTO_OMAPCTRL_MASK			(1 << 6)
- + #define OMAP3430_AUTO_OMAPCTRL_SHIFT			6
- + #define OMAP3430ES1_AUTO_FSHOSTUSB_MASK			(1 << 5)
- + #define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT		5
- + #define OMAP3430_AUTO_HSOTGUSB_MASK			(1 << 4)
- + #define OMAP3430_AUTO_HSOTGUSB_SHIFT			4
- + #define OMAP3430ES1_AUTO_D2D_MASK			(1 << 3)
- + #define OMAP3430ES1_AUTO_D2D_SHIFT			3
- + #define OMAP3430_AUTO_SAD2D_MASK			(1 << 3)
- + #define OMAP3430_AUTO_SAD2D_SHIFT			3
- + #define OMAP3430_AUTO_SSI_MASK				(1 << 0)
- + #define OMAP3430_AUTO_SSI_SHIFT				0
- + 
- + /* CM_AUTOIDLE2_CORE */
- + #define OMAP3430_AUTO_PKA_MASK				(1 << 4)
- + #define OMAP3430_AUTO_PKA_SHIFT				4
- + #define OMAP3430_AUTO_AES1_MASK				(1 << 3)
- + #define OMAP3430_AUTO_AES1_SHIFT			3
- + #define OMAP3430_AUTO_RNG_MASK				(1 << 2)
- + #define OMAP3430_AUTO_RNG_SHIFT				2
- + #define OMAP3430_AUTO_SHA11_MASK			(1 << 1)
- + #define OMAP3430_AUTO_SHA11_SHIFT			1
- + #define OMAP3430_AUTO_DES1_MASK				(1 << 0)
- + #define OMAP3430_AUTO_DES1_SHIFT			0
- + 
- + /* CM_AUTOIDLE3_CORE */
- + #define	OMAP3430ES2_AUTO_USBHOST			(1 << 0)
- + #define	OMAP3430ES2_AUTO_USBHOST_SHIFT			0
- + #define	OMAP3430ES2_AUTO_USBTLL				(1 << 2)
- + #define OMAP3430ES2_AUTO_USBTLL_SHIFT			2
- + #define OMAP3430ES2_AUTO_USBTLL_MASK			(1 << 2)
- + #define OMAP3430_AUTO_MAD2D_SHIFT			3
- + #define OMAP3430_AUTO_MAD2D_MASK			(1 << 3)
- + 
- + /* CM_CLKSEL_CORE */
- + #define OMAP3430_CLKSEL_SSI_SHIFT			8
- + #define OMAP3430_CLKSEL_SSI_MASK			(0xf << 8)
- + #define OMAP3430_CLKSEL_GPT11_MASK			(1 << 7)
- + #define OMAP3430_CLKSEL_GPT11_SHIFT			7
- + #define OMAP3430_CLKSEL_GPT10_MASK			(1 << 6)
- + #define OMAP3430_CLKSEL_GPT10_SHIFT			6
- + #define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT		4
- + #define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK		(0x3 << 4)
- + #define OMAP3430_CLKSEL_L4_SHIFT			2
- + #define OMAP3430_CLKSEL_L4_MASK				(0x3 << 2)
- + #define OMAP3430_CLKSEL_L3_SHIFT			0
- + #define OMAP3430_CLKSEL_L3_MASK				(0x3 << 0)
- + #define OMAP3630_CLKSEL_96M_SHIFT			12
- + #define OMAP3630_CLKSEL_96M_MASK			(0x3 << 12)
- + 
- + /* CM_CLKSTCTRL_CORE */
- + #define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT			4
- + #define OMAP3430ES1_CLKTRCTRL_D2D_MASK			(0x3 << 4)
- + #define OMAP3430_CLKTRCTRL_L4_SHIFT			2
- + #define OMAP3430_CLKTRCTRL_L4_MASK			(0x3 << 2)
- + #define OMAP3430_CLKTRCTRL_L3_SHIFT			0
- + #define OMAP3430_CLKTRCTRL_L3_MASK			(0x3 << 0)
- + 
- + /* CM_CLKSTST_CORE */
- + #define OMAP3430ES1_CLKACTIVITY_D2D_SHIFT		2
- + #define OMAP3430ES1_CLKACTIVITY_D2D_MASK		(1 << 2)
- + #define OMAP3430_CLKACTIVITY_L4_SHIFT			1
- + #define OMAP3430_CLKACTIVITY_L4_MASK			(1 << 1)
- + #define OMAP3430_CLKACTIVITY_L3_SHIFT			0
- + #define OMAP3430_CLKACTIVITY_L3_MASK			(1 << 0)
- + 
- + /* CM_FCLKEN_GFX */
- + #define OMAP3430ES1_EN_3D_MASK				(1 << 2)
- + #define OMAP3430ES1_EN_3D_SHIFT				2
- + #define OMAP3430ES1_EN_2D_MASK				(1 << 1)
- + #define OMAP3430ES1_EN_2D_SHIFT				1
- + 
- + /* CM_ICLKEN_GFX specific bits */
- + 
- + /* CM_IDLEST_GFX specific bits */
- + 
- + /* CM_CLKSEL_GFX specific bits */
- + 
- + /* CM_SLEEPDEP_GFX specific bits */
- + 
- + /* CM_CLKSTCTRL_GFX */
- + #define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT			0
- + #define OMAP3430ES1_CLKTRCTRL_GFX_MASK			(0x3 << 0)
- + 
- + /* CM_CLKSTST_GFX */
- + #define OMAP3430ES1_CLKACTIVITY_GFX_SHIFT		0
- + #define OMAP3430ES1_CLKACTIVITY_GFX_MASK		(1 << 0)
- + 
- + /* CM_FCLKEN_SGX */
- + #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT		1
- + #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK		(1 << 1)
- + 
- + /* CM_IDLEST_SGX */
- + #define OMAP3430ES2_ST_SGX_SHIFT			1
- + #define OMAP3430ES2_ST_SGX_MASK				(1 << 1)
- + 
- + /* CM_ICLKEN_SGX */
- + #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT		0
- + #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK		(1 << 0)
- + 
- + /* CM_CLKSEL_SGX */
- + #define OMAP3430ES2_CLKSEL_SGX_SHIFT			0
- + #define OMAP3430ES2_CLKSEL_SGX_MASK			(0x7 << 0)
- + 
- + /* CM_CLKSTCTRL_SGX */
- + #define OMAP3430ES2_CLKTRCTRL_SGX_SHIFT			0
- + #define OMAP3430ES2_CLKTRCTRL_SGX_MASK			(0x3 << 0)
- + 
- + /* CM_CLKSTST_SGX */
- + #define OMAP3430ES2_CLKACTIVITY_SGX_SHIFT		0
- + #define OMAP3430ES2_CLKACTIVITY_SGX_MASK		(1 << 0)
- + 
- + /* CM_FCLKEN_WKUP specific bits */
- + #define OMAP3430ES2_EN_USIMOCP_SHIFT			9
- + #define OMAP3430ES2_EN_USIMOCP_MASK			(1 << 9)
- + 
- + /* CM_ICLKEN_WKUP specific bits */
- + #define OMAP3430_EN_WDT1_MASK				(1 << 4)
- + #define OMAP3430_EN_WDT1_SHIFT				4
- + #define OMAP3430_EN_32KSYNC_MASK			(1 << 2)
- + #define OMAP3430_EN_32KSYNC_SHIFT			2
- + 
- + /* CM_IDLEST_WKUP specific bits */
- + #define OMAP3430ES2_ST_USIMOCP_SHIFT			9
- + #define OMAP3430ES2_ST_USIMOCP_MASK			(1 << 9)
- + #define OMAP3430_ST_WDT2_SHIFT				5
- + #define OMAP3430_ST_WDT2_MASK				(1 << 5)
- + #define OMAP3430_ST_WDT1_SHIFT				4
- + #define OMAP3430_ST_WDT1_MASK				(1 << 4)
- + #define OMAP3430_ST_32KSYNC_SHIFT			2
- + #define OMAP3430_ST_32KSYNC_MASK			(1 << 2)
- + 
- + /* CM_AUTOIDLE_WKUP */
- + #define OMAP3430ES2_AUTO_USIMOCP_MASK			(1 << 9)
- + #define OMAP3430ES2_AUTO_USIMOCP_SHIFT			9
- + #define OMAP3430_AUTO_WDT2_MASK				(1 << 5)
- + #define OMAP3430_AUTO_WDT2_SHIFT			5
- + #define OMAP3430_AUTO_WDT1_MASK				(1 << 4)
- + #define OMAP3430_AUTO_WDT1_SHIFT			4
- + #define OMAP3430_AUTO_GPIO1_MASK			(1 << 3)
- + #define OMAP3430_AUTO_GPIO1_SHIFT			3
- + #define OMAP3430_AUTO_32KSYNC_MASK			(1 << 2)
- + #define OMAP3430_AUTO_32KSYNC_SHIFT			2
- + #define OMAP3430_AUTO_GPT12_MASK			(1 << 1)
- + #define OMAP3430_AUTO_GPT12_SHIFT			1
- + #define OMAP3430_AUTO_GPT1_MASK				(1 << 0)
- + #define OMAP3430_AUTO_GPT1_SHIFT			0
- + 
- + /* CM_CLKSEL_WKUP */
- + #define OMAP3430ES2_CLKSEL_USIMOCP_MASK			(0xf << 3)
- + #define OMAP3430_CLKSEL_RM_SHIFT			1
- + #define OMAP3430_CLKSEL_RM_MASK				(0x3 << 1)
- + #define OMAP3430_CLKSEL_GPT1_SHIFT			0
- + #define OMAP3430_CLKSEL_GPT1_MASK			(1 << 0)
- + 
- + /* CM_CLKEN_PLL */
- + #define OMAP3430_PWRDN_EMU_PERIPH_SHIFT			31
- + #define OMAP3430_PWRDN_CAM_SHIFT			30
- + #define OMAP3430_PWRDN_DSS1_SHIFT			29
- + #define OMAP3430_PWRDN_TV_SHIFT				28
- + #define OMAP3430_PWRDN_96M_SHIFT			27
- + #define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT		24
- + #define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK		(0x3 << 24)
- + #define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT		20
- + #define OMAP3430_PERIPH_DPLL_FREQSEL_MASK		(0xf << 20)
- + #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT	19
- + #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK		(1 << 19)
- + #define OMAP3430_EN_PERIPH_DPLL_SHIFT			16
- + #define OMAP3430_EN_PERIPH_DPLL_MASK			(0x7 << 16)
- + #define OMAP3430_PWRDN_EMU_CORE_SHIFT			12
- + #define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT		8
- + #define OMAP3430_CORE_DPLL_RAMPTIME_MASK		(0x3 << 8)
- + #define OMAP3430_CORE_DPLL_FREQSEL_SHIFT		4
- + #define OMAP3430_CORE_DPLL_FREQSEL_MASK			(0xf << 4)
- + #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT		3
- + #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK		(1 << 3)
- + #define OMAP3430_EN_CORE_DPLL_SHIFT			0
- + #define OMAP3430_EN_CORE_DPLL_MASK			(0x7 << 0)
- + 
- + /* CM_CLKEN2_PLL */
- + #define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT	10
- + #define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK		(0x3 << 8)
- + #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT		4
- + #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK		(0xf << 4)
- + #define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT	3
- + #define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT		0
- + #define OMAP3430ES2_EN_PERIPH2_DPLL_MASK		(0x7 << 0)
- + 
- + /* CM_IDLEST_CKGEN */
- + #define OMAP3430_ST_54M_CLK_MASK			(1 << 5)
- + #define OMAP3430_ST_12M_CLK_MASK			(1 << 4)
- + #define OMAP3430_ST_48M_CLK_MASK			(1 << 3)
- + #define OMAP3430_ST_96M_CLK_MASK			(1 << 2)
- + #define OMAP3430_ST_PERIPH_CLK_SHIFT			1
- + #define OMAP3430_ST_PERIPH_CLK_MASK			(1 << 1)
- + #define OMAP3430_ST_CORE_CLK_SHIFT			0
- + #define OMAP3430_ST_CORE_CLK_MASK			(1 << 0)
- + 
- + /* CM_IDLEST2_CKGEN */
- + #define OMAP3430ES2_ST_USIM_CLK_SHIFT			2
- + #define OMAP3430ES2_ST_USIM_CLK_MASK			(1 << 2)
- + #define OMAP3430ES2_ST_120M_CLK_SHIFT			1
- + #define OMAP3430ES2_ST_120M_CLK_MASK			(1 << 1)
- + #define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT		0
- + #define OMAP3430ES2_ST_PERIPH2_CLK_MASK			(1 << 0)
- + 
- + /* CM_AUTOIDLE_PLL */
- + #define OMAP3430_AUTO_PERIPH_DPLL_SHIFT			3
- + #define OMAP3430_AUTO_PERIPH_DPLL_MASK			(0x7 << 3)
- + #define OMAP3430_AUTO_CORE_DPLL_SHIFT			0
- + #define OMAP3430_AUTO_CORE_DPLL_MASK			(0x7 << 0)
- + 
- + /* CM_AUTOIDLE2_PLL */
- + #define OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT		0
- + #define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK		(0x7 << 0)
- + 
- + /* CM_CLKSEL1_PLL */
- + /* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */
- + #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT		27
- + #define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK		(0x1f << 27)
- + #define OMAP3430_CORE_DPLL_MULT_SHIFT			16
- + #define OMAP3430_CORE_DPLL_MULT_MASK			(0x7ff << 16)
- + #define OMAP3430_CORE_DPLL_DIV_SHIFT			8
- + #define OMAP3430_CORE_DPLL_DIV_MASK			(0x7f << 8)
- + #define OMAP3430_SOURCE_96M_SHIFT			6
- + #define OMAP3430_SOURCE_96M_MASK			(1 << 6)
- + #define OMAP3430_SOURCE_54M_SHIFT			5
- + #define OMAP3430_SOURCE_54M_MASK			(1 << 5)
- + #define OMAP3430_SOURCE_48M_SHIFT			3
- + #define OMAP3430_SOURCE_48M_MASK			(1 << 3)
- + 
- + /* CM_CLKSEL2_PLL */
- + #define OMAP3430_PERIPH_DPLL_MULT_SHIFT			8
- + #define OMAP3430_PERIPH_DPLL_MULT_MASK			(0x7ff << 8)
- + #define OMAP3630_PERIPH_DPLL_MULT_MASK			(0xfff << 8)
- + #define OMAP3430_PERIPH_DPLL_DIV_SHIFT			0
- + #define OMAP3430_PERIPH_DPLL_DIV_MASK			(0x7f << 0)
- + #define OMAP3630_PERIPH_DPLL_DCO_SEL_SHIFT		21
- + #define OMAP3630_PERIPH_DPLL_DCO_SEL_MASK		(0x7 << 21)
- + #define OMAP3630_PERIPH_DPLL_SD_DIV_SHIFT		24
- + #define OMAP3630_PERIPH_DPLL_SD_DIV_MASK		(0xff << 24)
- + 
- + /* CM_CLKSEL3_PLL */
- + #define OMAP3430_DIV_96M_SHIFT				0
- + #define OMAP3430_DIV_96M_MASK				(0x1f << 0)
- + #define OMAP3630_DIV_96M_MASK				(0x3f << 0)
- + 
- + /* CM_CLKSEL4_PLL */
- + #define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT		8
- + #define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK		(0x7ff << 8)
- + #define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT		0
- + #define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK		(0x7f << 0)
- + 
- + /* CM_CLKSEL5_PLL */
- + #define OMAP3430ES2_DIV_120M_SHIFT			0
- + #define OMAP3430ES2_DIV_120M_MASK			(0x1f << 0)
- + 
- + /* CM_CLKOUT_CTRL */
- + #define OMAP3430_CLKOUT2_EN_SHIFT			7
- + #define OMAP3430_CLKOUT2_EN_MASK			(1 << 7)
- + #define OMAP3430_CLKOUT2_DIV_SHIFT			3
- + #define OMAP3430_CLKOUT2_DIV_MASK			(0x7 << 3)
- + #define OMAP3430_CLKOUT2SOURCE_SHIFT			0
- + #define OMAP3430_CLKOUT2SOURCE_MASK			(0x3 << 0)
- + 
- + /* CM_FCLKEN_DSS */
- + #define OMAP3430_EN_TV_MASK				(1 << 2)
- + #define OMAP3430_EN_TV_SHIFT				2
- + #define OMAP3430_EN_DSS2_MASK				(1 << 1)
- + #define OMAP3430_EN_DSS2_SHIFT				1
- + #define OMAP3430_EN_DSS1_MASK				(1 << 0)
- + #define OMAP3430_EN_DSS1_SHIFT				0
- + 
- + /* CM_ICLKEN_DSS */
- + #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_MASK		(1 << 0)
- + #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT		0
- + 
- + /* CM_IDLEST_DSS */
- + #define OMAP3430ES2_ST_DSS_IDLE_SHIFT			1
- + #define OMAP3430ES2_ST_DSS_IDLE_MASK			(1 << 1)
- + #define OMAP3430ES2_ST_DSS_STDBY_SHIFT			0
- + #define OMAP3430ES2_ST_DSS_STDBY_MASK			(1 << 0)
- + #define OMAP3430ES1_ST_DSS_SHIFT			0
- + #define OMAP3430ES1_ST_DSS_MASK				(1 << 0)
- + 
- + /* CM_AUTOIDLE_DSS */
- + #define OMAP3430_AUTO_DSS_MASK				(1 << 0)
- + #define OMAP3430_AUTO_DSS_SHIFT				0
- + 
- + /* CM_CLKSEL_DSS */
- + #define OMAP3430_CLKSEL_TV_SHIFT			8
- + #define OMAP3430_CLKSEL_TV_MASK				(0x1f << 8)
- + #define OMAP3630_CLKSEL_TV_MASK				(0x3f << 8)
- + #define OMAP3430_CLKSEL_DSS1_SHIFT			0
- + #define OMAP3430_CLKSEL_DSS1_MASK			(0x1f << 0)
- + #define OMAP3630_CLKSEL_DSS1_MASK			(0x3f << 0)
- + 
- + /* CM_SLEEPDEP_DSS specific bits */
- + 
- + /* CM_CLKSTCTRL_DSS */
- + #define OMAP3430_CLKTRCTRL_DSS_SHIFT			0
- + #define OMAP3430_CLKTRCTRL_DSS_MASK			(0x3 << 0)
- + 
- + /* CM_CLKSTST_DSS */
- + #define OMAP3430_CLKACTIVITY_DSS_SHIFT			0
- + #define OMAP3430_CLKACTIVITY_DSS_MASK			(1 << 0)
- + 
- + /* CM_FCLKEN_CAM specific bits */
- + #define OMAP3430_EN_CSI2_MASK				(1 << 1)
- + #define OMAP3430_EN_CSI2_SHIFT				1
- + 
- + /* CM_ICLKEN_CAM specific bits */
- + 
- + /* CM_IDLEST_CAM */
- + #define OMAP3430_ST_CAM_MASK				(1 << 0)
- + 
- + /* CM_AUTOIDLE_CAM */
- + #define OMAP3430_AUTO_CAM_MASK				(1 << 0)
- + #define OMAP3430_AUTO_CAM_SHIFT				0
- + 
- + /* CM_CLKSEL_CAM */
- + #define OMAP3430_CLKSEL_CAM_SHIFT			0
- + #define OMAP3430_CLKSEL_CAM_MASK			(0x1f << 0)
- + #define OMAP3630_CLKSEL_CAM_MASK			(0x3f << 0)
- + 
- + /* CM_SLEEPDEP_CAM specific bits */
- + 
- + /* CM_CLKSTCTRL_CAM */
- + #define OMAP3430_CLKTRCTRL_CAM_SHIFT			0
- + #define OMAP3430_CLKTRCTRL_CAM_MASK			(0x3 << 0)
- + 
- + /* CM_CLKSTST_CAM */
- + #define OMAP3430_CLKACTIVITY_CAM_SHIFT			0
- + #define OMAP3430_CLKACTIVITY_CAM_MASK			(1 << 0)
- + 
- + /* CM_FCLKEN_PER specific bits */
- + 
- + /* CM_ICLKEN_PER specific bits */
- + 
- + /* CM_IDLEST_PER */
- + #define OMAP3430_ST_WDT3_SHIFT				12
- + #define OMAP3430_ST_WDT3_MASK				(1 << 12)
- + #define OMAP3430_ST_MCBSP4_SHIFT			2
- + #define OMAP3430_ST_MCBSP4_MASK				(1 << 2)
- + #define OMAP3430_ST_MCBSP3_SHIFT			1
- + #define OMAP3430_ST_MCBSP3_MASK				(1 << 1)
- + #define OMAP3430_ST_MCBSP2_SHIFT			0
- + #define OMAP3430_ST_MCBSP2_MASK				(1 << 0)
- + 
- + /* CM_AUTOIDLE_PER */
- + #define OMAP3630_AUTO_UART4_MASK			(1 << 18)
- + #define OMAP3630_AUTO_UART4_SHIFT			18
- + #define OMAP3430_AUTO_GPIO6_MASK			(1 << 17)
- + #define OMAP3430_AUTO_GPIO6_SHIFT			17
- + #define OMAP3430_AUTO_GPIO5_MASK			(1 << 16)
- + #define OMAP3430_AUTO_GPIO5_SHIFT			16
- + #define OMAP3430_AUTO_GPIO4_MASK			(1 << 15)
- + #define OMAP3430_AUTO_GPIO4_SHIFT			15
- + #define OMAP3430_AUTO_GPIO3_MASK			(1 << 14)
- + #define OMAP3430_AUTO_GPIO3_SHIFT			14
- + #define OMAP3430_AUTO_GPIO2_MASK			(1 << 13)
- + #define OMAP3430_AUTO_GPIO2_SHIFT			13
- + #define OMAP3430_AUTO_WDT3_MASK				(1 << 12)
- + #define OMAP3430_AUTO_WDT3_SHIFT			12
- + #define OMAP3430_AUTO_UART3_MASK			(1 << 11)
- + #define OMAP3430_AUTO_UART3_SHIFT			11
- + #define OMAP3430_AUTO_GPT9_MASK				(1 << 10)
- + #define OMAP3430_AUTO_GPT9_SHIFT			10
- + #define OMAP3430_AUTO_GPT8_MASK				(1 << 9)
- + #define OMAP3430_AUTO_GPT8_SHIFT			9
- + #define OMAP3430_AUTO_GPT7_MASK				(1 << 8)
- + #define OMAP3430_AUTO_GPT7_SHIFT			8
- + #define OMAP3430_AUTO_GPT6_MASK				(1 << 7)
- + #define OMAP3430_AUTO_GPT6_SHIFT			7
- + #define OMAP3430_AUTO_GPT5_MASK				(1 << 6)
- + #define OMAP3430_AUTO_GPT5_SHIFT			6
- + #define OMAP3430_AUTO_GPT4_MASK				(1 << 5)
- + #define OMAP3430_AUTO_GPT4_SHIFT			5
- + #define OMAP3430_AUTO_GPT3_MASK				(1 << 4)
- + #define OMAP3430_AUTO_GPT3_SHIFT			4
- + #define OMAP3430_AUTO_GPT2_MASK				(1 << 3)
- + #define OMAP3430_AUTO_GPT2_SHIFT			3
- + #define OMAP3430_AUTO_MCBSP4_MASK			(1 << 2)
- + #define OMAP3430_AUTO_MCBSP4_SHIFT			2
- + #define OMAP3430_AUTO_MCBSP3_MASK			(1 << 1)
- + #define OMAP3430_AUTO_MCBSP3_SHIFT			1
- + #define OMAP3430_AUTO_MCBSP2_MASK			(1 << 0)
- + #define OMAP3430_AUTO_MCBSP2_SHIFT			0
- + 
- + /* CM_CLKSEL_PER */
- + #define OMAP3430_CLKSEL_GPT9_MASK			(1 << 7)
- + #define OMAP3430_CLKSEL_GPT9_SHIFT			7
- + #define OMAP3430_CLKSEL_GPT8_MASK			(1 << 6)
- + #define OMAP3430_CLKSEL_GPT8_SHIFT			6
- + #define OMAP3430_CLKSEL_GPT7_MASK			(1 << 5)
- + #define OMAP3430_CLKSEL_GPT7_SHIFT			5
- + #define OMAP3430_CLKSEL_GPT6_MASK			(1 << 4)
- + #define OMAP3430_CLKSEL_GPT6_SHIFT			4
- + #define OMAP3430_CLKSEL_GPT5_MASK			(1 << 3)
- + #define OMAP3430_CLKSEL_GPT5_SHIFT			3
- + #define OMAP3430_CLKSEL_GPT4_MASK			(1 << 2)
- + #define OMAP3430_CLKSEL_GPT4_SHIFT			2
- + #define OMAP3430_CLKSEL_GPT3_MASK			(1 << 1)
- + #define OMAP3430_CLKSEL_GPT3_SHIFT			1
- + #define OMAP3430_CLKSEL_GPT2_MASK			(1 << 0)
- + #define OMAP3430_CLKSEL_GPT2_SHIFT			0
- + 
- + /* CM_SLEEPDEP_PER specific bits */
- + #define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2_MASK		(1 << 2)
- + 
- + /* CM_CLKSTCTRL_PER */
- + #define OMAP3430_CLKTRCTRL_PER_SHIFT			0
- + #define OMAP3430_CLKTRCTRL_PER_MASK			(0x3 << 0)
- + 
- + /* CM_CLKSTST_PER */
- + #define OMAP3430_CLKACTIVITY_PER_SHIFT			0
- + #define OMAP3430_CLKACTIVITY_PER_MASK			(1 << 0)
- + 
- + /* CM_CLKSEL1_EMU */
- + #define OMAP3430_DIV_DPLL4_SHIFT			24
- + #define OMAP3430_DIV_DPLL4_MASK				(0x1f << 24)
- + #define OMAP3630_DIV_DPLL4_MASK				(0x3f << 24)
- + #define OMAP3430_DIV_DPLL3_SHIFT			16
- + #define OMAP3430_DIV_DPLL3_MASK				(0x1f << 16)
- + #define OMAP3430_CLKSEL_TRACECLK_SHIFT			11
- + #define OMAP3430_CLKSEL_TRACECLK_MASK			(0x7 << 11)
- + #define OMAP3430_CLKSEL_PCLK_SHIFT			8
- + #define OMAP3430_CLKSEL_PCLK_MASK			(0x7 << 8)
- + #define OMAP3430_CLKSEL_PCLKX2_SHIFT			6
- + #define OMAP3430_CLKSEL_PCLKX2_MASK			(0x3 << 6)
- + #define OMAP3430_CLKSEL_ATCLK_SHIFT			4
- + #define OMAP3430_CLKSEL_ATCLK_MASK			(0x3 << 4)
- + #define OMAP3430_TRACE_MUX_CTRL_SHIFT			2
- + #define OMAP3430_TRACE_MUX_CTRL_MASK			(0x3 << 2)
- + #define OMAP3430_MUX_CTRL_SHIFT				0
- + #define OMAP3430_MUX_CTRL_MASK				(0x3 << 0)
- + 
- + /* CM_CLKSTCTRL_EMU */
- + #define OMAP3430_CLKTRCTRL_EMU_SHIFT			0
- + #define OMAP3430_CLKTRCTRL_EMU_MASK			(0x3 << 0)
- + 
- + /* CM_CLKSTST_EMU */
- + #define OMAP3430_CLKACTIVITY_EMU_SHIFT			0
- + #define OMAP3430_CLKACTIVITY_EMU_MASK			(1 << 0)
- + 
- + /* CM_CLKSEL2_EMU specific bits */
- + #define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT		8
- + #define OMAP3430_CORE_DPLL_EMU_MULT_MASK		(0x7ff << 8)
- + #define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT		0
- + #define OMAP3430_CORE_DPLL_EMU_DIV_MASK			(0x7f << 0)
- + 
- + /* CM_CLKSEL3_EMU specific bits */
- + #define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT		8
- + #define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK		(0x7ff << 8)
- + #define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT		0
- + #define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK		(0x7f << 0)
- + 
- + /* CM_POLCTRL */
- + #define OMAP3430_CLKOUT2_POL_MASK			(1 << 0)
- + 
- + /* CM_IDLEST_NEON */
- + #define OMAP3430_ST_NEON_MASK				(1 << 0)
- + 
- + /* CM_CLKSTCTRL_NEON */
- + #define OMAP3430_CLKTRCTRL_NEON_SHIFT			0
- + #define OMAP3430_CLKTRCTRL_NEON_MASK			(0x3 << 0)
- + 
- + /* CM_FCLKEN_USBHOST */
- + #define OMAP3430ES2_EN_USBHOST2_SHIFT			1
- + #define OMAP3430ES2_EN_USBHOST2_MASK			(1 << 1)
- + #define OMAP3430ES2_EN_USBHOST1_SHIFT			0
- + #define OMAP3430ES2_EN_USBHOST1_MASK			(1 << 0)
- + 
- + /* CM_ICLKEN_USBHOST */
- + #define OMAP3430ES2_EN_USBHOST_SHIFT			0
- + #define OMAP3430ES2_EN_USBHOST_MASK			(1 << 0)
- + 
- + /* CM_IDLEST_USBHOST */
- + #define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT		1
- + #define OMAP3430ES2_ST_USBHOST_IDLE_MASK		(1 << 1)
- + #define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT		0
- + #define OMAP3430ES2_ST_USBHOST_STDBY_MASK		(1 << 0)
- + 
- + /* CM_AUTOIDLE_USBHOST */
- + #define OMAP3430ES2_AUTO_USBHOST_SHIFT			0
- + #define OMAP3430ES2_AUTO_USBHOST_MASK			(1 << 0)
- + 
- + /* CM_SLEEPDEP_USBHOST */
- + #define OMAP3430ES2_EN_MPU_SHIFT			1
- + #define OMAP3430ES2_EN_MPU_MASK				(1 << 1)
- + #define OMAP3430ES2_EN_IVA2_SHIFT			2
- + #define OMAP3430ES2_EN_IVA2_MASK			(1 << 2)
- + 
- + /* CM_CLKSTCTRL_USBHOST */
- + #define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT		0
- + #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK		(3 << 0)
- + 
- + /* CM_CLKSTST_USBHOST */
- + #define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT		0
- + #define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK		(1 << 0)
- + 
- + /*
- +  *
- +  */
- + 
- + /* OMAP3XXX CM_CLKSTCTRL_*.CLKTRCTRL_* register bit values */
- + #define OMAP34XX_CLKSTCTRL_DISABLE_AUTO		0x0
- + #define OMAP34XX_CLKSTCTRL_FORCE_SLEEP		0x1
- + #define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP		0x2
- + #define OMAP34XX_CLKSTCTRL_ENABLE_AUTO		0x3
- + 
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/cm-regbits-44xx.h linux-3.2.1/arch/arm/mach-ckb_3352/cm-regbits-44xx.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/cm-regbits-44xx.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/cm-regbits-44xx.h	2014-05-15 13:25:13.891248083 +0900
- ***************
- *** 0 ****
- --- 1,1445 ----
- + /*
- +  * OMAP44xx Clock Management register bits
- +  *
- +  * Copyright (C) 2009-2010 Texas Instruments, Inc.
- +  * Copyright (C) 2009-2010 Nokia Corporation
- +  *
- +  * Paul Walmsley (paul@pwsan.com)
- +  * Rajendra Nayak (rnayak@ti.com)
- +  * Benoit Cousson (b-cousson@ti.com)
- +  *
- +  * This file is automatically generated from the OMAP hardware databases.
- +  * We respectfully ask that any modifications to this file be coordinated
- +  * with the public linux-omap@vger.kernel.org mailing list and the
- +  * authors above to ensure that the autogeneration scripts are kept
- +  * up-to-date with the file contents.
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
- + #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
- + 
- + /* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
- + #define OMAP4430_ABE_DYNDEP_SHIFT				3
- + #define OMAP4430_ABE_DYNDEP_MASK				(1 << 3)
- + 
- + /*
- +  * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
- +  * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
- +  */
- + #define OMAP4430_ABE_STATDEP_SHIFT				3
- + #define OMAP4430_ABE_STATDEP_MASK				(1 << 3)
- + 
- + /* Used by CM_L4CFG_DYNAMICDEP */
- + #define OMAP4430_ALWONCORE_DYNDEP_SHIFT				16
- + #define OMAP4430_ALWONCORE_DYNDEP_MASK				(1 << 16)
- + 
- + /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
- + #define OMAP4430_ALWONCORE_STATDEP_SHIFT			16
- + #define OMAP4430_ALWONCORE_STATDEP_MASK				(1 << 16)
- + 
- + /*
- +  * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE,
- +  * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU,
- +  * CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB
- +  */
- + #define OMAP4430_AUTO_DPLL_MODE_SHIFT				0
- + #define OMAP4430_AUTO_DPLL_MODE_MASK				(0x7 << 0)
- + 
- + /* Used by CM_L4CFG_DYNAMICDEP */
- + #define OMAP4430_CEFUSE_DYNDEP_SHIFT				17
- + #define OMAP4430_CEFUSE_DYNDEP_MASK				(1 << 17)
- + 
- + /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
- + #define OMAP4430_CEFUSE_STATDEP_SHIFT				17
- + #define OMAP4430_CEFUSE_STATDEP_MASK				(1 << 17)
- + 
- + /* Used by CM1_ABE_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT		13
- + #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK			(1 << 13)
- + 
- + /* Used by CM1_ABE_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT		12
- + #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK		(1 << 12)
- + 
- + /* Used by CM_WKUP_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT			9
- + #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK			(1 << 9)
- + 
- + /* Used by CM1_ABE_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT			11
- + #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK			(1 << 11)
- + 
- + /* Used by CM1_ABE_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT			8
- + #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK			(1 << 8)
- + 
- + /* Used by CM_MEMIF_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT		11
- + #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK			(1 << 11)
- + 
- + /* Used by CM_MEMIF_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT		12
- + #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK		(1 << 12)
- + 
- + /* Used by CM_MEMIF_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT		13
- + #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK		(1 << 13)
- + 
- + /* Used by CM_CAM_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT		9
- + #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK		(1 << 9)
- + 
- + /* Used by CM_ALWON_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_SHIFT		12
- + #define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_MASK		(1 << 12)
- + 
- + /* Used by CM_EMU_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT		9
- + #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK		(1 << 9)
- + 
- + /* Used by CM_L4CFG_CLKSTCTRL */
- + #define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_SHIFT		9
- + #define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_MASK			(1 << 9)
- + 
- + /* Used by CM_CEFUSE_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT		9
- + #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK		(1 << 9)
- + 
- + /* Used by CM_MEMIF_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT			9
- + #define OMAP4430_CLKACTIVITY_DLL_CLK_MASK			(1 << 9)
- + 
- + /* Used by CM_L4PER_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT			9
- + #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK			(1 << 9)
- + 
- + /* Used by CM_L4PER_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT			10
- + #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK			(1 << 10)
- + 
- + /* Used by CM_L4PER_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT			11
- + #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK			(1 << 11)
- + 
- + /* Used by CM_L4PER_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT			12
- + #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK			(1 << 12)
- + 
- + /* Used by CM_L4PER_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT			13
- + #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK			(1 << 13)
- + 
- + /* Used by CM_L4PER_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT			14
- + #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK			(1 << 14)
- + 
- + /* Used by CM_DSS_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT		10
- + #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK		(1 << 10)
- + 
- + /* Used by CM_DSS_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT			9
- + #define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK			(1 << 9)
- + 
- + /* Used by CM_DUCATI_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT			8
- + #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK			(1 << 8)
- + 
- + /* Used by CM_EMU_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT			8
- + #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK			(1 << 8)
- + 
- + /* Used by CM_CAM_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT			10
- + #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK			(1 << 10)
- + 
- + /* Used by CM_L4PER_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT		15
- + #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK		(1 << 15)
- + 
- + /* Used by CM1_ABE_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT		10
- + #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK		(1 << 10)
- + 
- + /* Used by CM_DSS_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT		11
- + #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK		(1 << 11)
- + 
- + /* Used by CM_L3INIT_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT		20
- + #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK		(1 << 20)
- + 
- + /* Used by CM_L3INIT_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT		26
- + #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK			(1 << 26)
- + 
- + /* Used by CM_L3INIT_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT		21
- + #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK		(1 << 21)
- + 
- + /* Used by CM_L3INIT_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT		27
- + #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK			(1 << 27)
- + 
- + /* Used by CM_L3INIT_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT		13
- + #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK		(1 << 13)
- + 
- + /* Used by CM_L3INIT_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT		12
- + #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK		(1 << 12)
- + 
- + /* Used by CM_L3INIT_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT		28
- + #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK		(1 << 28)
- + 
- + /* Used by CM_L3INIT_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT		29
- + #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK		(1 << 29)
- + 
- + /* Used by CM_L3INIT_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT		11
- + #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK		(1 << 11)
- + 
- + /* Used by CM_L3INIT_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT		16
- + #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK		(1 << 16)
- + 
- + /* Used by CM_L3INIT_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT		17
- + #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK		(1 << 17)
- + 
- + /* Used by CM_L3INIT_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT		18
- + #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK		(1 << 18)
- + 
- + /* Used by CM_L3INIT_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT		19
- + #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK		(1 << 19)
- + 
- + /* Used by CM_CAM_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT			8
- + #define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK			(1 << 8)
- + 
- + /* Used by CM_IVAHD_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT		8
- + #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK		(1 << 8)
- + 
- + /* Used by CM_D2D_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT		10
- + #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK		(1 << 10)
- + 
- + /* Used by CM_L3_1_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT			8
- + #define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK			(1 << 8)
- + 
- + /* Used by CM_L3_2_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT			8
- + #define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK			(1 << 8)
- + 
- + /* Used by CM_D2D_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT			8
- + #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK			(1 << 8)
- + 
- + /* Used by CM_SDMA_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT			8
- + #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK			(1 << 8)
- + 
- + /* Used by CM_DSS_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT			8
- + #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK			(1 << 8)
- + 
- + /* Used by CM_MEMIF_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT		8
- + #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK			(1 << 8)
- + 
- + /* Used by CM_GFX_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT			8
- + #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK			(1 << 8)
- + 
- + /* Used by CM_L3INIT_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT		8
- + #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK			(1 << 8)
- + 
- + /* Used by CM_L3INSTR_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT		8
- + #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK		(1 << 8)
- + 
- + /* Used by CM_L4SEC_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT		8
- + #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK		(1 << 8)
- + 
- + /* Used by CM_ALWON_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT			8
- + #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK			(1 << 8)
- + 
- + /* Used by CM_CEFUSE_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT		8
- + #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK		(1 << 8)
- + 
- + /* Used by CM_L4CFG_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT			8
- + #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK			(1 << 8)
- + 
- + /* Used by CM_D2D_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT			9
- + #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK			(1 << 9)
- + 
- + /* Used by CM_L3INIT_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT		9
- + #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK			(1 << 9)
- + 
- + /* Used by CM_L4PER_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT			8
- + #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK			(1 << 8)
- + 
- + /* Used by CM_L4SEC_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT		9
- + #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK		(1 << 9)
- + 
- + /* Used by CM_WKUP_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT		12
- + #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK			(1 << 12)
- + 
- + /* Used by CM_MPU_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT			8
- + #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK			(1 << 8)
- + 
- + /* Used by CM1_ABE_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT		9
- + #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK			(1 << 9)
- + 
- + /* Used by CM_L4PER_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT		16
- + #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK		(1 << 16)
- + 
- + /* Used by CM_L4PER_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT		17
- + #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK			(1 << 17)
- + 
- + /* Used by CM_L4PER_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT		18
- + #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK			(1 << 18)
- + 
- + /* Used by CM_L4PER_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT		19
- + #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK			(1 << 19)
- + 
- + /* Used by CM_L4PER_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT		25
- + #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK		(1 << 25)
- + 
- + /* Used by CM_L4PER_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT		20
- + #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK		(1 << 20)
- + 
- + /* Used by CM_L4PER_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT		21
- + #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK		(1 << 21)
- + 
- + /* Used by CM_L4PER_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT		22
- + #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK		(1 << 22)
- + 
- + /* Used by CM_L4PER_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT		24
- + #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK			(1 << 24)
- + 
- + /* Used by CM_MEMIF_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT			10
- + #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK			(1 << 10)
- + 
- + /* Used by CM_GFX_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT			9
- + #define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK			(1 << 9)
- + 
- + /* Used by CM_ALWON_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT		11
- + #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK		(1 << 11)
- + 
- + /* Used by CM_ALWON_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT		10
- + #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK			(1 << 10)
- + 
- + /* Used by CM_ALWON_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT		9
- + #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK			(1 << 9)
- + 
- + /* Used by CM_WKUP_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT			8
- + #define OMAP4430_CLKACTIVITY_SYS_CLK_MASK			(1 << 8)
- + 
- + /* Used by CM_TESLA_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT		8
- + #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK		(1 << 8)
- + 
- + /* Used by CM_L3INIT_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT		22
- + #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK			(1 << 22)
- + 
- + /* Used by CM_L3INIT_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT		23
- + #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK			(1 << 23)
- + 
- + /* Used by CM_L3INIT_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT		24
- + #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK			(1 << 24)
- + 
- + /* Used by CM_L3INIT_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT		10
- + #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK		(1 << 10)
- + 
- + /* Used by CM_L3INIT_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT			14
- + #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK			(1 << 14)
- + 
- + /* Used by CM_L3INIT_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT		15
- + #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK		(1 << 15)
- + 
- + /* Used by CM_WKUP_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT			10
- + #define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK			(1 << 10)
- + 
- + /* Used by CM_L3INIT_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT		30
- + #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK			(1 << 30)
- + 
- + /* Used by CM_L3INIT_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT		25
- + #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK		(1 << 25)
- + 
- + /* Used by CM_WKUP_CLKSTCTRL */
- + #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT		11
- + #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK		(1 << 11)
- + 
- + /* Used by CM_WKUP_CLKSTCTRL */
- + #define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_SHIFT		13
- + #define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_MASK			(1 << 13)
- + 
- + /*
- +  * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL,
- +  * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
- +  * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MMC6_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
- +  * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL,
- +  * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL,
- +  * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL,
- +  * CM_WKUP_TIMER1_CLKCTRL
- +  */
- + #define OMAP4430_CLKSEL_SHIFT					24
- + #define OMAP4430_CLKSEL_MASK					(1 << 24)
- + 
- + /*
- +  * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL,
- +  * CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ, CM_L4_WKUP_CLKSEL
- +  */
- + #define OMAP4430_CLKSEL_0_0_SHIFT				0
- + #define OMAP4430_CLKSEL_0_0_MASK				(1 << 0)
- + 
- + /* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */
- + #define OMAP4430_CLKSEL_0_1_SHIFT				0
- + #define OMAP4430_CLKSEL_0_1_MASK				(0x3 << 0)
- + 
- + /* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */
- + #define OMAP4430_CLKSEL_24_25_SHIFT				24
- + #define OMAP4430_CLKSEL_24_25_MASK				(0x3 << 24)
- + 
- + /* Used by CM_L3INIT_USB_OTG_CLKCTRL */
- + #define OMAP4430_CLKSEL_60M_SHIFT				24
- + #define OMAP4430_CLKSEL_60M_MASK				(1 << 24)
- + 
- + /* Used by CM_MPU_MPU_CLKCTRL */
- + #define OMAP4460_CLKSEL_ABE_DIV_MODE_SHIFT			25
- + #define OMAP4460_CLKSEL_ABE_DIV_MODE_MASK			(1 << 25)
- + 
- + /* Used by CM1_ABE_AESS_CLKCTRL */
- + #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT				24
- + #define OMAP4430_CLKSEL_AESS_FCLK_MASK				(1 << 24)
- + 
- + /* Used by CM_CLKSEL_CORE */
- + #define OMAP4430_CLKSEL_CORE_SHIFT				0
- + #define OMAP4430_CLKSEL_CORE_MASK				(1 << 0)
- + 
- + /* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */
- + #define OMAP4430_CLKSEL_CORE_1_1_SHIFT				1
- + #define OMAP4430_CLKSEL_CORE_1_1_MASK				(1 << 1)
- + 
- + /* Used by CM_WKUP_USIM_CLKCTRL */
- + #define OMAP4430_CLKSEL_DIV_SHIFT				24
- + #define OMAP4430_CLKSEL_DIV_MASK				(1 << 24)
- + 
- + /* Used by CM_MPU_MPU_CLKCTRL */
- + #define OMAP4460_CLKSEL_EMIF_DIV_MODE_SHIFT			24
- + #define OMAP4460_CLKSEL_EMIF_DIV_MODE_MASK			(1 << 24)
- + 
- + /* Used by CM_CAM_FDIF_CLKCTRL */
- + #define OMAP4430_CLKSEL_FCLK_SHIFT				24
- + #define OMAP4430_CLKSEL_FCLK_MASK				(0x3 << 24)
- + 
- + /* Used by CM_L4PER_MCBSP4_CLKCTRL */
- + #define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT			25
- + #define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK			(1 << 25)
- + 
- + /*
- +  * Renamed from CLKSEL_INTERNAL_SOURCE Used by CM1_ABE_DMIC_CLKCTRL,
- +  * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
- +  * CM1_ABE_MCBSP3_CLKCTRL
- +  */
- + #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT	26
- + #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK	(0x3 << 26)
- + 
- + /* Used by CM_CLKSEL_CORE */
- + #define OMAP4430_CLKSEL_L3_SHIFT				4
- + #define OMAP4430_CLKSEL_L3_MASK					(1 << 4)
- + 
- + /* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
- + #define OMAP4430_CLKSEL_L3_SHADOW_SHIFT				2
- + #define OMAP4430_CLKSEL_L3_SHADOW_MASK				(1 << 2)
- + 
- + /* Used by CM_CLKSEL_CORE */
- + #define OMAP4430_CLKSEL_L4_SHIFT				8
- + #define OMAP4430_CLKSEL_L4_MASK					(1 << 8)
- + 
- + /* Used by CM_CLKSEL_ABE */
- + #define OMAP4430_CLKSEL_OPP_SHIFT				0
- + #define OMAP4430_CLKSEL_OPP_MASK				(0x3 << 0)
- + 
- + /* Used by CM_EMU_DEBUGSS_CLKCTRL */
- + #define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT			27
- + #define OMAP4430_CLKSEL_PMD_STM_CLK_MASK			(0x7 << 27)
- + 
- + /* Used by CM_EMU_DEBUGSS_CLKCTRL */
- + #define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT			24
- + #define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK			(0x7 << 24)
- + 
- + /* Used by CM_GFX_GFX_CLKCTRL */
- + #define OMAP4430_CLKSEL_SGX_FCLK_SHIFT				24
- + #define OMAP4430_CLKSEL_SGX_FCLK_MASK				(1 << 24)
- + 
- + /*
- +  * Used by CM1_ABE_DMIC_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL,
- +  * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL
- +  */
- + #define OMAP4430_CLKSEL_SOURCE_SHIFT				24
- + #define OMAP4430_CLKSEL_SOURCE_MASK				(0x3 << 24)
- + 
- + /* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */
- + #define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT			24
- + #define OMAP4430_CLKSEL_SOURCE_24_24_MASK			(1 << 24)
- + 
- + /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
- + #define OMAP4430_CLKSEL_UTMI_P1_SHIFT				24
- + #define OMAP4430_CLKSEL_UTMI_P1_MASK				(1 << 24)
- + 
- + /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
- + #define OMAP4430_CLKSEL_UTMI_P2_SHIFT				25
- + #define OMAP4430_CLKSEL_UTMI_P2_MASK				(1 << 25)
- + 
- + /*
- +  * Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL,
- +  * CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL,
- +  * CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL,
- +  * CM_L3INIT_CLKSTCTRL, CM_L3INSTR_CLKSTCTRL, CM_L3_1_CLKSTCTRL,
- +  * CM_L3_2_CLKSTCTRL, CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL,
- +  * CM_L4SEC_CLKSTCTRL, CM_MEMIF_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_SDMA_CLKSTCTRL,
- +  * CM_TESLA_CLKSTCTRL, CM_WKUP_CLKSTCTRL
- +  */
- + #define OMAP4430_CLKTRCTRL_SHIFT				0
- + #define OMAP4430_CLKTRCTRL_MASK					(0x3 << 0)
- + 
- + /* Used by CM_EMU_OVERRIDE_DPLL_CORE */
- + #define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT			0
- + #define OMAP4430_CORE_DPLL_EMU_DIV_MASK				(0x7f << 0)
- + 
- + /* Used by CM_EMU_OVERRIDE_DPLL_CORE */
- + #define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT			8
- + #define OMAP4430_CORE_DPLL_EMU_MULT_MASK			(0x7ff << 8)
- + 
- + /* Used by REVISION_CM1, REVISION_CM2 */
- + #define OMAP4430_CUSTOM_SHIFT					6
- + #define OMAP4430_CUSTOM_MASK					(0x3 << 6)
- + 
- + /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
- + #define OMAP4430_D2D_DYNDEP_SHIFT				18
- + #define OMAP4430_D2D_DYNDEP_MASK				(1 << 18)
- + 
- + /* Used by CM_MPU_STATICDEP */
- + #define OMAP4430_D2D_STATDEP_SHIFT				18
- + #define OMAP4430_D2D_STATDEP_MASK				(1 << 18)
- + 
- + /* Used by CM_CLKSEL_DPLL_MPU */
- + #define OMAP4460_DCC_COUNT_MAX_SHIFT				24
- + #define OMAP4460_DCC_COUNT_MAX_MASK				(0xff << 24)
- + 
- + /* Used by CM_CLKSEL_DPLL_MPU */
- + #define OMAP4460_DCC_EN_SHIFT					22
- + #define OMAP4460_DCC_EN_MASK					(1 << 22)
- + 
- + /*
- +  * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
- +  * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA,
- +  * CM_SSC_DELTAMSTEP_DPLL_MPU, CM_SSC_DELTAMSTEP_DPLL_PER,
- +  * CM_SSC_DELTAMSTEP_DPLL_UNIPRO, CM_SSC_DELTAMSTEP_DPLL_USB
- +  */
- + #define OMAP4430_DELTAMSTEP_SHIFT				0
- + #define OMAP4430_DELTAMSTEP_MASK				(0xfffff << 0)
- + 
- + /* Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_USB */
- + #define OMAP4460_DELTAMSTEP_0_20_SHIFT				0
- + #define OMAP4460_DELTAMSTEP_0_20_MASK				(0x1fffff << 0)
- + 
- + /* Used by CM_DLL_CTRL */
- + #define OMAP4430_DLL_OVERRIDE_SHIFT				0
- + #define OMAP4430_DLL_OVERRIDE_MASK				(1 << 0)
- + 
- + /* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */
- + #define OMAP4430_DLL_OVERRIDE_2_2_SHIFT				2
- + #define OMAP4430_DLL_OVERRIDE_2_2_MASK				(1 << 2)
- + 
- + /* Used by CM_SHADOW_FREQ_CONFIG1 */
- + #define OMAP4430_DLL_RESET_SHIFT				3
- + #define OMAP4430_DLL_RESET_MASK					(1 << 3)
- + 
- + /*
- +  * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
- +  * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
- +  * CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB
- +  */
- + #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT				23
- + #define OMAP4430_DPLL_BYP_CLKSEL_MASK				(1 << 23)
- + 
- + /* Used by CM_CLKDCOLDO_DPLL_USB */
- + #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT			8
- + #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK			(1 << 8)
- + 
- + /* Used by CM_CLKSEL_DPLL_CORE */
- + #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT			20
- + #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK			(1 << 20)
- + 
- + /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
- + #define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT			0
- + #define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK			(0x1f << 0)
- + 
- + /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
- + #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT			5
- + #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK			(1 << 5)
- + 
- + /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
- + #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT			8
- + #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK			(1 << 8)
- + 
- + /* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
- + #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT			10
- + #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK			(1 << 10)
- + 
- + /*
- +  * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
- +  * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
- +  */
- + #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT				0
- + #define OMAP4430_DPLL_CLKOUT_DIV_MASK				(0x1f << 0)
- + 
- + /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */
- + #define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT			0
- + #define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK			(0x7f << 0)
- + 
- + /*
- +  * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
- +  * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
- +  */
- + #define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT			5
- + #define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK			(1 << 5)
- + 
- + /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */
- + #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT		7
- + #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK		(1 << 7)
- + 
- + /*
- +  * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
- +  * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
- +  */
- + #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT			8
- + #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK			(1 << 8)
- + 
- + /* Used by CM_SHADOW_FREQ_CONFIG1 */
- + #define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT			8
- + #define OMAP4430_DPLL_CORE_DPLL_EN_MASK				(0x7 << 8)
- + 
- + /* Used by CM_SHADOW_FREQ_CONFIG1 */
- + #define OMAP4430_DPLL_CORE_M2_DIV_SHIFT				11
- + #define OMAP4430_DPLL_CORE_M2_DIV_MASK				(0x1f << 11)
- + 
- + /* Used by CM_SHADOW_FREQ_CONFIG2 */
- + #define OMAP4430_DPLL_CORE_M5_DIV_SHIFT				3
- + #define OMAP4430_DPLL_CORE_M5_DIV_MASK				(0x1f << 3)
- + 
- + /*
- +  * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
- +  * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
- +  * CM_CLKSEL_DPLL_UNIPRO
- +  */
- + #define OMAP4430_DPLL_DIV_SHIFT					0
- + #define OMAP4430_DPLL_DIV_MASK					(0x7f << 0)
- + 
- + /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */
- + #define OMAP4430_DPLL_DIV_0_7_SHIFT				0
- + #define OMAP4430_DPLL_DIV_0_7_MASK				(0xff << 0)
- + 
- + /*
- +  * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
- +  * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
- +  */
- + #define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT			8
- + #define OMAP4430_DPLL_DRIFTGUARD_EN_MASK			(1 << 8)
- + 
- + /* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */
- + #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT			3
- + #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK			(1 << 3)
- + 
- + /*
- +  * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
- +  * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
- +  * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
- +  */
- + #define OMAP4430_DPLL_EN_SHIFT					0
- + #define OMAP4430_DPLL_EN_MASK					(0x7 << 0)
- + 
- + /*
- +  * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
- +  * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
- +  * CM_CLKMODE_DPLL_UNIPRO
- +  */
- + #define OMAP4430_DPLL_LPMODE_EN_SHIFT				10
- + #define OMAP4430_DPLL_LPMODE_EN_MASK				(1 << 10)
- + 
- + /*
- +  * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
- +  * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
- +  * CM_CLKSEL_DPLL_UNIPRO
- +  */
- + #define OMAP4430_DPLL_MULT_SHIFT				8
- + #define OMAP4430_DPLL_MULT_MASK					(0x7ff << 8)
- + 
- + /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */
- + #define OMAP4430_DPLL_MULT_USB_SHIFT				8
- + #define OMAP4430_DPLL_MULT_USB_MASK				(0xfff << 8)
- + 
- + /*
- +  * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
- +  * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
- +  * CM_CLKMODE_DPLL_UNIPRO
- +  */
- + #define OMAP4430_DPLL_REGM4XEN_SHIFT				11
- + #define OMAP4430_DPLL_REGM4XEN_MASK				(1 << 11)
- + 
- + /* Used by CM_CLKSEL_DPLL_USB */
- + #define OMAP4430_DPLL_SD_DIV_SHIFT				24
- + #define OMAP4430_DPLL_SD_DIV_MASK				(0xff << 24)
- + 
- + /*
- +  * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
- +  * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
- +  * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
- +  */
- + #define OMAP4430_DPLL_SSC_ACK_SHIFT				13
- + #define OMAP4430_DPLL_SSC_ACK_MASK				(1 << 13)
- + 
- + /*
- +  * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
- +  * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
- +  * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
- +  */
- + #define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT			14
- + #define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK			(1 << 14)
- + 
- + /*
- +  * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
- +  * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
- +  * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
- +  */
- + #define OMAP4430_DPLL_SSC_EN_SHIFT				12
- + #define OMAP4430_DPLL_SSC_EN_MASK				(1 << 12)
- + 
- + /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
- + #define OMAP4430_DSS_DYNDEP_SHIFT				8
- + #define OMAP4430_DSS_DYNDEP_MASK				(1 << 8)
- + 
- + /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
- + #define OMAP4430_DSS_STATDEP_SHIFT				8
- + #define OMAP4430_DSS_STATDEP_MASK				(1 << 8)
- + 
- + /* Used by CM_L3_2_DYNAMICDEP */
- + #define OMAP4430_DUCATI_DYNDEP_SHIFT				0
- + #define OMAP4430_DUCATI_DYNDEP_MASK				(1 << 0)
- + 
- + /* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
- + #define OMAP4430_DUCATI_STATDEP_SHIFT				0
- + #define OMAP4430_DUCATI_STATDEP_MASK				(1 << 0)
- + 
- + /* Used by CM_SHADOW_FREQ_CONFIG1 */
- + #define OMAP4430_FREQ_UPDATE_SHIFT				0
- + #define OMAP4430_FREQ_UPDATE_MASK				(1 << 0)
- + 
- + /* Used by REVISION_CM1, REVISION_CM2 */
- + #define OMAP4430_FUNC_SHIFT					16
- + #define OMAP4430_FUNC_MASK					(0xfff << 16)
- + 
- + /* Used by CM_L3_2_DYNAMICDEP */
- + #define OMAP4430_GFX_DYNDEP_SHIFT				10
- + #define OMAP4430_GFX_DYNDEP_MASK				(1 << 10)
- + 
- + /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
- + #define OMAP4430_GFX_STATDEP_SHIFT				10
- + #define OMAP4430_GFX_STATDEP_MASK				(1 << 10)
- + 
- + /* Used by CM_SHADOW_FREQ_CONFIG2 */
- + #define OMAP4430_GPMC_FREQ_UPDATE_SHIFT				0
- + #define OMAP4430_GPMC_FREQ_UPDATE_MASK				(1 << 0)
- + 
- + /*
- +  * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
- +  * CM_DIV_M4_DPLL_PER
- +  */
- + #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT			0
- + #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK			(0x1f << 0)
- + 
- + /*
- +  * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
- +  * CM_DIV_M4_DPLL_PER
- +  */
- + #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT		5
- + #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK		(1 << 5)
- + 
- + /*
- +  * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
- +  * CM_DIV_M4_DPLL_PER
- +  */
- + #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT		8
- + #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK		(1 << 8)
- + 
- + /*
- +  * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
- +  * CM_DIV_M4_DPLL_PER
- +  */
- + #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT			12
- + #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK			(1 << 12)
- + 
- + /*
- +  * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
- +  * CM_DIV_M5_DPLL_PER
- +  */
- + #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT			0
- + #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK			(0x1f << 0)
- + 
- + /*
- +  * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
- +  * CM_DIV_M5_DPLL_PER
- +  */
- + #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT		5
- + #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK		(1 << 5)
- + 
- + /*
- +  * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
- +  * CM_DIV_M5_DPLL_PER
- +  */
- + #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT		8
- + #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK		(1 << 8)
- + 
- + /*
- +  * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
- +  * CM_DIV_M5_DPLL_PER
- +  */
- + #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT			12
- + #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK			(1 << 12)
- + 
- + /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
- + #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT			0
- + #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK			(0x1f << 0)
- + 
- + /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
- + #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT		5
- + #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK		(1 << 5)
- + 
- + /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
- + #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT		8
- + #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK		(1 << 8)
- + 
- + /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
- + #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT			12
- + #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK			(1 << 12)
- + 
- + /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
- + #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT			0
- + #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK			(0x1f << 0)
- + 
- + /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
- + #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT		5
- + #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK		(1 << 5)
- + 
- + /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
- + #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT		8
- + #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK		(1 << 8)
- + 
- + /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
- + #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT			12
- + #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK			(1 << 12)
- + 
- + /*
- +  * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL,
- +  * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
- +  * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL,
- +  * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
- +  * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
- +  * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
- +  * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
- +  * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
- +  * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
- +  * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
- +  * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
- +  * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
- +  * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
- +  * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
- +  * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
- +  * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
- +  * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
- +  * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL,
- +  * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL,
- +  * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
- +  * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
- +  * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
- +  * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
- +  * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
- +  * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
- +  * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
- +  * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
- +  * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL,
- +  * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL,
- +  * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL,
- +  * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL,
- +  * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL,
- +  * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL,
- +  * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
- +  * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
- +  * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
- +  * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
- +  * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL,
- +  * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
- +  * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
- +  * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
- +  * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL,
- +  * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL,
- +  * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL,
- +  * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
- +  */
- + #define OMAP4430_IDLEST_SHIFT					16
- + #define OMAP4430_IDLEST_MASK					(0x3 << 16)
- + 
- + /* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
- + #define OMAP4430_ISS_DYNDEP_SHIFT				9
- + #define OMAP4430_ISS_DYNDEP_MASK				(1 << 9)
- + 
- + /*
- +  * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
- +  * CM_TESLA_STATICDEP
- +  */
- + #define OMAP4430_ISS_STATDEP_SHIFT				9
- + #define OMAP4430_ISS_STATDEP_MASK				(1 << 9)
- + 
- + /* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
- + #define OMAP4430_IVAHD_DYNDEP_SHIFT				2
- + #define OMAP4430_IVAHD_DYNDEP_MASK				(1 << 2)
- + 
- + /*
- +  * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
- +  * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_L3INIT_STATICDEP,
- +  * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
- +  */
- + #define OMAP4430_IVAHD_STATDEP_SHIFT				2
- + #define OMAP4430_IVAHD_STATDEP_MASK				(1 << 2)
- + 
- + /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
- + #define OMAP4430_L3INIT_DYNDEP_SHIFT				7
- + #define OMAP4430_L3INIT_DYNDEP_MASK				(1 << 7)
- + 
- + /*
- +  * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_MPU_STATICDEP,
- +  * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
- +  */
- + #define OMAP4430_L3INIT_STATDEP_SHIFT				7
- + #define OMAP4430_L3INIT_STATDEP_MASK				(1 << 7)
- + 
- + /*
- +  * Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
- +  * CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
- +  */
- + #define OMAP4430_L3_1_DYNDEP_SHIFT				5
- + #define OMAP4430_L3_1_DYNDEP_MASK				(1 << 5)
- + 
- + /*
- +  * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
- +  * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
- +  * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
- +  * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
- +  */
- + #define OMAP4430_L3_1_STATDEP_SHIFT				5
- + #define OMAP4430_L3_1_STATDEP_MASK				(1 << 5)
- + 
- + /*
- +  * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP,
- +  * CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP, CM_IVAHD_DYNAMICDEP,
- +  * CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
- +  * CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP
- +  */
- + #define OMAP4430_L3_2_DYNDEP_SHIFT				6
- + #define OMAP4430_L3_2_DYNDEP_MASK				(1 << 6)
- + 
- + /*
- +  * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
- +  * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
- +  * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
- +  * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
- +  */
- + #define OMAP4430_L3_2_STATDEP_SHIFT				6
- + #define OMAP4430_L3_2_STATDEP_MASK				(1 << 6)
- + 
- + /* Used by CM_L3_1_DYNAMICDEP */
- + #define OMAP4430_L4CFG_DYNDEP_SHIFT				12
- + #define OMAP4430_L4CFG_DYNDEP_MASK				(1 << 12)
- + 
- + /*
- +  * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
- +  * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
- +  */
- + #define OMAP4430_L4CFG_STATDEP_SHIFT				12
- + #define OMAP4430_L4CFG_STATDEP_MASK				(1 << 12)
- + 
- + /* Used by CM_L3_2_DYNAMICDEP */
- + #define OMAP4430_L4PER_DYNDEP_SHIFT				13
- + #define OMAP4430_L4PER_DYNDEP_MASK				(1 << 13)
- + 
- + /*
- +  * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
- +  * CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
- +  */
- + #define OMAP4430_L4PER_STATDEP_SHIFT				13
- + #define OMAP4430_L4PER_STATDEP_MASK				(1 << 13)
- + 
- + /* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
- + #define OMAP4430_L4SEC_DYNDEP_SHIFT				14
- + #define OMAP4430_L4SEC_DYNDEP_MASK				(1 << 14)
- + 
- + /*
- +  * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
- +  * CM_SDMA_STATICDEP
- +  */
- + #define OMAP4430_L4SEC_STATDEP_SHIFT				14
- + #define OMAP4430_L4SEC_STATDEP_MASK				(1 << 14)
- + 
- + /* Used by CM_L4CFG_DYNAMICDEP */
- + #define OMAP4430_L4WKUP_DYNDEP_SHIFT				15
- + #define OMAP4430_L4WKUP_DYNDEP_MASK				(1 << 15)
- + 
- + /*
- +  * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
- +  * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
- +  */
- + #define OMAP4430_L4WKUP_STATDEP_SHIFT				15
- + #define OMAP4430_L4WKUP_STATDEP_MASK				(1 << 15)
- + 
- + /*
- +  * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
- +  * CM_MPU_DYNAMICDEP
- +  */
- + #define OMAP4430_MEMIF_DYNDEP_SHIFT				4
- + #define OMAP4430_MEMIF_DYNDEP_MASK				(1 << 4)
- + 
- + /*
- +  * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
- +  * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
- +  * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
- +  * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
- +  */
- + #define OMAP4430_MEMIF_STATDEP_SHIFT				4
- + #define OMAP4430_MEMIF_STATDEP_MASK				(1 << 4)
- + 
- + /*
- +  * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
- +  * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
- +  * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER,
- +  * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
- +  */
- + #define OMAP4430_MODFREQDIV_EXPONENT_SHIFT			8
- + #define OMAP4430_MODFREQDIV_EXPONENT_MASK			(0x7 << 8)
- + 
- + /*
- +  * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
- +  * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
- +  * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER,
- +  * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
- +  */
- + #define OMAP4430_MODFREQDIV_MANTISSA_SHIFT			0
- + #define OMAP4430_MODFREQDIV_MANTISSA_MASK			(0x7f << 0)
- + 
- + /*
- +  * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL,
- +  * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
- +  * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL,
- +  * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
- +  * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
- +  * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
- +  * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
- +  * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
- +  * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
- +  * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
- +  * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
- +  * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
- +  * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
- +  * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
- +  * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
- +  * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
- +  * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
- +  * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL,
- +  * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL,
- +  * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
- +  * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
- +  * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
- +  * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
- +  * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
- +  * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
- +  * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
- +  * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
- +  * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL,
- +  * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL,
- +  * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL,
- +  * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL,
- +  * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL,
- +  * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL,
- +  * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
- +  * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
- +  * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
- +  * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
- +  * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL,
- +  * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
- +  * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
- +  * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
- +  * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL,
- +  * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL,
- +  * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL,
- +  * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
- +  */
- + #define OMAP4430_MODULEMODE_SHIFT				0
- + #define OMAP4430_MODULEMODE_MASK				(0x3 << 0)
- + 
- + /* Used by CM_L4CFG_DYNAMICDEP */
- + #define OMAP4460_MPU_DYNDEP_SHIFT				19
- + #define OMAP4460_MPU_DYNDEP_MASK				(1 << 19)
- + 
- + /* Used by CM_DSS_DSS_CLKCTRL */
- + #define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT			9
- + #define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK			(1 << 9)
- + 
- + /* Used by CM_WKUP_BANDGAP_CLKCTRL */
- + #define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT			8
- + #define OMAP4430_OPTFCLKEN_BGAP_32K_MASK			(1 << 8)
- + 
- + /* Used by CM_ALWON_USBPHY_CLKCTRL */
- + #define OMAP4430_OPTFCLKEN_CLK32K_SHIFT				8
- + #define OMAP4430_OPTFCLKEN_CLK32K_MASK				(1 << 8)
- + 
- + /* Used by CM_CAM_ISS_CLKCTRL */
- + #define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT			8
- + #define OMAP4430_OPTFCLKEN_CTRLCLK_MASK				(1 << 8)
- + 
- + /*
- +  * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL,
- +  * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL,
- +  * CM_WKUP_GPIO1_CLKCTRL
- +  */
- + #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT				8
- + #define OMAP4430_OPTFCLKEN_DBCLK_MASK				(1 << 8)
- + 
- + /* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */
- + #define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT			8
- + #define OMAP4430_OPTFCLKEN_DLL_CLK_MASK				(1 << 8)
- + 
- + /* Used by CM_DSS_DSS_CLKCTRL */
- + #define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT				8
- + #define OMAP4430_OPTFCLKEN_DSSCLK_MASK				(1 << 8)
- + 
- + /* Used by CM_WKUP_USIM_CLKCTRL */
- + #define OMAP4430_OPTFCLKEN_FCLK_SHIFT				8
- + #define OMAP4430_OPTFCLKEN_FCLK_MASK				(1 << 8)
- + 
- + /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
- + #define OMAP4430_OPTFCLKEN_FCLK0_SHIFT				8
- + #define OMAP4430_OPTFCLKEN_FCLK0_MASK				(1 << 8)
- + 
- + /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
- + #define OMAP4430_OPTFCLKEN_FCLK1_SHIFT				9
- + #define OMAP4430_OPTFCLKEN_FCLK1_MASK				(1 << 9)
- + 
- + /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
- + #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT				10
- + #define OMAP4430_OPTFCLKEN_FCLK2_MASK				(1 << 10)
- + 
- + /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
- + #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT			15
- + #define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK			(1 << 15)
- + 
- + /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
- + #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT		13
- + #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK			(1 << 13)
- + 
- + /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
- + #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT		14
- + #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK			(1 << 14)
- + 
- + /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
- + #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT			11
- + #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK			(1 << 11)
- + 
- + /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
- + #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT			12
- + #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK			(1 << 12)
- + 
- + /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
- + #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT			8
- + #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK			(1 << 8)
- + 
- + /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
- + #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT		9
- + #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK			(1 << 9)
- + 
- + /* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */
- + #define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT			8
- + #define OMAP4430_OPTFCLKEN_PHY_48M_MASK				(1 << 8)
- + 
- + /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
- + #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT			10
- + #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK			(1 << 10)
- + 
- + /* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */
- + #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT		11
- + #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK		(1 << 11)
- + 
- + /* Used by CM_DSS_DSS_CLKCTRL */
- + #define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT			10
- + #define OMAP4430_OPTFCLKEN_SYS_CLK_MASK				(1 << 10)
- + 
- + /* Used by CM_WKUP_BANDGAP_CLKCTRL */
- + #define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT			8
- + #define OMAP4460_OPTFCLKEN_TS_FCLK_MASK				(1 << 8)
- + 
- + /* Used by CM_DSS_DSS_CLKCTRL */
- + #define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT				11
- + #define OMAP4430_OPTFCLKEN_TV_CLK_MASK				(1 << 11)
- + 
- + /* Used by CM_L3INIT_UNIPRO1_CLKCTRL */
- + #define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT			8
- + #define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK			(1 << 8)
- + 
- + /* Used by CM_L3INIT_USB_TLL_CLKCTRL */
- + #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT			8
- + #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK			(1 << 8)
- + 
- + /* Used by CM_L3INIT_USB_TLL_CLKCTRL */
- + #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT			9
- + #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK			(1 << 9)
- + 
- + /* Used by CM_L3INIT_USB_TLL_CLKCTRL */
- + #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT			10
- + #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK			(1 << 10)
- + 
- + /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
- + #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT			8
- + #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK			(1 << 8)
- + 
- + /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
- + #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT			9
- + #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK			(1 << 9)
- + 
- + /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
- + #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT			10
- + #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK			(1 << 10)
- + 
- + /* Used by CM_L3INIT_USB_OTG_CLKCTRL */
- + #define OMAP4430_OPTFCLKEN_XCLK_SHIFT				8
- + #define OMAP4430_OPTFCLKEN_XCLK_MASK				(1 << 8)
- + 
- + /* Used by CM_EMU_OVERRIDE_DPLL_CORE */
- + #define OMAP4430_OVERRIDE_ENABLE_SHIFT				19
- + #define OMAP4430_OVERRIDE_ENABLE_MASK				(1 << 19)
- + 
- + /* Used by CM_CLKSEL_ABE */
- + #define OMAP4430_PAD_CLKS_GATE_SHIFT				8
- + #define OMAP4430_PAD_CLKS_GATE_MASK				(1 << 8)
- + 
- + /* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */
- + #define OMAP4430_PERF_CURRENT_SHIFT				0
- + #define OMAP4430_PERF_CURRENT_MASK				(0xff << 0)
- + 
- + /*
- +  * Used by CM_CORE_DVFS_PERF1, CM_CORE_DVFS_PERF2, CM_CORE_DVFS_PERF3,
- +  * CM_CORE_DVFS_PERF4, CM_IVA_DVFS_PERF_ABE, CM_IVA_DVFS_PERF_IVAHD,
- +  * CM_IVA_DVFS_PERF_TESLA
- +  */
- + #define OMAP4430_PERF_REQ_SHIFT					0
- + #define OMAP4430_PERF_REQ_MASK					(0xff << 0)
- + 
- + /* Used by CM_RESTORE_ST */
- + #define OMAP4430_PHASE1_COMPLETED_SHIFT				0
- + #define OMAP4430_PHASE1_COMPLETED_MASK				(1 << 0)
- + 
- + /* Used by CM_RESTORE_ST */
- + #define OMAP4430_PHASE2A_COMPLETED_SHIFT			1
- + #define OMAP4430_PHASE2A_COMPLETED_MASK				(1 << 1)
- + 
- + /* Used by CM_RESTORE_ST */
- + #define OMAP4430_PHASE2B_COMPLETED_SHIFT			2
- + #define OMAP4430_PHASE2B_COMPLETED_MASK				(1 << 2)
- + 
- + /* Used by CM_EMU_DEBUGSS_CLKCTRL */
- + #define OMAP4430_PMD_STM_MUX_CTRL_SHIFT				20
- + #define OMAP4430_PMD_STM_MUX_CTRL_MASK				(0x3 << 20)
- + 
- + /* Used by CM_EMU_DEBUGSS_CLKCTRL */
- + #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT			22
- + #define OMAP4430_PMD_TRACE_MUX_CTRL_MASK			(0x3 << 22)
- + 
- + /* Used by CM_DYN_DEP_PRESCAL */
- + #define OMAP4430_PRESCAL_SHIFT					0
- + #define OMAP4430_PRESCAL_MASK					(0x3f << 0)
- + 
- + /* Used by REVISION_CM1, REVISION_CM2 */
- + #define OMAP4430_R_RTL_SHIFT					11
- + #define OMAP4430_R_RTL_MASK					(0x1f << 11)
- + 
- + /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL */
- + #define OMAP4430_SAR_MODE_SHIFT					4
- + #define OMAP4430_SAR_MODE_MASK					(1 << 4)
- + 
- + /* Used by CM_SCALE_FCLK */
- + #define OMAP4430_SCALE_FCLK_SHIFT				0
- + #define OMAP4430_SCALE_FCLK_MASK				(1 << 0)
- + 
- + /* Used by REVISION_CM1, REVISION_CM2 */
- + #define OMAP4430_SCHEME_SHIFT					30
- + #define OMAP4430_SCHEME_MASK					(0x3 << 30)
- + 
- + /* Used by CM_L4CFG_DYNAMICDEP */
- + #define OMAP4430_SDMA_DYNDEP_SHIFT				11
- + #define OMAP4430_SDMA_DYNDEP_MASK				(1 << 11)
- + 
- + /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
- + #define OMAP4430_SDMA_STATDEP_SHIFT				11
- + #define OMAP4430_SDMA_STATDEP_MASK				(1 << 11)
- + 
- + /* Used by CM_CLKSEL_ABE */
- + #define OMAP4430_SLIMBUS_CLK_GATE_SHIFT				10
- + #define OMAP4430_SLIMBUS_CLK_GATE_MASK				(1 << 10)
- + 
- + /*
- +  * Used by CM1_ABE_AESS_CLKCTRL, CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL,
- +  * CM_D2D_SAD2D_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL,
- +  * CM_DUCATI_DUCATI_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL,
- +  * CM_IVAHD_IVAHD_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
- +  * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
- +  * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
- +  * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
- +  * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
- +  * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL,
- +  * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
- +  * CM_TESLA_TESLA_CLKCTRL
- +  */
- + #define OMAP4430_STBYST_SHIFT					18
- + #define OMAP4430_STBYST_MASK					(1 << 18)
- + 
- + /*
- +  * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY,
- +  * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER,
- +  * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB
- +  */
- + #define OMAP4430_ST_DPLL_CLK_SHIFT				0
- + #define OMAP4430_ST_DPLL_CLK_MASK				(1 << 0)
- + 
- + /* Used by CM_CLKDCOLDO_DPLL_USB */
- + #define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT			9
- + #define OMAP4430_ST_DPLL_CLKDCOLDO_MASK				(1 << 9)
- + 
- + /*
- +  * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
- +  * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
- +  */
- + #define OMAP4430_ST_DPLL_CLKOUT_SHIFT				9
- + #define OMAP4430_ST_DPLL_CLKOUT_MASK				(1 << 9)
- + 
- + /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
- + #define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT			9
- + #define OMAP4430_ST_DPLL_CLKOUTHIF_MASK				(1 << 9)
- + 
- + /* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
- + #define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT				11
- + #define OMAP4430_ST_DPLL_CLKOUTX2_MASK				(1 << 11)
- + 
- + /*
- +  * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
- +  * CM_DIV_M4_DPLL_PER
- +  */
- + #define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT			9
- + #define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK			(1 << 9)
- + 
- + /*
- +  * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
- +  * CM_DIV_M5_DPLL_PER
- +  */
- + #define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT			9
- + #define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK			(1 << 9)
- + 
- + /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
- + #define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT			9
- + #define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK			(1 << 9)
- + 
- + /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
- + #define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT			9
- + #define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK			(1 << 9)
- + 
- + /*
- +  * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY,
- +  * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER,
- +  * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB
- +  */
- + #define OMAP4430_ST_MN_BYPASS_SHIFT				8
- + #define OMAP4430_ST_MN_BYPASS_MASK				(1 << 8)
- + 
- + /* Used by CM_SYS_CLKSEL */
- + #define OMAP4430_SYS_CLKSEL_SHIFT				0
- + #define OMAP4430_SYS_CLKSEL_MASK				(0x7 << 0)
- + 
- + /* Used by CM_L4CFG_DYNAMICDEP */
- + #define OMAP4430_TESLA_DYNDEP_SHIFT				1
- + #define OMAP4430_TESLA_DYNDEP_MASK				(1 << 1)
- + 
- + /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
- + #define OMAP4430_TESLA_STATDEP_SHIFT				1
- + #define OMAP4430_TESLA_STATDEP_MASK				(1 << 1)
- + 
- + /*
- +  * Used by CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP,
- +  * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
- +  * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
- +  */
- + #define OMAP4430_WINDOWSIZE_SHIFT				24
- + #define OMAP4430_WINDOWSIZE_MASK				(0xf << 24)
- + 
- + /* Used by REVISION_CM1, REVISION_CM2 */
- + #define OMAP4430_X_MAJOR_SHIFT					8
- + #define OMAP4430_X_MAJOR_MASK					(0x7 << 8)
- + 
- + /* Used by REVISION_CM1, REVISION_CM2 */
- + #define OMAP4430_Y_MINOR_SHIFT					0
- + #define OMAP4430_Y_MINOR_MASK					(0x3f << 0)
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/common.c linux-3.2.1/arch/arm/mach-ckb_3352/common.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/common.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/common.c	2014-05-15 13:25:13.891248083 +0900
- ***************
- *** 0 ****
- --- 1,322 ----
- + /*
- +  * linux/arch/arm/mach-omap2/common.c
- +  *
- +  * Code common to all OMAP2+ machines.
- +  *
- +  * Copyright (C) 2009 Texas Instruments
- +  * Copyright (C) 2010 Nokia Corporation
- +  * Tony Lindgren <tony@atomide.com>
- +  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + #include <linux/kernel.h>
- + #include <linux/init.h>
- + #include <linux/clk.h>
- + #include <linux/io.h>
- + #include <linux/module.h>
- + 
- + #include <asm/cputype.h>
- + 
- + #include <plat/cpu.h>
- + 
- + #include "common.h"
- + #include <plat/board.h>
- + #include <plat/mux.h>
- + 
- + #include <plat/clock.h>
- + 
- + #include "sdrc.h"
- + #include "control.h"
- + 
- + /* Global address base setup code */
- + 
- + 
- + static void __init __omap2_set_globals(struct omap_globals *omap2_globals)
- + {
- + 	omap2_set_globals_tap(omap2_globals);
- + 	omap2_set_globals_sdrc(omap2_globals);
- + 	omap2_set_globals_control(omap2_globals);
- + 	omap2_set_globals_prcm(omap2_globals);
- + }
- + 
- + #define AM33XX_TAP_BASE		(AM33XX_CTRL_BASE + \
- + 				TI81XX_CONTROL_DEVICE_ID - 0x204)
- + 
- + static struct omap_globals am33xx_globals = {
- + 	.class  = AM335X_CLASS,
- + 	.tap    = AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE),
- + 	.ctrl   = AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
- + 	.prm    = AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE),
- + 	.cm     = AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE),
- + };
- + 
- + void __init omap2_set_globals_am33xx(void)
- + {
- + 	__omap2_set_globals(&am33xx_globals);
- + }
- + 
- + void __init am33xx_map_io(void)
- + {
- + 	omapam33xx_map_common_io();
- + }
- + 
- + 
- + static unsigned int omap_revision;
- + static const char *cpu_rev;
- + u32 omap_features;
- + 
- + unsigned int omap_rev(void)
- + {
- + 	return omap_revision;
- + }
- + EXPORT_SYMBOL(omap_rev);
- + 
- + int omap_type(void)
- + {
- + 	u32 val = 0;
- + 
- + 	val = omap_ctrl_readl(AM33XX_CONTROL_STATUS_OFF);
- + 	val &= OMAP2_DEVICETYPE_MASK;
- + 	val >>= 8;
- + 
- + out:
- + 	return val;
- + }
- + EXPORT_SYMBOL(omap_type);
- + 
- + 
- + /*----------------------------------------------------------------------------*/
- + 
- + #define OMAP_TAP_IDCODE		0x0204
- + #define OMAP_TAP_DIE_ID_0	0x0218
- + #define OMAP_TAP_DIE_ID_1	0x021C
- + #define OMAP_TAP_DIE_ID_2	0x0220
- + #define OMAP_TAP_DIE_ID_3	0x0224
- + 
- + #define OMAP_TAP_DIE_ID_44XX_0	0x0200
- + #define OMAP_TAP_DIE_ID_44XX_1	0x0208
- + #define OMAP_TAP_DIE_ID_44XX_2	0x020c
- + #define OMAP_TAP_DIE_ID_44XX_3	0x0210
- + 
- + #define read_tap_reg(reg)	__raw_readl(tap_base  + (reg))
- + 
- + static void __iomem *tap_base;
- + static u16 tap_prod_id;
- + 
- + 
- + #define OMAP3_SHOW_FEATURE(feat)		\
- + 	if (omap3_has_ ##feat())		\
- + 		printk(#feat" ");
- + 
- + static void __init omap3_cpuinfo(void)
- + {
- + 	const char *cpu_name;
- + 
- + 	/*
- + 	 * OMAP3430 and OMAP3530 are assumed to be same.
- + 	 *
- + 	 * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
- + 	 * on available features. Upon detection, update the CPU id
- + 	 * and CPU class bits.
- + 	 */
- + 	cpu_name =  "AM335X";
- + 	
- + 	/* Print verbose information */
- + 	pr_info("%s ES%s (", cpu_name, cpu_rev);
- + 
- + 	OMAP3_SHOW_FEATURE(l2cache);
- + 	OMAP3_SHOW_FEATURE(iva);
- + 	OMAP3_SHOW_FEATURE(sgx);
- + 	OMAP3_SHOW_FEATURE(neon);
- + 	OMAP3_SHOW_FEATURE(isp);
- + 	OMAP3_SHOW_FEATURE(192mhz_clk);
- + 
- + 	printk(")\n");
- + }
- + 
- + #define OMAP3_CHECK_FEATURE(status,feat)				\
- + 	if (((status & OMAP3_ ##feat## _MASK) 				\
- + 		>> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { 	\
- + 		omap_features |= OMAP3_HAS_ ##feat;			\
- + 	}
- + 
- + void __init am33xx_check_features(void)
- + {
- + 	u32 status;
- + 
- + 	omap_features = OMAP3_HAS_NEON;
- + 
- + 	status = omap_ctrl_readl(AM33XX_DEV_FEATURE);
- + 	if (status & AM33XX_SGX_MASK)
- + 		omap_features |= OMAP3_HAS_SGX;
- + 
- + 	omap3_cpuinfo();
- + }
- + 
- + void __init omap3xxx_check_revision(void)
- + {
- + 	u32 cpuid, idcode;
- + 	u16 hawkeye;
- + 	u8 rev;
- + 
- + 	/*
- + 	 * We cannot access revision registers on ES1.0.
- + 	 * If the processor type is Cortex-A8 and the revision is 0x0
- + 	 * it means its Cortex r0p0 which is 3430 ES1.0.
- + 	 */
- + 	cpuid = read_cpuid(CPUID_ID);
- + 	if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
- + 		omap_revision = OMAP3430_REV_ES1_0;
- + 		cpu_rev = "1.0";
- + 		return;
- + 	}
- + 
- + 	/*
- + 	 * Detection for 34xx ES2.0 and above can be done with just
- + 	 * hawkeye and rev. See TRM 1.5.2 Device Identification.
- + 	 * Note that rev does not map directly to our defined processor
- + 	 * revision numbers as ES1.0 uses value 0.
- + 	 */
- + 	idcode = read_tap_reg(OMAP_TAP_IDCODE);
- + 	hawkeye = (idcode >> 12) & 0xffff;
- + 	rev = (idcode >> 28) & 0xff;
- + 
- + 	switch (hawkeye) {
- + 	case 0xb7ae:
- + 		/* Handle 34xx/35xx devices */
- + 		switch (rev) {
- + 		case 0: /* Take care of early samples */
- + 		case 1:
- + 			omap_revision = OMAP3430_REV_ES2_0;
- + 			cpu_rev = "2.0";
- + 			break;
- + 		case 2:
- + 			omap_revision = OMAP3430_REV_ES2_1;
- + 			cpu_rev = "2.1";
- + 			break;
- + 		case 3:
- + 			omap_revision = OMAP3430_REV_ES3_0;
- + 			cpu_rev = "3.0";
- + 			break;
- + 		case 4:
- + 			omap_revision = OMAP3430_REV_ES3_1;
- + 			cpu_rev = "3.1";
- + 			break;
- + 		case 7:
- + 		/* FALLTHROUGH */
- + 		default:
- + 			/* Use the latest known revision as default */
- + 			omap_revision = OMAP3430_REV_ES3_1_2;
- + 			cpu_rev = "3.1.2";
- + 		}
- + 		break;
- + 	case 0xb868:
- + 		/*
- + 		 * Handle OMAP/AM 3505/3517 devices
- + 		 *
- + 		 * Set the device to be OMAP3517 here. Actual device
- + 		 * is identified later based on the features.
- + 		 */
- + 		switch (rev) {
- + 		case 0:
- + 			omap_revision = OMAP3517_REV_ES1_0;
- + 			cpu_rev = "1.0";
- + 			break;
- + 		case 1:
- + 		/* FALLTHROUGH */
- + 		default:
- + 			omap_revision = OMAP3517_REV_ES1_1;
- + 			cpu_rev = "1.1";
- + 		}
- + 		break;
- + 	case 0xb891:
- + 		/* Handle 36xx devices */
- + 
- + 		switch(rev) {
- + 		case 0: /* Take care of early samples */
- + 			omap_revision = OMAP3630_REV_ES1_0;
- + 			cpu_rev = "1.0";
- + 			break;
- + 		case 1:
- + 			omap_revision = OMAP3630_REV_ES1_1;
- + 			cpu_rev = "1.1";
- + 			break;
- + 		case 2:
- + 		/* FALLTHROUGH */
- + 		default:
- + 			omap_revision = OMAP3630_REV_ES1_2;
- + 			cpu_rev = "1.2";
- + 		}
- + 		break;
- + 	case 0xb81e:
- + 		switch (rev) {
- + 		case 0:
- + 			omap_revision = TI8168_REV_ES1_0;
- + 			cpu_rev = "1.0";
- + 			break;
- + 		case 1:
- + 		/* FALLTHROUGH */
- + 		default:
- + 			omap_revision = TI8168_REV_ES1_1;
- + 			cpu_rev = "1.1";
- + 			break;
- + 		}
- + 		break;
- + 	case 0xb944:
- + 		switch (rev) {
- + 		case 0:
- + 			omap_revision = AM335X_REV_ES1_0;
- + 			cpu_rev = "1.0";
- + 			break;
- + 		case 1:
- + 		/* FALLTHROUGH */
- + 		default:
- + 			omap_revision = AM335X_REV_ES2_0;
- + 			cpu_rev = "2.0";
- + 			break;
- + 		}
- + 		break;
- + 	case 0xb8f2:
- + 		switch (rev) {
- + 		case 0:
- + 		/* FALLTHROUGH */
- + 		case 1:
- + 			omap_revision = TI8148_REV_ES1_0;
- + 			cpu_rev = "1.0";
- + 			break;
- + 		case 2:
- + 			omap_revision = TI8148_REV_ES2_0;
- + 			cpu_rev = "2.0";
- + 			break;
- + 		case 3:
- + 		/* FALLTHROUGH */
- + 		default:
- + 			omap_revision = TI8148_REV_ES2_1;
- + 			cpu_rev = "2.1";
- + 			break;
- + 		}
- + 		break;
- + 	default:
- + 		/* Unknown default to latest silicon rev as default */
- + 		omap_revision = OMAP3630_REV_ES1_2;
- + 		cpu_rev = "1.2";
- + 		pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
- + 	}
- + }
- + 
- + /*
- +  * Set up things for map_io and processor detection later on. Gets called
- +  * pretty much first thing from board init. For multi-omap, this gets
- +  * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
- +  * detect the exact revision later on in omap2_detect_revision() once map_io
- +  * is done.
- +  */
- + void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
- + {
- + 	omap_revision = omap2_globals->class;
- + 	tap_base = omap2_globals->tap;
- + 	tap_prod_id = 0x0208;
- + }
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/common.h linux-3.2.1/arch/arm/mach-ckb_3352/common.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/common.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/common.h	2014-05-15 13:25:13.895246182 +0900
- ***************
- *** 0 ****
- --- 1,186 ----
- + /*
- +  * Header for code common to all OMAP2+ machines.
- +  *
- +  * This program is free software; you can redistribute it and/or modify it
- +  * under the terms of the GNU General Public License as published by the
- +  * Free Software Foundation; either version 2 of the License, or (at your
- +  * option) any later version.
- +  *
- +  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- +  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- +  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- +  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- +  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- +  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- +  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- +  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- +  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- +  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- +  *
- +  * You should have received a copy of the  GNU General Public License along
- +  * with this program; if not, write  to the Free Software Foundation, Inc.,
- +  * 675 Mass Ave, Cambridge, MA 02139, USA.
- +  */
- + 
- + #ifndef __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
- + #define __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
- + #ifndef __ASSEMBLER__
- + 
- + #include <linux/delay.h>
- + #include <plat/common.h>
- + #include <asm/proc-fns.h>
- + 
- + #ifdef CONFIG_SOC_OMAPAM33XX
- + extern void omapam33xx_map_common_io(void);
- + #else
- + static inline void omapam33xx_map_common_io(void)
- + {
- + }
- + #endif
- + 
- + 
- + extern void omap2_init_common_infrastructure(void);
- + 
- + extern struct sys_timer omap2_timer;
- + extern struct sys_timer omap3_timer;
- + extern struct sys_timer omap3_secure_timer;
- + extern struct sys_timer omap3_am33xx_timer;
- + extern struct sys_timer omap4_timer;
- + 
- + void omap2420_init_early(void);
- + void omap2430_init_early(void);
- + void omap3430_init_early(void);
- + void omap35xx_init_early(void);
- + void omap3630_init_early(void);
- + void omap3_init_early(void);	/* Do not use this one */
- + void am35xx_init_early(void);
- + void am33xx_init_early(void);
- + void omap4430_init_early(void);
- + 
- + /*
- +  * IO bases for various OMAP processors
- +  * Except the tap base, rest all the io bases
- +  * listed are physical addresses.
- +  */
- + struct omap_globals {
- + 	u32		class;		/* OMAP class to detect */
- + 	void __iomem	*tap;		/* Control module ID code */
- + 	void __iomem	*sdrc;           /* SDRAM Controller */
- + 	void __iomem	*sms;            /* SDRAM Memory Scheduler */
- + 	void __iomem	*ctrl;           /* System Control Module */
- + 	void __iomem	*ctrl_pad;	/* PAD Control Module */
- + 	void __iomem	*prm;            /* Power and Reset Management */
- + 	void __iomem	*cm;             /* Clock Management */
- + 	void __iomem	*cm2;
- + };
- + 
- + void omap2_set_globals_am33xx(void);
- + 
- + /* These get called from omap2_set_globals_xxxx(), do not call these */
- + void omap2_set_globals_tap(struct omap_globals *);
- + void omap2_set_globals_sdrc(struct omap_globals *);
- + void omap2_set_globals_control(struct omap_globals *);
- + void omap2_set_globals_prcm(struct omap_globals *);
- + 
- + void am33xx_map_io(void);
- + void omap4_map_io(void);
- + void ti81xx_map_io(void);
- + 
- + /**
- +  * omap_test_timeout - busy-loop, testing a condition
- +  * @cond: condition to test until it evaluates to true
- +  * @timeout: maximum number of microseconds in the timeout
- +  * @index: loop index (integer)
- +  *
- +  * Loop waiting for @cond to become true or until at least @timeout
- +  * microseconds have passed.  To use, define some integer @index in the
- +  * calling code.  After running, if @index == @timeout, then the loop has
- +  * timed out.
- +  */
- + #define omap_test_timeout(cond, timeout, index)			\
- + ({								\
- + 	for (index = 0; index < timeout; index++) {		\
- + 		if (cond)					\
- + 			break;					\
- + 		udelay(1);					\
- + 	}							\
- + })
- + 
- + extern struct device *omap2_get_mpuss_device(void);
- + extern struct device *omap2_get_iva_device(void);
- + extern struct device *omap2_get_l3_device(void);
- + extern struct device *omap4_get_dsp_device(void);
- + 
- + void omap3_init_irq(void);
- + void ti81xx_init_irq(void);
- + extern int omap_irq_pending(void);
- + void omap3_intc_suspend(void);
- + void omap3_intc_handle_irq(struct pt_regs *regs);
- + 
- + #ifdef CONFIG_CACHE_L2X0
- + extern void __iomem *omap4_get_l2cache_base(void);
- + #endif
- + 
- + #ifdef CONFIG_SMP
- + extern void __iomem *omap4_get_scu_base(void);
- + #else
- + static inline void __iomem *omap4_get_scu_base(void)
- + {
- + 	return NULL;
- + }
- + #endif
- + 
- + extern void __init gic_init_irq(void);
- + extern void omap_smc1(u32 fn, u32 arg);
- + extern void __iomem *omap4_get_sar_ram_base(void);
- + extern void omap_do_wfi(void);
- + 
- + #ifdef CONFIG_SMP
- + /* Needed for secondary core boot */
- + extern void omap_secondary_startup(void);
- + extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
- + extern void omap_auxcoreboot_addr(u32 cpu_addr);
- + extern u32 omap_read_auxcoreboot0(void);
- + #endif
- + 
- + #if defined(CONFIG_SMP) && defined(CONFIG_PM)
- + extern int omap4_mpuss_init(void);
- + extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state);
- + extern int omap4_finish_suspend(unsigned long cpu_state);
- + extern void omap4_cpu_resume(void);
- + extern int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state);
- + extern u32 omap4_mpuss_read_prev_context_state(void);
- + #else
- + static inline int omap4_enter_lowpower(unsigned int cpu,
- + 					unsigned int power_state)
- + {
- + 	cpu_do_idle();
- + 	return 0;
- + }
- + 
- + static inline int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
- + {
- + 	cpu_do_idle();
- + 	return 0;
- + }
- + 
- + static inline int omap4_mpuss_init(void)
- + {
- + 	return 0;
- + }
- + 
- + static inline int omap4_finish_suspend(unsigned long cpu_state)
- + {
- + 	return 0;
- + }
- + 
- + static inline void omap4_cpu_resume(void)
- + {}
- + 
- + static inline u32 omap4_mpuss_read_prev_context_state(void)
- + {
- + 	return 0;
- + }
- + #endif
- + #endif /* __ASSEMBLER__ */
- + #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/control.c linux-3.2.1/arch/arm/mach-ckb_3352/control.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/control.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/control.c	2014-05-15 13:25:13.895246182 +0900
- ***************
- *** 0 ****
- --- 1,212 ----
- + /*
- +  * OMAP2/3 System Control Module register access
- +  *
- +  * Copyright (C) 2007 Texas Instruments, Inc.
- +  * Copyright (C) 2007 Nokia Corporation
- +  *
- +  * Written by Paul Walmsley
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + #undef DEBUG
- + 
- + #include <linux/kernel.h>
- + #include <linux/module.h>
- + #include <linux/io.h>
- + 
- + #include "common.h"
- + #include <plat/sdrc.h>
- + 
- + #include "cm-regbits-34xx.h"
- + #include "prm-regbits-34xx.h"
- + #include "prm2xxx_3xxx.h"
- + #include "cm2xxx_3xxx.h"
- + #include "sdrc.h"
- + #include "pm.h"
- + #include "control.h"
- + 
- + /* Used by omap3_ctrl_save_padconf() */
- + #define START_PADCONF_SAVE		0x2
- + #define PADCONF_SAVE_DONE		0x1
- + 
- + static void __iomem *omap2_ctrl_base;
- + static void __iomem *omap4_ctrl_pad_base;
- + 
- + #if defined(CONFIG_PM)
- + struct omap3_scratchpad {
- + 	u32 boot_config_ptr;
- + 	u32 public_restore_ptr;
- + 	u32 secure_ram_restore_ptr;
- + 	u32 sdrc_module_semaphore;
- + 	u32 prcm_block_offset;
- + 	u32 sdrc_block_offset;
- + };
- + 
- + struct omap3_scratchpad_prcm_block {
- + 	u32 prm_clksrc_ctrl;
- + 	u32 prm_clksel;
- + 	u32 cm_clksel_core;
- + 	u32 cm_clksel_wkup;
- + 	u32 cm_clken_pll;
- + 	u32 cm_autoidle_pll;
- + 	u32 cm_clksel1_pll;
- + 	u32 cm_clksel2_pll;
- + 	u32 cm_clksel3_pll;
- + 	u32 cm_clken_pll_mpu;
- + 	u32 cm_autoidle_pll_mpu;
- + 	u32 cm_clksel1_pll_mpu;
- + 	u32 cm_clksel2_pll_mpu;
- + 	u32 prcm_block_size;
- + };
- + 
- + struct omap3_scratchpad_sdrc_block {
- + 	u16 sysconfig;
- + 	u16 cs_cfg;
- + 	u16 sharing;
- + 	u16 err_type;
- + 	u32 dll_a_ctrl;
- + 	u32 dll_b_ctrl;
- + 	u32 power;
- + 	u32 cs_0;
- + 	u32 mcfg_0;
- + 	u16 mr_0;
- + 	u16 emr_1_0;
- + 	u16 emr_2_0;
- + 	u16 emr_3_0;
- + 	u32 actim_ctrla_0;
- + 	u32 actim_ctrlb_0;
- + 	u32 rfr_ctrl_0;
- + 	u32 cs_1;
- + 	u32 mcfg_1;
- + 	u16 mr_1;
- + 	u16 emr_1_1;
- + 	u16 emr_2_1;
- + 	u16 emr_3_1;
- + 	u32 actim_ctrla_1;
- + 	u32 actim_ctrlb_1;
- + 	u32 rfr_ctrl_1;
- + 	u16 dcdl_1_ctrl;
- + 	u16 dcdl_2_ctrl;
- + 	u32 flags;
- + 	u32 block_size;
- + };
- + 
- + void *omap3_secure_ram_storage;
- + 
- + /*
- +  * This is used to store ARM registers in SDRAM before attempting
- +  * an MPU OFF. The save and restore happens from the SRAM sleep code.
- +  * The address is stored in scratchpad, so that it can be used
- +  * during the restore path.
- +  */
- + u32 omap3_arm_context[128];
- + 
- + struct omap3_control_regs {
- + 	u32 sysconfig;
- + 	u32 devconf0;
- + 	u32 mem_dftrw0;
- + 	u32 mem_dftrw1;
- + 	u32 msuspendmux_0;
- + 	u32 msuspendmux_1;
- + 	u32 msuspendmux_2;
- + 	u32 msuspendmux_3;
- + 	u32 msuspendmux_4;
- + 	u32 msuspendmux_5;
- + 	u32 sec_ctrl;
- + 	u32 devconf1;
- + 	u32 csirxfe;
- + 	u32 iva2_bootaddr;
- + 	u32 iva2_bootmod;
- + 	u32 debobs_0;
- + 	u32 debobs_1;
- + 	u32 debobs_2;
- + 	u32 debobs_3;
- + 	u32 debobs_4;
- + 	u32 debobs_5;
- + 	u32 debobs_6;
- + 	u32 debobs_7;
- + 	u32 debobs_8;
- + 	u32 prog_io0;
- + 	u32 prog_io1;
- + 	u32 dss_dpll_spreading;
- + 	u32 core_dpll_spreading;
- + 	u32 per_dpll_spreading;
- + 	u32 usbhost_dpll_spreading;
- + 	u32 pbias_lite;
- + 	u32 temp_sensor;
- + 	u32 sramldo4;
- + 	u32 sramldo5;
- + 	u32 csi;
- + 	u32 padconf_sys_nirq;
- + };
- + 
- + static struct omap3_control_regs control_context;
- + #endif /* CONFIG_PM */
- + 
- + #define OMAP_CTRL_REGADDR(reg)		(omap2_ctrl_base + (reg))
- + #define OMAP4_CTRL_PAD_REGADDR(reg)	(omap4_ctrl_pad_base + (reg))
- + 
- + void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
- + {
- + 	if (omap2_globals->ctrl)
- + 		omap2_ctrl_base = omap2_globals->ctrl;
- + 
- + 	if (omap2_globals->ctrl_pad)
- + 		omap4_ctrl_pad_base = omap2_globals->ctrl_pad;
- + }
- + 
- + void __iomem *omap_ctrl_base_get(void)
- + {
- + 	return omap2_ctrl_base;
- + }
- + 
- + u8 omap_ctrl_readb(u16 offset)
- + {
- + 	return __raw_readb(OMAP_CTRL_REGADDR(offset));
- + }
- + 
- + u16 omap_ctrl_readw(u16 offset)
- + {
- + 	return __raw_readw(OMAP_CTRL_REGADDR(offset));
- + }
- + 
- + u32 omap_ctrl_readl(u16 offset)
- + {
- + 	return __raw_readl(OMAP_CTRL_REGADDR(offset));
- + }
- + 
- + void omap_ctrl_writeb(u8 val, u16 offset)
- + {
- + 	__raw_writeb(val, OMAP_CTRL_REGADDR(offset));
- + }
- + 
- + void omap_ctrl_writew(u16 val, u16 offset)
- + {
- + 	__raw_writew(val, OMAP_CTRL_REGADDR(offset));
- + }
- + 
- + void omap_ctrl_writel(u32 val, u16 offset)
- + {
- + 	__raw_writel(val, OMAP_CTRL_REGADDR(offset));
- + }
- + EXPORT_SYMBOL_GPL(omap_ctrl_writel);
- + 
- + /*
- +  * On OMAP4 control pad are not addressable from control
- +  * core base. So the common omap_ctrl_read/write APIs breaks
- +  * Hence export separate APIs to manage the omap4 pad control
- +  * registers. This APIs will work only for OMAP4
- +  */
- + 
- + u32 omap4_ctrl_pad_readl(u16 offset)
- + {
- + 	return __raw_readl(OMAP4_CTRL_PAD_REGADDR(offset));
- + }
- + 
- + void omap4_ctrl_pad_writel(u32 val, u16 offset)
- + {
- + 	__raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset));
- + }
- + 
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/control.h linux-3.2.1/arch/arm/mach-ckb_3352/control.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/control.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/control.h	2014-05-15 13:25:13.895246182 +0900
- ***************
- *** 0 ****
- --- 1,432 ----
- + /*
- +  * arch/arm/mach-ckb_3352/control.h
- +  *
- +  * CKB 3352 System Control Module definitions
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation.
- +  */
- + 
- + #ifndef __ARCH_ARM_MACH_CKB_3352_CONTROL_H
- + #define __ARCH_ARM_MACH_CKB_3352_CONTROL_H
- + 
- + #include <mach/io.h>
- + 
- + #ifndef __ASSEMBLY__
- + #define OMAP343X_CTRL_REGADDR(reg)					\
- + 		OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
- + #define AM33XX_CTRL_REGADDR(reg)					\
- + 		AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
- + #else
- + #define OMAP343X_CTRL_REGADDR(reg)					\
- + 		OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
- + #define AM33XX_CTRL_REGADDR(reg)					\
- + 		AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
- + #endif /* __ASSEMBLY__ */
- + 
- + /*
- +  * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for
- +  * OMAP24XX and OMAP34XX.
- +  */
- + 
- + /* Control submodule offsets */
- + 
- + #define OMAP2_CONTROL_INTERFACE		0x000
- + #define OMAP2_CONTROL_PADCONFS		0x030
- + #define OMAP2_CONTROL_GENERAL		0x270
- + #define OMAP343X_CONTROL_MEM_WKUP	0x600
- + #define OMAP343X_CONTROL_PADCONFS_WKUP	0xa00
- + #define OMAP343X_CONTROL_GENERAL_WKUP	0xa60
- + 
- + /* TI81XX spefic control submodules */
- + #define TI81XX_CONTROL_DEVCONF		0x600
- + 
- + /* TI81XX CONTROL_DEVCONF register offsets */
- + #define TI81XX_CONTROL_MAC_ID0_LO       (TI81XX_CONTROL_DEVCONF + 0x030)
- + #define TI81XX_CONTROL_MAC_ID0_HI       (TI81XX_CONTROL_DEVCONF + 0x034)
- + #define TI81XX_CONTROL_MAC_ID1_LO       (TI81XX_CONTROL_DEVCONF + 0x038)
- + #define TI81XX_CONTROL_MAC_ID1_HI       (TI81XX_CONTROL_DEVCONF + 0x03c)
- + 
- + /* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
- + 
- + #define OMAP2_CONTROL_SYSCONFIG		(OMAP2_CONTROL_INTERFACE + 0x10)
- + 
- + /* CONTROL_GENERAL register offsets common to OMAP2 & 3 */
- + #define OMAP2_CONTROL_DEVCONF0		(OMAP2_CONTROL_GENERAL + 0x0004)
- + #define OMAP2_CONTROL_MSUSPENDMUX_0	(OMAP2_CONTROL_GENERAL + 0x0020)
- + #define OMAP2_CONTROL_MSUSPENDMUX_1	(OMAP2_CONTROL_GENERAL + 0x0024)
- + #define OMAP2_CONTROL_MSUSPENDMUX_2	(OMAP2_CONTROL_GENERAL + 0x0028)
- + #define OMAP2_CONTROL_MSUSPENDMUX_3	(OMAP2_CONTROL_GENERAL + 0x002c)
- + #define OMAP2_CONTROL_MSUSPENDMUX_4	(OMAP2_CONTROL_GENERAL + 0x0030)
- + #define OMAP2_CONTROL_MSUSPENDMUX_5	(OMAP2_CONTROL_GENERAL + 0x0034)
- + #define OMAP2_CONTROL_SEC_CTRL		(OMAP2_CONTROL_GENERAL + 0x0040)
- + #define OMAP2_CONTROL_RPUB_KEY_H_0	(OMAP2_CONTROL_GENERAL + 0x0090)
- + #define OMAP2_CONTROL_RPUB_KEY_H_1	(OMAP2_CONTROL_GENERAL + 0x0094)
- + #define OMAP2_CONTROL_RPUB_KEY_H_2	(OMAP2_CONTROL_GENERAL + 0x0098)
- + #define OMAP2_CONTROL_RPUB_KEY_H_3	(OMAP2_CONTROL_GENERAL + 0x009c)
- + 
- + /* 242x-only CONTROL_GENERAL register offsets */
- + #define OMAP242X_CONTROL_DEVCONF	OMAP2_CONTROL_DEVCONF0 /* match TRM */
- + #define OMAP242X_CONTROL_OCM_RAM_PERM	(OMAP2_CONTROL_GENERAL + 0x0068)
- + 
- + /* 243x-only CONTROL_GENERAL register offsets */
- + /* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */
- + #define OMAP243X_CONTROL_DEVCONF1	(OMAP2_CONTROL_GENERAL + 0x0078)
- + #define OMAP243X_CONTROL_CSIRXFE	(OMAP2_CONTROL_GENERAL + 0x007c)
- + #define OMAP243X_CONTROL_IVA2_BOOTADDR	(OMAP2_CONTROL_GENERAL + 0x0190)
- + #define OMAP243X_CONTROL_IVA2_BOOTMOD	(OMAP2_CONTROL_GENERAL + 0x0194)
- + #define OMAP243X_CONTROL_IVA2_GEMCFG	(OMAP2_CONTROL_GENERAL + 0x0198)
- + #define OMAP243X_CONTROL_PBIAS_LITE	(OMAP2_CONTROL_GENERAL + 0x0230)
- + 
- + /* 24xx-only CONTROL_GENERAL register offsets */
- + #define OMAP24XX_CONTROL_DEBOBS		(OMAP2_CONTROL_GENERAL + 0x0000)
- + #define OMAP24XX_CONTROL_EMU_SUPPORT	(OMAP2_CONTROL_GENERAL + 0x0008)
- + #define OMAP24XX_CONTROL_SEC_TEST	(OMAP2_CONTROL_GENERAL + 0x0044)
- + #define OMAP24XX_CONTROL_PSA_CTRL	(OMAP2_CONTROL_GENERAL + 0x0048)
- + #define OMAP24XX_CONTROL_PSA_CMD	(OMAP2_CONTROL_GENERAL + 0x004c)
- + #define OMAP24XX_CONTROL_PSA_VALUE	(OMAP2_CONTROL_GENERAL + 0x0050)
- + #define OMAP24XX_CONTROL_SEC_EMU	(OMAP2_CONTROL_GENERAL + 0x0060)
- + #define OMAP24XX_CONTROL_SEC_TAP	(OMAP2_CONTROL_GENERAL + 0x0064)
- + #define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD	(OMAP2_CONTROL_GENERAL + 0x006c)
- + #define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD	(OMAP2_CONTROL_GENERAL + 0x0070)
- + #define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD	(OMAP2_CONTROL_GENERAL + 0x0074)
- + #define OMAP24XX_CONTROL_SEC_STATUS		(OMAP2_CONTROL_GENERAL + 0x0080)
- + #define OMAP24XX_CONTROL_SEC_ERR_STATUS		(OMAP2_CONTROL_GENERAL + 0x0084)
- + #define OMAP24XX_CONTROL_STATUS			(OMAP2_CONTROL_GENERAL + 0x0088)
- + #define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS	(OMAP2_CONTROL_GENERAL + 0x008c)
- + #define OMAP24XX_CONTROL_RAND_KEY_0	(OMAP2_CONTROL_GENERAL + 0x00a0)
- + #define OMAP24XX_CONTROL_RAND_KEY_1	(OMAP2_CONTROL_GENERAL + 0x00a4)
- + #define OMAP24XX_CONTROL_RAND_KEY_2	(OMAP2_CONTROL_GENERAL + 0x00a8)
- + #define OMAP24XX_CONTROL_RAND_KEY_3	(OMAP2_CONTROL_GENERAL + 0x00ac)
- + #define OMAP24XX_CONTROL_CUST_KEY_0	(OMAP2_CONTROL_GENERAL + 0x00b0)
- + #define OMAP24XX_CONTROL_CUST_KEY_1	(OMAP2_CONTROL_GENERAL + 0x00b4)
- + #define OMAP24XX_CONTROL_TEST_KEY_0	(OMAP2_CONTROL_GENERAL + 0x00c0)
- + #define OMAP24XX_CONTROL_TEST_KEY_1	(OMAP2_CONTROL_GENERAL + 0x00c4)
- + #define OMAP24XX_CONTROL_TEST_KEY_2	(OMAP2_CONTROL_GENERAL + 0x00c8)
- + #define OMAP24XX_CONTROL_TEST_KEY_3	(OMAP2_CONTROL_GENERAL + 0x00cc)
- + #define OMAP24XX_CONTROL_TEST_KEY_4	(OMAP2_CONTROL_GENERAL + 0x00d0)
- + #define OMAP24XX_CONTROL_TEST_KEY_5	(OMAP2_CONTROL_GENERAL + 0x00d4)
- + #define OMAP24XX_CONTROL_TEST_KEY_6	(OMAP2_CONTROL_GENERAL + 0x00d8)
- + #define OMAP24XX_CONTROL_TEST_KEY_7	(OMAP2_CONTROL_GENERAL + 0x00dc)
- + #define OMAP24XX_CONTROL_TEST_KEY_8	(OMAP2_CONTROL_GENERAL + 0x00e0)
- + #define OMAP24XX_CONTROL_TEST_KEY_9	(OMAP2_CONTROL_GENERAL + 0x00e4)
- + 
- + #define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0)
- + 
- + /* 34xx-only CONTROL_GENERAL register offsets */
- + #define OMAP343X_CONTROL_PADCONF_OFF	(OMAP2_CONTROL_GENERAL + 0x0000)
- + #define OMAP343X_CONTROL_MEM_DFTRW0	(OMAP2_CONTROL_GENERAL + 0x0008)
- + #define OMAP343X_CONTROL_MEM_DFTRW1	(OMAP2_CONTROL_GENERAL + 0x000c)
- + #define OMAP343X_CONTROL_DEVCONF1	(OMAP2_CONTROL_GENERAL + 0x0068)
- + #define OMAP343X_CONTROL_CSIRXFE		(OMAP2_CONTROL_GENERAL + 0x006c)
- + #define OMAP343X_CONTROL_SEC_STATUS		(OMAP2_CONTROL_GENERAL + 0x0070)
- + #define OMAP343X_CONTROL_SEC_ERR_STATUS		(OMAP2_CONTROL_GENERAL + 0x0074)
- + #define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG	(OMAP2_CONTROL_GENERAL + 0x0078)
- + #define OMAP343X_CONTROL_STATUS			(OMAP2_CONTROL_GENERAL + 0x0080)
- + #define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS	(OMAP2_CONTROL_GENERAL + 0x0084)
- + #define OMAP343X_CONTROL_RPUB_KEY_H_4	(OMAP2_CONTROL_GENERAL + 0x00a0)
- + #define OMAP343X_CONTROL_RAND_KEY_0	(OMAP2_CONTROL_GENERAL + 0x00a8)
- + #define OMAP343X_CONTROL_RAND_KEY_1	(OMAP2_CONTROL_GENERAL + 0x00ac)
- + #define OMAP343X_CONTROL_RAND_KEY_2	(OMAP2_CONTROL_GENERAL + 0x00b0)
- + #define OMAP343X_CONTROL_RAND_KEY_3	(OMAP2_CONTROL_GENERAL + 0x00b4)
- + #define OMAP343X_CONTROL_TEST_KEY_0	(OMAP2_CONTROL_GENERAL + 0x00c8)
- + #define OMAP343X_CONTROL_TEST_KEY_1	(OMAP2_CONTROL_GENERAL + 0x00cc)
- + #define OMAP343X_CONTROL_TEST_KEY_2	(OMAP2_CONTROL_GENERAL + 0x00d0)
- + #define OMAP343X_CONTROL_TEST_KEY_3	(OMAP2_CONTROL_GENERAL + 0x00d4)
- + #define OMAP343X_CONTROL_TEST_KEY_4	(OMAP2_CONTROL_GENERAL + 0x00d8)
- + #define OMAP343X_CONTROL_TEST_KEY_5	(OMAP2_CONTROL_GENERAL + 0x00dc)
- + #define OMAP343X_CONTROL_TEST_KEY_6	(OMAP2_CONTROL_GENERAL + 0x00e0)
- + #define OMAP343X_CONTROL_TEST_KEY_7	(OMAP2_CONTROL_GENERAL + 0x00e4)
- + #define OMAP343X_CONTROL_TEST_KEY_8	(OMAP2_CONTROL_GENERAL + 0x00e8)
- + #define OMAP343X_CONTROL_TEST_KEY_9	(OMAP2_CONTROL_GENERAL + 0x00ec)
- + #define OMAP343X_CONTROL_TEST_KEY_10	(OMAP2_CONTROL_GENERAL + 0x00f0)
- + #define OMAP343X_CONTROL_TEST_KEY_11	(OMAP2_CONTROL_GENERAL + 0x00f4)
- + #define OMAP343X_CONTROL_TEST_KEY_12	(OMAP2_CONTROL_GENERAL + 0x00f8)
- + #define OMAP343X_CONTROL_TEST_KEY_13	(OMAP2_CONTROL_GENERAL + 0x00fc)
- + #define OMAP343X_CONTROL_FUSE_OPP1_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110)
- + #define OMAP343X_CONTROL_FUSE_OPP2_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114)
- + #define OMAP343X_CONTROL_FUSE_OPP3_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118)
- + #define OMAP343X_CONTROL_FUSE_OPP4_VDD1 (OMAP2_CONTROL_GENERAL + 0x011c)
- + #define OMAP343X_CONTROL_FUSE_OPP5_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120)
- + #define OMAP343X_CONTROL_FUSE_OPP1_VDD2 (OMAP2_CONTROL_GENERAL + 0x0124)
- + #define OMAP343X_CONTROL_FUSE_OPP2_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128)
- + #define OMAP343X_CONTROL_FUSE_OPP3_VDD2 (OMAP2_CONTROL_GENERAL + 0x012c)
- + #define OMAP343X_CONTROL_FUSE_SR        (OMAP2_CONTROL_GENERAL + 0x0130)
- + #define OMAP343X_CONTROL_IVA2_BOOTADDR	(OMAP2_CONTROL_GENERAL + 0x0190)
- + #define OMAP343X_CONTROL_IVA2_BOOTMOD	(OMAP2_CONTROL_GENERAL + 0x0194)
- + #define OMAP343X_CONTROL_DEBOBS(i)	(OMAP2_CONTROL_GENERAL + 0x01B0 \
- + 					+ ((i) >> 1) * 4 + (!((i) & 1)) * 2)
- + #define OMAP343X_CONTROL_PROG_IO0	(OMAP2_CONTROL_GENERAL + 0x01D4)
- + #define OMAP343X_CONTROL_PROG_IO1	(OMAP2_CONTROL_GENERAL + 0x01D8)
- + #define OMAP343X_CONTROL_DSS_DPLL_SPREADING	(OMAP2_CONTROL_GENERAL + 0x01E0)
- + #define OMAP343X_CONTROL_CORE_DPLL_SPREADING	(OMAP2_CONTROL_GENERAL + 0x01E4)
- + #define OMAP343X_CONTROL_PER_DPLL_SPREADING	(OMAP2_CONTROL_GENERAL + 0x01E8)
- + #define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING	(OMAP2_CONTROL_GENERAL + 0x01EC)
- + #define OMAP343X_CONTROL_PBIAS_LITE	(OMAP2_CONTROL_GENERAL + 0x02B0)
- + #define OMAP343X_CONTROL_TEMP_SENSOR	(OMAP2_CONTROL_GENERAL + 0x02B4)
- + #define OMAP343X_CONTROL_SRAMLDO4	(OMAP2_CONTROL_GENERAL + 0x02B8)
- + #define OMAP343X_CONTROL_SRAMLDO5	(OMAP2_CONTROL_GENERAL + 0x02C0)
- + #define OMAP343X_CONTROL_CSI		(OMAP2_CONTROL_GENERAL + 0x02C4)
- + 
- + /* OMAP3630 only CONTROL_GENERAL register offsets */
- + #define OMAP3630_CONTROL_FUSE_OPP1G_VDD1        (OMAP2_CONTROL_GENERAL + 0x0110)
- + #define OMAP3630_CONTROL_FUSE_OPP50_VDD1        (OMAP2_CONTROL_GENERAL + 0x0114)
- + #define OMAP3630_CONTROL_FUSE_OPP100_VDD1       (OMAP2_CONTROL_GENERAL + 0x0118)
- + #define OMAP3630_CONTROL_FUSE_OPP120_VDD1       (OMAP2_CONTROL_GENERAL + 0x0120)
- + #define OMAP3630_CONTROL_FUSE_OPP50_VDD2        (OMAP2_CONTROL_GENERAL + 0x0128)
- + #define OMAP3630_CONTROL_FUSE_OPP100_VDD2       (OMAP2_CONTROL_GENERAL + 0x012C)
- + 
- + /* OMAP44xx control efuse offsets */
- + #define OMAP44XX_CONTROL_FUSE_IVA_OPP50		0x22C
- + #define OMAP44XX_CONTROL_FUSE_IVA_OPP100	0x22F
- + #define OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO	0x232
- + #define OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO	0x235
- + #define OMAP44XX_CONTROL_FUSE_MPU_OPP50		0x240
- + #define OMAP44XX_CONTROL_FUSE_MPU_OPP100	0x243
- + #define OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO	0x246
- + #define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO	0x249
- + #define OMAP44XX_CONTROL_FUSE_CORE_OPP50	0x254
- + #define OMAP44XX_CONTROL_FUSE_CORE_OPP100	0x257
- + 
- + /* AM35XX only CONTROL_GENERAL register offsets */
- + #define AM35XX_CONTROL_MSUSPENDMUX_6    (OMAP2_CONTROL_GENERAL + 0x0038)
- + #define AM35XX_CONTROL_DEVCONF2         (OMAP2_CONTROL_GENERAL + 0x0310)
- + #define AM35XX_CONTROL_DEVCONF3         (OMAP2_CONTROL_GENERAL + 0x0314)
- + #define AM35XX_CONTROL_CBA_PRIORITY     (OMAP2_CONTROL_GENERAL + 0x0320)
- + #define AM35XX_CONTROL_LVL_INTR_CLEAR   (OMAP2_CONTROL_GENERAL + 0x0324)
- + #define AM35XX_CONTROL_IP_SW_RESET      (OMAP2_CONTROL_GENERAL + 0x0328)
- + #define AM35XX_CONTROL_IPSS_CLK_CTRL    (OMAP2_CONTROL_GENERAL + 0x032C)
- + 
- + /* 34xx PADCONF register offsets */
- + #define OMAP343X_PADCONF_ETK(i)		(OMAP2_CONTROL_PADCONFS + 0x5a8 + \
- + 						(i)*2)
- + #define OMAP343X_PADCONF_ETK_CLK	OMAP343X_PADCONF_ETK(0)
- + #define OMAP343X_PADCONF_ETK_CTL	OMAP343X_PADCONF_ETK(1)
- + #define OMAP343X_PADCONF_ETK_D0		OMAP343X_PADCONF_ETK(2)
- + #define OMAP343X_PADCONF_ETK_D1		OMAP343X_PADCONF_ETK(3)
- + #define OMAP343X_PADCONF_ETK_D2		OMAP343X_PADCONF_ETK(4)
- + #define OMAP343X_PADCONF_ETK_D3		OMAP343X_PADCONF_ETK(5)
- + #define OMAP343X_PADCONF_ETK_D4		OMAP343X_PADCONF_ETK(6)
- + #define OMAP343X_PADCONF_ETK_D5		OMAP343X_PADCONF_ETK(7)
- + #define OMAP343X_PADCONF_ETK_D6		OMAP343X_PADCONF_ETK(8)
- + #define OMAP343X_PADCONF_ETK_D7		OMAP343X_PADCONF_ETK(9)
- + #define OMAP343X_PADCONF_ETK_D8		OMAP343X_PADCONF_ETK(10)
- + #define OMAP343X_PADCONF_ETK_D9		OMAP343X_PADCONF_ETK(11)
- + #define OMAP343X_PADCONF_ETK_D10	OMAP343X_PADCONF_ETK(12)
- + #define OMAP343X_PADCONF_ETK_D11	OMAP343X_PADCONF_ETK(13)
- + #define OMAP343X_PADCONF_ETK_D12	OMAP343X_PADCONF_ETK(14)
- + #define OMAP343X_PADCONF_ETK_D13	OMAP343X_PADCONF_ETK(15)
- + #define OMAP343X_PADCONF_ETK_D14	OMAP343X_PADCONF_ETK(16)
- + #define OMAP343X_PADCONF_ETK_D15	OMAP343X_PADCONF_ETK(17)
- + 
- + /* 34xx GENERAL_WKUP regist offsets */
- + #define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \
- + 						0x008 + (i))
- + #define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008)
- + #define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C)
- + #define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010)
- + #define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
- + #define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
- + 
- + /* 36xx-only RTA - Retention till Access control registers and bits */
- + #define OMAP36XX_CONTROL_MEM_RTA_CTRL	0x40C
- + #define OMAP36XX_RTA_DISABLE		0x0
- + 
- + /* 34xx D2D idle-related pins, handled by PM core */
- + #define OMAP3_PADCONF_SAD2D_MSTANDBY   0x250
- + #define OMAP3_PADCONF_SAD2D_IDLEACK    0x254
- + 
- + /* TI81XX CONTROL_DEVCONF register offsets */
- + #define TI81XX_CONTROL_DEVICE_ID	(TI81XX_CONTROL_DEVCONF + 0x000)
- + 
- + /*
- +  * REVISIT: This list of registers is not comprehensive - there are more
- +  * that should be added.
- +  */
- + 
- + /*
- +  * Control module register bit defines - these should eventually go into
- +  * their own regbits file.  Some of these will be complicated, depending
- +  * on the device type (general-purpose, emulator, test, secure, bad, other)
- +  * and the security mode (secure, non-secure, don't care)
- +  */
- + /* CONTROL_DEVCONF0 bits */
- + #define OMAP2_MMCSDIO1ADPCLKISEL	(1 << 24) /* MMC1 loop back clock */
- + #define OMAP24XX_USBSTANDBYCTRL		(1 << 15)
- + #define OMAP2_MCBSP2_CLKS_MASK		(1 << 6)
- + #define OMAP2_MCBSP1_FSR_MASK		(1 << 4)
- + #define OMAP2_MCBSP1_CLKR_MASK		(1 << 3)
- + #define OMAP2_MCBSP1_CLKS_MASK		(1 << 2)
- + 
- + /* CONTROL_DEVCONF1 bits */
- + #define OMAP243X_MMC1_ACTIVE_OVERWRITE	(1 << 31)
- + #define OMAP2_MMCSDIO2ADPCLKISEL	(1 << 6) /* MMC2 loop back clock */
- + #define OMAP2_MCBSP5_CLKS_MASK		(1 << 4) /* > 242x */
- + #define OMAP2_MCBSP4_CLKS_MASK		(1 << 2) /* > 242x */
- + #define OMAP2_MCBSP3_CLKS_MASK		(1 << 0) /* > 242x */
- + 
- + /* CONTROL_STATUS bits */
- + #define OMAP2_DEVICETYPE_MASK		(0x7 << 8)
- + #define OMAP2_SYSBOOT_5_MASK		(1 << 5)
- + #define OMAP2_SYSBOOT_4_MASK		(1 << 4)
- + #define OMAP2_SYSBOOT_3_MASK		(1 << 3)
- + #define OMAP2_SYSBOOT_2_MASK		(1 << 2)
- + #define OMAP2_SYSBOOT_1_MASK		(1 << 1)
- + #define OMAP2_SYSBOOT_0_MASK		(1 << 0)
- + 
- + /* CONTROL_PBIAS_LITE bits */
- + #define OMAP343X_PBIASLITESUPPLY_HIGH1	(1 << 15)
- + #define OMAP343X_PBIASLITEVMODEERROR1	(1 << 11)
- + #define OMAP343X_PBIASSPEEDCTRL1	(1 << 10)
- + #define OMAP343X_PBIASLITEPWRDNZ1	(1 << 9)
- + #define OMAP343X_PBIASLITEVMODE1	(1 << 8)
- + #define OMAP343X_PBIASLITESUPPLY_HIGH0	(1 << 7)
- + #define OMAP343X_PBIASLITEVMODEERROR0	(1 << 3)
- + #define OMAP2_PBIASSPEEDCTRL0		(1 << 2)
- + #define OMAP2_PBIASLITEPWRDNZ0		(1 << 1)
- + #define OMAP2_PBIASLITEVMODE0		(1 << 0)
- + 
- + /* CONTROL_PROG_IO1 bits */
- + #define OMAP3630_PRG_SDMMC1_SPEEDCTRL	(1 << 20)
- + 
- + /* CONTROL_IVA2_BOOTMOD bits */
- + #define OMAP3_IVA2_BOOTMOD_SHIFT	0
- + #define OMAP3_IVA2_BOOTMOD_MASK		(0xf << 0)
- + #define OMAP3_IVA2_BOOTMOD_IDLE		(0x1 << 0)
- + 
- + /* CONTROL_PADCONF_X bits */
- + #define OMAP3_PADCONF_WAKEUPEVENT0	(1 << 15)
- + #define OMAP3_PADCONF_WAKEUPENABLE0	(1 << 14)
- + 
- + #define OMAP343X_SCRATCHPAD_ROM		(OMAP343X_CTRL_BASE + 0x860)
- + #define OMAP343X_SCRATCHPAD		(OMAP343X_CTRL_BASE + 0x910)
- + #define OMAP343X_SCRATCHPAD_ROM_OFFSET	0x19C
- + #define OMAP343X_SCRATCHPAD_REGADDR(reg)	OMAP2_L4_IO_ADDRESS(\
- + 						OMAP343X_SCRATCHPAD + reg)
- + 
- + /* AM35XX_CONTROL_IPSS_CLK_CTRL bits */
- + #define AM35XX_USBOTG_VBUSP_CLK_SHIFT   0
- + #define AM35XX_CPGMAC_VBUSP_CLK_SHIFT   1
- + #define AM35XX_VPFE_VBUSP_CLK_SHIFT     2
- + #define AM35XX_HECC_VBUSP_CLK_SHIFT     3
- + #define AM35XX_USBOTG_FCLK_SHIFT        8
- + #define AM35XX_CPGMAC_FCLK_SHIFT        9
- + #define AM35XX_VPFE_FCLK_SHIFT          10
- + 
- + /*AM35XX CONTROL_LVL_INTR_CLEAR bits*/
- + #define AM35XX_CPGMAC_C0_MISC_PULSE_CLR	BIT(0)
- + #define AM35XX_CPGMAC_C0_RX_PULSE_CLR	BIT(1)
- + #define AM35XX_CPGMAC_C0_RX_THRESH_CLR	BIT(2)
- + #define AM35XX_CPGMAC_C0_TX_PULSE_CLR	BIT(3)
- + #define AM35XX_USBOTGSS_INT_CLR		BIT(4)
- + #define AM35XX_VPFE_CCDC_VD0_INT_CLR	BIT(5)
- + #define AM35XX_VPFE_CCDC_VD1_INT_CLR	BIT(6)
- + #define AM35XX_VPFE_CCDC_VD2_INT_CLR	BIT(7)
- + 
- + /*AM35XX CONTROL_IP_SW_RESET bits*/
- + #define AM35XX_USBOTGSS_SW_RST		BIT(0)
- + #define AM35XX_CPGMACSS_SW_RST		BIT(1)
- + #define AM35XX_VPFE_VBUSP_SW_RST	BIT(2)
- + #define AM35XX_HECC_SW_RST		BIT(3)
- + #define AM35XX_VPFE_PCLK_SW_RST		BIT(4)
- + 
- + /* AM33XX CONTROL_STATUS bits */
- + #define AM33XX_SYSBOOT0			(0xff << 0)
- + #define AM33XX_DEVTYPE			(1 << 8)
- + #define AM33XX_GPMC_CS0_BW		(1 << 16)
- + #define AM33XX_GPMC_CS0_WAITEN		(1 << 17)
- + #define AM33XX_GPMC_CS0_ADMUX		(0x3 << 18)
- + #define AM33XX_SYSBOOT1			(0x3 << 22)
- + 
- + /*
- +  * CONTROL AM33XX STATUS register to identify boot-time configurations
- +  */
- + #define AM33XX_CONTROL_STATUS_OFF	0x040
- + #define AM33XX_CONTROL_STATUS		AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE + \
- + 						AM33XX_CONTROL_STATUS_OFF)
- + #define AM33XX_DEV_FEATURE		0x604
- + #define AM33XX_SGX_SHIFT		29
- + #define AM33XX_SGX_MASK			(1 << AM33XX_SGX_SHIFT)
- + 
- + /*
- +  * CONTROL AM33XX GMII_SEL register for MII mode selection
- +  */
- + #define AM33XX_CONTROL_GMII_SEL_OFFSET	0x650
- + #define AM33XX_RGMII_DISABLE_INT_DLY	(BIT(4) | BIT(5))
- + #define AM33XX_MII_MODE_EN		0x0
- + #define AM33XX_RMII_MODE_EN		((1 << 0) | (1 << 2))
- + #define AM33XX_RGMII_MODE_EN		((0x2 << 0) | (0x2 << 2) | \
- + 					(AM33XX_RGMII_DISABLE_INT_DLY))
- + 
- + /*
- +  * CONTROL AM33XX PWMSS_CTRL register to enable time base clock Enable
- +  */
- + 
- + #define AM33XX_CONTROL_PWMSS_CTRL_OFS	0x664
- + #define AM33XX_PWMSS0_TBCLKEN		0x0
- + #define AM33XX_PWMSS1_TBCLKEN		0x1
- + #define AM33XX_PWMSS2_TBCLKEN		0x2
- + #define AM33XX_CONTROL_PWMSS_CTRL	AM33XX_L4_WK_IO_ADDRESS( \
- + 		AM33XX_CTRL_BASE + AM33XX_CONTROL_PWMSS_CTRL_OFS)
- + 
- + /*
- +  * CONTROL OMAP STATUS register to identify OMAP3 features
- +  */
- + #define OMAP3_CONTROL_OMAP_STATUS	0x044c
- + 
- + #define OMAP3_SGX_SHIFT			13
- + #define OMAP3_SGX_MASK			(3 << OMAP3_SGX_SHIFT)
- + #define		FEAT_SGX_FULL		0
- + #define		FEAT_SGX_HALF		1
- + #define		FEAT_SGX_NONE		2
- + 
- + #define OMAP3_IVA_SHIFT			12
- + #define OMAP3_IVA_MASK			(1 << OMAP3_IVA_SHIFT)
- + #define		FEAT_IVA		0
- + #define		FEAT_IVA_NONE		1
- + 
- + #define OMAP3_L2CACHE_SHIFT		10
- + #define OMAP3_L2CACHE_MASK		(3 << OMAP3_L2CACHE_SHIFT)
- + #define		FEAT_L2CACHE_NONE	0
- + #define		FEAT_L2CACHE_64KB	1
- + #define		FEAT_L2CACHE_128KB	2
- + #define		FEAT_L2CACHE_256KB	3
- + 
- + #define OMAP3_ISP_SHIFT			5
- + #define OMAP3_ISP_MASK			(1 << OMAP3_ISP_SHIFT)
- + #define		FEAT_ISP		0
- + #define		FEAT_ISP_NONE		1
- + 
- + #define OMAP3_NEON_SHIFT		4
- + #define OMAP3_NEON_MASK			(1 << OMAP3_NEON_SHIFT)
- + #define		FEAT_NEON		0
- + #define		FEAT_NEON_NONE		1
- + 
- + 
- + #ifndef __ASSEMBLY__
- + extern void __iomem *omap_ctrl_base_get(void);
- + extern u8 omap_ctrl_readb(u16 offset);
- + extern u16 omap_ctrl_readw(u16 offset);
- + extern u32 omap_ctrl_readl(u16 offset);
- + extern u32 omap4_ctrl_pad_readl(u16 offset);
- + extern void omap_ctrl_writeb(u8 val, u16 offset);
- + extern void omap_ctrl_writew(u16 val, u16 offset);
- + extern void omap_ctrl_writel(u32 val, u16 offset);
- + extern void omap4_ctrl_pad_writel(u32 val, u16 offset);
- + 
- + extern void omap3_save_scratchpad_contents(void);
- + extern void omap3_clear_scratchpad_contents(void);
- + extern void omap3_restore(void);
- + extern void omap3_restore_es3(void);
- + extern void omap3_restore_3630(void);
- + extern u32 omap3_arm_context[128];
- + extern void omap3_control_save_context(void);
- + extern void omap3_control_restore_context(void);
- + extern void omap3_ctrl_write_boot_mode(u8 bootmode);
- + extern void omap3630_ctrl_disable_rta(void);
- + extern int omap3_ctrl_save_padconf(void);
- + #endif	/* __ASSEMBLY__ */
- + 
- + #endif /* __ARCH_ARM_MACH_CKB_3352_CONTROL_H */
- + 
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/cpuidle33xx.c linux-3.2.1/arch/arm/mach-ckb_3352/cpuidle33xx.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/cpuidle33xx.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/cpuidle33xx.c	2014-05-15 13:25:13.899315714 +0900
- ***************
- *** 0 ****
- --- 1,179 ----
- + /*
- +  * CPU idle for AM33XX SoCs
- +  *
- +  * Copyright (C) 2011 Texas Instruments Incorporated. http://www.ti.com/
- +  *
- +  * Derived from Davinci CPU idle code
- +  * (arch/arm/mach-davinci/cpuidle.c)
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #include <linux/kernel.h>
- + #include <linux/module.h>
- + #include <linux/init.h>
- + #include <linux/io.h>
- + #include <linux/platform_device.h>
- + #include <linux/cpuidle.h>
- + #include <linux/sched.h>
- + #include <asm/proc-fns.h>
- + 
- + #include <plat/emif.h>
- + 
- + #include "cpuidle33xx.h"
- + 
- + #define AM33XX_CPUIDLE_MAX_STATES	2
- + 
- + struct am33xx_ops {
- + 	void (*enter) (u32 flags);
- + 	void (*exit) (u32 flags);
- + 	u32 flags;
- + };
- + 
- + /* fields in am33xx_ops.flags */
- + #define AM33XX_CPUIDLE_FLAGS_DDR2_PWDN	BIT(0)
- + 
- + static struct cpuidle_driver am33xx_idle_driver = {
- + 	.name	= "cpuidle-am33xx",
- + 	.owner	= THIS_MODULE,
- + };
- + 
- + static DEFINE_PER_CPU(struct cpuidle_device, am33xx_cpuidle_device);
- + static void __iomem *emif_base;
- + 
- + static void am33xx_save_ddr_power(int enter, bool pdown)
- + {
- + 	u32 val;
- + 
- + 	val = __raw_readl(emif_base + EMIF4_0_SDRAM_MGMT_CTRL);
- + 
- + 	/* TODO: Choose the mode based on memory type */
- + 	if (enter)
- + 		val = SELF_REFRESH_ENABLE(64);
- + 	else
- + 		val = SELF_REFRESH_DISABLE;
- + 
- + 	__raw_writel(val, emif_base + EMIF4_0_SDRAM_MGMT_CTRL);
- + }
- + 
- + static void am33xx_c2state_enter(u32 flags)
- + {
- + 	am33xx_save_ddr_power(1, !!(flags & AM33XX_CPUIDLE_FLAGS_DDR2_PWDN));
- + }
- + 
- + static void am33xx_c2state_exit(u32 flags)
- + {
- + 	am33xx_save_ddr_power(0, !!(flags & AM33XX_CPUIDLE_FLAGS_DDR2_PWDN));
- + }
- + 
- + static struct am33xx_ops am33xx_states[AM33XX_CPUIDLE_MAX_STATES] = {
- + 	[1] = {
- + 		.enter	= am33xx_c2state_enter,
- + 		.exit	= am33xx_c2state_exit,
- + 	},
- + };
- + 
- + /* Actual code that puts the SoC in different idle states */
- + static int am33xx_enter_idle(struct cpuidle_device *dev,
- + 				struct cpuidle_driver *drv, int index)
- + {
- + 	struct cpuidle_state_usage *state_usage = &dev->states_usage[index];
- + 	struct am33xx_ops *ops = cpuidle_get_statedata(state_usage);
- + 	struct timeval before, after;
- + 	int idle_time;
- + 
- + 	local_irq_disable();
- + 	do_gettimeofday(&before);
- + 
- + 	if (ops && ops->enter)
- + 		ops->enter(ops->flags);
- + 
- + 	/* Wait for interrupt state */
- + 	cpu_do_idle();
- + 	if (ops && ops->exit)
- + 		ops->exit(ops->flags);
- + 
- + 	do_gettimeofday(&after);
- + 	local_irq_enable();
- + 	idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
- + 			(after.tv_usec - before.tv_usec);
- + 
- + 	dev->last_residency = idle_time;
- + 
- + 	return index;
- + }
- + 
- + static int __init am33xx_cpuidle_probe(struct platform_device *pdev)
- + {
- + 	int ret;
- + 	struct cpuidle_device *device;
- + 	struct cpuidle_driver *driver = &am33xx_idle_driver;
- + 	struct am33xx_cpuidle_config *pdata = pdev->dev.platform_data;
- + 
- + 	device = &per_cpu(am33xx_cpuidle_device, smp_processor_id());
- + 
- + 	if (!pdata) {
- + 		dev_err(&pdev->dev, "cannot get platform data\n");
- + 		return -ENOENT;
- + 	}
- + 
- + 	emif_base = pdata->emif_base;
- + 
- + 	/* Wait for interrupt state */
- + 	driver->states[0].enter = am33xx_enter_idle;
- + 	driver->states[0].exit_latency = 1;
- + 	driver->states[0].target_residency = 10000;
- + 	driver->states[0].flags = CPUIDLE_FLAG_TIME_VALID;
- + 	strcpy(driver->states[0].name, "WFI");
- + 	strcpy(driver->states[0].desc, "Wait for interrupt");
- + 
- + 	/* Wait for interrupt and DDR self refresh state */
- + 	driver->states[1].enter = am33xx_enter_idle;
- + 	driver->states[1].exit_latency = 100;
- + 	driver->states[1].target_residency = 10000;
- + 	driver->states[1].flags = CPUIDLE_FLAG_TIME_VALID;
- + 	strcpy(driver->states[1].name, "DDR SR");
- + 	strcpy(driver->states[1].desc, "WFI and DDR Self Refresh");
- + 	if (pdata->ddr2_pdown)
- + 		am33xx_states[1].flags |= AM33XX_CPUIDLE_FLAGS_DDR2_PWDN;
- + 	cpuidle_set_statedata(&device->states_usage[1], &am33xx_states[1]);
- + 
- + 	device->state_count = AM33XX_CPUIDLE_MAX_STATES;
- + 	driver->state_count = AM33XX_CPUIDLE_MAX_STATES;
- + 
- + 	ret = cpuidle_register_driver(&am33xx_idle_driver);
- + 	if (ret) {
- + 		dev_err(&pdev->dev, "failed to register driver\n");
- + 		return ret;
- + 	}
- + 
- + 	ret = cpuidle_register_device(device);
- + 	if (ret) {
- + 		dev_err(&pdev->dev, "failed to register device\n");
- + 		cpuidle_unregister_driver(&am33xx_idle_driver);
- + 		return ret;
- + 	}
- + 
- + 	return 0;
- + }
- + 
- + static struct platform_driver am33xx_cpuidle_driver = {
- + 	.driver = {
- + 		.name	= "cpuidle-am33xx",
- + 		.owner	= THIS_MODULE,
- + 	},
- + };
- + 
- + static int __init am33xx_cpuidle_init(void)
- + {
- + 	return platform_driver_probe(&am33xx_cpuidle_driver,
- + 						am33xx_cpuidle_probe);
- + }
- + device_initcall(am33xx_cpuidle_init);
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/cpuidle33xx.h linux-3.2.1/arch/arm/mach-ckb_3352/cpuidle33xx.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/cpuidle33xx.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/cpuidle33xx.h	2014-05-15 13:25:13.899315714 +0900
- ***************
- *** 0 ****
- --- 1,24 ----
- + /*
- +  * TI AM33XX cpuidle platform support
- +  *
- +  * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #ifndef _AM33XX_CPUIDLE_H
- + #define _AM33XX_CPUIDLE_H
- + 
- + struct am33xx_cpuidle_config {
- + 	u32 ddr2_pdown;
- + 	void __iomem *emif_base;
- + };
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/devices.c linux-3.2.1/arch/arm/mach-ckb_3352/devices.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/devices.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/devices.c	2014-05-15 13:25:13.899315714 +0900
- ***************
- *** 0 ****
- --- 1,1287 ----
- + /*
- +  * linux/arch/arm/mach-omap2/devices.c
- +  *
- +  * OMAP2 platform device setup/initialization
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; either version 2 of the License, or
- +  * (at your option) any later version.
- +  */
- + #include <linux/gpio.h>
- + #include <linux/kernel.h>
- + #include <linux/init.h>
- + #include <linux/platform_device.h>
- + #include <linux/io.h>
- + #include <linux/clk.h>
- + #include <linux/err.h>
- + #include <linux/export.h>
- + #include <linux/slab.h>
- + #include <linux/of.h>
- + #include <linux/davinci_emac.h>
- + #include <linux/cpsw.h>
- + #include <linux/etherdevice.h>
- + #include <linux/dma-mapping.h>
- + #include <linux/can/platform/d_can.h>
- + #include <linux/platform_data/uio_pruss.h>
- + #include <linux/pwm/pwm.h>
- + 
- + #include <mach/hardware.h>
- + #include <mach/irqs.h>
- + #include <asm/mach-types.h>
- + #include <asm/mach/map.h>
- + #include <asm/pmu.h>
- + 
- + #ifdef	CONFIG_OMAP3_EDMA
- + #include <mach/edma.h>
- + #endif
- + 
- + 
- + 
- + #include <plat/board.h>
- + #include <plat/mmc.h>
- + #include <plat/dma.h>
- + #include <plat/omap_hwmod.h>
- + #include <plat/omap_device.h>
- + #include <plat/am33xx.h>
- + #include <plat/config_pwm.h>
- + #include <plat/cpu.h>
- + #include <plat/gpmc.h>
- + #include <plat/smartreflex.h>
- + #include <plat/am33xx.h>
- + 
- + /* LCD controller similar DA8xx */
- + #include <video/da8xx-fb.h>
- + 
- + #include "mux.h"
- + #include "control.h"
- + #include "devices.h"
- + #include "omap_opp_data.h"
- + 
- + #define L3_MODULES_MAX_LEN 12
- + #define L3_MODULES 3
- + 
- + static unsigned int   am33xx_evmid;
- + 
- + /*
- +  * am33xx_evmid_fillup - set up board evmid
- +  * @evmid - evm id which needs to be configured
- +  *
- +  * This function is called to configure board evm id.
- +  * IA Motor Control EVM needs special setting of MAC PHY Id.
- +  * This function is called when IA Motor Control EVM is detected
- +  * during boot-up.
- +  */
- + void am33xx_evmid_fillup(unsigned int evmid)
- + {
- +        am33xx_evmid = evmid;
- +        return;
- + }
- + 
- + static int __init omap3_l3_init(void)
- + {
- + 	int l;
- + 	struct omap_hwmod *oh;
- + 	struct platform_device *pdev;
- + 	char oh_name[L3_MODULES_MAX_LEN];
- + 
- + 	l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
- + 
- + 	oh = omap_hwmod_lookup(oh_name);
- + 
- + 	if (!oh)
- + 		pr_err("could not look up %s\n", oh_name);
- + 
- + 	pdev = omap_device_build("omap_l3_smx", 0, oh, NULL, 0,
- + 							   NULL, 0, 0);
- + 
- + 	WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
- + 
- + 	return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
- + }
- + postcore_initcall(omap3_l3_init);
- + 
- + #if defined(CONFIG_CKB_LCD_SUPPORT) || defined(CONFIG_CKB_DVI_SUPPORT)
- + int __init am33xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
- + {
- + 	int id = 0;
- + 	struct platform_device *pdev;
- + 	struct omap_hwmod *oh;
- + 	char *oh_name = "lcdc";
- + 	char *dev_name = "da8xx_lcdc";
- + 
- + 	oh = omap_hwmod_lookup(oh_name);
- + 	if (!oh) {
- + 		pr_err("Could not look up LCD%d hwmod\n", id);
- + 		return -ENODEV;
- + 	}
- + 
- + 	pdev = omap_device_build(dev_name, id, oh, pdata,
- + 			sizeof(struct da8xx_lcdc_platform_data), NULL, 0, 0);
- + 	if (IS_ERR(pdev)) {
- + 		WARN(1, "Can't build omap_device for %s:%s.\n",
- + 			dev_name, oh->name);
- + 		return PTR_ERR(pdev);
- + 	}
- + 	return 0;
- + }
- + #endif
- + 
- + #ifdef CONFIG_CKB_3352_AUDIO
- + int __init am335x_register_mcasp(struct snd_platform_data *pdata, int ctrl_nr)
- + {
- + 	int l;
- + 	struct omap_hwmod *oh;
- + 	struct platform_device *pdev;
- + 	char oh_name[12];
- + 	char *dev_name = "davinci-mcasp";
- + 
- + 	l = snprintf(oh_name, 12, "mcasp%d", ctrl_nr);
- + 
- + 	oh = omap_hwmod_lookup(oh_name);
- + 	if (!oh) {
- + 		pr_err("could not look up %s\n", oh_name);
- + 		return -ENODEV;
- + 	}
- + 
- + 	pdev = omap_device_build(dev_name, ctrl_nr, oh, pdata,
- + 			sizeof(struct snd_platform_data), NULL, 0, 0);
- + 	WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
- + 			dev_name, oh->name);
- + 	return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
- + }
- + 
- + 
- + 
- + 
- + 
- + 
- + #endif
- + 
- + #ifdef CONFIG_CKB_3352_AUDIO
- + struct platform_device am33xx_pcm_device = {
- + 	.name		= "davinci-pcm-audio",
- + 	.id		= -1,
- + };
- + 
- + static void am33xx_init_pcm(void)
- + {
- + 	platform_device_register(&am33xx_pcm_device);
- + }
- + #endif
- + 
- + static struct resource omap3isp_resources[] = {
- + 	{
- + 		.start		= OMAP3430_ISP_BASE,
- + 		.end		= OMAP3430_ISP_END,
- + 		.flags		= IORESOURCE_MEM,
- + 	},
- + 	{
- + 		.start		= OMAP3430_ISP_CCP2_BASE,
- + 		.end		= OMAP3430_ISP_CCP2_END,
- + 		.flags		= IORESOURCE_MEM,
- + 	},
- + 	{
- + 		.start		= OMAP3430_ISP_CCDC_BASE,
- + 		.end		= OMAP3430_ISP_CCDC_END,
- + 		.flags		= IORESOURCE_MEM,
- + 	},
- + 	{
- + 		.start		= OMAP3430_ISP_HIST_BASE,
- + 		.end		= OMAP3430_ISP_HIST_END,
- + 		.flags		= IORESOURCE_MEM,
- + 	},
- + 	{
- + 		.start		= OMAP3430_ISP_H3A_BASE,
- + 		.end		= OMAP3430_ISP_H3A_END,
- + 		.flags		= IORESOURCE_MEM,
- + 	},
- + 	{
- + 		.start		= OMAP3430_ISP_PREV_BASE,
- + 		.end		= OMAP3430_ISP_PREV_END,
- + 		.flags		= IORESOURCE_MEM,
- + 	},
- + 	{
- + 		.start		= OMAP3430_ISP_RESZ_BASE,
- + 		.end		= OMAP3430_ISP_RESZ_END,
- + 		.flags		= IORESOURCE_MEM,
- + 	},
- + 	{
- + 		.start		= OMAP3430_ISP_SBL_BASE,
- + 		.end		= OMAP3430_ISP_SBL_END,
- + 		.flags		= IORESOURCE_MEM,
- + 	},
- + 	{
- + 		.start		= OMAP3430_ISP_CSI2A_REGS1_BASE,
- + 		.end		= OMAP3430_ISP_CSI2A_REGS1_END,
- + 		.flags		= IORESOURCE_MEM,
- + 	},
- + 	{
- + 		.start		= OMAP3430_ISP_CSIPHY2_BASE,
- + 		.end		= OMAP3430_ISP_CSIPHY2_END,
- + 		.flags		= IORESOURCE_MEM,
- + 	},
- + 	{
- + 		.start		= OMAP3630_ISP_CSI2A_REGS2_BASE,
- + 		.end		= OMAP3630_ISP_CSI2A_REGS2_END,
- + 		.flags		= IORESOURCE_MEM,
- + 	},
- + 	{
- + 		.start		= OMAP3630_ISP_CSI2C_REGS1_BASE,
- + 		.end		= OMAP3630_ISP_CSI2C_REGS1_END,
- + 		.flags		= IORESOURCE_MEM,
- + 	},
- + 	{
- + 		.start		= OMAP3630_ISP_CSIPHY1_BASE,
- + 		.end		= OMAP3630_ISP_CSIPHY1_END,
- + 		.flags		= IORESOURCE_MEM,
- + 	},
- + 	{
- + 		.start		= OMAP3630_ISP_CSI2C_REGS2_BASE,
- + 		.end		= OMAP3630_ISP_CSI2C_REGS2_END,
- + 		.flags		= IORESOURCE_MEM,
- + 	},
- + 	{
- + 		.start		= INT_34XX_CAM_IRQ,
- + 		.flags		= IORESOURCE_IRQ,
- + 	}
- + };
- + 
- + static struct platform_device omap3isp_device = {
- + 	.name		= "omap3isp",
- + 	.id		= -1,
- + 	.num_resources	= ARRAY_SIZE(omap3isp_resources),
- + 	.resource	= omap3isp_resources,
- + };
- + 
- + int omap3_init_camera(struct isp_platform_data *pdata)
- + {
- + 	omap3isp_device.dev.platform_data = pdata;
- + 	return platform_device_register(&omap3isp_device);
- + }
- + 
- + static inline void omap_init_mbox(void)
- + {
- + 	struct omap_hwmod *oh;
- + 	struct platform_device *pdev;
- + 
- + 	oh = omap_hwmod_lookup("mailbox");
- + 	if (!oh) {
- + 		pr_err("%s: unable to find hwmod\n", __func__);
- + 		return;
- + 	}
- + 
- + 	pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0, NULL, 0, 0);
- + 	WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n",
- + 						__func__, PTR_ERR(pdev));
- + }
- + static inline void omap_init_sti(void) {}
- + 
- + #if defined(CONFIG_SND_OMAP_SOC_MCPDM) || \
- + 		defined(CONFIG_SND_OMAP_SOC_MCPDM_MODULE)
- + 
- + static void omap_init_mcpdm(void)
- + {
- + 	struct omap_hwmod *oh;
- + 	struct platform_device *pdev;
- + 
- + 	oh = omap_hwmod_lookup("mcpdm");
- + 	if (!oh) {
- + 		printk(KERN_ERR "Could not look up mcpdm hw_mod\n");
- + 		return;
- + 	}
- + 
- + 	pdev = omap_device_build("omap-mcpdm", -1, oh, NULL, 0, NULL, 0, 0);
- + 	WARN(IS_ERR(pdev), "Can't build omap_device for omap-mcpdm.\n");
- + }
- + #else
- + static inline void omap_init_mcpdm(void) {}
- + #endif
- + 
- + #if defined(CONFIG_SND_OMAP_SOC_DMIC) || \
- + 		defined(CONFIG_SND_OMAP_SOC_DMIC_MODULE)
- + 
- + static void omap_init_dmic(void)
- + {
- + 	struct omap_hwmod *oh;
- + 	struct platform_device *pdev;
- + 
- + 	oh = omap_hwmod_lookup("dmic");
- + 	if (!oh) {
- + 		printk(KERN_ERR "Could not look up mcpdm hw_mod\n");
- + 		return;
- + 	}
- + 
- + 	pdev = omap_device_build("omap-dmic", -1, oh, NULL, 0, NULL, 0, 0);
- + 	WARN(IS_ERR(pdev), "Can't build omap_device for omap-dmic.\n");
- + }
- + #else
- + static inline void omap_init_dmic(void) {}
- + #endif
- + 
- + #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
- + 
- + #include <plat/mcspi.h>
- + 
- + static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
- + {
- + 	struct platform_device *pdev;
- + 	char *name = "omap2_mcspi";
- + 	struct omap2_mcspi_platform_config *pdata;
- + 	static int spi_num;
- + 	struct omap2_mcspi_dev_attr *mcspi_attrib = oh->dev_attr;
- + 
- + 	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
- + 	if (!pdata) {
- + 		pr_err("Memory allocation for McSPI device failed\n");
- + 		return -ENOMEM;
- + 	}
- + 
- + 	pdata->num_cs = mcspi_attrib->num_chipselect;
- + 	switch (oh->class->rev) {
- + 	case OMAP2_MCSPI_REV:
- + 	case OMAP3_MCSPI_REV:
- + 			pdata->regs_offset = 0;
- + 			break;
- + 	case OMAP4_MCSPI_REV:
- + 			pdata->regs_offset = OMAP4_MCSPI_REG_OFFSET;
- + 			break;
- + 	default:
- + 			pr_err("Invalid McSPI Revision value\n");
- + 			return -EINVAL;
- + 	}
- + 
- + 	spi_num++;
- + 	pdev = omap_device_build(name, spi_num, oh, pdata,
- + 				sizeof(*pdata),	NULL, 0, 0);
- + 	WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s\n",
- + 				name, oh->name);
- + 	kfree(pdata);
- + 	return 0;
- + }
- + 
- + static void omap_init_mcspi(void)
- + {
- + 	omap_hwmod_for_each_by_class("mcspi", omap_mcspi_init, NULL);
- + }
- + 
- + #else
- + static inline void omap_init_mcspi(void) {}
- + #endif
- + 
- + int __init omap_init_elm(void)
- + {
- + 	int id = -1;
- + 	struct platform_device *pdev;
- + 	struct omap_hwmod *oh;
- + 	char *oh_name = "elm";
- + 	char *name = "omap2_elm";
- + 
- + 	oh = omap_hwmod_lookup(oh_name);
- + 	if (!oh) {
- + 		pr_err("Could not look up %s\n", oh_name);
- + 		return -ENODEV;
- + 	}
- + 
- + 	pdev = omap_device_build(name, id, oh, NULL, 0, NULL, 0, 0);
- + 
- + 	if (IS_ERR(pdev)) {
- + 		WARN(1, "Can't build omap_device for %s:%s.\n",
- + 						name, oh->name);
- + 		return PTR_ERR(pdev);
- + 	}
- + 
- + 	return 0;
- + }
- + 
- + #ifdef CONFIG_SOC_OMAPAM33XX
- + #define PWM_STR_LEN 10
- + int __init am33xx_register_ecap(int id, struct pwmss_platform_data *pdata)
- + {
- + 	struct platform_device *pdev;
- + 	struct omap_hwmod *oh;
- + 	char *oh_name = "ecap";
- + 	char dev_name[PWM_STR_LEN];
- + 
- + 	sprintf(dev_name, "ecap.%d", id);
- + 
- + 	oh = omap_hwmod_lookup(dev_name);
- + 	if (!oh) {
- + 		pr_err("Could not look up %s hwmod\n", dev_name);
- + 		return -ENODEV;
- + 	}
- + 
- + 	pdev = omap_device_build(oh_name, id, oh, pdata,
- + 			sizeof(*pdata), NULL, 0, 0);
- + 
- + 	if (IS_ERR(pdev)) {
- + 		WARN(1, "Can't build omap_device for %s:%s.\n",
- + 			dev_name, oh->name);
- + 		return PTR_ERR(pdev);
- + 	}
- + 	return 0;
- + }
- + 
- + int __init am33xx_register_ehrpwm(int id, struct pwmss_platform_data *pdata)
- + {
- + 	struct platform_device *pdev;
- + 	struct omap_hwmod *oh;
- + 	char *oh_name = "ehrpwm";
- + 	char dev_name[PWM_STR_LEN];
- + 
- + 	sprintf(dev_name, "ehrpwm.%d", id);
- + 
- + 	oh = omap_hwmod_lookup(dev_name);
- + 	if (!oh) {
- + 		pr_err("Could not look up %s hwmod\n", dev_name);
- + 		return -ENODEV;
- + 	}
- + 
- + 	pdev = omap_device_build(oh_name, id, oh, pdata,
- + 			sizeof(*pdata), NULL, 0, 0);
- + 
- + 	if (IS_ERR(pdev)) {
- + 		WARN(1, "Can't build omap_device for %s:%s.\n",
- + 			dev_name, oh->name);
- + 		return PTR_ERR(pdev);
- + 	}
- + 	return 0;
- + }
- + 
- + #else
- + static int __init am335x_register_ehrpwm(int id,
- + 		struct pwmss_platform_data *pdata) { }
- + static int __init am335x_register_ecap(int id,
- + 		struct pwmss_platform_data *pdata) { }
- + #endif
- + #if defined(CONFIG_CRYPTO_DEV_OMAP4_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP4_SHAM_MODULE)
- + static void __init omap_init_sham(void)
- + {
- + 	struct omap_hwmod *oh;
- + 	struct platform_device *pdev;
- + 
- + 	oh = omap_hwmod_lookup("sha0");
- + 	if (!oh)
- + 		return;
- + 
- + 	pdev = omap_device_build("omap4-sham", -1, oh, NULL, 0, NULL, 0, 0);
- + 	WARN(IS_ERR(pdev), "Can't build omap_device for omap-sham\n");
- + }
- + #else
- + static inline void omap_init_sham(void) { }
- + #endif
- + #if defined(CONFIG_CRYPTO_DEV_OMAP4_AES) || defined(CONFIG_CRYPTO_DEV_OMAP4_AES_MODULE)
- + static void __init omap_init_aes(void)
- + {
- + 	struct omap_hwmod *oh;
- + 	struct platform_device *pdev;
- + 
- + 	oh = omap_hwmod_lookup("aes0");
- + 	if (!oh)
- + 		return;
- + 
- + 	pdev = omap_device_build("omap4-aes", -1, oh, NULL, 0, NULL, 0, 0);
- + 	WARN(IS_ERR(pdev), "Can't build omap_device for omap-aes\n");
- + }
- + #else
- + static inline void omap_init_aes(void) { }
- + #endif
- + 
- + 
- + /*-------------------------------------------------------------------------*/
- + 
- + #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
- + #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430)
- + #define OMAP_HDQ_BASE	0x480B2000
- + #endif
- + static struct resource omap_hdq_resources[] = {
- + 	{
- + 		.start		= OMAP_HDQ_BASE,
- + 		.end		= OMAP_HDQ_BASE + 0x1C,
- + 		.flags		= IORESOURCE_MEM,
- + 	},
- + 	{
- + 		.start		= INT_24XX_HDQ_IRQ,
- + 		.flags		= IORESOURCE_IRQ,
- + 	},
- + };
- + static struct platform_device omap_hdq_dev = {
- + 	.name = "omap_hdq",
- + 	.id = 0,
- + 	.dev = {
- + 		.platform_data = NULL,
- + 	},
- + 	.num_resources	= ARRAY_SIZE(omap_hdq_resources),
- + 	.resource	= omap_hdq_resources,
- + };
- + static inline void omap_hdq_init(void)
- + {
- + 	(void) platform_device_register(&omap_hdq_dev);
- + }
- + #else
- + static inline void omap_hdq_init(void) {}
- + #endif
- + 
- + /*---------------------------------------------------------------------------*/
- + 
- + #if defined(CONFIG_VIDEO_OMAP2_VOUT) || \
- + 	defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE)
- + #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
- + static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = {
- + };
- + #else
- + static struct resource omap_vout_resource[2] = {
- + };
- + #endif
- + 
- + static struct platform_device omap_vout_device = {
- + 	.name		= "omap_vout",
- + 	.num_resources	= ARRAY_SIZE(omap_vout_resource),
- + 	.resource 	= &omap_vout_resource[0],
- + 	.id		= -1,
- + };
- + static void omap_init_vout(void)
- + {
- + 	if (platform_device_register(&omap_vout_device) < 0)
- + 		printk(KERN_ERR "Unable to register OMAP-VOUT device\n");
- + }
- + #else
- + static inline void omap_init_vout(void) {}
- + #endif
- + 
- + #if defined(CONFIG_SOC_OMAPAM33XX) && defined(CONFIG_OMAP3_EDMA)
- + 
- + #define AM33XX_SCM_BASE_EDMA		0x00000f90
- + 
- + static const s16 am33xx_dma_rsv_chans[][2] = {
- + 	/* (offset, number) */
- + 	{0, 2},
- + 	{14, 2},
- + 	{26, 6},
- + 	{48, 4},
- + 	{56, 8},
- + 	{-1, -1}
- + };
- + 
- + static const s16 am33xx_dma_rsv_slots[][2] = {
- + 	/* (offset, number) */
- + 	{0, 2},
- + 	{14, 2},
- + 	{26, 6},
- + 	{48, 4},
- + 	{56, 8},
- + 	{64, 127},
- + 	{-1, -1}
- + };
- + 
- + /* Three Transfer Controllers on AM33XX */
- + static const s8 am33xx_queue_tc_mapping[][2] = {
- + 	/* {event queue no, TC no} */
- + 	{0, 0},
- + 	{1, 1},
- + 	{2, 2},
- + 	{-1, -1}
- + };
- + 
- + static const s8 am33xx_queue_priority_mapping[][2] = {
- + 	/* {event queue no, Priority} */
- + 	{0, 0},
- + 	{1, 1},
- + 	{2, 2},
- + 	{-1, -1}
- + };
- + 
- + static struct event_to_channel_map am33xx_xbar_event_mapping[] = {
- + 	/* {xbar event no, Channel} */
- + 	{1, 12},	/* SDTXEVT1 -> MMCHS2 */
- + 	{2, 13},	/* SDRXEVT1 -> MMCHS2 */
- + 	{3, -1},
- + 	{4, -1},
- + 	{5, -1},
- + 	{6, -1},
- + 	{7, -1},
- + 	{8, -1},
- + 	{9, -1},
- + 	{10, -1},
- + 	{11, -1},
- + 	{12, -1},
- + 	{13, -1},
- + 	{14, -1},
- + 	{15, -1},
- + 	{16, -1},
- + 	{17, -1},
- + 	{18, -1},
- + 	{19, -1},
- + 	{20, -1},
- + 	{21, -1},
- + 	{22, -1},
- + 	{23, -1},
- + 	{24, -1},
- + 	{25, -1},
- + 	{26, -1},
- + 	{27, -1},
- + 	{28, -1},
- + 	{29, -1},
- + 	{30, -1},
- + 	{31, -1},
- + 	{-1, -1}
- + };
- + 
- + /**
- +  * map_xbar_event_to_channel - maps a crossbar event to a DMA channel
- +  * according to the configuration provided
- +  * @event: the event number for which mapping is required
- +  * @channel: channel being activated
- +  * @xbar_event_mapping: array that has the event to channel map
- +  *
- +  * Events that are routed by default are not mapped. Only events that
- +  * are crossbar mapped are routed to available channels according to
- +  * the configuration provided
- +  *
- +  * Returns zero on success, else negative errno.
- +  */
- + int map_xbar_event_to_channel(unsigned int event, unsigned int *channel,
- + 			struct event_to_channel_map *xbar_event_mapping)
- + {
- + 	unsigned int ctrl = 0;
- + 	unsigned int xbar_evt_no = 0;
- + 	unsigned int val = 0;
- + 	unsigned int offset = 0;
- + 	unsigned int mask = 0;
- + 
- + 	ctrl = EDMA_CTLR(event);
- + 	xbar_evt_no = event - (edma_cc[ctrl]->num_channels);
- + 
- + 	if (event < edma_cc[ctrl]->num_channels) {
- + 		*channel = event;
- + 	} else if (event < edma_cc[ctrl]->num_events) {
- + 		*channel = xbar_event_mapping[xbar_evt_no].channel_no;
- + 		/* confirm the range */
- + 		if (*channel < EDMA_MAX_DMACH)
- + 			clear_bit(*channel, edma_cc[ctrl]->edma_unused);
- + 		offset = (*channel)/4;
- + 		offset *= 4;
- + 		val = (unsigned int)__raw_readl(AM33XX_CTRL_REGADDR(
- + 					AM33XX_SCM_BASE_EDMA + offset));
- + 		mask = *channel & 0x3;
- + 		mask <<= 3;
- + 		val &= ~(0xFF << mask);
- + 		val |= xbar_event_mapping[xbar_evt_no].xbar_event_no << mask;
- + 		__raw_writel(val,
- + 			AM33XX_CTRL_REGADDR(AM33XX_SCM_BASE_EDMA + offset));
- + 		return 0;
- + 	} else {
- + 		return -EINVAL;
- + 	}
- + 
- + 	return 0;
- + }
- + 
- + static struct edma_soc_info am33xx_edma_info[] = {
- + 	{
- + 		.n_channel		= 64,
- + 		.n_region		= 4,
- + 		.n_slot			= 256,
- + 		.n_tc			= 3,
- + 		.n_cc			= 1,
- + 		.rsv_chans		= am33xx_dma_rsv_chans,
- + 		.rsv_slots		= am33xx_dma_rsv_slots,
- + 		.queue_tc_mapping	= am33xx_queue_tc_mapping,
- + 		.queue_priority_mapping	= am33xx_queue_priority_mapping,
- + 		.is_xbar		= 1,
- + 		.n_events		= 95,
- + 		.xbar_event_mapping	= am33xx_xbar_event_mapping,
- + 		.map_xbar_channel	= map_xbar_event_to_channel,
- + 	},
- + };
- + 
- + static int __init am33xx_register_edma(void)
- + {
- + 	int i, l;
- + 	struct omap_hwmod *oh[4];
- + 	struct platform_device *pdev;
- + 	struct edma_soc_info *pdata = am33xx_edma_info;
- + 	char oh_name[8];
- + 
- + 	oh[0] = omap_hwmod_lookup("tpcc");
- + 	if (!oh[0]) {
- + 		pr_err("could not look up %s\n", "tpcc");
- + 		return -ENODEV;
- + 	}
- + 
- + 	for (i = 0; i < 3; i++) {
- + 		l = snprintf(oh_name, 8, "tptc%d", i);
- + 
- + 		oh[i+1] = omap_hwmod_lookup(oh_name);
- + 		if (!oh[i+1]) {
- + 			pr_err("could not look up %s\n", oh_name);
- + 			return -ENODEV;
- + 		}
- + 	}
- + 
- + 	pdev = omap_device_build_ss("edma", 0, oh, 4, pdata, sizeof(*pdata),
- + 								NULL, 0, 0);
- + 
- + 	WARN(IS_ERR(pdev), "could not build omap_device for edma\n");
- + 
- + 	return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
- + 
- + }
- + 
- + #else
- + static inline void am33xx_register_edma(void) {}
- + #endif
- + 
- + #if defined (CONFIG_SOC_OMAPAM33XX)
- + struct uio_pruss_pdata am335x_pruss_uio_pdata = {
- + 	.pintc_base	= 0x20000,
- + };
- + 
- + static struct resource am335x_pruss_resources[] = {
- + 	{
- + 		.start	= AM33XX_ICSS_BASE,
- + 		.end	= AM33XX_ICSS_BASE + AM33XX_ICSS_LEN,
- + 		.flags	= IORESOURCE_MEM,
- + 	},
- + 	{
- + 		.start	= AM33XX_IRQ_ICSS0_0,
- + 		.end	= AM33XX_IRQ_ICSS0_0,
- + 		.flags	= IORESOURCE_IRQ,
- + 	},
- + 	{
- + 		.start	= AM33XX_IRQ_ICSS0_1,
- + 		.end	= AM33XX_IRQ_ICSS0_1,
- + 		.flags	= IORESOURCE_IRQ,
- + 	},
- + 	{
- + 		.start	= AM33XX_IRQ_ICSS0_2,
- + 		.end	= AM33XX_IRQ_ICSS0_2,
- + 		.flags	= IORESOURCE_IRQ,
- + 	},
- + 	{
- + 		.start	= AM33XX_IRQ_ICSS0_3,
- + 		.end	= AM33XX_IRQ_ICSS0_3,
- + 		.flags	= IORESOURCE_IRQ,
- + 	},
- + 	{
- + 		.start	= AM33XX_IRQ_ICSS0_4,
- + 		.end	= AM33XX_IRQ_ICSS0_4,
- + 		.flags	= IORESOURCE_IRQ,
- + 	},
- + 	{
- + 		.start	= AM33XX_IRQ_ICSS0_5,
- + 		.end	= AM33XX_IRQ_ICSS0_5,
- + 		.flags	= IORESOURCE_IRQ,
- + 	},
- + 	{
- + 		.start	= AM33XX_IRQ_ICSS0_6,
- + 		.end	= AM33XX_IRQ_ICSS0_6,
- + 		.flags	= IORESOURCE_IRQ,
- + 	},
- + 	{
- + 		.start	= AM33XX_IRQ_ICSS0_7,
- + 		.end	= AM33XX_IRQ_ICSS0_7,
- + 		.flags	= IORESOURCE_IRQ,
- + 	},
- + };
- + 
- + static struct platform_device am335x_pruss_uio_dev = {
- + 	.name		= "pruss_uio",
- + 	.id		= -1,
- + 	.num_resources	= ARRAY_SIZE(am335x_pruss_resources),
- + 	.resource	= am335x_pruss_resources,
- + 	.dev	 =	{
- + 		.coherent_dma_mask = 0xffffffff,
- + 	}
- + };
- + 
- + int __init am335x_register_pruss_uio(struct uio_pruss_pdata *config)
- + {
- + 	am335x_pruss_uio_dev.dev.platform_data = config;
- + 	return platform_device_register(&am335x_pruss_uio_dev);
- + }
- + 
- + static struct platform_device am335x_sgx = {
- + 	.name	= "sgx",
- + 	.id	= -1,
- + };
- + 
- + #endif
- + 
- + #ifdef CONFIG_AM33XX_SMARTREFLEX
- + 
- + /* smartreflex platform data */
- + 
- + /* The values below are based upon silicon characterization data.
- +  * Each OPP and sensor combination potentially has different values.
- +  * The values of ERR2VOLT_GAIN and ERR_MIN_LIMIT also change based on
- +  * the PMIC step size.  Values have been given to cover the AM335 EVM
- +  * (12.5mV step) and the Beaglebone (25mV step).  If the step
- +  * size changes, you should update these values, and don't forget to
- +  * change the step size in the platform data structure, am33xx_sr_pdata.
- +  */
- + 
- + #define AM33XX_SR0_OPP50_CNTRL_OFFSET          0x07B8
- + #define AM33XX_SR0_OPP50_EVM_ERR2VOLT_GAIN     0xC
- + #define AM33XX_SR0_OPP50_EVM_ERR_MIN_LIMIT     0xF5
- + #define AM33XX_SR0_OPP50_BB_ERR2VOLT_GAIN      0x6
- + #define AM33XX_SR0_OPP50_BB_ERR_MIN_LIMIT      0xEA
- + #define AM33XX_SR0_OPP50_ERR_MAX_LIMIT         0x2
- + #define AM33XX_SR0_OPP50_ERR_WEIGHT             0x4
- + #define AM33XX_SR0_OPP50_MARGIN                 0
- + 
- + #define AM33XX_SR0_OPP100_CNTRL_OFFSET         0x07BC
- + #define AM33XX_SR0_OPP100_EVM_ERR2VOLT_GAIN     0x12
- + #define AM33XX_SR0_OPP100_EVM_ERR_MIN_LIMIT    0xF8
- + #define AM33XX_SR0_OPP100_BB_ERR2VOLT_GAIN      0x9
- + #define AM33XX_SR0_OPP100_BB_ERR_MIN_LIMIT     0xF1
- + #define AM33XX_SR0_OPP100_ERR_MAX_LIMIT                0x2
- + #define AM33XX_SR0_OPP100_ERR_WEIGHT            0x4
- + #define AM33XX_SR0_OPP100_MARGIN                0
- + 
- + #define AM33XX_SR1_OPP50_CNTRL_OFFSET          0x0770
- + #define AM33XX_SR1_OPP50_EVM_ERR2VOLT_GAIN     0x5
- + #define AM33XX_SR1_OPP50_EVM_ERR_MIN_LIMIT     0xE6
- + #define AM33XX_SR1_OPP50_BB_ERR2VOLT_GAIN      0x2
- + #define AM33XX_SR1_OPP50_BB_ERR_MIN_LIMIT      0xC0
- + #define AM33XX_SR1_OPP50_ERR_MAX_LIMIT         0x2
- + #define AM33XX_SR1_OPP50_ERR_WEIGHT             0x4
- + #define AM33XX_SR1_OPP50_MARGIN                 0
- + 
- + #define AM33XX_SR1_OPP100_CNTRL_OFFSET         0x0774
- + #define AM33XX_SR1_OPP100_EVM_ERR2VOLT_GAIN    0x8
- + #define AM33XX_SR1_OPP100_EVM_ERR_MIN_LIMIT    0xF0
- + #define AM33XX_SR1_OPP100_BB_ERR2VOLT_GAIN     0x4
- + #define AM33XX_SR1_OPP100_BB_ERR_MIN_LIMIT     0xDF
- + #define AM33XX_SR1_OPP100_ERR_MAX_LIMIT                0x2
- + #define AM33XX_SR1_OPP100_ERR_WEIGHT            0x4
- + #define AM33XX_SR1_OPP100_MARGIN                0
- + 
- + #define AM33XX_SR1_OPP120_CNTRL_OFFSET         0x0778
- + #define AM33XX_SR1_OPP120_EVM_ERR2VOLT_GAIN    0xB
- + #define AM33XX_SR1_OPP120_EVM_ERR_MIN_LIMIT    0xF4
- + #define AM33XX_SR1_OPP120_BB_ERR2VOLT_GAIN     0x5
- + #define AM33XX_SR1_OPP120_BB_ERR_MIN_LIMIT     0xE6
- + #define AM33XX_SR1_OPP120_ERR_MAX_LIMIT                0x2
- + #define AM33XX_SR1_OPP120_ERR_WEIGHT            0x4
- + #define AM33XX_SR1_OPP120_MARGIN                0
- + 
- + #define AM33XX_SR1_OPPTURBO_CNTRL_OFFSET        0x077C
- + #define AM33XX_SR1_OPPTURBO_EVM_ERR2VOLT_GAIN  0xC
- + #define AM33XX_SR1_OPPTURBO_EVM_ERR_MIN_LIMIT  0xF5
- + #define AM33XX_SR1_OPPTURBO_BB_ERR2VOLT_GAIN   0x6
- + #define AM33XX_SR1_OPPTURBO_BB_ERR_MIN_LIMIT   0xEA
- + #define AM33XX_SR1_OPPTURBO_ERR_MAX_LIMIT      0x2
- + #define AM33XX_SR1_OPPTURBO_ERR_WEIGHT          0x4
- + #define AM33XX_SR1_OPPTURBO_MARGIN              0
- + 
- + /* the voltages and frequencies should probably be defined in opp3xxx_data.c.
- +    Once SR is integrated to the mainline driver, and voltdm is working
- +    correctly in AM335x, these can be removed.  */
- + #define AM33XX_VDD_MPU_OPP50_UV                950000
- + #define AM33XX_VDD_MPU_OPP100_UV       1100000
- + #define AM33XX_VDD_MPU_OPP120_UV       1200000
- + #define AM33XX_VDD_MPU_OPPTURBO_UV     1260000
- + #define AM33XX_VDD_CORE_OPP50_UV        950000
- + #define AM33XX_VDD_CORE_OPP100_UV       1100000
- + 
- + #define AM33XX_VDD_MPU_OPP50_FREQ      275000000
- + #define AM33XX_VDD_MPU_OPP100_FREQ     500000000
- + #define AM33XX_VDD_MPU_OPP120_FREQ     600000000
- + #define AM33XX_VDD_MPU_OPPTURBO_FREQ   720000000
- + 
- + static struct am33xx_sr_opp_data sr1_opp_data[] = {
- +         {
- +                 .efuse_offs    = AM33XX_SR1_OPP50_CNTRL_OFFSET,
- +                .e2v_gain       = AM33XX_SR1_OPP50_EVM_ERR2VOLT_GAIN,
- +                .err_minlimit   = AM33XX_SR1_OPP50_EVM_ERR_MIN_LIMIT,
- +                .err_maxlimit   = AM33XX_SR1_OPP50_ERR_MAX_LIMIT,
- +                .err_weight     = AM33XX_SR1_OPP50_ERR_WEIGHT,
- +                 .margin         = AM33XX_SR1_OPP50_MARGIN,
- +                 .nominal_volt   = AM33XX_VDD_MPU_OPP50_UV,
- +                 .frequency      = AM33XX_VDD_MPU_OPP50_FREQ,
- +         },
- +         {
- +                 .efuse_offs    = AM33XX_SR1_OPP100_CNTRL_OFFSET,
- +                .e2v_gain       = AM33XX_SR1_OPP100_EVM_ERR2VOLT_GAIN,
- +                .err_minlimit   = AM33XX_SR1_OPP100_EVM_ERR_MIN_LIMIT,
- +                .err_maxlimit   = AM33XX_SR1_OPP100_ERR_MAX_LIMIT,
- +                .err_weight     = AM33XX_SR1_OPP100_ERR_WEIGHT,
- +                 .margin         = AM33XX_SR1_OPP100_MARGIN,
- +                 .nominal_volt   = AM33XX_VDD_MPU_OPP100_UV,
- +                 .frequency      = AM33XX_VDD_MPU_OPP100_FREQ,
- +         },
- +         {
- +                 .efuse_offs    = AM33XX_SR1_OPP120_CNTRL_OFFSET,
- +                .e2v_gain       = AM33XX_SR1_OPP120_EVM_ERR2VOLT_GAIN,
- +                .err_minlimit   = AM33XX_SR1_OPP120_EVM_ERR_MIN_LIMIT,
- +                .err_maxlimit   = AM33XX_SR1_OPP120_ERR_MAX_LIMIT,
- +                .err_weight     = AM33XX_SR1_OPP120_ERR_WEIGHT,
- +                 .margin         = AM33XX_SR1_OPP120_MARGIN,
- +                 .nominal_volt   = AM33XX_VDD_MPU_OPP120_UV,
- +                 .frequency      = AM33XX_VDD_MPU_OPP120_FREQ,
- +         },
- +         {
- +                 .efuse_offs    = AM33XX_SR1_OPPTURBO_CNTRL_OFFSET,
- +                .e2v_gain       = AM33XX_SR1_OPPTURBO_EVM_ERR2VOLT_GAIN,
- +                .err_minlimit   = AM33XX_SR1_OPPTURBO_EVM_ERR_MIN_LIMIT,
- +                .err_maxlimit   = AM33XX_SR1_OPPTURBO_ERR_MAX_LIMIT,
- +                .err_weight     = AM33XX_SR1_OPPTURBO_ERR_WEIGHT,
- +                 .margin         = AM33XX_SR1_OPPTURBO_MARGIN,
- +                 .nominal_volt   = AM33XX_VDD_MPU_OPPTURBO_UV,
- +                 .frequency      = AM33XX_VDD_MPU_OPPTURBO_FREQ,
- +         },
- + };
- + 
- + static struct am33xx_sr_opp_data sr0_opp_data[] = {
- +         {
- +                 .efuse_offs    = AM33XX_SR0_OPP50_CNTRL_OFFSET,
- +                .e2v_gain       = AM33XX_SR0_OPP50_EVM_ERR2VOLT_GAIN,
- +                .err_minlimit   = AM33XX_SR0_OPP50_EVM_ERR_MIN_LIMIT,
- +                .err_maxlimit   = AM33XX_SR0_OPP50_ERR_MAX_LIMIT,
- +                .err_weight     = AM33XX_SR0_OPP50_ERR_WEIGHT,
- +                 .margin         = AM33XX_SR0_OPP50_MARGIN,
- +                 .nominal_volt   = AM33XX_VDD_CORE_OPP50_UV,
- +         },
- +         {
- +                 .efuse_offs    = AM33XX_SR0_OPP100_CNTRL_OFFSET,
- +                .e2v_gain       = AM33XX_SR0_OPP100_EVM_ERR2VOLT_GAIN,
- +                .err_minlimit   = AM33XX_SR0_OPP100_EVM_ERR_MIN_LIMIT,
- +                .err_maxlimit   = AM33XX_SR0_OPP100_ERR_MAX_LIMIT,
- +                .err_weight     = AM33XX_SR0_OPP100_ERR_WEIGHT,
- +                 .margin         = AM33XX_SR0_OPP100_MARGIN,
- +                 .nominal_volt   = AM33XX_VDD_CORE_OPP100_UV,
- +         },
- + };
- + 
- + static struct am33xx_sr_sdata sr_sensor_data[] = {
- +        {
- +                 .sr_opp_data    = sr0_opp_data,
- +                 /* note that OPP50 is NOT used in Linux kernel for AM335x */
- +                 .no_of_opps     = 0x2,
- +                 .default_opp    = 0x1,
- +                .senn_mod       = 0x1,
- +                .senp_mod       = 0x1,
- +        },
- +        {
- +                .sr_opp_data    = sr1_opp_data,
- +                 /* the opp data below should be determined
- +                    dynamically during SR probe */
- +                 .no_of_opps     = 0x4,
- +                 .default_opp    = 0x3,
- +                .senn_mod       = 0x1,
- +                .senp_mod       = 0x1,
- +        },
- + };
- + 
- + static struct am33xx_sr_platform_data am33xx_sr_pdata = {
- +        .vd_name[0]             = "vdd_core",
- +         .vd_name[1]             = "vdd_mpu",
- +        .ip_type                = 2,
- +         .irq_delay              = 1000,
- +        .no_of_vds              = 2,
- +        .no_of_sens             = ARRAY_SIZE(sr_sensor_data),
- +        .vstep_size_uv          = 12500,
- +        .enable_on_init         = true,
- +        .sr_sdata               = sr_sensor_data,
- + };
- + 
- + static struct resource am33xx_sr_resources[] = {
- +        {
- +                .name   =       "smartreflex0",
- +                .start  =       AM33XX_SR0_BASE,
- +                .end    =       AM33XX_SR0_BASE + SZ_4K - 1,
- +                .flags  =       IORESOURCE_MEM,
- +        },
- +        {
- +                .name   =       "smartreflex0",
- +                .start  =       AM33XX_IRQ_SMARTREFLEX0,
- +                .end    =       AM33XX_IRQ_SMARTREFLEX0,
- +                .flags  =       IORESOURCE_IRQ,
- +        },
- +        {
- +                .name   =       "smartreflex1",
- +                .start  =       AM33XX_SR1_BASE,
- +                .end    =       AM33XX_SR1_BASE + SZ_4K - 1,
- +                .flags  =       IORESOURCE_MEM,
- +        },
- +        {
- +                .name   =       "smartreflex1",
- +                .start  =       AM33XX_IRQ_SMARTREFLEX1,
- +                .end    =       AM33XX_IRQ_SMARTREFLEX1,
- +                .flags  =       IORESOURCE_IRQ,
- +        },
- + };
- + 
- + /* VCORE for SR regulator init */
- + static struct platform_device am33xx_sr_device = {
- +        .name           = "smartreflex",
- +        .id             = -1,
- +        .num_resources  = ARRAY_SIZE(am33xx_sr_resources),
- +        .resource       = am33xx_sr_resources,
- +        .dev = {
- +                .platform_data = &am33xx_sr_pdata,
- +        },
- + };
- + 
- + void __init am33xx_sr_init(void)
- + {
- +        if (platform_device_register(&am33xx_sr_device))
- +                printk(KERN_ERR "failed to register am33xx_sr device\n");
- +        else
- +                printk(KERN_INFO "registered am33xx_sr device\n");
- + }
- + #else
- + inline void am33xx_sr_init(void) {}
- + #endif
- + 
- + /*-------------------------------------------------------------------------*/
- + 
- + static int __init omap2_init_devices(void)
- + {
- + 	/*
- + 	 * please keep these calls, and their implementations above,
- + 	 * in alphabetical order so they're easier to sort through.
- + 	 */
- + 	omap_init_mcpdm();
- + 	omap_init_dmic();
- + 	omap_init_mbox();
- + 	omap_init_mcspi();
- + 	omap_hdq_init();
- + 	omap_init_sti();
- + 	omap_init_sham();
- + 	omap_init_aes();
- + 	omap_init_vout();
- + 	am33xx_register_edma();
- + 
- + #if defined (CONFIG_SOC_OMAPAM33XX)
- + 	am335x_register_pruss_uio(&am335x_pruss_uio_pdata);
- + 	if (omap3_has_sgx())
- + 		platform_device_register(&am335x_sgx);
- + #endif
- + #ifdef CONFIG_CKB_3352_AUDIO
- + 	am335x_register_mcasp();
- + 	am33xx_init_pcm();
- + #endif
- + 	return 0;
- + }
- + arch_initcall(omap2_init_devices);
- + 
- + #define AM33XX_EMAC_MDIO_FREQ		(1000000)
- + /* Port Vlan IDs for Dual Mac Mode */
- + #define CPSW_PORT_VLAN_SLAVE_0		2
- + #define CPSW_PORT_VLAN_SLAVE_1		3
- + 
- + /* TODO : Verify the offsets */
- + static struct cpsw_slave_data am33xx_cpsw_slaves = {
- + 		.slave_reg_ofs  = 0x200,
- + 		.sliver_reg_ofs = 0xd80,
- + 		.phy_id		= "0:00",
- + 		.dual_emac_reserved_vlan = CPSW_PORT_VLAN_SLAVE_0,
- + };
- + 
- + static struct cpsw_platform_data am33xx_cpsw_pdata = {
- + 	.ss_reg_ofs		= 0x1200,
- + 	.channels		= 8,
- + 	.cpdma_reg_ofs		= 0x800,
- + 	.slaves			= 1,
- + 	.slave_data		= &am33xx_cpsw_slaves,
- + 	.ale_reg_ofs		= 0xd00,
- + 	.ale_entries		= 1024,
- + 	.host_port_reg_ofs      = 0x108,
- + 	.hw_stats_reg_ofs       = 0x900,
- + 	.cpts_reg_ofs		= 0xc00,
- + 	.cpts_clock_mult	= 0x80000000,
- + 	.cpts_clock_shift	= 29,
- + 	.bd_ram_ofs		= 0x2000,
- + 	.bd_ram_size		= SZ_8K,
- + 	.rx_descs               = 64,
- + 	.mac_control            = BIT(5), /* MIIEN */
- + 	.gigabit_en		= 1,
- + 	.host_port_num		= 0,
- + 	.no_bd_ram		= false,
- + 	.version		= CPSW_VERSION_2,
- + };
- + 
- + static struct mdio_platform_data am33xx_cpsw_mdiopdata = {
- + 	.bus_freq       = AM33XX_EMAC_MDIO_FREQ,
- + };
- + 
- + int am33xx_cpsw_init(enum am33xx_cpsw_mac_mode mode, unsigned char *mac_id, void (*save_mac_addr) (char *))
- + {
- + 	struct omap_hwmod *oh;
- + 	struct platform_device *pdev;
- + 	u32 gmii_sel;
- + 	u32 i;
- + 
- + 	/* Read MACID0 from eeprom */
- + 	for (i = 0; i < ETH_ALEN; i++)
- + 		am33xx_cpsw_slaves.mac_addr[i] = mac_id[i];
- + 	
- + 	switch (mode) {
- + 	case AM33XX_CPSW_MODE_MII:
- + 		gmii_sel = AM33XX_MII_MODE_EN;
- + 		break;
- + 	case AM33XX_CPSW_MODE_RMII:
- + 		gmii_sel = AM33XX_RMII_MODE_EN;
- + 		break;
- + 	case AM33XX_CPSW_MODE_RGMII:
- + 		gmii_sel = AM33XX_RGMII_MODE_EN;
- + 		break;
- + 	default:
- + 		return -EINVAL;
- + 	}
- + 
- + 	writel(gmii_sel, AM33XX_CTRL_REGADDR(AM33XX_CONTROL_GMII_SEL_OFFSET));
- + 
- + 	memcpy(am33xx_cpsw_pdata.mac_addr,
- + 			am33xx_cpsw_slaves.mac_addr, ETH_ALEN);
- + 
- + 	am33xx_cpsw_pdata.save_mac_addr = save_mac_addr;
- + 
- + 	oh = omap_hwmod_lookup("mdio");
- + 	if (!oh) {
- + 		pr_err("could not find cpgmac0 hwmod data\n");
- + 		return -ENODEV;
- + 	}
- + 
- + 	pdev = omap_device_build("davinci_mdio", 0, oh, &am33xx_cpsw_mdiopdata,
- + 			sizeof(am33xx_cpsw_mdiopdata), NULL, 0, 0);
- + 	if (IS_ERR(pdev))
- + 		pr_err("could not build omap_device for cpsw\n");
- + 
- + 	oh = omap_hwmod_lookup("cpgmac0");
- + 	if (!oh) {
- + 		pr_err("could not find cpgmac0 hwmod data\n");
- + 		return -ENODEV;
- + 	}
- + 
- + 	pdev = omap_device_build("cpsw", -1, oh, &am33xx_cpsw_pdata,
- + 			sizeof(am33xx_cpsw_pdata), NULL, 0, 0);
- + 	if (IS_ERR(pdev))
- + 		pr_err("could not build omap_device for cpsw\n");
- + 
- + 	return 0;
- + }
- + 
- + #define AM33XX_DCAN_NUM_MSG_OBJS		64
- + #define AM33XX_DCAN_RAMINIT_OFFSET		0x644
- + #define AM33XX_DCAN_RAMINIT_START(n)		(0x1 << n)
- + 
- + static void d_can_hw_raminit(unsigned int instance, unsigned int enable)
- + {
- + 	u32 val;
- + 
- + 	/* Read the value */
- + 	val = readl(AM33XX_CTRL_REGADDR(AM33XX_DCAN_RAMINIT_OFFSET));
- + 	if (enable) {
- + 		/* Set to "1" */
- + 		val &= ~AM33XX_DCAN_RAMINIT_START(instance);
- + 		val |= AM33XX_DCAN_RAMINIT_START(instance);
- + 		writel(val, AM33XX_CTRL_REGADDR(AM33XX_DCAN_RAMINIT_OFFSET));
- + 	} else {
- + 		/* Set to "0" */
- + 		val &= ~AM33XX_DCAN_RAMINIT_START(instance);
- + 		writel(val, AM33XX_CTRL_REGADDR(AM33XX_DCAN_RAMINIT_OFFSET));
- + 	}
- + }
- + 
- + /* dcan dev_attr */
- + static struct d_can_platform_data am33xx_dcan_info = {
- + 	.num_of_msg_objs	= AM33XX_DCAN_NUM_MSG_OBJS,
- + 	.ram_init		= d_can_hw_raminit,
- + 	.dma_support		= false,
- + };
- + 
- + void am33xx_d_can_init(unsigned int instance)
- + {
- + 	struct omap_hwmod *oh;
- + 	struct platform_device *pdev;
- + 	char oh_name[L3_MODULES_MAX_LEN];
- + 
- + 	/* Copy string name to oh_name buffer */
- + 	snprintf(oh_name, L3_MODULES_MAX_LEN, "d_can%d", instance);
- + 
- + 	oh = omap_hwmod_lookup(oh_name);
- + 	if (!oh) {
- + 		pr_err("could not find %s hwmod data\n", oh_name);
- + 		return;
- + 	}
- + 
- + 	pdev = omap_device_build("d_can", instance, oh, &am33xx_dcan_info,
- + 			sizeof(am33xx_dcan_info), NULL, 0, 0);
- + 	if (IS_ERR(pdev))
- + 		pr_err("could not build omap_device for %s\n", oh_name);
- + }
- + 
- + #if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
- + static int __init omap_init_wdt(void)
- + {
- + 	int id = -1;
- + 	struct platform_device *pdev;
- + 	struct omap_hwmod *oh;
- + 	char *oh_name = "wd_timer2";
- + 	char *dev_name = "omap_wdt";
- + 
- + 	oh = omap_hwmod_lookup(oh_name);
- + 	if (!oh) {
- + 		pr_err("Could not look up wd_timer%d hwmod\n", id);
- + 		return -EINVAL;
- + 	}
- + 
- + 	pdev = omap_device_build(dev_name, id, oh, NULL, 0, NULL, 0, 0);
- + 	WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
- + 				dev_name, oh->name);
- + 	return 0;
- + }
- + subsys_initcall(omap_init_wdt);
- + #endif
- + 
- + int __init omap_init_gpmc(struct gpmc_devices_info *pdata, int pdata_len)
- + {
- + 	struct omap_hwmod *oh;
- + 	struct platform_device *pdev;
- + 	char *name = "omap-gpmc";
- + 	char *oh_name = "gpmc";
- + 
- + 	oh = omap_hwmod_lookup(oh_name);
- + 	if (!oh) {
- + 		pr_err("Could not look up %s\n", oh_name);
- + 		return -ENODEV;
- + 	}
- + 
- + 	pdev = omap_device_build(name, -1, oh, pdata,
- + 					pdata_len, NULL, 0, 0);
- + 	if (IS_ERR(pdev)) {
- + 		WARN(1, "Can't build omap_device for %s:%s.\n",
- + 						name, oh->name);
- + 		return PTR_ERR(pdev);
- + 	}
- + 
- + 	return 0;
- + }
- + 
- + #ifdef CONFIG_CKB_EXTCN_ADC
- + #include <linux/mfd/ti_tscadc.h>
- + int __init am33xx_register_mfd_tscadc(struct mfd_tscadc_board *pdata)
- + {
- + 	int id = -1;
- + 	struct platform_device *pdev;
- + 	struct omap_hwmod *oh;
- + 	char *oh_name = "adc_tsc";
- + 	char *dev_name = "ti_tscadc";
- + 
- + 	oh = omap_hwmod_lookup(oh_name);
- + 	if (!oh) {
- + 		pr_err("Could not look up TSCADC%d hwmod\n", id);
- + 		return -ENODEV;
- + 	}
- + 
- + 	pdev = omap_device_build(dev_name, id, oh, pdata,
- + 			sizeof(struct mfd_tscadc_board), NULL, 0, 0);
- + 
- + 	WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
- + 			dev_name, oh->name);
- + 	return 0;
- + }
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/devices.h linux-3.2.1/arch/arm/mach-ckb_3352/devices.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/devices.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/devices.h	2014-05-15 13:25:13.903232838 +0900
- ***************
- *** 0 ****
- --- 1,29 ----
- + /*
- +  * arch/arm/mach-omap2/devices.h
- +  *
- +  * OMAP2 platform device setup/initialization
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; either version 2 of the License, or
- +  * (at your option) any later version.
- +  */
- + 
- + #ifndef __ARCH_ARM_MACH_OMAP_DEVICES_H
- + #define __ARCH_ARM_MACH_OMAP_DEVICES_H
- + 
- + struct isp_platform_data;
- + int omap3_init_camera(struct isp_platform_data *pdata);
- + #if defined(CONFIG_SND_AM335X_SOC_EVM) || defined(CONFIG_SND_AM335X_SOC_EVM_MODULE)
- + int __init am335x_register_mcasp(struct snd_platform_data *pdata, int ctrl_nr);
- + #endif
- + extern int __init am33xx_register_ecap(int id,
- + 		struct pwmss_platform_data *pdata);
- + extern int __init am33xx_register_ehrpwm(int id,
- + 		struct pwmss_platform_data *pdata);
- + extern int __init omap_init_elm(void);
- + 
- + void am33xx_sr_init(void);
- + void am33xx_d_can_init(unsigned int instance);
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/display.c linux-3.2.1/arch/arm/mach-ckb_3352/display.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/display.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/display.c	2014-05-15 13:25:13.903232838 +0900
- ***************
- *** 0 ****
- --- 1,261 ----
- + /*
- +  * OMAP2plus display device setup / initialization.
- +  *
- +  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- +  *	Senthilvadivu Guruswamy
- +  *	Sumit Semwal
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #include <linux/string.h>
- + #include <linux/kernel.h>
- + #include <linux/init.h>
- + #include <linux/platform_device.h>
- + #include <linux/io.h>
- + #include <linux/clk.h>
- + #include <linux/err.h>
- + #include <linux/delay.h>
- + 
- + #include <video/omapdss.h>
- + #include <plat/omap_hwmod.h>
- + #include <plat/omap_device.h>
- + #include <plat/omap-pm.h>
- + #include "common.h"
- + 
- + #include "control.h"
- + #include "display.h"
- + 
- + #define DISPC_CONTROL		0x0040
- + #define DISPC_CONTROL2		0x0238
- + #define DISPC_IRQSTATUS		0x0018
- + 
- + #define DSS_SYSCONFIG		0x10
- + #define DSS_SYSSTATUS		0x14
- + #define DSS_CONTROL		0x40
- + #define DSS_SDI_CONTROL		0x44
- + #define DSS_PLL_CONTROL		0x48
- + 
- + #define LCD_EN_MASK		(0x1 << 0)
- + #define DIGIT_EN_MASK		(0x1 << 1)
- + 
- + #define FRAMEDONE_IRQ_SHIFT	0
- + #define EVSYNC_EVEN_IRQ_SHIFT	2
- + #define EVSYNC_ODD_IRQ_SHIFT	3
- + #define FRAMEDONE2_IRQ_SHIFT	22
- + #define FRAMEDONETV_IRQ_SHIFT	24
- + 
- + /*
- +  * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
- +  *     reset before deciding that something has gone wrong
- +  */
- + #define FRAMEDONE_IRQ_TIMEOUT		100
- + 
- + static struct platform_device omap_display_device = {
- + 	.name          = "omapdss",
- + 	.id            = -1,
- + 	.dev            = {
- + 		.platform_data = NULL,
- + 	},
- + };
- + 
- + struct omap_dss_hwmod_data {
- + 	const char *oh_name;
- + 	const char *dev_name;
- + 	const int id;
- + };
- + 
- + static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initdata = {
- + 	{ "dss_hdmi", "omapdss_hdmi", -1 },
- + };
- + 
- + static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
- + {
- + 	return 0;
- + }
- + 
- + static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
- + {
- + }
- + 
- + int __init omap_display_init(struct omap_dss_board_info *board_data)
- + {
- + 	int r = 0;
- + 	struct omap_hwmod *oh;
- + 	struct platform_device *pdev;
- + 	int i, oh_count;
- + 	struct omap_display_platform_data pdata;
- + 	const struct omap_dss_hwmod_data *curr_dss_hwmod;
- + 
- + 	memset(&pdata, 0, sizeof(pdata));
- + 
- + 	curr_dss_hwmod = omap3_dss_hwmod_data;
- + 	oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
- + 	
- + 	if (board_data->dsi_enable_pads == NULL)
- + 		board_data->dsi_enable_pads = omap_dsi_enable_pads;
- + 	if (board_data->dsi_disable_pads == NULL)
- + 		board_data->dsi_disable_pads = omap_dsi_disable_pads;
- + 
- + 	pdata.board_data = board_data;
- + 	pdata.board_data->get_context_loss_count =
- + 		omap_pm_get_dev_context_loss_count;
- + 
- + 	for (i = 0; i < oh_count; i++) {
- + 		oh = omap_hwmod_lookup(curr_dss_hwmod[i].oh_name);
- + 		if (!oh) {
- + 			pr_err("Could not look up %s\n",
- + 				curr_dss_hwmod[i].oh_name);
- + 			return -ENODEV;
- + 		}
- + 
- + 		pdev = omap_device_build(curr_dss_hwmod[i].dev_name,
- + 				curr_dss_hwmod[i].id, oh, &pdata,
- + 				sizeof(struct omap_display_platform_data),
- + 				NULL, 0, 0);
- + 
- + 		if (WARN((IS_ERR(pdev)), "Could not build omap_device for %s\n",
- + 				curr_dss_hwmod[i].oh_name))
- + 			return -ENODEV;
- + 	}
- + 	omap_display_device.dev.platform_data = board_data;
- + 
- + 	r = platform_device_register(&omap_display_device);
- + 	if (r < 0)
- + 		printk(KERN_ERR "Unable to register OMAP-Display device\n");
- + 
- + 	return r;
- + }
- + 
- + static void dispc_disable_outputs(void)
- + {
- + 	u32 v, irq_mask = 0;
- + 	bool lcd_en, digit_en, lcd2_en = false;
- + 	int i;
- + 	struct omap_dss_dispc_dev_attr *da;
- + 	struct omap_hwmod *oh;
- + 
- + 	oh = omap_hwmod_lookup("dss_dispc");
- + 	if (!oh) {
- + 		WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
- + 		return;
- + 	}
- + 
- + 	if (!oh->dev_attr) {
- + 		pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
- + 		return;
- + 	}
- + 
- + 	da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
- + 
- + 	/* store value of LCDENABLE and DIGITENABLE bits */
- + 	v = omap_hwmod_read(oh, DISPC_CONTROL);
- + 	lcd_en = v & LCD_EN_MASK;
- + 	digit_en = v & DIGIT_EN_MASK;
- + 
- + 	/* store value of LCDENABLE for LCD2 */
- + 	if (da->manager_count > 2) {
- + 		v = omap_hwmod_read(oh, DISPC_CONTROL2);
- + 		lcd2_en = v & LCD_EN_MASK;
- + 	}
- + 
- + 	if (!(lcd_en | digit_en | lcd2_en))
- + 		return; /* no managers currently enabled */
- + 
- + 	/*
- + 	 * If any manager was enabled, we need to disable it before
- + 	 * DSS clocks are disabled or DISPC module is reset
- + 	 */
- + 	if (lcd_en)
- + 		irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;
- + 
- + 	if (digit_en) {
- + 		if (da->has_framedonetv_irq) {
- + 			irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
- + 		} else {
- + 			irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
- + 				1 << EVSYNC_ODD_IRQ_SHIFT;
- + 		}
- + 	}
- + 
- + 	if (lcd2_en)
- + 		irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
- + 
- + 	/*
- + 	 * clear any previous FRAMEDONE, FRAMEDONETV,
- + 	 * EVSYNC_EVEN/ODD or FRAMEDONE2 interrupts
- + 	 */
- + 	omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
- + 
- + 	/* disable LCD and TV managers */
- + 	v = omap_hwmod_read(oh, DISPC_CONTROL);
- + 	v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
- + 	omap_hwmod_write(v, oh, DISPC_CONTROL);
- + 
- + 	/* disable LCD2 manager */
- + 	if (da->manager_count > 2) {
- + 		v = omap_hwmod_read(oh, DISPC_CONTROL2);
- + 		v &= ~LCD_EN_MASK;
- + 		omap_hwmod_write(v, oh, DISPC_CONTROL2);
- + 	}
- + 
- + 	i = 0;
- + 	while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
- + 	       irq_mask) {
- + 		i++;
- + 		if (i > FRAMEDONE_IRQ_TIMEOUT) {
- + 			pr_err("didn't get FRAMEDONE1/2 or TV interrupt\n");
- + 			break;
- + 		}
- + 		mdelay(1);
- + 	}
- + }
- + 
- + #define MAX_MODULE_SOFTRESET_WAIT	10000
- + int omap_dss_reset(struct omap_hwmod *oh)
- + {
- + 	struct omap_hwmod_opt_clk *oc;
- + 	int c = 0;
- + 	int i, r;
- + 
- + 	if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
- + 		pr_err("dss_core: hwmod data doesn't contain reset data\n");
- + 		return -EINVAL;
- + 	}
- + 
- + 	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
- + 		if (oc->_clk)
- + 			clk_enable(oc->_clk);
- + 
- + 	dispc_disable_outputs();
- + 
- + 	/*
- + 	 * clear DSS_CONTROL register to switch DSS clock sources to
- + 	 * PRCM clock, if any
- + 	 */
- + 	omap_hwmod_write(0x0, oh, DSS_CONTROL);
- + 
- + 	omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
- + 				& SYSS_RESETDONE_MASK),
- + 			MAX_MODULE_SOFTRESET_WAIT, c);
- + 
- + 	if (c == MAX_MODULE_SOFTRESET_WAIT)
- + 		pr_warning("dss_core: waiting for reset to finish failed\n");
- + 	else
- + 		pr_debug("dss_core: softreset done\n");
- + 
- + 	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
- + 		if (oc->_clk)
- + 			clk_disable(oc->_clk);
- + 
- + 	r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
- + 
- + 	return r;
- + }
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/display.h linux-3.2.1/arch/arm/mach-ckb_3352/display.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/display.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/display.h	2014-05-15 13:25:13.903232838 +0900
- ***************
- *** 0 ****
- --- 1,29 ----
- + /*
- +  * display.h - OMAP2+ integration-specific DSS header
- +  *
- +  * Copyright (C) 2011 Texas Instruments, Inc.
- +  *
- +  * This program is free software; you can redistribute it and/or modify it
- +  * under the terms of the GNU General Public License version 2 as published by
- +  * the Free Software Foundation.
- +  *
- +  * This program is distributed in the hope that it will be useful, but WITHOUT
- +  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- +  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- +  * more details.
- +  *
- +  * You should have received a copy of the GNU General Public License along with
- +  * this program.  If not, see <http://www.gnu.org/licenses/>.
- +  */
- + 
- + #ifndef __ARCH_ARM_MACH_OMAP2_DISPLAY_H
- + #define __ARCH_ARM_MACH_OMAP2_DISPLAY_H
- + 
- + #include <linux/kernel.h>
- + 
- + struct omap_dss_dispc_dev_attr {
- + 	u8	manager_count;
- + 	bool	has_framedonetv_irq;
- + };
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/dma.c linux-3.2.1/arch/arm/mach-ckb_3352/dma.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/dma.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/dma.c	2014-05-15 13:25:13.903232838 +0900
- ***************
- *** 0 ****
- --- 1,283 ----
- + /*
- +  * OMAP2+ DMA driver
- +  *
- +  * Copyright (C) 2003 - 2008 Nokia Corporation
- +  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
- +  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
- +  * Graphics DMA and LCD DMA graphics tranformations
- +  * by Imre Deak <imre.deak@nokia.com>
- +  * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
- +  * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
- +  *
- +  * Copyright (C) 2009 Texas Instruments
- +  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
- +  *
- +  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- +  * Converted DMA library into platform driver
- +  *	- G, Manjunath Kondaiah <manjugk@ti.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #include <linux/err.h>
- + #include <linux/io.h>
- + #include <linux/slab.h>
- + #include <linux/module.h>
- + #include <linux/init.h>
- + #include <linux/device.h>
- + 
- + #include <plat/omap_hwmod.h>
- + #include <plat/omap_device.h>
- + #include <plat/dma.h>
- + 
- + #define OMAP2_DMA_STRIDE	0x60
- + 
- + static u32 errata;
- + static u8 dma_stride;
- + 
- + static struct omap_dma_dev_attr *d;
- + 
- + static enum omap_reg_offsets dma_common_ch_start, dma_common_ch_end;
- + 
- + static u16 reg_map[] = {
- + 	[REVISION]		= 0x00,
- + 	[GCR]			= 0x78,
- + 	[IRQSTATUS_L0]		= 0x08,
- + 	[IRQSTATUS_L1]		= 0x0c,
- + 	[IRQSTATUS_L2]		= 0x10,
- + 	[IRQSTATUS_L3]		= 0x14,
- + 	[IRQENABLE_L0]		= 0x18,
- + 	[IRQENABLE_L1]		= 0x1c,
- + 	[IRQENABLE_L2]		= 0x20,
- + 	[IRQENABLE_L3]		= 0x24,
- + 	[SYSSTATUS]		= 0x28,
- + 	[OCP_SYSCONFIG]		= 0x2c,
- + 	[CAPS_0]		= 0x64,
- + 	[CAPS_2]		= 0x6c,
- + 	[CAPS_3]		= 0x70,
- + 	[CAPS_4]		= 0x74,
- + 
- + 	/* Common register offsets */
- + 	[CCR]			= 0x80,
- + 	[CLNK_CTRL]		= 0x84,
- + 	[CICR]			= 0x88,
- + 	[CSR]			= 0x8c,
- + 	[CSDP]			= 0x90,
- + 	[CEN]			= 0x94,
- + 	[CFN]			= 0x98,
- + 	[CSEI]			= 0xa4,
- + 	[CSFI]			= 0xa8,
- + 	[CDEI]			= 0xac,
- + 	[CDFI]			= 0xb0,
- + 	[CSAC]			= 0xb4,
- + 	[CDAC]			= 0xb8,
- + 
- + 	/* Channel specific register offsets */
- + 	[CSSA]			= 0x9c,
- + 	[CDSA]			= 0xa0,
- + 	[CCEN]			= 0xbc,
- + 	[CCFN]			= 0xc0,
- + 	[COLOR]			= 0xc4,
- + 
- + 	/* OMAP4 specific registers */
- + 	[CDP]			= 0xd0,
- + 	[CNDP]			= 0xd4,
- + 	[CCDN]			= 0xd8,
- + };
- + 
- + static void __iomem *dma_base;
- + static inline void dma_write(u32 val, int reg, int lch)
- + {
- + 	u8  stride;
- + 	u32 offset;
- + 
- + 	stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
- + 	offset = reg_map[reg] + (stride * lch);
- + 	__raw_writel(val, dma_base + offset);
- + }
- + 
- + static inline u32 dma_read(int reg, int lch)
- + {
- + 	u8 stride;
- + 	u32 offset, val;
- + 
- + 	stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
- + 	offset = reg_map[reg] + (stride * lch);
- + 	val = __raw_readl(dma_base + offset);
- + 	return val;
- + }
- + 
- + static inline void omap2_disable_irq_lch(int lch)
- + {
- + 	u32 val;
- + 
- + 	val = dma_read(IRQENABLE_L0, lch);
- + 	val &= ~(1 << lch);
- + 	dma_write(val, IRQENABLE_L0, lch);
- + }
- + 
- + static void omap2_clear_dma(int lch)
- + {
- + 	int i = dma_common_ch_start;
- + 
- + 	for (; i <= dma_common_ch_end; i += 1)
- + 		dma_write(0, i, lch);
- + }
- + 
- + static void omap2_show_dma_caps(void)
- + {
- + 	u8 revision = dma_read(REVISION, 0) & 0xff;
- + 	printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
- + 				revision >> 4, revision & 0xf);
- + 	return;
- + }
- + 
- + static u32 configure_dma_errata(void)
- + {
- + 
- + 	/*
- + 	 * Errata applicable for OMAP2430ES1.0 and all omap2420
- + 	 *
- + 	 * I.
- + 	 * Erratum ID: Not Available
- + 	 * Inter Frame DMA buffering issue DMA will wrongly
- + 	 * buffer elements if packing and bursting is enabled. This might
- + 	 * result in data gets stalled in FIFO at the end of the block.
- + 	 * Workaround: DMA channels must have BUFFERING_DISABLED bit set to
- + 	 * guarantee no data will stay in the DMA FIFO in case inter frame
- + 	 * buffering occurs
- + 	 *
- + 	 * II.
- + 	 * Erratum ID: Not Available
- + 	 * DMA may hang when several channels are used in parallel
- + 	 * In the following configuration, DMA channel hanging can occur:
- + 	 * a. Channel i, hardware synchronized, is enabled
- + 	 * b. Another channel (Channel x), software synchronized, is enabled.
- + 	 * c. Channel i is disabled before end of transfer
- + 	 * d. Channel i is reenabled.
- + 	 * e. Steps 1 to 4 are repeated a certain number of times.
- + 	 * f. A third channel (Channel y), software synchronized, is enabled.
- + 	 * Channel x and Channel y may hang immediately after step 'f'.
- + 	 * Workaround:
- + 	 * For any channel used - make sure NextLCH_ID is set to the value j.
- + 	 */
- + 	if (cpu_is_omap2420() || (cpu_is_omap2430() &&
- + 				(omap_type() == OMAP2430_REV_ES1_0))) {
- + 
- + 		SET_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING);
- + 		SET_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS);
- + 	}
- + 
- + 	/*
- + 	 * Erratum ID: i378: OMAP2+: sDMA Channel is not disabled
- + 	 * after a transaction error.
- + 	 * Workaround: SW should explicitely disable the channel.
- + 	 */
- + 	SET_DMA_ERRATA(DMA_ERRATA_i378);
- + 
- + 	/*
- + 	 * Erratum ID: i541: sDMA FIFO draining does not finish
- + 	 * If sDMA channel is disabled on the fly, sDMA enters standby even
- + 	 * through FIFO Drain is still in progress
- + 	 * Workaround: Put sDMA in NoStandby more before a logical channel is
- + 	 * disabled, then put it back to SmartStandby right after the channel
- + 	 * finishes FIFO draining.
- + 	 */
- + 	SET_DMA_ERRATA(DMA_ERRATA_i541);
- + 
- + 	/*
- + 	 * Erratum ID: i88 : Special programming model needed to disable DMA
- + 	 * before end of block.
- + 	 * Workaround: software must ensure that the DMA is configured in No
- + 	 * Standby mode(DMAx_OCP_SYSCONFIG.MIDLEMODE = "01")
- + 	 */
- + 	if (omap_type() == OMAP3430_REV_ES1_0)
- + 		SET_DMA_ERRATA(DMA_ERRATA_i88);
- + 
- + 	/*
- + 	 * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
- + 	 * read before the DMA controller finished disabling the channel.
- + 	 */
- + 	SET_DMA_ERRATA(DMA_ERRATA_3_3);
- + 
- + 	/*
- + 	 * Erratum ID: Not Available
- + 	 * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
- + 	 * after secure sram context save and restore.
- + 	 * Work around: Hence we need to manually clear those IRQs to avoid
- + 	 * spurious interrupts. This affects only secure devices.
- + 	 */
- + 	if (omap_type() != OMAP2_DEVICE_TYPE_GP)
- + 		SET_DMA_ERRATA(DMA_ROMCODE_BUG);
- + 
- + 	return errata;
- + }
- + 
- + /* One time initializations */
- + static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
- + {
- + 	struct platform_device			*pdev;
- + 	struct omap_system_dma_plat_info	*p;
- + 	struct resource				*mem;
- + 	char					*name = "omap_dma_system";
- + 
- + 	dma_stride		= OMAP2_DMA_STRIDE;
- + 	dma_common_ch_start	= CSDP;
- + 	dma_common_ch_end = CCFN;
- + 
- + 	p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL);
- + 	if (!p) {
- + 		pr_err("%s: Unable to allocate pdata for %s:%s\n",
- + 			__func__, name, oh->name);
- + 		return -ENOMEM;
- + 	}
- + 
- + 	p->dma_attr		= (struct omap_dma_dev_attr *)oh->dev_attr;
- + 	p->disable_irq_lch	= omap2_disable_irq_lch;
- + 	p->show_dma_caps	= omap2_show_dma_caps;
- + 	p->clear_dma		= omap2_clear_dma;
- + 	p->dma_write		= dma_write;
- + 	p->dma_read		= dma_read;
- + 
- + 	p->clear_lch_regs	= NULL;
- + 
- + 	p->errata		= configure_dma_errata();
- + 
- + 	pdev = omap_device_build(name, 0, oh, p, sizeof(*p), NULL, 0, 0);
- + 	kfree(p);
- + 	if (IS_ERR(pdev)) {
- + 		pr_err("%s: Can't build omap_device for %s:%s.\n",
- + 			__func__, name, oh->name);
- + 		return PTR_ERR(pdev);
- + 	}
- + 
- + 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- + 	if (!mem) {
- + 		dev_err(&pdev->dev, "%s: no mem resource\n", __func__);
- + 		return -EINVAL;
- + 	}
- + 	dma_base = ioremap(mem->start, resource_size(mem));
- + 	if (!dma_base) {
- + 		dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
- + 		return -ENOMEM;
- + 	}
- + 
- + 	d = oh->dev_attr;
- + 	d->chan = kzalloc(sizeof(struct omap_dma_lch) *
- + 					(d->lch_count), GFP_KERNEL);
- + 
- + 	if (!d->chan) {
- + 		dev_err(&pdev->dev, "%s: kzalloc fail\n", __func__);
- + 		return -ENOMEM;
- + 	}
- + 	return 0;
- + }
- + 
- + static int __init omap2_system_dma_init(void)
- + {
- + 	return omap_hwmod_for_each_by_class("dma",
- + 			omap2_system_dma_init_dev, NULL);
- + }
- + arch_initcall(omap2_system_dma_init);
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/dpll3xxx.c linux-3.2.1/arch/arm/mach-ckb_3352/dpll3xxx.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/dpll3xxx.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/dpll3xxx.c	2014-05-15 13:25:13.907513273 +0900
- ***************
- *** 0 ****
- --- 1,574 ----
- + /*
- +  * OMAP3/4 - specific DPLL control functions
- +  *
- +  * Copyright (C) 2009-2010 Texas Instruments, Inc.
- +  * Copyright (C) 2009-2010 Nokia Corporation
- +  *
- +  * Written by Paul Walmsley
- +  * Testing and integration fixes by Jouni Högander
- +  *
- +  * 36xx support added by Vishwanath BS, Richard Woodruff, and Nishanth
- +  * Menon
- +  *
- +  * Parts of this code are based on code written by
- +  * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #include <linux/kernel.h>
- + #include <linux/device.h>
- + #include <linux/list.h>
- + #include <linux/errno.h>
- + #include <linux/delay.h>
- + #include <linux/clk.h>
- + #include <linux/io.h>
- + #include <linux/bitops.h>
- + #include <linux/clkdev.h>
- + 
- + #include <plat/cpu.h>
- + #include <plat/clock.h>
- + 
- + #include "clock.h"
- + #include "cm2xxx_3xxx.h"
- + 
- + /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
- + #define DPLL_AUTOIDLE_DISABLE			0x0
- + #define DPLL_AUTOIDLE_LOW_POWER_STOP		0x1
- + 
- + #define MAX_DPLL_WAIT_TRIES		1000000
- + 
- + /* Private functions */
- + 
- + /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
- + static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
- + {
- + 	const struct dpll_data *dd;
- + 	u32 v;
- + 
- + 	dd = clk->dpll_data;
- + 
- + 	v = __raw_readl(dd->control_reg);
- + 	v &= ~dd->enable_mask;
- + 	v |= clken_bits << __ffs(dd->enable_mask);
- + 	__raw_writel(v, dd->control_reg);
- + }
- + 
- + /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
- + static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
- + {
- + 	const struct dpll_data *dd;
- + 	int i = 0;
- + 	int ret = -EINVAL;
- + 
- + 	dd = clk->dpll_data;
- + 
- + 	state <<= __ffs(dd->idlest_mask);
- + 
- + 	while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
- + 	       i < MAX_DPLL_WAIT_TRIES) {
- + 		i++;
- + 		udelay(1);
- + 	}
- + 
- + 	if (i == MAX_DPLL_WAIT_TRIES) {
- + 		printk(KERN_ERR "clock: %s failed transition to '%s'\n",
- + 		       clk->name, (state) ? "locked" : "bypassed");
- + 	} else {
- + 		pr_debug("clock: %s transition to '%s' in %d loops\n",
- + 			 clk->name, (state) ? "locked" : "bypassed", i);
- + 
- + 		ret = 0;
- + 	}
- + 
- + 	return ret;
- + }
- + 
- + /*
- +  * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
- +  * @clk: pointer to a DPLL struct clk
- +  *
- +  * Instructs a non-CORE DPLL to lock.  Waits for the DPLL to report
- +  * readiness before returning.  Will save and restore the DPLL's
- +  * autoidle state across the enable, per the CDP code.  If the DPLL
- +  * locked successfully, return 0; if the DPLL did not lock in the time
- +  * allotted, or DPLL3 was passed in, return -EINVAL.
- +  */
- + static int _omap3_noncore_dpll_lock(struct clk *clk)
- + {
- + 	u8 ai;
- + 	int r;
- + 
- + 	pr_debug("clock: locking DPLL %s\n", clk->name);
- + 
- + 	ai = omap3_dpll_autoidle_read(clk);
- + 
- + 	if (ai)
- + 		omap3_dpll_deny_idle(clk);
- + 
- + 	_omap3_dpll_write_clken(clk, DPLL_LOCKED);
- + 
- + 	r = _omap3_wait_dpll_status(clk, 1);
- + 
- + 	if (ai)
- + 		omap3_dpll_allow_idle(clk);
- + 
- + 	return r;
- + }
- + 
- + /*
- +  * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
- +  * @clk: pointer to a DPLL struct clk
- +  *
- +  * Instructs a non-CORE DPLL to enter low-power bypass mode.  In
- +  * bypass mode, the DPLL's rate is set equal to its parent clock's
- +  * rate.  Waits for the DPLL to report readiness before returning.
- +  * Will save and restore the DPLL's autoidle state across the enable,
- +  * per the CDP code.  If the DPLL entered bypass mode successfully,
- +  * return 0; if the DPLL did not enter bypass in the time allotted, or
- +  * DPLL3 was passed in, or the DPLL does not support low-power bypass,
- +  * return -EINVAL.
- +  */
- + static int _omap3_noncore_dpll_bypass(struct clk *clk)
- + {
- + 	int r;
- + 	u8 ai;
- + 
- + 	if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
- + 		return -EINVAL;
- + 
- + 	pr_debug("clock: configuring DPLL %s for low-power bypass\n",
- + 		 clk->name);
- + 
- + 	ai = omap3_dpll_autoidle_read(clk);
- + 
- + 	_omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
- + 
- + 	r = _omap3_wait_dpll_status(clk, 0);
- + 
- + 	if (ai)
- + 		omap3_dpll_allow_idle(clk);
- + 
- + 	return r;
- + }
- + 
- + /*
- +  * _omap3_noncore_dpll_stop - instruct a DPLL to stop
- +  * @clk: pointer to a DPLL struct clk
- +  *
- +  * Instructs a non-CORE DPLL to enter low-power stop. Will save and
- +  * restore the DPLL's autoidle state across the stop, per the CDP
- +  * code.  If DPLL3 was passed in, or the DPLL does not support
- +  * low-power stop, return -EINVAL; otherwise, return 0.
- +  */
- + static int _omap3_noncore_dpll_stop(struct clk *clk)
- + {
- + 	u8 ai;
- + 
- + 	if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
- + 		return -EINVAL;
- + 
- + 	pr_debug("clock: stopping DPLL %s\n", clk->name);
- + 
- + 	ai = omap3_dpll_autoidle_read(clk);
- + 
- + 	_omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
- + 
- + 	if (ai)
- + 		omap3_dpll_allow_idle(clk);
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * _lookup_dco - Lookup DCO used by j-type DPLL
- +  * @clk: pointer to a DPLL struct clk
- +  * @dco: digital control oscillator selector
- +  * @m: DPLL multiplier to set
- +  * @n: DPLL divider to set
- +  *
- +  * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
- +  *
- +  * XXX This code is not needed for 3430/AM35xx; can it be optimized
- +  * out in non-multi-OMAP builds for those chips?
- +  */
- + static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n)
- + {
- + 	unsigned long fint, clkinp; /* watch out for overflow */
- + 
- + 	clkinp = clk->parent->rate;
- + 	fint = (clkinp / n) * m;
- + 
- + 	if (fint < 1000000000)
- + 		*dco = 2;
- + 	else
- + 		*dco = 4;
- + }
- + 
- + /**
- +  * _lookup_sddiv - Calculate sigma delta divider for j-type DPLL
- +  * @clk: pointer to a DPLL struct clk
- +  * @sd_div: target sigma-delta divider
- +  * @m: DPLL multiplier to set
- +  * @n: DPLL divider to set
- +  *
- +  * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
- +  *
- +  * XXX This code is not needed for 3430/AM35xx; can it be optimized
- +  * out in non-multi-OMAP builds for those chips?
- +  */
- + static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n)
- + {
- + 	unsigned long clkinp, sd; /* watch out for overflow */
- + 	int mod1, mod2;
- + 
- + 	clkinp = clk->parent->rate;
- + 
- + 	/*
- + 	 * target sigma-delta to near 250MHz
- + 	 * sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)]
- + 	 */
- + 	clkinp /= 100000; /* shift from MHz to 10*Hz for 38.4 and 19.2 */
- + 	mod1 = (clkinp * m) % (250 * n);
- + 	sd = (clkinp * m) / (250 * n);
- + 	mod2 = sd % 10;
- + 	sd /= 10;
- + 
- + 	if (mod1 || mod2)
- + 		sd++;
- + 	*sd_div = sd;
- + }
- + 
- + /*
- +  * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly
- +  * @clk: struct clk * of DPLL to set
- +  * @m: DPLL multiplier to set
- +  * @n: DPLL divider to set
- +  * @freqsel: FREQSEL value to set
- +  *
- +  * Program the DPLL with the supplied M, N values, and wait for the DPLL to
- +  * lock..  Returns -EINVAL upon error, or 0 upon success.
- +  */
- + static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
- + {
- + 	struct dpll_data *dd = clk->dpll_data;
- + 	u8 dco, sd_div;
- + 	u32 v;
- + 
- + 	/* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
- + 	_omap3_noncore_dpll_bypass(clk);
- + 
- + 	/* Set DPLL multiplier, divider */
- + 	v = __raw_readl(dd->mult_div1_reg);
- + 	v &= ~(dd->mult_mask | dd->div1_mask);
- + 	v |= m << __ffs(dd->mult_mask);
- + 	v |= (n - 1) << __ffs(dd->div1_mask);
- + 
- + 	/* Configure dco and sd_div for dplls that have these fields */
- + 	if (dd->dco_mask) {
- + 		_lookup_dco(clk, &dco, m, n);
- + 		v &= ~(dd->dco_mask);
- + 		v |= dco << __ffs(dd->dco_mask);
- + 	}
- + 	if (dd->sddiv_mask) {
- + 		_lookup_sddiv(clk, &sd_div, m, n);
- + 		v &= ~(dd->sddiv_mask);
- + 		v |= sd_div << __ffs(dd->sddiv_mask);
- + 	}
- + 
- + 	__raw_writel(v, dd->mult_div1_reg);
- + 
- + 	/* We let the clock framework set the other output dividers later */
- + 
- + 	/* REVISIT: Set ramp-up delay? */
- + 
- + 	_omap3_noncore_dpll_lock(clk);
- + 
- + 	return 0;
- + }
- + 
- + /* Public functions */
- + 
- + /**
- +  * omap3_dpll_recalc - recalculate DPLL rate
- +  * @clk: DPLL struct clk
- +  *
- +  * Recalculate and propagate the DPLL rate.
- +  */
- + unsigned long omap3_dpll_recalc(struct clk *clk)
- + {
- + 	return omap2_get_dpll_rate(clk);
- + }
- + 
- + /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
- + 
- + /**
- +  * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
- +  * @clk: pointer to a DPLL struct clk
- +  *
- +  * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
- +  * The choice of modes depends on the DPLL's programmed rate: if it is
- +  * the same as the DPLL's parent clock, it will enter bypass;
- +  * otherwise, it will enter lock.  This code will wait for the DPLL to
- +  * indicate readiness before returning, unless the DPLL takes too long
- +  * to enter the target state.  Intended to be used as the struct clk's
- +  * enable function.  If DPLL3 was passed in, or the DPLL does not
- +  * support low-power stop, or if the DPLL took too long to enter
- +  * bypass or lock, return -EINVAL; otherwise, return 0.
- +  */
- + int omap3_noncore_dpll_enable(struct clk *clk)
- + {
- + 	int r;
- + 	struct dpll_data *dd;
- + 
- + 	dd = clk->dpll_data;
- + 	if (!dd)
- + 		return -EINVAL;
- + 
- + 	if (clk->rate == dd->clk_bypass->rate) {
- + 		WARN_ON(clk->parent != dd->clk_bypass);
- + 		r = _omap3_noncore_dpll_bypass(clk);
- + 	} else {
- + 		WARN_ON(clk->parent != dd->clk_ref);
- + 		r = _omap3_noncore_dpll_lock(clk);
- + 	}
- + 	/*
- + 	 *FIXME: this is dubious - if clk->rate has changed, what about
- + 	 * propagating?
- + 	 */
- + 	if (!r)
- + 		clk->rate = (clk->recalc) ? clk->recalc(clk) :
- + 			omap2_get_dpll_rate(clk);
- + 
- + 	return r;
- + }
- + 
- + /**
- +  * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop
- +  * @clk: pointer to a DPLL struct clk
- +  *
- +  * Instructs a non-CORE DPLL to enter low-power stop.  This function is
- +  * intended for use in struct clkops.  No return value.
- +  */
- + void omap3_noncore_dpll_disable(struct clk *clk)
- + {
- + 	_omap3_noncore_dpll_stop(clk);
- + }
- + 
- + 
- + /* Non-CORE DPLL rate set code */
- + 
- + /**
- +  * omap3_noncore_dpll_set_rate - set non-core DPLL rate
- +  * @clk: struct clk * of DPLL to set
- +  * @rate: rounded target rate
- +  *
- +  * Set the DPLL CLKOUT to the target rate.  If the DPLL can enter
- +  * low-power bypass, and the target rate is the bypass source clock
- +  * rate, then configure the DPLL for bypass.  Otherwise, round the
- +  * target rate if it hasn't been done already, then program and lock
- +  * the DPLL.  Returns -EINVAL upon error, or 0 upon success.
- +  */
- + int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
- + {
- + 	struct clk *new_parent = NULL;
- + 	unsigned long hw_rate;
- + 	u16 freqsel = 0;
- + 	struct dpll_data *dd;
- + 	int ret;
- + 
- + 	if (!clk || !rate)
- + 		return -EINVAL;
- + 
- + 	dd = clk->dpll_data;
- + 	if (!dd)
- + 		return -EINVAL;
- + 
- + 	hw_rate = (clk->recalc) ? clk->recalc(clk) : omap2_get_dpll_rate(clk);
- + 	if (rate == hw_rate)
- + 		return 0;
- + 
- + 	/*
- + 	 * Ensure both the bypass and ref clocks are enabled prior to
- + 	 * doing anything; we need the bypass clock running to reprogram
- + 	 * the DPLL.
- + 	 */
- + 	omap2_clk_enable(dd->clk_bypass);
- + 	omap2_clk_enable(dd->clk_ref);
- + 
- + 	if (dd->clk_bypass->rate == rate &&
- + 	    (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
- + 		pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
- + 
- + 		ret = _omap3_noncore_dpll_bypass(clk);
- + 		if (!ret)
- + 			new_parent = dd->clk_bypass;
- + 	} else {
- + 		if (dd->last_rounded_rate != rate)
- + 			rate = clk->round_rate(clk, rate);
- + 
- + 		if (dd->last_rounded_rate == 0)
- + 			return -EINVAL;
- + 
- + 		pr_debug("clock: %s: set rate: locking rate to %lu.\n",
- + 			 clk->name, rate);
- + 
- + 		ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
- + 						 dd->last_rounded_n, freqsel);
- + 		if (!ret)
- + 			new_parent = dd->clk_ref;
- + 	}
- + 	if (!ret) {
- + 		/*
- + 		 * Switch the parent clock in the hierarchy, and make sure
- + 		 * that the new parent's usecount is correct.  Note: we
- + 		 * enable the new parent before disabling the old to avoid
- + 		 * any unnecessary hardware disable->enable transitions.
- + 		 */
- + 		if (clk->usecount) {
- + 			omap2_clk_enable(new_parent);
- + 			omap2_clk_disable(clk->parent);
- + 		}
- + 		clk_reparent(clk, new_parent);
- + 		clk->rate = rate;
- + 	}
- + 	omap2_clk_disable(dd->clk_ref);
- + 	omap2_clk_disable(dd->clk_bypass);
- + 
- + 	return 0;
- + }
- + 
- + /* DPLL autoidle read/set code */
- + 
- + /**
- +  * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
- +  * @clk: struct clk * of the DPLL to read
- +  *
- +  * Return the DPLL's autoidle bits, shifted down to bit 0.  Returns
- +  * -EINVAL if passed a null pointer or if the struct clk does not
- +  * appear to refer to a DPLL.
- +  */
- + u32 omap3_dpll_autoidle_read(struct clk *clk)
- + {
- + 	const struct dpll_data *dd;
- + 	u32 v;
- + 
- + 	if (!clk || !clk->dpll_data)
- + 		return -EINVAL;
- + 
- + 	dd = clk->dpll_data;
- + 
- + 	if (!dd->autoidle_reg)
- + 		return -EINVAL;
- + 
- + 	v = __raw_readl(dd->autoidle_reg);
- + 	v &= dd->autoidle_mask;
- + 	v >>= __ffs(dd->autoidle_mask);
- + 
- + 	return v;
- + }
- + 
- + /**
- +  * omap3_dpll_allow_idle - enable DPLL autoidle bits
- +  * @clk: struct clk * of the DPLL to operate on
- +  *
- +  * Enable DPLL automatic idle control.  This automatic idle mode
- +  * switching takes effect only when the DPLL is locked, at least on
- +  * OMAP3430.  The DPLL will enter low-power stop when its downstream
- +  * clocks are gated.  No return value.
- +  */
- + void omap3_dpll_allow_idle(struct clk *clk)
- + {
- + 	const struct dpll_data *dd;
- + 	u32 v;
- + 
- + 	if (!clk || !clk->dpll_data)
- + 		return;
- + 
- + 	dd = clk->dpll_data;
- + 
- + 	if (!dd->autoidle_reg) {
- + 		pr_debug("clock: DPLL %s: autoidle not supported\n",
- + 			clk->name);
- + 		return;
- + 	}
- + 
- + 	/*
- + 	 * REVISIT: CORE DPLL can optionally enter low-power bypass
- + 	 * by writing 0x5 instead of 0x1.  Add some mechanism to
- + 	 * optionally enter this mode.
- + 	 */
- + 	v = __raw_readl(dd->autoidle_reg);
- + 	v &= ~dd->autoidle_mask;
- + 	v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
- + 	__raw_writel(v, dd->autoidle_reg);
- + 
- + }
- + 
- + /**
- +  * omap3_dpll_deny_idle - prevent DPLL from automatically idling
- +  * @clk: struct clk * of the DPLL to operate on
- +  *
- +  * Disable DPLL automatic idle control.  No return value.
- +  */
- + void omap3_dpll_deny_idle(struct clk *clk)
- + {
- + 	const struct dpll_data *dd;
- + 	u32 v;
- + 
- + 	if (!clk || !clk->dpll_data)
- + 		return;
- + 
- + 	dd = clk->dpll_data;
- + 
- + 	if (!dd->autoidle_reg) {
- + 		pr_debug("clock: DPLL %s: autoidle not supported\n",
- + 			clk->name);
- + 		return;
- + 	}
- + 
- + 	v = __raw_readl(dd->autoidle_reg);
- + 	v &= ~dd->autoidle_mask;
- + 	v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
- + 	__raw_writel(v, dd->autoidle_reg);
- + 
- + }
- + 
- + /* Clock control for DPLL outputs */
- + 
- + /**
- +  * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
- +  * @clk: DPLL output struct clk
- +  *
- +  * Using parent clock DPLL data, look up DPLL state.  If locked, set our
- +  * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
- +  */
- + unsigned long omap3_clkoutx2_recalc(struct clk *clk)
- + {
- + 	const struct dpll_data *dd;
- + 	unsigned long rate;
- + 	u32 v;
- + 	struct clk *pclk;
- + 
- + 	/* Walk up the parents of clk, looking for a DPLL */
- + 	pclk = clk->parent;
- + 	while (pclk && !pclk->dpll_data)
- + 		pclk = pclk->parent;
- + 
- + 	/* clk does not have a DPLL as a parent? */
- + 	WARN_ON(!pclk);
- + 
- + 	dd = pclk->dpll_data;
- + 
- + 	WARN_ON(!dd->enable_mask);
- + 
- + 	v = __raw_readl(dd->control_reg) & dd->enable_mask;
- + 	v >>= __ffs(dd->enable_mask);
- + 	if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
- + 		rate = clk->parent->rate;
- + 	else
- + 		rate = clk->parent->rate * 2;
- + 	return rate;
- + }
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/gpio.c linux-3.2.1/arch/arm/mach-ckb_3352/gpio.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/gpio.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/gpio.c	2014-05-15 13:25:13.907513273 +0900
- ***************
- *** 0 ****
- --- 1,128 ----
- + /*
- +  * OMAP2+ specific gpio initialization
- +  *
- +  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- +  *
- +  * Author:
- +  *	Charulatha V <charu@ti.com>
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #include <linux/gpio.h>
- + #include <linux/err.h>
- + #include <linux/slab.h>
- + #include <linux/interrupt.h>
- + 
- + #include <plat/omap_hwmod.h>
- + #include <plat/omap_device.h>
- + 
- + static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
- + {
- + 	struct platform_device *pdev;
- + 	struct omap_gpio_platform_data *pdata;
- + 	struct omap_gpio_dev_attr *dev_attr;
- + 	char *name = "omap_gpio";
- + 	int id;
- + 
- + 	/*
- + 	 * extract the device id from name field available in the
- + 	 * hwmod database and use the same for constructing ids for
- + 	 * gpio devices.
- + 	 * CAUTION: Make sure the name in the hwmod database does
- + 	 * not change. If changed, make corresponding change here
- + 	 * or make use of static variable mechanism to handle this.
- + 	 */
- + 	sscanf(oh->name, "gpio%d", &id);
- + 
- + 	pdata = kzalloc(sizeof(struct omap_gpio_platform_data), GFP_KERNEL);
- + 	if (!pdata) {
- + 		pr_err("gpio%d: Memory allocation failed\n", id);
- + 		return -ENOMEM;
- + 	}
- + 
- + 	dev_attr = (struct omap_gpio_dev_attr *)oh->dev_attr;
- + 	pdata->bank_width = dev_attr->bank_width;
- + 	pdata->dbck_flag = dev_attr->dbck_flag;
- + 	pdata->virtual_irq_start = IH_GPIO_BASE + 32 * (id - 1);
- + 
- + 	pdata->regs = kzalloc(sizeof(struct omap_gpio_reg_offs), GFP_KERNEL);
- + 	if (!pdata) {
- + 		pr_err("gpio%d: Memory allocation failed\n", id);
- + 		return -ENOMEM;
- + 	}
- + 
- + 	switch (oh->class->rev) {
- + 	case 0:
- + 	case 1:
- + 		pdata->bank_type = METHOD_GPIO_24XX;
- + 		pdata->regs->revision = OMAP24XX_GPIO_REVISION;
- + 		pdata->regs->direction = OMAP24XX_GPIO_OE;
- + 		pdata->regs->datain = OMAP24XX_GPIO_DATAIN;
- + 		pdata->regs->dataout = OMAP24XX_GPIO_DATAOUT;
- + 		pdata->regs->set_dataout = OMAP24XX_GPIO_SETDATAOUT;
- + 		pdata->regs->clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT;
- + 		pdata->regs->irqstatus = OMAP24XX_GPIO_IRQSTATUS1;
- + 		pdata->regs->irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2;
- + 		pdata->regs->irqenable = OMAP24XX_GPIO_IRQENABLE1;
- + 		pdata->regs->set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1;
- + 		pdata->regs->clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1;
- + 		pdata->regs->debounce = OMAP24XX_GPIO_DEBOUNCE_VAL;
- + 		pdata->regs->debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN;
- + 		break;
- + 	case 2:
- + 		pdata->bank_type = METHOD_GPIO_44XX;
- + 		pdata->regs->revision = OMAP4_GPIO_REVISION;
- + 		pdata->regs->direction = OMAP4_GPIO_OE;
- + 		pdata->regs->datain = OMAP4_GPIO_DATAIN;
- + 		pdata->regs->dataout = OMAP4_GPIO_DATAOUT;
- + 		pdata->regs->set_dataout = OMAP4_GPIO_SETDATAOUT;
- + 		pdata->regs->clr_dataout = OMAP4_GPIO_CLEARDATAOUT;
- + 		pdata->regs->irqstatus = OMAP4_GPIO_IRQSTATUS0;
- + 		pdata->regs->irqstatus2 = OMAP4_GPIO_IRQSTATUS1;
- + 		pdata->regs->irqenable = OMAP4_GPIO_IRQSTATUSSET0;
- + 		pdata->regs->set_irqenable = OMAP4_GPIO_IRQSTATUSSET0;
- + 		pdata->regs->clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0;
- + 		pdata->regs->debounce = OMAP4_GPIO_DEBOUNCINGTIME;
- + 		pdata->regs->debounce_en = OMAP4_GPIO_DEBOUNCENABLE;
- + 		break;
- + 	default:
- + 		WARN(1, "Invalid gpio bank_type\n");
- + 		kfree(pdata);
- + 		return -EINVAL;
- + 	}
- + 
- + 	pdev = omap_device_build(name, id - 1, oh, pdata,
- + 				sizeof(*pdata),	NULL, 0, false);
- + 	kfree(pdata);
- + 
- + 	if (IS_ERR(pdev)) {
- + 		WARN(1, "Can't build omap_device for %s:%s.\n",
- + 					name, oh->name);
- + 		return PTR_ERR(pdev);
- + 	}
- + 
- + 	omap_device_disable_idle_on_suspend(pdev);
- + 
- + 	gpio_bank_count++;
- + 	return 0;
- + }
- + 
- + /*
- +  * gpio_init needs to be done before
- +  * machine_init functions access gpio APIs.
- +  * Hence gpio_init is a postcore_initcall.
- +  */
- + static int __init omap2_gpio_init(void)
- + {
- + 	return omap_hwmod_for_each_by_class("gpio", omap2_gpio_dev_init,
- + 						NULL);
- + }
- + postcore_initcall(omap2_gpio_init);
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/gpmc.c linux-3.2.1/arch/arm/mach-ckb_3352/gpmc.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/gpmc.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/gpmc.c	2014-05-15 13:25:13.907513273 +0900
- ***************
- *** 0 ****
- --- 1,1033 ----
- + /*
- +  * GPMC support functions
- +  *
- +  * Copyright (C) 2005-2006 Nokia Corporation
- +  *
- +  * Author: Juha Yrjola
- +  *
- +  * Copyright (C) 2009 Texas Instruments
- +  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + #undef DEBUG
- + 
- + #include <linux/platform_device.h>
- + 
- + #include <linux/irq.h>
- + #include <linux/kernel.h>
- + #include <linux/init.h>
- + #include <linux/err.h>
- + #include <linux/clk.h>
- + #include <linux/ioport.h>
- + #include <linux/spinlock.h>
- + #include <linux/io.h>
- + #include <linux/module.h>
- + #include <linux/interrupt.h>
- + #include <linux/pm_runtime.h>
- + 
- + #include <asm/mach-types.h>
- + #include <plat/gpmc.h>
- + 
- + #include <plat/sdrc.h>
- + 
- + /* GPMC register offsets */
- + #define GPMC_REVISION		0x00
- + #define GPMC_SYSCONFIG		0x10
- + #define GPMC_SYSSTATUS		0x14
- + #define GPMC_IRQSTATUS		0x18
- + #define GPMC_IRQENABLE		0x1c
- + #define GPMC_TIMEOUT_CONTROL	0x40
- + #define GPMC_ERR_ADDRESS	0x44
- + #define GPMC_ERR_TYPE		0x48
- + #define GPMC_CONFIG		0x50
- + #define GPMC_STATUS		0x54
- + #define GPMC_PREFETCH_CONFIG1	0x1e0
- + #define GPMC_PREFETCH_CONFIG2	0x1e4
- + #define GPMC_PREFETCH_CONTROL	0x1ec
- + #define GPMC_PREFETCH_STATUS	0x1f0
- + #define GPMC_ECC_CONFIG		0x1f4
- + #define GPMC_ECC_CONTROL	0x1f8
- + #define GPMC_ECC_SIZE_CONFIG	0x1fc
- + #define GPMC_ECC1_RESULT        0x200
- + #define GPMC_ECC_BCH_RESULT_0	0x240
- + 
- + #define GPMC_SYSCONF_SIDLEMODE	(2<<3)
- + #define GPMC_SYSCONF_SOFTRESET	(0<<1)
- + #define GPMC_SYSCONF_AUTOIDLE	(0)
- + 
- + #define GPMC_CS0_OFFSET		0x60
- + #define GPMC_CS_SIZE		0x30
- + 
- + #define GPMC_MEM_START		0x00000000
- + #define GPMC_MEM_END		0x3FFFFFFF
- + #define BOOT_ROM_SPACE		0x100000	/* 1MB */
- + 
- + #define GPMC_CHUNK_SHIFT	24		/* 16 MB */
- + #define GPMC_SECTION_SHIFT	28		/* 128 MB */
- + 
- + #define CS_NUM_SHIFT		24
- + #define ENABLE_PREFETCH		(0x1 << 7)
- + #define DMA_MPU_MODE		2
- + 
- + /* Structure to save gpmc cs context */
- + struct gpmc_cs_config {
- + 	u32 config1;
- + 	u32 config2;
- + 	u32 config3;
- + 	u32 config4;
- + 	u32 config5;
- + 	u32 config6;
- + 	u32 config7;
- + 	int is_valid;
- + };
- + 
- + /*
- +  * Structure to save/restore gpmc context
- +  * to support core off on OMAP3
- +  */
- + struct omap3_gpmc_regs {
- + 	u32 sysconfig;
- + 	u32 irqenable;
- + 	u32 timeout_ctrl;
- + 	u32 config;
- + 	u32 prefetch_config1;
- + 	u32 prefetch_config2;
- + 	u32 prefetch_control;
- + 	struct gpmc_cs_config cs_context[GPMC_CS_NUM];
- + };
- + 
- + 
- + #define	DRIVER_NAME	"omap-gpmc"
- + 
- + struct gpmc {
- + 	struct device	*dev;
- + 	void __iomem	*io_base;
- + 	unsigned long	phys_base;
- + 	u32		memsize;
- + 	unsigned int	cs_map;
- + 	int		ecc_used;
- + 	spinlock_t	mem_lock;
- + 	struct resource	mem_root;
- + 	struct resource	cs_mem[GPMC_CS_NUM];
- + };
- + 
- + static struct gpmc *gpmc;
- + 
- + static void gpmc_write_reg(int idx, u32 val)
- + {
- + 	writel(val, gpmc->io_base + idx);
- + }
- + 
- + static u32 gpmc_read_reg(int idx)
- + {
- + 	return readl(gpmc->io_base + idx);
- + }
- + 
- + static void gpmc_cs_write_byte(int cs, int idx, u8 val)
- + {
- + 	void __iomem *reg_addr;
- + 
- + 	reg_addr = gpmc->io_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
- + 	writeb(val, reg_addr);
- + }
- + 
- + static u8 gpmc_cs_read_byte(int cs, int idx)
- + {
- + 	void __iomem *reg_addr;
- + 
- + 	reg_addr = gpmc->io_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
- + 	return readb(reg_addr);
- + }
- + 
- + void gpmc_cs_write_reg(int cs, int idx, u32 val)
- + {
- + 	void __iomem *reg_addr;
- + 
- + 	if (!gpmc) {
- + 		pr_err("%s invoked without initializing GPMC\n", __func__);
- + 		return;
- + 	}
- + 
- + 	reg_addr = gpmc->io_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
- + 	writel(val, reg_addr);
- + }
- + 
- + u32 gpmc_cs_read_reg(int cs, int idx)
- + {
- + 	void __iomem *reg_addr;
- + 
- + 	if (!gpmc) {
- + 		pr_err("%s invoked without initializing GPMC\n", __func__);
- + 		return 0;
- + 	}
- + 
- + 	reg_addr = gpmc->io_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
- + 	return readl(reg_addr);
- + }
- + 
- + static struct clk *gpmc_l3_clk;
- + 
- + static void __devinit gpmc_clk_init(struct device *dev)
- + {
- + 	char *ck = NULL;
- + 
- + 	ck = "gpmc_fck";
- + 	
- + 	if (WARN_ON(!ck))
- + 		return;
- + 
- + 	gpmc_l3_clk = clk_get(NULL, ck);
- + 	if (IS_ERR(gpmc_l3_clk)) {
- + 		printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
- + 		BUG();
- + 	}
- + 
- + 	pm_runtime_enable(dev);
- + 	pm_runtime_get_sync(dev);
- + }
- + 
- + /* TODO: Add support for gpmc_fck to clock framework and use it */
- + unsigned long gpmc_get_fclk_period(void)
- + {
- + 	unsigned long rate = clk_get_rate(gpmc_l3_clk);
- + 
- + 	if (rate == 0) {
- + 		printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
- + 		return 0;
- + 	}
- + 
- + 	rate /= 1000;
- + 	rate = 1000000000 / rate;	/* In picoseconds */
- + 
- + 	return rate;
- + }
- + 
- + unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
- + {
- + 	unsigned long tick_ps;
- + 
- + 	/* Calculate in picosecs to yield more exact results */
- + 	tick_ps = gpmc_get_fclk_period();
- + 
- + 	return (time_ns * 1000 + tick_ps - 1) / tick_ps;
- + }
- + 
- + unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
- + {
- + 	unsigned long tick_ps;
- + 
- + 	/* Calculate in picosecs to yield more exact results */
- + 	tick_ps = gpmc_get_fclk_period();
- + 
- + 	return (time_ps + tick_ps - 1) / tick_ps;
- + }
- + 
- + unsigned int gpmc_ticks_to_ns(unsigned int ticks)
- + {
- + 	return ticks * gpmc_get_fclk_period() / 1000;
- + }
- + 
- + unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
- + {
- + 	unsigned long ticks = gpmc_ns_to_ticks(time_ns);
- + 
- + 	return ticks * gpmc_get_fclk_period() / 1000;
- + }
- + 
- + #ifdef DEBUG
- + static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
- + 			       int time, const char *name)
- + #else
- + static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
- + 			       int time)
- + #endif
- + {
- + 	u32 l;
- + 	int ticks, mask, nr_bits;
- + 
- + 	if (time == 0)
- + 		ticks = 0;
- + 	else
- + 		ticks = gpmc_ns_to_ticks(time);
- + 	nr_bits = end_bit - st_bit + 1;
- + 	if (ticks >= 1 << nr_bits) {
- + #ifdef DEBUG
- + 		printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
- + 				cs, name, time, ticks, 1 << nr_bits);
- + #endif
- + 		return -1;
- + 	}
- + 
- + 	mask = (1 << nr_bits) - 1;
- + 	l = gpmc_cs_read_reg(cs, reg);
- + #ifdef DEBUG
- + 	printk(KERN_INFO
- + 		"GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
- + 	       cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
- + 			(l >> st_bit) & mask, time);
- + #endif
- + 	l &= ~(mask << st_bit);
- + 	l |= ticks << st_bit;
- + 	gpmc_cs_write_reg(cs, reg, l);
- + 
- + 	return 0;
- + }
- + 
- + #ifdef DEBUG
- + #define GPMC_SET_ONE(reg, st, end, field) \
- + 	if (set_gpmc_timing_reg(cs, (reg), (st), (end),		\
- + 			t->field, #field) < 0)			\
- + 		return -1
- + #else
- + #define GPMC_SET_ONE(reg, st, end, field) \
- + 	if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
- + 		return -1
- + #endif
- + 
- + int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
- + {
- + 	int div;
- + 	u32 l;
- + 
- + 	l = sync_clk + (gpmc_get_fclk_period() - 1);
- + 	div = l / gpmc_get_fclk_period();
- + 	if (div > 4)
- + 		return -1;
- + 	if (div <= 0)
- + 		div = 1;
- + 
- + 	return div;
- + }
- + 
- + int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
- + {
- + 	int div;
- + 	u32 l;
- + 
- + 	div = gpmc_cs_calc_divider(cs, t->sync_clk);
- + 	if (div < 0)
- + 		return -1;
- + 
- + 	GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
- + 	GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
- + 	GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
- + 
- + 	GPMC_SET_ONE(GPMC_CS_CONFIG3,  0,  3, adv_on);
- + 	GPMC_SET_ONE(GPMC_CS_CONFIG3,  8, 12, adv_rd_off);
- + 	GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
- + 
- + 	GPMC_SET_ONE(GPMC_CS_CONFIG4,  0,  3, oe_on);
- + 	GPMC_SET_ONE(GPMC_CS_CONFIG4,  8, 12, oe_off);
- + 	GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
- + 	GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
- + 
- + 	GPMC_SET_ONE(GPMC_CS_CONFIG5,  0,  4, rd_cycle);
- + 	GPMC_SET_ONE(GPMC_CS_CONFIG5,  8, 12, wr_cycle);
- + 	GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
- + 
- + 	GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
- + 
- + 	GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
- + 	GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
- + 	
- + 	/* caller is expected to have initialized CONFIG1 to cover
- + 	 * at least sync vs async
- + 	 */
- + 	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
- + 	if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
- + #ifdef DEBUG
- + 		printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
- + 				cs, (div * gpmc_get_fclk_period()) / 1000, div);
- + #endif
- + 		l &= ~0x03;
- + 		l |= (div - 1);
- + 		gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
- + 	}
- + 
- + 	return 0;
- + }
- + 
- + static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
- + {
- + 	u32 l;
- + 	u32 mask;
- + 
- + 	mask = (1 << GPMC_SECTION_SHIFT) - size;
- + 	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
- + 	l &= ~0x3f;
- + 	l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
- + 	l &= ~(0x0f << 8);
- + 	l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
- + 	l |= GPMC_CONFIG7_CSVALID;
- + 	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
- + }
- + 
- + static void gpmc_cs_disable_mem(int cs)
- + {
- + 	u32 l;
- + 
- + 	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
- + 	l &= ~GPMC_CONFIG7_CSVALID;
- + 	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
- + }
- + 
- + static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
- + {
- + 	u32 l;
- + 	u32 mask;
- + 
- + 	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
- + 	*base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
- + 	mask = (l >> 8) & 0x0f;
- + 	*size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
- + 
- + 	*base = 0x8000000;
- + 	*size = 0x10000000;
- + }
- + 
- + static int gpmc_cs_mem_enabled(int cs)
- + {
- + 	u32 l;
- + 
- + 	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
- + 	return l & GPMC_CONFIG7_CSVALID;
- + }
- + 
- + int gpmc_cs_set_reserved(int cs, int reserved)
- + {
- + 	if (cs > GPMC_CS_NUM)
- + 		return -ENODEV;
- + 
- + 	gpmc->cs_map &= ~(1 << cs);
- + 	gpmc->cs_map |= (reserved ? 1 : 0) << cs;
- + 
- + 	return 0;
- + }
- + 
- + int gpmc_cs_reserved(int cs)
- + {
- + 	if (cs > GPMC_CS_NUM)
- + 		return -ENODEV;
- + 
- + 	return gpmc->cs_map & (1 << cs);
- + }
- + 
- + static unsigned long gpmc_mem_align(unsigned long size)
- + {
- + 	int order;
- + 
- + 	size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
- + 	order = GPMC_CHUNK_SHIFT - 1;
- + 	do {
- + 		size >>= 1;
- + 		order++;
- + 	} while (size);
- + 	size = 1 << order;
- + 	return size;
- + }
- + 
- + static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
- + {
- + 	struct resource	*res = &gpmc->cs_mem[cs];
- + 	int r;
- + 
- + 	size = gpmc_mem_align(size);
- + 	spin_lock(&gpmc->mem_lock);
- + 	res->start = base;
- + 	res->end = base + size - 1;
- + 	r = request_resource(&gpmc->mem_root, res);
- + 	spin_unlock(&gpmc->mem_lock);
- + 
- + 	return r;
- + }
- + 
- + int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
- + {
- + 	struct resource *res = &gpmc->cs_mem[cs];
- + 	int r = -1;
- + 
- + 	if (cs > GPMC_CS_NUM)
- + 		return -ENODEV;
- + 
- + 	size = gpmc_mem_align(size);
- + 	if (size > (1 << GPMC_SECTION_SHIFT))
- + 		return -ENOMEM;
- + 
- + 	spin_lock(&gpmc->mem_lock);
- + 	if (gpmc_cs_reserved(cs)) {
- + 		r = -EBUSY;
- + 		goto out;
- + 	}
- + 	if (gpmc_cs_mem_enabled(cs))
- + 		r = adjust_resource(res, res->start & ~(size - 1), size);
- + 	if (r < 0)
- + 		r = allocate_resource(&gpmc->mem_root, res, size, 0, ~0,
- + 				      size, NULL, NULL);
- + 	if (r < 0)
- + 		goto out;
- + 
- + 	gpmc_cs_enable_mem(cs, res->start, resource_size(res));
- + 	*base = res->start;
- + 	gpmc_cs_set_reserved(cs, 1);
- + out:
- + 	spin_unlock(&gpmc->mem_lock);
- + 	return r;
- + }
- + EXPORT_SYMBOL(gpmc_cs_request);
- + 
- + void gpmc_cs_free(int cs)
- + {
- + 	spin_lock(&gpmc->mem_lock);
- + 	if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) {
- + 		printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
- + 		BUG();
- + 		spin_unlock(&gpmc->mem_lock);
- + 		return;
- + 	}
- + 	gpmc_cs_disable_mem(cs);
- + 	release_resource(&gpmc->cs_mem[cs]);
- + 	gpmc_cs_set_reserved(cs, 0);
- + 	spin_unlock(&gpmc->mem_lock);
- + }
- + EXPORT_SYMBOL(gpmc_cs_free);
- + 
- + /**
- +  * gpmc_read_status - read access request to get the different gpmc status
- +  * @cmd: command type
- +  * @return status
- +  */
- + int gpmc_read_status(int cmd)
- + {
- + 	int	status = -EINVAL;
- + 	u32	regval = 0;
- + 
- + 	switch (cmd) {
- + 	case GPMC_GET_IRQ_STATUS:
- + 		status = gpmc_read_reg(GPMC_IRQSTATUS);
- + 		break;
- + 
- + 	case GPMC_PREFETCH_FIFO_CNT:
- + 		regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
- + 		status = GPMC_PREFETCH_STATUS_FIFO_CNT(regval);
- + 		break;
- + 
- + 	case GPMC_PREFETCH_COUNT:
- + 		regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
- + 		status = GPMC_PREFETCH_STATUS_COUNT(regval);
- + 		break;
- + 
- + 	case GPMC_STATUS_BUFFER:
- + 		regval = gpmc_read_reg(GPMC_STATUS);
- + 		/* 1 : buffer is available to write */
- + 		status = regval & GPMC_STATUS_BUFF_EMPTY;
- + 		break;
- + 
- + 	default:
- + 		printk(KERN_ERR "gpmc_read_status: Not supported\n");
- + 	}
- + 	return status;
- + }
- + EXPORT_SYMBOL(gpmc_read_status);
- + 
- + /**
- +  * gpmc_cs_configure - write request to configure gpmc
- +  * @cs: chip select number
- +  * @cmd: command type
- +  * @wval: value to write
- +  * @return status of the operation
- +  */
- + int gpmc_cs_configure(int cs, int cmd, int wval)
- + {
- + 	int err = 0;
- + 	u32 regval = 0;
- + 
- + 	switch (cmd) {
- + 	case GPMC_ENABLE_IRQ:
- + 		gpmc_write_reg(GPMC_IRQENABLE, wval);
- + 		break;
- + 
- + 	case GPMC_SET_IRQ_STATUS:
- + 		gpmc_write_reg(GPMC_IRQSTATUS, wval);
- + 		break;
- + 
- + 	case GPMC_CONFIG_WP:
- + 		regval = gpmc_read_reg(GPMC_CONFIG);
- + 		if (wval)
- + 			regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
- + 		else
- + 			regval |= GPMC_CONFIG_WRITEPROTECT;  /* WP is OFF */
- + 		gpmc_write_reg(GPMC_CONFIG, regval);
- + 		break;
- + 
- + 	case GPMC_CONFIG_RDY_BSY:
- + 		regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
- + 		if (wval)
- + 			regval |= WR_RD_PIN_MONITORING;
- + 		else
- + 			regval &= ~WR_RD_PIN_MONITORING;
- + 		gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
- + 		break;
- + 
- + 	case GPMC_CONFIG_DEV_SIZE:
- + 		regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
- + 		regval |= GPMC_CONFIG1_DEVICESIZE(wval);
- + 		gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
- + 		break;
- + 
- + 	case GPMC_CONFIG_DEV_TYPE:
- + 		regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
- + 		regval |= GPMC_CONFIG1_DEVICETYPE(wval);
- + 		if (wval == GPMC_DEVICETYPE_NOR)
- + 			regval |= GPMC_CONFIG1_MUXADDDATA;
- + 		gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
- + 		break;
- + 
- + 	default:
- + 		printk(KERN_ERR "gpmc_configure_cs: Not supported\n");
- + 		err = -EINVAL;
- + 	}
- + 
- + 	return err;
- + }
- + EXPORT_SYMBOL(gpmc_cs_configure);
- + 
- + /**
- +  * gpmc_nand_read - nand specific read access request
- +  * @cs: chip select number
- +  * @cmd: command type
- +  */
- + int gpmc_nand_read(int cs, int cmd)
- + {
- + 	int rval = -EINVAL;
- + 
- + 	switch (cmd) {
- + 	case GPMC_NAND_DATA:
- + 		rval = gpmc_cs_read_byte(cs, GPMC_CS_NAND_DATA);
- + 		break;
- + 
- + 	default:
- + 		printk(KERN_ERR "gpmc_read_nand_ctrl: Not supported\n");
- + 	}
- + 	return rval;
- + }
- + EXPORT_SYMBOL(gpmc_nand_read);
- + 
- + /**
- +  * gpmc_nand_write - nand specific write request
- +  * @cs: chip select number
- +  * @cmd: command type
- +  * @wval: value to write
- +  */
- + int gpmc_nand_write(int cs, int cmd, int wval)
- + {
- + 	int err = 0;
- + 
- + 	switch (cmd) {
- + 	case GPMC_NAND_COMMAND:
- + 		gpmc_cs_write_byte(cs, GPMC_CS_NAND_COMMAND, wval);
- + 		break;
- + 
- + 	case GPMC_NAND_ADDRESS:
- + 		gpmc_cs_write_byte(cs, GPMC_CS_NAND_ADDRESS, wval);
- + 		break;
- + 
- + 	case GPMC_NAND_DATA:
- + 		gpmc_cs_write_byte(cs, GPMC_CS_NAND_DATA, wval);
- + 
- + 	default:
- + 		printk(KERN_ERR "gpmc_write_nand_ctrl: Not supported\n");
- + 		err = -EINVAL;
- + 	}
- + 	return err;
- + }
- + EXPORT_SYMBOL(gpmc_nand_write);
- + 
- + 
- + 
- + /**
- +  * gpmc_prefetch_enable - configures and starts prefetch transfer
- +  * @cs: cs (chip select) number
- +  * @fifo_th: fifo threshold to be used for read/ write
- +  * @dma_mode: dma mode enable (1) or disable (0)
- +  * @u32_count: number of bytes to be transferred
- +  * @is_write: prefetch read(0) or write post(1) mode
- +  */
- + int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
- + 				unsigned int u32_count, int is_write)
- + {
- + 
- + 	if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) {
- + 		pr_err("gpmc: fifo threshold is not supported\n");
- + 		return -1;
- + 	} else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
- + 		/* Set the amount of bytes to be prefetched */
- + 		gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
- + 
- + 		/* Set dma/mpu mode, the prefetch read / post write and
- + 		 * enable the engine. Set which cs is has requested for.
- + 		 */
- + 		gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) |
- + 					PREFETCH_FIFOTHRESHOLD(fifo_th) |
- + 					ENABLE_PREFETCH |
- + 					(dma_mode << DMA_MPU_MODE) |
- + 					(0x1 & is_write)));
- + 
- + 		/*  Start the prefetch engine */
- + 		gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1);
- + 	} else {
- + 		return -EBUSY;
- + 	}
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(gpmc_prefetch_enable);
- + 
- + /**
- +  * gpmc_prefetch_reset - disables and stops the prefetch engine
- +  */
- + int gpmc_prefetch_reset(int cs)
- + {
- + 	u32 config1;
- + 
- + 	/* check if the same module/cs is trying to reset */
- + 	config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
- + 	if (((config1 >> CS_NUM_SHIFT) & 0x7) != cs)
- + 		return -EINVAL;
- + 
- + 	/* Stop the PFPW engine */
- + 	gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0);
- + 
- + 	/* Reset/disable the PFPW engine */
- + 	gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x0);
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(gpmc_prefetch_reset);
- + 
- + static void __devinit gpmc_mem_init(void)
- + {
- + 	int cs;
- + 	unsigned long boot_rom_space = 0;
- + 
- + 	/* never allocate the first page, to facilitate bug detection;
- + 	 * even if we didn't boot from ROM.
- + 	 */
- + 	boot_rom_space = BOOT_ROM_SPACE;
- + 	/* In apollon the CS0 is mapped as 0x0000 0000 */
- + 	if (machine_is_omap_apollon())
- + 		boot_rom_space = 0;
- + 	gpmc->mem_root.start = GPMC_MEM_START + boot_rom_space;
- + 	gpmc->mem_root.end = GPMC_MEM_END;
- + 
- + 	/* Reserve all regions that has been set up by bootloader */
- + 	for (cs = 0; cs < GPMC_CS_NUM; cs++) {
- + 		u32 base, size;
- + 
- + 		if (!gpmc_cs_mem_enabled(cs))
- + 			continue;
- + 		gpmc_cs_get_memconf(cs, &base, &size);
- + 		if (gpmc_cs_insert_mem(cs, base, size) < 0)
- + 			BUG();
- + 	}
- + }
- + 
- + struct device *gpmc_dev;
- + 
- + static int __devinit gpmc_probe(struct platform_device *pdev)
- + {
- + 	u32 l;
- + 	int ret = -EINVAL;
- + 	struct resource *res = NULL;
- + 	struct gpmc_devices_info *gpmc_device = pdev->dev.platform_data;
- + 	void *p;
- + 
- + 	/* XXX: This should go away with HWMOD & runtime PM adaptation */
- + 	gpmc_clk_init(&pdev->dev);
- + 
- + 	gpmc_dev = &pdev->dev;
- + 
- + 	gpmc = devm_kzalloc(&pdev->dev, sizeof(struct gpmc), GFP_KERNEL);
- + 	if (!gpmc)
- + 		return -ENOMEM;
- + 
- + 	gpmc->dev = &pdev->dev;
- + 
- + 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- + 	if (!res) {
- + 		ret = -ENOENT;
- + 		dev_err(gpmc->dev, "Failed to get resource: memory\n");
- + 		goto err_res;
- + 	}
- + 	gpmc->phys_base = res->start;
- + 	gpmc->memsize = resource_size(res);
- + 
- + 	if (request_mem_region(gpmc->phys_base,
- + 		gpmc->memsize, DRIVER_NAME) == NULL) {
- + 		ret = -ENOMEM;
- + 		dev_err(gpmc->dev, "Failed to request memory region\n");
- + 		goto err_mem;
- + 	}
- + 
- + 	gpmc->io_base = ioremap(gpmc->phys_base, gpmc->memsize);
- + 	if (!gpmc->io_base) {
- + 		ret = -ENOMEM;
- + 		dev_err(gpmc->dev, "Failed to ioremap memory\n");
- + 		goto err_remap;
- + 	}
- + 
- + 	gpmc->ecc_used = -EINVAL;
- + 	spin_lock_init(&gpmc->mem_lock);
- + 	platform_set_drvdata(pdev, gpmc);
- + 
- + 	gpmc_write_reg(GPMC_SYSCONFIG, GPMC_SYSCONF_SIDLEMODE
- + 						| GPMC_SYSCONF_SOFTRESET
- + 						| GPMC_SYSCONF_AUTOIDLE);
- + 
- + 	l = gpmc_read_reg(GPMC_REVISION);
- + 	dev_info(gpmc->dev, "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
- + 
- + 	gpmc_mem_init();
- + 
- + 	return 0;
- + 
- + err_remap:
- + 	release_mem_region(gpmc->phys_base, gpmc->memsize);
- + err_mem:
- + err_res:
- + 	devm_kfree(&pdev->dev, gpmc);
- + 	return ret;
- + }
- + 
- + static int __devexit gpmc_remove(struct platform_device *pdev)
- + {
- + 	struct gpmc *gpmc = platform_get_drvdata(pdev);
- + 
- + 	platform_set_drvdata(pdev, NULL);
- + 	iounmap(gpmc->io_base);
- + 	release_mem_region(gpmc->phys_base, gpmc->memsize);
- + 	devm_kfree(&pdev->dev, gpmc);
- + 
- + 	return 0;
- + }
- + 
- + static struct platform_driver gpmc_driver = {
- + 	.probe		= gpmc_probe,
- + 	.remove		= __devexit_p(gpmc_remove),
- + 	.driver		= {
- + 		.name	= DRIVER_NAME,
- + 		.owner	= THIS_MODULE,
- + 	},
- + };
- + 
- + module_platform_driver(gpmc_driver);
- + 
- + int gpmc_suspend(void)
- + {
- + 	omap3_gpmc_save_context();
- + 	pm_runtime_put_sync(gpmc_dev);
- + 	return 0;
- + }
- + 
- + int gpmc_resume(void)
- + {
- + 	pm_runtime_get_sync(gpmc_dev);
- + 	omap3_gpmc_restore_context();
- + 	return 0;
- + }
- + 
- + static struct omap3_gpmc_regs gpmc_context;
- + 
- + void omap3_gpmc_save_context(void)
- + {
- + 	int i;
- + 
- + 	gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
- + 	gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
- + 	gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
- + 	gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
- + 	gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
- + 	gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
- + 	gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
- + 	for (i = 0; i < GPMC_CS_NUM; i++) {
- + 		gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
- + 		if (gpmc_context.cs_context[i].is_valid) {
- + 			gpmc_context.cs_context[i].config1 =
- + 				gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
- + 			gpmc_context.cs_context[i].config2 =
- + 				gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
- + 			gpmc_context.cs_context[i].config3 =
- + 				gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
- + 			gpmc_context.cs_context[i].config4 =
- + 				gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
- + 			gpmc_context.cs_context[i].config5 =
- + 				gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
- + 			gpmc_context.cs_context[i].config6 =
- + 				gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
- + 			gpmc_context.cs_context[i].config7 =
- + 				gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
- + 		}
- + 	}
- + }
- + 
- + void omap3_gpmc_restore_context(void)
- + {
- + 	int i;
- + 
- + 	gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
- + 	gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
- + 	gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
- + 	gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
- + 	gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
- + 	gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
- + 	gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
- + 	for (i = 0; i < GPMC_CS_NUM; i++) {
- + 		if (gpmc_context.cs_context[i].is_valid) {
- + 			gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
- + 				gpmc_context.cs_context[i].config1);
- + 			gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
- + 				gpmc_context.cs_context[i].config2);
- + 			gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
- + 				gpmc_context.cs_context[i].config3);
- + 			gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
- + 				gpmc_context.cs_context[i].config4);
- + 			gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
- + 				gpmc_context.cs_context[i].config5);
- + 			gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
- + 				gpmc_context.cs_context[i].config6);
- + 			gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
- + 				gpmc_context.cs_context[i].config7);
- + 		}
- + 	}
- + }
- + 
- + /**
- +  * gpmc_enable_hwecc - enable hardware ecc functionality
- +  * @ecc_type: ecc type e.g. Hamming, BCH
- +  * @cs: chip select number
- +  * @mode: read/write mode
- +  * @dev_width: device bus width(1 for x16, 0 for x8)
- +  * @ecc_size: bytes for which ECC will be generated
- +  */
- + int gpmc_enable_hwecc(int ecc_type, int cs, int mode,
- + 			int dev_width, int ecc_size)
- + {
- + 	unsigned int bch_mod = 0, bch_wrapmode = 0, eccsize1 = 0, eccsize0 = 0;
- + 	unsigned int ecc_conf_val = 0, ecc_size_conf_val = 0;
- + 
- + 	switch (mode) {
- + 	case GPMC_ECC_READ:
- + 		if (ecc_type == OMAP_ECC_BCH4_CODE_HW) {
- + 			eccsize1 = 0xD; eccsize0 = 0x48;
- + 			bch_mod = 0;
- + 			bch_wrapmode = 0x09;
- + 		} else if (ecc_type == OMAP_ECC_BCH8_CODE_HW) {
- + 			eccsize1 = 0x2; eccsize0 = 0x1A;
- + 			bch_mod = 1;
- + 			bch_wrapmode = 0x01;
- + 		} else
- + 			eccsize1 = ((ecc_size >> 1) - 1);
- + 		break;
- + 	case GPMC_ECC_READSYN:
- + 		break;
- + 	case GPMC_ECC_WRITE:
- + 		if (ecc_type == OMAP_ECC_BCH4_CODE_HW) {
- + 			eccsize1 = 0x20; eccsize0 = 0x00;
- + 			bch_mod = 0;
- + 			bch_wrapmode = 0x06;
- + 		} else if (ecc_type == OMAP_ECC_BCH8_CODE_HW) {
- + 			eccsize1 = 0x00; eccsize0 = 0x00;
- + 			bch_mod = 1;
- + 			bch_wrapmode = 0x01;
- + 		} else
- + 			eccsize1 = ((ecc_size >> 1) - 1);
- + 		break;
- + 	default:
- + 		printk(KERN_INFO "Error: Unrecognized Mode[%d]!\n", mode);
- + 		break;
- + 	}
- + 
- + 	/* clear ecc and enable bits */
- + 	if ((ecc_type == OMAP_ECC_BCH4_CODE_HW) ||
- + 		(ecc_type == OMAP_ECC_BCH8_CODE_HW)) {
- + 		gpmc_write_reg(GPMC_ECC_CONTROL, 0x00000001);
- + 		ecc_size_conf_val = (eccsize1 << 22) | (eccsize0 << 12);
- + 		ecc_conf_val = ((0x01 << 16) | (bch_mod << 12)
- + 			| (bch_wrapmode << 8) | (dev_width << 7)
- + 			| (0x00 << 4) | (cs << 1) | (0x1));
- + 	} else {
- + 		gpmc_write_reg(GPMC_ECC_CONTROL, 0x00000101);
- + 		ecc_size_conf_val = (eccsize1 << 22) | 0x0000000F;
- + 		ecc_conf_val = (dev_width << 7) | (cs << 1) | (0x1);
- + 	}
- + 
- + 	gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, ecc_size_conf_val);
- + 	gpmc_write_reg(GPMC_ECC_CONFIG, ecc_conf_val);
- + 	gpmc_write_reg(GPMC_ECC_CONTROL, 0x00000101);
- + 	return 0;
- + }
- + EXPORT_SYMBOL(gpmc_enable_hwecc);
- + 
- + /**
- +  * gpmc_calculate_ecc - generate non-inverted ecc bytes
- +  * @ecc_type: ecc type e.g. Hamming, BCH
- +  * @cs: chip select number
- +  * @dat: data pointer over which ecc is computed
- +  * @ecc_code: ecc code buffer
- +  *
- +  * Using non-inverted ECC is considered ugly since writing a blank
- +  * page (padding) will clear the ECC bytes. This is not a problem as long
- +  * no one is trying to write data on the seemingly unused page. Reading
- +  * an erased page will produce an ECC mismatch between generated and read
- +  * ECC bytes that has to be dealt with separately.
- +  */
- + int gpmc_calculate_ecc(int ecc_type, int cs,
- + 		const u_char *dat, u_char *ecc_code)
- + {
- + 	unsigned int reg;
- + 	unsigned int val1 = 0x0, val2 = 0x0;
- + 	unsigned int val3 = 0x0, val4 = 0x0;
- + 	int i;
- + 
- + 	if ((ecc_type == OMAP_ECC_BCH4_CODE_HW) ||
- + 		(ecc_type == OMAP_ECC_BCH8_CODE_HW)) {
- + 		for (i = 0; i < 1; i++) {
- + 			/*
- + 			 * Reading HW ECC_BCH_Results
- + 			 * 0x240-0x24C, 0x250-0x25C, 0x260-0x26C, 0x270-0x27C
- + 			 */
- + 			reg =  GPMC_ECC_BCH_RESULT_0 + (0x10 * i);
- + 			val1 = gpmc_read_reg(reg);
- + 			val2 = gpmc_read_reg(reg + 4);
- + 			if (ecc_type == OMAP_ECC_BCH8_CODE_HW) {
- + 				val3 = gpmc_read_reg(reg + 8);
- + 				val4 = gpmc_read_reg(reg + 12);
- + 
- + 				*ecc_code++ = (val4 & 0xFF);
- + 				*ecc_code++ = ((val3 >> 24) & 0xFF);
- + 				*ecc_code++ = ((val3 >> 16) & 0xFF);
- + 				*ecc_code++ = ((val3 >> 8) & 0xFF);
- + 				*ecc_code++ = (val3 & 0xFF);
- + 				*ecc_code++ = ((val2 >> 24) & 0xFF);
- + 			}
- + 			*ecc_code++ = ((val2 >> 16) & 0xFF);
- + 			*ecc_code++ = ((val2 >> 8) & 0xFF);
- + 			*ecc_code++ = (val2 & 0xFF);
- + 			*ecc_code++ = ((val1 >> 24) & 0xFF);
- + 			*ecc_code++ = ((val1 >> 16) & 0xFF);
- + 			*ecc_code++ = ((val1 >> 8) & 0xFF);
- + 			*ecc_code++ = (val1 & 0xFF);
- + 		}
- + 	} else {
- + 		/* read ecc result */
- + 		val1 = gpmc_read_reg(GPMC_ECC1_RESULT);
- + 		*ecc_code++ = val1;          /* P128e, ..., P1e */
- + 		*ecc_code++ = val1 >> 16;    /* P128o, ..., P1o */
- + 		/* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
- + 		*ecc_code++ = ((val1 >> 8) & 0x0f) | ((val1 >> 20) & 0xf0);
- + 	}
- + 	return 0;
- + }
- + EXPORT_SYMBOL(gpmc_calculate_ecc);
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/hsmmc.c linux-3.2.1/arch/arm/mach-ckb_3352/hsmmc.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/hsmmc.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/hsmmc.c	2014-05-15 13:25:13.912098460 +0900
- ***************
- *** 0 ****
- --- 1,309 ----
- + /*
- +  * linux/arch/arm/mach-omap2/hsmmc.c
- +  *
- +  * Copyright (C) 2007-2008 Texas Instruments
- +  * Copyright (C) 2008 Nokia Corporation
- +  * Author: Texas Instruments
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + #include <linux/kernel.h>
- + #include <linux/slab.h>
- + #include <linux/string.h>
- + #include <linux/delay.h>
- + #include <linux/gpio.h>
- + #include <mach/hardware.h>
- + #include <plat/mmc.h>
- + #include <plat/omap-pm.h>
- + #include <plat/mux.h>
- + #include <plat/omap_device.h>
- + 
- + #include "mux.h"
- + #include "hsmmc.h"
- + #include "control.h"
- + 
- + #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
- + 
- + static u16 control_pbias_offset;
- + static u16 control_devconf1_offset;
- + 
- + #define HSMMC_NAME_LEN	9
- + 
- + #if defined(CONFIG_PM)
- + 
- + static int hsmmc_get_context_loss(struct device *dev)
- + {
- + 	return omap_pm_get_dev_context_loss_count(dev);
- + }
- + 
- + #else
- + #define hsmmc_get_context_loss NULL
- + #endif
- + 
- + static void omap_hsmmc1_before_set_reg(struct device *dev, int slot,
- + 				  int power_on, int vdd)
- + {
- + 	u32 reg, prog_io;
- + 	struct omap_mmc_platform_data *mmc = dev->platform_data;
- + 
- + 	if (mmc->slots[0].remux)
- + 		mmc->slots[0].remux(dev, slot, power_on);
- + 
- + 	/*
- + 	 * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
- + 	 * card with Vcc regulator (from twl4030 or whatever).  OMAP has both
- + 	 * 1.8V and 3.0V modes, controlled by the PBIAS register.
- + 	 *
- + 	 * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
- + 	 * is most naturally TWL VSIM; those pins also use PBIAS.
- + 	 *
- + 	 * FIXME handle VMMC1A as needed ...
- + 	 */
- + 	if (power_on) {
- + 		if (mmc->slots[0].internal_clock) {
- + 			reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
- + 			reg |= OMAP2_MMCSDIO1ADPCLKISEL;
- + 			omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
- + 		}
- + 
- + 		reg = omap_ctrl_readl(control_pbias_offset);
- + 		reg |= OMAP2_PBIASSPEEDCTRL0;
- + 		reg &= ~OMAP2_PBIASLITEPWRDNZ0;
- + 		omap_ctrl_writel(reg, control_pbias_offset);
- + 	} else {
- + 		reg = omap_ctrl_readl(control_pbias_offset);
- + 		reg &= ~OMAP2_PBIASLITEPWRDNZ0;
- + 		omap_ctrl_writel(reg, control_pbias_offset);
- + 	}
- + }
- + 
- + static void omap_hsmmc1_after_set_reg(struct device *dev, int slot,
- + 				 int power_on, int vdd)
- + {
- + 	u32 reg;
- + 
- + 	/* 100ms delay required for PBIAS configuration */
- + 	msleep(100);
- + 
- + 	if (power_on) {
- + 		reg = omap_ctrl_readl(control_pbias_offset);
- + 		reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
- + 		if ((1 << vdd) <= MMC_VDD_165_195)
- + 			reg &= ~OMAP2_PBIASLITEVMODE0;
- + 		else
- + 			reg |= OMAP2_PBIASLITEVMODE0;
- + 		omap_ctrl_writel(reg, control_pbias_offset);
- + 	} else {
- + 		reg = omap_ctrl_readl(control_pbias_offset);
- + 		reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
- + 			OMAP2_PBIASLITEVMODE0);
- + 		omap_ctrl_writel(reg, control_pbias_offset);
- + 	}
- + }
- + 
- + static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc)
- + {
- + 	u32 reg;
- + 
- + 	if (mmc->slots[0].internal_clock) {
- + 		reg = omap_ctrl_readl(control_devconf1_offset);
- + 		reg |= OMAP2_MMCSDIO2ADPCLKISEL;
- + 		omap_ctrl_writel(reg, control_devconf1_offset);
- + 	}
- + }
- + 
- + static void hsmmc23_before_set_reg(struct device *dev, int slot,
- + 				   int power_on, int vdd)
- + {
- + 	struct omap_mmc_platform_data *mmc = dev->platform_data;
- + 
- + 	if (mmc->slots[0].remux)
- + 		mmc->slots[0].remux(dev, slot, power_on);
- + 
- + 	if (power_on)
- + 		hsmmc2_select_input_clk_src(mmc);
- + }
- + 
- + 
- + static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
- + 							int vdd)
- + {
- + 	return 0;
- + }
- + 
- + static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
- + 					struct omap_mmc_platform_data *mmc)
- + {
- + 	char *hc_name;
- + 
- + 	hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
- + 	if (!hc_name) {
- + 		pr_err("Cannot allocate memory for controller slot name\n");
- + 		kfree(hc_name);
- + 		return -ENOMEM;
- + 	}
- + 
- + 	mmc->version = MMC_CTRL_VERSION_2;
- + 
- + 	if (c->name)
- + 		strncpy(hc_name, c->name, HSMMC_NAME_LEN);
- + 	else
- + 		snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
- + 								c->mmc, 1);
- + 	mmc->slots[0].name = hc_name;
- + 	mmc->nr_slots = 1;
- + 	mmc->slots[0].caps = c->caps;
- + 	mmc->slots[0].pm_caps = c->pm_caps;
- + 	mmc->slots[0].internal_clock = !c->ext_clock;
- + 	mmc->dma_mask = 0xffffffff;
- + 	mmc->reg_offset = 0;
- + 
- + 	mmc->get_context_loss_count = hsmmc_get_context_loss;
- + 
- + 	mmc->slots[0].switch_pin = c->gpio_cd;
- + 	mmc->slots[0].gpio_wp = c->gpio_wp;
- + 
- + 	mmc->slots[0].remux = c->remux;
- + 	mmc->slots[0].init_card = c->init_card;
- + 
- + 	if (c->cover_only)
- + 		mmc->slots[0].cover = 1;
- + 
- + 	if (c->nonremovable)
- + 		mmc->slots[0].nonremovable = 1;
- + 
- + 	if (c->power_saving)
- + 		mmc->slots[0].power_saving = 1;
- + 
- + 	if (c->no_off)
- + 		mmc->slots[0].no_off = 1;
- + 
- + 	if (c->no_off_init)
- + 		mmc->slots[0].no_regulator_off_init = c->no_off_init;
- + 
- + 	if (c->vcc_aux_disable_is_sleep)
- + 		mmc->slots[0].vcc_aux_disable_is_sleep = 1;
- + 
- + 	/*
- + 	 * NOTE:  MMC slots should have a Vcc regulator set up.
- + 	 * This may be from a TWL4030-family chip, another
- + 	 * controllable regulator, or a fixed supply.
- + 	 *
- + 	 * temporary HACK: ocr_mask instead of fixed supply
- + 	 */
- + 	mmc->slots[0].ocr_mask = c->ocr_mask;
- + 
- + 	mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
- + 
- + 	switch (c->mmc) {
- + 	case 1:
- + 		if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
- + 			mmc->slots[0].before_set_reg =
- + 					omap_hsmmc1_before_set_reg;
- + 			mmc->slots[0].after_set_reg =
- + 					omap_hsmmc1_after_set_reg;
- + 		}
- + 		mmc->slots[0].set_power = nop_mmc_set_power;
- + 		break;
- + 	case 2:
- + 		mmc->slots[0].set_power = nop_mmc_set_power;
- + 
- + 		if (c->ext_clock)
- + 			c->transceiver = 1;
- + 		if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
- + 			c->caps &= ~MMC_CAP_8_BIT_DATA;
- + 			c->caps |= MMC_CAP_4_BIT_DATA;
- + 		}
- + 		/* FALLTHROUGH */
- + 	case 3:
- + 		if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
- + 			/* off-chip level shifting, or none */
- + 			mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
- + 			mmc->slots[0].after_set_reg = NULL;
- + 		}
- + 		break;
- + 	case 4:
- + 	case 5:
- + 		mmc->slots[0].before_set_reg = NULL;
- + 		mmc->slots[0].after_set_reg = NULL;
- + 		break;
- + 	default:
- + 		pr_err("MMC%d configuration not supported!\n", c->mmc);
- + 		kfree(hc_name);
- + 		return -ENODEV;
- + 	}
- + 	return 0;
- + }
- + 
- + #define MAX_OMAP_MMC_HWMOD_NAME_LEN		16
- + 
- + void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo)
- + {
- + 	struct omap_hwmod *oh;
- + 	struct platform_device *pdev;
- + 	char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
- + 	struct omap_mmc_platform_data *mmc_data;
- + 	struct omap_mmc_dev_attr *mmc_dev_attr;
- + 	char *name;
- + 	int l;
- + 	int ctrl_nr;
- + 
- + 	mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
- + 	if (!mmc_data) {
- + 		pr_err("Cannot allocate memory for mmc device!\n");
- + 		goto done;
- + 	}
- + 
- + 	if (omap_hsmmc_pdata_init(hsmmcinfo, mmc_data) < 0) {
- + 		pr_err("%s fails!\n", __func__);
- + 		goto done;
- + 	}
- + 
- + 	ctrl_nr = hsmmcinfo->mmc;
- + 	name = "omap_hsmmc";
- + 
- + 	
- + 	
- + 	l = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
- + 		     "mmc%d", ctrl_nr);
- + 	
- + 	WARN(l >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
- + 	     "String buffer overflow in MMC%d device setup\n", ctrl_nr);
- + 	oh = omap_hwmod_lookup(oh_name);
- + 	if (!oh) {
- + 		pr_err("Could not look up %s\n", oh_name);
- + 		kfree(mmc_data->slots[0].name);
- + 		goto done;
- + 	}
- + 
- + 	if (oh->dev_attr != NULL) {
- + 		mmc_dev_attr = oh->dev_attr;
- + 		mmc_data->controller_flags = mmc_dev_attr->flags;
- + 	}
- + 
- + 	pdev = omap_device_build(name, ctrl_nr - 1, oh, mmc_data,
- + 		sizeof(struct omap_mmc_platform_data), NULL, 0, false);
- + 	if (IS_ERR(pdev)) {
- + 		WARN(1, "Can't build omap_device for %s:%s.\n", name, oh->name);
- + 		kfree(mmc_data->slots[0].name);
- + 		goto done;
- + 	}
- + 	/*
- + 	 * return device handle to board setup code
- + 	 * required to populate for regulator framework structure
- + 	 */
- + 	hsmmcinfo->dev = &pdev->dev;
- + 
- + done:
- + 	kfree(mmc_data);
- + }
- + 
- + void __init omap2_hsmmc_init()
- + {
- + 	control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
- + 	control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
- + }
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/hsmmc.h linux-3.2.1/arch/arm/mach-ckb_3352/hsmmc.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/hsmmc.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/hsmmc.h	2014-05-15 13:25:13.912098460 +0900
- ***************
- *** 0 ****
- --- 1,49 ----
- + /*
- +  * MMC definitions for OMAP2
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + struct mmc_card;
- + 
- + struct omap2_hsmmc_info {
- + 	u8	mmc;		/* controller 1/2/3 */
- + 	u32	caps;		/* 4/8 wires and any additional host
- + 				 * capabilities OR'd (ref. linux/mmc/host.h) */
- + 	u32	pm_caps;	/* PM capabilities */
- + 	bool	transceiver;	/* MMC-2 option */
- + 	bool	ext_clock;	/* use external pin for input clock */
- + 	bool	cover_only;	/* No card detect - just cover switch */
- + 	bool	nonremovable;	/* Nonremovable e.g. eMMC */
- + 	bool	power_saving;	/* Try to sleep or power off when possible */
- + 	bool	no_off;		/* power_saving and power is not to go off */
- + 	bool	no_off_init;	/* no power off when not in MMC sleep state */
- + 	bool	vcc_aux_disable_is_sleep; /* Regulator off remapped to sleep */
- + 	int	gpio_cd;	/* or -EINVAL */
- + 	int	gpio_wp;	/* or -EINVAL */
- + 	char	*name;		/* or NULL for default */
- + 	struct device *dev;	/* returned: pointer to mmc adapter */
- + 	int	ocr_mask;	/* temporary HACK */
- + 	/* Remux (pad configuration) when powering on/off */
- + 	void (*remux)(struct device *dev, int slot, int power_on);
- + 	/* init some special card */
- + 	void (*init_card)(struct mmc_card *card);
- + };
- + 
- + #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
- + 
- + void omap2_hsmmc_init(void);
- + void omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo);
- + 
- + #else
- + 
- + static inline void omap2_hsmmc_init(void)
- + {
- + }
- + 
- + void omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo)
- + {
- + }
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/hwspinlock.c linux-3.2.1/arch/arm/mach-ckb_3352/hwspinlock.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/hwspinlock.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/hwspinlock.c	2014-05-15 13:25:13.912098460 +0900
- ***************
- *** 0 ****
- --- 1,60 ----
- + /*
- +  * OMAP hardware spinlock device initialization
- +  *
- +  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
- +  *
- +  * Contact: Simon Que <sque@ti.com>
- +  *          Hari Kanigeri <h-kanigeri2@ti.com>
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License
- +  * version 2 as published by the Free Software Foundation.
- +  *
- +  * This program is distributed in the hope that it will be useful, but
- +  * WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- +  * General Public License for more details.
- +  */
- + 
- + #include <linux/kernel.h>
- + #include <linux/init.h>
- + #include <linux/err.h>
- + #include <linux/hwspinlock.h>
- + 
- + #include <plat/omap_hwmod.h>
- + #include <plat/omap_device.h>
- + 
- + static struct hwspinlock_pdata omap_hwspinlock_pdata __initdata = {
- + 	.base_id = 0,
- + };
- + 
- + int __init hwspinlocks_init(void)
- + {
- + 	int retval = 0;
- + 	struct omap_hwmod *oh;
- + 	struct platform_device *pdev;
- + 	const char *oh_name = "spinlock";
- + 	const char *dev_name = "omap_hwspinlock";
- + 
- + 	/*
- + 	 * Hwmod lookup will fail in case our platform doesn't support the
- + 	 * hardware spinlock module, so it is safe to run this initcall
- + 	 * on all omaps
- + 	 */
- + 	oh = omap_hwmod_lookup(oh_name);
- + 	if (oh == NULL)
- + 		return -EINVAL;
- + 
- + 	pdev = omap_device_build(dev_name, 0, oh, &omap_hwspinlock_pdata,
- + 				sizeof(struct hwspinlock_pdata),
- + 				NULL, 0, false);
- + 	if (IS_ERR(pdev)) {
- + 		pr_err("Can't build omap_device for %s:%s\n", dev_name,
- + 								oh_name);
- + 		retval = PTR_ERR(pdev);
- + 	}
- + 
- + 	return retval;
- + }
- + /* early board code might need to reserve specific hwspinlock instances */
- + postcore_initcall(hwspinlocks_init);
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/i2c.c linux-3.2.1/arch/arm/mach-ckb_3352/i2c.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/i2c.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/i2c.c	2014-05-15 13:25:13.915089671 +0900
- ***************
- *** 0 ****
- --- 1,107 ----
- + /*
- +  * Helper module for board specific I2C bus registration
- +  *
- +  * Copyright (C) 2009 Nokia Corporation.
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License
- +  * version 2 as published by the Free Software Foundation.
- +  *
- +  * This program is distributed in the hope that it will be useful, but
- +  * WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- +  * General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- +  * 02110-1301 USA
- +  *
- +  */
- + 
- + #include <plat/cpu.h>
- + #include <plat/i2c.h>
- + #include "common.h"
- + #include <plat/omap_hwmod.h>
- + 
- + #include "mux.h"
- + 
- + /* In register I2C_CON, Bit 15 is the I2C enable bit */
- + #define I2C_EN					BIT(15)
- + #define OMAP2_I2C_CON_OFFSET			0x24
- + #define OMAP4_I2C_CON_OFFSET			0xA4
- + 
- + /* Maximum microseconds to wait for OMAP module to softreset */
- + #define MAX_MODULE_SOFTRESET_WAIT	10000
- + 
- + void __init omap2_i2c_mux_pins(int bus_id)
- + {
- + 	char mux_name[sizeof("i2c2_scl.i2c2_scl")];
- + 
- + 	/* First I2C bus is not muxable */
- + 	if (bus_id == 1)
- + 		return;
- + 
- + 	sprintf(mux_name, "i2c%i_scl.i2c%i_scl", bus_id, bus_id);
- + 	omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
- + 	sprintf(mux_name, "i2c%i_sda.i2c%i_sda", bus_id, bus_id);
- + 	omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
- + }
- + 
- + /**
- +  * omap_i2c_reset - reset the omap i2c module.
- +  * @oh: struct omap_hwmod *
- +  *
- +  * The i2c moudle in omap2, omap3 had a special sequence to reset. The
- +  * sequence is:
- +  * - Disable the I2C.
- +  * - Write to SOFTRESET bit.
- +  * - Enable the I2C.
- +  * - Poll on the RESETDONE bit.
- +  * The sequence is implemented in below function. This is called for 2420,
- +  * 2430 and omap3.
- +  */
- + int omap_i2c_reset(struct omap_hwmod *oh)
- + {
- + 	u32 v;
- + 	u16 i2c_con;
- + 	int c = 0;
- + 
- + 	if (oh->class->rev == OMAP_I2C_IP_VERSION_2) {
- + 		i2c_con = OMAP4_I2C_CON_OFFSET;
- + 	} else if (oh->class->rev == OMAP_I2C_IP_VERSION_1) {
- + 		i2c_con = OMAP2_I2C_CON_OFFSET;
- + 	} else {
- + 		WARN(1, "Cannot reset I2C block %s: unsupported revision\n",
- + 		     oh->name);
- + 		return -EINVAL;
- + 	}
- + 
- + 	/* Disable I2C */
- + 	v = omap_hwmod_read(oh, i2c_con);
- + 	v &= ~I2C_EN;
- + 	omap_hwmod_write(v, oh, i2c_con);
- + 
- + 	/* Write to the SOFTRESET bit */
- + 	omap_hwmod_softreset(oh);
- + 
- + 	/* Enable I2C */
- + 	v = omap_hwmod_read(oh, i2c_con);
- + 	v |= I2C_EN;
- + 	omap_hwmod_write(v, oh, i2c_con);
- + 
- + 	/* Poll on RESETDONE bit */
- + 	omap_test_timeout((omap_hwmod_read(oh,
- + 				oh->class->sysc->syss_offs)
- + 				& SYSS_RESETDONE_MASK),
- + 				MAX_MODULE_SOFTRESET_WAIT, c);
- + 
- + 	if (c == MAX_MODULE_SOFTRESET_WAIT)
- + 		pr_warning("%s: %s: softreset failed (waited %d usec)\n",
- + 			__func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
- + 	else
- + 		pr_debug("%s: %s: softreset in %d usec\n", __func__,
- + 			oh->name, c);
- + 
- + 	return 0;
- + }
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/asp.h linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/asp.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/asp.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/asp.h	2014-05-15 13:25:13.915089671 +0900
- ***************
- *** 0 ****
- --- 1,139 ----
- + /*
- +  * <asm/hardware/asp.h> - DaVinci Audio Serial Port support
- +  */
- + #ifndef __ASM_HARDWARE_MCASP_H
- + #define __ASM_HARDWARE_MCASP_H
- + 
- + #include <mach/irqs.h>
- + #include <mach/edma.h>
- + 
- + /* Bases of dm644x and dm355 register banks */
- + #define DAVINCI_ASP0_BASE	0x01E02000
- + #define DAVINCI_ASP1_BASE	0x01E04000
- + 
- + /* Bases of dm365 register banks */
- + #define DAVINCI_DM365_ASP0_BASE	0x01D02000
- + 
- + /* Bases of dm646x register banks */
- + #define	DAVINCI_DM646X_MCASP0_REG_BASE		0x01D01000
- + #define DAVINCI_DM646X_MCASP1_REG_BASE		0x01D01800
- + 
- + /* Bases of da850/da830 McASP0  register banks */
- + #define DAVINCI_DA8XX_MCASP0_REG_BASE	0x01D00000
- + 
- + /* Bases of da830 McASP1 register banks */
- + #define DAVINCI_DA830_MCASP1_REG_BASE	0x01D04000
- + 
- + /* EDMA channels of dm644x and dm355 */
- + #define DAVINCI_DMA_ASP0_TX	2
- + #define DAVINCI_DMA_ASP0_RX	3
- + #define DAVINCI_DMA_ASP1_TX	8
- + #define DAVINCI_DMA_ASP1_RX	9
- + 
- + /* EDMA channels of dm646x */
- + #define	DAVINCI_DM646X_DMA_MCASP0_AXEVT0	6
- + #define	DAVINCI_DM646X_DMA_MCASP0_AREVT0	9
- + #define	DAVINCI_DM646X_DMA_MCASP1_AXEVT1	12
- + 
- + /* EDMA channels of da850/da830 McASP0 */
- + #define	DAVINCI_DA8XX_DMA_MCASP0_AREVT	0
- + #define	DAVINCI_DA8XX_DMA_MCASP0_AXEVT	1
- + 
- + /* EDMA channels of da830 McASP1 */
- + #define	DAVINCI_DA830_DMA_MCASP1_AREVT	2
- + #define	DAVINCI_DA830_DMA_MCASP1_AXEVT	3
- + 
- + /* Interrupts */
- + #define DAVINCI_ASP0_RX_INT	IRQ_MBRINT
- + #define DAVINCI_ASP0_TX_INT	IRQ_MBXINT
- + #define DAVINCI_ASP1_RX_INT	IRQ_MBRINT
- + #define DAVINCI_ASP1_TX_INT	IRQ_MBXINT
- + 
- + struct snd_platform_data {
- + 	u32 tx_dma_offset;
- + 	u32 rx_dma_offset;
- + 	enum dma_event_q asp_chan_q;	/* event queue number for ASP channel */
- + 	enum dma_event_q ram_chan_q;	/* event queue number for RAM channel */
- + 	unsigned int codec_fmt;
- + 	/*
- + 	 * Allowing this is more efficient and eliminates left and right swaps
- + 	 * caused by underruns, but will swap the left and right channels
- + 	 * when compared to previous behavior.
- + 	 */
- + 	unsigned enable_channel_combine:1;
- + 	unsigned sram_size_playback;
- + 	unsigned sram_size_capture;
- + 
- + 	/*
- + 	 * If McBSP peripheral gets the clock from an external pin,
- + 	 * there are three chooses, that are MCBSP_CLKX, MCBSP_CLKR
- + 	 * and MCBSP_CLKS.
- + 	 * Depending on different hardware connections it is possible
- + 	 * to use this setting to change the behaviour of McBSP
- + 	 * driver. The dm365_clk_input_pin enum is available for dm365
- + 	 */
- + 	int clk_input_pin;
- + 
- + 	/*
- + 	 * This flag works when both clock and FS are outputs for the cpu
- + 	 * and makes clock more accurate (FS is not symmetrical and the
- + 	 * clock is very fast.
- + 	 * The clock becoming faster is named
- + 	 * i2s continuous serial clock (I2S_SCK) and it is an externally
- + 	 * visible bit clock.
- + 	 *
- + 	 * first line : WordSelect
- + 	 * second line : ContinuousSerialClock
- + 	 * third line: SerialData
- + 	 *
- + 	 * SYMMETRICAL APPROACH:
- + 	 *   _______________________          LEFT
- + 	 * _|         RIGHT         |______________________|
- + 	 *     _   _         _   _   _   _         _   _
- + 	 *   _| |_| |_ x16 _| |_| |_| |_| |_ x16 _| |_| |_
- + 	 *     _   _         _   _   _   _         _   _
- + 	 *   _/ \_/ \_ ... _/ \_/ \_/ \_/ \_ ... _/ \_/ \_
- + 	 *    \_/ \_/       \_/ \_/ \_/ \_/       \_/ \_/
- + 	 *
- + 	 * ACCURATE CLOCK APPROACH:
- + 	 *   ______________          LEFT
- + 	 * _|     RIGHT    |_______________________________|
- + 	 *     _         _   _         _   _   _   _   _   _
- + 	 *   _| |_ x16 _| |_| |_ x16 _| |_| |_| |_| |_| |_| |
- + 	 *     _         _   _          _      dummy cycles
- + 	 *   _/ \_ ... _/ \_/ \_  ... _/ \__________________
- + 	 *    \_/       \_/ \_/        \_/
- + 	 *
- + 	 */
- + 	bool i2s_accurate_sck;
- + 
- + 	/* McASP specific fields */
- + 	int tdm_slots;
- + 	u8 op_mode;
- + 	u8 num_serializer;
- + 	u8 *serial_dir;
- + 	u8 version;
- + 	u8 txnumevt;
- + 	u8 rxnumevt;
- + };
- + 
- + enum {
- + 	MCASP_VERSION_1 = 0,	/* DM646x */
- + 	MCASP_VERSION_2,	/* DA8xx/OMAPL1x */
- + 	MCASP_VERSION_3,	/* AM33xx */
- + };
- + 
- + enum dm365_clk_input_pin {
- + 	MCBSP_CLKR = 0,		/* DM365 */
- + 	MCBSP_CLKS,
- + };
- + 
- + #define INACTIVE_MODE	0
- + #define TX_MODE		1
- + #define RX_MODE		2
- + 
- + #define DAVINCI_MCASP_IIS_MODE	0
- + #define DAVINCI_MCASP_DIT_MODE	1
- + 
- + 
- + #endif /* __ASM_HARDWARE_MCASP_H */
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/barriers.h linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/barriers.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/barriers.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/barriers.h	2014-05-15 13:25:13.915089671 +0900
- ***************
- *** 0 ****
- --- 1,31 ----
- + /*
- +  * OMAP memory barrier header.
- +  *
- +  * Copyright (C) 2011 Texas Instruments, Inc.
- +  *  Santosh Shilimkar <santosh.shilimkar@ti.com>
- +  *  Richard Woodruff <r-woodruff2@ti.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- +  */
- + 
- + #ifndef __MACH_BARRIERS_H
- + #define __MACH_BARRIERS_H
- + 
- + extern void omap_bus_sync(void);
- + 
- + #define rmb()		dsb()
- + #define wmb()		do { dsb(); outer_sync(); omap_bus_sync(); } while (0)
- + #define mb()		wmb()
- + 
- + #endif	/* __MACH_BARRIERS_H */
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/ckb_3352.h linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/ckb_3352.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/ckb_3352.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/ckb_3352.h	2014-05-15 13:25:13.915089671 +0900
- ***************
- *** 0 ****
- --- 1,31 ----
- + /*
- +  * Header containing CKB info
- +  *
- +  * Copyright (C) 2013 Computex Co.Ltd.
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; version 2 of the License.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- +  *
- +  */
- +  
- + #ifndef __ASM_MACH_CKB_3352_H
- + #define __ASM_MACH_CKB_3352_H
- + 
- + typedef struct {
- + 	unsigned char id;
- + 	unsigned char mac[ETH_ALEN];
- + }ckb_3352_eeprom_mac_address;
- + 
- + #define CKB_3352_MAC_HEADER		0x5A
- + 
- + #endif  /*  __ASM_MACH_CKB_3352_H */
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/ckb_3352_mem.h linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/ckb_3352_mem.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/ckb_3352_mem.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/ckb_3352_mem.h	2014-05-15 13:25:13.915089671 +0900
- ***************
- *** 0 ****
- --- 1,28 ----
- + /*
- +  * Header containing CKB memory info
- +  *
- +  * Copyright (C) 2013 Computex Co.Ltd.
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; version 2 of the License.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- +  *
- +  */
- +  
- + #ifndef __ASM_MACH_CKB_3352_MEM_H
- + #define __ASM_MACH_CKB_3352_MEM_H
- + 
- + extern unsigned long FB_DATA_ADDRESS;
- + extern unsigned long FB_DATA_VADDRESS;
- + extern unsigned long FB_MAP_SIZE;
- + 
- + #endif  /*  __ASM_MACH_CKB_3352_MEM_H */
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/debug-macro.S linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/debug-macro.S
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/debug-macro.S	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/debug-macro.S	2014-05-15 13:25:13.918640389 +0900
- ***************
- *** 0 ****
- --- 1,169 ----
- + /* arch/arm/mach-omap2/include/mach/debug-macro.S
- +  *
- +  * Debugging macro include header
- +  *
- +  *  Copyright (C) 1994-1999 Russell King
- +  *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  *
- + */
- + 
- + #include <linux/serial_reg.h>
- + 
- + #include <plat/serial.h>
- + 
- + #define UART_OFFSET(addr)	((addr) & 0x00ffffff)
- + 
- + 		.pushsection .data
- + omap_uart_phys:	.word	0
- + omap_uart_virt:	.word	0
- + omap_uart_lsr:	.word	0
- + 		.popsection
- + 
- + 		/*
- + 		 * Note that this code won't work if the bootloader passes
- + 		 * a wrong machine ID number in r1. To debug, just hardcode
- + 		 * the desired UART phys and virt addresses temporarily into
- + 		 * the omap_uart_phys and omap_uart_virt above.
- + 		 */
- + 		.macro	addruart, rp, rv, tmp
- + 
- + 		/* Use omap_uart_phys/virt if already configured */
- + 10:		adr	\rp, 99f		@ get effective addr of 99f
- + 		ldr	\rv, [\rp]		@ get absolute addr of 99f
- + 		sub	\rv, \rv, \rp		@ offset between the two
- + 		ldr	\rp, [\rp, #4]		@ abs addr of omap_uart_phys
- + 		sub	\tmp, \rp, \rv		@ make it effective
- + 		ldr	\rp, [\tmp, #0]		@ omap_uart_phys
- + 		ldr	\rv, [\tmp, #4]		@ omap_uart_virt
- + 		cmp	\rp, #0			@ is port configured?
- + 		cmpne	\rv, #0
- + 		bne	100f			@ already configured
- + 
- + 		/* Check the debug UART configuration set in uncompress.h */
- + 		mov	\rp, pc
- + 		ldr	\rv, =OMAP_UART_INFO_OFS
- + 		and	\rp, \rp, #0xff000000
- + 		ldr	\rp, [\rp, \rv]
- + 
- + 		/* Select the UART to use based on the UART1 scratchpad value */
- + 		cmp	\rp, #0			@ no port configured?
- + 		beq	21f			@ if none, try to use UART1
- + 		cmp	\rp, #OMAP2UART1	@ OMAP2/3/4UART1
- + 		beq	21f			@ configure OMAP2/3/4UART1
- + 		cmp	\rp, #OMAP2UART2	@ OMAP2/3/4UART2
- + 		beq	22f			@ configure OMAP2/3/4UART2
- + 		cmp	\rp, #OMAP2UART3	@ only on 24xx
- + 		beq	23f			@ configure OMAP2UART3
- + 		cmp	\rp, #OMAP3UART3	@ only on 34xx
- + 		beq	33f			@ configure OMAP3UART3
- + 		cmp	\rp, #OMAP4UART3	@ only on 44xx
- + 		beq	43f			@ configure OMAP4UART3
- + 		cmp	\rp, #OMAP3UART4	@ only on 36xx
- + 		beq	34f			@ configure OMAP3UART4
- + 		cmp	\rp, #OMAP4UART4	@ only on 44xx
- + 		beq	44f			@ configure OMAP4UART4
- + 		cmp	\rp, #TI81XXUART1	@ ti81Xx UART offsets different
- + 		beq	81f			@ configure UART1
- + 		cmp	\rp, #TI81XXUART2	@ ti81Xx UART offsets different
- + 		beq	82f			@ configure UART2
- + 		cmp	\rp, #TI81XXUART3	@ ti81Xx UART offsets different
- + 		beq	83f			@ configure UART3
- + 		cmp	\rp, #AM33XXUART1	@ AM33XX UART offsets different
- + 		beq	84f			@ configure UART1
- + 		cmp	\rp, #AM33XXUART4	@ AM33XX UART offsets different
- + 		beq	85f			@ configure UART1
- + 		cmp	\rp, #ZOOM_UART		@ only on zoom2/3
- + 		beq	95f			@ configure ZOOM_UART
- + 
- + 		/* Configure the UART offset from the phys/virt base */
- + 21:		mov	\rp, #UART_OFFSET(OMAP2_UART1_BASE)	@ omap2/3/4
- + 		b	98f
- + 22:		mov	\rp, #UART_OFFSET(OMAP2_UART2_BASE)	@ omap2/3/4
- + 		b	98f
- + 23:		mov	\rp, #UART_OFFSET(OMAP2_UART3_BASE)
- + 		b	98f
- + 33:		mov	\rp, #UART_OFFSET(OMAP3_UART1_BASE)
- + 		add	\rp, \rp, #0x00fb0000
- + 		add	\rp, \rp, #0x00006000		@ OMAP3_UART3_BASE
- + 		b	98f
- + 34:		mov	\rp, #UART_OFFSET(OMAP3_UART1_BASE)
- + 		add	\rp, \rp, #0x00fb0000
- + 		add	\rp, \rp, #0x00028000		@ OMAP3_UART4_BASE
- + 		b	98f
- + 43:		mov	\rp, #UART_OFFSET(OMAP4_UART3_BASE)
- + 		b	98f
- + 44:		mov	\rp, #UART_OFFSET(OMAP4_UART4_BASE)
- + 		b	98f
- + 81:		mov	\rp, #UART_OFFSET(TI81XX_UART1_BASE)
- + 		b	98f
- + 82:		mov	\rp, #UART_OFFSET(TI81XX_UART2_BASE)
- + 		b	98f
- + 83:		mov	\rp, #UART_OFFSET(TI81XX_UART3_BASE)
- + 		b	98f
- + 84:		ldr	\rp, =AM33XX_UART1_BASE
- + 		and	\rp, \rp, #0x00ffffff
- + 		b	97f
- + 85:		ldr	\rp, =UART_OFFSET(AM33XX_UART4_BASE)
- + 		b	98f
- + 95:		ldr	\rp, =ZOOM_UART_BASE
- + 		str	\rp, [\tmp, #0]		@ omap_uart_phys
- + 		ldr	\rp, =ZOOM_UART_VIRT
- + 		str	\rp, [\tmp, #4]		@ omap_uart_virt
- + 		mov	\rp, #(UART_LSR << ZOOM_PORT_SHIFT)
- + 		str	\rp, [\tmp, #8]		@ omap_uart_lsr
- + 		b	10b
- + 
- + 		/* AM33XX: Store both phys and virt address for the uart */
- + 97:		add	\rp, \rp, #0x44000000	@ phys base
- + 		str	\rp, [\tmp, #0]		@ omap_uart_phys
- + 		sub	\rp, \rp, #0x44000000	@ phys base
- + 		add	\rp, \rp, #0xf9000000	@ virt base
- + 		str	\rp, [\tmp, #4]		@ omap_uart_virt
- + 		mov	\rp, #(UART_LSR << OMAP_PORT_SHIFT)
- + 		str	\rp, [\tmp, #8]		@ omap_uart_lsr
- + 
- + 		b	10b
- + 
- + 		/* Store both phys and virt address for the uart */
- + 98:		add	\rp, \rp, #0x48000000	@ phys base
- + 		str	\rp, [\tmp, #0]		@ omap_uart_phys
- + 		sub	\rp, \rp, #0x48000000	@ phys base
- + 		add	\rp, \rp, #0xfa000000	@ virt base
- + 		str	\rp, [\tmp, #4]		@ omap_uart_virt
- + 		mov	\rp, #(UART_LSR << OMAP_PORT_SHIFT)
- + 		str	\rp, [\tmp, #8]		@ omap_uart_lsr
- + 
- + 		b	10b
- + 
- + 		.align
- + 99:		.word	.
- + 		.word	omap_uart_phys
- + 		.ltorg
- + 
- + 100:		/* Pass the UART_LSR reg address */
- + 		ldr	\tmp, [\tmp, #8]	@ omap_uart_lsr
- + 		add	\rp, \rp, \tmp
- + 		add	\rv, \rv, \tmp
- + 		.endm
- + 
- + 		.macro	senduart,rd,rx
- + 		orr	\rd, \rd, \rx, lsl #24	@ preserve LSR reg offset
- + 		bic	\rx, \rx, #0xff		@ get base (THR) reg address
- + 		strb	\rd, [\rx]		@ send lower byte of rd
- + 		orr	\rx, \rx, \rd, lsr #24	@ restore original rx (LSR)
- + 		bic	\rd, \rd, #(0xff << 24)	@ restore original rd
- + 		.endm
- + 
- + 		.macro	busyuart,rd,rx
- + 1001:		ldrb	\rd, [\rx]		@ rx contains UART_LSR address
- + 		and	\rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
- + 		teq	\rd, #(UART_LSR_TEMT | UART_LSR_THRE)
- + 		bne	1001b
- + 		.endm
- + 
- + 		.macro	waituart,rd,rx
- + 		.endm
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/devices.h linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/devices.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/devices.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/devices.h	2014-05-15 13:25:13.918640389 +0900
- ***************
- *** 0 ****
- --- 1,27 ----
- + /*
- +  * Header for CKB 
- +  *
- +  * Copyright (C) 2013 Computex Co.Ltd.
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; version 2 of the License.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- +  *
- +  */
- +  
- + #ifndef __ASM_ARCH_DEVICES_H
- + #define __ASM_ARCH_DEVICES_H
- + 
- + #define CKB_EMIF_CS5_MAJOR		255
- + #define CKB_DVI_MAJOR			254
- + 
- + #endif  /*  __ASM_ARCH_DEVICES_H */
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/edma.h linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/edma.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/edma.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/edma.h	2014-05-15 13:25:13.918640389 +0900
- ***************
- *** 0 ****
- --- 1,250 ----
- + /*
- +  * TI EDMA3 definitions
- +  *
- +  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + /*
- +  * This EDMA3 programming framework exposes two basic kinds of resource:
- +  *
- +  *  Channel	Triggers transfers, usually from a hardware event but
- +  *		also manually or by "chaining" from DMA completions.
- +  *		Each channel is coupled to a Parameter RAM (PaRAM) slot.
- +  *
- +  *  Slot	Each PaRAM slot holds a DMA transfer descriptor (PaRAM
- +  *		"set"), source and destination addresses, a link to a
- +  *		next PaRAM slot (if any), options for the transfer, and
- +  *		instructions for updating those addresses.  There are
- +  *		more than twice as many slots as event channels.
- +  *
- +  * Each PaRAM set describes a sequence of transfers, either for one large
- +  * buffer or for several discontiguous smaller buffers.  An EDMA transfer
- +  * is driven only from a channel, which performs the transfers specified
- +  * in its PaRAM slot until there are no more transfers.  When that last
- +  * transfer completes, the "link" field may be used to reload the channel's
- +  * PaRAM slot with a new transfer descriptor.
- +  *
- +  * The EDMA Channel Controller (CC) maps requests from channels into physical
- +  * Transfer Controller (TC) requests when the channel triggers (by hardware
- +  * or software events, or by chaining).  The two physical DMA channels provided
- +  * by the TCs are thus shared by many logical channels.
- +  *
- +  * EDMA hardware also has a "QDMA" mechanism which is not currently
- +  * supported through this interface.  (DSP firmware uses it though.)
- +  */
- + 
- + #ifndef EDMA_H_
- + #define EDMA_H_
- + 
- + /* PaRAM slots are laid out like this */
- + struct edmacc_param {
- + 	unsigned int opt;
- + 	unsigned int src;
- + 	unsigned int a_b_cnt;
- + 	unsigned int dst;
- + 	unsigned int src_dst_bidx;
- + 	unsigned int link_bcntrld;
- + 	unsigned int src_dst_cidx;
- + 	unsigned int ccnt;
- + };
- + 
- + /* fields in edmacc_param.opt */
- + #define SAM		BIT(0)
- + #define DAM		BIT(1)
- + #define SYNCDIM		BIT(2)
- + #define STATIC		BIT(3)
- + #define EDMA_FWID	(0x07 << 8)
- + #define TCCMODE		BIT(11)
- + #define EDMA_TCC(t)	((t) << 12)
- + #define TCINTEN		BIT(20)
- + #define ITCINTEN	BIT(21)
- + #define TCCHEN		BIT(22)
- + #define ITCCHEN		BIT(23)
- + 
- + #define TRWORD (0x7<<2)
- + #define PAENTRY (0x1ff<<5)
- + 
- + /*ch_status paramater of callback function possible values*/
- + #define DMA_COMPLETE 1
- + #define DMA_CC_ERROR 2
- + #define DMA_TC0_ERROR 3
- + #define DMA_TC1_ERROR 4
- + #define DMA_TC2_ERROR 5
- + #define DMA_TC3_ERROR 6
- + 
- + enum address_mode {
- + 	INCR = 0,
- + 	FIFO = 1
- + };
- + 
- + enum fifo_width {
- + 	W8BIT = 0,
- + 	W16BIT = 1,
- + 	W32BIT = 2,
- + 	W64BIT = 3,
- + 	W128BIT = 4,
- + 	W256BIT = 5
- + };
- + 
- + enum dma_event_q {
- + 	EVENTQ_0 = 0,
- + 	EVENTQ_1 = 1,
- + 	EVENTQ_2 = 2,
- + 	EVENTQ_3 = 3,
- + 	EVENTQ_DEFAULT = -1
- + };
- + 
- + enum sync_dimension {
- + 	ASYNC = 0,
- + 	ABSYNC = 1
- + };
- + 
- + #define EDMA_CTLR_CHAN(ctlr, chan)	(((ctlr) << 16) | (chan))
- + #define EDMA_CTLR(i)			((i) >> 16)
- + #define EDMA_CHAN_SLOT(i)		((i) & 0xffff)
- + 
- + #define EDMA_CHANNEL_ANY		-1	/* for edma_alloc_channel() */
- + #define EDMA_SLOT_ANY			-1	/* for edma_alloc_slot() */
- + #define EDMA_CONT_PARAMS_ANY		 1001
- + #define EDMA_CONT_PARAMS_FIXED_EXACT	 1002
- + #define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
- + 
- + #define EDMA_MAX_DMACH           64
- + #define EDMA_MAX_PARAMENTRY     512
- + #define EDMA_MAX_CC               2
- + #define EDMA_MAX_REGION           4
- + 
- + 
- + /* Mapping of crossbar event numbers to actual DMA channels*/
- + struct event_to_channel_map {
- + 	unsigned        xbar_event_no;
- + 	int		channel_no;
- + };
- + 
- + /* actual number of DMA channels and slots on this silicon */
- + struct edma {
- + 	/* how many dma resources of each type */
- + 	unsigned	num_channels;
- + 	unsigned	num_region;
- + 	unsigned	num_slots;
- + 	unsigned	num_tc;
- + 	unsigned	num_cc;
- + 	enum dma_event_q	default_queue;
- + 
- + 	/* list of channels with no even trigger; terminated by "-1" */
- + 	const s8	*noevent;
- + 
- + 	/* The edma_inuse bit for each PaRAM slot is clear unless the
- + 	 * channel is in use ... by ARM or DSP, for QDMA, or whatever.
- + 	 */
- + 	DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
- + 
- + 	/* The edma_unused bit for each channel is clear unless
- + 	 * it is not being used on this platform. It uses a bit
- + 	 * of SOC-specific initialization code.
- + 	 */
- + 	DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH);
- + 
- + 	unsigned	irq_res_start;
- + 	unsigned	irq_res_end;
- + 
- + 	struct dma_interrupt_data {
- + 		void (*callback)(unsigned channel, unsigned short ch_status,
- + 				void *data);
- + 		void *data;
- + 	} intr_data[EDMA_MAX_DMACH];
- + 
- + 	unsigned	is_xbar;
- + 	unsigned	num_events;
- + 	struct event_to_channel_map	*xbar_event_mapping;
- + 
- + 	/* suspend/resume backup parameters */
- + 	struct edmacc_param *bkp_prm_set;
- + 	unsigned int *bkp_ch_map;		/* 64 registers */
- + 	unsigned int *bkp_que_num;		/* 8 registers */
- + 	unsigned int *bkp_drae;
- + 	unsigned int *bkp_draeh;
- + 	unsigned int *bkp_qrae;
- + 	unsigned int bkp_sh_esr;
- + 	unsigned int bkp_sh_esrh;
- + 	unsigned int bkp_sh_eesr;
- + 	unsigned int bkp_sh_eesrh;
- + 	unsigned int bkp_sh_iesr;
- + 	unsigned int bkp_sh_iesrh;
- + 	unsigned int bkp_que_tc_map;
- + 	unsigned int bkp_que_pri;
- + };
- + 
- + extern struct edma *edma_cc[EDMA_MAX_CC];
- + 
- + /* alloc/free DMA channels and their dedicated parameter RAM slots */
- + int edma_alloc_channel(int channel,
- + 	void (*callback)(unsigned channel, u16 ch_status, void *data),
- + 	void *data, enum dma_event_q);
- + void edma_free_channel(unsigned channel);
- + 
- + /* alloc/free parameter RAM slots */
- + int edma_alloc_slot(unsigned ctlr, int slot);
- + void edma_free_slot(unsigned slot);
- + 
- + /* alloc/free a set of contiguous parameter RAM slots */
- + int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count);
- + int edma_free_cont_slots(unsigned slot, int count);
- + 
- + /* calls that operate on part of a parameter RAM slot */
- + void edma_set_src(unsigned slot, dma_addr_t src_port,
- + 				enum address_mode mode, enum fifo_width);
- + void edma_set_dest(unsigned slot, dma_addr_t dest_port,
- + 				 enum address_mode mode, enum fifo_width);
- + void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst);
- + void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx);
- + void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx);
- + void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt,
- + 		u16 bcnt_rld, enum sync_dimension sync_mode);
- + void edma_link(unsigned from, unsigned to);
- + void edma_unlink(unsigned from);
- + 
- + /* calls that operate on an entire parameter RAM slot */
- + void edma_write_slot(unsigned slot, const struct edmacc_param *params);
- + void edma_read_slot(unsigned slot, struct edmacc_param *params);
- + 
- + /* channel control operations */
- + int edma_start(unsigned channel);
- + void edma_stop(unsigned channel);
- + void edma_clean_channel(unsigned channel);
- + void edma_clear_event(unsigned channel);
- + void edma_pause(unsigned channel);
- + void edma_resume(unsigned channel);
- + 
- + /* platform_data for EDMA driver */
- + struct edma_soc_info {
- + 
- + 	/* how many dma resources of each type */
- + 	unsigned	n_channel;
- + 	unsigned	n_region;
- + 	unsigned	n_slot;
- + 	unsigned	n_tc;
- + 	unsigned	n_cc;
- + 	enum dma_event_q	default_queue;
- + 
- + 	const s16	(*rsv_chans)[2];
- + 	const s16	(*rsv_slots)[2];
- + 	const s8	(*queue_tc_mapping)[2];
- + 	const s8	(*queue_priority_mapping)[2];
- + 	unsigned	is_xbar;
- + 	unsigned	n_events;
- + 	struct event_to_channel_map    *xbar_event_mapping;
- + 	int		(*map_xbar_channel)(unsigned event, unsigned *channel,
- + 				struct event_to_channel_map *xbar_event_map);
- + };
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/entry-macro.S linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/entry-macro.S
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/entry-macro.S	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/entry-macro.S	2014-05-15 13:25:13.918640389 +0900
- ***************
- *** 0 ****
- --- 1,55 ----
- + /*
- +  * arch/arm/plat-omap/include/mach/entry-macro.S
- +  *
- +  * Low-level IRQ helper macros for OMAP-based platforms
- +  *
- +  * Copyright (C) 2009 Texas Instruments
- +  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
- +  *
- +  * This file is licensed under  the terms of the GNU General Public
- +  * License version 2. This program is licensed "as is" without any
- +  * warranty of any kind, whether express or implied.
- +  */
- +  #include <mach/hardware.h>
- + #include <mach/io.h>
- + #include <mach/irqs.h>
- + #include <asm/hardware/gic.h>
- + 
- + #include <plat/omap34xx.h>
- + 
- + #include <plat/multi.h>
- + 
- + #define OMAP3_IRQ_BASE		OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
- + #define INTCPS_SIR_IRQ_OFFSET	0x0040	/* omap2/3 active interrupt offset */
- + #define	ACTIVEIRQ_MASK		0x7f	/* omap2/3 active interrupt bits */
- + 
- + 		.macro	disable_fiq
- + 		.endm
- + 
- + 		.macro  arch_ret_to_user, tmp1, tmp2
- + 		.endm
- + 
- + /*
- +  * Optimized irq functions for omap2, 3 and 4
- +  */
- + 
- + 		.macro  get_irqnr_preamble, base, tmp
- + 		ldr	\base, =OMAP3_IRQ_BASE
- + 		.endm
- + 
- + 		/* Check the pending interrupts. Note that base already set */
- + 		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
- + 		ldr	\irqnr, [\base, #0x98] /* IRQ pending reg 1 */
- + 		cmp	\irqnr, #0x0
- + 		bne	9999f
- + 		ldr	\irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
- + 		cmp	\irqnr, #0x0
- + 		bne	9999f
- + 		ldr	\irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
- + 		cmp	\irqnr, #0x0
- + 9999:
- + 		ldrne	\irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
- + 		and	\irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
- + 
- + 		.endm
- + 
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/gpio.h linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/gpio.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/gpio.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/gpio.h	2014-05-15 13:25:13.918640389 +0900
- ***************
- *** 0 ****
- --- 1,5 ----
- + /*
- +  * arch/arm/mach-omap2/include/mach/gpio.h
- +  */
- + 
- + #include <plat/gpio.h>
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/hardware.h linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/hardware.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/hardware.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/hardware.h	2014-05-15 13:25:13.918640389 +0900
- ***************
- *** 0 ****
- --- 1,7 ----
- + /*
- +  * arch/arm/mach-omap2/include/mach/hardware.h
- +  */
- + 
- + #include <plat/hardware.h>
- + #define AM3352_GPMC_BASE		0x50000000
- + #define CKB_GPMC_CS1_BASE		0x09000000
- \ No newline at end of file
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/io.h linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/io.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/io.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/io.h	2014-05-15 13:25:13.922685175 +0900
- ***************
- *** 0 ****
- --- 1,5 ----
- + /*
- +  * arch/arm/mach-omap2/include/mach/io.h
- +  */
- + 
- + #include <plat/io.h>
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/irqs.h linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/irqs.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/irqs.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/irqs.h	2014-05-15 13:25:13.922685175 +0900
- ***************
- *** 0 ****
- --- 1,5 ----
- + /*
- +  * arch/arm/mach-omap2/include/mach/irqs.h
- +  */
- + 
- + #include <plat/irqs.h>
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/memory.h linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/memory.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/memory.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/memory.h	2014-05-15 13:25:13.922685175 +0900
- ***************
- *** 0 ****
- --- 1,22 ----
- + /*
- +  * Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; version 2 of the License.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- +  *
- +  */
- + #ifndef __ASM_ARCH_CKB_MEMORY_H
- + #define __ASM_ARCH_CKB_MEMORY_H
- + 
- + 
- + #endif /* __ASM_ARCH_CKB_MEMORY_H */
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/omap-secure.h linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/omap-secure.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/omap-secure.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/omap-secure.h	2014-05-15 13:25:13.922685175 +0900
- ***************
- *** 0 ****
- --- 1,57 ----
- + /*
- +  * omap-secure.h: OMAP Secure infrastructure header.
- +  *
- +  * Copyright (C) 2011 Texas Instruments, Inc.
- +  *	Santosh Shilimkar <santosh.shilimkar@ti.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + #ifndef OMAP_ARCH_OMAP_SECURE_H
- + #define OMAP_ARCH_OMAP_SECURE_H
- + 
- + /* Monitor error code */
- + #define  API_HAL_RET_VALUE_NS2S_CONVERSION_ERROR	0xFFFFFFFE
- + #define  API_HAL_RET_VALUE_SERVICE_UNKNWON		0xFFFFFFFF
- + 
- + /* HAL API error codes */
- + #define  API_HAL_RET_VALUE_OK		0x00
- + #define  API_HAL_RET_VALUE_FAIL		0x01
- + 
- + /* Secure HAL API flags */
- + #define FLAG_START_CRITICAL		0x4
- + #define FLAG_IRQFIQ_MASK		0x3
- + #define FLAG_IRQ_ENABLE			0x2
- + #define FLAG_FIQ_ENABLE			0x1
- + #define NO_FLAG				0x0
- + 
- + /* Maximum Secure memory storage size */
- + #define OMAP_SECURE_RAM_STORAGE	(88 * SZ_1K)
- + 
- + /* Secure low power HAL API index */
- + #define OMAP4_HAL_SAVESECURERAM_INDEX	0x1a
- + #define OMAP4_HAL_SAVEHW_INDEX		0x1b
- + #define OMAP4_HAL_SAVEALL_INDEX		0x1c
- + #define OMAP4_HAL_SAVEGIC_INDEX		0x1d
- + 
- + /* Secure Monitor mode APIs */
- + #define OMAP4_MON_SCU_PWR_INDEX		0x108
- + #define OMAP4_MON_L2X0_DBG_CTRL_INDEX	0x100
- + #define OMAP4_MON_L2X0_CTRL_INDEX	0x102
- + #define OMAP4_MON_L2X0_AUXCTRL_INDEX	0x109
- + #define OMAP4_MON_L2X0_PREFETCH_INDEX	0x113
- + 
- + /* Secure PPA(Primary Protected Application) APIs */
- + #define OMAP4_PPA_L2_POR_INDEX		0x23
- + #define OMAP4_PPA_CPU_ACTRL_SMP_INDEX	0x25
- + 
- + #ifndef __ASSEMBLER__
- + 
- + extern u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs,
- + 				u32 arg1, u32 arg2, u32 arg3, u32 arg4);
- + extern u32 omap_smc2(u32 id, u32 falg, u32 pargs);
- + extern phys_addr_t omap_secure_ram_mempool_base(void);
- + 
- + #endif /* __ASSEMBLER__ */
- + #endif /* OMAP_ARCH_OMAP_SECURE_H */
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/smp.h linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/smp.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/smp.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/smp.h	2014-05-15 13:25:13.922685175 +0900
- ***************
- *** 0 ****
- --- 1,5 ----
- + /*
- +  * arch/arm/mach-omap2/include/mach/smp.h
- +  */
- + 
- + #include <plat/smp.h>
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/sram.h linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/sram.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/sram.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/sram.h	2014-05-15 13:25:13.926571658 +0900
- ***************
- *** 0 ****
- --- 1,14 ----
- + /*
- +  * arch/arm/mach-omap2/include/mach/sram.h
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #ifndef __ARCH_ARM_SRAM_H
- + #define __ARCH_ARM_SRAM_H
- + 
- + #include <plat/sram.h>
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/system.h linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/system.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/system.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/system.h	2014-05-15 13:25:13.926571658 +0900
- ***************
- *** 0 ****
- --- 1,5 ----
- + /*
- +  * arch/arm/mach-omap2/include/mach/system.h
- +  */
- + 
- + #include <plat/system.h>
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/timex.h linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/timex.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/timex.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/timex.h	2014-05-15 13:25:13.926571658 +0900
- ***************
- *** 0 ****
- --- 1,5 ----
- + /*
- +  * arch/arm/mach-omap2/include/mach/timex.h
- +  */
- + 
- + #include <plat/timex.h>
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/uncompress.h linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/uncompress.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/uncompress.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/uncompress.h	2014-05-15 13:25:13.926571658 +0900
- ***************
- *** 0 ****
- --- 1,5 ----
- + /*
- +  * arch/arm/mach-omap2/include/mach/uncompress.h
- +  */
- + 
- + #include <plat/uncompress.h>
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/vmalloc.h linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/vmalloc.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/vmalloc.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/vmalloc.h	2014-05-15 13:25:13.926571658 +0900
- ***************
- *** 0 ****
- --- 1,6 ----
- + #ifndef __ASM_ARCH_VMALLOC_H
- + #define __ASM_ARCH_VMALLOC_H
- + 
- + #define VMALLOC_END	  (0xff000000UL)
- + 
- + #endif  /*  __ASM_ARCH_VMALLOC_H */
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/io.c linux-3.2.1/arch/arm/mach-ckb_3352/io.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/io.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/io.c	2014-05-15 13:25:13.926571658 +0900
- ***************
- *** 0 ****
- --- 1,215 ----
- + /*
- +  * linux/arch/arm/mach-omap2/io.c
- +  *
- +  * OMAP2 I/O mapping code
- +  *
- +  * Copyright (C) 2005 Nokia Corporation
- +  * Copyright (C) 2007-2009 Texas Instruments
- +  *
- +  * Author:
- +  *	Juha Yrjola <juha.yrjola@nokia.com>
- +  *	Syed Khasim <x0khasim@ti.com>
- +  *
- +  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + #include <linux/module.h>
- + #include <linux/kernel.h>
- + #include <linux/init.h>
- + #include <linux/io.h>
- + #include <linux/clk.h>
- + #include <linux/omapfb.h>
- + 
- + #include <asm/tlb.h>
- + 
- + #include <asm/mach/map.h>
- + 
- + #include <plat/sram.h>
- + #include <plat/sdrc.h>
- + #include <plat/serial.h>
- + 
- + #include "clock.h"
- + #include "clock33xx.h"
- + 
- + #include "common.h"
- + #include <plat/omap-pm.h>
- + #include "voltage.h"
- + #include "powerdomain.h"
- + #include "prminst44xx.h"
- + #include "cminst44xx.h"
- + 
- + #include "clockdomain.h"
- + #include <plat/omap_hwmod.h>
- + #include <plat/multi.h>
- + #include "common.h"
- + 
- + #include <mach/ckb_3352_mem.h>
- + 
- + #ifdef CONFIG_SOC_OMAPAM33XX
- + static struct map_desc omapam33xx_io_desc[] __initdata = {
- + 	{
- + 		.virtual	= L4_34XX_VIRT,
- + 		.pfn		= __phys_to_pfn(L4_34XX_PHYS),
- + 		.length		= L4_34XX_SIZE,
- + 		.type		= MT_DEVICE
- + 	},
- + 	{
- + 		.virtual	= L4_WK_AM33XX_VIRT,
- + 		.pfn		= __phys_to_pfn(L4_WK_AM33XX_PHYS),
- + 		.length		= L4_WK_AM33XX_SIZE,
- + 		.type		= MT_DEVICE
- + 	},
- + };
- + #endif
- + 
- + #ifdef CONFIG_SOC_OMAPAM33XX
- + void __init omapam33xx_map_common_io(void)
- + {
- + 	iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
- + }
- + #endif
- + 
- + /*
- +  * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
- +  *
- +  * Sets the CORE DPLL3 M2 divider to the same value that it's at
- +  * currently.  This has the effect of setting the SDRC SDRAM AC timing
- +  * registers to the values currently defined by the kernel.  Currently
- +  * only defined for OMAP3; will return 0 if called on OMAP2.  Returns
- +  * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
- +  * or passes along the return value of clk_set_rate().
- +  */
- + static int __init _omap2_init_reprogram_sdrc(void)
- + {
- + 	struct clk *dpll3_m2_ck;
- + 	int v = -EINVAL;
- + 	long rate;
- + 
- + 	dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
- + 	if (IS_ERR(dpll3_m2_ck))
- + 		return -EINVAL;
- + 
- + 	rate = clk_get_rate(dpll3_m2_ck);
- + 	pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
- + 	v = clk_set_rate(dpll3_m2_ck, rate);
- + 	if (v)
- + 		pr_err("dpll3_m2_clk rate change failed: %d\n", v);
- + 
- + 	clk_put(dpll3_m2_ck);
- + 
- + 	return v;
- + }
- + 
- + static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
- + {
- + 	return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
- + }
- + 
- + static void __init omap_common_init_early(void)
- + {
- + 	omap_init_consistent_dma_size();
- + }
- + 
- + static void __init omap_hwmod_init_postsetup(void)
- + {
- + 	u8 postsetup_state;
- + 
- + 	/* Set the default postsetup state for all hwmods */
- + #ifdef CONFIG_PM_RUNTIME
- + 	postsetup_state = _HWMOD_STATE_IDLE;
- + #else
- + 	postsetup_state = _HWMOD_STATE_ENABLED;
- + #endif
- + 	omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
- + 
- + 	/*
- + 	 * Set the default postsetup state for unusual modules (like
- + 	 * MPU WDT).
- + 	 *
- + 	 * The postsetup_state is not actually used until
- + 	 * omap_hwmod_late_init(), so boards that desire full watchdog
- + 	 * coverage of kernel initialization can reprogram the
- + 	 * postsetup_state between the calls to
- + 	 * omap2_init_common_infra() and omap_sdrc_init().
- + 	 *
- + 	 * XXX ideally we could detect whether the MPU WDT was currently
- + 	 * enabled here and make this conditional
- + 	 */
- + 	postsetup_state = _HWMOD_STATE_DISABLED;
- + 	omap_hwmod_for_each_by_class("wd_timer",
- + 				     _set_hwmod_postsetup_state,
- + 				     &postsetup_state);
- + 
- + 	omap_pm_if_early_init();
- + }
- + 
- + void __init am33xx_init_early(void)
- + {
- + 	omap2_set_globals_am33xx();
- + 	omap3xxx_check_revision();
- + 	am33xx_check_features();
- + 	omap_common_init_early();
- + 	am33xx_voltagedomains_init();
- + 	omap44xx_prminst_init();
- + 	am33xx_powerdomains_init();
- + 	omap44xx_cminst_init();
- + 	am33xx_clockdomains_init();
- + 	am33xx_hwmod_init();
- + 	omap_hwmod_init_postsetup();
- + 	am33xx_clk_init();
- + }
- + 
- + 
- + void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
- + 				      struct omap_sdrc_params *sdrc_cs1)
- + {
- + 	omap_sram_init();
- + 
- + 	if (omap3_has_sdrc()) {
- + 		omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
- + 		_omap2_init_reprogram_sdrc();
- + 	}
- + }
- + 
- + /*
- +  * NOTE: Please use ioremap + __raw_read/write where possible instead of these
- +  */
- + 
- + u8 omap_readb(u32 pa)
- + {
- + 	return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
- + }
- + EXPORT_SYMBOL(omap_readb);
- + 
- + u16 omap_readw(u32 pa)
- + {
- + 	return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
- + }
- + EXPORT_SYMBOL(omap_readw);
- + 
- + u32 omap_readl(u32 pa)
- + {
- + 	return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
- + }
- + EXPORT_SYMBOL(omap_readl);
- + 
- + void omap_writeb(u8 v, u32 pa)
- + {
- + 	__raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
- + }
- + EXPORT_SYMBOL(omap_writeb);
- + 
- + void omap_writew(u16 v, u32 pa)
- + {
- + 	__raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
- + }
- + EXPORT_SYMBOL(omap_writew);
- + 
- + void omap_writel(u32 v, u32 pa)
- + {
- + 	__raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
- + }
- + EXPORT_SYMBOL(omap_writel);
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/irq.c linux-3.2.1/arch/arm/mach-ckb_3352/irq.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/irq.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/irq.c	2014-05-15 13:25:13.931017353 +0900
- ***************
- *** 0 ****
- --- 1,239 ----
- + /*
- +  * linux/arch/arm/mach-omap2/irq.c
- +  *
- +  * Interrupt handler for OMAP2 boards.
- +  *
- +  * Copyright (C) 2005 Nokia Corporation
- +  * Author: Paul Mundt <paul.mundt@nokia.com>
- +  *
- +  * This file is subject to the terms and conditions of the GNU General Public
- +  * License. See the file "COPYING" in the main directory of this archive
- +  * for more details.
- +  */
- + #include <linux/kernel.h>
- + #include <linux/init.h>
- + #include <linux/interrupt.h>
- + #include <linux/io.h>
- + #include <mach/hardware.h>
- + #include <asm/exception.h>
- + #include <asm/mach/irq.h>
- + 
- + 
- + /* selected INTC register offsets */
- + 
- + #define INTC_REVISION		0x0000
- + #define INTC_SYSCONFIG		0x0010
- + #define INTC_SYSSTATUS		0x0014
- + #define INTC_SIR		0x0040
- + #define INTC_CONTROL		0x0048
- + #define INTC_PROTECTION		0x004C
- + #define INTC_IDLE		0x0050
- + #define INTC_THRESHOLD		0x0068
- + #define INTC_MIR0		0x0084
- + #define INTC_MIR_CLEAR0		0x0088
- + #define INTC_MIR_SET0		0x008c
- + #define INTC_PENDING_IRQ0	0x0098
- + /* Number of IRQ state bits in each MIR register */
- + #define IRQ_BITS_PER_REG	32
- + 
- + #define OMAP2_IRQ_BASE		OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
- + #define OMAP3_IRQ_BASE		OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
- + #define INTCPS_SIR_IRQ_OFFSET	0x0040	/* omap2/3 active interrupt offset */
- + #define ACTIVEIRQ_MASK		0x7f	/* omap2/3 active interrupt bits */
- + 
- + /*
- +  * OMAP2 has a number of different interrupt controllers, each interrupt
- +  * controller is identified as its own "bank". Register definitions are
- +  * fairly consistent for each bank, but not all registers are implemented
- +  * for each bank.. when in doubt, consult the TRM.
- +  */
- + static struct omap_irq_bank {
- + 	void __iomem *base_reg;
- + 	unsigned int nr_irqs;
- + 	unsigned int nr_regs_req;
- + } __attribute__ ((aligned(4))) irq_banks[] = {
- + 	{
- + 		/* MPU INTC */
- + 		.nr_irqs	= 96,
- + 		.nr_regs_req	= 3,
- + 	},
- + };
- + 
- + /* Structure to save interrupt controller context */
- + struct omap3_intc_regs {
- + 	u32 sysconfig;
- + 	u32 protection;
- + 	u32 idle;
- + 	u32 threshold;
- + 	u32 ilr[INTCPS_MAX_NR_IRQS];
- + 	u32 mir[INTCPS_MAX_NR_REGS_REQ];
- + };
- + 
- + /* INTC bank register get/set */
- + 
- + static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
- + {
- + 	__raw_writel(val, bank->base_reg + reg);
- + }
- + 
- + static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
- + {
- + 	return __raw_readl(bank->base_reg + reg);
- + }
- + 
- + /* XXX: FIQ and additional INTC support (only MPU at the moment) */
- + static void omap_ack_irq(struct irq_data *d)
- + {
- + 	intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
- + }
- + 
- + static void omap_mask_ack_irq(struct irq_data *d)
- + {
- + 	irq_gc_mask_disable_reg(d);
- + 	omap_ack_irq(d);
- + }
- + 
- + static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
- + {
- + 	unsigned long tmp;
- + 
- + 	tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
- + 	printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
- + 			 "(revision %ld.%ld) with %d interrupts\n",
- + 			 bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
- + 
- + 	tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
- + 	tmp |= 1 << 1;	/* soft reset */
- + 	intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);
- + 
- + 	while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
- + 		/* Wait for reset to complete */;
- + 
- + 	/* Enable autoidle */
- + 	intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
- + }
- + 
- + int omap_irq_pending(void)
- + {
- + 	int i;
- + 
- + 	for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
- + 		struct omap_irq_bank *bank = irq_banks + i;
- + 		int irq;
- + 
- + 		for (irq = 0; irq < bank->nr_irqs; irq += 32)
- + 			if (intc_bank_read_reg(bank, INTC_PENDING_IRQ0 +
- + 					       ((irq >> 5) << 5)))
- + 				return 1;
- + 	}
- + 	return 0;
- + }
- + 
- + static __init void
- + omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
- + {
- + 	struct irq_chip_generic *gc;
- + 	struct irq_chip_type *ct;
- + 
- + 	gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
- + 					handle_level_irq);
- + 	ct = gc->chip_types;
- + 	ct->chip.irq_ack = omap_mask_ack_irq;
- + 	ct->chip.irq_mask = irq_gc_mask_disable_reg;
- + 	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
- + 	ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;
- + 
- + 	ct->regs.ack = INTC_CONTROL;
- + 	ct->regs.enable = INTC_MIR_CLEAR0;
- + 	ct->regs.disable = INTC_MIR_SET0;
- + 	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
- + 				IRQ_NOREQUEST | IRQ_NOPROBE, 0);
- + }
- + 
- + static void __init omap_init_irq(u32 base, int nr_irqs)
- + {
- + 	void __iomem *omap_irq_base;
- + 	unsigned long nr_of_irqs = 0;
- + 	unsigned int nr_banks = 0;
- + 	int i, j;
- + 
- + 	omap_irq_base = ioremap(base, SZ_4K);
- + 	if (WARN_ON(!omap_irq_base))
- + 		return;
- + 
- + 	for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
- + 		struct omap_irq_bank *bank = irq_banks + i;
- + 
- + 		bank->nr_irqs = nr_irqs;
- + 		bank->nr_regs_req = 0;
- + 
- + 		/* Static mapping, never released */
- + 		bank->base_reg = ioremap(base, SZ_4K);
- + 		if (!bank->base_reg) {
- + 			printk(KERN_ERR "Could not ioremap irq bank%i\n", i);
- + 			continue;
- + 		}
- + 
- + 		omap_irq_bank_init_one(bank);
- + 
- + 		for (j = 0; j < bank->nr_irqs; j += 32) {
- + 			omap_alloc_gc(bank->base_reg + j, j, 32);
- + 			bank->nr_regs_req++;
- + 		}
- + 
- + 		nr_of_irqs += bank->nr_irqs;
- + 		nr_banks++;
- + 	}
- + 
- + 	printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
- + 	       nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
- + }
- + 
- + void __init omap3_init_irq(void)
- + {
- + 	omap_init_irq(OMAP34XX_IC_BASE, 96);
- + }
- + 
- + void __init ti81xx_init_irq(void)
- + {
- + 	omap_init_irq(OMAP34XX_IC_BASE, 128);
- + }
- + 
- + static inline void omap_intc_handle_irq(void __iomem *base_addr,
- + 		unsigned int no_regs_req, struct pt_regs *regs)
- + {
- + 	u32 irqnr = 0;
- + 
- + 	do {
- + 		int i = 0;
- + 
- + 		for (i = 0; i < no_regs_req; i++) {
- + 			irqnr = readl_relaxed(base_addr + 0x98 + (0x20 * i));
- + 			if (irqnr)
- + 				goto out;
- + 		}
- + 
- + out:
- + 		if (!irqnr)
- + 			break;
- + 
- + 		irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);
- + 		irqnr &= ACTIVEIRQ_MASK;
- + 
- + 		if (irqnr)
- + 			handle_IRQ(irqnr, regs);
- + 	} while (irqnr);
- + }
- + 
- + void omap3_intc_suspend(void)
- + {
- + 	/* A pending interrupt would prevent OMAP from entering suspend */
- + 	omap_ack_irq(0);
- + }
- + 
- + asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs)
- + {
- + 	void __iomem *base_addr = OMAP3_IRQ_BASE;
- + 	omap_intc_handle_irq(base_addr, irq_banks[0].nr_regs_req, regs);
- + }
- + 
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/Kconfig linux-3.2.1/arch/arm/mach-ckb_3352/Kconfig
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/Kconfig	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/Kconfig	2014-06-09 17:46:49.010000000 +0900
- ***************
- *** 0 ****
- --- 1,1243 ----
- + if ARCH_CKB
- + 
- + config SOC_OMAPAM33XX
- + 	bool
- + 
- + config MACH_CKB_3352
- + 	bool "CKB 3352 board"
- + 	default y
- + 	select OMAP_PACKAGE_CBB
- + 	select NEED_MACH_MEMORY_H
- + 	select SOC_OMAPAM33XX
- + 	select CPU_V7
- + 	select CLKDEV_LOOKUP
- + 	select GENERIC_IRQ_CHIP
- + 	select USE_OF
- + 	select PROC_DEVICETREE
- + 	select USB_ARCH_HAS_EHCI
- + 	select ARM_L1_CACHE_SHIFT_6
- + 	select ARCH_HAS_OPP
- + 	select PM_OPP if PM
- + 	select ARM_CPU_SUSPEND if PM
- + 	select MULTI_IRQ_HANDLER
- + 	select AEABI
- + 	select REGULATOR
- + 	select PM_RUNTIME
- + 	select VFP
- + 	select NEON
- + 	select SERIAL_OMAP
- + 	select SERIAL_OMAP_CONSOLE
- + 	select I2C
- + 	select I2C_OMAP
- + 	select HAVE_PWM
- + 
- + config CKB_SUSPEND_SUPPORT
- + 	bool "Suspend support"
- + 
- + 
- + config CKB_TSC2007_TOUCH_PANEL
- + 	bool
- + 
- + config CKB_RTC
- + 	bool
- + 
- + config CKB_LCD_SUPPORT
- + 	bool "Support LCD"
- + 	depends on MACH_CKB_3352
- + 	select FB_DA8XX
- + 		
- + choice
- + 	prompt "Select LCD board"
- + 	depends on CKB_LCD_SUPPORT
- + 	help
- + 	  Select LCD board with peripherals. 
- + 
- + config CKB_LCD_01
- + 	bool "CKB LCD-01"
- + 	select CKB_TSC2007_TOUCH_PANEL
- + 	select CKB_RTC
- + 	help
- + 	  Support for Computex CKB LCD_01 LCD board (Visionx KTM050AL02).
- + 	  	  	
- + config CKB_LCD_02
- + 	bool "CKB LCD-02"
- + 	select CKB_TSC2007_TOUCH_PANEL
- + 	help
- + 	  Support for Computex CKB LCD_02 LCD board (Kyocera TCG070WVLPAAFA_AA00).
- + endchoice
- + 
- + config CKB_DVI_SUPPORT
- + 	bool "Support DVI"
- + 	depends on MACH_CKB_3352
- + 	select FB_DA8XX
- + 	select FB_DDC
- + 	select FB_MODE_HELPERS
- + 	help
- + 		Select this option to add DVI support on CKB 3352.
- + 
- + config DISPLAY_DVI_RESOLUTIONS
- + 	bool "Display DVI resolutions when a device is connected"
- + 	depends on CKB_DVI_SUPPORT
- + 	help
- + 	Select this option to display the DVI resolution read from the
- + 	device on the terminal. Some resolutions may not be supported.
- + 	The file /etc/fb.modes will have a list of resolutions that are
- + 	be supported.
- + 
- + config DISPLAY_UNSUPPORTED_DVI_RESOLUTIONS
- + 	bool "Display DVI unsupported resolutions"
- + 	depends on DISPLAY_DVI_RESOLUTIONS
- + 	help
- + 	Select this option to display the DVI resolution that have been
- + 	ignored because of incompatibility.
- + 
- + config LCD_CLOCK_CLOSEST_MATCH
- + 	bool "Compute best match for LCD/DVI output clock"
- + 	depends on CKB_LCD_SUPPORT || CKB_DVI_SUPPORT
- + 	help
- + 	This option finds the best matching output clock for LCD/DVI
- + 	and uses it.
- + 
- + config CKB_EASY_SWITCH_MODE
- + 	bool "Use numbers instead of names in /etc/fb.modes"
- + 	depends on CKB_LCD_SUPPORT || CKB_DVI_SUPPORT
- + 	help
- + 	  This option makes it easier to switch the LCD configuration bootloader.
- + 	  Instead of "fbset <mode_name>", "fbset <number>" can be used.
- + 	  <number> will be shorter than <mode_name>.
- + 
- + config OMAP_PACKAGE_CBB
- +        bool
- + 
- + config SUPPORT_CMJ100
- + 	bool "CM-J100 WLAN card support"
- + 	depends on MACH_CKB_3352
- + 	help
- + 	  Select this option to add support for CM-J100 WLAN card.
- + 
- + config SUPPORT_CKB_LED
- + 	bool "Support on-board LEDs"
- + 	depends on MACH_CKB_3352
- + 	help
- + 	  Select this option to add support for on-baord LEDs. 
- + 
- + config SUPPORT_GPMC_CS1_MEM
- + 	bool "Support GPMC CS1 mem on EX_CN"
- + 	depends on MACH_CKB_3352
- + 	help
- + 	  Select this option to add support for GPMC CS1 mem device on EX_CN.
- + 	
- + menu "EX_CN devices/ pin multiplex options"
- + 	depends on MACH_CKB_3352
- + 		
- + 		
- + comment "EX_CN devices"
- + 
- + config CKB_EXTCN_26_28
- + 	bool "Devices on Pins 26,28"
- + 
- + choice
- + 	bool "Pin 26,28 device"
- + 	depends on CKB_EXTCN_26_28
- + 	help
- + 	  Choose which peripheral to use. 
- + 	  
- + config CKB_EXTCN_I2C1
- + 	bool "I2C1"
- + 	help
- + 	  Select this to use I2C1 on Pin26 and Pin28.
- + 	  
- + config CKB_EXTCN_UART4
- + 	bool "UART4"
- + 	help
- + 	  Select this to use UART4 on Pin26 and Pin28
- + 
- + config CKB_EXTCN_CAN1
- + 	bool "CAN1"
- + 	help
- + 	  Select this to use CAN1 on Pin26 and Pin28
- + 
- + endchoice
- + 
- + menu "Disable LCD support to enable spidev on Pins 6,31,36,38"
- + 	depends on CKB_LCD_SUPPORT
- + endmenu
- + 
- + config CKB_EXTCN_SPIDEV_SPI1
- + 	bool "spidev (Pins 6,31,36,38) - Do not connect LCD board"
- + 	depends on !CKB_LCD_SUPPORT
- + 	help
- + 	  Select this if SPI1 has to be used on EX_CN
- + 
- + config CKB_EXTCN_ADC
- + 	bool "ADC (Pins 3,5,7)"
- + 	select MFD_TI_AM335X_TSCADC
- + 	help
- + 	  ADC on EX_CN
- + 
- + comment "EX_CN pin multiplex"
- + 
- + menu "Disable LCD support to enable Pin2 multiplex options"
- + 	depends on CKB_LCD_SUPPORT
- + endmenu
- + 
- + choice
- + 	prompt "Pin2 - Do not connect LCD board"
- + 	depends on !CKB_LCD_SUPPORT
- + 	help
- + 	  The LCD board shoudn't be connected as this is multiplexed with LCD data lines.
- + 
- + config CKB_EX_CN_PIN2_LCD_DATA12
- + 	bool "LCD_DATA12"
- + 
- + config CKB_EX_CN_PIN2_A16
- + 	bool "A16"
- + 
- + config CKB_EX_CN_PIN2_EQEP1A_IN
- + 	bool "EQEP1A_IN"
- + 
- + config CKB_EX_CN_PIN2_MCASP0_ACLKR
- + 	bool "MCASP0_ACLKR"
- + 
- + config CKB_EX_CN_PIN2_MCAP0_AXR2
- + 	bool "MCAP0_AXR2"
- + 	
- + config CKB_EX_CN_PIN2_PR1_MII0_RXLINK
- + 	bool "PR1_MII0_RXLINK"
- + 
- + config CKB_EX_CN_PIN2_UART4_CTS
- + 	bool "UART4_CTS"
- + 
- + config CKB_EX_CN_PIN2_OGPIO
- + 	bool "GPIO output (GPIO0_8)"
- + 
- + config CKB_EX_CN_PIN2_IGPIO
- + 	bool "GPIO input (GPIO0_8)"
- + 
- + endchoice
- + 
- + menu "Disable LCD support to enable Pin4 multiplex options"
- + 	depends on CKB_LCD_SUPPORT
- + endmenu
- + 
- + choice 
- + 	prompt "Pin4 - Do not connect LCD board"
- + 	depends on !CKB_LCD_SUPPORT
- + 	help
- + 	  The LCD board shoudn't be connected as this is multiplexed with LCD data lines.
- + 	  
- + config CKB_EX_CN_PIN4_LCD_DATA13
- + 	bool "LCD_DATA13"
- + 	
- + config CKB_EX_CN_PIN4_A17
- + 	bool "A17"
- + 
- + config CKB_EX_CN_PIN4_EQEP1B_IN
- + 	bool "EQEP1B_IN"
- + 
- + config CKB_EX_CN_PIN4_MCASP0_FSR
- + 	bool "MCASP0_FSR"
- + 
- + config CKB_EX_CN_PIN4_MCAP0_AXR3
- + 	bool "MCAP0_AXR3"
- + 
- + config CKB_EX_CN_PIN2_PR1_MII0_RXER
- + 	bool "PR1_MII0_RXER"
- + 	
- + config CKB_EX_CN_PIN4_UART4_RTS
- + 	bool "UART4_RTS"
- + 	
- + config CKB_EX_CN_PIN4_OGPIO
- + 	bool "GPIO output (GPIO0_9)"
- + 
- + config CKB_EX_CN_PIN4_IGPIO
- + 	bool "GPIO input (GPIO0_9)"
- + 
- + endchoice
- + 
- + menu "Disable LCD support to enable Pin6 multiplex options"
- + 	depends on CKB_LCD_SUPPORT
- + endmenu
- + 
- + menu "Disable spidev to enable Pin6 multiplex options"
- + 	depends on !CKB_LCD_SUPPORT && CKB_EXTCN_SPIDEV_SPI1
- + endmenu
- + 
- + choice
- + 	prompt "Pin6 - Do not connect LCD board"
- + 	depends on !CKB_LCD_SUPPORT && !CKB_EXTCN_SPIDEV_SPI1
- + 	help
- + 	  The LCD board shoudn't be connected as this is multiplexed with TP IRQ.
- + 	  Yes, 'shoud not be connected'. 
- + 
- + config CKB_EX_CN_PIN6_MCASP0_AHCLKR
- + 	bool "MCASP0_AHCLKR"
- + 
- + config CKB_EX_CN_PIN6_EHRPWM0_SYNCI
- + 	bool "EHRPWM0_SYNCI"
- + 	
- + config CKB_EX_CN_PIN6_MCASP0_AXR2
- + 	bool "MCASP0_AXR2"
- + 
- + config CKB_EX_CN_PIN6_SPI1_CS0
- + 	bool "SPI1_CS0"
- + 
- + config CKB_EX_CN_PIN6_ECAP2_IN_PWM2_OUT
- + 	bool "ECAP2_IN_PWM2_OUT"
- + 	
- + config CKB_EX_CN_PIN6_PR1_PRU0_PRU_R30_3
- + 	bool "PR1_PRU0_PRU_R30_3"
- + 
- + config CKB_EX_CN_PIN6_PR1_PRU0_PRU_R31_3
- + 	bool "PR1_PRU0_PRU_R31_3"
- + 
- + config CKB_EX_CN_PIN6_OGPIO
- + 	bool "GPIO output (GPIO3_17)"
- + 
- + config CKB_EX_CN_PIN6_IGPIO
- + 	bool "GPIO input (GPIO3_17)"
- + 
- + endchoice
- + 
- + 
- + menu "Disable LCD support to enable Pin10 multiplex options"
- + 	depends on CKB_LCD_SUPPORT
- + endmenu
- + 
- + choice 
- + 	prompt "Pin10"
- + 	depends on !CKB_LCD_SUPPORT
- + 	help
- + 	 Choose multiplex options.
- + 	 
- + config CKB_EX_CN_PIN10_MCASP0_FSR
- + 	bool "MCASP0_FSR"
- + 
- + config CKB_EX_CN_PIN10_EQEP0B_IN
- + 	bool "EQEP0B_IN"
- + 
- + config CKB_EX_CN_PIN10_MCASP0_AXR3
- + 	bool "MCASP0_AXR3"
- + 
- + config CKB_EX_CN_PIN10_MCASP1_FSX
- + 	bool "MCASP1_FSX"
- + 
- + config CKB_EX_CN_PIN10_EMU2
- + 	bool "PIN10_EMU2"
- + 	
- + config CKB_EX_CN_PIN10_PR1_PRU0_PRU_R30_5
- + 	bool "PR1_PRU0_PRU_R30_5"
- + 	
- + config CKB_EX_CN_PIN10_PR1_PRU0_PRU_R31_5
- + 	bool "PR1_PRU0_PRU_R31_5"
- + 
- + config CKB_EX_CN_PIN10_OGPIO
- + 	bool "GPIO output (GPIO3_19)"
- + 
- + config CKB_EX_CN_PIN10_IGPIO
- + 	bool "GPIO intput (GPIO3_19)"
- + 
- + endchoice
- + 
- + # Pins 13~20, Pins 23, Pin 25 are used by NOR flash
- + # for now USED_BY_NOR_FLASH is used to mask this menuconfig option...
- + 
- + choice 
- + 	prompt "Pin13"
- + 	depends on USED_BY_NOR_FLASH
- + 	help
- + 	 Choose multiplex options.
- + 
- + config CKB_EX_CN_PIN13_AD1
- + 	bool "AD1"
- + 
- + config CKB_EX_CN_PIN13_MMC1_DAT1
- + 	bool "MMC1_DAT1"
- + 
- + config CKB_EX_CN_PIN13_OGPIO
- + 	bool "GPIO output (GPIO1_1)"
- + 
- + config CKB_EX_CN_PIN13_IGPIO
- + 	bool "GPIO input (GPIO1_1)"
- + 
- + endchoice
- + 
- + choice 
- + 	prompt "Pin14"
- + 	depends on USED_BY_NOR_FLASH
- + 	help
- + 	 Choose multiplex options.
- + 
- + config CKB_EX_CN_PIN14_AD0
- + 	bool "AD0"
- + 
- + config CKB_EX_CN_PIN14_MMC1_DAT0
- + 	bool "MMC1_DAT0"
- + 	
- + config CKB_EX_CN_PIN14_OGPIO
- + 	bool "GPIO output (GPIO1_0)"
- + 
- + config CKB_EX_CN_PIN14_IGPIO
- + 	bool "GPIO input (GPIO1_0)"
- + 
- + endchoice
- + 
- + choice 
- + 	prompt "Pin15"
- + 	depends on USED_BY_NOR_FLASH
- + 	help
- + 	 Choose multiplex options.
- + 
- + config CKB_EX_CN_PIN15_AD3
- + 	bool "AD3"
- + 
- + config CKB_EX_CN_PIN15_MMC1_DAT3
- + 	bool "MMC1_DAT3"
- + 	
- + config CKB_EX_CN_PIN15_OGPIO
- + 	bool "GPIO output (GPIO1_3)"
- + 
- + config CKB_EX_CN_PIN15_IGPIO
- + 	bool "GPIO input (GPIO1_3)"
- + 
- + endchoice
- + 
- + choice 
- + 	prompt "Pin16"
- + 	depends on USED_BY_NOR_FLASH
- + 	help
- + 	 Choose multiplex options.
- + 
- + config CKB_EX_CN_PIN16_AD2
- + 	bool "AD2"
- + 
- + config CKB_EX_CN_PIN16_MMC1_DAT2
- + 	bool "MMC1_DAT2"
- + 	
- + config CKB_EX_CN_PIN16_OGPIO
- + 	bool "GPIO output (GPIO1_2)"
- + 
- + config CKB_EX_CN_PIN16_IGPIO
- + 	bool "GPIO input (GPIO1_2)"
- + 
- + endchoice
- + 
- + choice 
- + 	prompt "Pin17"
- + 	depends on USED_BY_NOR_FLASH
- + 	help
- + 	 Choose multiplex options.
- + 
- + config CKB_EX_CN_PIN17_AD5
- + 	bool "AD5"
- + 
- + config CKB_EX_CN_PIN17_MMC1_DAT5
- + 	bool "MMC1_DAT5"
- + 	
- + config CKB_EX_CN_PIN17_OGPIO
- + 	bool "GPIO output (GPIO1_5)"
- + 
- + config CKB_EX_CN_PIN17_IGPIO
- + 	bool "GPIO input (GPIO1_5)"
- + 
- + endchoice
- + 
- + choice 
- + 	prompt "Pin18"
- + 	depends on USED_BY_NOR_FLASH
- + 	help
- + 	 Choose multiplex options.
- + 
- + config CKB_EX_CN_PIN18_AD4
- + 	bool "AD4"
- + 
- + config CKB_EX_CN_PIN18_MMC1_DAT4
- + 	bool "MMC1_DAT4"
- + 	
- + config CKB_EX_CN_PIN18_OGPIO
- + 	bool "GPIO output (GPIO1_4)"
- + 
- + config CKB_EX_CN_PIN18_IGPIO
- + 	bool "GPIO input (GPIO1_4)"
- + 
- + endchoice
- + 
- + choice 
- + 	prompt "Pin19"
- + 	depends on USED_BY_NOR_FLASH
- + 	help
- + 	 Choose multiplex options.
- + 
- + config CKB_EX_CN_PIN19_AD7
- + 	bool "AD7"
- + 
- + config CKB_EX_CN_PIN19_MMC1_DAT7
- + 	bool "MMC1_DAT7"
- + 	
- + config CKB_EX_CN_PIN19_OGPIO
- + 	bool "GPIO output (GPIO1_7)"
- + 
- + config CKB_EX_CN_PIN19_IGPIO
- + 	bool "GPIO input (GPIO1_7)"
- + 
- + endchoice
- + 
- + choice 
- + 	prompt "Pin20"
- + 	depends on USED_BY_NOR_FLASH
- + 	help
- + 	 Choose multiplex options.
- + 
- + config CKB_EX_CN_PIN20_AD6
- + 	bool "AD6"
- + 
- + config CKB_EX_CN_PIN20_MMC1_DAT6
- + 	bool "MMC1_DAT6"
- + 	
- + config CKB_EX_CN_PIN20_OGPIO
- + 	bool "GPIO output (GPIO1_6)"
- + 
- + config CKB_EX_CN_PIN20_IGPIO
- + 	bool "GPIO input (GPIO1_6)"
- + 
- + endchoice
- + 
- + menu "Disable Support GPMC CS1 mem to enable Pin21 multiplex options"
- + 	depends on SUPPORT_GPMC_CS1_MEM
- + endmenu
- + 
- + choice 
- + 	prompt "Pin21"
- + 	depends on !SUPPORT_GPMC_CS1_MEM
- + 	help
- + 	 Choose multiplex options.
- + 
- + config CKB_EX_CN_PIN21_GPMC_CSN1
- + 	bool "GPMC_CSN1"
- + 
- + config CKB_EX_CN_PIN21_GPMC_CLK
- + 	bool "GPMC_CLK"
- + 
- + config CKB_EX_CN_PIN21_MMC1_CLK
- + 	bool "MMC1_CLK"
- + 
- + config CKB_EX_CN_PIN21_PR1_EDIO_DATA_IN6
- + 	bool "PR1_EDIO_DATA_IN6"
- + 
- + config CKB_EX_CN_PIN21_PR1_EDIO_DATA_OUT6
- + 	bool "PR1_EDIO_DATA_OUT6"
- + 	
- + config CKB_EX_CN_PIN21_PR1_PRU1_PRU_R30_12
- + 	bool "PR1_PRU1_PRU_R30_12"
- + 
- + config CKB_EX_CN_PIN21_PR1_PRU1_PRU_R31_12
- + 	bool "PR1_PRU1_PRU_R31_12"
- + 
- + config CKB_EX_CN_PIN21_OGPIO
- + 	bool "GPIO output (GPIO1_30)"
- + 
- + config CKB_EX_CN_PIN21_IGPIO
- + 	bool "GPIO input (GPIO1_30)"
- + 
- + endchoice
- + 
- + menu "Disable on-board LED support to enable Pin22 multiplex options"
- + 	depends on SUPPORT_CKB_LED
- + endmenu
- + 
- + choice 
- + 	prompt "Pin22"
- + 	depends on !SUPPORT_CKB_LED
- + 	help
- + 	 Choose multiplex options.
- + 	 
- + config CKB_EX_CN_PIN22_XDMA_EVENT_INTR0
- + 	bool "XDMA_EVENT_INTR0"
- + 	
- + config CKB_EX_CN_PIN22_TIM4
- + 	bool "TIM4"
- + 
- + config CKB_EX_CN_PIN22_CLKOUT1
- + 	bool "CLKOUT1"
- + 	
- + config CKB_EX_CN_PIN22_SPI1_CS1
- + 	bool "SPI1_CS1"
- + 
- + config CKB_EX_CN_PIN22_PR1_PRU1_PRU_R31_16
- + 	bool "PR1_PRU1_PRU_R31_16"
- + 	
- + config CKB_EX_CN_PIN22_EMU2
- + 	bool "EMU2"
- + 		
- + config CKB_EX_CN_PIN22_OGPIO
- + 	bool "GPIO output (GPIO0_19)"
- + 
- + config CKB_EX_CN_PIN22_IGPIO
- + 	bool "GPIO input (GPIO0_19)"
- + 
- + endchoice
- + 
- + choice
- + 	prompt "Pin23"
- + 	depends on USED_BY_NOR_FLASH
- + 	help
- + 	 Choose multiplex options.
- + 	 
- + config CKB_EX_CN_PIN23_GPMC_WEN
- + 	bool "GPMC_WEN"
- + 
- + config CKB_EX_CN_PIN23_TIM6
- + 	bool "TIM6"
- + 
- + config CKB_EX_CN_PIN23_OGPIO
- + 	bool "GPIO output (GPIO2_4)"
- + 
- + config CKB_EX_CN_PIN23_IGPIO
- + 	bool "GPIO input (GPIO2_4)"
- + 
- + endchoice
- + 
- + menu "Disable on-board LED support to enable Pin24 multiplex options"
- + 	depends on SUPPORT_CKB_LED
- + endmenu
- + 
- + choice 
- + 	prompt "Pin24"
- + 	depends on !SUPPORT_CKB_LED
- + 	help
- + 	 Choose multiplex options.
- + 	 
- + config CKB_EX_CN_PIN24_XDMA_EVENT_INTR1
- + 	bool "XDMA_EVENT_INTR1"
- + 
- + config CKB_EX_CN_PIN24_TCLKIN
- + 	bool "TCLKIN"
- + 
- + config CKB_EX_CN_PIN24_CLKOUT2
- + 	bool "CLKOUT2"
- + 
- + config CKB_EX_CN_PIN24_TIM7
- + 	bool "TIM7"
- + 
- + config CKB_EX_CN_PIN24_PR1_PRU0_PRU_R31_16
- + 	bool "PR1_PRU0_PRU_R31_16"
- + 	
- + config CKB_EX_CN_PIN24_EMU3
- + 	bool "EMU3"
- + 
- + config CKB_EX_CN_PIN24_OGPIO
- + 	bool "GPIO output (GPIO0_20)"
- + 
- + config CKB_EX_CN_PIN24_IGPIO
- + 	bool "GPIO input (GPIO0_20)"
- + 
- + endchoice
- + 
- + choice
- + 	prompt "Pin25"
- + 	depends on USED_BY_NOR_FLASH
- + 	help
- + 	 Choose multiplex options.
- + 	 
- + config CKB_EX_CN_PIN25_GPMC_OEN_REN
- + 	bool "GPMC_OEN_REN"
- + 
- + config CKB_EX_CN_PIN25_TIM7
- + 	bool "TIM7"
- + 
- + config CKB_EX_CN_PIN25_OGPIO
- + 	bool "GPIO output (GPIO2_3)"
- + 
- + config CKB_EX_CN_PIN25_IGPIO
- + 	bool "GPIO input (GPIO2_3)"
- + 
- + endchoice
- + 
- + menu "Disable devices on Pin26 to enable Pin26 multiplex options"
- + 	depends on CKB_EXTCN_26_28
- + endmenu
- + 
- + choice 
- + 	prompt "Pin26"
- + 	depends on !CKB_EXTCN_26_28
- + 	help
- + 	  Choose multiplex options. 
- + 
- + config CKB_EX_CN_PIN26_UART0_CTSN
- + 	bool "UART0_CTSN"
- + 	
- + config CKB_EX_CN_PIN26_UART4_RXD
- + 	bool "UART4_RXD"
- + 	
- + config CKB_EX_CN_PIN26_DCAN1_TX
- + 	bool "DCAN1_TX"
- + 		  
- + config CKB_EX_CN_PIN26_I2C1_SDA
- + 	bool "I2C1_SDA"
- + 
- + config CKB_EX_CN_PIN26_SPI1_D0
- + 	bool "SPI1_D0"
- + 
- + config CKB_EX_CN_PIN26_TIM7
- + 	bool "TIM7"
- + 
- + config CKB_EX_CN_PIN26_PR1_EDC_SYNC0_OUT
- + 	bool "PR1_EDC_SYNC0_OUT"
- + 
- + config CKB_EX_CN_PIN26_OGPIO
- + 	bool "GPIO output (GPIO1_8)"
- + 
- + config CKB_EX_CN_PIN26_IGPIO
- + 	bool "GPIO input (GPIO1_8)"
- + 
- + endchoice
- + 
- + choice
- + 	prompt "Pin27"
- + 	help
- + 	 Choose multiplex options.
- + 	 
- + config CKB_EX_CN_PIN27_GPMC_ADVN_ALE
- + 	bool "GPMC_ADVN_ALE"
- + 
- + config CKB_EX_CN_PIN27_TIM4
- + 	bool "TIM4"
- + 
- + config CKB_EX_CN_PIN27_OGPIO
- + 	bool "GPIO output (GPIO2_2)"
- + 
- + config CKB_EX_CN_PIN27_IGPIO
- + 	bool "GPIO input (GPIO2_2)"
- + 
- + endchoice
- + 
- + menu "Disable devices on Pin28 to enable Pin28 multiplex options"
- + 	depends on CKB_EXTCN_26_28
- + endmenu
- + 
- + choice 
- + 	prompt "Pin28"
- + 	depends on !CKB_EXTCN_26_28
- + 	help
- + 	  Choose multiplex options. 
- + 
- + config CKB_EX_CN_PIN28_UART0_RTSN
- + 	bool "UART0_RTSN"
- + 
- + config CKB_EX_CN_PIN28_UART4_TXD
- + 	bool "UART4_TXD"
- + 	
- + config CKB_EX_CN_PIN28_DCAN1_RX
- + 	bool "DCAN1_RX"
- + 		  
- + config CKB_EX_CN_PIN28_I2C1_SCL
- + 	bool "I2C1_SCL"
- + 
- + config CKB_EX_CN_PIN28_SPI1_D1
- + 	bool "SPI1_D1"
- + 
- + config CKB_EX_CN_PIN28_SPI1_CS0
- + 	bool "SPI1_CS0"
- + 
- + config CKB_EX_CN_PIN28_PR1_EDC_SYNC1_OUT
- + 	bool "PR1_EDC_SYNC1_OUT"
- + 	
- + config CKB_EX_CN_PIN28_OGPIO
- + 	bool "GPIO output (GPIO1_9)"
- + 
- + config CKB_EX_CN_PIN28_IGPIO
- + 	bool "GPIO input (GPIO1_9)"
- + 
- + endchoice
- + 
- + menu "Disable CM-J100 WLAN card support to enable Pin29 multiplex options"
- + 	depends on SUPPORT_CMJ100
- + endmenu
- + 
- + choice
- + 	prompt "Pin29"
- + 	depends on !SUPPORT_CMJ100
- + 	help
- + 	 Choose multiplex options.
- + 	 
- + config CKB_EX_CN_PIN29_GPMC_A1
- + 	bool "GPMC_A1"
- + 
- + config CKB_EX_CN_PIN29_MII2_RXDV
- + 	bool "MII2_RXDV"
- + 
- + config CKB_EX_CN_PIN29_RGMII2_RCTL
- + 	bool "RGMII2_RCTL"
- + 		
- + config CKB_EX_CN_PIN29_MMC2_D0
- + 	bool "MMC2_D0"
- + 
- + config CKB_EX_CN_PIN29_GPMC_A17
- + 	bool "GPMC_A17"
- + 
- + config CKB_EX_CN_PIN29_PR1_MII1_TXD3
- + 	bool "PR1_MII1_TXD3"
- + 
- + config CKB_EX_CN_PIN29_EHRPWM0_SYNCO
- + 	bool "EHRPWM0_SYNCO"
- + 	
- + config CKB_EX_CN_PIN29_OGPIO
- + 	bool "GPIO output (GPIO1_17)"
- + 
- + config CKB_EX_CN_PIN29_IGPIO
- + 	bool "GPIO input (GPIO1_17)"
- + 
- + endchoice
- + 
- + choice 
- + 	prompt "Pin30"
- + 	help
- + 	  Choose multiplex options. 
- + 
- + config CKB_EX_CN_PIN30_ECAP0_IN_PWM0_OUT
- + 	bool "ECAP0_IN_PWM0_OUT"
- + 
- + config CKB_EX_CN_PIN30_UART3_TXD
- + 	bool "UART3_TXD"
- + 
- + config CKB_EX_CN_PIN30_SPI1_CS1
- + 	bool "SPI1_CS1"
- + 	
- + config CKB_EX_CN_PIN30_PR1_ECAP0_ECAP_CAPIN_APWM_O
- + 	bool "PR1_ECAP0_ECAP_CAPIN_APWM_O"
- + 
- + config CKB_EX_CN_PIN30_SPI1_SCK
- + 	bool "SPI1_SCK"
- + 
- + config CKB_EX_CN_PIN30_MMC0_SDWP
- + 	bool "MMC0_SDWP"
- + 	
- + config CKB_EX_CN_PIN30_XDMA_EVENT_INTR2
- + 	bool "XDMA_EVENT_INTR2"
- + 	
- + config CKB_EX_CN_PIN30_OGPIO
- + 	bool "GPIO output (GPIO0_7)"
- + 
- + config CKB_EX_CN_PIN30_IGPIO
- + 	bool "GPIO input (GPIO0_7)"
- + 
- + endchoice
- + 
- + menu "Disable LCD support to enable Pin31 multiplex options"
- + 	depends on CKB_LCD_SUPPORT
- + endmenu
- + 
- + menu "Disable spidev to enable Pin31 multiplex options"
- + 	depends on !CKB_LCD_SUPPORT && CKB_EXTCN_SPIDEV_SPI1
- + endmenu
- + 
- + choice 
- + 	prompt "Pin31"
- + 	depends on !CKB_LCD_SUPPORT && !CKB_EXTCN_SPIDEV_SPI1
- + 	help
- + 	  Choose multiplex options. 
- + 
- + config CKB_EX_CN_PIN31_MCASP0_AXR0
- + 	bool "MCASP0_AXR0"
- + 
- + config CKB_EX_CN_PIN31_EHRPWM0_TRIPZONE_INPUT
- + 	bool "EHRPWM0_TRIPZONE_INPUT"
- + 	
- + config CKB_EX_CN_PIN31_SPI1_D1
- + 	bool "SPI1_D1"
- + 	
- + config CKB_EX_CN_PIN31_MMC2_SDCD
- + 	bool "MMC2_SDCD"
- + 
- + config CKB_EX_CN_PIN31_PR1_PRU0_PRU_R30_2
- + 	bool "PR1_PRU0_PRU_R30_2"
- + 
- + config CKB_EX_CN_PIN31_PR1_PRU0_PRU_R31_2
- + 	bool "PR1_PRU0_PRU_R31_2"
- + 
- + config CKB_EX_CN_PIN31_OGPIO
- + 	bool "GPIO output (GPIO3_16)"
- + 
- + config CKB_EX_CN_PIN31_IGPIO
- + 	bool "GPIO input (GPIO3_16)"
- + 
- + endchoice
- + 
- + choice 
- + 	prompt "Pin33"
- + 	help
- + 	  Choose multiplex options. 
- + 
- + config CKB_EX_CN_PIN33_MCASP0_AXR1
- + 	bool "MCASP0_AXR1"
- + 
- + config CKB_EX_CN_PIN33_EQEP0_INDEX
- + 	bool "EQEP0_INDEX"
- + 
- + config CKB_EX_CN_PIN33_MCASP1_AXR0
- + 	bool "MCASP1_AXR0"
- + 
- + config CKB_EX_CN_PIN33_EMU3
- + 	bool "EMU3"
- + 	
- + config CKB_EX_CN_PIN33_PR1_PRU0_PRU_R30_6
- + 	bool "PR1_PRU0_PRU_R30_6"
- + 
- + config CKB_EX_CN_PIN33_PR1_PRU0_PRU_R31_6
- + 	bool "PR1_PRU0_PRU_R31_6"
- + 	
- + config CKB_EX_CN_PIN33_OGPIO
- + 	bool "GPIO output (GPIO3_20)"
- + 
- + config CKB_EX_CN_PIN33_IGPIO
- + 	bool "GPIO input (GPIO3_20)"
- + 
- + endchoice
- + 
- + choice 
- + 	prompt "Pin34"
- + 	help
- + 	  Choose multiplex options. 
- + 
- + config CKB_EX_CN_PIN34_MCASP0_AHCLKX
- + 	bool "MCASP0_AHCLKX"
- + 
- + config CKB_EX_CN_PIN34_EQEP0_STROBE
- + 	bool "EQEP0_STROBE"
- + 
- + config CKB_EX_CN_PIN34_MCASP0_AXR3
- + 	bool "MCASP0_AXR3"
- + 
- + config CKB_EX_CN_PIN34_MCASP1_AXR1
- + 	bool "MCASP1_AXR1"
- + 	
- + config CKB_EX_CN_PIN34_EMU4
- + 	bool "EMU4"
- + 
- + config CKB_EX_CN_PIN34_PR1_PRU0_PRU_R30_7
- + 	bool "PR1_PRU0_PRU_R30_7"
- + 	
- + config CKB_EX_CN_PIN34_PR1_PRU0_PRU_R31_7
- + 	bool "PR1_PRU0_PRU_R31_7"
- + 
- + config CKB_EX_CN_PIN34_OGPIO
- + 	bool "GPIO output (GPIO3_21)"
- + 
- + config CKB_EX_CN_PIN34_IGPIO
- + 	bool "GPIO input (GPIO3_21)"
- + 
- + endchoice
- + 
- + menu "Disable LCD support to enable Pin36 multiplex options"
- + 	depends on CKB_LCD_SUPPORT
- + endmenu
- + 
- + menu "Disable spidev to enable Pin36 multiplex options"
- + 	depends on !CKB_LCD_SUPPORT && CKB_EXTCN_SPIDEV_SPI1
- + endmenu
- + 
- + choice 
- + 	prompt "Pin36"
- + 	depends on !CKB_LCD_SUPPORT && !CKB_EXTCN_SPIDEV_SPI1
- + 	help
- + 	  Choose multiplex options. 
- + 
- + config CKB_EX_CN_PIN36_MCASP0_ACLKX
- + 	bool "MCASP0_ACLKX"
- + 
- + config CKB_EX_CN_PIN36_EHRPWM0A
- + 	bool "EHRPWM0A"
- + 
- + config CKB_EX_CN_PIN36_SPI1_SCLK
- + 	bool "SPI1_SCLK"
- + 	
- + config CKB_EX_CN_PIN36_MMC0_SDCD
- + 	bool "MMC0_SDCD"
- + 	
- + config CKB_EX_CN_PIN36_PR1_PRU0_PRU_R30_0
- + 	bool "PR1_PRU0_PRU_R30_0"
- + 
- + config CKB_EX_CN_PIN36_PR1_PRU0_PRU_R31_0
- + 	bool "PR1_PRU0_PRU_R31_0"
- + 
- + config CKB_EX_CN_PIN36_OGPIO
- + 	bool "GPIO output (GPIO3_14)"
- + 
- + config CKB_EX_CN_PIN36_IGPIO
- + 	bool "GPIO input (GPIO3_14)"
- + 
- + endchoice
- + 
- + menu "Disable LCD support to enable Pin38 multiplex options"
- + 	depends on CKB_LCD_SUPPORT
- + endmenu
- + 
- + menu "Disable spidev to enable Pin38 multiplex options"
- + 	depends on !CKB_LCD_SUPPORT && CKB_EXTCN_SPIDEV_SPI1
- + endmenu
- + 
- + choice 
- + 	prompt "Pin38"
- + 	depends on !CKB_LCD_SUPPORT && !CKB_EXTCN_SPIDEV_SPI1
- + 	help
- + 	  Choose multiplex options. 
- + 
- + config CKB_EX_CN_PIN38_MCASP0_FSX
- + 	bool "MCASP0_FSX"
- + 
- + config CKB_EX_CN_PIN38_EHRPWM0B
- + 	bool "EHRPWM0B"
- + 	
- + config CKB_EX_CN_PIN38_SPI1_D0
- + 	bool "SPI1_D0"
- + 	
- + config CKB_EX_CN_PIN38_MMC1_SDCD
- + 	bool "MMC1_SDCD"
- + 
- + config CKB_EX_CN_PIN38_PR1_PRU0_PRU_R30_1
- + 	bool "PR1_PRU0_PRU_R30_1"
- + 
- + config CKB_EX_CN_PIN38_PR1_PRU0_PRU_R31_1
- + 	bool "PR1_PRU0_PRU_R31_1"
- + 
- + config CKB_EX_CN_PIN38_OGPIO
- + 	bool "GPIO output (GPIO3_15)"
- + 
- + config CKB_EX_CN_PIN38_IGPIO
- + 	bool "GPIO input (GPIO3_15)"
- + 
- + endchoice
- + 
- + endmenu
- + 
- + menu "WLAN_CN multiplex options"
- + 	depends on MACH_CKB_3352
- + 
- + choice 
- + 	prompt "Pin24"
- + 	help
- + 	  Choose multiplex options. 
- + 
- + config CKB_WLAN_CN_PIN24_UART1_TXD
- + 	bool "UART1_TXD"
- + 
- + config CKB_WLAN_CN_PIN24_MMC2_SDWP
- + 	bool "MMC2_SDWP"
- + 
- + config CKB_WLAN_CN_PIN24_DCAN1_TX
- + 	bool "DCAN1_TX"
- + 
- + config CKB_WLAN_CN_PIN24_I2C1_SCL
- + 	bool "I2C1_SCL"
- + 
- + config CKB_WLAN_CN_PIN24_PR1_UART0_TXD
- + 	bool "PR1_UART0_TXD"
- + 
- + config CKB_WLAN_CN_PIN24_PR1_PRU0_PRU_R31_16
- + 	bool "PR1_PRU0_PRU_R31_16"
- + 	
- + config CKB_WLAN_CN_PIN24_OGPIO
- + 	bool "GPIO output (GPIO0_15)"
- + 
- + config CKB_WLAN_CN_PIN24_IGPIO
- + 	bool "GPIO input (GPIO0_15)"
- + 
- + endchoice
- + 
- + choice 
- + 	prompt "Pin26"
- + 	help
- + 	  Choose multiplex options. 
- + 
- + config CKB_WLAN_CN_PIN26_UART1_RXD
- + 	bool "UART1_RXD"
- + 
- + config CKB_WLAN_CN_PIN26_MMC1_SDWP
- + 	bool "MMC1_SDWP"
- + 
- + config CKB_WLAN_CN_PIN26_DCAN0_TX
- + 	bool "DCAN0_TX"
- + 
- + config CKB_WLAN_CN_PIN26_I2C1_SDA
- + 	bool "I2C1_SDA"
- + 
- + config CKB_WLAN_CN_PIN26_PR1_UART0_RXD
- + 	bool "PR1_UART0_RXD"
- + 
- + config CKB_WLAN_CN_PIN26_PR1_PRU1_PRU_R31_16
- + 	bool "PR1_PRU1_PRU_R31_16"
- + 	
- + config CKB_WLAN_CN_PIN26_OGPIO
- + 	bool "GPIO output (GPIO0_14)"
- + 
- + config CKB_WLAN_CN_PIN26_IGPIO
- + 	bool "GPIO input (GPIO0_14)"
- + 
- + endchoice
- + 
- + choice 
- + 	prompt "Pin28"
- + 	help
- + 	  Choose multiplex options. 
- + 
- + config CKB_WLAN_CN_PIN28_UART1_CTSN
- + 	bool "UART1_CTSN"
- + 
- + config CKB_WLAN_CN_PIN28_TIMER6
- + 	bool "TIMER6"
- + 
- + config CKB_WLAN_CN_PIN28_DCAN0_TX
- + 	bool "DCAN0_TX"
- + 
- + config CKB_WLAN_CN_PIN28_I2C2_SDA
- + 	bool "I2C2_SDA"
- + 	
- + config CKB_WLAN_CN_PIN28_SPI1_CS0
- + 	bool "SPI_CS0"
- + 
- + config CKB_WLAN_CN_PIN28_PR1_UART0_CTS_N
- + 	bool "PR1_UART0_CTS_N"
- + 
- + config CKB_WLAN_CN_PIN28_PR1_EDC_LATCH0_IN
- + 	bool "PR1_EDC_LATCH0_IN"
- + 	
- + config CKB_WLAN_CN_PIN28_OGPIO
- + 	bool "GPIO output (GPIO0_12)"
- + 
- + config CKB_WLAN_CN_PIN28_IGPIO
- + 	bool "GPIO input (GPIO0_12)"
- + 
- + endchoice
- + 
- + choice 
- + 	prompt "Pin30"
- + 	help
- + 	  Choose multiplex options. 
- + 
- + config CKB_WLAN_CN_PIN30_UART1_RTSN
- + 	bool "UART1_RTSN"
- + 
- + config CKB_WLAN_CN_PIN30_TIMER5
- + 	bool "TIMER5"
- + 
- + config CKB_WLAN_CN_PIN30_DCAN0_RX
- + 	bool "DCAN0_RX"
- + 
- + config CKB_WLAN_CN_PIN30_I2C2_SCL
- + 	bool "I2C2_SCL"
- + 	
- + config CKB_WLAN_CN_PIN30_SPI1_CS1
- + 	bool "SPI_CS1"
- + 
- + config CKB_WLAN_CN_PIN30_PR1_UART0_RTS_N
- + 	bool "PR1_UART0_RTS_N"
- + 
- + config CKB_WLAN_CN_PIN30_PR1_EDC_LATCH1_IN
- + 	bool "PR1_EDC_LATCH1_IN"
- + 	
- + config CKB_WLAN_CN_PIN30_OGPIO
- + 	bool "GPIO output (GPIO0_13)"
- + 
- + config CKB_WLAN_CN_PIN30_IGPIO
- + 	bool "GPIO input (GPIO0_13)"
- + 
- + endchoice
- + 
- + endmenu
- + 
- + config OMAP3_EDMA
- + 	bool "OMAP3 EDMA support"
- + 	default n
- + 	help
- + 	  Select this option if EDMA is used
- + 
- + config AM33XX_SMARTREFLEX
- + 	bool "AM33XX SmartReflex support"
- + 	depends on (SOC_OMAPAM33XX) && PM
- + 	help
- + 	  Say Y if you want to enable SmartReflex.
- + 
- + 	  SmartReflex can perform continuous dynamic voltage
- + 	  scaling around the nominal operating point voltage
- + 	  according to silicon characteristics and operating
- + 	  conditions. Enabling SmartReflex reduces active power
- + 	  consumption.
- + 
- + 	  Please note, that by default SmartReflex is enabled.
- +           To disable the automatic voltage compensation for
- +           vdd mpu and vdd core from user space, user must
- +           write 1 to /debug/smartreflex/autocomp.
- + 
- + 	  Optionally autocompensation can be disabled in the kernel
- + 	  by default during system init via the enable_on_init flag
- + 	  which an be passed as platform data to the smartreflex driver.
- + 
- + config OMAP_RESET_CLOCKS
- + 	bool "Reset unused clocks during boot"
- + 	help
- + 	  Say Y if you want to reset unused clocks during boot.
- + 	  This option saves power, but assumes all drivers are
- + 	  using the clock framework. Broken drivers that do not
- + 	  yet use clock framework may not work with this option.
- + 	  If you are booting from another operating system, you
- + 	  probably do not want this option enabled until your
- + 	  device drivers work properly.
- + 
- + config OMAP_MUX
- + 	bool "OMAP multiplexing support"
- + 	depends on ARCH_CKB
- + 	default y
- + 	help
- + 	  Pin multiplexing support for OMAP boards. If your bootloader
- + 	  sets the multiplexing correctly, say N. Otherwise, or if unsure,
- + 	  say Y.
- + 
- + config OMAP_MUX_DEBUG
- + 	bool "Multiplexing debug output"
- + 	depends on OMAP_MUX
- + 	help
- + 	  Makes the multiplexing functions print out a lot of debug info.
- + 	  This is useful if you want to find out the correct values of the
- + 	  multiplexing registers.
- + 
- + config OMAP_IOMMU_IVA2
- + 	bool
- + 
- + config OMAP_32K_TIMER
- + 	bool "Use 32KHz timer"
- + 	help
- + 	  Select this option if you want to enable the OMAP 32KHz timer.
- + 	  This timer saves power compared to the OMAP_MPU_TIMER, and has
- + 	  support for no tick during idle. The 32KHz timer provides less
- + 	  intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
- + 	  currently only available for OMAP16XX, 24XX, 34XX and OMAP4.
- + 
- + 
- + config OMAP_32K_TIMER_HZ
- + 	int "Kernel internal timer frequency for 32KHz timer"
- + 	range 32 1024
- + 	depends on OMAP_32K_TIMER
- + 	default "128"
- + 	help
- + 	  Kernel internal timer frequency should be a divisor of 32768,
- + 	  such as 64 or 128.
- + 
- + config CKB_SUSPEND_SUPPORT
- + 	bool "Support suspend (Not tested)"
- + 	depends on MACH_CKB_3352
- + 	depends on SUSPEND
- + 	default n
- + 	help
- + 	  This feature is still under development. 
- + 
- + 
- + config TI_PM_DISABLE_VT_SWITCH
- + 	bool "Disable PM Console Switch"
- + 	depends on CKB_SUSPEND_SUPPORT
- + 	default y
- + 	help
- + 	  This option disables the default PM VT switch behavior for TI devices.
- + 	  Some platforms hang during suspend due to a failed attempt to
- + 	  perform the VT switch.  The VT switch is unnecessary on many platforms.
- + 
- + endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/mailbox.c linux-3.2.1/arch/arm/mach-ckb_3352/mailbox.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/mailbox.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/mailbox.c	2014-05-15 13:25:13.931017353 +0900
- ***************
- *** 0 ****
- --- 1,432 ----
- + /*
- +  * Mailbox reservation modules for OMAP2/3
- +  *
- +  * Copyright (C) 2006-2009 Nokia Corporation
- +  * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
- +  *        and  Paul Mundt
- +  *
- +  * This file is subject to the terms and conditions of the GNU General Public
- +  * License.  See the file "COPYING" in the main directory of this archive
- +  * for more details.
- +  */
- + 
- + #include <linux/module.h>
- + #include <linux/clk.h>
- + #include <linux/err.h>
- + #include <linux/platform_device.h>
- + #include <linux/io.h>
- + #include <linux/pm_runtime.h>
- + #include <plat/mailbox.h>
- + #include <mach/irqs.h>
- + 
- + #define MAILBOX_REVISION		0x000
- + #define MAILBOX_MESSAGE(m)		(0x040 + 0x4 * (m))
- + #define MAILBOX_FIFOSTATUS(m)		(0x080 + 0x4 * (m))
- + #define MAILBOX_MSGSTATUS(m)		(0x0c0 + 0x4 * (m))
- + #define MAILBOX_IRQSTATUS(u)		(0x100 + 0x8 * (u))
- + #define MAILBOX_IRQENABLE(u)		(0x104 + 0x8 * (u))
- + 
- + #define OMAP4_MAILBOX_IRQSTATUS(u)	(0x104 + 0x10 * (u))
- + #define OMAP4_MAILBOX_IRQENABLE(u)	(0x108 + 0x10 * (u))
- + #define OMAP4_MAILBOX_IRQENABLE_CLR(u)	(0x10c + 0x10 * (u))
- + 
- + #define MAILBOX_IRQ_NEWMSG(m)		(1 << (2 * (m)))
- + #define MAILBOX_IRQ_NOTFULL(m)		(1 << (2 * (m) + 1))
- + 
- + /* TODO: This can and should be based on #users and #sub-modules */
- + #define MBOX_REG_SIZE			0x120
- + 
- + #define OMAP4_MBOX_REG_SIZE		0x130
- + 
- + #define AM33XX_MBOX_REG_SIZE		0x140
- + 
- + #define MBOX_NR_REGS			(MBOX_REG_SIZE / sizeof(u32))
- + #define OMAP4_MBOX_NR_REGS		(OMAP4_MBOX_REG_SIZE / sizeof(u32))
- + #define AM33XX_MBOX_NR_REGS		(AM33XX_MBOX_REG_SIZE / sizeof(u32))
- + 
- + static void __iomem *mbox_base;
- + 
- + struct omap_mbox2_fifo {
- + 	unsigned long msg;
- + 	unsigned long fifo_stat;
- + 	unsigned long msg_stat;
- + };
- + 
- + struct omap_mbox2_priv {
- + 	struct omap_mbox2_fifo tx_fifo;
- + 	struct omap_mbox2_fifo rx_fifo;
- + 	unsigned long irqenable;
- + 	unsigned long irqstatus;
- + 	u32 newmsg_bit;
- + 	u32 notfull_bit;
- + 	u32 ctx[OMAP4_MBOX_NR_REGS];
- + 	unsigned long irqdisable;
- + };
- + 
- + static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
- + 				  omap_mbox_type_t irq);
- + 
- + static inline unsigned int mbox_read_reg(size_t ofs)
- + {
- + 	return __raw_readl(mbox_base + ofs);
- + }
- + 
- + static inline void mbox_write_reg(u32 val, size_t ofs)
- + {
- + 	__raw_writel(val, mbox_base + ofs);
- + }
- + 
- + /* Mailbox H/W preparations */
- + static int omap2_mbox_startup(struct omap_mbox *mbox)
- + {
- + 	u32 l;
- + 
- + 	pm_runtime_enable(mbox->dev->parent);
- + 	pm_runtime_get_sync(mbox->dev->parent);
- + 
- + 	l = mbox_read_reg(MAILBOX_REVISION);
- + 	pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
- + 
- + 	omap2_mbox_enable_irq(mbox, IRQ_RX);
- + 
- + 	return 0;
- + }
- + 
- + static void omap2_mbox_shutdown(struct omap_mbox *mbox)
- + {
- + 	pm_runtime_put_sync(mbox->dev->parent);
- + 	pm_runtime_disable(mbox->dev->parent);
- + }
- + 
- + /* Mailbox FIFO handle functions */
- + static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
- + {
- + 	struct omap_mbox2_fifo *fifo =
- + 		&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
- + 	return (mbox_msg_t) mbox_read_reg(fifo->msg);
- + }
- + 
- + static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
- + {
- + 	struct omap_mbox2_fifo *fifo =
- + 		&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
- + 	mbox_write_reg(msg, fifo->msg);
- + }
- + 
- + static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
- + {
- + 	struct omap_mbox2_fifo *fifo =
- + 		&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
- + 	return (mbox_read_reg(fifo->msg_stat) == 0);
- + }
- + 
- + static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
- + {
- + 	struct omap_mbox2_fifo *fifo =
- + 		&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
- + 	return mbox_read_reg(fifo->fifo_stat);
- + }
- + 
- + static int omap2_mbox_fifo_needs_flush(struct omap_mbox *mbox)
- + {
- + 	struct omap_mbox2_fifo *fifo =
- + 		&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
- + 	return (mbox_read_reg(fifo->msg_stat) == 0);
- + }
- + 
- + static mbox_msg_t omap2_mbox_fifo_readback(struct omap_mbox *mbox)
- + {
- + 	struct omap_mbox2_fifo *fifo =
- + 		&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
- + 	return (mbox_msg_t) mbox_read_reg(fifo->msg);
- + }
- + 
- + /* Mailbox IRQ handle functions */
- + static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
- + 		omap_mbox_type_t irq)
- + {
- + 	struct omap_mbox2_priv *p = mbox->priv;
- + 	u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
- + 
- + 	l = mbox_read_reg(p->irqenable);
- + 	l |= bit;
- + 	mbox_write_reg(l, p->irqenable);
- + }
- + 
- + static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
- + 		omap_mbox_type_t irq)
- + {
- + 	struct omap_mbox2_priv *p = mbox->priv;
- + 	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
- + 
- + 	if (!cpu_is_omap44xx() && !cpu_is_am33xx())
- + 		bit = mbox_read_reg(p->irqdisable) & ~bit;
- + 
- + 	mbox_write_reg(bit, p->irqdisable);
- + }
- + 
- + static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
- + 		omap_mbox_type_t irq)
- + {
- + 	struct omap_mbox2_priv *p = mbox->priv;
- + 	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
- + 
- + 	mbox_write_reg(bit, p->irqstatus);
- + 
- + 	/* Flush posted write for irq status to avoid spurious interrupts */
- + 	mbox_read_reg(p->irqstatus);
- + }
- + 
- + static int omap2_mbox_is_irq(struct omap_mbox *mbox,
- + 		omap_mbox_type_t irq)
- + {
- + 	struct omap_mbox2_priv *p = mbox->priv;
- + 	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
- + 	u32 enable = mbox_read_reg(p->irqenable);
- + 	u32 status = mbox_read_reg(p->irqstatus);
- + 
- + 	return (int)(enable & status & bit);
- + }
- + 
- + static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
- + {
- + 	int i;
- + 	struct omap_mbox2_priv *p = mbox->priv;
- + 	int nr_regs;
- + 	if (cpu_is_omap44xx())
- + 		nr_regs = OMAP4_MBOX_NR_REGS;
- + 	else
- + 		nr_regs = MBOX_NR_REGS;
- + 	for (i = 0; i < nr_regs; i++) {
- + 		p->ctx[i] = mbox_read_reg(i * sizeof(u32));
- + 
- + 		dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
- + 			i, p->ctx[i]);
- + 	}
- + }
- + 
- + static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
- + {
- + 	int i;
- + 	struct omap_mbox2_priv *p = mbox->priv;
- + 	int nr_regs;
- + 	if (cpu_is_omap44xx())
- + 		nr_regs = OMAP4_MBOX_NR_REGS;
- + 	else
- + 		nr_regs = MBOX_NR_REGS;
- + 	for (i = 0; i < nr_regs; i++) {
- + 		mbox_write_reg(p->ctx[i], i * sizeof(u32));
- + 
- + 		dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
- + 			i, p->ctx[i]);
- + 	}
- + }
- + 
- + static struct omap_mbox_ops omap2_mbox_ops = {
- + 	.type			= OMAP_MBOX_TYPE2,
- + 	.startup		= omap2_mbox_startup,
- + 	.shutdown		= omap2_mbox_shutdown,
- + 	.fifo_read		= omap2_mbox_fifo_read,
- + 	.fifo_write		= omap2_mbox_fifo_write,
- + 	.fifo_empty		= omap2_mbox_fifo_empty,
- + 	.fifo_full		= omap2_mbox_fifo_full,
- + 	.fifo_needs_flush	= omap2_mbox_fifo_needs_flush,
- + 	.fifo_readback		= omap2_mbox_fifo_readback,
- + 	.enable_irq		= omap2_mbox_enable_irq,
- + 	.disable_irq		= omap2_mbox_disable_irq,
- + 	.ack_irq		= omap2_mbox_ack_irq,
- + 	.is_irq			= omap2_mbox_is_irq,
- + 	.save_ctx		= omap2_mbox_save_ctx,
- + 	.restore_ctx		= omap2_mbox_restore_ctx,
- + };
- + 
- + /*
- +  * MAILBOX 0: ARM -> DSP,
- +  * MAILBOX 1: ARM <- DSP.
- +  * MAILBOX 2: ARM -> IVA,
- +  * MAILBOX 3: ARM <- IVA.
- +  */
- + 
- + /* FIXME: the following structs should be filled automatically by the user id */
- + 
- + /* DSP */
- + static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
- + 	.tx_fifo = {
- + 		.msg		= MAILBOX_MESSAGE(0),
- + 		.fifo_stat	= MAILBOX_FIFOSTATUS(0),
- + 	},
- + 	.rx_fifo = {
- + 		.msg		= MAILBOX_MESSAGE(1),
- + 		.msg_stat	= MAILBOX_MSGSTATUS(1),
- + 	},
- + 	.irqenable	= MAILBOX_IRQENABLE(0),
- + 	.irqstatus	= MAILBOX_IRQSTATUS(0),
- + 	.notfull_bit	= MAILBOX_IRQ_NOTFULL(0),
- + 	.newmsg_bit	= MAILBOX_IRQ_NEWMSG(1),
- + 	.irqdisable	= MAILBOX_IRQENABLE(0),
- + };
- + 
- + struct omap_mbox mbox_dsp_info = {
- + 	.name	= "dsp",
- + 	.ops	= &omap2_mbox_ops,
- + 	.priv	= &omap2_mbox_dsp_priv,
- + };
- + 
- + struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL };
- + 
- + /* IVA */
- + static struct omap_mbox2_priv omap2_mbox_iva_priv = {
- + 	.tx_fifo = {
- + 		.msg		= MAILBOX_MESSAGE(2),
- + 		.fifo_stat	= MAILBOX_FIFOSTATUS(2),
- + 	},
- + 	.rx_fifo = {
- + 		.msg		= MAILBOX_MESSAGE(3),
- + 		.msg_stat	= MAILBOX_MSGSTATUS(3),
- + 	},
- + 	.irqenable	= MAILBOX_IRQENABLE(3),
- + 	.irqstatus	= MAILBOX_IRQSTATUS(3),
- + 	.notfull_bit	= MAILBOX_IRQ_NOTFULL(2),
- + 	.newmsg_bit	= MAILBOX_IRQ_NEWMSG(3),
- + 	.irqdisable	= MAILBOX_IRQENABLE(3),
- + };
- + 
- + static struct omap_mbox mbox_iva_info = {
- + 	.name	= "iva",
- + 	.ops	= &omap2_mbox_ops,
- + 	.priv	= &omap2_mbox_iva_priv,
- + };
- + 
- + struct omap_mbox *omap2_mboxes[] = { &mbox_dsp_info, &mbox_iva_info, NULL };
- + 
- + /* A8 -> Wakeup-M3 */
- + static struct omap_mbox2_priv omap2_mbox_m3_priv = {
- + 	.tx_fifo = {
- + 		.msg		= MAILBOX_MESSAGE(0),
- + 		.fifo_stat	= MAILBOX_FIFOSTATUS(0),
- + 		.msg_stat	= MAILBOX_MSGSTATUS(0),
- + 	},
- + 	/* TODO: No M3->A8 so this needs to be removed */
- + 	.rx_fifo = {
- + 		.msg		= MAILBOX_MESSAGE(1),
- + 		.msg_stat	= MAILBOX_MSGSTATUS(1),
- + 	},
- + 	.irqenable	= OMAP4_MAILBOX_IRQENABLE(3),
- + 	.irqstatus	= OMAP4_MAILBOX_IRQSTATUS(3),
- + 	.notfull_bit	= MAILBOX_IRQ_NOTFULL(0),
- + 	.newmsg_bit	= MAILBOX_IRQ_NEWMSG(0),
- + 	.irqdisable	= OMAP4_MAILBOX_IRQENABLE_CLR(3),
- + };
- + 
- + struct omap_mbox wkup_m3_info = {
- + 	.name	= "wkup_m3",
- + 	.ops	= &omap2_mbox_ops,
- + 	.priv	= &omap2_mbox_m3_priv,
- + };
- + 
- + struct omap_mbox *am33xx_mboxes[] = { &wkup_m3_info, NULL };
- + 
- + /* OMAP4 */
- + static struct omap_mbox2_priv omap2_mbox_1_priv = {
- + 	.tx_fifo = {
- + 		.msg		= MAILBOX_MESSAGE(0),
- + 		.fifo_stat	= MAILBOX_FIFOSTATUS(0),
- + 	},
- + 	.rx_fifo = {
- + 		.msg		= MAILBOX_MESSAGE(1),
- + 		.msg_stat	= MAILBOX_MSGSTATUS(1),
- + 	},
- + 	.irqenable	= OMAP4_MAILBOX_IRQENABLE(0),
- + 	.irqstatus	= OMAP4_MAILBOX_IRQSTATUS(0),
- + 	.notfull_bit	= MAILBOX_IRQ_NOTFULL(0),
- + 	.newmsg_bit	= MAILBOX_IRQ_NEWMSG(1),
- + 	.irqdisable	= OMAP4_MAILBOX_IRQENABLE_CLR(0),
- + };
- + 
- + struct omap_mbox mbox_1_info = {
- + 	.name	= "mailbox-1",
- + 	.ops	= &omap2_mbox_ops,
- + 	.priv	= &omap2_mbox_1_priv,
- + };
- + 
- + static struct omap_mbox2_priv omap2_mbox_2_priv = {
- + 	.tx_fifo = {
- + 		.msg		= MAILBOX_MESSAGE(3),
- + 		.fifo_stat	= MAILBOX_FIFOSTATUS(3),
- + 	},
- + 	.rx_fifo = {
- + 		.msg		= MAILBOX_MESSAGE(2),
- + 		.msg_stat	= MAILBOX_MSGSTATUS(2),
- + 	},
- + 	.irqenable	= OMAP4_MAILBOX_IRQENABLE(0),
- + 	.irqstatus	= OMAP4_MAILBOX_IRQSTATUS(0),
- + 	.notfull_bit	= MAILBOX_IRQ_NOTFULL(3),
- + 	.newmsg_bit	= MAILBOX_IRQ_NEWMSG(2),
- + 	.irqdisable     = OMAP4_MAILBOX_IRQENABLE_CLR(0),
- + };
- + 
- + struct omap_mbox mbox_2_info = {
- + 	.name	= "mailbox-2",
- + 	.ops	= &omap2_mbox_ops,
- + 	.priv	= &omap2_mbox_2_priv,
- + };
- + 
- + struct omap_mbox *omap4_mboxes[] = { &mbox_1_info, &mbox_2_info, NULL };
- + 
- + static int __devinit omap2_mbox_probe(struct platform_device *pdev)
- + {
- + 	struct resource *mem;
- + 	int ret;
- + 	struct omap_mbox **list;
- + 
- + 	list = am33xx_mboxes;
- + 
- + 	list[0]->irq = platform_get_irq(pdev, 0);
- + 	
- + 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- + 	mbox_base = ioremap(mem->start, resource_size(mem));
- + 	if (!mbox_base)
- + 		return -ENOMEM;
- + 
- + 	ret = omap_mbox_register(&pdev->dev, list);
- + 	if (ret) {
- + 		iounmap(mbox_base);
- + 		return ret;
- + 	}
- + 
- + 	return 0;
- + }
- + 
- + static int __devexit omap2_mbox_remove(struct platform_device *pdev)
- + {
- + 	omap_mbox_unregister();
- + 	iounmap(mbox_base);
- + 	return 0;
- + }
- + 
- + static struct platform_driver omap2_mbox_driver = {
- + 	.probe = omap2_mbox_probe,
- + 	.remove = __devexit_p(omap2_mbox_remove),
- + 	.driver = {
- + 		.name = "omap-mailbox",
- + 	},
- + };
- + 
- + static int __init omap2_mbox_init(void)
- + {
- + 	return platform_driver_register(&omap2_mbox_driver);
- + }
- + 
- + static void __exit omap2_mbox_exit(void)
- + {
- + 	platform_driver_unregister(&omap2_mbox_driver);
- + }
- + 
- + device_initcall(omap2_mbox_init);
- + module_exit(omap2_mbox_exit);
- + 
- + MODULE_LICENSE("GPL v2");
- + MODULE_DESCRIPTION("omap mailbox: omap2/3/4 architecture specific functions");
- + MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>");
- + MODULE_AUTHOR("Paul Mundt");
- + MODULE_ALIAS("platform:omap2-mailbox");
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/Makefile linux-3.2.1/arch/arm/mach-ckb_3352/Makefile
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/Makefile	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/Makefile	2014-05-15 13:25:13.934979913 +0900
- ***************
- *** 0 ****
- --- 1,117 ----
- + #
- + # Makefile for the linux kernel.
- + #
- + 
- + # Common support
- + obj-y := io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
- + 	 common.o gpio.o dma.o wd_timer.o display.o
- + 
- + omap-2-3-common				= irq.o sdrc.o
- + hwmod-common				= omap_hwmod.o \
- + 					  omap_hwmod_common_data.o
- + clock-common				= clock.o clock_common_data.o \
- + 					  clkt_dpll.o clkt_clksel.o
- + 
- + obj-$(CONFIG_MACH_CKB_3352) += $(omap-2-3-common) $(hwmod-common)
- + 
- + # SMP support ONLY available for OMAP4
- + obj-$(CONFIG_HOTPLUG_CPU)		+= omap-hotplug.o
- + 
- + plus_sec := $(call as-instr,.arch_extension sec,+sec)
- + AFLAGS_omap-headsmp.o			:=-Wa,-march=armv7-a$(plus_sec)
- + AFLAGS_omap-smc.o			:=-Wa,-march=armv7-a$(plus_sec)
- + 
- + # Functions loaded to SRAM
- + obj-$(CONFIG_MACH_CKB_3352)		+= sram34xx.o
- + 
- + obj-$(CONFIG_PM_DEBUG)			+= pm-debug.o
- + 
- + AFLAGS_sram242x.o			:=-Wa,-march=armv6
- + AFLAGS_sram243x.o			:=-Wa,-march=armv6
- + AFLAGS_sram34xx.o			:=-Wa,-march=armv7-a
- + 
- + # Pin multiplexing
- + obj-$(CONFIG_MACH_CKB_3352)           += mux33xx.o
- + 
- + obj-$(CONFIG_MACH_CKB_3352)		+= mailbox.o
- + 
- + # OPP table initialization
- + ifeq ($(CONFIG_PM_OPP),y)
- + obj-y					+= opp.o
- + obj-$(CONFIG_MACH_CKB_3352)		+= opp3xxx_data.o
- + endif
- + 
- + # Power Management
- + ifeq ($(CONFIG_PM),y)
- + 					   
- + obj-$(CONFIG_SOC_OMAPAM33XX)		+= cpuidle33xx.o pm33xx.o \
- + 					   sleep33xx.o
- + 
- + obj-$(CONFIG_AM33XX_SMARTREFLEX)        += am33xx-smartreflex-class2.o
- + 
- + AFLAGS_sleep33xx.o			:=-Wa,-march=armv7-a$(plus_sec)
- + 
- + ifeq ($(CONFIG_PM_VERBOSE),y)
- + CFLAGS_pm_bus.o				+= -DDEBUG
- + endif
- + 
- + endif
- + 
- + # PRCM
- + obj-$(CONFIG_MACH_CKB_3352)		+=  prcm.o prm2xxx_3xxx.o vc3xxx_data.o vp3xxx_data.o
- + obj-$(CONFIG_SOC_OMAPAM33XX)		+= cminst44xx.o
- + 
- + # XXX The presence of cm2xxx_3xxx.o on the line below is temporary and
- + # will be removed once the OMAP4 part of the codebase is converted to
- + # use OMAP4-specific PRCM functions.
- + 
- + # OMAP voltage domains
- + voltagedomain-common			:= voltage.o vc.o vp.o
- + obj-$(CONFIG_MACH_CKB_3352)		+= $(voltagedomain-common) \
- + 					   voltagedomains3xxx_data.o
- + obj-$(CONFIG_SOC_OMAPAM33XX)		+= $(voltagedomain-common) \
- + 					   voltagedomains33xx_data.o
- + 
- + # OMAP powerdomain framework
- + powerdomain-common			+= powerdomain.o powerdomain-common.o
- + obj-$(CONFIG_MACH_CKB_3352)		+= $(powerdomain-common) \
- + 					   powerdomains3xxx_data.o \
- + 					   powerdomains2xxx_3xxx_data.o
- + obj-$(CONFIG_SOC_OMAPAM33XX)		+= prminst44xx.o \
- + 					   powerdomain44xx.o \
- + 					   powerdomains33xx_data.o
- + 
- + # PRCM clockdomain control
- + obj-$(CONFIG_MACH_CKB_3352)		+= clockdomain.o
- + obj-$(CONFIG_SOC_OMAPAM33XX)		+= clockdomain44xx.o \
- + 					   clockdomains33xx_data.o
- + 
- + # Clock framework
- + obj-$(CONFIG_MACH_CKB_3352)		+= $(clock-common) dpll3xxx.o clock33xx_data.o
- + 
- + # hwmod data
- + obj-$(CONFIG_MACH_CKB_3352)		+= omap_hwmod_2xxx_3xxx_ipblock_data.o \
- + 					   
- + 					  
- + obj-$(CONFIG_SOC_OMAPAM33XX)		+= omap_hwmod_33xx_data.o
- + 
- + # L3 interconnect
- + obj-$(CONFIG_MACH_CKB_3352)		+= omap_l3_smx.o
- + 
- + i2c-omap-$(CONFIG_I2C_OMAP)		:= i2c.o
- + obj-y					+= $(i2c-omap-m) $(i2c-omap-y)
- + 
- + # Specific board support
- + obj-y				+= board-ckb-3352.o
- + 
- + # Platform specific device init code
- + 
- + omap-hsmmc-$(CONFIG_MMC_OMAP_HS)	:= hsmmc.o
- + obj-y					+= $(omap-hsmmc-m) $(omap-hsmmc-y)
- + 
- + 
- + obj-y					+= usb-musb.o
- + obj-y					+= omap_phy_internal.o
- + 
- + dobj-y					+= usb-host.o
- + 
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/Makefile.boot linux-3.2.1/arch/arm/mach-ckb_3352/Makefile.boot
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/Makefile.boot	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/Makefile.boot	2014-05-15 13:25:13.934979913 +0900
- ***************
- *** 0 ****
- --- 1,3 ----
- +   zreladdr-y		+= 0x80008000
- + params_phys-y		:= 0x80000100
- + initrd_phys-y		:= 0x80800000
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/mux33xx.c linux-3.2.1/arch/arm/mach-ckb_3352/mux33xx.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/mux33xx.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/mux33xx.c	2014-05-15 13:25:13.939257527 +0900
- ***************
- *** 0 ****
- --- 1,1235 ----
- + /*
- +  * AM33XX mux data
- +  *
- +  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- +  *
- +  * Derived from: arch/arm/mach-omap2/mux34xx.c Original copyright follows:
- +  *
- +  * Copyright (C) 2009 Nokia
- +  * Copyright (C) 2009 Texas Instruments
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #include <linux/module.h>
- + #include <linux/init.h>
- + #include <linux/io.h>
- + #include <linux/debugfs.h>
- + #include <linux/slab.h>
- + #include <linux/seq_file.h>
- + #include <linux/uaccess.h>
- + #include <linux/gpio.h>
- + #include <linux/interrupt.h>
- + #include <linux/suspend.h>
- + 
- + #include "cm33xx.h"
- + #include "control.h"
- + #include "mux.h"
- + 
- + #ifdef CONFIG_OMAP_MUX
- + 
- + #define _AM33XX_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7)		\
- + {									\
- + 	.reg_offset	= (AM33XX_CONTROL_PADCONF_##M0##_OFFSET),	\
- + 	.gpio		= (g),						\
- + 	.muxnames	= { m0, m1, m2, m3, m4, m5, m6, m7 },		\
- + }
- + 
- + /* AM33XX pin mux super set */
- + static struct omap_mux am33xx_muxmodes[] = {
- + 	_AM33XX_MUXENTRY(GPMC_AD0, 0,
- + 		"gpmc_ad0", "mmc1_dat0", NULL, NULL,
- + 		NULL, NULL, NULL, "gpio1_0"),
- + 	_AM33XX_MUXENTRY(GPMC_AD1, 0,
- + 		"gpmc_ad1", "mmc1_dat1", NULL, NULL,
- + 		NULL, NULL, NULL, "gpio1_1"),
- + 	_AM33XX_MUXENTRY(GPMC_AD2, 0,
- + 		"gpmc_ad2", "mmc1_dat2", NULL, NULL,
- + 		NULL, NULL, NULL, "gpio1_2"),
- + 	_AM33XX_MUXENTRY(GPMC_AD3, 0,
- + 		"gpmc_ad3", "mmc1_dat3", NULL, NULL,
- + 		NULL, NULL, NULL, "gpio1_3"),
- + 	_AM33XX_MUXENTRY(GPMC_AD4, 0,
- + 		"gpmc_ad4", "mmc1_dat4", NULL, NULL,
- + 		NULL, NULL, NULL, "gpio1_4"),
- + 	_AM33XX_MUXENTRY(GPMC_AD5, 0,
- + 		"gpmc_ad5", "mmc1_dat5", NULL, NULL,
- + 		NULL, NULL, NULL, "gpio1_5"),
- + 	_AM33XX_MUXENTRY(GPMC_AD6, 0,
- + 		"gpmc_ad6", "mmc1_dat6", NULL, NULL,
- + 		NULL, NULL, NULL, "gpio1_6"),
- + 	_AM33XX_MUXENTRY(GPMC_AD7, 0,
- + 		"gpmc_ad7", "mmc1_dat7", NULL, NULL,
- + 		NULL, NULL, NULL, "gpio1_7"),
- + 	_AM33XX_MUXENTRY(GPMC_AD8, 0,
- + 		"gpmc_ad8", "lcd_data16", "mmc1_dat0", "mmc2_dat4",
- + 		NULL, NULL, NULL, "gpio0_22"),
- + 	_AM33XX_MUXENTRY(GPMC_AD9, 0,
- + 		"gpmc_ad9", "lcd_data17", "mmc1_dat1", "mmc2_dat5",
- + 		"ehrpwm2B", NULL, NULL, "gpio0_23"),
- + 	_AM33XX_MUXENTRY(GPMC_AD10, 0,
- + 		"gpmc_ad10", "lcd_data18", "mmc1_dat2", "mmc2_dat6",
- + 		NULL, NULL, NULL, "gpio0_26"),
- + 	_AM33XX_MUXENTRY(GPMC_AD11, 0,
- + 		"gpmc_ad11", "lcd_data19", "mmc1_dat3", "mmc2_dat7",
- + 		NULL, NULL, NULL, "gpio0_27"),
- + 	_AM33XX_MUXENTRY(GPMC_AD12, 0,
- + 		"gpmc_ad12", "lcd_data20", "mmc1_dat4", "mmc2_dat0",
- + 		NULL, NULL, NULL, "gpio1_12"),
- + 	_AM33XX_MUXENTRY(GPMC_AD13, 0,
- + 		"gpmc_ad13", "lcd_data21", "mmc1_dat5", "mmc2_dat1",
- + 		NULL, NULL, NULL, "gpio1_13"),
- + 	_AM33XX_MUXENTRY(GPMC_AD14, 0,
- + 		"gpmc_ad14", "lcd_data22", "mmc1_dat6", "mmc2_dat2",
- + 		NULL, NULL, NULL, "gpio1_14"),
- + 	_AM33XX_MUXENTRY(GPMC_AD15, 0,
- + 		"gpmc_ad15", "lcd_data23", "mmc1_dat7", "mmc2_dat3",
- + 		NULL, NULL, NULL, "gpio1_15"),
- + 	_AM33XX_MUXENTRY(GPMC_A0, 0,
- + 		"gpmc_a0", "mii2_txen", "rgmii2_tctl", "rmii2_txen",
- + 		NULL, NULL, NULL, "gpio1_16"),
- + 	_AM33XX_MUXENTRY(GPMC_A1, 0,
- + 		"gpmc_a1", "mii2_rxdv", "rgmii2_rctl", "mmc2_dat0",
- + 		"gpmc_a17", "pr1_mii1_txd3", "ehrpwm0_synco", "gpio1_17"),
- + 	_AM33XX_MUXENTRY(GPMC_A2, 0,
- + 		"gpmc_a2", "mii2_txd3", "rgmii2_td3", "mmc2_dat1",
- + 		NULL, NULL, NULL, "gpio1_18"),
- + 	_AM33XX_MUXENTRY(GPMC_A3, 0,
- + 		"gpmc_a3", "mii2_txd2", "rgmii2_td2", "mmc2_dat2",
- + 		NULL, NULL, NULL, "gpio1_19"),
- + 	_AM33XX_MUXENTRY(GPMC_A4, 0,
- + 		"gpmc_a4", "mii2_txd1", "rgmii2_td1", "rmii2_txd1",
- + 		"gpmc_a20", NULL, NULL, "gpio1_20"),
- + 	_AM33XX_MUXENTRY(GPMC_A5, 0,
- + 		"gpmc_a5", "mii2_txd0", "rgmii2_td0", "rmii2_txd0",
- + 		"gpmc_a21", NULL, NULL, "gpio1_21"),
- + 	_AM33XX_MUXENTRY(GPMC_A6, 0,
- + 		"gpmc_a6", "mii2_txclk", "rgmii2_tclk", "mmc2_dat4",
- + 		"gpmc_a22", NULL, NULL, "gpio1_22"),
- + 	_AM33XX_MUXENTRY(GPMC_A7, 0,
- + 		"gpmc_a7", "mii2_rxclk", "rgmii2_rclk", "mmc2_dat5",
- + 		NULL, NULL, NULL, "gpio1_23"),
- + 	_AM33XX_MUXENTRY(GPMC_A8, 0,
- + 		"gpmc_a8", "mii2_rxd3", "rgmii2_rd3", "mmc2_dat6",
- + 		NULL, NULL, "mcasp0_aclkx", "gpio1_24"),
- + 	_AM33XX_MUXENTRY(GPMC_A9, 0,
- + 		"gpmc_a9", "mii2_rxd2", "rgmii2_rd2", "mmc2_dat7",
- + 		NULL, NULL, "mcasp0_fsx", "gpio1_25"),
- + 	_AM33XX_MUXENTRY(GPMC_A10, 0,
- + 		"gpmc_a10", "mii2_rxd1", "rgmii2_rd1", "rmii2_rxd1",
- + 		NULL, NULL, "mcasp0_axr0", "gpio1_26"),
- + 	_AM33XX_MUXENTRY(GPMC_A11, 0,
- + 		"gpmc_a11", "mii2_rxd0", "rgmii2_rd0", "rmii2_rxd0",
- + 		NULL, NULL, "mcasp0_axr1", "gpio1_27"),
- + 	_AM33XX_MUXENTRY(GPMC_WAIT0, 0,
- + 		"gpmc_wait0", "mii2_crs", NULL, "rmii2_crs_dv",
- + 		"mmc1_sdcd", NULL, NULL, "gpio0_30"),
- + 	_AM33XX_MUXENTRY(GPMC_WPN, 0,
- + 		"gpmc_wpn", "mii2_rxerr", NULL, "rmii2_rxerr",
- + 		"mmc2_sdcd", NULL, NULL, "gpio0_31"),
- + 	_AM33XX_MUXENTRY(GPMC_BEN1, 0,
- + 		"gpmc_ben1", "mii2_col", NULL, "mmc2_dat3",
- + 		NULL, NULL, "mcasp0_aclkr", "gpio1_28"),
- + 	_AM33XX_MUXENTRY(GPMC_CSN0, 0,
- + 		"gpmc_csn0", NULL, NULL, NULL,
- + 		NULL, NULL, NULL, "gpio1_29"),
- + 	_AM33XX_MUXENTRY(GPMC_CSN1, 0,
- + 		"gpmc_csn1", "gpmc_clk", "mmc1_clk", "pr1_edio_data_in6",
- + 		"pr1_edio_data_out6", "pr1_pru1_pru_r30_12", "pr1_pru1_pru_r31_12", "gpio1_30"),
- + 	_AM33XX_MUXENTRY(GPMC_CSN2, 0,
- + 		"gpmc_csn2", NULL, "mmc1_cmd", NULL,
- + 		NULL, NULL, NULL, "gpio1_31"),
- + 	_AM33XX_MUXENTRY(GPMC_CSN3, 0,
- + 		"gpmc_csn3", NULL, NULL, "mmc2_cmd",
- + 		NULL, NULL, NULL, "gpio2_0"),
- + 	_AM33XX_MUXENTRY(GPMC_CLK, 0,
- + 		"gpmc_clk", "lcd_memory_clk_mux", NULL, "mmc2_clk",
- + 		NULL, NULL, "mcasp0_fsr", "gpio2_1"),
- + 	_AM33XX_MUXENTRY(GPMC_ADVN_ALE, 0,
- + 		"gpmc_advn_ale", NULL, "timer4", NULL,
- + 		NULL, NULL, NULL, "gpio2_2"),
- + 	_AM33XX_MUXENTRY(GPMC_OEN_REN, 0,
- + 		"gpmc_oen_ren", NULL, "timer7", NULL,
- + 		NULL, NULL, NULL, "gpio2_3"),
- + 	_AM33XX_MUXENTRY(GPMC_WEN, 0,
- + 		"gpmc_wen", NULL, "timer6", NULL,
- + 		NULL, NULL, NULL, "gpio2_4"),
- + 	_AM33XX_MUXENTRY(GPMC_BEN0_CLE, 0,
- + 		"gpmc_ben0_cle", NULL, NULL, NULL,
- + 		NULL, NULL, NULL, "gpio2_5"),
- + 	_AM33XX_MUXENTRY(LCD_DATA0, 0,
- + 		"lcd_data0", "gpmc_a0", NULL, NULL,
- + 		NULL, NULL, NULL, "gpio2_6"),
- + 	_AM33XX_MUXENTRY(LCD_DATA1, 0,
- + 		"lcd_data1", "gpmc_a1", NULL, NULL,
- + 		NULL, NULL, NULL, "gpio2_7"),
- + 	_AM33XX_MUXENTRY(LCD_DATA2, 0,
- + 		"lcd_data2", "gpmc_a2", NULL, NULL,
- + 		NULL, NULL, NULL, "gpio2_8"),
- + 	_AM33XX_MUXENTRY(LCD_DATA3, 0,
- + 		"lcd_data3", "gpmc_a3", NULL, NULL,
- + 		NULL, NULL, NULL, "gpio2_9"),
- + 	_AM33XX_MUXENTRY(LCD_DATA4, 0,
- + 		"lcd_data4", "gpmc_a4", NULL, NULL,
- + 		NULL, NULL, NULL, "gpio2_10"),
- + 	_AM33XX_MUXENTRY(LCD_DATA5, 0,
- + 		"lcd_data5", "gpmc_a5", NULL, NULL,
- + 		NULL, NULL, NULL, "gpio2_11"),
- + 	_AM33XX_MUXENTRY(LCD_DATA6, 0,
- + 		"lcd_data6", "gpmc_a6", NULL, NULL,
- + 		NULL, NULL, NULL, "gpio2_12"),
- + 	_AM33XX_MUXENTRY(LCD_DATA7, 0,
- + 		"lcd_data7", "gpmc_a7", NULL, NULL,
- + 		NULL, NULL, NULL, "gpio2_13"),
- + 	_AM33XX_MUXENTRY(LCD_DATA8, 0,
- + 		"lcd_data8", "gpmc_a12", NULL, "mcasp0_aclkx",
- + 		NULL, NULL, "uart2_ctsn", "gpio2_14"),
- + 	_AM33XX_MUXENTRY(LCD_DATA9, 0,
- + 		"lcd_data9", "gpmc_a13", NULL, "mcasp0_fsx",
- + 		NULL, NULL, "uart2_rtsn", "gpio2_15"),
- + 	_AM33XX_MUXENTRY(LCD_DATA10, 0,
- + 		"lcd_data10", "gpmc_a14", NULL, "mcasp0_axr0",
- + 		NULL, NULL, NULL, "gpio2_16"),
- + 	_AM33XX_MUXENTRY(LCD_DATA11, 0,
- + 		"lcd_data11", "gpmc_a15", NULL, "mcasp0_ahclkr",
- + 		"mcasp0_axr2", NULL, NULL, "gpio2_17"),
- + 	_AM33XX_MUXENTRY(LCD_DATA12, 0,
- + 		"lcd_data12", "gpmc_a16", "eQEP1A_in", "mcasp0_aclkr",
- + 		"mcasp0_axr2", "pr1_mii0_rxlink", "uart4_ctsn", "gpio0_8"),
- + 	_AM33XX_MUXENTRY(LCD_DATA13, 0,
- + 		"lcd_data13", "gpmc_a17", "eQEP1B_in", "mcasp0_fsr",
- + 		"mcasp0_axr3", "pr1_mii0_rxer", "uart4_rtsn", "gpio0_9"),
- + 	_AM33XX_MUXENTRY(LCD_DATA14, 0,
- + 		"lcd_data14", "gpmc_a18", NULL, "mcasp0_axr1",
- + 		NULL, NULL, NULL, "gpio0_10"),
- + 	_AM33XX_MUXENTRY(LCD_DATA15, 0,
- + 		"lcd_data15", "gpmc_a19", NULL, "mcasp0_ahclkx",
- + 		"mcasp0_axr3", NULL, NULL, "gpio0_11"),
- + 	_AM33XX_MUXENTRY(LCD_VSYNC, 0,
- + 		"lcd_vsync", NULL, NULL, NULL,
- + 		NULL, NULL, NULL, "gpio2_22"),
- + 	_AM33XX_MUXENTRY(LCD_HSYNC, 0,
- + 		"lcd_hsync", NULL, NULL, NULL,
- + 		NULL, NULL, NULL, "gpio2_23"),
- + 	_AM33XX_MUXENTRY(LCD_PCLK, 0,
- + 		"lcd_pclk", NULL, NULL, NULL,
- + 		NULL, NULL, NULL, "gpio2_24"),
- + 	_AM33XX_MUXENTRY(LCD_AC_BIAS_EN, 0,
- + 		"lcd_ac_bias_en", NULL, NULL, NULL,
- + 		NULL, NULL, NULL, "gpio2_25"),
- + 	_AM33XX_MUXENTRY(MMC0_DAT3, 0,
- + 		"mmc0_dat3", NULL, NULL, NULL,
- + 		NULL, NULL, NULL, "gpio2_26"),
- + 	_AM33XX_MUXENTRY(MMC0_DAT2, 0,
- + 		"mmc0_dat2", NULL, NULL, NULL,
- + 		NULL, NULL, NULL, "gpio2_27"),
- + 	_AM33XX_MUXENTRY(MMC0_DAT1, 0,
- + 		"mmc0_dat1", NULL, NULL, NULL,
- + 		NULL, NULL, NULL, "gpio2_28"),
- + 	_AM33XX_MUXENTRY(MMC0_DAT0, 0,
- + 		"mmc0_dat0", NULL, NULL, NULL,
- + 		NULL, NULL, NULL, "gpio2_29"),
- + 	_AM33XX_MUXENTRY(MMC0_CLK, 0,
- + 		"mmc0_clk", NULL, NULL, NULL,
- + 		NULL, NULL, NULL, "gpio2_30"),
- + 	_AM33XX_MUXENTRY(MMC0_CMD, 0,
- + 		"mmc0_cmd", NULL, NULL, NULL,
- + 		NULL, NULL, NULL, "gpio2_31"),
- + 	_AM33XX_MUXENTRY(MII1_COL, 0,
- + 		"mii1_col", "rmii2_refclk", "spi1_sclk", NULL,
- + 		"mcasp1_axr2", "mmc2_dat3", "mcasp0_axr2", "gpio3_0"),
- + 	_AM33XX_MUXENTRY(MII1_CRS, 0,
- + 		"mii1_crs", "rmii1_crs_dv", "spi1_d0", "i2c1_sda",
- + 		"mcasp1_aclkx", NULL, NULL, "gpio3_1"),
- + 	_AM33XX_MUXENTRY(MII1_RXERR, 0,
- + 		"mii1_rxerr", "rmii1_rxerr", "spi1_d1", "i2c1_scl",
- + 		"mcasp1_fsx", NULL, NULL, "gpio3_2"),
- + 	_AM33XX_MUXENTRY(MII1_TXEN, 0,
- + 		"mii1_txen", "rmii1_txen", "rgmii1_tctl", NULL,
- + 		"mcasp1_axr0", NULL, "mmc2_cmd", "gpio3_3"),
- + 	_AM33XX_MUXENTRY(MII1_RXDV, 0,
- + 		"mii1_rxdv", NULL, "rgmii1_rctl", NULL,
- + 		"mcasp1_aclx", "mmc2_dat0", "mcasp0_aclkr", "gpio3_4"),
- + 	_AM33XX_MUXENTRY(MII1_TXD3, 0,
- + 		"mii1_txd3", NULL, "rgmii1_td3", NULL,
- + 		"mcasp1_fsx", "mmc2_dat1", "mcasp0_fsr", "gpio0_16"),
- + 	_AM33XX_MUXENTRY(MII1_TXD2, 0,
- + 		"mii1_txd2", NULL, "rgmii1_td2", NULL,
- + 		"mcasp1_axr0", "mmc2_dat2", "mcasp0_ahclkx", "gpio0_17"),
- + 	_AM33XX_MUXENTRY(MII1_TXD1, 0,
- + 		"mii1_txd1", "rmii1_txd1", "rgmii1_td1", "mcasp1_fsr",
- + 		"mcasp1_axr1", NULL, "mmc1_cmd", "gpio0_21"),
- + 	_AM33XX_MUXENTRY(MII1_TXD0, 0,
- + 		"mii1_txd0", "rmii1_txd0", "rgmii1_td0", "mcasp1_axr2",
- + 		"mcasp1_aclkr", NULL, "mmc1_clk", "gpio0_28"),
- + 	_AM33XX_MUXENTRY(MII1_TXCLK, 0,
- + 		"mii1_txclk", NULL, "rgmii1_tclk", "mmc0_dat7",
- + 		"mmc1_dat0", NULL, "mcasp0_aclkx", "gpio3_9"),
- + 	_AM33XX_MUXENTRY(MII1_RXCLK, 0,
- + 		"mii1_rxclk", NULL, "rgmii1_rclk", "mmc0_dat6",
- + 		"mmc1_dat1", NULL, "mcasp0_fsx", "gpio3_10"),
- + 	_AM33XX_MUXENTRY(MII1_RXD3, 0,
- + 		"mii1_rxd3", NULL, "rgmii1_rd3", "mmc0_dat5",
- + 		"mmc1_dat2", NULL, "mcasp0_axr0", "gpio2_18"),
- + 	_AM33XX_MUXENTRY(MII1_RXD2, 0,
- + 		"mii1_rxd2", NULL, "rgmii1_rd2", "mmc0_dat4",
- + 		"mmc1_dat3", NULL, "mcasp0_axr1", "gpio2_19"),
- + 	_AM33XX_MUXENTRY(MII1_RXD1, 0,
- + 		"mii1_rxd1", "rmii1_rxd1", "rgmii1_rd1", "mcasp1_axr3",
- + 		"mcasp1_fsr", NULL, "mmc2_clk", "gpio2_20"),
- + 	_AM33XX_MUXENTRY(MII1_RXD0, 0,
- + 		"mii1_rxd0", "rmii1_rxd0", "rgmii1_rd0", "mcasp1_ahclkx",
- + 		"mcasp1_ahclkr", "mcasp1_aclkr", "mcasp0_axr3", "gpio2_21"),
- + 	_AM33XX_MUXENTRY(MII1_REFCLK, 0,
- + 		"rmii1_refclk", NULL, "spi1_cs0", NULL,
- + 		"mcasp1_axr3", "mmc0_pow", "mcasp1_ahclkx", "gpio0_29"),
- + 	_AM33XX_MUXENTRY(MDIO_DATA, 0,
- + 		"mdio_data", NULL, NULL, NULL,
- + 		"mmc0_sdcd", "mmc1_cmd", "mmc2_cmd", "gpio0_0"),
- + 	_AM33XX_MUXENTRY(MDIO_CLK, 0,
- + 		"mdio_clk", NULL, NULL, NULL,
- + 		"mmc0_sdwp", "mmc1_clk", "mmc2_clk", "gpio0_1"),
- + 	_AM33XX_MUXENTRY(SPI0_SCLK, 0,
- + 		"spi0_sclk", "uart2_rxd", "i2c2_sda", NULL,
- + 		NULL, NULL, NULL, "gpio0_2"),
- + 	_AM33XX_MUXENTRY(SPI0_D0, 0,
- + 		"spi0_d0", "uart2_txd", "i2c2_scl", NULL,
- + 		NULL, NULL, NULL, "gpio0_3"),
- + 	_AM33XX_MUXENTRY(SPI0_D1, 0,
- + 		"spi0_d1", "mmc1_sdwp", "i2c1_sda", NULL,
- + 		NULL, NULL, NULL, "gpio0_4"),
- + 	_AM33XX_MUXENTRY(SPI0_CS0, 0,
- + 		"spi0_cs0", "mmc2_sdwp", "i2c1_scl", NULL,
- + 		NULL, NULL, NULL, "gpio0_5"),
- + 	_AM33XX_MUXENTRY(SPI0_CS1, 0,
- + 		"spi0_cs1", "uart3_rxd", NULL, "mmc0_pow",
- + 		NULL, "mmc0_sdcd", NULL, "gpio0_6"),
- + 	_AM33XX_MUXENTRY(ECAP0_IN_PWM0_OUT, 0,
- + 		"ecap0_in_pwm0_out", "uart3_txd", "spi1_cs1", "pr1_ecap0_ecap_capin_apwm_o",
- + 		"spi1_sclk", "mmc0_sdwp", "xdma_event_intr2", "gpio0_7"),
- + 	_AM33XX_MUXENTRY(UART0_CTSN, 0,
- + 		"uart0_ctsn", "uart4_rxd", "d_can1_tx", "i2c1_sda",
- + 		"spi1_d0", "timer7", "pr1_edc_sync0_out", "gpio1_8"),
- + 	_AM33XX_MUXENTRY(UART0_RTSN, 0,
- + 		"uart0_rtsn", "uart4_txd", "d_can1_rx", "i2c1_scl",
- + 		"spi1_d1", "spi1_cs0", "pr1_edc_sync1_out", "gpio1_9"),
- + 	_AM33XX_MUXENTRY(UART0_RXD, 0,
- + 		"uart0_rxd", "spi1_cs0", "d_can0_tx", "i2c2_sda",
- + 		NULL, NULL, NULL, "gpio1_10"),
- + 	_AM33XX_MUXENTRY(UART0_TXD, 0,
- + 		"uart0_txd", "spi1_cs1", "d_can0_rx", "i2c2_scl",
- + 		NULL, NULL, NULL, "gpio1_11"),
- + 	_AM33XX_MUXENTRY(UART1_CTSN, 0,
- + 		"uart1_ctsn", "timer6", "dcan0_tx", "i2c2_sda",
- + 		"spi1_cs0", "pr1_uart0_cts_n", "pr1_edc_latch0_in", "gpio0_12"),
- + 	_AM33XX_MUXENTRY(UART1_RTSN, 0,
- + 	"uart1_rtsn", "timer5", "dcan0_rx", "i2c2_scl",
- + 		"spi1_cs1", "pr1_uart0_rts_n", "pr1_edc_latch1_in", "gpio0_13"),
- + 	_AM33XX_MUXENTRY(UART1_RXD, 0,
- + 		"uart1_rxd", "mmc1_sdwp", "dcan1_tx", "i2c1_sda",
- + 		NULL, "pr1_uart0_rxd", "pr1_pru1_pru_r31_16", "gpio0_14"),
- + 	_AM33XX_MUXENTRY(UART1_TXD, 0,
- + 		"uart1_txd", "mmc2_sdwp", "dcan1_rx", "i2c1_scl",
- + 		NULL, "pr1_uart0_txd", "pr1_pru0_pru_r31_16", "gpio0_15"),
- + 	_AM33XX_MUXENTRY(I2C0_SDA, 0,
- + 		"i2c0_sda", NULL, NULL, NULL,
- + 		NULL, NULL, NULL, "gpio3_5"),
- + 	_AM33XX_MUXENTRY(I2C0_SCL, 0,
- + 		"i2c0_scl", NULL, NULL, NULL,
- + 		NULL, NULL, NULL, "gpio3_6"),
- + 	_AM33XX_MUXENTRY(MCASP0_ACLKX, 0,
- + 		"mcasp0_aclkx", "ehrpwm0A", NULL, "spi1_sclk",
- + 		"mmc0_sdcd", "pr1_pru0_pru_r30_0", "pr1_pru0_pru_r31_0", "gpio3_14"),
- + 	_AM33XX_MUXENTRY(MCASP0_FSX, 0,
- + 		"mcasp0_fsx", "ehrpwm0B", NULL, "spi1_d0",
- + 		"mmc1_sdcd", "pr1_pru0_pru_r30_1", "pr1_pru0_pru_r31_1", "gpio3_15"),
- + 	_AM33XX_MUXENTRY(MCASP0_AXR0, 0,
- + 		"mcasp0_axr0", "ehrpwm0_tripzone_input", NULL, "spi1_d1",
- + 		"mmc2_sdcd", "pr1_pru0_pru_r30_2", "pr1_pru0_pru_r31_2", "gpio3_16"),
- + 	_AM33XX_MUXENTRY(MCASP0_AHCLKR, 0,
- + 		"mcasp0_ahclkr", "ehrpwm0_synci", "mcasp0_axr2", "spi1_cs0",
- + 		"ecap2_in_pwm2_out", "pr1_pru0_pru_r30_3", "pr1_pru0_pru_r31_3", "gpio3_17"),
- + 	_AM33XX_MUXENTRY(MCASP0_ACLKR, 0,
- + 		"mcasp0_aclkr", NULL, "mcasp0_axr2", "mcasp1_aclkx",
- + 		"mmc0_sdwp", NULL, NULL, "gpio3_18"),
- + 	_AM33XX_MUXENTRY(MCASP0_FSR, 0,
- + 		"mcasp0_fsr", "eQEP0B_in", "mcasp0_axr3", "mcasp1_fsx",
- + 		"EMU2", "pr1_pru0_pru_r30_5", "pr1_pru0_pru_r31_5", "gpio3_19"),
- + 	_AM33XX_MUXENTRY(MCASP0_AXR1, 0,
- + 		"mcasp0_axr1", "eQEP0_index", NULL, "mcasp1_axr0",
- + 		"EMU3", "pr1_pru0_pru_r30_6", "pr1_pru0_pru_r31_6", "gpio3_20"),
- + 	_AM33XX_MUXENTRY(MCASP0_AHCLKX, 0,
- + 		"mcasp0_ahclkx", "eQEP0_strobe", "mcasp0_axr3", "mcasp1_axr1",
- + 		"EMU4", "pr1_pru0_pru_r30_7", "pr1_pru0_pru_r31_7", "gpio3_21"),
- + 	_AM33XX_MUXENTRY(XDMA_EVENT_INTR0, 0,
- + 		"xdma_event_intr0", NULL, "timer4", "clkout1",
- + 		"spi1_cs1", "pr1_pru1_pru_r31_16", "EMU2", "gpio0_19"),
- + 	_AM33XX_MUXENTRY(XDMA_EVENT_INTR1, 0,
- + 		"xdma_event_intr1", NULL, "tclkin", "clkout2",
- + 		"timer7", "pr1_pru0_pru_r31_16", "EMU3", "gpio0_20"),
- + 	_AM33XX_MUXENTRY(WARMRSTN, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(PWRONRSTN, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(NMIN, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(XTALIN, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(XTALOUT, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(TMS, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(TDI, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(TDO, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(TCK, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(TRSTN, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(EMU0, 0,
- + 		"emu0", NULL, NULL, NULL,
- + 		NULL, NULL, NULL, "gpio3_7"),
- + 	_AM33XX_MUXENTRY(EMU1, 0,
- + 		"emu1", NULL, NULL, NULL,
- + 		NULL, NULL, NULL, "gpio3_8"),
- + 	_AM33XX_MUXENTRY(RTC_XTALIN, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(RTC_XTALOUT, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(RTC_PWRONRSTN, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(PMIC_POWER_EN, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(EXT_WAKEUP, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(USB0_DRVVBUS, 0,
- + 		"usb0_drvvbus", NULL, NULL, NULL,
- + 		NULL, NULL, NULL, "gpio0_18"),
- + 	_AM33XX_MUXENTRY(USB1_DRVVBUS, 0,
- + 		"usb1_drvvbus", NULL, NULL, NULL,
- + 		NULL, NULL, NULL, "gpio3_13"),
- + 	_AM33XX_MUXENTRY(DDR_RESETN, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_CSN0, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_CKE, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_CK, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_CKN, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_CASN, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_RASN, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_WEN, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_BA0, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_BA1, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_BA2, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_A0, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_A1, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_A2, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_A3, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_A4, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_A5, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_A6, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_A7, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_A8, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_A9, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_A10, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_A11, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_A12, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_A13, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_A14, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_A15, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_ODT, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_D0, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_D1, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_D2, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_D3, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_D4, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_D5, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_D6, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_D7, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_D8, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_D9, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_D10, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_D11, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_D12, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_D13, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_D14, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_D15, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_DQM0, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_DQM1, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_DQS0, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_DQSN0, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_DQS1, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_DQSN1, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_VREF, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(DDR_VTP, 0,
- + 		NULL, NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(AIN0, 0,
- + 		"ain0", NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(AIN1, 0,
- + 		"ain1", NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(AIN2, 0,
- + 		"ain2", NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(AIN3, 0,
- + 		"ain3", NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(VREFP, 0,
- + 		"vrefp", NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	_AM33XX_MUXENTRY(VREFN, 0,
- + 		"vrefn", NULL, NULL, NULL,
- + 		NULL, NULL, NULL, NULL),
- + 	{ .reg_offset = OMAP_MUX_TERMINATOR },
- + };
- + 
- + int __init am33xx_mux_init(struct omap_board_mux *board_subset)
- + {
- + 	return omap_mux_init("core", 0, AM33XX_CONTROL_PADCONF_MUX_PBASE,
- + 			AM33XX_CONTROL_PADCONF_MUX_SIZE, am33xx_muxmodes,
- + 			NULL, board_subset, NULL);
- + }
- + 
- + #ifdef CONFIG_SUSPEND
- + struct am33xx_padconf_regs {
- + 	u16 offset;
- + 	u32 val;
- + };
- + 
- + static struct am33xx_padconf_regs am33xx_lp_padconf[] = {
- + 	{.offset = AM33XX_CONTROL_GMII_SEL_OFFSET},
- + 	{.offset = AM33XX_CONTROL_PADCONF_GPMC_A0_OFFSET},
- + 	{.offset = AM33XX_CONTROL_PADCONF_GPMC_A1_OFFSET},
- + 	{.offset = AM33XX_CONTROL_PADCONF_GPMC_A2_OFFSET},
- + 	{.offset = AM33XX_CONTROL_PADCONF_GPMC_A3_OFFSET},
- + 	{.offset = AM33XX_CONTROL_PADCONF_GPMC_A4_OFFSET},
- + 	{.offset = AM33XX_CONTROL_PADCONF_GPMC_A5_OFFSET},
- + 	{.offset = AM33XX_CONTROL_PADCONF_GPMC_A6_OFFSET},
- + 	{.offset = AM33XX_CONTROL_PADCONF_GPMC_A7_OFFSET},
- + 	{.offset = AM33XX_CONTROL_PADCONF_GPMC_A8_OFFSET},
- + 	{.offset = AM33XX_CONTROL_PADCONF_GPMC_A9_OFFSET},
- + 	{.offset = AM33XX_CONTROL_PADCONF_GPMC_A10_OFFSET},
- + 	{.offset = AM33XX_CONTROL_PADCONF_GPMC_A11_OFFSET},
- + 	{.offset = AM33XX_CONTROL_PADCONF_GPMC_WAIT0_OFFSET},
- + 	{.offset = AM33XX_CONTROL_PADCONF_GPMC_WPN_OFFSET},
- + 	{.offset = AM33XX_CONTROL_PADCONF_GPMC_BEN1_OFFSET},
- + 	{.offset = AM33XX_CONTROL_PADCONF_MII1_COL_OFFSET},
- + 	{.offset = AM33XX_CONTROL_PADCONF_MII1_CRS_OFFSET},
- + 	{.offset = AM33XX_CONTROL_PADCONF_MII1_RXERR_OFFSET},
- + 	{.offset = AM33XX_CONTROL_PADCONF_MII1_TXEN_OFFSET},
- + 	{.offset = AM33XX_CONTROL_PADCONF_MII1_RXDV_OFFSET},
- + 	{.offset = AM33XX_CONTROL_PADCONF_MII1_TXD3_OFFSET},
- + 	{.offset = AM33XX_CONTROL_PADCONF_MII1_TXD2_OFFSET},
- + 	{.offset = AM33XX_CONTROL_PADCONF_MII1_TXD1_OFFSET},
- + 	{.offset = AM33XX_CONTROL_PADCONF_MII1_TXD0_OFFSET},
- + 	{.offset = AM33XX_CONTROL_PADCONF_MII1_TXCLK_OFFSET},
- + 	{.offset = AM33XX_CONTROL_PADCONF_MII1_RXCLK_OFFSET},
- + 	{.offset = AM33XX_CONTROL_PADCONF_MII1_RXD3_OFFSET},
- + 	{.offset = AM33XX_CONTROL_PADCONF_MII1_RXD2_OFFSET},
- + 	{.offset = AM33XX_CONTROL_PADCONF_MII1_RXD1_OFFSET},
- + 	{.offset = AM33XX_CONTROL_PADCONF_MII1_RXD0_OFFSET},
- + 	{.offset = AM33XX_CONTROL_PADCONF_MII1_REFCLK_OFFSET},
- + 	{.offset = AM33XX_CONTROL_PADCONF_MDIO_DATA_OFFSET},
- + 	{.offset = AM33XX_CONTROL_PADCONF_MDIO_CLK_OFFSET},
- + };
- + #endif /* CONFIG_SUSPEND */
- + 
- + struct susp_io_pad_conf {
- + 	u32 enabled;
- + 	u32 val;
- + };
- + 
- + static u32 susp_io_pad_conf_enabled;
- + static struct susp_io_pad_conf pad_array[MAX_IO_PADCONF];
- + 
- + struct standby_gpio_pad_struct {
- + 	u32 enabled;
- + 	u32 gpio_request_success;
- + 	u32 pin_val;
- + 	u32 trigger;
- + 	u32 gpio_pin;
- + 	u32 curr_pin_mux;
- + };
- + 
- + static struct standby_gpio_pad_struct standby_gpio_array[MAX_IO_PADCONF];
- + 
- + /*
- +  * Expected input: 1/0
- +  * Example: "echo 1 > enable_suspend_io_pad_conf" enables IO PAD Config
- +  */
- + static int susp_io_pad_enable_set(void *data, u64 val)
- + {
- + 	u32 *enabled = data;
- + 
- + 	*enabled = val & 0x1;
- + 
- + 	return 0;
- + }
- + 
- + static int susp_io_pad_enable_get(void *data, u64 *val)
- + {
- + 	u32 *enabled = data;
- + 
- + 	*val = *enabled;
- + 
- + 	return 0;
- + }
- + 
- + DEFINE_SIMPLE_ATTRIBUTE(susp_io_pad_enable_fops, susp_io_pad_enable_get,
- + 			susp_io_pad_enable_set, "%llx\n");
- + 
- + static unsigned int am335x_pin_mux_addr_to_skip[] = {
- + 	0x9bc,
- + 	0x9c4, 0x9c8, 0x9cc,
- + 	0x9ec,
- + 	0x9f0, 0x9f4,
- + 	0xa08, 0xa0c,
- + 	0xa10, 0xa14, 0xa18,
- + 	0xa20, 0xa24, 0xa28, 0xa2c,
- + 	0xa30,
- + };
- + 
- + static int susp_io_pad_status_show(struct seq_file *s, void *unused)
- + {
- + 	struct omap_mux *mux_arr = &am33xx_muxmodes[0];
- + 	u32 *enabled = s->private;
- + 	int i;
- + 
- + 	if (!*enabled) {
- + 		pr_err("%s: IO PAD Configuration is not enabled\n", __func__);
- + 		return 0;
- + 	}
- + 
- + 	for (i = 0; i < MAX_IO_PADCONF;) {
- + 		int off, j, addr_match = 0;
- + 
- + 		if (pad_array[i].enabled) {
- + 			int mode = pad_array[i].val & OMAP_MUX_MODE7;
- + 			seq_printf(s, "%s.%s (0x%08x = 0x%02x)\n",
- + 				mux_arr->muxnames[0], mux_arr->muxnames[mode],
- + 				(unsigned int)(AM33XX_CONTROL_PADCONF_MUX_PBASE
- + 				+ mux_arr->reg_offset),
- + 				pad_array[i].val);
- + 		}
- + 
- + 		i++;
- + 
- + 		/*
- + 		 * AM335x pin-mux register offset sequence is broken, meaning
- + 		 * there is no pin-mux setting at some offset and at some
- + 		 * offsets, the modes are not supposed to be changed. Because
- + 		 * of this, the "am33xx_muxmodes" array above will not have any
- + 		 * values at these indexes. Hence the pad_array &
- + 		 * am33xx_muxmodes array will be out of sync at these index.
- + 		 * Handle missing pin-mux entries accordingly by using a special
- + 		 * array that indicate these offsets.
- + 		 */
- + 		off = ((i * 4) + 0x800);
- + 		for (j = 0; j < ARRAY_SIZE(am335x_pin_mux_addr_to_skip); j++) {
- + 			if (off == am335x_pin_mux_addr_to_skip[j]) {
- + 				addr_match = 1;
- + 				break;
- + 			}
- + 		}
- + 		if (addr_match == 0)
- + 			mux_arr++;
- + 	}
- + 
- + 	return 0;
- + }
- + 
- + /*
- +  * Expected input: pinmux_name=<value1>
- +  *	pinmux_name = Pin-mux name that is to be setup during suspend with value
- +  *		<value1>. Pin-mux name should be in "mode0_name.function_name"
- +  *		format. Internally the pin-mux offset is calculated from the
- +  *		pin-mux names. Invalid pin-mux names and values are ignored.
- +  *		Remember, NO spaces anywhere in the input.
- +  *
- +  * Example:
- +  *	  echo mcasp0_aclkx.gpio3_14=0x27 > suspend_pad_conf
- +  *		stores 0x27 as the value to be written to the pinmux (with
- +  *		mode0_name.function_name as mcasp0_aclkx.gpio3_14) when entering
- +  *		suspend
- +  */
- + static ssize_t susp_io_pad_write(struct file *file,
- + 					 const char __user *user_buf,
- + 					 size_t count, loff_t *ppos)
- + {
- + 	struct seq_file *seqf;
- + 	u32 *enabled, val;
- + 	char *export_string, *token, *name;
- + 
- + 	seqf = file->private_data;
- + 	enabled = seqf->private;
- + 
- + 	if (!*enabled) {
- + 		pr_err("%s: IO PAD Configuration is not enabled\n", __func__);
- + 		return -EINVAL;
- + 	}
- + 
- + 	export_string = kzalloc(count + 1, GFP_KERNEL);
- + 	if (!export_string)
- + 		return -ENOMEM;
- + 
- + 	if (copy_from_user(export_string, user_buf, count)) {
- + 		kfree(export_string);
- + 		return -EFAULT;
- + 	}
- + 
- + 	token = export_string;
- + 	name = strsep(&token, "=");
- + 	if (name) {
- + 		struct omap_mux_partition *partition = NULL;
- + 		struct omap_mux *mux = NULL;
- + 		int mux_index, mux_mode;
- + 		int res;
- + 
- + 		mux_mode = omap_mux_get_by_name(name, &partition, &mux);
- + 		if (mux_mode < 0) {
- + 			pr_err("%s: Invalid mux name (%s). Ignoring the"
- + 					" value\n", __func__, name);
- + 			goto err_out;
- + 		}
- + 
- + 		res = kstrtouint(token, 0, &val);
- + 		if (res < 0) {
- + 			pr_err("%s: Invalid value (%s). Ignoring\n",
- + 						__func__, token);
- + 			goto err_out;
- + 		}
- + 
- + 		mux_index = (mux->reg_offset -
- + 			AM33XX_CONTROL_PADCONF_GPMC_AD0_OFFSET) / 4;
- + 
- + 		if (mux_index > MAX_IO_PADCONF) {
- + 			pr_err("%s: Invalid index (0x%x). Ignoring\n",
- + 						__func__, mux_index);
- + 			goto err_out;
- + 		}
- + 
- + 		pad_array[mux_index].enabled = true;
- + 		pad_array[mux_index].val = val;
- + 	} else {
- + 		pr_err("%s: Invalid mux name (%s). Ignoring the entry\n",
- + 						__func__, export_string);
- + 	}
- + 
- + err_out:
- + 	*ppos += count;
- + 	kfree(export_string);
- + 	return count;
- + }
- + 
- + static int susp_io_pad_open(struct inode *inode, struct file *file)
- + {
- + 	return single_open(file, susp_io_pad_status_show, inode->i_private);
- + }
- + 
- + static const struct file_operations susp_io_pad_fops = {
- + 	.open		= susp_io_pad_open,
- + 	.read		= seq_read,
- + 	.write		= susp_io_pad_write,
- + 	.release	= single_release,
- + };
- + 
- + static int standby_gpio_status_show(struct seq_file *s, void *unused)
- + {
- + 	struct omap_mux *mux_arr = &am33xx_muxmodes[0];
- + 
- + 	int i;
- + 
- + 	for (i = 0; i < MAX_IO_PADCONF;) {
- + 		int off, j, addr_match = 0;
- + 		char *trigger;
- + 
- + 		if (standby_gpio_array[i].enabled) {
- + 			switch (standby_gpio_array[i].trigger) {
- + 			case IRQF_TRIGGER_RISING:
- + 				trigger = "rising";
- + 				break;
- + 
- + 			case IRQF_TRIGGER_FALLING:
- + 				trigger = "falling";
- + 				break;
- + 
- + 			case IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING:
- + 			/* fall through */
- + 			default:
- + 				trigger = "falling_rising";
- + 				break;
- + 			}
- + 
- + 			seq_printf(s, "%s.%s (0x%08x = 0x%02x), trigger = %s\n",
- + 				mux_arr->muxnames[0],
- + 				mux_arr->muxnames[OMAP_MUX_MODE7],
- + 				(unsigned int)(AM33XX_CONTROL_PADCONF_MUX_PBASE
- + 				+ mux_arr->reg_offset),
- + 				standby_gpio_array[i].pin_val,
- + 				trigger);
- + 
- + 
- + 		}
- + 
- + 		/*
- + 		 * AM335x pin-mux register offset sequence is broken, meaning
- + 		 * there is no pin-mux setting at some offset and at some
- + 		 * offsets, the modes are not supposed to be changed. Because
- + 		 * of this, the "am33xx_muxmodes" array above will not have any
- + 		 * values at these indexes. Hence the standby_gpio_array &
- + 		 * am33xx_muxmodes array will be out of sync at these index.
- + 		 * Handle missing pin-mux entries accordingly by using a special
- + 		 * array that indicate these offsets.
- + 		 */
- + 
- + 		i++;
- + 		off = ((i * 4) + 0x800);
- + 		for (j = 0; j < ARRAY_SIZE(am335x_pin_mux_addr_to_skip); j++) {
- + 			if (off == am335x_pin_mux_addr_to_skip[j]) {
- + 				addr_match = 1;
- + 				break;
- + 			}
- + 		}
- + 		if (addr_match == 0)
- + 			mux_arr++;
- + 	}
- + 
- + 	return 0;
- + }
- + 
- + /*
- +  * Expected input: pinmux_name=<value1>,<trigger>
- +  *	pinmux_name = Pin-mux name that is to be setup as gpio during standby
- +  *		suspend with gpio interrupt trigger mode as per <trigger> field
- +  *		with value <value1>.
- +  *		Pin-mux name should be in "mode0_name.mode7_function_name"
- +  *		format. Internally the pin-mux offset is calculated from the
- +  *		pin-mux names. Invalid pin-mux names and values are ignored.
- +  *		Remember,
- +  *			- No spaces anywhere in the input.
- +  *			- <value1> field is a must
- +  *			- <trigger> field is a must and must be one of "rising",
- +  *			  "falling"
- +  *
- +  * Example:
- +  *	  echo uart0_rxd.gpio1_10=0x27,rising > standby_gpio_pad_conf
- +  *		sets up uart0_rxd.gpio1_10 for gpio mode with interrupt trigger
- +  *		as rising and pin-mux value as 0x27 when entering standby mode.
- +  */
- + static ssize_t standby_gpio_pad_write(struct file *file,
- + 					 const char __user *user_buf,
- + 					 size_t count, loff_t *ppos)
- + {
- + 	u32 trigger;
- + 	char *export_string, *token, *name;
- + 
- + 	export_string = kzalloc(count + 1, GFP_KERNEL);
- + 	if (!export_string)
- + 		return -ENOMEM;
- + 
- + 	if (copy_from_user(export_string, user_buf, count)) {
- + 		kfree(export_string);
- + 		return -EFAULT;
- + 	}
- + 
- + 	export_string[count-1] = '\0';   /* force null terminator */
- + 	token = export_string;
- + 	name = strsep(&token, "=");
- + 	if (name) {
- + 		struct omap_mux_partition *partition = NULL;
- + 		struct omap_mux *mux = NULL;
- + 		int mux_index, mux_mode, gpio_bank, gpio_pin, res, pin_val;
- + 		char *gpio_name;
- + 
- + 		mux_mode = omap_mux_get_by_name(name, &partition, &mux);
- + 		if (mux_mode < 0) {
- + 			pr_err("%s: Invalid mux name (%s). Ignoring the"
- + 					" value\n", __func__, name);
- + 			goto err_out;
- + 		}
- + 
- + 		name = strsep(&token, ",");
- + 		if (!name) {
- + 			pr_err("%s: Invalid value (%s). Ignoring\n",
- + 				__func__, token);
- + 			goto err_out;
- + 		}
- + 
- + 		res = kstrtouint(name, 0, &pin_val);
- + 		if (res < 0) {
- + 			pr_err("%s: Invalid pin mux value (%s). Ignoring\n",
- + 						__func__, token);
- + 			goto err_out;
- + 		}
- + 
- + 		if (token && !strncmp("rising", token, 6)) {
- + 			trigger = IRQF_TRIGGER_RISING;
- + 		} else if (token && !strncmp("falling", token, 7)) {
- + 			trigger = IRQF_TRIGGER_FALLING;
- + 		} else {
- + 			pr_err("%s: Invalid trigger (%s). Defaulting to"
- + 					" falling_rising\n", __func__, token);
- + 			trigger = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
- + 		}
- + 
- + 		/* confirm whether a gpio pin exists here */
- + 		gpio_name = mux->muxnames[OMAP_MUX_MODE7];
- + 
- + 		if (!gpio_name) {
- + 			pr_err("%s: Invalid mux name (%s)\n", __func__, name);
- + 			goto err_out;
- + 		} else if (strncmp(gpio_name, "gpio", 4)) {
- + 			pr_err("%s: Invalid mux name found (%s)\n",
- + 					__func__, gpio_name);
- + 			goto err_out;
- + 		}
- + 
- + 		/*
- + 		 * parse the string name and get the gpio bank & pin number.
- + 		 * gpio_name will be in the format of "gpioX_Y" where
- + 		 *	X = bank
- + 		 *	Y = pin number
- + 		 */
- + 		gpio_bank = *(gpio_name + 4) - '0';
- + 
- + 		gpio_name += 6;
- + 		res = kstrtoint(gpio_name, 10, &gpio_pin);
- + 		if (res < 0) {
- + 			pr_err("%s: Invalid gpio pin number (%s). Ignoring\n",
- + 				__func__, gpio_name);
- + 			goto err_out;
- + 		}
- + 
- + 		mux_index = (mux->reg_offset -
- + 			AM33XX_CONTROL_PADCONF_GPMC_AD0_OFFSET) / 4;
- + 
- + 		if (mux_index > MAX_IO_PADCONF) {
- + 			pr_err("%s: Invalid index (0x%x). Ignoring\n",
- + 						__func__, mux_index);
- + 			goto err_out;
- + 		}
- + 
- + 		standby_gpio_array[mux_index].enabled = true;
- + 		standby_gpio_array[mux_index].pin_val = pin_val;
- + 		standby_gpio_array[mux_index].trigger = trigger;
- + 		standby_gpio_array[mux_index].gpio_pin =
- + 						((gpio_bank * 32) + gpio_pin);
- + 	} else {
- + 		pr_err("%s: Invalid mux name (%s). Ignoring the entry\n",
- + 						__func__, export_string);
- + 	}
- + 
- + err_out:
- + 	*ppos += count;
- + 	kfree(export_string);
- + 	return count;
- + }
- + 
- + static int standby_gpio_pad_open(struct inode *inode, struct file *file)
- + {
- + 	return single_open(file, standby_gpio_status_show, inode->i_private);
- + }
- + 
- + static const struct file_operations standby_gpio_pad_conf_fops = {
- + 	.open		= standby_gpio_pad_open,
- + 	.read		= seq_read,
- + 	.write		= standby_gpio_pad_write,
- + 	.release	= single_release,
- + };
- + 
- + void am33xx_mux_dbg_create_entry(struct dentry *mux_dbg_dir)
- + {
- + 	struct dentry *mux_dbg_suspend_io_conf_dir;
- + 
- + 	if (!mux_dbg_dir)
- + 		return;
- + 
- + 	/*
- + 	 * create a directory by the name suspend_io_pad_conf in
- + 	 * <debugfs-mount-dir>/<mux_dbg_dir>/
- + 	 */
- + 	mux_dbg_suspend_io_conf_dir = debugfs_create_dir("suspend_io_pad_conf",
- + 								mux_dbg_dir);
- + 	if (!mux_dbg_suspend_io_conf_dir)
- + 		return;
- + 
- + 	memset(pad_array, 0, sizeof(pad_array));
- + 
- + 	(void)debugfs_create_file("enable_suspend_io_pad_conf",
- + 						S_IRUGO | S_IWUSR,
- + 						mux_dbg_suspend_io_conf_dir,
- + 						&susp_io_pad_conf_enabled,
- + 						&susp_io_pad_enable_fops);
- + 	(void)debugfs_create_file("suspend_pad_conf", S_IRUGO | S_IWUSR,
- + 						mux_dbg_suspend_io_conf_dir,
- + 						&susp_io_pad_conf_enabled,
- + 						&susp_io_pad_fops);
- + 	(void)debugfs_create_file("standby_gpio_pad_conf", S_IRUGO | S_IWUSR,
- + 						mux_dbg_dir,
- + 						&susp_io_pad_conf_enabled,
- + 						&standby_gpio_pad_conf_fops);
- + }
- + 
- + void am33xx_setup_pinmux_on_suspend(void)
- + {
- + 	u32 reg_off, i;
- + 
- + 	if (susp_io_pad_conf_enabled == 1) {
- + 		reg_off = AM33XX_CONTROL_PADCONF_GPMC_AD0_OFFSET;
- + 		for (i = 0; i < MAX_IO_PADCONF; reg_off += 4, i++) {
- + 			if (pad_array[i].enabled)
- + 				writel(pad_array[i].val,
- + 						AM33XX_CTRL_REGADDR(reg_off));
- + 		}
- + 	}
- + }
- + 
- + static u32 am33xx_lp_padconf_complete[MAX_IO_PADCONF];
- + 
- + void am335x_save_padconf(void)
- + {
- + 	struct am33xx_padconf_regs *temp = am33xx_lp_padconf;
- + 	u32 reg_off;
- + 	int i;
- + 	if (susp_io_pad_conf_enabled == 1) {
- + 		i = AM33XX_CONTROL_PADCONF_GPMC_AD0_OFFSET;
- + 		reg_off = 0;
- + 
- + 		for (; i < AM33XX_CONTROL_PADCONF_MUX_SIZE; i += 4, reg_off++)
- + 			am33xx_lp_padconf_complete[reg_off] =
- + 						readl(AM33XX_CTRL_REGADDR(i));
- + 	} else {
- + 		for (i = 0; i < ARRAY_SIZE(am33xx_lp_padconf); i++, temp++)
- + 			temp->val = readl(AM33XX_CTRL_REGADDR(temp->offset));
- + 	}
- + }
- + 
- + void am335x_restore_padconf(void)
- + {
- + 	struct am33xx_padconf_regs *temp = am33xx_lp_padconf;
- + 	u32 reg_off;
- + 	int i;
- + 	if (susp_io_pad_conf_enabled == 1) {
- + 		i = AM33XX_CONTROL_PADCONF_GPMC_AD0_OFFSET;
- + 		reg_off = 0;
- + 		for (; i < AM33XX_CONTROL_PADCONF_MUX_SIZE; i += 4, reg_off++)
- + 			writel(am33xx_lp_padconf_complete[reg_off],
- + 							AM33XX_CTRL_REGADDR(i));
- + 	} else {
- + 		for (i = 0; i < ARRAY_SIZE(am33xx_lp_padconf); i++, temp++)
- + 			writel(temp->val, AM33XX_CTRL_REGADDR(temp->offset));
- + 	}
- + }
- + 
- + /*
- +  * Dummy GPIO interrupt Handler
- +  */
- + static irqreturn_t gpio_irq(int irq, void *dev_id)
- + {
- + 	return IRQ_HANDLED;
- + }
- + 
- + void am33xx_standby_setup(unsigned int state)
- + {
- + 	u32 reg_off, i;
- + 
- + 	if (state != PM_SUSPEND_STANDBY)
- + 		return;
- + 
- + 	writel(0x2, AM33XX_CM_PER_GPIO1_CLKCTRL);
- + 	writel(0x2, AM33XX_CM_PER_GPIO2_CLKCTRL);
- + 	writel(0x2, AM33XX_CM_PER_GPIO3_CLKCTRL);
- + 
- + 	reg_off = AM33XX_CONTROL_PADCONF_GPMC_AD0_OFFSET;
- + 	for (i = 0; i < MAX_IO_PADCONF; reg_off += 4, i++) {
- + 		if (standby_gpio_array[i].enabled) {
- + 			int ret, reg_val, irq;
- + 			u32 gpio_pin = standby_gpio_array[i].gpio_pin;
- + 
- + 			reg_val = readl(AM33XX_CTRL_REGADDR(reg_off));
- + 			standby_gpio_array[i].curr_pin_mux = reg_val;
- + 			reg_val = standby_gpio_array[i].pin_val;
- + 			writel(reg_val, AM33XX_CTRL_REGADDR(reg_off));
- + 
- + 			ret = gpio_request(gpio_pin, "pm_standby");
- + 			if (ret) {
- + 				pr_err("%s: Error in gpio request (%d)\n",
- + 						__func__, ret);
- + 				continue;
- + 			}
- + 			irq = gpio_to_irq(gpio_pin);
- + 			if (irq < 0) {
- + 				gpio_free(gpio_pin);
- + 				pr_err("%s: gpio_to_irq failed (%d)\n",
- + 								__func__, irq);
- + 				continue;
- + 			}
- + 			ret = request_irq(irq, gpio_irq,
- + 						standby_gpio_array[i].trigger,
- + 						"pm_standby", NULL);
- + 			if (ret) {
- + 				gpio_free(gpio_pin);
- + 				pr_err("%s: interrupt request failed (%d)\n",
- + 								__func__, ret);
- + 				continue;
- + 			}
- + 
- + 			standby_gpio_array[i].gpio_request_success = true;
- + 		}
- + 	}
- + 
- + }
- + 
- + void am33xx_standby_release(unsigned int state)
- + {
- + 	u32 reg_off, i;
- + 
- + 	if (state != PM_SUSPEND_STANDBY)
- + 		return;
- + 
- + 	reg_off = AM33XX_CONTROL_PADCONF_GPMC_AD0_OFFSET;
- + 	for (i = 0; i < MAX_IO_PADCONF; reg_off += 4, i++) {
- + 		u32 gpio_pin = standby_gpio_array[i].gpio_pin;
- + 
- + 		if (standby_gpio_array[i].enabled) {
- + 			writel(standby_gpio_array[i].curr_pin_mux,
- + 						AM33XX_CTRL_REGADDR(reg_off));
- + 
- + 			if (standby_gpio_array[i].gpio_request_success ==
- + 									true) {
- + 				int irq;
- + 
- + 				irq = gpio_to_irq(gpio_pin);
- + 				gpio_free(gpio_pin);
- + 				free_irq(irq, 0);
- + 			}
- + 		}
- + 	}
- + }
- + 
- + #else
- + int __init am33xx_mux_init(struct omap_board_mux *board_subset)
- + {
- + 	return 0;
- + }
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/mux33xx.h linux-3.2.1/arch/arm/mach-ckb_3352/mux33xx.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/mux33xx.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/mux33xx.h	2014-05-15 13:25:13.939257527 +0900
- ***************
- *** 0 ****
- --- 1,257 ----
- + /*
- +  * AM33XX pad control register macros.
- +  *
- +  * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #ifndef __ARCH_ARM_MACH_OMAP2_MUX335X_H
- + #define __ARCH_ARM_MACH_OMAP2_MUX335X_H
- + 
- + #define AM33XX_CONTROL_PADCONF_MUX_PBASE			0x44E10000LU
- + 
- + /* If pin is not defined as input, pull would get disabled.
- +  * If defined as input, flags supplied will determine pull on/off.
- +  */
- + #define AM33XX_MUX(mode0, mux_value)					\
- + {									\
- + 	.reg_offset	= (AM33XX_CONTROL_PADCONF_##mode0##_OFFSET),	\
- + 	.value		= (((mux_value) & AM33XX_INPUT_EN) ? (mux_value)\
- + 				: ((mux_value) | AM33XX_PULL_DISA)),	\
- + }
- + 
- + /*
- +  * AM33XX CONTROL_PADCONF* register offsets for pin-muxing
- +  *
- +  * Add AM33XX_CONTROL_PADCONF_MUX_PBASE to these values to get the
- +  * absolute addresses. The macro names below are mode-0 names of
- +  * corresponding pins.
- +  */
- + 
- + #define AM33XX_CONTROL_PADCONF_GPMC_AD0_OFFSET			0x0800
- + #define AM33XX_CONTROL_PADCONF_GPMC_AD1_OFFSET			0x0804
- + #define AM33XX_CONTROL_PADCONF_GPMC_AD2_OFFSET			0x0808
- + #define AM33XX_CONTROL_PADCONF_GPMC_AD3_OFFSET			0x080C
- + #define AM33XX_CONTROL_PADCONF_GPMC_AD4_OFFSET			0x0810
- + #define AM33XX_CONTROL_PADCONF_GPMC_AD5_OFFSET			0x0814
- + #define AM33XX_CONTROL_PADCONF_GPMC_AD6_OFFSET			0x0818
- + #define AM33XX_CONTROL_PADCONF_GPMC_AD7_OFFSET			0x081C
- + #define AM33XX_CONTROL_PADCONF_GPMC_AD8_OFFSET			0x0820
- + #define AM33XX_CONTROL_PADCONF_GPMC_AD9_OFFSET			0x0824
- + #define AM33XX_CONTROL_PADCONF_GPMC_AD10_OFFSET			0x0828
- + #define AM33XX_CONTROL_PADCONF_GPMC_AD11_OFFSET			0x082C
- + #define AM33XX_CONTROL_PADCONF_GPMC_AD12_OFFSET			0x0830
- + #define AM33XX_CONTROL_PADCONF_GPMC_AD13_OFFSET			0x0834
- + #define AM33XX_CONTROL_PADCONF_GPMC_AD14_OFFSET			0x0838
- + #define AM33XX_CONTROL_PADCONF_GPMC_AD15_OFFSET			0x083C
- + #define AM33XX_CONTROL_PADCONF_GPMC_A0_OFFSET			0x0840
- + #define AM33XX_CONTROL_PADCONF_GPMC_A1_OFFSET			0x0844
- + #define AM33XX_CONTROL_PADCONF_GPMC_A2_OFFSET			0x0848
- + #define AM33XX_CONTROL_PADCONF_GPMC_A3_OFFSET			0x084C
- + #define AM33XX_CONTROL_PADCONF_GPMC_A4_OFFSET			0x0850
- + #define AM33XX_CONTROL_PADCONF_GPMC_A5_OFFSET			0x0854
- + #define AM33XX_CONTROL_PADCONF_GPMC_A6_OFFSET			0x0858
- + #define AM33XX_CONTROL_PADCONF_GPMC_A7_OFFSET			0x085C
- + #define AM33XX_CONTROL_PADCONF_GPMC_A8_OFFSET			0x0860
- + #define AM33XX_CONTROL_PADCONF_GPMC_A9_OFFSET			0x0864
- + #define AM33XX_CONTROL_PADCONF_GPMC_A10_OFFSET			0x0868
- + #define AM33XX_CONTROL_PADCONF_GPMC_A11_OFFSET			0x086C
- + #define AM33XX_CONTROL_PADCONF_GPMC_WAIT0_OFFSET		0x0870
- + #define AM33XX_CONTROL_PADCONF_GPMC_WPN_OFFSET			0x0874
- + #define AM33XX_CONTROL_PADCONF_GPMC_BEN1_OFFSET			0x0878
- + #define AM33XX_CONTROL_PADCONF_GPMC_CSN0_OFFSET			0x087C
- + #define AM33XX_CONTROL_PADCONF_GPMC_CSN1_OFFSET			0x0880
- + #define AM33XX_CONTROL_PADCONF_GPMC_CSN2_OFFSET			0x0884
- + #define AM33XX_CONTROL_PADCONF_GPMC_CSN3_OFFSET			0x0888
- + #define AM33XX_CONTROL_PADCONF_GPMC_CLK_OFFSET			0x088C
- + #define AM33XX_CONTROL_PADCONF_GPMC_ADVN_ALE_OFFSET		0x0890
- + #define AM33XX_CONTROL_PADCONF_GPMC_OEN_REN_OFFSET		0x0894
- + #define AM33XX_CONTROL_PADCONF_GPMC_WEN_OFFSET			0x0898
- + #define AM33XX_CONTROL_PADCONF_GPMC_BEN0_CLE_OFFSET		0x089C
- + #define AM33XX_CONTROL_PADCONF_LCD_DATA0_OFFSET			0x08A0
- + #define AM33XX_CONTROL_PADCONF_LCD_DATA1_OFFSET			0x08A4
- + #define AM33XX_CONTROL_PADCONF_LCD_DATA2_OFFSET			0x08A8
- + #define AM33XX_CONTROL_PADCONF_LCD_DATA3_OFFSET			0x08AC
- + #define AM33XX_CONTROL_PADCONF_LCD_DATA4_OFFSET			0x08B0
- + #define AM33XX_CONTROL_PADCONF_LCD_DATA5_OFFSET			0x08B4
- + #define AM33XX_CONTROL_PADCONF_LCD_DATA6_OFFSET			0x08B8
- + #define AM33XX_CONTROL_PADCONF_LCD_DATA7_OFFSET			0x08BC
- + #define AM33XX_CONTROL_PADCONF_LCD_DATA8_OFFSET			0x08C0
- + #define AM33XX_CONTROL_PADCONF_LCD_DATA9_OFFSET			0x08C4
- + #define AM33XX_CONTROL_PADCONF_LCD_DATA10_OFFSET		0x08C8
- + #define AM33XX_CONTROL_PADCONF_LCD_DATA11_OFFSET		0x08CC
- + #define AM33XX_CONTROL_PADCONF_LCD_DATA12_OFFSET		0x08D0
- + #define AM33XX_CONTROL_PADCONF_LCD_DATA13_OFFSET		0x08D4
- + #define AM33XX_CONTROL_PADCONF_LCD_DATA14_OFFSET		0x08D8
- + #define AM33XX_CONTROL_PADCONF_LCD_DATA15_OFFSET		0x08DC
- + #define AM33XX_CONTROL_PADCONF_LCD_VSYNC_OFFSET			0x08E0
- + #define AM33XX_CONTROL_PADCONF_LCD_HSYNC_OFFSET			0x08E4
- + #define AM33XX_CONTROL_PADCONF_LCD_PCLK_OFFSET			0x08E8
- + #define AM33XX_CONTROL_PADCONF_LCD_AC_BIAS_EN_OFFSET		0x08EC
- + #define AM33XX_CONTROL_PADCONF_MMC0_DAT3_OFFSET			0x08F0
- + #define AM33XX_CONTROL_PADCONF_MMC0_DAT2_OFFSET			0x08F4
- + #define AM33XX_CONTROL_PADCONF_MMC0_DAT1_OFFSET			0x08F8
- + #define AM33XX_CONTROL_PADCONF_MMC0_DAT0_OFFSET			0x08FC
- + #define AM33XX_CONTROL_PADCONF_MMC0_CLK_OFFSET			0x0900
- + #define AM33XX_CONTROL_PADCONF_MMC0_CMD_OFFSET			0x0904
- + #define AM33XX_CONTROL_PADCONF_MII1_COL_OFFSET			0x0908
- + #define AM33XX_CONTROL_PADCONF_MII1_CRS_OFFSET			0x090C
- + #define AM33XX_CONTROL_PADCONF_MII1_RXERR_OFFSET		0x0910
- + #define AM33XX_CONTROL_PADCONF_MII1_TXEN_OFFSET			0x0914
- + #define AM33XX_CONTROL_PADCONF_MII1_RXDV_OFFSET			0x0918
- + #define AM33XX_CONTROL_PADCONF_MII1_TXD3_OFFSET			0x091C
- + #define AM33XX_CONTROL_PADCONF_MII1_TXD2_OFFSET			0x0920
- + #define AM33XX_CONTROL_PADCONF_MII1_TXD1_OFFSET			0x0924
- + #define AM33XX_CONTROL_PADCONF_MII1_TXD0_OFFSET			0x0928
- + #define AM33XX_CONTROL_PADCONF_MII1_TXCLK_OFFSET		0x092C
- + #define AM33XX_CONTROL_PADCONF_MII1_RXCLK_OFFSET		0x0930
- + #define AM33XX_CONTROL_PADCONF_MII1_RXD3_OFFSET			0x0934
- + #define AM33XX_CONTROL_PADCONF_MII1_RXD2_OFFSET			0x0938
- + #define AM33XX_CONTROL_PADCONF_MII1_RXD1_OFFSET			0x093C
- + #define AM33XX_CONTROL_PADCONF_MII1_RXD0_OFFSET			0x0940
- + #define AM33XX_CONTROL_PADCONF_MII1_REFCLK_OFFSET		0x0944
- + #define AM33XX_CONTROL_PADCONF_MDIO_DATA_OFFSET			0x0948
- + #define AM33XX_CONTROL_PADCONF_MDIO_CLK_OFFSET			0x094C
- + #define AM33XX_CONTROL_PADCONF_SPI0_SCLK_OFFSET			0x0950
- + #define AM33XX_CONTROL_PADCONF_SPI0_D0_OFFSET			0x0954
- + #define AM33XX_CONTROL_PADCONF_SPI0_D1_OFFSET			0x0958
- + #define AM33XX_CONTROL_PADCONF_SPI0_CS0_OFFSET			0x095C
- + #define AM33XX_CONTROL_PADCONF_SPI0_CS1_OFFSET			0x0960
- + #define AM33XX_CONTROL_PADCONF_ECAP0_IN_PWM0_OUT_OFFSET		0x0964
- + #define AM33XX_CONTROL_PADCONF_UART0_CTSN_OFFSET		0x0968
- + #define AM33XX_CONTROL_PADCONF_UART0_RTSN_OFFSET		0x096C
- + #define AM33XX_CONTROL_PADCONF_UART0_RXD_OFFSET			0x0970
- + #define AM33XX_CONTROL_PADCONF_UART0_TXD_OFFSET			0x0974
- + #define AM33XX_CONTROL_PADCONF_UART1_CTSN_OFFSET		0x0978
- + #define AM33XX_CONTROL_PADCONF_UART1_RTSN_OFFSET		0x097C
- + #define AM33XX_CONTROL_PADCONF_UART1_RXD_OFFSET			0x0980
- + #define AM33XX_CONTROL_PADCONF_UART1_TXD_OFFSET			0x0984
- + #define AM33XX_CONTROL_PADCONF_I2C0_SDA_OFFSET			0x0988
- + #define AM33XX_CONTROL_PADCONF_I2C0_SCL_OFFSET			0x098C
- + #define AM33XX_CONTROL_PADCONF_MCASP0_ACLKX_OFFSET		0x0990
- + #define AM33XX_CONTROL_PADCONF_MCASP0_FSX_OFFSET		0x0994
- + #define AM33XX_CONTROL_PADCONF_MCASP0_AXR0_OFFSET		0x0998
- + #define AM33XX_CONTROL_PADCONF_MCASP0_AHCLKR_OFFSET		0x099C
- + #define AM33XX_CONTROL_PADCONF_MCASP0_ACLKR_OFFSET		0x09A0
- + #define AM33XX_CONTROL_PADCONF_MCASP0_FSR_OFFSET		0x09A4
- + #define AM33XX_CONTROL_PADCONF_MCASP0_AXR1_OFFSET		0x09A8
- + #define AM33XX_CONTROL_PADCONF_MCASP0_AHCLKX_OFFSET		0x09AC
- + #define AM33XX_CONTROL_PADCONF_XDMA_EVENT_INTR0_OFFSET		0x09B0
- + #define AM33XX_CONTROL_PADCONF_XDMA_EVENT_INTR1_OFFSET		0x09B4
- + #define AM33XX_CONTROL_PADCONF_WARMRSTN_OFFSET			0x09B8
- + #define AM33XX_CONTROL_PADCONF_PWRONRSTN_OFFSET			0x09BC
- + #define AM33XX_CONTROL_PADCONF_NMIN_OFFSET			0x09C0
- + #define AM33XX_CONTROL_PADCONF_XTALIN_OFFSET			0x09C4
- + #define AM33XX_CONTROL_PADCONF_XTALOUT_OFFSET			0x09C8
- + #define AM33XX_CONTROL_PADCONF_TMS_OFFSET			0x09D0
- + #define AM33XX_CONTROL_PADCONF_TDI_OFFSET			0x09D4
- + #define AM33XX_CONTROL_PADCONF_TDO_OFFSET			0x09D8
- + #define AM33XX_CONTROL_PADCONF_TCK_OFFSET			0x09DC
- + #define AM33XX_CONTROL_PADCONF_TRSTN_OFFSET			0x09E0
- + #define AM33XX_CONTROL_PADCONF_EMU0_OFFSET			0x09E4
- + #define AM33XX_CONTROL_PADCONF_EMU1_OFFSET			0x09E8
- + #define AM33XX_CONTROL_PADCONF_RTC_XTALIN_OFFSET		0x09EC
- + #define AM33XX_CONTROL_PADCONF_RTC_XTALOUT_OFFSET		0x09F0
- + #define AM33XX_CONTROL_PADCONF_RTC_PWRONRSTN_OFFSET		0x09F8
- + #define AM33XX_CONTROL_PADCONF_EXT_WAKEUP_OFFSET		0x0A00
- + #define AM33XX_CONTROL_PADCONF_PMIC_POWER_EN_OFFSET		0x09F4
- + #define AM33XX_CONTROL_PADCONF_RTC_KALDO_ENN_OFFSET		0x0A04
- + #define AM33XX_CONTROL_PADCONF_USB0_DM_OFFSET			0x0A08
- + #define AM33XX_CONTROL_PADCONF_USB0_DP_OFFSET		        0x0A0C
- + #define AM33XX_CONTROL_PADCONF_USB0_CE_OFFSET		        0x0A10
- + #define AM33XX_CONTROL_PADCONF_USB0_ID_OFFSET		        0x0A14
- + #define AM33XX_CONTROL_PADCONF_USB0_VBUS_OFFSET			0x0A18
- + #define AM33XX_CONTROL_PADCONF_USB0_DRVVBUS_OFFSET		0x0A1C
- + #define AM33XX_CONTROL_PADCONF_USB1_DM_OFFSET			0x0A20
- + #define AM33XX_CONTROL_PADCONF_USB1_DP_OFFSET		        0x0A24
- + #define AM33XX_CONTROL_PADCONF_USB1_CE_OFFSET		        0x0A28
- + #define AM33XX_CONTROL_PADCONF_USB1_ID_OFFSET		        0x0A2C
- + #define AM33XX_CONTROL_PADCONF_USB1_VBUS_OFFSET			0x0A30
- + #define AM33XX_CONTROL_PADCONF_USB1_DRVVBUS_OFFSET		0x0A34
- + #define AM33XX_CONTROL_PADCONF_DDR_RESETN_OFFSET		0x0A38
- + #define AM33XX_CONTROL_PADCONF_DDR_CSN0_OFFSET			0x0A3C
- + #define AM33XX_CONTROL_PADCONF_DDR_CKE_OFFSET			0x0A40
- + #define AM33XX_CONTROL_PADCONF_DDR_CK_OFFSET			0x0A44
- + #define AM33XX_CONTROL_PADCONF_DDR_CKN_OFFSET			0x0A48
- + #define AM33XX_CONTROL_PADCONF_DDR_CASN_OFFSET			0x0A4C
- + #define AM33XX_CONTROL_PADCONF_DDR_RASN_OFFSET			0x0A50
- + #define AM33XX_CONTROL_PADCONF_DDR_WEN_OFFSET			0x0A54
- + #define AM33XX_CONTROL_PADCONF_DDR_BA0_OFFSET			0x0A58
- + #define AM33XX_CONTROL_PADCONF_DDR_BA1_OFFSET			0x0A5C
- + #define AM33XX_CONTROL_PADCONF_DDR_BA2_OFFSET			0x0A60
- + #define AM33XX_CONTROL_PADCONF_DDR_A0_OFFSET			0x0A64
- + #define AM33XX_CONTROL_PADCONF_DDR_A1_OFFSET			0x0A68
- + #define AM33XX_CONTROL_PADCONF_DDR_A2_OFFSET			0x0A6C
- + #define AM33XX_CONTROL_PADCONF_DDR_A3_OFFSET			0x0A70
- + #define AM33XX_CONTROL_PADCONF_DDR_A4_OFFSET			0x0A74
- + #define AM33XX_CONTROL_PADCONF_DDR_A5_OFFSET			0x0A78
- + #define AM33XX_CONTROL_PADCONF_DDR_A6_OFFSET			0x0A7C
- + #define AM33XX_CONTROL_PADCONF_DDR_A7_OFFSET			0x0A80
- + #define AM33XX_CONTROL_PADCONF_DDR_A8_OFFSET			0x0A84
- + #define AM33XX_CONTROL_PADCONF_DDR_A9_OFFSET			0x0A88
- + #define AM33XX_CONTROL_PADCONF_DDR_A10_OFFSET			0x0A8C
- + #define AM33XX_CONTROL_PADCONF_DDR_A11_OFFSET			0x0A90
- + #define AM33XX_CONTROL_PADCONF_DDR_A12_OFFSET			0x0A94
- + #define AM33XX_CONTROL_PADCONF_DDR_A13_OFFSET			0x0A98
- + #define AM33XX_CONTROL_PADCONF_DDR_A14_OFFSET			0x0A9C
- + #define AM33XX_CONTROL_PADCONF_DDR_A15_OFFSET			0x0AA0
- + #define AM33XX_CONTROL_PADCONF_DDR_ODT_OFFSET			0x0AA4
- + #define AM33XX_CONTROL_PADCONF_DDR_D0_OFFSET			0x0AA8
- + #define AM33XX_CONTROL_PADCONF_DDR_D1_OFFSET			0x0AAC
- + #define AM33XX_CONTROL_PADCONF_DDR_D2_OFFSET			0x0AB0
- + #define AM33XX_CONTROL_PADCONF_DDR_D3_OFFSET			0x0AB4
- + #define AM33XX_CONTROL_PADCONF_DDR_D4_OFFSET			0x0AB8
- + #define AM33XX_CONTROL_PADCONF_DDR_D5_OFFSET			0x0ABC
- + #define AM33XX_CONTROL_PADCONF_DDR_D6_OFFSET			0x0AC0
- + #define AM33XX_CONTROL_PADCONF_DDR_D7_OFFSET			0x0AC4
- + #define AM33XX_CONTROL_PADCONF_DDR_D8_OFFSET			0x0AC8
- + #define AM33XX_CONTROL_PADCONF_DDR_D9_OFFSET			0x0ACC
- + #define AM33XX_CONTROL_PADCONF_DDR_D10_OFFSET			0x0AD0
- + #define AM33XX_CONTROL_PADCONF_DDR_D11_OFFSET			0x0AD4
- + #define AM33XX_CONTROL_PADCONF_DDR_D12_OFFSET			0x0AD8
- + #define AM33XX_CONTROL_PADCONF_DDR_D13_OFFSET			0x0ADC
- + #define AM33XX_CONTROL_PADCONF_DDR_D14_OFFSET			0x0AE0
- + #define AM33XX_CONTROL_PADCONF_DDR_D15_OFFSET			0x0AE4
- + #define AM33XX_CONTROL_PADCONF_DDR_DQM0_OFFSET			0x0AE8
- + #define AM33XX_CONTROL_PADCONF_DDR_DQM1_OFFSET			0x0AEC
- + #define AM33XX_CONTROL_PADCONF_DDR_DQS0_OFFSET			0x0AF0
- + #define AM33XX_CONTROL_PADCONF_DDR_DQSN0_OFFSET			0x0AF4
- + #define AM33XX_CONTROL_PADCONF_DDR_DQS1_OFFSET			0x0AF8
- + #define AM33XX_CONTROL_PADCONF_DDR_DQSN1_OFFSET			0x0AFC
- + #define AM33XX_CONTROL_PADCONF_DDR_VREF_OFFSET			0x0B00
- + #define AM33XX_CONTROL_PADCONF_DDR_VTP_OFFSET			0x0B04
- + #define AM33XX_CONTROL_PADCONF_AIN3_OFFSET			0x0B20
- + #define AM33XX_CONTROL_PADCONF_AIN2_OFFSET			0x0B24
- + #define AM33XX_CONTROL_PADCONF_AIN1_OFFSET			0x0B28
- + #define AM33XX_CONTROL_PADCONF_AIN0_OFFSET			0x0B2C
- + #define AM33XX_CONTROL_PADCONF_VREFP_OFFSET			0x0B30
- + #define AM33XX_CONTROL_PADCONF_VREFN_OFFSET			0x0B34
- + 
- + #define AM33XX_CONTROL_PADCONF_MUX_SIZE				\
- + 		(AM33XX_CONTROL_PADCONF_VREFN_OFFSET + 0x4)
- + 
- + #define MAX_IO_PADCONF	((AM33XX_CONTROL_PADCONF_MUX_SIZE -	\
- + 				AM33XX_CONTROL_PADCONF_GPMC_AD0_OFFSET) / 4)
- + 
- + #ifndef __ASSEMBLER__
- + void am335x_save_padconf(void);
- + void am335x_restore_padconf(void);
- + 
- + struct dentry;
- + void am33xx_mux_dbg_create_entry(struct dentry *mux_dbg_dir);
- + void am33xx_setup_pinmux_on_suspend(void);
- + 
- + void am33xx_standby_setup(unsigned int state);
- + void am33xx_standby_release(unsigned int state);
- + 
- + #endif
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/mux.c linux-3.2.1/arch/arm/mach-ckb_3352/mux.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/mux.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/mux.c	2014-05-15 13:25:13.939257527 +0900
- ***************
- *** 0 ****
- --- 1,1208 ----
- + /*
- +  * linux/arch/arm/mach-omap2/mux.c
- +  *
- +  * OMAP2, OMAP3 and OMAP4 pin multiplexing configurations
- +  *
- +  * Copyright (C) 2004 - 2010 Texas Instruments Inc.
- +  * Copyright (C) 2003 - 2008 Nokia Corporation
- +  *
- +  * Written by Tony Lindgren
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; either version 2 of the License, or
- +  * (at your option) any later version.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- +  *
- +  */
- + #include <linux/kernel.h>
- + #include <linux/init.h>
- + #include <linux/io.h>
- + #include <linux/list.h>
- + #include <linux/slab.h>
- + #include <linux/ctype.h>
- + #include <linux/debugfs.h>
- + #include <linux/seq_file.h>
- + #include <linux/uaccess.h>
- + #include <linux/irq.h>
- + #include <linux/interrupt.h>
- + 
- + #include <asm/system.h>
- + 
- + #include <plat/omap_hwmod.h>
- + 
- + #include "control.h"
- + #include "mux.h"
- + #include "prm.h"
- + 
- + #define OMAP_MUX_BASE_OFFSET		0x30	/* Offset from CTRL_BASE */
- + #define OMAP_MUX_BASE_SZ		0x5ca
- + 
- + struct omap_mux_entry {
- + 	struct omap_mux		mux;
- + 	struct list_head	node;
- + };
- + 
- + static LIST_HEAD(mux_partitions);
- + static DEFINE_MUTEX(muxmode_mutex);
- + 
- + struct omap_mux_partition *omap_mux_get(const char *name)
- + {
- + 	struct omap_mux_partition *partition;
- + 
- + 	list_for_each_entry(partition, &mux_partitions, node) {
- + 		if (!strcmp(name, partition->name))
- + 			return partition;
- + 	}
- + 
- + 	return NULL;
- + }
- + 
- + u16 omap_mux_read(struct omap_mux_partition *partition, u16 reg)
- + {
- + 	if (partition->flags & OMAP_MUX_REG_8BIT)
- + 		return __raw_readb(partition->base + reg);
- + 	else
- + 		return __raw_readw(partition->base + reg);
- + }
- + 
- + void omap_mux_write(struct omap_mux_partition *partition, u16 val,
- + 			   u16 reg)
- + {
- + 	if (partition->flags & OMAP_MUX_REG_8BIT)
- + 		__raw_writeb(val, partition->base + reg);
- + 	else
- + 		__raw_writew(val, partition->base + reg);
- + }
- + 
- + void omap_mux_write_array(struct omap_mux_partition *partition,
- + 				 struct omap_board_mux *board_mux)
- + {
- + 	if (!board_mux)
- + 		return;
- + 
- + 	while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) {
- + 		omap_mux_write(partition, board_mux->value,
- + 			       board_mux->reg_offset);
- + 		board_mux++;
- + 	}
- + }
- + 
- + #ifdef CONFIG_OMAP_MUX
- + 
- + static char *omap_mux_options;
- + 
- + static int _omap_mux_init_gpio(struct omap_mux_partition *partition,
- + 				      int gpio, int val)
- + {
- + 	struct omap_mux_entry *e;
- + 	struct omap_mux *gpio_mux = NULL;
- + 	u16 old_mode;
- + 	u16 mux_mode;
- + 	int found = 0;
- + 	struct list_head *muxmodes = &partition->muxmodes;
- + 
- + 	if (!gpio)
- + 		return -EINVAL;
- + 
- + 	list_for_each_entry(e, muxmodes, node) {
- + 		struct omap_mux *m = &e->mux;
- + 		if (gpio == m->gpio) {
- + 			gpio_mux = m;
- + 			found++;
- + 		}
- + 	}
- + 
- + 	if (found == 0) {
- + 		pr_err("%s: Could not set gpio%i\n", __func__, gpio);
- + 		return -ENODEV;
- + 	}
- + 
- + 	if (found > 1) {
- + 		pr_info("%s: Multiple gpio paths (%d) for gpio%i\n", __func__,
- + 			found, gpio);
- + 		return -EINVAL;
- + 	}
- + 
- + 	old_mode = omap_mux_read(partition, gpio_mux->reg_offset);
- + 	mux_mode = val & ~(OMAP_MUX_NR_MODES - 1);
- + 	if (partition->flags & OMAP_MUX_GPIO_IN_MODE3)
- + 		mux_mode |= OMAP_MUX_MODE3;
- + 	else
- + 		mux_mode |= OMAP_MUX_MODE4;
- + 	pr_debug("%s: Setting signal %s.gpio%i 0x%04x -> 0x%04x\n", __func__,
- + 		 gpio_mux->muxnames[0], gpio, old_mode, mux_mode);
- + 	omap_mux_write(partition, mux_mode, gpio_mux->reg_offset);
- + 
- + 	return 0;
- + }
- + 
- + int omap_mux_init_gpio(int gpio, int val)
- + {
- + 	struct omap_mux_partition *partition;
- + 	int ret;
- + 
- + 	list_for_each_entry(partition, &mux_partitions, node) {
- + 		ret = _omap_mux_init_gpio(partition, gpio, val);
- + 		if (!ret)
- + 			return ret;
- + 	}
- + 
- + 	return -ENODEV;
- + }
- + 
- + static int _omap_mux_get_by_name(struct omap_mux_partition *partition,
- + 					const char *muxname,
- + 					struct omap_mux **found_mux)
- + {
- + 	struct omap_mux *mux = NULL;
- + 	struct omap_mux_entry *e;
- + 	const char *mode_name;
- + 	int found = 0, found_mode = 0, mode0_len = 0;
- + 	struct list_head *muxmodes = &partition->muxmodes;
- + 
- + 	mode_name = strchr(muxname, '.');
- + 	if (mode_name) {
- + 		mode0_len = strlen(muxname) - strlen(mode_name);
- + 		mode_name++;
- + 	} else {
- + 		mode_name = muxname;
- + 	}
- + 
- + 	list_for_each_entry(e, muxmodes, node) {
- + 		char *m0_entry;
- + 		int i;
- + 
- + 		mux = &e->mux;
- + 		m0_entry = mux->muxnames[0];
- + 
- + 		/* First check for full name in mode0.muxmode format */
- + 		if (mode0_len && strncmp(muxname, m0_entry, mode0_len))
- + 			continue;
- + 
- + 		/* Then check for muxmode only */
- + 		for (i = 0; i < OMAP_MUX_NR_MODES; i++) {
- + 			char *mode_cur = mux->muxnames[i];
- + 
- + 			if (!mode_cur)
- + 				continue;
- + 
- + 			if (!strcmp(mode_name, mode_cur)) {
- + 				*found_mux = mux;
- + 				found++;
- + 				found_mode = i;
- + 			}
- + 		}
- + 	}
- + 
- + 	if (found == 1) {
- + 		return found_mode;
- + 	}
- + 
- + 	if (found > 1) {
- + 		pr_err("%s: Multiple signal paths (%i) for %s\n", __func__,
- + 		       found, muxname);
- + 		return -EINVAL;
- + 	}
- + 
- + 	pr_err("%s: Could not find signal %s\n", __func__, muxname);
- + 
- + 	return -ENODEV;
- + }
- + 
- + int omap_mux_get_by_name(const char *muxname,
- + 			struct omap_mux_partition **found_partition,
- + 			struct omap_mux **found_mux)
- + {
- + 	struct omap_mux_partition *partition;
- + 
- + 	list_for_each_entry(partition, &mux_partitions, node) {
- + 		struct omap_mux *mux = NULL;
- + 		int mux_mode = _omap_mux_get_by_name(partition, muxname, &mux);
- + 		if (mux_mode < 0)
- + 			continue;
- + 
- + 		*found_partition = partition;
- + 		*found_mux = mux;
- + 
- + 		return mux_mode;
- + 	}
- + 
- + 	return -ENODEV;
- + }
- + 
- + int omap_mux_init_signal(const char *muxname, int val)
- + {
- + 	struct omap_mux_partition *partition = NULL;
- + 	struct omap_mux *mux = NULL;
- + 	u16 old_mode;
- + 	int mux_mode;
- + 
- + 	mux_mode = omap_mux_get_by_name(muxname, &partition, &mux);
- + 	if (mux_mode < 0)
- + 		return mux_mode;
- + 
- + 	old_mode = omap_mux_read(partition, mux->reg_offset);
- + 	mux_mode |= val;
- + 	pr_debug("%s: Setting signal %s 0x%04x -> 0x%04x\n",
- + 			 __func__, muxname, old_mode, mux_mode);
- + 	omap_mux_write(partition, mux_mode, mux->reg_offset);
- + 
- + 	return 0;
- + }
- + 
- + struct omap_hwmod_mux_info *
- + omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads)
- + {
- + 	struct omap_hwmod_mux_info *hmux;
- + 	int i, nr_pads_dynamic = 0;
- + 
- + 	if (!bpads || nr_pads < 1)
- + 		return NULL;
- + 
- + 	hmux = kzalloc(sizeof(struct omap_hwmod_mux_info), GFP_KERNEL);
- + 	if (!hmux)
- + 		goto err1;
- + 
- + 	hmux->nr_pads = nr_pads;
- + 
- + 	hmux->pads = kzalloc(sizeof(struct omap_device_pad) *
- + 				nr_pads, GFP_KERNEL);
- + 	if (!hmux->pads)
- + 		goto err2;
- + 
- + 	for (i = 0; i < hmux->nr_pads; i++) {
- + 		struct omap_mux_partition *partition;
- + 		struct omap_device_pad *bpad = &bpads[i], *pad = &hmux->pads[i];
- + 		struct omap_mux *mux;
- + 		int mux_mode;
- + 
- + 		mux_mode = omap_mux_get_by_name(bpad->name, &partition, &mux);
- + 		if (mux_mode < 0)
- + 			goto err3;
- + 		if (!pad->partition)
- + 			pad->partition = partition;
- + 		if (!pad->mux)
- + 			pad->mux = mux;
- + 
- + 		pad->name = kzalloc(strlen(bpad->name) + 1, GFP_KERNEL);
- + 		if (!pad->name) {
- + 			int j;
- + 
- + 			for (j = i - 1; j >= 0; j--)
- + 				kfree(hmux->pads[j].name);
- + 			goto err3;
- + 		}
- + 		strcpy(pad->name, bpad->name);
- + 
- + 		pad->flags = bpad->flags;
- + 		pad->enable = bpad->enable;
- + 		pad->idle = bpad->idle;
- + 		pad->off = bpad->off;
- + 
- + 		if (pad->flags &
- + 		    (OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP))
- + 			nr_pads_dynamic++;
- + 
- + 		pr_debug("%s: Initialized %s\n", __func__, pad->name);
- + 	}
- + 
- + 	if (!nr_pads_dynamic)
- + 		return hmux;
- + 
- + 	/*
- + 	 * Add pads that need dynamic muxing into a separate list
- + 	 */
- + 
- + 	hmux->nr_pads_dynamic = nr_pads_dynamic;
- + 	hmux->pads_dynamic = kzalloc(sizeof(struct omap_device_pad *) *
- + 					nr_pads_dynamic, GFP_KERNEL);
- + 	if (!hmux->pads_dynamic) {
- + 		pr_err("%s: Could not allocate dynamic pads\n", __func__);
- + 		return hmux;
- + 	}
- + 
- + 	nr_pads_dynamic = 0;
- + 	for (i = 0; i < hmux->nr_pads; i++) {
- + 		struct omap_device_pad *pad = &hmux->pads[i];
- + 
- + 		if (pad->flags &
- + 		    (OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP)) {
- + 			pr_debug("%s: pad %s tagged dynamic\n",
- + 					__func__, pad->name);
- + 			hmux->pads_dynamic[nr_pads_dynamic] = pad;
- + 			nr_pads_dynamic++;
- + 		}
- + 	}
- + 
- + 	return hmux;
- + 
- + err3:
- + 	kfree(hmux->pads);
- + err2:
- + 	kfree(hmux);
- + err1:
- + 	pr_err("%s: Could not allocate device mux entry\n", __func__);
- + 
- + 	return NULL;
- + }
- + 
- + /**
- +  * omap_hwmod_mux_scan_wakeups - omap hwmod scan wakeup pads
- +  * @hmux: Pads for a hwmod
- +  * @mpu_irqs: MPU irq array for a hwmod
- +  *
- +  * Scans the wakeup status of pads for a single hwmod.  If an irq
- +  * array is defined for this mux, the parser will call the registered
- +  * ISRs for corresponding pads, otherwise the parser will stop at the
- +  * first wakeup active pad and return.  Returns true if there is a
- +  * pending and non-served wakeup event for the mux, otherwise false.
- +  */
- + static bool omap_hwmod_mux_scan_wakeups(struct omap_hwmod_mux_info *hmux,
- + 		struct omap_hwmod_irq_info *mpu_irqs)
- + {
- + 	int i, irq;
- + 	unsigned int val;
- + 	u32 handled_irqs = 0;
- + 
- + 	for (i = 0; i < hmux->nr_pads_dynamic; i++) {
- + 		struct omap_device_pad *pad = hmux->pads_dynamic[i];
- + 
- + 		if (!(pad->flags & OMAP_DEVICE_PAD_WAKEUP) ||
- + 		    !(pad->idle & OMAP_WAKEUP_EN))
- + 			continue;
- + 
- + 		val = omap_mux_read(pad->partition, pad->mux->reg_offset);
- + 		if (!(val & OMAP_WAKEUP_EVENT))
- + 			continue;
- + 
- + 		if (!hmux->irqs)
- + 			return true;
- + 
- + 		irq = hmux->irqs[i];
- + 		/* make sure we only handle each irq once */
- + 		if (handled_irqs & 1 << irq)
- + 			continue;
- + 
- + 		handled_irqs |= 1 << irq;
- + 
- + 		generic_handle_irq(mpu_irqs[irq].irq);
- + 	}
- + 
- + 	return false;
- + }
- + 
- + /**
- +  * _omap_hwmod_mux_handle_irq - Process wakeup events for a single hwmod
- +  *
- +  * Checks a single hwmod for every wakeup capable pad to see if there is an
- +  * active wakeup event. If this is the case, call the corresponding ISR.
- +  */
- + static int _omap_hwmod_mux_handle_irq(struct omap_hwmod *oh, void *data)
- + {
- + 	if (!oh->mux || !oh->mux->enabled)
- + 		return 0;
- + 	if (omap_hwmod_mux_scan_wakeups(oh->mux, oh->mpu_irqs))
- + 		generic_handle_irq(oh->mpu_irqs[0].irq);
- + 	return 0;
- + }
- + 
- + /**
- +  * omap_hwmod_mux_handle_irq - Process pad wakeup irqs.
- +  *
- +  * Calls a function for each registered omap_hwmod to check
- +  * pad wakeup statuses.
- +  */
- + static irqreturn_t omap_hwmod_mux_handle_irq(int irq, void *unused)
- + {
- + 	omap_hwmod_for_each(_omap_hwmod_mux_handle_irq, NULL);
- + 	return IRQ_HANDLED;
- + }
- + 
- + /* Assumes the calling function takes care of locking */
- + void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
- + {
- + 	int i;
- + 
- + 	/* Runtime idling of dynamic pads */
- + 	if (state == _HWMOD_STATE_IDLE && hmux->enabled) {
- + 		for (i = 0; i < hmux->nr_pads_dynamic; i++) {
- + 			struct omap_device_pad *pad = hmux->pads_dynamic[i];
- + 			int val = -EINVAL;
- + 
- + 			val = pad->idle;
- + 			omap_mux_write(pad->partition, val,
- + 					pad->mux->reg_offset);
- + 		}
- + 
- + 		return;
- + 	}
- + 
- + 	/* Runtime enabling of dynamic pads */
- + 	if ((state == _HWMOD_STATE_ENABLED) && hmux->pads_dynamic
- + 					&& hmux->enabled) {
- + 		for (i = 0; i < hmux->nr_pads_dynamic; i++) {
- + 			struct omap_device_pad *pad = hmux->pads_dynamic[i];
- + 			int val = -EINVAL;
- + 
- + 			val = pad->enable;
- + 			omap_mux_write(pad->partition, val,
- + 					pad->mux->reg_offset);
- + 		}
- + 
- + 		return;
- + 	}
- + 
- + 	/* Enabling or disabling of all pads */
- + 	for (i = 0; i < hmux->nr_pads; i++) {
- + 		struct omap_device_pad *pad = &hmux->pads[i];
- + 		int flags, val = -EINVAL;
- + 
- + 		flags = pad->flags;
- + 
- + 		switch (state) {
- + 		case _HWMOD_STATE_ENABLED:
- + 			val = pad->enable;
- + 			pr_debug("%s: Enabling %s %x\n", __func__,
- + 					pad->name, val);
- + 			break;
- + 		case _HWMOD_STATE_DISABLED:
- + 			/* Use safe mode unless OMAP_DEVICE_PAD_REMUX */
- + 			if (flags & OMAP_DEVICE_PAD_REMUX)
- + 				val = pad->off;
- + 			else
- + 				val = OMAP_MUX_MODE7;
- + 			pr_debug("%s: Disabling %s %x\n", __func__,
- + 					pad->name, val);
- + 			break;
- + 		default:
- + 			/* Nothing to be done */
- + 			break;
- + 		};
- + 
- + 		if (val >= 0) {
- + 			omap_mux_write(pad->partition, val,
- + 					pad->mux->reg_offset);
- + 			pad->flags = flags;
- + 		}
- + 	}
- + 
- + 	if (state == _HWMOD_STATE_ENABLED)
- + 		hmux->enabled = true;
- + 	else
- + 		hmux->enabled = false;
- + }
- + 
- + #ifdef CONFIG_DEBUG_FS
- + 
- + #define OMAP_MUX_MAX_NR_FLAGS	10
- + #define OMAP_MUX_TEST_FLAG(val, mask)				\
- + 	if (((val) & (mask)) == (mask)) {			\
- + 		i++;						\
- + 		flags[i] =  #mask;				\
- + 	}
- + 
- + /* REVISIT: Add checking for non-optimal mux settings */
- + static inline void omap_mux_decode(struct seq_file *s, u16 val)
- + {
- + 	char *flags[OMAP_MUX_MAX_NR_FLAGS];
- + 	char mode[sizeof("OMAP_MUX_MODE") + 1];
- + 	int i = -1;
- + 
- + 	sprintf(mode, "OMAP_MUX_MODE%d", val & 0x7);
- + 	i++;
- + 	flags[i] = mode;
- + 
- + 	OMAP_MUX_TEST_FLAG(val, OMAP_PIN_OFF_WAKEUPENABLE);
- + 	if (val & OMAP_OFF_EN) {
- + 		if (!(val & OMAP_OFFOUT_EN)) {
- + 			if (!(val & OMAP_OFF_PULL_UP)) {
- + 				OMAP_MUX_TEST_FLAG(val,
- + 					OMAP_PIN_OFF_INPUT_PULLDOWN);
- + 			} else {
- + 				OMAP_MUX_TEST_FLAG(val,
- + 					OMAP_PIN_OFF_INPUT_PULLUP);
- + 			}
- + 		} else {
- + 			if (!(val & OMAP_OFFOUT_VAL)) {
- + 				OMAP_MUX_TEST_FLAG(val,
- + 					OMAP_PIN_OFF_OUTPUT_LOW);
- + 			} else {
- + 				OMAP_MUX_TEST_FLAG(val,
- + 					OMAP_PIN_OFF_OUTPUT_HIGH);
- + 			}
- + 		}
- + 	}
- + 
- + 	if (val & OMAP_INPUT_EN) {
- + 		if (val & OMAP_PULL_ENA) {
- + 			if (!(val & OMAP_PULL_UP)) {
- + 				OMAP_MUX_TEST_FLAG(val,
- + 					OMAP_PIN_INPUT_PULLDOWN);
- + 			} else {
- + 				OMAP_MUX_TEST_FLAG(val, OMAP_PIN_INPUT_PULLUP);
- + 			}
- + 		} else {
- + 			OMAP_MUX_TEST_FLAG(val, OMAP_PIN_INPUT);
- + 		}
- + 	} else {
- + 		i++;
- + 		flags[i] = "OMAP_PIN_OUTPUT";
- + 	}
- + 
- + 	do {
- + 		seq_printf(s, "%s", flags[i]);
- + 		if (i > 0)
- + 			seq_printf(s, " | ");
- + 	} while (i-- > 0);
- + }
- + 
- + static inline void am33xx_mux_decode(struct seq_file *s, u16 val)
- + {
- + 	char *flags[OMAP_MUX_MAX_NR_FLAGS];
- + 	char mode[sizeof("OMAP_MUX_MODE") + 1];
- + 	int i , j;
- + 
- + 	i = j = 0;
- + 	sprintf(mode, "OMAP_MUX_MODE%d", val & 0x7);
- + 	flags[i] = mode;
- + 
- + 	if (val & AM33XX_INPUT_EN) {
- + 		j = 1;
- + 		if (val & AM33XX_PULL_DISA) {
- + 			OMAP_MUX_TEST_FLAG(val, AM33XX_PIN_INPUT);
- + 		} else if (!(val & AM33XX_PULL_UP)) {
- + 			OMAP_MUX_TEST_FLAG(val, AM33XX_PIN_INPUT_PULLDOWN);
- + 		} else {
- + 			OMAP_MUX_TEST_FLAG(val, AM33XX_PIN_INPUT_PULLUP);
- + 		}
- + 	}
- + 	if (val & AM33XX_SLEWCTRL_SLOW) {
- + 		j = 1;
- + 		OMAP_MUX_TEST_FLAG(val, AM33XX_SLEWCTRL_SLOW);
- + 	} else if (!(val & AM33XX_INPUT_EN)) {
- + 		if (val & AM33XX_PIN_OUTPUT_PULLUP) {
- + 			j = 1;
- + 			OMAP_MUX_TEST_FLAG(val, AM33XX_PIN_OUTPUT_PULLUP);
- + 		} else if (val & AM33XX_PULL_DISA) {
- + 			j = 1;
- + 			OMAP_MUX_TEST_FLAG(val, AM33XX_PULL_DISA);
- + 		}
- + 	}
- + 	if (j == 0)
- + 		OMAP_MUX_TEST_FLAG(val, AM33XX_PIN_OUTPUT);
- + 
- + 	for (j = 0; j <= i; j++) {
- + 		seq_printf(s, "%s", flags[j]);
- + 		if (j != i)
- + 			seq_printf(s, " | ");
- + 	}
- + }
- + 
- + #define OMAP_MUX_DEFNAME_LEN	32
- + 
- + static int omap_mux_dbg_board_show(struct seq_file *s, void *unused)
- + {
- + 	struct omap_mux_partition *partition = s->private;
- + 	struct omap_mux_entry *e;
- + 	u8 omap_gen = omap_rev() >> 28;
- + 
- + 	list_for_each_entry(e, &partition->muxmodes, node) {
- + 		struct omap_mux *m = &e->mux;
- + 		char m0_def[OMAP_MUX_DEFNAME_LEN];
- + 		char *m0_name = m->muxnames[0];
- + 		u16 val;
- + 		int i, mode;
- + 
- + 		if (!m0_name)
- + 			continue;
- + 
- + 		/* REVISIT: Needs to be updated if mode0 names get longer */
- + 		for (i = 0; i < OMAP_MUX_DEFNAME_LEN; i++) {
- + 			if (m0_name[i] == '\0') {
- + 				m0_def[i] = m0_name[i];
- + 				break;
- + 			}
- + 			m0_def[i] = toupper(m0_name[i]);
- + 		}
- + 		val = omap_mux_read(partition, m->reg_offset);
- + 		mode = val & OMAP_MUX_MODE7;
- + 		if (mode != 0)
- + 			seq_printf(s, "/* %s */\n", m->muxnames[mode]);
- + 
- + 		/*
- + 		 * XXX: Might be revisited to support differences across
- + 		 * same OMAP generation.
- + 		 */
- + 		seq_printf(s, "OMAP%d_MUX(%s, ", omap_gen, m0_def);
- + 		if (cpu_is_am335x())
- + 			am33xx_mux_decode(s, val);
- + 		else
- + 			omap_mux_decode(s, val);
- + 		seq_printf(s, "),\n");
- + 	}
- + 
- + 	return 0;
- + }
- + 
- + static int omap_mux_dbg_board_open(struct inode *inode, struct file *file)
- + {
- + 	return single_open(file, omap_mux_dbg_board_show, inode->i_private);
- + }
- + 
- + static const struct file_operations omap_mux_dbg_board_fops = {
- + 	.open		= omap_mux_dbg_board_open,
- + 	.read		= seq_read,
- + 	.llseek		= seq_lseek,
- + 	.release	= single_release,
- + };
- + 
- + static struct omap_mux_partition *omap_mux_get_partition(struct omap_mux *mux)
- + {
- + 	struct omap_mux_partition *partition;
- + 
- + 	list_for_each_entry(partition, &mux_partitions, node) {
- + 		struct list_head *muxmodes = &partition->muxmodes;
- + 		struct omap_mux_entry *e;
- + 
- + 		list_for_each_entry(e, muxmodes, node) {
- + 			struct omap_mux *m = &e->mux;
- + 
- + 			if (m == mux)
- + 				return partition;
- + 		}
- + 	}
- + 
- + 	return NULL;
- + }
- + 
- + static int omap_mux_dbg_signal_show(struct seq_file *s, void *unused)
- + {
- + 	struct omap_mux *m = s->private;
- + 	struct omap_mux_partition *partition;
- + 	const char *none = "NA";
- + 	u16 val;
- + 	int mode;
- + 
- + 	partition = omap_mux_get_partition(m);
- + 	if (!partition)
- + 		return 0;
- + 
- + 	val = omap_mux_read(partition, m->reg_offset);
- + 	mode = val & OMAP_MUX_MODE7;
- + 
- + 	seq_printf(s, "name: %s.%s (0x%08x/0x%03x = 0x%04x), b %s, t %s\n",
- + 			m->muxnames[0], m->muxnames[mode],
- + 			partition->phys + m->reg_offset, m->reg_offset, val,
- + 			m->balls[0] ? m->balls[0] : none,
- + 			m->balls[1] ? m->balls[1] : none);
- + 	seq_printf(s, "mode: ");
- + 	if (cpu_is_am335x())
- + 		am33xx_mux_decode(s, val);
- + 	else
- + 		omap_mux_decode(s, val);
- + 	seq_printf(s, "\n");
- + 	seq_printf(s, "signals: %s | %s | %s | %s | %s | %s | %s | %s\n",
- + 			m->muxnames[0] ? m->muxnames[0] : none,
- + 			m->muxnames[1] ? m->muxnames[1] : none,
- + 			m->muxnames[2] ? m->muxnames[2] : none,
- + 			m->muxnames[3] ? m->muxnames[3] : none,
- + 			m->muxnames[4] ? m->muxnames[4] : none,
- + 			m->muxnames[5] ? m->muxnames[5] : none,
- + 			m->muxnames[6] ? m->muxnames[6] : none,
- + 			m->muxnames[7] ? m->muxnames[7] : none);
- + 
- + 	return 0;
- + }
- + 
- + #define OMAP_MUX_MAX_ARG_CHAR  7
- + 
- + static ssize_t omap_mux_dbg_signal_write(struct file *file,
- + 					 const char __user *user_buf,
- + 					 size_t count, loff_t *ppos)
- + {
- + 	char buf[OMAP_MUX_MAX_ARG_CHAR];
- + 	struct seq_file *seqf;
- + 	struct omap_mux *m;
- + 	unsigned long val;
- + 	int buf_size, ret;
- + 	struct omap_mux_partition *partition;
- + 
- + 	if (count > OMAP_MUX_MAX_ARG_CHAR)
- + 		return -EINVAL;
- + 
- + 	memset(buf, 0, sizeof(buf));
- + 	buf_size = min(count, sizeof(buf) - 1);
- + 
- + 	if (copy_from_user(buf, user_buf, buf_size))
- + 		return -EFAULT;
- + 
- + 	ret = strict_strtoul(buf, 0x10, &val);
- + 	if (ret < 0)
- + 		return ret;
- + 
- + 	if (val > 0xffff)
- + 		return -EINVAL;
- + 
- + 	seqf = file->private_data;
- + 	m = seqf->private;
- + 
- + 	partition = omap_mux_get_partition(m);
- + 	if (!partition)
- + 		return -ENODEV;
- + 
- + 	omap_mux_write(partition, (u16)val, m->reg_offset);
- + 	*ppos += count;
- + 
- + 	return count;
- + }
- + 
- + static int omap_mux_dbg_signal_open(struct inode *inode, struct file *file)
- + {
- + 	return single_open(file, omap_mux_dbg_signal_show, inode->i_private);
- + }
- + 
- + static const struct file_operations omap_mux_dbg_signal_fops = {
- + 	.open		= omap_mux_dbg_signal_open,
- + 	.read		= seq_read,
- + 	.write		= omap_mux_dbg_signal_write,
- + 	.llseek		= seq_lseek,
- + 	.release	= single_release,
- + };
- + 
- + static struct dentry *mux_dbg_dir;
- + 
- + static void omap_mux_dbg_create_entry(
- + 				struct omap_mux_partition *partition,
- + 				struct dentry *mux_dbg_dir)
- + {
- + 	struct omap_mux_entry *e;
- + 
- + 	list_for_each_entry(e, &partition->muxmodes, node) {
- + 		struct omap_mux *m = &e->mux;
- + 
- + 		(void)debugfs_create_file(m->muxnames[0], S_IWUSR, mux_dbg_dir,
- + 					  m, &omap_mux_dbg_signal_fops);
- + 	}
- + }
- + 
- + static void omap_mux_dbg_init(void)
- + {
- + 	struct omap_mux_partition *partition;
- + 	static struct dentry *mux_dbg_board_dir;
- + 
- + 	mux_dbg_dir = debugfs_create_dir("omap_mux", NULL);
- + 	if (!mux_dbg_dir)
- + 		return;
- + 
- + 	mux_dbg_board_dir = debugfs_create_dir("board", mux_dbg_dir);
- + 	if (!mux_dbg_board_dir)
- + 		return;
- + 
- + 	list_for_each_entry(partition, &mux_partitions, node) {
- + 		omap_mux_dbg_create_entry(partition, mux_dbg_dir);
- + 		(void)debugfs_create_file(partition->name, S_IRUGO,
- + 					  mux_dbg_board_dir, partition,
- + 					  &omap_mux_dbg_board_fops);
- + 	}
- + }
- + 
- + #else
- + static inline void omap_mux_dbg_init(void)
- + {
- + }
- + #endif	/* CONFIG_DEBUG_FS */
- + 
- + static void omap_mux_free_names(struct omap_mux *m)
- + {
- + 	int i;
- + 
- + 	for (i = 0; i < OMAP_MUX_NR_MODES; i++)
- + 		kfree(m->muxnames[i]);
- + 
- + #ifdef CONFIG_DEBUG_FS
- + 	for (i = 0; i < OMAP_MUX_NR_SIDES; i++)
- + 		kfree(m->balls[i]);
- + #endif
- + 
- + }
- + 
- + /* Free all data except for GPIO pins unless CONFIG_DEBUG_FS is set */
- + static int omap_mux_late_init(void)
- + {
- + 	struct omap_mux_partition *partition;
- + 	int ret;
- + 
- + 	list_for_each_entry(partition, &mux_partitions, node) {
- + 		struct omap_mux_entry *e, *tmp;
- + 		list_for_each_entry_safe(e, tmp, &partition->muxmodes, node) {
- + 			struct omap_mux *m = &e->mux;
- + 			u16 mode = omap_mux_read(partition, m->reg_offset);
- + 
- + 			if (OMAP_MODE_GPIO(mode))
- + 				continue;
- + 
- + #ifndef CONFIG_DEBUG_FS
- + 			mutex_lock(&muxmode_mutex);
- + 			list_del(&e->node);
- + 			mutex_unlock(&muxmode_mutex);
- + 			omap_mux_free_names(m);
- + 			kfree(m);
- + #endif
- + 		}
- + 	}
- + #if 0	/* this will fail anyway becasue PCM is not registerd */
- + 	printk("IRQ num %d\n", omap_prcm_event_to_irq("io"));
- + 
- + 	ret = request_irq(omap_prcm_event_to_irq("io"),
- + 		omap_hwmod_mux_handle_irq, IRQF_SHARED | IRQF_NO_SUSPEND,
- + 			"hwmod_io", omap_mux_late_init);
- + 
- + 	if (ret)
- + 		pr_warning("mux: Failed to setup hwmod io irq %d\n", ret);
- + #endif
- + 	omap_mux_dbg_init();
- + 
- + 	return 0;
- + }
- + late_initcall(omap_mux_late_init);
- + 
- + static void omap_mux_package_fixup(struct omap_mux *p,
- + 					struct omap_mux *superset)
- + {
- + 	while (p->reg_offset !=  OMAP_MUX_TERMINATOR) {
- + 		struct omap_mux *s = superset;
- + 		int found = 0;
- + 
- + 		while (s->reg_offset != OMAP_MUX_TERMINATOR) {
- + 			if (s->reg_offset == p->reg_offset) {
- + 				*s = *p;
- + 				found++;
- + 				break;
- + 			}
- + 			s++;
- + 		}
- + 		if (!found)
- + 			pr_err("%s: Unknown entry offset 0x%x\n", __func__,
- + 			       p->reg_offset);
- + 		p++;
- + 	}
- + }
- + 
- + #ifdef CONFIG_DEBUG_FS
- + 
- + static void omap_mux_package_init_balls(struct omap_ball *b,
- + 				struct omap_mux *superset)
- + {
- + 	while (b->reg_offset != OMAP_MUX_TERMINATOR) {
- + 		struct omap_mux *s = superset;
- + 		int found = 0;
- + 
- + 		while (s->reg_offset != OMAP_MUX_TERMINATOR) {
- + 			if (s->reg_offset == b->reg_offset) {
- + 				s->balls[0] = b->balls[0];
- + 				s->balls[1] = b->balls[1];
- + 				found++;
- + 				break;
- + 			}
- + 			s++;
- + 		}
- + 		if (!found)
- + 			pr_err("%s: Unknown ball offset 0x%x\n", __func__,
- + 			       b->reg_offset);
- + 		b++;
- + 	}
- + }
- + 
- + #else	/* CONFIG_DEBUG_FS */
- + 
- + static inline void omap_mux_package_init_balls(struct omap_ball *b,
- + 					struct omap_mux *superset)
- + {
- + }
- + 
- + #endif	/* CONFIG_DEBUG_FS */
- + 
- + static int omap_mux_setup(char *options)
- + {
- + 	if (!options)
- + 		return 0;
- + 
- + 	omap_mux_options = options;
- + 
- + 	return 1;
- + }
- + __setup("omap_mux=", omap_mux_setup);
- + 
- + /*
- +  * Note that the omap_mux=some.signal1=0x1234,some.signal2=0x1234
- +  * cmdline options only override the bootloader values.
- +  * During development, please enable CONFIG_DEBUG_FS, and use the
- +  * signal specific entries under debugfs.
- +  */
- + static void omap_mux_set_cmdline_signals(void)
- + {
- + 	char *options, *next_opt, *token;
- + 
- + 	if (!omap_mux_options)
- + 		return;
- + 
- + 	options = kstrdup(omap_mux_options, GFP_KERNEL);
- + 	if (!options)
- + 		return;
- + 
- + 	next_opt = options;
- + 
- + 	while ((token = strsep(&next_opt, ",")) != NULL) {
- + 		char *keyval, *name;
- + 		unsigned long val;
- + 
- + 		keyval = token;
- + 		name = strsep(&keyval, "=");
- + 		if (name) {
- + 			int res;
- + 
- + 			res = strict_strtoul(keyval, 0x10, &val);
- + 			if (res < 0)
- + 				continue;
- + 
- + 			omap_mux_init_signal(name, (u16)val);
- + 		}
- + 	}
- + 
- + 	kfree(options);
- + }
- + 
- + static int omap_mux_copy_names(struct omap_mux *src,
- + 				      struct omap_mux *dst)
- + {
- + 	int i;
- + 
- + 	for (i = 0; i < OMAP_MUX_NR_MODES; i++) {
- + 		if (src->muxnames[i]) {
- + 			dst->muxnames[i] = kstrdup(src->muxnames[i],
- + 						   GFP_KERNEL);
- + 			if (!dst->muxnames[i])
- + 				goto free;
- + 		}
- + 	}
- + 
- + #ifdef CONFIG_DEBUG_FS
- + 	for (i = 0; i < OMAP_MUX_NR_SIDES; i++) {
- + 		if (src->balls[i]) {
- + 			dst->balls[i] = kstrdup(src->balls[i], GFP_KERNEL);
- + 			if (!dst->balls[i])
- + 				goto free;
- + 		}
- + 	}
- + #endif
- + 
- + 	return 0;
- + 
- + free:
- + 	omap_mux_free_names(dst);
- + 	return -ENOMEM;
- + 
- + }
- + 
- + #endif	/* CONFIG_OMAP_MUX */
- + 
- + static struct omap_mux *omap_mux_get_by_gpio(
- + 				struct omap_mux_partition *partition,
- + 				int gpio)
- + {
- + 	struct omap_mux_entry *e;
- + 	struct omap_mux *ret = NULL;
- + 
- + 	list_for_each_entry(e, &partition->muxmodes, node) {
- + 		struct omap_mux *m = &e->mux;
- + 		if (m->gpio == gpio) {
- + 			ret = m;
- + 			break;
- + 		}
- + 	}
- + 
- + 	return ret;
- + }
- + 
- + /* Needed for dynamic muxing of GPIO pins for off-idle */
- + u16 omap_mux_get_gpio(int gpio)
- + {
- + 	struct omap_mux_partition *partition;
- + 	struct omap_mux *m = NULL;
- + 
- + 	list_for_each_entry(partition, &mux_partitions, node) {
- + 		m = omap_mux_get_by_gpio(partition, gpio);
- + 		if (m)
- + 			return omap_mux_read(partition, m->reg_offset);
- + 	}
- + 
- + 	if (!m || m->reg_offset == OMAP_MUX_TERMINATOR)
- + 		pr_err("%s: Could not get gpio%i\n", __func__, gpio);
- + 
- + 	return OMAP_MUX_TERMINATOR;
- + }
- + 
- + /* Needed for dynamic muxing of GPIO pins for off-idle */
- + void omap_mux_set_gpio(u16 val, int gpio)
- + {
- + 	struct omap_mux_partition *partition;
- + 	struct omap_mux *m = NULL;
- + 
- + 	list_for_each_entry(partition, &mux_partitions, node) {
- + 		m = omap_mux_get_by_gpio(partition, gpio);
- + 		if (m) {
- + 			omap_mux_write(partition, val, m->reg_offset);
- + 			return;
- + 		}
- + 	}
- + 
- + 	if (!m || m->reg_offset == OMAP_MUX_TERMINATOR)
- + 		pr_err("%s: Could not set gpio%i\n", __func__, gpio);
- + }
- + 
- + static struct omap_mux * omap_mux_list_add(
- + 					struct omap_mux_partition *partition,
- + 					struct omap_mux *src)
- + {
- + 	struct omap_mux_entry *entry;
- + 	struct omap_mux *m;
- + 
- + 	entry = kzalloc(sizeof(struct omap_mux_entry), GFP_KERNEL);
- + 	if (!entry)
- + 		return NULL;
- + 
- + 	m = &entry->mux;
- + 	entry->mux = *src;
- + 
- + #ifdef CONFIG_OMAP_MUX
- + 	if (omap_mux_copy_names(src, m)) {
- + 		kfree(entry);
- + 		return NULL;
- + 	}
- + #endif
- + 
- + 	mutex_lock(&muxmode_mutex);
- + 	list_add_tail(&entry->node, &partition->muxmodes);
- + 	mutex_unlock(&muxmode_mutex);
- + 
- + 	return m;
- + }
- + 
- + /*
- +  * Note if CONFIG_OMAP_MUX is not selected, we will only initialize
- +  * the GPIO to mux offset mapping that is needed for dynamic muxing
- +  * of GPIO pins for off-idle.
- +  */
- + static void omap_mux_init_list(struct omap_mux_partition *partition,
- + 				      struct omap_mux *superset)
- + {
- + 	while (superset->reg_offset !=  OMAP_MUX_TERMINATOR) {
- + 		struct omap_mux *entry;
- + 
- + #ifdef CONFIG_OMAP_MUX
- + 		if (!superset->muxnames || !superset->muxnames[0]) {
- + 			superset++;
- + 			continue;
- + 		}
- + #else
- + 		/* Skip pins that are not muxed as GPIO by bootloader */
- + 		if (!OMAP_MODE_GPIO(omap_mux_read(partition,
- + 				    superset->reg_offset))) {
- + 			superset++;
- + 			continue;
- + 		}
- + #endif
- + 
- + 		entry = omap_mux_list_add(partition, superset);
- + 		if (!entry) {
- + 			pr_err("%s: Could not add entry\n", __func__);
- + 			return;
- + 		}
- + 		superset++;
- + 	}
- + }
- + 
- + #ifdef CONFIG_OMAP_MUX
- + 
- + static void omap_mux_init_package(struct omap_mux *superset,
- + 				  struct omap_mux *package_subset,
- + 				  struct omap_ball *package_balls)
- + {
- + 	if (package_subset)
- + 		omap_mux_package_fixup(package_subset, superset);
- + 	if (package_balls)
- + 		omap_mux_package_init_balls(package_balls, superset);
- + }
- + 
- + static void omap_mux_init_signals(struct omap_mux_partition *partition,
- + 				  struct omap_board_mux *board_mux)
- + {
- + 	omap_mux_set_cmdline_signals();
- + 	omap_mux_write_array(partition, board_mux);
- + }
- + 
- + #else
- + 
- + static void omap_mux_init_package(struct omap_mux *superset,
- + 				  struct omap_mux *package_subset,
- + 				  struct omap_ball *package_balls)
- + {
- + }
- + 
- + static void omap_mux_init_signals(struct omap_mux_partition *partition,
- + 				  struct omap_board_mux *board_mux)
- + {
- + }
- + 
- + #endif
- + 
- + static u32 mux_partitions_cnt;
- + 
- + int omap_mux_init(const char *name, u32 flags,
- + 			 u32 mux_pbase, u32 mux_size,
- + 			 struct omap_mux *superset,
- + 			 struct omap_mux *package_subset,
- + 			 struct omap_board_mux *board_mux,
- + 			 struct omap_ball *package_balls)
- + {
- + 	struct omap_mux_partition *partition;
- + 
- + 	partition = kzalloc(sizeof(struct omap_mux_partition), GFP_KERNEL);
- + 	if (!partition)
- + 		return -ENOMEM;
- + 
- + 	partition->name = name;
- + 	partition->flags = flags;
- + 	partition->size = mux_size;
- + 	partition->phys = mux_pbase;
- + 	partition->base = ioremap(mux_pbase, mux_size);
- + 	if (!partition->base) {
- + 		pr_err("%s: Could not ioremap mux partition at 0x%08x\n",
- + 			__func__, partition->phys);
- + 		kfree(partition);
- + 		return -ENODEV;
- + 	}
- + 
- + 	INIT_LIST_HEAD(&partition->muxmodes);
- + 
- + 	list_add_tail(&partition->node, &mux_partitions);
- + 	mux_partitions_cnt++;
- + 	pr_info("%s: Add partition: #%d: %s, flags: %x\n", __func__,
- + 		mux_partitions_cnt, partition->name, partition->flags);
- + 
- + 	omap_mux_init_package(superset, package_subset, package_balls);
- + 	omap_mux_init_list(partition, superset);
- + 	omap_mux_init_signals(partition, board_mux);
- + 
- + 	return 0;
- + }
- + 
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/mux.h linux-3.2.1/arch/arm/mach-ckb_3352/mux.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/mux.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/mux.h	2014-05-15 13:25:13.943902860 +0900
- ***************
- *** 0 ****
- --- 1,370 ----
- + /*
- +  * Copyright (C) 2009 Nokia
- +  * Copyright (C) 2009-2010 Texas Instruments
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #include "mux33xx.h"
- + 
- + #define OMAP_MUX_TERMINATOR	0xffff
- + 
- + /* 34xx mux mode options for each pin. See TRM for options */
- + #define OMAP_MUX_MODE0      0
- + #define OMAP_MUX_MODE1      1
- + #define OMAP_MUX_MODE2      2
- + #define OMAP_MUX_MODE3      3
- + #define OMAP_MUX_MODE4      4
- + #define OMAP_MUX_MODE5      5
- + #define OMAP_MUX_MODE6      6
- + #define OMAP_MUX_MODE7      7
- + 
- + /* 24xx/34xx mux bit defines */
- + #define OMAP_PULL_ENA			(1 << 3)
- + #define OMAP_PULL_UP			(1 << 4)
- + #define OMAP_ALTELECTRICALSEL		(1 << 5)
- + 
- + /* 34xx specific mux bit defines */
- + #define OMAP_INPUT_EN			(1 << 8)
- + #define OMAP_OFF_EN			(1 << 9)
- + #define OMAP_OFFOUT_EN			(1 << 10)
- + #define OMAP_OFFOUT_VAL			(1 << 11)
- + #define OMAP_OFF_PULL_EN		(1 << 12)
- + #define OMAP_OFF_PULL_UP		(1 << 13)
- + #define OMAP_WAKEUP_EN			(1 << 14)
- + 
- + /* 44xx specific mux bit defines */
- + #define OMAP_WAKEUP_EVENT		(1 << 15)
- + 
- + /* am33xx specific mux bit defines */
- + #define AM33XX_SLEWCTRL_FAST		(0 << 6)
- + #define AM33XX_SLEWCTRL_SLOW		(1 << 6)
- + #define AM33XX_INPUT_EN			(1 << 5)
- + #define AM33XX_PULL_UP			(1 << 4)
- + /* bit 3: 0 - enable, 1 - disable for pull enable */
- + #define AM33XX_PULL_DISA		(1 << 3)
- + #define AM33XX_PULL_ENBL		(0 << 3)
- + 
- + /* Definition of output pin could have pull disabled, but
- +  * this has not been done due to two reasons
- +  * 1. AM33XX_MUX will take care of it
- +  * 2. If pull was disabled for out macro, combining out & in pull on macros
- +  *    would disable pull resistor and AM33XX_MUX cannot take care of the
- +  *    correct pull setting and unintentionally pull would get disabled
- +  */
- + #define	AM33XX_PIN_OUTPUT		(0)
- + #define	AM33XX_PIN_OUTPUT_PULLUP	(AM33XX_PULL_UP)
- + #define	AM33XX_PIN_INPUT		(AM33XX_INPUT_EN | AM33XX_PULL_DISA)
- + #define	AM33XX_PIN_INPUT_PULLUP		(AM33XX_INPUT_EN | AM33XX_PULL_UP)
- + #define	AM33XX_PIN_INPUT_PULLDOWN	(AM33XX_INPUT_EN)
- + 
- + /* Active pin states */
- + #define OMAP_PIN_OUTPUT			0
- + #define OMAP_PIN_INPUT			OMAP_INPUT_EN
- + #define OMAP_PIN_INPUT_PULLUP		(OMAP_PULL_ENA | OMAP_INPUT_EN \
- + 						| OMAP_PULL_UP)
- + #define OMAP_PIN_INPUT_PULLDOWN		(OMAP_PULL_ENA | OMAP_INPUT_EN)
- + 
- + /* Off mode states */
- + #define OMAP_PIN_OFF_NONE		0
- + #define OMAP_PIN_OFF_OUTPUT_HIGH	(OMAP_OFF_EN | OMAP_OFFOUT_EN \
- + 						| OMAP_OFFOUT_VAL)
- + #define OMAP_PIN_OFF_OUTPUT_LOW		(OMAP_OFF_EN | OMAP_OFFOUT_EN)
- + #define OMAP_PIN_OFF_INPUT_PULLUP	(OMAP_OFF_EN | OMAP_OFF_PULL_EN \
- + 						| OMAP_OFF_PULL_UP)
- + #define OMAP_PIN_OFF_INPUT_PULLDOWN	(OMAP_OFF_EN | OMAP_OFF_PULL_EN)
- + #define OMAP_PIN_OFF_WAKEUPENABLE	OMAP_WAKEUP_EN
- + 
- + #define OMAP_MODE_GPIO(x)	(((x) & OMAP_MUX_MODE7) == OMAP_MUX_MODE4)
- + 
- + /* Flags for omapX_mux_init */
- + #define OMAP_PACKAGE_MASK		0xffff
- + #define OMAP_PACKAGE_CBS		8		/* 547-pin 0.40 0.40 */
- + #define OMAP_PACKAGE_CBL		7		/* 547-pin 0.40 0.40 */
- + #define OMAP_PACKAGE_CBP		6		/* 515-pin 0.40 0.50 */
- + #define OMAP_PACKAGE_CUS		5		/* 423-pin 0.65 */
- + #define OMAP_PACKAGE_CBB		4		/* 515-pin 0.40 0.50 */
- + #define OMAP_PACKAGE_CBC		3		/* 515-pin 0.50 0.65 */
- + #define OMAP_PACKAGE_ZAC		2		/* 24xx 447-pin POP */
- + #define OMAP_PACKAGE_ZAF		1		/* 2420 447-pin SIP */
- + 
- + 
- + #define OMAP_MUX_NR_MODES		8		/* Available modes */
- + #define OMAP_MUX_NR_SIDES		2		/* Bottom & top */
- + 
- + /*
- +  * omap_mux_init flags definition:
- +  *
- +  * OMAP_MUX_REG_8BIT: Ensure that access to padconf is done in 8 bits.
- +  * The default value is 16 bits.
- +  * OMAP_MUX_GPIO_IN_MODE3: The GPIO is selected in mode3.
- +  * The default is mode4.
- +  */
- + #define OMAP_MUX_REG_8BIT		(1 << 0)
- + #define OMAP_MUX_GPIO_IN_MODE3		(1 << 1)
- + 
- + /**
- +  * struct omap_board_data - board specific device data
- +  * @id: instance id
- +  * @flags: additional flags for platform init code
- +  * @pads: array of device specific pads
- +  * @pads_cnt: ARRAY_SIZE() of pads
- +  */
- + struct omap_board_data {
- + 	int			id;
- + 	u32			flags;
- + 	struct omap_device_pad	*pads;
- + 	int			pads_cnt;
- + };
- + 
- + /**
- +  * struct mux_partition - contain partition related information
- +  * @name: name of the current partition
- +  * @flags: flags specific to this partition
- +  * @phys: physical address
- +  * @size: partition size
- +  * @base: virtual address after ioremap
- +  * @muxmodes: list of nodes that belong to a partition
- +  * @node: list node for the partitions linked list
- +  */
- + struct omap_mux_partition {
- + 	const char		*name;
- + 	u32			flags;
- + 	u32			phys;
- + 	u32			size;
- + 	void __iomem		*base;
- + 	struct list_head	muxmodes;
- + 	struct list_head	node;
- + };
- + 
- + /**
- +  * struct omap_mux - data for omap mux register offset and it's value
- +  * @reg_offset:	mux register offset from the mux base
- +  * @gpio:	GPIO number
- +  * @muxnames:	available signal modes for a ball
- +  * @balls:	available balls on the package
- +  * @partition:	mux partition
- +  */
- + struct omap_mux {
- + 	u16	reg_offset;
- + 	u16	gpio;
- + #ifdef CONFIG_OMAP_MUX
- + 	char	*muxnames[OMAP_MUX_NR_MODES];
- + #ifdef CONFIG_DEBUG_FS
- + 	char	*balls[OMAP_MUX_NR_SIDES];
- + #endif
- + #endif
- + };
- + 
- + /**
- +  * struct omap_ball - data for balls on omap package
- +  * @reg_offset:	mux register offset from the mux base
- +  * @balls:	available balls on the package
- +  */
- + struct omap_ball {
- + 	u16	reg_offset;
- + 	char	*balls[OMAP_MUX_NR_SIDES];
- + };
- + 
- + /**
- +  * struct omap_board_mux - data for initializing mux registers
- +  * @reg_offset:	mux register offset from the mux base
- +  * @mux_value:	desired mux value to set
- +  */
- + struct omap_board_mux {
- + 	u16	reg_offset;
- + 	u16	value;
- + };
- + 
- + #define OMAP_DEVICE_PAD_REMUX		BIT(1)	/* Dynamically remux a pad,
- + 						   needs enable, idle and off
- + 						   values */
- + #define OMAP_DEVICE_PAD_WAKEUP		BIT(0)	/* Pad is wake-up capable */
- + 
- + /**
- +  * struct omap_device_pad - device specific pad configuration
- +  * @name:		signal name
- +  * @flags:		pad specific runtime flags
- +  * @enable:		runtime value for a pad
- +  * @idle:		idle value for a pad
- +  * @off:		off value for a pad, defaults to safe mode
- +  * @partition:		mux partition
- +  * @mux:		mux register
- +  */
- + struct omap_device_pad {
- + 	char				*name;
- + 	u8				flags;
- + 	u16				enable;
- + 	u16				idle;
- + 	u16				off;
- + 	struct omap_mux_partition	*partition;
- + 	struct omap_mux			*mux;
- + };
- + 
- + struct omap_hwmod_mux_info;
- + 
- + #define OMAP_MUX_STATIC(signal, mode)					\
- + {									\
- + 	.name	= (signal),						\
- + 	.enable	= (mode),						\
- + }
- + 
- + #if defined(CONFIG_OMAP_MUX)
- + 
- + /**
- +  * omap_mux_init_gpio - initialize a signal based on the GPIO number
- +  * @gpio:		GPIO number
- +  * @val:		Options for the mux register value
- +  */
- + int omap_mux_init_gpio(int gpio, int val);
- + 
- + /**
- +  * omap_mux_init_signal - initialize a signal based on the signal name
- +  * @muxname:		Mux name in mode0_name.signal_name format
- +  * @val:		Options for the mux register value
- +  */
- + int omap_mux_init_signal(const char *muxname, int val);
- + 
- + /**
- +  * omap_hwmod_mux_init - initialize hwmod specific mux data
- +  * @bpads:		Board specific device signal names
- +  * @nr_pads:		Number of signal names for the device
- +  */
- + extern struct omap_hwmod_mux_info *
- + omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads);
- + 
- + /**
- +  * omap_hwmod_mux - omap hwmod specific pin muxing
- +  * @hmux:		Pads for a hwmod
- +  * @state:		Desired _HWMOD_STATE
- +  *
- +  * Called only from omap_hwmod.c, do not use.
- +  */
- + void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state);
- + 
- + #else
- + 
- + static inline int omap_mux_init_gpio(int gpio, int val)
- + {
- + 	return 0;
- + }
- + static inline int omap_mux_init_signal(char *muxname, int val)
- + {
- + 	return 0;
- + }
- + 
- + static inline struct omap_hwmod_mux_info *
- + omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads)
- + {
- + 	return NULL;
- + }
- + 
- + static inline void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
- + {
- + }
- + 
- + static struct omap_board_mux *board_mux __initdata __maybe_unused;
- + 
- + #endif
- + 
- + /**
- +  * omap_mux_get_gpio() - get mux register value based on GPIO number
- +  * @gpio:		GPIO number
- +  *
- +  */
- + u16 omap_mux_get_gpio(int gpio);
- + 
- + /**
- +  * omap_mux_set_gpio() - set mux register value based on GPIO number
- +  * @val:		New mux register value
- +  * @gpio:		GPIO number
- +  *
- +  */
- + void omap_mux_set_gpio(u16 val, int gpio);
- + 
- + /**
- +  * omap_mux_get() - get a mux partition by name
- +  * @name:		Name of the mux partition
- +  *
- +  */
- + struct omap_mux_partition *omap_mux_get(const char *name);
- + 
- + /**
- +  * omap_mux_read() - read mux register
- +  * @partition:		Mux partition
- +  * @mux_offset:		Offset of the mux register
- +  *
- +  */
- + u16 omap_mux_read(struct omap_mux_partition *p, u16 mux_offset);
- + 
- + /**
- +  * omap_mux_write() - write mux register
- +  * @partition:		Mux partition
- +  * @val:		New mux register value
- +  * @mux_offset:		Offset of the mux register
- +  *
- +  * This should be only needed for dynamic remuxing of non-gpio signals.
- +  */
- + void omap_mux_write(struct omap_mux_partition *p, u16 val, u16 mux_offset);
- + 
- + /**
- +  * omap_mux_write_array() - write an array of mux registers
- +  * @partition:		Mux partition
- +  * @board_mux:		Array of mux registers terminated by MAP_MUX_TERMINATOR
- +  *
- +  * This should be only needed for dynamic remuxing of non-gpio signals.
- +  */
- + void omap_mux_write_array(struct omap_mux_partition *p,
- + 			  struct omap_board_mux *board_mux);
- + 
- + /**
- +  * omap2420_mux_init() - initialize mux system with board specific set
- +  * @board_mux:		Board specific mux table
- +  * @flags:		OMAP package type used for the board
- +  */
- + int omap2420_mux_init(struct omap_board_mux *board_mux, int flags);
- + 
- + /**
- +  * omap2430_mux_init() - initialize mux system with board specific set
- +  * @board_mux:		Board specific mux table
- +  * @flags:		OMAP package type used for the board
- +  */
- + int omap2430_mux_init(struct omap_board_mux *board_mux, int flags);
- + 
- + /**
- +  * omap3_mux_init() - initialize mux system with board specific set
- +  * @board_mux:		Board specific mux table
- +  * @flags:		OMAP package type used for the board
- +  */
- + int omap3_mux_init(struct omap_board_mux *board_mux, int flags);
- + 
- + /**
- +  * omap4_mux_init() - initialize mux system with board specific set
- +  * @board_subset:	Board specific mux table
- +  * @board_wkup_subset:	Board specific mux table for wakeup instance
- +  * @flags:		OMAP package type used for the board
- +  */
- + int omap4_mux_init(struct omap_board_mux *board_subset,
- + 	struct omap_board_mux *board_wkup_subset, int flags);
- + 
- + /**
- +  * am33xx_mux_init() - initialize mux system along with board specific set
- +  * @board_mux:		Board specific mux table
- +  */
- + int am33xx_mux_init(struct omap_board_mux *board_mux);
- + 
- + /**
- +  * omap_mux_init - private mux init function, do not call
- +  */
- + int omap_mux_init(const char *name, u32 flags,
- + 		  u32 mux_pbase, u32 mux_size,
- + 		  struct omap_mux *superset,
- + 		  struct omap_mux *package_subset,
- + 		  struct omap_board_mux *board_mux,
- + 		  struct omap_ball *package_balls);
- + 
- + int omap_mux_get_by_name(const char *muxname,
- + 			struct omap_mux_partition **found_partition,
- + 			struct omap_mux **found_mux);
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_hwmod_2xxx_3xxx_ipblock_data.c linux-3.2.1/arch/arm/mach-ckb_3352/omap_hwmod_2xxx_3xxx_ipblock_data.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_hwmod_2xxx_3xxx_ipblock_data.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/omap_hwmod_2xxx_3xxx_ipblock_data.c	2014-05-15 13:25:13.943902860 +0900
- ***************
- *** 0 ****
- --- 1,325 ----
- + /*
- +  * omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3
- +  *
- +  * Copyright (C) 2011 Nokia Corporation
- +  * Paul Walmsley
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + #include <plat/omap_hwmod.h>
- + #include <plat/serial.h>
- + #include <plat/dma.h>
- + #include <plat/common.h>
- + 
- + #include <mach/irqs.h>
- + 
- + #include "omap_hwmod_common_data.h"
- + 
- + /* UART */
- + 
- + static struct omap_hwmod_class_sysconfig omap2_uart_sysc = {
- + 	.rev_offs	= 0x50,
- + 	.sysc_offs	= 0x54,
- + 	.syss_offs	= 0x58,
- + 	.sysc_flags	= (SYSC_HAS_SIDLEMODE |
- + 			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
- + 			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
- + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- + 	.sysc_fields	= &omap_hwmod_sysc_type1,
- + };
- + 
- + struct omap_hwmod_class omap2_uart_class = {
- + 	.name	= "uart",
- + 	.sysc	= &omap2_uart_sysc,
- + };
- + 
- + /*
- +  * 'dss' class
- +  * display sub-system
- +  */
- + 
- + static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
- + 	.rev_offs	= 0x0000,
- + 	.sysc_offs	= 0x0010,
- + 	.syss_offs	= 0x0014,
- + 	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
- + 			   SYSS_HAS_RESET_STATUS),
- + 	.sysc_fields	= &omap_hwmod_sysc_type1,
- + };
- + 
- + struct omap_hwmod_class omap2_dss_hwmod_class = {
- + 	.name	= "dss",
- + 	.sysc	= &omap2_dss_sysc,
- + 	.reset	= omap_dss_reset,
- + };
- + 
- + /*
- +  * 'dispc' class
- +  * display controller
- +  */
- + 
- + static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
- + 	.rev_offs	= 0x0000,
- + 	.sysc_offs	= 0x0010,
- + 	.syss_offs	= 0x0014,
- + 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
- + 			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
- + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- + 			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
- + 	.sysc_fields	= &omap_hwmod_sysc_type1,
- + };
- + 
- + struct omap_hwmod_class omap2_dispc_hwmod_class = {
- + 	.name	= "dispc",
- + 	.sysc	= &omap2_dispc_sysc,
- + };
- + 
- + /*
- +  * 'rfbi' class
- +  * remote frame buffer interface
- +  */
- + 
- + static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = {
- + 	.rev_offs	= 0x0000,
- + 	.sysc_offs	= 0x0010,
- + 	.syss_offs	= 0x0014,
- + 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- + 			   SYSC_HAS_AUTOIDLE),
- + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- + 	.sysc_fields	= &omap_hwmod_sysc_type1,
- + };
- + 
- + struct omap_hwmod_class omap2_rfbi_hwmod_class = {
- + 	.name	= "rfbi",
- + 	.sysc	= &omap2_rfbi_sysc,
- + };
- + 
- + /*
- +  * 'venc' class
- +  * video encoder
- +  */
- + 
- + struct omap_hwmod_class omap2_venc_hwmod_class = {
- + 	.name = "venc",
- + };
- + 
- + 
- + /* Common DMA request line data */
- + struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {
- + 	{ .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
- + 	{ .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
- + 	{ .dma_req = -1 }
- + };
- + 
- + struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {
- + 	{ .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
- + 	{ .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
- + 	{ .dma_req = -1 }
- + };
- + 
- + struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {
- + 	{ .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
- + 	{ .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
- + 	{ .dma_req = -1 }
- + };
- + 
- + struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {
- + 	{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
- + 	{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
- + 	{ .dma_req = -1 }
- + };
- + 
- + struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {
- + 	{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
- + 	{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
- + 	{ .dma_req = -1 }
- + };
- + 
- + struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = {
- + 	{ .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
- + 	{ .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
- + 	{ .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
- + 	{ .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
- + 	{ .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
- + 	{ .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
- + 	{ .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
- + 	{ .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
- + 	{ .dma_req = -1 }
- + };
- + 
- + struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = {
- + 	{ .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
- + 	{ .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
- + 	{ .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
- + 	{ .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
- + 	{ .dma_req = -1 }
- + };
- + 
- + struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = {
- + 	{ .name = "rx", .dma_req = 32 },
- + 	{ .name = "tx", .dma_req = 31 },
- + 	{ .dma_req = -1 }
- + };
- + 
- + struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = {
- + 	{ .name = "rx", .dma_req = 34 },
- + 	{ .name = "tx", .dma_req = 33 },
- + 	{ .dma_req = -1 }
- + };
- + 
- + struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = {
- + 	{ .name = "rx", .dma_req = 18 },
- + 	{ .name = "tx", .dma_req = 17 },
- + 	{ .dma_req = -1 }
- + };
- + 
- + /* Other IP block data */
- + 
- + 
- + /*
- +  * omap_hwmod class data
- +  */
- + 
- + struct omap_hwmod_class l3_hwmod_class = {
- + 	.name = "l3"
- + };
- + 
- + struct omap_hwmod_class l4_hwmod_class = {
- + 	.name = "l4"
- + };
- + 
- + struct omap_hwmod_class mpu_hwmod_class = {
- + 	.name = "mpu"
- + };
- + 
- + struct omap_hwmod_class iva_hwmod_class = {
- + 	.name = "iva"
- + };
- + 
- + /* Common MPU IRQ line data */
- + 
- + struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = {
- + 	{ .irq = 37, },
- + 	{ .irq = -1 }
- + };
- + 
- + struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = {
- + 	{ .irq = 38, },
- + 	{ .irq = -1 }
- + };
- + 
- + struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = {
- + 	{ .irq = 39, },
- + 	{ .irq = -1 }
- + };
- + 
- + struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = {
- + 	{ .irq = 40, },
- + 	{ .irq = -1 }
- + };
- + 
- + struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = {
- + 	{ .irq = 41, },
- + 	{ .irq = -1 }
- + };
- + 
- + struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = {
- + 	{ .irq = 42, },
- + 	{ .irq = -1 }
- + };
- + 
- + struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = {
- + 	{ .irq = 43, },
- + 	{ .irq = -1 }
- + };
- + 
- + struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = {
- + 	{ .irq = 44, },
- + 	{ .irq = -1 }
- + };
- + 
- + struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = {
- + 	{ .irq = 45, },
- + 	{ .irq = -1 }
- + };
- + 
- + struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = {
- + 	{ .irq = 46, },
- + 	{ .irq = -1 }
- + };
- + 
- + struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = {
- + 	{ .irq = 47, },
- + 	{ .irq = -1 }
- + };
- + 
- + struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = {
- + 	{ .irq = INT_24XX_UART1_IRQ, },
- + 	{ .irq = -1 }
- + };
- + 
- + struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = {
- + 	{ .irq = INT_24XX_UART2_IRQ, },
- + 	{ .irq = -1 }
- + };
- + 
- + struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = {
- + 	{ .irq = INT_24XX_UART3_IRQ, },
- + 	{ .irq = -1 }
- + };
- + 
- + struct omap_hwmod_irq_info omap2_dispc_irqs[] = {
- + 	{ .irq = 25 },
- + 	{ .irq = -1 }
- + };
- + 
- + struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = {
- + 	{ .irq = INT_24XX_I2C1_IRQ, },
- + 	{ .irq = -1 }
- + };
- + 
- + struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = {
- + 	{ .irq = INT_24XX_I2C2_IRQ, },
- + 	{ .irq = -1 }
- + };
- + 
- + struct omap_hwmod_irq_info omap2_gpio1_irqs[] = {
- + 	{ .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
- + 	{ .irq = -1 }
- + };
- + 
- + struct omap_hwmod_irq_info omap2_gpio2_irqs[] = {
- + 	{ .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
- + 	{ .irq = -1 }
- + };
- + 
- + struct omap_hwmod_irq_info omap2_gpio3_irqs[] = {
- + 	{ .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
- + 	{ .irq = -1 }
- + };
- + 
- + struct omap_hwmod_irq_info omap2_gpio4_irqs[] = {
- + 	{ .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
- + 	{ .irq = -1 }
- + };
- + 
- + struct omap_hwmod_irq_info omap2_dma_system_irqs[] = {
- + 	{ .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
- + 	{ .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
- + 	{ .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
- + 	{ .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
- + 	{ .irq = -1 }
- + };
- + 
- + struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = {
- + 	{ .irq = 65 },
- + 	{ .irq = -1 }
- + };
- + 
- + struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
- + 	{ .irq = 66 },
- + 	{ .irq = -1 }
- + };
- + 
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_hwmod_33xx_data.c linux-3.2.1/arch/arm/mach-ckb_3352/omap_hwmod_33xx_data.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_hwmod_33xx_data.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/omap_hwmod_33xx_data.c	2014-05-15 13:25:13.951232466 +0900
- ***************
- *** 0 ****
- --- 1,3742 ----
- + /*
- +  * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
- +  *
- +  * Copyright (C) {2011} Texas Instruments Incorporated - http://www.ti.com/
- +  *
- +  * This file is automatically generated from the AM33XX hardware databases.
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #include <linux/io.h>
- + #include <linux/slab.h>
- + #include <linux/err.h>
- + #include <linux/errno.h>
- + 
- + #include <plat/omap_hwmod.h>
- + #include <plat/cpu.h>
- + #include <plat/gpio.h>
- + #include <plat/dma.h>
- + #include <plat/mmc.h>
- + #include <plat/mcspi.h>
- + #include <plat/i2c.h>
- + #include <plat/clock.h>
- + #include <plat/prcm.h>
- + 
- + #include "omap_hwmod_common_data.h"
- + #include "control.h"
- + #include "cm33xx.h"
- + #include "prm33xx.h"
- + #include "common.h"
- + #include "wd_timer.h"
- + 
- + /* Backward references (IPs with Bus Master capability) */
- + static struct omap_hwmod am33xx_mpu_hwmod;
- + static struct omap_hwmod am33xx_l3_main_hwmod;
- + static struct omap_hwmod am33xx_l3slow_hwmod;
- + static struct omap_hwmod am33xx_l4wkup_hwmod;
- + static struct omap_hwmod am33xx_l4per_hwmod;
- + static struct omap_hwmod am33xx_uart1_hwmod;
- + static struct omap_hwmod am33xx_uart2_hwmod;
- + static struct omap_hwmod am33xx_uart3_hwmod;
- + static struct omap_hwmod am33xx_uart4_hwmod;
- + static struct omap_hwmod am33xx_uart5_hwmod;
- + static struct omap_hwmod am33xx_uart6_hwmod;
- + static struct omap_hwmod am33xx_timer0_hwmod;
- + static struct omap_hwmod am33xx_timer1_hwmod;
- + static struct omap_hwmod am33xx_timer2_hwmod;
- + static struct omap_hwmod am33xx_timer3_hwmod;
- + static struct omap_hwmod am33xx_timer4_hwmod;
- + static struct omap_hwmod am33xx_timer5_hwmod;
- + static struct omap_hwmod am33xx_timer6_hwmod;
- + static struct omap_hwmod am33xx_timer7_hwmod;
- + static struct omap_hwmod am33xx_wd_timer1_hwmod;
- + static struct omap_hwmod am33xx_tpcc_hwmod;
- + static struct omap_hwmod am33xx_tptc0_hwmod;
- + static struct omap_hwmod am33xx_tptc1_hwmod;
- + static struct omap_hwmod am33xx_tptc2_hwmod;
- + static struct omap_hwmod am33xx_dcan0_hwmod;
- + static struct omap_hwmod am33xx_dcan1_hwmod;
- + static struct omap_hwmod am33xx_gpio0_hwmod;
- + static struct omap_hwmod am33xx_gpio1_hwmod;
- + static struct omap_hwmod am33xx_gpio2_hwmod;
- + static struct omap_hwmod am33xx_gpio3_hwmod;
- + static struct omap_hwmod am33xx_i2c1_hwmod;
- + static struct omap_hwmod am33xx_i2c2_hwmod;
- + static struct omap_hwmod am33xx_i2c3_hwmod;
- + static struct omap_hwmod am33xx_usbss_hwmod;
- + static struct omap_hwmod am33xx_mmc0_hwmod;
- + static struct omap_hwmod am33xx_mmc1_hwmod;
- + static struct omap_hwmod am33xx_mmc2_hwmod;
- + static struct omap_hwmod am33xx_spi0_hwmod;
- + static struct omap_hwmod am33xx_spi1_hwmod;
- + static struct omap_hwmod am33xx_elm_hwmod;
- + static struct omap_hwmod am33xx_adc_tsc_hwmod;
- + static struct omap_hwmod am33xx_aes0_hwmod;
- + static struct omap_hwmod am33xx_rtc_hwmod;
- + static struct omap_hwmod am33xx_sha0_hwmod;
- + static struct omap_hwmod am33xx_mcasp0_hwmod;
- + static struct omap_hwmod am33xx_mcasp1_hwmod;
- + static struct omap_hwmod am33xx_ehrpwm0_hwmod;
- + static struct omap_hwmod am33xx_ehrpwm1_hwmod;
- + static struct omap_hwmod am33xx_ehrpwm2_hwmod;
- + static struct omap_hwmod am33xx_ecap0_hwmod;
- + static struct omap_hwmod am33xx_ecap1_hwmod;
- + static struct omap_hwmod am33xx_ecap2_hwmod;
- + static struct omap_hwmod am33xx_gpmc_hwmod;
- + static struct omap_hwmod am33xx_lcdc_hwmod;
- + static struct omap_hwmod am33xx_mailbox_hwmod;
- + static struct omap_hwmod am33xx_cpgmac0_hwmod;
- + static struct omap_hwmod am33xx_mdio_hwmod;
- + static struct omap_hwmod am33xx_rng_hwmod;
- + 
- + /*
- +  * ERRATA: (Yet to conform from IP team)
- +  * As per the observation, in order to disable the cpsw clock/module
- +  * from already enabled state, module level reset assertion is
- +  * required; without reset the clock/module won't enter into
- +  * idle state at all.
- +  * Also, as per observation (have not conformed yet), we have to
- +  * assert reset signal for all cpsw (4) submodules.
- +  */
- + 
- + /* OCP SYSSTATUS bit shifts/masks */
- + #define SOFT_RESETDONE_SHIFT		0
- + #define SOFT_RESETDONE_MASK		(1 << SOFT_RESETDONE_SHIFT)
- + 
- + #define MAX_MODULE_SOFTRESET_WAIT	10000
- + 
- + static int am33xx_cpgmac_reset(struct omap_hwmod *oh)
- + {
- + 	int i;
- + 	int ret = 0;
- + 
- + 	pr_debug("%s: resetting via Module SOFTRESET bit\n", oh->name);
- + 
- + 	for (i = 0; i < oh->slaves_cnt; i++) {
- + 		int c = 0;
- + 		void __iomem *va_start;
- + 		struct omap_hwmod_ocp_if *os;
- + 		struct omap_hwmod_addr_space *mem;
- + 
- + 		os = oh->slaves[i];
- + 		/* FIXME: Only first instance's OCP_RST is asserted */
- + 		mem = &os->addr[0];
- + 
- + 		va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
- + 		if (!va_start) {
- + 			pr_err("%s: Could not ioremap (%x)\n",
- + 					oh->name, mem->pa_start);
- + 			ret = -ENOMEM;
- + 			break;
- + 		}
- + 		/* Assert reset signal */
- + 		writel(1, va_start + oh->class->sysc->rst_offs);
- + 		omap_test_timeout(((readl(va_start + oh->class->sysc->rst_offs)
- + 					& SOFT_RESETDONE_MASK) == 0),
- + 				MAX_MODULE_SOFTRESET_WAIT, c);
- + 
- + 		if (c == MAX_MODULE_SOFTRESET_WAIT) {
- + 			pr_warning("%s: softreset failed (waited %d usec)\n",
- + 					oh->name, MAX_MODULE_SOFTRESET_WAIT);
- + 			ret = -ETIMEDOUT;
- + 		}
- + 	}
- + 
- + 	return ret;
- + }
- + 
- + /*
- +  * Interconnects hwmod structures
- +  * hwmods that compose the global AM33XX OCP interconnect
- +  */
- + 
- + /* MPU -> L3_SLOW Peripheral interface */
- + static struct omap_hwmod_ocp_if am33xx_mpu__l3_slow = {
- + 	.master 	= &am33xx_mpu_hwmod,
- + 	.slave		= &am33xx_l3slow_hwmod,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + /* L3 SLOW -> L4_PER Peripheral interface */
- + static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_per = {
- + 	.master 	= &am33xx_l3slow_hwmod,
- + 	.slave		= &am33xx_l4per_hwmod,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + /* L3 SLOW -> L4_WKUP Peripheral interface */
- + static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_wkup = {
- + 	.master 	= &am33xx_l3slow_hwmod,
- + 	.slave		= &am33xx_l4wkup_hwmod,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + /* Master interfaces on the L4_WKUP interconnect */
- + static struct omap_hwmod_ocp_if *am33xx_l3_slow_masters[] = {
- + 	&am33xx_l3_slow__l4_per,
- + 	&am33xx_l3_slow__l4_wkup,
- + };
- + 
- + /* Slave interfaces on the L3_SLOW interconnect */
- + static struct omap_hwmod_ocp_if *am33xx_l3_slow_slaves[] = {
- + 	&am33xx_mpu__l3_slow,
- + };
- + 
- + static struct omap_hwmod am33xx_l3slow_hwmod = {
- + 	.name		= "l3_slow",
- + 	.class		= &l3_hwmod_class,
- + 	.clkdm_name	= "l3s_clkdm",
- + 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
- + 	.masters	= am33xx_l3_slow_masters,
- + 	.masters_cnt	= ARRAY_SIZE(am33xx_l3_slow_masters),
- + 	.slaves		= am33xx_l3_slow_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_l3_slow_slaves),
- + };
- + 
- + /* L4 PER -> DCAN0 */
- + static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = {
- + 	{
- + 		.pa_start	= 0x481CC000,
- + 		.pa_end		= 0x481CC000 + SZ_4K - 1,
- + 		.flags		= ADDR_TYPE_RT
- + 	},
- + 	{ }
- + };
- + 
- + static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
- + 	.master		= &am33xx_l4per_hwmod,
- + 	.slave		= &am33xx_dcan0_hwmod,
- + 	.clk		= "dcan0_ick",
- + 	.addr		= am33xx_dcan0_addrs,
- + 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
- + };
- + 
- + /* L4 PER -> DCAN1 */
- + static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = {
- + 	{
- + 		.pa_start	= 0x481D0000,
- + 		.pa_end		= 0x481D0000 + SZ_4K - 1,
- + 		.flags		= ADDR_TYPE_RT
- + 	},
- + 	{ }
- + };
- + 
- + static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
- + 	.master		= &am33xx_l4per_hwmod,
- + 	.slave		= &am33xx_dcan1_hwmod,
- + 	.clk		= "dcan1_ick",
- + 	.addr		= am33xx_dcan1_addrs,
- + 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
- + };
- + 
- + /* L4 PER -> GPIO2 */
- + static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
- + 	{
- + 		.pa_start	= 0x4804C000,
- + 		.pa_end		= 0x4804C000 + SZ_4K - 1,
- + 		.flags		= ADDR_TYPE_RT,
- + 	},
- + 	{ }
- + };
- + 
- + static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
- + 	.master		= &am33xx_l4per_hwmod,
- + 	.slave		= &am33xx_gpio1_hwmod,
- + 	.clk		= "l4ls_gclk",
- + 	.addr		= am33xx_gpio1_addrs,
- + 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
- + };
- + 
- + /* L4 PER -> GPIO3 */
- + static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
- + 	{
- + 		.pa_start	= 0x481AC000,
- + 		.pa_end		= 0x481AC000 + SZ_4K - 1,
- + 		.flags		= ADDR_TYPE_RT,
- + 	},
- + 	{ }
- + };
- + 
- + static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
- + 	.master		= &am33xx_l4per_hwmod,
- + 	.slave		= &am33xx_gpio2_hwmod,
- + 	.clk		= "l4ls_gclk",
- + 	.addr		= am33xx_gpio2_addrs,
- + 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
- + };
- + 
- + /* L4 PER -> GPIO4 */
- + static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
- + 	{
- + 		.pa_start	= 0x481AE000,
- + 		.pa_end		= 0x481AE000 + SZ_4K - 1,
- + 		.flags		= ADDR_TYPE_RT,
- + 	},
- + 	{ }
- + };
- + 
- + static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
- + 	.master		= &am33xx_l4per_hwmod,
- + 	.slave		= &am33xx_gpio3_hwmod,
- + 	.clk		= "l4ls_gclk",
- + 	.addr		= am33xx_gpio3_addrs,
- + 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
- + };
- + 
- + /* Master interfaces on the L4_PER interconnect */
- + static struct omap_hwmod_ocp_if *am33xx_l4_per_masters[] = {
- + 	&am33xx_l4_per__dcan0,
- + 	&am33xx_l4_per__dcan1,
- + 	&am33xx_l4_per__gpio1,
- + 	&am33xx_l4_per__gpio2,
- + 	&am33xx_l4_per__gpio3,
- + };
- + 
- + /* Slave interfaces on the L4_PER interconnect */
- + static struct omap_hwmod_ocp_if *am33xx_l4_per_slaves[] = {
- + 	&am33xx_l3_slow__l4_per,
- + };
- + 
- + static struct omap_hwmod am33xx_l4per_hwmod = {
- + 	.name		= "l4_per",
- + 	.class		= &l4_hwmod_class,
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
- + 	.masters	= am33xx_l4_per_masters,
- + 	.masters_cnt	= ARRAY_SIZE(am33xx_l4_per_masters),
- + 	.slaves		= am33xx_l4_per_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_l4_per_slaves),
- + };
- + 
- + /* L4 WKUP -> I2C1 */
- + static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
- + 	{
- + 		.pa_start	= 0x44E0B000,
- + 		.pa_end		= 0x44E0B000 + SZ_4K - 1,
- + 		.flags		= ADDR_TYPE_RT,
- + 	},
- + 	{ }
- + };
- + 
- + static struct omap_hwmod_ocp_if am33xx_l4_wkup_i2c1 = {
- + 	.master		= &am33xx_l4wkup_hwmod,
- + 	.slave		= &am33xx_i2c1_hwmod,
- + 	.addr		= am33xx_i2c1_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + /* L4 WKUP -> GPIO1 */
- + static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
- + 	{
- + 		.pa_start	= 0x44E07000,
- + 		.pa_end		= 0x44E07000 + SZ_4K - 1,
- + 		.flags		= ADDR_TYPE_RT,
- + 	},
- + 	{ }
- + };
- + 
- + static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
- + 	.master		= &am33xx_l4wkup_hwmod,
- + 	.slave		= &am33xx_gpio0_hwmod,
- + 	.clk		= "l4ls_gclk",
- + 	.addr		= am33xx_gpio0_addrs,
- + 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
- + };
- + 
- + /* Master interfaces on the L4_WKUP interconnect */
- + static struct omap_hwmod_ocp_if *am33xx_l4_wkup_masters[] = {
- + 	&am33xx_l4_wkup__gpio0,
- + };
- + /* Slave interfaces on the L4_WKUP interconnect */
- + static struct omap_hwmod_ocp_if *am33xx_l4_wkup_slaves[] = {
- + 	&am33xx_l3_slow__l4_wkup,
- + };
- + 
- + static struct omap_hwmod am33xx_l4wkup_hwmod = {
- + 	.name		= "l4_wkup",
- + 	.class		= &l4_hwmod_class,
- + 	.clkdm_name	= "l4_wkup_clkdm",
- + 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
- + 	.masters	= am33xx_l4_wkup_masters,
- + 	.masters_cnt	= ARRAY_SIZE(am33xx_l4_wkup_masters),
- + 	.slaves		= am33xx_l4_wkup_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_l4_wkup_slaves),
- + };
- + 
- + /* adc_tsc */
- + static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
- + 	.rev_offs	= 0x00,
- + 	.sysc_offs	= 0x10,
- + 	.sysc_flags	= SYSC_HAS_SIDLEMODE,
- + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- + 			SIDLE_SMART_WKUP),
- + 	.sysc_fields	= &omap_hwmod_sysc_type2,
- + };
- + 
- + static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
- + 	.name		= "adc_tsc",
- + 	.sysc		= &am33xx_adc_tsc_sysc,
- + };
- + 
- + /* L4 WKUP -> ADC_TSC */
- + static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
- + 	{
- + 		.pa_start	= 0x44E0D000,
- + 		.pa_end		= 0x44E0D000 + SZ_8K - 1,
- + 		.flags		= ADDR_TYPE_RT
- + 	},
- + 	{ }
- + };
- + 
- + static struct omap_hwmod_ocp_if am33xx_l4_wkup_adc_tsc = {
- + 	.master		= &am33xx_l4wkup_hwmod,
- + 	.slave		= &am33xx_adc_tsc_hwmod,
- + 	.clk		= "adc_tsc_ick",
- + 	.addr		= am33xx_adc_tsc_addrs,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_adc_tsc_slaves[] = {
- + 	&am33xx_l4_wkup_adc_tsc,
- + };
- + 
- + static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
- + 	{ .irq = 16 },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod am33xx_adc_tsc_hwmod = {
- + 	.name		= "adc_tsc",
- + 	.class		= &am33xx_adc_tsc_hwmod_class,
- + 	.clkdm_name	= "l4_wkup_clkdm",
- + 	.mpu_irqs	= am33xx_adc_tsc_irqs,
- + 	.main_clk	= "adc_tsc_fck",
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.slaves		= am33xx_adc_tsc_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_adc_tsc_slaves),
- + };
- + 
- + /* 'aes' class */
- + static struct omap_hwmod_class_sysconfig am33xx_aes_sysc = {
- + 	.rev_offs	= 0x80,
- + 	.sysc_offs	= 0x84,
- + 	.syss_offs	= 0x88,
- + 	.sysc_flags	= SYSS_HAS_RESET_STATUS,
- + };
- + 
- + static struct omap_hwmod_class am33xx_aes_hwmod_class = {
- + 	.name		= "aes",
- + 	.sysc		= &am33xx_aes_sysc,
- + };
- + 
- + /* aes0 */
- + static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
- + 	{ .irq = 102 },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod_dma_info am33xx_aes0_dma[] = {
- + 	{ .dma_req = AM33XX_DMA_AESEIP36T0_DOUT },
- + 	{ .dma_req = AM33XX_DMA_AESEIP36T0_DIN },
- + 	{ .dma_req = -1 }
- + };
- + 
- + static struct omap_hwmod_addr_space am33xx_aes0_addrs[] = {
- + 	{
- + 		.pa_start	= 0x53500000,
- + 		.pa_end		= 0x53500000 + SZ_1M - 1,
- + 		.flags		= ADDR_TYPE_RT
- + 	},
- + 	{ }
- + };
- + 
- + static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
- + 	.master		= &am33xx_l3_main_hwmod,
- + 	.slave		= &am33xx_aes0_hwmod,
- + 	.clk		= "aes0_fck",
- + 	.addr		= am33xx_aes0_addrs,
- + 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_aes0_slaves[] = {
- + 	&am33xx_l3_main__aes0,
- + };
- + 
- + static struct omap_hwmod am33xx_aes0_hwmod = {
- + 	.name		= "aes0",
- + 	.class		= &am33xx_aes_hwmod_class,
- + 	.clkdm_name	= "l3_clkdm",
- + 	.mpu_irqs	= am33xx_aes0_irqs,
- + 	.sdma_reqs	= am33xx_aes0_dma,
- + 	.main_clk	= "aes0_fck",
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.slaves		= am33xx_aes0_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_aes0_slaves),
- + };
- + 
- + /* cefuse */
- + static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
- + 	.name		= "cefuse",
- + };
- + 
- + static struct omap_hwmod am33xx_cefuse_hwmod = {
- + 	.name		= "cefuse",
- + 	.class		= &am33xx_cefuse_hwmod_class,
- + 	.clkdm_name	= "l4_cefuse_clkdm",
- + 	.main_clk	= "cefuse_fck",
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + };
- + 
- + /* clkdiv32k */
- + static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
- + 	.name		= "clkdiv32k",
- + };
- + 
- + static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
- + 	.name		= "clkdiv32k",
- + 	.class		= &am33xx_clkdiv32k_hwmod_class,
- + 	.clkdm_name	= "clk_24mhz_clkdm",
- + 	.main_clk	= "clkdiv32k_ick",
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
- + };
- + 
- + /* control */
- + static struct omap_hwmod_class am33xx_control_hwmod_class = {
- + 	.name		= "control",
- + };
- + 
- + static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
- + 	{ .irq = 8 },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod am33xx_control_hwmod = {
- + 	.name		= "control",
- + 	.class		= &am33xx_control_hwmod_class,
- + 	.clkdm_name	= "l4_wkup_clkdm",
- + 	.mpu_irqs	= am33xx_control_irqs,
- + 	.main_clk	= "control_fck",
- + 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + };
- + 
- + /* cpgmac0 */
- + static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
- + 	.rev_offs	= 0x0,
- + 	.sysc_offs	= 0x8,
- + 	.syss_offs	= 0x4,
- + 	.rst_offs	= 0x8,
- + 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
- + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
- + 			MSTANDBY_NO),
- + 	.sysc_fields	= &omap_hwmod_sysc_type3,
- + };
- + 
- + static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
- + 	.name		= "cpsw",
- + 	.sysc		= &am33xx_cpgmac_sysc,
- + 	.reset		= am33xx_cpgmac_reset,
- + };
- + 
- + /* Used by driver */
- + struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
- + 	/* cpsw ss */
- + 	{
- + 		.pa_start	= 0x4A100000,
- + 		.pa_end		= 0x4A100000 + SZ_2K - 1,
- + 		.flags		= ADDR_MAP_ON_INIT,
- + 	},
- + 	/* cpsw wr */
- + 	{
- + 		.pa_start	= 0x4A101200,
- + 		.pa_end		= 0x4A101200 + SZ_256 - 1,
- + 		.flags		= ADDR_TYPE_RT,
- + 	},
- + 	{ }
- + };
- + 
- + struct omap_hwmod_ocp_if am33xx_l3_main__cpgmac0 = {
- + 	.master		= &am33xx_l3_main_hwmod,
- + 	.slave		= &am33xx_cpgmac0_hwmod,
- + 	.addr		= am33xx_cpgmac0_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + struct omap_hwmod_addr_space am33xx_cpsw_sl1_addr_space[] = {
- + 	/* cpsw sl1 */
- + 	{
- + 		.pa_start	= 0x4A100D84,
- + 		.pa_end		= 0x4A100D84 + SZ_32 - 1,
- + 		.flags		= ADDR_TYPE_RT,
- + 	},
- + 	{ }
- + };
- + 
- + struct omap_hwmod_ocp_if am33xx_l3_main__cpsw_sl1 = {
- + 	.master		= &am33xx_l3_main_hwmod,
- + 	.slave		= &am33xx_cpgmac0_hwmod,
- + 	.addr		= am33xx_cpsw_sl1_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + struct omap_hwmod_addr_space am33xx_cpsw_sl2_addr_space[] = {
- + 	/* cpsw sl2 */
- + 	{
- + 		.pa_start	= 0x4A100DC4,
- + 		.pa_end		= 0x4A100DC4 + SZ_32 - 1,
- + 		.flags		= ADDR_TYPE_RT,
- + 	},
- + 	{ }
- + };
- + 
- + struct omap_hwmod_ocp_if am33xx_l3_main__cpsw_sl2 = {
- + 	.master		= &am33xx_l3_main_hwmod,
- + 	.slave		= &am33xx_cpgmac0_hwmod,
- + 	.addr		= am33xx_cpsw_sl2_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + struct omap_hwmod_addr_space am33xx_cpsw_cpdma_addr_space[] = {
- + 	/* cpsw cpdma */
- + 	{
- + 		.pa_start	= 0x4A100814,
- + 		.pa_end		= 0x4A100814 + SZ_32 - 1,
- + 		.flags		= ADDR_TYPE_RT,
- + 	},
- + 	{ }
- + };
- + 
- + struct omap_hwmod_ocp_if am33xx_l3_main__cpsw_cpdma = {
- + 	.master		= &am33xx_l3_main_hwmod,
- + 	.slave		= &am33xx_cpgmac0_hwmod,
- + 	.addr		= am33xx_cpsw_cpdma_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_cpgmac0_slaves[] = {
- + 	&am33xx_l3_main__cpgmac0,
- + 	&am33xx_l3_main__cpsw_sl1,
- + 	&am33xx_l3_main__cpsw_sl2,
- + 	&am33xx_l3_main__cpsw_cpdma,
- + };
- + 
- + static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
- + 	{ .name = "c0_rx_thresh_pend", .irq = 40 },
- + 	{ .name = "c0_rx_pend", .irq = 93 },
- + 	{ .name = "c0_tx_pend", .irq = 94 },
- + 	{ .name = "c0_misc_pend", .irq = 43 },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod am33xx_cpgmac0_hwmod = {
- + 	.name		= "cpgmac0",
- + 	.class		= &am33xx_cpgmac0_hwmod_class,
- + 	.clkdm_name	= "cpsw_125mhz_clkdm",
- + 	.mpu_irqs	= am33xx_cpgmac0_irqs,
- + 	.main_clk	= "cpgmac0_ick",
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.slaves		= am33xx_cpgmac0_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_cpgmac0_slaves),
- + 	.flags		= (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
- + 				HWMOD_SWSUP_RESET_BEFORE_IDLE),
- + };
- + 
- + /* mdio class */
- + static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
- + 	.name		= "davinci_mdio",
- + };
- + 
- + struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
- + 	{
- + 		.pa_start	= 0x4A101000,
- + 		.pa_end		= 0x4A101000 + SZ_256 - 1,
- + 		.flags		= ADDR_MAP_ON_INIT,
- + 	},
- + 	{ }
- + };
- + 
- + struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
- + 	.master		= &am33xx_cpgmac0_hwmod,
- + 	.slave		= &am33xx_mdio_hwmod,
- + 	.addr		= am33xx_mdio_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_mdio_slaves[] = {
- + 	&am33xx_cpgmac0__mdio,
- + };
- + 
- + static struct omap_hwmod am33xx_mdio_hwmod = {
- + 	.name		= "mdio",
- + 	.class		= &am33xx_mdio_hwmod_class,
- + 	.clkdm_name	= "cpsw_125mhz_clkdm",
- + 	.main_clk	= "cpgmac0_ick",
- + 	.slaves		= am33xx_mdio_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_mdio_slaves),
- + };
- + 
- + /* 'dcan' class */
- + static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
- + 	.name		= "d_can",
- + };
- + 
- + /* dcan0 slave ports */
- + static struct omap_hwmod_ocp_if *am33xx_dcan0_slaves[] = {
- + 	&am33xx_l4_per__dcan0,
- + };
- + 
- + /* dcan0 */
- + static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
- + 	{ .name = "d_can_ms", .irq = 52 },
- + 	{ .name = "d_can_mo", .irq = 53 },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod am33xx_dcan0_hwmod = {
- + 	.name		= "d_can0",
- + 	.class		= &am33xx_dcan_hwmod_class,
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.mpu_irqs	= am33xx_dcan0_irqs,
- + 	.main_clk	= "dcan0_fck",
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.slaves		= am33xx_dcan0_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_dcan0_slaves),
- + };
- + 
- + /* dcan1 slave ports */
- + static struct omap_hwmod_ocp_if *am33xx_dcan1_slaves[] = {
- + 	&am33xx_l4_per__dcan1,
- + };
- + 
- + /* dcan1 */
- + static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
- + 	{ .name = "d_can_ms", .irq = 55 },
- + 	{ .name = "d_can_mo", .irq = 56 },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod am33xx_dcan1_hwmod = {
- + 	.name		= "d_can1",
- + 	.class		= &am33xx_dcan_hwmod_class,
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.mpu_irqs	= am33xx_dcan1_irqs,
- + 	.main_clk	= "dcan1_fck",
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.slaves		= am33xx_dcan1_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_dcan1_slaves),
- + };
- + 
- + /* debugss */
- + static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
- + 	.name		= "debugss",
- + };
- + 
- + static struct omap_hwmod am33xx_debugss_hwmod = {
- + 	.name		= "debugss",
- + 	.class		= &am33xx_debugss_hwmod_class,
- + 	.clkdm_name	= "l3_aon_clkdm",
- + 	.main_clk	= "debugss_ick",
- + #ifdef CONFIG_DEBUG_JTAG_ENABLE
- + 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
- + #endif
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + };
- + 
- + /* elm */
- + static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
- + 	.rev_offs	= 0x0000,
- + 	.sysc_offs	= 0x0010,
- + 	.syss_offs	= 0x0014,
- + 	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
- + 			SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
- + 			SYSS_HAS_RESET_STATUS),
- + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- + 	.sysc_fields	= &omap_hwmod_sysc_type1,
- + };
- + 
- + static struct omap_hwmod_class am33xx_elm_hwmod_class = {
- + 	.name		= "elm",
- + 	.sysc		= &am33xx_elm_sysc,
- + };
- + 
- + static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
- + 	{ .irq = 4 },
- + 	{ .irq = -1 }
- + };
- + 
- + struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
- + 	{
- + 		.pa_start	= 0x48080000,
- + 		.pa_end		= 0x48080000 + SZ_8K - 1,
- + 		.flags		= ADDR_TYPE_RT
- + 	},
- + 	{ }
- + };
- + 
- + struct omap_hwmod_ocp_if am33xx_l4_core__elm = {
- + 	.master		= &am33xx_l4per_hwmod,
- + 	.slave		= &am33xx_elm_hwmod,
- + 	.addr		= am33xx_elm_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_elm_slaves[] = {
- + 	&am33xx_l4_core__elm,
- + };
- + 
- + static struct omap_hwmod am33xx_elm_hwmod = {
- + 	.name		= "elm",
- + 	.class		= &am33xx_elm_hwmod_class,
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.mpu_irqs	= am33xx_elm_irqs,
- + 	.main_clk	= "elm_fck",
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.slaves		= am33xx_elm_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_elm_slaves),
- + };
- + 
- + /* emif_fw */
- + static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
- + 	.name		= "emif_fw",
- + };
- + 
- + static struct omap_hwmod am33xx_emif_fw_hwmod = {
- + 	.name		= "emif_fw",
- + 	.class		= &am33xx_emif_fw_hwmod_class,
- + 	.clkdm_name	= "l4fw_clkdm",
- + 	.main_clk	= "emif_fw_fck",
- + 	.flags		= HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + };
- + 
- + /* 'epwmss' class */
- + static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
- + 	.rev_offs	= 0x0,
- + 	.sysc_offs	= 0x4,
- + 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
- + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- + 			SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
- + 			MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
- + 	.sysc_fields	= &omap_hwmod_sysc_type2,
- + };
- + 
- + static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
- + 	.name		= "epwmss",
- + 	.sysc		= &am33xx_epwmss_sysc,
- + };
- + 
- + /* ehrpwm0 */
- + static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
- + 	{ .irq		= 86 },
- + 	{ .irq		= 58 },
- + 	{ .irq		= -1 }
- + };
- + 
- + struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
- + /*
- +  * Splitting the resources to handle access of PWMSS config space and module
- +  * specific part independently
- +  */
- + 	{
- + 		.pa_start	= 0x48300000,
- + 		.pa_end		= 0x48300000 + SZ_16 - 1,
- + 		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT
- + 	},
- + 	{
- + 		.pa_start	= 0x48300000 + SZ_512,
- + 		.pa_end		= 0x48300000 + SZ_512 + SZ_256 - 1,
- + 		.flags		= ADDR_TYPE_RT
- + 	},
- + 	{ }
- + };
- + 
- + struct omap_hwmod_ocp_if am33xx_l4_core__ehrpwm0 = {
- + 	.master		= &am33xx_l4per_hwmod,
- + 	.slave		= &am33xx_ehrpwm0_hwmod,
- + 	.addr		= am33xx_ehrpwm0_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_ehrpwm0_slaves[] = {
- + 	&am33xx_l4_core__ehrpwm0,
- + };
- + 
- + static struct omap_hwmod_opt_clk ehrpwm0_opt_clks[] = {
- + 	{ .role = "tbclk", .clk = "ehrpwm0_tbclk" },
- + };
- + 
- + static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
- + 	.name		= "ehrpwm.0",
- + 	.mpu_irqs	= am33xx_ehrpwm0_irqs,
- + 	.class		= &am33xx_epwmss_hwmod_class,
- + 	.main_clk	= "epwmss0_fck",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.slaves		= am33xx_ehrpwm0_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_ehrpwm0_slaves),
- + 	.opt_clks	= ehrpwm0_opt_clks,
- + 	.opt_clks_cnt	= ARRAY_SIZE(ehrpwm0_opt_clks),
- + };
- + 
- + /* ehrpwm1 */
- + static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
- + 	{ .irq		= 87 },
- + 	{ .irq		= 59 },
- + 	{ .irq		= -1 }
- + };
- + 
- + struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
- + /*
- +  * Splitting the resources to handle access of PWMSS config space and module
- +  * specific part independently
- +  */
- + 	{
- + 		.pa_start	= 0x48302000,
- + 		.pa_end		= 0x48302000 + SZ_16 - 1,
- + 		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT
- + 	},
- + 	{
- + 		.pa_start	= 0x48302000 + SZ_512,
- + 		.pa_end		= 0x48302000 + SZ_512 + SZ_256 - 1,
- + 		.flags		= ADDR_TYPE_RT
- + 	},
- + 	{ }
- + };
- + 
- + struct omap_hwmod_ocp_if am33xx_l4_core__ehrpwm1 = {
- + 	.master		= &am33xx_l4per_hwmod,
- + 	.slave		= &am33xx_ehrpwm1_hwmod,
- + 	.addr		= am33xx_ehrpwm1_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_ehrpwm1_slaves[] = {
- + 	&am33xx_l4_core__ehrpwm1,
- + };
- + 
- + static struct omap_hwmod_opt_clk ehrpwm1_opt_clks[] = {
- + 	{ .role = "tbclk", .clk = "ehrpwm1_tbclk" },
- + };
- + 
- + static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
- + 	.name		= "ehrpwm.1",
- + 	.mpu_irqs	= am33xx_ehrpwm1_irqs,
- + 	.class		= &am33xx_epwmss_hwmod_class,
- + 	.main_clk	= "epwmss1_fck",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.slaves		= am33xx_ehrpwm1_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_ehrpwm1_slaves),
- + 	.opt_clks	= ehrpwm1_opt_clks,
- + 	.opt_clks_cnt	= ARRAY_SIZE(ehrpwm1_opt_clks),
- + };
- + 
- + /* ehrpwm2 */
- + static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
- + 	{ .irq		= 39 },
- + 	{ .irq		= 60 },
- + 	{ .irq		= -1 }
- + };
- + 
- + struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
- + /*
- +  * Splitting the resources to handle access of PWMSS config space and module
- +  * specific part independently
- +  */
- + 	{
- + 		.pa_start	= 0x48304000,
- + 		.pa_end		= 0x48304000 + SZ_16 - 1,
- + 		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT
- + 	},
- + 	{
- + 		.pa_start	= 0x48304000 + SZ_512,
- + 		.pa_end		= 0x48304000 + SZ_512 + SZ_256 - 1,
- + 		.flags		= ADDR_TYPE_RT
- + 	},
- + 	{ }
- + };
- + 
- + struct omap_hwmod_ocp_if am33xx_l4_core__ehrpwm2 = {
- + 	.master		= &am33xx_l4per_hwmod,
- + 	.slave		= &am33xx_ehrpwm2_hwmod,
- + 	.addr		= am33xx_ehrpwm2_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_ehrpwm2_slaves[] = {
- + 	&am33xx_l4_core__ehrpwm2,
- + };
- + 
- + static struct omap_hwmod_opt_clk ehrpwm2_opt_clks[] = {
- + 	{ .role = "tbclk", .clk = "ehrpwm2_tbclk" },
- + };
- + 
- + static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
- + 	.name		= "ehrpwm.2",
- + 	.mpu_irqs	= am33xx_ehrpwm2_irqs,
- + 	.class		= &am33xx_epwmss_hwmod_class,
- + 	.main_clk	= "epwmss2_fck",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.slaves		= am33xx_ehrpwm2_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_ehrpwm2_slaves),
- + 	.opt_clks	= ehrpwm2_opt_clks,
- + 	.opt_clks_cnt	= ARRAY_SIZE(ehrpwm2_opt_clks),
- + };
- + 
- + /* ecap0 */
- + static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
- + 	{ .irq		= 31 },
- + 	{ .irq		= -1 }
- + };
- + 
- + struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
- + /*
- +  * Splitting the resources to handle access of PWMSS config space and module
- +  * specific part independently
- +  */
- + 	{
- + 		.pa_start	= 0x48300000,
- + 		.pa_end		= 0x48300000 + SZ_16 - 1,
- + 		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT
- + 	},
- + 	{
- + 		.pa_start	= 0x48300000 + SZ_256,
- + 		.pa_end		= 0x48300000 + SZ_256 + SZ_256 - 1,
- + 		.flags		= ADDR_TYPE_RT
- + 	},
- + 	{ }
- + };
- + 
- + struct omap_hwmod_ocp_if am33xx_l4_core__ecap0 = {
- + 	.master		= &am33xx_l4per_hwmod,
- + 	.slave		= &am33xx_ecap0_hwmod,
- + 	.addr		= am33xx_ecap0_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_ecap0_slaves[] = {
- + 	&am33xx_l4_core__ecap0,
- + };
- + 
- + static struct omap_hwmod am33xx_ecap0_hwmod = {
- + 	.name		= "ecap.0",
- + 	.mpu_irqs	= am33xx_ecap0_irqs,
- + 	.class		= &am33xx_epwmss_hwmod_class,
- + 	.main_clk	= "epwmss0_fck",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.slaves		= am33xx_ecap0_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_ecap0_slaves),
- + };
- + 
- + /* ecap1 */
- + static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
- + 	{ .irq		= 47 },
- + 	{ .irq		= -1 }
- + };
- + 
- + struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
- + /*
- +  * Splitting the resources to handle access of PWMSS config space and module
- +  * specific part independently
- +  */
- + 	{
- + 		.pa_start	= 0x48302000,
- + 		.pa_end		= 0x48302000 + SZ_16 - 1,
- + 		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT
- + 	},
- + 	{
- + 		.pa_start	= 0x48302000 + SZ_256,
- + 		.pa_end		= 0x48302000 + SZ_256 + SZ_256 - 1,
- + 		.flags		= ADDR_TYPE_RT
- + 	},
- + 	{ }
- + };
- + 
- + struct omap_hwmod_ocp_if am33xx_l4_core__ecap1 = {
- + 	.master		= &am33xx_l4per_hwmod,
- + 	.slave		= &am33xx_ecap1_hwmod,
- + 	.addr		= am33xx_ecap1_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_ecap1_slaves[] = {
- + 	&am33xx_l4_core__ecap1,
- + };
- + 
- + static struct omap_hwmod am33xx_ecap1_hwmod = {
- + 	.name		= "ecap.1",
- + 	.mpu_irqs	= am33xx_ecap1_irqs,
- + 	.class		= &am33xx_epwmss_hwmod_class,
- + 	.main_clk	= "epwmss1_fck",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.slaves		= am33xx_ecap1_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_ecap1_slaves),
- + };
- + 
- + /* ecap2 */
- + static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
- + 	{ .irq		= 61 },
- + 	{ .irq		= -1 }
- + };
- + 
- + struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
- + /*
- +  * Splitting the resources to handle access of PWMSS config space and module
- +  * specific part independently
- +  */
- + 	{
- + 		.pa_start	= 0x48304000,
- + 		.pa_end		= 0x48304000 + SZ_16 - 1,
- + 		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT
- + 	},
- + 	{
- + 		.pa_start	= 0x48304000 + SZ_256,
- + 		.pa_end		= 0x48304000 + SZ_256 + SZ_256 - 1,
- + 		.flags		= ADDR_TYPE_RT
- + 	},
- + 	{ }
- + };
- + 
- + struct omap_hwmod_ocp_if am33xx_l4_core__ecap2 = {
- + 	.master		= &am33xx_l4per_hwmod,
- + 	.slave		= &am33xx_ecap2_hwmod,
- + 	.addr		= am33xx_ecap2_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_ecap2_slaves[] = {
- + 	&am33xx_l4_core__ecap2,
- + };
- + 
- + static struct omap_hwmod am33xx_ecap2_hwmod = {
- + 	.name		= "ecap.2",
- + 	.mpu_irqs	= am33xx_ecap2_irqs,
- + 	.class		= &am33xx_epwmss_hwmod_class,
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.main_clk	= "epwmss2_fck",
- + 	.slaves		= am33xx_ecap2_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_ecap2_slaves),
- + };
- + 
- + static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
- + 	.rev_offs	= 0x0000,
- + 	.sysc_offs	= 0x0010,
- + 	.syss_offs	= 0x0114,
- + 	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
- + 			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- + 			   SYSS_HAS_RESET_STATUS),
- + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- + 			SIDLE_SMART_WKUP),
- + 	.sysc_fields	= &omap_hwmod_sysc_type1,
- + };
- + 
- + /* 'gpio' class */
- + static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
- + 	.name		= "gpio",
- + 	.sysc		= &am33xx_gpio_sysc,
- + 	.rev		= 2,
- + };
- + 
- + static struct omap_gpio_dev_attr gpio_dev_attr = {
- + 	.bank_width	= 32,
- + 	.dbck_flag	= true,
- + };
- + 
- + /* gpio0 */
- + static struct omap_hwmod_ocp_if *am33xx_gpio0_slaves[] = {
- + 	&am33xx_l4_wkup__gpio0,
- + };
- + 
- + static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
- + 	{ .role = "dbclk", .clk = "gpio0_dbclk" },
- + };
- + 
- + static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
- + 	{ .irq = 96 },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod am33xx_gpio0_hwmod = {
- + 	.name		= "gpio1",
- + 	.class		= &am33xx_gpio_hwmod_class,
- + 	.clkdm_name	= "l4_wkup_clkdm",
- + 	.mpu_irqs	= am33xx_gpio0_irqs,
- + 	.main_clk	= "gpio0_ick",
- + 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET | HWMOD_INIT_NO_RESET,
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.opt_clks	= gpio0_opt_clks,
- + 	.opt_clks_cnt	= ARRAY_SIZE(gpio0_opt_clks),
- + 	.dev_attr	= &gpio_dev_attr,
- + 	.slaves		= am33xx_gpio0_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_gpio0_slaves),
- + };
- + 
- + /* gpio1 */
- + static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
- + 	{ .irq = 98 },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_gpio1_slaves[] = {
- + 	&am33xx_l4_per__gpio1,
- + };
- + 
- + static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
- + 	{ .role = "dbclk", .clk = "gpio1_dbclk" },
- + };
- + 
- + static struct omap_hwmod am33xx_gpio1_hwmod = {
- + 	.name		= "gpio2",
- + 	.class		= &am33xx_gpio_hwmod_class,
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.mpu_irqs	= am33xx_gpio1_irqs,
- + 	.main_clk	= "gpio1_ick",
- + 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.opt_clks	= gpio1_opt_clks,
- + 	.opt_clks_cnt	= ARRAY_SIZE(gpio1_opt_clks),
- + 	.dev_attr	= &gpio_dev_attr,
- + 	.slaves		= am33xx_gpio1_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_gpio1_slaves),
- + };
- + 
- + /* gpio2 */
- + static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
- + 	{ .irq = 32 },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_gpio2_slaves[] = {
- + 	&am33xx_l4_per__gpio2,
- + };
- + 
- + static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
- + 	{ .role = "dbclk", .clk = "gpio2_dbclk" },
- + };
- + 
- + static struct omap_hwmod am33xx_gpio2_hwmod = {
- + 	.name		= "gpio3",
- + 	.class		= &am33xx_gpio_hwmod_class,
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.mpu_irqs	= am33xx_gpio2_irqs,
- + 	.main_clk	= "gpio2_ick",
- + 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.opt_clks	= gpio2_opt_clks,
- + 	.opt_clks_cnt	= ARRAY_SIZE(gpio2_opt_clks),
- + 	.dev_attr	= &gpio_dev_attr,
- + 	.slaves		= am33xx_gpio2_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_gpio2_slaves),
- + };
- + 
- + /* gpio3 */
- + static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
- + 	{ .irq = 62 },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_gpio3_slaves[] = {
- + 	&am33xx_l4_per__gpio3,
- + };
- + 
- + static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
- + 	{ .role = "dbclk", .clk = "gpio3_dbclk" },
- + };
- + 
- + static struct omap_hwmod am33xx_gpio3_hwmod = {
- + 	.name		= "gpio4",
- + 	.class		= &am33xx_gpio_hwmod_class,
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.mpu_irqs	= am33xx_gpio3_irqs,
- + 	.main_clk	= "gpio3_ick",
- + #if defined(CONFIG_CKB_LCD_SUPPORT)
- + 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET | HWMOD_INIT_NO_RESET, /* this is needed for backlight and LCD */
- + #else
- + 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- + #endif
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.opt_clks	= gpio3_opt_clks,
- + 	.opt_clks_cnt	= ARRAY_SIZE(gpio3_opt_clks),
- + 	.dev_attr	= &gpio_dev_attr,
- + 	.slaves		= am33xx_gpio3_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_gpio3_slaves),
- + };
- + 
- + /* gpmc */
- + static struct omap_hwmod_class_sysconfig gpmc_sysc = {
- + 	.rev_offs	= 0x0,
- + 	.sysc_offs	= 0x10,
- + 	.syss_offs	= 0x14,
- + 	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
- + 			SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- + 	.sysc_fields	= &omap_hwmod_sysc_type1,
- + };
- + 
- + static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
- + 	.name		= "gpmc",
- + 	.sysc		= &gpmc_sysc,
- + };
- + 
- + struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
- + 	{
- + 		.pa_start	= 0x50000000,
- + 		.pa_end		= 0x50000000 + SZ_8K - 1,
- + 		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
- + 	},
- + 	{ }
- + };
- + 
- + struct omap_hwmod_ocp_if am33xx_l3_main__gpmc = {
- + 	.master		= &am33xx_l3_main_hwmod,
- + 	.slave		= &am33xx_gpmc_hwmod,
- + 	.addr		= am33xx_gpmc_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_gpmc_slaves[] = {
- + 	&am33xx_l3_main__gpmc,
- + };
- + 
- + static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = {
- + 	{ .irq = 100 },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod am33xx_gpmc_hwmod = {
- + 	.name		= "gpmc",
- + 	.class		= &am33xx_gpmc_hwmod_class,
- + 	.clkdm_name	= "l3s_clkdm",
- + 	.mpu_irqs	= am33xx_gpmc_irqs,
- + 	.main_clk	= "gpmc_fck",
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.slaves		= am33xx_gpmc_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_gpmc_slaves),
- + 	.flags		= (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
- + 				HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
- + };
- + 
- + /* 'i2c' class */
- + static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
- + 	.sysc_offs	= 0x0010,
- + 	.syss_offs	= 0x0090,
- + 	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
- + 			SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
- + 			SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- + 			SIDLE_SMART_WKUP),
- + 	.sysc_fields	= &omap_hwmod_sysc_type1,
- + };
- + 
- + static struct omap_i2c_dev_attr i2c_dev_attr = {
- + 	.flags		= OMAP_I2C_FLAG_BUS_SHIFT_NONE |
- + 					OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
- + };
- + 
- + static struct omap_hwmod_class i2c_class = {
- + 	.name		= "i2c",
- + 	.sysc		= &am33xx_i2c_sysc,
- + 	.rev		= OMAP_I2C_IP_VERSION_2,
- + 	.reset		= &omap_i2c_reset,
- + };
- + 
- + /* I2C1 */
- + static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
- + 	{ .irq = 70 },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
- + 	{ .name = "tx", .dma_req = 0, },
- + 	{ .name = "rx", .dma_req = 0, },
- + 	{ .dma_req = -1 }
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_i2c1_slaves[] = {
- + 	&am33xx_l4_wkup_i2c1,
- + };
- + 
- + static struct omap_hwmod am33xx_i2c1_hwmod = {
- + 	.name		= "i2c1",
- + 	.class		= &i2c_class,
- + 	.clkdm_name	= "l4_wkup_clkdm",
- + 	.mpu_irqs	= i2c1_mpu_irqs,
- + 	.main_clk	= "i2c1_fck",
- + 	.sdma_reqs	= i2c1_edma_reqs,
- + 	.flags		= HWMOD_16BIT_REG,
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.dev_attr	= &i2c_dev_attr,
- + 	.slaves		= am33xx_i2c1_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_i2c1_slaves),
- + };
- + 
- + /* i2c2 */
- + static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
- + 	{
- + 		.pa_start	= 0x4802A000,
- + 		.pa_end		= 0x4802A000 + SZ_4K - 1,
- + 		.flags		= ADDR_TYPE_RT,
- + 	},
- + 	{ }
- + };
- + 
- + static struct omap_hwmod_ocp_if am335_l4_per_i2c2 = {
- + 	.master		= &am33xx_l4per_hwmod,
- + 	.slave		= &am33xx_i2c2_hwmod,
- + 	.addr		= am33xx_i2c2_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
- + 	{ .irq = 71 },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
- + 	{ .name = "tx", .dma_req = 0, },
- + 	{ .name = "rx", .dma_req = 0, },
- + 	{ .dma_req = -1 }
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_i2c2_slaves[] = {
- + 	&am335_l4_per_i2c2,
- + };
- + 
- + static struct omap_hwmod am33xx_i2c2_hwmod = {
- + 	.name		= "i2c2",
- + 	.class		= &i2c_class,
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.mpu_irqs	= i2c2_mpu_irqs,
- + 	.main_clk	= "i2c2_fck",
- + 	.sdma_reqs	= i2c2_edma_reqs,
- + 	.flags		= HWMOD_16BIT_REG,
- + 	.prcm		= {
- + 		.omap4 = {
- + 			.clkctrl_offs	= AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.dev_attr	= &i2c_dev_attr,
- + 	.slaves		= am33xx_i2c2_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_i2c2_slaves),
- + };
- + 
- + /* I2C3 */
- + static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
- + 	{
- + 		.pa_start	= 0x4819C000,
- + 		.pa_end		= 0x4819C000 + SZ_4K - 1,
- + 		.flags		= ADDR_TYPE_RT
- + 	},
- + 	{ }
- + };
- + 
- + static struct omap_hwmod_ocp_if am335_l4_per_i2c3 = {
- + 	.master		= &am33xx_l4per_hwmod,
- + 	.slave		= &am33xx_i2c3_hwmod,
- + 	.addr		= am33xx_i2c3_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_i2c3_slaves[] = {
- + 	&am335_l4_per_i2c3,
- + };
- + 
- + static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
- + 	{ .name = "tx", .dma_req = 0, },
- + 	{ .name = "rx", .dma_req = 0, },
- + 	{ .dma_req = -1 }
- + };
- + 
- + static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
- + 	{ .irq = 30 },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod am33xx_i2c3_hwmod = {
- + 	.name		= "i2c3",
- + 	.class		= &i2c_class,
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.mpu_irqs	= i2c3_mpu_irqs,
- + 	.main_clk	= "i2c3_fck",
- + 	.sdma_reqs	= i2c3_edma_reqs,
- + 	.flags		= HWMOD_16BIT_REG,
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.dev_attr	= &i2c_dev_attr,
- + 	.slaves		= am33xx_i2c3_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_i2c3_slaves),
- + };
- + 
- + 
- + /* ieee5000 */
- + static struct omap_hwmod_class am33xx_ieee5000_hwmod_class = {
- + 	.name		= "ieee5000",
- + };
- + 
- + static struct omap_hwmod am33xx_ieee5000_hwmod = {
- + 	.name		= "ieee5000",
- + 	.class		= &am33xx_ieee5000_hwmod_class,
- + 	.clkdm_name	= "l3s_clkdm",
- + 	.main_clk	= "ieee5000_fck",
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + };
- + 
- + 
- + /* 'l3' class */
- + static struct omap_hwmod_class am33xx_l3_hwmod_class = {
- + 	.name		= "l3",
- + };
- + 
- + /* l4_hs */
- + static struct omap_hwmod am33xx_l4_hs_hwmod = {
- + 	.name		= "l4_hs",
- + 	.class		= &am33xx_l3_hwmod_class,
- + 	.clkdm_name	= "l4hs_clkdm",
- + 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + };
- + 
- + /* l3_instr */
- + static struct omap_hwmod am33xx_l3_instr_hwmod = {
- + 	.name		= "l3_instr",
- + 	.class		= &am33xx_l3_hwmod_class,
- + 	.clkdm_name	= "l3_clkdm",
- + 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + };
- + 
- + /* l3_main */
- + static struct omap_hwmod am33xx_l3_main_hwmod = {
- + 	.name		= "l3_main",
- + 	.class		= &am33xx_l3_hwmod_class,
- + 	.clkdm_name	= "l3_clkdm",
- + 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + };
- + 
- + /* 'l4fw' class */
- + static struct omap_hwmod_class am33xx_l4fw_hwmod_class = {
- + 	.name		= "l4fw",
- + };
- + 
- + /* l4fw */
- + static struct omap_hwmod am33xx_l4fw_hwmod = {
- + 	.name		= "l4fw",
- + 	.class		= &am33xx_l4fw_hwmod_class,
- + 	.clkdm_name	= "l4fw_clkdm",
- + 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + };
- + 
- + /* 'l4ls' class */
- + static struct omap_hwmod_class am33xx_l4ls_hwmod_class = {
- + 	.name		= "l4ls",
- + };
- + 
- + /* l4ls */
- + static struct omap_hwmod am33xx_l4ls_hwmod = {
- + 	.name		= "l4ls",
- + 	.class		= &am33xx_l4ls_hwmod_class,
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.main_clk	= "l4ls_gclk",
- + 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + };
- + 
- + /* lcdc */
- + static struct omap_hwmod_class_sysconfig lcdc_sysc = {
- + 	.rev_offs	= 0x0,
- + 	.sysc_offs	= 0x54,
- + 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
- + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- + 	.sysc_fields	= &omap_hwmod_sysc_type2,
- + };
- + 
- + static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
- + 	.name		= "lcdc",
- + 	.sysc		= &lcdc_sysc,
- + };
- + 
- + static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
- + 	{ .irq = 36 },
- + 	{ .irq = -1 }
- + };
- + 
- + struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
- + 	{
- + 		.pa_start	= 0x4830E000,
- + 		.pa_end		= 0x4830E000 + SZ_8K - 1,
- + 		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
- + 	},
- + 	{ }
- + };
- + 
- + struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
- + 	.master		= &am33xx_l3_main_hwmod,
- + 	.slave		= &am33xx_lcdc_hwmod,
- + 	.addr		= am33xx_lcdc_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_lcdc_slaves[] = {
- + 	&am33xx_l3_main__lcdc,
- + };
- + 
- + static struct omap_hwmod am33xx_lcdc_hwmod = {
- + 	.name		= "lcdc",
- + 	.class		= &am33xx_lcdc_hwmod_class,
- + 	.clkdm_name	= "lcdc_clkdm",
- + 	.mpu_irqs	= am33xx_lcdc_irqs,
- + 	.main_clk	= "lcdc_fck",
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.slaves		= am33xx_lcdc_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_lcdc_slaves),
- + #if defined(CONFIG_CKB_LCD_SUPPORT) || defined(CONFIG_CKB_DVI_SUPPORT)
- + 	.flags		= HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,				/* LCD clock shouldn't be reset or stopped */
- + #else
- + 	.flags		= (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
- + #endif
- + };
- + 
- + /*
- +  * 'mailbox' class
- +  * mailbox module allowing communication between the on-chip processors using a
- +  * queued mailbox-interrupt mechanism.
- +  */
- + 
- + static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
- + 	.rev_offs	= 0x0000,
- + 	.sysc_offs	= 0x0010,
- + 	.sysc_flags	= (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
- + 			SYSC_HAS_SOFTRESET),
- + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- + 	.sysc_fields	= &omap_hwmod_sysc_type2,
- + };
- + 
- + static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
- + 	.name	= "mailbox",
- + 	.sysc	= &am33xx_mailbox_sysc,
- + };
- + 
- + static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
- + 	{ .irq = 77 },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
- + 	{
- + 		.pa_start	= 0x480C8000,
- + 		.pa_end		= 0x480C8000 + (SZ_4K - 1),
- + 		.flags		= ADDR_TYPE_RT
- + 	},
- + 	{ }
- + };
- + 
- + /* l4_cfg -> mailbox */
- + static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
- + 	.master		= &am33xx_l4per_hwmod,
- + 	.slave		= &am33xx_mailbox_hwmod,
- + 	.addr		= am33xx_mailbox_addrs,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_mailbox_slaves[] = {
- + 	&am33xx_l4_per__mailbox,
- + };
- + 
- + static struct omap_hwmod am33xx_mailbox_hwmod = {
- + 	.name		= "mailbox",
- + 	.class		= &am33xx_mailbox_hwmod_class,
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.mpu_irqs	= am33xx_mailbox_irqs,
- + 	.main_clk	= "mailbox0_fck",
- + 	.prcm = {
- + 		.omap4 = {
- + 			.clkctrl_offs	= AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.slaves		= am33xx_mailbox_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_mailbox_slaves),
- + };
- + 
- + /* 'mcasp' class */
- + 
- + static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
- + 	.rev_offs	= 0x0,
- + 	.sysc_offs	= 0x4,
- + 	.sysc_flags	= SYSC_HAS_SIDLEMODE,
- + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- + 	.sysc_fields	= &omap_hwmod_sysc_type3,
- + };
- + 
- + static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
- + 	.name	= "mcasp",
- + 	.sysc	= &am33xx_mcasp_sysc,
- + };
- + 
- + /* mcasp0 */
- + static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
- + 	{ .name = "ax", .irq = 80, },
- + 	{ .name = "ar", .irq = 81, },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = {
- + 	{ .name = "tx", .dma_req = AM33XX_DMA_MCASP0_X, },
- + 	{ .name = "rx", .dma_req = AM33XX_DMA_MCASP0_R, },
- + 	{ .dma_req = -1 }
- + };
- + 
- + static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
- + 	{
- + 		.pa_start	= 0x48038000,
- + 		.pa_end		= 0x48038000 + (SZ_1K * 12) - 1,
- + 		.flags		= ADDR_TYPE_RT
- + 	},
- + 	{ }
- + };
- + 
- + static struct omap_hwmod_ocp_if am33xx_l3_slow__mcasp0 = {
- + 	.master		= &am33xx_l3slow_hwmod,
- + 	.slave		= &am33xx_mcasp0_hwmod,
- + 	.clk		= "mcasp0_ick",
- + 	.addr		= am33xx_mcasp0_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_mcasp0_slaves[] = {
- + 	&am33xx_l3_slow__mcasp0,
- + };
- + 
- + static struct omap_hwmod am33xx_mcasp0_hwmod = {
- + 	.name		= "mcasp0",
- + 	.class		= &am33xx_mcasp_hwmod_class,
- + 	.clkdm_name	= "l3s_clkdm",
- + 	.mpu_irqs	= am33xx_mcasp0_irqs,
- + 	.sdma_reqs	= am33xx_mcasp0_edma_reqs,
- + 	.main_clk	= "mcasp0_fck",
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.slaves		= am33xx_mcasp0_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_mcasp0_slaves),
- + };
- + 
- + /* mcasp1 */
- + static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
- + 	{ .name = "ax", .irq = 82, },
- + 	{ .name = "ar", .irq = 83, },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = {
- + 	{ .name = "tx", .dma_req = AM33XX_DMA_MCASP1_X, },
- + 	{ .name = "rx", .dma_req = AM33XX_DMA_MCASP1_R, },
- + 	{ .dma_req = -1 }
- + };
- + 
- + 
- + static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
- + 	{
- + 		.pa_start	= 0x4803C000,
- + 		.pa_end		= 0x4803C000 + (SZ_1K * 12) - 1,
- + 		.flags		= ADDR_TYPE_RT
- + 	},
- + 	{ }
- + };
- + 
- + static struct omap_hwmod_ocp_if am33xx_l3_slow__mcasp1 = {
- + 	.master		= &am33xx_l3slow_hwmod,
- + 	.slave		= &am33xx_mcasp1_hwmod,
- + 	.clk		= "mcasp1_ick",
- + 	.addr		= am33xx_mcasp1_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_mcasp1_slaves[] = {
- + 	&am33xx_l3_slow__mcasp1,
- + };
- + 
- + static struct omap_hwmod am33xx_mcasp1_hwmod = {
- + 	.name		= "mcasp1",
- + 	.class		= &am33xx_mcasp_hwmod_class,
- + 	.clkdm_name	= "l3s_clkdm",
- + 	.mpu_irqs	= am33xx_mcasp1_irqs,
- + 	.sdma_reqs	= am33xx_mcasp1_edma_reqs,
- + 	.main_clk	= "mcasp1_fck",
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.slaves		= am33xx_mcasp1_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_mcasp1_slaves),
- + };
- + 
- + /* 'mmc' class */
- + static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
- + 	.rev_offs	= 0x1fc,
- + 	.sysc_offs	= 0x10,
- + 	.syss_offs	= 0x14,
- + 	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
- + 			SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
- + 			SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
- + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- + 	.sysc_fields	= &omap_hwmod_sysc_type1,
- + };
- + 
- + static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
- + 	.name		= "mmc",
- + 	.sysc		= &am33xx_mmc_sysc,
- + };
- + 
- + /* mmc0 */
- + static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
- + 	{ .irq = 64 },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
- + 	{ .name = "tx", .dma_req = 24, },
- + 	{ .name = "rx", .dma_req = 25, },
- + 	{ .dma_req = -1 }
- + };
- + 
- + static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
- + 	{
- + 		.pa_start	= 0x48060100,
- + 		.pa_end		= 0x48060100 + SZ_4K - 1,
- + 		.flags		= ADDR_TYPE_RT,
- + 	},
- + 	{ }
- + };
- + 
- + static struct omap_hwmod_ocp_if am33xx_l4ls__mmc0 = {
- + 	.master		= &am33xx_l4ls_hwmod,
- + 	.slave		= &am33xx_mmc0_hwmod,
- + 	.clk		= "mmc0_ick",
- + 	.addr		= am33xx_mmc0_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_mmc0_slaves[] = {
- + 	&am33xx_l4ls__mmc0,
- + };
- + 
- + static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
- + 	.flags		= OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
- + };
- + 
- + static struct omap_hwmod am33xx_mmc0_hwmod = {
- + 	.name		= "mmc1",
- + 	.class		= &am33xx_mmc_hwmod_class,
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.mpu_irqs	= am33xx_mmc0_irqs,
- + 	.main_clk	= "mmc0_fck",
- + 	.sdma_reqs	= am33xx_mmc0_edma_reqs,
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.dev_attr	= &am33xx_mmc0_dev_attr,
- + 	.slaves		= am33xx_mmc0_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_mmc0_slaves),
- + };
- + 
- + /* mmc1 */
- + static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
- + 	{ .irq = 28 },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
- + 	{ .name = "tx", .dma_req = 2, },
- + 	{ .name = "rx", .dma_req = 3, },
- + 	{ .dma_req = -1 }
- + };
- + 
- + static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
- + 	{
- + 		.pa_start	= 0x481D8100,
- + 		.pa_end		= 0x481D8100 + SZ_4K - 1,
- + 		.flags		= ADDR_TYPE_RT,
- + 	},
- + 	{ }
- + };
- + 
- + static struct omap_hwmod_ocp_if am33xx_l4ls__mmc1 = {
- + 	.master		= &am33xx_l4ls_hwmod,
- + 	.slave		= &am33xx_mmc1_hwmod,
- + 	.clk		= "mmc1_ick",
- + 	.addr		= am33xx_mmc1_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_mmc1_slaves[] = {
- + 	&am33xx_l4ls__mmc1,
- + };
- + 
- + static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
- + 	.flags		= OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
- + };
- + 
- + static struct omap_hwmod am33xx_mmc1_hwmod = {
- + 	.name		= "mmc2",
- + 	.class		= &am33xx_mmc_hwmod_class,
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.mpu_irqs	= am33xx_mmc1_irqs,
- + 	.main_clk	= "mmc1_fck",
- + 	.sdma_reqs	= am33xx_mmc1_edma_reqs,
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.dev_attr	= &am33xx_mmc1_dev_attr,
- + 	.slaves		= am33xx_mmc1_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_mmc1_slaves),
- + };
- + 
- + /* mmc2 */
- + static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
- + 	{ .irq = 29 },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
- + 	{ .name = "tx", .dma_req = 64, },
- + 	{ .name = "rx", .dma_req = 65, },
- + 	{ .dma_req = -1 }
- + };
- + 
- + static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
- + 	{
- + 		.pa_start	= 0x47810100,
- + 		.pa_end		= 0x47810100 + SZ_64K - 1,
- + 		.flags		= ADDR_TYPE_RT,
- + 	},
- + 	{ }
- + };
- + 
- + static struct omap_hwmod_ocp_if am33xx_l3_main__mmc2 = {
- + 	.master		= &am33xx_l3_main_hwmod,
- + 	.slave		= &am33xx_mmc2_hwmod,
- + 	.clk		= "mmc2_ick",
- + 	.addr		= am33xx_mmc2_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_mmc2_slaves[] = {
- + 	&am33xx_l3_main__mmc2,
- + };
- + 
- + static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
- + 	.flags		= OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
- + };
- + static struct omap_hwmod am33xx_mmc2_hwmod = {
- + 	.name		= "mmc3",
- + 	.class		= &am33xx_mmc_hwmod_class,
- + 	.clkdm_name	= "l3s_clkdm",
- + 	.mpu_irqs	= am33xx_mmc2_irqs,
- + 	.main_clk	= "mmc2_fck",
- + 	.sdma_reqs	= am33xx_mmc2_edma_reqs,
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.dev_attr	= &am33xx_mmc2_dev_attr,
- + 	.slaves		= am33xx_mmc2_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_mmc2_slaves),
- + };
- + 
- + /* Master interfaces on the MPU interconnect */
- + static struct omap_hwmod_ocp_if *am33xx_l3_mpu_masters[] = {
- + 	&am33xx_mpu__l3_slow,
- + };
- + 
- + /* mpu */
- + static struct omap_hwmod am33xx_mpu_hwmod = {
- + 	.name		= "mpu",
- + 	.class		= &mpu_hwmod_class,
- + 	.clkdm_name	= "mpu_clkdm",
- + 	.main_clk	= "mpu_fck",
- + 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.masters	= am33xx_l3_mpu_masters,
- + 	.masters_cnt	= ARRAY_SIZE(am33xx_l3_mpu_masters),
- + };
- + 
- + /* ocmcram */
- + static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
- + 	.name = "ocmcram",
- + };
- + 
- + static struct omap_hwmod am33xx_ocmcram_hwmod = {
- + 	.name		= "ocmcram",
- + 	.class		= &am33xx_ocmcram_hwmod_class,
- + 	.clkdm_name	= "l3_clkdm",
- + 	.main_clk	= "ocmcram_ick",
- + 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + };
- + 
- + /* ocpwp */
- + static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
- + 	.name		= "ocpwp",
- + };
- + 
- + static struct omap_hwmod am33xx_ocpwp_hwmod = {
- + 	.name		= "ocpwp",
- + 	.class		= &am33xx_ocpwp_hwmod_class,
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.main_clk	= "ocpwp_fck",
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + };
- + 
- + static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
- + 	.rev_offs	= 0x74,
- + 	.sysc_offs	= 0x78,
- + 	.sysc_flags	= SYSC_HAS_SIDLEMODE,
- + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- + 			SIDLE_SMART_WKUP),
- + 	.sysc_fields	= &omap_hwmod_sysc_type3,
- + };
- + 
- + /* rtc */
- + static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
- + 	.name		= "rtc",
- + 	.sysc		= &am33xx_rtc_sysc,
- + };
- + 
- + static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
- + 	{ .irq = 75 },
- + 	{ .irq = 76 },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod_addr_space am33xx_rtc_addrs[] = {
- + 	{
- + 		.pa_start	= 0x44E3E000,
- + 		.pa_end		= 0x44E3E000 + SZ_4K - 1,
- + 		.flags		= ADDR_TYPE_RT
- + 	},
- + 	{ }
- + };
- + 
- + static struct omap_hwmod_ocp_if am33xx_l4_wkup_rtc = {
- + 	.master		= &am33xx_l4wkup_hwmod,
- + 	.slave		= &am33xx_rtc_hwmod,
- + 	.clk		= "rtc_ick",
- + 	.addr		= am33xx_rtc_addrs,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_adc_rtc_slaves[] = {
- + 	&am33xx_l4_wkup_rtc,
- + };
- + 
- + static struct omap_hwmod am33xx_rtc_hwmod = {
- + 	.name		= "rtc",
- + 	.class		= &am33xx_rtc_hwmod_class,
- + 	.clkdm_name	= "l4_rtc_clkdm",
- + 	.mpu_irqs	= am33xx_rtc_irqs,
- + 	.main_clk	= "rtc_fck",
- + 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), /* ??? */
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.slaves		= am33xx_adc_rtc_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_adc_rtc_slaves),
- + };
- + 
- + /* sha0 */
- + static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
- + 	.rev_offs	= 0x100,
- + 	.sysc_offs	= 0x110,
- + 	.syss_offs	= 0x114,
- + 	.sysc_flags	= SYSS_HAS_RESET_STATUS,
- + };
- + 
- + static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
- + 	.name		= "sha0",
- + 	.sysc		= &am33xx_sha0_sysc,
- + };
- + 
- + static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
- + 	{ .irq = AM33XX_IRQ_SHAEIP57t0_P },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod_dma_info am33xx_sha0_dma[] = {
- + 	{ .dma_req = AM33XX_DMA_SHAEIP57T0_DIN },
- + 	{ .dma_req = -1 }
- + };
- + 
- + struct omap_hwmod_addr_space am33xx_sha0_addr_space[] = {
- + 	{
- + 		.pa_start	= 0x53100000,
- + 		.pa_end		= 0x53100000 + SZ_1M - 1,
- + 		.flags		= ADDR_TYPE_RT,
- + 	},
- + 	{ }
- + };
- + 
- + struct omap_hwmod_ocp_if am33xx_l3_core__sha0 = {
- + 	.master		= &am33xx_l3_main_hwmod,
- + 	.slave		= &am33xx_sha0_hwmod,
- + 	.clk		= "sha0_fck",
- + 	.addr		= am33xx_sha0_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_sha0_slaves[] = {
- + 	&am33xx_l3_core__sha0,
- + };
- + 
- + static struct omap_hwmod am33xx_sha0_hwmod = {
- + 	.name		= "sha0",
- + 	.class		= &am33xx_sha0_hwmod_class,
- + 	.clkdm_name	= "l3_clkdm",
- + 	.mpu_irqs	= am33xx_sha0_irqs,
- + 	.sdma_reqs	= am33xx_sha0_dma,
- + 	.main_clk	= "sha0_fck",
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.slaves		= am33xx_sha0_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_sha0_slaves),
- + };
- + 
- + /* 'smartreflex' class */
- + static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
- + 	.name		= "smartreflex",
- + };
- + 
- + /* smartreflex0 */
- + static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
- + 	{ .irq = 120 },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod am33xx_smartreflex0_hwmod = {
- + 	.name		= "smartreflex0",
- + 	.class		= &am33xx_smartreflex_hwmod_class,
- + 	.clkdm_name	= "l4_wkup_clkdm",
- + 	.mpu_irqs	= am33xx_smartreflex0_irqs,
- + 	.main_clk	= "smartreflex0_fck",
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + };
- + 
- + /* smartreflex1 */
- + static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
- + 	{ .irq = 121 },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod am33xx_smartreflex1_hwmod = {
- + 	.name		= "smartreflex1",
- + 	.class		= &am33xx_smartreflex_hwmod_class,
- + 	.clkdm_name	= "l4_wkup_clkdm",
- + 	.mpu_irqs	= am33xx_smartreflex1_irqs,
- + 	.main_clk	= "smartreflex1_fck",
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + };
- + 
- + /* 'spi' class */
- + static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
- + 	.rev_offs	= 0x0000,
- + 	.sysc_offs	= 0x0110,
- + 	.syss_offs	= 0x0114,
- + 	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
- + 			SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
- + 			SYSS_HAS_RESET_STATUS),
- + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- + 	.sysc_fields	= &omap_hwmod_sysc_type1,
- + };
- + 
- + static struct omap_hwmod_class am33xx_spi_hwmod_class = {
- + 	.name		= "mcspi",
- + 	.sysc		= &am33xx_mcspi_sysc,
- + 	.rev		= OMAP4_MCSPI_REV,
- + };
- + 
- + /* spi0 */
- + static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
- + 	{ .irq = 65 },
- + 	{ .irq = -1 }
- + };
- + 
- + struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = {
- + 	{ .name = "rx0", .dma_req = 17 },
- + 	{ .name = "tx0", .dma_req = 16 },
- + 	{ .name = "rx1", .dma_req = 19 },
- + 	{ .name = "tx1", .dma_req = 18 },
- + 	{ .dma_req = -1 }
- + };
- + 
- + struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
- + 	{
- + 		.pa_start	= 0x48030000,
- + 		.pa_end		= 0x48030000 + SZ_1K - 1,
- + 		.flags		= ADDR_TYPE_RT,
- + 	},
- + 	{ }
- + };
- + 
- + struct omap_hwmod_ocp_if am33xx_l4_core__mcspi0 = {
- + 	.master		= &am33xx_l4per_hwmod,
- + 	.slave		= &am33xx_spi0_hwmod,
- + 	.clk		= "spi0_ick",
- + 	.addr		= am33xx_mcspi0_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_mcspi0_slaves[] = {
- + 	&am33xx_l4_core__mcspi0,
- + };
- + 
- + struct omap2_mcspi_dev_attr mcspi_attrib = {
- + 	.num_chipselect	= 2,
- + };
- + static struct omap_hwmod am33xx_spi0_hwmod = {
- + 	.name		= "spi0",
- + 	.class		= &am33xx_spi_hwmod_class,
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.mpu_irqs	= am33xx_spi0_irqs,
- + 	.main_clk	= "spi0_fck",
- + 	.sdma_reqs	= am33xx_mcspi0_edma_reqs,
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.dev_attr	= &mcspi_attrib,
- + 	.slaves		= am33xx_mcspi0_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_mcspi0_slaves),
- + };
- + 
- + /* spi1 */
- + static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
- + 	{ .irq = 125 },
- + 	{ .irq = -1 }
- + };
- + 
- + struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = {
- + 	{ .name = "rx0", .dma_req = 43 },
- + 	{ .name = "tx0", .dma_req = 42 },
- + 	{ .name = "rx1", .dma_req = 45 },
- + 	{ .name = "tx1", .dma_req = 44 },
- + 	{ .dma_req = -1 }
- + };
- + 
- + struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
- + 	{
- + 		.pa_start	= 0x481A0000,
- + 		.pa_end		= 0x481A0000 + SZ_1K - 1,
- + 		.flags		= ADDR_TYPE_RT,
- + 	},
- + 	{ }
- + };
- + 
- + struct omap_hwmod_ocp_if am33xx_l4_core__mcspi1 = {
- + 	.master		= &am33xx_l4per_hwmod,
- + 	.slave		= &am33xx_spi1_hwmod,
- + 	.clk		= "spi1_ick",
- + 	.addr		= am33xx_mcspi1_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_mcspi1_slaves[] = {
- + 	&am33xx_l4_core__mcspi1,
- + };
- + static struct omap_hwmod am33xx_spi1_hwmod = {
- + 	.name		= "spi1",
- + 	.class		= &am33xx_spi_hwmod_class,
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.mpu_irqs	= am33xx_spi1_irqs,
- + 	.main_clk	= "spi1_fck",
- + 	.sdma_reqs	= am33xx_mcspi1_edma_reqs,
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.dev_attr	= &mcspi_attrib,
- + 	.slaves		= am33xx_mcspi1_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_mcspi1_slaves),
- + };
- + 
- + /* spinlock */
- + static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
- + 	.name		= "spinlock",
- + };
- + 
- + static struct omap_hwmod am33xx_spinlock_hwmod = {
- + 	.name		= "spinlock",
- + 	.class		= &am33xx_spinlock_hwmod_class,
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.main_clk	= "spinlock_fck",
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + };
- + 
- + /* 'timer 0 & 2-7' class */
- + static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
- + 	.rev_offs	= 0x0000,
- + 	.sysc_offs	= 0x0010,
- + 	.syss_offs	= 0x0014,
- + 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
- + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- + 			SIDLE_SMART_WKUP),
- + 	.sysc_fields	= &omap_hwmod_sysc_type2,
- + };
- + 
- + static struct omap_hwmod_class am33xx_timer_hwmod_class = {
- + 	.name		= "timer",
- + 	.sysc		= &am33xx_timer_sysc,
- + };
- + 
- + /* timer0 */
- + /* l4 wkup -> timer0 interface */
- + static struct omap_hwmod_addr_space am33xx_timer0_addr_space[] = {
- + 	{
- + 		.pa_start	= 0x44E05000,
- + 		.pa_end		= 0x44E05000 + SZ_1K - 1,
- + 		.flags		= ADDR_TYPE_RT
- + 	},
- + 	{ }
- + };
- + 
- + static struct omap_hwmod_ocp_if am33xx_l4wkup__timer0 = {
- + 	.master		= &am33xx_l4wkup_hwmod,
- + 	.slave		= &am33xx_timer0_hwmod,
- + 	.clk		= "timer0_ick",
- + 	.addr		= am33xx_timer0_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_timer0_slaves[] = {
- + 	&am33xx_l4wkup__timer0,
- + };
- + 
- + static struct omap_hwmod_irq_info am33xx_timer0_irqs[] = {
- + 	{ .irq = 66 },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod am33xx_timer0_hwmod = {
- + 	.name		= "timer0",
- + 	.class		= &am33xx_timer_hwmod_class,
- + 	.clkdm_name	= "l4_wkup_clkdm",
- + 	.mpu_irqs	= am33xx_timer0_irqs,
- + 	.main_clk	= "timer0_fck",
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.slaves		= am33xx_timer0_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_timer0_slaves),
- + 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
- + };
- + 
- + /* timer1 1ms */
- + static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
- + 	.rev_offs	= 0x0000,
- + 	.sysc_offs	= 0x0010,
- + 	.syss_offs	= 0x0014,
- + 	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
- + 			SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
- + 			SYSS_HAS_RESET_STATUS),
- + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- + 	.sysc_fields	= &omap_hwmod_sysc_type1,
- + };
- + 
- + static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
- + 	.name		= "timer",
- + 	.sysc		= &am33xx_timer1ms_sysc,
- + };
- + 
- + /* l4 wkup -> timer1 interface */
- + static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
- + 	{
- + 		.pa_start	= 0x44E31000,
- + 		.pa_end		= 0x44E31000 + SZ_1K - 1,
- + 		.flags		= ADDR_TYPE_RT
- + 	},
- + 	{ }
- + };
- + 
- + static struct omap_hwmod_ocp_if am33xx_l4wkup__timer1 = {
- + 	.master		= &am33xx_l4wkup_hwmod,
- + 	.slave		= &am33xx_timer1_hwmod,
- + 	.clk		= "timer1_ick",
- + 	.addr		= am33xx_timer1_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_timer1_slaves[] = {
- + 	&am33xx_l4wkup__timer1,
- + };
- + 
- + static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
- + 	{ .irq = 67 },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod am33xx_timer1_hwmod = {
- + 	.name		= "timer1",
- + 	.class		= &am33xx_timer1ms_hwmod_class,
- + 	.clkdm_name	= "l4_wkup_clkdm",
- + 	.mpu_irqs	= am33xx_timer1_irqs,
- + 	.main_clk	= "timer1_fck",
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.slaves		= am33xx_timer1_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_timer1_slaves),
- + };
- + 
- + /* timer2 */
- + /* l4 per -> timer2 interface */
- + static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
- + 	{
- + 		.pa_start	= 0x48040000,
- + 		.pa_end		= 0x48040000 + SZ_1K - 1,
- + 		.flags		= ADDR_TYPE_RT
- + 	},
- + 	{ }
- + };
- + 
- + static struct omap_hwmod_ocp_if am33xx_l4per__timer2 = {
- + 	.master		= &am33xx_l4per_hwmod,
- + 	.slave		= &am33xx_timer2_hwmod,
- + 	.clk		= "timer2_ick",
- + 	.addr		= am33xx_timer2_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_timer2_slaves[] = {
- + 	&am33xx_l4per__timer2,
- + };
- + 
- + static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
- + 	{ .irq = 68 },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod am33xx_timer2_hwmod = {
- + 	.name		= "timer2",
- + 	.class		= &am33xx_timer_hwmod_class,
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.mpu_irqs	= am33xx_timer2_irqs,
- + 	.main_clk	= "timer2_fck",
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.slaves		= am33xx_timer2_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_timer2_slaves),
- + };
- + 
- + /* timer3 */
- + /* l4 per -> timer3 interface */
- + static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
- + 	{
- + 		.pa_start	= 0x48042000,
- + 		.pa_end		= 0x48042000 + SZ_1K - 1,
- + 		.flags		= ADDR_TYPE_RT
- + 	},
- + 	{ }
- + };
- + 
- + static struct omap_hwmod_ocp_if am33xx_l4per__timer3 = {
- + 	.master		= &am33xx_l4per_hwmod,
- + 	.slave		= &am33xx_timer3_hwmod,
- + 	.clk		= "timer3_ick",
- + 	.addr		= am33xx_timer3_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_timer3_slaves[] = {
- + 	&am33xx_l4per__timer3,
- + };
- + 
- + static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
- + 	{ .irq = 69 },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod am33xx_timer3_hwmod = {
- + 	.name		= "timer3",
- + 	.class		= &am33xx_timer_hwmod_class,
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.mpu_irqs	= am33xx_timer3_irqs,
- + 	.main_clk	= "timer3_fck",
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.slaves		= am33xx_timer3_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_timer3_slaves),
- + };
- + 
- + /* timer4 */
- + /* l4 per -> timer4 interface */
- + static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
- + 	{
- + 		.pa_start	= 0x48044000,
- + 		.pa_end		= 0x48044000 + SZ_1K - 1,
- + 		.flags		= ADDR_TYPE_RT
- + 	},
- + 	{ }
- + };
- + 
- + static struct omap_hwmod_ocp_if am33xx_l4per__timer4 = {
- + 	.master		= &am33xx_l4per_hwmod,
- + 	.slave		= &am33xx_timer4_hwmod,
- + 	.clk		= "timer4_ick",
- + 	.addr		= am33xx_timer4_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_timer4_slaves[] = {
- + 	&am33xx_l4per__timer4,
- + };
- + 
- + static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
- + 	{ .irq = 92 },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod am33xx_timer4_hwmod = {
- + 	.name		= "timer4",
- + 	.class		= &am33xx_timer_hwmod_class,
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.mpu_irqs	= am33xx_timer4_irqs,
- + 	.main_clk	= "timer4_fck",
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.slaves		= am33xx_timer4_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_timer4_slaves),
- + };
- + 
- + /* timer5 */
- + /* l4 per -> timer5 interface */
- + static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
- + 	{
- + 		.pa_start	= 0x48046000,
- + 		.pa_end		= 0x48046000 + SZ_1K - 1,
- + 		.flags		= ADDR_TYPE_RT
- + 	},
- + 	{ }
- + };
- + 
- + static struct omap_hwmod_ocp_if am33xx_l4per__timer5 = {
- + 	.master		= &am33xx_l4per_hwmod,
- + 	.slave		= &am33xx_timer5_hwmod,
- + 	.clk		= "timer5_ick",
- + 	.addr		= am33xx_timer5_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_timer5_slaves[] = {
- + 	&am33xx_l4per__timer5,
- + };
- + 
- + static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
- + 	{ .irq = 93 },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod am33xx_timer5_hwmod = {
- + 	.name		= "timer5",
- + 	.class		= &am33xx_timer_hwmod_class,
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.mpu_irqs	= am33xx_timer5_irqs,
- + 	.main_clk	= "timer5_fck",
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.slaves		= am33xx_timer5_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_timer5_slaves),
- + };
- + 
- + /* timer6 */
- + /* l4 per -> timer6 interface */
- + static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
- + 	{
- + 		.pa_start	= 0x48048000,
- + 		.pa_end		= 0x48048000 + SZ_1K - 1,
- + 		.flags		= ADDR_TYPE_RT
- + 	},
- + 	{ }
- + };
- + 
- + static struct omap_hwmod_ocp_if am33xx_l4per__timer6 = {
- + 	.master		= &am33xx_l4per_hwmod,
- + 	.slave		= &am33xx_timer6_hwmod,
- + 	.clk		= "timer6_ick",
- + 	.addr		= am33xx_timer6_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_timer6_slaves[] = {
- + 	&am33xx_l4per__timer6,
- + };
- + 
- + static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
- + 	{ .irq = 94 },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod am33xx_timer6_hwmod = {
- + 	.name		= "timer6",
- + 	.class		= &am33xx_timer_hwmod_class,
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.mpu_irqs	= am33xx_timer6_irqs,
- + 	.main_clk	= "timer6_fck",
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.slaves		= am33xx_timer6_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_timer6_slaves),
- + };
- + 
- + /* timer7 */
- + /* l4 per -> timer7 interface */
- + static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
- + 	{
- + 		.pa_start	= 0x4804A000,
- + 		.pa_end		= 0x4804A000 + SZ_1K - 1,
- + 		.flags		= ADDR_TYPE_RT
- + 	},
- + 	{ }
- + };
- + 
- + static struct omap_hwmod_ocp_if am33xx_l4per__timer7 = {
- + 	.master		= &am33xx_l4per_hwmod,
- + 	.slave		= &am33xx_timer7_hwmod,
- + 	.clk		= "timer7_ick",
- + 	.addr		= am33xx_timer7_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_timer7_slaves[] = {
- + 	&am33xx_l4per__timer7,
- + };
- + 
- + static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
- + 	{ .irq = 95 },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod am33xx_timer7_hwmod = {
- + 	.name		= "timer7",
- + 	.class		= &am33xx_timer_hwmod_class,
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.mpu_irqs	= am33xx_timer7_irqs,
- + 	.main_clk	= "timer7_fck",
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.slaves		= am33xx_timer7_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_timer7_slaves),
- + };
- + 
- + /* tpcc */
- + #define AM33XX_TPCC_BASE		0x49000000
- + #define AM33XX_TPTC0_BASE		0x49800000
- + #define AM33XX_TPTC1_BASE		0x49900000
- + #define AM33XX_TPTC2_BASE		0x49a00000
- + 
- + /* 'tpcc' class */
- + static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
- + 	.name		= "tpcc",
- + };
- + 
- + static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
- + 	{ .name	= "edma0", .irq = 12 },
- + 	{ .name = "edma0_mperr", .irq = 13, },
- + 	{ .name	= "edma0_err", .irq = 14 },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
- + 	{
- + 		.name		= "edma_cc0",
- + 		.pa_start	= AM33XX_TPCC_BASE,
- + 		.pa_end		= AM33XX_TPCC_BASE + SZ_32K - 1,
- + 		.flags		= ADDR_TYPE_RT
- + 	},
- + 	{ }
- + };
- + 
- + static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
- + 	.master		= &am33xx_l3_main_hwmod,
- + 	.slave		= &am33xx_tpcc_hwmod,
- + 	.addr		= am33xx_tpcc_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_tpcc_slaves[] = {
- + 	&am33xx_l3_main__tpcc,
- + };
- + 
- + static struct omap_hwmod am33xx_tpcc_hwmod = {
- + 	.name		= "tpcc",
- + 	.class		= &am33xx_tpcc_hwmod_class,
- + 	.clkdm_name	= "l3_clkdm",
- + 	.mpu_irqs	= am33xx_tpcc_irqs,
- + 	.main_clk	= "tpcc_ick",
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.slaves		= am33xx_tpcc_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_tpcc_slaves),
- + };
- + 
- + static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
- + 	.rev_offs	= 0x0,
- + 	.sysc_offs	= 0x10,
- + 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- + 			SYSC_HAS_MIDLEMODE),
- + 	.idlemodes	= (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
- + 	.sysc_fields	= &omap_hwmod_sysc_type2,
- + };
- + 
- + /* 'tptc' class */
- + static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
- + 	.name		= "tptc",
- + 	.sysc		= &am33xx_tptc_sysc,
- + };
- + 
- + /* tptc0 */
- + static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
- + 	{ .irq = 112 },
- + 	{ .irq = -1 }
- + };
- + 
- + struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
- + 	{
- + 		.name		= "edma_tc0",
- + 		.pa_start	= AM33XX_TPTC0_BASE,
- + 		.pa_end		= AM33XX_TPTC0_BASE + SZ_8K - 1,
- + 		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
- + 	},
- + 	{ }
- + };
- + 
- + struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
- + 	.master		= &am33xx_l3_main_hwmod,
- + 	.slave		= &am33xx_tptc0_hwmod,
- + 	.addr		= am33xx_tptc0_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_tptc0_slaves[] = {
- + 	&am33xx_l3_main__tptc0,
- + };
- + 
- + static struct omap_hwmod am33xx_tptc0_hwmod = {
- + 	.name		= "tptc0",
- + 	.class		= &am33xx_tptc_hwmod_class,
- + 	.clkdm_name	= "l3_clkdm",
- + 	.mpu_irqs	= am33xx_tptc0_irqs,
- + 	.main_clk	= "tptc0_ick",
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.slaves		= am33xx_tptc0_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_tptc0_slaves),
- + 	.flags		= (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
- + };
- + 
- + /* tptc1 */
- + static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
- + 	{ .irq = 113 },
- + 	{ .irq = -1 }
- + };
- + 
- + struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
- + 	{
- + 		.name		= "edma_tc1",
- + 		.pa_start	= AM33XX_TPTC1_BASE,
- + 		.pa_end		= AM33XX_TPTC1_BASE + SZ_8K - 1,
- + 		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
- + 	},
- + 	{ }
- + };
- + 
- + struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
- + 	.master		= &am33xx_l3_main_hwmod,
- + 	.slave		= &am33xx_tptc1_hwmod,
- + 	.addr		= am33xx_tptc1_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_tptc1_slaves[] = {
- + 	&am33xx_l3_main__tptc1,
- + };
- + 
- + static struct omap_hwmod am33xx_tptc1_hwmod = {
- + 	.name		= "tptc1",
- + 	.class		= &am33xx_tptc_hwmod_class,
- + 	.clkdm_name	= "l3_clkdm",
- + 	.mpu_irqs	= am33xx_tptc1_irqs,
- + 	.main_clk	= "tptc1_ick",
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.slaves		= am33xx_tptc1_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_tptc1_slaves),
- + 	.flags		= (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
- + };
- + 
- + /* tptc2 */
- + static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
- + 	{ .irq = 114 },
- + 	{ .irq = -1 }
- + };
- + 
- + struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
- + 	{
- + 		.name		= "edma_tc2",
- + 		.pa_start	= AM33XX_TPTC2_BASE,
- + 		.pa_end		= AM33XX_TPTC2_BASE + SZ_8K - 1,
- + 		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
- + 	},
- + 	{ }
- + };
- + 
- + struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
- + 	.master		= &am33xx_l3_main_hwmod,
- + 	.slave		= &am33xx_tptc2_hwmod,
- + 	.addr		= am33xx_tptc2_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_tptc2_slaves[] = {
- + 	&am33xx_l3_main__tptc2,
- + };
- + 
- + static struct omap_hwmod am33xx_tptc2_hwmod = {
- + 	.name		= "tptc2",
- + 	.class		= &am33xx_tptc_hwmod_class,
- + 	.clkdm_name	= "l3_clkdm",
- + 	.mpu_irqs	= am33xx_tptc2_irqs,
- + 	.main_clk	= "tptc2_ick",
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.slaves		= am33xx_tptc2_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_tptc2_slaves),
- + 	.flags		= (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
- + };
- + 
- + /* 'uart' class */
- + static struct omap_hwmod_class_sysconfig uart_sysc = {
- + 	.rev_offs	= 0x50,
- + 	.sysc_offs	= 0x54,
- + 	.syss_offs	= 0x58,
- + 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
- + 			SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
- + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- + 			SIDLE_SMART_WKUP),
- + 	.sysc_fields	= &omap_hwmod_sysc_type1,
- + };
- + 
- + static struct omap_hwmod_class uart_class = {
- + 	.name		= "uart",
- + 	.sysc		= &uart_sysc,
- + };
- + 
- + /* uart1 */
- + static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
- + 	{ .name = "tx",	.dma_req = 26, },
- + 	{ .name = "rx",	.dma_req = 27, },
- + 	{ .dma_req = -1 }
- + };
- + 
- + static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
- + 	{
- + 		.pa_start	= 0x44E09000,
- + 		.pa_end		= 0x44E09000 + SZ_8K - 1,
- + 		.flags		= ADDR_TYPE_RT,
- + 	},
- + 	{ }
- + };
- + 
- + static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
- + 	.master		= &am33xx_l4wkup_hwmod,
- + 	.slave		= &am33xx_uart1_hwmod,
- + 	.clk		= "uart1_ick",
- + 	.addr		= am33xx_uart1_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
- + 	{ .irq = 72 },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_uart1_slaves[] = {
- + 	&am33xx_l4_wkup__uart1,
- + };
- + 
- + static struct omap_hwmod am33xx_uart1_hwmod = {
- + 	.name		= "uart1",
- + 	.class		= &uart_class,
- + 	.clkdm_name	= "l4_wkup_clkdm",
- + 	.mpu_irqs	= am33xx_uart1_irqs,
- + 	.main_clk	= "uart1_fck",
- + 	.sdma_reqs	= uart1_edma_reqs,
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.slaves		= am33xx_uart1_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_uart1_slaves),
- + };
- + 
- + /* uart2 */
- + static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
- + 	{
- + 		.pa_start	= 0x48022000,
- + 		.pa_end		= 0x48022000 + SZ_8K - 1,
- + 		.flags		= ADDR_TYPE_RT,
- + 	},
- + 	{ }
- + };
- + 
- + static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
- + 	.slave		= &am33xx_uart2_hwmod,
- + 	.clk		= "uart2_ick",
- + 	.addr		= am33xx_uart2_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
- + 	{ .irq = 73 },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_uart2_slaves[] = {
- + 	&am33xx_l4_ls__uart2,
- + };
- + 
- + static struct omap_hwmod am33xx_uart2_hwmod = {
- + 	.name		= "uart2",
- + 	.class		= &uart_class,
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.mpu_irqs	= am33xx_uart2_irqs,
- + 	.main_clk	= "uart2_fck",
- + 	.sdma_reqs	= uart1_edma_reqs,
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.slaves		= am33xx_uart2_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_uart2_slaves),
- + };
- + 
- + /* uart3 */
- + static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
- + 	{ .name = "tx",	.dma_req = 30, },
- + 	{ .name = "rx",	.dma_req = 31, },
- + 	{ .dma_req = -1 }
- + };
- + 
- + static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
- + 	{
- + 		.pa_start	= 0x48024000,
- + 		.pa_end		= 0x48024000 + SZ_8K - 1,
- + 		.flags		= ADDR_TYPE_RT,
- + 	},
- + 	{ }
- + };
- + 
- + static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
- + 	.slave		= &am33xx_uart3_hwmod,
- + 	.clk		= "uart3_ick",
- + 	.addr		= am33xx_uart3_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
- + 	{ .irq = 74 },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_uart3_slaves[] = {
- + 	&am33xx_l4_ls__uart3,
- + };
- + 
- + static struct omap_hwmod am33xx_uart3_hwmod = {
- + 	.name		= "uart3",
- + 	.class		= &uart_class,
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.mpu_irqs	= am33xx_uart3_irqs,
- + 	.main_clk	= "uart3_fck",
- + 	.sdma_reqs	= uart3_edma_reqs,
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.slaves		= am33xx_uart3_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_uart3_slaves),
- + };
- + 
- + /* uart4 */
- + static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
- + 	{
- + 		.pa_start	= 0x481A6000,
- + 		.pa_end		= 0x481A6000 + SZ_8K - 1,
- + 		.flags		= ADDR_TYPE_RT,
- + 	},
- + 	{ }
- + };
- + 
- + static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
- + 	.slave		= &am33xx_uart4_hwmod,
- + 	.clk		= "uart4_ick",
- + 	.addr		= am33xx_uart4_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
- + 	{ .irq = 44 },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_uart4_slaves[] = {
- + 	&am33xx_l4_ls__uart4,
- + };
- + 
- + static struct omap_hwmod am33xx_uart4_hwmod = {
- + 	.name		= "uart4",
- + 	.class		= &uart_class,
- + 	.mpu_irqs	= am33xx_uart4_irqs,
- + 	.main_clk	= "uart4_fck",
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.sdma_reqs	= uart1_edma_reqs,
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.slaves		= am33xx_uart4_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_uart4_slaves),
- + };
- + 
- + /* uart5 */
- + static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
- + 	{
- + 		.pa_start	= 0x481A8000,
- + 		.pa_end		= 0x481A8000 + SZ_8K - 1,
- + 		.flags		= ADDR_TYPE_RT,
- + 	},
- + 	{ }
- + };
- + 
- + static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
- + 	.slave		= &am33xx_uart5_hwmod,
- + 	.clk		= "uart5_ick",
- + 	.addr		= am33xx_uart5_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
- + 	{ .irq = 45 },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_uart5_slaves[] = {
- + 	&am33xx_l4_ls__uart5,
- + };
- + 
- + static struct omap_hwmod am33xx_uart5_hwmod = {
- + 	.name		= "uart5",
- + 	.class		= &uart_class,
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.mpu_irqs	= am33xx_uart5_irqs,
- + 	.main_clk	= "uart5_fck",
- + 	.sdma_reqs	= uart1_edma_reqs,
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.slaves		= am33xx_uart5_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_uart5_slaves),
- + };
- + 
- + /* uart6 */
- + static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
- + 	{
- + 		.pa_start	= 0x481AA000,
- + 		.pa_end		= 0x481AA000 + SZ_8K - 1,
- + 		.flags		= ADDR_TYPE_RT,
- + 	},
- + 	{ }
- + };
- + 
- + static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
- + 	.slave		= &am33xx_uart6_hwmod,
- + 	.clk		= "uart6_ick",
- + 	.addr		= am33xx_uart6_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
- + 	{ .irq = 46 },
- + 	{ .irq = -1 }
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_uart6_slaves[] = {
- + 	&am33xx_l4_ls__uart6,
- + };
- + 
- + static struct omap_hwmod am33xx_uart6_hwmod = {
- + 	.name		= "uart6",
- + 	.class		= &uart_class,
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.mpu_irqs	= am33xx_uart6_irqs,
- + 	.main_clk	= "uart6_fck",
- + 	.sdma_reqs	= uart1_edma_reqs,
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.slaves		= am33xx_uart6_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_uart6_slaves),
- + };
- + 
- + /* 'wd_timer' class */
- + static struct omap_hwmod_class_sysconfig wdt_sysc = {
- + 	.rev_offs	= 0x0,
- + 	.sysc_offs	= 0x10,
- + 	.syss_offs	= 0x14,
- + 	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
- + 			SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- + 			SIDLE_SMART_WKUP),
- + 	.sysc_fields	= &omap_hwmod_sysc_type1,
- + };
- + 
- + static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
- + 	.name		= "wd_timer",
- + 	.sysc		= &wdt_sysc,
- + 	.pre_shutdown	= &omap2_wd_timer_disable,
- + };
- + 
- + static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
- + 	{
- + 		.pa_start	= 0x44E35000,
- + 		.pa_end		= 0x44E35000 + SZ_4K - 1,
- + 		.flags		= ADDR_TYPE_RT
- + 	},
- + 	{ }
- + };
- + 
- + /* l4_wkup -> wd_timer1 */
- + static struct omap_hwmod_ocp_if am33xx_l4wkup__wd_timer1 = {
- + 	.master		= &am33xx_l4wkup_hwmod,
- + 	.slave		= &am33xx_wd_timer1_hwmod,
- + 	.addr		= am33xx_wd_timer1_addrs,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_wd_timer1_slaves[] = {
- + 	&am33xx_l4wkup__wd_timer1,
- + };
- + 
- + /*
- +  * TODO: device.c file uses hardcoded name for watchdog timer
- +  * driver "wd_timer2, so we are also using same name as of now...
- +  */
- + static struct omap_hwmod am33xx_wd_timer1_hwmod = {
- + 	.name		= "wd_timer2",
- + 	.class		= &am33xx_wd_timer_hwmod_class,
- + 	.clkdm_name	= "l4_wkup_clkdm",
- + 	.flags		= HWMOD_SWSUP_SIDLE,
- + 	.main_clk	= "wdt1_fck",
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.slaves		= am33xx_wd_timer1_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_wd_timer1_slaves),
- + };
- + 
- + /* wkup_m3 */
- + static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
- + 	.name		= "wkup_m3",
- + };
- + 
- + static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
- + 	{ .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
- + };
- + 
- + static struct omap_hwmod am33xx_wkup_m3_hwmod = {
- + 	.name		= "wkup_m3",
- + 	.class		= &am33xx_wkup_m3_hwmod_class,
- + 	.clkdm_name	= "l4_wkup_aon_clkdm",
- + 	.main_clk	= "wkup_m3_fck",
- + 	.flags		= HWMOD_INIT_NO_RESET,	/* Keep hardreset asserted */
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
- + 			.rstctrl_offs	= AM33XX_RM_WKUP_RSTCTRL_OFFSET,
- + 			.rstst_offs	= AM33XX_RM_WKUP_RSTST_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.rst_lines	= am33xx_wkup_m3_resets,
- + 	.rst_lines_cnt	= ARRAY_SIZE(am33xx_wkup_m3_resets),
- + };
- + 
- + /* usbss */
- + /* L3 SLOW -> USBSS interface */
- + static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
- + 	{
- + 		.name		= "usbss",
- + 		.pa_start	= 0x47400000,
- + 		.pa_end		= 0x47400000 + SZ_4K - 1,
- + 		.flags		= ADDR_TYPE_RT
- + 	},
- + 	{
- + 		.name		= "musb0",
- + 		.pa_start	= 0x47401000,
- + 		.pa_end		= 0x47401000 + SZ_2K - 1,
- + 		.flags		= ADDR_TYPE_RT
- + 	},
- + 	{
- + 		.name		= "musb1",
- + 		.pa_start	= 0x47401800,
- + 		.pa_end		= 0x47401800 + SZ_2K - 1,
- + 		.flags		= ADDR_TYPE_RT
- + 	},
- + 	{ }
- + };
- + 
- + static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
- + 	.rev_offs	= 0x0,
- + 	.sysc_offs	= 0x10,
- + 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
- + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- + 			MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
- + 	.sysc_fields	= &omap_hwmod_sysc_type2,
- + };
- + 
- + static struct omap_hwmod_class am33xx_usbotg_class = {
- + 	.name		= "usbotg",
- + 	.sysc		= &am33xx_usbhsotg_sysc,
- + };
- + 
- + static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
- + 	{ .name = "usbss-irq", .irq = 17, },
- + 	{ .name = "musb0-irq", .irq = 18, },
- + 	{ .name = "musb1-irq", .irq = 19, },
- + 	{ .irq = -1, },
- + };
- + 
- + static struct omap_hwmod_ocp_if am33xx_l3_slow__usbss = {
- + 	.master		= &am33xx_l3slow_hwmod,
- + 	.slave		= &am33xx_usbss_hwmod,
- + 	.clk		= "usbotg_ick",
- + 	.addr		= am33xx_usbss_addr_space,
- + 	.user		= OCP_USER_MPU,
- + 	.flags		= OCPIF_SWSUP_IDLE,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_usbss_slaves[] = {
- + 	&am33xx_l3_slow__usbss,
- + };
- + 
- + static struct omap_hwmod am33xx_usbss_hwmod = {
- + 	.name		= "usb_otg_hs",
- + 	.class		= &am33xx_usbotg_class,
- + 	.clkdm_name	= "l3s_clkdm",
- + 	.mpu_irqs	= am33xx_usbss_mpu_irqs,
- + 	.main_clk	= "usbotg_fck",
- + 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.slaves		= am33xx_usbss_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_usbss_slaves),
- + 	.class		= &am33xx_usbotg_class,
- + 	.flags		= (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
- + };
- + 
- + /* gfx */
- + /* Pseudo hwmod for reset control purpose only */
- + static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
- + 	.name	= "gfx",
- + };
- + 
- + static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
- + 	{ .name = "gfx", .rst_shift = 0, .st_shift = 0 },
- + };
- + 
- + static struct omap_hwmod am33xx_gfx_hwmod = {
- + 	.name		= "gfx",
- + 	.class		= &am33xx_gfx_hwmod_class,
- + 	.clkdm_name	= "gfx_l3_clkdm",
- + 	.main_clk	= "gfx_fclk",
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
- + 			.rstctrl_offs	= AM33XX_RM_GFX_RSTCTRL_OFFSET,
- + 			.rstst_offs	= AM33XX_RM_GFX_RSTST_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.rst_lines	= am33xx_gfx_resets,
- + 	.rst_lines_cnt	= ARRAY_SIZE(am33xx_gfx_resets),
- + };
- + 
- + /* PRUSS */
- + /* Pseudo hwmod for reset control purpose only */
- + static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
- + 	.name	= "pruss",
- + };
- + 
- + static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
- + 	{ .name = "pruss", .rst_shift = 1 },
- + };
- + 
- + static struct omap_hwmod am33xx_pruss_hwmod = {
- + 	.name		= "pruss",
- + 	.class		= &am33xx_pruss_hwmod_class,
- + 	.clkdm_name	= "pruss_ocp_clkdm",
- + 	.main_clk	= "pruss_uart_gclk",
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET,
- + 			.rstctrl_offs	= AM33XX_RM_PER_RSTCTRL_OFFSET,
- + 			.rstst_offs	= AM33XX_RM_PER_RSTST_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.rst_lines	= am33xx_pruss_resets,
- + 	.rst_lines_cnt	= ARRAY_SIZE(am33xx_pruss_resets),
- + };
- + 
- + /* rng */
- + static struct omap_hwmod_sysc_fields omap3_rng_sysc_fields = {
- + 	.sidle_shift	= 3,
- + 	.autoidle_shift	= 0,
- + };
- + 
- + static struct omap_hwmod_class_sysconfig am33xx_rng_sysc = {
- + 	.rev_offs	= 0x1fe0,
- + 	.sysc_offs	= 0x1fe4,
- + 	.rst_offs	= 0x1ff0,
- + 	.sysc_flags	= SYSC_HAS_AUTOIDLE,
- + 	.sysc_fields	= &omap3_rng_sysc_fields,
- + };
- + 
- + static struct omap_hwmod_class am33xx_rng_hwmod_class = {
- + 	.name		= "rng",
- + 	.sysc		= &am33xx_rng_sysc,
- + };
- + 
- + static struct omap_hwmod_irq_info am33xx_rng_irqs[] = {
- + 	{ .irq = 111 },
- + 	{ .irq = -1 }
- + };
- + 
- + struct omap_hwmod_addr_space am33xx_rng_addr_space[] = {
- + 	{
- + 		.pa_start	= 0x48310000,
- + 		.pa_end		= 0x48310000 + SZ_8K - 1,
- + 		.flags		= ADDR_TYPE_RT,
- + 	},
- + 	{ }
- + };
- + 
- + struct omap_hwmod_ocp_if am33xx_l4per__rng = {
- + 	.master		= &am33xx_l4per_hwmod,
- + 	.slave		= &am33xx_rng_hwmod,
- + 	.clk		= "rng_fck",
- + 	.addr		= am33xx_rng_addr_space,
- + 	.user		= OCP_USER_MPU,
- + };
- + 
- + static struct omap_hwmod_ocp_if *am33xx_rng_slaves[] = {
- + 	&am33xx_l4per__rng,
- + };
- + 
- + static struct omap_hwmod am33xx_rng_hwmod = {
- + 	.name		= "rng",
- + 	.class		= &am33xx_rng_hwmod_class,
- + 	.clkdm_name	= "l4ls_clkdm",
- + 	.mpu_irqs	= am33xx_rng_irqs,
- + 	.main_clk	= "rng_fck",
- + 	.prcm		= {
- + 		.omap4	= {
- + 			.clkctrl_offs	= AM33XX_CM_PER_RNG_CLKCTRL_OFFSET,
- + 			.modulemode	= MODULEMODE_SWCTRL,
- + 		},
- + 	},
- + 	.slaves		= am33xx_rng_slaves,
- + 	.slaves_cnt	= ARRAY_SIZE(am33xx_rng_slaves),
- + };
- + 
- + static __initdata struct omap_hwmod *am33xx_hwmods[] = {
- + 	/* l3 class */
- + 	&am33xx_l3_instr_hwmod,
- + 	&am33xx_l3_main_hwmod,
- + 	/* l3s class */
- + 	&am33xx_l3slow_hwmod,
- + 	/* l4hs class */
- + 	&am33xx_l4_hs_hwmod,
- + 	/* l4fw class */
- + 	&am33xx_l4fw_hwmod,
- + 	/* l4ls class */
- + 	&am33xx_l4ls_hwmod,
- + 	/* l4per class */
- + 	&am33xx_l4per_hwmod,
- + 	/* l4wkup class */
- + 	&am33xx_l4wkup_hwmod,
- + 	/* clkdiv32k class */
- + 	&am33xx_clkdiv32k_hwmod,
- + 	/* mpu class */
- + 	&am33xx_mpu_hwmod,
- + 	/* adc_tsc class */
- + 	&am33xx_adc_tsc_hwmod,
- + 	/* aes class */
- + 	&am33xx_aes0_hwmod,
- + 	/* cefuse class */
- + 	&am33xx_cefuse_hwmod,
- + 	/* control class */
- + 	&am33xx_control_hwmod,
- + 	/* dcan class */
- + 	&am33xx_dcan0_hwmod,
- + 	&am33xx_dcan1_hwmod,
- + 	/* debugss class */
- + 	&am33xx_debugss_hwmod,
- + 	/* elm class */
- + 	&am33xx_elm_hwmod,
- + 	/* emif_fw class */
- + 	&am33xx_emif_fw_hwmod,
- + 	/* epwmss class */
- + 	&am33xx_ehrpwm0_hwmod,
- + 	&am33xx_ehrpwm1_hwmod,
- + 	&am33xx_ehrpwm2_hwmod,
- + 	&am33xx_ecap0_hwmod,
- + 	&am33xx_ecap1_hwmod,
- + 	&am33xx_ecap2_hwmod,
- + 	/* gpio class */
- + 	&am33xx_gpio0_hwmod,
- + 	&am33xx_gpio1_hwmod,
- + 	&am33xx_gpio2_hwmod,
- + 	&am33xx_gpio3_hwmod,
- + 	/* gpmc class */
- + 	&am33xx_gpmc_hwmod,
- + 	/* i2c class */
- + 	&am33xx_i2c1_hwmod,
- + 	&am33xx_i2c2_hwmod,
- + 	&am33xx_i2c3_hwmod,
- + 	/* ieee5000 class */
- + 	&am33xx_ieee5000_hwmod,
- + 	/* mailbox class */
- + 	&am33xx_mailbox_hwmod,
- + 	/* mcasp class */
- + 	&am33xx_mcasp0_hwmod,
- + 	&am33xx_mcasp1_hwmod,
- + 	/* mmc class */
- + 	&am33xx_mmc0_hwmod,
- + 	&am33xx_mmc1_hwmod,
- + 	&am33xx_mmc2_hwmod,
- + 	/* ocmcram class */
- + 	&am33xx_ocmcram_hwmod,
- + 	/* ocpwp class */
- + 	&am33xx_ocpwp_hwmod,
- + 	/* rtc class */
- + 	&am33xx_rtc_hwmod,
- + 	/* sha0 class */
- + 	&am33xx_sha0_hwmod,
- + 	/* smartreflex class */
- + 	&am33xx_smartreflex0_hwmod,
- + 	&am33xx_smartreflex1_hwmod,
- + 	/* spi class */
- + 	&am33xx_spi0_hwmod,
- + 	&am33xx_spi1_hwmod,
- + 	/* spinlock class */
- + 	&am33xx_spinlock_hwmod,
- + 	/* uart class */
- + 	&am33xx_uart1_hwmod,
- + 	&am33xx_uart2_hwmod,
- + 	&am33xx_uart3_hwmod,
- + 	&am33xx_uart4_hwmod,
- + 	&am33xx_uart5_hwmod,
- + 	&am33xx_uart6_hwmod,
- + 	/* timer class */
- + 	&am33xx_timer0_hwmod,
- + 	&am33xx_timer1_hwmod,
- + 	&am33xx_timer2_hwmod,
- + 	&am33xx_timer3_hwmod,
- + 	&am33xx_timer4_hwmod,
- + 	&am33xx_timer5_hwmod,
- + 	&am33xx_timer6_hwmod,
- + 	&am33xx_timer7_hwmod,
- + 	/* wkup_m3 class */
- + 	&am33xx_wkup_m3_hwmod,
- + 	/* wd_timer class */
- + 	&am33xx_wd_timer1_hwmod,
- + 	/* usbss hwmod */
- + 	&am33xx_usbss_hwmod,
- + 	/* cpgmac0 class */
- + 	&am33xx_cpgmac0_hwmod,
- + 	/* mdio class */
- + 	&am33xx_mdio_hwmod,
- + 	/* tptc class */
- + 	&am33xx_tptc0_hwmod,
- + 	&am33xx_tptc1_hwmod,
- + 	&am33xx_tptc2_hwmod,
- + 	/* tpcc class */
- + 	&am33xx_tpcc_hwmod,
- + 	/* LCDC class */
- + 	&am33xx_lcdc_hwmod,
- + 	/* gfx/sgx */
- + 	&am33xx_gfx_hwmod,
- + 	/* pruss */
- + 	&am33xx_pruss_hwmod,
- + 	/* rng */
- + 	&am33xx_rng_hwmod,
- + 	NULL,
- + };
- + 
- + int __init am33xx_hwmod_init(void)
- + {
- + 	return omap_hwmod_register(am33xx_hwmods);
- + }
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_hwmod.c linux-3.2.1/arch/arm/mach-ckb_3352/omap_hwmod.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_hwmod.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/omap_hwmod.c	2014-05-15 13:25:13.954556406 +0900
- ***************
- *** 0 ****
- --- 1,2788 ----
- + /*
- +  * omap_hwmod implementation for OMAP2/3/4
- +  *
- +  * Copyright (C) 2009-2011 Nokia Corporation
- +  * Copyright (C) 2011 Texas Instruments, Inc.
- +  *
- +  * Paul Walmsley, Benoît Cousson, Kevin Hilman
- +  *
- +  * Created in collaboration with (alphabetical order): Thara Gopinath,
- +  * Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari Poussa, Anand
- +  * Sawant, Santosh Shilimkar, Richard Woodruff
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  *
- +  * Introduction
- +  * ------------
- +  * One way to view an OMAP SoC is as a collection of largely unrelated
- +  * IP blocks connected by interconnects.  The IP blocks include
- +  * devices such as ARM processors, audio serial interfaces, UARTs,
- +  * etc.  Some of these devices, like the DSP, are created by TI;
- +  * others, like the SGX, largely originate from external vendors.  In
- +  * TI's documentation, on-chip devices are referred to as "OMAP
- +  * modules."  Some of these IP blocks are identical across several
- +  * OMAP versions.  Others are revised frequently.
- +  *
- +  * These OMAP modules are tied together by various interconnects.
- +  * Most of the address and data flow between modules is via OCP-based
- +  * interconnects such as the L3 and L4 buses; but there are other
- +  * interconnects that distribute the hardware clock tree, handle idle
- +  * and reset signaling, supply power, and connect the modules to
- +  * various pads or balls on the OMAP package.
- +  *
- +  * OMAP hwmod provides a consistent way to describe the on-chip
- +  * hardware blocks and their integration into the rest of the chip.
- +  * This description can be automatically generated from the TI
- +  * hardware database.  OMAP hwmod provides a standard, consistent API
- +  * to reset, enable, idle, and disable these hardware blocks.  And
- +  * hwmod provides a way for other core code, such as the Linux device
- +  * code or the OMAP power management and address space mapping code,
- +  * to query the hardware database.
- +  *
- +  * Using hwmod
- +  * -----------
- +  * Drivers won't call hwmod functions directly.  That is done by the
- +  * omap_device code, and in rare occasions, by custom integration code
- +  * in arch/arm/ *omap*.  The omap_device code includes functions to
- +  * build a struct platform_device using omap_hwmod data, and that is
- +  * currently how hwmod data is communicated to drivers and to the
- +  * Linux driver model.  Most drivers will call omap_hwmod functions only
- +  * indirectly, via pm_runtime*() functions.
- +  *
- +  * From a layering perspective, here is where the OMAP hwmod code
- +  * fits into the kernel software stack:
- +  *
- +  *            +-------------------------------+
- +  *            |      Device driver code       |
- +  *            |      (e.g., drivers/)         |
- +  *            +-------------------------------+
- +  *            |      Linux driver model       |
- +  *            |     (platform_device /        |
- +  *            |  platform_driver data/code)   |
- +  *            +-------------------------------+
- +  *            | OMAP core-driver integration  |
- +  *            |(arch/arm/mach-omap2/devices.c)|
- +  *            +-------------------------------+
- +  *            |      omap_device code         |
- +  *            | (../plat-omap/omap_device.c)  |
- +  *            +-------------------------------+
- +  *   ---->    |    omap_hwmod code/data       |    <-----
- +  *            | (../mach-omap2/omap_hwmod*)   |
- +  *            +-------------------------------+
- +  *            | OMAP clock/PRCM/register fns  |
- +  *            | (__raw_{read,write}l, clk*)   |
- +  *            +-------------------------------+
- +  *
- +  * Device drivers should not contain any OMAP-specific code or data in
- +  * them.  They should only contain code to operate the IP block that
- +  * the driver is responsible for.  This is because these IP blocks can
- +  * also appear in other SoCs, either from TI (such as DaVinci) or from
- +  * other manufacturers; and drivers should be reusable across other
- +  * platforms.
- +  *
- +  * The OMAP hwmod code also will attempt to reset and idle all on-chip
- +  * devices upon boot.  The goal here is for the kernel to be
- +  * completely self-reliant and independent from bootloaders.  This is
- +  * to ensure a repeatable configuration, both to ensure consistent
- +  * runtime behavior, and to make it easier for others to reproduce
- +  * bugs.
- +  *
- +  * OMAP module activity states
- +  * ---------------------------
- +  * The hwmod code considers modules to be in one of several activity
- +  * states.  IP blocks start out in an UNKNOWN state, then once they
- +  * are registered via the hwmod code, proceed to the REGISTERED state.
- +  * Once their clock names are resolved to clock pointers, the module
- +  * enters the CLKS_INITED state; and finally, once the module has been
- +  * reset and the integration registers programmed, the INITIALIZED state
- +  * is entered.  The hwmod code will then place the module into either
- +  * the IDLE state to save power, or in the case of a critical system
- +  * module, the ENABLED state.
- +  *
- +  * OMAP core integration code can then call omap_hwmod*() functions
- +  * directly to move the module between the IDLE, ENABLED, and DISABLED
- +  * states, as needed.  This is done during both the PM idle loop, and
- +  * in the OMAP core integration code's implementation of the PM runtime
- +  * functions.
- +  *
- +  * References
- +  * ----------
- +  * This is a partial list.
- +  * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064)
- +  * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090)
- +  * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108)
- +  * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140)
- +  * - Open Core Protocol Specification 2.2
- +  *
- +  * To do:
- +  * - handle IO mapping
- +  * - bus throughput & module latency measurement code
- +  *
- +  * XXX add tests at the beginning of each function to ensure the hwmod is
- +  * in the appropriate state
- +  * XXX error return values should be checked to ensure that they are
- +  * appropriate
- +  */
- + #undef DEBUG
- + 
- + #include <linux/kernel.h>
- + #include <linux/errno.h>
- + #include <linux/io.h>
- + #include <linux/clk.h>
- + #include <linux/delay.h>
- + #include <linux/err.h>
- + #include <linux/list.h>
- + #include <linux/mutex.h>
- + #include <linux/spinlock.h>
- + #include <linux/slab.h>
- + 
- + #include "common.h"
- + #include <plat/cpu.h>
- + #include "clockdomain.h"
- + #include "powerdomain.h"
- + #include <plat/clock.h>
- + #include <plat/omap_hwmod.h>
- + #include <plat/prcm.h>
- + 
- + //#include "cm2xxx_3xxx.h"
- + #include "cminst44xx.h"
- + #include "prm2xxx_3xxx.h"
- + #include "prm33xx.h"
- + #include "prminst44xx.h"
- + #include "mux.h"
- + 
- + /* Maximum microseconds to wait for OMAP module to softreset */
- + #define MAX_MODULE_SOFTRESET_WAIT	10000
- + 
- + /* Name of the OMAP hwmod for the MPU */
- + #define MPU_INITIATOR_NAME		"mpu"
- + 
- + /* omap_hwmod_list contains all registered struct omap_hwmods */
- + static LIST_HEAD(omap_hwmod_list);
- + 
- + /* mpu_oh: used to add/remove MPU initiator from sleepdep list */
- + static struct omap_hwmod *mpu_oh;
- + 
- + 
- + /* Private functions */
- + 
- + /**
- +  * _update_sysc_cache - return the module OCP_SYSCONFIG register, keep copy
- +  * @oh: struct omap_hwmod *
- +  *
- +  * Load the current value of the hwmod OCP_SYSCONFIG register into the
- +  * struct omap_hwmod for later use.  Returns -EINVAL if the hwmod has no
- +  * OCP_SYSCONFIG register or 0 upon success.
- +  */
- + static int _update_sysc_cache(struct omap_hwmod *oh)
- + {
- + 	if (!oh->class->sysc) {
- + 		WARN(1, "omap_hwmod: %s: cannot read OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name);
- + 		return -EINVAL;
- + 	}
- + 
- + 	/* XXX ensure module interface clock is up */
- + 
- + 	oh->_sysc_cache = omap_hwmod_read(oh, oh->class->sysc->sysc_offs);
- + 
- + 	if (!(oh->class->sysc->sysc_flags & SYSC_NO_CACHE))
- + 		oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED;
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * _write_sysconfig - write a value to the module's OCP_SYSCONFIG register
- +  * @v: OCP_SYSCONFIG value to write
- +  * @oh: struct omap_hwmod *
- +  *
- +  * Write @v into the module class' OCP_SYSCONFIG register, if it has
- +  * one.  No return value.
- +  */
- + static void _write_sysconfig(u32 v, struct omap_hwmod *oh)
- + {
- + 	if (!oh->class->sysc) {
- + 		WARN(1, "omap_hwmod: %s: cannot write OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name);
- + 		return;
- + 	}
- + 
- + 	/* XXX ensure module interface clock is up */
- + 
- + 	/* Module might have lost context, always update cache and register */
- + 	oh->_sysc_cache = v;
- + 	omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs);
- + }
- + 
- + /**
- +  * _set_master_standbymode: set the OCP_SYSCONFIG MIDLEMODE field in @v
- +  * @oh: struct omap_hwmod *
- +  * @standbymode: MIDLEMODE field bits
- +  * @v: pointer to register contents to modify
- +  *
- +  * Update the master standby mode bits in @v to be @standbymode for
- +  * the @oh hwmod.  Does not write to the hardware.  Returns -EINVAL
- +  * upon error or 0 upon success.
- +  */
- + static int _set_master_standbymode(struct omap_hwmod *oh, u8 standbymode,
- + 				   u32 *v)
- + {
- + 	u32 mstandby_mask;
- + 	u8 mstandby_shift;
- + 
- + 	if (!oh->class->sysc ||
- + 	    !(oh->class->sysc->sysc_flags & SYSC_HAS_MIDLEMODE))
- + 		return -EINVAL;
- + 
- + 	if (!oh->class->sysc->sysc_fields) {
- + 		WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
- + 		return -EINVAL;
- + 	}
- + 
- + 	mstandby_shift = oh->class->sysc->sysc_fields->midle_shift;
- + 	mstandby_mask = (0x3 << mstandby_shift);
- + 
- + 	*v &= ~mstandby_mask;
- + 	*v |= __ffs(standbymode) << mstandby_shift;
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * _set_slave_idlemode: set the OCP_SYSCONFIG SIDLEMODE field in @v
- +  * @oh: struct omap_hwmod *
- +  * @idlemode: SIDLEMODE field bits
- +  * @v: pointer to register contents to modify
- +  *
- +  * Update the slave idle mode bits in @v to be @idlemode for the @oh
- +  * hwmod.  Does not write to the hardware.  Returns -EINVAL upon error
- +  * or 0 upon success.
- +  */
- + static int _set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode, u32 *v)
- + {
- + 	u32 sidle_mask;
- + 	u8 sidle_shift;
- + 
- + 	if (!oh->class->sysc ||
- + 	    !(oh->class->sysc->sysc_flags & SYSC_HAS_SIDLEMODE))
- + 		return -EINVAL;
- + 
- + 	if (!oh->class->sysc->sysc_fields) {
- + 		WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
- + 		return -EINVAL;
- + 	}
- + 
- + 	sidle_shift = oh->class->sysc->sysc_fields->sidle_shift;
- + 	sidle_mask = (0x3 << sidle_shift);
- + 
- + 	*v &= ~sidle_mask;
- + 	*v |= __ffs(idlemode) << sidle_shift;
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * _set_clockactivity: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v
- +  * @oh: struct omap_hwmod *
- +  * @clockact: CLOCKACTIVITY field bits
- +  * @v: pointer to register contents to modify
- +  *
- +  * Update the clockactivity mode bits in @v to be @clockact for the
- +  * @oh hwmod.  Used for additional powersaving on some modules.  Does
- +  * not write to the hardware.  Returns -EINVAL upon error or 0 upon
- +  * success.
- +  */
- + static int _set_clockactivity(struct omap_hwmod *oh, u8 clockact, u32 *v)
- + {
- + 	u32 clkact_mask;
- + 	u8  clkact_shift;
- + 
- + 	if (!oh->class->sysc ||
- + 	    !(oh->class->sysc->sysc_flags & SYSC_HAS_CLOCKACTIVITY))
- + 		return -EINVAL;
- + 
- + 	if (!oh->class->sysc->sysc_fields) {
- + 		WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
- + 		return -EINVAL;
- + 	}
- + 
- + 	clkact_shift = oh->class->sysc->sysc_fields->clkact_shift;
- + 	clkact_mask = (0x3 << clkact_shift);
- + 
- + 	*v &= ~clkact_mask;
- + 	*v |= clockact << clkact_shift;
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * _set_softreset: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v
- +  * @oh: struct omap_hwmod *
- +  * @v: pointer to register contents to modify
- +  *
- +  * Set the SOFTRESET bit in @v for hwmod @oh.  Returns -EINVAL upon
- +  * error or 0 upon success.
- +  */
- + static int _set_softreset(struct omap_hwmod *oh, u32 *v)
- + {
- + 	u32 softrst_mask;
- + 
- + 	if (!oh->class->sysc ||
- + 	    !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET))
- + 		return -EINVAL;
- + 
- + 	if (!oh->class->sysc->sysc_fields) {
- + 		WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
- + 		return -EINVAL;
- + 	}
- + 
- + 	softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift);
- + 
- + 	*v |= softrst_mask;
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * _set_module_autoidle: set the OCP_SYSCONFIG AUTOIDLE field in @v
- +  * @oh: struct omap_hwmod *
- +  * @autoidle: desired AUTOIDLE bitfield value (0 or 1)
- +  * @v: pointer to register contents to modify
- +  *
- +  * Update the module autoidle bit in @v to be @autoidle for the @oh
- +  * hwmod.  The autoidle bit controls whether the module can gate
- +  * internal clocks automatically when it isn't doing anything; the
- +  * exact function of this bit varies on a per-module basis.  This
- +  * function does not write to the hardware.  Returns -EINVAL upon
- +  * error or 0 upon success.
- +  */
- + static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle,
- + 				u32 *v)
- + {
- + 	u32 autoidle_mask;
- + 	u8 autoidle_shift;
- + 
- + 	if (!oh->class->sysc ||
- + 	    !(oh->class->sysc->sysc_flags & SYSC_HAS_AUTOIDLE))
- + 		return -EINVAL;
- + 
- + 	if (!oh->class->sysc->sysc_fields) {
- + 		WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
- + 		return -EINVAL;
- + 	}
- + 
- + 	autoidle_shift = oh->class->sysc->sysc_fields->autoidle_shift;
- + 	autoidle_mask = (0x1 << autoidle_shift);
- + 
- + 	*v &= ~autoidle_mask;
- + 	*v |= autoidle << autoidle_shift;
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * _set_idle_ioring_wakeup - enable/disable IO pad wakeup on hwmod idle for mux
- +  * @oh: struct omap_hwmod *
- +  * @set_wake: bool value indicating to set (true) or clear (false) wakeup enable
- +  *
- +  * Set or clear the I/O pad wakeup flag in the mux entries for the
- +  * hwmod @oh.  This function changes the @oh->mux->pads_dynamic array
- +  * in memory.  If the hwmod is currently idled, and the new idle
- +  * values don't match the previous ones, this function will also
- +  * update the SCM PADCTRL registers.  Otherwise, if the hwmod is not
- +  * currently idled, this function won't touch the hardware: the new
- +  * mux settings are written to the SCM PADCTRL registers when the
- +  * hwmod is idled.  No return value.
- +  */
- + static void _set_idle_ioring_wakeup(struct omap_hwmod *oh, bool set_wake)
- + {
- + 	struct omap_device_pad *pad;
- + 	bool change = false;
- + 	u16 prev_idle;
- + 	int j;
- + 
- + 	if (!oh->mux || !oh->mux->enabled)
- + 		return;
- + 
- + 	for (j = 0; j < oh->mux->nr_pads_dynamic; j++) {
- + 		pad = oh->mux->pads_dynamic[j];
- + 
- + 		if (!(pad->flags & OMAP_DEVICE_PAD_WAKEUP))
- + 			continue;
- + 
- + 		prev_idle = pad->idle;
- + 
- + 		if (set_wake)
- + 			pad->idle |= OMAP_WAKEUP_EN;
- + 		else
- + 			pad->idle &= ~OMAP_WAKEUP_EN;
- + 
- + 		if (prev_idle != pad->idle)
- + 			change = true;
- + 	}
- + 
- + 	if (change && oh->_state == _HWMOD_STATE_IDLE)
- + 		omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE);
- + }
- + 
- + /**
- +  * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware
- +  * @oh: struct omap_hwmod *
- +  *
- +  * Allow the hardware module @oh to send wakeups.  Returns -EINVAL
- +  * upon error or 0 upon success.
- +  */
- + static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
- + {
- + 	if (!oh->class->sysc ||
- + 	    !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) ||
- + 	      (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) ||
- + 	      (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)))
- + 		return -EINVAL;
- + 
- + 	if (!oh->class->sysc->sysc_fields) {
- + 		WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
- + 		return -EINVAL;
- + 	}
- + 
- + 	if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)
- + 		*v |= 0x1 << oh->class->sysc->sysc_fields->enwkup_shift;
- + 
- + 	if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
- + 		_set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
- + 	if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
- + 		_set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
- + 
- + 	/* XXX test pwrdm_get_wken for this hwmod's subsystem */
- + 
- + 	oh->_int_flags |= _HWMOD_WAKEUP_ENABLED;
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * _disable_wakeup: clear OCP_SYSCONFIG.ENAWAKEUP bit in the hardware
- +  * @oh: struct omap_hwmod *
- +  *
- +  * Prevent the hardware module @oh to send wakeups.  Returns -EINVAL
- +  * upon error or 0 upon success.
- +  */
- + static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
- + {
- + 	if (!oh->class->sysc ||
- + 	    !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) ||
- + 	      (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) ||
- + 	      (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)))
- + 		return -EINVAL;
- + 
- + 	if (!oh->class->sysc->sysc_fields) {
- + 		WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
- + 		return -EINVAL;
- + 	}
- + 
- + 	if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)
- + 		*v &= ~(0x1 << oh->class->sysc->sysc_fields->enwkup_shift);
- + 
- + 	if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
- + 		_set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v);
- + 	if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
- + 		_set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
- + 
- + 	/* XXX test pwrdm_get_wken for this hwmod's subsystem */
- + 
- + 	oh->_int_flags &= ~_HWMOD_WAKEUP_ENABLED;
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * _add_initiator_dep: prevent @oh from smart-idling while @init_oh is active
- +  * @oh: struct omap_hwmod *
- +  *
- +  * Prevent the hardware module @oh from entering idle while the
- +  * hardare module initiator @init_oh is active.  Useful when a module
- +  * will be accessed by a particular initiator (e.g., if a module will
- +  * be accessed by the IVA, there should be a sleepdep between the IVA
- +  * initiator and the module).  Only applies to modules in smart-idle
- +  * mode.  If the clockdomain is marked as not needing autodeps, return
- +  * 0 without doing anything.  Otherwise, returns -EINVAL upon error or
- +  * passes along clkdm_add_sleepdep() value upon success.
- +  */
- + static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
- + {
- + 	if (!oh->_clk)
- + 		return -EINVAL;
- + 
- + 	if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS)
- + 		return 0;
- + 
- + 	return clkdm_add_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm);
- + }
- + 
- + /**
- +  * _del_initiator_dep: allow @oh to smart-idle even if @init_oh is active
- +  * @oh: struct omap_hwmod *
- +  *
- +  * Allow the hardware module @oh to enter idle while the hardare
- +  * module initiator @init_oh is active.  Useful when a module will not
- +  * be accessed by a particular initiator (e.g., if a module will not
- +  * be accessed by the IVA, there should be no sleepdep between the IVA
- +  * initiator and the module).  Only applies to modules in smart-idle
- +  * mode.  If the clockdomain is marked as not needing autodeps, return
- +  * 0 without doing anything.  Returns -EINVAL upon error or passes
- +  * along clkdm_del_sleepdep() value upon success.
- +  */
- + static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
- + {
- + 	if (!oh->_clk)
- + 		return -EINVAL;
- + 
- + 	if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS)
- + 		return 0;
- + 
- + 	return clkdm_del_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm);
- + }
- + 
- + /**
- +  * _init_main_clk - get a struct clk * for the the hwmod's main functional clk
- +  * @oh: struct omap_hwmod *
- +  *
- +  * Called from _init_clocks().  Populates the @oh _clk (main
- +  * functional clock pointer) if a main_clk is present.  Returns 0 on
- +  * success or -EINVAL on error.
- +  */
- + static int _init_main_clk(struct omap_hwmod *oh)
- + {
- + 	int ret = 0;
- + 
- + 	if (!oh->main_clk)
- + 		return 0;
- + 
- + 	oh->_clk = omap_clk_get_by_name(oh->main_clk);
- + 	if (!oh->_clk) {
- + 		pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n",
- + 			   oh->name, oh->main_clk);
- + 		return -EINVAL;
- + 	}
- + 
- + 	if (!oh->_clk->clkdm)
- + 		pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n",
- + 			   oh->main_clk, oh->_clk->name);
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * _init_interface_clks - get a struct clk * for the the hwmod's interface clks
- +  * @oh: struct omap_hwmod *
- +  *
- +  * Called from _init_clocks().  Populates the @oh OCP slave interface
- +  * clock pointers.  Returns 0 on success or -EINVAL on error.
- +  */
- + static int _init_interface_clks(struct omap_hwmod *oh)
- + {
- + 	struct clk *c;
- + 	int i;
- + 	int ret = 0;
- + 
- + 	if (oh->slaves_cnt == 0)
- + 		return 0;
- + 
- + 	for (i = 0; i < oh->slaves_cnt; i++) {
- + 		struct omap_hwmod_ocp_if *os = oh->slaves[i];
- + 
- + 		if (!os->clk)
- + 			continue;
- + 
- + 		c = omap_clk_get_by_name(os->clk);
- + 		if (!c) {
- + 			pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n",
- + 				   oh->name, os->clk);
- + 			ret = -EINVAL;
- + 		}
- + 		os->_clk = c;
- + 	}
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * _init_opt_clk - get a struct clk * for the the hwmod's optional clocks
- +  * @oh: struct omap_hwmod *
- +  *
- +  * Called from _init_clocks().  Populates the @oh omap_hwmod_opt_clk
- +  * clock pointers.  Returns 0 on success or -EINVAL on error.
- +  */
- + static int _init_opt_clks(struct omap_hwmod *oh)
- + {
- + 	struct omap_hwmod_opt_clk *oc;
- + 	struct clk *c;
- + 	int i;
- + 	int ret = 0;
- + 
- + 	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) {
- + 		c = omap_clk_get_by_name(oc->clk);
- + 		if (!c) {
- + 			pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n",
- + 				   oh->name, oc->clk);
- + 			ret = -EINVAL;
- + 		}
- + 		oc->_clk = c;
- + 	}
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * _enable_clocks - enable hwmod main clock and interface clocks
- +  * @oh: struct omap_hwmod *
- +  *
- +  * Enables all clocks necessary for register reads and writes to succeed
- +  * on the hwmod @oh.  Returns 0.
- +  */
- + static int _enable_clocks(struct omap_hwmod *oh)
- + {
- + 	int i;
- + 
- + 	pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name);
- + 
- + 	if (oh->_clk)
- + 		clk_enable(oh->_clk);
- + 
- + 	if (oh->slaves_cnt > 0) {
- + 		for (i = 0; i < oh->slaves_cnt; i++) {
- + 			struct omap_hwmod_ocp_if *os = oh->slaves[i];
- + 			struct clk *c = os->_clk;
- + 
- + 			if (c && (os->flags & OCPIF_SWSUP_IDLE))
- + 				clk_enable(c);
- + 		}
- + 	}
- + 
- + 	/* The opt clocks are controlled by the device driver. */
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * _disable_clocks - disable hwmod main clock and interface clocks
- +  * @oh: struct omap_hwmod *
- +  *
- +  * Disables the hwmod @oh main functional and interface clocks.  Returns 0.
- +  */
- + static int _disable_clocks(struct omap_hwmod *oh)
- + {
- + 	int i;
- + 
- + 	pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name);
- + 
- + 	if (oh->_clk)
- + 		clk_disable(oh->_clk);
- + 
- + 	if (oh->slaves_cnt > 0) {
- + 		for (i = 0; i < oh->slaves_cnt; i++) {
- + 			struct omap_hwmod_ocp_if *os = oh->slaves[i];
- + 			struct clk *c = os->_clk;
- + 
- + 			if (c && (os->flags & OCPIF_SWSUP_IDLE))
- + 				clk_disable(c);
- + 		}
- + 	}
- + 
- + 	/* The opt clocks are controlled by the device driver. */
- + 
- + 	return 0;
- + }
- + 
- + static void _enable_optional_clocks(struct omap_hwmod *oh)
- + {
- + 	struct omap_hwmod_opt_clk *oc;
- + 	int i;
- + 
- + 	pr_debug("omap_hwmod: %s: enabling optional clocks\n", oh->name);
- + 
- + 	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
- + 		if (oc->_clk) {
- + 			pr_debug("omap_hwmod: enable %s:%s\n", oc->role,
- + 				 oc->_clk->name);
- + 			clk_enable(oc->_clk);
- + 		}
- + }
- + 
- + static void _disable_optional_clocks(struct omap_hwmod *oh)
- + {
- + 	struct omap_hwmod_opt_clk *oc;
- + 	int i;
- + 
- + 	pr_debug("omap_hwmod: %s: disabling optional clocks\n", oh->name);
- + 
- + 	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
- + 		if (oc->_clk) {
- + 			pr_debug("omap_hwmod: disable %s:%s\n", oc->role,
- + 				 oc->_clk->name);
- + 			clk_disable(oc->_clk);
- + 		}
- + }
- + 
- + /**
- +  * _enable_module - enable CLKCTRL modulemode on OMAP4
- +  * @oh: struct omap_hwmod *
- +  *
- +  * Enables the PRCM module mode related to the hwmod @oh.
- +  * No return value.
- +  */
- + static void _enable_module(struct omap_hwmod *oh)
- + {
- + 	if (!oh->clkdm || !oh->prcm.omap4.modulemode)
- + 		return;
- + 
- + 	pr_debug("omap_hwmod: %s: _enable_module: %d\n",
- + 			oh->name, oh->prcm.omap4.modulemode);
- + 
- + 	omap4_cminst_module_enable(oh->prcm.omap4.modulemode,
- + 			oh->clkdm->prcm_partition,
- + 			oh->clkdm->cm_inst,
- + 			oh->clkdm->clkdm_offs,
- + 			oh->prcm.omap4.clkctrl_offs);
- + }
- + 
- + /**
- +  * _omap4_wait_target_disable - wait for a module to be disabled on OMAP4
- +  * @oh: struct omap_hwmod *
- +  *
- +  * Wait for a module @oh to enter slave idle.  Returns 0 if the module
- +  * does not have an IDLEST bit or if the module successfully enters
- +  * slave idle; otherwise, pass along the return value of the
- +  * appropriate *_cm*_wait_module_idle() function.
- +  */
- + static int _omap4_wait_target_disable(struct omap_hwmod *oh)
- + {
- + 	if (!oh)
- + 		return -EINVAL;
- + 
- + 	if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
- + 		return 0;
- + 
- + 	if (oh->flags & HWMOD_NO_IDLEST)
- + 		return 0;
- + 
- + 	return omap4_cminst_wait_module_idle(oh->clkdm->prcm_partition,
- + 					     oh->clkdm->cm_inst,
- + 					     oh->clkdm->clkdm_offs,
- + 					     oh->prcm.omap4.clkctrl_offs);
- + }
- + 
- + /**
- +  * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4
- +  * @oh: struct omap_hwmod *
- +  *
- +  * Disable the PRCM module mode related to the hwmod @oh.
- +  * Return EINVAL if the modulemode is not supported and 0 in case of success.
- +  */
- + static int _omap4_disable_module(struct omap_hwmod *oh)
- + {
- + 	int v;
- + 
- + 	if (!oh->clkdm || !oh->prcm.omap4.modulemode)
- + 		return -EINVAL;
- + 
- + 	pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__);
- + 
- + 	omap4_cminst_module_disable(oh->clkdm->prcm_partition,
- + 			oh->clkdm->cm_inst,
- + 			oh->clkdm->clkdm_offs,
- + 			oh->prcm.omap4.clkctrl_offs);
- + 
- + 	v = _omap4_wait_target_disable(oh);
- + 	if (v)
- + 		pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
- + 				oh->name);
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh
- +  * @oh: struct omap_hwmod *oh
- +  *
- +  * Count and return the number of MPU IRQs associated with the hwmod
- +  * @oh.  Used to allocate struct resource data.  Returns 0 if @oh is
- +  * NULL.
- +  */
- + static int _count_mpu_irqs(struct omap_hwmod *oh)
- + {
- + 	struct omap_hwmod_irq_info *ohii;
- + 	int i = 0;
- + 
- + 	if (!oh || !oh->mpu_irqs)
- + 		return 0;
- + 
- + 	do {
- + 		ohii = &oh->mpu_irqs[i++];
- + 	} while (ohii->irq != -1);
- + 
- + 	return i-1;
- + }
- + 
- + /**
- +  * _count_sdma_reqs - count the number of SDMA request lines associated with @oh
- +  * @oh: struct omap_hwmod *oh
- +  *
- +  * Count and return the number of SDMA request lines associated with
- +  * the hwmod @oh.  Used to allocate struct resource data.  Returns 0
- +  * if @oh is NULL.
- +  */
- + static int _count_sdma_reqs(struct omap_hwmod *oh)
- + {
- + 	struct omap_hwmod_dma_info *ohdi;
- + 	int i = 0;
- + 
- + 	if (!oh || !oh->sdma_reqs)
- + 		return 0;
- + 
- + 	do {
- + 		ohdi = &oh->sdma_reqs[i++];
- + 	} while (ohdi->dma_req != -1);
- + 
- + 	return i-1;
- + }
- + 
- + /**
- +  * _count_ocp_if_addr_spaces - count the number of address space entries for @oh
- +  * @oh: struct omap_hwmod *oh
- +  *
- +  * Count and return the number of address space ranges associated with
- +  * the hwmod @oh.  Used to allocate struct resource data.  Returns 0
- +  * if @oh is NULL.
- +  */
- + static int _count_ocp_if_addr_spaces(struct omap_hwmod_ocp_if *os)
- + {
- + 	struct omap_hwmod_addr_space *mem;
- + 	int i = 0;
- + 
- + 	if (!os || !os->addr)
- + 		return 0;
- + 
- + 	do {
- + 		mem = &os->addr[i++];
- + 	} while (mem->pa_start != mem->pa_end);
- + 
- + 	return i-1;
- + }
- + 
- + /**
- +  * _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use
- +  * @oh: struct omap_hwmod *
- +  *
- +  * Returns the array index of the OCP slave port that the MPU
- +  * addresses the device on, or -EINVAL upon error or not found.
- +  */
- + static int __init _find_mpu_port_index(struct omap_hwmod *oh)
- + {
- + 	int i;
- + 	int found = 0;
- + 
- + 	if (!oh || oh->slaves_cnt == 0)
- + 		return -EINVAL;
- + 
- + 	for (i = 0; i < oh->slaves_cnt; i++) {
- + 		struct omap_hwmod_ocp_if *os = oh->slaves[i];
- + 
- + 		if (os->user & OCP_USER_MPU) {
- + 			found = 1;
- + 			break;
- + 		}
- + 	}
- + 
- + 	if (found)
- + 		pr_debug("omap_hwmod: %s: MPU OCP slave port ID  %d\n",
- + 			 oh->name, i);
- + 	else
- + 		pr_debug("omap_hwmod: %s: no MPU OCP slave port found\n",
- + 			 oh->name);
- + 
- + 	return (found) ? i : -EINVAL;
- + }
- + 
- + /**
- +  * _find_mpu_rt_base - find hwmod register target base addr accessible by MPU
- +  * @oh: struct omap_hwmod *
- +  *
- +  * Return the virtual address of the base of the register target of
- +  * device @oh, or NULL on error.
- +  */
- + static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
- + {
- + 	struct omap_hwmod_ocp_if *os;
- + 	struct omap_hwmod_addr_space *mem;
- + 	int i = 0, found = 0;
- + 	void __iomem *va_start;
- + 
- + 	if (!oh || oh->slaves_cnt == 0)
- + 		return NULL;
- + 
- + 	os = oh->slaves[index];
- + 
- + 	if (!os->addr)
- + 		return NULL;
- + 
- + 	do {
- + 		mem = &os->addr[i++];
- + 		if (mem->flags & ADDR_TYPE_RT)
- + 			found = 1;
- + 	} while (!found && mem->pa_start != mem->pa_end);
- + 
- + 	if (found) {
- + 		va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
- + 		if (!va_start) {
- + 			pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name);
- + 			return NULL;
- + 		}
- + 		pr_debug("omap_hwmod: %s: MPU register target at va %p\n",
- + 			 oh->name, va_start);
- + 	} else {
- + 		pr_debug("omap_hwmod: %s: no MPU register target found\n",
- + 			 oh->name);
- + 	}
- + 
- + 	return (found) ? va_start : NULL;
- + }
- + 
- + /**
- +  * _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG
- +  * @oh: struct omap_hwmod *
- +  *
- +  * If module is marked as SWSUP_SIDLE, force the module out of slave
- +  * idle; otherwise, configure it for smart-idle.  If module is marked
- +  * as SWSUP_MSUSPEND, force the module out of master standby;
- +  * otherwise, configure it for smart-standby.  No return value.
- +  */
- + static void _enable_sysc(struct omap_hwmod *oh)
- + {
- + 	u8 idlemode, sf;
- + 	u32 v;
- + 
- + 	if (!oh->class->sysc)
- + 		return;
- + 
- + 	v = oh->_sysc_cache;
- + 	sf = oh->class->sysc->sysc_flags;
- + 
- + 	if (sf & SYSC_HAS_SIDLEMODE) {
- + 		idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ?
- + 			HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART;
- + 		_set_slave_idlemode(oh, idlemode, &v);
- + 	}
- + 
- + 	if (sf & SYSC_HAS_MIDLEMODE) {
- + 		if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
- + 			idlemode = HWMOD_IDLEMODE_NO;
- + 		} else {
- + 			if (sf & SYSC_HAS_ENAWAKEUP)
- + 				_enable_wakeup(oh, &v);
- + 			if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
- + 				idlemode = HWMOD_IDLEMODE_SMART_WKUP;
- + 			else
- + 				idlemode = HWMOD_IDLEMODE_SMART;
- + 		}
- + 		_set_master_standbymode(oh, idlemode, &v);
- + 	}
- + 
- + 	/*
- + 	 * XXX The clock framework should handle this, by
- + 	 * calling into this code.  But this must wait until the
- + 	 * clock structures are tagged with omap_hwmod entries
- + 	 */
- + 	if ((oh->flags & HWMOD_SET_DEFAULT_CLOCKACT) &&
- + 	    (sf & SYSC_HAS_CLOCKACTIVITY))
- + 		_set_clockactivity(oh, oh->class->sysc->clockact, &v);
- + 
- + 	/* If slave is in SMARTIDLE, also enable wakeup */
- + 	if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE))
- + 		_enable_wakeup(oh, &v);
- + 
- + 	_write_sysconfig(v, oh);
- + 
- + 	/*
- + 	 * Set the autoidle bit only after setting the smartidle bit
- + 	 * Setting this will not have any impact on the other modules.
- + 	 */
- + 	if (sf & SYSC_HAS_AUTOIDLE) {
- + 		idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ?
- + 			0 : 1;
- + 		_set_module_autoidle(oh, idlemode, &v);
- + 		_write_sysconfig(v, oh);
- + 	}
- + }
- + 
- + /**
- +  * _idle_sysc - try to put a module into idle via OCP_SYSCONFIG
- +  * @oh: struct omap_hwmod *
- +  *
- +  * If module is marked as SWSUP_SIDLE, force the module into slave
- +  * idle; otherwise, configure it for smart-idle.  If module is marked
- +  * as SWSUP_MSUSPEND, force the module into master standby; otherwise,
- +  * configure it for smart-standby.  No return value.
- +  */
- + static void _idle_sysc(struct omap_hwmod *oh)
- + {
- + 	u8 idlemode, sf;
- + 	u32 v;
- + 
- + 	if (!oh->class->sysc)
- + 		return;
- + 
- + 	v = oh->_sysc_cache;
- + 	sf = oh->class->sysc->sysc_flags;
- + 
- + 	if (sf & SYSC_HAS_SIDLEMODE) {
- + 		idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ?
- + 			HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART;
- + 		_set_slave_idlemode(oh, idlemode, &v);
- + 	}
- + 
- + 	if (sf & SYSC_HAS_MIDLEMODE) {
- + 		if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
- + 			idlemode = HWMOD_IDLEMODE_FORCE;
- + 		} else {
- + 			if (sf & SYSC_HAS_ENAWAKEUP)
- + 				_enable_wakeup(oh, &v);
- + 			if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
- + 				idlemode = HWMOD_IDLEMODE_SMART_WKUP;
- + 			else
- + 				idlemode = HWMOD_IDLEMODE_SMART;
- + 		}
- + 		_set_master_standbymode(oh, idlemode, &v);
- + 	}
- + 
- + 	/* If slave is in SMARTIDLE, also enable wakeup */
- + 	if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE))
- + 		_enable_wakeup(oh, &v);
- + 
- + 	_write_sysconfig(v, oh);
- + }
- + 
- + /**
- +  * _shutdown_sysc - force a module into idle via OCP_SYSCONFIG
- +  * @oh: struct omap_hwmod *
- +  *
- +  * Force the module into slave idle and master suspend. No return
- +  * value.
- +  */
- + static void _shutdown_sysc(struct omap_hwmod *oh)
- + {
- + 	u32 v;
- + 	u8 sf;
- + 
- + 	if (!oh->class->sysc)
- + 		return;
- + 
- + 	v = oh->_sysc_cache;
- + 	sf = oh->class->sysc->sysc_flags;
- + 
- + 	if (sf & SYSC_HAS_SIDLEMODE)
- + 		_set_slave_idlemode(oh, HWMOD_IDLEMODE_FORCE, &v);
- + 
- + 	if (sf & SYSC_HAS_MIDLEMODE)
- + 		_set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v);
- + 
- + 	if (sf & SYSC_HAS_AUTOIDLE)
- + 		_set_module_autoidle(oh, 1, &v);
- + 
- + 	_write_sysconfig(v, oh);
- + }
- + 
- + /**
- +  * _lookup - find an omap_hwmod by name
- +  * @name: find an omap_hwmod by name
- +  *
- +  * Return a pointer to an omap_hwmod by name, or NULL if not found.
- +  */
- + static struct omap_hwmod *_lookup(const char *name)
- + {
- + 	struct omap_hwmod *oh, *temp_oh;
- + 
- + 	oh = NULL;
- + 
- + 	list_for_each_entry(temp_oh, &omap_hwmod_list, node) {
- + 		if (!strcmp(name, temp_oh->name)) {
- + 			oh = temp_oh;
- + 			break;
- + 		}
- + 	}
- + 
- + 	return oh;
- + }
- + /**
- +  * _init_clkdm - look up a clockdomain name, store pointer in omap_hwmod
- +  * @oh: struct omap_hwmod *
- +  *
- +  * Convert a clockdomain name stored in a struct omap_hwmod into a
- +  * clockdomain pointer, and save it into the struct omap_hwmod.
- +  * return -EINVAL if clkdm_name does not exist or if the lookup failed.
- +  */
- + static int _init_clkdm(struct omap_hwmod *oh)
- + {
- + 	if (!oh->clkdm_name) {
- + 		pr_warning("omap_hwmod: %s: no clkdm_name\n", oh->name);
- + 		return -EINVAL;
- + 	}
- + 
- + 	oh->clkdm = clkdm_lookup(oh->clkdm_name);
- + 	if (!oh->clkdm) {
- + 		pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n",
- + 			oh->name, oh->clkdm_name);
- + 		return -EINVAL;
- + 	}
- + 
- + 	pr_debug("omap_hwmod: %s: associated to clkdm %s\n",
- + 		oh->name, oh->clkdm_name);
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * _init_clocks - clk_get() all clocks associated with this hwmod. Retrieve as
- +  * well the clockdomain.
- +  * @oh: struct omap_hwmod *
- +  * @data: not used; pass NULL
- +  *
- +  * Called by omap_hwmod_setup_*() (after omap2_clk_init()).
- +  * Resolves all clock names embedded in the hwmod.  Returns 0 on
- +  * success, or a negative error code on failure.
- +  */
- + static int _init_clocks(struct omap_hwmod *oh, void *data)
- + {
- + 	int ret = 0;
- + 
- + 	if (oh->_state != _HWMOD_STATE_REGISTERED)
- + 		return 0;
- + 
- + 	pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name);
- + 
- + 	ret |= _init_main_clk(oh);
- + 	ret |= _init_interface_clks(oh);
- + 	ret |= _init_opt_clks(oh);
- + 	ret |= _init_clkdm(oh);
- + 
- + 	if (!ret)
- + 		oh->_state = _HWMOD_STATE_CLKS_INITED;
- + 	else
- + 		pr_warning("omap_hwmod: %s: cannot _init_clocks\n", oh->name);
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * _wait_target_ready - wait for a module to leave slave idle
- +  * @oh: struct omap_hwmod *
- +  *
- +  * Wait for a module @oh to leave slave idle.  Returns 0 if the module
- +  * does not have an IDLEST bit or if the module successfully leaves
- +  * slave idle; otherwise, pass along the return value of the
- +  * appropriate *_cm*_wait_module_ready() function.
- +  */
- + static int _wait_target_ready(struct omap_hwmod *oh)
- + {
- + 	struct omap_hwmod_ocp_if *os;
- + 	int ret;
- + 
- + 	if (!oh)
- + 		return -EINVAL;
- + 
- + 	if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
- + 		return 0;
- + 
- + 	os = oh->slaves[oh->_mpu_port_index];
- + 
- + 	if (oh->flags & HWMOD_NO_IDLEST)
- + 		return 0;
- + 
- + 	/* XXX check module SIDLEMODE */
- + 
- + 	/* XXX check clock enable states */
- + 
- + 	if (!oh->clkdm)
- + 		return -EINVAL;
- + 
- + 	ret = omap4_cminst_wait_module_ready(oh->clkdm->prcm_partition,
- + 					     oh->clkdm->cm_inst,
- + 					     oh->clkdm->clkdm_offs,
- + 					     oh->prcm.omap4.clkctrl_offs);
- + 	
- + 	return ret;
- + }
- + 
- + /**
- +  * _lookup_hardreset - fill register bit info for this hwmod/reset line
- +  * @oh: struct omap_hwmod *
- +  * @name: name of the reset line in the context of this hwmod
- +  * @ohri: struct omap_hwmod_rst_info * that this function will fill in
- +  *
- +  * Return the bit position of the reset line that match the
- +  * input name. Return -ENOENT if not found.
- +  */
- + static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name,
- + 			    struct omap_hwmod_rst_info *ohri)
- + {
- + 	int i;
- + 
- + 	for (i = 0; i < oh->rst_lines_cnt; i++) {
- + 		const char *rst_line = oh->rst_lines[i].name;
- + 		if (!strcmp(rst_line, name)) {
- + 			ohri->rst_shift = oh->rst_lines[i].rst_shift;
- + 			ohri->st_shift = oh->rst_lines[i].st_shift;
- + 			pr_debug("omap_hwmod: %s: %s: %s: rst %d st %d\n",
- + 				 oh->name, __func__, rst_line, ohri->rst_shift,
- + 				 ohri->st_shift);
- + 
- + 			return 0;
- + 		}
- + 	}
- + 
- + 	return -ENOENT;
- + }
- + 
- + /**
- +  * _assert_hardreset - assert the HW reset line of submodules
- +  * contained in the hwmod module.
- +  * @oh: struct omap_hwmod *
- +  * @name: name of the reset line to lookup and assert
- +  *
- +  * Some IP like dsp, ipu or iva contain processor that require
- +  * an HW reset line to be assert / deassert in order to enable fully
- +  * the IP.
- +  */
- + static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
- + {
- + 	struct omap_hwmod_rst_info ohri;
- + 	u8 ret;
- + 
- + 	if (!oh)
- + 		return -EINVAL;
- + 
- + 	ret = _lookup_hardreset(oh, name, &ohri);
- + 	if (IS_ERR_VALUE(ret))
- + 		return ret;
- + 
- + 	/*
- + 	 * In order to use omap4 prm code for am33xx family of devices,
- + 	 * first check cpu_is_am33xx here.
- + 	 *
- + 	 * Note: cpu_is_omap34xx is true for am33xx device as well.
- + 	 */
- + 	return omap4_prminst_assert_hardreset(ohri.rst_shift,
- + 				  oh->clkdm->pwrdm.ptr->prcm_partition,
- + 				  oh->clkdm->pwrdm.ptr->prcm_offs,
- + 				  oh->prcm.omap4.rstctrl_offs);
- + 	
- + }
- + 
- + /**
- +  * _deassert_hardreset - deassert the HW reset line of submodules contained
- +  * in the hwmod module.
- +  * @oh: struct omap_hwmod *
- +  * @name: name of the reset line to look up and deassert
- +  *
- +  * Some IP like dsp, ipu or iva contain processor that require
- +  * an HW reset line to be assert / deassert in order to enable fully
- +  * the IP.
- +  */
- + static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
- + {
- + 	struct omap_hwmod_rst_info ohri;
- + 	int ret;
- + 
- + 	if (!oh)
- + 		return -EINVAL;
- + 
- + 	ret = _lookup_hardreset(oh, name, &ohri);
- + 	if (IS_ERR_VALUE(ret))
- + 		return ret;
- + 
- + 	/*
- + 	 * In order to use omap4 prm code for am33xx family of devices,
- + 	 * first check cpu_is_am33xx here.
- + 	 *
- + 	 * Note: cpu_is_omap34xx is true for am33xx device as well.
- + 	 */
- + 	ret = omap4_prminst_deassert_hardreset(ohri.rst_shift,
- + 			  ohri.st_shift,
- + 			  oh->clkdm->pwrdm.ptr->prcm_partition,
- + 			  oh->clkdm->pwrdm.ptr->prcm_offs,
- + 			  oh->prcm.omap4.rstctrl_offs,
- + 			  oh->prcm.omap4.rstst_offs);
- + 	
- + 	if (ret == -EBUSY)
- + 		pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name);
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * _read_hardreset - read the HW reset line state of submodules
- +  * contained in the hwmod module
- +  * @oh: struct omap_hwmod *
- +  * @name: name of the reset line to look up and read
- +  *
- +  * Return the state of the reset line.
- +  */
- + static int _read_hardreset(struct omap_hwmod *oh, const char *name)
- + {
- + 	struct omap_hwmod_rst_info ohri;
- + 	u8 ret;
- + 
- + 	if (!oh)
- + 		return -EINVAL;
- + 
- + 	ret = _lookup_hardreset(oh, name, &ohri);
- + 	if (IS_ERR_VALUE(ret))
- + 		return ret;
- + 
- + 	/*
- + 	 * In order to use omap4 prm code for am33xx family of devices,
- + 	 * first check cpu_is_am33xx here.
- + 	 *
- + 	 * Note: cpu_is_omap34xx is true for am33xx device as well.
- + 	 */
- + 	return omap4_prminst_is_hardreset_asserted(ohri.rst_shift,
- + 			  oh->clkdm->pwrdm.ptr->prcm_partition,
- + 			  oh->clkdm->pwrdm.ptr->prcm_offs,
- + 			  oh->prcm.omap4.rstctrl_offs);
- + }
- + 
- + /**
- +  * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit
- +  * @oh: struct omap_hwmod *
- +  *
- +  * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit.  hwmod must be
- +  * enabled for this to work.  Returns -EINVAL if the hwmod cannot be
- +  * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if
- +  * the module did not reset in time, or 0 upon success.
- +  *
- +  * In OMAP3 a specific SYSSTATUS register is used to get the reset status.
- +  * Starting in OMAP4, some IPs do not have SYSSTATUS registers and instead
- +  * use the SYSCONFIG softreset bit to provide the status.
- +  *
- +  * Note that some IP like McBSP do have reset control but don't have
- +  * reset status.
- +  */
- + static int _ocp_softreset(struct omap_hwmod *oh)
- + {
- + 	u32 v;
- + 	int c = 0;
- + 	int ret = 0;
- + 
- + 	if (!oh->class->sysc ||
- + 	    !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET))
- + 		return -EINVAL;
- + 
- + 	/* clocks must be on for this operation */
- + 	if (oh->_state != _HWMOD_STATE_ENABLED) {
- + 		pr_warning("omap_hwmod: %s: reset can only be entered from "
- + 			   "enabled state\n", oh->name);
- + 		return -EINVAL;
- + 	}
- + 
- + 	/* For some modules, all optionnal clocks need to be enabled as well */
- + 	if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)
- + 		_enable_optional_clocks(oh);
- + 
- + 	pr_debug("omap_hwmod: %s: resetting via OCP SOFTRESET\n", oh->name);
- + 
- + 	v = oh->_sysc_cache;
- + 	ret = _set_softreset(oh, &v);
- + 	if (ret)
- + 		goto dis_opt_clks;
- + 	_write_sysconfig(v, oh);
- + 
- + 	if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)
- + 		omap_test_timeout((omap_hwmod_read(oh,
- + 						    oh->class->sysc->syss_offs)
- + 				   & SYSS_RESETDONE_MASK),
- + 				  MAX_MODULE_SOFTRESET_WAIT, c);
- + 	else if (oh->class->sysc->sysc_flags & SYSC_HAS_RESET_STATUS)
- + 		omap_test_timeout(!(omap_hwmod_read(oh,
- + 						     oh->class->sysc->sysc_offs)
- + 				   & SYSC_TYPE2_SOFTRESET_MASK),
- + 				  MAX_MODULE_SOFTRESET_WAIT, c);
- + 
- + 	if (c == MAX_MODULE_SOFTRESET_WAIT)
- + 		pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n",
- + 			   oh->name, MAX_MODULE_SOFTRESET_WAIT);
- + 	else
- + 		pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c);
- + 
- + 	/*
- + 	 * XXX add _HWMOD_STATE_WEDGED for modules that don't come back from
- + 	 * _wait_target_ready() or _reset()
- + 	 */
- + 
- + 	ret = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
- + 
- + dis_opt_clks:
- + 	if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)
- + 		_disable_optional_clocks(oh);
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * _reset - reset an omap_hwmod
- +  * @oh: struct omap_hwmod *
- +  *
- +  * Resets an omap_hwmod @oh.  The default software reset mechanism for
- +  * most OMAP IP blocks is triggered via the OCP_SYSCONFIG.SOFTRESET
- +  * bit.  However, some hwmods cannot be reset via this method: some
- +  * are not targets and therefore have no OCP header registers to
- +  * access; others (like the IVA) have idiosyncratic reset sequences.
- +  * So for these relatively rare cases, custom reset code can be
- +  * supplied in the struct omap_hwmod_class .reset function pointer.
- +  * Passes along the return value from either _reset() or the custom
- +  * reset function - these must return -EINVAL if the hwmod cannot be
- +  * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if
- +  * the module did not reset in time, or 0 upon success.
- +  */
- + static int _reset(struct omap_hwmod *oh)
- + {
- + 	int ret;
- + 
- + 	pr_debug("omap_hwmod: %s: resetting\n", oh->name);
- + 
- + 	ret = (oh->class->reset) ? oh->class->reset(oh) : _ocp_softreset(oh);
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * _enable - enable an omap_hwmod
- +  * @oh: struct omap_hwmod *
- +  *
- +  * Enables an omap_hwmod @oh such that the MPU can access the hwmod's
- +  * register target.  Returns -EINVAL if the hwmod is in the wrong
- +  * state or passes along the return value of _wait_target_ready().
- +  */
- + static int _enable(struct omap_hwmod *oh)
- + {
- + 	int r;
- + 	int hwsup = 0;
- + 
- + 	pr_debug("omap_hwmod: %s: enabling\n", oh->name);
- + 
- + 	/*
- + 	 * hwmods with HWMOD_INIT_NO_IDLE flag set are left
- + 	 * in enabled state at init.
- + 	 * Now that someone is really trying to enable them,
- + 	 * just ensure that the hwmod mux is set.
- + 	 */
- + 	if (oh->_int_flags & _HWMOD_SKIP_ENABLE) {
- + 		/*
- + 		 * If the caller has mux data populated, do the mux'ing
- + 		 * which wouldn't have been done as part of the _enable()
- + 		 * done during setup.
- + 		 */
- + 		if (oh->mux)
- + 			omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
- + 
- + 		oh->_int_flags &= ~_HWMOD_SKIP_ENABLE;
- + 		return 0;
- + 	}
- + 
- + 	if (oh->_state != _HWMOD_STATE_INITIALIZED &&
- + 	    oh->_state != _HWMOD_STATE_IDLE &&
- + 	    oh->_state != _HWMOD_STATE_DISABLED) {
- + 		WARN(1, "omap_hwmod: %s: enabled state can only be entered "
- + 		     "from initialized, idle, or disabled state\n", oh->name);
- + 		return -EINVAL;
- + 	}
- + 
- + 	/* Mux pins for device runtime if populated */
- + 	if (oh->mux && (!oh->mux->enabled ||
- + 			((oh->_state == _HWMOD_STATE_IDLE) &&
- + 			 oh->mux->pads_dynamic)))
- + 		omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
- + 
- + 	_add_initiator_dep(oh, mpu_oh);
- + 
- + 	if (oh->clkdm) {
- + 		/*
- + 		 * A clockdomain must be in SW_SUP before enabling
- + 		 * completely the module. The clockdomain can be set
- + 		 * in HW_AUTO only when the module become ready.
- + 		 */
- + 		hwsup = clkdm_in_hwsup(oh->clkdm);
- + 	}
- + 
- + 	_enable_clocks(oh);
- + 	_enable_module(oh);
- + 
- + 	/*
- + 	 * If an IP contains only one HW reset line, then de-assert it in order
- + 	 * to allow the module state transition. Otherwise the PRCM will return
- + 	 * Intransition status, and the init will failed.
- + 	 *
- + 	 * TODO: Based on observation, on module enable sate, we can safely
- + 	 *	assert the reset signal here (irrespective of idlemode state).
- + 	 */
- + 	if ((oh->_state == _HWMOD_STATE_INITIALIZED ||
- + 	     oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1)
- + 		_deassert_hardreset(oh, oh->rst_lines[0].name);
- + 
- + 	r = _wait_target_ready(oh);
- + 	if (!r) {
- + 		/*
- + 		 * Set the clockdomain to HW_AUTO only if the target is ready,
- + 		 * assuming that the previous state was HW_AUTO
- + 		 */
- + 		if (oh->clkdm && hwsup)
- + 			clkdm_allow_idle(oh->clkdm);
- + 
- + 		oh->_state = _HWMOD_STATE_ENABLED;
- + 
- + 		/* Access the sysconfig only if the target is ready */
- + 		if (oh->class->sysc) {
- + 			if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED))
- + 				_update_sysc_cache(oh);
- + 			_enable_sysc(oh);
- + 		}
- + 	} else {
- + 		_disable_clocks(oh);
- + 		pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n",
- + 			 oh->name, r);
- + 
- + 	}
- + 
- + 	return r;
- + }
- + 
- + /**
- +  * _idle - idle an omap_hwmod
- +  * @oh: struct omap_hwmod *
- +  *
- +  * Idles an omap_hwmod @oh.  This should be called once the hwmod has
- +  * no further work.  Returns -EINVAL if the hwmod is in the wrong
- +  * state or returns 0.
- +  */
- + static int _idle(struct omap_hwmod *oh)
- + {
- + 	pr_debug("omap_hwmod: %s: idling\n", oh->name);
- + 
- + 	if (oh->_state != _HWMOD_STATE_ENABLED) {
- + 		WARN(1, "omap_hwmod: %s: idle state can only be entered from "
- + 		     "enabled state\n", oh->name);
- + 		return -EINVAL;
- + 	}
- + 
- + 	/*
- + 	 * FIXME: Due to AM33XX CPSW IP integration bug, it is required
- + 	 * to assert ocp reset signal to the module before disabling it.
- + 	 */
- + 	if (oh->flags & HWMOD_SWSUP_RESET_BEFORE_IDLE)
- + 		_reset(oh);
- + 
- + 	if (oh->class->sysc)
- + 		_idle_sysc(oh);
- + 	_del_initiator_dep(oh, mpu_oh);
- + 
- + 	_omap4_disable_module(oh);
- + 
- + 	/*
- + 	 * The module must be in idle mode before disabling any parents
- + 	 * clocks. Otherwise, the parent clock might be disabled before
- + 	 * the module transition is done, and thus will prevent the
- + 	 * transition to complete properly.
- + 	 */
- + 	_disable_clocks(oh);
- + 	
- + 	/* Mux pins for device idle if populated */
- + 	if (oh->mux && oh->mux->pads_dynamic)
- + 		omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE);
- + 
- + 	oh->_state = _HWMOD_STATE_IDLE;
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * omap_hwmod_set_ocp_autoidle - set the hwmod's OCP autoidle bit
- +  * @oh: struct omap_hwmod *
- +  * @autoidle: desired AUTOIDLE bitfield value (0 or 1)
- +  *
- +  * Sets the IP block's OCP autoidle bit in hardware, and updates our
- +  * local copy. Intended to be used by drivers that require
- +  * direct manipulation of the AUTOIDLE bits.
- +  * Returns -EINVAL if @oh is null or is not in the ENABLED state, or passes
- +  * along the return value from _set_module_autoidle().
- +  *
- +  * Any users of this function should be scrutinized carefully.
- +  */
- + int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle)
- + {
- + 	u32 v;
- + 	int retval = 0;
- + 	unsigned long flags;
- + 
- + 	if (!oh || oh->_state != _HWMOD_STATE_ENABLED)
- + 		return -EINVAL;
- + 
- + 	spin_lock_irqsave(&oh->_lock, flags);
- + 
- + 	v = oh->_sysc_cache;
- + 
- + 	retval = _set_module_autoidle(oh, autoidle, &v);
- + 
- + 	if (!retval)
- + 		_write_sysconfig(v, oh);
- + 
- + 	spin_unlock_irqrestore(&oh->_lock, flags);
- + 
- + 	return retval;
- + }
- + 
- + /**
- +  * _shutdown - shutdown an omap_hwmod
- +  * @oh: struct omap_hwmod *
- +  *
- +  * Shut down an omap_hwmod @oh.  This should be called when the driver
- +  * used for the hwmod is removed or unloaded or if the driver is not
- +  * used by the system.  Returns -EINVAL if the hwmod is in the wrong
- +  * state or returns 0.
- +  */
- + static int _shutdown(struct omap_hwmod *oh)
- + {
- + 	int ret;
- + 	u8 prev_state;
- + 
- + 	if (oh->_state != _HWMOD_STATE_IDLE &&
- + 	    oh->_state != _HWMOD_STATE_ENABLED) {
- + 		WARN(1, "omap_hwmod: %s: disabled state can only be entered "
- + 		     "from idle, or enabled state\n", oh->name);
- + 		return -EINVAL;
- + 	}
- + 
- + 	pr_debug("omap_hwmod: %s: disabling\n", oh->name);
- + 
- + 	if (oh->class->pre_shutdown) {
- + 		prev_state = oh->_state;
- + 		if (oh->_state == _HWMOD_STATE_IDLE)
- + 			_enable(oh);
- + 		ret = oh->class->pre_shutdown(oh);
- + 		if (ret) {
- + 			if (prev_state == _HWMOD_STATE_IDLE)
- + 				_idle(oh);
- + 			return ret;
- + 		}
- + 	}
- + 
- + 	if (oh->class->sysc) {
- + 		if (oh->_state == _HWMOD_STATE_IDLE)
- + 			_enable(oh);
- + 		_shutdown_sysc(oh);
- + 	}
- + 
- + 	/* clocks and deps are already disabled in idle */
- + 	if (oh->_state == _HWMOD_STATE_ENABLED) {
- + 		_del_initiator_dep(oh, mpu_oh);
- + 		/* XXX what about the other system initiators here? dma, dsp */
- + 		_omap4_disable_module(oh);
- + 		_disable_clocks(oh);
- + 	}
- + 	/* XXX Should this code also force-disable the optional clocks? */
- + 
- + 	/*
- + 	 * If an IP contains only one HW reset line, then assert it
- + 	 * after disabling the clocks and before shutting down the IP.
- + 	 */
- + 	if (oh->rst_lines_cnt == 1)
- + 		_assert_hardreset(oh, oh->rst_lines[0].name);
- + 
- + 	/* Mux pins to safe mode or use populated off mode values */
- + 	if (oh->mux)
- + 		omap_hwmod_mux(oh->mux, _HWMOD_STATE_DISABLED);
- + 
- + 	oh->_state = _HWMOD_STATE_DISABLED;
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * _setup - do initial configuration of omap_hwmod
- +  * @oh: struct omap_hwmod *
- +  *
- +  * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh
- +  * OCP_SYSCONFIG register.  Returns 0.
- +  */
- + static int _setup(struct omap_hwmod *oh, void *data)
- + {
- + 	int i, r;
- + 	u8 postsetup_state;
- + 
- + 	if (oh->_state != _HWMOD_STATE_CLKS_INITED)
- + 		return 0;
- + 
- + 	/* Set iclk autoidle mode */
- + 	if (oh->slaves_cnt > 0) {
- + 		for (i = 0; i < oh->slaves_cnt; i++) {
- + 			struct omap_hwmod_ocp_if *os = oh->slaves[i];
- + 			struct clk *c = os->_clk;
- + 
- + 			if (!c)
- + 				continue;
- + 
- + 			if (os->flags & OCPIF_SWSUP_IDLE) {
- + 				/* XXX omap_iclk_deny_idle(c); */
- + 			} else {
- + 				/* XXX omap_iclk_allow_idle(c); */
- + 				clk_enable(c);
- + 			}
- + 		}
- + 	}
- + 
- + 	oh->_state = _HWMOD_STATE_INITIALIZED;
- + 
- + 	/*
- + 	 * In the case of hwmod with hardreset that should not be
- + 	 * de-assert at boot time, we have to keep the module
- + 	 * initialized, because we cannot enable it properly with the
- + 	 * reset asserted. Exit without warning because that behavior is
- + 	 * expected.
- + 	 */
- + 	if ((oh->flags & HWMOD_INIT_NO_RESET) && oh->rst_lines_cnt == 1)
- + 		return 0;
- + 
- + 	r = _enable(oh);
- + 	if (r) {
- + 		pr_warning("omap_hwmod: %s: cannot be enabled (%d)\n",
- + 			   oh->name, oh->_state);
- + 		return 0;
- + 	}
- + 
- + 	if (!(oh->flags & HWMOD_INIT_NO_RESET)) {
- + 		_reset(oh);
- + 
- + 		/*
- + 		 * OCP_SYSCONFIG bits need to be reprogrammed after a softreset.
- + 		 * The _enable() function should be split to
- + 		 * avoid the rewrite of the OCP_SYSCONFIG register.
- + 		 */
- + 		if (oh->class->sysc) {
- + 			_update_sysc_cache(oh);
- + 			_enable_sysc(oh);
- + 		}
- + 	}
- + 
- + 	postsetup_state = oh->_postsetup_state;
- + 	if (postsetup_state == _HWMOD_STATE_UNKNOWN)
- + 		postsetup_state = _HWMOD_STATE_ENABLED;
- + 
- + 	/*
- + 	 * XXX HWMOD_INIT_NO_IDLE does not belong in hwmod data -
- + 	 * it should be set by the core code as a runtime flag during startup
- + 	 */
- + 	if ((oh->flags & HWMOD_INIT_NO_IDLE) &&
- + 	    (postsetup_state == _HWMOD_STATE_IDLE)) {
- + 		oh->_int_flags |= _HWMOD_SKIP_ENABLE;
- + 		postsetup_state = _HWMOD_STATE_ENABLED;
- + 	}
- + 
- + 	if (postsetup_state == _HWMOD_STATE_IDLE)
- + 		_idle(oh);
- + 	else if (postsetup_state == _HWMOD_STATE_DISABLED)
- + 		_shutdown(oh);
- + 	else if (postsetup_state != _HWMOD_STATE_ENABLED)
- + 		WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n",
- + 		     oh->name, postsetup_state);
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * _register - register a struct omap_hwmod
- +  * @oh: struct omap_hwmod *
- +  *
- +  * Registers the omap_hwmod @oh.  Returns -EEXIST if an omap_hwmod
- +  * already has been registered by the same name; -EINVAL if the
- +  * omap_hwmod is in the wrong state, if @oh is NULL, if the
- +  * omap_hwmod's class field is NULL; if the omap_hwmod is missing a
- +  * name, or if the omap_hwmod's class is missing a name; or 0 upon
- +  * success.
- +  *
- +  * XXX The data should be copied into bootmem, so the original data
- +  * should be marked __initdata and freed after init.  This would allow
- +  * unneeded omap_hwmods to be freed on multi-OMAP configurations.  Note
- +  * that the copy process would be relatively complex due to the large number
- +  * of substructures.
- +  */
- + static int __init _register(struct omap_hwmod *oh)
- + {
- + 	int ms_id;
- + 
- + 	if (!oh || !oh->name || !oh->class || !oh->class->name ||
- + 	    (oh->_state != _HWMOD_STATE_UNKNOWN))
- + 		return -EINVAL;
- + 
- + 	pr_debug("omap_hwmod: %s: registering\n", oh->name);
- + 
- + 	if (_lookup(oh->name))
- + 		return -EEXIST;
- + 
- + 	ms_id = _find_mpu_port_index(oh);
- + 	if (!IS_ERR_VALUE(ms_id))
- + 		oh->_mpu_port_index = ms_id;
- + 	else
- + 		oh->_int_flags |= _HWMOD_NO_MPU_PORT;
- + 
- + 	list_add_tail(&oh->node, &omap_hwmod_list);
- + 
- + 	spin_lock_init(&oh->_lock);
- + 
- + 	oh->_state = _HWMOD_STATE_REGISTERED;
- + 
- + 	/*
- + 	 * XXX Rather than doing a strcmp(), this should test a flag
- + 	 * set in the hwmod data, inserted by the autogenerator code.
- + 	 */
- + 	if (!strcmp(oh->name, MPU_INITIATOR_NAME))
- + 		mpu_oh = oh;
- + 
- + 	return 0;
- + }
- + 
- + 
- + /* Public functions */
- + 
- + u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs)
- + {
- + 	if (oh->flags & HWMOD_16BIT_REG)
- + 		return __raw_readw(oh->_mpu_rt_va + reg_offs);
- + 	else
- + 		return __raw_readl(oh->_mpu_rt_va + reg_offs);
- + }
- + 
- + void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs)
- + {
- + 	if (oh->flags & HWMOD_16BIT_REG)
- + 		__raw_writew(v, oh->_mpu_rt_va + reg_offs);
- + 	else
- + 		__raw_writel(v, oh->_mpu_rt_va + reg_offs);
- + }
- + 
- + /**
- +  * omap_hwmod_softreset - reset a module via SYSCONFIG.SOFTRESET bit
- +  * @oh: struct omap_hwmod *
- +  *
- +  * This is a public function exposed to drivers. Some drivers may need to do
- +  * some settings before and after resetting the device.  Those drivers after
- +  * doing the necessary settings could use this function to start a reset by
- +  * setting the SYSCONFIG.SOFTRESET bit.
- +  */
- + int omap_hwmod_softreset(struct omap_hwmod *oh)
- + {
- + 	u32 v;
- + 	int ret;
- + 
- + 	if (!oh || !(oh->_sysc_cache))
- + 		return -EINVAL;
- + 
- + 	v = oh->_sysc_cache;
- + 	ret = _set_softreset(oh, &v);
- + 	if (ret)
- + 		goto error;
- + 	_write_sysconfig(v, oh);
- + 
- + error:
- + 	return ret;
- + }
- + 
- + /**
- +  * omap_hwmod_set_master_standbymode - set the hwmod's OCP master standbymode
- +  * @oh: struct omap_hwmod *
- +  * @standbymode: MSTANDBY field bits (shifted to bit 0)
- +  *
- +  * Sets the IP block's OCP master staandby mode in hardware, and updates our
- +  * local copy.  Intended to be used by drivers that have some erratum
- +  * that requires direct manipulation of the MSTANDBY bits.  Returns
- +  * -EINVAL if @oh is null, or passes along the return value from
- +  * _set_master_standbymode().
- +  *
- +  */
- + int omap_hwmod_set_master_standbymode(struct omap_hwmod *oh, u8 standbymode)
- + {
- + 	u32 v;
- + 	int retval = 0;
- + 
- + 	if (!oh)
- + 		return -EINVAL;
- + 
- + 	v = oh->_sysc_cache;
- + 
- + 	retval = _set_master_standbymode(oh, standbymode, &v);
- + 	if (!retval)
- + 		_write_sysconfig(v, oh);
- + 
- + 	return retval;
- + }
- + 
- + /**
- +  * omap_hwmod_set_slave_idlemode - set the hwmod's OCP slave idlemode
- +  * @oh: struct omap_hwmod *
- +  * @idlemode: SIDLEMODE field bits (shifted to bit 0)
- +  *
- +  * Sets the IP block's OCP slave idlemode in hardware, and updates our
- +  * local copy.  Intended to be used by drivers that have some erratum
- +  * that requires direct manipulation of the SIDLEMODE bits.  Returns
- +  * -EINVAL if @oh is null, or passes along the return value from
- +  * _set_slave_idlemode().
- +  *
- +  * XXX Does this function have any current users?  If not, we should
- +  * remove it; it is better to let the rest of the hwmod code handle this.
- +  * Any users of this function should be scrutinized carefully.
- +  */
- + int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode)
- + {
- + 	u32 v;
- + 	int retval = 0;
- + 
- + 	if (!oh)
- + 		return -EINVAL;
- + 
- + 	v = oh->_sysc_cache;
- + 
- + 	retval = _set_slave_idlemode(oh, idlemode, &v);
- + 	if (!retval)
- + 		_write_sysconfig(v, oh);
- + 
- + 	return retval;
- + }
- + 
- + /**
- +  * omap_hwmod_lookup - look up a registered omap_hwmod by name
- +  * @name: name of the omap_hwmod to look up
- +  *
- +  * Given a @name of an omap_hwmod, return a pointer to the registered
- +  * struct omap_hwmod *, or NULL upon error.
- +  */
- + struct omap_hwmod *omap_hwmod_lookup(const char *name)
- + {
- + 	struct omap_hwmod *oh;
- + 
- + 	if (!name)
- + 		return NULL;
- + 
- + 	oh = _lookup(name);
- + 
- + 	return oh;
- + }
- + 
- + /**
- +  * omap_hwmod_for_each - call function for each registered omap_hwmod
- +  * @fn: pointer to a callback function
- +  * @data: void * data to pass to callback function
- +  *
- +  * Call @fn for each registered omap_hwmod, passing @data to each
- +  * function.  @fn must return 0 for success or any other value for
- +  * failure.  If @fn returns non-zero, the iteration across omap_hwmods
- +  * will stop and the non-zero return value will be passed to the
- +  * caller of omap_hwmod_for_each().  @fn is called with
- +  * omap_hwmod_for_each() held.
- +  */
- + int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
- + 			void *data)
- + {
- + 	struct omap_hwmod *temp_oh;
- + 	int ret = 0;
- + 
- + 	if (!fn)
- + 		return -EINVAL;
- + 
- + 	list_for_each_entry(temp_oh, &omap_hwmod_list, node) {
- + 		ret = (*fn)(temp_oh, data);
- + 		if (ret)
- + 			break;
- + 	}
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * omap_hwmod_register - register an array of hwmods
- +  * @ohs: pointer to an array of omap_hwmods to register
- +  *
- +  * Intended to be called early in boot before the clock framework is
- +  * initialized.  If @ohs is not null, will register all omap_hwmods
- +  * listed in @ohs that are valid for this chip.  Returns 0.
- +  */
- + int __init omap_hwmod_register(struct omap_hwmod **ohs)
- + {
- + 	int r, i;
- + 
- + 	if (!ohs)
- + 		return 0;
- + 
- + 	i = 0;
- + 	do {
- + 		r = _register(ohs[i]);
- + 		WARN(r, "omap_hwmod: %s: _register returned %d\n", ohs[i]->name,
- + 		     r);
- + 	} while (ohs[++i]);
- + 
- + 	return 0;
- + }
- + 
- + /*
- +  * _populate_mpu_rt_base - populate the virtual address for a hwmod
- +  *
- +  * Must be called only from omap_hwmod_setup_*() so ioremap works properly.
- +  * Assumes the caller takes care of locking if needed.
- +  */
- + static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data)
- + {
- + 	if (oh->_state != _HWMOD_STATE_REGISTERED)
- + 		return 0;
- + 
- + 	if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
- + 		return 0;
- + 
- + 	oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index);
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * omap_hwmod_setup_one - set up a single hwmod
- +  * @oh_name: const char * name of the already-registered hwmod to set up
- +  *
- +  * Must be called after omap2_clk_init().  Resolves the struct clk
- +  * names to struct clk pointers for each registered omap_hwmod.  Also
- +  * calls _setup() on each hwmod.  Returns -EINVAL upon error or 0 upon
- +  * success.
- +  */
- + int __init omap_hwmod_setup_one(const char *oh_name)
- + {
- + 	struct omap_hwmod *oh;
- + 	int r;
- + 
- + 	pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__);
- + 
- + 	if (!mpu_oh) {
- + 		pr_err("omap_hwmod: %s: cannot setup_one: MPU initiator hwmod %s not yet registered\n",
- + 		       oh_name, MPU_INITIATOR_NAME);
- + 		return -EINVAL;
- + 	}
- + 
- + 	oh = _lookup(oh_name);
- + 	if (!oh) {
- + 		WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name);
- + 		return -EINVAL;
- + 	}
- + 
- + 	if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh)
- + 		omap_hwmod_setup_one(MPU_INITIATOR_NAME);
- + 
- + 	r = _populate_mpu_rt_base(oh, NULL);
- + 	if (IS_ERR_VALUE(r)) {
- + 		WARN(1, "omap_hwmod: %s: couldn't set mpu_rt_base\n", oh_name);
- + 		return -EINVAL;
- + 	}
- + 
- + 	r = _init_clocks(oh, NULL);
- + 	if (IS_ERR_VALUE(r)) {
- + 		WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh_name);
- + 		return -EINVAL;
- + 	}
- + 
- + 	_setup(oh, NULL);
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * omap_hwmod_setup - do some post-clock framework initialization
- +  *
- +  * Must be called after omap2_clk_init().  Resolves the struct clk names
- +  * to struct clk pointers for each registered omap_hwmod.  Also calls
- +  * _setup() on each hwmod.  Returns 0 upon success.
- +  */
- + static int __init omap_hwmod_setup_all(void)
- + {
- + 	int r;
- + 
- + 	if (!mpu_oh) {
- + 		pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n",
- + 		       __func__, MPU_INITIATOR_NAME);
- + 		return -EINVAL;
- + 	}
- + 
- + 	r = omap_hwmod_for_each(_populate_mpu_rt_base, NULL);
- + 
- + 	r = omap_hwmod_for_each(_init_clocks, NULL);
- + 	WARN(IS_ERR_VALUE(r),
- + 	     "omap_hwmod: %s: _init_clocks failed\n", __func__);
- + 
- + 	omap_hwmod_for_each(_setup, NULL);
- + 
- + 	return 0;
- + }
- + core_initcall(omap_hwmod_setup_all);
- + 
- + /**
- +  * omap_hwmod_enable - enable an omap_hwmod
- +  * @oh: struct omap_hwmod *
- +  *
- +  * Enable an omap_hwmod @oh.  Intended to be called by omap_device_enable().
- +  * Returns -EINVAL on error or passes along the return value from _enable().
- +  */
- + int omap_hwmod_enable(struct omap_hwmod *oh)
- + {
- + 	int r;
- + 	unsigned long flags;
- + 
- + 	if (!oh)
- + 		return -EINVAL;
- + 
- + 	spin_lock_irqsave(&oh->_lock, flags);
- + 	r = _enable(oh);
- + 	spin_unlock_irqrestore(&oh->_lock, flags);
- + 
- + 	return r;
- + }
- + 
- + /**
- +  * omap_hwmod_idle - idle an omap_hwmod
- +  * @oh: struct omap_hwmod *
- +  *
- +  * Idle an omap_hwmod @oh.  Intended to be called by omap_device_idle().
- +  * Returns -EINVAL on error or passes along the return value from _idle().
- +  */
- + int omap_hwmod_idle(struct omap_hwmod *oh)
- + {
- + 	unsigned long flags;
- + 
- + 	if (!oh)
- + 		return -EINVAL;
- + 
- + 	spin_lock_irqsave(&oh->_lock, flags);
- + 	_idle(oh);
- + 	spin_unlock_irqrestore(&oh->_lock, flags);
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * omap_hwmod_shutdown - shutdown an omap_hwmod
- +  * @oh: struct omap_hwmod *
- +  *
- +  * Shutdown an omap_hwmod @oh.  Intended to be called by
- +  * omap_device_shutdown().  Returns -EINVAL on error or passes along
- +  * the return value from _shutdown().
- +  */
- + int omap_hwmod_shutdown(struct omap_hwmod *oh)
- + {
- + 	unsigned long flags;
- + 
- + 	if (!oh)
- + 		return -EINVAL;
- + 
- + 	spin_lock_irqsave(&oh->_lock, flags);
- + 	_shutdown(oh);
- + 	spin_unlock_irqrestore(&oh->_lock, flags);
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * omap_hwmod_enable_clocks - enable main_clk, all interface clocks
- +  * @oh: struct omap_hwmod *oh
- +  *
- +  * Intended to be called by the omap_device code.
- +  */
- + int omap_hwmod_enable_clocks(struct omap_hwmod *oh)
- + {
- + 	unsigned long flags;
- + 
- + 	spin_lock_irqsave(&oh->_lock, flags);
- + 	_enable_clocks(oh);
- + 	spin_unlock_irqrestore(&oh->_lock, flags);
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * omap_hwmod_disable_clocks - disable main_clk, all interface clocks
- +  * @oh: struct omap_hwmod *oh
- +  *
- +  * Intended to be called by the omap_device code.
- +  */
- + int omap_hwmod_disable_clocks(struct omap_hwmod *oh)
- + {
- + 	unsigned long flags;
- + 
- + 	spin_lock_irqsave(&oh->_lock, flags);
- + 	_disable_clocks(oh);
- + 	spin_unlock_irqrestore(&oh->_lock, flags);
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * omap_hwmod_ocp_barrier - wait for posted writes against the hwmod to complete
- +  * @oh: struct omap_hwmod *oh
- +  *
- +  * Intended to be called by drivers and core code when all posted
- +  * writes to a device must complete before continuing further
- +  * execution (for example, after clearing some device IRQSTATUS
- +  * register bits)
- +  *
- +  * XXX what about targets with multiple OCP threads?
- +  */
- + void omap_hwmod_ocp_barrier(struct omap_hwmod *oh)
- + {
- + 	BUG_ON(!oh);
- + 
- + 	if (!oh->class->sysc || !oh->class->sysc->sysc_flags) {
- + 		WARN(1, "omap_device: %s: OCP barrier impossible due to "
- + 		      "device configuration\n", oh->name);
- + 		return;
- + 	}
- + 
- + 	/*
- + 	 * Forces posted writes to complete on the OCP thread handling
- + 	 * register writes
- + 	 */
- + 	omap_hwmod_read(oh, oh->class->sysc->sysc_offs);
- + }
- + 
- + /**
- +  * omap_hwmod_reset - reset the hwmod
- +  * @oh: struct omap_hwmod *
- +  *
- +  * Under some conditions, a driver may wish to reset the entire device.
- +  * Called from omap_device code.  Returns -EINVAL on error or passes along
- +  * the return value from _reset().
- +  */
- + int omap_hwmod_reset(struct omap_hwmod *oh)
- + {
- + 	int r;
- + 	unsigned long flags;
- + 
- + 	if (!oh)
- + 		return -EINVAL;
- + 
- + 	spin_lock_irqsave(&oh->_lock, flags);
- + 	r = _reset(oh);
- + 	spin_unlock_irqrestore(&oh->_lock, flags);
- + 
- + 	return r;
- + }
- + 
- + /**
- +  * omap_hwmod_count_resources - count number of struct resources needed by hwmod
- +  * @oh: struct omap_hwmod *
- +  * @res: pointer to the first element of an array of struct resource to fill
- +  *
- +  * Count the number of struct resource array elements necessary to
- +  * contain omap_hwmod @oh resources.  Intended to be called by code
- +  * that registers omap_devices.  Intended to be used to determine the
- +  * size of a dynamically-allocated struct resource array, before
- +  * calling omap_hwmod_fill_resources().  Returns the number of struct
- +  * resource array elements needed.
- +  *
- +  * XXX This code is not optimized.  It could attempt to merge adjacent
- +  * resource IDs.
- +  *
- +  */
- + int omap_hwmod_count_resources(struct omap_hwmod *oh)
- + {
- + 	int ret, i;
- + 
- + 	ret = _count_mpu_irqs(oh) + _count_sdma_reqs(oh);
- + 
- + 	for (i = 0; i < oh->slaves_cnt; i++)
- + 		ret += _count_ocp_if_addr_spaces(oh->slaves[i]);
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * omap_hwmod_fill_resources - fill struct resource array with hwmod data
- +  * @oh: struct omap_hwmod *
- +  * @res: pointer to the first element of an array of struct resource to fill
- +  *
- +  * Fill the struct resource array @res with resource data from the
- +  * omap_hwmod @oh.  Intended to be called by code that registers
- +  * omap_devices.  See also omap_hwmod_count_resources().  Returns the
- +  * number of array elements filled.
- +  */
- + int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
- + {
- + 	int i, j, mpu_irqs_cnt, sdma_reqs_cnt;
- + 	int r = 0;
- + 
- + 	/* For each IRQ, DMA, memory area, fill in array.*/
- + 
- + 	mpu_irqs_cnt = _count_mpu_irqs(oh);
- + 	for (i = 0; i < mpu_irqs_cnt; i++) {
- + 		(res + r)->name = (oh->mpu_irqs + i)->name;
- + 		(res + r)->start = (oh->mpu_irqs + i)->irq;
- + 		(res + r)->end = (oh->mpu_irqs + i)->irq;
- + 		(res + r)->flags = IORESOURCE_IRQ;
- + 		r++;
- + 	}
- + 
- + 	sdma_reqs_cnt = _count_sdma_reqs(oh);
- + 	for (i = 0; i < sdma_reqs_cnt; i++) {
- + 		(res + r)->name = (oh->sdma_reqs + i)->name;
- + 		(res + r)->start = (oh->sdma_reqs + i)->dma_req;
- + 		(res + r)->end = (oh->sdma_reqs + i)->dma_req;
- + 		(res + r)->flags = IORESOURCE_DMA;
- + 		r++;
- + 	}
- + 
- + 	for (i = 0; i < oh->slaves_cnt; i++) {
- + 		struct omap_hwmod_ocp_if *os;
- + 		int addr_cnt;
- + 
- + 		os = oh->slaves[i];
- + 		addr_cnt = _count_ocp_if_addr_spaces(os);
- + 
- + 		for (j = 0; j < addr_cnt; j++) {
- + 			(res + r)->name = (os->addr + j)->name;
- + 			(res + r)->start = (os->addr + j)->pa_start;
- + 			(res + r)->end = (os->addr + j)->pa_end;
- + 			(res + r)->flags = IORESOURCE_MEM;
- + 			r++;
- + 		}
- + 	}
- + 
- + 	return r;
- + }
- + 
- + /**
- +  * omap_hwmod_get_pwrdm - return pointer to this module's main powerdomain
- +  * @oh: struct omap_hwmod *
- +  *
- +  * Return the powerdomain pointer associated with the OMAP module
- +  * @oh's main clock.  If @oh does not have a main clk, return the
- +  * powerdomain associated with the interface clock associated with the
- +  * module's MPU port. (XXX Perhaps this should use the SDMA port
- +  * instead?)  Returns NULL on error, or a struct powerdomain * on
- +  * success.
- +  */
- + struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh)
- + {
- + 	struct clk *c;
- + 
- + 	if (!oh)
- + 		return NULL;
- + 
- + 	if (oh->_clk) {
- + 		c = oh->_clk;
- + 	} else {
- + 		if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
- + 			return NULL;
- + 		c = oh->slaves[oh->_mpu_port_index]->_clk;
- + 	}
- + 
- + 	if (!c->clkdm)
- + 		return NULL;
- + 
- + 	return c->clkdm->pwrdm.ptr;
- + 
- + }
- + 
- + /**
- +  * omap_hwmod_get_mpu_rt_va - return the module's base address (for the MPU)
- +  * @oh: struct omap_hwmod *
- +  *
- +  * Returns the virtual address corresponding to the beginning of the
- +  * module's register target, in the address range that is intended to
- +  * be used by the MPU.  Returns the virtual address upon success or NULL
- +  * upon error.
- +  */
- + void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh)
- + {
- + 	if (!oh)
- + 		return NULL;
- + 
- + 	if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
- + 		return NULL;
- + 
- + 	if (oh->_state == _HWMOD_STATE_UNKNOWN)
- + 		return NULL;
- + 
- + 	return oh->_mpu_rt_va;
- + }
- + 
- + /**
- +  * omap_hwmod_add_initiator_dep - add sleepdep from @init_oh to @oh
- +  * @oh: struct omap_hwmod *
- +  * @init_oh: struct omap_hwmod * (initiator)
- +  *
- +  * Add a sleep dependency between the initiator @init_oh and @oh.
- +  * Intended to be called by DSP/Bridge code via platform_data for the
- +  * DSP case; and by the DMA code in the sDMA case.  DMA code, *Bridge
- +  * code needs to add/del initiator dependencies dynamically
- +  * before/after accessing a device.  Returns the return value from
- +  * _add_initiator_dep().
- +  *
- +  * XXX Keep a usecount in the clockdomain code
- +  */
- + int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh,
- + 				 struct omap_hwmod *init_oh)
- + {
- + 	return _add_initiator_dep(oh, init_oh);
- + }
- + 
- + /*
- +  * XXX what about functions for drivers to save/restore ocp_sysconfig
- +  * for context save/restore operations?
- +  */
- + 
- + /**
- +  * omap_hwmod_del_initiator_dep - remove sleepdep from @init_oh to @oh
- +  * @oh: struct omap_hwmod *
- +  * @init_oh: struct omap_hwmod * (initiator)
- +  *
- +  * Remove a sleep dependency between the initiator @init_oh and @oh.
- +  * Intended to be called by DSP/Bridge code via platform_data for the
- +  * DSP case; and by the DMA code in the sDMA case.  DMA code, *Bridge
- +  * code needs to add/del initiator dependencies dynamically
- +  * before/after accessing a device.  Returns the return value from
- +  * _del_initiator_dep().
- +  *
- +  * XXX Keep a usecount in the clockdomain code
- +  */
- + int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh,
- + 				 struct omap_hwmod *init_oh)
- + {
- + 	return _del_initiator_dep(oh, init_oh);
- + }
- + 
- + /**
- +  * omap_hwmod_enable_wakeup - allow device to wake up the system
- +  * @oh: struct omap_hwmod *
- +  *
- +  * Sets the module OCP socket ENAWAKEUP bit to allow the module to
- +  * send wakeups to the PRCM.  Eventually this should sets PRCM wakeup
- +  * registers to cause the PRCM to receive wakeup events from the
- +  * module.  Does not set any wakeup routing registers beyond this
- +  * point - if the module is to wake up any other module or subsystem,
- +  * that must be set separately.  Called by omap_device code.  Returns
- +  * -EINVAL on error or 0 upon success.
- +  */
- + int omap_hwmod_enable_wakeup(struct omap_hwmod *oh)
- + {
- + 	unsigned long flags;
- + 	u32 v;
- + 
- + 	if (!oh->class->sysc ||
- + 	    !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP))
- + 		return -EINVAL;
- + 
- + 	spin_lock_irqsave(&oh->_lock, flags);
- + 	v = oh->_sysc_cache;
- + 	_enable_wakeup(oh, &v);
- + 	_write_sysconfig(v, oh);
- + 	_set_idle_ioring_wakeup(oh, true);
- + 	spin_unlock_irqrestore(&oh->_lock, flags);
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * omap_hwmod_disable_wakeup - prevent device from waking the system
- +  * @oh: struct omap_hwmod *
- +  *
- +  * Clears the module OCP socket ENAWAKEUP bit to prevent the module
- +  * from sending wakeups to the PRCM.  Eventually this should clear
- +  * PRCM wakeup registers to cause the PRCM to ignore wakeup events
- +  * from the module.  Does not set any wakeup routing registers beyond
- +  * this point - if the module is to wake up any other module or
- +  * subsystem, that must be set separately.  Called by omap_device
- +  * code.  Returns -EINVAL on error or 0 upon success.
- +  */
- + int omap_hwmod_disable_wakeup(struct omap_hwmod *oh)
- + {
- + 	unsigned long flags;
- + 	u32 v;
- + 
- + 	if (!oh->class->sysc ||
- + 	    !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP))
- + 		return -EINVAL;
- + 
- + 	spin_lock_irqsave(&oh->_lock, flags);
- + 	v = oh->_sysc_cache;
- + 	_disable_wakeup(oh, &v);
- + 	_write_sysconfig(v, oh);
- + 	_set_idle_ioring_wakeup(oh, false);
- + 	spin_unlock_irqrestore(&oh->_lock, flags);
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * omap_hwmod_assert_hardreset - assert the HW reset line of submodules
- +  * contained in the hwmod module.
- +  * @oh: struct omap_hwmod *
- +  * @name: name of the reset line to lookup and assert
- +  *
- +  * Some IP like dsp, ipu or iva contain processor that require
- +  * an HW reset line to be assert / deassert in order to enable fully
- +  * the IP.  Returns -EINVAL if @oh is null or if the operation is not
- +  * yet supported on this OMAP; otherwise, passes along the return value
- +  * from _assert_hardreset().
- +  */
- + int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name)
- + {
- + 	int ret;
- + 	unsigned long flags;
- + 
- + 	if (!oh)
- + 		return -EINVAL;
- + 
- + 	spin_lock_irqsave(&oh->_lock, flags);
- + 	ret = _assert_hardreset(oh, name);
- + 	spin_unlock_irqrestore(&oh->_lock, flags);
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * omap_hwmod_deassert_hardreset - deassert the HW reset line of submodules
- +  * contained in the hwmod module.
- +  * @oh: struct omap_hwmod *
- +  * @name: name of the reset line to look up and deassert
- +  *
- +  * Some IP like dsp, ipu or iva contain processor that require
- +  * an HW reset line to be assert / deassert in order to enable fully
- +  * the IP.  Returns -EINVAL if @oh is null or if the operation is not
- +  * yet supported on this OMAP; otherwise, passes along the return value
- +  * from _deassert_hardreset().
- +  */
- + int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name)
- + {
- + 	int ret;
- + 	unsigned long flags;
- + 
- + 	if (!oh)
- + 		return -EINVAL;
- + 
- + 	spin_lock_irqsave(&oh->_lock, flags);
- + 	ret = _deassert_hardreset(oh, name);
- + 	spin_unlock_irqrestore(&oh->_lock, flags);
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * omap_hwmod_read_hardreset - read the HW reset line state of submodules
- +  * contained in the hwmod module
- +  * @oh: struct omap_hwmod *
- +  * @name: name of the reset line to look up and read
- +  *
- +  * Return the current state of the hwmod @oh's reset line named @name:
- +  * returns -EINVAL upon parameter error or if this operation
- +  * is unsupported on the current OMAP; otherwise, passes along the return
- +  * value from _read_hardreset().
- +  */
- + int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name)
- + {
- + 	int ret;
- + 	unsigned long flags;
- + 
- + 	if (!oh)
- + 		return -EINVAL;
- + 
- + 	spin_lock_irqsave(&oh->_lock, flags);
- + 	ret = _read_hardreset(oh, name);
- + 	spin_unlock_irqrestore(&oh->_lock, flags);
- + 
- + 	return ret;
- + }
- + 
- + 
- + /**
- +  * omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname
- +  * @classname: struct omap_hwmod_class name to search for
- +  * @fn: callback function pointer to call for each hwmod in class @classname
- +  * @user: arbitrary context data to pass to the callback function
- +  *
- +  * For each omap_hwmod of class @classname, call @fn.
- +  * If the callback function returns something other than
- +  * zero, the iterator is terminated, and the callback function's return
- +  * value is passed back to the caller.  Returns 0 upon success, -EINVAL
- +  * if @classname or @fn are NULL, or passes back the error code from @fn.
- +  */
- + int omap_hwmod_for_each_by_class(const char *classname,
- + 				 int (*fn)(struct omap_hwmod *oh,
- + 					   void *user),
- + 				 void *user)
- + {
- + 	struct omap_hwmod *temp_oh;
- + 	int ret = 0;
- + 
- + 	if (!classname || !fn)
- + 		return -EINVAL;
- + 
- + 	pr_debug("omap_hwmod: %s: looking for modules of class %s\n",
- + 		 __func__, classname);
- + 
- + 	list_for_each_entry(temp_oh, &omap_hwmod_list, node) {
- + 		if (!strcmp(temp_oh->class->name, classname)) {
- + 			pr_debug("omap_hwmod: %s: %s: calling callback fn\n",
- + 				 __func__, temp_oh->name);
- + 			ret = (*fn)(temp_oh, user);
- + 			if (ret)
- + 				break;
- + 		}
- + 	}
- + 
- + 	if (ret)
- + 		pr_debug("omap_hwmod: %s: iterator terminated early: %d\n",
- + 			 __func__, ret);
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * omap_hwmod_set_postsetup_state - set the post-_setup() state for this hwmod
- +  * @oh: struct omap_hwmod *
- +  * @state: state that _setup() should leave the hwmod in
- +  *
- +  * Sets the hwmod state that @oh will enter at the end of _setup()
- +  * (called by omap_hwmod_setup_*()).  Only valid to call between
- +  * calling omap_hwmod_register() and omap_hwmod_setup_*().  Returns
- +  * 0 upon success or -EINVAL if there is a problem with the arguments
- +  * or if the hwmod is in the wrong state.
- +  */
- + int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state)
- + {
- + 	int ret;
- + 	unsigned long flags;
- + 
- + 	if (!oh)
- + 		return -EINVAL;
- + 
- + 	if (state != _HWMOD_STATE_DISABLED &&
- + 	    state != _HWMOD_STATE_ENABLED &&
- + 	    state != _HWMOD_STATE_IDLE)
- + 		return -EINVAL;
- + 
- + 	spin_lock_irqsave(&oh->_lock, flags);
- + 
- + 	if (oh->_state != _HWMOD_STATE_REGISTERED) {
- + 		ret = -EINVAL;
- + 		goto ohsps_unlock;
- + 	}
- + 
- + 	oh->_postsetup_state = state;
- + 	ret = 0;
- + 
- + ohsps_unlock:
- + 	spin_unlock_irqrestore(&oh->_lock, flags);
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * omap_hwmod_get_context_loss_count - get lost context count
- +  * @oh: struct omap_hwmod *
- +  *
- +  * Query the powerdomain of of @oh to get the context loss
- +  * count for this device.
- +  *
- +  * Returns the context loss count of the powerdomain assocated with @oh
- +  * upon success, or zero if no powerdomain exists for @oh.
- +  */
- + int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh)
- + {
- + 	struct powerdomain *pwrdm;
- + 	int ret = 0;
- + 
- + 	pwrdm = omap_hwmod_get_pwrdm(oh);
- + 	if (pwrdm)
- + 		ret = pwrdm_get_context_loss_count(pwrdm);
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * omap_hwmod_no_setup_reset - prevent a hwmod from being reset upon setup
- +  * @oh: struct omap_hwmod *
- +  *
- +  * Prevent the hwmod @oh from being reset during the setup process.
- +  * Intended for use by board-*.c files on boards with devices that
- +  * cannot tolerate being reset.  Must be called before the hwmod has
- +  * been set up.  Returns 0 upon success or negative error code upon
- +  * failure.
- +  */
- + int omap_hwmod_no_setup_reset(struct omap_hwmod *oh)
- + {
- + 	if (!oh)
- + 		return -EINVAL;
- + 
- + 	if (oh->_state != _HWMOD_STATE_REGISTERED) {
- + 		pr_err("omap_hwmod: %s: cannot prevent setup reset; in wrong state\n",
- + 			oh->name);
- + 		return -EINVAL;
- + 	}
- + 
- + 	oh->flags |= HWMOD_INIT_NO_RESET;
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * omap_hwmod_pad_route_irq - route an I/O pad wakeup to a particular MPU IRQ
- +  * @oh: struct omap_hwmod * containing hwmod mux entries
- +  * @pad_idx: array index in oh->mux of the hwmod mux entry to route wakeup
- +  * @irq_idx: the hwmod mpu_irqs array index of the IRQ to trigger on wakeup
- +  *
- +  * When an I/O pad wakeup arrives for the dynamic or wakeup hwmod mux
- +  * entry number @pad_idx for the hwmod @oh, trigger the interrupt
- +  * service routine for the hwmod's mpu_irqs array index @irq_idx.  If
- +  * this function is not called for a given pad_idx, then the ISR
- +  * associated with @oh's first MPU IRQ will be triggered when an I/O
- +  * pad wakeup occurs on that pad.  Note that @pad_idx is the index of
- +  * the _dynamic or wakeup_ entry: if there are other entries not
- +  * marked with OMAP_DEVICE_PAD_WAKEUP or OMAP_DEVICE_PAD_REMUX, these
- +  * entries are NOT COUNTED in the dynamic pad index.  This function
- +  * must be called separately for each pad that requires its interrupt
- +  * to be re-routed this way.  Returns -EINVAL if there is an argument
- +  * problem or if @oh does not have hwmod mux entries or MPU IRQs;
- +  * returns -ENOMEM if memory cannot be allocated; or 0 upon success.
- +  *
- +  * XXX This function interface is fragile.  Rather than using array
- +  * indexes, which are subject to unpredictable change, it should be
- +  * using hwmod IRQ names, and some other stable key for the hwmod mux
- +  * pad records.
- +  */
- + int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx)
- + {
- + 	int nr_irqs;
- + 
- + 	might_sleep();
- + 
- + 	if (!oh || !oh->mux || !oh->mpu_irqs || pad_idx < 0 ||
- + 	    pad_idx >= oh->mux->nr_pads_dynamic)
- + 		return -EINVAL;
- + 
- + 	/* Check the number of available mpu_irqs */
- + 	for (nr_irqs = 0; oh->mpu_irqs[nr_irqs].irq >= 0; nr_irqs++)
- + 		;
- + 
- + 	if (irq_idx >= nr_irqs)
- + 		return -EINVAL;
- + 
- + 	if (!oh->mux->irqs) {
- + 		/* XXX What frees this? */
- + 		oh->mux->irqs = kzalloc(sizeof(int) * oh->mux->nr_pads_dynamic,
- + 			GFP_KERNEL);
- + 		if (!oh->mux->irqs)
- + 			return -ENOMEM;
- + 	}
- + 	oh->mux->irqs[pad_idx] = irq_idx;
- + 
- + 	return 0;
- + }
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_hwmod_common_data.c linux-3.2.1/arch/arm/mach-ckb_3352/omap_hwmod_common_data.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_hwmod_common_data.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/omap_hwmod_common_data.c	2014-05-15 13:25:13.954556406 +0900
- ***************
- *** 0 ****
- --- 1,77 ----
- + /*
- +  * omap_hwmod common data structures
- +  *
- +  * Copyright (C) 2010 Texas Instruments, Inc.
- +  * Thara Gopinath <thara@ti.com>
- +  * Benoît Cousson
- +  *
- +  * Copyright (C) 2010 Nokia Corporation
- +  * Paul Walmsley
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  *
- +  * This data/structures are to be used while defining OMAP on-chip module
- +  * data and their integration with other OMAP modules and Linux.
- +  */
- + 
- + #include <plat/omap_hwmod.h>
- + 
- + #include "omap_hwmod_common_data.h"
- + 
- + /**
- +  * struct omap_hwmod_sysc_type1 - TYPE1 sysconfig scheme.
- +  *
- +  * To be used by hwmod structure to specify the sysconfig offsets
- +  * if the device ip is compliant with the original PRCM protocol
- +  * defined for OMAP2420.
- +  */
- + struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1 = {
- + 	.midle_shift	= SYSC_TYPE1_MIDLEMODE_SHIFT,
- + 	.clkact_shift	= SYSC_TYPE1_CLOCKACTIVITY_SHIFT,
- + 	.sidle_shift	= SYSC_TYPE1_SIDLEMODE_SHIFT,
- + 	.enwkup_shift	= SYSC_TYPE1_ENAWAKEUP_SHIFT,
- + 	.srst_shift	= SYSC_TYPE1_SOFTRESET_SHIFT,
- + 	.autoidle_shift	= SYSC_TYPE1_AUTOIDLE_SHIFT,
- + };
- + 
- + /**
- +  * struct omap_hwmod_sysc_type2 - TYPE2 sysconfig scheme.
- +  *
- +  * To be used by hwmod structure to specify the sysconfig offsets if the
- +  * device ip is compliant with the new PRCM protocol defined for new
- +  * OMAP4 IPs.
- +  */
- + struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2 = {
- + 	.midle_shift	= SYSC_TYPE2_MIDLEMODE_SHIFT,
- + 	.sidle_shift	= SYSC_TYPE2_SIDLEMODE_SHIFT,
- + 	.srst_shift	= SYSC_TYPE2_SOFTRESET_SHIFT,
- + };
- + 
- + /**
- +  * struct omap_hwmod_sysc_type3 - TYPE3 sysconfig scheme.
- +  * Used by some IPs on AM33xx
- +  */
- + struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3 = {
- + 	.midle_shift	= SYSC_TYPE3_MIDLEMODE_SHIFT,
- + 	.sidle_shift	= SYSC_TYPE3_SIDLEMODE_SHIFT,
- + };
- + 
- + /**
- +  * struct omap_hwmod_sysc_type4 - TYPE4 sysconfig scheme.
- +  * Used by some IPs on AM33xx
- +  */
- + struct omap_hwmod_sysc_fields omap_hwmod_sysc_type4 = {
- + 	.midle_shift	= SYSC_TYPE4_MIDLEMODE_SHIFT,
- + 	.clkact_shift	= SYSC_TYPE4_CLOCKACTIVITY_SHIFT,
- + 	.sidle_shift	= SYSC_TYPE4_SIDLEMODE_SHIFT,
- + 	.enwkup_shift	= SYSC_TYPE4_ENAWAKEUP_SHIFT,
- + 	.srst_shift	= SYSC_TYPE4_SOFTRESET_SHIFT,
- + 	.autoidle_shift	= SYSC_TYPE4_AUTOIDLE_SHIFT,
- + };
- + 
- + struct omap_dss_dispc_dev_attr omap2_3_dss_dispc_dev_attr = {
- + 	.manager_count		= 2,
- + 	.has_framedonetv_irq	= 0
- + };
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_hwmod_common_data.h linux-3.2.1/arch/arm/mach-ckb_3352/omap_hwmod_common_data.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_hwmod_common_data.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/omap_hwmod_common_data.h	2014-05-15 13:25:13.958819078 +0900
- ***************
- *** 0 ****
- --- 1,118 ----
- + /*
- +  * omap_hwmod_common_data.h - OMAP hwmod common macros and declarations
- +  *
- +  * Copyright (C) 2010-2011 Nokia Corporation
- +  * Paul Walmsley
- +  *
- +  * Copyright (C) 2010-2011 Texas Instruments, Inc.
- +  * Benoît Cousson
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + #ifndef __ARCH_ARM_MACH_OMAP2_OMAP_HWMOD_COMMON_DATA_H
- + #define __ARCH_ARM_MACH_OMAP2_OMAP_HWMOD_COMMON_DATA_H
- + 
- + #include <plat/omap_hwmod.h>
- + 
- + #include "display.h"
- + 
- + /* Common address space across OMAP2xxx */
- + extern struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[];
- + extern struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[];
- + extern struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[];
- + extern struct omap_hwmod_addr_space omap2xxx_timer2_addrs[];
- + extern struct omap_hwmod_addr_space omap2xxx_timer3_addrs[];
- + extern struct omap_hwmod_addr_space omap2xxx_timer4_addrs[];
- + extern struct omap_hwmod_addr_space omap2xxx_timer5_addrs[];
- + extern struct omap_hwmod_addr_space omap2xxx_timer6_addrs[];
- + extern struct omap_hwmod_addr_space omap2xxx_timer7_addrs[];
- + extern struct omap_hwmod_addr_space omap2xxx_timer8_addrs[];
- + extern struct omap_hwmod_addr_space omap2xxx_timer9_addrs[];
- + extern struct omap_hwmod_addr_space omap2xxx_timer12_addrs[];
- + extern struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[];
- + 
- + /* Common address space across OMAP2xxx/3xxx */
- + extern struct omap_hwmod_addr_space omap2_i2c1_addr_space[];
- + extern struct omap_hwmod_addr_space omap2_i2c2_addr_space[];
- + extern struct omap_hwmod_addr_space omap2_dss_addrs[];
- + extern struct omap_hwmod_addr_space omap2_dss_dispc_addrs[];
- + extern struct omap_hwmod_addr_space omap2_dss_rfbi_addrs[];
- + extern struct omap_hwmod_addr_space omap2_dss_venc_addrs[];
- + extern struct omap_hwmod_addr_space omap2_timer10_addrs[];
- + extern struct omap_hwmod_addr_space omap2_timer11_addrs[];
- + extern struct omap_hwmod_addr_space omap2430_mmc1_addr_space[];
- + extern struct omap_hwmod_addr_space omap2430_mmc2_addr_space[];
- + extern struct omap_hwmod_addr_space omap2_mcspi1_addr_space[];
- + extern struct omap_hwmod_addr_space omap2_mcspi2_addr_space[];
- + extern struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[];
- + extern struct omap_hwmod_addr_space omap2_dma_system_addrs[];
- + extern struct omap_hwmod_addr_space omap2_mailbox_addrs[];
- + extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[];
- + 
- + /* Common IP block data across OMAP2xxx */
- + extern struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[];
- + extern struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[];
- + 
- + /* Common IP block data */
- + extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[];
- + extern struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[];
- + extern struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[];
- + extern struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[];
- + extern struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[];
- + extern struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[];
- + extern struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[];
- + extern struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[];
- + extern struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[];
- + 
- + /* Common IP block data on OMAP2430/OMAP3 */
- + extern struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[];
- + 
- + /* Common IP block data across OMAP2/3 */
- + extern struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[];
- + extern struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[];
- + extern struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[];
- + extern struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[];
- + extern struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[];
- + extern struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[];
- + extern struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[];
- + extern struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[];
- + extern struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[];
- + extern struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[];
- + extern struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[];
- + extern struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[];
- + extern struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[];
- + extern struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[];
- + extern struct omap_hwmod_irq_info omap2_dispc_irqs[];
- + extern struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[];
- + extern struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[];
- + extern struct omap_hwmod_irq_info omap2_gpio1_irqs[];
- + extern struct omap_hwmod_irq_info omap2_gpio2_irqs[];
- + extern struct omap_hwmod_irq_info omap2_gpio3_irqs[];
- + extern struct omap_hwmod_irq_info omap2_gpio4_irqs[];
- + extern struct omap_hwmod_irq_info omap2_dma_system_irqs[];
- + extern struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[];
- + extern struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[];
- + 
- + /* OMAP hwmod classes - forward declarations */
- + extern struct omap_hwmod_class l3_hwmod_class;
- + extern struct omap_hwmod_class l4_hwmod_class;
- + extern struct omap_hwmod_class mpu_hwmod_class;
- + extern struct omap_hwmod_class iva_hwmod_class;
- + extern struct omap_hwmod_class omap2_uart_class;
- + extern struct omap_hwmod_class omap2_dss_hwmod_class;
- + extern struct omap_hwmod_class omap2_dispc_hwmod_class;
- + extern struct omap_hwmod_class omap2_rfbi_hwmod_class;
- + extern struct omap_hwmod_class omap2_venc_hwmod_class;
- + 
- + extern struct omap_hwmod_class omap2xxx_timer_hwmod_class;
- + extern struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class;
- + extern struct omap_hwmod_class omap2xxx_gpio_hwmod_class;
- + extern struct omap_hwmod_class omap2xxx_dma_hwmod_class;
- + extern struct omap_hwmod_class omap2xxx_mailbox_hwmod_class;
- + extern struct omap_hwmod_class omap2xxx_mcspi_class;
- + 
- + extern struct omap_dss_dispc_dev_attr omap2_3_dss_dispc_dev_attr;
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_l3_smx.c linux-3.2.1/arch/arm/mach-ckb_3352/omap_l3_smx.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_l3_smx.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/omap_l3_smx.c	2014-05-15 13:25:13.958819078 +0900
- ***************
- *** 0 ****
- --- 1,296 ----
- + /*
- +  * OMAP3XXX L3 Interconnect Driver
- +  *
- +  * Copyright (C) 2011 Texas Corporation
- +  *	Felipe Balbi <balbi@ti.com>
- +  *	Santosh Shilimkar <santosh.shilimkar@ti.com>
- +  *	Sricharan <r.sricharan@ti.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; either version 2 of the License, or
- +  * (at your option) any later version.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
- +  * USA
- +  */
- + 
- + #include <linux/kernel.h>
- + #include <linux/slab.h>
- + #include <linux/platform_device.h>
- + #include <linux/interrupt.h>
- + #include <linux/io.h>
- + #include "omap_l3_smx.h"
- + 
- + static inline u64 omap3_l3_readll(void __iomem *base, u16 reg)
- + {
- + 	return __raw_readll(base + reg);
- + }
- + 
- + static inline void omap3_l3_writell(void __iomem *base, u16 reg, u64 value)
- + {
- + 	__raw_writell(value, base + reg);
- + }
- + 
- + static inline enum omap3_l3_code omap3_l3_decode_error_code(u64 error)
- + {
- + 	return (error & 0x0f000000) >> L3_ERROR_LOG_CODE;
- + }
- + 
- + static inline u32 omap3_l3_decode_addr(u64 error_addr)
- + {
- + 	return error_addr & 0xffffffff;
- + }
- + 
- + static inline unsigned omap3_l3_decode_cmd(u64 error)
- + {
- + 	return (error & 0x07) >> L3_ERROR_LOG_CMD;
- + }
- + 
- + static inline enum omap3_l3_initiator_id omap3_l3_decode_initid(u64 error)
- + {
- + 	return (error & 0xff00) >> L3_ERROR_LOG_INITID;
- + }
- + 
- + static inline unsigned omap3_l3_decode_req_info(u64 error)
- + {
- + 	return (error >> 32) & 0xffff;
- + }
- + 
- + static char *omap3_l3_code_string(u8 code)
- + {
- + 	switch (code) {
- + 	case OMAP_L3_CODE_NOERROR:
- + 		return "No Error";
- + 	case OMAP_L3_CODE_UNSUP_CMD:
- + 		return "Unsupported Command";
- + 	case OMAP_L3_CODE_ADDR_HOLE:
- + 		return "Address Hole";
- + 	case OMAP_L3_CODE_PROTECT_VIOLATION:
- + 		return "Protection Violation";
- + 	case OMAP_L3_CODE_IN_BAND_ERR:
- + 		return "In-band Error";
- + 	case OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT:
- + 		return "Request Timeout Not Accepted";
- + 	case OMAP_L3_CODE_REQ_TOUT_NO_RESP:
- + 		return "Request Timeout, no response";
- + 	default:
- + 		return "UNKNOWN error";
- + 	}
- + }
- + 
- + static char *omap3_l3_initiator_string(u8 initid)
- + {
- + 	switch (initid) {
- + 	case OMAP_L3_LCD:
- + 		return "LCD";
- + 	case OMAP_L3_SAD2D:
- + 		return "SAD2D";
- + 	case OMAP_L3_IA_MPU_SS_1:
- + 	case OMAP_L3_IA_MPU_SS_2:
- + 	case OMAP_L3_IA_MPU_SS_3:
- + 	case OMAP_L3_IA_MPU_SS_4:
- + 	case OMAP_L3_IA_MPU_SS_5:
- + 		return "MPU";
- + 	case OMAP_L3_IA_IVA_SS_1:
- + 	case OMAP_L3_IA_IVA_SS_2:
- + 	case OMAP_L3_IA_IVA_SS_3:
- + 		return "IVA_SS";
- + 	case OMAP_L3_IA_IVA_SS_DMA_1:
- + 	case OMAP_L3_IA_IVA_SS_DMA_2:
- + 	case OMAP_L3_IA_IVA_SS_DMA_3:
- + 	case OMAP_L3_IA_IVA_SS_DMA_4:
- + 	case OMAP_L3_IA_IVA_SS_DMA_5:
- + 	case OMAP_L3_IA_IVA_SS_DMA_6:
- + 		return "IVA_SS_DMA";
- + 	case OMAP_L3_IA_SGX:
- + 		return "SGX";
- + 	case OMAP_L3_IA_CAM_1:
- + 	case OMAP_L3_IA_CAM_2:
- + 	case OMAP_L3_IA_CAM_3:
- + 		return "CAM";
- + 	case OMAP_L3_IA_DAP:
- + 		return "DAP";
- + 	case OMAP_L3_SDMA_WR_1:
- + 	case OMAP_L3_SDMA_WR_2:
- + 		return "SDMA_WR";
- + 	case OMAP_L3_SDMA_RD_1:
- + 	case OMAP_L3_SDMA_RD_2:
- + 	case OMAP_L3_SDMA_RD_3:
- + 	case OMAP_L3_SDMA_RD_4:
- + 		return "SDMA_RD";
- + 	case OMAP_L3_USBOTG:
- + 		return "USB_OTG";
- + 	case OMAP_L3_USBHOST:
- + 		return "USB_HOST";
- + 	default:
- + 		return "UNKNOWN Initiator";
- + 	}
- + }
- + 
- + /*
- +  * omap3_l3_block_irq - handles a register block's irq
- +  * @l3: struct omap3_l3 *
- +  * @base: register block base address
- +  * @error: L3_ERROR_LOG register of our block
- +  *
- +  * Called in hard-irq context. Caller should take care of locking
- +  *
- +  * OMAP36xx TRM gives, on page 2001, Figure 9-10, the Typical Error
- +  * Analysis Sequence, we are following that sequence here, please
- +  * refer to that Figure for more information on the subject.
- +  */
- + static irqreturn_t omap3_l3_block_irq(struct omap3_l3 *l3,
- + 					u64 error, int error_addr)
- + {
- + 	u8 code = omap3_l3_decode_error_code(error);
- + 	u8 initid = omap3_l3_decode_initid(error);
- + 	u8 multi = error & L3_ERROR_LOG_MULTI;
- + 	u32 address = omap3_l3_decode_addr(error_addr);
- + 
- + 	WARN(true, "%s seen by %s %s at address %x\n",
- + 			omap3_l3_code_string(code),
- + 			omap3_l3_initiator_string(initid),
- + 			multi ? "Multiple Errors" : "", address);
- + 
- + 	return IRQ_HANDLED;
- + }
- + 
- + static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
- + {
- + 	struct omap3_l3 *l3 = _l3;
- + 	u64 status, clear;
- + 	u64 error;
- + 	u64 error_addr;
- + 	u64 err_source = 0;
- + 	void __iomem *base;
- + 	int int_type;
- + 	irqreturn_t ret = IRQ_NONE;
- + 
- + 	int_type = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
- + 	if (!int_type) {
- + 		status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_0);
- + 		/*
- + 		 * if we have a timeout error, there's nothing we can
- + 		 * do besides rebooting the board. So let's BUG on any
- + 		 * of such errors and handle the others. timeout error
- + 		 * is severe and not expected to occur.
- + 		 */
- + 		BUG_ON(status & L3_STATUS_0_TIMEOUT_MASK);
- + 	} else {
- + 		status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_1);
- + 		/* No timeout error for debug sources */
- + 	}
- + 
- + 	/* identify the error source */
- + 	err_source = __ffs(status);
- + 
- + 	base = l3->rt + omap3_l3_bases[int_type][err_source];
- + 	error = omap3_l3_readll(base, L3_ERROR_LOG);
- + 	if (error) {
- + 		error_addr = omap3_l3_readll(base, L3_ERROR_LOG_ADDR);
- + 		ret |= omap3_l3_block_irq(l3, error, error_addr);
- + 	}
- + 
- + 	/* Clear the status register */
- + 	clear = (L3_AGENT_STATUS_CLEAR_IA << int_type) |
- + 		L3_AGENT_STATUS_CLEAR_TA;
- + 	omap3_l3_writell(base, L3_AGENT_STATUS, clear);
- + 
- + 	/* clear the error log register */
- + 	omap3_l3_writell(base, L3_ERROR_LOG, error);
- + 
- + 	return ret;
- + }
- + 
- + static int __init omap3_l3_probe(struct platform_device *pdev)
- + {
- + 	struct omap3_l3 *l3;
- + 	struct resource *res;
- + 	int ret;
- + 
- + 	l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
- + 	if (!l3)
- + 		return -ENOMEM;
- + 
- + 	platform_set_drvdata(pdev, l3);
- + 
- + 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- + 	if (!res) {
- + 		dev_err(&pdev->dev, "couldn't find resource\n");
- + 		ret = -ENODEV;
- + 		goto err0;
- + 	}
- + 	l3->rt = ioremap(res->start, resource_size(res));
- + 	if (!l3->rt) {
- + 		dev_err(&pdev->dev, "ioremap failed\n");
- + 		ret = -ENOMEM;
- + 		goto err0;
- + 	}
- + 
- + 	l3->debug_irq = platform_get_irq(pdev, 0);
- + 	ret = request_irq(l3->debug_irq, omap3_l3_app_irq,
- + 		IRQF_DISABLED | IRQF_TRIGGER_RISING,
- + 		"l3-debug-irq", l3);
- + 	if (ret) {
- + 		dev_err(&pdev->dev, "couldn't request debug irq\n");
- + 		goto err1;
- + 	}
- + 
- + 	l3->app_irq = platform_get_irq(pdev, 1);
- + 	ret = request_irq(l3->app_irq, omap3_l3_app_irq,
- + 		IRQF_DISABLED | IRQF_TRIGGER_RISING,
- + 		"l3-app-irq", l3);
- + 	if (ret) {
- + 		dev_err(&pdev->dev, "couldn't request app irq\n");
- + 		goto err2;
- + 	}
- + 
- + 	return 0;
- + 
- + err2:
- + 	free_irq(l3->debug_irq, l3);
- + err1:
- + 	iounmap(l3->rt);
- + err0:
- + 	kfree(l3);
- + 	return ret;
- + }
- + 
- + static int __exit omap3_l3_remove(struct platform_device *pdev)
- + {
- + 	struct omap3_l3         *l3 = platform_get_drvdata(pdev);
- + 
- + 	free_irq(l3->app_irq, l3);
- + 	free_irq(l3->debug_irq, l3);
- + 	iounmap(l3->rt);
- + 	kfree(l3);
- + 
- + 	return 0;
- + }
- + 
- + static struct platform_driver omap3_l3_driver = {
- + 	.remove         = __exit_p(omap3_l3_remove),
- + 	.driver         = {
- + 	.name   = "omap_l3_smx",
- + 	},
- + };
- + 
- + static int __init omap3_l3_init(void)
- + {
- + 	return platform_driver_probe(&omap3_l3_driver, omap3_l3_probe);
- + }
- + postcore_initcall_sync(omap3_l3_init);
- + 
- + static void __exit omap3_l3_exit(void)
- + {
- + 	platform_driver_unregister(&omap3_l3_driver);
- + }
- + module_exit(omap3_l3_exit);
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_l3_smx.h linux-3.2.1/arch/arm/mach-ckb_3352/omap_l3_smx.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_l3_smx.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/omap_l3_smx.h	2014-05-15 13:25:13.958819078 +0900
- ***************
- *** 0 ****
- --- 1,338 ----
- + /*
- +  * OMAP3XXX L3 Interconnect Driver header
- +  *
- +  * Copyright (C) 2011 Texas Corporation
- +  *	Felipe Balbi <balbi@ti.com>
- +  *	Santosh Shilimkar <santosh.shilimkar@ti.com>
- +  *	sricharan <r.sricharan@ti.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; either version 2 of the License, or
- +  * (at your option) any later version.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
- +  * USA
- +  */
- + #ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
- + #define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
- + 
- + /* Register definitions. All 64-bit wide */
- + #define L3_COMPONENT			0x000
- + #define L3_CORE				0x018
- + #define L3_AGENT_CONTROL		0x020
- + #define L3_AGENT_STATUS			0x028
- + #define L3_ERROR_LOG			0x058
- + 
- + #define L3_ERROR_LOG_MULTI		(1 << 31)
- + #define L3_ERROR_LOG_SECONDARY		(1 << 30)
- + 
- + #define L3_ERROR_LOG_ADDR		0x060
- + 
- + /* Register definitions for Sideband Interconnect */
- + #define L3_SI_CONTROL			0x020
- + #define L3_SI_FLAG_STATUS_0		0x510
- + 
- + static const u64 shift = 1;
- + 
- + #define L3_STATUS_0_MPUIA_BRST		(shift << 0)
- + #define L3_STATUS_0_MPUIA_RSP		(shift << 1)
- + #define L3_STATUS_0_MPUIA_INBAND	(shift << 2)
- + #define L3_STATUS_0_IVAIA_BRST		(shift << 6)
- + #define L3_STATUS_0_IVAIA_RSP		(shift << 7)
- + #define L3_STATUS_0_IVAIA_INBAND	(shift << 8)
- + #define L3_STATUS_0_SGXIA_BRST		(shift << 9)
- + #define L3_STATUS_0_SGXIA_RSP		(shift << 10)
- + #define L3_STATUS_0_SGXIA_MERROR	(shift << 11)
- + #define L3_STATUS_0_CAMIA_BRST		(shift << 12)
- + #define L3_STATUS_0_CAMIA_RSP		(shift << 13)
- + #define L3_STATUS_0_CAMIA_INBAND	(shift << 14)
- + #define L3_STATUS_0_DISPIA_BRST		(shift << 15)
- + #define L3_STATUS_0_DISPIA_RSP		(shift << 16)
- + #define L3_STATUS_0_DMARDIA_BRST	(shift << 18)
- + #define L3_STATUS_0_DMARDIA_RSP		(shift << 19)
- + #define L3_STATUS_0_DMAWRIA_BRST	(shift << 21)
- + #define L3_STATUS_0_DMAWRIA_RSP		(shift << 22)
- + #define L3_STATUS_0_USBOTGIA_BRST	(shift << 24)
- + #define L3_STATUS_0_USBOTGIA_RSP	(shift << 25)
- + #define L3_STATUS_0_USBOTGIA_INBAND	(shift << 26)
- + #define L3_STATUS_0_USBHOSTIA_BRST	(shift << 27)
- + #define L3_STATUS_0_USBHOSTIA_INBAND	(shift << 28)
- + #define L3_STATUS_0_SMSTA_REQ		(shift << 48)
- + #define L3_STATUS_0_GPMCTA_REQ		(shift << 49)
- + #define L3_STATUS_0_OCMRAMTA_REQ	(shift << 50)
- + #define L3_STATUS_0_OCMROMTA_REQ	(shift << 51)
- + #define L3_STATUS_0_IVATA_REQ		(shift << 54)
- + #define L3_STATUS_0_SGXTA_REQ		(shift << 55)
- + #define L3_STATUS_0_SGXTA_SERROR	(shift << 56)
- + #define L3_STATUS_0_GPMCTA_SERROR	(shift << 57)
- + #define L3_STATUS_0_L4CORETA_REQ	(shift << 58)
- + #define L3_STATUS_0_L4PERTA_REQ		(shift << 59)
- + #define L3_STATUS_0_L4EMUTA_REQ		(shift << 60)
- + #define L3_STATUS_0_MAD2DTA_REQ		(shift << 61)
- + 
- + #define L3_STATUS_0_TIMEOUT_MASK	(L3_STATUS_0_MPUIA_BRST		\
- + 					| L3_STATUS_0_MPUIA_RSP		\
- + 					| L3_STATUS_0_IVAIA_BRST	\
- + 					| L3_STATUS_0_IVAIA_RSP		\
- + 					| L3_STATUS_0_SGXIA_BRST	\
- + 					| L3_STATUS_0_SGXIA_RSP		\
- + 					| L3_STATUS_0_CAMIA_BRST	\
- + 					| L3_STATUS_0_CAMIA_RSP		\
- + 					| L3_STATUS_0_DISPIA_BRST	\
- + 					| L3_STATUS_0_DISPIA_RSP	\
- + 					| L3_STATUS_0_DMARDIA_BRST	\
- + 					| L3_STATUS_0_DMARDIA_RSP	\
- + 					| L3_STATUS_0_DMAWRIA_BRST	\
- + 					| L3_STATUS_0_DMAWRIA_RSP	\
- + 					| L3_STATUS_0_USBOTGIA_BRST	\
- + 					| L3_STATUS_0_USBOTGIA_RSP	\
- + 					| L3_STATUS_0_USBHOSTIA_BRST	\
- + 					| L3_STATUS_0_SMSTA_REQ		\
- + 					| L3_STATUS_0_GPMCTA_REQ	\
- + 					| L3_STATUS_0_OCMRAMTA_REQ	\
- + 					| L3_STATUS_0_OCMROMTA_REQ	\
- + 					| L3_STATUS_0_IVATA_REQ		\
- + 					| L3_STATUS_0_SGXTA_REQ		\
- + 					| L3_STATUS_0_L4CORETA_REQ	\
- + 					| L3_STATUS_0_L4PERTA_REQ	\
- + 					| L3_STATUS_0_L4EMUTA_REQ	\
- + 					| L3_STATUS_0_MAD2DTA_REQ)
- + 
- + #define L3_SI_FLAG_STATUS_1		0x530
- + 
- + #define L3_STATUS_1_MPU_DATAIA		(1 << 0)
- + #define L3_STATUS_1_DAPIA0		(1 << 3)
- + #define L3_STATUS_1_DAPIA1		(1 << 4)
- + #define L3_STATUS_1_IVAIA		(1 << 6)
- + 
- + #define L3_PM_ERROR_LOG			0x020
- + #define L3_PM_CONTROL			0x028
- + #define L3_PM_ERROR_CLEAR_SINGLE	0x030
- + #define L3_PM_ERROR_CLEAR_MULTI		0x038
- + #define L3_PM_REQ_INFO_PERMISSION(n)	(0x048 + (0x020 * n))
- + #define L3_PM_READ_PERMISSION(n)	(0x050 + (0x020 * n))
- + #define L3_PM_WRITE_PERMISSION(n)	(0x058 + (0x020 * n))
- + #define L3_PM_ADDR_MATCH(n)		(0x060 + (0x020 * n))
- + 
- + /* L3 error log bit fields. Common for IA and TA */
- + #define L3_ERROR_LOG_CODE		24
- + #define L3_ERROR_LOG_INITID		8
- + #define L3_ERROR_LOG_CMD		0
- + 
- + /* L3 agent status bit fields. */
- + #define L3_AGENT_STATUS_CLEAR_IA	0x10000000
- + #define L3_AGENT_STATUS_CLEAR_TA	0x01000000
- + 
- + #define OMAP34xx_IRQ_L3_APP		10
- + #define L3_APPLICATION_ERROR		0x0
- + #define L3_DEBUG_ERROR			0x1
- + 
- + enum omap3_l3_initiator_id {
- + 	/* LCD has 1 ID */
- + 	OMAP_L3_LCD = 29,
- + 	/* SAD2D has 1 ID */
- + 	OMAP_L3_SAD2D = 28,
- + 	/* MPU has 5 IDs */
- + 	OMAP_L3_IA_MPU_SS_1 = 27,
- + 	OMAP_L3_IA_MPU_SS_2 = 26,
- + 	OMAP_L3_IA_MPU_SS_3 = 25,
- + 	OMAP_L3_IA_MPU_SS_4 = 24,
- + 	OMAP_L3_IA_MPU_SS_5 = 23,
- + 	/* IVA2.2 SS has 3 IDs*/
- + 	OMAP_L3_IA_IVA_SS_1 = 22,
- + 	OMAP_L3_IA_IVA_SS_2 = 21,
- + 	OMAP_L3_IA_IVA_SS_3 = 20,
- + 	/* IVA 2.2 SS DMA has 6 IDS */
- + 	OMAP_L3_IA_IVA_SS_DMA_1 = 19,
- + 	OMAP_L3_IA_IVA_SS_DMA_2 = 18,
- + 	OMAP_L3_IA_IVA_SS_DMA_3 = 17,
- + 	OMAP_L3_IA_IVA_SS_DMA_4 = 16,
- + 	OMAP_L3_IA_IVA_SS_DMA_5 = 15,
- + 	OMAP_L3_IA_IVA_SS_DMA_6 = 14,
- + 	/* SGX has 1 ID */
- + 	OMAP_L3_IA_SGX = 13,
- + 	/* CAM has 3 ID */
- + 	OMAP_L3_IA_CAM_1 = 12,
- + 	OMAP_L3_IA_CAM_2 = 11,
- + 	OMAP_L3_IA_CAM_3 = 10,
- + 	/* DAP has 1 ID */
- + 	OMAP_L3_IA_DAP = 9,
- + 	/* SDMA WR has 2 IDs */
- + 	OMAP_L3_SDMA_WR_1 = 8,
- + 	OMAP_L3_SDMA_WR_2 = 7,
- + 	/* SDMA RD has 4 IDs */
- + 	OMAP_L3_SDMA_RD_1 = 6,
- + 	OMAP_L3_SDMA_RD_2 = 5,
- + 	OMAP_L3_SDMA_RD_3 = 4,
- + 	OMAP_L3_SDMA_RD_4 = 3,
- + 	/* HSUSB OTG has 1 ID */
- + 	OMAP_L3_USBOTG = 2,
- + 	/* HSUSB HOST has 1 ID */
- + 	OMAP_L3_USBHOST = 1,
- + };
- + 
- + enum omap3_l3_code {
- + 	OMAP_L3_CODE_NOERROR = 0,
- + 	OMAP_L3_CODE_UNSUP_CMD = 1,
- + 	OMAP_L3_CODE_ADDR_HOLE = 2,
- + 	OMAP_L3_CODE_PROTECT_VIOLATION = 3,
- + 	OMAP_L3_CODE_IN_BAND_ERR = 4,
- + 	/* codes 5 and 6 are reserved */
- + 	OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT = 7,
- + 	OMAP_L3_CODE_REQ_TOUT_NO_RESP = 8,
- + 	/* codes 9 - 15 are also reserved */
- + };
- + 
- + struct omap3_l3 {
- + 	struct device *dev;
- + 	struct clk *ick;
- + 
- + 	/* memory base*/
- + 	void __iomem *rt;
- + 
- + 	int debug_irq;
- + 	int app_irq;
- + 
- + 	/* true when and inband functional error occurs */
- + 	unsigned inband:1;
- + };
- + 
- + /* offsets for l3 agents in order with the Flag status register */
- + static unsigned int omap3_l3_app_bases[] = {
- + 	/* MPU IA */
- + 	0x1400,
- + 	0x1400,
- + 	0x1400,
- + 	/* RESERVED */
- + 	0,
- + 	0,
- + 	0,
- + 	/* IVA 2.2 IA */
- + 	0x1800,
- + 	0x1800,
- + 	0x1800,
- + 	/* SGX IA */
- + 	0x1c00,
- + 	0x1c00,
- + 	/* RESERVED */
- + 	0,
- + 	/* CAMERA IA */
- + 	0x5800,
- + 	0x5800,
- + 	0x5800,
- + 	/* DISPLAY IA */
- + 	0x5400,
- + 	0x5400,
- + 	/* RESERVED */
- + 	0,
- + 	/*SDMA RD IA */
- + 	0x4c00,
- + 	0x4c00,
- + 	/* RESERVED */
- + 	0,
- + 	/* SDMA WR IA */
- + 	0x5000,
- + 	0x5000,
- + 	/* RESERVED */
- + 	0,
- + 	/* USB OTG IA */
- + 	0x4400,
- + 	0x4400,
- + 	0x4400,
- + 	/* USB HOST IA */
- + 	0x4000,
- + 	0x4000,
- + 	/* RESERVED */
- + 	0,
- + 	0,
- + 	0,
- + 	0,
- + 	/* SAD2D IA */
- + 	0x3000,
- + 	0x3000,
- + 	0x3000,
- + 	/* RESERVED */
- + 	0,
- + 	0,
- + 	0,
- + 	0,
- + 	0,
- + 	0,
- + 	0,
- + 	0,
- + 	0,
- + 	0,
- + 	0,
- + 	0,
- + 	/* SMA TA */
- + 	0x2000,
- + 	/* GPMC TA */
- + 	0x2400,
- + 	/* OCM RAM TA */
- + 	0x2800,
- + 	/* OCM ROM TA */
- + 	0x2C00,
- + 	/* L4 CORE TA */
- + 	0x6800,
- + 	/* L4 PER TA */
- + 	0x6c00,
- + 	/* IVA 2.2 TA */
- + 	0x6000,
- + 	/* SGX TA */
- + 	0x6400,
- + 	/* L4 EMU TA */
- + 	0x7000,
- + 	/* GPMC TA */
- + 	0x2400,
- + 	/* L4 CORE TA */
- + 	0x6800,
- + 	/* L4 PER TA */
- + 	0x6c00,
- + 	/* L4 EMU TA */
- + 	0x7000,
- + 	/* MAD2D TA */
- + 	0x3400,
- + 	/* RESERVED */
- + 	0,
- + 	0,
- + };
- + 
- + static unsigned int omap3_l3_debug_bases[] = {
- + 	/* MPU DATA IA */
- + 	0x1400,
- + 	/* RESERVED */
- + 	0,
- + 	0,
- + 	/* DAP IA */
- + 	0x5c00,
- + 	0x5c00,
- + 	/* RESERVED */
- + 	0,
- + 	/* IVA 2.2 IA */
- + 	0x1800,
- + 	/* REST RESERVED */
- + };
- + 
- + static u32 *omap3_l3_bases[] = {
- + 	omap3_l3_app_bases,
- + 	omap3_l3_debug_bases,
- + };
- + 
- + /*
- +  * REVISIT define __raw_readll/__raw_writell here, but move them to
- +  * <asm/io.h> at some point
- +  */
- + #define __raw_writell(v, a)	(__chk_io_ptr(a), \
- + 				*(volatile u64 __force *)(a) = (v))
- + #define __raw_readll(a)		(__chk_io_ptr(a), \
- + 				*(volatile u64 __force *)(a))
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_opp_data.h linux-3.2.1/arch/arm/mach-ckb_3352/omap_opp_data.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_opp_data.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/omap_opp_data.h	2014-05-15 13:25:13.958819078 +0900
- ***************
- *** 0 ****
- --- 1,96 ----
- + /*
- +  * OMAP SoC specific OPP Data helpers
- +  *
- +  * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/
- +  *	Nishanth Menon
- +  *	Kevin Hilman
- +  * Copyright (C) 2010 Nokia Corporation.
- +  *      Eduardo Valentin
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + #ifndef __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H
- + #define __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H
- + 
- + #include <plat/omap_hwmod.h>
- + 
- + #include "voltage.h"
- + 
- + /*
- +  * *BIG FAT WARNING*:
- +  * USE the following ONLY in opp data initialization common to an SoC.
- +  * DO NOT USE these in board files/pm core etc.
- +  */
- + 
- + /**
- +  * struct omap_opp_def - OMAP OPP Definition
- +  * @hwmod_name:	Name of the hwmod for this domain
- +  * @freq:	Frequency in hertz corresponding to this OPP
- +  * @u_volt:	Nominal voltage in microvolts corresponding to this OPP
- +  * @default_available:	True/false - is this OPP available by default
- +  *
- +  * OMAP SOCs have a standard set of tuples consisting of frequency and voltage
- +  * pairs that the device will support per voltage domain. This is called
- +  * Operating Points or OPP. The actual definitions of OMAP Operating Points
- +  * varies over silicon within the same family of devices. For a specific
- +  * domain, you can have a set of {frequency, voltage} pairs and this is denoted
- +  * by an array of omap_opp_def. As the kernel boots and more information is
- +  * available, a set of these are activated based on the precise nature of
- +  * device the kernel boots up on. It is interesting to remember that each IP
- +  * which belongs to a voltage domain may define their own set of OPPs on top
- +  * of this - but this is handled by the appropriate driver.
- +  */
- + struct omap_opp_def {
- + 	char *hwmod_name;
- + 
- + 	unsigned long freq;
- + 	unsigned long u_volt;
- + 
- + 	bool default_available;
- + };
- + 
- + /*
- +  * Initialization wrapper used to define an OPP for OMAP variants.
- +  */
- + #define OPP_INITIALIZER(_hwmod_name, _enabled, _freq, _uv)	\
- + {								\
- + 	.hwmod_name	= _hwmod_name,				\
- + 	.default_available	= _enabled,			\
- + 	.freq		= _freq,				\
- + 	.u_volt		= _uv,					\
- + }
- + 
- + /*
- +  * Initialization wrapper used to define SmartReflex process data
- +  * XXX Is this needed?  Just use C99 initializers in data files?
- +  */
- + #define VOLT_DATA_DEFINE(_v_nom, _efuse_offs, _errminlimit, _errgain)  \
- + {								       \
- + 	.volt_nominal	= _v_nom,				       \
- + 	.sr_efuse_offs	= _efuse_offs,				       \
- + 	.sr_errminlimit = _errminlimit,				       \
- + 	.vp_errgain	= _errgain				       \
- + }
- + 
- + /* Use this to initialize the default table */
- + extern int __init omap_init_opp_table(struct omap_opp_def *opp_def,
- + 		u32 opp_def_size);
- + 
- + 
- + extern struct omap_volt_data omap34xx_vddmpu_volt_data[];
- + extern struct omap_volt_data omap34xx_vddcore_volt_data[];
- + extern struct omap_volt_data omap36xx_vddmpu_volt_data[];
- + extern struct omap_volt_data omap36xx_vddcore_volt_data[];
- + 
- + extern struct omap_volt_data omap44xx_vdd_mpu_volt_data[];
- + extern struct omap_volt_data omap44xx_vdd_iva_volt_data[];
- + extern struct omap_volt_data omap44xx_vdd_core_volt_data[];
- + 
- + #endif		/* __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H */
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_phy_internal.c linux-3.2.1/arch/arm/mach-ckb_3352/omap_phy_internal.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_phy_internal.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/omap_phy_internal.c	2014-05-15 13:25:13.958819078 +0900
- ***************
- *** 0 ****
- --- 1,79 ----
- + /*
- +   * This file configures the internal USB PHY in OMAP4430. Used
- +   * with TWL6030 transceiver and MUSB on OMAP4430.
- +   *
- +   * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
- +   * This program is free software; you can redistribute it and/or modify
- +   * it under the terms of the GNU General Public License as published by
- +   * the Free Software Foundation; either version 2 of the License, or
- +   * (at your option) any later version.
- +   *
- +   * Author: Hema HK <hemahk@ti.com>
- +   *
- +   * This program is distributed in the hope that it will be useful,
- +   * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +   * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +   * GNU General Public License for more details.
- +   *
- +   * You should have received a copy of the GNU General Public License
- +   * along with this program; if not, write to the Free Software
- +   * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- +   *
- +   */
- + 
- + #include <linux/types.h>
- + #include <linux/delay.h>
- + #include <linux/clk.h>
- + #include <linux/io.h>
- + #include <linux/err.h>
- + #include <linux/usb.h>
- + 
- + #include <plat/usb.h>
- + #include <plat/am33xx.h>
- + #include "control.h"
- + 
- + /* OMAP control module register for UTMI PHY */
- + #define CONTROL_DEV_CONF		0x300
- + #define PHY_PD				0x1
- + 
- + #define USBOTGHS_CONTROL		0x33c
- + #define	AVALID				BIT(0)
- + #define	BVALID				BIT(1)
- + #define	VBUSVALID			BIT(2)
- + #define	SESSEND				BIT(3)
- + #define	IDDIG				BIT(4)
- + 
- + void ti81xx_musb_phy_power(u8 id, u8 on , bool wkup)
- + {
- + 	void __iomem *scm_base = NULL;
- + 	u32 usbphycfg;
- + 	u32 usbwkupctrl = 0;
- + 
- + 	scm_base = ioremap(AM33XX_SCM_BASE, SZ_2K);
- + 
- + 	if (!scm_base) {
- + 		pr_err("system control module ioremap failed\n");
- + 		return;
- + 	}
- + 
- + 	usbphycfg = __raw_readl(scm_base + (id ? USBCTRL1 : USBCTRL0));
- + 	usbwkupctrl = readl(scm_base + USBWKUPCTRL);
- + 
- + 	if (on) {
- + 		usbphycfg &= ~(USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN);
- + 		usbphycfg |= (USBPHY_OTGVDET_EN | USBPHY_OTGSESSEND_EN);
- + 		usbwkupctrl = AM33XX_USB_WKUP_CTRL_DISABLE;
- + 	} else {
- + 		usbphycfg |= USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN;
- + 		if (wkup)
- + 			usbwkupctrl |= id ? AM33XX_USB1_WKUP_CTRL_ENABLE :
- + 							AM33XX_USB0_WKUP_CTRL_ENABLE;
- + 		else
- + 			usbwkupctrl &= id ? ~AM33XX_USB1_WKUP_CTRL_ENABLE :
- + 							~AM33XX_USB0_WKUP_CTRL_ENABLE;
- + 	}
- + 	__raw_writel(usbphycfg, scm_base + (id ? USBCTRL1 : USBCTRL0));
- + 	writel(usbwkupctrl , scm_base + USBWKUPCTRL);
- + 
- + 	iounmap(scm_base);
- + }
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_twl.c linux-3.2.1/arch/arm/mach-ckb_3352/omap_twl.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_twl.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/omap_twl.c	2014-05-15 13:25:13.963199907 +0900
- ***************
- *** 0 ****
- --- 1,263 ----
- + /**
- +  * OMAP and TWL PMIC specific intializations.
- +  *
- +  * Copyright (C) 2010 Texas Instruments Incorporated.
- +  * Thara Gopinath
- +  * Copyright (C) 2009 Texas Instruments Incorporated.
- +  * Nishanth Menon
- +  * Copyright (C) 2009 Nokia Corporation
- +  * Paul Walmsley
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #include <linux/err.h>
- + #include <linux/io.h>
- + #include <linux/kernel.h>
- + #include <linux/i2c/twl.h>
- + 
- + #include "voltage.h"
- + 
- + #include "pm.h"
- + 
- + #define OMAP3_SRI2C_SLAVE_ADDR		0x12
- + #define OMAP3_VDD_MPU_SR_CONTROL_REG	0x00
- + #define OMAP3_VDD_CORE_SR_CONTROL_REG	0x01
- + #define OMAP3_VP_CONFIG_ERROROFFSET	0x00
- + #define OMAP3_VP_VSTEPMIN_VSTEPMIN	0x1
- + #define OMAP3_VP_VSTEPMAX_VSTEPMAX	0x04
- + #define OMAP3_VP_VLIMITTO_TIMEOUT_US	200
- + 
- + #define OMAP3430_VP1_VLIMITTO_VDDMIN	0x14
- + #define OMAP3430_VP1_VLIMITTO_VDDMAX	0x42
- + #define OMAP3430_VP2_VLIMITTO_VDDMIN	0x18
- + #define OMAP3430_VP2_VLIMITTO_VDDMAX	0x2c
- + 
- + #define OMAP3630_VP1_VLIMITTO_VDDMIN	0x18
- + #define OMAP3630_VP1_VLIMITTO_VDDMAX	0x3c
- + #define OMAP3630_VP2_VLIMITTO_VDDMIN	0x18
- + #define OMAP3630_VP2_VLIMITTO_VDDMAX	0x30
- + 
- + #define OMAP4_SRI2C_SLAVE_ADDR		0x12
- + #define OMAP4_VDD_MPU_SR_VOLT_REG	0x55
- + #define OMAP4_VDD_MPU_SR_CMD_REG	0x56
- + #define OMAP4_VDD_IVA_SR_VOLT_REG	0x5B
- + #define OMAP4_VDD_IVA_SR_CMD_REG	0x5C
- + #define OMAP4_VDD_CORE_SR_VOLT_REG	0x61
- + #define OMAP4_VDD_CORE_SR_CMD_REG	0x62
- + 
- + #define OMAP4_VP_CONFIG_ERROROFFSET	0x00
- + #define OMAP4_VP_VSTEPMIN_VSTEPMIN	0x01
- + #define OMAP4_VP_VSTEPMAX_VSTEPMAX	0x04
- + #define OMAP4_VP_VLIMITTO_TIMEOUT_US	200
- + 
- + #define OMAP4_VP_MPU_VLIMITTO_VDDMIN	0xA
- + #define OMAP4_VP_MPU_VLIMITTO_VDDMAX	0x39
- + #define OMAP4_VP_IVA_VLIMITTO_VDDMIN	0xA
- + #define OMAP4_VP_IVA_VLIMITTO_VDDMAX	0x2D
- + #define OMAP4_VP_CORE_VLIMITTO_VDDMIN	0xA
- + #define OMAP4_VP_CORE_VLIMITTO_VDDMAX	0x28
- + 
- + static bool is_offset_valid;
- + static u8 smps_offset;
- + /*
- +  * Flag to ensure Smartreflex bit in TWL
- +  * being cleared in board file is not overwritten.
- +  */
- + static bool __initdata twl_sr_enable_autoinit;
- + 
- + #define TWL4030_DCDC_GLOBAL_CFG        0x06
- + #define REG_SMPS_OFFSET         0xE0
- + #define SMARTREFLEX_ENABLE     BIT(3)
- + 
- + static unsigned long twl4030_vsel_to_uv(const u8 vsel)
- + {
- + 	return (((vsel * 125) + 6000)) * 100;
- + }
- + 
- + static u8 twl4030_uv_to_vsel(unsigned long uv)
- + {
- + 	return DIV_ROUND_UP(uv - 600000, 12500);
- + }
- + 
- + static unsigned long twl6030_vsel_to_uv(const u8 vsel)
- + {
- + 	/*
- + 	 * In TWL6030 depending on the value of SMPS_OFFSET
- + 	 * efuse register the voltage range supported in
- + 	 * standard mode can be either between 0.6V - 1.3V or
- + 	 * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
- + 	 * is programmed to all 0's where as starting from
- + 	 * TWL6030 ES1.1 the efuse is programmed to 1
- + 	 */
- + 	if (!is_offset_valid) {
- + 		twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset,
- + 				REG_SMPS_OFFSET);
- + 		is_offset_valid = true;
- + 	}
- + 
- + 	if (!vsel)
- + 		return 0;
- + 	/*
- + 	 * There is no specific formula for voltage to vsel
- + 	 * conversion above 1.3V. There are special hardcoded
- + 	 * values for voltages above 1.3V. Currently we are
- + 	 * hardcoding only for 1.35 V which is used for 1GH OPP for
- + 	 * OMAP4430.
- + 	 */
- + 	if (vsel == 0x3A)
- + 		return 1350000;
- + 
- + 	if (smps_offset & 0x8)
- + 		return ((((vsel - 1) * 1266) + 70900)) * 10;
- + 	else
- + 		return ((((vsel - 1) * 1266) + 60770)) * 10;
- + }
- + 
- + static u8 twl6030_uv_to_vsel(unsigned long uv)
- + {
- + 	/*
- + 	 * In TWL6030 depending on the value of SMPS_OFFSET
- + 	 * efuse register the voltage range supported in
- + 	 * standard mode can be either between 0.6V - 1.3V or
- + 	 * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
- + 	 * is programmed to all 0's where as starting from
- + 	 * TWL6030 ES1.1 the efuse is programmed to 1
- + 	 */
- + 	if (!is_offset_valid) {
- + 		twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset,
- + 				REG_SMPS_OFFSET);
- + 		is_offset_valid = true;
- + 	}
- + 
- + 	if (!uv)
- + 		return 0x00;
- + 	/*
- + 	 * There is no specific formula for voltage to vsel
- + 	 * conversion above 1.3V. There are special hardcoded
- + 	 * values for voltages above 1.3V. Currently we are
- + 	 * hardcoding only for 1.35 V which is used for 1GH OPP for
- + 	 * OMAP4430.
- + 	 */
- + 	if (uv > twl6030_vsel_to_uv(0x39)) {
- + 		if (uv == 1350000)
- + 			return 0x3A;
- + 		pr_err("%s:OUT OF RANGE! non mapped vsel for %ld Vs max %ld\n",
- + 			__func__, uv, twl6030_vsel_to_uv(0x39));
- + 		return 0x3A;
- + 	}
- + 
- + 	if (smps_offset & 0x8)
- + 		return DIV_ROUND_UP(uv - 709000, 12660) + 1;
- + 	else
- + 		return DIV_ROUND_UP(uv - 607700, 12660) + 1;
- + }
- + 
- + static struct omap_voltdm_pmic omap3_mpu_pmic = {
- + 	.slew_rate		= 4000,
- + 	.step_size		= 12500,
- + 	.on_volt		= 1200000,
- + 	.onlp_volt		= 1000000,
- + 	.ret_volt		= 975000,
- + 	.off_volt		= 600000,
- + 	.volt_setup_time	= 0xfff,
- + 	.vp_erroroffset		= OMAP3_VP_CONFIG_ERROROFFSET,
- + 	.vp_vstepmin		= OMAP3_VP_VSTEPMIN_VSTEPMIN,
- + 	.vp_vstepmax		= OMAP3_VP_VSTEPMAX_VSTEPMAX,
- + 	.vp_vddmin		= OMAP3430_VP1_VLIMITTO_VDDMIN,
- + 	.vp_vddmax		= OMAP3430_VP1_VLIMITTO_VDDMAX,
- + 	.vp_timeout_us		= OMAP3_VP_VLIMITTO_TIMEOUT_US,
- + 	.i2c_slave_addr		= OMAP3_SRI2C_SLAVE_ADDR,
- + 	.volt_reg_addr		= OMAP3_VDD_MPU_SR_CONTROL_REG,
- + 	.i2c_high_speed		= true,
- + 	.vsel_to_uv		= twl4030_vsel_to_uv,
- + 	.uv_to_vsel		= twl4030_uv_to_vsel,
- + };
- + 
- + static struct omap_voltdm_pmic omap3_core_pmic = {
- + 	.slew_rate		= 4000,
- + 	.step_size		= 12500,
- + 	.on_volt                = 1200000,
- + 	.onlp_volt              = 1000000,
- + 	.ret_volt               = 975000,
- + 	.off_volt               = 600000,
- + 	.volt_setup_time        = 0xfff,
- + 	.vp_erroroffset		= OMAP3_VP_CONFIG_ERROROFFSET,
- + 	.vp_vstepmin		= OMAP3_VP_VSTEPMIN_VSTEPMIN,
- + 	.vp_vstepmax		= OMAP3_VP_VSTEPMAX_VSTEPMAX,
- + 	.vp_vddmin		= OMAP3430_VP2_VLIMITTO_VDDMIN,
- + 	.vp_vddmax		= OMAP3430_VP2_VLIMITTO_VDDMAX,
- + 	.vp_timeout_us		= OMAP3_VP_VLIMITTO_TIMEOUT_US,
- + 	.i2c_slave_addr		= OMAP3_SRI2C_SLAVE_ADDR,
- + 	.volt_reg_addr		= OMAP3_VDD_CORE_SR_CONTROL_REG,
- + 	.i2c_high_speed		= true,
- + 	.vsel_to_uv		= twl4030_vsel_to_uv,
- + 	.uv_to_vsel		= twl4030_uv_to_vsel,
- + };
- + 
- + static struct omap_voltdm_pmic omap4_mpu_pmic = {
- + 	.slew_rate		= 4000,
- + 	.step_size		= 12660,
- + 	.on_volt		= 1375000,
- + 	.onlp_volt		= 1375000,
- + 	.ret_volt		= 830000,
- + 	.off_volt		= 0,
- + 	.volt_setup_time	= 0,
- + 	.vp_erroroffset		= OMAP4_VP_CONFIG_ERROROFFSET,
- + 	.vp_vstepmin		= OMAP4_VP_VSTEPMIN_VSTEPMIN,
- + 	.vp_vstepmax		= OMAP4_VP_VSTEPMAX_VSTEPMAX,
- + 	.vp_vddmin		= OMAP4_VP_MPU_VLIMITTO_VDDMIN,
- + 	.vp_vddmax		= OMAP4_VP_MPU_VLIMITTO_VDDMAX,
- + 	.vp_timeout_us		= OMAP4_VP_VLIMITTO_TIMEOUT_US,
- + 	.i2c_slave_addr		= OMAP4_SRI2C_SLAVE_ADDR,
- + 	.volt_reg_addr		= OMAP4_VDD_MPU_SR_VOLT_REG,
- + 	.cmd_reg_addr		= OMAP4_VDD_MPU_SR_CMD_REG,
- + 	.i2c_high_speed		= true,
- + 	.vsel_to_uv		= twl6030_vsel_to_uv,
- + 	.uv_to_vsel		= twl6030_uv_to_vsel,
- + };
- + 
- + static struct omap_voltdm_pmic omap4_iva_pmic = {
- + 	.slew_rate		= 4000,
- + 	.step_size		= 12660,
- + 	.on_volt		= 1188000,
- + 	.onlp_volt		= 1188000,
- + 	.ret_volt		= 830000,
- + 	.off_volt		= 0,
- + 	.volt_setup_time	= 0,
- + 	.vp_erroroffset		= OMAP4_VP_CONFIG_ERROROFFSET,
- + 	.vp_vstepmin		= OMAP4_VP_VSTEPMIN_VSTEPMIN,
- + 	.vp_vstepmax		= OMAP4_VP_VSTEPMAX_VSTEPMAX,
- + 	.vp_vddmin		= OMAP4_VP_IVA_VLIMITTO_VDDMIN,
- + 	.vp_vddmax		= OMAP4_VP_IVA_VLIMITTO_VDDMAX,
- + 	.vp_timeout_us		= OMAP4_VP_VLIMITTO_TIMEOUT_US,
- + 	.i2c_slave_addr		= OMAP4_SRI2C_SLAVE_ADDR,
- + 	.volt_reg_addr		= OMAP4_VDD_IVA_SR_VOLT_REG,
- + 	.cmd_reg_addr		= OMAP4_VDD_IVA_SR_CMD_REG,
- + 	.i2c_high_speed		= true,
- + 	.vsel_to_uv		= twl6030_vsel_to_uv,
- + 	.uv_to_vsel		= twl6030_uv_to_vsel,
- + };
- + 
- + static struct omap_voltdm_pmic omap4_core_pmic = {
- + 	.slew_rate		= 4000,
- + 	.step_size		= 12660,
- + 	.on_volt		= 1200000,
- + 	.onlp_volt		= 1200000,
- + 	.ret_volt		= 830000,
- + 	.off_volt		= 0,
- + 	.volt_setup_time	= 0,
- + 	.vp_erroroffset		= OMAP4_VP_CONFIG_ERROROFFSET,
- + 	.vp_vstepmin		= OMAP4_VP_VSTEPMIN_VSTEPMIN,
- + 	.vp_vstepmax		= OMAP4_VP_VSTEPMAX_VSTEPMAX,
- + 	.vp_vddmin		= OMAP4_VP_CORE_VLIMITTO_VDDMIN,
- + 	.vp_vddmax		= OMAP4_VP_CORE_VLIMITTO_VDDMAX,
- + 	.vp_timeout_us		= OMAP4_VP_VLIMITTO_TIMEOUT_US,
- + 	.i2c_slave_addr		= OMAP4_SRI2C_SLAVE_ADDR,
- + 	.volt_reg_addr		= OMAP4_VDD_CORE_SR_VOLT_REG,
- + 	.cmd_reg_addr		= OMAP4_VDD_CORE_SR_CMD_REG,
- + 	.vsel_to_uv		= twl6030_vsel_to_uv,
- + 	.uv_to_vsel		= twl6030_uv_to_vsel,
- + };
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/opp3xxx_data.c linux-3.2.1/arch/arm/mach-ckb_3352/opp3xxx_data.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/opp3xxx_data.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/opp3xxx_data.c	2014-05-15 13:25:13.963199907 +0900
- ***************
- *** 0 ****
- --- 1,98 ----
- + /*
- +  * OMAP3 OPP table definitions.
- +  *
- +  * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/
- +  *	Nishanth Menon
- +  *	Kevin Hilman
- +  * Copyright (C) 2010-2011 Nokia Corporation.
- +  *      Eduardo Valentin
- +  *      Paul Walmsley
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + #include <linux/module.h>
- + 
- + #include <plat/cpu.h>
- + 
- + #include "control.h"
- + #include "omap_opp_data.h"
- + #include "pm.h"
- + 
- + /* 34xx */
- + 
- + /* VDD1 */
- + 
- + #define OMAP3430_VDD_MPU_OPP1_UV		975000
- + #define OMAP3430_VDD_MPU_OPP2_UV		1075000
- + #define OMAP3430_VDD_MPU_OPP3_UV		1200000
- + #define OMAP3430_VDD_MPU_OPP4_UV		1270000
- + #define OMAP3430_VDD_MPU_OPP5_UV		1350000
- + 
- + struct omap_volt_data omap34xx_vddmpu_volt_data[] = {
- + 	VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD1, 0xf4, 0x0c),
- + 	VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD1, 0xf4, 0x0c),
- + 	VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD1, 0xf9, 0x18),
- + 	VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP4_UV, OMAP343X_CONTROL_FUSE_OPP4_VDD1, 0xf9, 0x18),
- + 	VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP5_UV, OMAP343X_CONTROL_FUSE_OPP5_VDD1, 0xf9, 0x18),
- + 	VOLT_DATA_DEFINE(0, 0, 0, 0),
- + };
- + 
- + /* VDD2 */
- + 
- + #define OMAP3430_VDD_CORE_OPP1_UV		975000
- + #define OMAP3430_VDD_CORE_OPP2_UV		1050000
- + #define OMAP3430_VDD_CORE_OPP3_UV		1150000
- + 
- + struct omap_volt_data omap34xx_vddcore_volt_data[] = {
- + 	VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD2, 0xf4, 0x0c),
- + 	VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD2, 0xf4, 0x0c),
- + 	VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD2, 0xf9, 0x18),
- + 	VOLT_DATA_DEFINE(0, 0, 0, 0),
- + };
- + 
- + /* 36xx */
- + 
- + /*
- +  * Errata 1.0.15: OPP50 Operation on MPU Domain is Not Supported.
- +  *
- +  * To minimize power consumption, the ARM Cortex-A8 may be operated at
- +  * the lower frequency defined by OPP50, but the respective voltage
- +  * domain VDD_MPU must be operated as defined by OPP100. So MPU OPP50
- +  * definition is modified to 275MHz, 1.1V.
- +  */
- + #define AM33XX_VDD_MPU_OPP50_UV		1100000
- + #define AM33XX_VDD_MPU_OPP100_UV	1100000
- + #define AM33XX_VDD_MPU_OPP120_UV	1200000
- + #define AM33XX_VDD_MPU_OPPTURBO_UV	1260000
- + 
- + static struct omap_opp_def __initdata am33xx_es1_0_opp_def_list[] = {
- + 	/* MPU OPP1 - OPP50 */
- + 	OPP_INITIALIZER("mpu", true,  275000000, AM33XX_VDD_MPU_OPP50_UV),
- + 	/* MPU OPP2 - OPP100 */
- + 	OPP_INITIALIZER("mpu", true,  500000000, AM33XX_VDD_MPU_OPP100_UV),
- + 	/* MPU OPP3 - OPP120 */
- + 	OPP_INITIALIZER("mpu", true,  600000000, AM33XX_VDD_MPU_OPP120_UV),
- + 	/* MPU OPP4 - OPPTurbo */
- + 	OPP_INITIALIZER("mpu", true,  720000000, AM33XX_VDD_MPU_OPPTURBO_UV),
- + };
- + 
- + /**
- +  * omap3_opp_init() - initialize omap3 opp table
- +  */
- + int __init omap3_opp_init(void)
- + {
- + 	int r = -ENODEV;
- + 	
- + 	r = omap_init_opp_table(am33xx_es1_0_opp_def_list,
- + 			ARRAY_SIZE(am33xx_es1_0_opp_def_list));
- + 	
- + 	return r;
- + }
- + device_initcall(omap3_opp_init);
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/opp.c linux-3.2.1/arch/arm/mach-ckb_3352/opp.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/opp.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/opp.c	2014-05-15 13:25:13.963199907 +0900
- ***************
- *** 0 ****
- --- 1,93 ----
- + /*
- +  * OMAP SoC specific OPP wrapper function
- +  *
- +  * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/
- +  *	Nishanth Menon
- +  *	Kevin Hilman
- +  * Copyright (C) 2010 Nokia Corporation.
- +  *      Eduardo Valentin
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + #include <linux/module.h>
- + #include <linux/opp.h>
- + 
- + #include <plat/omap_device.h>
- + 
- + #include "omap_opp_data.h"
- + 
- + /* Temp variable to allow multiple calls */
- + static u8 __initdata omap_table_init;
- + 
- + /**
- +  * omap_init_opp_table() - Initialize opp table as per the CPU type
- +  * @opp_def:		opp default list for this silicon
- +  * @opp_def_size:	number of opp entries for this silicon
- +  *
- +  * Register the initial OPP table with the OPP library based on the CPU
- +  * type. This is meant to be used only by SoC specific registration.
- +  */
- + int __init omap_init_opp_table(struct omap_opp_def *opp_def,
- + 		u32 opp_def_size)
- + {
- + 	int i, r;
- + 
- + 	if (!opp_def || !opp_def_size) {
- + 		pr_err("%s: invalid params!\n", __func__);
- + 		return -EINVAL;
- + 	}
- + 
- + 	/*
- + 	 * Initialize only if not already initialized even if the previous
- + 	 * call failed, because, no reason we'd succeed again.
- + 	 */
- + 	if (omap_table_init)
- + 		return -EEXIST;
- + 	omap_table_init = 1;
- + 
- + 	/* Lets now register with OPP library */
- + 	for (i = 0; i < opp_def_size; i++) {
- + 		struct omap_hwmod *oh;
- + 		struct device *dev;
- + 
- + 		if (!opp_def->hwmod_name) {
- + 			pr_err("%s: NULL name of omap_hwmod, failing [%d].\n",
- + 				__func__, i);
- + 			return -EINVAL;
- + 		}
- + 		oh = omap_hwmod_lookup(opp_def->hwmod_name);
- + 		if (!oh || !oh->od) {
- + 			pr_warn("%s: no hwmod or odev for %s, [%d] "
- + 				"cannot add OPPs.\n", __func__,
- + 				opp_def->hwmod_name, i);
- + 			return -EINVAL;
- + 		}
- + 		dev = &oh->od->pdev->dev;
- + 
- + 		r = opp_add(dev, opp_def->freq, opp_def->u_volt);
- + 		if (r) {
- + 			dev_err(dev, "%s: add OPP %ld failed for %s [%d] "
- + 				"result=%d\n",
- + 			       __func__, opp_def->freq,
- + 			       opp_def->hwmod_name, i, r);
- + 		} else {
- + 			if (!opp_def->default_available)
- + 				r = opp_disable(dev, opp_def->freq);
- + 			if (r)
- + 				dev_err(dev, "%s: disable %ld failed for %s "
- + 					"[%d] result=%d\n",
- + 					__func__, opp_def->freq,
- + 					opp_def->hwmod_name, i, r);
- + 		}
- + 		opp_def++;
- + 	}
- + 
- + 	return 0;
- + }
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/pm33xx.c linux-3.2.1/arch/arm/mach-ckb_3352/pm33xx.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/pm33xx.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/pm33xx.c	2014-05-15 13:25:13.963199907 +0900
- ***************
- *** 0 ****
- --- 1,689 ----
- + /*
- +  * AM33XX Power Management Routines
- +  *
- +  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #include <linux/kernel.h>
- + #include <linux/init.h>
- + #include <linux/clk.h>
- + #include <linux/console.h>
- + #include <linux/err.h>
- + #include <linux/firmware.h>
- + #include <linux/io.h>
- + #include <linux/platform_device.h>
- + #include <linux/sched.h>
- + #include <linux/suspend.h>
- + #include <linux/completion.h>
- + #include <linux/pm_runtime.h>
- + 
- + #include <plat/prcm.h>
- + #include <plat/mailbox.h>
- + #include <plat/sram.h>
- + #include <plat/omap_hwmod.h>
- + #include <plat/omap_device.h>
- + #include <plat/emif.h>
- + 
- + #include <asm/suspend.h>
- + #include <asm/proc-fns.h>
- + #include <asm/sizes.h>
- + 
- + #include "pm.h"
- + #include "cm33xx.h"
- + #include "pm33xx.h"
- + #include "control.h"
- + #include "clockdomain.h"
- + #include "powerdomain.h"
- + 
- + void (*am33xx_do_wfi_sram)(u32 *);
- + 
- + #define DS_MODE		DS0_ID	/* DS0/1_ID */
- + #define MODULE_DISABLE	0x0
- + #define MODULE_ENABLE	0x2
- + 
- + #define GEN_PURP_EVM		0
- + #define IND_AUT_MTR_EVM		1
- + #define BEAGLE_BONE_OLD		2
- + #define BEAGLE_BONE_A3		3
- + #define EVM_SK				4
- + #define GEN_PURP_DDR3_EVM	5
- + 
- + #ifdef CONFIG_SUSPEND
- + void __iomem *ipc_regs;
- + void __iomem *m3_eoi;
- + void __iomem *m3_code;
- + u32 suspend_cfg_param_list[SUSPEND_CFG_PARAMS_END];
- + 
- + bool enable_deep_sleep = true;
- + static suspend_state_t suspend_state = PM_SUSPEND_ON;
- + 
- + static struct device *mpu_dev;
- + static struct omap_mbox *m3_mbox;
- + static struct powerdomain *cefuse_pwrdm, *gfx_pwrdm, *per_pwrdm;
- + static struct clockdomain *gfx_l3_clkdm, *gfx_l4ls_clkdm;
- + 
- + static int m3_state = M3_STATE_UNKNOWN;
- + static int m3_version = M3_VERSION_UNKNOWN;
- + 
- + static int am33xx_ipc_cmd(struct a8_wkup_m3_ipc_data *);
- + static int am33xx_verify_lp_state(int);
- + static void am33xx_m3_state_machine_reset(void);
- + 
- + static DECLARE_COMPLETION(a8_m3_sync);
- + 
- + static int am33xx_pm_prepare_late(void)
- + {
- + 	int ret = 0;
- + 
- + 	am335x_save_padconf();
- + 	am33xx_setup_pinmux_on_suspend();
- + 	am33xx_standby_setup(suspend_state);
- + 
- + 	return ret;
- + }
- + 
- + static void am33xx_pm_finish(void)
- + {
- + 	am33xx_standby_release(suspend_state);
- + 	am335x_restore_padconf();
- + }
- + 
- + static int am33xx_do_sram_idle(long unsigned int state)
- + {
- + 	am33xx_do_wfi_sram(&suspend_cfg_param_list[0]);
- + 
- + 	return 0;
- + }
- + 
- + static int am33xx_pm_suspend(void)
- + {
- + 	int state, ret = 0;
- + 
- + 	struct omap_hwmod *gpmc_oh, *usb_oh, *gpio1_oh;
- + 
- + 	usb_oh		= omap_hwmod_lookup("usb_otg_hs");
- + 	gpmc_oh		= omap_hwmod_lookup("gpmc");
- + 	gpio1_oh	= omap_hwmod_lookup("gpio1");	/* WKUP domain GPIO */
- + 
- + 	omap_hwmod_enable(usb_oh);
- + 	omap_hwmod_enable(gpmc_oh);
- + 
- + 	/*
- + 	 * Keep USB module enabled during standby
- + 	 * to enable USB remote wakeup
- + 	 * Note: This will result in hard-coding USB state
- + 	 * during standby
- + 	 */
- + 	if (suspend_state != PM_SUSPEND_STANDBY)
- + 		omap_hwmod_idle(usb_oh);
- + 
- + 	omap_hwmod_idle(gpmc_oh);
- + 
- + 	/*
- + 	 * Disable the GPIO module. This ensure that
- + 	 * only sWAKEUP interrupts to Cortex-M3 get generated
- + 	 *
- + 	 * XXX: EVM_SK uses a GPIO0 pin for VTP control
- + 	 * in suspend and hence we can't do this for EVM_SK
- + 	 * alone. The side-effect of this is that GPIO wakeup
- + 	 * might have issues. Refer to commit 672639b for the
- + 	 * details
- + 	 */
- + 	/*
- + 	 * Keep GPIO0 module enabled during standby to
- + 	 * support wakeup via GPIO0 keys.
- + 	 */
- + 	if ((suspend_cfg_param_list[EVM_ID] != EVM_SK) &&
- + 			(suspend_state != PM_SUSPEND_STANDBY))
- + 		omap_hwmod_idle(gpio1_oh);
- + 	/*
- + 	 * Update Suspend_State value to be used in sleep33xx.S to keep
- + 	 * GPIO0 module enabled during standby for EVM-SK
- + 	 */
- + 	if (suspend_state == PM_SUSPEND_STANDBY)
- + 		suspend_cfg_param_list[SUSPEND_STATE] = PM_STANDBY;
- + 	else
- + 		suspend_cfg_param_list[SUSPEND_STATE] = PM_DS0;
- + 
- + 	/*
- + 	 * Keep Touchscreen module enabled during standby
- + 	 * to enable wakeup from standby.
- + 	 */
- + 	if (suspend_state == PM_SUSPEND_STANDBY)
- + 		writel(0x2, AM33XX_CM_WKUP_ADC_TSC_CLKCTRL);
- + 
- + 	if (gfx_l3_clkdm && gfx_l4ls_clkdm) {
- + 		clkdm_sleep(gfx_l3_clkdm);
- + 		clkdm_sleep(gfx_l4ls_clkdm);
- + 	}
- + 
- + 	/* Try to put GFX to sleep */
- + 	if (gfx_pwrdm)
- + 		pwrdm_set_next_pwrst(gfx_pwrdm, PWRDM_POWER_OFF);
- + 	else
- + 		pr_err("Could not program GFX to low power state\n");
- + 
- + 	omap3_intc_suspend();
- + 
- + 	writel(0x0, AM33XX_CM_MPU_MPU_CLKCTRL);
- + 
- + 	ret = cpu_suspend(0, am33xx_do_sram_idle);
- + 
- + 	writel(0x2, AM33XX_CM_MPU_MPU_CLKCTRL);
- + 
- + 	if (gfx_pwrdm) {
- + 		state = pwrdm_read_pwrst(gfx_pwrdm);
- + 		if (state != PWRDM_POWER_OFF)
- + 			pr_err("GFX domain did not transition to low power state\n");
- + 		else
- + 			pr_info("GFX domain entered low power state\n");
- + 	}
- + 
- + 	/* XXX: Why do we need to wakeup the clockdomains? */
- + 	if(gfx_l3_clkdm && gfx_l4ls_clkdm) {
- + 		clkdm_wakeup(gfx_l3_clkdm);
- + 		clkdm_wakeup(gfx_l4ls_clkdm);
- + 	}
- + 
- + 	/*
- + 	 * Touchscreen module was enabled during standby
- + 	 * Disable it here.
- + 	 */
- + 	if (suspend_state == PM_SUSPEND_STANDBY)
- + 		writel(0x0, AM33XX_CM_WKUP_ADC_TSC_CLKCTRL);
- + 
- + 	/*
- + 	 * Put USB module to idle on resume from standby
- + 	 */
- + 	if (suspend_state == PM_SUSPEND_STANDBY)
- + 		omap_hwmod_idle(usb_oh);
- + 
- + 	ret = am33xx_verify_lp_state(ret);
- + 
- + 	/*
- + 	 * Enable the GPIO module. Once the driver is
- + 	 * fully adapted to runtime PM this will go away
- + 	 */
- + 	/*
- + 	 * During standby, GPIO was not disabled. Hence no
- + 	 * need to enable it here.
- + 	 */
- + 	if ((suspend_cfg_param_list[EVM_ID] != EVM_SK) &&
- + 			(suspend_state != PM_SUSPEND_STANDBY))
- + 		omap_hwmod_enable(gpio1_oh);
- + 
- + 	return ret;
- + }
- + 
- + static int am33xx_pm_enter(suspend_state_t unused)
- + {
- + 	int ret = 0;
- + 
- + 	switch (suspend_state) {
- + 	case PM_SUSPEND_STANDBY:
- + 	case PM_SUSPEND_MEM:
- + 		ret = am33xx_pm_suspend();
- + 		break;
- + 	default:
- + 		ret = -EINVAL;
- + 	}
- + 
- + 	return ret;
- + }
- + 
- + static int am33xx_pm_begin(suspend_state_t state)
- + {
- + 	int ret = 0;
- + 	int state_id = 0;
- + 
- + 	disable_hlt();
- + 
- + 	switch (state) {
- + 	case PM_SUSPEND_STANDBY:
- + 		state_id = 0xb;
- + 		break;
- + 	case PM_SUSPEND_MEM:
- + 		state_id = 0x3;
- + 		break;
- + 	}
- + 
- + 	/*
- + 	 * Populate the resume address as part of IPC data
- + 	 * The offset to be added comes from sleep33xx.S
- + 	 * Add 4 bytes to ensure that resume happens from
- + 	 * the word *after* the word which holds the resume offset
- + 	 */
- + 	am33xx_lp_ipc.resume_addr = (DS_RESUME_BASE + am33xx_resume_offset + 4);
- + 	am33xx_lp_ipc.sleep_mode  = state_id;
- + 	am33xx_lp_ipc.ipc_data1	  = DS_IPC_DEFAULT;
- + 	am33xx_lp_ipc.ipc_data2   = DS_IPC_DEFAULT;
- + 
- + 	am33xx_ipc_cmd(&am33xx_lp_ipc);
- + 
- + 	m3_state = M3_STATE_MSG_FOR_LP;
- + 
- + 	omap_mbox_enable_irq(m3_mbox, IRQ_RX);
- + 
- + 	ret = omap_mbox_msg_send(m3_mbox, 0xABCDABCD);
- + 	if (ret) {
- + 		pr_err("A8<->CM3 MSG for LP failed\n");
- + 		am33xx_m3_state_machine_reset();
- + 		ret = -1;
- + 	}
- + 
- + 	if (!wait_for_completion_timeout(&a8_m3_sync, msecs_to_jiffies(5000))) {
- + 		pr_err("A8<->CM3 sync failure\n");
- + 		am33xx_m3_state_machine_reset();
- + 		ret = -1;
- + 	} else {
- + 		pr_debug("Message sent for entering %s\n",
- + 			(DS_MODE == DS0_ID ? "DS0" : "DS1"));
- + 		omap_mbox_disable_irq(m3_mbox, IRQ_RX);
- + 	}
- + 
- + 	suspend_state = state;
- + 	return ret;
- + }
- + 
- + static void am33xx_m3_state_machine_reset(void)
- + {
- + 	int ret = 0;
- + 
- + 	am33xx_lp_ipc.resume_addr = 0x0;
- + 	am33xx_lp_ipc.sleep_mode  = 0xe;
- + 	am33xx_lp_ipc.ipc_data1	  = DS_IPC_DEFAULT;
- + 	am33xx_lp_ipc.ipc_data2   = DS_IPC_DEFAULT;
- + 
- + 	am33xx_ipc_cmd(&am33xx_lp_ipc);
- + 
- + 	m3_state = M3_STATE_MSG_FOR_RESET;
- + 
- + 	ret = omap_mbox_msg_send(m3_mbox, 0xABCDABCD);
- + 	if (!ret) {
- + 		pr_debug("Message sent for resetting M3 state machine\n");
- + 		if (!wait_for_completion_timeout(&a8_m3_sync, msecs_to_jiffies(5000)))
- + 			pr_err("A8<->CM3 sync failure\n");
- + 	} else {
- + 		pr_err("Could not reset M3 state machine!!!\n");
- + 		m3_state = M3_STATE_UNKNOWN;
- + 	}
- + }
- + 
- + static void am33xx_pm_end(void)
- + {
- + 	suspend_state = PM_SUSPEND_ON;
- + 
- + 	omap_mbox_enable_irq(m3_mbox, IRQ_RX);
- + 
- + 	am33xx_m3_state_machine_reset();
- + 
- + 	enable_hlt();
- + 
- + 	return;
- + }
- + 
- + static int am33xx_pm_valid(suspend_state_t state)
- + {
- + 	switch (state) {
- + 	case PM_SUSPEND_STANDBY:
- + 	case PM_SUSPEND_MEM:
- + 		return 1;
- + 	default:
- + 		return 0;
- + 	}
- + }
- + 
- + static const struct platform_suspend_ops am33xx_pm_ops = {
- + 	.begin		= am33xx_pm_begin,
- + 	.end		= am33xx_pm_end,
- + 	.enter		= am33xx_pm_enter,
- + 	.valid		= am33xx_pm_valid,
- + 	.prepare	= am33xx_pm_prepare_late,
- + 	.finish		= am33xx_pm_finish,
- + };
- + 
- + int am33xx_ipc_cmd(struct a8_wkup_m3_ipc_data *data)
- + {
- + 	writel(data->resume_addr, ipc_regs);
- + 	writel(data->sleep_mode, ipc_regs + 0x4);
- + 	writel(data->ipc_data1, ipc_regs + 0x8);
- + 	writel(data->ipc_data2, ipc_regs + 0xc);
- + 
- + 	return 0;
- + }
- + 
- + /* return 0 if no reset M3 needed, 1 otherwise */
- + static int am33xx_verify_lp_state(int core_suspend_stat)
- + {
- + 	int status, ret = 0;
- + 
- + 	if (core_suspend_stat) {
- + 		pr_err("Kernel core reported suspend failure\n");
- + 		ret = -1;
- + 		goto clear_old_status;
- + 	}
- + 
- + 	status = readl(ipc_regs + 0x4);
- + 	status &= 0xffff0000;
- + 
- + 	if (status == 0x0) {
- + 		pr_info("Successfully transitioned all domains to low power state\n");
- + 		if (am33xx_lp_ipc.sleep_mode == DS0_ID)
- + 			per_pwrdm->ret_logic_off_counter++;
- + 		goto clear_old_status;
- + 	} else if (status == 0x10000) {
- + 		pr_err("Could not enter low power state\n"
- + 			"Please check for active clocks in PER domain\n");
- + 		ret = -1;
- + 		goto clear_old_status;
- + 	} else {
- + 		pr_err("Something is terribly wrong :(\nStatus = %0x\n",
- + 				status);
- + 		ret = -1;
- + 	}
- + 
- + clear_old_status:
- + 	/* After decoding write back the bad status */
- + 	status = readl(ipc_regs + 0x4);
- + 	status &= 0xffff0000;
- + 	status |= 0x10000;
- + 	writel(status, ipc_regs + 0x4);
- + 
- + 	return ret;
- + }
- + 
- + /*
- +  * Dummy notifier for the mailbox
- +  * TODO: Can this be completely removed?
- +  */
- + int wkup_m3_mbox_msg(struct notifier_block *self, unsigned long len, void *msg)
- + {
- + 	return 0;
- + }
- + 
- + static struct notifier_block wkup_m3_mbox_notifier = {
- + 	.notifier_call = wkup_m3_mbox_msg,
- + };
- + 
- + static irqreturn_t wkup_m3_txev_handler(int irq, void *unused)
- + {
- + 	writel(0x1, m3_eoi);
- + 
- + 	if (m3_state == M3_STATE_RESET) {
- + 		m3_state = M3_STATE_INITED;
- + 		m3_version = readl(ipc_regs + 0x8);
- + 		m3_version &= 0x0000ffff;
- + 		if (m3_version == M3_VERSION_UNKNOWN) {
- + 			pr_warning("Unable to read CM3 firmware version\n");
- + 		} else {
- + 			pr_info("Cortex M3 Firmware Version = 0x%x\n",
- + 							m3_version);
- + 		}
- + 	} else if (m3_state == M3_STATE_MSG_FOR_RESET) {
- + 		m3_state = M3_STATE_INITED;
- + 		omap_mbox_msg_rx_flush(m3_mbox);
- + 		if (m3_mbox->ops->ack_irq)
- + 			m3_mbox->ops->ack_irq(m3_mbox, IRQ_RX);
- + 		complete(&a8_m3_sync);
- + 	} else if (m3_state == M3_STATE_MSG_FOR_LP) {
- + 		omap_mbox_msg_rx_flush(m3_mbox);
- + 		if (m3_mbox->ops->ack_irq)
- + 			m3_mbox->ops->ack_irq(m3_mbox, IRQ_RX);
- + 		complete(&a8_m3_sync);
- + 	} else if (m3_state == M3_STATE_UNKNOWN) {
- + 		pr_err("IRQ %d with CM3 in unknown state\n", irq);
- + 		omap_mbox_msg_rx_flush(m3_mbox);
- + 		if (m3_mbox->ops->ack_irq)
- + 			m3_mbox->ops->ack_irq(m3_mbox, IRQ_RX);
- + 		return IRQ_NONE;
- + 	}
- + 
- + 	writel(0x0, m3_eoi);
- + 
- + 	return IRQ_HANDLED;
- + }
- + 
- + /* Initiliaze WKUP_M3, load the binary blob and let it run */
- + static int wkup_m3_init(void)
- + {
- + 	struct clk *m3_clk;
- + 	struct omap_hwmod *wkup_m3_oh;
- + 	const struct firmware *firmware;
- + 	int ret = 0;
- + 	int ipc_reg_r = 0;
- + 
- + 	wkup_m3_oh = omap_hwmod_lookup("wkup_m3");
- + 
- + 	if (!wkup_m3_oh) {
- + 		pr_err("%s: could not find omap_hwmod\n", __func__);
- + 		ret = -ENODEV;
- + 		goto exit;
- + 	}
- + 
- + 	ipc_regs = ioremap(A8_M3_IPC_REGS, 0x4*8);
- + 	if (!ipc_regs) {
- + 		pr_err("Could not ioremap the IPC area\b");
- + 		ret = -ENOMEM;
- + 		goto exit;
- + 	}
- + 
- + 	m3_eoi = ioremap(M3_TXEV_EOI, 0x4);
- + 	if (!m3_eoi) {
- + 		pr_err("Could not ioremap the EOI register\n");
- + 		ret = -ENOMEM;
- + 		goto err1;
- + 	}
- + 
- + 	/* Reserve the MBOX for sending messages to M3 */
- + 	m3_mbox = omap_mbox_get("wkup_m3", &wkup_m3_mbox_notifier);
- + 	if (IS_ERR(m3_mbox)) {
- + 		pr_err("Could not reserve mailbox for A8->M3 IPC\n");
- + 		ret = -ENODEV;
- + 		goto err2;
- + 	}
- + 
- + 	/* Enable access to the M3 code and data area from A8 */
- + 	m3_clk = clk_get(NULL, "wkup_m3_fck");
- + 	if (IS_ERR(m3_clk)) {
- + 		pr_err("%s failed to enable WKUP_M3 clock\n", __func__);
- + 		goto err3;
- + 	}
- + 
- + 	if (clk_enable(m3_clk)) {
- + 		pr_err("%s WKUP_M3: clock enable Failed\n", __func__);
- + 		goto err4;
- + 	}
- + 
- + 	m3_code = ioremap(M3_UMEM, SZ_16K);
- + 	if (!m3_code) {
- + 		pr_err("%s Could not ioremap M3 code space\n", __func__);
- + 		ret = -ENOMEM;
- + 		goto err5;
- + 	}
- + 
- + 	pr_info("Trying to load am335x-pm-firmware.bin (60 secs timeout)\n");
- + 
- + 	ret = request_firmware(&firmware, "am335x-pm-firmware.bin", mpu_dev);
- + 	if (ret < 0) {
- + 		dev_err(mpu_dev, "request_firmware failed\n");
- + 		goto err6;
- + 	} else {
- + 		memcpy(m3_code, firmware->data, firmware->size);
- + 		pr_info("Copied the M3 firmware to UMEM\n");
- + 	}
- + 
- + 	ret = request_irq(AM33XX_IRQ_M3_M3SP_TXEV, wkup_m3_txev_handler,
- + 			  IRQF_DISABLED, "wkup_m3_txev", NULL);
- + 	if (ret) {
- + 		pr_err("%s request_irq failed for 0x%x\n", __func__,
- + 			AM33XX_IRQ_M3_M3SP_TXEV);
- + 		goto err6;
- + 	}
- + 
- + 	m3_state = M3_STATE_RESET;
- + 
- + 	/*
- + 	 * Invalidate M3 firmware version before hardreset.
- + 	 * Write invalid version in lower 4 nibbles of parameter
- + 	 * register (ipc_regs + 0x8).
- + 	 */
- + 	ipc_reg_r = readl(ipc_regs + 0x8);
- + 	ipc_reg_r &= 0xffff0000;
- + 	m3_version |= ipc_reg_r;
- + 	writel(m3_version, ipc_regs + 0x8);
- + 
- + 	ret = omap_hwmod_deassert_hardreset(wkup_m3_oh, "wkup_m3");
- + 	if (ret) {
- + 		pr_err("Could not deassert the reset for WKUP_M3\n");
- + 		goto err6;
- + 	} else {
- + 		return 0;
- + 	}
- + 
- + err6:
- + 	release_firmware(firmware);
- + 	iounmap(m3_code);
- + err5:
- + 	clk_disable(m3_clk);
- + err4:
- + 	clk_put(m3_clk);
- + err3:
- + 	omap_mbox_put(m3_mbox, &wkup_m3_mbox_notifier);
- + err2:
- + 	iounmap(m3_eoi);
- + err1:
- + 	iounmap(ipc_regs);
- + exit:
- + 	return ret;
- + }
- + 
- + /*
- +  * Initiate sleep transition for other clockdomains, if
- +  * they are not used
- +  */
- + static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
- + {
- + 	if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
- + 			atomic_read(&clkdm->usecount) == 0)
- + 		clkdm_sleep(clkdm);
- + 	return 0;
- + }
- + #endif /* CONFIG_SUSPEND */
- + 
- + /*
- +  * Push the minimal suspend-resume code to SRAM
- +  */
- + void am33xx_push_sram_idle(void)
- + {
- + 	am33xx_do_wfi_sram = (void *)omap_sram_push
- + 					(am33xx_do_wfi, am33xx_do_wfi_sz);
- + }
- + 
- + static int __init am33xx_pm_init(void)
- + {
- + #ifdef CONFIG_CKB_SUSPEND_SUPPORT
- + 	int ret;
- + #ifdef CONFIG_SUSPEND
- + 	void __iomem *base;
- + 	u32 reg;
- + 	u32 evm_id;
- + 
- + #endif
- + 	
- + 	pr_info("Power Management for AM33XX family\n");
- + 
- + #ifdef CONFIG_SUSPEND
- + /* Read SDRAM_CONFIG register to determine Memory Type */
- + 	base = am33xx_get_ram_base();
- + 	reg = readl(base + EMIF4_0_SDRAM_CONFIG);
- + 	reg = (reg & SDRAM_TYPE_MASK) >> SDRAM_TYPE_SHIFT;
- + 	suspend_cfg_param_list[MEMORY_TYPE] = reg;
- + 
- + /*
- +  * vtp_ctrl register value for DDR2 and DDR3 as suggested
- +  * by h/w team
- +  */
- + 	if (reg == MEM_TYPE_DDR2)
- + 		suspend_cfg_param_list[SUSP_VTP_CTRL_VAL] = SUSP_VTP_CTRL_DDR2;
- + 	else
- + 		suspend_cfg_param_list[SUSP_VTP_CTRL_VAL] = SUSP_VTP_CTRL_DDR3;
- + 
- + 
- + 	/* Get Board Id */
- + #if 0
- + 	evm_id = am335x_evm_get_id();
- + 	if (evm_id != -EINVAL)
- + 		suspend_cfg_param_list[EVM_ID] = evm_id;
- + 	else
- + 		suspend_cfg_param_list[EVM_ID] = 0xff;
- + #else
- + 	//suspend_cfg_param_list[EVM_ID] = BEAGLE_BONE_A3;
- + 	suspend_cfg_param_list[EVM_ID] = GEN_PURP_DDR3_EVM;
- + #endif
- + 
- + 	/* CPU Revision */
- + 	reg = omap_rev();
- + 	if (reg == AM335X_REV_ES2_0)
- + 		suspend_cfg_param_list[CPU_REV] = CPU_REV_2;
- + 	else
- + 		suspend_cfg_param_list[CPU_REV] = CPU_REV_1;
- + 
- + 	(void) clkdm_for_each(clkdms_setup, NULL);
- + 
- + 	/* CEFUSE domain should be turned off post bootup */
- + 	cefuse_pwrdm = pwrdm_lookup("cefuse_pwrdm");
- + 	if (cefuse_pwrdm == NULL)
- + 		pr_err("Failed to get cefuse_pwrdm\n");
- + 	else
- + 		pwrdm_set_next_pwrst(cefuse_pwrdm, PWRDM_POWER_OFF);
- + 
- + 	gfx_pwrdm = pwrdm_lookup("gfx_pwrdm");
- + 	if (gfx_pwrdm == NULL)
- + 		pr_err("Failed to get gfx_pwrdm\n");
- + 
- + 	per_pwrdm = pwrdm_lookup("per_pwrdm");
- + 	if (per_pwrdm == NULL)
- + 		pr_err("Failed to get per_pwrdm\n");
- + 
- + 	gfx_l3_clkdm = clkdm_lookup("gfx_l3_clkdm");
- + 	if (gfx_l3_clkdm == NULL)
- + 		pr_err("Failed to get gfx_l3_clkdm\n");
- + 
- + 	gfx_l4ls_clkdm = clkdm_lookup("gfx_l4ls_gfx_clkdm");
- + 	if (gfx_l4ls_clkdm == NULL)
- + 		pr_err("Failed to get gfx_l4ls_gfx_clkdm\n");
- + 
- + 	mpu_dev = omap_device_get_by_hwmod_name("mpu");
- + 
- + 	if (!mpu_dev) {
- + 		pr_warning("%s: unable to get the mpu device\n", __func__);
- + 		return -EINVAL;
- + 	}
- + 
- + 	ret = wkup_m3_init();
- + 
- + 	if (ret) {
- + 		pr_err("Could not initialise WKUP_M3. "
- + 			"Power management will be compromised\n");
- + 		enable_deep_sleep = false;
- + 	}
- + 
- + 	if (enable_deep_sleep)
- + 		suspend_set_ops(&am33xx_pm_ops);
- + #endif /* CONFIG_SUSPEND */
- + 
- + 	return ret;
- + #else
- + 	return 0;
- + #endif
- + }
- + late_initcall(am33xx_pm_init);
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/pm33xx.h linux-3.2.1/arch/arm/mach-ckb_3352/pm33xx.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/pm33xx.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/pm33xx.h	2014-05-15 13:25:13.966977369 +0900
- ***************
- *** 0 ****
- --- 1,88 ----
- + /*
- +  * AM33XX Power Management Routines
- +  *
- +  * Copyright (C) 2012 Texas Instruments Inc.
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #ifndef __ARCH_ARM_MACH_OMAP2_PM33XX_H
- + #define __ARCH_ARM_MACH_OMAP2_PM33XX_H
- + 
- + #include <mach/hardware.h>	/* XXX Is this the right one to include? */
- + #include "control.h"
- + #include "mux33xx.h"
- + 
- + #ifndef __ASSEMBLER__
- + extern void __iomem *am33xx_get_ram_base(void);
- + 
- + /*
- +  * This enum is used to index the array passed to suspend routine with
- +  * parameters that vary across DDR2 and DDR3 sleep sequence.
- +  *
- +  * Since these are used to load into registers by suspend code,
- +  * entries here must always be in sync with the suspend code
- +  * in arm/mach-omap2/sleep33xx.S
- +  */
- + enum suspend_cfg_params {
- + 	MEMORY_TYPE = 0,
- + 	SUSP_VTP_CTRL_VAL,
- + 	EVM_ID,
- + 	CPU_REV,
- + 	SUSPEND_STATE,
- + 	SUSPEND_CFG_PARAMS_END /* Must be the last entry */
- + };
- + 
- + struct a8_wkup_m3_ipc_data {
- + 	int resume_addr;
- + 	int sleep_mode;
- + 	int ipc_data1;
- + 	int ipc_data2;
- + } am33xx_lp_ipc;
- + 
- + #endif /* ASSEMBLER */
- + 
- + #define M3_TXEV_EOI			(AM33XX_CTRL_BASE + 0x1324)
- + #define A8_M3_IPC_REGS			(AM33XX_CTRL_BASE + 0x1328)
- + #define DS_RESUME_BASE			0x40300000
- + #define DS_IPC_DEFAULT			0xffffffff
- + #define M3_UMEM				0x44D00000
- + 
- + #define	DS0_ID				0x3
- + #define DS1_ID				0x5
- + 
- + #define M3_STATE_UNKNOWN		-1
- + #define M3_STATE_RESET			0
- + #define M3_STATE_INITED			1
- + #define M3_STATE_MSG_FOR_LP		2
- + #define M3_STATE_MSG_FOR_RESET		3
- + 
- + #define VTP_CTRL_READY		(0x1 << 5)
- + #define VTP_CTRL_ENABLE		(0x1 << 6)
- + #define VTP_CTRL_LOCK_EN	(0x1 << 4)
- + #define VTP_CTRL_START_EN	(0x1)
- + 
- + #define DDR_IO_CTRL		(AM33XX_CTRL_BASE + 0x0E04)
- + #define VTP0_CTRL_REG		(AM33XX_CTRL_BASE + 0x0E0C)
- + #define DDR_CMD0_IOCTRL		(AM33XX_CTRL_BASE + 0x1404)
- + #define DDR_CMD1_IOCTRL		(AM33XX_CTRL_BASE + 0x1408)
- + #define DDR_CMD2_IOCTRL		(AM33XX_CTRL_BASE + 0x140C)
- + #define DDR_DATA0_IOCTRL	(AM33XX_CTRL_BASE + 0x1440)
- + #define DDR_DATA1_IOCTRL	(AM33XX_CTRL_BASE + 0x1444)
- + 
- + #define MEM_TYPE_DDR2		2
- + 
- + #define SUSP_VTP_CTRL_DDR2	0x10117
- + #define SUSP_VTP_CTRL_DDR3	0x0
- + 
- + #define CPU_REV_1		1
- + #define CPU_REV_2		2
- + 
- + #define M3_VERSION_UNKNOWN		0x0000ffff
- + 
- + #define PM_DS0			0
- + #define PM_STANDBY		1
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/pm.c linux-3.2.1/arch/arm/mach-ckb_3352/pm.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/pm.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/pm.c	2014-05-15 13:25:13.966977369 +0900
- ***************
- *** 0 ****
- --- 1,225 ----
- + /*
- +  * pm.c - Common OMAP2+ power management-related code
- +  *
- +  * Copyright (C) 2010 Texas Instruments, Inc.
- +  * Copyright (C) 2010 Nokia Corporation
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #include <linux/kernel.h>
- + #include <linux/init.h>
- + #include <linux/io.h>
- + #include <linux/err.h>
- + #include <linux/opp.h>
- + #include <linux/export.h>
- + 
- + #include <plat/omap-pm.h>
- + #include <plat/omap_device.h>
- + #include "common.h"
- + 
- + #include "voltage.h"
- + #include "powerdomain.h"
- + #include "clockdomain.h"
- + #include "pm.h"
- + #include "twl-common.h"
- + 
- + static struct omap_device_pm_latency *pm_lats;
- + 
- + static int _init_omap_device(char *name)
- + {
- + 	struct omap_hwmod *oh;
- + 	struct platform_device *pdev;
- + 
- + 	oh = omap_hwmod_lookup(name);
- + 	if (WARN(!oh, "%s: could not find omap_hwmod for %s\n",
- + 		 __func__, name))
- + 		return -ENODEV;
- + 
- + 	pdev = omap_device_build(oh->name, 0, oh, NULL, 0, pm_lats, 0, false);
- + 	if (WARN(IS_ERR(pdev), "%s: could not build omap_device for %s\n",
- + 		 __func__, name))
- + 		return -ENODEV;
- + 
- + 	return 0;
- + }
- + 
- + /*
- +  * Build omap_devices for processors and bus.
- +  */
- + static void omap2_init_processor_devices(void)
- + {
- + 	_init_omap_device("mpu");
- + 	if (omap3_has_iva())
- + 		_init_omap_device("iva");
- + 
- + 	_init_omap_device("l3_main");
- + }
- + 
- + /* Types of sleep_switch used in omap_set_pwrdm_state */
- + #define FORCEWAKEUP_SWITCH	0
- + #define LOWPOWERSTATE_SWITCH	1
- + 
- + /*
- +  * This sets pwrdm state (other than mpu & core. Currently only ON &
- +  * RET are supported.
- +  */
- + int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
- + {
- + 	u32 cur_state;
- + 	int sleep_switch = -1;
- + 	int ret = 0;
- + 	int hwsup = 0;
- + 
- + 	if (pwrdm == NULL || IS_ERR(pwrdm))
- + 		return -EINVAL;
- + 
- + 	while (!(pwrdm->pwrsts & (1 << state))) {
- + 		if (state == PWRDM_POWER_OFF)
- + 			return ret;
- + 		state--;
- + 	}
- + 
- + 	cur_state = pwrdm_read_next_pwrst(pwrdm);
- + 	if (cur_state == state)
- + 		return ret;
- + 
- + 	if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
- + 		if ((pwrdm_read_pwrst(pwrdm) > state) &&
- + 			(pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE)) {
- + 			sleep_switch = LOWPOWERSTATE_SWITCH;
- + 		} else {
- + 			hwsup = clkdm_in_hwsup(pwrdm->pwrdm_clkdms[0]);
- + 			clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
- + 			sleep_switch = FORCEWAKEUP_SWITCH;
- + 		}
- + 	}
- + 
- + 	ret = pwrdm_set_next_pwrst(pwrdm, state);
- + 	if (ret) {
- + 		pr_err("%s: unable to set state of powerdomain: %s\n",
- + 		       __func__, pwrdm->name);
- + 		goto err;
- + 	}
- + 
- + 	switch (sleep_switch) {
- + 	case FORCEWAKEUP_SWITCH:
- + 		if (hwsup)
- + 			clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
- + 		else
- + 			clkdm_sleep(pwrdm->pwrdm_clkdms[0]);
- + 		break;
- + 	case LOWPOWERSTATE_SWITCH:
- + 		pwrdm_set_lowpwrstchange(pwrdm);
- + 		break;
- + 	default:
- + 		return ret;
- + 	}
- + 
- + 	pwrdm_state_switch(pwrdm);
- + err:
- + 	return ret;
- + }
- + 
- + /*
- +  * This API is to be called during init to set the various voltage
- +  * domains to the voltage as per the opp table. Typically we boot up
- +  * at the nominal voltage. So this function finds out the rate of
- +  * the clock associated with the voltage domain, finds out the correct
- +  * opp entry and sets the voltage domain to the voltage specified
- +  * in the opp entry
- +  */
- + static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
- + 					 const char *oh_name)
- + {
- + 	struct voltagedomain *voltdm;
- + 	struct clk *clk;
- + 	struct opp *opp;
- + 	unsigned long freq, bootup_volt;
- + 	struct device *dev;
- + 
- + 	if (!vdd_name || !clk_name || !oh_name) {
- + 		pr_err("%s: invalid parameters\n", __func__);
- + 		goto exit;
- + 	}
- + 
- + 	dev = omap_device_get_by_hwmod_name(oh_name);
- + 	if (IS_ERR(dev)) {
- + 		pr_err("%s: Unable to get dev pointer for hwmod %s\n",
- + 			__func__, oh_name);
- + 		goto exit;
- + 	}
- + 
- + 	voltdm = voltdm_lookup(vdd_name);
- + 	if (IS_ERR(voltdm)) {
- + 		pr_err("%s: unable to get vdd pointer for vdd_%s\n",
- + 			__func__, vdd_name);
- + 		goto exit;
- + 	}
- + 
- + 	clk =  clk_get(NULL, clk_name);
- + 	if (IS_ERR(clk)) {
- + 		pr_err("%s: unable to get clk %s\n", __func__, clk_name);
- + 		goto exit;
- + 	}
- + 
- + 	freq = clk->rate;
- + 	clk_put(clk);
- + 
- + 	opp = opp_find_freq_ceil(dev, &freq);
- + 	if (IS_ERR(opp)) {
- + 		pr_err("%s: unable to find boot up OPP for vdd_%s\n",
- + 			__func__, vdd_name);
- + 		goto exit;
- + 	}
- + 
- + 	bootup_volt = opp_get_voltage(opp);
- + 	if (!bootup_volt) {
- + 		pr_err("%s: unable to find voltage corresponding "
- + 			"to the bootup OPP for vdd_%s\n", __func__, vdd_name);
- + 		goto exit;
- + 	}
- + 
- + 	voltdm_scale(voltdm, bootup_volt);
- + 	return 0;
- + 
- + exit:
- + 	pr_err("%s: unable to set vdd_%s\n", __func__, vdd_name);
- + 	return -EINVAL;
- + }
- + 
- + static void __init omap3_init_voltages(void)
- + {
- + 	if (!cpu_is_omap34xx() || cpu_is_am33xx())
- + 		return;
- + 
- + 	omap2_set_init_voltage("mpu_iva", "dpll1_ck", "mpu");
- + 	omap2_set_init_voltage("core", "l3_ick", "l3_main");
- + }
- + 
- + static int __init omap2_common_pm_init(void)
- + {
- + 	if (!of_have_populated_dt())
- + 		omap2_init_processor_devices();
- + 	omap_pm_if_init();
- + 
- + 	return 0;
- + }
- + postcore_initcall(omap2_common_pm_init);
- + 
- + static int __init omap2_common_pm_late_init(void)
- + {
- + 	/* Init the voltage layer */
- + 	omap_voltage_late_init();
- + 
- + 	/* Initialize the voltages */
- + 	omap3_init_voltages();
- + 	
- + 	/* Smartreflex device init */
- + 	omap_devinit_smartreflex();
- + 
- + 	return 0;
- + }
- + late_initcall(omap2_common_pm_late_init);
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/pm-debug.c linux-3.2.1/arch/arm/mach-ckb_3352/pm-debug.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/pm-debug.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/pm-debug.c	2014-05-15 13:25:13.966977369 +0900
- ***************
- *** 0 ****
- --- 1,278 ----
- + /*
- +  * OMAP Power Management debug routines
- +  *
- +  * Copyright (C) 2005 Texas Instruments, Inc.
- +  * Copyright (C) 2006-2008 Nokia Corporation
- +  *
- +  * Written by:
- +  * Richard Woodruff <r-woodruff2@ti.com>
- +  * Tony Lindgren
- +  * Juha Yrjola
- +  * Amit Kucheria <amit.kucheria@nokia.com>
- +  * Igor Stoppa <igor.stoppa@nokia.com>
- +  * Jouni Hogander
- +  *
- +  * Based on pm.c for omap2
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #include <linux/kernel.h>
- + #include <linux/sched.h>
- + #include <linux/clk.h>
- + #include <linux/err.h>
- + #include <linux/io.h>
- + #include <linux/module.h>
- + #include <linux/slab.h>
- + 
- + #include <plat/clock.h>
- + #include <plat/board.h>
- + #include "powerdomain.h"
- + #include "clockdomain.h"
- + #include <plat/dmtimer.h>
- + #include <plat/omap-pm.h>
- + 
- + #include "cm2xxx_3xxx.h"
- + #include "prm2xxx_3xxx.h"
- + #include "pm.h"
- + 
- + u32 enable_off_mode;
- + 
- + #ifdef CONFIG_DEBUG_FS
- + #include <linux/debugfs.h>
- + #include <linux/seq_file.h>
- + 
- + static int pm_dbg_init_done;
- + 
- + static int pm_dbg_init(void);
- + 
- + enum {
- + 	DEBUG_FILE_COUNTERS = 0,
- + 	DEBUG_FILE_TIMERS,
- + };
- + 
- + static const char pwrdm_state_names[][PWRDM_MAX_PWRSTS] = {
- + 	"OFF",
- + 	"RET",
- + 	"INA",
- + 	"ON"
- + };
- + 
- + void pm_dbg_update_time(struct powerdomain *pwrdm, int prev)
- + {
- + 	s64 t;
- + 
- + 	if (!pm_dbg_init_done)
- + 		return ;
- + 
- + 	/* Update timer for previous state */
- + 	t = sched_clock();
- + 
- + 	pwrdm->state_timer[prev] += t - pwrdm->timer;
- + 
- + 	pwrdm->timer = t;
- + }
- + 
- + static int clkdm_dbg_show_counter(struct clockdomain *clkdm, void *user)
- + {
- + 	struct seq_file *s = (struct seq_file *)user;
- + 
- + 	if (strcmp(clkdm->name, "emu_clkdm") == 0 ||
- + 		strcmp(clkdm->name, "wkup_clkdm") == 0 ||
- + 		strncmp(clkdm->name, "dpll", 4) == 0)
- + 		return 0;
- + 
- + 	seq_printf(s, "%s->%s (%d)", clkdm->name,
- + 			clkdm->pwrdm.ptr->name,
- + 			atomic_read(&clkdm->usecount));
- + 	seq_printf(s, "\n");
- + 
- + 	return 0;
- + }
- + 
- + static int pwrdm_dbg_show_counter(struct powerdomain *pwrdm, void *user)
- + {
- + 	struct seq_file *s = (struct seq_file *)user;
- + 	int i;
- + 
- + 	if (strcmp(pwrdm->name, "emu_pwrdm") == 0 ||
- + 		strcmp(pwrdm->name, "wkup_pwrdm") == 0 ||
- + 		strncmp(pwrdm->name, "dpll", 4) == 0)
- + 		return 0;
- + 
- + 	if (pwrdm->state != pwrdm_read_pwrst(pwrdm))
- + 		printk(KERN_ERR "pwrdm state mismatch(%s) %d != %d\n",
- + 			pwrdm->name, pwrdm->state, pwrdm_read_pwrst(pwrdm));
- + 
- + 	seq_printf(s, "%s (%s)", pwrdm->name,
- + 			pwrdm_state_names[pwrdm->state]);
- + 	for (i = 0; i < PWRDM_MAX_PWRSTS; i++)
- + 		seq_printf(s, ",%s:%d", pwrdm_state_names[i],
- + 			pwrdm->state_counter[i]);
- + 
- + 	seq_printf(s, ",RET-LOGIC-OFF:%d", pwrdm->ret_logic_off_counter);
- + 	for (i = 0; i < pwrdm->banks; i++)
- + 		seq_printf(s, ",RET-MEMBANK%d-OFF:%d", i + 1,
- + 				pwrdm->ret_mem_off_counter[i]);
- + 
- + 	seq_printf(s, "\n");
- + 
- + 	return 0;
- + }
- + 
- + static int pwrdm_dbg_show_timer(struct powerdomain *pwrdm, void *user)
- + {
- + 	struct seq_file *s = (struct seq_file *)user;
- + 	int i;
- + 
- + 	if (strcmp(pwrdm->name, "emu_pwrdm") == 0 ||
- + 		strcmp(pwrdm->name, "wkup_pwrdm") == 0 ||
- + 		strncmp(pwrdm->name, "dpll", 4) == 0)
- + 		return 0;
- + 
- + 	pwrdm_state_switch(pwrdm);
- + 
- + 	seq_printf(s, "%s (%s)", pwrdm->name,
- + 		pwrdm_state_names[pwrdm->state]);
- + 
- + 	for (i = 0; i < 4; i++)
- + 		seq_printf(s, ",%s:%lld", pwrdm_state_names[i],
- + 			pwrdm->state_timer[i]);
- + 
- + 	seq_printf(s, "\n");
- + 	return 0;
- + }
- + 
- + static int pm_dbg_show_counters(struct seq_file *s, void *unused)
- + {
- + 	pwrdm_for_each(pwrdm_dbg_show_counter, s);
- + 	clkdm_for_each(clkdm_dbg_show_counter, s);
- + 
- + 	return 0;
- + }
- + 
- + static int pm_dbg_show_timers(struct seq_file *s, void *unused)
- + {
- + 	pwrdm_for_each(pwrdm_dbg_show_timer, s);
- + 	return 0;
- + }
- + 
- + static int pm_dbg_open(struct inode *inode, struct file *file)
- + {
- + 	switch ((int)inode->i_private) {
- + 	case DEBUG_FILE_COUNTERS:
- + 		return single_open(file, pm_dbg_show_counters,
- + 			&inode->i_private);
- + 	case DEBUG_FILE_TIMERS:
- + 	default:
- + 		return single_open(file, pm_dbg_show_timers,
- + 			&inode->i_private);
- + 	};
- + }
- + 
- + static const struct file_operations debug_fops = {
- + 	.open           = pm_dbg_open,
- + 	.read           = seq_read,
- + 	.llseek         = seq_lseek,
- + 	.release        = single_release,
- + };
- + 
- + static int pwrdm_suspend_get(void *data, u64 *val)
- + {
- + 	int ret = -EINVAL;
- + 
- + 	*val = ret;
- + 
- + 	if (ret >= 0)
- + 		return 0;
- + 	return *val;
- + }
- + 
- + static int pwrdm_suspend_set(void *data, u64 val)
- + {
- + 	return -EINVAL;
- + }
- + 
- + DEFINE_SIMPLE_ATTRIBUTE(pwrdm_suspend_fops, pwrdm_suspend_get,
- + 			pwrdm_suspend_set, "%llu\n");
- + 
- + static int __init pwrdms_setup(struct powerdomain *pwrdm, void *dir)
- + {
- + 	int i;
- + 	s64 t;
- + 	struct dentry *d;
- + 
- + 	t = sched_clock();
- + 
- + 	for (i = 0; i < 4; i++)
- + 		pwrdm->state_timer[i] = 0;
- + 
- + 	pwrdm->timer = t;
- + 
- + 	if (strncmp(pwrdm->name, "dpll", 4) == 0)
- + 		return 0;
- + 
- + 	d = debugfs_create_dir(pwrdm->name, (struct dentry *)dir);
- + 
- + 	(void) debugfs_create_file("suspend", S_IRUGO|S_IWUSR, d,
- + 			(void *)pwrdm, &pwrdm_suspend_fops);
- + 
- + 	return 0;
- + }
- + 
- + static int option_get(void *data, u64 *val)
- + {
- + 	u32 *option = data;
- + 
- + 	*val = *option;
- + 
- + 	return 0;
- + }
- + 
- + static int option_set(void *data, u64 val)
- + {
- + 	u32 *option = data;
- + 
- + 	*option = val;
- + 
- + 	if (option == &enable_off_mode) {
- + 		if (val)
- + 			omap_pm_enable_off_mode();
- + 		else
- + 			omap_pm_disable_off_mode();
- + 	}
- + 
- + 	return 0;
- + }
- + 
- + DEFINE_SIMPLE_ATTRIBUTE(pm_dbg_option_fops, option_get, option_set, "%llu\n");
- + 
- + static int __init pm_dbg_init(void)
- + {
- + 	struct dentry *d;
- + 
- + 	if (pm_dbg_init_done)
- + 		return 0;
- + 
- + 	d = debugfs_create_dir("pm_debug", NULL);
- + 	if (IS_ERR(d))
- + 		return PTR_ERR(d);
- + 
- + 	(void) debugfs_create_file("count", S_IRUGO,
- + 		d, (void *)DEBUG_FILE_COUNTERS, &debug_fops);
- + 	(void) debugfs_create_file("time", S_IRUGO,
- + 		d, (void *)DEBUG_FILE_TIMERS, &debug_fops);
- + 
- + 	pwrdm_for_each(pwrdms_setup, (void *)d);
- + 
- + 	(void) debugfs_create_file("enable_off_mode", S_IRUGO | S_IWUSR, d,
- + 				   &enable_off_mode, &pm_dbg_option_fops);
- + 	pm_dbg_init_done = 1;
- + 
- + 	return 0;
- + }
- + arch_initcall(pm_dbg_init);
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/pm.h linux-3.2.1/arch/arm/mach-ckb_3352/pm.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/pm.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/pm.h	2014-05-15 13:25:13.966977369 +0900
- ***************
- *** 0 ****
- --- 1,124 ----
- + /*
- +  * OMAP2/3 Power Management Routines
- +  *
- +  * Copyright (C) 2008 Nokia Corporation
- +  * Jouni Hogander
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + #ifndef __ARCH_ARM_MACH_OMAP2_PM_H
- + #define __ARCH_ARM_MACH_OMAP2_PM_H
- + 
- + #include <linux/err.h>
- + 
- + #include "powerdomain.h"
- + 
- + extern void *omap3_secure_ram_storage;
- + extern void omap3_pm_off_mode_enable(int);
- + extern void omap_sram_idle(void);
- + extern int omap3_can_sleep(void);
- + extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
- + extern int omap3_idle_init(void);
- + extern int omap4_idle_init(void);
- + 
- + #if defined(CONFIG_PM_OPP)
- + extern int omap3_opp_init(void);
- + extern int omap4_opp_init(void);
- + #else
- + static inline int omap3_opp_init(void)
- + {
- + 	return -EINVAL;
- + }
- + static inline int omap4_opp_init(void)
- + {
- + 	return -EINVAL;
- + }
- + #endif
- + 
- + /*
- +  * cpuidle mach specific parameters
- +  *
- +  * The board code can override the default C-states definition using
- +  * omap3_pm_init_cpuidle
- +  */
- + struct cpuidle_params {
- + 	u32 exit_latency;	/* exit_latency = sleep + wake-up latencies */
- + 	u32 target_residency;
- + 	u8 valid;		/* validates the C-state */
- + };
- + 
- + #if defined(CONFIG_PM) && defined(CONFIG_CPU_IDLE)
- + extern void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params);
- + #else
- + static
- + inline void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
- + {
- + }
- + #endif
- + 
- + extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
- + extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
- + 
- + #ifdef CONFIG_PM_DEBUG
- + extern u32 enable_off_mode;
- + #else
- + #define enable_off_mode 0
- + #endif
- + 
- + #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
- + extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev);
- + #else
- + #define pm_dbg_update_time(pwrdm, prev) do {} while (0);
- + #endif /* CONFIG_PM_DEBUG */
- + 
- + /* 24xx */
- + extern void omap24xx_idle_loop_suspend(void);
- + extern unsigned int omap24xx_idle_loop_suspend_sz;
- + 
- + extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl,
- + 					void __iomem *sdrc_power);
- + extern unsigned int omap24xx_cpu_suspend_sz;
- + 
- + /* 3xxx */
- + extern void omap34xx_cpu_suspend(int save_state);
- + 
- + /* save_secure_ram_context function pointer and size, for copy to SRAM */
- + extern int save_secure_ram_context(u32 *addr);
- + extern unsigned int save_secure_ram_context_sz;
- + 
- + extern void omap3_save_scratchpad_contents(void);
- + 
- + /* 33xx */
- + /* am33xx_do_wfi function pointer and size, for copy to SRAM */
- + extern void am33xx_do_wfi(void);
- + extern unsigned int am33xx_do_wfi_sz;
- + extern unsigned int am33xx_resume_offset;
- + /* ... and its pointer from SRAM after copy */
- + extern void (*am33xx_do_wfi_sram)(u32 *);
- + /* The resume location */
- + extern void am33xx_resume_vector(void);
- + 
- + #define PM_RTA_ERRATUM_i608		(1 << 0)
- + #define PM_SDRC_WAKEUP_ERRATUM_i583	(1 << 1)
- + 
- + #if defined(CONFIG_PM)
- + extern u16 pm34xx_errata;
- + #define IS_PM34XX_ERRATUM(id)		(pm34xx_errata & (id))
- + extern void enable_omap3630_toggle_l2_on_restore(void);
- + #endif		/* defined(CONFIG_PM) */
- + 
- + #ifdef CONFIG_OMAP_SMARTREFLEX
- + extern int omap_devinit_smartreflex(void);
- + extern void omap_enable_smartreflex_on_init(void);
- + #else
- + static inline int omap_devinit_smartreflex(void)
- + {
- + 	return -EINVAL;
- + }
- + 
- + static inline void omap_enable_smartreflex_on_init(void) {}
- + #endif
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/powerdomain44xx.c linux-3.2.1/arch/arm/mach-ckb_3352/powerdomain44xx.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/powerdomain44xx.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/powerdomain44xx.c	2014-05-15 13:25:13.970604039 +0900
- ***************
- *** 0 ****
- --- 1,225 ----
- + /*
- +  * OMAP4 powerdomain control
- +  *
- +  * Copyright (C) 2009-2010 Texas Instruments, Inc.
- +  * Copyright (C) 2007-2009 Nokia Corporation
- +  *
- +  * Derived from mach-omap2/powerdomain.c written by Paul Walmsley
- +  * Rajendra Nayak <rnayak@ti.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #include <linux/io.h>
- + #include <linux/errno.h>
- + #include <linux/delay.h>
- + 
- + #include "powerdomain.h"
- + #include <plat/prcm.h>
- + #include "prm2xxx_3xxx.h"
- + #include "prm44xx.h"
- + #include "prminst44xx.h"
- + #include "prm-regbits-44xx.h"
- + 
- + static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
- + {
- + 	omap4_prminst_rmw_inst_reg_bits(OMAP_POWERSTATE_MASK,
- + 					(pwrst << OMAP_POWERSTATE_SHIFT),
- + 					pwrdm->prcm_partition,
- + 					pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
- + 	return 0;
- + }
- + 
- + static int omap4_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
- + {
- + 	u32 v;
- + 
- + 	v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
- + 					pwrdm->pwrstctrl_offs);
- + 	v &= OMAP_POWERSTATE_MASK;
- + 	v >>= OMAP_POWERSTATE_SHIFT;
- + 
- + 	return v;
- + }
- + 
- + static int omap4_pwrdm_read_pwrst(struct powerdomain *pwrdm)
- + {
- + 	u32 v;
- + 
- + 	v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
- + 					pwrdm->pwrstst_offs);
- + 	v &= OMAP_POWERSTATEST_MASK;
- + 	v >>= OMAP_POWERSTATEST_SHIFT;
- + 
- + 	return v;
- + }
- + 
- + static int omap4_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
- + {
- + 	u32 v;
- + 
- + 	v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
- + 					pwrdm->pwrstst_offs);
- + 	v &= OMAP4430_LASTPOWERSTATEENTERED_MASK;
- + 	v >>= OMAP4430_LASTPOWERSTATEENTERED_SHIFT;
- + 
- + 	return v;
- + }
- + 
- + static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
- + {
- + 	omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK,
- + 					(1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT),
- + 					pwrdm->prcm_partition,
- + 					pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
- + 	return 0;
- + }
- + 
- + static int omap4_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
- + {
- + 	omap4_prminst_rmw_inst_reg_bits(OMAP4430_LASTPOWERSTATEENTERED_MASK,
- + 					OMAP4430_LASTPOWERSTATEENTERED_MASK,
- + 					pwrdm->prcm_partition,
- + 					pwrdm->prcm_offs, pwrdm->pwrstst_offs);
- + 	return 0;
- + }
- + 
- + static int omap4_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
- + {
- + 	u32 v;
- + 
- + 	v = pwrst << __ffs(OMAP4430_LOGICRETSTATE_MASK);
- + 	omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v,
- + 					pwrdm->prcm_partition, pwrdm->prcm_offs,
- + 					pwrdm->pwrstctrl_offs);
- + 
- + 	return 0;
- + }
- + 
- + static int omap4_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
- + 				    u8 pwrst)
- + {
- + 	u32 m;
- + 
- + 	m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
- + 
- + 	omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
- + 					pwrdm->prcm_partition, pwrdm->prcm_offs,
- + 					pwrdm->pwrstctrl_offs);
- + 
- + 	return 0;
- + }
- + 
- + static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
- + 				     u8 pwrst)
- + {
- + 	u32 m;
- + 
- + 	m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
- + 
- + 	omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
- + 					pwrdm->prcm_partition, pwrdm->prcm_offs,
- + 					OMAP4_PM_PWSTCTRL);
- + 
- + 	return 0;
- + }
- + 
- + static int omap4_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
- + {
- + 	u32 v;
- + 
- + 	v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
- + 					pwrdm->pwrstst_offs);
- + 	v &= OMAP4430_LOGICSTATEST_MASK;
- + 	v >>= OMAP4430_LOGICSTATEST_SHIFT;
- + 
- + 	return v;
- + }
- + 
- + static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
- + {
- + 	u32 v;
- + 
- + 	v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
- + 					OMAP4_PM_PWSTCTRL);
- + 	v &= OMAP4430_LOGICRETSTATE_MASK;
- + 	v >>= OMAP4430_LOGICRETSTATE_SHIFT;
- + 
- + 	return v;
- + }
- + 
- + static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
- + {
- + 	u32 m, v;
- + 
- + 	m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
- + 
- + 	v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
- + 					pwrdm->pwrstst_offs);
- + 	v &= m;
- + 	v >>= __ffs(m);
- + 
- + 	return v;
- + }
- + 
- + static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
- + {
- + 	u32 m, v;
- + 
- + 	m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
- + 
- + 	v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
- + 					pwrdm->pwrstctrl_offs);
- + 	v &= m;
- + 	v >>= __ffs(m);
- + 
- + 	return v;
- + }
- + 
- + static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
- + {
- + 	u32 c = 0;
- + 
- + 	/*
- + 	 * REVISIT: pwrdm_wait_transition() may be better implemented
- + 	 * via a callback and a periodic timer check -- how long do we expect
- + 	 * powerdomain transitions to take?
- + 	 */
- + 
- + 	/* XXX Is this udelay() value meaningful? */
- + 	while ((omap4_prminst_read_inst_reg(pwrdm->prcm_partition,
- + 					    pwrdm->prcm_offs,
- + 					    pwrdm->pwrstst_offs) &
- + 		OMAP_INTRANSITION_MASK) &&
- + 	       (c++ < PWRDM_TRANSITION_BAILOUT))
- + 		udelay(1);
- + 
- + 	if (c > PWRDM_TRANSITION_BAILOUT) {
- + 		printk(KERN_ERR "powerdomain: waited too long for "
- + 		       "powerdomain %s to complete transition\n", pwrdm->name);
- + 		return -EAGAIN;
- + 	}
- + 
- + 	pr_debug("powerdomain: completed transition in %d loops\n", c);
- + 
- + 	return 0;
- + }
- + 
- + struct pwrdm_ops omap4_pwrdm_operations = {
- + 	.pwrdm_set_next_pwrst	= omap4_pwrdm_set_next_pwrst,
- + 	.pwrdm_read_next_pwrst	= omap4_pwrdm_read_next_pwrst,
- + 	.pwrdm_read_pwrst	= omap4_pwrdm_read_pwrst,
- + 	.pwrdm_read_prev_pwrst	= omap4_pwrdm_read_prev_pwrst,
- + 	.pwrdm_set_lowpwrstchange	= omap4_pwrdm_set_lowpwrstchange,
- + 	.pwrdm_clear_all_prev_pwrst	= omap4_pwrdm_clear_all_prev_pwrst,
- + 	.pwrdm_set_logic_retst	= omap4_pwrdm_set_logic_retst,
- + 	.pwrdm_read_logic_pwrst	= omap4_pwrdm_read_logic_pwrst,
- + 	.pwrdm_read_logic_retst	= omap4_pwrdm_read_logic_retst,
- + 	.pwrdm_read_mem_pwrst	= omap4_pwrdm_read_mem_pwrst,
- + 	.pwrdm_read_mem_retst	= omap4_pwrdm_read_mem_retst,
- + 	.pwrdm_set_mem_onst	= omap4_pwrdm_set_mem_onst,
- + 	.pwrdm_set_mem_retst	= omap4_pwrdm_set_mem_retst,
- + 	.pwrdm_wait_transition	= omap4_pwrdm_wait_transition,
- + };
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/powerdomain.c linux-3.2.1/arch/arm/mach-ckb_3352/powerdomain.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/powerdomain.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/powerdomain.c	2014-05-15 13:25:13.970604039 +0900
- ***************
- *** 0 ****
- --- 1,1066 ----
- + /*
- +  * OMAP powerdomain control
- +  *
- +  * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
- +  * Copyright (C) 2007-2011 Nokia Corporation
- +  *
- +  * Written by Paul Walmsley
- +  * Added OMAP4 specific support by Abhijit Pagare <abhijitpagare@ti.com>
- +  * State counting code by Tero Kristo <tero.kristo@nokia.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + #undef DEBUG
- + 
- + #include <linux/kernel.h>
- + #include <linux/types.h>
- + #include <linux/list.h>
- + #include <linux/errno.h>
- + #include <linux/string.h>
- + #include <trace/events/power.h>
- + 
- + #include "cm2xxx_3xxx.h"
- + #include "prcm44xx.h"
- + #include "cm44xx.h"
- + #include "prm2xxx_3xxx.h"
- + 
- + #include <asm/cpu.h>
- + #include <plat/cpu.h>
- + #include "powerdomain.h"
- + #include "clockdomain.h"
- + #include <plat/prcm.h>
- + 
- + #include "pm.h"
- + 
- + #define PWRDM_TRACE_STATES_FLAG	(1<<31)
- + 
- + enum {
- + 	PWRDM_STATE_NOW = 0,
- + 	PWRDM_STATE_PREV,
- + };
- + 
- + 
- + /* pwrdm_list contains all registered struct powerdomains */
- + static LIST_HEAD(pwrdm_list);
- + 
- + static struct pwrdm_ops *arch_pwrdm;
- + 
- + /* Private functions */
- + 
- + static struct powerdomain *_pwrdm_lookup(const char *name)
- + {
- + 	struct powerdomain *pwrdm, *temp_pwrdm;
- + 
- + 	pwrdm = NULL;
- + 
- + 	list_for_each_entry(temp_pwrdm, &pwrdm_list, node) {
- + 		if (!strcmp(name, temp_pwrdm->name)) {
- + 			pwrdm = temp_pwrdm;
- + 			break;
- + 		}
- + 	}
- + 
- + 	return pwrdm;
- + }
- + 
- + /**
- +  * _pwrdm_register - register a powerdomain
- +  * @pwrdm: struct powerdomain * to register
- +  *
- +  * Adds a powerdomain to the internal powerdomain list.  Returns
- +  * -EINVAL if given a null pointer, -EEXIST if a powerdomain is
- +  * already registered by the provided name, or 0 upon success.
- +  */
- + static int _pwrdm_register(struct powerdomain *pwrdm)
- + {
- + 	int i;
- + 	struct voltagedomain *voltdm;
- + 
- + 	if (!pwrdm || !pwrdm->name)
- + 		return -EINVAL;
- + 
- + 	if (_pwrdm_lookup(pwrdm->name))
- + 		return -EEXIST;
- + 
- + 	voltdm = voltdm_lookup(pwrdm->voltdm.name);
- + 	if (!voltdm) {
- + 		pr_err("powerdomain: %s: voltagedomain %s does not exist\n",
- + 		       pwrdm->name, pwrdm->voltdm.name);
- + 		return -EINVAL;
- + 	}
- + 	pwrdm->voltdm.ptr = voltdm;
- + 	INIT_LIST_HEAD(&pwrdm->voltdm_node);
- + 	voltdm_add_pwrdm(voltdm, pwrdm);
- + 
- + 	list_add(&pwrdm->node, &pwrdm_list);
- + 
- + 	/* Initialize the powerdomain's state counter */
- + 	for (i = 0; i < PWRDM_MAX_PWRSTS; i++)
- + 		pwrdm->state_counter[i] = 0;
- + 
- + 	pwrdm->ret_logic_off_counter = 0;
- + 	for (i = 0; i < pwrdm->banks; i++)
- + 		pwrdm->ret_mem_off_counter[i] = 0;
- + 
- + 	pwrdm_wait_transition(pwrdm);
- + 	pwrdm->state = pwrdm_read_pwrst(pwrdm);
- + 	pwrdm->state_counter[pwrdm->state] = 1;
- + 
- + 	pr_debug("powerdomain: registered %s\n", pwrdm->name);
- + 
- + 	return 0;
- + }
- + 
- + static void _update_logic_membank_counters(struct powerdomain *pwrdm)
- + {
- + 	int i;
- + 	u8 prev_logic_pwrst, prev_mem_pwrst;
- + 
- + 	prev_logic_pwrst = pwrdm_read_prev_logic_pwrst(pwrdm);
- + 	if ((pwrdm->pwrsts_logic_ret == PWRSTS_OFF_RET) &&
- + 	    (prev_logic_pwrst == PWRDM_POWER_OFF))
- + 		pwrdm->ret_logic_off_counter++;
- + 
- + 	for (i = 0; i < pwrdm->banks; i++) {
- + 		prev_mem_pwrst = pwrdm_read_prev_mem_pwrst(pwrdm, i);
- + 
- + 		if ((pwrdm->pwrsts_mem_ret[i] == PWRSTS_OFF_RET) &&
- + 		    (prev_mem_pwrst == PWRDM_POWER_OFF))
- + 			pwrdm->ret_mem_off_counter[i]++;
- + 	}
- + }
- + 
- + static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
- + {
- + 
- + 	int prev, state, trace_state = 0;
- + 
- + 	if (pwrdm == NULL)
- + 		return -EINVAL;
- + 
- + 	state = pwrdm_read_pwrst(pwrdm);
- + 
- + 	switch (flag) {
- + 	case PWRDM_STATE_NOW:
- + 		prev = pwrdm->state;
- + 		break;
- + 	case PWRDM_STATE_PREV:
- + 		prev = pwrdm_read_prev_pwrst(pwrdm);
- + 		if (pwrdm->state != prev)
- + 			pwrdm->state_counter[prev]++;
- + 		if (prev == PWRDM_POWER_RET)
- + 			_update_logic_membank_counters(pwrdm);
- + 		/*
- + 		 * If the power domain did not hit the desired state,
- + 		 * generate a trace event with both the desired and hit states
- + 		 */
- + 		if (state != prev) {
- + 			trace_state = (PWRDM_TRACE_STATES_FLAG |
- + 				       ((state & OMAP_POWERSTATE_MASK) << 8) |
- + 				       ((prev & OMAP_POWERSTATE_MASK) << 0));
- + 			trace_power_domain_target(pwrdm->name, trace_state,
- + 						  smp_processor_id());
- + 		}
- + 		break;
- + 	default:
- + 		return -EINVAL;
- + 	}
- + 
- + 	if (state != prev)
- + 		pwrdm->state_counter[state]++;
- + 
- + 	pm_dbg_update_time(pwrdm, prev);
- + 
- + 	pwrdm->state = state;
- + 
- + 	return 0;
- + }
- + 
- + static int _pwrdm_pre_transition_cb(struct powerdomain *pwrdm, void *unused)
- + {
- + 	pwrdm_clear_all_prev_pwrst(pwrdm);
- + 	_pwrdm_state_switch(pwrdm, PWRDM_STATE_NOW);
- + 	return 0;
- + }
- + 
- + static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused)
- + {
- + 	_pwrdm_state_switch(pwrdm, PWRDM_STATE_PREV);
- + 	return 0;
- + }
- + 
- + /* Public functions */
- + 
- + /**
- +  * pwrdm_register_platform_funcs - register powerdomain implementation fns
- +  * @po: func pointers for arch specific implementations
- +  *
- +  * Register the list of function pointers used to implement the
- +  * powerdomain functions on different OMAP SoCs.  Should be called
- +  * before any other pwrdm_register*() function.  Returns -EINVAL if
- +  * @po is null, -EEXIST if platform functions have already been
- +  * registered, or 0 upon success.
- +  */
- + int pwrdm_register_platform_funcs(struct pwrdm_ops *po)
- + {
- + 	if (!po)
- + 		return -EINVAL;
- + 
- + 	if (arch_pwrdm)
- + 		return -EEXIST;
- + 
- + 	arch_pwrdm = po;
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * pwrdm_register_pwrdms - register SoC powerdomains
- +  * @ps: pointer to an array of struct powerdomain to register
- +  *
- +  * Register the powerdomains available on a particular OMAP SoC.  Must
- +  * be called after pwrdm_register_platform_funcs().  May be called
- +  * multiple times.  Returns -EACCES if called before
- +  * pwrdm_register_platform_funcs(); -EINVAL if the argument @ps is
- +  * null; or 0 upon success.
- +  */
- + int pwrdm_register_pwrdms(struct powerdomain **ps)
- + {
- + 	struct powerdomain **p = NULL;
- + 
- + 	if (!arch_pwrdm)
- + 		return -EEXIST;
- + 
- + 	if (!ps)
- + 		return -EINVAL;
- + 
- + 	for (p = ps; *p; p++)
- + 		_pwrdm_register(*p);
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * pwrdm_complete_init - set up the powerdomain layer
- +  *
- +  * Do whatever is necessary to initialize registered powerdomains and
- +  * powerdomain code.  Currently, this programs the next power state
- +  * for each powerdomain to ON.  This prevents powerdomains from
- +  * unexpectedly losing context or entering high wakeup latency modes
- +  * with non-power-management-enabled kernels.  Must be called after
- +  * pwrdm_register_pwrdms().  Returns -EACCES if called before
- +  * pwrdm_register_pwrdms(), or 0 upon success.
- +  */
- + int pwrdm_complete_init(void)
- + {
- + 	struct powerdomain *temp_p;
- + 
- + 	if (list_empty(&pwrdm_list))
- + 		return -EACCES;
- + 
- + 	list_for_each_entry(temp_p, &pwrdm_list, node)
- + 		pwrdm_set_next_pwrst(temp_p, PWRDM_POWER_ON);
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * pwrdm_lookup - look up a powerdomain by name, return a pointer
- +  * @name: name of powerdomain
- +  *
- +  * Find a registered powerdomain by its name @name.  Returns a pointer
- +  * to the struct powerdomain if found, or NULL otherwise.
- +  */
- + struct powerdomain *pwrdm_lookup(const char *name)
- + {
- + 	struct powerdomain *pwrdm;
- + 
- + 	if (!name)
- + 		return NULL;
- + 
- + 	pwrdm = _pwrdm_lookup(name);
- + 
- + 	return pwrdm;
- + }
- + 
- + /**
- +  * pwrdm_for_each - call function on each registered clockdomain
- +  * @fn: callback function *
- +  *
- +  * Call the supplied function @fn for each registered powerdomain.
- +  * The callback function @fn can return anything but 0 to bail out
- +  * early from the iterator.  Returns the last return value of the
- +  * callback function, which should be 0 for success or anything else
- +  * to indicate failure; or -EINVAL if the function pointer is null.
- +  */
- + int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
- + 		   void *user)
- + {
- + 	struct powerdomain *temp_pwrdm;
- + 	int ret = 0;
- + 
- + 	if (!fn)
- + 		return -EINVAL;
- + 
- + 	list_for_each_entry(temp_pwrdm, &pwrdm_list, node) {
- + 		ret = (*fn)(temp_pwrdm, user);
- + 		if (ret)
- + 			break;
- + 	}
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * pwrdm_add_clkdm - add a clockdomain to a powerdomain
- +  * @pwrdm: struct powerdomain * to add the clockdomain to
- +  * @clkdm: struct clockdomain * to associate with a powerdomain
- +  *
- +  * Associate the clockdomain @clkdm with a powerdomain @pwrdm.  This
- +  * enables the use of pwrdm_for_each_clkdm().  Returns -EINVAL if
- +  * presented with invalid pointers; -ENOMEM if memory could not be allocated;
- +  * or 0 upon success.
- +  */
- + int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
- + {
- + 	int i;
- + 	int ret = -EINVAL;
- + 
- + 	if (!pwrdm || !clkdm)
- + 		return -EINVAL;
- + 
- + 	pr_debug("powerdomain: associating clockdomain %s with powerdomain "
- + 		 "%s\n", clkdm->name, pwrdm->name);
- + 
- + 	for (i = 0; i < PWRDM_MAX_CLKDMS; i++) {
- + 		if (!pwrdm->pwrdm_clkdms[i])
- + 			break;
- + #ifdef DEBUG
- + 		if (pwrdm->pwrdm_clkdms[i] == clkdm) {
- + 			ret = -EINVAL;
- + 			goto pac_exit;
- + 		}
- + #endif
- + 	}
- + 
- + 	if (i == PWRDM_MAX_CLKDMS) {
- + 		pr_debug("powerdomain: increase PWRDM_MAX_CLKDMS for "
- + 			 "pwrdm %s clkdm %s\n", pwrdm->name, clkdm->name);
- + 		WARN_ON(1);
- + 		ret = -ENOMEM;
- + 		goto pac_exit;
- + 	}
- + 
- + 	pwrdm->pwrdm_clkdms[i] = clkdm;
- + 
- + 	ret = 0;
- + 
- + pac_exit:
- + 	return ret;
- + }
- + 
- + /**
- +  * pwrdm_del_clkdm - remove a clockdomain from a powerdomain
- +  * @pwrdm: struct powerdomain * to add the clockdomain to
- +  * @clkdm: struct clockdomain * to associate with a powerdomain
- +  *
- +  * Dissociate the clockdomain @clkdm from the powerdomain
- +  * @pwrdm. Returns -EINVAL if presented with invalid pointers; -ENOENT
- +  * if @clkdm was not associated with the powerdomain, or 0 upon
- +  * success.
- +  */
- + int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
- + {
- + 	int ret = -EINVAL;
- + 	int i;
- + 
- + 	if (!pwrdm || !clkdm)
- + 		return -EINVAL;
- + 
- + 	pr_debug("powerdomain: dissociating clockdomain %s from powerdomain "
- + 		 "%s\n", clkdm->name, pwrdm->name);
- + 
- + 	for (i = 0; i < PWRDM_MAX_CLKDMS; i++)
- + 		if (pwrdm->pwrdm_clkdms[i] == clkdm)
- + 			break;
- + 
- + 	if (i == PWRDM_MAX_CLKDMS) {
- + 		pr_debug("powerdomain: clkdm %s not associated with pwrdm "
- + 			 "%s ?!\n", clkdm->name, pwrdm->name);
- + 		ret = -ENOENT;
- + 		goto pdc_exit;
- + 	}
- + 
- + 	pwrdm->pwrdm_clkdms[i] = NULL;
- + 
- + 	ret = 0;
- + 
- + pdc_exit:
- + 	return ret;
- + }
- + 
- + /**
- +  * pwrdm_for_each_clkdm - call function on each clkdm in a pwrdm
- +  * @pwrdm: struct powerdomain * to iterate over
- +  * @fn: callback function *
- +  *
- +  * Call the supplied function @fn for each clockdomain in the powerdomain
- +  * @pwrdm.  The callback function can return anything but 0 to bail
- +  * out early from the iterator.  Returns -EINVAL if presented with
- +  * invalid pointers; or passes along the last return value of the
- +  * callback function, which should be 0 for success or anything else
- +  * to indicate failure.
- +  */
- + int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
- + 			 int (*fn)(struct powerdomain *pwrdm,
- + 				   struct clockdomain *clkdm))
- + {
- + 	int ret = 0;
- + 	int i;
- + 
- + 	if (!fn)
- + 		return -EINVAL;
- + 
- + 	for (i = 0; i < PWRDM_MAX_CLKDMS && !ret; i++)
- + 		ret = (*fn)(pwrdm, pwrdm->pwrdm_clkdms[i]);
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * pwrdm_get_voltdm - return a ptr to the voltdm that this pwrdm resides in
- +  * @pwrdm: struct powerdomain *
- +  *
- +  * Return a pointer to the struct voltageomain that the specified powerdomain
- +  * @pwrdm exists in.
- +  */
- + struct voltagedomain *pwrdm_get_voltdm(struct powerdomain *pwrdm)
- + {
- + 	return pwrdm->voltdm.ptr;
- + }
- + 
- + /**
- +  * pwrdm_get_mem_bank_count - get number of memory banks in this powerdomain
- +  * @pwrdm: struct powerdomain *
- +  *
- +  * Return the number of controllable memory banks in powerdomain @pwrdm,
- +  * starting with 1.  Returns -EINVAL if the powerdomain pointer is null.
- +  */
- + int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm)
- + {
- + 	if (!pwrdm)
- + 		return -EINVAL;
- + 
- + 	return pwrdm->banks;
- + }
- + 
- + /**
- +  * pwrdm_set_next_pwrst - set next powerdomain power state
- +  * @pwrdm: struct powerdomain * to set
- +  * @pwrst: one of the PWRDM_POWER_* macros
- +  *
- +  * Set the powerdomain @pwrdm's next power state to @pwrst.  The powerdomain
- +  * may not enter this state immediately if the preconditions for this state
- +  * have not been satisfied.  Returns -EINVAL if the powerdomain pointer is
- +  * null or if the power state is invalid for the powerdomin, or returns 0
- +  * upon success.
- +  */
- + int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
- + {
- + 	int ret = -EINVAL;
- + 
- + 	if (!pwrdm)
- + 		return -EINVAL;
- + 
- + 	if (!(pwrdm->pwrsts & (1 << pwrst)))
- + 		return -EINVAL;
- + 
- + 	pr_debug("powerdomain: setting next powerstate for %s to %0x\n",
- + 		 pwrdm->name, pwrst);
- + 
- + 	if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst) {
- + 		/* Trace the pwrdm desired target state */
- + 		trace_power_domain_target(pwrdm->name, pwrst,
- + 					  smp_processor_id());
- + 		/* Program the pwrdm desired target state */
- + 		ret = arch_pwrdm->pwrdm_set_next_pwrst(pwrdm, pwrst);
- + 	}
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * pwrdm_read_next_pwrst - get next powerdomain power state
- +  * @pwrdm: struct powerdomain * to get power state
- +  *
- +  * Return the powerdomain @pwrdm's next power state.  Returns -EINVAL
- +  * if the powerdomain pointer is null or returns the next power state
- +  * upon success.
- +  */
- + int pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
- + {
- + 	int ret = -EINVAL;
- + 
- + 	if (!pwrdm)
- + 		return -EINVAL;
- + 
- + 	if (arch_pwrdm && arch_pwrdm->pwrdm_read_next_pwrst)
- + 		ret = arch_pwrdm->pwrdm_read_next_pwrst(pwrdm);
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * pwrdm_read_pwrst - get current powerdomain power state
- +  * @pwrdm: struct powerdomain * to get power state
- +  *
- +  * Return the powerdomain @pwrdm's current power state.	Returns -EINVAL
- +  * if the powerdomain pointer is null or returns the current power state
- +  * upon success.
- +  */
- + int pwrdm_read_pwrst(struct powerdomain *pwrdm)
- + {
- + 	int ret = -EINVAL;
- + 
- + 	if (!pwrdm)
- + 		return -EINVAL;
- + 
- + 	if (arch_pwrdm && arch_pwrdm->pwrdm_read_pwrst)
- + 		ret = arch_pwrdm->pwrdm_read_pwrst(pwrdm);
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * pwrdm_read_prev_pwrst - get previous powerdomain power state
- +  * @pwrdm: struct powerdomain * to get previous power state
- +  *
- +  * Return the powerdomain @pwrdm's previous power state.  Returns -EINVAL
- +  * if the powerdomain pointer is null or returns the previous power state
- +  * upon success.
- +  */
- + int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
- + {
- + 	int ret = -EINVAL;
- + 
- + 	if (!pwrdm)
- + 		return -EINVAL;
- + 
- + 	if (arch_pwrdm && arch_pwrdm->pwrdm_read_prev_pwrst)
- + 		ret = arch_pwrdm->pwrdm_read_prev_pwrst(pwrdm);
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * pwrdm_set_logic_retst - set powerdomain logic power state upon retention
- +  * @pwrdm: struct powerdomain * to set
- +  * @pwrst: one of the PWRDM_POWER_* macros
- +  *
- +  * Set the next power state @pwrst that the logic portion of the
- +  * powerdomain @pwrdm will enter when the powerdomain enters retention.
- +  * This will be either RETENTION or OFF, if supported.  Returns
- +  * -EINVAL if the powerdomain pointer is null or the target power
- +  * state is not not supported, or returns 0 upon success.
- +  */
- + int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
- + {
- + 	int ret = -EINVAL;
- + 
- + 	if (!pwrdm)
- + 		return -EINVAL;
- + 
- + 	if (!(pwrdm->pwrsts_logic_ret & (1 << pwrst)))
- + 		return -EINVAL;
- + 
- + 	pr_debug("powerdomain: setting next logic powerstate for %s to %0x\n",
- + 		 pwrdm->name, pwrst);
- + 
- + 	if (arch_pwrdm && arch_pwrdm->pwrdm_set_logic_retst)
- + 		ret = arch_pwrdm->pwrdm_set_logic_retst(pwrdm, pwrst);
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * pwrdm_set_mem_onst - set memory power state while powerdomain ON
- +  * @pwrdm: struct powerdomain * to set
- +  * @bank: memory bank number to set (0-3)
- +  * @pwrst: one of the PWRDM_POWER_* macros
- +  *
- +  * Set the next power state @pwrst that memory bank @bank of the
- +  * powerdomain @pwrdm will enter when the powerdomain enters the ON
- +  * state.  @bank will be a number from 0 to 3, and represents different
- +  * types of memory, depending on the powerdomain.  Returns -EINVAL if
- +  * the powerdomain pointer is null or the target power state is not
- +  * not supported for this memory bank, -EEXIST if the target memory
- +  * bank does not exist or is not controllable, or returns 0 upon
- +  * success.
- +  */
- + int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
- + {
- + 	int ret = -EINVAL;
- + 
- + 	if (!pwrdm)
- + 		return -EINVAL;
- + 
- + 	if (pwrdm->banks < (bank + 1))
- + 		return -EEXIST;
- + 
- + 	if (!(pwrdm->pwrsts_mem_on[bank] & (1 << pwrst)))
- + 		return -EINVAL;
- + 
- + 	pr_debug("powerdomain: setting next memory powerstate for domain %s "
- + 		 "bank %0x while pwrdm-ON to %0x\n", pwrdm->name, bank, pwrst);
- + 
- + 	if (arch_pwrdm && arch_pwrdm->pwrdm_set_mem_onst)
- + 		ret = arch_pwrdm->pwrdm_set_mem_onst(pwrdm, bank, pwrst);
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * pwrdm_set_mem_retst - set memory power state while powerdomain in RET
- +  * @pwrdm: struct powerdomain * to set
- +  * @bank: memory bank number to set (0-3)
- +  * @pwrst: one of the PWRDM_POWER_* macros
- +  *
- +  * Set the next power state @pwrst that memory bank @bank of the
- +  * powerdomain @pwrdm will enter when the powerdomain enters the
- +  * RETENTION state.  Bank will be a number from 0 to 3, and represents
- +  * different types of memory, depending on the powerdomain.  @pwrst
- +  * will be either RETENTION or OFF, if supported.  Returns -EINVAL if
- +  * the powerdomain pointer is null or the target power state is not
- +  * not supported for this memory bank, -EEXIST if the target memory
- +  * bank does not exist or is not controllable, or returns 0 upon
- +  * success.
- +  */
- + int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
- + {
- + 	int ret = -EINVAL;
- + 
- + 	if (!pwrdm)
- + 		return -EINVAL;
- + 
- + 	if (pwrdm->banks < (bank + 1))
- + 		return -EEXIST;
- + 
- + 	if (!(pwrdm->pwrsts_mem_ret[bank] & (1 << pwrst)))
- + 		return -EINVAL;
- + 
- + 	pr_debug("powerdomain: setting next memory powerstate for domain %s "
- + 		 "bank %0x while pwrdm-RET to %0x\n", pwrdm->name, bank, pwrst);
- + 
- + 	if (arch_pwrdm && arch_pwrdm->pwrdm_set_mem_retst)
- + 		ret = arch_pwrdm->pwrdm_set_mem_retst(pwrdm, bank, pwrst);
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * pwrdm_read_logic_pwrst - get current powerdomain logic retention power state
- +  * @pwrdm: struct powerdomain * to get current logic retention power state
- +  *
- +  * Return the power state that the logic portion of powerdomain @pwrdm
- +  * will enter when the powerdomain enters retention.  Returns -EINVAL
- +  * if the powerdomain pointer is null or returns the logic retention
- +  * power state upon success.
- +  */
- + int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
- + {
- + 	int ret = -EINVAL;
- + 
- + 	if (!pwrdm)
- + 		return -EINVAL;
- + 
- + 	if (arch_pwrdm && arch_pwrdm->pwrdm_read_logic_pwrst)
- + 		ret = arch_pwrdm->pwrdm_read_logic_pwrst(pwrdm);
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * pwrdm_read_prev_logic_pwrst - get previous powerdomain logic power state
- +  * @pwrdm: struct powerdomain * to get previous logic power state
- +  *
- +  * Return the powerdomain @pwrdm's previous logic power state.  Returns
- +  * -EINVAL if the powerdomain pointer is null or returns the previous
- +  * logic power state upon success.
- +  */
- + int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
- + {
- + 	int ret = -EINVAL;
- + 
- + 	if (!pwrdm)
- + 		return -EINVAL;
- + 
- + 	if (arch_pwrdm && arch_pwrdm->pwrdm_read_prev_logic_pwrst)
- + 		ret = arch_pwrdm->pwrdm_read_prev_logic_pwrst(pwrdm);
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * pwrdm_read_logic_retst - get next powerdomain logic power state
- +  * @pwrdm: struct powerdomain * to get next logic power state
- +  *
- +  * Return the powerdomain pwrdm's logic power state.  Returns -EINVAL
- +  * if the powerdomain pointer is null or returns the next logic
- +  * power state upon success.
- +  */
- + int pwrdm_read_logic_retst(struct powerdomain *pwrdm)
- + {
- + 	int ret = -EINVAL;
- + 
- + 	if (!pwrdm)
- + 		return -EINVAL;
- + 
- + 	if (arch_pwrdm && arch_pwrdm->pwrdm_read_logic_retst)
- + 		ret = arch_pwrdm->pwrdm_read_logic_retst(pwrdm);
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * pwrdm_read_mem_pwrst - get current memory bank power state
- +  * @pwrdm: struct powerdomain * to get current memory bank power state
- +  * @bank: memory bank number (0-3)
- +  *
- +  * Return the powerdomain @pwrdm's current memory power state for bank
- +  * @bank.  Returns -EINVAL if the powerdomain pointer is null, -EEXIST if
- +  * the target memory bank does not exist or is not controllable, or
- +  * returns the current memory power state upon success.
- +  */
- + int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
- + {
- + 	int ret = -EINVAL;
- + 
- + 	if (!pwrdm)
- + 		return ret;
- + 
- + 	if (pwrdm->banks < (bank + 1))
- + 		return ret;
- + 
- + 	if (pwrdm->flags & PWRDM_HAS_MPU_QUIRK)
- + 		bank = 1;
- + 
- + 	if (arch_pwrdm && arch_pwrdm->pwrdm_read_mem_pwrst)
- + 		ret = arch_pwrdm->pwrdm_read_mem_pwrst(pwrdm, bank);
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * pwrdm_read_prev_mem_pwrst - get previous memory bank power state
- +  * @pwrdm: struct powerdomain * to get previous memory bank power state
- +  * @bank: memory bank number (0-3)
- +  *
- +  * Return the powerdomain @pwrdm's previous memory power state for
- +  * bank @bank.  Returns -EINVAL if the powerdomain pointer is null,
- +  * -EEXIST if the target memory bank does not exist or is not
- +  * controllable, or returns the previous memory power state upon
- +  * success.
- +  */
- + int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
- + {
- + 	int ret = -EINVAL;
- + 
- + 	if (!pwrdm)
- + 		return ret;
- + 
- + 	if (pwrdm->banks < (bank + 1))
- + 		return ret;
- + 
- + 	if (pwrdm->flags & PWRDM_HAS_MPU_QUIRK)
- + 		bank = 1;
- + 
- + 	if (arch_pwrdm && arch_pwrdm->pwrdm_read_prev_mem_pwrst)
- + 		ret = arch_pwrdm->pwrdm_read_prev_mem_pwrst(pwrdm, bank);
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * pwrdm_read_mem_retst - get next memory bank power state
- +  * @pwrdm: struct powerdomain * to get mext memory bank power state
- +  * @bank: memory bank number (0-3)
- +  *
- +  * Return the powerdomain pwrdm's next memory power state for bank
- +  * x.  Returns -EINVAL if the powerdomain pointer is null, -EEXIST if
- +  * the target memory bank does not exist or is not controllable, or
- +  * returns the next memory power state upon success.
- +  */
- + int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
- + {
- + 	int ret = -EINVAL;
- + 
- + 	if (!pwrdm)
- + 		return ret;
- + 
- + 	if (pwrdm->banks < (bank + 1))
- + 		return ret;
- + 
- + 	if (arch_pwrdm && arch_pwrdm->pwrdm_read_mem_retst)
- + 		ret = arch_pwrdm->pwrdm_read_mem_retst(pwrdm, bank);
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * pwrdm_clear_all_prev_pwrst - clear previous powerstate register for a pwrdm
- +  * @pwrdm: struct powerdomain * to clear
- +  *
- +  * Clear the powerdomain's previous power state register @pwrdm.
- +  * Clears the entire register, including logic and memory bank
- +  * previous power states.  Returns -EINVAL if the powerdomain pointer
- +  * is null, or returns 0 upon success.
- +  */
- + int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
- + {
- + 	int ret = -EINVAL;
- + 
- + 	if (!pwrdm)
- + 		return ret;
- + 
- + 	/*
- + 	 * XXX should get the powerdomain's current state here;
- + 	 * warn & fail if it is not ON.
- + 	 */
- + 
- + 	pr_debug("powerdomain: clearing previous power state reg for %s\n",
- + 		 pwrdm->name);
- + 
- + 	if (arch_pwrdm && arch_pwrdm->pwrdm_clear_all_prev_pwrst)
- + 		ret = arch_pwrdm->pwrdm_clear_all_prev_pwrst(pwrdm);
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * pwrdm_enable_hdwr_sar - enable automatic hardware SAR for a pwrdm
- +  * @pwrdm: struct powerdomain *
- +  *
- +  * Enable automatic context save-and-restore upon power state change
- +  * for some devices in the powerdomain @pwrdm.  Warning: this only
- +  * affects a subset of devices in a powerdomain; check the TRM
- +  * closely.  Returns -EINVAL if the powerdomain pointer is null or if
- +  * the powerdomain does not support automatic save-and-restore, or
- +  * returns 0 upon success.
- +  */
- + int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
- + {
- + 	int ret = -EINVAL;
- + 
- + 	if (!pwrdm)
- + 		return ret;
- + 
- + 	if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR))
- + 		return ret;
- + 
- + 	pr_debug("powerdomain: %s: setting SAVEANDRESTORE bit\n",
- + 		 pwrdm->name);
- + 
- + 	if (arch_pwrdm && arch_pwrdm->pwrdm_enable_hdwr_sar)
- + 		ret = arch_pwrdm->pwrdm_enable_hdwr_sar(pwrdm);
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * pwrdm_disable_hdwr_sar - disable automatic hardware SAR for a pwrdm
- +  * @pwrdm: struct powerdomain *
- +  *
- +  * Disable automatic context save-and-restore upon power state change
- +  * for some devices in the powerdomain @pwrdm.  Warning: this only
- +  * affects a subset of devices in a powerdomain; check the TRM
- +  * closely.  Returns -EINVAL if the powerdomain pointer is null or if
- +  * the powerdomain does not support automatic save-and-restore, or
- +  * returns 0 upon success.
- +  */
- + int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
- + {
- + 	int ret = -EINVAL;
- + 
- + 	if (!pwrdm)
- + 		return ret;
- + 
- + 	if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR))
- + 		return ret;
- + 
- + 	pr_debug("powerdomain: %s: clearing SAVEANDRESTORE bit\n",
- + 		 pwrdm->name);
- + 
- + 	if (arch_pwrdm && arch_pwrdm->pwrdm_disable_hdwr_sar)
- + 		ret = arch_pwrdm->pwrdm_disable_hdwr_sar(pwrdm);
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * pwrdm_has_hdwr_sar - test whether powerdomain supports hardware SAR
- +  * @pwrdm: struct powerdomain *
- +  *
- +  * Returns 1 if powerdomain @pwrdm supports hardware save-and-restore
- +  * for some devices, or 0 if it does not.
- +  */
- + bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm)
- + {
- + 	return (pwrdm && pwrdm->flags & PWRDM_HAS_HDWR_SAR) ? 1 : 0;
- + }
- + 
- + /**
- +  * pwrdm_set_lowpwrstchange - Request a low power state change
- +  * @pwrdm: struct powerdomain *
- +  *
- +  * Allows a powerdomain to transtion to a lower power sleep state
- +  * from an existing sleep state without waking up the powerdomain.
- +  * Returns -EINVAL if the powerdomain pointer is null or if the
- +  * powerdomain does not support LOWPOWERSTATECHANGE, or returns 0
- +  * upon success.
- +  */
- + int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
- + {
- + 	int ret = -EINVAL;
- + 
- + 	if (!pwrdm)
- + 		return -EINVAL;
- + 
- + 	if (!(pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE))
- + 		return -EINVAL;
- + 
- + 	pr_debug("powerdomain: %s: setting LOWPOWERSTATECHANGE bit\n",
- + 		 pwrdm->name);
- + 
- + 	if (arch_pwrdm && arch_pwrdm->pwrdm_set_lowpwrstchange)
- + 		ret = arch_pwrdm->pwrdm_set_lowpwrstchange(pwrdm);
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * pwrdm_wait_transition - wait for powerdomain power transition to finish
- +  * @pwrdm: struct powerdomain * to wait for
- +  *
- +  * If the powerdomain @pwrdm is in the process of a state transition,
- +  * spin until it completes the power transition, or until an iteration
- +  * bailout value is reached. Returns -EINVAL if the powerdomain
- +  * pointer is null, -EAGAIN if the bailout value was reached, or
- +  * returns 0 upon success.
- +  */
- + int pwrdm_wait_transition(struct powerdomain *pwrdm)
- + {
- + 	int ret = -EINVAL;
- + 
- + 	if (!pwrdm)
- + 		return -EINVAL;
- + 
- + 	if (arch_pwrdm && arch_pwrdm->pwrdm_wait_transition)
- + 		ret = arch_pwrdm->pwrdm_wait_transition(pwrdm);
- + 
- + 	return ret;
- + }
- + 
- + int pwrdm_state_switch(struct powerdomain *pwrdm)
- + {
- + 	return _pwrdm_state_switch(pwrdm, PWRDM_STATE_NOW);
- + }
- + 
- + int pwrdm_clkdm_state_switch(struct clockdomain *clkdm)
- + {
- + 	if (clkdm != NULL && clkdm->pwrdm.ptr != NULL) {
- + 		pwrdm_wait_transition(clkdm->pwrdm.ptr);
- + 		return pwrdm_state_switch(clkdm->pwrdm.ptr);
- + 	}
- + 
- + 	return -EINVAL;
- + }
- + 
- + int pwrdm_pre_transition(void)
- + {
- + 	pwrdm_for_each(_pwrdm_pre_transition_cb, NULL);
- + 	return 0;
- + }
- + 
- + int pwrdm_post_transition(void)
- + {
- + 	pwrdm_for_each(_pwrdm_post_transition_cb, NULL);
- + 	return 0;
- + }
- + 
- + /**
- +  * pwrdm_get_context_loss_count - get powerdomain's context loss count
- +  * @pwrdm: struct powerdomain * to wait for
- +  *
- +  * Context loss count is the sum of powerdomain off-mode counter, the
- +  * logic off counter and the per-bank memory off counter.  Returns negative
- +  * (and WARNs) upon error, otherwise, returns the context loss count.
- +  */
- + int pwrdm_get_context_loss_count(struct powerdomain *pwrdm)
- + {
- + 	int i, count;
- + 
- + 	if (!pwrdm) {
- + 		WARN(1, "powerdomain: %s: pwrdm is null\n", __func__);
- + 		return -ENODEV;
- + 	}
- + 
- + 	count = pwrdm->state_counter[PWRDM_POWER_OFF];
- + 	count += pwrdm->ret_logic_off_counter;
- + 
- + 	for (i = 0; i < pwrdm->banks; i++)
- + 		count += pwrdm->ret_mem_off_counter[i];
- + 
- + 	/*
- + 	 * Context loss count has to be a non-negative value. Clear the sign
- + 	 * bit to get a value range from 0 to INT_MAX.
- + 	 */
- + 	count &= INT_MAX;
- + 
- + 	pr_debug("powerdomain: %s: context loss count = %d\n",
- + 		 pwrdm->name, count);
- + 
- + 	return count;
- + }
- + 
- + /**
- +  * pwrdm_can_ever_lose_context - can this powerdomain ever lose context?
- +  * @pwrdm: struct powerdomain *
- +  *
- +  * Given a struct powerdomain * @pwrdm, returns 1 if the powerdomain
- +  * can lose either memory or logic context or if @pwrdm is invalid, or
- +  * returns 0 otherwise.  This function is not concerned with how the
- +  * powerdomain registers are programmed (i.e., to go off or not); it's
- +  * concerned with whether it's ever possible for this powerdomain to
- +  * go off while some other part of the chip is active.  This function
- +  * assumes that every powerdomain can go to either ON or INACTIVE.
- +  */
- + bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm)
- + {
- + 	int i;
- + 
- + 	if (IS_ERR_OR_NULL(pwrdm)) {
- + 		pr_debug("powerdomain: %s: invalid powerdomain pointer\n",
- + 			 __func__);
- + 		return 1;
- + 	}
- + 
- + 	if (pwrdm->pwrsts & PWRSTS_OFF)
- + 		return 1;
- + 
- + 	if (pwrdm->pwrsts & PWRSTS_RET) {
- + 		if (pwrdm->pwrsts_logic_ret & PWRSTS_OFF)
- + 			return 1;
- + 
- + 		for (i = 0; i < pwrdm->banks; i++)
- + 			if (pwrdm->pwrsts_mem_ret[i] & PWRSTS_OFF)
- + 				return 1;
- + 	}
- + 
- + 	for (i = 0; i < pwrdm->banks; i++)
- + 		if (pwrdm->pwrsts_mem_on[i] & PWRSTS_OFF)
- + 			return 1;
- + 
- + 	return 0;
- + }
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/powerdomain-common.c linux-3.2.1/arch/arm/mach-ckb_3352/powerdomain-common.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/powerdomain-common.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/powerdomain-common.c	2014-05-15 13:25:13.970604039 +0900
- ***************
- *** 0 ****
- --- 1,109 ----
- + /*
- +  * Common powerdomain framework functions
- +  *
- +  * Copyright (C) 2010-2011 Texas Instruments, Inc.
- +  * Copyright (C) 2010 Nokia Corporation
- +  *
- +  * Derived from mach-omap2/powerdomain.c written by Paul Walmsley
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #include <linux/errno.h>
- + #include <linux/kernel.h>
- + #include "pm.h"
- + #include "cm.h"
- + #include "cm-regbits-34xx.h"
- + #include "cm-regbits-44xx.h"
- + #include "prm-regbits-34xx.h"
- + #include "prm-regbits-44xx.h"
- + 
- + /*
- +  * OMAP3 and OMAP4 specific register bit initialisations
- +  * Notice that the names here are not according to each power
- +  * domain but the bit mapping used applies to all of them
- +  */
- + /* OMAP3 and OMAP4 Memory Onstate Masks (common across all power domains) */
- + #define OMAP_MEM0_ONSTATE_MASK OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK
- + #define OMAP_MEM1_ONSTATE_MASK OMAP3430_L1FLATMEMONSTATE_MASK
- + #define OMAP_MEM2_ONSTATE_MASK OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK
- + #define OMAP_MEM3_ONSTATE_MASK OMAP3430_L2FLATMEMONSTATE_MASK
- + #define OMAP_MEM4_ONSTATE_MASK OMAP4430_OCP_NRET_BANK_ONSTATE_MASK
- + 
- + /* OMAP3 and OMAP4 Memory Retstate Masks (common across all power domains) */
- + #define OMAP_MEM0_RETSTATE_MASK OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK
- + #define OMAP_MEM1_RETSTATE_MASK OMAP3430_L1FLATMEMRETSTATE_MASK
- + #define OMAP_MEM2_RETSTATE_MASK OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK
- + #define OMAP_MEM3_RETSTATE_MASK OMAP3430_L2FLATMEMRETSTATE_MASK
- + #define OMAP_MEM4_RETSTATE_MASK OMAP4430_OCP_NRET_BANK_RETSTATE_MASK
- + 
- + /* OMAP3 and OMAP4 Memory Status bits */
- + #define OMAP_MEM0_STATEST_MASK OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK
- + #define OMAP_MEM1_STATEST_MASK OMAP3430_L1FLATMEMSTATEST_MASK
- + #define OMAP_MEM2_STATEST_MASK OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK
- + #define OMAP_MEM3_STATEST_MASK OMAP3430_L2FLATMEMSTATEST_MASK
- + #define OMAP_MEM4_STATEST_MASK OMAP4430_OCP_NRET_BANK_STATEST_MASK
- + 
- + /* Common Internal functions used across OMAP rev's*/
- + u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank)
- + {
- + 	switch (bank) {
- + 	case 0:
- + 		return OMAP_MEM0_ONSTATE_MASK;
- + 	case 1:
- + 		return OMAP_MEM1_ONSTATE_MASK;
- + 	case 2:
- + 		return OMAP_MEM2_ONSTATE_MASK;
- + 	case 3:
- + 		return OMAP_MEM3_ONSTATE_MASK;
- + 	case 4:
- + 		return OMAP_MEM4_ONSTATE_MASK;
- + 	default:
- + 		WARN_ON(1); /* should never happen */
- + 		return -EEXIST;
- + 	}
- + 	return 0;
- + }
- + 
- + u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank)
- + {
- + 	switch (bank) {
- + 	case 0:
- + 		return OMAP_MEM0_RETSTATE_MASK;
- + 	case 1:
- + 		return OMAP_MEM1_RETSTATE_MASK;
- + 	case 2:
- + 		return OMAP_MEM2_RETSTATE_MASK;
- + 	case 3:
- + 		return OMAP_MEM3_RETSTATE_MASK;
- + 	case 4:
- + 		return OMAP_MEM4_RETSTATE_MASK;
- + 	default:
- + 		WARN_ON(1); /* should never happen */
- + 		return -EEXIST;
- + 	}
- + 	return 0;
- + }
- + 
- + u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank)
- + {
- + 	switch (bank) {
- + 	case 0:
- + 		return OMAP_MEM0_STATEST_MASK;
- + 	case 1:
- + 		return OMAP_MEM1_STATEST_MASK;
- + 	case 2:
- + 		return OMAP_MEM2_STATEST_MASK;
- + 	case 3:
- + 		return OMAP_MEM3_STATEST_MASK;
- + 	case 4:
- + 		return OMAP_MEM4_STATEST_MASK;
- + 	default:
- + 		WARN_ON(1); /* should never happen */
- + 		return -EEXIST;
- + 	}
- + 	return 0;
- + }
- + 
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/powerdomain.h linux-3.2.1/arch/arm/mach-ckb_3352/powerdomain.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/powerdomain.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/powerdomain.h	2014-05-15 13:25:13.970604039 +0900
- ***************
- *** 0 ****
- --- 1,242 ----
- + /*
- +  * OMAP2/3/4 powerdomain control
- +  *
- +  * Copyright (C) 2007-2008, 2010 Texas Instruments, Inc.
- +  * Copyright (C) 2007-2011 Nokia Corporation
- +  *
- +  * Paul Walmsley
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  *
- +  * XXX This should be moved to the mach-omap2/ directory at the earliest
- +  * opportunity.
- +  */
- + 
- + #ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H
- + #define __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H
- + 
- + #include <linux/types.h>
- + #include <linux/list.h>
- + 
- + #include <linux/atomic.h>
- + 
- + #include <plat/cpu.h>
- + 
- + #include "voltage.h"
- + 
- + /* Powerdomain basic power states */
- + #define PWRDM_POWER_OFF		0x0
- + #define PWRDM_POWER_RET		0x1
- + #define PWRDM_POWER_INACTIVE	0x2
- + #define PWRDM_POWER_ON		0x3
- + 
- + #define PWRDM_MAX_PWRSTS	4
- + 
- + /* Powerdomain allowable state bitfields */
- + #define PWRSTS_ON		(1 << PWRDM_POWER_ON)
- + #define PWRSTS_INACTIVE		(1 << PWRDM_POWER_INACTIVE)
- + #define PWRSTS_RET		(1 << PWRDM_POWER_RET)
- + #define PWRSTS_OFF		(1 << PWRDM_POWER_OFF)
- + 
- + #define PWRSTS_OFF_ON		(PWRSTS_OFF | PWRSTS_ON)
- + #define PWRSTS_OFF_RET		(PWRSTS_OFF | PWRSTS_RET)
- + #define PWRSTS_RET_ON		(PWRSTS_RET | PWRSTS_ON)
- + #define PWRSTS_OFF_RET_ON	(PWRSTS_OFF_RET | PWRSTS_ON)
- + 
- + 
- + /* Powerdomain flags */
- + #define PWRDM_HAS_HDWR_SAR	(1 << 0) /* hardware save-and-restore support */
- + #define PWRDM_HAS_MPU_QUIRK	(1 << 1) /* MPU pwr domain has MEM bank 0 bits
- + 					  * in MEM bank 1 position. This is
- + 					  * true for OMAP3430
- + 					  */
- + #define PWRDM_HAS_LOWPOWERSTATECHANGE	(1 << 2) /*
- + 						  * support to transition from a
- + 						  * sleep state to a lower sleep
- + 						  * state without waking up the
- + 						  * powerdomain
- + 						  */
- + 
- + /*
- +  * Number of memory banks that are power-controllable.	On OMAP4430, the
- +  * maximum is 5.
- +  */
- + #define PWRDM_MAX_MEM_BANKS	5
- + 
- + /*
- +  * Maximum number of clockdomains that can be associated with a powerdomain.
- +  * CORE powerdomain on AM33XX is the worst case
- +  */
- + #define PWRDM_MAX_CLKDMS	11
- + 
- + /* XXX A completely arbitrary number. What is reasonable here? */
- + #define PWRDM_TRANSITION_BAILOUT 100000
- + 
- + struct clockdomain;
- + struct powerdomain;
- + 
- + /**
- +  * struct powerdomain - OMAP powerdomain
- +  * @name: Powerdomain name
- +  * @voltdm: voltagedomain containing this powerdomain
- +  * @prcm_offs: the address offset from CM_BASE/PRM_BASE
- +  * @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs
- +  * @pwrsts: Possible powerdomain power states
- +  * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION
- +  * @flags: Powerdomain flags
- +  * @banks: Number of software-controllable memory banks in this powerdomain
- +  * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION
- +  * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON
- +  * @pwrdm_clkdms: Clockdomains in this powerdomain
- +  * @node: list_head linking all powerdomains
- +  * @voltdm_node: list_head linking all powerdomains in a voltagedomain
- +  * @pwrstctrl_offs: XXX_PWRSTCTRL reg offset from prcm_offs
- +  * @pwrstst_offs: XXX_PWRSTST reg offset from prcm_offs
- +  * @state:
- +  * @state_counter:
- +  * @timer:
- +  * @state_timer:
- +  *
- +  * @prcm_partition possible values are defined in mach-omap2/prcm44xx.h.
- +  */
- + struct powerdomain {
- + 	const char *name;
- + 	union {
- + 		const char *name;
- + 		struct voltagedomain *ptr;
- + 	} voltdm;
- + 	const s16 prcm_offs;
- + 	const u8 pwrsts;
- + 	const u8 pwrsts_logic_ret;
- + 	const u8 flags;
- + 	const u8 banks;
- + 	const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
- + 	const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
- + 	const u8 prcm_partition;
- + 	struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
- + 	struct list_head node;
- + 	struct list_head voltdm_node;
- + 	int state;
- + 	unsigned state_counter[PWRDM_MAX_PWRSTS];
- + 	unsigned ret_logic_off_counter;
- + 	unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];
- + 
- + 	u8 pwrstctrl_offs;
- + 	u8 pwrstst_offs;
- + #ifdef CONFIG_PM_DEBUG
- + 	s64 timer;
- + 	s64 state_timer[PWRDM_MAX_PWRSTS];
- + #endif
- + };
- + 
- + /**
- +  * struct pwrdm_ops - Arch specific function implementations
- +  * @pwrdm_set_next_pwrst: Set the target power state for a pd
- +  * @pwrdm_read_next_pwrst: Read the target power state set for a pd
- +  * @pwrdm_read_pwrst: Read the current power state of a pd
- +  * @pwrdm_read_prev_pwrst: Read the prev power state entered by the pd
- +  * @pwrdm_set_logic_retst: Set the logic state in RET for a pd
- +  * @pwrdm_set_mem_onst: Set the Memory state in ON for a pd
- +  * @pwrdm_set_mem_retst: Set the Memory state in RET for a pd
- +  * @pwrdm_read_logic_pwrst: Read the current logic state of a pd
- +  * @pwrdm_read_prev_logic_pwrst: Read the previous logic state entered by a pd
- +  * @pwrdm_read_logic_retst: Read the logic state in RET for a pd
- +  * @pwrdm_read_mem_pwrst: Read the current memory state of a pd
- +  * @pwrdm_read_prev_mem_pwrst: Read the previous memory state entered by a pd
- +  * @pwrdm_read_mem_retst: Read the memory state in RET for a pd
- +  * @pwrdm_clear_all_prev_pwrst: Clear all previous power states logged for a pd
- +  * @pwrdm_enable_hdwr_sar: Enable Hardware Save-Restore feature for the pd
- +  * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd
- +  * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep
- +  * @pwrdm_wait_transition: Wait for a pd state transition to complete
- +  */
- + struct pwrdm_ops {
- + 	int	(*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst);
- + 	int	(*pwrdm_read_next_pwrst)(struct powerdomain *pwrdm);
- + 	int	(*pwrdm_read_pwrst)(struct powerdomain *pwrdm);
- + 	int	(*pwrdm_read_prev_pwrst)(struct powerdomain *pwrdm);
- + 	int	(*pwrdm_set_logic_retst)(struct powerdomain *pwrdm, u8 pwrst);
- + 	int	(*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
- + 	int	(*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
- + 	int	(*pwrdm_read_logic_pwrst)(struct powerdomain *pwrdm);
- + 	int	(*pwrdm_read_prev_logic_pwrst)(struct powerdomain *pwrdm);
- + 	int	(*pwrdm_read_logic_retst)(struct powerdomain *pwrdm);
- + 	int	(*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
- + 	int	(*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
- + 	int	(*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank);
- + 	int	(*pwrdm_clear_all_prev_pwrst)(struct powerdomain *pwrdm);
- + 	int	(*pwrdm_enable_hdwr_sar)(struct powerdomain *pwrdm);
- + 	int	(*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm);
- + 	int	(*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm);
- + 	int	(*pwrdm_wait_transition)(struct powerdomain *pwrdm);
- + };
- + 
- + int pwrdm_register_platform_funcs(struct pwrdm_ops *custom_funcs);
- + int pwrdm_register_pwrdms(struct powerdomain **pwrdm_list);
- + int pwrdm_complete_init(void);
- + 
- + struct powerdomain *pwrdm_lookup(const char *name);
- + 
- + int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
- + 			void *user);
- + int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
- + 			void *user);
- + 
- + int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
- + int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
- + int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
- + 			 int (*fn)(struct powerdomain *pwrdm,
- + 				   struct clockdomain *clkdm));
- + struct voltagedomain *pwrdm_get_voltdm(struct powerdomain *pwrdm);
- + 
- + int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
- + 
- + int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
- + int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
- + int pwrdm_read_pwrst(struct powerdomain *pwrdm);
- + int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
- + int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
- + 
- + int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
- + int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
- + int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
- + 
- + int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
- + int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
- + int pwrdm_read_logic_retst(struct powerdomain *pwrdm);
- + int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
- + int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
- + int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
- + 
- + int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
- + int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
- + bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
- + 
- + int pwrdm_wait_transition(struct powerdomain *pwrdm);
- + 
- + int pwrdm_state_switch(struct powerdomain *pwrdm);
- + int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
- + int pwrdm_pre_transition(void);
- + int pwrdm_post_transition(void);
- + int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
- + int pwrdm_get_context_loss_count(struct powerdomain *pwrdm);
- + bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
- + 
- + extern void am33xx_powerdomains_init(void);
- + 
- + 
- + extern struct pwrdm_ops omap3_pwrdm_operations;
- + extern struct pwrdm_ops omap4_pwrdm_operations;
- + 
- + /* Common Internal functions used across OMAP rev's */
- + extern u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank);
- + extern u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank);
- + extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank);
- + 
- + extern struct powerdomain wkup_omap2_pwrdm;
- + extern struct powerdomain gfx_omap2_pwrdm;
- + 
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/powerdomains2xxx_3xxx_data.c linux-3.2.1/arch/arm/mach-ckb_3352/powerdomains2xxx_3xxx_data.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/powerdomains2xxx_3xxx_data.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/powerdomains2xxx_3xxx_data.c	2014-05-15 13:25:13.975211631 +0900
- ***************
- *** 0 ****
- --- 1,65 ----
- + /*
- +  * OMAP2/3 common powerdomain definitions
- +  *
- +  * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
- +  * Copyright (C) 2007-2011 Nokia Corporation
- +  *
- +  * Paul Walmsley, Jouni Högander
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + /*
- +  * The names for the DSP/IVA2 powerdomains are confusing.
- +  *
- +  * Most OMAP chips have an on-board DSP.
- +  *
- +  * On the 2420, this is a 'C55 DSP called, simply, the DSP.  Its
- +  * powerdomain is called the "DSP power domain."  On the 2430, the
- +  * on-board DSP is a 'C64 DSP, now called (along with its hardware
- +  * accelerators) the IVA2 or IVA2.1.  Its powerdomain is still called
- +  * the "DSP power domain." On the 3430, the DSP is a 'C64 DSP like the
- +  * 2430, also known as the IVA2; but its powerdomain is now called the
- +  * "IVA2 power domain."
- +  *
- +  * The 2420 also has something called the IVA, which is a separate ARM
- +  * core, and has nothing to do with the DSP/IVA2.
- +  *
- +  * Ideally the DSP/IVA2 could just be the same powerdomain, but the PRCM
- +  * address offset is different between the C55 and C64 DSPs.
- +  */
- + 
- + #include "powerdomain.h"
- + 
- + #include "prcm-common.h"
- + #include "prm.h"
- + 
- + /* OMAP2/3-common powerdomains */
- + 
- + /*
- +  * The GFX powerdomain is not present on 3430ES2, but currently we do not
- +  * have a macro to filter it out at compile-time.
- +  */
- + struct powerdomain gfx_omap2_pwrdm = {
- + 	.name		  = "gfx_pwrdm",
- + 	.prcm_offs	  = GFX_MOD,
- + 	.pwrsts		  = PWRSTS_OFF_RET_ON,
- + 	.pwrsts_logic_ret = PWRSTS_RET,
- + 	.banks		  = 1,
- + 	.pwrsts_mem_ret	  = {
- + 		[0] = PWRSTS_RET, /* MEMRETSTATE */
- + 	},
- + 	.pwrsts_mem_on	  = {
- + 		[0] = PWRSTS_ON,  /* MEMONSTATE */
- + 	},
- + 	.voltdm           = { .name = "core" },
- + };
- + 
- + struct powerdomain wkup_omap2_pwrdm = {
- + 	.name		= "wkup_pwrdm",
- + 	.prcm_offs	= WKUP_MOD,
- + 	.pwrsts		= PWRSTS_ON,
- + 	.voltdm         = { .name = "wakeup" },
- + };
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/powerdomains2xxx_3xxx_data.h linux-3.2.1/arch/arm/mach-ckb_3352/powerdomains2xxx_3xxx_data.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/powerdomains2xxx_3xxx_data.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/powerdomains2xxx_3xxx_data.h	2014-05-15 13:25:13.975211631 +0900
- ***************
- *** 0 ****
- --- 1,22 ----
- + /*
- +  * OMAP2/3 common powerdomains - prototypes
- +  *
- +  * Copyright (C) 2008 Texas Instruments, Inc.
- +  * Copyright (C) 2008-2010 Nokia Corporation
- +  *
- +  * Paul Walmsley
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAINS2XXX_3XXX_DATA_H
- + #define __ARCH_ARM_MACH_OMAP2_POWERDOMAINS2XXX_3XXX_DATA_H
- + 
- + #include "powerdomain.h"
- + 
- + extern struct powerdomain gfx_omap2_pwrdm;
- + extern struct powerdomain wkup_omap2_pwrdm;
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/powerdomains33xx_data.c linux-3.2.1/arch/arm/mach-ckb_3352/powerdomains33xx_data.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/powerdomains33xx_data.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/powerdomains33xx_data.c	2014-05-15 13:25:13.975211631 +0900
- ***************
- *** 0 ****
- --- 1,134 ----
- + /*
- +  * AM33XX Power domains framework
- +  *
- +  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #include <linux/kernel.h>
- + #include <linux/init.h>
- + 
- + #include "powerdomain.h"
- + #include "prcm-common.h"
- + #include "prm33xx.h"
- + #include "prcm44xx.h"
- + 
- + static struct powerdomain gfx_33xx_pwrdm = {
- + 	.name			= "gfx_pwrdm",
- + 	.voltdm			= { .name = "core" },
- + 	.prcm_partition		= AM33XX_PRM_PARTITION,
- + 	.prcm_offs		= AM33XX_PRM_GFX_MOD,
- + 	.pwrsts			= PWRSTS_OFF_ON,
- + 	.pwrsts_logic_ret	= PWRSTS_OFF_RET,
- + 	.pwrstctrl_offs		= AM33XX_PM_GFX_PWRSTCTRL_OFFSET,
- + 	.pwrstst_offs		= AM33XX_PM_GFX_PWRSTST_OFFSET,
- + 	.flags			= PWRDM_HAS_LOWPOWERSTATECHANGE,
- + 	.banks			= 1,
- + 	.pwrsts_mem_ret		= {
- + 		[0]	= PWRSTS_OFF_RET,	/* gfx_mem */
- + 	},
- + 	.pwrsts_mem_on		= {
- + 		[0]	= PWRSTS_ON,		/* gfx_mem */
- + 	},
- + };
- + 
- + static struct powerdomain rtc_33xx_pwrdm = {
- + 	.name			= "rtc_pwrdm",
- + 	.voltdm			= { .name = "rtc" },
- + 	.prcm_partition		= AM33XX_PRM_PARTITION,
- + 	.prcm_offs		= AM33XX_PRM_RTC_MOD,
- + 	.pwrsts			= PWRSTS_ON,
- + 	.pwrstctrl_offs		= AM33XX_PM_RTC_PWRSTCTRL_OFFSET,
- + 	.pwrstst_offs		= AM33XX_PM_RTC_PWRSTST_OFFSET,
- + };
- + 
- + static struct powerdomain wkup_33xx_pwrdm = {
- + 	.name			= "wkup_pwrdm",
- + 	.voltdm			= { .name = "core" },
- + 	.prcm_partition		= AM33XX_PRM_PARTITION,
- + 	.prcm_offs		= AM33XX_PRM_WKUP_MOD,
- + 	.pwrsts			= PWRSTS_ON,
- + 	.pwrstctrl_offs		= AM33XX_PM_WKUP_PWRSTCTRL_OFFSET,
- + 	.pwrstst_offs		= AM33XX_PM_WKUP_PWRSTST_OFFSET,
- + };
- + 
- + static struct powerdomain per_33xx_pwrdm = {
- + 	.name			= "per_pwrdm",
- + 	.voltdm			= { .name = "core" },
- + 	.prcm_partition		= AM33XX_PRM_PARTITION,
- + 	.prcm_offs		= AM33XX_PRM_PER_MOD,
- + 	.pwrsts			= PWRSTS_OFF_RET_ON,
- + 	.pwrsts_logic_ret	= PWRSTS_OFF_RET,
- + 	.pwrstctrl_offs		= AM33XX_PM_PER_PWRSTCTRL_OFFSET,
- + 	.pwrstst_offs		= AM33XX_PM_PER_PWRSTST_OFFSET,
- + 	.flags			= PWRDM_HAS_LOWPOWERSTATECHANGE,
- + 	.banks			= 3,
- + 	.pwrsts_mem_ret		= {
- + 		[0]	= PWRSTS_OFF_RET,	/* pruss_mem */
- + 		[1]	= PWRSTS_OFF_RET,	/* per_mem */
- + 		[2]	= PWRSTS_OFF_RET,	/* ram_mem */
- + 	},
- + 	.pwrsts_mem_on		= {
- + 		[0]	= PWRSTS_ON,		/* pruss_mem */
- + 		[1]	= PWRSTS_ON,		/* per_mem */
- + 		[2]	= PWRSTS_ON,		/* ram_mem */
- + 	},
- + };
- + 
- + static struct powerdomain mpu_33xx_pwrdm = {
- + 	.name			= "mpu_pwrdm",
- + 	.voltdm			= { .name = "mpu" },
- + 	.prcm_partition		= AM33XX_PRM_PARTITION,
- + 	.prcm_offs		= AM33XX_PRM_MPU_MOD,
- + 	.pwrsts			= PWRSTS_OFF_RET_ON,
- + 	.pwrsts_logic_ret	= PWRSTS_OFF_RET,
- + 	.pwrstctrl_offs		= AM33XX_PM_MPU_PWRSTCTRL_OFFSET,
- + 	.pwrstst_offs		= AM33XX_PM_MPU_PWRSTST_OFFSET,
- + 	.flags			= PWRDM_HAS_LOWPOWERSTATECHANGE,
- + 	.banks			= 3,
- + 	.pwrsts_mem_ret		= {
- + 		[0]	= PWRSTS_OFF_RET,	/* mpu_l1 */
- + 		[1]	= PWRSTS_OFF_RET,	/* mpu_l2 */
- + 		[2]	= PWRSTS_OFF_RET,	/* mpu_ram */
- + 	},
- + 	.pwrsts_mem_on		= {
- + 		[0]	= PWRSTS_ON,		/* mpu_l1 */
- + 		[1]	= PWRSTS_ON,		/* mpu_l2 */
- + 		[2]	= PWRSTS_ON,		/* mpu_ram */
- + 	},
- + };
- + 
- + static struct powerdomain cefuse_33xx_pwrdm = {
- + 	.name			= "cefuse_pwrdm",
- + 	.voltdm			= { .name = "core" },
- + 	.prcm_partition		= AM33XX_PRM_PARTITION,
- + 	.prcm_offs		= AM33XX_PRM_CEFUSE_MOD,
- + 	.pwrsts			= PWRSTS_OFF_ON,
- + 	.pwrstctrl_offs		= AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET,
- + 	.pwrstst_offs		= AM33XX_PM_CEFUSE_PWRSTST_OFFSET,
- + };
- + 
- + static struct powerdomain *powerdomains_am33xx[] __initdata = {
- + 	&gfx_33xx_pwrdm,
- + 	&rtc_33xx_pwrdm,
- + 	&wkup_33xx_pwrdm,
- + 	&per_33xx_pwrdm,
- + 	&mpu_33xx_pwrdm,
- + 	&cefuse_33xx_pwrdm,
- + 	NULL,
- + };
- + 
- + void __init am33xx_powerdomains_init(void)
- + {
- + 	pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
- + 	pwrdm_register_pwrdms(powerdomains_am33xx);
- + 	pwrdm_complete_init();
- + }
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/powerdomains3xxx_data.c linux-3.2.1/arch/arm/mach-ckb_3352/powerdomains3xxx_data.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/powerdomains3xxx_data.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/powerdomains3xxx_data.c	2014-05-15 13:25:13.975211631 +0900
- ***************
- *** 0 ****
- --- 1,293 ----
- + /*
- +  * OMAP3 powerdomain definitions
- +  *
- +  * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
- +  * Copyright (C) 2007-2011 Nokia Corporation
- +  *
- +  * Paul Walmsley, Jouni Högander
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #include <linux/kernel.h>
- + #include <linux/init.h>
- + 
- + #include <plat/cpu.h>
- + 
- + #include "powerdomain.h"
- + #include "powerdomains2xxx_3xxx_data.h"
- + 
- + #include "prcm-common.h"
- + #include "prm2xxx_3xxx.h"
- + #include "prm-regbits-34xx.h"
- + #include "cm2xxx_3xxx.h"
- + #include "cm-regbits-34xx.h"
- + 
- + /*
- +  * 34XX-specific powerdomains, dependencies
- +  */
- + 
- + /*
- +  * Powerdomains
- +  */
- + 
- + static struct powerdomain iva2_pwrdm = {
- + 	.name		  = "iva2_pwrdm",
- + 	.prcm_offs	  = OMAP3430_IVA2_MOD,
- + 	.pwrsts		  = PWRSTS_OFF_RET_ON,
- + 	.pwrsts_logic_ret = PWRSTS_OFF_RET,
- + 	.banks		  = 4,
- + 	.pwrsts_mem_ret	  = {
- + 		[0] = PWRSTS_OFF_RET,
- + 		[1] = PWRSTS_OFF_RET,
- + 		[2] = PWRSTS_OFF_RET,
- + 		[3] = PWRSTS_OFF_RET,
- + 	},
- + 	.pwrsts_mem_on	  = {
- + 		[0] = PWRSTS_ON,
- + 		[1] = PWRSTS_ON,
- + 		[2] = PWRSTS_OFF_ON,
- + 		[3] = PWRSTS_ON,
- + 	},
- + 	.voltdm           = { .name = "mpu_iva" },
- + };
- + 
- + static struct powerdomain mpu_3xxx_pwrdm = {
- + 	.name		  = "mpu_pwrdm",
- + 	.prcm_offs	  = MPU_MOD,
- + 	.pwrsts		  = PWRSTS_OFF_RET_ON,
- + 	.pwrsts_logic_ret = PWRSTS_OFF_RET,
- + 	.flags		  = PWRDM_HAS_MPU_QUIRK,
- + 	.banks		  = 1,
- + 	.pwrsts_mem_ret	  = {
- + 		[0] = PWRSTS_OFF_RET,
- + 	},
- + 	.pwrsts_mem_on	  = {
- + 		[0] = PWRSTS_OFF_ON,
- + 	},
- + 	.voltdm           = { .name = "mpu_iva" },
- + };
- + 
- + /*
- +  * The USBTLL Save-and-Restore mechanism is broken on
- +  * 3430s up to ES3.0 and 3630ES1.0. Hence this feature
- +  * needs to be disabled on these chips.
- +  * Refer: 3430 errata ID i459 and 3630 errata ID i579
- +  *
- +  * Note: setting the SAR flag could help for errata ID i478
- +  *  which applies to 3430 <= ES3.1, but since the SAR feature
- +  *  is broken, do not use it.
- +  */
- + static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
- + 	.name		  = "core_pwrdm",
- + 	.prcm_offs	  = CORE_MOD,
- + 	.pwrsts		  = PWRSTS_OFF_RET_ON,
- + 	.pwrsts_logic_ret = PWRSTS_OFF_RET,
- + 	.banks		  = 2,
- + 	.pwrsts_mem_ret	  = {
- + 		[0] = PWRSTS_OFF_RET,	 /* MEM1RETSTATE */
- + 		[1] = PWRSTS_OFF_RET,	 /* MEM2RETSTATE */
- + 	},
- + 	.pwrsts_mem_on	  = {
- + 		[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
- + 		[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
- + 	},
- + 	.voltdm           = { .name = "core" },
- + };
- + 
- + static struct powerdomain core_3xxx_es3_1_pwrdm = {
- + 	.name		  = "core_pwrdm",
- + 	.prcm_offs	  = CORE_MOD,
- + 	.pwrsts		  = PWRSTS_OFF_RET_ON,
- + 	.pwrsts_logic_ret = PWRSTS_OFF_RET,
- + 	/*
- + 	 * Setting the SAR flag for errata ID i478 which applies
- + 	 *  to 3430 <= ES3.1
- + 	 */
- + 	.flags		  = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
- + 	.banks		  = 2,
- + 	.pwrsts_mem_ret	  = {
- + 		[0] = PWRSTS_OFF_RET,	 /* MEM1RETSTATE */
- + 		[1] = PWRSTS_OFF_RET,	 /* MEM2RETSTATE */
- + 	},
- + 	.pwrsts_mem_on	  = {
- + 		[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
- + 		[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
- + 	},
- + 	.voltdm           = { .name = "core" },
- + };
- + 
- + static struct powerdomain dss_pwrdm = {
- + 	.name		  = "dss_pwrdm",
- + 	.prcm_offs	  = OMAP3430_DSS_MOD,
- + 	.pwrsts		  = PWRSTS_OFF_RET_ON,
- + 	.pwrsts_logic_ret = PWRSTS_RET,
- + 	.banks		  = 1,
- + 	.pwrsts_mem_ret	  = {
- + 		[0] = PWRSTS_RET, /* MEMRETSTATE */
- + 	},
- + 	.pwrsts_mem_on	  = {
- + 		[0] = PWRSTS_ON,  /* MEMONSTATE */
- + 	},
- + 	.voltdm           = { .name = "core" },
- + };
- + 
- + /*
- +  * Although the 34XX TRM Rev K Table 4-371 notes that retention is a
- +  * possible SGX powerstate, the SGX device itself does not support
- +  * retention.
- +  */
- + static struct powerdomain sgx_pwrdm = {
- + 	.name		  = "sgx_pwrdm",
- + 	.prcm_offs	  = OMAP3430ES2_SGX_MOD,
- + 	/* XXX This is accurate for 3430 SGX, but what about GFX? */
- + 	.pwrsts		  = PWRSTS_OFF_ON,
- + 	.pwrsts_logic_ret = PWRSTS_RET,
- + 	.banks		  = 1,
- + 	.pwrsts_mem_ret	  = {
- + 		[0] = PWRSTS_RET, /* MEMRETSTATE */
- + 	},
- + 	.pwrsts_mem_on	  = {
- + 		[0] = PWRSTS_ON,  /* MEMONSTATE */
- + 	},
- + 	.voltdm           = { .name = "core" },
- + };
- + 
- + static struct powerdomain cam_pwrdm = {
- + 	.name		  = "cam_pwrdm",
- + 	.prcm_offs	  = OMAP3430_CAM_MOD,
- + 	.pwrsts		  = PWRSTS_OFF_RET_ON,
- + 	.pwrsts_logic_ret = PWRSTS_RET,
- + 	.banks		  = 1,
- + 	.pwrsts_mem_ret	  = {
- + 		[0] = PWRSTS_RET, /* MEMRETSTATE */
- + 	},
- + 	.pwrsts_mem_on	  = {
- + 		[0] = PWRSTS_ON,  /* MEMONSTATE */
- + 	},
- + 	.voltdm           = { .name = "core" },
- + };
- + 
- + static struct powerdomain per_pwrdm = {
- + 	.name		  = "per_pwrdm",
- + 	.prcm_offs	  = OMAP3430_PER_MOD,
- + 	.pwrsts		  = PWRSTS_OFF_RET_ON,
- + 	.pwrsts_logic_ret = PWRSTS_OFF_RET,
- + 	.banks		  = 1,
- + 	.pwrsts_mem_ret	  = {
- + 		[0] = PWRSTS_RET, /* MEMRETSTATE */
- + 	},
- + 	.pwrsts_mem_on	  = {
- + 		[0] = PWRSTS_ON,  /* MEMONSTATE */
- + 	},
- + 	.voltdm           = { .name = "core" },
- + };
- + 
- + static struct powerdomain emu_pwrdm = {
- + 	.name		= "emu_pwrdm",
- + 	.prcm_offs	= OMAP3430_EMU_MOD,
- + 	.voltdm           = { .name = "core" },
- + };
- + 
- + static struct powerdomain neon_pwrdm = {
- + 	.name		  = "neon_pwrdm",
- + 	.prcm_offs	  = OMAP3430_NEON_MOD,
- + 	.pwrsts		  = PWRSTS_OFF_RET_ON,
- + 	.pwrsts_logic_ret = PWRSTS_RET,
- + 	.voltdm           = { .name = "mpu_iva" },
- + };
- + 
- + static struct powerdomain usbhost_pwrdm = {
- + 	.name		  = "usbhost_pwrdm",
- + 	.prcm_offs	  = OMAP3430ES2_USBHOST_MOD,
- + 	.pwrsts		  = PWRSTS_OFF_RET_ON,
- + 	.pwrsts_logic_ret = PWRSTS_RET,
- + 	/*
- + 	 * REVISIT: Enabling usb host save and restore mechanism seems to
- + 	 * leave the usb host domain permanently in ACTIVE mode after
- + 	 * changing the usb host power domain state from OFF to active once.
- + 	 * Disabling for now.
- + 	 */
- + 	/*.flags	  = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */
- + 	.banks		  = 1,
- + 	.pwrsts_mem_ret	  = {
- + 		[0] = PWRSTS_RET, /* MEMRETSTATE */
- + 	},
- + 	.pwrsts_mem_on	  = {
- + 		[0] = PWRSTS_ON,  /* MEMONSTATE */
- + 	},
- + 	.voltdm           = { .name = "core" },
- + };
- + 
- + static struct powerdomain dpll1_pwrdm = {
- + 	.name		= "dpll1_pwrdm",
- + 	.prcm_offs	= MPU_MOD,
- + 	.voltdm           = { .name = "mpu_iva" },
- + };
- + 
- + static struct powerdomain dpll2_pwrdm = {
- + 	.name		= "dpll2_pwrdm",
- + 	.prcm_offs	= OMAP3430_IVA2_MOD,
- + 	.voltdm           = { .name = "mpu_iva" },
- + };
- + 
- + static struct powerdomain dpll3_pwrdm = {
- + 	.name		= "dpll3_pwrdm",
- + 	.prcm_offs	= PLL_MOD,
- + 	.voltdm           = { .name = "core" },
- + };
- + 
- + static struct powerdomain dpll4_pwrdm = {
- + 	.name		= "dpll4_pwrdm",
- + 	.prcm_offs	= PLL_MOD,
- + 	.voltdm           = { .name = "core" },
- + };
- + 
- + static struct powerdomain dpll5_pwrdm = {
- + 	.name		= "dpll5_pwrdm",
- + 	.prcm_offs	= PLL_MOD,
- + 	.voltdm           = { .name = "core" },
- + };
- + 
- + /* As powerdomains are added or removed above, this list must also be changed */
- + static struct powerdomain *powerdomains_omap3430_common[] __initdata = {
- + 	&wkup_omap2_pwrdm,
- + 	&iva2_pwrdm,
- + 	&mpu_3xxx_pwrdm,
- + 	&neon_pwrdm,
- + 	&cam_pwrdm,
- + 	&dss_pwrdm,
- + 	&per_pwrdm,
- + 	&emu_pwrdm,
- + 	&dpll1_pwrdm,
- + 	&dpll2_pwrdm,
- + 	&dpll3_pwrdm,
- + 	&dpll4_pwrdm,
- + 	NULL
- + };
- + 
- + static struct powerdomain *powerdomains_omap3430es1[] __initdata = {
- + 	&gfx_omap2_pwrdm,
- + 	&core_3xxx_pre_es3_1_pwrdm,
- + 	NULL
- + };
- + 
- + /* also includes 3630ES1.0 */
- + static struct powerdomain *powerdomains_omap3430es2_es3_0[] __initdata = {
- + 	&core_3xxx_pre_es3_1_pwrdm,
- + 	&sgx_pwrdm,
- + 	&usbhost_pwrdm,
- + 	&dpll5_pwrdm,
- + 	NULL
- + };
- + 
- + /* also includes 3630ES1.1+ */
- + static struct powerdomain *powerdomains_omap3430es3_1plus[] __initdata = {
- + 	&core_3xxx_es3_1_pwrdm,
- + 	&sgx_pwrdm,
- + 	&usbhost_pwrdm,
- + 	&dpll5_pwrdm,
- + 	NULL
- + };
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/prcm44xx.h linux-3.2.1/arch/arm/mach-ckb_3352/prcm44xx.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/prcm44xx.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/prcm44xx.h	2014-05-15 13:25:13.975211631 +0900
- ***************
- *** 0 ****
- --- 1,44 ----
- + /*
- +  * OMAP4 PRCM definitions
- +  *
- +  * Copyright (C) 2010 Texas Instruments, Inc.
- +  * Copyright (C) 2010 Nokia Corporation
- +  *
- +  * Paul Walmsley
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  *
- +  * This file contains macros and functions that are common to all of
- +  * the PRM/CM/PRCM blocks on the OMAP4 devices: PRM, CM1, CM2,
- +  * PRCM_MPU, SCRM
- +  */
- + 
- + #ifndef __ARCH_ARM_MACH_OMAP2_PRCM44XX_H
- + #define __ARCH_ARM_MACH_OMAP2_PRCM44XX_H
- + 
- + /*
- +  * OMAP4 PRCM partition IDs
- +  *
- +  * The numbers and order are arbitrary, but 0 is reserved for the
- +  * 'invalid' partition in case someone forgets to add a
- +  * .prcm_partition field.
- +  */
- + #define OMAP4430_INVALID_PRCM_PARTITION		0
- + #define OMAP4430_PRM_PARTITION			1
- + #define OMAP4430_CM1_PARTITION			2
- + #define OMAP4430_CM2_PARTITION			3
- + #define OMAP4430_SCRM_PARTITION			4
- + #define OMAP4430_PRCM_MPU_PARTITION		5
- + /* AM33XX PRCM is closer to OMAP4, so try to reuse all API's */
- + #define AM33XX_PRM_PARTITION			1
- + 
- + /*
- +  * OMAP4_MAX_PRCM_PARTITIONS: set to the highest value of the PRCM partition
- +  * IDs, plus one
- +  */
- + #define OMAP4_MAX_PRCM_PARTITIONS		6
- + 
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/prcm.c linux-3.2.1/arch/arm/mach-ckb_3352/prcm.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/prcm.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/prcm.c	2014-05-15 13:25:13.975211631 +0900
- ***************
- *** 0 ****
- --- 1,142 ----
- + /*
- +  * linux/arch/arm/mach-omap2/prcm.c
- +  *
- +  * OMAP 24xx Power Reset and Clock Management (PRCM) functions
- +  *
- +  * Copyright (C) 2005 Nokia Corporation
- +  *
- +  * Written by Tony Lindgren <tony.lindgren@nokia.com>
- +  *
- +  * Copyright (C) 2007 Texas Instruments, Inc.
- +  * Rajendra Nayak <rnayak@ti.com>
- +  *
- +  * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
- +  * Upgraded with OMAP4 support by Abhijit Pagare <abhijitpagare@ti.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #include <linux/kernel.h>
- + #include <linux/init.h>
- + #include <linux/clk.h>
- + #include <linux/io.h>
- + #include <linux/delay.h>
- + #include <linux/export.h>
- + 
- + #include <mach/system.h>
- + #include "common.h"
- + #include <plat/prcm.h>
- + #include <plat/irqs.h>
- + 
- + #include "clock.h"
- + //#include "clock2xxx.h"
- + #include "cm2xxx_3xxx.h"
- + #include "prm2xxx_3xxx.h"
- + //#include "prm44xx.h"
- + #include "prm33xx.h"
- + #include "prminst44xx.h"
- + #include "prm-regbits-24xx.h"
- + #include "prm-regbits-44xx.h"
- + #include "control.h"
- + 
- + void __iomem *prm_base;
- + void __iomem *cm_base;
- + void __iomem *cm2_base;
- + 
- + #define MAX_MODULE_ENABLE_WAIT		100000
- + 
- + 
- + /* Resets clock rates and reboots the system. Only called from system.h */
- + static void omap_prcm_arch_reset(char mode, const char *cmd)
- + {
- + 	s16 prcm_offs = 0;
- + 
- + 	prcm_offs = AM33XX_PRM_DEVICE_MOD;
- + 	omap2_prm_set_mod_reg_bits(OMAP4430_RST_GLOBAL_COLD_SW_MASK,
- + 				prcm_offs, AM33XX_PRM_RSTCTRL_OFFSET);
- + 	
- + 	/*
- + 	 * As per Errata i520, in some cases, user will not be able to
- + 	 * access DDR memory after warm-reset.
- + 	 * This situation occurs while the warm-reset happens during a read
- + 	 * access to DDR memory. In that particular condition, DDR memory
- + 	 * does not respond to a corrupted read command due to the warm
- + 	 * reset occurrence but SDRC is waiting for read completion.
- + 	 * SDRC is not sensitive to the warm reset, but the interconnect is
- + 	 * reset on the fly, thus causing a misalignment between SDRC logic,
- + 	 * interconnect logic and DDR memory state.
- + 	 * WORKAROUND:
- + 	 * Steps to perform before a Warm reset is trigged:
- + 	 * 1. enable self-refresh on idle request
- + 	 * 2. put SDRC in idle
- + 	 * 3. wait until SDRC goes to idle
- + 	 * 4. generate SW reset (Global SW reset)
- + 	 *
- + 	 * Steps to be performed after warm reset occurs (in bootloader):
- + 	 * if HW warm reset is the source, apply below steps before any
- + 	 * accesses to SDRAM:
- + 	 * 1. Reset SMS and SDRC and wait till reset is complete
- + 	 * 2. Re-initialize SMS, SDRC and memory
- + 	 *
- + 	 * NOTE: Above work around is required only if arch reset is implemented
- + 	 * using Global SW reset(GLOBAL_SW_RST). DPLL3 reset does not need
- + 	 * the WA since it resets SDRC as well as part of cold reset.
- + 	 */
- + 
- + 	/* XXX should be moved to some OMAP2/3 specific code */
- + 	omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
- + 				   OMAP2_RM_RSTCTRL);
- + 	omap2_prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */
- + }
- + 
- + void (*arch_reset)(char, const char *) = omap_prcm_arch_reset;
- + 
- + /**
- +  * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
- +  * @reg: physical address of module IDLEST register
- +  * @mask: value to mask against to determine if the module is active
- +  * @idlest: idle state indicator (0 or 1) for the clock
- +  * @name: name of the clock (for printk)
- +  *
- +  * Returns 1 if the module indicated readiness in time, or 0 if it
- +  * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
- +  *
- +  * XXX This function is deprecated.  It should be removed once the
- +  * hwmod conversion is complete.
- +  */
- + int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
- + 				const char *name)
- + {
- + 	int i = 0;
- + 	int ena = 0;
- + 
- + 	if (idlest)
- + 		ena = 0;
- + 	else
- + 		ena = mask;
- + 
- + 	/* Wait for lock */
- + 	omap_test_timeout(((__raw_readl(reg) & mask) == ena),
- + 			  MAX_MODULE_ENABLE_WAIT, i);
- + 
- + 	if (i < MAX_MODULE_ENABLE_WAIT)
- + 		pr_debug("cm: Module associated with clock %s ready after %d "
- + 			 "loops\n", name, i);
- + 	else
- + 		pr_err("cm: Module associated with clock %s didn't enable in "
- + 		       "%d tries\n", name, MAX_MODULE_ENABLE_WAIT);
- + 
- + 	return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
- + };
- + 
- + void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
- + {
- + 	if (omap2_globals->prm)
- + 		prm_base = omap2_globals->prm;
- + 	if (omap2_globals->cm)
- + 		cm_base = omap2_globals->cm;
- + 	if (omap2_globals->cm2)
- + 		cm2_base = omap2_globals->cm2;
- + }
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/prcm-common.h linux-3.2.1/arch/arm/mach-ckb_3352/prcm-common.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/prcm-common.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/prcm-common.h	2014-05-15 13:25:13.979558443 +0900
- ***************
- *** 0 ****
- --- 1,489 ----
- + #ifndef __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
- + #define __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
- + 
- + /*
- +  * OMAP2/3 PRCM base and module definitions
- +  *
- +  * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc.
- +  * Copyright (C) 2007-2009 Nokia Corporation
- +  *
- +  * Written by Paul Walmsley
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + /* Module offsets from both CM_BASE & PRM_BASE */
- + 
- + /*
- +  * Offsets that are the same on 24xx and 34xx
- +  *
- +  * Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is
- +  * CCR_MOD on 3430; and GFX_MOD only exists < 3430ES2.
- +  */
- + #define OCP_MOD						0x000
- + #define MPU_MOD						0x100
- + #define CORE_MOD					0x200
- + #define GFX_MOD						0x300
- + #define WKUP_MOD					0x400
- + #define PLL_MOD						0x500
- + 
- + 
- + /* Chip-specific module offsets */
- + #define OMAP24XX_GR_MOD					OCP_MOD
- + #define OMAP24XX_DSP_MOD				0x800
- + 
- + #define OMAP2430_MDM_MOD				0xc00
- + 
- + /* IVA2 module is < base on 3430 */
- + #define OMAP3430_IVA2_MOD				-0x800
- + #define OMAP3430ES2_SGX_MOD				GFX_MOD
- + #define OMAP3430_CCR_MOD				PLL_MOD
- + #define OMAP3430_DSS_MOD				0x600
- + #define OMAP3430_CAM_MOD				0x700
- + #define OMAP3430_PER_MOD				0x800
- + #define OMAP3430_EMU_MOD				0x900
- + #define OMAP3430_GR_MOD					0xa00
- + #define OMAP3430_NEON_MOD				0xb00
- + #define OMAP3430ES2_USBHOST_MOD				0xc00
- + 
- + /* 24XX register bits shared between CM & PRM registers */
- + 
- + /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
- + #define OMAP2420_EN_MMC_SHIFT				26
- + #define OMAP2420_EN_MMC_MASK				(1 << 26)
- + #define OMAP24XX_EN_UART2_SHIFT				22
- + #define OMAP24XX_EN_UART2_MASK				(1 << 22)
- + #define OMAP24XX_EN_UART1_SHIFT				21
- + #define OMAP24XX_EN_UART1_MASK				(1 << 21)
- + #define OMAP24XX_EN_MCSPI2_SHIFT			18
- + #define OMAP24XX_EN_MCSPI2_MASK				(1 << 18)
- + #define OMAP24XX_EN_MCSPI1_SHIFT			17
- + #define OMAP24XX_EN_MCSPI1_MASK				(1 << 17)
- + #define OMAP24XX_EN_MCBSP2_SHIFT			16
- + #define OMAP24XX_EN_MCBSP2_MASK				(1 << 16)
- + #define OMAP24XX_EN_MCBSP1_SHIFT			15
- + #define OMAP24XX_EN_MCBSP1_MASK				(1 << 15)
- + #define OMAP24XX_EN_GPT12_SHIFT				14
- + #define OMAP24XX_EN_GPT12_MASK				(1 << 14)
- + #define OMAP24XX_EN_GPT11_SHIFT				13
- + #define OMAP24XX_EN_GPT11_MASK				(1 << 13)
- + #define OMAP24XX_EN_GPT10_SHIFT				12
- + #define OMAP24XX_EN_GPT10_MASK				(1 << 12)
- + #define OMAP24XX_EN_GPT9_SHIFT				11
- + #define OMAP24XX_EN_GPT9_MASK				(1 << 11)
- + #define OMAP24XX_EN_GPT8_SHIFT				10
- + #define OMAP24XX_EN_GPT8_MASK				(1 << 10)
- + #define OMAP24XX_EN_GPT7_SHIFT				9
- + #define OMAP24XX_EN_GPT7_MASK				(1 << 9)
- + #define OMAP24XX_EN_GPT6_SHIFT				8
- + #define OMAP24XX_EN_GPT6_MASK				(1 << 8)
- + #define OMAP24XX_EN_GPT5_SHIFT				7
- + #define OMAP24XX_EN_GPT5_MASK				(1 << 7)
- + #define OMAP24XX_EN_GPT4_SHIFT				6
- + #define OMAP24XX_EN_GPT4_MASK				(1 << 6)
- + #define OMAP24XX_EN_GPT3_SHIFT				5
- + #define OMAP24XX_EN_GPT3_MASK				(1 << 5)
- + #define OMAP24XX_EN_GPT2_SHIFT				4
- + #define OMAP24XX_EN_GPT2_MASK				(1 << 4)
- + #define OMAP2420_EN_VLYNQ_SHIFT				3
- + #define OMAP2420_EN_VLYNQ_MASK				(1 << 3)
- + 
- + /* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
- + #define OMAP2430_EN_GPIO5_SHIFT				10
- + #define OMAP2430_EN_GPIO5_MASK				(1 << 10)
- + #define OMAP2430_EN_MCSPI3_SHIFT			9
- + #define OMAP2430_EN_MCSPI3_MASK				(1 << 9)
- + #define OMAP2430_EN_MMCHS2_SHIFT			8
- + #define OMAP2430_EN_MMCHS2_MASK				(1 << 8)
- + #define OMAP2430_EN_MMCHS1_SHIFT			7
- + #define OMAP2430_EN_MMCHS1_MASK				(1 << 7)
- + #define OMAP24XX_EN_UART3_SHIFT				2
- + #define OMAP24XX_EN_UART3_MASK				(1 << 2)
- + #define OMAP24XX_EN_USB_SHIFT				0
- + #define OMAP24XX_EN_USB_MASK				(1 << 0)
- + 
- + /* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
- + #define OMAP2430_EN_MDM_INTC_SHIFT			11
- + #define OMAP2430_EN_MDM_INTC_MASK			(1 << 11)
- + #define OMAP2430_EN_USBHS_SHIFT				6
- + #define OMAP2430_EN_USBHS_MASK				(1 << 6)
- + 
- + /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
- + #define OMAP2420_ST_MMC_SHIFT				26
- + #define OMAP2420_ST_MMC_MASK				(1 << 26)
- + #define OMAP24XX_ST_UART2_SHIFT				22
- + #define OMAP24XX_ST_UART2_MASK				(1 << 22)
- + #define OMAP24XX_ST_UART1_SHIFT				21
- + #define OMAP24XX_ST_UART1_MASK				(1 << 21)
- + #define OMAP24XX_ST_MCSPI2_SHIFT			18
- + #define OMAP24XX_ST_MCSPI2_MASK				(1 << 18)
- + #define OMAP24XX_ST_MCSPI1_SHIFT			17
- + #define OMAP24XX_ST_MCSPI1_MASK				(1 << 17)
- + #define OMAP24XX_ST_MCBSP2_SHIFT			16
- + #define OMAP24XX_ST_MCBSP2_MASK				(1 << 16)
- + #define OMAP24XX_ST_MCBSP1_SHIFT			15
- + #define OMAP24XX_ST_MCBSP1_MASK				(1 << 15)
- + #define OMAP24XX_ST_GPT12_SHIFT				14
- + #define OMAP24XX_ST_GPT12_MASK				(1 << 14)
- + #define OMAP24XX_ST_GPT11_SHIFT				13
- + #define OMAP24XX_ST_GPT11_MASK				(1 << 13)
- + #define OMAP24XX_ST_GPT10_SHIFT				12
- + #define OMAP24XX_ST_GPT10_MASK				(1 << 12)
- + #define OMAP24XX_ST_GPT9_SHIFT				11
- + #define OMAP24XX_ST_GPT9_MASK				(1 << 11)
- + #define OMAP24XX_ST_GPT8_SHIFT				10
- + #define OMAP24XX_ST_GPT8_MASK				(1 << 10)
- + #define OMAP24XX_ST_GPT7_SHIFT				9
- + #define OMAP24XX_ST_GPT7_MASK				(1 << 9)
- + #define OMAP24XX_ST_GPT6_SHIFT				8
- + #define OMAP24XX_ST_GPT6_MASK				(1 << 8)
- + #define OMAP24XX_ST_GPT5_SHIFT				7
- + #define OMAP24XX_ST_GPT5_MASK				(1 << 7)
- + #define OMAP24XX_ST_GPT4_SHIFT				6
- + #define OMAP24XX_ST_GPT4_MASK				(1 << 6)
- + #define OMAP24XX_ST_GPT3_SHIFT				5
- + #define OMAP24XX_ST_GPT3_MASK				(1 << 5)
- + #define OMAP24XX_ST_GPT2_SHIFT				4
- + #define OMAP24XX_ST_GPT2_MASK				(1 << 4)
- + #define OMAP2420_ST_VLYNQ_SHIFT				3
- + #define OMAP2420_ST_VLYNQ_MASK				(1 << 3)
- + 
- + /* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */
- + #define OMAP2430_ST_MDM_INTC_SHIFT			11
- + #define OMAP2430_ST_MDM_INTC_MASK			(1 << 11)
- + #define OMAP2430_ST_GPIO5_SHIFT				10
- + #define OMAP2430_ST_GPIO5_MASK				(1 << 10)
- + #define OMAP2430_ST_MCSPI3_SHIFT			9
- + #define OMAP2430_ST_MCSPI3_MASK				(1 << 9)
- + #define OMAP2430_ST_MMCHS2_SHIFT			8
- + #define OMAP2430_ST_MMCHS2_MASK				(1 << 8)
- + #define OMAP2430_ST_MMCHS1_SHIFT			7
- + #define OMAP2430_ST_MMCHS1_MASK				(1 << 7)
- + #define OMAP2430_ST_USBHS_SHIFT				6
- + #define OMAP2430_ST_USBHS_MASK				(1 << 6)
- + #define OMAP24XX_ST_UART3_SHIFT				2
- + #define OMAP24XX_ST_UART3_MASK				(1 << 2)
- + #define OMAP24XX_ST_USB_SHIFT				0
- + #define OMAP24XX_ST_USB_MASK				(1 << 0)
- + 
- + /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
- + #define OMAP24XX_EN_GPIOS_SHIFT				2
- + #define OMAP24XX_EN_GPIOS_MASK				(1 << 2)
- + #define OMAP24XX_EN_GPT1_SHIFT				0
- + #define OMAP24XX_EN_GPT1_MASK				(1 << 0)
- + 
- + /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
- + #define OMAP24XX_ST_GPIOS_SHIFT				2
- + #define OMAP24XX_ST_GPIOS_MASK				(1 << 2)
- + #define OMAP24XX_ST_GPT1_SHIFT				0
- + #define OMAP24XX_ST_GPT1_MASK				(1 << 0)
- + 
- + /* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
- + #define OMAP2430_ST_MDM_SHIFT				0
- + #define OMAP2430_ST_MDM_MASK				(1 << 0)
- + 
- + 
- + /* 3430 register bits shared between CM & PRM registers */
- + 
- + /* CM_REVISION, PRM_REVISION shared bits */
- + #define OMAP3430_REV_SHIFT				0
- + #define OMAP3430_REV_MASK				(0xff << 0)
- + 
- + /* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */
- + #define OMAP3430_AUTOIDLE_MASK				(1 << 0)
- + 
- + /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
- + #define OMAP3430_EN_MMC3_MASK				(1 << 30)
- + #define OMAP3430_EN_MMC3_SHIFT				30
- + #define OMAP3430_EN_MMC2_MASK				(1 << 25)
- + #define OMAP3430_EN_MMC2_SHIFT				25
- + #define OMAP3430_EN_MMC1_MASK				(1 << 24)
- + #define OMAP3430_EN_MMC1_SHIFT				24
- + #define OMAP3430_EN_UART4_MASK				(1 << 23)
- + #define OMAP3430_EN_UART4_SHIFT				23
- + #define OMAP3430_EN_MCSPI4_MASK				(1 << 21)
- + #define OMAP3430_EN_MCSPI4_SHIFT			21
- + #define OMAP3430_EN_MCSPI3_MASK				(1 << 20)
- + #define OMAP3430_EN_MCSPI3_SHIFT			20
- + #define OMAP3430_EN_MCSPI2_MASK				(1 << 19)
- + #define OMAP3430_EN_MCSPI2_SHIFT			19
- + #define OMAP3430_EN_MCSPI1_MASK				(1 << 18)
- + #define OMAP3430_EN_MCSPI1_SHIFT			18
- + #define OMAP3430_EN_I2C3_MASK				(1 << 17)
- + #define OMAP3430_EN_I2C3_SHIFT				17
- + #define OMAP3430_EN_I2C2_MASK				(1 << 16)
- + #define OMAP3430_EN_I2C2_SHIFT				16
- + #define OMAP3430_EN_I2C1_MASK				(1 << 15)
- + #define OMAP3430_EN_I2C1_SHIFT				15
- + #define OMAP3430_EN_UART2_MASK				(1 << 14)
- + #define OMAP3430_EN_UART2_SHIFT				14
- + #define OMAP3430_EN_UART1_MASK				(1 << 13)
- + #define OMAP3430_EN_UART1_SHIFT				13
- + #define OMAP3430_EN_GPT11_MASK				(1 << 12)
- + #define OMAP3430_EN_GPT11_SHIFT				12
- + #define OMAP3430_EN_GPT10_MASK				(1 << 11)
- + #define OMAP3430_EN_GPT10_SHIFT				11
- + #define OMAP3430_EN_MCBSP5_MASK				(1 << 10)
- + #define OMAP3430_EN_MCBSP5_SHIFT			10
- + #define OMAP3430_EN_MCBSP1_MASK				(1 << 9)
- + #define OMAP3430_EN_MCBSP1_SHIFT			9
- + #define OMAP3430_EN_FSHOSTUSB_MASK			(1 << 5)
- + #define OMAP3430_EN_FSHOSTUSB_SHIFT			5
- + #define OMAP3430_EN_D2D_MASK				(1 << 3)
- + #define OMAP3430_EN_D2D_SHIFT				3
- + 
- + /* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
- + #define OMAP3430_EN_HSOTGUSB_MASK			(1 << 4)
- + #define OMAP3430_EN_HSOTGUSB_SHIFT			4
- + 
- + /* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */
- + #define OMAP3430_ST_MMC3_SHIFT				30
- + #define OMAP3430_ST_MMC3_MASK				(1 << 30)
- + #define OMAP3430_ST_MMC2_SHIFT				25
- + #define OMAP3430_ST_MMC2_MASK				(1 << 25)
- + #define OMAP3430_ST_MMC1_SHIFT				24
- + #define OMAP3430_ST_MMC1_MASK				(1 << 24)
- + #define OMAP3430_ST_MCSPI4_SHIFT			21
- + #define OMAP3430_ST_MCSPI4_MASK				(1 << 21)
- + #define OMAP3430_ST_MCSPI3_SHIFT			20
- + #define OMAP3430_ST_MCSPI3_MASK				(1 << 20)
- + #define OMAP3430_ST_MCSPI2_SHIFT			19
- + #define OMAP3430_ST_MCSPI2_MASK				(1 << 19)
- + #define OMAP3430_ST_MCSPI1_SHIFT			18
- + #define OMAP3430_ST_MCSPI1_MASK				(1 << 18)
- + #define OMAP3430_ST_I2C3_SHIFT				17
- + #define OMAP3430_ST_I2C3_MASK				(1 << 17)
- + #define OMAP3430_ST_I2C2_SHIFT				16
- + #define OMAP3430_ST_I2C2_MASK				(1 << 16)
- + #define OMAP3430_ST_I2C1_SHIFT				15
- + #define OMAP3430_ST_I2C1_MASK				(1 << 15)
- + #define OMAP3430_ST_UART2_SHIFT				14
- + #define OMAP3430_ST_UART2_MASK				(1 << 14)
- + #define OMAP3430_ST_UART1_SHIFT				13
- + #define OMAP3430_ST_UART1_MASK				(1 << 13)
- + #define OMAP3430_ST_GPT11_SHIFT				12
- + #define OMAP3430_ST_GPT11_MASK				(1 << 12)
- + #define OMAP3430_ST_GPT10_SHIFT				11
- + #define OMAP3430_ST_GPT10_MASK				(1 << 11)
- + #define OMAP3430_ST_MCBSP5_SHIFT			10
- + #define OMAP3430_ST_MCBSP5_MASK				(1 << 10)
- + #define OMAP3430_ST_MCBSP1_SHIFT			9
- + #define OMAP3430_ST_MCBSP1_MASK				(1 << 9)
- + #define OMAP3430ES1_ST_FSHOSTUSB_SHIFT			5
- + #define OMAP3430ES1_ST_FSHOSTUSB_MASK			(1 << 5)
- + #define OMAP3430ES1_ST_HSOTGUSB_SHIFT			4
- + #define OMAP3430ES1_ST_HSOTGUSB_MASK			(1 << 4)
- + #define OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT		5
- + #define OMAP3430ES2_ST_HSOTGUSB_IDLE_MASK		(1 << 5)
- + #define OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT		4
- + #define OMAP3430ES2_ST_HSOTGUSB_STDBY_MASK		(1 << 4)
- + #define OMAP3430_ST_D2D_SHIFT				3
- + #define OMAP3430_ST_D2D_MASK				(1 << 3)
- + 
- + /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
- + #define OMAP3430_EN_GPIO1_MASK				(1 << 3)
- + #define OMAP3430_EN_GPIO1_SHIFT				3
- + #define OMAP3430_EN_GPT12_MASK				(1 << 1)
- + #define OMAP3430_EN_GPT12_SHIFT				1
- + #define OMAP3430_EN_GPT1_MASK				(1 << 0)
- + #define OMAP3430_EN_GPT1_SHIFT				0
- + 
- + /* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */
- + #define OMAP3430_EN_SR2_MASK				(1 << 7)
- + #define OMAP3430_EN_SR2_SHIFT				7
- + #define OMAP3430_EN_SR1_MASK				(1 << 6)
- + #define OMAP3430_EN_SR1_SHIFT				6
- + 
- + /* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
- + #define OMAP3430_EN_GPT12_MASK				(1 << 1)
- + #define OMAP3430_EN_GPT12_SHIFT				1
- + 
- + /* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */
- + #define OMAP3430_ST_SR2_SHIFT				7
- + #define OMAP3430_ST_SR2_MASK				(1 << 7)
- + #define OMAP3430_ST_SR1_SHIFT				6
- + #define OMAP3430_ST_SR1_MASK				(1 << 6)
- + #define OMAP3430_ST_GPIO1_SHIFT				3
- + #define OMAP3430_ST_GPIO1_MASK				(1 << 3)
- + #define OMAP3430_ST_GPT12_SHIFT				1
- + #define OMAP3430_ST_GPT12_MASK				(1 << 1)
- + #define OMAP3430_ST_GPT1_SHIFT				0
- + #define OMAP3430_ST_GPT1_MASK				(1 << 0)
- + 
- + /*
- +  * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM,
- +  * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX,
- +  * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits
- +  */
- + #define OMAP3430_EN_MPU_MASK				(1 << 1)
- + #define OMAP3430_EN_MPU_SHIFT				1
- + 
- + /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */
- + 
- + #define OMAP3630_EN_UART4_MASK				(1 << 18)
- + #define OMAP3630_EN_UART4_SHIFT				18
- + #define OMAP3430_EN_GPIO6_MASK				(1 << 17)
- + #define OMAP3430_EN_GPIO6_SHIFT				17
- + #define OMAP3430_EN_GPIO5_MASK				(1 << 16)
- + #define OMAP3430_EN_GPIO5_SHIFT				16
- + #define OMAP3430_EN_GPIO4_MASK				(1 << 15)
- + #define OMAP3430_EN_GPIO4_SHIFT				15
- + #define OMAP3430_EN_GPIO3_MASK				(1 << 14)
- + #define OMAP3430_EN_GPIO3_SHIFT				14
- + #define OMAP3430_EN_GPIO2_MASK				(1 << 13)
- + #define OMAP3430_EN_GPIO2_SHIFT				13
- + #define OMAP3430_EN_UART3_MASK				(1 << 11)
- + #define OMAP3430_EN_UART3_SHIFT				11
- + #define OMAP3430_EN_GPT9_MASK				(1 << 10)
- + #define OMAP3430_EN_GPT9_SHIFT				10
- + #define OMAP3430_EN_GPT8_MASK				(1 << 9)
- + #define OMAP3430_EN_GPT8_SHIFT				9
- + #define OMAP3430_EN_GPT7_MASK				(1 << 8)
- + #define OMAP3430_EN_GPT7_SHIFT				8
- + #define OMAP3430_EN_GPT6_MASK				(1 << 7)
- + #define OMAP3430_EN_GPT6_SHIFT				7
- + #define OMAP3430_EN_GPT5_MASK				(1 << 6)
- + #define OMAP3430_EN_GPT5_SHIFT				6
- + #define OMAP3430_EN_GPT4_MASK				(1 << 5)
- + #define OMAP3430_EN_GPT4_SHIFT				5
- + #define OMAP3430_EN_GPT3_MASK				(1 << 4)
- + #define OMAP3430_EN_GPT3_SHIFT				4
- + #define OMAP3430_EN_GPT2_MASK				(1 << 3)
- + #define OMAP3430_EN_GPT2_SHIFT				3
- + 
- + /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */
- + /* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits
- +  * be ST_* bits instead? */
- + #define OMAP3430_EN_MCBSP4_MASK				(1 << 2)
- + #define OMAP3430_EN_MCBSP4_SHIFT			2
- + #define OMAP3430_EN_MCBSP3_MASK				(1 << 1)
- + #define OMAP3430_EN_MCBSP3_SHIFT			1
- + #define OMAP3430_EN_MCBSP2_MASK				(1 << 0)
- + #define OMAP3430_EN_MCBSP2_SHIFT			0
- + 
- + /* CM_IDLEST_PER, PM_WKST_PER shared bits */
- + #define OMAP3630_ST_UART4_SHIFT				18
- + #define OMAP3630_ST_UART4_MASK				(1 << 18)
- + #define OMAP3430_ST_GPIO6_SHIFT				17
- + #define OMAP3430_ST_GPIO6_MASK				(1 << 17)
- + #define OMAP3430_ST_GPIO5_SHIFT				16
- + #define OMAP3430_ST_GPIO5_MASK				(1 << 16)
- + #define OMAP3430_ST_GPIO4_SHIFT				15
- + #define OMAP3430_ST_GPIO4_MASK				(1 << 15)
- + #define OMAP3430_ST_GPIO3_SHIFT				14
- + #define OMAP3430_ST_GPIO3_MASK				(1 << 14)
- + #define OMAP3430_ST_GPIO2_SHIFT				13
- + #define OMAP3430_ST_GPIO2_MASK				(1 << 13)
- + #define OMAP3430_ST_UART3_SHIFT				11
- + #define OMAP3430_ST_UART3_MASK				(1 << 11)
- + #define OMAP3430_ST_GPT9_SHIFT				10
- + #define OMAP3430_ST_GPT9_MASK				(1 << 10)
- + #define OMAP3430_ST_GPT8_SHIFT				9
- + #define OMAP3430_ST_GPT8_MASK				(1 << 9)
- + #define OMAP3430_ST_GPT7_SHIFT				8
- + #define OMAP3430_ST_GPT7_MASK				(1 << 8)
- + #define OMAP3430_ST_GPT6_SHIFT				7
- + #define OMAP3430_ST_GPT6_MASK				(1 << 7)
- + #define OMAP3430_ST_GPT5_SHIFT				6
- + #define OMAP3430_ST_GPT5_MASK				(1 << 6)
- + #define OMAP3430_ST_GPT4_SHIFT				5
- + #define OMAP3430_ST_GPT4_MASK				(1 << 5)
- + #define OMAP3430_ST_GPT3_SHIFT				4
- + #define OMAP3430_ST_GPT3_MASK				(1 << 4)
- + #define OMAP3430_ST_GPT2_SHIFT				3
- + #define OMAP3430_ST_GPT2_MASK				(1 << 3)
- + 
- + /* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */
- + #define OMAP3430_EN_CORE_SHIFT				0
- + #define OMAP3430_EN_CORE_MASK				(1 << 0)
- + 
- + 
- + /*
- +  * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP
- +  * submodule to exit hardreset
- +  */
- + #define MAX_MODULE_HARDRESET_WAIT		10000
- + 
- + # ifndef __ASSEMBLER__
- + extern void __iomem *prm_base;
- + extern void __iomem *cm_base;
- + extern void __iomem *cm2_base;
- + 
- + /**
- +  * struct omap_prcm_irq - describes a PRCM interrupt bit
- +  * @name: a short name describing the interrupt type, e.g. "wkup" or "io"
- +  * @offset: the bit shift of the interrupt inside the IRQ{ENABLE,STATUS} regs
- +  * @priority: should this interrupt be handled before @priority=false IRQs?
- +  *
- +  * Describes interrupt bits inside the PRM_IRQ{ENABLE,STATUS}_MPU* registers.
- +  * On systems with multiple PRM MPU IRQ registers, the bitfields read from
- +  * the registers are concatenated, so @offset could be > 31 on these systems -
- +  * see omap_prm_irq_handler() for more details.  I/O ring interrupts should
- +  * have @priority set to true.
- +  */
- + struct omap_prcm_irq {
- + 	const char *name;
- + 	unsigned int offset;
- + 	bool priority;
- + };
- + 
- + /**
- +  * struct omap_prcm_irq_setup - PRCM interrupt controller details
- +  * @ack: PRM register offset for the first PRM_IRQSTATUS_MPU register
- +  * @mask: PRM register offset for the first PRM_IRQENABLE_MPU register
- +  * @nr_regs: number of PRM_IRQ{STATUS,ENABLE}_MPU* registers
- +  * @nr_irqs: number of entries in the @irqs array
- +  * @irqs: ptr to an array of PRCM interrupt bits (see @nr_irqs)
- +  * @irq: MPU IRQ asserted when a PRCM interrupt arrives
- +  * @read_pending_irqs: fn ptr to determine if any PRCM IRQs are pending
- +  * @ocp_barrier: fn ptr to force buffered PRM writes to complete
- +  * @save_and_clear_irqen: fn ptr to save and clear IRQENABLE regs
- +  * @restore_irqen: fn ptr to save and clear IRQENABLE regs
- +  * @saved_mask: IRQENABLE regs are saved here during suspend
- +  * @priority_mask: 1 bit per IRQ, set to 1 if omap_prcm_irq.priority = true
- +  * @base_irq: base dynamic IRQ number, returned from irq_alloc_descs() in init
- +  * @suspended: set to true after Linux suspend code has called our ->prepare()
- +  * @suspend_save_flag: set to true after IRQ masks have been saved and disabled
- +  *
- +  * @saved_mask, @priority_mask, @base_irq, @suspended, and
- +  * @suspend_save_flag are populated dynamically, and are not to be
- +  * specified in static initializers.
- +  */
- + struct omap_prcm_irq_setup {
- + 	u16 ack;
- + 	u16 mask;
- + 	u8 nr_regs;
- + 	u8 nr_irqs;
- + 	const struct omap_prcm_irq *irqs;
- + 	int irq;
- + 	void (*read_pending_irqs)(unsigned long *events);
- + 	void (*ocp_barrier)(void);
- + 	void (*save_and_clear_irqen)(u32 *saved_mask);
- + 	void (*restore_irqen)(u32 *saved_mask);
- + 	u32 *saved_mask;
- + 	u32 *priority_mask;
- + 	int base_irq;
- + 	bool suspended;
- + 	bool suspend_save_flag;
- + };
- + 
- + /* OMAP_PRCM_IRQ: convenience macro for creating struct omap_prcm_irq records */
- + #define OMAP_PRCM_IRQ(_name, _offset, _priority) {	\
- + 	.name = _name,					\
- + 	.offset = _offset,				\
- + 	.priority = _priority				\
- + 	}
- + 
- + extern void omap_prcm_irq_cleanup(void);
- + extern int omap_prcm_register_chain_handler(
- + 	struct omap_prcm_irq_setup *irq_setup);
- + extern int omap_prcm_event_to_irq(const char *event);
- + extern void omap_prcm_irq_prepare(void);
- + extern void omap_prcm_irq_complete(void);
- + 
- + # endif
- + 
- + #endif
- + 
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/prm2xxx_3xxx.c linux-3.2.1/arch/arm/mach-ckb_3352/prm2xxx_3xxx.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/prm2xxx_3xxx.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/prm2xxx_3xxx.c	2014-05-15 13:25:13.979558443 +0900
- ***************
- *** 0 ****
- --- 1,221 ----
- + /*
- +  * OMAP2/3 PRM module functions
- +  *
- +  * Copyright (C) 2010-2011 Texas Instruments, Inc.
- +  * Copyright (C) 2010 Nokia Corporation
- +  * Benoît Cousson
- +  * Paul Walmsley
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #include <linux/kernel.h>
- + #include <linux/errno.h>
- + #include <linux/err.h>
- + #include <linux/io.h>
- + 
- + #include "common.h"
- + #include <plat/cpu.h>
- + #include <plat/prcm.h>
- + 
- + #include "vp.h"
- + 
- + #include "prm2xxx_3xxx.h"
- + #include "cm2xxx_3xxx.h"
- + #include "prm-regbits-24xx.h"
- + #include "prm-regbits-34xx.h"
- + 
- + static const struct omap_prcm_irq omap3_prcm_irqs[] = {
- + 	OMAP_PRCM_IRQ("wkup",	0,	0),
- + 	OMAP_PRCM_IRQ("io",	9,	1),
- + };
- + 
- + static struct omap_prcm_irq_setup omap3_prcm_irq_setup = {
- + 	.ack			= OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
- + 	.mask			= OMAP3_PRM_IRQENABLE_MPU_OFFSET,
- + 	.nr_regs		= 1,
- + 	.irqs			= omap3_prcm_irqs,
- + 	.nr_irqs		= ARRAY_SIZE(omap3_prcm_irqs),
- + 	.irq			= INT_34XX_PRCM_MPU_IRQ,
- + 	.read_pending_irqs	= &omap3xxx_prm_read_pending_irqs,
- + 	.ocp_barrier		= &omap3xxx_prm_ocp_barrier,
- + 	.save_and_clear_irqen	= &omap3xxx_prm_save_and_clear_irqen,
- + 	.restore_irqen		= &omap3xxx_prm_restore_irqen,
- + };
- + 
- + u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
- + {
- + 	return __raw_readl(prm_base + module + idx);
- + }
- + 
- + void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
- + {
- + 	__raw_writel(val, prm_base + module + idx);
- + }
- + 
- + /* Read-modify-write a register in a PRM module. Caller must lock */
- + u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
- + {
- + 	u32 v;
- + 
- + 	v = omap2_prm_read_mod_reg(module, idx);
- + 	v &= ~mask;
- + 	v |= bits;
- + 	omap2_prm_write_mod_reg(v, module, idx);
- + 
- + 	return v;
- + }
- + 
- + /* Read a PRM register, AND it, and shift the result down to bit 0 */
- + u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
- + {
- + 	u32 v;
- + 
- + 	v = omap2_prm_read_mod_reg(domain, idx);
- + 	v &= mask;
- + 	v >>= __ffs(mask);
- + 
- + 	return v;
- + }
- + 
- + u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
- + {
- + 	return omap2_prm_rmw_mod_reg_bits(bits, bits, module, idx);
- + }
- + 
- + u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
- + {
- + 	return omap2_prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
- + }
- + 
- + 
- + /* PRM VP */
- + 
- + /*
- +  * struct omap3_vp - OMAP3 VP register access description.
- +  * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
- +  */
- + struct omap3_vp {
- + 	u32 tranxdone_status;
- + };
- + 
- + static struct omap3_vp omap3_vp[] = {
- + 	[OMAP3_VP_VDD_MPU_ID] = {
- + 		.tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK,
- + 	},
- + 	[OMAP3_VP_VDD_CORE_ID] = {
- + 		.tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK,
- + 	},
- + };
- + 
- + #define MAX_VP_ID ARRAY_SIZE(omap3_vp);
- + 
- + u32 omap3_prm_vp_check_txdone(u8 vp_id)
- + {
- + 	struct omap3_vp *vp = &omap3_vp[vp_id];
- + 	u32 irqstatus;
- + 
- + 	irqstatus = omap2_prm_read_mod_reg(OCP_MOD,
- + 					   OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
- + 	return irqstatus & vp->tranxdone_status;
- + }
- + 
- + void omap3_prm_vp_clear_txdone(u8 vp_id)
- + {
- + 	struct omap3_vp *vp = &omap3_vp[vp_id];
- + 
- + 	omap2_prm_write_mod_reg(vp->tranxdone_status,
- + 				OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
- + }
- + 
- + u32 omap3_prm_vcvp_read(u8 offset)
- + {
- + 	return omap2_prm_read_mod_reg(OMAP3430_GR_MOD, offset);
- + }
- + 
- + void omap3_prm_vcvp_write(u32 val, u8 offset)
- + {
- + 	omap2_prm_write_mod_reg(val, OMAP3430_GR_MOD, offset);
- + }
- + 
- + u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
- + {
- + 	return omap2_prm_rmw_mod_reg_bits(mask, bits, OMAP3430_GR_MOD, offset);
- + }
- + 
- + /**
- +  * omap3xxx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
- +  * @events: ptr to a u32, preallocated by caller
- +  *
- +  * Read PRM_IRQSTATUS_MPU bits, AND'ed with the currently-enabled PRM
- +  * MPU IRQs, and store the result into the u32 pointed to by @events.
- +  * No return value.
- +  */
- + void omap3xxx_prm_read_pending_irqs(unsigned long *events)
- + {
- + 	u32 mask, st;
- + 
- + 	/* XXX Can the mask read be avoided (e.g., can it come from RAM?) */
- + 	mask = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
- + 	st = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
- + 
- + 	events[0] = mask & st;
- + }
- + 
- + /**
- +  * omap3xxx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
- +  *
- +  * Force any buffered writes to the PRM IP block to complete.  Needed
- +  * by the PRM IRQ handler, which reads and writes directly to the IP
- +  * block, to avoid race conditions after acknowledging or clearing IRQ
- +  * bits.  No return value.
- +  */
- + void omap3xxx_prm_ocp_barrier(void)
- + {
- + 	omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
- + }
- + 
- + /**
- +  * omap3xxx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU reg
- +  * @saved_mask: ptr to a u32 array to save IRQENABLE bits
- +  *
- +  * Save the PRM_IRQENABLE_MPU register to @saved_mask.  @saved_mask
- +  * must be allocated by the caller.  Intended to be used in the PRM
- +  * interrupt handler suspend callback.  The OCP barrier is needed to
- +  * ensure the write to disable PRM interrupts reaches the PRM before
- +  * returning; otherwise, spurious interrupts might occur.  No return
- +  * value.
- +  */
- + void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask)
- + {
- + 	saved_mask[0] = omap2_prm_read_mod_reg(OCP_MOD,
- + 					       OMAP3_PRM_IRQENABLE_MPU_OFFSET);
- + 	omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
- + 
- + 	/* OCP barrier */
- + 	omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
- + }
- + 
- + /**
- +  * omap3xxx_prm_restore_irqen - set PRM_IRQENABLE_MPU register from args
- +  * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
- +  *
- +  * Restore the PRM_IRQENABLE_MPU register from @saved_mask.  Intended
- +  * to be used in the PRM interrupt handler resume callback to restore
- +  * values saved by omap3xxx_prm_save_and_clear_irqen().  No OCP
- +  * barrier should be needed here; any pending PRM interrupts will fire
- +  * once the writes reach the PRM.  No return value.
- +  */
- + void omap3xxx_prm_restore_irqen(u32 *saved_mask)
- + {
- + 	omap2_prm_write_mod_reg(saved_mask[0], OCP_MOD,
- + 				OMAP3_PRM_IRQENABLE_MPU_OFFSET);
- + }
- + 
- + static int __init omap3xxx_prcm_init(void)
- + {
- + 	return 0;
- + }
- + subsys_initcall(omap3xxx_prcm_init);
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/prm2xxx_3xxx.h linux-3.2.1/arch/arm/mach-ckb_3352/prm2xxx_3xxx.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/prm2xxx_3xxx.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/prm2xxx_3xxx.h	2014-05-15 13:25:13.979558443 +0900
- ***************
- *** 0 ****
- --- 1,379 ----
- + /*
- +  * OMAP2/3 Power/Reset Management (PRM) register definitions
- +  *
- +  * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc.
- +  * Copyright (C) 2008-2010 Nokia Corporation
- +  * Paul Walmsley
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  *
- +  * The PRM hardware modules on the OMAP2/3 are quite similar to each
- +  * other.  The PRM on OMAP4 has a new register layout, and is handled
- +  * in a separate file.
- +  */
- + #ifndef __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H
- + #define __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H
- + 
- + #include "prcm-common.h"
- + #include "prm.h"
- + 
- + #define OMAP2420_PRM_REGADDR(module, reg)				\
- + 		OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
- + #define OMAP2430_PRM_REGADDR(module, reg)				\
- + 		OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
- + #define OMAP34XX_PRM_REGADDR(module, reg)				\
- + 		OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
- + 
- + 
- + /*
- +  * OMAP2-specific global PRM registers
- +  * Use __raw_{read,write}l() with these registers.
- +  *
- +  * With a few exceptions, these are the register names beginning with
- +  * PRCM_* on 24xx.  (The exceptions are the IRQSTATUS and IRQENABLE
- +  * bits.)
- +  *
- +  */
- + 
- + #define OMAP2_PRCM_REVISION_OFFSET	0x0000
- + #define OMAP2420_PRCM_REVISION		OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000)
- + #define OMAP2_PRCM_SYSCONFIG_OFFSET	0x0010
- + #define OMAP2420_PRCM_SYSCONFIG		OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010)
- + 
- + #define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET	0x0018
- + #define OMAP2420_PRCM_IRQSTATUS_MPU	OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018)
- + #define OMAP2_PRCM_IRQENABLE_MPU_OFFSET	0x001c
- + #define OMAP2420_PRCM_IRQENABLE_MPU	OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c)
- + 
- + #define OMAP2_PRCM_VOLTCTRL_OFFSET	0x0050
- + #define OMAP2420_PRCM_VOLTCTRL		OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050)
- + #define OMAP2_PRCM_VOLTST_OFFSET	0x0054
- + #define OMAP2420_PRCM_VOLTST		OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054)
- + #define OMAP2_PRCM_CLKSRC_CTRL_OFFSET	0x0060
- + #define OMAP2420_PRCM_CLKSRC_CTRL	OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060)
- + #define OMAP2_PRCM_CLKOUT_CTRL_OFFSET	0x0070
- + #define OMAP2420_PRCM_CLKOUT_CTRL	OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070)
- + #define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET	0x0078
- + #define OMAP2420_PRCM_CLKEMUL_CTRL	OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078)
- + #define OMAP2_PRCM_CLKCFG_CTRL_OFFSET	0x0080
- + #define OMAP2420_PRCM_CLKCFG_CTRL	OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080)
- + #define OMAP2_PRCM_CLKCFG_STATUS_OFFSET	0x0084
- + #define OMAP2420_PRCM_CLKCFG_STATUS	OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084)
- + #define OMAP2_PRCM_VOLTSETUP_OFFSET	0x0090
- + #define OMAP2420_PRCM_VOLTSETUP		OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090)
- + #define OMAP2_PRCM_CLKSSETUP_OFFSET	0x0094
- + #define OMAP2420_PRCM_CLKSSETUP		OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094)
- + #define OMAP2_PRCM_POLCTRL_OFFSET	0x0098
- + #define OMAP2420_PRCM_POLCTRL		OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098)
- + 
- + #define OMAP2430_PRCM_REVISION		OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000)
- + #define OMAP2430_PRCM_SYSCONFIG		OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010)
- + 
- + #define OMAP2430_PRCM_IRQSTATUS_MPU	OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018)
- + #define OMAP2430_PRCM_IRQENABLE_MPU	OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c)
- + 
- + #define OMAP2430_PRCM_VOLTCTRL		OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050)
- + #define OMAP2430_PRCM_VOLTST		OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054)
- + #define OMAP2430_PRCM_CLKSRC_CTRL	OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060)
- + #define OMAP2430_PRCM_CLKOUT_CTRL	OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070)
- + #define OMAP2430_PRCM_CLKEMUL_CTRL	OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078)
- + #define OMAP2430_PRCM_CLKCFG_CTRL	OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080)
- + #define OMAP2430_PRCM_CLKCFG_STATUS	OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084)
- + #define OMAP2430_PRCM_VOLTSETUP		OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090)
- + #define OMAP2430_PRCM_CLKSSETUP		OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094)
- + #define OMAP2430_PRCM_POLCTRL		OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098)
- + 
- + /*
- +  * OMAP3-specific global PRM registers
- +  * Use __raw_{read,write}l() with these registers.
- +  *
- +  * With a few exceptions, these are the register names beginning with
- +  * PRM_* on 34xx.  (The exceptions are the IRQSTATUS and IRQENABLE
- +  * bits.)
- +  */
- + 
- + #define OMAP3_PRM_REVISION_OFFSET	0x0004
- + #define OMAP3430_PRM_REVISION		OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
- + #define OMAP3_PRM_SYSCONFIG_OFFSET	0x0014
- + #define OMAP3430_PRM_SYSCONFIG		OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
- + 
- + #define OMAP3_PRM_IRQSTATUS_MPU_OFFSET	0x0018
- + #define OMAP3430_PRM_IRQSTATUS_MPU	OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
- + #define OMAP3_PRM_IRQENABLE_MPU_OFFSET	0x001c
- + #define OMAP3430_PRM_IRQENABLE_MPU	OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
- + 
- + 
- + #define OMAP3_PRM_VC_SMPS_SA_OFFSET	0x0020
- + #define OMAP3430_PRM_VC_SMPS_SA		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
- + #define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET	0x0024
- + #define OMAP3430_PRM_VC_SMPS_VOL_RA	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
- + #define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET	0x0028
- + #define OMAP3430_PRM_VC_SMPS_CMD_RA	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
- + #define OMAP3_PRM_VC_CMD_VAL_0_OFFSET	0x002c
- + #define OMAP3430_PRM_VC_CMD_VAL_0	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
- + #define OMAP3_PRM_VC_CMD_VAL_1_OFFSET	0x0030
- + #define OMAP3430_PRM_VC_CMD_VAL_1	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
- + #define OMAP3_PRM_VC_CH_CONF_OFFSET	0x0034
- + #define OMAP3430_PRM_VC_CH_CONF		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
- + #define OMAP3_PRM_VC_I2C_CFG_OFFSET	0x0038
- + #define OMAP3430_PRM_VC_I2C_CFG		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
- + #define OMAP3_PRM_VC_BYPASS_VAL_OFFSET	0x003c
- + #define OMAP3430_PRM_VC_BYPASS_VAL	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
- + #define OMAP3_PRM_RSTCTRL_OFFSET	0x0050
- + #define OMAP3430_PRM_RSTCTRL		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
- + #define OMAP3_PRM_RSTTIME_OFFSET	0x0054
- + #define OMAP3430_PRM_RSTTIME		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
- + #define OMAP3_PRM_RSTST_OFFSET	0x0058
- + #define OMAP3430_PRM_RSTST		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
- + #define OMAP3_PRM_VOLTCTRL_OFFSET	0x0060
- + #define OMAP3430_PRM_VOLTCTRL		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
- + #define OMAP3_PRM_SRAM_PCHARGE_OFFSET	0x0064
- + #define OMAP3430_PRM_SRAM_PCHARGE	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
- + #define OMAP3_PRM_CLKSRC_CTRL_OFFSET	0x0070
- + #define OMAP3430_PRM_CLKSRC_CTRL	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
- + #define OMAP3_PRM_VOLTSETUP1_OFFSET	0x0090
- + #define OMAP3430_PRM_VOLTSETUP1		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
- + #define OMAP3_PRM_VOLTOFFSET_OFFSET	0x0094
- + #define OMAP3430_PRM_VOLTOFFSET		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
- + #define OMAP3_PRM_CLKSETUP_OFFSET	0x0098
- + #define OMAP3430_PRM_CLKSETUP		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
- + #define OMAP3_PRM_POLCTRL_OFFSET	0x009c
- + #define OMAP3430_PRM_POLCTRL		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
- + #define OMAP3_PRM_VOLTSETUP2_OFFSET	0x00a0
- + #define OMAP3430_PRM_VOLTSETUP2		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
- + #define OMAP3_PRM_VP1_CONFIG_OFFSET	0x00b0
- + #define OMAP3430_PRM_VP1_CONFIG		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
- + #define OMAP3_PRM_VP1_VSTEPMIN_OFFSET	0x00b4
- + #define OMAP3430_PRM_VP1_VSTEPMIN	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
- + #define OMAP3_PRM_VP1_VSTEPMAX_OFFSET	0x00b8
- + #define OMAP3430_PRM_VP1_VSTEPMAX	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
- + #define OMAP3_PRM_VP1_VLIMITTO_OFFSET	0x00bc
- + #define OMAP3430_PRM_VP1_VLIMITTO	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
- + #define OMAP3_PRM_VP1_VOLTAGE_OFFSET	0x00c0
- + #define OMAP3430_PRM_VP1_VOLTAGE	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
- + #define OMAP3_PRM_VP1_STATUS_OFFSET	0x00c4
- + #define OMAP3430_PRM_VP1_STATUS		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
- + #define OMAP3_PRM_VP2_CONFIG_OFFSET	0x00d0
- + #define OMAP3430_PRM_VP2_CONFIG		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
- + #define OMAP3_PRM_VP2_VSTEPMIN_OFFSET	0x00d4
- + #define OMAP3430_PRM_VP2_VSTEPMIN	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
- + #define OMAP3_PRM_VP2_VSTEPMAX_OFFSET	0x00d8
- + #define OMAP3430_PRM_VP2_VSTEPMAX	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
- + #define OMAP3_PRM_VP2_VLIMITTO_OFFSET	0x00dc
- + #define OMAP3430_PRM_VP2_VLIMITTO	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
- + #define OMAP3_PRM_VP2_VOLTAGE_OFFSET	0x00e0
- + #define OMAP3430_PRM_VP2_VOLTAGE	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
- + #define OMAP3_PRM_VP2_STATUS_OFFSET	0x00e4
- + #define OMAP3430_PRM_VP2_STATUS		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
- + 
- + #define OMAP3_PRM_CLKSEL_OFFSET	0x0040
- + #define OMAP3430_PRM_CLKSEL		OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
- + #define OMAP3_PRM_CLKOUT_CTRL_OFFSET	0x0070
- + #define OMAP3430_PRM_CLKOUT_CTRL	OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
- + 
- + /*
- +  * Module specific PRM register offsets from PRM_BASE + domain offset
- +  *
- +  * Use prm_{read,write}_mod_reg() with these registers.
- +  *
- +  * With a few exceptions, these are the register names beginning with
- +  * {PM,RM}_* on both OMAP2/3 SoC families..  (The exceptions are the
- +  * IRQSTATUS and IRQENABLE bits.)
- +  */
- + 
- + /* Register offsets appearing on both OMAP2 and OMAP3 */
- + 
- + #define OMAP2_RM_RSTCTRL				0x0050
- + #define OMAP2_RM_RSTTIME				0x0054
- + #define OMAP2_RM_RSTST					0x0058
- + #define OMAP2_PM_PWSTCTRL				0x00e0
- + #define OMAP2_PM_PWSTST					0x00e4
- + 
- + #define PM_WKEN						0x00a0
- + #define PM_WKEN1					PM_WKEN
- + #define PM_WKST						0x00b0
- + #define PM_WKST1					PM_WKST
- + #define PM_WKDEP					0x00c8
- + #define PM_EVGENCTRL					0x00d4
- + #define PM_EVGENONTIM					0x00d8
- + #define PM_EVGENOFFTIM					0x00dc
- + 
- + /* OMAP2xxx specific register offsets */
- + #define OMAP24XX_PM_WKEN2				0x00a4
- + #define OMAP24XX_PM_WKST2				0x00b4
- + 
- + #define OMAP24XX_PRCM_IRQSTATUS_DSP			0x00f0	/* IVA mod */
- + #define OMAP24XX_PRCM_IRQENABLE_DSP			0x00f4	/* IVA mod */
- + #define OMAP24XX_PRCM_IRQSTATUS_IVA			0x00f8
- + #define OMAP24XX_PRCM_IRQENABLE_IVA			0x00fc
- + 
- + /* OMAP3 specific register offsets */
- + #define OMAP3430ES2_PM_WKEN3				0x00f0
- + #define OMAP3430ES2_PM_WKST3				0x00b8
- + 
- + #define OMAP3430_PM_MPUGRPSEL				0x00a4
- + #define OMAP3430_PM_MPUGRPSEL1				OMAP3430_PM_MPUGRPSEL
- + #define OMAP3430ES2_PM_MPUGRPSEL3			0x00f8
- + 
- + #define OMAP3430_PM_IVAGRPSEL				0x00a8
- + #define OMAP3430_PM_IVAGRPSEL1				OMAP3430_PM_IVAGRPSEL
- + #define OMAP3430ES2_PM_IVAGRPSEL3			0x00f4
- + 
- + #define OMAP3430_PM_PREPWSTST				0x00e8
- + 
- + #define OMAP3430_PRM_IRQSTATUS_IVA2			0x00f8
- + #define OMAP3430_PRM_IRQENABLE_IVA2			0x00fc
- + 
- + 
- + #ifndef __ASSEMBLER__
- + /* Power/reset management domain register get/set */
- + extern u32 omap2_prm_read_mod_reg(s16 module, u16 idx);
- + extern void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx);
- + extern u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
- + extern u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx);
- + extern u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx);
- + extern u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask);
- + 
- + /* OMAP3-specific VP functions */
- + u32 omap3_prm_vp_check_txdone(u8 vp_id);
- + void omap3_prm_vp_clear_txdone(u8 vp_id);
- + 
- + /*
- +  * OMAP3 access functions for voltage controller (VC) and
- +  * voltage proccessor (VP) in the PRM.
- +  */
- + extern u32 omap3_prm_vcvp_read(u8 offset);
- + extern void omap3_prm_vcvp_write(u32 val, u8 offset);
- + extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
- + 
- + /* PRM interrupt-related functions */
- + extern void omap3xxx_prm_read_pending_irqs(unsigned long *events);
- + extern void omap3xxx_prm_ocp_barrier(void);
- + extern void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask);
- + extern void omap3xxx_prm_restore_irqen(u32 *saved_mask);
- + 
- + #endif
- + 
- + /*
- +  * Bits common to specific registers
- +  *
- +  * The 3430 register and bit names are generally used,
- +  * since they tend to make more sense
- +  */
- + 
- + /* PM_EVGENONTIM_MPU */
- + /* Named PM_EVEGENONTIM_MPU on the 24XX */
- + #define OMAP_ONTIMEVAL_SHIFT				0
- + #define OMAP_ONTIMEVAL_MASK				(0xffffffff << 0)
- + 
- + /* PM_EVGENOFFTIM_MPU */
- + /* Named PM_EVEGENOFFTIM_MPU on the 24XX */
- + #define OMAP_OFFTIMEVAL_SHIFT				0
- + #define OMAP_OFFTIMEVAL_MASK				(0xffffffff << 0)
- + 
- + /* PRM_CLKSETUP and PRCM_VOLTSETUP */
- + /* Named PRCM_CLKSSETUP on the 24XX */
- + #define OMAP_SETUP_TIME_SHIFT				0
- + #define OMAP_SETUP_TIME_MASK				(0xffff << 0)
- + 
- + /* PRM_CLKSRC_CTRL */
- + /* Named PRCM_CLKSRC_CTRL on the 24XX */
- + #define OMAP_SYSCLKDIV_SHIFT				6
- + #define OMAP_SYSCLKDIV_MASK				(0x3 << 6)
- + #define OMAP_AUTOEXTCLKMODE_SHIFT			3
- + #define OMAP_AUTOEXTCLKMODE_MASK			(0x3 << 3)
- + #define OMAP_SYSCLKSEL_SHIFT				0
- + #define OMAP_SYSCLKSEL_MASK				(0x3 << 0)
- + 
- + /* PM_EVGENCTRL_MPU */
- + #define OMAP_OFFLOADMODE_SHIFT				3
- + #define OMAP_OFFLOADMODE_MASK				(0x3 << 3)
- + #define OMAP_ONLOADMODE_SHIFT				1
- + #define OMAP_ONLOADMODE_MASK				(0x3 << 1)
- + #define OMAP_ENABLE_MASK				(1 << 0)
- + 
- + /* PRM_RSTTIME */
- + /* Named RM_RSTTIME_WKUP on the 24xx */
- + #define OMAP_RSTTIME2_SHIFT				8
- + #define OMAP_RSTTIME2_MASK				(0x1f << 8)
- + #define OMAP_RSTTIME1_SHIFT				0
- + #define OMAP_RSTTIME1_MASK				(0xff << 0)
- + 
- + /* PRM_RSTCTRL */
- + /* Named RM_RSTCTRL_WKUP on the 24xx */
- + /* 2420 calls RST_DPLL3 'RST_DPLL' */
- + #define OMAP_RST_DPLL3_MASK				(1 << 2)
- + #define OMAP_RST_GS_MASK				(1 << 1)
- + 
- + 
- + /*
- +  * Bits common to module-shared registers
- +  *
- +  * Not all registers of a particular type support all of these bits -
- +  * check TRM if you are unsure
- +  */
- + 
- + /*
- +  * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is
- +  *	 called 'COREWKUP_RST'
- +  *
- +  * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
- +  *	 RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
- +  */
- + #define OMAP_COREDOMAINWKUP_RST_MASK			(1 << 3)
- + 
- + /*
- +  * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
- +  *
- +  * 2430: RM_RSTST_MDM
- +  *
- +  * 3430: RM_RSTST_CORE, RM_RSTST_EMU
- +  */
- + #define OMAP_DOMAINWKUP_RST_MASK			(1 << 2)
- + 
- + /*
- +  * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
- +  *	 On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'.
- +  *
- +  * 2430: RM_RSTST_MDM
- +  *
- +  * 3430: RM_RSTST_CORE, RM_RSTST_EMU
- +  */
- + #define OMAP_GLOBALWARM_RST_MASK			(1 << 1)
- + #define OMAP_GLOBALCOLD_RST_MASK			(1 << 0)
- + 
- + /*
- +  * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
- +  *	 2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP"
- +  *
- +  * 2430: PM_WKDEP_MDM
- +  *
- +  * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
- +  *	 PM_WKDEP_PER
- +  */
- + #define OMAP_EN_WKUP_SHIFT				4
- + #define OMAP_EN_WKUP_MASK				(1 << 4)
- + 
- + /*
- +  * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
- +  *	 PM_PWSTCTRL_DSP
- +  *
- +  * 2430: PM_PWSTCTRL_MDM
- +  *
- +  * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
- +  *	 PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
- +  *	 PM_PWSTCTRL_NEON
- +  */
- + #define OMAP_LOGICRETSTATE_MASK				(1 << 2)
- + 
- + 
- + /*
- +  * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP
- +  * submodule to exit hardreset
- +  */
- + #define MAX_MODULE_HARDRESET_WAIT		10000
- + 
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/prm33xx.h linux-3.2.1/arch/arm/mach-ckb_3352/prm33xx.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/prm33xx.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/prm33xx.h	2014-05-15 13:25:13.979558443 +0900
- ***************
- *** 0 ****
- --- 1,118 ----
- + /*
- +  * AM33XX PRM instance offset macros
- +  *
- +  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #ifndef __ARCH_ARM_MACH_OMAP2_PRM33XX_H
- + #define __ARCH_ARM_MACH_OMAP2_PRM33XX_H
- + 
- + #include "prcm-common.h"
- + #include "prm.h"
- + 
- + #define AM33XX_PRM_BASE               0x44E00000
- + 
- + #define AM33XX_PRM_REGADDR(inst, reg)                         \
- + 	AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRM_BASE + (inst) + (reg))
- + 
- + /* PRM instances */
- + #define AM33XX_PRM_OCP_SOCKET_MOD	0x0B00
- + #define AM33XX_PRM_PER_MOD		0x0C00
- + #define AM33XX_PRM_WKUP_MOD		0x0D00
- + #define AM33XX_PRM_MPU_MOD		0x0E00
- + #define AM33XX_PRM_DEVICE_MOD		0x0F00
- + #define AM33XX_PRM_RTC_MOD		0x1000
- + #define AM33XX_PRM_GFX_MOD		0x1100
- + #define AM33XX_PRM_CEFUSE_MOD		0x1200
- + 
- + /* PRM */
- + 
- + /* PRM.OCP_SOCKET_PRM register offsets */
- + #define AM33XX_REVISION_PRM_OFFSET		0x0000
- + #define AM33XX_REVISION_PRM			AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0000)
- + #define AM33XX_PRM_IRQSTATUS_MPU_OFFSET		0x0004
- + #define AM33XX_PRM_IRQSTATUS_MPU		AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0004)
- + #define AM33XX_PRM_IRQENABLE_MPU_OFFSET		0x0008
- + #define AM33XX_PRM_IRQENABLE_MPU		AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0008)
- + #define AM33XX_PRM_IRQSTATUS_M3_OFFSET		0x000c
- + #define AM33XX_PRM_IRQSTATUS_M3			AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x000c)
- + #define AM33XX_PRM_IRQENABLE_M3_OFFSET		0x0010
- + #define AM33XX_PRM_IRQENABLE_M3			AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0010)
- + 
- + /* PRM.PER_PRM register offsets */
- + #define AM33XX_RM_PER_RSTCTRL_OFFSET		0x0000
- + #define AM33XX_RM_PER_RSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0000)
- + #define AM33XX_RM_PER_RSTST_OFFSET		0x0004
- + #define AM33XX_RM_PER_RSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0004)
- + #define AM33XX_PM_PER_PWRSTST_OFFSET		0x0008
- + #define AM33XX_PM_PER_PWRSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0008)
- + #define AM33XX_PM_PER_PWRSTCTRL_OFFSET		0x000c
- + #define AM33XX_PM_PER_PWRSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x000c)
- + 
- + /* PRM.WKUP_PRM register offsets */
- + #define AM33XX_RM_WKUP_RSTCTRL_OFFSET		0x0000
- + #define AM33XX_RM_WKUP_RSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0000)
- + #define AM33XX_PM_WKUP_PWRSTCTRL_OFFSET		0x0004
- + #define AM33XX_PM_WKUP_PWRSTCTRL		AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0004)
- + #define AM33XX_PM_WKUP_PWRSTST_OFFSET		0x0008
- + #define AM33XX_PM_WKUP_PWRSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0008)
- + #define AM33XX_RM_WKUP_RSTST_OFFSET		0x000c
- + #define AM33XX_RM_WKUP_RSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x000c)
- + 
- + /* PRM.MPU_PRM register offsets */
- + #define AM33XX_PM_MPU_PWRSTCTRL_OFFSET		0x0000
- + #define AM33XX_PM_MPU_PWRSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0000)
- + #define AM33XX_PM_MPU_PWRSTST_OFFSET		0x0004
- + #define AM33XX_PM_MPU_PWRSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0004)
- + #define AM33XX_RM_MPU_RSTST_OFFSET		0x0008
- + #define AM33XX_RM_MPU_RSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0008)
- + 
- + /* PRM.DEVICE_PRM register offsets */
- + #define AM33XX_PRM_RSTCTRL_OFFSET		0x0000
- + #define AM33XX_PRM_RSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0000)
- + #define AM33XX_PRM_RSTTIME_OFFSET		0x0004
- + #define AM33XX_PRM_RSTTIME			AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0004)
- + #define AM33XX_PRM_RSTST_OFFSET			0x0008
- + #define AM33XX_PRM_RSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0008)
- + #define AM33XX_PRM_SRAM_COUNT_OFFSET		0x000c
- + #define AM33XX_PRM_SRAM_COUNT			AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x000c)
- + #define AM33XX_PRM_LDO_SRAM_CORE_SETUP_OFFSET	0x0010
- + #define AM33XX_PRM_LDO_SRAM_CORE_SETUP		AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0010)
- + #define AM33XX_PRM_LDO_SRAM_CORE_CTRL_OFFSET	0x0014
- + #define AM33XX_PRM_LDO_SRAM_CORE_CTRL		AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0014)
- + #define AM33XX_PRM_LDO_SRAM_MPU_SETUP_OFFSET	0x0018
- + #define AM33XX_PRM_LDO_SRAM_MPU_SETUP		AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0018)
- + #define AM33XX_PRM_LDO_SRAM_MPU_CTRL_OFFSET	0x001c
- + #define AM33XX_PRM_LDO_SRAM_MPU_CTRL		AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x001c)
- + 
- + /* PRM.RTC_PRM register offsets */
- + #define AM33XX_PM_RTC_PWRSTCTRL_OFFSET		0x0000
- + #define AM33XX_PM_RTC_PWRSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_RTC_MOD, 0x0000)
- + #define AM33XX_PM_RTC_PWRSTST_OFFSET		0x0004
- + #define AM33XX_PM_RTC_PWRSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_RTC_MOD, 0x0004)
- + 
- + /* PRM.GFX_PRM register offsets */
- + #define AM33XX_PM_GFX_PWRSTCTRL_OFFSET		0x0000
- + #define AM33XX_PM_GFX_PWRSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0000)
- + #define AM33XX_RM_GFX_RSTCTRL_OFFSET		0x0004
- + #define AM33XX_RM_GFX_RSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0004)
- + #define AM33XX_PM_GFX_PWRSTST_OFFSET		0x0010
- + #define AM33XX_PM_GFX_PWRSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0010)
- + #define AM33XX_RM_GFX_RSTST_OFFSET		0x0014
- + #define AM33XX_RM_GFX_RSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0014)
- + 
- + /* PRM.CEFUSE_PRM register offsets */
- + #define AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET	0x0000
- + #define AM33XX_PM_CEFUSE_PWRSTCTRL		AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0000)
- + #define AM33XX_PM_CEFUSE_PWRSTST_OFFSET		0x0004
- + #define AM33XX_PM_CEFUSE_PWRSTST		AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004)
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/prm44xx.h linux-3.2.1/arch/arm/mach-ckb_3352/prm44xx.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/prm44xx.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/prm44xx.h	2014-05-15 13:25:13.983443033 +0900
- ***************
- *** 0 ****
- --- 1,774 ----
- + /*
- +  * OMAP44xx PRM instance offset macros
- +  *
- +  * Copyright (C) 2009-2011 Texas Instruments, Inc.
- +  * Copyright (C) 2009-2010 Nokia Corporation
- +  *
- +  * Paul Walmsley (paul@pwsan.com)
- +  * Rajendra Nayak (rnayak@ti.com)
- +  * Benoit Cousson (b-cousson@ti.com)
- +  *
- +  * This file is automatically generated from the OMAP hardware databases.
- +  * We respectfully ask that any modifications to this file be coordinated
- +  * with the public linux-omap@vger.kernel.org mailing list and the
- +  * authors above to ensure that the autogeneration scripts are kept
- +  * up-to-date with the file contents.
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  *
- +  * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
- +  *     or "OMAP4430".
- +  */
- + 
- + #ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H
- + #define __ARCH_ARM_MACH_OMAP2_PRM44XX_H
- + 
- + #include "prcm-common.h"
- + #include "prm.h"
- + 
- + #define OMAP4430_PRM_BASE		0x4a306000
- + 
- + #define OMAP44XX_PRM_REGADDR(inst, reg)				\
- + 	OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg))
- + 
- + 
- + /* PRM instances */
- + #define OMAP4430_PRM_OCP_SOCKET_INST	0x0000
- + #define OMAP4430_PRM_CKGEN_INST		0x0100
- + #define OMAP4430_PRM_MPU_INST		0x0300
- + #define OMAP4430_PRM_TESLA_INST		0x0400
- + #define OMAP4430_PRM_ABE_INST		0x0500
- + #define OMAP4430_PRM_ALWAYS_ON_INST	0x0600
- + #define OMAP4430_PRM_CORE_INST		0x0700
- + #define OMAP4430_PRM_IVAHD_INST		0x0f00
- + #define OMAP4430_PRM_CAM_INST		0x1000
- + #define OMAP4430_PRM_DSS_INST		0x1100
- + #define OMAP4430_PRM_GFX_INST		0x1200
- + #define OMAP4430_PRM_L3INIT_INST	0x1300
- + #define OMAP4430_PRM_L4PER_INST		0x1400
- + #define OMAP4430_PRM_CEFUSE_INST	0x1600
- + #define OMAP4430_PRM_WKUP_INST		0x1700
- + #define OMAP4430_PRM_WKUP_CM_INST	0x1800
- + #define OMAP4430_PRM_EMU_INST		0x1900
- + #define OMAP4430_PRM_EMU_CM_INST	0x1a00
- + #define OMAP4430_PRM_DEVICE_INST	0x1b00
- + #define OMAP4430_PRM_INSTR_INST		0x1f00
- + 
- + /* PRM clockdomain register offsets (from instance start) */
- + #define OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS	0x0000
- + #define OMAP4430_PRM_EMU_CM_EMU_CDOFFS		0x0000
- + 
- + /* OMAP4 specific register offsets */
- + #define OMAP4_RM_RSTCTRL				0x0000
- + #define OMAP4_RM_RSTTIME				0x0004
- + #define OMAP4_RM_RSTST					0x0008
- + #define OMAP4_PM_PWSTCTRL				0x0000
- + #define OMAP4_PM_PWSTST					0x0004
- + 
- + 
- + /* PRM */
- + 
- + /* PRM.OCP_SOCKET_PRM register offsets */
- + #define OMAP4_REVISION_PRM_OFFSET			0x0000
- + #define OMAP4430_REVISION_PRM				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0000)
- + #define OMAP4_PRM_IRQSTATUS_MPU_OFFSET			0x0010
- + #define OMAP4430_PRM_IRQSTATUS_MPU			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0010)
- + #define OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET		0x0014
- + #define OMAP4430_PRM_IRQSTATUS_MPU_2			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0014)
- + #define OMAP4_PRM_IRQENABLE_MPU_OFFSET			0x0018
- + #define OMAP4430_PRM_IRQENABLE_MPU			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0018)
- + #define OMAP4_PRM_IRQENABLE_MPU_2_OFFSET		0x001c
- + #define OMAP4430_PRM_IRQENABLE_MPU_2			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x001c)
- + #define OMAP4_PRM_IRQSTATUS_DUCATI_OFFSET		0x0020
- + #define OMAP4430_PRM_IRQSTATUS_DUCATI			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0020)
- + #define OMAP4_PRM_IRQENABLE_DUCATI_OFFSET		0x0028
- + #define OMAP4430_PRM_IRQENABLE_DUCATI			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0028)
- + #define OMAP4_PRM_IRQSTATUS_TESLA_OFFSET		0x0030
- + #define OMAP4430_PRM_IRQSTATUS_TESLA			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0030)
- + #define OMAP4_PRM_IRQENABLE_TESLA_OFFSET		0x0038
- + #define OMAP4430_PRM_IRQENABLE_TESLA			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0038)
- + #define OMAP4_CM_PRM_PROFILING_CLKCTRL_OFFSET		0x0040
- + #define OMAP4430_CM_PRM_PROFILING_CLKCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0040)
- + 
- + /* PRM.CKGEN_PRM register offsets */
- + #define OMAP4_CM_ABE_DSS_SYS_CLKSEL_OFFSET		0x0000
- + #define OMAP4430_CM_ABE_DSS_SYS_CLKSEL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0000)
- + #define OMAP4_CM_L4_WKUP_CLKSEL_OFFSET			0x0008
- + #define OMAP4430_CM_L4_WKUP_CLKSEL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0008)
- + #define OMAP4_CM_ABE_PLL_REF_CLKSEL_OFFSET		0x000c
- + #define OMAP4430_CM_ABE_PLL_REF_CLKSEL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x000c)
- + #define OMAP4_CM_SYS_CLKSEL_OFFSET			0x0010
- + #define OMAP4430_CM_SYS_CLKSEL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0010)
- + 
- + /* PRM.MPU_PRM register offsets */
- + #define OMAP4_PM_MPU_PWRSTCTRL_OFFSET			0x0000
- + #define OMAP4430_PM_MPU_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0000)
- + #define OMAP4_PM_MPU_PWRSTST_OFFSET			0x0004
- + #define OMAP4430_PM_MPU_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0004)
- + #define OMAP4_RM_MPU_RSTST_OFFSET			0x0014
- + #define OMAP4430_RM_MPU_RSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0014)
- + #define OMAP4_RM_MPU_MPU_CONTEXT_OFFSET			0x0024
- + #define OMAP4430_RM_MPU_MPU_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0024)
- + 
- + /* PRM.TESLA_PRM register offsets */
- + #define OMAP4_PM_TESLA_PWRSTCTRL_OFFSET			0x0000
- + #define OMAP4430_PM_TESLA_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0000)
- + #define OMAP4_PM_TESLA_PWRSTST_OFFSET			0x0004
- + #define OMAP4430_PM_TESLA_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0004)
- + #define OMAP4_RM_TESLA_RSTCTRL_OFFSET			0x0010
- + #define OMAP4430_RM_TESLA_RSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0010)
- + #define OMAP4_RM_TESLA_RSTST_OFFSET			0x0014
- + #define OMAP4430_RM_TESLA_RSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0014)
- + #define OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET		0x0024
- + #define OMAP4430_RM_TESLA_TESLA_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0024)
- + 
- + /* PRM.ABE_PRM register offsets */
- + #define OMAP4_PM_ABE_PWRSTCTRL_OFFSET			0x0000
- + #define OMAP4430_PM_ABE_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0000)
- + #define OMAP4_PM_ABE_PWRSTST_OFFSET			0x0004
- + #define OMAP4430_PM_ABE_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0004)
- + #define OMAP4_RM_ABE_AESS_CONTEXT_OFFSET		0x002c
- + #define OMAP4430_RM_ABE_AESS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x002c)
- + #define OMAP4_PM_ABE_PDM_WKDEP_OFFSET			0x0030
- + #define OMAP4430_PM_ABE_PDM_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0030)
- + #define OMAP4_RM_ABE_PDM_CONTEXT_OFFSET			0x0034
- + #define OMAP4430_RM_ABE_PDM_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0034)
- + #define OMAP4_PM_ABE_DMIC_WKDEP_OFFSET			0x0038
- + #define OMAP4430_PM_ABE_DMIC_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0038)
- + #define OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET		0x003c
- + #define OMAP4430_RM_ABE_DMIC_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x003c)
- + #define OMAP4_PM_ABE_MCASP_WKDEP_OFFSET			0x0040
- + #define OMAP4430_PM_ABE_MCASP_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0040)
- + #define OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET		0x0044
- + #define OMAP4430_RM_ABE_MCASP_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0044)
- + #define OMAP4_PM_ABE_MCBSP1_WKDEP_OFFSET		0x0048
- + #define OMAP4430_PM_ABE_MCBSP1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0048)
- + #define OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET		0x004c
- + #define OMAP4430_RM_ABE_MCBSP1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x004c)
- + #define OMAP4_PM_ABE_MCBSP2_WKDEP_OFFSET		0x0050
- + #define OMAP4430_PM_ABE_MCBSP2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0050)
- + #define OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET		0x0054
- + #define OMAP4430_RM_ABE_MCBSP2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0054)
- + #define OMAP4_PM_ABE_MCBSP3_WKDEP_OFFSET		0x0058
- + #define OMAP4430_PM_ABE_MCBSP3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0058)
- + #define OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET		0x005c
- + #define OMAP4430_RM_ABE_MCBSP3_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x005c)
- + #define OMAP4_PM_ABE_SLIMBUS_WKDEP_OFFSET		0x0060
- + #define OMAP4430_PM_ABE_SLIMBUS_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0060)
- + #define OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET		0x0064
- + #define OMAP4430_RM_ABE_SLIMBUS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0064)
- + #define OMAP4_PM_ABE_TIMER5_WKDEP_OFFSET		0x0068
- + #define OMAP4430_PM_ABE_TIMER5_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0068)
- + #define OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET		0x006c
- + #define OMAP4430_RM_ABE_TIMER5_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x006c)
- + #define OMAP4_PM_ABE_TIMER6_WKDEP_OFFSET		0x0070
- + #define OMAP4430_PM_ABE_TIMER6_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0070)
- + #define OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET		0x0074
- + #define OMAP4430_RM_ABE_TIMER6_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0074)
- + #define OMAP4_PM_ABE_TIMER7_WKDEP_OFFSET		0x0078
- + #define OMAP4430_PM_ABE_TIMER7_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0078)
- + #define OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET		0x007c
- + #define OMAP4430_RM_ABE_TIMER7_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x007c)
- + #define OMAP4_PM_ABE_TIMER8_WKDEP_OFFSET		0x0080
- + #define OMAP4430_PM_ABE_TIMER8_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0080)
- + #define OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET		0x0084
- + #define OMAP4430_RM_ABE_TIMER8_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0084)
- + #define OMAP4_PM_ABE_WDT3_WKDEP_OFFSET			0x0088
- + #define OMAP4430_PM_ABE_WDT3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0088)
- + #define OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET		0x008c
- + #define OMAP4430_RM_ABE_WDT3_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x008c)
- + 
- + /* PRM.ALWAYS_ON_PRM register offsets */
- + #define OMAP4_RM_ALWON_MDMINTC_CONTEXT_OFFSET		0x0024
- + #define OMAP4430_RM_ALWON_MDMINTC_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0024)
- + #define OMAP4_PM_ALWON_SR_MPU_WKDEP_OFFSET		0x0028
- + #define OMAP4430_PM_ALWON_SR_MPU_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0028)
- + #define OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET		0x002c
- + #define OMAP4430_RM_ALWON_SR_MPU_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x002c)
- + #define OMAP4_PM_ALWON_SR_IVA_WKDEP_OFFSET		0x0030
- + #define OMAP4430_PM_ALWON_SR_IVA_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0030)
- + #define OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET		0x0034
- + #define OMAP4430_RM_ALWON_SR_IVA_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0034)
- + #define OMAP4_PM_ALWON_SR_CORE_WKDEP_OFFSET		0x0038
- + #define OMAP4430_PM_ALWON_SR_CORE_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0038)
- + #define OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET		0x003c
- + #define OMAP4430_RM_ALWON_SR_CORE_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x003c)
- + 
- + /* PRM.CORE_PRM register offsets */
- + #define OMAP4_PM_CORE_PWRSTCTRL_OFFSET			0x0000
- + #define OMAP4430_PM_CORE_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0000)
- + #define OMAP4_PM_CORE_PWRSTST_OFFSET			0x0004
- + #define OMAP4430_PM_CORE_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0004)
- + #define OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET		0x0024
- + #define OMAP4430_RM_L3_1_L3_1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0024)
- + #define OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET		0x0124
- + #define OMAP4430_RM_L3_2_L3_2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0124)
- + #define OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET		0x012c
- + #define OMAP4430_RM_L3_2_GPMC_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x012c)
- + #define OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET		0x0134
- + #define OMAP4430_RM_L3_2_OCMC_RAM_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0134)
- + #define OMAP4_RM_DUCATI_RSTCTRL_OFFSET			0x0210
- + #define OMAP4430_RM_DUCATI_RSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0210)
- + #define OMAP4_RM_DUCATI_RSTST_OFFSET			0x0214
- + #define OMAP4430_RM_DUCATI_RSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0214)
- + #define OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET		0x0224
- + #define OMAP4430_RM_DUCATI_DUCATI_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0224)
- + #define OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET		0x0324
- + #define OMAP4430_RM_SDMA_SDMA_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0324)
- + #define OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET		0x0424
- + #define OMAP4430_RM_MEMIF_DMM_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0424)
- + #define OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET		0x042c
- + #define OMAP4430_RM_MEMIF_EMIF_FW_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x042c)
- + #define OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET		0x0434
- + #define OMAP4430_RM_MEMIF_EMIF_1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0434)
- + #define OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET		0x043c
- + #define OMAP4430_RM_MEMIF_EMIF_2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x043c)
- + #define OMAP4_RM_MEMIF_DLL_CONTEXT_OFFSET		0x0444
- + #define OMAP4430_RM_MEMIF_DLL_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0444)
- + #define OMAP4_RM_MEMIF_EMIF_H1_CONTEXT_OFFSET		0x0454
- + #define OMAP4430_RM_MEMIF_EMIF_H1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0454)
- + #define OMAP4_RM_MEMIF_EMIF_H2_CONTEXT_OFFSET		0x045c
- + #define OMAP4430_RM_MEMIF_EMIF_H2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x045c)
- + #define OMAP4_RM_MEMIF_DLL_H_CONTEXT_OFFSET		0x0464
- + #define OMAP4430_RM_MEMIF_DLL_H_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0464)
- + #define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET		0x0524
- + #define OMAP4430_RM_D2D_SAD2D_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0524)
- + #define OMAP4_RM_D2D_MODEM_ICR_CONTEXT_OFFSET		0x052c
- + #define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x052c)
- + #define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET		0x0534
- + #define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0534)
- + #define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET		0x0624
- + #define OMAP4430_RM_L4CFG_L4_CFG_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0624)
- + #define OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET		0x062c
- + #define OMAP4430_RM_L4CFG_HW_SEM_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x062c)
- + #define OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET		0x0634
- + #define OMAP4430_RM_L4CFG_MAILBOX_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0634)
- + #define OMAP4_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET		0x063c
- + #define OMAP4430_RM_L4CFG_SAR_ROM_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x063c)
- + #define OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET		0x0724
- + #define OMAP4430_RM_L3INSTR_L3_3_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0724)
- + #define OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET	0x072c
- + #define OMAP4430_RM_L3INSTR_L3_INSTR_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x072c)
- + #define OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET		0x0744
- + #define OMAP4430_RM_L3INSTR_OCP_WP1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0744)
- + 
- + /* PRM.IVAHD_PRM register offsets */
- + #define OMAP4_PM_IVAHD_PWRSTCTRL_OFFSET			0x0000
- + #define OMAP4430_PM_IVAHD_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0000)
- + #define OMAP4_PM_IVAHD_PWRSTST_OFFSET			0x0004
- + #define OMAP4430_PM_IVAHD_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0004)
- + #define OMAP4_RM_IVAHD_RSTCTRL_OFFSET			0x0010
- + #define OMAP4430_RM_IVAHD_RSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0010)
- + #define OMAP4_RM_IVAHD_RSTST_OFFSET			0x0014
- + #define OMAP4430_RM_IVAHD_RSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0014)
- + #define OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET		0x0024
- + #define OMAP4430_RM_IVAHD_IVAHD_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0024)
- + #define OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET		0x002c
- + #define OMAP4430_RM_IVAHD_SL2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x002c)
- + 
- + /* PRM.CAM_PRM register offsets */
- + #define OMAP4_PM_CAM_PWRSTCTRL_OFFSET			0x0000
- + #define OMAP4430_PM_CAM_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0000)
- + #define OMAP4_PM_CAM_PWRSTST_OFFSET			0x0004
- + #define OMAP4430_PM_CAM_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0004)
- + #define OMAP4_RM_CAM_ISS_CONTEXT_OFFSET			0x0024
- + #define OMAP4430_RM_CAM_ISS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0024)
- + #define OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET		0x002c
- + #define OMAP4430_RM_CAM_FDIF_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x002c)
- + 
- + /* PRM.DSS_PRM register offsets */
- + #define OMAP4_PM_DSS_PWRSTCTRL_OFFSET			0x0000
- + #define OMAP4430_PM_DSS_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0000)
- + #define OMAP4_PM_DSS_PWRSTST_OFFSET			0x0004
- + #define OMAP4430_PM_DSS_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0004)
- + #define OMAP4_PM_DSS_DSS_WKDEP_OFFSET			0x0020
- + #define OMAP4430_PM_DSS_DSS_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0020)
- + #define OMAP4_RM_DSS_DSS_CONTEXT_OFFSET			0x0024
- + #define OMAP4430_RM_DSS_DSS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0024)
- + #define OMAP4_RM_DSS_DEISS_CONTEXT_OFFSET		0x002c
- + #define OMAP4430_RM_DSS_DEISS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x002c)
- + 
- + /* PRM.GFX_PRM register offsets */
- + #define OMAP4_PM_GFX_PWRSTCTRL_OFFSET			0x0000
- + #define OMAP4430_PM_GFX_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0000)
- + #define OMAP4_PM_GFX_PWRSTST_OFFSET			0x0004
- + #define OMAP4430_PM_GFX_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0004)
- + #define OMAP4_RM_GFX_GFX_CONTEXT_OFFSET			0x0024
- + #define OMAP4430_RM_GFX_GFX_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0024)
- + 
- + /* PRM.L3INIT_PRM register offsets */
- + #define OMAP4_PM_L3INIT_PWRSTCTRL_OFFSET		0x0000
- + #define OMAP4430_PM_L3INIT_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0000)
- + #define OMAP4_PM_L3INIT_PWRSTST_OFFSET			0x0004
- + #define OMAP4430_PM_L3INIT_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0004)
- + #define OMAP4_PM_L3INIT_MMC1_WKDEP_OFFSET		0x0028
- + #define OMAP4430_PM_L3INIT_MMC1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0028)
- + #define OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET		0x002c
- + #define OMAP4430_RM_L3INIT_MMC1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x002c)
- + #define OMAP4_PM_L3INIT_MMC2_WKDEP_OFFSET		0x0030
- + #define OMAP4430_PM_L3INIT_MMC2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0030)
- + #define OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET		0x0034
- + #define OMAP4430_RM_L3INIT_MMC2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0034)
- + #define OMAP4_PM_L3INIT_HSI_WKDEP_OFFSET		0x0038
- + #define OMAP4430_PM_L3INIT_HSI_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0038)
- + #define OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET		0x003c
- + #define OMAP4430_RM_L3INIT_HSI_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x003c)
- + #define OMAP4_PM_L3INIT_UNIPRO1_WKDEP_OFFSET		0x0040
- + #define OMAP4430_PM_L3INIT_UNIPRO1_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0040)
- + #define OMAP4_RM_L3INIT_UNIPRO1_CONTEXT_OFFSET		0x0044
- + #define OMAP4430_RM_L3INIT_UNIPRO1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0044)
- + #define OMAP4_PM_L3INIT_USB_HOST_WKDEP_OFFSET		0x0058
- + #define OMAP4430_PM_L3INIT_USB_HOST_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0058)
- + #define OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET		0x005c
- + #define OMAP4430_RM_L3INIT_USB_HOST_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x005c)
- + #define OMAP4_PM_L3INIT_USB_OTG_WKDEP_OFFSET		0x0060
- + #define OMAP4430_PM_L3INIT_USB_OTG_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0060)
- + #define OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET		0x0064
- + #define OMAP4430_RM_L3INIT_USB_OTG_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0064)
- + #define OMAP4_PM_L3INIT_USB_TLL_WKDEP_OFFSET		0x0068
- + #define OMAP4430_PM_L3INIT_USB_TLL_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0068)
- + #define OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET		0x006c
- + #define OMAP4430_RM_L3INIT_USB_TLL_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x006c)
- + #define OMAP4_RM_L3INIT_P1500_CONTEXT_OFFSET		0x007c
- + #define OMAP4430_RM_L3INIT_P1500_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x007c)
- + #define OMAP4_RM_L3INIT_EMAC_CONTEXT_OFFSET		0x0084
- + #define OMAP4430_RM_L3INIT_EMAC_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0084)
- + #define OMAP4_PM_L3INIT_SATA_WKDEP_OFFSET		0x0088
- + #define OMAP4430_PM_L3INIT_SATA_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0088)
- + #define OMAP4_RM_L3INIT_SATA_CONTEXT_OFFSET		0x008c
- + #define OMAP4430_RM_L3INIT_SATA_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x008c)
- + #define OMAP4_RM_L3INIT_TPPSS_CONTEXT_OFFSET		0x0094
- + #define OMAP4430_RM_L3INIT_TPPSS_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0094)
- + #define OMAP4_PM_L3INIT_PCIESS_WKDEP_OFFSET		0x0098
- + #define OMAP4430_PM_L3INIT_PCIESS_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0098)
- + #define OMAP4_RM_L3INIT_PCIESS_CONTEXT_OFFSET		0x009c
- + #define OMAP4430_RM_L3INIT_PCIESS_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x009c)
- + #define OMAP4_RM_L3INIT_CCPTX_CONTEXT_OFFSET		0x00ac
- + #define OMAP4430_RM_L3INIT_CCPTX_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00ac)
- + #define OMAP4_PM_L3INIT_XHPI_WKDEP_OFFSET		0x00c0
- + #define OMAP4430_PM_L3INIT_XHPI_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c0)
- + #define OMAP4_RM_L3INIT_XHPI_CONTEXT_OFFSET		0x00c4
- + #define OMAP4430_RM_L3INIT_XHPI_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c4)
- + #define OMAP4_PM_L3INIT_MMC6_WKDEP_OFFSET		0x00c8
- + #define OMAP4430_PM_L3INIT_MMC6_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c8)
- + #define OMAP4_RM_L3INIT_MMC6_CONTEXT_OFFSET		0x00cc
- + #define OMAP4430_RM_L3INIT_MMC6_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00cc)
- + #define OMAP4_PM_L3INIT_USB_HOST_FS_WKDEP_OFFSET	0x00d0
- + #define OMAP4430_PM_L3INIT_USB_HOST_FS_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00d0)
- + #define OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET	0x00d4
- + #define OMAP4430_RM_L3INIT_USB_HOST_FS_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00d4)
- + #define OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET	0x00e4
- + #define OMAP4430_RM_L3INIT_USBPHYOCP2SCP_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00e4)
- + 
- + /* PRM.L4PER_PRM register offsets */
- + #define OMAP4_PM_L4PER_PWRSTCTRL_OFFSET			0x0000
- + #define OMAP4430_PM_L4PER_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0000)
- + #define OMAP4_PM_L4PER_PWRSTST_OFFSET			0x0004
- + #define OMAP4430_PM_L4PER_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0004)
- + #define OMAP4_RM_L4PER_ADC_CONTEXT_OFFSET		0x0024
- + #define OMAP4430_RM_L4PER_ADC_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0024)
- + #define OMAP4_PM_L4PER_DMTIMER10_WKDEP_OFFSET		0x0028
- + #define OMAP4430_PM_L4PER_DMTIMER10_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0028)
- + #define OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET		0x002c
- + #define OMAP4430_RM_L4PER_DMTIMER10_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x002c)
- + #define OMAP4_PM_L4PER_DMTIMER11_WKDEP_OFFSET		0x0030
- + #define OMAP4430_PM_L4PER_DMTIMER11_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0030)
- + #define OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET		0x0034
- + #define OMAP4430_RM_L4PER_DMTIMER11_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0034)
- + #define OMAP4_PM_L4PER_DMTIMER2_WKDEP_OFFSET		0x0038
- + #define OMAP4430_PM_L4PER_DMTIMER2_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0038)
- + #define OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET		0x003c
- + #define OMAP4430_RM_L4PER_DMTIMER2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x003c)
- + #define OMAP4_PM_L4PER_DMTIMER3_WKDEP_OFFSET		0x0040
- + #define OMAP4430_PM_L4PER_DMTIMER3_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0040)
- + #define OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET		0x0044
- + #define OMAP4430_RM_L4PER_DMTIMER3_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0044)
- + #define OMAP4_PM_L4PER_DMTIMER4_WKDEP_OFFSET		0x0048
- + #define OMAP4430_PM_L4PER_DMTIMER4_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0048)
- + #define OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET		0x004c
- + #define OMAP4430_RM_L4PER_DMTIMER4_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x004c)
- + #define OMAP4_PM_L4PER_DMTIMER9_WKDEP_OFFSET		0x0050
- + #define OMAP4430_PM_L4PER_DMTIMER9_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0050)
- + #define OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET		0x0054
- + #define OMAP4430_RM_L4PER_DMTIMER9_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0054)
- + #define OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET		0x005c
- + #define OMAP4430_RM_L4PER_ELM_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x005c)
- + #define OMAP4_PM_L4PER_GPIO2_WKDEP_OFFSET		0x0060
- + #define OMAP4430_PM_L4PER_GPIO2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0060)
- + #define OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET		0x0064
- + #define OMAP4430_RM_L4PER_GPIO2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0064)
- + #define OMAP4_PM_L4PER_GPIO3_WKDEP_OFFSET		0x0068
- + #define OMAP4430_PM_L4PER_GPIO3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0068)
- + #define OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET		0x006c
- + #define OMAP4430_RM_L4PER_GPIO3_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x006c)
- + #define OMAP4_PM_L4PER_GPIO4_WKDEP_OFFSET		0x0070
- + #define OMAP4430_PM_L4PER_GPIO4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0070)
- + #define OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET		0x0074
- + #define OMAP4430_RM_L4PER_GPIO4_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0074)
- + #define OMAP4_PM_L4PER_GPIO5_WKDEP_OFFSET		0x0078
- + #define OMAP4430_PM_L4PER_GPIO5_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0078)
- + #define OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET		0x007c
- + #define OMAP4430_RM_L4PER_GPIO5_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x007c)
- + #define OMAP4_PM_L4PER_GPIO6_WKDEP_OFFSET		0x0080
- + #define OMAP4430_PM_L4PER_GPIO6_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0080)
- + #define OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET		0x0084
- + #define OMAP4430_RM_L4PER_GPIO6_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0084)
- + #define OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET		0x008c
- + #define OMAP4430_RM_L4PER_HDQ1W_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x008c)
- + #define OMAP4_PM_L4PER_HECC1_WKDEP_OFFSET		0x0090
- + #define OMAP4430_PM_L4PER_HECC1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0090)
- + #define OMAP4_RM_L4PER_HECC1_CONTEXT_OFFSET		0x0094
- + #define OMAP4430_RM_L4PER_HECC1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0094)
- + #define OMAP4_PM_L4PER_HECC2_WKDEP_OFFSET		0x0098
- + #define OMAP4430_PM_L4PER_HECC2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0098)
- + #define OMAP4_RM_L4PER_HECC2_CONTEXT_OFFSET		0x009c
- + #define OMAP4430_RM_L4PER_HECC2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x009c)
- + #define OMAP4_PM_L4PER_I2C1_WKDEP_OFFSET		0x00a0
- + #define OMAP4430_PM_L4PER_I2C1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a0)
- + #define OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET		0x00a4
- + #define OMAP4430_RM_L4PER_I2C1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a4)
- + #define OMAP4_PM_L4PER_I2C2_WKDEP_OFFSET		0x00a8
- + #define OMAP4430_PM_L4PER_I2C2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a8)
- + #define OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET		0x00ac
- + #define OMAP4430_RM_L4PER_I2C2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00ac)
- + #define OMAP4_PM_L4PER_I2C3_WKDEP_OFFSET		0x00b0
- + #define OMAP4430_PM_L4PER_I2C3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b0)
- + #define OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET		0x00b4
- + #define OMAP4430_RM_L4PER_I2C3_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b4)
- + #define OMAP4_PM_L4PER_I2C4_WKDEP_OFFSET		0x00b8
- + #define OMAP4430_PM_L4PER_I2C4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b8)
- + #define OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET		0x00bc
- + #define OMAP4430_RM_L4PER_I2C4_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00bc)
- + #define OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET		0x00c0
- + #define OMAP4430_RM_L4PER_L4_PER_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00c0)
- + #define OMAP4_PM_L4PER_MCASP2_WKDEP_OFFSET		0x00d0
- + #define OMAP4430_PM_L4PER_MCASP2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d0)
- + #define OMAP4_RM_L4PER_MCASP2_CONTEXT_OFFSET		0x00d4
- + #define OMAP4430_RM_L4PER_MCASP2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d4)
- + #define OMAP4_PM_L4PER_MCASP3_WKDEP_OFFSET		0x00d8
- + #define OMAP4430_PM_L4PER_MCASP3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d8)
- + #define OMAP4_RM_L4PER_MCASP3_CONTEXT_OFFSET		0x00dc
- + #define OMAP4430_RM_L4PER_MCASP3_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00dc)
- + #define OMAP4_PM_L4PER_MCBSP4_WKDEP_OFFSET		0x00e0
- + #define OMAP4430_PM_L4PER_MCBSP4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00e0)
- + #define OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET		0x00e4
- + #define OMAP4430_RM_L4PER_MCBSP4_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00e4)
- + #define OMAP4_RM_L4PER_MGATE_CONTEXT_OFFSET		0x00ec
- + #define OMAP4430_RM_L4PER_MGATE_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00ec)
- + #define OMAP4_PM_L4PER_MCSPI1_WKDEP_OFFSET		0x00f0
- + #define OMAP4430_PM_L4PER_MCSPI1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f0)
- + #define OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET		0x00f4
- + #define OMAP4430_RM_L4PER_MCSPI1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f4)
- + #define OMAP4_PM_L4PER_MCSPI2_WKDEP_OFFSET		0x00f8
- + #define OMAP4430_PM_L4PER_MCSPI2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f8)
- + #define OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET		0x00fc
- + #define OMAP4430_RM_L4PER_MCSPI2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00fc)
- + #define OMAP4_PM_L4PER_MCSPI3_WKDEP_OFFSET		0x0100
- + #define OMAP4430_PM_L4PER_MCSPI3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0100)
- + #define OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET		0x0104
- + #define OMAP4430_RM_L4PER_MCSPI3_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0104)
- + #define OMAP4_PM_L4PER_MCSPI4_WKDEP_OFFSET		0x0108
- + #define OMAP4430_PM_L4PER_MCSPI4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0108)
- + #define OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET		0x010c
- + #define OMAP4430_RM_L4PER_MCSPI4_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x010c)
- + #define OMAP4_PM_L4PER_MMCSD3_WKDEP_OFFSET		0x0120
- + #define OMAP4430_PM_L4PER_MMCSD3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0120)
- + #define OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET		0x0124
- + #define OMAP4430_RM_L4PER_MMCSD3_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0124)
- + #define OMAP4_PM_L4PER_MMCSD4_WKDEP_OFFSET		0x0128
- + #define OMAP4430_PM_L4PER_MMCSD4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0128)
- + #define OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET		0x012c
- + #define OMAP4430_RM_L4PER_MMCSD4_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x012c)
- + #define OMAP4_RM_L4PER_MSPROHG_CONTEXT_OFFSET		0x0134
- + #define OMAP4430_RM_L4PER_MSPROHG_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0134)
- + #define OMAP4_PM_L4PER_SLIMBUS2_WKDEP_OFFSET		0x0138
- + #define OMAP4430_PM_L4PER_SLIMBUS2_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0138)
- + #define OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET		0x013c
- + #define OMAP4430_RM_L4PER_SLIMBUS2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x013c)
- + #define OMAP4_PM_L4PER_UART1_WKDEP_OFFSET		0x0140
- + #define OMAP4430_PM_L4PER_UART1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0140)
- + #define OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET		0x0144
- + #define OMAP4430_RM_L4PER_UART1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0144)
- + #define OMAP4_PM_L4PER_UART2_WKDEP_OFFSET		0x0148
- + #define OMAP4430_PM_L4PER_UART2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0148)
- + #define OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET		0x014c
- + #define OMAP4430_RM_L4PER_UART2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x014c)
- + #define OMAP4_PM_L4PER_UART3_WKDEP_OFFSET		0x0150
- + #define OMAP4430_PM_L4PER_UART3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0150)
- + #define OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET		0x0154
- + #define OMAP4430_RM_L4PER_UART3_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0154)
- + #define OMAP4_PM_L4PER_UART4_WKDEP_OFFSET		0x0158
- + #define OMAP4430_PM_L4PER_UART4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0158)
- + #define OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET		0x015c
- + #define OMAP4430_RM_L4PER_UART4_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x015c)
- + #define OMAP4_PM_L4PER_MMCSD5_WKDEP_OFFSET		0x0160
- + #define OMAP4430_PM_L4PER_MMCSD5_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0160)
- + #define OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET		0x0164
- + #define OMAP4430_RM_L4PER_MMCSD5_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0164)
- + #define OMAP4_PM_L4PER_I2C5_WKDEP_OFFSET		0x0168
- + #define OMAP4430_PM_L4PER_I2C5_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0168)
- + #define OMAP4_RM_L4PER_I2C5_CONTEXT_OFFSET		0x016c
- + #define OMAP4430_RM_L4PER_I2C5_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x016c)
- + #define OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET		0x01a4
- + #define OMAP4430_RM_L4SEC_AES1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01a4)
- + #define OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET		0x01ac
- + #define OMAP4430_RM_L4SEC_AES2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01ac)
- + #define OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET		0x01b4
- + #define OMAP4430_RM_L4SEC_DES3DES_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01b4)
- + #define OMAP4_RM_L4SEC_PKAEIP29_CONTEXT_OFFSET		0x01bc
- + #define OMAP4430_RM_L4SEC_PKAEIP29_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01bc)
- + #define OMAP4_RM_L4SEC_RNG_CONTEXT_OFFSET		0x01c4
- + #define OMAP4430_RM_L4SEC_RNG_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01c4)
- + #define OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET		0x01cc
- + #define OMAP4430_RM_L4SEC_SHA2MD51_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01cc)
- + #define OMAP4_RM_L4SEC_CRYPTODMA_CONTEXT_OFFSET		0x01dc
- + #define OMAP4430_RM_L4SEC_CRYPTODMA_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01dc)
- + 
- + /* PRM.CEFUSE_PRM register offsets */
- + #define OMAP4_PM_CEFUSE_PWRSTCTRL_OFFSET		0x0000
- + #define OMAP4430_PM_CEFUSE_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0000)
- + #define OMAP4_PM_CEFUSE_PWRSTST_OFFSET			0x0004
- + #define OMAP4430_PM_CEFUSE_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0004)
- + #define OMAP4_RM_CEFUSE_CEFUSE_CONTEXT_OFFSET		0x0024
- + #define OMAP4430_RM_CEFUSE_CEFUSE_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0024)
- + 
- + /* PRM.WKUP_PRM register offsets */
- + #define OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET		0x0024
- + #define OMAP4430_RM_WKUP_L4WKUP_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0024)
- + #define OMAP4_RM_WKUP_WDT1_CONTEXT_OFFSET		0x002c
- + #define OMAP4430_RM_WKUP_WDT1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x002c)
- + #define OMAP4_PM_WKUP_WDT2_WKDEP_OFFSET			0x0030
- + #define OMAP4430_PM_WKUP_WDT2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0030)
- + #define OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET		0x0034
- + #define OMAP4430_RM_WKUP_WDT2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0034)
- + #define OMAP4_PM_WKUP_GPIO1_WKDEP_OFFSET		0x0038
- + #define OMAP4430_PM_WKUP_GPIO1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0038)
- + #define OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET		0x003c
- + #define OMAP4430_RM_WKUP_GPIO1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x003c)
- + #define OMAP4_PM_WKUP_TIMER1_WKDEP_OFFSET		0x0040
- + #define OMAP4430_PM_WKUP_TIMER1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0040)
- + #define OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET		0x0044
- + #define OMAP4430_RM_WKUP_TIMER1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0044)
- + #define OMAP4_PM_WKUP_TIMER12_WKDEP_OFFSET		0x0048
- + #define OMAP4430_PM_WKUP_TIMER12_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0048)
- + #define OMAP4_RM_WKUP_TIMER12_CONTEXT_OFFSET		0x004c
- + #define OMAP4430_RM_WKUP_TIMER12_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x004c)
- + #define OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET		0x0054
- + #define OMAP4430_RM_WKUP_SYNCTIMER_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0054)
- + #define OMAP4_PM_WKUP_USIM_WKDEP_OFFSET			0x0058
- + #define OMAP4430_PM_WKUP_USIM_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0058)
- + #define OMAP4_RM_WKUP_USIM_CONTEXT_OFFSET		0x005c
- + #define OMAP4430_RM_WKUP_USIM_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x005c)
- + #define OMAP4_RM_WKUP_SARRAM_CONTEXT_OFFSET		0x0064
- + #define OMAP4430_RM_WKUP_SARRAM_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0064)
- + #define OMAP4_PM_WKUP_KEYBOARD_WKDEP_OFFSET		0x0078
- + #define OMAP4430_PM_WKUP_KEYBOARD_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0078)
- + #define OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET		0x007c
- + #define OMAP4430_RM_WKUP_KEYBOARD_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x007c)
- + #define OMAP4_PM_WKUP_RTC_WKDEP_OFFSET			0x0080
- + #define OMAP4430_PM_WKUP_RTC_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0080)
- + #define OMAP4_RM_WKUP_RTC_CONTEXT_OFFSET		0x0084
- + #define OMAP4430_RM_WKUP_RTC_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0084)
- + 
- + /* PRM.WKUP_CM register offsets */
- + #define OMAP4_CM_WKUP_CLKSTCTRL_OFFSET			0x0000
- + #define OMAP4430_CM_WKUP_CLKSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0000)
- + #define OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET		0x0020
- + #define OMAP4430_CM_WKUP_L4WKUP_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0020)
- + #define OMAP4_CM_WKUP_WDT1_CLKCTRL_OFFSET		0x0028
- + #define OMAP4430_CM_WKUP_WDT1_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0028)
- + #define OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET		0x0030
- + #define OMAP4430_CM_WKUP_WDT2_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0030)
- + #define OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET		0x0038
- + #define OMAP4430_CM_WKUP_GPIO1_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0038)
- + #define OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET		0x0040
- + #define OMAP4430_CM_WKUP_TIMER1_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0040)
- + #define OMAP4_CM_WKUP_TIMER12_CLKCTRL_OFFSET		0x0048
- + #define OMAP4430_CM_WKUP_TIMER12_CLKCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0048)
- + #define OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET		0x0050
- + #define OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0050)
- + #define OMAP4_CM_WKUP_USIM_CLKCTRL_OFFSET		0x0058
- + #define OMAP4430_CM_WKUP_USIM_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0058)
- + #define OMAP4_CM_WKUP_SARRAM_CLKCTRL_OFFSET		0x0060
- + #define OMAP4430_CM_WKUP_SARRAM_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0060)
- + #define OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET		0x0078
- + #define OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0078)
- + #define OMAP4_CM_WKUP_RTC_CLKCTRL_OFFSET		0x0080
- + #define OMAP4430_CM_WKUP_RTC_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0080)
- + #define OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET		0x0088
- + #define OMAP4430_CM_WKUP_BANDGAP_CLKCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0088)
- + 
- + /* PRM.EMU_PRM register offsets */
- + #define OMAP4_PM_EMU_PWRSTCTRL_OFFSET			0x0000
- + #define OMAP4430_PM_EMU_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0000)
- + #define OMAP4_PM_EMU_PWRSTST_OFFSET			0x0004
- + #define OMAP4430_PM_EMU_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0004)
- + #define OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET		0x0024
- + #define OMAP4430_RM_EMU_DEBUGSS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0024)
- + 
- + /* PRM.EMU_CM register offsets */
- + #define OMAP4_CM_EMU_CLKSTCTRL_OFFSET			0x0000
- + #define OMAP4430_CM_EMU_CLKSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0000)
- + #define OMAP4_CM_EMU_DYNAMICDEP_OFFSET			0x0008
- + #define OMAP4430_CM_EMU_DYNAMICDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0008)
- + #define OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET		0x0020
- + #define OMAP4430_CM_EMU_DEBUGSS_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0020)
- + 
- + /* PRM.DEVICE_PRM register offsets */
- + #define OMAP4_PRM_RSTCTRL_OFFSET			0x0000
- + #define OMAP4430_PRM_RSTCTRL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0000)
- + #define OMAP4_PRM_RSTST_OFFSET				0x0004
- + #define OMAP4430_PRM_RSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0004)
- + #define OMAP4_PRM_RSTTIME_OFFSET			0x0008
- + #define OMAP4430_PRM_RSTTIME				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0008)
- + #define OMAP4_PRM_CLKREQCTRL_OFFSET			0x000c
- + #define OMAP4430_PRM_CLKREQCTRL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x000c)
- + #define OMAP4_PRM_VOLTCTRL_OFFSET			0x0010
- + #define OMAP4430_PRM_VOLTCTRL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0010)
- + #define OMAP4_PRM_PWRREQCTRL_OFFSET			0x0014
- + #define OMAP4430_PRM_PWRREQCTRL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0014)
- + #define OMAP4_PRM_PSCON_COUNT_OFFSET			0x0018
- + #define OMAP4430_PRM_PSCON_COUNT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0018)
- + #define OMAP4_PRM_IO_COUNT_OFFSET			0x001c
- + #define OMAP4430_PRM_IO_COUNT				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x001c)
- + #define OMAP4_PRM_IO_PMCTRL_OFFSET			0x0020
- + #define OMAP4430_PRM_IO_PMCTRL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0020)
- + #define OMAP4_PRM_VOLTSETUP_WARMRESET_OFFSET		0x0024
- + #define OMAP4430_PRM_VOLTSETUP_WARMRESET		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0024)
- + #define OMAP4_PRM_VOLTSETUP_CORE_OFF_OFFSET		0x0028
- + #define OMAP4430_PRM_VOLTSETUP_CORE_OFF			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0028)
- + #define OMAP4_PRM_VOLTSETUP_MPU_OFF_OFFSET		0x002c
- + #define OMAP4430_PRM_VOLTSETUP_MPU_OFF			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x002c)
- + #define OMAP4_PRM_VOLTSETUP_IVA_OFF_OFFSET		0x0030
- + #define OMAP4430_PRM_VOLTSETUP_IVA_OFF			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0030)
- + #define OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET	0x0034
- + #define OMAP4430_PRM_VOLTSETUP_CORE_RET_SLEEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0034)
- + #define OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET	0x0038
- + #define OMAP4430_PRM_VOLTSETUP_MPU_RET_SLEEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0038)
- + #define OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET	0x003c
- + #define OMAP4430_PRM_VOLTSETUP_IVA_RET_SLEEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x003c)
- + #define OMAP4_PRM_VP_CORE_CONFIG_OFFSET			0x0040
- + #define OMAP4430_PRM_VP_CORE_CONFIG			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0040)
- + #define OMAP4_PRM_VP_CORE_STATUS_OFFSET			0x0044
- + #define OMAP4430_PRM_VP_CORE_STATUS			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0044)
- + #define OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET		0x0048
- + #define OMAP4430_PRM_VP_CORE_VLIMITTO			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0048)
- + #define OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET		0x004c
- + #define OMAP4430_PRM_VP_CORE_VOLTAGE			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x004c)
- + #define OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET		0x0050
- + #define OMAP4430_PRM_VP_CORE_VSTEPMAX			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0050)
- + #define OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET		0x0054
- + #define OMAP4430_PRM_VP_CORE_VSTEPMIN			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0054)
- + #define OMAP4_PRM_VP_MPU_CONFIG_OFFSET			0x0058
- + #define OMAP4430_PRM_VP_MPU_CONFIG			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0058)
- + #define OMAP4_PRM_VP_MPU_STATUS_OFFSET			0x005c
- + #define OMAP4430_PRM_VP_MPU_STATUS			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x005c)
- + #define OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET		0x0060
- + #define OMAP4430_PRM_VP_MPU_VLIMITTO			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0060)
- + #define OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET			0x0064
- + #define OMAP4430_PRM_VP_MPU_VOLTAGE			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0064)
- + #define OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET		0x0068
- + #define OMAP4430_PRM_VP_MPU_VSTEPMAX			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0068)
- + #define OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET		0x006c
- + #define OMAP4430_PRM_VP_MPU_VSTEPMIN			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x006c)
- + #define OMAP4_PRM_VP_IVA_CONFIG_OFFSET			0x0070
- + #define OMAP4430_PRM_VP_IVA_CONFIG			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0070)
- + #define OMAP4_PRM_VP_IVA_STATUS_OFFSET			0x0074
- + #define OMAP4430_PRM_VP_IVA_STATUS			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0074)
- + #define OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET		0x0078
- + #define OMAP4430_PRM_VP_IVA_VLIMITTO			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0078)
- + #define OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET			0x007c
- + #define OMAP4430_PRM_VP_IVA_VOLTAGE			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x007c)
- + #define OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET		0x0080
- + #define OMAP4430_PRM_VP_IVA_VSTEPMAX			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0080)
- + #define OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET		0x0084
- + #define OMAP4430_PRM_VP_IVA_VSTEPMIN			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0084)
- + #define OMAP4_PRM_VC_SMPS_SA_OFFSET			0x0088
- + #define OMAP4430_PRM_VC_SMPS_SA				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0088)
- + #define OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET		0x008c
- + #define OMAP4430_PRM_VC_VAL_SMPS_RA_VOL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x008c)
- + #define OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET		0x0090
- + #define OMAP4430_PRM_VC_VAL_SMPS_RA_CMD			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0090)
- + #define OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET		0x0094
- + #define OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0094)
- + #define OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET		0x0098
- + #define OMAP4430_PRM_VC_VAL_CMD_VDD_MPU_L		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0098)
- + #define OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET		0x009c
- + #define OMAP4430_PRM_VC_VAL_CMD_VDD_IVA_L		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x009c)
- + #define OMAP4_PRM_VC_VAL_BYPASS_OFFSET			0x00a0
- + #define OMAP4430_PRM_VC_VAL_BYPASS			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a0)
- + #define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET			0x00a4
- + #define OMAP4430_PRM_VC_CFG_CHANNEL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a4)
- + #define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET		0x00a8
- + #define OMAP4430_PRM_VC_CFG_I2C_MODE			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a8)
- + #define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET			0x00ac
- + #define OMAP4430_PRM_VC_CFG_I2C_CLK			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ac)
- + #define OMAP4_PRM_SRAM_COUNT_OFFSET			0x00b0
- + #define OMAP4430_PRM_SRAM_COUNT				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b0)
- + #define OMAP4_PRM_SRAM_WKUP_SETUP_OFFSET		0x00b4
- + #define OMAP4430_PRM_SRAM_WKUP_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b4)
- + #define OMAP4_PRM_LDO_SRAM_CORE_SETUP_OFFSET		0x00b8
- + #define OMAP4430_PRM_LDO_SRAM_CORE_SETUP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b8)
- + #define OMAP4_PRM_LDO_SRAM_CORE_CTRL_OFFSET		0x00bc
- + #define OMAP4430_PRM_LDO_SRAM_CORE_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00bc)
- + #define OMAP4_PRM_LDO_SRAM_MPU_SETUP_OFFSET		0x00c0
- + #define OMAP4430_PRM_LDO_SRAM_MPU_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c0)
- + #define OMAP4_PRM_LDO_SRAM_MPU_CTRL_OFFSET		0x00c4
- + #define OMAP4430_PRM_LDO_SRAM_MPU_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c4)
- + #define OMAP4_PRM_LDO_SRAM_IVA_SETUP_OFFSET		0x00c8
- + #define OMAP4430_PRM_LDO_SRAM_IVA_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c8)
- + #define OMAP4_PRM_LDO_SRAM_IVA_CTRL_OFFSET		0x00cc
- + #define OMAP4430_PRM_LDO_SRAM_IVA_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00cc)
- + #define OMAP4_PRM_LDO_ABB_MPU_SETUP_OFFSET		0x00d0
- + #define OMAP4430_PRM_LDO_ABB_MPU_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d0)
- + #define OMAP4_PRM_LDO_ABB_MPU_CTRL_OFFSET		0x00d4
- + #define OMAP4430_PRM_LDO_ABB_MPU_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d4)
- + #define OMAP4_PRM_LDO_ABB_IVA_SETUP_OFFSET		0x00d8
- + #define OMAP4430_PRM_LDO_ABB_IVA_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d8)
- + #define OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET		0x00dc
- + #define OMAP4430_PRM_LDO_ABB_IVA_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00dc)
- + #define OMAP4_PRM_LDO_BANDGAP_SETUP_OFFSET		0x00e0
- + #define OMAP4430_PRM_LDO_BANDGAP_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e0)
- + #define OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET		0x00e4
- + #define OMAP4430_PRM_DEVICE_OFF_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e4)
- + #define OMAP4_PRM_PHASE1_CNDP_OFFSET			0x00e8
- + #define OMAP4430_PRM_PHASE1_CNDP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e8)
- + #define OMAP4_PRM_PHASE2A_CNDP_OFFSET			0x00ec
- + #define OMAP4430_PRM_PHASE2A_CNDP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ec)
- + #define OMAP4_PRM_PHASE2B_CNDP_OFFSET			0x00f0
- + #define OMAP4430_PRM_PHASE2B_CNDP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f0)
- + #define OMAP4_PRM_MODEM_IF_CTRL_OFFSET			0x00f4
- + #define OMAP4430_PRM_MODEM_IF_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f4)
- + #define OMAP4_PRM_VC_ERRST_OFFSET			0x00f8
- + #define OMAP4430_PRM_VC_ERRST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8)
- + 
- + /* Function prototypes */
- + # ifndef __ASSEMBLER__
- + 
- + extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx);
- + extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx);
- + extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
- + 
- + /* OMAP4-specific VP functions */
- + u32 omap4_prm_vp_check_txdone(u8 vp_id);
- + void omap4_prm_vp_clear_txdone(u8 vp_id);
- + 
- + /*
- +  * OMAP4 access functions for voltage controller (VC) and
- +  * voltage proccessor (VP) in the PRM.
- +  */
- + extern u32 omap4_prm_vcvp_read(u8 offset);
- + extern void omap4_prm_vcvp_write(u32 val, u8 offset);
- + extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
- + 
- + /* PRM interrupt-related functions */
- + extern void omap44xx_prm_read_pending_irqs(unsigned long *events);
- + extern void omap44xx_prm_ocp_barrier(void);
- + extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
- + extern void omap44xx_prm_restore_irqen(u32 *saved_mask);
- + 
- + # endif
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/prm.h linux-3.2.1/arch/arm/mach-ckb_3352/prm.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/prm.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/prm.h	2014-05-15 13:25:13.983443033 +0900
- ***************
- *** 0 ****
- --- 1,56 ----
- + /*
- +  * OMAP2/3/4 Power/Reset Management (PRM) bitfield definitions
- +  *
- +  * Copyright (C) 2007-2009 Texas Instruments, Inc.
- +  * Copyright (C) 2010 Nokia Corporation
- +  *
- +  * Paul Walmsley
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + #ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
- + #define __ARCH_ARM_MACH_OMAP2_PRM_H
- + 
- + #include "prcm-common.h"
- + 
- + /*
- +  * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP
- +  *
- +  * 2430: PM_PWSTST_MDM
- +  *
- +  * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
- +  *	 PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
- +  *	 PM_PWSTST_NEON
- +  */
- + #define OMAP_INTRANSITION_MASK				(1 << 20)
- + 
- + 
- + /*
- +  * 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP
- +  *
- +  * 2430: PM_PWSTST_MDM
- +  *
- +  * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
- +  *	 PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
- +  *	 PM_PWSTST_NEON
- +  */
- + #define OMAP_POWERSTATEST_SHIFT				0
- + #define OMAP_POWERSTATEST_MASK				(0x3 << 0)
- + 
- + /*
- +  * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
- +  *       PM_PWSTCTRL_DSP, PM_PWSTST_MPU
- +  *
- +  * 2430: PM_PWSTCTRL_MDM shared bits
- +  *
- +  * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE,
- +  *	 PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
- +  *	 PM_PWSTCTRL_NEON shared bits
- +  */
- + #define OMAP_POWERSTATE_SHIFT				0
- + #define OMAP_POWERSTATE_MASK				(0x3 << 0)
- + 
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/prminst33xx.h linux-3.2.1/arch/arm/mach-ckb_3352/prminst33xx.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/prminst33xx.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/prminst33xx.h	2014-05-15 13:25:13.983443033 +0900
- ***************
- *** 0 ****
- --- 1,29 ----
- + /*
- +  * AM33XX Power/Reset Management (PRM) function prototypes
- +  *
- +  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #ifndef __ARCH_ASM_MACH_OMAP2_PRMINST33XX_H
- + #define __ARCH_ASM_MACH_OMAP2_PRMINST33XX_H
- + 
- + extern u32 am33xx_prminst_read_inst_reg(s16 inst, u16 idx);
- + extern void am33xx_prminst_write_inst_reg(u32 val, s16 inst, u16 idx);
- + extern u32 am33xx_prminst_rmw_inst_reg_bits(u32 mask, u32 bits,
- + 					   s16 inst, s16 idx);
- + extern u32 am33xx_prminst_is_hardreset_asserted(s16 domain, s16 idx, u32 mask);
- + extern int am33xx_prminst_assert_hardreset(s16 prm_mod, u8 shift);
- + extern int am33xx_prminst_deassert_hardreset(s16 prm_mod, u8 rst_shift,
- + 					u8 st_shift);
- + extern void am33xx_prm_global_warm_sw_reset(void);
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/prminst44xx.c linux-3.2.1/arch/arm/mach-ckb_3352/prminst44xx.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/prminst44xx.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/prminst44xx.c	2014-05-15 13:25:13.983443033 +0900
- ***************
- *** 0 ****
- --- 1,166 ----
- + /*
- +  * OMAP4 PRM instance functions
- +  *
- +  * Copyright (C) 2009 Nokia Corporation
- +  * Copyright (C) 2011 Texas Instruments, Inc.
- +  * Paul Walmsley
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #include <linux/kernel.h>
- + #include <linux/types.h>
- + #include <linux/errno.h>
- + #include <linux/err.h>
- + #include <linux/io.h>
- + 
- + #include "common.h"
- + 
- + //#include "prm44xx.h"
- + #include "prm33xx.h"
- + #include "prminst44xx.h"
- + #include "prm-regbits-44xx.h"
- + #include "prcm44xx.h"
- + //#include "prcm_mpu44xx.h"
- + 
- + static u32 **_prm_bases;
- + static u32 max_prm_partitions;
- + 
- + static u32 *am33xx_prm_bases[] = {
- + 	[OMAP4430_INVALID_PRCM_PARTITION]	= 0,
- + 	[AM33XX_PRM_PARTITION]			= AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRM_BASE),
- + };
- + 
- + /* Read a register in a PRM instance */
- + u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
- + {
- + 	BUG_ON(part >= max_prm_partitions ||
- + 	       part == OMAP4430_INVALID_PRCM_PARTITION ||
- + 	       !_prm_bases[part]);
- + 	return __raw_readl(_prm_bases[part] + ((inst + idx)/sizeof(u32)));
- + }
- + 
- + /* Write into a register in a PRM instance */
- + void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
- + {
- + 	BUG_ON(part >= max_prm_partitions ||
- + 	       part == OMAP4430_INVALID_PRCM_PARTITION ||
- + 	       !_prm_bases[part]);
- + 	__raw_writel(val, _prm_bases[part] + ((inst + idx)/sizeof(u32)));
- + }
- + 
- + /* Read-modify-write a register in PRM. Caller must lock */
- + u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
- + 				    u16 idx)
- + {
- + 	u32 v;
- + 
- + 	v = omap4_prminst_read_inst_reg(part, inst, idx);
- + 	v &= ~mask;
- + 	v |= bits;
- + 	omap4_prminst_write_inst_reg(v, part, inst, idx);
- + 
- + 	return v;
- + }
- + 
- + /*
- +  * Address offset (in bytes) between the reset control and the reset
- +  * status registers: 4 bytes on OMAP4
- +  */
- + #define OMAP4_RST_CTRL_ST_OFFSET		4
- + 
- + /**
- +  * omap4_prminst_is_hardreset_asserted - read the HW reset line state of
- +  * submodules contained in the hwmod module
- +  * @rstctrl_reg: RM_RSTCTRL register address for this module
- +  * @shift: register bit shift corresponding to the reset line to check
- +  *
- +  * Returns 1 if the (sub)module hardreset line is currently asserted,
- +  * 0 if the (sub)module hardreset line is not currently asserted, or
- +  * -EINVAL upon parameter error.
- +  */
- + int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
- + 					u16 rstctrl_offs)
- + {
- + 	u32 v;
- + 
- + 	v = omap4_prminst_read_inst_reg(part, inst, rstctrl_offs);
- + 	v &= 1 << shift;
- + 	v >>= shift;
- + 
- + 	return v;
- + }
- + 
- + /**
- +  * omap4_prminst_assert_hardreset - assert the HW reset line of a submodule
- +  * @rstctrl_reg: RM_RSTCTRL register address for this module
- +  * @shift: register bit shift corresponding to the reset line to assert
- +  *
- +  * Some IPs like dsp, ipu or iva contain processors that require an HW
- +  * reset line to be asserted / deasserted in order to fully enable the
- +  * IP.  These modules may have multiple hard-reset lines that reset
- +  * different 'submodules' inside the IP block.  This function will
- +  * place the submodule into reset.  Returns 0 upon success or -EINVAL
- +  * upon an argument error.
- +  */
- + int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
- + 				   u16 rstctrl_offs)
- + {
- + 	u32 mask = 1 << shift;
- + 
- + 	omap4_prminst_rmw_inst_reg_bits(mask, mask, part, inst, rstctrl_offs);
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * omap4_prminst_deassert_hardreset - deassert a submodule hardreset line and
- +  * wait
- +  * @rstctrl_reg: RM_RSTCTRL register address for this module
- +  * @shift: register bit shift corresponding to the reset line to deassert
- +  * @st_shift: register bit shift corresponding to the reset line to deassert
- +  *
- +  * Some IPs like dsp, ipu or iva contain processors that require an HW
- +  * reset line to be asserted / deasserted in order to fully enable the
- +  * IP.  These modules may have multiple hard-reset lines that reset
- +  * different 'submodules' inside the IP block.  This function will
- +  * take the submodule out of reset and wait until the PRCM indicates
- +  * that the reset has completed before returning.  Returns 0 upon success or
- +  * -EINVAL upon an argument error, -EEXIST if the submodule was already out
- +  * of reset, or -EBUSY if the submodule did not exit reset promptly.
- +  */
- + int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part,
- + 				s16 inst, u16 rstctrl_offs, u16 rstst_offs)
- + {
- + 	int c;
- + 
- + 	rstst_offs = rstst_offs ? rstst_offs :
- + 			(rstctrl_offs + OMAP4_RST_CTRL_ST_OFFSET);
- + 	st_shift = st_shift ? st_shift : shift;
- + 
- + 	/* Check the current status to avoid de-asserting the line twice */
- + 	if (omap4_prminst_is_hardreset_asserted(shift, part, inst,
- + 						rstctrl_offs) == 0)
- + 		return -EEXIST;
- + 
- + 	/* Clear the reset status by writing 1 to the status bit */
- + 	omap4_prminst_rmw_inst_reg_bits(0xffffffff, (1 << st_shift), part, inst,
- + 					rstst_offs);
- + 	/* de-assert the reset control line */
- + 	omap4_prminst_rmw_inst_reg_bits((1 << shift), 0, part, inst, rstctrl_offs);
- + 	/* wait the status to be set */
- + 	omap_test_timeout(omap4_prminst_is_hardreset_asserted(st_shift,
- + 					part, inst, rstst_offs),
- + 			  MAX_MODULE_HARDRESET_WAIT, c);
- + 
- + 	return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
- + }
- + 
- + 
- + void __init omap44xx_prminst_init(void)
- + {
- + 	_prm_bases = am33xx_prm_bases;
- + 	max_prm_partitions = ARRAY_SIZE(am33xx_prm_bases);
- + }
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/prminst44xx.h linux-3.2.1/arch/arm/mach-ckb_3352/prminst44xx.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/prminst44xx.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/prminst44xx.h	2014-05-15 13:25:13.983443033 +0900
- ***************
- *** 0 ****
- --- 1,31 ----
- + /*
- +  * OMAP4 Power/Reset Management (PRM) function prototypes
- +  *
- +  * Copyright (C) 2010 Nokia Corporation
- +  * Copyright (C) 2011 Texas Instruments, Inc.
- +  * Paul Walmsley
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + #ifndef __ARCH_ASM_MACH_OMAP2_PRMINST44XX_H
- + #define __ARCH_ASM_MACH_OMAP2_PRMINST44XX_H
- + 
- + /*
- +  * In an ideal world, we would not export these low-level functions,
- +  * but this will probably take some time to fix properly
- +  */
- + extern u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx);
- + extern void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx);
- + extern u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part,
- + 					   s16 inst, u16 idx);
- + 
- + extern int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
- + 					       u16 rstctrl_offs);
- + extern int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
- + 					  u16 rstctrl_offs);
- + extern int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part,
- + 				s16 inst, u16 rstctrl_offs, u16 rstst_offs);
- + extern void __init omap44xx_prminst_init(void);
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/prm-regbits-24xx.h linux-3.2.1/arch/arm/mach-ckb_3352/prm-regbits-24xx.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/prm-regbits-24xx.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/prm-regbits-24xx.h	2014-05-15 13:25:13.988186688 +0900
- ***************
- *** 0 ****
- --- 1,283 ----
- + #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H
- + #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H
- + 
- + /*
- +  * OMAP24XX Power/Reset Management register bits
- +  *
- +  * Copyright (C) 2007 Texas Instruments, Inc.
- +  * Copyright (C) 2007 Nokia Corporation
- +  *
- +  * Written by Paul Walmsley
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #include "prm2xxx_3xxx.h"
- + 
- + /* Bits shared between registers */
- + 
- + /* PRCM_IRQSTATUS_MPU, PM_IRQSTATUS_DSP, PRCM_IRQSTATUS_IVA shared bits */
- + #define OMAP24XX_VOLTTRANS_ST_MASK			(1 << 2)
- + #define OMAP24XX_WKUP2_ST_MASK				(1 << 1)
- + #define OMAP24XX_WKUP1_ST_MASK				(1 << 0)
- + 
- + /* PRCM_IRQENABLE_MPU, PM_IRQENABLE_DSP, PRCM_IRQENABLE_IVA shared bits */
- + #define OMAP24XX_VOLTTRANS_EN_MASK			(1 << 2)
- + #define OMAP24XX_WKUP2_EN_MASK				(1 << 1)
- + #define OMAP24XX_WKUP1_EN_MASK				(1 << 0)
- + 
- + /* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */
- + #define OMAP24XX_EN_MPU_SHIFT				1
- + #define OMAP24XX_EN_MPU_MASK				(1 << 1)
- + #define OMAP24XX_EN_CORE_SHIFT 				0
- + #define OMAP24XX_EN_CORE_MASK				(1 << 0)
- + 
- + /*
- +  * PM_PWSTCTRL_MPU, PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM
- +  * shared bits
- +  */
- + #define OMAP24XX_MEMONSTATE_SHIFT			10
- + #define OMAP24XX_MEMONSTATE_MASK			(0x3 << 10)
- + #define OMAP24XX_MEMRETSTATE_MASK			(1 << 3)
- + 
- + /* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM shared bits */
- + #define OMAP24XX_FORCESTATE_MASK			(1 << 18)
- + 
- + /*
- +  * PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP,
- +  * PM_PWSTST_MDM shared bits
- +  */
- + #define OMAP24XX_CLKACTIVITY_MASK			(1 << 19)
- + 
- + /* PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_DSP shared bits */
- + #define OMAP24XX_LASTSTATEENTERED_SHIFT			4
- + #define OMAP24XX_LASTSTATEENTERED_MASK			(0x3 << 4)
- + 
- + /* PM_PWSTST_MPU and PM_PWSTST_DSP shared bits */
- + #define OMAP2430_MEMSTATEST_SHIFT			10
- + #define OMAP2430_MEMSTATEST_MASK			(0x3 << 10)
- + 
- + /* PM_PWSTST_GFX, PM_PWSTST_DSP, PM_PWSTST_MDM shared bits */
- + #define OMAP24XX_POWERSTATEST_SHIFT			0
- + #define OMAP24XX_POWERSTATEST_MASK			(0x3 << 0)
- + 
- + 
- + /* Bits specific to each register */
- + 
- + /* PRCM_REVISION */
- + #define OMAP24XX_REV_SHIFT				0
- + #define OMAP24XX_REV_MASK				(0xff << 0)
- + 
- + /* PRCM_SYSCONFIG */
- + #define OMAP24XX_AUTOIDLE_MASK				(1 << 0)
- + 
- + /* PRCM_IRQSTATUS_MPU specific bits */
- + #define OMAP2430_DPLL_RECAL_ST_MASK			(1 << 6)
- + #define OMAP24XX_TRANSITION_ST_MASK			(1 << 5)
- + #define OMAP24XX_EVGENOFF_ST_MASK			(1 << 4)
- + #define OMAP24XX_EVGENON_ST_MASK			(1 << 3)
- + 
- + /* PRCM_IRQENABLE_MPU specific bits */
- + #define OMAP2430_DPLL_RECAL_EN_MASK			(1 << 6)
- + #define OMAP24XX_TRANSITION_EN_MASK			(1 << 5)
- + #define OMAP24XX_EVGENOFF_EN_MASK			(1 << 4)
- + #define OMAP24XX_EVGENON_EN_MASK			(1 << 3)
- + 
- + /* PRCM_VOLTCTRL */
- + #define OMAP24XX_AUTO_EXTVOLT_MASK			(1 << 15)
- + #define OMAP24XX_FORCE_EXTVOLT_MASK			(1 << 14)
- + #define OMAP24XX_SETOFF_LEVEL_SHIFT			12
- + #define OMAP24XX_SETOFF_LEVEL_MASK			(0x3 << 12)
- + #define OMAP24XX_MEMRETCTRL_MASK			(1 << 8)
- + #define OMAP24XX_SETRET_LEVEL_SHIFT			6
- + #define OMAP24XX_SETRET_LEVEL_MASK			(0x3 << 6)
- + #define OMAP24XX_VOLT_LEVEL_SHIFT			0
- + #define OMAP24XX_VOLT_LEVEL_MASK			(0x3 << 0)
- + 
- + /* PRCM_VOLTST */
- + #define OMAP24XX_ST_VOLTLEVEL_SHIFT			0
- + #define OMAP24XX_ST_VOLTLEVEL_MASK			(0x3 << 0)
- + 
- + /* PRCM_CLKSRC_CTRL specific bits */
- + 
- + /* PRCM_CLKOUT_CTRL */
- + #define OMAP2420_CLKOUT2_EN_SHIFT			15
- + #define OMAP2420_CLKOUT2_EN_MASK			(1 << 15)
- + #define OMAP2420_CLKOUT2_DIV_SHIFT			11
- + #define OMAP2420_CLKOUT2_DIV_MASK			(0x7 << 11)
- + #define OMAP2420_CLKOUT2_SOURCE_SHIFT			8
- + #define OMAP2420_CLKOUT2_SOURCE_MASK			(0x3 << 8)
- + #define OMAP24XX_CLKOUT_EN_SHIFT			7
- + #define OMAP24XX_CLKOUT_EN_MASK				(1 << 7)
- + #define OMAP24XX_CLKOUT_DIV_SHIFT			3
- + #define OMAP24XX_CLKOUT_DIV_MASK			(0x7 << 3)
- + #define OMAP24XX_CLKOUT_SOURCE_SHIFT			0
- + #define OMAP24XX_CLKOUT_SOURCE_MASK			(0x3 << 0)
- + 
- + /* PRCM_CLKEMUL_CTRL */
- + #define OMAP24XX_EMULATION_EN_SHIFT			0
- + #define OMAP24XX_EMULATION_EN_MASK			(1 << 0)
- + 
- + /* PRCM_CLKCFG_CTRL */
- + #define OMAP24XX_VALID_CONFIG_MASK			(1 << 0)
- + 
- + /* PRCM_CLKCFG_STATUS */
- + #define OMAP24XX_CONFIG_STATUS_MASK			(1 << 0)
- + 
- + /* PRCM_VOLTSETUP specific bits */
- + 
- + /* PRCM_CLKSSETUP specific bits */
- + 
- + /* PRCM_POLCTRL */
- + #define OMAP2420_CLKOUT2_POL_MASK			(1 << 10)
- + #define OMAP24XX_CLKOUT_POL_MASK			(1 << 9)
- + #define OMAP24XX_CLKREQ_POL_MASK			(1 << 8)
- + #define OMAP2430_USE_POWEROK_MASK			(1 << 2)
- + #define OMAP2430_POWEROK_POL_MASK			(1 << 1)
- + #define OMAP24XX_EXTVOL_POL_MASK			(1 << 0)
- + 
- + /* RM_RSTST_MPU specific bits */
- + /* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */
- + 
- + /* PM_WKDEP_MPU specific bits */
- + #define OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT		5
- + #define OMAP2430_PM_WKDEP_MPU_EN_MDM_MASK		(1 << 5)
- + #define OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT		2
- + #define OMAP24XX_PM_WKDEP_MPU_EN_DSP_MASK		(1 << 2)
- + 
- + /* PM_EVGENCTRL_MPU specific bits */
- + 
- + /* PM_EVEGENONTIM_MPU specific bits */
- + 
- + /* PM_EVEGENOFFTIM_MPU specific bits */
- + 
- + /* PM_PWSTCTRL_MPU specific bits */
- + #define OMAP2430_FORCESTATE_MASK			(1 << 18)
- + 
- + /* PM_PWSTST_MPU specific bits */
- + /* INTRANSITION, CLKACTIVITY, POWERSTATE, MEMSTATEST are 2430 only */
- + 
- + /* PM_WKEN1_CORE specific bits */
- + 
- + /* PM_WKEN2_CORE specific bits */
- + 
- + /* PM_WKST1_CORE specific bits*/
- + 
- + /* PM_WKST2_CORE specific bits */
- + 
- + /* PM_WKDEP_CORE specific bits*/
- + #define OMAP2430_PM_WKDEP_CORE_EN_MDM_MASK		(1 << 5)
- + #define OMAP24XX_PM_WKDEP_CORE_EN_GFX_MASK		(1 << 3)
- + #define OMAP24XX_PM_WKDEP_CORE_EN_DSP_MASK		(1 << 2)
- + 
- + /* PM_PWSTCTRL_CORE specific bits */
- + #define OMAP24XX_MEMORYCHANGE_MASK			(1 << 20)
- + #define OMAP24XX_MEM3ONSTATE_SHIFT			14
- + #define OMAP24XX_MEM3ONSTATE_MASK			(0x3 << 14)
- + #define OMAP24XX_MEM2ONSTATE_SHIFT			12
- + #define OMAP24XX_MEM2ONSTATE_MASK			(0x3 << 12)
- + #define OMAP24XX_MEM1ONSTATE_SHIFT			10
- + #define OMAP24XX_MEM1ONSTATE_MASK			(0x3 << 10)
- + #define OMAP24XX_MEM3RETSTATE_MASK			(1 << 5)
- + #define OMAP24XX_MEM2RETSTATE_MASK			(1 << 4)
- + #define OMAP24XX_MEM1RETSTATE_MASK			(1 << 3)
- + 
- + /* PM_PWSTST_CORE specific bits */
- + #define OMAP24XX_MEM3STATEST_SHIFT			14
- + #define OMAP24XX_MEM3STATEST_MASK			(0x3 << 14)
- + #define OMAP24XX_MEM2STATEST_SHIFT			12
- + #define OMAP24XX_MEM2STATEST_MASK			(0x3 << 12)
- + #define OMAP24XX_MEM1STATEST_SHIFT			10
- + #define OMAP24XX_MEM1STATEST_MASK			(0x3 << 10)
- + 
- + /* RM_RSTCTRL_GFX */
- + #define OMAP24XX_GFX_RST_MASK				(1 << 0)
- + 
- + /* RM_RSTST_GFX specific bits */
- + #define OMAP24XX_GFX_SW_RST_MASK			(1 << 4)
- + 
- + /* PM_PWSTCTRL_GFX specific bits */
- + 
- + /* PM_WKDEP_GFX specific bits */
- + /* 2430 often calls EN_WAKEUP "EN_WKUP" */
- + 
- + /* RM_RSTCTRL_WKUP specific bits */
- + 
- + /* RM_RSTTIME_WKUP specific bits */
- + 
- + /* RM_RSTST_WKUP specific bits */
- + /* 2430 calls EXTWMPU_RST "EXTWARM_RST" and GLOBALWMPU_RST "GLOBALWARM_RST" */
- + #define OMAP24XX_EXTWMPU_RST_MASK			(1 << 6)
- + #define OMAP24XX_SECU_WD_RST_MASK			(1 << 5)
- + #define OMAP24XX_MPU_WD_RST_MASK			(1 << 4)
- + #define OMAP24XX_SECU_VIOL_RST_MASK			(1 << 3)
- + 
- + /* PM_WKEN_WKUP specific bits */
- + 
- + /* PM_WKST_WKUP specific bits */
- + 
- + /* RM_RSTCTRL_DSP */
- + #define OMAP2420_RST_IVA_MASK				(1 << 8)
- + #define OMAP24XX_RST2_DSP_MASK				(1 << 1)
- + #define OMAP24XX_RST1_DSP_MASK				(1 << 0)
- + 
- + /* RM_RSTST_DSP specific bits */
- + /* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" */
- + #define OMAP2420_IVA_SW_RST_MASK			(1 << 8)
- + #define OMAP24XX_DSP_SW_RST2_MASK			(1 << 5)
- + #define OMAP24XX_DSP_SW_RST1_MASK			(1 << 4)
- + 
- + /* PM_WKDEP_DSP specific bits */
- + 
- + /* PM_PWSTCTRL_DSP specific bits */
- + /* 2430 only: MEMONSTATE, MEMRETSTATE */
- + #define OMAP2420_MEMIONSTATE_SHIFT			12
- + #define OMAP2420_MEMIONSTATE_MASK			(0x3 << 12)
- + #define OMAP2420_MEMIRETSTATE_MASK			(1 << 4)
- + 
- + /* PM_PWSTST_DSP specific bits */
- + /* MEMSTATEST is 2430 only */
- + #define OMAP2420_MEMISTATEST_SHIFT			12
- + #define OMAP2420_MEMISTATEST_MASK			(0x3 << 12)
- + 
- + /* PRCM_IRQSTATUS_DSP specific bits */
- + 
- + /* PRCM_IRQENABLE_DSP specific bits */
- + 
- + /* RM_RSTCTRL_MDM */
- + /* 2430 only */
- + #define OMAP2430_PWRON1_MDM_MASK			(1 << 1)
- + #define OMAP2430_RST1_MDM_MASK				(1 << 0)
- + 
- + /* RM_RSTST_MDM specific bits */
- + /* 2430 only */
- + #define OMAP2430_MDM_SECU_VIOL_MASK			(1 << 6)
- + #define OMAP2430_MDM_SW_PWRON1_MASK			(1 << 5)
- + #define OMAP2430_MDM_SW_RST1_MASK			(1 << 4)
- + 
- + /* PM_WKEN_MDM */
- + /* 2430 only */
- + #define OMAP2430_PM_WKEN_MDM_EN_MDM_MASK		(1 << 0)
- + 
- + /* PM_WKST_MDM specific bits */
- + /* 2430 only */
- + 
- + /* PM_WKDEP_MDM specific bits */
- + /* 2430 only */
- + 
- + /* PM_PWSTCTRL_MDM specific bits */
- + /* 2430 only */
- + #define OMAP2430_KILLDOMAINWKUP_MASK			(1 << 19)
- + 
- + /* PM_PWSTST_MDM specific bits */
- + /* 2430 only */
- + 
- + /* PRCM_IRQSTATUS_IVA */
- + /* 2420 only */
- + 
- + /* PRCM_IRQENABLE_IVA */
- + /* 2420 only */
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/prm-regbits-33xx.h linux-3.2.1/arch/arm/mach-ckb_3352/prm-regbits-33xx.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/prm-regbits-33xx.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/prm-regbits-33xx.h	2014-05-15 13:25:13.988186688 +0900
- ***************
- *** 0 ****
- --- 1,357 ----
- + /*
- +  * AM33XX Power Management register bits
- +  *
- +  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H
- + #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H
- + 
- + #include "prm.h"
- + 
- + /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
- + #define AM33XX_ABBOFF_ACT_EXPORT_SHIFT			1
- + #define AM33XX_ABBOFF_ACT_EXPORT_MASK			(1 << 1)
- + 
- + /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
- + #define AM33XX_ABBOFF_SLEEP_EXPORT_SHIFT		2
- + #define AM33XX_ABBOFF_SLEEP_EXPORT_MASK			(1 << 2)
- + 
- + /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
- + #define AM33XX_AIPOFF_SHIFT				8
- + #define AM33XX_AIPOFF_MASK				(1 << 8)
- + 
- + /* Used by PM_WKUP_PWRSTST */
- + #define AM33XX_DEBUGSS_MEM_STATEST_SHIFT		17
- + #define AM33XX_DEBUGSS_MEM_STATEST_MASK			(0x3 << 17)
- + 
- + /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
- + #define AM33XX_DISABLE_RTA_EXPORT_SHIFT			0
- + #define AM33XX_DISABLE_RTA_EXPORT_MASK			(1 << 0)
- + 
- + /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
- + #define AM33XX_DPLL_CORE_RECAL_EN_SHIFT			12
- + #define AM33XX_DPLL_CORE_RECAL_EN_MASK			(1 << 12)
- + 
- + /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
- + #define AM33XX_DPLL_CORE_RECAL_ST_SHIFT			12
- + #define AM33XX_DPLL_CORE_RECAL_ST_MASK			(1 << 12)
- + 
- + /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
- + #define AM33XX_DPLL_DDR_RECAL_EN_SHIFT			14
- + #define AM33XX_DPLL_DDR_RECAL_EN_MASK			(1 << 14)
- + 
- + /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
- + #define AM33XX_DPLL_DDR_RECAL_ST_SHIFT			14
- + #define AM33XX_DPLL_DDR_RECAL_ST_MASK			(1 << 14)
- + 
- + /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
- + #define AM33XX_DPLL_DISP_RECAL_EN_SHIFT			15
- + #define AM33XX_DPLL_DISP_RECAL_EN_MASK			(1 << 15)
- + 
- + /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
- + #define AM33XX_DPLL_DISP_RECAL_ST_SHIFT			13
- + #define AM33XX_DPLL_DISP_RECAL_ST_MASK			(1 << 13)
- + 
- + /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
- + #define AM33XX_DPLL_MPU_RECAL_EN_SHIFT			11
- + #define AM33XX_DPLL_MPU_RECAL_EN_MASK			(1 << 11)
- + 
- + /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
- + #define AM33XX_DPLL_MPU_RECAL_ST_SHIFT			11
- + #define AM33XX_DPLL_MPU_RECAL_ST_MASK			(1 << 11)
- + 
- + /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
- + #define AM33XX_DPLL_PER_RECAL_EN_SHIFT			13
- + #define AM33XX_DPLL_PER_RECAL_EN_MASK			(1 << 13)
- + 
- + /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
- + #define AM33XX_DPLL_PER_RECAL_ST_SHIFT			15
- + #define AM33XX_DPLL_PER_RECAL_ST_MASK			(1 << 15)
- + 
- + /* Used by RM_WKUP_RSTST */
- + #define AM33XX_EMULATION_M3_RST_SHIFT			6
- + #define AM33XX_EMULATION_M3_RST_MASK			(1 << 6)
- + 
- + /* Used by RM_MPU_RSTST */
- + #define AM33XX_EMULATION_MPU_RST_SHIFT			5
- + #define AM33XX_EMULATION_MPU_RST_MASK			(1 << 5)
- + 
- + /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
- + #define AM33XX_ENFUNC1_EXPORT_SHIFT			3
- + #define AM33XX_ENFUNC1_EXPORT_MASK			(1 << 3)
- + 
- + /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
- + #define AM33XX_ENFUNC3_EXPORT_SHIFT			5
- + #define AM33XX_ENFUNC3_EXPORT_MASK			(1 << 5)
- + 
- + /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
- + #define AM33XX_ENFUNC4_SHIFT				6
- + #define AM33XX_ENFUNC4_MASK				(1 << 6)
- + 
- + /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
- + #define AM33XX_ENFUNC5_SHIFT				7
- + #define AM33XX_ENFUNC5_MASK				(1 << 7)
- + 
- + /* Used by PRM_RSTST */
- + #define AM33XX_EXTERNAL_WARM_RST_SHIFT			5
- + #define AM33XX_EXTERNAL_WARM_RST_MASK			(1 << 5)
- + 
- + /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
- + #define AM33XX_FORCEWKUP_EN_SHIFT			10
- + #define AM33XX_FORCEWKUP_EN_MASK			(1 << 10)
- + 
- + /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
- + #define AM33XX_FORCEWKUP_ST_SHIFT			10
- + #define AM33XX_FORCEWKUP_ST_MASK			(1 << 10)
- + 
- + /* Used by PM_GFX_PWRSTCTRL */
- + #define AM33XX_GFX_MEM_ONSTATE_SHIFT			17
- + #define AM33XX_GFX_MEM_ONSTATE_MASK			(0x3 << 17)
- + 
- + /* Used by PM_GFX_PWRSTCTRL */
- + #define AM33XX_GFX_MEM_RETSTATE_SHIFT			6
- + #define AM33XX_GFX_MEM_RETSTATE_MASK			(1 << 6)
- + 
- + /* Used by PM_GFX_PWRSTST */
- + #define AM33XX_GFX_MEM_STATEST_SHIFT			4
- + #define AM33XX_GFX_MEM_STATEST_MASK			(0x3 << 4)
- + 
- + /* Used by RM_GFX_RSTCTRL, RM_GFX_RSTST */
- + #define AM33XX_GFX_RST_SHIFT				0
- + #define AM33XX_GFX_RST_MASK				(1 << 0)
- + 
- + /* Used by PRM_RSTST */
- + #define AM33XX_GLOBAL_COLD_RST_SHIFT			0
- + #define AM33XX_GLOBAL_COLD_RST_MASK			(1 << 0)
- + 
- + /* Used by PRM_RSTST */
- + #define AM33XX_GLOBAL_WARM_SW_RST_SHIFT			1
- + #define AM33XX_GLOBAL_WARM_SW_RST_MASK			(1 << 1)
- + 
- + /* Used by RM_WKUP_RSTST */
- + #define AM33XX_ICECRUSHER_M3_RST_SHIFT			7
- + #define AM33XX_ICECRUSHER_M3_RST_MASK			(1 << 7)
- + 
- + /* Used by RM_MPU_RSTST */
- + #define AM33XX_ICECRUSHER_MPU_RST_SHIFT			6
- + #define AM33XX_ICECRUSHER_MPU_RST_MASK			(1 << 6)
- + 
- + /* Used by PRM_RSTST */
- + #define AM33XX_ICEPICK_RST_SHIFT			9
- + #define AM33XX_ICEPICK_RST_MASK				(1 << 9)
- + 
- + /* Used by RM_PER_RSTCTRL */
- + #define AM33XX_ICSS_LRST_SHIFT				1
- + #define AM33XX_ICSS_LRST_MASK				(1 << 1)
- + 
- + /* Used by PM_PER_PWRSTCTRL */
- + #define AM33XX_ICSS_MEM_ONSTATE_SHIFT			5
- + #define AM33XX_ICSS_MEM_ONSTATE_MASK			(0x3 << 5)
- + 
- + /* Used by PM_PER_PWRSTCTRL */
- + #define AM33XX_ICSS_MEM_RETSTATE_SHIFT			7
- + #define AM33XX_ICSS_MEM_RETSTATE_MASK			(1 << 7)
- + 
- + /* Used by PM_PER_PWRSTST */
- + #define AM33XX_ICSS_MEM_STATEST_SHIFT			23
- + #define AM33XX_ICSS_MEM_STATEST_MASK			(0x3 << 23)
- + 
- + /*
- +  * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST,
- +  * PM_WKUP_PWRSTST, PM_RTC_PWRSTST
- +  */
- + #define AM33XX_INTRANSITION_SHIFT			20
- + #define AM33XX_INTRANSITION_MASK			(1 << 20)
- + 
- + /* Used by PM_CEFUSE_PWRSTST */
- + #define AM33XX_LASTPOWERSTATEENTERED_SHIFT		24
- + #define AM33XX_LASTPOWERSTATEENTERED_MASK		(0x3 << 24)
- + 
- + /* Used by PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_RTC_PWRSTCTRL */
- + #define AM33XX_LOGICRETSTATE_SHIFT			2
- + #define AM33XX_LOGICRETSTATE_MASK			(1 << 2)
- + 
- + /* Renamed from LOGICRETSTATE Used by PM_PER_PWRSTCTRL, PM_WKUP_PWRSTCTRL */
- + #define AM33XX_LOGICRETSTATE_3_3_SHIFT			3
- + #define AM33XX_LOGICRETSTATE_3_3_MASK			(1 << 3)
- + 
- + /*
- +  * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST,
- +  * PM_WKUP_PWRSTST, PM_RTC_PWRSTST
- +  */
- + #define AM33XX_LOGICSTATEST_SHIFT			2
- + #define AM33XX_LOGICSTATEST_MASK			(1 << 2)
- + 
- + /*
- +  * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL,
- +  * PM_MPU_PWRSTCTRL, PM_WKUP_PWRSTCTRL, PM_RTC_PWRSTCTRL
- +  */
- + #define AM33XX_LOWPOWERSTATECHANGE_SHIFT		4
- + #define AM33XX_LOWPOWERSTATECHANGE_MASK			(1 << 4)
- + 
- + /* Used by PM_MPU_PWRSTCTRL */
- + #define AM33XX_MPU_L1_ONSTATE_SHIFT			18
- + #define AM33XX_MPU_L1_ONSTATE_MASK			(0x3 << 18)
- + 
- + /* Used by PM_MPU_PWRSTCTRL */
- + #define AM33XX_MPU_L1_RETSTATE_SHIFT			22
- + #define AM33XX_MPU_L1_RETSTATE_MASK			(1 << 22)
- + 
- + /* Used by PM_MPU_PWRSTST */
- + #define AM33XX_MPU_L1_STATEST_SHIFT			6
- + #define AM33XX_MPU_L1_STATEST_MASK			(0x3 << 6)
- + 
- + /* Used by PM_MPU_PWRSTCTRL */
- + #define AM33XX_MPU_L2_ONSTATE_SHIFT			20
- + #define AM33XX_MPU_L2_ONSTATE_MASK			(0x3 << 20)
- + 
- + /* Used by PM_MPU_PWRSTCTRL */
- + #define AM33XX_MPU_L2_RETSTATE_SHIFT			23
- + #define AM33XX_MPU_L2_RETSTATE_MASK			(1 << 23)
- + 
- + /* Used by PM_MPU_PWRSTST */
- + #define AM33XX_MPU_L2_STATEST_SHIFT			8
- + #define AM33XX_MPU_L2_STATEST_MASK			(0x3 << 8)
- + 
- + /* Used by PM_MPU_PWRSTCTRL */
- + #define AM33XX_MPU_RAM_ONSTATE_SHIFT			16
- + #define AM33XX_MPU_RAM_ONSTATE_MASK			(0x3 << 16)
- + 
- + /* Used by PM_MPU_PWRSTCTRL */
- + #define AM33XX_MPU_RAM_RETSTATE_SHIFT			24
- + #define AM33XX_MPU_RAM_RETSTATE_MASK			(1 << 24)
- + 
- + /* Used by PM_MPU_PWRSTST */
- + #define AM33XX_MPU_RAM_STATEST_SHIFT			4
- + #define AM33XX_MPU_RAM_STATEST_MASK			(0x3 << 4)
- + 
- + /* Used by PRM_RSTST */
- + #define AM33XX_MPU_SECURITY_VIOL_RST_SHIFT		2
- + #define AM33XX_MPU_SECURITY_VIOL_RST_MASK		(1 << 2)
- + 
- + /* Used by PRM_SRAM_COUNT */
- + #define AM33XX_PCHARGECNT_VALUE_SHIFT			0
- + #define AM33XX_PCHARGECNT_VALUE_MASK			(0x3f << 0)
- + 
- + /* Used by RM_PER_RSTCTRL */
- + #define AM33XX_PCI_LRST_SHIFT				0
- + #define AM33XX_PCI_LRST_MASK				(1 << 0)
- + 
- + /* Renamed from PCI_LRST Used by RM_PER_RSTST */
- + #define AM33XX_PCI_LRST_5_5_SHIFT			5
- + #define AM33XX_PCI_LRST_5_5_MASK			(1 << 5)
- + 
- + /* Used by PM_PER_PWRSTCTRL */
- + #define AM33XX_PER_MEM_ONSTATE_SHIFT			25
- + #define AM33XX_PER_MEM_ONSTATE_MASK			(0x3 << 25)
- + 
- + /* Used by PM_PER_PWRSTCTRL */
- + #define AM33XX_PER_MEM_RETSTATE_SHIFT			29
- + #define AM33XX_PER_MEM_RETSTATE_MASK			(1 << 29)
- + 
- + /* Used by PM_PER_PWRSTST */
- + #define AM33XX_PER_MEM_STATEST_SHIFT			17
- + #define AM33XX_PER_MEM_STATEST_MASK			(0x3 << 17)
- + 
- + /*
- +  * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL,
- +  * PM_MPU_PWRSTCTRL
- +  */
- + #define AM33XX_POWERSTATE_SHIFT				0
- + #define AM33XX_POWERSTATE_MASK				(0x3 << 0)
- + 
- + /* Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST */
- + #define AM33XX_POWERSTATEST_SHIFT			0
- + #define AM33XX_POWERSTATEST_MASK			(0x3 << 0)
- + 
- + /* Used by PM_PER_PWRSTCTRL */
- + #define AM33XX_RAM_MEM_ONSTATE_SHIFT			30
- + #define AM33XX_RAM_MEM_ONSTATE_MASK			(0x3 << 30)
- + 
- + /* Used by PM_PER_PWRSTCTRL */
- + #define AM33XX_RAM_MEM_RETSTATE_SHIFT			27
- + #define AM33XX_RAM_MEM_RETSTATE_MASK			(1 << 27)
- + 
- + /* Used by PM_PER_PWRSTST */
- + #define AM33XX_RAM_MEM_STATEST_SHIFT			21
- + #define AM33XX_RAM_MEM_STATEST_MASK			(0x3 << 21)
- + 
- + /* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
- + #define AM33XX_RETMODE_ENABLE_SHIFT			0
- + #define AM33XX_RETMODE_ENABLE_MASK			(1 << 0)
- + 
- + /* Used by REVISION_PRM */
- + #define AM33XX_REV_SHIFT				0
- + #define AM33XX_REV_MASK					(0xff << 0)
- + 
- + /* Used by PRM_RSTTIME */
- + #define AM33XX_RSTTIME1_SHIFT				0
- + #define AM33XX_RSTTIME1_MASK				(0xff << 0)
- + 
- + /* Used by PRM_RSTTIME */
- + #define AM33XX_RSTTIME2_SHIFT				8
- + #define AM33XX_RSTTIME2_MASK				(0x1f << 8)
- + 
- + /* Used by PRM_RSTCTRL */
- + #define AM33XX_RST_GLOBAL_COLD_SW_SHIFT			1
- + #define AM33XX_RST_GLOBAL_COLD_SW_MASK			(1 << 1)
- + 
- + /* Used by PRM_RSTCTRL */
- + #define AM33XX_RST_GLOBAL_WARM_SW_SHIFT			0
- + #define AM33XX_RST_GLOBAL_WARM_SW_MASK			(1 << 0)
- + 
- + /* Used by PRM_SRAM_COUNT */
- + #define AM33XX_SLPCNT_VALUE_SHIFT			16
- + #define AM33XX_SLPCNT_VALUE_MASK			(0xff << 16)
- + 
- + /* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
- + #define AM33XX_SRAMLDO_STATUS_SHIFT			8
- + #define AM33XX_SRAMLDO_STATUS_MASK			(1 << 8)
- + 
- + /* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
- + #define AM33XX_SRAM_IN_TRANSITION_SHIFT			9
- + #define AM33XX_SRAM_IN_TRANSITION_MASK			(1 << 9)
- + 
- + /* Used by PRM_SRAM_COUNT */
- + #define AM33XX_STARTUP_COUNT_SHIFT			24
- + #define AM33XX_STARTUP_COUNT_MASK			(0xff << 24)
- + 
- + /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
- + #define AM33XX_TRANSITION_EN_SHIFT			8
- + #define AM33XX_TRANSITION_EN_MASK			(1 << 8)
- + 
- + /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
- + #define AM33XX_TRANSITION_ST_SHIFT			8
- + #define AM33XX_TRANSITION_ST_MASK			(1 << 8)
- + 
- + /* Used by PRM_SRAM_COUNT */
- + #define AM33XX_VSETUPCNT_VALUE_SHIFT			8
- + #define AM33XX_VSETUPCNT_VALUE_MASK			(0xff << 8)
- + 
- + /* Used by PRM_RSTST */
- + #define AM33XX_WDT0_RST_SHIFT				3
- + #define AM33XX_WDT0_RST_MASK				(1 << 3)
- + 
- + /* Used by PRM_RSTST */
- + #define AM33XX_WDT1_RST_SHIFT				4
- + #define AM33XX_WDT1_RST_MASK				(1 << 4)
- + 
- + /* Used by RM_WKUP_RSTCTRL */
- + #define AM33XX_WKUP_M3_LRST_SHIFT			3
- + #define AM33XX_WKUP_M3_LRST_MASK			(1 << 3)
- + 
- + /* Renamed from WKUP_M3_LRST Used by RM_WKUP_RSTST */
- + #define AM33XX_WKUP_M3_LRST_5_5_SHIFT			5
- + #define AM33XX_WKUP_M3_LRST_5_5_MASK			(1 << 5)
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/prm-regbits-34xx.h linux-3.2.1/arch/arm/mach-ckb_3352/prm-regbits-34xx.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/prm-regbits-34xx.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/prm-regbits-34xx.h	2014-05-15 13:25:13.991148739 +0900
- ***************
- *** 0 ****
- --- 1,600 ----
- + /*
- +  * OMAP3430 Power/Reset Management register bits
- +  *
- +  * Copyright (C) 2007-2008 Texas Instruments, Inc.
- +  * Copyright (C) 2007-2008 Nokia Corporation
- +  *
- +  * Written by Paul Walmsley
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
- + #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
- + 
- + 
- + #include "prm2xxx_3xxx.h"
- + 
- + /* Shared register bits */
- + 
- + /* PRM_VC_CMD_VAL_0, PRM_VC_CMD_VAL_1 shared bits */
- + #define OMAP3430_ON_SHIFT				24
- + #define OMAP3430_ON_MASK				(0xff << 24)
- + #define OMAP3430_ONLP_SHIFT				16
- + #define OMAP3430_ONLP_MASK				(0xff << 16)
- + #define OMAP3430_RET_SHIFT				8
- + #define OMAP3430_RET_MASK				(0xff << 8)
- + #define OMAP3430_OFF_SHIFT				0
- + #define OMAP3430_OFF_MASK				(0xff << 0)
- + 
- + /* PRM_VP1_CONFIG, PRM_VP2_CONFIG shared bits */
- + #define OMAP3430_ERROROFFSET_SHIFT			24
- + #define OMAP3430_ERROROFFSET_MASK			(0xff << 24)
- + #define OMAP3430_ERRORGAIN_SHIFT			16
- + #define OMAP3430_ERRORGAIN_MASK				(0xff << 16)
- + #define OMAP3430_INITVOLTAGE_SHIFT			8
- + #define OMAP3430_INITVOLTAGE_MASK			(0xff << 8)
- + #define OMAP3430_TIMEOUTEN_MASK				(1 << 3)
- + #define OMAP3430_INITVDD_MASK				(1 << 2)
- + #define OMAP3430_FORCEUPDATE_MASK			(1 << 1)
- + #define OMAP3430_VPENABLE_MASK				(1 << 0)
- + 
- + /* PRM_VP1_VSTEPMIN, PRM_VP2_VSTEPMIN shared bits */
- + #define OMAP3430_SMPSWAITTIMEMIN_SHIFT			8
- + #define OMAP3430_SMPSWAITTIMEMIN_MASK			(0xffff << 8)
- + #define OMAP3430_VSTEPMIN_SHIFT				0
- + #define OMAP3430_VSTEPMIN_MASK				(0xff << 0)
- + 
- + /* PRM_VP1_VSTEPMAX, PRM_VP2_VSTEPMAX shared bits */
- + #define OMAP3430_SMPSWAITTIMEMAX_SHIFT			8
- + #define OMAP3430_SMPSWAITTIMEMAX_MASK			(0xffff << 8)
- + #define OMAP3430_VSTEPMAX_SHIFT				0
- + #define OMAP3430_VSTEPMAX_MASK				(0xff << 0)
- + 
- + /* PRM_VP1_VLIMITTO, PRM_VP2_VLIMITTO shared bits */
- + #define OMAP3430_VDDMAX_SHIFT				24
- + #define OMAP3430_VDDMAX_MASK				(0xff << 24)
- + #define OMAP3430_VDDMIN_SHIFT				16
- + #define OMAP3430_VDDMIN_MASK				(0xff << 16)
- + #define OMAP3430_TIMEOUT_SHIFT				0
- + #define OMAP3430_TIMEOUT_MASK				(0xffff << 0)
- + 
- + /* PRM_VP1_VOLTAGE, PRM_VP2_VOLTAGE shared bits */
- + #define OMAP3430_VPVOLTAGE_SHIFT			0
- + #define OMAP3430_VPVOLTAGE_MASK				(0xff << 0)
- + 
- + /* PRM_VP1_STATUS, PRM_VP2_STATUS shared bits */
- + #define OMAP3430_VPINIDLE_MASK				(1 << 0)
- + 
- + /* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */
- + #define OMAP3430_EN_PER_SHIFT				7
- + #define OMAP3430_EN_PER_MASK				(1 << 7)
- + 
- + /* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */
- + #define OMAP3430_MEMORYCHANGE_MASK			(1 << 3)
- + 
- + /* PM_PWSTST_IVA2, PM_PWSTST_CORE shared bits */
- + #define OMAP3430_LOGICSTATEST_MASK			(1 << 2)
- + 
- + /* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */
- + #define OMAP3430_LASTLOGICSTATEENTERED_MASK		(1 << 2)
- + 
- + /*
- +  * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE,
- +  * PM_PREPWSTST_GFX, PM_PREPWSTST_DSS, PM_PREPWSTST_CAM,
- +  * PM_PREPWSTST_PER, PM_PREPWSTST_NEON shared bits
- +  */
- + #define OMAP3430_LASTPOWERSTATEENTERED_SHIFT		0
- + #define OMAP3430_LASTPOWERSTATEENTERED_MASK		(0x3 << 0)
- + 
- + /* PRM_IRQSTATUS_IVA2, PRM_IRQSTATUS_MPU shared bits */
- + #define OMAP3430_WKUP_ST_MASK				(1 << 0)
- + 
- + /* PRM_IRQENABLE_IVA2, PRM_IRQENABLE_MPU shared bits */
- + #define OMAP3430_WKUP_EN_MASK				(1 << 0)
- + 
- + /* PM_MPUGRPSEL1_CORE, PM_IVA2GRPSEL1_CORE shared bits */
- + #define OMAP3430_GRPSEL_MMC2_MASK			(1 << 25)
- + #define OMAP3430_GRPSEL_MMC1_MASK			(1 << 24)
- + #define OMAP3430_GRPSEL_MCSPI4_MASK			(1 << 21)
- + #define OMAP3430_GRPSEL_MCSPI3_MASK			(1 << 20)
- + #define OMAP3430_GRPSEL_MCSPI2_MASK			(1 << 19)
- + #define OMAP3430_GRPSEL_MCSPI1_MASK			(1 << 18)
- + #define OMAP3430_GRPSEL_I2C3_SHIFT			17
- + #define OMAP3430_GRPSEL_I2C3_MASK			(1 << 17)
- + #define OMAP3430_GRPSEL_I2C2_SHIFT			16
- + #define OMAP3430_GRPSEL_I2C2_MASK			(1 << 16)
- + #define OMAP3430_GRPSEL_I2C1_SHIFT			15
- + #define OMAP3430_GRPSEL_I2C1_MASK			(1 << 15)
- + #define OMAP3430_GRPSEL_UART2_MASK			(1 << 14)
- + #define OMAP3430_GRPSEL_UART1_MASK			(1 << 13)
- + #define OMAP3430_GRPSEL_GPT11_MASK			(1 << 12)
- + #define OMAP3430_GRPSEL_GPT10_MASK			(1 << 11)
- + #define OMAP3430_GRPSEL_MCBSP5_MASK			(1 << 10)
- + #define OMAP3430_GRPSEL_MCBSP1_MASK			(1 << 9)
- + #define OMAP3430_GRPSEL_HSOTGUSB_MASK			(1 << 4)
- + #define OMAP3430_GRPSEL_D2D_MASK			(1 << 3)
- + 
- + /*
- +  * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM,
- +  * PM_PWSTCTRL_PER shared bits
- +  */
- + #define OMAP3430_MEMONSTATE_SHIFT			16
- + #define OMAP3430_MEMONSTATE_MASK			(0x3 << 16)
- + #define OMAP3430_MEMRETSTATE_MASK			(1 << 8)
- + 
- + /* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */
- + #define OMAP3630_GRPSEL_UART4_MASK			(1 << 18)
- + #define OMAP3430_GRPSEL_GPIO6_MASK			(1 << 17)
- + #define OMAP3430_GRPSEL_GPIO5_MASK			(1 << 16)
- + #define OMAP3430_GRPSEL_GPIO4_MASK			(1 << 15)
- + #define OMAP3430_GRPSEL_GPIO3_MASK			(1 << 14)
- + #define OMAP3430_GRPSEL_GPIO2_MASK			(1 << 13)
- + #define OMAP3430_GRPSEL_UART3_MASK			(1 << 11)
- + #define OMAP3430_GRPSEL_GPT9_MASK			(1 << 10)
- + #define OMAP3430_GRPSEL_GPT8_MASK			(1 << 9)
- + #define OMAP3430_GRPSEL_GPT7_MASK			(1 << 8)
- + #define OMAP3430_GRPSEL_GPT6_MASK			(1 << 7)
- + #define OMAP3430_GRPSEL_GPT5_MASK			(1 << 6)
- + #define OMAP3430_GRPSEL_GPT4_MASK			(1 << 5)
- + #define OMAP3430_GRPSEL_GPT3_MASK			(1 << 4)
- + #define OMAP3430_GRPSEL_GPT2_MASK			(1 << 3)
- + #define OMAP3430_GRPSEL_MCBSP4_MASK			(1 << 2)
- + #define OMAP3430_GRPSEL_MCBSP3_MASK			(1 << 1)
- + #define OMAP3430_GRPSEL_MCBSP2_MASK			(1 << 0)
- + 
- + /* PM_MPUGRPSEL_WKUP, PM_IVA2GRPSEL_WKUP shared bits */
- + #define OMAP3430_GRPSEL_IO_MASK				(1 << 8)
- + #define OMAP3430_GRPSEL_SR2_MASK			(1 << 7)
- + #define OMAP3430_GRPSEL_SR1_MASK			(1 << 6)
- + #define OMAP3430_GRPSEL_GPIO1_MASK			(1 << 3)
- + #define OMAP3430_GRPSEL_GPT12_MASK			(1 << 1)
- + #define OMAP3430_GRPSEL_GPT1_MASK			(1 << 0)
- + 
- + /* Bits specific to each register */
- + 
- + /* RM_RSTCTRL_IVA2 */
- + #define OMAP3430_RST3_IVA2_MASK				(1 << 2)
- + #define OMAP3430_RST2_IVA2_MASK				(1 << 1)
- + #define OMAP3430_RST1_IVA2_MASK				(1 << 0)
- + 
- + /* RM_RSTST_IVA2 specific bits */
- + #define OMAP3430_EMULATION_VSEQ_RST_MASK		(1 << 13)
- + #define OMAP3430_EMULATION_VHWA_RST_MASK		(1 << 12)
- + #define OMAP3430_EMULATION_IVA2_RST_MASK		(1 << 11)
- + #define OMAP3430_IVA2_SW_RST3_MASK			(1 << 10)
- + #define OMAP3430_IVA2_SW_RST2_MASK			(1 << 9)
- + #define OMAP3430_IVA2_SW_RST1_MASK			(1 << 8)
- + 
- + /* PM_WKDEP_IVA2 specific bits */
- + 
- + /* PM_PWSTCTRL_IVA2 specific bits */
- + #define OMAP3430_L2FLATMEMONSTATE_SHIFT			22
- + #define OMAP3430_L2FLATMEMONSTATE_MASK			(0x3 << 22)
- + #define OMAP3430_SHAREDL2CACHEFLATONSTATE_SHIFT		20
- + #define OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK		(0x3 << 20)
- + #define OMAP3430_L1FLATMEMONSTATE_SHIFT			18
- + #define OMAP3430_L1FLATMEMONSTATE_MASK			(0x3 << 18)
- + #define OMAP3430_SHAREDL1CACHEFLATONSTATE_SHIFT		16
- + #define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK		(0x3 << 16)
- + #define OMAP3430_L2FLATMEMRETSTATE_MASK			(1 << 11)
- + #define OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK		(1 << 10)
- + #define OMAP3430_L1FLATMEMRETSTATE_MASK			(1 << 9)
- + #define OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK		(1 << 8)
- + 
- + /* PM_PWSTST_IVA2 specific bits */
- + #define OMAP3430_L2FLATMEMSTATEST_SHIFT			10
- + #define OMAP3430_L2FLATMEMSTATEST_MASK			(0x3 << 10)
- + #define OMAP3430_SHAREDL2CACHEFLATSTATEST_SHIFT		8
- + #define OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK		(0x3 << 8)
- + #define OMAP3430_L1FLATMEMSTATEST_SHIFT			6
- + #define OMAP3430_L1FLATMEMSTATEST_MASK			(0x3 << 6)
- + #define OMAP3430_SHAREDL1CACHEFLATSTATEST_SHIFT		4
- + #define OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK		(0x3 << 4)
- + 
- + /* PM_PREPWSTST_IVA2 specific bits */
- + #define OMAP3430_LASTL2FLATMEMSTATEENTERED_SHIFT		10
- + #define OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK			(0x3 << 10)
- + #define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_SHIFT	8
- + #define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK		(0x3 << 8)
- + #define OMAP3430_LASTL1FLATMEMSTATEENTERED_SHIFT		6
- + #define OMAP3430_LASTL1FLATMEMSTATEENTERED_MASK			(0x3 << 6)
- + #define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_SHIFT	4
- + #define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_MASK		(0x3 << 4)
- + 
- + /* PRM_IRQSTATUS_IVA2 specific bits */
- + #define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST_MASK	(1 << 2)
- + #define OMAP3430_FORCEWKUP_ST_MASK			(1 << 1)
- + 
- + /* PRM_IRQENABLE_IVA2 specific bits */
- + #define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN_MASK	(1 << 2)
- + #define OMAP3430_FORCEWKUP_EN_MASK				(1 << 1)
- + 
- + /* PRM_REVISION specific bits */
- + 
- + /* PRM_SYSCONFIG specific bits */
- + 
- + /* PRM_IRQSTATUS_MPU specific bits */
- + #define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT		25
- + #define OMAP3430ES2_SND_PERIPH_DPLL_ST_MASK		(1 << 25)
- + #define OMAP3430_VC_TIMEOUTERR_ST_MASK			(1 << 24)
- + #define OMAP3430_VC_RAERR_ST_MASK			(1 << 23)
- + #define OMAP3430_VC_SAERR_ST_MASK			(1 << 22)
- + #define OMAP3430_VP2_TRANXDONE_ST_MASK			(1 << 21)
- + #define OMAP3430_VP2_EQVALUE_ST_MASK			(1 << 20)
- + #define OMAP3430_VP2_NOSMPSACK_ST_MASK			(1 << 19)
- + #define OMAP3430_VP2_MAXVDD_ST_MASK			(1 << 18)
- + #define OMAP3430_VP2_MINVDD_ST_MASK			(1 << 17)
- + #define OMAP3430_VP2_OPPCHANGEDONE_ST_MASK		(1 << 16)
- + #define OMAP3430_VP1_TRANXDONE_ST_MASK			(1 << 15)
- + #define OMAP3430_VP1_EQVALUE_ST_MASK			(1 << 14)
- + #define OMAP3430_VP1_NOSMPSACK_ST_MASK			(1 << 13)
- + #define OMAP3430_VP1_MAXVDD_ST_MASK			(1 << 12)
- + #define OMAP3430_VP1_MINVDD_ST_MASK			(1 << 11)
- + #define OMAP3430_VP1_OPPCHANGEDONE_ST_MASK		(1 << 10)
- + #define OMAP3430_IO_ST_MASK				(1 << 9)
- + #define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_MASK	(1 << 8)
- + #define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT	8
- + #define OMAP3430_MPU_DPLL_ST_MASK			(1 << 7)
- + #define OMAP3430_MPU_DPLL_ST_SHIFT			7
- + #define OMAP3430_PERIPH_DPLL_ST_MASK			(1 << 6)
- + #define OMAP3430_PERIPH_DPLL_ST_SHIFT			6
- + #define OMAP3430_CORE_DPLL_ST_MASK			(1 << 5)
- + #define OMAP3430_CORE_DPLL_ST_SHIFT			5
- + #define OMAP3430_TRANSITION_ST_MASK			(1 << 4)
- + #define OMAP3430_EVGENOFF_ST_MASK			(1 << 3)
- + #define OMAP3430_EVGENON_ST_MASK			(1 << 2)
- + #define OMAP3430_FS_USB_WKUP_ST_MASK			(1 << 1)
- + 
- + /* PRM_IRQENABLE_MPU specific bits */
- + #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT		25
- + #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_MASK		(1 << 25)
- + #define OMAP3430_VC_TIMEOUTERR_EN_MASK				(1 << 24)
- + #define OMAP3430_VC_RAERR_EN_MASK				(1 << 23)
- + #define OMAP3430_VC_SAERR_EN_MASK				(1 << 22)
- + #define OMAP3430_VP2_TRANXDONE_EN_MASK				(1 << 21)
- + #define OMAP3430_VP2_EQVALUE_EN_MASK				(1 << 20)
- + #define OMAP3430_VP2_NOSMPSACK_EN_MASK				(1 << 19)
- + #define OMAP3430_VP2_MAXVDD_EN_MASK				(1 << 18)
- + #define OMAP3430_VP2_MINVDD_EN_MASK				(1 << 17)
- + #define OMAP3430_VP2_OPPCHANGEDONE_EN_MASK			(1 << 16)
- + #define OMAP3430_VP1_TRANXDONE_EN_MASK				(1 << 15)
- + #define OMAP3430_VP1_EQVALUE_EN_MASK				(1 << 14)
- + #define OMAP3430_VP1_NOSMPSACK_EN_MASK				(1 << 13)
- + #define OMAP3430_VP1_MAXVDD_EN_MASK				(1 << 12)
- + #define OMAP3430_VP1_MINVDD_EN_MASK				(1 << 11)
- + #define OMAP3430_VP1_OPPCHANGEDONE_EN_MASK			(1 << 10)
- + #define OMAP3430_IO_EN_MASK					(1 << 9)
- + #define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_MASK	(1 << 8)
- + #define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT	8
- + #define OMAP3430_MPU_DPLL_RECAL_EN_MASK				(1 << 7)
- + #define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT			7
- + #define OMAP3430_PERIPH_DPLL_RECAL_EN_MASK			(1 << 6)
- + #define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT			6
- + #define OMAP3430_CORE_DPLL_RECAL_EN_MASK			(1 << 5)
- + #define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT			5
- + #define OMAP3430_TRANSITION_EN_MASK				(1 << 4)
- + #define OMAP3430_EVGENOFF_EN_MASK				(1 << 3)
- + #define OMAP3430_EVGENON_EN_MASK				(1 << 2)
- + #define OMAP3430_FS_USB_WKUP_EN_MASK				(1 << 1)
- + 
- + /* RM_RSTST_MPU specific bits */
- + #define OMAP3430_EMULATION_MPU_RST_MASK			(1 << 11)
- + 
- + /* PM_WKDEP_MPU specific bits */
- + #define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT		5
- + #define OMAP3430_PM_WKDEP_MPU_EN_DSS_MASK		(1 << 5)
- + #define OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT		2
- + #define OMAP3430_PM_WKDEP_MPU_EN_IVA2_MASK		(1 << 2)
- + 
- + /* PM_EVGENCTRL_MPU */
- + #define OMAP3430_OFFLOADMODE_SHIFT			3
- + #define OMAP3430_OFFLOADMODE_MASK			(0x3 << 3)
- + #define OMAP3430_ONLOADMODE_SHIFT			1
- + #define OMAP3430_ONLOADMODE_MASK			(0x3 << 1)
- + #define OMAP3430_ENABLE_MASK				(1 << 0)
- + 
- + /* PM_EVGENONTIM_MPU */
- + #define OMAP3430_ONTIMEVAL_SHIFT			0
- + #define OMAP3430_ONTIMEVAL_MASK				(0xffffffff << 0)
- + 
- + /* PM_EVGENOFFTIM_MPU */
- + #define OMAP3430_OFFTIMEVAL_SHIFT			0
- + #define OMAP3430_OFFTIMEVAL_MASK			(0xffffffff << 0)
- + 
- + /* PM_PWSTCTRL_MPU specific bits */
- + #define OMAP3430_L2CACHEONSTATE_SHIFT			16
- + #define OMAP3430_L2CACHEONSTATE_MASK			(0x3 << 16)
- + #define OMAP3430_L2CACHERETSTATE_MASK			(1 << 8)
- + #define OMAP3430_LOGICL1CACHERETSTATE_MASK		(1 << 2)
- + 
- + /* PM_PWSTST_MPU specific bits */
- + #define OMAP3430_L2CACHESTATEST_SHIFT			6
- + #define OMAP3430_L2CACHESTATEST_MASK			(0x3 << 6)
- + #define OMAP3430_LOGICL1CACHESTATEST_MASK		(1 << 2)
- + 
- + /* PM_PREPWSTST_MPU specific bits */
- + #define OMAP3430_LASTL2CACHESTATEENTERED_SHIFT		6
- + #define OMAP3430_LASTL2CACHESTATEENTERED_MASK		(0x3 << 6)
- + #define OMAP3430_LASTLOGICL1CACHESTATEENTERED_MASK	(1 << 2)
- + 
- + /* RM_RSTCTRL_CORE */
- + #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK		(1 << 1)
- + #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK		(1 << 0)
- + 
- + /* RM_RSTST_CORE specific bits */
- + #define OMAP3430_MODEM_SECURITY_VIOL_RST_MASK		(1 << 10)
- + #define OMAP3430_RM_RSTST_CORE_MODEM_SW_RSTPWRON_MASK	(1 << 9)
- + #define OMAP3430_RM_RSTST_CORE_MODEM_SW_RST_MASK	(1 << 8)
- + 
- + /* PM_WKEN1_CORE specific bits */
- + 
- + /* PM_MPUGRPSEL1_CORE specific bits */
- + #define OMAP3430_GRPSEL_FSHOSTUSB_MASK			(1 << 5)
- + 
- + /* PM_IVA2GRPSEL1_CORE specific bits */
- + 
- + /* PM_WKST1_CORE specific bits */
- + 
- + /* PM_PWSTCTRL_CORE specific bits */
- + #define OMAP3430_MEM2ONSTATE_SHIFT			18
- + #define OMAP3430_MEM2ONSTATE_MASK			(0x3 << 18)
- + #define OMAP3430_MEM1ONSTATE_SHIFT			16
- + #define OMAP3430_MEM1ONSTATE_MASK			(0x3 << 16)
- + #define OMAP3430_MEM2RETSTATE_MASK			(1 << 9)
- + #define OMAP3430_MEM1RETSTATE_MASK			(1 << 8)
- + 
- + /* PM_PWSTST_CORE specific bits */
- + #define OMAP3430_MEM2STATEST_SHIFT			6
- + #define OMAP3430_MEM2STATEST_MASK			(0x3 << 6)
- + #define OMAP3430_MEM1STATEST_SHIFT			4
- + #define OMAP3430_MEM1STATEST_MASK			(0x3 << 4)
- + 
- + /* PM_PREPWSTST_CORE specific bits */
- + #define OMAP3430_LASTMEM2STATEENTERED_SHIFT		6
- + #define OMAP3430_LASTMEM2STATEENTERED_MASK		(0x3 << 6)
- + #define OMAP3430_LASTMEM1STATEENTERED_SHIFT		4
- + #define OMAP3430_LASTMEM1STATEENTERED_MASK		(0x3 << 4)
- + 
- + /* RM_RSTST_GFX specific bits */
- + 
- + /* PM_WKDEP_GFX specific bits */
- + #define OMAP3430_PM_WKDEP_GFX_EN_IVA2_MASK		(1 << 2)
- + 
- + /* PM_PWSTCTRL_GFX specific bits */
- + 
- + /* PM_PWSTST_GFX specific bits */
- + 
- + /* PM_PREPWSTST_GFX specific bits */
- + 
- + /* PM_WKEN_WKUP specific bits */
- + #define OMAP3430_EN_IO_CHAIN_MASK			(1 << 16)
- + #define OMAP3430_EN_IO_MASK				(1 << 8)
- + #define OMAP3430_EN_GPIO1_MASK				(1 << 3)
- + 
- + /* PM_MPUGRPSEL_WKUP specific bits */
- + 
- + /* PM_IVA2GRPSEL_WKUP specific bits */
- + 
- + /* PM_WKST_WKUP specific bits */
- + #define OMAP3430_ST_IO_CHAIN_MASK			(1 << 16)
- + #define OMAP3430_ST_IO_MASK				(1 << 8)
- + 
- + /* PRM_CLKSEL */
- + #define OMAP3430_SYS_CLKIN_SEL_SHIFT			0
- + #define OMAP3430_SYS_CLKIN_SEL_MASK			(0x7 << 0)
- + 
- + /* PRM_CLKOUT_CTRL */
- + #define OMAP3430_CLKOUT_EN_MASK				(1 << 7)
- + #define OMAP3430_CLKOUT_EN_SHIFT			7
- + 
- + /* RM_RSTST_DSS specific bits */
- + 
- + /* PM_WKEN_DSS */
- + #define OMAP3430_PM_WKEN_DSS_EN_DSS_MASK		(1 << 0)
- + 
- + /* PM_WKDEP_DSS specific bits */
- + #define OMAP3430_PM_WKDEP_DSS_EN_IVA2_MASK		(1 << 2)
- + 
- + /* PM_PWSTCTRL_DSS specific bits */
- + 
- + /* PM_PWSTST_DSS specific bits */
- + 
- + /* PM_PREPWSTST_DSS specific bits */
- + 
- + /* RM_RSTST_CAM specific bits */
- + 
- + /* PM_WKDEP_CAM specific bits */
- + #define OMAP3430_PM_WKDEP_CAM_EN_IVA2_MASK		(1 << 2)
- + 
- + /* PM_PWSTCTRL_CAM specific bits */
- + 
- + /* PM_PWSTST_CAM specific bits */
- + 
- + /* PM_PREPWSTST_CAM specific bits */
- + 
- + /* PM_PWSTCTRL_USBHOST specific bits */
- + #define OMAP3430ES2_SAVEANDRESTORE_SHIFT		4
- + 
- + /* RM_RSTST_PER specific bits */
- + 
- + /* PM_WKEN_PER specific bits */
- + 
- + /* PM_MPUGRPSEL_PER specific bits */
- + 
- + /* PM_IVA2GRPSEL_PER specific bits */
- + 
- + /* PM_WKST_PER specific bits */
- + 
- + /* PM_WKDEP_PER specific bits */
- + #define OMAP3430_PM_WKDEP_PER_EN_IVA2_MASK		(1 << 2)
- + 
- + /* PM_PWSTCTRL_PER specific bits */
- + 
- + /* PM_PWSTST_PER specific bits */
- + 
- + /* PM_PREPWSTST_PER specific bits */
- + 
- + /* RM_RSTST_EMU specific bits */
- + 
- + /* PM_PWSTST_EMU specific bits */
- + 
- + /* PRM_VC_SMPS_SA */
- + #define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT		16
- + #define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK		(0x7f << 16)
- + #define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT		0
- + #define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK		(0x7f << 0)
- + 
- + /* PRM_VC_SMPS_VOL_RA */
- + #define OMAP3430_VOLRA1_SHIFT				16
- + #define OMAP3430_VOLRA1_MASK				(0xff << 16)
- + #define OMAP3430_VOLRA0_SHIFT				0
- + #define OMAP3430_VOLRA0_MASK				(0xff << 0)
- + 
- + /* PRM_VC_SMPS_CMD_RA */
- + #define OMAP3430_CMDRA1_SHIFT				16
- + #define OMAP3430_CMDRA1_MASK				(0xff << 16)
- + #define OMAP3430_CMDRA0_SHIFT				0
- + #define OMAP3430_CMDRA0_MASK				(0xff << 0)
- + 
- + /* PRM_VC_CMD_VAL_0 specific bits */
- + #define OMAP3430_VC_CMD_ON_SHIFT			24
- + #define OMAP3430_VC_CMD_ON_MASK				(0xFF << 24)
- + #define OMAP3430_VC_CMD_ONLP_SHIFT			16
- + #define OMAP3430_VC_CMD_ONLP_MASK			(0xFF << 16)
- + #define OMAP3430_VC_CMD_RET_SHIFT			8
- + #define OMAP3430_VC_CMD_RET_MASK			(0xFF << 8)
- + #define OMAP3430_VC_CMD_OFF_SHIFT			0
- + #define OMAP3430_VC_CMD_OFF_MASK			(0xFF << 0)
- + 
- + /* PRM_VC_CMD_VAL_1 specific bits */
- + 
- + /* PRM_VC_CH_CONF */
- + #define OMAP3430_CMD1_MASK				(1 << 20)
- + #define OMAP3430_RACEN1_MASK				(1 << 19)
- + #define OMAP3430_RAC1_MASK				(1 << 18)
- + #define OMAP3430_RAV1_MASK				(1 << 17)
- + #define OMAP3430_PRM_VC_CH_CONF_SA1_MASK		(1 << 16)
- + #define OMAP3430_CMD0_MASK				(1 << 4)
- + #define OMAP3430_RACEN0_MASK				(1 << 3)
- + #define OMAP3430_RAC0_MASK				(1 << 2)
- + #define OMAP3430_RAV0_MASK				(1 << 1)
- + #define OMAP3430_PRM_VC_CH_CONF_SA0_MASK		(1 << 0)
- + 
- + /* PRM_VC_I2C_CFG */
- + #define OMAP3430_HSMASTER_MASK				(1 << 5)
- + #define OMAP3430_SREN_MASK				(1 << 4)
- + #define OMAP3430_HSEN_MASK				(1 << 3)
- + #define OMAP3430_MCODE_SHIFT				0
- + #define OMAP3430_MCODE_MASK				(0x7 << 0)
- + 
- + /* PRM_VC_BYPASS_VAL */
- + #define OMAP3430_VALID_MASK				(1 << 24)
- + #define OMAP3430_DATA_SHIFT				16
- + #define OMAP3430_DATA_MASK				(0xff << 16)
- + #define OMAP3430_REGADDR_SHIFT				8
- + #define OMAP3430_REGADDR_MASK				(0xff << 8)
- + #define OMAP3430_SLAVEADDR_SHIFT			0
- + #define OMAP3430_SLAVEADDR_MASK				(0x7f << 0)
- + 
- + /* PRM_RSTCTRL */
- + #define OMAP3430_RST_DPLL3_MASK				(1 << 2)
- + #define OMAP3430_RST_GS_MASK				(1 << 1)
- + 
- + /* PRM_RSTTIME */
- + #define OMAP3430_RSTTIME2_SHIFT				8
- + #define OMAP3430_RSTTIME2_MASK				(0x1f << 8)
- + #define OMAP3430_RSTTIME1_SHIFT				0
- + #define OMAP3430_RSTTIME1_MASK				(0xff << 0)
- + 
- + /* PRM_RSTST */
- + #define OMAP3430_ICECRUSHER_RST_MASK			(1 << 10)
- + #define OMAP3430_ICEPICK_RST_MASK			(1 << 9)
- + #define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_MASK		(1 << 8)
- + #define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_MASK		(1 << 7)
- + #define OMAP3430_EXTERNAL_WARM_RST_MASK			(1 << 6)
- + #define OMAP3430_SECURE_WD_RST_MASK			(1 << 5)
- + #define OMAP3430_MPU_WD_RST_MASK			(1 << 4)
- + #define OMAP3430_SECURITY_VIOL_RST_MASK			(1 << 3)
- + #define OMAP3430_GLOBAL_SW_RST_MASK			(1 << 1)
- + #define OMAP3430_GLOBAL_COLD_RST_MASK			(1 << 0)
- + 
- + /* PRM_VOLTCTRL */
- + #define OMAP3430_SEL_VMODE_MASK				(1 << 4)
- + #define OMAP3430_SEL_OFF_MASK				(1 << 3)
- + #define OMAP3430_AUTO_OFF_MASK				(1 << 2)
- + #define OMAP3430_AUTO_RET_MASK				(1 << 1)
- + #define OMAP3430_AUTO_SLEEP_MASK			(1 << 0)
- + 
- + /* PRM_SRAM_PCHARGE */
- + #define OMAP3430_PCHARGE_TIME_SHIFT			0
- + #define OMAP3430_PCHARGE_TIME_MASK			(0xff << 0)
- + 
- + /* PRM_CLKSRC_CTRL */
- + #define OMAP3430_SYSCLKDIV_SHIFT			6
- + #define OMAP3430_SYSCLKDIV_MASK				(0x3 << 6)
- + #define OMAP3430_AUTOEXTCLKMODE_SHIFT			3
- + #define OMAP3430_AUTOEXTCLKMODE_MASK			(0x3 << 3)
- + #define OMAP3430_SYSCLKSEL_SHIFT			0
- + #define OMAP3430_SYSCLKSEL_MASK				(0x3 << 0)
- + 
- + /* PRM_VOLTSETUP1 */
- + #define OMAP3430_SETUP_TIME2_SHIFT			16
- + #define OMAP3430_SETUP_TIME2_MASK			(0xffff << 16)
- + #define OMAP3430_SETUP_TIME1_SHIFT			0
- + #define OMAP3430_SETUP_TIME1_MASK			(0xffff << 0)
- + 
- + /* PRM_VOLTOFFSET */
- + #define OMAP3430_OFFSET_TIME_SHIFT			0
- + #define OMAP3430_OFFSET_TIME_MASK			(0xffff << 0)
- + 
- + /* PRM_CLKSETUP */
- + #define OMAP3430_SETUP_TIME_SHIFT			0
- + #define OMAP3430_SETUP_TIME_MASK			(0xffff << 0)
- + 
- + /* PRM_POLCTRL */
- + #define OMAP3430_OFFMODE_POL_MASK			(1 << 3)
- + #define OMAP3430_CLKOUT_POL_MASK			(1 << 2)
- + #define OMAP3430_CLKREQ_POL_MASK			(1 << 1)
- + #define OMAP3430_EXTVOL_POL_MASK			(1 << 0)
- + 
- + /* PRM_VOLTSETUP2 */
- + #define OMAP3430_OFFMODESETUPTIME_SHIFT			0
- + #define OMAP3430_OFFMODESETUPTIME_MASK			(0xffff << 0)
- + 
- + /* PRM_VP1_CONFIG specific bits */
- + 
- + /* PRM_VP1_VSTEPMIN specific bits */
- + 
- + /* PRM_VP1_VSTEPMAX specific bits */
- + 
- + /* PRM_VP1_VLIMITTO specific bits */
- + 
- + /* PRM_VP1_VOLTAGE specific bits */
- + 
- + /* PRM_VP1_STATUS specific bits */
- + 
- + /* PRM_VP2_CONFIG specific bits */
- + 
- + /* PRM_VP2_VSTEPMIN specific bits */
- + 
- + /* PRM_VP2_VSTEPMAX specific bits */
- + 
- + /* PRM_VP2_VLIMITTO specific bits */
- + 
- + /* PRM_VP2_VOLTAGE specific bits */
- + 
- + /* PRM_VP2_STATUS specific bits */
- + 
- + /* RM_RSTST_NEON specific bits */
- + 
- + /* PM_WKDEP_NEON specific bits */
- + 
- + /* PM_PWSTCTRL_NEON specific bits */
- + 
- + /* PM_PWSTST_NEON specific bits */
- + 
- + /* PM_PREPWSTST_NEON specific bits */
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/prm-regbits-44xx.h linux-3.2.1/arch/arm/mach-ckb_3352/prm-regbits-44xx.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/prm-regbits-44xx.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/prm-regbits-44xx.h	2014-05-15 13:25:13.995230576 +0900
- ***************
- *** 0 ****
- --- 1,2327 ----
- + /*
- +  * OMAP44xx Power Management register bits
- +  *
- +  * Copyright (C) 2009-2010 Texas Instruments, Inc.
- +  * Copyright (C) 2009-2010 Nokia Corporation
- +  *
- +  * Paul Walmsley (paul@pwsan.com)
- +  * Rajendra Nayak (rnayak@ti.com)
- +  * Benoit Cousson (b-cousson@ti.com)
- +  *
- +  * This file is automatically generated from the OMAP hardware databases.
- +  * We respectfully ask that any modifications to this file be coordinated
- +  * with the public linux-omap@vger.kernel.org mailing list and the
- +  * authors above to ensure that the autogeneration scripts are kept
- +  * up-to-date with the file contents.
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H
- + #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H
- + 
- + 
- + /*
- +  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
- +  * PRM_LDO_SRAM_MPU_SETUP
- +  */
- + #define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT				1
- + #define OMAP4430_ABBOFF_ACT_EXPORT_MASK					(1 << 1)
- + 
- + /*
- +  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
- +  * PRM_LDO_SRAM_MPU_SETUP
- +  */
- + #define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT				2
- + #define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK				(1 << 2)
- + 
- + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
- + #define OMAP4430_ABB_IVA_DONE_EN_SHIFT					31
- + #define OMAP4430_ABB_IVA_DONE_EN_MASK					(1 << 31)
- + 
- + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
- + #define OMAP4430_ABB_IVA_DONE_ST_SHIFT					31
- + #define OMAP4430_ABB_IVA_DONE_ST_MASK					(1 << 31)
- + 
- + /* Used by PRM_IRQENABLE_MPU_2 */
- + #define OMAP4430_ABB_MPU_DONE_EN_SHIFT					7
- + #define OMAP4430_ABB_MPU_DONE_EN_MASK					(1 << 7)
- + 
- + /* Used by PRM_IRQSTATUS_MPU_2 */
- + #define OMAP4430_ABB_MPU_DONE_ST_SHIFT					7
- + #define OMAP4430_ABB_MPU_DONE_ST_MASK					(1 << 7)
- + 
- + /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
- + #define OMAP4430_ACTIVE_FBB_SEL_SHIFT					2
- + #define OMAP4430_ACTIVE_FBB_SEL_MASK					(1 << 2)
- + 
- + /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
- + #define OMAP4430_ACTIVE_RBB_SEL_SHIFT					1
- + #define OMAP4430_ACTIVE_RBB_SEL_MASK					(1 << 1)
- + 
- + /* Used by PM_ABE_PWRSTCTRL */
- + #define OMAP4430_AESSMEM_ONSTATE_SHIFT					16
- + #define OMAP4430_AESSMEM_ONSTATE_MASK					(0x3 << 16)
- + 
- + /* Used by PM_ABE_PWRSTCTRL */
- + #define OMAP4430_AESSMEM_RETSTATE_SHIFT					8
- + #define OMAP4430_AESSMEM_RETSTATE_MASK					(1 << 8)
- + 
- + /* Used by PM_ABE_PWRSTST */
- + #define OMAP4430_AESSMEM_STATEST_SHIFT					4
- + #define OMAP4430_AESSMEM_STATEST_MASK					(0x3 << 4)
- + 
- + /*
- +  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
- +  * PRM_LDO_SRAM_MPU_SETUP
- +  */
- + #define OMAP4430_AIPOFF_SHIFT						8
- + #define OMAP4430_AIPOFF_MASK						(1 << 8)
- + 
- + /* Used by PRM_VOLTCTRL */
- + #define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT				0
- + #define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK				(0x3 << 0)
- + 
- + /* Used by PRM_VOLTCTRL */
- + #define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT				4
- + #define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK				(0x3 << 4)
- + 
- + /* Used by PRM_VOLTCTRL */
- + #define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT				2
- + #define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK				(0x3 << 2)
- + 
- + /* Used by PRM_VC_ERRST */
- + #define OMAP4430_BYPS_RA_ERR_SHIFT					25
- + #define OMAP4430_BYPS_RA_ERR_MASK					(1 << 25)
- + 
- + /* Used by PRM_VC_ERRST */
- + #define OMAP4430_BYPS_SA_ERR_SHIFT					24
- + #define OMAP4430_BYPS_SA_ERR_MASK					(1 << 24)
- + 
- + /* Used by PRM_VC_ERRST */
- + #define OMAP4430_BYPS_TIMEOUT_ERR_SHIFT					26
- + #define OMAP4430_BYPS_TIMEOUT_ERR_MASK					(1 << 26)
- + 
- + /* Used by PRM_RSTST */
- + #define OMAP4430_C2C_RST_SHIFT						10
- + #define OMAP4430_C2C_RST_MASK						(1 << 10)
- + 
- + /* Used by PM_CAM_PWRSTCTRL */
- + #define OMAP4430_CAM_MEM_ONSTATE_SHIFT					16
- + #define OMAP4430_CAM_MEM_ONSTATE_MASK					(0x3 << 16)
- + 
- + /* Used by PM_CAM_PWRSTST */
- + #define OMAP4430_CAM_MEM_STATEST_SHIFT					4
- + #define OMAP4430_CAM_MEM_STATEST_MASK					(0x3 << 4)
- + 
- + /* Used by PRM_CLKREQCTRL */
- + #define OMAP4430_CLKREQ_COND_SHIFT					0
- + #define OMAP4430_CLKREQ_COND_MASK					(0x7 << 0)
- + 
- + /* Used by PRM_VC_VAL_SMPS_RA_CMD */
- + #define OMAP4430_CMDRA_VDD_CORE_L_SHIFT					0
- + #define OMAP4430_CMDRA_VDD_CORE_L_MASK					(0xff << 0)
- + 
- + /* Used by PRM_VC_VAL_SMPS_RA_CMD */
- + #define OMAP4430_CMDRA_VDD_IVA_L_SHIFT					8
- + #define OMAP4430_CMDRA_VDD_IVA_L_MASK					(0xff << 8)
- + 
- + /* Used by PRM_VC_VAL_SMPS_RA_CMD */
- + #define OMAP4430_CMDRA_VDD_MPU_L_SHIFT					16
- + #define OMAP4430_CMDRA_VDD_MPU_L_MASK					(0xff << 16)
- + 
- + /* Used by PRM_VC_CFG_CHANNEL */
- + #define OMAP4430_CMD_VDD_CORE_L_SHIFT					4
- + #define OMAP4430_CMD_VDD_CORE_L_MASK					(1 << 4)
- + 
- + /* Used by PRM_VC_CFG_CHANNEL */
- + #define OMAP4430_CMD_VDD_IVA_L_SHIFT					12
- + #define OMAP4430_CMD_VDD_IVA_L_MASK					(1 << 12)
- + 
- + /* Used by PRM_VC_CFG_CHANNEL */
- + #define OMAP4430_CMD_VDD_MPU_L_SHIFT					17
- + #define OMAP4430_CMD_VDD_MPU_L_MASK					(1 << 17)
- + 
- + /* Used by PM_CORE_PWRSTCTRL */
- + #define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT				18
- + #define OMAP4430_CORE_OCMRAM_ONSTATE_MASK				(0x3 << 18)
- + 
- + /* Used by PM_CORE_PWRSTCTRL */
- + #define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT				9
- + #define OMAP4430_CORE_OCMRAM_RETSTATE_MASK				(1 << 9)
- + 
- + /* Used by PM_CORE_PWRSTST */
- + #define OMAP4430_CORE_OCMRAM_STATEST_SHIFT				6
- + #define OMAP4430_CORE_OCMRAM_STATEST_MASK				(0x3 << 6)
- + 
- + /* Used by PM_CORE_PWRSTCTRL */
- + #define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT				16
- + #define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK				(0x3 << 16)
- + 
- + /* Used by PM_CORE_PWRSTCTRL */
- + #define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT				8
- + #define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK				(1 << 8)
- + 
- + /* Used by PM_CORE_PWRSTST */
- + #define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT				4
- + #define OMAP4430_CORE_OTHER_BANK_STATEST_MASK				(0x3 << 4)
- + 
- + /* Used by REVISION_PRM */
- + #define OMAP4430_CUSTOM_SHIFT						6
- + #define OMAP4430_CUSTOM_MASK						(0x3 << 6)
- + 
- + /* Used by PRM_VC_VAL_BYPASS */
- + #define OMAP4430_DATA_SHIFT						16
- + #define OMAP4430_DATA_MASK						(0xff << 16)
- + 
- + /* Used by PRM_DEVICE_OFF_CTRL */
- + #define OMAP4430_DEVICE_OFF_ENABLE_SHIFT				0
- + #define OMAP4430_DEVICE_OFF_ENABLE_MASK					(1 << 0)
- + 
- + /* Used by PRM_VC_CFG_I2C_MODE */
- + #define OMAP4430_DFILTEREN_SHIFT					6
- + #define OMAP4430_DFILTEREN_MASK						(1 << 6)
- + 
- + /*
- +  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
- +  * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP
- +  */
- + #define OMAP4430_DISABLE_RTA_EXPORT_SHIFT				0
- + #define OMAP4430_DISABLE_RTA_EXPORT_MASK				(1 << 0)
- + 
- + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */
- + #define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT				4
- + #define OMAP4430_DPLL_ABE_RECAL_EN_MASK					(1 << 4)
- + 
- + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */
- + #define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT				4
- + #define OMAP4430_DPLL_ABE_RECAL_ST_MASK					(1 << 4)
- + 
- + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
- + #define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT				0
- + #define OMAP4430_DPLL_CORE_RECAL_EN_MASK				(1 << 0)
- + 
- + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
- + #define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT				0
- + #define OMAP4430_DPLL_CORE_RECAL_ST_MASK				(1 << 0)
- + 
- + /* Used by PRM_IRQENABLE_MPU */
- + #define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT				6
- + #define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK				(1 << 6)
- + 
- + /* Used by PRM_IRQSTATUS_MPU */
- + #define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT				6
- + #define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK				(1 << 6)
- + 
- + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */
- + #define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT				2
- + #define OMAP4430_DPLL_IVA_RECAL_EN_MASK					(1 << 2)
- + 
- + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */
- + #define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT				2
- + #define OMAP4430_DPLL_IVA_RECAL_ST_MASK					(1 << 2)
- + 
- + /* Used by PRM_IRQENABLE_MPU */
- + #define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT				1
- + #define OMAP4430_DPLL_MPU_RECAL_EN_MASK					(1 << 1)
- + 
- + /* Used by PRM_IRQSTATUS_MPU */
- + #define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT				1
- + #define OMAP4430_DPLL_MPU_RECAL_ST_MASK					(1 << 1)
- + 
- + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
- + #define OMAP4430_DPLL_PER_RECAL_EN_SHIFT				3
- + #define OMAP4430_DPLL_PER_RECAL_EN_MASK					(1 << 3)
- + 
- + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
- + #define OMAP4430_DPLL_PER_RECAL_ST_SHIFT				3
- + #define OMAP4430_DPLL_PER_RECAL_ST_MASK					(1 << 3)
- + 
- + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
- + #define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT				7
- + #define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK				(1 << 7)
- + 
- + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
- + #define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT				7
- + #define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK				(1 << 7)
- + 
- + /* Used by PM_DSS_PWRSTCTRL */
- + #define OMAP4430_DSS_MEM_ONSTATE_SHIFT					16
- + #define OMAP4430_DSS_MEM_ONSTATE_MASK					(0x3 << 16)
- + 
- + /* Used by PM_DSS_PWRSTCTRL */
- + #define OMAP4430_DSS_MEM_RETSTATE_SHIFT					8
- + #define OMAP4430_DSS_MEM_RETSTATE_MASK					(1 << 8)
- + 
- + /* Used by PM_DSS_PWRSTST */
- + #define OMAP4430_DSS_MEM_STATEST_SHIFT					4
- + #define OMAP4430_DSS_MEM_STATEST_MASK					(0x3 << 4)
- + 
- + /* Used by PM_CORE_PWRSTCTRL */
- + #define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT				20
- + #define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK				(0x3 << 20)
- + 
- + /* Used by PM_CORE_PWRSTCTRL */
- + #define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT				10
- + #define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK				(1 << 10)
- + 
- + /* Used by PM_CORE_PWRSTST */
- + #define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT				8
- + #define OMAP4430_DUCATI_L2RAM_STATEST_MASK				(0x3 << 8)
- + 
- + /* Used by PM_CORE_PWRSTCTRL */
- + #define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT				22
- + #define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK				(0x3 << 22)
- + 
- + /* Used by PM_CORE_PWRSTCTRL */
- + #define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT				11
- + #define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK				(1 << 11)
- + 
- + /* Used by PM_CORE_PWRSTST */
- + #define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT				10
- + #define OMAP4430_DUCATI_UNICACHE_STATEST_MASK				(0x3 << 10)
- + 
- + /* Used by PRM_DEVICE_OFF_CTRL */
- + #define OMAP4460_EMIF1_OFFWKUP_DISABLE_SHIFT				8
- + #define OMAP4460_EMIF1_OFFWKUP_DISABLE_MASK				(1 << 8)
- + 
- + /* Used by PRM_DEVICE_OFF_CTRL */
- + #define OMAP4460_EMIF2_OFFWKUP_DISABLE_SHIFT				9
- + #define OMAP4460_EMIF2_OFFWKUP_DISABLE_MASK				(1 << 9)
- + 
- + /* Used by RM_MPU_RSTST */
- + #define OMAP4430_EMULATION_RST_SHIFT					0
- + #define OMAP4430_EMULATION_RST_MASK					(1 << 0)
- + 
- + /* Used by RM_DUCATI_RSTST */
- + #define OMAP4430_EMULATION_RST1ST_SHIFT					3
- + #define OMAP4430_EMULATION_RST1ST_MASK					(1 << 3)
- + 
- + /* Used by RM_DUCATI_RSTST */
- + #define OMAP4430_EMULATION_RST2ST_SHIFT					4
- + #define OMAP4430_EMULATION_RST2ST_MASK					(1 << 4)
- + 
- + /* Used by RM_IVAHD_RSTST */
- + #define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT				3
- + #define OMAP4430_EMULATION_SEQ1_RST1ST_MASK				(1 << 3)
- + 
- + /* Used by RM_IVAHD_RSTST */
- + #define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT				4
- + #define OMAP4430_EMULATION_SEQ2_RST2ST_MASK				(1 << 4)
- + 
- + /* Used by PM_EMU_PWRSTCTRL */
- + #define OMAP4430_EMU_BANK_ONSTATE_SHIFT					16
- + #define OMAP4430_EMU_BANK_ONSTATE_MASK					(0x3 << 16)
- + 
- + /* Used by PM_EMU_PWRSTST */
- + #define OMAP4430_EMU_BANK_STATEST_SHIFT					4
- + #define OMAP4430_EMU_BANK_STATEST_MASK					(0x3 << 4)
- + 
- + /*
- +  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
- +  * PRM_LDO_SRAM_MPU_SETUP
- +  */
- + #define OMAP4430_ENFUNC1_EXPORT_SHIFT					3
- + #define OMAP4430_ENFUNC1_EXPORT_MASK					(1 << 3)
- + 
- + /*
- +  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
- +  * PRM_LDO_SRAM_MPU_SETUP
- +  */
- + #define OMAP4430_ENFUNC3_EXPORT_SHIFT					5
- + #define OMAP4430_ENFUNC3_EXPORT_MASK					(1 << 5)
- + 
- + /*
- +  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
- +  * PRM_LDO_SRAM_MPU_SETUP
- +  */
- + #define OMAP4430_ENFUNC4_SHIFT						6
- + #define OMAP4430_ENFUNC4_MASK						(1 << 6)
- + 
- + /*
- +  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
- +  * PRM_LDO_SRAM_MPU_SETUP
- +  */
- + #define OMAP4430_ENFUNC5_SHIFT						7
- + #define OMAP4430_ENFUNC5_MASK						(1 << 7)
- + 
- + /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
- + #define OMAP4430_ERRORGAIN_SHIFT					16
- + #define OMAP4430_ERRORGAIN_MASK						(0xff << 16)
- + 
- + /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
- + #define OMAP4430_ERROROFFSET_SHIFT					24
- + #define OMAP4430_ERROROFFSET_MASK					(0xff << 24)
- + 
- + /* Used by PRM_RSTST */
- + #define OMAP4430_EXTERNAL_WARM_RST_SHIFT				5
- + #define OMAP4430_EXTERNAL_WARM_RST_MASK					(1 << 5)
- + 
- + /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
- + #define OMAP4430_FORCEUPDATE_SHIFT					1
- + #define OMAP4430_FORCEUPDATE_MASK					(1 << 1)
- + 
- + /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */
- + #define OMAP4430_FORCEUPDATEWAIT_SHIFT					8
- + #define OMAP4430_FORCEUPDATEWAIT_MASK					(0xffffff << 8)
- + 
- + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_TESLA */
- + #define OMAP4430_FORCEWKUP_EN_SHIFT					10
- + #define OMAP4430_FORCEWKUP_EN_MASK					(1 << 10)
- + 
- + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_TESLA */
- + #define OMAP4430_FORCEWKUP_ST_SHIFT					10
- + #define OMAP4430_FORCEWKUP_ST_MASK					(1 << 10)
- + 
- + /* Used by REVISION_PRM */
- + #define OMAP4430_FUNC_SHIFT						16
- + #define OMAP4430_FUNC_MASK						(0xfff << 16)
- + 
- + /* Used by PM_GFX_PWRSTCTRL */
- + #define OMAP4430_GFX_MEM_ONSTATE_SHIFT					16
- + #define OMAP4430_GFX_MEM_ONSTATE_MASK					(0x3 << 16)
- + 
- + /* Used by PM_GFX_PWRSTST */
- + #define OMAP4430_GFX_MEM_STATEST_SHIFT					4
- + #define OMAP4430_GFX_MEM_STATEST_MASK					(0x3 << 4)
- + 
- + /* Used by PRM_RSTST */
- + #define OMAP4430_GLOBAL_COLD_RST_SHIFT					0
- + #define OMAP4430_GLOBAL_COLD_RST_MASK					(1 << 0)
- + 
- + /* Used by PRM_RSTST */
- + #define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT				1
- + #define OMAP4430_GLOBAL_WARM_SW_RST_MASK				(1 << 1)
- + 
- + /* Used by PRM_IO_PMCTRL */
- + #define OMAP4430_GLOBAL_WUEN_SHIFT					16
- + #define OMAP4430_GLOBAL_WUEN_MASK					(1 << 16)
- + 
- + /* Used by PRM_VC_CFG_I2C_MODE */
- + #define OMAP4430_HSMCODE_SHIFT						0
- + #define OMAP4430_HSMCODE_MASK						(0x7 << 0)
- + 
- + /* Used by PRM_VC_CFG_I2C_MODE */
- + #define OMAP4430_HSMODEEN_SHIFT						3
- + #define OMAP4430_HSMODEEN_MASK						(1 << 3)
- + 
- + /* Used by PRM_VC_CFG_I2C_CLK */
- + #define OMAP4430_HSSCLH_SHIFT						16
- + #define OMAP4430_HSSCLH_MASK						(0xff << 16)
- + 
- + /* Used by PRM_VC_CFG_I2C_CLK */
- + #define OMAP4430_HSSCLL_SHIFT						24
- + #define OMAP4430_HSSCLL_MASK						(0xff << 24)
- + 
- + /* Used by PM_IVAHD_PWRSTCTRL */
- + #define OMAP4430_HWA_MEM_ONSTATE_SHIFT					16
- + #define OMAP4430_HWA_MEM_ONSTATE_MASK					(0x3 << 16)
- + 
- + /* Used by PM_IVAHD_PWRSTCTRL */
- + #define OMAP4430_HWA_MEM_RETSTATE_SHIFT					8
- + #define OMAP4430_HWA_MEM_RETSTATE_MASK					(1 << 8)
- + 
- + /* Used by PM_IVAHD_PWRSTST */
- + #define OMAP4430_HWA_MEM_STATEST_SHIFT					4
- + #define OMAP4430_HWA_MEM_STATEST_MASK					(0x3 << 4)
- + 
- + /* Used by RM_MPU_RSTST */
- + #define OMAP4430_ICECRUSHER_MPU_RST_SHIFT				1
- + #define OMAP4430_ICECRUSHER_MPU_RST_MASK				(1 << 1)
- + 
- + /* Used by RM_DUCATI_RSTST */
- + #define OMAP4430_ICECRUSHER_RST1ST_SHIFT				5
- + #define OMAP4430_ICECRUSHER_RST1ST_MASK					(1 << 5)
- + 
- + /* Used by RM_DUCATI_RSTST */
- + #define OMAP4430_ICECRUSHER_RST2ST_SHIFT				6
- + #define OMAP4430_ICECRUSHER_RST2ST_MASK					(1 << 6)
- + 
- + /* Used by RM_IVAHD_RSTST */
- + #define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT				5
- + #define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK				(1 << 5)
- + 
- + /* Used by RM_IVAHD_RSTST */
- + #define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT				6
- + #define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK				(1 << 6)
- + 
- + /* Used by PRM_RSTST */
- + #define OMAP4430_ICEPICK_RST_SHIFT					9
- + #define OMAP4430_ICEPICK_RST_MASK					(1 << 9)
- + 
- + /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
- + #define OMAP4430_INITVDD_SHIFT						2
- + #define OMAP4430_INITVDD_MASK						(1 << 2)
- + 
- + /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
- + #define OMAP4430_INITVOLTAGE_SHIFT					8
- + #define OMAP4430_INITVOLTAGE_MASK					(0xff << 8)
- + 
- + /*
- +  * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST,
- +  * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST,
- +  * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
- +  */
- + #define OMAP4430_INTRANSITION_SHIFT					20
- + #define OMAP4430_INTRANSITION_MASK					(1 << 20)
- + 
- + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
- + #define OMAP4430_IO_EN_SHIFT						9
- + #define OMAP4430_IO_EN_MASK						(1 << 9)
- + 
- + /* Used by PRM_IO_PMCTRL */
- + #define OMAP4430_IO_ON_STATUS_SHIFT					5
- + #define OMAP4430_IO_ON_STATUS_MASK					(1 << 5)
- + 
- + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
- + #define OMAP4430_IO_ST_SHIFT						9
- + #define OMAP4430_IO_ST_MASK						(1 << 9)
- + 
- + /* Used by PRM_IO_PMCTRL */
- + #define OMAP4430_ISOCLK_OVERRIDE_SHIFT					0
- + #define OMAP4430_ISOCLK_OVERRIDE_MASK					(1 << 0)
- + 
- + /* Used by PRM_IO_PMCTRL */
- + #define OMAP4430_ISOCLK_STATUS_SHIFT					1
- + #define OMAP4430_ISOCLK_STATUS_MASK					(1 << 1)
- + 
- + /* Used by PRM_IO_PMCTRL */
- + #define OMAP4430_ISOOVR_EXTEND_SHIFT					4
- + #define OMAP4430_ISOOVR_EXTEND_MASK					(1 << 4)
- + 
- + /* Used by PRM_IO_COUNT */
- + #define OMAP4430_ISO_2_ON_TIME_SHIFT					0
- + #define OMAP4430_ISO_2_ON_TIME_MASK					(0xff << 0)
- + 
- + /* Used by PM_L3INIT_PWRSTCTRL */
- + #define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT				16
- + #define OMAP4430_L3INIT_BANK1_ONSTATE_MASK				(0x3 << 16)
- + 
- + /* Used by PM_L3INIT_PWRSTCTRL */
- + #define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT				8
- + #define OMAP4430_L3INIT_BANK1_RETSTATE_MASK				(1 << 8)
- + 
- + /* Used by PM_L3INIT_PWRSTST */
- + #define OMAP4430_L3INIT_BANK1_STATEST_SHIFT				4
- + #define OMAP4430_L3INIT_BANK1_STATEST_MASK				(0x3 << 4)
- + 
- + /*
- +  * Used by PM_ABE_PWRSTST, PM_CORE_PWRSTST, PM_IVAHD_PWRSTST,
- +  * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
- +  */
- + #define OMAP4430_LASTPOWERSTATEENTERED_SHIFT				24
- + #define OMAP4430_LASTPOWERSTATEENTERED_MASK				(0x3 << 24)
- + 
- + /*
- +  * Used by PM_ABE_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL,
- +  * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL,
- +  * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL
- +  */
- + #define OMAP4430_LOGICRETSTATE_SHIFT					2
- + #define OMAP4430_LOGICRETSTATE_MASK					(1 << 2)
- + 
- + /*
- +  * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST,
- +  * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST,
- +  * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
- +  */
- + #define OMAP4430_LOGICSTATEST_SHIFT					2
- + #define OMAP4430_LOGICSTATEST_MASK					(1 << 2)
- + 
- + /*
- +  * Used by RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT,
- +  * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT,
- +  * RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT, RM_ABE_TIMER5_CONTEXT,
- +  * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT,
- +  * RM_ABE_WDT3_CONTEXT, RM_ALWON_MDMINTC_CONTEXT, RM_ALWON_SR_CORE_CONTEXT,
- +  * RM_ALWON_SR_IVA_CONTEXT, RM_ALWON_SR_MPU_CONTEXT, RM_CAM_FDIF_CONTEXT,
- +  * RM_CAM_ISS_CONTEXT, RM_CEFUSE_CEFUSE_CONTEXT, RM_D2D_SAD2D_CONTEXT,
- +  * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT,
- +  * RM_DUCATI_DUCATI_CONTEXT, RM_EMU_DEBUGSS_CONTEXT, RM_GFX_GFX_CONTEXT,
- +  * RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT, RM_L3INIT_CCPTX_CONTEXT,
- +  * RM_L3INIT_EMAC_CONTEXT, RM_L3INIT_P1500_CONTEXT, RM_L3INIT_PCIESS_CONTEXT,
- +  * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT,
- +  * RM_L3INIT_USBPHYOCP2SCP_CONTEXT, RM_L3INIT_XHPI_CONTEXT,
- +  * RM_L3INSTR_L3_3_CONTEXT, RM_L3INSTR_L3_INSTR_CONTEXT,
- +  * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_L3_2_CONTEXT,
- +  * RM_L3_2_OCMC_RAM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT,
- +  * RM_L4PER_ADC_CONTEXT, RM_L4PER_DMTIMER10_CONTEXT,
- +  * RM_L4PER_DMTIMER11_CONTEXT, RM_L4PER_DMTIMER2_CONTEXT,
- +  * RM_L4PER_DMTIMER3_CONTEXT, RM_L4PER_DMTIMER4_CONTEXT,
- +  * RM_L4PER_DMTIMER9_CONTEXT, RM_L4PER_ELM_CONTEXT, RM_L4PER_HDQ1W_CONTEXT,
- +  * RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, RM_L4PER_I2C2_CONTEXT,
- +  * RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, RM_L4PER_I2C5_CONTEXT,
- +  * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCASP2_CONTEXT, RM_L4PER_MCASP3_CONTEXT,
- +  * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, RM_L4PER_MCSPI2_CONTEXT,
- +  * RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, RM_L4PER_MGATE_CONTEXT,
- +  * RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, RM_L4PER_MMCSD5_CONTEXT,
- +  * RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT,
- +  * RM_L4SEC_PKAEIP29_CONTEXT, RM_MEMIF_DLL_CONTEXT, RM_MEMIF_DLL_H_CONTEXT,
- +  * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT,
- +  * RM_MEMIF_EMIF_FW_CONTEXT, RM_MPU_MPU_CONTEXT, RM_TESLA_TESLA_CONTEXT,
- +  * RM_WKUP_GPIO1_CONTEXT, RM_WKUP_KEYBOARD_CONTEXT, RM_WKUP_L4WKUP_CONTEXT,
- +  * RM_WKUP_RTC_CONTEXT, RM_WKUP_SARRAM_CONTEXT, RM_WKUP_SYNCTIMER_CONTEXT,
- +  * RM_WKUP_TIMER12_CONTEXT, RM_WKUP_TIMER1_CONTEXT, RM_WKUP_USIM_CONTEXT,
- +  * RM_WKUP_WDT1_CONTEXT, RM_WKUP_WDT2_CONTEXT
- +  */
- + #define OMAP4430_LOSTCONTEXT_DFF_SHIFT					0
- + #define OMAP4430_LOSTCONTEXT_DFF_MASK					(1 << 0)
- + 
- + /*
- +  * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_D2D_SAD2D_CONTEXT,
- +  * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DSS_CONTEXT, RM_DUCATI_DUCATI_CONTEXT,
- +  * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT,
- +  * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_USB_HOST_CONTEXT,
- +  * RM_L3INIT_USB_HOST_FS_CONTEXT, RM_L3INIT_USB_OTG_CONTEXT,
- +  * RM_L3INIT_USB_TLL_CONTEXT, RM_L3INSTR_L3_3_CONTEXT,
- +  * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_GPMC_CONTEXT,
- +  * RM_L3_2_L3_2_CONTEXT, RM_L4CFG_HW_SEM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT,
- +  * RM_L4CFG_MAILBOX_CONTEXT, RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT,
- +  * RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT,
- +  * RM_L4PER_I2C1_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT,
- +  * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT,
- +  * RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT,
- +  * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT,
- +  * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT,
- +  * RM_MEMIF_EMIF_FW_CONTEXT, RM_MEMIF_EMIF_H1_CONTEXT,
- +  * RM_MEMIF_EMIF_H2_CONTEXT, RM_SDMA_SDMA_CONTEXT, RM_TESLA_TESLA_CONTEXT
- +  */
- + #define OMAP4430_LOSTCONTEXT_RFF_SHIFT					1
- + #define OMAP4430_LOSTCONTEXT_RFF_MASK					(1 << 1)
- + 
- + /* Used by RM_ABE_AESS_CONTEXT */
- + #define OMAP4430_LOSTMEM_AESSMEM_SHIFT					8
- + #define OMAP4430_LOSTMEM_AESSMEM_MASK					(1 << 8)
- + 
- + /* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */
- + #define OMAP4430_LOSTMEM_CAM_MEM_SHIFT					8
- + #define OMAP4430_LOSTMEM_CAM_MEM_MASK					(1 << 8)
- + 
- + /* Used by RM_L3INSTR_OCP_WP1_CONTEXT */
- + #define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT				8
- + #define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK				(1 << 8)
- + 
- + /* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_MEMIF_DMM_CONTEXT */
- + #define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT			9
- + #define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK			(1 << 9)
- + 
- + /* Used by RM_L3_2_OCMC_RAM_CONTEXT */
- + #define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT				8
- + #define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK				(1 << 8)
- + 
- + /*
- +  * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_MEMIF_DMM_CONTEXT,
- +  * RM_SDMA_SDMA_CONTEXT
- +  */
- + #define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT				8
- + #define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK				(1 << 8)
- + 
- + /* Used by RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT */
- + #define OMAP4430_LOSTMEM_DSS_MEM_SHIFT					8
- + #define OMAP4430_LOSTMEM_DSS_MEM_MASK					(1 << 8)
- + 
- + /* Used by RM_DUCATI_DUCATI_CONTEXT */
- + #define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT				9
- + #define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK				(1 << 9)
- + 
- + /* Used by RM_DUCATI_DUCATI_CONTEXT */
- + #define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT				8
- + #define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK				(1 << 8)
- + 
- + /* Used by RM_EMU_DEBUGSS_CONTEXT */
- + #define OMAP4430_LOSTMEM_EMU_BANK_SHIFT					8
- + #define OMAP4430_LOSTMEM_EMU_BANK_MASK					(1 << 8)
- + 
- + /* Used by RM_GFX_GFX_CONTEXT */
- + #define OMAP4430_LOSTMEM_GFX_MEM_SHIFT					8
- + #define OMAP4430_LOSTMEM_GFX_MEM_MASK					(1 << 8)
- + 
- + /* Used by RM_IVAHD_IVAHD_CONTEXT */
- + #define OMAP4430_LOSTMEM_HWA_MEM_SHIFT					10
- + #define OMAP4430_LOSTMEM_HWA_MEM_MASK					(1 << 10)
- + 
- + /*
- +  * Used by RM_L3INIT_CCPTX_CONTEXT, RM_L3INIT_EMAC_CONTEXT,
- +  * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT,
- +  * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_PCIESS_CONTEXT, RM_L3INIT_SATA_CONTEXT,
- +  * RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT,
- +  * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_XHPI_CONTEXT
- +  */
- + #define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT				8
- + #define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK				(1 << 8)
- + 
- + /* Used by RM_MPU_MPU_CONTEXT */
- + #define OMAP4430_LOSTMEM_MPU_L1_SHIFT					8
- + #define OMAP4430_LOSTMEM_MPU_L1_MASK					(1 << 8)
- + 
- + /* Used by RM_MPU_MPU_CONTEXT */
- + #define OMAP4430_LOSTMEM_MPU_L2_SHIFT					9
- + #define OMAP4430_LOSTMEM_MPU_L2_MASK					(1 << 9)
- + 
- + /* Used by RM_MPU_MPU_CONTEXT */
- + #define OMAP4430_LOSTMEM_MPU_RAM_SHIFT					10
- + #define OMAP4430_LOSTMEM_MPU_RAM_MASK					(1 << 10)
- + 
- + /*
- +  * Used by RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT,
- +  * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT,
- +  * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT
- +  */
- + #define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT				8
- + #define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK				(1 << 8)
- + 
- + /*
- +  * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT,
- +  * RM_ABE_MCBSP3_CONTEXT, RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT
- +  */
- + #define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT				8
- + #define OMAP4430_LOSTMEM_PERIHPMEM_MASK					(1 << 8)
- + 
- + /*
- +  * Used by RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_UART1_CONTEXT,
- +  * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT,
- +  * RM_L4SEC_CRYPTODMA_CONTEXT
- +  */
- + #define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT				8
- + #define OMAP4430_LOSTMEM_RETAINED_BANK_MASK				(1 << 8)
- + 
- + /* Used by RM_IVAHD_SL2_CONTEXT */
- + #define OMAP4430_LOSTMEM_SL2_MEM_SHIFT					8
- + #define OMAP4430_LOSTMEM_SL2_MEM_MASK					(1 << 8)
- + 
- + /* Used by RM_IVAHD_IVAHD_CONTEXT */
- + #define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT					8
- + #define OMAP4430_LOSTMEM_TCM1_MEM_MASK					(1 << 8)
- + 
- + /* Used by RM_IVAHD_IVAHD_CONTEXT */
- + #define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT					9
- + #define OMAP4430_LOSTMEM_TCM2_MEM_MASK					(1 << 9)
- + 
- + /* Used by RM_TESLA_TESLA_CONTEXT */
- + #define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT				10
- + #define OMAP4430_LOSTMEM_TESLA_EDMA_MASK				(1 << 10)
- + 
- + /* Used by RM_TESLA_TESLA_CONTEXT */
- + #define OMAP4430_LOSTMEM_TESLA_L1_SHIFT					8
- + #define OMAP4430_LOSTMEM_TESLA_L1_MASK					(1 << 8)
- + 
- + /* Used by RM_TESLA_TESLA_CONTEXT */
- + #define OMAP4430_LOSTMEM_TESLA_L2_SHIFT					9
- + #define OMAP4430_LOSTMEM_TESLA_L2_MASK					(1 << 9)
- + 
- + /* Used by RM_WKUP_SARRAM_CONTEXT */
- + #define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT				8
- + #define OMAP4430_LOSTMEM_WKUP_BANK_MASK					(1 << 8)
- + 
- + /*
- +  * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL,
- +  * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_IVAHD_PWRSTCTRL,
- +  * PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL
- +  */
- + #define OMAP4430_LOWPOWERSTATECHANGE_SHIFT				4
- + #define OMAP4430_LOWPOWERSTATECHANGE_MASK				(1 << 4)
- + 
- + /* Used by PRM_MODEM_IF_CTRL */
- + #define OMAP4430_MODEM_READY_SHIFT					1
- + #define OMAP4430_MODEM_READY_MASK					(1 << 1)
- + 
- + /* Used by PRM_MODEM_IF_CTRL */
- + #define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT				9
- + #define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK				(1 << 9)
- + 
- + /* Used by PRM_MODEM_IF_CTRL */
- + #define OMAP4430_MODEM_SLEEP_ST_SHIFT					16
- + #define OMAP4430_MODEM_SLEEP_ST_MASK					(1 << 16)
- + 
- + /* Used by PRM_MODEM_IF_CTRL */
- + #define OMAP4430_MODEM_WAKE_IRQ_SHIFT					8
- + #define OMAP4430_MODEM_WAKE_IRQ_MASK					(1 << 8)
- + 
- + /* Used by PM_MPU_PWRSTCTRL */
- + #define OMAP4430_MPU_L1_ONSTATE_SHIFT					16
- + #define OMAP4430_MPU_L1_ONSTATE_MASK					(0x3 << 16)
- + 
- + /* Used by PM_MPU_PWRSTCTRL */
- + #define OMAP4430_MPU_L1_RETSTATE_SHIFT					8
- + #define OMAP4430_MPU_L1_RETSTATE_MASK					(1 << 8)
- + 
- + /* Used by PM_MPU_PWRSTST */
- + #define OMAP4430_MPU_L1_STATEST_SHIFT					4
- + #define OMAP4430_MPU_L1_STATEST_MASK					(0x3 << 4)
- + 
- + /* Used by PM_MPU_PWRSTCTRL */
- + #define OMAP4430_MPU_L2_ONSTATE_SHIFT					18
- + #define OMAP4430_MPU_L2_ONSTATE_MASK					(0x3 << 18)
- + 
- + /* Used by PM_MPU_PWRSTCTRL */
- + #define OMAP4430_MPU_L2_RETSTATE_SHIFT					9
- + #define OMAP4430_MPU_L2_RETSTATE_MASK					(1 << 9)
- + 
- + /* Used by PM_MPU_PWRSTST */
- + #define OMAP4430_MPU_L2_STATEST_SHIFT					6
- + #define OMAP4430_MPU_L2_STATEST_MASK					(0x3 << 6)
- + 
- + /* Used by PM_MPU_PWRSTCTRL */
- + #define OMAP4430_MPU_RAM_ONSTATE_SHIFT					20
- + #define OMAP4430_MPU_RAM_ONSTATE_MASK					(0x3 << 20)
- + 
- + /* Used by PM_MPU_PWRSTCTRL */
- + #define OMAP4430_MPU_RAM_RETSTATE_SHIFT					10
- + #define OMAP4430_MPU_RAM_RETSTATE_MASK					(1 << 10)
- + 
- + /* Used by PM_MPU_PWRSTST */
- + #define OMAP4430_MPU_RAM_STATEST_SHIFT					8
- + #define OMAP4430_MPU_RAM_STATEST_MASK					(0x3 << 8)
- + 
- + /* Used by PRM_RSTST */
- + #define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT				2
- + #define OMAP4430_MPU_SECURITY_VIOL_RST_MASK				(1 << 2)
- + 
- + /* Used by PRM_RSTST */
- + #define OMAP4430_MPU_WDT_RST_SHIFT					3
- + #define OMAP4430_MPU_WDT_RST_MASK					(1 << 3)
- + 
- + /* Used by PM_L4PER_PWRSTCTRL */
- + #define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT				18
- + #define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK				(0x3 << 18)
- + 
- + /* Used by PM_L4PER_PWRSTCTRL */
- + #define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT			9
- + #define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK				(1 << 9)
- + 
- + /* Used by PM_L4PER_PWRSTST */
- + #define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT				6
- + #define OMAP4430_NONRETAINED_BANK_STATEST_MASK				(0x3 << 6)
- + 
- + /* Used by PM_CORE_PWRSTCTRL */
- + #define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT				24
- + #define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK				(0x3 << 24)
- + 
- + /* Used by PM_CORE_PWRSTCTRL */
- + #define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT				12
- + #define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK				(1 << 12)
- + 
- + /* Used by PM_CORE_PWRSTST */
- + #define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT				12
- + #define OMAP4430_OCP_NRET_BANK_STATEST_MASK				(0x3 << 12)
- + 
- + /*
- +  * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
- +  * PRM_VC_VAL_CMD_VDD_MPU_L
- +  */
- + #define OMAP4430_OFF_SHIFT						0
- + #define OMAP4430_OFF_MASK						(0xff << 0)
- + 
- + /*
- +  * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
- +  * PRM_VC_VAL_CMD_VDD_MPU_L
- +  */
- + #define OMAP4430_ON_SHIFT						24
- + #define OMAP4430_ON_MASK						(0xff << 24)
- + 
- + /*
- +  * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
- +  * PRM_VC_VAL_CMD_VDD_MPU_L
- +  */
- + #define OMAP4430_ONLP_SHIFT						16
- + #define OMAP4430_ONLP_MASK						(0xff << 16)
- + 
- + /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
- + #define OMAP4430_OPP_CHANGE_SHIFT					2
- + #define OMAP4430_OPP_CHANGE_MASK					(1 << 2)
- + 
- + /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
- + #define OMAP4430_OPP_SEL_SHIFT						0
- + #define OMAP4430_OPP_SEL_MASK						(0x3 << 0)
- + 
- + /* Used by PRM_SRAM_COUNT */
- + #define OMAP4430_PCHARGECNT_VALUE_SHIFT					0
- + #define OMAP4430_PCHARGECNT_VALUE_MASK					(0x3f << 0)
- + 
- + /* Used by PRM_PSCON_COUNT */
- + #define OMAP4430_PCHARGE_TIME_SHIFT					0
- + #define OMAP4430_PCHARGE_TIME_MASK					(0xff << 0)
- + 
- + /* Used by PM_ABE_PWRSTCTRL */
- + #define OMAP4430_PERIPHMEM_ONSTATE_SHIFT				20
- + #define OMAP4430_PERIPHMEM_ONSTATE_MASK					(0x3 << 20)
- + 
- + /* Used by PM_ABE_PWRSTCTRL */
- + #define OMAP4430_PERIPHMEM_RETSTATE_SHIFT				10
- + #define OMAP4430_PERIPHMEM_RETSTATE_MASK				(1 << 10)
- + 
- + /* Used by PM_ABE_PWRSTST */
- + #define OMAP4430_PERIPHMEM_STATEST_SHIFT				8
- + #define OMAP4430_PERIPHMEM_STATEST_MASK					(0x3 << 8)
- + 
- + /* Used by PRM_PHASE1_CNDP */
- + #define OMAP4430_PHASE1_CNDP_SHIFT					0
- + #define OMAP4430_PHASE1_CNDP_MASK					(0xffffffff << 0)
- + 
- + /* Used by PRM_PHASE2A_CNDP */
- + #define OMAP4430_PHASE2A_CNDP_SHIFT					0
- + #define OMAP4430_PHASE2A_CNDP_MASK					(0xffffffff << 0)
- + 
- + /* Used by PRM_PHASE2B_CNDP */
- + #define OMAP4430_PHASE2B_CNDP_SHIFT					0
- + #define OMAP4430_PHASE2B_CNDP_MASK					(0xffffffff << 0)
- + 
- + /* Used by PRM_PSCON_COUNT */
- + #define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT				8
- + #define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK				(0xff << 8)
- + 
- + /*
- +  * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL,
- +  * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_EMU_PWRSTCTRL, PM_GFX_PWRSTCTRL,
- +  * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL,
- +  * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL
- +  */
- + #define OMAP4430_POWERSTATE_SHIFT					0
- + #define OMAP4430_POWERSTATE_MASK					(0x3 << 0)
- + 
- + /*
- +  * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST,
- +  * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST,
- +  * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
- +  */
- + #define OMAP4430_POWERSTATEST_SHIFT					0
- + #define OMAP4430_POWERSTATEST_MASK					(0x3 << 0)
- + 
- + /* Used by PRM_PWRREQCTRL */
- + #define OMAP4430_PWRREQ_COND_SHIFT					0
- + #define OMAP4430_PWRREQ_COND_MASK					(0x3 << 0)
- + 
- + /* Used by PRM_VC_CFG_CHANNEL */
- + #define OMAP4430_RACEN_VDD_CORE_L_SHIFT					3
- + #define OMAP4430_RACEN_VDD_CORE_L_MASK					(1 << 3)
- + 
- + /* Used by PRM_VC_CFG_CHANNEL */
- + #define OMAP4430_RACEN_VDD_IVA_L_SHIFT					11
- + #define OMAP4430_RACEN_VDD_IVA_L_MASK					(1 << 11)
- + 
- + /* Used by PRM_VC_CFG_CHANNEL */
- + #define OMAP4430_RACEN_VDD_MPU_L_SHIFT					20
- + #define OMAP4430_RACEN_VDD_MPU_L_MASK					(1 << 20)
- + 
- + /* Used by PRM_VC_CFG_CHANNEL */
- + #define OMAP4430_RAC_VDD_CORE_L_SHIFT					2
- + #define OMAP4430_RAC_VDD_CORE_L_MASK					(1 << 2)
- + 
- + /* Used by PRM_VC_CFG_CHANNEL */
- + #define OMAP4430_RAC_VDD_IVA_L_SHIFT					10
- + #define OMAP4430_RAC_VDD_IVA_L_MASK					(1 << 10)
- + 
- + /* Used by PRM_VC_CFG_CHANNEL */
- + #define OMAP4430_RAC_VDD_MPU_L_SHIFT					19
- + #define OMAP4430_RAC_VDD_MPU_L_MASK					(1 << 19)
- + 
- + /*
- +  * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
- +  * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
- +  * PRM_VOLTSETUP_MPU_RET_SLEEP
- +  */
- + #define OMAP4430_RAMP_DOWN_COUNT_SHIFT					16
- + #define OMAP4430_RAMP_DOWN_COUNT_MASK					(0x3f << 16)
- + 
- + /*
- +  * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
- +  * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
- +  * PRM_VOLTSETUP_MPU_RET_SLEEP
- +  */
- + #define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT				24
- + #define OMAP4430_RAMP_DOWN_PRESCAL_MASK					(0x3 << 24)
- + 
- + /*
- +  * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
- +  * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
- +  * PRM_VOLTSETUP_MPU_RET_SLEEP
- +  */
- + #define OMAP4430_RAMP_UP_COUNT_SHIFT					0
- + #define OMAP4430_RAMP_UP_COUNT_MASK					(0x3f << 0)
- + 
- + /*
- +  * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
- +  * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
- +  * PRM_VOLTSETUP_MPU_RET_SLEEP
- +  */
- + #define OMAP4430_RAMP_UP_PRESCAL_SHIFT					8
- + #define OMAP4430_RAMP_UP_PRESCAL_MASK					(0x3 << 8)
- + 
- + /* Used by PRM_VC_CFG_CHANNEL */
- + #define OMAP4430_RAV_VDD_CORE_L_SHIFT					1
- + #define OMAP4430_RAV_VDD_CORE_L_MASK					(1 << 1)
- + 
- + /* Used by PRM_VC_CFG_CHANNEL */
- + #define OMAP4430_RAV_VDD_IVA_L_SHIFT					9
- + #define OMAP4430_RAV_VDD_IVA_L_MASK					(1 << 9)
- + 
- + /* Used by PRM_VC_CFG_CHANNEL */
- + #define OMAP4430_RAV_VDD_MPU_L_SHIFT					18
- + #define OMAP4430_RAV_VDD_MPU_L_MASK					(1 << 18)
- + 
- + /* Used by PRM_VC_VAL_BYPASS */
- + #define OMAP4430_REGADDR_SHIFT						8
- + #define OMAP4430_REGADDR_MASK						(0xff << 8)
- + 
- + /*
- +  * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
- +  * PRM_VC_VAL_CMD_VDD_MPU_L
- +  */
- + #define OMAP4430_RET_SHIFT						8
- + #define OMAP4430_RET_MASK						(0xff << 8)
- + 
- + /* Used by PM_L4PER_PWRSTCTRL */
- + #define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT				16
- + #define OMAP4430_RETAINED_BANK_ONSTATE_MASK				(0x3 << 16)
- + 
- + /* Used by PM_L4PER_PWRSTCTRL */
- + #define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT				8
- + #define OMAP4430_RETAINED_BANK_RETSTATE_MASK				(1 << 8)
- + 
- + /* Used by PM_L4PER_PWRSTST */
- + #define OMAP4430_RETAINED_BANK_STATEST_SHIFT				4
- + #define OMAP4430_RETAINED_BANK_STATEST_MASK				(0x3 << 4)
- + 
- + /*
- +  * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
- +  * PRM_LDO_SRAM_MPU_CTRL
- +  */
- + #define OMAP4430_RETMODE_ENABLE_SHIFT					0
- + #define OMAP4430_RETMODE_ENABLE_MASK					(1 << 0)
- + 
- + /* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */
- + #define OMAP4430_RST1_SHIFT						0
- + #define OMAP4430_RST1_MASK						(1 << 0)
- + 
- + /* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */
- + #define OMAP4430_RST1ST_SHIFT						0
- + #define OMAP4430_RST1ST_MASK						(1 << 0)
- + 
- + /* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */
- + #define OMAP4430_RST2_SHIFT						1
- + #define OMAP4430_RST2_MASK						(1 << 1)
- + 
- + /* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */
- + #define OMAP4430_RST2ST_SHIFT						1
- + #define OMAP4430_RST2ST_MASK						(1 << 1)
- + 
- + /* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL */
- + #define OMAP4430_RST3_SHIFT						2
- + #define OMAP4430_RST3_MASK						(1 << 2)
- + 
- + /* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST */
- + #define OMAP4430_RST3ST_SHIFT						2
- + #define OMAP4430_RST3ST_MASK						(1 << 2)
- + 
- + /* Used by PRM_RSTTIME */
- + #define OMAP4430_RSTTIME1_SHIFT						0
- + #define OMAP4430_RSTTIME1_MASK						(0x3ff << 0)
- + 
- + /* Used by PRM_RSTTIME */
- + #define OMAP4430_RSTTIME2_SHIFT						10
- + #define OMAP4430_RSTTIME2_MASK						(0x1f << 10)
- + 
- + /* Used by PRM_RSTCTRL */
- + #define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT				1
- + #define OMAP4430_RST_GLOBAL_COLD_SW_MASK				(1 << 1)
- + 
- + /* Used by PRM_RSTCTRL */
- + #define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT				0
- + #define OMAP4430_RST_GLOBAL_WARM_SW_MASK				(1 << 0)
- + 
- + /* Used by REVISION_PRM */
- + #define OMAP4430_R_RTL_SHIFT						11
- + #define OMAP4430_R_RTL_MASK						(0x1f << 11)
- + 
- + /* Used by PRM_VC_CFG_CHANNEL */
- + #define OMAP4430_SA_VDD_CORE_L_SHIFT					0
- + #define OMAP4430_SA_VDD_CORE_L_MASK					(1 << 0)
- + 
- + /* Renamed from SA_VDD_CORE_L Used by PRM_VC_SMPS_SA */
- + #define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT				0
- + #define OMAP4430_SA_VDD_CORE_L_0_6_MASK					(0x7f << 0)
- + 
- + /* Used by PRM_VC_CFG_CHANNEL */
- + #define OMAP4430_SA_VDD_IVA_L_SHIFT					8
- + #define OMAP4430_SA_VDD_IVA_L_MASK					(1 << 8)
- + 
- + /* Renamed from SA_VDD_IVA_L Used by PRM_VC_SMPS_SA */
- + #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT			8
- + #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK			(0x7f << 8)
- + 
- + /* Used by PRM_VC_CFG_CHANNEL */
- + #define OMAP4430_SA_VDD_MPU_L_SHIFT					16
- + #define OMAP4430_SA_VDD_MPU_L_MASK					(1 << 16)
- + 
- + /* Renamed from SA_VDD_MPU_L Used by PRM_VC_SMPS_SA */
- + #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT			16
- + #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK			(0x7f << 16)
- + 
- + /* Used by REVISION_PRM */
- + #define OMAP4430_SCHEME_SHIFT						30
- + #define OMAP4430_SCHEME_MASK						(0x3 << 30)
- + 
- + /* Used by PRM_VC_CFG_I2C_CLK */
- + #define OMAP4430_SCLH_SHIFT						0
- + #define OMAP4430_SCLH_MASK						(0xff << 0)
- + 
- + /* Used by PRM_VC_CFG_I2C_CLK */
- + #define OMAP4430_SCLL_SHIFT						8
- + #define OMAP4430_SCLL_MASK						(0xff << 8)
- + 
- + /* Used by PRM_RSTST */
- + #define OMAP4430_SECURE_WDT_RST_SHIFT					4
- + #define OMAP4430_SECURE_WDT_RST_MASK					(1 << 4)
- + 
- + /* Used by PM_IVAHD_PWRSTCTRL */
- + #define OMAP4430_SL2_MEM_ONSTATE_SHIFT					18
- + #define OMAP4430_SL2_MEM_ONSTATE_MASK					(0x3 << 18)
- + 
- + /* Used by PM_IVAHD_PWRSTCTRL */
- + #define OMAP4430_SL2_MEM_RETSTATE_SHIFT					9
- + #define OMAP4430_SL2_MEM_RETSTATE_MASK					(1 << 9)
- + 
- + /* Used by PM_IVAHD_PWRSTST */
- + #define OMAP4430_SL2_MEM_STATEST_SHIFT					6
- + #define OMAP4430_SL2_MEM_STATEST_MASK					(0x3 << 6)
- + 
- + /* Used by PRM_VC_VAL_BYPASS */
- + #define OMAP4430_SLAVEADDR_SHIFT					0
- + #define OMAP4430_SLAVEADDR_MASK						(0x7f << 0)
- + 
- + /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
- + #define OMAP4430_SLEEP_RBB_SEL_SHIFT					3
- + #define OMAP4430_SLEEP_RBB_SEL_MASK					(1 << 3)
- + 
- + /* Used by PRM_SRAM_COUNT */
- + #define OMAP4430_SLPCNT_VALUE_SHIFT					16
- + #define OMAP4430_SLPCNT_VALUE_MASK					(0xff << 16)
- + 
- + /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
- + #define OMAP4430_SMPSWAITTIMEMAX_SHIFT					8
- + #define OMAP4430_SMPSWAITTIMEMAX_MASK					(0xffff << 8)
- + 
- + /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
- + #define OMAP4430_SMPSWAITTIMEMIN_SHIFT					8
- + #define OMAP4430_SMPSWAITTIMEMIN_MASK					(0xffff << 8)
- + 
- + /* Used by PRM_VC_ERRST */
- + #define OMAP4430_SMPS_RA_ERR_CORE_SHIFT					1
- + #define OMAP4430_SMPS_RA_ERR_CORE_MASK					(1 << 1)
- + 
- + /* Used by PRM_VC_ERRST */
- + #define OMAP4430_SMPS_RA_ERR_IVA_SHIFT					9
- + #define OMAP4430_SMPS_RA_ERR_IVA_MASK					(1 << 9)
- + 
- + /* Used by PRM_VC_ERRST */
- + #define OMAP4430_SMPS_RA_ERR_MPU_SHIFT					17
- + #define OMAP4430_SMPS_RA_ERR_MPU_MASK					(1 << 17)
- + 
- + /* Used by PRM_VC_ERRST */
- + #define OMAP4430_SMPS_SA_ERR_CORE_SHIFT					0
- + #define OMAP4430_SMPS_SA_ERR_CORE_MASK					(1 << 0)
- + 
- + /* Used by PRM_VC_ERRST */
- + #define OMAP4430_SMPS_SA_ERR_IVA_SHIFT					8
- + #define OMAP4430_SMPS_SA_ERR_IVA_MASK					(1 << 8)
- + 
- + /* Used by PRM_VC_ERRST */
- + #define OMAP4430_SMPS_SA_ERR_MPU_SHIFT					16
- + #define OMAP4430_SMPS_SA_ERR_MPU_MASK					(1 << 16)
- + 
- + /* Used by PRM_VC_ERRST */
- + #define OMAP4430_SMPS_TIMEOUT_ERR_CORE_SHIFT				2
- + #define OMAP4430_SMPS_TIMEOUT_ERR_CORE_MASK				(1 << 2)
- + 
- + /* Used by PRM_VC_ERRST */
- + #define OMAP4430_SMPS_TIMEOUT_ERR_IVA_SHIFT				10
- + #define OMAP4430_SMPS_TIMEOUT_ERR_IVA_MASK				(1 << 10)
- + 
- + /* Used by PRM_VC_ERRST */
- + #define OMAP4430_SMPS_TIMEOUT_ERR_MPU_SHIFT				18
- + #define OMAP4430_SMPS_TIMEOUT_ERR_MPU_MASK				(1 << 18)
- + 
- + /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
- + #define OMAP4430_SR2EN_SHIFT						0
- + #define OMAP4430_SR2EN_MASK						(1 << 0)
- + 
- + /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
- + #define OMAP4430_SR2_IN_TRANSITION_SHIFT				6
- + #define OMAP4430_SR2_IN_TRANSITION_MASK					(1 << 6)
- + 
- + /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
- + #define OMAP4430_SR2_STATUS_SHIFT					3
- + #define OMAP4430_SR2_STATUS_MASK					(0x3 << 3)
- + 
- + /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
- + #define OMAP4430_SR2_WTCNT_VALUE_SHIFT					8
- + #define OMAP4430_SR2_WTCNT_VALUE_MASK					(0xff << 8)
- + 
- + /*
- +  * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
- +  * PRM_LDO_SRAM_MPU_CTRL
- +  */
- + #define OMAP4430_SRAMLDO_STATUS_SHIFT					8
- + #define OMAP4430_SRAMLDO_STATUS_MASK					(1 << 8)
- + 
- + /*
- +  * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
- +  * PRM_LDO_SRAM_MPU_CTRL
- +  */
- + #define OMAP4430_SRAM_IN_TRANSITION_SHIFT				9
- + #define OMAP4430_SRAM_IN_TRANSITION_MASK				(1 << 9)
- + 
- + /* Used by PRM_VC_CFG_I2C_MODE */
- + #define OMAP4430_SRMODEEN_SHIFT						4
- + #define OMAP4430_SRMODEEN_MASK						(1 << 4)
- + 
- + /* Used by PRM_VOLTSETUP_WARMRESET */
- + #define OMAP4430_STABLE_COUNT_SHIFT					0
- + #define OMAP4430_STABLE_COUNT_MASK					(0x3f << 0)
- + 
- + /* Used by PRM_VOLTSETUP_WARMRESET */
- + #define OMAP4430_STABLE_PRESCAL_SHIFT					8
- + #define OMAP4430_STABLE_PRESCAL_MASK					(0x3 << 8)
- + 
- + /* Used by PRM_LDO_BANDGAP_SETUP */
- + #define OMAP4430_STARTUP_COUNT_SHIFT					0
- + #define OMAP4430_STARTUP_COUNT_MASK					(0xff << 0)
- + 
- + /* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */
- + #define OMAP4430_STARTUP_COUNT_24_31_SHIFT				24
- + #define OMAP4430_STARTUP_COUNT_24_31_MASK				(0xff << 24)
- + 
- + /* Used by PM_IVAHD_PWRSTCTRL */
- + #define OMAP4430_TCM1_MEM_ONSTATE_SHIFT					20
- + #define OMAP4430_TCM1_MEM_ONSTATE_MASK					(0x3 << 20)
- + 
- + /* Used by PM_IVAHD_PWRSTCTRL */
- + #define OMAP4430_TCM1_MEM_RETSTATE_SHIFT				10
- + #define OMAP4430_TCM1_MEM_RETSTATE_MASK					(1 << 10)
- + 
- + /* Used by PM_IVAHD_PWRSTST */
- + #define OMAP4430_TCM1_MEM_STATEST_SHIFT					8
- + #define OMAP4430_TCM1_MEM_STATEST_MASK					(0x3 << 8)
- + 
- + /* Used by PM_IVAHD_PWRSTCTRL */
- + #define OMAP4430_TCM2_MEM_ONSTATE_SHIFT					22
- + #define OMAP4430_TCM2_MEM_ONSTATE_MASK					(0x3 << 22)
- + 
- + /* Used by PM_IVAHD_PWRSTCTRL */
- + #define OMAP4430_TCM2_MEM_RETSTATE_SHIFT				11
- + #define OMAP4430_TCM2_MEM_RETSTATE_MASK					(1 << 11)
- + 
- + /* Used by PM_IVAHD_PWRSTST */
- + #define OMAP4430_TCM2_MEM_STATEST_SHIFT					10
- + #define OMAP4430_TCM2_MEM_STATEST_MASK					(0x3 << 10)
- + 
- + /* Used by RM_TESLA_RSTST */
- + #define OMAP4430_TESLASS_EMU_RSTST_SHIFT				2
- + #define OMAP4430_TESLASS_EMU_RSTST_MASK					(1 << 2)
- + 
- + /* Used by RM_TESLA_RSTST */
- + #define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT				3
- + #define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK				(1 << 3)
- + 
- + /* Used by PM_TESLA_PWRSTCTRL */
- + #define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT				20
- + #define OMAP4430_TESLA_EDMA_ONSTATE_MASK				(0x3 << 20)
- + 
- + /* Used by PM_TESLA_PWRSTCTRL */
- + #define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT				10
- + #define OMAP4430_TESLA_EDMA_RETSTATE_MASK				(1 << 10)
- + 
- + /* Used by PM_TESLA_PWRSTST */
- + #define OMAP4430_TESLA_EDMA_STATEST_SHIFT				8
- + #define OMAP4430_TESLA_EDMA_STATEST_MASK				(0x3 << 8)
- + 
- + /* Used by PM_TESLA_PWRSTCTRL */
- + #define OMAP4430_TESLA_L1_ONSTATE_SHIFT					16
- + #define OMAP4430_TESLA_L1_ONSTATE_MASK					(0x3 << 16)
- + 
- + /* Used by PM_TESLA_PWRSTCTRL */
- + #define OMAP4430_TESLA_L1_RETSTATE_SHIFT				8
- + #define OMAP4430_TESLA_L1_RETSTATE_MASK					(1 << 8)
- + 
- + /* Used by PM_TESLA_PWRSTST */
- + #define OMAP4430_TESLA_L1_STATEST_SHIFT					4
- + #define OMAP4430_TESLA_L1_STATEST_MASK					(0x3 << 4)
- + 
- + /* Used by PM_TESLA_PWRSTCTRL */
- + #define OMAP4430_TESLA_L2_ONSTATE_SHIFT					18
- + #define OMAP4430_TESLA_L2_ONSTATE_MASK					(0x3 << 18)
- + 
- + /* Used by PM_TESLA_PWRSTCTRL */
- + #define OMAP4430_TESLA_L2_RETSTATE_SHIFT				9
- + #define OMAP4430_TESLA_L2_RETSTATE_MASK					(1 << 9)
- + 
- + /* Used by PM_TESLA_PWRSTST */
- + #define OMAP4430_TESLA_L2_STATEST_SHIFT					6
- + #define OMAP4430_TESLA_L2_STATEST_MASK					(0x3 << 6)
- + 
- + /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
- + #define OMAP4430_TIMEOUT_SHIFT						0
- + #define OMAP4430_TIMEOUT_MASK						(0xffff << 0)
- + 
- + /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
- + #define OMAP4430_TIMEOUTEN_SHIFT					3
- + #define OMAP4430_TIMEOUTEN_MASK						(1 << 3)
- + 
- + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
- + #define OMAP4430_TRANSITION_EN_SHIFT					8
- + #define OMAP4430_TRANSITION_EN_MASK					(1 << 8)
- + 
- + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
- + #define OMAP4430_TRANSITION_ST_SHIFT					8
- + #define OMAP4430_TRANSITION_ST_MASK					(1 << 8)
- + 
- + /* Used by PRM_VC_VAL_BYPASS */
- + #define OMAP4430_VALID_SHIFT						24
- + #define OMAP4430_VALID_MASK						(1 << 24)
- + 
- + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
- + #define OMAP4430_VC_BYPASSACK_EN_SHIFT					14
- + #define OMAP4430_VC_BYPASSACK_EN_MASK					(1 << 14)
- + 
- + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
- + #define OMAP4430_VC_BYPASSACK_ST_SHIFT					14
- + #define OMAP4430_VC_BYPASSACK_ST_MASK					(1 << 14)
- + 
- + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
- + #define OMAP4430_VC_CORE_VPACK_EN_SHIFT					22
- + #define OMAP4430_VC_CORE_VPACK_EN_MASK					(1 << 22)
- + 
- + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
- + #define OMAP4430_VC_CORE_VPACK_ST_SHIFT					22
- + #define OMAP4430_VC_CORE_VPACK_ST_MASK					(1 << 22)
- + 
- + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
- + #define OMAP4430_VC_IVA_VPACK_EN_SHIFT					30
- + #define OMAP4430_VC_IVA_VPACK_EN_MASK					(1 << 30)
- + 
- + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
- + #define OMAP4430_VC_IVA_VPACK_ST_SHIFT					30
- + #define OMAP4430_VC_IVA_VPACK_ST_MASK					(1 << 30)
- + 
- + /* Used by PRM_IRQENABLE_MPU_2 */
- + #define OMAP4430_VC_MPU_VPACK_EN_SHIFT					6
- + #define OMAP4430_VC_MPU_VPACK_EN_MASK					(1 << 6)
- + 
- + /* Used by PRM_IRQSTATUS_MPU_2 */
- + #define OMAP4430_VC_MPU_VPACK_ST_SHIFT					6
- + #define OMAP4430_VC_MPU_VPACK_ST_MASK					(1 << 6)
- + 
- + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
- + #define OMAP4430_VC_RAERR_EN_SHIFT					12
- + #define OMAP4430_VC_RAERR_EN_MASK					(1 << 12)
- + 
- + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
- + #define OMAP4430_VC_RAERR_ST_SHIFT					12
- + #define OMAP4430_VC_RAERR_ST_MASK					(1 << 12)
- + 
- + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
- + #define OMAP4430_VC_SAERR_EN_SHIFT					11
- + #define OMAP4430_VC_SAERR_EN_MASK					(1 << 11)
- + 
- + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
- + #define OMAP4430_VC_SAERR_ST_SHIFT					11
- + #define OMAP4430_VC_SAERR_ST_MASK					(1 << 11)
- + 
- + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
- + #define OMAP4430_VC_TOERR_EN_SHIFT					13
- + #define OMAP4430_VC_TOERR_EN_MASK					(1 << 13)
- + 
- + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
- + #define OMAP4430_VC_TOERR_ST_SHIFT					13
- + #define OMAP4430_VC_TOERR_ST_MASK					(1 << 13)
- + 
- + /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
- + #define OMAP4430_VDDMAX_SHIFT						24
- + #define OMAP4430_VDDMAX_MASK						(0xff << 24)
- + 
- + /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
- + #define OMAP4430_VDDMIN_SHIFT						16
- + #define OMAP4430_VDDMIN_MASK						(0xff << 16)
- + 
- + /* Used by PRM_VOLTCTRL */
- + #define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT				12
- + #define OMAP4430_VDD_CORE_I2C_DISABLE_MASK				(1 << 12)
- + 
- + /* Used by PRM_RSTST */
- + #define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT				8
- + #define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK				(1 << 8)
- + 
- + /* Used by PRM_VOLTCTRL */
- + #define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT				14
- + #define OMAP4430_VDD_IVA_I2C_DISABLE_MASK				(1 << 14)
- + 
- + /* Used by PRM_VOLTCTRL */
- + #define OMAP4430_VDD_IVA_PRESENCE_SHIFT					9
- + #define OMAP4430_VDD_IVA_PRESENCE_MASK					(1 << 9)
- + 
- + /* Used by PRM_RSTST */
- + #define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT				7
- + #define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK				(1 << 7)
- + 
- + /* Used by PRM_VOLTCTRL */
- + #define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT				13
- + #define OMAP4430_VDD_MPU_I2C_DISABLE_MASK				(1 << 13)
- + 
- + /* Used by PRM_VOLTCTRL */
- + #define OMAP4430_VDD_MPU_PRESENCE_SHIFT					8
- + #define OMAP4430_VDD_MPU_PRESENCE_MASK					(1 << 8)
- + 
- + /* Used by PRM_RSTST */
- + #define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT				6
- + #define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK				(1 << 6)
- + 
- + /* Used by PRM_VC_ERRST */
- + #define OMAP4430_VFSM_RA_ERR_CORE_SHIFT					4
- + #define OMAP4430_VFSM_RA_ERR_CORE_MASK					(1 << 4)
- + 
- + /* Used by PRM_VC_ERRST */
- + #define OMAP4430_VFSM_RA_ERR_IVA_SHIFT					12
- + #define OMAP4430_VFSM_RA_ERR_IVA_MASK					(1 << 12)
- + 
- + /* Used by PRM_VC_ERRST */
- + #define OMAP4430_VFSM_RA_ERR_MPU_SHIFT					20
- + #define OMAP4430_VFSM_RA_ERR_MPU_MASK					(1 << 20)
- + 
- + /* Used by PRM_VC_ERRST */
- + #define OMAP4430_VFSM_SA_ERR_CORE_SHIFT					3
- + #define OMAP4430_VFSM_SA_ERR_CORE_MASK					(1 << 3)
- + 
- + /* Used by PRM_VC_ERRST */
- + #define OMAP4430_VFSM_SA_ERR_IVA_SHIFT					11
- + #define OMAP4430_VFSM_SA_ERR_IVA_MASK					(1 << 11)
- + 
- + /* Used by PRM_VC_ERRST */
- + #define OMAP4430_VFSM_SA_ERR_MPU_SHIFT					19
- + #define OMAP4430_VFSM_SA_ERR_MPU_MASK					(1 << 19)
- + 
- + /* Used by PRM_VC_ERRST */
- + #define OMAP4430_VFSM_TIMEOUT_ERR_CORE_SHIFT				5
- + #define OMAP4430_VFSM_TIMEOUT_ERR_CORE_MASK				(1 << 5)
- + 
- + /* Used by PRM_VC_ERRST */
- + #define OMAP4430_VFSM_TIMEOUT_ERR_IVA_SHIFT				13
- + #define OMAP4430_VFSM_TIMEOUT_ERR_IVA_MASK				(1 << 13)
- + 
- + /* Used by PRM_VC_ERRST */
- + #define OMAP4430_VFSM_TIMEOUT_ERR_MPU_SHIFT				21
- + #define OMAP4430_VFSM_TIMEOUT_ERR_MPU_MASK				(1 << 21)
- + 
- + /* Used by PRM_VC_VAL_SMPS_RA_VOL */
- + #define OMAP4430_VOLRA_VDD_CORE_L_SHIFT					0
- + #define OMAP4430_VOLRA_VDD_CORE_L_MASK					(0xff << 0)
- + 
- + /* Used by PRM_VC_VAL_SMPS_RA_VOL */
- + #define OMAP4430_VOLRA_VDD_IVA_L_SHIFT					8
- + #define OMAP4430_VOLRA_VDD_IVA_L_MASK					(0xff << 8)
- + 
- + /* Used by PRM_VC_VAL_SMPS_RA_VOL */
- + #define OMAP4430_VOLRA_VDD_MPU_L_SHIFT					16
- + #define OMAP4430_VOLRA_VDD_MPU_L_MASK					(0xff << 16)
- + 
- + /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
- + #define OMAP4430_VPENABLE_SHIFT						0
- + #define OMAP4430_VPENABLE_MASK						(1 << 0)
- + 
- + /* Used by PRM_VP_CORE_STATUS, PRM_VP_IVA_STATUS, PRM_VP_MPU_STATUS */
- + #define OMAP4430_VPINIDLE_SHIFT						0
- + #define OMAP4430_VPINIDLE_MASK						(1 << 0)
- + 
- + /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */
- + #define OMAP4430_VPVOLTAGE_SHIFT					0
- + #define OMAP4430_VPVOLTAGE_MASK						(0xff << 0)
- + 
- + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
- + #define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT				20
- + #define OMAP4430_VP_CORE_EQVALUE_EN_MASK				(1 << 20)
- + 
- + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
- + #define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT				20
- + #define OMAP4430_VP_CORE_EQVALUE_ST_MASK				(1 << 20)
- + 
- + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
- + #define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT				18
- + #define OMAP4430_VP_CORE_MAXVDD_EN_MASK					(1 << 18)
- + 
- + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
- + #define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT				18
- + #define OMAP4430_VP_CORE_MAXVDD_ST_MASK					(1 << 18)
- + 
- + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
- + #define OMAP4430_VP_CORE_MINVDD_EN_SHIFT				17
- + #define OMAP4430_VP_CORE_MINVDD_EN_MASK					(1 << 17)
- + 
- + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
- + #define OMAP4430_VP_CORE_MINVDD_ST_SHIFT				17
- + #define OMAP4430_VP_CORE_MINVDD_ST_MASK					(1 << 17)
- + 
- + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
- + #define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT				19
- + #define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK				(1 << 19)
- + 
- + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
- + #define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT				19
- + #define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK				(1 << 19)
- + 
- + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
- + #define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT				16
- + #define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK				(1 << 16)
- + 
- + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
- + #define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT				16
- + #define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK				(1 << 16)
- + 
- + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
- + #define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT				21
- + #define OMAP4430_VP_CORE_TRANXDONE_EN_MASK				(1 << 21)
- + 
- + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
- + #define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT				21
- + #define OMAP4430_VP_CORE_TRANXDONE_ST_MASK				(1 << 21)
- + 
- + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
- + #define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT				28
- + #define OMAP4430_VP_IVA_EQVALUE_EN_MASK					(1 << 28)
- + 
- + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
- + #define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT				28
- + #define OMAP4430_VP_IVA_EQVALUE_ST_MASK					(1 << 28)
- + 
- + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
- + #define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT					26
- + #define OMAP4430_VP_IVA_MAXVDD_EN_MASK					(1 << 26)
- + 
- + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
- + #define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT					26
- + #define OMAP4430_VP_IVA_MAXVDD_ST_MASK					(1 << 26)
- + 
- + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
- + #define OMAP4430_VP_IVA_MINVDD_EN_SHIFT					25
- + #define OMAP4430_VP_IVA_MINVDD_EN_MASK					(1 << 25)
- + 
- + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
- + #define OMAP4430_VP_IVA_MINVDD_ST_SHIFT					25
- + #define OMAP4430_VP_IVA_MINVDD_ST_MASK					(1 << 25)
- + 
- + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
- + #define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT				27
- + #define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK				(1 << 27)
- + 
- + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
- + #define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT				27
- + #define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK				(1 << 27)
- + 
- + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
- + #define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT				24
- + #define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK				(1 << 24)
- + 
- + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
- + #define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT				24
- + #define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK				(1 << 24)
- + 
- + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
- + #define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT				29
- + #define OMAP4430_VP_IVA_TRANXDONE_EN_MASK				(1 << 29)
- + 
- + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
- + #define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT				29
- + #define OMAP4430_VP_IVA_TRANXDONE_ST_MASK				(1 << 29)
- + 
- + /* Used by PRM_IRQENABLE_MPU_2 */
- + #define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT				4
- + #define OMAP4430_VP_MPU_EQVALUE_EN_MASK					(1 << 4)
- + 
- + /* Used by PRM_IRQSTATUS_MPU_2 */
- + #define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT				4
- + #define OMAP4430_VP_MPU_EQVALUE_ST_MASK					(1 << 4)
- + 
- + /* Used by PRM_IRQENABLE_MPU_2 */
- + #define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT					2
- + #define OMAP4430_VP_MPU_MAXVDD_EN_MASK					(1 << 2)
- + 
- + /* Used by PRM_IRQSTATUS_MPU_2 */
- + #define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT					2
- + #define OMAP4430_VP_MPU_MAXVDD_ST_MASK					(1 << 2)
- + 
- + /* Used by PRM_IRQENABLE_MPU_2 */
- + #define OMAP4430_VP_MPU_MINVDD_EN_SHIFT					1
- + #define OMAP4430_VP_MPU_MINVDD_EN_MASK					(1 << 1)
- + 
- + /* Used by PRM_IRQSTATUS_MPU_2 */
- + #define OMAP4430_VP_MPU_MINVDD_ST_SHIFT					1
- + #define OMAP4430_VP_MPU_MINVDD_ST_MASK					(1 << 1)
- + 
- + /* Used by PRM_IRQENABLE_MPU_2 */
- + #define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT				3
- + #define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK				(1 << 3)
- + 
- + /* Used by PRM_IRQSTATUS_MPU_2 */
- + #define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT				3
- + #define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK				(1 << 3)
- + 
- + /* Used by PRM_IRQENABLE_MPU_2 */
- + #define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT				0
- + #define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK				(1 << 0)
- + 
- + /* Used by PRM_IRQSTATUS_MPU_2 */
- + #define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT				0
- + #define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK				(1 << 0)
- + 
- + /* Used by PRM_IRQENABLE_MPU_2 */
- + #define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT				5
- + #define OMAP4430_VP_MPU_TRANXDONE_EN_MASK				(1 << 5)
- + 
- + /* Used by PRM_IRQSTATUS_MPU_2 */
- + #define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT				5
- + #define OMAP4430_VP_MPU_TRANXDONE_ST_MASK				(1 << 5)
- + 
- + /* Used by PRM_SRAM_COUNT */
- + #define OMAP4430_VSETUPCNT_VALUE_SHIFT					8
- + #define OMAP4430_VSETUPCNT_VALUE_MASK					(0xff << 8)
- + 
- + /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
- + #define OMAP4430_VSTEPMAX_SHIFT						0
- + #define OMAP4430_VSTEPMAX_MASK						(0xff << 0)
- + 
- + /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
- + #define OMAP4430_VSTEPMIN_SHIFT						0
- + #define OMAP4430_VSTEPMIN_MASK						(0xff << 0)
- + 
- + /* Used by PRM_MODEM_IF_CTRL */
- + #define OMAP4430_WAKE_MODEM_SHIFT					0
- + #define OMAP4430_WAKE_MODEM_MASK					(1 << 0)
- + 
- + /* Used by PM_DSS_DSS_WKDEP */
- + #define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT				1
- + #define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK				(1 << 1)
- + 
- + /* Used by PM_DSS_DSS_WKDEP */
- + #define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_DISPC_MPU_MASK					(1 << 0)
- + 
- + /* Used by PM_DSS_DSS_WKDEP */
- + #define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT				3
- + #define OMAP4430_WKUPDEP_DISPC_SDMA_MASK				(1 << 3)
- + 
- + /* Used by PM_DSS_DSS_WKDEP */
- + #define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT				2
- + #define OMAP4430_WKUPDEP_DISPC_TESLA_MASK				(1 << 2)
- + 
- + /* Used by PM_ABE_DMIC_WKDEP */
- + #define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT				7
- + #define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK				(1 << 7)
- + 
- + /* Used by PM_ABE_DMIC_WKDEP */
- + #define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT				6
- + #define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK				(1 << 6)
- + 
- + /* Used by PM_ABE_DMIC_WKDEP */
- + #define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_ABE_DMIC_WKDEP */
- + #define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT				2
- + #define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK				(1 << 2)
- + 
- + /* Used by PM_L4PER_DMTIMER10_WKDEP */
- + #define OMAP4430_WKUPDEP_DMTIMER10_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_L4PER_DMTIMER11_WKDEP */
- + #define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_SHIFT				1
- + #define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK				(1 << 1)
- + 
- + /* Used by PM_L4PER_DMTIMER11_WKDEP */
- + #define OMAP4430_WKUPDEP_DMTIMER11_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_L4PER_DMTIMER2_WKDEP */
- + #define OMAP4430_WKUPDEP_DMTIMER2_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_L4PER_DMTIMER3_WKDEP */
- + #define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_SHIFT				1
- + #define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK				(1 << 1)
- + 
- + /* Used by PM_L4PER_DMTIMER3_WKDEP */
- + #define OMAP4430_WKUPDEP_DMTIMER3_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_L4PER_DMTIMER4_WKDEP */
- + #define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_SHIFT				1
- + #define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK				(1 << 1)
- + 
- + /* Used by PM_L4PER_DMTIMER4_WKDEP */
- + #define OMAP4430_WKUPDEP_DMTIMER4_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_L4PER_DMTIMER9_WKDEP */
- + #define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_SHIFT				1
- + #define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK				(1 << 1)
- + 
- + /* Used by PM_L4PER_DMTIMER9_WKDEP */
- + #define OMAP4430_WKUPDEP_DMTIMER9_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_DSS_DSS_WKDEP */
- + #define OMAP4430_WKUPDEP_DSI1_DUCATI_SHIFT				5
- + #define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK				(1 << 5)
- + 
- + /* Used by PM_DSS_DSS_WKDEP */
- + #define OMAP4430_WKUPDEP_DSI1_MPU_SHIFT					4
- + #define OMAP4430_WKUPDEP_DSI1_MPU_MASK					(1 << 4)
- + 
- + /* Used by PM_DSS_DSS_WKDEP */
- + #define OMAP4430_WKUPDEP_DSI1_SDMA_SHIFT				7
- + #define OMAP4430_WKUPDEP_DSI1_SDMA_MASK					(1 << 7)
- + 
- + /* Used by PM_DSS_DSS_WKDEP */
- + #define OMAP4430_WKUPDEP_DSI1_TESLA_SHIFT				6
- + #define OMAP4430_WKUPDEP_DSI1_TESLA_MASK				(1 << 6)
- + 
- + /* Used by PM_DSS_DSS_WKDEP */
- + #define OMAP4430_WKUPDEP_DSI2_DUCATI_SHIFT				9
- + #define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK				(1 << 9)
- + 
- + /* Used by PM_DSS_DSS_WKDEP */
- + #define OMAP4430_WKUPDEP_DSI2_MPU_SHIFT					8
- + #define OMAP4430_WKUPDEP_DSI2_MPU_MASK					(1 << 8)
- + 
- + /* Used by PM_DSS_DSS_WKDEP */
- + #define OMAP4430_WKUPDEP_DSI2_SDMA_SHIFT				11
- + #define OMAP4430_WKUPDEP_DSI2_SDMA_MASK					(1 << 11)
- + 
- + /* Used by PM_DSS_DSS_WKDEP */
- + #define OMAP4430_WKUPDEP_DSI2_TESLA_SHIFT				10
- + #define OMAP4430_WKUPDEP_DSI2_TESLA_MASK				(1 << 10)
- + 
- + /* Used by PM_WKUP_GPIO1_WKDEP */
- + #define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_SHIFT			1
- + #define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK				(1 << 1)
- + 
- + /* Used by PM_WKUP_GPIO1_WKDEP */
- + #define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_WKUP_GPIO1_WKDEP */
- + #define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_SHIFT				6
- + #define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK				(1 << 6)
- + 
- + /* Used by PM_L4PER_GPIO2_WKDEP */
- + #define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_SHIFT			1
- + #define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK				(1 << 1)
- + 
- + /* Used by PM_L4PER_GPIO2_WKDEP */
- + #define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_L4PER_GPIO2_WKDEP */
- + #define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_SHIFT				6
- + #define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK				(1 << 6)
- + 
- + /* Used by PM_L4PER_GPIO3_WKDEP */
- + #define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_L4PER_GPIO3_WKDEP */
- + #define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_SHIFT				6
- + #define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK				(1 << 6)
- + 
- + /* Used by PM_L4PER_GPIO4_WKDEP */
- + #define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_L4PER_GPIO4_WKDEP */
- + #define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_SHIFT				6
- + #define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK				(1 << 6)
- + 
- + /* Used by PM_L4PER_GPIO5_WKDEP */
- + #define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_L4PER_GPIO5_WKDEP */
- + #define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_SHIFT				6
- + #define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK				(1 << 6)
- + 
- + /* Used by PM_L4PER_GPIO6_WKDEP */
- + #define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_L4PER_GPIO6_WKDEP */
- + #define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_SHIFT				6
- + #define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK				(1 << 6)
- + 
- + /* Used by PM_DSS_DSS_WKDEP */
- + #define OMAP4430_WKUPDEP_HDMIDMA_SDMA_SHIFT				19
- + #define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK				(1 << 19)
- + 
- + /* Used by PM_DSS_DSS_WKDEP */
- + #define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_SHIFT				13
- + #define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK				(1 << 13)
- + 
- + /* Used by PM_DSS_DSS_WKDEP */
- + #define OMAP4430_WKUPDEP_HDMIIRQ_MPU_SHIFT				12
- + #define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK				(1 << 12)
- + 
- + /* Used by PM_DSS_DSS_WKDEP */
- + #define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_SHIFT				14
- + #define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK				(1 << 14)
- + 
- + /* Used by PM_L4PER_HECC1_WKDEP */
- + #define OMAP4430_WKUPDEP_HECC1_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_HECC1_MPU_MASK					(1 << 0)
- + 
- + /* Used by PM_L4PER_HECC2_WKDEP */
- + #define OMAP4430_WKUPDEP_HECC2_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_HECC2_MPU_MASK					(1 << 0)
- + 
- + /* Used by PM_L3INIT_HSI_WKDEP */
- + #define OMAP4430_WKUPDEP_HSI_DSP_TESLA_SHIFT				6
- + #define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK				(1 << 6)
- + 
- + /* Used by PM_L3INIT_HSI_WKDEP */
- + #define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_SHIFT				1
- + #define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK				(1 << 1)
- + 
- + /* Used by PM_L3INIT_HSI_WKDEP */
- + #define OMAP4430_WKUPDEP_HSI_MCU_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_L4PER_I2C1_WKDEP */
- + #define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_SHIFT				7
- + #define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK				(1 << 7)
- + 
- + /* Used by PM_L4PER_I2C1_WKDEP */
- + #define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_SHIFT				1
- + #define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK				(1 << 1)
- + 
- + /* Used by PM_L4PER_I2C1_WKDEP */
- + #define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_L4PER_I2C2_WKDEP */
- + #define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_SHIFT				7
- + #define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK				(1 << 7)
- + 
- + /* Used by PM_L4PER_I2C2_WKDEP */
- + #define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_SHIFT				1
- + #define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK				(1 << 1)
- + 
- + /* Used by PM_L4PER_I2C2_WKDEP */
- + #define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_L4PER_I2C3_WKDEP */
- + #define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_SHIFT				7
- + #define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK				(1 << 7)
- + 
- + /* Used by PM_L4PER_I2C3_WKDEP */
- + #define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_SHIFT				1
- + #define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK				(1 << 1)
- + 
- + /* Used by PM_L4PER_I2C3_WKDEP */
- + #define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_L4PER_I2C4_WKDEP */
- + #define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_SHIFT				7
- + #define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK				(1 << 7)
- + 
- + /* Used by PM_L4PER_I2C4_WKDEP */
- + #define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_SHIFT				1
- + #define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK				(1 << 1)
- + 
- + /* Used by PM_L4PER_I2C4_WKDEP */
- + #define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_L4PER_I2C5_WKDEP */
- + #define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_SHIFT				7
- + #define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK				(1 << 7)
- + 
- + /* Used by PM_L4PER_I2C5_WKDEP */
- + #define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_WKUP_KEYBOARD_WKDEP */
- + #define OMAP4430_WKUPDEP_KEYBOARD_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_ABE_MCASP_WKDEP */
- + #define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_SHIFT				7
- + #define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK				(1 << 7)
- + 
- + /* Used by PM_ABE_MCASP_WKDEP */
- + #define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_SHIFT				6
- + #define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK				(1 << 6)
- + 
- + /* Used by PM_ABE_MCASP_WKDEP */
- + #define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_ABE_MCASP_WKDEP */
- + #define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_SHIFT				2
- + #define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK				(1 << 2)
- + 
- + /* Used by PM_L4PER_MCASP2_WKDEP */
- + #define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_SHIFT				7
- + #define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK				(1 << 7)
- + 
- + /* Used by PM_L4PER_MCASP2_WKDEP */
- + #define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_SHIFT				6
- + #define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK				(1 << 6)
- + 
- + /* Used by PM_L4PER_MCASP2_WKDEP */
- + #define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_L4PER_MCASP2_WKDEP */
- + #define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_SHIFT				2
- + #define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK				(1 << 2)
- + 
- + /* Used by PM_L4PER_MCASP3_WKDEP */
- + #define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_SHIFT				7
- + #define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK				(1 << 7)
- + 
- + /* Used by PM_L4PER_MCASP3_WKDEP */
- + #define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_SHIFT				6
- + #define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK				(1 << 6)
- + 
- + /* Used by PM_L4PER_MCASP3_WKDEP */
- + #define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_L4PER_MCASP3_WKDEP */
- + #define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_SHIFT				2
- + #define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK				(1 << 2)
- + 
- + /* Used by PM_ABE_MCBSP1_WKDEP */
- + #define OMAP4430_WKUPDEP_MCBSP1_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_ABE_MCBSP1_WKDEP */
- + #define OMAP4430_WKUPDEP_MCBSP1_SDMA_SHIFT				3
- + #define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK				(1 << 3)
- + 
- + /* Used by PM_ABE_MCBSP1_WKDEP */
- + #define OMAP4430_WKUPDEP_MCBSP1_TESLA_SHIFT				2
- + #define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK				(1 << 2)
- + 
- + /* Used by PM_ABE_MCBSP2_WKDEP */
- + #define OMAP4430_WKUPDEP_MCBSP2_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_ABE_MCBSP2_WKDEP */
- + #define OMAP4430_WKUPDEP_MCBSP2_SDMA_SHIFT				3
- + #define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK				(1 << 3)
- + 
- + /* Used by PM_ABE_MCBSP2_WKDEP */
- + #define OMAP4430_WKUPDEP_MCBSP2_TESLA_SHIFT				2
- + #define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK				(1 << 2)
- + 
- + /* Used by PM_ABE_MCBSP3_WKDEP */
- + #define OMAP4430_WKUPDEP_MCBSP3_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_ABE_MCBSP3_WKDEP */
- + #define OMAP4430_WKUPDEP_MCBSP3_SDMA_SHIFT				3
- + #define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK				(1 << 3)
- + 
- + /* Used by PM_ABE_MCBSP3_WKDEP */
- + #define OMAP4430_WKUPDEP_MCBSP3_TESLA_SHIFT				2
- + #define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK				(1 << 2)
- + 
- + /* Used by PM_L4PER_MCBSP4_WKDEP */
- + #define OMAP4430_WKUPDEP_MCBSP4_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_L4PER_MCBSP4_WKDEP */
- + #define OMAP4430_WKUPDEP_MCBSP4_SDMA_SHIFT				3
- + #define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK				(1 << 3)
- + 
- + /* Used by PM_L4PER_MCBSP4_WKDEP */
- + #define OMAP4430_WKUPDEP_MCBSP4_TESLA_SHIFT				2
- + #define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK				(1 << 2)
- + 
- + /* Used by PM_L4PER_MCSPI1_WKDEP */
- + #define OMAP4430_WKUPDEP_MCSPI1_DUCATI_SHIFT				1
- + #define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK				(1 << 1)
- + 
- + /* Used by PM_L4PER_MCSPI1_WKDEP */
- + #define OMAP4430_WKUPDEP_MCSPI1_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_L4PER_MCSPI1_WKDEP */
- + #define OMAP4430_WKUPDEP_MCSPI1_SDMA_SHIFT				3
- + #define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK				(1 << 3)
- + 
- + /* Used by PM_L4PER_MCSPI1_WKDEP */
- + #define OMAP4430_WKUPDEP_MCSPI1_TESLA_SHIFT				2
- + #define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK				(1 << 2)
- + 
- + /* Used by PM_L4PER_MCSPI2_WKDEP */
- + #define OMAP4430_WKUPDEP_MCSPI2_DUCATI_SHIFT				1
- + #define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK				(1 << 1)
- + 
- + /* Used by PM_L4PER_MCSPI2_WKDEP */
- + #define OMAP4430_WKUPDEP_MCSPI2_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_L4PER_MCSPI2_WKDEP */
- + #define OMAP4430_WKUPDEP_MCSPI2_SDMA_SHIFT				3
- + #define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK				(1 << 3)
- + 
- + /* Used by PM_L4PER_MCSPI3_WKDEP */
- + #define OMAP4430_WKUPDEP_MCSPI3_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_L4PER_MCSPI3_WKDEP */
- + #define OMAP4430_WKUPDEP_MCSPI3_SDMA_SHIFT				3
- + #define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK				(1 << 3)
- + 
- + /* Used by PM_L4PER_MCSPI4_WKDEP */
- + #define OMAP4430_WKUPDEP_MCSPI4_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_L4PER_MCSPI4_WKDEP */
- + #define OMAP4430_WKUPDEP_MCSPI4_SDMA_SHIFT				3
- + #define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK				(1 << 3)
- + 
- + /* Used by PM_L3INIT_MMC1_WKDEP */
- + #define OMAP4430_WKUPDEP_MMC1_DUCATI_SHIFT				1
- + #define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK				(1 << 1)
- + 
- + /* Used by PM_L3INIT_MMC1_WKDEP */
- + #define OMAP4430_WKUPDEP_MMC1_MPU_SHIFT					0
- + #define OMAP4430_WKUPDEP_MMC1_MPU_MASK					(1 << 0)
- + 
- + /* Used by PM_L3INIT_MMC1_WKDEP */
- + #define OMAP4430_WKUPDEP_MMC1_SDMA_SHIFT				3
- + #define OMAP4430_WKUPDEP_MMC1_SDMA_MASK					(1 << 3)
- + 
- + /* Used by PM_L3INIT_MMC1_WKDEP */
- + #define OMAP4430_WKUPDEP_MMC1_TESLA_SHIFT				2
- + #define OMAP4430_WKUPDEP_MMC1_TESLA_MASK				(1 << 2)
- + 
- + /* Used by PM_L3INIT_MMC2_WKDEP */
- + #define OMAP4430_WKUPDEP_MMC2_DUCATI_SHIFT				1
- + #define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK				(1 << 1)
- + 
- + /* Used by PM_L3INIT_MMC2_WKDEP */
- + #define OMAP4430_WKUPDEP_MMC2_MPU_SHIFT					0
- + #define OMAP4430_WKUPDEP_MMC2_MPU_MASK					(1 << 0)
- + 
- + /* Used by PM_L3INIT_MMC2_WKDEP */
- + #define OMAP4430_WKUPDEP_MMC2_SDMA_SHIFT				3
- + #define OMAP4430_WKUPDEP_MMC2_SDMA_MASK					(1 << 3)
- + 
- + /* Used by PM_L3INIT_MMC2_WKDEP */
- + #define OMAP4430_WKUPDEP_MMC2_TESLA_SHIFT				2
- + #define OMAP4430_WKUPDEP_MMC2_TESLA_MASK				(1 << 2)
- + 
- + /* Used by PM_L3INIT_MMC6_WKDEP */
- + #define OMAP4430_WKUPDEP_MMC6_DUCATI_SHIFT				1
- + #define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK				(1 << 1)
- + 
- + /* Used by PM_L3INIT_MMC6_WKDEP */
- + #define OMAP4430_WKUPDEP_MMC6_MPU_SHIFT					0
- + #define OMAP4430_WKUPDEP_MMC6_MPU_MASK					(1 << 0)
- + 
- + /* Used by PM_L3INIT_MMC6_WKDEP */
- + #define OMAP4430_WKUPDEP_MMC6_TESLA_SHIFT				2
- + #define OMAP4430_WKUPDEP_MMC6_TESLA_MASK				(1 << 2)
- + 
- + /* Used by PM_L4PER_MMCSD3_WKDEP */
- + #define OMAP4430_WKUPDEP_MMCSD3_DUCATI_SHIFT				1
- + #define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK				(1 << 1)
- + 
- + /* Used by PM_L4PER_MMCSD3_WKDEP */
- + #define OMAP4430_WKUPDEP_MMCSD3_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_L4PER_MMCSD3_WKDEP */
- + #define OMAP4430_WKUPDEP_MMCSD3_SDMA_SHIFT				3
- + #define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK				(1 << 3)
- + 
- + /* Used by PM_L4PER_MMCSD4_WKDEP */
- + #define OMAP4430_WKUPDEP_MMCSD4_DUCATI_SHIFT				1
- + #define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK				(1 << 1)
- + 
- + /* Used by PM_L4PER_MMCSD4_WKDEP */
- + #define OMAP4430_WKUPDEP_MMCSD4_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_L4PER_MMCSD4_WKDEP */
- + #define OMAP4430_WKUPDEP_MMCSD4_SDMA_SHIFT				3
- + #define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK				(1 << 3)
- + 
- + /* Used by PM_L4PER_MMCSD5_WKDEP */
- + #define OMAP4430_WKUPDEP_MMCSD5_DUCATI_SHIFT				1
- + #define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK				(1 << 1)
- + 
- + /* Used by PM_L4PER_MMCSD5_WKDEP */
- + #define OMAP4430_WKUPDEP_MMCSD5_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_L4PER_MMCSD5_WKDEP */
- + #define OMAP4430_WKUPDEP_MMCSD5_SDMA_SHIFT				3
- + #define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK				(1 << 3)
- + 
- + /* Used by PM_L3INIT_PCIESS_WKDEP */
- + #define OMAP4430_WKUPDEP_PCIESS_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_PCIESS_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_L3INIT_PCIESS_WKDEP */
- + #define OMAP4430_WKUPDEP_PCIESS_TESLA_SHIFT				2
- + #define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK				(1 << 2)
- + 
- + /* Used by PM_ABE_PDM_WKDEP */
- + #define OMAP4430_WKUPDEP_PDM_DMA_SDMA_SHIFT				7
- + #define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK				(1 << 7)
- + 
- + /* Used by PM_ABE_PDM_WKDEP */
- + #define OMAP4430_WKUPDEP_PDM_DMA_TESLA_SHIFT				6
- + #define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK				(1 << 6)
- + 
- + /* Used by PM_ABE_PDM_WKDEP */
- + #define OMAP4430_WKUPDEP_PDM_IRQ_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_ABE_PDM_WKDEP */
- + #define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_SHIFT				2
- + #define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK				(1 << 2)
- + 
- + /* Used by PM_WKUP_RTC_WKDEP */
- + #define OMAP4430_WKUPDEP_RTC_MPU_SHIFT					0
- + #define OMAP4430_WKUPDEP_RTC_MPU_MASK					(1 << 0)
- + 
- + /* Used by PM_L3INIT_SATA_WKDEP */
- + #define OMAP4430_WKUPDEP_SATA_MPU_SHIFT					0
- + #define OMAP4430_WKUPDEP_SATA_MPU_MASK					(1 << 0)
- + 
- + /* Used by PM_L3INIT_SATA_WKDEP */
- + #define OMAP4430_WKUPDEP_SATA_TESLA_SHIFT				2
- + #define OMAP4430_WKUPDEP_SATA_TESLA_MASK				(1 << 2)
- + 
- + /* Used by PM_ABE_SLIMBUS_WKDEP */
- + #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT			7
- + #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK				(1 << 7)
- + 
- + /* Used by PM_ABE_SLIMBUS_WKDEP */
- + #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_SHIFT			6
- + #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK			(1 << 6)
- + 
- + /* Used by PM_ABE_SLIMBUS_WKDEP */
- + #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_ABE_SLIMBUS_WKDEP */
- + #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_SHIFT			2
- + #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK			(1 << 2)
- + 
- + /* Used by PM_L4PER_SLIMBUS2_WKDEP */
- + #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_SHIFT			7
- + #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK				(1 << 7)
- + 
- + /* Used by PM_L4PER_SLIMBUS2_WKDEP */
- + #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_SHIFT			6
- + #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK			(1 << 6)
- + 
- + /* Used by PM_L4PER_SLIMBUS2_WKDEP */
- + #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_L4PER_SLIMBUS2_WKDEP */
- + #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_SHIFT			2
- + #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK			(1 << 2)
- + 
- + /* Used by PM_ALWON_SR_CORE_WKDEP */
- + #define OMAP4430_WKUPDEP_SR_CORE_DUCATI_SHIFT				1
- + #define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK				(1 << 1)
- + 
- + /* Used by PM_ALWON_SR_CORE_WKDEP */
- + #define OMAP4430_WKUPDEP_SR_CORE_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_ALWON_SR_IVA_WKDEP */
- + #define OMAP4430_WKUPDEP_SR_IVA_DUCATI_SHIFT				1
- + #define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK				(1 << 1)
- + 
- + /* Used by PM_ALWON_SR_IVA_WKDEP */
- + #define OMAP4430_WKUPDEP_SR_IVA_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_ALWON_SR_MPU_WKDEP */
- + #define OMAP4430_WKUPDEP_SR_MPU_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_WKUP_TIMER12_WKDEP */
- + #define OMAP4430_WKUPDEP_TIMER12_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_TIMER12_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_WKUP_TIMER1_WKDEP */
- + #define OMAP4430_WKUPDEP_TIMER1_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_TIMER1_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_ABE_TIMER5_WKDEP */
- + #define OMAP4430_WKUPDEP_TIMER5_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_TIMER5_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_ABE_TIMER5_WKDEP */
- + #define OMAP4430_WKUPDEP_TIMER5_TESLA_SHIFT				2
- + #define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK				(1 << 2)
- + 
- + /* Used by PM_ABE_TIMER6_WKDEP */
- + #define OMAP4430_WKUPDEP_TIMER6_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_TIMER6_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_ABE_TIMER6_WKDEP */
- + #define OMAP4430_WKUPDEP_TIMER6_TESLA_SHIFT				2
- + #define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK				(1 << 2)
- + 
- + /* Used by PM_ABE_TIMER7_WKDEP */
- + #define OMAP4430_WKUPDEP_TIMER7_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_TIMER7_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_ABE_TIMER7_WKDEP */
- + #define OMAP4430_WKUPDEP_TIMER7_TESLA_SHIFT				2
- + #define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK				(1 << 2)
- + 
- + /* Used by PM_ABE_TIMER8_WKDEP */
- + #define OMAP4430_WKUPDEP_TIMER8_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_TIMER8_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_ABE_TIMER8_WKDEP */
- + #define OMAP4430_WKUPDEP_TIMER8_TESLA_SHIFT				2
- + #define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK				(1 << 2)
- + 
- + /* Used by PM_L4PER_UART1_WKDEP */
- + #define OMAP4430_WKUPDEP_UART1_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_UART1_MPU_MASK					(1 << 0)
- + 
- + /* Used by PM_L4PER_UART1_WKDEP */
- + #define OMAP4430_WKUPDEP_UART1_SDMA_SHIFT				3
- + #define OMAP4430_WKUPDEP_UART1_SDMA_MASK				(1 << 3)
- + 
- + /* Used by PM_L4PER_UART2_WKDEP */
- + #define OMAP4430_WKUPDEP_UART2_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_UART2_MPU_MASK					(1 << 0)
- + 
- + /* Used by PM_L4PER_UART2_WKDEP */
- + #define OMAP4430_WKUPDEP_UART2_SDMA_SHIFT				3
- + #define OMAP4430_WKUPDEP_UART2_SDMA_MASK				(1 << 3)
- + 
- + /* Used by PM_L4PER_UART3_WKDEP */
- + #define OMAP4430_WKUPDEP_UART3_DUCATI_SHIFT				1
- + #define OMAP4430_WKUPDEP_UART3_DUCATI_MASK				(1 << 1)
- + 
- + /* Used by PM_L4PER_UART3_WKDEP */
- + #define OMAP4430_WKUPDEP_UART3_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_UART3_MPU_MASK					(1 << 0)
- + 
- + /* Used by PM_L4PER_UART3_WKDEP */
- + #define OMAP4430_WKUPDEP_UART3_SDMA_SHIFT				3
- + #define OMAP4430_WKUPDEP_UART3_SDMA_MASK				(1 << 3)
- + 
- + /* Used by PM_L4PER_UART3_WKDEP */
- + #define OMAP4430_WKUPDEP_UART3_TESLA_SHIFT				2
- + #define OMAP4430_WKUPDEP_UART3_TESLA_MASK				(1 << 2)
- + 
- + /* Used by PM_L4PER_UART4_WKDEP */
- + #define OMAP4430_WKUPDEP_UART4_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_UART4_MPU_MASK					(1 << 0)
- + 
- + /* Used by PM_L4PER_UART4_WKDEP */
- + #define OMAP4430_WKUPDEP_UART4_SDMA_SHIFT				3
- + #define OMAP4430_WKUPDEP_UART4_SDMA_MASK				(1 << 3)
- + 
- + /* Used by PM_L3INIT_UNIPRO1_WKDEP */
- + #define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_SHIFT				1
- + #define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK				(1 << 1)
- + 
- + /* Used by PM_L3INIT_UNIPRO1_WKDEP */
- + #define OMAP4430_WKUPDEP_UNIPRO1_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_L3INIT_USB_HOST_WKDEP */
- + #define OMAP4430_WKUPDEP_USB_HOST_DUCATI_SHIFT				1
- + #define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK				(1 << 1)
- + 
- + /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */
- + #define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_SHIFT			1
- + #define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK			(1 << 1)
- + 
- + /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */
- + #define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_L3INIT_USB_HOST_WKDEP */
- + #define OMAP4430_WKUPDEP_USB_HOST_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_L3INIT_USB_OTG_WKDEP */
- + #define OMAP4430_WKUPDEP_USB_OTG_DUCATI_SHIFT				1
- + #define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK				(1 << 1)
- + 
- + /* Used by PM_L3INIT_USB_OTG_WKDEP */
- + #define OMAP4430_WKUPDEP_USB_OTG_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_L3INIT_USB_TLL_WKDEP */
- + #define OMAP4430_WKUPDEP_USB_TLL_DUCATI_SHIFT				1
- + #define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK				(1 << 1)
- + 
- + /* Used by PM_L3INIT_USB_TLL_WKDEP */
- + #define OMAP4430_WKUPDEP_USB_TLL_MPU_SHIFT				0
- + #define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK				(1 << 0)
- + 
- + /* Used by PM_WKUP_USIM_WKDEP */
- + #define OMAP4430_WKUPDEP_USIM_MPU_SHIFT					0
- + #define OMAP4430_WKUPDEP_USIM_MPU_MASK					(1 << 0)
- + 
- + /* Used by PM_WKUP_USIM_WKDEP */
- + #define OMAP4430_WKUPDEP_USIM_SDMA_SHIFT				3
- + #define OMAP4430_WKUPDEP_USIM_SDMA_MASK					(1 << 3)
- + 
- + /* Used by PM_WKUP_WDT2_WKDEP */
- + #define OMAP4430_WKUPDEP_WDT2_DUCATI_SHIFT				1
- + #define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK				(1 << 1)
- + 
- + /* Used by PM_WKUP_WDT2_WKDEP */
- + #define OMAP4430_WKUPDEP_WDT2_MPU_SHIFT					0
- + #define OMAP4430_WKUPDEP_WDT2_MPU_MASK					(1 << 0)
- + 
- + /* Used by PM_ABE_WDT3_WKDEP */
- + #define OMAP4430_WKUPDEP_WDT3_MPU_SHIFT					0
- + #define OMAP4430_WKUPDEP_WDT3_MPU_MASK					(1 << 0)
- + 
- + /* Used by PM_L3INIT_HSI_WKDEP */
- + #define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_SHIFT				8
- + #define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK				(1 << 8)
- + 
- + /* Used by PM_L3INIT_XHPI_WKDEP */
- + #define OMAP4430_WKUPDEP_XHPI_DUCATI_SHIFT				1
- + #define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK				(1 << 1)
- + 
- + /* Used by PRM_IO_PMCTRL */
- + #define OMAP4430_WUCLK_CTRL_SHIFT					8
- + #define OMAP4430_WUCLK_CTRL_MASK					(1 << 8)
- + 
- + /* Used by PRM_IO_PMCTRL */
- + #define OMAP4430_WUCLK_STATUS_SHIFT					9
- + #define OMAP4430_WUCLK_STATUS_MASK					(1 << 9)
- + 
- + /* Used by REVISION_PRM */
- + #define OMAP4430_X_MAJOR_SHIFT						8
- + #define OMAP4430_X_MAJOR_MASK						(0x7 << 8)
- + 
- + /* Used by REVISION_PRM */
- + #define OMAP4430_Y_MINOR_SHIFT						0
- + #define OMAP4430_Y_MINOR_MASK						(0x3f << 0)
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/scrm44xx.h linux-3.2.1/arch/arm/mach-ckb_3352/scrm44xx.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/scrm44xx.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/scrm44xx.h	2014-05-15 13:25:13.999143414 +0900
- ***************
- *** 0 ****
- --- 1,175 ----
- + /*
- +  * OMAP44xx SCRM registers and bitfields
- +  *
- +  * Copyright (C) 2010 Texas Instruments, Inc.
- +  *
- +  * Benoit Cousson (b-cousson@ti.com)
- +  *
- +  * This file is automatically generated from the OMAP hardware databases.
- +  * We respectfully ask that any modifications to this file be coordinated
- +  * with the public linux-omap@vger.kernel.org mailing list and the
- +  * authors above to ensure that the autogeneration scripts are kept
- +  * up-to-date with the file contents.
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #ifndef __ARCH_ARM_MACH_OMAP2_SCRM_44XX_H
- + #define __ARCH_ARM_MACH_OMAP2_SCRM_44XX_H
- + 
- + #define OMAP4_SCRM_BASE				0x4a30a000
- + 
- + #define OMAP44XX_SCRM_REGADDR(reg)	\
- + 		OMAP2_L4_IO_ADDRESS(OMAP4_SCRM_BASE + (reg))
- + 
- + /* Registers offset */
- + #define OMAP4_SCRM_REVISION_SCRM_OFFSET		0x0000
- + #define OMAP4_SCRM_REVISION_SCRM		OMAP44XX_SCRM_REGADDR(0x0000)
- + #define OMAP4_SCRM_CLKSETUPTIME_OFFSET		0x0100
- + #define OMAP4_SCRM_CLKSETUPTIME			OMAP44XX_SCRM_REGADDR(0x0100)
- + #define OMAP4_SCRM_PMICSETUPTIME_OFFSET		0x0104
- + #define OMAP4_SCRM_PMICSETUPTIME		OMAP44XX_SCRM_REGADDR(0x0104)
- + #define OMAP4_SCRM_ALTCLKSRC_OFFSET		0x0110
- + #define OMAP4_SCRM_ALTCLKSRC			OMAP44XX_SCRM_REGADDR(0x0110)
- + #define OMAP4_SCRM_MODEMCLKM_OFFSET		0x0118
- + #define OMAP4_SCRM_MODEMCLKM			OMAP44XX_SCRM_REGADDR(0x0118)
- + #define OMAP4_SCRM_D2DCLKM_OFFSET		0x011c
- + #define OMAP4_SCRM_D2DCLKM			OMAP44XX_SCRM_REGADDR(0x011c)
- + #define OMAP4_SCRM_EXTCLKREQ_OFFSET		0x0200
- + #define OMAP4_SCRM_EXTCLKREQ			OMAP44XX_SCRM_REGADDR(0x0200)
- + #define OMAP4_SCRM_ACCCLKREQ_OFFSET		0x0204
- + #define OMAP4_SCRM_ACCCLKREQ			OMAP44XX_SCRM_REGADDR(0x0204)
- + #define OMAP4_SCRM_PWRREQ_OFFSET		0x0208
- + #define OMAP4_SCRM_PWRREQ			OMAP44XX_SCRM_REGADDR(0x0208)
- + #define OMAP4_SCRM_AUXCLKREQ0_OFFSET		0x0210
- + #define OMAP4_SCRM_AUXCLKREQ0			OMAP44XX_SCRM_REGADDR(0x0210)
- + #define OMAP4_SCRM_AUXCLKREQ1_OFFSET		0x0214
- + #define OMAP4_SCRM_AUXCLKREQ1			OMAP44XX_SCRM_REGADDR(0x0214)
- + #define OMAP4_SCRM_AUXCLKREQ2_OFFSET		0x0218
- + #define OMAP4_SCRM_AUXCLKREQ2			OMAP44XX_SCRM_REGADDR(0x0218)
- + #define OMAP4_SCRM_AUXCLKREQ3_OFFSET		0x021c
- + #define OMAP4_SCRM_AUXCLKREQ3			OMAP44XX_SCRM_REGADDR(0x021c)
- + #define OMAP4_SCRM_AUXCLKREQ4_OFFSET		0x0220
- + #define OMAP4_SCRM_AUXCLKREQ4			OMAP44XX_SCRM_REGADDR(0x0220)
- + #define OMAP4_SCRM_AUXCLKREQ5_OFFSET		0x0224
- + #define OMAP4_SCRM_AUXCLKREQ5			OMAP44XX_SCRM_REGADDR(0x0224)
- + #define OMAP4_SCRM_D2DCLKREQ_OFFSET		0x0234
- + #define OMAP4_SCRM_D2DCLKREQ			OMAP44XX_SCRM_REGADDR(0x0234)
- + #define OMAP4_SCRM_AUXCLK0_OFFSET		0x0310
- + #define OMAP4_SCRM_AUXCLK0			OMAP44XX_SCRM_REGADDR(0x0310)
- + #define OMAP4_SCRM_AUXCLK1_OFFSET		0x0314
- + #define OMAP4_SCRM_AUXCLK1			OMAP44XX_SCRM_REGADDR(0x0314)
- + #define OMAP4_SCRM_AUXCLK2_OFFSET		0x0318
- + #define OMAP4_SCRM_AUXCLK2			OMAP44XX_SCRM_REGADDR(0x0318)
- + #define OMAP4_SCRM_AUXCLK3_OFFSET		0x031c
- + #define OMAP4_SCRM_AUXCLK3			OMAP44XX_SCRM_REGADDR(0x031c)
- + #define OMAP4_SCRM_AUXCLK4_OFFSET		0x0320
- + #define OMAP4_SCRM_AUXCLK4			OMAP44XX_SCRM_REGADDR(0x0320)
- + #define OMAP4_SCRM_AUXCLK5_OFFSET		0x0324
- + #define OMAP4_SCRM_AUXCLK5			OMAP44XX_SCRM_REGADDR(0x0324)
- + #define OMAP4_SCRM_RSTTIME_OFFSET		0x0400
- + #define OMAP4_SCRM_RSTTIME			OMAP44XX_SCRM_REGADDR(0x0400)
- + #define OMAP4_SCRM_MODEMRSTCTRL_OFFSET		0x0418
- + #define OMAP4_SCRM_MODEMRSTCTRL			OMAP44XX_SCRM_REGADDR(0x0418)
- + #define OMAP4_SCRM_D2DRSTCTRL_OFFSET		0x041c
- + #define OMAP4_SCRM_D2DRSTCTRL			OMAP44XX_SCRM_REGADDR(0x041c)
- + #define OMAP4_SCRM_EXTPWRONRSTCTRL_OFFSET	0x0420
- + #define OMAP4_SCRM_EXTPWRONRSTCTRL		OMAP44XX_SCRM_REGADDR(0x0420)
- + #define OMAP4_SCRM_EXTWARMRSTST_OFFSET		0x0510
- + #define OMAP4_SCRM_EXTWARMRSTST			OMAP44XX_SCRM_REGADDR(0x0510)
- + #define OMAP4_SCRM_APEWARMRSTST_OFFSET		0x0514
- + #define OMAP4_SCRM_APEWARMRSTST			OMAP44XX_SCRM_REGADDR(0x0514)
- + #define OMAP4_SCRM_MODEMWARMRSTST_OFFSET	0x0518
- + #define OMAP4_SCRM_MODEMWARMRSTST		OMAP44XX_SCRM_REGADDR(0x0518)
- + #define OMAP4_SCRM_D2DWARMRSTST_OFFSET		0x051c
- + #define OMAP4_SCRM_D2DWARMRSTST			OMAP44XX_SCRM_REGADDR(0x051c)
- + 
- + /* Registers shifts and masks */
- + 
- + /* REVISION_SCRM */
- + #define OMAP4_REV_SHIFT				0
- + #define OMAP4_REV_MASK				(0xff << 0)
- + 
- + /* CLKSETUPTIME */
- + #define OMAP4_DOWNTIME_SHIFT			16
- + #define OMAP4_DOWNTIME_MASK			(0x3f << 16)
- + #define OMAP4_SETUPTIME_SHIFT			0
- + #define OMAP4_SETUPTIME_MASK			(0xfff << 0)
- + 
- + /* PMICSETUPTIME */
- + #define OMAP4_WAKEUPTIME_SHIFT			16
- + #define OMAP4_WAKEUPTIME_MASK			(0x3f << 16)
- + #define OMAP4_SLEEPTIME_SHIFT			0
- + #define OMAP4_SLEEPTIME_MASK			(0x3f << 0)
- + 
- + /* ALTCLKSRC */
- + #define OMAP4_ENABLE_EXT_SHIFT			3
- + #define OMAP4_ENABLE_EXT_MASK			(1 << 3)
- + #define OMAP4_ENABLE_INT_SHIFT			2
- + #define OMAP4_ENABLE_INT_MASK			(1 << 2)
- + #define OMAP4_ALTCLKSRC_MODE_SHIFT		0
- + #define OMAP4_ALTCLKSRC_MODE_MASK		(0x3 << 0)
- + 
- + /* MODEMCLKM */
- + #define OMAP4_CLK_32KHZ_SHIFT			0
- + #define OMAP4_CLK_32KHZ_MASK			(1 << 0)
- + 
- + /* D2DCLKM */
- + #define OMAP4_SYSCLK_SHIFT			1
- + #define OMAP4_SYSCLK_MASK			(1 << 1)
- + 
- + /* EXTCLKREQ */
- + #define OMAP4_POLARITY_SHIFT			0
- + #define OMAP4_POLARITY_MASK			(1 << 0)
- + 
- + /* AUXCLKREQ0 */
- + #define OMAP4_MAPPING_SHIFT			2
- + #define OMAP4_MAPPING_MASK			(0x7 << 2)
- + #define OMAP4_ACCURACY_SHIFT			1
- + #define OMAP4_ACCURACY_MASK			(1 << 1)
- + 
- + /* AUXCLK0 */
- + #define OMAP4_CLKDIV_SHIFT			16
- + #define OMAP4_CLKDIV_MASK			(0xf << 16)
- + #define OMAP4_DISABLECLK_SHIFT			9
- + #define OMAP4_DISABLECLK_MASK			(1 << 9)
- + #define OMAP4_ENABLE_SHIFT			8
- + #define OMAP4_ENABLE_MASK			(1 << 8)
- + #define OMAP4_SRCSELECT_SHIFT			1
- + #define OMAP4_SRCSELECT_MASK			(0x3 << 1)
- + 
- + /* RSTTIME */
- + #define OMAP4_RSTTIME_SHIFT			0
- + #define OMAP4_RSTTIME_MASK			(0xf << 0)
- + 
- + /* MODEMRSTCTRL */
- + #define OMAP4_WARMRST_SHIFT			1
- + #define OMAP4_WARMRST_MASK			(1 << 1)
- + #define OMAP4_COLDRST_SHIFT			0
- + #define OMAP4_COLDRST_MASK			(1 << 0)
- + 
- + /* EXTPWRONRSTCTRL */
- + #define OMAP4_PWRONRST_SHIFT			1
- + #define OMAP4_PWRONRST_MASK			(1 << 1)
- + #define OMAP4_ENABLE_EXTPWRONRSTCTRL_SHIFT	0
- + #define OMAP4_ENABLE_EXTPWRONRSTCTRL_MASK	(1 << 0)
- + 
- + /* EXTWARMRSTST */
- + #define OMAP4_EXTWARMRSTST_SHIFT		0
- + #define OMAP4_EXTWARMRSTST_MASK			(1 << 0)
- + 
- + /* APEWARMRSTST */
- + #define OMAP4_APEWARMRSTST_SHIFT		1
- + #define OMAP4_APEWARMRSTST_MASK			(1 << 1)
- + 
- + /* MODEMWARMRSTST */
- + #define OMAP4_MODEMWARMRSTST_SHIFT		2
- + #define OMAP4_MODEMWARMRSTST_MASK		(1 << 2)
- + 
- + /* D2DWARMRSTST */
- + #define OMAP4_D2DWARMRSTST_SHIFT		3
- + #define OMAP4_D2DWARMRSTST_MASK			(1 << 3)
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/sdrc.c linux-3.2.1/arch/arm/mach-ckb_3352/sdrc.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/sdrc.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/sdrc.c	2014-05-15 13:25:13.999143414 +0900
- ***************
- *** 0 ****
- --- 1,178 ----
- + /*
- +  * SMS/SDRC (SDRAM controller) common code for OMAP2/3
- +  *
- +  * Copyright (C) 2005, 2008 Texas Instruments Inc.
- +  * Copyright (C) 2005, 2008 Nokia Corporation
- +  *
- +  * Tony Lindgren <tony@atomide.com>
- +  * Paul Walmsley
- +  * Richard Woodruff <r-woodruff2@ti.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + #undef DEBUG
- + 
- + #include <linux/module.h>
- + #include <linux/kernel.h>
- + #include <linux/device.h>
- + #include <linux/list.h>
- + #include <linux/errno.h>
- + #include <linux/delay.h>
- + #include <linux/clk.h>
- + #include <linux/io.h>
- + 
- + #include "common.h"
- + #include <plat/clock.h>
- + #include <plat/sram.h>
- + 
- + #include <plat/sdrc.h>
- + #include "sdrc.h"
- + 
- + static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1;
- + 
- + void __iomem *omap2_sdrc_base;
- + void __iomem *omap2_sms_base;
- + 
- + struct omap2_sms_regs {
- + 	u32	sms_sysconfig;
- + };
- + 
- + static struct omap2_sms_regs sms_context;
- + 
- + /* SDRC_POWER register bits */
- + #define SDRC_POWER_EXTCLKDIS_SHIFT		3
- + #define SDRC_POWER_PWDENA_SHIFT			2
- + #define SDRC_POWER_PAGEPOLICY_SHIFT		0
- + 
- + /**
- +  * omap2_sms_save_context - Save SMS registers
- +  *
- +  * Save SMS registers that need to be restored after off mode.
- +  */
- + void omap2_sms_save_context(void)
- + {
- + 	sms_context.sms_sysconfig = sms_read_reg(SMS_SYSCONFIG);
- + }
- + 
- + /**
- +  * omap2_sms_restore_context - Restore SMS registers
- +  *
- +  * Restore SMS registers that need to be Restored after off mode.
- +  */
- + void omap2_sms_restore_context(void)
- + {
- + 	sms_write_reg(sms_context.sms_sysconfig, SMS_SYSCONFIG);
- + }
- + 
- + /**
- +  * omap2_sdrc_get_params - return SDRC register values for a given clock rate
- +  * @r: SDRC clock rate (in Hz)
- +  * @sdrc_cs0: chip select 0 ram timings **
- +  * @sdrc_cs1: chip select 1 ram timings **
- +  *
- +  * Return pre-calculated values for the SDRC_ACTIM_CTRLA,
- +  *  SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in sdrc_cs[01]
- +  *  structs,for a given SDRC clock rate 'r'.
- +  * These parameters control various timing delays in the SDRAM controller
- +  *  that are expressed in terms of the number of SDRC clock cycles to
- +  *  wait; hence the clock rate dependency.
- +  *
- +  * Supports 2 different timing parameters for both chip selects.
- +  *
- +  * Note 1: the sdrc_init_params_cs[01] must be sorted rate descending.
- +  * Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same size
- +  *  as sdrc_init_params_cs_0.
- +  *
- +  * Fills in the struct omap_sdrc_params * for each chip select.
- +  * Returns 0 upon success or -1 upon failure.
- +  */
- + int omap2_sdrc_get_params(unsigned long r,
- + 			  struct omap_sdrc_params **sdrc_cs0,
- + 			  struct omap_sdrc_params **sdrc_cs1)
- + {
- + 	struct omap_sdrc_params *sp0, *sp1;
- + 
- + 	if (!sdrc_init_params_cs0)
- + 		return -1;
- + 
- + 	sp0 = sdrc_init_params_cs0;
- + 	sp1 = sdrc_init_params_cs1;
- + 
- + 	while (sp0->rate && sp0->rate != r) {
- + 		sp0++;
- + 		if (sdrc_init_params_cs1)
- + 			sp1++;
- + 	}
- + 
- + 	if (!sp0->rate)
- + 		return -1;
- + 
- + 	*sdrc_cs0 = sp0;
- + 	*sdrc_cs1 = sp1;
- + 	return 0;
- + }
- + 
- + 
- + void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals)
- + {
- + 	if (omap2_globals->sdrc)
- + 		omap2_sdrc_base = omap2_globals->sdrc;
- + 	if (omap2_globals->sms)
- + 		omap2_sms_base = omap2_globals->sms;
- + }
- + 
- + /**
- +  * omap2_sdrc_init - initialize SMS, SDRC devices on boot
- +  * @sdrc_cs[01]: pointers to a null-terminated list of struct omap_sdrc_params
- +  *  Support for 2 chip selects timings
- +  *
- +  * Turn on smart idle modes for SDRAM scheduler and controller.
- +  * Program a known-good configuration for the SDRC to deal with buggy
- +  * bootloaders.
- +  */
- + void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
- + 			    struct omap_sdrc_params *sdrc_cs1)
- + {
- + 	u32 l;
- + 
- + 	l = sms_read_reg(SMS_SYSCONFIG);
- + 	l &= ~(0x3 << 3);
- + 	l |= (0x2 << 3);
- + 	sms_write_reg(l, SMS_SYSCONFIG);
- + 
- + 	l = sdrc_read_reg(SDRC_SYSCONFIG);
- + 	l &= ~(0x3 << 3);
- + 	l |= (0x2 << 3);
- + 	sdrc_write_reg(l, SDRC_SYSCONFIG);
- + 
- + 	sdrc_init_params_cs0 = sdrc_cs0;
- + 	sdrc_init_params_cs1 = sdrc_cs1;
- + 
- + 	/* XXX Enable SRFRONIDLEREQ here also? */
- + 	/*
- + 	 * PWDENA should not be set due to 34xx erratum 1.150 - PWDENA
- + 	 * can cause random memory corruption
- + 	 */
- + 	l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
- + 		(1 << SDRC_POWER_PAGEPOLICY_SHIFT);
- + 	sdrc_write_reg(l, SDRC_POWER);
- + 	omap2_sms_save_context();
- + }
- + 
- + void omap2_sms_write_rot_control(u32 val, unsigned ctx)
- + {
- + 	sms_write_reg(val, SMS_ROT_CONTROL(ctx));
- + }
- + 
- + void omap2_sms_write_rot_size(u32 val, unsigned ctx)
- + {
- + 	sms_write_reg(val, SMS_ROT_SIZE(ctx));
- + }
- + 
- + void omap2_sms_write_rot_physical_ba(u32 val, unsigned ctx)
- + {
- + 	sms_write_reg(val, SMS_ROT_PHYSICAL_BA(ctx));
- + }
- + 
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/sdrc.h linux-3.2.1/arch/arm/mach-ckb_3352/sdrc.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/sdrc.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/sdrc.h	2014-05-15 13:25:13.999143414 +0900
- ***************
- *** 0 ****
- --- 1,70 ----
- + #ifndef __ARCH_ARM_MACH_OMAP2_SDRC_H
- + #define __ARCH_ARM_MACH_OMAP2_SDRC_H
- + 
- + /*
- +  * OMAP2 SDRC register definitions
- +  *
- +  * Copyright (C) 2007 Texas Instruments, Inc.
- +  * Copyright (C) 2007 Nokia Corporation
- +  *
- +  * Written by Paul Walmsley
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + #undef DEBUG
- + 
- + #include <plat/sdrc.h>
- + 
- + #ifndef __ASSEMBLER__
- + 
- + #include <linux/io.h>
- + 
- + extern void __iomem *omap2_sdrc_base;
- + extern void __iomem *omap2_sms_base;
- + 
- + #define OMAP_SDRC_REGADDR(reg)			(omap2_sdrc_base + (reg))
- + #define OMAP_SMS_REGADDR(reg)			(omap2_sms_base + (reg))
- + 
- + /* SDRC global register get/set */
- + 
- + static inline void sdrc_write_reg(u32 val, u16 reg)
- + {
- + 	__raw_writel(val, OMAP_SDRC_REGADDR(reg));
- + }
- + 
- + static inline u32 sdrc_read_reg(u16 reg)
- + {
- + 	return __raw_readl(OMAP_SDRC_REGADDR(reg));
- + }
- + 
- + /* SMS global register get/set */
- + 
- + static inline void sms_write_reg(u32 val, u16 reg)
- + {
- + 	__raw_writel(val, OMAP_SMS_REGADDR(reg));
- + }
- + 
- + static inline u32 sms_read_reg(u16 reg)
- + {
- + 	return __raw_readl(OMAP_SMS_REGADDR(reg));
- + }
- + #else
- + #define OMAP34XX_SDRC_REGADDR(reg)					\
- + 			OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
- + #endif	/* __ASSEMBLER__ */
- + 
- + /* Minimum frequency that the SDRC DLL can lock at */
- + #define MIN_SDRC_DLL_LOCK_FREQ		83000000
- + 
- + /* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */
- + #define SDRC_MPURATE_BASE_SHIFT		9
- + 
- + /*
- +  * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at
- +  * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize
- +  */
- + #define SDRC_MPURATE_LOOPS		96
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/serial.c linux-3.2.1/arch/arm/mach-ckb_3352/serial.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/serial.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/serial.c	2014-05-15 13:25:13.999143414 +0900
- ***************
- *** 0 ****
- --- 1,299 ----
- + /*
- +  * arch/arm/mach-omap2/serial.c
- +  *
- +  * OMAP2 serial support.
- +  *
- +  * Copyright (C) 2005-2008 Nokia Corporation
- +  * Author: Paul Mundt <paul.mundt@nokia.com>
- +  *
- +  * Major rework for PM support by Kevin Hilman
- +  *
- +  * Based off of arch/arm/mach-omap/omap1/serial.c
- +  *
- +  * Copyright (C) 2009 Texas Instruments
- +  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
- +  *
- +  * This file is subject to the terms and conditions of the GNU General Public
- +  * License. See the file "COPYING" in the main directory of this archive
- +  * for more details.
- +  */
- + #include <linux/kernel.h>
- + #include <linux/init.h>
- + #include <linux/clk.h>
- + #include <linux/io.h>
- + #include <linux/delay.h>
- + #include <linux/platform_device.h>
- + #include <linux/slab.h>
- + #include <linux/pm_runtime.h>
- + #include <linux/console.h>
- + 
- + #include <plat/omap-serial.h>
- + #include "common.h"
- + #include <plat/board.h>
- + #include <plat/dma.h>
- + #include <plat/omap_hwmod.h>
- + #include <plat/omap_device.h>
- + #include <plat/omap-pm.h>
- + 
- + #include "prm2xxx_3xxx.h"
- + #include "pm.h"
- + #include "cm2xxx_3xxx.h"
- + #include "prm-regbits-34xx.h"
- + #include "control.h"
- + #include "mux.h"
- + 
- + /*
- +  * NOTE: By default the serial auto_suspend timeout is disabled as it causes
- +  * lost characters over the serial ports. This means that the UART clocks will
- +  * stay on until power/autosuspend_delay is set for the uart from sysfs.
- +  * This also causes that any deeper omap sleep states are blocked.
- +  */
- + #define DEFAULT_AUTOSUSPEND_DELAY	-1
- + 
- + #define MAX_UART_HWMOD_NAME_LEN		16
- + 
- + struct omap_uart_state {
- + 	int num;
- + 	int can_sleep;
- + 
- + 	struct list_head node;
- + 	struct omap_hwmod *oh;
- + 	struct platform_device *pdev;
- + };
- + 
- + static LIST_HEAD(uart_list);
- + static u8 num_uarts;
- + static u8 console_uart_id = -1;
- + static u8 no_console_suspend;
- + static u8 uart_debug;
- + 
- + #define DEFAULT_RXDMA_POLLRATE		1	/* RX DMA polling rate (us) */
- + #define DEFAULT_RXDMA_BUFSIZE		4096	/* RX DMA buffer size */
- + #define DEFAULT_RXDMA_TIMEOUT		(3 * HZ)/* RX DMA timeout (jiffies) */
- + 
- + static struct omap_uart_port_info omap_serial_default_info[] __initdata = {
- + 	{
- + 		.dma_enabled	= false,
- + 		.dma_rx_buf_size = DEFAULT_RXDMA_BUFSIZE,
- + 		.dma_rx_poll_rate = DEFAULT_RXDMA_POLLRATE,
- + 		.dma_rx_timeout = DEFAULT_RXDMA_TIMEOUT,
- + 		.autosuspend_timeout = DEFAULT_AUTOSUSPEND_DELAY,
- + 	},
- + };
- + 
- + #ifdef CONFIG_PM
- + static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable)
- + {
- + 	struct omap_device *od = to_omap_device(pdev);
- + 
- + 	if (!od)
- + 		return;
- + 
- + 	if (enable)
- + 		omap_hwmod_enable_wakeup(od->hwmods[0]);
- + 	else
- + 		omap_hwmod_disable_wakeup(od->hwmods[0]);
- + }
- + 
- + /*
- +  * Errata i291: [UART]:Cannot Acknowledge Idle Requests
- +  * in Smartidle Mode When Configured for DMA Operations.
- +  * WA: configure uart in force idle mode.
- +  */
- + static void omap_uart_set_noidle(struct platform_device *pdev)
- + {
- + 	struct omap_device *od = to_omap_device(pdev);
- + 
- + 	omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_NO);
- + }
- + 
- + static void omap_uart_set_forceidle(struct platform_device *pdev)
- + {
- + 	struct omap_device *od = to_omap_device(pdev);
- + 
- + 	omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_FORCE);
- + }
- + 
- + #else
- + static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable)
- + {}
- + static void omap_uart_set_noidle(struct platform_device *pdev) {}
- + static void omap_uart_set_forceidle(struct platform_device *pdev) {}
- + #endif /* CONFIG_PM */
- + 
- + char *cmdline_find_option(char *str)
- + {
- + 	extern char *saved_command_line;
- + 
- + 	return strstr(saved_command_line, str);
- + }
- + 
- + static int __init omap_serial_early_init(void)
- + {
- + 	do {
- + 		char oh_name[MAX_UART_HWMOD_NAME_LEN];
- + 		struct omap_hwmod *oh;
- + 		struct omap_uart_state *uart;
- + 		char uart_name[MAX_UART_HWMOD_NAME_LEN];
- + 
- + 		snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN,
- + 			 "uart%d", num_uarts + 1);
- + 		oh = omap_hwmod_lookup(oh_name);
- + 		if (!oh)
- + 			break;
- + 
- + 		uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL);
- + 		if (WARN_ON(!uart))
- + 			return -ENODEV;
- + 
- + 		uart->oh = oh;
- + 		uart->num = num_uarts++;
- + 		list_add_tail(&uart->node, &uart_list);
- + 		snprintf(uart_name, MAX_UART_HWMOD_NAME_LEN,
- + 				"%s%d", OMAP_SERIAL_NAME, uart->num);
- + 
- + 		if (cmdline_find_option(uart_name)) {
- + 			console_uart_id = uart->num;
- + 
- + 			if (console_loglevel >= 10) {
- + 				uart_debug = true;
- + 				pr_info("%s used as console in debug mode"
- + 						" uart%d clocks will not be"
- + 						" gated", uart_name, uart->num);
- + 			}
- + 
- + 			if (cmdline_find_option("no_console_suspend"))
- + 				no_console_suspend = true;
- + 
- + 			/*
- + 			 * omap-uart can be used for earlyprintk logs
- + 			 * So if omap-uart is used as console then prevent
- + 			 * uart reset and idle to get logs from omap-uart
- + 			 * until uart console driver is available to take
- + 			 * care for console messages.
- + 			 * Idling or resetting omap-uart while printing logs
- + 			 * early boot logs can stall the boot-up.
- + 			 */
- + 			oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET;
- + 		}
- + 	} while (1);
- + 
- + 	return 0;
- + }
- + core_initcall(omap_serial_early_init);
- + 
- + /**
- +  * omap_serial_init_port() - initialize single serial port
- +  * @bdata: port specific board data pointer
- +  * @info: platform specific data pointer
- +  *
- +  * This function initialies serial driver for given port only.
- +  * Platforms can call this function instead of omap_serial_init()
- +  * if they don't plan to use all available UARTs as serial ports.
- +  *
- +  * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
- +  * use only one of the two.
- +  */
- + void __init omap_serial_init_port(struct omap_board_data *bdata,
- + 			struct omap_uart_port_info *info)
- + {
- + 	struct omap_uart_state *uart;
- + 	struct omap_hwmod *oh;
- + 	struct platform_device *pdev;
- + 	void *pdata = NULL;
- + 	u32 pdata_size = 0;
- + 	char *name;
- + 	struct omap_uart_port_info omap_up;
- + 
- + 	if (WARN_ON(!bdata))
- + 		return;
- + 	if (WARN_ON(bdata->id < 0))
- + 		return;
- + 	if (WARN_ON(bdata->id >= num_uarts))
- + 		return;
- + 
- + 	list_for_each_entry(uart, &uart_list, node)
- + 		if (bdata->id == uart->num)
- + 			break;
- + 	if (!info)
- + 		info = omap_serial_default_info;
- + 
- + 	oh = uart->oh;
- + 	name = DRIVER_NAME;
- + 
- + 	omap_up.dma_enabled = info->dma_enabled;
- + 	omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
- + 	omap_up.flags = UPF_BOOT_AUTOCONF;
- + 	omap_up.get_context_loss_count = omap_pm_get_dev_context_loss_count;
- + 	omap_up.set_forceidle = omap_uart_set_forceidle;
- + 	omap_up.set_noidle = omap_uart_set_noidle;
- + 	omap_up.enable_wakeup = omap_uart_enable_wakeup;
- + 	omap_up.dma_rx_buf_size = info->dma_rx_buf_size;
- + 	omap_up.dma_rx_timeout = info->dma_rx_timeout;
- + 	omap_up.dma_rx_poll_rate = info->dma_rx_poll_rate;
- + 	omap_up.autosuspend_timeout = info->autosuspend_timeout;
- + 
- + 	/* Enable the MDR1 Errata i202 for OMAP2430/3xxx/44xx */
- + 	omap_up.errata |= UART_ERRATA_i202_MDR1_ACCESS;
- + 
- + 	pdata = &omap_up;
- + 	pdata_size = sizeof(struct omap_uart_port_info);
- + 
- + 	if (WARN_ON(!oh))
- + 		return;
- + 
- + 	pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size,
- + 				 NULL, 0, false);
- + 	WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n",
- + 	     name, oh->name);
- + 
- + 	if ((console_uart_id == bdata->id) && no_console_suspend)
- + 		omap_device_disable_idle_on_suspend(pdev);
- + 
- + 	oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
- + 
- + 	uart->pdev = pdev;
- + 
- + 	oh->dev_attr = uart;
- + 
- + 	if (bdata->pads	&& !uart_debug)
- + 		device_init_wakeup(&pdev->dev, true);
- + }
- + 
- + /**
- +  * omap_serial_board_init() - initialize all supported serial ports
- +  * @info: platform specific data pointer
- +  *
- +  * Initializes all available UARTs as serial ports. Platforms
- +  * can call this function when they want to have default behaviour
- +  * for serial ports (e.g initialize them all as serial ports).
- +  */
- + void __init omap_serial_board_init(struct omap_uart_port_info *info)
- + {
- + 	struct omap_uart_state *uart;
- + 	struct omap_board_data bdata;
- + 
- + 	list_for_each_entry(uart, &uart_list, node) {
- + 		bdata.id = uart->num;
- + 		bdata.flags = 0;
- + 		bdata.pads = NULL;
- + 		bdata.pads_cnt = 0;
- + 
- + 		if (!info)
- + 			omap_serial_init_port(&bdata, NULL);
- + 		else
- + 			omap_serial_init_port(&bdata, &info[uart->num]);
- + 	}
- + }
- + 
- + /**
- +  * omap_serial_init() - initialize all supported serial ports
- +  *
- +  * Initializes all available UARTs.
- +  * Platforms can call this function when they want to have default behaviour
- +  * for serial ports (e.g initialize them all as serial ports).
- +  */
- + void __init omap_serial_init(void)
- + {
- + 	omap_serial_board_init(NULL);
- + }
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/sleep33xx.S linux-3.2.1/arch/arm/mach-ckb_3352/sleep33xx.S
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/sleep33xx.S	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/sleep33xx.S	2014-05-15 13:25:13.999143414 +0900
- ***************
- *** 0 ****
- --- 1,919 ----
- + 
- + /*
- +  * Low level suspend code for AM33XX SoCs
- +  *
- +  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #include <linux/linkage.h>
- + #include <linux/init.h>
- + #include <asm/memory.h>
- + #include <asm/assembler.h>
- + #include <mach/io.h>
- + 
- + #include <plat/emif.h>
- + #include <plat/sram.h>
- + #include <plat/gpio.h>
- + 
- + #include "cm33xx.h"
- + #include "pm33xx.h"
- + #include "prm33xx.h"
- + #include "control.h"
- + 
- + /*
- +  * We should probably pass in the virtual address of PRCM, Control and EMIF
- +  * along with the physical addresses, load it into the registers
- +  * and then continue.
- +  *
- +  * This routine is executed from internal RAM and expects the memory type and
- +  * other DDR configuration values which are different across different memory
- +  * types to be passed in r0 _strictly_ in following order:
- +  * 1) memory_type [r0]
- +  * 2) susp_vtp_ctrl_val [r1]
- +  * 3) evm_id [r2]
- +  * 4) cpu_rev [r3]
- +  * 5) suspend_state[r4]
- +  *
- +  * The code loads these values taking r0 value as reference to the array in
- +  * registers starting from r0, i,e memory_type goes to r0 and susp_vtp_ctrl_val
- +  * goes to r1 and so on. These are then saved into memory locations before
- +  * proceeding with the sleep sequence and hence registers r0,r1 can still be
- +  * used in the rest of the sleep code.
- +  *
- +  * mem_type is used to decide different suspend-resume sequences for DDR2
- +  * and DDR3.
- +  * cpu_rev is used to have/skip certain steps selectively for PG2.0 suspend-resume
- +  * sequence like switching to LVCMOS mode is not required for PG2.0.
- +  */
- + 	.align 3
- + ENTRY(am33xx_do_wfi)
- + 	stmfd	sp!, {r4 - r11, lr}	@ save registers on stack
- + 
- + 	.macro	pll_bypass, name, clk_mode_addr, idlest_addr, pll_mode
- + pll_bypass_\name:
- + 	ldr	r0, \clk_mode_addr
- + 	ldr	r1, [r0]
- + 	str	r1, clk_mode_\pll_mode
- + 	bic	r1, r1, #(7 << 0)
- + 	orr	r1, r1, #0x5
- + 	str	r1, [r0]
- + 	ldr	r0, \idlest_addr
- + wait_pll_bypass_\name:
- + 	ldr	r1, [r0]
- + 	tst	r1, #0x0
- + 	bne	wait_pll_bypass_\name
- + 	.endm
- + 
- + 	.macro	pll_lock, name, clk_mode_addr, idlest_addr, pll_mode
- + pll_lock_\name:
- + 	ldr	r0, \clk_mode_addr
- + 	ldr	r1, clk_mode_\pll_mode
- + 	str	r1, [r0]
- + 	and	r1, r1, #0x7
- + 	cmp	r1, #0x7
- + 	bne	pll_mode_restored_\name
- + 	ldr	r0, \idlest_addr
- + wait_pll_lock_\name:
- + 	ldr	r1, [r0]
- + 	ands	r1, #0x1
- + 	beq	wait_pll_lock_\name
- + pll_mode_restored_\name:
- + 	nop
- + 	.endm
- + 
- + 	.macro	ddr_self_refresh, num
- + ddr_self_refresh_\num:
- + 	add	r1, r0, #EMIF4_0_SDRAM_MGMT_CTRL
- + 	ldr	r2, [r1]
- + 	orr	r2, r2, #0xa0		@ a reasonable delay for entering SR
- + 	str	r2, [r1, #0]
- + 	str	r2, [r1, #4]		@ write to shadow register also
- + 
- + 	ldr	r2, ddr_start		@ do a dummy access to DDR
- + 	ldr	r3, [r2, #0]
- + 	ldr	r3, [r1, #0]
- + 	orr	r3, r3, #0x200		@ now set the LP MODE to Self-Refresh
- + 	str	r3, [r1, #0]
- + 
- + 	mov	r1, #0x1000		@ Give some time for system to enter SR
- + wait_sr_\num:
- + 	subs	r1, r1, #1
- + 	bne	wait_sr_\num
- + 	.endm
- + 
- + 	.macro	wait_sdram_config ,num
- + wait_sdram_config_\num:
- + 	mov	r0, #0x100
- + wait_sc_\num:
- + 	subs	r0, r0 ,#1
- + 	bne	wait_sc_\num
- + 	.endm
- + 
- + 	mov	r8, r0			@ same arg list passed to us
- + 
- + 	/* EMIF config for low power mode */
- + 	ldr	r0, emif_addr_func
- + 	blx	r0
- + 
- + 	str	r0, emif_addr_virt
- + 
- + 	ldr	r0, gpio0_addr_func
- + 	blx	r0
- + 
- + 	str	r0, gpio0_addr_virt
- + 
- + 	/* This ensures isb */
- + 	ldr	r0, dcache_flush
- + 	blx	r0
- + 
- + 	/* Same as v7_flush_icache_all - saving a branch */
- + 	mov	r0, #0
- + 	mcr	p15, 0, r0, c7, c5, 0	@ I+BTB cache invalidate
- + 
- + 	ldm	r8, {r0-r4}		@ gather values passed
- + 
- + 	/* Save the values passed */
- + 	str	r0, mem_type
- + 	str	r1, susp_vtp_ctrl_val
- + 	str	r2, evm_id
- + 	str	r3, cpu_rev
- + 	str	r4, suspend_state
- + 
- + 	ldr	r0, emif_addr_virt
- + 
- + 	/* Save EMIF configuration */
- + 	ldr	r1, [r0, #EMIF4_0_SDRAM_CONFIG]
- + 	str	r1, emif_sdcfg_val
- + 	ldr	r1, [r0, #EMIF4_0_SDRAM_REF_CTRL]
- + 	str	r1, emif_ref_ctrl_val
- + 	ldr	r1, [r0, #EMIF4_0_SDRAM_TIM_1]
- + 	str	r1, emif_timing1_val
- + 	ldr	r1, [r0, #EMIF4_0_SDRAM_TIM_2]
- + 	str	r1, emif_timing2_val
- + 	ldr	r1, [r0, #EMIF4_0_SDRAM_TIM_3]
- + 	str	r1, emif_timing3_val
- + 	ldr	r1, [r0, #EMIF4_0_SDRAM_MGMT_CTRL]
- + 	str	r1, emif_pmcr_val
- + 	ldr	r1, [r0, #EMIF4_0_SDRAM_MGMT_CTRL_SHADOW]
- + 	str	r1, emif_pmcr_shdw_val
- + 	ldr	r1, [r0, #EMIF4_0_ZQ_CONFIG]
- + 	str	r1, emif_zqcfg_val
- + 	ldr	r1, [r0, #EMIF4_0_DDR_PHY_CTRL_1]
- + 	str	r1, emif_rd_lat_val
- + 
- + 	/* Ensure that all the writes to DDR leave the A8 */
- + 	dsb
- + 	dmb
- + 	isb
- + 
- + 	/* Different sleep sequences for DDR2 and DDR3 */
- + 	ldr	r6, mem_type
- + 	cmp	r6, #MEM_TYPE_DDR2
- + 	beq	ddr2_susp_seq
- + 
- + 	/* DDR3 suspend sequence */
- + 
- + 	/* For DDR3, hold DDR_RESET high via control module */
- + 	ldr	r2, virt_ddr_io_ctrl
- + 	ldr	r1, [r2]
- + 	mov	r3,#1
- + 	mov	r3,r3,lsl #31
- + 	orr	r1,r1,r3		@ set ddr3_rst_def_val
- + 	str	r1, [r2]
- + 
- + 	ddr_self_refresh	1
- + 
- + 	/* Weak pull down for macro DATA0 */
- + 	ldr	r1, virt_ddr_data0_ioctrl
- + 	ldr	r2, susp_io_pull_data
- + 	str	r2, [r1]
- + 
- + 	/* Weak pull down for macro DATA1 */
- + 	ldr	r1, virt_ddr_data1_ioctrl
- + 	ldr	r2, susp_io_pull_data
- + 	str	r2, [r1]
- + 
- + 	/* Weak pull down for macro CMD0 */
- + 	ldr	r1, virt_ddr_cmd0_ioctrl
- + 	ldr	r2, susp_io_pull_cmd1
- + 	str	r2, [r1]
- + 
- + 	/* Weak pull down for macro CMD1 */
- + 	ldr	r1, virt_ddr_cmd1_ioctrl
- + 	ldr	r2, susp_io_pull_cmd1
- + 	str	r2, [r1]
- + 
- + 	/*
- + 	 * Weak pull down for macro CMD2
- + 	 * exception: keep DDR_RESET pullup
- + 	 */
- + 	ldr	r1, virt_ddr_cmd2_ioctrl
- + 	ldr	r2, susp_io_pull_cmd2
- + 	str	r2, [r1]
- + 
- + 	/* mddr mode selection not required for PG2.0 */
- + 	ldr	r6, cpu_rev
- + 	cmp	r6, #CPU_REV_2
- + 	beq	mddr_modesel_skip
- + 
- + 	/* Put IO in mDDR (cmos) mode */
- + 	ldr	r0, virt_ddr_io_ctrl
- + 	ldr	r1, [r0]
- + 	mov	r2, #(0x1 << 28)
- + 	orr	r3,r2,r1
- + 	str	r3, [r0]
- + 
- + mddr_modesel_skip:
- + 	/* Disable EMIF at this point */
- + 	ldr	r1, virt_emif_clkctrl
- + 	ldr	r2, [r1]
- + 	bic	r2, r2, #(3 << 0)
- + 	str	r2, [r1]
- + 
- + 	ldr	r1, virt_emif_clkctrl
- + wait_emif_disable3:
- + 	ldr	r2, [r1]
- + 	ldr	r3, module_disabled_val
- + 	cmp	r2, r3
- + 	bne	wait_emif_disable3
- + 
- + 	/* Disable VTP */
- + 	ldr	r1, virt_ddr_vtp_ctrl
- + 	ldr	r2, susp_vtp_ctrl_val
- + 	str	r2, [r1]
- + 
- + 	/* Enable SRAM LDO ret mode */
- + 	ldr	r0, virt_sram_ldo_addr
- + 	ldr	r1, [r0]
- + 	orr	r1, #1
- + 	str	r1, [r0]
- + 
- + 	b	put_pll_bypass
- + 
- + ddr2_susp_seq:
- + 	ddr_self_refresh	2
- + 
- + 	/* Disable EMIF at this point */
- + 	ldr	r1, virt_emif_clkctrl
- + 	ldr	r2, [r1]
- + 	bic	r2, r2, #(3 << 0)
- + 	str	r2, [r1]
- + 
- + 	ldr	r1, virt_emif_clkctrl
- + wait_emif_disable:
- + 	ldr	r2, [r1]
- + 	ldr	r3, module_disabled_val
- + 	cmp	r2, r3
- + 	bne	wait_emif_disable
- + 
- + 	/* DDR3 reset override and mDDR mode selection */
- + 	ldr	r0, virt_ddr_io_ctrl
- + 	mov	r1, #(0x9 << 28)
- + 	str	r1, [r0]
- + 
- + 	/* Weak pull down for DQ, DM */
- + 	ldr	r1, virt_ddr_io_pull1
- + 	ldr	r2, susp_io_pull_data
- + 	str	r2, [r1]
- + 
- + 	ldr	r1, virt_ddr_io_pull2
- + 	ldr	r2, susp_io_pull_data
- + 	str	r2, [r1]
- + 
- + 	/* Disable VTP */
- + 	ldr	r1, virt_ddr_vtp_ctrl
- + 	ldr	r2, susp_vtp_ctrl_val
- + 	str	r2, [r1]
- + 
- + 	/* Enable SRAM LDO ret mode */
- + 	ldr	r0, virt_sram_ldo_addr
- + 	ldr	r1, [r0]
- + 	orr	r1, #1
- + 	str	r1, [r0]
- + 
- + put_pll_bypass:
- + 	/* Put the PLLs in bypass mode */
- + 	pll_bypass	core, virt_core_clk_mode, virt_core_idlest, core_val
- + 	pll_bypass	ddr, virt_ddr_clk_mode, virt_ddr_idlest, ddr_val
- + 	pll_bypass	disp, virt_disp_clk_mode, virt_disp_idlest, disp_val
- + 	pll_bypass	per, virt_per_clk_mode, virt_per_idlest, per_val
- + 	pll_bypass	mpu, virt_mpu_clk_mode, virt_mpu_idlest, mpu_val
- + 
- + 	dsb
- + 	dmb
- + 	isb
- + 
- + 	wfi
- + 	nop
- + 	nop
- + 	nop
- + 	nop
- + 	nop
- + 	nop
- + 	nop
- + 	nop
- + 	nop
- + 	nop
- + 	nop
- + 	nop
- + 	nop
- + 
- + 	/* We come here in case of an abort */
- + 
- + 	/* Relock the PLLs */
- + 	pll_lock	mpu_abt, virt_mpu_clk_mode, virt_mpu_idlest, mpu_val
- + 	pll_lock	per_abt, virt_per_clk_mode, virt_per_idlest, per_val
- + 	pll_lock	disp_abt, virt_disp_clk_mode, virt_disp_idlest, disp_val
- + 	pll_lock	ddr_abt, virt_ddr_clk_mode, virt_ddr_idlest, ddr_val
- + 	pll_lock	core_abt, virt_core_clk_mode, virt_core_idlest, core_val
- + 
- + 	ldr	r6, mem_type
- + 	cmp	r6, #MEM_TYPE_DDR2
- + 	beq	ddr2_resume_seq_abt
- + 
- + 	/* DDR3 resume path */
- + 
- + 	/* Disable SRAM LDO ret mode */
- + 	ldr	r0, virt_sram_ldo_addr
- + 	ldr	r1, [r0]
- + 	bic	r1, #1
- + 	str	r1, [r0]
- + 
- + 	/* Enable EMIF */
- + 	ldr	r1, virt_emif_clkctrl
- + 	mov	r2, #0x2
- + 	str	r2, [r1]
- + wait_emif_enable3:
- + 	ldr	r3, [r1]
- + 	cmp	r2, r3
- + 	bne	wait_emif_enable3
- + 
- + 	/* mddr mode selection not required for PG2.0 */
- + 	ldr	r6, cpu_rev
- + 	cmp	r6, #CPU_REV_2
- + 	beq	config_vtp_abt3
- + 
- + 	/* Take out IO of mDDR mode */
- + 	ldr	r0, virt_ddr_io_ctrl
- + 	ldr	r1, [r0]
- + 	bic	r1, r1, #(1 << 28)
- + 	str	r1, [r0]
- + 
- + 	/* Enable VTP */
- + config_vtp_abt3:
- + 	ldr	r0, virt_ddr_vtp_ctrl
- + 	ldr	r1, [r0]
- + 	mov	r2, #0x0	@ clear the register
- + 	str	r2, [r0]
- + 	mov	r2, #0x6	@ write the filter value
- + 	str	r2, [r0]
- + 
- + 	ldr	r1, [r0]
- + 	ldr	r2, vtp_enable	@ set the enable bit
- + 	orr	r2, r2, r1
- + 	str	r2, [r0]
- + 
- + 	ldr	r1, [r0]	@ toggle the CLRZ bit
- + 	bic	r1, #1
- + 	str	r1, [r0]
- + 
- + 	ldr	r1, [r0]
- + 	orr	r1, #1
- + 	str	r1, [r0]
- + 
- + poll_vtp_ready_abt3:
- + 	ldr	r1, [r0]	@ poll for VTP ready
- + 	tst	r1, #(1 << 5)
- + 	beq	poll_vtp_ready_abt3
- + 
- + 	/* Disable the pull for CMD2 */
- + 	ldr	r1, virt_ddr_cmd2_ioctrl
- + 	ldr	r2, resume_io_pull_cmd
- + 	str	r2, [r1]
- + 	/* Disable the pull for CMD1 */
- + 	ldr	r1, virt_ddr_cmd1_ioctrl
- + 	ldr	r2, resume_io_pull_cmd
- + 	str	r2, [r1]
- + 	/* Disable the pull for CMD0 */
- + 	ldr	r1, virt_ddr_cmd0_ioctrl
- + 	ldr	r2, resume_io_pull_cmd
- + 	str	r2, [r1]
- + 	/* Disable the pull for DATA1 */
- + 	ldr	r1, virt_ddr_data1_ioctrl
- + 	ldr	r2, resume_io_pull_data
- + 	str	r2, [r1]
- + 	/* Disable the pull for DATA0 */
- + 	ldr	r1, virt_ddr_data0_ioctrl
- + 	ldr	r2, resume_io_pull_data
- + 	str	r2, [r1]
- + 
- + 	wait_sdram_config	1
- + 
- + 	/* Disable EMIF self-refresh */
- + 	ldr	r0, emif_addr_virt
- + 	add	r0, r0, #EMIF4_0_SDRAM_MGMT_CTRL
- + 	ldr	r1, [r0]
- + 	bic	r1, r1, #(0x7 << 8)
- + 	str	r1, [r0]
- + 	str	r1, [r0, #4]
- + 
- + 	/* For DDR3, make DDR_RESET low via control module */
- + 	ldr	r0, virt_ddr_io_ctrl
- + 	ldr	r1, [r0]
- + 	bic	r1, r1, #(1 << 31)
- + 	str	r1, [r0]
- + 
- + 	b	return_to_ddr_abt
- + 
- + 	/* DDR2 resume path */
- + ddr2_resume_seq_abt:
- + 	/* Disable SRAM LDO ret mode */
- + 	ldr	r0, virt_sram_ldo_addr
- + 	ldr	r1, [r0]
- + 	bic	r1, #1
- + 	str	r1, [r0]
- + 
- + 	/* Restore the pull for DQ, DM */
- + 	ldr	r1, virt_ddr_io_pull1
- + 	ldr	r2, resume_io_pull_data
- + 	str	r2, [r1]
- + 
- + 	ldr	r1, virt_ddr_io_pull2
- + 	ldr	r2, resume_io_pull_data
- + 	str	r2, [r1]
- + 
- + 	/* Enable EMIF */
- + 	ldr	r1, virt_emif_clkctrl
- + 	mov	r2, #0x2
- + 	str	r2, [r1]
- + wait_emif_enable:
- + 	ldr	r3, [r1]
- + 	cmp	r2, r3
- + 	bne	wait_emif_enable
- + 
- + 	/* Enable VTP */
- + config_vtp_abt:
- + 	ldr	r0, virt_ddr_vtp_ctrl
- + 	ldr	r1, [r0]
- + 	mov	r2, #0x0	@ clear the register
- + 	str	r2, [r0]
- + 	mov	r2, #0x6	@ write the filter value
- + 	str	r2, [r0]
- + 
- + 	ldr	r1, [r0]
- + 	ldr	r2, vtp_enable	@ set the enable bit
- + 	orr	r2, r2, r1
- + 	str	r2, [r0]
- + 
- + 	ldr	r1, [r0]	@ toggle the CLRZ bit
- + 	bic	r1, #1
- + 	str	r1, [r0]
- + 
- + 	ldr	r1, [r0]
- + 	orr	r1, #1
- + 	str	r1, [r0]
- + 
- + poll_vtp_ready_abt:
- + 	ldr	r1, [r0]	@ poll for VTP ready
- + 	tst	r1, #(1 << 5)
- + 	beq	poll_vtp_ready_abt
- + 
- + 	/* DDR3 reset override and mDDR mode clear */
- + 	ldr	r0, virt_ddr_io_ctrl
- + 	mov	r1, #0
- + 	str	r1, [r0]
- + 
- + emif_self_refresh_dis:
- + 	/* Disable EMIF self-refresh */
- + 	ldr	r0, emif_addr_virt
- + 	add	r0, r0, #EMIF4_0_SDRAM_MGMT_CTRL
- + 	ldr	r1, [r0]
- + 	bic	r1, r1, #(0x7 << 8)
- + 	str	r1, [r0]
- + 	str	r1, [r0, #4]
- + 
- + /*
- +  * A write to SDRAM CONFIG register triggers
- +  * an init sequence and hence it must be done
- +  * at the end
- +  */
- + 	ldr r0,	emif_addr_virt
- + 	add r0,	r0, #EMIF4_0_SDRAM_CONFIG
- + 	ldr r4,	emif_sdcfg_val
- + 	str r4,	[r0]
- + 
- + 	mov r0,	#0x2000
- + wait_loop4:
- + 	subs	r0, r0, #1
- + 	bne	wait_loop4
- + 
- + return_to_ddr_abt:
- + 	mov	r0, #7
- + 	ldmfd	sp!, {r4 - r11, pc}	@ restore regs and return
- + 
- + ENTRY(am33xx_resume_offset)
- + 	.word . - am33xx_do_wfi
- + 
- + ENTRY(am33xx_resume_from_deep_sleep)
- + 	/* Take the PLLs out of LP_BYPASS */
- + 	pll_lock	mpu, phys_mpu_clk_mode, phys_mpu_idlest, mpu_val
- + 	pll_lock	per, phys_per_clk_mode, phys_per_idlest, per_val
- + 	pll_lock	disp, phys_disp_clk_mode, phys_disp_idlest, disp_val
- + 	pll_lock	ddr, phys_ddr_clk_mode, phys_ddr_idlest, ddr_val
- + 	pll_lock	core, phys_core_clk_mode, phys_core_idlest, core_val
- + 
- + 	ldr	r6, mem_type
- + 	cmp	r6, #MEM_TYPE_DDR2
- + 	beq	ddr2_resume_seq
- + 
- + 	/* DDR3 resume path */
- + 
- + 	/* Disable SRAM LDO ret mode */
- + 	ldr	r0, phys_sram_ldo_addr
- + 	ldr	r1, [r0]
- + 	bic	r1, #1
- + 	str	r1, [r0]
- + 
- + 	/* TODO: Put EMIF enable here */
- + 
- + 	/* mddr mode selection not required for PG2.0 */
- + 	ldr	r6, cpu_rev
- + 	cmp	r6, #CPU_REV_2
- + 	beq	config_vtp3
- + 
- + 	/* Take out IO of mDDR mode */
- + 	ldr	r0, phys_ddr_io_ctrl
- + 	ldr	r1, [r0]
- + 	bic	r1, r1, #(1 << 28)
- + 	str	r1, [r0]
- + 
- + config_vtp3:
- + 	ldr	r0, phys_ddr_vtp_ctrl
- + 	ldr	r1, [r0]
- + 	mov	r2, #0x0	@ clear the register
- + 	str	r2, [r0]
- + 	mov	r2, #0x6	@ write the filter value
- + 	str	r2, [r0]
- + 
- + 	ldr	r1, [r0]
- + 	ldr	r2, vtp_enable	@ set the enable bit
- + 	orr	r2, r2, r1
- + 	str	r2, [r0]
- + 
- + 	ldr	r1, [r0]	@ toggle the CLRZ bit
- + 	bic	r1, #1
- + 	str	r1, [r0]
- + 
- + 	ldr	r1, [r0]
- + 	orr	r1, #1
- + 	str	r1, [r0]
- + poll_vtp_ready3:
- + 	ldr	r1, [r0]	@ poll for VTP ready
- + 	tst	r1, #(1 << 5)
- + 	beq	poll_vtp_ready3
- + 
- + 	/* Disable the pull for CMD2 */
- + 	ldr	r1, phys_ddr_cmd2_ioctrl
- + 	ldr	r2, resume_io_pull_cmd
- + 	str	r2, [r1]
- + 	/* Disable the pull for CMD1 */
- + 	ldr	r1, phys_ddr_cmd1_ioctrl
- + 	ldr	r2, resume_io_pull_cmd
- + 	str	r2, [r1]
- + 	/* Disable the pull for CMD0 */
- + 	ldr	r1, phys_ddr_cmd0_ioctrl
- + 	ldr	r2, resume_io_pull_cmd
- + 	str	r2, [r1]
- + 	/* Disable the pull for DATA1 */
- + 	ldr	r1, phys_ddr_data1_ioctrl
- + 	ldr	r2, resume_io_pull_data
- + 	str	r2, [r1]
- + 	/* Disable the pull for DATA0 */
- + 	ldr	r1, phys_ddr_data0_ioctrl
- + 	ldr	r2, resume_io_pull_data
- + 	str	r2, [r1]
- + 
- + 	wait_sdram_config	2
- + 
- + 	b	config_emif_timings
- + 
- + 	/* DDR2 resume path */
- + ddr2_resume_seq:
- + 	/* Disable SRAM LDO ret mode */
- + 	ldr	r0, phys_sram_ldo_addr
- + 	ldr	r1, [r0]
- + 	bic	r1, #1
- + 	str	r1, [r0]
- + 
- + 	/* Restore the pull for DQ, DM */
- + 	ldr	r1, phys_ddr_io_pull1
- + 	ldr	r2, resume_io_pull_data
- + 	str	r2, [r1]
- + 
- + 	ldr	r1, phys_ddr_io_pull2
- + 	ldr	r2, resume_io_pull_data
- + 	str	r2, [r1]
- + 
- + config_vtp:
- + 	ldr	r0, phys_ddr_vtp_ctrl
- + 	ldr	r1, [r0]
- + 	mov	r2, #0x0	@ clear the register
- + 	str	r2, [r0]
- + 	mov	r2, #0x6	@ write the filter value
- + 	str	r2, [r0]
- + 
- + 	ldr	r1, [r0]
- + 	ldr	r2, vtp_enable	@ set the enable bit
- + 	orr	r2, r2, r1
- + 	str	r2, [r0]
- + 
- + 	ldr	r1, [r0]	@ toggle the CLRZ bit
- + 	bic	r1, #1
- + 	str	r1, [r0]
- + 
- + 	ldr	r1, [r0]
- + 	orr	r1, #1
- + 	str	r1, [r0]
- + 
- + poll_vtp_ready:
- + 	ldr	r1, [r0]	@ poll for VTP ready
- + 	tst	r1, #(1 << 5)
- + 	beq	poll_vtp_ready
- + 
- + 	/* DDR3 reset override and mDDR mode clear */
- + 	ldr	r0, phys_ddr_io_ctrl
- + 	mov	r1, #0
- + 	str	r1, [r0]
- + 
- + config_emif_timings:
- + 	ldr	r3, emif_phys_addr
- + 	ldr	r4, emif_rd_lat_val
- + rd_lat:
- + 	str	r4, [r3, #EMIF4_0_DDR_PHY_CTRL_1]
- + 	str	r4, [r3, #EMIF4_0_DDR_PHY_CTRL_1_SHADOW]
- + timing1:
- + 	ldr	r4, emif_timing1_val
- + 	str	r4, [r3, #EMIF4_0_SDRAM_TIM_1]
- + 	str	r4, [r3, #EMIF4_0_SDRAM_TIM_1_SHADOW]
- + timing2:
- + 	ldr	r4, emif_timing2_val
- + 	str	r4, [r3, #EMIF4_0_SDRAM_TIM_2]
- + 	str	r4, [r3, #EMIF4_0_SDRAM_TIM_2_SHADOW]
- + timing3:
- + 	ldr	r4, emif_timing3_val
- + 	str	r4, [r3, #EMIF4_0_SDRAM_TIM_3]
- + 	str	r4, [r3, #EMIF4_0_SDRAM_TIM_3_SHADOW]
- + sdram_ref_ctrl:
- + 	ldr	r4, emif_ref_ctrl_val
- + 	str	r4, [r3, #EMIF4_0_SDRAM_REF_CTRL]
- + 	str	r4, [r3, #EMIF4_0_SDRAM_REF_CTRL_SHADOW]
- + pmcr:
- + 	ldr	r4, emif_pmcr_val
- + 	str	r4, [r3, #EMIF4_0_SDRAM_MGMT_CTRL]
- + pmcr_shdw:
- + 	ldr	r4, emif_pmcr_shdw_val
- + 	str	r4, [r3, #EMIF4_0_SDRAM_MGMT_CTRL_SHADOW]
- + 
- + 	/*
- + 	 * Output impedence calib needed only for DDR3
- + 	 * but since the initial state of this will be
- + 	 * disabled for DDR2 no harm in restoring the
- + 	 * old configuration
- + 	 */
- + zqcfg:
- + 	ldr	r4, emif_zqcfg_val
- + 	str	r4, [r3, #EMIF4_0_ZQ_CONFIG]
- + 
- + 	/* Write to SDRAM_CONFIG only for DDR2 */
- + 	ldr	r6, mem_type
- + 	cmp	r6, #MEM_TYPE_DDR2
- + 	beq	ddr2_sdcfg
- + 
- + 	/* For DDR3, make DDR_RESET low via control module */
- + 	ldr	r0, phys_ddr_io_ctrl
- + 	ldr	r1, [r0]
- + 	bic	r1, r1, #(1 << 31)
- + 	str	r1, [r0]
- + 
- + 	b	return_to_ddr
- + 
- + 	/*
- + 	 * A write to SDRAM CONFIG register triggers
- + 	 * an init sequence and hence it must be done
- + 	 * at the end for DDR2
- + 	 */
- + ddr2_sdcfg:
- + 	ldr	r4, emif_sdcfg_val
- + 	str	r4, [r3, #EMIF4_0_SDRAM_CONFIG]
- + 
- + return_to_ddr:
- + 	/* Back from la-la-land. Kill some time for sanity to settle in */
- + 	mov	r0, #0x1000
- + wait_loop2:
- + 	subs	r0, r0, #1
- + 	bne	wait_loop2
- + 
- + 	/* We are back. Branch to the common CPU resume routine */
- + ENTRY(am33xx_resume_vector)
- + 	ldr	pc, resume_addr
- + 
- + /*
- +  * Local variables
- +  */
- + 
- + dcache_flush:
- + 	.word   v7_flush_dcache_all
- + resume_addr:
- + 	.word	cpu_resume - PAGE_OFFSET + 0x80000000
- + 
- + emif_addr_func:
- + 	.word	am33xx_get_ram_base
- + emif_phys_addr:
- + 	.word	AM33XX_EMIF0_BASE
- + 
- + gpio0_addr_func:
- + 	.word	am33xx_get_gpio0_base
- + gpio0_phys_addr:
- + 	.word	AM33XX_GPIO0_BASE
- + 
- + ddr_start:
- + 	.word	PAGE_OFFSET
- + 
- + virt_mpu_idlest:
- + 	.word	AM33XX_CM_IDLEST_DPLL_MPU
- + virt_mpu_clk_mode:
- + 	.word	AM33XX_CM_CLKMODE_DPLL_MPU
- + 
- + phys_pll_mod:
- + 	.word	AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD
- + phys_mpu_clk_mode:
- + 	.word	AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + AM33XX_CM_CLKMODE_DPLL_MPU_OFFSET
- + phys_mpu_idlest:
- + 	.word	AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + AM33XX_CM_IDLEST_DPLL_MPU_OFFSET
- + 
- + virt_core_idlest:
- + 	.word	AM33XX_CM_IDLEST_DPLL_CORE
- + virt_core_clk_mode:
- + 	.word	AM33XX_CM_CLKMODE_DPLL_CORE
- + phys_core_clk_mode:
- + 	.word	AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + AM33XX_CM_CLKMODE_DPLL_CORE_OFFSET
- + phys_core_idlest:
- + 	.word	AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + AM33XX_CM_IDLEST_DPLL_CORE_OFFSET
- + 
- + virt_per_idlest:
- + 	.word	AM33XX_CM_IDLEST_DPLL_PER
- + virt_per_clk_mode:
- + 	.word	AM33XX_CM_CLKMODE_DPLL_PER
- + phys_per_clk_mode:
- + 	.word	AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + AM33XX_CM_CLKMODE_DPLL_PER_OFFSET
- + phys_per_idlest:
- + 	.word	AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + AM33XX_CM_IDLEST_DPLL_PER_OFFSET
- + 
- + virt_disp_idlest:
- + 	.word	AM33XX_CM_IDLEST_DPLL_DISP
- + virt_disp_clk_mode:
- + 	.word	AM33XX_CM_CLKMODE_DPLL_DISP
- + phys_disp_clk_mode:
- + 	.word	AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + AM33XX_CM_CLKMODE_DPLL_DISP_OFFSET
- + phys_disp_idlest:
- + 	.word	AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + AM33XX_CM_IDLEST_DPLL_DISP_OFFSET
- + 
- + virt_ddr_idlest:
- + 	.word	AM33XX_CM_IDLEST_DPLL_DDR
- + virt_ddr_clk_mode:
- + 	.word	AM33XX_CM_CLKMODE_DPLL_DDR
- + phys_ddr_clk_mode:
- + 	.word	AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + AM33XX_CM_CLKMODE_DPLL_DDR_OFFSET
- + phys_ddr_idlest:
- + 	.word	AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + AM33XX_CM_IDLEST_DPLL_DDR_OFFSET
- + 
- + virt_sram_ldo_addr:
- + 	.word	AM33XX_PRM_LDO_SRAM_MPU_CTRL
- + phys_sram_ldo_addr:
- + 	.word	AM33XX_PRM_BASE + AM33XX_PRM_DEVICE_MOD + AM33XX_PRM_LDO_SRAM_MPU_CTRL_OFFSET
- + 
- + virt_gpio0_clkctrl:
- + 	.word	AM33XX_CM_WKUP_GPIO0_CLKCTRL
- + phys_gpio0_clkctrl:
- + 	.word	AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET
- + 
- + virt_emif_clkctrl:
- + 	.word	AM33XX_CM_PER_EMIF_CLKCTRL
- + phys_emif_clkctrl:
- + 	.word	AM33XX_CM_BASE + AM33XX_CM_PER_MOD + AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET
- + module_disabled_val:
- + 	.word	0x30000
- + 
- + /* DDR related stuff */
- + virt_ddr_io_ctrl:
- + 	.word	AM33XX_CTRL_REGADDR(0x0E04)
- + phys_ddr_io_ctrl:
- + 	.word	DDR_IO_CTRL
- + virt_ddr_vtp_ctrl:
- + 	.word	AM33XX_CTRL_REGADDR(0x0E0C)
- + phys_ddr_vtp_ctrl:
- + 	.word	VTP0_CTRL_REG
- + virt_ddr_cmd0_ioctrl:
- + 	.word	AM33XX_CTRL_REGADDR(0x1404)
- + phys_ddr_cmd0_ioctrl:
- + 	.word	DDR_CMD0_IOCTRL
- + virt_ddr_cmd1_ioctrl:
- + 	.word	AM33XX_CTRL_REGADDR(0x1408)
- + phys_ddr_cmd1_ioctrl:
- + 	.word	DDR_CMD1_IOCTRL
- + virt_ddr_cmd2_ioctrl:
- + 	.word	AM33XX_CTRL_REGADDR(0x140C)
- + phys_ddr_cmd2_ioctrl:
- + 	.word	DDR_CMD2_IOCTRL
- + virt_ddr_data0_ioctrl:
- + 	.word	AM33XX_CTRL_REGADDR(0x1440)
- + phys_ddr_data0_ioctrl:
- + 	.word	DDR_DATA0_IOCTRL
- + virt_ddr_data1_ioctrl:
- + 	.word	AM33XX_CTRL_REGADDR(0x1444)
- + phys_ddr_data1_ioctrl:
- + 	.word	DDR_DATA1_IOCTRL
- + vtp_enable:
- + 	.word	VTP_CTRL_ENABLE
- + 
- + virt_ddr_io_pull1:
- + 	.word	AM33XX_CTRL_REGADDR(0x1440)
- + phys_ddr_io_pull1:
- + 	.word	AM33XX_CTRL_BASE + (0x1440)
- + virt_ddr_io_pull2:
- + 	.word	AM33XX_CTRL_REGADDR(0x1444)
- + phys_ddr_io_pull2:
- + 	.word	AM33XX_CTRL_BASE + (0x1444)
- + virt_ddr_io_pull3:
- + 	.word	AM33XX_CTRL_REGADDR(0x1448)
- + phys_ddr_io_pull3:
- + 	.word	AM33XX_CTRL_BASE + (0x1448)
- + 
- + susp_io_pull_data:
- + 	.word	0x3FF00003
- + susp_io_pull_cmd1:
- + 	.word   0xFFE0018B
- + susp_io_pull_cmd2:
- + 	.word   0xFFA0098B
- + 
- + resume_io_pull_data:
- + 	.word	0x18B
- + resume_io_pull_cmd:
- + 	.word	0x18B
- + 
- + susp_vtp_ctrl_val:
- + 	.word	0xDEADBEEF
- + mem_type:
- + 	.word	0xDEADBEEF
- + evm_id:
- + 	.word	0xDEADBEEF
- + cpu_rev:
- + 	.word	0xDEADBEEF
- + suspend_state:
- + 	.word	0xDEADBEEF
- + emif_addr_virt:
- + 	.word	0xDEADBEEF
- + gpio0_addr_virt:
- + 	.word	0xDEADBEEF
- + emif_rd_lat_val:
- + 	.word	0xDEADBEEF
- + emif_timing1_val:
- + 	.word	0xDEADBEEF
- + emif_timing2_val:
- + 	.word	0xDEADBEEF
- + emif_timing3_val:
- + 	.word	0xDEADBEEF
- + emif_sdcfg_val:
- + 	.word	0xDEADBEEF
- + emif_ref_ctrl_val:
- + 	.word	0xDEADBEEF
- + emif_zqcfg_val:
- + 	.word	0xDEADBEEF
- + emif_pmcr_val:
- + 	.word	0xDEADBEEF
- + emif_pmcr_shdw_val:
- + 	.word	0xDEADBEEF
- + 
- + /* PLL CLKMODE before suspend */
- + clk_mode_mpu_val:
- + 	.word	0xDEADBEEF
- + clk_mode_per_val:
- + 	.word	0xDEADBEEF
- + clk_mode_disp_val:
- + 	.word	0xDEADBEEF
- + clk_mode_ddr_val:
- + 	.word	0xDEADBEEF
- + clk_mode_core_val:
- + 	.word	0xDEADBEEF
- + 
- + ENTRY(am33xx_do_wfi_sz)
- + 	.word	. - am33xx_do_wfi
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/smartreflex.h linux-3.2.1/arch/arm/mach-ckb_3352/smartreflex.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/smartreflex.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/smartreflex.h	2014-05-15 13:25:14.003319096 +0900
- ***************
- *** 0 ****
- --- 1,246 ----
- + /*
- +  * OMAP Smartreflex Defines and Routines
- +  *
- +  * Author: Thara Gopinath	<thara@ti.com>
- +  *
- +  * Copyright (C) 2010 Texas Instruments, Inc.
- +  * Thara Gopinath <thara@ti.com>
- +  *
- +  * Copyright (C) 2008 Nokia Corporation
- +  * Kalle Jokiniemi
- +  *
- +  * Copyright (C) 2007 Texas Instruments, Inc.
- +  * Lesly A M <x0080970@ti.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #ifndef __ASM_ARM_OMAP_SMARTREFLEX_H
- + #define __ASM_ARM_OMAP_SMARTREFLEX_H
- + 
- + #include <linux/platform_device.h>
- + 
- + #include "voltage.h"
- + 
- + /*
- +  * Different Smartreflex IPs version. The v1 is the 65nm version used in
- +  * OMAP3430. The v2 is the update for the 45nm version of the IP
- +  * used in OMAP3630 and OMAP4430
- +  */
- + #define SR_TYPE_V1	1
- + #define SR_TYPE_V2	2
- + 
- + /* SMART REFLEX REG ADDRESS OFFSET */
- + #define SRCONFIG		0x00
- + #define SRSTATUS		0x04
- + #define SENVAL			0x08
- + #define SENMIN			0x0C
- + #define SENMAX			0x10
- + #define SENAVG			0x14
- + #define AVGWEIGHT		0x18
- + #define NVALUERECIPROCAL	0x1c
- + #define SENERROR_V1		0x20
- + #define ERRCONFIG_V1		0x24
- + #define IRQ_EOI			0x20
- + #define IRQSTATUS_RAW		0x24
- + #define IRQSTATUS		0x28
- + #define IRQENABLE_SET		0x2C
- + #define IRQENABLE_CLR		0x30
- + #define SENERROR_V2		0x34
- + #define ERRCONFIG_V2		0x38
- + 
- + /* Bit/Shift Positions */
- + 
- + /* SRCONFIG */
- + #define SRCONFIG_ACCUMDATA_SHIFT	22
- + #define SRCONFIG_SRCLKLENGTH_SHIFT	12
- + #define SRCONFIG_SENNENABLE_V1_SHIFT	5
- + #define SRCONFIG_SENPENABLE_V1_SHIFT	3
- + #define SRCONFIG_SENNENABLE_V2_SHIFT	1
- + #define SRCONFIG_SENPENABLE_V2_SHIFT	0
- + #define SRCONFIG_CLKCTRL_SHIFT		0
- + 
- + #define SRCONFIG_ACCUMDATA_MASK		(0x3ff << 22)
- + 
- + #define SRCONFIG_SRENABLE		BIT(11)
- + #define SRCONFIG_SENENABLE		BIT(10)
- + #define SRCONFIG_ERRGEN_EN		BIT(9)
- + #define SRCONFIG_MINMAXAVG_EN		BIT(8)
- + #define SRCONFIG_DELAYCTRL		BIT(2)
- + 
- + /* AVGWEIGHT */
- + #define AVGWEIGHT_SENPAVGWEIGHT_SHIFT	2
- + #define AVGWEIGHT_SENNAVGWEIGHT_SHIFT	0
- + 
- + /* NVALUERECIPROCAL */
- + #define NVALUERECIPROCAL_SENPGAIN_SHIFT	20
- + #define NVALUERECIPROCAL_SENNGAIN_SHIFT	16
- + #define NVALUERECIPROCAL_RNSENP_SHIFT	8
- + #define NVALUERECIPROCAL_RNSENN_SHIFT	0
- + 
- + /* ERRCONFIG */
- + #define ERRCONFIG_ERRWEIGHT_SHIFT	16
- + #define ERRCONFIG_ERRMAXLIMIT_SHIFT	8
- + #define ERRCONFIG_ERRMINLIMIT_SHIFT	0
- + 
- + #define SR_ERRWEIGHT_MASK		(0x07 << 16)
- + #define SR_ERRMAXLIMIT_MASK		(0xff << 8)
- + #define SR_ERRMINLIMIT_MASK		(0xff << 0)
- + 
- + #define ERRCONFIG_VPBOUNDINTEN_V1	BIT(31)
- + #define ERRCONFIG_VPBOUNDINTST_V1	BIT(30)
- + #define	ERRCONFIG_MCUACCUMINTEN		BIT(29)
- + #define ERRCONFIG_MCUACCUMINTST		BIT(28)
- + #define	ERRCONFIG_MCUVALIDINTEN		BIT(27)
- + #define ERRCONFIG_MCUVALIDINTST		BIT(26)
- + #define ERRCONFIG_MCUBOUNDINTEN		BIT(25)
- + #define	ERRCONFIG_MCUBOUNDINTST		BIT(24)
- + #define	ERRCONFIG_MCUDISACKINTEN	BIT(23)
- + #define ERRCONFIG_VPBOUNDINTST_V2	BIT(23)
- + #define ERRCONFIG_MCUDISACKINTST	BIT(22)
- + #define ERRCONFIG_VPBOUNDINTEN_V2	BIT(22)
- + 
- + #define ERRCONFIG_STATUS_V1_MASK	(ERRCONFIG_VPBOUNDINTST_V1 | \
- + 					ERRCONFIG_MCUACCUMINTST | \
- + 					ERRCONFIG_MCUVALIDINTST | \
- + 					ERRCONFIG_MCUBOUNDINTST | \
- + 					ERRCONFIG_MCUDISACKINTST)
- + /* IRQSTATUS */
- + #define IRQSTATUS_MCUACCUMINT		BIT(3)
- + #define IRQSTATUS_MCVALIDINT		BIT(2)
- + #define IRQSTATUS_MCBOUNDSINT		BIT(1)
- + #define IRQSTATUS_MCUDISABLEACKINT	BIT(0)
- + 
- + /* IRQENABLE_SET and IRQENABLE_CLEAR */
- + #define IRQENABLE_MCUACCUMINT		BIT(3)
- + #define IRQENABLE_MCUVALIDINT		BIT(2)
- + #define IRQENABLE_MCUBOUNDSINT		BIT(1)
- + #define IRQENABLE_MCUDISABLEACKINT	BIT(0)
- + 
- + /* Common Bit values */
- + 
- + #define SRCLKLENGTH_12MHZ_SYSCLK	0x3c
- + #define SRCLKLENGTH_13MHZ_SYSCLK	0x41
- + #define SRCLKLENGTH_19MHZ_SYSCLK	0x60
- + #define SRCLKLENGTH_26MHZ_SYSCLK	0x82
- + #define SRCLKLENGTH_38MHZ_SYSCLK	0xC0
- + 
- + /*
- +  * 3430 specific values. Maybe these should be passed from board file or
- +  * pmic structures.
- +  */
- + #define OMAP3430_SR_ACCUMDATA		0x1f4
- + 
- + #define OMAP3430_SR1_SENPAVGWEIGHT	0x03
- + #define OMAP3430_SR1_SENNAVGWEIGHT	0x03
- + 
- + #define OMAP3430_SR2_SENPAVGWEIGHT	0x01
- + #define OMAP3430_SR2_SENNAVGWEIGHT	0x01
- + 
- + #define OMAP3430_SR_ERRWEIGHT		0x04
- + #define OMAP3430_SR_ERRMAXLIMIT		0x02
- + 
- + /**
- +  * struct omap_sr_pmic_data - Strucutre to be populated by pmic code to pass
- +  *				pmic specific info to smartreflex driver
- +  *
- +  * @sr_pmic_init:	API to initialize smartreflex on the PMIC side.
- +  */
- + struct omap_sr_pmic_data {
- + 	void (*sr_pmic_init) (void);
- + };
- + 
- + #ifdef CONFIG_OMAP_SMARTREFLEX
- + /*
- +  * The smart reflex driver supports CLASS1 CLASS2 and CLASS3 SR.
- +  * The smartreflex class driver should pass the class type.
- +  * Should be used to populate the class_type field of the
- +  * omap_smartreflex_class_data structure.
- +  */
- + #define SR_CLASS1	0x1
- + #define SR_CLASS2	0x2
- + #define SR_CLASS3	0x3
- + 
- + /**
- +  * struct omap_sr_class_data - Smartreflex class driver info
- +  *
- +  * @enable:		API to enable a particular class smaartreflex.
- +  * @disable:		API to disable a particular class smartreflex.
- +  * @configure:		API to configure a particular class smartreflex.
- +  * @notify:		API to notify the class driver about an event in SR.
- +  *			Not needed for class3.
- +  * @notify_flags:	specify the events to be notified to the class driver
- +  * @class_type:		specify which smartreflex class.
- +  *			Can be used by the SR driver to take any class
- +  *			based decisions.
- +  */
- + struct omap_sr_class_data {
- + 	int (*enable)(struct voltagedomain *voltdm);
- + 	int (*disable)(struct voltagedomain *voltdm, int is_volt_reset);
- + 	int (*configure)(struct voltagedomain *voltdm);
- + 	int (*notify)(struct voltagedomain *voltdm, u32 status);
- + 	u8 notify_flags;
- + 	u8 class_type;
- + };
- + 
- + /**
- +  * struct omap_sr_nvalue_table	- Smartreflex n-target value info
- +  *
- +  * @efuse_offs:	The offset of the efuse where n-target values are stored.
- +  * @nvalue:	The n-target value.
- +  */
- + struct omap_sr_nvalue_table {
- + 	u32 efuse_offs;
- + 	u32 nvalue;
- + };
- + 
- + /**
- +  * struct omap_sr_data - Smartreflex platform data.
- +  *
- +  * @ip_type:		Smartreflex IP type.
- +  * @senp_mod:		SENPENABLE value for the sr
- +  * @senn_mod:		SENNENABLE value for sr
- +  * @nvalue_count:	Number of distinct nvalues in the nvalue table
- +  * @enable_on_init:	whether this sr module needs to enabled at
- +  *			boot up or not.
- +  * @nvalue_table:	table containing the  efuse offsets and nvalues
- +  *			corresponding to them.
- +  * @voltdm:		Pointer to the voltage domain associated with the SR
- +  */
- + struct omap_sr_data {
- + 	int				ip_type;
- + 	u32				senp_mod;
- + 	u32				senn_mod;
- + 	int				nvalue_count;
- + 	bool				enable_on_init;
- + 	struct omap_sr_nvalue_table	*nvalue_table;
- + 	struct voltagedomain		*voltdm;
- + };
- + 
- + /* Smartreflex module enable/disable interface */
- + void omap_sr_enable(struct voltagedomain *voltdm);
- + void omap_sr_disable(struct voltagedomain *voltdm);
- + void omap_sr_disable_reset_volt(struct voltagedomain *voltdm);
- + 
- + /* API to register the pmic specific data with the smartreflex driver. */
- + void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data);
- + 
- + /* Smartreflex driver hooks to be called from Smartreflex class driver */
- + int sr_enable(struct voltagedomain *voltdm, unsigned long volt);
- + void sr_disable(struct voltagedomain *voltdm);
- + int sr_configure_errgen(struct voltagedomain *voltdm);
- + int sr_configure_minmax(struct voltagedomain *voltdm);
- + 
- + /* API to register the smartreflex class driver with the smartreflex driver */
- + int sr_register_class(struct omap_sr_class_data *class_data);
- + #else
- + static inline void omap_sr_enable(struct voltagedomain *voltdm) {}
- + static inline void omap_sr_disable(struct voltagedomain *voltdm) {}
- + static inline void omap_sr_disable_reset_volt(
- + 		struct voltagedomain *voltdm) {}
- + static inline void omap_sr_register_pmic(
- + 		struct omap_sr_pmic_data *pmic_data) {}
- + #endif
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/sram34xx.S linux-3.2.1/arch/arm/mach-ckb_3352/sram34xx.S
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/sram34xx.S	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/sram34xx.S	2014-05-15 13:25:14.003319096 +0900
- ***************
- *** 0 ****
- --- 1,346 ----
- + /*
- +  * linux/arch/arm/mach-omap3/sram.S
- +  *
- +  * Omap3 specific functions that need to be run in internal SRAM
- +  *
- +  * Copyright (C) 2004, 2007, 2008 Texas Instruments, Inc.
- +  * Copyright (C) 2008 Nokia Corporation
- +  *
- +  * Rajendra Nayak <rnayak@ti.com>
- +  * Richard Woodruff <r-woodruff2@ti.com>
- +  * Paul Walmsley
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation; either version 2 of
- +  * the License, or (at your option) any later version.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- +  * MA 02111-1307 USA
- +  */
- + #include <linux/linkage.h>
- + #include <asm/assembler.h>
- + #include <mach/hardware.h>
- + 
- + #include <mach/io.h>
- + 
- + #include "sdrc.h"
- + #include "cm2xxx_3xxx.h"
- + 
- + /*
- +  * This file needs be built unconditionally as ARM to interoperate correctly
- +  * with non-Thumb-2-capable firmware.
- +  */
- + 	.arm
- + 
- + 	.text
- + 
- + /* r1 parameters */
- + #define SDRC_NO_UNLOCK_DLL		0x0
- + #define SDRC_UNLOCK_DLL			0x1
- + 
- + /* SDRC_DLLA_CTRL bit settings */
- + #define FIXEDDELAY_SHIFT		24
- + #define FIXEDDELAY_MASK			(0xff << FIXEDDELAY_SHIFT)
- + #define DLLIDLE_MASK			0x4
- + 
- + /*
- +  * SDRC_DLLA_CTRL default values: TI hardware team indicates that
- +  * FIXEDDELAY should be initialized to 0xf.  This apparently was
- +  * empirically determined during process testing, so no derivation
- +  * was provided.
- +  */
- + #define FIXEDDELAY_DEFAULT		(0x0f << FIXEDDELAY_SHIFT)
- + 
- + /* SDRC_DLLA_STATUS bit settings */
- + #define LOCKSTATUS_MASK			0x4
- + 
- + /* SDRC_POWER bit settings */
- + #define SRFRONIDLEREQ_MASK		0x40
- + 
- + /* CM_IDLEST1_CORE bit settings */
- + #define ST_SDRC_MASK			0x2
- + 
- + /* CM_ICLKEN1_CORE bit settings */
- + #define EN_SDRC_MASK			0x2
- + 
- + /* CM_CLKSEL1_PLL bit settings */
- + #define CORE_DPLL_CLKOUT_DIV_SHIFT	0x1b
- + 
- + /*
- +  * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
- +  *
- +  * Params passed in registers:
- +  *  r0 = new M2 divider setting (only 1 and 2 supported right now)
- +  *  r1 = unlock SDRC DLL? (1 = yes, 0 = no).  Only unlock DLL for
- +  *      SDRC rates < 83MHz
- +  *  r2 = number of MPU cycles to wait for SDRC to stabilize after
- +  *      reprogramming the SDRC when switching to a slower MPU speed
- +  *  r3 = increasing SDRC rate? (1 = yes, 0 = no)
- +  *
- +  * Params passed via the stack. The needed params will be copied in SRAM
- +  *  before use by the code in SRAM (SDRAM is not accessible during SDRC
- +  *  reconfiguration):
- +  *  new SDRC_RFR_CTRL_0 register contents
- +  *  new SDRC_ACTIM_CTRL_A_0 register contents
- +  *  new SDRC_ACTIM_CTRL_B_0 register contents
- +  *  new SDRC_MR_0 register value
- +  *  new SDRC_RFR_CTRL_1 register contents
- +  *  new SDRC_ACTIM_CTRL_A_1 register contents
- +  *  new SDRC_ACTIM_CTRL_B_1 register contents
- +  *  new SDRC_MR_1 register value
- +  *
- +  * If the param SDRC_RFR_CTRL_1 is 0, the parameters are not programmed into
- +  * the SDRC CS1 registers
- +  *
- +  * NOTE: This code no longer attempts to program the SDRC AC timing and MR
- +  * registers.  This is because the code currently cannot ensure that all
- +  * L3 initiators (e.g., sDMA, IVA, DSS DISPC, etc.) are not accessing the
- +  * SDRAM when the registers are written.  If the registers are changed while
- +  * an initiator is accessing SDRAM, memory can be corrupted and/or the SDRC
- +  * may enter an unpredictable state.  In the future, the intent is to
- +  * re-enable this code in cases where we can ensure that no initiators are
- +  * touching the SDRAM.  Until that time, users who know that their use case
- +  * can satisfy the above requirement can enable the CONFIG_OMAP3_SDRC_AC_TIMING
- +  * option.
- +  *
- +  * Richard Woodruff notes that any changes to this code must be carefully
- +  * audited and tested to ensure that they don't cause a TLB miss while
- +  * the SDRAM is inaccessible.  Such a situation will crash the system
- +  * since it will cause the ARM MMU to attempt to walk the page tables.
- +  * These crashes may be intermittent.
- +  */
- + 	.align	3
- + ENTRY(omap3_sram_configure_core_dpll)
- + 	stmfd	sp!, {r1-r12, lr}	@ store regs to stack
- + 
- + 					@ pull the extra args off the stack
- + 					@  and store them in SRAM
- + 
- + /*
- +  * PC-relative stores are deprecated in ARMv7 and lead to undefined behaviour
- +  * in Thumb-2: use a r7 as a base instead.
- +  * Be careful not to clobber r7 when maintaing this file.
- +  */
- +  THUMB(	adr	r7, omap3_sram_configure_core_dpll			)
- + 	.macro strtext Rt:req, label:req
- +  ARM(	str	\Rt, \label						)
- +  THUMB(	str	\Rt, [r7, \label - omap3_sram_configure_core_dpll]	)
- + 	.endm
- + 
- + 	ldr	r4, [sp, #52]
- + 	strtext	r4, omap_sdrc_rfr_ctrl_0_val
- + 	ldr	r4, [sp, #56]
- + 	strtext	r4, omap_sdrc_actim_ctrl_a_0_val
- + 	ldr	r4, [sp, #60]
- + 	strtext	r4, omap_sdrc_actim_ctrl_b_0_val
- + 	ldr	r4, [sp, #64]
- + 	strtext	r4, omap_sdrc_mr_0_val
- + 	ldr	r4, [sp, #68]
- + 	strtext	r4, omap_sdrc_rfr_ctrl_1_val
- + 	cmp	r4, #0			@ if SDRC_RFR_CTRL_1 is 0,
- + 	beq	skip_cs1_params		@  do not use cs1 params
- + 	ldr	r4, [sp, #72]
- + 	strtext	r4, omap_sdrc_actim_ctrl_a_1_val
- + 	ldr	r4, [sp, #76]
- + 	strtext	r4, omap_sdrc_actim_ctrl_b_1_val
- + 	ldr	r4, [sp, #80]
- + 	strtext	r4, omap_sdrc_mr_1_val
- + skip_cs1_params:
- + 	mrc	p15, 0, r8, c1, c0, 0	@ read ctrl register
- + 	bic	r10, r8, #0x800		@ clear Z-bit, disable branch prediction
- + 	mcr	p15, 0, r10, c1, c0, 0	@ write ctrl register
- + 	dsb				@ flush buffered writes to interconnect
- + 	isb				@ prevent speculative exec past here
- + 	cmp	r3, #1			@ if increasing SDRC clk rate,
- + 	bleq	configure_sdrc		@ program the SDRC regs early (for RFR)
- + 	cmp	r1, #SDRC_UNLOCK_DLL	@ set the intended DLL state
- + 	bleq	unlock_dll
- + 	blne	lock_dll
- + 	bl	sdram_in_selfrefresh	@ put SDRAM in self refresh, idle SDRC
- + 	bl 	configure_core_dpll	@ change the DPLL3 M2 divider
- + 	mov	r12, r2
- + 	bl	wait_clk_stable		@ wait for SDRC to stabilize
- + 	bl	enable_sdrc		@ take SDRC out of idle
- + 	cmp	r1, #SDRC_UNLOCK_DLL	@ wait for DLL status to change
- + 	bleq	wait_dll_unlock
- + 	blne	wait_dll_lock
- + 	cmp	r3, #1			@ if increasing SDRC clk rate,
- + 	beq	return_to_sdram		@ return to SDRAM code, otherwise,
- + 	bl	configure_sdrc		@ reprogram SDRC regs now
- + return_to_sdram:
- + 	mcr	p15, 0, r8, c1, c0, 0	@ restore ctrl register
- + 	isb				@ prevent speculative exec past here
- + 	mov 	r0, #0 			@ return value
- + 	ldmfd	sp!, {r1-r12, pc}	@ restore regs and return
- + unlock_dll:
- + 	ldr	r11, omap3_sdrc_dlla_ctrl
- + 	ldr	r12, [r11]
- + 	bic	r12, r12, #FIXEDDELAY_MASK
- + 	orr	r12, r12, #FIXEDDELAY_DEFAULT
- + 	orr	r12, r12, #DLLIDLE_MASK
- + 	str	r12, [r11]		@ (no OCP barrier needed)
- + 	bx	lr
- + lock_dll:
- + 	ldr	r11, omap3_sdrc_dlla_ctrl
- + 	ldr	r12, [r11]
- + 	bic	r12, r12, #DLLIDLE_MASK
- + 	str	r12, [r11]		@ (no OCP barrier needed)
- + 	bx	lr
- + sdram_in_selfrefresh:
- + 	ldr	r11, omap3_sdrc_power	@ read the SDRC_POWER register
- + 	ldr	r12, [r11]		@ read the contents of SDRC_POWER
- + 	mov	r9, r12			@ keep a copy of SDRC_POWER bits
- + 	orr 	r12, r12, #SRFRONIDLEREQ_MASK	@ enable self refresh on idle
- + 	str 	r12, [r11]		@ write back to SDRC_POWER register
- + 	ldr	r12, [r11]		@ posted-write barrier for SDRC
- + idle_sdrc:
- + 	ldr	r11, omap3_cm_iclken1_core	@ read the CM_ICLKEN1_CORE reg
- + 	ldr	r12, [r11]
- + 	bic	r12, r12, #EN_SDRC_MASK		@ disable iclk bit for SDRC
- + 	str 	r12, [r11]
- + wait_sdrc_idle:
- + 	ldr 	r11, omap3_cm_idlest1_core
- + 	ldr 	r12, [r11]
- + 	and 	r12, r12, #ST_SDRC_MASK		@ check for SDRC idle
- + 	cmp 	r12, #ST_SDRC_MASK
- + 	bne 	wait_sdrc_idle
- + 	bx 	lr
- + configure_core_dpll:
- + 	ldr 	r11, omap3_cm_clksel1_pll
- + 	ldr	r12, [r11]
- + 	ldr	r10, core_m2_mask_val	@ modify m2 for core dpll
- + 	and	r12, r12, r10
- + 	orr	r12, r12, r0, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
- + 	str	r12, [r11]
- + 	ldr	r12, [r11]		@ posted-write barrier for CM
- + 	bx	lr
- + wait_clk_stable:
- + 	subs 	r12, r12, #1
- + 	bne	wait_clk_stable
- + 	bx	lr
- + enable_sdrc:
- + 	ldr 	r11, omap3_cm_iclken1_core
- + 	ldr	r12, [r11]
- + 	orr 	r12, r12, #EN_SDRC_MASK		@ enable iclk bit for SDRC
- + 	str 	r12, [r11]
- + wait_sdrc_idle1:
- + 	ldr 	r11, omap3_cm_idlest1_core
- + 	ldr	r12, [r11]
- + 	and 	r12, r12, #ST_SDRC_MASK
- + 	cmp	r12, #0
- + 	bne	wait_sdrc_idle1
- + restore_sdrc_power_val:
- + 	ldr	r11, omap3_sdrc_power
- + 	str	r9, [r11]		@ restore SDRC_POWER, no barrier needed
- + 	bx	lr
- + wait_dll_lock:
- + 	ldr	r11, omap3_sdrc_dlla_status
- + 	ldr	r12, [r11]
- + 	and 	r12, r12, #LOCKSTATUS_MASK
- + 	cmp	r12, #LOCKSTATUS_MASK
- + 	bne	wait_dll_lock
- + 	bx	lr
- + wait_dll_unlock:
- + 	ldr	r11, omap3_sdrc_dlla_status
- + 	ldr	r12, [r11]
- + 	and	r12, r12, #LOCKSTATUS_MASK
- + 	cmp	r12, #0x0
- + 	bne	wait_dll_unlock
- + 	bx	lr
- + configure_sdrc:
- + 	ldr	r12, omap_sdrc_rfr_ctrl_0_val	@ fetch value from SRAM
- + 	ldr	r11, omap3_sdrc_rfr_ctrl_0	@ fetch addr from SRAM
- + 	str	r12, [r11]			@ store
- + #ifdef CONFIG_OMAP3_SDRC_AC_TIMING
- + 	ldr	r12, omap_sdrc_actim_ctrl_a_0_val
- + 	ldr	r11, omap3_sdrc_actim_ctrl_a_0
- + 	str	r12, [r11]
- + 	ldr	r12, omap_sdrc_actim_ctrl_b_0_val
- + 	ldr	r11, omap3_sdrc_actim_ctrl_b_0
- + 	str	r12, [r11]
- + 	ldr	r12, omap_sdrc_mr_0_val
- + 	ldr	r11, omap3_sdrc_mr_0
- + 	str	r12, [r11]
- + #endif
- + 	ldr	r12, omap_sdrc_rfr_ctrl_1_val
- + 	cmp	r12, #0			@ if SDRC_RFR_CTRL_1 is 0,
- + 	beq	skip_cs1_prog		@  do not program cs1 params
- + 	ldr	r11, omap3_sdrc_rfr_ctrl_1
- + 	str	r12, [r11]
- + #ifdef CONFIG_OMAP3_SDRC_AC_TIMING
- + 	ldr	r12, omap_sdrc_actim_ctrl_a_1_val
- + 	ldr	r11, omap3_sdrc_actim_ctrl_a_1
- + 	str	r12, [r11]
- + 	ldr	r12, omap_sdrc_actim_ctrl_b_1_val
- + 	ldr	r11, omap3_sdrc_actim_ctrl_b_1
- + 	str	r12, [r11]
- + 	ldr	r12, omap_sdrc_mr_1_val
- + 	ldr	r11, omap3_sdrc_mr_1
- + 	str	r12, [r11]
- + #endif
- + skip_cs1_prog:
- + 	ldr	r12, [r11]		@ posted-write barrier for SDRC
- + 	bx	lr
- + 
- + 	.align
- + omap3_sdrc_power:
- + 	.word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
- + omap3_cm_clksel1_pll:
- + 	.word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
- + omap3_cm_idlest1_core:
- + 	.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
- + omap3_cm_iclken1_core:
- + 	.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
- + 
- + omap3_sdrc_rfr_ctrl_0:
- + 	.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
- + omap3_sdrc_rfr_ctrl_1:
- + 	.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_1)
- + omap3_sdrc_actim_ctrl_a_0:
- + 	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
- + omap3_sdrc_actim_ctrl_a_1:
- + 	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_1)
- + omap3_sdrc_actim_ctrl_b_0:
- + 	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
- + omap3_sdrc_actim_ctrl_b_1:
- + 	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_1)
- + omap3_sdrc_mr_0:
- + 	.word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
- + omap3_sdrc_mr_1:
- + 	.word OMAP34XX_SDRC_REGADDR(SDRC_MR_1)
- + omap_sdrc_rfr_ctrl_0_val:
- + 	.word 0xDEADBEEF
- + omap_sdrc_rfr_ctrl_1_val:
- + 	.word 0xDEADBEEF
- + omap_sdrc_actim_ctrl_a_0_val:
- + 	.word 0xDEADBEEF
- + omap_sdrc_actim_ctrl_a_1_val:
- + 	.word 0xDEADBEEF
- + omap_sdrc_actim_ctrl_b_0_val:
- + 	.word 0xDEADBEEF
- + omap_sdrc_actim_ctrl_b_1_val:
- + 	.word 0xDEADBEEF
- + omap_sdrc_mr_0_val:
- + 	.word 0xDEADBEEF
- + omap_sdrc_mr_1_val:
- + 	.word 0xDEADBEEF
- + 
- + omap3_sdrc_dlla_status:
- + 	.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
- + omap3_sdrc_dlla_ctrl:
- + 	.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
- + core_m2_mask_val:
- + 	.word 0x07FFFFFF
- + ENDPROC(omap3_sram_configure_core_dpll)
- + 
- + ENTRY(omap3_sram_configure_core_dpll_sz)
- + 	.word	. - omap3_sram_configure_core_dpll
- + 
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/timer.c linux-3.2.1/arch/arm/mach-ckb_3352/timer.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/timer.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/timer.c	2014-05-15 13:25:14.003319096 +0900
- ***************
- *** 0 ****
- --- 1,563 ----
- + /*
- +  * linux/arch/arm/mach-omap2/timer.c
- +  *
- +  * OMAP2 GP timer support.
- +  *
- +  * Copyright (C) 2009 Nokia Corporation
- +  *
- +  * Update to use new clocksource/clockevent layers
- +  * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
- +  * Copyright (C) 2007 MontaVista Software, Inc.
- +  *
- +  * Original driver:
- +  * Copyright (C) 2005 Nokia Corporation
- +  * Author: Paul Mundt <paul.mundt@nokia.com>
- +  *         Juha Yrjölä <juha.yrjola@nokia.com>
- +  * OMAP Dual-mode timer framework support by Timo Teras
- +  *
- +  * Some parts based off of TI's 24xx code:
- +  *
- +  * Copyright (C) 2004-2009 Texas Instruments, Inc.
- +  *
- +  * Roughly modelled after the OMAP1 MPU timer code.
- +  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
- +  *
- +  * This file is subject to the terms and conditions of the GNU General Public
- +  * License. See the file "COPYING" in the main directory of this archive
- +  * for more details.
- +  */
- + #include <linux/init.h>
- + #include <linux/time.h>
- + #include <linux/interrupt.h>
- + #include <linux/err.h>
- + #include <linux/clk.h>
- + #include <linux/delay.h>
- + #include <linux/irq.h>
- + #include <linux/clocksource.h>
- + #include <linux/clockchips.h>
- + #include <linux/slab.h>
- + 
- + #include <asm/mach/time.h>
- + #include <plat/dmtimer.h>
- + #include <asm/localtimer.h>
- + #include <asm/sched_clock.h>
- + #include "common.h"
- + #include <plat/omap_hwmod.h>
- + #include <plat/omap_device.h>
- + #include <plat/omap-pm.h>
- + #include <plat/clock.h>
- + 
- + #include "clockdomain.h"
- + #include "powerdomain.h"
- + #include "cm2xxx_3xxx.h"
- + #include "cminst44xx.h"
- + 
- + /* Parent clocks, eventually these will come from the clock framework */
- + 
- + #define OMAP2_MPU_SOURCE	"sys_ck"
- + #define OMAP3_MPU_SOURCE	OMAP2_MPU_SOURCE
- + #define OMAP4_MPU_SOURCE	"sys_clkin_ck"
- + #define OMAP2_32K_SOURCE	"func_32k_ck"
- + #define OMAP3_32K_SOURCE	"omap_32k_fck"
- + #define OMAP4_32K_SOURCE	"sys_32k_ck"
- + #define AM33XX_RTC32K_SOURCE	"clk_32768_ck"
- + 
- + #ifdef CONFIG_OMAP_32K_TIMER
- + #define OMAP2_CLKEV_SOURCE	OMAP2_32K_SOURCE
- + #define OMAP3_CLKEV_SOURCE	OMAP3_32K_SOURCE
- + #define OMAP4_CLKEV_SOURCE	OMAP4_32K_SOURCE
- + #define OMAP3_SECURE_TIMER	12
- + #else
- + #define OMAP2_CLKEV_SOURCE	OMAP2_MPU_SOURCE
- + #define OMAP3_CLKEV_SOURCE	OMAP3_MPU_SOURCE
- + #define OMAP4_CLKEV_SOURCE	OMAP4_MPU_SOURCE
- + #define OMAP3_SECURE_TIMER	1
- + #endif
- + 
- + /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
- + #define MAX_GPTIMER_ID		12
- + 
- + static u32 sys_timer_reserved;
- + 
- + /* Clockevent code */
- + 
- + static struct omap_dm_timer clkev;
- + static struct clock_event_device clockevent_gpt;
- + 
- + static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
- + {
- + 	struct clock_event_device *evt = &clockevent_gpt;
- + 
- + 	__omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
- + 
- + 	evt->event_handler(evt);
- + 	return IRQ_HANDLED;
- + }
- + 
- + static struct irqaction omap2_gp_timer_irq = {
- + 	.name		= "gp timer",
- + 	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
- + 	.handler	= omap2_gp_timer_interrupt,
- + };
- + 
- + static int omap2_gp_timer_set_next_event(unsigned long cycles,
- + 					 struct clock_event_device *evt)
- + {
- + 	__omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
- + 						0xffffffff - cycles, 1);
- + 
- + 	return 0;
- + }
- + 
- + static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
- + 				    struct clock_event_device *evt)
- + {
- + 	u32 period;
- + 
- + 	__omap_dm_timer_stop(&clkev, 1, clkev.rate);
- + 
- + 	switch (mode) {
- + 	case CLOCK_EVT_MODE_PERIODIC:
- + 		period = clkev.rate / HZ;
- + 		period -= 1;
- + 		/* Looks like we need to first set the load value separately */
- + 		__omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
- + 					0xffffffff - period, 1);
- + 		__omap_dm_timer_load_start(&clkev,
- + 					OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
- + 						0xffffffff - period, 1);
- + 		break;
- + 	case CLOCK_EVT_MODE_ONESHOT:
- + 		break;
- + 	case CLOCK_EVT_MODE_UNUSED:
- + 	case CLOCK_EVT_MODE_SHUTDOWN:
- + 	case CLOCK_EVT_MODE_RESUME:
- + 		break;
- + 	}
- + }
- + 
- + static struct clock_event_device clockevent_gpt = {
- + 	.name		= "gp timer",
- + 	.features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
- + 	.shift		= 32,
- + 	.set_next_event	= omap2_gp_timer_set_next_event,
- + 	.set_mode	= omap2_gp_timer_set_mode,
- + };
- + 
- + static int _is_timer_idle(struct omap_hwmod *oh)
- + {
- + 	int ret;
- + 
- + 	if (!oh->clkdm)
- + 		return -EINVAL;
- + 	ret = omap4_cminst_wait_module_ready(oh->clkdm->prcm_partition,
- + 			oh->clkdm->cm_inst,
- + 			oh->clkdm->clkdm_offs,
- + 			oh->prcm.omap4.clkctrl_offs);
- + 	return ret;
- + }
- + 
- + static int omap_dm_timer_switch_src(struct omap_hwmod *oh,
- + 		struct omap_dm_timer *timer, const char *fck_source)
- + {
- + 	struct clk *src, *cur_parent;
- + 	int res;
- + 
- + 	src = clk_get(NULL, fck_source);
- + 	if (IS_ERR(src))
- + 		return -EINVAL;
- + 
- + 	/* Reserve HW/clock-tree default source for fallback */
- + 	cur_parent = clk_get_parent(timer->fclk);
- + 
- + 	/* Switch to configured source */
- + 	res = __omap_dm_timer_set_source(timer->fclk, src);
- + 	if (IS_ERR_VALUE(res))
- + 		pr_warning("%s: timer%i cannot set source\n",
- + 				__func__, timer->id);
- + 
- + 	/* Check whether timer module is went into idle state */
- + 	res = _is_timer_idle(oh);
- + 	if (res && cur_parent) {
- + 		/* Fallback to default timer source */
- + 		pr_warning("%s: Switching to HW default clocksource(%s) for "
- + 				"timer%i, this may impact timekeeping in low "
- + 				"power state\n",
- + 				__func__, cur_parent->name, timer->id);
- + 
- + 		res = __omap_dm_timer_set_source(timer->fclk, cur_parent);
- + 		if (IS_ERR_VALUE(res))
- + 			pr_warning("%s: timer%i cannot set source\n",
- + 					__func__, timer->id);
- + 	}
- + 	clk_put(src);
- + 
- + 	return res;
- + }
- + 
- + static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
- + 						int gptimer_id,
- + 						const char *fck_source)
- + {
- + 	char name[10]; /* 10 = sizeof("gptXX_Xck0") */
- + 	struct omap_hwmod *oh;
- + 	size_t size;
- + 	int res = 0;
- + 
- + 	sprintf(name, "timer%d", gptimer_id);
- + 	omap_hwmod_setup_one(name);
- + 	oh = omap_hwmod_lookup(name);
- + 	if (!oh)
- + 		return -ENODEV;
- + 
- + 	timer->irq = oh->mpu_irqs[0].irq;
- + 	timer->id = gptimer_id;
- + 	timer->phys_base = oh->slaves[0]->addr->pa_start;
- + 	size = oh->slaves[0]->addr->pa_end - timer->phys_base;
- + 
- + 	/* Static mapping, never released */
- + 	timer->io_base = ioremap(timer->phys_base, size);
- + 	if (!timer->io_base)
- + 		return -ENXIO;
- + 
- + 	/* After the dmtimer is using hwmod these clocks won't be needed */
- + 	sprintf(name, "gpt%d_fck", gptimer_id);
- + 	timer->fclk = clk_get(NULL, name);
- + 	if (IS_ERR(timer->fclk))
- + 		return -ENODEV;
- + 
- + 	sprintf(name, "gpt%d_ick", gptimer_id);
- + 	timer->iclk = clk_get(NULL, name);
- + 	if (IS_ERR(timer->iclk)) {
- + 		clk_put(timer->fclk);
- + 		return -ENODEV;
- + 	}
- + 
- + 	omap_hwmod_enable(oh);
- + 
- + 	sys_timer_reserved |= (1 << (gptimer_id));
- + 
- + 	if (gptimer_id != 12) {
- + 		res = omap_dm_timer_switch_src(oh, timer, fck_source);
- + 	}
- + 	__omap_dm_timer_init_regs(timer);
- + 	__omap_dm_timer_reset(timer, 1, 1);
- + 	timer->posted = 1;
- + 
- + 	timer->rate = clk_get_rate(timer->fclk);
- + 
- + 	timer->reserved = 1;
- + 
- + 	return res;
- + }
- + 
- + static void __init omap2_gp_clockevent_init(int gptimer_id,
- + 						const char *fck_source)
- + {
- + 	int res;
- + 
- + 	res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
- + 	BUG_ON(res);
- + 
- + 	omap2_gp_timer_irq.dev_id = (void *)&clkev;
- + 	setup_irq(clkev.irq, &omap2_gp_timer_irq);
- + 
- + 	__omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
- + 
- + 	clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
- + 				     clockevent_gpt.shift);
- + 	clockevent_gpt.max_delta_ns =
- + 		clockevent_delta2ns(0xffffffff, &clockevent_gpt);
- + 	clockevent_gpt.min_delta_ns =
- + 		clockevent_delta2ns(3, &clockevent_gpt);
- + 		/* Timer internal resynch latency. */
- + 
- + 	clockevent_gpt.cpumask = cpumask_of(0);
- + 	clockevents_register_device(&clockevent_gpt);
- + 
- + 	pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
- + 		gptimer_id, clkev.rate);
- + }
- + 
- + /* Clocksource code */
- + 
- + #ifdef CONFIG_OMAP_32K_TIMER
- + /*
- +  * When 32k-timer is enabled, don't use GPTimer for clocksource
- +  * instead, just leave default clocksource which uses the 32k
- +  * sync counter.  See clocksource setup in plat-omap/counter_32k.c
- +  */
- + 
- + static void __init omap2_gp_clocksource_init(int unused, const char *dummy)
- + {
- + 	omap_init_clocksource_32k();
- + }
- + 
- + #else
- + 
- + static struct omap_dm_timer clksrc;
- + 
- + /*
- +  * clocksource
- +  */
- + static DEFINE_CLOCK_DATA(cd);
- + static cycle_t clocksource_read_cycles(struct clocksource *cs)
- + {
- + 	return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1);
- + }
- + 
- + static struct clocksource clocksource_gpt = {
- + 	.name		= "gp timer",
- + 	.rating		= 300,
- + 	.read		= clocksource_read_cycles,
- + 	.mask		= CLOCKSOURCE_MASK(32),
- + 	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
- + };
- + 
- + static void notrace dmtimer_update_sched_clock(void)
- + {
- + 	u32 cyc;
- + 
- + 	cyc = __omap_dm_timer_read_counter(&clksrc, 1);
- + 
- + 	update_sched_clock(&cd, cyc, (u32)~0);
- + }
- + 
- + unsigned long long notrace sched_clock(void)
- + {
- + 	u32 cyc = 0;
- + 
- + 	if (clksrc.reserved)
- + 		cyc = __omap_dm_timer_read_counter(&clksrc, 1);
- + 
- + 	return cyc_to_sched_clock(&cd, cyc, (u32)~0);
- + }
- + 
- + /* Setup free-running counter for clocksource */
- + static void __init omap2_gp_clocksource_init(int gptimer_id,
- + 						const char *fck_source)
- + {
- + 	int res;
- + 
- + 	res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source);
- + 	BUG_ON(res);
- + 
- + 	pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
- + 		gptimer_id, clksrc.rate);
- + 
- + 	__omap_dm_timer_load_start(&clksrc,
- + 			OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
- + 	init_sched_clock(&cd, dmtimer_update_sched_clock, 32, clksrc.rate);
- + 
- + 	if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
- + 		pr_err("Could not register clocksource %s\n",
- + 			clocksource_gpt.name);
- + }
- + #endif
- + 
- + static void omap_dmtimer_resume(void)
- + {
- + 	char name[10];
- + 	struct omap_hwmod *oh;
- + 
- + 	sprintf(name, "timer%d", clkev.id);
- + 	oh = omap_hwmod_lookup(name);
- + 	if (!oh)
- + 		return;
- + 
- + 	omap_hwmod_enable(oh);
- + 	__omap_dm_timer_load_start(&clkev,
- + 			OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
- + 	__omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
- + }
- + 
- + static void omap_dmtimer_suspend(void)
- + {
- + 	char name[10];
- + 	struct omap_hwmod *oh;
- + 
- + 	sprintf(name, "timer%d", clkev.id);
- + 	oh = omap_hwmod_lookup(name);
- + 	if (!oh)
- + 		return;
- + 
- + 	omap_hwmod_idle(oh);
- + }
- + 
- + #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src,			\
- + 				clksrc_nr, clksrc_src)			\
- + static void __init omap##name##_timer_init(void)			\
- + {									\
- + 	omap2_gp_clockevent_init((clkev_nr), clkev_src);		\
- + 	omap2_gp_clocksource_init((clksrc_nr), clksrc_src);		\
- + }
- + 
- + #define OMAP_SYS_TIMER(name)						\
- + struct sys_timer omap##name##_timer = {					\
- + 	.init		= omap##name##_timer_init,			\
- + 	.suspend	= omap_dmtimer_suspend,				\
- + 	.resume		= omap_dmtimer_resume,				\
- + };
- + 
- + OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
- + OMAP_SYS_TIMER(3)
- + OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
- + 			2, OMAP3_MPU_SOURCE)
- + OMAP_SYS_TIMER(3_secure)
- + OMAP_SYS_TIMER_INIT(3_am33xx, 2, OMAP4_MPU_SOURCE, 1, AM33XX_RTC32K_SOURCE)
- + OMAP_SYS_TIMER(3_am33xx)
- + 
- + 
- + /**
- +  * omap2_dm_timer_set_src - change the timer input clock source
- +  * @pdev:	timer platform device pointer
- +  * @source:	array index of parent clock source
- +  */
- + static int omap2_dm_timer_set_src(struct platform_device *pdev, int source)
- + {
- + 	int ret;
- + 	struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
- + 	struct clk *fclk, *parent;
- + 	char *parent_name = NULL;
- + 
- + 	fclk = clk_get(&pdev->dev, "fck");
- + 	if (IS_ERR_OR_NULL(fclk)) {
- + 		dev_err(&pdev->dev, "%s: %d: clk_get() FAILED\n",
- + 				__func__, __LINE__);
- + 		return -EINVAL;
- + 	}
- + 
- + 	switch (source) {
- + 	case OMAP_TIMER_SRC_SYS_CLK:
- + 		parent_name = "sys_ck";
- + 		break;
- + 
- + 	case OMAP_TIMER_SRC_32_KHZ:
- + 		parent_name = "32k_ck";
- + 		break;
- + 
- + 	case OMAP_TIMER_SRC_EXT_CLK:
- + 		if (pdata->timer_ip_version == OMAP_TIMER_IP_VERSION_1) {
- + 			parent_name = "alt_ck";
- + 			break;
- + 		}
- + 		dev_err(&pdev->dev, "%s: %d: invalid clk src.\n",
- + 			__func__, __LINE__);
- + 		clk_put(fclk);
- + 		return -EINVAL;
- + 	}
- + 
- + 	parent = clk_get(&pdev->dev, parent_name);
- + 	if (IS_ERR_OR_NULL(parent)) {
- + 		dev_err(&pdev->dev, "%s: %d: clk_get() %s FAILED\n",
- + 			__func__, __LINE__, parent_name);
- + 		clk_put(fclk);
- + 		return -EINVAL;
- + 	}
- + 
- + 	ret = clk_set_parent(fclk, parent);
- + 	if (IS_ERR_VALUE(ret)) {
- + 		dev_err(&pdev->dev, "%s: clk_set_parent() to %s FAILED\n",
- + 			__func__, parent_name);
- + 		ret = -EINVAL;
- + 	}
- + 
- + 	clk_put(parent);
- + 	clk_put(fclk);
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * omap_timer_init - build and register timer device with an
- +  * associated timer hwmod
- +  * @oh:	timer hwmod pointer to be used to build timer device
- +  * @user:	parameter that can be passed from calling hwmod API
- +  *
- +  * Called by omap_hwmod_for_each_by_class to register each of the timer
- +  * devices present in the system. The number of timer devices is known
- +  * by parsing through the hwmod database for a given class name. At the
- +  * end of function call memory is allocated for timer device and it is
- +  * registered to the framework ready to be proved by the driver.
- +  */
- + static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
- + {
- + 	int id;
- + 	int ret = 0;
- + 	char *name = "omap_timer";
- + 	struct dmtimer_platform_data *pdata;
- + 	struct platform_device *pdev;
- + 	struct omap_timer_capability_dev_attr *timer_dev_attr;
- + 	struct powerdomain *pwrdm;
- + 
- + 	pr_debug("%s: %s\n", __func__, oh->name);
- + 
- + 	/* on secure device, do not register secure timer */
- + 	timer_dev_attr = oh->dev_attr;
- + 	if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr)
- + 		if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE)
- + 			return ret;
- + 
- + 	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
- + 	if (!pdata) {
- + 		pr_err("%s: No memory for [%s]\n", __func__, oh->name);
- + 		return -ENOMEM;
- + 	}
- + 
- + 	/*
- + 	 * Extract the IDs from name field in hwmod database
- + 	 * and use the same for constructing ids' for the
- + 	 * timer devices. In a way, we are avoiding usage of
- + 	 * static variable witin the function to do the same.
- + 	 * CAUTION: We have to be careful and make sure the
- + 	 * name in hwmod database does not change in which case
- + 	 * we might either make corresponding change here or
- + 	 * switch back static variable mechanism.
- + 	 */
- + 	sscanf(oh->name, "timer%2d", &id);
- + 
- + 	pdata->set_timer_src = omap2_dm_timer_set_src;
- + 	pdata->timer_ip_version = oh->class->rev;
- + 
- + 	/* Mark clocksource and clockevent timers as reserved */
- + 	if ((sys_timer_reserved & (0x1 << id)))
- + 		pdata->reserved = 1;
- + 
- + 	pwrdm = omap_hwmod_get_pwrdm(oh);
- + 	pdata->loses_context = pwrdm_can_ever_lose_context(pwrdm);
- + #ifdef CONFIG_PM
- + 	pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
- + #endif
- + 	pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
- + 				 NULL, 0, 0);
- + 
- + 	if (IS_ERR(pdev)) {
- + 		pr_err("%s: Can't build omap_device for %s: %s.\n",
- + 			__func__, name, oh->name);
- + 		ret = -EINVAL;
- + 	}
- + 
- + 	kfree(pdata);
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * omap2_dm_timer_init - top level regular device initialization
- +  *
- +  * Uses dedicated hwmod api to parse through hwmod database for
- +  * given class name and then build and register the timer device.
- +  */
- + static int __init omap2_dm_timer_init(void)
- + {
- + 	int ret;
- + 
- + 	ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL);
- + 	if (unlikely(ret)) {
- + 		pr_err("%s: device registration failed.\n", __func__);
- + 		return -EINVAL;
- + 	}
- + 
- + 	return 0;
- + }
- + arch_initcall(omap2_dm_timer_init);
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/twl-common.h linux-3.2.1/arch/arm/mach-ckb_3352/twl-common.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/twl-common.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/twl-common.h	2014-05-15 13:25:14.003319096 +0900
- ***************
- *** 0 ****
- --- 1,55 ----
- + #ifndef __OMAP_PMIC_COMMON__
- + #define __OMAP_PMIC_COMMON__
- + 
- + #include <plat/irqs.h>
- + 
- + #define TWL_COMMON_PDATA_USB		(1 << 0)
- + #define TWL_COMMON_PDATA_BCI		(1 << 1)
- + #define TWL_COMMON_PDATA_MADC		(1 << 2)
- + #define TWL_COMMON_PDATA_AUDIO		(1 << 3)
- + 
- + /* Common LDO regulators for TWL4030/TWL6030 */
- + #define TWL_COMMON_REGULATOR_VDAC	(1 << 0)
- + #define TWL_COMMON_REGULATOR_VAUX1	(1 << 1)
- + #define TWL_COMMON_REGULATOR_VAUX2	(1 << 2)
- + #define TWL_COMMON_REGULATOR_VAUX3	(1 << 3)
- + 
- + /* TWL6030 LDO regulators */
- + #define TWL_COMMON_REGULATOR_VMMC	(1 << 4)
- + #define TWL_COMMON_REGULATOR_VPP	(1 << 5)
- + #define TWL_COMMON_REGULATOR_VUSIM	(1 << 6)
- + #define TWL_COMMON_REGULATOR_VANA	(1 << 7)
- + #define TWL_COMMON_REGULATOR_VCXIO	(1 << 8)
- + #define TWL_COMMON_REGULATOR_VUSB	(1 << 9)
- + #define TWL_COMMON_REGULATOR_CLK32KG	(1 << 10)
- + 
- + /* TWL4030 LDO regulators */
- + #define TWL_COMMON_REGULATOR_VPLL1	(1 << 4)
- + #define TWL_COMMON_REGULATOR_VPLL2	(1 << 5)
- + 
- + 
- + struct twl4030_platform_data;
- + 
- + void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq,
- + 		    struct twl4030_platform_data *pmic_data);
- + void omap_pmic_late_init(void);
- + 
- + static inline void omap2_pmic_init(const char *pmic_type,
- + 				   struct twl4030_platform_data *pmic_data)
- + {
- + 	omap_pmic_init(2, 2600, pmic_type, INT_24XX_SYS_NIRQ, pmic_data);
- + }
- + 
- + static inline void omap3_pmic_init(const char *pmic_type,
- + 				   struct twl4030_platform_data *pmic_data)
- + {
- + 	omap_pmic_init(1, 2600, pmic_type, INT_34XX_SYS_NIRQ, pmic_data);
- + }
- + 
- + void omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
- + 			   u32 pdata_flags, u32 regulators_flags);
- + 
- + void omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
- + 			   u32 pdata_flags, u32 regulators_flags);
- + 
- + #endif /* __OMAP_PMIC_COMMON__ */
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/usb-host.c linux-3.2.1/arch/arm/mach-ckb_3352/usb-host.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/usb-host.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/usb-host.c	2014-05-15 13:25:14.003319096 +0900
- ***************
- *** 0 ****
- --- 1,348 ----
- + /*
- +  * usb-host.c - OMAP USB Host
- +  *
- +  * This file will contain the board specific details for the
- +  * Synopsys EHCI/OHCI host controller on OMAP3430 and onwards
- +  *
- +  * Copyright (C) 2007-2011 Texas Instruments
- +  * Author: Vikram Pandita <vikram.pandita@ti.com>
- +  * Author: Keshava Munegowda <keshava_mgowda@ti.com>
- +  *
- +  * Generalization by:
- +  * Felipe Balbi <balbi@ti.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #include <linux/types.h>
- + #include <linux/errno.h>
- + #include <linux/delay.h>
- + #include <linux/platform_device.h>
- + #include <linux/slab.h>
- + #include <linux/dma-mapping.h>
- + 
- + #include <asm/io.h>
- + 
- + #include <mach/hardware.h>
- + #include <mach/irqs.h>
- + #include <plat/usb.h>
- + #include <plat/omap_device.h>
- + 
- + #include "mux.h"
- + 
- + #ifdef CONFIG_MFD_OMAP_USB_HOST
- + 
- + #define OMAP_USBHS_DEVICE	"usbhs_omap"
- + #define	USBHS_UHH_HWMODNAME	"usb_host_hs"
- + #define USBHS_TLL_HWMODNAME	"usb_tll_hs"
- + 
- + static struct usbhs_omap_platform_data		usbhs_data;
- + static struct ehci_hcd_omap_platform_data	ehci_data;
- + static struct ohci_hcd_omap_platform_data	ohci_data;
- + 
- + static struct omap_device_pm_latency omap_uhhtll_latency[] = {
- + 	  {
- + 		.deactivate_func = omap_device_idle_hwmods,
- + 		.activate_func	 = omap_device_enable_hwmods,
- + 		.flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
- + 	  },
- + };
- + 
- + /* MUX settings for EHCI pins */
- + /*
- +  * setup_ehci_io_mux - initialize IO pad mux for USBHOST
- +  */
- + static void setup_ehci_io_mux(const enum usbhs_omap_port_mode *port_mode)
- + {
- + 	switch (port_mode[0]) {
- + 	case OMAP_EHCI_PORT_MODE_PHY:
- + 		omap_mux_init_signal("hsusb1_stp", OMAP_PIN_OUTPUT);
- + 		omap_mux_init_signal("hsusb1_clk", OMAP_PIN_OUTPUT);
- + 		omap_mux_init_signal("hsusb1_dir", OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb1_nxt", OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb1_data0", OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb1_data1", OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb1_data2", OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb1_data3", OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb1_data4", OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb1_data5", OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb1_data6", OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb1_data7", OMAP_PIN_INPUT_PULLDOWN);
- + 		break;
- + 	case OMAP_EHCI_PORT_MODE_TLL:
- + 		omap_mux_init_signal("hsusb1_tll_stp",
- + 			OMAP_PIN_INPUT_PULLUP);
- + 		omap_mux_init_signal("hsusb1_tll_clk",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb1_tll_dir",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb1_tll_nxt",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb1_tll_data0",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb1_tll_data1",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb1_tll_data2",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb1_tll_data3",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb1_tll_data4",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb1_tll_data5",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb1_tll_data6",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb1_tll_data7",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		break;
- + 	case OMAP_USBHS_PORT_MODE_UNUSED:
- + 		/* FALLTHROUGH */
- + 	default:
- + 		break;
- + 	}
- + 
- + 	switch (port_mode[1]) {
- + 	case OMAP_EHCI_PORT_MODE_PHY:
- + 		omap_mux_init_signal("hsusb2_stp", OMAP_PIN_OUTPUT);
- + 		omap_mux_init_signal("hsusb2_clk", OMAP_PIN_OUTPUT);
- + 		omap_mux_init_signal("hsusb2_dir", OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb2_nxt", OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb2_data0",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb2_data1",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb2_data2",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb2_data3",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb2_data4",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb2_data5",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb2_data6",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb2_data7",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		break;
- + 	case OMAP_EHCI_PORT_MODE_TLL:
- + 		omap_mux_init_signal("hsusb2_tll_stp",
- + 			OMAP_PIN_INPUT_PULLUP);
- + 		omap_mux_init_signal("hsusb2_tll_clk",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb2_tll_dir",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb2_tll_nxt",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb2_tll_data0",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb2_tll_data1",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb2_tll_data2",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb2_tll_data3",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb2_tll_data4",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb2_tll_data5",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb2_tll_data6",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb2_tll_data7",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		break;
- + 	case OMAP_USBHS_PORT_MODE_UNUSED:
- + 		/* FALLTHROUGH */
- + 	default:
- + 		break;
- + 	}
- + 
- + 	switch (port_mode[2]) {
- + 	case OMAP_EHCI_PORT_MODE_PHY:
- + 		printk(KERN_WARNING "Port3 can't be used in PHY mode\n");
- + 		break;
- + 	case OMAP_EHCI_PORT_MODE_TLL:
- + 		omap_mux_init_signal("hsusb3_tll_stp",
- + 			OMAP_PIN_INPUT_PULLUP);
- + 		omap_mux_init_signal("hsusb3_tll_clk",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb3_tll_dir",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb3_tll_nxt",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb3_tll_data0",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb3_tll_data1",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb3_tll_data2",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb3_tll_data3",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb3_tll_data4",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb3_tll_data5",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb3_tll_data6",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("hsusb3_tll_data7",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		break;
- + 	case OMAP_USBHS_PORT_MODE_UNUSED:
- + 		/* FALLTHROUGH */
- + 	default:
- + 		break;
- + 	}
- + 
- + 	return;
- + }
- + 
- + static void setup_ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
- + {
- + 	switch (port_mode[0]) {
- + 	case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
- + 	case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
- + 	case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
- + 	case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
- + 		omap_mux_init_signal("mm1_rxdp",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("mm1_rxdm",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		/* FALLTHROUGH */
- + 	case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
- + 	case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
- + 		omap_mux_init_signal("mm1_rxrcv",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		/* FALLTHROUGH */
- + 	case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
- + 	case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
- + 		omap_mux_init_signal("mm1_txen_n", OMAP_PIN_OUTPUT);
- + 		/* FALLTHROUGH */
- + 	case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
- + 	case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
- + 		omap_mux_init_signal("mm1_txse0",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("mm1_txdat",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		break;
- + 	case OMAP_USBHS_PORT_MODE_UNUSED:
- + 		/* FALLTHROUGH */
- + 	default:
- + 		break;
- + 	}
- + 	switch (port_mode[1]) {
- + 	case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
- + 	case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
- + 	case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
- + 	case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
- + 		omap_mux_init_signal("mm2_rxdp",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("mm2_rxdm",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		/* FALLTHROUGH */
- + 	case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
- + 	case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
- + 		omap_mux_init_signal("mm2_rxrcv",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		/* FALLTHROUGH */
- + 	case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
- + 	case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
- + 		omap_mux_init_signal("mm2_txen_n", OMAP_PIN_OUTPUT);
- + 		/* FALLTHROUGH */
- + 	case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
- + 	case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
- + 		omap_mux_init_signal("mm2_txse0",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("mm2_txdat",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		break;
- + 	case OMAP_USBHS_PORT_MODE_UNUSED:
- + 		/* FALLTHROUGH */
- + 	default:
- + 		break;
- + 	}
- + 	switch (port_mode[2]) {
- + 	case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
- + 	case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
- + 	case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
- + 	case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
- + 		omap_mux_init_signal("mm3_rxdp",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("mm3_rxdm",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		/* FALLTHROUGH */
- + 	case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
- + 	case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
- + 		omap_mux_init_signal("mm3_rxrcv",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		/* FALLTHROUGH */
- + 	case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
- + 	case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
- + 		omap_mux_init_signal("mm3_txen_n", OMAP_PIN_OUTPUT);
- + 		/* FALLTHROUGH */
- + 	case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
- + 	case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
- + 		omap_mux_init_signal("mm3_txse0",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		omap_mux_init_signal("mm3_txdat",
- + 			OMAP_PIN_INPUT_PULLDOWN);
- + 		break;
- + 	case OMAP_USBHS_PORT_MODE_UNUSED:
- + 		/* FALLTHROUGH */
- + 	default:
- + 		break;
- + 	}
- + }
- + 
- + void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
- + {
- + 	struct omap_hwmod	*oh[2];
- + 	struct omap_device	*od;
- + 	int			bus_id = -1;
- + 	int			i;
- + 
- + 	for (i = 0; i < OMAP3_HS_USB_PORTS; i++) {
- + 		usbhs_data.port_mode[i] = pdata->port_mode[i];
- + 		ohci_data.port_mode[i] = pdata->port_mode[i];
- + 		ehci_data.port_mode[i] = pdata->port_mode[i];
- + 		ehci_data.reset_gpio_port[i] = pdata->reset_gpio_port[i];
- + 		ehci_data.regulator[i] = pdata->regulator[i];
- + 	}
- + 	ehci_data.phy_reset = pdata->phy_reset;
- + 	ohci_data.es2_compatibility = pdata->es2_compatibility;
- + 	usbhs_data.ehci_data = &ehci_data;
- + 	usbhs_data.ohci_data = &ohci_data;
- + 
- + 	setup_ehci_io_mux(pdata->port_mode);
- + 	setup_ohci_io_mux(pdata->port_mode);
- + 	
- + 	oh[0] = omap_hwmod_lookup(USBHS_UHH_HWMODNAME);
- + 	if (!oh[0]) {
- + 		pr_err("Could not look up %s\n", USBHS_UHH_HWMODNAME);
- + 		return;
- + 	}
- + 
- + 	oh[1] = omap_hwmod_lookup(USBHS_TLL_HWMODNAME);
- + 	if (!oh[1]) {
- + 		pr_err("Could not look up %s\n", USBHS_TLL_HWMODNAME);
- + 		return;
- + 	}
- + 
- + 	od = omap_device_build_ss(OMAP_USBHS_DEVICE, bus_id, oh, 2,
- + 				(void *)&usbhs_data, sizeof(usbhs_data),
- + 				omap_uhhtll_latency,
- + 				ARRAY_SIZE(omap_uhhtll_latency), false);
- + 	if (IS_ERR(od)) {
- + 		pr_err("Could not build hwmod devices %s,%s\n",
- + 			USBHS_UHH_HWMODNAME, USBHS_TLL_HWMODNAME);
- + 		return;
- + 	}
- + }
- + 
- + #else
- + 
- + void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
- + {
- + }
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/usb-musb.c linux-3.2.1/arch/arm/mach-ckb_3352/usb-musb.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/usb-musb.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/usb-musb.c	2014-05-15 13:25:14.003319096 +0900
- ***************
- *** 0 ****
- --- 1,115 ----
- + /*
- +  * linux/arch/arm/mach-omap2/usb-musb.c
- +  *
- +  * This file will contain the board specific details for the
- +  * MENTOR USB OTG controller on OMAP3430
- +  *
- +  * Copyright (C) 2007-2008 Texas Instruments
- +  * Copyright (C) 2008 Nokia Corporation
- +  * Author: Vikram Pandita
- +  *
- +  * Generalization by:
- +  * Felipe Balbi <felipe.balbi@nokia.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #include <linux/types.h>
- + #include <linux/errno.h>
- + #include <linux/delay.h>
- + #include <linux/platform_device.h>
- + #include <linux/clk.h>
- + #include <linux/dma-mapping.h>
- + #include <linux/io.h>
- + 
- + #include <linux/usb/musb.h>
- + 
- + #include <mach/hardware.h>
- + #include <mach/irqs.h>
- + #include <plat/usb.h>
- + #include <plat/omap_device.h>
- + #include "mux.h"
- + 
- + static struct musb_hdrc_config musb_config = {
- + 	.fifo_mode	= 4,
- + 	.multipoint	= 1,
- + 	.dyn_fifo	= 1,
- + 	.num_eps	= 16,
- + 	.ram_bits	= 12,
- + };
- + 
- + static struct musb_hdrc_platform_data musb_plat[] = {
- + 	{
- + 		.config         = &musb_config,
- + 		.clock          = "ick",
- + 	},
- + 	{
- + 		.config         = &musb_config,
- + 		.clock          = "ick",
- + 	},
- + };
- + 
- + static u64 musb_dmamask = DMA_BIT_MASK(32);
- + 
- + static struct omap_musb_board_data musb_default_board_data = {
- + 	.interface_type		= MUSB_INTERFACE_ULPI,
- + 	.mode			= MUSB_OTG,
- + 	.power			= 100,
- + };
- + 
- + void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
- + {
- + 	struct omap_hwmod		*oh;
- + 	struct platform_device		*pdev;
- + 	struct device			*dev;
- + 	int				bus_id = -1;
- + 	const char			*oh_name, *name;
- + 	struct omap_musb_board_data	*board_data;
- + 
- + 	if (musb_board_data)
- + 		board_data = musb_board_data;
- + 	else
- + 		board_data = &musb_default_board_data;
- + 
- + 	/*
- + 	 * REVISIT: This line can be removed once all the platforms using
- + 	 * musb_core.c have been converted to use use clkdev.
- + 	 */
- + 	musb_plat[0].clock = "ick";
- + 	musb_plat[0].board_data = board_data;
- + 	musb_plat[0].power = board_data->power >> 1;
- + 	musb_plat[0].mode = board_data->mode;
- + 	musb_plat[0].extvbus = board_data->extvbus;
- + 
- + 	board_data->set_phy_power = ti81xx_musb_phy_power;
- + 	oh_name = "usb_otg_hs";
- + 	name = "musb-ti81xx";
- + 	board_data->grndis_for_host_rx = 0;
- + 	board_data->babble_ctrl = 0;
- + 	if (omap_rev() >= AM335X_REV_ES2_0) {
- + 		board_data->grndis_for_host_rx = 1;
- + 		board_data->babble_ctrl = 1;
- + 	}
- + 
- +         oh = omap_hwmod_lookup(oh_name);
- +         if (WARN(!oh, "%s: could not find omap_hwmod for %s\n",
- +                  __func__, oh_name))
- +                 return;
- + 
- + 	pdev = omap_device_build(name, bus_id, oh, &musb_plat,
- + 			       sizeof(musb_plat), NULL, 0, false);
- + 	if (IS_ERR(pdev)) {
- + 		pr_err("Could not build omap_device for %s %s\n",
- + 						name, oh_name);
- + 		return;
- + 	}
- + 
- + 	dev = &pdev->dev;
- + 	get_device(dev);
- + 	dev->dma_mask = &musb_dmamask;
- + 	dev->coherent_dma_mask = musb_dmamask;
- + 	put_device(dev);
- + 
- + }
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/vc3xxx_data.c linux-3.2.1/arch/arm/mach-ckb_3352/vc3xxx_data.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/vc3xxx_data.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/vc3xxx_data.c	2014-05-15 13:25:14.003319096 +0900
- ***************
- *** 0 ****
- --- 1,72 ----
- + /*
- +  * OMAP3 Voltage Controller (VC) data
- +  *
- +  * Copyright (C) 2007, 2010 Texas Instruments, Inc.
- +  * Rajendra Nayak <rnayak@ti.com>
- +  * Lesly A M <x0080970@ti.com>
- +  * Thara Gopinath <thara@ti.com>
- +  *
- +  * Copyright (C) 2008, 2011 Nokia Corporation
- +  * Kalle Jokiniemi
- +  * Paul Walmsley
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + #include <linux/io.h>
- + #include <linux/err.h>
- + #include <linux/init.h>
- + 
- + #include "common.h"
- + 
- + #include "prm-regbits-34xx.h"
- + #include "voltage.h"
- + 
- + #include "vc.h"
- + 
- + /*
- +  * VC data common to 34xx/36xx chips
- +  * XXX This stuff presumably belongs in the vc3xxx.c or vc.c file.
- +  */
- + static struct omap_vc_common omap3_vc_common = {
- + 	.bypass_val_reg	 = OMAP3_PRM_VC_BYPASS_VAL_OFFSET,
- + 	.data_shift	 = OMAP3430_DATA_SHIFT,
- + 	.slaveaddr_shift = OMAP3430_SLAVEADDR_SHIFT,
- + 	.regaddr_shift	 = OMAP3430_REGADDR_SHIFT,
- + 	.valid		 = OMAP3430_VALID_MASK,
- + 	.cmd_on_shift	 = OMAP3430_VC_CMD_ON_SHIFT,
- + 	.cmd_on_mask	 = OMAP3430_VC_CMD_ON_MASK,
- + 	.cmd_onlp_shift	 = OMAP3430_VC_CMD_ONLP_SHIFT,
- + 	.cmd_ret_shift	 = OMAP3430_VC_CMD_RET_SHIFT,
- + 	.cmd_off_shift	 = OMAP3430_VC_CMD_OFF_SHIFT,
- + 	.i2c_cfg_hsen_mask = OMAP3430_HSEN_MASK,
- + 	.i2c_cfg_reg	 = OMAP3_PRM_VC_I2C_CFG_OFFSET,
- + 	.i2c_mcode_mask	 = OMAP3430_MCODE_MASK,
- + };
- + 
- + struct omap_vc_channel omap3_vc_mpu = {
- + 	.common = &omap3_vc_common,
- + 	.smps_sa_reg	 = OMAP3_PRM_VC_SMPS_SA_OFFSET,
- + 	.smps_volra_reg	 = OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET,
- + 	.smps_cmdra_reg	 = OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET,
- + 	.cfg_channel_reg = OMAP3_PRM_VC_CH_CONF_OFFSET,
- + 	.cmdval_reg = OMAP3_PRM_VC_CMD_VAL_0_OFFSET,
- + 	.smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA0_MASK,
- + 	.smps_volra_mask = OMAP3430_VOLRA0_MASK,
- + 	.smps_cmdra_mask = OMAP3430_CMDRA0_MASK,
- + 	.cfg_channel_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT,
- + };
- + 
- + struct omap_vc_channel omap3_vc_core = {
- + 	.common = &omap3_vc_common,
- + 	.smps_sa_reg	 = OMAP3_PRM_VC_SMPS_SA_OFFSET,
- + 	.smps_volra_reg	 = OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET,
- + 	.smps_cmdra_reg	 = OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET,
- + 	.cfg_channel_reg = OMAP3_PRM_VC_CH_CONF_OFFSET,
- + 	.cmdval_reg = OMAP3_PRM_VC_CMD_VAL_1_OFFSET,
- + 	.smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA1_MASK,
- + 	.smps_volra_mask = OMAP3430_VOLRA1_MASK,
- + 	.smps_cmdra_mask = OMAP3430_CMDRA1_MASK,
- + 	.cfg_channel_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT,
- + };
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/vc.c linux-3.2.1/arch/arm/mach-ckb_3352/vc.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/vc.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/vc.c	2014-05-15 13:25:14.008187139 +0900
- ***************
- *** 0 ****
- --- 1,346 ----
- + /*
- +  * OMAP Voltage Controller (VC) interface
- +  *
- +  * Copyright (C) 2011 Texas Instruments, Inc.
- +  *
- +  * This file is licensed under the terms of the GNU General Public
- +  * License version 2. This program is licensed "as is" without any
- +  * warranty of any kind, whether express or implied.
- +  */
- + #include <linux/kernel.h>
- + #include <linux/delay.h>
- + #include <linux/init.h>
- + 
- + #include <plat/cpu.h>
- + 
- + #include "voltage.h"
- + #include "vc.h"
- + #include "prm-regbits-34xx.h"
- + #include "prm-regbits-44xx.h"
- + //#include "prm44xx.h"
- + 
- + /**
- +  * struct omap_vc_channel_cfg - describe the cfg_channel bitfield
- +  * @sa: bit for slave address
- +  * @rav: bit for voltage configuration register
- +  * @rac: bit for command configuration register
- +  * @racen: enable bit for RAC
- +  * @cmd: bit for command value set selection
- +  *
- +  * Channel configuration bits, common for OMAP3+
- +  * OMAP3 register: PRM_VC_CH_CONF
- +  * OMAP4 register: PRM_VC_CFG_CHANNEL
- +  * OMAP5 register: PRM_VC_SMPS_<voltdm>_CONFIG
- +  */
- + struct omap_vc_channel_cfg {
- + 	u8 sa;
- + 	u8 rav;
- + 	u8 rac;
- + 	u8 racen;
- + 	u8 cmd;
- + };
- + 
- + static struct omap_vc_channel_cfg vc_default_channel_cfg = {
- + 	.sa    = BIT(0),
- + 	.rav   = BIT(1),
- + 	.rac   = BIT(2),
- + 	.racen = BIT(3),
- + 	.cmd   = BIT(4),
- + };
- + 
- + /*
- +  * On OMAP3+, all VC channels have the above default bitfield
- +  * configuration, except the OMAP4 MPU channel.  This appears
- +  * to be a freak accident as every other VC channel has the
- +  * default configuration, thus creating a mutant channel config.
- +  */
- + static struct omap_vc_channel_cfg vc_mutant_channel_cfg = {
- + 	.sa    = BIT(0),
- + 	.rav   = BIT(2),
- + 	.rac   = BIT(3),
- + 	.racen = BIT(4),
- + 	.cmd   = BIT(1),
- + };
- + 
- + static struct omap_vc_channel_cfg *vc_cfg_bits;
- + #define CFG_CHANNEL_MASK 0x1f
- + 
- + /**
- +  * omap_vc_config_channel - configure VC channel to PMIC mappings
- +  * @voltdm: pointer to voltagdomain defining the desired VC channel
- +  *
- +  * Configures the VC channel to PMIC mappings for the following
- +  * PMIC settings
- +  * - i2c slave address (SA)
- +  * - voltage configuration address (RAV)
- +  * - command configuration address (RAC) and enable bit (RACEN)
- +  * - command values for ON, ONLP, RET and OFF (CMD)
- +  *
- +  * This function currently only allows flexible configuration of the
- +  * non-default channel.  Starting with OMAP4, there are more than 2
- +  * channels, with one defined as the default (on OMAP4, it's MPU.)
- +  * Only the non-default channel can be configured.
- +  */
- + static int omap_vc_config_channel(struct voltagedomain *voltdm)
- + {
- + 	struct omap_vc_channel *vc = voltdm->vc;
- + 
- + 	/*
- + 	 * For default channel, the only configurable bit is RACEN.
- + 	 * All others must stay at zero (see function comment above.)
- + 	 */
- + 	if (vc->flags & OMAP_VC_CHANNEL_DEFAULT)
- + 		vc->cfg_channel &= vc_cfg_bits->racen;
- + 
- + 	voltdm->rmw(CFG_CHANNEL_MASK << vc->cfg_channel_sa_shift,
- + 		    vc->cfg_channel << vc->cfg_channel_sa_shift,
- + 		    vc->cfg_channel_reg);
- + 
- + 	return 0;
- + }
- + 
- + /* Voltage scale and accessory APIs */
- + int omap_vc_pre_scale(struct voltagedomain *voltdm,
- + 		      unsigned long target_volt,
- + 		      u8 *target_vsel, u8 *current_vsel)
- + {
- + 	struct omap_vc_channel *vc = voltdm->vc;
- + 	u32 vc_cmdval;
- + 
- + 	/* Check if sufficient pmic info is available for this vdd */
- + 	if (!voltdm->pmic) {
- + 		pr_err("%s: Insufficient pmic info to scale the vdd_%s\n",
- + 			__func__, voltdm->name);
- + 		return -EINVAL;
- + 	}
- + 
- + 	if (!voltdm->pmic->uv_to_vsel) {
- + 		pr_err("%s: PMIC function to convert voltage in uV to"
- + 			"vsel not registered. Hence unable to scale voltage"
- + 			"for vdd_%s\n", __func__, voltdm->name);
- + 		return -ENODATA;
- + 	}
- + 
- + 	if (!voltdm->read || !voltdm->write) {
- + 		pr_err("%s: No read/write API for accessing vdd_%s regs\n",
- + 			__func__, voltdm->name);
- + 		return -EINVAL;
- + 	}
- + 
- + 	*target_vsel = voltdm->pmic->uv_to_vsel(target_volt);
- + 	*current_vsel = voltdm->pmic->uv_to_vsel(voltdm->nominal_volt);
- + 
- + 	/* Setting the ON voltage to the new target voltage */
- + 	vc_cmdval = voltdm->read(vc->cmdval_reg);
- + 	vc_cmdval &= ~vc->common->cmd_on_mask;
- + 	vc_cmdval |= (*target_vsel << vc->common->cmd_on_shift);
- + 	voltdm->write(vc_cmdval, vc->cmdval_reg);
- + 
- + 	omap_vp_update_errorgain(voltdm, target_volt);
- + 
- + 	return 0;
- + }
- + 
- + void omap_vc_post_scale(struct voltagedomain *voltdm,
- + 			unsigned long target_volt,
- + 			u8 target_vsel, u8 current_vsel)
- + {
- + 	u32 smps_steps = 0, smps_delay = 0;
- + 
- + 	smps_steps = abs(target_vsel - current_vsel);
- + 	/* SMPS slew rate / step size. 2us added as buffer. */
- + 	smps_delay = ((smps_steps * voltdm->pmic->step_size) /
- + 			voltdm->pmic->slew_rate) + 2;
- + 	udelay(smps_delay);
- + }
- + 
- + /* vc_bypass_scale - VC bypass method of voltage scaling */
- + int omap_vc_bypass_scale(struct voltagedomain *voltdm,
- + 			 unsigned long target_volt)
- + {
- + 	struct omap_vc_channel *vc = voltdm->vc;
- + 	u32 loop_cnt = 0, retries_cnt = 0;
- + 	u32 vc_valid, vc_bypass_val_reg, vc_bypass_value;
- + 	u8 target_vsel, current_vsel;
- + 	int ret;
- + 
- + 	ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, &current_vsel);
- + 	if (ret)
- + 		return ret;
- + 
- + 	vc_valid = vc->common->valid;
- + 	vc_bypass_val_reg = vc->common->bypass_val_reg;
- + 	vc_bypass_value = (target_vsel << vc->common->data_shift) |
- + 		(vc->volt_reg_addr << vc->common->regaddr_shift) |
- + 		(vc->i2c_slave_addr << vc->common->slaveaddr_shift);
- + 
- + 	voltdm->write(vc_bypass_value, vc_bypass_val_reg);
- + 	voltdm->write(vc_bypass_value | vc_valid, vc_bypass_val_reg);
- + 
- + 	vc_bypass_value = voltdm->read(vc_bypass_val_reg);
- + 	/*
- + 	 * Loop till the bypass command is acknowledged from the SMPS.
- + 	 * NOTE: This is legacy code. The loop count and retry count needs
- + 	 * to be revisited.
- + 	 */
- + 	while (!(vc_bypass_value & vc_valid)) {
- + 		loop_cnt++;
- + 
- + 		if (retries_cnt > 10) {
- + 			pr_warning("%s: Retry count exceeded\n", __func__);
- + 			return -ETIMEDOUT;
- + 		}
- + 
- + 		if (loop_cnt > 50) {
- + 			retries_cnt++;
- + 			loop_cnt = 0;
- + 			udelay(10);
- + 		}
- + 		vc_bypass_value = voltdm->read(vc_bypass_val_reg);
- + 	}
- + 
- + 	omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel);
- + 	return 0;
- + }
- + 
- + static void __init omap3_vfsm_init(struct voltagedomain *voltdm)
- + {
- + 	/*
- + 	 * Voltage Manager FSM parameters init
- + 	 * XXX This data should be passed in from the board file
- + 	 */
- + 	voltdm->write(OMAP3_CLKSETUP, OMAP3_PRM_CLKSETUP_OFFSET);
- + 	voltdm->write(OMAP3_VOLTOFFSET, OMAP3_PRM_VOLTOFFSET_OFFSET);
- + 	voltdm->write(OMAP3_VOLTSETUP2, OMAP3_PRM_VOLTSETUP2_OFFSET);
- + }
- + 
- + static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
- + {
- + 	static bool is_initialized;
- + 
- + 	if (is_initialized)
- + 		return;
- + 
- + 	omap3_vfsm_init(voltdm);
- + 
- + 	is_initialized = true;
- + }
- + 
- + /**
- +  * omap_vc_i2c_init - initialize I2C interface to PMIC
- +  * @voltdm: voltage domain containing VC data
- +  *
- +  * Use PMIC supplied seetings for I2C high-speed mode and
- +  * master code (if set) and program the VC I2C configuration
- +  * register.
- +  *
- +  * The VC I2C configuration is common to all VC channels,
- +  * so this function only configures I2C for the first VC
- +  * channel registers.  All other VC channels will use the
- +  * same configuration.
- +  */
- + static void __init omap_vc_i2c_init(struct voltagedomain *voltdm)
- + {
- + 	struct omap_vc_channel *vc = voltdm->vc;
- + 	static bool initialized;
- + 	static bool i2c_high_speed;
- + 	u8 mcode;
- + 
- + 	if (initialized) {
- + 		if (voltdm->pmic->i2c_high_speed != i2c_high_speed)
- + 			pr_warn("%s: I2C config for all channels must match.",
- + 				__func__);
- + 		return;
- + 	}
- + 
- + 	i2c_high_speed = voltdm->pmic->i2c_high_speed;
- + 	if (i2c_high_speed)
- + 		voltdm->rmw(vc->common->i2c_cfg_hsen_mask,
- + 			    vc->common->i2c_cfg_hsen_mask,
- + 			    vc->common->i2c_cfg_reg);
- + 
- + 	mcode = voltdm->pmic->i2c_mcode;
- + 	if (mcode)
- + 		voltdm->rmw(vc->common->i2c_mcode_mask,
- + 			    mcode << __ffs(vc->common->i2c_mcode_mask),
- + 			    vc->common->i2c_cfg_reg);
- + 
- + 	initialized = true;
- + }
- + 
- + void __init omap_vc_init_channel(struct voltagedomain *voltdm)
- + {
- + 	struct omap_vc_channel *vc = voltdm->vc;
- + 	u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
- + 	u32 val;
- + 
- + 	if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) {
- + 		pr_err("%s: missing PMIC for vdd_%s.\n",
- + 		       __func__, voltdm->name);
- + 		return;
- + 	}
- + 
- + 	if (!voltdm->read || !voltdm->write) {
- + 		pr_err("%s: No read/write API for accessing vdd_%s regs\n",
- + 			__func__, voltdm->name);
- + 		return;
- + 	}
- + 
- + 	vc->cfg_channel = 0;
- + 	if (vc->flags & OMAP_VC_CHANNEL_CFG_MUTANT)
- + 		vc_cfg_bits = &vc_mutant_channel_cfg;
- + 	else
- + 		vc_cfg_bits = &vc_default_channel_cfg;
- + 
- + 	/* get PMIC/board specific settings */
- + 	vc->i2c_slave_addr = voltdm->pmic->i2c_slave_addr;
- + 	vc->volt_reg_addr = voltdm->pmic->volt_reg_addr;
- + 	vc->cmd_reg_addr = voltdm->pmic->cmd_reg_addr;
- + 	vc->setup_time = voltdm->pmic->volt_setup_time;
- + 
- + 	/* Configure the i2c slave address for this VC */
- + 	voltdm->rmw(vc->smps_sa_mask,
- + 		    vc->i2c_slave_addr << __ffs(vc->smps_sa_mask),
- + 		    vc->smps_sa_reg);
- + 	vc->cfg_channel |= vc_cfg_bits->sa;
- + 
- + 	/*
- + 	 * Configure the PMIC register addresses.
- + 	 */
- + 	voltdm->rmw(vc->smps_volra_mask,
- + 		    vc->volt_reg_addr << __ffs(vc->smps_volra_mask),
- + 		    vc->smps_volra_reg);
- + 	vc->cfg_channel |= vc_cfg_bits->rav;
- + 
- + 	if (vc->cmd_reg_addr) {
- + 		voltdm->rmw(vc->smps_cmdra_mask,
- + 			    vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask),
- + 			    vc->smps_cmdra_reg);
- + 		vc->cfg_channel |= vc_cfg_bits->rac | vc_cfg_bits->racen;
- + 	}
- + 
- + 	/* Set up the on, inactive, retention and off voltage */
- + 	on_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->on_volt);
- + 	onlp_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->onlp_volt);
- + 	ret_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->ret_volt);
- + 	off_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->off_volt);
- + 	val = ((on_vsel << vc->common->cmd_on_shift) |
- + 	       (onlp_vsel << vc->common->cmd_onlp_shift) |
- + 	       (ret_vsel << vc->common->cmd_ret_shift) |
- + 	       (off_vsel << vc->common->cmd_off_shift));
- + 	voltdm->write(val, vc->cmdval_reg);
- + 	vc->cfg_channel |= vc_cfg_bits->cmd;
- + 
- + 	/* Channel configuration */
- + 	omap_vc_config_channel(voltdm);
- + 
- + 	/* Configure the setup times */
- + 	voltdm->rmw(voltdm->vfsm->voltsetup_mask,
- + 		    vc->setup_time << __ffs(voltdm->vfsm->voltsetup_mask),
- + 		    voltdm->vfsm->voltsetup_reg);
- + 
- + 	omap_vc_i2c_init(voltdm);
- + 
- + 	omap3_vc_init_channel(voltdm);
- + }
- + 
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/vc.h linux-3.2.1/arch/arm/mach-ckb_3352/vc.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/vc.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/vc.h	2014-05-15 13:25:14.008187139 +0900
- ***************
- *** 0 ****
- --- 1,125 ----
- + /*
- +  * OMAP3/4 Voltage Controller (VC) structure and macro definitions
- +  *
- +  * Copyright (C) 2007, 2010 Texas Instruments, Inc.
- +  * Rajendra Nayak <rnayak@ti.com>
- +  * Lesly A M <x0080970@ti.com>
- +  * Thara Gopinath <thara@ti.com>
- +  *
- +  * Copyright (C) 2008, 2011 Nokia Corporation
- +  * Kalle Jokiniemi
- +  * Paul Walmsley
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License version
- +  * 2 as published by the Free Software Foundation.
- +  */
- + #ifndef __ARCH_ARM_MACH_OMAP2_VC_H
- + #define __ARCH_ARM_MACH_OMAP2_VC_H
- + 
- + #include <linux/kernel.h>
- + 
- + struct voltagedomain;
- + 
- + /**
- +  * struct omap_vc_common - per-VC register/bitfield data
- +  * @cmd_on_mask: ON bitmask in PRM_VC_CMD_VAL* register
- +  * @valid: VALID bitmask in PRM_VC_BYPASS_VAL register
- +  * @bypass_val_reg: Offset of PRM_VC_BYPASS_VAL reg from PRM start
- +  * @data_shift: DATA field shift in PRM_VC_BYPASS_VAL register
- +  * @slaveaddr_shift: SLAVEADDR field shift in PRM_VC_BYPASS_VAL register
- +  * @regaddr_shift: REGADDR field shift in PRM_VC_BYPASS_VAL register
- +  * @cmd_on_shift: ON field shift in PRM_VC_CMD_VAL_* register
- +  * @cmd_onlp_shift: ONLP field shift in PRM_VC_CMD_VAL_* register
- +  * @cmd_ret_shift: RET field shift in PRM_VC_CMD_VAL_* register
- +  * @cmd_off_shift: OFF field shift in PRM_VC_CMD_VAL_* register
- +  * @i2c_cfg_reg: I2C configuration register offset
- +  * @i2c_cfg_hsen_mask: high-speed mode bit field mask in I2C config register
- +  * @i2c_mcode_mask: MCODE field mask for I2C config register
- +  *
- +  * XXX One of cmd_on_mask and cmd_on_shift are not needed
- +  * XXX VALID should probably be a shift, not a mask
- +  */
- + struct omap_vc_common {
- + 	u32 cmd_on_mask;
- + 	u32 valid;
- + 	u8 bypass_val_reg;
- + 	u8 data_shift;
- + 	u8 slaveaddr_shift;
- + 	u8 regaddr_shift;
- + 	u8 cmd_on_shift;
- + 	u8 cmd_onlp_shift;
- + 	u8 cmd_ret_shift;
- + 	u8 cmd_off_shift;
- + 	u8 i2c_cfg_reg;
- + 	u8 i2c_cfg_hsen_mask;
- + 	u8 i2c_mcode_mask;
- + };
- + 
- + /* omap_vc_channel.flags values */
- + #define OMAP_VC_CHANNEL_DEFAULT BIT(0)
- + #define OMAP_VC_CHANNEL_CFG_MUTANT BIT(1)
- + 
- + /**
- +  * struct omap_vc_channel - VC per-instance data
- +  * @i2c_slave_addr: I2C slave address of PMIC for this VC channel
- +  * @volt_reg_addr: voltage configuration register address
- +  * @cmd_reg_addr: command configuration register address
- +  * @setup_time: setup time (in sys_clk cycles) of regulator for this channel
- +  * @cfg_channel: current value of VC channel configuration register
- +  * @i2c_high_speed: whether or not to use I2C high-speed mode
- +  *
- +  * @common: pointer to VC common data for this platform
- +  * @smps_sa_mask: i2c slave address bitmask in the PRM_VC_SMPS_SA register
- +  * @smps_volra_mask: VOLRA* bitmask in the PRM_VC_VOL_RA register
- +  * @smps_cmdra_mask: CMDRA* bitmask in the PRM_VC_CMD_RA register
- +  * @cmdval_reg: register for on/ret/off voltage level values for this channel
- +  * @smps_sa_reg: Offset of PRM_VC_SMPS_SA reg from PRM start
- +  * @smps_volra_reg: Offset of PRM_VC_SMPS_VOL_RA reg from PRM start
- +  * @smps_cmdra_reg: Offset of PRM_VC_SMPS_CMD_RA reg from PRM start
- +  * @cfg_channel_reg: VC channel configuration register
- +  * @cfg_channel_sa_shift: bit shift for slave address cfg_channel register
- +  * @flags: VC channel-specific flags (optional)
- +  */
- + struct omap_vc_channel {
- + 	/* channel state */
- + 	u16 i2c_slave_addr;
- + 	u16 volt_reg_addr;
- + 	u16 cmd_reg_addr;
- + 	u16 setup_time;
- + 	u8 cfg_channel;
- + 	bool i2c_high_speed;
- + 
- + 	/* register access data */
- + 	const struct omap_vc_common *common;
- + 	u32 smps_sa_mask;
- + 	u32 smps_volra_mask;
- + 	u32 smps_cmdra_mask;
- + 	u8 cmdval_reg;
- + 	u8 smps_sa_reg;
- + 	u8 smps_volra_reg;
- + 	u8 smps_cmdra_reg;
- + 	u8 cfg_channel_reg;
- + 	u8 cfg_channel_sa_shift;
- + 	u8 flags;
- + };
- + 
- + extern struct omap_vc_channel omap3_vc_mpu;
- + extern struct omap_vc_channel omap3_vc_core;
- + 
- + extern struct omap_vc_channel omap4_vc_mpu;
- + extern struct omap_vc_channel omap4_vc_iva;
- + extern struct omap_vc_channel omap4_vc_core;
- + 
- + void omap_vc_init_channel(struct voltagedomain *voltdm);
- + int omap_vc_pre_scale(struct voltagedomain *voltdm,
- + 		      unsigned long target_volt,
- + 		      u8 *target_vsel, u8 *current_vsel);
- + void omap_vc_post_scale(struct voltagedomain *voltdm,
- + 			unsigned long target_volt,
- + 			u8 target_vsel, u8 current_vsel);
- + int omap_vc_bypass_scale(struct voltagedomain *voltdm,
- + 			 unsigned long target_volt);
- + 
- + #endif
- + 
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/voltage.c linux-3.2.1/arch/arm/mach-ckb_3352/voltage.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/voltage.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/voltage.c	2014-05-15 13:25:14.008187139 +0900
- ***************
- *** 0 ****
- --- 1,431 ----
- + /*
- +  * OMAP3/OMAP4 Voltage Management Routines
- +  *
- +  * Author: Thara Gopinath	<thara@ti.com>
- +  *
- +  * Copyright (C) 2007 Texas Instruments, Inc.
- +  * Rajendra Nayak <rnayak@ti.com>
- +  * Lesly A M <x0080970@ti.com>
- +  *
- +  * Copyright (C) 2008, 2011 Nokia Corporation
- +  * Kalle Jokiniemi
- +  * Paul Walmsley
- +  *
- +  * Copyright (C) 2010 Texas Instruments, Inc.
- +  * Thara Gopinath <thara@ti.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #include <linux/delay.h>
- + #include <linux/io.h>
- + #include <linux/err.h>
- + #include <linux/export.h>
- + #include <linux/debugfs.h>
- + #include <linux/slab.h>
- + #include <linux/clk.h>
- + 
- + #include "common.h"
- + 
- + #include "prm-regbits-34xx.h"
- + #include "prm-regbits-44xx.h"
- + //#include "prm44xx.h"
- + #include "prcm44xx.h"
- + #include "prminst44xx.h"
- + #include "control.h"
- + 
- + #include "voltage.h"
- + #include "powerdomain.h"
- + 
- + #include "vc.h"
- + #include "vp.h"
- + 
- + static LIST_HEAD(voltdm_list);
- + 
- + /* Public functions */
- + /**
- +  * voltdm_get_voltage() - Gets the current non-auto-compensated voltage
- +  * @voltdm:	pointer to the voltdm for which current voltage info is needed
- +  *
- +  * API to get the current non-auto-compensated voltage for a voltage domain.
- +  * Returns 0 in case of error else returns the current voltage.
- +  */
- + unsigned long voltdm_get_voltage(struct voltagedomain *voltdm)
- + {
- + 	if (!voltdm || IS_ERR(voltdm)) {
- + 		pr_warning("%s: VDD specified does not exist!\n", __func__);
- + 		return 0;
- + 	}
- + 
- + 	return voltdm->nominal_volt;
- + }
- + 
- + /**
- +  * voltdm_scale() - API to scale voltage of a particular voltage domain.
- +  * @voltdm: pointer to the voltage domain which is to be scaled.
- +  * @target_volt: The target voltage of the voltage domain
- +  *
- +  * This API should be called by the kernel to do the voltage scaling
- +  * for a particular voltage domain during DVFS.
- +  */
- + int voltdm_scale(struct voltagedomain *voltdm,
- + 		 unsigned long target_volt)
- + {
- + 	int ret;
- + 
- + 	if (!voltdm || IS_ERR(voltdm)) {
- + 		pr_warning("%s: VDD specified does not exist!\n", __func__);
- + 		return -EINVAL;
- + 	}
- + 
- + 	if (!voltdm->scale) {
- + 		pr_err("%s: No voltage scale API registered for vdd_%s\n",
- + 			__func__, voltdm->name);
- + 		return -ENODATA;
- + 	}
- + 
- + 	ret = voltdm->scale(voltdm, target_volt);
- + 	if (!ret)
- + 		voltdm->nominal_volt = target_volt;
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * voltdm_reset() - Resets the voltage of a particular voltage domain
- +  *		    to that of the current OPP.
- +  * @voltdm: pointer to the voltage domain whose voltage is to be reset.
- +  *
- +  * This API finds out the correct voltage the voltage domain is supposed
- +  * to be at and resets the voltage to that level. Should be used especially
- +  * while disabling any voltage compensation modules.
- +  */
- + void voltdm_reset(struct voltagedomain *voltdm)
- + {
- + 	unsigned long target_volt;
- + 
- + 	if (!voltdm || IS_ERR(voltdm)) {
- + 		pr_warning("%s: VDD specified does not exist!\n", __func__);
- + 		return;
- + 	}
- + 
- + 	target_volt = voltdm_get_voltage(voltdm);
- + 	if (!target_volt) {
- + 		pr_err("%s: unable to find current voltage for vdd_%s\n",
- + 			__func__, voltdm->name);
- + 		return;
- + 	}
- + 
- + 	voltdm_scale(voltdm, target_volt);
- + }
- + 
- + /**
- +  * omap_voltage_get_volttable() - API to get the voltage table associated with a
- +  *				particular voltage domain.
- +  * @voltdm:	pointer to the VDD for which the voltage table is required
- +  * @volt_data:	the voltage table for the particular vdd which is to be
- +  *		populated by this API
- +  *
- +  * This API populates the voltage table associated with a VDD into the
- +  * passed parameter pointer. Returns the count of distinct voltages
- +  * supported by this vdd.
- +  *
- +  */
- + void omap_voltage_get_volttable(struct voltagedomain *voltdm,
- + 				struct omap_volt_data **volt_data)
- + {
- + 	if (!voltdm || IS_ERR(voltdm)) {
- + 		pr_warning("%s: VDD specified does not exist!\n", __func__);
- + 		return;
- + 	}
- + 
- + 	*volt_data = voltdm->volt_data;
- + }
- + 
- + /**
- +  * omap_voltage_get_voltdata() - API to get the voltage table entry for a
- +  *				particular voltage
- +  * @voltdm:	pointer to the VDD whose voltage table has to be searched
- +  * @volt:	the voltage to be searched in the voltage table
- +  *
- +  * This API searches through the voltage table for the required voltage
- +  * domain and tries to find a matching entry for the passed voltage volt.
- +  * If a matching entry is found volt_data is populated with that entry.
- +  * This API searches only through the non-compensated voltages int the
- +  * voltage table.
- +  * Returns pointer to the voltage table entry corresponding to volt on
- +  * success. Returns -ENODATA if no voltage table exisits for the passed voltage
- +  * domain or if there is no matching entry.
- +  */
- + struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
- + 						 unsigned long volt)
- + {
- + 	int i;
- + 
- + 	if (!voltdm || IS_ERR(voltdm)) {
- + 		pr_warning("%s: VDD specified does not exist!\n", __func__);
- + 		return ERR_PTR(-EINVAL);
- + 	}
- + 
- + 	if (!voltdm->volt_data) {
- + 		pr_warning("%s: voltage table does not exist for vdd_%s\n",
- + 			__func__, voltdm->name);
- + 		return ERR_PTR(-ENODATA);
- + 	}
- + 
- + 	for (i = 0; voltdm->volt_data[i].volt_nominal != 0; i++) {
- + 		if (voltdm->volt_data[i].volt_nominal == volt)
- + 			return &voltdm->volt_data[i];
- + 	}
- + 
- + 	pr_notice("%s: Unable to match the current voltage with the voltage"
- + 		"table for vdd_%s\n", __func__, voltdm->name);
- + 
- + 	return ERR_PTR(-ENODATA);
- + }
- + 
- + /**
- +  * omap_voltage_register_pmic() - API to register PMIC specific data
- +  * @voltdm:	pointer to the VDD for which the PMIC specific data is
- +  *		to be registered
- +  * @pmic:	the structure containing pmic info
- +  *
- +  * This API is to be called by the SOC/PMIC file to specify the
- +  * pmic specific info as present in omap_voltdm_pmic structure.
- +  */
- + int omap_voltage_register_pmic(struct voltagedomain *voltdm,
- + 			       struct omap_voltdm_pmic *pmic)
- + {
- + 	if (!voltdm || IS_ERR(voltdm)) {
- + 		pr_warning("%s: VDD specified does not exist!\n", __func__);
- + 		return -EINVAL;
- + 	}
- + 
- + 	voltdm->pmic = pmic;
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * omap_change_voltscale_method() - API to change the voltage scaling method.
- +  * @voltdm:	pointer to the VDD whose voltage scaling method
- +  *		has to be changed.
- +  * @voltscale_method:	the method to be used for voltage scaling.
- +  *
- +  * This API can be used by the board files to change the method of voltage
- +  * scaling between vpforceupdate and vcbypass. The parameter values are
- +  * defined in voltage.h
- +  */
- + void omap_change_voltscale_method(struct voltagedomain *voltdm,
- + 				  int voltscale_method)
- + {
- + 	if (!voltdm || IS_ERR(voltdm)) {
- + 		pr_warning("%s: VDD specified does not exist!\n", __func__);
- + 		return;
- + 	}
- + 
- + 	switch (voltscale_method) {
- + 	case VOLTSCALE_VPFORCEUPDATE:
- + 		voltdm->scale = omap_vp_forceupdate_scale;
- + 		return;
- + 	case VOLTSCALE_VCBYPASS:
- + 		voltdm->scale = omap_vc_bypass_scale;
- + 		return;
- + 	default:
- + 		pr_warning("%s: Trying to change the method of voltage scaling"
- + 			"to an unsupported one!\n", __func__);
- + 	}
- + }
- + 
- + /**
- +  * omap_voltage_late_init() - Init the various voltage parameters
- +  *
- +  * This API is to be called in the later stages of the
- +  * system boot to init the voltage controller and
- +  * voltage processors.
- +  */
- + int __init omap_voltage_late_init(void)
- + {
- + 	struct voltagedomain *voltdm;
- + 
- + 	if (list_empty(&voltdm_list)) {
- + 		pr_err("%s: Voltage driver support not added\n",
- + 			__func__);
- + 		return -EINVAL;
- + 	}
- + 
- + 	list_for_each_entry(voltdm, &voltdm_list, node) {
- + 		struct clk *sys_ck;
- + 
- + 		if (!voltdm->scalable)
- + 			continue;
- + 
- + 		sys_ck = clk_get(NULL, voltdm->sys_clk.name);
- + 		if (IS_ERR(sys_ck)) {
- + 			pr_warning("%s: Could not get sys clk.\n", __func__);
- + 			return -EINVAL;
- + 		}
- + 		voltdm->sys_clk.rate = clk_get_rate(sys_ck);
- + 		WARN_ON(!voltdm->sys_clk.rate);
- + 		clk_put(sys_ck);
- + 
- + 		if (voltdm->vc) {
- + 			voltdm->scale = omap_vc_bypass_scale;
- + 			omap_vc_init_channel(voltdm);
- + 		}
- + 
- + 		if (voltdm->vp) {
- + 			voltdm->scale = omap_vp_forceupdate_scale;
- + 			omap_vp_init(voltdm);
- + 		}
- + 	}
- + 
- + 	return 0;
- + }
- + 
- + static struct voltagedomain *_voltdm_lookup(const char *name)
- + {
- + 	struct voltagedomain *voltdm, *temp_voltdm;
- + 
- + 	voltdm = NULL;
- + 
- + 	list_for_each_entry(temp_voltdm, &voltdm_list, node) {
- + 		if (!strcmp(name, temp_voltdm->name)) {
- + 			voltdm = temp_voltdm;
- + 			break;
- + 		}
- + 	}
- + 
- + 	return voltdm;
- + }
- + 
- + /**
- +  * voltdm_add_pwrdm - add a powerdomain to a voltagedomain
- +  * @voltdm: struct voltagedomain * to add the powerdomain to
- +  * @pwrdm: struct powerdomain * to associate with a voltagedomain
- +  *
- +  * Associate the powerdomain @pwrdm with a voltagedomain @voltdm.  This
- +  * enables the use of voltdm_for_each_pwrdm().  Returns -EINVAL if
- +  * presented with invalid pointers; -ENOMEM if memory could not be allocated;
- +  * or 0 upon success.
- +  */
- + int voltdm_add_pwrdm(struct voltagedomain *voltdm, struct powerdomain *pwrdm)
- + {
- + 	if (!voltdm || !pwrdm)
- + 		return -EINVAL;
- + 
- + 	pr_debug("voltagedomain: associating powerdomain %s with voltagedomain "
- + 		 "%s\n", pwrdm->name, voltdm->name);
- + 
- + 	list_add(&pwrdm->voltdm_node, &voltdm->pwrdm_list);
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * voltdm_for_each_pwrdm - call function for each pwrdm in a voltdm
- +  * @voltdm: struct voltagedomain * to iterate over
- +  * @fn: callback function *
- +  *
- +  * Call the supplied function @fn for each powerdomain in the
- +  * voltagedomain @voltdm.  Returns -EINVAL if presented with invalid
- +  * pointers; or passes along the last return value of the callback
- +  * function, which should be 0 for success or anything else to
- +  * indicate failure.
- +  */
- + int voltdm_for_each_pwrdm(struct voltagedomain *voltdm,
- + 			  int (*fn)(struct voltagedomain *voltdm,
- + 				    struct powerdomain *pwrdm))
- + {
- + 	struct powerdomain *pwrdm;
- + 	int ret = 0;
- + 
- + 	if (!fn)
- + 		return -EINVAL;
- + 
- + 	list_for_each_entry(pwrdm, &voltdm->pwrdm_list, voltdm_node)
- + 		ret = (*fn)(voltdm, pwrdm);
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * voltdm_for_each - call function on each registered voltagedomain
- +  * @fn: callback function *
- +  *
- +  * Call the supplied function @fn for each registered voltagedomain.
- +  * The callback function @fn can return anything but 0 to bail out
- +  * early from the iterator.  Returns the last return value of the
- +  * callback function, which should be 0 for success or anything else
- +  * to indicate failure; or -EINVAL if the function pointer is null.
- +  */
- + int voltdm_for_each(int (*fn)(struct voltagedomain *voltdm, void *user),
- + 		    void *user)
- + {
- + 	struct voltagedomain *temp_voltdm;
- + 	int ret = 0;
- + 
- + 	if (!fn)
- + 		return -EINVAL;
- + 
- + 	list_for_each_entry(temp_voltdm, &voltdm_list, node) {
- + 		ret = (*fn)(temp_voltdm, user);
- + 		if (ret)
- + 			break;
- + 	}
- + 
- + 	return ret;
- + }
- + 
- + static int _voltdm_register(struct voltagedomain *voltdm)
- + {
- + 	if (!voltdm || !voltdm->name)
- + 		return -EINVAL;
- + 
- + 	INIT_LIST_HEAD(&voltdm->pwrdm_list);
- + 	list_add(&voltdm->node, &voltdm_list);
- + 
- + 	pr_debug("voltagedomain: registered %s\n", voltdm->name);
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * voltdm_lookup - look up a voltagedomain by name, return a pointer
- +  * @name: name of voltagedomain
- +  *
- +  * Find a registered voltagedomain by its name @name.  Returns a pointer
- +  * to the struct voltagedomain if found, or NULL otherwise.
- +  */
- + struct voltagedomain *voltdm_lookup(const char *name)
- + {
- + 	struct voltagedomain *voltdm ;
- + 
- + 	if (!name)
- + 		return NULL;
- + 
- + 	voltdm = _voltdm_lookup(name);
- + 
- + 	return voltdm;
- + }
- + 
- + /**
- +  * voltdm_init - set up the voltagedomain layer
- +  * @voltdm_list: array of struct voltagedomain pointers to register
- +  *
- +  * Loop through the array of voltagedomains @voltdm_list, registering all
- +  * that are available on the current CPU. If voltdm_list is supplied
- +  * and not null, all of the referenced voltagedomains will be
- +  * registered.  No return value.
- +  */
- + void voltdm_init(struct voltagedomain **voltdms)
- + {
- + 	struct voltagedomain **v;
- + 
- + 	if (voltdms) {
- + 		for (v = voltdms; *v; v++)
- + 			_voltdm_register(*v);
- + 	}
- + }
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/voltagedomains33xx_data.c linux-3.2.1/arch/arm/mach-ckb_3352/voltagedomains33xx_data.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/voltagedomains33xx_data.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/voltagedomains33xx_data.c	2014-05-15 13:25:14.008187139 +0900
- ***************
- *** 0 ****
- --- 1,43 ----
- + /*
- +  * AM33XX voltage domain data
- +  *
- +  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #include <linux/kernel.h>
- + #include <linux/init.h>
- + 
- + #include "voltage.h"
- + 
- + static struct voltagedomain am33xx_voltdm_mpu = {
- + 	.name		= "mpu",
- + };
- + 
- + static struct voltagedomain am33xx_voltdm_core = {
- + 	.name		= "core",
- + };
- + 
- + static struct voltagedomain am33xx_voltdm_rtc = {
- + 	.name		= "rtc",
- + };
- + 
- + static struct voltagedomain *voltagedomains_am33xx[] __initdata = {
- + 	&am33xx_voltdm_mpu,
- + 	&am33xx_voltdm_core,
- + 	&am33xx_voltdm_rtc,
- + 	NULL,
- + };
- + 
- + void __init am33xx_voltagedomains_init(void)
- + {
- + 	voltdm_init(voltagedomains_am33xx);
- + }
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/voltagedomains3xxx_data.c linux-3.2.1/arch/arm/mach-ckb_3352/voltagedomains3xxx_data.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/voltagedomains3xxx_data.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/voltagedomains3xxx_data.c	2014-05-15 13:25:14.008187139 +0900
- ***************
- *** 0 ****
- --- 1,97 ----
- + /*
- +  * OMAP3 voltage domain data
- +  *
- +  * Copyright (C) 2007, 2010 Texas Instruments, Inc.
- +  * Rajendra Nayak <rnayak@ti.com>
- +  * Lesly A M <x0080970@ti.com>
- +  * Thara Gopinath <thara@ti.com>
- +  *
- +  * Copyright (C) 2008, 2011 Nokia Corporation
- +  * Kalle Jokiniemi
- +  * Paul Walmsley
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + #include <linux/kernel.h>
- + #include <linux/err.h>
- + #include <linux/init.h>
- + 
- + #include "common.h"
- + #include <plat/cpu.h>
- + 
- + #include "prm-regbits-34xx.h"
- + #include "omap_opp_data.h"
- + #include "voltage.h"
- + #include "vc.h"
- + #include "vp.h"
- + 
- + /*
- +  * VDD data
- +  */
- + 
- + /* OMAP3-common voltagedomain data */
- + 
- + static struct voltagedomain omap3_voltdm_wkup = {
- + 	.name = "wakeup",
- + };
- + 
- + /* 34xx/36xx voltagedomain data */
- + 
- + static const struct omap_vfsm_instance omap3_vdd1_vfsm = {
- + 	.voltsetup_reg = OMAP3_PRM_VOLTSETUP1_OFFSET,
- + 	.voltsetup_mask = OMAP3430_SETUP_TIME1_MASK,
- + };
- + 
- + static const struct omap_vfsm_instance omap3_vdd2_vfsm = {
- + 	.voltsetup_reg = OMAP3_PRM_VOLTSETUP1_OFFSET,
- + 	.voltsetup_mask = OMAP3430_SETUP_TIME2_MASK,
- + };
- + 
- + static struct voltagedomain omap3_voltdm_mpu = {
- + 	.name = "mpu_iva",
- + 	.scalable = true,
- + 	.read = omap3_prm_vcvp_read,
- + 	.write = omap3_prm_vcvp_write,
- + 	.rmw = omap3_prm_vcvp_rmw,
- + 	.vc = &omap3_vc_mpu,
- + 	.vfsm = &omap3_vdd1_vfsm,
- + 	.vp = &omap3_vp_mpu,
- + };
- + 
- + static struct voltagedomain omap3_voltdm_core = {
- + 	.name = "core",
- + 	.scalable = true,
- + 	.read = omap3_prm_vcvp_read,
- + 	.write = omap3_prm_vcvp_write,
- + 	.rmw = omap3_prm_vcvp_rmw,
- + 	.vc = &omap3_vc_core,
- + 	.vfsm = &omap3_vdd2_vfsm,
- + 	.vp = &omap3_vp_core,
- + };
- + 
- + static struct voltagedomain *voltagedomains_omap3[] __initdata = {
- + 	&omap3_voltdm_mpu,
- + 	&omap3_voltdm_core,
- + 	&omap3_voltdm_wkup,
- + 	NULL,
- + };
- + 
- + static const char *sys_clk_name __initdata = "sys_ck";
- + 
- + void __init omap3xxx_voltagedomains_init(void)
- + {
- + 	struct voltagedomain *voltdm;
- + 	struct voltagedomain **voltdms;
- + 	int i;
- + 	omap3_voltdm_mpu.volt_data = omap34xx_vddmpu_volt_data;
- + 	omap3_voltdm_core.volt_data = omap34xx_vddcore_volt_data;
- + 
- + 	voltdms = voltagedomains_omap3;
- + 
- + 	for (i = 0; voltdm = voltdms[i], voltdm; i++)
- + 		voltdm->sys_clk.name = sys_clk_name;
- + 
- + 	voltdm_init(voltdms);
- + };
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/voltage.h linux-3.2.1/arch/arm/mach-ckb_3352/voltage.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/voltage.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/voltage.h	2014-05-15 13:25:14.012131471 +0900
- ***************
- *** 0 ****
- --- 1,173 ----
- + /*
- +  * OMAP Voltage Management Routines
- +  *
- +  * Author: Thara Gopinath	<thara@ti.com>
- +  *
- +  * Copyright (C) 2009 Texas Instruments, Inc.
- +  * Thara Gopinath <thara@ti.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #ifndef __ARCH_ARM_MACH_OMAP2_VOLTAGE_H
- + #define __ARCH_ARM_MACH_OMAP2_VOLTAGE_H
- + 
- + #include <linux/err.h>
- + 
- + #include "vc.h"
- + #include "vp.h"
- + 
- + struct powerdomain;
- + 
- + /* XXX document */
- + #define VOLTSCALE_VPFORCEUPDATE		1
- + #define VOLTSCALE_VCBYPASS		2
- + 
- + /*
- +  * OMAP3 GENERIC setup times. Revisit to see if these needs to be
- +  * passed from board or PMIC file
- +  */
- + #define OMAP3_CLKSETUP		0xff
- + #define OMAP3_VOLTOFFSET	0xff
- + #define OMAP3_VOLTSETUP2	0xff
- + 
- + /**
- +  * struct omap_vfsm_instance - per-voltage manager FSM register/bitfield
- +  * data
- +  * @voltsetup_mask: SETUP_TIME* bitmask in the PRM_VOLTSETUP* register
- +  * @voltsetup_reg: register offset of PRM_VOLTSETUP from PRM base
- +  *
- +  * XXX What about VOLTOFFSET/VOLTCTRL?
- +  */
- + struct omap_vfsm_instance {
- + 	u32 voltsetup_mask;
- + 	u8 voltsetup_reg;
- + };
- + 
- + /**
- +  * struct voltagedomain - omap voltage domain global structure.
- +  * @name: Name of the voltage domain which can be used as a unique identifier.
- +  * @scalable: Whether or not this voltage domain is scalable
- +  * @node: list_head linking all voltage domains
- +  * @pwrdm_list: list_head linking all powerdomains in this voltagedomain
- +  * @vc: pointer to VC channel associated with this voltagedomain
- +  * @vp: pointer to VP associated with this voltagedomain
- +  * @read: read a VC/VP register
- +  * @write: write a VC/VP register
- +  * @read: read-modify-write a VC/VP register
- +  * @sys_clk: system clock name/frequency, used for various timing calculations
- +  * @scale: function used to scale the voltage of the voltagedomain
- +  * @nominal_volt: current nominal voltage for this voltage domain
- +  * @volt_data: voltage table having the distinct voltages supported
- +  *             by the domain and other associated per voltage data.
- +  */
- + struct voltagedomain {
- + 	char *name;
- + 	bool scalable;
- + 	struct list_head node;
- + 	struct list_head pwrdm_list;
- + 	struct omap_vc_channel *vc;
- + 	const struct omap_vfsm_instance *vfsm;
- + 	struct omap_vp_instance *vp;
- + 	struct omap_voltdm_pmic *pmic;
- + 
- + 	/* VC/VP register access functions: SoC specific */
- + 	u32 (*read) (u8 offset);
- + 	void (*write) (u32 val, u8 offset);
- + 	u32 (*rmw)(u32 mask, u32 bits, u8 offset);
- + 
- + 	union {
- + 		const char *name;
- + 		u32 rate;
- + 	} sys_clk;
- + 
- + 	int (*scale) (struct voltagedomain *voltdm,
- + 		      unsigned long target_volt);
- + 
- + 	u32 nominal_volt;
- + 	struct omap_volt_data *volt_data;
- + };
- + 
- + /**
- +  * struct omap_volt_data - Omap voltage specific data.
- +  * @voltage_nominal:	The possible voltage value in uV
- +  * @sr_efuse_offs:	The offset of the efuse register(from system
- +  *			control module base address) from where to read
- +  *			the n-target value for the smartreflex module.
- +  * @sr_errminlimit:	Error min limit value for smartreflex. This value
- +  *			differs at differnet opp and thus is linked
- +  *			with voltage.
- +  * @vp_errorgain:	Error gain value for the voltage processor. This
- +  *			field also differs according to the voltage/opp.
- +  */
- + struct omap_volt_data {
- + 	u32	volt_nominal;
- + 	u32	sr_efuse_offs;
- + 	u8	sr_errminlimit;
- + 	u8	vp_errgain;
- + };
- + 
- + /**
- +  * struct omap_voltdm_pmic - PMIC specific data required by voltage driver.
- +  * @slew_rate:	PMIC slew rate (in uv/us)
- +  * @step_size:	PMIC voltage step size (in uv)
- +  * @i2c_slave_addr: I2C slave address of PMIC
- +  * @volt_reg_addr: voltage configuration register address
- +  * @cmd_reg_addr: command (on, on-LP, ret, off) configuration register address
- +  * @i2c_high_speed: whether VC uses I2C high-speed mode to PMIC
- +  * @i2c_mcode: master code value for I2C high-speed preamble transmission
- +  * @vsel_to_uv:	PMIC API to convert vsel value to actual voltage in uV.
- +  * @uv_to_vsel:	PMIC API to convert voltage in uV to vsel value.
- +  */
- + struct omap_voltdm_pmic {
- + 	int slew_rate;
- + 	int step_size;
- + 	u32 on_volt;
- + 	u32 onlp_volt;
- + 	u32 ret_volt;
- + 	u32 off_volt;
- + 	u16 volt_setup_time;
- + 	u16 i2c_slave_addr;
- + 	u16 volt_reg_addr;
- + 	u16 cmd_reg_addr;
- + 	u8 vp_erroroffset;
- + 	u8 vp_vstepmin;
- + 	u8 vp_vstepmax;
- + 	u8 vp_vddmin;
- + 	u8 vp_vddmax;
- + 	u8 vp_timeout_us;
- + 	bool i2c_high_speed;
- + 	u8 i2c_mcode;
- + 	unsigned long (*vsel_to_uv) (const u8 vsel);
- + 	u8 (*uv_to_vsel) (unsigned long uV);
- + };
- + 
- + void omap_voltage_get_volttable(struct voltagedomain *voltdm,
- + 		struct omap_volt_data **volt_data);
- + struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
- + 		unsigned long volt);
- + int omap_voltage_register_pmic(struct voltagedomain *voltdm,
- + 			       struct omap_voltdm_pmic *pmic);
- + void omap_change_voltscale_method(struct voltagedomain *voltdm,
- + 		int voltscale_method);
- + int omap_voltage_late_init(void);
- + 
- + extern void omap2xxx_voltagedomains_init(void);
- + extern void omap3xxx_voltagedomains_init(void);
- + extern void am33xx_voltagedomains_init(void);
- + extern void omap44xx_voltagedomains_init(void);
- + 
- + struct voltagedomain *voltdm_lookup(const char *name);
- + void voltdm_init(struct voltagedomain **voltdm_list);
- + int voltdm_add_pwrdm(struct voltagedomain *voltdm, struct powerdomain *pwrdm);
- + int voltdm_for_each(int (*fn)(struct voltagedomain *voltdm, void *user),
- + 		    void *user);
- + int voltdm_for_each_pwrdm(struct voltagedomain *voltdm,
- + 			  int (*fn)(struct voltagedomain *voltdm,
- + 				    struct powerdomain *pwrdm));
- + int voltdm_scale(struct voltagedomain *voltdm, unsigned long target_volt);
- + void voltdm_reset(struct voltagedomain *voltdm);
- + unsigned long voltdm_get_voltage(struct voltagedomain *voltdm);
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/vp3xxx_data.c linux-3.2.1/arch/arm/mach-ckb_3352/vp3xxx_data.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/vp3xxx_data.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/vp3xxx_data.c	2014-05-15 13:25:14.012131471 +0900
- ***************
- *** 0 ****
- --- 1,79 ----
- + /*
- +  * OMAP3 Voltage Processor (VP) data
- +  *
- +  * Copyright (C) 2007, 2010 Texas Instruments, Inc.
- +  * Rajendra Nayak <rnayak@ti.com>
- +  * Lesly A M <x0080970@ti.com>
- +  * Thara Gopinath <thara@ti.com>
- +  *
- +  * Copyright (C) 2008, 2011 Nokia Corporation
- +  * Kalle Jokiniemi
- +  * Paul Walmsley
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #include <linux/io.h>
- + #include <linux/err.h>
- + #include <linux/init.h>
- + 
- + #include "common.h"
- + 
- + #include "prm-regbits-34xx.h"
- + #include "voltage.h"
- + 
- + #include "vp.h"
- + #include "prm2xxx_3xxx.h"
- + 
- + static const struct omap_vp_ops omap3_vp_ops = {
- + 	.check_txdone = omap3_prm_vp_check_txdone,
- + 	.clear_txdone = omap3_prm_vp_clear_txdone,
- + };
- + 
- + /*
- +  * VP data common to 34xx/36xx chips
- +  * XXX This stuff presumably belongs in the vp3xxx.c or vp.c file.
- +  */
- + static const struct omap_vp_common omap3_vp_common = {
- + 	.vpconfig_erroroffset_mask = OMAP3430_ERROROFFSET_MASK,
- + 	.vpconfig_errorgain_mask = OMAP3430_ERRORGAIN_MASK,
- + 	.vpconfig_initvoltage_mask = OMAP3430_INITVOLTAGE_MASK,
- + 	.vpconfig_timeouten = OMAP3430_TIMEOUTEN_MASK,
- + 	.vpconfig_initvdd = OMAP3430_INITVDD_MASK,
- + 	.vpconfig_forceupdate = OMAP3430_FORCEUPDATE_MASK,
- + 	.vpconfig_vpenable = OMAP3430_VPENABLE_MASK,
- + 	.vstepmin_smpswaittimemin_shift = OMAP3430_SMPSWAITTIMEMIN_SHIFT,
- + 	.vstepmax_smpswaittimemax_shift = OMAP3430_SMPSWAITTIMEMAX_SHIFT,
- + 	.vstepmin_stepmin_shift = OMAP3430_VSTEPMIN_SHIFT,
- + 	.vstepmax_stepmax_shift = OMAP3430_VSTEPMAX_SHIFT,
- + 	.vlimitto_vddmin_shift = OMAP3430_VDDMIN_SHIFT,
- + 	.vlimitto_vddmax_shift = OMAP3430_VDDMAX_SHIFT,
- + 	.vlimitto_timeout_shift = OMAP3430_TIMEOUT_SHIFT,
- + 	.vpvoltage_mask = OMAP3430_VPVOLTAGE_MASK,
- + 
- + 	.ops = &omap3_vp_ops,
- + };
- + 
- + struct omap_vp_instance omap3_vp_mpu = {
- + 	.id = OMAP3_VP_VDD_MPU_ID,
- + 	.common = &omap3_vp_common,
- + 	.vpconfig = OMAP3_PRM_VP1_CONFIG_OFFSET,
- + 	.vstepmin = OMAP3_PRM_VP1_VSTEPMIN_OFFSET,
- + 	.vstepmax = OMAP3_PRM_VP1_VSTEPMAX_OFFSET,
- + 	.vlimitto = OMAP3_PRM_VP1_VLIMITTO_OFFSET,
- + 	.vstatus = OMAP3_PRM_VP1_STATUS_OFFSET,
- + 	.voltage = OMAP3_PRM_VP1_VOLTAGE_OFFSET,
- + };
- + 
- + struct omap_vp_instance omap3_vp_core = {
- + 	.id = OMAP3_VP_VDD_CORE_ID,
- + 	.common = &omap3_vp_common,
- + 	.vpconfig = OMAP3_PRM_VP2_CONFIG_OFFSET,
- + 	.vstepmin = OMAP3_PRM_VP2_VSTEPMIN_OFFSET,
- + 	.vstepmax = OMAP3_PRM_VP2_VSTEPMAX_OFFSET,
- + 	.vlimitto = OMAP3_PRM_VP2_VLIMITTO_OFFSET,
- + 	.vstatus = OMAP3_PRM_VP2_STATUS_OFFSET,
- + 	.voltage = OMAP3_PRM_VP2_VOLTAGE_OFFSET,
- + };
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/vp.c linux-3.2.1/arch/arm/mach-ckb_3352/vp.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/vp.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/vp.c	2014-05-15 13:25:14.012131471 +0900
- ***************
- *** 0 ****
- --- 1,284 ----
- + #include <linux/kernel.h>
- + #include <linux/init.h>
- + 
- + #include "common.h"
- + 
- + #include "voltage.h"
- + #include "vp.h"
- + #include "prm-regbits-34xx.h"
- + #include "prm-regbits-44xx.h"
- + //#include "prm44xx.h"
- + 
- + static u32 _vp_set_init_voltage(struct voltagedomain *voltdm, u32 volt)
- + {
- + 	struct omap_vp_instance *vp = voltdm->vp;
- + 	u32 vpconfig;
- + 	char vsel;
- + 
- + 	vsel = voltdm->pmic->uv_to_vsel(volt);
- + 
- + 	vpconfig = voltdm->read(vp->vpconfig);
- + 	vpconfig &= ~(vp->common->vpconfig_initvoltage_mask |
- + 		      vp->common->vpconfig_forceupdate |
- + 		      vp->common->vpconfig_initvdd);
- + 	vpconfig |= vsel << __ffs(vp->common->vpconfig_initvoltage_mask);
- + 	voltdm->write(vpconfig, vp->vpconfig);
- + 
- + 	/* Trigger initVDD value copy to voltage processor */
- + 	voltdm->write((vpconfig | vp->common->vpconfig_initvdd),
- + 		       vp->vpconfig);
- + 
- + 	/* Clear initVDD copy trigger bit */
- + 	voltdm->write(vpconfig, vp->vpconfig);
- + 
- + 	return vpconfig;
- + }
- + 
- + /* Generic voltage init functions */
- + void __init omap_vp_init(struct voltagedomain *voltdm)
- + {
- + 	struct omap_vp_instance *vp = voltdm->vp;
- + 	u32 val, sys_clk_rate, timeout, waittime;
- + 	u32 vddmin, vddmax, vstepmin, vstepmax;
- + 
- + 	if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) {
- + 		pr_err("%s: missing PMIC for vdd_%s.\n",
- + 		       __func__, voltdm->name);
- + 		return;
- + 	}
- + 
- + 	if (!voltdm->read || !voltdm->write) {
- + 		pr_err("%s: No read/write API for accessing vdd_%s regs\n",
- + 			__func__, voltdm->name);
- + 		return;
- + 	}
- + 
- + 	vp->enabled = false;
- + 
- + 	/* Divide to avoid overflow */
- + 	sys_clk_rate = voltdm->sys_clk.rate / 1000;
- + 
- + 	timeout = (sys_clk_rate * voltdm->pmic->vp_timeout_us) / 1000;
- + 	vddmin = voltdm->pmic->vp_vddmin;
- + 	vddmax = voltdm->pmic->vp_vddmax;
- + 
- + 	waittime = ((voltdm->pmic->step_size / voltdm->pmic->slew_rate) *
- + 		    sys_clk_rate) / 1000;
- + 	vstepmin = voltdm->pmic->vp_vstepmin;
- + 	vstepmax = voltdm->pmic->vp_vstepmax;
- + 
- + 	/*
- + 	 * VP_CONFIG: error gain is not set here, it will be updated
- + 	 * on each scale, based on OPP.
- + 	 */
- + 	val = (voltdm->pmic->vp_erroroffset <<
- + 	       __ffs(voltdm->vp->common->vpconfig_erroroffset_mask)) |
- + 		vp->common->vpconfig_timeouten;
- + 	voltdm->write(val, vp->vpconfig);
- + 
- + 	/* VSTEPMIN */
- + 	val = (waittime << vp->common->vstepmin_smpswaittimemin_shift) |
- + 		(vstepmin <<  vp->common->vstepmin_stepmin_shift);
- + 	voltdm->write(val, vp->vstepmin);
- + 
- + 	/* VSTEPMAX */
- + 	val = (vstepmax << vp->common->vstepmax_stepmax_shift) |
- + 		(waittime << vp->common->vstepmax_smpswaittimemax_shift);
- + 	voltdm->write(val, vp->vstepmax);
- + 
- + 	/* VLIMITTO */
- + 	val = (vddmax << vp->common->vlimitto_vddmax_shift) |
- + 		(vddmin << vp->common->vlimitto_vddmin_shift) |
- + 		(timeout <<  vp->common->vlimitto_timeout_shift);
- + 	voltdm->write(val, vp->vlimitto);
- + }
- + 
- + int omap_vp_update_errorgain(struct voltagedomain *voltdm,
- + 			     unsigned long target_volt)
- + {
- + 	struct omap_volt_data *volt_data;
- + 
- + 	if (!voltdm->vp)
- + 		return -EINVAL;
- + 
- + 	/* Get volt_data corresponding to target_volt */
- + 	volt_data = omap_voltage_get_voltdata(voltdm, target_volt);
- + 	if (IS_ERR(volt_data))
- + 		return -EINVAL;
- + 
- + 	/* Setting vp errorgain based on the voltage */
- + 	voltdm->rmw(voltdm->vp->common->vpconfig_errorgain_mask,
- + 		    volt_data->vp_errgain <<
- + 		    __ffs(voltdm->vp->common->vpconfig_errorgain_mask),
- + 		    voltdm->vp->vpconfig);
- + 
- + 	return 0;
- + }
- + 
- + /* VP force update method of voltage scaling */
- + int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
- + 			      unsigned long target_volt)
- + {
- + 	struct omap_vp_instance *vp = voltdm->vp;
- + 	u32 vpconfig;
- + 	u8 target_vsel, current_vsel;
- + 	int ret, timeout = 0;
- + 
- + 	ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, &current_vsel);
- + 	if (ret)
- + 		return ret;
- + 
- + 	/*
- + 	 * Clear all pending TransactionDone interrupt/status. Typical latency
- + 	 * is <3us
- + 	 */
- + 	while (timeout++ < VP_TRANXDONE_TIMEOUT) {
- + 		vp->common->ops->clear_txdone(vp->id);
- + 		if (!vp->common->ops->check_txdone(vp->id))
- + 			break;
- + 		udelay(1);
- + 	}
- + 	if (timeout >= VP_TRANXDONE_TIMEOUT) {
- + 		pr_warning("%s: vdd_%s TRANXDONE timeout exceeded."
- + 			"Voltage change aborted", __func__, voltdm->name);
- + 		return -ETIMEDOUT;
- + 	}
- + 
- + 	vpconfig = _vp_set_init_voltage(voltdm, target_volt);
- + 
- + 	/* Force update of voltage */
- + 	voltdm->write(vpconfig | vp->common->vpconfig_forceupdate,
- + 		      voltdm->vp->vpconfig);
- + 
- + 	/*
- + 	 * Wait for TransactionDone. Typical latency is <200us.
- + 	 * Depends on SMPSWAITTIMEMIN/MAX and voltage change
- + 	 */
- + 	timeout = 0;
- + 	omap_test_timeout(vp->common->ops->check_txdone(vp->id),
- + 			  VP_TRANXDONE_TIMEOUT, timeout);
- + 	if (timeout >= VP_TRANXDONE_TIMEOUT)
- + 		pr_err("%s: vdd_%s TRANXDONE timeout exceeded."
- + 			"TRANXDONE never got set after the voltage update\n",
- + 			__func__, voltdm->name);
- + 
- + 	omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel);
- + 
- + 	/*
- + 	 * Disable TransactionDone interrupt , clear all status, clear
- + 	 * control registers
- + 	 */
- + 	timeout = 0;
- + 	while (timeout++ < VP_TRANXDONE_TIMEOUT) {
- + 		vp->common->ops->clear_txdone(vp->id);
- + 		if (!vp->common->ops->check_txdone(vp->id))
- + 			break;
- + 		udelay(1);
- + 	}
- + 
- + 	if (timeout >= VP_TRANXDONE_TIMEOUT)
- + 		pr_warning("%s: vdd_%s TRANXDONE timeout exceeded while trying"
- + 			"to clear the TRANXDONE status\n",
- + 			__func__, voltdm->name);
- + 
- + 	/* Clear force bit */
- + 	voltdm->write(vpconfig, vp->vpconfig);
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * omap_vp_enable() - API to enable a particular VP
- +  * @voltdm:	pointer to the VDD whose VP is to be enabled.
- +  *
- +  * This API enables a particular voltage processor. Needed by the smartreflex
- +  * class drivers.
- +  */
- + void omap_vp_enable(struct voltagedomain *voltdm)
- + {
- + 	struct omap_vp_instance *vp;
- + 	u32 vpconfig, volt;
- + 
- + 	if (!voltdm || IS_ERR(voltdm)) {
- + 		pr_warning("%s: VDD specified does not exist!\n", __func__);
- + 		return;
- + 	}
- + 
- + 	vp = voltdm->vp;
- + 	if (!voltdm->read || !voltdm->write) {
- + 		pr_err("%s: No read/write API for accessing vdd_%s regs\n",
- + 			__func__, voltdm->name);
- + 		return;
- + 	}
- + 
- + 	/* If VP is already enabled, do nothing. Return */
- + 	if (vp->enabled)
- + 		return;
- + 
- + 	volt = voltdm_get_voltage(voltdm);
- + 	if (!volt) {
- + 		pr_warning("%s: unable to find current voltage for %s\n",
- + 			   __func__, voltdm->name);
- + 		return;
- + 	}
- + 
- + 	vpconfig = _vp_set_init_voltage(voltdm, volt);
- + 
- + 	/* Enable VP */
- + 	vpconfig |= vp->common->vpconfig_vpenable;
- + 	voltdm->write(vpconfig, vp->vpconfig);
- + 
- + 	vp->enabled = true;
- + }
- + 
- + /**
- +  * omap_vp_disable() - API to disable a particular VP
- +  * @voltdm:	pointer to the VDD whose VP is to be disabled.
- +  *
- +  * This API disables a particular voltage processor. Needed by the smartreflex
- +  * class drivers.
- +  */
- + void omap_vp_disable(struct voltagedomain *voltdm)
- + {
- + 	struct omap_vp_instance *vp;
- + 	u32 vpconfig;
- + 	int timeout;
- + 
- + 	if (!voltdm || IS_ERR(voltdm)) {
- + 		pr_warning("%s: VDD specified does not exist!\n", __func__);
- + 		return;
- + 	}
- + 
- + 	vp = voltdm->vp;
- + 	if (!voltdm->read || !voltdm->write) {
- + 		pr_err("%s: No read/write API for accessing vdd_%s regs\n",
- + 			__func__, voltdm->name);
- + 		return;
- + 	}
- + 
- + 	/* If VP is already disabled, do nothing. Return */
- + 	if (!vp->enabled) {
- + 		pr_warning("%s: Trying to disable VP for vdd_%s when"
- + 			"it is already disabled\n", __func__, voltdm->name);
- + 		return;
- + 	}
- + 
- + 	/* Disable VP */
- + 	vpconfig = voltdm->read(vp->vpconfig);
- + 	vpconfig &= ~vp->common->vpconfig_vpenable;
- + 	voltdm->write(vpconfig, vp->vpconfig);
- + 
- + 	/*
- + 	 * Wait for VP idle Typical latency is <2us. Maximum latency is ~100us
- + 	 */
- + 	omap_test_timeout((voltdm->read(vp->vstatus)),
- + 			  VP_IDLE_TIMEOUT, timeout);
- + 
- + 	if (timeout >= VP_IDLE_TIMEOUT)
- + 		pr_warning("%s: vdd_%s idle timedout\n",
- + 			__func__, voltdm->name);
- + 
- + 	vp->enabled = false;
- + 
- + 	return;
- + }
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/vp.h linux-3.2.1/arch/arm/mach-ckb_3352/vp.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/vp.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/vp.h	2014-05-15 13:25:14.012131471 +0900
- ***************
- *** 0 ****
- --- 1,128 ----
- + /*
- +  * OMAP3/4 Voltage Processor (VP) structure and macro definitions
- +  *
- +  * Copyright (C) 2007, 2010 Texas Instruments, Inc.
- +  * Rajendra Nayak <rnayak@ti.com>
- +  * Lesly A M <x0080970@ti.com>
- +  * Thara Gopinath <thara@ti.com>
- +  *
- +  * Copyright (C) 2008, 2011 Nokia Corporation
- +  * Kalle Jokiniemi
- +  * Paul Walmsley
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License version
- +  * 2 as published by the Free Software Foundation.
- +  */
- + #ifndef __ARCH_ARM_MACH_OMAP2_VP_H
- + #define __ARCH_ARM_MACH_OMAP2_VP_H
- + 
- + #include <linux/kernel.h>
- + 
- + struct voltagedomain;
- + 
- + /*
- +  * Voltage Processor (VP) identifiers
- +  */
- + #define OMAP3_VP_VDD_MPU_ID 0
- + #define OMAP3_VP_VDD_CORE_ID 1
- + #define OMAP4_VP_VDD_CORE_ID 0
- + #define OMAP4_VP_VDD_IVA_ID 1
- + #define OMAP4_VP_VDD_MPU_ID 2
- + 
- + /* XXX document */
- + #define VP_IDLE_TIMEOUT		200
- + #define VP_TRANXDONE_TIMEOUT	300
- + 
- + /**
- +  * struct omap_vp_ops - per-VP operations
- +  * @check_txdone: check for VP transaction done
- +  * @clear_txdone: clear VP transaction done status
- +  */
- + struct omap_vp_ops {
- + 	u32 (*check_txdone)(u8 vp_id);
- + 	void (*clear_txdone)(u8 vp_id);
- + };
- + 
- + /**
- +  * struct omap_vp_common - register data common to all VDDs
- +  * @vpconfig_erroroffset_mask: ERROROFFSET bitmask in the PRM_VP*_CONFIG reg
- +  * @vpconfig_errorgain_mask: ERRORGAIN bitmask in the PRM_VP*_CONFIG reg
- +  * @vpconfig_initvoltage_mask: INITVOLTAGE bitmask in the PRM_VP*_CONFIG reg
- +  * @vpconfig_timeouten: TIMEOUT bitmask in the PRM_VP*_CONFIG reg
- +  * @vpconfig_initvdd: INITVDD bitmask in the PRM_VP*_CONFIG reg
- +  * @vpconfig_forceupdate: FORCEUPDATE bitmask in the PRM_VP*_CONFIG reg
- +  * @vpconfig_vpenable: VPENABLE bitmask in the PRM_VP*_CONFIG reg
- +  * @vpconfig_erroroffset_shift: ERROROFFSET field shift in PRM_VP*_CONFIG reg
- +  * @vpconfig_errorgain_shift: ERRORGAIN field shift in PRM_VP*_CONFIG reg
- +  * @vpconfig_initvoltage_shift: INITVOLTAGE field shift in PRM_VP*_CONFIG reg
- +  * @vstepmin_stepmin_shift: VSTEPMIN field shift in the PRM_VP*_VSTEPMIN reg
- +  * @vstepmin_smpswaittimemin_shift: SMPSWAITTIMEMIN field shift in PRM_VP*_VSTEPMIN reg
- +  * @vstepmax_stepmax_shift: VSTEPMAX field shift in the PRM_VP*_VSTEPMAX reg
- +  * @vstepmax_smpswaittimemax_shift: SMPSWAITTIMEMAX field shift in PRM_VP*_VSTEPMAX reg
- +  * @vlimitto_vddmin_shift: VDDMIN field shift in PRM_VP*_VLIMITTO reg
- +  * @vlimitto_vddmax_shift: VDDMAX field shift in PRM_VP*_VLIMITTO reg
- +  * @vlimitto_timeout_shift: TIMEOUT field shift in PRM_VP*_VLIMITTO reg
- +  * @vpvoltage_mask: VPVOLTAGE field mask in PRM_VP*_VOLTAGE reg
- +  */
- + struct omap_vp_common {
- + 	u32 vpconfig_erroroffset_mask;
- + 	u32 vpconfig_errorgain_mask;
- + 	u32 vpconfig_initvoltage_mask;
- + 	u8 vpconfig_timeouten;
- + 	u8 vpconfig_initvdd;
- + 	u8 vpconfig_forceupdate;
- + 	u8 vpconfig_vpenable;
- + 	u8 vstepmin_stepmin_shift;
- + 	u8 vstepmin_smpswaittimemin_shift;
- + 	u8 vstepmax_stepmax_shift;
- + 	u8 vstepmax_smpswaittimemax_shift;
- + 	u8 vlimitto_vddmin_shift;
- + 	u8 vlimitto_vddmax_shift;
- + 	u8 vlimitto_timeout_shift;
- + 	u8 vpvoltage_mask;
- + 
- + 	const struct omap_vp_ops *ops;
- + };
- + 
- + /**
- +  * struct omap_vp_instance - VP register offsets (per-VDD)
- +  * @common: pointer to struct omap_vp_common * for this SoC
- +  * @vpconfig: PRM_VP*_CONFIG reg offset from PRM start
- +  * @vstepmin: PRM_VP*_VSTEPMIN reg offset from PRM start
- +  * @vlimitto: PRM_VP*_VLIMITTO reg offset from PRM start
- +  * @vstatus: PRM_VP*_VSTATUS reg offset from PRM start
- +  * @voltage: PRM_VP*_VOLTAGE reg offset from PRM start
- +  * @id: Unique identifier for VP instance.
- +  * @enabled: flag to keep track of whether vp is enabled or not
- +  *
- +  * XXX vp_common is probably not needed since it is per-SoC
- +  */
- + struct omap_vp_instance {
- + 	const struct omap_vp_common *common;
- + 	u8 vpconfig;
- + 	u8 vstepmin;
- + 	u8 vstepmax;
- + 	u8 vlimitto;
- + 	u8 vstatus;
- + 	u8 voltage;
- + 	u8 id;
- + 	bool enabled;
- + };
- + 
- + extern struct omap_vp_instance omap3_vp_mpu;
- + extern struct omap_vp_instance omap3_vp_core;
- + 
- + extern struct omap_vp_instance omap4_vp_mpu;
- + extern struct omap_vp_instance omap4_vp_iva;
- + extern struct omap_vp_instance omap4_vp_core;
- + 
- + void omap_vp_init(struct voltagedomain *voltdm);
- + void omap_vp_enable(struct voltagedomain *voltdm);
- + void omap_vp_disable(struct voltagedomain *voltdm);
- + int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
- + 			      unsigned long target_volt);
- + int omap_vp_update_errorgain(struct voltagedomain *voltdm,
- + 			     unsigned long target_volt);
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/wd_timer.c linux-3.2.1/arch/arm/mach-ckb_3352/wd_timer.c
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/wd_timer.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/wd_timer.c	2014-05-15 13:25:14.012131471 +0900
- ***************
- *** 0 ****
- --- 1,56 ----
- + /*
- +  * OMAP2+ MPU WD_TIMER-specific code
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; either version 2 of the License, or
- +  * (at your option) any later version.
- +  */
- + 
- + #include <linux/kernel.h>
- + #include <linux/io.h>
- + #include <linux/err.h>
- + 
- + #include <plat/omap_hwmod.h>
- + 
- + #include "wd_timer.h"
- + 
- + /*
- +  * In order to avoid any assumptions from bootloader regarding WDT
- +  * settings, WDT module is reset during init. This enables the watchdog
- +  * timer. Hence it is required to disable the watchdog after the WDT reset
- +  * during init. Otherwise the system would reboot as per the default
- +  * watchdog timer registers settings.
- +  */
- + #define OMAP_WDT_WPS		0x34
- + #define OMAP_WDT_SPR		0x48
- + 
- + 
- + int omap2_wd_timer_disable(struct omap_hwmod *oh)
- + {
- + 	void __iomem *base;
- + 
- + 	if (!oh) {
- + 		pr_err("%s: Could not look up wdtimer_hwmod\n", __func__);
- + 		return -EINVAL;
- + 	}
- + 
- + 	base = omap_hwmod_get_mpu_rt_va(oh);
- + 	if (!base) {
- + 		pr_err("%s: Could not get the base address for %s\n",
- + 				oh->name, __func__);
- + 		return -EINVAL;
- + 	}
- + 
- + 	/* sequence required to disable watchdog */
- + 	__raw_writel(0xAAAA, base + OMAP_WDT_SPR);
- + 	while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
- + 		cpu_relax();
- + 
- + 	__raw_writel(0x5555, base + OMAP_WDT_SPR);
- + 	while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
- + 		cpu_relax();
- + 
- + 	return 0;
- + }
- + 
- diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/wd_timer.h linux-3.2.1/arch/arm/mach-ckb_3352/wd_timer.h
- *** linux-3.2.1_o/arch/arm/mach-ckb_3352/wd_timer.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/mach-ckb_3352/wd_timer.h	2014-05-15 13:25:14.012131471 +0900
- ***************
- *** 0 ****
- --- 1,17 ----
- + /*
- +  * OMAP2+ MPU WD_TIMER-specific function prototypes
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; either version 2 of the License, or
- +  * (at your option) any later version.
- +  */
- + 
- + #ifndef __ARCH_ARM_MACH_OMAP2_WD_TIMER_H
- + #define __ARCH_ARM_MACH_OMAP2_WD_TIMER_H
- + 
- + #include <plat/omap_hwmod.h>
- + 
- + extern int omap2_wd_timer_disable(struct omap_hwmod *oh);
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/Makefile linux-3.2.1/arch/arm/Makefile
- *** linux-3.2.1_o/arch/arm/Makefile	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/arch/arm/Makefile	2014-05-15 13:25:14.012131471 +0900
- ***************
- *** 136,141 ****
- --- 136,142 ----
-   # by CONFIG_* macro name.
-   machine-$(CONFIG_ARCH_AT91)		:= at91
-   machine-$(CONFIG_ARCH_BCMRING)		:= bcmring
- + machine-$(CONFIG_ARCH_CKB)			:= ckb_3352
-   machine-$(CONFIG_ARCH_CLPS711X)		:= clps711x
-   machine-$(CONFIG_ARCH_CNS3XXX)		:= cns3xxx
-   machine-$(CONFIG_ARCH_DAVINCI)		:= davinci
- ***************
- *** 201,206 ****
- --- 202,208 ----
-   
-   # Platform directory name.  This list is sorted alphanumerically
-   # by CONFIG_* macro name.
- + plat-$(CONFIG_ARCH_CKB)		:= ckb
-   plat-$(CONFIG_ARCH_MXC)		:= mxc
-   plat-$(CONFIG_ARCH_OMAP)	:= omap
-   plat-$(CONFIG_ARCH_S3C64XX)	:= samsung
- diff -crN linux-3.2.1_o/arch/arm/mm/idmap.c linux-3.2.1/arch/arm/mm/idmap.c
- *** linux-3.2.1_o/arch/arm/mm/idmap.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/arch/arm/mm/idmap.c	2014-05-15 13:25:14.032225410 +0900
- ***************
- *** 78,84 ****
-    * the user-mode pages.  This will then ensure that we have predictable
-    * results when turning the mmu off
-    */
- ! void setup_mm_for_reboot(char mode)
-   {
-   	/*
-   	 * We need to access to user-mode page tables here. For kernel threads
- --- 78,84 ----
-    * the user-mode pages.  This will then ensure that we have predictable
-    * results when turning the mmu off
-    */
- ! void setup_mm_for_reboot(void)
-   {
-   	/*
-   	 * We need to access to user-mode page tables here. For kernel threads
- diff -crN linux-3.2.1_o/arch/arm/mm/init.c linux-3.2.1/arch/arm/mm/init.c
- *** linux-3.2.1_o/arch/arm/mm/init.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/arch/arm/mm/init.c	2014-05-15 13:25:14.087648856 +0900
- ***************
- *** 35,40 ****
- --- 35,44 ----
-   
-   #include "mm.h"
-   
- + #ifdef CONFIG_MACH_CKB_3352
- + #include <mach/ckb_3352_mem.h>
- + #endif
- + 
-   static unsigned long phys_initrd_start __initdata = 0;
-   static unsigned long phys_initrd_size __initdata = 0;
-   
- ***************
- *** 692,697 ****
- --- 696,709 ----
-   			MLK_ROUNDUP(_sdata, _edata),
-   			MLK_ROUNDUP(__bss_start, __bss_stop));
-   
- + #ifdef CONFIG_MACH_CKB_3352
- + 	if(FB_DATA_ADDRESS !=0)
- + 	{
- + 		printk(KERN_NOTICE "   FB vaddr : 0x%08lx - 0x%08lx   (%4ld MB)\n", 
- + 					MLM(FB_DATA_VADDRESS, FB_DATA_VADDRESS+FB_MAP_SIZE));
- + 	}
- + #endif
- + 
-   #undef MLK
-   #undef MLM
-   #undef MLK_ROUNDUP
- diff -crN linux-3.2.1_o/arch/arm/mm/nommu.c linux-3.2.1/arch/arm/mm/nommu.c
- *** linux-3.2.1_o/arch/arm/mm/nommu.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/arch/arm/mm/nommu.c	2014-05-15 13:25:14.092289387 +0900
- ***************
- *** 29,34 ****
- --- 29,36 ----
-   
-   void __init sanity_check_meminfo(void)
-   {
- + 	phys_addr_t end = bank_phys_end(&meminfo.bank[meminfo.nr_banks - 1]);
- + 	high_memory = __va(end - 1) + 1;
-   }
-   
-   /*
- ***************
- *** 43,49 ****
-   /*
-    * We don't need to do anything here for nommu machines.
-    */
- ! void setup_mm_for_reboot(char mode)
-   {
-   }
-   
- --- 45,51 ----
-   /*
-    * We don't need to do anything here for nommu machines.
-    */
- ! void setup_mm_for_reboot(void)
-   {
-   }
-   
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/clock.c linux-3.2.1/arch/arm/plat-ckb/clock.c
- *** linux-3.2.1_o/arch/arm/plat-ckb/clock.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/clock.c	2014-05-15 13:25:14.095221515 +0900
- ***************
- *** 0 ****
- --- 1,595 ----
- + /*
- +  *  linux/arch/arm/plat-omap/clock.c
- +  *
- +  *  Copyright (C) 2004 - 2008 Nokia corporation
- +  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
- +  *
- +  *  Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + #include <linux/kernel.h>
- + #include <linux/init.h>
- + #include <linux/list.h>
- + #include <linux/errno.h>
- + #include <linux/export.h>
- + #include <linux/err.h>
- + #include <linux/string.h>
- + #include <linux/clk.h>
- + #include <linux/mutex.h>
- + #include <linux/cpufreq.h>
- + #include <linux/debugfs.h>
- + #include <linux/io.h>
- + 
- + #include <plat/clock.h>
- + 
- + static LIST_HEAD(clocks);
- + static DEFINE_MUTEX(clocks_mutex);
- + static DEFINE_SPINLOCK(clockfw_lock);
- + 
- + static struct clk_functions *arch_clock;
- + 
- + /*
- +  * Standard clock functions defined in include/linux/clk.h
- +  */
- + 
- + int clk_enable(struct clk *clk)
- + {
- + 	unsigned long flags;
- + 	int ret;
- + 
- + 	if (clk == NULL || IS_ERR(clk))
- + 		return -EINVAL;
- + 
- + 	if (!arch_clock || !arch_clock->clk_enable)
- + 		return -EINVAL;
- + 
- + 	spin_lock_irqsave(&clockfw_lock, flags);
- + 	ret = arch_clock->clk_enable(clk);
- + 	spin_unlock_irqrestore(&clockfw_lock, flags);
- + 
- + 	return ret;
- + }
- + EXPORT_SYMBOL(clk_enable);
- + 
- + void clk_disable(struct clk *clk)
- + {
- + 	unsigned long flags;
- + 
- + 	if (clk == NULL || IS_ERR(clk))
- + 		return;
- + 
- + 	if (!arch_clock || !arch_clock->clk_disable)
- + 		return;
- + 
- + 	spin_lock_irqsave(&clockfw_lock, flags);
- + 	if (clk->usecount == 0) {
- + 		pr_err("Trying disable clock %s with 0 usecount\n",
- + 		       clk->name);
- + 		WARN_ON(1);
- + 		goto out;
- + 	}
- + 
- + 	arch_clock->clk_disable(clk);
- + 
- + out:
- + 	spin_unlock_irqrestore(&clockfw_lock, flags);
- + }
- + EXPORT_SYMBOL(clk_disable);
- + 
- + unsigned long clk_get_rate(struct clk *clk)
- + {
- + 	unsigned long flags;
- + 	unsigned long ret;
- + 
- + 	if (clk == NULL || IS_ERR(clk))
- + 		return 0;
- + 
- + 	spin_lock_irqsave(&clockfw_lock, flags);
- + 	ret = clk->rate;
- + 	spin_unlock_irqrestore(&clockfw_lock, flags);
- + 
- + 	return ret;
- + }
- + EXPORT_SYMBOL(clk_get_rate);
- + 
- + /*
- +  * Optional clock functions defined in include/linux/clk.h
- +  */
- + 
- + long clk_round_rate(struct clk *clk, unsigned long rate)
- + {
- + 	unsigned long flags;
- + 	long ret;
- + 
- + 	if (clk == NULL || IS_ERR(clk))
- + 		return 0;
- + 
- + 	if (!arch_clock || !arch_clock->clk_round_rate)
- + 		return 0;
- + 
- + 	spin_lock_irqsave(&clockfw_lock, flags);
- + 	ret = arch_clock->clk_round_rate(clk, rate);
- + 	spin_unlock_irqrestore(&clockfw_lock, flags);
- + 
- + 	return ret;
- + }
- + EXPORT_SYMBOL(clk_round_rate);
- + 
- + int clk_set_rate(struct clk *clk, unsigned long rate)
- + {
- + 	unsigned long flags;
- + 	int ret = -EINVAL;
- + 
- + 	if (clk == NULL || IS_ERR(clk))
- + 		return ret;
- + 
- + 	if (!arch_clock || !arch_clock->clk_set_rate)
- + 		return ret;
- + 
- + 	spin_lock_irqsave(&clockfw_lock, flags);
- + 	ret = arch_clock->clk_set_rate(clk, rate);
- + 	if (ret == 0)
- + 		propagate_rate(clk);
- + 	spin_unlock_irqrestore(&clockfw_lock, flags);
- + 
- + 	return ret;
- + }
- + EXPORT_SYMBOL(clk_set_rate);
- + 
- + int clk_set_parent(struct clk *clk, struct clk *parent)
- + {
- + 	unsigned long flags;
- + 	int ret = -EINVAL;
- + 
- + 	if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent))
- + 		return ret;
- + 
- + 	if (!arch_clock || !arch_clock->clk_set_parent)
- + 		return ret;
- + 
- + 	spin_lock_irqsave(&clockfw_lock, flags);
- + 	if (clk->usecount == 0) {
- + 		ret = arch_clock->clk_set_parent(clk, parent);
- + 		if (ret == 0)
- + 			propagate_rate(clk);
- + 	} else
- + 		ret = -EBUSY;
- + 	spin_unlock_irqrestore(&clockfw_lock, flags);
- + 
- + 	return ret;
- + }
- + EXPORT_SYMBOL(clk_set_parent);
- + 
- + struct clk *clk_get_parent(struct clk *clk)
- + {
- + 	return clk->parent;
- + }
- + EXPORT_SYMBOL(clk_get_parent);
- + 
- + /*
- +  * OMAP specific clock functions shared between omap1 and omap2
- +  */
- + 
- + int __initdata mpurate;
- + 
- + /*
- +  * By default we use the rate set by the bootloader.
- +  * You can override this with mpurate= cmdline option.
- +  */
- + static int __init omap_clk_setup(char *str)
- + {
- + 	get_option(&str, &mpurate);
- + 
- + 	if (!mpurate)
- + 		return 1;
- + 
- + 	if (mpurate < 1000)
- + 		mpurate *= 1000000;
- + 
- + 	return 1;
- + }
- + __setup("mpurate=", omap_clk_setup);
- + 
- + /* Used for clocks that always have same value as the parent clock */
- + unsigned long followparent_recalc(struct clk *clk)
- + {
- + 	return clk->parent->rate;
- + }
- + 
- + /*
- +  * Used for clocks that have the same value as the parent clock,
- +  * divided by some factor
- +  */
- + unsigned long omap_fixed_divisor_recalc(struct clk *clk)
- + {
- + 	WARN_ON(!clk->fixed_div);
- + 
- + 	return clk->parent->rate / clk->fixed_div;
- + }
- + 
- + void clk_reparent(struct clk *child, struct clk *parent)
- + {
- + 	list_del_init(&child->sibling);
- + 	if (parent)
- + 		list_add(&child->sibling, &parent->children);
- + 	child->parent = parent;
- + 
- + 	/* now do the debugfs renaming to reattach the child
- + 	   to the proper parent */
- + }
- + 
- + /* Propagate rate to children */
- + void propagate_rate(struct clk *tclk)
- + {
- + 	struct clk *clkp;
- + 
- + 	list_for_each_entry(clkp, &tclk->children, sibling) {
- + 		if (clkp->recalc)
- + 			clkp->rate = clkp->recalc(clkp);
- + 		propagate_rate(clkp);
- + 	}
- + }
- + 
- + static LIST_HEAD(root_clks);
- + 
- + /**
- +  * recalculate_root_clocks - recalculate and propagate all root clocks
- +  *
- +  * Recalculates all root clocks (clocks with no parent), which if the
- +  * clock's .recalc is set correctly, should also propagate their rates.
- +  * Called at init.
- +  */
- + void recalculate_root_clocks(void)
- + {
- + 	struct clk *clkp;
- + 
- + 	list_for_each_entry(clkp, &root_clks, sibling) {
- + 		if (clkp->recalc)
- + 			clkp->rate = clkp->recalc(clkp);
- + 		propagate_rate(clkp);
- + 	}
- + }
- + 
- + /**
- +  * clk_preinit - initialize any fields in the struct clk before clk init
- +  * @clk: struct clk * to initialize
- +  *
- +  * Initialize any struct clk fields needed before normal clk initialization
- +  * can run.  No return value.
- +  */
- + void clk_preinit(struct clk *clk)
- + {
- + 	INIT_LIST_HEAD(&clk->children);
- + }
- + 
- + int clk_register(struct clk *clk)
- + {
- + 	if (clk == NULL || IS_ERR(clk))
- + 		return -EINVAL;
- + 
- + 	/*
- + 	 * trap out already registered clocks
- + 	 */
- + 	if (clk->node.next || clk->node.prev)
- + 		return 0;
- + 
- + 	mutex_lock(&clocks_mutex);
- + 	if (clk->parent)
- + 		list_add(&clk->sibling, &clk->parent->children);
- + 	else
- + 		list_add(&clk->sibling, &root_clks);
- + 
- + 	list_add(&clk->node, &clocks);
- + 	if (clk->init)
- + 		clk->init(clk);
- + 	mutex_unlock(&clocks_mutex);
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(clk_register);
- + 
- + void clk_unregister(struct clk *clk)
- + {
- + 	if (clk == NULL || IS_ERR(clk))
- + 		return;
- + 
- + 	mutex_lock(&clocks_mutex);
- + 	list_del(&clk->sibling);
- + 	list_del(&clk->node);
- + 	mutex_unlock(&clocks_mutex);
- + }
- + EXPORT_SYMBOL(clk_unregister);
- + 
- + void clk_enable_init_clocks(void)
- + {
- + 	struct clk *clkp;
- + 
- + 	list_for_each_entry(clkp, &clocks, node) {
- + 		if (clkp->flags & ENABLE_ON_INIT)
- + 			clk_enable(clkp);
- + 	}
- + }
- + 
- + /**
- +  * omap_clk_get_by_name - locate OMAP struct clk by its name
- +  * @name: name of the struct clk to locate
- +  *
- +  * Locate an OMAP struct clk by its name.  Assumes that struct clk
- +  * names are unique.  Returns NULL if not found or a pointer to the
- +  * struct clk if found.
- +  */
- + struct clk *omap_clk_get_by_name(const char *name)
- + {
- + 	struct clk *c;
- + 	struct clk *ret = NULL;
- + 
- + 	mutex_lock(&clocks_mutex);
- + 
- + 	list_for_each_entry(c, &clocks, node) {
- + 		if (!strcmp(c->name, name)) {
- + 			ret = c;
- + 			break;
- + 		}
- + 	}
- + 
- + 	mutex_unlock(&clocks_mutex);
- + 
- + 	return ret;
- + }
- + 
- + int omap_clk_enable_autoidle_all(void)
- + {
- + 	struct clk *c;
- + 	unsigned long flags;
- + 
- + 	spin_lock_irqsave(&clockfw_lock, flags);
- + 
- + 	list_for_each_entry(c, &clocks, node)
- + 		if (c->ops->allow_idle)
- + 			c->ops->allow_idle(c);
- + 
- + 	spin_unlock_irqrestore(&clockfw_lock, flags);
- + 
- + 	return 0;
- + }
- + 
- + int omap_clk_disable_autoidle_all(void)
- + {
- + 	struct clk *c;
- + 	unsigned long flags;
- + 
- + 	spin_lock_irqsave(&clockfw_lock, flags);
- + 
- + 	list_for_each_entry(c, &clocks, node)
- + 		if (c->ops->deny_idle)
- + 			c->ops->deny_idle(c);
- + 
- + 	spin_unlock_irqrestore(&clockfw_lock, flags);
- + 
- + 	return 0;
- + }
- + 
- + /*
- +  * Low level helpers
- +  */
- + static int clkll_enable_null(struct clk *clk)
- + {
- + 	return 0;
- + }
- + 
- + static void clkll_disable_null(struct clk *clk)
- + {
- + }
- + 
- + const struct clkops clkops_null = {
- + 	.enable		= clkll_enable_null,
- + 	.disable	= clkll_disable_null,
- + };
- + 
- + /*
- +  * Dummy clock
- +  *
- +  * Used for clock aliases that are needed on some OMAPs, but not others
- +  */
- + struct clk dummy_ck = {
- + 	.name	= "dummy",
- + 	.ops	= &clkops_null,
- + };
- + 
- + #ifdef CONFIG_CPU_FREQ
- + void clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
- + {
- + 	unsigned long flags;
- + 
- + 	if (!arch_clock || !arch_clock->clk_init_cpufreq_table)
- + 		return;
- + 
- + 	spin_lock_irqsave(&clockfw_lock, flags);
- + 	arch_clock->clk_init_cpufreq_table(table);
- + 	spin_unlock_irqrestore(&clockfw_lock, flags);
- + }
- + 
- + void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
- + {
- + 	unsigned long flags;
- + 
- + 	if (!arch_clock || !arch_clock->clk_exit_cpufreq_table)
- + 		return;
- + 
- + 	spin_lock_irqsave(&clockfw_lock, flags);
- + 	arch_clock->clk_exit_cpufreq_table(table);
- + 	spin_unlock_irqrestore(&clockfw_lock, flags);
- + }
- + #endif
- + 
- + /*
- +  *
- +  */
- + 
- + #ifdef CONFIG_OMAP_RESET_CLOCKS
- + /*
- +  * Disable any unused clocks left on by the bootloader
- +  */
- + static int __init clk_disable_unused(void)
- + {
- + 	struct clk *ck;
- + 	unsigned long flags;
- + 
- + 	if (!arch_clock || !arch_clock->clk_disable_unused)
- + 		return 0;
- + 
- + 	pr_info("clock: disabling unused clocks to save power\n");
- + 	list_for_each_entry(ck, &clocks, node) {
- + 		if (ck->ops == &clkops_null)
- + 			continue;
- + 
- + 		if (ck->usecount > 0 || !ck->enable_reg)
- + 			continue;
- + 
- + 		spin_lock_irqsave(&clockfw_lock, flags);
- + 		arch_clock->clk_disable_unused(ck);
- + 		spin_unlock_irqrestore(&clockfw_lock, flags);
- + 	}
- + 
- + 	return 0;
- + }
- + late_initcall(clk_disable_unused);
- + late_initcall(omap_clk_enable_autoidle_all);
- + #endif
- + 
- + int __init clk_init(struct clk_functions * custom_clocks)
- + {
- + 	if (!custom_clocks) {
- + 		pr_err("No custom clock functions registered\n");
- + 		BUG();
- + 	}
- + 
- + 	arch_clock = custom_clocks;
- + 
- + 	return 0;
- + }
- + 
- + #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
- + /*
- +  *	debugfs support to trace clock tree hierarchy and attributes
- +  */
- + 
- + #include <linux/debugfs.h>
- + #include <linux/seq_file.h>
- + 
- + static struct dentry *clk_debugfs_root;
- + 
- + static int clk_dbg_show_summary(struct seq_file *s, void *unused)
- + {
- + 	struct clk *c;
- + 	struct clk *pa;
- + 
- + 	seq_printf(s, "%-30s %-30s %-10s %s\n",
- + 		"clock-name", "parent-name", "rate", "use-count");
- + 
- + 	list_for_each_entry(c, &clocks, node) {
- + 		pa = c->parent;
- + 		seq_printf(s, "%-30s %-30s %-10lu %d\n",
- + 			c->name, pa ? pa->name : "none", c->rate, c->usecount);
- + 	}
- + 
- + 	return 0;
- + }
- + 
- + static int clk_dbg_open(struct inode *inode, struct file *file)
- + {
- + 	return single_open(file, clk_dbg_show_summary, inode->i_private);
- + }
- + 
- + static const struct file_operations debug_clock_fops = {
- + 	.open           = clk_dbg_open,
- + 	.read           = seq_read,
- + 	.llseek         = seq_lseek,
- + 	.release        = single_release,
- + };
- + 
- + static int clk_debugfs_register_one(struct clk *c)
- + {
- + 	int err;
- + 	struct dentry *d;
- + 	struct clk *pa = c->parent;
- + 
- + 	d = debugfs_create_dir(c->name, pa ? pa->dent : clk_debugfs_root);
- + 	if (!d)
- + 		return -ENOMEM;
- + 	c->dent = d;
- + 
- + 	d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usecount);
- + 	if (!d) {
- + 		err = -ENOMEM;
- + 		goto err_out;
- + 	}
- + 	d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
- + 	if (!d) {
- + 		err = -ENOMEM;
- + 		goto err_out;
- + 	}
- + 	d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
- + 	if (!d) {
- + 		err = -ENOMEM;
- + 		goto err_out;
- + 	}
- + 	return 0;
- + 
- + err_out:
- + 	debugfs_remove_recursive(c->dent);
- + 	return err;
- + }
- + 
- + static int clk_debugfs_register(struct clk *c)
- + {
- + 	int err;
- + 	struct clk *pa = c->parent;
- + 
- + 	if (pa && !pa->dent) {
- + 		err = clk_debugfs_register(pa);
- + 		if (err)
- + 			return err;
- + 	}
- + 
- + 	if (!c->dent) {
- + 		err = clk_debugfs_register_one(c);
- + 		if (err)
- + 			return err;
- + 	}
- + 	return 0;
- + }
- + 
- + static int __init clk_debugfs_init(void)
- + {
- + 	struct clk *c;
- + 	struct dentry *d;
- + 	int err;
- + 
- + 	d = debugfs_create_dir("clock", NULL);
- + 	if (!d)
- + 		return -ENOMEM;
- + 	clk_debugfs_root = d;
- + 
- + 	list_for_each_entry(c, &clocks, node) {
- + 		err = clk_debugfs_register(c);
- + 		if (err)
- + 			goto err_out;
- + 	}
- + 
- + 	d = debugfs_create_file("summary", S_IRUGO,
- + 		d, NULL, &debug_clock_fops);
- + 	if (!d)
- + 		return -ENOMEM;
- + 
- + 	return 0;
- + err_out:
- + 	debugfs_remove_recursive(clk_debugfs_root);
- + 	return err;
- + }
- + late_initcall(clk_debugfs_init);
- + 
- + #endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/common.c linux-3.2.1/arch/arm/plat-ckb/common.c
- *** linux-3.2.1_o/arch/arm/plat-ckb/common.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/common.c	2014-05-15 13:25:14.095221515 +0900
- ***************
- *** 0 ****
- --- 1,68 ----
- + /*
- +  * linux/arch/arm/plat-omap/common.c
- +  *
- +  * Code common to all OMAP machines.
- +  * The file is created by Tony Lindgren <tony@atomide.com>
- +  *
- +  * Copyright (C) 2009 Texas Instruments
- +  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + #include <linux/kernel.h>
- + #include <linux/init.h>
- + #include <linux/io.h>
- + #include <linux/dma-mapping.h>
- + #include <linux/omapfb.h>
- + 
- + #include <plat/common.h>
- + #include <plat/board.h>
- + //#include <plat/vram.h>
- + 
- + 
- + #define NO_LENGTH_CHECK 0xffffffff
- + 
- + struct omap_board_config_kernel *omap_board_config __initdata;
- + int omap_board_config_size;
- + 
- + static const void *__init get_config(u16 tag, size_t len,
- + 		int skip, size_t *len_out)
- + {
- + 	struct omap_board_config_kernel *kinfo = NULL;
- + 	int i;
- + 
- + 	/* Try to find the config from the board-specific structures
- + 	 * in the kernel. */
- + 	for (i = 0; i < omap_board_config_size; i++) {
- + 		if (omap_board_config[i].tag == tag) {
- + 			if (skip == 0) {
- + 				kinfo = &omap_board_config[i];
- + 				break;
- + 			} else {
- + 				skip--;
- + 			}
- + 		}
- + 	}
- + 	if (kinfo == NULL)
- + 		return NULL;
- + 	return kinfo->data;
- + }
- + 
- + const void *__init __omap_get_config(u16 tag, size_t len, int nr)
- + {
- +         return get_config(tag, len, nr, NULL);
- + }
- + 
- + const void *__init omap_get_var_config(u16 tag, size_t *len)
- + {
- +         return get_config(tag, NO_LENGTH_CHECK, 0, len);
- + }
- + 
- + void __init omap_init_consistent_dma_size(void)
- + {
- + #ifdef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
- + 	init_consistent_dma_size(CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE << 20);
- + #endif
- + }
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/counter_32k.c linux-3.2.1/arch/arm/plat-ckb/counter_32k.c
- *** linux-3.2.1_o/arch/arm/plat-ckb/counter_32k.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/counter_32k.c	2014-05-15 13:25:14.099048990 +0900
- ***************
- *** 0 ****
- --- 1,142 ----
- + /*
- +  * OMAP 32ksynctimer/counter_32k-related code
- +  *
- +  * Copyright (C) 2009 Texas Instruments
- +  * Copyright (C) 2010 Nokia Corporation
- +  * Tony Lindgren <tony@atomide.com>
- +  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  *
- +  * NOTE: This timer is not the same timer as the old OMAP1 MPU timer.
- +  */
- + #include <linux/kernel.h>
- + #include <linux/init.h>
- + #include <linux/clk.h>
- + #include <linux/err.h>
- + #include <linux/io.h>
- + #include <linux/sched.h>
- + #include <linux/clocksource.h>
- + 
- + #include <asm/sched_clock.h>
- + 
- + #include <plat/common.h>
- + #include <plat/board.h>
- + 
- + #include <plat/clock.h>
- + 
- + /*
- +  * 32KHz clocksource ... always available, on pretty most chips except
- +  * OMAP 730 and 1510.  Other timers could be used as clocksources, with
- +  * higher resolution in free-running counter modes (e.g. 12 MHz xtal),
- +  * but systems won't necessarily want to spend resources that way.
- +  */
- + static void __iomem *timer_32k_base;
- + 
- + #define OMAP16XX_TIMER_32K_SYNCHRONIZED		0xfffbc410
- + 
- + /*
- +  * Returns current time from boot in nsecs. It's OK for this to wrap
- +  * around for now, as it's just a relative time stamp.
- +  */
- + static DEFINE_CLOCK_DATA(cd);
- + 
- + /*
- +  * Constants generated by clocks_calc_mult_shift(m, s, 32768, NSEC_PER_SEC, 60).
- +  * This gives a resolution of about 30us and a wrap period of about 36hrs.
- +  */
- + #define SC_MULT		4000000000u
- + #define SC_SHIFT	17
- + 
- + static inline unsigned long long notrace _omap_32k_sched_clock(void)
- + {
- + 	u32 cyc = timer_32k_base ? __raw_readl(timer_32k_base) : 0;
- + 	return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, SC_MULT, SC_SHIFT);
- + }
- + 
- + #if defined(CONFIG_OMAP_32K_TIMER) && !defined(CONFIG_OMAP_MPU_TIMER)
- + unsigned long long notrace sched_clock(void)
- + {
- + 	return _omap_32k_sched_clock();
- + }
- + #else
- + unsigned long long notrace omap_32k_sched_clock(void)
- + {
- + 	return _omap_32k_sched_clock();
- + }
- + #endif
- + 
- + 
- + static void notrace omap_update_sched_clock(void)
- + {
- + 	u32 cyc = timer_32k_base ? __raw_readl(timer_32k_base) : 0;
- + 	update_sched_clock(&cd, cyc, (u32)~0);
- + }
- + 
- + /**
- +  * read_persistent_clock -  Return time from a persistent clock.
- +  *
- +  * Reads the time from a source which isn't disabled during PM, the
- +  * 32k sync timer.  Convert the cycles elapsed since last read into
- +  * nsecs and adds to a monotonically increasing timespec.
- +  */
- + static struct timespec persistent_ts;
- + static cycles_t cycles, last_cycles;
- + static unsigned int persistent_mult, persistent_shift;
- + void read_persistent_clock(struct timespec *ts)
- + {
- + 	unsigned long long nsecs;
- + 	cycles_t delta;
- + 	struct timespec *tsp = &persistent_ts;
- + 
- + 	last_cycles = cycles;
- + 	cycles = timer_32k_base ? __raw_readl(timer_32k_base) : 0;
- + 	delta = cycles - last_cycles;
- + 
- + 	nsecs = clocksource_cyc2ns(delta, persistent_mult, persistent_shift);
- + 
- + 	timespec_add_ns(tsp, nsecs);
- + 	*ts = *tsp;
- + }
- + 
- + int __init omap_init_clocksource_32k(void)
- + {
- + 	static char err[] __initdata = KERN_ERR
- + 			"%s: can't register clocksource!\n";
- + 
- + 		u32 pbase;
- + 		unsigned long size = SZ_4K;
- + 		void __iomem *base;
- + 		struct clk *sync_32k_ick;
- + 
- + 		pbase = OMAP3430_32KSYNCT_BASE + 0x10;
- + 		
- + 		/* For this to work we must have a static mapping in io.c for this area */
- + 		base = ioremap(pbase, size);
- + 		if (!base)
- + 			return -ENODEV;
- + 
- + 		sync_32k_ick = clk_get(NULL, "omap_32ksync_ick");
- + 		if (!IS_ERR(sync_32k_ick))
- + 			clk_enable(sync_32k_ick);
- + 
- + 		timer_32k_base = base;
- + 
- + 		/*
- + 		 * 120000 rough estimate from the calculations in
- + 		 * __clocksource_updatefreq_scale.
- + 		 */
- + 		clocks_calc_mult_shift(&persistent_mult, &persistent_shift,
- + 				32768, NSEC_PER_SEC, 120000);
- + 
- + 		if (clocksource_mmio_init(base, "32k_counter", 32768, 250, 32,
- + 					  clocksource_mmio_readl_up))
- + 			printk(err, "32k_counter");
- + 
- + 		init_fixed_sched_clock(&cd, omap_update_sched_clock, 32,
- + 				       32768, SC_MULT, SC_SHIFT);
- + 
- + 	return 0;
- + }
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/devices.c linux-3.2.1/arch/arm/plat-ckb/devices.c
- *** linux-3.2.1_o/arch/arm/plat-ckb/devices.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/devices.c	2014-05-15 13:25:14.099048990 +0900
- ***************
- *** 0 ****
- --- 1,146 ----
- + /*
- +  * linux/arch/arm/plat-omap/devices.c
- +  *
- +  * Common platform device setup/initialization for OMAP1 and OMAP2
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; either version 2 of the License, or
- +  * (at your option) any later version.
- +  */
- + #include <linux/gpio.h>
- + #include <linux/module.h>
- + #include <linux/kernel.h>
- + #include <linux/init.h>
- + #include <linux/platform_device.h>
- + #include <linux/io.h>
- + #include <linux/slab.h>
- + #include <linux/memblock.h>
- + 
- + #include <mach/hardware.h>
- + #include <asm/mach-types.h>
- + #include <asm/mach/map.h>
- + 
- + #include <plat/board.h>
- + #include <plat/mmc.h>
- + //#include <plat/omap44xx.h>
- + #include <plat/am33xx.h>
- + 
- + #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
- + 	defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
- + 
- + #define OMAP_MMC_NR_RES		2
- + 
- + /*
- +  * Register MMC devices. Called from mach-omap1 and mach-omap2 device init.
- +  */
- + int __init omap_mmc_add(const char *name, int id, unsigned long base,
- + 				unsigned long size, unsigned int irq,
- + 				struct omap_mmc_platform_data *data)
- + {
- + 	struct platform_device *pdev;
- + 	struct resource res[OMAP_MMC_NR_RES];
- + 	int ret;
- + 
- + 	pdev = platform_device_alloc(name, id);
- + 	if (!pdev)
- + 		return -ENOMEM;
- + 
- + 	memset(res, 0, OMAP_MMC_NR_RES * sizeof(struct resource));
- + 	res[0].start = base;
- + 	res[0].end = base + size - 1;
- + 	res[0].flags = IORESOURCE_MEM;
- + 	res[1].start = res[1].end = irq;
- + 	res[1].flags = IORESOURCE_IRQ;
- + 
- + 	ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
- + 	if (ret == 0)
- + 		ret = platform_device_add_data(pdev, data, sizeof(*data));
- + 	if (ret)
- + 		goto fail;
- + 
- + 	ret = platform_device_add(pdev);
- + 	if (ret)
- + 		goto fail;
- + 
- + 	/* return device handle to board setup code */
- + 	data->dev = &pdev->dev;
- + 	return 0;
- + 
- + fail:
- + 	platform_device_put(pdev);
- + 	return ret;
- + }
- + 
- + #endif
- + 
- + /*-------------------------------------------------------------------------*/
- + 
- + #if defined(CONFIG_HW_RANDOM_OMAP) || defined(CONFIG_HW_RANDOM_OMAP_MODULE)
- + 
- + #define	OMAP_RNG_BASE		0xfffe5000
- + 
- + static struct resource rng_resources[] = {
- + 	{
- + 		.start		= OMAP_RNG_BASE,
- + 		.end		= OMAP_RNG_BASE + 0x4f,
- + 		.flags		= IORESOURCE_MEM,
- + 	},
- + };
- + 
- + static struct platform_device omap_rng_device = {
- + 	.name		= "omap_rng",
- + 	.id		= -1,
- + 	.num_resources	= ARRAY_SIZE(rng_resources),
- + 	.resource	= rng_resources,
- + };
- + 
- + static void omap_init_rng(void)
- + {
- + 	(void) platform_device_register(&omap_rng_device);
- + }
- + #else
- + static inline void omap_init_rng(void) {}
- + #endif
- + 
- + 
- + #if defined(CONFIG_TIDSPBRIDGE) || defined(CONFIG_TIDSPBRIDGE_MODULE)
- + 
- + static phys_addr_t omap_dsp_phys_mempool_base;
- + 
- + phys_addr_t omap_dsp_get_mempool_base(void)
- + {
- + 	return omap_dsp_phys_mempool_base;
- + }
- + EXPORT_SYMBOL(omap_dsp_get_mempool_base);
- + #endif
- + 
- + /*
- +  * This gets called after board-specific INIT_MACHINE, and initializes most
- +  * on-chip peripherals accessible on this board (except for few like USB):
- +  *
- +  *  (a) Does any "standard config" pin muxing needed.  Board-specific
- +  *	code will have muxed GPIO pins and done "nonstandard" setup;
- +  *	that code could live in the boot loader.
- +  *  (b) Populating board-specific platform_data with the data drivers
- +  *	rely on to handle wiring variations.
- +  *  (c) Creating platform devices as meaningful on this board and
- +  *	with this kernel configuration.
- +  *
- +  * Claiming GPIOs, and setting their direction and initial values, is the
- +  * responsibility of the device drivers.  So is responding to probe().
- +  *
- +  * Board-specific knowledge like creating devices or pin setup is to be
- +  * kept out of drivers as much as possible.  In particular, pin setup
- +  * may be handled by the boot loader, and drivers should expect it will
- +  * normally have been done by the time they're probed.
- +  */
- + static int __init omap_init_devices(void)
- + {
- + 	/* please keep these calls, and their implementations above,
- + 	 * in alphabetical order so they're easier to sort through.
- + 	 */
- + 	omap_init_rng();
- + 	return 0;
- + }
- + arch_initcall(omap_init_devices);
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/dmtimer.c linux-3.2.1/arch/arm/plat-ckb/dmtimer.c
- *** linux-3.2.1_o/arch/arm/plat-ckb/dmtimer.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/dmtimer.c	2014-05-15 13:25:14.099048990 +0900
- ***************
- *** 0 ****
- --- 1,742 ----
- + /*
- +  * linux/arch/arm/plat-omap/dmtimer.c
- +  *
- +  * OMAP Dual-Mode Timers
- +  *
- +  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- +  * Tarun Kanti DebBarma <tarun.kanti@ti.com>
- +  * Thara Gopinath <thara@ti.com>
- +  *
- +  * dmtimer adaptation to platform_driver.
- +  *
- +  * Copyright (C) 2005 Nokia Corporation
- +  * OMAP2 support by Juha Yrjola
- +  * API improvements and OMAP2 clock framework support by Timo Teras
- +  *
- +  * Copyright (C) 2009 Texas Instruments
- +  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify it
- +  * under the terms of the GNU General Public License as published by the
- +  * Free Software Foundation; either version 2 of the License, or (at your
- +  * option) any later version.
- +  *
- +  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- +  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- +  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- +  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- +  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- +  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- +  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- +  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- +  *
- +  * You should have received a copy of the  GNU General Public License along
- +  * with this program; if not, write  to the Free Software Foundation, Inc.,
- +  * 675 Mass Ave, Cambridge, MA 02139, USA.
- +  */
- + 
- + #include <linux/module.h>
- + #include <linux/io.h>
- + #include <linux/slab.h>
- + #include <linux/err.h>
- + #include <linux/pm_runtime.h>
- + 
- + #include <plat/dmtimer.h>
- + 
- + static LIST_HEAD(omap_timer_list);
- + static DEFINE_SPINLOCK(dm_timer_lock);
- + 
- + /**
- +  * omap_dm_timer_read_reg - read timer registers in posted and non-posted mode
- +  * @timer:      timer pointer over which read operation to perform
- +  * @reg:        lowest byte holds the register offset
- +  *
- +  * The posted mode bit is encoded in reg. Note that in posted mode write
- +  * pending bit must be checked. Otherwise a read of a non completed write
- +  * will produce an error.
- +  */
- + static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
- + {
- + 	WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
- + 	return __omap_dm_timer_read(timer, reg, timer->posted);
- + }
- + 
- + /**
- +  * omap_dm_timer_write_reg - write timer registers in posted and non-posted mode
- +  * @timer:      timer pointer over which write operation is to perform
- +  * @reg:        lowest byte holds the register offset
- +  * @value:      data to write into the register
- +  *
- +  * The posted mode bit is encoded in reg. Note that in posted mode the write
- +  * pending bit must be checked. Otherwise a write on a register which has a
- +  * pending write will be lost.
- +  */
- + static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
- + 						u32 value)
- + {
- + 	WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
- + 	__omap_dm_timer_write(timer, reg, value, timer->posted);
- + }
- + 
- + static void omap_timer_restore_context(struct omap_dm_timer *timer)
- + {
- + 	omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_OFFSET,
- + 				timer->context.tiocp_cfg);
- + 	if (timer->revision > 1)
- + 		__raw_writel(timer->context.tistat, timer->sys_stat);
- + 
- + 	__raw_writel(timer->context.tisr, timer->irq_stat);
- + 	omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG,
- + 				timer->context.twer);
- + 	omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG,
- + 				timer->context.tcrr);
- + 	omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG,
- + 				timer->context.tldr);
- + 	omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG,
- + 				timer->context.tmar);
- + 	omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
- + 				timer->context.tsicr);
- + 	__raw_writel(timer->context.tier, timer->irq_ena);
- + 	omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG,
- + 				timer->context.tclr);
- + }
- + 
- + static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
- + {
- + 	int c;
- + 
- + 	if (!timer->sys_stat)
- + 		return;
- + 
- + 	c = 0;
- + 	while (!(__raw_readl(timer->sys_stat) & 1)) {
- + 		c++;
- + 		if (c > 100000) {
- + 			printk(KERN_ERR "Timer failed to reset\n");
- + 			return;
- + 		}
- + 	}
- + }
- + 
- + static void omap_dm_timer_reset(struct omap_dm_timer *timer)
- + {
- + 	omap_dm_timer_enable(timer);
- + 	if (timer->pdev->id != 1) {
- + 		omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
- + 		omap_dm_timer_wait_for_reset(timer);
- + 	}
- + 
- + 	__omap_dm_timer_reset(timer, 0, 0);
- + 	omap_dm_timer_disable(timer);
- + 	timer->posted = 1;
- + }
- + 
- + int omap_dm_timer_prepare(struct omap_dm_timer *timer)
- + {
- + 	struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data;
- + 
- + 	timer->fclk = clk_get(&timer->pdev->dev, "fck");
- + 	if (WARN_ON_ONCE(IS_ERR_OR_NULL(timer->fclk))) {
- + 		timer->fclk = NULL;
- + 		dev_err(&timer->pdev->dev, ": No fclk handle.\n");
- + 		return -EINVAL;
- + 	}
- + 
- + 	if (pdata->needs_manual_reset)
- + 		omap_dm_timer_reset(timer);
- + 
- + 	timer->posted = 1;
- + 	return 0;
- + }
- + 
- + struct omap_dm_timer *omap_dm_timer_request(void)
- + {
- + 	struct omap_dm_timer *timer = NULL, *t;
- + 	unsigned long flags;
- + 	int ret = 0;
- + 
- + 	spin_lock_irqsave(&dm_timer_lock, flags);
- + 	list_for_each_entry(t, &omap_timer_list, node) {
- + 		if (t->reserved)
- + 			continue;
- + 
- + 		timer = t;
- + 		timer->reserved = 1;
- + 		break;
- + 	}
- + 
- + 	if (timer) {
- + 		ret = omap_dm_timer_prepare(timer);
- + 		if (ret) {
- + 			timer->reserved = 0;
- + 			timer = NULL;
- + 		}
- + 	}
- + 	spin_unlock_irqrestore(&dm_timer_lock, flags);
- + 
- + 	if (!timer)
- + 		pr_debug("%s: timer request failed!\n", __func__);
- + 
- + 	return timer;
- + }
- + EXPORT_SYMBOL_GPL(omap_dm_timer_request);
- + 
- + struct omap_dm_timer *omap_dm_timer_request_specific(int id)
- + {
- + 	struct omap_dm_timer *timer = NULL, *t;
- + 	unsigned long flags;
- + 	int ret = 0;
- + 
- + 	spin_lock_irqsave(&dm_timer_lock, flags);
- + 	list_for_each_entry(t, &omap_timer_list, node) {
- + 		if (t->pdev->id == id && !t->reserved) {
- + 			timer = t;
- + 			timer->reserved = 1;
- + 			break;
- + 		}
- + 	}
- + 
- + 	if (timer) {
- + 		ret = omap_dm_timer_prepare(timer);
- + 		if (ret) {
- + 			timer->reserved = 0;
- + 			timer = NULL;
- + 		}
- + 	}
- + 	spin_unlock_irqrestore(&dm_timer_lock, flags);
- + 
- + 	if (!timer)
- + 		pr_debug("%s: timer%d request failed!\n", __func__, id);
- + 
- + 	return timer;
- + }
- + EXPORT_SYMBOL_GPL(omap_dm_timer_request_specific);
- + 
- + int omap_dm_timer_free(struct omap_dm_timer *timer)
- + {
- + 	if (unlikely(!timer))
- + 		return -EINVAL;
- + 
- + 	clk_put(timer->fclk);
- + 
- + 	WARN_ON(!timer->reserved);
- + 	timer->reserved = 0;
- + 	return 0;
- + }
- + EXPORT_SYMBOL_GPL(omap_dm_timer_free);
- + 
- + void omap_dm_timer_enable(struct omap_dm_timer *timer)
- + {
- + 	pm_runtime_get_sync(&timer->pdev->dev);
- + }
- + EXPORT_SYMBOL_GPL(omap_dm_timer_enable);
- + 
- + void omap_dm_timer_disable(struct omap_dm_timer *timer)
- + {
- + 	pm_runtime_put(&timer->pdev->dev);
- + }
- + EXPORT_SYMBOL_GPL(omap_dm_timer_disable);
- + 
- + int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
- + {
- + 	if (timer)
- + 		return timer->irq;
- + 	return -EINVAL;
- + }
- + EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq);
- + 
- + 
- + struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
- + {
- + 	if (timer)
- + 		return timer->fclk;
- + 	return NULL;
- + }
- + EXPORT_SYMBOL_GPL(omap_dm_timer_get_fclk);
- + 
- + __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
- + {
- + 	BUG();
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
- + 
- + int omap_dm_timer_trigger(struct omap_dm_timer *timer)
- + {
- + 	if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
- + 		pr_err("%s: timer not available or enabled.\n", __func__);
- + 		return -EINVAL;
- + 	}
- + 
- + 	omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
- + 	return 0;
- + }
- + EXPORT_SYMBOL_GPL(omap_dm_timer_trigger);
- + 
- + int omap_dm_timer_start(struct omap_dm_timer *timer)
- + {
- + 	u32 l;
- + 
- + 	if (unlikely(!timer))
- + 		return -EINVAL;
- + 
- + 	omap_dm_timer_enable(timer);
- + 
- + 	if (timer->loses_context) {
- + 		u32 ctx_loss_cnt_after =
- + 			timer->get_context_loss_count(&timer->pdev->dev);
- + 		if (ctx_loss_cnt_after != timer->ctx_loss_count)
- + 			omap_timer_restore_context(timer);
- + 	}
- + 
- + 	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
- + 	if (!(l & OMAP_TIMER_CTRL_ST)) {
- + 		l |= OMAP_TIMER_CTRL_ST;
- + 		omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
- + 	}
- + 
- + 	/* Save the context */
- + 	timer->context.tclr = l;
- + 	return 0;
- + }
- + EXPORT_SYMBOL_GPL(omap_dm_timer_start);
- + 
- + int omap_dm_timer_stop(struct omap_dm_timer *timer)
- + {
- + 	unsigned long rate = 0;
- + 	struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data;
- + 
- + 	if (unlikely(!timer))
- + 		return -EINVAL;
- + 
- + 	if (!pdata->needs_manual_reset)
- + 		rate = clk_get_rate(timer->fclk);
- + 
- + 	__omap_dm_timer_stop(timer, timer->posted, rate);
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
- + 
- + int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
- + {
- + 	int ret;
- + 	struct dmtimer_platform_data *pdata;
- + 
- + 	if (unlikely(!timer))
- + 		return -EINVAL;
- + 
- + 	pdata = timer->pdev->dev.platform_data;
- + 
- + 	if (source < 0 || source >= 3)
- + 		return -EINVAL;
- + 
- + 	ret = pdata->set_timer_src(timer->pdev, source);
- + 
- + 	return ret;
- + }
- + EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
- + 
- + int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
- + 			    unsigned int load)
- + {
- + 	u32 l;
- + 
- + 	if (unlikely(!timer))
- + 		return -EINVAL;
- + 
- + 	omap_dm_timer_enable(timer);
- + 	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
- + 	if (autoreload)
- + 		l |= OMAP_TIMER_CTRL_AR;
- + 	else
- + 		l &= ~OMAP_TIMER_CTRL_AR;
- + 	omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
- + 	omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
- + 
- + 	omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
- + 	/* Save the context */
- + 	timer->context.tclr = l;
- + 	timer->context.tldr = load;
- + 	omap_dm_timer_disable(timer);
- + 	return 0;
- + }
- + EXPORT_SYMBOL_GPL(omap_dm_timer_set_load);
- + 
- + /* Optimized set_load which removes costly spin wait in timer_start */
- + int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
- +                             unsigned int load)
- + {
- + 	u32 l;
- + 
- + 	if (unlikely(!timer))
- + 		return -EINVAL;
- + 
- + 	omap_dm_timer_enable(timer);
- + 
- + 	if (timer->loses_context) {
- + 		u32 ctx_loss_cnt_after =
- + 			timer->get_context_loss_count(&timer->pdev->dev);
- + 		if (ctx_loss_cnt_after != timer->ctx_loss_count)
- + 			omap_timer_restore_context(timer);
- + 	}
- + 
- + 	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
- + 	if (autoreload) {
- + 		l |= OMAP_TIMER_CTRL_AR;
- + 		omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
- + 	} else {
- + 		l &= ~OMAP_TIMER_CTRL_AR;
- + 	}
- + 	l |= OMAP_TIMER_CTRL_ST;
- + 
- + 	__omap_dm_timer_load_start(timer, l, load, timer->posted);
- + 
- + 	/* Save the context */
- + 	timer->context.tclr = l;
- + 	timer->context.tldr = load;
- + 	timer->context.tcrr = load;
- + 	return 0;
- + }
- + EXPORT_SYMBOL_GPL(omap_dm_timer_set_load_start);
- + 
- + int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
- + 			     unsigned int match)
- + {
- + 	u32 l;
- + 
- + 	if (unlikely(!timer))
- + 		return -EINVAL;
- + 
- + 	omap_dm_timer_enable(timer);
- + 	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
- + 	if (enable)
- + 		l |= OMAP_TIMER_CTRL_CE;
- + 	else
- + 		l &= ~OMAP_TIMER_CTRL_CE;
- + 	omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
- + 	omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
- + 
- + 	/* Save the context */
- + 	timer->context.tclr = l;
- + 	timer->context.tmar = match;
- + 	omap_dm_timer_disable(timer);
- + 	return 0;
- + }
- + EXPORT_SYMBOL_GPL(omap_dm_timer_set_match);
- + 
- + int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
- + 			   int toggle, int trigger)
- + {
- + 	u32 l;
- + 
- + 	if (unlikely(!timer))
- + 		return -EINVAL;
- + 
- + 	omap_dm_timer_enable(timer);
- + 	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
- + 	l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
- + 	       OMAP_TIMER_CTRL_PT | (0x03 << 10));
- + 	if (def_on)
- + 		l |= OMAP_TIMER_CTRL_SCPWM;
- + 	if (toggle)
- + 		l |= OMAP_TIMER_CTRL_PT;
- + 	l |= trigger << 10;
- + 	omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
- + 
- + 	/* Save the context */
- + 	timer->context.tclr = l;
- + 	omap_dm_timer_disable(timer);
- + 	return 0;
- + }
- + EXPORT_SYMBOL_GPL(omap_dm_timer_set_pwm);
- + 
- + int omap_dm_timer_set_capture(struct omap_dm_timer *timer, bool lht,
- + 				bool hlt, bool cm)
- + {
- + 	u32 l;
- + 
- + 	if (unlikely(!timer))
- + 		return -EINVAL;
- + 
- + 	omap_dm_timer_enable(timer);
- + 	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
- + 
- + 	if (lht && hlt)
- + 		l |= OMAP_TIMER_CTRL_TCM_BOTHEDGES;
- + 	else if (lht)
- + 		l |= OMAP_TIMER_CTRL_TCM_LOWTOHIGH;
- + 	else if (hlt)
- + 		l |= OMAP_TIMER_CTRL_TCM_HIGHTOLOW;
- + 	else
- + 		l &= ~OMAP_TIMER_CTRL_TCM_BOTHEDGES;
- + 
- + 	if (cm)
- + 		l |= OMAP_TIMER_CTRL_CAPTMODE;
- + 	else
- + 		l &= ~OMAP_TIMER_CTRL_CAPTMODE;
- + 
- + 	omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
- + 
- + 	/* Save the context */
- + 	timer->context.tclr = l;
- + 	omap_dm_timer_disable(timer);
- + 	return 0;
- + }
- + EXPORT_SYMBOL_GPL(omap_dm_timer_set_capture);
- + 
- + int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
- + {
- + 	u32 l;
- + 
- + 	if (unlikely(!timer))
- + 		return -EINVAL;
- + 
- + 	omap_dm_timer_enable(timer);
- + 	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
- + 	l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
- + 	if (prescaler >= 0x00 && prescaler <= 0x07) {
- + 		l |= OMAP_TIMER_CTRL_PRE;
- + 		l |= prescaler << 2;
- + 	}
- + 	omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
- + 
- + 	/* Save the context */
- + 	timer->context.tclr = l;
- + 	omap_dm_timer_disable(timer);
- + 	return 0;
- + }
- + EXPORT_SYMBOL_GPL(omap_dm_timer_set_prescaler);
- + 
- + int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
- + 				  unsigned int value)
- + {
- + 	if (unlikely(!timer))
- + 		return -EINVAL;
- + 
- + 	omap_dm_timer_enable(timer);
- + 	__omap_dm_timer_int_enable(timer, value);
- + 
- + 	/* Save the context */
- + 	timer->context.tier = value;
- + 	timer->context.twer = value;
- + 	omap_dm_timer_disable(timer);
- + 	return 0;
- + }
- + EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable);
- + 
- + unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
- + {
- + 	unsigned int l;
- + 
- + 	if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
- + 		pr_err("%s: timer not available or enabled.\n", __func__);
- + 		return 0;
- + 	}
- + 
- + 	l = __raw_readl(timer->irq_stat);
- + 
- + 	return l;
- + }
- + EXPORT_SYMBOL_GPL(omap_dm_timer_read_status);
- + 
- + int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
- + {
- + 	if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev)))
- + 		return -EINVAL;
- + 
- + 	__omap_dm_timer_write_status(timer, value);
- + 	/* Save the context */
- + 	timer->context.tisr = value;
- + 	return 0;
- + }
- + EXPORT_SYMBOL_GPL(omap_dm_timer_write_status);
- + 
- + unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
- + {
- + 	if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
- + 		pr_err("%s: timer not iavailable or enabled.\n", __func__);
- + 		return 0;
- + 	}
- + 
- + 	return __omap_dm_timer_read_counter(timer, timer->posted);
- + }
- + EXPORT_SYMBOL_GPL(omap_dm_timer_read_counter);
- + 
- + int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
- + {
- + 	if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
- + 		pr_err("%s: timer not available or enabled.\n", __func__);
- + 		return -EINVAL;
- + 	}
- + 
- + 	omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
- + 
- + 	/* Save the context */
- + 	timer->context.tcrr = value;
- + 	return 0;
- + }
- + EXPORT_SYMBOL_GPL(omap_dm_timer_write_counter);
- + 
- + int omap_dm_timers_active(void)
- + {
- + 	struct omap_dm_timer *timer;
- + 
- + 	list_for_each_entry(timer, &omap_timer_list, node) {
- + 		if (!timer->reserved)
- + 			continue;
- + 
- + 		if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
- + 		    OMAP_TIMER_CTRL_ST) {
- + 			return 1;
- + 		}
- + 	}
- + 	return 0;
- + }
- + EXPORT_SYMBOL_GPL(omap_dm_timers_active);
- + 
- + /**
- +  * omap_dm_timer_probe - probe function called for every registered device
- +  * @pdev:	pointer to current timer platform device
- +  *
- +  * Called by driver framework at the end of device registration for all
- +  * timer devices.
- +  */
- + static int __devinit omap_dm_timer_probe(struct platform_device *pdev)
- + {
- + 	int ret;
- + 	unsigned long flags;
- + 	struct omap_dm_timer *timer;
- + 	struct resource *mem, *irq, *ioarea;
- + 	struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
- + 
- + 	if (!pdata) {
- + 		dev_err(&pdev->dev, "%s: no platform data.\n", __func__);
- + 		return -ENODEV;
- + 	}
- + 
- + 	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
- + 	if (unlikely(!irq)) {
- + 		dev_err(&pdev->dev, "%s: no IRQ resource.\n", __func__);
- + 		return -ENODEV;
- + 	}
- + 
- + 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- + 	if (unlikely(!mem)) {
- + 		dev_err(&pdev->dev, "%s: no memory resource.\n", __func__);
- + 		return -ENODEV;
- + 	}
- + 
- + 	ioarea = request_mem_region(mem->start, resource_size(mem),
- + 			pdev->name);
- + 	if (!ioarea) {
- + 		dev_err(&pdev->dev, "%s: region already claimed.\n", __func__);
- + 		return -EBUSY;
- + 	}
- + 
- + 	timer = kzalloc(sizeof(struct omap_dm_timer), GFP_KERNEL);
- + 	if (!timer) {
- + 		dev_err(&pdev->dev, "%s: no memory for omap_dm_timer.\n",
- + 			__func__);
- + 		ret = -ENOMEM;
- + 		goto err_free_ioregion;
- + 	}
- + 
- + 	timer->io_base = ioremap(mem->start, resource_size(mem));
- + 	if (!timer->io_base) {
- + 		dev_err(&pdev->dev, "%s: ioremap failed.\n", __func__);
- + 		ret = -ENOMEM;
- + 		goto err_free_mem;
- + 	}
- + 
- + 	timer->id = pdev->id;
- + 	timer->irq = irq->start;
- + 	timer->reserved = pdata->reserved;
- + 	timer->pdev = pdev;
- + 	timer->loses_context = pdata->loses_context;
- + 	timer->get_context_loss_count = pdata->get_context_loss_count;
- + 
- + 	/* Skip pm_runtime_enable for OMAP1 */
- + 	if (!pdata->needs_manual_reset) {
- + 		pm_runtime_enable(&pdev->dev);
- + 		pm_runtime_irq_safe(&pdev->dev);
- + 	}
- + 
- + 	if (!timer->reserved) {
- + 		pm_runtime_get_sync(&pdev->dev);
- + 		__omap_dm_timer_init_regs(timer);
- + 		pm_runtime_put(&pdev->dev);
- + 	}
- + 
- + 	/* add the timer element to the list */
- + 	spin_lock_irqsave(&dm_timer_lock, flags);
- + 	list_add_tail(&timer->node, &omap_timer_list);
- + 	spin_unlock_irqrestore(&dm_timer_lock, flags);
- + 
- + 	dev_dbg(&pdev->dev, "Device Probed.\n");
- + 
- + 	return 0;
- + 
- + err_free_mem:
- + 	kfree(timer);
- + 
- + err_free_ioregion:
- + 	release_mem_region(mem->start, resource_size(mem));
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * omap_dm_timer_remove - cleanup a registered timer device
- +  * @pdev:	pointer to current timer platform device
- +  *
- +  * Called by driver framework whenever a timer device is unregistered.
- +  * In addition to freeing platform resources it also deletes the timer
- +  * entry from the local list.
- +  */
- + static int __devexit omap_dm_timer_remove(struct platform_device *pdev)
- + {
- + 	struct omap_dm_timer *timer;
- + 	unsigned long flags;
- + 	int ret = -EINVAL;
- + 
- + 	spin_lock_irqsave(&dm_timer_lock, flags);
- + 	list_for_each_entry(timer, &omap_timer_list, node)
- + 		if (timer->pdev->id == pdev->id) {
- + 			list_del(&timer->node);
- + 			kfree(timer);
- + 			ret = 0;
- + 			break;
- + 		}
- + 	spin_unlock_irqrestore(&dm_timer_lock, flags);
- + 
- + 	return ret;
- + }
- + 
- + static struct platform_driver omap_dm_timer_driver = {
- + 	.probe  = omap_dm_timer_probe,
- + 	.remove = __devexit_p(omap_dm_timer_remove),
- + 	.driver = {
- + 		.name   = "omap_timer",
- + 	},
- + };
- + 
- + static int __init omap_dm_timer_driver_init(void)
- + {
- + 	return platform_driver_register(&omap_dm_timer_driver);
- + }
- + 
- + static void __exit omap_dm_timer_driver_exit(void)
- + {
- + 	platform_driver_unregister(&omap_dm_timer_driver);
- + }
- + 
- + early_platform_init("earlytimer", &omap_dm_timer_driver);
- + module_init(omap_dm_timer_driver_init);
- + module_exit(omap_dm_timer_driver_exit);
- + 
- + MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver");
- + MODULE_LICENSE("GPL");
- + MODULE_ALIAS("platform:" DRIVER_NAME);
- + MODULE_AUTHOR("Texas Instruments Inc");
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/i2c.c linux-3.2.1/arch/arm/plat-ckb/i2c.c
- *** linux-3.2.1_o/arch/arm/plat-ckb/i2c.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/i2c.c	2014-05-15 13:25:14.103862744 +0900
- ***************
- *** 0 ****
- --- 1,193 ----
- + /*
- +  * linux/arch/arm/plat-omap/i2c.c
- +  *
- +  * Helper module for board specific I2C bus registration
- +  *
- +  * Copyright (C) 2007 Nokia Corporation.
- +  *
- +  * Contact: Jarkko Nikula <jhnikula@gmail.com>
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License
- +  * version 2 as published by the Free Software Foundation.
- +  *
- +  * This program is distributed in the hope that it will be useful, but
- +  * WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- +  * General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- +  * 02110-1301 USA
- +  *
- +  */
- + 
- + #include <linux/kernel.h>
- + #include <linux/platform_device.h>
- + #include <linux/i2c.h>
- + #include <linux/i2c-omap.h>
- + #include <linux/slab.h>
- + #include <linux/err.h>
- + #include <linux/clk.h>
- + 
- + #include <mach/irqs.h>
- + #include <plat/mux.h>
- + #include <plat/i2c.h>
- + #include <plat/omap-pm.h>
- + #include <plat/omap_device.h>
- + 
- + 
- + static const char name[] = "omap_i2c";
- + 
- + #define MAX_OMAP_I2C_HWMOD_NAME_LEN	16
- + #define OMAP_I2C_MAX_CONTROLLERS 4
- + static struct omap_i2c_bus_platform_data i2c_pdata[OMAP_I2C_MAX_CONTROLLERS];
- + 
- + #define OMAP_I2C_CMDLINE_SETUP	(BIT(31))
- + 
- + static int __init omap_i2c_nr_ports(void)
- + {
- + 	return 3;
- + }
- + 
- + /*
- +  * XXX This function is a temporary compatibility wrapper - only
- +  * needed until the I2C driver can be converted to call
- +  * omap_pm_set_max_dev_wakeup_lat() and handle a return code.
- +  */
- + static void omap_pm_set_max_mpu_wakeup_lat_compat(struct device *dev, long t)
- + {
- + 	omap_pm_set_max_mpu_wakeup_lat(dev, t);
- + }
- + 
- + static inline int omap2_i2c_add_bus(int bus_id)
- + {
- + 	int l;
- + 	struct omap_hwmod *oh;
- + 	struct platform_device *pdev;
- + 	char oh_name[MAX_OMAP_I2C_HWMOD_NAME_LEN];
- + 	struct omap_i2c_bus_platform_data *pdata;
- + 	struct omap_i2c_dev_attr *dev_attr;
- + 
- + 	l = snprintf(oh_name, MAX_OMAP_I2C_HWMOD_NAME_LEN, "i2c%d", bus_id);
- + 	WARN(l >= MAX_OMAP_I2C_HWMOD_NAME_LEN,
- + 		"String buffer overflow in I2C%d device setup\n", bus_id);
- + 	oh = omap_hwmod_lookup(oh_name);
- + 	if (!oh) {
- + 			pr_err("Could not look up %s\n", oh_name);
- + 			return -EEXIST;
- + 	}
- + 
- + 	pdata = &i2c_pdata[bus_id - 1];
- + 	/*
- + 	 * pass the hwmod class's CPU-specific knowledge of I2C IP revision in
- + 	 * use, and functionality implementation flags, up to the OMAP I2C
- + 	 * driver via platform data
- + 	 */
- + 	pdata->rev = oh->class->rev;
- + 
- + 	dev_attr = (struct omap_i2c_dev_attr *)oh->dev_attr;
- + 	pdata->flags = dev_attr->flags;
- + 
- + 	/*
- + 	 * When waiting for completion of a i2c transfer, we need to
- + 	 * set a wake up latency constraint for the MPU. This is to
- + 	 * ensure quick enough wakeup from idle, when transfer
- + 	 * completes.
- + 	 * Only omap3 has support for constraints
- + 	 */
- + 	pdata->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat;
- + 
- + 	pdata->device_reset = omap_device_reset;
- + 	pdev = omap_device_build(name, bus_id, oh, pdata,
- + 			sizeof(struct omap_i2c_bus_platform_data),
- + 			NULL, 0, 0);
- + 	WARN(IS_ERR(pdev), "Could not build omap_device for %s\n", name);
- + 
- + 	return PTR_RET(pdev);
- + }
- + 
- + static int __init omap_i2c_add_bus(int bus_id)
- + {
- + 	return omap2_i2c_add_bus(bus_id);
- + }
- + 
- + /**
- +  * omap_i2c_bus_setup - Process command line options for the I2C bus speed
- +  * @str: String of options
- +  *
- +  * This function allow to override the default I2C bus speed for given I2C
- +  * bus with a command line option.
- +  *
- +  * Format: i2c_bus=bus_id,clkrate (in kHz)
- +  *
- +  * Returns 1 on success, 0 otherwise.
- +  */
- + static int __init omap_i2c_bus_setup(char *str)
- + {
- + 	int ports;
- + 	int ints[3];
- + 
- + 	ports = omap_i2c_nr_ports();
- + 	get_options(str, 3, ints);
- + 	if (ints[0] < 2 || ints[1] < 1 || ints[1] > ports)
- + 		return 0;
- + 	i2c_pdata[ints[1] - 1].clkrate = ints[2];
- + 	i2c_pdata[ints[1] - 1].clkrate |= OMAP_I2C_CMDLINE_SETUP;
- + 
- + 	return 1;
- + }
- + __setup("i2c_bus=", omap_i2c_bus_setup);
- + 
- + /*
- +  * Register busses defined in command line but that are not registered with
- +  * omap_register_i2c_bus from board initialization code.
- +  */
- + static int __init omap_register_i2c_bus_cmdline(void)
- + {
- + 	int i, err = 0;
- + 
- + 	for (i = 0; i < ARRAY_SIZE(i2c_pdata); i++)
- + 		if (i2c_pdata[i].clkrate & OMAP_I2C_CMDLINE_SETUP) {
- + 			i2c_pdata[i].clkrate &= ~OMAP_I2C_CMDLINE_SETUP;
- + 			err = omap_i2c_add_bus(i + 1);
- + 			if (err)
- + 				goto out;
- + 		}
- + 
- + out:
- + 	return err;
- + }
- + subsys_initcall(omap_register_i2c_bus_cmdline);
- + 
- + /**
- +  * omap_register_i2c_bus - register I2C bus with device descriptors
- +  * @bus_id: bus id counting from number 1
- +  * @clkrate: clock rate of the bus in kHz
- +  * @info: pointer into I2C device descriptor table or NULL
- +  * @len: number of descriptors in the table
- +  *
- +  * Returns 0 on success or an error code.
- +  */
- + int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
- + 			  struct i2c_board_info const *info,
- + 			  unsigned len)
- + {
- + 	int err;
- + 
- + 	BUG_ON(bus_id < 1 || bus_id > omap_i2c_nr_ports());
- + 
- + 	if (info) {
- + 		err = i2c_register_board_info(bus_id, info, len);
- + 		if (err)
- + 			return err;
- + 	}
- + 
- + 	if (!i2c_pdata[bus_id - 1].clkrate)
- + 		i2c_pdata[bus_id - 1].clkrate = clkrate;
- + 
- + 	i2c_pdata[bus_id - 1].clkrate &= ~OMAP_I2C_CMDLINE_SETUP;
- + 
- + 	return omap_i2c_add_bus(bus_id);
- + }
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/am33xx.h linux-3.2.1/arch/arm/plat-ckb/include/plat/am33xx.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/am33xx.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/am33xx.h	2014-05-15 13:25:14.103862744 +0900
- ***************
- *** 0 ****
- --- 1,111 ----
- + /*
- +  * This file contains the address info for various AM33XX modules.
- +  *
- +  * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #ifndef __ASM_ARCH_AM33XX_H
- + #define __ASM_ARCH_AM33XX_H
- + 
- + #define L4_SLOW_AM33XX_BASE	0x48000000
- + 
- + #define AM33XX_SCM_BASE		0x44E10000
- + #define AM33XX_CTRL_BASE	AM33XX_SCM_BASE
- + #define AM33XX_PRCM_BASE	0x44E00000
- + 
- + #define AM33XX_EMIF0_BASE	0x4C000000
- + 
- + #define AM33XX_GPIO0_BASE	0x44E07000
- + #define AM33XX_GPIO1_BASE	0x4804C000
- + #define AM33XX_GPIO2_BASE	0x481AC000
- + #define AM33XX_GPIO3_BASE	0x481AE000
- + 
- + #define AM33XX_TIMER0_BASE	0x44E05000
- + #define AM33XX_TIMER1_BASE	0x44E31000
- + #define AM33XX_TIMER2_BASE	0x48040000
- + #define AM33XX_TIMER3_BASE	0x48042000
- + #define AM33XX_TIMER4_BASE	0x48044000
- + #define AM33XX_TIMER5_BASE	0x48046000
- + #define AM33XX_TIMER6_BASE	0x48048000
- + #define AM33XX_TIMER7_BASE	0x4804A000
- + 
- + #define AM33XX_WDT1_BASE	0x44E35000
- + 
- + #define AM33XX_TSC_BASE		0x44E0D000
- + #define AM33XX_RTC_BASE		0x44E3E000
- + 
- + #define AM33XX_SR0_BASE         0x44E37000
- + #define AM33XX_SR1_BASE         0x44E39000
- + 
- + #define AM33XX_ASP0_BASE	0x48038000
- + #define AM33XX_ASP1_BASE	0x4803C000
- + 
- + #define AM33XX_MAILBOX0_BASE	0x480C8000
- + 
- + #define AM33XX_MMC0_BASE	0x48060100
- + #define AM33XX_MMC1_BASE	0x481D8100
- + #define AM33XX_MMC2_BASE	0x47810100
- + 
- + #define AM33XX_I2C0_BASE	0x44E0B000
- + #define AM33XX_I2C1_BASE	0x4802A000
- + #define AM33XX_I2C2_BASE	0x4819C000
- + 
- + #define AM33XX_SPI0_BASE	0x48030000
- + #define AM33XX_SPI1_BASE	0x481A0000
- + 
- + #define AM33XX_USBSS_BASE	0x47400000
- + #define AM33XX_USB0_BASE	0x47401000
- + #define AM33XX_USB1_BASE	0x47401800
- + 
- + #define AM33XX_ELM_BASE		0x48080000
- + 
- + /* Base address for crypto modules */
- + #define AM33XX_SHA1MD5_S_BASE	0x53000000
- + #define AM33XX_SHA1MD5_P_BASE	0x53100000
- + 
- + #define	AM33XX_AES0_S_BASE	0x53400000
- + #define	AM33XX_AES0_P_BASE	0x53500000
- + #define	AM33XX_AES1_S_BASE	0x53600000
- + #define	AM33XX_AES1_P_BASE	0x53700000
- + 
- + #define	AM33XX_RNG_BASE		0x48310000
- + 
- + #define AM33XX_ASP0_BASE	0x48038000
- + #define AM33XX_ASP1_BASE	0x4803C000
- + 
- + #define AM33XX_CPSW_BASE       0x4A100000
- + #define AM33XX_CPSW_MDIO_BASE  0x4A101000
- + #define AM33XX_CPSW_SS_BASE    0x4A101200
- + 
- + #define AM33XX_ICSS_BASE	0x4A300000
- + #define AM33XX_ICSS_LEN		0x3FFFF
- + 
- + #define AM33XX_EPWMSS0_BASE	0x48300000
- + #define AM33XX_EPWMSS1_BASE	0x48302000
- + #define AM33XX_EPWMSS2_BASE	0x48304000
- + 
- + /*
- +  * ----------------------------------------------------------------------------
- +  * CPSW
- +  * ----------------------------------------------------------------------------
- +  */
- + #ifndef __ASSEMBLER__
- + enum am33xx_cpsw_mac_mode {
- + 	AM33XX_CPSW_MODE_MII,
- + 	AM33XX_CPSW_MODE_RMII,
- + 	AM33XX_CPSW_MODE_RGMII,
- + };
- + int am33xx_cpsw_init(enum am33xx_cpsw_mac_mode mode, unsigned char *mac_id, void (*save_mac_addr) (char *));
- + #endif
- + 
- + 
- + #endif /* __ASM_ARCH_AM33XX_H */
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/board.h linux-3.2.1/arch/arm/plat-ckb/include/plat/board.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/board.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/board.h	2014-05-15 13:25:14.107920501 +0900
- ***************
- *** 0 ****
- --- 1,176 ----
- + /*
- +  *  arch/arm/plat-omap/include/mach/board.h
- +  *
- +  *  Information structures for board-specific data
- +  *
- +  *  Copyright (C) 2004	Nokia Corporation
- +  *  Written by Juha Yrjölä <juha.yrjola@nokia.com>
- +  */
- + 
- + #ifndef _OMAP_BOARD_H
- + #define _OMAP_BOARD_H
- + 
- + #include <linux/types.h>
- + 
- + #include <plat/gpio-switch.h>
- + 
- + /*
- +  * OMAP35x EVM revision
- +  * Run time detection of EVM revision is done by reading Ethernet
- +  * PHY ID -
- +  *	GEN_1	= 0x01150000
- +  *	GEN_2	= 0x92200000
- +  */
- + enum {
- + 	OMAP3EVM_BOARD_GEN_1 = 0,	/* EVM Rev between  A - D */
- + 	OMAP3EVM_BOARD_GEN_2,		/* EVM Rev >= Rev E */
- + };
- + 
- + /* Different peripheral ids */
- + #define OMAP_TAG_CLOCK		0x4f01
- + #define OMAP_TAG_LCD		0x4f05
- + #define OMAP_TAG_GPIO_SWITCH	0x4f06
- + #define OMAP_TAG_FBMEM		0x4f08
- + #define OMAP_TAG_STI_CONSOLE	0x4f09
- + #define OMAP_TAG_CAMERA_SENSOR	0x4f0a
- + 
- + #define OMAP_TAG_BOOT_REASON    0x4f80
- + #define OMAP_TAG_FLASH_PART	0x4f81
- + #define OMAP_TAG_VERSION_STR	0x4f82
- + 
- + struct omap_clock_config {
- + 	/* 0 for 12 MHz, 1 for 13 MHz and 2 for 19.2 MHz */
- + 	u8 system_clock_type;
- + };
- + 
- + struct omap_serial_console_config {
- + 	u8 console_uart;
- + 	u32 console_speed;
- + };
- + 
- + struct omap_sti_console_config {
- + 	unsigned enable:1;
- + 	u8 channel;
- + };
- + 
- + struct omap_camera_sensor_config {
- + 	u16 reset_gpio;
- + 	int (*power_on)(void * data);
- + 	int (*power_off)(void * data);
- + };
- + 
- + struct omap_usb_config {
- + 	/* Configure drivers according to the connectors on your board:
- + 	 *  - "A" connector (rectagular)
- + 	 *	... for host/OHCI use, set "register_host".
- + 	 *  - "B" connector (squarish) or "Mini-B"
- + 	 *	... for device/gadget use, set "register_dev".
- + 	 *  - "Mini-AB" connector (very similar to Mini-B)
- + 	 *	... for OTG use as device OR host, initialize "otg"
- + 	 */
- + 	unsigned	register_host:1;
- + 	unsigned	register_dev:1;
- + 	u8		otg;	/* port number, 1-based:  usb1 == 2 */
- + 
- + 	u8		hmc_mode;
- + 
- + 	/* implicitly true if otg:  host supports remote wakeup? */
- + 	u8		rwc;
- + 
- + 	/* signaling pins used to talk to transceiver on usbN:
- + 	 *  0 == usbN unused
- + 	 *  2 == usb0-only, using internal transceiver
- + 	 *  3 == 3 wire bidirectional
- + 	 *  4 == 4 wire bidirectional
- + 	 *  6 == 6 wire unidirectional (or TLL)
- + 	 */
- + 	u8		pins[3];
- + 
- + 	struct platform_device *udc_device;
- + 	struct platform_device *ohci_device;
- + 	struct platform_device *otg_device;
- + 
- + 	u32 (*usb0_init)(unsigned nwires, unsigned is_device);
- + 	u32 (*usb1_init)(unsigned nwires);
- + 	u32 (*usb2_init)(unsigned nwires, unsigned alt_pingroup);
- + };
- + 
- + struct omap_lcd_config {
- + 	char panel_name[16];
- + 	char ctrl_name[16];
- + 	s16  nreset_gpio;
- + 	u8   data_lines;
- + };
- + 
- + struct device;
- + struct fb_info;
- + struct omap_backlight_config {
- + 	int default_intensity;
- + 	int (*set_power)(struct device *dev, int state);
- + };
- + 
- + struct omap_fbmem_config {
- + 	u32 start;
- + 	u32 size;
- + };
- + 
- + struct omap_pwm_led_platform_data {
- + 	const char *name;
- + 	int intensity_timer;
- + 	int blink_timer;
- + 	void (*set_power)(struct omap_pwm_led_platform_data *self, int on_off);
- + };
- + 
- + struct omap_uart_config {
- + 	/* Bit field of UARTs present; bit 0 --> UART1 */
- + 	unsigned int enabled_uarts;
- + };
- + 
- + 
- + struct omap_flash_part_config {
- + 	char part_table[0];
- + };
- + 
- + struct omap_boot_reason_config {
- + 	char reason_str[12];
- + };
- + 
- + struct omap_version_config {
- + 	char component[12];
- + 	char version[12];
- + };
- + 
- + struct omap_board_config_entry {
- + 	u16 tag;
- + 	u16 len;
- + 	u8  data[0];
- + };
- + 
- + struct omap_board_config_kernel {
- + 	u16 tag;
- + 	const void *data;
- + };
- + 
- + extern const void *__init __omap_get_config(u16 tag, size_t len, int nr);
- + 
- + #define omap_get_config(tag, type) \
- + 	((const type *) __omap_get_config((tag), sizeof(type), 0))
- + #define omap_get_nr_config(tag, type, nr) \
- + 	((const type *) __omap_get_config((tag), sizeof(type), (nr)))
- + 
- + extern const void *__init omap_get_var_config(u16 tag, size_t *len);
- + 
- + extern struct omap_board_config_kernel *omap_board_config;
- + extern int omap_board_config_size;
- + 
- + 
- + /* for TI reference platforms sharing the same debug card */
- + extern int debug_card_init(u32 addr, unsigned gpio);
- + 
- + /* OMAP3EVM revision */
- + #if defined(CONFIG_MACH_OMAP3EVM)
- + u8 get_omap3_evm_rev(void);
- + #else
- + #define get_omap3_evm_rev() (-EINVAL)
- + #endif
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/clkdev_omap.h linux-3.2.1/arch/arm/plat-ckb/include/plat/clkdev_omap.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/clkdev_omap.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/clkdev_omap.h	2014-05-15 13:25:14.107920501 +0900
- ***************
- *** 0 ****
- --- 1,53 ----
- + /*
- +  * clkdev <-> OMAP integration
- +  *
- +  * Russell King <linux@arm.linux.org.uk>
- +  *
- +  */
- + 
- + #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H
- + #define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H
- + 
- + #include <linux/clkdev.h>
- + 
- + struct omap_clk {
- + 	u16				cpu;
- + 	struct clk_lookup		lk;
- + };
- + 
- + #define CLK(dev, con, ck, cp) 		\
- + 	{				\
- + 		 .cpu = cp,		\
- + 		.lk = {			\
- + 			.dev_id = dev,	\
- + 			.con_id = con,	\
- + 			.clk = ck,	\
- + 		},			\
- + 	}
- + 
- + /* Platform flags for the clkdev-OMAP integration code */
- + #define CK_310		(1 << 0)
- + #define CK_7XX		(1 << 1)	/* 7xx, 850 */
- + #define CK_1510		(1 << 2)
- + #define CK_16XX		(1 << 3)	/* 16xx, 17xx, 5912 */
- + #define CK_242X		(1 << 4)
- + #define CK_243X		(1 << 5)	/* 243x, 253x */
- + #define CK_3430ES1	(1 << 6)	/* 34xxES1 only */
- + #define CK_3430ES2PLUS	(1 << 7)	/* 34xxES2, ES3, non-Sitara 35xx only */
- + #define CK_3505		(1 << 8)
- + #define CK_3517		(1 << 9)
- + #define CK_36XX		(1 << 10)	/* 36xx/37xx-specific clocks */
- + #define CK_443X		(1 << 11)
- + #define CK_TI816X	(1 << 12)
- + #define CK_446X		(1 << 13)
- + #define CK_AM33XX	(1 << 14)	/* AM33xx specific clocks */
- + #define CK_1710		(1 << 15)	/* 1710 extra for rate selection */
- + 
- + 
- + #define CK_34XX		(CK_3430ES1 | CK_3430ES2PLUS)
- + #define CK_AM35XX	(CK_3505 | CK_3517)	/* all Sitara AM35xx */
- + #define CK_3XXX		(CK_34XX | CK_AM35XX | CK_36XX)
- + 
- + 
- + #endif
- + 
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/clock.h linux-3.2.1/arch/arm/plat-ckb/include/plat/clock.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/clock.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/clock.h	2014-05-15 13:25:14.110666144 +0900
- ***************
- *** 0 ****
- --- 1,306 ----
- + /*
- +  * OMAP clock: data structure definitions, function prototypes, shared macros
- +  *
- +  * Copyright (C) 2004-2005, 2008-2010 Nokia Corporation
- +  * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
- +  * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #ifndef __ARCH_ARM_OMAP_CLOCK_H
- + #define __ARCH_ARM_OMAP_CLOCK_H
- + 
- + #include <linux/list.h>
- + 
- + struct module;
- + struct clk;
- + struct clockdomain;
- + 
- + /**
- +  * struct clkops - some clock function pointers
- +  * @enable: fn ptr that enables the current clock in hardware
- +  * @disable: fn ptr that enables the current clock in hardware
- +  * @find_idlest: function returning the IDLEST register for the clock's IP blk
- +  * @find_companion: function returning the "companion" clk reg for the clock
- +  * @allow_idle: fn ptr that enables autoidle for the current clock in hardware
- +  * @deny_idle: fn ptr that disables autoidle for the current clock in hardware
- +  *
- +  * A "companion" clk is an accompanying clock to the one being queried
- +  * that must be enabled for the IP module connected to the clock to
- +  * become accessible by the hardware.  Neither @find_idlest nor
- +  * @find_companion should be needed; that information is IP
- +  * block-specific; the hwmod code has been created to handle this, but
- +  * until hwmod data is ready and drivers have been converted to use PM
- +  * runtime calls in place of clk_enable()/clk_disable(), @find_idlest and
- +  * @find_companion must, unfortunately, remain.
- +  */
- + struct clkops {
- + 	int			(*enable)(struct clk *);
- + 	void			(*disable)(struct clk *);
- + 	void			(*find_idlest)(struct clk *, void __iomem **,
- + 					       u8 *, u8 *);
- + 	void			(*find_companion)(struct clk *, void __iomem **,
- + 						  u8 *);
- + 	void			(*allow_idle)(struct clk *);
- + 	void			(*deny_idle)(struct clk *);
- + };
- + 
- + 
- + /* struct clksel_rate.flags possibilities */
- + #define RATE_IN_242X		(1 << 0)
- + #define RATE_IN_243X		(1 << 1)
- + #define RATE_IN_3430ES1		(1 << 2)	/* 3430ES1 rates only */
- + #define RATE_IN_3430ES2PLUS	(1 << 3)	/* 3430 ES >= 2 rates only */
- + #define RATE_IN_36XX		(1 << 4)
- + #define RATE_IN_4430		(1 << 5)
- + #define RATE_IN_TI816X		(1 << 6)
- + #define RATE_IN_4460		(1 << 7)
- + #define RATE_IN_AM33XX		(1 << 8)
- + #define RATE_IN_TI814X		(1 << 9)
- + 
- + #define RATE_IN_24XX		(RATE_IN_242X | RATE_IN_243X)
- + #define RATE_IN_34XX		(RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
- + #define RATE_IN_3XXX		(RATE_IN_34XX | RATE_IN_36XX)
- + #define RATE_IN_44XX		(RATE_IN_4430 | RATE_IN_4460)
- + 
- + /* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
- + #define RATE_IN_3430ES2PLUS_36XX	(RATE_IN_3430ES2PLUS | RATE_IN_36XX)
- + 
- + 
- + /**
- +  * struct clksel_rate - register bitfield values corresponding to clk divisors
- +  * @val: register bitfield value (shifted to bit 0)
- +  * @div: clock divisor corresponding to @val
- +  * @flags: (see "struct clksel_rate.flags possibilities" above)
- +  *
- +  * @val should match the value of a read from struct clk.clksel_reg
- +  * AND'ed with struct clk.clksel_mask, shifted right to bit 0.
- +  *
- +  * @div is the divisor that should be applied to the parent clock's rate
- +  * to produce the current clock's rate.
- +  */
- + struct clksel_rate {
- + 	u32			val;
- + 	u8			div;
- + 	u16			flags;
- + };
- + 
- + /**
- +  * struct clksel - available parent clocks, and a pointer to their divisors
- +  * @parent: struct clk * to a possible parent clock
- +  * @rates: available divisors for this parent clock
- +  *
- +  * A struct clksel is always associated with one or more struct clks
- +  * and one or more struct clksel_rates.
- +  */
- + struct clksel {
- + 	struct clk		 *parent;
- + 	const struct clksel_rate *rates;
- + };
- + 
- + /**
- +  * struct dpll_data - DPLL registers and integration data
- +  * @mult_div1_reg: register containing the DPLL M and N bitfields
- +  * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
- +  * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
- +  * @clk_bypass: struct clk pointer to the clock's bypass clock input
- +  * @clk_ref: struct clk pointer to the clock's reference clock input
- +  * @control_reg: register containing the DPLL mode bitfield
- +  * @enable_mask: mask of the DPLL mode bitfield in @control_reg
- +  * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
- +  * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
- +  * @max_multiplier: maximum valid non-bypass multiplier value (actual)
- +  * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
- +  * @min_divider: minimum valid non-bypass divider value (actual)
- +  * @max_divider: maximum valid non-bypass divider value (actual)
- +  * @modes: possible values of @enable_mask
- +  * @autoidle_reg: register containing the DPLL autoidle mode bitfield
- +  * @idlest_reg: register containing the DPLL idle status bitfield
- +  * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
- +  * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
- +  * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
- +  * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
- +  * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
- +  * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
- +  * @flags: DPLL type/features (see below)
- +  *
- +  * Possible values for @flags:
- +  * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
- +  *
- +  * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
- +  *
- +  * XXX Some DPLLs have multiple bypass inputs, so it's not technically
- +  * correct to only have one @clk_bypass pointer.
- +  *
- +  * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
- +  * @last_rounded_n) should be separated from the runtime-fixed fields
- +  * and placed into a different structure, so that the runtime-fixed data
- +  * can be placed into read-only space.
- +  */
- + struct dpll_data {
- + 	void __iomem		*mult_div1_reg;
- + 	u32			mult_mask;
- + 	u32			div1_mask;
- + 	struct clk		*clk_bypass;
- + 	struct clk		*clk_ref;
- + 	void __iomem		*control_reg;
- + 	u32			enable_mask;
- + 	unsigned long		last_rounded_rate;
- + 	u16			last_rounded_m;
- + 	u16			max_multiplier;
- + 	u8			last_rounded_n;
- + 	u8			min_divider;
- + 	u16			max_divider;
- + 	u8			modes;
- + 	void __iomem		*autoidle_reg;
- + 	void __iomem		*idlest_reg;
- + 	u32			autoidle_mask;
- + 	u32			freqsel_mask;
- + 	u32			idlest_mask;
- + 	u32			dco_mask;
- + 	u32			sddiv_mask;
- + 	u8			auto_recal_bit;
- + 	u8			recal_en_bit;
- + 	u8			recal_st_bit;
- + 	u8			flags;
- + };
- + 
- + /*
- +  * struct clk.flags possibilities
- +  *
- +  * XXX document the rest of the clock flags here
- +  *
- +  * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
- +  *     bits share the same register.  This flag allows the
- +  *     omap4_dpllmx*() code to determine which GATE_CTRL bit field
- +  *     should be used.  This is a temporary solution - a better approach
- +  *     would be to associate clock type-specific data with the clock,
- +  *     similar to the struct dpll_data approach.
- +  */
- + #define ENABLE_REG_32BIT	(1 << 0)	/* Use 32-bit access */
- + #define CLOCK_IDLE_CONTROL	(1 << 1)
- + #define CLOCK_NO_IDLE_PARENT	(1 << 2)
- + #define ENABLE_ON_INIT		(1 << 3)	/* Enable upon framework init */
- + #define INVERT_ENABLE		(1 << 4)	/* 0 enables, 1 disables */
- + #define CLOCK_CLKOUTX2		(1 << 5)
- + 
- + /**
- +  * struct clk - OMAP struct clk
- +  * @node: list_head connecting this clock into the full clock list
- +  * @ops: struct clkops * for this clock
- +  * @name: the name of the clock in the hardware (used in hwmod data and debug)
- +  * @parent: pointer to this clock's parent struct clk
- +  * @children: list_head connecting to the child clks' @sibling list_heads
- +  * @sibling: list_head connecting this clk to its parent clk's @children
- +  * @rate: current clock rate
- +  * @enable_reg: register to write to enable the clock (see @enable_bit)
- +  * @recalc: fn ptr that returns the clock's current rate
- +  * @set_rate: fn ptr that can change the clock's current rate
- +  * @round_rate: fn ptr that can round the clock's current rate
- +  * @init: fn ptr to do clock-specific initialization
- +  * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
- +  * @usecount: number of users that have requested this clock to be enabled
- +  * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div
- +  * @flags: see "struct clk.flags possibilities" above
- +  * @clksel_reg: for clksel clks, register va containing src/divisor select
- +  * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
- +  * @clksel: for clksel clks, pointer to struct clksel for this clock
- +  * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
- +  * @clkdm_name: clockdomain name that this clock is contained in
- +  * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
- +  * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
- +  * @src_offset: bitshift for source selection bitfield (OMAP1 only)
- +  *
- +  * XXX @rate_offset, @src_offset should probably be removed and OMAP1
- +  * clock code converted to use clksel.
- +  *
- +  * XXX @usecount is poorly named.  It should be "enable_count" or
- +  * something similar.  "users" in the description refers to kernel
- +  * code (core code or drivers) that have called clk_enable() and not
- +  * yet called clk_disable(); the usecount of parent clocks is also
- +  * incremented by the clock code when clk_enable() is called on child
- +  * clocks and decremented by the clock code when clk_disable() is
- +  * called on child clocks.
- +  *
- +  * XXX @clkdm, @usecount, @children, @sibling should be marked for
- +  * internal use only.
- +  *
- +  * @children and @sibling are used to optimize parent-to-child clock
- +  * tree traversals.  (child-to-parent traversals use @parent.)
- +  *
- +  * XXX The notion of the clock's current rate probably needs to be
- +  * separated from the clock's target rate.
- +  */
- + struct clk {
- + 	struct list_head	node;
- + 	const struct clkops	*ops;
- + 	const char		*name;
- + 	struct clk		*parent;
- + 	struct list_head	children;
- + 	struct list_head	sibling;	/* node for children */
- + 	unsigned long		rate;
- + 	void __iomem		*enable_reg;
- + 	unsigned long		(*recalc)(struct clk *);
- + 	int			(*set_rate)(struct clk *, unsigned long);
- + 	long			(*round_rate)(struct clk *, unsigned long);
- + 	void			(*init)(struct clk *);
- + 	u8			enable_bit;
- + 	s8			usecount;
- + 	u8			fixed_div;
- + 	u8			flags;
- + 	void __iomem		*clksel_reg;
- + 	u32			clksel_mask;
- + 	const struct clksel	*clksel;
- + 	struct dpll_data	*dpll_data;
- + 	const char		*clkdm_name;
- + 	struct clockdomain	*clkdm;
- + #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
- + 	struct dentry		*dent;	/* For visible tree hierarchy */
- + #endif
- + };
- + 
- + struct cpufreq_frequency_table;
- + 
- + struct clk_functions {
- + 	int		(*clk_enable)(struct clk *clk);
- + 	void		(*clk_disable)(struct clk *clk);
- + 	long		(*clk_round_rate)(struct clk *clk, unsigned long rate);
- + 	int		(*clk_set_rate)(struct clk *clk, unsigned long rate);
- + 	int		(*clk_set_parent)(struct clk *clk, struct clk *parent);
- + 	void		(*clk_allow_idle)(struct clk *clk);
- + 	void		(*clk_deny_idle)(struct clk *clk);
- + 	void		(*clk_disable_unused)(struct clk *clk);
- + #ifdef CONFIG_CPU_FREQ
- + 	void		(*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
- + 	void		(*clk_exit_cpufreq_table)(struct cpufreq_frequency_table **);
- + #endif
- + };
- + 
- + extern int mpurate;
- + 
- + extern int clk_init(struct clk_functions *custom_clocks);
- + extern void clk_preinit(struct clk *clk);
- + extern int clk_register(struct clk *clk);
- + extern void clk_reparent(struct clk *child, struct clk *parent);
- + extern void clk_unregister(struct clk *clk);
- + extern void propagate_rate(struct clk *clk);
- + extern void recalculate_root_clocks(void);
- + extern unsigned long followparent_recalc(struct clk *clk);
- + extern void clk_enable_init_clocks(void);
- + unsigned long omap_fixed_divisor_recalc(struct clk *clk);
- + #ifdef CONFIG_CPU_FREQ
- + extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
- + extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
- + #endif
- + extern struct clk *omap_clk_get_by_name(const char *name);
- + extern int omap_clk_enable_autoidle_all(void);
- + extern int omap_clk_disable_autoidle_all(void);
- + 
- + extern const struct clkops clkops_null;
- + 
- + extern struct clk dummy_ck;
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/common.h linux-3.2.1/arch/arm/plat-ckb/include/plat/common.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/common.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/common.h	2014-05-15 13:25:14.110666144 +0900
- ***************
- *** 0 ****
- --- 1,41 ----
- + /*
- +  * arch/arm/plat-omap/include/mach/common.h
- +  *
- +  * Header for code common to all OMAP machines.
- +  *
- +  * This program is free software; you can redistribute it and/or modify it
- +  * under the terms of the GNU General Public License as published by the
- +  * Free Software Foundation; either version 2 of the License, or (at your
- +  * option) any later version.
- +  *
- +  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- +  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- +  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- +  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- +  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- +  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- +  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- +  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- +  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- +  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- +  *
- +  * You should have received a copy of the  GNU General Public License along
- +  * with this program; if not, write  to the Free Software Foundation, Inc.,
- +  * 675 Mass Ave, Cambridge, MA 02139, USA.
- +  */
- + 
- + #ifndef __ARCH_ARM_MACH_OMAP_COMMON_H
- + #define __ARCH_ARM_MACH_OMAP_COMMON_H
- + 
- + #include <plat/i2c.h>
- + #include <plat/omap_hwmod.h>
- + 
- + extern int __init omap_init_clocksource_32k(void);
- + extern unsigned long long notrace omap_32k_sched_clock(void);
- + 
- + extern void omap_reserve(void);
- + extern int omap_dss_reset(struct omap_hwmod *);
- + 
- + void omap_sram_init(void);
- + 
- + #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/config_pwm.h linux-3.2.1/arch/arm/plat-ckb/include/plat/config_pwm.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/config_pwm.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/config_pwm.h	2014-05-15 13:25:14.110666144 +0900
- ***************
- *** 0 ****
- --- 1,26 ----
- + #ifndef __CONFIG_CONFIG_PWM
- + #define __CONFIG_CONFIG_PWM
- + 
- + #define AM33XX_CONFIG_BASE      (0x0)
- + #define AM33XX_CONFIG_SIZE      (AM33XX_CONFIG_BASE + 0x10)
- + #define AM33XX_ECAP_BASE        (0x0100)
- + #define AM33XX_ECAP_SIZE        (AM33XX_ECAP_BASE + 0x080)
- + #define AM33XX_EQEP_BASE        (0x0180)
- + #define AM33XX_EQeP_SIZE        (AM33XX_EQEP_BASE + 0x080)
- + #define AM33XX_EPWM_BASE        (0x0200)
- + #define AM33XX_EPWM_SIZE        (AM33XX_EPWM_BASE + 0x0100)
- + 
- + #define PWMSS_CLKCONFIG          (0x08)
- + #define ECAP_CLK_EN              (0x0)
- + #define ECAP_CLK_STOP_REQ        (0x1)
- + #define EQEP_CLK_EN              (0x4)
- + #define EQEP_CLK_STOP_REQ        (0x5)
- + #define EPWM_CLK_EN              (0x8)
- + #define EPWM_CLK_STOP_REQ        (0x9)
- + 
- + #define SET                      (1)
- + #define CLEAR                    (0)
- + 
- + #define PWM_CON_ID_STRING_LENGTH (12)
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/cpu.h linux-3.2.1/arch/arm/plat-ckb/include/plat/cpu.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/cpu.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/cpu.h	2014-05-15 13:25:14.116270792 +0900
- ***************
- *** 0 ****
- --- 1,405 ----
- + /*
- +  * arch/arm/plat-omap/include/mach/cpu.h
- +  *
- +  * OMAP cpu type detection
- +  *
- +  * Copyright (C) 2004, 2008 Nokia Corporation
- +  *
- +  * Copyright (C) 2009-11 Texas Instruments.
- +  *
- +  * Written by Tony Lindgren <tony.lindgren@nokia.com>
- +  *
- +  * Added OMAP4 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; either version 2 of the License, or
- +  * (at your option) any later version.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- +  *
- +  */
- + 
- + #ifndef __ASM_ARCH_OMAP_CPU_H
- + #define __ASM_ARCH_OMAP_CPU_H
- + 
- + #include <linux/bitops.h>
- + #include <plat/multi.h>
- + 
- + /*
- +  * Omap device type i.e. EMU/HS/TST/GP/BAD
- +  */
- + #define OMAP2_DEVICE_TYPE_TEST		0
- + #define OMAP2_DEVICE_TYPE_EMU		1
- + #define OMAP2_DEVICE_TYPE_SEC		2
- + #define OMAP2_DEVICE_TYPE_GP		3
- + #define OMAP2_DEVICE_TYPE_BAD		4
- + 
- + int omap_type(void);
- + 
- + /*
- +  * omap_rev bits:
- +  * CPU id bits	(0730, 1510, 1710, 2422...)	[31:16]
- +  * CPU revision	(See _REV_ defined in cpu.h)	[15:08]
- +  * CPU class bits (15xx, 16xx, 24xx, 34xx...)	[07:00]
- +  */
- + unsigned int omap_rev(void);
- + 
- + /*
- +  * Get the CPU revision for OMAP devices
- +  */
- + #define GET_OMAP_REVISION()	((omap_rev() >> 8) & 0xff)
- + 
- + /*
- +  * Macros to group OMAP into cpu classes.
- +  * These can be used in most places.
- +  * cpu_is_omap7xx():	True for OMAP730, OMAP850
- +  * cpu_is_omap15xx():	True for OMAP1510, OMAP5910 and OMAP310
- +  * cpu_is_omap16xx():	True for OMAP1610, OMAP5912 and OMAP1710
- +  * cpu_is_omap24xx():	True for OMAP2420, OMAP2422, OMAP2423, OMAP2430
- +  * cpu_is_omap242x():	True for OMAP2420, OMAP2422, OMAP2423
- +  * cpu_is_omap243x():	True for OMAP2430
- +  * cpu_is_omap343x():	True for OMAP3430
- +  * cpu_is_omap443x():	True for OMAP4430
- +  * cpu_is_omap446x():	True for OMAP4460
- +  * cpu_is_omap447x():	True for OMAP4470
- +  */
- + #define GET_OMAP_CLASS	(omap_rev() & 0xff)
- + 
- + #define IS_OMAP_CLASS(class, id)			\
- + static inline int is_omap ##class (void)		\
- + {							\
- + 	return (GET_OMAP_CLASS == (id)) ? 1 : 0;	\
- + }
- + 
- + #define GET_AM_CLASS	((omap_rev() >> 24) & 0xff)
- + 
- + #define IS_AM_CLASS(class, id)				\
- + static inline int is_am ##class (void)			\
- + {							\
- + 	return (GET_AM_CLASS == (id)) ? 1 : 0;		\
- + }
- + 
- + #define GET_TI_CLASS	((omap_rev() >> 24) & 0xff)
- + 
- + #define IS_TI_CLASS(class, id)			\
- + static inline int is_ti ##class (void)		\
- + {							\
- + 	return (GET_TI_CLASS == (id)) ? 1 : 0;	\
- + }
- + 
- + #define GET_OMAP_SUBCLASS	((omap_rev() >> 20) & 0x0fff)
- + 
- + #define IS_OMAP_SUBCLASS(subclass, id)			\
- + static inline int is_omap ##subclass (void)		\
- + {							\
- + 	return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;	\
- + }
- + 
- + #define IS_TI_SUBCLASS(subclass, id)			\
- + static inline int is_ti ##subclass (void)		\
- + {							\
- + 	return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;	\
- + }
- + 
- + #define IS_AM_SUBCLASS(subclass, id)			\
- + static inline int is_am ##subclass (void)		\
- + {							\
- + 	return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;	\
- + }
- + 
- + IS_OMAP_CLASS(7xx, 0x07)
- + IS_OMAP_CLASS(15xx, 0x15)
- + IS_OMAP_CLASS(16xx, 0x16)
- + IS_OMAP_CLASS(24xx, 0x24)
- + IS_OMAP_CLASS(34xx, 0x34)
- + IS_OMAP_CLASS(44xx, 0x44)
- + IS_AM_CLASS(33xx, 0x33)
- + 
- + IS_TI_CLASS(81xx, 0x81)
- + 
- + IS_OMAP_SUBCLASS(242x, 0x242)
- + IS_OMAP_SUBCLASS(243x, 0x243)
- + IS_OMAP_SUBCLASS(343x, 0x343)
- + IS_OMAP_SUBCLASS(363x, 0x363)
- + IS_OMAP_SUBCLASS(443x, 0x443)
- + IS_OMAP_SUBCLASS(446x, 0x446)
- + IS_OMAP_SUBCLASS(447x, 0x447)
- + 
- + IS_TI_SUBCLASS(816x, 0x816)
- + IS_TI_SUBCLASS(814x, 0x814)
- + IS_AM_SUBCLASS(335x, 0x335)
- + 
- + #define cpu_is_omap7xx()		0
- + #define cpu_is_omap15xx()		0
- + #define cpu_is_omap16xx()		0
- + #define cpu_is_omap24xx()		0
- + #define cpu_is_omap242x()		0
- + #define cpu_is_omap243x()		0
- + #define cpu_is_omap34xx()		0
- + #define cpu_is_omap343x()		0
- + #define cpu_is_ti81xx()			0
- + #define cpu_is_ti816x()			0
- + #define cpu_is_ti814x()			0
- + #define cpu_is_am33xx()			0
- + #define cpu_is_am335x()			0
- + #define cpu_is_omap44xx()		0
- + #define cpu_is_omap443x()		0
- + #define cpu_is_omap446x()		0
- + #define cpu_is_omap447x()		0
- + 
- + #  undef  cpu_is_omap34xx
- + #  define cpu_is_omap34xx()		1
- + 
- + /*
- +  * Macros to detect individual cpu types.
- +  * These are only rarely needed.
- +  * cpu_is_omap330():	True for OMAP330
- +  * cpu_is_omap730():	True for OMAP730
- +  * cpu_is_omap850():	True for OMAP850
- +  * cpu_is_omap1510():	True for OMAP1510
- +  * cpu_is_omap1610():	True for OMAP1610
- +  * cpu_is_omap1611():	True for OMAP1611
- +  * cpu_is_omap5912():	True for OMAP5912
- +  * cpu_is_omap1621():	True for OMAP1621
- +  * cpu_is_omap1710():	True for OMAP1710
- +  * cpu_is_omap2420():	True for OMAP2420
- +  * cpu_is_omap2422():	True for OMAP2422
- +  * cpu_is_omap2423():	True for OMAP2423
- +  * cpu_is_omap2430():	True for OMAP2430
- +  * cpu_is_omap3430():	True for OMAP3430
- +  * cpu_is_omap4430():	True for OMAP4430
- +  * cpu_is_omap3505():	True for OMAP3505
- +  * cpu_is_omap3517():	True for OMAP3517
- +  */
- + #define GET_OMAP_TYPE	((omap_rev() >> 16) & 0xffff)
- + 
- + #define IS_OMAP_TYPE(type, id)				\
- + static inline int is_omap ##type (void)			\
- + {							\
- + 	return (GET_OMAP_TYPE == (id)) ? 1 : 0;		\
- + }
- + 
- + IS_OMAP_TYPE(310, 0x0310)
- + IS_OMAP_TYPE(730, 0x0730)
- + IS_OMAP_TYPE(850, 0x0850)
- + IS_OMAP_TYPE(1510, 0x1510)
- + IS_OMAP_TYPE(1610, 0x1610)
- + IS_OMAP_TYPE(1611, 0x1611)
- + IS_OMAP_TYPE(5912, 0x1611)
- + IS_OMAP_TYPE(1621, 0x1621)
- + IS_OMAP_TYPE(1710, 0x1710)
- + IS_OMAP_TYPE(2420, 0x2420)
- + IS_OMAP_TYPE(2422, 0x2422)
- + IS_OMAP_TYPE(2423, 0x2423)
- + IS_OMAP_TYPE(2430, 0x2430)
- + IS_OMAP_TYPE(3430, 0x3430)
- + IS_OMAP_TYPE(3505, 0x3517)
- + IS_OMAP_TYPE(3517, 0x3517)
- + 
- + #define cpu_is_omap310()		0
- + #define cpu_is_omap730()		0
- + #define cpu_is_omap850()		0
- + #define cpu_is_omap1510()		0
- + #define cpu_is_omap1610()		0
- + #define cpu_is_omap5912()		0
- + #define cpu_is_omap1611()		0
- + #define cpu_is_omap1621()		0
- + #define cpu_is_omap1710()		0
- + #define cpu_is_omap2420()		0
- + #define cpu_is_omap2422()		0
- + #define cpu_is_omap2423()		0
- + #define cpu_is_omap2430()		0
- + #define cpu_is_omap3503()		0
- + #define cpu_is_omap3515()		0
- + #define cpu_is_omap3525()		0
- + #define cpu_is_omap3530()		0
- + #define cpu_is_omap3505()		0
- + #define cpu_is_omap3517()		0
- + #define cpu_is_omap3430()		0
- + #define cpu_is_omap4430()		0
- + #define cpu_is_omap3630()		0
- + 
- + /*
- +  * Whether we have MULTI_OMAP1 or not, we still need to distinguish
- +  * between 730 vs 850, 330 vs. 1510 and 1611B/5912 vs. 1710.
- +  */
- + 
- + #if defined(CONFIG_ARCH_OMAP730)
- + # undef  cpu_is_omap730
- + # define cpu_is_omap730()		is_omap730()
- + #endif
- + 
- + #if defined(CONFIG_ARCH_OMAP850)
- + # undef  cpu_is_omap850
- + # define cpu_is_omap850()		is_omap850()
- + #endif
- + 
- + #if defined(CONFIG_ARCH_OMAP15XX)
- + # undef  cpu_is_omap310
- + # undef  cpu_is_omap1510
- + # define cpu_is_omap310()		is_omap310()
- + # define cpu_is_omap1510()		is_omap1510()
- + #endif
- + 
- + # undef cpu_is_omap3430
- + # undef cpu_is_omap3503
- + # undef cpu_is_omap3515
- + # undef cpu_is_omap3525
- + # undef cpu_is_omap3530
- + # undef cpu_is_omap3505
- + # undef cpu_is_omap3517
- + # undef cpu_is_ti81xx
- + # undef cpu_is_ti816x
- + # undef cpu_is_ti814x
- + # undef cpu_is_am33xx
- + # undef cpu_is_am335x
- + # define cpu_is_omap3430()		is_omap3430()
- + # define cpu_is_omap3503()		(cpu_is_omap3430() &&		\
- + 						(!omap3_has_iva()) &&	\
- + 						(!omap3_has_sgx()))
- + # define cpu_is_omap3515()		(cpu_is_omap3430() &&		\
- + 						(!omap3_has_iva()) &&	\
- + 						(omap3_has_sgx()))
- + # define cpu_is_omap3525()		(cpu_is_omap3430() &&		\
- + 						(!omap3_has_sgx()) &&	\
- + 						(omap3_has_iva()))
- + # define cpu_is_omap3530()		(cpu_is_omap3430())
- + # define cpu_is_omap3517()		is_omap3517()
- + # define cpu_is_omap3505()		(cpu_is_omap3517() &&		\
- + 						!omap3_has_sgx())
- + # undef cpu_is_omap3630
- + # define cpu_is_omap3630()		is_omap363x()
- + # define cpu_is_ti81xx()		is_ti81xx()
- + # define cpu_is_ti816x()		is_ti816x()
- + # define cpu_is_ti814x()		is_ti814x()
- + # define cpu_is_am33xx()		is_am33xx()
- + # define cpu_is_am335x()		is_am335x()
- + 
- + /* Macros to detect if we have OMAP1 or OMAP2 */
- + #define cpu_class_is_omap1()	(cpu_is_omap7xx() || cpu_is_omap15xx() || \
- + 				cpu_is_omap16xx())
- + #define cpu_class_is_omap2()	(cpu_is_omap24xx() || cpu_is_omap34xx() || \
- + 				cpu_is_omap44xx())
- + 
- + /* Various silicon revisions for omap2 */
- + #define OMAP242X_CLASS		0x24200024
- + #define OMAP2420_REV_ES1_0	OMAP242X_CLASS
- + #define OMAP2420_REV_ES2_0	(OMAP242X_CLASS | (0x1 << 8))
- + 
- + #define OMAP243X_CLASS		0x24300024
- + #define OMAP2430_REV_ES1_0	OMAP243X_CLASS
- + 
- + #define OMAP343X_CLASS		0x34300034
- + #define OMAP3430_REV_ES1_0	OMAP343X_CLASS
- + #define OMAP3430_REV_ES2_0	(OMAP343X_CLASS | (0x1 << 8))
- + #define OMAP3430_REV_ES2_1	(OMAP343X_CLASS | (0x2 << 8))
- + #define OMAP3430_REV_ES3_0	(OMAP343X_CLASS | (0x3 << 8))
- + #define OMAP3430_REV_ES3_1	(OMAP343X_CLASS | (0x4 << 8))
- + #define OMAP3430_REV_ES3_1_2	(OMAP343X_CLASS | (0x5 << 8))
- + 
- + #define OMAP363X_CLASS		0x36300034
- + #define OMAP3630_REV_ES1_0	OMAP363X_CLASS
- + #define OMAP3630_REV_ES1_1	(OMAP363X_CLASS | (0x1 << 8))
- + #define OMAP3630_REV_ES1_2	(OMAP363X_CLASS | (0x2 << 8))
- + 
- + #define OMAP3517_CLASS		0x35170034
- + #define OMAP3517_REV_ES1_0	OMAP3517_CLASS
- + #define OMAP3517_REV_ES1_1	(OMAP3517_CLASS | (0x1 << 8))
- + 
- + #define TI816X_CLASS		0x81600034
- + #define TI8168_REV_ES1_0	TI816X_CLASS
- + #define TI8168_REV_ES1_1	(TI816X_CLASS | (0x1 << 8))
- + 
- + #define TI814X_CLASS		0x81400034
- + #define TI8148_REV_ES1_0	TI814X_CLASS
- + #define TI8148_REV_ES2_0	(TI814X_CLASS | (0x1 << 8))
- + #define TI8148_REV_ES2_1	(TI814X_CLASS | (0x2 << 8))
- + 
- + #define AM335X_CLASS		0x33500034
- + #define AM335X_REV_ES1_0	AM335X_CLASS
- + #define AM335X_REV_ES2_0	(AM335X_CLASS | (0x1 << 8))
- + 
- + #define OMAP443X_CLASS		0x44300044
- + #define OMAP4430_REV_ES1_0	(OMAP443X_CLASS | (0x10 << 8))
- + #define OMAP4430_REV_ES2_0	(OMAP443X_CLASS | (0x20 << 8))
- + #define OMAP4430_REV_ES2_1	(OMAP443X_CLASS | (0x21 << 8))
- + #define OMAP4430_REV_ES2_2	(OMAP443X_CLASS | (0x22 << 8))
- + #define OMAP4430_REV_ES2_3	(OMAP443X_CLASS | (0x23 << 8))
- + 
- + #define OMAP446X_CLASS		0x44600044
- + #define OMAP4460_REV_ES1_0	(OMAP446X_CLASS | (0x10 << 8))
- + 
- + #define OMAP447X_CLASS		0x44700044
- + #define OMAP4470_REV_ES1_0	(OMAP447X_CLASS | (0x10 << 8))
- + 
- + void omap2xxx_check_revision(void);
- + void omap3xxx_check_revision(void);
- + void omap4xxx_check_revision(void);
- + void ti81xx_check_features(void);
- + void am33xx_check_features(void);
- + void omap4xxx_check_features(void);
- + 
- + /*
- +  * Runtime detection of OMAP3 features
- +  *
- +  * OMAP3_HAS_IO_CHAIN_CTRL: Some later members of the OMAP3 chip
- +  *    family have OS-level control over the I/O chain clock.  This is
- +  *    to avoid a window during which wakeups could potentially be lost
- +  *    during powerdomain transitions.  If this bit is set, it
- +  *    indicates that the chip does support OS-level control of this
- +  *    feature.
- +  */
- + extern u32 omap_features;
- + 
- + #define OMAP3_HAS_L2CACHE		BIT(0)
- + #define OMAP3_HAS_IVA			BIT(1)
- + #define OMAP3_HAS_SGX			BIT(2)
- + #define OMAP3_HAS_NEON			BIT(3)
- + #define OMAP3_HAS_ISP			BIT(4)
- + #define OMAP3_HAS_192MHZ_CLK		BIT(5)
- + #define OMAP3_HAS_IO_WAKEUP		BIT(6)
- + #define OMAP3_HAS_SDRC			BIT(7)
- + #define OMAP3_HAS_IO_CHAIN_CTRL		BIT(8)
- + #define OMAP4_HAS_MPU_1GHZ		BIT(9)
- + #define OMAP4_HAS_MPU_1_2GHZ		BIT(10)
- + #define OMAP4_HAS_MPU_1_5GHZ		BIT(11)
- + 
- + 
- + #define OMAP3_HAS_FEATURE(feat,flag)			\
- + static inline unsigned int omap3_has_ ##feat(void)	\
- + {							\
- + 	return omap_features & OMAP3_HAS_ ##flag;	\
- + }							\
- + 
- + OMAP3_HAS_FEATURE(l2cache, L2CACHE)
- + OMAP3_HAS_FEATURE(sgx, SGX)
- + OMAP3_HAS_FEATURE(iva, IVA)
- + OMAP3_HAS_FEATURE(neon, NEON)
- + OMAP3_HAS_FEATURE(isp, ISP)
- + OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK)
- + OMAP3_HAS_FEATURE(io_wakeup, IO_WAKEUP)
- + OMAP3_HAS_FEATURE(sdrc, SDRC)
- + OMAP3_HAS_FEATURE(io_chain_ctrl, IO_CHAIN_CTRL)
- + 
- + /*
- +  * Runtime detection of OMAP4 features
- +  */
- + #define OMAP4_HAS_FEATURE(feat, flag)			\
- + static inline unsigned int omap4_has_ ##feat(void)	\
- + {							\
- + 	return omap_features & OMAP4_HAS_ ##flag;	\
- + }							\
- + 
- + OMAP4_HAS_FEATURE(mpu_1ghz, MPU_1GHZ)
- + OMAP4_HAS_FEATURE(mpu_1_2ghz, MPU_1_2GHZ)
- + OMAP4_HAS_FEATURE(mpu_1_5ghz, MPU_1_5GHZ)
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/dma-33xx.h linux-3.2.1/arch/arm/plat-ckb/include/plat/dma-33xx.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/dma-33xx.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/dma-33xx.h	2014-05-15 13:25:14.119220727 +0900
- ***************
- *** 0 ****
- --- 1,87 ----
- + /*
- +  * AM33XX SDMA channel definitions
- +  *
- +  * This file is automatically generated from the AM33XX hardware databases.
- +  *
- +  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #ifndef __ARCH_ARM_MACH_OMAP2_AM33XX_DMA_H
- + #define __ARCH_ARM_MACH_OMAP2_AM33XX_DMA_H
- + 
- + 
- + #define AM33XX_DMA_ICSS0_7				0
- + #define AM33XX_DMA_ICSS0_6				1
- + #define AM33XX_DMA_MMCHS1_W				2
- + #define AM33XX_DMA_MMCHS1_R				3
- + #define AM33XX_DMA_AESEIP36T0_CTXIN			4
- + #define AM33XX_DMA_AESEIP36T0_DIN			5
- + #define AM33XX_DMA_AESEIP36T0_DOUT			6
- + #define AM33XX_DMA_AESEIP36T0_CTXOUT			7
- + #define AM33XX_DMA_MCASP0_X				8
- + #define AM33XX_DMA_MCASP0_R				9
- + #define AM33XX_DMA_MCASP1_X				10
- + #define AM33XX_DMA_MCASP1_R				11
- + #define AM33XX_DMA_MCASP2_X				12
- + #define AM33XX_DMA_MCASP2_R				13
- + #define AM33XX_DMA_PWMSS0_EPWM				14
- + #define AM33XX_DMA_PWMSS1_EPWM				15
- + #define AM33XX_DMA_SPIOCP0_CH0W				16
- + #define AM33XX_DMA_SPIOCP0_CH0R				17
- + #define AM33XX_DMA_SPIOCP0_CH1W				18
- + #define AM33XX_DMA_SPIOCP0_CH1R				19
- + #define AM33XX_DMA_SPIOCP3_CH1W				20
- + #define AM33XX_DMA_SPIOCP3_CH1R				21
- + #define AM33XX_DMA_GPIO					22
- + #define AM33XX_DMA_GPIO1				23
- + #define AM33XX_DMA_MMCHS0_W				24
- + #define AM33XX_DMA_MMCHS0_R				25
- + #define AM33XX_DMA_UART0_0				26
- + #define AM33XX_DMA_UART0_1				27
- + #define AM33XX_DMA_UART1_0				28
- + #define AM33XX_DMA_UART1_1				29
- + #define AM33XX_DMA_UART2_0				30
- + #define AM33XX_DMA_UART2_1				31
- + #define AM33XX_DMA_DESEIP16T0_IN			32
- + #define AM33XX_DMA_DESEIP16T0				33
- + #define AM33XX_DMA_DESEIP16T0_OUT			34
- + #define AM33XX_DMA_SHAEIP57T0_CTXIN			35
- + #define AM33XX_DMA_SHAEIP57T0_DIN			36
- + #define AM33XX_DMA_SHAEIP57T0_CTXOUT			37
- + #define AM33XX_DMA_PWMSS0_ECAP				38
- + #define AM33XX_DMA_PWMSS1_ECAP				39
- + #define AM33XX_DMA_DCAN_1				40
- + #define AM33XX_DMA_DCAN_2				41
- + #define AM33XX_DMA_SPIOCP1_CH0W				42
- + #define AM33XX_DMA_SPIOCP1_CH0R				43
- + #define AM33XX_DMA_SPIOCP1_CH1W				44
- + #define AM33XX_DMA_SPIOCP1_CH1R				45
- + #define AM33XX_DMA_PWMSS0_EQEP				46
- + #define AM33XX_DMA_DCAN_3				47
- + #define AM33XX_DMA_TIMER_4				48
- + #define AM33XX_DMA_TIMER_5				49
- + #define AM33XX_DMA_TIMER_6				50
- + #define AM33XX_DMA_TIMER_7				51
- + #define AM33XX_DMA_GPM					52
- + #define AM33XX_DMA_ADC0					53
- + #define AM33XX_DMA_PWMSS1_EQEP				56
- + #define AM33XX_DMA_ADC1					57
- + #define AM33XX_DMA_MSHSI2COCP0_TX			58
- + #define AM33XX_DMA_MSHSI2COCP0_RX			59
- + #define AM33XX_DMA_MSHSI2COCP1_TX			60
- + #define AM33XX_DMA_MSHSI2COCP1_RX			61
- + #define AM33XX_DMA_PWMSS2_ECAP				62
- + #define AM33XX_DMA_PWMSS2_EPW				63
- + #define AM33XX_DMA_MMCHS2_W				64	/* xBar */
- + #define AM33XX_DMA_MMCHS2_R				65	/* xBar */
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/dma-44xx.h linux-3.2.1/arch/arm/plat-ckb/include/plat/dma-44xx.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/dma-44xx.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/dma-44xx.h	2014-05-15 13:25:14.119220727 +0900
- ***************
- *** 0 ****
- --- 1,147 ----
- + /*
- +  * OMAP4 SDMA channel definitions
- +  *
- +  * Copyright (C) 2009-2010 Texas Instruments, Inc.
- +  * Copyright (C) 2009-2010 Nokia Corporation
- +  *
- +  * Santosh Shilimkar (santosh.shilimkar@ti.com)
- +  * Benoit Cousson (b-cousson@ti.com)
- +  * Paul Walmsley (paul@pwsan.com)
- +  *
- +  * This file is automatically generated from the OMAP hardware databases.
- +  * We respectfully ask that any modifications to this file be coordinated
- +  * with the public linux-omap@vger.kernel.org mailing list and the
- +  * authors above to ensure that the autogeneration scripts are kept
- +  * up-to-date with the file contents.
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #ifndef __ARCH_ARM_MACH_OMAP2_OMAP44XX_DMA_H
- + #define __ARCH_ARM_MACH_OMAP2_OMAP44XX_DMA_H
- + 
- + #define OMAP44XX_DMA_SYS_REQ0			2
- + #define OMAP44XX_DMA_SYS_REQ1			3
- + #define OMAP44XX_DMA_GPMC			4
- + #define OMAP44XX_DMA_DSS_DISPC_REQ		6
- + #define OMAP44XX_DMA_SYS_REQ2			7
- + #define OMAP44XX_DMA_MCASP1_AXEVT		8
- + #define OMAP44XX_DMA_ISS_REQ1			9
- + #define OMAP44XX_DMA_ISS_REQ2			10
- + #define OMAP44XX_DMA_MCASP1_AREVT		11
- + #define OMAP44XX_DMA_ISS_REQ3			12
- + #define OMAP44XX_DMA_ISS_REQ4			13
- + #define OMAP44XX_DMA_DSS_RFBI_REQ		14
- + #define OMAP44XX_DMA_SPI3_TX0			15
- + #define OMAP44XX_DMA_SPI3_RX0			16
- + #define OMAP44XX_DMA_MCBSP2_TX			17
- + #define OMAP44XX_DMA_MCBSP2_RX			18
- + #define OMAP44XX_DMA_MCBSP3_TX			19
- + #define OMAP44XX_DMA_MCBSP3_RX			20
- + #define OMAP44XX_DMA_C2C_SSCM_GPO0		21
- + #define OMAP44XX_DMA_C2C_SSCM_GPO1		22
- + #define OMAP44XX_DMA_SPI3_TX1			23
- + #define OMAP44XX_DMA_SPI3_RX1			24
- + #define OMAP44XX_DMA_I2C3_TX			25
- + #define OMAP44XX_DMA_I2C3_RX			26
- + #define OMAP44XX_DMA_I2C1_TX			27
- + #define OMAP44XX_DMA_I2C1_RX			28
- + #define OMAP44XX_DMA_I2C2_TX			29
- + #define OMAP44XX_DMA_I2C2_RX			30
- + #define OMAP44XX_DMA_MCBSP4_TX			31
- + #define OMAP44XX_DMA_MCBSP4_RX			32
- + #define OMAP44XX_DMA_MCBSP1_TX			33
- + #define OMAP44XX_DMA_MCBSP1_RX			34
- + #define OMAP44XX_DMA_SPI1_TX0			35
- + #define OMAP44XX_DMA_SPI1_RX0			36
- + #define OMAP44XX_DMA_SPI1_TX1			37
- + #define OMAP44XX_DMA_SPI1_RX1			38
- + #define OMAP44XX_DMA_SPI1_TX2			39
- + #define OMAP44XX_DMA_SPI1_RX2			40
- + #define OMAP44XX_DMA_SPI1_TX3			41
- + #define OMAP44XX_DMA_SPI1_RX3			42
- + #define OMAP44XX_DMA_SPI2_TX0			43
- + #define OMAP44XX_DMA_SPI2_RX0			44
- + #define OMAP44XX_DMA_SPI2_TX1			45
- + #define OMAP44XX_DMA_SPI2_RX1			46
- + #define OMAP44XX_DMA_MMC2_TX			47
- + #define OMAP44XX_DMA_MMC2_RX			48
- + #define OMAP44XX_DMA_UART1_TX			49
- + #define OMAP44XX_DMA_UART1_RX			50
- + #define OMAP44XX_DMA_UART2_TX			51
- + #define OMAP44XX_DMA_UART2_RX			52
- + #define OMAP44XX_DMA_UART3_TX			53
- + #define OMAP44XX_DMA_UART3_RX			54
- + #define OMAP44XX_DMA_UART4_TX			55
- + #define OMAP44XX_DMA_UART4_RX			56
- + #define OMAP44XX_DMA_MMC4_TX			57
- + #define OMAP44XX_DMA_MMC4_RX			58
- + #define OMAP44XX_DMA_MMC5_TX			59
- + #define OMAP44XX_DMA_MMC5_RX			60
- + #define OMAP44XX_DMA_MMC1_TX			61
- + #define OMAP44XX_DMA_MMC1_RX			62
- + #define OMAP44XX_DMA_SYS_REQ3			64
- + #define OMAP44XX_DMA_MCPDM_UP			65
- + #define OMAP44XX_DMA_MCPDM_DL			66
- + #define OMAP44XX_DMA_DMIC_REQ			67
- + #define OMAP44XX_DMA_C2C_SSCM_GPO2		68
- + #define OMAP44XX_DMA_C2C_SSCM_GPO3		69
- + #define OMAP44XX_DMA_SPI4_TX0			70
- + #define OMAP44XX_DMA_SPI4_RX0			71
- + #define OMAP44XX_DMA_DSS_DSI1_REQ0		72
- + #define OMAP44XX_DMA_DSS_DSI1_REQ1		73
- + #define OMAP44XX_DMA_DSS_DSI1_REQ2		74
- + #define OMAP44XX_DMA_DSS_DSI1_REQ3		75
- + #define OMAP44XX_DMA_DSS_HDMI_REQ		76
- + #define OMAP44XX_DMA_MMC3_TX			77
- + #define OMAP44XX_DMA_MMC3_RX			78
- + #define OMAP44XX_DMA_USIM_TX			79
- + #define OMAP44XX_DMA_USIM_RX			80
- + #define OMAP44XX_DMA_DSS_DSI2_REQ0		81
- + #define OMAP44XX_DMA_DSS_DSI2_REQ1		82
- + #define OMAP44XX_DMA_DSS_DSI2_REQ2		83
- + #define OMAP44XX_DMA_DSS_DSI2_REQ3		84
- + #define OMAP44XX_DMA_SLIMBUS1_TX0		85
- + #define OMAP44XX_DMA_SLIMBUS1_TX1		86
- + #define OMAP44XX_DMA_SLIMBUS1_TX2		87
- + #define OMAP44XX_DMA_SLIMBUS1_TX3		88
- + #define OMAP44XX_DMA_SLIMBUS1_RX0		89
- + #define OMAP44XX_DMA_SLIMBUS1_RX1		90
- + #define OMAP44XX_DMA_SLIMBUS1_RX2		91
- + #define OMAP44XX_DMA_SLIMBUS1_RX3		92
- + #define OMAP44XX_DMA_SLIMBUS2_TX0		93
- + #define OMAP44XX_DMA_SLIMBUS2_TX1		94
- + #define OMAP44XX_DMA_SLIMBUS2_TX2		95
- + #define OMAP44XX_DMA_SLIMBUS2_TX3		96
- + #define OMAP44XX_DMA_SLIMBUS2_RX0		97
- + #define OMAP44XX_DMA_SLIMBUS2_RX1		98
- + #define OMAP44XX_DMA_SLIMBUS2_RX2		99
- + #define OMAP44XX_DMA_SLIMBUS2_RX3		100
- + #define OMAP44XX_DMA_ABE_REQ_0			101
- + #define OMAP44XX_DMA_ABE_REQ_1			102
- + #define OMAP44XX_DMA_ABE_REQ_2			103
- + #define OMAP44XX_DMA_ABE_REQ_3			104
- + #define OMAP44XX_DMA_ABE_REQ_4			105
- + #define OMAP44XX_DMA_ABE_REQ_5			106
- + #define OMAP44XX_DMA_ABE_REQ_6			107
- + #define OMAP44XX_DMA_ABE_REQ_7			108
- + #define OMAP44XX_DMA_AES1_P_CTX_IN_REQ		109
- + #define OMAP44XX_DMA_AES1_P_DATA_IN_REQ		110
- + #define OMAP44XX_DMA_AES1_P_DATA_OUT_REQ	111
- + #define OMAP44XX_DMA_AES2_P_CTX_IN_REQ		112
- + #define OMAP44XX_DMA_AES2_P_DATA_IN_REQ		113
- + #define OMAP44XX_DMA_AES2_P_DATA_OUT_REQ	114
- + #define OMAP44XX_DMA_DES_P_CTX_IN_REQ		115
- + #define OMAP44XX_DMA_DES_P_DATA_IN_REQ		116
- + #define OMAP44XX_DMA_DES_P_DATA_OUT_REQ		117
- + #define OMAP44XX_DMA_SHA2_CTXIN_P		118
- + #define OMAP44XX_DMA_SHA2_DIN_P			119
- + #define OMAP44XX_DMA_SHA2_CTXOUT_P		120
- + #define OMAP44XX_DMA_AES1_P_CONTEXT_OUT_REQ	121
- + #define OMAP44XX_DMA_AES2_P_CONTEXT_OUT_REQ	122
- + #define OMAP44XX_DMA_I2C4_TX			124
- + #define OMAP44XX_DMA_I2C4_RX			125
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/dma.h linux-3.2.1/arch/arm/plat-ckb/include/plat/dma.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/dma.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/dma.h	2014-05-15 13:25:14.119220727 +0900
- ***************
- *** 0 ****
- --- 1,535 ----
- + /*
- +  *  arch/arm/plat-omap/include/mach/dma.h
- +  *
- +  *  Copyright (C) 2003 Nokia Corporation
- +  *  Author: Juha Yrjölä <juha.yrjola@nokia.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; either version 2 of the License, or
- +  * (at your option) any later version.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- +  */
- + #ifndef __ASM_ARCH_DMA_H
- + #define __ASM_ARCH_DMA_H
- + 
- + #include <linux/platform_device.h>
- + 
- + /*
- +  * TODO: These dma channel defines should go away once all
- +  * the omap drivers hwmod adapted.
- +  */
- + 
- + /* Move omap4 specific defines to dma-44xx.h */
- + #include "dma-44xx.h"
- + #include "dma-33xx.h"
- + 
- + /* DMA channels for omap1 */
- + #define OMAP_DMA_NO_DEVICE		0
- + #define OMAP_DMA_MCSI1_TX		1
- + #define OMAP_DMA_MCSI1_RX		2
- + #define OMAP_DMA_I2C_RX			3
- + #define OMAP_DMA_I2C_TX			4
- + #define OMAP_DMA_EXT_NDMA_REQ		5
- + #define OMAP_DMA_EXT_NDMA_REQ2		6
- + #define OMAP_DMA_UWIRE_TX		7
- + #define OMAP_DMA_MCBSP1_TX		8
- + #define OMAP_DMA_MCBSP1_RX		9
- + #define OMAP_DMA_MCBSP3_TX		10
- + #define OMAP_DMA_MCBSP3_RX		11
- + #define OMAP_DMA_UART1_TX		12
- + #define OMAP_DMA_UART1_RX		13
- + #define OMAP_DMA_UART2_TX		14
- + #define OMAP_DMA_UART2_RX		15
- + #define OMAP_DMA_MCBSP2_TX		16
- + #define OMAP_DMA_MCBSP2_RX		17
- + #define OMAP_DMA_UART3_TX		18
- + #define OMAP_DMA_UART3_RX		19
- + #define OMAP_DMA_CAMERA_IF_RX		20
- + #define OMAP_DMA_MMC_TX			21
- + #define OMAP_DMA_MMC_RX			22
- + #define OMAP_DMA_NAND			23
- + #define OMAP_DMA_IRQ_LCD_LINE		24
- + #define OMAP_DMA_MEMORY_STICK		25
- + #define OMAP_DMA_USB_W2FC_RX0		26
- + #define OMAP_DMA_USB_W2FC_RX1		27
- + #define OMAP_DMA_USB_W2FC_RX2		28
- + #define OMAP_DMA_USB_W2FC_TX0		29
- + #define OMAP_DMA_USB_W2FC_TX1		30
- + #define OMAP_DMA_USB_W2FC_TX2		31
- + 
- + /* These are only for 1610 */
- + #define OMAP_DMA_CRYPTO_DES_IN		32
- + #define OMAP_DMA_SPI_TX			33
- + #define OMAP_DMA_SPI_RX			34
- + #define OMAP_DMA_CRYPTO_HASH		35
- + #define OMAP_DMA_CCP_ATTN		36
- + #define OMAP_DMA_CCP_FIFO_NOT_EMPTY	37
- + #define OMAP_DMA_CMT_APE_TX_CHAN_0	38
- + #define OMAP_DMA_CMT_APE_RV_CHAN_0	39
- + #define OMAP_DMA_CMT_APE_TX_CHAN_1	40
- + #define OMAP_DMA_CMT_APE_RV_CHAN_1	41
- + #define OMAP_DMA_CMT_APE_TX_CHAN_2	42
- + #define OMAP_DMA_CMT_APE_RV_CHAN_2	43
- + #define OMAP_DMA_CMT_APE_TX_CHAN_3	44
- + #define OMAP_DMA_CMT_APE_RV_CHAN_3	45
- + #define OMAP_DMA_CMT_APE_TX_CHAN_4	46
- + #define OMAP_DMA_CMT_APE_RV_CHAN_4	47
- + #define OMAP_DMA_CMT_APE_TX_CHAN_5	48
- + #define OMAP_DMA_CMT_APE_RV_CHAN_5	49
- + #define OMAP_DMA_CMT_APE_TX_CHAN_6	50
- + #define OMAP_DMA_CMT_APE_RV_CHAN_6	51
- + #define OMAP_DMA_CMT_APE_TX_CHAN_7	52
- + #define OMAP_DMA_CMT_APE_RV_CHAN_7	53
- + #define OMAP_DMA_MMC2_TX		54
- + #define OMAP_DMA_MMC2_RX		55
- + #define OMAP_DMA_CRYPTO_DES_OUT		56
- + 
- + /* DMA channels for 24xx */
- + #define OMAP24XX_DMA_NO_DEVICE		0
- + #define OMAP24XX_DMA_XTI_DMA		1	/* S_DMA_0 */
- + #define OMAP24XX_DMA_EXT_DMAREQ0	2	/* S_DMA_1 */
- + #define OMAP24XX_DMA_EXT_DMAREQ1	3	/* S_DMA_2 */
- + #define OMAP24XX_DMA_GPMC		4	/* S_DMA_3 */
- + #define OMAP24XX_DMA_GFX		5	/* S_DMA_4 */
- + #define OMAP24XX_DMA_DSS		6	/* S_DMA_5 */
- + #define OMAP242X_DMA_VLYNQ_TX		7	/* S_DMA_6 */
- + #define OMAP24XX_DMA_EXT_DMAREQ2	7	/* S_DMA_6 */
- + #define OMAP24XX_DMA_CWT		8	/* S_DMA_7 */
- + #define OMAP24XX_DMA_AES_TX		9	/* S_DMA_8 */
- + #define OMAP24XX_DMA_AES_RX		10	/* S_DMA_9 */
- + #define OMAP24XX_DMA_DES_TX		11	/* S_DMA_10 */
- + #define OMAP24XX_DMA_DES_RX		12	/* S_DMA_11 */
- + #define OMAP24XX_DMA_SHA1MD5_RX		13	/* S_DMA_12 */
- + #define OMAP34XX_DMA_SHA2MD5_RX		13	/* S_DMA_12 */
- + #define OMAP242X_DMA_EXT_DMAREQ2	14	/* S_DMA_13 */
- + #define OMAP242X_DMA_EXT_DMAREQ3	15	/* S_DMA_14 */
- + #define OMAP242X_DMA_EXT_DMAREQ4	16	/* S_DMA_15 */
- + #define OMAP242X_DMA_EAC_AC_RD		17	/* S_DMA_16 */
- + #define OMAP242X_DMA_EAC_AC_WR		18	/* S_DMA_17 */
- + #define OMAP242X_DMA_EAC_MD_UL_RD	19	/* S_DMA_18 */
- + #define OMAP242X_DMA_EAC_MD_UL_WR	20	/* S_DMA_19 */
- + #define OMAP242X_DMA_EAC_MD_DL_RD	21	/* S_DMA_20 */
- + #define OMAP242X_DMA_EAC_MD_DL_WR	22	/* S_DMA_21 */
- + #define OMAP242X_DMA_EAC_BT_UL_RD	23	/* S_DMA_22 */
- + #define OMAP242X_DMA_EAC_BT_UL_WR	24	/* S_DMA_23 */
- + #define OMAP242X_DMA_EAC_BT_DL_RD	25	/* S_DMA_24 */
- + #define OMAP242X_DMA_EAC_BT_DL_WR	26	/* S_DMA_25 */
- + #define OMAP243X_DMA_EXT_DMAREQ3	14	/* S_DMA_13 */
- + #define OMAP24XX_DMA_SPI3_TX0		15	/* S_DMA_14 */
- + #define OMAP24XX_DMA_SPI3_RX0		16	/* S_DMA_15 */
- + #define OMAP24XX_DMA_MCBSP3_TX		17	/* S_DMA_16 */
- + #define OMAP24XX_DMA_MCBSP3_RX		18	/* S_DMA_17 */
- + #define OMAP24XX_DMA_MCBSP4_TX		19	/* S_DMA_18 */
- + #define OMAP24XX_DMA_MCBSP4_RX		20	/* S_DMA_19 */
- + #define OMAP24XX_DMA_MCBSP5_TX		21	/* S_DMA_20 */
- + #define OMAP24XX_DMA_MCBSP5_RX		22	/* S_DMA_21 */
- + #define OMAP24XX_DMA_SPI3_TX1		23	/* S_DMA_22 */
- + #define OMAP24XX_DMA_SPI3_RX1		24	/* S_DMA_23 */
- + #define OMAP243X_DMA_EXT_DMAREQ4	25	/* S_DMA_24 */
- + #define OMAP243X_DMA_EXT_DMAREQ5	26	/* S_DMA_25 */
- + #define OMAP34XX_DMA_I2C3_TX		25	/* S_DMA_24 */
- + #define OMAP34XX_DMA_I2C3_RX		26	/* S_DMA_25 */
- + #define OMAP24XX_DMA_I2C1_TX		27	/* S_DMA_26 */
- + #define OMAP24XX_DMA_I2C1_RX		28	/* S_DMA_27 */
- + #define OMAP24XX_DMA_I2C2_TX		29	/* S_DMA_28 */
- + #define OMAP24XX_DMA_I2C2_RX		30	/* S_DMA_29 */
- + #define OMAP24XX_DMA_MCBSP1_TX		31	/* S_DMA_30 */
- + #define OMAP24XX_DMA_MCBSP1_RX		32	/* S_DMA_31 */
- + #define OMAP24XX_DMA_MCBSP2_TX		33	/* S_DMA_32 */
- + #define OMAP24XX_DMA_MCBSP2_RX		34	/* S_DMA_33 */
- + #define OMAP24XX_DMA_SPI1_TX0		35	/* S_DMA_34 */
- + #define OMAP24XX_DMA_SPI1_RX0		36	/* S_DMA_35 */
- + #define OMAP24XX_DMA_SPI1_TX1		37	/* S_DMA_36 */
- + #define OMAP24XX_DMA_SPI1_RX1		38	/* S_DMA_37 */
- + #define OMAP24XX_DMA_SPI1_TX2		39	/* S_DMA_38 */
- + #define OMAP24XX_DMA_SPI1_RX2		40	/* S_DMA_39 */
- + #define OMAP24XX_DMA_SPI1_TX3		41	/* S_DMA_40 */
- + #define OMAP24XX_DMA_SPI1_RX3		42	/* S_DMA_41 */
- + #define OMAP24XX_DMA_SPI2_TX0		43	/* S_DMA_42 */
- + #define OMAP24XX_DMA_SPI2_RX0		44	/* S_DMA_43 */
- + #define OMAP24XX_DMA_SPI2_TX1		45	/* S_DMA_44 */
- + #define OMAP24XX_DMA_SPI2_RX1		46	/* S_DMA_45 */
- + #define OMAP24XX_DMA_MMC2_TX		47	/* S_DMA_46 */
- + #define OMAP24XX_DMA_MMC2_RX		48	/* S_DMA_47 */
- + #define OMAP24XX_DMA_UART1_TX		49	/* S_DMA_48 */
- + #define OMAP24XX_DMA_UART1_RX		50	/* S_DMA_49 */
- + #define OMAP24XX_DMA_UART2_TX		51	/* S_DMA_50 */
- + #define OMAP24XX_DMA_UART2_RX		52	/* S_DMA_51 */
- + #define OMAP24XX_DMA_UART3_TX		53	/* S_DMA_52 */
- + #define OMAP24XX_DMA_UART3_RX		54	/* S_DMA_53 */
- + #define OMAP24XX_DMA_USB_W2FC_TX0	55	/* S_DMA_54 */
- + #define OMAP24XX_DMA_USB_W2FC_RX0	56	/* S_DMA_55 */
- + #define OMAP24XX_DMA_USB_W2FC_TX1	57	/* S_DMA_56 */
- + #define OMAP24XX_DMA_USB_W2FC_RX1	58	/* S_DMA_57 */
- + #define OMAP24XX_DMA_USB_W2FC_TX2	59	/* S_DMA_58 */
- + #define OMAP24XX_DMA_USB_W2FC_RX2	60	/* S_DMA_59 */
- + #define OMAP24XX_DMA_MMC1_TX		61	/* S_DMA_60 */
- + #define OMAP24XX_DMA_MMC1_RX		62	/* S_DMA_61 */
- + #define OMAP24XX_DMA_MS			63	/* S_DMA_62 */
- + #define OMAP242X_DMA_EXT_DMAREQ5	64	/* S_DMA_63 */
- + #define OMAP243X_DMA_EXT_DMAREQ6	64	/* S_DMA_63 */
- + #define OMAP34XX_DMA_EXT_DMAREQ3	64	/* S_DMA_63 */
- + #define OMAP34XX_DMA_AES2_TX		65	/* S_DMA_64 */
- + #define OMAP34XX_DMA_AES2_RX		66	/* S_DMA_65 */
- + #define OMAP34XX_DMA_DES2_TX		67	/* S_DMA_66 */
- + #define OMAP34XX_DMA_DES2_RX		68	/* S_DMA_67 */
- + #define OMAP34XX_DMA_SHA1MD5_RX		69	/* S_DMA_68 */
- + #define OMAP34XX_DMA_SPI4_TX0		70	/* S_DMA_69 */
- + #define OMAP34XX_DMA_SPI4_RX0		71	/* S_DMA_70 */
- + #define OMAP34XX_DSS_DMA0		72	/* S_DMA_71 */
- + #define OMAP34XX_DSS_DMA1		73	/* S_DMA_72 */
- + #define OMAP34XX_DSS_DMA2		74	/* S_DMA_73 */
- + #define OMAP34XX_DSS_DMA3		75	/* S_DMA_74 */
- + #define OMAP34XX_DMA_MMC3_TX		77	/* S_DMA_76 */
- + #define OMAP34XX_DMA_MMC3_RX		78	/* S_DMA_77 */
- + #define OMAP34XX_DMA_USIM_TX		79	/* S_DMA_78 */
- + #define OMAP34XX_DMA_USIM_RX		80	/* S_DMA_79 */
- + 
- + #define OMAP36XX_DMA_UART4_TX		81	/* S_DMA_80 */
- + #define OMAP36XX_DMA_UART4_RX		82	/* S_DMA_81 */
- + 
- + /* Only for AM35xx */
- + #define AM35XX_DMA_UART4_TX		54
- + #define AM35XX_DMA_UART4_RX		55
- + 
- + /*----------------------------------------------------------------------------*/
- + 
- + #define OMAP1_DMA_TOUT_IRQ		(1 << 0)
- + #define OMAP_DMA_DROP_IRQ		(1 << 1)
- + #define OMAP_DMA_HALF_IRQ		(1 << 2)
- + #define OMAP_DMA_FRAME_IRQ		(1 << 3)
- + #define OMAP_DMA_LAST_IRQ		(1 << 4)
- + #define OMAP_DMA_BLOCK_IRQ		(1 << 5)
- + #define OMAP1_DMA_SYNC_IRQ		(1 << 6)
- + #define OMAP2_DMA_PKT_IRQ		(1 << 7)
- + #define OMAP2_DMA_TRANS_ERR_IRQ		(1 << 8)
- + #define OMAP2_DMA_SECURE_ERR_IRQ	(1 << 9)
- + #define OMAP2_DMA_SUPERVISOR_ERR_IRQ	(1 << 10)
- + #define OMAP2_DMA_MISALIGNED_ERR_IRQ	(1 << 11)
- + 
- + #define OMAP_DMA_CCR_EN			(1 << 7)
- + #define OMAP_DMA_CCR_RD_ACTIVE		(1 << 9)
- + #define OMAP_DMA_CCR_WR_ACTIVE		(1 << 10)
- + #define OMAP_DMA_CCR_SEL_SRC_DST_SYNC	(1 << 24)
- + #define OMAP_DMA_CCR_BUFFERING_DISABLE	(1 << 25)
- + 
- + #define OMAP_DMA_DATA_TYPE_S8		0x00
- + #define OMAP_DMA_DATA_TYPE_S16		0x01
- + #define OMAP_DMA_DATA_TYPE_S32		0x02
- + 
- + #define OMAP_DMA_SYNC_ELEMENT		0x00
- + #define OMAP_DMA_SYNC_FRAME		0x01
- + #define OMAP_DMA_SYNC_BLOCK		0x02
- + #define OMAP_DMA_SYNC_PACKET		0x03
- + 
- + #define OMAP_DMA_DST_SYNC_PREFETCH	0x02
- + #define OMAP_DMA_SRC_SYNC		0x01
- + #define OMAP_DMA_DST_SYNC		0x00
- + 
- + #define OMAP_DMA_PORT_EMIFF		0x00
- + #define OMAP_DMA_PORT_EMIFS		0x01
- + #define OMAP_DMA_PORT_OCP_T1		0x02
- + #define OMAP_DMA_PORT_TIPB		0x03
- + #define OMAP_DMA_PORT_OCP_T2		0x04
- + #define OMAP_DMA_PORT_MPUI		0x05
- + 
- + #define OMAP_DMA_AMODE_CONSTANT		0x00
- + #define OMAP_DMA_AMODE_POST_INC		0x01
- + #define OMAP_DMA_AMODE_SINGLE_IDX	0x02
- + #define OMAP_DMA_AMODE_DOUBLE_IDX	0x03
- + 
- + #define DMA_DEFAULT_FIFO_DEPTH		0x10
- + #define DMA_DEFAULT_ARB_RATE		0x01
- + /* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */
- + #define DMA_THREAD_RESERVE_NORM		(0x00 << 12) /* Def */
- + #define DMA_THREAD_RESERVE_ONET		(0x01 << 12)
- + #define DMA_THREAD_RESERVE_TWOT		(0x02 << 12)
- + #define DMA_THREAD_RESERVE_THREET	(0x03 << 12)
- + #define DMA_THREAD_FIFO_NONE		(0x00 << 14) /* Def */
- + #define DMA_THREAD_FIFO_75		(0x01 << 14)
- + #define DMA_THREAD_FIFO_25		(0x02 << 14)
- + #define DMA_THREAD_FIFO_50		(0x03 << 14)
- + 
- + /* DMA4_OCP_SYSCONFIG bits */
- + #define DMA_SYSCONFIG_MIDLEMODE_MASK		(3 << 12)
- + #define DMA_SYSCONFIG_CLOCKACTIVITY_MASK	(3 << 8)
- + #define DMA_SYSCONFIG_EMUFREE			(1 << 5)
- + #define DMA_SYSCONFIG_SIDLEMODE_MASK		(3 << 3)
- + #define DMA_SYSCONFIG_SOFTRESET			(1 << 2)
- + #define DMA_SYSCONFIG_AUTOIDLE			(1 << 0)
- + 
- + #define DMA_SYSCONFIG_MIDLEMODE(n)		((n) << 12)
- + #define DMA_SYSCONFIG_SIDLEMODE(n)		((n) << 3)
- + 
- + #define DMA_IDLEMODE_SMARTIDLE			0x2
- + #define DMA_IDLEMODE_NO_IDLE			0x1
- + #define DMA_IDLEMODE_FORCE_IDLE			0x0
- + 
- + /* Chaining modes*/
- + #ifndef CONFIG_ARCH_OMAP1
- + #define OMAP_DMA_STATIC_CHAIN		0x1
- + #define OMAP_DMA_DYNAMIC_CHAIN		0x2
- + #define OMAP_DMA_CHAIN_ACTIVE		0x1
- + #define OMAP_DMA_CHAIN_INACTIVE		0x0
- + #endif
- + 
- + #define DMA_CH_PRIO_HIGH		0x1
- + #define DMA_CH_PRIO_LOW			0x0 /* Def */
- + 
- + /* Errata handling */
- + #define IS_DMA_ERRATA(id)		(errata & (id))
- + #define SET_DMA_ERRATA(id)		(errata |= (id))
- + 
- + #define DMA_ERRATA_IFRAME_BUFFERING	BIT(0x0)
- + #define DMA_ERRATA_PARALLEL_CHANNELS	BIT(0x1)
- + #define DMA_ERRATA_i378			BIT(0x2)
- + #define DMA_ERRATA_i541			BIT(0x3)
- + #define DMA_ERRATA_i88			BIT(0x4)
- + #define DMA_ERRATA_3_3			BIT(0x5)
- + #define DMA_ROMCODE_BUG			BIT(0x6)
- + 
- + /* Attributes for OMAP DMA Contrller */
- + #define DMA_LINKED_LCH			BIT(0x0)
- + #define GLOBAL_PRIORITY			BIT(0x1)
- + #define RESERVE_CHANNEL			BIT(0x2)
- + #define IS_CSSA_32			BIT(0x3)
- + #define IS_CDSA_32			BIT(0x4)
- + #define IS_RW_PRIORITY			BIT(0x5)
- + #define ENABLE_1510_MODE		BIT(0x6)
- + #define SRC_PORT			BIT(0x7)
- + #define DST_PORT			BIT(0x8)
- + #define SRC_INDEX			BIT(0x9)
- + #define DST_INDEX			BIT(0xA)
- + #define IS_BURST_ONLY4			BIT(0xB)
- + #define CLEAR_CSR_ON_READ		BIT(0xC)
- + #define IS_WORD_16			BIT(0xD)
- + 
- + enum omap_reg_offsets {
- + 
- + GCR,		GSCR,		GRST1,		HW_ID,
- + PCH2_ID,	PCH0_ID,	PCH1_ID,	PCHG_ID,
- + PCHD_ID,	CAPS_0,		CAPS_1,		CAPS_2,
- + CAPS_3,		CAPS_4,		PCH2_SR,	PCH0_SR,
- + PCH1_SR,	PCHD_SR,	REVISION,	IRQSTATUS_L0,
- + IRQSTATUS_L1,	IRQSTATUS_L2,	IRQSTATUS_L3,	IRQENABLE_L0,
- + IRQENABLE_L1,	IRQENABLE_L2,	IRQENABLE_L3,	SYSSTATUS,
- + OCP_SYSCONFIG,
- + 
- + /* omap1+ specific */
- + CPC, CCR2, LCH_CTRL,
- + 
- + /* Common registers for all omap's */
- + CSDP,		CCR,		CICR,		CSR,
- + CEN,		CFN,		CSFI,		CSEI,
- + CSAC,		CDAC,		CDEI,
- + CDFI,		CLNK_CTRL,
- + 
- + /* Channel specific registers */
- + CSSA,		CDSA,		COLOR,
- + CCEN,		CCFN,
- + 
- + /* omap3630 and omap4 specific */
- + CDP,		CNDP,		CCDN,
- + 
- + };
- + 
- + enum omap_dma_burst_mode {
- + 	OMAP_DMA_DATA_BURST_DIS = 0,
- + 	OMAP_DMA_DATA_BURST_4,
- + 	OMAP_DMA_DATA_BURST_8,
- + 	OMAP_DMA_DATA_BURST_16,
- + };
- + 
- + enum end_type {
- + 	OMAP_DMA_LITTLE_ENDIAN = 0,
- + 	OMAP_DMA_BIG_ENDIAN
- + };
- + 
- + enum omap_dma_color_mode {
- + 	OMAP_DMA_COLOR_DIS = 0,
- + 	OMAP_DMA_CONSTANT_FILL,
- + 	OMAP_DMA_TRANSPARENT_COPY
- + };
- + 
- + enum omap_dma_write_mode {
- + 	OMAP_DMA_WRITE_NON_POSTED = 0,
- + 	OMAP_DMA_WRITE_POSTED,
- + 	OMAP_DMA_WRITE_LAST_NON_POSTED
- + };
- + 
- + enum omap_dma_channel_mode {
- + 	OMAP_DMA_LCH_2D = 0,
- + 	OMAP_DMA_LCH_G,
- + 	OMAP_DMA_LCH_P,
- + 	OMAP_DMA_LCH_PD
- + };
- + 
- + struct omap_dma_channel_params {
- + 	int data_type;		/* data type 8,16,32 */
- + 	int elem_count;		/* number of elements in a frame */
- + 	int frame_count;	/* number of frames in a element */
- + 
- + 	int src_port;		/* Only on OMAP1 REVISIT: Is this needed? */
- + 	int src_amode;		/* constant, post increment, indexed,
- + 					double indexed */
- + 	unsigned long src_start;	/* source address : physical */
- + 	int src_ei;		/* source element index */
- + 	int src_fi;		/* source frame index */
- + 
- + 	int dst_port;		/* Only on OMAP1 REVISIT: Is this needed? */
- + 	int dst_amode;		/* constant, post increment, indexed,
- + 					double indexed */
- + 	unsigned long dst_start;	/* source address : physical */
- + 	int dst_ei;		/* source element index */
- + 	int dst_fi;		/* source frame index */
- + 
- + 	int trigger;		/* trigger attached if the channel is
- + 					synchronized */
- + 	int sync_mode;		/* sycn on element, frame , block or packet */
- + 	int src_or_dst_synch;	/* source synch(1) or destination synch(0) */
- + 
- + 	int ie;			/* interrupt enabled */
- + 
- + 	unsigned char read_prio;/* read priority */
- + 	unsigned char write_prio;/* write priority */
- + 
- + #ifndef CONFIG_ARCH_OMAP1
- + 	enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */
- + #endif
- + };
- + 
- + struct omap_dma_lch {
- + 	int next_lch;
- + 	int dev_id;
- + 	u16 saved_csr;
- + 	u16 enabled_irqs;
- + 	const char *dev_name;
- + 	void (*callback)(int lch, u16 ch_status, void *data);
- + 	void *data;
- + 	long flags;
- + 	/* required for Dynamic chaining */
- + 	int prev_linked_ch;
- + 	int next_linked_ch;
- + 	int state;
- + 	int chain_id;
- + 	int status;
- + };
- + 
- + struct omap_dma_dev_attr {
- + 	u32 dev_caps;
- + 	u16 lch_count;
- + 	u16 chan_count;
- + 	struct omap_dma_lch *chan;
- + };
- + 
- + /* System DMA platform data structure */
- + struct omap_system_dma_plat_info {
- + 	struct omap_dma_dev_attr *dma_attr;
- + 	u32 errata;
- + 	void (*disable_irq_lch)(int lch);
- + 	void (*show_dma_caps)(void);
- + 	void (*clear_lch_regs)(int lch);
- + 	void (*clear_dma)(int lch);
- + 	void (*dma_write)(u32 val, int reg, int lch);
- + 	u32 (*dma_read)(int reg, int lch);
- + };
- + 
- + extern void omap_set_dma_priority(int lch, int dst_port, int priority);
- + extern int omap_request_dma(int dev_id, const char *dev_name,
- + 			void (*callback)(int lch, u16 ch_status, void *data),
- + 			void *data, int *dma_ch);
- + extern void omap_enable_dma_irq(int ch, u16 irq_bits);
- + extern void omap_disable_dma_irq(int ch, u16 irq_bits);
- + extern void omap_free_dma(int ch);
- + extern void omap_start_dma(int lch);
- + extern void omap_stop_dma(int lch);
- + extern void omap_set_dma_transfer_params(int lch, int data_type,
- + 					 int elem_count, int frame_count,
- + 					 int sync_mode,
- + 					 int dma_trigger, int src_or_dst_synch);
- + extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
- + 				    u32 color);
- + extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
- + extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);
- + 
- + extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
- + 				    unsigned long src_start,
- + 				    int src_ei, int src_fi);
- + extern void omap_set_dma_src_index(int lch, int eidx, int fidx);
- + extern void omap_set_dma_src_data_pack(int lch, int enable);
- + extern void omap_set_dma_src_burst_mode(int lch,
- + 					enum omap_dma_burst_mode burst_mode);
- + 
- + extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
- + 				     unsigned long dest_start,
- + 				     int dst_ei, int dst_fi);
- + extern void omap_set_dma_dest_index(int lch, int eidx, int fidx);
- + extern void omap_set_dma_dest_data_pack(int lch, int enable);
- + extern void omap_set_dma_dest_burst_mode(int lch,
- + 					 enum omap_dma_burst_mode burst_mode);
- + 
- + extern void omap_set_dma_params(int lch,
- + 				struct omap_dma_channel_params *params);
- + 
- + extern void omap_dma_link_lch(int lch_head, int lch_queue);
- + extern void omap_dma_unlink_lch(int lch_head, int lch_queue);
- + 
- + extern int omap_set_dma_callback(int lch,
- + 			void (*callback)(int lch, u16 ch_status, void *data),
- + 			void *data);
- + extern dma_addr_t omap_get_dma_src_pos(int lch);
- + extern dma_addr_t omap_get_dma_dst_pos(int lch);
- + extern void omap_clear_dma(int lch);
- + extern int omap_get_dma_active_status(int lch);
- + extern int omap_dma_running(void);
- + extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
- + 				       int tparams);
- + extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
- + 				 unsigned char write_prio);
- + extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype);
- + extern void omap_set_dma_src_endian_type(int lch, enum end_type etype);
- + extern int omap_get_dma_index(int lch, int *ei, int *fi);
- + 
- + void omap_dma_global_context_save(void);
- + void omap_dma_global_context_restore(void);
- + 
- + extern void omap_dma_disable_irq(int lch);
- + 
- + /* Chaining APIs */
- + #ifndef CONFIG_ARCH_OMAP1
- + extern int omap_request_dma_chain(int dev_id, const char *dev_name,
- + 				  void (*callback) (int lch, u16 ch_status,
- + 						    void *data),
- + 				  int *chain_id, int no_of_chans,
- + 				  int chain_mode,
- + 				  struct omap_dma_channel_params params);
- + extern int omap_free_dma_chain(int chain_id);
- + extern int omap_dma_chain_a_transfer(int chain_id, int src_start,
- + 				     int dest_start, int elem_count,
- + 				     int frame_count, void *callbk_data);
- + extern int omap_start_dma_chain_transfers(int chain_id);
- + extern int omap_stop_dma_chain_transfers(int chain_id);
- + extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi);
- + extern int omap_get_dma_chain_dst_pos(int chain_id);
- + extern int omap_get_dma_chain_src_pos(int chain_id);
- + 
- + extern int omap_modify_dma_chain_params(int chain_id,
- + 					struct omap_dma_channel_params params);
- + extern int omap_dma_chain_status(int chain_id);
- + #endif
- + 
- + static inline int omap_lcd_dma_running(void)
- + {
- + 	return 0;
- + }
- + 
- + #endif /* __ASM_ARCH_DMA_H */
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/dmtimer.h linux-3.2.1/arch/arm/plat-ckb/include/plat/dmtimer.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/dmtimer.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/dmtimer.h	2014-05-15 13:25:14.123055996 +0900
- ***************
- *** 0 ****
- --- 1,429 ----
- + /*
- +  * arch/arm/plat-omap/include/plat/dmtimer.h
- +  *
- +  * OMAP Dual-Mode Timers
- +  *
- +  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- +  * Tarun Kanti DebBarma <tarun.kanti@ti.com>
- +  * Thara Gopinath <thara@ti.com>
- +  *
- +  * Platform device conversion and hwmod support.
- +  *
- +  * Copyright (C) 2005 Nokia Corporation
- +  * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
- +  * PWM and clock framwork support by Timo Teras.
- +  *
- +  * This program is free software; you can redistribute it and/or modify it
- +  * under the terms of the GNU General Public License as published by the
- +  * Free Software Foundation; either version 2 of the License, or (at your
- +  * option) any later version.
- +  *
- +  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- +  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- +  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- +  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- +  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- +  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- +  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- +  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- +  *
- +  * You should have received a copy of the  GNU General Public License along
- +  * with this program; if not, write  to the Free Software Foundation, Inc.,
- +  * 675 Mass Ave, Cambridge, MA 02139, USA.
- +  */
- + 
- + #include <linux/clk.h>
- + #include <linux/delay.h>
- + #include <linux/io.h>
- + #include <linux/platform_device.h>
- + 
- + #ifndef __ASM_ARCH_DMTIMER_H
- + #define __ASM_ARCH_DMTIMER_H
- + 
- + /* clock sources */
- + #define OMAP_TIMER_SRC_SYS_CLK			0x00
- + #define OMAP_TIMER_SRC_32_KHZ			0x01
- + #define OMAP_TIMER_SRC_EXT_CLK			0x02
- + 
- + /* timer interrupt enable bits */
- + #define OMAP_TIMER_INT_CAPTURE			(1 << 2)
- + #define OMAP_TIMER_INT_CAPTURE_RESET		(0 << 2)
- + #define OMAP_TIMER_INT_OVERFLOW			(1 << 1)
- + #define OMAP_TIMER_INT_MATCH			(1 << 0)
- + 
- + /* trigger types */
- + #define OMAP_TIMER_TRIGGER_NONE			0x00
- + #define OMAP_TIMER_TRIGGER_OVERFLOW		0x01
- + #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE	0x02
- + 
- + /*
- +  * IP revision identifier so that Highlander IP
- +  * in OMAP4 can be distinguished.
- +  */
- + #define OMAP_TIMER_IP_VERSION_1                        0x1
- + 
- + /* timer capabilities used in hwmod database */
- + #define OMAP_TIMER_SECURE				0x80000000
- + #define OMAP_TIMER_ALWON				0x40000000
- + #define OMAP_TIMER_HAS_PWM				0x20000000
- + 
- + struct omap_timer_capability_dev_attr {
- + 	u32 timer_capability;
- + };
- + 
- + struct omap_dm_timer;
- + struct clk;
- + 
- + struct timer_regs {
- + 	u32 tidr;
- + 	u32 tiocp_cfg;
- + 	u32 tistat;
- + 	u32 tisr;
- + 	u32 tier;
- + 	u32 twer;
- + 	u32 tclr;
- + 	u32 tcrr;
- + 	u32 tldr;
- + 	u32 ttrg;
- + 	u32 twps;
- + 	u32 tmar;
- + 	u32 tcar1;
- + 	u32 tsicr;
- + 	u32 tcar2;
- + 	u32 tpir;
- + 	u32 tnir;
- + 	u32 tcvr;
- + 	u32 tocr;
- + 	u32 towr;
- + };
- + 
- + struct dmtimer_platform_data {
- + 	int (*set_timer_src)(struct platform_device *pdev, int source);
- + 	int timer_ip_version;
- + 	u32 needs_manual_reset:1;
- + 	bool reserved;
- + 
- + 	bool loses_context;
- + 
- + 	int (*get_context_loss_count)(struct device *dev);
- + };
- + 
- + struct omap_dm_timer *omap_dm_timer_request(void);
- + struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
- + int omap_dm_timer_free(struct omap_dm_timer *timer);
- + void omap_dm_timer_enable(struct omap_dm_timer *timer);
- + void omap_dm_timer_disable(struct omap_dm_timer *timer);
- + 
- + int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
- + 
- + u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
- + struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer);
- + 
- + int omap_dm_timer_trigger(struct omap_dm_timer *timer);
- + int omap_dm_timer_start(struct omap_dm_timer *timer);
- + int omap_dm_timer_stop(struct omap_dm_timer *timer);
- + 
- + int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
- + int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
- + int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
- + int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
- + int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
- + int omap_dm_timer_set_capture(struct omap_dm_timer *timer,
- + 				bool lht, bool hlt, bool cm);
- + int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
- + 
- + int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
- + 
- + unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
- + int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
- + unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer);
- + int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value);
- + 
- + int omap_dm_timers_active(void);
- + 
- + /*
- +  * Do not use the defines below, they are not needed. They should be only
- +  * used by dmtimer.c and sys_timer related code.
- +  */
- + 
- + /*
- +  * The interrupt registers are different between v1 and v2 ip.
- +  * These registers are offsets from timer->iobase.
- +  */
- + #define OMAP_TIMER_ID_OFFSET		0x00
- + #define OMAP_TIMER_OCP_CFG_OFFSET	0x10
- + 
- + #define OMAP_TIMER_V1_SYS_STAT_OFFSET	0x14
- + #define OMAP_TIMER_V1_STAT_OFFSET	0x18
- + #define OMAP_TIMER_V1_INT_EN_OFFSET	0x1c
- + 
- + #define OMAP_TIMER_V2_IRQSTATUS_RAW	0x24
- + #define OMAP_TIMER_V2_IRQSTATUS		0x28
- + #define OMAP_TIMER_V2_IRQENABLE_SET	0x2c
- + #define OMAP_TIMER_V2_IRQENABLE_CLR	0x30
- + 
- + /*
- +  * The functional registers have a different base on v1 and v2 ip.
- +  * These registers are offsets from timer->func_base. The func_base
- +  * is samae as io_base for v1 and io_base + 0x14 for v2 ip.
- +  *
- +  */
- + #define OMAP_TIMER_V2_FUNC_OFFSET		0x14
- + 
- + #define _OMAP_TIMER_WAKEUP_EN_OFFSET	0x20
- + #define _OMAP_TIMER_CTRL_OFFSET		0x24
- + #define		OMAP_TIMER_CTRL_GPOCFG		(1 << 14)
- + #define		OMAP_TIMER_CTRL_CAPTMODE	(1 << 13)
- + #define		OMAP_TIMER_CTRL_PT		(1 << 12)
- + #define		OMAP_TIMER_CTRL_TCM_LOWTOHIGH	(0x1 << 8)
- + #define		OMAP_TIMER_CTRL_TCM_HIGHTOLOW	(0x2 << 8)
- + #define		OMAP_TIMER_CTRL_TCM_BOTHEDGES	(0x3 << 8)
- + #define		OMAP_TIMER_CTRL_SCPWM		(1 << 7)
- + #define		OMAP_TIMER_CTRL_CE		(1 << 6) /* compare enable */
- + #define		OMAP_TIMER_CTRL_PRE		(1 << 5) /* prescaler enable */
- + #define		OMAP_TIMER_CTRL_PTV_SHIFT	2 /* prescaler value shift */
- + #define		OMAP_TIMER_CTRL_POSTED		(1 << 2)
- + #define		OMAP_TIMER_CTRL_AR		(1 << 1) /* auto-reload enable */
- + #define		OMAP_TIMER_CTRL_ST		(1 << 0) /* start timer */
- + #define _OMAP_TIMER_COUNTER_OFFSET	0x28
- + #define _OMAP_TIMER_LOAD_OFFSET		0x2c
- + #define _OMAP_TIMER_TRIGGER_OFFSET	0x30
- + #define _OMAP_TIMER_WRITE_PEND_OFFSET	0x34
- + #define		WP_NONE			0	/* no write pending bit */
- + #define		WP_TCLR			(1 << 0)
- + #define		WP_TCRR			(1 << 1)
- + #define		WP_TLDR			(1 << 2)
- + #define		WP_TTGR			(1 << 3)
- + #define		WP_TMAR			(1 << 4)
- + #define		WP_TPIR			(1 << 5)
- + #define		WP_TNIR			(1 << 6)
- + #define		WP_TCVR			(1 << 7)
- + #define		WP_TOCR			(1 << 8)
- + #define		WP_TOWR			(1 << 9)
- + #define _OMAP_TIMER_MATCH_OFFSET	0x38
- + #define _OMAP_TIMER_CAPTURE_OFFSET	0x3c
- + #define _OMAP_TIMER_IF_CTRL_OFFSET	0x40
- + #define _OMAP_TIMER_CAPTURE2_OFFSET		0x44	/* TCAR2, 34xx only */
- + #define _OMAP_TIMER_TICK_POS_OFFSET		0x48	/* TPIR, 34xx only */
- + #define _OMAP_TIMER_TICK_NEG_OFFSET		0x4c	/* TNIR, 34xx only */
- + #define _OMAP_TIMER_TICK_COUNT_OFFSET		0x50	/* TCVR, 34xx only */
- + #define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET	0x54	/* TOCR, 34xx only */
- + #define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET	0x58	/* TOWR, 34xx only */
- + 
- + /* register offsets with the write pending bit encoded */
- + #define	WPSHIFT					16
- + 
- + #define OMAP_TIMER_WAKEUP_EN_REG		(_OMAP_TIMER_WAKEUP_EN_OFFSET \
- + 							| (WP_NONE << WPSHIFT))
- + 
- + #define OMAP_TIMER_CTRL_REG			(_OMAP_TIMER_CTRL_OFFSET \
- + 							| (WP_TCLR << WPSHIFT))
- + 
- + #define OMAP_TIMER_COUNTER_REG			(_OMAP_TIMER_COUNTER_OFFSET \
- + 							| (WP_TCRR << WPSHIFT))
- + 
- + #define OMAP_TIMER_LOAD_REG			(_OMAP_TIMER_LOAD_OFFSET \
- + 							| (WP_TLDR << WPSHIFT))
- + 
- + #define OMAP_TIMER_TRIGGER_REG			(_OMAP_TIMER_TRIGGER_OFFSET \
- + 							| (WP_TTGR << WPSHIFT))
- + 
- + #define OMAP_TIMER_WRITE_PEND_REG		(_OMAP_TIMER_WRITE_PEND_OFFSET \
- + 							| (WP_NONE << WPSHIFT))
- + 
- + #define OMAP_TIMER_MATCH_REG			(_OMAP_TIMER_MATCH_OFFSET \
- + 							| (WP_TMAR << WPSHIFT))
- + 
- + #define OMAP_TIMER_CAPTURE_REG			(_OMAP_TIMER_CAPTURE_OFFSET \
- + 							| (WP_NONE << WPSHIFT))
- + 
- + #define OMAP_TIMER_IF_CTRL_REG			(_OMAP_TIMER_IF_CTRL_OFFSET \
- + 							| (WP_NONE << WPSHIFT))
- + 
- + #define OMAP_TIMER_CAPTURE2_REG			(_OMAP_TIMER_CAPTURE2_OFFSET \
- + 							| (WP_NONE << WPSHIFT))
- + 
- + #define OMAP_TIMER_TICK_POS_REG			(_OMAP_TIMER_TICK_POS_OFFSET \
- + 							| (WP_TPIR << WPSHIFT))
- + 
- + #define OMAP_TIMER_TICK_NEG_REG			(_OMAP_TIMER_TICK_NEG_OFFSET \
- + 							| (WP_TNIR << WPSHIFT))
- + 
- + #define OMAP_TIMER_TICK_COUNT_REG		(_OMAP_TIMER_TICK_COUNT_OFFSET \
- + 							| (WP_TCVR << WPSHIFT))
- + 
- + #define OMAP_TIMER_TICK_INT_MASK_SET_REG				\
- + 		(_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
- + 
- + #define OMAP_TIMER_TICK_INT_MASK_COUNT_REG				\
- + 		(_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
- + 
- + struct omap_dm_timer {
- + 	unsigned long phys_base;
- + 	int id;
- + 	int irq;
- + 	struct clk *iclk, *fclk;
- + 
- + 	void __iomem	*io_base;
- + 	void __iomem	*sys_stat;	/* TISTAT timer status */
- + 	void __iomem	*irq_stat;	/* TISR/IRQSTATUS interrupt status */
- + 	void __iomem	*irq_ena;	/* irq enable */
- + 	void __iomem	*irq_dis;	/* irq disable, only on v2 ip */
- + 	void __iomem	*pend;		/* write pending */
- + 	void __iomem	*func_base;	/* function register base */
- + 
- + 	unsigned long rate;
- + 	unsigned reserved:1;
- + 	unsigned posted:1;
- + 	struct timer_regs context;
- + 	bool loses_context;
- + 	int ctx_loss_count;
- + 	int revision;
- + 	struct platform_device *pdev;
- + 	struct list_head node;
- + 
- + 	int (*get_context_loss_count)(struct device *dev);
- + };
- + 
- + int omap_dm_timer_prepare(struct omap_dm_timer *timer);
- + 
- + static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg,
- + 						int posted)
- + {
- + 	if (posted)
- + 		while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
- + 			cpu_relax();
- + 
- + 	return __raw_readl(timer->func_base + (reg & 0xff));
- + }
- + 
- + static inline void __omap_dm_timer_write(struct omap_dm_timer *timer,
- + 					u32 reg, u32 val, int posted)
- + {
- + 	if (posted)
- + 		while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
- + 			cpu_relax();
- + 
- + 	__raw_writel(val, timer->func_base + (reg & 0xff));
- + }
- + 
- + static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
- + {
- + 	u32 tidr;
- + 
- + 	/* Assume v1 ip if bits [31:16] are zero */
- + 	tidr = __raw_readl(timer->io_base);
- + 	if (!(tidr >> 16)) {
- + 		timer->revision = 1;
- + 		timer->sys_stat = timer->io_base +
- + 				OMAP_TIMER_V1_SYS_STAT_OFFSET;
- + 		timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
- + 		timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
- + 		timer->irq_dis = 0;
- + 		timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
- + 		timer->func_base = timer->io_base;
- + 	} else {
- + 		timer->revision = 2;
- + 		timer->sys_stat = 0;
- + 		timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS;
- + 		timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET;
- + 		timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR;
- + 		timer->pend = timer->io_base +
- + 			_OMAP_TIMER_WRITE_PEND_OFFSET +
- + 				OMAP_TIMER_V2_FUNC_OFFSET;
- + 		timer->func_base = timer->io_base + OMAP_TIMER_V2_FUNC_OFFSET;
- + 	}
- + }
- + 
- + /* Assumes the source clock has been set by caller */
- + static inline void __omap_dm_timer_reset(struct omap_dm_timer *timer,
- + 					int autoidle, int wakeup)
- + {
- + 	u32 l;
- + 
- + 	l = __raw_readl(timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
- + 	l |= 0x02 << 3;  /* Set to smart-idle mode */
- + 	l |= 0x2 << 8;   /* Set clock activity to perserve f-clock on idle */
- + 
- + 	if (autoidle)
- + 		l |= 0x1 << 0;
- + 
- + 	if (wakeup)
- + 		l |= 1 << 2;
- + 
- + 	__raw_writel(l, timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
- + 
- + 	/* Match hardware reset default of posted mode */
- + 	__omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
- + 					OMAP_TIMER_CTRL_POSTED, 0);
- + }
- + 
- + static inline int __omap_dm_timer_set_source(struct clk *timer_fck,
- + 						struct clk *parent)
- + {
- + 	int ret;
- + 
- + 	clk_disable(timer_fck);
- + 	ret = clk_set_parent(timer_fck, parent);
- + 	clk_enable(timer_fck);
- + 
- + 	/*
- + 	 * When the functional clock disappears, too quick writes seem
- + 	 * to cause an abort. XXX Is this still necessary?
- + 	 */
- + 	__delay(300000);
- + 
- + 	return ret;
- + }
- + 
- + static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer,
- + 					int posted, unsigned long rate)
- + {
- + 	u32 l;
- + 
- + 	l = __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
- + 	if (l & OMAP_TIMER_CTRL_ST) {
- + 		l &= ~0x1;
- + 		__omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, l, posted);
- + 
- + 		/* Readback to make sure write has completed */
- + 		__omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
- + 		/*
- + 		 * Wait for functional clock period x 3.5 to make sure that
- + 		 * timer is stopped
- + 		 */
- + 		udelay(3500000 / rate + 1);
- + 	}
- + 
- + 	/* Ack possibly pending interrupt */
- + 	__raw_writel(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat);
- + }
- + 
- + static inline void __omap_dm_timer_load_start(struct omap_dm_timer *timer,
- + 						u32 ctrl, unsigned int load,
- + 						int posted)
- + {
- + 	__omap_dm_timer_write(timer, OMAP_TIMER_COUNTER_REG, load, posted);
- + 	__omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, ctrl, posted);
- + }
- + 
- + static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer,
- + 						unsigned int value)
- + {
- + 	__raw_writel(value, timer->irq_ena);
- + 	__omap_dm_timer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
- + }
- + 
- + static inline unsigned int
- + __omap_dm_timer_read_counter(struct omap_dm_timer *timer, int posted)
- + {
- + 	return __omap_dm_timer_read(timer, OMAP_TIMER_COUNTER_REG, posted);
- + }
- + 
- + static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer,
- + 						unsigned int value)
- + {
- + 	__raw_writel(value, timer->irq_stat);
- + }
- + 
- + #endif /* __ASM_ARCH_DMTIMER_H */
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/emif.h linux-3.2.1/arch/arm/plat-ckb/include/plat/emif.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/emif.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/emif.h	2014-05-15 13:25:14.123055996 +0900
- ***************
- *** 0 ****
- --- 1,43 ----
- + /*
- +  * EMIF register definitions for TI81xx and AM33xx
- +  *
- +  * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #ifndef __EMIF_H
- + #define __EMIF_H
- + 
- + #define EMIF_MOD_ID_REV			(0x0)
- + #define EMIF4_0_SDRAM_STATUS		(0x04)
- + #define EMIF4_0_SDRAM_CONFIG		(0x08)
- + #define EMIF4_0_SDRAM_CONFIG2		(0x0C)
- + #define EMIF4_0_SDRAM_REF_CTRL		(0x10)
- + #define EMIF4_0_SDRAM_REF_CTRL_SHADOW	(0x14)
- + #define EMIF4_0_SDRAM_TIM_1		(0x18)
- + #define EMIF4_0_SDRAM_TIM_1_SHADOW	(0x1C)
- + #define EMIF4_0_SDRAM_TIM_2		(0x20)
- + #define EMIF4_0_SDRAM_TIM_2_SHADOW	(0x24)
- + #define EMIF4_0_SDRAM_TIM_3		(0x28)
- + #define EMIF4_0_SDRAM_TIM_3_SHADOW	(0x2C)
- + #define EMIF4_0_SDRAM_MGMT_CTRL		(0x38)
- + #define EMIF4_0_SDRAM_MGMT_CTRL_SHADOW	(0x3C)
- + #define EMIF4_0_IODFT_TLGC		(0x60)
- + #define EMIF4_0_ZQ_CONFIG		(0xC8)
- + #define EMIF4_0_DDR_PHY_CTRL_1		(0xE4)
- + #define EMIF4_0_DDR_PHY_CTRL_1_SHADOW	(0xE8)
- + 
- + #define SELF_REFRESH_ENABLE(m)		(0x2 << 8 | (m << 4))
- + #define SELF_REFRESH_DISABLE		(0x0 << 8)
- + 
- + #define SDRAM_TYPE_MASK			0xe0000000
- + #define SDRAM_TYPE_SHIFT		29
- + #endif /* __EMIF_H */
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/gpio.h linux-3.2.1/arch/arm/plat-ckb/include/plat/gpio.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/gpio.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/gpio.h	2014-05-15 13:25:14.123055996 +0900
- ***************
- *** 0 ****
- --- 1,242 ----
- + /*
- +  * arch/arm/plat-omap/include/mach/gpio.h
- +  *
- +  * OMAP GPIO handling defines and functions
- +  *
- +  * Copyright (C) 2003-2005 Nokia Corporation
- +  *
- +  * Written by Juha Yrjölä <juha.yrjola@nokia.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; either version 2 of the License, or
- +  * (at your option) any later version.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- +  *
- +  */
- + 
- + #ifndef __ASM_ARCH_OMAP_GPIO_H
- + #define __ASM_ARCH_OMAP_GPIO_H
- + 
- + #ifndef __ASSEMBLER__
- + #include <linux/io.h>
- + #include <linux/platform_device.h>
- + #include <mach/irqs.h>
- + 
- + #endif
- + #define OMAP1_MPUIO_BASE			0xfffb5000
- + 
- + /*
- +  * These are the omap15xx/16xx offsets. The omap7xx offset are
- +  * OMAP_MPUIO_ / 2 offsets below.
- +  */
- + #define OMAP_MPUIO_INPUT_LATCH		0x00
- + #define OMAP_MPUIO_OUTPUT		0x04
- + #define OMAP_MPUIO_IO_CNTL		0x08
- + #define OMAP_MPUIO_KBR_LATCH		0x10
- + #define OMAP_MPUIO_KBC			0x14
- + #define OMAP_MPUIO_GPIO_EVENT_MODE	0x18
- + #define OMAP_MPUIO_GPIO_INT_EDGE	0x1c
- + #define OMAP_MPUIO_KBD_INT		0x20
- + #define OMAP_MPUIO_GPIO_INT		0x24
- + #define OMAP_MPUIO_KBD_MASKIT		0x28
- + #define OMAP_MPUIO_GPIO_MASKIT		0x2c
- + #define OMAP_MPUIO_GPIO_DEBOUNCING	0x30
- + #define OMAP_MPUIO_LATCH		0x34
- + 
- + #define OMAP34XX_NR_GPIOS		6
- + 
- + /*
- +  * OMAP1510 GPIO registers
- +  */
- + #define OMAP1510_GPIO_DATA_INPUT	0x00
- + #define OMAP1510_GPIO_DATA_OUTPUT	0x04
- + #define OMAP1510_GPIO_DIR_CONTROL	0x08
- + #define OMAP1510_GPIO_INT_CONTROL	0x0c
- + #define OMAP1510_GPIO_INT_MASK		0x10
- + #define OMAP1510_GPIO_INT_STATUS	0x14
- + #define OMAP1510_GPIO_PIN_CONTROL	0x18
- + 
- + #define OMAP1510_IH_GPIO_BASE		64
- + 
- + /*
- +  * OMAP1610 specific GPIO registers
- +  */
- + #define OMAP1610_GPIO_REVISION		0x0000
- + #define OMAP1610_GPIO_SYSCONFIG		0x0010
- + #define OMAP1610_GPIO_SYSSTATUS		0x0014
- + #define OMAP1610_GPIO_IRQSTATUS1	0x0018
- + #define OMAP1610_GPIO_IRQENABLE1	0x001c
- + #define OMAP1610_GPIO_WAKEUPENABLE	0x0028
- + #define OMAP1610_GPIO_DATAIN		0x002c
- + #define OMAP1610_GPIO_DATAOUT		0x0030
- + #define OMAP1610_GPIO_DIRECTION		0x0034
- + #define OMAP1610_GPIO_EDGE_CTRL1	0x0038
- + #define OMAP1610_GPIO_EDGE_CTRL2	0x003c
- + #define OMAP1610_GPIO_CLEAR_IRQENABLE1	0x009c
- + #define OMAP1610_GPIO_CLEAR_WAKEUPENA	0x00a8
- + #define OMAP1610_GPIO_CLEAR_DATAOUT	0x00b0
- + #define OMAP1610_GPIO_SET_IRQENABLE1	0x00dc
- + #define OMAP1610_GPIO_SET_WAKEUPENA	0x00e8
- + #define OMAP1610_GPIO_SET_DATAOUT	0x00f0
- + 
- + /*
- +  * OMAP7XX specific GPIO registers
- +  */
- + #define OMAP7XX_GPIO_DATA_INPUT		0x00
- + #define OMAP7XX_GPIO_DATA_OUTPUT	0x04
- + #define OMAP7XX_GPIO_DIR_CONTROL	0x08
- + #define OMAP7XX_GPIO_INT_CONTROL	0x0c
- + #define OMAP7XX_GPIO_INT_MASK		0x10
- + #define OMAP7XX_GPIO_INT_STATUS		0x14
- + 
- + /*
- +  * omap2+ specific GPIO registers
- +  */
- + #define OMAP24XX_GPIO_REVISION		0x0000
- + #define OMAP24XX_GPIO_IRQSTATUS1	0x0018
- + #define OMAP24XX_GPIO_IRQSTATUS2	0x0028
- + #define OMAP24XX_GPIO_IRQENABLE2	0x002c
- + #define OMAP24XX_GPIO_IRQENABLE1	0x001c
- + #define OMAP24XX_GPIO_WAKE_EN		0x0020
- + #define OMAP24XX_GPIO_CTRL		0x0030
- + #define OMAP24XX_GPIO_OE		0x0034
- + #define OMAP24XX_GPIO_DATAIN		0x0038
- + #define OMAP24XX_GPIO_DATAOUT		0x003c
- + #define OMAP24XX_GPIO_LEVELDETECT0	0x0040
- + #define OMAP24XX_GPIO_LEVELDETECT1	0x0044
- + #define OMAP24XX_GPIO_RISINGDETECT	0x0048
- + #define OMAP24XX_GPIO_FALLINGDETECT	0x004c
- + #define OMAP24XX_GPIO_DEBOUNCE_EN	0x0050
- + #define OMAP24XX_GPIO_DEBOUNCE_VAL	0x0054
- + #define OMAP24XX_GPIO_CLEARIRQENABLE1	0x0060
- + #define OMAP24XX_GPIO_SETIRQENABLE1	0x0064
- + #define OMAP24XX_GPIO_CLEARWKUENA	0x0080
- + #define OMAP24XX_GPIO_SETWKUENA		0x0084
- + #define OMAP24XX_GPIO_CLEARDATAOUT	0x0090
- + #define OMAP24XX_GPIO_SETDATAOUT	0x0094
- + 
- + #define OMAP4_GPIO_REVISION		0x0000
- + #define OMAP4_GPIO_EOI			0x0020
- + #define OMAP4_GPIO_IRQSTATUSRAW0	0x0024
- + #define OMAP4_GPIO_IRQSTATUSRAW1	0x0028
- + #define OMAP4_GPIO_IRQSTATUS0		0x002c
- + #define OMAP4_GPIO_IRQSTATUS1		0x0030
- + #define OMAP4_GPIO_IRQSTATUSSET0	0x0034
- + #define OMAP4_GPIO_IRQSTATUSSET1	0x0038
- + #define OMAP4_GPIO_IRQSTATUSCLR0	0x003c
- + #define OMAP4_GPIO_IRQSTATUSCLR1	0x0040
- + #define OMAP4_GPIO_IRQWAKEN0		0x0044
- + #define OMAP4_GPIO_IRQWAKEN1		0x0048
- + #define OMAP4_GPIO_IRQENABLE1		0x011c
- + #define OMAP4_GPIO_WAKE_EN		0x0120
- + #define OMAP4_GPIO_IRQSTATUS2		0x0128
- + #define OMAP4_GPIO_IRQENABLE2		0x012c
- + #define OMAP4_GPIO_CTRL			0x0130
- + #define OMAP4_GPIO_OE			0x0134
- + #define OMAP4_GPIO_DATAIN		0x0138
- + #define OMAP4_GPIO_DATAOUT		0x013c
- + #define OMAP4_GPIO_LEVELDETECT0		0x0140
- + #define OMAP4_GPIO_LEVELDETECT1		0x0144
- + #define OMAP4_GPIO_RISINGDETECT		0x0148
- + #define OMAP4_GPIO_FALLINGDETECT	0x014c
- + #define OMAP4_GPIO_DEBOUNCENABLE	0x0150
- + #define OMAP4_GPIO_DEBOUNCINGTIME	0x0154
- + #define OMAP4_GPIO_CLEARIRQENABLE1	0x0160
- + #define OMAP4_GPIO_SETIRQENABLE1	0x0164
- + #define OMAP4_GPIO_CLEARWKUENA		0x0180
- + #define OMAP4_GPIO_SETWKUENA		0x0184
- + #define OMAP4_GPIO_CLEARDATAOUT		0x0190
- + #define OMAP4_GPIO_SETDATAOUT		0x0194
- + 
- + #define OMAP_MPUIO(nr)		(OMAP_MAX_GPIO_LINES + (nr))
- + #define OMAP_GPIO_IS_MPUIO(nr)	((nr) >= OMAP_MAX_GPIO_LINES)
- + 
- + #define OMAP_GPIO_IRQ(nr)	(OMAP_GPIO_IS_MPUIO(nr) ? \
- + 				 IH_MPUIO_BASE + ((nr) & 0x0f) : \
- + 				 IH_GPIO_BASE + (nr))
- + 
- + #define METHOD_MPUIO		0
- + #define METHOD_GPIO_1510	1
- + #define METHOD_GPIO_1610	2
- + #define METHOD_GPIO_7XX		3
- + #define METHOD_GPIO_24XX	5
- + #define METHOD_GPIO_44XX	6
- + 
- + #ifndef __ASSEMBLER__
- + struct omap_gpio_dev_attr {
- + 	int bank_width;		/* GPIO bank width */
- + 	bool dbck_flag;		/* dbck required or not - True for OMAP3&4 */
- + };
- + 
- + struct omap_gpio_reg_offs {
- + 	u16 revision;
- + 	u16 direction;
- + 	u16 datain;
- + 	u16 dataout;
- + 	u16 set_dataout;
- + 	u16 clr_dataout;
- + 	u16 irqstatus;
- + 	u16 irqstatus2;
- + 	u16 irqenable;
- + 	u16 set_irqenable;
- + 	u16 clr_irqenable;
- + 	u16 debounce;
- + 	u16 debounce_en;
- + 
- + 	bool irqenable_inv;
- + };
- + 
- + struct omap_gpio_platform_data {
- + 	u16 virtual_irq_start;
- + 	int bank_type;
- + 	int bank_width;		/* GPIO bank width */
- + 	int bank_stride;	/* Only needed for omap1 MPUIO */
- + 	bool dbck_flag;		/* dbck required or not - True for OMAP3&4 */
- + 
- + 	struct omap_gpio_reg_offs *regs;
- + };
- + 
- + /* TODO: Analyze removing gpio_bank_count usage from driver code */
- + extern int gpio_bank_count;
- + 
- + extern void omap2_gpio_prepare_for_idle(int off_mode);
- + extern void omap2_gpio_resume_after_idle(void);
- + extern void omap_set_gpio_debounce(int gpio, int enable);
- + extern void omap_set_gpio_debounce_time(int gpio, int enable);
- + extern void omap_gpio_save_context(void);
- + extern void omap_gpio_restore_context(void);
- + /*-------------------------------------------------------------------------*/
- + 
- + /* Wrappers for "new style" GPIO calls, using the new infrastructure
- +  * which lets us plug in FPGA, I2C, and other implementations.
- +  * *
- +  * The original OMAP-specific calls should eventually be removed.
- +  */
- + 
- + #include <linux/errno.h>
- + #include <asm-generic/gpio.h>
- + 
- + static inline int irq_to_gpio(unsigned irq)
- + {
- + 	int tmp;
- + 
- + 	/* SOC gpio */
- + 	tmp = irq - IH_GPIO_BASE;
- + 	if (tmp < OMAP_MAX_GPIO_LINES)
- + 		return tmp;
- + 
- + 	/* we don't supply reverse mappings for non-SOC gpios */
- + 	return -EIO;
- + }
- + #endif
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/gpio-switch.h linux-3.2.1/arch/arm/plat-ckb/include/plat/gpio-switch.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/gpio-switch.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/gpio-switch.h	2014-05-15 13:25:14.123055996 +0900
- ***************
- *** 0 ****
- --- 1,54 ----
- + /*
- +  * GPIO switch definitions
- +  *
- +  * Copyright (C) 2006 Nokia Corporation
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #ifndef __ASM_ARCH_OMAP_GPIO_SWITCH_H
- + #define __ASM_ARCH_OMAP_GPIO_SWITCH_H
- + 
- + #include <linux/types.h>
- + 
- + /* Cover:
- +  *	high -> closed
- +  *	low  -> open
- +  * Connection:
- +  *	high -> connected
- +  *	low  -> disconnected
- +  * Activity:
- +  *	high -> active
- +  *	low  -> inactive
- +  *
- +  */
- + #define OMAP_GPIO_SWITCH_TYPE_COVER		0x0000
- + #define OMAP_GPIO_SWITCH_TYPE_CONNECTION	0x0001
- + #define OMAP_GPIO_SWITCH_TYPE_ACTIVITY		0x0002
- + #define OMAP_GPIO_SWITCH_FLAG_INVERTED		0x0001
- + #define OMAP_GPIO_SWITCH_FLAG_OUTPUT		0x0002
- + 
- + struct omap_gpio_switch {
- + 	const char *name;
- + 	s16 gpio;
- + 	unsigned flags:4;
- + 	unsigned type:4;
- + 
- + 	/* Time in ms to debounce when transitioning from
- + 	 * inactive state to active state. */
- + 	u16 debounce_rising;
- + 	/* Same for transition from active to inactive state. */
- + 	u16 debounce_falling;
- + 
- + 	/* notify board-specific code about state changes */
- + 	void (* notify)(void *data, int state);
- + 	void *notify_data;
- + };
- + 
- + /* Call at init time only */
- + extern void omap_register_gpio_switches(const struct omap_gpio_switch *tbl,
- + 					int count);
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/gpmc.h linux-3.2.1/arch/arm/plat-ckb/include/plat/gpmc.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/gpmc.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/gpmc.h	2014-05-15 13:25:14.123055996 +0900
- ***************
- *** 0 ****
- --- 1,179 ----
- + /*
- +  * General-Purpose Memory Controller for OMAP2
- +  *
- +  * Copyright (C) 2005-2006 Nokia Corporation
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #ifndef __OMAP2_GPMC_H
- + #define __OMAP2_GPMC_H
- + 
- + /* Maximum Number of Chip Selects */
- + #define GPMC_CS_NUM		8
- + 
- + #define GPMC_CS_CONFIG1		0x00
- + #define GPMC_CS_CONFIG2		0x04
- + #define GPMC_CS_CONFIG3		0x08
- + #define GPMC_CS_CONFIG4		0x0c
- + #define GPMC_CS_CONFIG5		0x10
- + #define GPMC_CS_CONFIG6		0x14
- + #define GPMC_CS_CONFIG7		0x18
- + #define GPMC_CS_NAND_COMMAND	0x1c
- + #define GPMC_CS_NAND_ADDRESS	0x20
- + #define GPMC_CS_NAND_DATA	0x24
- + 
- + /* Control Commands */
- + #define GPMC_CONFIG_RDY_BSY	0x00000001
- + #define GPMC_CONFIG_DEV_SIZE	0x00000002
- + #define GPMC_CONFIG_DEV_TYPE	0x00000003
- + #define GPMC_SET_IRQ_STATUS	0x00000004
- + #define GPMC_CONFIG_WP		0x00000005
- + 
- + #define GPMC_GET_IRQ_STATUS	0x00000006
- + #define GPMC_PREFETCH_FIFO_CNT	0x00000007 /* bytes available in FIFO for r/w */
- + #define GPMC_PREFETCH_COUNT	0x00000008 /* remaining bytes to be read/write*/
- + #define GPMC_STATUS_BUFFER	0x00000009 /* 1: buffer is available to write */
- + 
- + #define GPMC_NAND_COMMAND	0x0000000a
- + #define GPMC_NAND_ADDRESS	0x0000000b
- + #define GPMC_NAND_DATA		0x0000000c
- + 
- + #define GPMC_ENABLE_IRQ		0x0000000d
- + 
- + /* ECC commands */
- + #define GPMC_ECC_READ		0 /* Reset Hardware ECC for read */
- + #define GPMC_ECC_WRITE		1 /* Reset Hardware ECC for write */
- + #define GPMC_ECC_READSYN	2 /* Reset before syndrom is read back */
- + 
- + #define GPMC_CONFIG1_WRAPBURST_SUPP     (1 << 31)
- + #define GPMC_CONFIG1_READMULTIPLE_SUPP  (1 << 30)
- + #define GPMC_CONFIG1_READTYPE_ASYNC     (0 << 29)
- + #define GPMC_CONFIG1_READTYPE_SYNC      (1 << 29)
- + #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
- + #define GPMC_CONFIG1_WRITETYPE_ASYNC    (0 << 27)
- + #define GPMC_CONFIG1_WRITETYPE_SYNC     (1 << 27)
- + #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
- + #define GPMC_CONFIG1_PAGE_LEN(val)      ((val & 3) << 23)
- + #define GPMC_CONFIG1_WAIT_READ_MON      (1 << 22)
- + #define GPMC_CONFIG1_WAIT_WRITE_MON     (1 << 21)
- + #define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18)
- + #define GPMC_CONFIG1_WAIT_PIN_SEL(val)  ((val & 3) << 16)
- + #define GPMC_CONFIG1_DEVICESIZE(val)    ((val & 3) << 12)
- + #define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
- + #define GPMC_CONFIG1_DEVICETYPE(val)    ((val & 3) << 10)
- + #define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
- + #define GPMC_CONFIG1_MUXADDDATA         (1 << 9)
- + #define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
- + #define GPMC_CONFIG1_FCLK_DIV(val)      (val & 3)
- + #define GPMC_CONFIG1_FCLK_DIV2          (GPMC_CONFIG1_FCLK_DIV(1))
- + #define GPMC_CONFIG1_FCLK_DIV3          (GPMC_CONFIG1_FCLK_DIV(2))
- + #define GPMC_CONFIG1_FCLK_DIV4          (GPMC_CONFIG1_FCLK_DIV(3))
- + #define GPMC_CONFIG7_CSVALID		(1 << 6)
- + 
- + #define GPMC_DEVICETYPE_NOR		0
- + #define GPMC_DEVICETYPE_NAND		2
- + #define GPMC_CONFIG_WRITEPROTECT	0x00000010
- + #define GPMC_STATUS_BUFF_EMPTY		0x00000001
- + #define WR_RD_PIN_MONITORING		0x00600000
- + #define GPMC_PREFETCH_STATUS_FIFO_CNT(val)	((val >> 24) & 0x7F)
- + #define GPMC_PREFETCH_STATUS_COUNT(val)	(val & 0x00003fff)
- + #define GPMC_IRQ_FIFOEVENTENABLE	0x01
- + #define GPMC_IRQ_COUNT_EVENT		0x02
- + 
- + #define PREFETCH_FIFOTHRESHOLD_MAX	0x40
- + #define PREFETCH_FIFOTHRESHOLD(val)	((val) << 8)
- + 
- + enum omap_ecc {
- + 		/* 1-bit ecc: stored at end of spare area */
- + 	OMAP_ECC_HAMMING_CODE_DEFAULT = 0, /* Default, s/w method */
- + 	OMAP_ECC_HAMMING_CODE_HW, /* gpmc to detect the error */
- + 		/* 1-bit ecc: stored at beginning of spare area as romcode */
- + 	OMAP_ECC_HAMMING_CODE_HW_ROMCODE, /* gpmc method & romcode layout */
- + 	OMAP_ECC_BCH4_CODE_HW, /* gpmc bch detection & s/w method correction */
- + 	OMAP_ECC_BCH8_CODE_HW, /* gpmc bch detection & s/w method correction */
- + };
- + 
- + /*
- +  * Note that all values in this struct are in nanoseconds except sync_clk
- +  * (which is in picoseconds), while the register values are in gpmc_fck cycles.
- +  */
- + struct gpmc_timings {
- + 	/* Minimum clock period for synchronous mode (in picoseconds) */
- + 	u32 sync_clk;
- + 
- + 	/* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
- + 	u16 cs_on;		/* Assertion time */
- + 	u16 cs_rd_off;		/* Read deassertion time */
- + 	u16 cs_wr_off;		/* Write deassertion time */
- + 
- + 	/* ADV signal timings corresponding to GPMC_CONFIG3 */
- + 	u16 adv_on;		/* Assertion time */
- + 	u16 adv_rd_off;		/* Read deassertion time */
- + 	u16 adv_wr_off;		/* Write deassertion time */
- + 
- + 	/* WE signals timings corresponding to GPMC_CONFIG4 */
- + 	u16 we_on;		/* WE assertion time */
- + 	u16 we_off;		/* WE deassertion time */
- + 
- + 	/* OE signals timings corresponding to GPMC_CONFIG4 */
- + 	u16 oe_on;		/* OE assertion time */
- + 	u16 oe_off;		/* OE deassertion time */
- + 
- + 	/* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
- + 	u16 page_burst_access;	/* Multiple access word delay */
- + 	u16 access;		/* Start-cycle to first data valid delay */
- + 	u16 rd_cycle;		/* Total read cycle time */
- + 	u16 wr_cycle;		/* Total write cycle time */
- + 
- + 	/* The following are only on OMAP3430 */
- + 	u16 wr_access;		/* WRACCESSTIME */
- + 	u16 wr_data_mux_bus;	/* WRDATAONADMUXBUS */
- + };
- + 
- + 
- + struct gpmc_devices_info {
- + 	void	*pdata;
- + 	int	flag;
- + };
- + 
- + #define	GPMC_DEVICE_NAND	(1 << 0)
- + #define	GPMC_DEVICE_ONENAND	(1 << 1)
- + #define	GPMC_DEVICE_NOR		(1 << 2)
- + #define	GPMC_DEVICE_SMC91X	(1 << 3)
- + #define	GPMC_DEVICE_SMS911X	(1 << 4)
- + #define	GPMC_DEVICE_TUSB6010	(1 << 5)
- + 
- + extern int omap_init_gpmc(struct gpmc_devices_info *pdata, int pdata_len);
- + 
- + extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
- + extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps);
- + extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
- + extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
- + extern unsigned long gpmc_get_fclk_period(void);
- + 
- + extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
- + extern u32 gpmc_cs_read_reg(int cs, int idx);
- + extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk);
- + extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
- + extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
- + extern void gpmc_cs_free(int cs);
- + extern int gpmc_cs_set_reserved(int cs, int reserved);
- + extern int gpmc_cs_reserved(int cs);
- + extern int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
- + 					unsigned int u32_count, int is_write);
- + extern int gpmc_prefetch_reset(int cs);
- + extern void omap3_gpmc_save_context(void);
- + extern void omap3_gpmc_restore_context(void);
- + extern int gpmc_read_status(int cmd);
- + extern int gpmc_cs_configure(int cs, int cmd, int wval);
- + extern int gpmc_nand_read(int cs, int cmd);
- + extern int gpmc_nand_write(int cs, int cmd, int wval);
- + 
- + int gpmc_enable_hwecc(int ecc, int cs, int mode, int dev_width, int ecc_size);
- + int gpmc_calculate_ecc(int ecc, int cs, const u_char *dat, u_char *ecc_code);
- + int gpmc_suspend(void);
- + int gpmc_resume(void);
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/hardware.h linux-3.2.1/arch/arm/plat-ckb/include/plat/hardware.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/hardware.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/hardware.h	2014-05-15 13:25:14.127028930 +0900
- ***************
- *** 0 ****
- --- 1,246 ----
- + /*
- +  * arch/arm/plat-omap/include/mach/hardware.h
- +  *
- +  * Hardware definitions for TI OMAP processors and boards
- +  *
- +  * NOTE: Please put device driver specific defines into a separate header
- +  *	 file for each driver.
- +  *
- +  * Copyright (C) 2001 RidgeRun, Inc.
- +  * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
- +  *
- +  * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
- +  *                          and Dirk Behme <dirk.behme@de.bosch.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify it
- +  * under the terms of the GNU General Public License as published by the
- +  * Free Software Foundation; either version 2 of the License, or (at your
- +  * option) any later version.
- +  *
- +  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- +  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- +  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- +  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- +  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- +  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- +  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- +  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- +  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- +  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- +  *
- +  * You should have received a copy of the GNU General Public License along
- +  * with this program; if not, write to the Free Software Foundation, Inc.,
- +  * 675 Mass Ave, Cambridge, MA 02139, USA.
- +  */
- + 
- + #ifndef __ASM_ARCH_OMAP_HARDWARE_H
- + #define __ASM_ARCH_OMAP_HARDWARE_H
- + 
- + #include <asm/sizes.h>
- + #ifndef __ASSEMBLER__
- + #include <asm/types.h>
- + #include <plat/cpu.h>
- + #endif
- + #include <plat/serial.h>
- + 
- + /*
- +  * ---------------------------------------------------------------------------
- +  * Common definitions for all OMAP processors
- +  * NOTE: Put all processor or board specific parts to the special header
- +  *	 files.
- +  * ---------------------------------------------------------------------------
- +  */
- + 
- + /*
- +  * ----------------------------------------------------------------------------
- +  * Timers
- +  * ----------------------------------------------------------------------------
- +  */
- + #define OMAP_MPU_TIMER1_BASE	(0xfffec500)
- + #define OMAP_MPU_TIMER2_BASE	(0xfffec600)
- + #define OMAP_MPU_TIMER3_BASE	(0xfffec700)
- + #define MPU_TIMER_FREE		(1 << 6)
- + #define MPU_TIMER_CLOCK_ENABLE	(1 << 5)
- + #define MPU_TIMER_AR		(1 << 1)
- + #define MPU_TIMER_ST		(1 << 0)
- + 
- + /*
- +  * ----------------------------------------------------------------------------
- +  * Clocks
- +  * ----------------------------------------------------------------------------
- +  */
- + #define CLKGEN_REG_BASE		(0xfffece00)
- + #define ARM_CKCTL		(CLKGEN_REG_BASE + 0x0)
- + #define ARM_IDLECT1		(CLKGEN_REG_BASE + 0x4)
- + #define ARM_IDLECT2		(CLKGEN_REG_BASE + 0x8)
- + #define ARM_EWUPCT		(CLKGEN_REG_BASE + 0xC)
- + #define ARM_RSTCT1		(CLKGEN_REG_BASE + 0x10)
- + #define ARM_RSTCT2		(CLKGEN_REG_BASE + 0x14)
- + #define ARM_SYSST		(CLKGEN_REG_BASE + 0x18)
- + #define ARM_IDLECT3		(CLKGEN_REG_BASE + 0x24)
- + 
- + #define CK_RATEF		1
- + #define CK_IDLEF		2
- + #define CK_ENABLEF		4
- + #define CK_SELECTF		8
- + #define SETARM_IDLE_SHIFT
- + 
- + /* DPLL control registers */
- + #define DPLL_CTL		(0xfffecf00)
- + 
- + /* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
- + #define DSP_CONFIG_REG_BASE     IOMEM(0xe1008000)
- + #define DSP_CKCTL		(DSP_CONFIG_REG_BASE + 0x0)
- + #define DSP_IDLECT1		(DSP_CONFIG_REG_BASE + 0x4)
- + #define DSP_IDLECT2		(DSP_CONFIG_REG_BASE + 0x8)
- + #define DSP_RSTCT2		(DSP_CONFIG_REG_BASE + 0x14)
- + 
- + /*
- +  * ---------------------------------------------------------------------------
- +  * UPLD
- +  * ---------------------------------------------------------------------------
- +  */
- + #define ULPD_REG_BASE		(0xfffe0800)
- + #define ULPD_IT_STATUS		(ULPD_REG_BASE + 0x14)
- + #define ULPD_SETUP_ANALOG_CELL_3	(ULPD_REG_BASE + 0x24)
- + #define ULPD_CLOCK_CTRL		(ULPD_REG_BASE + 0x30)
- + #	define DIS_USB_PVCI_CLK		(1 << 5)	/* no USB/FAC synch */
- + #	define USB_MCLK_EN		(1 << 4)	/* enable W4_USB_CLKO */
- + #define ULPD_SOFT_REQ		(ULPD_REG_BASE + 0x34)
- + #	define SOFT_UDC_REQ		(1 << 4)
- + #	define SOFT_USB_CLK_REQ		(1 << 3)
- + #	define SOFT_DPLL_REQ		(1 << 0)
- + #define ULPD_DPLL_CTRL		(ULPD_REG_BASE + 0x3c)
- + #define ULPD_STATUS_REQ		(ULPD_REG_BASE + 0x40)
- + #define ULPD_APLL_CTRL		(ULPD_REG_BASE + 0x4c)
- + #define ULPD_POWER_CTRL		(ULPD_REG_BASE + 0x50)
- + #define ULPD_SOFT_DISABLE_REQ_REG	(ULPD_REG_BASE + 0x68)
- + #	define DIS_MMC2_DPLL_REQ	(1 << 11)
- + #	define DIS_MMC1_DPLL_REQ	(1 << 10)
- + #	define DIS_UART3_DPLL_REQ	(1 << 9)
- + #	define DIS_UART2_DPLL_REQ	(1 << 8)
- + #	define DIS_UART1_DPLL_REQ	(1 << 7)
- + #	define DIS_USB_HOST_DPLL_REQ	(1 << 6)
- + #define ULPD_SDW_CLK_DIV_CTRL_SEL	(ULPD_REG_BASE + 0x74)
- + #define ULPD_CAM_CLK_CTRL	(ULPD_REG_BASE + 0x7c)
- + 
- + /*
- +  * ---------------------------------------------------------------------------
- +  * Watchdog timer
- +  * ---------------------------------------------------------------------------
- +  */
- + 
- + /* Watchdog timer within the OMAP3.2 gigacell */
- + #define OMAP_MPU_WATCHDOG_BASE	(0xfffec800)
- + #define OMAP_WDT_TIMER		(OMAP_MPU_WATCHDOG_BASE + 0x0)
- + #define OMAP_WDT_LOAD_TIM	(OMAP_MPU_WATCHDOG_BASE + 0x4)
- + #define OMAP_WDT_READ_TIM	(OMAP_MPU_WATCHDOG_BASE + 0x4)
- + #define OMAP_WDT_TIMER_MODE	(OMAP_MPU_WATCHDOG_BASE + 0x8)
- + 
- + /*
- +  * ----------------------------------------------------------------------------
- +  * System control registers
- +  * ----------------------------------------------------------------------------
- +  */
- + #define MOD_CONF_CTRL_0		0xfffe1080
- + #define MOD_CONF_CTRL_1		0xfffe1110
- + 
- + /*
- +  * ----------------------------------------------------------------------------
- +  * Pin multiplexing registers
- +  * ----------------------------------------------------------------------------
- +  */
- + #define FUNC_MUX_CTRL_0		0xfffe1000
- + #define FUNC_MUX_CTRL_1		0xfffe1004
- + #define FUNC_MUX_CTRL_2		0xfffe1008
- + #define COMP_MODE_CTRL_0	0xfffe100c
- + #define FUNC_MUX_CTRL_3		0xfffe1010
- + #define FUNC_MUX_CTRL_4		0xfffe1014
- + #define FUNC_MUX_CTRL_5		0xfffe1018
- + #define FUNC_MUX_CTRL_6		0xfffe101C
- + #define FUNC_MUX_CTRL_7		0xfffe1020
- + #define FUNC_MUX_CTRL_8		0xfffe1024
- + #define FUNC_MUX_CTRL_9		0xfffe1028
- + #define FUNC_MUX_CTRL_A		0xfffe102C
- + #define FUNC_MUX_CTRL_B		0xfffe1030
- + #define FUNC_MUX_CTRL_C		0xfffe1034
- + #define FUNC_MUX_CTRL_D		0xfffe1038
- + #define PULL_DWN_CTRL_0		0xfffe1040
- + #define PULL_DWN_CTRL_1		0xfffe1044
- + #define PULL_DWN_CTRL_2		0xfffe1048
- + #define PULL_DWN_CTRL_3		0xfffe104c
- + #define PULL_DWN_CTRL_4		0xfffe10ac
- + 
- + /* OMAP-1610 specific multiplexing registers */
- + #define FUNC_MUX_CTRL_E		0xfffe1090
- + #define FUNC_MUX_CTRL_F		0xfffe1094
- + #define FUNC_MUX_CTRL_10	0xfffe1098
- + #define FUNC_MUX_CTRL_11	0xfffe109c
- + #define FUNC_MUX_CTRL_12	0xfffe10a0
- + #define PU_PD_SEL_0		0xfffe10b4
- + #define PU_PD_SEL_1		0xfffe10b8
- + #define PU_PD_SEL_2		0xfffe10bc
- + #define PU_PD_SEL_3		0xfffe10c0
- + #define PU_PD_SEL_4		0xfffe10c4
- + 
- + /* Timer32K for 1610 and 1710*/
- + #define OMAP_TIMER32K_BASE	0xFFFBC400
- + 
- + /*
- +  * ---------------------------------------------------------------------------
- +  * TIPB bus interface
- +  * ---------------------------------------------------------------------------
- +  */
- + #define TIPB_PUBLIC_CNTL_BASE		0xfffed300
- + #define MPU_PUBLIC_TIPB_CNTL		(TIPB_PUBLIC_CNTL_BASE + 0x8)
- + #define TIPB_PRIVATE_CNTL_BASE		0xfffeca00
- + #define MPU_PRIVATE_TIPB_CNTL		(TIPB_PRIVATE_CNTL_BASE + 0x8)
- + 
- + /*
- +  * ----------------------------------------------------------------------------
- +  * MPUI interface
- +  * ----------------------------------------------------------------------------
- +  */
- + #define MPUI_BASE			(0xfffec900)
- + #define MPUI_CTRL			(MPUI_BASE + 0x0)
- + #define MPUI_DEBUG_ADDR			(MPUI_BASE + 0x4)
- + #define MPUI_DEBUG_DATA			(MPUI_BASE + 0x8)
- + #define MPUI_DEBUG_FLAG			(MPUI_BASE + 0xc)
- + #define MPUI_STATUS_REG			(MPUI_BASE + 0x10)
- + #define MPUI_DSP_STATUS			(MPUI_BASE + 0x14)
- + #define MPUI_DSP_BOOT_CONFIG		(MPUI_BASE + 0x18)
- + #define MPUI_DSP_API_CONFIG		(MPUI_BASE + 0x1c)
- + 
- + /*
- +  * ----------------------------------------------------------------------------
- +  * LED Pulse Generator
- +  * ----------------------------------------------------------------------------
- +  */
- + #define OMAP_LPG1_BASE			0xfffbd000
- + #define OMAP_LPG2_BASE			0xfffbd800
- + #define OMAP_LPG1_LCR			(OMAP_LPG1_BASE + 0x00)
- + #define OMAP_LPG1_PMR			(OMAP_LPG1_BASE + 0x04)
- + #define OMAP_LPG2_LCR			(OMAP_LPG2_BASE + 0x00)
- + #define OMAP_LPG2_PMR			(OMAP_LPG2_BASE + 0x04)
- + 
- + /*
- +  * ----------------------------------------------------------------------------
- +  * Pulse-Width Light
- +  * ----------------------------------------------------------------------------
- +  */
- + #define OMAP_PWL_BASE			0xfffb5800
- + #define OMAP_PWL_ENABLE			(OMAP_PWL_BASE + 0x00)
- + #define OMAP_PWL_CLK_ENABLE		(OMAP_PWL_BASE + 0x04)
- + 
- + /*
- +  * ---------------------------------------------------------------------------
- +  * Processor specific defines
- +  * ---------------------------------------------------------------------------
- +  */
- + 
- + 
- + #include <plat/omap34xx.h>
- + //#include <plat/omap44xx.h>
- + #include <plat/am33xx.h>
- + 
- + #endif	/* __ASM_ARCH_OMAP_HARDWARE_H */
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/i2c.h linux-3.2.1/arch/arm/plat-ckb/include/plat/i2c.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/i2c.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/i2c.h	2014-05-15 13:25:14.127028930 +0900
- ***************
- *** 0 ****
- --- 1,59 ----
- + /*
- +  * Helper module for board specific I2C bus registration
- +  *
- +  * Copyright (C) 2009 Nokia Corporation.
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License
- +  * version 2 as published by the Free Software Foundation.
- +  *
- +  * This program is distributed in the hope that it will be useful, but
- +  * WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- +  * General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- +  * 02110-1301 USA
- +  *
- +  */
- + #ifndef __ASM__ARCH_OMAP_I2C_H
- + #define __ASM__ARCH_OMAP_I2C_H
- + 
- + #include <linux/i2c.h>
- + #include <linux/i2c-omap.h>
- + 
- + #if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
- + extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
- + 				 struct i2c_board_info const *info,
- + 				 unsigned len);
- + #else
- + static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
- + 				 struct i2c_board_info const *info,
- + 				 unsigned len)
- + {
- + 	return 0;
- + }
- + #endif
- + 
- + /**
- +  * i2c_dev_attr - OMAP I2C controller device attributes for omap_hwmod
- +  * @fifo_depth: total controller FIFO size (in bytes)
- +  * @flags: differences in hardware support capability
- +  *
- +  * @fifo_depth represents what exists on the hardware, not what is
- +  * actually configured at runtime by the device driver.
- +  */
- + struct omap_i2c_dev_attr {
- + 	u8	fifo_depth;
- + 	u32	flags;
- + };
- + 
- + void __init omap1_i2c_mux_pins(int bus_id);
- + void __init omap2_i2c_mux_pins(int bus_id);
- + 
- + struct omap_hwmod;
- + int omap_i2c_reset(struct omap_hwmod *oh);
- + 
- + #endif /* __ASM__ARCH_OMAP_I2C_H */
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/io.h linux-3.2.1/arch/arm/plat-ckb/include/plat/io.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/io.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/io.h	2014-05-15 13:25:14.127028930 +0900
- ***************
- *** 0 ****
- --- 1,117 ----
- + /*
- +  * arch/arm/plat-omap/include/mach/io.h
- +  *
- +  * IO definitions for TI OMAP processors and boards
- +  *
- +  * Copied from arch/arm/mach-sa1100/include/mach/io.h
- +  * Copyright (C) 1997-1999 Russell King
- +  *
- +  * Copyright (C) 2009 Texas Instruments
- +  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify it
- +  * under the terms of the GNU General Public License as published by the
- +  * Free Software Foundation; either version 2 of the License, or (at your
- +  * option) any later version.
- +  *
- +  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- +  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- +  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- +  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- +  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- +  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- +  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- +  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- +  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- +  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- +  *
- +  * You should have received a copy of the GNU General Public License along
- +  * with this program; if not, write to the Free Software Foundation, Inc.,
- +  * 675 Mass Ave, Cambridge, MA 02139, USA.
- +  *
- +  * Modifications:
- +  *  06-12-1997	RMK	Created.
- +  *  07-04-1999	RMK	Major cleanup
- +  */
- + 
- + #ifndef __ASM_ARM_ARCH_IO_H
- + #define __ASM_ARM_ARCH_IO_H
- + 
- + #include <mach/hardware.h>
- + 
- + #define IO_SPACE_LIMIT 0xffffffff
- + 
- + /*
- +  * We don't actually have real ISA nor PCI buses, but there is so many
- +  * drivers out there that might just work if we fake them...
- +  */
- + #define __io(a)		__typesafe_io(a)
- + #define __mem_pci(a)	(a)
- + 
- + /*
- +  * ----------------------------------------------------------------------------
- +  * I/O mapping
- +  * ----------------------------------------------------------------------------
- +  */
- + 
- + #ifdef __ASSEMBLER__
- + #define IOMEM(x)		(x)
- + #else
- + #define IOMEM(x)		((void __force __iomem *)(x))
- + #endif
- + 
- + #define OMAP2_L3_IO_OFFSET	0x90000000
- + #define OMAP2_L3_IO_ADDRESS(pa)	IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */
- + 
- + #define OMAP2_L4_IO_OFFSET	0xB7100000
- + #define OMAP2_L4_IO_ADDRESS(pa)	IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */
- + 
- + #define AM33XX_L4_WK_IO_OFFSET	0xBA900000
- + #define AM33XX_L4_WK_IO_ADDRESS(pa)	IOMEM((pa) + AM33XX_L4_WK_IO_OFFSET)
- + 
- + /*
- +  * ----------------------------------------------------------------------------
- +  * Omap3 specific IO mapping
- +  * ----------------------------------------------------------------------------
- +  */
- + #define L4_34XX_PHYS		L4_34XX_BASE	/* 0x48000000 --> 0xff100000 */
- + #define L4_34XX_VIRT		(L4_34XX_PHYS + OMAP2_L4_IO_OFFSET)
- + #define L4_34XX_SIZE		SZ_4M   /* 1MB of 128MB used, want 1MB sect */
- + 
- + /*
- +  * ----------------------------------------------------------------------------
- +  * AM33XX specific IO mapping
- +  * ----------------------------------------------------------------------------
- +  */
- + #define L4_WK_AM33XX_PHYS	L4_WK_AM33XX_BASE /* 0x44C00000 --> 0xff500000 */
- + #define L4_WK_AM33XX_VIRT	(L4_WK_AM33XX_PHYS + AM33XX_L4_WK_IO_OFFSET)
- + #define L4_WK_AM33XX_SIZE	SZ_4M   /* 1MB of 128MB used, want 1MB sect */
- + 
- + /*
- +  * ----------------------------------------------------------------------------
- +  * Omap specific register access
- +  * ----------------------------------------------------------------------------
- +  */
- + 
- + #ifndef __ASSEMBLER__
- + 
- + /*
- +  * NOTE: Please use ioremap + __raw_read/write where possible instead of these
- +  */
- + 
- + extern u8 omap_readb(u32 pa);
- + extern u16 omap_readw(u32 pa);
- + extern u32 omap_readl(u32 pa);
- + extern void omap_writeb(u8 v, u32 pa);
- + extern void omap_writew(u16 v, u32 pa);
- + extern void omap_writel(u32 v, u32 pa);
- + 
- + struct omap_sdrc_params;
- + extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
- + 				      struct omap_sdrc_params *sdrc_cs1);
- + 
- + extern void __init omap_init_consistent_dma_size(void);
- + 
- + #endif
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/iommu2.h linux-3.2.1/arch/arm/plat-ckb/include/plat/iommu2.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/iommu2.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/iommu2.h	2014-05-15 13:25:14.127028930 +0900
- ***************
- *** 0 ****
- --- 1,96 ----
- + /*
- +  * omap iommu: omap2 architecture specific definitions
- +  *
- +  * Copyright (C) 2008-2009 Nokia Corporation
- +  *
- +  * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #ifndef __MACH_IOMMU2_H
- + #define __MACH_IOMMU2_H
- + 
- + #include <linux/io.h>
- + 
- + /*
- +  * MMU Register offsets
- +  */
- + #define MMU_REVISION		0x00
- + #define MMU_SYSCONFIG		0x10
- + #define MMU_SYSSTATUS		0x14
- + #define MMU_IRQSTATUS		0x18
- + #define MMU_IRQENABLE		0x1c
- + #define MMU_WALKING_ST		0x40
- + #define MMU_CNTL		0x44
- + #define MMU_FAULT_AD		0x48
- + #define MMU_TTB			0x4c
- + #define MMU_LOCK		0x50
- + #define MMU_LD_TLB		0x54
- + #define MMU_CAM			0x58
- + #define MMU_RAM			0x5c
- + #define MMU_GFLUSH		0x60
- + #define MMU_FLUSH_ENTRY		0x64
- + #define MMU_READ_CAM		0x68
- + #define MMU_READ_RAM		0x6c
- + #define MMU_EMU_FAULT_AD	0x70
- + 
- + #define MMU_REG_SIZE		256
- + 
- + /*
- +  * MMU Register bit definitions
- +  */
- + #define MMU_LOCK_BASE_SHIFT	10
- + #define MMU_LOCK_BASE_MASK	(0x1f << MMU_LOCK_BASE_SHIFT)
- + #define MMU_LOCK_BASE(x)	\
- + 	((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT)
- + 
- + #define MMU_LOCK_VICT_SHIFT	4
- + #define MMU_LOCK_VICT_MASK	(0x1f << MMU_LOCK_VICT_SHIFT)
- + #define MMU_LOCK_VICT(x)	\
- + 	((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT)
- + 
- + #define MMU_CAM_VATAG_SHIFT	12
- + #define MMU_CAM_VATAG_MASK \
- + 	((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
- + #define MMU_CAM_P		(1 << 3)
- + #define MMU_CAM_V		(1 << 2)
- + #define MMU_CAM_PGSZ_MASK	3
- + #define MMU_CAM_PGSZ_1M		(0 << 0)
- + #define MMU_CAM_PGSZ_64K	(1 << 0)
- + #define MMU_CAM_PGSZ_4K		(2 << 0)
- + #define MMU_CAM_PGSZ_16M	(3 << 0)
- + 
- + #define MMU_RAM_PADDR_SHIFT	12
- + #define MMU_RAM_PADDR_MASK \
- + 	((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
- + #define MMU_RAM_ENDIAN_SHIFT	9
- + #define MMU_RAM_ENDIAN_MASK	(1 << MMU_RAM_ENDIAN_SHIFT)
- + #define MMU_RAM_ENDIAN_BIG	(1 << MMU_RAM_ENDIAN_SHIFT)
- + #define MMU_RAM_ENDIAN_LITTLE	(0 << MMU_RAM_ENDIAN_SHIFT)
- + #define MMU_RAM_ELSZ_SHIFT	7
- + #define MMU_RAM_ELSZ_MASK	(3 << MMU_RAM_ELSZ_SHIFT)
- + #define MMU_RAM_ELSZ_8		(0 << MMU_RAM_ELSZ_SHIFT)
- + #define MMU_RAM_ELSZ_16		(1 << MMU_RAM_ELSZ_SHIFT)
- + #define MMU_RAM_ELSZ_32		(2 << MMU_RAM_ELSZ_SHIFT)
- + #define MMU_RAM_ELSZ_NONE	(3 << MMU_RAM_ELSZ_SHIFT)
- + #define MMU_RAM_MIXED_SHIFT	6
- + #define MMU_RAM_MIXED_MASK	(1 << MMU_RAM_MIXED_SHIFT)
- + #define MMU_RAM_MIXED		MMU_RAM_MIXED_MASK
- + 
- + /*
- +  * register accessors
- +  */
- + static inline u32 iommu_read_reg(struct omap_iommu *obj, size_t offs)
- + {
- + 	return __raw_readl(obj->regbase + offs);
- + }
- + 
- + static inline void iommu_write_reg(struct omap_iommu *obj, u32 val, size_t offs)
- + {
- + 	__raw_writel(val, obj->regbase + offs);
- + }
- + 
- + #endif /* __MACH_IOMMU2_H */
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/iommu.h linux-3.2.1/arch/arm/plat-ckb/include/plat/iommu.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/iommu.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/iommu.h	2014-05-15 13:25:14.130677966 +0900
- ***************
- *** 0 ****
- --- 1,177 ----
- + /*
- +  * omap iommu: main structures
- +  *
- +  * Copyright (C) 2008-2009 Nokia Corporation
- +  *
- +  * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #ifndef __MACH_IOMMU_H
- + #define __MACH_IOMMU_H
- + 
- + struct iotlb_entry {
- + 	u32 da;
- + 	u32 pa;
- + 	u32 pgsz, prsvd, valid;
- + 	union {
- + 		u16 ap;
- + 		struct {
- + 			u32 endian, elsz, mixed;
- + 		};
- + 	};
- + };
- + 
- + struct omap_iommu {
- + 	const char	*name;
- + 	struct module	*owner;
- + 	struct clk	*clk;
- + 	void __iomem	*regbase;
- + 	struct device	*dev;
- + 	void		*isr_priv;
- + 	struct iommu_domain *domain;
- + 
- + 	unsigned int	refcount;
- + 	spinlock_t	iommu_lock;	/* global for this whole object */
- + 
- + 	/*
- + 	 * We don't change iopgd for a situation like pgd for a task,
- + 	 * but share it globally for each iommu.
- + 	 */
- + 	u32		*iopgd;
- + 	spinlock_t	page_table_lock; /* protect iopgd */
- + 
- + 	int		nr_tlb_entries;
- + 
- + 	struct list_head	mmap;
- + 	struct mutex		mmap_lock; /* protect mmap */
- + 
- + 	void *ctx; /* iommu context: registres saved area */
- + 	u32 da_start;
- + 	u32 da_end;
- + };
- + 
- + struct cr_regs {
- + 	union {
- + 		struct {
- + 			u16 cam_l;
- + 			u16 cam_h;
- + 		};
- + 		u32 cam;
- + 	};
- + 	union {
- + 		struct {
- + 			u16 ram_l;
- + 			u16 ram_h;
- + 		};
- + 		u32 ram;
- + 	};
- + };
- + 
- + struct iotlb_lock {
- + 	short base;
- + 	short vict;
- + };
- + 
- + /* architecture specific functions */
- + struct iommu_functions {
- + 	unsigned long	version;
- + 
- + 	int (*enable)(struct omap_iommu *obj);
- + 	void (*disable)(struct omap_iommu *obj);
- + 	void (*set_twl)(struct omap_iommu *obj, bool on);
- + 	u32 (*fault_isr)(struct omap_iommu *obj, u32 *ra);
- + 
- + 	void (*tlb_read_cr)(struct omap_iommu *obj, struct cr_regs *cr);
- + 	void (*tlb_load_cr)(struct omap_iommu *obj, struct cr_regs *cr);
- + 
- + 	struct cr_regs *(*alloc_cr)(struct omap_iommu *obj,
- + 							struct iotlb_entry *e);
- + 	int (*cr_valid)(struct cr_regs *cr);
- + 	u32 (*cr_to_virt)(struct cr_regs *cr);
- + 	void (*cr_to_e)(struct cr_regs *cr, struct iotlb_entry *e);
- + 	ssize_t (*dump_cr)(struct omap_iommu *obj, struct cr_regs *cr,
- + 							char *buf);
- + 
- + 	u32 (*get_pte_attr)(struct iotlb_entry *e);
- + 
- + 	void (*save_ctx)(struct omap_iommu *obj);
- + 	void (*restore_ctx)(struct omap_iommu *obj);
- + 	ssize_t (*dump_ctx)(struct omap_iommu *obj, char *buf, ssize_t len);
- + };
- + 
- + struct iommu_platform_data {
- + 	const char *name;
- + 	const char *clk_name;
- + 	const int nr_tlb_entries;
- + 	u32 da_start;
- + 	u32 da_end;
- + };
- + 
- + /* IOMMU errors */
- + #define OMAP_IOMMU_ERR_TLB_MISS		(1 << 0)
- + #define OMAP_IOMMU_ERR_TRANS_FAULT	(1 << 1)
- + #define OMAP_IOMMU_ERR_EMU_MISS		(1 << 2)
- + #define OMAP_IOMMU_ERR_TBLWALK_FAULT	(1 << 3)
- + #define OMAP_IOMMU_ERR_MULTIHIT_FAULT	(1 << 4)
- + 
- + #include <plat/iommu2.h>
- + 
- + /*
- +  * utilities for super page(16MB, 1MB, 64KB and 4KB)
- +  */
- + 
- + #define iopgsz_max(bytes)			\
- + 	(((bytes) >= SZ_16M) ? SZ_16M :		\
- + 	 ((bytes) >= SZ_1M)  ? SZ_1M  :		\
- + 	 ((bytes) >= SZ_64K) ? SZ_64K :		\
- + 	 ((bytes) >= SZ_4K)  ? SZ_4K  :	0)
- + 
- + #define bytes_to_iopgsz(bytes)				\
- + 	(((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M :	\
- + 	 ((bytes) == SZ_1M)  ? MMU_CAM_PGSZ_1M  :	\
- + 	 ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K :	\
- + 	 ((bytes) == SZ_4K)  ? MMU_CAM_PGSZ_4K  : -1)
- + 
- + #define iopgsz_to_bytes(iopgsz)				\
- + 	(((iopgsz) == MMU_CAM_PGSZ_16M)	? SZ_16M :	\
- + 	 ((iopgsz) == MMU_CAM_PGSZ_1M)	? SZ_1M  :	\
- + 	 ((iopgsz) == MMU_CAM_PGSZ_64K)	? SZ_64K :	\
- + 	 ((iopgsz) == MMU_CAM_PGSZ_4K)	? SZ_4K  : 0)
- + 
- + #define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)
- + 
- + /*
- +  * global functions
- +  */
- + extern u32 omap_iommu_arch_version(void);
- + 
- + extern void omap_iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e);
- + 
- + extern int
- + omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e);
- + 
- + extern int omap_iommu_set_isr(const char *name,
- + 		 int (*isr)(struct omap_iommu *obj, u32 da, u32 iommu_errs,
- + 				    void *priv),
- + 			 void *isr_priv);
- + 
- + extern void omap_iommu_save_ctx(struct omap_iommu *obj);
- + extern void omap_iommu_restore_ctx(struct omap_iommu *obj);
- + 
- + extern int omap_install_iommu_arch(const struct iommu_functions *ops);
- + extern void omap_uninstall_iommu_arch(const struct iommu_functions *ops);
- + 
- + extern int omap_foreach_iommu_device(void *data,
- + 				int (*fn)(struct device *, void *));
- + 
- + extern ssize_t
- + omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t len);
- + extern size_t
- + omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t len);
- + struct device *omap_find_iommu_device(const char *name);
- + 
- + #endif /* __MACH_IOMMU_H */
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/iopgtable.h linux-3.2.1/arch/arm/plat-ckb/include/plat/iopgtable.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/iopgtable.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/iopgtable.h	2014-05-15 13:25:14.130677966 +0900
- ***************
- *** 0 ****
- --- 1,120 ----
- + /*
- +  * omap iommu: pagetable definitions
- +  *
- +  * Copyright (C) 2008-2010 Nokia Corporation
- +  *
- +  * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #ifndef __PLAT_OMAP_IOMMU_H
- + #define __PLAT_OMAP_IOMMU_H
- + 
- + /*
- +  * "L2 table" address mask and size definitions.
- +  */
- + #define IOPGD_SHIFT		20
- + #define IOPGD_SIZE		(1UL << IOPGD_SHIFT)
- + #define IOPGD_MASK		(~(IOPGD_SIZE - 1))
- + 
- + /*
- +  * "section" address mask and size definitions.
- +  */
- + #define IOSECTION_SHIFT		20
- + #define IOSECTION_SIZE		(1UL << IOSECTION_SHIFT)
- + #define IOSECTION_MASK		(~(IOSECTION_SIZE - 1))
- + 
- + /*
- +  * "supersection" address mask and size definitions.
- +  */
- + #define IOSUPER_SHIFT		24
- + #define IOSUPER_SIZE		(1UL << IOSUPER_SHIFT)
- + #define IOSUPER_MASK		(~(IOSUPER_SIZE - 1))
- + 
- + #define PTRS_PER_IOPGD		(1UL << (32 - IOPGD_SHIFT))
- + #define IOPGD_TABLE_SIZE	(PTRS_PER_IOPGD * sizeof(u32))
- + 
- + /*
- +  * "small page" address mask and size definitions.
- +  */
- + #define IOPTE_SHIFT		12
- + #define IOPTE_SIZE		(1UL << IOPTE_SHIFT)
- + #define IOPTE_MASK		(~(IOPTE_SIZE - 1))
- + 
- + /*
- +  * "large page" address mask and size definitions.
- +  */
- + #define IOLARGE_SHIFT		16
- + #define IOLARGE_SIZE		(1UL << IOLARGE_SHIFT)
- + #define IOLARGE_MASK		(~(IOLARGE_SIZE - 1))
- + 
- + #define PTRS_PER_IOPTE		(1UL << (IOPGD_SHIFT - IOPTE_SHIFT))
- + #define IOPTE_TABLE_SIZE	(PTRS_PER_IOPTE * sizeof(u32))
- + 
- + #define IOPAGE_MASK		IOPTE_MASK
- + 
- + /**
- +  * omap_iommu_translate() - va to pa translation
- +  * @d:		omap iommu descriptor
- +  * @va:		virtual address
- +  * @mask:	omap iommu descriptor mask
- +  *
- +  * va to pa translation
- +  */
- + static inline phys_addr_t omap_iommu_translate(u32 d, u32 va, u32 mask)
- + {
- + 	return (d & mask) | (va & (~mask));
- + }
- + 
- + /*
- +  * some descriptor attributes.
- +  */
- + #define IOPGD_TABLE		(1 << 0)
- + #define IOPGD_SECTION		(2 << 0)
- + #define IOPGD_SUPER		(1 << 18 | 2 << 0)
- + 
- + #define iopgd_is_table(x)	(((x) & 3) == IOPGD_TABLE)
- + #define iopgd_is_section(x)	(((x) & (1 << 18 | 3)) == IOPGD_SECTION)
- + #define iopgd_is_super(x)	(((x) & (1 << 18 | 3)) == IOPGD_SUPER)
- + 
- + #define IOPTE_SMALL		(2 << 0)
- + #define IOPTE_LARGE		(1 << 0)
- + 
- + #define iopte_is_small(x)	(((x) & 2) == IOPTE_SMALL)
- + #define iopte_is_large(x)	(((x) & 3) == IOPTE_LARGE)
- + 
- + /* to find an entry in a page-table-directory */
- + #define iopgd_index(da)		(((da) >> IOPGD_SHIFT) & (PTRS_PER_IOPGD - 1))
- + #define iopgd_offset(obj, da)	((obj)->iopgd + iopgd_index(da))
- + 
- + #define iopgd_page_paddr(iopgd)	(*iopgd & ~((1 << 10) - 1))
- + #define iopgd_page_vaddr(iopgd)	((u32 *)phys_to_virt(iopgd_page_paddr(iopgd)))
- + 
- + /* to find an entry in the second-level page table. */
- + #define iopte_index(da)		(((da) >> IOPTE_SHIFT) & (PTRS_PER_IOPTE - 1))
- + #define iopte_offset(iopgd, da)	(iopgd_page_vaddr(iopgd) + iopte_index(da))
- + 
- + static inline u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa,
- + 				   u32 flags)
- + {
- + 	memset(e, 0, sizeof(*e));
- + 
- + 	e->da		= da;
- + 	e->pa		= pa;
- + 	e->valid	= 1;
- + 	/* FIXME: add OMAP1 support */
- + 	e->pgsz		= flags & MMU_CAM_PGSZ_MASK;
- + 	e->endian	= flags & MMU_RAM_ENDIAN_MASK;
- + 	e->elsz		= flags & MMU_RAM_ELSZ_MASK;
- + 	e->mixed	= flags & MMU_RAM_MIXED_MASK;
- + 
- + 	return iopgsz_to_bytes(e->pgsz);
- + }
- + 
- + #define to_iommu(dev)							\
- + 	(struct omap_iommu *)platform_get_drvdata(to_platform_device(dev))
- + 
- + #endif /* __PLAT_OMAP_IOMMU_H */
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/iovmm.h linux-3.2.1/arch/arm/plat-ckb/include/plat/iovmm.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/iovmm.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/iovmm.h	2014-05-15 13:25:14.130677966 +0900
- ***************
- *** 0 ****
- --- 1,89 ----
- + /*
- +  * omap iommu: simple virtual address space management
- +  *
- +  * Copyright (C) 2008-2009 Nokia Corporation
- +  *
- +  * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #ifndef __IOMMU_MMAP_H
- + #define __IOMMU_MMAP_H
- + 
- + #include <linux/iommu.h>
- + 
- + struct iovm_struct {
- + 	struct omap_iommu	*iommu;	/* iommu object which this belongs to */
- + 	u32			da_start; /* area definition */
- + 	u32			da_end;
- + 	u32			flags; /* IOVMF_: see below */
- + 	struct list_head	list; /* linked in ascending order */
- + 	const struct sg_table	*sgt; /* keep 'page' <-> 'da' mapping */
- + 	void			*va; /* mpu side mapped address */
- + };
- + 
- + /*
- +  * IOVMF_FLAGS: attribute for iommu virtual memory area(iovma)
- +  *
- +  * lower 16 bit is used for h/w and upper 16 bit is for s/w.
- +  */
- + #define IOVMF_SW_SHIFT		16
- + 
- + /*
- +  * iovma: h/w flags derived from cam and ram attribute
- +  */
- + #define IOVMF_CAM_MASK		(~((1 << 10) - 1))
- + #define IOVMF_RAM_MASK		(~IOVMF_CAM_MASK)
- + 
- + #define IOVMF_PGSZ_MASK		(3 << 0)
- + #define IOVMF_PGSZ_1M		MMU_CAM_PGSZ_1M
- + #define IOVMF_PGSZ_64K		MMU_CAM_PGSZ_64K
- + #define IOVMF_PGSZ_4K		MMU_CAM_PGSZ_4K
- + #define IOVMF_PGSZ_16M		MMU_CAM_PGSZ_16M
- + 
- + #define IOVMF_ENDIAN_MASK	(1 << 9)
- + #define IOVMF_ENDIAN_BIG	MMU_RAM_ENDIAN_BIG
- + #define IOVMF_ENDIAN_LITTLE	MMU_RAM_ENDIAN_LITTLE
- + 
- + #define IOVMF_ELSZ_MASK		(3 << 7)
- + #define IOVMF_ELSZ_8		MMU_RAM_ELSZ_8
- + #define IOVMF_ELSZ_16		MMU_RAM_ELSZ_16
- + #define IOVMF_ELSZ_32		MMU_RAM_ELSZ_32
- + #define IOVMF_ELSZ_NONE		MMU_RAM_ELSZ_NONE
- + 
- + #define IOVMF_MIXED_MASK	(1 << 6)
- + #define IOVMF_MIXED		MMU_RAM_MIXED
- + 
- + /*
- +  * iovma: s/w flags, used for mapping and umapping internally.
- +  */
- + #define IOVMF_MMIO		(1 << IOVMF_SW_SHIFT)
- + #define IOVMF_ALLOC		(2 << IOVMF_SW_SHIFT)
- + #define IOVMF_ALLOC_MASK	(3 << IOVMF_SW_SHIFT)
- + 
- + /* "superpages" is supported just with physically linear pages */
- + #define IOVMF_DISCONT		(1 << (2 + IOVMF_SW_SHIFT))
- + #define IOVMF_LINEAR		(2 << (2 + IOVMF_SW_SHIFT))
- + #define IOVMF_LINEAR_MASK	(3 << (2 + IOVMF_SW_SHIFT))
- + 
- + #define IOVMF_DA_FIXED		(1 << (4 + IOVMF_SW_SHIFT))
- + 
- + 
- + extern struct iovm_struct *omap_find_iovm_area(struct omap_iommu *obj, u32 da);
- + extern u32
- + omap_iommu_vmap(struct iommu_domain *domain, struct omap_iommu *obj, u32 da,
- + 			const struct sg_table *sgt, u32 flags);
- + extern struct sg_table *omap_iommu_vunmap(struct iommu_domain *domain,
- + 				struct omap_iommu *obj, u32 da);
- + extern u32
- + omap_iommu_vmalloc(struct iommu_domain *domain, struct omap_iommu *obj,
- + 				u32 da, size_t bytes, u32 flags);
- + extern void
- + omap_iommu_vfree(struct iommu_domain *domain, struct omap_iommu *obj,
- + 				const u32 da);
- + extern void *omap_da_to_va(struct omap_iommu *obj, u32 da);
- + 
- + #endif /* __IOMMU_MMAP_H */
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/irqs-33xx.h linux-3.2.1/arch/arm/plat-ckb/include/plat/irqs-33xx.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/irqs-33xx.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/irqs-33xx.h	2014-05-15 13:25:14.130677966 +0900
- ***************
- *** 0 ****
- --- 1,143 ----
- + /*
- +  * AM33XX interrupts.
- +  *
- +  * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #ifndef __ARCH_ARM_MACH_OMAP2_AM33XX_IRQS_H
- + #define __ARCH_ARM_MACH_OMAP2_AM33XX_IRQS_H
- + 
- + 
- + #define AM33XX_IRQ_ELM			4
- + #define AM33XX_IRQ_PI_NMI		7
- + #define AM33XX_IRQ_CONTROL_PLATFORM	8
- + #define AM33XX_IRQ_L3_FLAGMUX0		9
- + #define AM33XX_IRQ_L3_FLAGMUX1		10
- + #define AM33XX_IRQ_PRCM			11
- + #define AM33XX_IRQ_TPCC0_INT_PO0	12
- + #define AM33XX_IRQ_TPCC0_MPINT_PO	13
- + #define AM33XX_IRQ_TPCC0_ERRINT_PO	14
- + #define AM33XX_IRQ_WDT0			15
- + #define AM33XX_IRQ_ADC_GEN		16
- + #define AM33XX_IRQ_USBSS		17
- + #define AM33XX_IRQ_USB0			18
- + #define AM33XX_IRQ_USB1			19
- + #define AM33XX_IRQ_ICSS0_0		20
- + #define AM33XX_IRQ_ICSS0_1		21
- + #define AM33XX_IRQ_ICSS0_2		22
- + #define AM33XX_IRQ_ICSS0_3		23
- + #define AM33XX_IRQ_ICSS0_4		24
- + #define AM33XX_IRQ_ICSS0_5		25
- + #define AM33XX_IRQ_ICSS0_6		26
- + #define AM33XX_IRQ_ICSS0_7		27
- + #define AM33XX_IRQ_MMCHS1		28
- + #define AM33XX_IRQ_MMCHS2		29
- + #define AM33XX_IRQ_MSHSI2COCP2		30
- + #define AM33XX_IRQ_PWMSS0_ECAP		31
- + #define AM33XX_IRQ_GPIO2_1		32
- + #define AM33XX_IRQ_GPIO2_2		33
- + #define AM33XX_IRQ_USB_P		34
- + #define AM33XX_IRQ_PCI_SLV		35
- + #define AM33XX_IRQ_LCD			36
- + #define AM33XX_IRQ_THALIAIRQ		37
- + #define AM33XX_IRQ_BB_2DHWA		38
- + #define AM33XX_IRQ_PWMSS2_EPWM		39
- + #define AM33XX_IRQ_CPSW_C0_RX		40
- + #define AM33XX_IRQ_CPSW_RX		41
- + #define AM33XX_IRQ_CPSW_TX		42
- + #define AM33XX_IRQ_CPSW_C0		43
- + #define AM33XX_IRQ_UART3		44
- + #define AM33XX_IRQ_UART4		45
- + #define AM33XX_IRQ_UART5		46
- + #define AM33XX_IRQ_PWMSS1_ECAP		47
- + #define AM33XX_IRQ_PCI0			48
- + #define AM33XX_IRQ_PCI1			49
- + #define AM33XX_IRQ_PCI2			50
- + #define AM33XX_IRQ_PCI3			51
- + #define AM33XX_IRQ_DCAN0_0		52
- + #define AM33XX_IRQ_DCAN0_1		53
- + #define AM33XX_IRQ_DCAN0_UERR		54
- + #define AM33XX_IRQ_DCAN1_0		55
- + #define AM33XX_IRQ_DCAN1_1		56
- + #define AM33XX_IRQ_DCAN1_UERR		57
- + #define AM33XX_IRQ_PWMSS0		58
- + #define AM33XX_IRQ_PWMSS1		59
- + #define AM33XX_IRQ_PWMSS2		60
- + #define AM33XX_IRQ_PWMSS2_ECAP		61
- + #define AM33XX_IRQ_GPIO3_1		62
- + #define AM33XX_IRQ_GPIO3_2		63
- + #define AM33XX_IRQ_MMCHS0		64
- + #define AM33XX_IRQ_MCSPIOCP0		65
- + #define AM33XX_IRQ_DMTIMER0		66
- + #define AM33XX_IRQ_DMTIMER1		67
- + #define AM33XX_IRQ_DMTIMER2		68
- + #define AM33XX_IRQ_DMTIMER3		69
- + #define AM33XX_IRQ_MSHSI2COCP0		70
- + #define AM33XX_IRQ_MSHSI2COCP1		71
- + #define AM33XX_IRQ_UART0		72
- + #define AM33XX_IRQ_UART1		73
- + #define AM33XX_IRQ_UART2		74
- + #define AM33XX_IRQ_RTC_TIMER		75
- + #define AM33XX_IRQ_RTC_ALARM		76
- + #define AM33XX_IRQ_MAILBOX		77
- + #define AM33XX_IRQ_M3_M3SP_TXEV		78
- + #define AM33XX_IRQ_PWMSS0_EQEP		79
- + #define AM33XX_IRQ_MCASP0_AX		80
- + #define AM33XX_IRQ_MCASP0_AR		81
- + #define AM33XX_IRQ_MCASP1_AX		82
- + #define AM33XX_IRQ_MCASP1_AR		83
- + #define AM33XX_IRQ_MCASP2_X		84
- + #define AM33XX_IRQ_MCASP2_R		85
- + #define AM33XX_IRQ_PWMSS0_EPWM		86
- + #define AM33XX_IRQ_PWMSS1_EPWM		87
- + #define AM33XX_IRQ_PWMSS1_EQEP		88
- + #define AM33XX_IRQ_PWMSS2_EQEP		89
- + #define AM33XX_IRQ_DMA			90
- + #define AM33XX_IRQ_WDT1			91
- + #define AM33XX_IRQ_DMTIMER4		92
- + #define AM33XX_IRQ_DMTIMER5		93
- + #define AM33XX_IRQ_DMTIMER6		94
- + #define AM33XX_IRQ_DMTIMER7		95
- + #define AM33XX_IRQ_GPIO0_1		96
- + #define AM33XX_IRQ_GPIO0_2		97
- + #define AM33XX_IRQ_GPIO1_1		98
- + #define AM33XX_IRQ_GPIO1_2		99
- + #define AM33XX_IRQ_GPMC0		100
- + #define AM33XX_IRQ_EMI			101
- + #define AM33XX_IRQ_AESEIP36t0_S		102
- + #define AM33XX_IRQ_AESEIP36t0_P		103
- + #define AM33XX_IRQ_AESEIP36t1_S		104
- + #define AM33XX_IRQ_AESEIP36t1_P		105
- + #define AM33XX_IRQ_DESEIP16t0_S		106
- + #define AM33XX_IRQ_DESEIP16t0_P		107
- + #define AM33XX_IRQ_SHAEIP57t0_S		108
- + #define AM33XX_IRQ_SHAEIP57t0_P		109
- + #define AM33XX_IRQ_PKAEIP29t0_S		110
- + #define AM33XX_IRQ_RNGEIP75t0		111
- + #define AM33XX_IRQ_TPTC0		112
- + #define AM33XX_IRQ_TPTC1		113
- + #define AM33XX_IRQ_TPTC2		114
- + #define AM33XX_IRQ_TSC			115
- + #define AM33XX_IRQ_SDMA0		116
- + #define AM33XX_IRQ_SDMA1		117
- + #define AM33XX_IRQ_SDMA2		118
- + #define AM33XX_IRQ_SDMA3		119
- + #define AM33XX_IRQ_SMARTREFLEX0		120
- + #define AM33XX_IRQ_SMARTREFLEX1		121
- + #define AM33XX_IRQ_NETRA_MMU		122
- + #define AM33XX_IRQ_DMA0			123
- + #define AM33XX_IRQ_DMA1			124
- + #define AM33XX_IRQ_SPI1			125
- + #define AM33XX_IRQ_SPI2			126
- + #define AM33XX_IRQ_SPI			127
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/irqs.h linux-3.2.1/arch/arm/plat-ckb/include/plat/irqs.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/irqs.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/irqs.h	2014-05-15 13:25:14.134646030 +0900
- ***************
- *** 0 ****
- --- 1,367 ----
- + /*
- +  *  arch/arm/plat-omap/include/mach/irqs.h
- +  *
- +  *  Copyright (C) Greg Lonnon 2001
- +  *  Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
- +  *
- +  * Copyright (C) 2009 Texas Instruments
- +  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; either version 2 of the License, or
- +  * (at your option) any later version.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- +  *
- +  * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610
- +  *	 are different.
- +  */
- + 
- + #ifndef __ASM_ARCH_OMAP15XX_IRQS_H
- + #define __ASM_ARCH_OMAP15XX_IRQS_H
- + 
- + #include "irqs-33xx.h"
- + 
- + /*
- +  * IRQ numbers for interrupt handler 1
- +  *
- +  * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
- +  *
- +  */
- + #define INT_CAMERA		1
- + #define INT_FIQ			3
- + #define INT_RTDX		6
- + #define INT_DSP_MMU_ABORT	7
- + #define INT_HOST		8
- + #define INT_ABORT		9
- + #define INT_BRIDGE_PRIV		13
- + #define INT_GPIO_BANK1		14
- + #define INT_UART3		15
- + #define INT_TIMER3		16
- + #define INT_DMA_CH0_6		19
- + #define INT_DMA_CH1_7		20
- + #define INT_DMA_CH2_8		21
- + #define INT_DMA_CH3		22
- + #define INT_DMA_CH4		23
- + #define INT_DMA_CH5		24
- + #define INT_DMA_LCD		25
- + #define INT_TIMER1		26
- + #define INT_WD_TIMER		27
- + #define INT_BRIDGE_PUB		28
- + #define INT_TIMER2		30
- + #define INT_LCD_CTRL		31
- + 
- + /*
- +  * OMAP-1510 specific IRQ numbers for interrupt handler 1
- +  */
- + #define INT_1510_IH2_IRQ	0
- + #define INT_1510_RES2		2
- + #define INT_1510_SPI_TX		4
- + #define INT_1510_SPI_RX		5
- + #define INT_1510_DSP_MAILBOX1	10
- + #define INT_1510_DSP_MAILBOX2	11
- + #define INT_1510_RES12		12
- + #define INT_1510_LB_MMU		17
- + #define INT_1510_RES18		18
- + #define INT_1510_LOCAL_BUS	29
- + 
- + 
- + /*
- +  * IRQ numbers for interrupt handler 2
- +  *
- +  * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
- +  */
- + #define IH2_BASE		32
- + 
- + #define INT_KEYBOARD		(1 + IH2_BASE)
- + #define INT_uWireTX		(2 + IH2_BASE)
- + #define INT_uWireRX		(3 + IH2_BASE)
- + #define INT_I2C			(4 + IH2_BASE)
- + #define INT_MPUIO		(5 + IH2_BASE)
- + #define INT_USB_HHC_1		(6 + IH2_BASE)
- + #define INT_McBSP3TX		(10 + IH2_BASE)
- + #define INT_McBSP3RX		(11 + IH2_BASE)
- + #define INT_McBSP1TX		(12 + IH2_BASE)
- + #define INT_McBSP1RX		(13 + IH2_BASE)
- + #define INT_UART1		(14 + IH2_BASE)
- + #define INT_UART2		(15 + IH2_BASE)
- + #define INT_BT_MCSI1TX		(16 + IH2_BASE)
- + #define INT_BT_MCSI1RX		(17 + IH2_BASE)
- + #define INT_SOSSI_MATCH		(19 + IH2_BASE)
- + #define INT_USB_W2FC		(20 + IH2_BASE)
- + #define INT_1WIRE		(21 + IH2_BASE)
- + #define INT_OS_TIMER		(22 + IH2_BASE)
- + #define INT_MMC			(23 + IH2_BASE)
- + #define INT_GAUGE_32K		(24 + IH2_BASE)
- + #define INT_RTC_TIMER		(25 + IH2_BASE)
- + #define INT_RTC_ALARM		(26 + IH2_BASE)
- + #define INT_MEM_STICK		(27 + IH2_BASE)
- + 
- + /*
- +  * OMAP-1510 specific IRQ numbers for interrupt handler 2
- +  */
- + #define INT_1510_DSP_MMU	(28 + IH2_BASE)
- + #define INT_1510_COM_SPI_RO	(31 + IH2_BASE)
- + 
- + /*
- +  * OMAP-1610 specific IRQ numbers for interrupt handler 2
- +  */
- + #define INT_1610_FAC		(0 + IH2_BASE)
- + #define INT_1610_USB_HHC_2	(7 + IH2_BASE)
- + #define INT_1610_USB_OTG	(8 + IH2_BASE)
- + #define INT_1610_SoSSI		(9 + IH2_BASE)
- + #define INT_1610_SoSSI_MATCH	(19 + IH2_BASE)
- + #define INT_1610_DSP_MMU	(28 + IH2_BASE)
- + #define INT_1610_McBSP2RX_OF	(31 + IH2_BASE)
- + #define INT_1610_STI		(32 + IH2_BASE)
- + #define INT_1610_STI_WAKEUP	(33 + IH2_BASE)
- + #define INT_1610_GPTIMER3	(34 + IH2_BASE)
- + #define INT_1610_GPTIMER4	(35 + IH2_BASE)
- + #define INT_1610_GPTIMER5	(36 + IH2_BASE)
- + #define INT_1610_GPTIMER6	(37 + IH2_BASE)
- + #define INT_1610_GPTIMER7	(38 + IH2_BASE)
- + #define INT_1610_GPTIMER8	(39 + IH2_BASE)
- + #define INT_1610_GPIO_BANK2	(40 + IH2_BASE)
- + #define INT_1610_GPIO_BANK3	(41 + IH2_BASE)
- + #define INT_1610_MMC2		(42 + IH2_BASE)
- + #define INT_1610_CF		(43 + IH2_BASE)
- + #define INT_1610_WAKE_UP_REQ	(46 + IH2_BASE)
- + #define INT_1610_GPIO_BANK4	(48 + IH2_BASE)
- + #define INT_1610_SPI		(49 + IH2_BASE)
- + #define INT_1610_DMA_CH6	(53 + IH2_BASE)
- + #define INT_1610_DMA_CH7	(54 + IH2_BASE)
- + #define INT_1610_DMA_CH8	(55 + IH2_BASE)
- + #define INT_1610_DMA_CH9	(56 + IH2_BASE)
- + #define INT_1610_DMA_CH10	(57 + IH2_BASE)
- + #define INT_1610_DMA_CH11	(58 + IH2_BASE)
- + #define INT_1610_DMA_CH12	(59 + IH2_BASE)
- + #define INT_1610_DMA_CH13	(60 + IH2_BASE)
- + #define INT_1610_DMA_CH14	(61 + IH2_BASE)
- + #define INT_1610_DMA_CH15	(62 + IH2_BASE)
- + #define INT_1610_NAND		(63 + IH2_BASE)
- + #define INT_1610_SHA1MD5	(91 + IH2_BASE)
- + 
- + /*
- +  * OMAP-7xx specific IRQ numbers for interrupt handler 2
- +  */
- + #define INT_7XX_HW_ERRORS	(0 + IH2_BASE)
- + #define INT_7XX_NFIQ_PWR_FAIL	(1 + IH2_BASE)
- + #define INT_7XX_CFCD		(2 + IH2_BASE)
- + #define INT_7XX_CFIREQ		(3 + IH2_BASE)
- + #define INT_7XX_I2C		(4 + IH2_BASE)
- + #define INT_7XX_PCC		(5 + IH2_BASE)
- + #define INT_7XX_MPU_EXT_NIRQ	(6 + IH2_BASE)
- + #define INT_7XX_SPI_100K_1	(7 + IH2_BASE)
- + #define INT_7XX_SYREN_SPI	(8 + IH2_BASE)
- + #define INT_7XX_VLYNQ		(9 + IH2_BASE)
- + #define INT_7XX_GPIO_BANK4	(10 + IH2_BASE)
- + #define INT_7XX_McBSP1TX	(11 + IH2_BASE)
- + #define INT_7XX_McBSP1RX	(12 + IH2_BASE)
- + #define INT_7XX_McBSP1RX_OF	(13 + IH2_BASE)
- + #define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE)
- + #define INT_7XX_UART_MODEM_1	(15 + IH2_BASE)
- + #define INT_7XX_MCSI		(16 + IH2_BASE)
- + #define INT_7XX_uWireTX		(17 + IH2_BASE)
- + #define INT_7XX_uWireRX		(18 + IH2_BASE)
- + #define INT_7XX_SMC_CD		(19 + IH2_BASE)
- + #define INT_7XX_SMC_IREQ	(20 + IH2_BASE)
- + #define INT_7XX_HDQ_1WIRE	(21 + IH2_BASE)
- + #define INT_7XX_TIMER32K	(22 + IH2_BASE)
- + #define INT_7XX_MMC_SDIO	(23 + IH2_BASE)
- + #define INT_7XX_UPLD		(24 + IH2_BASE)
- + #define INT_7XX_USB_HHC_1	(27 + IH2_BASE)
- + #define INT_7XX_USB_HHC_2	(28 + IH2_BASE)
- + #define INT_7XX_USB_GENI	(29 + IH2_BASE)
- + #define INT_7XX_USB_OTG		(30 + IH2_BASE)
- + #define INT_7XX_CAMERA_IF	(31 + IH2_BASE)
- + #define INT_7XX_RNG		(32 + IH2_BASE)
- + #define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE)
- + #define INT_7XX_DBB_RF_EN	(34 + IH2_BASE)
- + #define INT_7XX_MPUIO_KEYPAD	(35 + IH2_BASE)
- + #define INT_7XX_SHA1_MD5	(36 + IH2_BASE)
- + #define INT_7XX_SPI_100K_2	(37 + IH2_BASE)
- + #define INT_7XX_RNG_IDLE	(38 + IH2_BASE)
- + #define INT_7XX_MPUIO		(39 + IH2_BASE)
- + #define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF	(40 + IH2_BASE)
- + #define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE)
- + #define INT_7XX_LLPC_OE_RISING	(42 + IH2_BASE)
- + #define INT_7XX_LLPC_VSYNC	(43 + IH2_BASE)
- + #define INT_7XX_WAKE_UP_REQ	(46 + IH2_BASE)
- + #define INT_7XX_DMA_CH6		(53 + IH2_BASE)
- + #define INT_7XX_DMA_CH7		(54 + IH2_BASE)
- + #define INT_7XX_DMA_CH8		(55 + IH2_BASE)
- + #define INT_7XX_DMA_CH9		(56 + IH2_BASE)
- + #define INT_7XX_DMA_CH10	(57 + IH2_BASE)
- + #define INT_7XX_DMA_CH11	(58 + IH2_BASE)
- + #define INT_7XX_DMA_CH12	(59 + IH2_BASE)
- + #define INT_7XX_DMA_CH13	(60 + IH2_BASE)
- + #define INT_7XX_DMA_CH14	(61 + IH2_BASE)
- + #define INT_7XX_DMA_CH15	(62 + IH2_BASE)
- + #define INT_7XX_NAND		(63 + IH2_BASE)
- + 
- + #define INT_24XX_SYS_NIRQ	7
- + #define INT_24XX_SDMA_IRQ0	12
- + #define INT_24XX_SDMA_IRQ1	13
- + #define INT_24XX_SDMA_IRQ2	14
- + #define INT_24XX_SDMA_IRQ3	15
- + #define INT_24XX_CAM_IRQ	24
- + #define INT_24XX_DSS_IRQ	25
- + #define INT_24XX_MAIL_U0_MPU	26
- + #define INT_24XX_DSP_UMA	27
- + #define INT_24XX_DSP_MMU	28
- + #define INT_24XX_GPIO_BANK1	29
- + #define INT_24XX_GPIO_BANK2	30
- + #define INT_24XX_GPIO_BANK3	31
- + #define INT_24XX_GPIO_BANK4	32
- + #define INT_24XX_GPIO_BANK5	33
- + #define INT_24XX_MAIL_U3_MPU	34
- + #define INT_24XX_GPTIMER1	37
- + #define INT_24XX_GPTIMER2	38
- + #define INT_24XX_GPTIMER3	39
- + #define INT_24XX_GPTIMER4	40
- + #define INT_24XX_GPTIMER5	41
- + #define INT_24XX_GPTIMER6	42
- + #define INT_24XX_GPTIMER7	43
- + #define INT_24XX_GPTIMER8	44
- + #define INT_24XX_GPTIMER9	45
- + #define INT_24XX_GPTIMER10	46
- + #define INT_24XX_GPTIMER11	47
- + #define INT_24XX_GPTIMER12	48
- + #define INT_24XX_SHA1MD5	51
- + #define INT_24XX_MCBSP4_IRQ_TX	54
- + #define INT_24XX_MCBSP4_IRQ_RX	55
- + #define INT_24XX_I2C1_IRQ	56
- + #define INT_24XX_I2C2_IRQ	57
- + #define INT_24XX_HDQ_IRQ	58
- + #define INT_24XX_MCBSP1_IRQ_TX	59
- + #define INT_24XX_MCBSP1_IRQ_RX	60
- + #define INT_24XX_MCBSP2_IRQ_TX	62
- + #define INT_24XX_MCBSP2_IRQ_RX	63
- + #define INT_24XX_SPI1_IRQ	65
- + #define INT_24XX_SPI2_IRQ	66
- + #define INT_24XX_UART1_IRQ	72
- + #define INT_24XX_UART2_IRQ	73
- + #define INT_24XX_UART3_IRQ	74
- + #define INT_24XX_USB_IRQ_GEN	75
- + #define INT_24XX_USB_IRQ_NISO	76
- + #define INT_24XX_USB_IRQ_ISO	77
- + #define INT_24XX_USB_IRQ_HGEN	78
- + #define INT_24XX_USB_IRQ_HSOF	79
- + #define INT_24XX_USB_IRQ_OTG	80
- + #define INT_24XX_MCBSP5_IRQ_TX	81
- + #define INT_24XX_MCBSP5_IRQ_RX	82
- + #define INT_24XX_MMC_IRQ	83
- + #define INT_24XX_MMC2_IRQ	86
- + #define INT_24XX_MCBSP3_IRQ_TX	89
- + #define INT_24XX_MCBSP3_IRQ_RX	90
- + #define INT_24XX_SPI3_IRQ	91
- + 
- + #define INT_243X_MCBSP2_IRQ	16
- + #define INT_243X_MCBSP3_IRQ	17
- + #define INT_243X_MCBSP4_IRQ	18
- + #define INT_243X_MCBSP5_IRQ	19
- + #define INT_243X_MCBSP1_IRQ	64
- + #define INT_243X_HS_USB_MC	92
- + #define INT_243X_HS_USB_DMA	93
- + #define INT_243X_CARKIT_IRQ	94
- + 
- + #define INT_34XX_BENCH_MPU_EMUL	3
- + #define INT_34XX_ST_MCBSP2_IRQ	4
- + #define INT_34XX_ST_MCBSP3_IRQ	5
- + #define INT_34XX_SSM_ABORT_IRQ	6
- + #define INT_34XX_SYS_NIRQ	7
- + #define INT_34XX_D2D_FW_IRQ	8
- + #define INT_34XX_L3_DBG_IRQ     9
- + #define INT_34XX_L3_APP_IRQ     10
- + #define INT_34XX_PRCM_MPU_IRQ	11
- + #define INT_34XX_MCBSP1_IRQ	16
- + #define INT_34XX_MCBSP2_IRQ	17
- + #define INT_34XX_GPMC_IRQ	20
- + #define INT_34XX_MCBSP3_IRQ	22
- + #define INT_34XX_MCBSP4_IRQ	23
- + #define INT_34XX_CAM_IRQ	24
- + #define INT_34XX_MCBSP5_IRQ	27
- + #define INT_34XX_GPIO_BANK1	29
- + #define INT_34XX_GPIO_BANK2	30
- + #define INT_34XX_GPIO_BANK3	31
- + #define INT_34XX_GPIO_BANK4	32
- + #define INT_34XX_GPIO_BANK5	33
- + #define INT_34XX_GPIO_BANK6	34
- + #define INT_34XX_USIM_IRQ	35
- + #define INT_34XX_WDT3_IRQ	36
- + #define INT_34XX_SPI4_IRQ	48
- + #define INT_34XX_SHA1MD52_IRQ	49
- + #define INT_34XX_FPKA_READY_IRQ	50
- + #define INT_34XX_SHA1MD51_IRQ	51
- + #define INT_34XX_RNG_IRQ	52
- + #define INT_34XX_I2C3_IRQ	61
- + #define INT_34XX_FPKA_ERROR_IRQ	64
- + #define INT_34XX_PBIAS_IRQ	75
- + #define INT_34XX_OHCI_IRQ	76
- + #define INT_34XX_EHCI_IRQ	77
- + #define INT_34XX_TLL_IRQ	78
- + #define INT_34XX_PARTHASH_IRQ	79
- + #define INT_34XX_MMC3_IRQ	94
- + #define INT_34XX_GPT12_IRQ	95
- + 
- + #define INT_36XX_UART4_IRQ	80
- + 
- + #define INT_35XX_HECC0_IRQ		24
- + #define INT_35XX_HECC1_IRQ		28
- + #define INT_35XX_EMAC_C0_RXTHRESH_IRQ	67
- + #define INT_35XX_EMAC_C0_RX_PULSE_IRQ	68
- + #define INT_35XX_EMAC_C0_TX_PULSE_IRQ	69
- + #define INT_35XX_EMAC_C0_MISC_PULSE_IRQ	70
- + #define INT_35XX_USBOTG_IRQ		71
- + #define INT_35XX_UART4_IRQ		84
- + #define INT_35XX_CCDC_VD0_IRQ		88
- + #define INT_35XX_CCDC_VD1_IRQ		92
- + #define INT_35XX_CCDC_VD2_IRQ		93
- + 
- + /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
- +  * 16 MPUIO lines */
- + #define OMAP_MAX_GPIO_LINES	192
- + #define IH_GPIO_BASE		(128 + IH2_BASE)
- + #define IH_MPUIO_BASE		(OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
- + #define OMAP_IRQ_END		(IH_MPUIO_BASE + 16)
- + 
- + /* External FPGA handles interrupts on Innovator boards */
- + #define	OMAP_FPGA_IRQ_BASE	(OMAP_IRQ_END)
- + #ifdef	CONFIG_MACH_OMAP_INNOVATOR
- + #define OMAP_FPGA_NR_IRQS	24
- + #else
- + #define OMAP_FPGA_NR_IRQS	0
- + #endif
- + #define OMAP_FPGA_IRQ_END	(OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
- + 
- + /* GPMC related */
- + #define OMAP_GPMC_IRQ_BASE	(OMAP_FPGA_IRQ_END)
- + #define OMAP_GPMC_NR_IRQS	8
- + #define OMAP_GPMC_IRQ_END	(OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS)
- + 
- + 
- + #define NR_IRQS			OMAP_GPMC_IRQ_END
- + 
- + #define OMAP_IRQ_BIT(irq)	(1 << ((irq) % 32))
- + 
- + /*
- +  * Max from AM33XX device
- +  */
- + #define INTCPS_MAX_NR_REGS_REQ	4
- + #define INTCPS_MAX_NR_IRQS	128
- + 
- + #include <mach/hardware.h>
- + 
- + #ifdef CONFIG_FIQ
- + #define FIQ_START		1024
- + #endif
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/l3_2xxx.h linux-3.2.1/arch/arm/plat-ckb/include/plat/l3_2xxx.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/l3_2xxx.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/l3_2xxx.h	2014-05-15 13:25:14.134646030 +0900
- ***************
- *** 0 ****
- --- 1,20 ----
- + /*
- +  * arch/arm/plat-omap/include/plat/l3_2xxx.h - L3 firewall definitions
- +  *
- +  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- +  *	Sumit Semwal
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; either version 2 of the License, or
- +  * (at your option) any later version.
- +  *
- +  */
- + #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H
- + #define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H
- + 
- + /* L3 CONNIDs */
- + /* Display Sub system (DSS) */
- + #define OMAP2_L3_CORE_FW_CONNID_DSS			8
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/l3_3xxx.h linux-3.2.1/arch/arm/plat-ckb/include/plat/l3_3xxx.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/l3_3xxx.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/l3_3xxx.h	2014-05-15 13:25:14.134646030 +0900
- ***************
- *** 0 ****
- --- 1,20 ----
- + /*
- +  * arch/arm/plat-omap/include/plat/l3_3xxx.h - L3 firewall definitions
- +  *
- +  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- +  *	Sumit Semwal
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; either version 2 of the License, or
- +  * (at your option) any later version.
- +  *
- +  */
- + #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_3XXX_H
- + #define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_3XXX_H
- + 
- + /* L3 Initiator IDs */
- + /* Display Sub system (DSS) */
- + #define OMAP3_L3_CORE_FW_INIT_ID_DSS			29
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/lcdc.h linux-3.2.1/arch/arm/plat-ckb/include/plat/lcdc.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/lcdc.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/lcdc.h	2014-05-15 13:25:14.134646030 +0900
- ***************
- *** 0 ****
- --- 1,21 ----
- + /*
- +  * Header file for LCD controller
- +  *
- +  * Copyright (C) {2011} Texas Instruments Incorporated - http://www.ti.com/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
- +  * GNU General Public License for more details.
- +  **/
- + 
- + #ifndef __OMAP2_LCDC_H
- + #define __OMAP2_LCDC_H
- + 
- + struct platform_device *am33xx_register_lcdc(
- + 		struct da8xx_lcdc_platform_data *pdata);
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/led.h linux-3.2.1/arch/arm/plat-ckb/include/plat/led.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/led.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/led.h	2014-05-15 13:25:14.134646030 +0900
- ***************
- *** 0 ****
- --- 1,24 ----
- + /*
- +  *  arch/arm/plat-omap/include/mach/led.h
- +  *
- +  *  Copyright (C) 2006 Samsung Electronics
- +  *  Kyungmin Park <kyungmin.park@samsung.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + #ifndef ASMARM_ARCH_LED_H
- + #define ASMARM_ARCH_LED_H
- + 
- + struct omap_led_config {
- + 	struct led_classdev	cdev;
- + 	s16			gpio;
- + };
- + 
- + struct omap_led_platform_data {
- + 	s16			nr_leds;
- + 	struct omap_led_config	*leds;
- + };
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/mailbox.h linux-3.2.1/arch/arm/plat-ckb/include/plat/mailbox.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/mailbox.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/mailbox.h	2014-05-15 13:25:14.134646030 +0900
- ***************
- *** 0 ****
- --- 1,108 ----
- + /* mailbox.h */
- + 
- + #ifndef MAILBOX_H
- + #define MAILBOX_H
- + 
- + #include <linux/spinlock.h>
- + #include <linux/workqueue.h>
- + #include <linux/interrupt.h>
- + #include <linux/device.h>
- + #include <linux/kfifo.h>
- + 
- + typedef u32 mbox_msg_t;
- + struct omap_mbox;
- + 
- + typedef int __bitwise omap_mbox_irq_t;
- + #define IRQ_TX ((__force omap_mbox_irq_t) 1)
- + #define IRQ_RX ((__force omap_mbox_irq_t) 2)
- + 
- + typedef int __bitwise omap_mbox_type_t;
- + #define OMAP_MBOX_TYPE1 ((__force omap_mbox_type_t) 1)
- + #define OMAP_MBOX_TYPE2 ((__force omap_mbox_type_t) 2)
- + 
- + struct omap_mbox_ops {
- + 	omap_mbox_type_t	type;
- + 	int		(*startup)(struct omap_mbox *mbox);
- + 	void		(*shutdown)(struct omap_mbox *mbox);
- + 	/* fifo */
- + 	mbox_msg_t	(*fifo_read)(struct omap_mbox *mbox);
- + 	void		(*fifo_write)(struct omap_mbox *mbox, mbox_msg_t msg);
- + 	int		(*fifo_empty)(struct omap_mbox *mbox);
- + 	int		(*fifo_full)(struct omap_mbox *mbox);
- + 	int		(*fifo_needs_flush)(struct omap_mbox *mbox);
- + 	mbox_msg_t	(*fifo_readback)(struct omap_mbox *mbox);
- + 	/* irq */
- + 	void		(*enable_irq)(struct omap_mbox *mbox,
- + 						omap_mbox_irq_t irq);
- + 	void		(*disable_irq)(struct omap_mbox *mbox,
- + 						omap_mbox_irq_t irq);
- + 	void		(*ack_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
- + 	int		(*is_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
- + 	/* ctx */
- + 	void		(*save_ctx)(struct omap_mbox *mbox);
- + 	void		(*restore_ctx)(struct omap_mbox *mbox);
- + };
- + 
- + struct omap_mbox_queue {
- + 	spinlock_t		lock;
- + 	struct kfifo		fifo;
- + 	struct work_struct	work;
- + 	struct tasklet_struct	tasklet;
- + 	struct omap_mbox	*mbox;
- + 	bool full;
- + };
- + 
- + struct omap_mbox {
- + 	char			*name;
- + 	unsigned int		irq;
- + 	struct omap_mbox_queue	*txq, *rxq;
- + 	struct omap_mbox_ops	*ops;
- + 	struct device		*dev;
- + 	void			*priv;
- + 	int			use_count;
- + 	struct blocking_notifier_head   notifier;
- + };
- + 
- + int omap_mbox_msg_rx_flush(struct omap_mbox *mbox);
- + int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg);
- + void omap_mbox_init_seq(struct omap_mbox *);
- + 
- + struct omap_mbox *omap_mbox_get(const char *, struct notifier_block *nb);
- + void omap_mbox_put(struct omap_mbox *mbox, struct notifier_block *nb);
- + 
- + int omap_mbox_register(struct device *parent, struct omap_mbox **);
- + int omap_mbox_unregister(void);
- + 
- + static inline void omap_mbox_save_ctx(struct omap_mbox *mbox)
- + {
- + 	if (!mbox->ops->save_ctx) {
- + 		dev_err(mbox->dev, "%s:\tno save\n", __func__);
- + 		return;
- + 	}
- + 
- + 	mbox->ops->save_ctx(mbox);
- + }
- + 
- + static inline void omap_mbox_restore_ctx(struct omap_mbox *mbox)
- + {
- + 	if (!mbox->ops->restore_ctx) {
- + 		dev_err(mbox->dev, "%s:\tno restore\n", __func__);
- + 		return;
- + 	}
- + 
- + 	mbox->ops->restore_ctx(mbox);
- + }
- + 
- + static inline void omap_mbox_enable_irq(struct omap_mbox *mbox,
- + 					omap_mbox_irq_t irq)
- + {
- + 	mbox->ops->enable_irq(mbox, irq);
- + }
- + 
- + static inline void omap_mbox_disable_irq(struct omap_mbox *mbox,
- + 					 omap_mbox_irq_t irq)
- + {
- + 	mbox->ops->disable_irq(mbox, irq);
- + }
- + 
- + #endif /* MAILBOX_H */
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/mcspi.h linux-3.2.1/arch/arm/plat-ckb/include/plat/mcspi.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/mcspi.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/mcspi.h	2014-05-15 13:25:14.134646030 +0900
- ***************
- *** 0 ****
- --- 1,23 ----
- + #ifndef _OMAP2_MCSPI_H
- + #define _OMAP2_MCSPI_H
- + 
- + #define OMAP2_MCSPI_REV 0
- + #define OMAP3_MCSPI_REV 1
- + #define OMAP4_MCSPI_REV 2
- + 
- + #define OMAP4_MCSPI_REG_OFFSET 0x100
- + 
- + struct omap2_mcspi_platform_config {
- + 	unsigned short	num_cs;
- + 	unsigned int regs_offset;
- + };
- + 
- + struct omap2_mcspi_dev_attr {
- + 	unsigned short num_chipselect;
- + };
- + 
- + struct omap2_mcspi_device_config {
- + 	unsigned turbo_mode:1;
- + };
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/mmc.h linux-3.2.1/arch/arm/plat-ckb/include/plat/mmc.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/mmc.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/mmc.h	2014-05-15 13:25:14.138737749 +0900
- ***************
- *** 0 ****
- --- 1,208 ----
- + /*
- +  * MMC definitions for OMAP2
- +  *
- +  * Copyright (C) 2006 Nokia Corporation
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #ifndef __OMAP2_MMC_H
- + #define __OMAP2_MMC_H
- + 
- + #include <linux/types.h>
- + #include <linux/device.h>
- + #include <linux/mmc/host.h>
- + 
- + #include <plat/board.h>
- + 
- + #define OMAP15XX_NR_MMC		1
- + #define OMAP16XX_NR_MMC		2
- + #define OMAP1_MMC_SIZE		0x080
- + #define OMAP1_MMC1_BASE		0xfffb7800
- + #define OMAP1_MMC2_BASE		0xfffb7c00	/* omap16xx only */
- + 
- + #define OMAP24XX_NR_MMC		2
- + #define OMAP2420_MMC_SIZE	OMAP1_MMC_SIZE
- + #define OMAP2_MMC1_BASE		0x4809c000
- + 
- + #define OMAP4_MMC_REG_OFFSET	0x100
- + 
- + #define OMAP_MMC_MAX_SLOTS	2
- + 
- + /*
- +  * struct omap_mmc_dev_attr.flags possibilities
- +  *
- +  * OMAP_HSMMC_SUPPORTS_DUAL_VOLT: Some HSMMC controller instances can
- +  *    operate with either 1.8Vdc or 3.0Vdc card voltages; this flag
- +  *    should be set if this is the case.  See for example Section 22.5.3
- +  *    "MMC/SD/SDIO1 Bus Voltage Selection" of the OMAP34xx Multimedia
- +  *    Device Silicon Revision 3.1.x Revision ZR (July 2011) (SWPU223R).
- +  *
- +  * OMAP_HSMMC_BROKEN_MULTIBLOCK_READ: Multiple-block read transfers
- +  *    don't work correctly on some MMC controller instances on some
- +  *    OMAP3 SoCs; this flag should be set if this is the case.  See
- +  *    for example Advisory 2.1.1.128 "MMC: Multiple Block Read
- +  *    Operation Issue" in _OMAP3530/3525/3515/3503 Silicon Errata_
- +  *    Revision F (October 2010) (SPRZ278F).
- +  */
- + #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT		BIT(0)
- + #define OMAP_HSMMC_BROKEN_MULTIBLOCK_READ	BIT(1)
- + 
- + enum {
- + 	MMC_CTRL_VERSION_1 = 0, /* OMAP class devicess */
- + 	MMC_CTRL_VERSION_2	/* AM33XX class devices */
- + };
- + 
- + struct omap_mmc_dev_attr {
- + 	u8 flags;
- + };
- + 
- + struct omap_mmc_platform_data {
- + 	/* back-link to device */
- + 	struct device *dev;
- + 
- + 	/* number of slots per controller */
- + 	unsigned nr_slots:2;
- + 
- + 	/* set if your board has components or wiring that limits the
- + 	 * maximum frequency on the MMC bus */
- + 	unsigned int max_freq;
- + 
- + 	/* switch the bus to a new slot */
- + 	int (*switch_slot)(struct device *dev, int slot);
- + 	/* initialize board-specific MMC functionality, can be NULL if
- + 	 * not supported */
- + 	int (*init)(struct device *dev);
- + 	void (*cleanup)(struct device *dev);
- + 	void (*shutdown)(struct device *dev);
- + 
- + 	/* To handle board related suspend/resume functionality for MMC */
- + 	int (*suspend)(struct device *dev, int slot);
- + 	int (*resume)(struct device *dev, int slot);
- + 
- + 	/* Return context loss count due to PM states changing */
- + 	int (*get_context_loss_count)(struct device *dev);
- + 
- + 	u64 dma_mask;
- + 
- + 	/* Integrating attributes from the omap_hwmod layer */
- + 	u8 controller_flags;
- + 
- + 	/* Register offset deviation */
- + 	u16 reg_offset;
- + 
- + 	struct omap_mmc_slot_data {
- + 
- + 		/*
- + 		 * 4/8 wires and any additional host capabilities
- + 		 * need to OR'd all capabilities (ref. linux/mmc/host.h)
- + 		 */
- + 		u8  wires;	/* Used for the MMC driver on omap1 and 2420 */
- + 		u32 caps;	/* Used for the MMC driver on 2430 and later */
- + 		u32 pm_caps;	/* PM capabilities of the mmc */
- + 
- + 		/*
- + 		 * nomux means "standard" muxing is wrong on this board, and
- + 		 * that board-specific code handled it before common init logic.
- + 		 */
- + 		unsigned nomux:1;
- + 
- + 		/* switch pin can be for card detect (default) or card cover */
- + 		unsigned cover:1;
- + 
- + 		/* use the internal clock */
- + 		unsigned internal_clock:1;
- + 
- + 		/* nonremovable e.g. eMMC */
- + 		unsigned nonremovable:1;
- + 
- + 		/* Try to sleep or power off when possible */
- + 		unsigned power_saving:1;
- + 
- + 		/* If using power_saving and the MMC power is not to go off */
- + 		unsigned no_off:1;
- + 
- + 		/* eMMC does not handle power off when not in sleep state */
- + 		unsigned no_regulator_off_init:1;
- + 
- + 		/* Regulator off remapped to sleep */
- + 		unsigned vcc_aux_disable_is_sleep:1;
- + 
- + 		/* we can put the features above into this variable */
- + #define HSMMC_HAS_PBIAS		(1 << 0)
- + #define HSMMC_HAS_UPDATED_RESET	(1 << 1)
- + 		unsigned features;
- + 
- + 		int switch_pin;			/* gpio (card detect) */
- + 		int gpio_wp;			/* gpio (write protect) */
- + 
- + 		int (*set_bus_mode)(struct device *dev, int slot, int bus_mode);
- + 		int (*set_power)(struct device *dev, int slot,
- + 				 int power_on, int vdd);
- + 		int (*get_ro)(struct device *dev, int slot);
- + 		int (*set_sleep)(struct device *dev, int slot, int sleep,
- + 				 int vdd, int cardsleep);
- + 		void (*remux)(struct device *dev, int slot, int power_on);
- + 		/* Call back before enabling / disabling regulators */
- + 		void (*before_set_reg)(struct device *dev, int slot,
- + 				       int power_on, int vdd);
- + 		/* Call back after enabling / disabling regulators */
- + 		void (*after_set_reg)(struct device *dev, int slot,
- + 				      int power_on, int vdd);
- + 		/* if we have special card, init it using this callback */
- + 		void (*init_card)(struct mmc_card *card);
- + 
- + 		/* return MMC cover switch state, can be NULL if not supported.
- + 		 *
- + 		 * possible return values:
- + 		 *   0 - closed
- + 		 *   1 - open
- + 		 */
- + 		int (*get_cover_state)(struct device *dev, int slot);
- + 
- + 		const char *name;
- + 		u32 ocr_mask;
- + 
- + 		/* Card detection IRQs */
- + 		int card_detect_irq;
- + 		int (*card_detect)(struct device *dev, int slot);
- + 
- + 		unsigned int ban_openended:1;
- + 
- + 	} slots[OMAP_MMC_MAX_SLOTS];
- + 
- + 	u8 version;
- + 	
- + };
- + 
- + /* called from board-specific card detection service routine */
- + extern void omap_mmc_notify_cover_event(struct device *dev, int slot,
- + 					int is_closed);
- + 
- + #if	defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
- + 	defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
- + void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
- + 				int nr_controllers);
- + void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data);
- + int omap_mmc_add(const char *name, int id, unsigned long base,
- + 				unsigned long size, unsigned int irq,
- + 				struct omap_mmc_platform_data *data);
- + #else
- + static inline void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
- + 				int nr_controllers)
- + {
- + }
- + static inline void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
- + {
- + }
- + static inline int omap_mmc_add(const char *name, int id, unsigned long base,
- + 				unsigned long size, unsigned int irq,
- + 				struct omap_mmc_platform_data *data)
- + {
- + 	return 0;
- + }
- + 
- + #endif
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/multi.h linux-3.2.1/arch/arm/plat-ckb/include/plat/multi.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/multi.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/multi.h	2014-05-15 13:25:14.138737749 +0900
- ***************
- *** 0 ****
- --- 1,42 ----
- + /*
- +  * Support for compiling in multiple OMAP processors
- +  *
- +  * Copyright (C) 2010 Nokia Corporation
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; either version 2 of the License, or
- +  * (at your option) any later version.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- +  *
- +  */
- + 
- + #ifndef __PLAT_OMAP_MULTI_H
- + #define __PLAT_OMAP_MULTI_H
- + 
- + /*
- +  * Test if multicore OMAP support is needed
- +  */
- + #undef MULTI_OMAP1
- + #undef MULTI_OMAP2
- + #undef OMAP_NAME
- + 
- + # if (defined(OMAP_NAME) || defined(MULTI_OMAP1))
- + #  error "OMAP1 and OMAP2PLUS can't be selected at the same time"
- + # endif
- + # ifdef OMAP_NAME
- + #  undef  MULTI_OMAP2
- + #  define MULTI_OMAP2
- + # else
- + #  define OMAP_NAME omap3
- + # endif
- + 
- + #endif	/* __PLAT_OMAP_MULTI_H */
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/mux.h linux-3.2.1/arch/arm/plat-ckb/include/plat/mux.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/mux.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/mux.h	2014-05-15 13:25:14.138737749 +0900
- ***************
- *** 0 ****
- --- 1,451 ----
- + /*
- +  * arch/arm/plat-omap/include/mach/mux.h
- +  *
- +  * Table of the Omap register configurations for the FUNC_MUX and
- +  * PULL_DWN combinations.
- +  *
- +  * Copyright (C) 2004 - 2008 Texas Instruments Inc.
- +  * Copyright (C) 2003 - 2008 Nokia Corporation
- +  *
- +  * Written by Tony Lindgren
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; either version 2 of the License, or
- +  * (at your option) any later version.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- +  *
- +  * NOTE: Please use the following naming style for new pin entries.
- +  *	 For example, W8_1610_MMC2_DAT0, where:
- +  *	 - W8	     = ball
- +  *	 - 1610	     = 1510 or 1610, none if common for both 1510 and 1610
- +  *	 - MMC2_DAT0 = function
- +  */
- + 
- + #ifndef __ASM_ARCH_MUX_H
- + #define __ASM_ARCH_MUX_H
- + 
- + #define PU_PD_SEL_NA		0	/* No pu_pd reg available */
- + #define PULL_DWN_CTRL_NA	0	/* No pull-down control needed */
- + 
- + #ifdef	CONFIG_OMAP_MUX_DEBUG
- + #define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \
- + 					.mux_reg = FUNC_MUX_CTRL_##reg, \
- + 					.mask_offset = mode_offset, \
- + 					.mask = mode,
- + 
- + #define PULL_REG(reg, bit, status)	.pull_name = "PULL_DWN_CTRL_"#reg, \
- + 					.pull_reg = PULL_DWN_CTRL_##reg, \
- + 					.pull_bit = bit, \
- + 					.pull_val = status,
- + 
- + #define PU_PD_REG(reg, status)		.pu_pd_name = "PU_PD_SEL_"#reg, \
- + 					.pu_pd_reg = PU_PD_SEL_##reg, \
- + 					.pu_pd_val = status,
- + 
- + #define MUX_REG_7XX(reg, mode_offset, mode) .mux_reg_name = "OMAP7XX_IO_CONF_"#reg, \
- + 					.mux_reg = OMAP7XX_IO_CONF_##reg, \
- + 					.mask_offset = mode_offset, \
- + 					.mask = mode,
- + 
- + #define PULL_REG_7XX(reg, bit, status)	.pull_name = "OMAP7XX_IO_CONF_"#reg, \
- + 					.pull_reg = OMAP7XX_IO_CONF_##reg, \
- + 					.pull_bit = bit, \
- + 					.pull_val = status,
- + 
- + #else
- + 
- + #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
- + 					.mask_offset = mode_offset, \
- + 					.mask = mode,
- + 
- + #define PULL_REG(reg, bit, status)	.pull_reg = PULL_DWN_CTRL_##reg, \
- + 					.pull_bit = bit, \
- + 					.pull_val = status,
- + 
- + #define PU_PD_REG(reg, status)		.pu_pd_reg = PU_PD_SEL_##reg, \
- + 					.pu_pd_val = status,
- + 
- + #define MUX_REG_7XX(reg, mode_offset, mode) \
- + 					.mux_reg = OMAP7XX_IO_CONF_##reg, \
- + 					.mask_offset = mode_offset, \
- + 					.mask = mode,
- + 
- + #define PULL_REG_7XX(reg, bit, status)	.pull_reg = OMAP7XX_IO_CONF_##reg, \
- + 					.pull_bit = bit, \
- + 					.pull_val = status,
- + 
- + #endif /* CONFIG_OMAP_MUX_DEBUG */
- + 
- + #define MUX_CFG(desc, mux_reg, mode_offset, mode,	\
- + 		pull_reg, pull_bit, pull_status,	\
- + 		pu_pd_reg, pu_pd_status, debug_status)	\
- + {							\
- + 	.name =	 desc,					\
- + 	.debug = debug_status,				\
- + 	MUX_REG(mux_reg, mode_offset, mode)		\
- + 	PULL_REG(pull_reg, pull_bit, pull_status)	\
- + 	PU_PD_REG(pu_pd_reg, pu_pd_status)		\
- + },
- + 
- + 
- + /*
- +  * OMAP730/850 has a slightly different config for the pin mux.
- +  * - config regs are the OMAP7XX_IO_CONF_x regs (see omap730.h) regs and
- +  *   not the FUNC_MUX_CTRL_x regs from hardware.h
- +  * - for pull-up/down, only has one enable bit which is is in the same register
- +  *   as mux config
- +  */
- + #define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode,	\
- + 		   pull_bit, pull_status, debug_status)\
- + {							\
- + 	.name =	 desc,					\
- + 	.debug = debug_status,				\
- + 	MUX_REG_7XX(mux_reg, mode_offset, mode)		\
- + 	PULL_REG_7XX(mux_reg, pull_bit, pull_status)	\
- + 	PU_PD_REG(NA, 0)		\
- + },
- + 
- + struct pin_config {
- + 	char 			*name;
- + 	const unsigned int 	mux_reg;
- + 	unsigned char		debug;
- + 
- + 	const unsigned char mask_offset;
- + 	const unsigned char mask;
- + 
- + 	const char *pull_name;
- + 	const unsigned int pull_reg;
- + 	const unsigned char pull_val;
- + 	const unsigned char pull_bit;
- + 
- + 	const char *pu_pd_name;
- + 	const unsigned int pu_pd_reg;
- + 	const unsigned char pu_pd_val;
- + 
- + #if	defined(CONFIG_OMAP_MUX_DEBUG)
- + 	const char *mux_reg_name;
- + #endif
- + 
- + };
- + 
- + enum omap7xx_index {
- + 	/* OMAP 730 keyboard */
- + 	E2_7XX_KBR0,
- + 	J7_7XX_KBR1,
- + 	E1_7XX_KBR2,
- + 	F3_7XX_KBR3,
- + 	D2_7XX_KBR4,
- + 	C2_7XX_KBC0,
- + 	D3_7XX_KBC1,
- + 	E4_7XX_KBC2,
- + 	F4_7XX_KBC3,
- + 	E3_7XX_KBC4,
- + 
- + 	/* USB */
- + 	AA17_7XX_USB_DM,
- + 	W16_7XX_USB_PU_EN,
- + 	W17_7XX_USB_VBUSI,
- + 	W18_7XX_USB_DMCK_OUT,
- + 	W19_7XX_USB_DCRST,
- + 
- + 	/* MMC */
- + 	MMC_7XX_CMD,
- + 	MMC_7XX_CLK,
- + 	MMC_7XX_DAT0,
- + 
- + 	/* I2C */
- + 	I2C_7XX_SCL,
- + 	I2C_7XX_SDA,
- + 
- + 	/* SPI */
- + 	SPI_7XX_1,
- + 	SPI_7XX_2,
- + 	SPI_7XX_3,
- + 	SPI_7XX_4,
- + 	SPI_7XX_5,
- + 	SPI_7XX_6,
- + 
- + 	/* UART */
- + 	UART_7XX_1,
- + 	UART_7XX_2,
- + };
- + 
- + enum omap1xxx_index {
- + 	/* UART1 (BT_UART_GATING)*/
- + 	UART1_TX = 0,
- + 	UART1_RTS,
- + 
- + 	/* UART2 (COM_UART_GATING)*/
- + 	UART2_TX,
- + 	UART2_RX,
- + 	UART2_CTS,
- + 	UART2_RTS,
- + 
- + 	/* UART3 (GIGA_UART_GATING) */
- + 	UART3_TX,
- + 	UART3_RX,
- + 	UART3_CTS,
- + 	UART3_RTS,
- + 	UART3_CLKREQ,
- + 	UART3_BCLK,	/* 12MHz clock out */
- + 	Y15_1610_UART3_RTS,
- + 
- + 	/* PWT & PWL */
- + 	PWT,
- + 	PWL,
- + 
- + 	/* USB master generic */
- + 	R18_USB_VBUS,
- + 	R18_1510_USB_GPIO0,
- + 	W4_USB_PUEN,
- + 	W4_USB_CLKO,
- + 	W4_USB_HIGHZ,
- + 	W4_GPIO58,
- + 
- + 	/* USB1 master */
- + 	USB1_SUSP,
- + 	USB1_SEO,
- + 	W13_1610_USB1_SE0,
- + 	USB1_TXEN,
- + 	USB1_TXD,
- + 	USB1_VP,
- + 	USB1_VM,
- + 	USB1_RCV,
- + 	USB1_SPEED,
- + 	R13_1610_USB1_SPEED,
- + 	R13_1710_USB1_SE0,
- + 
- + 	/* USB2 master */
- + 	USB2_SUSP,
- + 	USB2_VP,
- + 	USB2_TXEN,
- + 	USB2_VM,
- + 	USB2_RCV,
- + 	USB2_SEO,
- + 	USB2_TXD,
- + 
- + 	/* OMAP-1510 GPIO */
- + 	R18_1510_GPIO0,
- + 	R19_1510_GPIO1,
- + 	M14_1510_GPIO2,
- + 
- + 	/* OMAP1610 GPIO */
- + 	P18_1610_GPIO3,
- + 	Y15_1610_GPIO17,
- + 
- + 	/* OMAP-1710 GPIO */
- + 	R18_1710_GPIO0,
- + 	V2_1710_GPIO10,
- + 	N21_1710_GPIO14,
- + 	W15_1710_GPIO40,
- + 
- + 	/* MPUIO */
- + 	MPUIO2,
- + 	N15_1610_MPUIO2,
- + 	MPUIO4,
- + 	MPUIO5,
- + 	T20_1610_MPUIO5,
- + 	W11_1610_MPUIO6,
- + 	V10_1610_MPUIO7,
- + 	W11_1610_MPUIO9,
- + 	V10_1610_MPUIO10,
- + 	W10_1610_MPUIO11,
- + 	E20_1610_MPUIO13,
- + 	U20_1610_MPUIO14,
- + 	E19_1610_MPUIO15,
- + 
- + 	/* MCBSP2 */
- + 	MCBSP2_CLKR,
- + 	MCBSP2_CLKX,
- + 	MCBSP2_DR,
- + 	MCBSP2_DX,
- + 	MCBSP2_FSR,
- + 	MCBSP2_FSX,
- + 
- + 	/* MCBSP3 */
- + 	MCBSP3_CLKX,
- + 
- + 	/* Misc ballouts */
- + 	BALLOUT_V8_ARMIO3,
- + 	N20_HDQ,
- + 
- + 	/* OMAP-1610 MMC2 */
- + 	W8_1610_MMC2_DAT0,
- + 	V8_1610_MMC2_DAT1,
- + 	W15_1610_MMC2_DAT2,
- + 	R10_1610_MMC2_DAT3,
- + 	Y10_1610_MMC2_CLK,
- + 	Y8_1610_MMC2_CMD,
- + 	V9_1610_MMC2_CMDDIR,
- + 	V5_1610_MMC2_DATDIR0,
- + 	W19_1610_MMC2_DATDIR1,
- + 	R18_1610_MMC2_CLKIN,
- + 
- + 	/* OMAP-1610 External Trace Interface */
- + 	M19_1610_ETM_PSTAT0,
- + 	L15_1610_ETM_PSTAT1,
- + 	L18_1610_ETM_PSTAT2,
- + 	L19_1610_ETM_D0,
- + 	J19_1610_ETM_D6,
- + 	J18_1610_ETM_D7,
- + 
- + 	/* OMAP16XX GPIO */
- + 	P20_1610_GPIO4,
- + 	V9_1610_GPIO7,
- + 	W8_1610_GPIO9,
- + 	N20_1610_GPIO11,
- + 	N19_1610_GPIO13,
- + 	P10_1610_GPIO22,
- + 	V5_1610_GPIO24,
- + 	AA20_1610_GPIO_41,
- + 	W19_1610_GPIO48,
- + 	M7_1610_GPIO62,
- + 	V14_16XX_GPIO37,
- + 	R9_16XX_GPIO18,
- + 	L14_16XX_GPIO49,
- + 
- + 	/* OMAP-1610 uWire */
- + 	V19_1610_UWIRE_SCLK,
- + 	U18_1610_UWIRE_SDI,
- + 	W21_1610_UWIRE_SDO,
- + 	N14_1610_UWIRE_CS0,
- + 	P15_1610_UWIRE_CS3,
- + 	N15_1610_UWIRE_CS1,
- + 
- + 	/* OMAP-1610 SPI */
- + 	U19_1610_SPIF_SCK,
- + 	U18_1610_SPIF_DIN,
- + 	P20_1610_SPIF_DIN,
- + 	W21_1610_SPIF_DOUT,
- + 	R18_1610_SPIF_DOUT,
- + 	N14_1610_SPIF_CS0,
- + 	N15_1610_SPIF_CS1,
- + 	T19_1610_SPIF_CS2,
- + 	P15_1610_SPIF_CS3,
- + 
- + 	/* OMAP-1610 Flash */
- + 	L3_1610_FLASH_CS2B_OE,
- + 	M8_1610_FLASH_CS2B_WE,
- + 
- + 	/* First MMC */
- + 	MMC_CMD,
- + 	MMC_DAT1,
- + 	MMC_DAT2,
- + 	MMC_DAT0,
- + 	MMC_CLK,
- + 	MMC_DAT3,
- + 
- + 	/* OMAP-1710 MMC CMDDIR and DATDIR0 */
- + 	M15_1710_MMC_CLKI,
- + 	P19_1710_MMC_CMDDIR,
- + 	P20_1710_MMC_DATDIR0,
- + 
- + 	/* OMAP-1610 USB0 alternate pin configuration */
- + 	W9_USB0_TXEN,
- + 	AA9_USB0_VP,
- + 	Y5_USB0_RCV,
- + 	R9_USB0_VM,
- + 	V6_USB0_TXD,
- + 	W5_USB0_SE0,
- + 	V9_USB0_SPEED,
- + 	V9_USB0_SUSP,
- + 
- + 	/* USB2 */
- + 	W9_USB2_TXEN,
- + 	AA9_USB2_VP,
- + 	Y5_USB2_RCV,
- + 	R9_USB2_VM,
- + 	V6_USB2_TXD,
- + 	W5_USB2_SE0,
- + 
- + 	/* 16XX UART */
- + 	R13_1610_UART1_TX,
- + 	V14_16XX_UART1_RX,
- + 	R14_1610_UART1_CTS,
- + 	AA15_1610_UART1_RTS,
- + 	R9_16XX_UART2_RX,
- + 	L14_16XX_UART3_RX,
- + 
- + 	/* I2C OMAP-1610 */
- + 	I2C_SCL,
- + 	I2C_SDA,
- + 
- + 	/* Keypad */
- + 	F18_1610_KBC0,
- + 	D20_1610_KBC1,
- + 	D19_1610_KBC2,
- + 	E18_1610_KBC3,
- + 	C21_1610_KBC4,
- + 	G18_1610_KBR0,
- + 	F19_1610_KBR1,
- + 	H14_1610_KBR2,
- + 	E20_1610_KBR3,
- + 	E19_1610_KBR4,
- + 	N19_1610_KBR5,
- + 
- + 	/* Power management */
- + 	T20_1610_LOW_PWR,
- + 
- + 	/* MCLK Settings */
- + 	V5_1710_MCLK_ON,
- + 	V5_1710_MCLK_OFF,
- + 	R10_1610_MCLK_ON,
- + 	R10_1610_MCLK_OFF,
- + 
- + 	/* CompactFlash controller */
- + 	P11_1610_CF_CD2,
- + 	R11_1610_CF_IOIS16,
- + 	V10_1610_CF_IREQ,
- + 	W10_1610_CF_RESET,
- + 	W11_1610_CF_CD1,
- + 
- + 	/* parallel camera */
- + 	J15_1610_CAM_LCLK,
- + 	J18_1610_CAM_D7,
- + 	J19_1610_CAM_D6,
- + 	J14_1610_CAM_D5,
- + 	K18_1610_CAM_D4,
- + 	K19_1610_CAM_D3,
- + 	K15_1610_CAM_D2,
- + 	K14_1610_CAM_D1,
- + 	L19_1610_CAM_D0,
- + 	L18_1610_CAM_VS,
- + 	L15_1610_CAM_HS,
- + 	M19_1610_CAM_RSTZ,
- + 	Y15_1610_CAM_OUTCLK,
- + 
- + 	/* serial camera */
- + 	H19_1610_CAM_EXCLK,
- + 	Y12_1610_CCP_CLKP,
- + 	W13_1610_CCP_CLKM,
- + 	W14_1610_CCP_DATAP,
- + 	Y14_1610_CCP_DATAM,
- + 
- + };
- + 
- + struct omap_mux_cfg {
- + 	struct pin_config	*pins;
- + 	unsigned long		size;
- + 	int			(*cfg_reg)(const struct pin_config *cfg);
- + };
- + 
- + #ifdef	CONFIG_OMAP_MUX
- + /* setup pin muxing in Linux */
- + extern int omap1_mux_init(void);
- + extern int omap_mux_register(struct omap_mux_cfg *);
- + #else
- + static inline int omap1_mux_init(void) { return 0; }
- + #endif
- + 
- + extern int omap2_mux_init(void);
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/omap34xx.h linux-3.2.1/arch/arm/plat-ckb/include/plat/omap34xx.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/omap34xx.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/omap34xx.h	2014-05-15 13:25:14.142646404 +0900
- ***************
- *** 0 ****
- --- 1,101 ----
- + /*
- +  * arch/arm/plat-omap/include/mach/omap34xx.h
- +  *
- +  * This file contains the processor specific definitions of the TI OMAP34XX.
- +  *
- +  * Copyright (C) 2007 Texas Instruments.
- +  * Copyright (C) 2007 Nokia Corporation.
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; either version 2 of the License, or
- +  * (at your option) any later version.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- +  */
- + 
- + #ifndef __ASM_ARCH_OMAP3_H
- + #define __ASM_ARCH_OMAP3_H
- + 
- + /*
- +  * Please place only base defines here and put the rest in device
- +  * specific headers.
- +  */
- + 
- + #define L4_34XX_BASE		0x48000000
- + #define L4_WK_34XX_BASE		0x48300000
- + #define L4_PER_34XX_BASE	0x49000000
- + #define L4_EMU_34XX_BASE	0x54000000
- + #define L3_34XX_BASE		0x68000000
- + 
- + #define L4_WK_AM33XX_BASE	0x44C00000
- + 
- + #define OMAP3430_32KSYNCT_BASE	0x48320000
- + #define OMAP3430_CM_BASE	0x48004800
- + #define OMAP3430_PRM_BASE	0x48306800
- + #define OMAP343X_SMS_BASE	0x6C000000
- + #define OMAP343X_SDRC_BASE	0x6D000000
- + #define OMAP34XX_GPMC_BASE	0x6E000000
- + #define OMAP343X_SCM_BASE	0x48002000
- + #define OMAP343X_CTRL_BASE	OMAP343X_SCM_BASE
- + 
- + #define OMAP34XX_IC_BASE	0x48200000
- + 
- + #define OMAP3430_ISP_BASE		(L4_34XX_BASE + 0xBC000)
- + #define OMAP3430_ISP_CBUFF_BASE		(OMAP3430_ISP_BASE + 0x0100)
- + #define OMAP3430_ISP_CCP2_BASE		(OMAP3430_ISP_BASE + 0x0400)
- + #define OMAP3430_ISP_CCDC_BASE		(OMAP3430_ISP_BASE + 0x0600)
- + #define OMAP3430_ISP_HIST_BASE		(OMAP3430_ISP_BASE + 0x0A00)
- + #define OMAP3430_ISP_H3A_BASE		(OMAP3430_ISP_BASE + 0x0C00)
- + #define OMAP3430_ISP_PREV_BASE		(OMAP3430_ISP_BASE + 0x0E00)
- + #define OMAP3430_ISP_RESZ_BASE		(OMAP3430_ISP_BASE + 0x1000)
- + #define OMAP3430_ISP_SBL_BASE		(OMAP3430_ISP_BASE + 0x1200)
- + #define OMAP3430_ISP_MMU_BASE		(OMAP3430_ISP_BASE + 0x1400)
- + #define OMAP3430_ISP_CSI2A_REGS1_BASE	(OMAP3430_ISP_BASE + 0x1800)
- + #define OMAP3430_ISP_CSIPHY2_BASE	(OMAP3430_ISP_BASE + 0x1970)
- + #define OMAP3630_ISP_CSI2A_REGS2_BASE	(OMAP3430_ISP_BASE + 0x19C0)
- + #define OMAP3630_ISP_CSI2C_REGS1_BASE	(OMAP3430_ISP_BASE + 0x1C00)
- + #define OMAP3630_ISP_CSIPHY1_BASE	(OMAP3430_ISP_BASE + 0x1D70)
- + #define OMAP3630_ISP_CSI2C_REGS2_BASE	(OMAP3430_ISP_BASE + 0x1DC0)
- + 
- + #define OMAP3430_ISP_END		(OMAP3430_ISP_BASE         + 0x06F)
- + #define OMAP3430_ISP_CBUFF_END		(OMAP3430_ISP_CBUFF_BASE   + 0x077)
- + #define OMAP3430_ISP_CCP2_END		(OMAP3430_ISP_CCP2_BASE    + 0x1EF)
- + #define OMAP3430_ISP_CCDC_END		(OMAP3430_ISP_CCDC_BASE    + 0x0A7)
- + #define OMAP3430_ISP_HIST_END		(OMAP3430_ISP_HIST_BASE    + 0x047)
- + #define OMAP3430_ISP_H3A_END		(OMAP3430_ISP_H3A_BASE     + 0x05F)
- + #define OMAP3430_ISP_PREV_END		(OMAP3430_ISP_PREV_BASE    + 0x09F)
- + #define OMAP3430_ISP_RESZ_END		(OMAP3430_ISP_RESZ_BASE    + 0x0AB)
- + #define OMAP3430_ISP_SBL_END		(OMAP3430_ISP_SBL_BASE     + 0x0FB)
- + #define OMAP3430_ISP_MMU_END		(OMAP3430_ISP_MMU_BASE     + 0x06F)
- + #define OMAP3430_ISP_CSI2A_REGS1_END	(OMAP3430_ISP_CSI2A_REGS1_BASE + 0x16F)
- + #define OMAP3430_ISP_CSIPHY2_END	(OMAP3430_ISP_CSIPHY2_BASE + 0x00B)
- + #define OMAP3630_ISP_CSI2A_REGS2_END	(OMAP3630_ISP_CSI2A_REGS2_BASE + 0x3F)
- + #define OMAP3630_ISP_CSI2C_REGS1_END	(OMAP3630_ISP_CSI2C_REGS1_BASE + 0x16F)
- + #define OMAP3630_ISP_CSIPHY1_END	(OMAP3630_ISP_CSIPHY1_BASE + 0x00B)
- + #define OMAP3630_ISP_CSI2C_REGS2_END	(OMAP3630_ISP_CSI2C_REGS2_BASE + 0x3F)
- + 
- + #define OMAP34XX_HSUSB_OTG_BASE	(L4_34XX_BASE + 0xAB000)
- + #define OMAP34XX_USBTLL_BASE	(L4_34XX_BASE + 0x62000)
- + #define OMAP34XX_UHH_CONFIG_BASE	(L4_34XX_BASE + 0x64000)
- + #define OMAP34XX_OHCI_BASE	(L4_34XX_BASE + 0x64400)
- + #define OMAP34XX_EHCI_BASE	(L4_34XX_BASE + 0x64800)
- + #define OMAP34XX_SR1_BASE	0x480C9000
- + #define OMAP34XX_SR2_BASE	0x480CB000
- + 
- + #define OMAP34XX_MAILBOX_BASE		(L4_34XX_BASE + 0x94000)
- + 
- + /* Security */
- + #define OMAP34XX_SEC_BASE	(L4_34XX_BASE + 0xA0000)
- + #define OMAP34XX_SEC_SHA1MD5_BASE	(OMAP34XX_SEC_BASE + 0x23000)
- + #define OMAP34XX_SEC_AES_BASE	(OMAP34XX_SEC_BASE + 0x25000)
- + 
- + #endif /* __ASM_ARCH_OMAP3_H */
- + 
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/omap_device.h linux-3.2.1/arch/arm/plat-ckb/include/plat/omap_device.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/omap_device.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/omap_device.h	2014-05-15 13:25:14.142646404 +0900
- ***************
- *** 0 ****
- --- 1,171 ----
- + /*
- +  * omap_device headers
- +  *
- +  * Copyright (C) 2009 Nokia Corporation
- +  * Paul Walmsley
- +  *
- +  * Developed in collaboration with (alphabetical order): Benoit
- +  * Cousson, Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram
- +  * Pandita, Sakari Poussa, Anand Sawant, Santosh Shilimkar, Richard
- +  * Woodruff
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  *
- +  * Eventually this type of functionality should either be
- +  * a) implemented via arch-specific pointers in platform_device
- +  * or
- +  * b) implemented as a proper omap_bus/omap_device in Linux, no more
- +  *    platform_device
- +  *
- +  * omap_device differs from omap_hwmod in that it includes external
- +  * (e.g., board- and system-level) integration details.  omap_hwmod
- +  * stores hardware data that is invariant for a given OMAP chip.
- +  *
- +  * To do:
- +  * - GPIO integration
- +  * - regulator integration
- +  *
- +  */
- + #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_DEVICE_H
- + #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_DEVICE_H
- + 
- + #include <linux/kernel.h>
- + #include <linux/platform_device.h>
- + 
- + #include <plat/omap_hwmod.h>
- + 
- + extern struct device omap_device_parent;
- + 
- + /* omap_device._state values */
- + #define OMAP_DEVICE_STATE_UNKNOWN	0
- + #define OMAP_DEVICE_STATE_ENABLED	1
- + #define OMAP_DEVICE_STATE_IDLE		2
- + #define OMAP_DEVICE_STATE_SHUTDOWN	3
- + 
- + /* omap_device.flags values */
- + #define OMAP_DEVICE_SUSPENDED BIT(0)
- + #define OMAP_DEVICE_NO_IDLE_ON_SUSPEND BIT(1)
- + 
- + /**
- +  * struct omap_device - omap_device wrapper for platform_devices
- +  * @pdev: platform_device
- +  * @hwmods: (one .. many per omap_device)
- +  * @hwmods_cnt: ARRAY_SIZE() of @hwmods
- +  * @pm_lats: ptr to an omap_device_pm_latency table
- +  * @pm_lats_cnt: ARRAY_SIZE() of what is passed to @pm_lats
- +  * @pm_lat_level: array index of the last odpl entry executed - -1 if never
- +  * @dev_wakeup_lat: dev wakeup latency in nanoseconds
- +  * @_dev_wakeup_lat_limit: dev wakeup latency limit in nsec - set by OMAP PM
- +  * @_state: one of OMAP_DEVICE_STATE_* (see above)
- +  * @flags: device flags
- +  *
- +  * Integrates omap_hwmod data into Linux platform_device.
- +  *
- +  * Field names beginning with underscores are for the internal use of
- +  * the omap_device code.
- +  *
- +  */
- + struct omap_device {
- + 	struct platform_device		*pdev;
- + 	struct omap_hwmod		**hwmods;
- + 	struct omap_device_pm_latency	*pm_lats;
- + 	u32				dev_wakeup_lat;
- + 	u32				_dev_wakeup_lat_limit;
- + 	u8				pm_lats_cnt;
- + 	s8				pm_lat_level;
- + 	u8				hwmods_cnt;
- + 	u8				_state;
- + 	u8                              flags;
- + };
- + 
- + /* Device driver interface (call via platform_data fn ptrs) */
- + 
- + int omap_device_enable(struct platform_device *pdev);
- + int omap_device_idle(struct platform_device *pdev);
- + int omap_device_shutdown(struct platform_device *pdev);
- + 
- + /* Core code interface */
- + 
- + struct platform_device *omap_device_build(const char *pdev_name, int pdev_id,
- + 				      struct omap_hwmod *oh, void *pdata,
- + 				      int pdata_len,
- + 				      struct omap_device_pm_latency *pm_lats,
- + 				      int pm_lats_cnt, int is_early_device);
- + 
- + struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
- + 					 struct omap_hwmod **oh, int oh_cnt,
- + 					 void *pdata, int pdata_len,
- + 					 struct omap_device_pm_latency *pm_lats,
- + 					 int pm_lats_cnt, int is_early_device);
- + 
- + struct omap_device *omap_device_alloc(struct platform_device *pdev,
- + 				      struct omap_hwmod **ohs, int oh_cnt,
- + 				      struct omap_device_pm_latency *pm_lats,
- + 				      int pm_lats_cnt);
- + void omap_device_delete(struct omap_device *od);
- + int omap_device_register(struct platform_device *pdev);
- + 
- + void __iomem *omap_device_get_rt_va(struct omap_device *od);
- + struct device *omap_device_get_by_hwmod_name(const char *oh_name);
- + 
- + /* OMAP PM interface */
- + int omap_device_align_pm_lat(struct platform_device *pdev,
- + 			     u32 new_wakeup_lat_limit);
- + struct powerdomain *omap_device_get_pwrdm(struct omap_device *od);
- + int omap_device_get_context_loss_count(struct platform_device *pdev);
- + 
- + /* Other */
- + 
- + int omap_device_idle_hwmods(struct omap_device *od);
- + int omap_device_enable_hwmods(struct omap_device *od);
- + 
- + int omap_device_disable_clocks(struct omap_device *od);
- + int omap_device_enable_clocks(struct omap_device *od);
- + int omap_device_reset(struct device *dev);
- + 
- + /*
- +  * Entries should be kept in latency order ascending
- +  *
- +  * deact_lat is the maximum number of microseconds required to complete
- +  * deactivate_func() at the device's slowest OPP.
- +  *
- +  * act_lat is the maximum number of microseconds required to complete
- +  * activate_func() at the device's slowest OPP.
- +  *
- +  * This will result in some suboptimal power management decisions at fast
- +  * OPPs, but avoids having to recompute all device power management decisions
- +  * if the system shifts from a fast OPP to a slow OPP (in order to meet
- +  * latency requirements).
- +  *
- +  * XXX should deactivate_func/activate_func() take platform_device pointers
- +  * rather than omap_device pointers?
- +  */
- + struct omap_device_pm_latency {
- + 	u32 deactivate_lat;
- + 	u32 deactivate_lat_worst;
- + 	int (*deactivate_func)(struct omap_device *od);
- + 	u32 activate_lat;
- + 	u32 activate_lat_worst;
- + 	int (*activate_func)(struct omap_device *od);
- + 	u32 flags;
- + };
- + 
- + #define OMAP_DEVICE_LATENCY_AUTO_ADJUST BIT(1)
- + 
- + /* Get omap_device pointer from platform_device pointer */
- + static inline struct omap_device *to_omap_device(struct platform_device *pdev)
- + {
- + 	return pdev ? pdev->archdata.od : NULL;
- + }
- + 
- + static inline
- + void omap_device_disable_idle_on_suspend(struct platform_device *pdev)
- + {
- + 	struct omap_device *od = to_omap_device(pdev);
- + 
- + 	od->flags |= OMAP_DEVICE_NO_IDLE_ON_SUSPEND;
- + }
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/omap_hwmod.h linux-3.2.1/arch/arm/plat-ckb/include/plat/omap_hwmod.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/omap_hwmod.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/omap_hwmod.h	2014-05-15 13:25:14.142646404 +0900
- ***************
- *** 0 ****
- --- 1,659 ----
- + /*
- +  * omap_hwmod macros, structures
- +  *
- +  * Copyright (C) 2009-2011 Nokia Corporation
- +  * Copyright (C) 2011 Texas Instruments, Inc.
- +  * Paul Walmsley
- +  *
- +  * Created in collaboration with (alphabetical order): Benoît Cousson,
- +  * Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari
- +  * Poussa, Anand Sawant, Santosh Shilimkar, Richard Woodruff
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  *
- +  * These headers and macros are used to define OMAP on-chip module
- +  * data and their integration with other OMAP modules and Linux.
- +  * Copious documentation and references can also be found in the
- +  * omap_hwmod code, in arch/arm/mach-omap2/omap_hwmod.c (as of this
- +  * writing).
- +  *
- +  * To do:
- +  * - add interconnect error log structures
- +  * - add pinmuxing
- +  * - init_conn_id_bit (CONNID_BIT_VECTOR)
- +  * - implement default hwmod SMS/SDRC flags?
- +  * - move Linux-specific data ("non-ROM data") out
- +  *
- +  */
- + #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
- + #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
- + 
- + #include <linux/kernel.h>
- + #include <linux/init.h>
- + #include <linux/list.h>
- + #include <linux/ioport.h>
- + #include <linux/spinlock.h>
- + #include <plat/cpu.h>
- + 
- + struct omap_device;
- + 
- + extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1;
- + extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
- + extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3;
- + extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type4;
- + 
- + /*
- +  * OCP SYSCONFIG bit shifts/masks TYPE1. These are for IPs compliant
- +  * with the original PRCM protocol defined for OMAP2420
- +  */
- + #define SYSC_TYPE1_MIDLEMODE_SHIFT	12
- + #define SYSC_TYPE1_MIDLEMODE_MASK	(0x3 << SYSC_MIDLEMODE_SHIFT)
- + #define SYSC_TYPE1_CLOCKACTIVITY_SHIFT	8
- + #define SYSC_TYPE1_CLOCKACTIVITY_MASK	(0x3 << SYSC_CLOCKACTIVITY_SHIFT)
- + #define SYSC_TYPE1_SIDLEMODE_SHIFT	3
- + #define SYSC_TYPE1_SIDLEMODE_MASK	(0x3 << SYSC_SIDLEMODE_SHIFT)
- + #define SYSC_TYPE1_ENAWAKEUP_SHIFT	2
- + #define SYSC_TYPE1_ENAWAKEUP_MASK	(1 << SYSC_ENAWAKEUP_SHIFT)
- + #define SYSC_TYPE1_SOFTRESET_SHIFT	1
- + #define SYSC_TYPE1_SOFTRESET_MASK	(1 << SYSC_SOFTRESET_SHIFT)
- + #define SYSC_TYPE1_AUTOIDLE_SHIFT	0
- + #define SYSC_TYPE1_AUTOIDLE_MASK	(1 << SYSC_AUTOIDLE_SHIFT)
- + 
- + /*
- +  * OCP SYSCONFIG bit shifts/masks TYPE2. These are for IPs compliant
- +  * with the new PRCM protocol defined for new OMAP4 IPs.
- +  */
- + #define SYSC_TYPE2_SOFTRESET_SHIFT	0
- + #define SYSC_TYPE2_SOFTRESET_MASK	(1 << SYSC_TYPE2_SOFTRESET_SHIFT)
- + #define SYSC_TYPE2_SIDLEMODE_SHIFT	2
- + #define SYSC_TYPE2_SIDLEMODE_MASK	(0x3 << SYSC_TYPE2_SIDLEMODE_SHIFT)
- + #define SYSC_TYPE2_MIDLEMODE_SHIFT	4
- + #define SYSC_TYPE2_MIDLEMODE_MASK	(0x3 << SYSC_TYPE2_MIDLEMODE_SHIFT)
- + 
- + /*
- +  * OCP SYSCONFIG bit shifts/masks TYPE3.
- +  * This is applicable for some IPs present in AM33XX
- +  */
- + #define SYSC_TYPE3_SIDLEMODE_SHIFT	0
- + #define SYSC_TYPE3_SIDLEMODE_MASK	(0x3 << SYSC_TYPE3_SIDLEMODE_SHIFT)
- + #define SYSC_TYPE3_MIDLEMODE_SHIFT	2
- + #define SYSC_TYPE3_MIDLEMODE_MASK	(0x3 << SYSC_TYPE3_MIDLEMODE_SHIFT)
- + 
- + /*
- +  * OCP SYSCONFIG bit shifts/masks TYPE4.
- +  * This is applicable for some IPs present in AM33XX
- +  */
- + #define SYSC_TYPE4_CLOCKACTIVITY_SHIFT	8
- + #define SYSC_TYPE4_CLOCKACTIVITY_MASK	(0x3 << SYSC_CLOCKACTIVITY_SHIFT)
- + #define SYSC_TYPE4_MIDLEMODE_SHIFT	5
- + #define SYSC_TYPE4_MIDLEMODE_MASK	(0x3 << SYSC_MIDLEMODE_SHIFT)
- + #define SYSC_TYPE4_SIDLEMODE_SHIFT	3
- + #define SYSC_TYPE4_SIDLEMODE_MASK	(0x3 << SYSC_SIDLEMODE_SHIFT)
- + #define SYSC_TYPE4_ENAWAKEUP_SHIFT	2
- + #define SYSC_TYPE4_ENAWAKEUP_MASK	(1 << SYSC_ENAWAKEUP_SHIFT)
- + #define SYSC_TYPE4_SOFTRESET_SHIFT	1
- + #define SYSC_TYPE4_SOFTRESET_MASK	(1 << SYSC_SOFTRESET_SHIFT)
- + #define SYSC_TYPE4_AUTOIDLE_SHIFT	0
- + #define SYSC_TYPE4_AUTOIDLE_MASK	(1 << SYSC_AUTOIDLE_SHIFT)
- + 
- + /* OCP SYSSTATUS bit shifts/masks */
- + #define SYSS_RESETDONE_SHIFT		0
- + #define SYSS_RESETDONE_MASK		(1 << SYSS_RESETDONE_SHIFT)
- + 
- + /* Master standby/slave idle mode flags */
- + #define HWMOD_IDLEMODE_FORCE		(1 << 0)
- + #define HWMOD_IDLEMODE_NO		(1 << 1)
- + #define HWMOD_IDLEMODE_SMART		(1 << 2)
- + #define HWMOD_IDLEMODE_SMART_WKUP	(1 << 3)
- + 
- + /* modulemode control type (SW or HW) */
- + #define MODULEMODE_HWCTRL		1
- + #define MODULEMODE_SWCTRL		2
- + 
- + 
- + /**
- +  * struct omap_hwmod_mux_info - hwmod specific mux configuration
- +  * @pads:              array of omap_device_pad entries
- +  * @nr_pads:           number of omap_device_pad entries
- +  *
- +  * Note that this is currently built during init as needed.
- +  */
- + struct omap_hwmod_mux_info {
- + 	int				nr_pads;
- + 	struct omap_device_pad		*pads;
- + 	int				nr_pads_dynamic;
- + 	struct omap_device_pad		**pads_dynamic;
- + 	int				*irqs;
- + 	bool				enabled;
- + };
- + 
- + /**
- +  * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod
- +  * @name: name of the IRQ channel (module local name)
- +  * @irq: IRQ channel ID (should be non-negative except -1 = terminator)
- +  *
- +  * @name should be something short, e.g., "tx" or "rx".  It is for use
- +  * by platform_get_resource_byname().  It is defined locally to the
- +  * hwmod.
- +  */
- + struct omap_hwmod_irq_info {
- + 	const char	*name;
- + 	s16		irq;
- + };
- + 
- + /**
- +  * struct omap_hwmod_dma_info - DMA channels used by the hwmod
- +  * @name: name of the DMA channel (module local name)
- +  * @dma_req: DMA request ID (should be non-negative except -1 = terminator)
- +  *
- +  * @name should be something short, e.g., "tx" or "rx".  It is for use
- +  * by platform_get_resource_byname().  It is defined locally to the
- +  * hwmod.
- +  */
- + struct omap_hwmod_dma_info {
- + 	const char	*name;
- + 	s16		dma_req;
- + };
- + 
- + /**
- +  * struct omap_hwmod_rst_info - IPs reset lines use by hwmod
- +  * @name: name of the reset line (module local name)
- +  * @rst_shift: Offset of the reset bit
- +  * @st_shift: Offset of the reset status bit (OMAP2/3 only)
- +  *
- +  * @name should be something short, e.g., "cpu0" or "rst". It is defined
- +  * locally to the hwmod.
- +  */
- + struct omap_hwmod_rst_info {
- + 	const char	*name;
- + 	u8		rst_shift;
- + 	u8		st_shift;
- + };
- + 
- + /**
- +  * struct omap_hwmod_opt_clk - optional clocks used by this hwmod
- +  * @role: "sys", "32k", "tv", etc -- for use in clk_get()
- +  * @clk: opt clock: OMAP clock name
- +  * @_clk: pointer to the struct clk (filled in at runtime)
- +  *
- +  * The module's interface clock and main functional clock should not
- +  * be added as optional clocks.
- +  */
- + struct omap_hwmod_opt_clk {
- + 	const char	*role;
- + 	const char	*clk;
- + 	struct clk	*_clk;
- + };
- + 
- + 
- + /* omap_hwmod_omap2_firewall.flags bits */
- + #define OMAP_FIREWALL_L3		(1 << 0)
- + #define OMAP_FIREWALL_L4		(1 << 1)
- + 
- + /**
- +  * struct omap_hwmod_omap2_firewall - OMAP2/3 device firewall data
- +  * @l3_perm_bit: bit shift for L3_PM_*_PERMISSION_*
- +  * @l4_fw_region: L4 firewall region ID
- +  * @l4_prot_group: L4 protection group ID
- +  * @flags: (see omap_hwmod_omap2_firewall.flags macros above)
- +  */
- + struct omap_hwmod_omap2_firewall {
- + 	u8 l3_perm_bit;
- + 	u8 l4_fw_region;
- + 	u8 l4_prot_group;
- + 	u8 flags;
- + };
- + 
- + 
- + /*
- +  * omap_hwmod_addr_space.flags bits
- +  *
- +  * ADDR_MAP_ON_INIT: Map this address space during omap_hwmod init.
- +  * ADDR_TYPE_RT: Address space contains module register target data.
- +  */
- + #define ADDR_MAP_ON_INIT	(1 << 0)	/* XXX does not belong */
- + #define ADDR_TYPE_RT		(1 << 1)
- + 
- + /**
- +  * struct omap_hwmod_addr_space - address space handled by the hwmod
- +  * @name: name of the address space
- +  * @pa_start: starting physical address
- +  * @pa_end: ending physical address
- +  * @flags: (see omap_hwmod_addr_space.flags macros above)
- +  *
- +  * Address space doesn't necessarily follow physical interconnect
- +  * structure.  GPMC is one example.
- +  */
- + struct omap_hwmod_addr_space {
- + 	const char *name;
- + 	u32 pa_start;
- + 	u32 pa_end;
- + 	u8 flags;
- + };
- + 
- + 
- + /*
- +  * omap_hwmod_ocp_if.user bits: these indicate the initiators that use this
- +  * interface to interact with the hwmod.  Used to add sleep dependencies
- +  * when the module is enabled or disabled.
- +  */
- + #define OCP_USER_MPU			(1 << 0)
- + #define OCP_USER_SDMA			(1 << 1)
- + 
- + /* omap_hwmod_ocp_if.flags bits */
- + #define OCPIF_SWSUP_IDLE		(1 << 0)
- + #define OCPIF_CAN_BURST			(1 << 1)
- + 
- + /**
- +  * struct omap_hwmod_ocp_if - OCP interface data
- +  * @master: struct omap_hwmod that initiates OCP transactions on this link
- +  * @slave: struct omap_hwmod that responds to OCP transactions on this link
- +  * @addr: address space associated with this link
- +  * @clk: interface clock: OMAP clock name
- +  * @_clk: pointer to the interface struct clk (filled in at runtime)
- +  * @fw: interface firewall data
- +  * @width: OCP data width
- +  * @user: initiators using this interface (see OCP_USER_* macros above)
- +  * @flags: OCP interface flags (see OCPIF_* macros above)
- +  *
- +  * It may also be useful to add a tag_cnt field for OCP2.x devices.
- +  *
- +  * Parameter names beginning with an underscore are managed internally by
- +  * the omap_hwmod code and should not be set during initialization.
- +  */
- + struct omap_hwmod_ocp_if {
- + 	struct omap_hwmod		*master;
- + 	struct omap_hwmod		*slave;
- + 	struct omap_hwmod_addr_space	*addr;
- + 	const char			*clk;
- + 	struct clk			*_clk;
- + 	union {
- + 		struct omap_hwmod_omap2_firewall omap2;
- + 	}				fw;
- + 	u8				width;
- + 	u8				user;
- + 	u8				flags;
- + };
- + 
- + 
- + /* Macros for use in struct omap_hwmod_sysconfig */
- + 
- + /* Flags for use in omap_hwmod_sysconfig.idlemodes */
- + #define MASTER_STANDBY_SHIFT	4
- + #define SLAVE_IDLE_SHIFT	0
- + #define SIDLE_FORCE		(HWMOD_IDLEMODE_FORCE << SLAVE_IDLE_SHIFT)
- + #define SIDLE_NO		(HWMOD_IDLEMODE_NO << SLAVE_IDLE_SHIFT)
- + #define SIDLE_SMART		(HWMOD_IDLEMODE_SMART << SLAVE_IDLE_SHIFT)
- + #define SIDLE_SMART_WKUP	(HWMOD_IDLEMODE_SMART_WKUP << SLAVE_IDLE_SHIFT)
- + #define MSTANDBY_FORCE		(HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT)
- + #define MSTANDBY_NO		(HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT)
- + #define MSTANDBY_SMART		(HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT)
- + #define MSTANDBY_SMART_WKUP	(HWMOD_IDLEMODE_SMART_WKUP << MASTER_STANDBY_SHIFT)
- + 
- + /* omap_hwmod_sysconfig.sysc_flags capability flags */
- + #define SYSC_HAS_AUTOIDLE	(1 << 0)
- + #define SYSC_HAS_SOFTRESET	(1 << 1)
- + #define SYSC_HAS_ENAWAKEUP	(1 << 2)
- + #define SYSC_HAS_EMUFREE	(1 << 3)
- + #define SYSC_HAS_CLOCKACTIVITY	(1 << 4)
- + #define SYSC_HAS_SIDLEMODE	(1 << 5)
- + #define SYSC_HAS_MIDLEMODE	(1 << 6)
- + #define SYSS_HAS_RESET_STATUS	(1 << 7)
- + #define SYSC_NO_CACHE		(1 << 8)  /* XXX SW flag, belongs elsewhere */
- + #define SYSC_HAS_RESET_STATUS	(1 << 9)
- + 
- + /* omap_hwmod_sysconfig.clockact flags */
- + #define CLOCKACT_TEST_BOTH	0x0
- + #define CLOCKACT_TEST_MAIN	0x1
- + #define CLOCKACT_TEST_ICLK	0x2
- + #define CLOCKACT_TEST_NONE	0x3
- + 
- + /**
- +  * struct omap_hwmod_sysc_fields - hwmod OCP_SYSCONFIG register field offsets.
- +  * @midle_shift: Offset of the midle bit
- +  * @clkact_shift: Offset of the clockactivity bit
- +  * @sidle_shift: Offset of the sidle bit
- +  * @enwkup_shift: Offset of the enawakeup bit
- +  * @srst_shift: Offset of the softreset bit
- +  * @autoidle_shift: Offset of the autoidle bit
- +  */
- + struct omap_hwmod_sysc_fields {
- + 	u8 midle_shift;
- + 	u8 clkact_shift;
- + 	u8 sidle_shift;
- + 	u8 enwkup_shift;
- + 	u8 srst_shift;
- + 	u8 autoidle_shift;
- + };
- + 
- + /**
- +  * struct omap_hwmod_class_sysconfig - hwmod class OCP_SYS* data
- +  * @rev_offs: IP block revision register offset (from module base addr)
- +  * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr)
- +  * @syss_offs: OCP_SYSSTATUS register offset (from module base addr)
- +  * @rst_offs: OCP_SOFTRST register offset (from module base addr)
- +  * @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART}
- +  * @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported
- +  * @clockact: the default value of the module CLOCKACTIVITY bits
- +  *
- +  * @clockact describes to the module which clocks are likely to be
- +  * disabled when the PRCM issues its idle request to the module.  Some
- +  * modules have separate clockdomains for the interface clock and main
- +  * functional clock, and can check whether they should acknowledge the
- +  * idle request based on the internal module functionality that has
- +  * been associated with the clocks marked in @clockact.  This field is
- +  * only used if HWMOD_SET_DEFAULT_CLOCKACT is set (see below)
- +  *
- +  * @sysc_fields: structure containing the offset positions of various bits in
- +  * SYSCONFIG register. This can be populated using omap_hwmod_sysc_type1 or
- +  * omap_hwmod_sysc_type2 defined in omap_hwmod_common_data.c depending on
- +  * whether the device ip is compliant with the original PRCM protocol
- +  * defined for OMAP2420 or the new PRCM protocol for new OMAP4 IPs.
- +  * If the device follows a different scheme for the sysconfig register ,
- +  * then this field has to be populated with the correct offset structure.
- +  */
- + struct omap_hwmod_class_sysconfig {
- + 	u16 rev_offs;
- + 	u16 sysc_offs;
- + 	u16 syss_offs;
- + 	u16 rst_offs;
- + 	u16 sysc_flags;
- + 	u8 idlemodes;
- + 	u8 clockact;
- + 	struct omap_hwmod_sysc_fields *sysc_fields;
- + };
- + 
- + /**
- +  * struct omap_hwmod_omap2_prcm - OMAP2/3-specific PRCM data
- +  * @module_offs: PRCM submodule offset from the start of the PRM/CM
- +  * @prcm_reg_id: PRCM register ID (e.g., 3 for CM_AUTOIDLE3)
- +  * @module_bit: register bit shift for AUTOIDLE, WKST, WKEN, GRPSEL regs
- +  * @idlest_reg_id: IDLEST register ID (e.g., 3 for CM_IDLEST3)
- +  * @idlest_idle_bit: register bit shift for CM_IDLEST slave idle bit
- +  * @idlest_stdby_bit: register bit shift for CM_IDLEST master standby bit
- +  *
- +  * @prcm_reg_id and @module_bit are specific to the AUTOIDLE, WKST,
- +  * WKEN, GRPSEL registers.  In an ideal world, no extra information
- +  * would be needed for IDLEST information, but alas, there are some
- +  * exceptions, so @idlest_reg_id, @idlest_idle_bit, @idlest_stdby_bit
- +  * are needed for the IDLEST registers (c.f. 2430 I2CHS, 3430 USBHOST)
- +  */
- + struct omap_hwmod_omap2_prcm {
- + 	s16 module_offs;
- + 	u8 prcm_reg_id;
- + 	u8 module_bit;
- + 	u8 idlest_reg_id;
- + 	u8 idlest_idle_bit;
- + 	u8 idlest_stdby_bit;
- + };
- + 
- + 
- + /**
- +  * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
- +  * @clkctrl_reg: PRCM address of the clock control register
- +  * @rstctrl_reg: address of the XXX_RSTCTRL register located in the PRM
- +  * @rstst_reg: address of the XXX_RSTST register located in the PRM
- +  * @submodule_wkdep_bit: bit shift of the WKDEP range
- +  */
- + struct omap_hwmod_omap4_prcm {
- + 	u16		clkctrl_offs;
- + 	u16		rstctrl_offs;
- + 	u16		rstst_offs;
- + 	u16		context_offs;
- + 	u8		submodule_wkdep_bit;
- + 	u8		modulemode;
- + };
- + 
- + 
- + /*
- +  * omap_hwmod.flags definitions
- +  *
- +  * HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out
- +  *     of idle, rather than relying on module smart-idle
- +  * HWMOD_SWSUP_MSTDBY: omap_hwmod code should manually bring module in and out
- +  *     of standby, rather than relying on module smart-standby
- +  * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for
- +  *     SDRAM controller, etc. XXX probably belongs outside the main hwmod file
- +  *     XXX Should be HWMOD_SETUP_NO_RESET
- +  * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM
- +  *     controller, etc. XXX probably belongs outside the main hwmod file
- +  *     XXX Should be HWMOD_SETUP_NO_IDLE
- +  * HWMOD_NO_OCP_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE)
- +  *     when module is enabled, rather than the default, which is to
- +  *     enable autoidle
- +  * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup
- +  * HWMOD_NO_IDLEST: this module does not have idle status - this is the case
- +  *     only for few initiator modules on OMAP2 & 3.
- +  * HWMOD_CONTROL_OPT_CLKS_IN_RESET: Enable all optional clocks during reset.
- +  *     This is needed for devices like DSS that require optional clocks enabled
- +  *     in order to complete the reset. Optional clocks will be disabled
- +  *     again after the reset.
- +  * HWMOD_16BIT_REG: Module has 16bit registers
- +  * HWMOD_SWSUP_RESET_BEFORE_IDLE: omap_hwmod code should assert the ocp_reset before
- +  *     idling/disabling the module.
- +  */
- + #define HWMOD_SWSUP_SIDLE			(1 << 0)
- + #define HWMOD_SWSUP_MSTANDBY			(1 << 1)
- + #define HWMOD_INIT_NO_RESET			(1 << 2)
- + #define HWMOD_INIT_NO_IDLE			(1 << 3)
- + #define HWMOD_NO_OCP_AUTOIDLE			(1 << 4)
- + #define HWMOD_SET_DEFAULT_CLOCKACT		(1 << 5)
- + #define HWMOD_NO_IDLEST				(1 << 6)
- + #define HWMOD_CONTROL_OPT_CLKS_IN_RESET		(1 << 7)
- + #define HWMOD_16BIT_REG				(1 << 8)
- + #define HWMOD_SWSUP_RESET_BEFORE_IDLE		(1 << 9)
- + 
- + /*
- +  * omap_hwmod._int_flags definitions
- +  * These are for internal use only and are managed by the omap_hwmod code.
- +  *
- +  * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module
- +  * _HWMOD_WAKEUP_ENABLED: set when the omap_hwmod code has enabled ENAWAKEUP
- +  * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached
- +  * _HWMOD_SKIP_ENABLE: set if hwmod enabled during init (HWMOD_INIT_NO_IDLE) -
- +  *     causes the first call to _enable() to only update the pinmux
- +  */
- + #define _HWMOD_NO_MPU_PORT			(1 << 0)
- + #define _HWMOD_WAKEUP_ENABLED			(1 << 1)
- + #define _HWMOD_SYSCONFIG_LOADED			(1 << 2)
- + #define _HWMOD_SKIP_ENABLE			(1 << 3)
- + 
- + /*
- +  * omap_hwmod._state definitions
- +  *
- +  * INITIALIZED: reset (optionally), initialized, enabled, disabled
- +  *              (optionally)
- +  *
- +  *
- +  */
- + #define _HWMOD_STATE_UNKNOWN			0
- + #define _HWMOD_STATE_REGISTERED			1
- + #define _HWMOD_STATE_CLKS_INITED		2
- + #define _HWMOD_STATE_INITIALIZED		3
- + #define _HWMOD_STATE_ENABLED			4
- + #define _HWMOD_STATE_IDLE			5
- + #define _HWMOD_STATE_DISABLED			6
- + 
- + /**
- +  * struct omap_hwmod_class - the type of an IP block
- +  * @name: name of the hwmod_class
- +  * @sysc: device SYSCONFIG/SYSSTATUS register data
- +  * @rev: revision of the IP class
- +  * @pre_shutdown: ptr to fn to be executed immediately prior to device shutdown
- +  * @reset: ptr to fn to be executed in place of the standard hwmod reset fn
- +  *
- +  * Represent the class of a OMAP hardware "modules" (e.g. timer,
- +  * smartreflex, gpio, uart...)
- +  *
- +  * @pre_shutdown is a function that will be run immediately before
- +  * hwmod clocks are disabled, etc.  It is intended for use for hwmods
- +  * like the MPU watchdog, which cannot be disabled with the standard
- +  * omap_hwmod_shutdown().  The function should return 0 upon success,
- +  * or some negative error upon failure.  Returning an error will cause
- +  * omap_hwmod_shutdown() to abort the device shutdown and return an
- +  * error.
- +  *
- +  * If @reset is defined, then the function it points to will be
- +  * executed in place of the standard hwmod _reset() code in
- +  * mach-omap2/omap_hwmod.c.  This is needed for IP blocks which have
- +  * unusual reset sequences - usually processor IP blocks like the IVA.
- +  */
- + struct omap_hwmod_class {
- + 	const char				*name;
- + 	struct omap_hwmod_class_sysconfig	*sysc;
- + 	u32					rev;
- + 	int					(*pre_shutdown)(struct omap_hwmod *oh);
- + 	int					(*reset)(struct omap_hwmod *oh);
- + };
- + 
- + /**
- +  * struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks)
- +  * @name: name of the hwmod
- +  * @class: struct omap_hwmod_class * to the class of this hwmod
- +  * @od: struct omap_device currently associated with this hwmod (internal use)
- +  * @mpu_irqs: ptr to an array of MPU IRQs
- +  * @sdma_reqs: ptr to an array of System DMA request IDs
- +  * @prcm: PRCM data pertaining to this hwmod
- +  * @main_clk: main clock: OMAP clock name
- +  * @_clk: pointer to the main struct clk (filled in at runtime)
- +  * @opt_clks: other device clocks that drivers can request (0..*)
- +  * @vdd_name: voltage domain name
- +  * @voltdm: pointer to voltage domain (filled in at runtime)
- +  * @masters: ptr to array of OCP ifs that this hwmod can initiate on
- +  * @slaves: ptr to array of OCP ifs that this hwmod can respond on
- +  * @dev_attr: arbitrary device attributes that can be passed to the driver
- +  * @_sysc_cache: internal-use hwmod flags
- +  * @_mpu_rt_va: cached register target start address (internal use)
- +  * @_mpu_port_index: cached MPU register target slave ID (internal use)
- +  * @opt_clks_cnt: number of @opt_clks
- +  * @master_cnt: number of @master entries
- +  * @slaves_cnt: number of @slave entries
- +  * @response_lat: device OCP response latency (in interface clock cycles)
- +  * @_int_flags: internal-use hwmod flags
- +  * @_state: internal-use hwmod state
- +  * @_postsetup_state: internal-use state to leave the hwmod in after _setup()
- +  * @flags: hwmod flags (documented below)
- +  * @_lock: spinlock serializing operations on this hwmod
- +  * @node: list node for hwmod list (internal use)
- +  *
- +  * @main_clk refers to this module's "main clock," which for our
- +  * purposes is defined as "the functional clock needed for register
- +  * accesses to complete."  Modules may not have a main clock if the
- +  * interface clock also serves as a main clock.
- +  *
- +  * Parameter names beginning with an underscore are managed internally by
- +  * the omap_hwmod code and should not be set during initialization.
- +  */
- + struct omap_hwmod {
- + 	const char			*name;
- + 	struct omap_hwmod_class		*class;
- + 	struct omap_device		*od;
- + 	struct omap_hwmod_mux_info	*mux;
- + 	struct omap_hwmod_irq_info	*mpu_irqs;
- + 	struct omap_hwmod_dma_info	*sdma_reqs;
- + 	struct omap_hwmod_rst_info	*rst_lines;
- + 	union {
- + 		struct omap_hwmod_omap2_prcm omap2;
- + 		struct omap_hwmod_omap4_prcm omap4;
- + 	}				prcm;
- + 	const char			*main_clk;
- + 	struct clk			*_clk;
- + 	struct omap_hwmod_opt_clk	*opt_clks;
- + 	char				*clkdm_name;
- + 	struct clockdomain		*clkdm;
- + 	char				*vdd_name;
- + 	struct omap_hwmod_ocp_if	**masters; /* connect to *_IA */
- + 	struct omap_hwmod_ocp_if	**slaves;  /* connect to *_TA */
- + 	void				*dev_attr;
- + 	u32				_sysc_cache;
- + 	void __iomem			*_mpu_rt_va;
- + 	spinlock_t			_lock;
- + 	struct list_head		node;
- + 	u16				flags;
- + 	u8				_mpu_port_index;
- + 	u8				response_lat;
- + 	u8				rst_lines_cnt;
- + 	u8				opt_clks_cnt;
- + 	u8				masters_cnt;
- + 	u8				slaves_cnt;
- + 	u8				hwmods_cnt;
- + 	u8				_int_flags;
- + 	u8				_state;
- + 	u8				_postsetup_state;
- + };
- + 
- + int omap_hwmod_register(struct omap_hwmod **ohs);
- + struct omap_hwmod *omap_hwmod_lookup(const char *name);
- + int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
- + 			void *data);
- + 
- + int __init omap_hwmod_setup_one(const char *name);
- + 
- + int omap_hwmod_enable(struct omap_hwmod *oh);
- + int _omap_hwmod_enable(struct omap_hwmod *oh);
- + int omap_hwmod_idle(struct omap_hwmod *oh);
- + int _omap_hwmod_idle(struct omap_hwmod *oh);
- + int omap_hwmod_shutdown(struct omap_hwmod *oh);
- + 
- + int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name);
- + int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name);
- + int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name);
- + 
- + int omap_hwmod_enable_clocks(struct omap_hwmod *oh);
- + int omap_hwmod_disable_clocks(struct omap_hwmod *oh);
- + 
- + int omap_hwmod_set_master_standbymode(struct omap_hwmod *oh, u8 idlemode);
- + int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode);
- + int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle);
- + 
- + int omap_hwmod_reset(struct omap_hwmod *oh);
- + void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);
- + 
- + void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs);
- + u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs);
- + int omap_hwmod_softreset(struct omap_hwmod *oh);
- + 
- + int omap_hwmod_count_resources(struct omap_hwmod *oh);
- + int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
- + 
- + struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh);
- + void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh);
- + 
- + int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh,
- + 				 struct omap_hwmod *init_oh);
- + int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh,
- + 				 struct omap_hwmod *init_oh);
- + 
- + int omap_hwmod_set_clockact_both(struct omap_hwmod *oh);
- + int omap_hwmod_set_clockact_main(struct omap_hwmod *oh);
- + int omap_hwmod_set_clockact_iclk(struct omap_hwmod *oh);
- + int omap_hwmod_set_clockact_none(struct omap_hwmod *oh);
- + 
- + int omap_hwmod_enable_wakeup(struct omap_hwmod *oh);
- + int omap_hwmod_disable_wakeup(struct omap_hwmod *oh);
- + 
- + int omap_hwmod_for_each_by_class(const char *classname,
- + 				 int (*fn)(struct omap_hwmod *oh,
- + 					   void *user),
- + 				 void *user);
- + 
- + int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state);
- + int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh);
- + 
- + int omap_hwmod_no_setup_reset(struct omap_hwmod *oh);
- + 
- + int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx);
- + 
- + /*
- +  * Chip variant-specific hwmod init routines - XXX should be converted
- +  * to use initcalls once the initial boot ordering is straightened out
- +  */
- + extern int omap2420_hwmod_init(void);
- + extern int omap2430_hwmod_init(void);
- + extern int omap3xxx_hwmod_init(void);
- + extern int omap44xx_hwmod_init(void);
- + extern int am33xx_hwmod_init(void);
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/omap-pm.h linux-3.2.1/arch/arm/plat-ckb/include/plat/omap-pm.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/omap-pm.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/omap-pm.h	2014-05-15 13:25:14.142646404 +0900
- ***************
- *** 0 ****
- --- 1,352 ----
- + /*
- +  * omap-pm.h - OMAP power management interface
- +  *
- +  * Copyright (C) 2008-2010 Texas Instruments, Inc.
- +  * Copyright (C) 2008-2010 Nokia Corporation
- +  * Paul Walmsley
- +  *
- +  * Interface developed by (in alphabetical order): Karthik Dasu, Jouni
- +  * Högander, Tony Lindgren, Rajendra Nayak, Sakari Poussa,
- +  * Veeramanikandan Raju, Anand Sawant, Igor Stoppa, Paul Walmsley,
- +  * Richard Woodruff
- +  */
- + 
- + #ifndef ASM_ARM_ARCH_OMAP_OMAP_PM_H
- + #define ASM_ARM_ARCH_OMAP_OMAP_PM_H
- + 
- + #include <linux/device.h>
- + #include <linux/cpufreq.h>
- + #include <linux/clk.h>
- + #include <linux/opp.h>
- + 
- + /*
- +  * agent_id values for use with omap_pm_set_min_bus_tput():
- +  *
- +  * OCP_INITIATOR_AGENT is only valid for devices that can act as
- +  * initiators -- it represents the device's L3 interconnect
- +  * connection.  OCP_TARGET_AGENT represents the device's L4
- +  * interconnect connection.
- +  */
- + #define OCP_TARGET_AGENT		1
- + #define OCP_INITIATOR_AGENT		2
- + 
- + /**
- +  * omap_pm_if_early_init - OMAP PM init code called before clock fw init
- +  * @mpu_opp_table: array ptr to struct omap_opp for MPU
- +  * @dsp_opp_table: array ptr to struct omap_opp for DSP
- +  * @l3_opp_table : array ptr to struct omap_opp for CORE
- +  *
- +  * Initialize anything that must be configured before the clock
- +  * framework starts.  The "_if_" is to avoid name collisions with the
- +  * PM idle-loop code.
- +  */
- + int __init omap_pm_if_early_init(void);
- + 
- + /**
- +  * omap_pm_if_init - OMAP PM init code called after clock fw init
- +  *
- +  * The main initialization code.  OPP tables are passed in here.  The
- +  * "_if_" is to avoid name collisions with the PM idle-loop code.
- +  */
- + int __init omap_pm_if_init(void);
- + 
- + /**
- +  * omap_pm_if_exit - OMAP PM exit code
- +  *
- +  * Exit code; currently unused.  The "_if_" is to avoid name
- +  * collisions with the PM idle-loop code.
- +  */
- + void omap_pm_if_exit(void);
- + 
- + /*
- +  * Device-driver-originated constraints (via board-*.c files, platform_data)
- +  */
- + 
- + 
- + /**
- +  * omap_pm_set_max_mpu_wakeup_lat - set the maximum MPU wakeup latency
- +  * @dev: struct device * requesting the constraint
- +  * @t: maximum MPU wakeup latency in microseconds
- +  *
- +  * Request that the maximum interrupt latency for the MPU to be no
- +  * greater than @t microseconds. "Interrupt latency" in this case is
- +  * defined as the elapsed time from the occurrence of a hardware or
- +  * timer interrupt to the time when the device driver's interrupt
- +  * service routine has been entered by the MPU.
- +  *
- +  * It is intended that underlying PM code will use this information to
- +  * determine what power state to put the MPU powerdomain into, and
- +  * possibly the CORE powerdomain as well, since interrupt handling
- +  * code currently runs from SDRAM.  Advanced PM or board*.c code may
- +  * also configure interrupt controller priorities, OCP bus priorities,
- +  * CPU speed(s), etc.
- +  *
- +  * This function will not affect device wakeup latency, e.g., time
- +  * elapsed from when a device driver enables a hardware device with
- +  * clk_enable(), to when the device is ready for register access or
- +  * other use.  To control this device wakeup latency, use
- +  * omap_pm_set_max_dev_wakeup_lat()
- +  *
- +  * Multiple calls to omap_pm_set_max_mpu_wakeup_lat() will replace the
- +  * previous t value.  To remove the latency target for the MPU, call
- +  * with t = -1.
- +  *
- +  * XXX This constraint will be deprecated soon in favor of the more
- +  * general omap_pm_set_max_dev_wakeup_lat()
- +  *
- +  * Returns -EINVAL for an invalid argument, -ERANGE if the constraint
- +  * is not satisfiable, or 0 upon success.
- +  */
- + int omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t);
- + 
- + 
- + /**
- +  * omap_pm_set_min_bus_tput - set minimum bus throughput needed by device
- +  * @dev: struct device * requesting the constraint
- +  * @tbus_id: interconnect to operate on (OCP_{INITIATOR,TARGET}_AGENT)
- +  * @r: minimum throughput (in KiB/s)
- +  *
- +  * Request that the minimum data throughput on the OCP interconnect
- +  * attached to device @dev interconnect agent @tbus_id be no less
- +  * than @r KiB/s.
- +  *
- +  * It is expected that the OMAP PM or bus code will use this
- +  * information to set the interconnect clock to run at the lowest
- +  * possible speed that satisfies all current system users.  The PM or
- +  * bus code will adjust the estimate based on its model of the bus, so
- +  * device driver authors should attempt to specify an accurate
- +  * quantity for their device use case, and let the PM or bus code
- +  * overestimate the numbers as necessary to handle request/response
- +  * latency, other competing users on the system, etc.  On OMAP2/3, if
- +  * a driver requests a minimum L4 interconnect speed constraint, the
- +  * code will also need to add an minimum L3 interconnect speed
- +  * constraint,
- +  *
- +  * Multiple calls to omap_pm_set_min_bus_tput() will replace the
- +  * previous rate value for this device.  To remove the interconnect
- +  * throughput restriction for this device, call with r = 0.
- +  *
- +  * Returns -EINVAL for an invalid argument, -ERANGE if the constraint
- +  * is not satisfiable, or 0 upon success.
- +  */
- + int omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r);
- + 
- + 
- + /**
- +  * omap_pm_set_max_dev_wakeup_lat - set the maximum device enable latency
- +  * @req_dev: struct device * requesting the constraint, or NULL if none
- +  * @dev: struct device * to set the constraint one
- +  * @t: maximum device wakeup latency in microseconds
- +  *
- +  * Request that the maximum amount of time necessary for a device @dev
- +  * to become accessible after its clocks are enabled should be no
- +  * greater than @t microseconds.  Specifically, this represents the
- +  * time from when a device driver enables device clocks with
- +  * clk_enable(), to when the register reads and writes on the device
- +  * will succeed.  This function should be called before clk_disable()
- +  * is called, since the power state transition decision may be made
- +  * during clk_disable().
- +  *
- +  * It is intended that underlying PM code will use this information to
- +  * determine what power state to put the powerdomain enclosing this
- +  * device into.
- +  *
- +  * Multiple calls to omap_pm_set_max_dev_wakeup_lat() will replace the
- +  * previous wakeup latency values for this device.  To remove the
- +  * wakeup latency restriction for this device, call with t = -1.
- +  *
- +  * Returns -EINVAL for an invalid argument, -ERANGE if the constraint
- +  * is not satisfiable, or 0 upon success.
- +  */
- + int omap_pm_set_max_dev_wakeup_lat(struct device *req_dev, struct device *dev,
- + 				   long t);
- + 
- + 
- + /**
- +  * omap_pm_set_max_sdma_lat - set the maximum system DMA transfer start latency
- +  * @dev: struct device *
- +  * @t: maximum DMA transfer start latency in microseconds
- +  *
- +  * Request that the maximum system DMA transfer start latency for this
- +  * device 'dev' should be no greater than 't' microseconds.  "DMA
- +  * transfer start latency" here is defined as the elapsed time from
- +  * when a device (e.g., McBSP) requests that a system DMA transfer
- +  * start or continue, to the time at which data starts to flow into
- +  * that device from the system DMA controller.
- +  *
- +  * It is intended that underlying PM code will use this information to
- +  * determine what power state to put the CORE powerdomain into.
- +  *
- +  * Since system DMA transfers may not involve the MPU, this function
- +  * will not affect MPU wakeup latency.  Use set_max_cpu_lat() to do
- +  * so.  Similarly, this function will not affect device wakeup latency
- +  * -- use set_max_dev_wakeup_lat() to affect that.
- +  *
- +  * Multiple calls to set_max_sdma_lat() will replace the previous t
- +  * value for this device.  To remove the maximum DMA latency for this
- +  * device, call with t = -1.
- +  *
- +  * Returns -EINVAL for an invalid argument, -ERANGE if the constraint
- +  * is not satisfiable, or 0 upon success.
- +  */
- + int omap_pm_set_max_sdma_lat(struct device *dev, long t);
- + 
- + 
- + /**
- +  * omap_pm_set_min_clk_rate - set minimum clock rate requested by @dev
- +  * @dev: struct device * requesting the constraint
- +  * @clk: struct clk * to set the minimum rate constraint on
- +  * @r: minimum rate in Hz
- +  *
- +  * Request that the minimum clock rate on the device @dev's clk @clk
- +  * be no less than @r Hz.
- +  *
- +  * It is expected that the OMAP PM code will use this information to
- +  * find an OPP or clock setting that will satisfy this clock rate
- +  * constraint, along with any other applicable system constraints on
- +  * the clock rate or corresponding voltage, etc.
- +  *
- +  * omap_pm_set_min_clk_rate() differs from the clock code's
- +  * clk_set_rate() in that it considers other constraints before taking
- +  * any hardware action, and may change a system OPP rather than just a
- +  * clock rate.  clk_set_rate() is intended to be a low-level
- +  * interface.
- +  *
- +  * omap_pm_set_min_clk_rate() is easily open to abuse.  A better API
- +  * would be something like "omap_pm_set_min_dev_performance()";
- +  * however, there is no easily-generalizable concept of performance
- +  * that applies to all devices.  Only a device (and possibly the
- +  * device subsystem) has both the subsystem-specific knowledge, and
- +  * the hardware IP block-specific knowledge, to translate a constraint
- +  * on "touchscreen sampling accuracy" or "number of pixels or polygons
- +  * rendered per second" to a clock rate.  This translation can be
- +  * dependent on the hardware IP block's revision, or firmware version,
- +  * and the driver is the only code on the system that has this
- +  * information and can know how to translate that into a clock rate.
- +  *
- +  * The intended use-case for this function is for userspace or other
- +  * kernel code to communicate a particular performance requirement to
- +  * a subsystem; then for the subsystem to communicate that requirement
- +  * to something that is meaningful to the device driver; then for the
- +  * device driver to convert that requirement to a clock rate, and to
- +  * then call omap_pm_set_min_clk_rate().
- +  *
- +  * Users of this function (such as device drivers) should not simply
- +  * call this function with some high clock rate to ensure "high
- +  * performance."  Rather, the device driver should take a performance
- +  * constraint from its subsystem, such as "render at least X polygons
- +  * per second," and use some formula or table to convert that into a
- +  * clock rate constraint given the hardware type and hardware
- +  * revision.  Device drivers or subsystems should not assume that they
- +  * know how to make a power/performance tradeoff - some device use
- +  * cases may tolerate a lower-fidelity device function for lower power
- +  * consumption; others may demand a higher-fidelity device function,
- +  * no matter what the power consumption.
- +  *
- +  * Multiple calls to omap_pm_set_min_clk_rate() will replace the
- +  * previous rate value for the device @dev.  To remove the minimum clock
- +  * rate constraint for the device, call with r = 0.
- +  *
- +  * Returns -EINVAL for an invalid argument, -ERANGE if the constraint
- +  * is not satisfiable, or 0 upon success.
- +  */
- + int omap_pm_set_min_clk_rate(struct device *dev, struct clk *c, long r);
- + 
- + /*
- +  * DSP Bridge-specific constraints
- +  */
- + 
- + /**
- +  * omap_pm_dsp_get_opp_table - get OPP->DSP clock frequency table
- +  *
- +  * Intended for use by DSPBridge.  Returns an array of OPP->DSP clock
- +  * frequency entries.  The final item in the array should have .rate =
- +  * .opp_id = 0.
- +  */
- + const struct omap_opp *omap_pm_dsp_get_opp_table(void);
- + 
- + /**
- +  * omap_pm_dsp_set_min_opp - receive desired OPP target ID from DSP Bridge
- +  * @opp_id: target DSP OPP ID
- +  *
- +  * Set a minimum OPP ID for the DSP.  This is intended to be called
- +  * only from the DSP Bridge MPU-side driver.  Unfortunately, the only
- +  * information that code receives from the DSP/BIOS load estimator is the
- +  * target OPP ID; hence, this interface.  No return value.
- +  */
- + void omap_pm_dsp_set_min_opp(u8 opp_id);
- + 
- + /**
- +  * omap_pm_dsp_get_opp - report the current DSP OPP ID
- +  *
- +  * Report the current OPP for the DSP.  Since on OMAP3, the DSP and
- +  * MPU share a single voltage domain, the OPP ID returned back may
- +  * represent a higher DSP speed than the OPP requested via
- +  * omap_pm_dsp_set_min_opp().
- +  *
- +  * Returns the current VDD1 OPP ID, or 0 upon error.
- +  */
- + u8 omap_pm_dsp_get_opp(void);
- + 
- + 
- + /*
- +  * CPUFreq-originated constraint
- +  *
- +  * In the future, this should be handled by custom OPP clocktype
- +  * functions.
- +  */
- + 
- + /**
- +  * omap_pm_cpu_get_freq_table - return a cpufreq_frequency_table array ptr
- +  *
- +  * Provide a frequency table usable by CPUFreq for the current chip/board.
- +  * Returns a pointer to a struct cpufreq_frequency_table array or NULL
- +  * upon error.
- +  */
- + struct cpufreq_frequency_table **omap_pm_cpu_get_freq_table(void);
- + 
- + /**
- +  * omap_pm_cpu_set_freq - set the current minimum MPU frequency
- +  * @f: MPU frequency in Hz
- +  *
- +  * Set the current minimum CPU frequency.  The actual CPU frequency
- +  * used could end up higher if the DSP requested a higher OPP.
- +  * Intended to be called by plat-omap/cpu_omap.c:omap_target().  No
- +  * return value.
- +  */
- + void omap_pm_cpu_set_freq(unsigned long f);
- + 
- + /**
- +  * omap_pm_cpu_get_freq - report the current CPU frequency
- +  *
- +  * Returns the current MPU frequency, or 0 upon error.
- +  */
- + unsigned long omap_pm_cpu_get_freq(void);
- + 
- + 
- + /*
- +  * Device context loss tracking
- +  */
- + 
- + /**
- +  * omap_pm_get_dev_context_loss_count - return count of times dev has lost ctx
- +  * @dev: struct device *
- +  *
- +  * This function returns the number of times that the device @dev has
- +  * lost its internal context.  This generally occurs on a powerdomain
- +  * transition to OFF.  Drivers use this as an optimization to avoid restoring
- +  * context if the device hasn't lost it.  To use, drivers should initially
- +  * call this in their context save functions and store the result.  Early in
- +  * the driver's context restore function, the driver should call this function
- +  * again, and compare the result to the stored counter.  If they differ, the
- +  * driver must restore device context.   If the number of context losses
- +  * exceeds the maximum positive integer, the function will wrap to 0 and
- +  * continue counting.  Returns the number of context losses for this device,
- +  * or negative value upon error.
- +  */
- + int omap_pm_get_dev_context_loss_count(struct device *dev);
- + 
- + void omap_pm_enable_off_mode(void);
- + void omap_pm_disable_off_mode(void);
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/omap-serial.h linux-3.2.1/arch/arm/plat-ckb/include/plat/omap-serial.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/omap-serial.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/omap-serial.h	2014-05-15 13:25:14.167225238 +0900
- ***************
- *** 0 ****
- --- 1,141 ----
- + /*
- +  * Driver for OMAP-UART controller.
- +  * Based on drivers/serial/8250.c
- +  *
- +  * Copyright (C) 2010 Texas Instruments.
- +  *
- +  * Authors:
- +  *	Govindraj R	<govindraj.raja@ti.com>
- +  *	Thara Gopinath	<thara@ti.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; either version 2 of the License, or
- +  * (at your option) any later version.
- +  */
- + 
- + #ifndef __OMAP_SERIAL_H__
- + #define __OMAP_SERIAL_H__
- + 
- + #include <linux/serial_core.h>
- + #include <linux/platform_device.h>
- + #include <linux/pm_qos.h>
- + 
- + #include <plat/mux.h>
- + 
- + #define DRIVER_NAME	"omap_uart"
- + 
- + /*
- +  * Use tty device name as ttyO, [O -> OMAP]
- +  * in bootargs we specify as console=ttyO0 if uart1
- +  * is used as console uart.
- +  */
- + #define OMAP_SERIAL_NAME	"ttyO"
- + 
- + #define OMAP_MODE13X_SPEED	230400
- + 
- + #define OMAP_UART_SCR_TX_EMPTY	0x08
- + 
- + /* WER = 0x7F
- +  * Enable module level wakeup in WER reg
- +  */
- + #define OMAP_UART_WER_MOD_WKUP	0X7F
- + 
- + /* Enable XON/XOFF flow control on output */
- + #define OMAP_UART_SW_TX		0x04
- + 
- + /* Enable XON/XOFF flow control on input */
- + #define OMAP_UART_SW_RX		0x04
- + 
- + #define OMAP_UART_SYSC_RESET	0X07
- + #define OMAP_UART_TCR_TRIG	0X0F
- + #define OMAP_UART_SW_CLR	0XF0
- + #define OMAP_UART_FIFO_CLR	0X06
- + 
- + #define OMAP_UART_DMA_CH_FREE	-1
- + 
- + #define OMAP_MAX_HSUART_PORTS	6
- + 
- + #define MSR_SAVE_FLAGS		UART_MSR_ANY_DELTA
- + 
- + #define UART_ERRATA_i202_MDR1_ACCESS	BIT(0)
- + #define UART_ERRATA_i291_DMA_FORCEIDLE	BIT(1)
- + 
- + struct omap_uart_port_info {
- + 	bool			dma_enabled;	/* To specify DMA Mode */
- + 	unsigned int		uartclk;	/* UART clock rate */
- + 	upf_t			flags;		/* UPF_* flags */
- + 	u32			errata;
- + 	unsigned int		dma_rx_buf_size;
- + 	unsigned int		dma_rx_timeout;
- + 	unsigned int		autosuspend_timeout;
- + 	unsigned int		dma_rx_poll_rate;
- + 
- + 	int (*get_context_loss_count)(struct device *);
- + 	void (*set_forceidle)(struct platform_device *);
- + 	void (*set_noidle)(struct platform_device *);
- + 	void (*enable_wakeup)(struct platform_device *, bool);
- + };
- + 
- + struct uart_omap_dma {
- + 	u8			uart_dma_tx;
- + 	u8			uart_dma_rx;
- + 	int			rx_dma_channel;
- + 	int			tx_dma_channel;
- + 	dma_addr_t		rx_buf_dma_phys;
- + 	dma_addr_t		tx_buf_dma_phys;
- + 	unsigned int		uart_base;
- + 	/*
- + 	 * Buffer for rx dma.It is not required for tx because the buffer
- + 	 * comes from port structure.
- + 	 */
- + 	unsigned char		*rx_buf;
- + 	unsigned int		prev_rx_dma_pos;
- + 	int			tx_buf_size;
- + 	int			tx_dma_used;
- + 	int			rx_dma_used;
- + 	spinlock_t		tx_lock;
- + 	spinlock_t		rx_lock;
- + 	/* timer to poll activity on rx dma */
- + 	struct timer_list	rx_timer;
- + 	unsigned int		rx_buf_size;
- + 	unsigned int		rx_poll_rate;
- + 	unsigned int		rx_timeout;
- + };
- + 
- + struct uart_omap_port {
- + 	struct uart_port	port;
- + 	struct uart_omap_dma	uart_dma;
- + 	struct platform_device	*pdev;
- + 
- + 	unsigned char		ier;
- + 	unsigned char		lcr;
- + 	unsigned char		mcr;
- + 	unsigned char		fcr;
- + 	unsigned char		efr;
- + 	unsigned char		dll;
- + 	unsigned char		dlh;
- + 	unsigned char		mdr1;
- + 	unsigned char		scr;
- + 
- + 	int			use_dma;
- + 	/*
- + 	 * Some bits in registers are cleared on a read, so they must
- + 	 * be saved whenever the register is read but the bits will not
- + 	 * be immediately processed.
- + 	 */
- + 	unsigned int		lsr_break_flag;
- + 	unsigned char		msr_saved_flags;
- + 	char			name[20];
- + 	unsigned long		port_activity;
- + 	u32			context_loss_cnt;
- + 	u32			errata;
- + 	u8			wakeups_enabled;
- + 
- + 	struct pm_qos_request	pm_qos_request;
- + 	u32			latency;
- + 	u32			calc_latency;
- + 	struct work_struct	qos_work;
- + };
- + 
- + #endif /* __OMAP_SERIAL_H__ */
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/param.h linux-3.2.1/arch/arm/plat-ckb/include/plat/param.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/param.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/param.h	2014-05-15 13:25:14.167225238 +0900
- ***************
- *** 0 ****
- --- 1,8 ----
- + /*
- +  *  arch/arm/plat-omap/include/mach/param.h
- +  *
- +  */
- + 
- + #ifdef CONFIG_OMAP_32K_TIMER_HZ
- + #define HZ	CONFIG_OMAP_32K_TIMER_HZ
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/prcm.h linux-3.2.1/arch/arm/plat-ckb/include/plat/prcm.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/prcm.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/prcm.h	2014-05-15 13:25:14.167225238 +0900
- ***************
- *** 0 ****
- --- 1,37 ----
- + /*
- +  * arch/arm/plat-omap/include/mach/prcm.h
- +  *
- +  * Access definations for use in OMAP24XX clock and power management
- +  *
- +  * Copyright (C) 2005 Texas Instruments, Inc.
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; either version 2 of the License, or
- +  * (at your option) any later version.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- +  *
- +  * XXX This file is deprecated.  The PRCM is an OMAP2+-only subsystem,
- +  * so this file doesn't belong in plat-omap/include/plat.  Please
- +  * do not add anything new to this file.
- +  */
- + 
- + #ifndef __ASM_ARM_ARCH_OMAP_PRCM_H
- + #define __ASM_ARM_ARCH_OMAP_PRCM_H
- + 
- + u32 omap_prcm_get_reset_sources(void);
- + int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
- + 			 const char *name);
- + 
- + #endif
- + 
- + 
- + 
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/sdrc.h linux-3.2.1/arch/arm/plat-ckb/include/plat/sdrc.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/sdrc.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/sdrc.h	2014-05-15 13:25:14.167225238 +0900
- ***************
- *** 0 ****
- --- 1,131 ----
- + #ifndef ____ASM_ARCH_SDRC_H
- + #define ____ASM_ARCH_SDRC_H
- + 
- + /*
- +  * OMAP2/3 SDRC/SMS register definitions
- +  *
- +  * Copyright (C) 2007-2008 Texas Instruments, Inc.
- +  * Copyright (C) 2007-2008 Nokia Corporation
- +  *
- +  * Tony Lindgren
- +  * Paul Walmsley
- +  * Richard Woodruff
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #include <mach/io.h>
- + 
- + /* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
- + 
- + #define SDRC_SYSCONFIG		0x010
- + #define SDRC_CS_CFG		0x040
- + #define SDRC_SHARING		0x044
- + #define SDRC_ERR_TYPE		0x04C
- + #define SDRC_DLLA_CTRL		0x060
- + #define SDRC_DLLA_STATUS	0x064
- + #define SDRC_DLLB_CTRL		0x068
- + #define SDRC_DLLB_STATUS	0x06C
- + #define SDRC_POWER		0x070
- + #define SDRC_MCFG_0		0x080
- + #define SDRC_MR_0		0x084
- + #define SDRC_EMR2_0		0x08c
- + #define SDRC_ACTIM_CTRL_A_0	0x09c
- + #define SDRC_ACTIM_CTRL_B_0	0x0a0
- + #define SDRC_RFR_CTRL_0		0x0a4
- + #define SDRC_MANUAL_0		0x0a8
- + #define SDRC_MCFG_1		0x0B0
- + #define SDRC_MR_1		0x0B4
- + #define SDRC_EMR2_1		0x0BC
- + #define SDRC_ACTIM_CTRL_A_1	0x0C4
- + #define SDRC_ACTIM_CTRL_B_1	0x0C8
- + #define SDRC_RFR_CTRL_1		0x0D4
- + #define SDRC_MANUAL_1		0x0D8
- + 
- + #define SDRC_POWER_AUTOCOUNT_SHIFT	8
- + #define SDRC_POWER_AUTOCOUNT_MASK	(0xffff << SDRC_POWER_AUTOCOUNT_SHIFT)
- + #define SDRC_POWER_CLKCTRL_SHIFT	4
- + #define SDRC_POWER_CLKCTRL_MASK		(0x3 << SDRC_POWER_CLKCTRL_SHIFT)
- + #define SDRC_SELF_REFRESH_ON_AUTOCOUNT	(0x2 << SDRC_POWER_CLKCTRL_SHIFT)
- + 
- + /*
- +  * These values represent the number of memory clock cycles between
- +  * autorefresh initiation.  They assume 1 refresh per 64 ms (JEDEC), 8192
- +  * rows per device, and include a subtraction of a 50 cycle window in the
- +  * event that the autorefresh command is delayed due to other SDRC activity.
- +  * The '| 1' sets the ARE field to send one autorefresh when the autorefresh
- +  * counter reaches 0.
- +  *
- +  * These represent optimal values for common parts, it won't work for all.
- +  * As long as you scale down, most parameters are still work, they just
- +  * become sub-optimal. The RFR value goes in the opposite direction. If you
- +  * don't adjust it down as your clock period increases the refresh interval
- +  * will not be met. Setting all parameters for complete worst case may work,
- +  * but may cut memory performance by 2x. Due to errata the DLLs need to be
- +  * unlocked and their value needs run time calibration.	A dynamic call is
- +  * need for that as no single right value exists acorss production samples.
- +  *
- +  * Only the FULL speed values are given. Current code is such that rate
- +  * changes must be made at DPLLoutx2. The actual value adjustment for low
- +  * frequency operation will be handled by omap_set_performance()
- +  *
- +  * By having the boot loader boot up in the fastest L4 speed available likely
- +  * will result in something which you can switch between.
- +  */
- + #define SDRC_RFR_CTRL_165MHz	(0x00044c00 | 1)
- + #define SDRC_RFR_CTRL_133MHz	(0x0003de00 | 1)
- + #define SDRC_RFR_CTRL_100MHz	(0x0002da01 | 1)
- + #define SDRC_RFR_CTRL_110MHz	(0x0002da01 | 1) /* Need to calc */
- + #define SDRC_RFR_CTRL_BYPASS	(0x00005000 | 1) /* Need to calc */
- + 
- + 
- + /* SMS register offsets - read/write with sms_{read,write}_reg() */
- + 
- + #define SMS_SYSCONFIG			0x010
- + #define SMS_ROT_CONTROL(context)	(0x180 + 0x10 * context)
- + #define SMS_ROT_SIZE(context)		(0x184 + 0x10 * context)
- + #define SMS_ROT_PHYSICAL_BA(context)	(0x188 + 0x10 * context)
- + /* REVISIT: fill in other SMS registers here */
- + 
- + 
- + #ifndef __ASSEMBLER__
- + 
- + /**
- +  * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate
- +  * @rate: SDRC clock rate (in Hz)
- +  * @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate
- +  * @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate
- +  * @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate
- +  * @mr: Value to program to SDRC_MR for this rate
- +  *
- +  * This structure holds a pre-computed set of register values for the
- +  * SDRC for a given SDRC clock rate and SDRAM chip.  These are
- +  * intended to be pre-computed and specified in an array in the board-*.c
- +  * files.  The structure is keyed off the 'rate' field.
- +  */
- + struct omap_sdrc_params {
- + 	unsigned long rate;
- + 	u32 actim_ctrla;
- + 	u32 actim_ctrlb;
- + 	u32 rfr_ctrl;
- + 	u32 mr;
- + };
- + 
- + void omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
- + 			    struct omap_sdrc_params *sdrc_cs1);
- + 
- + int omap2_sdrc_get_params(unsigned long r,
- + 			  struct omap_sdrc_params **sdrc_cs0,
- + 			  struct omap_sdrc_params **sdrc_cs1);
- + void omap2_sms_save_context(void);
- + void omap2_sms_restore_context(void);
- + 
- + void omap2_sms_write_rot_control(u32 val, unsigned ctx);
- + void omap2_sms_write_rot_size(u32 val, unsigned ctx);
- + void omap2_sms_write_rot_physical_ba(u32 val, unsigned ctx);
- + 
- + #endif  /* __ASSEMBLER__ */
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/serial.h linux-3.2.1/arch/arm/plat-ckb/include/plat/serial.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/serial.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/serial.h	2014-05-15 13:25:14.167225238 +0900
- ***************
- *** 0 ****
- --- 1,129 ----
- + /*
- +  * arch/arm/plat-omap/include/mach/serial.h
- +  *
- +  * Copyright (C) 2009 Texas Instruments
- +  * Addded OMAP4 support- Santosh Shilimkar <santosh.shilimkar@ti.com>
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #ifndef __ASM_ARCH_SERIAL_H
- + #define __ASM_ARCH_SERIAL_H
- + 
- + #include <linux/init.h>
- + 
- + /*
- +  * Memory entry used for the DEBUG_LL UART configuration, relative to
- +  * start of RAM. See also uncompress.h and debug-macro.S.
- +  *
- +  * Note that using a memory location for storing the UART configuration
- +  * has at least two limitations:
- +  *
- +  * 1. Kernel uncompress code cannot overlap OMAP_UART_INFO as the
- +  *    uncompress code could then partially overwrite itself
- +  * 2. We assume printascii is called at least once before paging_init,
- +  *    and addruart has a chance to read OMAP_UART_INFO
- +  */
- + #define OMAP_UART_INFO_OFS	0x3ffc
- + 
- + /* OMAP1 serial ports */
- + #define OMAP1_UART1_BASE	0xfffb0000
- + #define OMAP1_UART2_BASE	0xfffb0800
- + #define OMAP1_UART3_BASE	0xfffb9800
- + 
- + /* OMAP2 serial ports */
- + #define OMAP2_UART1_BASE	0x4806a000
- + #define OMAP2_UART2_BASE	0x4806c000
- + #define OMAP2_UART3_BASE	0x4806e000
- + 
- + /* OMAP3 serial ports */
- + #define OMAP3_UART1_BASE	OMAP2_UART1_BASE
- + #define OMAP3_UART2_BASE	OMAP2_UART2_BASE
- + #define OMAP3_UART3_BASE	0x49020000
- + #define OMAP3_UART4_BASE	0x49042000	/* Only on 36xx */
- + #define OMAP3_UART4_AM35XX_BASE	0x4809E000	/* Only on AM35xx */
- + 
- + /* OMAP4 serial ports */
- + #define OMAP4_UART1_BASE	OMAP2_UART1_BASE
- + #define OMAP4_UART2_BASE	OMAP2_UART2_BASE
- + #define OMAP4_UART3_BASE	0x48020000
- + #define OMAP4_UART4_BASE	0x4806e000
- + 
- + /* TI81XX serial ports */
- + #define TI81XX_UART1_BASE	0x48020000
- + #define TI81XX_UART2_BASE	0x48022000
- + #define TI81XX_UART3_BASE	0x48024000
- + 
- + /* AM3505/3517 UART4 */
- + #define AM35XX_UART4_BASE	0x4809E000	/* Only on AM3505/3517 */
- + 
- + /* AM33XX serial port */
- + #define AM33XX_UART1_BASE	0x44E09000
- + #define AM33XX_UART2_BASE	0x48022000
- + #define AM33XX_UART3_BASE	0x48024000
- + #define AM33XX_UART4_BASE	0x481A6000
- + #define AM33XX_UART5_BASE	0x481A8000
- + #define AM33XX_UART6_BASE	0x481AA000
- + 
- + /* External port on Zoom2/3 */
- + #define ZOOM_UART_BASE		0x10000000
- + #define ZOOM_UART_VIRT		0xfa400000
- + 
- + #define OMAP_PORT_SHIFT		2
- + #define OMAP7XX_PORT_SHIFT	0
- + #define ZOOM_PORT_SHIFT		1
- + 
- + #define OMAP1510_BASE_BAUD	(12000000/16)
- + #define OMAP16XX_BASE_BAUD	(48000000/16)
- + #define OMAP24XX_BASE_BAUD	(48000000/16)
- + 
- + /*
- +  * DEBUG_LL port encoding stored into the UART1 scratchpad register by
- +  * decomp_setup in uncompress.h
- +  */
- + #define OMAP1UART1		11
- + #define OMAP1UART2		12
- + #define OMAP1UART3		13
- + #define OMAP2UART1		21
- + #define OMAP2UART2		22
- + #define OMAP2UART3		23
- + #define OMAP3UART1		OMAP2UART1
- + #define OMAP3UART2		OMAP2UART2
- + #define OMAP3UART3		33
- + #define OMAP3UART4		34		/* Only on 36xx */
- + #define OMAP4UART1		OMAP2UART1
- + #define OMAP4UART2		OMAP2UART2
- + #define OMAP4UART3		43
- + #define OMAP4UART4		44
- + #define TI81XXUART1		81
- + #define TI81XXUART2		82
- + #define TI81XXUART3		83
- + #define AM33XXUART1		84
- + #define AM33XXUART4		85
- + #define ZOOM_UART		95		/* Only on zoom2/3 */
- + 
- + /* This is only used by 8250.c for omap1510 */
- + #define is_omap_port(pt)	({int __ret = 0;			\
- + 			if ((pt)->port.mapbase == OMAP1_UART1_BASE ||	\
- + 			    (pt)->port.mapbase == OMAP1_UART2_BASE ||	\
- + 			    (pt)->port.mapbase == OMAP1_UART3_BASE)	\
- + 				__ret = 1;				\
- + 			__ret;						\
- + 			})
- + 
- + #ifndef __ASSEMBLER__
- + 
- + struct omap_board_data;
- + struct omap_uart_port_info;
- + 
- + extern void omap_serial_init(void);
- + extern int omap_uart_can_sleep(void);
- + extern void omap_serial_board_init(struct omap_uart_port_info *platform_data);
- + extern void omap_serial_init_port(struct omap_board_data *bdata,
- + 		struct omap_uart_port_info *platform_data);
- + #endif
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/smartreflex.h linux-3.2.1/arch/arm/plat-ckb/include/plat/smartreflex.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/smartreflex.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/smartreflex.h	2014-05-15 13:25:14.167225238 +0900
- ***************
- *** 0 ****
- --- 1,431 ----
- + /*
- +  * OMAP Smartreflex Defines and Routines
- +  *
- +  * Author: Thara Gopinath	<thara@ti.com>
- +  *
- +  * Copyright (C) 2010 Texas Instruments, Inc.
- +  * Thara Gopinath <thara@ti.com>
- +  *
- +  * Copyright (C) 2008 Nokia Corporation
- +  * Kalle Jokiniemi
- +  *
- +  * Copyright (C) 2007 Texas Instruments, Inc.
- +  * Lesly A M <x0080970@ti.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #ifndef __ASM_ARM_OMAP_SMARTREFLEX_H
- + #define __ASM_ARM_OMAP_SMARTREFLEX_H
- + 
- + #include <linux/platform_device.h>
- + #include <plat/voltage.h>
- + 
- + /*
- +  * Different Smartreflex IPs version. The v1 is the 65nm version used in
- +  * OMAP3430. The v2 is the update for the 45nm version of the IP
- +  * used in OMAP3630 and OMAP4430
- +  */
- + #define SR_TYPE_V1	1
- + #define SR_TYPE_V2	2
- + 
- + /* SMART REFLEX REG ADDRESS OFFSET */
- + #define SRCONFIG		0x00
- + #define SRSTATUS		0x04
- + #define SENVAL			0x08
- + #define SENMIN			0x0C
- + #define SENMAX			0x10
- + #define SENAVG			0x14
- + #define AVGWEIGHT		0x18
- + #define NVALUERECIPROCAL	0x1c
- + #define SENERROR_V1		0x20
- + #define ERRCONFIG_V1		0x24
- + #define IRQ_EOI			0x20
- + #define IRQSTATUS_RAW		0x24
- + #define IRQSTATUS		0x28
- + #define IRQENABLE_SET		0x2C
- + #define IRQENABLE_CLR		0x30
- + #define SENERROR_V2		0x34
- + #define ERRCONFIG_V2		0x38
- + 
- + /* Bit/Shift Positions */
- + 
- + /* SRCONFIG */
- + #define SRCONFIG_ACCUMDATA_SHIFT	22
- + #define SRCONFIG_SRCLKLENGTH_SHIFT	12
- + #define SRCONFIG_SENNENABLE_V1_SHIFT	5
- + #define SRCONFIG_SENPENABLE_V1_SHIFT	3
- + #define SRCONFIG_SENNENABLE_V2_SHIFT	1
- + #define SRCONFIG_SENPENABLE_V2_SHIFT	0
- + #define SRCONFIG_CLKCTRL_SHIFT		0
- + 
- + #define SRCONFIG_ACCUMDATA_MASK		(0x3ff << 22)
- + 
- + #define SRCONFIG_SRENABLE		BIT(11)
- + #define SRCONFIG_SENENABLE		BIT(10)
- + #define SRCONFIG_ERRGEN_EN		BIT(9)
- + #define SRCONFIG_MINMAXAVG_EN		BIT(8)
- + #define SRCONFIG_DELAYCTRL		BIT(2)
- + 
- + /* AVGWEIGHT */
- + #define AVGWEIGHT_SENPAVGWEIGHT_SHIFT	2
- + #define AVGWEIGHT_SENNAVGWEIGHT_SHIFT	0
- + 
- + /* NVALUERECIPROCAL */
- + #define NVALUERECIPROCAL_SENPGAIN_SHIFT	20
- + #define NVALUERECIPROCAL_SENNGAIN_SHIFT	16
- + #define NVALUERECIPROCAL_RNSENP_SHIFT	8
- + #define NVALUERECIPROCAL_RNSENN_SHIFT	0
- + 
- + /* ERRCONFIG */
- + #define ERRCONFIG_ERRWEIGHT_SHIFT	16
- + #define ERRCONFIG_ERRMAXLIMIT_SHIFT	8
- + #define ERRCONFIG_ERRMINLIMIT_SHIFT	0
- + 
- + #define SR_ERRWEIGHT_MASK		(0x07 << 16)
- + #define SR_ERRMAXLIMIT_MASK		(0xff << 8)
- + #define SR_ERRMINLIMIT_MASK		(0xff << 0)
- + 
- + #define ERRCONFIG_VPBOUNDINTEN_V1	BIT(31)
- + #define ERRCONFIG_VPBOUNDINTST_V1	BIT(30)
- + #define	ERRCONFIG_MCUACCUMINTEN		BIT(29)
- + #define ERRCONFIG_MCUACCUMINTST		BIT(28)
- + #define	ERRCONFIG_MCUVALIDINTEN		BIT(27)
- + #define ERRCONFIG_MCUVALIDINTST		BIT(26)
- + #define ERRCONFIG_MCUBOUNDINTEN		BIT(25)
- + #define	ERRCONFIG_MCUBOUNDINTST		BIT(24)
- + #define	ERRCONFIG_MCUDISACKINTEN	BIT(23)
- + #define ERRCONFIG_VPBOUNDINTST_V2	BIT(23)
- + #define ERRCONFIG_MCUDISACKINTST	BIT(22)
- + #define ERRCONFIG_VPBOUNDINTEN_V2	BIT(22)
- + 
- + #define ERRCONFIG_STATUS_V1_MASK	(ERRCONFIG_VPBOUNDINTST_V1 | \
- + 					ERRCONFIG_MCUACCUMINTST | \
- + 					ERRCONFIG_MCUVALIDINTST | \
- + 					ERRCONFIG_MCUBOUNDINTST | \
- + 					ERRCONFIG_MCUDISACKINTST)
- + /* IRQSTATUS */
- + #define IRQSTATUS_MCUACCUMINT		BIT(3)
- + #define IRQSTATUS_MCVALIDINT		BIT(2)
- + #define IRQSTATUS_MCBOUNDSINT		BIT(1)
- + #define IRQSTATUS_MCUDISABLEACKINT	BIT(0)
- + 
- + /* IRQENABLE_SET and IRQENABLE_CLEAR */
- + #define IRQENABLE_MCUACCUMINT		BIT(3)
- + #define IRQENABLE_MCUVALIDINT		BIT(2)
- + #define IRQENABLE_MCUBOUNDSINT		BIT(1)
- + #define IRQENABLE_MCUDISABLEACKINT	BIT(0)
- + 
- + /* Common Bit values */
- + 
- + #define SRCLKLENGTH_12MHZ_SYSCLK	0x3c
- + #define SRCLKLENGTH_13MHZ_SYSCLK	0x41
- + #define SRCLKLENGTH_19MHZ_SYSCLK	0x60
- + #define SRCLKLENGTH_26MHZ_SYSCLK	0x82
- + #define SRCLKLENGTH_38MHZ_SYSCLK	0xC0
- + 
- + /*
- +  * 3430 specific values. Maybe these should be passed from board file or
- +  * pmic structures.
- +  */
- + #define OMAP3430_SR_ACCUMDATA		0x1f4
- + 
- + #define OMAP3430_SR1_SENPAVGWEIGHT	0x03
- + #define OMAP3430_SR1_SENNAVGWEIGHT	0x03
- + 
- + #define OMAP3430_SR2_SENPAVGWEIGHT	0x01
- + #define OMAP3430_SR2_SENNAVGWEIGHT	0x01
- + 
- + #define OMAP3430_SR_ERRWEIGHT		0x04
- + #define OMAP3430_SR_ERRMAXLIMIT		0x02
- + 
- + /**
- +  * struct omap_sr_pmic_data - Strucutre to be populated by pmic code to pass
- +  *				pmic specific info to smartreflex driver
- +  *
- +  * @sr_pmic_init:	API to initialize smartreflex on the PMIC side.
- +  */
- + struct omap_sr_pmic_data {
- + 	void (*sr_pmic_init) (void);
- + };
- + 
- + #ifdef CONFIG_OMAP_SMARTREFLEX
- + /*
- +  * The smart reflex driver supports CLASS1 CLASS2 and CLASS3 SR.
- +  * The smartreflex class driver should pass the class type.
- +  * Should be used to populate the class_type field of the
- +  * omap_smartreflex_class_data structure.
- +  */
- + #define SR_CLASS1	0x1
- + #define SR_CLASS2	0x2
- + #define SR_CLASS3	0x3
- + 
- + /**
- +  * struct omap_sr_class_data - Smartreflex class driver info
- +  *
- +  * @enable:		API to enable a particular class smaartreflex.
- +  * @disable:		API to disable a particular class smartreflex.
- +  * @configure:		API to configure a particular class smartreflex.
- +  * @notify:		API to notify the class driver about an event in SR.
- +  *			Not needed for class3.
- +  * @notify_flags:	specify the events to be notified to the class driver
- +  * @class_type:		specify which smartreflex class.
- +  *			Can be used by the SR driver to take any class
- +  *			based decisions.
- +  */
- + struct omap_sr_class_data {
- + 	int (*enable)(struct voltagedomain *voltdm);
- + 	int (*disable)(struct voltagedomain *voltdm, int is_volt_reset);
- + 	int (*configure)(struct voltagedomain *voltdm);
- + 	int (*notify)(struct voltagedomain *voltdm, u32 status);
- + 	u8 notify_flags;
- + 	u8 class_type;
- + };
- + 
- + /**
- +  * struct omap_sr_nvalue_table	- Smartreflex n-target value info
- +  *
- +  * @efuse_offs:	The offset of the efuse where n-target values are stored.
- +  * @nvalue:	The n-target value.
- +  */
- + struct omap_sr_nvalue_table {
- + 	u32 efuse_offs;
- + 	u32 nvalue;
- + };
- + 
- + /**
- +  * struct omap_sr_data - Smartreflex platform data.
- +  *
- +  * @ip_type:		Smartreflex IP type.
- +  * @senp_mod:		SENPENABLE value for the sr
- +  * @senn_mod:		SENNENABLE value for sr
- +  * @nvalue_count:	Number of distinct nvalues in the nvalue table
- +  * @enable_on_init:	whether this sr module needs to enabled at
- +  *			boot up or not.
- +  * @nvalue_table:	table containing the  efuse offsets and nvalues
- +  *			corresponding to them.
- +  * @voltdm:		Pointer to the voltage domain associated with the SR
- +  */
- + struct omap_sr_data {
- + 	int				ip_type;
- + 	u32				senp_mod;
- + 	u32				senn_mod;
- + 	int				nvalue_count;
- + 	bool				enable_on_init;
- + 	struct omap_sr_nvalue_table	*nvalue_table;
- + 	struct voltagedomain		*voltdm;
- + };
- + 
- + /* Smartreflex module enable/disable interface */
- + void omap_sr_enable(struct voltagedomain *voltdm);
- + void omap_sr_disable(struct voltagedomain *voltdm);
- + void omap_sr_disable_reset_volt(struct voltagedomain *voltdm);
- + 
- + /* API to register the pmic specific data with the smartreflex driver. */
- + void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data);
- + 
- + /* Smartreflex driver hooks to be called from Smartreflex class driver */
- + int sr_enable(struct voltagedomain *voltdm, unsigned long volt);
- + void sr_disable(struct voltagedomain *voltdm);
- + int sr_configure_errgen(struct voltagedomain *voltdm);
- + int sr_configure_minmax(struct voltagedomain *voltdm);
- + 
- + /* API to register the smartreflex class driver with the smartreflex driver */
- + int sr_register_class(struct omap_sr_class_data *class_data);
- + #else
- + 
- + #ifdef CONFIG_AM33XX_SMARTREFLEX
- + 
- + #define SR_CORE                         (0)
- + #define SR_MPU                          (1)
- + #define SRCLKLENGTH_125MHZ_SYSCLK	(0x78 << 12)
- + #define GAIN_MAXLIMIT                   (16)
- + #define R_MAXLIMIT                      (256)
- + #define MAX_SENSORS                     2
- + /* GG: eventually this should be determined at runtime */
- + #define AM33XX_OPP_COUNT                4
- + 
- + /**
- +  * struct am33xx_sr_opp_data	- Smartreflex data per OPP
- +  * @efuse_offs:		The offset of the efuse where n-target values are
- +  *			stored.
- +  * @nvalue:             NTarget as stored in EFUSE.
- +  * @adj_nvalue:         Adjusted NTarget (adjusted by margin)
- +  * @e2v_gain:		Error to voltage gain for changing the percentage
- +  *			error into voltage delta
- +  * @err_weight:		Average sensor error weight
- +  * @err_minlimit:	Minimum error limit of the sensor
- +  * @err_maxlimit:	Maximum error limit of the sensor
- +  * @margin:             Voltage margin to apply
- +  * @nominal_volt:       Nominal voltage for this OPP
- +  * @frequency:          Defined frequency for this OPP (in KHz)
- +  */
- + struct am33xx_sr_opp_data {
- + 	u32	efuse_offs;
- +         u32     nvalue;
- +         u32     adj_nvalue;
- + 	s32	e2v_gain;
- + 	u32	err_weight;
- + 	u32	err_minlimit;
- + 	u32	err_maxlimit;
- +         s32     margin;
- +         u32     nominal_volt; /* nominal_volt and frequency may be removed
- +                                  once am33xx voltdm layer works */
- +         u32     frequency;
- +         u32     opp_id;
- + };
- + 
- + /**
- +  * struct am33xx_sr_sdata	- Smartreflex sensors data
- +  * @sr_opp_data:	Pointer to data structure containing per OPP data
- +  *                      for this SR module.
- +  * @no_of_opps:         Number of OPP's supported for this sensor -
- +  *                       determined dynamically when possible.
- +  * @default_opp:        Defines the opp to use on startup if OPP is fixed
- +  *                       or cannot be determined dynamically.
- +  * @senn_mod:		Enable bit for N sensor
- +  * @senp_mod:		Enable bit for P sensor
- +  */
- + struct am33xx_sr_sdata {
- + 	struct am33xx_sr_opp_data *sr_opp_data;
- +         u32     no_of_opps;
- +         u32     default_opp;
- + 	u32	senn_mod;
- + 	u32	senp_mod;
- + };
- + 
- + struct am33xx_sr_sensor {
- +         u32                             sr_id;
- + 	u32			        irq;
- + 	u32			        irq_status;
- + 	u32			        senn_en;
- + 	u32			        senp_en;
- + 	char			        *name;
- +         char                            *reg_name;
- + 	void __iomem		        *base;
- +         int				init_volt_mv;
- +         int                             curr_opp;
- +         u32                             no_of_opps;
- +         struct delayed_work             work_reenable;
- +         struct regulator		*reg;
- +         struct am33xx_sr_opp_data       opp_data[AM33XX_OPP_COUNT];
- + 	struct clk		        *fck;
- +         struct voltagedomain		*voltdm;
- +         struct omap_volt_data           *volt_data;
- + };
- + 
- + struct am33xx_sr {
- + 	u32				autocomp_active;
- + 	u32				sens_per_vd;
- +         u32                             no_of_sens;
- +         u32                             no_of_vds;
- + 	u32				ip_type;
- +         u32				irq_delay;
- +         u32                             disabled_by_user;
- + 	int				uvoltage_step_size;
- +         char                            *res_name[MAX_SENSORS];
- + #ifdef CONFIG_CPU_FREQ
- + 	struct notifier_block	        freq_transition;
- + #endif
- + 	/*struct work_struct		work;*/
- +         struct delayed_work             work;
- + 	struct sr_platform_data		*sr_data;
- + 	struct am33xx_sr_sensor		sen[MAX_SENSORS];
- + 	struct platform_device		*pdev;
- + };
- + 
- + /**
- +  * struct am33xx_sr_platform_data - Smartreflex platform data.
- +  * @sr_sdata:		SR per sensor details, contains the efuse off-sets,
- +  *			error to voltage gain factor, minimum error limits
- +  * @vd_name:		Name of the voltage domain.
- +  * @ip_type:		Smartreflex IP type, class1 or class2 or class3.
- +  * @irq_delay:          Amount of time required for changed voltage to settle.
- +  * @no_of_vds:		Number of voltage domains to which SR applicable
- +  * @no_of_sens:		Number of SR sensors used to monitor the device
- +  *			performance, temp etc...
- +  * @vstep_size_uv:	PMIC voltage step size in micro volts
- +  * @enable_on_init:	whether this sr module needs to enabled at
- +  *			boot up or not.
- +  */
- + struct am33xx_sr_platform_data {
- + 	struct am33xx_sr_sdata	*sr_sdata;
- + 	char			*vd_name[2];
- + 	u32			ip_type;
- +         u32                     irq_delay;
- + 	u32			no_of_vds;
- + 	u32			no_of_sens;
- + 	u32			vstep_size_uv;
- + 	bool			enable_on_init;
- + };
- + 
- + #endif /*CONFIG_AM33XX_SMARTREFLEX*/
- + 
- + #ifdef CONFIG_TI816X_SMARTREFLEX
- + 
- + #define SRHVT				0
- + #define SRSVT				1
- + 
- + /* SRClk = 100KHz */
- + #define SRCLKLENGTH_125MHZ_SYSCLK	(0x271 << 12)
- + 
- + /**
- +  * struct ti816x_sr_sdata	- Smartreflex sensors data
- +  * @efuse_offs:		The offset of the efuse where n-target values are
- +  *			stored.
- +  * @e2v_gain:		Error to voltage gain for changing the percentage
- +  *			error into voltage delta
- +  * @err_weight:		Average sensor error weight
- +  * @err_minlimit:	Minimum error limit of the sensor
- +  * @err_maxlimit:	Maximum error limit of the sensor
- +  * @senn_mod:		Enable bit for N sensor
- +  * @senp_mod:		Enable bit for P sensor
- +  */
- + struct ti816x_sr_sdata {
- + 	u32	efuse_offs;
- + 	u32	e2v_gain;
- + 	u32	err_weight;
- + 	u32	err_minlimit;
- + 	u32	err_maxlimit;
- + 	u32	senn_mod;
- + 	u32	senp_mod;
- + };
- + 
- + /**
- +  * struct ti816x_sr_platform_data - Smartreflex platform data.
- +  * @sr_sdata:		SR per sensor details, contains the efuse off-sets,
- +  *			error to voltage gain factor, minimum error limits
- +  * @vd_name:		Name of the voltage domain.
- +  * @ip_type:		Smartreflex IP type, class1 or class2 or class3.
- +  * @irq_delay:		Time delay between disable and re-enable the
- +  *			interrupts, in msec
- +  * @no_of_vds:		Number of voltage domains to which SR applicable
- +  * @no_of_sens:		Number of SR sensors used to monitor the device
- +  *			performance, temp etc...
- +  * @vstep_size_uv:	PMIC voltage step size in micro volts
- +  * @enable_on_init:	whether this sr module needs to enabled at
- +  *			boot up or not.
- +  */
- + struct ti816x_sr_platform_data {
- + 	struct ti816x_sr_sdata	*sr_sdata;
- + 	char			*vd_name;
- + 	u32			ip_type;
- + 	u32			irq_delay;
- + 	u32			no_of_vds;
- + 	u32			no_of_sens;
- + 	u32			vstep_size_uv;
- + 	bool			enable_on_init;
- + };
- + 
- + #endif /* CONFIG_TI816X_SMARTREFLEX */
- + 
- + static inline void omap_sr_enable(struct voltagedomain *voltdm) {}
- + static inline void omap_sr_disable(struct voltagedomain *voltdm) {}
- + static inline void omap_sr_disable_reset_volt(
- + 		struct voltagedomain *voltdm) {}
- + static inline void omap_sr_register_pmic(
- + 		struct omap_sr_pmic_data *pmic_data) {}
- + #endif
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/sram.h linux-3.2.1/arch/arm/plat-ckb/include/plat/sram.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/sram.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/sram.h	2014-05-15 13:25:14.167225238 +0900
- ***************
- *** 0 ****
- --- 1,107 ----
- + /*
- +  * arch/arm/plat-omap/include/mach/sram.h
- +  *
- +  * Interface for functions that need to be run in internal SRAM
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #ifndef __ARCH_ARM_OMAP_SRAM_H
- + #define __ARCH_ARM_OMAP_SRAM_H
- + 
- + #ifndef __ASSEMBLY__
- + #include <linux/slab.h>
- + #include <linux/genalloc.h>
- + #include <asm/fncpy.h>
- + 
- + extern struct gen_pool *omap_gen_pool;
- + 
- + /*
- +  * Note that fncpy requires the SRAM address to be aligned to an 8-byte
- +  * boundary, so the min_alloc_order for the pool is set appropriately.
- +  */
- + #define omap_sram_push(funcp, size) ({					\
- + 	typeof(&(funcp)) _res;						\
- + 	size_t _sz = size;						\
- + 	void *_sram = (void *) gen_pool_alloc(omap_gen_pool, _sz);	\
- + 	_res = (_sram ? fncpy(_sram, &(funcp), _sz) : NULL);		\
- + 	if (!_res)							\
- + 		pr_err("Not enough space in SRAM to copy suspend code\n");			\
- + 	_res;								\
- + })
- + 
- + extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
- + 
- + extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
- + 				u32 base_cs, u32 force_unlock);
- + extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
- + 				      u32 mem_type);
- + extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
- + 
- + extern u32 omap3_configure_core_dpll(
- + 			u32 m2, u32 unlock_dll, u32 f, u32 inc,
- + 			u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
- + 			u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
- + 			u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
- + 			u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
- + extern void omap3_sram_restore_context(void);
- + 
- + /* Do not use these */
- + extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
- + extern unsigned long omap1_sram_reprogram_clock_sz;
- + 
- + extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
- + extern unsigned long omap24xx_sram_reprogram_clock_sz;
- + 
- + extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
- + 						u32 base_cs, u32 force_unlock);
- + extern unsigned long omap242x_sram_ddr_init_sz;
- + 
- + extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
- + 						int bypass);
- + extern unsigned long omap242x_sram_set_prcm_sz;
- + 
- + extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
- + 						u32 mem_type);
- + extern unsigned long omap242x_sram_reprogram_sdrc_sz;
- + 
- + 
- + extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
- + 						u32 base_cs, u32 force_unlock);
- + extern unsigned long omap243x_sram_ddr_init_sz;
- + 
- + extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
- + 						int bypass);
- + extern unsigned long omap243x_sram_set_prcm_sz;
- + 
- + extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
- + 						u32 mem_type);
- + extern unsigned long omap243x_sram_reprogram_sdrc_sz;
- + 
- + extern u32 omap3_sram_configure_core_dpll(
- + 			u32 m2, u32 unlock_dll, u32 f, u32 inc,
- + 			u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
- + 			u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
- + 			u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
- + 			u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
- + extern unsigned long omap3_sram_configure_core_dpll_sz;
- + 
- + #ifdef CONFIG_PM
- + extern void am33xx_push_sram_idle(void);
- + extern void omap_push_sram_idle(void);
- + #else
- + static inline void am33xx_push_sram_idle(void) {}
- + static inline void omap_push_sram_idle(void) {}
- + #endif /* CONFIG_PM */
- + 
- + #endif /* __ASSEMBLY__ */
- + 
- + /*
- +  * OMAP2+: define the SRAM PA addresses.
- +  * Used by the SRAM management code and the idle sleep code.
- +  */
- + #define OMAP3_SUSPEND_SRAM_PA   0x402F1000
- + #define AM33XX_SRAM_PA			0x40300000
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/system.h linux-3.2.1/arch/arm/plat-ckb/include/plat/system.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/system.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/system.h	2014-05-15 13:25:14.171740516 +0900
- ***************
- *** 0 ****
- --- 1,17 ----
- + /*
- +  * Copied from arch/arm/mach-sa1100/include/mach/system.h
- +  * Copyright (c) 1999 Nicolas Pitre <nico@fluxnic.net>
- +  */
- + #ifndef __ASM_ARCH_SYSTEM_H
- + #define __ASM_ARCH_SYSTEM_H
- + 
- + #include <asm/proc-fns.h>
- + 
- + static inline void arch_idle(void)
- + {
- + 	cpu_do_idle();
- + }
- + 
- + extern void (*arch_reset)(char, const char *);
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/timex.h linux-3.2.1/arch/arm/plat-ckb/include/plat/timex.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/timex.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/timex.h	2014-05-15 13:25:14.171740516 +0900
- ***************
- *** 0 ****
- --- 1,41 ----
- + /*
- +  * arch/arm/plat-omap/include/mach/timex.h
- +  *
- +  * Copyright (C) 2000 RidgeRun, Inc.
- +  * Author:  Greg Lonnon <glonnon@ridgerun.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify it
- +  * under the terms of the GNU General Public License as published by the
- +  * Free Software Foundation; either version 2 of the License, or (at your
- +  * option) any later version.
- +  *
- +  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- +  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- +  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- +  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- +  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- +  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- +  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- +  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- +  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- +  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- +  *
- +  * You should have received a copy of the  GNU General Public License along
- +  * with this program; if not, write  to the Free Software Foundation, Inc.,
- +  * 675 Mass Ave, Cambridge, MA 02139, USA.
- +  */
- + 
- + #if !defined(__ASM_ARCH_OMAP_TIMEX_H)
- + #define __ASM_ARCH_OMAP_TIMEX_H
- + 
- + /*
- +  * OMAP 32KHz timer updates time one jiffie at a time from a secondary timer,
- +  * and that's why the CLOCK_TICK_RATE is not 32768.
- +  */
- + #ifdef CONFIG_OMAP_32K_TIMER
- + #define CLOCK_TICK_RATE		(CONFIG_OMAP_32K_TIMER_HZ)
- + #else
- + #define CLOCK_TICK_RATE		(HZ * 100000UL)
- + #endif
- + 
- + #endif /* __ASM_ARCH_OMAP_TIMEX_H */
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/uncompress.h linux-3.2.1/arch/arm/plat-ckb/include/plat/uncompress.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/uncompress.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/uncompress.h	2014-05-15 13:25:14.171740516 +0900
- ***************
- *** 0 ****
- --- 1,55 ----
- + /*
- +  * arch/arm/plat-omap/include/mach/uncompress.h
- +  *
- +  * Serial port stubs for kernel decompress status messages
- +  *
- +  * Initially based on:
- +  * linux-2.4.15-rmk1-dsplinux1.6/arch/arm/plat-omap/include/mach1510/uncompress.h
- +  * Copyright (C) 2000 RidgeRun, Inc.
- +  * Author: Greg Lonnon <glonnon@ridgerun.com>
- +  *
- +  * Rewritten by:
- +  * Author: <source@mvista.com>
- +  * 2004 (c) MontaVista Software, Inc.
- +  *
- +  * This file is licensed under the terms of the GNU General Public License
- +  * version 2. This program is licensed "as is" without any warranty of any
- +  * kind, whether express or implied.
- +  */
- + 
- + #include <linux/types.h>
- + #include <linux/serial_reg.h>
- + 
- + #include <asm/memory.h>
- + #include <asm/mach-types.h>
- + 
- + #include <plat/serial.h>
- + 
- + #define MDR1_MODE_MASK			0x07
- + 
- + volatile u8 *uart_base;
- + int uart_shift;
- + 
- + static void putc(int c)
- + {
- + 	if (!uart_base)
- + 		return;
- + 
- + 	/* Check for UART 16x mode */
- + 	if ((uart_base[UART_OMAP_MDR1 << uart_shift] & MDR1_MODE_MASK) != 0)
- + 		return;
- + 
- + 	while (!(uart_base[UART_LSR << uart_shift] & UART_LSR_THRE))
- + 		barrier();
- + 	uart_base[UART_TX << uart_shift] = c;
- + }
- + 
- + static inline void flush(void)
- + {
- + }
- + 
- + /*
- +  * nothing to do
- +  */
- + #define arch_decomp_setup()
- + #define arch_decomp_wdog()
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/usb.h linux-3.2.1/arch/arm/plat-ckb/include/plat/usb.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/usb.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/usb.h	2014-05-15 13:25:14.171740516 +0900
- ***************
- *** 0 ****
- --- 1,383 ----
- + // include/asm-arm/mach-omap/usb.h
- + 
- + #ifndef	__ASM_ARCH_OMAP_USB_H
- + #define	__ASM_ARCH_OMAP_USB_H
- + 
- + #include <linux/usb/musb.h>
- + #include <plat/board.h>
- + 
- + #define OMAP3_HS_USB_PORTS	3
- + 
- + enum usbhs_omap_port_mode {
- + 	OMAP_USBHS_PORT_MODE_UNUSED,
- + 	OMAP_EHCI_PORT_MODE_PHY,
- + 	OMAP_EHCI_PORT_MODE_TLL,
- + 	OMAP_EHCI_PORT_MODE_HSIC,
- + 	OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0,
- + 	OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM,
- + 	OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0,
- + 	OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM,
- + 	OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0,
- + 	OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM,
- + 	OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0,
- + 	OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM,
- + 	OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0,
- + 	OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM
- + };
- + 
- + struct usbhs_omap_board_data {
- + 	enum usbhs_omap_port_mode	port_mode[OMAP3_HS_USB_PORTS];
- + 
- + 	/* have to be valid if phy_reset is true and portx is in phy mode */
- + 	int	reset_gpio_port[OMAP3_HS_USB_PORTS];
- + 
- + 	/* Set this to true for ES2.x silicon */
- + 	unsigned			es2_compatibility:1;
- + 
- + 	unsigned			phy_reset:1;
- + 
- + 	/*
- + 	 * Regulators for USB PHYs.
- + 	 * Each PHY can have a separate regulator.
- + 	 */
- + 	struct regulator		*regulator[OMAP3_HS_USB_PORTS];
- + };
- + 
- + struct ehci_hcd_omap_platform_data {
- + 	enum usbhs_omap_port_mode	port_mode[OMAP3_HS_USB_PORTS];
- + 	int				reset_gpio_port[OMAP3_HS_USB_PORTS];
- + 	struct regulator		*regulator[OMAP3_HS_USB_PORTS];
- + 	unsigned			phy_reset:1;
- + };
- + 
- + struct ohci_hcd_omap_platform_data {
- + 	enum usbhs_omap_port_mode	port_mode[OMAP3_HS_USB_PORTS];
- + 	unsigned			es2_compatibility:1;
- + };
- + 
- + struct usbhs_omap_platform_data {
- + 	enum usbhs_omap_port_mode		port_mode[OMAP3_HS_USB_PORTS];
- + 
- + 	struct ehci_hcd_omap_platform_data	*ehci_data;
- + 	struct ohci_hcd_omap_platform_data	*ohci_data;
- + };
- + /*-------------------------------------------------------------------------*/
- + 
- + #define OMAP1_OTG_BASE			0xfffb0400
- + #define OMAP1_UDC_BASE			0xfffb4000
- + #define OMAP1_OHCI_BASE			0xfffba000
- + 
- + #define OMAP2_OHCI_BASE			0x4805e000
- + #define OMAP2_UDC_BASE			0x4805e200
- + #define OMAP2_OTG_BASE			0x4805e300
- + 
- + #ifdef CONFIG_ARCH_OMAP1
- + 
- + #define OTG_BASE			OMAP1_OTG_BASE
- + #define UDC_BASE			OMAP1_UDC_BASE
- + #define OMAP_OHCI_BASE			OMAP1_OHCI_BASE
- + 
- + #else
- + 
- + #define OTG_BASE			OMAP2_OTG_BASE
- + #define UDC_BASE			OMAP2_UDC_BASE
- + #define OMAP_OHCI_BASE			OMAP2_OHCI_BASE
- + 
- + struct omap_musb_board_data {
- + 	u8	interface_type;
- + 	u8	mode;
- + 	u16	power;
- + 	unsigned extvbus:1;
- + 	u8	instances;
- + 	u8	grndis_for_host_rx;
- + 	u8	babble_ctrl;
- + 	void	(*set_phy_power)(u8 id, u8 on, bool wkup);
- + 	void	(*clear_irq)(void);
- + 	void	(*set_mode)(u8 mode);
- + 	void	(*reset)(void);
- + };
- + 
- + enum musb_interface    {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
- + 
- + extern void usb_musb_init(struct omap_musb_board_data *board_data);
- + 
- + extern void usbhs_init(const struct usbhs_omap_board_data *pdata);
- + 
- + extern int omap4430_phy_power(struct device *dev, int ID, int on);
- + extern int omap4430_phy_set_clk(struct device *dev, int on);
- + extern int omap4430_phy_exit(struct device *dev);
- + extern int omap4430_phy_suspend(struct device *dev, int suspend);
- + #endif
- + 
- + extern void am35x_musb_reset(void);
- + extern void am35x_musb_phy_power(u8 id, u8 on);
- + extern void am35x_musb_clear_irq(void);
- + extern void am35x_set_mode(u8 musb_mode);
- + extern void ti81xx_musb_phy_power(u8 id, u8 on, bool wkup);
- + 
- + /*
- +  * FIXME correct answer depends on hmc_mode,
- +  * as does (on omap1) any nonzero value for config->otg port number
- +  */
- + #ifdef	CONFIG_USB_GADGET_OMAP
- + #define	is_usb0_device(config)	1
- + #else
- + #define	is_usb0_device(config)	0
- + #endif
- + 
- + void omap_otg_init(struct omap_usb_config *config);
- + 
- + #if defined(CONFIG_USB) || defined(CONFIG_USB_MODULE)
- + void omap1_usb_init(struct omap_usb_config *pdata);
- + #else
- + static inline void omap1_usb_init(struct omap_usb_config *pdata)
- + {
- + }
- + #endif
- + 
- + #if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP_OTG_MODULE)
- + void omap2_usbfs_init(struct omap_usb_config *pdata);
- + #else
- + static inline void omap2_usbfs_init(struct omap_usb_config *pdata)
- + {
- + }
- + #endif
- + 
- + /*-------------------------------------------------------------------------*/
- + 
- + /*
- +  * OTG and transceiver registers, for OMAPs starting with ARM926
- +  */
- + #define OTG_REV				(OTG_BASE + 0x00)
- + #define OTG_SYSCON_1			(OTG_BASE + 0x04)
- + #	define	 USB2_TRX_MODE(w)	(((w)>>24)&0x07)
- + #	define	 USB1_TRX_MODE(w)	(((w)>>20)&0x07)
- + #	define	 USB0_TRX_MODE(w)	(((w)>>16)&0x07)
- + #	define	 OTG_IDLE_EN		(1 << 15)
- + #	define	 HST_IDLE_EN		(1 << 14)
- + #	define	 DEV_IDLE_EN		(1 << 13)
- + #	define	 OTG_RESET_DONE		(1 << 2)
- + #	define	 OTG_SOFT_RESET		(1 << 1)
- + #define OTG_SYSCON_2			(OTG_BASE + 0x08)
- + #	define	 OTG_EN			(1 << 31)
- + #	define	 USBX_SYNCHRO		(1 << 30)
- + #	define	 OTG_MST16		(1 << 29)
- + #	define	 SRP_GPDATA		(1 << 28)
- + #	define	 SRP_GPDVBUS		(1 << 27)
- + #	define	 SRP_GPUVBUS(w)		(((w)>>24)&0x07)
- + #	define	 A_WAIT_VRISE(w)	(((w)>>20)&0x07)
- + #	define	 B_ASE_BRST(w)		(((w)>>16)&0x07)
- + #	define	 SRP_DPW		(1 << 14)
- + #	define	 SRP_DATA		(1 << 13)
- + #	define	 SRP_VBUS		(1 << 12)
- + #	define	 OTG_PADEN		(1 << 10)
- + #	define	 HMC_PADEN		(1 << 9)
- + #	define	 UHOST_EN		(1 << 8)
- + #	define	 HMC_TLLSPEED		(1 << 7)
- + #	define	 HMC_TLLATTACH		(1 << 6)
- + #	define	 OTG_HMC(w)		(((w)>>0)&0x3f)
- + #define OTG_CTRL			(OTG_BASE + 0x0c)
- + #	define	 OTG_USB2_EN		(1 << 29)
- + #	define	 OTG_USB2_DP		(1 << 28)
- + #	define	 OTG_USB2_DM		(1 << 27)
- + #	define	 OTG_USB1_EN		(1 << 26)
- + #	define	 OTG_USB1_DP		(1 << 25)
- + #	define	 OTG_USB1_DM		(1 << 24)
- + #	define	 OTG_USB0_EN		(1 << 23)
- + #	define	 OTG_USB0_DP		(1 << 22)
- + #	define	 OTG_USB0_DM		(1 << 21)
- + #	define	 OTG_ASESSVLD		(1 << 20)
- + #	define	 OTG_BSESSEND		(1 << 19)
- + #	define	 OTG_BSESSVLD		(1 << 18)
- + #	define	 OTG_VBUSVLD		(1 << 17)
- + #	define	 OTG_ID			(1 << 16)
- + #	define	 OTG_DRIVER_SEL		(1 << 15)
- + #	define	 OTG_A_SETB_HNPEN	(1 << 12)
- + #	define	 OTG_A_BUSREQ		(1 << 11)
- + #	define	 OTG_B_HNPEN		(1 << 9)
- + #	define	 OTG_B_BUSREQ		(1 << 8)
- + #	define	 OTG_BUSDROP		(1 << 7)
- + #	define	 OTG_PULLDOWN		(1 << 5)
- + #	define	 OTG_PULLUP		(1 << 4)
- + #	define	 OTG_DRV_VBUS		(1 << 3)
- + #	define	 OTG_PD_VBUS		(1 << 2)
- + #	define	 OTG_PU_VBUS		(1 << 1)
- + #	define	 OTG_PU_ID		(1 << 0)
- + #define OTG_IRQ_EN			(OTG_BASE + 0x10)	/* 16-bit */
- + #	define	 DRIVER_SWITCH		(1 << 15)
- + #	define	 A_VBUS_ERR		(1 << 13)
- + #	define	 A_REQ_TMROUT		(1 << 12)
- + #	define	 A_SRP_DETECT		(1 << 11)
- + #	define	 B_HNP_FAIL		(1 << 10)
- + #	define	 B_SRP_TMROUT		(1 << 9)
- + #	define	 B_SRP_DONE		(1 << 8)
- + #	define	 B_SRP_STARTED		(1 << 7)
- + #	define	 OPRT_CHG		(1 << 0)
- + #define OTG_IRQ_SRC			(OTG_BASE + 0x14)	/* 16-bit */
- + 	// same bits as in IRQ_EN
- + #define OTG_OUTCTRL			(OTG_BASE + 0x18)	/* 16-bit */
- + #	define	 OTGVPD			(1 << 14)
- + #	define	 OTGVPU			(1 << 13)
- + #	define	 OTGPUID		(1 << 12)
- + #	define	 USB2VDR		(1 << 10)
- + #	define	 USB2PDEN		(1 << 9)
- + #	define	 USB2PUEN		(1 << 8)
- + #	define	 USB1VDR		(1 << 6)
- + #	define	 USB1PDEN		(1 << 5)
- + #	define	 USB1PUEN		(1 << 4)
- + #	define	 USB0VDR		(1 << 2)
- + #	define	 USB0PDEN		(1 << 1)
- + #	define	 USB0PUEN		(1 << 0)
- + #define OTG_TEST			(OTG_BASE + 0x20)	/* 16-bit */
- + #define OTG_VENDOR_CODE			(OTG_BASE + 0xfc)	/* 16-bit */
- + 
- + /*-------------------------------------------------------------------------*/
- + 
- + /* OMAP1 */
- + #define	USB_TRANSCEIVER_CTRL		(0xfffe1000 + 0x0064)
- + #	define	CONF_USB2_UNI_R		(1 << 8)
- + #	define	CONF_USB1_UNI_R		(1 << 7)
- + #	define	CONF_USB_PORT0_R(x)	(((x)>>4)&0x7)
- + #	define	CONF_USB0_ISOLATE_R	(1 << 3)
- + #	define	CONF_USB_PWRDN_DM_R	(1 << 2)
- + #	define	CONF_USB_PWRDN_DP_R	(1 << 1)
- + 
- + /* OMAP2 */
- + #	define	USB_UNIDIR			0x0
- + #	define	USB_UNIDIR_TLL			0x1
- + #	define	USB_BIDIR			0x2
- + #	define	USB_BIDIR_TLL			0x3
- + #	define	USBTXWRMODEI(port, x)	((x) << (22 - (port * 2)))
- + #	define	USBT2TLL5PI		(1 << 17)
- + #	define	USB0PUENACTLOI		(1 << 16)
- + #	define	USBSTANDBYCTRL		(1 << 15)
- + /* AM35x */
- + /* USB 2.0 PHY Control */
- + #define CONF2_PHY_GPIOMODE	(1 << 23)
- + #define CONF2_OTGMODE		(3 << 14)
- + #define CONF2_NO_OVERRIDE	(0 << 14)
- + #define CONF2_FORCE_HOST	(1 << 14)
- + #define CONF2_FORCE_DEVICE	(2 << 14)
- + #define CONF2_FORCE_HOST_VBUS_LOW (3 << 14)
- + #define CONF2_SESENDEN		(1 << 13)
- + #define CONF2_VBDTCTEN		(1 << 12)
- + #define CONF2_REFFREQ_24MHZ	(2 << 8)
- + #define CONF2_REFFREQ_26MHZ	(7 << 8)
- + #define CONF2_REFFREQ_13MHZ	(6 << 8)
- + #define CONF2_REFFREQ		(0xf << 8)
- + #define CONF2_PHYCLKGD		(1 << 7)
- + #define CONF2_VBUSSENSE		(1 << 6)
- + #define CONF2_PHY_PLLON		(1 << 5)
- + #define CONF2_RESET		(1 << 4)
- + #define CONF2_PHYPWRDN		(1 << 3)
- + #define CONF2_OTGPWRDN		(1 << 2)
- + #define CONF2_DATPOL		(1 << 1)
- + 
- + /* TI81XX specific definitions */
- + #define USBCTRL0	0x620
- + #define USBSTAT0	0x624
- + #define USBCTRL1	0x628
- + #define USBSTAT1	0x62c
- + #define USBWKUPCTRL	0x648
- + 
- + /* TI816X PHY controls bits */
- + #define TI816X_USBPHY0_NORMAL_MODE	(1 << 0)
- + #define TI816X_USBPHY1_NORMAL_MODE	(1 << 1)
- + #define TI816X_USBPHY_REFCLK_OSC	(1 << 8)
- + 
- + /* TI814X PHY controls bits */
- + #define USBPHY_CM_PWRDN		(1 << 0)
- + #define USBPHY_OTG_PWRDN	(1 << 1)
- + #define USBPHY_CHGDET_DIS	(1 << 2)
- + #define USBPHY_CHGDET_RSTRT	(1 << 3)
- + #define USBPHY_SRCONDM		(1 << 4)
- + #define USBPHY_SINKONDP		(1 << 5)
- + #define USBPHY_CHGISINK_EN	(1 << 6)
- + #define USBPHY_CHGVSRC_EN	(1 << 7)
- + #define USBPHY_DMPULLUP		(1 << 8)
- + #define USBPHY_DPPULLUP		(1 << 9)
- + #define USBPHY_CDET_EXTCTL	(1 << 10)
- + #define USBPHY_GPIO_MODE	(1 << 12)
- + #define USBPHY_DPGPIO_PD	(1 << 17)
- + #define USBPHY_DMGPIO_PD	(1 << 18)
- + #define USBPHY_OTGVDET_EN	(1 << 19)
- + #define USBPHY_OTGSESSEND_EN	(1 << 20)
- + #define USBPHY_DATA_POLARITY	(1 << 23)
- + 
- + /* TI81XX only PHY bits */
- + #define TI81XX_USBPHY_DPOPBUFCTL	(1 << 13)
- + #define TI81XX_USBPHY_DMOPBUFCTL	(1 << 14)
- + #define TI81XX_USBPHY_DPINPUT		(1 << 15)
- + #define TI81XX_USBPHY_DMINPUT		(1 << 16)
- + 
- + /* AM335X only PHY bits */
- + #define AM335X_USBPHY_GPIO_SIG_INV     (1 << 13)
- + #define AM335X_USBPHY_GPIO_SIG_CROSS   (1 << 14)
- + 
- + /*AM335X USB wakeup control bits */
- + #define AM33XX_USB_WKUP_CTRL_ENABLE    ((1 << 8) | (1 << 0))
- + #define AM33XX_USB0_WKUP_CTRL_ENABLE    (1 << 0)
- + #define AM33XX_USB1_WKUP_CTRL_ENABLE    (1 << 8)
- + #define AM33XX_USB_WKUP_CTRL_DISABLE   0x0
- + 
- + 
- + static inline u32 omap1_usb0_init(unsigned nwires, unsigned is_device)
- + {
- + 	return 0;
- + }
- + static inline u32 omap1_usb1_init(unsigned nwires)
- + {
- + 	return 0;
- + 
- + }
- + static inline u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup)
- + {
- + 	return 0;
- + }
- + 
- + /* DMA registers */
- + #define TI81XX_USB_AUTOREQ_REG	0xd0
- + #define TI81XX_USB_TEARDOWN_REG	0xd8
- + #define USB_AUTOREQ_REG		0x14
- + #define USB_TEARDOWN_REG	0x1c
- + #define MOP_SOP_INTR_ENABLE	0x64
- + /* 0x68-0x6c Reserved */
- + #define USB_TX_MODE_REG		0x70	/* Transparent, CDC, [Generic] RNDIS */
- + #define USB_RX_MODE_REG		0x74	/* Transparent, CDC, [Generic] RNDIS */
- + #define EP_COUNT_MODE_REG	0x78
- + #define USB_GENERIC_RNDIS_EP_SIZE_REG(n) (0x80 + (((n) - 1) << 2))
- + 
- + #define QUEUE_THRESHOLD_INTR_ENABLE_REG	0xc0
- + #define	QUEUE_63_THRESHOLD_REG	0xc4
- + #define QUEUE_63_THRESHOLD_INTR_CLEAR_REG 0xc8
- + #define	QUEUE_65_THRESHOLD_REG	0xd4
- + #define QUEUE_65_THRESHOLD_INTR_CLEAR_REG 0xd8
- + 
- + /* Mode register bits */
- + #define USB_MODE_SHIFT(n)	((((n) - 1) << 1))
- + #define USB_MODE_MASK(n)	(3 << USB_MODE_SHIFT(n))
- + #define USB_RX_MODE_SHIFT(n)	USB_MODE_SHIFT(n)
- + #define USB_TX_MODE_SHIFT(n)	USB_MODE_SHIFT(n)
- + #define USB_RX_MODE_MASK(n)	USB_MODE_MASK(n)
- + #define USB_TX_MODE_MASK(n)	USB_MODE_MASK(n)
- + #define USB_TRANSPARENT_MODE	0
- + #define USB_RNDIS_MODE		1
- + #define USB_CDC_MODE		2
- + #define USB_GENERIC_RNDIS_MODE	3
- + 
- + /* AutoReq register bits */
- + #define USB_RX_AUTOREQ_SHIFT(n) (((n) - 1) << 1)
- + #define USB_RX_AUTOREQ_MASK(n)	(3 << USB_RX_AUTOREQ_SHIFT(n))
- + #define USB_NO_AUTOREQ		0
- + #define USB_AUTOREQ_ALL_BUT_EOP 1
- + #define USB_AUTOREQ_ALWAYS	3
- + 
- + /* Teardown register bits */
- + #define USB_TX_TDOWN_SHIFT(n)	(16 + (n))
- + #define USB_TX_TDOWN_MASK(n)	(1 << USB_TX_TDOWN_SHIFT(n))
- + #define USB_RX_TDOWN_SHIFT(n)	(n)
- + #define USB_RX_TDOWN_MASK(n)	(1 << USB_RX_TDOWN_SHIFT(n))
- + 
- + #define USB_CPPI41_NUM_CH	15
- + 
- + #endif	/* __ASM_ARCH_OMAP_USB_H */
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/voltage.h linux-3.2.1/arch/arm/plat-ckb/include/plat/voltage.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/voltage.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/include/plat/voltage.h	2014-05-15 13:25:14.171740516 +0900
- ***************
- *** 0 ****
- --- 1,20 ----
- + /*
- +  * OMAP Voltage Management Routines
- +  *
- +  * Copyright (C) 2011, Texas Instruments, Inc.
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + 
- + #ifndef __ARCH_ARM_OMAP_VOLTAGE_H
- + #define __ARCH_ARM_OMAP_VOLTAGE_H
- + 
- + struct voltagedomain;
- + 
- + struct voltagedomain *voltdm_lookup(const char *name);
- + int voltdm_scale(struct voltagedomain *voltdm, unsigned long target_volt);
- + unsigned long voltdm_get_voltage(struct voltagedomain *voltdm);
- + 
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/mailbox.c linux-3.2.1/arch/arm/plat-ckb/mailbox.c
- *** linux-3.2.1_o/arch/arm/plat-ckb/mailbox.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/mailbox.c	2014-05-15 13:25:14.175611435 +0900
- ***************
- *** 0 ****
- --- 1,460 ----
- + /*
- +  * OMAP mailbox driver
- +  *
- +  * Copyright (C) 2006-2009 Nokia Corporation. All rights reserved.
- +  *
- +  * Contact: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License
- +  * version 2 as published by the Free Software Foundation.
- +  *
- +  * This program is distributed in the hope that it will be useful, but
- +  * WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- +  * General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- +  * 02110-1301 USA
- +  *
- +  */
- + 
- + #include <linux/interrupt.h>
- + #include <linux/spinlock.h>
- + #include <linux/mutex.h>
- + #include <linux/delay.h>
- + #include <linux/slab.h>
- + #include <linux/kfifo.h>
- + #include <linux/err.h>
- + #include <linux/notifier.h>
- + #include <linux/module.h>
- + 
- + #include <plat/mailbox.h>
- + 
- + static struct omap_mbox **mboxes;
- + 
- + static int mbox_configured;
- + static DEFINE_MUTEX(mbox_configured_lock);
- + #define CONFIG_OMAP_MBOX_KFIFO_SIZE  256
- + static unsigned int mbox_kfifo_size = CONFIG_OMAP_MBOX_KFIFO_SIZE;
- + module_param(mbox_kfifo_size, uint, S_IRUGO);
- + MODULE_PARM_DESC(mbox_kfifo_size, "Size of omap's mailbox kfifo (bytes)");
- + 
- + /* Mailbox FIFO handle functions */
- + static inline mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox)
- + {
- + 	return mbox->ops->fifo_read(mbox);
- + }
- + static inline void mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
- + {
- + 	mbox->ops->fifo_write(mbox, msg);
- + }
- + static inline int mbox_fifo_empty(struct omap_mbox *mbox)
- + {
- + 	return mbox->ops->fifo_empty(mbox);
- + }
- + static inline int mbox_fifo_full(struct omap_mbox *mbox)
- + {
- + 	return mbox->ops->fifo_full(mbox);
- + }
- + static inline int mbox_fifo_needs_flush(struct omap_mbox *mbox)
- + {
- + 	return mbox->ops->fifo_needs_flush(mbox);
- + }
- + static inline mbox_msg_t mbox_fifo_readback(struct omap_mbox *mbox)
- + {
- + 	return mbox->ops->fifo_readback(mbox);
- + }
- + 
- + /* Mailbox IRQ handle functions */
- + static inline void ack_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
- + {
- + 	if (mbox->ops->ack_irq)
- + 		mbox->ops->ack_irq(mbox, irq);
- + }
- + static inline int is_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
- + {
- + 	return mbox->ops->is_irq(mbox, irq);
- + }
- + 
- + /*
- +  * message sender
- +  */
- + static int __mbox_poll_for_space(struct omap_mbox *mbox)
- + {
- + 	int ret = 0, i = 1000;
- + 
- + 	while (mbox_fifo_full(mbox)) {
- + 		if (mbox->ops->type == OMAP_MBOX_TYPE2)
- + 			return -1;
- + 		if (--i == 0)
- + 			return -1;
- + 		udelay(1);
- + 	}
- + 	return ret;
- + }
- + 
- + int omap_mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg)
- + {
- + 	struct omap_mbox_queue *mq = mbox->txq;
- + 	int ret = 0, len;
- + 
- + 	spin_lock_bh(&mq->lock);
- + 
- + 	if (kfifo_avail(&mq->fifo) < sizeof(msg)) {
- + 		ret = -ENOMEM;
- + 		goto out;
- + 	}
- + 
- + 	if (kfifo_is_empty(&mq->fifo) && !__mbox_poll_for_space(mbox)) {
- + 		mbox_fifo_write(mbox, msg);
- + 		goto out;
- + 	}
- + 
- + 	len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
- + 	WARN_ON(len != sizeof(msg));
- + 
- + 	tasklet_schedule(&mbox->txq->tasklet);
- + 
- + out:
- + 	spin_unlock_bh(&mq->lock);
- + 	return ret;
- + }
- + EXPORT_SYMBOL(omap_mbox_msg_send);
- + 
- + /*
- +  * Flush the Rx FIFO by reading back the messages
- +  * Since the normal expectation is that the Rx will do the
- +  * reading, add a debug message to indicate if we really flush
- +  * returns the no. of messages read back
- +  */
- + int omap_mbox_msg_rx_flush(struct omap_mbox *mbox)
- + {
- + 	int ret = 0;
- + 	mbox_msg_t msg;
- + 
- + 	while (!mbox_fifo_needs_flush(mbox)) {
- + 		ret++;
- + 		msg = mbox_fifo_readback(mbox);
- + 	}
- + 	if (ret)
- + 		pr_debug("Flushed %s Rx FIFO via %d readbacks\n", mbox->name, ret);
- + 
- + 	return ret;
- + }
- + EXPORT_SYMBOL(omap_mbox_msg_rx_flush);
- + 
- + static void mbox_tx_tasklet(unsigned long tx_data)
- + {
- + 	struct omap_mbox *mbox = (struct omap_mbox *)tx_data;
- + 	struct omap_mbox_queue *mq = mbox->txq;
- + 	mbox_msg_t msg;
- + 	int ret;
- + 
- + 	while (kfifo_len(&mq->fifo)) {
- + 		if (__mbox_poll_for_space(mbox)) {
- + 			omap_mbox_enable_irq(mbox, IRQ_TX);
- + 			break;
- + 		}
- + 
- + 		ret = kfifo_out(&mq->fifo, (unsigned char *)&msg,
- + 								sizeof(msg));
- + 		WARN_ON(ret != sizeof(msg));
- + 
- + 		mbox_fifo_write(mbox, msg);
- + 	}
- + }
- + 
- + /*
- +  * Message receiver(workqueue)
- +  */
- + static void mbox_rx_work(struct work_struct *work)
- + {
- + 	struct omap_mbox_queue *mq =
- + 			container_of(work, struct omap_mbox_queue, work);
- + 	mbox_msg_t msg;
- + 	int len;
- + 
- + 	while (kfifo_len(&mq->fifo) >= sizeof(msg)) {
- + 		len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
- + 		WARN_ON(len != sizeof(msg));
- + 
- + 		blocking_notifier_call_chain(&mq->mbox->notifier, len,
- + 								(void *)msg);
- + 		spin_lock_irq(&mq->lock);
- + 		if (mq->full) {
- + 			mq->full = false;
- + 			omap_mbox_enable_irq(mq->mbox, IRQ_RX);
- + 		}
- + 		spin_unlock_irq(&mq->lock);
- + 	}
- + }
- + 
- + /*
- +  * Mailbox interrupt handler
- +  */
- + static void __mbox_tx_interrupt(struct omap_mbox *mbox)
- + {
- + 	omap_mbox_disable_irq(mbox, IRQ_TX);
- + 	ack_mbox_irq(mbox, IRQ_TX);
- + 	tasklet_schedule(&mbox->txq->tasklet);
- + }
- + 
- + static void __mbox_rx_interrupt(struct omap_mbox *mbox)
- + {
- + 	struct omap_mbox_queue *mq = mbox->rxq;
- + 	mbox_msg_t msg;
- + 	int len;
- + 
- + 	while (!mbox_fifo_empty(mbox)) {
- + 		if (unlikely(kfifo_avail(&mq->fifo) < sizeof(msg))) {
- + 			omap_mbox_disable_irq(mbox, IRQ_RX);
- + 			mq->full = true;
- + 			goto nomem;
- + 		}
- + 
- + 		msg = mbox_fifo_read(mbox);
- + 
- + 		len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
- + 		WARN_ON(len != sizeof(msg));
- + 
- + 		if (mbox->ops->type == OMAP_MBOX_TYPE1)
- + 			break;
- + 	}
- + 
- + 	/* no more messages in the fifo. clear IRQ source. */
- + 	ack_mbox_irq(mbox, IRQ_RX);
- + nomem:
- + 	schedule_work(&mbox->rxq->work);
- + }
- + 
- + static irqreturn_t mbox_interrupt(int irq, void *p)
- + {
- + 	struct omap_mbox *mbox = p;
- + 
- + 	if (is_mbox_irq(mbox, IRQ_TX))
- + 		__mbox_tx_interrupt(mbox);
- + 
- + 	if (is_mbox_irq(mbox, IRQ_RX))
- + 		__mbox_rx_interrupt(mbox);
- + 
- + 	return IRQ_HANDLED;
- + }
- + 
- + static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox,
- + 					void (*work) (struct work_struct *),
- + 					void (*tasklet)(unsigned long))
- + {
- + 	struct omap_mbox_queue *mq;
- + 
- + 	mq = kzalloc(sizeof(struct omap_mbox_queue), GFP_KERNEL);
- + 	if (!mq)
- + 		return NULL;
- + 
- + 	spin_lock_init(&mq->lock);
- + 
- + 	if (kfifo_alloc(&mq->fifo, mbox_kfifo_size, GFP_KERNEL))
- + 		goto error;
- + 
- + 	if (work)
- + 		INIT_WORK(&mq->work, work);
- + 
- + 	if (tasklet)
- + 		tasklet_init(&mq->tasklet, tasklet, (unsigned long)mbox);
- + 	return mq;
- + error:
- + 	kfree(mq);
- + 	return NULL;
- + }
- + 
- + static void mbox_queue_free(struct omap_mbox_queue *q)
- + {
- + 	kfifo_free(&q->fifo);
- + 	kfree(q);
- + }
- + 
- + static int omap_mbox_startup(struct omap_mbox *mbox)
- + {
- + 	int ret = 0;
- + 	struct omap_mbox_queue *mq;
- + 
- + 	mutex_lock(&mbox_configured_lock);
- + 	if (!mbox_configured++) {
- + 		if (likely(mbox->ops->startup)) {
- + 			ret = mbox->ops->startup(mbox);
- + 			if (unlikely(ret))
- + 				goto fail_startup;
- + 		} else
- + 			goto fail_startup;
- + 	}
- + 
- + 	if (!mbox->use_count++) {
- + 		ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED,
- + 							mbox->name, mbox);
- + 		if (unlikely(ret)) {
- + 			pr_err("failed to register mailbox interrupt:%d\n",
- + 									ret);
- + 			goto fail_request_irq;
- + 		}
- + 		mq = mbox_queue_alloc(mbox, NULL, mbox_tx_tasklet);
- + 		if (!mq) {
- + 			ret = -ENOMEM;
- + 			goto fail_alloc_txq;
- + 		}
- + 		mbox->txq = mq;
- + 
- + 		mq = mbox_queue_alloc(mbox, mbox_rx_work, NULL);
- + 		if (!mq) {
- + 			ret = -ENOMEM;
- + 			goto fail_alloc_rxq;
- + 		}
- + 		mbox->rxq = mq;
- + 		mq->mbox = mbox;
- + 	}
- + 	mutex_unlock(&mbox_configured_lock);
- + 	return 0;
- + 
- + fail_alloc_rxq:
- + 	mbox_queue_free(mbox->txq);
- + fail_alloc_txq:
- + 	free_irq(mbox->irq, mbox);
- + fail_request_irq:
- + 	if (mbox->ops->shutdown)
- + 		mbox->ops->shutdown(mbox);
- + 	mbox->use_count--;
- + fail_startup:
- + 	mbox_configured--;
- + 	mutex_unlock(&mbox_configured_lock);
- + 	return ret;
- + }
- + 
- + static void omap_mbox_fini(struct omap_mbox *mbox)
- + {
- + 	mutex_lock(&mbox_configured_lock);
- + 
- + 	if (!--mbox->use_count) {
- + 		free_irq(mbox->irq, mbox);
- + 		tasklet_kill(&mbox->txq->tasklet);
- + 	flush_work_sync(&mbox->rxq->work);
- + 		mbox_queue_free(mbox->txq);
- + 		mbox_queue_free(mbox->rxq);
- + 	}
- + 
- + 	if (likely(mbox->ops->shutdown)) {
- + 		if (!--mbox_configured)
- + 			mbox->ops->shutdown(mbox);
- + 	}
- + 
- + 	mutex_unlock(&mbox_configured_lock);
- + }
- + 
- + struct omap_mbox *omap_mbox_get(const char *name, struct notifier_block *nb)
- + {
- + 	struct omap_mbox *_mbox, *mbox = NULL;
- + 	int i, ret;
- + 
- + 	if (!mboxes)
- + 		return ERR_PTR(-EINVAL);
- + 
- + 	for (i = 0; (_mbox = mboxes[i]); i++) {
- + 		if (!strcmp(_mbox->name, name)) {
- + 			mbox = _mbox;
- + 			break;
- + 		}
- + 	}
- + 
- + 	if (!mbox)
- + 		return ERR_PTR(-ENOENT);
- + 
- + 	ret = omap_mbox_startup(mbox);
- + 	if (ret)
- + 		return ERR_PTR(-ENODEV);
- + 
- + 	if (nb)
- + 		blocking_notifier_chain_register(&mbox->notifier, nb);
- + 
- + 	return mbox;
- + }
- + EXPORT_SYMBOL(omap_mbox_get);
- + 
- + void omap_mbox_put(struct omap_mbox *mbox, struct notifier_block *nb)
- + {
- + 	blocking_notifier_chain_unregister(&mbox->notifier, nb);
- + 	omap_mbox_fini(mbox);
- + }
- + EXPORT_SYMBOL(omap_mbox_put);
- + 
- + static struct class omap_mbox_class = { .name = "mbox", };
- + 
- + int omap_mbox_register(struct device *parent, struct omap_mbox **list)
- + {
- + 	int ret;
- + 	int i;
- + 
- + 	mboxes = list;
- + 	if (!mboxes)
- + 		return -EINVAL;
- + 
- + 	for (i = 0; mboxes[i]; i++) {
- + 		struct omap_mbox *mbox = mboxes[i];
- + 		mbox->dev = device_create(&omap_mbox_class,
- + 				parent, 0, mbox, "%s", mbox->name);
- + 		if (IS_ERR(mbox->dev)) {
- + 			ret = PTR_ERR(mbox->dev);
- + 			goto err_out;
- + 		}
- + 
- + 		BLOCKING_INIT_NOTIFIER_HEAD(&mbox->notifier);
- + 	}
- + 	return 0;
- + 
- + err_out:
- + 	while (i--)
- + 		device_unregister(mboxes[i]->dev);
- + 	return ret;
- + }
- + EXPORT_SYMBOL(omap_mbox_register);
- + 
- + int omap_mbox_unregister(void)
- + {
- + 	int i;
- + 
- + 	if (!mboxes)
- + 		return -EINVAL;
- + 
- + 	for (i = 0; mboxes[i]; i++)
- + 		device_unregister(mboxes[i]->dev);
- + 	mboxes = NULL;
- + 	return 0;
- + }
- + EXPORT_SYMBOL(omap_mbox_unregister);
- + 
- + static int __init omap_mbox_init(void)
- + {
- + 	int err;
- + 
- + 	err = class_register(&omap_mbox_class);
- + 	if (err)
- + 		return err;
- + 
- + 	/* kfifo size sanity check: alignment and minimal size */
- + 	mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(mbox_msg_t));
- + 	mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size,
- + 							sizeof(mbox_msg_t));
- + 
- + 	return 0;
- + }
- + subsys_initcall(omap_mbox_init);
- + 
- + static void __exit omap_mbox_exit(void)
- + {
- + 	class_unregister(&omap_mbox_class);
- + }
- + module_exit(omap_mbox_exit);
- + 
- + MODULE_LICENSE("GPL v2");
- + MODULE_DESCRIPTION("omap mailbox: interrupt driven messaging");
- + MODULE_AUTHOR("Toshihiro Kobayashi");
- + MODULE_AUTHOR("Hiroshi DOYU");
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/Makefile linux-3.2.1/arch/arm/plat-ckb/Makefile
- *** linux-3.2.1_o/arch/arm/plat-ckb/Makefile	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/Makefile	2014-05-15 13:25:14.175611435 +0900
- ***************
- *** 0 ****
- --- 1,24 ----
- + #
- + # Makefile for the linux kernel.
- + #
- + 
- + # Common support
- + obj-y := common.o sram.o clock.o devices.o mux.o \
- + 	 usb.o counter_32k.o mailbox.o
- + 
- + 
- + obj-m :=
- + obj-n :=
- + obj-  :=
- + 
- + obj-$(CONFIG_OMAP3_EDMA) += sdma2edma.o
- + 
- + # omap_device support (OMAP2+ only at the moment)
- + obj-$(CONFIG_MACH_CKB_3352) += omap_device.o
- + 
- + obj-$(CONFIG_MACH_CKB_3352) += dmtimer.o
- + 
- + i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o
- + obj-y += $(i2c-omap-m) $(i2c-omap-y)
- + 
- + obj-$(CONFIG_MACH_CKB_3352) += omap-pm-noop.o
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/mux.c linux-3.2.1/arch/arm/plat-ckb/mux.c
- *** linux-3.2.1_o/arch/arm/plat-ckb/mux.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/mux.c	2014-05-15 13:25:14.175611435 +0900
- ***************
- *** 0 ****
- --- 1,51 ----
- + /*
- +  * linux/arch/arm/plat-omap/mux.c
- +  *
- +  * Utility to set the Omap MUX and PULL_DWN registers from a table in mux.h
- +  *
- +  * Copyright (C) 2003 - 2008 Nokia Corporation
- +  *
- +  * Written by Tony Lindgren
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; either version 2 of the License, or
- +  * (at your option) any later version.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- +  *
- +  */
- + #include <linux/module.h>
- + #include <linux/init.h>
- + #include <linux/kernel.h>
- + #include <linux/io.h>
- + #include <asm/system.h>
- + #include <linux/spinlock.h>
- + #include <plat/mux.h>
- + 
- + #ifdef CONFIG_OMAP_MUX
- + 
- + static struct omap_mux_cfg *mux_cfg;
- + 
- + int __init omap_mux_register(struct omap_mux_cfg *arch_mux_cfg)
- + {
- + 	if (!arch_mux_cfg || !arch_mux_cfg->pins || arch_mux_cfg->size == 0
- + 			|| !arch_mux_cfg->cfg_reg) {
- + 		printk(KERN_ERR "Invalid pin table\n");
- + 		return -EINVAL;
- + 	}
- + 
- + 	mux_cfg = arch_mux_cfg;
- + 
- + 	return 0;
- + }
- + #else
- + #define omap_mux_init() do {} while(0)
- + #endif	/* CONFIG_OMAP_MUX */
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/omap_device.c linux-3.2.1/arch/arm/plat-ckb/omap_device.c
- *** linux-3.2.1_o/arch/arm/plat-ckb/omap_device.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/omap_device.c	2014-05-15 13:25:14.175611435 +0900
- ***************
- *** 0 ****
- --- 1,1162 ----
- + /*
- +  * omap_device implementation
- +  *
- +  * Copyright (C) 2009-2010 Nokia Corporation
- +  * Paul Walmsley, Kevin Hilman
- +  *
- +  * Developed in collaboration with (alphabetical order): Benoit
- +  * Cousson, Thara Gopinath, Tony Lindgren, Rajendra Nayak, Vikram
- +  * Pandita, Sakari Poussa, Anand Sawant, Santosh Shilimkar, Richard
- +  * Woodruff
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  *
- +  * This code provides a consistent interface for OMAP device drivers
- +  * to control power management and interconnect properties of their
- +  * devices.
- +  *
- +  * In the medium- to long-term, this code should either be
- +  * a) implemented via arch-specific pointers in platform_data
- +  * or
- +  * b) implemented as a proper omap_bus/omap_device in Linux, no more
- +  *    platform_data func pointers
- +  *
- +  *
- +  * Guidelines for usage by driver authors:
- +  *
- +  * 1. These functions are intended to be used by device drivers via
- +  * function pointers in struct platform_data.  As an example,
- +  * omap_device_enable() should be passed to the driver as
- +  *
- +  * struct foo_driver_platform_data {
- +  * ...
- +  *      int (*device_enable)(struct platform_device *pdev);
- +  * ...
- +  * }
- +  *
- +  * Note that the generic "device_enable" name is used, rather than
- +  * "omap_device_enable".  This is so other architectures can pass in their
- +  * own enable/disable functions here.
- +  *
- +  * This should be populated during device setup:
- +  *
- +  * ...
- +  * pdata->device_enable = omap_device_enable;
- +  * ...
- +  *
- +  * 2. Drivers should first check to ensure the function pointer is not null
- +  * before calling it, as in:
- +  *
- +  * if (pdata->device_enable)
- +  *     pdata->device_enable(pdev);
- +  *
- +  * This allows other architectures that don't use similar device_enable()/
- +  * device_shutdown() functions to execute normally.
- +  *
- +  * ...
- +  *
- +  * Suggested usage by device drivers:
- +  *
- +  * During device initialization:
- +  * device_enable()
- +  *
- +  * During device idle:
- +  * (save remaining device context if necessary)
- +  * device_idle();
- +  *
- +  * During device resume:
- +  * device_enable();
- +  * (restore context if necessary)
- +  *
- +  * During device shutdown:
- +  * device_shutdown()
- +  * (device must be reinitialized at this point to use it again)
- +  *
- +  */
- + #undef DEBUG
- + 
- + #include <linux/kernel.h>
- + #include <linux/export.h>
- + #include <linux/platform_device.h>
- + #include <linux/slab.h>
- + #include <linux/err.h>
- + #include <linux/io.h>
- + #include <linux/clk.h>
- + #include <linux/clkdev.h>
- + #include <linux/pm_runtime.h>
- + #include <linux/of.h>
- + #include <linux/notifier.h>
- + 
- + #include <plat/omap_device.h>
- + #include <plat/omap_hwmod.h>
- + #include <plat/clock.h>
- + 
- + /* These parameters are passed to _omap_device_{de,}activate() */
- + #define USE_WAKEUP_LAT			0
- + #define IGNORE_WAKEUP_LAT		1
- + 
- + static int omap_early_device_register(struct platform_device *pdev);
- + 
- + static struct omap_device_pm_latency omap_default_latency[] = {
- + 	{
- + 		.deactivate_func = omap_device_idle_hwmods,
- + 		.activate_func   = omap_device_enable_hwmods,
- + 		.flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
- + 	}
- + };
- + 
- + /* Private functions */
- + 
- + /**
- +  * _omap_device_activate - increase device readiness
- +  * @od: struct omap_device *
- +  * @ignore_lat: increase to latency target (0) or full readiness (1)?
- +  *
- +  * Increase readiness of omap_device @od (thus decreasing device
- +  * wakeup latency, but consuming more power).  If @ignore_lat is
- +  * IGNORE_WAKEUP_LAT, make the omap_device fully active.  Otherwise,
- +  * if @ignore_lat is USE_WAKEUP_LAT, and the device's maximum wakeup
- +  * latency is greater than the requested maximum wakeup latency, step
- +  * backwards in the omap_device_pm_latency table to ensure the
- +  * device's maximum wakeup latency is less than or equal to the
- +  * requested maximum wakeup latency.  Returns 0.
- +  */
- + static int _omap_device_activate(struct omap_device *od, u8 ignore_lat)
- + {
- + 	struct timespec a, b, c;
- + 
- + 	dev_dbg(&od->pdev->dev, "omap_device: activating\n");
- + 
- + 	while (od->pm_lat_level > 0) {
- + 		struct omap_device_pm_latency *odpl;
- + 		unsigned long long act_lat = 0;
- + 
- + 		od->pm_lat_level--;
- + 
- + 		odpl = od->pm_lats + od->pm_lat_level;
- + 
- + 		if (!ignore_lat &&
- + 		    (od->dev_wakeup_lat <= od->_dev_wakeup_lat_limit))
- + 			break;
- + 
- + 		read_persistent_clock(&a);
- + 
- + 		/* XXX check return code */
- + 		odpl->activate_func(od);
- + 
- + 		read_persistent_clock(&b);
- + 
- + 		c = timespec_sub(b, a);
- + 		act_lat = timespec_to_ns(&c);
- + 
- + 		dev_dbg(&od->pdev->dev,
- + 			"omap_device: pm_lat %d: activate: elapsed time "
- + 			"%llu nsec\n", od->pm_lat_level, act_lat);
- + 
- + 		if (act_lat > odpl->activate_lat) {
- + 			odpl->activate_lat_worst = act_lat;
- + 			if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) {
- + 				odpl->activate_lat = act_lat;
- + 				dev_dbg(&od->pdev->dev,
- + 					"new worst case activate latency "
- + 					"%d: %llu\n",
- + 					od->pm_lat_level, act_lat);
- + 			} else
- + 				dev_warn(&od->pdev->dev,
- + 					 "activate latency %d "
- + 					 "higher than exptected. (%llu > %d)\n",
- + 					 od->pm_lat_level, act_lat,
- + 					 odpl->activate_lat);
- + 		}
- + 
- + 		od->dev_wakeup_lat -= odpl->activate_lat;
- + 	}
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * _omap_device_deactivate - decrease device readiness
- +  * @od: struct omap_device *
- +  * @ignore_lat: decrease to latency target (0) or full inactivity (1)?
- +  *
- +  * Decrease readiness of omap_device @od (thus increasing device
- +  * wakeup latency, but conserving power).  If @ignore_lat is
- +  * IGNORE_WAKEUP_LAT, make the omap_device fully inactive.  Otherwise,
- +  * if @ignore_lat is USE_WAKEUP_LAT, and the device's maximum wakeup
- +  * latency is less than the requested maximum wakeup latency, step
- +  * forwards in the omap_device_pm_latency table to ensure the device's
- +  * maximum wakeup latency is less than or equal to the requested
- +  * maximum wakeup latency.  Returns 0.
- +  */
- + static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
- + {
- + 	struct timespec a, b, c;
- + 
- + 	dev_dbg(&od->pdev->dev, "omap_device: deactivating\n");
- + 
- + 	while (od->pm_lat_level < od->pm_lats_cnt) {
- + 		struct omap_device_pm_latency *odpl;
- + 		unsigned long long deact_lat = 0;
- + 
- + 		odpl = od->pm_lats + od->pm_lat_level;
- + 
- + 		if (!ignore_lat &&
- + 		    ((od->dev_wakeup_lat + odpl->activate_lat) >
- + 		     od->_dev_wakeup_lat_limit))
- + 			break;
- + 
- + 		read_persistent_clock(&a);
- + 
- + 		/* XXX check return code */
- + 		odpl->deactivate_func(od);
- + 
- + 		read_persistent_clock(&b);
- + 
- + 		c = timespec_sub(b, a);
- + 		deact_lat = timespec_to_ns(&c);
- + 
- + 		dev_dbg(&od->pdev->dev,
- + 			"omap_device: pm_lat %d: deactivate: elapsed time "
- + 			"%llu nsec\n", od->pm_lat_level, deact_lat);
- + 
- + 		if (deact_lat > odpl->deactivate_lat) {
- + 			odpl->deactivate_lat_worst = deact_lat;
- + 			if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) {
- + 				odpl->deactivate_lat = deact_lat;
- + 				dev_dbg(&od->pdev->dev,
- + 					"new worst case deactivate latency "
- + 					"%d: %llu\n",
- + 					od->pm_lat_level, deact_lat);
- + 			} else
- + 				dev_warn(&od->pdev->dev,
- + 					 "deactivate latency %d "
- + 					 "higher than exptected. (%llu > %d)\n",
- + 					 od->pm_lat_level, deact_lat,
- + 					 odpl->deactivate_lat);
- + 		}
- + 
- + 		od->dev_wakeup_lat += odpl->activate_lat;
- + 
- + 		od->pm_lat_level++;
- + 	}
- + 
- + 	return 0;
- + }
- + 
- + static void _add_clkdev(struct omap_device *od, const char *clk_alias,
- + 		       const char *clk_name)
- + {
- + 	struct clk *r;
- + 	struct clk_lookup *l;
- + 
- + 	if (!clk_alias || !clk_name)
- + 		return;
- + 
- + 	dev_dbg(&od->pdev->dev, "Creating %s -> %s\n", clk_alias, clk_name);
- + 
- + 	r = clk_get_sys(dev_name(&od->pdev->dev), clk_alias);
- + 	if (!IS_ERR(r)) {
- + 		dev_warn(&od->pdev->dev,
- + 			 "alias %s already exists\n", clk_alias);
- + 		clk_put(r);
- + 		return;
- + 	}
- + 
- + 	r = omap_clk_get_by_name(clk_name);
- + 	if (IS_ERR(r)) {
- + 		dev_err(&od->pdev->dev,
- + 			"omap_clk_get_by_name for %s failed\n", clk_name);
- + 		return;
- + 	}
- + 
- + 	l = clkdev_alloc(r, clk_alias, dev_name(&od->pdev->dev));
- + 	if (!l) {
- + 		dev_err(&od->pdev->dev,
- + 			"clkdev_alloc for %s failed\n", clk_alias);
- + 		return;
- + 	}
- + 
- + 	clkdev_add(l);
- + }
- + 
- + /**
- +  * _add_hwmod_clocks_clkdev - Add clkdev entry for hwmod optional clocks
- +  * and main clock
- +  * @od: struct omap_device *od
- +  * @oh: struct omap_hwmod *oh
- +  *
- +  * For the main clock and every optional clock present per hwmod per
- +  * omap_device, this function adds an entry in the clkdev table of the
- +  * form <dev-id=dev_name, con-id=role> if it does not exist already.
- +  *
- +  * The function is called from inside omap_device_build_ss(), after
- +  * omap_device_register.
- +  *
- +  * This allows drivers to get a pointer to its optional clocks based on its role
- +  * by calling clk_get(<dev*>, <role>).
- +  * In the case of the main clock, a "fck" alias is used.
- +  *
- +  * No return value.
- +  */
- + static void _add_hwmod_clocks_clkdev(struct omap_device *od,
- + 				     struct omap_hwmod *oh)
- + {
- + 	int i;
- + 
- + 	_add_clkdev(od, "fck", oh->main_clk);
- + 
- + 	for (i = 0; i < oh->opt_clks_cnt; i++)
- + 		_add_clkdev(od, oh->opt_clks[i].role, oh->opt_clks[i].clk);
- + }
- + 
- + 
- + static struct dev_pm_domain omap_device_pm_domain;
- + 
- + /**
- +  * omap_device_build_from_dt - build an omap_device with multiple hwmods
- +  * @pdev_name: name of the platform_device driver to use
- +  * @pdev_id: this platform_device's connection ID
- +  * @oh: ptr to the single omap_hwmod that backs this omap_device
- +  * @pdata: platform_data ptr to associate with the platform_device
- +  * @pdata_len: amount of memory pointed to by @pdata
- +  * @pm_lats: pointer to a omap_device_pm_latency array for this device
- +  * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats
- +  * @is_early_device: should the device be registered as an early device or not
- +  *
- +  * Function for building an omap_device already registered from device-tree
- +  *
- +  * Returns 0 or PTR_ERR() on error.
- +  */
- + static int omap_device_build_from_dt(struct platform_device *pdev)
- + {
- + 	struct omap_hwmod **hwmods;
- + 	struct omap_device *od;
- + 	struct omap_hwmod *oh;
- + 	struct device_node *node = pdev->dev.of_node;
- + 	const char *oh_name;
- + 	int oh_cnt, i, ret = 0;
- + 
- + 	oh_cnt = of_property_count_strings(node, "ti,hwmods");
- + 	if (!oh_cnt || IS_ERR_VALUE(oh_cnt)) {
- + 		dev_warn(&pdev->dev, "No 'hwmods' to build omap_device\n");
- + 		return -ENODEV;
- + 	}
- + 
- + 	hwmods = kzalloc(sizeof(struct omap_hwmod *) * oh_cnt, GFP_KERNEL);
- + 	if (!hwmods) {
- + 		ret = -ENOMEM;
- + 		goto odbfd_exit;
- + 	}
- + 
- + 	for (i = 0; i < oh_cnt; i++) {
- + 		of_property_read_string_index(node, "ti,hwmods", i, &oh_name);
- + 		oh = omap_hwmod_lookup(oh_name);
- + 		if (!oh) {
- + 			dev_err(&pdev->dev, "Cannot lookup hwmod '%s'\n",
- + 				oh_name);
- + 			ret = -EINVAL;
- + 			goto odbfd_exit1;
- + 		}
- + 		hwmods[i] = oh;
- + 	}
- + 
- + 	od = omap_device_alloc(pdev, hwmods, oh_cnt, NULL, 0);
- + 	if (!od) {
- + 		dev_err(&pdev->dev, "Cannot allocate omap_device for :%s\n",
- + 			oh_name);
- + 		ret = PTR_ERR(od);
- + 		goto odbfd_exit1;
- + 	}
- + 
- + 	if (of_get_property(node, "ti,no_idle_on_suspend", NULL))
- + 		omap_device_disable_idle_on_suspend(pdev);
- + 
- + 	pdev->dev.pm_domain = &omap_device_pm_domain;
- + 
- + odbfd_exit1:
- + 	kfree(hwmods);
- + odbfd_exit:
- + 	return ret;
- + }
- + 
- + static int _omap_device_notifier_call(struct notifier_block *nb,
- + 				      unsigned long event, void *dev)
- + {
- + 	struct platform_device *pdev = to_platform_device(dev);
- + 
- + 	switch (event) {
- + 	case BUS_NOTIFY_ADD_DEVICE:
- + 		if (pdev->dev.of_node)
- + 			omap_device_build_from_dt(pdev);
- + 		break;
- + 
- + 	case BUS_NOTIFY_DEL_DEVICE:
- + 		if (pdev->archdata.od)
- + 			omap_device_delete(pdev->archdata.od);
- + 		break;
- + 	}
- + 
- + 	return NOTIFY_DONE;
- + }
- + 
- + 
- + /* Public functions for use by core code */
- + 
- + /**
- +  * omap_device_get_context_loss_count - get lost context count
- +  * @od: struct omap_device *
- +  *
- +  * Using the primary hwmod, query the context loss count for this
- +  * device.
- +  *
- +  * Callers should consider context for this device lost any time this
- +  * function returns a value different than the value the caller got
- +  * the last time it called this function.
- +  *
- +  * If any hwmods exist for the omap_device assoiated with @pdev,
- +  * return the context loss counter for that hwmod, otherwise return
- +  * zero.
- +  */
- + int omap_device_get_context_loss_count(struct platform_device *pdev)
- + {
- + 	struct omap_device *od;
- + 	u32 ret = 0;
- + 
- + 	od = to_omap_device(pdev);
- + 
- + 	if (od->hwmods_cnt)
- + 		ret = omap_hwmod_get_context_loss_count(od->hwmods[0]);
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * omap_device_count_resources - count number of struct resource entries needed
- +  * @od: struct omap_device *
- +  *
- +  * Count the number of struct resource entries needed for this
- +  * omap_device @od.  Used by omap_device_build_ss() to determine how
- +  * much memory to allocate before calling
- +  * omap_device_fill_resources().  Returns the count.
- +  */
- + static int omap_device_count_resources(struct omap_device *od)
- + {
- + 	int c = 0;
- + 	int i;
- + 
- + 	for (i = 0; i < od->hwmods_cnt; i++)
- + 		c += omap_hwmod_count_resources(od->hwmods[i]);
- + 
- + 	pr_debug("omap_device: %s: counted %d total resources across %d "
- + 		 "hwmods\n", od->pdev->name, c, od->hwmods_cnt);
- + 
- + 	return c;
- + }
- + 
- + /**
- +  * omap_device_fill_resources - fill in array of struct resource
- +  * @od: struct omap_device *
- +  * @res: pointer to an array of struct resource to be filled in
- +  *
- +  * Populate one or more empty struct resource pointed to by @res with
- +  * the resource data for this omap_device @od.  Used by
- +  * omap_device_build_ss() after calling omap_device_count_resources().
- +  * Ideally this function would not be needed at all.  If omap_device
- +  * replaces platform_device, then we can specify our own
- +  * get_resource()/ get_irq()/etc functions that use the underlying
- +  * omap_hwmod information.  Or if platform_device is extended to use
- +  * subarchitecture-specific function pointers, the various
- +  * platform_device functions can simply call omap_device internal
- +  * functions to get device resources.  Hacking around the existing
- +  * platform_device code wastes memory.  Returns 0.
- +  */
- + static int omap_device_fill_resources(struct omap_device *od,
- + 				      struct resource *res)
- + {
- + 	int c = 0;
- + 	int i, r;
- + 
- + 	for (i = 0; i < od->hwmods_cnt; i++) {
- + 		r = omap_hwmod_fill_resources(od->hwmods[i], res);
- + 		res += r;
- + 		c += r;
- + 	}
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * omap_device_alloc - allocate an omap_device
- +  * @pdev: platform_device that will be included in this omap_device
- +  * @oh: ptr to the single omap_hwmod that backs this omap_device
- +  * @pdata: platform_data ptr to associate with the platform_device
- +  * @pdata_len: amount of memory pointed to by @pdata
- +  * @pm_lats: pointer to a omap_device_pm_latency array for this device
- +  * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats
- +  *
- +  * Convenience function for allocating an omap_device structure and filling
- +  * hwmods, resources and pm_latency attributes.
- +  *
- +  * Returns an struct omap_device pointer or ERR_PTR() on error;
- +  */
- + struct omap_device *omap_device_alloc(struct platform_device *pdev,
- + 					struct omap_hwmod **ohs, int oh_cnt,
- + 					struct omap_device_pm_latency *pm_lats,
- + 					int pm_lats_cnt)
- + {
- + 	int ret = -ENOMEM;
- + 	struct omap_device *od;
- + 	struct resource *res = NULL;
- + 	int i, res_count;
- + 	struct omap_hwmod **hwmods;
- + 
- + 	od = kzalloc(sizeof(struct omap_device), GFP_KERNEL);
- + 	if (!od) {
- + 		ret = -ENOMEM;
- + 		goto oda_exit1;
- + 	}
- + 	od->hwmods_cnt = oh_cnt;
- + 
- + 	hwmods = kmemdup(ohs, sizeof(struct omap_hwmod *) * oh_cnt, GFP_KERNEL);
- + 	if (!hwmods)
- + 		goto oda_exit2;
- + 
- + 	od->hwmods = hwmods;
- + 	od->pdev = pdev;
- + 
- + 	/*
- + 	 * HACK: Ideally the resources from DT should match, and hwmod
- + 	 * should just add the missing ones. Since the name is not
- + 	 * properly populated by DT, stick to hwmod resources only.
- + 	 */
- + 	if (pdev->num_resources && pdev->resource)
- + 		dev_warn(&pdev->dev, "%s(): resources already allocated %d\n",
- + 			__func__, pdev->num_resources);
- + 
- + 	res_count = omap_device_count_resources(od);
- + 	if (res_count > 0) {
- + 		dev_dbg(&pdev->dev, "%s(): resources allocated from hwmod %d\n",
- + 			__func__, res_count);
- + 		res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL);
- + 		if (!res)
- + 			goto oda_exit3;
- + 
- + 		omap_device_fill_resources(od, res);
- + 
- + 		ret = platform_device_add_resources(pdev, res, res_count);
- + 		kfree(res);
- + 
- + 		if (ret)
- + 			goto oda_exit3;
- + 	}
- + 
- + 	if (!pm_lats) {
- + 		pm_lats = omap_default_latency;
- + 		pm_lats_cnt = ARRAY_SIZE(omap_default_latency);
- + 	}
- + 
- + 	od->pm_lats_cnt = pm_lats_cnt;
- + 	od->pm_lats = kmemdup(pm_lats,
- + 			sizeof(struct omap_device_pm_latency) * pm_lats_cnt,
- + 			GFP_KERNEL);
- + 	if (!od->pm_lats)
- + 		goto oda_exit3;
- + 
- + 	pdev->archdata.od = od;
- + 
- + 	for (i = 0; i < oh_cnt; i++) {
- + 		hwmods[i]->od = od;
- + 		_add_hwmod_clocks_clkdev(od, hwmods[i]);
- + 	}
- + 
- + 	return od;
- + 
- + oda_exit3:
- + 	kfree(hwmods);
- + oda_exit2:
- + 	kfree(od);
- + oda_exit1:
- + 	dev_err(&pdev->dev, "omap_device: build failed (%d)\n", ret);
- + 
- + 	return ERR_PTR(ret);
- + }
- + 
- + void omap_device_delete(struct omap_device *od)
- + {
- + 	if (!od)
- + 		return;
- + 
- + 	od->pdev->archdata.od = NULL;
- + 	kfree(od->pm_lats);
- + 	kfree(od->hwmods);
- + 	kfree(od);
- + }
- + 
- + /**
- +  * omap_device_build - build and register an omap_device with one omap_hwmod
- +  * @pdev_name: name of the platform_device driver to use
- +  * @pdev_id: this platform_device's connection ID
- +  * @oh: ptr to the single omap_hwmod that backs this omap_device
- +  * @pdata: platform_data ptr to associate with the platform_device
- +  * @pdata_len: amount of memory pointed to by @pdata
- +  * @pm_lats: pointer to a omap_device_pm_latency array for this device
- +  * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats
- +  * @is_early_device: should the device be registered as an early device or not
- +  *
- +  * Convenience function for building and registering a single
- +  * omap_device record, which in turn builds and registers a
- +  * platform_device record.  See omap_device_build_ss() for more
- +  * information.  Returns ERR_PTR(-EINVAL) if @oh is NULL; otherwise,
- +  * passes along the return value of omap_device_build_ss().
- +  */
- + struct platform_device *omap_device_build(const char *pdev_name, int pdev_id,
- + 				      struct omap_hwmod *oh, void *pdata,
- + 				      int pdata_len,
- + 				      struct omap_device_pm_latency *pm_lats,
- + 				      int pm_lats_cnt, int is_early_device)
- + {
- + 	struct omap_hwmod *ohs[] = { oh };
- + 
- + 	if (!oh)
- + 		return ERR_PTR(-EINVAL);
- + 
- + 	return omap_device_build_ss(pdev_name, pdev_id, ohs, 1, pdata,
- + 				    pdata_len, pm_lats, pm_lats_cnt,
- + 				    is_early_device);
- + }
- + 
- + /**
- +  * omap_device_build_ss - build and register an omap_device with multiple hwmods
- +  * @pdev_name: name of the platform_device driver to use
- +  * @pdev_id: this platform_device's connection ID
- +  * @oh: ptr to the single omap_hwmod that backs this omap_device
- +  * @pdata: platform_data ptr to associate with the platform_device
- +  * @pdata_len: amount of memory pointed to by @pdata
- +  * @pm_lats: pointer to a omap_device_pm_latency array for this device
- +  * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats
- +  * @is_early_device: should the device be registered as an early device or not
- +  *
- +  * Convenience function for building and registering an omap_device
- +  * subsystem record.  Subsystem records consist of multiple
- +  * omap_hwmods.  This function in turn builds and registers a
- +  * platform_device record.  Returns an ERR_PTR() on error, or passes
- +  * along the return value of omap_device_register().
- +  */
- + struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
- + 					 struct omap_hwmod **ohs, int oh_cnt,
- + 					 void *pdata, int pdata_len,
- + 					 struct omap_device_pm_latency *pm_lats,
- + 					 int pm_lats_cnt, int is_early_device)
- + {
- + 	int ret = -ENOMEM;
- + 	struct platform_device *pdev;
- + 	struct omap_device *od;
- + 
- + 	if (!ohs || oh_cnt == 0 || !pdev_name)
- + 		return ERR_PTR(-EINVAL);
- + 
- + 	if (!pdata && pdata_len > 0)
- + 		return ERR_PTR(-EINVAL);
- + 
- + 	pdev = platform_device_alloc(pdev_name, pdev_id);
- + 	if (!pdev) {
- + 		ret = -ENOMEM;
- + 		goto odbs_exit;
- + 	}
- + 
- + 	/* Set the dev_name early to allow dev_xxx in omap_device_alloc */
- + 	if (pdev->id != -1)
- + 		dev_set_name(&pdev->dev, "%s.%d", pdev->name,  pdev->id);
- + 	else
- + 		dev_set_name(&pdev->dev, "%s", pdev->name);
- + 
- + 	od = omap_device_alloc(pdev, ohs, oh_cnt, pm_lats, pm_lats_cnt);
- + 	if (!od)
- + 		goto odbs_exit1;
- + 
- + 	ret = platform_device_add_data(pdev, pdata, pdata_len);
- + 	if (ret)
- + 		goto odbs_exit2;
- + 
- + 	if (is_early_device)
- + 		ret = omap_early_device_register(pdev);
- + 	else
- + 		ret = omap_device_register(pdev);
- + 	if (ret)
- + 		goto odbs_exit2;
- + 
- + 	return pdev;
- + 
- + odbs_exit2:
- + 	omap_device_delete(od);
- + odbs_exit1:
- + 	platform_device_put(pdev);
- + odbs_exit:
- + 
- + 	pr_err("omap_device: %s: build failed (%d)\n", pdev_name, ret);
- + 
- + 	return ERR_PTR(ret);
- + }
- + 
- + /**
- +  * omap_early_device_register - register an omap_device as an early platform
- +  * device.
- +  * @od: struct omap_device * to register
- +  *
- +  * Register the omap_device structure.  This currently just calls
- +  * platform_early_add_device() on the underlying platform_device.
- +  * Returns 0 by default.
- +  */
- + static int omap_early_device_register(struct platform_device *pdev)
- + {
- + 	struct platform_device *devices[1];
- + 
- + 	devices[0] = pdev;
- + 	early_platform_add_devices(devices, 1);
- + 	return 0;
- + }
- + 
- + #ifdef CONFIG_PM_RUNTIME
- + static int _od_runtime_suspend(struct device *dev)
- + {
- + 	struct platform_device *pdev = to_platform_device(dev);
- + 	int ret;
- + 
- + 	ret = pm_generic_runtime_suspend(dev);
- + 
- + 	if (!ret)
- + 		omap_device_idle(pdev);
- + 
- + 	return ret;
- + }
- + 
- + static int _od_runtime_idle(struct device *dev)
- + {
- + 	return pm_generic_runtime_idle(dev);
- + }
- + 
- + static int _od_runtime_resume(struct device *dev)
- + {
- + 	struct platform_device *pdev = to_platform_device(dev);
- + 
- + 	omap_device_enable(pdev);
- + 
- + 	return pm_generic_runtime_resume(dev);
- + }
- + #endif
- + 
- + #ifdef CONFIG_SUSPEND
- + static int _od_suspend_noirq(struct device *dev)
- + {
- + 	struct platform_device *pdev = to_platform_device(dev);
- + 	struct omap_device *od = to_omap_device(pdev);
- + 	int ret;
- + 
- + 	if (od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND)
- + 		return pm_generic_suspend_noirq(dev);
- + 
- + 	ret = pm_generic_suspend_noirq(dev);
- + 
- + 	if (!ret && !pm_runtime_status_suspended(dev)) {
- + 		if (pm_generic_runtime_suspend(dev) == 0) {
- + 			omap_device_idle(pdev);
- + 			od->flags |= OMAP_DEVICE_SUSPENDED;
- + 		}
- + 	}
- + 
- + 	return ret;
- + }
- + 
- + static int _od_resume_noirq(struct device *dev)
- + {
- + 	struct platform_device *pdev = to_platform_device(dev);
- + 	struct omap_device *od = to_omap_device(pdev);
- + 
- + 	if (od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND)
- + 		return pm_generic_resume_noirq(dev);
- + 
- + 	if ((od->flags & OMAP_DEVICE_SUSPENDED) &&
- + 	    !pm_runtime_status_suspended(dev)) {
- + 		od->flags &= ~OMAP_DEVICE_SUSPENDED;
- + 		omap_device_enable(pdev);
- + 		pm_generic_runtime_resume(dev);
- + 	}
- + 
- + 	return pm_generic_resume_noirq(dev);
- + }
- + #else
- + #define _od_suspend_noirq NULL
- + #define _od_resume_noirq NULL
- + #endif
- + 
- + static struct dev_pm_domain omap_device_pm_domain = {
- + 	.ops = {
- + 		SET_RUNTIME_PM_OPS(_od_runtime_suspend, _od_runtime_resume,
- + 				   _od_runtime_idle)
- + 		USE_PLATFORM_PM_SLEEP_OPS
- + 		.suspend_noirq = _od_suspend_noirq,
- + 		.resume_noirq = _od_resume_noirq,
- + 	}
- + };
- + 
- + /**
- +  * omap_device_register - register an omap_device with one omap_hwmod
- +  * @od: struct omap_device * to register
- +  *
- +  * Register the omap_device structure.  This currently just calls
- +  * platform_device_register() on the underlying platform_device.
- +  * Returns the return value of platform_device_register().
- +  */
- + int omap_device_register(struct platform_device *pdev)
- + {
- + 	pr_debug("omap_device: %s: registering\n", pdev->name);
- + 
- + 	pdev->dev.parent = &omap_device_parent;
- + 	pdev->dev.pm_domain = &omap_device_pm_domain;
- + 	return platform_device_add(pdev);
- + }
- + 
- + 
- + /* Public functions for use by device drivers through struct platform_data */
- + 
- + /**
- +  * omap_device_enable - fully activate an omap_device
- +  * @od: struct omap_device * to activate
- +  *
- +  * Do whatever is necessary for the hwmods underlying omap_device @od
- +  * to be accessible and ready to operate.  This generally involves
- +  * enabling clocks, setting SYSCONFIG registers; and in the future may
- +  * involve remuxing pins.  Device drivers should call this function
- +  * (through platform_data function pointers) where they would normally
- +  * enable clocks, etc.  Returns -EINVAL if called when the omap_device
- +  * is already enabled, or passes along the return value of
- +  * _omap_device_activate().
- +  */
- + int omap_device_enable(struct platform_device *pdev)
- + {
- + 	int ret;
- + 	struct omap_device *od;
- + 
- + 	od = to_omap_device(pdev);
- + 
- + 	if (od->_state == OMAP_DEVICE_STATE_ENABLED) {
- + 		dev_warn(&pdev->dev,
- + 			 "omap_device: %s() called from invalid state %d\n",
- + 			 __func__, od->_state);
- + 		return -EINVAL;
- + 	}
- + 
- + 	/* Enable everything if we're enabling this device from scratch */
- + 	if (od->_state == OMAP_DEVICE_STATE_UNKNOWN)
- + 		od->pm_lat_level = od->pm_lats_cnt;
- + 
- + 	ret = _omap_device_activate(od, IGNORE_WAKEUP_LAT);
- + 
- + 	od->dev_wakeup_lat = 0;
- + 	od->_dev_wakeup_lat_limit = UINT_MAX;
- + 	od->_state = OMAP_DEVICE_STATE_ENABLED;
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * omap_device_idle - idle an omap_device
- +  * @od: struct omap_device * to idle
- +  *
- +  * Idle omap_device @od by calling as many .deactivate_func() entries
- +  * in the omap_device's pm_lats table as is possible without exceeding
- +  * the device's maximum wakeup latency limit, pm_lat_limit.  Device
- +  * drivers should call this function (through platform_data function
- +  * pointers) where they would normally disable clocks after operations
- +  * complete, etc..  Returns -EINVAL if the omap_device is not
- +  * currently enabled, or passes along the return value of
- +  * _omap_device_deactivate().
- +  */
- + int omap_device_idle(struct platform_device *pdev)
- + {
- + 	int ret;
- + 	struct omap_device *od;
- + 
- + 	od = to_omap_device(pdev);
- + 
- + 	if (od->_state != OMAP_DEVICE_STATE_ENABLED) {
- + 		dev_warn(&pdev->dev,
- + 			 "omap_device: %s() called from invalid state %d\n",
- + 			 __func__, od->_state);
- + 		return -EINVAL;
- + 	}
- + 
- + 	ret = _omap_device_deactivate(od, USE_WAKEUP_LAT);
- + 
- + 	od->_state = OMAP_DEVICE_STATE_IDLE;
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * omap_device_shutdown - shut down an omap_device
- +  * @od: struct omap_device * to shut down
- +  *
- +  * Shut down omap_device @od by calling all .deactivate_func() entries
- +  * in the omap_device's pm_lats table and then shutting down all of
- +  * the underlying omap_hwmods.  Used when a device is being "removed"
- +  * or a device driver is being unloaded.  Returns -EINVAL if the
- +  * omap_device is not currently enabled or idle, or passes along the
- +  * return value of _omap_device_deactivate().
- +  */
- + int omap_device_shutdown(struct platform_device *pdev)
- + {
- + 	int ret, i;
- + 	struct omap_device *od;
- + 
- + 	od = to_omap_device(pdev);
- + 
- + 	if (od->_state != OMAP_DEVICE_STATE_ENABLED &&
- + 	    od->_state != OMAP_DEVICE_STATE_IDLE) {
- + 		dev_warn(&pdev->dev,
- + 			 "omap_device: %s() called from invalid state %d\n",
- + 			 __func__, od->_state);
- + 		return -EINVAL;
- + 	}
- + 
- + 	ret = _omap_device_deactivate(od, IGNORE_WAKEUP_LAT);
- + 
- + 	for (i = 0; i < od->hwmods_cnt; i++)
- + 		omap_hwmod_shutdown(od->hwmods[i]);
- + 
- + 	od->_state = OMAP_DEVICE_STATE_SHUTDOWN;
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * omap_device_align_pm_lat - activate/deactivate device to match wakeup lat lim
- +  * @od: struct omap_device *
- +  *
- +  * When a device's maximum wakeup latency limit changes, call some of
- +  * the .activate_func or .deactivate_func function pointers in the
- +  * omap_device's pm_lats array to ensure that the device's maximum
- +  * wakeup latency is less than or equal to the new latency limit.
- +  * Intended to be called by OMAP PM code whenever a device's maximum
- +  * wakeup latency limit changes (e.g., via
- +  * omap_pm_set_dev_wakeup_lat()).  Returns 0 if nothing needs to be
- +  * done (e.g., if the omap_device is not currently idle, or if the
- +  * wakeup latency is already current with the new limit) or passes
- +  * along the return value of _omap_device_deactivate() or
- +  * _omap_device_activate().
- +  */
- + int omap_device_align_pm_lat(struct platform_device *pdev,
- + 			     u32 new_wakeup_lat_limit)
- + {
- + 	int ret = -EINVAL;
- + 	struct omap_device *od;
- + 
- + 	od = to_omap_device(pdev);
- + 
- + 	if (new_wakeup_lat_limit == od->dev_wakeup_lat)
- + 		return 0;
- + 
- + 	od->_dev_wakeup_lat_limit = new_wakeup_lat_limit;
- + 
- + 	if (od->_state != OMAP_DEVICE_STATE_IDLE)
- + 		return 0;
- + 	else if (new_wakeup_lat_limit > od->dev_wakeup_lat)
- + 		ret = _omap_device_deactivate(od, USE_WAKEUP_LAT);
- + 	else if (new_wakeup_lat_limit < od->dev_wakeup_lat)
- + 		ret = _omap_device_activate(od, USE_WAKEUP_LAT);
- + 
- + 	return ret;
- + }
- + 
- + /**
- +  * omap_device_get_pwrdm - return the powerdomain * associated with @od
- +  * @od: struct omap_device *
- +  *
- +  * Return the powerdomain associated with the first underlying
- +  * omap_hwmod for this omap_device.  Intended for use by core OMAP PM
- +  * code.  Returns NULL on error or a struct powerdomain * upon
- +  * success.
- +  */
- + struct powerdomain *omap_device_get_pwrdm(struct omap_device *od)
- + {
- + 	/*
- + 	 * XXX Assumes that all omap_hwmod powerdomains are identical.
- + 	 * This may not necessarily be true.  There should be a sanity
- + 	 * check in here to WARN() if any difference appears.
- + 	 */
- + 	if (!od->hwmods_cnt)
- + 		return NULL;
- + 
- + 	return omap_hwmod_get_pwrdm(od->hwmods[0]);
- + }
- + 
- + /**
- +  * omap_device_get_mpu_rt_va - return the MPU's virtual addr for the hwmod base
- +  * @od: struct omap_device *
- +  *
- +  * Return the MPU's virtual address for the base of the hwmod, from
- +  * the ioremap() that the hwmod code does.  Only valid if there is one
- +  * hwmod associated with this device.  Returns NULL if there are zero
- +  * or more than one hwmods associated with this omap_device;
- +  * otherwise, passes along the return value from
- +  * omap_hwmod_get_mpu_rt_va().
- +  */
- + void __iomem *omap_device_get_rt_va(struct omap_device *od)
- + {
- + 	if (od->hwmods_cnt != 1)
- + 		return NULL;
- + 
- + 	return omap_hwmod_get_mpu_rt_va(od->hwmods[0]);
- + }
- + 
- + /**
- +  * omap_device_get_by_hwmod_name() - convert a hwmod name to
- +  * device pointer.
- +  * @oh_name: name of the hwmod device
- +  *
- +  * Returns back a struct device * pointer associated with a hwmod
- +  * device represented by a hwmod_name
- +  */
- + struct device *omap_device_get_by_hwmod_name(const char *oh_name)
- + {
- + 	struct omap_hwmod *oh;
- + 
- + 	if (!oh_name) {
- + 		WARN(1, "%s: no hwmod name!\n", __func__);
- + 		return ERR_PTR(-EINVAL);
- + 	}
- + 
- + 	oh = omap_hwmod_lookup(oh_name);
- + 	if (IS_ERR_OR_NULL(oh)) {
- + 		WARN(1, "%s: no hwmod for %s\n", __func__,
- + 			oh_name);
- + 		return ERR_PTR(oh ? PTR_ERR(oh) : -ENODEV);
- + 	}
- + 	if (IS_ERR_OR_NULL(oh->od)) {
- + 		WARN(1, "%s: no omap_device for %s\n", __func__,
- + 			oh_name);
- + 		return ERR_PTR(oh->od ? PTR_ERR(oh->od) : -ENODEV);
- + 	}
- + 
- + 	if (IS_ERR_OR_NULL(oh->od->pdev))
- + 		return ERR_PTR(oh->od->pdev ? PTR_ERR(oh->od->pdev) : -ENODEV);
- + 
- + 	return &oh->od->pdev->dev;
- + }
- + EXPORT_SYMBOL(omap_device_get_by_hwmod_name);
- + 
- + /*
- +  * Public functions intended for use in omap_device_pm_latency
- +  * .activate_func and .deactivate_func function pointers
- +  */
- + 
- + /**
- +  * omap_device_enable_hwmods - call omap_hwmod_enable() on all hwmods
- +  * @od: struct omap_device *od
- +  *
- +  * Enable all underlying hwmods.  Returns 0.
- +  */
- + int omap_device_enable_hwmods(struct omap_device *od)
- + {
- + 	int i;
- + 
- + 	for (i = 0; i < od->hwmods_cnt; i++)
- + 		omap_hwmod_enable(od->hwmods[i]);
- + 
- + 	/* XXX pass along return value here? */
- + 	return 0;
- + }
- + 
- + /**
- +  * omap_device_idle_hwmods - call omap_hwmod_idle() on all hwmods
- +  * @od: struct omap_device *od
- +  *
- +  * Idle all underlying hwmods.  Returns 0.
- +  */
- + int omap_device_idle_hwmods(struct omap_device *od)
- + {
- + 	int i;
- + 
- + 	for (i = 0; i < od->hwmods_cnt; i++)
- + 		omap_hwmod_idle(od->hwmods[i]);
- + 
- + 	/* XXX pass along return value here? */
- + 	return 0;
- + }
- + 
- + /**
- +  * omap_device_disable_clocks - disable all main and interface clocks
- +  * @od: struct omap_device *od
- +  *
- +  * Disable the main functional clock and interface clock for all of the
- +  * omap_hwmods associated with the omap_device.  Returns 0.
- +  */
- + int omap_device_disable_clocks(struct omap_device *od)
- + {
- + 	int i;
- + 
- + 	for (i = 0; i < od->hwmods_cnt; i++)
- + 		omap_hwmod_disable_clocks(od->hwmods[i]);
- + 
- + 	/* XXX pass along return value here? */
- + 	return 0;
- + }
- + 
- + /**
- +  * omap_device_enable_clocks - enable all main and interface clocks
- +  * @od: struct omap_device *od
- +  *
- +  * Enable the main functional clock and interface clock for all of the
- +  * omap_hwmods associated with the omap_device.  Returns 0.
- +  */
- + int omap_device_enable_clocks(struct omap_device *od)
- + {
- + 	int i;
- + 
- + 	for (i = 0; i < od->hwmods_cnt; i++)
- + 		omap_hwmod_enable_clocks(od->hwmods[i]);
- + 
- + 	/* XXX pass along return value here? */
- + 	return 0;
- + }
- + 
- + /**
- +  * omap_device_reset - reset the module.
- +  * @dev: struct device *
- +  *
- +  * Reset all the hwmods associated with the device @dev.
- +  */
- + int omap_device_reset(struct device *dev)
- + {
- + 	int r = 0;
- + 	int i;
- + 	struct platform_device *pdev = to_platform_device(dev);
- + 	struct omap_device *odev = to_omap_device(pdev);
- + 	struct omap_hwmod *oh;
- + 
- + 	for (i = 0; i < odev->hwmods_cnt; i++) {
- + 		oh = odev->hwmods[i];
- + 		r |= omap_hwmod_reset(oh);
- + 	}
- + 	return r;
- + }
- + 
- + 
- + struct device omap_device_parent = {
- + 	.init_name	= "omap",
- + 	.parent         = &platform_bus,
- + };
- + 
- + static struct notifier_block platform_nb = {
- + 	.notifier_call = _omap_device_notifier_call,
- + };
- + 
- + static int __init omap_device_init(void)
- + {
- + 	bus_register_notifier(&platform_bus_type, &platform_nb);
- + 	return device_register(&omap_device_parent);
- + }
- + core_initcall(omap_device_init);
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/omap-pm-noop.c linux-3.2.1/arch/arm/plat-ckb/omap-pm-noop.c
- *** linux-3.2.1_o/arch/arm/plat-ckb/omap-pm-noop.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/omap-pm-noop.c	2014-05-15 13:25:14.179890715 +0900
- ***************
- *** 0 ****
- --- 1,363 ----
- + /*
- +  * omap-pm-noop.c - OMAP power management interface - dummy version
- +  *
- +  * This code implements the OMAP power management interface to
- +  * drivers, CPUIdle, CPUFreq, and DSP Bridge.  It is strictly for
- +  * debug/demonstration use, as it does nothing but printk() whenever a
- +  * function is called (when DEBUG is defined, below)
- +  *
- +  * Copyright (C) 2008-2009 Texas Instruments, Inc.
- +  * Copyright (C) 2008-2009 Nokia Corporation
- +  * Paul Walmsley
- +  *
- +  * Interface developed by (in alphabetical order):
- +  * Karthik Dasu, Tony Lindgren, Rajendra Nayak, Sakari Poussa, Veeramanikandan
- +  * Raju, Anand Sawant, Igor Stoppa, Paul Walmsley, Richard Woodruff
- +  */
- + 
- + #undef DEBUG
- + 
- + #include <linux/init.h>
- + #include <linux/cpufreq.h>
- + #include <linux/device.h>
- + #include <linux/platform_device.h>
- + 
- + /* Interface documentation is in mach/omap-pm.h */
- + #include <plat/omap-pm.h>
- + #include <plat/omap_device.h>
- + 
- + static bool off_mode_enabled;
- + static int dummy_context_loss_counter;
- + 
- + /*
- +  * Device-driver-originated constraints (via board-*.c files)
- +  */
- + 
- + int omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t)
- + {
- + 	if (!dev || t < -1) {
- + 		WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
- + 		return -EINVAL;
- + 	};
- + 
- + 	if (t == -1)
- + 		pr_debug("OMAP PM: remove max MPU wakeup latency constraint: "
- + 			 "dev %s\n", dev_name(dev));
- + 	else
- + 		pr_debug("OMAP PM: add max MPU wakeup latency constraint: "
- + 			 "dev %s, t = %ld usec\n", dev_name(dev), t);
- + 
- + 	/*
- + 	 * For current Linux, this needs to map the MPU to a
- + 	 * powerdomain, then go through the list of current max lat
- + 	 * constraints on the MPU and find the smallest.  If
- + 	 * the latency constraint has changed, the code should
- + 	 * recompute the state to enter for the next powerdomain
- + 	 * state.
- + 	 *
- + 	 * TI CDP code can call constraint_set here.
- + 	 */
- + 
- + 	return 0;
- + }
- + 
- + int omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r)
- + {
- + 	if (!dev || (agent_id != OCP_INITIATOR_AGENT &&
- + 	    agent_id != OCP_TARGET_AGENT)) {
- + 		WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
- + 		return -EINVAL;
- + 	};
- + 
- + 	if (r == 0)
- + 		pr_debug("OMAP PM: remove min bus tput constraint: "
- + 			 "dev %s for agent_id %d\n", dev_name(dev), agent_id);
- + 	else
- + 		pr_debug("OMAP PM: add min bus tput constraint: "
- + 			 "dev %s for agent_id %d: rate %ld KiB\n",
- + 			 dev_name(dev), agent_id, r);
- + 
- + 	/*
- + 	 * This code should model the interconnect and compute the
- + 	 * required clock frequency, convert that to a VDD2 OPP ID, then
- + 	 * set the VDD2 OPP appropriately.
- + 	 *
- + 	 * TI CDP code can call constraint_set here on the VDD2 OPP.
- + 	 */
- + 
- + 	return 0;
- + }
- + 
- + int omap_pm_set_max_dev_wakeup_lat(struct device *req_dev, struct device *dev,
- + 				   long t)
- + {
- + 	if (!req_dev || !dev || t < -1) {
- + 		WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
- + 		return -EINVAL;
- + 	};
- + 
- + 	if (t == -1)
- + 		pr_debug("OMAP PM: remove max device latency constraint: "
- + 			 "dev %s\n", dev_name(dev));
- + 	else
- + 		pr_debug("OMAP PM: add max device latency constraint: "
- + 			 "dev %s, t = %ld usec\n", dev_name(dev), t);
- + 
- + 	/*
- + 	 * For current Linux, this needs to map the device to a
- + 	 * powerdomain, then go through the list of current max lat
- + 	 * constraints on that powerdomain and find the smallest.  If
- + 	 * the latency constraint has changed, the code should
- + 	 * recompute the state to enter for the next powerdomain
- + 	 * state.  Conceivably, this code should also determine
- + 	 * whether to actually disable the device clocks or not,
- + 	 * depending on how long it takes to re-enable the clocks.
- + 	 *
- + 	 * TI CDP code can call constraint_set here.
- + 	 */
- + 
- + 	return 0;
- + }
- + 
- + int omap_pm_set_max_sdma_lat(struct device *dev, long t)
- + {
- + 	if (!dev || t < -1) {
- + 		WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
- + 		return -EINVAL;
- + 	};
- + 
- + 	if (t == -1)
- + 		pr_debug("OMAP PM: remove max DMA latency constraint: "
- + 			 "dev %s\n", dev_name(dev));
- + 	else
- + 		pr_debug("OMAP PM: add max DMA latency constraint: "
- + 			 "dev %s, t = %ld usec\n", dev_name(dev), t);
- + 
- + 	/*
- + 	 * For current Linux PM QOS params, this code should scan the
- + 	 * list of maximum CPU and DMA latencies and select the
- + 	 * smallest, then set cpu_dma_latency pm_qos_param
- + 	 * accordingly.
- + 	 *
- + 	 * For future Linux PM QOS params, with separate CPU and DMA
- + 	 * latency params, this code should just set the dma_latency param.
- + 	 *
- + 	 * TI CDP code can call constraint_set here.
- + 	 */
- + 
- + 	return 0;
- + }
- + 
- + int omap_pm_set_min_clk_rate(struct device *dev, struct clk *c, long r)
- + {
- + 	if (!dev || !c || r < 0) {
- + 		WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
- + 		return -EINVAL;
- + 	}
- + 
- + 	if (r == 0)
- + 		pr_debug("OMAP PM: remove min clk rate constraint: "
- + 			 "dev %s\n", dev_name(dev));
- + 	else
- + 		pr_debug("OMAP PM: add min clk rate constraint: "
- + 			 "dev %s, rate = %ld Hz\n", dev_name(dev), r);
- + 
- + 	/*
- + 	 * Code in a real implementation should keep track of these
- + 	 * constraints on the clock, and determine the highest minimum
- + 	 * clock rate.  It should iterate over each OPP and determine
- + 	 * whether the OPP will result in a clock rate that would
- + 	 * satisfy this constraint (and any other PM constraint in effect
- + 	 * at that time).  Once it finds the lowest-voltage OPP that
- + 	 * meets those conditions, it should switch to it, or return
- + 	 * an error if the code is not capable of doing so.
- + 	 */
- + 
- + 	return 0;
- + }
- + 
- + /*
- +  * DSP Bridge-specific constraints
- +  */
- + 
- + const struct omap_opp *omap_pm_dsp_get_opp_table(void)
- + {
- + 	pr_debug("OMAP PM: DSP request for OPP table\n");
- + 
- + 	/*
- + 	 * Return DSP frequency table here:  The final item in the
- + 	 * array should have .rate = .opp_id = 0.
- + 	 */
- + 
- + 	return NULL;
- + }
- + 
- + void omap_pm_dsp_set_min_opp(u8 opp_id)
- + {
- + 	if (opp_id == 0) {
- + 		WARN_ON(1);
- + 		return;
- + 	}
- + 
- + 	pr_debug("OMAP PM: DSP requests minimum VDD1 OPP to be %d\n", opp_id);
- + 
- + 	/*
- + 	 *
- + 	 * For l-o dev tree, our VDD1 clk is keyed on OPP ID, so we
- + 	 * can just test to see which is higher, the CPU's desired OPP
- + 	 * ID or the DSP's desired OPP ID, and use whichever is
- + 	 * highest.
- + 	 *
- + 	 * In CDP12.14+, the VDD1 OPP custom clock that controls the DSP
- + 	 * rate is keyed on MPU speed, not the OPP ID.  So we need to
- + 	 * map the OPP ID to the MPU speed for use with clk_set_rate()
- + 	 * if it is higher than the current OPP clock rate.
- + 	 *
- + 	 */
- + }
- + 
- + 
- + u8 omap_pm_dsp_get_opp(void)
- + {
- + 	pr_debug("OMAP PM: DSP requests current DSP OPP ID\n");
- + 
- + 	/*
- + 	 * For l-o dev tree, call clk_get_rate() on VDD1 OPP clock
- + 	 *
- + 	 * CDP12.14+:
- + 	 * Call clk_get_rate() on the OPP custom clock, map that to an
- + 	 * OPP ID using the tables defined in board-*.c/chip-*.c files.
- + 	 */
- + 
- + 	return 0;
- + }
- + 
- + /*
- +  * CPUFreq-originated constraint
- +  *
- +  * In the future, this should be handled by custom OPP clocktype
- +  * functions.
- +  */
- + 
- + struct cpufreq_frequency_table **omap_pm_cpu_get_freq_table(void)
- + {
- + 	pr_debug("OMAP PM: CPUFreq request for frequency table\n");
- + 
- + 	/*
- + 	 * Return CPUFreq frequency table here: loop over
- + 	 * all VDD1 clkrates, pull out the mpu_ck frequencies, build
- + 	 * table
- + 	 */
- + 
- + 	return NULL;
- + }
- + 
- + void omap_pm_cpu_set_freq(unsigned long f)
- + {
- + 	if (f == 0) {
- + 		WARN_ON(1);
- + 		return;
- + 	}
- + 
- + 	pr_debug("OMAP PM: CPUFreq requests CPU frequency to be set to %lu\n",
- + 		 f);
- + 
- + 	/*
- + 	 * For l-o dev tree, determine whether MPU freq or DSP OPP id
- + 	 * freq is higher.  Find the OPP ID corresponding to the
- + 	 * higher frequency.  Call clk_round_rate() and clk_set_rate()
- + 	 * on the OPP custom clock.
- + 	 *
- + 	 * CDP should just be able to set the VDD1 OPP clock rate here.
- + 	 */
- + }
- + 
- + unsigned long omap_pm_cpu_get_freq(void)
- + {
- + 	pr_debug("OMAP PM: CPUFreq requests current CPU frequency\n");
- + 
- + 	/*
- + 	 * Call clk_get_rate() on the mpu_ck.
- + 	 */
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * omap_pm_enable_off_mode - notify OMAP PM that off-mode is enabled
- +  *
- +  * Intended for use only by OMAP PM core code to notify this layer
- +  * that off mode has been enabled.
- +  */
- + void omap_pm_enable_off_mode(void)
- + {
- + 	off_mode_enabled = true;
- + }
- + 
- + /**
- +  * omap_pm_disable_off_mode - notify OMAP PM that off-mode is disabled
- +  *
- +  * Intended for use only by OMAP PM core code to notify this layer
- +  * that off mode has been disabled.
- +  */
- + void omap_pm_disable_off_mode(void)
- + {
- + 	off_mode_enabled = false;
- + }
- + 
- + /*
- +  * Device context loss tracking
- +  */
- + 
- + int omap_pm_get_dev_context_loss_count(struct device *dev)
- + {
- + 	struct platform_device *pdev = to_platform_device(dev);
- + 	int count;
- + 
- + 	if (WARN_ON(!dev))
- + 		return -ENODEV;
- + 
- + 	if (dev->parent == &omap_device_parent) {
- + 		count = omap_device_get_context_loss_count(pdev);
- + 	} else {
- + 		WARN_ONCE(off_mode_enabled, "omap_pm: using dummy context loss counter; device %s should be converted to omap_device",
- + 			  dev_name(dev));
- + 
- + 		count = dummy_context_loss_counter;
- + 
- + 		if (off_mode_enabled) {
- + 			count++;
- + 			/*
- + 			 * Context loss count has to be a non-negative value.
- + 			 * Clear the sign bit to get a value range from 0 to
- + 			 * INT_MAX.
- + 			 */
- + 			count &= INT_MAX;
- + 			dummy_context_loss_counter = count;
- + 		}
- + 	}
- + 
- + 	pr_debug("OMAP PM: context loss count for dev %s = %d\n",
- + 		 dev_name(dev), count);
- + 
- + 	return count;
- + }
- + 
- + 
- + /* Should be called before clk framework init */
- + int __init omap_pm_if_early_init(void)
- + {
- + 	return 0;
- + }
- + 
- + /* Must be called after clock framework is initialized */
- + int __init omap_pm_if_init(void)
- + {
- + 	return 0;
- + }
- + 
- + void omap_pm_if_exit(void)
- + {
- + 	/* Deallocate CPUFreq frequency table here */
- + }
- + 
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/sdma2edma.c linux-3.2.1/arch/arm/plat-ckb/sdma2edma.c
- *** linux-3.2.1_o/arch/arm/plat-ckb/sdma2edma.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/sdma2edma.c	2014-05-15 13:25:14.179890715 +0900
- ***************
- *** 0 ****
- --- 1,358 ----
- + /*
- +  * sdma2edma.c
- +  *
- +  * SDMA to EDMA3 Wrapper.
- +  *
- +  * NOTE: Since we are invoking EDMA API, comments for all APIs in this file
- +  * are EDMA specific.
- +  *
- +  * Copyright (C) 2010-2011 Texas Instruments.
- +  * Author: Mansoor Ahamed <mansoor.ahamed@ti.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; either version 2 of the License, or
- +  * (at your option) any later version.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- +  */
- + 
- + #include <linux/module.h>
- + #include <linux/init.h>
- + #include <linux/sched.h>
- + #include <linux/spinlock.h>
- + #include <linux/errno.h>
- + #include <linux/interrupt.h>
- + #include <linux/irq.h>
- + #include <linux/io.h>
- + 
- + #include <asm/system.h>
- + #include <mach/hardware.h>
- + #include <plat/dma.h>
- + 
- + /* some edma specific hacks which might change */
- + #include <mach/edma.h>
- + 
- + /**
- +  * omap_request_dma - allocate DMA channel and paired parameter RAM
- +  * @dev_id: specific channel to allocate; negative for "any unmapped channel"
- +  * @callback: optional; to be issued on DMA completion or errors
- +  * @data: passed to callback
- +  * @dma_ch_out: allocated channel number returned in this variable
- +  *
- +  * This allocates a DMA channel and its associated parameter RAM slot.
- +  * The parameter RAM is initialized to hold a dummy transfer.
- +  *
- +  * Normal use is to pass a specific channel number as @channel, to make
- +  * use of hardware events mapped to that channel.  When the channel will
- +  * be used only for software triggering or event chaining, channels not
- +  * mapped to hardware events (or mapped to unused events) are preferable.
- +  *
- +  * DMA transfers start from a channel using edma_start(), or by
- +  * chaining.  When the transfer described in that channel's parameter RAM
- +  * slot completes, that slot's data may be reloaded through a link.
- +  *
- +  * DMA errors are only reported to the @callback associated with the
- +  * channel driving that transfer, but transfer completion callbacks can
- +  * be sent to another channel under control of the TCC field in
- +  * the option word of the transfer's parameter RAM set.  Drivers must not
- +  * use DMA transfer completion callbacks for channels they did not allocate.
- +  * (The same applies to TCC codes used in transfer chaining.)
- +  *
- +  * TODO: -
- +  * . In the edma call, last param i.e TC hard coded to EVENTQ_2
- +  * . The callback's ch_status which should be used in McSPI driver
- +  *   to stop/clean EDMA is currently ignored in some driver (eg. McSPI)
- +  */
- + int omap_request_dma(int dev_id, const char *dev_name,
- + 		void (*callback)(int lch, u16 ch_status, void *data),
- + 		void *data, int *dma_ch_out)
- + {
- + 	struct edmacc_param p_ram;
- + 	typedef void (*EDMA_CALLBACK)(unsigned, u16, void*);
- + 	EDMA_CALLBACK edma_callback = (EDMA_CALLBACK)(callback);
- + 
- + 	*dma_ch_out = edma_alloc_channel(dev_id, edma_callback, data, EVENTQ_2);
- + 	if (*dma_ch_out < 0)
- + 		return -1;
- + 
- + 	/* enable interrupts */
- + 	edma_read_slot(*dma_ch_out, &p_ram);
- + 	p_ram.opt |= TCINTEN | EDMA_TCC(EDMA_CHAN_SLOT(*dma_ch_out));
- + 	edma_write_slot(*dma_ch_out, &p_ram);
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(omap_request_dma);
- + 
- + /**
- +  * omap_free_dma - deallocate DMA channel
- +  * @lch: dma channel returned from edma_alloc_channel()
- +  *
- +  * This deallocates the DMA channel and associated parameter RAM slot
- +  * allocated by omap_request_dma().
- +  *
- +  * Callers are responsible for ensuring the channel is inactive, and
- +  * will not be reactivated by linking, chaining, or software calls to
- +  * omap_start_dma().
- +  */
- + void omap_free_dma(int lch)
- + {
- + 	edma_free_channel((unsigned)lch);
- + }
- + EXPORT_SYMBOL(omap_free_dma);
- + 
- + /**
- +  * omap_start_dma - start dma on a channel
- +  * @lch: channel being activated
- +  *
- +  * Channels with event associations will be triggered by their hardware
- +  * events, and channels without such associations will be triggered by
- +  * software.  (At this writing there is no interface for using software
- +  * triggers except with channels that don't support hardware triggers.)
- +  *
- +  */
- + void omap_start_dma(int lch)
- + {
- + 	edma_start((unsigned)lch);
- + }
- + EXPORT_SYMBOL(omap_start_dma);
- + 
- + /**
- +  * omap_stop_dma - stops dma on the channel passed
- +  * @lch: channel being deactivated
- +  *
- +  * When @lch is a channel, any active transfer is paused and
- +  * all pending hardware events are cleared.  The current transfer
- +  * may not be resumed, and the channel's Parameter RAM should be
- +  * reinitialized before being reused.
- +  */
- + void omap_stop_dma(int lch)
- + {
- + 	edma_stop((unsigned)lch);
- + }
- + EXPORT_SYMBOL(omap_stop_dma);
- + 
- + /**
- +  * omap_cleanup_dma - Bring back DMA to initial state
- +  * @lch: channel being cleaned up
- +  *
- +  * It cleans ParamEntry and bring back EDMA to initial state if media has
- +  * been removed before EDMA has finished.It is usedful for removable media.
- +  *
- +  *
- +  * FIXME this should not be needed ... edma_stop() should suffice.
- +  *
- +  */
- + void omap_cleanup_dma(int lch)
- + {
- + 	edma_clean_channel((unsigned)lch);
- + }
- + EXPORT_SYMBOL(omap_cleanup_dma);
- + 
- + /**
- +  * omap_set_dma_transfer_params - configure DMA transfer parameters
- +  * @lch: parameter RAM slot being configured
- +  * @data_type: how many bytes per array (at least one)
- +  * @elem_count: how many arrays per frame (at least one)
- +  * @frame_count: how many frames per block (at least one)
- +  * @sync_mode: ASYNC or ABSYNC
- +  * @dma_trigger: device id (not used)
- +  * @src_or_dst_synch: not used
- +  *
- +  * See the EDMA3 documentation to understand how to configure and link
- +  * transfers using the fields in PaRAM slots.  If you are not doing it
- +  * all at once with edma_write_slot(), you will use this routine
- +  * plus two calls each for source and destination, setting the initial
- +  * address and saying how to index that address.
- +  *
- +  * An example of an A-Synchronized transfer is a serial link using a
- +  * single word shift register.  In that case, @acnt would be equal to
- +  * that word size; the serial controller issues a DMA synchronization
- +  * event to transfer each word, and memory access by the DMA transfer
- +  * controller will be word-at-a-time.
- +  *
- +  * An example of an AB-Synchronized transfer is a device using a FIFO.
- +  * In that case, @acnt equals the FIFO width and @bcnt equals its depth.
- +  * The controller with the FIFO issues DMA synchronization events when
- +  * the FIFO threshold is reached, and the DMA transfer controller will
- +  * transfer one frame to (or from) the FIFO.  It will probably use
- +  * efficient burst modes to access memory.
- +  *
- +  * . dma_trigger and channel number, this is ignored for EDMA
- +  * . Setting bcnt_rld same as bcnt
- +  * TODO
- +  * . what is src_or_dst_synch?
- +  */
- + void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
- + 			int frame_count, int sync_mode,
- + 			int dma_trigger, int src_or_dst_synch)
- + {
- + 	int d_type[3] = {1, 2, 4};
- + 	if ((enum sync_dimension)sync_mode > ABSYNC) {
- + 		printk(KERN_ERR "SDMA2EDMA: Line:%d : Param \'sync_mode\' out"
- + 				" of range\n", __LINE__);
- + 		return;
- + 	}
- + 
- + 	/* translate data_type */
- + 	data_type = d_type[data_type];
- + 
- + 	edma_set_transfer_params(lch, (u16)data_type, (u16)elem_count,
- + 					(u16)frame_count, (u16)elem_count,
- + 					(enum sync_dimension)sync_mode);
- + }
- + EXPORT_SYMBOL(omap_set_dma_transfer_params);
- + 
- + /**
- +  * omap_set_dma_dest_params - Set initial DMA destination addr in param RAM slot
- +  * @lch: parameter RAM slot being configured
- +  * @dest_port: not used
- +  * @dest_amode: INCR, except in very rare cases
- +  * @dest_start: physical address of destination (memory, controller FIFO, etc)
- +  * @dst_ei: byte offset between destination arrays in a frame
- +  * @dst_fi: byte offset between destination frames in a block
- +  *
- +  * Note that the destination address is modified during the DMA transfer
- +  * according to edma_set_dest_index().
- +  *
- +  * TODO
- +  * . Not sure about dst_ei and dst_fi
- +  * . fifo_width for edma is not available in sdma API hence setting it to
- +  *   W8BIT
- +  * . dest_port is ignored
- +  */
- + void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
- + 			unsigned long dest_start, int dst_ei, int dst_fi)
- + {
- + 	if ((enum address_mode)dest_amode > FIFO) {
- + 		printk(KERN_ERR "SDMA2EDMA: Line:%d : Param \'dest_amode\' out"
- + 				" of range\n", __LINE__);
- + 		return;
- + 	}
- + 
- + 	edma_set_dest((unsigned)lch, (dma_addr_t)dest_start,
- + 					!dest_amode, W32BIT);
- + 	edma_set_dest_index((unsigned)(lch), (s16)dst_ei, (s16)dst_fi);
- + }
- + EXPORT_SYMBOL(omap_set_dma_dest_params);
- + 
- + /**
- +  * omap_set_dma_src_params - Set initial DMA source addr in param RAM slot
- +  * @lch: parameter RAM slot being configured
- +  * @src_port: not used
- +  * @src_amode: INCR, except in very rare cases
- +  * @src_start: physical address of destination (memory, controller FIFO, etc)
- +  * @src_ei: byte offset between destination arrays in a frame
- +  * @src_fi: byte offset between destination frames in a block
- +  *
- +  * Note that the source address is modified during the DMA transfer
- +  * according to edma_set_src_index().
- +  *
- +  * TODO
- +  * . Not sure about src_ei and src_fi
- +  * . fifo_width for edma is not available in sdma API hence setting it to
- +  *   W8BIT
- +  * . src_port is ignored
- +  */
- + void omap_set_dma_src_params(int lch, int src_port, int src_amode,
- + 			unsigned long src_start, int src_ei, int src_fi)
- + {
- + 	if ((enum address_mode)src_amode > FIFO) {
- + 		printk(KERN_ERR "SDMA2EDMA: Line:%d : Param \'src_amode\' out "
- + 				"of range\n", __LINE__);
- + 		return;
- + 	}
- + 
- + 	edma_set_src((unsigned)lch, (dma_addr_t)src_start,
- + 					!src_amode, W32BIT);
- + 	edma_set_src_index((unsigned)(lch), (s16)src_ei, (s16)src_fi);
- + }
- + EXPORT_SYMBOL(omap_set_dma_src_params);
- + 
- + void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
- + {
- + 	printk(KERN_WARNING "omap_set_dma_src_burst_mode: un-supported SDMA"
- + 				" wrapper\n");
- + }
- + EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
- + 
- + void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
- + {
- + 	printk(KERN_WARNING "omap_set_dma_dest_burst_mode: un-supported SDMA"
- + 				" wrapper\n");
- + }
- + EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
- + 
- + dma_addr_t omap_get_dma_dst_pos(int lch)
- + {
- + 	printk(KERN_WARNING "omap_get_dma_dst_pos: un-supported in SDMA"
- + 				" wrapper\n");
- + 	return 0;
- + }
- + EXPORT_SYMBOL(omap_get_dma_dst_pos);
- + 
- + int omap_get_dma_active_status(int lch)
- + {
- + 	printk(KERN_WARNING "omap_get_dma_active_status: un-supported in SDMA"
- + 				" wrapper\n");
- + 	return 0;
- + }
- + EXPORT_SYMBOL(omap_get_dma_active_status);
- + 
- + void omap_dma_global_context_save(void)
- + {
- + 	printk(KERN_WARNING "omap_dma_global_context_save: un-supported in SDMA"
- + 				" wrapper\n");
- + }
- + EXPORT_SYMBOL(omap_dma_global_context_save);
- + 
- + void omap_dma_global_context_restore(void)
- + {
- + 	printk(KERN_WARNING "omap_dma_global_context_restore: un-supported in"
- + 				"SDMA wrapper\n");
- + }
- + EXPORT_SYMBOL(omap_dma_global_context_restore);
- + 
- + int omap_dma_running(void)
- + {
- + 	printk(KERN_WARNING "omap_dma_running: un-supported in SDMA wrapper\n");
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(omap_dma_running);
- + 
- + void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
- + {
- + 	printk(KERN_WARNING "omap_set_dma_color_mode: un-supported in"
- + 				"SDMA wrapper\n");
- + }
- + EXPORT_SYMBOL(omap_set_dma_color_mode);
- + 
- + void omap_set_dma_dest_data_pack(int lch, int enable)
- + {
- + 	printk(KERN_WARNING "omap_set_dma_dest_data_pack: un-supported in"
- + 				"SDMA wrapper\n");
- + }
- + EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
- + 
- + void omap_set_dma_src_data_pack(int lch, int enable)
- + {
- + 	printk(KERN_WARNING "omap_set_dma_src_data_pack: un-supported in"
- + 				"SDMA wrapper\n");
- + }
- + EXPORT_SYMBOL(omap_set_dma_src_data_pack);
- + 
- + void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
- + {
- + 	printk(KERN_WARNING "omap_set_dma_write_mode: un-supported in"
- + 				"SDMA wrapper\n");
- + }
- + EXPORT_SYMBOL(omap_set_dma_write_mode);
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/sram.c linux-3.2.1/arch/arm/plat-ckb/sram.c
- *** linux-3.2.1_o/arch/arm/plat-ckb/sram.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/sram.c	2014-05-15 13:25:14.179890715 +0900
- ***************
- *** 0 ****
- --- 1,153 ----
- + /*
- +  * linux/arch/arm/plat-omap/sram.c
- +  *
- +  * OMAP SRAM detection and management
- +  *
- +  * Copyright (C) 2005 Nokia Corporation
- +  * Written by Tony Lindgren <tony@atomide.com>
- +  *
- +  * Copyright (C) 2009 Texas Instruments
- +  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + #undef DEBUG
- + 
- + #include <linux/module.h>
- + #include <linux/kernel.h>
- + #include <linux/init.h>
- + #include <linux/io.h>
- + 
- + #include <asm/tlb.h>
- + #include <asm/cacheflush.h>
- + 
- + #include <asm/mach/map.h>
- + 
- + #include <plat/sram.h>
- + #include <plat/board.h>
- + #include <plat/cpu.h>
- + 
- + #include "sram.h"
- + 
- + /* XXX These "sideways" includes are a sign that something is wrong */
- + //# include "../mach-omap2/prm2xxx_3xxx.h"
- + # include "../mach-ckb_3352/sdrc.h"
- + 
- + #define SRAM_BOOTLOADER_SZ	0x00
- + 
- + #define GP_DEVICE		0x300
- + 
- + #define ROUND_DOWN(value,boundary)	((value) & (~((boundary)-1)))
- + 
- + static unsigned long omap_sram_start;
- + static void __iomem *omap_sram_base;
- + static unsigned long omap_sram_size;
- + 
- + 
- + struct gen_pool *omap_gen_pool;
- + EXPORT_SYMBOL_GPL(omap_gen_pool);
- + 
- + /*
- +  * The amount of SRAM depends on the core type.
- +  * Note that we cannot try to test for SRAM here because writes
- +  * to secure SRAM will hang the system. Also the SRAM is not
- +  * yet mapped at this point.
- +  */
- + static void __init omap_detect_sram(void)
- + {
- + #if 0
- + 	if (is_sram_locked()) {
- + 		omap_sram_start = OMAP2_SRAM_PUB_PA;
- + 		omap_sram_size = 0x800; /* 2K */
- + 	} else {
- + 		omap_sram_start = AM33XX_SRAM_PA;
- + 		omap_sram_size = 0x10000; /* 64K */
- + 	}
- + #else
- + 	omap_sram_start = OMAP3_SUSPEND_SRAM_PA;
- + 	omap_sram_size = 0x6400; /* 25K */
- + #endif
- + }
- + 
- + /*
- +  * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
- +  */
- + static void __init omap_map_sram(void)
- + {
- + 	if (omap_sram_size == 0)
- + 		return;
- + 
- + 	/*
- + 	 * SRAM must be marked as non-cached on OMAP3 since the
- + 	 * CORE DPLL M2 divider change code (in SRAM) runs with the
- + 	 * SDRAM controller disabled, and if it is marked cached,
- + 	 * the ARM may attempt to write cache lines back to SDRAM
- + 	 * which will cause the system to hang.
- + 	 */
- + 
- + 	omap_sram_start = ROUND_DOWN(omap_sram_start, PAGE_SIZE);
- + 	omap_sram_base = __arm_ioremap_exec(omap_sram_start, omap_sram_size,
- + 						0);
- + 	if (!omap_sram_base) {
- + 		pr_err("SRAM: Could not map\n");
- + 		return;
- + 	}
- + 
- + 	/*
- + 	 * Looks like we need to preserve some bootloader code at the
- + 	 * beginning of SRAM for jumping to flash for reboot to work...
- + 	 */
- + 	memset((void *)omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
- + 	       omap_sram_size - SRAM_BOOTLOADER_SZ);
- + 	{
- + 		/* The first SRAM_BOOTLOADER_SZ of SRAM are reserved */
- + 		void *base = (void *)omap_sram_base + SRAM_BOOTLOADER_SZ;
- + 		phys_addr_t phys = omap_sram_start + SRAM_BOOTLOADER_SZ;
- + 		size_t len = omap_sram_size - SRAM_BOOTLOADER_SZ;
- + 
- + 		omap_gen_pool = gen_pool_create(ilog2(FNCPY_ALIGN), -1);
- + 		if (omap_gen_pool)
- + 			WARN_ON(gen_pool_add_virt(omap_gen_pool,
- + 					(unsigned long)base, phys, len, -1));
- + 		WARN_ON(!omap_gen_pool);
- + 	}
- + }
- + 
- + static u32 (*_omap3_sram_configure_core_dpll)(
- + 			u32 m2, u32 unlock_dll, u32 f, u32 inc,
- + 			u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
- + 			u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
- + 			u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
- + 			u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
- + 
- + u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
- + 			u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
- + 			u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
- + 			u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
- + 			u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
- + {
- + 	BUG_ON(!_omap3_sram_configure_core_dpll);
- + 	return _omap3_sram_configure_core_dpll(
- + 			m2, unlock_dll, f, inc,
- + 			sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
- + 			sdrc_actim_ctrl_b_0, sdrc_mr_0,
- + 			sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
- + 			sdrc_actim_ctrl_b_1, sdrc_mr_1);
- + }
- + 
- + static inline int am33xx_sram_init(void)
- + {
- + 	am33xx_push_sram_idle();
- + 	return 0;
- + }
- + 
- + int __init omap_sram_init(void)
- + {
- + 	omap_detect_sram();
- + 	omap_map_sram();
- + 	am33xx_sram_init();
- + 
- + 	return 0;
- + }
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/sram.h linux-3.2.1/arch/arm/plat-ckb/sram.h
- *** linux-3.2.1_o/arch/arm/plat-ckb/sram.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/sram.h	2014-05-15 13:25:14.179890715 +0900
- ***************
- *** 0 ****
- --- 1,6 ----
- + #ifndef __PLAT_OMAP_SRAM_H__
- + #define __PLAT_OMAP_SRAM_H__
- + 
- + extern int __init omap_sram_init(void);
- + 
- + #endif /* __PLAT_OMAP_SRAM_H__ */
- diff -crN linux-3.2.1_o/arch/arm/plat-ckb/usb.c linux-3.2.1/arch/arm/plat-ckb/usb.c
- *** linux-3.2.1_o/arch/arm/plat-ckb/usb.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/arch/arm/plat-ckb/usb.c	2014-05-15 13:25:14.179890715 +0900
- ***************
- *** 0 ****
- --- 1,128 ----
- +  /*
- +  * arch/arm/plat-omap/usb.c -- platform level USB initialization
- +  *
- +  * Copyright (C) 2004 Texas Instruments, Inc.
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; either version 2 of the License, or
- +  * (at your option) any later version.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- +  */
- + 
- + #undef	DEBUG
- + 
- + #include <linux/module.h>
- + #include <linux/kernel.h>
- + #include <linux/init.h>
- + #include <linux/platform_device.h>
- + #include <linux/io.h>
- + 
- + #include <plat/usb.h>
- + #include <plat/board.h>
- + 
- + #ifdef	CONFIG_ARCH_OMAP_OTG
- + 
- + void __init
- + omap_otg_init(struct omap_usb_config *config)
- + {
- + 	u32		syscon;
- + 	int		status;
- + 	int		alt_pingroup = 0;
- + 
- + 	/* NOTE:  no bus or clock setup (yet?) */
- + 
- + 	syscon = omap_readl(OTG_SYSCON_1) & 0xffff;
- + 	if (!(syscon & OTG_RESET_DONE))
- + 		pr_debug("USB resets not complete?\n");
- + 
- + 	//omap_writew(0, OTG_IRQ_EN);
- + 
- + 	/* pin muxing and transceiver pinouts */
- + 	if (config->pins[0] > 2)	/* alt pingroup 2 */
- + 		alt_pingroup = 1;
- + 	syscon |= config->usb0_init(config->pins[0], is_usb0_device(config));
- + 	syscon |= config->usb1_init(config->pins[1]);
- + 	syscon |= config->usb2_init(config->pins[2], alt_pingroup);
- + 	pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
- + 	omap_writel(syscon, OTG_SYSCON_1);
- + 
- + 	syscon = config->hmc_mode;
- + 	syscon |= USBX_SYNCHRO | (4 << 16) /* B_ASE0_BRST */;
- + #ifdef	CONFIG_USB_OTG
- + 	if (config->otg)
- + 		syscon |= OTG_EN;
- + #endif
- + 	
- + 	pr_debug("OTG_SYSCON_2 = %08x\n", omap_readl(OTG_SYSCON_2));
- + 	omap_writel(syscon, OTG_SYSCON_2);
- + 
- + 	printk("USB: hmc %d", config->hmc_mode);
- + 	if (!alt_pingroup)
- + 		printk(", usb2 alt %d wires", config->pins[2]);
- + 	else if (config->pins[0])
- + 		printk(", usb0 %d wires%s", config->pins[0],
- + 			is_usb0_device(config) ? " (dev)" : "");
- + 	if (config->pins[1])
- + 		printk(", usb1 %d wires", config->pins[1]);
- + 	if (!alt_pingroup && config->pins[2])
- + 		printk(", usb2 %d wires", config->pins[2]);
- + 	if (config->otg)
- + 		printk(", Mini-AB on usb%d", config->otg - 1);
- + 	printk("\n");
- + 
- + 	syscon = omap_readl(OTG_SYSCON_1);
- + 	syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN;
- + 
- + #ifdef	CONFIG_USB_GADGET_OMAP
- + 	if (config->otg || config->register_dev) {
- + 		struct platform_device *udc_device = config->udc_device;
- + 
- + 		syscon &= ~DEV_IDLE_EN;
- + 		udc_device->dev.platform_data = config;
- + 		status = platform_device_register(udc_device);
- + 		if (status)
- + 			pr_debug("can't register UDC device, %d\n", status);
- + 	}
- + #endif
- + 
- + #if	defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
- + 	if (config->otg || config->register_host) {
- + 		struct platform_device *ohci_device = config->ohci_device;
- + 
- + 		syscon &= ~HST_IDLE_EN;
- + 		ohci_device->dev.platform_data = config;
- + 		status = platform_device_register(ohci_device);
- + 		if (status)
- + 			pr_debug("can't register OHCI device, %d\n", status);
- + 	}
- + #endif
- + 
- + #ifdef	CONFIG_USB_OTG
- + 	if (config->otg) {
- + 		struct platform_device *otg_device = config->otg_device;
- + 
- + 		syscon &= ~OTG_IDLE_EN;
- + 		otg_device->dev.platform_data = config;
- + 		status = platform_device_register(otg_device);
- + 		if (status)
- + 			pr_debug("can't register OTG device, %d\n", status);
- + 	}
- + #endif
- + 	pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
- + 	omap_writel(syscon, OTG_SYSCON_1);
- + 
- + 	status = 0;
- + }
- + 
- + #else
- + void omap_otg_init(struct omap_usb_config *config) {}
- + #endif
- diff -crN linux-3.2.1_o/arch/arm/tools/mach-types linux-3.2.1/arch/arm/tools/mach-types
- *** linux-3.2.1_o/arch/arm/tools/mach-types	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/arch/arm/tools/mach-types	2014-05-15 13:25:14.200022307 +0900
- ***************
- *** 1126,1128 ****
- --- 1126,1129 ----
-   m28evk			MACH_M28EVK		M28EVK			3613
-   smdk4212		MACH_SMDK4212		SMDK4212		3638
-   smdk4412		MACH_SMDK4412		SMDK4412		3765
- + ckb_3352		MACH_CKB_3352		CKB_3352		4744
- diff -crN linux-3.2.1_o/drivers/char/hw_random/Kconfig linux-3.2.1/drivers/char/hw_random/Kconfig
- *** linux-3.2.1_o/drivers/char/hw_random/Kconfig	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/char/hw_random/Kconfig	2014-05-15 13:25:14.200022307 +0900
- ***************
- *** 139,144 ****
- --- 139,157 ----
-   
-    	  If unsure, say Y.
-   
- + config HW_RANDOM_OMAP4
- + 	tristate "OMAP4 Random Number Generator support"
- + 	depends on HW_RANDOM && SOC_OMAPAM33XX
- + 	default HW_RANDOM
- + 	---help---
- + 	  This driver provides kernel-side support for the Random Number
- + 	  Generator hardware found on OMAP4 derived processors.
- + 
- + 	  To compile this driver as a module, choose M here: the
- + 	  module will be called omap4-rng.
- + 
- + 	  If unsure, say Y.
- + 
-   config HW_RANDOM_OCTEON
-   	tristate "Octeon Random Number Generator support"
-   	depends on HW_RANDOM && CPU_CAVIUM_OCTEON
- diff -crN linux-3.2.1_o/drivers/char/hw_random/Makefile linux-3.2.1/drivers/char/hw_random/Makefile
- *** linux-3.2.1_o/drivers/char/hw_random/Makefile	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/char/hw_random/Makefile	2014-05-15 13:25:14.200022307 +0900
- ***************
- *** 14,19 ****
- --- 14,20 ----
-   obj-$(CONFIG_HW_RANDOM_VIA) += via-rng.o
-   obj-$(CONFIG_HW_RANDOM_IXP4XX) += ixp4xx-rng.o
-   obj-$(CONFIG_HW_RANDOM_OMAP) += omap-rng.o
- + obj-$(CONFIG_HW_RANDOM_OMAP4) += omap4-rng.o
-   obj-$(CONFIG_HW_RANDOM_PASEMI) += pasemi-rng.o
-   obj-$(CONFIG_HW_RANDOM_VIRTIO) += virtio-rng.o
-   obj-$(CONFIG_HW_RANDOM_TX4939) += tx4939-rng.o
- diff -crN linux-3.2.1_o/drivers/char/hw_random/omap4-rng.c linux-3.2.1/drivers/char/hw_random/omap4-rng.c
- *** linux-3.2.1_o/drivers/char/hw_random/omap4-rng.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/drivers/char/hw_random/omap4-rng.c	2014-05-15 13:25:14.200022307 +0900
- ***************
- *** 0 ****
- --- 1,301 ----
- + /*
- +  * drivers/char/hw_random/omap4-rng.c
- +  *
- +  * Copyright (c) 2012 Texas Instruments
- +  * TRNG driver for OMAP4 derivatives (AM33x, etc) -  Herman Schuurman <herman@ti.com>
- +  *
- +  * derived from omap-rng.c.
- +  *
- +  * Author: Deepak Saxena <dsaxena@plexity.net>
- +  *
- +  * Copyright 2005 (c) MontaVista Software, Inc.
- +  *
- +  * Mostly based on original driver:
- +  *
- +  * Copyright (C) 2005 Nokia Corporation
- +  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
- +  *
- +  * This file is licensed under  the terms of the GNU General Public
- +  * License version 2. This program is licensed "as is" without any
- +  * warranty of any kind, whether express or implied.
- +  */
- + 
- + #include <linux/module.h>
- + #include <linux/init.h>
- + #include <linux/random.h>
- + #include <linux/pm_runtime.h>
- + #include <linux/err.h>
- + #include <linux/platform_device.h>
- + #include <linux/hw_random.h>
- + #include <linux/delay.h>
- + 
- + #include <mach/hardware.h>
- + #include <asm/io.h>
- + 
- + /* ==================================================================== */
- + /** RNG module layout.
- +  */
- + /* ==================================================================== */
- + #define	RNG_REG_OUTPUT_L		0x00
- + #define	RNG_REG_OUTPUT_H		0x04
- + 
- + #define	RNG_REG_STATUS			0x08
- + #define	RNG_REG_STATUS_NEED_CLK		(1 << 31)
- + #define	RNG_REG_STATUS_SHUTDOWN_OFLO	(1 << 1)
- + #define	RNG_REG_STATUS_RDY		(1 << 0)
- + 
- + #define	RNG_REG_IMASK			0x0C
- + #define	RNG_REG_IMASK_SHUTDOWN_OFLO	(1 << 1)
- + #define	RNG_REG_IMASK_RDY		(1 << 0)
- + 
- + #define	RNG_REG_INTACK			0x10
- + #define	RNG_REG_INTACK_SHUTDOWN_OFLO	(1 << 1)
- + #define	RNG_REG_INTACK_RDY		(1 << 0)
- + 
- + #define	RNG_REG_CONTROL			0x14
- + #define	RNG_REG_CONTROL_STARTUP_MASK	0xFFFF0000
- + #define	RNG_REG_CONTROL_ENABLE_TRNG	(1 << 10)
- + #define	RNG_REG_CONTROL_NO_LFSR_FB	(1 << 2)
- + 
- + #define	RNG_REG_CONFIG			0x18
- + #define	RNG_REG_CONFIG_MAX_REFILL_MASK	0xFFFF0000
- + #define	RNG_REG_CONFIG_SAMPLE_DIV	0x00000F00
- + #define	RNG_REG_CONFIG_MIN_REFILL_MASK	0x000000FF
- + 
- + #define	RNG_REG_ALARMCNT		0x1C
- + #define	RNG_REG_ALARMCNT_SHTDWN_MASK	0x3F000000
- + #define	RNG_REG_ALARMCNT_SD_THLD_MASK	0x001F0000
- + #define	RNG_REG_ALARMCNT_ALM_THLD_MASK	0x000000FF
- + 
- + #define	RNG_REG_FROENABLE		0x20
- + #define	RNG_REG_FRODETUNE		0x24
- + #define	RNG_REG_ALARMMASK		0x28
- + #define	RNG_REG_ALARMSTOP		0x2C
- + #define	RNG_REG_LFSR_L			0x30
- + #define	RNG_REG_LFSR_M			0x34
- + #define	RNG_REG_LFSR_H			0x38
- + #define	RNG_REG_COUNT			0x3C
- + #define	RNG_REG_TEST			0x40
- + 
- + #define	RNG_REG_OPTIONS			0x78
- + #define	RNG_REG_OPTIONS_NUM_FROS_MASK	0x00000FC0
- + 
- + #define	RNG_REG_EIP_REV			0x7C
- + #define	RNG_REG_STATUS_EN		0x1FD8
- + #define	RNG_REG_STATUS_EN_SHUTDOWN_OFLO	(1 << 1)
- + #define	RNG_REG_STATUS_EN_RDY		(1 << 0)
- + 
- + #define	RNG_REG_REV			0x1FE0
- + #define	 RNG_REG_REV_X_MAJOR_MASK	(0x0F << 4)
- + #define	 RNG_REG_REV_Y_MINOR_MASK	(0x0F << 0)
- + 
- + #define	RNG_REG_SYSCFG			0x1FE4
- + #define	RNG_REG_SYSCFG_SIDLEMODE_MASK	(3 << 3)
- + #define	 RNG_REG_SYSCFG_SIDLEMODE_FORCE	(0 << 3)
- + #define	 RNG_REG_SYSCFG_SIDLEMODE_NO	(1 << 3)
- + #define	 RNG_REG_SYSCFG_SIDLEMODE_SMART	(2 << 3)
- + #define	RNG_REG_SYSCFG_AUTOIDLE		(1 << 0)
- + 
- + #define	RNG_REG_STATUS_SET		0x1FEC
- + #define	RNG_REG_STATUS_SET_SHUTDOWN_OFLO (1 << 1)
- + #define	RNG_REG_STATUS_SET_RDY		(1 << 0)
- + 
- + #define	RNG_REG_SOFT_RESET		0x1FF0
- + #define	RNG_REG_SOFTRESET		(1 << 0)
- + 
- + #define	RNG_REG_IRQ_EOI			0x1FF4
- + #define	RNG_REG_IRQ_EOI_PULSE_INT_CLEAR	(1 << 0)
- + 
- + #define	RNG_REG_IRQSTATUS		0x1FF8
- + #define	RNG_REG_IRQSTATUS_IRQ_EN	(1 << 0)
- + 
- + 
- + static void __iomem *rng_base;
- + static struct platform_device *rng_dev;
- + 
- + #define trng_read(reg)						\
- + ({								\
- + 	u32 __val;						\
- + 	__val = __raw_readl(rng_base + RNG_REG_##reg);		\
- + })
- + 
- + #define trng_write(val, reg)					\
- + ({								\
- + 	__raw_writel((val), rng_base + RNG_REG_##reg);		\
- + })
- + 
- + static int omap4_rng_data_read(struct hwrng *rng, void *buf, size_t max, bool wait)
- + {
- + 	int res, i;
- + 
- + 	for (i = 0; i < 20; i++) {
- + 		res = trng_read(STATUS) & RNG_REG_STATUS_RDY;
- + 		if (res || !wait)
- + 			break;
- + 		/* RNG produces data fast enough (2+ MBit/sec, even
- + 		 * during "rngtest" loads, that these delays don't
- + 		 * seem to trigger.  We *could* use the RNG IRQ, but
- + 		 * that'd be higher overhead ... so why bother?
- + 		 */
- + 		udelay(10);
- + 	}
- + 
- + 	/* If we have data waiting, collect it... */
- + 	if (res) {
- + 		*(u32 *)buf = trng_read(OUTPUT_L);
- + 		buf += sizeof(u32);
- + 		*(u32 *)buf = trng_read(OUTPUT_H);
- + 
- + 		trng_write(RNG_REG_INTACK_RDY, INTACK);
- + 
- + 		res = 2  * sizeof(u32);
- + 	}
- + 	return res;
- + }
- + 
- + static struct hwrng omap4_rng_ops = {
- + 	.name		= "omap4",
- + 	.read		= omap4_rng_data_read,
- + };
- + 
- + static int __devinit omap4_rng_probe(struct platform_device *pdev)
- + {
- + 	struct resource *res;
- + 	int ret;
- + 	u32 reg;
- + 
- + 	/*
- + 	 * A bit ugly, and it will never actually happen but there can
- + 	 * be only one RNG and this catches any bork
- + 	 */
- + 	if (rng_dev)
- + 		return -EBUSY;
- + 
- + 	pm_runtime_enable(&pdev->dev);
- + 	pm_runtime_get_sync(&pdev->dev);
- + 
- + 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- + 	if (!res) {
- + 		ret = -ENOENT;
- + 		goto err_region;
- + 	}
- + 
- + 	if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
- + 		ret = -EBUSY;
- + 		goto err_region;
- + 	}
- + 
- + 	dev_set_drvdata(&pdev->dev, res);
- + 	rng_base = ioremap(res->start, resource_size(res));
- + 	if (!rng_base) {
- + 		ret = -ENOMEM;
- + 		goto err_ioremap;
- + 	}
- + 
- + 	ret = hwrng_register(&omap4_rng_ops);
- + 	if (ret)
- + 		goto err_register;
- + 
- + 	reg = trng_read(REV);
- + 	dev_info(&pdev->dev, "OMAP4 Random Number Generator ver. %u.%02u\n",
- + 		 ((reg & RNG_REG_REV_X_MAJOR_MASK) >> 4),
- + 		 (reg & RNG_REG_REV_Y_MINOR_MASK));
- + 
- + 	rng_dev = pdev;
- + 
- + 	/* start TRNG if not running yet */
- + 	if (!(trng_read(CONTROL) & RNG_REG_CONTROL_ENABLE_TRNG)) {
- + 		trng_write(0x00220021, CONFIG);
- + 		trng_write(0x00210400, CONTROL);
- + 	}
- + 
- + 	return 0;
- + 
- + err_register:
- + 	iounmap(rng_base);
- + 	rng_base = NULL;
- + err_ioremap:
- + 	release_mem_region(res->start, resource_size(res));
- + err_region:
- + 	pm_runtime_put_sync(&pdev->dev);
- + 	pm_runtime_disable(&pdev->dev);
- + 	return ret;
- + }
- + 
- + static int __exit omap4_rng_remove(struct platform_device *pdev)
- + {
- + 	struct resource *res = dev_get_drvdata(&pdev->dev);
- + 
- + 	hwrng_unregister(&omap4_rng_ops);
- + 
- + 	trng_write(trng_read(CONTROL) & ~RNG_REG_CONTROL_ENABLE_TRNG, CONTROL);
- + 
- + 	iounmap(rng_base);
- + 
- + 	pm_runtime_put_sync(&pdev->dev);
- + 	pm_runtime_disable(&pdev->dev);
- + 	release_mem_region(res->start, resource_size(res));
- + 	rng_base = NULL;
- + 
- + 	return 0;
- + }
- + 
- + #ifdef CONFIG_PM
- + 
- + static int omap4_rng_suspend(struct platform_device *pdev, pm_message_t message)
- + {
- + 	trng_write(trng_read(CONTROL) & ~RNG_REG_CONTROL_ENABLE_TRNG, CONTROL);
- + 
- + 	pm_runtime_put_sync(&pdev->dev);
- + 
- + 	return 0;
- + }
- + 
- + static int omap4_rng_resume(struct platform_device *pdev)
- + {
- + 	pm_runtime_get_sync(&pdev->dev);
- + 
- + 	trng_write(trng_read(CONTROL) | RNG_REG_CONTROL_ENABLE_TRNG, CONTROL);
- + 
- + 	return 0;
- + }
- + 
- + #else
- + 
- + #define	omap4_rng_suspend	NULL
- + #define	omap4_rng_resume	NULL
- + 
- + #endif
- + 
- + /* work with hotplug and coldplug */
- + MODULE_ALIAS("platform:omap4_rng");
- + 
- + static struct platform_driver omap4_rng_driver = {
- + 	.driver = {
- + 		.name		= "omap4_rng",
- + 		.owner		= THIS_MODULE,
- + 	},
- + 	.probe		= omap4_rng_probe,
- + 	.remove		= __exit_p(omap4_rng_remove),
- + 	.suspend	= omap4_rng_suspend,
- + 	.resume		= omap4_rng_resume
- + };
- + 
- + static int __init omap4_rng_init(void)
- + {
- + 	if (!cpu_is_am33xx()  || omap_type() != OMAP2_DEVICE_TYPE_GP)
- + 		return -ENODEV;
- + 
- + 	return platform_driver_register(&omap4_rng_driver);
- + }
- + 
- + static void __exit omap4_rng_exit(void)
- + {
- + 	platform_driver_unregister(&omap4_rng_driver);
- + }
- + 
- + module_init(omap4_rng_init);
- + module_exit(omap4_rng_exit);
- + 
- + MODULE_LICENSE("GPL");
- + MODULE_DESCRIPTION("AM33X TRNG driver");
- diff -crN linux-3.2.1_o/drivers/char/random.c linux-3.2.1/drivers/char/random.c
- *** linux-3.2.1_o/drivers/char/random.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/char/random.c	2014-05-15 13:25:14.203788815 +0900
- ***************
- *** 130,135 ****
- --- 130,138 ----
-    * 	void add_interrupt_randomness(int irq);
-    * 	void add_disk_randomness(struct gendisk *disk);
-    *
- +  *      void random_input_words(__u32 *buf, size_t wordcount, int ent_count)
- +  *      int random_input_wait(void);
- +  *
-    * add_input_randomness() uses the input layer interrupt timing, as well as
-    * the event type information from the hardware.
-    *
- ***************
- *** 147,152 ****
- --- 150,162 ----
-    * seek times do not make for good sources of entropy, as their seek
-    * times are usually fairly consistent.
-    *
- +  * random_input_words() just provides a raw block of entropy to the input
- +  * pool, such as from a hardware entropy generator.
- +  *
- +  * random_input_wait() suspends the caller until such time as the
- +  * entropy pool falls below the write threshold, and returns a count of how
- +  * much entropy (in bits) is needed to sustain the pool.
- +  *
-    * All of these routines try to estimate how many bits of randomness a
-    * particular randomness source.  They do this by keeping track of the
-    * first and second order deltas of the event timings.
- ***************
- *** 722,727 ****
- --- 732,794 ----
-   }
-   #endif
-   
- + /*
- +  * random_input_words - add bulk entropy to pool
- +  *
- +  * @buf: buffer to add
- +  * @wordcount: number of __u32 words to add
- +  * @ent_count: total amount of entropy (in bits) to credit
- +  *
- +  * this provides bulk input of entropy to the input pool
- +  *
- +  */
- + void random_input_words(__u32 *buf, size_t wordcount, int ent_count)
- + {
- + 	mix_pool_bytes(&input_pool, buf, wordcount*4);
- + 
- + 	credit_entropy_bits(&input_pool, ent_count);
- + 
- + 	DEBUG_ENT("crediting %d bits => %d\n",
- + 		  ent_count, input_pool.entropy_count);
- + 	/*
- + 	 * Wake up waiting processes if we have enough
- + 	 * entropy.
- + 	 */
- + 	if (input_pool.entropy_count >= random_read_wakeup_thresh)
- + 		wake_up_interruptible(&random_read_wait);
- + }
- + EXPORT_SYMBOL(random_input_words);
- + 
- + /*
- +  * random_input_wait - wait until random needs entropy
- +  *
- +  * this function sleeps until the /dev/random subsystem actually
- +  * needs more entropy, and then return the amount of entropy
- +  * that it would be nice to have added to the system.
- +  */
- + int random_input_wait(void)
- + {
- + 	int count;
- + 
- + 	wait_event_interruptible(random_write_wait,
- + 			 input_pool.entropy_count < random_write_wakeup_thresh);
- + 
- + 	count = random_write_wakeup_thresh - input_pool.entropy_count;
- + 
- +         /* likely we got woken up due to a signal */
- + 	if (count <= 0) count = random_read_wakeup_thresh;
- + 
- + 	DEBUG_ENT("requesting %d bits from input_wait()er %d<%d\n",
- + 		  count,
- + 		  input_pool.entropy_count, random_write_wakeup_thresh);
- + 
- + 	return count;
- + }
- + EXPORT_SYMBOL(random_input_wait);
- + 
- + 
- + #define EXTRACT_SIZE 10
- + 
-   /*********************************************************************
-    *
-    * Entropy extraction routines
- diff -crN linux-3.2.1_o/drivers/cpufreq/cpufreq.c linux-3.2.1/drivers/cpufreq/cpufreq.c
- *** linux-3.2.1_o/drivers/cpufreq/cpufreq.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/cpufreq/cpufreq.c	2014-05-15 13:25:14.216231174 +0900
- ***************
- *** 204,211 ****
-   		pr_debug("saving %lu as reference value for loops_per_jiffy; "
-   			"freq is %u kHz\n", l_p_j_ref, l_p_j_ref_freq);
-   	}
- ! 	if ((val == CPUFREQ_PRECHANGE  && ci->old < ci->new) ||
- ! 	    (val == CPUFREQ_POSTCHANGE && ci->old > ci->new) ||
-   	    (val == CPUFREQ_RESUMECHANGE || val == CPUFREQ_SUSPENDCHANGE)) {
-   		loops_per_jiffy = cpufreq_scale(l_p_j_ref, l_p_j_ref_freq,
-   								ci->new);
- --- 204,210 ----
-   		pr_debug("saving %lu as reference value for loops_per_jiffy; "
-   			"freq is %u kHz\n", l_p_j_ref, l_p_j_ref_freq);
-   	}
- ! 	if ((val == CPUFREQ_POSTCHANGE  && ci->old != ci->new) ||
-   	    (val == CPUFREQ_RESUMECHANGE || val == CPUFREQ_SUSPENDCHANGE)) {
-   		loops_per_jiffy = cpufreq_scale(l_p_j_ref, l_p_j_ref_freq,
-   								ci->new);
- diff -crN linux-3.2.1_o/drivers/cpufreq/cpufreq_userspace.c linux-3.2.1/drivers/cpufreq/cpufreq_userspace.c
- *** linux-3.2.1_o/drivers/cpufreq/cpufreq_userspace.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/cpufreq/cpufreq_userspace.c	2014-05-15 13:25:14.248276562 +0900
- ***************
- *** 47,55 ****
-   	if (!per_cpu(cpu_is_managed, freq->cpu))
-   		return 0;
-   
- ! 	pr_debug("saving cpu_cur_freq of cpu %u to be %u kHz\n",
- ! 			freq->cpu, freq->new);
- ! 	per_cpu(cpu_cur_freq, freq->cpu) = freq->new;
-   
-   	return 0;
-   }
- --- 47,57 ----
-   	if (!per_cpu(cpu_is_managed, freq->cpu))
-   		return 0;
-   
- ! 	if (val == CPUFREQ_POSTCHANGE) {
- ! 		pr_debug("saving cpu_cur_freq of cpu %u to be %u kHz\n",
- ! 				freq->cpu, freq->new);
- ! 		per_cpu(cpu_cur_freq, freq->cpu) = freq->new;
- ! 	}
-   
-   	return 0;
-   }
- diff -crN linux-3.2.1_o/drivers/cpufreq/Makefile linux-3.2.1/drivers/cpufreq/Makefile
- *** linux-3.2.1_o/drivers/cpufreq/Makefile	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/cpufreq/Makefile	2014-05-15 13:25:14.251305260 +0900
- ***************
- *** 44,49 ****
- --- 44,51 ----
-   obj-$(CONFIG_ARM_S5PV210_CPUFREQ)	+= s5pv210-cpufreq.o
-   obj-$(CONFIG_ARM_EXYNOS4210_CPUFREQ)	+= exynos4210-cpufreq.o
-   
- + obj-$(CONFIG_ARCH_CKB)            += omap-cpufreq.o
- + 
-   ##################################################################################
-   # PowerPC platform drivers
-   obj-$(CONFIG_CPU_FREQ_MAPLE)		+= maple-cpufreq.o
- diff -crN linux-3.2.1_o/drivers/cpufreq/omap-cpufreq.c linux-3.2.1/drivers/cpufreq/omap-cpufreq.c
- *** linux-3.2.1_o/drivers/cpufreq/omap-cpufreq.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/drivers/cpufreq/omap-cpufreq.c	2014-05-15 13:25:14.256285367 +0900
- ***************
- *** 0 ****
- --- 1,412 ----
- + /*
- +  *  CPU frequency scaling for OMAP using OPP information
- +  *
- +  *  Copyright (C) 2005 Nokia Corporation
- +  *  Written by Tony Lindgren <tony@atomide.com>
- +  *
- +  *  Based on cpu-sa1110.c, Copyright (C) 2001 Russell King
- +  *
- +  * Copyright (C) 2007-2011 Texas Instruments, Inc.
- +  * - OMAP3/4 support by Rajendra Nayak, Santosh Shilimkar
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  */
- + #include <linux/types.h>
- + #include <linux/kernel.h>
- + #include <linux/sched.h>
- + #include <linux/cpufreq.h>
- + #include <linux/delay.h>
- + #include <linux/init.h>
- + #include <linux/err.h>
- + #include <linux/clk.h>
- + #include <linux/io.h>
- + #include <linux/opp.h>
- + #include <linux/cpu.h>
- + #include <linux/module.h>
- + #include <linux/regulator/consumer.h>
- + #include <linux/suspend.h>
- + 
- + #include <asm/system.h>
- + #include <asm/smp_plat.h>
- + #include <asm/cpu.h>
- + 
- + #include <plat/clock.h>
- + #include <plat/omap-pm.h>
- + #include <plat/common.h>
- + #include <plat/omap_device.h>
- + 
- + #include <mach/hardware.h>
- + 
- + /* Tolerance for MPU voltage is 4%, we have to pass +4% as a
- +  * maximum voltage while setting the MPU regulator voltage.
- +  * Which is taken from AM33XX datasheet */
- + #define MPU_TOLERANCE	4
- + #define PER_ROUND_VAL	100
- + 
- + /* Use 275MHz when entering suspend */
- + #define SLEEP_FREQ	(275 * 1000)
- + 
- + 
- + #ifdef CONFIG_SMP
- + struct lpj_info {
- + 	unsigned long	ref;
- + 	unsigned int	freq;
- + };
- + 
- + static DEFINE_PER_CPU(struct lpj_info, lpj_ref);
- + static struct lpj_info global_lpj_ref;
- + #endif
- + 
- + static struct cpufreq_frequency_table *freq_table;
- + static atomic_t freq_table_users = ATOMIC_INIT(0);
- + static struct clk *mpu_clk;
- + static char *mpu_clk_name;
- + static struct device *mpu_dev;
- + static struct regulator *mpu_reg;
- + static DEFINE_MUTEX(omap_cpu_lock);
- + static bool is_suspended;
- + 
- + static int omap_verify_speed(struct cpufreq_policy *policy)
- + {
- + 	if (!freq_table)
- + 		return -EINVAL;
- + 	return cpufreq_frequency_table_verify(policy, freq_table);
- + }
- + 
- + static unsigned int omap_getspeed(unsigned int cpu)
- + {
- + 	unsigned long rate;
- + 
- + 	if (cpu >= NR_CPUS)
- + 		return 0;
- + 
- + 	rate = clk_get_rate(mpu_clk) / 1000;
- + 	return rate;
- + }
- + 
- + static int omap_target(struct cpufreq_policy *policy,
- + 		       unsigned int target_freq,
- + 		       unsigned int relation)
- + {
- + 	unsigned int i;
- + 	int ret = 0;
- + 	struct cpufreq_freqs freqs;
- + 	struct opp *opp;
- + 	int volt_old = 0, volt_new = 0;
- + 
- + 	if (is_suspended)
- + 		return -EBUSY;
- + 
- + 	if (!freq_table) {
- + 		dev_err(mpu_dev, "%s: cpu%d: no freq table!\n", __func__,
- + 				policy->cpu);
- + 		return -EINVAL;
- + 	}
- + 
- + 	ret = cpufreq_frequency_table_target(policy, freq_table, target_freq,
- + 			relation, &i);
- + 	if (ret) {
- + 		dev_dbg(mpu_dev, "%s: cpu%d: no freq match for %d(ret=%d)\n",
- + 			__func__, policy->cpu, target_freq, ret);
- + 		return ret;
- + 	}
- + 	freqs.new = freq_table[i].frequency;
- + 	if (!freqs.new) {
- + 		dev_err(mpu_dev, "%s: cpu%d: no match for freq %d\n", __func__,
- + 			policy->cpu, target_freq);
- + 		return -EINVAL;
- + 	}
- + 
- + 	freqs.old = omap_getspeed(policy->cpu);
- + 	freqs.cpu = policy->cpu;
- + 
- + 	if (freqs.old == freqs.new && policy->cur == freqs.new)
- + 		return ret;
- + 
- + 	opp = opp_find_freq_exact(mpu_dev, freqs.new * 1000, true);
- + 	if (IS_ERR(opp)) {
- + 		dev_err(mpu_dev, "%s: cpu%d: no opp match for freq %d\n",
- + 			__func__, policy->cpu, target_freq);
- + 		return -EINVAL;
- + 	}
- + 
- + 	volt_new = opp_get_voltage(opp);
- + 	if (!volt_new) {
- + 		dev_err(mpu_dev, "%s: cpu%d: no opp voltage for freq %d\n",
- + 			__func__, policy->cpu, target_freq);
- + 		return -EINVAL;
- + 	}
- + 
- + 	volt_old = regulator_get_voltage(mpu_reg);
- + 
- + #ifdef CONFIG_CPU_FREQ_DEBUG
- + 	pr_info("cpufreq-omap: frequency transition: %u --> %u\n",
- + 			freqs.old, freqs.new);
- + 	pr_info("cpufreq-omap: voltage transition: %d --> %d\n",
- + 			volt_old, volt_new);
- + #endif
- + 
- + 	if (freqs.new > freqs.old) {
- + 		ret = regulator_set_voltage(mpu_reg, volt_new,
- + 			volt_new + (volt_new * MPU_TOLERANCE) / PER_ROUND_VAL);
- + 		if (ret) {
- + 			dev_err(mpu_dev, "%s: unable to set voltage to %d uV (for %u MHz)\n",
- + 				__func__, volt_new, freqs.new/1000);
- + 			return ret;
- + 		}
- + 	}
- + 
- + 	/* notifiers */
- + 	for_each_cpu(i, policy->cpus) {
- + 		freqs.cpu = i;
- + 		cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
- + 	}
- + 
- + 	ret = clk_set_rate(mpu_clk, freqs.new * 1000);
- + 	freqs.new = omap_getspeed(policy->cpu);
- + 
- + #ifdef CONFIG_SMP
- + 	/*
- + 	 * Note that loops_per_jiffy is not updated on SMP systems in
- + 	 * cpufreq driver. So, update the per-CPU loops_per_jiffy value
- + 	 * on frequency transition. We need to update all dependent CPUs.
- + 	 */
- + 	for_each_cpu(i, policy->cpus) {
- + 		struct lpj_info *lpj = &per_cpu(lpj_ref, i);
- + 		if (!lpj->freq) {
- + 			lpj->ref = per_cpu(cpu_data, i).loops_per_jiffy;
- + 			lpj->freq = freqs.old;
- + 		}
- + 
- + 		per_cpu(cpu_data, i).loops_per_jiffy =
- + 			cpufreq_scale(lpj->ref, lpj->freq, freqs.new);
- + 	}
- + 
- + 	/* And don't forget to adjust the global one */
- + 	if (!global_lpj_ref.freq) {
- + 		global_lpj_ref.ref = loops_per_jiffy;
- + 		global_lpj_ref.freq = freqs.old;
- + 	}
- + 	loops_per_jiffy = cpufreq_scale(global_lpj_ref.ref, global_lpj_ref.freq,
- + 					freqs.new);
- + #endif
- + 
- + 	/* notifiers */
- + 	for_each_cpu(i, policy->cpus) {
- + 		freqs.cpu = i;
- + 		cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
- + 	}
- + 
- + 	if (freqs.new < freqs.old) {
- + 		ret = regulator_set_voltage(mpu_reg, volt_new,
- + 			volt_new + (volt_new * MPU_TOLERANCE) / PER_ROUND_VAL);
- + 		if (ret) {
- + 			unsigned int temp;
- + 
- + 			dev_err(mpu_dev, "%s: unable to set voltage to %d uV (for %u MHz)\n",
- + 				__func__, volt_new, freqs.new/1000);
- + 
- + 			if (clk_set_rate(mpu_clk, freqs.old * 1000)) {
- + 				dev_err(mpu_dev,
- + 					"%s: failed restoring clock rate to %u MHz, clock rate is %u MHz",
- + 					__func__,
- + 					freqs.old/1000, freqs.new/1000);
- + 				return ret;
- + 			}
- + 
- + 			temp = freqs.new;
- + 			freqs.new = freqs.old;
- + 			freqs.old = temp;
- + 
- + 			for_each_cpu(i, policy->cpus) {
- + 				freqs.cpu = i;
- + 				cpufreq_notify_transition(&freqs,
- + 					CPUFREQ_PRECHANGE);
- + 				cpufreq_notify_transition(&freqs,
- + 					CPUFREQ_POSTCHANGE);
- + 			}
- + 			return ret;
- + 		}
- + 	}
- + 
- + 	return ret;
- + }
- + 
- + static inline void freq_table_free(void)
- + {
- + 	if (atomic_dec_and_test(&freq_table_users))
- + 		opp_free_cpufreq_table(mpu_dev, &freq_table);
- + }
- + 
- + static int omap_pm_notify(struct notifier_block *nb, unsigned long event,
- +                                 void *dummy)
- + {
- + 	struct cpufreq_policy *policy = cpufreq_cpu_get(0);
- + 	static unsigned int saved_frequency;
- + 
- + 	mutex_lock(&omap_cpu_lock);
- + 	switch (event) {
- + 	case PM_SUSPEND_PREPARE:
- + 		if (is_suspended)
- + 			goto out;
- + 
- +                 saved_frequency = omap_getspeed(0);
- + 
- +                 mutex_unlock(&omap_cpu_lock);
- + 		omap_target(policy, SLEEP_FREQ, CPUFREQ_RELATION_H);
- + 		mutex_lock(&omap_cpu_lock);
- + 		is_suspended = true;
- +                 break;
- + 
- +         case PM_POST_SUSPEND:
- +                 is_suspended = false;
- +                 mutex_unlock(&omap_cpu_lock);
- + 		omap_target(policy, saved_frequency, CPUFREQ_RELATION_H);
- + 		mutex_lock(&omap_cpu_lock);
- +                 break;
- + 	}
- + out:
- + 	mutex_unlock(&omap_cpu_lock);
- + 
- + 	return NOTIFY_OK;
- + }
- + 
- + static struct notifier_block omap_cpu_pm_notifier = {
- + 	.notifier_call = omap_pm_notify,
- + };
- + 
- + static int __cpuinit omap_cpu_init(struct cpufreq_policy *policy)
- + {
- + 	int result = 0;
- + 
- + 	mpu_clk = clk_get(NULL, mpu_clk_name);
- + 	if (IS_ERR(mpu_clk))
- + 		return PTR_ERR(mpu_clk);
- + 
- + 	mpu_reg = regulator_get(NULL, "vdd_mpu");
- + 	if (IS_ERR(mpu_reg)) {
- + 		result = -EINVAL;
- + 		goto fail_ck;
- + 	}
- + 
- + 	/* success of regulator_get doesn't gurantee presence of driver for
- + 	   physical regulator and presence of physical regulator (this
- + 	   situation arises if dummy regulator is enabled),so check voltage
- + 	   to verify that physical regulator and it's driver is present
- + 	 */
- + 	if (regulator_get_voltage(mpu_reg) < 0) {
- + 		result = -EINVAL;
- + 		goto fail_reg;
- + 	}
- + 
- + 	if (policy->cpu >= NR_CPUS) {
- + 		result = -EINVAL;
- + 		goto fail_reg;
- + 	}
- + 
- + 	policy->cur = policy->min = policy->max = omap_getspeed(policy->cpu);
- + 
- + 	if (atomic_inc_return(&freq_table_users) == 1)
- + 		result = opp_init_cpufreq_table(mpu_dev, &freq_table);
- + 
- + 	if (result) {
- + 		dev_err(mpu_dev, "%s: cpu%d: failed creating freq table[%d]\n",
- + 				__func__, policy->cpu, result);
- + 		goto fail_reg;
- + 	}
- + 
- + 	result = cpufreq_frequency_table_cpuinfo(policy, freq_table);
- + 	if (result)
- + 		goto fail_table;
- + 
- + 	cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
- + 
- + 	policy->min = policy->cpuinfo.min_freq;
- + 	policy->max = policy->cpuinfo.max_freq;
- + 	policy->cur = omap_getspeed(policy->cpu);
- + 
- + 	/*
- + 	 * On OMAP SMP configuartion, both processors share the voltage
- + 	 * and clock. So both CPUs needs to be scaled together and hence
- + 	 * needs software co-ordination. Use cpufreq affected_cpus
- + 	 * interface to handle this scenario. Additional is_smp() check
- + 	 * is to keep SMP_ON_UP build working.
- + 	 */
- + 	if (is_smp()) {
- + 		policy->shared_type = CPUFREQ_SHARED_TYPE_ANY;
- + 		cpumask_setall(policy->cpus);
- + 	}
- + 
- + 	/* FIXME: what's the actual transition time? */
- + 	policy->cpuinfo.transition_latency = 300 * 1000;
- + 
- + 	register_pm_notifier(&omap_cpu_pm_notifier);
- + 
- + 	return 0;
- + 
- + fail_table:
- + 	freq_table_free();
- + fail_reg:
- + 	regulator_put(mpu_reg);
- + fail_ck:
- + 	clk_put(mpu_clk);
- + 	return result;
- + }
- + 
- + static int omap_cpu_exit(struct cpufreq_policy *policy)
- + {
- + 	freq_table_free();
- + 	clk_put(mpu_clk);
- + 	return 0;
- + }
- + 
- + static struct freq_attr *omap_cpufreq_attr[] = {
- + 	&cpufreq_freq_attr_scaling_available_freqs,
- + 	NULL,
- + };
- + 
- + static struct cpufreq_driver omap_driver = {
- + 	.flags		= CPUFREQ_STICKY,
- + 	.verify		= omap_verify_speed,
- + 	.target		= omap_target,
- + 	.get		= omap_getspeed,
- + 	.init		= omap_cpu_init,
- + 	.exit		= omap_cpu_exit,
- + 	.name		= "omap",
- + 	.attr		= omap_cpufreq_attr,
- + };
- + 
- + static int __init omap_cpufreq_init(void)
- + {
- + 	if (cpu_is_omap24xx())
- + 		mpu_clk_name = "virt_prcm_set";
- + 	else if (cpu_is_omap34xx() && !cpu_is_am33xx())
- + 		mpu_clk_name = "dpll1_ck";
- + 	else if (cpu_is_omap44xx() || cpu_is_am33xx())
- + 		mpu_clk_name = "dpll_mpu_ck";
- + 
- + 	if (!mpu_clk_name) {
- + 		pr_err("%s: unsupported Silicon?\n", __func__);
- + 		return -EINVAL;
- + 	}
- + 
- + 	mpu_dev = omap_device_get_by_hwmod_name("mpu");
- + 	if (!mpu_dev) {
- + 		pr_warning("%s: unable to get the mpu device\n", __func__);
- + 		return -EINVAL;
- + 	}
- + 
- + 	return cpufreq_register_driver(&omap_driver);
- + }
- + 
- + static void __exit omap_cpufreq_exit(void)
- + {
- + 	cpufreq_unregister_driver(&omap_driver);
- + }
- + 
- + MODULE_DESCRIPTION("cpufreq driver for OMAP SoCs");
- + MODULE_LICENSE("GPL");
- + module_init(omap_cpufreq_init);
- + module_exit(omap_cpufreq_exit);
- diff -crN linux-3.2.1_o/drivers/gpio/gpio-omap.c linux-3.2.1/drivers/gpio/gpio-omap.c
- *** linux-3.2.1_o/drivers/gpio/gpio-omap.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/gpio/gpio-omap.c	2014-05-15 13:25:14.283268081 +0900
- ***************
- *** 35,41 ****
-   	u16 virtual_irq_start;
-   	int method;
-   	u32 suspend_wakeup;
- ! #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
-   	u32 saved_wakeup;
-   #endif
-   	u32 non_wakeup_gpios;
- --- 35,41 ----
-   	u16 virtual_irq_start;
-   	int method;
-   	u32 suspend_wakeup;
- ! #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_ARCH_CKB)
-   	u32 saved_wakeup;
-   #endif
-   	u32 non_wakeup_gpios;
- ***************
- *** 61,67 ****
-   	struct omap_gpio_reg_offs *regs;
-   };
-   
- ! #ifdef CONFIG_ARCH_OMAP3
-   struct omap3_gpio_regs {
-   	u32 irqenable1;
-   	u32 irqenable2;
- --- 61,67 ----
-   	struct omap_gpio_reg_offs *regs;
-   };
-   
- ! #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_CKB)
-   struct omap3_gpio_regs {
-   	u32 irqenable1;
-   	u32 irqenable2;
- ***************
- *** 206,219 ****
-   	__raw_writel(val, reg);
-   }
-   
- ! #ifdef CONFIG_ARCH_OMAP2PLUS
-   static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
-   						int trigger)
-   {
-   	void __iomem *base = bank->base;
-   	u32 gpio_bit = 1 << gpio;
-   
- ! 	if (cpu_is_omap44xx()) {
-   		_gpio_rmw(base, OMAP4_GPIO_LEVELDETECT0, gpio_bit,
-   			  trigger & IRQ_TYPE_LEVEL_LOW);
-   		_gpio_rmw(base, OMAP4_GPIO_LEVELDETECT1, gpio_bit,
- --- 206,219 ----
-   	__raw_writel(val, reg);
-   }
-   
- ! #if defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_ARCH_CKB)
-   static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
-   						int trigger)
-   {
-   	void __iomem *base = bank->base;
-   	u32 gpio_bit = 1 << gpio;
-   
- ! 	if (cpu_is_omap44xx() || cpu_is_am33xx()) {
-   		_gpio_rmw(base, OMAP4_GPIO_LEVELDETECT0, gpio_bit,
-   			  trigger & IRQ_TYPE_LEVEL_LOW);
-   		_gpio_rmw(base, OMAP4_GPIO_LEVELDETECT1, gpio_bit,
- ***************
- *** 233,239 ****
-   			  trigger & IRQ_TYPE_EDGE_FALLING);
-   	}
-   	if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
- ! 		if (cpu_is_omap44xx()) {
-   			_gpio_rmw(base, OMAP4_GPIO_IRQWAKEN0, gpio_bit,
-   				  trigger != 0);
-   		} else {
- --- 233,239 ----
-   			  trigger & IRQ_TYPE_EDGE_FALLING);
-   	}
-   	if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
- ! 		if (cpu_is_omap44xx() || cpu_is_am33xx()) {
-   			_gpio_rmw(base, OMAP4_GPIO_IRQWAKEN0, gpio_bit,
-   				  trigger != 0);
-   		} else {
- ***************
- *** 264,270 ****
-   			bank->enabled_non_wakeup_gpios &= ~gpio_bit;
-   	}
-   
- ! 	if (cpu_is_omap44xx()) {
-   		bank->level_mask =
-   			__raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
-   			__raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
- --- 264,270 ----
-   			bank->enabled_non_wakeup_gpios &= ~gpio_bit;
-   	}
-   
- ! 	if (cpu_is_omap44xx() || cpu_is_am33xx()) {
-   		bank->level_mask =
-   			__raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
-   			__raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
- ***************
- *** 382,388 ****
-   			goto bad;
-   		break;
-   #endif
- ! #ifdef CONFIG_ARCH_OMAP2PLUS
-   	case METHOD_GPIO_24XX:
-   	case METHOD_GPIO_44XX:
-   		set_24xx_gpio_triggering(bank, gpio, trigger);
- --- 382,388 ----
-   			goto bad;
-   		break;
-   #endif
- ! #if defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_ARCH_CKB)
-   	case METHOD_GPIO_24XX:
-   	case METHOD_GPIO_44XX:
-   		set_24xx_gpio_triggering(bank, gpio, trigger);
- ***************
- *** 588,597 ****
-   			void __iomem *reg = bank->base;
-   			u32 ctrl;
-   
- ! 			if (cpu_is_omap24xx() || cpu_is_omap34xx())
- ! 				reg += OMAP24XX_GPIO_CTRL;
- ! 			else if (cpu_is_omap44xx())
-   				reg += OMAP4_GPIO_CTRL;
-   			ctrl = __raw_readl(reg);
-   			/* Module is enabled, clocks are not gated */
-   			ctrl &= 0xFFFFFFFE;
- --- 588,597 ----
-   			void __iomem *reg = bank->base;
-   			u32 ctrl;
-   
- ! 			if (cpu_is_omap44xx() || cpu_is_am33xx())
-   				reg += OMAP4_GPIO_CTRL;
- + 			else if (cpu_is_omap24xx() || cpu_is_omap34xx())
- + 				reg += OMAP24XX_GPIO_CTRL;
-   			ctrl = __raw_readl(reg);
-   			/* Module is enabled, clocks are not gated */
-   			ctrl &= 0xFFFFFFFE;
- ***************
- *** 617,630 ****
-   		__raw_writel(1 << offset, reg);
-   	}
-   #endif
- ! #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-   	if (bank->method == METHOD_GPIO_24XX) {
-   		/* Disable wake-up during idle for dynamic tick */
-   		void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
-   		__raw_writel(1 << offset, reg);
-   	}
-   #endif
- ! #ifdef CONFIG_ARCH_OMAP4
-   	if (bank->method == METHOD_GPIO_44XX) {
-   		/* Disable wake-up during idle for dynamic tick */
-   		void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
- --- 617,630 ----
-   		__raw_writel(1 << offset, reg);
-   	}
-   #endif
- ! #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_CKB)
-   	if (bank->method == METHOD_GPIO_24XX) {
-   		/* Disable wake-up during idle for dynamic tick */
-   		void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
-   		__raw_writel(1 << offset, reg);
-   	}
-   #endif
- ! #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAPAM33XX) || defined(CONFIG_ARCH_CKB)
-   	if (bank->method == METHOD_GPIO_44XX) {
-   		/* Disable wake-up during idle for dynamic tick */
-   		void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
- ***************
- *** 637,646 ****
-   			void __iomem *reg = bank->base;
-   			u32 ctrl;
-   
- ! 			if (cpu_is_omap24xx() || cpu_is_omap34xx())
- ! 				reg += OMAP24XX_GPIO_CTRL;
- ! 			else if (cpu_is_omap44xx())
-   				reg += OMAP4_GPIO_CTRL;
-   			ctrl = __raw_readl(reg);
-   			/* Module is disabled, clocks are gated */
-   			ctrl |= 1;
- --- 637,646 ----
-   			void __iomem *reg = bank->base;
-   			u32 ctrl;
-   
- ! 			if (cpu_is_omap44xx() || cpu_is_am33xx())
-   				reg += OMAP4_GPIO_CTRL;
- + 			else if (cpu_is_omap24xx() || cpu_is_omap34xx())
- + 				reg += OMAP24XX_GPIO_CTRL;
-   			ctrl = __raw_readl(reg);
-   			/* Module is disabled, clocks are gated */
-   			ctrl |= 1;
- ***************
- *** 1023,1029 ****
-   static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
-   {
-   	if (cpu_class_is_omap2()) {
- ! 		if (cpu_is_omap44xx()) {
-   			__raw_writel(0xffffffff, bank->base +
-   					OMAP4_GPIO_IRQSTATUSCLR0);
-   			__raw_writel(0x00000000, bank->base +
- --- 1023,1029 ----
-   static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
-   {
-   	if (cpu_class_is_omap2()) {
- ! 		if (cpu_is_omap44xx() || cpu_is_am33xx()) {
-   			__raw_writel(0xffffffff, bank->base +
-   					OMAP4_GPIO_IRQSTATUSCLR0);
-   			__raw_writel(0x00000000, bank->base +
- ***************
- *** 1232,1238 ****
-   	return 0;
-   }
-   
- ! #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
-   static int omap_gpio_suspend(void)
-   {
-   	int i;
- --- 1232,1238 ----
-   	return 0;
-   }
-   
- ! #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_ARCH_CKB)
-   static int omap_gpio_suspend(void)
-   {
-   	int i;
- ***************
- *** 1255,1268 ****
-   			wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
-   			break;
-   #endif
- ! #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-   		case METHOD_GPIO_24XX:
-   			wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
-   			wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
-   			wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
-   			break;
-   #endif
- ! #ifdef CONFIG_ARCH_OMAP4
-   		case METHOD_GPIO_44XX:
-   			wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
-   			wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
- --- 1255,1268 ----
-   			wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
-   			break;
-   #endif
- ! #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_CKB)
-   		case METHOD_GPIO_24XX:
-   			wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
-   			wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
-   			wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
-   			break;
-   #endif
- ! #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAPAM33XX) || defined(CONFIG_ARCH_CKB)
-   		case METHOD_GPIO_44XX:
-   			wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
-   			wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
- ***************
- *** 1303,1315 ****
-   			wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
-   			break;
-   #endif
- ! #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-   		case METHOD_GPIO_24XX:
-   			wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
-   			wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
-   			break;
-   #endif
- ! #ifdef CONFIG_ARCH_OMAP4
-   		case METHOD_GPIO_44XX:
-   			wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
-   			wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
- --- 1303,1315 ----
-   			wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
-   			break;
-   #endif
- ! #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_CKB)
-   		case METHOD_GPIO_24XX:
-   			wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
-   			wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
-   			break;
-   #endif
- ! #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAPAM33XX) || defined(CONFIG_ARCH_CKB)
-   		case METHOD_GPIO_44XX:
-   			wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
-   			wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
- ***************
- *** 1333,1339 ****
-   
-   #endif
-   
- ! #ifdef CONFIG_ARCH_OMAP2PLUS
-   
-   static int workaround_enabled;
-   
- --- 1333,1339 ----
-   
-   #endif
-   
- ! #if defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_ARCH_CKB)
-   
-   static int workaround_enabled;
-   
- ***************
- *** 1342,1348 ****
-   	int i, c = 0;
-   	int min = 0;
-   
- ! 	if (cpu_is_omap34xx())
-   		min = 1;
-   
-   	for (i = min; i < gpio_bank_count; i++) {
- --- 1342,1348 ----
-   	int i, c = 0;
-   	int min = 0;
-   
- ! 	if ((cpu_is_omap34xx() && !cpu_is_am33xx()))
-   		min = 1;
-   
-   	for (i = min; i < gpio_bank_count; i++) {
- ***************
- *** 1362,1368 ****
-   		if (!(bank->enabled_non_wakeup_gpios))
-   			continue;
-   
- ! 		if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
-   			bank->saved_datain = __raw_readl(bank->base +
-   					OMAP24XX_GPIO_DATAIN);
-   			l1 = __raw_readl(bank->base +
- --- 1362,1369 ----
-   		if (!(bank->enabled_non_wakeup_gpios))
-   			continue;
-   
- ! 		if (cpu_is_omap24xx() || (cpu_is_omap34xx() &&
- ! 							!cpu_is_am33xx())) {
-   			bank->saved_datain = __raw_readl(bank->base +
-   					OMAP24XX_GPIO_DATAIN);
-   			l1 = __raw_readl(bank->base +
- ***************
- *** 1371,1377 ****
-   					OMAP24XX_GPIO_RISINGDETECT);
-   		}
-   
- ! 		if (cpu_is_omap44xx()) {
-   			bank->saved_datain = __raw_readl(bank->base +
-   						OMAP4_GPIO_DATAIN);
-   			l1 = __raw_readl(bank->base +
- --- 1372,1378 ----
-   					OMAP24XX_GPIO_RISINGDETECT);
-   		}
-   
- ! 		if (cpu_is_omap44xx() || cpu_is_am33xx()) {
-   			bank->saved_datain = __raw_readl(bank->base +
-   						OMAP4_GPIO_DATAIN);
-   			l1 = __raw_readl(bank->base +
- ***************
- *** 1385,1398 ****
-   		l1 &= ~bank->enabled_non_wakeup_gpios;
-   		l2 &= ~bank->enabled_non_wakeup_gpios;
-   
- ! 		if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
-   			__raw_writel(l1, bank->base +
-   					OMAP24XX_GPIO_FALLINGDETECT);
-   			__raw_writel(l2, bank->base +
-   					OMAP24XX_GPIO_RISINGDETECT);
-   		}
-   
- ! 		if (cpu_is_omap44xx()) {
-   			__raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
-   			__raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
-   		}
- --- 1386,1400 ----
-   		l1 &= ~bank->enabled_non_wakeup_gpios;
-   		l2 &= ~bank->enabled_non_wakeup_gpios;
-   
- ! 		if (cpu_is_omap24xx() || (cpu_is_omap34xx() &&
- ! 							!cpu_is_am33xx())) {
-   			__raw_writel(l1, bank->base +
-   					OMAP24XX_GPIO_FALLINGDETECT);
-   			__raw_writel(l2, bank->base +
-   					OMAP24XX_GPIO_RISINGDETECT);
-   		}
-   
- ! 		if (cpu_is_omap44xx() || cpu_is_am33xx()) {
-   			__raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
-   			__raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
-   		}
- ***************
- *** 1411,1417 ****
-   	int i;
-   	int min = 0;
-   
- ! 	if (cpu_is_omap34xx())
-   		min = 1;
-   	for (i = min; i < gpio_bank_count; i++) {
-   		struct gpio_bank *bank = &gpio_bank[i];
- --- 1413,1419 ----
-   	int i;
-   	int min = 0;
-   
- ! 	if ((cpu_is_omap34xx() && !cpu_is_am33xx()))
-   		min = 1;
-   	for (i = min; i < gpio_bank_count; i++) {
-   		struct gpio_bank *bank = &gpio_bank[i];
- ***************
- *** 1427,1433 ****
-   		if (!(bank->enabled_non_wakeup_gpios))
-   			continue;
-   
- ! 		if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
-   			__raw_writel(bank->saved_fallingdetect,
-   				 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
-   			__raw_writel(bank->saved_risingdetect,
- --- 1429,1436 ----
-   		if (!(bank->enabled_non_wakeup_gpios))
-   			continue;
-   
- ! 		if (cpu_is_omap24xx() || (cpu_is_omap34xx() &&
- ! 							!cpu_is_am33xx())) {
-   			__raw_writel(bank->saved_fallingdetect,
-   				 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
-   			__raw_writel(bank->saved_risingdetect,
- ***************
- *** 1435,1441 ****
-   			l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
-   		}
-   
- ! 		if (cpu_is_omap44xx()) {
-   			__raw_writel(bank->saved_fallingdetect,
-   				 bank->base + OMAP4_GPIO_FALLINGDETECT);
-   			__raw_writel(bank->saved_risingdetect,
- --- 1438,1444 ----
-   			l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
-   		}
-   
- ! 		if (cpu_is_omap44xx() || cpu_is_am33xx()) {
-   			__raw_writel(bank->saved_fallingdetect,
-   				 bank->base + OMAP4_GPIO_FALLINGDETECT);
-   			__raw_writel(bank->saved_risingdetect,
- ***************
- *** 1469,1475 ****
-   		if (gen) {
-   			u32 old0, old1;
-   
- ! 			if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
-   				old0 = __raw_readl(bank->base +
-   					OMAP24XX_GPIO_LEVELDETECT0);
-   				old1 = __raw_readl(bank->base +
- --- 1472,1479 ----
-   		if (gen) {
-   			u32 old0, old1;
-   
- ! 			if (cpu_is_omap24xx() || (cpu_is_omap34xx() &&
- ! 							!cpu_is_am33xx())) {
-   				old0 = __raw_readl(bank->base +
-   					OMAP24XX_GPIO_LEVELDETECT0);
-   				old1 = __raw_readl(bank->base +
- ***************
- *** 1484,1490 ****
-   					OMAP24XX_GPIO_LEVELDETECT1);
-   			}
-   
- ! 			if (cpu_is_omap44xx()) {
-   				old0 = __raw_readl(bank->base +
-   						OMAP4_GPIO_LEVELDETECT0);
-   				old1 = __raw_readl(bank->base +
- --- 1488,1494 ----
-   					OMAP24XX_GPIO_LEVELDETECT1);
-   			}
-   
- ! 			if (cpu_is_omap44xx() || cpu_is_am33xx()) {
-   				old0 = __raw_readl(bank->base +
-   						OMAP4_GPIO_LEVELDETECT0);
-   				old1 = __raw_readl(bank->base +
- ***************
- *** 1505,1511 ****
-   
-   #endif
-   
- ! #ifdef CONFIG_ARCH_OMAP3
-   /* save the registers of bank 2-6 */
-   void omap_gpio_save_context(void)
-   {
- --- 1509,1515 ----
-   
-   #endif
-   
- ! #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_CKB)
-   /* save the registers of bank 2-6 */
-   void omap_gpio_save_context(void)
-   {
- ***************
- *** 1590,1596 ****
-   {
-   	mpuio_init();
-   
- ! #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
-   	if (cpu_is_omap16xx() || cpu_class_is_omap2())
-   		register_syscore_ops(&omap_gpio_syscore_ops);
-   #endif
- --- 1594,1600 ----
-   {
-   	mpuio_init();
-   
- ! #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_ARCH_CKB)
-   	if (cpu_is_omap16xx() || cpu_class_is_omap2())
-   		register_syscore_ops(&omap_gpio_syscore_ops);
-   #endif
- diff -crN linux-3.2.1_o/drivers/gpio/Makefile linux-3.2.1/drivers/gpio/Makefile
- *** linux-3.2.1_o/drivers/gpio/Makefile	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/gpio/Makefile	2014-05-15 13:25:14.286544821 +0900
- ***************
- *** 36,41 ****
- --- 36,42 ----
-   obj-$(CONFIG_GPIO_MXS)		+= gpio-mxs.o
-   obj-$(CONFIG_PLAT_NOMADIK)	+= gpio-nomadik.o
-   obj-$(CONFIG_ARCH_OMAP)		+= gpio-omap.o
- + obj-$(CONFIG_ARCH_CKB)		+= gpio-omap.o
-   obj-$(CONFIG_GPIO_PCA953X)	+= gpio-pca953x.o
-   obj-$(CONFIG_GPIO_PCF857X)	+= gpio-pcf857x.o
-   obj-$(CONFIG_GPIO_PCH)		+= gpio-pch.o
- diff -crN linux-3.2.1_o/drivers/hv/vmbus_drv.c linux-3.2.1/drivers/hv/vmbus_drv.c
- *** linux-3.2.1_o/drivers/hv/vmbus_drv.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/hv/vmbus_drv.c	2014-05-15 13:25:14.295697591 +0900
- ***************
- *** 62,75 ****
-   	struct hv_dev_port_info outbound;
-   };
-   
- - static int vmbus_exists(void)
- - {
- - 	if (hv_acpi_dev == NULL)
- - 		return -ENODEV;
- - 
- - 	return 0;
- - }
- - 
-   
-   static void get_channel_info(struct hv_device *device,
-   			     struct hv_device_info *info)
- --- 62,67 ----
- ***************
- *** 598,607 ****
-   
-   	pr_info("registering driver %s\n", hv_driver->name);
-   
- - 	ret = vmbus_exists();
- - 	if (ret < 0)
- - 		return ret;
- - 
-   	hv_driver->driver.name = hv_driver->name;
-   	hv_driver->driver.owner = owner;
-   	hv_driver->driver.mod_name = mod_name;
- --- 590,595 ----
- ***************
- *** 626,633 ****
-   {
-   	pr_info("unregistering driver %s\n", hv_driver->name);
-   
- ! 	if (!vmbus_exists())
- ! 		driver_unregister(&hv_driver->driver);
-   }
-   EXPORT_SYMBOL_GPL(vmbus_driver_unregister);
-   
- --- 614,621 ----
-   {
-   	pr_info("unregistering driver %s\n", hv_driver->name);
-   
- ! 	driver_unregister(&hv_driver->driver);
- ! 
-   }
-   EXPORT_SYMBOL_GPL(vmbus_driver_unregister);
-   
- ***************
- *** 788,794 ****
-   
-   cleanup:
-   	acpi_bus_unregister_driver(&vmbus_acpi_driver);
- - 	hv_acpi_dev = NULL;
-   	return ret;
-   }
-   
- --- 776,781 ----
- diff -crN linux-3.2.1_o/drivers/i2c/busses/i2c-omap.c linux-3.2.1/drivers/i2c/busses/i2c-omap.c
- *** linux-3.2.1_o/drivers/i2c/busses/i2c-omap.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/i2c/busses/i2c-omap.c	2014-05-15 13:25:14.316376591 +0900
- ***************
- *** 235,241 ****
-   	[OMAP_I2C_BUF_REG] = 0x94,
-   	[OMAP_I2C_CNT_REG] = 0x98,
-   	[OMAP_I2C_DATA_REG] = 0x9c,
- ! 	[OMAP_I2C_SYSC_REG] = 0x20,
-   	[OMAP_I2C_CON_REG] = 0xa4,
-   	[OMAP_I2C_OA_REG] = 0xa8,
-   	[OMAP_I2C_SA_REG] = 0xac,
- --- 235,241 ----
-   	[OMAP_I2C_BUF_REG] = 0x94,
-   	[OMAP_I2C_CNT_REG] = 0x98,
-   	[OMAP_I2C_DATA_REG] = 0x9c,
- ! 	[OMAP_I2C_SYSC_REG] = 0x10,
-   	[OMAP_I2C_CON_REG] = 0xa4,
-   	[OMAP_I2C_OA_REG] = 0xa8,
-   	[OMAP_I2C_SA_REG] = 0xac,
- ***************
- *** 498,503 ****
- --- 498,504 ----
-    */
-   static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
-   {
- + #if 1 //Change this to 1 while testing Suspend
-   	unsigned long timeout;
-   
-   	timeout = jiffies + OMAP_I2C_TIMEOUT;
- ***************
- *** 508,514 ****
-   		}
-   		msleep(1);
-   	}
- ! 
-   	return 0;
-   }
-   
- --- 509,517 ----
-   		}
-   		msleep(1);
-   	}
- ! #else
- ! 	msleep(5);
- ! #endif
-   	return 0;
-   }
-   
- ***************
- *** 830,840 ****
-   				~(OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
-   				OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
-   
- ! 		if (stat & OMAP_I2C_STAT_NACK) {
-   			err |= OMAP_I2C_STAT_NACK;
- ! 			omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
- ! 					   OMAP_I2C_CON_STP);
- ! 		}
-   		if (stat & OMAP_I2C_STAT_AL) {
-   			dev_err(dev->dev, "Arbitration lost\n");
-   			err |= OMAP_I2C_STAT_AL;
- --- 833,841 ----
-   				~(OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
-   				OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
-   
- ! 		if (stat & OMAP_I2C_STAT_NACK)
-   			err |= OMAP_I2C_STAT_NACK;
- ! 
-   		if (stat & OMAP_I2C_STAT_AL) {
-   			dev_err(dev->dev, "Arbitration lost\n");
-   			err |= OMAP_I2C_STAT_AL;
- ***************
- *** 1066,1072 ****
-   
-   	isr = (dev->rev < OMAP_I2C_OMAP1_REV_2) ? omap_i2c_omap1_isr :
-   								   omap_i2c_isr;
- ! 	r = request_irq(dev->irq, isr, 0, pdev->name, dev);
-   
-   	if (r) {
-   		dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
- --- 1067,1073 ----
-   
-   	isr = (dev->rev < OMAP_I2C_OMAP1_REV_2) ? omap_i2c_omap1_isr :
-   								   omap_i2c_isr;
- ! 	r = request_irq(dev->irq, isr, IRQF_NO_SUSPEND, pdev->name, dev);
-   
-   	if (r) {
-   		dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
- diff -crN linux-3.2.1_o/drivers/i2c/busses/Kconfig linux-3.2.1/drivers/i2c/busses/Kconfig
- *** linux-3.2.1_o/drivers/i2c/busses/Kconfig	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/i2c/busses/Kconfig	2014-05-15 13:25:14.356262009 +0900
- ***************
- *** 501,507 ****
-   
-   config I2C_OMAP
-   	tristate "OMAP I2C adapter"
- ! 	depends on ARCH_OMAP
-   	default y if MACH_OMAP_H3 || MACH_OMAP_OSK
-   	help
-   	  If you say yes to this option, support will be included for the
- --- 501,507 ----
-   
-   config I2C_OMAP
-   	tristate "OMAP I2C adapter"
- ! 	depends on ARCH_OMAP || ARCH_CKB
-   	default y if MACH_OMAP_H3 || MACH_OMAP_OSK
-   	help
-   	  If you say yes to this option, support will be included for the
- diff -crN linux-3.2.1_o/drivers/Kconfig linux-3.2.1/drivers/Kconfig
- *** linux-3.2.1_o/drivers/Kconfig	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/Kconfig	2014-05-15 13:25:14.372288232 +0900
- ***************
- *** 60,65 ****
- --- 60,67 ----
-   
-   source "drivers/gpio/Kconfig"
-   
- + source "drivers/pwm/Kconfig"
- + 
-   source "drivers/w1/Kconfig"
-   
-   source "drivers/power/Kconfig"
- diff -crN linux-3.2.1_o/drivers/media/video/uvc/uvc_driver.c linux-3.2.1/drivers/media/video/uvc/uvc_driver.c
- *** linux-3.2.1_o/drivers/media/video/uvc/uvc_driver.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/media/video/uvc/uvc_driver.c	2014-07-22 09:32:14.237711000 +0900
- ***************
- *** 2374,2379 ****
- --- 2374,2401 ----
-   	  .bInterfaceProtocol	= 0,
-   	  .driver_info		= UVC_QUIRK_PROBE_MINMAX
-   				| UVC_QUIRK_IGNORE_SELECTOR_UNIT },
- + 	/* iBUFFALO */
- + 	{ .match_flags		= USB_DEVICE_ID_MATCH_DEVICE
- + 				| USB_DEVICE_ID_MATCH_INT_INFO,
- + 	  .idVendor		= 0x1e4e,
- + 	  .idProduct		= 0x0103,
- + 	  .bInterfaceClass	= USB_CLASS_VIDEO,
- + 	  .bInterfaceSubClass	= 1,
- + 	  .bInterfaceProtocol	= 0,
- + 	  .driver_info		= UVC_QUIRK_PROBE_DEF  
- + 	  			| UVC_QUIRK_PROBE_MINMAX
- + 				| UVC_QUIRK_PROBE_EXTRAFIELDS },
- + 	/* F2M_USB */
- + 	{ .match_flags		= USB_DEVICE_ID_MATCH_DEVICE
- + 				| USB_DEVICE_ID_MATCH_INT_INFO,
- + 	  .idVendor		= 0x1e4e,
- + 	  .idProduct		= 0x0110,
- + 	  .bInterfaceClass	= USB_CLASS_VIDEO,
- + 	  .bInterfaceSubClass	= 1,
- + 	  .bInterfaceProtocol	= 0,
- + 	  .driver_info		= UVC_QUIRK_PROBE_DEF  
- + 	  			 | UVC_QUIRK_PROBE_MINMAX
- + 				| UVC_QUIRK_PROBE_EXTRAFIELDS },
-   	/* Generic USB Video Class */
-   	{ USB_INTERFACE_INFO(USB_CLASS_VIDEO, 1, 0) },
-   	{}
- diff -crN linux-3.2.1_o/drivers/mfd/Kconfig linux-3.2.1/drivers/mfd/Kconfig
- *** linux-3.2.1_o/drivers/mfd/Kconfig	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/mfd/Kconfig	2014-05-15 13:25:14.391288127 +0900
- ***************
- *** 142,147 ****
- --- 142,170 ----
-   	  This driver can also be built as a module.  If so, the module
-   	  will be called tps6507x.
-   
- + config MFD_TI_TSCADC
- + 	tristate "TI ADC / Touch Screen chip support"
- + 	help
- + 	  If you say yes here you get support for Texas Instruments series
- + 	  of Touch Screen /ADC chips.
- + 	  To compile this driver as a module, choose M here: the
- + 	  module will be called ti_tscadc.
- + 
- + config MFD_TPS65217
- + 	tristate "TPS65217 Power Management / White LED chips"
- + 	depends on I2C
- + 	select MFD_CORE
- + 	select REGMAP_I2C
- + 	help
- + 	  If you say yes here you get support for the TPS65217 series of
- + 	  Power Management / White LED chips.
- + 	  These include voltage regulators, lithium ion/polymer battery
- + 	  charger, wled and other features that are often used in portable
- + 	  devices.
- + 
- + 	  This driver can also be built as a module.  If so, the module
- + 	  will be called tps65217.
- + 
-   config MFD_TPS6586X
-   	bool "TPS6586x Power Management chips"
-   	depends on I2C=y && GPIOLIB && GENERIC_HARDIRQS
- diff -crN linux-3.2.1_o/drivers/mfd/Makefile linux-3.2.1/drivers/mfd/Makefile
- *** linux-3.2.1_o/drivers/mfd/Makefile	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/mfd/Makefile	2014-05-15 13:25:14.411998228 +0900
- ***************
- *** 36,41 ****
- --- 36,42 ----
-   obj-$(CONFIG_TPS6105X)		+= tps6105x.o
-   obj-$(CONFIG_TPS65010)		+= tps65010.o
-   obj-$(CONFIG_TPS6507X)		+= tps6507x.o
- + obj-$(CONFIG_MFD_TPS65217)	+= tps65217.o
-   obj-$(CONFIG_MFD_TPS65910)	+= tps65910.o tps65910-irq.o
-   tps65912-objs                   := tps65912-core.o tps65912-irq.o
-   obj-$(CONFIG_MFD_TPS65912)	+= tps65912.o
- ***************
- *** 104,106 ****
- --- 105,108 ----
-   obj-$(CONFIG_TPS65911_COMPARATOR)	+= tps65911-comparator.o
-   obj-$(CONFIG_MFD_AAT2870_CORE)	+= aat2870-core.o
-   obj-$(CONFIG_MFD_INTEL_MSIC)	+= intel_msic.o
- + obj-$(CONFIG_MFD_TI_TSCADC)	+= ti_tscadc.o
- diff -crN linux-3.2.1_o/drivers/mfd/omap-usb-host.c linux-3.2.1/drivers/mfd/omap-usb-host.c
- *** linux-3.2.1_o/drivers/mfd/omap-usb-host.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/mfd/omap-usb-host.c	2014-05-15 13:25:14.427949595 +0900
- ***************
- *** 27,34 ****
-   #include <linux/spinlock.h>
-   #include <linux/gpio.h>
-   #include <plat/usb.h>
-   
- ! #define USBHS_DRIVER_NAME	"usbhs-omap"
-   #define OMAP_EHCI_DEVICE	"ehci-omap"
-   #define OMAP_OHCI_DEVICE	"ohci-omap3"
-   
- --- 27,35 ----
-   #include <linux/spinlock.h>
-   #include <linux/gpio.h>
-   #include <plat/usb.h>
- + #include <linux/pm_runtime.h>
-   
- ! #define USBHS_DRIVER_NAME	"usbhs_omap"
-   #define OMAP_EHCI_DEVICE	"ehci-omap"
-   #define OMAP_OHCI_DEVICE	"ohci-omap3"
-   
- ***************
- *** 147,155 ****
-   
-   
-   struct usbhs_hcd_omap {
- - 	struct clk			*usbhost_ick;
- - 	struct clk			*usbhost_hs_fck;
- - 	struct clk			*usbhost_fs_fck;
-   	struct clk			*xclk60mhsp1_ck;
-   	struct clk			*xclk60mhsp2_ck;
-   	struct clk			*utmi_p1_fck;
- --- 148,153 ----
- ***************
- *** 159,166 ****
-   	struct clk			*usbhost_p2_fck;
-   	struct clk			*usbtll_p2_fck;
-   	struct clk			*init_60m_fclk;
- ! 	struct clk			*usbtll_fck;
- ! 	struct clk			*usbtll_ick;
-   
-   	void __iomem			*uhh_base;
-   	void __iomem			*tll_base;
- --- 157,163 ----
-   	struct clk			*usbhost_p2_fck;
-   	struct clk			*usbtll_p2_fck;
-   	struct clk			*init_60m_fclk;
- ! 	struct clk			*ehci_logic_fck;
-   
-   	void __iomem			*uhh_base;
-   	void __iomem			*tll_base;
- ***************
- *** 169,175 ****
-   
-   	u32				usbhs_rev;
-   	spinlock_t			lock;
- - 	int				count;
-   };
-   /*-------------------------------------------------------------------------*/
-   
- --- 166,171 ----
- ***************
- *** 319,587 ****
-   	return ret;
-   }
-   
- - /**
- -  * usbhs_omap_probe - initialize TI-based HCDs
- -  *
- -  * Allocates basic resources for this USB host controller.
- -  */
- - static int __devinit usbhs_omap_probe(struct platform_device *pdev)
- - {
- - 	struct device			*dev =  &pdev->dev;
- - 	struct usbhs_omap_platform_data	*pdata = dev->platform_data;
- - 	struct usbhs_hcd_omap		*omap;
- - 	struct resource			*res;
- - 	int				ret = 0;
- - 	int				i;
- - 
- - 	if (!pdata) {
- - 		dev_err(dev, "Missing platform data\n");
- - 		ret = -ENOMEM;
- - 		goto end_probe;
- - 	}
- - 
- - 	omap = kzalloc(sizeof(*omap), GFP_KERNEL);
- - 	if (!omap) {
- - 		dev_err(dev, "Memory allocation failed\n");
- - 		ret = -ENOMEM;
- - 		goto end_probe;
- - 	}
- - 
- - 	spin_lock_init(&omap->lock);
- - 
- - 	for (i = 0; i < OMAP3_HS_USB_PORTS; i++)
- - 		omap->platdata.port_mode[i] = pdata->port_mode[i];
- - 
- - 	omap->platdata.ehci_data = pdata->ehci_data;
- - 	omap->platdata.ohci_data = pdata->ohci_data;
- - 
- - 	omap->usbhost_ick = clk_get(dev, "usbhost_ick");
- - 	if (IS_ERR(omap->usbhost_ick)) {
- - 		ret =  PTR_ERR(omap->usbhost_ick);
- - 		dev_err(dev, "usbhost_ick failed error:%d\n", ret);
- - 		goto err_end;
- - 	}
- - 
- - 	omap->usbhost_hs_fck = clk_get(dev, "hs_fck");
- - 	if (IS_ERR(omap->usbhost_hs_fck)) {
- - 		ret = PTR_ERR(omap->usbhost_hs_fck);
- - 		dev_err(dev, "usbhost_hs_fck failed error:%d\n", ret);
- - 		goto err_usbhost_ick;
- - 	}
- - 
- - 	omap->usbhost_fs_fck = clk_get(dev, "fs_fck");
- - 	if (IS_ERR(omap->usbhost_fs_fck)) {
- - 		ret = PTR_ERR(omap->usbhost_fs_fck);
- - 		dev_err(dev, "usbhost_fs_fck failed error:%d\n", ret);
- - 		goto err_usbhost_hs_fck;
- - 	}
- - 
- - 	omap->usbtll_fck = clk_get(dev, "usbtll_fck");
- - 	if (IS_ERR(omap->usbtll_fck)) {
- - 		ret = PTR_ERR(omap->usbtll_fck);
- - 		dev_err(dev, "usbtll_fck failed error:%d\n", ret);
- - 		goto err_usbhost_fs_fck;
- - 	}
- - 
- - 	omap->usbtll_ick = clk_get(dev, "usbtll_ick");
- - 	if (IS_ERR(omap->usbtll_ick)) {
- - 		ret = PTR_ERR(omap->usbtll_ick);
- - 		dev_err(dev, "usbtll_ick failed error:%d\n", ret);
- - 		goto err_usbtll_fck;
- - 	}
- - 
- - 	omap->utmi_p1_fck = clk_get(dev, "utmi_p1_gfclk");
- - 	if (IS_ERR(omap->utmi_p1_fck)) {
- - 		ret = PTR_ERR(omap->utmi_p1_fck);
- - 		dev_err(dev, "utmi_p1_gfclk failed error:%d\n",	ret);
- - 		goto err_usbtll_ick;
- - 	}
- - 
- - 	omap->xclk60mhsp1_ck = clk_get(dev, "xclk60mhsp1_ck");
- - 	if (IS_ERR(omap->xclk60mhsp1_ck)) {
- - 		ret = PTR_ERR(omap->xclk60mhsp1_ck);
- - 		dev_err(dev, "xclk60mhsp1_ck failed error:%d\n", ret);
- - 		goto err_utmi_p1_fck;
- - 	}
- - 
- - 	omap->utmi_p2_fck = clk_get(dev, "utmi_p2_gfclk");
- - 	if (IS_ERR(omap->utmi_p2_fck)) {
- - 		ret = PTR_ERR(omap->utmi_p2_fck);
- - 		dev_err(dev, "utmi_p2_gfclk failed error:%d\n", ret);
- - 		goto err_xclk60mhsp1_ck;
- - 	}
- - 
- - 	omap->xclk60mhsp2_ck = clk_get(dev, "xclk60mhsp2_ck");
- - 	if (IS_ERR(omap->xclk60mhsp2_ck)) {
- - 		ret = PTR_ERR(omap->xclk60mhsp2_ck);
- - 		dev_err(dev, "xclk60mhsp2_ck failed error:%d\n", ret);
- - 		goto err_utmi_p2_fck;
- - 	}
- - 
- - 	omap->usbhost_p1_fck = clk_get(dev, "usb_host_hs_utmi_p1_clk");
- - 	if (IS_ERR(omap->usbhost_p1_fck)) {
- - 		ret = PTR_ERR(omap->usbhost_p1_fck);
- - 		dev_err(dev, "usbhost_p1_fck failed error:%d\n", ret);
- - 		goto err_xclk60mhsp2_ck;
- - 	}
- - 
- - 	omap->usbtll_p1_fck = clk_get(dev, "usb_tll_hs_usb_ch0_clk");
- - 	if (IS_ERR(omap->usbtll_p1_fck)) {
- - 		ret = PTR_ERR(omap->usbtll_p1_fck);
- - 		dev_err(dev, "usbtll_p1_fck failed error:%d\n", ret);
- - 		goto err_usbhost_p1_fck;
- - 	}
- - 
- - 	omap->usbhost_p2_fck = clk_get(dev, "usb_host_hs_utmi_p2_clk");
- - 	if (IS_ERR(omap->usbhost_p2_fck)) {
- - 		ret = PTR_ERR(omap->usbhost_p2_fck);
- - 		dev_err(dev, "usbhost_p2_fck failed error:%d\n", ret);
- - 		goto err_usbtll_p1_fck;
- - 	}
- - 
- - 	omap->usbtll_p2_fck = clk_get(dev, "usb_tll_hs_usb_ch1_clk");
- - 	if (IS_ERR(omap->usbtll_p2_fck)) {
- - 		ret = PTR_ERR(omap->usbtll_p2_fck);
- - 		dev_err(dev, "usbtll_p2_fck failed error:%d\n", ret);
- - 		goto err_usbhost_p2_fck;
- - 	}
- - 
- - 	omap->init_60m_fclk = clk_get(dev, "init_60m_fclk");
- - 	if (IS_ERR(omap->init_60m_fclk)) {
- - 		ret = PTR_ERR(omap->init_60m_fclk);
- - 		dev_err(dev, "init_60m_fclk failed error:%d\n", ret);
- - 		goto err_usbtll_p2_fck;
- - 	}
- - 
- - 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "uhh");
- - 	if (!res) {
- - 		dev_err(dev, "UHH EHCI get resource failed\n");
- - 		ret = -ENODEV;
- - 		goto err_init_60m_fclk;
- - 	}
- - 
- - 	omap->uhh_base = ioremap(res->start, resource_size(res));
- - 	if (!omap->uhh_base) {
- - 		dev_err(dev, "UHH ioremap failed\n");
- - 		ret = -ENOMEM;
- - 		goto err_init_60m_fclk;
- - 	}
- - 
- - 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tll");
- - 	if (!res) {
- - 		dev_err(dev, "UHH EHCI get resource failed\n");
- - 		ret = -ENODEV;
- - 		goto err_tll;
- - 	}
- - 
- - 	omap->tll_base = ioremap(res->start, resource_size(res));
- - 	if (!omap->tll_base) {
- - 		dev_err(dev, "TLL ioremap failed\n");
- - 		ret = -ENOMEM;
- - 		goto err_tll;
- - 	}
- - 
- - 	platform_set_drvdata(pdev, omap);
- - 
- - 	ret = omap_usbhs_alloc_children(pdev);
- - 	if (ret) {
- - 		dev_err(dev, "omap_usbhs_alloc_children failed\n");
- - 		goto err_alloc;
- - 	}
- - 
- - 	goto end_probe;
- - 
- - err_alloc:
- - 	iounmap(omap->tll_base);
- - 
- - err_tll:
- - 	iounmap(omap->uhh_base);
- - 
- - err_init_60m_fclk:
- - 	clk_put(omap->init_60m_fclk);
- - 
- - err_usbtll_p2_fck:
- - 	clk_put(omap->usbtll_p2_fck);
- - 
- - err_usbhost_p2_fck:
- - 	clk_put(omap->usbhost_p2_fck);
- - 
- - err_usbtll_p1_fck:
- - 	clk_put(omap->usbtll_p1_fck);
- - 
- - err_usbhost_p1_fck:
- - 	clk_put(omap->usbhost_p1_fck);
- - 
- - err_xclk60mhsp2_ck:
- - 	clk_put(omap->xclk60mhsp2_ck);
- - 
- - err_utmi_p2_fck:
- - 	clk_put(omap->utmi_p2_fck);
- - 
- - err_xclk60mhsp1_ck:
- - 	clk_put(omap->xclk60mhsp1_ck);
- - 
- - err_utmi_p1_fck:
- - 	clk_put(omap->utmi_p1_fck);
- - 
- - err_usbtll_ick:
- - 	clk_put(omap->usbtll_ick);
- - 
- - err_usbtll_fck:
- - 	clk_put(omap->usbtll_fck);
- - 
- - err_usbhost_fs_fck:
- - 	clk_put(omap->usbhost_fs_fck);
- - 
- - err_usbhost_hs_fck:
- - 	clk_put(omap->usbhost_hs_fck);
- - 
- - err_usbhost_ick:
- - 	clk_put(omap->usbhost_ick);
- - 
- - err_end:
- - 	kfree(omap);
- - 
- - end_probe:
- - 	return ret;
- - }
- - 
- - /**
- -  * usbhs_omap_remove - shutdown processing for UHH & TLL HCDs
- -  * @pdev: USB Host Controller being removed
- -  *
- -  * Reverses the effect of usbhs_omap_probe().
- -  */
- - static int __devexit usbhs_omap_remove(struct platform_device *pdev)
- - {
- - 	struct usbhs_hcd_omap *omap = platform_get_drvdata(pdev);
- - 
- - 	if (omap->count != 0) {
- - 		dev_err(&pdev->dev,
- - 			"Either EHCI or OHCI is still using usbhs core\n");
- - 		return -EBUSY;
- - 	}
- - 
- - 	iounmap(omap->tll_base);
- - 	iounmap(omap->uhh_base);
- - 	clk_put(omap->init_60m_fclk);
- - 	clk_put(omap->usbtll_p2_fck);
- - 	clk_put(omap->usbhost_p2_fck);
- - 	clk_put(omap->usbtll_p1_fck);
- - 	clk_put(omap->usbhost_p1_fck);
- - 	clk_put(omap->xclk60mhsp2_ck);
- - 	clk_put(omap->utmi_p2_fck);
- - 	clk_put(omap->xclk60mhsp1_ck);
- - 	clk_put(omap->utmi_p1_fck);
- - 	clk_put(omap->usbtll_ick);
- - 	clk_put(omap->usbtll_fck);
- - 	clk_put(omap->usbhost_fs_fck);
- - 	clk_put(omap->usbhost_hs_fck);
- - 	clk_put(omap->usbhost_ick);
- - 	kfree(omap);
- - 
- - 	return 0;
- - }
- - 
-   static bool is_ohci_port(enum usbhs_omap_port_mode pmode)
-   {
-   	switch (pmode) {
- --- 315,320 ----
- ***************
- *** 689,718 ****
-   	}
-   }
-   
- ! static int usbhs_enable(struct device *dev)
-   {
-   	struct usbhs_hcd_omap		*omap = dev_get_drvdata(dev);
-   	struct usbhs_omap_platform_data	*pdata = &omap->platdata;
- ! 	unsigned long			flags = 0;
- ! 	int				ret = 0;
- ! 	unsigned long			timeout;
- ! 	unsigned			reg;
-   
- - 	dev_dbg(dev, "starting TI HSUSB Controller\n");
-   	if (!pdata) {
-   		dev_dbg(dev, "missing platform_data\n");
-   		return  -ENODEV;
-   	}
-   
-   	spin_lock_irqsave(&omap->lock, flags);
- - 	if (omap->count > 0)
- - 		goto end_count;
-   
- ! 	clk_enable(omap->usbhost_ick);
- ! 	clk_enable(omap->usbhost_hs_fck);
- ! 	clk_enable(omap->usbhost_fs_fck);
- ! 	clk_enable(omap->usbtll_fck);
- ! 	clk_enable(omap->usbtll_ick);
-   
-   	if (pdata->ehci_data->phy_reset) {
-   		if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) {
- --- 422,506 ----
-   	}
-   }
-   
- ! static int usbhs_runtime_resume(struct device *dev)
-   {
-   	struct usbhs_hcd_omap		*omap = dev_get_drvdata(dev);
-   	struct usbhs_omap_platform_data	*pdata = &omap->platdata;
- ! 	unsigned long			flags;
- ! 
- ! 	dev_dbg(dev, "usbhs_runtime_resume\n");
- ! 
- ! 	if (!pdata) {
- ! 		dev_dbg(dev, "missing platform_data\n");
- ! 		return  -ENODEV;
- ! 	}
- ! 
- ! 	spin_lock_irqsave(&omap->lock, flags);
- ! 
- ! 	if (omap->ehci_logic_fck && !IS_ERR(omap->ehci_logic_fck))
- ! 		clk_enable(omap->ehci_logic_fck);
- ! 
- ! 	if (is_ehci_tll_mode(pdata->port_mode[0])) {
- ! 		clk_enable(omap->usbhost_p1_fck);
- ! 		clk_enable(omap->usbtll_p1_fck);
- ! 	}
- ! 	if (is_ehci_tll_mode(pdata->port_mode[1])) {
- ! 		clk_enable(omap->usbhost_p2_fck);
- ! 		clk_enable(omap->usbtll_p2_fck);
- ! 	}
- ! 	clk_enable(omap->utmi_p1_fck);
- ! 	clk_enable(omap->utmi_p2_fck);
- ! 
- ! 	spin_unlock_irqrestore(&omap->lock, flags);
- ! 
- ! 	return 0;
- ! }
- ! 
- ! static int usbhs_runtime_suspend(struct device *dev)
- ! {
- ! 	struct usbhs_hcd_omap		*omap = dev_get_drvdata(dev);
- ! 	struct usbhs_omap_platform_data	*pdata = &omap->platdata;
- ! 	unsigned long			flags;
- ! 
- ! 	dev_dbg(dev, "usbhs_runtime_suspend\n");
-   
-   	if (!pdata) {
-   		dev_dbg(dev, "missing platform_data\n");
-   		return  -ENODEV;
-   	}
-   
-   	spin_lock_irqsave(&omap->lock, flags);
-   
- ! 	if (is_ehci_tll_mode(pdata->port_mode[0])) {
- ! 		clk_disable(omap->usbhost_p1_fck);
- ! 		clk_disable(omap->usbtll_p1_fck);
- ! 	}
- ! 	if (is_ehci_tll_mode(pdata->port_mode[1])) {
- ! 		clk_disable(omap->usbhost_p2_fck);
- ! 		clk_disable(omap->usbtll_p2_fck);
- ! 	}
- ! 	clk_disable(omap->utmi_p2_fck);
- ! 	clk_disable(omap->utmi_p1_fck);
- ! 
- ! 	if (omap->ehci_logic_fck && !IS_ERR(omap->ehci_logic_fck))
- ! 		clk_disable(omap->ehci_logic_fck);
- ! 
- ! 	spin_unlock_irqrestore(&omap->lock, flags);
- ! 
- ! 	return 0;
- ! }
- ! 
- ! static void omap_usbhs_init(struct device *dev)
- ! {
- ! 	struct usbhs_hcd_omap		*omap = dev_get_drvdata(dev);
- ! 	struct usbhs_omap_platform_data	*pdata = &omap->platdata;
- ! 	unsigned long			flags;
- ! 	unsigned			reg;
- ! 
- ! 	dev_dbg(dev, "starting TI HSUSB Controller\n");
- ! 
- ! 	pm_runtime_get_sync(dev);
- ! 	spin_lock_irqsave(&omap->lock, flags);
-   
-   	if (pdata->ehci_data->phy_reset) {
-   		if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) {
- ***************
- *** 736,785 ****
-   	omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION);
-   	dev_dbg(dev, "OMAP UHH_REVISION 0x%x\n", omap->usbhs_rev);
-   
- - 	/* perform TLL soft reset, and wait until reset is complete */
- - 	usbhs_write(omap->tll_base, OMAP_USBTLL_SYSCONFIG,
- - 			OMAP_USBTLL_SYSCONFIG_SOFTRESET);
- - 
- - 	/* Wait for TLL reset to complete */
- - 	timeout = jiffies + msecs_to_jiffies(1000);
- - 	while (!(usbhs_read(omap->tll_base, OMAP_USBTLL_SYSSTATUS)
- - 			& OMAP_USBTLL_SYSSTATUS_RESETDONE)) {
- - 		cpu_relax();
- - 
- - 		if (time_after(jiffies, timeout)) {
- - 			dev_dbg(dev, "operation timed out\n");
- - 			ret = -EINVAL;
- - 			goto err_tll;
- - 		}
- - 	}
- - 
- - 	dev_dbg(dev, "TLL RESET DONE\n");
- - 
- - 	/* (1<<3) = no idle mode only for initial debugging */
- - 	usbhs_write(omap->tll_base, OMAP_USBTLL_SYSCONFIG,
- - 			OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
- - 			OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
- - 			OMAP_USBTLL_SYSCONFIG_AUTOIDLE);
- - 
- - 	/* Put UHH in NoIdle/NoStandby mode */
- - 	reg = usbhs_read(omap->uhh_base, OMAP_UHH_SYSCONFIG);
- - 	if (is_omap_usbhs_rev1(omap)) {
- - 		reg |= (OMAP_UHH_SYSCONFIG_ENAWAKEUP
- - 				| OMAP_UHH_SYSCONFIG_SIDLEMODE
- - 				| OMAP_UHH_SYSCONFIG_CACTIVITY
- - 				| OMAP_UHH_SYSCONFIG_MIDLEMODE);
- - 		reg &= ~OMAP_UHH_SYSCONFIG_AUTOIDLE;
- - 
- - 
- - 	} else if (is_omap_usbhs_rev2(omap)) {
- - 		reg &= ~OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR;
- - 		reg |= OMAP4_UHH_SYSCONFIG_NOIDLE;
- - 		reg &= ~OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR;
- - 		reg |= OMAP4_UHH_SYSCONFIG_NOSTDBY;
- - 	}
- - 
- - 	usbhs_write(omap->uhh_base, OMAP_UHH_SYSCONFIG, reg);
- - 
-   	reg = usbhs_read(omap->uhh_base, OMAP_UHH_HOSTCONFIG);
-   	/* setup ULPI bypass and burst configurations */
-   	reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
- --- 524,529 ----
- ***************
- *** 825,873 ****
-   		reg &= ~OMAP4_P1_MODE_CLEAR;
-   		reg &= ~OMAP4_P2_MODE_CLEAR;
-   
- - 		if (is_ehci_phy_mode(pdata->port_mode[0])) {
- - 			ret = clk_set_parent(omap->utmi_p1_fck,
- - 						omap->xclk60mhsp1_ck);
- - 			if (ret != 0) {
- - 				dev_err(dev, "xclk60mhsp1_ck set parent"
- - 				"failed error:%d\n", ret);
- - 				goto err_tll;
- - 			}
- - 		} else if (is_ehci_tll_mode(pdata->port_mode[0])) {
- - 			ret = clk_set_parent(omap->utmi_p1_fck,
- - 						omap->init_60m_fclk);
- - 			if (ret != 0) {
- - 				dev_err(dev, "init_60m_fclk set parent"
- - 				"failed error:%d\n", ret);
- - 				goto err_tll;
- - 			}
- - 			clk_enable(omap->usbhost_p1_fck);
- - 			clk_enable(omap->usbtll_p1_fck);
- - 		}
- - 
- - 		if (is_ehci_phy_mode(pdata->port_mode[1])) {
- - 			ret = clk_set_parent(omap->utmi_p2_fck,
- - 						omap->xclk60mhsp2_ck);
- - 			if (ret != 0) {
- - 				dev_err(dev, "xclk60mhsp1_ck set parent"
- - 					"failed error:%d\n", ret);
- - 				goto err_tll;
- - 			}
- - 		} else if (is_ehci_tll_mode(pdata->port_mode[1])) {
- - 			ret = clk_set_parent(omap->utmi_p2_fck,
- - 						omap->init_60m_fclk);
- - 			if (ret != 0) {
- - 				dev_err(dev, "init_60m_fclk set parent"
- - 				"failed error:%d\n", ret);
- - 				goto err_tll;
- - 			}
- - 			clk_enable(omap->usbhost_p2_fck);
- - 			clk_enable(omap->usbtll_p2_fck);
- - 		}
- - 
- - 		clk_enable(omap->utmi_p1_fck);
- - 		clk_enable(omap->utmi_p2_fck);
- - 
-   		if (is_ehci_tll_mode(pdata->port_mode[0]) ||
-   			(is_ohci_port(pdata->port_mode[0])))
-   			reg |= OMAP4_P1_MODE_TLL;
- --- 569,574 ----
- ***************
- *** 913,924 ****
-   				(pdata->ehci_data->reset_gpio_port[1], 1);
-   	}
-   
- - end_count:
- - 	omap->count++;
-   	spin_unlock_irqrestore(&omap->lock, flags);
- ! 	return 0;
-   
- - err_tll:
-   	if (pdata->ehci_data->phy_reset) {
-   		if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0]))
-   			gpio_free(pdata->ehci_data->reset_gpio_port[0]);
- --- 614,628 ----
-   				(pdata->ehci_data->reset_gpio_port[1], 1);
-   	}
-   
-   	spin_unlock_irqrestore(&omap->lock, flags);
- ! 	pm_runtime_put_sync(dev);
- ! }
- ! 
- ! static void omap_usbhs_deinit(struct device *dev)
- ! {
- ! 	struct usbhs_hcd_omap		*omap = dev_get_drvdata(dev);
- ! 	struct usbhs_omap_platform_data	*pdata = &omap->platdata;
-   
-   	if (pdata->ehci_data->phy_reset) {
-   		if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0]))
-   			gpio_free(pdata->ehci_data->reset_gpio_port[0]);
- ***************
- *** 926,1048 ****
-   		if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1]))
-   			gpio_free(pdata->ehci_data->reset_gpio_port[1]);
-   	}
- - 
- - 	clk_disable(omap->usbtll_ick);
- - 	clk_disable(omap->usbtll_fck);
- - 	clk_disable(omap->usbhost_fs_fck);
- - 	clk_disable(omap->usbhost_hs_fck);
- - 	clk_disable(omap->usbhost_ick);
- - 	spin_unlock_irqrestore(&omap->lock, flags);
- - 	return ret;
-   }
-   
- ! static void usbhs_disable(struct device *dev)
-   {
- ! 	struct usbhs_hcd_omap		*omap = dev_get_drvdata(dev);
- ! 	struct usbhs_omap_platform_data	*pdata = &omap->platdata;
- ! 	unsigned long			flags = 0;
- ! 	unsigned long			timeout;
-   
- ! 	dev_dbg(dev, "stopping TI HSUSB Controller\n");
-   
- ! 	spin_lock_irqsave(&omap->lock, flags);
-   
- ! 	if (omap->count == 0)
- ! 		goto end_disble;
-   
- ! 	omap->count--;
-   
- ! 	if (omap->count != 0)
- ! 		goto end_disble;
-   
- - 	/* Reset OMAP modules for insmod/rmmod to work */
- - 	usbhs_write(omap->uhh_base, OMAP_UHH_SYSCONFIG,
- - 			is_omap_usbhs_rev2(omap) ?
- - 			OMAP4_UHH_SYSCONFIG_SOFTRESET :
- - 			OMAP_UHH_SYSCONFIG_SOFTRESET);
-   
- ! 	timeout = jiffies + msecs_to_jiffies(100);
- ! 	while (!(usbhs_read(omap->uhh_base, OMAP_UHH_SYSSTATUS)
- ! 				& (1 << 0))) {
- ! 		cpu_relax();
-   
- ! 		if (time_after(jiffies, timeout))
- ! 			dev_dbg(dev, "operation timed out\n");
-   	}
-   
- ! 	while (!(usbhs_read(omap->uhh_base, OMAP_UHH_SYSSTATUS)
- ! 				& (1 << 1))) {
- ! 		cpu_relax();
-   
- ! 		if (time_after(jiffies, timeout))
- ! 			dev_dbg(dev, "operation timed out\n");
-   	}
-   
- ! 	while (!(usbhs_read(omap->uhh_base, OMAP_UHH_SYSSTATUS)
- ! 				& (1 << 2))) {
- ! 		cpu_relax();
-   
- ! 		if (time_after(jiffies, timeout))
- ! 			dev_dbg(dev, "operation timed out\n");
-   	}
-   
- ! 	usbhs_write(omap->tll_base, OMAP_USBTLL_SYSCONFIG, (1 << 1));
-   
- ! 	while (!(usbhs_read(omap->tll_base, OMAP_USBTLL_SYSSTATUS)
- ! 				& (1 << 0))) {
- ! 		cpu_relax();
-   
- ! 		if (time_after(jiffies, timeout))
- ! 			dev_dbg(dev, "operation timed out\n");
-   	}
-   
- ! 	if (is_omap_usbhs_rev2(omap)) {
- ! 		if (is_ehci_tll_mode(pdata->port_mode[0]))
- ! 			clk_disable(omap->usbtll_p1_fck);
- ! 		if (is_ehci_tll_mode(pdata->port_mode[1]))
- ! 			clk_disable(omap->usbtll_p2_fck);
- ! 		clk_disable(omap->utmi_p2_fck);
- ! 		clk_disable(omap->utmi_p1_fck);
-   	}
-   
- ! 	clk_disable(omap->usbtll_ick);
- ! 	clk_disable(omap->usbtll_fck);
- ! 	clk_disable(omap->usbhost_fs_fck);
- ! 	clk_disable(omap->usbhost_hs_fck);
- ! 	clk_disable(omap->usbhost_ick);
-   
- ! 	/* The gpio_free migh sleep; so unlock the spinlock */
- ! 	spin_unlock_irqrestore(&omap->lock, flags);
-   
- ! 	if (pdata->ehci_data->phy_reset) {
- ! 		if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0]))
- ! 			gpio_free(pdata->ehci_data->reset_gpio_port[0]);
-   
- ! 		if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1]))
- ! 			gpio_free(pdata->ehci_data->reset_gpio_port[1]);
-   	}
- - 	return;
-   
- ! end_disble:
- ! 	spin_unlock_irqrestore(&omap->lock, flags);
- ! }
-   
- ! int omap_usbhs_enable(struct device *dev)
- ! {
- ! 	return  usbhs_enable(dev->parent);
-   }
- - EXPORT_SYMBOL_GPL(omap_usbhs_enable);
-   
- ! void omap_usbhs_disable(struct device *dev)
-   {
- ! 	usbhs_disable(dev->parent);
-   }
- ! EXPORT_SYMBOL_GPL(omap_usbhs_disable);
-   
-   static struct platform_driver usbhs_omap_driver = {
-   	.driver = {
-   		.name		= (char *)usbhs_driver_name,
-   		.owner		= THIS_MODULE,
-   	},
-   	.remove		= __exit_p(usbhs_omap_remove),
-   };
- --- 630,901 ----
-   		if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1]))
-   			gpio_free(pdata->ehci_data->reset_gpio_port[1]);
-   	}
-   }
-   
- ! 
- ! /**
- !  * usbhs_omap_probe - initialize TI-based HCDs
- !  *
- !  * Allocates basic resources for this USB host controller.
- !  */
- ! static int __devinit usbhs_omap_probe(struct platform_device *pdev)
-   {
- ! 	struct device			*dev =  &pdev->dev;
- ! 	struct usbhs_omap_platform_data	*pdata = dev->platform_data;
- ! 	struct usbhs_hcd_omap		*omap;
- ! 	struct resource			*res;
- ! 	int				ret = 0;
- ! 	int				i;
- ! 
- ! 	if (!pdata) {
- ! 		dev_err(dev, "Missing platform data\n");
- ! 		ret = -ENOMEM;
- ! 		goto end_probe;
- ! 	}
-   
- ! 	omap = kzalloc(sizeof(*omap), GFP_KERNEL);
- ! 	if (!omap) {
- ! 		dev_err(dev, "Memory allocation failed\n");
- ! 		ret = -ENOMEM;
- ! 		goto end_probe;
- ! 	}
-   
- ! 	spin_lock_init(&omap->lock);
-   
- ! 	for (i = 0; i < OMAP3_HS_USB_PORTS; i++)
- ! 		omap->platdata.port_mode[i] = pdata->port_mode[i];
-   
- ! 	omap->platdata.ehci_data = pdata->ehci_data;
- ! 	omap->platdata.ohci_data = pdata->ohci_data;
-   
- ! 	pm_runtime_enable(dev);
-   
-   
- ! 	for (i = 0; i < OMAP3_HS_USB_PORTS; i++)
- ! 		if (is_ehci_phy_mode(i) || is_ehci_tll_mode(i) ||
- ! 			is_ehci_hsic_mode(i)) {
- ! 			omap->ehci_logic_fck = clk_get(dev, "ehci_logic_fck");
- ! 			if (IS_ERR(omap->ehci_logic_fck)) {
- ! 				ret = PTR_ERR(omap->ehci_logic_fck);
- ! 				dev_warn(dev, "ehci_logic_fck failed:%d\n",
- ! 					 ret);
- ! 			}
- ! 			break;
- ! 		}
-   
- ! 	omap->utmi_p1_fck = clk_get(dev, "utmi_p1_gfclk");
- ! 	if (IS_ERR(omap->utmi_p1_fck)) {
- ! 		ret = PTR_ERR(omap->utmi_p1_fck);
- ! 		dev_err(dev, "utmi_p1_gfclk failed error:%d\n",	ret);
- ! 		goto err_end;
-   	}
-   
- ! 	omap->xclk60mhsp1_ck = clk_get(dev, "xclk60mhsp1_ck");
- ! 	if (IS_ERR(omap->xclk60mhsp1_ck)) {
- ! 		ret = PTR_ERR(omap->xclk60mhsp1_ck);
- ! 		dev_err(dev, "xclk60mhsp1_ck failed error:%d\n", ret);
- ! 		goto err_utmi_p1_fck;
- ! 	}
-   
- ! 	omap->utmi_p2_fck = clk_get(dev, "utmi_p2_gfclk");
- ! 	if (IS_ERR(omap->utmi_p2_fck)) {
- ! 		ret = PTR_ERR(omap->utmi_p2_fck);
- ! 		dev_err(dev, "utmi_p2_gfclk failed error:%d\n", ret);
- ! 		goto err_xclk60mhsp1_ck;
- ! 	}
- ! 
- ! 	omap->xclk60mhsp2_ck = clk_get(dev, "xclk60mhsp2_ck");
- ! 	if (IS_ERR(omap->xclk60mhsp2_ck)) {
- ! 		ret = PTR_ERR(omap->xclk60mhsp2_ck);
- ! 		dev_err(dev, "xclk60mhsp2_ck failed error:%d\n", ret);
- ! 		goto err_utmi_p2_fck;
- ! 	}
- ! 
- ! 	omap->usbhost_p1_fck = clk_get(dev, "usb_host_hs_utmi_p1_clk");
- ! 	if (IS_ERR(omap->usbhost_p1_fck)) {
- ! 		ret = PTR_ERR(omap->usbhost_p1_fck);
- ! 		dev_err(dev, "usbhost_p1_fck failed error:%d\n", ret);
- ! 		goto err_xclk60mhsp2_ck;
- ! 	}
- ! 
- ! 	omap->usbtll_p1_fck = clk_get(dev, "usb_tll_hs_usb_ch0_clk");
- ! 	if (IS_ERR(omap->usbtll_p1_fck)) {
- ! 		ret = PTR_ERR(omap->usbtll_p1_fck);
- ! 		dev_err(dev, "usbtll_p1_fck failed error:%d\n", ret);
- ! 		goto err_usbhost_p1_fck;
- ! 	}
- ! 
- ! 	omap->usbhost_p2_fck = clk_get(dev, "usb_host_hs_utmi_p2_clk");
- ! 	if (IS_ERR(omap->usbhost_p2_fck)) {
- ! 		ret = PTR_ERR(omap->usbhost_p2_fck);
- ! 		dev_err(dev, "usbhost_p2_fck failed error:%d\n", ret);
- ! 		goto err_usbtll_p1_fck;
-   	}
-   
- ! 	omap->usbtll_p2_fck = clk_get(dev, "usb_tll_hs_usb_ch1_clk");
- ! 	if (IS_ERR(omap->usbtll_p2_fck)) {
- ! 		ret = PTR_ERR(omap->usbtll_p2_fck);
- ! 		dev_err(dev, "usbtll_p2_fck failed error:%d\n", ret);
- ! 		goto err_usbhost_p2_fck;
- ! 	}
-   
- ! 	omap->init_60m_fclk = clk_get(dev, "init_60m_fclk");
- ! 	if (IS_ERR(omap->init_60m_fclk)) {
- ! 		ret = PTR_ERR(omap->init_60m_fclk);
- ! 		dev_err(dev, "init_60m_fclk failed error:%d\n", ret);
- ! 		goto err_usbtll_p2_fck;
-   	}
-   
- ! 	if (is_ehci_phy_mode(pdata->port_mode[0])) {
- ! 		/* for OMAP3 , the clk set paretn fails */
- ! 		ret = clk_set_parent(omap->utmi_p1_fck,
- ! 					omap->xclk60mhsp1_ck);
- ! 		if (ret != 0)
- ! 			dev_err(dev, "xclk60mhsp1_ck set parent"
- ! 				"failed error:%d\n", ret);
- ! 	} else if (is_ehci_tll_mode(pdata->port_mode[0])) {
- ! 		ret = clk_set_parent(omap->utmi_p1_fck,
- ! 					omap->init_60m_fclk);
- ! 		if (ret != 0)
- ! 			dev_err(dev, "init_60m_fclk set parent"
- ! 				"failed error:%d\n", ret);
- ! 	}
-   
- ! 	if (is_ehci_phy_mode(pdata->port_mode[1])) {
- ! 		ret = clk_set_parent(omap->utmi_p2_fck,
- ! 					omap->xclk60mhsp2_ck);
- ! 		if (ret != 0)
- ! 			dev_err(dev, "xclk60mhsp2_ck set parent"
- ! 					"failed error:%d\n", ret);
- ! 	} else if (is_ehci_tll_mode(pdata->port_mode[1])) {
- ! 		ret = clk_set_parent(omap->utmi_p2_fck,
- ! 						omap->init_60m_fclk);
- ! 		if (ret != 0)
- ! 			dev_err(dev, "init_60m_fclk set parent"
- ! 				"failed error:%d\n", ret);
- ! 	}
-   
- ! 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "uhh");
- ! 	if (!res) {
- ! 		dev_err(dev, "UHH EHCI get resource failed\n");
- ! 		ret = -ENODEV;
- ! 		goto err_init_60m_fclk;
-   	}
-   
- ! 	omap->uhh_base = ioremap(res->start, resource_size(res));
- ! 	if (!omap->uhh_base) {
- ! 		dev_err(dev, "UHH ioremap failed\n");
- ! 		ret = -ENOMEM;
- ! 		goto err_init_60m_fclk;
-   	}
-   
- ! 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tll");
- ! 	if (!res) {
- ! 		dev_err(dev, "UHH EHCI get resource failed\n");
- ! 		ret = -ENODEV;
- ! 		goto err_tll;
- ! 	}
-   
- ! 	omap->tll_base = ioremap(res->start, resource_size(res));
- ! 	if (!omap->tll_base) {
- ! 		dev_err(dev, "TLL ioremap failed\n");
- ! 		ret = -ENOMEM;
- ! 		goto err_tll;
- ! 	}
-   
- ! 	platform_set_drvdata(pdev, omap);
-   
- ! 	ret = omap_usbhs_alloc_children(pdev);
- ! 	if (ret) {
- ! 		dev_err(dev, "omap_usbhs_alloc_children failed\n");
- ! 		goto err_alloc;
-   	}
-   
- ! 	omap_usbhs_init(dev);
-   
- ! 	goto end_probe;
- ! 
- ! err_alloc:
- ! 	iounmap(omap->tll_base);
- ! 
- ! err_tll:
- ! 	iounmap(omap->uhh_base);
- ! 
- ! err_init_60m_fclk:
- ! 	clk_put(omap->init_60m_fclk);
- ! 
- ! err_usbtll_p2_fck:
- ! 	clk_put(omap->usbtll_p2_fck);
- ! 
- ! err_usbhost_p2_fck:
- ! 	clk_put(omap->usbhost_p2_fck);
- ! 
- ! err_usbtll_p1_fck:
- ! 	clk_put(omap->usbtll_p1_fck);
- ! 
- ! err_usbhost_p1_fck:
- ! 	clk_put(omap->usbhost_p1_fck);
- ! 
- ! err_xclk60mhsp2_ck:
- ! 	clk_put(omap->xclk60mhsp2_ck);
- ! 
- ! err_utmi_p2_fck:
- ! 	clk_put(omap->utmi_p2_fck);
- ! 
- ! err_xclk60mhsp1_ck:
- ! 	clk_put(omap->xclk60mhsp1_ck);
- ! 
- ! err_utmi_p1_fck:
- ! 	clk_put(omap->utmi_p1_fck);
- ! 
- ! err_end:
- ! 	clk_put(omap->ehci_logic_fck);
- ! 	pm_runtime_disable(dev);
- ! 	kfree(omap);
- ! 
- ! end_probe:
- ! 	return ret;
-   }
-   
- ! /**
- !  * usbhs_omap_remove - shutdown processing for UHH & TLL HCDs
- !  * @pdev: USB Host Controller being removed
- !  *
- !  * Reverses the effect of usbhs_omap_probe().
- !  */
- ! static int __devexit usbhs_omap_remove(struct platform_device *pdev)
-   {
- ! 	struct usbhs_hcd_omap *omap = platform_get_drvdata(pdev);
- ! 
- ! 	omap_usbhs_deinit(&pdev->dev);
- ! 	iounmap(omap->tll_base);
- ! 	iounmap(omap->uhh_base);
- ! 	clk_put(omap->init_60m_fclk);
- ! 	clk_put(omap->usbtll_p2_fck);
- ! 	clk_put(omap->usbhost_p2_fck);
- ! 	clk_put(omap->usbtll_p1_fck);
- ! 	clk_put(omap->usbhost_p1_fck);
- ! 	clk_put(omap->xclk60mhsp2_ck);
- ! 	clk_put(omap->utmi_p2_fck);
- ! 	clk_put(omap->xclk60mhsp1_ck);
- ! 	clk_put(omap->utmi_p1_fck);
- ! 	clk_put(omap->ehci_logic_fck);
- ! 	pm_runtime_disable(&pdev->dev);
- ! 	kfree(omap);
- ! 
- ! 	return 0;
-   }
- ! 
- ! static const struct dev_pm_ops usbhsomap_dev_pm_ops = {
- ! 	.runtime_suspend	= usbhs_runtime_suspend,
- ! 	.runtime_resume		= usbhs_runtime_resume,
- ! };
-   
-   static struct platform_driver usbhs_omap_driver = {
-   	.driver = {
-   		.name		= (char *)usbhs_driver_name,
-   		.owner		= THIS_MODULE,
- + 		.pm		= &usbhsomap_dev_pm_ops,
-   	},
-   	.remove		= __exit_p(usbhs_omap_remove),
-   };
- diff -crN linux-3.2.1_o/drivers/mfd/ti_tscadc.c linux-3.2.1/drivers/mfd/ti_tscadc.c
- *** linux-3.2.1_o/drivers/mfd/ti_tscadc.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/drivers/mfd/ti_tscadc.c	2014-05-15 13:25:14.436019220 +0900
- ***************
- *** 0 ****
- --- 1,261 ----
- + /*
- +  * TI Touch Screen / ADC MFD driver
- +  *
- +  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #include <linux/module.h>
- + #include <linux/init.h>
- + #include <linux/slab.h>
- + #include <linux/err.h>
- + #include <linux/io.h>
- + #include <linux/clk.h>
- + #include <linux/mfd/core.h>
- + #include <linux/pm_runtime.h>
- + #include <linux/mfd/ti_tscadc.h>
- + #include <linux/input/ti_tsc.h>
- + #include <linux/platform_data/ti_adc.h>
- + 
- + static unsigned int tscadc_readl(struct ti_tscadc_dev *tsadc, unsigned int reg)
- + {
- + 	return readl(tsadc->tscadc_base + reg);
- + }
- + 
- + static void tscadc_writel(struct ti_tscadc_dev *tsadc, unsigned int reg,
- + 					unsigned int val)
- + {
- + 	writel(val, tsadc->tscadc_base + reg);
- + }
- + 
- + static void tscadc_idle_config(struct ti_tscadc_dev *config)
- + {
- + 	unsigned int idleconfig;
- + 
- + 	idleconfig = TSCADC_STEPCONFIG_YNN | TSCADC_STEPCONFIG_INM_ADCREFM |
- + 			TSCADC_STEPCONFIG_INP_ADCREFM | TSCADC_STEPCONFIG_YPN;
- + 
- + 	tscadc_writel(config, TSCADC_REG_IDLECONFIG, idleconfig);
- + }
- + 
- + static int __devinit ti_tscadc_probe(struct platform_device *pdev)
- + {
- + 	struct ti_tscadc_dev	*tscadc;
- + 	struct resource		*res;
- + 	struct clk		*clk;
- + 	struct mfd_tscadc_board	*pdata = pdev->dev.platform_data;
- + 	struct mfd_cell		*cell;
- + 	int			err, ctrl, children = 0;
- + 	int			clk_value, clock_rate;
- + 	int			tsc_wires = 0, adc_channels = 0, total_channels;
- + 
- + 	if (!pdata) {
- + 		dev_err(&pdev->dev, "Could not find platform data\n");
- + 		return -EINVAL;
- + 	}
- + 
- + 	if (pdata->adc_init)
- + 		adc_channels = pdata->adc_init->adc_channels;
- + 
- + 	if (pdata->tsc_init)
- + 		tsc_wires = pdata->tsc_init->wires;
- + 
- + 	total_channels = tsc_wires + adc_channels;
- + 
- + 	if (total_channels > 8) {
- + 		dev_err(&pdev->dev, "Number of i/p channels more than 8\n");
- + 		return -EINVAL;
- + 	}
- + 
- + 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- + 	if (!res) {
- + 		dev_err(&pdev->dev, "no memory resource defined.\n");
- + 		return -EINVAL;
- + 	}
- + 
- + 	/* Allocate memory for device */
- + 	tscadc = kzalloc(sizeof(struct ti_tscadc_dev), GFP_KERNEL);
- + 	if (!tscadc) {
- + 		dev_err(&pdev->dev, "failed to allocate memory.\n");
- + 		return -ENOMEM;
- + 	}
- + 
- + 	res = request_mem_region(res->start, resource_size(res),
- + 			pdev->name);
- + 	if (!res) {
- + 		dev_err(&pdev->dev, "failed to reserve registers.\n");
- + 		err = -EBUSY;
- + 		goto err_free_mem;
- + 	}
- + 
- + 	tscadc->tscadc_base = ioremap(res->start, resource_size(res));
- + 	if (!tscadc->tscadc_base) {
- + 		dev_err(&pdev->dev, "failed to map registers.\n");
- + 		err = -ENOMEM;
- + 		goto err_release_mem;
- + 	}
- + 
- + 	tscadc->irq = platform_get_irq(pdev, 0);
- + 	if (tscadc->irq < 0) {
- + 		dev_err(&pdev->dev, "no irq ID is specified.\n");
- + 		return -ENODEV;
- + 	}
- + 
- + 	tscadc->dev = &pdev->dev;
- + 
- + 	pm_runtime_enable(&pdev->dev);
- + 	pm_runtime_get_sync(&pdev->dev);
- + 
- + 	/*
- + 	 * The TSC_ADC_Subsystem has 2 clock domains
- + 	 * OCP_CLK and ADC_CLK.
- + 	 * The ADC clock is expected to run at target of 3MHz,
- + 	 * and expected to capture 12-bit data at a rate of 200 KSPS.
- + 	 * The TSC_ADC_SS controller design assumes the OCP clock is
- + 	 * at least 6x faster than the ADC clock.
- + 	 */
- + 	clk = clk_get(&pdev->dev, "adc_tsc_fck");
- + 	if (IS_ERR(clk)) {
- + 		dev_err(&pdev->dev, "failed to get TSC fck\n");
- + 		err = PTR_ERR(clk);
- + 		goto err_fail;
- + 	}
- + 	clock_rate = clk_get_rate(clk);
- + 	clk_put(clk);
- + 	clk_value = clock_rate / ADC_CLK;
- + 	/* TSCADC_CLKDIV needs to be configured to the value minus 1 */
- + 	clk_value = clk_value - 1;
- + 	tscadc_writel(tscadc, TSCADC_REG_CLKDIV, clk_value);
- + 
- + 	/* Set the control register bits */
- + 	ctrl = TSCADC_CNTRLREG_STEPCONFIGWRT |
- + 			TSCADC_CNTRLREG_STEPID;
- + 	if (pdata->tsc_init)
- + 		ctrl |= TSCADC_CNTRLREG_4WIRE |
- + 				TSCADC_CNTRLREG_TSCENB;
- + 	tscadc_writel(tscadc, TSCADC_REG_CTRL, ctrl);
- + 
- + 	/* Set register bits for Idle Config Mode */
- + 	if (pdata->tsc_init)
- + 		tscadc_idle_config(tscadc);
- + 
- + 	/* Enable the TSC module enable bit */
- + 	ctrl = tscadc_readl(tscadc, TSCADC_REG_CTRL);
- + 	ctrl |= TSCADC_CNTRLREG_TSCSSENB;
- + 	tscadc_writel(tscadc, TSCADC_REG_CTRL, ctrl);
- + 
- + 	/* TSC Cell */
- + 	if (pdata->tsc_init) {
- + 		cell = &tscadc->cells[children];
- + 		cell->name = "tsc";
- + 		cell->platform_data = tscadc;
- + 		cell->pdata_size = sizeof(*tscadc);
- + 		children++;
- + 	}
- + 
- + 	/* ADC Cell */
- + 	if (pdata->adc_init) {
- + 		cell = &tscadc->cells[children];
- + 		cell->name = "tiadc";
- + 		cell->platform_data = tscadc;
- + 		cell->pdata_size = sizeof(*tscadc);
- + 		children++;
- + 	}
- + 
- + 	err = mfd_add_devices(&pdev->dev, pdev->id, tscadc->cells,
- + 			children, NULL, 0);
- + 	if (err < 0)
- + 		goto err_fail;
- + 
- + 	device_init_wakeup(&pdev->dev, true);
- + 	platform_set_drvdata(pdev, tscadc);
- + 	return 0;
- + 
- + err_fail:
- + 	pm_runtime_put_sync(&pdev->dev);
- + 	pm_runtime_disable(&pdev->dev);
- + 	iounmap(tscadc->tscadc_base);
- + err_release_mem:
- + 	release_mem_region(res->start, resource_size(res));
- + 	mfd_remove_devices(tscadc->dev);
- + err_free_mem:
- + 	platform_set_drvdata(pdev, NULL);
- + 	kfree(tscadc);
- + 	return err;
- + }
- + 
- + static int __devexit ti_tscadc_remove(struct platform_device *pdev)
- + {
- + 	struct ti_tscadc_dev	*tscadc = platform_get_drvdata(pdev);
- + 	struct resource		*res;
- + 
- + 	tscadc_writel(tscadc, TSCADC_REG_SE, 0x00);
- + 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- + 	iounmap(tscadc->tscadc_base);
- + 	release_mem_region(res->start, resource_size(res));
- + 
- + 	pm_runtime_put_sync(&pdev->dev);
- + 	pm_runtime_disable(&pdev->dev);
- + 
- + 	mfd_remove_devices(tscadc->dev);
- + 	kfree(tscadc);
- + 
- + 	platform_set_drvdata(pdev, NULL);
- + 	return 0;
- + }
- + 
- + static int tscadc_suspend(struct platform_device *pdev, pm_message_t state)
- + {
- + 	struct ti_tscadc_dev	*tscadc_dev = platform_get_drvdata(pdev);
- + 
- + 	tscadc_writel(tscadc_dev, TSCADC_REG_SE, 0x00);
- + 	tscadc_dev->irqstat = tscadc_readl(tscadc_dev, TSCADC_REG_IRQENABLE);
- + 	tscadc_dev->ctrl = tscadc_readl(tscadc_dev, TSCADC_REG_CTRL);
- + 	pm_runtime_put_sync(&pdev->dev);
- + 	return 0;
- + }
- + 
- + static int tscadc_resume(struct platform_device *pdev)
- + {
- + 	struct ti_tscadc_dev	*tscadc_dev = platform_get_drvdata(pdev);
- + 	struct mfd_tscadc_board	*pdata = pdev->dev.platform_data;
- + 	unsigned int irq_read;
- + 
- + 	pm_runtime_get_sync(&pdev->dev);
- + 
- + 	/* context restore */
- + 	irq_read = tscadc_readl(tscadc_dev, TSCADC_REG_IRQSTATUS);
- + 	tscadc_writel(tscadc_dev, TSCADC_REG_IRQSTATUS, irq_read);
- + 
- + 	tscadc_writel(tscadc_dev, TSCADC_REG_IRQENABLE, tscadc_dev->irqstat);
- + 	if (pdata->tsc_init)
- + 		tscadc_idle_config(tscadc_dev);
- + 	tscadc_writel(tscadc_dev, TSCADC_REG_SE, TSCADC_STPENB_STEPENB_TC);
- + 	tscadc_writel(tscadc_dev, TSCADC_REG_CTRL, tscadc_dev->ctrl);
- + 	return 0;
- + }
- + 
- + static struct platform_driver ti_tscadc_driver = {
- + 	.driver = {
- + 		.name   = "ti_tscadc",
- + 		.owner	= THIS_MODULE,
- + 	},
- + 	.probe	= ti_tscadc_probe,
- + 	.remove	= __devexit_p(ti_tscadc_remove),
- + 	.suspend = tscadc_suspend,
- + 	.resume = tscadc_resume,
- + };
- + 
- + module_platform_driver(ti_tscadc_driver);
- + 
- + MODULE_DESCRIPTION("TI touchscreen / ADC MFD controller driver");
- + MODULE_AUTHOR("Rachna Patil <rachna@ti.com>");
- + MODULE_LICENSE("GPL");
- diff -crN linux-3.2.1_o/drivers/mfd/tps65217.c linux-3.2.1/drivers/mfd/tps65217.c
- *** linux-3.2.1_o/drivers/mfd/tps65217.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/drivers/mfd/tps65217.c	2014-05-15 13:25:14.436019220 +0900
- ***************
- *** 0 ****
- --- 1,253 ----
- + /*
- +  * tps65217.c
- +  *
- +  * TPS65217 chip family multi-function driver
- +  *
- +  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #include <linux/kernel.h>
- + #include <linux/device.h>
- + #include <linux/module.h>
- + #include <linux/platform_device.h>
- + #include <linux/init.h>
- + #include <linux/i2c.h>
- + #include <linux/slab.h>
- + #include <linux/regmap.h>
- + #include <linux/err.h>
- + 
- + #include <linux/mfd/core.h>
- + #include <linux/mfd/tps65217.h>
- + 
- + /**
- +  * tps65217_reg_read: Read a single tps65217 register.
- +  *
- +  * @tps: Device to read from.
- +  * @reg: Register to read.
- +  * @val: Contians the value
- +  */
- + int tps65217_reg_read(struct tps65217 *tps, unsigned int reg,
- + 			unsigned int *val)
- + {
- + 	return regmap_read(tps->regmap, reg, val);
- + }
- + EXPORT_SYMBOL_GPL(tps65217_reg_read);
- + 
- + /**
- +  * tps65217_reg_write: Write a single tps65217 register.
- +  *
- +  * @tps65217: Device to write to.
- +  * @reg: Register to write to.
- +  * @val: Value to write.
- +  * @level: Password protected level
- +  */
- + int tps65217_reg_write(struct tps65217 *tps, unsigned int reg,
- + 			unsigned int val, unsigned int level)
- + {
- + 	int ret;
- + 	unsigned int xor_reg_val;
- + 
- + 	switch (level) {
- + 	case TPS65217_PROTECT_NONE:
- + 		return regmap_write(tps->regmap, reg, val);
- + 	case TPS65217_PROTECT_L1:
- + 		xor_reg_val = reg ^ TPS65217_PASSWORD_REGS_UNLOCK;
- + 		ret = regmap_write(tps->regmap, TPS65217_REG_PASSWORD,
- + 							xor_reg_val);
- + 		if (ret < 0)
- + 			return ret;
- + 
- + 		return regmap_write(tps->regmap, reg, val);
- + 	case TPS65217_PROTECT_L2:
- + 		xor_reg_val = reg ^ TPS65217_PASSWORD_REGS_UNLOCK;
- + 		ret = regmap_write(tps->regmap, TPS65217_REG_PASSWORD,
- + 							xor_reg_val);
- + 		if (ret < 0)
- + 			return ret;
- + 		ret = regmap_write(tps->regmap, reg, val);
- + 		if (ret < 0)
- + 			return ret;
- + 		ret = regmap_write(tps->regmap, TPS65217_REG_PASSWORD,
- + 							xor_reg_val);
- + 		if (ret < 0)
- + 			return ret;
- + 		return regmap_write(tps->regmap, reg, val);
- + 	default:
- + 		return -EINVAL;
- + 	}
- + }
- + EXPORT_SYMBOL_GPL(tps65217_reg_write);
- + 
- + /**
- +  * tps65217_update_bits: Modify bits w.r.t mask, val and level.
- +  *
- +  * @tps65217: Device to write to.
- +  * @reg: Register to read-write to.
- +  * @mask: Mask.
- +  * @val: Value to write.
- +  * @level: Password protected level
- +  */
- + int tps65217_update_bits(struct tps65217 *tps, unsigned int reg,
- + 		unsigned int mask, unsigned int val, unsigned int level)
- + {
- + 	int ret;
- + 	unsigned int data;
- + 
- + 	ret = tps65217_reg_read(tps, reg, &data);
- + 	if (ret) {
- + 		dev_err(tps->dev, "Read from reg 0x%x failed\n", reg);
- + 		return ret;
- + 	}
- + 
- + 	data &= ~mask;
- + 	data |= val & mask;
- + 
- + 	ret = tps65217_reg_write(tps, reg, data, level);
- + 	if (ret)
- + 		dev_err(tps->dev, "Write for reg 0x%x failed\n", reg);
- + 
- + 	return ret;
- + }
- + 
- + int tps65217_set_bits(struct tps65217 *tps, unsigned int reg,
- + 		unsigned int mask, unsigned int val, unsigned int level)
- + {
- + 	return tps65217_update_bits(tps, reg, mask, val, level);
- + }
- + EXPORT_SYMBOL_GPL(tps65217_set_bits);
- + 
- + int tps65217_clear_bits(struct tps65217 *tps, unsigned int reg,
- + 		unsigned int mask, unsigned int level)
- + {
- + 	return tps65217_update_bits(tps, reg, mask, 0, level);
- + }
- + EXPORT_SYMBOL_GPL(tps65217_clear_bits);
- + 
- + static struct regmap_config tps65217_regmap_config = {
- + 	.reg_bits = 8,
- + 	.val_bits = 8,
- + };
- + 
- + static int __devinit tps65217_probe(struct i2c_client *client,
- + 				const struct i2c_device_id *ids)
- + {
- + 	struct tps65217 *tps;
- + 	struct tps65217_board *pdata = client->dev.platform_data;
- + 	int i, ret;
- + 	unsigned int version;
- + 
- + 	tps = devm_kzalloc(&client->dev, sizeof(*tps), GFP_KERNEL);
- + 	if (!tps)
- + 		return -ENOMEM;
- + 
- + 	tps->pdata = pdata;
- + 	tps->regmap = regmap_init_i2c(client, &tps65217_regmap_config);
- + 	if (IS_ERR(tps->regmap)) {
- + 		ret = PTR_ERR(tps->regmap);
- + 		dev_err(tps->dev, "Failed to allocate register map: %d\n",
- + 			ret);
- + 		return ret;
- + 	}
- + 
- + 	i2c_set_clientdata(client, tps);
- + 	tps->dev = &client->dev;
- + 
- + 	ret = tps65217_reg_read(tps, TPS65217_REG_CHIPID, &version);
- + 	if (ret < 0) {
- + 		dev_err(tps->dev, "Failed to read revision"
- + 					" register: %d\n", ret);
- + 		goto err_regmap;
- + 	}
- + 
- + 	/* Set the PMIC to shutdown on PWR_EN toggle */
- + 	if (pdata->status_off) {
- + 		ret = tps65217_set_bits(tps, TPS65217_REG_STATUS,
- + 				TPS65217_STATUS_OFF, TPS65217_STATUS_OFF,
- + 				TPS65217_PROTECT_NONE);
- + 		if (ret) {
- + 			dev_err(tps->dev, "Failed to set the status OFF\n");
- + 			goto err_regmap;
- + 		}
- + 	}
- + 
- + 	dev_info(tps->dev, "TPS65217 ID %#x version 1.%d\n",
- + 			(version & TPS65217_CHIPID_CHIP_MASK) >> 4,
- + 			version & TPS65217_CHIPID_REV_MASK);
- + 
- + 	for (i = 0; i < TPS65217_NUM_REGULATOR; i++) {
- + 		struct platform_device *pdev;
- + 
- + 		pdev = platform_device_alloc("tps65217-pmic", i);
- + 		if (!pdev) {
- + 			dev_err(tps->dev, "Cannot create regulator %d\n", i);
- + 			continue;
- + 		}
- + 
- + 		pdev->dev.parent = tps->dev;
- + 		platform_device_add_data(pdev, &pdata->tps65217_init_data[i],
- + 					sizeof(pdata->tps65217_init_data[i]));
- + 		tps->regulator_pdev[i] = pdev;
- + 
- + 		platform_device_add(pdev);
- + 	}
- + 
- + 	return 0;
- + 
- + err_regmap:
- + 	regmap_exit(tps->regmap);
- + 
- + 	return ret;
- + }
- + 
- + static int __devexit tps65217_remove(struct i2c_client *client)
- + {
- + 	struct tps65217 *tps = i2c_get_clientdata(client);
- + 	int i;
- + 
- + 	for (i = 0; i < TPS65217_NUM_REGULATOR; i++)
- + 		platform_device_unregister(tps->regulator_pdev[i]);
- + 
- + 	regmap_exit(tps->regmap);
- + 
- + 	return 0;
- + }
- + 
- + static const struct i2c_device_id tps65217_id_table[] = {
- + 	{"tps65217", 0xF0},
- + 	{/* end of list */}
- + };
- + MODULE_DEVICE_TABLE(i2c, tps65217_id_table);
- + 
- + static struct i2c_driver tps65217_driver = {
- + 	.driver		= {
- + 		.name	= "tps65217",
- + 	},
- + 	.id_table	= tps65217_id_table,
- + 	.probe		= tps65217_probe,
- + 	.remove		= __devexit_p(tps65217_remove),
- + };
- + 
- + static int __init tps65217_init(void)
- + {
- + 	return i2c_add_driver(&tps65217_driver);
- + }
- + subsys_initcall(tps65217_init);
- + 
- + static void __exit tps65217_exit(void)
- + {
- + 	i2c_del_driver(&tps65217_driver);
- + }
- + module_exit(tps65217_exit);
- + 
- + MODULE_AUTHOR("AnilKumar Ch <anilkumar@ti.com>");
- + MODULE_DESCRIPTION("TPS65217 chip family multi-function driver");
- + MODULE_LICENSE("GPL v2");
- diff -crN linux-3.2.1_o/drivers/misc/eeprom/at24.c linux-3.2.1/drivers/misc/eeprom/at24.c
- *** linux-3.2.1_o/drivers/misc/eeprom/at24.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/misc/eeprom/at24.c	2014-05-15 13:25:14.436019220 +0900
- ***************
- *** 662,667 ****
- --- 662,671 ----
-   	int i;
-   
-   	at24 = i2c_get_clientdata(client);
- + #ifdef CONFIG_MACH_CKB_3352
- + 	if(at24->chip.unload)
- + 		at24->chip.unload();
- + #endif
-   	sysfs_remove_bin_file(&client->dev.kobj, &at24->bin);
-   
-   	for (i = 1; i < at24->num_addresses; i++)
- diff -crN linux-3.2.1_o/drivers/mmc/card/block.c linux-3.2.1/drivers/mmc/card/block.c
- *** linux-3.2.1_o/drivers/mmc/card/block.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/mmc/card/block.c	2014-05-15 13:25:14.448249920 +0900
- ***************
- *** 119,124 ****
- --- 119,125 ----
-   	MMC_BLK_ABORT,
-   	MMC_BLK_DATA_ERR,
-   	MMC_BLK_ECC_ERR,
- + 	MMC_BLK_NOMEDIUM,
-   };
-   
-   module_param(perdev_minors, int, 0444);
- ***************
- *** 565,570 ****
- --- 566,572 ----
-   	return err;
-   }
-   
- + #define ERR_NOMEDIUM	3
-   #define ERR_RETRY	2
-   #define ERR_ABORT	1
-   #define ERR_CONTINUE	0
- ***************
- *** 632,637 ****
- --- 634,642 ----
-   	u32 status, stop_status = 0;
-   	int err, retry;
-   
- + 	if (mmc_card_removed(card))
- + 		return ERR_NOMEDIUM;
- + 
-   	/*
-   	 * Try to get card status which indicates both the card state
-   	 * and why there was no response.  If the first attempt fails,
- ***************
- *** 648,655 ****
-   	}
-   
-   	/* We couldn't get a response from the card.  Give up. */
- ! 	if (err)
-   		return ERR_ABORT;
-   
-   	/* Flag ECC errors */
-   	if ((status & R1_CARD_ECC_FAILED) ||
- --- 653,664 ----
-   	}
-   
-   	/* We couldn't get a response from the card.  Give up. */
- ! 	if (err) {
- ! 		/* Check if the card is removed */
- ! 		if (mmc_detect_card_removed(card->host))
- ! 			return ERR_NOMEDIUM;
-   		return ERR_ABORT;
- + 	}
-   
-   	/* Flag ECC errors */
-   	if ((status & R1_CARD_ECC_FAILED) ||
- ***************
- *** 922,927 ****
- --- 931,938 ----
-   			return MMC_BLK_RETRY;
-   		case ERR_ABORT:
-   			return MMC_BLK_ABORT;
- + 		case ERR_NOMEDIUM:
- + 			return MMC_BLK_NOMEDIUM;
-   		case ERR_CONTINUE:
-   			break;
-   		}
- ***************
- *** 1255,1260 ****
- --- 1266,1273 ----
-   			if (!ret)
-   				goto start_new_req;
-   			break;
- + 		case MMC_BLK_NOMEDIUM:
- + 			goto cmd_abort;
-   		}
-   
-   		if (ret) {
- ***************
- *** 1271,1276 ****
- --- 1284,1291 ----
-   
-    cmd_abort:
-   	spin_lock_irq(&md->lock);
- + 	if (mmc_card_removed(card))
- + 		req->cmd_flags |= REQ_QUIET;
-   	while (ret)
-   		ret = __blk_end_request(req, -EIO, blk_rq_cur_bytes(req));
-   	spin_unlock_irq(&md->lock);
- ***************
- *** 1677,1683 ****
-   }
-   
-   #ifdef CONFIG_PM
- ! static int mmc_blk_suspend(struct mmc_card *card, pm_message_t state)
-   {
-   	struct mmc_blk_data *part_md;
-   	struct mmc_blk_data *md = mmc_get_drvdata(card);
- --- 1692,1698 ----
-   }
-   
-   #ifdef CONFIG_PM
- ! static int mmc_blk_suspend(struct mmc_card *card)
-   {
-   	struct mmc_blk_data *part_md;
-   	struct mmc_blk_data *md = mmc_get_drvdata(card);
- diff -crN linux-3.2.1_o/drivers/mmc/card/queue.c linux-3.2.1/drivers/mmc/card/queue.c
- *** linux-3.2.1_o/drivers/mmc/card/queue.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/mmc/card/queue.c	2014-05-15 13:25:14.455882359 +0900
- ***************
- *** 29,34 ****
- --- 29,36 ----
-    */
-   static int mmc_prep_request(struct request_queue *q, struct request *req)
-   {
- + 	struct mmc_queue *mq = q->queuedata;
- + 
-   	/*
-   	 * We only like normal block requests and discards.
-   	 */
- ***************
- *** 37,42 ****
- --- 39,47 ----
-   		return BLKPREP_KILL;
-   	}
-   
- + 	if (mq && mmc_card_removed(mq->card))
- + 		return BLKPREP_KILL;
- + 
-   	req->cmd_flags |= REQ_DONTPREP;
-   
-   	return BLKPREP_OK;
- diff -crN linux-3.2.1_o/drivers/mmc/core/bus.c linux-3.2.1/drivers/mmc/core/bus.c
- *** linux-3.2.1_o/drivers/mmc/core/bus.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/mmc/core/bus.c	2014-05-15 13:25:14.482722353 +0900
- ***************
- *** 122,135 ****
-   	return 0;
-   }
-   
- ! static int mmc_bus_suspend(struct device *dev, pm_message_t state)
-   {
-   	struct mmc_driver *drv = to_mmc_driver(dev->driver);
-   	struct mmc_card *card = mmc_dev_to_card(dev);
-   	int ret = 0;
-   
-   	if (dev->driver && drv->suspend)
- ! 		ret = drv->suspend(card, state);
-   	return ret;
-   }
-   
- --- 122,135 ----
-   	return 0;
-   }
-   
- ! static int mmc_bus_suspend(struct device *dev)
-   {
-   	struct mmc_driver *drv = to_mmc_driver(dev->driver);
-   	struct mmc_card *card = mmc_dev_to_card(dev);
-   	int ret = 0;
-   
-   	if (dev->driver && drv->suspend)
- ! 		ret = drv->suspend(card);
-   	return ret;
-   }
-   
- ***************
- *** 165,184 ****
-   	return pm_runtime_suspend(dev);
-   }
-   
-   static const struct dev_pm_ops mmc_bus_pm_ops = {
-   	.runtime_suspend	= mmc_runtime_suspend,
-   	.runtime_resume		= mmc_runtime_resume,
-   	.runtime_idle		= mmc_runtime_idle,
-   };
-   
- - #define MMC_PM_OPS_PTR	(&mmc_bus_pm_ops)
- - 
- - #else /* !CONFIG_PM_RUNTIME */
- - 
- - #define MMC_PM_OPS_PTR	NULL
- - 
- - #endif /* !CONFIG_PM_RUNTIME */
- - 
-   static struct bus_type mmc_bus_type = {
-   	.name		= "mmc",
-   	.dev_attrs	= mmc_dev_attrs,
- --- 165,184 ----
-   	return pm_runtime_suspend(dev);
-   }
-   
- + #else /* !CONFIG_PM_RUNTIME */
- + #define mmc_runtime_suspend	NULL
- + #define mmc_runtime_resume	NULL
- + #define mmc_runtime_idle	NULL
- + #endif /* !CONFIG_PM_RUNTIME */
- + 
-   static const struct dev_pm_ops mmc_bus_pm_ops = {
-   	.runtime_suspend	= mmc_runtime_suspend,
-   	.runtime_resume		= mmc_runtime_resume,
-   	.runtime_idle		= mmc_runtime_idle,
- + 	.suspend		= mmc_bus_suspend,
- + 	.resume			= mmc_bus_resume,
-   };
-   
-   static struct bus_type mmc_bus_type = {
-   	.name		= "mmc",
-   	.dev_attrs	= mmc_dev_attrs,
- ***************
- *** 186,194 ****
-   	.uevent		= mmc_bus_uevent,
-   	.probe		= mmc_bus_probe,
-   	.remove		= mmc_bus_remove,
- ! 	.suspend	= mmc_bus_suspend,
- ! 	.resume		= mmc_bus_resume,
- ! 	.pm		= MMC_PM_OPS_PTR,
-   };
-   
-   int mmc_register_bus(void)
- --- 186,192 ----
-   	.uevent		= mmc_bus_uevent,
-   	.probe		= mmc_bus_probe,
-   	.remove		= mmc_bus_remove,
- ! 	.pm		= &mmc_bus_pm_ops,
-   };
-   
-   int mmc_register_bus(void)
- diff -crN linux-3.2.1_o/drivers/mmc/core/core.c linux-3.2.1/drivers/mmc/core/core.c
- *** linux-3.2.1_o/drivers/mmc/core/core.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/mmc/core/core.c	2014-05-15 13:25:14.547023668 +0900
- ***************
- *** 140,146 ****
-   			cmd->retries = 0;
-   	}
-   
- ! 	if (err && cmd->retries) {
-   		/*
-   		 * Request starter must handle retries - see
-   		 * mmc_wait_for_req_done().
- --- 140,146 ----
-   			cmd->retries = 0;
-   	}
-   
- ! 	if (err && cmd->retries && !mmc_card_removed(host->card)) {
-   		/*
-   		 * Request starter must handle retries - see
-   		 * mmc_wait_for_req_done().
- ***************
- *** 208,214 ****
-   	}
-   
-   	WARN_ON(!host->claimed);
- - 
-   	mrq->cmd->error = 0;
-   	mrq->cmd->mrq = mrq;
-   	if (mrq->data) {
- --- 208,213 ----
- ***************
- *** 243,253 ****
-   	complete(&mrq->completion);
-   }
-   
- ! static void __mmc_start_req(struct mmc_host *host, struct mmc_request *mrq)
-   {
-   	init_completion(&mrq->completion);
-   	mrq->done = mmc_wait_done;
-   	mmc_start_request(host, mrq);
-   }
-   
-   static void mmc_wait_for_req_done(struct mmc_host *host,
- --- 242,258 ----
-   	complete(&mrq->completion);
-   }
-   
- ! static int __mmc_start_req(struct mmc_host *host, struct mmc_request *mrq)
-   {
-   	init_completion(&mrq->completion);
-   	mrq->done = mmc_wait_done;
- + 	if (mmc_card_removed(host->card)) {
- + 		mrq->cmd->error = -ENOMEDIUM;
- + 		complete(&mrq->completion);
- + 		return -ENOMEDIUM;
- + 	}
-   	mmc_start_request(host, mrq);
- + 	return 0;
-   }
-   
-   static void mmc_wait_for_req_done(struct mmc_host *host,
- ***************
- *** 259,265 ****
-   		wait_for_completion(&mrq->completion);
-   
-   		cmd = mrq->cmd;
- ! 		if (!cmd->error || !cmd->retries)
-   			break;
-   
-   		pr_debug("%s: req failed (CMD%u): %d, retrying...\n",
- --- 264,271 ----
-   		wait_for_completion(&mrq->completion);
-   
-   		cmd = mrq->cmd;
- ! 		if (!cmd->error || !cmd->retries ||
- ! 		    mmc_card_removed(host->card))
-   			break;
-   
-   		pr_debug("%s: req failed (CMD%u): %d, retrying...\n",
- ***************
- *** 324,329 ****
- --- 330,336 ----
-   				    struct mmc_async_req *areq, int *error)
-   {
-   	int err = 0;
- + 	int start_err = 0;
-   	struct mmc_async_req *data = host->areq;
-   
-   	/* Prepare a new request */
- ***************
- *** 333,362 ****
-   	if (host->areq) {
-   		mmc_wait_for_req_done(host, host->areq->mrq);
-   		err = host->areq->err_check(host->card, host->areq);
- - 		if (err) {
- - 			/* post process the completed failed request */
- - 			mmc_post_req(host, host->areq->mrq, 0);
- - 			if (areq)
- - 				/*
- - 				 * Cancel the new prepared request, because
- - 				 * it can't run until the failed
- - 				 * request has been properly handled.
- - 				 */
- - 				mmc_post_req(host, areq->mrq, -EINVAL);
- - 
- - 			host->areq = NULL;
- - 			goto out;
- - 		}
-   	}
-   
- ! 	if (areq)
- ! 		__mmc_start_req(host, areq->mrq);
-   
-   	if (host->areq)
-   		mmc_post_req(host, host->areq->mrq, 0);
-   
- ! 	host->areq = areq;
- !  out:
-   	if (error)
-   		*error = err;
-   	return data;
- --- 340,362 ----
-   	if (host->areq) {
-   		mmc_wait_for_req_done(host, host->areq->mrq);
-   		err = host->areq->err_check(host->card, host->areq);
-   	}
-   
- ! 	if (!err && areq)
- ! 		start_err = __mmc_start_req(host, areq->mrq);
-   
-   	if (host->areq)
-   		mmc_post_req(host, host->areq->mrq, 0);
-   
- ! 	 /* Cancel a prepared request if it was not started. */
- ! 	if ((err || start_err) && areq)
- ! 			mmc_post_req(host, areq->mrq, -EINVAL);
- ! 
- ! 	if (err)
- ! 		host->areq = NULL;
- ! 	else
- ! 		host->areq = areq;
- ! 
-   	if (error)
-   		*error = err;
-   	return data;
- ***************
- *** 834,839 ****
- --- 834,841 ----
-   
-   EXPORT_SYMBOL(mmc_release_host);
-   
- + volatile struct mmc_host *vagi;
- + volatile struct mmc_ios *anu;
-   /*
-    * Internal function that does the actual ios call to the host driver,
-    * optionally printing some debug output.
- ***************
- *** 841,847 ****
-   static inline void mmc_set_ios(struct mmc_host *host)
-   {
-   	struct mmc_ios *ios = &host->ios;
- ! 
-   	pr_debug("%s: clock %uHz busmode %u powermode %u cs %u Vdd %u "
-   		"width %u timing %u\n",
-   		 mmc_hostname(host), ios->clock, ios->bus_mode,
- --- 843,850 ----
-   static inline void mmc_set_ios(struct mmc_host *host)
-   {
-   	struct mmc_ios *ios = &host->ios;
- ! 	vagi = host;
- ! 	anu = ios;
-   	pr_debug("%s: clock %uHz busmode %u powermode %u cs %u Vdd %u "
-   		"width %u timing %u\n",
-   		 mmc_hostname(host), ios->clock, ios->bus_mode,
- ***************
- *** 1456,1462 ****
-   	WARN_ON(host->removed);
-   	spin_unlock_irqrestore(&host->lock, flags);
-   #endif
- ! 
-   	mmc_schedule_delayed_work(&host->detect, delay);
-   }
-   
- --- 1459,1465 ----
-   	WARN_ON(host->removed);
-   	spin_unlock_irqrestore(&host->lock, flags);
-   #endif
- ! 	host->detect_change = 1;
-   	mmc_schedule_delayed_work(&host->detect, delay);
-   }
-   
- ***************
- *** 2049,2054 ****
- --- 2052,2112 ----
-   	return -EIO;
-   }
-   
- + int _mmc_detect_card_removed(struct mmc_host *host)
- + {
- + 	int ret;
- + 
- + 	if ((host->caps & MMC_CAP_NONREMOVABLE) || !host->bus_ops->alive)
- + 		return 0;
- + 
- + 	if (!host->card || mmc_card_removed(host->card))
- + 		return 1;
- + 
- + 	ret = host->bus_ops->alive(host);
- + 	if (ret) {
- + 		mmc_card_set_removed(host->card);
- + 		pr_debug("%s: card remove detected\n", mmc_hostname(host));
- + 	}
- + 
- + 	return ret;
- + }
- + 
- + int mmc_detect_card_removed(struct mmc_host *host)
- + {
- + 	struct mmc_card *card = host->card;
- + 	int ret;
- + 
- + 	WARN_ON(!host->claimed);
- + 
- + 	if (!card)
- + 		return 1;
- + 
- + 	ret = mmc_card_removed(card);
- + 	/*
- + 	 * The card will be considered unchanged unless we have been asked to
- + 	 * detect a change or host requires polling to provide card detection.
- + 	 */
- + 	if (!host->detect_change && !(host->caps & MMC_CAP_NEEDS_POLL) &&
- + 	    !(host->caps2 & MMC_CAP2_DETECT_ON_ERR))
- + 		return ret;
- + 
- + 	host->detect_change = 0;
- + 	if (!ret) {
- + 		ret = _mmc_detect_card_removed(host);
- + 		if (ret && (host->caps2 & MMC_CAP2_DETECT_ON_ERR)) {
- + 			/*
- + 			 * Schedule a detect work as soon as possible to let a
- + 			 * rescan handle the card removal.
- + 			 */
- + 			cancel_delayed_work(&host->detect);
- + 			mmc_detect_change(host, 0);
- + 		}
- + 	}
- + 
- + 	return ret;
- + }
- + EXPORT_SYMBOL(mmc_detect_card_removed);
- + 
-   void mmc_rescan(struct work_struct *work)
-   {
-   	static const unsigned freqs[] = { 400000, 300000, 200000, 100000 };
- ***************
- *** 2069,2074 ****
- --- 2127,2134 ----
-   	    && !(host->caps & MMC_CAP_NONREMOVABLE))
-   		host->bus_ops->detect(host);
-   
- + 	host->detect_change = 0;
- + 
-   	/*
-   	 * Let mmc_bus_put() free the bus/bus_ops if we've found that
-   	 * the card is no longer present.
- diff -crN linux-3.2.1_o/drivers/mmc/core/core.h linux-3.2.1/drivers/mmc/core/core.h
- *** linux-3.2.1_o/drivers/mmc/core/core.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/mmc/core/core.h	2014-05-15 13:25:14.551208071 +0900
- ***************
- *** 24,29 ****
- --- 24,30 ----
-   	int (*resume)(struct mmc_host *);
-   	int (*power_save)(struct mmc_host *);
-   	int (*power_restore)(struct mmc_host *);
- + 	int (*alive)(struct mmc_host *);
-   };
-   
-   void mmc_attach_bus(struct mmc_host *host, const struct mmc_bus_ops *ops);
- ***************
- *** 59,64 ****
- --- 60,67 ----
-   void mmc_start_host(struct mmc_host *host);
-   void mmc_stop_host(struct mmc_host *host);
-   
- + int _mmc_detect_card_removed(struct mmc_host *host);
- + 
-   int mmc_attach_mmc(struct mmc_host *host);
-   int mmc_attach_sd(struct mmc_host *host);
-   int mmc_attach_sdio(struct mmc_host *host);
- diff -crN linux-3.2.1_o/drivers/mmc/core/mmc.c linux-3.2.1/drivers/mmc/core/mmc.c
- *** linux-3.2.1_o/drivers/mmc/core/mmc.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/mmc/core/mmc.c	2014-05-15 13:25:14.555213815 +0900
- ***************
- *** 1105,1110 ****
- --- 1105,1118 ----
-   }
-   
-   /*
- +  * Card detection - card is alive.
- +  */
- + static int mmc_alive(struct mmc_host *host)
- + {
- + 	return mmc_send_status(host->card, NULL);
- + }
- + 
- + /*
-    * Card detection callback from host.
-    */
-   static void mmc_detect(struct mmc_host *host)
- ***************
- *** 1119,1125 ****
-   	/*
-   	 * Just check if our card has been removed.
-   	 */
- ! 	err = mmc_send_status(host->card, NULL);
-   
-   	mmc_release_host(host);
-   
- --- 1127,1133 ----
-   	/*
-   	 * Just check if our card has been removed.
-   	 */
- ! 	err = _mmc_detect_card_removed(host);
-   
-   	mmc_release_host(host);
-   
- ***************
- *** 1224,1229 ****
- --- 1232,1238 ----
-   	.suspend = NULL,
-   	.resume = NULL,
-   	.power_restore = mmc_power_restore,
- + 	.alive = mmc_alive,
-   };
-   
-   static const struct mmc_bus_ops mmc_ops_unsafe = {
- ***************
- *** 1234,1239 ****
- --- 1243,1249 ----
-   	.suspend = mmc_suspend,
-   	.resume = mmc_resume,
-   	.power_restore = mmc_power_restore,
- + 	.alive = mmc_alive,
-   };
-   
-   static void mmc_attach_bus_ops(struct mmc_host *host)
- diff -crN linux-3.2.1_o/drivers/mmc/core/sd.c linux-3.2.1/drivers/mmc/core/sd.c
- *** linux-3.2.1_o/drivers/mmc/core/sd.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/mmc/core/sd.c	2014-05-15 13:25:14.559211528 +0900
- ***************
- *** 1019,1024 ****
- --- 1019,1032 ----
-   }
-   
-   /*
- +  * Card detection - card is alive.
- +  */
- + static int mmc_sd_alive(struct mmc_host *host)
- + {
- + 	return mmc_send_status(host->card, NULL);
- + }
- + 
- + /*
-    * Card detection callback from host.
-    */
-   static void mmc_sd_detect(struct mmc_host *host)
- ***************
- *** 1033,1039 ****
-   	/*
-   	 * Just check if our card has been removed.
-   	 */
- ! 	err = mmc_send_status(host->card, NULL);
-   
-   	mmc_release_host(host);
-   
- --- 1041,1047 ----
-   	/*
-   	 * Just check if our card has been removed.
-   	 */
- ! 	err = _mmc_detect_card_removed(host);
-   
-   	mmc_release_host(host);
-   
- ***************
- *** 1102,1107 ****
- --- 1110,1116 ----
-   	.suspend = NULL,
-   	.resume = NULL,
-   	.power_restore = mmc_sd_power_restore,
- + 	.alive = mmc_sd_alive,
-   };
-   
-   static const struct mmc_bus_ops mmc_sd_ops_unsafe = {
- ***************
- *** 1110,1115 ****
- --- 1119,1125 ----
-   	.suspend = mmc_sd_suspend,
-   	.resume = mmc_sd_resume,
-   	.power_restore = mmc_sd_power_restore,
- + 	.alive = mmc_sd_alive,
-   };
-   
-   static void mmc_sd_attach_bus_ops(struct mmc_host *host)
- diff -crN linux-3.2.1_o/drivers/mmc/core/sdio.c linux-3.2.1/drivers/mmc/core/sdio.c
- *** linux-3.2.1_o/drivers/mmc/core/sdio.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/mmc/core/sdio.c	2014-05-15 13:25:14.562598385 +0900
- ***************
- *** 550,555 ****
- --- 550,563 ----
-   }
-   
-   /*
- +  * Card detection - card is alive.
- +  */
- + static int mmc_sdio_alive(struct mmc_host *host)
- + {
- + 	return mmc_select_card(host->card);
- + }
- + 
- + /*
-    * Card detection callback from host.
-    */
-   static void mmc_sdio_detect(struct mmc_host *host)
- ***************
- *** 571,577 ****
-   	/*
-   	 * Just check if our card has been removed.
-   	 */
- ! 	err = mmc_select_card(host->card);
-   
-   	mmc_release_host(host);
-   
- --- 579,585 ----
-   	/*
-   	 * Just check if our card has been removed.
-   	 */
- ! 	err = _mmc_detect_card_removed(host);
-   
-   	mmc_release_host(host);
-   
- ***************
- *** 749,754 ****
- --- 757,763 ----
-   	.suspend = mmc_sdio_suspend,
-   	.resume = mmc_sdio_resume,
-   	.power_restore = mmc_sdio_power_restore,
- + 	.alive = mmc_sdio_alive,
-   };
-   
-   
- diff -crN linux-3.2.1_o/drivers/mmc/host/Kconfig linux-3.2.1/drivers/mmc/host/Kconfig
- *** linux-3.2.1_o/drivers/mmc/host/Kconfig	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/mmc/host/Kconfig	2014-05-15 13:25:14.567227749 +0900
- ***************
- *** 231,237 ****
-   
-   config MMC_OMAP
-   	tristate "TI OMAP Multimedia Card Interface support"
- ! 	depends on ARCH_OMAP
-   	select TPS65010 if MACH_OMAP_H2
-   	help
-   	  This selects the TI OMAP Multimedia card Interface.
- --- 231,237 ----
-   
-   config MMC_OMAP
-   	tristate "TI OMAP Multimedia Card Interface support"
- ! 	depends on ARCH_OMAP || ARCH_CKB
-   	select TPS65010 if MACH_OMAP_H2
-   	help
-   	  This selects the TI OMAP Multimedia card Interface.
- ***************
- *** 242,248 ****
-   
-   config MMC_OMAP_HS
-   	tristate "TI OMAP High Speed Multimedia Card Interface support"
- ! 	depends on SOC_OMAP2430 || ARCH_OMAP3 || ARCH_OMAP4
-   	help
-   	  This selects the TI OMAP High Speed Multimedia card Interface.
-   	  If you have an OMAP2430 or OMAP3 board or OMAP4 board with a
- --- 242,248 ----
-   
-   config MMC_OMAP_HS
-   	tristate "TI OMAP High Speed Multimedia Card Interface support"
- ! 	depends on SOC_OMAP2430 || ARCH_OMAP3 || ARCH_OMAP4 || ARCH_CKB
-   	help
-   	  This selects the TI OMAP High Speed Multimedia card Interface.
-   	  If you have an OMAP2430 or OMAP3 board or OMAP4 board with a
- diff -crN linux-3.2.1_o/drivers/mmc/host/omap_hsmmc.c linux-3.2.1/drivers/mmc/host/omap_hsmmc.c
- *** linux-3.2.1_o/drivers/mmc/host/omap_hsmmc.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/mmc/host/omap_hsmmc.c	2014-05-15 13:25:14.571218032 +0900
- ***************
- *** 59,64 ****
- --- 59,65 ----
-   #define OMAP_HSMMC_IE		0x0134
-   #define OMAP_HSMMC_ISE		0x0138
-   #define OMAP_HSMMC_CAPA		0x0140
- + #define OMAP_HSMMC_PSTATE	0x0124
-   
-   #define VS18			(1 << 26)
-   #define VS30			(1 << 25)
- ***************
- *** 78,84 ****
-   #define CLKD_SHIFT		6
-   #define DTO_MASK		0x000F0000
-   #define DTO_SHIFT		16
- ! #define INT_EN_MASK		0x307F0033
-   #define BWR_ENABLE		(1 << 4)
-   #define BRR_ENABLE		(1 << 5)
-   #define DTO_ENABLE		(1 << 20)
- --- 79,85 ----
-   #define CLKD_SHIFT		6
-   #define DTO_MASK		0x000F0000
-   #define DTO_SHIFT		16
- ! #define INT_EN_MASK		0x307F00f3
-   #define BWR_ENABLE		(1 << 4)
-   #define BRR_ENABLE		(1 << 5)
-   #define DTO_ENABLE		(1 << 20)
- ***************
- *** 89,94 ****
- --- 90,100 ----
-   #define MSBS			(1 << 5)
-   #define BCE			(1 << 1)
-   #define FOUR_BIT		(1 << 1)
- + #define HSPE			(1 << 2)
- + #define DVAL_MASK		(3 << 9)
- + #define DVAL_MAX		(3 << 9)	/* 8.4 ms debounce period */
- + #define WPP_MASK		(1 << 8)
- + #define WPP_ACT_LOW		(1 << 8)	/* WPP is Active Low */
-   #define DW8			(1 << 5)
-   #define CC			0x1
-   #define TC			0x02
- ***************
- *** 106,111 ****
- --- 112,125 ----
-   #define SRD			(1 << 26)
-   #define SOFTRESET		(1 << 1)
-   #define RESETDONE		(1 << 0)
- + #define CINS			(1 << 6)
- + #define PSTATE_CINS_MASK	BIT(16)
- + #define PSTATE_CINS_SHIFT	16
- + #define PSTATE_WP_MASK		BIT(19)
- + #define PSTATE_WP_SHIFT		19
- + #define IE_CINS			0x00000040
- + #define IE_CINS_SHIFT		6
- + #define PSTATE_CINS     (1 << 16)
-   
-   /*
-    * FIXME: Most likely all the data using these _DEVID defines should come
- ***************
- *** 120,126 ****
-   
-   #define MMC_AUTOSUSPEND_DELAY	100
-   #define MMC_TIMEOUT_MS		20
- - #define OMAP_MMC_MASTER_CLOCK	96000000
-   #define OMAP_MMC_MIN_CLOCK	400000
-   #define OMAP_MMC_MAX_CLOCK	52000000
-   #define DRIVER_NAME		"omap_hsmmc"
- --- 134,139 ----
- ***************
- *** 193,198 ****
- --- 206,213 ----
-   	struct	omap_mmc_platform_data	*pdata;
-   };
-   
- + static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id);
- + 
-   static int omap_hsmmc_card_detect(struct device *dev, int slot)
-   {
-   	struct omap_mmc_platform_data *mmc = dev->platform_data;
- ***************
- *** 224,229 ****
- --- 239,245 ----
-   	struct omap_mmc_platform_data *mmc = dev->platform_data;
-   
-   	disable_irq(mmc->slots[0].card_detect_irq);
- + 
-   	return 0;
-   }
-   
- ***************
- *** 232,237 ****
- --- 248,254 ----
-   	struct omap_mmc_platform_data *mmc = dev->platform_data;
-   
-   	enable_irq(mmc->slots[0].card_detect_irq);
- + 
-   	return 0;
-   }
-   
- ***************
- *** 592,609 ****
-   
-   static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
-   {
-   	OMAP_HSMMC_WRITE(host->base, ISE, 0);
-   	OMAP_HSMMC_WRITE(host->base, IE, 0);
-   	OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
-   }
-   
-   /* Calculate divisor for the given clock frequency */
- ! static u16 calc_divisor(struct mmc_ios *ios)
-   {
-   	u16 dsor = 0;
-   
-   	if (ios->clock) {
- ! 		dsor = DIV_ROUND_UP(OMAP_MMC_MASTER_CLOCK, ios->clock);
-   		if (dsor > 250)
-   			dsor = 250;
-   	}
- --- 609,628 ----
-   
-   static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
-   {
- + 
-   	OMAP_HSMMC_WRITE(host->base, ISE, 0);
-   	OMAP_HSMMC_WRITE(host->base, IE, 0);
-   	OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
- + 
-   }
-   
-   /* Calculate divisor for the given clock frequency */
- ! static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
-   {
-   	u16 dsor = 0;
-   
-   	if (ios->clock) {
- ! 		dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
-   		if (dsor > 250)
-   			dsor = 250;
-   	}
- ***************
- *** 616,629 ****
-   	struct mmc_ios *ios = &host->mmc->ios;
-   	unsigned long regval;
-   	unsigned long timeout;
-   
-   	dev_dbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
-   
-   	omap_hsmmc_stop_clock(host);
-   
-   	regval = OMAP_HSMMC_READ(host->base, SYSCTL);
-   	regval = regval & ~(CLKD_MASK | DTO_MASK);
- ! 	regval = regval | (calc_divisor(ios) << 6) | (DTO << 16);
-   	OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
-   	OMAP_HSMMC_WRITE(host->base, SYSCTL,
-   		OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
- --- 635,660 ----
-   	struct mmc_ios *ios = &host->mmc->ios;
-   	unsigned long regval;
-   	unsigned long timeout;
- + 	unsigned long clkdiv;
- + //printk("************setting clock to %dHz\n", ios->clock);
-   
-   	dev_dbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
-   
- + 	clkdiv = calc_divisor(host, ios);
- + 	regval = OMAP_HSMMC_READ(host->base, HCTL);
- + 	/* Enable HSPE bit for high speed card */
- + 	if (ios->clock && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
- + 		regval |= HSPE;
- + 	else
- + 		regval &= ~HSPE;
- + 
- + 	OMAP_HSMMC_WRITE(host->base, HCTL, regval);
- + 
-   	omap_hsmmc_stop_clock(host);
-   
-   	regval = OMAP_HSMMC_READ(host->base, SYSCTL);
-   	regval = regval & ~(CLKD_MASK | DTO_MASK);
- ! 	regval = regval | (clkdiv << 6) | (DTO << 16);
-   	OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
-   	OMAP_HSMMC_WRITE(host->base, SYSCTL,
-   		OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
- ***************
- *** 862,868 ****
-   	struct mmc_data *data)
-   {
-   	int cmdreg = 0, resptype = 0, cmdtype = 0;
- - 
-   	dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
-   		mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
-   	host->cmd = cmd;
- --- 893,898 ----
- ***************
- *** 941,954 ****
-   {
-   	if (!data) {
-   		struct mmc_request *mrq = host->mrq;
- - 
-   		/* TC before CC from CMD6 - don't know why, but it happens */
-   		if (host->cmd && host->cmd->opcode == 6 &&
-   		    host->response_busy) {
-   			host->response_busy = 0;
-   			return;
-   		}
- - 
-   		omap_hsmmc_request_done(host, mrq);
-   		return;
-   	}
- --- 971,982 ----
- ***************
- *** 956,964 ****
- --- 984,997 ----
-   	host->data = NULL;
-   
-   	if (!data->error)
- + 	{
-   		data->bytes_xfered += data->blocks * (data->blksz);
- + 	}
-   	else
- + 	{
- + 		printk("data->error, trans bytes=0\n");
-   		data->bytes_xfered = 0;
- + 	}
-   
-   	if (!data->stop) {
-   		omap_hsmmc_request_done(host, data->mrq);
- ***************
- *** 1088,1094 ****
-   			__func__);
-   }
-   
- ! static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
-   {
-   	struct mmc_data *data;
-   	int end_cmd = 0, end_trans = 0;
- --- 1121,1127 ----
-   			__func__);
-   }
-   
- ! static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status, int irq)
-   {
-   	struct mmc_data *data;
-   	int end_cmd = 0, end_trans = 0;
- ***************
- *** 1155,1163 ****
- --- 1188,1200 ----
-   	OMAP_HSMMC_WRITE(host->base, STAT, status);
-   
-   	if (end_cmd || ((status & CC) && host->cmd))
- + 	{
-   		omap_hsmmc_cmd_done(host, host->cmd);
- + 	}
-   	if ((end_trans || (status & TC)) && host->mrq)
- + 	{
-   		omap_hsmmc_xfer_done(host, data);
- + 	}
-   }
-   
-   /*
- ***************
- *** 1167,1180 ****
-   {
-   	struct omap_hsmmc_host *host = dev_id;
-   	int status;
- ! 
-   	status = OMAP_HSMMC_READ(host->base, STAT);
-   	do {
- ! 		omap_hsmmc_do_irq(host, status);
-   		/* Flush posted write */
-   		status = OMAP_HSMMC_READ(host->base, STAT);
-   	} while (status & INT_EN_MASK);
- - 
-   	return IRQ_HANDLED;
-   }
-   
- --- 1204,1225 ----
-   {
-   	struct omap_hsmmc_host *host = dev_id;
-   	int status;
- ! 	static int count = 0;
-   	status = OMAP_HSMMC_READ(host->base, STAT);
- + 	if(irq == 29)
- + 	{
- + 		if (host->cmd == NULL && host->data == NULL) {
- + 			OMAP_HSMMC_WRITE(host->base, STAT, status);
- + 			return IRQ_NONE;
- + 		}
- + 	}
-   	do {
- ! 		if(irq == 39)
- ! 			printk("doing_irq 0x%x 0x%x\n", status, host->base); 
- ! 		omap_hsmmc_do_irq(host, status, irq);
-   		/* Flush posted write */
-   		status = OMAP_HSMMC_READ(host->base, STAT);
-   	} while (status & INT_EN_MASK);
-   	return IRQ_HANDLED;
-   }
-   
- ***************
- *** 1338,1360 ****
-   				       struct scatterlist *sgl)
-   {
-   	int blksz, nblk, dma_ch;
-   
-   	dma_ch = host->dma_ch;
-   	if (data->flags & MMC_DATA_WRITE) {
-   		omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
-   			(host->mapbase + OMAP_HSMMC_DATA), 0, 0);
-   		omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
- ! 			sg_dma_address(sgl), 0, 0);
-   	} else {
-   		omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
-   			(host->mapbase + OMAP_HSMMC_DATA), 0, 0);
-   		omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
- ! 			sg_dma_address(sgl), 0, 0);
-   	}
-   
- - 	blksz = host->data->blksz;
- - 	nblk = sg_dma_len(sgl) / blksz;
- - 
-   	omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
-   			blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
-   			omap_hsmmc_get_dma_sync_dev(host, data),
- --- 1383,1412 ----
-   				       struct scatterlist *sgl)
-   {
-   	int blksz, nblk, dma_ch;
- + 	int bindex = 0, cindex = 0;
- + 	struct omap_mmc_platform_data *pdata = host->pdata;
-   
-   	dma_ch = host->dma_ch;
- + 	blksz = host->data->blksz;
- + 	nblk = sg_dma_len(sgl) / blksz;
- + 
- + 	if (pdata->version == MMC_CTRL_VERSION_2) {
- + 		bindex = 4;
- + 		cindex = blksz;
- + 	}
- + 
-   	if (data->flags & MMC_DATA_WRITE) {
-   		omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
-   			(host->mapbase + OMAP_HSMMC_DATA), 0, 0);
-   		omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
- ! 			sg_dma_address(sgl), bindex, cindex);
-   	} else {
-   		omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
-   			(host->mapbase + OMAP_HSMMC_DATA), 0, 0);
-   		omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
- ! 			sg_dma_address(sgl), bindex, cindex);
-   	}
-   
-   	omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
-   			blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
-   			omap_hsmmc_get_dma_sync_dev(host, data),
- ***************
- *** 1370,1381 ****
-   {
-   	struct omap_hsmmc_host *host = cb_data;
-   	struct mmc_data *data;
-   	int dma_ch, req_in_progress;
-   
- ! 	if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
- ! 		dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
- ! 			ch_status);
- ! 		return;
-   	}
-   
-   	spin_lock(&host->irq_lock);
- --- 1422,1440 ----
-   {
-   	struct omap_hsmmc_host *host = cb_data;
-   	struct mmc_data *data;
- + 	struct omap_mmc_platform_data *pdata = host->pdata;
-   	int dma_ch, req_in_progress;
-   
- ! 
- ! 	if (pdata->version == MMC_CTRL_VERSION_2) {
- ! 		if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
- ! 			dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
- ! 	} else {
- ! 		if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
- ! 			dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
- ! 				ch_status);
- ! 			return;
- ! 		}
-   	}
-   
-   	spin_lock(&host->irq_lock);
- ***************
- *** 1498,1508 ****
-   	return 0;
-   }
-   
- ! static void set_data_timeout(struct omap_hsmmc_host *host,
- ! 			     unsigned int timeout_ns,
- ! 			     unsigned int timeout_clks)
-   {
- - 	unsigned int timeout, cycle_ns;
-   	uint32_t reg, clkd, dto = 0;
-   
-   	reg = OMAP_HSMMC_READ(host->base, SYSCTL);
- --- 1557,1564 ----
-   	return 0;
-   }
-   
- ! static void set_data_timeout(struct omap_hsmmc_host *host)
-   {
-   	uint32_t reg, clkd, dto = 0;
-   
-   	reg = OMAP_HSMMC_READ(host->base, SYSCTL);
- ***************
- *** 1510,1534 ****
-   	if (clkd == 0)
-   		clkd = 1;
-   
- ! 	cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
- ! 	timeout = timeout_ns / cycle_ns;
- ! 	timeout += timeout_clks;
- ! 	if (timeout) {
- ! 		while ((timeout & 0x80000000) == 0) {
- ! 			dto += 1;
- ! 			timeout <<= 1;
- ! 		}
- ! 		dto = 31 - dto;
- ! 		timeout <<= 1;
- ! 		if (timeout && dto)
- ! 			dto += 1;
- ! 		if (dto >= 13)
- ! 			dto -= 13;
- ! 		else
- ! 			dto = 0;
- ! 		if (dto > 14)
- ! 			dto = 14;
- ! 	}
-   
-   	reg &= ~DTO_MASK;
-   	reg |= dto << DTO_SHIFT;
- --- 1566,1573 ----
-   	if (clkd == 0)
-   		clkd = 1;
-   
- ! 	/* Use the maximum timeout value allowed in the standard of 14 or 0xE */
- ! 	dto = 14;
-   
-   	reg &= ~DTO_MASK;
-   	reg |= dto << DTO_SHIFT;
- ***************
- *** 1551,1563 ****
-   		 * busy signal.
-   		 */
-   		if (req->cmd->flags & MMC_RSP_BUSY)
- ! 			set_data_timeout(host, 100000000U, 0);
-   		return 0;
-   	}
-   
-   	OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
-   					| (req->data->blocks << 16));
- ! 	set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
-   
-   	if (host->use_dma) {
-   		ret = omap_hsmmc_start_dma_transfer(host, req);
- --- 1590,1602 ----
-   		 * busy signal.
-   		 */
-   		if (req->cmd->flags & MMC_RSP_BUSY)
- ! 			set_data_timeout(host);
-   		return 0;
-   	}
-   
-   	OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
-   					| (req->data->blocks << 16));
- ! 	set_data_timeout(host);
-   
-   	if (host->use_dma) {
-   		ret = omap_hsmmc_start_dma_transfer(host, req);
- ***************
- *** 1649,1654 ****
- --- 1688,1695 ----
-   {
-   	struct omap_hsmmc_host *host = mmc_priv(mmc);
-   	int do_send_init_stream = 0;
- + 	struct omap_mmc_platform_data *pdata = host->pdata;
- + 	u32 regVal;
-   
-   	pm_runtime_get_sync(host->dev);
-   
- ***************
- *** 1673,1678 ****
- --- 1714,1731 ----
-   
-   	/* FIXME: set registers based only on changes to ios */
-   
- + 	if (pdata->version == MMC_CTRL_VERSION_2) {
- + 		/*
- + 		* Set
- + 		*	Debounce filter value to max
- + 		*	Write protect polarity to Active low level
- + 		*/
- + 		regVal = OMAP_HSMMC_READ(host->base, CON);
- + 		regVal &= ~(DVAL_MASK | WPP_MASK);
- + 		regVal |= (DVAL_MAX | WPP_ACT_LOW);
- + 		OMAP_HSMMC_WRITE(host->base, CON, regVal);
- + 	}
- + 
-   	omap_hsmmc_set_bus_width(host);
-   
-   	if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
- ***************
- *** 1869,1875 ****
-   	struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
-   	struct mmc_host *mmc;
-   	struct omap_hsmmc_host *host = NULL;
- ! 	struct resource *res;
-   	int ret, irq;
-   
-   	if (pdata == NULL) {
- --- 1922,1928 ----
-   	struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
-   	struct mmc_host *mmc;
-   	struct omap_hsmmc_host *host = NULL;
- ! 	struct resource *res, *dma_tx, *dma_rx;
-   	int ret, irq;
-   
-   	if (pdata == NULL) {
- ***************
- *** 1949,1980 ****
-   		dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
-   		mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
-   	}
- ! 
-   	pm_runtime_enable(host->dev);
-   	pm_runtime_get_sync(host->dev);
-   	pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
-   	pm_runtime_use_autosuspend(host->dev);
-   
- - 	if (cpu_is_omap2430()) {
- - 		host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
- - 		/*
- - 		 * MMC can still work without debounce clock.
- - 		 */
- - 		if (IS_ERR(host->dbclk))
- - 			dev_warn(mmc_dev(host->mmc),
- - 				"Failed to get debounce clock\n");
- - 		else
- - 			host->got_dbclk = 1;
- - 
- - 		if (host->got_dbclk)
- - 			if (clk_enable(host->dbclk) != 0)
- - 				dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
- - 							" clk failed\n");
- - 	}
- - 
-   	/* Since we do only SG emulation, we can have as many segs
-   	 * as we want. */
- ! 	mmc->max_segs = 1024;
-   
-   	mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
-   	mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
- --- 2002,2019 ----
-   		dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
-   		mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
-   	}
- ! 	
-   	pm_runtime_enable(host->dev);
-   	pm_runtime_get_sync(host->dev);
-   	pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
-   	pm_runtime_use_autosuspend(host->dev);
-   
-   	/* Since we do only SG emulation, we can have as many segs
-   	 * as we want. */
- ! 	if (pdata->version == MMC_CTRL_VERSION_2)
- ! 		mmc->max_segs = 1;
- ! 	else
- ! 		mmc->max_segs = 1024;
-   
-   	mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
-   	mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
- ***************
- *** 1991,2025 ****
-   	if (mmc_slot(host).nonremovable)
-   		mmc->caps |= MMC_CAP_NONREMOVABLE;
-   
-   	omap_hsmmc_conf_bus_power(host);
-   
-   	/* Select DMA lines */
- ! 	switch (host->id) {
- ! 	case OMAP_MMC1_DEVID:
- ! 		host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
- ! 		host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
- ! 		break;
- ! 	case OMAP_MMC2_DEVID:
- ! 		host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
- ! 		host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
- ! 		break;
- ! 	case OMAP_MMC3_DEVID:
- ! 		host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
- ! 		host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
- ! 		break;
- ! 	case OMAP_MMC4_DEVID:
- ! 		host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
- ! 		host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
- ! 		break;
- ! 	case OMAP_MMC5_DEVID:
- ! 		host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
- ! 		host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
- ! 		break;
- ! 	default:
- ! 		dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
- ! 		goto err_irq;
- ! 	}
-   
-   	/* Request IRQ for MMC operations */
-   	ret = request_irq(host->irq, omap_hsmmc_irq, 0,
-   			mmc_hostname(mmc), host);
- --- 2030,2085 ----
-   	if (mmc_slot(host).nonremovable)
-   		mmc->caps |= MMC_CAP_NONREMOVABLE;
-   
- + 	mmc->pm_caps = mmc_slot(host).pm_caps;
- + 
-   	omap_hsmmc_conf_bus_power(host);
-   
-   	/* Select DMA lines */
- ! 	if (pdata->version == MMC_CTRL_VERSION_2) {
- ! 		dma_rx = platform_get_resource_byname(pdev,
- ! 							IORESOURCE_DMA, "rx");
- ! 		if (!dma_rx) {
- ! 			ret = -EINVAL;
- ! 			goto err1;
- ! 		}
- ! 
- ! 		dma_tx = platform_get_resource_byname(pdev,
- ! 							IORESOURCE_DMA, "tx");
- ! 		if (!dma_tx) {
- ! 			ret = -EINVAL;
- ! 			goto err1;
- ! 		}
- ! 		host->dma_line_tx = dma_tx->start;
- ! 		host->dma_line_rx = dma_rx->start;
-   
- + 	} else {
- + 		switch (host->id) {
- + 		case OMAP_MMC1_DEVID:
- + 			host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
- + 			host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
- + 			break;
- + 		case OMAP_MMC2_DEVID:
- + 			host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
- + 			host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
- + 			break;
- + 		case OMAP_MMC3_DEVID:
- + 			host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
- + 			host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
- + 			break;
- + 		case OMAP_MMC4_DEVID:
- + 			host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
- + 			host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
- + 			break;
- + 		case OMAP_MMC5_DEVID:
- + 			host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
- + 			host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
- + 			break;
- + 		default:
- + 			dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
- + 			goto err_irq;
- + 		}
- + 	}
- + 	
-   	/* Request IRQ for MMC operations */
-   	ret = request_irq(host->irq, omap_hsmmc_irq, 0,
-   			mmc_hostname(mmc), host);
- ***************
- *** 2042,2048 ****
-   			goto err_reg;
-   		host->use_reg = 1;
-   	}
- - 
-   	mmc->ocr_avail = mmc_slot(host).ocr_mask;
-   
-   	/* Request IRQ for card detect */
- --- 2102,2107 ----
- ***************
- *** 2065,2071 ****
-   	omap_hsmmc_protect_card(host);
-   
-   	mmc_add_host(mmc);
- - 
-   	if (mmc_slot(host).name != NULL) {
-   		ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
-   		if (ret < 0)
- --- 2124,2129 ----
- ***************
- *** 2179,2191 ****
-   		cancel_work_sync(&host->mmc_carddetect_work);
-   		ret = mmc_suspend_host(host->mmc);
-   
- ! 		if (ret == 0) {
- ! 			omap_hsmmc_disable_irq(host);
- ! 			OMAP_HSMMC_WRITE(host->base, HCTL,
- ! 				OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
- ! 			if (host->got_dbclk)
- ! 				clk_disable(host->dbclk);
- ! 		} else {
-   			host->suspended = 0;
-   			if (host->pdata->resume) {
-   				ret = host->pdata->resume(&pdev->dev,
- --- 2237,2243 ----
-   		cancel_work_sync(&host->mmc_carddetect_work);
-   		ret = mmc_suspend_host(host->mmc);
-   
- ! 		if (ret) {
-   			host->suspended = 0;
-   			if (host->pdata->resume) {
-   				ret = host->pdata->resume(&pdev->dev,
- ***************
- *** 2194,2202 ****
-   					dev_dbg(mmc_dev(host->mmc),
-   						"Unmask interrupt failed\n");
-   			}
-   		}
- ! 		pm_runtime_put_sync(host->dev);
-   	}
-   	return ret;
-   }
-   
- --- 2246,2266 ----
-   					dev_dbg(mmc_dev(host->mmc),
-   						"Unmask interrupt failed\n");
-   			}
- + 			ret = -EBUSY;
- + 			goto err;
-   		}
- ! 
- ! 		if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
- ! 			omap_hsmmc_disable_irq(host);
- ! 			OMAP_HSMMC_WRITE(host->base, HCTL,
- ! 				OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
- ! 		}
- ! 		if (host->got_dbclk)
- ! 			clk_disable(host->dbclk);
- ! 
-   	}
- + err:
- + 	pm_runtime_put_sync(host->dev);
-   	return ret;
-   }
-   
- ***************
- *** 2216,2222 ****
-   		if (host->got_dbclk)
-   			clk_enable(host->dbclk);
-   
- ! 		omap_hsmmc_conf_bus_power(host);
-   
-   		if (host->pdata->resume) {
-   			ret = host->pdata->resume(&pdev->dev, host->slot_id);
- --- 2280,2287 ----
-   		if (host->got_dbclk)
-   			clk_enable(host->dbclk);
-   
- ! 		if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
- ! 			omap_hsmmc_conf_bus_power(host);
-   
-   		if (host->pdata->resume) {
-   			ret = host->pdata->resume(&pdev->dev, host->slot_id);
- diff -crN linux-3.2.1_o/drivers/mtd/chips/ckb_gpmc_cs1.c linux-3.2.1/drivers/mtd/chips/ckb_gpmc_cs1.c
- *** linux-3.2.1_o/drivers/mtd/chips/ckb_gpmc_cs1.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/drivers/mtd/chips/ckb_gpmc_cs1.c	2014-05-15 13:25:14.575218357 +0900
- ***************
- *** 0 ****
- --- 1,333 ----
- + /*
- +  * CKB_3352 board : EMIFA CS5 driver
- +  * 
- +  * Copyright (C) 2013 Computex Co.Ltd.
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; version 2 of the License.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- +  *
- +  */     
- + #include <linux/module.h>
- + #include <linux/kernel.h>
- + #include <linux/sched.h>
- + #include <linux/slab.h>
- + #include <linux/init.h>
- + #include <asm/mach/map.h>
- + #include <linux/platform_device.h>
- + #include <linux/gpio.h>
- + #include <linux/mutex.h>
- + #include <linux/clk.h>
- + #include <linux/err.h>
- + #include <linux/platform_device.h>
- + #include <linux/fs.h>
- + #include <mach/hardware.h>
- + #include <asm/uaccess.h>
- + #include <asm/mach-types.h>
- + #include <asm/mach/arch.h>
- + #include <mtd/ckb_gpmc_cs1.h>
- + #include <linux/syscalls.h>
- + 
- + 
- + /* driver instance */
- + static struct class *ckb_gpmc_cs1_dev_class;
- + struct ckb_gpmc_cs1_device *cur_ckb_gpmc_cs1_dev=NULL;		/* single instance */
- + 
- + static long ckb_gpmc_cs1_ioctl_write_reg(int offset, unsigned long arg)
- + {
- + 	/* set the GPMC_CONFIGn register */
- + 	void __iomem *gpmc_addr;
- + 	unsigned long val;
- + 	if (get_user(val, (unsigned long __user *)arg))
- + 		return -EFAULT;
- + 	gpmc_addr = ioremap(AM3352_GPMC_BASE, SZ_1K);
- + 	writel(val, gpmc_addr + offset);
- + 	iounmap(gpmc_addr);
- + 	return 0;
- + }
- + 
- + static long ckb_gpmc_cs1_ioctl_read_reg(int offset, unsigned long arg)
- + {
- + 	/* get the GPMC_CONFIGn register value */
- + 	void __iomem *gpmc_addr;
- + 	unsigned long val;
- + 	gpmc_addr = ioremap(AM3352_GPMC_BASE, SZ_1K);
- + 	val = readl(gpmc_addr + offset);
- + 	iounmap(gpmc_addr);
- + 	if (put_user(val, (unsigned long __user *)arg))
- + 		return -EFAULT;
- + 	return 0;
- + }
- + 
- + static long ckb_gpmc_cs1_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
- + {	
- + 	switch(cmd)
- + 	{
- + 	case CKB_GPMC_CS1_IOCTL_SET_CONFIG1_REG:
- + 		return ckb_gpmc_cs1_ioctl_write_reg(GPMC_CONFIG1_1, arg);
- + 	case CKB_GPMC_CS1_IOCTL_GET_CONFIG1_REG:
- + 		return ckb_gpmc_cs1_ioctl_read_reg(GPMC_CONFIG1_1, arg);
- + 	case CKB_GPMC_CS1_IOCTL_SET_CONFIG2_REG:
- + 		return ckb_gpmc_cs1_ioctl_write_reg(GPMC_CONFIG2_1, arg);
- + 	case CKB_GPMC_CS1_IOCTL_GET_CONFIG2_REG:
- + 		return ckb_gpmc_cs1_ioctl_read_reg(GPMC_CONFIG2_1, arg);
- + 	case CKB_GPMC_CS1_IOCTL_SET_CONFIG3_REG:
- + 		return ckb_gpmc_cs1_ioctl_write_reg(GPMC_CONFIG3_1, arg);
- + 	case CKB_GPMC_CS1_IOCTL_GET_CONFIG3_REG:
- + 		return ckb_gpmc_cs1_ioctl_read_reg(GPMC_CONFIG3_1, arg);
- + 	case CKB_GPMC_CS1_IOCTL_SET_CONFIG4_REG:
- + 		return ckb_gpmc_cs1_ioctl_write_reg(GPMC_CONFIG4_1, arg);
- + 	case CKB_GPMC_CS1_IOCTL_GET_CONFIG4_REG:
- + 		return ckb_gpmc_cs1_ioctl_read_reg(GPMC_CONFIG4_1, arg);
- + 	case CKB_GPMC_CS1_IOCTL_SET_CONFIG5_REG:
- + 		return ckb_gpmc_cs1_ioctl_write_reg(GPMC_CONFIG5_1, arg);
- + 	case CKB_GPMC_CS1_IOCTL_GET_CONFIG5_REG:
- + 		return ckb_gpmc_cs1_ioctl_read_reg(GPMC_CONFIG5_1, arg);
- + 	case CKB_GPMC_CS1_IOCTL_SET_CONFIG6_REG:
- + 		return ckb_gpmc_cs1_ioctl_write_reg(GPMC_CONFIG6_1, arg);
- + 	case CKB_GPMC_CS1_IOCTL_GET_CONFIG6_REG:
- + 		return ckb_gpmc_cs1_ioctl_read_reg(GPMC_CONFIG6_1, arg);
- + 	case CKB_GPMC_CS1_IOCTL_SET_CONFIG7_REG:
- + 		return ckb_gpmc_cs1_ioctl_write_reg(GPMC_CONFIG7_1, arg);
- + 	case CKB_GPMC_CS1_IOCTL_GET_CONFIG7_REG:
- + 		return ckb_gpmc_cs1_ioctl_read_reg(GPMC_CONFIG7_1, arg);
- + 	}	
- + 	return 0;
- + }
- + 
- + static int ckb_gpmc_cs1_dev_mmap(struct file *file, struct vm_area_struct *vma)
- + {
- + 	unsigned long start;
- + 	unsigned long off;
- + 	u32 len;
- + #if 0
- + 	if ((vma->vm_end - vma->vm_start) > cur_ckb_gpmc_cs1_dev->mem_size)
- + 		return -EINVAL;
- + #endif
- + 	off = vma->vm_pgoff << PAGE_SHIFT;
- + 	start = cur_ckb_gpmc_cs1_dev->phys_base;
- + 	len = PAGE_ALIGN((start & ~PAGE_MASK) + cur_ckb_gpmc_cs1_dev->mem_size);
- + 	
- + 	start &= PAGE_MASK;
- + 	if ((vma->vm_end - vma->vm_start + off) > len)
- + 		return -EINVAL;
- + 	off += start;
- + 	vma->vm_pgoff = off >> PAGE_SHIFT;
- + 	vma->vm_flags |= VM_IO | VM_RESERVED;
- + 	if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
- + 				       vma->vm_end - vma->vm_start,
- + 				       vma->vm_page_prot))
- + 		return -EAGAIN;
- + 	return 0; 
- + }
- + 
- + static int ckb_gpmc_cs1_dev_open(struct inode *inode, struct file *file)
- + {
- + 	struct ckb_gpmc_cs1_dev *dev;
- + 	if (cur_ckb_gpmc_cs1_dev == NULL){
- + 		printk("ckb_gpmc_cs1 open: no device found\n");
- + 		return -ENODEV;
- + 	}
- + 	dev = kzalloc(sizeof(struct ckb_gpmc_cs1_dev), GFP_KERNEL);
- + 	if (!dev) {
- + 		printk("ckb_gpmc_cs1 open: failed to allocate memory\n");
- + 		return -ENOMEM;
- + 	}
- + 	dev->device = cur_ckb_gpmc_cs1_dev;
- + 	file->private_data = dev;
- + 	return 0;
- + }
- + 
- + static int wramdev_release(struct inode *inode, struct file *file)
- + {
- + 	struct ram_dev *dev = file->private_data;
- + 	kfree(dev);
- + 	file->private_data = NULL;
- + 	return 0;
- + }
- + 
- + static ssize_t ckb_gpmc_cs1_info_show(struct device *dev, struct device_attribute *attr, char *buf)
- + {
- + 	return sprintf(buf, "%s\n", "ckb_gpmc_cs1");
- + }
- + 
- + static DEVICE_ATTR(ckb_gpmc_cs1, 0666, ckb_gpmc_cs1_info_show, NULL);
- + 
- + static int __devinit ckb_gpmc_cs1_probe(struct platform_device *pdev)
- + {
- + 	struct resource *plat_res, *res;
- + 	void __iomem *gpmc_addr;
- + 	int ret = 0;
- + 	if(cur_ckb_gpmc_cs1_dev)
- + 	{
- + 		dev_err(&pdev->dev, "ckb_gpmc_cs1 access driver can only be loaded once\n");
- + 		return -ENODEV;
- + 	}
- + 	cur_ckb_gpmc_cs1_dev = kzalloc(sizeof(struct ckb_gpmc_cs1_device), GFP_KERNEL);
- + 	if (cur_ckb_gpmc_cs1_dev == NULL) {
- + 		dev_err(&pdev->dev, "failed to allocate memory\n");
- + 		return -ENOMEM;
- + 	}
- + 	cur_ckb_gpmc_cs1_dev->pdev = pdev;
- + 	
- + 	plat_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- + 	if (plat_res == NULL) {
- + 		dev_err(&pdev->dev, "no memory resource defined\n");
- + 		ret = -ENODEV;
- + 		goto err_free;
- + 	}
- + 	
- + 	res = request_mem_region(plat_res->start, plat_res->end - plat_res->start + 1,
- + 			pdev->name);
- + 	if (res == NULL) {
- + 		dev_err(&pdev->dev, "failed to request memory resource\n");
- + 		ret = -EBUSY;
- + 		goto err_free;
- + 	}
- + 	
- + 	gpmc_addr = ioremap(AM3352_GPMC_BASE, SZ_32K);
- + 
- + 	/* Initilaize and configure data bus width of CS1 to 8 bit */
- + 	writel(readl(gpmc_addr + GPMC_CONFIG1_1) & ~DEVICESIZE_MASK, gpmc_addr + GPMC_CONFIG1_1);
- + 
- + 	writel(WRAPBURST | READMULTIPLE | READTYPE | WRITEMULTIPLE | WRITETYPE | CLKACTIVATIONTIME | ATTACHDDVICEPAGELENGTH | WAITREADMONITORING | WAITWRITEMONITORING | WAITMONITORINGTIME | WAITPINSELECT | DEVICESIZE_8 | DEVICETYPE | MUXADDDATA | TIMEPARAGRANULARITY | GPMCFCLKDIVIDER
- + 		, gpmc_addr + GPMC_CONFIG1_1);
- + 	
- + 	writel(CSWROFFTIME | CSRDOFFTIME | CEEXTRADELAY | CSONTIME, gpmc_addr + GPMC_CONFIG2_1);
- + 	writel(ADVADMUXWROFFTIME | ADVAADMUXRDOFFTIME | ADVWROFFTIME | ADVRDOFFTIME | ADVEXTRADELAY | ADVAADMUXONTIME | ADVONTIME, gpmc_addr + GPMC_CONFIG3_1);
- + 	writel(WEOFFTIME | WEEXTRADELAY | WEONTIME | OEAADMUXOFFTIME | OEOFFTIME | OEEXTRADELAY | OEAADMUXONTIME | OEONTIME, gpmc_addr + GPMC_CONFIG4_1);
- + 	writel(PAGEBURSTACCESSTIME | RDACCESSTIME | WRCYCLETIME | RDCYCLETIME, gpmc_addr + GPMC_CONFIG5_1);
- + 	writel(WRACCESSTIME | WRDATAONADMUXBUS | CYCLE2CYCLEDELAY | CYCLE2CYCLESAMECSEN | CYCLE2CYCLEDIFFCSEN | BUSTURNAROUND, gpmc_addr + GPMC_CONFIG6_1);
- + 	writel(MASKADDRESS| CSVALID | 0x09, gpmc_addr + GPMC_CONFIG7_1);
- + 	
- + 	iounmap(gpmc_addr);
- + 
- + 	/* store WRAM physical address of the chipset and size */
- + 	cur_ckb_gpmc_cs1_dev->mem_size = plat_res->end - plat_res->start;
- + 	cur_ckb_gpmc_cs1_dev->phys_base = plat_res->start;
- + 	
- + 	cur_ckb_gpmc_cs1_dev->mmio_base = ioremap(res->start, res->end - res->start + 1);
- + 	if (cur_ckb_gpmc_cs1_dev->mmio_base == NULL) {
- + 		dev_err(&pdev->dev, "failed to ioremap() registers\n");
- + 		ret = -ENODEV;
- + 		goto err_free_mem;
- + 	}
- + 	
- + 	/* register the GPIO device with the driver core */
- + 	cur_ckb_gpmc_cs1_dev->dev = device_create(ckb_gpmc_cs1_dev_class, NULL,
- + 				     MKDEV(CKB_GPMC_CS1_MAJOR,0), NULL,
- + 				     CKB_GPMC_CS1_DEV_NAME);
- + 	if (IS_ERR(cur_ckb_gpmc_cs1_dev->dev)) {
- + 		goto err_free_dev;
- + 	}
- + 
- + 	if (device_create_file(cur_ckb_gpmc_cs1_dev->dev, &dev_attr_ckb_gpmc_cs1))
- + 		goto error_destroy;
- + 		
- + 	platform_set_drvdata(pdev, cur_ckb_gpmc_cs1_dev);
- + 	
- + 	return 0;
- + error_destroy:
- + 	device_destroy(ckb_gpmc_cs1_dev_class, MKDEV(CKB_GPMC_CS1_MAJOR,0));
- + err_free_dev:	
- + 	iounmap(cur_ckb_gpmc_cs1_dev->mmio_base);
- + err_free_mem:
- + 	release_mem_region(plat_res->start, plat_res->end - plat_res->start + 1);
- + err_free:
- + 	kfree(cur_ckb_gpmc_cs1_dev);
- + 	cur_ckb_gpmc_cs1_dev = NULL;
- + 	printk("ckb_gpmc_cs1 device not added\n");
- + 	return ret;
- + }
- + 
- + static int __devexit ckb_gpmc_cs1_remove(struct platform_device *pdev)
- + {
- + 	struct resource *res;
- + 	if (cur_ckb_gpmc_cs1_dev == NULL)
- + 		return -ENODEV;
- + 	device_destroy(ckb_gpmc_cs1_dev_class, MKDEV(CKB_GPMC_CS1_MAJOR,0));
- + 	iounmap(cur_ckb_gpmc_cs1_dev->mmio_base);
- + 	
- + 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- + 	release_mem_region(res->start, res->end - res->start + 1);
- + 	
- + 	kfree(cur_ckb_gpmc_cs1_dev);
- + 	cur_ckb_gpmc_cs1_dev = NULL;
- + 	return 0;
- + }
- + 
- + static struct platform_driver ckb_gpmc_cs1_driver = {
- + 	.probe		= ckb_gpmc_cs1_probe,
- + 	.remove		= __devexit_p(ckb_gpmc_cs1_remove),
- + 	.driver		= {
- + 		.owner	= THIS_MODULE,
- + 		.name	= CKB_GPMC_CS1_DEV_NAME,
- + 	},
- + };
- + 
- + static const struct file_operations ckb_cs_dev_fops = {
- + 	.owner		= THIS_MODULE,
- + 	.llseek		= no_llseek,
- + 	.read		= NULL,
- + 	.write		= NULL,
- + 	.unlocked_ioctl	= ckb_gpmc_cs1_ioctl,
- + 	.open		= ckb_gpmc_cs1_dev_open,
- + 	.release	= wramdev_release,
- + 	.mmap = ckb_gpmc_cs1_dev_mmap,
- + 	
- + };
- + 
- + static int ckb_gpmc_cs1_init(void)
- + {
- + 	int res;
- + 	res = register_chrdev(CKB_GPMC_CS1_MAJOR, CKB_GPMC_CS1_DEV_NAME, &ckb_cs_dev_fops);
- + 	if (res)
- + 	{
- + 		printk(KERN_ERR "%s: Can't create device file\n", __FILE__);
- + 		goto out;
- + 	}
- + 	ckb_gpmc_cs1_dev_class = class_create(THIS_MODULE, CKB_GPMC_CS1_DEV_NAME);
- + 	if (IS_ERR(ckb_gpmc_cs1_dev_class)) {
- + 		printk(KERN_ERR "%s: Can't create class\n", __FILE__);
- + 		res = PTR_ERR(ckb_gpmc_cs1_dev_class);
- + 		goto out_unreg_chrdev;
- + 	}
- + 	res = platform_driver_register(&ckb_gpmc_cs1_driver);
- + 	if(res)
- + 	{
- + 		printk(KERN_ERR "%s: Can't register driver\n", __FILE__);
- + 		goto out_unreg_class;
- + 	}
- + 	return 0;
- + 
- + out_unreg_class:
- + 	class_destroy(ckb_gpmc_cs1_dev_class);
- + out_unreg_chrdev:
- + 	unregister_chrdev(CKB_GPMC_CS1_MAJOR, CKB_GPMC_CS1_DEV_NAME);
- + out:
- + 	printk(KERN_ERR "%s: Driver Initialization failed\n", __FILE__);
- + 	return res;	
- + }
- + 
- + static void __exit ckb_gpmc_cs1_exit(void)
- + {
- + 	platform_driver_unregister(&ckb_gpmc_cs1_driver);
- + 	class_destroy(ckb_gpmc_cs1_dev_class);
- + 	unregister_chrdev(CKB_GPMC_CS1_MAJOR, CKB_GPMC_CS1_DEV_NAME);
- + }
- + 
- + arch_initcall(ckb_gpmc_cs1_init);
- + module_exit(ckb_gpmc_cs1_exit);
- + 
- + MODULE_DESCRIPTION("CKB 3352 GPMC CS1 driver");
- + MODULE_AUTHOR("Aiyappa M.S.");
- + MODULE_LICENSE("GPL");
- diff -crN linux-3.2.1_o/drivers/mtd/chips/Kconfig linux-3.2.1/drivers/mtd/chips/Kconfig
- *** linux-3.2.1_o/drivers/mtd/chips/Kconfig	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/mtd/chips/Kconfig	2014-05-15 13:25:14.575218357 +0900
- ***************
- *** 239,242 ****
- --- 239,248 ----
-   	  used for XIP purposes.  If you're not sure what this is all about
-   	  then say N.
-   
- + config CKB_GPMC_CS1_MEM
- + 	tristate "CKB 3352 GPMC CS1 driver"
- + 	depends on MACH_CKB_3352
- + 	help
- + 	  Builds CKB 3352 GPMC CS1 driver. The device has to be connected through EX_CN. 
- + 
-   endmenu
- diff -crN linux-3.2.1_o/drivers/mtd/chips/Makefile linux-3.2.1/drivers/mtd/chips/Makefile
- *** linux-3.2.1_o/drivers/mtd/chips/Makefile	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/mtd/chips/Makefile	2014-05-15 13:25:14.575218357 +0900
- ***************
- *** 13,15 ****
- --- 13,16 ----
-   obj-$(CONFIG_MTD_RAM)		+= map_ram.o
-   obj-$(CONFIG_MTD_ROM)		+= map_rom.o
-   obj-$(CONFIG_MTD_ABSENT)	+= map_absent.o
- + obj-$(CONFIG_CKB_GPMC_CS1_MEM)	+= ckb_gpmc_cs1.o
- diff -crN linux-3.2.1_o/drivers/mtd/devices/m25p80.c linux-3.2.1/drivers/mtd/devices/m25p80.c
- *** linux-3.2.1_o/drivers/mtd/devices/m25p80.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/mtd/devices/m25p80.c	2014-05-15 13:25:14.575218357 +0900
- ***************
- *** 679,684 ****
- --- 679,685 ----
-   	{ "mx25l4005a",  INFO(0xc22013, 0, 64 * 1024,   8, SECT_4K) },
-   	{ "mx25l8005",   INFO(0xc22014, 0, 64 * 1024,  16, 0) },
-   	{ "mx25l1606e",  INFO(0xc22015, 0, 64 * 1024,  32, SECT_4K) },
- + 	{ "mx25l1633e",  INFO(0xc22415, 0, 64 * 1024,  32, SECT_4K) },
-   	{ "mx25l3205d",  INFO(0xc22016, 0, 64 * 1024,  64, 0) },
-   	{ "mx25l6405d",  INFO(0xc22017, 0, 64 * 1024, 128, 0) },
-   	{ "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
- diff -crN linux-3.2.1_o/drivers/mtd/devices/Makefile linux-3.2.1/drivers/mtd/devices/Makefile
- *** linux-3.2.1_o/drivers/mtd/devices/Makefile	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/mtd/devices/Makefile	2014-05-15 13:25:14.575218357 +0900
- ***************
- *** 18,22 ****
-   obj-$(CONFIG_MTD_DATAFLASH)	+= mtd_dataflash.o
-   obj-$(CONFIG_MTD_M25P80)	+= m25p80.o
-   obj-$(CONFIG_MTD_SST25L)	+= sst25l.o
-   
- ! CFLAGS_docg3.o			+= -I$(src)
- \ No newline at end of file
- --- 18,23 ----
-   obj-$(CONFIG_MTD_DATAFLASH)	+= mtd_dataflash.o
-   obj-$(CONFIG_MTD_M25P80)	+= m25p80.o
-   obj-$(CONFIG_MTD_SST25L)	+= sst25l.o
- + obj-$(CONFIG_MTD_NAND_OMAP2)	+= omap2_elm.o
-   
- ! CFLAGS_docg3.o			+= -I$(src)
- diff -crN linux-3.2.1_o/drivers/net/can/d_can/d_can.c linux-3.2.1/drivers/net/can/d_can/d_can.c
- *** linux-3.2.1_o/drivers/net/can/d_can/d_can.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/drivers/net/can/d_can/d_can.c	2014-05-15 13:25:14.578604260 +0900
- ***************
- *** 0 ****
- --- 1,1415 ----
- + /*
- +  * CAN bus driver for Bosch D_CAN controller
- +  *
- +  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- +  *
- +  * Borrowed from C_CAN driver
- +  * Copyright (C) 2010 ST Microelectronics
- +  * - Bhupesh Sharma <bhupesh.sharma@st.com>
- +  *
- +  * Borrowed heavily from the C_CAN driver originally written by:
- +  * Copyright (C) 2007
- +  * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
- +  * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
- +  *
- +  * Bosch D_CAN controller is compliant to CAN protocol version 2.0 part A and B.
- +  * Bosch D_CAN user manual can be obtained from:
- +  * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/can/
- +  * d_can_users_manual_111.pdf
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #include <linux/kernel.h>
- + #include <linux/module.h>
- + #include <linux/interrupt.h>
- + #include <linux/delay.h>
- + #include <linux/netdevice.h>
- + #include <linux/if_arp.h>
- + #include <linux/if_ether.h>
- + #include <linux/list.h>
- + #include <linux/io.h>
- + 
- + #include <linux/platform_device.h>
- + #include <linux/can.h>
- + #include <linux/can/dev.h>
- + #include <linux/can/error.h>
- + 
- + #include "d_can.h"
- + 
- + /* TI D_CAN module registers */
- + #define D_CAN_CTL		0x0	/* CAN control register */
- + #define D_CAN_ES		0x4	/* Error and status */
- + #define D_CAN_PARITYERR_EOI	0x4	/* Parity error EOI */
- + #define D_CAN_ERRC		0x8	/* Error counter */
- + #define D_CAN_BTR		0xC	/* Bit timing */
- + #define D_CAN_INT		0x10	/* Interrupt register */
- + #define D_CAN_TEST		0x14	/* Test register */
- + #define D_CAN_PERR		0x1C	/* Parity Error Code */
- + #define D_CAN_ABOTR		0x80	/* Auto-Bus-On Time */
- + #define D_CAN_TXRQ_X		0x84	/* Transmission Request X */
- + #define D_CAN_TXRQ(n)		(0x88 + ((n) * 4)) /* Transmission request */
- + #define D_CAN_NWDAT_X		0x98	/* New data X register */
- + #define D_CAN_NWDAT(n)		(0x9C + ((n) * 4)) /* New data */
- + #define D_CAN_INTPND_X		0xAC	/* Interrupt Pending X */
- + #define D_CAN_INTPND(n)		(0xB0 + ((n) * 4)) /* Interrupt Pending */
- + #define D_CAN_MSGVAL_X		0xC0		/* Message Valid X */
- + #define D_CAN_MSGVAL(n)		(0xC4 + ((n) * 4)) /* Message Valid */
- + #define D_CAN_INTMUX(n)		(0xD8 + ((n) * 4)) /* Interrupt Multiplexer */
- + #define D_CAN_IFCMD(n)		(0x100 + ((n) * 0x20)) /* Command */
- + #define D_CAN_IFMSK(n)		(0x104 + ((n) * 0x20)) /* Mask */
- + #define D_CAN_IFARB(n)		(0x108 + ((n) * 0x20)) /* Arbitration */
- + #define D_CAN_IFMCTL(n)		(0x10c + ((n) * 0x20)) /* Message ctl */
- + #define D_CAN_IFDATA(n)		(0x110 + ((n) * 0x20)) /* DATA A */
- + #define D_CAN_IFDATB(n)		(0x114 + ((n) * 0x20)) /* DATA B */
- + #define D_CAN_IF3OBS		0x140	/* IF3 Observation */
- + #define D_CAN_IF3UPD(n)		(0x160 + ((n) * 4)) /* Update enable */
- + #define D_CAN_TIOC		0x1E0	/* CAN TX IO Control */
- + #define D_CAN_RIOC		0x1E4	/* CAN RX IO Control */
- + 
- + /* Control register Bit fields */
- + #define D_CAN_CTL_WUBA		BIT(26)	/* Automatic wake-up on bus activity */
- + #define D_CAN_CTL_PDR		BIT(24)	/* Request for local low power mode */
- + #define D_CAN_CTL_DE3		BIT(20)	/* Enable DMA request line for IF3 */
- + #define D_CAN_CTL_DE2		BIT(19)	/* Enable DMA request line for IF2 */
- + #define D_CAN_CTL_DE1		BIT(18)	/* Enable DMA request line for IF1 */
- + #define D_CAN_CTL_IE1		BIT(17)	/* Interrupt line 1 enable */
- + #define D_CAN_CTL_INITDBG	BIT(16)	/* Init state for debug access */
- + #define D_CAN_CTL_SWR		BIT(15)	/* S/W reset enable */
- + #define D_CAN_CTL_PMD		(0xF << 10)	/* Parity on/off */
- + #define D_CAN_CTL_ABO		BIT(9)	/* Auto bus on enable */
- + #define D_CAN_CTL_IDS		BIT(8)	/* Interruption debug support enable */
- + #define D_CAN_CTL_TEST		BIT(7)	/* Test mode enable */
- + #define D_CAN_CTL_CCE		BIT(6)	/* Configuration change enable */
- + #define D_CAN_CTL_DISABLE_AR	BIT(5)	/* Disable automatic retransmission */
- + #define D_CAN_CTL_ENABLE_AR	(0 << 5)
- + #define D_CAN_CTL_EIE		BIT(3)	/* Error interrupt enable */
- + #define D_CAN_CTL_SIE		BIT(2)	/* Status change int enable */
- + #define D_CAN_CTL_IE0		BIT(1)	/* Interrupt line 0 enable */
- + #define D_CAN_CTL_INIT		BIT(0)	/* D_CAN initialization mode */
- + 
- + /* D_CAN Error and Status and Parity Error EOI reg bit fields */
- + #define D_CAN_ES_PDA		BIT(10)	/* Local power-down ACK */
- + #define D_CAN_ES_WUP		BIT(9)	/* Wkae up pending */
- + #define D_CAN_ES_PER		BIT(8)	/* Parity error detected */
- + #define D_CAN_ES_BOFF		BIT(7)	/* Bus off state */
- + #define D_CAN_ES_EWARN		BIT(6)	/* Warning state */
- + #define D_CAN_ES_EPASS		BIT(5)	/* Error passive state */
- + #define D_CAN_ES_RXOK		BIT(4)	/* Received a msg successfully */
- + #define D_CAN_ES_TXOK		BIT(3)	/* Transmitted a msg successfully */
- + #define D_CAN_ES_LEC_MASK	0x7	/* Last error code */
- + 
- + /* Parity error reg bit fields */
- + #define D_CAN_PEEOI		BIT(8)	/* EOI indication for parity error */
- + 
- + /* Error counter reg bit fields */
- + #define D_CAN_ERRC_RP_SHIFT	15
- + #define D_CAN_ERRC_RP_MASK	BIT(15)		/* Receive error passive */
- + #define D_CAN_ERRC_REC_SHIFT	8
- + #define D_CAN_ERRC_REC_MASK	(0x7F << 8)	/* Receive err counter */
- + #define D_CAN_ERRC_TEC_SHIFT	0
- + #define D_CAN_ERRC_TEC_MASK	(0xFF << 0)	/* Transmit err counter */
- + 
- + /* Bit timing reg bit fields */
- + #define D_CAN_BTR_BRPE_SHIFT	16
- + #define D_CAN_BTR_BRPE_MASK	(0xF << 16)	/* Baud rate prescaler ext */
- + #define D_CAN_BTR_TSEG2_SHIFT	12
- + #define D_CAN_BTR_TSEG2_MASK	(0x7 << 12)	/* Time seg after smpl point */
- + #define D_CAN_BTR_TSEG1_SHIFT	8
- + #define D_CAN_BTR_TSEG1_MASK	(0xF << 8)	/* Time seg before smpl point */
- + #define D_CAN_BTR_SJW_SHIFT	6
- + #define D_CAN_BTR_SJW_MASK	(0x3 << 6)	/* Syncronization jump width */
- + #define D_CAN_BTR_BRP_SHIFT	0
- + #define D_CAN_BTR_BRP_MASK	(0x3F << 0)	/* Baud rate prescaler */
- + 
- + /* D_CAN Test register bit fields */
- + #define D_CAN_TEST_RDA		BIT(9)	/* RAM direct access enable */
- + #define D_CAN_TEST_EXL		BIT(8)	/* External loopback mode */
- + #define D_CAN_TEST_RX		BIT(7)	/* Monitors the reveive pin */
- + #define D_CAN_TEST_TX		(0x3 << 5)	/* Control of CAN_TX pin */
- + #define D_CAN_TEST_LBACK	BIT(4)	/* Loopback mode */
- + #define D_CAN_TEST_SILENT	BIT(3)	/* Silent mdoe */
- + 
- + /* D_CAN Parity error reg bit fields */
- + #define D_CAN_PERR_WN_MASK	(0x7 << 8)	/* Parity error word nuber */
- + #define D_CAN_PERR_MN_MASK	0xFF		/* Parity error msg object */
- + 
- + /* D_CAN X registers bit fields */
- + #define D_CAN_BIT_FIELD(n)	(0x3 << (2 * n)) /* X reg's bit field 1 mask */
- + 
- + /* D_CAN IF command reg bit fields */
- + #define D_CAN_IF_CMD_WR		BIT(23)	/* Write/read */
- + #define D_CAN_IF_CMD_MASK	BIT(22)	/* Access to mask bits */
- + #define D_CAN_IF_CMD_ARB	BIT(21)	/* Access to arbitration bits */
- + #define D_CAN_IF_CMD_CONTROL	BIT(20)	/* Acess to control bits */
- + #define D_CAN_IF_CMD_CIP	BIT(19)	/* Clear int pending */
- + #define D_CAN_IF_CMD_TXRQST	BIT(18)	/* Access transmission request */
- + #define D_CAN_IF_CMD_DATAA	BIT(17)	/* Access to Data Bytes 0-3 */
- + #define D_CAN_IF_CMD_DATAB	BIT(16)	/* Access to Data Bytes 4-7 */
- + #define D_CAN_IF_CMD_BUSY	BIT(15)	/* Busy flag */
- + #define D_CAN_IF_CMD_DAM	BIT(14)	/* Activation of DMA */
- + #define D_CAN_IF_CMD_MN_MASK	0xFF	/* No. of msg's used for DMA T/F */
- + #define D_CAN_IF_CMD_ALL	(D_CAN_IF_CMD_MASK | D_CAN_IF_CMD_ARB | \
- + 				D_CAN_IF_CMD_CONTROL | D_CAN_IF_CMD_TXRQST | \
- + 				D_CAN_IF_CMD_DATAA | D_CAN_IF_CMD_DATAB)
- + 
- + /* D_CAN IF mask reg bit fields */
- + #define D_CAN_IF_MASK_MX	BIT(31)	/* Mask Extended Identifier */
- + #define D_CAN_IF_MASK_MD	BIT(30)	/* Mask Message direction */
- + 
- + /* D_CAN IF Arbitration */
- + #define D_CAN_IF_ARB_MSGVAL	BIT(31)	/* Message Vaild */
- + #define D_CAN_IF_ARB_MSGXTD	BIT(30)	/* Extended Identifier 0-11 1-29 */
- + #define D_CAN_IF_ARB_DIR_XMIT	BIT(29) /* Message direction 0-R 1-T */
- + 
- + /* D_CAN IF Message control */
- + #define D_CAN_IF_MCTL_NEWDAT	BIT(15)	/* New data available */
- + #define D_CAN_IF_MCTL_MSGLST	BIT(14)	/* Message lost, only for receive */
- + #define D_CAN_IF_MCTL_CLR_MSGLST (0 << 14)
- + #define D_CAN_IF_MCTL_INTPND	BIT(13)	/* Interrupt pending */
- + #define D_CAN_IF_MCTL_UMASK	BIT(12)	/* Use acceptance mask */
- + #define D_CAN_IF_MCTL_TXIE	BIT(11)	/* Transmit int enable */
- + #define D_CAN_IF_MCTL_RXIE	BIT(10)	/* Receive int enable */
- + #define D_CAN_IF_MCTL_RMTEN	BIT(9)	/* Remote enable */
- + #define D_CAN_IF_MCTL_TXRQST	BIT(8)	/* Transmit request */
- + #define D_CAN_IF_MCTL_EOB	BIT(7)	/* Data frames */
- + #define D_CAN_IF_MCTL_DLC_MASK	0xF	/* Data length code */
- + 
- + /* D_CAN IF3 Observation reg bit fields */
- + #define D_CAN_IF3OBS_UP		BIT(15)	/* Update data status */
- + #define D_CAN_IF3OBS_SDB	BIT(12)	/* DataB read out status */
- + #define D_CAN_IF3OBS_SDA	BIT(11)	/* DataA read out status */
- + #define D_CAN_IF3OBS_SC		BIT(10)	/* Contol bits read out status */
- + #define D_CAN_IF3OBS_SA		BIT(9)	/* Arbitration read out status */
- + #define D_CAN_IF3OBS_SM		BIT(8)	/* Mask bits read out status */
- + #define D_CAN_IF3OBS_DB		BIT(4)	/* Data B read observation */
- + #define D_CAN_IF3OBS_DA		BIT(3)	/* Data A read observation */
- + #define D_CAN_IF3OBS_CTL	BIT(2)	/* Control read observation */
- + #define D_CAN_IF3OBS_ARB	BIT(1)	/* Arbitration data read observation */
- + #define D_CAN_IF3OBS_MASK	BIT(0)	/* Mask data read observation */
- + 
- + /* D_CAN TX I/O reg bit fields */
- + #define D_CAN_TIOC_PU		BIT(18)	/* CAN_TX pull up/down select */
- + #define D_CAN_TIOC_PD		BIT(17)	/* CAN_TX pull disable */
- + #define D_CAN_TIOC_OD		BIT(16)	/* CAN_TX open drain enable */
- + #define D_CAN_TIOC_FUNC		BIT(3)	/* CAN_TX function */
- + #define D_CAN_TIOC_DIR		BIT(2)	/* CAN_TX data direction */
- + #define D_CAN_TIOC_OUT		BIT(1)	/* CAN_TX data out write */
- + #define D_CAN_TIOC_IN		BIT(0)	/* CAN_TX data in */
- + 
- + /* D_CAN RX I/O reg bit fields */
- + #define D_CAN_RIOC_PU		BIT(18)	/* CAN_RX pull up/down select */
- + #define D_CAN_RIOC_PD		BIT(17)	/* CAN_RX pull disable */
- + #define D_CAN_RIOC_OD		BIT(16)	/* CAN_RX open drain enable */
- + #define D_CAN_RIOC_FUNC		BIT(3)	/* CAN_RX function */
- + #define D_CAN_RIOC_DIR		BIT(2)	/* CAN_RX data direction */
- + #define D_CAN_RIOC_OUT		BIT(1)	/* CAN_RX data out write */
- + #define D_CAN_RTIOC_IN		BIT(0)	/* CAN_RX data in */
- + 
- + #define D_CAN_SET_REG		0xFFFFFFFF
- + 
- + #define D_CAN_CANMID_IDE	BIT(31)	/* Extended frame format */
- + #define D_CAN_CANMID_AME	BIT(30)	/* Acceptance mask enable */
- + #define D_CAN_CANMID_AAM	BIT(29)	/* Auto answer mode */
- + 
- + /*
- +  * IF register masks:
- +  */
- + #define IFX_WRITE_IDR(x)		((x) & 0x1FFFFFFF)
- + 
- + #define IFX_CMD_BITS(x)			((x) & 0xFFFFFF00)
- + #define IFX_CMD_MSG_NUMBER(x)		((x) & 0xFF)
- + 
- + /* Message objects split */
- + #define D_CAN_NUM_MSG_OBJECTS		64
- + #define D_CAN_NUM_RX_MSG_OBJECTS	32
- + #define D_CAN_NUM_TX_MSG_OBJECTS	32
- + 
- + #define D_CAN_MSG_OBJ_RX_FIRST		1
- + #define D_CAN_MSG_OBJ_RX_LAST		(D_CAN_MSG_OBJ_RX_FIRST + \
- + 					D_CAN_NUM_RX_MSG_OBJECTS - 1)
- + 
- + #define D_CAN_MSG_OBJ_TX_FIRST		(D_CAN_MSG_OBJ_RX_LAST + 1)
- + #define D_CAN_MSG_OBJ_TX_LAST		(D_CAN_MSG_OBJ_TX_FIRST + \
- + 					D_CAN_NUM_TX_MSG_OBJECTS - 1)
- + 
- + #define D_CAN_MSG_OBJ_RX_SPLIT		17
- + #define D_CAN_MSG_OBJ_RX_LOW_LAST	(D_CAN_MSG_OBJ_RX_SPLIT - 1)
- + 
- + #define D_CAN_NEXT_MSG_OBJ_MASK		(D_CAN_NUM_TX_MSG_OBJECTS - 1)
- + 
- + /* status interrupt */
- + #define STATUS_INTERRUPT		0x8000
- + 
- + /* global interrupt masks */
- + #define ENABLE_ALL_INTERRUPTS		1
- + #define DISABLE_ALL_INTERRUPTS		0
- + 
- + /* minimum timeout for checking BUSY status */
- + #define MIN_TIMEOUT_VALUE		6
- + 
- + /* Wait for ~1 sec for INIT bit */
- + #define D_CAN_WAIT_COUNT		1000
- + 
- + #define D_CAN_IF_RX_NUM			0
- + #define D_CAN_IF_TX_NUM			1
- + 
- + #define D_CAN_GET_XREG_NUM(priv, reg)	(__ffs(d_can_read(priv, reg))/4)
- + 
- + /* CAN Bittiming constants as per D_CAN specs */
- + static struct can_bittiming_const d_can_bittiming_const = {
- + 	.name = D_CAN_DRV_NAME,
- + 	.tseg1_min = 1,		/* Time segment 1 = prop_seg + phase_seg1 */
- + 	.tseg1_max = 16,
- + 	.tseg2_min = 1,		/* Time segment 2 = phase_seg2 */
- + 	.tseg2_max = 8,
- + 	.sjw_max = 4,
- + 	.brp_min = 1,
- + 	.brp_max = 1024,	/* 6-bit BRP field + 4-bit BRPE field*/
- + 	.brp_inc = 1,
- + };
- + 
- + /* d_can last error code (lec) values */
- + enum d_can_lec_type {
- + 	LEC_NO_ERROR = 0,
- + 	LEC_STUFF_ERROR,
- + 	LEC_FORM_ERROR,
- + 	LEC_ACK_ERROR,
- + 	LEC_BIT1_ERROR,
- + 	LEC_BIT0_ERROR,
- + 	LEC_CRC_ERROR,
- + 	LEC_UNUSED,
- + };
- + 
- + /*
- +  * d_can error types:
- +  * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported
- +  */
- + enum d_can_bus_error_types {
- + 	D_CAN_NO_ERROR = 0,
- + 	D_CAN_BUS_OFF,
- + 	D_CAN_ERROR_WARNING,
- + 	D_CAN_ERROR_PASSIVE,
- + };
- + 
- + static inline void d_can_write(struct d_can_priv *priv, u32 reg, u32 val)
- + {
- + 	__raw_writel(val, priv->base + reg);
- + }
- + 
- + static inline u32 d_can_read(struct d_can_priv *priv, int reg)
- + {
- + 	return __raw_readl(priv->base + reg);
- + }
- + 
- + static inline void d_can_set_bit(struct d_can_priv *priv, int reg,
- + 	u32 bit_mask)
- + {
- + 	d_can_write(priv, reg, d_can_read(priv, reg) | bit_mask);
- + }
- + 
- + static inline u32 d_can_get_bit(struct d_can_priv *priv, int reg,
- + 	u32 bit_mask)
- + {
- + 	return (d_can_read(priv, reg) & bit_mask) ? 1 : 0;
- + }
- + 
- + static inline void d_can_clear_bit(struct d_can_priv *priv, int reg,
- + 	u32 bit_mask)
- + {
- + 	d_can_write(priv, reg, d_can_read(priv, reg) & ~bit_mask);
- + }
- + 
- + static inline int get_tx_next_msg_obj(const struct d_can_priv *priv)
- + {
- + 	return (priv->tx_next & D_CAN_NEXT_MSG_OBJ_MASK) +
- + 			D_CAN_MSG_OBJ_TX_FIRST;
- + }
- + 
- + static inline int get_tx_echo_msg_obj(const struct d_can_priv *priv)
- + {
- + 	return (priv->tx_echo & D_CAN_NEXT_MSG_OBJ_MASK) +
- + 			D_CAN_MSG_OBJ_TX_FIRST;
- + }
- + 
- + /*
- +  * API for enabling and disabling the multiple interrupts
- +  * of the DCAN module like error interrupt, status interrupt
- +  * error enable/disable for instance zero and one and etc.
- +  */
- + static void d_can_interrupts(struct d_can_priv *priv, int enable)
- + {
- + 	unsigned int cntrl_save = d_can_read(priv, D_CAN_CTL);
- + 
- + 	if (enable)
- + 		cntrl_save |= (D_CAN_CTL_IE1 | D_CAN_CTL_EIE |
- + 				D_CAN_CTL_IE0);
- + 	else
- + 		cntrl_save &= ~(D_CAN_CTL_IE1 | D_CAN_CTL_SIE |
- + 				D_CAN_CTL_EIE | D_CAN_CTL_IE0);
- + 
- + 	d_can_write(priv, D_CAN_CTL, cntrl_save);
- + }
- + 
- + static inline int d_can_msg_obj_is_busy(struct d_can_priv *priv, int iface)
- + {
- + 	int count = MIN_TIMEOUT_VALUE;
- + 
- + 	while (count && (d_can_read(priv, D_CAN_IFCMD(iface)) &
- + 				D_CAN_IF_CMD_BUSY)) {
- + 		count--;
- + 		udelay(1);
- + 	}
- + 
- + 	if (!count)
- + 		return 1;
- + 
- + 	return 0;
- + }
- + 
- + static inline void d_can_object_get(struct net_device *dev,
- + 					int iface, int objno, int mask)
- + {
- + 	struct d_can_priv *priv = netdev_priv(dev);
- + 
- + 	d_can_write(priv, D_CAN_IFCMD(iface), IFX_CMD_BITS(mask) |
- + 					IFX_CMD_MSG_NUMBER(objno));
- + 
- + 	/*
- + 	 * As per specs, after writing the message object number in the
- + 	 * IF command register the transfer b/w interface register and
- + 	 * message RAM must be complete in 12 CAN-CLK period.
- + 	 */
- + 	if (d_can_msg_obj_is_busy(priv, iface))
- + 		netdev_err(dev, "timed out in object get\n");
- + }
- + 
- + static inline void d_can_object_put(struct net_device *dev,
- + 					int iface, int objno, int mask)
- + {
- + 	struct d_can_priv *priv = netdev_priv(dev);
- + 
- + 	d_can_write(priv, D_CAN_IFCMD(iface), D_CAN_IF_CMD_WR |
- + 		IFX_CMD_BITS(mask) | IFX_CMD_MSG_NUMBER(objno));
- + 
- + 	/*
- + 	 * As per specs, after writing the message object number in the
- + 	 * IF command register the transfer b/w interface register and
- + 	 * message RAM must be complete in 12 CAN-CLK period.
- + 	 */
- + 	if (d_can_msg_obj_is_busy(priv, iface))
- + 		netdev_err(dev, "timed out in object put\n");
- + }
- + 
- + static void d_can_write_msg_object(struct net_device *dev,
- + 			int iface, struct can_frame *frame, int objno)
- + {
- + 	int i;
- + 	unsigned int id;
- + 	u32 dataA = 0;
- + 	u32 dataB = 0;
- + 	u32 flags = 0;
- + 	struct d_can_priv *priv = netdev_priv(dev);
- + 
- + 	if (!(frame->can_id & CAN_RTR_FLAG))
- + 		flags |= D_CAN_IF_ARB_DIR_XMIT;
- + 
- + 	if (frame->can_id & CAN_EFF_FLAG) {
- + 		id = frame->can_id & CAN_EFF_MASK;
- + 		flags |= D_CAN_IF_ARB_MSGXTD;
- + 	} else
- + 		id = ((frame->can_id & CAN_SFF_MASK) << 18);
- + 
- + 	flags |= D_CAN_IF_ARB_MSGVAL;
- + 	d_can_write(priv, D_CAN_IFARB(iface), IFX_WRITE_IDR(id) | flags);
- + 
- + 	for (i = 0; i < frame->can_dlc; i++) {
- + 		if (frame->can_dlc <= 4)
- + 			dataA |= (frame->data[i] << (8 * i));
- + 		else {
- + 			if (i < 4)
- + 				dataA |= (frame->data[i] << (8 * i));
- + 			else
- + 				dataB |= (frame->data[i] << (8 * (i - 4)));
- + 		}
- + 	}
- + 
- + 	/* DATA write to Message object registers DATAA and DATAB */
- + 	if (frame->can_dlc <= 4)
- + 		d_can_write(priv, D_CAN_IFDATA(iface), dataA);
- + 	else {
- + 		d_can_write(priv, D_CAN_IFDATB(iface), dataB);
- + 		d_can_write(priv, D_CAN_IFDATA(iface), dataA);
- + 	}
- + 
- + 	/* enable TX interrupt for this message object */
- + 	d_can_write(priv, D_CAN_IFMCTL(iface),
- + 			D_CAN_IF_MCTL_TXIE | D_CAN_IF_MCTL_EOB |
- + 			D_CAN_IF_MCTL_TXRQST | D_CAN_IF_MCTL_NEWDAT |
- + 			frame->can_dlc);
- + 
- + 	/* Put message data into message RAM */
- + 	d_can_object_put(dev, iface, objno, D_CAN_IF_CMD_ALL);
- + }
- + 
- + /*
- +  * Mark that this particular message object is received and clearing
- +  * the interrupt pending register value.
- +  */
- + static inline void d_can_mark_rx_msg_obj(struct net_device *dev,
- + 				int iface, int ctrl_mask, int obj)
- + {
- + 	struct d_can_priv *priv = netdev_priv(dev);
- + 
- + 	d_can_write(priv, D_CAN_IFMCTL(iface), ctrl_mask
- + 		& ~(D_CAN_IF_MCTL_MSGLST | D_CAN_IF_MCTL_INTPND));
- + 
- + 	d_can_object_put(dev, iface, obj, D_CAN_IF_CMD_CONTROL);
- + }
- + 
- + static inline void d_can_activate_all_lower_rx_msg_objs(struct net_device *dev,
- + 				int iface, int ctrl_mask)
- + {
- + 	int i;
- + 	struct d_can_priv *priv = netdev_priv(dev);
- + 
- + 	for (i = D_CAN_MSG_OBJ_RX_FIRST; i <= D_CAN_MSG_OBJ_RX_LOW_LAST; i++) {
- + 		d_can_write(priv, D_CAN_IFMCTL(iface),
- + 				ctrl_mask & ~(D_CAN_IF_MCTL_MSGLST |
- + 				D_CAN_IF_MCTL_INTPND | D_CAN_IF_MCTL_NEWDAT));
- + 		d_can_object_put(dev, iface, i, D_CAN_IF_CMD_CONTROL);
- + 	}
- + }
- + 
- + static inline void d_can_activate_rx_msg_obj(struct net_device *dev,
- + 						int iface, int ctrl_mask,
- + 						int obj)
- + {
- + 	struct d_can_priv *priv = netdev_priv(dev);
- + 
- + 	d_can_write(priv, D_CAN_IFMCTL(iface),
- + 			ctrl_mask & ~(D_CAN_IF_MCTL_MSGLST |
- + 			D_CAN_IF_MCTL_INTPND | D_CAN_IF_MCTL_NEWDAT));
- + 	d_can_object_put(dev, iface, obj, D_CAN_IF_CMD_CONTROL);
- + }
- + 
- + static void d_can_handle_lost_msg_obj(struct net_device *dev,
- + 					int iface, int objno)
- + {
- + 	struct d_can_priv *priv = netdev_priv(dev);
- + 	struct net_device_stats *stats = &dev->stats;
- + 	struct sk_buff *skb;
- + 	struct can_frame *frame;
- + 
- + 	netdev_err(dev, "msg lost in buffer %d\n", objno);
- + 
- + 	d_can_object_get(dev, iface, objno, D_CAN_IF_CMD_ALL &
- + 					~D_CAN_IF_CMD_TXRQST);
- + 
- + 	d_can_write(priv, D_CAN_IFMCTL(iface), D_CAN_IF_MCTL_CLR_MSGLST);
- + 
- + 	d_can_object_put(dev, iface, objno, D_CAN_IF_CMD_CONTROL);
- + 
- + 	/* create an error msg */
- + 	skb = alloc_can_err_skb(dev, &frame);
- + 	if (unlikely(!skb))
- + 		return;
- + 
- + 	frame->can_id |= CAN_ERR_CRTL;
- + 	frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
- + 	stats->rx_errors++;
- + 	stats->rx_over_errors++;
- + 
- + 	netif_receive_skb(skb);
- + }
- + 
- + static int d_can_read_msg_object(struct net_device *dev, int iface, int ctrl)
- + {
- + 	int i;
- + 	u32 dataA = 0;
- + 	u32 dataB = 0;
- + 	unsigned int arb_val;
- + 	unsigned int mctl_val;
- + 	struct d_can_priv *priv = netdev_priv(dev);
- + 	struct net_device_stats *stats = &dev->stats;
- + 	struct sk_buff *skb;
- + 	struct can_frame *frame;
- + 
- + 	skb = alloc_can_skb(dev, &frame);
- + 	if (!skb) {
- + 		stats->rx_dropped++;
- + 		return -ENOMEM;
- + 	}
- + 
- + 	frame->can_dlc = get_can_dlc(ctrl & 0x0F);
- + 
- + 	arb_val = d_can_read(priv, D_CAN_IFARB(iface));
- + 	mctl_val = d_can_read(priv, D_CAN_IFMCTL(iface));
- + 
- + 	if (arb_val & D_CAN_IF_ARB_MSGXTD)
- + 		frame->can_id = (arb_val & CAN_EFF_MASK) | CAN_EFF_FLAG;
- + 	else
- + 		frame->can_id = (arb_val >> 18) & CAN_SFF_MASK;
- + 
- + 	if (mctl_val & D_CAN_IF_MCTL_RMTEN)
- + 		frame->can_id |= CAN_RTR_FLAG;
- + 	else {
- + 		dataA = d_can_read(priv, D_CAN_IFDATA(iface));
- + 		dataB = d_can_read(priv, D_CAN_IFDATB(iface));
- + 		for (i = 0; i < frame->can_dlc; i++) {
- + 			/* Writing MO higher 4 data bytes to skb */
- + 			if (frame->can_dlc <= 4)
- + 				frame->data[i] = dataA >> (8 * i);
- + 			else {
- + 				if (i < 4)
- + 					frame->data[i] = dataA >> (8 * i);
- + 				else
- + 					frame->data[i] = dataB >> (8 * (i-4));
- + 			}
- + 		}
- + 	}
- + 
- + 	netif_receive_skb(skb);
- + 
- + 	stats->rx_packets++;
- + 	stats->rx_bytes += frame->can_dlc;
- + 
- + 	return 0;
- + }
- + 
- + static void d_can_setup_receive_object(struct net_device *dev, int iface,
- + 					int objno, unsigned int mask,
- + 					unsigned int id, unsigned int mcont)
- + {
- + 	struct d_can_priv *priv = netdev_priv(dev);
- + 
- + 	d_can_write(priv, D_CAN_IFMSK(iface), IFX_WRITE_IDR(mask));
- + 	d_can_write(priv, D_CAN_IFARB(iface), IFX_WRITE_IDR(id) |
- + 			D_CAN_IF_ARB_MSGVAL);
- + 	d_can_write(priv, D_CAN_IFMCTL(iface), mcont);
- + 
- + 	d_can_object_put(dev, iface, objno, D_CAN_IF_CMD_ALL &
- + 					~D_CAN_IF_CMD_TXRQST);
- + 
- + 	netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, d_can_read(priv,
- + 		D_CAN_MSGVAL(D_CAN_GET_XREG_NUM(priv, D_CAN_MSGVAL_X))));
- + }
- + 
- + static void d_can_inval_msg_object(struct net_device *dev, int iface, int objno)
- + {
- + 	struct d_can_priv *priv = netdev_priv(dev);
- + 
- + 	d_can_write(priv, D_CAN_IFARB(iface), 0);
- + 	d_can_write(priv, D_CAN_IFMCTL(iface), 0);
- + 
- + 	d_can_object_put(dev, iface, objno, D_CAN_IF_CMD_ARB |
- + 					D_CAN_IF_CMD_CONTROL);
- + 
- + 	netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, d_can_read(priv,
- + 		D_CAN_MSGVAL(D_CAN_GET_XREG_NUM(priv, D_CAN_MSGVAL_X))));
- + }
- + 
- + static inline int d_can_is_next_tx_obj_busy(struct d_can_priv *priv, int objno)
- + {
- + 	u32 txrq_x_reg_val = D_CAN_GET_XREG_NUM(priv, D_CAN_TXRQ_X);
- + 
- + 	/*
- + 	 * as transmission request register's bit n-1 corresponds to
- + 	 * message object n, we need to handle the same properly.
- + 	 */
- + 	if (d_can_read(priv, D_CAN_TXRQ(txrq_x_reg_val)) &
- + 			(1 << (objno - D_CAN_MSG_OBJ_TX_FIRST)))
- + 		return 1;
- + 
- + 	return 0;
- + }
- + 
- + static netdev_tx_t d_can_start_xmit(struct sk_buff *skb,
- + 					struct net_device *dev)
- + {
- + 	u32 msg_obj_no;
- + 	struct d_can_priv *priv = netdev_priv(dev);
- + 	struct can_frame *frame = (struct can_frame *)skb->data;
- + 
- + 	if (can_dropped_invalid_skb(dev, skb))
- + 		return NETDEV_TX_OK;
- + 
- + 	msg_obj_no = get_tx_next_msg_obj(priv);
- + 
- + 	/* prepare message object for transmission */
- + 	d_can_write_msg_object(dev, D_CAN_IF_TX_NUM, frame, msg_obj_no);
- + 	can_put_echo_skb(skb, dev, msg_obj_no - D_CAN_MSG_OBJ_TX_FIRST);
- + 
- + 	/*
- + 	 * we have to stop the queue in case of a wrap around or
- + 	 * if the next TX message object is still in use
- + 	 */
- + 	priv->tx_next++;
- + 	if (d_can_is_next_tx_obj_busy(priv, get_tx_next_msg_obj(priv)) ||
- + 		((priv->tx_next & D_CAN_NEXT_MSG_OBJ_MASK) == 0))
- + 		netif_stop_queue(dev);
- + 
- + 	return NETDEV_TX_OK;
- + }
- + 
- + static int d_can_set_bittiming(struct net_device *dev)
- + {
- + 	struct d_can_priv *priv = netdev_priv(dev);
- + 	const struct can_bittiming *bt = &priv->can.bittiming;
- + 	u32 can_btc;
- + 
- + 	can_btc = ((bt->phase_seg2 - 1) & 0x7) << D_CAN_BTR_TSEG2_SHIFT;
- + 	can_btc |= ((bt->phase_seg1 + bt->prop_seg - 1)
- + 			& 0xF) << D_CAN_BTR_TSEG1_SHIFT;
- + 
- + 	can_btc |= ((bt->sjw - 1) & 0x3) << D_CAN_BTR_SJW_SHIFT;
- + 
- + 	/* Ten bits contains the BRP, 6 bits for BRP and upper 4 bits for brpe*/
- + 	can_btc |= ((bt->brp - 1) & 0x3F) << D_CAN_BTR_BRP_SHIFT;
- + 	can_btc |= ((((bt->brp - 1) >> 6) & 0xF) << D_CAN_BTR_BRPE_SHIFT);
- + 
- + 	d_can_write(priv, D_CAN_BTR, can_btc);
- + 
- + 	netdev_info(dev, "setting CAN BT = %#x\n", can_btc);
- + 
- + 	return 0;
- + }
- + 
- + /*
- +  * Configure D_CAN message objects for Tx and Rx purposes:
- +  * D_CAN provides a total of 64 message objects that can be configured
- +  * either for Tx or Rx purposes. In this driver first 32 message objects
- +  * are used as a reception FIFO and the reception FIFO is signified by the
- +  * EoB bit being SET. The remaining 32 message objects are kept aside for
- +  * Tx purposes. See user guide document for further details on configuring
- +  * message objects.
- +  */
- + static void d_can_configure_msg_objects(struct net_device *dev)
- + {
- + 	unsigned int i;
- + 
- + 	/* first invalidate all message objects */
- + 	for (i = D_CAN_MSG_OBJ_RX_FIRST; i <= D_CAN_NUM_MSG_OBJECTS; i++)
- + 		d_can_inval_msg_object(dev, D_CAN_IF_RX_NUM, i);
- + 
- + 	/* setup receive message objects */
- + 	for (i = D_CAN_MSG_OBJ_RX_FIRST; i < D_CAN_MSG_OBJ_RX_LAST; i++)
- + 		d_can_setup_receive_object(dev, D_CAN_IF_RX_NUM, i, 0, 0,
- + 			(D_CAN_IF_MCTL_RXIE | D_CAN_IF_MCTL_UMASK) &
- + 			~D_CAN_IF_MCTL_EOB);
- + 
- + 	/* Last object EoB bit should be 1 for terminate */
- + 	d_can_setup_receive_object(dev, D_CAN_IF_RX_NUM, D_CAN_MSG_OBJ_RX_LAST,
- + 			0, 0, D_CAN_IF_MCTL_RXIE | D_CAN_IF_MCTL_UMASK |
- + 			D_CAN_IF_MCTL_EOB);
- + }
- + 
- + static void d_can_test_mode(struct net_device *dev)
- + {
- + 	struct d_can_priv *priv = netdev_priv(dev);
- + 
- + 	/* Test mode is enabled in this step & the specific TEST bits
- + 	 * are enabled accordingly */
- + 	d_can_write(priv, D_CAN_CTL, D_CAN_CTL_EIE |
- + 			D_CAN_CTL_IE1 |	D_CAN_CTL_IE0 | D_CAN_CTL_TEST);
- + 
- + 	if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
- + 		/* silent mode : bus-monitoring mode */
- + 		d_can_write(priv, D_CAN_TEST, D_CAN_TEST_SILENT);
- + 	} else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
- + 		/* loopback mode : useful for self-test function */
- + 		d_can_write(priv, D_CAN_TEST, D_CAN_TEST_LBACK);
- + 	} else {
- + 		/* loopback + silent mode : useful for hot self-test */
- + 		d_can_write(priv, D_CAN_TEST, D_CAN_TEST_LBACK |
- + 				D_CAN_TEST_SILENT);
- + 	}
- + }
- + 
- + /*
- +  * Configure D_CAN chip:
- +  * - enable/disable auto-retransmission
- +  * - set operating mode
- +  * - configure message objects
- +  */
- + static void d_can_init(struct net_device *dev)
- + {
- + 	struct d_can_priv *priv = netdev_priv(dev);
- + 	u32 cnt;
- + 
- + 	netdev_dbg(dev, "resetting d_can ...\n");
- + 	d_can_set_bit(priv, D_CAN_CTL, D_CAN_CTL_SWR);
- + 
- + 	/* Enter initialization mode by setting the Init bit */
- + 	d_can_set_bit(priv, D_CAN_CTL, D_CAN_CTL_INIT);
- + 
- + 	/* enable automatic retransmission */
- + 	d_can_set_bit(priv, D_CAN_CTL, D_CAN_CTL_ENABLE_AR);
- + 
- + 	/* Set the Configure Change Enable ( CCE) bit */
- + 	d_can_set_bit(priv, D_CAN_CTL, D_CAN_CTL_CCE);
- + 
- + 	/* Wait for the Init bit to get set */
- + 	cnt = D_CAN_WAIT_COUNT;
- + 	while (!d_can_get_bit(priv, D_CAN_CTL, D_CAN_CTL_INIT) && cnt != 0) {
- + 		--cnt;
- + 		udelay(10);
- + 	}
- + 
- + 	/* set bittiming params */
- + 	d_can_set_bittiming(dev);
- + 
- + 	d_can_clear_bit(priv, D_CAN_CTL, D_CAN_CTL_INIT | D_CAN_CTL_CCE);
- + 
- + 	/* Wait for the Init bit to get clear */
- + 	cnt = D_CAN_WAIT_COUNT;
- + 	while (d_can_get_bit(priv, D_CAN_CTL, D_CAN_CTL_INIT) && cnt != 0) {
- + 		--cnt;
- + 		udelay(10);
- + 	}
- + 
- + 	if (priv->can.ctrlmode & (CAN_CTRLMODE_LOOPBACK |
- + 				CAN_CTRLMODE_LISTENONLY))
- + 		d_can_test_mode(dev);
- + 	else
- + 		/* normal mode*/
- + 		d_can_write(priv, D_CAN_CTL, D_CAN_CTL_EIE | D_CAN_CTL_IE1 |
- + 							D_CAN_CTL_IE0);
- + 
- + 	/* Enable TX and RX I/O Control pins */
- + 	d_can_write(priv, D_CAN_TIOC, D_CAN_TIOC_FUNC);
- + 	d_can_write(priv, D_CAN_RIOC, D_CAN_RIOC_FUNC);
- + 
- + 	/* configure message objects */
- + 	d_can_configure_msg_objects(dev);
- + 
- + 	/* set a LEC value so that we can check for updates later */
- + 	d_can_write(priv, D_CAN_ES, LEC_UNUSED);
- + }
- + 
- + static void d_can_start(struct net_device *dev)
- + {
- + 	struct d_can_priv *priv = netdev_priv(dev);
- + 
- + 	/* basic d_can initialization */
- + 	d_can_init(dev);
- + 
- + 	priv->can.state = CAN_STATE_ERROR_ACTIVE;
- + 
- + 	/* reset tx helper pointers */
- + 	priv->tx_next = priv->tx_echo = 0;
- + 
- + 	/* enable status change, error and module interrupts */
- + 	d_can_interrupts(priv, ENABLE_ALL_INTERRUPTS);
- + }
- + 
- + static void d_can_stop(struct net_device *dev)
- + {
- + 	struct d_can_priv *priv = netdev_priv(dev);
- + 
- + 	/* disable all interrupts */
- + 	d_can_interrupts(priv, DISABLE_ALL_INTERRUPTS);
- + 
- + 	/* set the state as STOPPED */
- + 	priv->can.state = CAN_STATE_STOPPED;
- + }
- + 
- + static int d_can_set_mode(struct net_device *dev, enum can_mode mode)
- + {
- + 	switch (mode) {
- + 	case CAN_MODE_START:
- + 		d_can_start(dev);
- + 		netif_wake_queue(dev);
- + 		break;
- + 	default:
- + 		return -EOPNOTSUPP;
- + 	}
- + 
- + 	return 0;
- + }
- + 
- + static int d_can_get_berr_counter(const struct net_device *dev,
- + 					struct can_berr_counter *bec)
- + {
- + 	unsigned int reg_err_counter;
- + 	struct d_can_priv *priv = netdev_priv(dev);
- + 
- + 	reg_err_counter = d_can_read(priv, D_CAN_ERRC);
- + 	bec->rxerr = (reg_err_counter & D_CAN_ERRC_REC_MASK) >>
- + 				D_CAN_ERRC_REC_SHIFT;
- + 	bec->txerr = reg_err_counter & D_CAN_ERRC_TEC_MASK;
- + 
- + 	return 0;
- + }
- + 
- + /*
- +  * theory of operation:
- +  *
- +  * priv->tx_echo holds the number of the oldest can_frame put for
- +  * transmission into the hardware, but not yet ACKed by the CAN tx
- +  * complete IRQ.
- +  *
- +  * We iterate from priv->tx_echo to priv->tx_next and check if the
- +  * packet has been transmitted, echo it back to the CAN framework.
- +  * If we discover a not yet transmitted package, stop looking for more.
- +  */
- + static void d_can_do_tx(struct net_device *dev)
- + {
- + 	u32 msg_obj_no;
- + 	struct d_can_priv *priv = netdev_priv(dev);
- + 	struct net_device_stats *stats = &dev->stats;
- + 	u32 txrq_x_reg_val;
- + 	u32 txrq_reg_val;
- + 
- + 	for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) {
- + 		msg_obj_no = get_tx_echo_msg_obj(priv);
- + 		txrq_x_reg_val = D_CAN_GET_XREG_NUM(priv, D_CAN_TXRQ_X);
- + 		txrq_reg_val = d_can_read(priv, D_CAN_TXRQ(txrq_x_reg_val));
- + 		if (!(txrq_reg_val & (1 << (msg_obj_no -
- + 						D_CAN_MSG_OBJ_TX_FIRST)))) {
- + 			can_get_echo_skb(dev,
- + 					msg_obj_no - D_CAN_MSG_OBJ_TX_FIRST);
- + 			stats->tx_bytes += d_can_read(priv,
- + 					D_CAN_IFMCTL(D_CAN_IF_TX_NUM))
- + 					& D_CAN_IF_MCTL_DLC_MASK;
- + 			stats->tx_packets++;
- + 			d_can_inval_msg_object(dev, D_CAN_IF_TX_NUM,
- + 					msg_obj_no);
- + 		} else
- + 			break;
- + 	}
- + 
- + 	/* restart queue if wrap-up or if queue stalled on last pkt */
- + 	if (((priv->tx_next & D_CAN_NEXT_MSG_OBJ_MASK) != 0)
- + 		|| ((priv->tx_echo & D_CAN_NEXT_MSG_OBJ_MASK) == 0))
- + 		netif_wake_queue(dev);
- + }
- + 
- + /*
- +  * theory of operation:
- +  *
- +  * d_can core saves a received CAN message into the first free message
- +  * object it finds free (starting with the lowest). Bits NEWDAT and
- +  * INTPND are set for this message object indicating that a new message
- +  * has arrived. To work-around this issue, we keep two groups of message
- +  * objects whose partitioning is defined by D_CAN_MSG_OBJ_RX_SPLIT.
- +  *
- +  * To ensure in-order frame reception we use the following
- +  * approach while re-activating a message object to receive further
- +  * frames:
- +  * - if the current message object number is lower than
- +  *   D_CAN_MSG_RX_LOW_LAST, do not clear the NEWDAT bit while clearing
- +  *   the INTPND bit.
- +  * - if the current message object number is equal to
- +  *   D_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of all lower
- +  *   receive message objects.
- +  * - if the current message object number is greater than
- +  *   D_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of
- +  *   only this message object.
- +  */
- + static int d_can_do_rx_poll(struct net_device *dev, int quota)
- + {
- + 	struct d_can_priv *priv = netdev_priv(dev);
- + 	unsigned int msg_obj, mctrl_reg_val;
- + 	u32 num_rx_pkts = 0;
- + 	u32 intpnd_x_reg_val;
- + 	u32 intpnd_reg_val;
- + 
- + 	for (msg_obj = D_CAN_MSG_OBJ_RX_FIRST; msg_obj <= D_CAN_MSG_OBJ_RX_LAST
- + 				&& quota > 0; msg_obj++) {
- + 
- + 		intpnd_x_reg_val = D_CAN_GET_XREG_NUM(priv, D_CAN_INTPND_X);
- + 		intpnd_reg_val = d_can_read(priv,
- + 					D_CAN_INTPND(intpnd_x_reg_val));
- + 
- + 		/*
- + 		 * as interrupt pending register's bit n-1 corresponds to
- + 		 * message object n, we need to handle the same properly.
- + 		 */
- + 		if (intpnd_reg_val & (1 << (msg_obj - 1))) {
- + 
- + 			d_can_object_get(dev, D_CAN_IF_RX_NUM, msg_obj,
- + 					D_CAN_IF_CMD_ALL &
- + 					~D_CAN_IF_CMD_TXRQST);
- + 
- + 			mctrl_reg_val = d_can_read(priv,
- + 					D_CAN_IFMCTL(D_CAN_IF_RX_NUM));
- + 
- + 			if (!(mctrl_reg_val & D_CAN_IF_MCTL_NEWDAT))
- + 				continue;
- + 
- + 			/* read the data from the message object */
- + 			d_can_read_msg_object(dev, D_CAN_IF_RX_NUM,
- + 						mctrl_reg_val);
- + 
- + 			if (mctrl_reg_val & D_CAN_IF_MCTL_EOB)
- + 				d_can_setup_receive_object(dev, D_CAN_IF_RX_NUM,
- + 					D_CAN_MSG_OBJ_RX_LAST, 0, 0,
- + 					D_CAN_IF_MCTL_RXIE | D_CAN_IF_MCTL_UMASK
- + 					| D_CAN_IF_MCTL_EOB);
- + 
- + 			if (mctrl_reg_val & D_CAN_IF_MCTL_MSGLST) {
- + 				d_can_handle_lost_msg_obj(dev, D_CAN_IF_RX_NUM,
- + 					msg_obj);
- + 				num_rx_pkts++;
- + 				quota--;
- + 				continue;
- + 			}
- + 
- + 			if (msg_obj < D_CAN_MSG_OBJ_RX_LOW_LAST)
- + 				d_can_mark_rx_msg_obj(dev, D_CAN_IF_RX_NUM,
- + 						mctrl_reg_val, msg_obj);
- + 			else if (msg_obj > D_CAN_MSG_OBJ_RX_LOW_LAST)
- + 				/* activate this msg obj */
- + 				d_can_activate_rx_msg_obj(dev, D_CAN_IF_RX_NUM,
- + 						mctrl_reg_val, msg_obj);
- + 			else if (msg_obj == D_CAN_MSG_OBJ_RX_LOW_LAST)
- + 				/* activate all lower message objects */
- + 				d_can_activate_all_lower_rx_msg_objs(dev,
- + 						D_CAN_IF_RX_NUM, mctrl_reg_val);
- + 
- + 			num_rx_pkts++;
- + 			quota--;
- + 		}
- + 	}
- + 
- + 	return num_rx_pkts;
- + }
- + 
- + static inline int d_can_has_handle_berr(struct d_can_priv *priv)
- + {
- + 	return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
- + 		(priv->current_status & LEC_UNUSED);
- + }
- + 
- + static int d_can_handle_state_change(struct net_device *dev,
- + 				enum d_can_bus_error_types error_type)
- + {
- + 	unsigned int reg_err_counter;
- + 	unsigned int rx_err_passive;
- + 	struct d_can_priv *priv = netdev_priv(dev);
- + 	struct net_device_stats *stats = &dev->stats;
- + 	struct can_frame *cf;
- + 	struct sk_buff *skb;
- + 	struct can_berr_counter bec;
- + 
- + 	/* propagate the error condition to the CAN stack */
- + 	skb = alloc_can_err_skb(dev, &cf);
- + 	if (unlikely(!skb))
- + 		return 0;
- + 
- + 	d_can_get_berr_counter(dev, &bec);
- + 	reg_err_counter = d_can_read(priv, D_CAN_ERRC);
- + 	rx_err_passive = (reg_err_counter & D_CAN_ERRC_RP_MASK) >>
- + 				D_CAN_ERRC_RP_SHIFT;
- + 
- + 	switch (error_type) {
- + 	case D_CAN_ERROR_WARNING:
- + 		/* error warning state */
- + 		priv->can.can_stats.error_warning++;
- + 		priv->can.state = CAN_STATE_ERROR_WARNING;
- + 		cf->can_id |= CAN_ERR_CRTL;
- + 		cf->data[1] = (bec.txerr > bec.rxerr) ?
- + 			CAN_ERR_CRTL_TX_WARNING :
- + 			CAN_ERR_CRTL_RX_WARNING;
- + 		cf->data[6] = bec.txerr;
- + 		cf->data[7] = bec.rxerr;
- + 
- + 		break;
- + 	case D_CAN_ERROR_PASSIVE:
- + 		/* error passive state */
- + 		priv->can.can_stats.error_passive++;
- + 		priv->can.state = CAN_STATE_ERROR_PASSIVE;
- + 		cf->can_id |= CAN_ERR_CRTL;
- + 		if (rx_err_passive)
- + 			cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
- + 		if (bec.txerr > 127)
- + 			cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
- + 
- + 		cf->data[6] = bec.txerr;
- + 		cf->data[7] = bec.rxerr;
- + 		break;
- + 	case D_CAN_BUS_OFF:
- + 		/* bus-off state */
- + 		priv->can.state = CAN_STATE_BUS_OFF;
- + 		cf->can_id |= CAN_ERR_BUSOFF;
- + 		/*
- + 		 * disable all interrupts in bus-off mode to ensure that
- + 		 * the CPU is not hogged down
- + 		 */
- + 		d_can_interrupts(priv, DISABLE_ALL_INTERRUPTS);
- + 		can_bus_off(dev);
- + 		break;
- + 	default:
- + 		break;
- + 	}
- + 
- + 	netif_receive_skb(skb);
- + 	stats->rx_packets++;
- + 	stats->rx_bytes += cf->can_dlc;
- + 
- + 	return 1;
- + }
- + 
- + static int d_can_handle_bus_err(struct net_device *dev,
- + 				enum d_can_lec_type lec_type)
- + {
- + 	struct d_can_priv *priv = netdev_priv(dev);
- + 	struct net_device_stats *stats = &dev->stats;
- + 	struct can_frame *cf;
- + 	struct sk_buff *skb;
- + 
- + 	/*
- + 	 * early exit if no lec update or no error.
- + 	 * no lec update means that no CAN bus event has been detected
- + 	 * since CPU wrote 0x7 value to status reg.
- + 	 */
- + 	if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR)
- + 		return 0;
- + 
- + 	/* propagate the error condition to the CAN stack */
- + 	skb = alloc_can_err_skb(dev, &cf);
- + 	if (unlikely(!skb))
- + 		return 0;
- + 
- + 	/*
- + 	 * check for 'last error code' which tells us the
- + 	 * type of the last error to occur on the CAN bus
- + 	 */
- + 
- + 	/* common for all type of bus errors */
- + 	priv->can.can_stats.bus_error++;
- + 	stats->rx_errors++;
- + 	cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
- + 	cf->data[2] |= CAN_ERR_PROT_UNSPEC;
- + 
- + 	switch (lec_type) {
- + 	case LEC_STUFF_ERROR:
- + 		netdev_dbg(dev, "stuff error\n");
- + 		cf->data[2] |= CAN_ERR_PROT_STUFF;
- + 		break;
- + 	case LEC_FORM_ERROR:
- + 		netdev_dbg(dev, "form error\n");
- + 		cf->data[2] |= CAN_ERR_PROT_FORM;
- + 		break;
- + 	case LEC_ACK_ERROR:
- + 		netdev_dbg(dev, "ack error\n");
- + 		cf->data[2] |= (CAN_ERR_PROT_LOC_ACK |
- + 				CAN_ERR_PROT_LOC_ACK_DEL);
- + 		break;
- + 	case LEC_BIT1_ERROR:
- + 		netdev_dbg(dev, "bit1 error\n");
- + 		cf->data[2] |= CAN_ERR_PROT_BIT1;
- + 		break;
- + 	case LEC_BIT0_ERROR:
- + 		netdev_dbg(dev, "bit0 error\n");
- + 		cf->data[2] |= CAN_ERR_PROT_BIT0;
- + 		break;
- + 	case LEC_CRC_ERROR:
- + 		netdev_dbg(dev, "CRC error\n");
- + 		cf->data[2] |= (CAN_ERR_PROT_LOC_CRC_SEQ |
- + 				CAN_ERR_PROT_LOC_CRC_DEL);
- + 		break;
- + 	default:
- + 		break;
- + 	}
- + 
- + 	/* set a LEC value so that we can check for updates later */
- + 	d_can_write(priv, D_CAN_ES, LEC_UNUSED);
- + 
- + 	netif_receive_skb(skb);
- + 	stats->rx_packets++;
- + 	stats->rx_bytes += cf->can_dlc;
- + 
- + 	return 1;
- + }
- + 
- + static int d_can_poll(struct napi_struct *napi, int quota)
- + {
- + 	int lec_type = 0;
- + 	int work_done = 0;
- + 	struct net_device *dev = napi->dev;
- + 	struct d_can_priv *priv = netdev_priv(dev);
- + 
- + 	if (!priv->irqstatus)
- + 		goto end;
- + 
- + 	/* status events have the highest priority */
- + 	if (priv->irqstatus == STATUS_INTERRUPT) {
- + 		priv->current_status = d_can_read(priv, D_CAN_ES);
- + 
- + 		/* handle Tx/Rx events */
- + 		if (priv->current_status & D_CAN_ES_TXOK)
- + 			d_can_write(priv, D_CAN_ES,
- + 					priv->current_status & ~D_CAN_ES_TXOK);
- + 
- + 		if (priv->current_status & D_CAN_ES_RXOK)
- + 			d_can_write(priv, D_CAN_ES,
- + 					priv->current_status & ~D_CAN_ES_RXOK);
- + 
- + 		/* handle state changes */
- + 		if ((priv->current_status & D_CAN_ES_EWARN) &&
- + 				(!(priv->last_status & D_CAN_ES_EWARN))) {
- + 			netdev_dbg(dev, "entered error warning state\n");
- + 			work_done += d_can_handle_state_change(dev,
- + 						D_CAN_ERROR_WARNING);
- + 		}
- + 		if ((priv->current_status & D_CAN_ES_EPASS) &&
- + 				(!(priv->last_status & D_CAN_ES_EPASS))) {
- + 			netdev_dbg(dev, "entered error passive state\n");
- + 			work_done += d_can_handle_state_change(dev,
- + 						D_CAN_ERROR_PASSIVE);
- + 		}
- + 		if ((priv->current_status & D_CAN_ES_BOFF) &&
- + 				(!(priv->last_status & D_CAN_ES_BOFF))) {
- + 			netdev_dbg(dev, "entered bus off state\n");
- + 			work_done += d_can_handle_state_change(dev,
- + 						D_CAN_BUS_OFF);
- + 		}
- + 
- + 		/* handle bus recovery events */
- + 		if ((!(priv->current_status & D_CAN_ES_BOFF)) &&
- + 				(priv->last_status & D_CAN_ES_BOFF)) {
- + 			netdev_dbg(dev, "left bus off state\n");
- + 			priv->can.state = CAN_STATE_ERROR_ACTIVE;
- + 		}
- + 		if ((!(priv->current_status & D_CAN_ES_EPASS)) &&
- + 				(priv->last_status & D_CAN_ES_EPASS)) {
- + 			netdev_dbg(dev, "left error passive state\n");
- + 			priv->can.state = CAN_STATE_ERROR_ACTIVE;
- + 		}
- + 
- + 		priv->last_status = priv->current_status;
- + 
- + 		/* handle lec errors on the bus */
- + 		lec_type = d_can_has_handle_berr(priv);
- + 		if (lec_type)
- + 			work_done += d_can_handle_bus_err(dev, lec_type);
- + 	} else if ((priv->irqstatus >= D_CAN_MSG_OBJ_RX_FIRST) &&
- + 			(priv->irqstatus <= D_CAN_MSG_OBJ_RX_LAST)) {
- + 		/* handle events corresponding to receive message objects */
- + 		work_done += d_can_do_rx_poll(dev, (quota - work_done));
- + 	} else if ((priv->irqstatus >= D_CAN_MSG_OBJ_TX_FIRST) &&
- + 			(priv->irqstatus <= D_CAN_MSG_OBJ_TX_LAST)) {
- + 		/* handle events corresponding to transmit message objects */
- + 		d_can_do_tx(dev);
- + 	}
- + 
- + end:
- + 	if (work_done < quota) {
- + 		napi_complete(napi);
- + 		/* enable all IRQs */
- + 		d_can_interrupts(priv, ENABLE_ALL_INTERRUPTS);
- + 	}
- + 
- + 	return work_done;
- + }
- + 
- + static irqreturn_t d_can_isr(int irq, void *dev_id)
- + {
- + 	struct net_device *dev = (struct net_device *)dev_id;
- + 	struct d_can_priv *priv = netdev_priv(dev);
- + 
- + 	priv->irqstatus = d_can_read(priv, D_CAN_INT);
- + 	if (!priv->irqstatus)
- + 		return IRQ_NONE;
- + 
- + 	/* disable all interrupts and schedule the NAPI */
- + 	d_can_interrupts(priv, DISABLE_ALL_INTERRUPTS);
- + 	napi_schedule(&priv->napi);
- + 
- + 	return IRQ_HANDLED;
- + }
- + 
- + static int d_can_open(struct net_device *ndev)
- + {
- + 	int err;
- + 	struct d_can_priv *priv = netdev_priv(ndev);
- + 
- + 	/* Open common can device */
- + 	err = open_candev(ndev);
- + 	if (err) {
- + 		netdev_err(ndev, "open_candev() failed %d\n", err);
- + 		return err;
- + 	}
- + 
- + 	/* register interrupt handler for Message Object (MO)
- + 	 * and Error + status change (ES) */
- + 	err = request_irq(ndev->irq, &d_can_isr, IRQF_SHARED, ndev->name,
- + 				ndev);
- + 	if (err) {
- + 		netdev_err(ndev, "failed to request MO_ES interrupt\n");
- + 		goto exit_close_candev;
- + 	}
- + 
- + 	/* register interrupt handler for only Message Object */
- + 	err = request_irq(priv->irq_obj, &d_can_isr, IRQF_SHARED, ndev->name,
- + 				ndev);
- + 	if (err) {
- + 		netdev_err(ndev, "failed to request MO interrupt\n");
- + 		goto exit_free_irq;
- + 	}
- + 
- + 	/* start the d_can controller */
- + 	d_can_start(ndev);
- + 
- + 	napi_enable(&priv->napi);
- + 	netif_start_queue(ndev);
- + 
- + 	priv->opened = true;
- + 	return 0;
- + exit_free_irq:
- + 	free_irq(ndev->irq, ndev);
- + exit_close_candev:
- + 	close_candev(ndev);
- + 
- + 	return err;
- + }
- + 
- + static int d_can_close(struct net_device *ndev)
- + {
- + 	struct d_can_priv *priv = netdev_priv(ndev);
- + 
- + 	netif_stop_queue(ndev);
- + 	napi_disable(&priv->napi);
- + 	d_can_stop(ndev);
- + 	free_irq(ndev->irq, ndev);
- + 	free_irq(priv->irq_obj, ndev);
- + 	close_candev(ndev);
- + 	priv->opened = false;
- + 
- + 	return 0;
- + }
- + 
- + void d_can_reset_ram(struct d_can_priv *d_can, unsigned int instance,
- + 					unsigned int enable)
- + {
- + 	if (d_can->ram_init)
- + 		d_can->ram_init(instance, enable);
- + 
- + 	/* Give some time delay for DCAN RAM initialization */
- + 	udelay(1);
- + }
- + EXPORT_SYMBOL_GPL(d_can_reset_ram);
- + 
- + struct net_device *alloc_d_can_dev(int num_objs)
- + {
- + 	struct net_device *dev;
- + 	struct d_can_priv *priv;
- + 
- + 	dev = alloc_candev(sizeof(struct d_can_priv), num_objs/2);
- + 	if (!dev)
- + 		return NULL;
- + 
- + 	priv = netdev_priv(dev);
- + 	netif_napi_add(dev, &priv->napi, d_can_poll, num_objs/2);
- + 
- + 	priv->dev = dev;
- + 	priv->can.bittiming_const = &d_can_bittiming_const;
- + 	priv->can.do_set_mode = d_can_set_mode;
- + 	priv->can.do_get_berr_counter = d_can_get_berr_counter;
- + 	priv->can.ctrlmode_supported = (CAN_CTRLMODE_LOOPBACK |
- + 					CAN_CTRLMODE_LISTENONLY |
- + 					CAN_CTRLMODE_BERR_REPORTING |
- + 					CAN_CTRLMODE_3_SAMPLES);
- + 
- + 	return dev;
- + }
- + EXPORT_SYMBOL_GPL(alloc_d_can_dev);
- + 
- + #ifdef CONFIG_PM
- + int d_can_power_down(struct d_can_priv *d_can)
- + {
- + 	unsigned long time_out;
- + 	struct net_device *ndev = platform_get_drvdata(d_can->pdev);
- + 
- + 	d_can_set_bit(d_can, D_CAN_CTL, D_CAN_CTL_PDR);
- + 
- + 	/* Wait for the PDA bit to get set */
- + 	time_out = jiffies + msecs_to_jiffies(D_CAN_WAIT_COUNT);
- + 	while (!d_can_get_bit(d_can, D_CAN_ES, D_CAN_ES_PDA) &&
- + 				time_after(time_out, jiffies))
- + 		cpu_relax();
- + 
- + 	if (time_after(jiffies, time_out))
- + 		return -ETIMEDOUT;
- + 
- + 	if (d_can->opened)
- + 		d_can_stop(ndev);
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL_GPL(d_can_power_down);
- + 
- + int d_can_power_up(struct d_can_priv *d_can)
- + {
- + 	unsigned long time_out;
- + 	struct net_device *ndev = platform_get_drvdata(d_can->pdev);
- + 
- + 	d_can_clear_bit(d_can, D_CAN_CTL, D_CAN_CTL_PDR);
- + 	d_can_clear_bit(d_can, D_CAN_CTL, D_CAN_CTL_INIT);
- + 
- + 	/* Wait for the PDA bit to get clear */
- + 	time_out = jiffies + msecs_to_jiffies(D_CAN_WAIT_COUNT);
- + 	while (d_can_get_bit(d_can, D_CAN_ES, D_CAN_ES_PDA) &&
- + 				time_after(time_out, jiffies))
- + 		cpu_relax();
- + 
- + 	if (time_after(jiffies, time_out))
- + 		return -ETIMEDOUT;
- + 
- + 	if (d_can->opened)
- + 		d_can_start(ndev);
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL_GPL(d_can_power_up);
- + #else
- + #define d_can_power_down NULL
- + #define d_can_power_up NULL
- + #endif
- + 
- + void free_d_can_dev(struct net_device *dev)
- + {
- + 	free_candev(dev);
- + }
- + EXPORT_SYMBOL_GPL(free_d_can_dev);
- + 
- + static const struct net_device_ops d_can_netdev_ops = {
- + 	.ndo_open = d_can_open,
- + 	.ndo_stop = d_can_close,
- + 	.ndo_start_xmit = d_can_start_xmit,
- + };
- + 
- + int register_d_can_dev(struct net_device *dev)
- + {
- + 	/* we support local echo */
- + 	dev->flags |= IFF_ECHO;
- + 	dev->netdev_ops = &d_can_netdev_ops;
- + 
- + 	return register_candev(dev);
- + }
- + EXPORT_SYMBOL_GPL(register_d_can_dev);
- + 
- + void unregister_d_can_dev(struct net_device *dev)
- + {
- + 	struct d_can_priv *priv = netdev_priv(dev);
- + 
- + 	/* disable all interrupts */
- + 	d_can_interrupts(priv, DISABLE_ALL_INTERRUPTS);
- + 
- + 	unregister_candev(dev);
- + }
- + EXPORT_SYMBOL_GPL(unregister_d_can_dev);
- + 
- + MODULE_AUTHOR("AnilKumar Ch <anilkumar@ti.com>");
- + MODULE_LICENSE("GPL v2");
- + MODULE_VERSION(D_CAN_VERSION);
- + MODULE_DESCRIPTION(D_CAN_DRV_DESC);
- diff -crN linux-3.2.1_o/drivers/net/can/d_can/d_can.h linux-3.2.1/drivers/net/can/d_can/d_can.h
- *** linux-3.2.1_o/drivers/net/can/d_can/d_can.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/drivers/net/can/d_can/d_can.h	2014-05-15 13:25:14.583247951 +0900
- ***************
- *** 0 ****
- --- 1,72 ----
- + /*
- +  * CAN bus driver for Bosch D_CAN controller
- +  *
- +  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- +  *
- +  * Borrowed from C_CAN driver
- +  * Copyright (C) 2010 ST Microelectronics
- +  * - Bhupesh Sharma <bhupesh.sharma@st.com>
- +  *
- +  * Borrowed heavily from the C_CAN driver originally written by:
- +  * Copyright (C) 2007
- +  * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
- +  * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
- +  *
- +  * Bosch D_CAN controller is compliant to CAN protocol version 2.0 part A and B.
- +  * Bosch D_CAN user manual can be obtained from:
- +  * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/can/
- +  * d_can_users_manual_111.pdf
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #ifndef D_CAN_H
- + #define D_CAN_H
- + 
- + #define D_CAN_DRV_NAME	"d_can"
- + #define D_CAN_VERSION	"1.0"
- + #define D_CAN_DRV_DESC	"CAN bus driver for Bosch D_CAN controller " \
- + 			D_CAN_VERSION
- + 
- + /* d_can private data structure */
- + struct d_can_priv {
- + 	struct can_priv can;	/* must be the first member */
- + 	struct napi_struct napi;
- + 	struct net_device *dev;
- + 	struct platform_device *pdev;
- + 	int current_status;
- + 	int last_status;
- + 	unsigned int irqstatus;
- + 	void __iomem *base;
- + 	u32 napi_weight;
- + 	struct clk *fck;
- + 	struct clk *ick;
- + 	unsigned int irq;	/* device IRQ number, for all MO and ES	*/
- + 	unsigned int irq_obj;	/* device IRQ number for only Msg Object */
- + 	unsigned int irq_parity; /* device IRQ number for parity error */
- + 	unsigned long irq_flags; /* for request_irq() */
- + 	unsigned int tx_next;
- + 	unsigned int tx_echo;
- + 	unsigned int rx_next;
- + 	bool opened;
- + 	void *priv;		/* for board-specific data */
- + 	void (*ram_init) (unsigned int, unsigned int);
- + };
- + 
- + struct net_device *alloc_d_can_dev(int);
- + void free_d_can_dev(struct net_device *dev);
- + int d_can_power_up(struct d_can_priv *d_can);
- + int d_can_power_down(struct d_can_priv *d_can);
- + int register_d_can_dev(struct net_device *dev);
- + void unregister_d_can_dev(struct net_device *dev);
- + void d_can_reset_ram(struct d_can_priv *d_can, unsigned int instance,
- + 					unsigned int enable);
- + 
- + #endif /* D_CAN_H */
- diff -crN linux-3.2.1_o/drivers/net/can/d_can/d_can_platform.c linux-3.2.1/drivers/net/can/d_can/d_can_platform.c
- *** linux-3.2.1_o/drivers/net/can/d_can/d_can_platform.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/drivers/net/can/d_can/d_can_platform.c	2014-05-15 13:25:14.583247951 +0900
- ***************
- *** 0 ****
- --- 1,288 ----
- + /*
- +  * Platform CAN bus driver for Bosch D_CAN controller
- +  *
- +  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- +  *
- +  * Borrowed from C_CAN driver
- +  * Copyright (C) 2010 ST Microelectronics
- +  * - Bhupesh Sharma <bhupesh.sharma@st.com>
- +  *
- +  * Borrowed heavily from the C_CAN driver originally written by:
- +  * Copyright (C) 2007
- +  * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
- +  * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
- +  *
- +  * Bosch D_CAN controller is compliant to CAN protocol version 2.0 part A and B.
- +  * Bosch D_CAN user manual can be obtained from:
- +  * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/can/
- +  * d_can_users_manual_111.pdf
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + /*
- +  * Your platform definitions should specify module ram offsets and interrupt
- +  * number to use as follows:
- +  *
- +  * static struct d_can_platform_data am33xx_evm_d_can_pdata = {
- +  *	.num_of_msg_objs	= 64,
- +  *	.dma_support		= false,
- +  *	.ram_init		= d_can_hw_raminit,
- +  * };
- +  *
- +  * Please see include/linux/can/platform/d_can.h for description of
- +  * above fields.
- +  *
- +  */
- + 
- + #include <linux/kernel.h>
- + #include <linux/module.h>
- + #include <linux/interrupt.h>
- + #include <linux/delay.h>
- + #include <linux/netdevice.h>
- + #include <linux/if_arp.h>
- + #include <linux/if_ether.h>
- + #include <linux/list.h>
- + #include <linux/io.h>
- + #include <linux/platform_device.h>
- + #include <linux/can/platform/d_can.h>
- + #include <linux/clk.h>
- + #include <linux/pm_runtime.h>
- + #include <linux/slab.h>
- + #include <linux/can/dev.h>
- + 
- + #include "d_can.h"
- + 
- + static int __devinit d_can_plat_probe(struct platform_device *pdev)
- + {
- + 	int ret = 0;
- + 	void __iomem *addr;
- + 	struct net_device *ndev;
- + 	struct d_can_priv *priv;
- + 	struct resource *mem;
- + 	struct d_can_platform_data *pdata;
- + 	struct clk *fck;
- + 
- + 	pdata = pdev->dev.platform_data;
- + 	if (!pdata) {
- + 		dev_err(&pdev->dev, "No platform data\n");
- + 		goto exit;
- + 	}
- + 
- + 	/* allocate the d_can device */
- + 	ndev = alloc_d_can_dev(pdata->num_of_msg_objs);
- + 	if (!ndev) {
- + 		ret = -ENOMEM;
- + 		dev_err(&pdev->dev, "alloc_d_can_dev failed\n");
- + 		goto exit;
- + 	}
- + 
- + 	priv = netdev_priv(ndev);
- + 	fck = clk_get(&pdev->dev, "fck");
- + 	if (IS_ERR(fck)) {
- + 		dev_err(&pdev->dev, "fck is not found\n");
- + 		ret = -ENODEV;
- + 		goto exit_free_ndev;
- + 	}
- + 
- + 	/* get the platform data */
- + 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- + 	if (!mem) {
- + 		ret = -ENODEV;
- + 		dev_err(&pdev->dev, "No mem resource\n");
- + 		goto exit_clk_put;
- + 	}
- + 
- + 	if (!request_mem_region(mem->start, resource_size(mem),
- + 				D_CAN_DRV_NAME)) {
- + 		dev_err(&pdev->dev, "resource unavailable\n");
- + 		ret = -EBUSY;
- + 		goto exit_clk_put;
- + 	}
- + 
- + 	addr = ioremap(mem->start, resource_size(mem));
- + 	if (!addr) {
- + 		dev_err(&pdev->dev, "ioremap failed\n");
- + 		ret = -ENOMEM;
- + 		goto exit_release_mem;
- + 	}
- + 
- + 	/* IRQ specific to Error and status & can be used for Message Object */
- + 	ndev->irq = platform_get_irq_byname(pdev, "d_can_ms");
- + 	if (!ndev->irq) {
- + 		dev_err(&pdev->dev, "No irq0 resource\n");
- + 		goto exit_iounmap;
- + 	}
- + 
- + 	/* IRQ specific for Message Object */
- + 	priv->irq_obj = platform_get_irq_byname(pdev, "d_can_mo");
- + 	if (!priv->irq_obj) {
- + 		dev_err(&pdev->dev, "No irq1 resource\n");
- + 		goto exit_iounmap;
- + 	}
- + 
- + 	pm_runtime_enable(&pdev->dev);
- + 	pm_runtime_get_sync(&pdev->dev);
- + 	priv->pdev = pdev;
- + 	priv->base = addr;
- + 	priv->can.clock.freq = clk_get_rate(fck);
- + 	priv->ram_init = pdata->ram_init;
- + 	priv->opened = false;
- + 
- + 	platform_set_drvdata(pdev, ndev);
- + 	SET_NETDEV_DEV(ndev, &pdev->dev);
- + 
- + 	ret = register_d_can_dev(ndev);
- + 	if (ret) {
- + 		dev_err(&pdev->dev, "registering %s failed (err=%d)\n",
- + 				D_CAN_DRV_NAME, ret);
- + 		goto exit_free_device;
- + 	}
- + 
- + 	/* Initialize DCAN RAM */
- + 	d_can_reset_ram(priv, pdev->id, 1);
- + 
- + 	dev_info(&pdev->dev, "device registered (irq=%d, irq_obj=%d)\n",
- + 						ndev->irq, priv->irq_obj);
- + 
- + 	return 0;
- + 
- + exit_free_device:
- + 	platform_set_drvdata(pdev, NULL);
- + 	pm_runtime_disable(&pdev->dev);
- + exit_iounmap:
- + 	iounmap(addr);
- + exit_release_mem:
- + 	release_mem_region(mem->start, resource_size(mem));
- + exit_clk_put:
- + 	clk_put(fck);
- + exit_free_ndev:
- + 	free_d_can_dev(ndev);
- + exit:
- + 	dev_err(&pdev->dev, "probe failed\n");
- + 
- + 	return ret;
- + }
- + 
- + static int __devexit d_can_plat_remove(struct platform_device *pdev)
- + {
- + 	struct net_device *ndev = platform_get_drvdata(pdev);
- + 	struct d_can_priv *priv = netdev_priv(ndev);
- + 	struct resource *mem;
- + 
- + 	/* De-initialize DCAN RAM */
- + 	d_can_reset_ram(priv, pdev->id, 0);
- + 
- + 	unregister_d_can_dev(ndev);
- + 	platform_set_drvdata(pdev, NULL);
- + 
- + 	free_d_can_dev(ndev);
- + 	iounmap(priv->base);
- + 
- + 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- + 	release_mem_region(mem->start, resource_size(mem));
- + 
- + 	pm_runtime_put_sync(&pdev->dev);
- + 	pm_runtime_disable(&pdev->dev);
- + 
- + 	return 0;
- + }
- + 
- + #ifdef CONFIG_PM
- + static int d_can_suspend(struct platform_device *pdev, pm_message_t state)
- + {
- + 	int ret;
- + 	struct net_device *ndev = platform_get_drvdata(pdev);
- + 	struct d_can_priv *priv = netdev_priv(ndev);
- + 
- + 	if (netif_running(ndev)) {
- + 		netif_stop_queue(ndev);
- + 		netif_device_detach(ndev);
- + 	}
- + 
- + 	ret = d_can_power_down(priv);
- + 	if (ret) {
- + 		dev_err(&pdev->dev, "Not entered power down mode\n");
- + 		return ret;
- + 	}
- + 
- + 	priv->can.state = CAN_STATE_SLEEPING;
- + 
- + 	/* De-initialize DCAN RAM */
- + 	d_can_reset_ram(priv, pdev->id, 0);
- + 
- + 	/* Disable the module */
- + 	pm_runtime_put_sync(&pdev->dev);
- + 
- + 	return 0;
- + }
- + 
- + static int d_can_resume(struct platform_device *pdev)
- + {
- + 	int ret;
- + 
- + 	struct net_device *ndev = platform_get_drvdata(pdev);
- + 	struct d_can_priv *priv = netdev_priv(ndev);
- + 
- + 	/* Enable the module */
- + 	pm_runtime_get_sync(&pdev->dev);
- + 
- + 	/* Initialize DCAN RAM */
- + 	d_can_reset_ram(priv, pdev->id, 1);
- + 
- + 	ret = d_can_power_up(priv);
- + 	if (ret) {
- + 		dev_err(&pdev->dev, "Not came out from power down mode\n");
- + 		return ret;
- + 	}
- + 
- + 	priv->can.state = CAN_STATE_ERROR_ACTIVE;
- + 
- + 	if (netif_running(ndev)) {
- + 		netif_device_attach(ndev);
- + 		netif_start_queue(ndev);
- + 	}
- + 
- + 	return 0;
- + }
- + #else
- + #define d_can_suspend NULL
- + #define d_can_resume NULL
- + #endif
- + 
- + static struct platform_driver d_can_plat_driver = {
- + 	.driver = {
- + 		.name	= D_CAN_DRV_NAME,
- + 		.owner	= THIS_MODULE,
- + 	},
- + 	.probe		= d_can_plat_probe,
- + 	.remove		= __devexit_p(d_can_plat_remove),
- + 	.suspend	= d_can_suspend,
- + 	.resume		= d_can_resume,
- + };
- + 
- + static int __init d_can_plat_init(void)
- + {
- + 	printk(KERN_INFO D_CAN_DRV_DESC "\n");
- + 	return platform_driver_register(&d_can_plat_driver);
- + }
- + module_init(d_can_plat_init);
- + 
- + static void __exit d_can_plat_exit(void)
- + {
- + 	printk(KERN_INFO D_CAN_DRV_DESC " unloaded\n");
- + 	platform_driver_unregister(&d_can_plat_driver);
- + }
- + module_exit(d_can_plat_exit);
- + 
- + MODULE_AUTHOR("AnilKumar Ch <anilkumar@ti.com>");
- + MODULE_LICENSE("GPL v2");
- + MODULE_VERSION(D_CAN_VERSION);
- + MODULE_DESCRIPTION(D_CAN_DRV_DESC);
- diff -crN linux-3.2.1_o/drivers/net/can/d_can/Kconfig linux-3.2.1/drivers/net/can/d_can/Kconfig
- *** linux-3.2.1_o/drivers/net/can/d_can/Kconfig	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/drivers/net/can/d_can/Kconfig	2014-05-15 13:25:14.583247951 +0900
- ***************
- *** 0 ****
- --- 1,14 ----
- + menuconfig CAN_D_CAN
- + 	tristate "Bosch D_CAN devices"
- + 	depends on CAN_DEV && HAS_IOMEM
- + 
- + if CAN_D_CAN
- + 
- + config CAN_D_CAN_PLATFORM
- + 	tristate "Generic Platform Bus based D_CAN driver"
- + 	---help---
- + 	  This driver adds support for the D_CAN chips connected to
- + 	  the "platform bus" (Linux abstraction for directly to the
- + 	  processor attached devices) which can be found on am335x
- + 	  and dm814x boards from TI (http://www.ti.com).
- + endif
- diff -crN linux-3.2.1_o/drivers/net/can/d_can/Makefile linux-3.2.1/drivers/net/can/d_can/Makefile
- *** linux-3.2.1_o/drivers/net/can/d_can/Makefile	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/drivers/net/can/d_can/Makefile	2014-05-15 13:25:14.583247951 +0900
- ***************
- *** 0 ****
- --- 1,8 ----
- + #
- + #  Makefile for the Bosch D_CAN controller drivers.
- + #
- + 
- + obj-$(CONFIG_CAN_D_CAN) += d_can.o
- + obj-$(CONFIG_CAN_D_CAN_PLATFORM) += d_can_platform.o
- + 
- + ccflags-$(CONFIG_CAN_DEBUG_DEVICES) := -DDEBUG
- diff -crN linux-3.2.1_o/drivers/net/can/Kconfig linux-3.2.1/drivers/net/can/Kconfig
- *** linux-3.2.1_o/drivers/net/can/Kconfig	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/net/can/Kconfig	2014-05-15 13:25:14.583247951 +0900
- ***************
- *** 116,121 ****
- --- 116,123 ----
-   
-   source "drivers/net/can/c_can/Kconfig"
-   
- + source "drivers/net/can/d_can/Kconfig"
- + 
-   source "drivers/net/can/usb/Kconfig"
-   
-   source "drivers/net/can/softing/Kconfig"
- diff -crN linux-3.2.1_o/drivers/net/can/Makefile linux-3.2.1/drivers/net/can/Makefile
- *** linux-3.2.1_o/drivers/net/can/Makefile	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/net/can/Makefile	2014-05-15 13:25:14.583247951 +0900
- ***************
- *** 14,19 ****
- --- 14,20 ----
-   obj-$(CONFIG_CAN_SJA1000)	+= sja1000/
-   obj-$(CONFIG_CAN_MSCAN)		+= mscan/
-   obj-$(CONFIG_CAN_C_CAN)		+= c_can/
- + obj-$(CONFIG_CAN_D_CAN)		+= d_can/
-   obj-$(CONFIG_CAN_AT91)		+= at91_can.o
-   obj-$(CONFIG_CAN_TI_HECC)	+= ti_hecc.o
-   obj-$(CONFIG_CAN_MCP251X)	+= mcp251x.o
- diff -crN linux-3.2.1_o/drivers/net/ethernet/ti/cpsw_ale.c linux-3.2.1/drivers/net/ethernet/ti/cpsw_ale.c
- *** linux-3.2.1_o/drivers/net/ethernet/ti/cpsw_ale.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/drivers/net/ethernet/ti/cpsw_ale.c	2014-05-15 13:25:14.586776106 +0900
- ***************
- *** 0 ****
- --- 1,982 ----
- + /*
- +  * Texas Instruments 3-Port Ethernet Switch Address Lookup Engine
- +  *
- +  * Copyright (C) 2010 Texas Instruments
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + #include <linux/kernel.h>
- + #include <linux/platform_device.h>
- + #include <linux/seq_file.h>
- + #include <linux/slab.h>
- + #include <linux/err.h>
- + #include <linux/io.h>
- + #include <linux/stat.h>
- + #include <linux/sysfs.h>
- + #include <linux/export.h>
- + #include <linux/module.h>
- + #include <linux/etherdevice.h>
- + 
- + #include "cpsw_ale.h"
- + 
- + #define BITMASK(bits)		(BIT(bits) - 1)
- + #define ADDR_FMT_STR		"%02x:%02x:%02x:%02x:%02x:%02x"
- + #define ADDR_FMT_ARGS(addr)	(addr)[0], (addr)[1], (addr)[2], \
- + 				(addr)[3], (addr)[4], (addr)[5]
- + #define ALE_ENTRY_BITS		68
- + #define ALE_ENTRY_WORDS		DIV_ROUND_UP(ALE_ENTRY_BITS, 32)
- + 
- + /* ALE Registers */
- + #define ALE_IDVER		0x00
- + #define ALE_CONTROL		0x08
- + #define ALE_PRESCALE		0x10
- + #define ALE_UNKNOWNVLAN		0x18
- + #define ALE_TABLE_CONTROL	0x20
- + #define ALE_TABLE		0x34
- + #define ALE_PORTCTL		0x40
- + 
- + #define ALE_TABLE_WRITE		BIT(31)
- + 
- + #define ALE_TYPE_FREE			0
- + #define ALE_TYPE_ADDR			1
- + #define ALE_TYPE_VLAN			2
- + #define ALE_TYPE_VLAN_ADDR		3
- + 
- + #define ALE_UCAST_PERSISTANT		0
- + #define ALE_UCAST_UNTOUCHED		1
- + #define ALE_UCAST_OUI			2
- + #define ALE_UCAST_TOUCHED		3
- + 
- + #define ALE_MCAST_FWD			0
- + #define ALE_MCAST_BLOCK_LEARN_FWD	1
- + #define ALE_MCAST_FWD_LEARN		2
- + #define ALE_MCAST_FWD_2			3
- + 
- + /* the following remap params into members of cpsw_ale */
- + #define ale_regs	params.ale_regs
- + #define ale_entries	params.ale_entries
- + #define ale_ports	params.ale_ports
- + 
- + static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
- + {
- + 	int idx;
- + 
- + 	idx    = start / 32;
- + 	start -= idx * 32;
- + 	idx    = 2 - idx; /* flip */
- + 	return (ale_entry[idx] >> start) & BITMASK(bits);
- + }
- + 
- + static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits,
- + 				      u32 value)
- + {
- + 	int idx;
- + 
- + 	value &= BITMASK(bits);
- + 	idx    = start / 32;
- + 	start -= idx * 32;
- + 	idx    = 2 - idx; /* flip */
- + 	ale_entry[idx] &= ~(BITMASK(bits) << start);
- + 	ale_entry[idx] |=  (value << start);
- + }
- + 
- + #define DEFINE_ALE_FIELD(name, start, bits)				\
- + static inline int cpsw_ale_get_##name(u32 *ale_entry)			\
- + {									\
- + 	return cpsw_ale_get_field(ale_entry, start, bits);		\
- + }									\
- + static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value)	\
- + {									\
- + 	cpsw_ale_set_field(ale_entry, start, bits, value);		\
- + }
- + 
- + DEFINE_ALE_FIELD(entry_type,		60,	2)
- + DEFINE_ALE_FIELD(vlan_id,		48,	12)
- + DEFINE_ALE_FIELD(mcast_state,		62,	2)
- + DEFINE_ALE_FIELD(port_mask,		66,     3)
- + DEFINE_ALE_FIELD(super,			65,	1)
- + DEFINE_ALE_FIELD(ucast_type,		62,     2)
- + DEFINE_ALE_FIELD(port_num,		66,     2)
- + DEFINE_ALE_FIELD(blocked,		65,     1)
- + DEFINE_ALE_FIELD(secure,		64,     1)
- + DEFINE_ALE_FIELD(vlan_untag_force,	24,	3)
- + DEFINE_ALE_FIELD(vlan_reg_mcast,	16,	3)
- + DEFINE_ALE_FIELD(vlan_unreg_mcast,	8,	3)
- + DEFINE_ALE_FIELD(vlan_member_list,	0,	3)
- + DEFINE_ALE_FIELD(mcast,			40,     1)
- + 
- + /* The MAC address field in the ALE entry cannot be macroized as above */
- + static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr)
- + {
- + 	int i;
- + 
- + 	for (i = 0; i < 6; i++)
- + 		addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8);
- + }
- + 
- + static inline void cpsw_ale_set_addr(u32 *ale_entry, u8 *addr)
- + {
- + 	int i;
- + 
- + 	for (i = 0; i < 6; i++)
- + 		cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]);
- + }
- + 
- + static int cpsw_ale_read(struct cpsw_ale *ale, int idx, u32 *ale_entry)
- + {
- + 	int i;
- + 
- + 	WARN_ON(idx > ale->ale_entries);
- + 
- + 	__raw_writel(idx, ale->ale_regs + ALE_TABLE_CONTROL);
- + 
- + 	for (i = 0; i < ALE_ENTRY_WORDS; i++)
- + 		ale_entry[i] = __raw_readl(ale->ale_regs + ALE_TABLE + 4 * i);
- + 
- + 	return idx;
- + }
- + 
- + static int cpsw_ale_write(struct cpsw_ale *ale, int idx, u32 *ale_entry)
- + {
- + 	int i;
- + 
- + 	WARN_ON(idx > ale->ale_entries);
- + 
- + 	for (i = 0; i < ALE_ENTRY_WORDS; i++)
- + 		__raw_writel(ale_entry[i], ale->ale_regs + ALE_TABLE + 4 * i);
- + 
- + 	__raw_writel(idx | ALE_TABLE_WRITE, ale->ale_regs + ALE_TABLE_CONTROL);
- + 
- + 	return idx;
- + }
- + 
- + int cpsw_ale_match_addr(struct cpsw_ale *ale, u8* addr, u16 vid)
- + {
- + 	u32 ale_entry[ALE_ENTRY_WORDS];
- + 	int type, idx;
- + 
- + 	for (idx = 0; idx < ale->ale_entries; idx++) {
- + 		u8 entry_addr[6];
- + 
- + 		cpsw_ale_read(ale, idx, ale_entry);
- + 		type = cpsw_ale_get_entry_type(ale_entry);
- + 		if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
- + 			continue;
- + 		if (cpsw_ale_get_vlan_id(ale_entry) != vid)
- + 			continue;
- + 		cpsw_ale_get_addr(ale_entry, entry_addr);
- + 		if (memcmp(entry_addr, addr, 6) == 0)
- + 			return idx;
- + 	}
- + 	return -ENOENT;
- + }
- + 
- + int cpsw_ale_match_vlan(struct cpsw_ale *ale, u16 vid)
- + {
- + 	u32 ale_entry[ALE_ENTRY_WORDS];
- + 	int type, idx;
- + 
- + 	for (idx = 0; idx < ale->ale_entries; idx++) {
- + 		cpsw_ale_read(ale, idx, ale_entry);
- + 		type = cpsw_ale_get_entry_type(ale_entry);
- + 		if (type != ALE_TYPE_VLAN)
- + 			continue;
- + 		if (cpsw_ale_get_vlan_id(ale_entry) == vid)
- + 			return idx;
- + 	}
- + 	return -ENOENT;
- + }
- + 
- + static int cpsw_ale_match_free(struct cpsw_ale *ale)
- + {
- + 	u32 ale_entry[ALE_ENTRY_WORDS];
- + 	int type, idx;
- + 
- + 	for (idx = 0; idx < ale->ale_entries; idx++) {
- + 		cpsw_ale_read(ale, idx, ale_entry);
- + 		type = cpsw_ale_get_entry_type(ale_entry);
- + 		if (type == ALE_TYPE_FREE)
- + 			return idx;
- + 	}
- + 	return -ENOENT;
- + }
- + 
- + static int cpsw_ale_find_ageable(struct cpsw_ale *ale)
- + {
- + 	u32 ale_entry[ALE_ENTRY_WORDS];
- + 	int type, idx;
- + 
- + 	for (idx = 0; idx < ale->ale_entries; idx++) {
- + 		cpsw_ale_read(ale, idx, ale_entry);
- + 		type = cpsw_ale_get_entry_type(ale_entry);
- + 		if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
- + 			continue;
- + 		if (cpsw_ale_get_mcast(ale_entry))
- + 			continue;
- + 		type = cpsw_ale_get_ucast_type(ale_entry);
- + 		if (type != ALE_UCAST_PERSISTANT &&
- + 		    type != ALE_UCAST_OUI)
- + 			return idx;
- + 	}
- + 	return -ENOENT;
- + }
- + 
- + static void cpsw_ale_flush_mcast(struct cpsw_ale *ale, u32 *ale_entry,
- + 				 int port_mask)
- + {
- + 	int mask;
- + 
- + 	mask = cpsw_ale_get_port_mask(ale_entry);
- + 	if ((mask & port_mask) == 0)
- + 		return; /* ports dont intersect, not interested */
- + 	mask &= ~port_mask;
- + 
- + 	/* free if only remaining port is host port */
- + 	if (mask)
- + 		cpsw_ale_set_port_mask(ale_entry, mask);
- + 	else
- + 		cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
- + }
- + 
- + int cpsw_ale_flush_multicast(struct cpsw_ale *ale, int port_mask)
- + {
- + 	u32 ale_entry[ALE_ENTRY_WORDS];
- + 	int ret, idx;
- + 
- + 	for (idx = 0; idx < ale->ale_entries; idx++) {
- + 		cpsw_ale_read(ale, idx, ale_entry);
- + 		ret = cpsw_ale_get_entry_type(ale_entry);
- + 		if (ret != ALE_TYPE_ADDR && ret != ALE_TYPE_VLAN_ADDR)
- + 			continue;
- + 
- + 		if (cpsw_ale_get_mcast(ale_entry)) {
- + 			u8 addr[6];
- + 
- + 			cpsw_ale_get_addr(ale_entry, addr);
- + 			if (!is_broadcast_ether_addr(addr))
- + 				cpsw_ale_flush_mcast(ale, ale_entry, port_mask);
- + 		}
- + 
- + 		cpsw_ale_write(ale, idx, ale_entry);
- + 	}
- + 	return 0;
- + }
- + 
- + void cpsw_ale_flush_vlan_multicast(struct cpsw_ale *ale, u16 vid, int port_mask)
- + {
- + 	u32 ale_entry[ALE_ENTRY_WORDS];
- + 	int ret, idx;
- + 
- + 	for (idx = 0; idx < ale->ale_entries; idx++) {
- + 		cpsw_ale_read(ale, idx, ale_entry);
- + 		ret = cpsw_ale_get_entry_type(ale_entry);
- + 		if (ret != ALE_TYPE_VLAN_ADDR)
- + 			continue;
- + 		if (cpsw_ale_get_vlan_id(ale_entry) != vid)
- + 			continue;
- + 
- + 		if (cpsw_ale_get_mcast(ale_entry)) {
- + 			u8 addr[6];
- + 
- + 			cpsw_ale_get_addr(ale_entry, addr);
- + 			if (!is_broadcast_ether_addr(addr)) {
- + 				cpsw_ale_flush_mcast(ale, ale_entry, port_mask);
- + 				cpsw_ale_write(ale, idx, ale_entry);
- + 			}
- + 		}
- + 	}
- + }
- + 
- + static void cpsw_ale_flush_ucast(struct cpsw_ale *ale, u32 *ale_entry,
- + 				 int port_mask)
- + {
- + 	int port;
- + 
- + 	port = cpsw_ale_get_port_num(ale_entry);
- + 	if ((BIT(port) & port_mask) == 0)
- + 		return; /* ports dont intersect, not interested */
- + 	cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
- + }
- + 
- + int cpsw_ale_flush(struct cpsw_ale *ale, int port_mask)
- + {
- + 	u32 ale_entry[ALE_ENTRY_WORDS];
- + 	int ret, idx;
- + 
- + 	for (idx = 0; idx < ale->ale_entries; idx++) {
- + 		cpsw_ale_read(ale, idx, ale_entry);
- + 		ret = cpsw_ale_get_entry_type(ale_entry);
- + 		if (ret != ALE_TYPE_ADDR && ret != ALE_TYPE_VLAN_ADDR)
- + 			continue;
- + 
- + 		if (cpsw_ale_get_mcast(ale_entry))
- + 			cpsw_ale_flush_mcast(ale, ale_entry, port_mask);
- + 		else
- + 			cpsw_ale_flush_ucast(ale, ale_entry, port_mask);
- + 
- + 		cpsw_ale_write(ale, idx, ale_entry);
- + 	}
- + 	return 0;
- + }
- + 
- + static int cpsw_ale_dump_mcast(u32 *ale_entry, char *buf, int len)
- + {
- + 	int outlen = 0;
- + 	static const char *str_mcast_state[] = {"f", "blf", "lf", "f"};
- + 	int mcast_state = cpsw_ale_get_mcast_state(ale_entry);
- + 	int port_mask   = cpsw_ale_get_port_mask(ale_entry);
- + 	int super       = cpsw_ale_get_super(ale_entry);
- + 
- + 	outlen += snprintf(buf + outlen, len - outlen,
- + 			   "mcstate: %s(%d), ", str_mcast_state[mcast_state],
- + 			   mcast_state);
- + 	outlen += snprintf(buf + outlen, len - outlen,
- + 			   "port mask: %x, %ssuper\n", port_mask,
- + 			   super ? "" : "no ");
- + 	return outlen;
- + }
- + 
- + static int cpsw_ale_dump_ucast(u32 *ale_entry, char *buf, int len)
- + {
- + 	int outlen = 0;
- + 	static const char *str_ucast_type[] = {"persistant", "untouched",
- + 					       "oui", "touched"};
- + 	int ucast_type  = cpsw_ale_get_ucast_type(ale_entry);
- + 	int port_num    = cpsw_ale_get_port_num(ale_entry);
- + 	int secure      = cpsw_ale_get_secure(ale_entry);
- + 	int blocked     = cpsw_ale_get_blocked(ale_entry);
- + 
- + 	outlen += snprintf(buf + outlen, len - outlen,
- + 			   "uctype: %s(%d), ", str_ucast_type[ucast_type],
- + 			   ucast_type);
- + 	outlen += snprintf(buf + outlen, len - outlen,
- + 			   "port: %d%s%s\n", port_num, secure ? ", Secure" : "",
- + 			   blocked ? ", Blocked" : "");
- + 	return outlen;
- + }
- + 
- + static int cpsw_ale_dump_vlan(u32 *ale_entry, char *buf, int len)
- + {
- + 	int outlen = 0;
- + 	int untag_force = cpsw_ale_get_vlan_untag_force(ale_entry);
- + 	int reg_mcast   = cpsw_ale_get_vlan_reg_mcast(ale_entry);
- + 	int unreg_mcast = cpsw_ale_get_vlan_unreg_mcast(ale_entry);
- + 	int member_list = cpsw_ale_get_vlan_member_list(ale_entry);
- + 
- + 	outlen += snprintf(buf + outlen, len - outlen,
- + 			   "vlanuntag: %x, ", untag_force);
- + 	outlen += snprintf(buf + outlen, len - outlen,
- + 			   "vlanregmcast: %x, ", reg_mcast);
- + 	outlen += snprintf(buf + outlen, len - outlen,
- + 			   "vlanunregmcast: %x, ", unreg_mcast);
- + 	outlen += snprintf(buf + outlen, len - outlen,
- + 			   "vlanmemberlist: %x\n", member_list);
- + 	return outlen;
- + }
- + 
- + static int cpsw_ale_dump_entry(int idx, u32 *ale_entry, char *buf, int len)
- + {
- + 	int type, outlen = 0;
- + 	u8 addr[6];
- + 	static const char *str_type[] = {"free", "addr", "vlan", "vlan+addr"};
- + 
- + 	type = cpsw_ale_get_entry_type(ale_entry);
- + 	if (type == ALE_TYPE_FREE)
- + 		return outlen;
- + 
- + 	if (idx >= 0) {
- + 		outlen += snprintf(buf + outlen, len - outlen,
- + 				   "index %d, ", idx);
- + 	}
- + 
- + 	outlen += snprintf(buf + outlen, len - outlen, "raw: %08x %08x %08x, ",
- + 			   ale_entry[0], ale_entry[1], ale_entry[2]);
- + 
- + 	outlen += snprintf(buf + outlen, len - outlen,
- + 			   "type: %s(%d), ", str_type[type], type);
- + 
- + 	if (type == ALE_TYPE_VLAN || type == ALE_TYPE_VLAN_ADDR) {
- + 		outlen += snprintf(buf + outlen, len - outlen, "vlan: %d, ",
- + 				   cpsw_ale_get_vlan_id(ale_entry));
- + 	}
- + 
- + 	if (type == ALE_TYPE_ADDR || type == ALE_TYPE_VLAN_ADDR) {
- + 		cpsw_ale_get_addr(ale_entry, addr);
- + 		outlen += snprintf(buf + outlen, len - outlen,
- + 			"addr: " ADDR_FMT_STR ", ", ADDR_FMT_ARGS(addr));
- + 		outlen += cpsw_ale_get_mcast(ale_entry) ?
- + 			cpsw_ale_dump_mcast(ale_entry, buf + outlen,
- + 						len - outlen) :
- + 			cpsw_ale_dump_ucast(ale_entry, buf + outlen,
- + 						len - outlen);
- + 	} else {
- + 		/* type == ALE_TYPE_VLAN */
- + 		outlen += cpsw_ale_dump_vlan(ale_entry, buf + outlen,
- + 					     len - outlen);
- + 	}
- + 	return outlen;
- + }
- + 
- + int cpsw_ale_dump(struct cpsw_ale *ale, int index, char *buf, int len)
- + {
- + 	int outlen = 0, idx;
- + 	u32 ale_entry[ALE_ENTRY_WORDS];
- + 
- + 	if (index) {
- + 		cpsw_ale_read(ale, index, ale_entry);
- + 		outlen += cpsw_ale_dump_entry(index, ale_entry,
- + 				buf + outlen, len - outlen);
- + 	} else {
- + 		for (idx = 0; idx < ale->ale_entries; idx++) {
- + 			cpsw_ale_read(ale, idx, ale_entry);
- + 			outlen += cpsw_ale_dump_entry(idx, ale_entry,
- + 					buf + outlen, len - outlen);
- + 		}
- + 	}
- + 	return outlen;
- + }
- + 
- + int cpsw_ale_add_ucast(struct cpsw_ale *ale, u8 *addr, int port, int flags)
- + {
- + 	u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
- + 	int idx;
- + 
- + 	cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
- + 	cpsw_ale_set_addr(ale_entry, addr);
- + 	cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
- + 	cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
- + 	cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
- + 	cpsw_ale_set_port_num(ale_entry, port);
- + 
- + 	idx = cpsw_ale_match_addr(ale, addr, 0);
- + 	if (idx < 0)
- + 		idx = cpsw_ale_match_free(ale);
- + 	if (idx < 0)
- + 		idx = cpsw_ale_find_ageable(ale);
- + 	if (idx < 0)
- + 		return -ENOMEM;
- + 
- + 	cpsw_ale_write(ale, idx, ale_entry);
- + 	return 0;
- + }
- + EXPORT_SYMBOL_GPL(cpsw_ale_add_ucast);
- + 
- + int cpsw_ale_add_oui(struct cpsw_ale *ale, u8 *addr)
- + {
- + 	u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
- + 	int idx;
- + 
- + 	cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
- + 	cpsw_ale_set_addr(ale_entry, addr);
- + 	cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_OUI);
- + 
- + 	idx = cpsw_ale_match_addr(ale, addr, 0);
- + 	if (idx < 0)
- + 		idx = cpsw_ale_match_free(ale);
- + 	if (idx < 0)
- + 		idx = cpsw_ale_find_ageable(ale);
- + 	if (idx < 0)
- + 		return -ENOMEM;
- + 
- + 	cpsw_ale_write(ale, idx, ale_entry);
- + 	return 0;
- + }
- + 
- + int cpsw_ale_del_ucast(struct cpsw_ale *ale, u8 *addr, int port)
- + {
- + 	u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
- + 	int idx;
- + 
- + 	idx = cpsw_ale_match_addr(ale, addr, 0);
- + 	if (idx < 0)
- + 		return -ENOENT;
- + 
- + 	cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
- + 	cpsw_ale_write(ale, idx, ale_entry);
- + 	return 0;
- + }
- + EXPORT_SYMBOL_GPL(cpsw_ale_del_ucast);
- + 
- + int cpsw_ale_add_mcast(struct cpsw_ale *ale, u8 *addr, int port_mask,
- + 			int super, int mcast_state)
- + {
- + 	u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
- + 	int idx, mask;
- + 
- + 	idx = cpsw_ale_match_addr(ale, addr, 0);
- + 	if (idx >= 0)
- + 		cpsw_ale_read(ale, idx, ale_entry);
- + 
- + 	cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
- + 	cpsw_ale_set_addr(ale_entry, addr);
- + 	cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2);
- + 	cpsw_ale_set_super(ale_entry, super);
- + 	cpsw_ale_set_mcast_state(ale_entry, mcast_state);
- + 
- + 	mask = cpsw_ale_get_port_mask(ale_entry);
- + 	port_mask |= mask;
- + 	cpsw_ale_set_port_mask(ale_entry, port_mask);
- + 
- + 	if (idx < 0)
- + 		idx = cpsw_ale_match_free(ale);
- + 	if (idx < 0)
- + 		idx = cpsw_ale_find_ageable(ale);
- + 	if (idx < 0)
- + 		return -ENOMEM;
- + 
- + 	cpsw_ale_write(ale, idx, ale_entry);
- + 	return 0;
- + }
- + EXPORT_SYMBOL_GPL(cpsw_ale_add_mcast);
- + 
- + int cpsw_ale_del_mcast(struct cpsw_ale *ale, u8 *addr, int port_mask)
- + {
- + 	u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
- + 	int idx;
- + 
- + 	idx = cpsw_ale_match_addr(ale, addr, 0);
- + 	if (idx < 0)
- + 		return -EINVAL;
- + 
- + 	cpsw_ale_read(ale, idx, ale_entry);
- + 
- + 	if (port_mask)
- + 		cpsw_ale_set_port_mask(ale_entry, port_mask);
- + 	else
- + 		cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
- + 
- + 	cpsw_ale_write(ale, idx, ale_entry);
- + 	return 0;
- + }
- + 
- + int cpsw_ale_add_vlan(struct cpsw_ale *ale, u16 vid, int port, int untag,
- + 		      int reg_mcast, int unreg_mcast)
- + {
- + 	u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
- + 	int idx;
- + 
- + 	idx = cpsw_ale_match_vlan(ale, vid);
- + 	if (idx >= 0)
- + 		cpsw_ale_read(ale, idx, ale_entry);
- + 
- + 	cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_VLAN);
- + 	cpsw_ale_set_vlan_id(ale_entry, vid);
- + 
- + 	cpsw_ale_set_vlan_untag_force(ale_entry, untag);
- + 	cpsw_ale_set_vlan_reg_mcast(ale_entry, reg_mcast);
- + 	cpsw_ale_set_vlan_unreg_mcast(ale_entry, unreg_mcast);
- + 	cpsw_ale_set_vlan_member_list(ale_entry, port);
- + 
- + 	if (idx < 0)
- + 		idx = cpsw_ale_match_free(ale);
- + 	if (idx < 0)
- + 		idx = cpsw_ale_find_ageable(ale);
- + 	if (idx < 0)
- + 		return -ENOMEM;
- + 
- + 	cpsw_ale_write(ale, idx, ale_entry);
- + 	return 0;
- + }
- + 
- + int cpsw_ale_del_vlan(struct cpsw_ale *ale, u16 vid, int port)
- + {
- + 	u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
- + 	int idx, mask;
- + 
- + 	idx = cpsw_ale_match_vlan(ale, vid);
- + 	if (idx < 0)
- + 		return -ENOENT;
- + 
- + 	cpsw_ale_read(ale, idx, ale_entry);
- + 
- + 	mask  = cpsw_ale_get_vlan_member_list(ale_entry);
- + 	mask &= ~port;
- + 	if (!mask)
- + 		cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
- + 	else
- + 		cpsw_ale_set_vlan_member_list(ale_entry, mask);
- + 
- + 	cpsw_ale_write(ale, idx, ale_entry);
- + 	return 0;
- + }
- + 
- + int cpsw_ale_vlan_add_ucast(struct cpsw_ale *ale, u8 *addr, int port,
- + 				int flags, u16 vid)
- + {
- + 	u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
- + 	int idx;
- + 
- + 	cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_VLAN_ADDR);
- + 	cpsw_ale_set_addr(ale_entry, addr);
- + 	cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
- + 	cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
- + 	cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
- + 	cpsw_ale_set_port_num(ale_entry, port);
- + 	cpsw_ale_set_vlan_id(ale_entry, vid);
- + 
- + 	idx = cpsw_ale_match_addr(ale, addr, vid);
- + 	if (idx < 0)
- + 		idx = cpsw_ale_match_free(ale);
- + 	if (idx < 0)
- + 		idx = cpsw_ale_find_ageable(ale);
- + 	if (idx < 0)
- + 		return -ENOMEM;
- + 
- + 	cpsw_ale_write(ale, idx, ale_entry);
- + 	return 0;
- + }
- + 
- + int cpsw_ale_vlan_del_ucast(struct cpsw_ale *ale, u8 *addr, int port, u16 vid)
- + {
- + 	u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
- + 	int idx;
- + 
- + 	idx = cpsw_ale_match_addr(ale, addr, vid);
- + 	if (idx < 0)
- + 		return -ENOENT;
- + 
- + 	cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
- + 	cpsw_ale_write(ale, idx, ale_entry);
- + 	return 0;
- + }
- + 
- + int cpsw_ale_vlan_add_mcast(struct cpsw_ale *ale, u8 *addr,
- + 		int port_mask, u16 vid, int super, int mcast_state)
- + {
- + 	u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
- + 	int idx, mask;
- + 
- + 	idx = cpsw_ale_match_addr(ale, addr, vid);
- + 	if (idx >= 0)
- + 		cpsw_ale_read(ale, idx, ale_entry);
- + 
- + 	cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_VLAN_ADDR);
- + 	cpsw_ale_set_addr(ale_entry, addr);
- + 	cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2);
- + 	cpsw_ale_set_vlan_id(ale_entry, vid);
- + 	cpsw_ale_set_super(ale_entry, super);
- + 	cpsw_ale_set_mcast_state(ale_entry, mcast_state);
- + 
- + 	mask = cpsw_ale_get_port_mask(ale_entry);
- + 	port_mask |= mask;
- + 	cpsw_ale_set_port_mask(ale_entry, port_mask);
- + 
- + 	if (idx < 0)
- + 		idx = cpsw_ale_match_free(ale);
- + 	if (idx < 0)
- + 		idx = cpsw_ale_find_ageable(ale);
- + 	if (idx < 0)
- + 		return -ENOMEM;
- + 
- + 	cpsw_ale_write(ale, idx, ale_entry);
- + 	return 0;
- + }
- + 
- + int cpsw_ale_vlan_del_mcast(struct cpsw_ale *ale, u8 *addr,
- + 				int port_mask, u16 vid)
- + {
- + 	u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
- + 	int idx;
- + 
- + 	idx = cpsw_ale_match_addr(ale, addr, vid);
- + 	if (idx < 0)
- + 		return -EINVAL;
- + 
- + 	cpsw_ale_read(ale, idx, ale_entry);
- + 
- + 	if (port_mask)
- + 		cpsw_ale_set_port_mask(ale_entry, port_mask);
- + 	else
- + 		cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
- + 
- + 	cpsw_ale_write(ale, idx, ale_entry);
- + 	return 0;
- + }
- + EXPORT_SYMBOL_GPL(cpsw_ale_del_mcast);
- + 
- + struct ale_control_info {
- + 	const char	*name;
- + 	int		offset, port_offset;
- + 	int		shift, port_shift;
- + 	int		bits;
- + };
- + 
- + #define CTRL_GLOBAL(name, bit)		{#name, ALE_CONTROL, 0, bit, 0, 1}
- + #define CTRL_UNK(name, shift)		{#name, ALE_UNKNOWNVLAN, 0, shift, 0, 6}
- + #define CTRL_PORTCTL(name, start, bits)	{#name, ALE_PORTCTL, 4, start, 0, bits}
- + 
- + static struct ale_control_info ale_controls[] = {
- + 	[ALE_ENABLE]		= CTRL_GLOBAL(enable, 31),
- + 	[ALE_CLEAR]		= CTRL_GLOBAL(clear, 30),
- + 	[ALE_AGEOUT]		= CTRL_GLOBAL(ageout, 29),
- + 	[ALE_P0_UNI_FLOOD]	= CTRL_GLOBAL(p0_uni_flood, 8),
- + 	[ALE_VLAN_NOLEARN]	= CTRL_GLOBAL(vlan_nolearn, 7),
- + 	[ALE_NO_PORT_VLAN]	= CTRL_GLOBAL(no_port_vlan, 6),
- + 	[ALE_OUI_DENY]		= CTRL_GLOBAL(oui_deny, 5),
- + 	[ALE_BYPASS]		= CTRL_GLOBAL(bypass, 4),
- + 	[ALE_RATE_LIMIT_TX]	= CTRL_GLOBAL(rate_limit_tx, 3),
- + 	[ALE_VLAN_AWARE]	= CTRL_GLOBAL(vlan_aware, 2),
- + 	[ALE_AUTH_ENABLE]	= CTRL_GLOBAL(auth_enable, 1),
- + 	[ALE_RATE_LIMIT]	= CTRL_GLOBAL(rate_limit, 0),
- + 
- + 	[ALE_PORT_STATE]	     = CTRL_PORTCTL(port_state, 0, 2),
- + 	[ALE_PORT_DROP_UNTAGGED]     = CTRL_PORTCTL(drop_untagged, 2, 1),
- + 	[ALE_PORT_DROP_UNKNOWN_VLAN] = CTRL_PORTCTL(drop_unknown, 3, 1),
- + 	[ALE_PORT_NOLEARN]	     = CTRL_PORTCTL(nolearn, 4, 1),
- + 	[ALE_PORT_NO_SA_UPDATE]	     = CTRL_PORTCTL(nolearn, 5, 1),
- + 	[ALE_PORT_MCAST_LIMIT]	     = CTRL_PORTCTL(mcast_limit, 16, 8),
- + 	[ALE_PORT_BCAST_LIMIT]	     = CTRL_PORTCTL(bcast_limit, 24, 8),
- + 
- + 	[ALE_PORT_UNKNOWN_VLAN_MEMBER]	   = CTRL_UNK(unknown_vlan_member, 0),
- + 	[ALE_PORT_UNKNOWN_MCAST_FLOOD]	   = CTRL_UNK(unknown_mcast_flood, 8),
- + 	[ALE_PORT_UNKNOWN_REG_MCAST_FLOOD] = CTRL_UNK(unknown_reg_flood, 16),
- + 	[ALE_PORT_UNTAGGED_EGRESS]	   = CTRL_UNK(untagged_egress, 24),
- + };
- + 
- + int cpsw_ale_control_set(struct cpsw_ale *ale, int port, int control,
- + 			 int value)
- + {
- + 	struct ale_control_info *info = &ale_controls[control];
- + 	int offset, shift;
- + 	u32 tmp, mask;
- + 
- + 	if (control < 0 || control >= ARRAY_SIZE(ale_controls))
- + 		return -EINVAL;
- + 
- + 	if (info->port_offset == 0 && info->port_shift == 0)
- + 		port = 0; /* global, port is a dont care */
- + 
- + 	if (port < 0 || port > ale->ale_ports)
- + 		return -EINVAL;
- + 
- + 	mask = BITMASK(info->bits);
- + 	if (value & ~mask)
- + 		return -EINVAL;
- + 
- + 	offset = info->offset + (port * info->port_offset);
- + 	shift  = info->shift  + (port * info->port_shift);
- + 
- + 	tmp = __raw_readl(ale->ale_regs + offset);
- + 	tmp = (tmp & ~(mask << shift)) | (value << shift);
- + 	__raw_writel(tmp, ale->ale_regs + offset);
- + 
- + 	{
- + 		volatile u32 dly = 10000;
- + 		while (dly--)
- + 			;
- + 	}
- + 	return 0;
- + }
- + EXPORT_SYMBOL_GPL(cpsw_ale_control_set);
- + 
- + int cpsw_ale_control_get(struct cpsw_ale *ale, int port, int control)
- + {
- + 	struct ale_control_info *info = &ale_controls[control];
- + 	int offset, shift;
- + 	u32 tmp;
- + 
- + 	if (control < 0 || control >= ARRAY_SIZE(ale_controls))
- + 		return -EINVAL;
- + 
- + 	if (info->port_offset == 0 && info->port_shift == 0)
- + 		port = 0; /* global, port is a dont care */
- + 
- + 	if (port < 0 || port > ale->ale_ports)
- + 		return -EINVAL;
- + 
- + 	offset = info->offset + (port * info->port_offset);
- + 	shift  = info->shift  + (port * info->port_shift);
- + 
- + 	tmp = __raw_readl(ale->ale_regs + offset) >> shift;
- + 	return tmp & BITMASK(info->bits);
- + }
- + EXPORT_SYMBOL_GPL(cpsw_ale_control_get);
- + 
- + static ssize_t cpsw_ale_control_show(struct device *dev,
- + 				     struct device_attribute *attr,
- + 				     char *buf)
- + {
- + 	int i, port, len = 0;
- + 	struct ale_control_info *info;
- + 	struct cpsw_ale *ale = control_attr_to_ale(attr);
- + 
- + 	for (i = 0, info = ale_controls; i < ALE_NUM_CONTROLS; i++, info++) {
- + 		/* global controls */
- + 		if (info->port_shift == 0 &&  info->port_offset == 0) {
- + 			len += snprintf(buf + len, SZ_4K - len,
- + 					"%s=%d\n", info->name,
- + 					cpsw_ale_control_get(ale, 0, i));
- + 			continue;
- + 		}
- + 		/* port specific controls */
- + 		for (port = 0; port < ale->ale_ports; port++) {
- + 			len += snprintf(buf + len, SZ_4K - len,
- + 					"%s.%d=%d\n", info->name, port,
- + 					cpsw_ale_control_get(ale, port, i));
- + 		}
- + 	}
- + 	return len;
- + }
- + 
- + static ssize_t cpsw_ale_control_store(struct device *dev,
- + 				      struct device_attribute *attr,
- + 				      const char *buf, size_t count)
- + {
- + 	char ctrl_str[33], *end;
- + 	int port = 0, value, len, ret, control;
- + 	struct cpsw_ale *ale = control_attr_to_ale(attr);
- + 
- + 	len = strcspn(buf, ".=");
- + 	if (len >= 32)
- + 		return -ENOMEM;
- + 	strncpy(ctrl_str, buf, len);
- + 	ctrl_str[len] = '\0';
- + 	buf += len;
- + 
- + 	if (*buf == '.') {
- + 		port = simple_strtoul(buf + 1, &end, 0);
- + 		buf = end;
- + 	}
- + 
- + 	if (*buf != '=')
- + 		return -EINVAL;
- + 
- + 	value = simple_strtoul(buf + 1, NULL, 0);
- + 
- + 	for (control = 0; control < ALE_NUM_CONTROLS; control++)
- + 		if (strcmp(ctrl_str, ale_controls[control].name) == 0)
- + 			break;
- + 
- + 	if (control >= ALE_NUM_CONTROLS)
- + 		return -ENOENT;
- + 
- + 	dev_dbg(ale->params.dev, "processing command %s.%d=%d\n",
- + 		ale_controls[control].name, port, value);
- + 
- + 	ret = cpsw_ale_control_set(ale, port, control, value);
- + 	if (ret < 0)
- + 		return ret;
- + 	return count;
- + }
- + 
- + DEVICE_ATTR(ale_control, S_IRUGO | S_IWUSR, cpsw_ale_control_show,
- + 	    cpsw_ale_control_store);
- + 
- + static ssize_t cpsw_ale_table_show(struct device *dev,
- + 				   struct device_attribute *attr,
- + 				   char *buf)
- + {
- + 	int len = SZ_4K, outlen = 0, idx;
- + 	u32 ale_entry[ALE_ENTRY_WORDS];
- + 	struct cpsw_ale *ale = table_attr_to_ale(attr);
- + 
- + 	for (idx = 0; idx < ale->ale_entries; idx++) {
- + 		cpsw_ale_read(ale, idx, ale_entry);
- + 		outlen += cpsw_ale_dump_entry(idx, ale_entry, buf + outlen,
- + 					      len - outlen);
- + 	}
- + 	return outlen;
- + }
- + DEVICE_ATTR(ale_table, S_IRUGO, cpsw_ale_table_show, NULL);
- + 
- + static void cpsw_ale_timer(unsigned long arg)
- + {
- + 	struct cpsw_ale *ale = (struct cpsw_ale *)arg;
- + 
- + 	cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
- + 
- + 	if (ale->ageout) {
- + 		ale->timer.expires = jiffies + ale->ageout;
- + 		add_timer(&ale->timer);
- + 	}
- + }
- + 
- + int cpsw_ale_set_ageout(struct cpsw_ale *ale, int ageout)
- + {
- + 	del_timer_sync(&ale->timer);
- + 	ale->ageout = ageout * HZ;
- + 	if (ale->ageout) {
- + 		ale->timer.expires = jiffies + ale->ageout;
- + 		add_timer(&ale->timer);
- + 	}
- + 	return 0;
- + }
- + 
- + void cpsw_ale_start(struct cpsw_ale *ale)
- + {
- + 	u32 rev;
- + 	int ret;
- + 
- + 	rev = __raw_readl(ale->ale_regs + ALE_IDVER);
- + 	dev_dbg(ale->params.dev, "initialized cpsw ale revision %d.%d\n",
- + 		(rev >> 8) & 0xff, rev & 0xff);
- + 	cpsw_ale_control_set(ale, 0, ALE_ENABLE, 1);
- + 	cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1);
- + 
- + 	ale->ale_control_attr = dev_attr_ale_control;
- + 	sysfs_attr_init(&ale->ale_control_attr.attr);
- + 	ret = device_create_file(ale->params.dev, &ale->ale_control_attr);
- + 	WARN_ON(ret < 0);
- + 
- + 	ale->ale_table_attr = dev_attr_ale_table;
- + 	sysfs_attr_init(&ale->ale_table_attr.attr);
- + 	ret = device_create_file(ale->params.dev, &ale->ale_table_attr);
- + 	WARN_ON(ret < 0);
- + 
- + 	init_timer(&ale->timer);
- + 	ale->timer.data	    = (unsigned long)ale;
- + 	ale->timer.function = cpsw_ale_timer;
- + 	if (ale->ageout) {
- + 		ale->timer.expires = jiffies + ale->ageout;
- + 		add_timer(&ale->timer);
- + 	}
- + }
- + EXPORT_SYMBOL_GPL(cpsw_ale_start);
- + 
- + void cpsw_ale_stop(struct cpsw_ale *ale)
- + {
- + 	cpsw_ale_control_set(ale, 0, ALE_ENABLE, 0);
- + 	del_timer_sync(&ale->timer);
- + 	device_remove_file(ale->params.dev, &ale->ale_table_attr);
- + 	device_remove_file(ale->params.dev, &ale->ale_control_attr);
- + }
- + EXPORT_SYMBOL_GPL(cpsw_ale_stop);
- + 
- + struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params)
- + {
- + 	struct cpsw_ale *ale;
- + 	int ret;
- + 
- + 	ret = -ENOMEM;
- + 	ale = kzalloc(sizeof(*ale), GFP_KERNEL);
- + 	if (WARN_ON(!ale))
- + 		return NULL;
- + 
- + 	ale->params = *params;
- + 	ale->ageout = ale->params.ale_ageout * HZ;
- + 
- + 	return ale;
- + }
- + EXPORT_SYMBOL_GPL(cpsw_ale_create);
- + 
- + int cpsw_ale_destroy(struct cpsw_ale *ale)
- + {
- + 	if (!ale)
- + 		return -EINVAL;
- + 	cpsw_ale_stop(ale);
- + 	cpsw_ale_control_set(ale, 0, ALE_ENABLE, 0);
- + 	kfree(ale);
- + 	return 0;
- + }
- + EXPORT_SYMBOL_GPL(cpsw_ale_destroy);
- + 
- + MODULE_DESCRIPTION("Ethernet Switch Address Lookup Engine driver");
- + MODULE_AUTHOR("Chandan Nath <chandan.nath@ti.com>");
- + MODULE_LICENSE("GPL");
- diff -crN linux-3.2.1_o/drivers/net/ethernet/ti/cpsw_ale.h linux-3.2.1/drivers/net/ethernet/ti/cpsw_ale.h
- *** linux-3.2.1_o/drivers/net/ethernet/ti/cpsw_ale.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/drivers/net/ethernet/ti/cpsw_ale.h	2014-05-15 13:25:14.586776106 +0900
- ***************
- *** 0 ****
- --- 1,114 ----
- + /*
- +  * Texas Instruments 3-Port Ethernet Switch Address Lookup Engine APIs
- +  *
- +  * Copyright (C) 2010 Texas Instruments
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + #ifndef __TI_CPSW_ALE_H__
- + #define __TI_CPSW_ALE_H__
- + 
- + struct cpsw_ale_params {
- + 	struct device		*dev;
- + 	void __iomem		*ale_regs;
- + 	unsigned long		ale_ageout;	/* in secs */
- + 	unsigned long		ale_entries;
- + 	unsigned long		ale_ports;
- + };
- + 
- + struct cpsw_ale {
- + 	struct cpsw_ale_params	params;
- + 	struct timer_list	timer;
- + 	unsigned long		ageout;
- + 	struct device_attribute ale_control_attr;
- + #define control_attr_to_ale(attr)	\
- + 	container_of(attr, struct cpsw_ale, ale_control_attr);
- + 	struct device_attribute ale_table_attr;
- + #define table_attr_to_ale(attr)		\
- + 	container_of(attr, struct cpsw_ale, ale_table_attr);
- + };
- + 
- + enum cpsw_ale_control {
- + 	/* global */
- + 	ALE_ENABLE,
- + 	ALE_CLEAR,
- + 	ALE_AGEOUT,
- + 	ALE_P0_UNI_FLOOD,
- + 	ALE_VLAN_NOLEARN,
- + 	ALE_NO_PORT_VLAN,
- + 	ALE_OUI_DENY,
- + 	ALE_BYPASS,
- + 	ALE_RATE_LIMIT_TX,
- + 	ALE_VLAN_AWARE,
- + 	ALE_AUTH_ENABLE,
- + 	ALE_RATE_LIMIT,
- + 	/* port controls */
- + 	ALE_PORT_STATE,
- + 	ALE_PORT_DROP_UNTAGGED,
- + 	ALE_PORT_DROP_UNKNOWN_VLAN,
- + 	ALE_PORT_NOLEARN,
- + 	ALE_PORT_NO_SA_UPDATE,
- + 	ALE_PORT_UNKNOWN_VLAN_MEMBER,
- + 	ALE_PORT_UNKNOWN_MCAST_FLOOD,
- + 	ALE_PORT_UNKNOWN_REG_MCAST_FLOOD,
- + 	ALE_PORT_UNTAGGED_EGRESS,
- + 	ALE_PORT_BCAST_LIMIT,
- + 	ALE_PORT_MCAST_LIMIT,
- + 	ALE_NUM_CONTROLS,
- + };
- + 
- + enum cpsw_ale_port_state {
- + 	ALE_PORT_STATE_DISABLE	= 0x00,
- + 	ALE_PORT_STATE_BLOCK	= 0x01,
- + 	ALE_PORT_STATE_LEARN	= 0x02,
- + 	ALE_PORT_STATE_FORWARD	= 0x03,
- + };
- + 
- + /* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */
- + #define ALE_SECURE	1
- + #define ALE_BLOCKED	2
- + 
- + struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params);
- + int cpsw_ale_destroy(struct cpsw_ale *ale);
- + 
- + void cpsw_ale_start(struct cpsw_ale *ale);
- + void cpsw_ale_stop(struct cpsw_ale *ale);
- + 
- + int cpsw_ale_set_ageout(struct cpsw_ale *ale, int ageout);
- + int cpsw_ale_flush(struct cpsw_ale *ale, int port_mask);
- + int cpsw_ale_add_ucast(struct cpsw_ale *ale, u8 *addr, int port, int flags);
- + int cpsw_ale_del_ucast(struct cpsw_ale *ale, u8 *addr, int port);
- + int cpsw_ale_add_mcast(struct cpsw_ale *ale, u8 *addr, int port_mask,
- + 			int super, int mcast_state);
- + int cpsw_ale_del_mcast(struct cpsw_ale *ale, u8 *addr, int port_mask);
- + int cpsw_ale_add_vlan(struct cpsw_ale *ale, u16 vid, int port, int untag,
- + 			int reg_mcast, int unreg_mcast);
- + int cpsw_ale_del_vlan(struct cpsw_ale *ale, u16 vid, int port);
- + int cpsw_ale_vlan_add_ucast(struct cpsw_ale *ale, u8 *addr, int port,
- + 			int flags, u16 vid);
- + int cpsw_ale_vlan_del_ucast(struct cpsw_ale *ale, u8 *addr, int port,
- + 			u16 vid);
- + int cpsw_ale_vlan_add_mcast(struct cpsw_ale *ale, u8 *addr, int port_mask,
- + 			u16 vid, int super, int mcast_state);
- + int cpsw_ale_vlan_del_mcast(struct cpsw_ale *ale, u8 *addr, int port_mask,
- + 			u16 vid);
- + 
- + int cpsw_ale_control_get(struct cpsw_ale *ale, int port, int control);
- + int cpsw_ale_control_set(struct cpsw_ale *ale, int port,
- + 			 int control, int value);
- + int cpsw_ale_flush_multicast(struct cpsw_ale *ale, int port_mask);
- + void cpsw_ale_flush_vlan_multicast(struct cpsw_ale *ale, u16 vid,
- + 				   int port_mask);
- + int cpsw_ale_dump(struct cpsw_ale *ale, int index, char *buf, int len);
- + int cpsw_ale_match_addr(struct cpsw_ale *ale, u8* addr, u16 vid);
- + int cpsw_ale_match_vlan(struct cpsw_ale *ale, u16 vid);
- + int cpsw_ale_add_oui(struct cpsw_ale *ale, u8 *addr);
- + 
- + #endif
- diff -crN linux-3.2.1_o/drivers/net/ethernet/ti/cpsw.c linux-3.2.1/drivers/net/ethernet/ti/cpsw.c
- *** linux-3.2.1_o/drivers/net/ethernet/ti/cpsw.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/drivers/net/ethernet/ti/cpsw.c	2014-05-15 13:25:14.591233781 +0900
- ***************
- *** 0 ****
- --- 1,2969 ----
- + /*
- +  * Texas Instruments Ethernet Switch Driver
- +  *
- +  * Copyright (C) 2010 Texas Instruments
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + #include <linux/kernel.h>
- + #include <linux/io.h>
- + #include <linux/clk.h>
- + #include <linux/timer.h>
- + #include <linux/module.h>
- + #include <linux/platform_device.h>
- + #include <linux/if_ether.h>
- + #include <linux/etherdevice.h>
- + #include <linux/ethtool.h>
- + #include <linux/netdevice.h>
- + #include <linux/net_tstamp.h>
- + #include <linux/phy.h>
- + #include <linux/workqueue.h>
- + #include <linux/delay.h>
- + #include <linux/interrupt.h>
- + #include <linux/pm_runtime.h>
- + #include <linux/if_vlan.h>
- + #include <linux/net_switch_config.h>
- + 
- + #include <linux/cpsw.h>
- + #include <plat/dmtimer.h>
- + #include "cpsw_ale.h"
- + #include "cpts.h"
- + #include "davinci_cpdma.h"
- + 
- + 
- + #define CPSW_DEBUG	(NETIF_MSG_HW		| NETIF_MSG_WOL		| \
- + 			 NETIF_MSG_DRV		| NETIF_MSG_LINK	| \
- + 			 NETIF_MSG_IFUP		| NETIF_MSG_INTR	| \
- + 			 NETIF_MSG_PROBE	| NETIF_MSG_TIMER	| \
- + 			 NETIF_MSG_IFDOWN	| NETIF_MSG_RX_ERR	| \
- + 			 NETIF_MSG_TX_ERR	| NETIF_MSG_TX_DONE	| \
- + 			 NETIF_MSG_PKTDATA	| NETIF_MSG_TX_QUEUED	| \
- + 			 NETIF_MSG_RX_STATUS)
- + 
- + #define msg(level, type, format, ...)				\
- + do {								\
- + 	if (netif_msg_##type(priv) && net_ratelimit())		\
- + 		dev_##level(priv->dev, format, ## __VA_ARGS__);	\
- + } while (0)
- + 
- + #define CPSW_VERSION1		0x19010a
- + #define CPSW_VERSION2		0x19010c
- + #define CPDMA_RXTHRESH		0x0c0
- + #define CPDMA_RXFREE		0x0e0
- + #define CPDMA_TXHDP_VER1	0x100
- + #define CPDMA_TXHDP_VER2	0x200
- + #define CPDMA_RXHDP_VER1	0x120
- + #define CPDMA_RXHDP_VER2	0x220
- + #define CPDMA_TXCP_VER1		0x140
- + #define CPDMA_TXCP_VER2		0x240
- + #define CPDMA_RXCP_VER1		0x160
- + #define CPDMA_RXCP_VER2		0x260
- + 
- + #define CPSW_POLL_WEIGHT	64
- + #define CPSW_MIN_PACKET_SIZE	60
- + #define CPSW_MAX_PACKET_SIZE	(1500 + 14 + 4 + 4)
- + #define CPSW_PHY_SPEED		1000
- + 
- + #define CPSW_PRIMAP(shift, priority)	(priority << (shift * 4))
- + 
- + #define slave(priv, idx)	((priv)->slaves + idx)
- + #define switchcmd(__cmd__)	((__cmd__)->cmd_data.switchcmd)
- + #define portcmd(__cmd__)	((__cmd__)->cmd_data.portcmd)
- + #define priocmd(__cmd__)	((__cmd__)->cmd_data.priocmd)
- + 
- + /* CPSW control module masks */
- + #define CPSW_INTPACEEN		(0x3 << 16)
- + #define CPSW_INTPRESCALE_MASK	(0x7FF << 0)
- + #define CPSW_CMINTMAX_CNT	63
- + #define CPSW_CMINTMIN_CNT	2
- + #define CPSW_CMINTMAX_INTVL	(1000 / CPSW_CMINTMIN_CNT)
- + #define CPSW_CMINTMIN_INTVL	((1000 / CPSW_CMINTMAX_CNT) + 1)
- + 
- + #define cpsw_enable_irq(priv)	\
- + 	do {			\
- + 		u32 i;		\
- + 		for (i = 0; i < priv->num_irqs; i++) \
- + 			enable_irq(priv->irqs_table[i]); \
- + 	} while (0);
- + #define cpsw_disable_irq(priv)	\
- + 	do {			\
- + 		u32 i;		\
- + 		for (i = 0; i < priv->num_irqs; i++) \
- + 			disable_irq_nosync(priv->irqs_table[i]); \
- + 	} while (0);
- + 
- + #define ALE_ALL_PORTS		0x7
- + 
- + #define CPSW_CPDMA_EOI_REG	0x894
- + #define CPSW_TIMER_MASK		0xA0908
- + #define CPSW_TIMER_CAP_REG	0xFD0
- + #define CPSW_RX_TIMER_REQ	5
- + #define CPSW_TX_TIMER_REQ	6
- + 
- + /* CPSW_PORT_V1 */
- + #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
- + #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
- + #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
- + #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
- + #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
- + #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
- + #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
- + #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
- + 
- + /* CPSW_PORT_V2 */
- + #define CPSW2_CONTROL       0x00 /* Control Register */
- + #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
- + #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
- + #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
- + #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
- + #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
- + #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
- + 
- + /* CPSW_PORT_V1 and V2 */
- + #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
- + #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
- + #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
- + 
- + /* CPSW_PORT_V2 only */
- + #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
- + #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
- + #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
- + #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
- + #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
- + #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
- + #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
- + #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
- + 
- + /* Bit definitions for the CPSW2_CONTROL register */
- + #define PASS_PRI_TAGGED     (1<<24) /* Pass Priority Tagged */
- + #define VLAN_LTYPE2_EN      (1<<21) /* VLAN LTYPE 2 enable */
- + #define VLAN_LTYPE1_EN      (1<<20) /* VLAN LTYPE 1 enable */
- + #define DSCP_PRI_EN         (1<<16) /* DSCP Priority Enable */
- + #define TS_320              (1<<14) /* Time Sync Dest Port 320 enable */
- + #define TS_319              (1<<13) /* Time Sync Dest Port 319 enable */
- + #define TS_132              (1<<12) /* Time Sync Dest IP Addr 132 enable */
- + #define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
- + #define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
- + #define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
- + #define TS_BIT8             (1<<8)  /* ts_ttl_nonzero? */
- + #define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
- + #define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
- + #define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
- + #define TS_TX_EN            (1<<1)  /* Time Sync Transmit Enable */
- + #define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
- + 
- + #define CTRL_TS_BITS \
- + 	(TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \
- + 	 TS_ANNEX_D_EN | TS_LTYPE1_EN)
- + 
- + #define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN)
- + #define CTRL_TX_TS_BITS  (CTRL_TS_BITS | TS_TX_EN)
- + #define CTRL_RX_TS_BITS  (CTRL_TS_BITS | TS_RX_EN)
- + 
- + /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
- + #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
- + #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
- + #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
- + #define TS_MSG_TYPE_EN_MASK      (0xffff)
- + 
- + /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
- + #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
- + 
- + /* Bit definitions for the CPSW1_TS_CTL register */
- + #define CPSW_V1_TS_RX_EN		BIT(0)
- + #define CPSW_V1_TS_TX_EN		BIT(4)
- + #define CPSW_V1_MSG_TYPE_OFS		16
- + 
- + /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
- + #define CPSW_V1_SEQ_ID_OFS_SHIFT	16
- + 
- + #ifdef CONFIG_TI_CPSW_DUAL_EMAC
- + 
- + /* Enable VLAN aware mode to add VLAN for induvudual interface */
- + #define CPSW_VLAN_AWARE_MODE
- + 
- + #define cpsw_get_slave_ndev(priv, __slave_no__)		\
- + 	(priv->slaves[__slave_no__].ndev)
- + #define cpsw_get_slave_priv(priv, __slave_no__)		\
- + 	netdev_priv(priv->slaves[__slave_no__].ndev)
- + #define for_each_slave(priv, func, arg...)			\
- + 	do {							\
- + 		(func)((priv)->slaves + priv->emac_port, ##arg);\
- + 	} while (0)
- + #define cpsw_dual_emac_source_port_detect(status, priv, ndev, skb)	\
- + 	do {								\
- + 		if (CPDMA_RX_SOURCE_PORT(status) == 1) {		\
- + 			ndev = cpsw_get_slave_ndev(priv, 0);		\
- + 			priv = netdev_priv(ndev);			\
- + 			skb->dev = ndev;				\
- + 		} else if (CPDMA_RX_SOURCE_PORT(status) == 2) {		\
- + 			ndev = cpsw_get_slave_ndev(priv, 1);		\
- + 			priv = netdev_priv(ndev);			\
- + 			skb->dev = ndev;				\
- + 		}							\
- + 	} while (0)
- + #define cpsw_add_switch_mode_bcast_ale_entries(priv, slave_port)
- + #define cpsw_update_slave_open_state(priv, state)		\
- + 	priv->slaves[priv->emac_port].open_stat = state;
- + #define cpsw_slave_phy_index(priv)	((priv)->emac_port)
- + 
- + #else	/* CONFIG_TI_CPSW_DUAL_EMAC */
- + 
- + #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
- + #define VLAN_SUPPORT
- + #define CPSW_VLAN_AWARE_MODE
- + #endif
- + 
- + #define cpsw_get_slave_ndev(priv, __slave_no__)		NULL
- + #define cpsw_get_slave_priv(priv, __slave_no__)		NULL
- + #define for_each_slave(priv, func, arg...)			\
- + 	do {							\
- + 		int idx;					\
- + 		for (idx = 0; idx < (priv)->data.slaves; idx++)	\
- + 			(func)((priv)->slaves + idx, ##arg);	\
- + 	} while (0)
- + #define cpsw_dual_emac_source_port_detect(status, priv, ndev, skb)
- + #define cpsw_add_switch_mode_bcast_ale_entries(priv, slave_port)	\
- + 	cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,		\
- + 			   1 << slave_port, 0, 0)
- + #define cpsw_update_slave_open_state(priv, state)
- + #define cpsw_slave_phy_index(priv)	((priv)->data.ethtool_slave)
- + 
- + #endif	/* CONFIG_TI_CPSW_DUAL_EMAC */
- + 
- + #ifdef CPSW_VLAN_AWARE_MODE
- + #define CPSW_VLAN_AWARE		BIT(1)
- + #define CPSW_ALE_VLAN_AWARE	1
- + #else
- + #define CPSW_VLAN_AWARE		0x0
- + #define CPSW_ALE_VLAN_AWARE	0
- + #endif
- + 
- + struct omap_dm_timer *dmtimer_rx;
- + struct omap_dm_timer *dmtimer_tx;
- + 
- + extern u32 omap_ctrl_readl(u16 offset);
- + extern void omap_ctrl_writel(u32 val, u16 offset);
- + 
- + static int debug_level;
- + module_param(debug_level, int, 0);
- + MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
- + 
- + static int ale_ageout = 10;
- + module_param(ale_ageout, int, 0);
- + MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
- + 
- + static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
- + module_param(rx_packet_max, int, 0);
- + MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
- + 
- + struct cpsw_wr_regs {
- + 	u32	id_ver;
- + 	u32	soft_reset;
- + 	u32	control;
- + 	u32	int_control;
- + 	u32	rx_thresh_en;
- + 	u32	rx_en;
- + 	u32	tx_en;
- + 	u32	misc_en;
- + 	u32	mem_allign1[8];
- + 	u32	rx_thresh_stat;
- + 	u32	rx_stat;
- + 	u32	tx_stat;
- + 	u32	misc_stat;
- + 	u32	mem_allign2[8];
- + 	u32	rx_imax;
- + 	u32	tx_imax;
- + };
- + 
- + struct cpsw_ss_regs {
- + 	u32	id_ver;
- + 	u32	control;
- + 	u32	soft_reset;
- + 	u32	stat_port_en;
- + 	u32	ptype;
- + 	u32	soft_idle;
- + 	u32	thru_rate;
- + 	u32	gap_thresh;
- + 	u32	tx_start_wds;
- + 	u32	flow_control;
- + 	u32	vlan_ltype;
- + 	u32	ts_ltype;
- + 	u32	dlr_ltype;
- + };
- + 
- + struct cpsw_host_regs {
- + 	u32	max_blks;
- + 	u32	blk_cnt;
- + 	u32	flow_thresh;
- + 	u32	port_vlan;
- + 	u32	tx_pri_map;
- + 	u32	cpdma_tx_pri_map;
- + 	u32	cpdma_rx_chan_map;
- + };
- + 
- + struct cpsw_sliver_regs {
- + 	u32	id_ver;
- + 	u32	mac_control;
- + 	u32	mac_status;
- + 	u32	soft_reset;
- + 	u32	rx_maxlen;
- + 	u32	__reserved_0;
- + 	u32	rx_pause;
- + 	u32	tx_pause;
- + 	u32	__reserved_1;
- + 	u32	rx_pri_map;
- + };
- + 
- + struct cpsw_hw_stats {
- + 	u32	rxgoodframes;
- + 	u32	rxbroadcastframes;
- + 	u32	rxmulticastframes;
- + 	u32	rxpauseframes;
- + 	u32	rxcrcerrors;
- + 	u32	rxaligncodeerrors;
- + 	u32	rxoversizedframes;
- + 	u32	rxjabberframes;
- + 	u32	rxundersizedframes;
- + 	u32	rxfragments;
- + 	u32	__pad_0[2];
- + 	u32	rxoctets;
- + 	u32	txgoodframes;
- + 	u32	txbroadcastframes;
- + 	u32	txmulticastframes;
- + 	u32	txpauseframes;
- + 	u32	txdeferredframes;
- + 	u32	txcollisionframes;
- + 	u32	txsinglecollframes;
- + 	u32	txmultcollframes;
- + 	u32	txexcessivecollisions;
- + 	u32	txlatecollisions;
- + 	u32	txunderrun;
- + 	u32	txcarriersenseerrors;
- + 	u32	txoctets;
- + 	u32	octetframes64;
- + 	u32	octetframes65t127;
- + 	u32	octetframes128t255;
- + 	u32	octetframes256t511;
- + 	u32	octetframes512t1023;
- + 	u32	octetframes1024tup;
- + 	u32	netoctets;
- + 	u32	rxsofoverruns;
- + 	u32	rxmofoverruns;
- + 	u32	rxdmaoverruns;
- + };
- + 
- + struct cpsw_slave {
- + 	void __iomem			*regs;
- + 	struct cpsw_sliver_regs __iomem	*sliver;
- + 	int				slave_num;
- + 	u32				mac_control;
- + 	struct cpsw_slave_data		*data;
- + 	struct phy_device		*phy;
- + 	u32				port_vlan;
- + 	struct net_device		*ndev;
- + 	u32				open_stat;
- + };
- + 
- + struct cpsw_priv {
- + 	spinlock_t			lock;
- + 	struct platform_device		*pdev;
- + 	struct net_device		*ndev;
- + 	struct resource			*cpsw_res;
- + 	struct resource			*cpsw_ss_res;
- + 	struct napi_struct		napi;
- + #define napi_to_priv(napi)	container_of(napi, struct cpsw_priv, napi)
- + 	struct device			*dev;
- + 	struct cpsw_platform_data	data;
- + 	struct cpsw_ss_regs __iomem	*regs;
- + 	struct cpsw_wr_regs __iomem	*wr_regs;
- + 	struct cpsw_hw_stats __iomem	*hw_stats;
- + 	struct cpsw_host_regs __iomem	*host_port_regs;
- + 	u32				msg_enable;
- + 	u32				version;
- + 	u32				coal_intvl;
- + 	u32				bus_freq_mhz;
- + 	struct net_device_stats		stats;
- + 	int				rx_packet_max;
- + 	int				host_port;
- + 	struct clk			*clk;
- + 	u8				mac_addr[ETH_ALEN];
- + 	struct cpsw_slave		*slaves;
- + 	struct cpdma_ctlr		*dma;
- + 	struct cpdma_chan		*txch, *rxch;
- + 	struct cpsw_ale			*ale;
- + 	u32				emac_port;
- + 	u8				port_state[3];
- + 	/* snapshot of IRQ numbers */
- + 	u32 irqs_table[4];
- + 	u32 num_irqs;
- + 	struct cpts *cpts;
- + 	void (*save_mac_addr) (char *);		/* function for saving MAC address */
- + };
- + 
- + static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
- + {
- + 	return readl(slave->regs + offset);
- + }
- + 
- + static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
- + {
- + 	writel(val, slave->regs + offset);
- + }
- + 
- + #ifdef CONFIG_TI_CPTS
- + 
- + static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
- + {
- + 	struct cpsw_slave *slave = &priv->slaves[priv->data.cpts_active_slave];
- + 	u32 ts_en, seq_id;
- + 
- + 	if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
- + 		slave_write(slave, 0, CPSW1_TS_CTL);
- + 		return;
- + 	}
- + 
- + 	seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
- + 	ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
- + 
- + 	if (priv->cpts->tx_enable)
- + 		ts_en |= CPSW_V1_TS_TX_EN;
- + 
- + 	if (priv->cpts->rx_enable)
- + 		ts_en |= CPSW_V1_TS_RX_EN;
- + 
- + 	slave_write(slave, ts_en, CPSW1_TS_CTL);
- + 	slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
- + }
- + 
- + static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
- + {
- + 	struct cpsw_slave *slave = &priv->slaves[priv->data.cpts_active_slave];
- + 	u32 ctrl, mtype;
- + 
- + 	ctrl = slave_read(slave, CPSW2_CONTROL);
- + 	ctrl &= ~CTRL_ALL_TS_MASK;
- + 
- + 	if (priv->cpts->tx_enable)
- + 		ctrl |= CTRL_TX_TS_BITS;
- + 
- + 	if (priv->cpts->rx_enable)
- + 		ctrl |= CTRL_RX_TS_BITS;
- + 
- + 	mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
- + 
- + 	slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
- + 	slave_write(slave, ctrl, CPSW2_CONTROL);
- + 	__raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
- + }
- + 
- + #ifdef CONFIG_TI_CPSW_DUAL_EMAC
- + static int cpsw_select_ts_slave_port(struct cpsw_priv *priv)
- + {
- + 	if (priv->cpts->tx_enable)
- + 		return -ENOTSUPP;
- + 	priv->data.cpts_active_slave = priv->emac_port;
- + 	return 0;
- + }
- + #else
- + static int cpsw_select_ts_slave_port(struct cpsw_priv *priv)
- + {
- + 	return 0;
- + }
- + #endif
- + 
- + static int cpsw_hwtstamp_ioctl(struct net_device *ndev, struct ifreq *ifr)
- + {
- + 	struct cpsw_priv *priv = netdev_priv(ndev);
- + 	struct cpts *cpts = priv->cpts;
- + 	struct hwtstamp_config cfg;
- + 
- + 	if (cpsw_select_ts_slave_port(priv))
- + 		return -ENOTSUPP;
- + 
- + 	if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
- + 		return -EFAULT;
- + 
- + 	/* reserved for future extensions */
- + 	if (cfg.flags)
- + 		return -EINVAL;
- + 
- + 	switch (cfg.tx_type) {
- + 	case HWTSTAMP_TX_OFF:
- + 		cpts->tx_enable = 0;
- + 		break;
- + 	case HWTSTAMP_TX_ON:
- + 		cpts->tx_enable = 1;
- + 		break;
- + 	default:
- + 		return -ERANGE;
- + 	}
- + 
- + 	switch (cfg.rx_filter) {
- + 	case HWTSTAMP_FILTER_NONE:
- + 		cpts->rx_enable = 0;
- + 		break;
- + 	case HWTSTAMP_FILTER_ALL:
- + 	case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
- + 	case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
- + 	case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
- + 		return -ERANGE;
- + 	case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
- + 	case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
- + 	case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
- + 	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
- + 	case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
- + 	case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
- + 	case HWTSTAMP_FILTER_PTP_V2_EVENT:
- + 	case HWTSTAMP_FILTER_PTP_V2_SYNC:
- + 	case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
- + 		cpts->rx_enable = 1;
- + 		cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
- + 		break;
- + 	default:
- + 		return -ERANGE;
- + 	}
- + 
- + 	switch (priv->version) {
- + 	case CPSW_VERSION1:
- + 		cpsw_hwtstamp_v1(priv);
- + 		break;
- + 	case CPSW_VERSION2:
- + 		cpsw_hwtstamp_v2(priv);
- + 		break;
- + 	default:
- + 		return -ENOTSUPP;
- + 	}
- + 
- + 	return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
- + }
- + 
- + #endif
- + 
- + #ifdef CONFIG_TI_CPSW_DUAL_EMAC
- + 
- + static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
- + {
- + 	struct cpsw_priv *priv = netdev_priv(ndev);
- + 	struct cpsw_slave *slave = priv->slaves + priv->emac_port;
- + 
- + 	/* Clear all mcast from ALE */
- + 	cpsw_ale_flush_vlan_multicast(priv->ale, slave->port_vlan,
- + 			1 << (priv->emac_port + 1) | 1 << priv->host_port);
- + 
- + 	if (!netdev_mc_empty(ndev)) {
- + 		struct netdev_hw_addr *ha;
- + 
- + 		/* program multicast address list into ALE register */
- + 		netdev_for_each_mc_addr(ha, ndev) {
- + 			cpsw_ale_vlan_add_mcast(priv->ale, (u8 *)ha->addr,
- + 					1 << (priv->emac_port + 1) |
- + 					1 << priv->host_port,
- + 					slave->port_vlan, 0, 0);
- + 		}
- + 	}
- + }
- + 
- + static void cpsw_ndo_change_rx_flags(struct net_device *ndev, int flags)
- + {
- + 	struct cpsw_priv *priv = netdev_priv(ndev);
- + 	struct cpsw_ale *ale = priv->ale;
- + 
- + 	if (flags & IFF_PROMISC) {
- + 		if ((priv->slaves[0].ndev->flags & IFF_PROMISC) ||
- + 				(priv->slaves[1].ndev->flags & IFF_PROMISC)) {
- + 			/*
- + 			 * Enabling promiscuous mode for one interface will be
- + 			 * common for both the interface as the interface
- + 			 * shares the same hardware resource.
- + 			 */
- + 
- + 			/* Enable Bypass */
- + 			cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
- + 
- + 			dev_err(&ndev->dev, "promiscuity enabled\n");
- + 		} else {
- + 			/* Disable Bypass */
- + 			cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
- + 			dev_err(&ndev->dev, "promiscuity disabled\n");
- + 		}
- + 	}
- + 
- + 	/*
- + 	 * The switch cannot filter multicast traffic unless it is configured
- + 	 * in "VLAN Aware" mode.  Unfortunately, VLAN awareness requires a
- + 	 * whole bunch of additional logic that this driver does not implement
- + 	 * at present.
- + 	 */
- + 	if ((flags & IFF_ALLMULTI) && !(ndev->flags & IFF_ALLMULTI))
- + 		dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n");
- + }
- + 
- + static inline void cpsw_p0_fifo_type_select(struct cpsw_priv *priv)
- + {
- + 	u32 reg;
- + 	reg = readl(&priv->host_port_regs->flow_thresh);
- + 	reg &= ~(0x3 << 16);
- + 	reg |= 0x1 << 16;
- + 	writel(reg, &priv->host_port_regs->flow_thresh);
- + }
- + 
- + static inline void cpsw_add_dual_emac_mode_default_ale_entries(
- + 		struct cpsw_priv *priv, struct cpsw_slave *slave,
- + 		u32 slave_port)
- + {
- + 	if (priv->version == CPSW_VERSION1)
- + 		slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
- + 	else
- + 		slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
- + 	cpsw_ale_add_vlan(priv->ale, slave->port_vlan,
- + 		1 << slave_port | 1 << priv->host_port, 0,
- + 		1 << slave_port | 1 << priv->host_port,
- + 		1 << slave_port | 1 << priv->host_port);
- + 	cpsw_ale_vlan_add_mcast(priv->ale,
- + 		priv->ndev->broadcast,
- + 		1 << slave_port | 1 << priv->host_port,
- + 		slave->port_vlan, 0, 0);
- + 	cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
- + 		priv->host_port, 0);
- + 	cpsw_ale_add_vlan(priv->ale, 0,
- + 		ALE_ALL_PORTS << priv->host_port,
- + 		ALE_ALL_PORTS << priv->host_port, priv->host_port, 0);
- + }
- + 
- + static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
- + {
- + 	u32 i;
- + 	u32 usage_count = 0;
- + 
- + 	for (i = 0; i < priv->data.slaves; i++)
- + 		if (priv->slaves[i].open_stat)
- + 			usage_count++;
- + 
- + 	return usage_count;
- + }
- + 
- + static inline int cpsw_tx_packet_submit(struct net_device *ndev,
- + 			struct cpsw_priv *priv, struct sk_buff *skb)
- + {
- + 	if (ndev == cpsw_get_slave_ndev(priv, 0))
- + 		return cpdma_chan_submit(priv->txch, skb, skb->data,
- + 				  skb->len, 1, GFP_KERNEL);
- + 	else
- + 		return cpdma_chan_submit(priv->txch, skb, skb->data,
- + 				  skb->len, 2, GFP_KERNEL);
- + }
- + 
- + #define cpsw_add_switch_mode_default_ale_entries(priv)
- + 
- + #else	/* CONFIG_TI_CPSW_DUAL_EMAC */
- + 
- + static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
- + {
- + 	struct cpsw_priv *priv = netdev_priv(ndev);
- + 
- + 	/* Clear all mcast from ALE */
- + 	cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port);
- + 
- + 	if (!netdev_mc_empty(ndev)) {
- + 		struct netdev_hw_addr *ha;
- + 
- + 		/* program multicast address list into ALE register */
- + 		netdev_for_each_mc_addr(ha, ndev) {
- + 			cpsw_ale_add_mcast(priv->ale, (u8 *)ha->addr,
- + 				ALE_ALL_PORTS << priv->host_port, 0, 0);
- + 		}
- + 	}
- + }
- + 
- + static void cpsw_ndo_change_rx_flags(struct net_device *ndev, int flags)
- + {
- + 	struct cpsw_priv *priv = netdev_priv(ndev);
- + 	struct cpsw_ale *ale = priv->ale;
- + 	int i;
- + 
- + 	if (flags & IFF_PROMISC) {
- + 		if (ndev->flags & IFF_PROMISC) {
- + 			unsigned long timeout = jiffies + HZ;
- + 
- + 			/* Disable Learn for all ports */
- + 			for (i = 0; i <= priv->data.slaves; i++) {
- + 				cpsw_ale_control_set(ale, i,
- + 						     ALE_PORT_NOLEARN, 1);
- + 				cpsw_ale_control_set(ale, i,
- + 						     ALE_PORT_NO_SA_UPDATE, 1);
- + 			}
- + 
- + 			/* Clear All Untouched entries */
- + 			cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
- + 			do {
- + 				cpu_relax();
- + 				if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
- + 					break;
- + 			} while (time_after(timeout, jiffies));
- + 			cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
- + 
- + 			/* Clear all mcast from ALE */
- + 			cpsw_ale_flush_multicast(ale,
- + 					ALE_ALL_PORTS << priv->host_port);
- + 
- + 			/* Flood All Unicast Packets to Host port */
- + 			cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
- + 			dev_err(&ndev->dev, "promiscuity enabled\n");
- + 		} else {
- + 			/* Flood All Unicast Packets to Host port */
- + 			cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
- + 
- + 			/* Enable Learn for all ports */
- + 			for (i = 0; i <= priv->data.slaves; i++) {
- + 				cpsw_ale_control_set(ale, i,
- + 						     ALE_PORT_NOLEARN, 0);
- + 				cpsw_ale_control_set(ale, i,
- + 						     ALE_PORT_NO_SA_UPDATE, 0);
- + 			}
- + 
- + 			cpsw_ndo_set_rx_mode(ndev);
- + 			dev_err(&ndev->dev, "promiscuity disabled\n");
- + 		}
- + 	}
- + 
- + 	/*
- + 	 * The switch cannot filter multicast traffic unless it is configured
- + 	 * in "VLAN Aware" mode.  Unfortunately, VLAN awareness requires a
- + 	 * whole bunch of additional logic that this driver does not implement
- + 	 * at present.
- + 	 */
- + 	if ((flags & IFF_ALLMULTI) && !(ndev->flags & IFF_ALLMULTI))
- + 		dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n");
- + }
- + 
- + #define cpsw_p0_fifo_type_select(priv)
- + #define cpsw_add_dual_emac_mode_default_ale_entries(priv, slave, slave_port)
- + #define cpsw_update_slave_open_state(priv, state)
- + #define cpsw_common_res_usage_state(priv)	0
- + #define cpsw_tx_packet_submit(ndev, priv, skb)		\
- + 	cpdma_chan_submit(priv->txch, skb, skb->data,	\
- + 			  skb->len, 0, GFP_KERNEL)
- + 
- + static inline void cpsw_add_switch_mode_default_ale_entries(
- + 			struct cpsw_priv *priv)
- + {
- + 	cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
- + 			   priv->host_port, 0);
- + 	cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
- + 			   1 << priv->host_port, 0, 0);
- + }
- + 
- + #endif	/* CONFIG_TI_CPSW_DUAL_EMAC */
- + 
- + static int cpsw_set_coalesce(struct net_device *ndev,
- + 			struct ethtool_coalesce *coal);
- + 
- + static void cpsw_intr_enable(struct cpsw_priv *priv)
- + {
- + 	__raw_writel(0xFF, &priv->wr_regs->tx_en);
- + 	__raw_writel(0xFF, &priv->wr_regs->rx_en);
- + 
- + 	cpdma_ctlr_int_ctrl(priv->dma, true);
- + 	return;
- + }
- + 
- + static void cpsw_intr_disable(struct cpsw_priv *priv)
- + {
- + 	__raw_writel(0, &priv->wr_regs->tx_en);
- + 	__raw_writel(0, &priv->wr_regs->rx_en);
- + 
- + 	cpdma_ctlr_int_ctrl(priv->dma, false);
- + 	return;
- + }
- + 
- + void cpsw_tx_handler(void *token, int len, int status)
- + {
- + 	struct sk_buff		*skb = token;
- + 	struct net_device	*ndev = skb->dev;
- + 	struct cpsw_priv	*priv = netdev_priv(ndev);
- + 
- + 	if (unlikely(netif_queue_stopped(ndev)))
- + 		netif_start_queue(ndev);
- + 	cpts_tx_timestamp(priv->cpts, skb);
- + 	priv->stats.tx_packets++;
- + 	priv->stats.tx_bytes += len;
- + 	dev_kfree_skb_any(skb);
- + }
- + 
- + void cpsw_rx_handler(void *token, int len, int status)
- + {
- + 	struct sk_buff		*skb = token;
- + 	struct net_device	*ndev = skb->dev;
- + 	struct cpsw_priv	*priv = netdev_priv(ndev);
- + 	int			ret = 0;
- + 
- + 	cpsw_dual_emac_source_port_detect(status, priv, ndev, skb);
- + 
- + 	if (unlikely(!netif_running(ndev)) ||
- + 			unlikely(!netif_carrier_ok(ndev))) {
- + 		dev_kfree_skb_any(skb);
- + 		return;
- + 	}
- + 
- + 	if (likely(status >= 0)) {
- + 		skb_put(skb, len);
- + 		cpts_rx_timestamp(priv->cpts, skb);
- + 		skb->protocol = eth_type_trans(skb, ndev);
- + 		netif_receive_skb(skb);
- + 		priv->stats.rx_bytes += len;
- + 		priv->stats.rx_packets++;
- + 		skb = NULL;
- + 	}
- + 
- + 
- + 	if (unlikely(!netif_running(ndev))) {
- + 		if (skb)
- + 			dev_kfree_skb_any(skb);
- + 		return;
- + 	}
- + 
- + 	if (likely(!skb)) {
- + 		skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
- + 		if (WARN_ON(!skb))
- + 			return;
- + 
- + 		ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
- + 				skb_tailroom(skb), 0, GFP_KERNEL);
- + 	}
- + 
- + 	WARN_ON(ret < 0);
- + 
- + }
- + 
- + static void set_cpsw_dmtimer_clear(void)
- + {
- + 	omap_dm_timer_write_status(dmtimer_rx, OMAP_TIMER_INT_CAPTURE);
- + 	omap_dm_timer_write_status(dmtimer_tx, OMAP_TIMER_INT_CAPTURE);
- + 
- + 	return;
- + }
- + 
- + static irqreturn_t cpsw_interrupt(int irq, void *dev_id)
- + {
- + 	struct cpsw_priv *priv = dev_id;
- + 
- + 	if (likely(netif_running(priv->ndev))) {
- + 		cpsw_intr_disable(priv);
- + 		cpsw_disable_irq(priv);
- + 		napi_schedule(&priv->napi);
- + 	} else {
- + 		priv = cpsw_get_slave_priv(priv, 1);
- + 		if (likely(priv) && likely(netif_running(priv->ndev))) {
- + 			cpsw_intr_disable(priv);
- + 			cpsw_disable_irq(priv);
- + 			napi_schedule(&priv->napi);
- + 		}
- + 	}
- + 
- + 	return IRQ_HANDLED;
- + }
- + 
- + static int cpsw_poll(struct napi_struct *napi, int budget)
- + {
- + 	struct cpsw_priv	*priv = napi_to_priv(napi);
- + 	int			num_tx, num_rx;
- + 
- + 	num_tx = cpdma_chan_process(priv->txch, 128);
- + 	num_rx = cpdma_chan_process(priv->rxch, budget);
- + 
- + 	if (num_rx || num_tx)
- + 		msg(dbg, intr, "poll %d rx, %d tx pkts\n", num_rx, num_tx);
- + 
- + 	if (num_rx < budget) {
- + 		napi_complete(napi);
- + 		cpdma_ctlr_eoi(priv->dma);
- + 		set_cpsw_dmtimer_clear();
- + 		cpsw_intr_enable(priv);
- + 		cpsw_enable_irq(priv);
- + 	}
- + 
- + 	return num_rx;
- + }
- + 
- + static inline void soft_reset(const char *module, void __iomem *reg)
- + {
- + 	unsigned long timeout = jiffies + HZ;
- + 
- + 	__raw_writel(1, reg);
- + 	do {
- + 		cpu_relax();
- + 	} while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
- + 
- + 	WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
- + }
- + 
- + #define mac_hi(mac)	(((mac)[0] << 0) | ((mac)[1] << 8) |	\
- + 			 ((mac)[2] << 16) | ((mac)[3] << 24))
- + #define mac_lo(mac)	(((mac)[4] << 0) | ((mac)[5] << 8))
- + 
- + static void cpsw_set_slave_mac(struct cpsw_slave *slave,
- + 			       struct cpsw_priv *priv)
- + {
- + 	slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
- + 	slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
- + }
- + 
- + static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
- + {
- + 	if (priv->host_port == 0)
- + 		return slave_num + 1;
- + 	else
- + 		return slave_num;
- + }
- + 
- + static void _cpsw_adjust_link(struct cpsw_slave *slave,
- + 			      struct cpsw_priv *priv, bool *link)
- + {
- + 	struct phy_device	*phy = slave->phy;
- + 	u32			mac_control = 0;
- + 	u32			slave_port;
- + 	struct cpsw_platform_data *pdata;
- + 
- + 	if (!phy)
- + 		return;
- + 
- + 	slave_port = cpsw_get_slave_port(priv, slave->slave_num);
- + 
- + 	pdata = priv->pdev->dev.platform_data;
- + 	if (!pdata->gigabit_en)
- + 		phy->speed = 100;
- + 
- + 	if (phy->link) {
- + 		/* enable forwarding */
- + 		cpsw_ale_control_set(priv->ale, slave_port,
- + 			ALE_PORT_STATE, priv->port_state[slave_port]);
- + 
- + 		mac_control = priv->data.mac_control;
- + 		if (phy->speed == 10)
- + 			mac_control |= BIT(18); /* In Band mode */
- + 		if (phy->speed == 1000) {
- + 			mac_control |= BIT(7);	/* Enable gigabit mode */
- + 		}
- + 		if (phy->speed == 100)
- + 			mac_control |= BIT(15);
- + 		if (phy->duplex)
- + 			mac_control |= BIT(0);	/* FULLDUPLEXEN	*/
- + 		if (phy->interface == PHY_INTERFACE_MODE_RGMII) /* RGMII */
- + 			mac_control |= (BIT(15)|BIT(16));
- + 		*link = true;
- + 	} else {
- + 		cpsw_ale_control_set(priv->ale, slave_port,
- + 			     ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
- + 		mac_control = 0;
- + 	}
- + 
- + 	if (mac_control != slave->mac_control) {
- + 		phy_print_status(phy);
- + 		__raw_writel(mac_control, &slave->sliver->mac_control);
- + 	}
- + 
- + 	slave->mac_control = mac_control;
- + }
- + 
- + static void cpsw_adjust_link(struct net_device *ndev)
- + {
- + 	struct cpsw_priv	*priv = netdev_priv(ndev);
- + 	bool			link = false;
- + 
- + 	for_each_slave(priv, _cpsw_adjust_link, priv, &link);
- + 
- + 	if (link) {
- + 		netif_carrier_on(ndev);
- + 		if (netif_running(ndev))
- + 			netif_wake_queue(ndev);
- + 	} else {
- + 		netif_carrier_off(ndev);
- + 		netif_stop_queue(ndev);
- + 	}
- + }
- + 
- + static inline int __show_stat(char *buf, int maxlen, const char* name, u32 val)
- + {
- + 	static char *leader = "........................................";
- + 
- + 	if (!val)
- + 		return 0;
- + 	else
- + 		return snprintf(buf, maxlen, "%s %s %10d\n", name,
- + 				leader + strlen(name), val);
- + }
- + 
- + static ssize_t cpsw_hw_stats_show(struct device *dev,
- + 				     struct device_attribute *attr,
- + 				     char *buf)
- + {
- + 	struct net_device	*ndev = to_net_dev(dev);
- + 	struct cpsw_priv	*priv = netdev_priv(ndev);
- + 	int			len = 0;
- + 	struct cpdma_chan_stats	dma_stats;
- + 
- + #define show_stat(x) do {						\
- + 	len += __show_stat(buf + len, SZ_4K - len, #x,			\
- + 			   __raw_readl(&priv->hw_stats->x));		\
- + } while (0)
- + 
- + #define show_dma_stat(x) do {						\
- + 	len += __show_stat(buf + len, SZ_4K - len, #x, dma_stats.x);	\
- + } while (0)
- + 
- + 	len += snprintf(buf + len, SZ_4K - len, "CPSW Statistics:\n");
- + 	show_stat(rxgoodframes);	show_stat(rxbroadcastframes);
- + 	show_stat(rxmulticastframes);	show_stat(rxpauseframes);
- + 	show_stat(rxcrcerrors);		show_stat(rxaligncodeerrors);
- + 	show_stat(rxoversizedframes);	show_stat(rxjabberframes);
- + 	show_stat(rxundersizedframes);	show_stat(rxfragments);
- + 	show_stat(rxoctets);		show_stat(txgoodframes);
- + 	show_stat(txbroadcastframes);	show_stat(txmulticastframes);
- + 	show_stat(txpauseframes);	show_stat(txdeferredframes);
- + 	show_stat(txcollisionframes);	show_stat(txsinglecollframes);
- + 	show_stat(txmultcollframes);	show_stat(txexcessivecollisions);
- + 	show_stat(txlatecollisions);	show_stat(txunderrun);
- + 	show_stat(txcarriersenseerrors); show_stat(txoctets);
- + 	show_stat(octetframes64);	show_stat(octetframes65t127);
- + 	show_stat(octetframes128t255);	show_stat(octetframes256t511);
- + 	show_stat(octetframes512t1023);	show_stat(octetframes1024tup);
- + 	show_stat(netoctets);		show_stat(rxsofoverruns);
- + 	show_stat(rxmofoverruns);	show_stat(rxdmaoverruns);
- + 
- + 	cpdma_chan_get_stats(priv->rxch, &dma_stats);
- + 	len += snprintf(buf + len, SZ_4K - len, "\nRX DMA Statistics:\n");
- + 	show_dma_stat(head_enqueue);	show_dma_stat(tail_enqueue);
- + 	show_dma_stat(pad_enqueue);	show_dma_stat(misqueued);
- + 	show_dma_stat(desc_alloc_fail);	show_dma_stat(pad_alloc_fail);
- + 	show_dma_stat(runt_receive_buff); show_dma_stat(runt_transmit_buff);
- + 	show_dma_stat(empty_dequeue);	show_dma_stat(busy_dequeue);
- + 	show_dma_stat(good_dequeue);	show_dma_stat(teardown_dequeue);
- + 
- + 	cpdma_chan_get_stats(priv->txch, &dma_stats);
- + 	len += snprintf(buf + len, SZ_4K - len, "\nTX DMA Statistics:\n");
- + 	show_dma_stat(head_enqueue);	show_dma_stat(tail_enqueue);
- + 	show_dma_stat(pad_enqueue);	show_dma_stat(misqueued);
- + 	show_dma_stat(desc_alloc_fail);	show_dma_stat(pad_alloc_fail);
- + 	show_dma_stat(runt_receive_buff); show_dma_stat(runt_transmit_buff);
- + 	show_dma_stat(empty_dequeue);	show_dma_stat(busy_dequeue);
- + 	show_dma_stat(good_dequeue);	show_dma_stat(teardown_dequeue);
- + 
- + 	return len;
- + }
- + 
- + DEVICE_ATTR(hw_stats, S_IRUGO, cpsw_hw_stats_show, NULL);
- + 
- + #define PHY_CONFIG_REG	22
- + static void cpsw_set_phy_config(struct cpsw_priv *priv, struct phy_device *phy)
- + {
- + 	struct cpsw_platform_data *pdata = priv->pdev->dev.platform_data;
- + 	struct mii_bus *miibus;
- + 	int phy_addr = 0;
- + 	u16 val = 0;
- + 	u16 tmp = 0;
- + 
- + 	if (!phy)
- + 		return;
- + 
- + 	miibus = phy->bus;
- + 	
- + 	if (!miibus)
- + 		return;
- + 
- + 	phy_addr = phy->addr;
- + 
- + 	/* Disable 1 Gig mode support if it is not supported */
- + 	if (!pdata->gigabit_en)
- + 	{
- + 		phy->supported &= ~(SUPPORTED_1000baseT_Half |
- + 					SUPPORTED_1000baseT_Full);
- + 		phy->speed = 100;
- + 	}
- + 	/* Following lines enable gigbit advertisement capability even in case
- + 	 * the advertisement is not enabled by default
- + 	 */
- + 	val = miibus->read(miibus, phy_addr, MII_BMCR);
- + 	val |= (BMCR_SPEED100 | BMCR_ANENABLE | BMCR_FULLDPLX);
- + 	if (!pdata->gigabit_en)
- + 	{
- + 		val &= ~BMCR_SPEED1000;
- + 	}
- + 	miibus->write(miibus, phy_addr, MII_BMCR, val);
- + 	tmp = miibus->read(miibus, phy_addr, MII_BMCR);
- + 	
- + 	/* Enable gigabit support only if the speed is 1000Mbps */
- + 	if (phy->speed == CPSW_PHY_SPEED) {
- + 		tmp = miibus->read(miibus, phy_addr, MII_BMSR);
- + 		if (tmp & 0x1) {
- + 			val = miibus->read(miibus, phy_addr, MII_CTRL1000);
- + 			val |= BIT(9);
- + 			miibus->write(miibus, phy_addr, MII_CTRL1000, val);
- + 			tmp = miibus->read(miibus, phy_addr, MII_CTRL1000);
- + 		}
- + 	}
- + 
- + 	val = miibus->read(miibus, phy_addr, MII_ADVERTISE);
- + 	val |= (ADVERTISE_10HALF | ADVERTISE_10FULL | \
- + 		ADVERTISE_100HALF | ADVERTISE_100FULL);
- + 	if (!pdata->gigabit_en)
- + 	{
- + 		val &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF
- + 					| ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM);
- + 	}
- + 
- + 	miibus->write(miibus, phy_addr, MII_ADVERTISE, val);
- + 	tmp = miibus->read(miibus, phy_addr, MII_ADVERTISE);
- + 	/* TODO : This check is required. This should be
- + 	 * moved to a board init section as its specific
- + 	 * to a phy.*/
- + 	if (phy->phy_id == 0x0282F014) {
- + 		/* This enables TX_CLK-ing in case of 10/100MBps operation */
- + 		val = miibus->read(miibus, phy_addr, PHY_CONFIG_REG);
- + 		val |= BIT(5);
- + 		miibus->write(miibus, phy_addr, PHY_CONFIG_REG, val);
- + 		tmp = miibus->read(miibus, phy_addr, PHY_CONFIG_REG);
- + 	}
- + 
- + 	return;
- + }
- + 
- + static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
- + {
- + 	char name[32];
- + 	u32 slave_port;
- + 
- + 	sprintf(name, "slave-%d", slave->slave_num);
- + 
- + 	soft_reset(name, &slave->sliver->soft_reset);
- + 
- + 	/* setup priority mapping */
- + 	writel(0x76543210, &slave->sliver->rx_pri_map);
- + 	if (priv->version == CPSW_VERSION1)
- + 		slave_write(slave, 0x33221100, CPSW1_TX_PRI_MAP);
- + 	else
- + 		slave_write(slave, 0x33221100, CPSW2_TX_PRI_MAP);
- + 
- + 	/* setup max packet size, and mac address */
- + 	__raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
- + 	cpsw_set_slave_mac(slave, priv);
- + 
- + 	slave->mac_control = 0;	/* no link yet */
- + 
- + 	slave_port = cpsw_get_slave_port(priv, slave->slave_num);
- + 
- + 	cpsw_add_dual_emac_mode_default_ale_entries(priv, slave, slave_port);
- + 	cpsw_add_switch_mode_bcast_ale_entries(priv, slave_port);
- + 	priv->port_state[slave_port] = ALE_PORT_STATE_FORWARD;
- + 
- + 	slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
- + 				 &cpsw_adjust_link, 0, slave->data->phy_if);
- + 	if (IS_ERR(slave->phy)) {
- + 		msg(err, ifup, "phy %s not found on slave %d\n",
- + 		    slave->data->phy_id, slave->slave_num);
- + 		slave->phy = NULL;
- + 	} else {
- + 		dev_info(priv->dev, "CPSW phy found : id is : 0x%x\n",
- + 			slave->phy->phy_id);
- + 		cpsw_set_phy_config(priv, slave->phy);
- + 		phy_start(slave->phy);
- + 	}
- + }
- + 
- + #if defined(VLAN_SUPPORT) && !defined(CONFIG_TI_CPSW_DUAL_EMAC)
- + static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
- + {
- + 	writel(priv->data.default_vlan, &priv->host_port_regs->port_vlan);
- + 	if (priv->version == CPSW_VERSION1) {
- + 		slave_write(&priv->slaves[0], priv->data.default_vlan,
- + 			    CPSW1_PORT_VLAN);
- + 		slave_write(&priv->slaves[1], priv->data.default_vlan,
- + 			    CPSW1_PORT_VLAN);
- + 	} else {
- + 		slave_write(&priv->slaves[0], priv->data.default_vlan,
- + 			    CPSW2_PORT_VLAN);
- + 		slave_write(&priv->slaves[1], priv->data.default_vlan,
- + 			    CPSW2_PORT_VLAN);
- + 	}
- + 	cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan,
- + 			ALE_ALL_PORTS << priv->host_port,
- + 			ALE_ALL_PORTS << priv->host_port,
- + 			ALE_ALL_PORTS << priv->host_port, 0);
- + }
- + #else
- + #define cpsw_add_default_vlan(priv)
- + #endif
- + 
- + static void cpsw_init_host_port(struct cpsw_priv *priv)
- + {
- + 	u32 control_reg;
- + 
- + 	/* soft reset the controller and initialize ale */
- + 	soft_reset("cpsw", &priv->regs->soft_reset);
- + 	cpsw_ale_start(priv->ale);
- + 
- + 	/* switch to vlan aware/unaware mode */
- + 	cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
- + 			     CPSW_ALE_VLAN_AWARE);
- + 	control_reg = readl(&priv->regs->control);
- + 	control_reg |= CPSW_VLAN_AWARE;
- + 	writel(control_reg, &priv->regs->control);
- + 	cpsw_p0_fifo_type_select(priv);
- + 
- + 	/* setup host port priority mapping */
- + 	__raw_writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map);
- + 	__raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
- + 
- + 	cpsw_ale_control_set(priv->ale, priv->host_port,
- + 			     ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
- + 
- + 	cpsw_add_switch_mode_default_ale_entries(priv);
- + }
- + 
- + static int cpsw_ndo_open(struct net_device *ndev)
- + {
- + 	struct cpsw_priv *priv = netdev_priv(ndev);
- + 	int i, ret;
- + 	u32 reg;
- + 
- + 	if (!cpsw_common_res_usage_state(priv))
- + 		cpsw_intr_disable(priv);
- + 	netif_carrier_off(ndev);
- + 
- + 	if (priv->data.phy_control)
- + 		(*priv->data.phy_control)(true);
- + 
- + 	reg = __raw_readl(&priv->regs->id_ver);
- + 	priv->version = reg;
- + 
- + 	msg(info, ifup, "initializing cpsw version %d.%d (%d)\n",
- + 	    (reg >> 8 & 0x7), reg & 0xff, (reg >> 11) & 0x1f);
- + 
- + 	/* initialize host and slave ports */
- + 	if (!cpsw_common_res_usage_state(priv))
- + 		cpsw_init_host_port(priv);
- + 	for_each_slave(priv, cpsw_slave_open, priv);
- + 
- + 	/* Add default VLAN */
- + 	cpsw_add_default_vlan(priv);
- + 
- + 	if (!cpsw_common_res_usage_state(priv)) {
- + 		ret = device_create_file(&ndev->dev, &dev_attr_hw_stats);
- + 		if (ret < 0) {
- + 			dev_err(priv->dev, "unable to add device attr\n");
- + 			return ret;
- + 		}
- + 
- + 		/* setup tx dma to fixed prio and zero offset */
- + 		cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
- + 		cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
- + 
- + 		/* disable priority elevation and enable statistics */
- + 		/* on all ports */
- + 		writel(0, &priv->regs->ptype);
- + 		writel(0x7, &priv->regs->stat_port_en);
- + 
- + 		if (WARN_ON(!priv->data.rx_descs))
- + 			priv->data.rx_descs = 128;
- + 
- + 		for (i = 0; i < priv->data.rx_descs; i++) {
- + 			struct sk_buff *skb;
- + 
- + 			ret = -ENOMEM;
- + 			skb = netdev_alloc_skb_ip_align(priv->ndev,
- + 							priv->rx_packet_max);
- + 			if (!skb)
- + 				break;
- + 			ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
- + 					skb_tailroom(skb), 0, GFP_KERNEL);
- + 			if (WARN_ON(ret < 0)) {
- + 				dev_kfree_skb_any(skb);
- + 				break;
- + 			}
- + 		}
- + 		/*
- + 		 * continue even if we didn't manage to submit all
- + 		 * receive descs
- + 		 */
- + 		msg(info, ifup, "submitted %d rx descriptors\n", i);
- + 
- + 		if (cpts_register(&priv->pdev->dev, priv->cpts,
- + 				  priv->data.cpts_clock_mult,
- + 				  priv->data.cpts_clock_shift))
- + 			dev_err(priv->dev, "error registering cpts device\n");
- + 	}
- + 
- + 	/* Enable Interrupt pacing if configured */
- + 	if (priv->coal_intvl != 0) {
- + 		struct ethtool_coalesce coal;
- + 
- + 		coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
- + 		cpsw_set_coalesce(ndev, &coal);
- + 	}
- + 
- + 	/* Enable Timer for capturing cpsw rx interrupts */
- + 	omap_dm_timer_set_int_enable(dmtimer_rx, OMAP_TIMER_INT_CAPTURE);
- + 	omap_dm_timer_set_capture(dmtimer_rx, 1, 0, 0);
- + 	omap_dm_timer_enable(dmtimer_rx);
- + 
- + 	/* Enable Timer for capturing cpsw tx interrupts */
- + 	omap_dm_timer_set_int_enable(dmtimer_tx, OMAP_TIMER_INT_CAPTURE);
- + 	omap_dm_timer_set_capture(dmtimer_tx, 1, 0, 0);
- + 	omap_dm_timer_enable(dmtimer_tx);
- + 
- + 	cpdma_ctlr_start(priv->dma);
- + 	cpsw_intr_enable(priv);
- + 	napi_enable(&priv->napi);
- + 	cpdma_ctlr_eoi(priv->dma);
- + 
- + 	cpsw_update_slave_open_state(priv, true)
- + 
- + 	return 0;
- + }
- + 
- + static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
- + {
- + 	if (!slave->phy)
- + 		return;
- + 	phy_stop(slave->phy);
- + 	phy_disconnect(slave->phy);
- + 	slave->phy = NULL;
- + }
- + 
- + static int cpsw_ndo_stop(struct net_device *ndev)
- + {
- + 	struct cpsw_priv *priv = netdev_priv(ndev);
- + 
- + 	msg(info, ifdown, "shutting down cpsw device\n");
- + 
- + 	netif_stop_queue(priv->ndev);
- + 	napi_disable(&priv->napi);
- + 	netif_carrier_off(priv->ndev);
- + 
- + 	if (cpsw_common_res_usage_state(priv) <= 1) {
- + 		cpsw_intr_disable(priv);
- + 		cpdma_ctlr_int_ctrl(priv->dma, false);
- + 
- + 		omap_dm_timer_set_int_enable(dmtimer_rx, 0);
- + 		omap_dm_timer_set_int_enable(dmtimer_tx, 0);
- + 
- + 		cpdma_ctlr_stop(priv->dma);
- + 		cpsw_ale_stop(priv->ale);
- + 
- + 		cpts_unregister(priv->cpts);
- + 	}
- + 
- + 	device_remove_file(&ndev->dev, &dev_attr_hw_stats);
- + 	for_each_slave(priv, cpsw_slave_stop, priv);
- + 	if (priv->data.phy_control)
- + 		(*priv->data.phy_control)(false);
- + 
- + 	cpsw_update_slave_open_state(priv, false)
- + 
- + 	return 0;
- + }
- + 
- + static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
- + 				       struct net_device *ndev)
- + {
- + 	struct cpsw_priv *priv = netdev_priv(ndev);
- + 	int ret;
- + 
- + 	ndev->trans_start = jiffies;
- + 
- + 	ret = skb_padto(skb, CPSW_MIN_PACKET_SIZE);
- + 	if (unlikely(ret < 0)) {
- + 		msg(err, tx_err, "packet pad failed");
- + 		goto fail;
- + 	}
- + 
- + 	if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
- + 			priv->cpts->tx_enable)
- + 		skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
- + 
- + 	skb_tx_timestamp(skb);
- + 
- + 	ret = cpsw_tx_packet_submit(ndev, priv, skb);
- + 	if (unlikely(ret != 0)) {
- + 		msg(err, tx_err, "desc submit failed");
- + 		goto fail;
- + 	}
- + 
- + 	return NETDEV_TX_OK;
- + fail:
- + 	priv->stats.tx_dropped++;
- + 	netif_stop_queue(ndev);
- + 	return NETDEV_TX_BUSY;
- + }
- + 
- + #ifndef CONFIG_TI_CPSW_DUAL_EMAC
- + /*
- +  *  cpsw_set_priority_mapping
- +  *    This function configures the packet priority handling on each port.
- +  */
- + static int cpsw_set_priority_mapping(struct cpsw_priv *priv, int port,
- + 	int rxpriority, int txpriority, int switchpriority)
- + {
- + 	if (port == 0) {
- + 		writel(CPSW_PRIMAP(rxpriority, txpriority),
- + 			&priv->host_port_regs->cpdma_tx_pri_map);
- + 		writel(CPSW_PRIMAP(txpriority, switchpriority),
- + 			&priv->host_port_regs->cpdma_tx_pri_map);
- + 	} else {
- + 		/* Configure sliver priority mapping registers */
- + 		writel(CPSW_PRIMAP(rxpriority, txpriority),
- + 			&slave(priv, port-1)->sliver->rx_pri_map);
- + 		writel(CPSW_PRIMAP(txpriority, switchpriority),
- + 			&slave(priv, port-1)->sliver->rx_pri_map);
- + 	}
- + 	return 0;
- + }
- + 
- + /*
- +  * cpsw_rate_limit_tx
- +  * Limits the number of Tx packets on a port for a 100ms time period.
- +  * Rate limit can be done either on Tx or Rx for all the ports due to
- +  * hardware limitation
- +  */
- + static int cpsw_rate_limit_tx(struct cpsw_ale *ale, u32 enable, u32 port,
- + 				u32 addr_type, u32 limit)
- + {
- + 	u32 type;
- + 
- + 	if (!enable) {
- + 		cpsw_ale_control_set(ale, port, ALE_RATE_LIMIT, 0);
- + 		return 0;
- + 	}
- + 
- + 	/* ALE prescale is set for 100 ms time */
- + 	if (addr_type == ADDR_TYPE_BROADCAST)
- + 		type = ALE_PORT_BCAST_LIMIT;
- + 	else if (addr_type == ADDR_TYPE_MULTICAST)
- + 		type = ALE_PORT_MCAST_LIMIT;
- + 	else
- + 		return -EFAULT;
- + 
- + 	cpsw_ale_control_set(ale, port, type, limit);
- + 	/* Enable the bit for rate limiting transmission */
- + 	cpsw_ale_control_set(ale, port, ALE_RATE_LIMIT_TX, 1);
- + 	cpsw_ale_control_set(ale, port, ALE_RATE_LIMIT, 1);
- + 
- + 	return 0;
- + }
- + 
- + /*
- +  * cpsw_rate_limit_rx
- +  * Limits the number of Rx packets on a port for a 100ms time period.
- +  * Rate limit can be done either on Tx or Rx for all the ports due to
- +  * hardware limitation
- +  */
- + static int cpsw_rate_limit_rx(struct cpsw_ale *ale, u32 enable, u32 port,
- + 				u32 addr_type, u32 limit)
- + {
- + 	u32 type;
- + 
- + 	if (!enable) {
- + 		cpsw_ale_control_set(ale, port, ALE_RATE_LIMIT, 0);
- + 		return 0;
- + 	}
- + 
- + 	/* ALE prescale is set for 100 ms time */
- + 	if (addr_type == ADDR_TYPE_BROADCAST)
- + 		type = ALE_PORT_BCAST_LIMIT;
- + 	else if (addr_type == ADDR_TYPE_MULTICAST)
- + 		type = ALE_PORT_MCAST_LIMIT;
- + 	else
- + 		return -EFAULT;
- + 
- + 	cpsw_ale_control_set(ale, port, type, limit);
- + 	/* Disable the bit for rate limiting reception */
- + 	cpsw_ale_control_set(ale, port, ALE_RATE_LIMIT_TX, 0);
- + 	cpsw_ale_control_set(ale, port, ALE_RATE_LIMIT, 1);
- + 
- + 	return 0;
- + }
- + 
- + int cpsw_rate_limit(struct cpsw_ale *ale, u32 enable, u32 direction, u32 port,
- + 			u32 packet_type, u32 limit)
- + {
- + 
- + 	if (port == 0) {
- + 		/*
- + 		 * For host port transmit/receive terminlogy is inverse
- + 		 * of cpgmac port
- + 		 */
- + 		if (direction)
- + 			cpsw_rate_limit_rx(ale, enable, port,
- + 					packet_type, limit);
- + 		else
- + 			cpsw_rate_limit_tx(ale, enable, port,
- + 					packet_type, limit);
- + 	} else {
- + 		if (direction)
- + 			cpsw_rate_limit_tx(ale, enable, port,
- + 					packet_type, limit);
- + 		else
- + 			cpsw_rate_limit_rx(ale, enable, port,
- + 					packet_type, limit);
- + 	}
- + 	return 0;
- + }
- + 
- + static int cpsw_config_dump(struct cpsw_priv *priv, u8 *buf, u32 size)
- + {
- + 	int vlan_aware = 0;
- + 	int out_len = 0;
- + 	u32 port_state;
- + 	char *port_state_str[] = {"disabled", "blocked", "learn", "forward"};
- + 
- + 	out_len += snprintf(buf, size, "Switch Configuarion\n");
- + 
- + 	vlan_aware = readl(&priv->regs->control) & CPSW_VLAN_AWARE;
- + 
- + 	out_len += snprintf(buf + out_len, size - out_len, "VLAN Aware Mode"
- + 			"                              :  %s\n",
- + 			(vlan_aware ? "Yes" : "No"));
- + 	out_len += snprintf(buf + out_len, size - out_len, "ALE VLAN Aware "
- + 			"Mode                          :  %s\n",
- + 			(cpsw_ale_control_get(priv->ale, priv->host_port,
- + 				ALE_VLAN_AWARE) ? "Yes" : "No"));
- + 	out_len += snprintf(buf + out_len, size - out_len, "Unknown VLAN "
- + 			"Members                         :  %u\n",
- + 			cpsw_ale_control_get(priv->ale, 0,
- + 				ALE_PORT_UNKNOWN_VLAN_MEMBER));
- + 	out_len += snprintf(buf + out_len, size - out_len, "Unknown Multicast"
- + 			" Flood Mask                 :  %u\n",
- + 			cpsw_ale_control_get(priv->ale, 0,
- + 				ALE_PORT_UNKNOWN_MCAST_FLOOD));
- + 	out_len += snprintf(buf + out_len, size - out_len, "Unknown Registered"
- + 			" Multicast Flood Mask      :  %u\n",
- + 			cpsw_ale_control_get(priv->ale, 0,
- + 				ALE_PORT_UNKNOWN_REG_MCAST_FLOOD));
- + 	out_len += snprintf(buf + out_len, size - out_len, "Unknown VLAN Force"
- + 			" Untagged Egress           :  %u\n",
- + 			cpsw_ale_control_get(priv->ale, 0,
- + 				ALE_PORT_UNTAGGED_EGRESS));
- + 
- + 	out_len += snprintf(buf + out_len, size - out_len,
- + 			"\nPort Configuration\n");
- + 	out_len += snprintf(buf + out_len, size - out_len,
- + 			"\t%-8s %-8s %-8s %s\n", "PORT", "PVID", "PRIORITY",
- + 			"STATE");
- + 	out_len += snprintf(buf + out_len, size - out_len,
- + 			"\t---------------------------------\n");
- + 
- + 	if (vlan_aware) {
- + 		int port_vlan;
- + 		struct cpsw_slave *slave;
- + 
- + 		port_state = cpsw_ale_control_get(priv->ale, 0, ALE_PORT_STATE);
- + 		port_vlan = readl(&priv->host_port_regs->port_vlan);
- + 		out_len += snprintf(buf + out_len, size - out_len,
- + 			"\t%-8u %-8u %-8u %s\n", 0,
- + 			port_vlan & 0xfff, (port_vlan > 13) & 0x7,
- + 			port_state_str[port_state]);
- + 
- + 		port_state = cpsw_ale_control_get(priv->ale, 1, ALE_PORT_STATE);
- + 		slave = &priv->slaves[0];
- + 		if (priv->version == CPSW_VERSION1)
- + 			port_vlan = slave_read(slave, CPSW1_PORT_VLAN);
- + 		else
- + 			port_vlan = slave_read(slave, CPSW2_PORT_VLAN);
- + 		out_len += snprintf(buf + out_len, size - out_len,
- + 			"\t%-8u %-8u %-8u %s\n", 1,
- + 			port_vlan & 0xfff, (port_vlan > 13) & 0x7,
- + 			port_state_str[port_state]);
- + 
- + 		port_state = cpsw_ale_control_get(priv->ale, 2, ALE_PORT_STATE);
- + 		slave = &priv->slaves[1];
- + 		if (priv->version == CPSW_VERSION1)
- + 			port_vlan = slave_read(slave, CPSW1_PORT_VLAN);
- + 		else
- + 			port_vlan = slave_read(slave, CPSW2_PORT_VLAN);
- + 		out_len += snprintf(buf + out_len, size - out_len,
- + 			"\t%-8u %-8u %-8u %s\n", 2,
- + 			port_vlan & 0xfff, (port_vlan > 13) & 0x7,
- + 			port_state_str[port_state]);
- + 	} else {
- + 		port_state = cpsw_ale_control_get(priv->ale, 0, ALE_PORT_STATE);
- + 		out_len += snprintf(buf + out_len, size - out_len,
- + 			"\t%-8u %-8s %-8s %s\n", 0,
- + 			"-", "-", port_state_str[port_state]);
- + 
- + 		port_state = cpsw_ale_control_get(priv->ale, 1, ALE_PORT_STATE);
- + 		out_len += snprintf(buf + out_len, size - out_len,
- + 			"\t%-8u %-8s %-8s %s\n", 1,
- + 			"-", "-", port_state_str[port_state]);
- + 
- + 		port_state = cpsw_ale_control_get(priv->ale, 2, ALE_PORT_STATE);
- + 		out_len += snprintf(buf + out_len, size - out_len,
- + 			"\t%-8u %-8s %-8s %s\n", 2,
- + 			"-", "-", port_state_str[port_state]);
- + 	}
- + 
- + 	return out_len;
- + }
- + 
- + static int cpsw_set_port_state(struct cpsw_priv *priv, int port,
- + 			int port_state)
- + {
- + 	int ret = -EFAULT;
- + 	switch (port_state) {
- + 	case PORT_STATE_DISABLED:
- + 		priv->port_state[port] = ALE_PORT_STATE_DISABLE;
- + 		break;
- + 	case PORT_STATE_BLOCKED:
- + 		priv->port_state[port] = ALE_PORT_STATE_BLOCK;
- + 		break;
- + 	case PORT_STATE_LEARN:
- + 		priv->port_state[port] = ALE_PORT_STATE_LEARN;
- + 		break;
- + 	case PORT_STATE_FORWARD:
- + 		priv->port_state[port] = ALE_PORT_STATE_FORWARD;
- + 		break;
- + 	}
- + 	ret = cpsw_ale_control_set(priv->ale, port, ALE_PORT_STATE,
- + 			priv->port_state[port]);
- + 
- + 	return ret;
- + }
- + 
- + static int cpsw_switch_config_ioctl(struct net_device *ndev,
- + 		struct ifreq *ifrq, int cmd)
- + {
- + 	struct cpsw_priv *priv = netdev_priv(ndev);
- + 	struct net_switch_config *switch_config;
- + 	int ret = -EFAULT;
- + 
- + 	/*
- + 	* Only SIOCSWITCHCONFIG is used as cmd argument and hence, there is no
- + 	* switch statement required.
- + 	* Function calls are based on switch_config.cmd
- + 	*/
- + 	if (cmd != SIOCSWITCHCONFIG)
- + 		return ret;
- + 
- + 	switch_config = kzalloc(sizeof(struct net_switch_config), GFP_KERNEL);
- + 	if (copy_from_user(switch_config, (ifrq->ifr_data),
- + 			sizeof(struct net_switch_config)))
- + 		return ret;
- + 
- + 	switch (switch_config->cmd) {
- + 	case CONFIG_SWITCH_ADD_MULTICAST:
- + 		if ((switchcmd(switch_config).untag_port <= 3) &&
- + 				(switchcmd(switch_config).vid <= 4095) &&
- + 				(switchcmd(switch_config).mem_port > 0) &&
- + 				(switchcmd(switch_config).mem_port <= 7) &&
- + 				is_multicast_ether_addr(
- + 				switchcmd(switch_config).addr)) {
- + 			if (switchcmd(switch_config).vid == 0)
- + 				ret = cpsw_ale_add_mcast(priv->ale,
- + 					switchcmd(switch_config).addr,
- + 					switchcmd(switch_config).mem_port
- + 						<< priv->host_port,
- + 					switchcmd(switch_config).flag,
- + 					switchcmd(switch_config).untag_port);
- + 			else
- + 				ret = cpsw_ale_vlan_add_mcast(priv->ale,
- + 					switchcmd(switch_config).addr,
- + 					switchcmd(switch_config).mem_port
- + 						<< priv->host_port,
- + 					switchcmd(switch_config).vid,
- + 					switchcmd(switch_config).flag,
- + 					switchcmd(switch_config).untag_port);
- + 		} else {
- + 			dev_err(priv->dev, "Invalid Switch config arguments\n");
- + 			ret = -EFAULT;
- + 		}
- + 		break;
- + 
- + 	case CONFIG_SWITCH_ADD_UNICAST:
- + 		if ((switchcmd(switch_config).vid <= 4095) &&
- + 				(switchcmd(switch_config).mem_port <= 2) &&
- + 				is_valid_ether_addr(
- + 					switchcmd(switch_config).addr)) {
- + 			if (switchcmd(switch_config).vid == 0)
- + 				ret = cpsw_ale_add_ucast(priv->ale,
- + 					switchcmd(switch_config).addr,
- + 					priv->host_port, 0);
- + 			else
- + 				ret = cpsw_ale_vlan_add_ucast(priv->ale,
- + 					switchcmd(switch_config).addr,
- + 					priv->host_port, 0,
- + 					switchcmd(switch_config).vid);
- + 		} else {
- + 			dev_err(priv->dev, "Invalid Switch config arguments\n");
- + 			ret = -EFAULT;
- + 		}
- + 		break;
- + 
- + 	case CONFIG_SWITCH_ADD_OUI:
- + 		if (!is_zero_ether_addr(switchcmd(switch_config).addr)) {
- + 			ret = cpsw_ale_add_oui(priv->ale,
- + 				switchcmd(switch_config).addr);
- + 		} else {
- + 			dev_err(priv->dev, "Invalid Switch config arguments\n");
- + 			ret = -EFAULT;
- + 		}
- + 		break;
- + 
- + 	case CONFIG_SWITCH_FIND_ADDR:
- + 		if ((switchcmd(switch_config).vid <= 4095) &&
- + 			!is_zero_ether_addr(switchcmd(switch_config).addr)) {
- + 			ret = cpsw_ale_match_addr(priv->ale,
- + 				switchcmd(switch_config).addr,
- + 				switchcmd(switch_config).vid);
- + 			if (ret >= 0) {
- + 				switch_config->ret_type = ret;
- + 				ret = copy_to_user(ifrq->ifr_data,
- + 					switch_config,
- + 					sizeof(struct net_switch_config)) ?
- + 					-EFAULT : 0;
- + 			}
- + 		} else {
- + 			dev_err(priv->dev, "Invalid Arguments\n");
- + 			ret = -EFAULT;
- + 		}
- + 		break;
- + 
- + 	case CONFIG_SWITCH_DEL_MULTICAST:
- + 		if ((switchcmd(switch_config).vid <= 4095) &&
- + 				is_multicast_ether_addr(
- + 				switchcmd(switch_config).addr)) {
- + 			if (switchcmd(switch_config).vid == 0)
- + 				ret = cpsw_ale_del_mcast(priv->ale,
- + 					switchcmd(switch_config).addr,
- + 					switchcmd(switch_config).mem_port
- + 						<< priv->host_port);
- + 			else
- + 				ret = cpsw_ale_vlan_del_mcast(priv->ale,
- + 					switchcmd(switch_config).addr,
- + 					switchcmd(switch_config).mem_port
- + 						<< priv->host_port,
- + 					switchcmd(switch_config).vid);
- + 		} else {
- + 			dev_err(priv->dev, "Invalid Arguments\n");
- + 			ret = -EFAULT;
- + 		}
- + 		break;
- + 
- + 	case CONFIG_SWITCH_DEL_UNICAST:
- + 		if ((switchcmd(switch_config).vid <= 4095) &&
- + 			is_valid_ether_addr(switchcmd(switch_config).addr)) {
- + 			if (switchcmd(switch_config).vid == 0) {
- + 				if (!memcmp(switchcmd(switch_config).addr,
- + 						priv->mac_addr, 6)) {
- + 					ret = -EPERM;
- + 					break;
- + 				}
- + 				ret = cpsw_ale_del_ucast(priv->ale,
- + 					switchcmd(switch_config).addr, 0);
- + 			} else
- + 				ret = cpsw_ale_del_ucast(priv->ale,
- + 					switchcmd(switch_config).addr,
- + 					switchcmd(switch_config).vid);
- + 		} else {
- + 			dev_err(priv->dev, "Invalid Arguments\n");
- + 			ret = -EFAULT;
- + 		}
- + 		break;
- + 
- + 	case CONFIG_SWITCH_ADD_VLAN:
- + 		if ((switchcmd(switch_config).vid <= 4095) &&
- + 				(switchcmd(switch_config).mem_port > 0) &&
- + 				(switchcmd(switch_config).mem_port <= 7)) {
- + 			ret = cpsw_ale_add_vlan(priv->ale,
- + 				switchcmd(switch_config).vid,
- + 				switchcmd(switch_config).mem_port
- + 					<< priv->host_port,
- + 				switchcmd(switch_config).untag_port,
- + 				switchcmd(switch_config).reg_multi,
- + 				switchcmd(switch_config).unreg_multi);
- + 		} else {
- + 			dev_err(priv->dev, "Invalid Arguments\n");
- + 			ret = -EFAULT;
- + 		}
- + 		break;
- + 
- + 	case CONFIG_SWITCH_FIND_VLAN:
- + 		if (switchcmd(switch_config).vid <= 4095) {
- + 			switch_config->ret_type = cpsw_ale_match_vlan(priv->ale,
- + 				switchcmd(switch_config).vid);
- + 			ret = copy_to_user(ifrq->ifr_data, switch_config,
- + 				sizeof(struct net_switch_config)) ?
- + 				-EFAULT : 0;
- + 		} else {
- + 			dev_err(priv->dev, "Invalid Arguments\n");
- + 			ret = -EFAULT;
- + 		}
- + 		break;
- + 
- + 	case CONFIG_SWITCH_DEL_VLAN:
- + 		if ((switchcmd(switch_config).vid <= 4095) &&
- + 				(switchcmd(switch_config).mem_port <= 7)) {
- + 			ret = cpsw_ale_del_vlan(priv->ale,
- + 				switchcmd(switch_config).vid,
- + 				switchcmd(switch_config).mem_port
- + 				<< priv->host_port);
- + 		} else {
- + 			dev_err(priv->dev, "Invalid Arguments\n");
- + 			ret = -EFAULT;
- + 		}
- + 		break;
- + 
- + 	case CONFIG_SWITCH_SET_PORT_VLAN_CONFIG:
- + 	{
- + 		int port_vlan = switchcmd(switch_config).vid |
- + 				switchcmd(switch_config).prio_port << 13;
- + 
- + 		if ((switchcmd(switch_config).vid <= 4095) &&
- + 				(switchcmd(switch_config).port <= 2) &&
- + 				(switchcmd(switch_config).prio_port <= 7)) {
- + 			if (switchcmd(switch_config).CFI_port)
- + 				port_vlan |= (1 << 12);
- + 
- + 			if (switchcmd(switch_config).port == 0) {
- + 				writel(port_vlan,
- + 					&priv->host_port_regs->port_vlan);
- + 			} else if (switchcmd(switch_config).port == 1) {
- + 				if (priv->version == CPSW_VERSION1)
- + 					slave_write(&priv->slaves[0], port_vlan,
- + 						    CPSW1_PORT_VLAN);
- + 				else
- + 					slave_write(&priv->slaves[0], port_vlan,
- + 						    CPSW2_PORT_VLAN);
- + 			} else {
- + 				if (priv->version == CPSW_VERSION1)
- + 					slave_write(&priv->slaves[1], port_vlan,
- + 						    CPSW1_PORT_VLAN);
- + 				else
- + 					slave_write(&priv->slaves[1], port_vlan,
- + 						    CPSW2_PORT_VLAN);
- + 			}
- + 			ret = 0;
- + 		} else {
- + 			dev_err(priv->dev, "Invalid Arguments\n");
- + 			ret = -EFAULT;
- + 		}
- + 		break;
- + 	}
- + 
- + 	case CONFIG_SWITCH_TIMEOUT:
- + 		ret = cpsw_ale_set_ageout(priv->ale,
- + 			switchcmd(switch_config).ale_timeout);
- + 		break;
- + 
- + 	case CONFIG_SWITCH_DUMP:
- + 		ret = cpsw_ale_dump(priv->ale,
- + 			switchcmd(switch_config).aledump,
- + 			switch_config->cmd_data.buf, 4095);
- + 		if (ret)
- + 			ret = copy_to_user(ifrq->ifr_data, switch_config,
- + 				sizeof(struct net_switch_config)) ?
- + 				-EFAULT : 0;
- + 		break;
- + 
- + 	case CONFIG_SWITCH_SET_FLOW_CONTROL:
- + 		if (portcmd(switch_config).port <= 7) {
- + 			writel(portcmd(switch_config).port,
- + 				&priv->regs->flow_control);
- + 		} else {
- + 			dev_err(priv->dev, "Invalid Arguments\n");
- + 			ret = -EFAULT;
- + 		}
- + 		break;
- + 
- + 	case CONFIG_SWITCH_SET_PRIORITY_MAPPING:
- + 		if ((priocmd(switch_config).port <= 2) &&
- + 			(priocmd(switch_config).prio_rx <= 7) &&
- + 			(priocmd(switch_config).prio_tx <= 7) &&
- + 			(priocmd(switch_config).prio_switch <= 3)) {
- + 			ret = cpsw_set_priority_mapping(priv,
- + 				priocmd(switch_config).port,
- + 				priocmd(switch_config).prio_rx,
- + 				priocmd(switch_config).prio_tx,
- + 				priocmd(switch_config).prio_switch);
- + 		} else {
- + 			dev_err(priv->dev, "Invalid Arguments\n");
- + 			ret = -EFAULT;
- + 		}
- + 		break;
- + 
- + 	case CONFIG_SWITCH_PORT_STATISTICS_ENABLE:
- + 		if (portcmd(switch_config).port <= 7) {
- + 			writel(portcmd(switch_config).port,
- + 				&priv->regs->stat_port_en);
- + 			ret = 0;
- + 		} else {
- + 			dev_err(priv->dev, "Invalid Arguments\n");
- + 			ret = -EFAULT;
- + 		}
- + 		break;
- + 
- + 	case CONFIG_SWITCH_CONFIG_DUMP:
- + 		cpsw_config_dump(priv, switch_config->cmd_data.buf, 4096);
- + 		ret = copy_to_user(ifrq->ifr_data, switch_config,
- + 			sizeof(struct net_switch_config)) ?
- + 			-EFAULT : 0;
- + 		break;
- + 
- + 	case CONFIG_SWITCH_RATELIMIT:
- + 		if ((portcmd(switch_config).port <= 2) &&
- + 				(portcmd(switch_config).enable == 0))
- + 			ret = cpsw_ale_control_set(priv->ale,
- + 				portcmd(switch_config).port,
- + 				ALE_RATE_LIMIT, 0);
- + 		else if ((portcmd(switch_config).port <= 2) &&
- + 				((portcmd(switch_config).addr_type
- + 					== ADDR_TYPE_BROADCAST) ||
- + 				(portcmd(switch_config).addr_type
- + 					== ADDR_TYPE_MULTICAST)) &&
- + 				(portcmd(switch_config).limit <= 255)) {
- + 			ret = cpsw_rate_limit(priv->ale,
- + 				portcmd(switch_config).enable,
- + 				portcmd(switch_config).direction,
- + 				portcmd(switch_config).port,
- + 				portcmd(switch_config).addr_type,
- + 				portcmd(switch_config).limit);
- + 		} else {
- + 			dev_err(priv->dev, "Invalid Arguments\n");
- + 			ret = -EFAULT;
- + 		}
- + 		break;
- + 
- + 	case CONFIG_SWITCH_VID_INGRESS_CHECK:
- + 		if (portcmd(switch_config).port <= 2) {
- + 			cpsw_ale_control_set(priv->ale,
- + 				portcmd(switch_config).port,
- + 				ALE_PORT_DROP_UNTAGGED, 1);
- + 			cpsw_ale_control_set(priv->ale,
- + 				portcmd(switch_config).port,
- + 				ALE_PORT_DROP_UNKNOWN_VLAN, 1);
- + 			ret = 0;
- + 		} else {
- + 			dev_err(priv->dev, "Invalid Arguments\n");
- + 			ret = -EFAULT;
- + 		}
- + 		break;
- + 
- + 	case CONFIG_SWITCH_ADD_UNKNOWN_VLAN_INFO:
- + 		if ((portcmd(switch_config).port <= 7) &&
- + 				(portcmd(switch_config).
- + 					reg_multi_port_mask <= 7) &&
- + 				(portcmd(switch_config).
- + 					unknown_reg_multi_port_mask <= 7) &&
- + 				(portcmd(switch_config).
- + 					unknown_vlan_member <= 7)) {
- + 			cpsw_ale_control_set(priv->ale, 0,
- + 				ALE_PORT_UNTAGGED_EGRESS,
- + 				portcmd(switch_config).port);
- + 			cpsw_ale_control_set(priv->ale, 0,
- + 				ALE_PORT_UNKNOWN_REG_MCAST_FLOOD,
- + 				portcmd(switch_config).reg_multi_port_mask);
- + 			cpsw_ale_control_set(priv->ale, 0,
- + 				ALE_PORT_UNKNOWN_MCAST_FLOOD,
- + 				portcmd(switch_config).
- + 					unknown_reg_multi_port_mask);
- + 			cpsw_ale_control_set(priv->ale, 0,
- + 				ALE_PORT_UNKNOWN_VLAN_MEMBER,
- + 				portcmd(switch_config).unknown_vlan_member);
- + 			ret = 0;
- + 		} else {
- + 			dev_err(priv->dev, "Invalid Arguments\n");
- + 			ret = -EFAULT;
- + 		}
- + 		break;
- + 
- + 	case CONFIG_SWITCH_802_1:
- + 	{
- + 		char addr_802_1[6] = {0x01, 0x80, 0xc2, 0x0, 0x0, 0x03};
- + 		if (portcmd(switch_config).enable)
- + 			ret = cpsw_ale_add_mcast(priv->ale,
- + 					addr_802_1, 0x7, 0, 0);
- + 		else
- + 			ret = cpsw_ale_add_mcast(priv->ale,
- + 					addr_802_1, 0x3, 0, 0);
- + 		break;
- + 	}
- + 
- + 	case CONFIG_SWITCH_MACAUTH:
- + 		ret = cpsw_ale_control_set(priv->ale, priv->host_port,
- + 			ALE_AUTH_ENABLE, 1);
- + 		break;
- + 
- + 	case CONFIG_SWITCH_SET_PORT_CONFIG:
- + 	{
- + 		struct ethtool_cmd ecmd;
- + 
- + 		if (portcmd(switch_config).port == 1)
- + 			if (priv->slaves[0].phy) {
- + 				ecmd.phy_address = priv->slaves[0].phy->addr;
- + 				ret = phy_ethtool_gset(priv->slaves[0].phy,
- + 						&ecmd);
- + 			} else {
- + 				dev_err(priv->dev, "Phy not Found\n");
- + 				ret = -EFAULT;
- + 				break;
- + 			}
- + 		else if (portcmd(switch_config).port == 2)
- + 			if (priv->slaves[1].phy) {
- + 				ecmd.phy_address = priv->slaves[1].phy->addr;
- + 				ret = phy_ethtool_gset(priv->slaves[1].phy,
- + 						&ecmd);
- + 			} else {
- + 				dev_err(priv->dev, "Phy not Found\n");
- + 				ret = -EFAULT;
- + 				break;
- + 			}
- + 		else {
- + 			dev_err(priv->dev, "Invalid Arguments\n");
- + 			ret = -EFAULT;
- + 			break;
- + 		}
- + 
- + 		if (((portcmd(switch_config).limit == 0) ||
- + 			(portcmd(switch_config).limit == 10) ||
- + 			(portcmd(switch_config).limit == 100) ||
- + 			(portcmd(switch_config).limit == 1000))) {
- + 
- + 			if (portcmd(switch_config).limit == 0)
- + 				ecmd.autoneg = AUTONEG_ENABLE;
- + 			else {
- + 				ecmd.autoneg = AUTONEG_DISABLE;
- + 				ecmd.speed =
- + 					portcmd(switch_config).limit;
- + 				if (portcmd(switch_config).direction
- + 						== 1)
- + 					ecmd.duplex = DUPLEX_FULL;
- + 				else
- + 					ecmd.duplex = DUPLEX_HALF;
- + 			}
- + 
- + 			if (portcmd(switch_config).port == 1)
- + 				ret = phy_ethtool_sset(priv->slaves[0].phy,
- + 					&ecmd);
- + 			else
- + 				ret = phy_ethtool_sset(priv->slaves[1].phy,
- + 					&ecmd);
- + 		} else {
- + 			dev_err(priv->dev, "Invalid Arguments\n");
- + 			ret = -EFAULT;
- + 		}
- + 		break;
- + 	}
- + 
- + 	case CONFIG_SWITCH_GET_PORT_CONFIG:
- + 	{
- + 		struct ethtool_cmd ecmd;
- + 
- + 		if (portcmd(switch_config).port == 1)
- + 			if (priv->slaves[0].phy) {
- + 				ecmd.phy_address = priv->slaves[0].phy->addr;
- + 				ret = phy_ethtool_gset(priv->slaves[0].phy,
- + 						&ecmd);
- + 			} else {
- + 				dev_err(priv->dev, "Phy not Found\n");
- + 				ret = -EFAULT;
- + 				break;
- + 			}
- + 		else if (portcmd(switch_config).port == 2)
- + 			if (priv->slaves[1].phy) {
- + 				ecmd.phy_address = priv->slaves[1].phy->addr;
- + 				ret = phy_ethtool_gset(priv->slaves[1].phy,
- + 						&ecmd);
- + 			} else {
- + 				dev_err(priv->dev, "Phy not Found\n");
- + 				ret = -EFAULT;
- + 				break;
- + 			}
- + 		else {
- + 			dev_err(priv->dev, "Invalid Arguments\n");
- + 			ret = -EFAULT;
- + 			break;
- + 		}
- + 
- + 		if (!ret) {
- + 			portcmd(switch_config).limit = ecmd.speed;
- + 			if (ecmd.duplex == DUPLEX_FULL)
- + 				portcmd(switch_config).direction = 1;
- + 			else
- + 				portcmd(switch_config).direction = 0;
- + 			ret = copy_to_user(ifrq->ifr_data, switch_config,
- + 				sizeof(struct net_switch_config)) ?
- + 				-EFAULT : 0;
- + 		}
- + 
- + 		break;
- + 	}
- + 
- + 	case CONFIG_SWITCH_PORT_STATE:
- + 		if (portcmd(switch_config).port <= 2) {
- + 			ret = cpsw_set_port_state(priv,
- + 				portcmd(switch_config).port,
- + 				portcmd(switch_config).port_state);
- + 		} else {
- + 			dev_err(priv->dev, "Invalid Arguments\n");
- + 			ret = -EFAULT;
- + 		}
- + 		break;
- + 
- + 	case CONFIG_SWITCH_RESET:
- + 		ret = cpsw_ndo_stop(ndev);
- + 		if (!ret)
- + 			ret = cpsw_ndo_open(ndev);
- + 		break;
- + 
- + 	default:
- + 		ret = -EOPNOTSUPP;
- + 	}
- + 
- + 	kfree(switch_config);
- + 	return ret;
- + }
- + 
- + #else
- + #define cpsw_switch_config_ioctl(ndev, ifrq, cmd) (-EOPNOTSUPP)
- + #endif /* CONFIG_TI_CPSW_DUAL_EMAC */
- + 
- + static int cpsw_ndo_do_ioctl(struct net_device *ndev, struct ifreq *ifrq,
- + 		int cmd)
- + {
- + 	if (!(netif_running(ndev)))
- + 		return -EINVAL;
- + 
- + 	switch (cmd) {
- + 
- + 	case SIOCSWITCHCONFIG:
- + 		return cpsw_switch_config_ioctl(ndev, ifrq, cmd);
- + 
- + #ifdef CONFIG_TI_CPTS
- + 	case SIOCSHWTSTAMP:
- + 		return cpsw_hwtstamp_ioctl(ndev, ifrq);
- + #endif
- + 
- + 	default:
- + 		return -EOPNOTSUPP;
- + 	}
- + 	return 0;
- + }
- + 
- + static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
- + {
- + 	struct cpsw_priv *priv = netdev_priv(ndev);
- + 	struct sockaddr *addr = (struct sockaddr *)p;
- + 
- + 	if (!is_valid_ether_addr(addr->sa_data))
- + 		return -EADDRNOTAVAIL;
- + 
- + 	cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port);
- + 
- + 	memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
- + 	memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
- + 
- + 	cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
- + 			   0);
- + 	for_each_slave(priv, cpsw_set_slave_mac, priv);
- + 
- + 	/* save the mac address */
- + 	if(priv->save_mac_addr)
- + 		priv->save_mac_addr(priv->mac_addr);
- + 
- + 	return 0;
- + }
- + 
- + static void cpsw_ndo_tx_timeout(struct net_device *ndev)
- + {
- + 	struct cpsw_priv *priv = netdev_priv(ndev);
- + 
- + 	msg(err, tx_err, "transmit timeout, restarting dma");
- + 	priv->stats.tx_errors++;
- + 	cpsw_intr_disable(priv);
- + 	cpdma_ctlr_int_ctrl(priv->dma, false);
- + 	cpdma_chan_stop(priv->txch);
- + 	cpdma_chan_start(priv->txch);
- + 	cpdma_ctlr_int_ctrl(priv->dma, true);
- + 	cpsw_intr_enable(priv);
- + 	cpdma_ctlr_eoi(priv->dma);
- + }
- + 
- + static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev)
- + {
- + 	struct cpsw_priv *priv = netdev_priv(ndev);
- + 	return &priv->stats;
- + }
- + 
- + #ifdef CONFIG_NET_POLL_CONTROLLER
- + static void cpsw_ndo_poll_controller(struct net_device *ndev)
- + {
- + 	struct cpsw_priv *priv = netdev_priv(ndev);
- + 
- + 	cpsw_intr_disable(priv);
- + 	cpdma_ctlr_int_ctrl(priv->dma, false);
- + 	cpsw_interrupt(ndev->irq, priv);
- + 	cpdma_ctlr_int_ctrl(priv->dma, true);
- + 	cpsw_intr_enable(priv);
- + 	cpdma_ctlr_eoi(priv->dma);
- + }
- + #endif
- + 
- + /**
- +  * cpsw_get_coalesce : Get interrupt coalesce settings for this device
- +  * @ndev : CPSW network adapter
- +  * @coal : ethtool coalesce settings structure
- +  *
- +  * Fetch the current interrupt coalesce settings
- +  *
- +  */
- + static int cpsw_get_coalesce(struct net_device *ndev,
- + 				struct ethtool_coalesce *coal)
- + {
- + 	struct cpsw_priv *priv = netdev_priv(ndev);
- + 
- + 	coal->rx_coalesce_usecs = priv->coal_intvl;
- + 	return 0;
- + }
- + 
- + /**
- +  * cpsw_set_coalesce : Set interrupt coalesce settings for this device
- +  * @ndev : CPSW network adapter
- +  * @coal : ethtool coalesce settings structure
- +  *
- +  * Set interrupt coalesce parameters
- +  *
- +  */
- + static int cpsw_set_coalesce(struct net_device *ndev,
- + 				struct ethtool_coalesce *coal)
- + {
- + 	struct cpsw_priv *priv = netdev_priv(ndev);
- + 	u32 int_ctrl;
- + 	u32 num_interrupts = 0;
- + 	u32 prescale = 0;
- + 	u32 addnl_dvdr = 1;
- + 	u32 coal_intvl = 0;
- + 
- + 	if (!coal->rx_coalesce_usecs)
- + 		return -EINVAL;
- + 
- + 	coal_intvl = coal->rx_coalesce_usecs;
- + 
- + 	int_ctrl =  __raw_readl(&priv->wr_regs->int_control);
- + 	prescale = priv->bus_freq_mhz * 4;
- + 
- + 	if (coal_intvl < CPSW_CMINTMIN_INTVL)
- + 		coal_intvl = CPSW_CMINTMIN_INTVL;
- + 
- + 	if (coal_intvl > CPSW_CMINTMAX_INTVL) {
- + 		/*
- + 		 * Interrupt pacer works with 4us Pulse, we can
- + 		 * throttle further by dilating the 4us pulse.
- + 		 */
- + 		addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
- + 
- + 		if (addnl_dvdr > 1) {
- + 			prescale *= addnl_dvdr;
- + 			if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
- + 				coal_intvl = (CPSW_CMINTMAX_INTVL
- + 						* addnl_dvdr);
- + 		} else {
- + 			addnl_dvdr = 1;
- + 			coal_intvl = CPSW_CMINTMAX_INTVL;
- + 		}
- + 	}
- + 
- + 	num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
- + 
- + 	int_ctrl |= CPSW_INTPACEEN;
- + 	int_ctrl &= (~CPSW_INTPRESCALE_MASK);
- + 	int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
- + 	__raw_writel(int_ctrl, &priv->wr_regs->int_control);
- + 
- + 	__raw_writel(num_interrupts, &priv->wr_regs->rx_imax);
- + 	__raw_writel(num_interrupts, &priv->wr_regs->tx_imax);
- + 
- + 	printk(KERN_INFO"Set coalesce to %d usecs.\n", coal_intvl);
- + 	priv->coal_intvl = coal_intvl;
- + 
- + 	return 0;
- + }
- + 
- + #ifdef VLAN_SUPPORT
- + 
- + #ifdef CONFIG_TI_CPSW_DUAL_EMAC
- + 
- + static inline void cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
- + 					   unsigned short vid)
- + {
- + 	cpsw_ale_add_vlan(priv->ale, vid, 1 << priv->host_port |
- + 			1 << (priv->emac_port + 1), 0,
- + 			1 << priv->host_port | 1 << (priv->emac_port + 1), 0);
- + 	cpsw_ale_vlan_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
- + 			0, vid);
- + 	cpsw_ale_vlan_add_mcast(priv->ale, priv->ndev->broadcast,
- + 			1 << priv->host_port | 1 << (priv->emac_port + 1),
- + 			vid, 0, 0);
- + }
- + 
- + #else
- + 
- + static inline void cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
- + 				unsigned short vid)
- + {
- + 	cpsw_ale_add_vlan(priv->ale, vid, ALE_ALL_PORTS << priv->host_port,
- + 			0, ALE_ALL_PORTS << priv->host_port,
- + 			(BIT(1) | BIT(2)) << priv->host_port);
- + 	cpsw_ale_vlan_add_ucast(priv->ale, priv->mac_addr,
- + 			priv->host_port, 0, vid);
- + 	cpsw_ale_vlan_add_mcast(priv->ale, priv->ndev->broadcast,
- + 			ALE_ALL_PORTS << priv->host_port, vid, 0, 0);
- + }
- + 
- + #endif
- + 
- + static void cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
- + 		unsigned short vid)
- + {
- + 	struct cpsw_priv *priv = netdev_priv(ndev);
- + 
- + 	spin_lock(&priv->lock);
- + 
- + 	dev_dbg(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
- + 	if (vid) {
- + 		cpsw_add_vlan_ale_entry(priv, vid);
- + 	} else {
- + 		cpsw_ale_add_vlan(priv->ale, vid,
- + 				ALE_ALL_PORTS << priv->host_port,
- + 				ALE_ALL_PORTS << priv->host_port,
- + 				ALE_ALL_PORTS << priv->host_port,
- + 				(BIT(1) | BIT(2)) << priv->host_port);
- + 	}
- + 
- + 	spin_unlock(&priv->lock);
- + }
- + 
- + static void cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
- + 		unsigned short vid)
- + {
- + 	struct cpsw_priv *priv = netdev_priv(ndev);
- + 
- + 	spin_lock(&priv->lock);
- + 
- + 	dev_dbg(priv->dev, "removing vlanid %d from vlan filter\n", vid);
- + 	cpsw_ale_del_vlan(priv->ale, vid, ALE_ALL_PORTS << priv->host_port);
- + 	cpsw_ale_vlan_del_ucast(priv->ale, priv->mac_addr,
- + 				priv->host_port, vid);
- + 	cpsw_ale_vlan_del_mcast(priv->ale, priv->ndev->broadcast, 0, vid);
- + 
- + 	spin_unlock(&priv->lock);
- + }
- + 
- + #endif /* VLAN_SUPPORT */
- + 
- + static const struct net_device_ops cpsw_netdev_ops = {
- + 	.ndo_open		= cpsw_ndo_open,
- + 	.ndo_stop		= cpsw_ndo_stop,
- + 	.ndo_start_xmit		= cpsw_ndo_start_xmit,
- + 	.ndo_change_rx_flags	= cpsw_ndo_change_rx_flags,
- + 	.ndo_set_mac_address	= cpsw_ndo_set_mac_address,
- + 	.ndo_do_ioctl		= cpsw_ndo_do_ioctl,
- + 	.ndo_validate_addr	= eth_validate_addr,
- + 	.ndo_tx_timeout		= cpsw_ndo_tx_timeout,
- + 	.ndo_get_stats		= cpsw_ndo_get_stats,
- + 	.ndo_set_rx_mode	= cpsw_ndo_set_rx_mode,
- + #ifdef CONFIG_NET_POLL_CONTROLLER
- + 	.ndo_poll_controller	= cpsw_ndo_poll_controller,
- + #endif
- + #ifdef VLAN_SUPPORT
- + 	.ndo_vlan_rx_add_vid	= cpsw_ndo_vlan_rx_add_vid,
- + 	.ndo_vlan_rx_kill_vid	= cpsw_ndo_vlan_rx_kill_vid,
- + #endif
- + };
- + 
- + static void cpsw_get_drvinfo(struct net_device *ndev,
- + 			     struct ethtool_drvinfo *info)
- + {
- + 	struct cpsw_priv *priv = netdev_priv(ndev);
- + 	strcpy(info->driver, "TI CPSW Driver v1.0");
- + 	strcpy(info->version, "1.0");
- + 	strcpy(info->bus_info, priv->pdev->name);
- + }
- + 
- + static u32 cpsw_get_msglevel(struct net_device *ndev)
- + {
- + 	struct cpsw_priv *priv = netdev_priv(ndev);
- + 	return priv->msg_enable;
- + }
- + 
- + static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
- + {
- + 	struct cpsw_priv *priv = netdev_priv(ndev);
- + 	priv->msg_enable = value;
- + }
- + 
- + /**
- +  * cpsw_get_settings: Get EMAC settings
- +  * @ndev: CPSW network adapter
- +  * @ecmd: ethtool command
- +  *
- +  * Executes ethool get command
- +  *
- +  */
- + static int cpsw_get_settings(struct net_device *ndev,
- + 			     struct ethtool_cmd *ecmd)
- + {
- + 	struct cpsw_priv *priv = netdev_priv(ndev);
- + 	int slave_no = cpsw_slave_phy_index(priv);
- + 
- + 	if (priv->slaves[slave_no].phy)
- + 		return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
- + 	else
- + 		return -EOPNOTSUPP;
- + }
- + 
- + /**
- +  * cpsw_set_settings: Set EMAC settings
- +  * @ndev: CPSW network adapter
- +  * @ecmd: ethtool command
- +  *
- +  * Executes ethool set command
- +  *
- +  */
- + static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
- + {
- + 	struct cpsw_priv *priv = netdev_priv(ndev);
- + 	int slave_no = cpsw_slave_phy_index(priv);
- + 
- + 	if (priv->slaves[slave_no].phy)
- + 		return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
- + 	else
- + 		return -EOPNOTSUPP;
- + }
- + 
- + static const struct ethtool_ops cpsw_ethtool_ops = {
- + 	.get_drvinfo	= cpsw_get_drvinfo,
- + 	.get_msglevel	= cpsw_get_msglevel,
- + 	.set_msglevel	= cpsw_set_msglevel,
- + 	.get_link	= ethtool_op_get_link,
- + 	.get_settings	= cpsw_get_settings,
- + 	.set_settings	= cpsw_set_settings,
- + 	.get_coalesce	= cpsw_get_coalesce,
- + 	.set_coalesce	= cpsw_set_coalesce,
- + };
- + 
- + static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv)
- + {
- + 	void __iomem		*regs = priv->regs;
- + 	int			slave_num = slave->slave_num;
- + 	struct cpsw_slave_data	*data = priv->data.slave_data + slave_num;
- + 
- + 	slave->data	= data;
- + 	slave->regs	= regs + data->slave_reg_ofs;
- + 	slave->sliver	= regs + data->sliver_reg_ofs;
- + 	slave->port_vlan = data->dual_emac_reserved_vlan;
- + }
- + 
- + #ifdef CONFIG_TI_CPSW_DUAL_EMAC
- + 
- + static int cpsw_init_slave_emac(struct platform_device *pdev,
- + 				struct cpsw_priv *priv)
- + {
- + 	struct cpsw_platform_data	*data = pdev->dev.platform_data;
- + 	struct net_device		*ndev;
- + 	struct cpsw_priv		*priv_sl2;
- + 	int ret = 0, i;
- + 
- + 	ndev = alloc_etherdev(sizeof(struct cpsw_priv));
- + 	if (!ndev) {
- + 		pr_err("cpsw: error allocating net_device\n");
- + 		return -ENOMEM;
- + 	}
- + 
- + 	priv_sl2 = netdev_priv(ndev);
- + 	spin_lock_init(&priv_sl2->lock);
- + 	priv_sl2->data = *data;
- + 	priv_sl2->pdev = pdev;
- + 	priv_sl2->ndev = ndev;
- + 	priv_sl2->dev  = &ndev->dev;
- + 	priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
- + 	priv_sl2->rx_packet_max = max(rx_packet_max, 128);
- + 
- + 	if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
- + 		memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
- + 			ETH_ALEN);
- + 		pr_info("cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
- + 	} else {
- + 		random_ether_addr(priv_sl2->mac_addr);
- + 		pr_info("cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
- + 	}
- + 	memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
- + 
- + 	priv_sl2->slaves = priv->slaves;
- + 	priv_sl2->clk = priv->clk;
- + 
- + 	priv_sl2->coal_intvl = 0;
- + 	priv_sl2->bus_freq_mhz = clk_get_rate(priv_sl2->clk) / 1000000;
- + 
- + 	priv_sl2->cpsw_res = priv->cpsw_res;
- + 	priv_sl2->regs = priv->regs;
- + 	priv_sl2->host_port = priv->host_port;
- + 	priv_sl2->host_port_regs = priv->host_port_regs;
- + 	priv_sl2->hw_stats = priv->hw_stats;
- + 	priv_sl2->cpsw_ss_res = priv->cpsw_ss_res;
- + 	priv_sl2->wr_regs = priv->wr_regs;
- + 	priv_sl2->dma = priv->dma;
- + 	priv_sl2->txch = priv->txch;
- + 	priv_sl2->rxch = priv->rxch;
- + 	priv_sl2->ale = priv->ale;
- + 	priv_sl2->emac_port = 1;
- + 	priv->slaves[1].ndev = ndev;
- + 	priv_sl2->cpts = priv->cpts;
- + 	for_each_slave(priv_sl2, cpsw_slave_init, priv_sl2);
- + 
- + 	for (i = 0; i < priv->num_irqs; i++) {
- + 		priv_sl2->irqs_table[i] = priv->irqs_table[i];
- + 		priv_sl2->num_irqs = priv->num_irqs;
- + 	}
- + 
- + #ifdef VLAN_SUPPORT
- + 	ndev->features |= NETIF_F_HW_VLAN_FILTER;
- + #endif
- + 
- + 	ndev->flags |= IFF_ALLMULTI;	/* see cpsw_ndo_change_rx_flags() */
- + 
- + 	ndev->netdev_ops = &cpsw_netdev_ops;
- + 	SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops);
- + 	netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT);
- + 
- + 	/* register the network device */
- + 	SET_NETDEV_DEV(ndev, &pdev->dev);
- + 	ret = register_netdev(ndev);
- + 	if (ret) {
- + 		pr_err("cpsw: error registering net device\n");
- + 		ret = -ENODEV;
- + 	}
- + 
- + 	return ret;
- + }
- + 
- + static inline void cpsw_deinit_slave_emac(struct cpsw_priv *priv)
- + {
- + 	struct net_device *ndev = priv->slaves[1].ndev;
- + 
- + 	unregister_netdev(ndev);
- + 	free_netdev(ndev);
- + }
- + 
- + #else
- + #define cpsw_init_slave_emac(pdev, priv)	0
- + #define cpsw_deinit_slave_emac(priv)
- + #endif
- + 
- + static int __devinit cpsw_probe(struct platform_device *pdev)
- + {
- + 	struct cpsw_platform_data	*data = pdev->dev.platform_data;
- + 	struct net_device		*ndev;
- + 	struct cpsw_priv		*priv;
- + 	struct cpdma_params		dma_params;
- + 	struct cpsw_ale_params		ale_params;
- + 	void __iomem			*regs;
- + 	int ret = 0, i, k = 0;
- + 
- + 	if (!data) {
- + 		pr_err("cpsw: platform data missing\n");
- + 		return -ENODEV;
- + 	}
- + 
- + 	ndev = alloc_etherdev(sizeof(struct cpsw_priv));
- + 	if (!ndev) {
- + 		pr_err("cpsw: error allocating net_device\n");
- + 		return -ENOMEM;
- + 	}
- + 
- + 	platform_set_drvdata(pdev, ndev);
- + 	priv = netdev_priv(ndev);
- + 	spin_lock_init(&priv->lock);
- + 	priv->data = *data;
- + 	priv->pdev = pdev;
- + 	priv->ndev = ndev;
- + 	priv->dev  = &ndev->dev;
- + 	priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
- + 	priv->rx_packet_max = max(rx_packet_max, 128);
- + 	priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
- + 
- + 	if (is_valid_ether_addr(data->mac_addr)) {
- + 		memcpy(priv->mac_addr, data->mac_addr, ETH_ALEN);
- + 		printk(KERN_INFO"Detected MACID=%x:%x:%x:%x:%x:%x\n",
- + 			priv->mac_addr[0], priv->mac_addr[1],
- + 			priv->mac_addr[2], priv->mac_addr[3],
- + 			priv->mac_addr[4], priv->mac_addr[5]);
- + 	} else {
- + 		random_ether_addr(priv->mac_addr);
- + 		printk(KERN_INFO"Random MACID=%x:%x:%x:%x:%x:%x\n",
- + 			priv->mac_addr[0], priv->mac_addr[1],
- + 			priv->mac_addr[2], priv->mac_addr[3],
- + 			priv->mac_addr[4], priv->mac_addr[5]);
- + 	}
- + 
- + 	memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
- + 
- + 	priv->slaves = kzalloc(sizeof(struct cpsw_slave) * data->slaves,
- + 			       GFP_KERNEL);
- + 	if (!priv->slaves) {
- + 		dev_err(priv->dev, "failed to allocate slave ports\n");
- + 		ret = -EBUSY;
- + 		goto clean_ndev_ret;
- + 	}
- + 	for (i = 0; i < data->slaves; i++)
- + 		priv->slaves[i].slave_num = i;
- + 
- + 	priv->slaves[0].ndev = ndev;
- + 	priv->emac_port = 0;
- + 
- + 	pm_runtime_enable(&pdev->dev);
- + 	pm_runtime_get_sync(&pdev->dev);
- + 	priv->clk = clk_get(&pdev->dev, "fck");
- + 	if (IS_ERR(priv->clk)) {
- + 		dev_err(&pdev->dev, "fck is not found\n");
- + 		ret = -ENODEV;
- + 		goto clean_slave_ret;
- + 	}
- + 
- + 	priv->coal_intvl = 0;
- + 	priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
- + 
- + 	priv->cpsw_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- + 	if (!priv->cpsw_res) {
- + 		dev_err(priv->dev, "error getting i/o resource\n");
- + 		ret = -ENOENT;
- + 		goto clean_clk_ret;
- + 	}
- + 
- + 	if (!request_mem_region(priv->cpsw_res->start,
- + 		resource_size(priv->cpsw_res), ndev->name)) {
- + 		dev_err(priv->dev, "failed request i/o region\n");
- + 		ret = -ENXIO;
- + 		goto clean_clk_ret;
- + 	}
- + 
- + 	regs = ioremap(priv->cpsw_res->start, resource_size(priv->cpsw_res));
- + 	if (!regs) {
- + 		dev_err(priv->dev, "unable to map i/o region\n");
- + 		goto clean_cpsw_iores_ret;
- + 	}
- + 	priv->regs = regs;
- + 	priv->host_port = data->host_port_num;
- + 	priv->host_port_regs = regs + data->host_port_reg_ofs;
- + 	priv->hw_stats = regs + data->hw_stats_reg_ofs;
- + 	priv->cpts->reg = regs + data->cpts_reg_ofs;
- + 	priv->save_mac_addr = data->save_mac_addr;
- + 
- + 	priv->cpsw_ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- + 	if (!priv->cpsw_ss_res) {
- + 		dev_err(priv->dev, "error getting i/o resource\n");
- + 		ret = -ENOENT;
- + 		goto clean_clk_ret;
- + 	}
- + 
- + 	if (!request_mem_region(priv->cpsw_ss_res->start,
- + 		resource_size(priv->cpsw_ss_res), ndev->name)) {
- + 		dev_err(priv->dev, "failed request i/o region\n");
- + 		ret = -ENXIO;
- + 		goto clean_clk_ret;
- + 	}
- + 
- + 	regs = ioremap(priv->cpsw_ss_res->start,
- + 			resource_size(priv->cpsw_ss_res));
- + 	if (!regs) {
- + 		dev_err(priv->dev, "unable to map i/o region\n");
- + 		goto clean_cpsw_ss_iores_ret;
- + 	}
- + 	priv->wr_regs = regs;
- + 
- + 	for_each_slave(priv, cpsw_slave_init, priv);
- + 
- + 	omap_ctrl_writel(CPSW_TIMER_MASK, CPSW_TIMER_CAP_REG);
- + 
- + 	dmtimer_rx = omap_dm_timer_request_specific(CPSW_RX_TIMER_REQ);
- + 	if (!dmtimer_rx) {
- + 		dev_err(priv->dev, "Error getting Rx Timer resource\n");
- + 		ret = -ENODEV;
- + 		goto clean_iomap_ret;
- + 	}
- + 	dmtimer_tx = omap_dm_timer_request_specific(CPSW_TX_TIMER_REQ);
- + 	if (!dmtimer_tx) {
- + 		dev_err(priv->dev, "Error getting Tx Timer resource\n");
- + 		ret = -ENODEV;
- + 		goto clean_timer_rx_ret;
- + 	}
- + 
- + 	memset(&dma_params, 0, sizeof(dma_params));
- + 	dma_params.dev			= &pdev->dev;
- + 	dma_params.dmaregs		= (void __iomem *)(((u32)priv->regs) +
- + 						data->cpdma_reg_ofs);
- + 	dma_params.rxthresh		= (void __iomem *)(((u32)priv->regs) +
- + 					data->cpdma_reg_ofs + CPDMA_RXTHRESH);
- + 	dma_params.rxfree		= (void __iomem *)(((u32)priv->regs) +
- + 					data->cpdma_reg_ofs + CPDMA_RXFREE);
- + 
- + 	if (data->version == CPSW_VERSION_2) {
- + 		dma_params.txhdp	= (void __iomem *)(((u32)priv->regs) +
- + 					data->cpdma_reg_ofs + CPDMA_TXHDP_VER2);
- + 		dma_params.rxhdp	= (void __iomem *)(((u32)priv->regs) +
- + 					data->cpdma_reg_ofs + CPDMA_RXHDP_VER2);
- + 		dma_params.txcp		= (void __iomem *)(((u32)priv->regs) +
- + 					data->cpdma_reg_ofs + CPDMA_TXCP_VER2);
- + 		dma_params.rxcp		= (void __iomem *)(((u32)priv->regs) +
- + 					data->cpdma_reg_ofs + CPDMA_RXCP_VER2);
- + 	} else {
- + 		dma_params.txhdp	= (void __iomem *)(((u32)priv->regs) +
- + 					data->cpdma_reg_ofs + CPDMA_TXHDP_VER1);
- + 		dma_params.rxhdp	= (void __iomem *)(((u32)priv->regs) +
- + 					data->cpdma_reg_ofs + CPDMA_RXHDP_VER1);
- + 		dma_params.txcp		= (void __iomem *)(((u32)priv->regs) +
- + 					data->cpdma_reg_ofs + CPDMA_TXCP_VER1);
- + 		dma_params.rxcp		= (void __iomem *)(((u32)priv->regs) +
- + 					data->cpdma_reg_ofs + CPDMA_RXCP_VER1);
- + 	}
- + 
- + 	dma_params.num_chan		= data->channels;
- + 	dma_params.has_soft_reset	= true;
- + 	dma_params.min_packet_size	= CPSW_MIN_PACKET_SIZE;
- + 	dma_params.desc_mem_size	= data->bd_ram_size;
- + 	dma_params.desc_align		= 16;
- + 	dma_params.has_ext_regs		= true;
- + 	dma_params.desc_mem_phys	= data->no_bd_ram ? 0 :
- + 			(u32 __force)priv->cpsw_res->start + data->bd_ram_ofs;
- + 	dma_params.desc_hw_addr		= data->hw_ram_addr ?
- + 				data->hw_ram_addr : dma_params.desc_mem_phys ;
- + 
- + 	priv->dma = cpdma_ctlr_create(&dma_params);
- + 	if (!priv->dma) {
- + 		dev_err(priv->dev, "error initializing dma\n");
- + 		ret = -ENOMEM;
- + 		goto clean_timer_ret;
- + 	}
- + 
- + 	priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
- + 				       cpsw_tx_handler);
- + 	priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
- + 				       cpsw_rx_handler);
- + 
- + 	if (WARN_ON(!priv->txch || !priv->rxch)) {
- + 		dev_err(priv->dev, "error initializing dma channels\n");
- + 		ret = -ENOMEM;
- + 		goto clean_dma_ret;
- + 	}
- + 
- + 	memset(&ale_params, 0, sizeof(ale_params));
- + 	ale_params.dev		= &ndev->dev;
- + 	ale_params.ale_regs	= (void *)((u32)priv->regs) +
- + 					((u32)data->ale_reg_ofs);
- + 	ale_params.ale_ageout	= ale_ageout;
- + 	ale_params.ale_entries	= data->ale_entries;
- + 	ale_params.ale_ports	= data->slaves;
- + 
- + 	priv->ale = cpsw_ale_create(&ale_params);
- + 	if (!priv->ale) {
- + 		dev_err(priv->dev, "error initializing ale engine\n");
- + 		ret = -ENODEV;
- + 		goto clean_dma_ret;
- + 	}
- + 
- + 	while ((i = platform_get_irq(pdev, k)) >= 0) {
- + 		if (request_irq(i, cpsw_interrupt, IRQF_DISABLED,
- + 				dev_name(&pdev->dev), priv)) {
- + 			dev_err(priv->dev, "error attaching irq\n");
- + 			goto clean_ale_ret;
- + 		}
- + 		priv->irqs_table[k] = i;
- + 		priv->num_irqs = ++k;
- + 	}
- + 
- + #ifdef VLAN_SUPPORT
- + 	ndev->features |= NETIF_F_HW_VLAN_FILTER;
- + #endif
- + 
- + 	ndev->flags |= IFF_ALLMULTI;	/* see cpsw_ndo_change_rx_flags() */
- + 
- + 	ndev->netdev_ops = &cpsw_netdev_ops;
- + 	SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops);
- + 	netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);
- + 
- + 	/* register the network device */
- + 	SET_NETDEV_DEV(ndev, &pdev->dev);
- + 	ret = register_netdev(ndev);
- + 	if (ret) {
- + 		dev_err(priv->dev, "error registering net device\n");
- + 		ret = -ENODEV;
- + 		goto clean_irq_ret;
- + 	}
- + 
- + 	msg(notice, probe, "initialized device (regs %x, irq %d)\n",
- + 	    priv->cpsw_res->start, ndev->irq);
- + 
- + 	ret = cpsw_init_slave_emac(pdev, priv);
- + 	if (ret) {
- + 		dev_err(priv->dev, "error probe slave 2 emac interface\n");
- + 		goto clean_irq_ret;
- + 	}
- + 
- + 	return 0;
- + 
- + clean_irq_ret:
- + 	free_irq(ndev->irq, priv);
- + clean_ale_ret:
- + 	cpsw_ale_destroy(priv->ale);
- + clean_dma_ret:
- + 	cpdma_chan_destroy(priv->txch);
- + 	cpdma_chan_destroy(priv->rxch);
- + 	cpdma_ctlr_destroy(priv->dma);
- + clean_timer_ret:
- + 	omap_dm_timer_free(dmtimer_tx);
- + clean_timer_rx_ret:
- + 	omap_dm_timer_free(dmtimer_rx);
- + clean_iomap_ret:
- + 	iounmap(priv->regs);
- + clean_cpsw_ss_iores_ret:
- + 	release_mem_region(priv->cpsw_ss_res->start,
- + 				resource_size(priv->cpsw_ss_res));
- + clean_cpsw_iores_ret:
- + 	release_mem_region(priv->cpsw_res->start,
- + 				resource_size(priv->cpsw_res));
- + clean_clk_ret:
- + 	clk_put(priv->clk);
- + clean_slave_ret:
- + 	pm_runtime_get_sync(&pdev->dev);
- + 	pm_runtime_disable(&pdev->dev);
- + 	kfree(priv->slaves);
- + clean_ndev_ret:
- + 	free_netdev(ndev);
- + 	return ret;
- + }
- + 
- + static int __devexit cpsw_remove(struct platform_device *pdev)
- + {
- + 	struct net_device *ndev = platform_get_drvdata(pdev);
- + 	struct cpsw_priv *priv = netdev_priv(ndev);
- + 	u32 i;
- + 
- + 	msg(notice, probe, "removing device\n");
- + 	platform_set_drvdata(pdev, NULL);
- + 
- + 	cpsw_deinit_slave_emac(priv);
- + 	omap_dm_timer_free(dmtimer_rx);
- + 	omap_dm_timer_free(dmtimer_tx);
- + 	for (i = 0; i < priv->num_irqs; i++)
- + 		free_irq(priv->irqs_table[i], priv);
- + 	cpsw_ale_destroy(priv->ale);
- + 	cpdma_chan_destroy(priv->txch);
- + 	cpdma_chan_destroy(priv->rxch);
- + 	cpdma_ctlr_destroy(priv->dma);
- + 	iounmap(priv->regs);
- + 	release_mem_region(priv->cpsw_res->start,
- + 				resource_size(priv->cpsw_res));
- + 	release_mem_region(priv->cpsw_ss_res->start,
- + 				resource_size(priv->cpsw_ss_res));
- + 	pm_runtime_put_sync(&pdev->dev);
- + 	pm_runtime_disable(&pdev->dev);
- + 	clk_put(priv->clk);
- + 	kfree(priv->slaves);
- + 	unregister_netdev(ndev);
- + 	free_netdev(ndev);
- + 
- + 	return 0;
- + }
- + 
- + #ifdef CONFIG_TI_CPSW_DUAL_EMAC
- + 
- + static inline void cpsw_start_slaves_interface(struct net_device *ndev)
- + {
- + 	struct cpsw_priv *priv = netdev_priv(ndev);
- + 	u32 i = 0;
- + 
- + 	for (i = 0; i < priv->data.slaves; i++) {
- + 		ndev = cpsw_get_slave_ndev(priv, i);
- + 		if (netif_running(ndev))
- + 			cpsw_ndo_open(ndev);
- + 	}
- + }
- + 
- + static inline void cpsw_stop_slaves_interface(struct net_device *ndev)
- + {
- + 	u32 i = 0;
- + 	struct cpsw_priv *priv = netdev_priv(ndev);
- + 
- + 	for (i = 0; i < priv->data.slaves; i++) {
- + 		ndev = cpsw_get_slave_ndev(priv, i);
- + 		if (netif_running(ndev))
- + 			cpsw_ndo_stop(ndev);
- + 	}
- + }
- + 
- + #else
- + 
- + #define cpsw_start_slaves_interface(ndev)		\
- + 	if (netif_running(ndev))			\
- + 		cpsw_ndo_open(ndev)
- + #define cpsw_stop_slaves_interface(ndev)		\
- + 	if (netif_running(ndev))			\
- + 		cpsw_ndo_stop(ndev)
- + 
- + #endif
- + 
- + static int cpsw_suspend(struct device *dev)
- + {
- + 	struct platform_device	*pdev = to_platform_device(dev);
- + 	struct net_device	*ndev = platform_get_drvdata(pdev);
- + 
- + 	cpsw_stop_slaves_interface(ndev);
- + 	pm_runtime_put_sync(&pdev->dev);
- + 
- + 	return 0;
- + }
- + 
- + static int cpsw_resume(struct device *dev)
- + {
- + 	struct platform_device	*pdev = to_platform_device(dev);
- + 	struct net_device	*ndev = platform_get_drvdata(pdev);
- + 
- + 	pm_runtime_get_sync(&pdev->dev);
- + 	cpsw_start_slaves_interface(ndev);
- + 
- + 	return 0;
- + }
- + 
- + static const struct dev_pm_ops cpsw_pm_ops = {
- + 	.suspend	= cpsw_suspend,
- + 	.resume		= cpsw_resume,
- + };
- + 
- + static struct platform_driver cpsw_driver = {
- + 	.driver = {
- + 		.name	 = "cpsw",
- + 		.owner	 = THIS_MODULE,
- + 		.pm	 = &cpsw_pm_ops,
- + 	},
- + 	.probe = cpsw_probe,
- + 	.remove = __devexit_p(cpsw_remove),
- + };
- + 
- + static int __init cpsw_init(void)
- + {
- + 	return platform_driver_register(&cpsw_driver);
- + }
- + late_initcall(cpsw_init);
- + 
- + static void __exit cpsw_exit(void)
- + {
- + 	platform_driver_unregister(&cpsw_driver);
- + }
- + module_exit(cpsw_exit);
- + 
- + MODULE_LICENSE("GPL");
- + MODULE_DESCRIPTION("TI CPSW Ethernet driver");
- diff -crN linux-3.2.1_o/drivers/net/ethernet/ti/cpts.c linux-3.2.1/drivers/net/ethernet/ti/cpts.c
- *** linux-3.2.1_o/drivers/net/ethernet/ti/cpts.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/drivers/net/ethernet/ti/cpts.c	2014-05-15 13:25:14.591233781 +0900
- ***************
- *** 0 ****
- --- 1,425 ----
- + /*
- +  * TI Common Platform Time Sync
- +  *
- +  * Copyright (C) 2012 Richard Cochran <richardcochran@gmail.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; either version 2 of the License, or
- +  * (at your option) any later version.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- +  */
- + #include <linux/err.h>
- + #include <linux/if.h>
- + #include <linux/hrtimer.h>
- + #include <linux/module.h>
- + #include <linux/net_tstamp.h>
- + #include <linux/ptp_classify.h>
- + #include <linux/time.h>
- + #include <linux/uaccess.h>
- + #include <linux/workqueue.h>
- + 
- + #include <plat/clock.h>
- + 
- + #include "cpts.h"
- + 
- + #ifdef CONFIG_TI_CPTS
- + 
- + static struct sock_filter ptp_filter[] = {
- + 	PTP_FILTER
- + };
- + 
- + #define cpts_read32(c, r)	__raw_readl(&c->reg->r)
- + #define cpts_write32(c, v, r)	__raw_writel(v, &c->reg->r)
- + 
- + static int event_expired(struct cpts_event *event)
- + {
- + 	return time_after(jiffies, event->tmo);
- + }
- + 
- + static int event_type(struct cpts_event *event)
- + {
- + 	return (event->high >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
- + }
- + 
- + static int cpts_fifo_pop(struct cpts *cpts, u32 *high, u32 *low)
- + {
- + 	u32 r = cpts_read32(cpts, intstat_raw);
- + 
- + 	if (r & TS_PEND_RAW) {
- + 		*high = cpts_read32(cpts, event_high);
- + 		*low  = cpts_read32(cpts, event_low);
- + 		cpts_write32(cpts, EVENT_POP, event_pop);
- + 		return 0;
- + 	}
- + 	return -1;
- + }
- + 
- + /*
- +  * Returns zero if matching event type was found.
- +  */
- + static int cpts_fifo_read(struct cpts *cpts, int match)
- + {
- + 	int i, type = -1;
- + 	u32 hi, lo;
- + 	struct cpts_event *event;
- + 
- + 	for (i = 0; i < CPTS_FIFO_DEPTH; i++) {
- + 		if (cpts_fifo_pop(cpts, &hi, &lo))
- + 			break;
- + 		if (list_empty(&cpts->pool)) {
- + 			pr_err("cpts: event pool is empty\n");
- + 			return -1;
- + 		}
- + 		event = list_first_entry(&cpts->pool, struct cpts_event, list);
- + 		event->tmo = jiffies + 2;
- + 		event->high = hi;
- + 		event->low = lo;
- + 		type = event_type(event);
- + 		switch (type) {
- + 		case CPTS_EV_PUSH:
- + 		case CPTS_EV_RX:
- + 		case CPTS_EV_TX:
- + 			list_del_init(&event->list);
- + 			list_add_tail(&event->list, &cpts->events);
- + 			break;
- + 		case CPTS_EV_ROLL:
- + 		case CPTS_EV_HALF:
- + 		case CPTS_EV_HW:
- + 			break;
- + 		default:
- + 			pr_err("cpts: unkown event type\n");
- + 			break;
- + 		}
- + 		if (type == match)
- + 			break;
- + 	}
- + 	return type == match ? 0 : -1;
- + }
- + 
- + static cycle_t cpts_systim_read(const struct cyclecounter *cc)
- + {
- + 	u64 val = 0;
- + 	struct cpts_event *event;
- + 	struct list_head *this, *next;
- + 	struct cpts *cpts = container_of(cc, struct cpts, cc);
- + 
- + 	cpts_write32(cpts, TS_PUSH, ts_push);
- + 	if (cpts_fifo_read(cpts, CPTS_EV_PUSH))
- + 		pr_err("cpts: unable to obtain a time stamp\n");
- + 
- + 	list_for_each_safe(this, next, &cpts->events) {
- + 		event = list_entry(this, struct cpts_event, list);
- + 		if (event_type(event) == CPTS_EV_PUSH) {
- + 			list_del_init(&event->list);
- + 			list_add(&event->list, &cpts->pool);
- + 			val = event->low;
- + 			break;
- + 		}
- + 	}
- + 
- + 	return val;
- + }
- + 
- + /* PTP clock operations */
- + 
- + static int cpts_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
- + {
- + 	u64 adj;
- + 	u32 diff, mult;
- + 	int neg_adj = 0;
- + 	unsigned long flags;
- + 	struct cpts *cpts = container_of(ptp, struct cpts, info);
- + 
- + 	if (ppb < 0) {
- + 		neg_adj = 1;
- + 		ppb = -ppb;
- + 	}
- + 	mult = cpts->cc_mult;
- + 	adj = mult;
- + 	adj *= ppb;
- + 	diff = div_u64(adj, 1000000000ULL);
- + 
- + 	spin_lock_irqsave(&cpts->lock, flags);
- + 
- + 	timecounter_read(&cpts->tc);
- + 
- + 	cpts->cc.mult = neg_adj ? mult - diff : mult + diff;
- + 
- + 	spin_unlock_irqrestore(&cpts->lock, flags);
- + 
- + 	return 0;
- + }
- + 
- + static int cpts_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
- + {
- + 	s64 now;
- + 	unsigned long flags;
- + 	struct cpts *cpts = container_of(ptp, struct cpts, info);
- + 
- + 	spin_lock_irqsave(&cpts->lock, flags);
- + 	now = timecounter_read(&cpts->tc);
- + 	now += delta;
- + 	timecounter_init(&cpts->tc, &cpts->cc, now);
- + 	spin_unlock_irqrestore(&cpts->lock, flags);
- + 
- + 	return 0;
- + }
- + 
- + static int cpts_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
- + {
- + 	u64 ns;
- + 	u32 remainder;
- + 	unsigned long flags;
- + 	struct cpts *cpts = container_of(ptp, struct cpts, info);
- + 
- + 	spin_lock_irqsave(&cpts->lock, flags);
- + 	ns = timecounter_read(&cpts->tc);
- + 	spin_unlock_irqrestore(&cpts->lock, flags);
- + 
- + 	ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
- + 	ts->tv_nsec = remainder;
- + 
- + 	return 0;
- + }
- + 
- + static int cpts_ptp_settime(struct ptp_clock_info *ptp,
- + 			    const struct timespec *ts)
- + {
- + 	u64 ns;
- + 	unsigned long flags;
- + 	struct cpts *cpts = container_of(ptp, struct cpts, info);
- + 
- + 	ns = ts->tv_sec * 1000000000ULL;
- + 	ns += ts->tv_nsec;
- + 
- + 	spin_lock_irqsave(&cpts->lock, flags);
- + 	timecounter_init(&cpts->tc, &cpts->cc, ns);
- + 	spin_unlock_irqrestore(&cpts->lock, flags);
- + 
- + 	return 0;
- + }
- + 
- + static int cpts_ptp_enable(struct ptp_clock_info *ptp,
- + 			   struct ptp_clock_request *rq, int on)
- + {
- + 	return -EOPNOTSUPP;
- + }
- + 
- + static struct ptp_clock_info cpts_info = {
- + 	.owner		= THIS_MODULE,
- + 	.name		= "CTPS timer",
- + 	.max_adj	= 1000000,
- + 	.n_ext_ts	= 0,
- + 	.pps		= 0,
- + 	.adjfreq	= cpts_ptp_adjfreq,
- + 	.adjtime	= cpts_ptp_adjtime,
- + 	.gettime	= cpts_ptp_gettime,
- + 	.settime	= cpts_ptp_settime,
- + 	.enable		= cpts_ptp_enable,
- + };
- + 
- + static void cpts_overflow_check(struct work_struct *work)
- + {
- + 	struct timespec ts;
- + 	struct cpts *cpts = container_of(work, struct cpts, overflow_work.work);
- + 
- + 	cpts_write32(cpts, CPTS_EN, control);
- + 	cpts_write32(cpts, TS_PEND_EN, int_enable);
- + 	cpts_ptp_gettime(&cpts->info, &ts);
- + 	pr_debug("cpts overflow check at %ld.%09lu\n", ts.tv_sec, ts.tv_nsec);
- + 	schedule_delayed_work(&cpts->overflow_work, CPTS_OVERFLOW_PERIOD);
- + }
- + 
- + #define CPTS_REF_CLOCK_NAME "cpsw_cpts_rft_clk"
- + 
- + static void cpts_clk_init(struct cpts *cpts)
- + {
- + 	cpts->refclk = clk_get(NULL, CPTS_REF_CLOCK_NAME);
- + 	if (IS_ERR(cpts->refclk)) {
- + 		pr_err("Failed to clk_get %s\n", CPTS_REF_CLOCK_NAME);
- + 		cpts->refclk = NULL;
- + 		return;
- + 	}
- + 	clk_enable(cpts->refclk);
- + 	cpts->freq = cpts->refclk->recalc(cpts->refclk);
- + }
- + 
- + static void cpts_clk_release(struct cpts *cpts)
- + {
- + 	clk_disable(cpts->refclk);
- + 	clk_put(cpts->refclk);
- + }
- + 
- + static int cpts_match(struct sk_buff *skb, unsigned int ptp_class,
- + 		      u16 ts_seqid, u8 ts_msgtype)
- + {
- + 	u16 *seqid;
- + 	unsigned int offset;
- + 	u8 *msgtype, *data = skb->data;
- + 
- + 	switch (ptp_class) {
- + 	case PTP_CLASS_V1_IPV4:
- + 	case PTP_CLASS_V2_IPV4:
- + 		offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
- + 		break;
- + 	case PTP_CLASS_V1_IPV6:
- + 	case PTP_CLASS_V2_IPV6:
- + 		offset = OFF_PTP6;
- + 		break;
- + 	case PTP_CLASS_V2_L2:
- + 		offset = ETH_HLEN;
- + 		break;
- + 	case PTP_CLASS_V2_VLAN:
- + 		offset = ETH_HLEN + VLAN_HLEN;
- + 		break;
- + 	default:
- + 		return 0;
- + 	}
- + 
- + 	if (skb->len + ETH_HLEN < offset + OFF_PTP_SEQUENCE_ID + sizeof(*seqid))
- + 		return 0;
- + 
- + 	if (unlikely(ptp_class & PTP_CLASS_V1))
- + 		msgtype = data + offset + OFF_PTP_CONTROL;
- + 	else
- + 		msgtype = data + offset;
- + 
- + 	seqid = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
- + 
- + 	return (ts_msgtype == (*msgtype & 0xf) && ts_seqid == ntohs(*seqid));
- + }
- + 
- + static u64 cpts_find_ts(struct cpts *cpts, struct sk_buff *skb, int ev_type)
- + {
- + 	u64 ns = 0;
- + 	struct cpts_event *event;
- + 	struct list_head *this, *next;
- + 	unsigned int class = sk_run_filter(skb, ptp_filter);
- + 	unsigned long flags;
- + 	u16 seqid;
- + 	u8 mtype;
- + 
- + 	if (class == PTP_CLASS_NONE)
- + 		return 0;
- + 
- + 	spin_lock_irqsave(&cpts->lock, flags);
- + 	cpts_fifo_read(cpts, CPTS_EV_PUSH);
- + 	list_for_each_safe(this, next, &cpts->events) {
- + 		event = list_entry(this, struct cpts_event, list);
- + 		if (event_expired(event)) {
- + 			list_del_init(&event->list);
- + 			list_add(&event->list, &cpts->pool);
- + 			continue;
- + 		}
- + 		mtype = (event->high >> MESSAGE_TYPE_SHIFT) & MESSAGE_TYPE_MASK;
- + 		seqid = (event->high >> SEQUENCE_ID_SHIFT) & SEQUENCE_ID_MASK;
- + 		if (ev_type == event_type(event) &&
- + 		    cpts_match(skb, class, seqid, mtype)) {
- + 			ns = timecounter_cyc2time(&cpts->tc, event->low);
- + 			list_del_init(&event->list);
- + 			list_add(&event->list, &cpts->pool);
- + 			break;
- + 		}
- + 	}
- + 	spin_unlock_irqrestore(&cpts->lock, flags);
- + 
- + 	return ns;
- + }
- + 
- + void cpts_rx_timestamp(struct cpts *cpts, struct sk_buff *skb)
- + {
- + 	u64 ns;
- + 	struct skb_shared_hwtstamps *ssh;
- + 
- + 	if (!cpts->rx_enable)
- + 		return;
- + 	ns = cpts_find_ts(cpts, skb, CPTS_EV_RX);
- + 	if (!ns)
- + 		return;
- + 	ssh = skb_hwtstamps(skb);
- + 	memset(ssh, 0, sizeof(*ssh));
- + 	ssh->hwtstamp = ns_to_ktime(ns);
- + }
- + 
- + void cpts_tx_timestamp(struct cpts *cpts, struct sk_buff *skb)
- + {
- + 	u64 ns;
- + 	struct skb_shared_hwtstamps ssh;
- + 
- + 	if (!(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
- + 		return;
- + 	ns = cpts_find_ts(cpts, skb, CPTS_EV_TX);
- + 	if (!ns)
- + 		return;
- + 	memset(&ssh, 0, sizeof(ssh));
- + 	ssh.hwtstamp = ns_to_ktime(ns);
- + 	skb_tstamp_tx(skb, &ssh);
- + }
- + 
- + #endif /*CONFIG_TI_CPTS*/
- + 
- + int cpts_register(struct device *dev, struct cpts *cpts,
- + 		  u32 mult, u32 shift)
- + {
- + #ifdef CONFIG_TI_CPTS
- + 	int err, i;
- + 	unsigned long flags;
- + 
- + 	if (ptp_filter_init(ptp_filter, ARRAY_SIZE(ptp_filter))) {
- + 		pr_err("cpts: bad ptp filter\n");
- + 		return -EINVAL;
- + 	}
- + 	cpts->info = cpts_info;
- + 	cpts->clock = ptp_clock_register(&cpts->info);
- + 	if (IS_ERR(cpts->clock)) {
- + 		err = PTR_ERR(cpts->clock);
- + 		cpts->clock = NULL;
- + 		return err;
- + 	}
- + 	spin_lock_init(&cpts->lock);
- + 
- + 	cpts->cc.read = cpts_systim_read;
- + 	cpts->cc.mask = CLOCKSOURCE_MASK(32);
- + 	cpts->cc_mult = mult;
- + 	cpts->cc.mult = mult;
- + 	cpts->cc.shift = shift;
- + 
- + 	INIT_LIST_HEAD(&cpts->events);
- + 	INIT_LIST_HEAD(&cpts->pool);
- + 	for (i = 0; i < CPTS_MAX_EVENTS; i++)
- + 		list_add(&cpts->pool_data[i].list, &cpts->pool);
- + 
- + 	cpts_clk_init(cpts);
- + 	cpts_write32(cpts, CPTS_EN, control);
- + 	cpts_write32(cpts, TS_PEND_EN, int_enable);
- + 
- + 	spin_lock_irqsave(&cpts->lock, flags);
- + 	timecounter_init(&cpts->tc, &cpts->cc, ktime_to_ns(ktime_get_real()));
- + 	spin_unlock_irqrestore(&cpts->lock, flags);
- + 
- + 	INIT_DELAYED_WORK(&cpts->overflow_work, cpts_overflow_check);
- + 	schedule_delayed_work(&cpts->overflow_work, CPTS_OVERFLOW_PERIOD);
- + #endif
- + 	return 0;
- + }
- + 
- + void cpts_unregister(struct cpts *cpts)
- + {
- + #ifdef CONFIG_TI_CPTS
- + 	if (cpts->clock) {
- + 		ptp_clock_unregister(cpts->clock);
- + 		cancel_delayed_work_sync(&cpts->overflow_work);
- + 	}
- + 	if (cpts->refclk)
- + 		cpts_clk_release(cpts);
- + #endif
- + }
- diff -crN linux-3.2.1_o/drivers/net/ethernet/ti/cpts.h linux-3.2.1/drivers/net/ethernet/ti/cpts.h
- *** linux-3.2.1_o/drivers/net/ethernet/ti/cpts.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/drivers/net/ethernet/ti/cpts.h	2014-05-15 13:25:14.594998248 +0900
- ***************
- *** 0 ****
- --- 1,146 ----
- + /*
- +  * TI Common Platform Time Sync
- +  *
- +  * Copyright (C) 2012 Richard Cochran <richardcochran@gmail.com>
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; either version 2 of the License, or
- +  * (at your option) any later version.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- +  */
- + #ifndef _TI_CPTS_H_
- + #define _TI_CPTS_H_
- + 
- + #include <linux/clk.h>
- + #include <linux/clkdev.h>
- + #include <linux/clocksource.h>
- + #include <linux/device.h>
- + #include <linux/list.h>
- + #include <linux/ptp_clock_kernel.h>
- + #include <linux/skbuff.h>
- + 
- + struct cpsw_cpts {
- + 	u32 idver;                /* Identification and version */
- + 	u32 control;              /* Time sync control */
- + 	u32 res1;
- + 	u32 ts_push;              /* Time stamp event push */
- + 	u32 ts_load_val;          /* Time stamp load value */
- + 	u32 ts_load_en;           /* Time stamp load enable */
- + 	u32 res2[2];
- + 	u32 intstat_raw;          /* Time sync interrupt status raw */
- + 	u32 intstat_masked;       /* Time sync interrupt status masked */
- + 	u32 int_enable;           /* Time sync interrupt enable */
- + 	u32 res3;
- + 	u32 event_pop;            /* Event interrupt pop */
- + 	u32 event_low;            /* 32 Bit Event Time Stamp */
- + 	u32 event_high;           /* Event Type Fields */
- + };
- + 
- + /* Bit definitions for the IDVER register */
- + #define TX_IDENT_SHIFT       (16)    /* TX Identification Value */
- + #define TX_IDENT_MASK        (0xffff)
- + #define RTL_VER_SHIFT        (11)    /* RTL Version Value */
- + #define RTL_VER_MASK         (0x1f)
- + #define MAJOR_VER_SHIFT      (8)     /* Major Version Value */
- + #define MAJOR_VER_MASK       (0x7)
- + #define MINOR_VER_SHIFT      (0)     /* Minor Version Value */
- + #define MINOR_VER_MASK       (0xff)
- + 
- + /* Bit definitions for the CONTROL register */
- + #define HW4_TS_PUSH_EN       (1<<11) /* Hardware push 4 enable */
- + #define HW3_TS_PUSH_EN       (1<<10) /* Hardware push 3 enable */
- + #define HW2_TS_PUSH_EN       (1<<9)  /* Hardware push 2 enable */
- + #define HW1_TS_PUSH_EN       (1<<8)  /* Hardware push 1 enable */
- + #define INT_TEST             (1<<1)  /* Interrupt Test */
- + #define CPTS_EN              (1<<0)  /* Time Sync Enable */
- + 
- + /*
- +  * Definitions for the single bit resisters:
- +  * TS_PUSH TS_LOAD_EN  INTSTAT_RAW INTSTAT_MASKED INT_ENABLE EVENT_POP
- +  */
- + #define TS_PUSH             (1<<0)  /* Time stamp event push */
- + #define TS_LOAD_EN          (1<<0)  /* Time Stamp Load */
- + #define TS_PEND_RAW         (1<<0)  /* int read (before enable) */
- + #define TS_PEND             (1<<0)  /* masked interrupt read (after enable) */
- + #define TS_PEND_EN          (1<<0)  /* masked interrupt enable */
- + #define EVENT_POP           (1<<0)  /* writing discards one event */
- + 
- + /* Bit definitions for the EVENT_HIGH register */
- + #define PORT_NUMBER_SHIFT    (24)    /* Indicates Ethernet port or HW pin */
- + #define PORT_NUMBER_MASK     (0x1f)
- + #define EVENT_TYPE_SHIFT     (20)    /* Time sync event type */
- + #define EVENT_TYPE_MASK      (0xf)
- + #define MESSAGE_TYPE_SHIFT   (16)    /* PTP message type */
- + #define MESSAGE_TYPE_MASK    (0xf)
- + #define SEQUENCE_ID_SHIFT    (0)     /* PTP message sequence ID */
- + #define SEQUENCE_ID_MASK     (0xffff)
- + 
- + enum {
- + 	CPTS_EV_PUSH, /* Time Stamp Push Event */
- + 	CPTS_EV_ROLL, /* Time Stamp Rollover Event */
- + 	CPTS_EV_HALF, /* Time Stamp Half Rollover Event */
- + 	CPTS_EV_HW,   /* Hardware Time Stamp Push Event */
- + 	CPTS_EV_RX,   /* Ethernet Receive Event */
- + 	CPTS_EV_TX,   /* Ethernet Transmit Event */
- + };
- + 
- + /* This covers any input clock up to about 500 MHz. */
- + #define CPTS_OVERFLOW_PERIOD (HZ * 8)
- + 
- + #define CPTS_FIFO_DEPTH 16
- + #define CPTS_MAX_EVENTS 32
- + 
- + struct cpts_event {
- + 	struct list_head list;
- + 	unsigned long tmo;
- + 	u32 high;
- + 	u32 low;
- + };
- + 
- + struct cpts {
- + 	struct cpsw_cpts __iomem *reg;
- + 	int tx_enable;
- + 	int rx_enable;
- + #ifdef CONFIG_TI_CPTS
- + 	struct ptp_clock_info info;
- + 	struct ptp_clock *clock;
- + 	spinlock_t lock; /* protects time registers */
- + 	u32 cc_mult; /* for the nominal frequency */
- + 	struct cyclecounter cc;
- + 	struct timecounter tc;
- + 	struct delayed_work overflow_work;
- + 	int phc_index;
- + 	struct clk *refclk;
- + 	unsigned long freq;
- + 	struct list_head events;
- + 	struct list_head pool;
- + 	struct cpts_event pool_data[CPTS_MAX_EVENTS];
- + #endif
- + };
- + 
- + #ifdef CONFIG_TI_CPTS
- + extern void cpts_rx_timestamp(struct cpts *cpts, struct sk_buff *skb);
- + extern void cpts_tx_timestamp(struct cpts *cpts, struct sk_buff *skb);
- + #else
- + static inline void cpts_rx_timestamp(struct cpts *cpts, struct sk_buff *skb)
- + {
- + }
- + static inline void cpts_tx_timestamp(struct cpts *cpts, struct sk_buff *skb)
- + {
- + }
- + #endif
- + 
- + extern int cpts_register(struct device *dev, struct cpts *cpts,
- + 			 u32 mult, u32 shift);
- + extern void cpts_unregister(struct cpts *cpts);
- + 
- + #endif
- diff -crN linux-3.2.1_o/drivers/net/ethernet/ti/davinci_cpdma.c linux-3.2.1/drivers/net/ethernet/ti/davinci_cpdma.c
- *** linux-3.2.1_o/drivers/net/ethernet/ti/davinci_cpdma.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/net/ethernet/ti/davinci_cpdma.c	2014-05-15 13:25:14.594998248 +0900
- ***************
- *** 19,24 ****
- --- 19,25 ----
-   #include <linux/err.h>
-   #include <linux/dma-mapping.h>
-   #include <linux/io.h>
- + #include <linux/export.h>
-   
-   #include "davinci_cpdma.h"
-   
- ***************
- *** 59,64 ****
- --- 60,67 ----
-   #define CPDMA_DESC_EOQ		BIT(28)
-   #define CPDMA_DESC_TD_COMPLETE	BIT(27)
-   #define CPDMA_DESC_PASS_CRC	BIT(26)
- + #define CPDMA_DESC_TO_PORT_EN	BIT(20)
- + #define CPDMA_DESC_PORT_MASK	(BIT(18) | BIT(17) | BIT(16))
-   
-   #define CPDMA_TEARDOWN_VALUE	0xfffffffc
-   
- ***************
- *** 104,116 ****
-   };
-   
-   struct cpdma_chan {
-   	enum cpdma_state		state;
-   	struct cpdma_ctlr		*ctlr;
-   	int				chan_num;
-   	spinlock_t			lock;
- - 	struct cpdma_desc __iomem	*head, *tail;
-   	int				count;
- - 	void __iomem			*hdp, *cp, *rxfree;
-   	u32				mask;
-   	cpdma_handler_fn		handler;
-   	enum dma_data_direction		dir;
- --- 107,119 ----
-   };
-   
-   struct cpdma_chan {
- + 	struct cpdma_desc __iomem	*head, *tail;
- + 	void __iomem			*hdp, *cp, *rxfree;
-   	enum cpdma_state		state;
-   	struct cpdma_ctlr		*ctlr;
-   	int				chan_num;
-   	spinlock_t			lock;
-   	int				count;
-   	u32				mask;
-   	cpdma_handler_fn		handler;
-   	enum dma_data_direction		dir;
- ***************
- *** 216,222 ****
-   }
-   
-   static struct cpdma_desc __iomem *
- ! cpdma_desc_alloc(struct cpdma_desc_pool *pool, int num_desc)
-   {
-   	unsigned long flags;
-   	int index;
- --- 219,225 ----
-   }
-   
-   static struct cpdma_desc __iomem *
- ! cpdma_desc_alloc(struct cpdma_desc_pool *pool, int num_desc, bool is_rx)
-   {
-   	unsigned long flags;
-   	int index;
- ***************
- *** 224,231 ****
-   
-   	spin_lock_irqsave(&pool->lock, flags);
-   
- ! 	index = bitmap_find_next_zero_area(pool->bitmap, pool->num_desc, 0,
- ! 					   num_desc, 0);
-   	if (index < pool->num_desc) {
-   		bitmap_set(pool->bitmap, index, num_desc);
-   		desc = pool->iomap + pool->desc_size * index;
- --- 227,240 ----
-   
-   	spin_lock_irqsave(&pool->lock, flags);
-   
- ! 	if (is_rx) {
- ! 		index = bitmap_find_next_zero_area(pool->bitmap,
- ! 				pool->num_desc/2, 0, num_desc, 0);
- ! 	 } else {
- ! 		index = bitmap_find_next_zero_area(pool->bitmap,
- ! 				pool->num_desc, pool->num_desc/2, num_desc, 0);
- ! 	}
- ! 
-   	if (index < pool->num_desc) {
-   		bitmap_set(pool->bitmap, index, num_desc);
-   		desc = pool->iomap + pool->desc_size * index;
- ***************
- *** 276,281 ****
- --- 285,291 ----
-   		ctlr->num_chan = CPDMA_MAX_CHANNELS;
-   	return ctlr;
-   }
- + EXPORT_SYMBOL_GPL(cpdma_ctlr_create);
-   
-   int cpdma_ctlr_start(struct cpdma_ctlr *ctlr)
-   {
- ***************
- *** 321,326 ****
- --- 331,337 ----
-   	spin_unlock_irqrestore(&ctlr->lock, flags);
-   	return 0;
-   }
- + EXPORT_SYMBOL_GPL(cpdma_ctlr_start);
-   
-   int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr)
-   {
- ***************
- *** 351,356 ****
- --- 362,368 ----
-   	spin_unlock_irqrestore(&ctlr->lock, flags);
-   	return 0;
-   }
- + EXPORT_SYMBOL_GPL(cpdma_ctlr_stop);
-   
-   int cpdma_ctlr_dump(struct cpdma_ctlr *ctlr)
-   {
- ***************
- *** 444,449 ****
- --- 456,462 ----
-   	kfree(ctlr);
-   	return ret;
-   }
- + EXPORT_SYMBOL_GPL(cpdma_ctlr_destroy);
-   
-   int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable)
-   {
- ***************
- *** 467,477 ****
- --- 480,494 ----
-   	spin_unlock_irqrestore(&ctlr->lock, flags);
-   	return 0;
-   }
- + EXPORT_SYMBOL_GPL(cpdma_ctlr_int_ctrl);
-   
-   void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr)
-   {
-   	dma_reg_write(ctlr, CPDMA_MACEOIVECTOR, 0);
- + 	dma_reg_write(ctlr, CPDMA_MACEOIVECTOR, 1);
- + 	dma_reg_write(ctlr, CPDMA_MACEOIVECTOR, 2);
-   }
- + EXPORT_SYMBOL_GPL(cpdma_ctlr_eoi);
-   
-   struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num,
-   				     cpdma_handler_fn handler)
- ***************
- *** 528,533 ****
- --- 545,551 ----
-   err_chan_alloc:
-   	return ERR_PTR(ret);
-   }
- + EXPORT_SYMBOL_GPL(cpdma_chan_create);
-   
-   int cpdma_chan_destroy(struct cpdma_chan *chan)
-   {
- ***************
- *** 545,550 ****
- --- 563,569 ----
-   	kfree(chan);
-   	return 0;
-   }
- + EXPORT_SYMBOL_GPL(cpdma_chan_destroy);
-   
-   int cpdma_chan_get_stats(struct cpdma_chan *chan,
-   			 struct cpdma_chan_stats *stats)
- ***************
- *** 557,562 ****
- --- 576,582 ----
-   	spin_unlock_irqrestore(&chan->lock, flags);
-   	return 0;
-   }
- + EXPORT_SYMBOL_GPL(cpdma_chan_get_stats);
-   
-   int cpdma_chan_dump(struct cpdma_chan *chan)
-   {
- ***************
- *** 643,649 ****
-   }
-   
-   int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data,
- ! 		      int len, gfp_t gfp_mask)
-   {
-   	struct cpdma_ctlr		*ctlr = chan->ctlr;
-   	struct cpdma_desc __iomem	*desc;
- --- 663,669 ----
-   }
-   
-   int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data,
- ! 		      int len, int directed, gfp_t gfp_mask)
-   {
-   	struct cpdma_ctlr		*ctlr = chan->ctlr;
-   	struct cpdma_desc __iomem	*desc;
- ***************
- *** 651,656 ****
- --- 671,677 ----
-   	unsigned long			flags;
-   	u32				mode;
-   	int				ret = 0;
- + 	bool                            is_rx;
-   
-   	spin_lock_irqsave(&chan->lock, flags);
-   
- ***************
- *** 659,665 ****
-   		goto unlock_ret;
-   	}
-   
- ! 	desc = cpdma_desc_alloc(ctlr->pool, 1);
-   	if (!desc) {
-   		chan->stats.desc_alloc_fail++;
-   		ret = -ENOMEM;
- --- 680,687 ----
-   		goto unlock_ret;
-   	}
-   
- ! 	is_rx = (chan->rxfree != 0);
- ! 	desc = cpdma_desc_alloc(ctlr->pool, 1, is_rx);
-   	if (!desc) {
-   		chan->stats.desc_alloc_fail++;
-   		ret = -ENOMEM;
- ***************
- *** 673,678 ****
- --- 695,702 ----
-   
-   	buffer = dma_map_single(ctlr->dev, data, len, chan->dir);
-   	mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP;
- + 	if ((!is_rx) && ((directed == 1) || (directed == 2)))
- + 		mode |= (CPDMA_DESC_TO_PORT_EN | (directed << 16));
-   
-   	desc_write(desc, hw_next,   0);
-   	desc_write(desc, hw_buffer, buffer);
- ***************
- *** 693,698 ****
- --- 717,723 ----
-   	spin_unlock_irqrestore(&chan->lock, flags);
-   	return ret;
-   }
- + EXPORT_SYMBOL_GPL(cpdma_chan_submit);
-   
-   static void __cpdma_chan_free(struct cpdma_chan *chan,
-   			      struct cpdma_desc __iomem *desc,
- ***************
- *** 720,728 ****
-   	int				status, outlen;
-   	struct cpdma_desc_pool		*pool = ctlr->pool;
-   	dma_addr_t			desc_dma;
- - 	unsigned long			flags;
- - 
- - 	spin_lock_irqsave(&chan->lock, flags);
-   
-   	desc = chan->head;
-   	if (!desc) {
- --- 745,750 ----
- ***************
- *** 739,763 ****
-   		status = -EBUSY;
-   		goto unlock_ret;
-   	}
- ! 	status	= status & (CPDMA_DESC_EOQ | CPDMA_DESC_TD_COMPLETE);
-   
-   	chan->head = desc_from_phys(pool, desc_read(desc, hw_next));
-   	chan_write(chan, cp, desc_dma);
-   	chan->count--;
-   	chan->stats.good_dequeue++;
-   
- ! 	if (status & CPDMA_DESC_EOQ) {
-   		chan->stats.requeue++;
-   		chan_write(chan, hdp, desc_phys(pool, chan->head));
-   	}
-   
- - 	spin_unlock_irqrestore(&chan->lock, flags);
- - 
-   	__cpdma_chan_free(chan, desc, outlen, status);
-   	return status;
-   
-   unlock_ret:
- - 	spin_unlock_irqrestore(&chan->lock, flags);
-   	return status;
-   }
-   
- --- 761,784 ----
-   		status = -EBUSY;
-   		goto unlock_ret;
-   	}
- ! 	status	= status & (CPDMA_DESC_EOQ | CPDMA_DESC_TD_COMPLETE |
- ! 			    CPDMA_DESC_PORT_MASK);
-   
-   	chan->head = desc_from_phys(pool, desc_read(desc, hw_next));
-   	chan_write(chan, cp, desc_dma);
-   	chan->count--;
-   	chan->stats.good_dequeue++;
-   
- ! 	if ((status & CPDMA_DESC_EOQ) && (chan->head) &&
- ! 			(!(status & CPDMA_DESC_TD_COMPLETE))) {
-   		chan->stats.requeue++;
-   		chan_write(chan, hdp, desc_phys(pool, chan->head));
-   	}
-   
-   	__cpdma_chan_free(chan, desc, outlen, status);
-   	return status;
-   
-   unlock_ret:
-   	return status;
-   }
-   
- ***************
- *** 776,781 ****
- --- 797,803 ----
-   	}
-   	return used;
-   }
- + EXPORT_SYMBOL_GPL(cpdma_chan_process);
-   
-   int cpdma_chan_start(struct cpdma_chan *chan)
-   {
- ***************
- *** 803,808 ****
- --- 825,831 ----
-   	spin_unlock_irqrestore(&chan->lock, flags);
-   	return 0;
-   }
- + EXPORT_SYMBOL_GPL(cpdma_chan_start);
-   
-   int cpdma_chan_stop(struct cpdma_chan *chan)
-   {
- ***************
- *** 863,868 ****
- --- 886,892 ----
-   	spin_unlock_irqrestore(&chan->lock, flags);
-   	return 0;
-   }
- + EXPORT_SYMBOL_GPL(cpdma_chan_stop);
-   
-   int cpdma_chan_int_ctrl(struct cpdma_chan *chan, bool enable)
-   {
- ***************
- *** 934,939 ****
- --- 958,964 ----
-   	spin_unlock_irqrestore(&ctlr->lock, flags);
-   	return ret;
-   }
- + EXPORT_SYMBOL_GPL(cpdma_control_get);
-   
-   int cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value)
-   {
- ***************
- *** 970,972 ****
- --- 995,998 ----
-   	spin_unlock_irqrestore(&ctlr->lock, flags);
-   	return ret;
-   }
- + EXPORT_SYMBOL_GPL(cpdma_control_set);
- diff -crN linux-3.2.1_o/drivers/net/ethernet/ti/davinci_cpdma.h linux-3.2.1/drivers/net/ethernet/ti/davinci_cpdma.h
- *** linux-3.2.1_o/drivers/net/ethernet/ti/davinci_cpdma.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/net/ethernet/ti/davinci_cpdma.h	2014-05-15 13:25:14.594998248 +0900
- ***************
- *** 24,29 ****
- --- 24,31 ----
-   #define __chan_linear(chan_num)	((chan_num) & (CPDMA_MAX_CHANNELS - 1))
-   #define chan_linear(chan)	__chan_linear((chan)->chan_num)
-   
- + #define CPDMA_RX_SOURCE_PORT(__status__)	((__status__ >> 16) & 0x7)
- + 
-   struct cpdma_params {
-   	struct device		*dev;
-   	void __iomem		*dmaregs;
- ***************
- *** 82,88 ****
-   int cpdma_chan_get_stats(struct cpdma_chan *chan,
-   			 struct cpdma_chan_stats *stats);
-   int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data,
- ! 		      int len, gfp_t gfp_mask);
-   int cpdma_chan_process(struct cpdma_chan *chan, int quota);
-   
-   int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable);
- --- 84,90 ----
-   int cpdma_chan_get_stats(struct cpdma_chan *chan,
-   			 struct cpdma_chan_stats *stats);
-   int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data,
- ! 		      int len, int directed, gfp_t gfp_mask);
-   int cpdma_chan_process(struct cpdma_chan *chan, int quota);
-   
-   int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable);
- diff -crN linux-3.2.1_o/drivers/net/ethernet/ti/davinci_emac.c linux-3.2.1/drivers/net/ethernet/ti/davinci_emac.c
- *** linux-3.2.1_o/drivers/net/ethernet/ti/davinci_emac.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/net/ethernet/ti/davinci_emac.c	2014-05-15 13:25:14.594998248 +0900
- ***************
- *** 1035,1041 ****
-   
-   recycle:
-   	ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
- ! 			skb_tailroom(skb), GFP_KERNEL);
-   	if (WARN_ON(ret < 0))
-   		dev_kfree_skb_any(skb);
-   }
- --- 1035,1041 ----
-   
-   recycle:
-   	ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
- ! 			skb_tailroom(skb), 0, GFP_KERNEL);
-   	if (WARN_ON(ret < 0))
-   		dev_kfree_skb_any(skb);
-   }
- ***************
- *** 1085,1091 ****
-   	skb_tx_timestamp(skb);
-   
-   	ret_code = cpdma_chan_submit(priv->txchan, skb, skb->data, skb->len,
- ! 				     GFP_KERNEL);
-   	if (unlikely(ret_code != 0)) {
-   		if (netif_msg_tx_err(priv) && net_ratelimit())
-   			dev_err(emac_dev, "DaVinci EMAC: desc submit failed");
- --- 1085,1091 ----
-   	skb_tx_timestamp(skb);
-   
-   	ret_code = cpdma_chan_submit(priv->txchan, skb, skb->data, skb->len,
- ! 				     0, GFP_KERNEL);
-   	if (unlikely(ret_code != 0)) {
-   		if (netif_msg_tx_err(priv) && net_ratelimit())
-   			dev_err(emac_dev, "DaVinci EMAC: desc submit failed");
- ***************
- *** 1544,1550 ****
-   			break;
-   
-   		ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
- ! 					skb_tailroom(skb), GFP_KERNEL);
-   		if (WARN_ON(ret < 0))
-   			break;
-   	}
- --- 1544,1550 ----
-   			break;
-   
-   		ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
- ! 					skb_tailroom(skb), 0, GFP_KERNEL);
-   		if (WARN_ON(ret < 0))
-   			break;
-   	}
- diff -crN linux-3.2.1_o/drivers/net/ethernet/ti/davinci_mdio.c linux-3.2.1/drivers/net/ethernet/ti/davinci_mdio.c
- *** linux-3.2.1_o/drivers/net/ethernet/ti/davinci_mdio.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/net/ethernet/ti/davinci_mdio.c	2014-05-15 13:35:23.323807000 +0900
- ***************
- *** 34,39 ****
- --- 34,40 ----
-   #include <linux/clk.h>
-   #include <linux/err.h>
-   #include <linux/io.h>
- + #include <linux/pm_runtime.h>
-   #include <linux/davinci_emac.h>
-   
-   /*
- ***************
- *** 48,53 ****
- --- 49,58 ----
-   
-   #define DEF_OUT_FREQ		2200000		/* 2.2 MHz */
-   
- + #define CPGMAC_CLK_CTRL_REG	0x44E00014
- + #define CPGMAC_CLK_SYSC         0x4A101208
- + #define CPSW_NO_IDLE_NO_STDBY   0xA
- + 
-   struct davinci_mdio_regs {
-   	u32	version;
-   	u32	control;
- ***************
- *** 181,186 ****
- --- 186,196 ----
-   		__davinci_mdio_reset(data);
-   		return -EAGAIN;
-   	}
- + 
- + 	reg = __raw_readl(&regs->user[0].access);
- + 	if ((reg & USERACCESS_GO) == 0)
- + 		return 0;
- + 
-   	dev_err(data->dev, "timed out waiting for user access\n");
-   	return -ETIMEDOUT;
-   }
- ***************
- *** 315,321 ****
-   	data->bus->priv		= data;
-   	snprintf(data->bus->id, MII_BUS_ID_SIZE, "%x", pdev->id);
-   
- ! 	data->clk = clk_get(dev, NULL);
-   	if (IS_ERR(data->clk)) {
-   		data->clk = NULL;
-   		dev_err(dev, "failed to get device clock\n");
- --- 325,333 ----
-   	data->bus->priv		= data;
-   	snprintf(data->bus->id, MII_BUS_ID_SIZE, "%x", pdev->id);
-   
- ! 	pm_runtime_enable(&pdev->dev);
- ! 	pm_runtime_get_sync(&pdev->dev);
- ! 	data->clk = clk_get(&pdev->dev, "fck");
-   	if (IS_ERR(data->clk)) {
-   		data->clk = NULL;
-   		dev_err(dev, "failed to get device clock\n");
- ***************
- *** 323,330 ****
-   		goto bail_out;
-   	}
-   
- - 	clk_enable(data->clk);
- - 
-   	dev_set_drvdata(dev, data);
-   	data->dev = dev;
-   	spin_lock_init(&data->lock);
- --- 335,340 ----
- ***************
- *** 371,381 ****
-   bail_out:
-   	if (data->bus)
-   		mdiobus_free(data->bus);
- ! 
- ! 	if (data->clk) {
- ! 		clk_disable(data->clk);
-   		clk_put(data->clk);
- ! 	}
-   
-   	kfree(data);
-   
- --- 381,390 ----
-   bail_out:
-   	if (data->bus)
-   		mdiobus_free(data->bus);
- ! 	if (data->clk)
-   		clk_put(data->clk);
- ! 	pm_runtime_put_sync(&pdev->dev);
- ! 	pm_runtime_disable(&pdev->dev);
-   
-   	kfree(data);
-   
- ***************
- *** 387,399 ****
-   	struct device *dev = &pdev->dev;
-   	struct davinci_mdio_data *data = dev_get_drvdata(dev);
-   
- ! 	if (data->bus)
-   		mdiobus_free(data->bus);
-   
- ! 	if (data->clk) {
- ! 		clk_disable(data->clk);
-   		clk_put(data->clk);
- ! 	}
-   
-   	dev_set_drvdata(dev, NULL);
-   
- --- 396,410 ----
-   	struct device *dev = &pdev->dev;
-   	struct davinci_mdio_data *data = dev_get_drvdata(dev);
-   
- ! 	if (data->bus) {
- ! 		mdiobus_unregister(data->bus);
-   		mdiobus_free(data->bus);
- + 	}
-   
- ! 	if (data->clk)
-   		clk_put(data->clk);
- ! 	pm_runtime_put_sync(&pdev->dev);
- ! 	pm_runtime_disable(&pdev->dev);
-   
-   	dev_set_drvdata(dev, NULL);
-   
- ***************
- *** 402,407 ****
- --- 413,445 ----
-   	return 0;
-   }
-   
- + static inline int wait_for_clock_enable(struct davinci_mdio_data *data)
- + {
- + 	unsigned long timeout = jiffies + msecs_to_jiffies(MDIO_TIMEOUT);
- + 	u32 __iomem *cpgmac_clk = ioremap(CPGMAC_CLK_CTRL_REG, 4);
- + 	u32 __iomem *cpgmac_sysc = ioremap(CPGMAC_CLK_SYSC, 4);
- + 	u32 reg = 0;
- + 
- + 	while (time_after(timeout, jiffies)) {
- + 		reg = readl(cpgmac_clk);
- + 		if ((reg & 0x30000) == 0) {
- + 			writel(CPSW_NO_IDLE_NO_STDBY, cpgmac_sysc);
- + 			goto iounmap_ret;
- +                 }
- + 	}
- + 	dev_err(data->dev,
- + 		"timed out waiting for CPGMAC clock enable, value = 0x%x\n",
- + 		reg);
- + 	iounmap(cpgmac_sysc);
- + 	iounmap(cpgmac_clk);
- + 	return -ETIMEDOUT;
- + 
- + iounmap_ret:
- + 	iounmap(cpgmac_sysc);
- + 	iounmap(cpgmac_clk);
- + 	return 0;
- + }
- + 
-   static int davinci_mdio_suspend(struct device *dev)
-   {
-   	struct davinci_mdio_data *data = dev_get_drvdata(dev);
- ***************
- *** 415,422 ****
-   	__raw_writel(ctrl, &data->regs->control);
-   	wait_for_idle(data);
-   
- ! 	if (data->clk)
- ! 		clk_disable(data->clk);
-   
-   	data->suspended = true;
-   	spin_unlock(&data->lock);
- --- 453,459 ----
-   	__raw_writel(ctrl, &data->regs->control);
-   	wait_for_idle(data);
-   
- ! 	pm_runtime_put_sync(data->dev);
-   
-   	data->suspended = true;
-   	spin_unlock(&data->lock);
- ***************
- *** 430,444 ****
-   	u32 ctrl;
-   
-   	spin_lock(&data->lock);
- ! 	if (data->clk)
- ! 		clk_enable(data->clk);
-   
-   	/* restart the scan state machine */
-   	ctrl = __raw_readl(&data->regs->control);
-   	ctrl |= CONTROL_ENABLE;
-   	__raw_writel(ctrl, &data->regs->control);
- - 
-   	data->suspended = false;
-   	spin_unlock(&data->lock);
-   
-   	return 0;
- --- 467,483 ----
-   	u32 ctrl;
-   
-   	spin_lock(&data->lock);
- ! 	pm_runtime_put_sync(data->dev);
- ! 
- ! 	/* Need to wait till Module is enabled */
- ! 	wait_for_clock_enable(data);
-   
-   	/* restart the scan state machine */
-   	ctrl = __raw_readl(&data->regs->control);
-   	ctrl |= CONTROL_ENABLE;
-   	__raw_writel(ctrl, &data->regs->control);
-   	data->suspended = false;
- + 
-   	spin_unlock(&data->lock);
-   
-   	return 0;
- diff -crN linux-3.2.1_o/drivers/net/ethernet/ti/Kconfig linux-3.2.1/drivers/net/ethernet/ti/Kconfig
- *** linux-3.2.1_o/drivers/net/ethernet/ti/Kconfig	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/net/ethernet/ti/Kconfig	2014-05-15 13:25:14.594998248 +0900
- ***************
- *** 5,11 ****
-   config NET_VENDOR_TI
-   	bool "Texas Instruments (TI) devices"
-   	default y
- ! 	depends on PCI || EISA || AR7 || (ARM && (ARCH_DAVINCI || ARCH_OMAP3))
-   	---help---
-   	  If you have a network (Ethernet) card belonging to this class, say Y
-   	  and read the Ethernet-HOWTO, available from
- --- 5,11 ----
-   config NET_VENDOR_TI
-   	bool "Texas Instruments (TI) devices"
-   	default y
- ! 	depends on PCI || EISA || AR7 || (ARM && (ARCH_DAVINCI || ARCH_OMAP3 || ARCH_CKB))
-   	---help---
-   	  If you have a network (Ethernet) card belonging to this class, say Y
-   	  and read the Ethernet-HOWTO, available from
- ***************
- *** 20,26 ****
-   
-   config TI_DAVINCI_EMAC
-   	tristate "TI DaVinci EMAC Support"
- ! 	depends on ARM && ( ARCH_DAVINCI || ARCH_OMAP3 )
-   	select TI_DAVINCI_MDIO
-   	select TI_DAVINCI_CPDMA
-   	select PHYLIB
- --- 20,26 ----
-   
-   config TI_DAVINCI_EMAC
-   	tristate "TI DaVinci EMAC Support"
- ! 	depends on ARM && ( ARCH_DAVINCI || ARCH_OMAP3 || ARCH_CKB )
-   	select TI_DAVINCI_MDIO
-   	select TI_DAVINCI_CPDMA
-   	select PHYLIB
- ***************
- *** 32,38 ****
-   
-   config TI_DAVINCI_MDIO
-   	tristate "TI DaVinci MDIO Support"
- ! 	depends on ARM && ( ARCH_DAVINCI || ARCH_OMAP3 )
-   	select PHYLIB
-   	---help---
-   	  This driver supports TI's DaVinci MDIO module.
- --- 32,38 ----
-   
-   config TI_DAVINCI_MDIO
-   	tristate "TI DaVinci MDIO Support"
- ! 	depends on ARM && ( ARCH_DAVINCI || ARCH_OMAP3 || ARCH_CKB )
-   	select PHYLIB
-   	---help---
-   	  This driver supports TI's DaVinci MDIO module.
- ***************
- *** 42,54 ****
-   
-   config TI_DAVINCI_CPDMA
-   	tristate "TI DaVinci CPDMA Support"
- ! 	depends on ARM && ( ARCH_DAVINCI || ARCH_OMAP3 )
-   	---help---
-   	  This driver supports TI's DaVinci CPDMA dma engine.
-   
-   	  To compile this driver as a module, choose M here: the module
-   	  will be called davinci_cpdma.  This is recommended.
-   
-   config TLAN
-   	tristate "TI ThunderLAN support"
-   	depends on (PCI || EISA)
- --- 42,85 ----
-   
-   config TI_DAVINCI_CPDMA
-   	tristate "TI DaVinci CPDMA Support"
- ! 	depends on ARM && ( ARCH_DAVINCI || ARCH_OMAP3 || ARCH_CKB )
-   	---help---
-   	  This driver supports TI's DaVinci CPDMA dma engine.
-   
-   	  To compile this driver as a module, choose M here: the module
-   	  will be called davinci_cpdma.  This is recommended.
-   
- + config TI_CPSW
- + 	tristate "TI CPSW Switch Support"
- + 	depends on ARM && (ARCH_DAVINCI || SOC_OMAPAM33XX || ARCH_CKB )
- + 	select TI_DAVINCI_CPDMA
- + 	select TI_DAVINCI_MDIO
- + 	---help---
- + 	  This driver supports TI's CPSW Ethernet Switch.
- + 
- + 	  To compile this driver as a module, choose M here: the module
- + 	  will be called cpsw.
- + 
- + config TI_CPTS
- + 	boolean "TI Common Platform Time Sync (CPTS) Support"
- + 	depends on TI_CPSW
- + 	select PTP_1588_CLOCK
- + 	select PPS
- + 	---help---
- + 	  This driver supports the Common Platform Time Sync unit of
- + 	  the CPSW Ethernet Switch.
- + 
- + 	  The unit can time stamp PTP UDP/IPv4
- + 	  and Layer 2 packets, and the driver offers a PTP Hardware Clock.
- + 
- + config TI_CPSW_DUAL_EMAC
- + 	bool "TI CPSW Switch as Dual EMAC"
- + 	depends on TI_CPSW
- + 	help
- + 	  This driver makes TI's CPSW Ethernet Switch as Dual EMAC. Switch
- + 	  features will not be available in this mode, Dual Emac default
- + 	  VLAN ids should not be used in VLAN configuration
- + 
-   config TLAN
-   	tristate "TI ThunderLAN support"
-   	depends on (PCI || EISA)
- diff -crN linux-3.2.1_o/drivers/net/ethernet/ti/Makefile linux-3.2.1/drivers/net/ethernet/ti/Makefile
- *** linux-3.2.1_o/drivers/net/ethernet/ti/Makefile	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/net/ethernet/ti/Makefile	2014-05-15 13:25:14.598686576 +0900
- ***************
- *** 7,9 ****
- --- 7,11 ----
-   obj-$(CONFIG_TI_DAVINCI_EMAC) += davinci_emac.o
-   obj-$(CONFIG_TI_DAVINCI_MDIO) += davinci_mdio.o
-   obj-$(CONFIG_TI_DAVINCI_CPDMA) += davinci_cpdma.o
- + obj-$(CONFIG_TI_CPSW) += ti_cpsw.o
- + ti_cpsw-y := cpsw_ale.o cpsw.o cpts.o
- diff -crN linux-3.2.1_o/drivers/net/phy/micrel.c linux-3.2.1/drivers/net/phy/micrel.c
- *** linux-3.2.1_o/drivers/net/phy/micrel.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/net/phy/micrel.c	2014-05-15 13:25:14.598686576 +0900
- ***************
- *** 179,185 ****
-   	.features	= (PHY_GBIT_FEATURES | SUPPORTED_Pause
-   				| SUPPORTED_Asym_Pause),
-   	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
- ! 	.config_init	= kszphy_config_init,
-   	.config_aneg	= genphy_config_aneg,
-   	.read_status	= genphy_read_status,
-   	.ack_interrupt	= kszphy_ack_interrupt,
- --- 179,186 ----
-   	.features	= (PHY_GBIT_FEATURES | SUPPORTED_Pause
-   				| SUPPORTED_Asym_Pause),
-   	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
- ! 	//.config_init	= kszphy_config_init,
- ! 	.config_init	= genphy_config_init,
-   	.config_aneg	= genphy_config_aneg,
-   	.read_status	= genphy_read_status,
-   	.ack_interrupt	= kszphy_ack_interrupt,
- ***************
- *** 191,204 ****
-   {
-   	int ret;
-   
- ! 	ret = phy_driver_register(&ks8001_driver);
-   	if (ret)
-   		goto err1;
-   
- ! 	ret = phy_driver_register(&ksz9021_driver);
-   	if (ret)
-   		goto err2;
- ! 
-   	ret = phy_driver_register(&ks8737_driver);
-   	if (ret)
-   		goto err3;
- --- 192,205 ----
-   {
-   	int ret;
-   
- ! 	ret = phy_driver_register(&ksz9021_driver);
-   	if (ret)
-   		goto err1;
-   
- ! 	ret = phy_driver_register(&ks8001_driver);
-   	if (ret)
-   		goto err2;
- ! 		
-   	ret = phy_driver_register(&ks8737_driver);
-   	if (ret)
-   		goto err3;
- ***************
- *** 216,233 ****
-   err4:
-   	phy_driver_unregister(&ks8737_driver);
-   err3:
- - 	phy_driver_unregister(&ksz9021_driver);
- - err2:
-   	phy_driver_unregister(&ks8001_driver);
-   err1:
-   	return ret;
-   }
-   
-   static void __exit ksphy_exit(void)
-   {
-   	phy_driver_unregister(&ks8001_driver);
-   	phy_driver_unregister(&ks8737_driver);
- - 	phy_driver_unregister(&ksz9021_driver);
-   	phy_driver_unregister(&ks8041_driver);
-   	phy_driver_unregister(&ks8051_driver);
-   }
- --- 217,234 ----
-   err4:
-   	phy_driver_unregister(&ks8737_driver);
-   err3:
-   	phy_driver_unregister(&ks8001_driver);
- + err2:
- + 	phy_driver_unregister(&ksz9021_driver);
-   err1:
-   	return ret;
-   }
-   
-   static void __exit ksphy_exit(void)
-   {
- + 	phy_driver_unregister(&ksz9021_driver);
-   	phy_driver_unregister(&ks8001_driver);
-   	phy_driver_unregister(&ks8737_driver);
-   	phy_driver_unregister(&ks8041_driver);
-   	phy_driver_unregister(&ks8051_driver);
-   }
- diff -crN linux-3.2.1_o/drivers/net/phy/phy_device.c linux-3.2.1/drivers/net/phy/phy_device.c
- *** linux-3.2.1_o/drivers/net/phy/phy_device.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/net/phy/phy_device.c	2014-05-15 13:25:14.598686576 +0900
- ***************
- *** 169,176 ****
-   	dev->link = 1;
-   	dev->interface = PHY_INTERFACE_MODE_GMII;
-   
-   	dev->autoneg = AUTONEG_ENABLE;
- ! 
-   	dev->addr = addr;
-   	dev->phy_id = phy_id;
-   	dev->bus = bus;
- --- 169,179 ----
-   	dev->link = 1;
-   	dev->interface = PHY_INTERFACE_MODE_GMII;
-   
- + #if 1
-   	dev->autoneg = AUTONEG_ENABLE;
- ! #else
- ! 	dev->autoneg = AUTONEG_DISABLE;
- ! #endif
-   	dev->addr = addr;
-   	dev->phy_id = phy_id;
-   	dev->bus = bus;
- ***************
- *** 624,630 ****
-   {
-   	int err;
-   	int ctl = 0;
- ! 
-   	phydev->pause = phydev->asym_pause = 0;
-   
-   	if (SPEED_1000 == phydev->speed)
- --- 627,633 ----
-   {
-   	int err;
-   	int ctl = 0;
- ! 	int bmcr;
-   	phydev->pause = phydev->asym_pause = 0;
-   
-   	if (SPEED_1000 == phydev->speed)
- ***************
- *** 637,642 ****
- --- 640,660 ----
-   	
-   	err = phy_write(phydev, MII_BMCR, ctl);
-   
- + 	bmcr = phy_read(phydev, MII_BMCR);
- + 
- + 	if (bmcr & BMCR_SPEED1000)
- + 	{
- + 		printk("1000..haha\n");
- + 	}
- + 	if (bmcr & BMCR_SPEED100)
- + 	{
- + 		printk("100..haha\n");
- + 	}
- + 	else
- + 	{
- + 		printk("10..haha\n");
- + 	}
- + 
-   	return err;
-   }
-   
- ***************
- *** 836,842 ****
-   }
-   EXPORT_SYMBOL(genphy_read_status);
-   
- ! static int genphy_config_init(struct phy_device *phydev)
-   {
-   	int val;
-   	u32 features;
- --- 854,860 ----
-   }
-   EXPORT_SYMBOL(genphy_read_status);
-   
- ! int genphy_config_init(struct phy_device *phydev)
-   {
-   	int val;
-   	u32 features;
- ***************
- *** 882,887 ****
- --- 900,907 ----
-   
-   	return 0;
-   }
- + EXPORT_SYMBOL(genphy_config_init);
- + 
-   int genphy_suspend(struct phy_device *phydev)
-   {
-   	int value;
- diff -crN linux-3.2.1_o/drivers/net/wireless/iwlwifi/iwl-commands.h linux-3.2.1/drivers/net/wireless/iwlwifi/iwl-commands.h
- *** linux-3.2.1_o/drivers/net/wireless/iwlwifi/iwl-commands.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/net/wireless/iwlwifi/iwl-commands.h	2014-05-15 13:25:14.598686576 +0900
- ***************
- *** 809,815 ****
-   #define	IWLAGN_STATION_COUNT	16
-   
-   #define	IWL_INVALID_STATION 	255
- ! #define IWL_MAX_TID_COUNT	8
-   
-   #define STA_FLG_TX_RATE_MSK		cpu_to_le32(1 << 2)
-   #define STA_FLG_PWR_SAVE_MSK		cpu_to_le32(1 << 8)
- --- 809,815 ----
-   #define	IWLAGN_STATION_COUNT	16
-   
-   #define	IWL_INVALID_STATION 	255
- ! #define IWL_MAX_TID_COUNT	9
-   
-   #define STA_FLG_TX_RATE_MSK		cpu_to_le32(1 << 2)
-   #define STA_FLG_PWR_SAVE_MSK		cpu_to_le32(1 << 8)
- diff -crN linux-3.2.1_o/drivers/net/wireless/iwlwifi/iwl-trans-pcie-int.h linux-3.2.1/drivers/net/wireless/iwlwifi/iwl-trans-pcie-int.h
- *** linux-3.2.1_o/drivers/net/wireless/iwlwifi/iwl-trans-pcie-int.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/net/wireless/iwlwifi/iwl-trans-pcie-int.h	2014-05-15 13:25:14.598686576 +0900
- ***************
- *** 219,225 ****
- --- 219,227 ----
-   
-   	/* INT ICT Table */
-   	__le32 *ict_tbl;
- + 	void *ict_tbl_vir;
-   	dma_addr_t ict_tbl_dma;
- + 	dma_addr_t aligned_ict_tbl_dma;
-   	int ict_index;
-   	u32 inta;
-   	bool use_ict;
- diff -crN linux-3.2.1_o/drivers/net/wireless/iwlwifi/iwl-trans-pcie-rx.c linux-3.2.1/drivers/net/wireless/iwlwifi/iwl-trans-pcie-rx.c
- *** linux-3.2.1_o/drivers/net/wireless/iwlwifi/iwl-trans-pcie-rx.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/net/wireless/iwlwifi/iwl-trans-pcie-rx.c	2014-05-15 13:25:14.602584518 +0900
- ***************
- *** 1136,1146 ****
-    * ICT functions
-    *
-    ******************************************************************************/
- ! 
- ! /* a device (PCI-E) page is 4096 bytes long */
- ! #define ICT_SHIFT	12
- ! #define ICT_SIZE	(1 << ICT_SHIFT)
- ! #define ICT_COUNT	(ICT_SIZE / sizeof(u32))
-   
-   /* Free dram table */
-   void iwl_free_isr_ict(struct iwl_trans *trans)
- --- 1136,1142 ----
-    * ICT functions
-    *
-    ******************************************************************************/
- ! #define ICT_COUNT (PAGE_SIZE/sizeof(u32))
-   
-   /* Free dram table */
-   void iwl_free_isr_ict(struct iwl_trans *trans)
- ***************
- *** 1148,1166 ****
-   	struct iwl_trans_pcie *trans_pcie =
-   		IWL_TRANS_GET_PCIE_TRANS(trans);
-   
- ! 	if (trans_pcie->ict_tbl) {
- ! 		dma_free_coherent(bus(trans)->dev, ICT_SIZE,
- ! 				  trans_pcie->ict_tbl,
-   				  trans_pcie->ict_tbl_dma);
- ! 		trans_pcie->ict_tbl = NULL;
- ! 		trans_pcie->ict_tbl_dma = 0;
-   	}
-   }
-   
-   
- ! /*
- !  * allocate dram shared table, it is an aligned memory
- !  * block of ICT_SIZE.
-    * also reset all data related to ICT table interrupt.
-    */
-   int iwl_alloc_isr_ict(struct iwl_trans *trans)
- --- 1144,1164 ----
-   	struct iwl_trans_pcie *trans_pcie =
-   		IWL_TRANS_GET_PCIE_TRANS(trans);
-   
- ! 	if (trans_pcie->ict_tbl_vir) {
- ! 		dma_free_coherent(bus(trans)->dev,
- ! 				  (sizeof(u32) * ICT_COUNT) + PAGE_SIZE,
- ! 				  trans_pcie->ict_tbl_vir,
-   				  trans_pcie->ict_tbl_dma);
- ! 		trans_pcie->ict_tbl_vir = NULL;
- ! 		memset(&trans_pcie->ict_tbl_dma, 0,
- ! 			sizeof(trans_pcie->ict_tbl_dma));
- ! 		memset(&trans_pcie->aligned_ict_tbl_dma, 0,
- ! 			sizeof(trans_pcie->aligned_ict_tbl_dma));
-   	}
-   }
-   
-   
- ! /* allocate dram shared table it is a PAGE_SIZE aligned
-    * also reset all data related to ICT table interrupt.
-    */
-   int iwl_alloc_isr_ict(struct iwl_trans *trans)
- ***************
- *** 1168,1193 ****
-   	struct iwl_trans_pcie *trans_pcie =
-   		IWL_TRANS_GET_PCIE_TRANS(trans);
-   
- ! 	trans_pcie->ict_tbl =
- ! 		dma_alloc_coherent(bus(trans)->dev, ICT_SIZE,
- ! 				   &trans_pcie->ict_tbl_dma,
- ! 				   GFP_KERNEL);
- ! 	if (!trans_pcie->ict_tbl)
-   		return -ENOMEM;
-   
- ! 	/* just an API sanity check ... it is guaranteed to be aligned */
- ! 	if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) {
- ! 		iwl_free_isr_ict(trans);
- ! 		return -EINVAL;
- ! 	}
- ! 
- ! 	IWL_DEBUG_ISR(trans, "ict dma addr %Lx\n",
- ! 		      (unsigned long long)trans_pcie->ict_tbl_dma);
- ! 
- ! 	IWL_DEBUG_ISR(trans, "ict vir addr %p\n", trans_pcie->ict_tbl);
-   
-   	/* reset table and index to all 0 */
- ! 	memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
-   	trans_pcie->ict_index = 0;
-   
-   	/* add periodic RX interrupt */
- --- 1166,1201 ----
-   	struct iwl_trans_pcie *trans_pcie =
-   		IWL_TRANS_GET_PCIE_TRANS(trans);
-   
- ! 	/* allocate shrared data table */
- ! 	trans_pcie->ict_tbl_vir =
- ! 		dma_alloc_coherent(bus(trans)->dev,
- ! 				   (sizeof(u32) * ICT_COUNT) + PAGE_SIZE,
- ! 				   &trans_pcie->ict_tbl_dma, GFP_KERNEL);
- ! 	if (!trans_pcie->ict_tbl_vir)
-   		return -ENOMEM;
-   
- ! 	/* align table to PAGE_SIZE boundary */
- ! 	trans_pcie->aligned_ict_tbl_dma =
- ! 		ALIGN(trans_pcie->ict_tbl_dma, PAGE_SIZE);
- ! 
- ! 	IWL_DEBUG_ISR(trans, "ict dma addr %Lx dma aligned %Lx diff %d\n",
- ! 			   (unsigned long long)trans_pcie->ict_tbl_dma,
- ! 			   (unsigned long long)trans_pcie->aligned_ict_tbl_dma,
- ! 			   (int)(trans_pcie->aligned_ict_tbl_dma -
- ! 			   trans_pcie->ict_tbl_dma));
- ! 
- ! 	trans_pcie->ict_tbl =  trans_pcie->ict_tbl_vir +
- ! 			  (trans_pcie->aligned_ict_tbl_dma -
- ! 			  trans_pcie->ict_tbl_dma);
- ! 
- ! 	IWL_DEBUG_ISR(trans, "ict vir addr %p vir aligned %p diff %d\n",
- ! 			     trans_pcie->ict_tbl, trans_pcie->ict_tbl_vir,
- ! 			(int)(trans_pcie->aligned_ict_tbl_dma -
- ! 			    trans_pcie->ict_tbl_dma));
-   
-   	/* reset table and index to all 0 */
- ! 	memset(trans_pcie->ict_tbl_vir, 0,
- ! 		(sizeof(u32) * ICT_COUNT) + PAGE_SIZE);
-   	trans_pcie->ict_index = 0;
-   
-   	/* add periodic RX interrupt */
- ***************
- *** 1205,1224 ****
-   	struct iwl_trans_pcie *trans_pcie =
-   		IWL_TRANS_GET_PCIE_TRANS(trans);
-   
- ! 	if (!trans_pcie->ict_tbl)
-   		return 0;
-   
-   	spin_lock_irqsave(&trans->shrd->lock, flags);
-   	iwl_disable_interrupts(trans);
-   
- ! 	memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
-   
- ! 	val = trans_pcie->ict_tbl_dma >> ICT_SHIFT;
-   
-   	val |= CSR_DRAM_INT_TBL_ENABLE;
-   	val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
-   
- ! 	IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
-   
-   	iwl_write32(bus(trans), CSR_DRAM_INT_TBL_REG, val);
-   	trans_pcie->use_ict = true;
- --- 1213,1235 ----
-   	struct iwl_trans_pcie *trans_pcie =
-   		IWL_TRANS_GET_PCIE_TRANS(trans);
-   
- ! 	if (!trans_pcie->ict_tbl_vir)
-   		return 0;
-   
-   	spin_lock_irqsave(&trans->shrd->lock, flags);
-   	iwl_disable_interrupts(trans);
-   
- ! 	memset(&trans_pcie->ict_tbl[0], 0, sizeof(u32) * ICT_COUNT);
-   
- ! 	val = trans_pcie->aligned_ict_tbl_dma >> PAGE_SHIFT;
-   
-   	val |= CSR_DRAM_INT_TBL_ENABLE;
-   	val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
-   
- ! 	IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%X "
- ! 			"aligned dma address %Lx\n",
- ! 			val,
- ! 			(unsigned long long)trans_pcie->aligned_ict_tbl_dma);
-   
-   	iwl_write32(bus(trans), CSR_DRAM_INT_TBL_REG, val);
-   	trans_pcie->use_ict = true;
- diff -crN linux-3.2.1_o/drivers/pwm/ecap.c linux-3.2.1/drivers/pwm/ecap.c
- *** linux-3.2.1_o/drivers/pwm/ecap.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/drivers/pwm/ecap.c	2014-05-15 13:25:14.602584518 +0900
- ***************
- *** 0 ****
- --- 1,472 ----
- + /*
- +  * eCAP driver for PWM output generation
- +  *
- +  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed .as is. WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + #include <linux/module.h>
- + #include <linux/kernel.h>
- + #include <linux/platform_device.h>
- + #include <linux/err.h>
- + #include <linux/clk.h>
- + #include <linux/io.h>
- + #include <linux/pwm/pwm.h>
- + #include <linux/slab.h>
- + #include <linux/pm_runtime.h>
- + 
- + #include <plat/clock.h>
- + #include <plat/config_pwm.h>
- + 
- + #define TIMER_CTR_REG			0x0
- + #define CAPTURE_1_REG			0x08
- + #define CAPTURE_2_REG			0x0c
- + #define CAPTURE_3_REG			0x10
- + #define CAPTURE_4_REG			0x14
- + #define CAPTURE_CTRL2_REG		0x2A
- + 
- + #define ECTRL2_SYNCOSEL_MASK		(0x03 << 6)
- + 
- + #define ECTRL2_MDSL_ECAP		BIT(9)
- + #define ECTRL2_CTRSTP_FREERUN		BIT(4)
- + #define ECTRL2_PLSL_LOW			BIT(10)
- + #define ECTRL2_SYNC_EN			BIT(5)
- + 
- + struct ecap_regs {
- + 	unsigned	tsctr;
- + 	unsigned	cap1;
- + 	unsigned	cap2;
- + 	unsigned	cap3;
- + 	unsigned	cap4;
- + 	unsigned short	ecctl2;
- + 	unsigned short	clkconfig;
- + };
- + 
- + struct ecap_pwm {
- + 	struct pwm_device pwm;
- + 	struct pwm_device_ops ops;
- + 	spinlock_t	lock;
- + 	struct clk	*clk;
- + 	void __iomem	*mmio_base;
- + 	u8 version;
- + 	void __iomem *config_mem_base;
- + 	struct device *dev;
- + 	struct ecap_regs ctx;
- + };
- + 
- + static inline struct ecap_pwm *to_ecap_pwm(const struct pwm_device *p)
- + {
- + 	return pwm_get_drvdata(p);
- + }
- + 
- + static int ecap_pwm_stop(struct pwm_device *p)
- + {
- + 	unsigned long flags, v;
- + 	struct ecap_pwm *ep = to_ecap_pwm(p);
- + 
- + 	/* Trying to stop a non-running PWM, not allowed */
- + 	if (!pwm_is_running(p))
- + 		return -EPERM;
- + 
- + 	spin_lock_irqsave(&ep->lock, flags);
- + 	v = readw(ep->mmio_base + CAPTURE_CTRL2_REG);
- + 	v &= ~(ECTRL2_CTRSTP_FREERUN | ECTRL2_MDSL_ECAP);
- + 	writew(v, ep->mmio_base + CAPTURE_CTRL2_REG);
- + 	spin_unlock_irqrestore(&ep->lock, flags);
- + 
- + 	/* For PWM clock should be disabled on stop */
- + 	pm_runtime_put_sync(ep->dev);
- + 	clear_bit(FLAG_RUNNING, &p->flags);
- + 
- + 	return 0;
- + }
- + 
- + static int ecap_pwm_start(struct pwm_device *p)
- + {
- + 	int ret = 0;
- + 	unsigned long flags, v;
- + 	struct ecap_pwm *ep = to_ecap_pwm(p);
- + 
- + 	/* Trying to start a running PWM, not allowed */
- + 	if (pwm_is_running(p))
- + 		return -EPERM;
- + 
- + 	/* For PWM clock should be enabled on start */
- + 	pm_runtime_get_sync(ep->dev);
- + 
- + 	spin_lock_irqsave(&ep->lock, flags);
- + 	v = readw(ep->mmio_base + CAPTURE_CTRL2_REG);
- + 	v |= (ECTRL2_CTRSTP_FREERUN | ECTRL2_MDSL_ECAP);
- + 	writew(v, ep->mmio_base + CAPTURE_CTRL2_REG);
- + 	spin_unlock_irqrestore(&ep->lock, flags);
- + 	set_bit(FLAG_RUNNING, &p->flags);
- + 
- + 	return ret;
- + }
- + 
- + static int ecap_pwm_set_polarity(struct pwm_device *p, char pol)
- + {
- + 	unsigned long flags, v;
- + 	struct ecap_pwm *ep = to_ecap_pwm(p);
- + 
- + 	pm_runtime_get_sync(ep->dev);
- + 
- + 	spin_lock_irqsave(&ep->lock, flags);
- + 	v = readw(ep->mmio_base + CAPTURE_CTRL2_REG);
- + 	v &= ~ECTRL2_PLSL_LOW;
- + 	v |= pol << 10;
- + 	writew(v, ep->mmio_base + CAPTURE_CTRL2_REG);
- + 	spin_unlock_irqrestore(&ep->lock, flags);
- + 
- + 	pm_runtime_put_sync(ep->dev);
- + 	return 0;
- + }
- + 
- + static int ecap_pwm_config_period(struct pwm_device *p)
- + {
- + 	unsigned long flags;
- + 	struct ecap_pwm *ep = to_ecap_pwm(p);
- + 
- + 	 pm_runtime_get_sync(ep->dev);
- + 
- + 	spin_lock_irqsave(&ep->lock, flags);
- + 	writel((p->period_ticks) - 1, ep->mmio_base + CAPTURE_3_REG);
- + 	spin_unlock_irqrestore(&ep->lock, flags);
- + 
- + 	pm_runtime_put_sync(ep->dev);
- + 	return 0;
- + }
- + 
- + static int ecap_pwm_config_duty(struct pwm_device *p)
- + {
- + 	unsigned long flags, v;
- + 	struct ecap_pwm *ep = to_ecap_pwm(p);
- + 
- + 	pm_runtime_get_sync(ep->dev);
- + 
- + 	spin_lock_irqsave(&ep->lock, flags);
- + 	v = readw(ep->mmio_base + CAPTURE_CTRL2_REG);
- + 	v |= (ECTRL2_MDSL_ECAP | ECTRL2_SYNCOSEL_MASK);
- + 	writew(v, ep->mmio_base + CAPTURE_CTRL2_REG);
- + 
- + 	if (p->duty_ticks > 0) {
- + 		writel(p->duty_ticks, ep->mmio_base + CAPTURE_4_REG);
- + 	} else {
- + 		writel(p->duty_ticks, ep->mmio_base + CAPTURE_2_REG);
- + 		writel(0, ep->mmio_base + TIMER_CTR_REG);
- + 	}
- + 	spin_unlock_irqrestore(&ep->lock, flags);
- + 
- + 	if (!pwm_is_running(p)) {
- + 		v = readw(ep->mmio_base + CAPTURE_CTRL2_REG);
- + 		v &= ~ECTRL2_MDSL_ECAP;
- + 		writew(v, ep->mmio_base + CAPTURE_CTRL2_REG);
- + 	}
- + 
- + 	pm_runtime_put_sync(ep->dev);
- + 	return 0;
- + }
- + 
- + static int ecap_pwm_config(struct pwm_device *p,
- + 				struct pwm_config *c)
- + {
- + 	int ret = 0;
- + 	switch (c->config_mask) {
- + 
- + 	case BIT(PWM_CONFIG_DUTY_TICKS):
- + 		p->duty_ticks = c->duty_ticks;
- + 		ret = ecap_pwm_config_duty(p);
- + 		break;
- + 
- + 	case BIT(PWM_CONFIG_PERIOD_TICKS):
- + 		p->period_ticks = c->period_ticks;
- + 		ret = ecap_pwm_config_period(p);
- + 		break;
- + 
- + 	case BIT(PWM_CONFIG_POLARITY):
- + 		p->active_high = c->polarity;
- + 		ret = ecap_pwm_set_polarity(p, c->polarity);
- + 		break;
- + 
- + 	case BIT(PWM_CONFIG_START):
- + 		ret = ecap_pwm_start(p);
- + 		break;
- + 
- + 	case BIT(PWM_CONFIG_STOP):
- + 		ret = ecap_pwm_stop(p);
- + 		break;
- + 	}
- + 
- + 	return ret;
- + }
- + 
- + static int ecap_pwm_request(struct pwm_device *p)
- + {
- + 	struct ecap_pwm *ep = to_ecap_pwm(p);
- + 
- + 	p->tick_hz = clk_get_rate(ep->clk);
- + 	return 0;
- + }
- + 
- + static int ecap_frequency_transition_cb(struct pwm_device *p)
- + {
- + 	struct ecap_pwm *ep = to_ecap_pwm(p);
- + 	unsigned long duty_ns, rate;
- + 
- + 	rate = clk_get_rate(ep->clk);
- + 	if (rate == p->tick_hz)
- + 		return 0;
- + 	p->tick_hz = rate;
- + 
- + 	duty_ns = p->duty_ns;
- + 	if (pwm_is_running(p)) {
- + 		pwm_stop(p);
- + 		pwm_set_duty_ns(p, 0);
- + 		pwm_set_period_ns(p, p->period_ns);
- + 		pwm_set_duty_ns(p, duty_ns);
- + 		pwm_start(p);
- + 	} else {
- + 		pwm_set_duty_ns(p, 0);
- + 		pwm_set_period_ns(p, p->period_ns);
- + 		pwm_set_duty_ns(p, duty_ns);
- + 	}
- + 		return 0;
- + }
- + 
- + static int ecap_probe(struct platform_device *pdev)
- + {
- + 	struct ecap_pwm *ep = NULL;
- + 	struct resource *r;
- + 	int ret = 0;
- + 	int val;
- + 	char con_id[PWM_CON_ID_STRING_LENGTH] = "epwmss";
- + 	struct pwmss_platform_data *pdata = (&pdev->dev)->platform_data;
- + 
- + 	ep = kzalloc(sizeof(*ep), GFP_KERNEL);
- + 
- + 	if (!ep) {
- + 		dev_err(&pdev->dev, "failed to allocate memory\n");
- + 		return -ENOMEM;
- + 	}
- + 
- + 	ep->version = pdata->version;
- + 
- + 	if (ep->version == PWM_VERSION_1) {
- + 		sprintf(con_id, "%s%d_%s", con_id, pdev->id, "fck");
- + 		ep->clk = clk_get(&pdev->dev, con_id);
- + 	} else
- + 		ep->clk = clk_get(&pdev->dev, "ecap");
- + 
- + 	pm_runtime_enable(&pdev->dev);
- + 	ep->dev = &pdev->dev;
- + 	if (IS_ERR(ep->clk)) {
- + 		ret = PTR_ERR(ep->clk);
- + 		goto err_clk_get;
- + 	}
- + 
- + 	if (ep->version == PWM_VERSION_1) {
- + 		r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- + 
- + 		if (!r) {
- + 			dev_err(&pdev->dev, "no memory resource defined\n");
- + 			ret = -ENOMEM;
- + 			goto err_get_resource;
- + 		}
- + 
- + 		ep->config_mem_base = ioremap(r->start, resource_size(r));
- + 
- + 		if (!ep->config_mem_base) {
- + 
- + 			dev_err(&pdev->dev, "failed to ioremap() registers\n");
- + 			ret = -ENOMEM;
- + 			goto err_get_resource;
- + 		}
- + 
- + 		pm_runtime_get_sync(ep->dev);
- + 		val = readw(ep->config_mem_base + PWMSS_CLKCONFIG);
- + 		val |= BIT(ECAP_CLK_EN);
- + 		writew(val, ep->config_mem_base + PWMSS_CLKCONFIG);
- + 		pm_runtime_put_sync(ep->dev);
- + 	}
- + 
- + 	spin_lock_init(&ep->lock);
- + 	ep->ops.config = ecap_pwm_config;
- + 	ep->ops.request = ecap_pwm_request;
- + 	ep->ops.freq_transition_notifier_cb = ecap_frequency_transition_cb;
- + 
- + 	if (ep->version == PWM_VERSION_1)
- + 		r = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- + 	else
- + 		r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- + 
- + 	if (!r) {
- + 		dev_err(&pdev->dev, "no memory resource defined\n");
- + 		ret = -ENODEV;
- + 		goto err_request_mem;
- + 	}
- + 
- + 	r = request_mem_region(r->start, resource_size(r), pdev->name);
- + 	if (!r) {
- + 		dev_err(&pdev->dev, "failed to request memory resource\n");
- + 		ret = -EBUSY;
- + 		goto err_request_mem;
- + 	}
- + 
- + 	ep->mmio_base = ioremap(r->start, resource_size(r));
- + 	if (!ep->mmio_base) {
- + 		dev_err(&pdev->dev, "failed to ioremap() registers\n");
- + 		ret = -ENODEV;
- + 		goto err_ioremap;
- + 	}
- + 
- + 	ep->pwm.ops = &ep->ops;
- + 	pwm_set_drvdata(&ep->pwm, ep);
- + 	ret =  pwm_register(&ep->pwm, &pdev->dev, -1);
- + 	platform_set_drvdata(pdev, ep);
- + 	/* Inverse the polarity of PWM wave */
- + 	if (pdata->chan_attrib[0].inverse_pol) {
- + 		ep->pwm.active_high = 1;
- + 		ecap_pwm_set_polarity(&ep->pwm, 1);
- + 	}
- + 	return 0;
- + 
- + err_ioremap:
- + 	release_mem_region(r->start, resource_size(r));
- + err_request_mem:
- + 	if (ep->version == PWM_VERSION_1) {
- + 		iounmap(ep->config_mem_base);
- + 		ep->config_mem_base = NULL;
- + 	}
- + err_get_resource:
- + 	clk_put(ep->clk);
- + 	pm_runtime_disable(&pdev->dev);
- + err_clk_get:
- + 	kfree(ep);
- + 	return ret;
- + }
- + 
- + #ifdef CONFIG_PM
- + 
- + void ecap_save_reg(struct ecap_pwm *ep)
- + {
- + 	pm_runtime_get_sync(ep->dev);
- + 
- + 	ep->ctx.ecctl2 = readw(ep->mmio_base + CAPTURE_CTRL2_REG);
- + 	ep->ctx.tsctr = readl(ep->mmio_base + TIMER_CTR_REG);
- + 	ep->ctx.cap1 = readl(ep->mmio_base + CAPTURE_1_REG);
- + 	ep->ctx.cap2 = readl(ep->mmio_base + CAPTURE_2_REG);
- + 	ep->ctx.cap4 = readl(ep->mmio_base + CAPTURE_4_REG);
- + 	ep->ctx.cap3 = readl(ep->mmio_base + CAPTURE_3_REG);
- + 
- + 	ep->ctx.clkconfig = readw(ep->config_mem_base + PWMSS_CLKCONFIG);
- + 
- + 	pm_runtime_put_sync(ep->dev);
- + }
- + 
- + void ecap_restore_reg(struct ecap_pwm *ep)
- + {
- + 	writew(ep->ctx.clkconfig, ep->config_mem_base + PWMSS_CLKCONFIG);
- + 
- + 	writel(ep->ctx.cap3, ep->mmio_base + CAPTURE_3_REG);
- + 	writel(ep->ctx.cap4, ep->mmio_base + CAPTURE_4_REG);
- + 	writel(ep->ctx.cap2, ep->mmio_base + CAPTURE_2_REG);
- + 	writel(ep->ctx.cap1, ep->mmio_base + CAPTURE_1_REG);
- + 	writel(ep->ctx.tsctr, ep->mmio_base + TIMER_CTR_REG);
- + 	writew(ep->ctx.ecctl2, ep->mmio_base + CAPTURE_CTRL2_REG);
- + }
- + 
- + static int ecap_suspend(struct platform_device *pdev, pm_message_t state)
- + {
- + 	struct ecap_pwm *ep = platform_get_drvdata(pdev);
- + 
- + 	ecap_save_reg(ep);
- + 	pm_runtime_put_sync(ep->dev);
- + 
- + 	return 0;
- + }
- + 
- + static int ecap_resume(struct platform_device *pdev)
- + {
- + 	struct ecap_pwm *ep = platform_get_drvdata(pdev);
- + 
- + 	pm_runtime_get_sync(ep->dev);
- + 
- + 	ecap_restore_reg(ep);
- + 
- + 	return 0;
- + }
- + 
- + #else
- + #define ecap_suspend NULL
- + #define ecap_resume NULL
- + #endif
- + 
- + static int __devexit ecap_remove(struct platform_device *pdev)
- + {
- + 	struct ecap_pwm *ep = platform_get_drvdata(pdev);
- + 	struct resource *r;
- + 	struct pwmss_platform_data *pdata;
- + 	int val;
- + 
- + 	if (ep->version == PWM_VERSION_1) {
- + 		pdata = (&pdev->dev)->platform_data;
- + 		pm_runtime_get_sync(ep->dev);
- + 		val = readw(ep->config_mem_base + PWMSS_CLKCONFIG);
- + 		val &= ~BIT(ECAP_CLK_EN);
- + 		writew(val, ep->config_mem_base + PWMSS_CLKCONFIG);
- + 		pm_runtime_put_sync(ep->dev);
- + 		iounmap(ep->config_mem_base);
- + 		ep->config_mem_base = NULL;
- + 	}
- + 
- + 	pwm_unregister(&ep->pwm);
- + 	iounmap(ep->mmio_base);
- + 
- + 	if (ep->version == PWM_VERSION_1)
- + 		r = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- + 	else
- + 		r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- + 	release_mem_region(r->start, resource_size(r));
- + 	platform_set_drvdata(pdev, NULL);
- + 	clk_put(ep->clk);
- + 	pm_runtime_disable(&pdev->dev);
- + 	kfree(ep);
- + 
- + 	return 0;
- + }
- + 
- + static struct platform_driver ecap_driver = {
- + 	.driver	= {
- + 		.name	= "ecap",
- + 		.owner	= THIS_MODULE,
- + 	},
- + 	.probe		= ecap_probe,
- + 	.remove		= __devexit_p(ecap_remove),
- + 	.suspend	= ecap_suspend,
- + 	.resume		= ecap_resume,
- + };
- + 
- + static int __init ecap_init(void)
- + {
- + 	return platform_driver_register(&ecap_driver);
- + }
- + 
- + static void __exit ecap_exit(void)
- + {
- + 	platform_driver_unregister(&ecap_driver);
- + }
- + 
- + module_init(ecap_init);
- + module_exit(ecap_exit);
- + 
- + MODULE_AUTHOR("Texas Instruments");
- + MODULE_DESCRIPTION("Driver for Davinci eCAP peripheral");
- + MODULE_LICENSE("GPL v2");
- + MODULE_ALIAS("platform:ecap");
- diff -crN linux-3.2.1_o/drivers/pwm/ehrpwm.c linux-3.2.1/drivers/pwm/ehrpwm.c
- *** linux-3.2.1_o/drivers/pwm/ehrpwm.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/drivers/pwm/ehrpwm.c	2014-05-15 13:25:14.602584518 +0900
- ***************
- *** 0 ****
- --- 1,1646 ----
- + /*
- +  * eHRPWM driver for simple PWM output generation
- +  *
- +  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed .as is. WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + #include <linux/module.h>
- + #include <linux/init.h>
- + #include <linux/clk.h>
- + #include <linux/err.h>
- + #include <linux/io.h>
- + #include <linux/interrupt.h>
- + #include <linux/platform_device.h>
- + #include <linux/slab.h>
- + #include <linux/pwm/pwm.h>
- + #include <linux/pwm/ehrpwm.h>
- + #include <linux/pm_runtime.h>
- + 
- + #include <plat/clock.h>
- + #include <plat/config_pwm.h>
- + 
- + #ifdef DEBUG
- + #define debug(format, args...) printk(format, ##args)
- + #else
- + #define debug(format, args...) { }
- + #endif
- + 
- + /******************** Time base sub module*****************************/
- + #define TBCTL				0x0
- + #define TBSTS				0x2
- + #define TBPHS				0x6
- + #define TBCTR				0x8
- + #define TBPRD				0xA
- + 
- + #define TBCTL_CLKDIV_MASK		(BIT(12) | BIT(11) | BIT(10))
- + #define TBCTL_HSPCLKDIV_MASK		(BIT(9) | BIT(8) | BIT(7))
- + #define TBCTL_SYNCOSEL_MASK		(BIT(5) | BIT(4))
- + #define TBCTL_CTRMODE_MASK		(BIT(1) | BIT(0))
- + 
- + #define	TBCTL_CLKDIV_POS		0xA
- + #define TBCTL_HSPCLKDIV_POS		0x7
- + #define TBCTL_PHSEN_POS			0x2
- + #define TBCTL_SYNCOSEL_POS		0x4
- + #define TBCTL_PHSDIR_POS		0xD
- + #define TBCTL_FRC_SYC_POS		0x6
- + #define TBCTL_LOAD_MD_POS		0x3
- + 
- + #define TBCTL_FREERUN_FREE		0x2
- + #define TBCTL_CTRMOD_CTRUP		0x0
- + 
- + /******************* Counter-Compare Sub Module ***********************/
- + #define CMPCTL				0xE
- + #define CMPA				0x12
- + #define CMPB				0x14
- + 
- + #define CMPCTL_LDBMODE_MASK		(BIT(3) | BIT(2))
- + #define CMPCTL_LDAMODE_MASK		(BIT(1) | BIT(0))
- + 
- + #define CMPCTL_SHDAMODE_POS		0x4
- + #define CMPCTL_SHDBMODE_POS		0x6
- + #define CMPCTL_LDBMODE_POS		0x2
- + 
- + /*********************** Action Control Sub module ********************/
- + #define AQCTLA				0x16
- + #define AQCTLB				0x18
- + #define AQSFRC				0x1A
- + #define AQCSFRC				0x1c
- + 
- + #define ACTCTL_CBD_MASK			(BIT(11) | BIT(10))
- + #define ACTCTL_CBU_MASK			(BIT(9) | BIT(8))
- + #define ACTCTL_CAD_MASK			(BIT(7) | BIT(6))
- + #define ACTCTL_CAU_MASK			(BIT(5) | BIT(4))
- + #define ACTCTL_CPRD_MASK		(BIT(3) | BIT(2))
- + #define ACTCTL_CZRO_MASK		(BIT(1) | BIT(0))
- + 
- + #define ACTCTL_CTREQPRD_POS		0x2
- + #define ACTCTL_CTREQCMPAUP_POS		0x4
- + #define ACTCTL_CTREQCMPADN_POS		0x6
- + #define ACTCTL_CTREQCMPBUP_POS		0x8
- + #define ACTCTL_CTREQCMPBDN_POS		0xA
- + 
- + #define ACTCTL_CTREQCMP_LOW		0x1
- + #define ACTCTL_CTREQCMP_HIGH		0x2
- + #define ACTCTL_CTREQZRO_LOW		0x1
- + #define ACTCTL_CTREQZRO_HIGH		0x2
- + 
- + #define AQSFRC_ACTA_MASK		(BIT(1) | BIT(0))
- + #define AQSFRC_ACTB_MASK		(BIT(4) | BIT(3))
- + 
- + #define AQSFRC_ACTB_POS			0x3
- + #define AQSFRC_OTFRCA_POS		0x2
- + #define AQSFRC_OTFRCB_POS		0x5
- + 
- + #define AQSFRC_RLDCSF_ZRO		0
- + #define AQSFRC_RLDCSF_IMDT		(BIT(1) | BIT(0))
- + #define AQSFRC_LDMD_POS			0x6
- + #define AQSFRC_CFRC_LOAD_MASK		(BIT(7) | BIT(6))
- + 
- + #define AQCSFRC_CSF_FRCDIS		0
- + #define AQCSFRC_CSF_FRCLOW		BIT(0)
- + #define AQCSFRC_OUTB_MASK		(BIT(3) | BIT(2))
- + #define AQCSFRC_OUTA_MASK		(BIT(1) | BIT(0))
- + #define AQCSFRC_OUTB_POS		0x2
- + 
- + /******************** Dead Band Generator Sub module *******************/
- + #define DBCTL				0x1E
- + #define DBRED				0x20
- + #define DBFED				0x22
- + 
- + #define DBCTL_INMODE_MASK		(BIT(5) | BIT(4))
- + #define DBCTL_PLSEL_MASK		(BIT(3) | BIT(2))
- + #define DBCTL_OUTMODE_MASK		(BIT(1) | BIT(0))
- + 
- + #define DBCTL_INMODE_POS		0x4
- + #define DBCTL_POLSEL_POS		0x2
- + 
- + /********************** PWM Chopper Sub module ************************/
- + #define PCCTL				0x3C
- + 
- + #define PCCTL_CHPDUTY_MASK		(BIT(10) | BIT(9) | BIT(8))
- + #define PCCTL_CHPFREQ_MASK		(BIT(7) | BIT(6) | BIT(5))
- + #define PCCTL_OSHTWTH_MASK		(BIT(4) | BIT(3) | BIT(2) | BIT(1))
- + 
- + #define PCCTL_CHPDUTY_POS		0x8
- + #define PCCTL_CHPFRQ_POS		0x5
- + #define PCCTL_OSTWID_POS		0x1
- + 
- + /*************************Trip-zone submodule **************************/
- + #define TZSEL				0x24
- + #define TZCTL				0x28
- + #define TZEINT				0x2A
- + #define TZFLG				0x2C
- + #define TZCLR				0x2E
- + #define TZFRC				0x30
- + 
- + #define TZCTL_ACTA_MASK			(BIT(1) | BIT(0))
- + #define TZCTL_ACTB_MASK			(BIT(3) | BIT(2))
- + 
- + #define TZCTL_ACTB_POS			0x2
- + 
- + #define TZEINT_OSHTEVT_POS		0x2
- + #define TZEINT_CBCEVT_POS		0x1
- + 
- + /*************************Event-Trigger submodule registers**************/
- + #define ETSEL				0x32
- + #define ETPS				0x34
- + #define ETFLG				0x36
- + #define ETCLR				0x38
- + #define ETFRC				0x3A
- + 
- + #define ETSEL_INTSEL_MASK		(BIT(2) | BIT(1) | BIT(0))
- + #define ETPS_INTCNT_MASK		(BIT(3) | BIT(2))
- + #define ETPS_INTPRD_MASK		(BIT(1) | BIT(0))
- + 
- + #define ETSEL_EN_INT_EN_POS		0x3
- + 
- + /**********************High Resolution Registers ********************/
- + #define TBPHSHR				0x4
- + #define CMPAHR				0x10
- + #define HRCNFG				0x1040
- + 
- + #define AM335X_HRCNFG			0x40
- + 
- + #define HRCNFG_EDGEMD_MASK		(BIT(1) | BIT(0))
- + #define HRCNFG_LDMD_POS			0x3
- + #define HRCNFG_CTLMD_POS		0x2
- + 
- + struct ehrpwm_suspend_params {
- + 	struct pwm_device *pch;
- + 	unsigned long req_delay_cycles;
- + 	unsigned long act_delay;
- + } ehrpwm_suspend_params;
- + 
- + static inline unsigned short ehrpwm_read(struct ehrpwm_pwm *ehrpwm,
- + 	unsigned int offset)
- + {
- + 	return readw(ehrpwm->mmio_base + offset);
- + }
- + 
- + static inline void ehrpwm_write(struct ehrpwm_pwm *ehrpwm, unsigned int offset,
- + 	unsigned short val)
- + {
- + 	writew(val, ehrpwm->mmio_base + offset);
- + }
- + 
- + static void ehrpwm_reg_config(struct ehrpwm_pwm *ehrpwm, unsigned int offset,
- + 	       unsigned short val, unsigned short mask)
- + {
- + 	unsigned short read_val;
- + 
- + 	read_val = ehrpwm_read(ehrpwm, offset);
- + 	read_val = read_val & ~mask;
- + 	read_val = read_val | val;
- + 	ehrpwm_write(ehrpwm, offset, read_val);
- + }
- + 
- + static inline struct ehrpwm_pwm *to_ehrpwm_pwm(const struct pwm_device *p)
- + {
- + 	return pwm_get_drvdata(p);
- + }
- + 
- + /* Time Base Module Configurations */
- + int ehrpwm_tb_set_prescalar_val(struct pwm_device *p, unsigned char clkdiv,
- + 	unsigned char hspclkdiv)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 
- + 	if (clkdiv > 0x7 || hspclkdiv > 0x7)
- + 		return -EINVAL;
- + 
- + 	ehrpwm_reg_config(ehrpwm, TBCTL, clkdiv << TBCTL_CLKDIV_POS,
- + 		       TBCTL_CLKDIV_MASK);
- + 	ehrpwm_reg_config(ehrpwm, TBCTL, hspclkdiv << TBCTL_HSPCLKDIV_POS,
- + 		       TBCTL_HSPCLKDIV_MASK);
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_tb_set_prescalar_val);
- + 
- + int ehrpwm_tb_config_sync(struct pwm_device *p, unsigned char phsen,
- + 	unsigned char syncosel)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 
- + 	if (phsen > 1 || syncosel > 0x3)
- + 		return -EINVAL;
- + 
- + 	ehrpwm_reg_config(ehrpwm, TBCTL, phsen << TBCTL_PHSEN_POS, BIT(2));
- + 	ehrpwm_reg_config(ehrpwm, TBCTL, syncosel << TBCTL_SYNCOSEL_POS,
- + 		       TBCTL_SYNCOSEL_MASK);
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_tb_config_sync);
- + 
- + int ehrpwm_tb_set_counter_mode(struct pwm_device *p, unsigned char ctrmode,
- + 	       unsigned char phsdir)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 
- + 	if (ctrmode > 0x3 || phsdir > 1)
- + 		return -EINVAL;
- + 
- + 	ehrpwm_reg_config(ehrpwm, TBCTL, phsdir << TBCTL_PHSDIR_POS, BIT(13));
- + 	ehrpwm_reg_config(ehrpwm, TBCTL, ctrmode, TBCTL_CTRMODE_MASK);
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_tb_set_counter_mode);
- + 
- + int ehrpwm_tb_force_sync(struct pwm_device *p)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 
- + 	ehrpwm_reg_config(ehrpwm, TBCTL, ENABLE << TBCTL_FRC_SYC_POS, BIT(6));
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_tb_force_sync);
- + 
- + int ehrpwm_tb_set_periodload(struct pwm_device *p, unsigned char loadmode)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 
- + 	if (loadmode > 0x1)
- + 		return -EINVAL;
- + 
- + 	ehrpwm_reg_config(ehrpwm, TBCTL, loadmode << TBCTL_LOAD_MD_POS, BIT(3));
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_tb_set_periodload);
- + 
- + int ehrpwm_tb_read_status(struct pwm_device *p, unsigned short *val)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 
- + 	*val = ehrpwm_read(ehrpwm, TBSTS);
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_tb_read_status);
- + 
- + int ehrpwm_tb_read_counter(struct pwm_device *p, unsigned short *val)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 
- + 	*val = ehrpwm_read(ehrpwm, TBCTR);
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_tb_read_counter);
- + 
- + int ehrpwm_tb_set_period(struct pwm_device *p,	unsigned short val)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 
- + 	ehrpwm_write(ehrpwm, TBPRD, val);
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_tb_set_period);
- + 
- + int ehrpwm_tb_set_phase(struct pwm_device *p, unsigned short val)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 
- + 	ehrpwm_write(ehrpwm, TBPHS, val);
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_tb_set_phase);
- + 
- + int ehrpwm_cmp_set_cmp_ctl(struct pwm_device *p, unsigned char shdwamode,
- + 	unsigned char shdwbmode, unsigned char loadamode,
- + 	unsigned char loadbmode)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 
- + 	if (shdwamode > 0x1 || shdwbmode > 0x1 || loadamode > 0x3 ||
- + 		loadbmode > 0x3)
- + 		return -EINVAL;
- + 
- + 	ehrpwm_reg_config(ehrpwm, CMPCTL, shdwamode << CMPCTL_SHDAMODE_POS,
- + 		       BIT(4));
- + 	ehrpwm_reg_config(ehrpwm, CMPCTL, shdwbmode << CMPCTL_SHDBMODE_POS,
- + 		       BIT(6));
- + 	ehrpwm_reg_config(ehrpwm, CMPCTL, loadamode, CMPCTL_LDAMODE_MASK);
- + 	ehrpwm_reg_config(ehrpwm, CMPCTL, loadbmode << CMPCTL_LDBMODE_POS,
- + 		       CMPCTL_LDBMODE_MASK);
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_cmp_set_cmp_ctl);
- + 
- + int ehrpwm_cmp_set_cmp_val(struct pwm_device *p, unsigned char reg,
- + 	unsigned short val)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 	unsigned char offset;
- + 
- + 	if (reg > 0x1)
- + 		return -EINVAL;
- + 
- + 	if (reg == 0)
- + 		offset = CMPA;
- + 	else
- + 		offset = CMPB;
- + 
- + 	ehrpwm_write(ehrpwm, offset, val);
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_cmp_set_cmp_val);
- + 
- + int ehrpwm_aq_set_act_ctrl(struct pwm_device *p, struct aq_config_params *cfg)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 	unsigned char reg;
- + 
- + 	if (!cfg)
- + 		return -EINVAL;
- + 
- + 	if (cfg->ch > 1 || cfg->ctreqzro > 3 || cfg->ctreqprd > 3 ||
- + 		cfg->ctreqcmpaup > 3 || cfg->ctreqcmpadown > 3 ||
- + 		cfg->ctreqcmpbup > 3 || cfg->ctreqcmpbdown > 3)
- + 		return -EINVAL;
- + 
- + 	if (cfg->ch == 0)
- + 		reg = AQCTLA;
- + 	else
- + 		reg = AQCTLB;
- + 
- + 	ehrpwm_reg_config(ehrpwm, reg, cfg->ctreqzro, ACTCTL_CZRO_MASK);
- + 	ehrpwm_reg_config(ehrpwm, reg, cfg->ctreqprd << ACTCTL_CTREQPRD_POS,
- + 		       ACTCTL_CPRD_MASK);
- + 	ehrpwm_reg_config(ehrpwm, reg, cfg->ctreqcmpaup <<
- + 		       ACTCTL_CTREQCMPAUP_POS, ACTCTL_CAU_MASK);
- + 	ehrpwm_reg_config(ehrpwm, reg, cfg->ctreqcmpadown <<
- + 		       ACTCTL_CTREQCMPADN_POS, ACTCTL_CAD_MASK);
- + 	ehrpwm_reg_config(ehrpwm, reg, cfg->ctreqcmpbup <<
- + 		       ACTCTL_CTREQCMPBUP_POS, ACTCTL_CBU_MASK);
- + 	ehrpwm_reg_config(ehrpwm, reg, cfg->ctreqcmpbdown <<
- + 		       ACTCTL_CTREQCMPBDN_POS, ACTCTL_CBD_MASK);
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_aq_set_act_ctrl);
- + 
- + int ehrpwm_aq_set_one_shot_act(struct pwm_device  *p, unsigned char ch,
- + 	unsigned char act)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 
- + 	if (ch > 1 || act > 3)
- + 		return -EINVAL;
- + 
- + 	if (ch == 0)
- + 		ehrpwm_reg_config(ehrpwm, AQSFRC, act, AQSFRC_ACTA_MASK);
- + 	else
- + 		ehrpwm_reg_config(ehrpwm, AQSFRC, act << AQSFRC_ACTB_POS,
- + 			       AQSFRC_ACTB_MASK);
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_aq_set_one_shot_act);
- + 
- + int ehrpwm_aq_ot_frc(struct pwm_device *p, unsigned char ch)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 
- + 	if (ch > 1)
- + 		return -EINVAL;
- + 
- + 	if (ch == 0)
- + 		ehrpwm_reg_config(ehrpwm, AQSFRC, ENABLE << AQSFRC_OTFRCA_POS,
- + 			       BIT(2));
- + 	else
- + 		ehrpwm_reg_config(ehrpwm, AQSFRC, ENABLE << AQSFRC_OTFRCB_POS,
- + 			       BIT(5));
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_aq_ot_frc);
- + 
- + int ehrpwm_aq_set_csfrc_load_mode(struct pwm_device *p, unsigned char loadmode)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 
- + 	if (loadmode > 0x3)
- + 		return -EINVAL;
- + 
- + 	ehrpwm_reg_config(ehrpwm, AQSFRC, loadmode << AQSFRC_LDMD_POS,
- + 		       AQSFRC_CFRC_LOAD_MASK);
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_aq_set_csfrc_load_mode);
- + 
- + int ehrpwm_aq_continuous_frc(struct pwm_device *p, unsigned char ch,
- + 	unsigned char act)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 
- + 	if (ch > 1)
- + 		return -EINVAL;
- + 
- + 	if (ch == 0)
- + 		ehrpwm_reg_config(ehrpwm, AQCSFRC, act, AQCSFRC_OUTA_MASK);
- + 	else
- + 		ehrpwm_reg_config(ehrpwm, AQCSFRC, act << AQCSFRC_OUTB_POS,
- + 			       AQCSFRC_OUTB_MASK);
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_aq_continuous_frc);
- + 
- + int ehrpwm_db_get_max_delay(struct pwm_device *p, enum config_mask cfgmask,
- + 	unsigned long *delay_val)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 	unsigned long delay_ns;
- + 	unsigned long max_ticks;
- + 
- + 	if (cfgmask == CONFIG_NS) {
- + 		max_ticks = 0x3ff * ehrpwm->prescale_val;
- + 		delay_ns = pwm_ticks_to_ns(p, max_ticks);
- + 		*delay_val = delay_ns;
- + 	} else if (cfgmask == CONFIG_TICKS) {
- + 		*delay_val = 0x3ff * ehrpwm->prescale_val;
- + 	} else {
- + 		return -EINVAL;
- + 	}
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_db_get_max_delay);
- + 
- + int ehrpwm_db_get_delay(struct pwm_device *p, unsigned char edge,
- + 	enum config_mask cfgmask, unsigned long *delay_val)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 	unsigned long delay_ns;
- + 	unsigned long delay_ticks;
- + 	unsigned char offset;
- + 
- + 	if (!ehrpwm)
- + 		return -EINVAL;
- + 
- + 	if (edge == RISING_EDGE_DELAY)
- + 		offset = DBRED;
- + 	else if (edge == FALLING_EDGE_DELAY)
- + 		offset = DBFED;
- + 	else
- + 		return -EINVAL;
- + 
- + 	delay_ticks = ehrpwm_read(ehrpwm, offset);
- + 	/* Only least 10 bits are required */
- + 	delay_ticks = delay_ticks & 0x3ff;
- + 	if (cfgmask == CONFIG_TICKS) {
- + 		*delay_val = delay_ticks * ehrpwm->prescale_val;
- + 	} else if (cfgmask == CONFIG_NS) {
- + 		delay_ticks = delay_ticks * ehrpwm->prescale_val;
- + 		delay_ns = pwm_ticks_to_ns(p, delay_ticks);
- + 		debug("\n delay ns value is %lu", delay_ns);
- + 		*delay_val = delay_ns;
- + 	} else {
- + 		return -EINVAL;
- + 	}
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_db_get_delay);
- + 
- + int ehrpwm_db_set_delay(struct pwm_device *p, unsigned char edge,
- + 		enum config_mask cfgmask, unsigned long delay)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 	unsigned long delay_ticks;
- + 	unsigned char offset = 0;
- + 
- + 	if (!ehrpwm)
- + 		return -EINVAL;
- + 
- + 	if (edge == RISING_EDGE_DELAY)
- + 		offset = DBRED;
- + 	else if (edge == FALLING_EDGE_DELAY)
- + 		offset = DBFED;
- + 	else
- + 		return -EINVAL;
- + 
- + 	if (cfgmask == CONFIG_TICKS) {
- + 		delay = delay / ehrpwm->prescale_val;
- + 		if (delay > 0x3ff)
- + 			return -EINVAL;
- + 		ehrpwm_write(ehrpwm, offset, delay);
- + 	} else if (cfgmask == CONFIG_NS) {
- + 		delay_ticks = pwm_ns_to_ticks(p, delay);
- + 		delay_ticks = delay_ticks / ehrpwm->prescale_val;
- + 		if (delay_ticks > 0x3ff) {
- + 			ehrpwm_db_get_max_delay(p, CONFIG_NS, &delay_ticks);
- + 			dev_dbg(p->dev, "%s: Expected delay cannot be"
- + 			" attained setting the maximum possible delay of"
- + 			" %lu ns", __func__, delay_ticks);
- + 			delay_ticks = 0x3ff;
- + 		}
- + 		debug("\n delay ticks is %lu", delay_ticks);
- + 		ehrpwm_write(ehrpwm, offset, delay_ticks);
- + 	} else {
- + 		return -EINVAL;
- + 	}
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_db_set_delay);
- + 
- + /* Dead Band Configuration functions */
- + int ehrpwm_db_set_mode(struct pwm_device *p, unsigned char inmode,
- + 		unsigned char polsel, unsigned char outmode)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 
- + 	if (inmode > 0x3 || polsel > 0x3 || outmode > 0x3)
- + 		return -EINVAL;
- + 
- + 	ehrpwm_reg_config(ehrpwm, DBCTL, inmode << DBCTL_INMODE_POS,
- + 		       DBCTL_INMODE_MASK);
- + 	ehrpwm_reg_config(ehrpwm, DBCTL, polsel << DBCTL_POLSEL_POS,
- + 		       DBCTL_PLSEL_MASK);
- + 	ehrpwm_reg_config(ehrpwm, DBCTL, outmode, DBCTL_OUTMODE_MASK);
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_db_set_mode);
- + 
- + /* PWM chopper Configuration functions */
- + int ehrpwm_pc_configure(struct pwm_device *p, unsigned char chpduty,
- + 		unsigned char chpfreq, unsigned char oshtwidth)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 
- + 	if (chpduty > 0x7 || chpfreq > 0x7 || oshtwidth > 0xf)
- + 		return -EINVAL;
- + 
- + 	ehrpwm_reg_config(ehrpwm, PCCTL, chpduty << PCCTL_CHPDUTY_POS,
- + 		       PCCTL_CHPDUTY_MASK);
- + 	ehrpwm_reg_config(ehrpwm, PCCTL, chpfreq << PCCTL_CHPFRQ_POS,
- + 		       PCCTL_CHPFREQ_MASK);
- + 	ehrpwm_reg_config(ehrpwm, PCCTL, oshtwidth << PCCTL_OSTWID_POS,
- + 		       PCCTL_OSHTWTH_MASK);
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_pc_configure);
- + 
- + int ehrpwm_pc_en_dis(struct pwm_device *p, unsigned char chpen)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 
- + 	if (chpen > 1)
- + 		return -EINVAL;
- + 
- + 	ehrpwm_reg_config(ehrpwm, PCCTL, chpen, BIT(0));
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_pc_en_dis);
- + 
- + /* Trip Zone configuration functions */
- + int ehrpwm_tz_sel_event(struct pwm_device *p, unsigned char input,
- + 	       enum tz_event evt)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 
- + 	unsigned short val = 0;
- + 	unsigned short mask;
- + 	unsigned short pos;
- + 
- + 	if (evt > 4 || input > 7)
- + 		return -EINVAL;
- + 
- + 	switch (evt) {
- + 	case TZ_ONE_SHOT_EVENT:
- + 		pos = input + 8;
- + 		mask = BIT((pos)) | BIT(input);
- + 		ehrpwm_reg_config(ehrpwm, TZSEL, 1 << pos, mask);
- + 		break;
- + 
- + 	case TZ_CYCLE_BY_CYCLE:
- + 		pos = input;
- + 		mask = BIT(pos) | BIT((pos + 8));
- + 		ehrpwm_reg_config(ehrpwm, TZSEL, 1 << pos, mask);
- + 		break;
- + 
- + 	case TZ_OSHT_CBC:
- + 	case TZ_DIS_EVT:
- + 		if (evt == TZ_OSHT_CBC)
- + 			val = 1;
- + 		else
- + 			val = 0;
- + 
- + 		pos = input + 8;
- + 		mask = BIT((pos));
- + 		ehrpwm_reg_config(ehrpwm, TZSEL, val << pos, mask);
- + 		pos = input;
- + 		mask = BIT((pos));
- + 		ehrpwm_reg_config(ehrpwm, TZSEL, val << pos, mask);
- + 		break;
- + 
- + 	default:
- + 		dev_dbg(p->dev, "%s: Invalid command", __func__);
- + 		return -EINVAL;
- + 	}
- + 	debug("\n TZ_sel val is %0x", ehrpwm_read(ehrpwm, TZSEL));
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_tz_sel_event);
- + 
- + int ehrpwm_tz_set_action(struct pwm_device *p, unsigned char ch,
- + 	unsigned char act)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 
- + 	if (act > 0x3 || ch > 1)
- + 		return -EINVAL;
- + 
- + 	if (ch == 0)
- + 		ehrpwm_reg_config(ehrpwm, TZCTL, act, TZCTL_ACTA_MASK);
- + 	else
- + 		ehrpwm_reg_config(ehrpwm, TZCTL, act << TZCTL_ACTB_POS,
- + 			       TZCTL_ACTB_MASK);
- + 
- + 	debug("\n TZCTL reg val is %0x", ehrpwm_read(ehrpwm, TZCTL));
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_tz_set_action);
- + 
- + int ehrpwm_tz_set_int_en_dis(struct pwm_device *p, enum tz_event event,
- + 		unsigned char int_en_dis)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 
- + 	if (event == TZ_ONE_SHOT_EVENT)
- + 		ehrpwm_reg_config(ehrpwm, TZEINT, int_en_dis <<
- + 			       TZEINT_OSHTEVT_POS, BIT(2));
- + 	else if (event == TZ_CYCLE_BY_CYCLE)
- + 		ehrpwm_reg_config(ehrpwm, TZEINT, int_en_dis <<
- + 			       TZEINT_CBCEVT_POS, BIT(1));
- + 	else
- + 		return -EINVAL;
- + 
- + 	debug("\n TZEINT reg val is %0x", ehrpwm_read(ehrpwm, TZEINT));
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_tz_set_int_en_dis);
- + 
- + int ehrpwm_tz_force_evt(struct pwm_device *p, enum tz_event event)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 
- + 	if (event == TZ_ONE_SHOT_EVENT)
- + 		ehrpwm_write(ehrpwm, TZFRC, 0x4);
- + 	else if (event == TZ_CYCLE_BY_CYCLE)
- + 		ehrpwm_write(ehrpwm, TZFRC, 0x2);
- + 	else
- + 		return -EINVAL;
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_tz_force_evt);
- + 
- + inline int ehrpwm_tz_read_status(struct pwm_device *p, unsigned short *status)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 
- + 	*status = ehrpwm_read(ehrpwm, TZFLG);
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_tz_read_status);
- + 
- + inline int ehrpwm_tz_clr_evt_status(struct pwm_device *p)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 	unsigned short ret;
- + 
- + 	ret = ehrpwm_read(ehrpwm, TZFLG);
- + 	ehrpwm_write(ehrpwm, TZCLR, ret & ~0x1);
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_tz_clr_evt_status);
- + 
- + inline int ehrpwm_tz_clr_int_status(struct pwm_device *p)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 
- + 	ehrpwm_write(ehrpwm, TZCLR, 0x1);
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_tz_clr_int_status);
- + 
- + /* Event Trigger Configuration functions */
- + int ehrpwm_et_set_sel_evt(struct pwm_device *p, unsigned char evt,
- + 		unsigned char prd)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 
- + 	if (evt > 0x7 || prd > 0x3)
- + 		return -EINVAL;
- + 
- + 	ehrpwm_reg_config(ehrpwm, ETSEL, evt, ETSEL_INTSEL_MASK);
- + 	ehrpwm_reg_config(ehrpwm, ETPS, prd, ETPS_INTPRD_MASK);
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_et_set_sel_evt);
- + 
- + inline int ehrpwm_et_int_en_dis(struct pwm_device *p, unsigned char en_dis)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 
- + 	ehrpwm_reg_config(ehrpwm, ETSEL, en_dis << ETSEL_EN_INT_EN_POS, BIT(3));
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_et_int_en_dis);
- + 
- + inline int ehrpwm_et_read_evt_cnt(struct pwm_device *p,
- + 	unsigned long *evtcnt)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 
- + 	*evtcnt = ehrpwm_read(ehrpwm, ETPS) & ETPS_INTCNT_MASK;
- + 	*evtcnt >>= 0x2;
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_et_read_evt_cnt);
- + 
- + inline int ehrpwm_et_read_int_status(struct pwm_device *p,
- + 	unsigned long *status)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 
- + 	*status = ehrpwm_read(ehrpwm, ETFLG) & BIT(0);
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_et_read_int_status);
- + 
- + inline int ehrpwm_et_frc_int(struct pwm_device *p)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 
- + 	ehrpwm_write(ehrpwm, ETFRC, ENABLE);
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_et_frc_int);
- + 
- + inline int ehrpwm_et_clr_int(struct pwm_device *p)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 
- + 	ehrpwm_write(ehrpwm, ETCLR, ENABLE);
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_et_clr_int);
- + 
- + /* High Resolution Module configuration */
- + inline int ehrpwm_hr_set_phase(struct pwm_device *p, unsigned char val)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 
- + 	ehrpwm_write(ehrpwm, TBPHSHR, val << 8);
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_hr_set_phase);
- + 
- + inline int ehrpwm_hr_set_cmpval(struct pwm_device *p, unsigned char val)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 
- + 	ehrpwm_write(ehrpwm, CMPAHR, val << 8);
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_hr_set_cmpval);
- + 
- + int ehrpwm_hr_config(struct pwm_device *p, unsigned char loadmode,
- + 		unsigned char ctlmode, unsigned char edgemode)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 
- + 	if (loadmode > 1 || ctlmode > 1 || edgemode > 3)
- + 		return -EINVAL;
- + 
- + 	if (ehrpwm->version == PWM_VERSION_1) {
- + 		ehrpwm_reg_config(ehrpwm, AM335X_HRCNFG,
- + 				loadmode << HRCNFG_LDMD_POS, BIT(3));
- + 		ehrpwm_reg_config(ehrpwm, AM335X_HRCNFG,
- + 				ctlmode << HRCNFG_CTLMD_POS, BIT(2));
- + 		ehrpwm_reg_config(ehrpwm, AM335X_HRCNFG,
- + 				edgemode, HRCNFG_EDGEMD_MASK);
- + 	} else {
- + 		ehrpwm_reg_config(ehrpwm, HRCNFG,
- + 				loadmode << HRCNFG_LDMD_POS, BIT(3));
- + 		ehrpwm_reg_config(ehrpwm, HRCNFG,
- + 				ctlmode << HRCNFG_CTLMD_POS, BIT(2));
- + 		ehrpwm_reg_config(ehrpwm, HRCNFG,
- + 				edgemode, HRCNFG_EDGEMD_MASK);
- + 	}
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_hr_config);
- + 
- + inline int ehrpwm_reg_read(struct pwm_device *p, unsigned int reg,
- + 	       unsigned short *val)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 
- + 	if (!(ehrpwm->version == PWM_VERSION_1)) {
- + 		if (reg > HRCNFG)
- + 			return -EINVAL;
- + 	}
- + 
- + 	*val = ehrpwm_read(ehrpwm, reg);
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_reg_read);
- + 
- + inline int ehrpwm_reg_write(struct pwm_device *p, unsigned int reg,
- + 	       unsigned short val)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 
- + 	if (!(ehrpwm->version == PWM_VERSION_1)) {
- + 		if (reg > HRCNFG)
- + 			return -EINVAL;
- + 	}
- + 
- + 	ehrpwm_write(ehrpwm, reg, val);
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_reg_write);
- + 
- + 
- + static void ehrpwm_channel_output_low(struct pwm_device *p)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 	int chan = p - &ehrpwm->pwm[0];
- + 
- + 	ehrpwm_aq_set_csfrc_load_mode(p, AQSFRC_RLDCSF_IMDT);
- + 	ehrpwm_aq_continuous_frc(p, chan, AQCSFRC_CSF_FRCLOW);
- + }
- + 
- + static void ehrpwm_channel_output_enable(struct pwm_device *p, int channel)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 
- + 	pm_runtime_get_sync(ehrpwm->dev);
- + 	ehrpwm_aq_set_csfrc_load_mode(p, AQSFRC_RLDCSF_ZRO);
- + 	ehrpwm_aq_continuous_frc(p, channel, AQCSFRC_CSF_FRCDIS);
- + 	pm_runtime_put_sync(ehrpwm->dev);
- + }
- + 
- + static int ehrpwm_pwm_set_pol(struct pwm_device *p)
- + {
- + 	unsigned int act_ctrl_reg;
- + 	unsigned int cmp_reg;
- + 	unsigned int ctreqcmp_mask;
- + 	unsigned int ctreqcmp;
- + 	unsigned short val;
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 	int chan;
- + 
- + 	chan = p - &ehrpwm->pwm[0];
- + 	if (!chan) {
- + 		act_ctrl_reg = AQCTLA;
- + 		cmp_reg = CMPA;
- + 		ctreqcmp_mask = ACTCTL_CAU_MASK;
- + 		ctreqcmp = 4;
- + 	} else {
- + 		act_ctrl_reg = AQCTLB;
- + 		cmp_reg = CMPB;
- + 		ctreqcmp_mask = ACTCTL_CBU_MASK;
- + 		ctreqcmp = 8;
- + 	}
- + 
- + 
- + 	pm_runtime_get_sync(ehrpwm->dev);
- + 	val = ((p->active_high ? ACTCTL_CTREQCMP_HIGH : ACTCTL_CTREQCMP_LOW)
- + 		 << ctreqcmp) | (p->active_high ? ACTCTL_CTREQZRO_LOW :
- + 			ACTCTL_CTREQZRO_HIGH);
- + 	ehrpwm_write(ehrpwm, act_ctrl_reg, val);
- + 	pm_runtime_put_sync(ehrpwm->dev);
- + 	return 0;
- + }
- + 
- + static int ehrpwm_pwm_start(struct pwm_device *p)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 	unsigned short val;
- + 	int chan;
- + 
- + 	/* Trying to start a running PWM, not allowed */
- + 	if (pwm_is_running(p))
- + 		return -EPERM;
- + 
- + 	/* For PWM clock should be enabled on start */
- + 	pm_runtime_get_sync(ehrpwm->dev);
- + 
- + 	ehrpwm_pwm_set_pol(p);
- + 	chan = p - &ehrpwm->pwm[0];
- + 	val = ehrpwm_read(ehrpwm, TBCTL);
- + 	val = (val & ~TBCTL_CTRMODE_MASK) | (TBCTL_CTRMOD_CTRUP |
- + 		 TBCTL_FREERUN_FREE << 14);
- + 	ehrpwm_write(ehrpwm, TBCTL, val);
- + 
- + 	/* Enable PWM channel output */
- + 	ehrpwm_channel_output_enable(p, chan);
- + 
- + 	set_bit(FLAG_RUNNING, &p->flags);
- + 	return 0;
- + }
- + 
- + /*
- +  * Stop function is implemented using the Trip Zone module. Action for the
- +  * corresponding channel is set to low and the one shot software force
- +  * event is triggered.
- +  */
- + static int ehrpwm_pwm_stop(struct pwm_device *p)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 
- + 	/* Trying to stop a non-running PWM, not allowed */
- + 	if (!pwm_is_running(p))
- + 		return -EPERM;
- + 
- + 	/* Put PWM output to low */
- + 	ehrpwm_channel_output_low(p);
- + 
- + 	/* For PWM clock should be disabled on stop */
- + 	pm_runtime_put_sync(ehrpwm->dev);
- + 	clear_bit(FLAG_RUNNING, &p->flags);
- + 	return 0;
- + }
- + 
- + /*
- +  * Prescalar is used when the period value exceeds the maximum value
- +  * of the 16 bit period register. We always look for the minimum prescalar
- +  * value as it would result in wide range of duty control
- +  */
- + static char get_divider_val(unsigned int desired_ps_val, unsigned int
- + *ps_div_val, unsigned int *tb_div_val)
- + {
- + 	char i = 0;
- + 	char j = 0;
- + 
- + 	for (i = 0; i <= 7; i++) {
- + 		for (j = 0; j <= 7; j++) {
- + 			if (((1 << i) * (j ? (j * 2) : 1)) >= desired_ps_val) {
- + 				*ps_div_val = (1 << i) * (j ? (j * 2) : 1);
- + 				*tb_div_val = (i << 10) | (j << 7) ;
- + 				return 0;
- + 			}
- + 		}
- + 	}
- + 
- + 	return -1;
- + }
- + 
- + static int ehrpwm_pwm_set_prd(struct pwm_device *p)
- + {
- + 	unsigned int ps_div_val = 1;
- + 	unsigned int tb_div_val = 0;
- + 	char ret;
- + 	unsigned short val;
- + 	unsigned short period_ticks;
- + 	struct pwm_device *temp;
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 	int chan = 0;
- + 	/*
- + 	 * Since the device has a singe period register, copy the period
- + 	 * value to the other channel also.
- + 	 */
- + 	chan = p - &ehrpwm->pwm[0];
- + 	temp = &ehrpwm->pwm[!chan];
- + 	temp->period_ticks = p->period_ticks;
- + 	temp->period_ns = p->period_ns;
- + 	debug("\n period_ticks is %lu", p->period_ticks);
- + 
- + 	if (p->period_ticks > 65535) {
- + 		ret = get_divider_val(p->period_ticks / 65535 + 1, &ps_div_val,
- + 				&tb_div_val);
- + 		if (ret) {
- + 			dev_err(p->dev, "failed to get the divider value");
- + 			return -EINVAL;
- + 		}
- + 	}
- + 
- + 	pm_runtime_get_sync(ehrpwm->dev);
- + 	val = ehrpwm_read(ehrpwm, TBCTL);
- + 	val = (val & ~TBCTL_CLKDIV_MASK & ~TBCTL_HSPCLKDIV_MASK) | tb_div_val;
- + 	ehrpwm_write(ehrpwm, TBCTL, val);
- + 	period_ticks = p->period_ticks / ps_div_val;
- + 
- + 	if (period_ticks <= 1) {
- + 		dev_err(p->dev, "Required period/frequency cannot be obtained");
- + 		pm_runtime_put_sync(ehrpwm->dev);
- + 		return -EINVAL;
- + 	}
- + 	/*
- + 	 * Program the period register with 1 less than the actual value since
- + 	 * the module generates waveform with period always 1 greater
- + 	 * the programmed value.
- + 	 */
- + 	ehrpwm_write(ehrpwm, TBPRD, (unsigned short)(period_ticks - 1));
- + 	pm_runtime_put_sync(ehrpwm->dev);
- + 	debug("\n period_ticks is %d", period_ticks);
- + 	ehrpwm->prescale_val = ps_div_val;
- + 	debug("\n Prescaler value is %d", ehrpwm->prescale_val);
- + 
- + 	return 0;
- + }
- + 
- + static int ehrpwm_hr_duty_config(struct pwm_device *p)
- + {
- + 	unsigned char no_of_mepsteps;
- + 	unsigned short cmphr_val;
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 
- + 	if (!p->tick_hz) {
- + 		dev_dbg(p->dev, "%s: p->tick_hz is zero\n", __func__);
- + 		return -EINVAL;
- + 	}
- + 
- + 	/*
- + 	 * Calculate the no of MEP steps. Assume system clock
- + 	 * is in the order of MHZ.
- + 	 */
- + 	no_of_mepsteps = USEC_PER_SEC / ((p->tick_hz / USEC_PER_SEC) * 63);
- + 
- + 	pm_runtime_get_sync(ehrpwm->dev);
- + 	/* Calculate the CMPHR Value */
- + 	cmphr_val = p->tick_hz / USEC_PER_SEC;
- + 	cmphr_val = (p->duty_ns * cmphr_val) % MSEC_PER_SEC;
- + 	cmphr_val = (cmphr_val * no_of_mepsteps) / 1000;
- + 	cmphr_val = (cmphr_val << 8) + 0x180;
- + 	ehrpwm_write(ehrpwm, CMPAHR, cmphr_val);
- + 
- + 	if (ehrpwm->version == PWM_VERSION_1)
- + 		ehrpwm_write(ehrpwm, AM335X_HRCNFG, 0x2);
- + 	else
- + 		ehrpwm_write(ehrpwm, HRCNFG, 0x2);
- + 
- + 	pm_runtime_put_sync(ehrpwm->dev);
- + 	return 0;
- + }
- + 
- + static int ehrpwm_pwm_set_dty(struct pwm_device *p)
- + {
- + 	unsigned short duty_ticks = 0;
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 	int ret = 0;
- + 	int chan;
- + 
- + 	chan = p - &ehrpwm->pwm[0];
- + 
- + 	if (!ehrpwm->prescale_val) {
- + 		dev_dbg(p->dev, "%s: prescale_val is zero\n", __func__);
- + 		return -EINVAL;
- + 	}
- + 
- + 	duty_ticks = p->duty_ticks / ehrpwm->prescale_val;
- + 	debug("\n Prescaler value is %d", ehrpwm->prescale_val);
- + 	debug("\n duty ticks is %d", duty_ticks);
- + 	pm_runtime_get_sync(ehrpwm->dev);
- + 	/* High resolution module */
- + 	if (chan && ehrpwm->prescale_val <= 1) {
- + 		ret = ehrpwm_hr_duty_config(p);
- + 		if (ehrpwm->version == PWM_VERSION_1)
- + 			ehrpwm_write(ehrpwm, AM335X_HRCNFG, 0x2);
- + 		else
- + 			ehrpwm_write(ehrpwm, HRCNFG, 0x2);
- + 	}
- + 
- + 	ehrpwm_write(ehrpwm, (chan ? CMPB : CMPA), duty_ticks);
- + 	pm_runtime_put_sync(ehrpwm->dev);
- + 	return ret;
- + }
- + 
- + int ehrpwm_et_cb_register(struct pwm_device *p, void *data,
- + 	p_fcallback cb)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 	unsigned long flags;
- + 
- + 	spin_lock_irqsave(&ehrpwm->lock, flags);
- + 	ehrpwm->st_etint.data = data;
- + 	ehrpwm->st_etint.pcallback = cb;
- + 	spin_unlock_irqrestore(&ehrpwm->lock, flags);
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_et_cb_register);
- + 
- + int ehrpwm_tz_cb_register(struct pwm_device *p, void *data,
- + 	p_fcallback cb)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 	unsigned long flags;
- + 
- + 	spin_lock_irqsave(&ehrpwm->lock, flags);
- + 	ehrpwm->st_tzint.data = data;
- + 	ehrpwm->st_tzint.pcallback = cb;
- + 	spin_unlock_irqrestore(&ehrpwm->lock, flags);
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_tz_cb_register);
- + 
- + static int ehrpwm_pwm_suspend_cb(struct ehrpwm_pwm *ehrpwm, void *data)
- + {
- + 	struct ehrpwm_suspend_params *pwm_suspend_params =
- + 				(struct ehrpwm_suspend_params *)data;
- + 
- + 	if (pwm_suspend_params->act_delay++ >= pwm_suspend_params->
- + 			req_delay_cycles) {
- + 		pwm_start(pwm_suspend_params->pch);
- + 		ehrpwm_et_cb_register(pwm_suspend_params->pch, NULL, NULL);
- + 		ehrpwm_et_int_en_dis(pwm_suspend_params->pch, DISABLE);
- + 	}
- + 
- + 	return 0;
- + }
- + 
- + int ehrpwm_pwm_suspend(struct pwm_device *p, enum config_mask config_mask,
- + 	       unsigned long val)
- + {
- + 	unsigned long long req_cycles = 0;
- + 
- + 	if (!p->period_ns)
- + 		return -EINVAL;
- + 
- + 	ehrpwm_pwm_stop(p);
- + 	/* Calculate the delay in terms of cycles */
- + 	if (config_mask == CONFIG_NS)
- + 		req_cycles =  val / p->period_ns;
- + 	else if (config_mask == CONFIG_TICKS)
- + 		req_cycles = val;
- + 	else
- + 		return -EINVAL;
- + 
- + 	/* Configute the event interrupt */
- + 	ehrpwm_et_set_sel_evt(p, 0x2, 0x1);
- + 	ehrpwm_suspend_params.pch = p;
- + 	ehrpwm_suspend_params.req_delay_cycles = req_cycles;
- + 	ehrpwm_suspend_params.act_delay = 0;
- + 	ehrpwm_et_cb_register(p, &ehrpwm_suspend_params,
- + 		ehrpwm_pwm_suspend_cb);
- + 	ehrpwm_et_int_en_dis(p, ENABLE);
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(ehrpwm_pwm_suspend);
- + 
- + static irqreturn_t ehrpwm_trip_zone_irq_handler(int irq, void *data)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = (struct ehrpwm_pwm *)data;
- + 	unsigned long flags;
- + 	int ret = 0;
- + 
- + 	spin_lock_irqsave(&ehrpwm->lock, flags);
- + 	 ret = ehrpwm_read(ehrpwm, TZFLG);
- + 	if (!(ret & 0x1))
- + 		return IRQ_NONE;
- + 
- + 	if (ehrpwm->st_tzint.pcallback)
- + 		ret = ehrpwm->st_tzint.pcallback(ehrpwm, ehrpwm->st_tzint.data);
- + 
- + 	ret = ehrpwm_read(ehrpwm, TZFLG);
- + 	ehrpwm_write(ehrpwm, TZCLR, ret & ~0x1);
- + 	ehrpwm_write(ehrpwm, TZCLR, 0x1);
- + 	spin_unlock_irqrestore(&ehrpwm->lock, flags);
- + 
- + 	return IRQ_HANDLED;
- + }
- + 
- + static irqreturn_t ehrpwm_event_irq_handler(int irq, void *data)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = (struct ehrpwm_pwm *)data;
- + 	unsigned long flags;
- + 
- + 	spin_lock_irqsave(&ehrpwm->lock, flags);
- + 
- + 	if (ehrpwm->st_etint.pcallback)
- + 		ehrpwm->st_etint.pcallback(ehrpwm, ehrpwm->st_etint.data);
- + 
- + 	ehrpwm_write(ehrpwm, ETCLR, 0x1);
- + 
- + 	spin_unlock_irqrestore(&ehrpwm->lock, flags);
- + 
- + 	return IRQ_HANDLED;
- + }
- + 
- + static int ehrpwm_pwm_config(struct pwm_device *p,
- + 	struct pwm_config *c)
- + {
- + 	int ret = 0;
- + 
- + 	switch (c->config_mask) {
- + 	case BIT(PWM_CONFIG_PERIOD_TICKS):
- + 		if (p->max_period_ticks &&
- + 				(p->max_period_ticks >= c->period_ticks))
- + 			p->period_ticks = p->max_period_ticks;
- + 		else
- + 			p->period_ticks = c->period_ticks;
- + 
- + 		ret = ehrpwm_pwm_set_prd(p);
- + 		break;
- + 
- + 	case BIT(PWM_CONFIG_DUTY_TICKS):
- + 		p->duty_ticks = c->duty_ticks;
- + 		ret = ehrpwm_pwm_set_dty(p);
- + 		break;
- + 
- + 	case BIT(PWM_CONFIG_POLARITY):
- + 		p->active_high = c->polarity;
- + 		ret = ehrpwm_pwm_set_pol(p);
- + 		break;
- + 
- + 	case BIT(PWM_CONFIG_START):
- + 		 ret = ehrpwm_pwm_start(p);
- + 		 break;
- + 
- + 	case BIT(PWM_CONFIG_STOP):
- + 		ret = ehrpwm_pwm_stop(p);
- + 		break;
- + 
- + 	default:
- + 		dev_dbg(p->dev, "%s: Invalid configuration\n", __func__);
- + 		ret = -EINVAL;
- + 	}
- + 
- + 	return ret;
- + }
- + 
- + static int ehrpwm_pwm_request(struct pwm_device *p)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 	int chan;
- + 
- + 	chan = p - &ehrpwm->pwm[0];
- + 
- + 	p->tick_hz = clk_get_rate(ehrpwm->clk);
- + 	debug("\n The clk freq is %lu", p->tick_hz);
- + 	/* Put PWM output to low */
- + 	pm_runtime_get_sync(ehrpwm->dev);
- + 	ehrpwm_channel_output_low(p);
- + 	pm_runtime_put_sync(ehrpwm->dev);
- + 
- + 	return 0;
- + }
- + 
- + static int ehrpwm_freq_transition_cb(struct pwm_device *p)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
- + 	unsigned long duty_ns;
- + 
- + 	p->tick_hz = clk_get_rate(ehrpwm->clk);
- + 	duty_ns = p->duty_ns;
- + 	if (pwm_is_running(p)) {
- + 		pwm_stop(p);
- + 		pwm_set_duty_ns(p, 0);
- + 		pwm_set_period_ns(p, p->period_ns);
- + 		pwm_set_duty_ns(p, duty_ns);
- + 		pwm_start(p);
- + 	} else {
- + 		pwm_set_duty_ns(p, 0);
- + 		pwm_set_period_ns(p, p->period_ns);
- + 		pwm_set_duty_ns(p, duty_ns);
- + 	}
- + 		return 0;
- + }
- + 
- + static int ehrpwm_probe(struct platform_device *pdev)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = NULL;
- + 	struct resource *r;
- + 	int ret = 0;
- + 	int chan = 0;
- + 	struct pwmss_platform_data *pdata = (&pdev->dev)->platform_data;
- + 	int ch_mask = 0;
- + 	int val;
- + 	char con_id[PWM_CON_ID_STRING_LENGTH] = "epwmss";
- + 
- + 	ehrpwm = kzalloc(sizeof(*ehrpwm), GFP_KERNEL);
- + 	if (!ehrpwm) {
- + 		dev_err(&pdev->dev, "failed to allocate memory\n");
- + 		ret = -ENOMEM;
- + 		goto err_mem_failure;
- + 	}
- + 
- + 	ehrpwm->version = pdata->version;
- + 
- + 	if (ehrpwm->version == PWM_VERSION_1) {
- + 		sprintf(con_id, "%s%d_%s", con_id, pdev->id, "fck");
- + 		ehrpwm->clk = clk_get(&pdev->dev, con_id);
- + 	} else
- + 		ehrpwm->clk = clk_get(&pdev->dev, "ehrpwm");
- + 
- + 	pm_runtime_enable(&pdev->dev);
- + 	ehrpwm->dev = &pdev->dev;
- + 	if (IS_ERR(ehrpwm->clk)) {
- + 		ret = PTR_ERR(ehrpwm->clk);
- + 		goto err_clock_failure;
- + 	}
- + 
- + 	if (ehrpwm->version == PWM_VERSION_1) {
- + 		r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- + 
- + 		if (!r) {
- + 			dev_err(&pdev->dev, "no memory resource defined\n");
- + 			ret = -ENOMEM;
- + 			goto err_resource_mem_failure;
- + 		}
- + 
- + 		ehrpwm->config_mem_base = ioremap(r->start, resource_size(r));
- + 
- + 		if (!ehrpwm->config_mem_base) {
- + 
- + 			dev_err(&pdev->dev, "failed to ioremap() registers\n");
- + 			ret = -ENODEV;
- + 			goto err_free_mem_config;
- + 		}
- + 
- + 		pm_runtime_get_sync(ehrpwm->dev);
- + 		val = readw(ehrpwm->config_mem_base + PWMSS_CLKCONFIG);
- + 		val |= BIT(EPWM_CLK_EN);
- + 		writew(val, ehrpwm->config_mem_base + PWMSS_CLKCONFIG);
- + 		pm_runtime_put_sync(ehrpwm->dev);
- + 	} else
- + 		ch_mask = pdata->channel_mask;
- + 
- + 	spin_lock_init(&ehrpwm->lock);
- + 	ehrpwm->ops.config = ehrpwm_pwm_config;
- + 	ehrpwm->ops.request = ehrpwm_pwm_request;
- + 	ehrpwm->ops.freq_transition_notifier_cb = ehrpwm_freq_transition_cb;
- + 	ehrpwm->prescale_val = 1;
- + 
- + 	if (ehrpwm->version == PWM_VERSION_1)
- + 		r = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- + 	else
- + 		r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- + 
- + 	if (!r) {
- + 		dev_err(&pdev->dev, "no memory resource defined\n");
- + 		ret = -ENODEV;
- + 		goto err_resource_mem2_failiure;
- + 	}
- + 
- + 	r = request_mem_region(r->start, resource_size(r), pdev->name);
- + 	if (!r) {
- + 		dev_err(&pdev->dev, "failed to request memory resource\n");
- + 		ret = -EBUSY;
- + 		goto err_request_mem2_failure;
- + 	}
- + 
- + 	ehrpwm->mmio_base = ioremap(r->start, resource_size(r));
- + 	if (!ehrpwm->mmio_base) {
- + 		dev_err(&pdev->dev, "failed to ioremap() registers\n");
- + 		ret = -ENODEV;
- + 		goto err_free_mem2;
- + 	}
- + 
- + 	ehrpwm->irq[0] = platform_get_irq(pdev, 0);
- + 	if (ehrpwm->irq[0] == -ENXIO) {
- + 		dev_err(&pdev->dev, "No IRQ resource\n");
- + 		ret = -ENXIO;
- + 		goto err_free_io;
- + 	}
- + 
- + 	ret = request_irq(ehrpwm->irq[0], ehrpwm_trip_zone_irq_handler,
- + 				0, "ehrpwmTZ", ehrpwm);
- + 	if (ret)
- + 		goto err_free_io;
- + 
- + 	ehrpwm->irq[1] = platform_get_irq(pdev, 1);
- + 	if (ehrpwm->irq[1] == -ENXIO) {
- + 		dev_err(&pdev->dev, "No IRQ resource\n");
- + 		ret = -ENXIO;
- + 		goto err_request_irq;
- + 	}
- + 
- + 	ret = request_irq(ehrpwm->irq[1], ehrpwm_event_irq_handler,
- + 				0, "ehrpwm_evt", ehrpwm);
- + 	if (ret)
- + 		goto err_request_irq;
- + 
- + 	for (chan = 0; chan < NCHAN; chan++) {
- + 		ehrpwm->pwm[chan].ops = &ehrpwm->ops;
- + 		pwm_set_drvdata(&ehrpwm->pwm[chan], ehrpwm);
- + 		ehrpwm->pwm[chan].tick_hz = clk_get_rate(ehrpwm->clk);
- + 
- + 		if (pdata->chan_attrib[chan].max_freq) {
- + 			int period_ns = NSEC_PER_SEC
- + 				/ pdata->chan_attrib[chan].max_freq;
- + 
- + 			ehrpwm->pwm[chan].max_period_ticks =
- + 				pwm_ns_to_ticks(&ehrpwm->pwm[chan], period_ns);
- + 		}
- + 
- + 		if (!(ehrpwm->version == PWM_VERSION_1)) {
- + 			if (!(ch_mask & (0x1 << chan)))
- + 				continue;
- + 		}
- + 
- + 		ret =  pwm_register(&ehrpwm->pwm[chan], &pdev->dev, chan);
- + 		if (ret)
- + 			goto err_pwm_register;
- + 	}
- + 
- + 		platform_set_drvdata(pdev, ehrpwm);
- + 	return 0;
- + 
- + err_pwm_register:
- + 	for (chan = 0; chan < NCHAN; chan++) {
- + 		if (pwm_is_registered(&ehrpwm->pwm[chan]))
- + 			pwm_unregister(&ehrpwm->pwm[chan]);
- + 	}
- + 
- + err_request_irq:
- + 	if (ehrpwm->irq[0] != -ENXIO)
- + 		free_irq(ehrpwm->irq[0], ehrpwm);
- + err_free_io:
- + 	iounmap(ehrpwm->mmio_base);
- + err_free_mem2:
- + 	release_mem_region(r->start, resource_size(r));
- + err_request_mem2_failure:
- + err_resource_mem2_failiure:
- + 	if (ehrpwm->version == PWM_VERSION_1) {
- + 		iounmap(ehrpwm->config_mem_base);
- + 		ehrpwm->config_mem_base = NULL;
- + 	}
- + err_free_mem_config:
- + err_resource_mem_failure:
- + 	clk_put(ehrpwm->clk);
- + 	pm_runtime_disable(ehrpwm->dev);
- + err_clock_failure:
- + 	kfree(ehrpwm);
- + err_mem_failure:
- + 	return ret;
- + }
- + 
- + #ifdef CONFIG_PM
- + 
- + void ehrpwm_context_save(struct ehrpwm_pwm *ehrpwm,
- + 		struct ehrpwm_context *ehrpwm_ctx)
- + {
- + 	pm_runtime_get_sync(ehrpwm->dev);
- + 	ehrpwm_ctx->tbctl = ehrpwm_read(ehrpwm, TBCTL);
- + 	ehrpwm_ctx->tbprd = ehrpwm_read(ehrpwm, TBPRD);
- + 	if (ehrpwm->version == PWM_VERSION_1)
- + 		ehrpwm_ctx->hrcfg = ehrpwm_read(ehrpwm, AM335X_HRCNFG);
- + 	else
- + 		ehrpwm_ctx->hrcfg = ehrpwm_read(ehrpwm, HRCNFG);
- + 	ehrpwm_ctx->aqctla = ehrpwm_read(ehrpwm, AQCTLA);
- + 	ehrpwm_ctx->aqctlb = ehrpwm_read(ehrpwm, AQCTLB);
- + 	ehrpwm_ctx->aqsfrc = ehrpwm_read(ehrpwm, AQSFRC);
- + 	ehrpwm_ctx->aqcsfrc = ehrpwm_read(ehrpwm, AQCSFRC);
- + 	ehrpwm_ctx->cmpa = ehrpwm_read(ehrpwm, CMPA);
- + 	ehrpwm_ctx->cmpb = ehrpwm_read(ehrpwm, CMPB);
- + 	pm_runtime_put_sync(ehrpwm->dev);
- + }
- + 
- + void ehrpwm_context_restore(struct ehrpwm_pwm *ehrpwm,
- + 		struct ehrpwm_context *ehrpwm_ctx)
- + {
- + 	ehrpwm_write(ehrpwm, TBCTL, ehrpwm_ctx->tbctl);
- + 	ehrpwm_write(ehrpwm, TBPRD, ehrpwm_ctx->tbprd);
- + 	if (ehrpwm->version == PWM_VERSION_1)
- + 		ehrpwm_write(ehrpwm, AM335X_HRCNFG, ehrpwm_ctx->hrcfg);
- + 	else
- + 		ehrpwm_write(ehrpwm, HRCNFG, ehrpwm_ctx->hrcfg);
- + 	ehrpwm_write(ehrpwm, AQCTLA, ehrpwm_ctx->aqctla);
- + 	ehrpwm_write(ehrpwm, AQCTLB, ehrpwm_ctx->aqctlb);
- + 	ehrpwm_write(ehrpwm, AQSFRC, ehrpwm_ctx->aqsfrc);
- + 	ehrpwm_write(ehrpwm, AQCSFRC, ehrpwm_ctx->aqcsfrc);
- + 	ehrpwm_write(ehrpwm, CMPA, ehrpwm_ctx->cmpa);
- + 	ehrpwm_write(ehrpwm, CMPB, ehrpwm_ctx->cmpb);
- + }
- + 
- + static int ehrpwm_suspend(struct platform_device *pdev, pm_message_t state)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = platform_get_drvdata(pdev);
- + 
- + 	ehrpwm_context_save(ehrpwm, &ehrpwm->ctx);
- + 	pm_runtime_put_sync(ehrpwm->dev);
- + 
- + 	return 0;
- + }
- + 
- + static int ehrpwm_resume(struct platform_device *pdev)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = platform_get_drvdata(pdev);
- + 
- + 	pm_runtime_get_sync(ehrpwm->dev);
- + 	ehrpwm_context_restore(ehrpwm, &ehrpwm->ctx);
- + 
- + 	return 0;
- + }
- + 
- + #else
- + #define ehrpwm_suspend NULL
- + #define ehrpwm_resume NULL
- + #endif /* CONFIG_PM */
- + 
- + static int __devexit ehrpwm_remove(struct platform_device *pdev)
- + {
- + 	struct ehrpwm_pwm *ehrpwm = platform_get_drvdata(pdev);
- + 	struct resource *r;
- + 	unsigned char i;
- + 	int val;
- + 	struct pwmss_platform_data *pdata;
- + 
- + 	if (ehrpwm->version == PWM_VERSION_1) {
- + 		pdata = (&pdev->dev)->platform_data;
- + 		pm_runtime_get_sync(ehrpwm->dev);
- + 		val = readw(ehrpwm->config_mem_base + PWMSS_CLKCONFIG);
- + 		val &= ~BIT(EPWM_CLK_EN);
- + 		writew(val, ehrpwm->config_mem_base + PWMSS_CLKCONFIG);
- + 		pm_runtime_put_sync(ehrpwm->dev);
- + 		iounmap(ehrpwm->config_mem_base);
- + 		ehrpwm->config_mem_base = NULL;
- + 	}
- + 
- + 	for (i = 0; i < NCHAN; i++) {
- + 		if (pwm_is_registered(&ehrpwm->pwm[i]))
- + 			pwm_unregister(&ehrpwm->pwm[i]);
- + 	}
- + 
- + 	for (i = 0; i < 2; i++)
- + 		if (ehrpwm->irq[i] != -ENXIO)
- + 			free_irq(ehrpwm->irq[i], ehrpwm);
- + 	iounmap(ehrpwm->mmio_base);
- + 
- + 	if (ehrpwm->version == PWM_VERSION_1)
- + 		r = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- + 	else
- + 		r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- + 
- + 	release_mem_region(r->start, resource_size(r));
- + 	platform_set_drvdata(pdev, NULL);
- + 	clk_put(ehrpwm->clk);
- + 	pm_runtime_disable(ehrpwm->dev);
- + 	kfree(ehrpwm);
- + 
- + 	return 0;
- + }
- + 
- + static struct platform_driver ehrpwm_driver = {
- + 	.driver	= {
- + 		.name	= "ehrpwm",
- + 		.owner	= THIS_MODULE,
- + 	},
- + 	.probe		= ehrpwm_probe,
- + 	.remove		= __devexit_p(ehrpwm_remove),
- + 	.suspend	= ehrpwm_suspend,
- + 	.resume		= ehrpwm_resume,
- + };
- + 
- + static int __init ehrpwm_init(void)
- + {
- + 	return platform_driver_register(&ehrpwm_driver);
- + }
- + module_init(ehrpwm_init);
- + 
- + static void __exit ehrpwm_exit(void)
- + {
- + 	platform_driver_unregister(&ehrpwm_driver);
- + }
- + module_exit(ehrpwm_exit);
- + 
- + MODULE_AUTHOR("Texas Instruments");
- + MODULE_DESCRIPTION("Driver for Davinci eHRPWM peripheral");
- + MODULE_LICENSE("GPL");
- + MODULE_ALIAS("platform:ehrpwm");
- diff -crN linux-3.2.1_o/drivers/pwm/Kconfig linux-3.2.1/drivers/pwm/Kconfig
- *** linux-3.2.1_o/drivers/pwm/Kconfig	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/drivers/pwm/Kconfig	2014-05-15 13:25:14.607061061 +0900
- ***************
- *** 0 ****
- --- 1,29 ----
- + #
- + # PWM infrastructure and devices
- + #
- + 
- + menuconfig GENERIC_PWM
- + 	tristate "PWM Support"
- + 	default n
- + 	help
- + 	  Enables PWM device support implemented via a generic
- + 	  framework.  If unsure, say N.
- + 
- + config DAVINCI_EHRPWM
- + 	bool "Davinci eHRPWM support"
- + 	select HAVE_PWM
- + 	depends on GENERIC_PWM && (ARCH_DAVINCI_DA850 || SOC_OMAPAM33XX)
- + 	help
- + 	  This option enables support for eHRPWM driver. If
- + 	  unsure, say N.
- + 
- + config ECAP_PWM
- + 	tristate "eCAP PWM support"
- + 	select HAVE_PWM
- + 	depends on GENERIC_PWM && (ARCH_DAVINCI_DA850 || SOC_OMAPAM33XX)
- + 	help
- + 	  This option enables device driver support for eCAP module found
- + 	  on DA8xx Processors & AM335x processor. eCAP module is used to
- + 	  generate wide range of PWM waveforms. Maximum frequency generated
- + 	  is equal to half the system clock frequency.
- + 	  Say Y to enable the eCAP support. If unsure, say N.
- diff -crN linux-3.2.1_o/drivers/pwm/Makefile linux-3.2.1/drivers/pwm/Makefile
- *** linux-3.2.1_o/drivers/pwm/Makefile	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/drivers/pwm/Makefile	2014-05-15 13:25:14.607061061 +0900
- ***************
- *** 0 ****
- --- 1,8 ----
- + #
- + # Makefile for pwm devices
- + #
- + obj-$(CONFIG_GENERIC_PWM) := pwm.o
- + 
- + obj-$(CONFIG_DAVINCI_EHRPWM)	+= ehrpwm.o
- + 
- + obj-$(CONFIG_ECAP_PWM)		+= ecap.o
- diff -crN linux-3.2.1_o/drivers/pwm/pwm.c linux-3.2.1/drivers/pwm/pwm.c
- *** linux-3.2.1_o/drivers/pwm/pwm.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/drivers/pwm/pwm.c	2014-05-15 13:25:14.607061061 +0900
- ***************
- *** 0 ****
- --- 1,843 ----
- + /*
- +  * PWM API implementation
- +  *
- +  * Copyright (C) 2011 Bill Gatliff <bgat@billgatliff.com>
- +  * Copyright (C) 2011 Arun Murthy <arun.murthy@stericsson.com>
- +  *
- +  * This program is free software; you may redistribute and/or modify
- +  * it under the terms of the GNU General Public License version 2 as
- +  * published by the Free Software Foundation.
- +  *
- +  * This program is distributed in the hope that it will be useful, but
- +  * WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- +  * General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
- +  * USA
- +  */
- + 
- + #include <linux/module.h>
- + #include <linux/kernel.h>
- + #include <linux/init.h>
- + #include <linux/slab.h>
- + #include <linux/device.h>
- + #include <linux/fs.h>
- + #include <linux/completion.h>
- + #include <linux/workqueue.h>
- + #include <linux/list.h>
- + #include <linux/sched.h>
- + #include <linux/platform_device.h>
- + #include <linux/cpufreq.h>
- + #include <linux/pwm/pwm.h>
- + 
- + static const char *REQUEST_SYSFS = "sysfs";
- + static LIST_HEAD(pwm_device_list);
- + static DEFINE_MUTEX(device_list_mutex);
- + static struct class pwm_class;
- + static struct workqueue_struct *pwm_handler_workqueue;
- + 
- + static int pwm_match_name(struct device *dev, void *name)
- + {
- + 	return !strcmp(name, dev_name(dev));
- + }
- + 
- + static struct pwm_device *__pwm_request(struct pwm_device *p, const char *label)
- + {
- + 	int ret;
- + 
- + 	ret = test_and_set_bit(FLAG_REQUESTED, &p->flags);
- + 	if (ret) {
- + 		p = ERR_PTR(-EBUSY);
- + 		goto done;
- + 	}
- + 
- + 	p->label = label;
- + 	p->pid = current->pid;
- + 
- + 	if (p->ops->request) {
- + 		ret = p->ops->request(p);
- + 		if (ret) {
- + 			p = ERR_PTR(ret);
- + 			clear_bit(FLAG_REQUESTED, &p->flags);
- + 			goto done;
- + 		}
- + 	}
- + 
- + done:
- + 	return p;
- + }
- + 
- + static struct pwm_device *__pwm_request_byname(const char *name,
- + 					       const char *label)
- + {
- + 	struct device *d;
- + 	struct pwm_device *p;
- + 
- + 	d = class_find_device(&pwm_class, NULL, (char *)name, pwm_match_name);
- + 	if (!d) {
- + 		p = ERR_PTR(-EINVAL);
- + 		goto done;
- + 	}
- + 	if (IS_ERR(d)) {
- + 		p = (struct pwm_device *)d;
- + 		goto done;
- + 	}
- + 
- + 	p = __pwm_request(dev_get_drvdata(d), label);
- + 
- + done:
- + 	return p;
- + }
- + 
- + struct pwm_device *pwm_request_byname(const char *name, const char *label)
- + {
- + 	struct pwm_device *p;
- + 
- + 	mutex_lock(&device_list_mutex);
- + 	p = __pwm_request_byname(name, label);
- + 	mutex_unlock(&device_list_mutex);
- + 	return p;
- + }
- + EXPORT_SYMBOL(pwm_request_byname);
- + 
- + struct pwm_device *pwm_request(const char *bus_id, int id, const char *label)
- + {
- + 	char name[256];
- + 	int ret;
- + 
- + 	if (id == -1)
- + 		ret = scnprintf(name, sizeof name, "%s", bus_id);
- + 	else
- + 		ret = scnprintf(name, sizeof name, "%s:%d", bus_id, id);
- + 	if (ret <= 0 || ret >= sizeof name)
- + 		return ERR_PTR(-EINVAL);
- + 
- + 	return pwm_request_byname(name, label);
- + }
- + EXPORT_SYMBOL(pwm_request);
- + 
- + void pwm_release(struct pwm_device *p)
- + {
- + 	mutex_lock(&device_list_mutex);
- + 
- + 	if (!test_and_clear_bit(FLAG_REQUESTED, &p->flags)) {
- + 		pr_debug("%s pwm device is not requested!\n",
- + 				dev_name(p->dev));
- + 		goto done;
- + 	}
- + 
- + 	pwm_stop(p);
- + 	pwm_unsynchronize(p, NULL);
- + 	pwm_set_handler(p, NULL, NULL);
- + 
- + 	p->label = NULL;
- + 	p->pid = -1;
- + 
- + 	if (p->ops->release)
- + 		p->ops->release(p);
- + done:
- + 	mutex_unlock(&device_list_mutex);
- + }
- + EXPORT_SYMBOL(pwm_release);
- + 
- + unsigned long pwm_ns_to_ticks(struct pwm_device *p, unsigned long nsecs)
- + {
- + 	unsigned long long ticks;
- + 
- + 	ticks = nsecs;
- + 	ticks *= p->tick_hz;
- + 	do_div(ticks, 1000000000);
- + 	return ticks;
- + }
- + EXPORT_SYMBOL(pwm_ns_to_ticks);
- + 
- + unsigned long pwm_ticks_to_ns(struct pwm_device *p, unsigned long ticks)
- + {
- + 	unsigned long long ns;
- + 
- + 	if (!p->tick_hz) {
- + 		pr_debug("%s: frequency is zero\n", dev_name(p->dev));
- + 		return 0;
- + 	}
- + 
- + 	ns = ticks;
- + 	ns *= 1000000000UL;
- + 	do_div(ns, p->tick_hz);
- + 	return ns;
- + }
- + EXPORT_SYMBOL(pwm_ticks_to_ns);
- + 
- + static void pwm_config_ns_to_ticks(struct pwm_device *p, struct pwm_config *c)
- + {
- + 	if (test_bit(PWM_CONFIG_PERIOD_NS, &c->config_mask)) {
- + 		c->period_ticks = pwm_ns_to_ticks(p, c->period_ns);
- + 		clear_bit(PWM_CONFIG_PERIOD_NS, &c->config_mask);
- + 		set_bit(PWM_CONFIG_PERIOD_TICKS, &c->config_mask);
- + 	}
- + 
- + 	if (test_bit(PWM_CONFIG_DUTY_NS, &c->config_mask)) {
- + 		c->duty_ticks = pwm_ns_to_ticks(p, c->duty_ns);
- + 		clear_bit(PWM_CONFIG_DUTY_NS, &c->config_mask);
- + 		set_bit(PWM_CONFIG_DUTY_TICKS, &c->config_mask);
- + 	}
- + }
- + 
- + static void pwm_config_percent_to_ticks(struct pwm_device *p,
- + 					struct pwm_config *c)
- + {
- + 	if (test_bit(PWM_CONFIG_DUTY_PERCENT, &c->config_mask)) {
- + 		if (test_bit(PWM_CONFIG_PERIOD_TICKS, &c->config_mask))
- + 			c->duty_ticks = c->period_ticks;
- + 		else
- + 			c->duty_ticks = p->period_ticks;
- + 
- + 		c->duty_ticks *= c->duty_percent;
- + 		c->duty_ticks /= 100;
- + 		clear_bit(PWM_CONFIG_DUTY_PERCENT, &c->config_mask);
- + 		set_bit(PWM_CONFIG_DUTY_TICKS, &c->config_mask);
- + 	}
- + }
- + 
- + int pwm_config_nosleep(struct pwm_device *p, struct pwm_config *c)
- + {
- + 	if (!p->ops->config_nosleep)
- + 		return -EINVAL;
- + 
- + 	pwm_config_ns_to_ticks(p, c);
- + 	pwm_config_percent_to_ticks(p, c);
- + 
- + 	return p->ops->config_nosleep(p, c);
- + }
- + EXPORT_SYMBOL(pwm_config_nosleep);
- + 
- + int pwm_config(struct pwm_device *p, struct pwm_config *c)
- + {
- + 	int ret = 0;
- + 
- + 	pwm_config_ns_to_ticks(p, c);
- + 	pwm_config_percent_to_ticks(p, c);
- + 
- + 	switch (c->config_mask & (BIT(PWM_CONFIG_PERIOD_TICKS)
- + 				  | BIT(PWM_CONFIG_DUTY_TICKS))) {
- + 	case BIT(PWM_CONFIG_PERIOD_TICKS):
- + 		if (p->duty_ticks > c->period_ticks) {
- + 			ret = -EINVAL;
- + 			goto err;
- + 		}
- + 		break;
- + 	case BIT(PWM_CONFIG_DUTY_TICKS):
- + 		if (p->period_ticks < c->duty_ticks) {
- + 			ret = -EINVAL;
- + 			goto err;
- + 		}
- + 		break;
- + 	case BIT(PWM_CONFIG_DUTY_TICKS) | BIT(PWM_CONFIG_PERIOD_TICKS):
- + 		if (c->duty_ticks > c->period_ticks) {
- + 			ret = -EINVAL;
- + 			goto err;
- + 		}
- + 		break;
- + 	default:
- + 		break;
- + 	}
- + 
- + err:
- + 	dev_dbg(p->dev, "%s: config_mask %lu period_ticks %lu duty_ticks %lu"
- + 		" polarity %d duty_ns %lu period_ns %lu duty_percent %d\n",
- + 		__func__, c->config_mask, c->period_ticks, c->duty_ticks,
- + 		c->polarity, c->duty_ns, c->period_ns, c->duty_percent);
- + 
- + 	if (ret)
- + 		return ret;
- + 	spin_lock(&p->pwm_lock);
- + 	ret = p->ops->config(p, c);
- + 	spin_unlock(&p->pwm_lock);
- + 	return ret;
- + }
- + EXPORT_SYMBOL(pwm_config);
- + 
- + int pwm_set_period_ns(struct pwm_device *p, unsigned long period_ns)
- + {
- + 	struct pwm_config c = {
- + 		.config_mask = BIT(PWM_CONFIG_PERIOD_TICKS),
- + 		.period_ticks = pwm_ns_to_ticks(p, period_ns),
- + 	};
- + 
- + 	spin_lock(&p->pwm_lock);
- + 	p->period_ns = period_ns;
- + 	spin_unlock(&p->pwm_lock);
- + 	return pwm_config(p, &c);
- + }
- + EXPORT_SYMBOL(pwm_set_period_ns);
- + 
- + unsigned long pwm_get_period_ns(struct pwm_device *p)
- + {
- + 	return pwm_ticks_to_ns(p, p->period_ticks);
- + }
- + EXPORT_SYMBOL(pwm_get_period_ns);
- + 
- + int pwm_set_frequency(struct pwm_device *p, unsigned long freq)
- + {
- + 	struct pwm_config c;
- + 
- + 	if (!freq)
- + 		return -EINVAL;
- + 
- + 	c.config_mask = BIT(PWM_CONFIG_PERIOD_TICKS),
- + 	c.period_ticks = pwm_ns_to_ticks(p, (NSEC_PER_SEC / freq)),
- + 	spin_lock(&p->pwm_lock);
- + 	p->period_ns = NSEC_PER_SEC / freq;
- + 	spin_unlock(&p->pwm_lock);
- + 	return pwm_config(p, &c);
- + }
- + EXPORT_SYMBOL(pwm_set_frequency);
- + 
- + unsigned long pwm_get_frequency(struct pwm_device *p)
- + {
- + 	unsigned long period_ns;
- + 
- + 	 period_ns = pwm_ticks_to_ns(p, p->period_ticks);
- + 
- + 	if (!period_ns) {
- + 		pr_debug("%s: frequency is zero\n", dev_name(p->dev));
- + 		return 0;
- + 	}
- + 
- + 	return	NSEC_PER_SEC / period_ns;
- + }
- + EXPORT_SYMBOL(pwm_get_frequency);
- + 
- + int pwm_set_period_ticks(struct pwm_device *p,
- + 					unsigned long ticks)
- + {
- + 	struct pwm_config c = {
- + 		.config_mask = BIT(PWM_CONFIG_PERIOD_TICKS),
- + 		.period_ticks = ticks,
- + 	};
- + 
- + 	spin_lock(&p->pwm_lock);
- + 	p->period_ns = pwm_ticks_to_ns(p, ticks);
- + 	spin_unlock(&p->pwm_lock);
- + 	return pwm_config(p, &c);
- + }
- + EXPORT_SYMBOL(pwm_set_period_ticks);
- + 
- + int pwm_set_duty_ns(struct pwm_device *p, unsigned long duty_ns)
- + {
- + 	struct pwm_config c = {
- + 		.config_mask = BIT(PWM_CONFIG_DUTY_TICKS),
- + 		.duty_ticks = pwm_ns_to_ticks(p, duty_ns),
- + 	};
- + 	spin_lock(&p->pwm_lock);
- + 	p->duty_ns = duty_ns;
- + 	spin_unlock(&p->pwm_lock);
- + 	return pwm_config(p, &c);
- + }
- + EXPORT_SYMBOL(pwm_set_duty_ns);
- + 
- + unsigned long pwm_get_duty_ns(struct pwm_device *p)
- + {
- + 	return pwm_ticks_to_ns(p, p->duty_ticks);
- + }
- + EXPORT_SYMBOL(pwm_get_duty_ns);
- + 
- + int pwm_set_duty_percent(struct pwm_device *p, int percent)
- + {
- + 	struct pwm_config c = {
- + 		.config_mask = BIT(PWM_CONFIG_DUTY_PERCENT),
- + 		.duty_percent = percent,
- + 	};
- + 
- + 	spin_lock(&p->pwm_lock);
- + 	p->duty_ns = p->period_ns * percent;
- + 	p->duty_ns /= 100;
- + 	spin_unlock(&p->pwm_lock);
- + 	return pwm_config(p, &c);
- + }
- + EXPORT_SYMBOL(pwm_set_duty_percent);
- + 
- + unsigned long pwm_get_duty_percent(struct pwm_device *p)
- + {
- + 	unsigned long long duty_percent;
- + 
- + 	if (!p->period_ns) {
- + 		pr_debug("%s: frequency is zero\n", dev_name(p->dev));
- + 		return 0;
- + 	}
- + 
- + 	duty_percent = pwm_ticks_to_ns(p, p->duty_ticks);
- + 	duty_percent *= 100;
- + 	do_div(duty_percent, p->period_ns);
- + 	return duty_percent;
- + }
- + EXPORT_SYMBOL(pwm_get_duty_percent);
- + 
- + int pwm_set_duty_ticks(struct pwm_device *p,
- + 					unsigned long ticks)
- + {
- + 	struct pwm_config c = {
- + 		.config_mask = BIT(PWM_CONFIG_DUTY_TICKS),
- + 		.duty_ticks = ticks,
- + 	};
- + 
- + 	spin_lock(&p->pwm_lock);
- + 	p->duty_ns = pwm_ticks_to_ns(p, ticks);
- + 	spin_unlock(&p->pwm_lock);
- + 	return pwm_config(p, &c);
- + }
- + EXPORT_SYMBOL(pwm_set_duty_ticks);
- + 
- + int pwm_set_polarity(struct pwm_device *p, int active_high)
- + {
- + 	struct pwm_config c = {
- + 		.config_mask = BIT(PWM_CONFIG_POLARITY),
- + 		.polarity = active_high,
- + 	};
- + 	return pwm_config(p, &c);
- + }
- + EXPORT_SYMBOL(pwm_set_polarity);
- + 
- + int pwm_start(struct pwm_device *p)
- + {
- + 	struct pwm_config c = {
- + 		.config_mask = BIT(PWM_CONFIG_START),
- + 	};
- + 	return pwm_config(p, &c);
- + }
- + EXPORT_SYMBOL(pwm_start);
- + 
- + int pwm_stop(struct pwm_device *p)
- + {
- + 	struct pwm_config c = {
- + 		.config_mask = BIT(PWM_CONFIG_STOP),
- + 	};
- + 	return pwm_config(p, &c);
- + }
- + EXPORT_SYMBOL(pwm_stop);
- + 
- + int pwm_synchronize(struct pwm_device *p, struct pwm_device *to_p)
- + {
- + 	if (!p->ops->synchronize)
- + 		return -EINVAL;
- + 
- + 	return p->ops->synchronize(p, to_p);
- + }
- + EXPORT_SYMBOL(pwm_synchronize);
- + 
- + int pwm_unsynchronize(struct pwm_device *p, struct pwm_device *from_p)
- + {
- + 	if (!p->ops->unsynchronize)
- + 		return -EINVAL;
- + 
- + 	return p->ops->unsynchronize(p, from_p);
- + }
- + EXPORT_SYMBOL(pwm_unsynchronize);
- + 
- + static void pwm_handler(struct work_struct *w)
- + {
- + 	struct pwm_device *p = container_of(w, struct pwm_device,
- + 					    handler_work);
- + 	if (p->handler && p->handler(p, p->handler_data))
- + 		pwm_stop(p);
- + }
- + 
- + static void __pwm_callback(struct pwm_device *p)
- + {
- + 	queue_work(pwm_handler_workqueue, &p->handler_work);
- + }
- + 
- + int pwm_set_handler(struct pwm_device *p, pwm_handler_t handler, void *data)
- + {
- + 	if (p->ops->set_callback) {
- + 		p->handler_data = data;
- + 		p->handler = handler;
- + 		INIT_WORK(&p->handler_work, pwm_handler);
- + 		return p->ops->set_callback(p, handler ? __pwm_callback : NULL);
- + 	}
- + 	return -EINVAL;
- + }
- + EXPORT_SYMBOL(pwm_set_handler);
- + 
- + static ssize_t pwm_run_show(struct device *dev,
- + 			    struct device_attribute *attr,
- + 			    char *buf)
- + {
- + 	struct pwm_device *p = dev_get_drvdata(dev);
- + 	return sprintf(buf, "%d\n", pwm_is_running(p));
- + }
- + 
- + static ssize_t pwm_run_store(struct device *dev,
- + 			     struct device_attribute *attr,
- + 			     const char *buf, size_t len)
- + {
- + 	struct pwm_device *p = dev_get_drvdata(dev);
- + 	int ret;
- + 
- + 	if (sysfs_streq(buf, "1"))
- + 		ret = pwm_start(p);
- + 	else if (sysfs_streq(buf, "0"))
- + 		ret = pwm_stop(p);
- + 	else
- + 		ret = -EINVAL;
- + 
- + 	if (ret < 0)
- + 		return ret;
- + 	return len;
- + }
- + static DEVICE_ATTR(run, S_IRUGO | S_IWUSR, pwm_run_show, pwm_run_store);
- + 
- + static ssize_t pwm_tick_hz_show(struct device *dev,
- + 				struct device_attribute *attr,
- + 				char *buf)
- + {
- + 	struct pwm_device *p = dev_get_drvdata(dev);
- + 	return sprintf(buf, "%lu\n", p->tick_hz);
- + }
- + static DEVICE_ATTR(tick_hz, S_IRUGO, pwm_tick_hz_show, NULL);
- + 
- + static ssize_t pwm_duty_ns_show(struct device *dev,
- + 				struct device_attribute *attr,
- + 				char *buf)
- + {
- + 	struct pwm_device *p = dev_get_drvdata(dev);
- + 	return sprintf(buf, "%lu\n", pwm_get_duty_ns(p));
- + }
- + 
- + static ssize_t pwm_duty_ns_store(struct device *dev,
- + 				 struct device_attribute *attr,
- + 				 const char *buf, size_t len)
- + {
- + 	unsigned long duty_ns;
- + 	struct pwm_device *p = dev_get_drvdata(dev);
- + 	int ret;
- + 
- + 	if (!kstrtoul(buf, 10, &duty_ns)) {
- + 		ret = pwm_set_duty_ns(p, duty_ns);
- + 
- + 		if (ret < 0)
- + 			return ret;
- + 	}
- + 
- + 	return len;
- + }
- + static DEVICE_ATTR(duty_ns, S_IRUGO | S_IWUSR, pwm_duty_ns_show,
- + 	       pwm_duty_ns_store);
- + 
- + static ssize_t pwm_duty_percent_show(struct device *dev,
- + 				struct device_attribute *attr,
- + 				char *buf)
- + {
- + 	struct pwm_device *p = dev_get_drvdata(dev);
- + 	return sprintf(buf, "%lu\n", pwm_get_duty_percent(p));
- + }
- + 
- + static ssize_t pwm_duty_percent_store(struct device *dev,
- + 				 struct device_attribute *attr,
- + 				 const char *buf,
- + 				 size_t len)
- + {
- + 	unsigned long duty_ns;
- + 	struct pwm_device *p = dev_get_drvdata(dev);
- + 	int ret;
- + 
- + 	if (!kstrtoul(buf, 10, &duty_ns)) {
- + 		ret = pwm_set_duty_percent(p, duty_ns);
- + 
- + 		if (ret < 0)
- + 			return ret;
- + 	}
- + 
- + 	return len;
- + }
- + 
- + static DEVICE_ATTR(duty_percent, S_IRUGO | S_IWUSR, pwm_duty_percent_show,
- + 	       pwm_duty_percent_store);
- + 
- + static ssize_t pwm_period_ns_show(struct device *dev,
- + 				  struct device_attribute *attr,
- + 				  char *buf)
- + {
- + 	struct pwm_device *p = dev_get_drvdata(dev);
- + 	return sprintf(buf, "%lu\n", pwm_get_period_ns(p));
- + }
- + 
- + static ssize_t pwm_period_ns_store(struct device *dev,
- + 				   struct device_attribute *attr,
- + 				   const char *buf, size_t len)
- + {
- + 	unsigned long period_ns;
- + 	struct pwm_device *p = dev_get_drvdata(dev);
- + 	int ret;
- + 
- + 	if (!kstrtoul(buf, 10, &period_ns)) {
- + 		ret = pwm_set_period_ns(p, period_ns);
- + 
- + 		if (ret < 0)
- + 			return ret;
- + 	}
- + 
- + 	return len;
- + }
- + static DEVICE_ATTR(period_ns, S_IRUGO | S_IWUSR, pwm_period_ns_show,
- + 	       pwm_period_ns_store);
- + 
- + static ssize_t pwm_period_freq_show(struct device *dev,
- + 				  struct device_attribute *attr,
- + 				  char *buf)
- + {
- + 	struct pwm_device *p = dev_get_drvdata(dev);
- + 	return sprintf(buf, "%lu\n", pwm_get_frequency(p));
- + }
- + 
- + static ssize_t pwm_period_freq_store(struct device *dev,
- + 				   struct device_attribute *attr,
- + 				   const char *buf,
- + 				   size_t len)
- + {
- + 	unsigned long freq_hz;
- + 	int ret;
- + 
- + 	struct pwm_device *p = dev_get_drvdata(dev);
- + 	if (!kstrtoul(buf, 10, &freq_hz)) {
- + 		ret = pwm_set_frequency(p, freq_hz);
- + 
- + 		if (ret < 0)
- + 			return ret;
- + 	}
- + 	return len;
- + }
- + 
- + static DEVICE_ATTR(period_freq, S_IRUGO | S_IWUSR, pwm_period_freq_show,
- + 	       pwm_period_freq_store);
- + 
- + static ssize_t pwm_polarity_show(struct device *dev,
- + 				 struct device_attribute *attr,
- + 				 char *buf)
- + {
- + 	struct pwm_device *p = dev_get_drvdata(dev);
- + 	return sprintf(buf, "%d\n", p->active_high ? 1 : 0);
- + }
- + 
- + static ssize_t pwm_polarity_store(struct device *dev,
- + 				  struct device_attribute *attr,
- + 				  const char *buf, size_t len)
- + {
- + 	unsigned long polarity;
- + 	struct pwm_device *p = dev_get_drvdata(dev);
- + 	int ret;
- + 
- + 	if (!kstrtoul(buf, 10, &polarity)) {
- + 		ret = pwm_set_polarity(p, polarity);
- + 
- + 		if (ret < 0)
- + 			return ret;
- + 	}
- + 
- + 	return len;
- + }
- + static DEVICE_ATTR(polarity, S_IRUGO | S_IWUSR, pwm_polarity_show,
- + 	       pwm_polarity_store);
- + 
- + static ssize_t pwm_request_show(struct device *dev,
- + 				struct device_attribute *attr,
- + 				char *buf)
- + {
- + 	struct pwm_device *p = dev_get_drvdata(dev);
- + 	int ret;
- + 
- + 	ret = test_bit(FLAG_REQUESTED, &p->flags);
- + 
- + 	if (ret)
- + 		return sprintf(buf, "%s requested by %s\n",
- + 				dev_name(p->dev), p->label);
- + 	else
- + 		return sprintf(buf, "%s is free\n",
- + 				dev_name(p->dev));
- + }
- + 
- + static ssize_t pwm_request_store(struct device *dev,
- + 				 struct device_attribute *attr,
- + 				 const char *buf, size_t len)
- + {
- + 	struct pwm_device *p = dev_get_drvdata(dev);
- + 	unsigned long request;
- + 	struct pwm_device *ret;
- + 
- + 	if (!kstrtoul(buf, 10, &request)) {
- + 		if (request) {
- + 			mutex_lock(&device_list_mutex);
- + 			ret = __pwm_request(p, REQUEST_SYSFS);
- + 			mutex_unlock(&device_list_mutex);
- + 
- + 			if (IS_ERR(ret))
- + 				return PTR_ERR(ret);
- + 		} else
- + 			pwm_release(p);
- + 	}
- + 
- + 	return len;
- + }
- + static DEVICE_ATTR(request, S_IRUGO | S_IWUSR, pwm_request_show,
- + 	       pwm_request_store);
- + 
- + static const struct attribute *pwm_attrs[] = {
- + 	&dev_attr_tick_hz.attr,
- + 	&dev_attr_run.attr,
- + 	&dev_attr_polarity.attr,
- + 	&dev_attr_duty_ns.attr,
- + 	&dev_attr_period_ns.attr,
- + 	&dev_attr_request.attr,
- + 	&dev_attr_duty_percent.attr,
- + 	&dev_attr_period_freq.attr,
- + 	NULL,
- + };
- + 
- + static const struct attribute_group pwm_device_attr_group = {
- + 	.attrs = (struct attribute **) pwm_attrs,
- + };
- + 
- + static struct class_attribute pwm_class_attrs[] = {
- + 	__ATTR_NULL,
- + };
- + 
- + static struct class pwm_class = {
- + 	.name = "pwm",
- + 	.owner = THIS_MODULE,
- + 
- + 	.class_attrs = pwm_class_attrs,
- + };
- + 
- + static int pwm_freq_transition_notifier_cb(struct notifier_block *nb,
- + 		unsigned long val, void *data)
- + {
- + 	struct pwm_device *p;
- + 
- + 	p = container_of(nb, struct pwm_device, freq_transition);
- + 
- + 	if (val == CPUFREQ_POSTCHANGE && pwm_is_requested(p))
- + 		p->ops->freq_transition_notifier_cb(p);
- + 
- + 	return 0;
- + }
- + 
- + static inline int pwm_cpufreq_notifier_register(struct pwm_device *p)
- + {
- + 	p->freq_transition.notifier_call = pwm_freq_transition_notifier_cb;
- + 
- + 	return cpufreq_register_notifier(&p->freq_transition,
- + 		       CPUFREQ_TRANSITION_NOTIFIER);
- + }
- + 
- + int pwm_register_byname(struct pwm_device *p, struct device *parent,
- + 			const char *name)
- + {
- + 	struct device *d;
- + 	int ret;
- + 
- + 	if (!p->ops || !p->ops->config)
- + 		return -EINVAL;
- + 
- + 	mutex_lock(&device_list_mutex);
- + 
- + 	d = class_find_device(&pwm_class, NULL, (char *)name, pwm_match_name);
- + 	if (d) {
- + 		ret = -EEXIST;
- + 		goto err_found_device;
- + 	}
- + 
- + 	p->dev = device_create(&pwm_class, parent, MKDEV(0, 0), NULL, name);
- + 	if (IS_ERR(p->dev)) {
- + 		ret = PTR_ERR(p->dev);
- + 		goto err_device_create;
- + 	}
- + 
- + 	ret = sysfs_create_group(&p->dev->kobj, &pwm_device_attr_group);
- + 	if (ret)
- + 		goto err_create_group;
- + 
- + 	dev_set_drvdata(p->dev, p);
- + 	p->flags = BIT(FLAG_REGISTERED);
- + 
- + 	ret = pwm_cpufreq_notifier_register(p);
- + 
- + 	if (ret < 0)
- + 		printk(KERN_ERR "Failed to add cpufreq notifier\n");
- + 
- + 	spin_lock_init(&p->pwm_lock);
- + 	goto done;
- + 
- + err_create_group:
- + 	device_unregister(p->dev);
- + 	p->flags = 0;
- + 
- + err_device_create:
- + err_found_device:
- + done:
- + 	mutex_unlock(&device_list_mutex);
- + 
- + 	return ret;
- + }
- + EXPORT_SYMBOL(pwm_register_byname);
- + 
- + int pwm_register(struct pwm_device *p, struct device *parent, int id)
- + {
- + 	int ret;
- + 	char name[256];
- + 
- + 	if (IS_ERR_OR_NULL(parent))
- + 		return -EINVAL;
- + 
- + 	if (id == -1)
- + 		ret = scnprintf(name, sizeof name, "%s", dev_name(parent));
- + 	else
- + 		ret = scnprintf(name, sizeof name, "%s:%d",
- + 			       dev_name(parent), id);
- + 	if (ret <= 0 || ret >= sizeof name)
- + 		return -EINVAL;
- + 
- + 	return pwm_register_byname(p, parent, name);
- + }
- + EXPORT_SYMBOL(pwm_register);
- + 
- + int pwm_unregister(struct pwm_device *p)
- + {
- + 	int ret = 0;
- + 
- + 	mutex_lock(&device_list_mutex);
- + 
- + 	if (pwm_is_running(p) || pwm_is_requested(p)) {
- + 		ret = -EBUSY;
- + 		goto done;
- + 	}
- + 
- + 	sysfs_remove_group(&p->dev->kobj, &pwm_device_attr_group);
- + 	device_unregister(p->dev);
- + 	p->flags = 0;
- + 
- + done:
- + 	mutex_unlock(&device_list_mutex);
- + 
- + 	return ret;
- + }
- + EXPORT_SYMBOL(pwm_unregister);
- + 
- + static int __init pwm_init(void)
- + {
- + 	return class_register(&pwm_class);
- + }
- + 
- + static void __exit pwm_exit(void)
- + {
- + 	class_unregister(&pwm_class);
- + }
- + 
- + #ifdef MODULE
- + module_init(pwm_init);
- + module_exit(pwm_exit);
- + MODULE_LICENSE("GPL");
- + #else
- + postcore_initcall(pwm_init);
- + #endif
- diff -crN linux-3.2.1_o/drivers/regulator/core.c linux-3.2.1/drivers/regulator/core.c
- *** linux-3.2.1_o/drivers/regulator/core.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/regulator/core.c	2014-05-15 13:25:14.630985013 +0900
- ***************
- *** 169,174 ****
- --- 169,177 ----
-   {
-   	struct regulator *regulator;
-   
- +         if (rdev->ignore_check_consumers)
- +                 return 0;
- + 
-   	list_for_each_entry(regulator, &rdev->consumer_list, list) {
-   		/*
-   		 * Assume consumers that didn't say anything are OK
- ***************
- *** 1768,1810 ****
-   			}
-   		}
-   
-   		/*
-   		 * If we can't obtain the old selector there is not enough
-   		 * info to call set_voltage_time_sel().
-   		 */
-   		if (rdev->desc->ops->set_voltage_time_sel &&
-   		    rdev->desc->ops->get_voltage_sel) {
- ! 			unsigned int old_selector = 0;
-   
- - 			ret = rdev->desc->ops->get_voltage_sel(rdev);
- - 			if (ret < 0)
- - 				return ret;
- - 			old_selector = ret;
-   			delay = rdev->desc->ops->set_voltage_time_sel(rdev,
-   						old_selector, selector);
-   		}
-   
- ! 		if (best_val != INT_MAX) {
- ! 			ret = rdev->desc->ops->set_voltage_sel(rdev, selector);
- ! 			selector = best_val;
- ! 		} else {
- ! 			ret = -EINVAL;
-   		}
- - 	} else {
- - 		ret = -EINVAL;
- - 	}
-   
- - 	/* Insert any necessary delays */
- - 	if (delay >= 1000) {
- - 		mdelay(delay / 1000);
- - 		udelay(delay % 1000);
- - 	} else if (delay) {
- - 		udelay(delay);
- - 	}
- - 
- - 	if (ret == 0)
-   		_notifier_call_chain(rdev, REGULATOR_EVENT_VOLTAGE_CHANGE,
- ! 				     NULL);
-   
-   	trace_regulator_set_voltage_complete(rdev_get_name(rdev), selector);
-   
- --- 1771,1819 ----
-   			}
-   		}
-   
- + 		if (best_val != INT_MAX) {
- + 			ret = rdev->desc->ops->set_voltage_sel(rdev, selector);
- + 			selector = best_val;
- + 		} else {
- + 			ret = -EINVAL;
- + 		}
- + 	} else {
- + 		ret = -EINVAL;
- + 	}
- + 
- + 	if (ret == 0) {
-   		/*
-   		 * If we can't obtain the old selector there is not enough
-   		 * info to call set_voltage_time_sel().
-   		 */
-   		if (rdev->desc->ops->set_voltage_time_sel &&
-   		    rdev->desc->ops->get_voltage_sel) {
- ! 			int old_selector;
- ! 
- ! 			old_selector = rdev->desc->ops->get_voltage_sel(rdev);
- ! 			if (old_selector < 0)
- ! 				return old_selector;
-   
-   			delay = rdev->desc->ops->set_voltage_time_sel(rdev,
-   						old_selector, selector);
- + 			if (delay < 0) {
- + 				delay = 0;
- + 				rdev_warn(rdev, "set_voltage_time_sel() failed"
- + 							": %d\n", ret);
- + 			}
-   		}
-   
- ! 		/* Insert any necessary delays */
- ! 		if (delay >= 1000) {
- ! 			mdelay(delay / 1000);
- ! 			udelay(delay % 1000);
- ! 		} else if (delay) {
- ! 			udelay(delay);
-   		}
-   
-   		_notifier_call_chain(rdev, REGULATOR_EVENT_VOLTAGE_CHANGE,
- ! 					NULL);
- ! 	}
-   
-   	trace_regulator_set_voltage_complete(rdev_get_name(rdev), selector);
-   
- ***************
- *** 2682,2687 ****
- --- 2691,2697 ----
-   	rdev->reg_data = driver_data;
-   	rdev->owner = regulator_desc->owner;
-   	rdev->desc = regulator_desc;
- +         rdev->ignore_check_consumers = init_data->ignore_check_consumers;
-   	INIT_LIST_HEAD(&rdev->consumer_list);
-   	INIT_LIST_HEAD(&rdev->list);
-   	BLOCKING_INIT_NOTIFIER_HEAD(&rdev->notifier);
- diff -crN linux-3.2.1_o/drivers/regulator/Kconfig linux-3.2.1/drivers/regulator/Kconfig
- *** linux-3.2.1_o/drivers/regulator/Kconfig	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/regulator/Kconfig	2014-05-15 13:25:14.630985013 +0900
- ***************
- *** 259,264 ****
- --- 259,273 ----
-   	  three step-down converters and two general-purpose LDO voltage regulators.
-   	  It supports TI's software based Class-2 SmartReflex implementation.
-   
- + config REGULATOR_TPS65217
- + 	tristate "TI TPS65217 Power regulators"
- + 	depends on MFD_TPS65217
- + 	help
- + 	  This driver supports TPS65217 voltage regulator chips. TPS65217
- + 	  provides three step-down converters and four general-purpose LDO
- + 	  voltage regulators. It supports software based voltage control
- + 	  for different voltage domains
- + 
-   config REGULATOR_TPS65912
-   	tristate "TI TPS65912 Power regulator"
-   	depends on (MFD_TPS65912_I2C || MFD_TPS65912_SPI)
- diff -crN linux-3.2.1_o/drivers/regulator/Makefile linux-3.2.1/drivers/regulator/Makefile
- *** linux-3.2.1_o/drivers/regulator/Makefile	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/regulator/Makefile	2014-05-15 13:25:14.630985013 +0900
- ***************
- *** 38,43 ****
- --- 38,44 ----
-   obj-$(CONFIG_REGULATOR_TPS6105X) += tps6105x-regulator.o
-   obj-$(CONFIG_REGULATOR_TPS65023) += tps65023-regulator.o
-   obj-$(CONFIG_REGULATOR_TPS6507X) += tps6507x-regulator.o
- + obj-$(CONFIG_REGULATOR_TPS65217) += tps65217-regulator.o
-   obj-$(CONFIG_REGULATOR_TPS6524X) += tps6524x-regulator.o
-   obj-$(CONFIG_REGULATOR_TPS65912) += tps65912-regulator.o
-   obj-$(CONFIG_REGULATOR_88PM8607) += 88pm8607.o
- diff -crN linux-3.2.1_o/drivers/regulator/tps65217-regulator.c linux-3.2.1/drivers/regulator/tps65217-regulator.c
- *** linux-3.2.1_o/drivers/regulator/tps65217-regulator.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/drivers/regulator/tps65217-regulator.c	2014-05-15 13:25:14.634708883 +0900
- ***************
- *** 0 ****
- --- 1,514 ----
- + /*
- +  * tps65217-regulator.c
- +  *
- +  * Regulator driver for TPS65217 PMIC
- +  *
- +  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #include <linux/kernel.h>
- + #include <linux/module.h>
- + #include <linux/device.h>
- + #include <linux/init.h>
- + #include <linux/err.h>
- + #include <linux/platform_device.h>
- + 
- + #include <linux/regulator/driver.h>
- + #include <linux/regulator/machine.h>
- + #include <linux/mfd/tps65217.h>
- + 
- + #define TPS65217_REGULATOR(_name, _id, _ops, _n)	\
- + 	{						\
- + 		.name		= _name,		\
- + 		.id		= _id,			\
- + 		.ops		= &_ops,		\
- + 		.n_voltages	= _n,			\
- + 		.type		= REGULATOR_VOLTAGE,	\
- + 		.owner		= THIS_MODULE,		\
- + 	}						\
- + 
- + #define TPS65217_INFO(_nm, _min, _max, _f1, _f2, _t, _n, _em, _vr, _vm)	\
- + 	{						\
- + 		.name		= _nm,			\
- + 		.min_uV		= _min,			\
- + 		.max_uV		= _max,			\
- + 		.vsel_to_uv	= _f1,			\
- + 		.uv_to_vsel	= _f2,			\
- + 		.table		= _t,			\
- + 		.table_len	= _n,			\
- + 		.enable_mask	= _em,			\
- + 		.set_vout_reg	= _vr,			\
- + 		.set_vout_mask	= _vm,			\
- + 	}
- + 
- + static const int LDO1_VSEL_table[] = {
- + 	1000000, 1100000, 1200000, 1250000,
- + 	1300000, 1350000, 1400000, 1500000,
- + 	1600000, 1800000, 2500000, 2750000,
- + 	2800000, 3000000, 3100000, 3300000,
- + };
- + 
- + static int tps65217_vsel_to_uv1(unsigned int vsel)
- + {
- + 	int uV = 0;
- + 
- + 	if (vsel > 63)
- + 		return -EINVAL;
- + 
- + 	if (vsel <= 24)
- + 		uV = vsel * 25000 + 900000;
- + 	else if (vsel <= 52)
- + 		uV = (vsel - 24) * 50000 + 1500000;
- + 	else if (vsel < 56)
- + 		uV = (vsel - 52) * 100000 + 2900000;
- + 	else
- + 		uV = 3300000;
- + 
- + 	return uV;
- + }
- + 
- + static int tps65217_uv_to_vsel1(int uV, unsigned int *vsel)
- + {
- + 	if ((uV < 0) && (uV > 3300000))
- + 		return -EINVAL;
- + 
- + 	if (uV <= 1500000)
- + 		*vsel = (uV - 875001) / 25000;
- + 	else if (uV <= 2900000)
- + 		*vsel = 24 + (uV - 1450001) / 50000;
- + 	else if (uV < 3300000)
- + 		*vsel = 52 + (uV - 2800001) / 100000;
- + 	else
- + 		*vsel = 56;
- + 
- + 	return 0;
- + }
- + 
- + static int tps65217_vsel_to_uv2(unsigned int vsel)
- + {
- + 	int uV = 0;
- + 
- + 	if (vsel > 31)
- + 		return -EINVAL;
- + 
- + 	if (vsel <= 8)
- + 		uV = vsel * 50000 + 1500000;
- + 	else if (vsel <= 13)
- + 		uV = (vsel - 8) * 100000 + 1900000;
- + 	else
- + 		uV = (vsel - 13) * 50000 + 2400000;
- + 
- + 	return uV;
- + }
- + 
- + static int tps65217_uv_to_vsel2(int uV, unsigned int *vsel)
- + {
- + 	if ((uV < 0) && (uV > 3300000))
- + 		return -EINVAL;
- + 
- + 	if (uV <= 1900000)
- + 		*vsel = (uV - 1450001) / 50000;
- + 	else if (uV <= 2400000)
- + 		*vsel = 8 + (uV - 1800001) / 100000;
- + 	else
- + 		*vsel = 13 + (uV - 2350001) / 50000;
- + 
- + 	return 0;
- + }
- + 
- + static struct tps_info tps65217_pmic_regs[] = {
- + 	TPS65217_INFO("DCDC1", 900000, 1800000, tps65217_vsel_to_uv1,
- + 			tps65217_uv_to_vsel1, NULL, 64, TPS65217_ENABLE_DC1_EN,
- + 			TPS65217_REG_DEFDCDC1, TPS65217_DEFDCDCX_DCDC_MASK),
- + 	TPS65217_INFO("DCDC2", 900000, 3300000, tps65217_vsel_to_uv1,
- + 			tps65217_uv_to_vsel1, NULL, 64, TPS65217_ENABLE_DC2_EN,
- + 			TPS65217_REG_DEFDCDC2, TPS65217_DEFDCDCX_DCDC_MASK),
- + 	TPS65217_INFO("DCDC3", 900000, 1500000, tps65217_vsel_to_uv1,
- + 			tps65217_uv_to_vsel1, NULL, 64, TPS65217_ENABLE_DC3_EN,
- + 			TPS65217_REG_DEFDCDC3, TPS65217_DEFDCDCX_DCDC_MASK),
- + 	TPS65217_INFO("LDO1", 1000000, 3300000, NULL, NULL, LDO1_VSEL_table,
- + 			16, TPS65217_ENABLE_LDO1_EN, TPS65217_REG_DEFLDO1,
- + 			TPS65217_DEFLDO1_LDO1_MASK),
- + 	TPS65217_INFO("LDO2", 900000, 3300000, tps65217_vsel_to_uv1,
- + 			tps65217_uv_to_vsel1, NULL, 64, TPS65217_ENABLE_LDO2_EN,
- + 			TPS65217_REG_DEFLDO2, TPS65217_DEFLDO2_LDO2_MASK),
- + 	TPS65217_INFO("LDO3", 1800000, 3300000, tps65217_vsel_to_uv2,
- + 			tps65217_uv_to_vsel2, NULL, 32,
- + 			TPS65217_ENABLE_LS1_EN | TPS65217_DEFLDO3_LDO3_EN,
- + 			TPS65217_REG_DEFLS1, TPS65217_DEFLDO3_LDO3_MASK),
- + 	TPS65217_INFO("LDO4", 1800000, 3300000, tps65217_vsel_to_uv2,
- + 			tps65217_uv_to_vsel2, NULL, 32,
- + 			TPS65217_ENABLE_LS2_EN | TPS65217_DEFLDO4_LDO4_EN,
- + 			TPS65217_REG_DEFLS2, TPS65217_DEFLDO4_LDO4_MASK),
- + };
- + 
- + static int tps65217_pmic_dcdc_is_enabled(struct regulator_dev *dev)
- + {
- + 	int ret;
- + 	struct tps65217 *tps = rdev_get_drvdata(dev);
- + 	unsigned int data, dcdc = rdev_get_id(dev);
- + 
- + 	if (dcdc < TPS65217_DCDC_1 || dcdc > TPS65217_DCDC_3)
- + 		return -EINVAL;
- + 
- + 	ret = tps65217_reg_read(tps, TPS65217_REG_ENABLE, &data);
- + 	if (ret)
- + 		return ret;
- + 
- + 	return (data & tps->info[dcdc]->enable_mask) ? 1 : 0;
- + }
- + 
- + static int tps65217_pmic_ldo_is_enabled(struct regulator_dev *dev)
- + {
- + 	int ret;
- + 	struct tps65217 *tps = rdev_get_drvdata(dev);
- + 	unsigned int data, ldo = rdev_get_id(dev);
- + 
- + 	if (ldo < TPS65217_LDO_1 || ldo > TPS65217_LDO_4)
- + 		return -EINVAL;
- + 
- + 	ret = tps65217_reg_read(tps, TPS65217_REG_ENABLE, &data);
- + 	if (ret)
- + 		return ret;
- + 
- + 	return (data & tps->info[ldo]->enable_mask) ? 1 : 0;
- + }
- + 
- + static int tps65217_pmic_dcdc_enable(struct regulator_dev *dev)
- + {
- + 	struct tps65217 *tps = rdev_get_drvdata(dev);
- + 	unsigned int dcdc = rdev_get_id(dev);
- + 
- + 	if (dcdc < TPS65217_DCDC_1 || dcdc > TPS65217_DCDC_3)
- + 		return -EINVAL;
- + 
- + 	/* Enable the regulator and password protection is level 1 */
- + 	return tps65217_set_bits(tps, TPS65217_REG_ENABLE,
- + 				tps->info[dcdc]->enable_mask,
- + 				tps->info[dcdc]->enable_mask,
- + 				TPS65217_PROTECT_L1);
- + }
- + 
- + static int tps65217_pmic_dcdc_disable(struct regulator_dev *dev)
- + {
- + 	struct tps65217 *tps = rdev_get_drvdata(dev);
- + 	unsigned int dcdc = rdev_get_id(dev);
- + 
- + 	if (dcdc < TPS65217_DCDC_1 || dcdc > TPS65217_DCDC_3)
- + 		return -EINVAL;
- + 
- + 	/* Disable the regulator and password protection is level 1 */
- + 	return tps65217_clear_bits(tps, TPS65217_REG_ENABLE,
- + 			tps->info[dcdc]->enable_mask, TPS65217_PROTECT_L1);
- + }
- + 
- + static int tps65217_pmic_ldo_enable(struct regulator_dev *dev)
- + {
- + 	struct tps65217 *tps = rdev_get_drvdata(dev);
- + 	unsigned int ldo = rdev_get_id(dev);
- + 
- + 	if (ldo < TPS65217_LDO_1 || ldo > TPS65217_LDO_4)
- + 		return -EINVAL;
- + 
- + 	/* Enable the regulator and password protection is level 1 */
- + 	return tps65217_set_bits(tps, TPS65217_REG_ENABLE,
- + 				tps->info[ldo]->enable_mask,
- + 				tps->info[ldo]->enable_mask,
- + 				TPS65217_PROTECT_L1);
- + }
- + 
- + static int tps65217_pmic_ldo_disable(struct regulator_dev *dev)
- + {
- + 	struct tps65217 *tps = rdev_get_drvdata(dev);
- + 	unsigned int ldo = rdev_get_id(dev);
- + 
- + 	if (ldo < TPS65217_LDO_1 || ldo > TPS65217_LDO_4)
- + 		return -EINVAL;
- + 
- + 	/* Disable the regulator and password protection is level 1 */
- + 	return tps65217_clear_bits(tps, TPS65217_REG_ENABLE,
- + 			tps->info[ldo]->enable_mask, TPS65217_PROTECT_L1);
- + }
- + 
- + static int tps65217_pmic_dcdc_get_voltage_sel(struct regulator_dev *dev)
- + {
- + 	int ret;
- + 	struct tps65217 *tps = rdev_get_drvdata(dev);
- + 	unsigned int selector, dcdc = rdev_get_id(dev);
- + 
- + 	if (dcdc < TPS65217_DCDC_1 || dcdc > TPS65217_DCDC_3)
- + 		return -EINVAL;
- + 
- + 	ret = tps65217_reg_read(tps, tps->info[dcdc]->set_vout_reg, &selector);
- + 	if (ret)
- + 		return ret;
- + 
- + 	selector &= tps->info[dcdc]->set_vout_mask;
- + 
- + 	return selector;
- + }
- + 
- + static int tps65217_pmic_dcdc_set_voltage(struct regulator_dev *dev,
- + 				  int min_uV, int max_uV, unsigned *selector)
- + {
- + 	int ret;
- + 	struct tps65217 *tps = rdev_get_drvdata(dev);
- + 	unsigned int dcdc = rdev_get_id(dev);
- + 
- + 	if (dcdc < TPS65217_DCDC_1 || dcdc > TPS65217_DCDC_3)
- + 		return -EINVAL;
- + 
- + 	if (min_uV < tps->info[dcdc]->min_uV
- + 		|| min_uV > tps->info[dcdc]->max_uV)
- + 		return -EINVAL;
- + 
- + 	if (max_uV < tps->info[dcdc]->min_uV
- + 		|| max_uV > tps->info[dcdc]->max_uV)
- + 		return -EINVAL;
- + 
- + 	ret = tps->info[dcdc]->uv_to_vsel(min_uV, selector);
- + 	if (ret)
- + 		return ret;
- + 
- + 	/* Set the voltage based on vsel value and write protect level is 2 */
- + 	ret = tps65217_set_bits(tps, tps->info[dcdc]->set_vout_reg,
- + 					tps->info[dcdc]->set_vout_mask,
- + 					*selector, TPS65217_PROTECT_L2);
- + 	if (ret)
- + 		return ret;
- + 
- + 	/* Set GO bit to initiate voltage transistion */
- + 	return tps65217_set_bits(tps, TPS65217_REG_DEFSLEW,
- + 				TPS65217_DEFSLEW_GO, TPS65217_DEFSLEW_GO,
- + 				TPS65217_PROTECT_L2);
- + }
- + 
- + static int tps65217_pmic_ldo_get_voltage_sel(struct regulator_dev *dev)
- + {
- + 	int ret;
- + 	struct tps65217 *tps = rdev_get_drvdata(dev);
- + 	unsigned int selector, ldo = rdev_get_id(dev);
- + 
- + 	if (ldo < TPS65217_LDO_1 || ldo > TPS65217_LDO_4)
- + 		return -EINVAL;
- + 
- + 	ret = tps65217_reg_read(tps, tps->info[ldo]->set_vout_reg, &selector);
- + 	if (ret)
- + 		return ret;
- + 
- + 	selector &= tps->info[ldo]->set_vout_mask;
- + 
- + 	return selector;
- + }
- + 
- + static int tps65217_pmic_ldo_set_voltage_sel(struct regulator_dev *dev,
- + 						unsigned selector)
- + {
- + 	struct tps65217 *tps = rdev_get_drvdata(dev);
- + 	int ldo = rdev_get_id(dev);
- + 
- + 	if (ldo != TPS65217_LDO_1)
- + 		return -EINVAL;
- + 
- + 	if (selector >= tps->info[ldo]->table_len)
- + 		return -EINVAL;
- + 
- + 	/* Set the voltage based on vsel value and write protect level is 2 */
- + 	return tps65217_set_bits(tps, tps->info[ldo]->set_vout_reg,
- + 					tps->info[ldo]->set_vout_mask,
- + 					selector, TPS65217_PROTECT_L2);
- + }
- + 
- + static int tps65217_pmic_ldo_set_voltage(struct regulator_dev *dev,
- + 				  int min_uV, int max_uV, unsigned *selector)
- + {
- + 	int ret;
- + 	struct tps65217 *tps = rdev_get_drvdata(dev);
- + 	unsigned int ldo = rdev_get_id(dev);
- + 
- + 	if (ldo < TPS65217_LDO_2 || ldo > TPS65217_LDO_4)
- + 		return -EINVAL;
- + 
- + 	if (min_uV < tps->info[ldo]->min_uV
- + 		|| min_uV > tps->info[ldo]->max_uV)
- + 		return -EINVAL;
- + 
- + 	if (max_uV < tps->info[ldo]->min_uV
- + 		|| max_uV > tps->info[ldo]->max_uV)
- + 		return -EINVAL;
- + 
- + 	ret = tps->info[ldo]->uv_to_vsel(min_uV, selector);
- + 	if (ret)
- + 		return ret;
- + 
- + 	/* Set the voltage based on vsel value and write protect level is 2 */
- + 	return tps65217_set_bits(tps, tps->info[ldo]->set_vout_reg,
- + 					tps->info[ldo]->set_vout_mask,
- + 					*selector, TPS65217_PROTECT_L2);
- + }
- + 
- + static int tps65217_pmic_dcdc_list_voltage(struct regulator_dev *dev,
- + 					unsigned selector)
- + {
- + 	struct tps65217 *tps = rdev_get_drvdata(dev);
- + 	unsigned int dcdc = rdev_get_id(dev);
- + 
- + 	if (dcdc < TPS65217_DCDC_1 || dcdc > TPS65217_DCDC_3)
- + 		return -EINVAL;
- + 
- + 	if (selector >= tps->info[dcdc]->table_len)
- + 		return -EINVAL;
- + 
- + 	return tps->info[dcdc]->vsel_to_uv(selector);
- + }
- + 
- + static int tps65217_pmic_ldo_list_voltage(struct regulator_dev *dev,
- + 					unsigned selector)
- + {
- + 	struct tps65217 *tps = rdev_get_drvdata(dev);
- + 	unsigned int ldo = rdev_get_id(dev);
- + 
- + 	if (ldo < TPS65217_LDO_1 || ldo > TPS65217_LDO_4)
- + 		return -EINVAL;
- + 
- + 	if (selector >= tps->info[ldo]->table_len)
- + 		return -EINVAL;
- + 
- + 	if (tps->info[ldo]->table)
- + 		return tps->info[ldo]->table[selector];
- + 
- + 	return tps->info[ldo]->vsel_to_uv(selector);
- + }
- + 
- + static int tps65217_pmic_dcdc_set_voltage_time_sel(struct regulator_dev *dev,
- + 			unsigned int old_sel, unsigned int new_sel)
- + {
- + 	struct tps65217 *tps = rdev_get_drvdata(dev);
- + 	unsigned int dcdc = rdev_get_id(dev);
- + 	int ret;
- + 
- + 	/* If the regulator isn't on, it won't take time here */
- + 	ret = tps65217_pmic_dcdc_is_enabled(dev);
- + 	if (!ret || ret < 0)
- + 		return ret;
- + 
- + 	return tps->info[dcdc]->delay;
- + }
- + 
- + /* Operations permitted on DCDCx */
- + static struct regulator_ops tps65217_pmic_dcdc_ops = {
- + 	.is_enabled		= tps65217_pmic_dcdc_is_enabled,
- + 	.enable			= tps65217_pmic_dcdc_enable,
- + 	.disable		= tps65217_pmic_dcdc_disable,
- + 	.get_voltage_sel	= tps65217_pmic_dcdc_get_voltage_sel,
- + 	.set_voltage		= tps65217_pmic_dcdc_set_voltage,
- + 	.list_voltage		= tps65217_pmic_dcdc_list_voltage,
- + 	.set_voltage_time_sel	= tps65217_pmic_dcdc_set_voltage_time_sel,
- + };
- + 
- + /* Operations permitted on LDO1 */
- + static struct regulator_ops tps65217_pmic_ldo1_ops = {
- + 	.is_enabled		= tps65217_pmic_ldo_is_enabled,
- + 	.enable			= tps65217_pmic_ldo_enable,
- + 	.disable		= tps65217_pmic_ldo_disable,
- + 	.get_voltage_sel	= tps65217_pmic_ldo_get_voltage_sel,
- + 	.set_voltage_sel	= tps65217_pmic_ldo_set_voltage_sel,
- + 	.list_voltage		= tps65217_pmic_ldo_list_voltage,
- + };
- + 
- + /* Operations permitted on LDO2, LDO3 and LDO4 */
- + static struct regulator_ops tps65217_pmic_ldo234_ops = {
- + 	.is_enabled		= tps65217_pmic_ldo_is_enabled,
- + 	.enable			= tps65217_pmic_ldo_enable,
- + 	.disable		= tps65217_pmic_ldo_disable,
- + 	.get_voltage_sel	= tps65217_pmic_ldo_get_voltage_sel,
- + 	.set_voltage		= tps65217_pmic_ldo_set_voltage,
- + 	.list_voltage		= tps65217_pmic_ldo_list_voltage,
- + };
- + 
- + static struct regulator_desc regulators[] = {
- + 	TPS65217_REGULATOR("DCDC1", TPS65217_DCDC_1,
- + 				tps65217_pmic_dcdc_ops, 64),
- + 	TPS65217_REGULATOR("DCDC2",TPS65217_DCDC_2,
- + 				tps65217_pmic_dcdc_ops, 64),
- + 	TPS65217_REGULATOR("DCDC3", TPS65217_DCDC_3,
- + 				tps65217_pmic_dcdc_ops, 64),
- + 	TPS65217_REGULATOR("LDO1", TPS65217_LDO_1,
- + 				tps65217_pmic_ldo1_ops, 16),
- + 	TPS65217_REGULATOR("LDO2", TPS65217_LDO_2,
- + 				tps65217_pmic_ldo234_ops, 64),
- + 	TPS65217_REGULATOR("LDO3", TPS65217_LDO_3,
- + 				tps65217_pmic_ldo234_ops, 32),
- + 	TPS65217_REGULATOR("LDO4", TPS65217_LDO_4,
- + 				tps65217_pmic_ldo234_ops, 32),
- + };
- + 
- + static int __devinit tps65217_regulator_probe(struct platform_device *pdev)
- + {
- + 	struct regulator_dev *rdev;
- + 	struct tps65217 *tps;
- + 	struct tps_info *info = &tps65217_pmic_regs[pdev->id];
- + 	const struct regulator_init_data *init_data = pdev->dev.platform_data;
- + 	struct tps65217_rdelay *pd = init_data->driver_data;
- + 
- + 	/* Already set by core driver */
- + 	tps = dev_to_tps65217(pdev->dev.parent);
- + 	tps->info[pdev->id] = info;
- + 
- + 	if (pd)
- + 		tps->info[pdev->id]->delay = pd->ramp_delay;
- + 
- + 	rdev = regulator_register(&regulators[pdev->id], &pdev->dev,
- + 				  pdev->dev.platform_data, tps);
- + 	if (IS_ERR(rdev))
- + 		return PTR_ERR(rdev);
- + 
- + 	platform_set_drvdata(pdev, rdev);
- + 
- + 	return 0;
- + }
- + 
- + static int __devexit tps65217_regulator_remove(struct platform_device *pdev)
- + {
- + 	struct regulator_dev *rdev = platform_get_drvdata(pdev);
- + 
- + 	platform_set_drvdata(pdev, NULL);
- + 	regulator_unregister(rdev);
- + 
- + 	return 0;
- + }
- + 
- + static struct platform_driver tps65217_regulator_driver = {
- + 	.driver = {
- + 		.name = "tps65217-pmic",
- + 	},
- + 	.probe = tps65217_regulator_probe,
- + 	.remove = __devexit_p(tps65217_regulator_remove),
- + };
- + 
- + static int __init tps65217_regulator_init(void)
- + {
- + 	return platform_driver_register(&tps65217_regulator_driver);
- + }
- + subsys_initcall(tps65217_regulator_init);
- + 
- + static void __exit tps65217_regulator_exit(void)
- + {
- + 	platform_driver_unregister(&tps65217_regulator_driver);
- + }
- + module_exit(tps65217_regulator_exit);
- + 
- + 
- + MODULE_AUTHOR("AnilKumar Ch <anilkumar@ti.com>");
- + MODULE_DESCRIPTION("TPS65217 voltage regulator driver");
- + MODULE_ALIAS("platform:tps65217-pmic");
- + MODULE_LICENSE("GPL v2");
- diff -crN linux-3.2.1_o/drivers/rtc/Kconfig linux-3.2.1/drivers/rtc/Kconfig
- *** linux-3.2.1_o/drivers/rtc/Kconfig	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/rtc/Kconfig	2014-05-15 13:25:14.711692831 +0900
- ***************
- *** 733,739 ****
-   
-   config RTC_DRV_OMAP
-   	tristate "TI OMAP1"
- ! 	depends on ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_DAVINCI_DA8XX
-   	help
-   	  Say "yes" here to support the real time clock on TI OMAP1 and
-   	  DA8xx/OMAP-L13x chips.  This driver can also be built as a
- --- 733,739 ----
-   
-   config RTC_DRV_OMAP
-   	tristate "TI OMAP1"
- ! 	depends on ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_DAVINCI_DA8XX || SOC_OMAPAM33XX
-   	help
-   	  Say "yes" here to support the real time clock on TI OMAP1 and
-   	  DA8xx/OMAP-L13x chips.  This driver can also be built as a
- diff -crN linux-3.2.1_o/drivers/rtc/rtc-omap.c linux-3.2.1/drivers/rtc/rtc-omap.c
- *** linux-3.2.1_o/drivers/rtc/rtc-omap.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/rtc/rtc-omap.c	2014-05-15 13:25:14.715293592 +0900
- ***************
- *** 19,25 ****
- --- 19,27 ----
-   #include <linux/delay.h>
-   #include <linux/rtc.h>
-   #include <linux/bcd.h>
- + #include <linux/rtc/rtc-omap.h>
-   #include <linux/platform_device.h>
- + #include <linux/pm_runtime.h>
-   
-   #include <asm/io.h>
-   
- ***************
- *** 38,43 ****
- --- 40,47 ----
-    * the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment.
-    */
-   
- + #define DRIVER_NAME			"omap_rtc"
- + 
-   #define OMAP_RTC_BASE			0xfffb4800
-   
-   /* RTC registers */
- ***************
- *** 64,69 ****
- --- 68,83 ----
-   #define OMAP_RTC_COMP_MSB_REG		0x50
-   #define OMAP_RTC_OSC_REG		0x54
-   
- + #define OMAP_RTC_ALARM2_SECONDS_REG	0x80
- + #define OMAP_RTC_ALARM2_MINUTES_REG	0x84
- + #define OMAP_RTC_ALARM2_HOURS_REG	0x88
- + #define OMAP_RTC_ALARM2_DAYS_REG	0x8c
- + #define OMAP_RTC_ALARM2_MONTHS_REG	0x90
- + #define OMAP_RTC_ALARM2_YEARS_REG	0x94
- + #define OMAP_RTC_PMIC_REG		0x98
- + 
- + #define OMAP_RTC_IRQWAKEEN		0x7C
- + 
-   /* OMAP_RTC_CTRL_REG bit fields: */
-   #define OMAP_RTC_CTRL_SPLIT		(1<<7)
-   #define OMAP_RTC_CTRL_DISABLE		(1<<6)
- ***************
- *** 85,93 ****
- --- 99,125 ----
-   #define OMAP_RTC_STATUS_BUSY            (1<<0)
-   
-   /* OMAP_RTC_INTERRUPTS_REG bit fields: */
- + #define OMAP_RTC_INTERRUPTS_IT_ALARM2	(1<<4)
-   #define OMAP_RTC_INTERRUPTS_IT_ALARM    (1<<3)
-   #define OMAP_RTC_INTERRUPTS_IT_TIMER    (1<<2)
-   
- + /* OMAP_RTC_PMIC_REG bit fields: */
- + #define OMAP_RTC_PMIC_POWER_EN_EN	(1<<16)
- + 
- + #define SHUTDOWN_TIME_SEC		2
- + #define SECS_IN_MIN			60
- + #define WAIT_AFTER			(SECS_IN_MIN - SHUTDOWN_TIME_SEC)
- + #define WAIT_TIME_MS			(SHUTDOWN_TIME_SEC * 1000)
- + 
- + /* OMAP_RTC_IRQWAKEEN bit fields: */
- + #define OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN    (1<<1)
- + 
- + /*
- +  * Few RTC IP revision has special WAKEEN Register to enable Wakeup
- +  * generation for event Alarm.
- +  */
- + #define	OMAP_RTC_HAS_IRQWAKEEN		0x2
- + 
-   static void __iomem	*rtc_base;
-   
-   #define rtc_read(addr)		__raw_readb(rtc_base + (addr))
- ***************
- *** 274,279 ****
- --- 306,358 ----
-   	return 0;
-   }
-   
- + /*
- +  * rtc_power_off: Set the pmic power off sequence. The RTC generates
- +  * pmic_pwr_enable control, which can be used to control an external
- +  * PMIC.
- +  */
- + static void rtc_power_off(void)
- + {
- + 	u32 val;
- + 	struct rtc_time tm;
- + 
- + 	/* Set PMIC power enable */
- + 	val = readl(rtc_base + OMAP_RTC_PMIC_REG);
- + 	writel(val | OMAP_RTC_PMIC_POWER_EN_EN, rtc_base + OMAP_RTC_PMIC_REG);
- + 
- + 	/* Wait few seconds instead of rollover */
- + 	do {
- + 		omap_rtc_read_time(NULL, &tm);
- + 		if (WAIT_AFTER <= tm.tm_sec)
- + 			mdelay(WAIT_TIME_MS);
- + 	} while (WAIT_AFTER <= tm.tm_sec);
- + 
- + 	/* Add shutdown time to the current value */
- + 	tm.tm_sec += SHUTDOWN_TIME_SEC;
- + 
- + 	if (tm2bcd(&tm) < 0)
- + 		return;
- + 
- + 	pr_info("System will go to power_off state in approx. %d secs\n",
- + 			SHUTDOWN_TIME_SEC);
- + 
- + 	/* Set the ALARM2 time */
- + 	rtc_write(tm.tm_sec, OMAP_RTC_ALARM2_SECONDS_REG);
- + 	rtc_write(tm.tm_min, OMAP_RTC_ALARM2_MINUTES_REG);
- + 	rtc_write(tm.tm_hour, OMAP_RTC_ALARM2_HOURS_REG);
- + 	rtc_write(tm.tm_mday, OMAP_RTC_ALARM2_DAYS_REG);
- + 	rtc_write(tm.tm_mon, OMAP_RTC_ALARM2_MONTHS_REG);
- + 	rtc_write(tm.tm_year, OMAP_RTC_ALARM2_YEARS_REG);
- + 
- + 	/* Enable alarm2 interrupt */
- + 	val = readl(rtc_base + OMAP_RTC_INTERRUPTS_REG);
- + 	writel(val | OMAP_RTC_INTERRUPTS_IT_ALARM2,
- + 				rtc_base + OMAP_RTC_INTERRUPTS_REG);
- + 
- + 	/* Do not allow to execute any other task */
- + 	while (1);
- + }
- + 
-   static struct rtc_class_ops omap_rtc_ops = {
-   	.read_time	= omap_rtc_read_time,
-   	.set_time	= omap_rtc_set_time,
- ***************
- *** 285,292 ****
- --- 364,383 ----
-   static int omap_rtc_alarm;
-   static int omap_rtc_timer;
-   
- + static struct platform_device_id omap_rtc_devtype[] = {
- + 	{
- + 		.name	= DRIVER_NAME,
- + 	}, {
- + 		.name	= "am33xx-rtc",
- + 		.driver_data = OMAP_RTC_HAS_IRQWAKEEN,
- + 	},
- + 	{},
- + };
- + MODULE_DEVICE_TABLE(platform, omap_rtc_devtype);
- + 
-   static int __init omap_rtc_probe(struct platform_device *pdev)
-   {
- + 	struct omap_rtc_pdata	*pdata = pdev->dev.platform_data;
-   	struct resource		*res, *mem;
-   	struct rtc_device	*rtc;
-   	u8			reg, new_ctrl;
- ***************
- *** 322,327 ****
- --- 413,422 ----
-   		goto fail;
-   	}
-   
- + 	/* Enable the clock/module so that we can access the registers */
- + 	pm_runtime_enable(&pdev->dev);
- + 	pm_runtime_get_sync(&pdev->dev);
- + 
-   	rtc = rtc_device_register(pdev->name, &pdev->dev,
-   			&omap_rtc_ops, THIS_MODULE);
-   	if (IS_ERR(rtc)) {
- ***************
- *** 332,337 ****
- --- 427,436 ----
-   	platform_set_drvdata(pdev, rtc);
-   	dev_set_drvdata(&rtc->dev, mem);
-   
- + 	/* RTC power off */
- + 	if (pdata && pdata->pm_off && !pm_power_off)
- + 		pm_power_off = rtc_power_off;
- + 
-   	/* clear pending irqs, and set 1/second periodic,
-   	 * which we'll use instead of update irqs
-   	 */
- ***************
- *** 391,396 ****
- --- 490,498 ----
-   	if (reg != new_ctrl)
-   		rtc_write(new_ctrl, OMAP_RTC_CTRL_REG);
-   
- + 	if (pdata->wakeup_capable)
- + 		device_init_wakeup(&pdev->dev, 1);
- + 
-   	return 0;
-   
-   fail2:
- ***************
- *** 398,403 ****
- --- 500,507 ----
-   fail1:
-   	rtc_device_unregister(rtc);
-   fail0:
- + 	pm_runtime_put_sync(&pdev->dev);
- + 	pm_runtime_disable(&pdev->dev);
-   	iounmap(rtc_base);
-   fail:
-   	release_mem_region(mem->start, resource_size(mem));
- ***************
- *** 420,425 ****
- --- 524,534 ----
-   		free_irq(omap_rtc_alarm, rtc);
-   
-   	rtc_device_unregister(rtc);
- + 
- + 	/* Disable the clock/module */
- + 	pm_runtime_put_sync(&pdev->dev);
- + 	pm_runtime_disable(&pdev->dev);
- + 
-   	iounmap(rtc_base);
-   	release_mem_region(mem->start, resource_size(mem));
-   	return 0;
- ***************
- *** 431,456 ****
-   
-   static int omap_rtc_suspend(struct platform_device *pdev, pm_message_t state)
-   {
-   	irqstat = rtc_read(OMAP_RTC_INTERRUPTS_REG);
-   
-   	/* FIXME the RTC alarm is not currently acting as a wakeup event
-   	 * source, and in fact this enable() call is just saving a flag
-   	 * that's never used...
-   	 */
- ! 	if (device_may_wakeup(&pdev->dev))
-   		enable_irq_wake(omap_rtc_alarm);
- ! 	else
-   		rtc_write(0, OMAP_RTC_INTERRUPTS_REG);
-   
-   	return 0;
-   }
-   
-   static int omap_rtc_resume(struct platform_device *pdev)
-   {
- ! 	if (device_may_wakeup(&pdev->dev))
-   		disable_irq_wake(omap_rtc_alarm);
- ! 	else
-   		rtc_write(irqstat, OMAP_RTC_INTERRUPTS_REG);
-   	return 0;
-   }
-   
- --- 540,593 ----
-   
-   static int omap_rtc_suspend(struct platform_device *pdev, pm_message_t state)
-   {
- + 	u8 irqwake_stat;
- + 	const struct platform_device_id *id_entry =
- + 				platform_get_device_id(pdev);
- + 
-   	irqstat = rtc_read(OMAP_RTC_INTERRUPTS_REG);
-   
-   	/* FIXME the RTC alarm is not currently acting as a wakeup event
-   	 * source, and in fact this enable() call is just saving a flag
-   	 * that's never used...
-   	 */
- ! 	if (device_may_wakeup(&pdev->dev)) {
-   		enable_irq_wake(omap_rtc_alarm);
- ! 
- ! 		if (id_entry->driver_data & OMAP_RTC_HAS_IRQWAKEEN) {
- ! 			irqwake_stat = rtc_read(OMAP_RTC_IRQWAKEEN);
- ! 			irqwake_stat |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
- ! 			rtc_write(irqwake_stat, OMAP_RTC_IRQWAKEEN);
- ! 		}
- ! 	} else {
-   		rtc_write(0, OMAP_RTC_INTERRUPTS_REG);
- + 	}
- + 
- + 	/* Disable the clock/module */
- + 	pm_runtime_put_sync(&pdev->dev);
-   
-   	return 0;
-   }
-   
-   static int omap_rtc_resume(struct platform_device *pdev)
-   {
- ! 	u8 irqwake_stat;
- ! 	const struct platform_device_id *id_entry =
- ! 				platform_get_device_id(pdev);
- ! 
- ! 	/* Enable the clock/module so that we can access the registers */
- ! 	pm_runtime_get_sync(&pdev->dev);
- ! 
- ! 	if (device_may_wakeup(&pdev->dev)) {
-   		disable_irq_wake(omap_rtc_alarm);
- ! 
- ! 		if (id_entry->driver_data & OMAP_RTC_HAS_IRQWAKEEN) {
- ! 			irqwake_stat = rtc_read(OMAP_RTC_IRQWAKEEN);
- ! 			irqwake_stat &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
- ! 			rtc_write(irqwake_stat, OMAP_RTC_IRQWAKEEN);
- ! 		}
- ! 	} else {
-   		rtc_write(irqstat, OMAP_RTC_INTERRUPTS_REG);
- + 	}
-   	return 0;
-   }
-   
- ***************
- *** 471,479 ****
-   	.resume		= omap_rtc_resume,
-   	.shutdown	= omap_rtc_shutdown,
-   	.driver		= {
- ! 		.name	= "omap_rtc",
-   		.owner	= THIS_MODULE,
-   	},
-   };
-   
-   static int __init rtc_init(void)
- --- 608,617 ----
-   	.resume		= omap_rtc_resume,
-   	.shutdown	= omap_rtc_shutdown,
-   	.driver		= {
- ! 		.name	= DRIVER_NAME,
-   		.owner	= THIS_MODULE,
-   	},
- + 	.id_table	= omap_rtc_devtype,
-   };
-   
-   static int __init rtc_init(void)
- diff -crN linux-3.2.1_o/drivers/spi/Kconfig linux-3.2.1/drivers/spi/Kconfig
- *** linux-3.2.1_o/drivers/spi/Kconfig	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/spi/Kconfig	2014-05-15 13:25:14.734726819 +0900
- ***************
- *** 232,238 ****
-   
-   config SPI_OMAP24XX
-   	tristate "McSPI driver for OMAP"
- ! 	depends on ARCH_OMAP2PLUS
-   	help
-   	  SPI master controller for OMAP24XX and later Multichannel SPI
-   	  (McSPI) modules.
- --- 232,238 ----
-   
-   config SPI_OMAP24XX
-   	tristate "McSPI driver for OMAP"
- ! 	depends on ARCH_OMAP2PLUS || MACH_CKB_3352
-   	help
-   	  SPI master controller for OMAP24XX and later Multichannel SPI
-   	  (McSPI) modules.
- diff -crN linux-3.2.1_o/drivers/spi/spi-omap2-mcspi.c linux-3.2.1/drivers/spi/spi-omap2-mcspi.c
- *** linux-3.2.1_o/drivers/spi/spi-omap2-mcspi.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/spi/spi-omap2-mcspi.c	2014-05-15 13:25:14.779288672 +0900
- ***************
- *** 40,45 ****
- --- 40,46 ----
-   #include <plat/dma.h>
-   #include <plat/clock.h>
-   #include <plat/mcspi.h>
- + #include <mach/edma.h>
-   
-   #define OMAP2_MCSPI_MAX_FREQ		48000000
-   
- ***************
- *** 101,106 ****
- --- 102,108 ----
-   
-   	struct completion dma_tx_completion;
-   	struct completion dma_rx_completion;
- + 	int dummy_param_slot;
-   };
-   
-   /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
- ***************
- *** 108,114 ****
-    */
-   #define DMA_MIN_BYTES			160
-   
- - 
-   struct omap2_mcspi {
-   	struct work_struct	work;
-   	/* lock protects queue and registers */
- --- 110,115 ----
- ***************
- *** 303,308 ****
- --- 304,310 ----
-   	u8			* rx;
-   	const u8		* tx;
-   	void __iomem		*chstat_reg;
- + 	struct edmacc_param	param;
-   
-   	mcspi = spi_master_get_devdata(spi->master);
-   	mcspi_dma = &mcspi->dma_channels[spi->chip_select];
- ***************
- *** 332,368 ****
-   	}
-   
-   	if (tx != NULL) {
- ! 		omap_set_dma_transfer_params(mcspi_dma->dma_tx_channel,
- ! 				data_type, element_count, 1,
- ! 				OMAP_DMA_SYNC_ELEMENT,
- ! 				mcspi_dma->dma_tx_sync_dev, 0);
- ! 
- ! 		omap_set_dma_dest_params(mcspi_dma->dma_tx_channel, 0,
- ! 				OMAP_DMA_AMODE_CONSTANT,
- ! 				tx_reg, 0, 0);
- ! 
- ! 		omap_set_dma_src_params(mcspi_dma->dma_tx_channel, 0,
- ! 				OMAP_DMA_AMODE_POST_INC,
- ! 				xfer->tx_dma, 0, 0);
-   	}
-   
-   	if (rx != NULL) {
-   		elements = element_count - 1;
-   		if (l & OMAP2_MCSPI_CHCONF_TURBO)
-   			elements--;
-   
- ! 		omap_set_dma_transfer_params(mcspi_dma->dma_rx_channel,
- ! 				data_type, elements, 1,
- ! 				OMAP_DMA_SYNC_ELEMENT,
- ! 				mcspi_dma->dma_rx_sync_dev, 1);
- ! 
- ! 		omap_set_dma_src_params(mcspi_dma->dma_rx_channel, 0,
- ! 				OMAP_DMA_AMODE_CONSTANT,
- ! 				rx_reg, 0, 0);
- ! 
- ! 		omap_set_dma_dest_params(mcspi_dma->dma_rx_channel, 0,
- ! 				OMAP_DMA_AMODE_POST_INC,
- ! 				xfer->rx_dma, 0, 0);
-   	}
-   
-   	if (tx != NULL) {
- --- 334,390 ----
-   	}
-   
-   	if (tx != NULL) {
- ! 		int a_cnt, b_cnt, c_cnt, b_cntrld;
- ! 
- ! 		a_cnt    = 1 << data_type;
- ! 		b_cnt    = 1;
- ! 		c_cnt    = element_count / 256;
- ! 		b_cntrld = SZ_64K - 1;
- ! 
- ! 		param.opt          = TCINTEN |
- ! 			EDMA_TCC(mcspi_dma->dma_tx_channel) | SYNCDIM ;
- ! 		param.src          = xfer->tx_dma;
- ! 		param.a_b_cnt      = a_cnt | b_cnt << 16;
- ! 		param.dst          = tx_reg;
- ! 		param.src_dst_bidx = a_cnt;
- ! 		param.link_bcntrld = b_cntrld << 16;
- ! 		param.src_dst_cidx = a_cnt;
- ! 		param.ccnt         = element_count;
- ! 		edma_write_slot(mcspi_dma->dma_tx_channel, &param);
- ! 		edma_link(mcspi_dma->dma_tx_channel,
- ! 				mcspi_dma->dummy_param_slot);
-   	}
-   
-   	if (rx != NULL) {
- + 		int a_cnt, b_cnt, c_cnt, b_cntrld;
- + 
- + 		a_cnt    = 1 << data_type;
- + 		c_cnt    = element_count / (SZ_64K - 1);
- + 		b_cnt    = element_count - c_cnt * (SZ_64K - 1);
- + 		b_cntrld = SZ_64K - 1;
- + 
- + 		if (b_cnt)
- + 			c_cnt++;
- + 		else
- + 			b_cnt = SZ_64K - 1;
- + 
-   		elements = element_count - 1;
-   		if (l & OMAP2_MCSPI_CHCONF_TURBO)
-   			elements--;
-   
- ! 		param.opt          = TCINTEN |
- ! 			EDMA_TCC(mcspi_dma->dma_rx_channel);
- ! 		param.src          = rx_reg;
- ! 		param.a_b_cnt      = a_cnt | b_cnt << 16;
- ! 		param.dst          = xfer->rx_dma;
- ! 		param.src_dst_bidx = a_cnt << 16;
- ! 		param.link_bcntrld = b_cntrld << 16;
- ! 		param.src_dst_cidx = a_cnt << 16;
- ! 		param.ccnt         = c_cnt;
- ! 		edma_write_slot(mcspi_dma->dma_rx_channel, &param);
- ! 		edma_link(mcspi_dma->dma_rx_channel,
- ! 				mcspi_dma->dummy_param_slot);
- ! 
-   	}
-   
-   	if (tx != NULL) {
- ***************
- *** 419,441 ****
-   			}
-   		}
-   
- - 		if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
- - 				& OMAP2_MCSPI_CHSTAT_RXS)) {
- - 			u32 w;
- - 
- - 			w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
- - 			if (word_len <= 8)
- - 				((u8 *)xfer->rx_buf)[elements] = w;
- - 			else if (word_len <= 16)
- - 				((u16 *)xfer->rx_buf)[elements] = w;
- - 			else /* word_len <= 32 */
- - 				((u32 *)xfer->rx_buf)[elements] = w;
- - 		} else {
- - 			dev_err(&spi->dev, "DMA RX last word empty");
- - 			count -= (word_len <= 8)  ? 1 :
- - 				 (word_len <= 16) ? 2 :
- - 			       /* word_len <= 32 */ 4;
- - 		}
-   		omap2_mcspi_set_enable(spi, 1);
-   	}
-   	return count;
- --- 441,446 ----
- ***************
- *** 718,730 ****
-   	struct omap2_mcspi	*mcspi;
-   	struct omap2_mcspi_dma	*mcspi_dma;
-   
-   	mcspi = spi_master_get_devdata(spi->master);
-   	mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
-   
-   	complete(&mcspi_dma->dma_rx_completion);
-   
- - 	/* We must disable the DMA RX request */
- - 	omap2_mcspi_set_dma_req(spi, 1, 0);
-   }
-   
-   static void omap2_mcspi_dma_tx_callback(int lch, u16 ch_status, void *data)
- --- 723,735 ----
-   	struct omap2_mcspi	*mcspi;
-   	struct omap2_mcspi_dma	*mcspi_dma;
-   
- + 	/* We must disable the DMA RX request */
- + 	omap2_mcspi_set_dma_req(spi, 1, 0);
-   	mcspi = spi_master_get_devdata(spi->master);
-   	mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
-   
-   	complete(&mcspi_dma->dma_rx_completion);
-   
-   }
-   
-   static void omap2_mcspi_dma_tx_callback(int lch, u16 ch_status, void *data)
- ***************
- *** 733,745 ****
-   	struct omap2_mcspi	*mcspi;
-   	struct omap2_mcspi_dma	*mcspi_dma;
-   
-   	mcspi = spi_master_get_devdata(spi->master);
-   	mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
-   
-   	complete(&mcspi_dma->dma_tx_completion);
-   
- - 	/* We must disable the DMA TX request */
- - 	omap2_mcspi_set_dma_req(spi, 0, 0);
-   }
-   
-   static int omap2_mcspi_request_dma(struct spi_device *spi)
- --- 738,750 ----
-   	struct omap2_mcspi	*mcspi;
-   	struct omap2_mcspi_dma	*mcspi_dma;
-   
- + 	/* We must disable the DMA TX request */
- + 	omap2_mcspi_set_dma_req(spi, 0, 0);
-   	mcspi = spi_master_get_devdata(spi->master);
-   	mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
-   
-   	complete(&mcspi_dma->dma_tx_completion);
-   
-   }
-   
-   static int omap2_mcspi_request_dma(struct spi_device *spi)
- ***************
- *** 747,752 ****
- --- 752,758 ----
-   	struct spi_master	*master = spi->master;
-   	struct omap2_mcspi	*mcspi;
-   	struct omap2_mcspi_dma	*mcspi_dma;
- + 	int			ret = 0;
-   
-   	mcspi = spi_master_get_devdata(master);
-   	mcspi_dma = mcspi->dma_channels + spi->chip_select;
- ***************
- *** 766,771 ****
- --- 772,789 ----
-   		dev_err(&spi->dev, "no TX DMA channel for McSPI\n");
-   		return -EAGAIN;
-   	}
- + 	ret = edma_alloc_slot(EDMA_CTLR(mcspi_dma->dma_tx_channel),
- + 			EDMA_SLOT_ANY);
- + 
- + 	if (ret < 0) {
- + 		pr_err("Unable to request SPI TX DMA param slot\n");
- + 		ret = -EAGAIN;
- + 		return ret;
- + 	}
- + 
- + 	mcspi_dma->dummy_param_slot = ret;
- + 	edma_link(mcspi_dma->dummy_param_slot,
- + 			mcspi_dma->dummy_param_slot);
-   
-   	init_completion(&mcspi_dma->dma_rx_completion);
-   	init_completion(&mcspi_dma->dma_tx_completion);
- ***************
- *** 1114,1120 ****
-   	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-   	if (r == NULL) {
-   		status = -ENODEV;
- ! 		goto err1;
-   	}
-   
-   	r->start += pdata->regs_offset;
- --- 1132,1138 ----
-   	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-   	if (r == NULL) {
-   		status = -ENODEV;
- ! 		goto free_master;
-   	}
-   
-   	r->start += pdata->regs_offset;
- ***************
- *** 1123,1136 ****
-   	if (!request_mem_region(r->start, resource_size(r),
-   				dev_name(&pdev->dev))) {
-   		status = -EBUSY;
- ! 		goto err1;
-   	}
-   
-   	mcspi->base = ioremap(r->start, resource_size(r));
-   	if (!mcspi->base) {
-   		dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
-   		status = -ENOMEM;
- ! 		goto err2;
-   	}
-   
-   	mcspi->dev = &pdev->dev;
- --- 1141,1154 ----
-   	if (!request_mem_region(r->start, resource_size(r),
-   				dev_name(&pdev->dev))) {
-   		status = -EBUSY;
- ! 		goto free_master;
-   	}
-   
-   	mcspi->base = ioremap(r->start, resource_size(r));
-   	if (!mcspi->base) {
-   		dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
-   		status = -ENOMEM;
- ! 		goto release_region;
-   	}
-   
-   	mcspi->dev = &pdev->dev;
- ***************
- *** 1145,1151 ****
-   			GFP_KERNEL);
-   
-   	if (mcspi->dma_channels == NULL)
- ! 		goto err2;
-   
-   	for (i = 0; i < master->num_chipselect; i++) {
-   		char dma_ch_name[14];
- --- 1163,1169 ----
-   			GFP_KERNEL);
-   
-   	if (mcspi->dma_channels == NULL)
- ! 		goto unmap_io;
-   
-   	for (i = 0; i < master->num_chipselect; i++) {
-   		char dma_ch_name[14];
- ***************
- *** 1175,1199 ****
-   		mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
-   	}
-   
-   	pm_runtime_enable(&pdev->dev);
-   
-   	if (status || omap2_mcspi_master_setup(mcspi) < 0)
- ! 		goto err3;
-   
-   	status = spi_register_master(master);
-   	if (status < 0)
- ! 		goto err4;
-   
-   	return status;
-   
- ! err4:
-   	spi_master_put(master);
- ! err3:
-   	kfree(mcspi->dma_channels);
- ! err2:
- ! 	release_mem_region(r->start, resource_size(r));
-   	iounmap(mcspi->base);
- ! err1:
-   	return status;
-   }
-   
- --- 1193,1226 ----
-   		mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
-   	}
-   
- + 	if (status < 0)
- + 		goto dma_chnl_free;
- + 
-   	pm_runtime_enable(&pdev->dev);
-   
-   	if (status || omap2_mcspi_master_setup(mcspi) < 0)
- ! 		goto diable_pm;
-   
-   	status = spi_register_master(master);
-   	if (status < 0)
- ! 		goto err_spi_register;
-   
-   	return status;
-   
- ! err_spi_register:
-   	spi_master_put(master);
- ! diable_pm:
- ! 	pm_runtime_put_sync(&pdev->dev);
- ! 	pm_runtime_disable(&pdev->dev);
- ! dma_chnl_free:
-   	kfree(mcspi->dma_channels);
- ! unmap_io:
-   	iounmap(mcspi->base);
- ! release_region:
- ! 	release_mem_region(r->start, resource_size(r));
- ! free_master:
- ! 	kfree(master);
- ! 	platform_set_drvdata(pdev, NULL);
-   	return status;
-   }
-   
- ***************
- *** 1210,1222 ****
-   	dma_channels = mcspi->dma_channels;
-   
-   	omap2_mcspi_disable_clocks(mcspi);
-   	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-   	release_mem_region(r->start, resource_size(r));
-   
- - 	base = mcspi->base;
-   	spi_unregister_master(master);
- ! 	iounmap(base);
- ! 	kfree(dma_channels);
-   
-   	return 0;
-   }
- --- 1237,1252 ----
-   	dma_channels = mcspi->dma_channels;
-   
-   	omap2_mcspi_disable_clocks(mcspi);
- + 	pm_runtime_disable(&pdev->dev);
- + 	kfree(dma_channels);
- + 	base = mcspi->base;
- + 	iounmap(base);
- + 
-   	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-   	release_mem_region(r->start, resource_size(r));
-   
-   	spi_unregister_master(master);
- ! 	platform_set_drvdata(pdev, NULL);
-   
-   	return 0;
-   }
- diff -crN linux-3.2.1_o/drivers/staging/iio/adc/Kconfig linux-3.2.1/drivers/staging/iio/adc/Kconfig
- *** linux-3.2.1_o/drivers/staging/iio/adc/Kconfig	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/staging/iio/adc/Kconfig	2014-05-15 13:25:14.795281858 +0900
- ***************
- *** 193,196 ****
- --- 193,204 ----
-   	  Say yes here to include ring buffer support in the MAX1363
-   	  ADC driver.
-   
- + config TI_ADC
- + 	tristate "TI's ADC driver"
- + 	help
- + 	  Say yes here to build support for Texas Instruments ADC
- + 	  driver which is also a MFD.
- + 	  To compile this driver as a module, choose M here: the
- + 	  module will be called ti_adc.
- + 
-   endmenu
- diff -crN linux-3.2.1_o/drivers/staging/iio/adc/Makefile linux-3.2.1/drivers/staging/iio/adc/Makefile
- *** linux-3.2.1_o/drivers/staging/iio/adc/Makefile	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/staging/iio/adc/Makefile	2014-05-15 13:25:14.803231212 +0900
- ***************
- *** 37,39 ****
- --- 37,40 ----
-   obj-$(CONFIG_ADT7310) += adt7310.o
-   obj-$(CONFIG_ADT7410) += adt7410.o
-   obj-$(CONFIG_AD7280) += ad7280a.o
- + obj-$(CONFIG_TI_ADC) += ti_adc.o
- diff -crN linux-3.2.1_o/drivers/staging/iio/adc/ti_adc.c linux-3.2.1/drivers/staging/iio/adc/ti_adc.c
- *** linux-3.2.1_o/drivers/staging/iio/adc/ti_adc.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/drivers/staging/iio/adc/ti_adc.c	2014-05-15 13:25:14.807279613 +0900
- ***************
- *** 0 ****
- --- 1,542 ----
- + /*
- +  * TI ADC MFD driver
- +  *
- +  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #include <linux/init.h>
- + #include <linux/kernel.h>
- + #include <linux/err.h>
- + #include <linux/module.h>
- + #include <linux/slab.h>
- + #include <linux/interrupt.h>
- + #include <linux/platform_device.h>
- + #include <linux/io.h>
- + #include <linux/sched.h>
- + 
- + #include "../iio.h"
- + #include "../sysfs.h"
- + #include "../buffer_generic.h"
- + #include "../ring_sw.h"
- + 
- + #include <linux/mfd/ti_tscadc.h>
- + #include <linux/platform_data/ti_adc.h>
- + 
- + struct adc_device {
- + 	struct ti_tscadc_dev	*mfd_tscadc;
- + 	struct iio_dev		*idev;
- + 	struct work_struct	poll_work;
- + 	wait_queue_head_t	wq_data_avail;
- + 	int			channels;
- + 	int			irq;
- + 	bool			is_continuous_mode;
- + 	u16			*buffer;
- + };
- + 
- + static unsigned int adc_readl(struct adc_device *adc, unsigned int reg)
- + {
- + 	return readl(adc->mfd_tscadc->tscadc_base + reg);
- + }
- + 
- + static void adc_writel(struct adc_device *adc, unsigned int reg,
- + 					unsigned int val)
- + {
- + 	writel(val, adc->mfd_tscadc->tscadc_base + reg);
- + }
- + 
- + static void adc_step_config(struct adc_device *adc_dev, bool mode)
- + {
- + 	unsigned int    stepconfig;
- + 	int i, channels = 0, steps;
- + 
- + 	/*
- + 	 * There are 16 configurable steps and 8 analog input
- + 	 * lines available which are shared between Touchscreen and ADC.
- + 	 *
- + 	 * Steps backwards i.e. from 16 towards 0 are used by ADC
- + 	 * depending on number of input lines needed.
- + 	 * Channel would represent which analog input
- + 	 * needs to be given to ADC to digitalize data.
- + 	 */
- + 
- + 	steps = TOTAL_STEPS - adc_dev->channels;
- + 	channels = TOTAL_CHANNELS - adc_dev->channels;
- + 
- + 	if (mode == 0)
- + 		stepconfig = TSCADC_STEPCONFIG_AVG_16 | TSCADC_STEPCONFIG_FIFO1;
- + 	else
- + 		stepconfig = TSCADC_STEPCONFIG_AVG_16 | TSCADC_STEPCONFIG_FIFO1
- + 			| TSCADC_STEPCONFIG_MODE_SWCNT;
- + 
- + 	for (i = (steps + 1); i <= TOTAL_STEPS; i++) {
- + 		adc_writel(adc_dev, TSCADC_REG_STEPCONFIG(i),
- + 				stepconfig | TSCADC_STEPCONFIG_INP(channels));
- + 		adc_writel(adc_dev, TSCADC_REG_STEPDELAY(i),
- + 				TSCADC_STEPCONFIG_OPENDLY);
- + 		channels++;
- + 	}
- + }
- + 
- + static ssize_t tiadc_show_mode(struct device *dev,
- + 		struct device_attribute *attr, char *buf)
- + {
- + 	struct iio_dev *indio_dev = dev_get_drvdata(dev);
- + 	struct adc_device *adc_dev = iio_priv(indio_dev);
- + 	unsigned int tmp;
- + 
- + 	tmp = adc_readl(adc_dev, TSCADC_REG_STEPCONFIG(TOTAL_STEPS));
- + 	tmp &= TSCADC_STEPCONFIG_MODE(1);
- + 
- + 	if (tmp == 0x00)
- + 		return sprintf(buf, "oneshot\n");
- + 	else if (tmp == 0x01)
- + 		return sprintf(buf, "continuous\n");
- + 	else
- + 		return sprintf(buf, "Operation mode unknown\n");
- + }
- + 
- + static ssize_t tiadc_set_mode(struct device *dev,
- + 		struct device_attribute *attr, const char *buf, size_t count)
- + {
- + 	struct iio_dev *indio_dev = dev_get_drvdata(dev);
- + 	struct adc_device *adc_dev = iio_priv(indio_dev);
- + 	unsigned int config;
- + 
- + 	config = adc_readl(adc_dev, TSCADC_REG_CTRL);
- + 	config &= ~(TSCADC_CNTRLREG_TSCSSENB);
- + 	adc_writel(adc_dev, TSCADC_REG_CTRL, config);
- + 
- + 	if (!strncmp(buf, "oneshot", 7))
- + 		adc_dev->is_continuous_mode = false;
- + 	else if (!strncmp(buf, "continuous", 10))
- + 		adc_dev->is_continuous_mode = true;
- + 	else {
- + 		dev_err(dev, "Operational mode unknown\n");
- + 		return -EINVAL;
- + 	}
- + 
- + 	adc_step_config(adc_dev, adc_dev->is_continuous_mode);
- + 
- + 	config = adc_readl(adc_dev, TSCADC_REG_CTRL);
- + 	adc_writel(adc_dev, TSCADC_REG_CTRL,
- + 			(config | TSCADC_CNTRLREG_TSCSSENB));
- + 	return count;
- + }
- + 
- + static IIO_DEVICE_ATTR(mode, S_IRUGO | S_IWUSR, tiadc_show_mode,
- + 		tiadc_set_mode, 0);
- + 
- + static struct attribute *tiadc_attributes[] = {
- + 	&iio_dev_attr_mode.dev_attr.attr,
- + 	NULL,
- + };
- + 
- + static const struct attribute_group tiadc_attribute_group = {
- + 	.attrs = tiadc_attributes,
- + };
- + 
- + static irqreturn_t tiadc_irq(int irq, void *private)
- + {
- + 	struct iio_dev *idev = private;
- + 	struct adc_device *adc_dev = iio_priv(idev);
- + 	unsigned int status, config;
- + 
- + 	status = adc_readl(adc_dev, TSCADC_REG_IRQSTATUS);
- + 	if (status & TSCADC_IRQENB_FIFO1OVRRUN) {
- + 		config = adc_readl(adc_dev, TSCADC_REG_CTRL);
- + 		config &= ~(TSCADC_CNTRLREG_TSCSSENB);
- + 		adc_writel(adc_dev, TSCADC_REG_CTRL, config);
- + 
- + 		adc_writel(adc_dev, TSCADC_REG_IRQSTATUS,
- + 				TSCADC_IRQENB_FIFO1OVRRUN |
- + 				TSCADC_IRQENB_FIFO1UNDRFLW |
- + 				TSCADC_IRQENB_FIFO1THRES);
- + 
- + 		adc_writel(adc_dev, TSCADC_REG_CTRL,
- + 			(config | TSCADC_CNTRLREG_TSCSSENB));
- + 		return IRQ_HANDLED;
- + 	} else if (status & TSCADC_IRQENB_FIFO1THRES) {
- + 		adc_writel(adc_dev, TSCADC_REG_IRQCLR,
- + 				TSCADC_IRQENB_FIFO1THRES);
- + 
- + 		if (iio_buffer_enabled(idev)) {
- + 			if (!work_pending(&adc_dev->poll_work))
- + 				schedule_work(&adc_dev->poll_work);
- + 		} else {
- + 			wake_up_interruptible(&adc_dev->wq_data_avail);
- + 		}
- + 		return IRQ_HANDLED;
- + 	} else {
- + 		return IRQ_NONE;
- + 	}
- + }
- + 
- + static void tiadc_poll_handler(struct work_struct *work_s)
- + {
- + 	struct adc_device *adc_dev =
- + 		container_of(work_s, struct adc_device, poll_work);
- + 	struct iio_dev *idev = iio_priv_to_dev(adc_dev);
- + 	struct iio_buffer *buffer = idev->buffer;
- + 	unsigned int fifo1count, readx1;
- + 	int i;
- + 	u32 *iBuf;
- + 
- + 	fifo1count = adc_readl(adc_dev, TSCADC_REG_FIFO1CNT);
- + 	if (fifo1count * sizeof(u32) <
- + 				buffer->access->get_bytes_per_datum(buffer)) {
- + 		dev_err(adc_dev->mfd_tscadc->dev, "%s: Short FIFO event\n",
- + 								__func__);
- + 		goto out;
- + 	}
- + 
- + 	iBuf = kmalloc(fifo1count * sizeof(u32), GFP_KERNEL);
- + 	if (iBuf == NULL)
- + 		goto out;
- + 
- + 	for (i = 0; i < fifo1count; i++) {
- + 		readx1 = adc_readl(adc_dev, TSCADC_REG_FIFO1);
- + 		readx1 &= TSCADC_FIFOREAD_DATA_MASK;
- + 		iBuf[i] = readx1;
- + 	}
- + 
- + 	buffer->access->store_to(buffer, (u8 *) iBuf, iio_get_time_ns());
- + 	kfree(iBuf);
- + 
- + out:
- + 	adc_writel(adc_dev, TSCADC_REG_IRQSTATUS,
- + 				TSCADC_IRQENB_FIFO1THRES);
- + 	adc_writel(adc_dev, TSCADC_REG_IRQENABLE,
- + 				TSCADC_IRQENB_FIFO1THRES);
- + }
- + 
- + static int tiadc_buffer_preenable(struct iio_dev *idev)
- + {
- + 	struct iio_buffer *buffer = idev->buffer;
- + 
- + 	buffer->access->set_bytes_per_datum(buffer, 16);
- + 	return 0;
- + }
- + 
- + static int tiadc_buffer_postenable(struct iio_dev *idev)
- + {
- + 	struct adc_device *adc_dev = iio_priv(idev);
- + 	struct iio_buffer *buffer = idev->buffer;
- + 	unsigned int enb, config;
- + 	int stepnum;
- + 	u8 bit;
- + 
- + 	if (!adc_dev->is_continuous_mode) {
- + 		pr_info("Data cannot be read continuously in one shot mode\n");
- + 		return -EINVAL;
- + 	} else {
- + 
- + 		config = adc_readl(adc_dev, TSCADC_REG_CTRL);
- + 		adc_writel(adc_dev, TSCADC_REG_CTRL,
- + 					config & ~TSCADC_CNTRLREG_TSCSSENB);
- + 		adc_writel(adc_dev, TSCADC_REG_CTRL,
- + 					config | TSCADC_CNTRLREG_TSCSSENB);
- + 
- + 
- + 		adc_writel(adc_dev, TSCADC_REG_IRQSTATUS,
- + 				TSCADC_IRQENB_FIFO1THRES |
- + 				TSCADC_IRQENB_FIFO1OVRRUN |
- + 				TSCADC_IRQENB_FIFO1UNDRFLW);
- + 		adc_writel(adc_dev, TSCADC_REG_IRQENABLE,
- + 				TSCADC_IRQENB_FIFO1THRES |
- + 				TSCADC_IRQENB_FIFO1OVRRUN);
- + 
- + 		adc_writel(adc_dev, TSCADC_REG_SE, 0x00);
- + 		for_each_set_bit(bit, buffer->scan_mask,
- + 				adc_dev->channels) {
- + 			struct iio_chan_spec const *chan = idev->channels + bit;
- + 			/*
- + 			 * There are a total of 16 steps available
- + 			 * that are shared between ADC and touchscreen.
- + 			 * We start configuring from step 16 to 0 incase of
- + 			 * ADC. Hence the relation between input channel
- + 			 * and step for ADC would be as below.
- + 			 */
- + 			stepnum = chan->channel + 9;
- + 			enb = adc_readl(adc_dev, TSCADC_REG_SE);
- + 			enb |= (1 << stepnum);
- + 			adc_writel(adc_dev, TSCADC_REG_SE, enb);
- + 		}
- + 		return 0;
- + 	}
- + }
- + 
- + static int tiadc_buffer_postdisable(struct iio_dev *idev)
- + {
- + 	struct adc_device *adc_dev = iio_priv(idev);
- + 
- + 	adc_writel(adc_dev, TSCADC_REG_IRQCLR, (TSCADC_IRQENB_FIFO1THRES |
- + 				TSCADC_IRQENB_FIFO1OVRRUN |
- + 				TSCADC_IRQENB_FIFO1UNDRFLW));
- + 	adc_writel(adc_dev, TSCADC_REG_SE, TSCADC_STPENB_STEPENB_TC);
- + 	return 0;
- + }
- + 
- + static const struct iio_buffer_setup_ops tiadc_swring_setup_ops = {
- + 	.preenable = &tiadc_buffer_preenable,
- + 	.postenable = &tiadc_buffer_postenable,
- + 	.postdisable = &tiadc_buffer_postdisable,
- + };
- + 
- + static int tiadc_config_sw_ring(struct iio_dev *idev)
- + {
- + 	struct adc_device *adc_dev = iio_priv(idev);
- + 	int ret;
- + 
- + 	idev->buffer = iio_sw_rb_allocate(idev);
- + 	if (!idev->buffer)
- + 		ret = -ENOMEM;
- + 
- + 	idev->buffer->access = &ring_sw_access_funcs;
- + 	idev->buffer->setup_ops = &tiadc_swring_setup_ops;
- + 
- + 	INIT_WORK(&adc_dev->poll_work, &tiadc_poll_handler);
- + 
- + 	idev->modes |= INDIO_BUFFER_HARDWARE;
- + 	return 0;
- + }
- + 
- + static int tiadc_channel_init(struct iio_dev *idev, struct adc_device *adc_dev)
- + {
- + 	struct iio_chan_spec *chan_array;
- + 	int i, channels;
- + 
- + 	idev->num_channels = adc_dev->channels;
- + 	chan_array = kcalloc(idev->num_channels, sizeof(struct iio_chan_spec),
- + 					GFP_KERNEL);
- + 
- + 	if (chan_array == NULL)
- + 		return -ENOMEM;
- + 
- + 	channels = TOTAL_CHANNELS - adc_dev->channels;
- + 	for (i = 0; i < (idev->num_channels); i++) {
- + 		struct iio_chan_spec *chan = chan_array + i;
- + 		chan->type = IIO_VOLTAGE;
- + 		chan->indexed = 1;
- + 		chan->channel = channels;
- + 		chan->scan_index = i;
- + 		chan->scan_type.sign = 'u';
- + 		chan->scan_type.realbits = 12;
- + 		chan->scan_type.storagebits = 32;
- + 		chan->scan_type.shift = 0;
- + 		channels++;
- + 	}
- + 
- + 	idev->channels = chan_array;
- + 	return idev->num_channels;
- + }
- + 
- + static void tiadc_channel_remove(struct iio_dev *idev)
- + {
- + 	kfree(idev->channels);
- + }
- + 
- + static int tiadc_read_raw(struct iio_dev *idev,
- + 		struct iio_chan_spec const *chan,
- + 		int *val, int *val2, long mask)
- + {
- + 	struct adc_device *adc_dev = iio_priv(idev);
- + 	int i, map_val;
- + 	unsigned int fifo1count, readx1, stepid;
- + 	unsigned long timeout = jiffies + usecs_to_jiffies
- + 			(IDLE_TIMEOUT * adc_dev->channels);
- + 
- + 	if (adc_dev->is_continuous_mode) {
- + 		pr_info("One shot mode not enabled\n");
- + 		return -EINVAL;
- + 	} else {
- + 		adc_writel(adc_dev, TSCADC_REG_SE, TSCADC_STPENB_STEPENB);
- + 
- + 		/* Wait for ADC sequencer to complete sampling */
- + 		while (adc_readl(adc_dev, TSCADC_REG_ADCFSM) &
- + 				TSCADC_SEQ_STATUS) {
- + 			if (time_after(jiffies, timeout))
- + 				return -EAGAIN;
- + 		}
- + 
- + 		map_val = chan->channel + TOTAL_CHANNELS;
- + 		fifo1count = adc_readl(adc_dev, TSCADC_REG_FIFO1CNT);
- + 		for (i = 0; i < fifo1count; i++) {
- + 			readx1 = adc_readl(adc_dev, TSCADC_REG_FIFO1);
- + 			stepid = readx1 & TSCADC_FIFOREAD_CHNLID_MASK;
- + 			stepid = stepid >> 0x10;
- + 
- + 			if (stepid == map_val) {
- + 				readx1 = readx1 & TSCADC_FIFOREAD_DATA_MASK;
- + 				*val = readx1;
- + 			}
- + 		}
- + 		return IIO_VAL_INT;
- + 	}
- + }
- + 
- + static const struct iio_info tiadc_info = {
- + 	.read_raw = &tiadc_read_raw,
- + 	.attrs = &tiadc_attribute_group,
- + };
- + 
- + static int __devinit tiadc_probe(struct platform_device *pdev)
- + {
- + 	struct iio_dev		*idev;
- + 	struct adc_device	*adc_dev = NULL;
- + 	struct ti_tscadc_dev	*tscadc_dev = pdev->dev.platform_data;
- + 	struct mfd_tscadc_board	*pdata;
- + 	int			err;
- + 
- + 	pdata = (struct mfd_tscadc_board *)tscadc_dev->dev->platform_data;
- + 	if (!pdata || !pdata->adc_init)  {
- + 		dev_err(tscadc_dev->dev, "Could not find platform data\n");
- + 		return -EINVAL;
- + 	}
- + 
- + 	idev = iio_allocate_device(sizeof(struct adc_device));
- + 	if (idev == NULL) {
- + 		dev_err(&pdev->dev, "failed to allocate iio device.\n");
- + 		err = -ENOMEM;
- + 		goto err_ret;
- + 	}
- + 	adc_dev = iio_priv(idev);
- + 
- + 	tscadc_dev->adc = adc_dev;
- + 	adc_dev->mfd_tscadc = tscadc_dev;
- + 	adc_dev->idev = idev;
- + 	adc_dev->channels = pdata->adc_init->adc_channels;
- + 	adc_dev->irq = tscadc_dev->irq;
- + 
- + 	idev->dev.parent = &pdev->dev;
- + 	idev->name = dev_name(&pdev->dev);
- + 	idev->modes = INDIO_DIRECT_MODE;
- + 	idev->info = &tiadc_info;
- + 
- + 	/* by default driver comes up with oneshot mode */
- + 	adc_step_config(adc_dev, adc_dev->is_continuous_mode);
- + 
- + 	/* program FIFO threshold to value minus 1 */
- + 	adc_writel(adc_dev, TSCADC_REG_FIFO1THR, FIFO1_THRESHOLD);
- + 
- + 	err = tiadc_channel_init(idev, adc_dev);
- + 	if (err < 0)
- + 		goto err_free_device;
- + 
- + 	init_waitqueue_head(&adc_dev->wq_data_avail);
- + 
- + 	err = request_irq(adc_dev->irq, tiadc_irq, IRQF_SHARED,
- + 		idev->name, idev);
- + 	if (err)
- + 		goto err_cleanup_channels;
- + 
- + 	err = tiadc_config_sw_ring(idev);
- + 	if (err)
- + 		goto err_free_irq;
- + 
- + 	err = iio_buffer_register(idev,
- + 			idev->channels, idev->num_channels);
- + 	if (err < 0)
- + 		goto err_free_sw_rb;
- + 
- + 	err = iio_device_register(idev);
- + 	if (err)
- + 		goto err_unregister;
- + 
- + 	dev_info(&pdev->dev, "attached adc driver\n");
- + 	platform_set_drvdata(pdev, idev);
- + 
- + 	return 0;
- + 
- + err_unregister:
- + 	iio_buffer_unregister(idev);
- + err_free_sw_rb:
- + 	iio_sw_rb_free(idev->buffer);
- + err_free_irq:
- + 	free_irq(adc_dev->irq, idev);
- + err_cleanup_channels:
- + 	tiadc_channel_remove(idev);
- + err_free_device:
- + 	iio_free_device(idev);
- + err_ret:
- + 	return err;
- + }
- + 
- + static int __devexit tiadc_remove(struct platform_device *pdev)
- + {
- + 	struct ti_tscadc_dev	*tscadc_dev = pdev->dev.platform_data;
- + 	struct adc_device	*adc_dev = tscadc_dev->adc;
- + 	struct iio_dev		*idev = adc_dev->idev;
- + 
- + 	free_irq(adc_dev->irq, idev);
- + 	iio_device_unregister(idev);
- + 	iio_buffer_unregister(idev);
- + 	iio_sw_rb_free(idev->buffer);
- + 	tiadc_channel_remove(idev);
- + 
- + 	tscadc_dev->adc = NULL;
- + 	iio_free_device(idev);
- + 
- + 	platform_set_drvdata(pdev, NULL);
- + 	return 0;
- + }
- + 
- + static int adc_suspend(struct platform_device *pdev, pm_message_t state)
- + {
- + 	struct ti_tscadc_dev   *tscadc_dev = pdev->dev.platform_data;
- + 	struct adc_device	*adc_dev = tscadc_dev->adc;
- + 	unsigned int idle;
- + 
- + 	if (!device_may_wakeup(tscadc_dev->dev)) {
- + 		idle = adc_readl(adc_dev, TSCADC_REG_CTRL);
- + 		idle &= ~(TSCADC_CNTRLREG_TSCSSENB);
- + 		adc_writel(adc_dev, TSCADC_REG_CTRL, (idle |
- + 				TSCADC_CNTRLREG_POWERDOWN));
- + 	}
- + 	return 0;
- + }
- + 
- + static int adc_resume(struct platform_device *pdev)
- + {
- + 	struct ti_tscadc_dev   *tscadc_dev = pdev->dev.platform_data;
- + 	struct adc_device	*adc_dev = tscadc_dev->adc;
- + 	unsigned int restore;
- + 
- + 	restore = adc_readl(adc_dev, TSCADC_REG_CTRL);
- + 	restore &= ~(TSCADC_CNTRLREG_TSCSSENB);
- + 	adc_writel(adc_dev, TSCADC_REG_CTRL, restore);
- + 
- + 	adc_writel(adc_dev, TSCADC_REG_FIFO1THR, FIFO1_THRESHOLD);
- + 	adc_step_config(adc_dev, adc_dev->is_continuous_mode);
- + 
- + 	/* Make sure ADC is powered up */
- + 	restore &= ~(TSCADC_CNTRLREG_POWERDOWN);
- + 	restore |= TSCADC_CNTRLREG_TSCSSENB;
- + 	adc_writel(adc_dev, TSCADC_REG_CTRL, restore);
- + 	return 0;
- + }
- + 
- + static struct platform_driver tiadc_driver = {
- + 	.driver = {
- + 		.name   = "tiadc",
- + 		.owner = THIS_MODULE,
- + 	},
- + 	.probe          = tiadc_probe,
- + 	.remove         = __devexit_p(tiadc_remove),
- + 	.suspend = adc_suspend,
- + 	.resume = adc_resume,
- + };
- + 
- + module_platform_driver(tiadc_driver);
- + 
- + MODULE_DESCRIPTION("TI ADC controller driver");
- + MODULE_AUTHOR("Rachna Patil <rachna@ti.com>");
- + MODULE_LICENSE("GPL");
- diff -crN linux-3.2.1_o/drivers/staging/iio/Documentation/generic_buffer.c linux-3.2.1/drivers/staging/iio/Documentation/generic_buffer.c
- *** linux-3.2.1_o/drivers/staging/iio/Documentation/generic_buffer.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/staging/iio/Documentation/generic_buffer.c	2014-05-15 13:25:14.875289429 +0900
- ***************
- *** 129,141 ****
-   	int fp;
-   
-   	int num_channels;
- ! 	char *trigger_name = NULL, *device_name = NULL;
-   	char *dev_dir_name, *buf_dir_name;
-   
- - 	int datardytrigger = 1;
-   	char *data;
-   	ssize_t read_size;
- ! 	int dev_num, trig_num;
-   	char *buffer_access;
-   	int scan_size;
-   	int noevents = 0;
- --- 129,140 ----
-   	int fp;
-   
-   	int num_channels;
- ! 	char *device_name = NULL;
-   	char *dev_dir_name, *buf_dir_name;
-   
-   	char *data;
-   	ssize_t read_size;
- ! 	int dev_num;
-   	char *buffer_access;
-   	int scan_size;
-   	int noevents = 0;
- ***************
- *** 148,157 ****
-   		case 'n':
-   			device_name = optarg;
-   			break;
- - 		case 't':
- - 			trigger_name = optarg;
- - 			datardytrigger = 0;
- - 			break;
-   		case 'e':
-   			noevents = 1;
-   			break;
- --- 147,152 ----
- ***************
- *** 182,209 ****
-   	printf("iio device number being used is %d\n", dev_num);
-   
-   	asprintf(&dev_dir_name, "%siio:device%d", iio_dir, dev_num);
- - 	if (trigger_name == NULL) {
- - 		/*
- - 		 * Build the trigger name. If it is device associated it's
- - 		 * name is <device_name>_dev[n] where n matches the device
- - 		 * number found above
- - 		 */
- - 		ret = asprintf(&trigger_name,
- - 			       "%s-dev%d", device_name, dev_num);
- - 		if (ret < 0) {
- - 			ret = -ENOMEM;
- - 			goto error_ret;
- - 		}
- - 	}
- - 
- - 	/* Verify the trigger exists */
- - 	trig_num = find_type_by_name(trigger_name, "trigger");
- - 	if (trig_num < 0) {
- - 		printf("Failed to find the trigger %s\n", trigger_name);
- - 		ret = -ENODEV;
- - 		goto error_free_triggername;
- - 	}
- - 	printf("iio trigger number being used is %d\n", trig_num);
-   
-   	/*
-   	 * Parse the files in scan_elements to identify what channels are
- --- 177,182 ----
- ***************
- *** 213,219 ****
-   	if (ret) {
-   		printf("Problem reading scan element information\n");
-   		printf("diag %s\n", dev_dir_name);
- ! 		goto error_free_triggername;
-   	}
-   
-   	/*
- --- 186,192 ----
-   	if (ret) {
-   		printf("Problem reading scan element information\n");
-   		printf("diag %s\n", dev_dir_name);
- ! 		goto error_ret;
-   	}
-   
-   	/*
- ***************
- *** 225,262 ****
-   		       "%siio:device%d/buffer", iio_dir, dev_num);
-   	if (ret < 0) {
-   		ret = -ENOMEM;
- ! 		goto error_free_triggername;
- ! 	}
- ! 	printf("%s %s\n", dev_dir_name, trigger_name);
- ! 	/* Set the device trigger to be the data rdy trigger found above */
- ! 	ret = write_sysfs_string_and_verify("trigger/current_trigger",
- ! 					dev_dir_name,
- ! 					trigger_name);
- ! 	if (ret < 0) {
- ! 		printf("Failed to write current_trigger file\n");
- ! 		goto error_free_buf_dir_name;
-   	}
- ! 
-   	/* Setup ring buffer parameters */
-   	ret = write_sysfs_int("length", buf_dir_name, buf_len);
-   	if (ret < 0)
-   		goto error_free_buf_dir_name;
- - 
-   	/* Enable the buffer */
-   	ret = write_sysfs_int("enable", buf_dir_name, 1);
-   	if (ret < 0)
-   		goto error_free_buf_dir_name;
- - 	scan_size = size_from_channelarray(infoarray, num_channels);
- - 	data = malloc(scan_size*buf_len);
- - 	if (!data) {
- - 		ret = -ENOMEM;
- - 		goto error_free_buf_dir_name;
- - 	}
-   
-   	ret = asprintf(&buffer_access, "/dev/iio:device%d", dev_num);
-   	if (ret < 0) {
-   		ret = -ENOMEM;
- ! 		goto error_free_data;
-   	}
-   
-   	/* Attempt to open non blocking the access dev */
- --- 198,219 ----
-   		       "%siio:device%d/buffer", iio_dir, dev_num);
-   	if (ret < 0) {
-   		ret = -ENOMEM;
- ! 		goto error_ret;
-   	}
- ! 	printf("%s \n", dev_dir_name);
-   	/* Setup ring buffer parameters */
-   	ret = write_sysfs_int("length", buf_dir_name, buf_len);
-   	if (ret < 0)
-   		goto error_free_buf_dir_name;
-   	/* Enable the buffer */
-   	ret = write_sysfs_int("enable", buf_dir_name, 1);
-   	if (ret < 0)
-   		goto error_free_buf_dir_name;
-   
-   	ret = asprintf(&buffer_access, "/dev/iio:device%d", dev_num);
-   	if (ret < 0) {
-   		ret = -ENOMEM;
- ! 		goto error_free_buf_dir_name;
-   	}
-   
-   	/* Attempt to open non blocking the access dev */
- ***************
- *** 264,299 ****
-   	if (fp == -1) { /*If it isn't there make the node */
-   		printf("Failed to open %s\n", buffer_access);
-   		ret = -errno;
- ! 		goto error_free_buffer_access;
-   	}
-   
-   	/* Wait for events 10 times */
-   	for (j = 0; j < num_loops; j++) {
- ! 		if (!noevents) {
- ! 			struct pollfd pfd = {
- ! 				.fd = fp,
- ! 				.events = POLLIN,
- ! 			};
- ! 
- ! 			poll(&pfd, 1, -1);
- ! 			toread = buf_len;
- ! 
- ! 		} else {
- ! 			usleep(timedelay);
- ! 			toread = 64;
- ! 		}
- ! 
-   		read_size = read(fp,
-   				 data,
- ! 				 toread*scan_size);
-   		if (read_size == -EAGAIN) {
-   			printf("nothing available\n");
-   			continue;
-   		}
- ! 		for (i = 0; i < read_size/scan_size; i++)
- ! 			process_scan(data + scan_size*i,
- ! 				     infoarray,
- ! 				     num_channels);
-   	}
-   
-   	/* Stop the ring buffer */
- --- 221,248 ----
-   	if (fp == -1) { /*If it isn't there make the node */
-   		printf("Failed to open %s\n", buffer_access);
-   		ret = -errno;
- ! 		goto error_free_buf_dir_name;
- ! 	}
- ! 
- ! 	scan_size = size_from_channelarray(infoarray, num_channels);
- ! 	data = malloc(scan_size*buf_len);
- ! 	if (!data) {
- ! 		ret = -ENOMEM;
- ! 		goto error_close_buffer_access;
-   	}
-   
-   	/* Wait for events 10 times */
-   	for (j = 0; j < num_loops; j++) {
- ! 		usleep(timedelay);
-   		read_size = read(fp,
-   				 data,
- ! 				 buf_len*scan_size);
-   		if (read_size == -EAGAIN) {
-   			printf("nothing available\n");
-   			continue;
-   		}
- ! 		for (i = 0; i < read_size/4; i++, data+=4)
- ! 			printf("ADC Value: %d\n", *(long*)data);
-   	}
-   
-   	/* Stop the ring buffer */
- ***************
- *** 301,321 ****
-   	if (ret < 0)
-   		goto error_close_buffer_access;
-   
- - 	/* Disconnect from the trigger - just write a dummy name.*/
- - 	write_sysfs_string("trigger/current_trigger",
- - 			dev_dir_name, "NULL");
- - 
-   error_close_buffer_access:
-   	close(fp);
- - error_free_data:
- - 	free(data);
- - error_free_buffer_access:
- - 	free(buffer_access);
-   error_free_buf_dir_name:
-   	free(buf_dir_name);
- - error_free_triggername:
- - 	if (datardytrigger)
- - 		free(trigger_name);
-   error_ret:
-   	return ret;
-   }
- --- 250,259 ----
- diff -crN linux-3.2.1_o/drivers/tty/serial/atmel_serial.c linux-3.2.1/drivers/tty/serial/atmel_serial.c
- *** linux-3.2.1_o/drivers/tty/serial/atmel_serial.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/tty/serial/atmel_serial.c	2014-05-15 13:25:14.890672580 +0900
- ***************
- *** 212,220 ****
-   {
-   	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
-   	unsigned int mode;
- - 	unsigned long flags;
-   
- ! 	spin_lock_irqsave(&port->lock, flags);
-   
-   	/* Disable interrupts */
-   	UART_PUT_IDR(port, atmel_port->tx_done_mask);
- --- 212,219 ----
-   {
-   	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
-   	unsigned int mode;
-   
- ! 	spin_lock(&port->lock);
-   
-   	/* Disable interrupts */
-   	UART_PUT_IDR(port, atmel_port->tx_done_mask);
- ***************
- *** 245,251 ****
-   	/* Enable interrupts */
-   	UART_PUT_IER(port, atmel_port->tx_done_mask);
-   
- ! 	spin_unlock_irqrestore(&port->lock, flags);
-   
-   }
-   
- --- 244,250 ----
-   	/* Enable interrupts */
-   	UART_PUT_IER(port, atmel_port->tx_done_mask);
-   
- ! 	spin_unlock(&port->lock);
-   
-   }
-   
- diff -crN linux-3.2.1_o/drivers/tty/serial/Kconfig linux-3.2.1/drivers/tty/serial/Kconfig
- *** linux-3.2.1_o/drivers/tty/serial/Kconfig	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/tty/serial/Kconfig	2014-05-15 13:25:14.903285560 +0900
- ***************
- *** 1324,1330 ****
-   
-   config SERIAL_OMAP
-   	tristate "OMAP serial port support"
- ! 	depends on ARCH_OMAP2 || ARCH_OMAP3 || ARCH_OMAP4
-   	select SERIAL_CORE
-   	help
-   	  If you have a machine based on an Texas Instruments OMAP CPU you
- --- 1324,1330 ----
-   
-   config SERIAL_OMAP
-   	tristate "OMAP serial port support"
- ! 	depends on ARCH_OMAP2 || ARCH_OMAP3 || ARCH_OMAP4 || ARCH_CKB
-   	select SERIAL_CORE
-   	help
-   	  If you have a machine based on an Texas Instruments OMAP CPU you
- diff -crN linux-3.2.1_o/drivers/tty/serial/omap-serial.c linux-3.2.1/drivers/tty/serial/omap-serial.c
- *** linux-3.2.1_o/drivers/tty/serial/omap-serial.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/tty/serial/omap-serial.c	2014-05-15 13:25:14.919294564 +0900
- ***************
- *** 37,53 ****
-   #include <linux/clk.h>
-   #include <linux/serial_core.h>
-   #include <linux/irq.h>
-   
-   #include <plat/dma.h>
-   #include <plat/dmtimer.h>
-   #include <plat/omap-serial.h>
-   
-   static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
-   
-   /* Forward declaration of functions */
-   static void uart_tx_dma_callback(int lch, u16 ch_status, void *data);
- ! static void serial_omap_rx_timeout(unsigned long uart_no);
-   static int serial_omap_start_rxdma(struct uart_omap_port *up);
-   
-   static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
-   {
- --- 37,60 ----
-   #include <linux/clk.h>
-   #include <linux/serial_core.h>
-   #include <linux/irq.h>
- + #include <linux/pm_runtime.h>
- + #include <linux/of.h>
-   
-   #include <plat/dma.h>
-   #include <plat/dmtimer.h>
-   #include <plat/omap-serial.h>
-   
- + #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
- + 
-   static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
-   
-   /* Forward declaration of functions */
-   static void uart_tx_dma_callback(int lch, u16 ch_status, void *data);
- ! static void serial_omap_rxdma_poll(unsigned long uart_no);
-   static int serial_omap_start_rxdma(struct uart_omap_port *up);
- + static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
- + 
- + static struct workqueue_struct *serial_omap_uart_wq;
-   
-   static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
-   {
- ***************
- *** 102,107 ****
- --- 109,116 ----
-   		omap_free_dma(up->uart_dma.rx_dma_channel);
-   		up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
-   		up->uart_dma.rx_dma_used = false;
- + 		pm_runtime_mark_last_busy(&up->pdev->dev);
- + 		pm_runtime_put_autosuspend(&up->pdev->dev);
-   	}
-   }
-   
- ***************
- *** 109,117 ****
-   {
-   	struct uart_omap_port *up = (struct uart_omap_port *)port;
-   
- ! 	dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->pdev->id);
-   	up->ier |= UART_IER_MSI;
-   	serial_out(up, UART_IER, up->ier);
-   }
-   
-   static void serial_omap_stop_tx(struct uart_port *port)
- --- 118,129 ----
-   {
-   	struct uart_omap_port *up = (struct uart_omap_port *)port;
-   
- ! 	dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
- ! 
- ! 	pm_runtime_get_sync(&up->pdev->dev);
-   	up->ier |= UART_IER_MSI;
-   	serial_out(up, UART_IER, up->ier);
- + 	pm_runtime_put(&up->pdev->dev);
-   }
-   
-   static void serial_omap_stop_tx(struct uart_port *port)
- ***************
- *** 129,158 ****
-   		omap_stop_dma(up->uart_dma.tx_dma_channel);
-   		omap_free_dma(up->uart_dma.tx_dma_channel);
-   		up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
-   	}
-   
-   	if (up->ier & UART_IER_THRI) {
-   		up->ier &= ~UART_IER_THRI;
-   		serial_out(up, UART_IER, up->ier);
-   	}
-   }
-   
-   static void serial_omap_stop_rx(struct uart_port *port)
-   {
-   	struct uart_omap_port *up = (struct uart_omap_port *)port;
-   
-   	if (up->use_dma)
-   		serial_omap_stop_rxdma(up);
-   	up->ier &= ~UART_IER_RLSI;
-   	up->port.read_status_mask &= ~UART_LSR_DR;
-   	serial_out(up, UART_IER, up->ier);
-   }
-   
- ! static inline void receive_chars(struct uart_omap_port *up, int *status)
-   {
-   	struct tty_struct *tty = up->port.state->port.tty;
- ! 	unsigned int flag;
- ! 	unsigned char ch, lsr = *status;
-   	int max_count = 256;
-   
-   	do {
- --- 141,180 ----
-   		omap_stop_dma(up->uart_dma.tx_dma_channel);
-   		omap_free_dma(up->uart_dma.tx_dma_channel);
-   		up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
- + 		pm_runtime_mark_last_busy(&up->pdev->dev);
- + 		pm_runtime_put_autosuspend(&up->pdev->dev);
-   	}
-   
- + 	pm_runtime_get_sync(&up->pdev->dev);
-   	if (up->ier & UART_IER_THRI) {
-   		up->ier &= ~UART_IER_THRI;
-   		serial_out(up, UART_IER, up->ier);
-   	}
- + 
- + 	pm_runtime_mark_last_busy(&up->pdev->dev);
- + 	pm_runtime_put_autosuspend(&up->pdev->dev);
-   }
-   
-   static void serial_omap_stop_rx(struct uart_port *port)
-   {
-   	struct uart_omap_port *up = (struct uart_omap_port *)port;
-   
- + 	pm_runtime_get_sync(&up->pdev->dev);
-   	if (up->use_dma)
-   		serial_omap_stop_rxdma(up);
-   	up->ier &= ~UART_IER_RLSI;
-   	up->port.read_status_mask &= ~UART_LSR_DR;
-   	serial_out(up, UART_IER, up->ier);
- + 	pm_runtime_mark_last_busy(&up->pdev->dev);
- + 	pm_runtime_put_autosuspend(&up->pdev->dev);
-   }
-   
- ! static inline void receive_chars(struct uart_omap_port *up,
- ! 		unsigned int *status)
-   {
-   	struct tty_struct *tty = up->port.state->port.tty;
- ! 	unsigned int flag, lsr = *status;
- ! 	unsigned char ch = 0;
-   	int max_count = 256;
-   
-   	do {
- ***************
- *** 262,268 ****
- --- 284,293 ----
-   	int ret = 0;
-   
-   	if (!up->use_dma) {
- + 		pm_runtime_get_sync(&up->pdev->dev);
-   		serial_omap_enable_ier_thri(up);
- + 		pm_runtime_mark_last_busy(&up->pdev->dev);
- + 		pm_runtime_put_autosuspend(&up->pdev->dev);
-   		return;
-   	}
-   
- ***************
- *** 272,277 ****
- --- 297,303 ----
-   	xmit = &up->port.state->xmit;
-   
-   	if (up->uart_dma.tx_dma_channel == OMAP_UART_DMA_CH_FREE) {
- + 		pm_runtime_get_sync(&up->pdev->dev);
-   		ret = omap_request_dma(up->uart_dma.uart_dma_tx,
-   				"UART Tx DMA",
-   				(void *)uart_tx_dma_callback, up,
- ***************
- *** 354,362 ****
-   	unsigned int iir, lsr;
-   	unsigned long flags;
-   
-   	iir = serial_in(up, UART_IIR);
- ! 	if (iir & UART_IIR_NO_INT)
-   		return IRQ_NONE;
-   
-   	spin_lock_irqsave(&up->port.lock, flags);
-   	lsr = serial_in(up, UART_LSR);
- --- 380,392 ----
-   	unsigned int iir, lsr;
-   	unsigned long flags;
-   
- + 	pm_runtime_get_sync(&up->pdev->dev);
-   	iir = serial_in(up, UART_IIR);
- ! 	if (iir & UART_IIR_NO_INT) {
- ! 		pm_runtime_mark_last_busy(&up->pdev->dev);
- ! 		pm_runtime_put_autosuspend(&up->pdev->dev);
-   		return IRQ_NONE;
- + 	}
-   
-   	spin_lock_irqsave(&up->port.lock, flags);
-   	lsr = serial_in(up, UART_LSR);
- ***************
- *** 378,383 ****
- --- 408,416 ----
-   		transmit_chars(up);
-   
-   	spin_unlock_irqrestore(&up->port.lock, flags);
- + 	pm_runtime_mark_last_busy(&up->pdev->dev);
- + 	pm_runtime_put_autosuspend(&up->pdev->dev);
- + 
-   	up->port_activity = jiffies;
-   	return IRQ_HANDLED;
-   }
- ***************
- *** 388,398 ****
-   	unsigned long flags = 0;
-   	unsigned int ret = 0;
-   
- ! 	dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->pdev->id);
-   	spin_lock_irqsave(&up->port.lock, flags);
-   	ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
-   	spin_unlock_irqrestore(&up->port.lock, flags);
- ! 
-   	return ret;
-   }
-   
- --- 421,432 ----
-   	unsigned long flags = 0;
-   	unsigned int ret = 0;
-   
- ! 	pm_runtime_get_sync(&up->pdev->dev);
- ! 	dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
-   	spin_lock_irqsave(&up->port.lock, flags);
-   	ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
-   	spin_unlock_irqrestore(&up->port.lock, flags);
- ! 	pm_runtime_put(&up->pdev->dev);
-   	return ret;
-   }
-   
- ***************
- *** 402,409 ****
-   	unsigned char status;
-   	unsigned int ret = 0;
-   
-   	status = check_modem_status(up);
- ! 	dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->pdev->id);
-   
-   	if (status & UART_MSR_DCD)
-   		ret |= TIOCM_CAR;
- --- 436,446 ----
-   	unsigned char status;
-   	unsigned int ret = 0;
-   
- + 	pm_runtime_get_sync(&up->pdev->dev);
-   	status = check_modem_status(up);
- ! 	pm_runtime_put(&up->pdev->dev);
- ! 
- ! 	dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
-   
-   	if (status & UART_MSR_DCD)
-   		ret |= TIOCM_CAR;
- ***************
- *** 421,427 ****
-   	struct uart_omap_port *up = (struct uart_omap_port *)port;
-   	unsigned char mcr = 0;
-   
- ! 	dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->pdev->id);
-   	if (mctrl & TIOCM_RTS)
-   		mcr |= UART_MCR_RTS;
-   	if (mctrl & TIOCM_DTR)
- --- 458,464 ----
-   	struct uart_omap_port *up = (struct uart_omap_port *)port;
-   	unsigned char mcr = 0;
-   
- ! 	dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
-   	if (mctrl & TIOCM_RTS)
-   		mcr |= UART_MCR_RTS;
-   	if (mctrl & TIOCM_DTR)
- ***************
- *** 433,440 ****
-   	if (mctrl & TIOCM_LOOP)
-   		mcr |= UART_MCR_LOOP;
-   
- ! 	mcr |= up->mcr;
- ! 	serial_out(up, UART_MCR, mcr);
-   }
-   
-   static void serial_omap_break_ctl(struct uart_port *port, int break_state)
- --- 470,480 ----
-   	if (mctrl & TIOCM_LOOP)
-   		mcr |= UART_MCR_LOOP;
-   
- ! 	pm_runtime_get_sync(&up->pdev->dev);
- ! 	up->mcr = serial_in(up, UART_MCR);
- ! 	up->mcr |= mcr;
- ! 	serial_out(up, UART_MCR, up->mcr);
- ! 	pm_runtime_put(&up->pdev->dev);
-   }
-   
-   static void serial_omap_break_ctl(struct uart_port *port, int break_state)
- ***************
- *** 442,448 ****
-   	struct uart_omap_port *up = (struct uart_omap_port *)port;
-   	unsigned long flags = 0;
-   
- ! 	dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->pdev->id);
-   	spin_lock_irqsave(&up->port.lock, flags);
-   	if (break_state == -1)
-   		up->lcr |= UART_LCR_SBC;
- --- 482,489 ----
-   	struct uart_omap_port *up = (struct uart_omap_port *)port;
-   	unsigned long flags = 0;
-   
- ! 	dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
- ! 	pm_runtime_get_sync(&up->pdev->dev);
-   	spin_lock_irqsave(&up->port.lock, flags);
-   	if (break_state == -1)
-   		up->lcr |= UART_LCR_SBC;
- ***************
- *** 450,455 ****
- --- 491,497 ----
-   		up->lcr &= ~UART_LCR_SBC;
-   	serial_out(up, UART_LCR, up->lcr);
-   	spin_unlock_irqrestore(&up->port.lock, flags);
- + 	pm_runtime_put(&up->pdev->dev);
-   }
-   
-   static int serial_omap_startup(struct uart_port *port)
- ***************
- *** 466,473 ****
-   	if (retval)
-   		return retval;
-   
- ! 	dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->pdev->id);
-   
-   	/*
-   	 * Clear the FIFO buffers and disable them.
-   	 * (they will be reenabled in set_termios())
- --- 508,516 ----
-   	if (retval)
-   		return retval;
-   
- ! 	dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
-   
- + 	pm_runtime_get_sync(&up->pdev->dev);
-   	/*
-   	 * Clear the FIFO buffers and disable them.
-   	 * (they will be reenabled in set_termios())
- ***************
- *** 505,512 ****
-   			(dma_addr_t *)&(up->uart_dma.tx_buf_dma_phys),
-   			0);
-   		init_timer(&(up->uart_dma.rx_timer));
- ! 		up->uart_dma.rx_timer.function = serial_omap_rx_timeout;
- ! 		up->uart_dma.rx_timer.data = up->pdev->id;
-   		/* Currently the buffer size is 4KB. Can increase it */
-   		up->uart_dma.rx_buf = dma_alloc_coherent(NULL,
-   			up->uart_dma.rx_buf_size,
- --- 548,555 ----
-   			(dma_addr_t *)&(up->uart_dma.tx_buf_dma_phys),
-   			0);
-   		init_timer(&(up->uart_dma.rx_timer));
- ! 		up->uart_dma.rx_timer.function = serial_omap_rxdma_poll;
- ! 		up->uart_dma.rx_timer.data = up->port.line;
-   		/* Currently the buffer size is 4KB. Can increase it */
-   		up->uart_dma.rx_buf = dma_alloc_coherent(NULL,
-   			up->uart_dma.rx_buf_size,
- ***************
- *** 523,528 ****
- --- 566,573 ----
-   	/* Enable module level wake up */
-   	serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
-   
- + 	pm_runtime_mark_last_busy(&up->pdev->dev);
- + 	pm_runtime_put_autosuspend(&up->pdev->dev);
-   	up->port_activity = jiffies;
-   	return 0;
-   }
- ***************
- *** 532,538 ****
-   	struct uart_omap_port *up = (struct uart_omap_port *)port;
-   	unsigned long flags = 0;
-   
- ! 	dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->pdev->id);
-   	/*
-   	 * Disable interrupts from this port
-   	 */
- --- 577,585 ----
-   	struct uart_omap_port *up = (struct uart_omap_port *)port;
-   	unsigned long flags = 0;
-   
- ! 	dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
- ! 
- ! 	pm_runtime_get_sync(&up->pdev->dev);
-   	/*
-   	 * Disable interrupts from this port
-   	 */
- ***************
- *** 566,571 ****
- --- 613,620 ----
-   			up->uart_dma.rx_buf_dma_phys);
-   		up->uart_dma.rx_buf = NULL;
-   	}
- + 
- + 	pm_runtime_put(&up->pdev->dev);
-   	free_irq(up->port.irq, up);
-   }
-   
- ***************
- *** 573,580 ****
-   serial_omap_configure_xonxoff
-   		(struct uart_omap_port *up, struct ktermios *termios)
-   {
- - 	unsigned char efr = 0;
- - 
-   	up->lcr = serial_in(up, UART_LCR);
-   	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
-   	up->efr = serial_in(up, UART_EFR);
- --- 622,627 ----
- ***************
- *** 584,591 ****
-   	serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
-   
-   	/* clear SW control mode bits */
- ! 	efr = up->efr;
- ! 	efr &= OMAP_UART_SW_CLR;
-   
-   	/*
-   	 * IXON Flag:
- --- 631,637 ----
-   	serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
-   
-   	/* clear SW control mode bits */
- ! 	up->efr &= OMAP_UART_SW_CLR;
-   
-   	/*
-   	 * IXON Flag:
- ***************
- *** 593,599 ****
-   	 * Transmit XON1, XOFF1
-   	 */
-   	if (termios->c_iflag & IXON)
- ! 		efr |= OMAP_UART_SW_TX;
-   
-   	/*
-   	 * IXOFF Flag:
- --- 639,645 ----
-   	 * Transmit XON1, XOFF1
-   	 */
-   	if (termios->c_iflag & IXON)
- ! 		up->efr |= OMAP_UART_SW_TX;
-   
-   	/*
-   	 * IXOFF Flag:
- ***************
- *** 601,607 ****
-   	 * Receiver compares XON1, XOFF1.
-   	 */
-   	if (termios->c_iflag & IXOFF)
- ! 		efr |= OMAP_UART_SW_RX;
-   
-   	serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
-   	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
- --- 647,653 ----
-   	 * Receiver compares XON1, XOFF1.
-   	 */
-   	if (termios->c_iflag & IXOFF)
- ! 		up->efr |= OMAP_UART_SW_RX;
-   
-   	serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
-   	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
- ***************
- *** 624,636 ****
-   	 * load the new software flow control mode IXON or IXOFF
-   	 * and restore the UARTi.EFR_REG[4] ENHANCED_EN value.
-   	 */
- ! 	serial_out(up, UART_EFR, efr | UART_EFR_SCD);
-   	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
-   
-   	serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR);
-   	serial_out(up, UART_LCR, up->lcr);
-   }
-   
-   static void
-   serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
-   			struct ktermios *old)
- --- 670,690 ----
-   	 * load the new software flow control mode IXON or IXOFF
-   	 * and restore the UARTi.EFR_REG[4] ENHANCED_EN value.
-   	 */
- ! 	serial_out(up, UART_EFR, up->efr | UART_EFR_SCD);
-   	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
-   
-   	serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR);
-   	serial_out(up, UART_LCR, up->lcr);
-   }
-   
- + static void serial_omap_uart_qos_work(struct work_struct *work)
- + {
- + 	struct uart_omap_port *up = container_of(work, struct uart_omap_port,
- + 						qos_work);
- + 
- + 	pm_qos_update_request(&up->pm_qos_request, up->latency);
- + }
- + 
-   static void
-   serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
-   			struct ktermios *old)
- ***************
- *** 671,676 ****
- --- 725,740 ----
-   	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
-   	quot = serial_omap_get_divisor(port, baud);
-   
- + 	/* calculate wakeup latency constraint */
- + 	up->calc_latency = (1000000 * up->port.fifosize) /
- + 				(1000 * baud / 8);
- + 	up->latency = up->calc_latency;
- + 	schedule_work(&up->qos_work);
- + 
- + 	up->dll = quot & 0xff;
- + 	up->dlh = quot >> 8;
- + 	up->mdr1 = UART_OMAP_MDR1_DISABLE;
- + 
-   	up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
-   			UART_FCR_ENABLE_FIFO;
-   	if (up->use_dma)
- ***************
- *** 680,685 ****
- --- 744,750 ----
-   	 * Ok, we're now changing the port state. Do it with
-   	 * interrupts disabled.
-   	 */
- + 	pm_runtime_get_sync(&up->pdev->dev);
-   	spin_lock_irqsave(&up->port.lock, flags);
-   
-   	/*
- ***************
- *** 723,728 ****
- --- 788,795 ----
-   		up->ier |= UART_IER_MSI;
-   	serial_out(up, UART_IER, up->ier);
-   	serial_out(up, UART_LCR, cval);		/* reset DLAB */
- + 	up->lcr = cval;
- + 	up->scr = OMAP_UART_SCR_TX_EMPTY;
-   
-   	/* FIFOs and DMA Settings */
-   
- ***************
- *** 749,765 ****
-   
-   	if (up->use_dma) {
-   		serial_out(up, UART_TI752_TLR, 0);
- ! 		serial_out(up, UART_OMAP_SCR,
- ! 			(UART_FCR_TRIGGER_4 | UART_FCR_TRIGGER_8));
-   	}
-   
-   	serial_out(up, UART_EFR, up->efr);
-   	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
-   	serial_out(up, UART_MCR, up->mcr);
-   
-   	/* Protocol, Baud Rate, and Interrupt Settings */
-   
- ! 	serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
-   	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
-   
-   	up->efr = serial_in(up, UART_EFR);
- --- 816,837 ----
-   
-   	if (up->use_dma) {
-   		serial_out(up, UART_TI752_TLR, 0);
- ! 		up->scr |= (UART_FCR_TRIGGER_4 | UART_FCR_TRIGGER_8);
-   	}
-   
- + 	serial_out(up, UART_OMAP_SCR, up->scr);
- + 
-   	serial_out(up, UART_EFR, up->efr);
-   	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
-   	serial_out(up, UART_MCR, up->mcr);
-   
-   	/* Protocol, Baud Rate, and Interrupt Settings */
-   
- ! 	if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
- ! 		serial_omap_mdr1_errataset(up, up->mdr1);
- ! 	else
- ! 		serial_out(up, UART_OMAP_MDR1, up->mdr1);
- ! 
-   	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
-   
-   	up->efr = serial_in(up, UART_EFR);
- ***************
- *** 769,776 ****
-   	serial_out(up, UART_IER, 0);
-   	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
-   
- ! 	serial_out(up, UART_DLL, quot & 0xff);          /* LS of divisor */
- ! 	serial_out(up, UART_DLM, quot >> 8);            /* MS of divisor */
-   
-   	serial_out(up, UART_LCR, 0);
-   	serial_out(up, UART_IER, up->ier);
- --- 841,848 ----
-   	serial_out(up, UART_IER, 0);
-   	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
-   
- ! 	serial_out(up, UART_DLL, up->dll);	/* LS of divisor */
- ! 	serial_out(up, UART_DLM, up->dlh);	/* MS of divisor */
-   
-   	serial_out(up, UART_LCR, 0);
-   	serial_out(up, UART_IER, up->ier);
- ***************
- *** 780,788 ****
-   	serial_out(up, UART_LCR, cval);
-   
-   	if (baud > 230400 && baud != 3000000)
- ! 		serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_13X_MODE);
-   	else
- ! 		serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE);
-   
-   	/* Hardware Flow Control Configuration */
-   
- --- 852,865 ----
-   	serial_out(up, UART_LCR, cval);
-   
-   	if (baud > 230400 && baud != 3000000)
- ! 		up->mdr1 = UART_OMAP_MDR1_13X_MODE;
-   	else
- ! 		up->mdr1 = UART_OMAP_MDR1_16X_MODE;
- ! 
- ! 	if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
- ! 		serial_omap_mdr1_errataset(up, up->mdr1);
- ! 	else
- ! 		serial_out(up, UART_OMAP_MDR1, up->mdr1);
-   
-   	/* Hardware Flow Control Configuration */
-   
- ***************
- *** 809,815 ****
-   	serial_omap_configure_xonxoff(up, termios);
-   
-   	spin_unlock_irqrestore(&up->port.lock, flags);
- ! 	dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->pdev->id);
-   }
-   
-   static void
- --- 886,893 ----
-   	serial_omap_configure_xonxoff(up, termios);
-   
-   	spin_unlock_irqrestore(&up->port.lock, flags);
- ! 	pm_runtime_put(&up->pdev->dev);
- ! 	dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
-   }
-   
-   static void
- ***************
- *** 819,825 ****
-   	struct uart_omap_port *up = (struct uart_omap_port *)port;
-   	unsigned char efr;
-   
- ! 	dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->pdev->id);
-   	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
-   	efr = serial_in(up, UART_EFR);
-   	serial_out(up, UART_EFR, efr | UART_EFR_ECB);
- --- 897,905 ----
-   	struct uart_omap_port *up = (struct uart_omap_port *)port;
-   	unsigned char efr;
-   
- ! 	dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
- ! 
- ! 	pm_runtime_get_sync(&up->pdev->dev);
-   	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
-   	efr = serial_in(up, UART_EFR);
-   	serial_out(up, UART_EFR, efr | UART_EFR_ECB);
- ***************
- *** 829,834 ****
- --- 909,923 ----
-   	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
-   	serial_out(up, UART_EFR, efr);
-   	serial_out(up, UART_LCR, 0);
- + 
- + 	if (!device_may_wakeup(&up->pdev->dev)) {
- + 		if (!state)
- + 			pm_runtime_forbid(&up->pdev->dev);
- + 		else
- + 			pm_runtime_allow(&up->pdev->dev);
- + 	}
- + 
- + 	pm_runtime_put(&up->pdev->dev);
-   }
-   
-   static void serial_omap_release_port(struct uart_port *port)
- ***************
- *** 847,853 ****
-   	struct uart_omap_port *up = (struct uart_omap_port *)port;
-   
-   	dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
- ! 							up->pdev->id);
-   	up->port.type = PORT_OMAP;
-   }
-   
- --- 936,942 ----
-   	struct uart_omap_port *up = (struct uart_omap_port *)port;
-   
-   	dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
- ! 							up->port.line);
-   	up->port.type = PORT_OMAP;
-   }
-   
- ***************
- *** 864,870 ****
-   {
-   	struct uart_omap_port *up = (struct uart_omap_port *)port;
-   
- ! 	dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->pdev->id);
-   	return up->name;
-   }
-   
- --- 953,959 ----
-   {
-   	struct uart_omap_port *up = (struct uart_omap_port *)port;
-   
- ! 	dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
-   	return up->name;
-   }
-   
- ***************
- *** 906,924 ****
-   static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
-   {
-   	struct uart_omap_port *up = (struct uart_omap_port *)port;
-   	wait_for_xmitr(up);
-   	serial_out(up, UART_TX, ch);
-   }
-   
-   static int serial_omap_poll_get_char(struct uart_port *port)
-   {
-   	struct uart_omap_port *up = (struct uart_omap_port *)port;
- ! 	unsigned int status = serial_in(up, UART_LSR);
-   
-   	if (!(status & UART_LSR_DR))
-   		return NO_POLL_CHAR;
-   
- ! 	return serial_in(up, UART_RX);
-   }
-   
-   #endif /* CONFIG_CONSOLE_POLL */
- --- 995,1020 ----
-   static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
-   {
-   	struct uart_omap_port *up = (struct uart_omap_port *)port;
- + 
- + 	pm_runtime_get_sync(&up->pdev->dev);
-   	wait_for_xmitr(up);
-   	serial_out(up, UART_TX, ch);
- + 	pm_runtime_put(&up->pdev->dev);
-   }
-   
-   static int serial_omap_poll_get_char(struct uart_port *port)
-   {
-   	struct uart_omap_port *up = (struct uart_omap_port *)port;
- ! 	unsigned int status;
-   
- + 	pm_runtime_get_sync(&up->pdev->dev);
- + 	status = serial_in(up, UART_LSR);
-   	if (!(status & UART_LSR_DR))
-   		return NO_POLL_CHAR;
-   
- ! 	status = serial_in(up, UART_RX);
- ! 	pm_runtime_put(&up->pdev->dev);
- ! 	return status;
-   }
-   
-   #endif /* CONFIG_CONSOLE_POLL */
- ***************
- *** 946,951 ****
- --- 1042,1049 ----
-   	unsigned int ier;
-   	int locked = 1;
-   
- + 	pm_runtime_get_sync(&up->pdev->dev);
- + 
-   	local_irq_save(flags);
-   	if (up->port.sysrq)
-   		locked = 0;
- ***************
- *** 978,983 ****
- --- 1076,1083 ----
-   	if (up->msr_saved_flags)
-   		check_modem_status(up);
-   
- + 	pm_runtime_mark_last_busy(&up->pdev->dev);
- + 	pm_runtime_put_autosuspend(&up->pdev->dev);
-   	if (locked)
-   		spin_unlock(&up->port.lock);
-   	local_irq_restore(flags);
- ***************
- *** 1014,1020 ****
-   
-   static void serial_omap_add_console_port(struct uart_omap_port *up)
-   {
- ! 	serial_omap_console_ports[up->pdev->id] = up;
-   }
-   
-   #define OMAP_CONSOLE	(&serial_omap_console)
- --- 1114,1120 ----
-   
-   static void serial_omap_add_console_port(struct uart_omap_port *up)
-   {
- ! 	serial_omap_console_ports[up->port.line] = up;
-   }
-   
-   #define OMAP_CONSOLE	(&serial_omap_console)
- ***************
- *** 1060,1085 ****
-   	.cons		= OMAP_CONSOLE,
-   };
-   
- ! static int
- ! serial_omap_suspend(struct platform_device *pdev, pm_message_t state)
-   {
- ! 	struct uart_omap_port *up = platform_get_drvdata(pdev);
-   
- - 	if (up)
-   		uart_suspend_port(&serial_omap_reg, &up->port);
-   	return 0;
-   }
-   
- ! static int serial_omap_resume(struct platform_device *dev)
-   {
- ! 	struct uart_omap_port *up = platform_get_drvdata(dev);
-   
-   	if (up)
-   		uart_resume_port(&serial_omap_reg, &up->port);
-   	return 0;
-   }
-   
- ! static void serial_omap_rx_timeout(unsigned long uart_no)
-   {
-   	struct uart_omap_port *up = ui[uart_no];
-   	unsigned int curr_dma_pos, curr_transmitted_size;
- --- 1160,1199 ----
-   	.cons		= OMAP_CONSOLE,
-   };
-   
- ! #ifdef CONFIG_SUSPEND
- ! static int serial_omap_suspend(struct device *dev)
-   {
- ! 	struct uart_omap_port *up = dev_get_drvdata(dev);
- ! 
- ! 	if (up) {
- !                 /*
- !                   In case suspending during Bluetooth traffic, after resume
- !                   the bluetooth is stuck.
- !                   It was identified that suspend is happening before the
- !                   UART buffer was fully drained which caused this hang after
- !                   resume. The following delay is a temporary workaround until
- !                   the issue is resolved properly.
- !                 */
- !                 msleep(10);
-   
-   		uart_suspend_port(&serial_omap_reg, &up->port);
- + 		flush_work_sync(&up->qos_work);
- + 	}
- + 
-   	return 0;
-   }
-   
- ! static int serial_omap_resume(struct device *dev)
-   {
- ! 	struct uart_omap_port *up = dev_get_drvdata(dev);
-   
-   	if (up)
-   		uart_resume_port(&serial_omap_reg, &up->port);
-   	return 0;
-   }
- + #endif
-   
- ! static void serial_omap_rxdma_poll(unsigned long uart_no)
-   {
-   	struct uart_omap_port *up = ui[uart_no];
-   	unsigned int curr_dma_pos, curr_transmitted_size;
- ***************
- *** 1089,1097 ****
-   	if ((curr_dma_pos == up->uart_dma.prev_rx_dma_pos) ||
-   			     (curr_dma_pos == 0)) {
-   		if (jiffies_to_msecs(jiffies - up->port_activity) <
- ! 							RX_TIMEOUT) {
-   			mod_timer(&up->uart_dma.rx_timer, jiffies +
- ! 				usecs_to_jiffies(up->uart_dma.rx_timeout));
-   		} else {
-   			serial_omap_stop_rxdma(up);
-   			up->ier |= (UART_IER_RDI | UART_IER_RLSI);
- --- 1203,1211 ----
-   	if ((curr_dma_pos == up->uart_dma.prev_rx_dma_pos) ||
-   			     (curr_dma_pos == 0)) {
-   		if (jiffies_to_msecs(jiffies - up->port_activity) <
- ! 						up->uart_dma.rx_timeout) {
-   			mod_timer(&up->uart_dma.rx_timer, jiffies +
- ! 				usecs_to_jiffies(up->uart_dma.rx_poll_rate));
-   		} else {
-   			serial_omap_stop_rxdma(up);
-   			up->ier |= (UART_IER_RDI | UART_IER_RLSI);
- ***************
- *** 1120,1126 ****
-   		}
-   	} else  {
-   		mod_timer(&up->uart_dma.rx_timer, jiffies +
- ! 			usecs_to_jiffies(up->uart_dma.rx_timeout));
-   	}
-   	up->port_activity = jiffies;
-   }
- --- 1234,1240 ----
-   		}
-   	} else  {
-   		mod_timer(&up->uart_dma.rx_timer, jiffies +
- ! 			usecs_to_jiffies(up->uart_dma.rx_poll_rate));
-   	}
-   	up->port_activity = jiffies;
-   }
- ***************
- *** 1135,1140 ****
- --- 1249,1255 ----
-   	int ret = 0;
-   
-   	if (up->uart_dma.rx_dma_channel == -1) {
- + 		pm_runtime_get_sync(&up->pdev->dev);
-   		ret = omap_request_dma(up->uart_dma.uart_dma_rx,
-   				"UART Rx DMA",
-   				(void *)uart_rx_dma_callback, up,
- ***************
- *** 1158,1164 ****
-   	/* FIXME: Cache maintenance needed here? */
-   	omap_start_dma(up->uart_dma.rx_dma_channel);
-   	mod_timer(&up->uart_dma.rx_timer, jiffies +
- ! 				usecs_to_jiffies(up->uart_dma.rx_timeout));
-   	up->uart_dma.rx_dma_used = true;
-   	return ret;
-   }
- --- 1273,1279 ----
-   	/* FIXME: Cache maintenance needed here? */
-   	omap_start_dma(up->uart_dma.rx_dma_channel);
-   	mod_timer(&up->uart_dma.rx_timer, jiffies +
- ! 				usecs_to_jiffies(up->uart_dma.rx_poll_rate));
-   	up->uart_dma.rx_dma_used = true;
-   	return ret;
-   }
- ***************
- *** 1221,1226 ****
- --- 1336,1354 ----
-   	return;
-   }
-   
- + static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
- + {
- + 	struct omap_uart_port_info *omap_up_info;
- + 
- + 	omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
- + 	if (!omap_up_info)
- + 		return NULL; /* out of memory */
- + 
- + 	of_property_read_u32(dev->of_node, "clock-frequency",
- + 					 &omap_up_info->uartclk);
- + 	return omap_up_info;
- + }
- + 
-   static int serial_omap_probe(struct platform_device *pdev)
-   {
-   	struct uart_omap_port	*up;
- ***************
- *** 1228,1233 ****
- --- 1356,1364 ----
-   	struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
-   	int ret = -ENOSPC;
-   
- + 	if (pdev->dev.of_node)
- + 		omap_up_info = of_get_uart_port_info(&pdev->dev);
- + 
-   	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-   	if (!mem) {
-   		dev_err(&pdev->dev, "no mem resource?\n");
- ***************
- *** 1263,1269 ****
-   		ret = -ENOMEM;
-   		goto do_release_region;
-   	}
- - 	sprintf(up->name, "OMAP UART%d", pdev->id);
-   	up->pdev = pdev;
-   	up->port.dev = &pdev->dev;
-   	up->port.type = PORT_OMAP;
- --- 1394,1399 ----
- ***************
- *** 1273,1306 ****
-   	up->port.regshift = 2;
-   	up->port.fifosize = 64;
-   	up->port.ops = &serial_omap_pops;
- - 	up->port.line = pdev->id;
-   
- ! 	up->port.membase = omap_up_info->membase;
- ! 	up->port.mapbase = omap_up_info->mapbase;
-   	up->port.flags = omap_up_info->flags;
- - 	up->port.irqflags = omap_up_info->irqflags;
-   	up->port.uartclk = omap_up_info->uartclk;
-   	up->uart_dma.uart_base = mem->start;
-   
-   	if (omap_up_info->dma_enabled) {
-   		up->uart_dma.uart_dma_tx = dma_tx->start;
-   		up->uart_dma.uart_dma_rx = dma_rx->start;
-   		up->use_dma = 1;
- ! 		up->uart_dma.rx_buf_size = 4096;
- ! 		up->uart_dma.rx_timeout = 2;
-   		spin_lock_init(&(up->uart_dma.tx_lock));
-   		spin_lock_init(&(up->uart_dma.rx_lock));
-   		up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
-   		up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
-   	}
-   
- ! 	ui[pdev->id] = up;
-   	serial_omap_add_console_port(up);
-   
-   	ret = uart_add_one_port(&serial_omap_reg, &up->port);
-   	if (ret != 0)
-   		goto do_release_region;
-   
-   	platform_set_drvdata(pdev, up);
-   	return 0;
-   err:
- --- 1403,1476 ----
-   	up->port.regshift = 2;
-   	up->port.fifosize = 64;
-   	up->port.ops = &serial_omap_pops;
-   
- ! 	if (pdev->dev.of_node)
- ! 		up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
- ! 	else
- ! 		up->port.line = pdev->id;
- ! 
- ! 	if (up->port.line < 0) {
- ! 		dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
- ! 								up->port.line);
- ! 		ret = -ENODEV;
- ! 		goto err;
- ! 	}
- ! 
- ! 	sprintf(up->name, "OMAP UART%d", up->port.line);
- ! 	up->port.mapbase = mem->start;
- ! 	up->port.membase = ioremap(mem->start, resource_size(mem));
- ! 	if (!up->port.membase) {
- ! 		dev_err(&pdev->dev, "can't ioremap UART\n");
- ! 		ret = -ENOMEM;
- ! 		goto err;
- ! 	}
- ! 
-   	up->port.flags = omap_up_info->flags;
-   	up->port.uartclk = omap_up_info->uartclk;
- + 	if (!up->port.uartclk) {
- + 		up->port.uartclk = DEFAULT_CLK_SPEED;
- + 		dev_warn(&pdev->dev, "No clock speed specified: using default:"
- + 						"%d\n", DEFAULT_CLK_SPEED);
- + 	}
-   	up->uart_dma.uart_base = mem->start;
- + 	up->errata = omap_up_info->errata;
-   
-   	if (omap_up_info->dma_enabled) {
-   		up->uart_dma.uart_dma_tx = dma_tx->start;
-   		up->uart_dma.uart_dma_rx = dma_rx->start;
-   		up->use_dma = 1;
- ! 		up->uart_dma.rx_buf_size = omap_up_info->dma_rx_buf_size;
- ! 		up->uart_dma.rx_timeout = omap_up_info->dma_rx_timeout;
- ! 		up->uart_dma.rx_poll_rate = omap_up_info->dma_rx_poll_rate;
-   		spin_lock_init(&(up->uart_dma.tx_lock));
-   		spin_lock_init(&(up->uart_dma.rx_lock));
-   		up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
-   		up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
-   	}
-   
- ! 	up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
- ! 	up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
- ! 	pm_qos_add_request(&up->pm_qos_request,
- ! 		PM_QOS_CPU_DMA_LATENCY, up->latency);
- ! 	serial_omap_uart_wq = create_singlethread_workqueue(up->name);
- ! 	INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
- ! 
- ! 	pm_runtime_use_autosuspend(&pdev->dev);
- ! 	pm_runtime_set_autosuspend_delay(&pdev->dev,
- ! 			omap_up_info->autosuspend_timeout);
- ! 
- ! 	pm_runtime_irq_safe(&pdev->dev);
- ! 	pm_runtime_enable(&pdev->dev);
- ! 	pm_runtime_get_sync(&pdev->dev);
- ! 
- ! 	ui[up->port.line] = up;
-   	serial_omap_add_console_port(up);
-   
-   	ret = uart_add_one_port(&serial_omap_reg, &up->port);
-   	if (ret != 0)
-   		goto do_release_region;
-   
- + 	pm_runtime_put(&pdev->dev);
-   	platform_set_drvdata(pdev, up);
-   	return 0;
-   err:
- ***************
- *** 1315,1336 ****
-   {
-   	struct uart_omap_port *up = platform_get_drvdata(dev);
-   
- - 	platform_set_drvdata(dev, NULL);
-   	if (up) {
-   		uart_remove_one_port(&serial_omap_reg, &up->port);
-   		kfree(up);
-   	}
-   	return 0;
-   }
-   
-   static struct platform_driver serial_omap_driver = {
-   	.probe          = serial_omap_probe,
-   	.remove         = serial_omap_remove,
- - 
- - 	.suspend	= serial_omap_suspend,
- - 	.resume		= serial_omap_resume,
-   	.driver		= {
-   		.name	= DRIVER_NAME,
-   	},
-   };
-   
- --- 1485,1652 ----
-   {
-   	struct uart_omap_port *up = platform_get_drvdata(dev);
-   
-   	if (up) {
- + 		pm_runtime_disable(&up->pdev->dev);
-   		uart_remove_one_port(&serial_omap_reg, &up->port);
- + 		pm_qos_remove_request(&up->pm_qos_request);
- + 
-   		kfree(up);
-   	}
- + 
- + 	platform_set_drvdata(dev, NULL);
-   	return 0;
-   }
-   
- + /*
- +  * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
- +  * The access to uart register after MDR1 Access
- +  * causes UART to corrupt data.
- +  *
- +  * Need a delay =
- +  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
- +  * give 10 times as much
- +  */
- + static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
- + {
- + 	u8 timeout = 255;
- + 
- + 	serial_out(up, UART_OMAP_MDR1, mdr1);
- + 	udelay(2);
- + 	serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
- + 			UART_FCR_CLEAR_RCVR);
- + 	/*
- + 	 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
- + 	 * TX_FIFO_E bit is 1.
- + 	 */
- + 	while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
- + 				(UART_LSR_THRE | UART_LSR_DR))) {
- + 		timeout--;
- + 		if (!timeout) {
- + 			/* Should *never* happen. we warn and carry on */
- + 			dev_crit(&up->pdev->dev, "Errata i202: timedout %x\n",
- + 						serial_in(up, UART_LSR));
- + 			break;
- + 		}
- + 		udelay(1);
- + 	}
- + }
- + 
- + static void serial_omap_restore_context(struct uart_omap_port *up)
- + {
- + 	if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
- + 		serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
- + 	else
- + 		serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
- + 
- + 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
- + 	serial_out(up, UART_EFR, UART_EFR_ECB);
- + 	serial_out(up, UART_LCR, 0x0); /* Operational mode */
- + 	serial_out(up, UART_IER, 0x0);
- + 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
- + 	serial_out(up, UART_DLL, up->dll);
- + 	serial_out(up, UART_DLM, up->dlh);
- + 	serial_out(up, UART_LCR, 0x0); /* Operational mode */
- + 	serial_out(up, UART_IER, up->ier);
- + 	serial_out(up, UART_FCR, up->fcr);
- + 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
- + 	serial_out(up, UART_MCR, up->mcr);
- + 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
- + 	serial_out(up, UART_OMAP_SCR, up->scr);
- + 	serial_out(up, UART_EFR, up->efr);
- + 	serial_out(up, UART_LCR, up->lcr);
- + 	if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
- + 		serial_omap_mdr1_errataset(up, up->mdr1);
- + 	else
- + 		serial_out(up, UART_OMAP_MDR1, up->mdr1);
- + }
- + 
- + #ifdef CONFIG_PM_RUNTIME
- + static int serial_omap_runtime_suspend(struct device *dev)
- + {
- + 	struct uart_omap_port *up = dev_get_drvdata(dev);
- + 	struct omap_uart_port_info *pdata = dev->platform_data;
- + 
- + 	if (!up)
- + 		return -EINVAL;
- + 
- + 	if (!pdata || !pdata->enable_wakeup)
- + 		return 0;
- + 
- + 	if (pdata->get_context_loss_count)
- + 		up->context_loss_cnt = pdata->get_context_loss_count(dev);
- + 
- + 	if (device_may_wakeup(dev)) {
- + 		if (!up->wakeups_enabled) {
- + 			pdata->enable_wakeup(up->pdev, true);
- + 			up->wakeups_enabled = true;
- + 		}
- + 	} else {
- + 		if (up->wakeups_enabled) {
- + 			pdata->enable_wakeup(up->pdev, false);
- + 			up->wakeups_enabled = false;
- + 		}
- + 	}
- + 
- + 	/* Errata i291 */
- + 	if (up->use_dma && pdata->set_forceidle &&
- + 			(up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
- + 		pdata->set_forceidle(up->pdev);
- + 
- + 	up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
- + 	schedule_work(&up->qos_work);
- + 
- + 	return 0;
- + }
- + 
- + static int serial_omap_runtime_resume(struct device *dev)
- + {
- + 	struct uart_omap_port *up = dev_get_drvdata(dev);
- + 	struct omap_uart_port_info *pdata = dev->platform_data;
- + 
- + 	if (up) {
- + 		if (pdata->get_context_loss_count) {
- + 			u32 loss_cnt = pdata->get_context_loss_count(dev);
- + 
- + 			if (up->context_loss_cnt != loss_cnt)
- + 				serial_omap_restore_context(up);
- + 		}
- + 
- + 		/* Errata i291 */
- + 		if (up->use_dma && pdata->set_noidle &&
- + 				(up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
- + 			pdata->set_noidle(up->pdev);
- + 
- + 		up->latency = up->calc_latency;
- + 		schedule_work(&up->qos_work);
- + 	}
- + 
- + 	return 0;
- + }
- + #endif
- + 
- + static const struct dev_pm_ops serial_omap_dev_pm_ops = {
- + 	SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
- + 	SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
- + 				serial_omap_runtime_resume, NULL)
- + };
- + 
- + #if defined(CONFIG_OF)
- + static const struct of_device_id omap_serial_of_match[] = {
- + 	{ .compatible = "ti,omap2-uart" },
- + 	{ .compatible = "ti,omap3-uart" },
- + 	{ .compatible = "ti,omap4-uart" },
- + 	{},
- + };
- + MODULE_DEVICE_TABLE(of, omap_serial_of_match);
- + #endif
- + 
-   static struct platform_driver serial_omap_driver = {
-   	.probe          = serial_omap_probe,
-   	.remove         = serial_omap_remove,
-   	.driver		= {
-   		.name	= DRIVER_NAME,
- + 		.pm	= &serial_omap_dev_pm_ops,
- + 		.of_match_table = of_match_ptr(omap_serial_of_match),
-   	},
-   };
-   
- diff -crN linux-3.2.1_o/drivers/uio/Kconfig linux-3.2.1/drivers/uio/Kconfig
- *** linux-3.2.1_o/drivers/uio/Kconfig	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/uio/Kconfig	2014-05-15 13:25:14.981387131 +0900
- ***************
- *** 96,104 ****
-   
-   config UIO_PRUSS
-   	tristate "Texas Instruments PRUSS driver"
- ! 	depends on ARCH_DAVINCI_DA850
-   	help
- ! 	  PRUSS driver for OMAPL138/DA850/AM18XX devices
-   	  PRUSS driver requires user space components, examples and user space
-   	  driver is available from below SVN repo - you may use anonymous login
-   
- --- 96,104 ----
-   
-   config UIO_PRUSS
-   	tristate "Texas Instruments PRUSS driver"
- ! 	depends on ARCH_DAVINCI_DA850 || SOC_OMAPAM33XX
-   	help
- ! 	  PRUSS driver for OMAPL138/DA850/AM18XX/AM33XX devices
-   	  PRUSS driver requires user space components, examples and user space
-   	  driver is available from below SVN repo - you may use anonymous login
-   
- diff -crN linux-3.2.1_o/drivers/uio/uio_pruss.c linux-3.2.1/drivers/uio/uio_pruss.c
- *** linux-3.2.1_o/drivers/uio/uio_pruss.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/uio/uio_pruss.c	2014-05-15 13:25:14.983324758 +0900
- ***************
- *** 25,31 ****
- --- 25,38 ----
-   #include <linux/clk.h>
-   #include <linux/dma-mapping.h>
-   #include <linux/slab.h>
- + 
- + #ifdef ARCH_DAVINCI_DA850
- + #define ENABLE_SRAM_SUPPORT
- + #endif
- + 
- + #ifdef ENABLE_SRAM_SUPPORT
-   #include <mach/sram.h>
- + #endif
-   
-   #define DRV_NAME "pruss_uio"
-   #define DRV_VERSION "1.0"
- ***************
- *** 62,68 ****
-   struct uio_pruss_dev {
-   	struct uio_info *info;
-   	struct clk *pruss_clk;
- ! 	dma_addr_t sram_paddr;
-   	dma_addr_t ddr_paddr;
-   	void __iomem *prussio_vaddr;
-   	void *sram_vaddr;
- --- 69,75 ----
-   struct uio_pruss_dev {
-   	struct uio_info *info;
-   	struct clk *pruss_clk;
- ! 	phys_addr_t sram_paddr;
-   	dma_addr_t ddr_paddr;
-   	void __iomem *prussio_vaddr;
-   	void *sram_vaddr;
- ***************
- *** 105,112 ****
-   		dma_free_coherent(&dev->dev, extram_pool_sz, gdev->ddr_vaddr,
-   			gdev->ddr_paddr);
-   	}
-   	if (gdev->sram_vaddr)
- ! 		sram_free(gdev->sram_vaddr, sram_pool_sz);
-   	kfree(gdev->info);
-   	clk_put(gdev->pruss_clk);
-   	kfree(gdev);
- --- 112,122 ----
-   		dma_free_coherent(&dev->dev, extram_pool_sz, gdev->ddr_vaddr,
-   			gdev->ddr_paddr);
-   	}
- + #ifdef ENABLE_SRAM_SUPPORT
-   	if (gdev->sram_vaddr)
- ! 		gen_pool_free(davinci_gen_pool,
- ! 			      (unsigned long)gdev->sram_vaddr, sram_pool_sz);
- ! #endif
-   	kfree(gdev->info);
-   	clk_put(gdev->pruss_clk);
-   	kfree(gdev);
- ***************
- *** 152,163 ****
-   		goto out_free;
-   	}
-   
- ! 	gdev->sram_vaddr = sram_alloc(sram_pool_sz, &(gdev->sram_paddr));
-   	if (!gdev->sram_vaddr) {
-   		dev_err(&dev->dev, "Could not allocate SRAM pool\n");
-   		goto out_free;
-   	}
-   
-   	gdev->ddr_vaddr = dma_alloc_coherent(&dev->dev, extram_pool_sz,
-   				&(gdev->ddr_paddr), GFP_KERNEL | GFP_DMA);
-   	if (!gdev->ddr_vaddr) {
- --- 162,178 ----
-   		goto out_free;
-   	}
-   
- ! #ifdef ENABLE_SRAM_SUPPORT
- ! 	gdev->sram_vaddr = (void *)gen_pool_alloc(davinci_gen_pool,
- ! 						  sram_pool_sz);
-   	if (!gdev->sram_vaddr) {
-   		dev_err(&dev->dev, "Could not allocate SRAM pool\n");
-   		goto out_free;
-   	}
-   
- + 	gdev->sram_paddr = gen_pool_virt_to_phys(davinci_gen_pool,
- + 					(unsigned long)gdev->sram_vaddr);
- + #endif
-   	gdev->ddr_vaddr = dma_alloc_coherent(&dev->dev, extram_pool_sz,
-   				&(gdev->ddr_paddr), GFP_KERNEL | GFP_DMA);
-   	if (!gdev->ddr_vaddr) {
- ***************
- *** 179,186 ****
-   		p->mem[0].addr = regs_prussio->start;
-   		p->mem[0].size = resource_size(regs_prussio);
-   		p->mem[0].memtype = UIO_MEM_PHYS;
- - 
- - 		p->mem[1].addr = gdev->sram_paddr;
-   		p->mem[1].size = sram_pool_sz;
-   		p->mem[1].memtype = UIO_MEM_PHYS;
-   
- --- 194,199 ----
- diff -crN linux-3.2.1_o/drivers/usb/class/cdc-acm.c linux-3.2.1/drivers/usb/class/cdc-acm.c
- *** linux-3.2.1_o/drivers/usb/class/cdc-acm.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/class/cdc-acm.c	2014-05-15 13:25:14.987360798 +0900
- ***************
- *** 554,571 ****
-   
-   static void acm_tty_hangup(struct tty_struct *tty)
-   {
- ! 	struct acm *acm;
- ! 
- ! 	mutex_lock(&open_mutex);
- ! 	acm = tty->driver_data;
- ! 
- ! 	if (!acm)
- ! 		goto out;
- ! 
-   	tty_port_hangup(&acm->port);
-   	acm_port_down(acm);
- - 
- - out:
-   	mutex_unlock(&open_mutex);
-   }
-   
- --- 554,563 ----
-   
-   static void acm_tty_hangup(struct tty_struct *tty)
-   {
- ! 	struct acm *acm = tty->driver_data;
-   	tty_port_hangup(&acm->port);
- + 	mutex_lock(&open_mutex);
-   	acm_port_down(acm);
-   	mutex_unlock(&open_mutex);
-   }
-   
- ***************
- *** 1191,1198 ****
-   		i = device_create_file(&intf->dev, &dev_attr_wCountryCodes);
-   		if (i < 0) {
-   			kfree(acm->country_codes);
- - 			acm->country_codes = NULL;
- - 			acm->country_code_size = 0;
-   			goto skip_countries;
-   		}
-   
- --- 1183,1188 ----
- ***************
- *** 1201,1208 ****
-   		if (i < 0) {
-   			device_remove_file(&intf->dev, &dev_attr_wCountryCodes);
-   			kfree(acm->country_codes);
- - 			acm->country_codes = NULL;
- - 			acm->country_code_size = 0;
-   			goto skip_countries;
-   		}
-   	}
- --- 1191,1196 ----
- diff -crN linux-3.2.1_o/drivers/usb/core/devio.c linux-3.2.1/drivers/usb/core/devio.c
- *** linux-3.2.1_o/drivers/usb/core/devio.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/core/devio.c	2014-05-15 13:25:14.987360798 +0900
- ***************
- *** 249,256 ****
-   static void free_async(struct async *as)
-   {
-   	put_pid(as->pid);
- ! 	if (as->cred)
- ! 		put_cred(as->cred);
-   	kfree(as->urb->transfer_buffer);
-   	kfree(as->urb->setup_packet);
-   	usb_free_urb(as->urb);
- --- 249,255 ----
-   static void free_async(struct async *as)
-   {
-   	put_pid(as->pid);
- ! 	put_cred(as->cred);
-   	kfree(as->urb->transfer_buffer);
-   	kfree(as->urb->setup_packet);
-   	usb_free_urb(as->urb);
- diff -crN linux-3.2.1_o/drivers/usb/core/hcd.c linux-3.2.1/drivers/usb/core/hcd.c
- *** linux-3.2.1_o/drivers/usb/core/hcd.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/core/hcd.c	2014-05-15 13:25:14.990589574 +0900
- ***************
- *** 1412,1421 ****
-   					ret = -EAGAIN;
-   				else
-   					urb->transfer_flags |= URB_DMA_MAP_SG;
- ! 				urb->num_mapped_sgs = n;
- ! 				if (n != urb->num_sgs)
-   					urb->transfer_flags |=
-   							URB_DMA_SG_COMBINED;
-   			} else if (urb->sg) {
-   				struct scatterlist *sg = urb->sg;
-   				urb->transfer_dma = dma_map_page(
- --- 1412,1422 ----
-   					ret = -EAGAIN;
-   				else
-   					urb->transfer_flags |= URB_DMA_MAP_SG;
- ! 				if (n != urb->num_sgs) {
- ! 					urb->num_sgs = n;
-   					urb->transfer_flags |=
-   							URB_DMA_SG_COMBINED;
- + 				}
-   			} else if (urb->sg) {
-   				struct scatterlist *sg = urb->sg;
-   				urb->transfer_dma = dma_map_page(
- diff -crN linux-3.2.1_o/drivers/usb/core/hub.c linux-3.2.1/drivers/usb/core/hub.c
- *** linux-3.2.1_o/drivers/usb/core/hub.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/core/hub.c	2014-05-15 13:25:14.990589574 +0900
- ***************
- *** 1296,1302 ****
-   	 * since that isn't a "real" hub.
-   	 */
-   	if (!hub_is_superspeed(hdev) || !hdev->parent)
- ! 		usb_enable_autosuspend(hdev);
-   
-   	if (hdev->level == MAX_TOPO_LEVEL) {
-   		dev_err(&intf->dev,
- --- 1296,1302 ----
-   	 * since that isn't a "real" hub.
-   	 */
-   	if (!hub_is_superspeed(hdev) || !hdev->parent)
- ! 		usb_disable_autosuspend(hdev);
-   
-   	if (hdev->level == MAX_TOPO_LEVEL) {
-   		dev_err(&intf->dev,
- diff -crN linux-3.2.1_o/drivers/usb/core/quirks.c linux-3.2.1/drivers/usb/core/quirks.c
- *** linux-3.2.1_o/drivers/usb/core/quirks.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/core/quirks.c	2014-05-15 13:25:14.994955905 +0900
- ***************
- *** 117,127 ****
-   	{ USB_DEVICE(0x06a3, 0x0006), .driver_info =
-   			USB_QUIRK_CONFIG_INTF_STRINGS },
-   
- - 	/* Guillemot Webcam Hercules Dualpix Exchange (2nd ID) */
- - 	{ USB_DEVICE(0x06f8, 0x0804), .driver_info = USB_QUIRK_RESET_RESUME },
- - 
-   	/* Guillemot Webcam Hercules Dualpix Exchange*/
- ! 	{ USB_DEVICE(0x06f8, 0x3005), .driver_info = USB_QUIRK_RESET_RESUME },
-   
-   	/* M-Systems Flash Disk Pioneers */
-   	{ USB_DEVICE(0x08ec, 0x1000), .driver_info = USB_QUIRK_RESET_RESUME },
- --- 117,124 ----
-   	{ USB_DEVICE(0x06a3, 0x0006), .driver_info =
-   			USB_QUIRK_CONFIG_INTF_STRINGS },
-   
-   	/* Guillemot Webcam Hercules Dualpix Exchange*/
- ! 	{ USB_DEVICE(0x06f8, 0x0804), .driver_info = USB_QUIRK_RESET_RESUME },
-   
-   	/* M-Systems Flash Disk Pioneers */
-   	{ USB_DEVICE(0x08ec, 0x1000), .driver_info = USB_QUIRK_RESET_RESUME },
- diff -crN linux-3.2.1_o/drivers/usb/dwc3/gadget.c linux-3.2.1/drivers/usb/dwc3/gadget.c
- *** linux-3.2.1_o/drivers/usb/dwc3/gadget.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/dwc3/gadget.c	2014-05-15 13:25:14.994955905 +0900
- ***************
- *** 1986,1992 ****
-   	dev_set_name(&dwc->gadget.dev, "gadget");
-   
-   	dwc->gadget.ops			= &dwc3_gadget_ops;
- ! 	dwc->gadget.is_dualspeed	= true;
-   	dwc->gadget.speed		= USB_SPEED_UNKNOWN;
-   	dwc->gadget.dev.parent		= dwc->dev;
-   
- --- 1986,1992 ----
-   	dev_set_name(&dwc->gadget.dev, "gadget");
-   
-   	dwc->gadget.ops			= &dwc3_gadget_ops;
- ! 	dwc->gadget.max_speed		= USB_SPEED_SUPER;
-   	dwc->gadget.speed		= USB_SPEED_UNKNOWN;
-   	dwc->gadget.dev.parent		= dwc->dev;
-   
- diff -crN linux-3.2.1_o/drivers/usb/gadget/amd5536udc.c linux-3.2.1/drivers/usb/gadget/amd5536udc.c
- *** linux-3.2.1_o/drivers/usb/gadget/amd5536udc.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/gadget/amd5536udc.c	2014-05-15 13:25:14.994955905 +0900
- ***************
- *** 1959,1965 ****
-   	u32 tmp;
-   
-   	if (!driver || !bind || !driver->setup
- ! 			|| driver->speed < USB_SPEED_HIGH)
-   		return -EINVAL;
-   	if (!dev)
-   		return -ENODEV;
- --- 1959,1965 ----
-   	u32 tmp;
-   
-   	if (!driver || !bind || !driver->setup
- ! 			|| driver->max_speed < USB_SPEED_HIGH)
-   		return -EINVAL;
-   	if (!dev)
-   		return -ENODEV;
- ***************
- *** 3349,3355 ****
-   	dev_set_name(&dev->gadget.dev, "gadget");
-   	dev->gadget.dev.release = gadget_release;
-   	dev->gadget.name = name;
- ! 	dev->gadget.is_dualspeed = 1;
-   
-   	/* init registers, interrupts, ... */
-   	startup_registers(dev);
- --- 3349,3355 ----
-   	dev_set_name(&dev->gadget.dev, "gadget");
-   	dev->gadget.dev.release = gadget_release;
-   	dev->gadget.name = name;
- ! 	dev->gadget.max_speed = USB_SPEED_HIGH;
-   
-   	/* init registers, interrupts, ... */
-   	startup_registers(dev);
- diff -crN linux-3.2.1_o/drivers/usb/gadget/at91_udc.c linux-3.2.1/drivers/usb/gadget/at91_udc.c
- *** linux-3.2.1_o/drivers/usb/gadget/at91_udc.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/gadget/at91_udc.c	2014-05-15 13:25:14.999172232 +0900
- ***************
- *** 1633,1639 ****
-   	unsigned long	flags;
-   
-   	if (!driver
- ! 			|| driver->speed < USB_SPEED_FULL
-   			|| !bind
-   			|| !driver->setup) {
-   		DBG("bad parameter.\n");
- --- 1633,1639 ----
-   	unsigned long	flags;
-   
-   	if (!driver
- ! 			|| driver->max_speed < USB_SPEED_FULL
-   			|| !bind
-   			|| !driver->setup) {
-   		DBG("bad parameter.\n");
- diff -crN linux-3.2.1_o/drivers/usb/gadget/atmel_usba_udc.c linux-3.2.1/drivers/usb/gadget/atmel_usba_udc.c
- *** linux-3.2.1_o/drivers/usb/gadget/atmel_usba_udc.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/gadget/atmel_usba_udc.c	2014-05-15 13:25:14.999172232 +0900
- ***************
- *** 1038,1044 ****
-   	.gadget	= {
-   		.ops		= &usba_udc_ops,
-   		.ep_list	= LIST_HEAD_INIT(the_udc.gadget.ep_list),
- ! 		.is_dualspeed	= 1,
-   		.name		= "atmel_usba_udc",
-   		.dev	= {
-   			.init_name	= "gadget",
- --- 1038,1044 ----
-   	.gadget	= {
-   		.ops		= &usba_udc_ops,
-   		.ep_list	= LIST_HEAD_INIT(the_udc.gadget.ep_list),
- ! 		.max_speed	= USB_SPEED_HIGH,
-   		.name		= "atmel_usba_udc",
-   		.dev	= {
-   			.init_name	= "gadget",
- diff -crN linux-3.2.1_o/drivers/usb/gadget/ci13xxx_udc.c linux-3.2.1/drivers/usb/gadget/ci13xxx_udc.c
- *** linux-3.2.1_o/drivers/usb/gadget/ci13xxx_udc.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/gadget/ci13xxx_udc.c	2014-05-15 13:25:15.003061120 +0900
- ***************
- *** 754,761 ****
-   
-   	n += scnprintf(buf + n, PAGE_SIZE - n, "speed             = %d\n",
-   		       gadget->speed);
-   	n += scnprintf(buf + n, PAGE_SIZE - n, "is_dualspeed      = %d\n",
- ! 		       gadget->is_dualspeed);
-   	n += scnprintf(buf + n, PAGE_SIZE - n, "is_otg            = %d\n",
-   		       gadget->is_otg);
-   	n += scnprintf(buf + n, PAGE_SIZE - n, "is_a_peripheral   = %d\n",
- --- 754,764 ----
-   
-   	n += scnprintf(buf + n, PAGE_SIZE - n, "speed             = %d\n",
-   		       gadget->speed);
- + 	n += scnprintf(buf + n, PAGE_SIZE - n, "max_speed         = %d\n",
- + 		       gadget->max_speed);
- + 	/* TODO: Scheduled for removal in 3.8. */
-   	n += scnprintf(buf + n, PAGE_SIZE - n, "is_dualspeed      = %d\n",
- ! 		       gadget_is_dualspeed(gadget));
-   	n += scnprintf(buf + n, PAGE_SIZE - n, "is_otg            = %d\n",
-   		       gadget->is_otg);
-   	n += scnprintf(buf + n, PAGE_SIZE - n, "is_a_peripheral   = %d\n",
- ***************
- *** 798,804 ****
-   	n += scnprintf(buf + n, PAGE_SIZE - n, "function  = %s\n",
-   		       (driver->function ? driver->function : ""));
-   	n += scnprintf(buf + n, PAGE_SIZE - n, "max speed = %d\n",
- ! 		       driver->speed);
-   
-   	return n;
-   }
- --- 801,807 ----
-   	n += scnprintf(buf + n, PAGE_SIZE - n, "function  = %s\n",
-   		       (driver->function ? driver->function : ""));
-   	n += scnprintf(buf + n, PAGE_SIZE - n, "max speed = %d\n",
- ! 		       driver->max_speed);
-   
-   	return n;
-   }
- ***************
- *** 2871,2877 ****
-   
-   	udc->gadget.ops          = &usb_gadget_ops;
-   	udc->gadget.speed        = USB_SPEED_UNKNOWN;
- ! 	udc->gadget.is_dualspeed = 1;
-   	udc->gadget.is_otg       = 0;
-   	udc->gadget.name         = driver->name;
-   
- --- 2874,2880 ----
-   
-   	udc->gadget.ops          = &usb_gadget_ops;
-   	udc->gadget.speed        = USB_SPEED_UNKNOWN;
- ! 	udc->gadget.max_speed    = USB_SPEED_HIGH;
-   	udc->gadget.is_otg       = 0;
-   	udc->gadget.name         = driver->name;
-   
- diff -crN linux-3.2.1_o/drivers/usb/gadget/composite.c linux-3.2.1/drivers/usb/gadget/composite.c
- *** linux-3.2.1_o/drivers/usb/gadget/composite.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/gadget/composite.c	2014-05-15 13:25:15.003061120 +0900
- ***************
- *** 1535,1543 ****
-   
-   static struct usb_gadget_driver composite_driver = {
-   #ifdef CONFIG_USB_GADGET_SUPERSPEED
- ! 	.speed		= USB_SPEED_SUPER,
-   #else
- ! 	.speed		= USB_SPEED_HIGH,
-   #endif
-   
-   	.unbind		= composite_unbind,
- --- 1535,1543 ----
-   
-   static struct usb_gadget_driver composite_driver = {
-   #ifdef CONFIG_USB_GADGET_SUPERSPEED
- ! 	.max_speed	= USB_SPEED_SUPER,
-   #else
- ! 	.max_speed	= USB_SPEED_HIGH,
-   #endif
-   
-   	.unbind		= composite_unbind,
- ***************
- *** 1584,1591 ****
-   		driver->iProduct = driver->name;
-   	composite_driver.function =  (char *) driver->name;
-   	composite_driver.driver.name = driver->name;
- ! 	composite_driver.speed = min((u8)composite_driver.speed,
- ! 				     (u8)driver->max_speed);
-   	composite = driver;
-   	composite_gadget_bind = bind;
-   
- --- 1584,1591 ----
-   		driver->iProduct = driver->name;
-   	composite_driver.function =  (char *) driver->name;
-   	composite_driver.driver.name = driver->name;
- ! 	composite_driver.max_speed =
- ! 		min_t(u8, composite_driver.max_speed, driver->max_speed);
-   	composite = driver;
-   	composite_gadget_bind = bind;
-   
- diff -crN linux-3.2.1_o/drivers/usb/gadget/dbgp.c linux-3.2.1/drivers/usb/gadget/dbgp.c
- *** linux-3.2.1_o/drivers/usb/gadget/dbgp.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/gadget/dbgp.c	2014-05-15 13:25:15.006656946 +0900
- ***************
- *** 404,410 ****
-   
-   static struct usb_gadget_driver dbgp_driver = {
-   	.function = "dbgp",
- ! 	.speed = USB_SPEED_HIGH,
-   	.unbind = dbgp_unbind,
-   	.setup = dbgp_setup,
-   	.disconnect = dbgp_disconnect,
- --- 404,410 ----
-   
-   static struct usb_gadget_driver dbgp_driver = {
-   	.function = "dbgp",
- ! 	.max_speed = USB_SPEED_HIGH,
-   	.unbind = dbgp_unbind,
-   	.setup = dbgp_setup,
-   	.disconnect = dbgp_disconnect,
- diff -crN linux-3.2.1_o/drivers/usb/gadget/dummy_hcd.c linux-3.2.1/drivers/usb/gadget/dummy_hcd.c
- *** linux-3.2.1_o/drivers/usb/gadget/dummy_hcd.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/gadget/dummy_hcd.c	2014-05-15 13:25:15.006656946 +0900
- ***************
- *** 823,841 ****
-   
-   	if (value && dum->driver) {
-   		if (mod_data.is_super_speed)
- ! 			dum->gadget.speed = dum->driver->speed;
-   		else if (mod_data.is_high_speed)
-   			dum->gadget.speed = min_t(u8, USB_SPEED_HIGH,
- ! 					dum->driver->speed);
-   		else
-   			dum->gadget.speed = USB_SPEED_FULL;
-   		dummy_udc_udpate_ep0(dum);
-   
- ! 		if (dum->gadget.speed < dum->driver->speed)
-   			dev_dbg(udc_dev(dum), "This device can perform faster"
- ! 					" if you connect it to a %s port...\n",
- ! 					(dum->driver->speed == USB_SPEED_SUPER ?
- ! 					 "SuperSpeed" : "HighSpeed"));
-   	}
-   	dum_hcd = gadget_to_dummy_hcd(_gadget);
-   
- --- 823,840 ----
-   
-   	if (value && dum->driver) {
-   		if (mod_data.is_super_speed)
- ! 			dum->gadget.speed = dum->driver->max_speed;
-   		else if (mod_data.is_high_speed)
-   			dum->gadget.speed = min_t(u8, USB_SPEED_HIGH,
- ! 					dum->driver->max_speed);
-   		else
-   			dum->gadget.speed = USB_SPEED_FULL;
-   		dummy_udc_udpate_ep0(dum);
-   
- ! 		if (dum->gadget.speed < dum->driver->max_speed)
-   			dev_dbg(udc_dev(dum), "This device can perform faster"
- ! 				" if you connect it to a %s port...\n",
- ! 				usb_speed_string(dum->driver->max_speed));
-   	}
-   	dum_hcd = gadget_to_dummy_hcd(_gadget);
-   
- ***************
- *** 898,904 ****
-   	struct dummy_hcd	*dum_hcd = gadget_to_dummy_hcd(g);
-   	struct dummy		*dum = dum_hcd->dum;
-   
- ! 	if (driver->speed == USB_SPEED_UNKNOWN)
-   		return -EINVAL;
-   
-   	/*
- --- 897,903 ----
-   	struct dummy_hcd	*dum_hcd = gadget_to_dummy_hcd(g);
-   	struct dummy		*dum = dum_hcd->dum;
-   
- ! 	if (driver->max_speed == USB_SPEED_UNKNOWN)
-   		return -EINVAL;
-   
-   	/*
- ***************
- *** 977,983 ****
-   
-   	dum->gadget.name = gadget_name;
-   	dum->gadget.ops = &dummy_ops;
- ! 	dum->gadget.is_dualspeed = 1;
-   
-   	dev_set_name(&dum->gadget.dev, "gadget");
-   	dum->gadget.dev.parent = &pdev->dev;
- --- 976,982 ----
-   
-   	dum->gadget.name = gadget_name;
-   	dum->gadget.ops = &dummy_ops;
- ! 	dum->gadget.max_speed = USB_SPEED_SUPER;
-   
-   	dev_set_name(&dum->gadget.dev, "gadget");
-   	dum->gadget.dev.parent = &pdev->dev;
- diff -crN linux-3.2.1_o/drivers/usb/gadget/epautoconf.c linux-3.2.1/drivers/usb/gadget/epautoconf.c
- *** linux-3.2.1_o/drivers/usb/gadget/epautoconf.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/gadget/epautoconf.c	2014-05-15 13:25:15.010635341 +0900
- ***************
- *** 149,155 ****
-   	switch (type) {
-   	case USB_ENDPOINT_XFER_INT:
-   		/* INT:  limit 64 bytes full speed, 1024 high/super speed */
- ! 		if (!gadget->is_dualspeed && max > 64)
-   			return 0;
-   		/* FALLTHROUGH */
-   
- --- 149,155 ----
-   	switch (type) {
-   	case USB_ENDPOINT_XFER_INT:
-   		/* INT:  limit 64 bytes full speed, 1024 high/super speed */
- ! 		if (!gadget_is_dualspeed(gadget) && max > 64)
-   			return 0;
-   		/* FALLTHROUGH */
-   
- ***************
- *** 157,168 ****
-   		/* ISO:  limit 1023 bytes full speed, 1024 high/super speed */
-   		if (ep->maxpacket < max)
-   			return 0;
- ! 		if (!gadget->is_dualspeed && max > 1023)
-   			return 0;
-   
-   		/* BOTH:  "high bandwidth" works only at high speed */
-   		if ((desc->wMaxPacketSize & cpu_to_le16(3<<11))) {
- ! 			if (!gadget->is_dualspeed)
-   				return 0;
-   			/* configure your hardware with enough buffering!! */
-   		}
- --- 157,168 ----
-   		/* ISO:  limit 1023 bytes full speed, 1024 high/super speed */
-   		if (ep->maxpacket < max)
-   			return 0;
- ! 		if (!gadget_is_dualspeed(gadget) && max > 1023)
-   			return 0;
-   
-   		/* BOTH:  "high bandwidth" works only at high speed */
-   		if ((desc->wMaxPacketSize & cpu_to_le16(3<<11))) {
- ! 			if (!gadget_is_dualspeed(gadget))
-   				return 0;
-   			/* configure your hardware with enough buffering!! */
-   		}
- ***************
- *** 380,385 ****
- --- 380,386 ----
-   
-   	list_for_each_entry (ep, &gadget->ep_list, ep_list) {
-   		ep->driver_data = NULL;
- + 		ep->desc = NULL;
-   	}
-   #ifdef	MANY_ENDPOINTS
-   	in_epnum = 0;
- diff -crN linux-3.2.1_o/drivers/usb/gadget/ether.c linux-3.2.1/drivers/usb/gadget/ether.c
- *** linux-3.2.1_o/drivers/usb/gadget/ether.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/gadget/ether.c	2014-05-15 13:25:15.010635341 +0900
- ***************
- *** 93,98 ****
- --- 93,102 ----
-   #endif
-   }
-   
- + static char manufacturer[50];
- + 
- + static u16 vendorID;
- + 
-   /*-------------------------------------------------------------------------*/
-   
-   /*
- ***************
- *** 201,208 ****
-   #define STRING_MANUFACTURER_IDX		0
-   #define STRING_PRODUCT_IDX		1
-   
- - static char manufacturer[50];
- - 
-   static struct usb_string strings_dev[] = {
-   	[STRING_MANUFACTURER_IDX].s = manufacturer,
-   	[STRING_PRODUCT_IDX].s = PREFIX DRIVER_DESC,
- --- 205,210 ----
- ***************
- *** 323,328 ****
- --- 325,332 ----
-   		device_desc.bNumConfigurations = 2;
-   	}
-   
- + 	vendorID = device_desc.idVendor;
- + 
-   	gcnum = usb_gadget_controller_number(gadget);
-   	if (gcnum >= 0)
-   		device_desc.bcdDevice = cpu_to_le16(0x0300 | gcnum);
- diff -crN linux-3.2.1_o/drivers/usb/gadget/f_ecm.c linux-3.2.1/drivers/usb/gadget/f_ecm.c
- *** linux-3.2.1_o/drivers/usb/gadget/f_ecm.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/gadget/f_ecm.c	2014-05-15 13:25:15.010635341 +0900
- ***************
- *** 690,695 ****
- --- 690,696 ----
-   	status = -ENODEV;
-   
-   	/* allocate instance-specific endpoints */
- + 	usb_ep_autoconfig_reset(cdev->gadget);
-   	ep = usb_ep_autoconfig(cdev->gadget, &fs_ecm_in_desc);
-   	if (!ep)
-   		goto fail;
- diff -crN linux-3.2.1_o/drivers/usb/gadget/file_storage.c linux-3.2.1/drivers/usb/gadget/file_storage.c
- *** linux-3.2.1_o/drivers/usb/gadget/file_storage.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/gadget/file_storage.c	2014-05-15 13:25:15.010635341 +0900
- ***************
- *** 3584,3590 ****
-   /*-------------------------------------------------------------------------*/
-   
-   static struct usb_gadget_driver		fsg_driver = {
- ! 	.speed		= USB_SPEED_SUPER,
-   	.function	= (char *) fsg_string_product,
-   	.unbind		= fsg_unbind,
-   	.disconnect	= fsg_disconnect,
- --- 3584,3590 ----
-   /*-------------------------------------------------------------------------*/
-   
-   static struct usb_gadget_driver		fsg_driver = {
- ! 	.max_speed	= USB_SPEED_SUPER,
-   	.function	= (char *) fsg_string_product,
-   	.unbind		= fsg_unbind,
-   	.disconnect	= fsg_disconnect,
- diff -crN linux-3.2.1_o/drivers/usb/gadget/f_rndis.c linux-3.2.1/drivers/usb/gadget/f_rndis.c
- *** linux-3.2.1_o/drivers/usb/gadget/f_rndis.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/gadget/f_rndis.c	2014-05-15 13:25:15.014736230 +0900
- ***************
- *** 684,689 ****
- --- 684,690 ----
-   	status = -ENODEV;
-   
-   	/* allocate instance-specific endpoints */
- + 	usb_ep_autoconfig_reset(cdev->gadget);
-   	ep = usb_ep_autoconfig(cdev->gadget, &fs_in_desc);
-   	if (!ep)
-   		goto fail;
- ***************
- *** 767,778 ****
-   	rndis_set_param_medium(rndis->config, NDIS_MEDIUM_802_3, 0);
-   	rndis_set_host_mac(rndis->config, rndis->ethaddr);
-   
- - #if 0
- - // FIXME
-   	if (rndis_set_param_vendor(rndis->config, vendorID,
-   				manufacturer))
- ! 		goto fail0;
- ! #endif
-   
-   	/* NOTE:  all that is done without knowing or caring about
-   	 * the network link ... which is unavailable to this code
- --- 768,776 ----
-   	rndis_set_param_medium(rndis->config, NDIS_MEDIUM_802_3, 0);
-   	rndis_set_host_mac(rndis->config, rndis->ethaddr);
-   
-   	if (rndis_set_param_vendor(rndis->config, vendorID,
-   				manufacturer))
- ! 		goto fail;
-   
-   	/* NOTE:  all that is done without knowing or caring about
-   	 * the network link ... which is unavailable to this code
- diff -crN linux-3.2.1_o/drivers/usb/gadget/fsl_qe_udc.c linux-3.2.1/drivers/usb/gadget/fsl_qe_udc.c
- *** linux-3.2.1_o/drivers/usb/gadget/fsl_qe_udc.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/gadget/fsl_qe_udc.c	2014-05-15 13:25:15.014736230 +0900
- ***************
- *** 2336,2342 ****
-   	if (!udc_controller)
-   		return -ENODEV;
-   
- ! 	if (!driver || driver->speed < USB_SPEED_FULL
-   			|| !bind || !driver->disconnect || !driver->setup)
-   		return -EINVAL;
-   
- --- 2336,2342 ----
-   	if (!udc_controller)
-   		return -ENODEV;
-   
- ! 	if (!driver || driver->max_speed < USB_SPEED_FULL
-   			|| !bind || !driver->disconnect || !driver->setup)
-   		return -EINVAL;
-   
- ***************
- *** 2350,2356 ****
-   	/* hook up the driver */
-   	udc_controller->driver = driver;
-   	udc_controller->gadget.dev.driver = &driver->driver;
- ! 	udc_controller->gadget.speed = (enum usb_device_speed)(driver->speed);
-   	spin_unlock_irqrestore(&udc_controller->lock, flags);
-   
-   	retval = bind(&udc_controller->gadget);
- --- 2350,2356 ----
-   	/* hook up the driver */
-   	udc_controller->driver = driver;
-   	udc_controller->gadget.dev.driver = &driver->driver;
- ! 	udc_controller->gadget.speed = driver->max_speed;
-   	spin_unlock_irqrestore(&udc_controller->lock, flags);
-   
-   	retval = bind(&udc_controller->gadget);
- diff -crN linux-3.2.1_o/drivers/usb/gadget/fsl_udc_core.c linux-3.2.1/drivers/usb/gadget/fsl_udc_core.c
- *** linux-3.2.1_o/drivers/usb/gadget/fsl_udc_core.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/gadget/fsl_udc_core.c	2014-05-15 13:25:15.018870891 +0900
- ***************
- *** 1934,1940 ****
-   	if (!udc_controller)
-   		return -ENODEV;
-   
- ! 	if (!driver || driver->speed < USB_SPEED_FULL
-   			|| !bind || !driver->disconnect || !driver->setup)
-   		return -EINVAL;
-   
- --- 1934,1940 ----
-   	if (!udc_controller)
-   		return -ENODEV;
-   
- ! 	if (!driver || driver->max_speed < USB_SPEED_FULL
-   			|| !bind || !driver->disconnect || !driver->setup)
-   		return -EINVAL;
-   
- ***************
- *** 2525,2531 ****
-   
-   	/* Setup gadget structure */
-   	udc_controller->gadget.ops = &fsl_gadget_ops;
- ! 	udc_controller->gadget.is_dualspeed = 1;
-   	udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
-   	INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
-   	udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
- --- 2525,2531 ----
-   
-   	/* Setup gadget structure */
-   	udc_controller->gadget.ops = &fsl_gadget_ops;
- ! 	udc_controller->gadget.max_speed = USB_SPEED_HIGH;
-   	udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
-   	INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
-   	udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
- diff -crN linux-3.2.1_o/drivers/usb/gadget/f_subset.c linux-3.2.1/drivers/usb/gadget/f_subset.c
- *** linux-3.2.1_o/drivers/usb/gadget/f_subset.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/gadget/f_subset.c	2014-05-15 13:25:15.018870891 +0900
- ***************
- *** 307,312 ****
- --- 307,313 ----
-   	status = -ENODEV;
-   
-   	/* allocate instance-specific endpoints */
- + 	usb_ep_autoconfig_reset(cdev->gadget);
-   	ep = usb_ep_autoconfig(cdev->gadget, &fs_subset_in_desc);
-   	if (!ep)
-   		goto fail;
- diff -crN linux-3.2.1_o/drivers/usb/gadget/fusb300_udc.c linux-3.2.1/drivers/usb/gadget/fusb300_udc.c
- *** linux-3.2.1_o/drivers/usb/gadget/fusb300_udc.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/gadget/fusb300_udc.c	2014-05-15 13:25:15.018870891 +0900
- ***************
- *** 1317,1323 ****
-   	int retval;
-   
-   	if (!driver
- ! 			|| driver->speed < USB_SPEED_FULL
-   			|| !bind
-   			|| !driver->setup)
-   		return -EINVAL;
- --- 1317,1323 ----
-   	int retval;
-   
-   	if (!driver
- ! 			|| driver->max_speed < USB_SPEED_FULL
-   			|| !bind
-   			|| !driver->setup)
-   		return -EINVAL;
- ***************
- *** 1463,1469 ****
-   
-   	dev_set_name(&fusb300->gadget.dev, "gadget");
-   
- ! 	fusb300->gadget.is_dualspeed = 1;
-   	fusb300->gadget.dev.parent = &pdev->dev;
-   	fusb300->gadget.dev.dma_mask = pdev->dev.dma_mask;
-   	fusb300->gadget.dev.release = pdev->dev.release;
- --- 1463,1469 ----
-   
-   	dev_set_name(&fusb300->gadget.dev, "gadget");
-   
- ! 	fusb300->gadget.max_speed = USB_SPEED_HIGH;
-   	fusb300->gadget.dev.parent = &pdev->dev;
-   	fusb300->gadget.dev.dma_mask = pdev->dev.dma_mask;
-   	fusb300->gadget.dev.release = pdev->dev.release;
- diff -crN linux-3.2.1_o/drivers/usb/gadget/goku_udc.c linux-3.2.1/drivers/usb/gadget/goku_udc.c
- *** linux-3.2.1_o/drivers/usb/gadget/goku_udc.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/gadget/goku_udc.c	2014-05-15 13:25:15.022807398 +0900
- ***************
- *** 1357,1363 ****
-   	int			retval;
-   
-   	if (!driver
- ! 			|| driver->speed < USB_SPEED_FULL
-   			|| !bind
-   			|| !driver->disconnect
-   			|| !driver->setup)
- --- 1357,1363 ----
-   	int			retval;
-   
-   	if (!driver
- ! 			|| driver->max_speed < USB_SPEED_FULL
-   			|| !bind
-   			|| !driver->disconnect
-   			|| !driver->setup)
- ***************
- *** 1796,1801 ****
- --- 1796,1802 ----
-   	spin_lock_init(&dev->lock);
-   	dev->pdev = pdev;
-   	dev->gadget.ops = &goku_ops;
- + 	dev->gadget.max_speed = USB_SPEED_FULL;
-   
-   	/* the "gadget" abstracts/virtualizes the controller */
-   	dev_set_name(&dev->gadget.dev, "gadget");
- diff -crN linux-3.2.1_o/drivers/usb/gadget/imx_udc.c linux-3.2.1/drivers/usb/gadget/imx_udc.c
- *** linux-3.2.1_o/drivers/usb/gadget/imx_udc.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/gadget/imx_udc.c	2014-05-15 13:25:15.022807398 +0900
- ***************
- *** 1336,1342 ****
-   	int retval;
-   
-   	if (!driver
- ! 		|| driver->speed < USB_SPEED_FULL
-   		|| !bind
-   		|| !driver->disconnect
-   		|| !driver->setup)
- --- 1336,1342 ----
-   	int retval;
-   
-   	if (!driver
- ! 		|| driver->max_speed < USB_SPEED_FULL
-   		|| !bind
-   		|| !driver->disconnect
-   		|| !driver->setup)
- diff -crN linux-3.2.1_o/drivers/usb/gadget/inode.c linux-3.2.1/drivers/usb/gadget/inode.c
- *** linux-3.2.1_o/drivers/usb/gadget/inode.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/gadget/inode.c	2014-05-15 13:25:15.022807398 +0900
- ***************
- *** 1766,1774 ****
-   
-   static struct usb_gadget_driver gadgetfs_driver = {
-   #ifdef	CONFIG_USB_GADGET_DUALSPEED
- ! 	.speed		= USB_SPEED_HIGH,
-   #else
- ! 	.speed		= USB_SPEED_FULL,
-   #endif
-   	.function	= (char *) driver_desc,
-   	.unbind		= gadgetfs_unbind,
- --- 1766,1774 ----
-   
-   static struct usb_gadget_driver gadgetfs_driver = {
-   #ifdef	CONFIG_USB_GADGET_DUALSPEED
- ! 	.max_speed	= USB_SPEED_HIGH,
-   #else
- ! 	.max_speed	= USB_SPEED_FULL,
-   #endif
-   	.function	= (char *) driver_desc,
-   	.unbind		= gadgetfs_unbind,
- ***************
- *** 1792,1798 ****
-   }
-   
-   static struct usb_gadget_driver probe_driver = {
- ! 	.speed		= USB_SPEED_HIGH,
-   	.unbind		= gadgetfs_nop,
-   	.setup		= (void *)gadgetfs_nop,
-   	.disconnect	= gadgetfs_nop,
- --- 1792,1798 ----
-   }
-   
-   static struct usb_gadget_driver probe_driver = {
- ! 	.max_speed	= USB_SPEED_HIGH,
-   	.unbind		= gadgetfs_nop,
-   	.setup		= (void *)gadgetfs_nop,
-   	.disconnect	= gadgetfs_nop,
- diff -crN linux-3.2.1_o/drivers/usb/gadget/langwell_udc.c linux-3.2.1/drivers/usb/gadget/langwell_udc.c
- *** linux-3.2.1_o/drivers/usb/gadget/langwell_udc.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/gadget/langwell_udc.c	2014-05-15 13:25:15.022807398 +0900
- ***************
- *** 3267,3273 ****
-   	dev->gadget.ep0 = &dev->ep[0].ep;	/* gadget ep0 */
-   	INIT_LIST_HEAD(&dev->gadget.ep_list);	/* ep_list */
-   	dev->gadget.speed = USB_SPEED_UNKNOWN;	/* speed */
- ! 	dev->gadget.is_dualspeed = 1;		/* support dual speed */
-   #ifdef	OTG_TRANSCEIVER
-   	dev->gadget.is_otg = 1;			/* support otg mode */
-   #endif
- --- 3267,3273 ----
-   	dev->gadget.ep0 = &dev->ep[0].ep;	/* gadget ep0 */
-   	INIT_LIST_HEAD(&dev->gadget.ep_list);	/* ep_list */
-   	dev->gadget.speed = USB_SPEED_UNKNOWN;	/* speed */
- ! 	dev->gadget.max_speed = USB_SPEED_HIGH;	/* support dual speed */
-   #ifdef	OTG_TRANSCEIVER
-   	dev->gadget.is_otg = 1;			/* support otg mode */
-   #endif
- diff -crN linux-3.2.1_o/drivers/usb/gadget/m66592-udc.c linux-3.2.1/drivers/usb/gadget/m66592-udc.c
- *** linux-3.2.1_o/drivers/usb/gadget/m66592-udc.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/gadget/m66592-udc.c	2014-05-15 13:25:15.027061895 +0900
- ***************
- *** 1472,1478 ****
-   	int retval;
-   
-   	if (!driver
- ! 			|| driver->speed < USB_SPEED_HIGH
-   			|| !bind
-   			|| !driver->setup)
-   		return -EINVAL;
- --- 1472,1478 ----
-   	int retval;
-   
-   	if (!driver
- ! 			|| driver->max_speed < USB_SPEED_HIGH
-   			|| !bind
-   			|| !driver->setup)
-   		return -EINVAL;
- ***************
- *** 1653,1659 ****
-   	m66592->gadget.ops = &m66592_gadget_ops;
-   	device_initialize(&m66592->gadget.dev);
-   	dev_set_name(&m66592->gadget.dev, "gadget");
- ! 	m66592->gadget.is_dualspeed = 1;
-   	m66592->gadget.dev.parent = &pdev->dev;
-   	m66592->gadget.dev.dma_mask = pdev->dev.dma_mask;
-   	m66592->gadget.dev.release = pdev->dev.release;
- --- 1653,1659 ----
-   	m66592->gadget.ops = &m66592_gadget_ops;
-   	device_initialize(&m66592->gadget.dev);
-   	dev_set_name(&m66592->gadget.dev, "gadget");
- ! 	m66592->gadget.max_speed = USB_SPEED_HIGH;
-   	m66592->gadget.dev.parent = &pdev->dev;
-   	m66592->gadget.dev.dma_mask = pdev->dev.dma_mask;
-   	m66592->gadget.dev.release = pdev->dev.release;
- diff -crN linux-3.2.1_o/drivers/usb/gadget/mv_udc_core.c linux-3.2.1/drivers/usb/gadget/mv_udc_core.c
- *** linux-3.2.1_o/drivers/usb/gadget/mv_udc_core.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/gadget/mv_udc_core.c	2014-05-15 13:25:15.027061895 +0900
- ***************
- *** 2312,2318 ****
-   	udc->gadget.ep0 = &udc->eps[0].ep;	/* gadget ep0 */
-   	INIT_LIST_HEAD(&udc->gadget.ep_list);	/* ep_list */
-   	udc->gadget.speed = USB_SPEED_UNKNOWN;	/* speed */
- ! 	udc->gadget.is_dualspeed = 1;		/* support dual speed */
-   
-   	/* the "gadget" abstracts/virtualizes the controller */
-   	dev_set_name(&udc->gadget.dev, "gadget");
- --- 2312,2318 ----
-   	udc->gadget.ep0 = &udc->eps[0].ep;	/* gadget ep0 */
-   	INIT_LIST_HEAD(&udc->gadget.ep_list);	/* ep_list */
-   	udc->gadget.speed = USB_SPEED_UNKNOWN;	/* speed */
- ! 	udc->gadget.max_speed = USB_SPEED_HIGH;	/* support dual speed */
-   
-   	/* the "gadget" abstracts/virtualizes the controller */
-   	dev_set_name(&udc->gadget.dev, "gadget");
- diff -crN linux-3.2.1_o/drivers/usb/gadget/net2272.c linux-3.2.1/drivers/usb/gadget/net2272.c
- *** linux-3.2.1_o/drivers/usb/gadget/net2272.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/gadget/net2272.c	2014-05-15 13:25:15.027061895 +0900
- ***************
- *** 1459,1465 ****
-   	unsigned i;
-   
-   	if (!driver || !driver->unbind || !driver->setup ||
- ! 	    driver->speed != USB_SPEED_HIGH)
-   		return -EINVAL;
-   
-   	dev = container_of(_gadget, struct net2272, gadget);
- --- 1459,1465 ----
-   	unsigned i;
-   
-   	if (!driver || !driver->unbind || !driver->setup ||
- ! 	    driver->max_speed != USB_SPEED_HIGH)
-   		return -EINVAL;
-   
-   	dev = container_of(_gadget, struct net2272, gadget);
- ***************
- *** 2235,2241 ****
-   	ret->irq = irq;
-   	ret->dev = dev;
-   	ret->gadget.ops = &net2272_ops;
- ! 	ret->gadget.is_dualspeed = 1;
-   
-   	/* the "gadget" abstracts/virtualizes the controller */
-   	dev_set_name(&ret->gadget.dev, "gadget");
- --- 2235,2241 ----
-   	ret->irq = irq;
-   	ret->dev = dev;
-   	ret->gadget.ops = &net2272_ops;
- ! 	ret->gadget.max_speed = USB_SPEED_HIGH;
-   
-   	/* the "gadget" abstracts/virtualizes the controller */
-   	dev_set_name(&ret->gadget.dev, "gadget");
- diff -crN linux-3.2.1_o/drivers/usb/gadget/net2280.c linux-3.2.1/drivers/usb/gadget/net2280.c
- *** linux-3.2.1_o/drivers/usb/gadget/net2280.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/gadget/net2280.c	2014-05-15 13:25:15.030720256 +0900
- ***************
- *** 1881,1887 ****
-   	 * (dev->usb->xcvrdiag & FORCE_FULL_SPEED_MODE)
-   	 * "must not be used in normal operation"
-   	 */
- ! 	if (!driver || driver->speed < USB_SPEED_HIGH
-   			|| !driver->setup)
-   		return -EINVAL;
-   
- --- 1881,1887 ----
-   	 * (dev->usb->xcvrdiag & FORCE_FULL_SPEED_MODE)
-   	 * "must not be used in normal operation"
-   	 */
- ! 	if (!driver || driver->max_speed < USB_SPEED_HIGH
-   			|| !driver->setup)
-   		return -EINVAL;
-   
- ***************
- *** 2698,2704 ****
-   	spin_lock_init (&dev->lock);
-   	dev->pdev = pdev;
-   	dev->gadget.ops = &net2280_ops;
- ! 	dev->gadget.is_dualspeed = 1;
-   
-   	/* the "gadget" abstracts/virtualizes the controller */
-   	dev_set_name(&dev->gadget.dev, "gadget");
- --- 2698,2704 ----
-   	spin_lock_init (&dev->lock);
-   	dev->pdev = pdev;
-   	dev->gadget.ops = &net2280_ops;
- ! 	dev->gadget.max_speed = USB_SPEED_HIGH;
-   
-   	/* the "gadget" abstracts/virtualizes the controller */
-   	dev_set_name(&dev->gadget.dev, "gadget");
- diff -crN linux-3.2.1_o/drivers/usb/gadget/omap_udc.c linux-3.2.1/drivers/usb/gadget/omap_udc.c
- *** linux-3.2.1_o/drivers/usb/gadget/omap_udc.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/gadget/omap_udc.c	2014-05-15 13:25:15.030720256 +0900
- ***************
- *** 2110,2116 ****
-   		return -ENODEV;
-   	if (!driver
-   			// FIXME if otg, check:  driver->is_otg
- ! 			|| driver->speed < USB_SPEED_FULL
-   			|| !bind || !driver->setup)
-   		return -EINVAL;
-   
- --- 2110,2116 ----
-   		return -ENODEV;
-   	if (!driver
-   			// FIXME if otg, check:  driver->is_otg
- ! 			|| driver->max_speed < USB_SPEED_FULL
-   			|| !bind || !driver->setup)
-   		return -EINVAL;
-   
- ***************
- *** 2676,2681 ****
- --- 2676,2682 ----
-   	INIT_LIST_HEAD(&udc->gadget.ep_list);
-   	INIT_LIST_HEAD(&udc->iso);
-   	udc->gadget.speed = USB_SPEED_UNKNOWN;
- + 	udc->gadget.max_speed = USB_SPEED_FULL;
-   	udc->gadget.name = driver_name;
-   
-   	device_initialize(&udc->gadget.dev);
- ***************
- *** 2794,2799 ****
- --- 2795,2801 ----
-   	struct omap_usb_config	*config = pdev->dev.platform_data;
-   	struct clk		*dc_clk;
-   	struct clk		*hhc_clk;
- + 	u8			pdev_id;
-   
-   	/* NOTE:  "knows" the order of the resources! */
-   	if (!request_mem_region(pdev->resource[0].start,
- ***************
- *** 2862,2868 ****
-   		 * use it.  Except for OTG, we don't _need_ to talk to one;
-   		 * but not having one probably means no VBUS detection.
-   		 */
- ! 		xceiv = otg_get_transceiver();
-   		if (xceiv)
-   			type = xceiv->label;
-   		else if (config->otg) {
- --- 2864,2871 ----
-   		 * use it.  Except for OTG, we don't _need_ to talk to one;
-   		 * but not having one probably means no VBUS detection.
-   		 */
- ! 		pdev_id = (pdev->id >= 0) ? pdev->id : 0;
- ! 		xceiv = otg_get_transceiver(pdev_id);
-   		if (xceiv)
-   			type = xceiv->label;
-   		else if (config->otg) {
- diff -crN linux-3.2.1_o/drivers/usb/gadget/pch_udc.c linux-3.2.1/drivers/usb/gadget/pch_udc.c
- *** linux-3.2.1_o/drivers/usb/gadget/pch_udc.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/gadget/pch_udc.c	2014-05-15 13:25:15.034716553 +0900
- ***************
- *** 2693,2699 ****
-   	struct pch_udc_dev	*dev = pch_udc;
-   	int			retval;
-   
- ! 	if (!driver || (driver->speed == USB_SPEED_UNKNOWN) || !bind ||
-   	    !driver->setup || !driver->unbind || !driver->disconnect) {
-   		dev_err(&dev->pdev->dev,
-   			"%s: invalid driver parameter\n", __func__);
- --- 2693,2699 ----
-   	struct pch_udc_dev	*dev = pch_udc;
-   	int			retval;
-   
- ! 	if (!driver || (driver->max_speed == USB_SPEED_UNKNOWN) || !bind ||
-   	    !driver->setup || !driver->unbind || !driver->disconnect) {
-   		dev_err(&dev->pdev->dev,
-   			"%s: invalid driver parameter\n", __func__);
- ***************
- *** 2941,2947 ****
-   	dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
-   	dev->gadget.dev.release = gadget_release;
-   	dev->gadget.name = KBUILD_MODNAME;
- ! 	dev->gadget.is_dualspeed = 1;
-   
-   	retval = device_register(&dev->gadget.dev);
-   	if (retval)
- --- 2941,2947 ----
-   	dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
-   	dev->gadget.dev.release = gadget_release;
-   	dev->gadget.name = KBUILD_MODNAME;
- ! 	dev->gadget.max_speed = USB_SPEED_HIGH;
-   
-   	retval = device_register(&dev->gadget.dev);
-   	if (retval)
- diff -crN linux-3.2.1_o/drivers/usb/gadget/printer.c linux-3.2.1/drivers/usb/gadget/printer.c
- *** linux-3.2.1_o/drivers/usb/gadget/printer.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/gadget/printer.c	2014-05-15 13:25:15.034716553 +0900
- ***************
- *** 1141,1147 ****
-   				break;
-   #ifdef CONFIG_USB_GADGET_DUALSPEED
-   			case USB_DT_DEVICE_QUALIFIER:
- ! 				if (!gadget->is_dualspeed)
-   					break;
-   				/*
-   				 * assumes ep0 uses the same value for both
- --- 1141,1147 ----
-   				break;
-   #ifdef CONFIG_USB_GADGET_DUALSPEED
-   			case USB_DT_DEVICE_QUALIFIER:
- ! 				if (!gadget_is_dualspeed(gadget))
-   					break;
-   				/*
-   				 * assumes ep0 uses the same value for both
- ***************
- *** 1155,1161 ****
-   				break;
-   
-   			case USB_DT_OTHER_SPEED_CONFIG:
- ! 				if (!gadget->is_dualspeed)
-   					break;
-   				/* FALLTHROUGH */
-   #endif /* CONFIG_USB_GADGET_DUALSPEED */
- --- 1155,1161 ----
-   				break;
-   
-   			case USB_DT_OTHER_SPEED_CONFIG:
- ! 				if (!gadget_is_dualspeed(gadget))
-   					break;
-   				/* FALLTHROUGH */
-   #endif /* CONFIG_USB_GADGET_DUALSPEED */
- ***************
- *** 1535,1541 ****
-   /*-------------------------------------------------------------------------*/
-   
-   static struct usb_gadget_driver printer_driver = {
- ! 	.speed		= DEVSPEED,
-   
-   	.function	= (char *) driver_desc,
-   	.unbind		= printer_unbind,
- --- 1535,1541 ----
-   /*-------------------------------------------------------------------------*/
-   
-   static struct usb_gadget_driver printer_driver = {
- ! 	.max_speed	= DEVSPEED,
-   
-   	.function	= (char *) driver_desc,
-   	.unbind		= printer_unbind,
- diff -crN linux-3.2.1_o/drivers/usb/gadget/pxa25x_udc.c linux-3.2.1/drivers/usb/gadget/pxa25x_udc.c
- *** linux-3.2.1_o/drivers/usb/gadget/pxa25x_udc.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/gadget/pxa25x_udc.c	2014-05-15 13:25:15.034716553 +0900
- ***************
- *** 1264,1270 ****
-   	int			retval;
-   
-   	if (!driver
- ! 			|| driver->speed < USB_SPEED_FULL
-   			|| !bind
-   			|| !driver->disconnect
-   			|| !driver->setup)
- --- 1264,1270 ----
-   	int			retval;
-   
-   	if (!driver
- ! 			|| driver->max_speed < USB_SPEED_FULL
-   			|| !bind
-   			|| !driver->disconnect
-   			|| !driver->setup)
- diff -crN linux-3.2.1_o/drivers/usb/gadget/pxa27x_udc.c linux-3.2.1/drivers/usb/gadget/pxa27x_udc.c
- *** linux-3.2.1_o/drivers/usb/gadget/pxa27x_udc.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/gadget/pxa27x_udc.c	2014-05-15 13:25:15.038572249 +0900
- ***************
- *** 1807,1813 ****
-   	struct pxa_udc *udc = the_controller;
-   	int retval;
-   
- ! 	if (!driver || driver->speed < USB_SPEED_FULL || !bind
-   			|| !driver->disconnect || !driver->setup)
-   		return -EINVAL;
-   	if (!udc)
- --- 1807,1813 ----
-   	struct pxa_udc *udc = the_controller;
-   	int retval;
-   
- ! 	if (!driver || driver->max_speed < USB_SPEED_FULL || !bind
-   			|| !driver->disconnect || !driver->setup)
-   		return -EINVAL;
-   	if (!udc)
- diff -crN linux-3.2.1_o/drivers/usb/gadget/r8a66597-udc.c linux-3.2.1/drivers/usb/gadget/r8a66597-udc.c
- *** linux-3.2.1_o/drivers/usb/gadget/r8a66597-udc.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/gadget/r8a66597-udc.c	2014-05-15 13:25:15.038572249 +0900
- ***************
- *** 1746,1752 ****
-   	struct r8a66597 *r8a66597 = gadget_to_r8a66597(gadget);
-   
-   	if (!driver
- ! 			|| driver->speed < USB_SPEED_HIGH
-   			|| !driver->setup)
-   		return -EINVAL;
-   	if (!r8a66597)
- --- 1746,1752 ----
-   	struct r8a66597 *r8a66597 = gadget_to_r8a66597(gadget);
-   
-   	if (!driver
- ! 			|| driver->max_speed < USB_SPEED_HIGH
-   			|| !driver->setup)
-   		return -EINVAL;
-   	if (!r8a66597)
- ***************
- *** 1911,1917 ****
-   
-   	r8a66597->gadget.ops = &r8a66597_gadget_ops;
-   	dev_set_name(&r8a66597->gadget.dev, "gadget");
- ! 	r8a66597->gadget.is_dualspeed = 1;
-   	r8a66597->gadget.dev.parent = &pdev->dev;
-   	r8a66597->gadget.dev.dma_mask = pdev->dev.dma_mask;
-   	r8a66597->gadget.dev.release = pdev->dev.release;
- --- 1911,1917 ----
-   
-   	r8a66597->gadget.ops = &r8a66597_gadget_ops;
-   	dev_set_name(&r8a66597->gadget.dev, "gadget");
- ! 	r8a66597->gadget.max_speed = USB_SPEED_HIGH;
-   	r8a66597->gadget.dev.parent = &pdev->dev;
-   	r8a66597->gadget.dev.dma_mask = pdev->dev.dma_mask;
-   	r8a66597->gadget.dev.release = pdev->dev.release;
- diff -crN linux-3.2.1_o/drivers/usb/gadget/rndis.c linux-3.2.1/drivers/usb/gadget/rndis.c
- *** linux-3.2.1_o/drivers/usb/gadget/rndis.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/gadget/rndis.c	2014-05-15 13:25:15.038572249 +0900
- ***************
- *** 314,320 ****
-   	/* mandatory */
-   	case OID_GEN_CURRENT_PACKET_FILTER:
-   		pr_debug("%s: OID_GEN_CURRENT_PACKET_FILTER\n", __func__);
- ! 		*outbuf = cpu_to_le32(*rndis_per_dev_params[configNr].filter);
-   		retval = 0;
-   		break;
-   
- --- 314,321 ----
-   	/* mandatory */
-   	case OID_GEN_CURRENT_PACKET_FILTER:
-   		pr_debug("%s: OID_GEN_CURRENT_PACKET_FILTER\n", __func__);
- ! 		*outbuf =
- ! 		cpu_to_le32(*(u16 *)rndis_per_dev_params[configNr].filter);
-   		retval = 0;
-   		break;
-   
- ***************
- *** 336,342 ****
-   
-   	case OID_GEN_PHYSICAL_MEDIUM:
-   		pr_debug("%s: OID_GEN_PHYSICAL_MEDIUM\n", __func__);
- ! 		*outbuf = cpu_to_le32(0);
-   		retval = 0;
-   		break;
-   
- --- 337,343 ----
-   
-   	case OID_GEN_PHYSICAL_MEDIUM:
-   		pr_debug("%s: OID_GEN_PHYSICAL_MEDIUM\n", __func__);
- ! 		*outbuf = __constant_cpu_to_le32(2);
-   		retval = 0;
-   		break;
-   
- ***************
- *** 413,419 ****
-   		if (rndis_per_dev_params[configNr].dev) {
-   			length = ETH_ALEN;
-   			memcpy(outbuf,
- ! 				rndis_per_dev_params[configNr].host_mac,
-   				length);
-   			retval = 0;
-   		}
- --- 414,420 ----
-   		if (rndis_per_dev_params[configNr].dev) {
-   			length = ETH_ALEN;
-   			memcpy(outbuf,
- ! 				rndis_per_dev_params[configNr].perm_mac,
-   				length);
-   			retval = 0;
-   		}
- ***************
- *** 443,449 ****
-   	case OID_802_3_MAXIMUM_LIST_SIZE:
-   		pr_debug("%s: OID_802_3_MAXIMUM_LIST_SIZE\n", __func__);
-   		/* Multicast base address only */
- ! 		*outbuf = cpu_to_le32(1);
-   		retval = 0;
-   		break;
-   
- --- 444,450 ----
-   	case OID_802_3_MAXIMUM_LIST_SIZE:
-   		pr_debug("%s: OID_802_3_MAXIMUM_LIST_SIZE\n", __func__);
-   		/* Multicast base address only */
- ! 		*outbuf = __constant_cpu_to_le32(32);
-   		retval = 0;
-   		break;
-   
- ***************
- *** 549,554 ****
- --- 550,559 ----
-   	case OID_802_3_MULTICAST_LIST:
-   		/* I think we can ignore this */
-   		pr_debug("%s: OID_802_3_MULTICAST_LIST\n", __func__);
- + 		memset(rndis_per_dev_params[configNr].mcast_addr, 0,
- + 			RNDIS_MAX_MULTICAST_SIZE * 6);
- + 		memcpy(rndis_per_dev_params[configNr].mcast_addr,
- + 			buf, buf_len);
-   		retval = 0;
-   		break;
-   
- ***************
- *** 578,583 ****
- --- 583,591 ----
-   		return -ENOMEM;
-   	resp = (rndis_init_cmplt_type *)r->buf;
-   
- + 	if (!resp)
- + 		return -ENOMEM;
- + 
-   	resp->MessageType = cpu_to_le32(REMOTE_NDIS_INITIALIZE_CMPLT);
-   	resp->MessageLength = cpu_to_le32(52);
-   	resp->RequestID = buf->RequestID; /* Still LE in msg buffer */
- ***************
- *** 788,794 ****
-   
-   void rndis_set_host_mac(int configNr, const u8 *addr)
-   {
- ! 	rndis_per_dev_params[configNr].host_mac = addr;
-   }
-   
-   /*
- --- 796,803 ----
-   
-   void rndis_set_host_mac(int configNr, const u8 *addr)
-   {
- ! 	rndis_per_dev_params[configNr].host_mac = (u8 *)addr;
- ! 	memcpy((void *)rndis_per_dev_params[configNr].perm_mac, addr, 6);
-   }
-   
-   /*
- ***************
- *** 830,835 ****
- --- 839,846 ----
-   			__func__);
-   		params->state = RNDIS_UNINITIALIZED;
-   		if (params->dev) {
- + 			memcpy((void *)rndis_per_dev_params[configNr].host_mac,
- + 			(void *)rndis_per_dev_params[configNr].perm_mac, 6);
-   			netif_carrier_off(params->dev);
-   			netif_stop_queue(params->dev);
-   		}
- diff -crN linux-3.2.1_o/drivers/usb/gadget/rndis.h linux-3.2.1/drivers/usb/gadget/rndis.h
- *** linux-3.2.1_o/drivers/usb/gadget/rndis.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/gadget/rndis.h	2014-05-15 13:25:15.038572249 +0900
- ***************
- *** 18,24 ****
-   #include "ndis.h"
-   
-   #define RNDIS_MAXIMUM_FRAME_SIZE	1518
- ! #define RNDIS_MAX_TOTAL_SIZE		1558
-   
-   /* Remote NDIS Versions */
-   #define RNDIS_MAJOR_VERSION		1
- --- 18,25 ----
-   #include "ndis.h"
-   
-   #define RNDIS_MAXIMUM_FRAME_SIZE	1518
- ! #define RNDIS_MAX_TOTAL_SIZE		1514
- ! #define RNDIS_MAX_MULTICAST_SIZE        32
-   
-   /* Remote NDIS Versions */
-   #define RNDIS_MAJOR_VERSION		1
- ***************
- *** 230,236 ****
-   	u32			speed;
-   	u32			media_state;
-   
- ! 	const u8		*host_mac;
-   	u16			*filter;
-   	struct net_device	*dev;
-   
- --- 231,238 ----
-   	u32			speed;
-   	u32			media_state;
-   
- ! 	u8                      perm_mac[6];
- ! 	u8                      *host_mac;
-   	u16			*filter;
-   	struct net_device	*dev;
-   
- ***************
- *** 239,244 ****
- --- 241,247 ----
-   	void			(*resp_avail)(void *v);
-   	void			*v;
-   	struct list_head	resp_queue;
- + 	u8			mcast_addr[RNDIS_MAX_MULTICAST_SIZE][6];
-   } rndis_params;
-   
-   /* RNDIS Message parser and other useless functions */
- diff -crN linux-3.2.1_o/drivers/usb/gadget/s3c2410_udc.c linux-3.2.1/drivers/usb/gadget/s3c2410_udc.c
- *** linux-3.2.1_o/drivers/usb/gadget/s3c2410_udc.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/gadget/s3c2410_udc.c	2014-05-15 13:25:15.042542123 +0900
- ***************
- *** 1683,1691 ****
-   	if (udc->driver)
-   		return -EBUSY;
-   
- ! 	if (!bind || !driver->setup || driver->speed < USB_SPEED_FULL) {
-   		printk(KERN_ERR "Invalid driver: bind %p setup %p speed %d\n",
- ! 			bind, driver->setup, driver->speed);
-   		return -EINVAL;
-   	}
-   #if defined(MODULE)
- --- 1683,1691 ----
-   	if (udc->driver)
-   		return -EBUSY;
-   
- ! 	if (!bind || !driver->setup || driver->max_speed < USB_SPEED_FULL) {
-   		printk(KERN_ERR "Invalid driver: bind %p setup %p speed %d\n",
- ! 			bind, driver->setup, driver->max_speed);
-   		return -EINVAL;
-   	}
-   #if defined(MODULE)
- diff -crN linux-3.2.1_o/drivers/usb/gadget/s3c-hsotg.c linux-3.2.1/drivers/usb/gadget/s3c-hsotg.c
- *** linux-3.2.1_o/drivers/usb/gadget/s3c-hsotg.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/gadget/s3c-hsotg.c	2014-05-15 13:25:15.042542123 +0900
- ***************
- *** 2586,2592 ****
-   		return -EINVAL;
-   	}
-   
- ! 	if (driver->speed < USB_SPEED_FULL)
-   		dev_err(hsotg->dev, "%s: bad speed\n", __func__);
-   
-   	if (!bind || !driver->setup) {
- --- 2586,2592 ----
-   		return -EINVAL;
-   	}
-   
- ! 	if (driver->max_speed < USB_SPEED_FULL)
-   		dev_err(hsotg->dev, "%s: bad speed\n", __func__);
-   
-   	if (!bind || !driver->setup) {
- ***************
- *** 3362,3368 ****
-   
-   	dev_set_name(&hsotg->gadget.dev, "gadget");
-   
- ! 	hsotg->gadget.is_dualspeed = 1;
-   	hsotg->gadget.ops = &s3c_hsotg_gadget_ops;
-   	hsotg->gadget.name = dev_name(dev);
-   
- --- 3362,3368 ----
-   
-   	dev_set_name(&hsotg->gadget.dev, "gadget");
-   
- ! 	hsotg->gadget.max_speed = USB_SPEED_HIGH;
-   	hsotg->gadget.ops = &s3c_hsotg_gadget_ops;
-   	hsotg->gadget.name = dev_name(dev);
-   
- diff -crN linux-3.2.1_o/drivers/usb/gadget/s3c-hsudc.c linux-3.2.1/drivers/usb/gadget/s3c-hsudc.c
- *** linux-3.2.1_o/drivers/usb/gadget/s3c-hsudc.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/gadget/s3c-hsudc.c	2014-05-15 13:25:15.042542123 +0900
- ***************
- *** 1142,1148 ****
-   	int ret;
-   
-   	if (!driver
- ! 		|| driver->speed < USB_SPEED_FULL
-   		|| !bind
-   		|| !driver->unbind || !driver->disconnect || !driver->setup)
-   		return -EINVAL;
- --- 1142,1148 ----
-   	int ret;
-   
-   	if (!driver
- ! 		|| driver->max_speed < USB_SPEED_FULL
-   		|| !bind
-   		|| !driver->unbind || !driver->disconnect || !driver->setup)
-   		return -EINVAL;
- ***************
- *** 1310,1316 ****
-   	device_initialize(&hsudc->gadget.dev);
-   	dev_set_name(&hsudc->gadget.dev, "gadget");
-   
- ! 	hsudc->gadget.is_dualspeed = 1;
-   	hsudc->gadget.ops = &s3c_hsudc_gadget_ops;
-   	hsudc->gadget.name = dev_name(dev);
-   	hsudc->gadget.dev.parent = dev;
- --- 1310,1316 ----
-   	device_initialize(&hsudc->gadget.dev);
-   	dev_set_name(&hsudc->gadget.dev, "gadget");
-   
- ! 	hsudc->gadget.max_speed = USB_SPEED_HIGH;
-   	hsudc->gadget.ops = &s3c_hsudc_gadget_ops;
-   	hsudc->gadget.name = dev_name(dev);
-   	hsudc->gadget.dev.parent = dev;
- diff -crN linux-3.2.1_o/drivers/usb/gadget/udc-core.c linux-3.2.1/drivers/usb/gadget/udc-core.c
- *** linux-3.2.1_o/drivers/usb/gadget/udc-core.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/gadget/udc-core.c	2014-05-15 13:25:15.042542123 +0900
- ***************
- *** 211,219 ****
-   
-   	if (udc_is_newstyle(udc)) {
-   		udc->driver->disconnect(udc->gadget);
-   		udc->driver->unbind(udc->gadget);
-   		usb_gadget_udc_stop(udc->gadget, udc->driver);
- - 		usb_gadget_disconnect(udc->gadget);
-   	} else {
-   		usb_gadget_stop(udc->gadget, udc->driver);
-   	}
- --- 211,219 ----
-   
-   	if (udc_is_newstyle(udc)) {
-   		udc->driver->disconnect(udc->gadget);
- + 		usb_gadget_disconnect(udc->gadget);
-   		udc->driver->unbind(udc->gadget);
-   		usb_gadget_udc_stop(udc->gadget, udc->driver);
-   	} else {
-   		usb_gadget_stop(udc->gadget, udc->driver);
-   	}
- ***************
- *** 359,367 ****
- --- 359,371 ----
-   	struct usb_udc		*udc = container_of(dev, struct usb_udc, dev);
-   
-   	if (sysfs_streq(buf, "connect")) {
- + 		if (udc_is_newstyle(udc))
- + 			usb_gadget_udc_start(udc->gadget, udc->driver);
-   		usb_gadget_connect(udc->gadget);
-   	} else if (sysfs_streq(buf, "disconnect")) {
-   		usb_gadget_disconnect(udc->gadget);
- + 		if (udc_is_newstyle(udc))
- + 			usb_gadget_udc_stop(udc->gadget, udc->driver);
-   	} else {
-   		dev_err(dev, "unsupported command '%s'\n", buf);
-   		return -EINVAL;
- ***************
- *** 371,384 ****
-   }
-   static DEVICE_ATTR(soft_connect, S_IWUSR, NULL, usb_udc_softconn_store);
-   
- ! static ssize_t usb_udc_speed_show(struct device *dev,
-   		struct device_attribute *attr, char *buf)
-   {
-   	struct usb_udc		*udc = container_of(dev, struct usb_udc, dev);
- ! 	return snprintf(buf, PAGE_SIZE, "%s\n",
- ! 			usb_speed_string(udc->gadget->speed));
-   }
- ! static DEVICE_ATTR(speed, S_IRUGO, usb_udc_speed_show, NULL);
-   
-   #define USB_UDC_ATTR(name)					\
-   ssize_t usb_udc_##name##_show(struct device *dev,		\
- --- 375,402 ----
-   }
-   static DEVICE_ATTR(soft_connect, S_IWUSR, NULL, usb_udc_softconn_store);
-   
- ! #define USB_UDC_SPEED_ATTR(name, param)					\
- ! ssize_t usb_udc_##param##_show(struct device *dev,			\
- ! 		struct device_attribute *attr, char *buf)		\
- ! {									\
- ! 	struct usb_udc *udc = container_of(dev, struct usb_udc, dev);	\
- ! 	return snprintf(buf, PAGE_SIZE, "%s\n",				\
- ! 			usb_speed_string(udc->gadget->param));		\
- ! }									\
- ! static DEVICE_ATTR(name, S_IRUSR, usb_udc_##param##_show, NULL)
- ! 
- ! static USB_UDC_SPEED_ATTR(current_speed, speed);
- ! static USB_UDC_SPEED_ATTR(maximum_speed, max_speed);
- ! 
- ! /* TODO: Scheduled for removal in 3.8. */
- ! static ssize_t usb_udc_is_dualspeed_show(struct device *dev,
-   		struct device_attribute *attr, char *buf)
-   {
-   	struct usb_udc		*udc = container_of(dev, struct usb_udc, dev);
- ! 	return snprintf(buf, PAGE_SIZE, "%d\n",
- ! 			gadget_is_dualspeed(udc->gadget));
-   }
- ! static DEVICE_ATTR(is_dualspeed, S_IRUSR, usb_udc_is_dualspeed_show, NULL);
-   
-   #define USB_UDC_ATTR(name)					\
-   ssize_t usb_udc_##name##_show(struct device *dev,		\
- ***************
- *** 391,397 ****
-   }								\
-   static DEVICE_ATTR(name, S_IRUGO, usb_udc_##name##_show, NULL)
-   
- - static USB_UDC_ATTR(is_dualspeed);
-   static USB_UDC_ATTR(is_otg);
-   static USB_UDC_ATTR(is_a_peripheral);
-   static USB_UDC_ATTR(b_hnp_enable);
- --- 409,414 ----
- ***************
- *** 401,407 ****
-   static struct attribute *usb_udc_attrs[] = {
-   	&dev_attr_srp.attr,
-   	&dev_attr_soft_connect.attr,
- ! 	&dev_attr_speed.attr,
-   
-   	&dev_attr_is_dualspeed.attr,
-   	&dev_attr_is_otg.attr,
- --- 418,425 ----
-   static struct attribute *usb_udc_attrs[] = {
-   	&dev_attr_srp.attr,
-   	&dev_attr_soft_connect.attr,
- ! 	&dev_attr_current_speed.attr,
- ! 	&dev_attr_maximum_speed.attr,
-   
-   	&dev_attr_is_dualspeed.attr,
-   	&dev_attr_is_otg.attr,
- diff -crN linux-3.2.1_o/drivers/usb/host/ehci-omap.c linux-3.2.1/drivers/usb/host/ehci-omap.c
- *** linux-3.2.1_o/drivers/usb/host/ehci-omap.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/host/ehci-omap.c	2014-05-15 13:25:15.046591952 +0900
- ***************
- *** 41,46 ****
- --- 41,47 ----
-   #include <linux/usb/ulpi.h>
-   #include <plat/usb.h>
-   #include <linux/regulator/consumer.h>
- + #include <linux/pm_runtime.h>
-   
-   /* EHCI Register Set */
-   #define EHCI_INSNREG04					(0xA0)
- ***************
- *** 190,200 ****
-   		}
-   	}
-   
- ! 	ret = omap_usbhs_enable(dev);
- ! 	if (ret) {
- ! 		dev_err(dev, "failed to start usbhs with err %d\n", ret);
- ! 		goto err_enable;
- ! 	}
-   
-   	/*
-   	 * An undocumented "feature" in the OMAP3 EHCI controller,
- --- 191,198 ----
-   		}
-   	}
-   
- ! 	pm_runtime_enable(dev);
- ! 	pm_runtime_get_sync(dev);
-   
-   	/*
-   	 * An undocumented "feature" in the OMAP3 EHCI controller,
- ***************
- *** 240,250 ****
-   	return 0;
-   
-   err_add_hcd:
- - 	omap_usbhs_disable(dev);
- - 
- - err_enable:
-   	disable_put_regulator(pdata);
- ! 	usb_put_hcd(hcd);
-   
-   err_io:
-   	iounmap(regs);
- --- 238,245 ----
-   	return 0;
-   
-   err_add_hcd:
-   	disable_put_regulator(pdata);
- ! 	pm_runtime_put_sync(dev);
-   
-   err_io:
-   	iounmap(regs);
- ***************
- *** 266,275 ****
-   	struct usb_hcd *hcd	= dev_get_drvdata(dev);
-   
-   	usb_remove_hcd(hcd);
- - 	omap_usbhs_disable(dev);
-   	disable_put_regulator(dev->platform_data);
-   	iounmap(hcd->regs);
-   	usb_put_hcd(hcd);
-   	return 0;
-   }
-   
- --- 261,272 ----
-   	struct usb_hcd *hcd	= dev_get_drvdata(dev);
-   
-   	usb_remove_hcd(hcd);
-   	disable_put_regulator(dev->platform_data);
-   	iounmap(hcd->regs);
-   	usb_put_hcd(hcd);
- + 	pm_runtime_put_sync(dev);
- + 	pm_runtime_disable(dev);
- + 
-   	return 0;
-   }
-   
- diff -crN linux-3.2.1_o/drivers/usb/host/ehci-pxa168.c linux-3.2.1/drivers/usb/host/ehci-pxa168.c
- *** linux-3.2.1_o/drivers/usb/host/ehci-pxa168.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/host/ehci-pxa168.c	2014-05-15 13:25:15.046591952 +0900
- ***************
- *** 299,305 ****
-   	ehci = hcd_to_ehci(hcd);
-   	ehci->caps = hcd->regs + 0x100;
-   	ehci->regs = hcd->regs + 0x100 +
- ! 		HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
-   	ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
-   	hcd->has_tt = 1;
-   	ehci->sbrn = 0x20;
- --- 299,305 ----
-   	ehci = hcd_to_ehci(hcd);
-   	ehci->caps = hcd->regs + 0x100;
-   	ehci->regs = hcd->regs + 0x100 +
- ! 		HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
-   	ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
-   	hcd->has_tt = 1;
-   	ehci->sbrn = 0x20;
- diff -crN linux-3.2.1_o/drivers/usb/host/ehci-q.c linux-3.2.1/drivers/usb/host/ehci-q.c
- *** linux-3.2.1_o/drivers/usb/host/ehci-q.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/host/ehci-q.c	2014-05-15 13:25:15.046591952 +0900
- ***************
- *** 647,653 ****
-   	/*
-   	 * data transfer stage:  buffer setup
-   	 */
- ! 	i = urb->num_mapped_sgs;
-   	if (len > 0 && i > 0) {
-   		sg = urb->sg;
-   		buf = sg_dma_address(sg);
- --- 647,653 ----
-   	/*
-   	 * data transfer stage:  buffer setup
-   	 */
- ! 	i = urb->num_sgs;
-   	if (len > 0 && i > 0) {
-   		sg = urb->sg;
-   		buf = sg_dma_address(sg);
- diff -crN linux-3.2.1_o/drivers/usb/host/ohci-omap3.c linux-3.2.1/drivers/usb/host/ohci-omap3.c
- *** linux-3.2.1_o/drivers/usb/host/ohci-omap3.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/host/ohci-omap3.c	2014-05-15 13:25:15.046591952 +0900
- ***************
- *** 31,36 ****
- --- 31,37 ----
-   
-   #include <linux/platform_device.h>
-   #include <plat/usb.h>
- + #include <linux/pm_runtime.h>
-   
-   /*-------------------------------------------------------------------------*/
-   
- ***************
- *** 134,140 ****
-   	int			irq;
-   
-   	if (usb_disabled())
- ! 		goto err_end;
-   
-   	if (!dev->parent) {
-   		dev_err(dev, "Missing parent device\n");
- --- 135,141 ----
-   	int			irq;
-   
-   	if (usb_disabled())
- ! 		return -ENODEV;
-   
-   	if (!dev->parent) {
-   		dev_err(dev, "Missing parent device\n");
- ***************
- *** 172,182 ****
-   	hcd->rsrc_len = resource_size(res);
-   	hcd->regs =  regs;
-   
- ! 	ret = omap_usbhs_enable(dev);
- ! 	if (ret) {
- ! 		dev_dbg(dev, "failed to start ohci\n");
- ! 		goto err_end;
- ! 	}
-   
-   	ohci_hcd_init(hcd_to_ohci(hcd));
-   
- --- 173,180 ----
-   	hcd->rsrc_len = resource_size(res);
-   	hcd->regs =  regs;
-   
- ! 	pm_runtime_enable(dev);
- ! 	pm_runtime_get_sync(dev);
-   
-   	ohci_hcd_init(hcd_to_ohci(hcd));
-   
- ***************
- *** 189,197 ****
-   	return 0;
-   
-   err_add_hcd:
- ! 	omap_usbhs_disable(dev);
- ! 
- ! err_end:
-   	usb_put_hcd(hcd);
-   
-   err_io:
- --- 187,193 ----
-   	return 0;
-   
-   err_add_hcd:
- ! 	pm_runtime_put_sync(dev);
-   	usb_put_hcd(hcd);
-   
-   err_io:
- ***************
- *** 220,228 ****
-   
-   	iounmap(hcd->regs);
-   	usb_remove_hcd(hcd);
- ! 	omap_usbhs_disable(dev);
-   	usb_put_hcd(hcd);
- - 
-   	return 0;
-   }
-   
- --- 216,224 ----
-   
-   	iounmap(hcd->regs);
-   	usb_remove_hcd(hcd);
- ! 	pm_runtime_put_sync(dev);
- ! 	pm_runtime_disable(dev);
-   	usb_put_hcd(hcd);
-   	return 0;
-   }
-   
- diff -crN linux-3.2.1_o/drivers/usb/host/uhci-q.c linux-3.2.1/drivers/usb/host/uhci-q.c
- *** linux-3.2.1_o/drivers/usb/host/uhci-q.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/host/uhci-q.c	2014-05-15 13:25:15.046591952 +0900
- ***************
- *** 943,949 ****
-   	if (usb_pipein(urb->pipe))
-   		status |= TD_CTRL_SPD;
-   
- ! 	i = urb->num_mapped_sgs;
-   	if (len > 0 && i > 0) {
-   		sg = urb->sg;
-   		data = sg_dma_address(sg);
- --- 943,949 ----
-   	if (usb_pipein(urb->pipe))
-   		status |= TD_CTRL_SPD;
-   
- ! 	i = urb->num_sgs;
-   	if (len > 0 && i > 0) {
-   		sg = urb->sg;
-   		data = sg_dma_address(sg);
- diff -crN linux-3.2.1_o/drivers/usb/host/whci/qset.c linux-3.2.1/drivers/usb/host/whci/qset.c
- *** linux-3.2.1_o/drivers/usb/host/whci/qset.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/host/whci/qset.c	2014-05-15 13:25:15.050976872 +0900
- ***************
- *** 443,449 ****
-   
-   	remaining = urb->transfer_buffer_length;
-   
- ! 	for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) {
-   		dma_addr_t dma_addr;
-   		size_t dma_remaining;
-   		dma_addr_t sp, ep;
- --- 443,449 ----
-   
-   	remaining = urb->transfer_buffer_length;
-   
- ! 	for_each_sg(urb->sg, sg, urb->num_sgs, i) {
-   		dma_addr_t dma_addr;
-   		size_t dma_remaining;
-   		dma_addr_t sp, ep;
- ***************
- *** 561,567 ****
-   
-   	remaining = urb->transfer_buffer_length;
-   
- ! 	for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) {
-   		size_t len;
-   		size_t sg_remaining;
-   		void *orig;
- --- 561,567 ----
-   
-   	remaining = urb->transfer_buffer_length;
-   
- ! 	for_each_sg(urb->sg, sg, urb->num_sgs, i) {
-   		size_t len;
-   		size_t sg_remaining;
-   		void *orig;
- diff -crN linux-3.2.1_o/drivers/usb/host/xhci.c linux-3.2.1/drivers/usb/host/xhci.c
- *** linux-3.2.1_o/drivers/usb/host/xhci.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/host/xhci.c	2014-05-15 13:25:15.050976872 +0900
- ***************
- *** 1620,1626 ****
-   		/* FIXME: can we allocate more resources for the HC? */
-   		break;
-   	case COMP_BW_ERR:
- - 	case COMP_2ND_BW_ERR:
-   		dev_warn(&udev->dev, "Not enough bandwidth "
-   				"for new device state.\n");
-   		ret = -ENOSPC;
- --- 1620,1625 ----
- ***************
- *** 2797,2803 ****
-   		if (ret < 0)
-   			return ret;
-   
- ! 		max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
-   		if (max_streams < (*num_streams - 1)) {
-   			xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
-   					eps[i]->desc.bEndpointAddress,
- --- 2796,2803 ----
-   		if (ret < 0)
-   			return ret;
-   
- ! 		max_streams = USB_SS_MAX_STREAMS(
- ! 				eps[i]->ss_ep_comp.bmAttributes);
-   		if (max_streams < (*num_streams - 1)) {
-   			xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
-   					eps[i]->desc.bEndpointAddress,
- diff -crN linux-3.2.1_o/drivers/usb/host/xhci.h linux-3.2.1/drivers/usb/host/xhci.h
- *** linux-3.2.1_o/drivers/usb/host/xhci.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/host/xhci.h	2014-05-15 13:25:15.050976872 +0900
- ***************
- *** 1033,1038 ****
- --- 1033,1039 ----
-   /* Invalid Stream ID Error */
-   #define COMP_STRID_ERR	34
-   /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */
- + /* FIXME - check for this */
-   #define COMP_2ND_BW_ERR	35
-   /* Split Transaction Error */
-   #define	COMP_SPLIT_ERR	36
- diff -crN linux-3.2.1_o/drivers/usb/host/xhci-ring.c linux-3.2.1/drivers/usb/host/xhci-ring.c
- *** linux-3.2.1_o/drivers/usb/host/xhci-ring.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/host/xhci-ring.c	2014-05-15 13:25:15.055052376 +0900
- ***************
- *** 2561,2567 ****
-   	struct scatterlist *sg;
-   
-   	sg = NULL;
- ! 	num_sgs = urb->num_mapped_sgs;
-   	temp = urb->transfer_buffer_length;
-   
-   	xhci_dbg(xhci, "count sg list trbs: \n");
- --- 2561,2567 ----
-   	struct scatterlist *sg;
-   
-   	sg = NULL;
- ! 	num_sgs = urb->num_sgs;
-   	temp = urb->transfer_buffer_length;
-   
-   	xhci_dbg(xhci, "count sg list trbs: \n");
- ***************
- *** 2745,2751 ****
-   		return -EINVAL;
-   
-   	num_trbs = count_sg_trbs_needed(xhci, urb);
- ! 	num_sgs = urb->num_mapped_sgs;
-   	total_packet_count = roundup(urb->transfer_buffer_length,
-   			usb_endpoint_maxp(&urb->ep->desc));
-   
- --- 2745,2751 ----
-   		return -EINVAL;
-   
-   	num_trbs = count_sg_trbs_needed(xhci, urb);
- ! 	num_sgs = urb->num_sgs;
-   	total_packet_count = roundup(urb->transfer_buffer_length,
-   			usb_endpoint_maxp(&urb->ep->desc));
-   
- diff -crN linux-3.2.1_o/drivers/usb/misc/isight_firmware.c linux-3.2.1/drivers/usb/misc/isight_firmware.c
- *** linux-3.2.1_o/drivers/usb/misc/isight_firmware.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/misc/isight_firmware.c	2014-05-15 13:25:15.055052376 +0900
- ***************
- *** 55,63 ****
-   
-   	ptr = firmware->data;
-   
- - 	buf[0] = 0x01;
-   	if (usb_control_msg
- ! 	    (dev, usb_sndctrlpipe(dev, 0), 0xa0, 0x40, 0xe600, 0, buf, 1,
-   	     300) != 1) {
-   		printk(KERN_ERR
-   		       "Failed to initialise isight firmware loader\n");
- --- 55,62 ----
-   
-   	ptr = firmware->data;
-   
-   	if (usb_control_msg
- ! 	    (dev, usb_sndctrlpipe(dev, 0), 0xa0, 0x40, 0xe600, 0, "\1", 1,
-   	     300) != 1) {
-   		printk(KERN_ERR
-   		       "Failed to initialise isight firmware loader\n");
- ***************
- *** 101,109 ****
-   		}
-   	}
-   
- - 	buf[0] = 0x00;
-   	if (usb_control_msg
- ! 	    (dev, usb_sndctrlpipe(dev, 0), 0xa0, 0x40, 0xe600, 0, buf, 1,
-   	     300) != 1) {
-   		printk(KERN_ERR "isight firmware loading completion failed\n");
-   		ret = -ENODEV;
- --- 100,107 ----
-   		}
-   	}
-   
-   	if (usb_control_msg
- ! 	    (dev, usb_sndctrlpipe(dev, 0), 0xa0, 0x40, 0xe600, 0, "\0", 1,
-   	     300) != 1) {
-   		printk(KERN_ERR "isight firmware loading completion failed\n");
-   		ret = -ENODEV;
- diff -crN linux-3.2.1_o/drivers/usb/musb/am35x.c linux-3.2.1/drivers/usb/musb/am35x.c
- *** linux-3.2.1_o/drivers/usb/musb/am35x.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/musb/am35x.c	2014-05-15 13:25:15.055052376 +0900
- ***************
- *** 36,41 ****
- --- 36,43 ----
-   #include <plat/usb.h>
-   
-   #include "musb_core.h"
- + #include "cppi41.h"
- + #include "cppi41_dma.h"
-   
-   /*
-    * AM35x specific definitions
- ***************
- *** 46,54 ****
-   #define USB_STAT_REG		0x08
-   #define USB_EMULATION_REG	0x0c
-   /* 0x10 Reserved */
- - #define USB_AUTOREQ_REG		0x14
-   #define USB_SRP_FIX_TIME_REG	0x18
- - #define USB_TEARDOWN_REG	0x1c
-   #define EP_INTR_SRC_REG		0x20
-   #define EP_INTR_SRC_SET_REG	0x24
-   #define EP_INTR_SRC_CLEAR_REG	0x28
- --- 48,54 ----
- ***************
- *** 80,87 ****
- --- 80,275 ----
-   #define AM35X_TX_INTR_MASK	(AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT)
-   #define AM35X_RX_INTR_MASK	(AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT)
-   
- + /* CPPI 4.1 queue manager registers */
- + #define QMGR_PEND0_REG		0x4090
- + #define QMGR_PEND1_REG		0x4094
- + #define QMGR_PEND2_REG		0x4098
- + 
-   #define USB_MENTOR_CORE_OFFSET	0x400
-   
- + #ifdef CONFIG_USB_TI_CPPI41_DMA
- + #define CPPI41_QMGR_REG0SIZE	0x3fff
- + 
- + /*
- +  * CPPI 4.1 resources used for USB OTG controller module:
- +  *
- +  * USB   DMA  DMA  QMgr  Tx     Src
- +  *       Tx   Rx         QNum   Port
- +  * ---------------------------------
- +  * EP0   0    0    0     16,17  1
- +  * ---------------------------------
- +  * EP1   1    1    0     18,19  2
- +  * ---------------------------------
- +  * EP2   2    2    0     20,21  3
- +  * ---------------------------------
- +  * EP3   3    3    0     22,23  4
- +  * ---------------------------------
- +  */
- + 
- + static u16 tx_comp_q[] = {63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63,
- + 				63, 63};
- + static u16 rx_comp_q[] = {65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65,
- + 				65, 65};
- + 
- + /* Fair scheduling */
- + u32 dma_sched_table[] = {
- + 	0x81018000, 0x83038202, 0x85058404, 0x87078606,
- + 	0x89098808, 0x8b0b8a0a, 0x8d0d8c0c, 0x00008e0e
- + };
- + 
- + /* DMA block configuration */
- + static const struct cppi41_tx_ch tx_ch_info[] = {
- + 	[0] = {
- + 		.port_num	= 1,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 32} , {0, 33} }
- + 	},
- + 	[1] = {
- + 		.port_num	= 2,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 34} , {0, 35} }
- + 	},
- + 	[2] = {
- + 		.port_num	= 3,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 36} , {0, 37} }
- + 	},
- + 	[3] = {
- + 		.port_num	= 4,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 38} , {0, 39} }
- + 	},
- + 	[4] = {
- + 		.port_num	= 5,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 40} , {0, 41} }
- + 	},
- + 	[5] = {
- + 		.port_num	= 6,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 42} , {0, 43} }
- + 	},
- + 	[6] = {
- + 		.port_num	= 7,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 44} , {0, 45} }
- + 	},
- + 	[7] = {
- + 		.port_num	= 8,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 46} , {0, 47} }
- + 	},
- + 	[8] = {
- + 		.port_num	= 9,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 48} , {0, 49} }
- + 	},
- + 	[9] = {
- + 		.port_num	= 10,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 50} , {0, 51} }
- + 	},
- + 	[10] = {
- + 		.port_num	= 11,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 52} , {0, 53} }
- + 	},
- + 	[11] = {
- + 		.port_num	= 12,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 54} , {0, 55} }
- + 	},
- + 	[12] = {
- + 		.port_num	= 13,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 56} , {0, 57} }
- + 	},
- + 	[13] = {
- + 		.port_num	= 14,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 58} , {0, 59} }
- + 	},
- + 	[14] = {
- + 		.port_num	= 15,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 60} , {0, 61} }
- + 	}
- + };
- + 
- + /* Queues 0 to 66 are pre-assigned, others are spare */
- + static const u32 assigned_queues[] = { 0xffffffff, 0xffffffff, 0x7 };
- + 
- + int __devinit cppi41_init(struct musb *musb)
- + {
- + 	struct usb_cppi41_info *cppi_info = &usb_cppi41_info[musb->id];
- + 	u16 numch, blknum, order, i;
- + 
- + 	/* init cppi info structure  */
- + 	cppi_info->dma_block = 0;
- + 	for (i = 0 ; i < USB_CPPI41_NUM_CH ; i++)
- + 		cppi_info->ep_dma_ch[i] = i;
- + 
- + 	cppi_info->q_mgr = 0;
- + 	cppi_info->num_tx_comp_q = 15;
- + 	cppi_info->num_rx_comp_q = 15;
- + 	cppi_info->tx_comp_q = tx_comp_q;
- + 	cppi_info->rx_comp_q = rx_comp_q;
- + 	cppi_info->bd_intr_ctrl = 0; /* am35x dont support bd interrupt */
- + 
- + 	blknum = cppi_info->dma_block;
- + 
- + 	/* Queue manager information */
- + 	cppi41_queue_mgr[0].num_queue = 96;
- + 	cppi41_queue_mgr[0].queue_types = CPPI41_FREE_DESC_BUF_QUEUE |
- + 						CPPI41_UNASSIGNED_QUEUE;
- + 	cppi41_queue_mgr[0].base_fdbq_num = 0;
- + 	cppi41_queue_mgr[0].assigned = assigned_queues;
- + 
- + 	/* init mappings */
- + 	cppi41_queue_mgr[0].q_mgr_rgn_base = musb->ctrl_base + 0x4000;
- + 	cppi41_queue_mgr[0].desc_mem_rgn_base = musb->ctrl_base + 0x5000;
- + 	cppi41_queue_mgr[0].q_mgmt_rgn_base = musb->ctrl_base + 0x6000;
- + 	cppi41_queue_mgr[0].q_stat_rgn_base = musb->ctrl_base + 0x6800;
- + 
- + 	/* init DMA block */
- + 	cppi41_dma_block[0].num_tx_ch = 15;
- + 	cppi41_dma_block[0].num_rx_ch = 15;
- + 	cppi41_dma_block[0].tx_ch_info = tx_ch_info;
- + 
- + 	cppi41_dma_block[0].global_ctrl_base = musb->ctrl_base + 0x1000;
- + 	cppi41_dma_block[0].ch_ctrl_stat_base = musb->ctrl_base + 0x1800;
- + 	cppi41_dma_block[0].sched_ctrl_base = musb->ctrl_base + 0x2000;
- + 	cppi41_dma_block[0].sched_table_base = musb->ctrl_base + 0x2800;
- + 
- + 	/* Initialize for Linking RAM region 0 alone */
- + 	cppi41_queue_mgr_init(cppi_info->q_mgr, 0, CPPI41_QMGR_REG0SIZE);
- + 
- + 	numch =  USB_CPPI41_NUM_CH * 2;
- + 	order = get_count_order(numch);
- + 
- + 	/* TODO: check two teardown desc per channel (5 or 7 ?)*/
- + 	if (order < 5)
- + 		order = 5;
- + 
- + 	cppi41_dma_block_init(blknum, cppi_info->q_mgr, order,
- + 			dma_sched_table, numch);
- + 	return 0;
- + }
- + void cppi41_free(void)
- + {
- + 	u32 numch, blknum, order;
- + 	struct usb_cppi41_info *cppi_info = &usb_cppi41_info[0];
- + 
- + 	numch =  USB_CPPI41_NUM_CH * 2;
- + 	order = get_count_order(numch);
- + 	blknum = cppi_info->dma_block;
- + 
- + 	cppi41_dma_block_uninit(blknum, cppi_info->q_mgr, order,
- + 			dma_sched_table, numch);
- + 	cppi41_queue_mgr_uninit(cppi_info->q_mgr);
- + }
- + #endif /* CONFIG_USB_TI_CPPI41_DMA */
- + 
-   struct am35x_glue {
-   	struct device		*dev;
-   	struct platform_device	*musb;
- ***************
- *** 228,237 ****
- --- 416,451 ----
-   	struct omap_musb_board_data *data = plat->board_data;
-   	unsigned long flags;
-   	irqreturn_t ret = IRQ_NONE;
- + 	u32 pend1 = 0, pend2 = 0, tx, rx;
-   	u32 epintr, usbintr;
-   
-   	spin_lock_irqsave(&musb->lock, flags);
-   
- + 	/*
- + 	 * CPPI 4.1 interrupts share the same IRQ and the EOI register but
- + 	 * don't get reflected in the interrupt source/mask registers.
- + 	 */
- + 	if (is_cppi41_enabled(musb)) {
- + 		/*
- + 		 * Check for the interrupts from Tx/Rx completion queues; they
- + 		 * are level-triggered and will stay asserted until the queues
- + 		 * are emptied.  We're using the queue pending register 0 as a
- + 		 * substitute for the interrupt status register and reading it
- + 		 * directly for speed.
- + 		 */
- + 		pend1 = musb_readl(reg_base, QMGR_PEND1_REG);
- + 		pend2 = musb_readl(reg_base, QMGR_PEND2_REG);
- + 
- + 		/* AM3517 uses 63,64,65 and 66 queues as completion queue */
- + 		if ((pend1 & (1 << 31)) || (pend2 & (7 << 0))) {
- + 			tx = (pend1 >> 31)  | ((pend2 & 1) ? (1 << 1) : 0);
- + 			rx = (pend2 >> 1) & 0x3;
- + 
- + 			dev_dbg(musb->controller, "CPPI 4.1 IRQ: Tx %x, Rx %x\n", tx, rx);
- + 			cppi41_completion(musb, rx, tx);
- + 			ret = IRQ_HANDLED;
- + 		}
- + 	}
-   	/* Get endpoint interrupts */
-   	epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);
-   
- ***************
- *** 362,369 ****
-   	if (!rev)
-   		return -ENODEV;
-   
- ! 	usb_nop_xceiv_register();
- ! 	musb->xceiv = otg_get_transceiver();
-   	if (!musb->xceiv)
-   		return -ENODEV;
-   
- --- 576,583 ----
-   	if (!rev)
-   		return -ENODEV;
-   
- ! 	usb_nop_xceiv_register(musb->id);
- ! 	musb->xceiv = otg_get_transceiver(musb->id);
-   	if (!musb->xceiv)
-   		return -ENODEV;
-   
- ***************
- *** 379,388 ****
-   
-   	/* Start the on-chip PHY and its PLL. */
-   	if (data->set_phy_power)
- ! 		data->set_phy_power(1);
-   
-   	msleep(5);
-   
-   	musb->isr = am35x_musb_interrupt;
-   
-   	/* clear level interrupt */
- --- 593,606 ----
-   
-   	/* Start the on-chip PHY and its PLL. */
-   	if (data->set_phy_power)
- ! 		data->set_phy_power(0, 1);
-   
-   	msleep(5);
-   
- + #ifdef CONFIG_USB_TI_CPPI41_DMA
- + 	cppi41_init(musb);
- + #endif
- + 
-   	musb->isr = am35x_musb_interrupt;
-   
-   	/* clear level interrupt */
- ***************
- *** 403,418 ****
-   
-   	/* Shutdown the on-chip PHY and its PLL. */
-   	if (data->set_phy_power)
- ! 		data->set_phy_power(0);
-   
-   	otg_put_transceiver(musb->xceiv);
- ! 	usb_nop_xceiv_unregister();
-   
-   	return 0;
-   }
-   
-   /* AM35x supports only 32bit read operation */
- ! void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
-   {
-   	void __iomem *fifo = hw_ep->fifo;
-   	u32		val;
- --- 621,636 ----
-   
-   	/* Shutdown the on-chip PHY and its PLL. */
-   	if (data->set_phy_power)
- ! 		data->set_phy_power(0, 0);
-   
-   	otg_put_transceiver(musb->xceiv);
- ! 	usb_nop_xceiv_unregister(musb->id);
-   
-   	return 0;
-   }
-   
-   /* AM35x supports only 32bit read operation */
- ! static void am35x_musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
-   {
-   	void __iomem *fifo = hw_ep->fifo;
-   	u32		val;
- ***************
- *** 442,447 ****
- --- 660,667 ----
-   }
-   
-   static const struct musb_platform_ops am35x_ops = {
- + 	.fifo_mode	= 4,
- + 	.flags		= MUSB_GLUE_EP_ADDR_FLAT_MAPPING | MUSB_GLUE_DMA_CPPI41,
-   	.init		= am35x_musb_init,
-   	.exit		= am35x_musb_exit,
-   
- ***************
- *** 452,457 ****
- --- 672,683 ----
-   	.try_idle	= am35x_musb_try_idle,
-   
-   	.set_vbus	= am35x_musb_set_vbus,
- + 
- + 	.read_fifo  = am35x_musb_read_fifo,
- + 	.write_fifo = musb_write_fifo,
- + 
- + 	.dma_controller_create = cppi41_dma_controller_create,
- + 	.dma_controller_destroy = cppi41_dma_controller_destroy,
-   };
-   
-   static u64 am35x_dmamask = DMA_BIT_MASK(32);
- ***************
- *** 473,484 ****
-   		goto err0;
-   	}
-   
- ! 	musb = platform_device_alloc("musb-hdrc", -1);
-   	if (!musb) {
-   		dev_err(&pdev->dev, "failed to allocate musb device\n");
-   		goto err1;
-   	}
-   
-   	phy_clk = clk_get(&pdev->dev, "fck");
-   	if (IS_ERR(phy_clk)) {
-   		dev_err(&pdev->dev, "failed to get PHY clock\n");
- --- 699,711 ----
-   		goto err0;
-   	}
-   
- ! 	musb = platform_device_alloc("musb-hdrc", pdev->id);
-   	if (!musb) {
-   		dev_err(&pdev->dev, "failed to allocate musb device\n");
-   		goto err1;
-   	}
-   
- + 	dev_set_name(&pdev->dev, "musb-am35x");
-   	phy_clk = clk_get(&pdev->dev, "fck");
-   	if (IS_ERR(phy_clk)) {
-   		dev_err(&pdev->dev, "failed to get PHY clock\n");
- ***************
- *** 566,572 ****
-   	struct am35x_glue	*glue = platform_get_drvdata(pdev);
-   
-   	platform_device_del(glue->musb);
- ! 	platform_device_put(glue->musb);
-   	clk_disable(glue->clk);
-   	clk_disable(glue->phy_clk);
-   	clk_put(glue->clk);
- --- 793,799 ----
-   	struct am35x_glue	*glue = platform_get_drvdata(pdev);
-   
-   	platform_device_del(glue->musb);
- ! 	/*platform_device_put(glue->musb);*/
-   	clk_disable(glue->clk);
-   	clk_disable(glue->phy_clk);
-   	clk_put(glue->clk);
- ***************
- *** 585,591 ****
-   
-   	/* Shutdown the on-chip PHY and its PLL. */
-   	if (data->set_phy_power)
- ! 		data->set_phy_power(0);
-   
-   	clk_disable(glue->phy_clk);
-   	clk_disable(glue->clk);
- --- 812,818 ----
-   
-   	/* Shutdown the on-chip PHY and its PLL. */
-   	if (data->set_phy_power)
- ! 		data->set_phy_power(0, 0);
-   
-   	clk_disable(glue->phy_clk);
-   	clk_disable(glue->clk);
- ***************
- *** 602,608 ****
-   
-   	/* Start the on-chip PHY and its PLL. */
-   	if (data->set_phy_power)
- ! 		data->set_phy_power(1);
-   
-   	ret = clk_enable(glue->phy_clk);
-   	if (ret) {
- --- 829,835 ----
-   
-   	/* Start the on-chip PHY and its PLL. */
-   	if (data->set_phy_power)
- ! 		data->set_phy_power(0, 1);
-   
-   	ret = clk_enable(glue->phy_clk);
-   	if (ret) {
- ***************
- *** 649,654 ****
- --- 876,884 ----
-   
-   static void __exit am35x_exit(void)
-   {
- + #ifdef CONFIG_USB_TI_CPPI41_DMA
- + 	cppi41_free();
- + #endif
-   	platform_driver_unregister(&am35x_driver);
-   }
-   module_exit(am35x_exit);
- diff -crN linux-3.2.1_o/drivers/usb/musb/blackfin.c linux-3.2.1/drivers/usb/musb/blackfin.c
- *** linux-3.2.1_o/drivers/usb/musb/blackfin.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/musb/blackfin.c	2014-05-15 13:25:15.058636190 +0900
- ***************
- *** 34,40 ****
-   /*
-    * Load an endpoint's FIFO
-    */
- ! void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
-   {
-   	struct musb *musb = hw_ep->musb;
-   	void __iomem *fifo = hw_ep->fifo;
- --- 34,41 ----
-   /*
-    * Load an endpoint's FIFO
-    */
- ! static void bfin_musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
- ! 				const u8 *src)
-   {
-   	struct musb *musb = hw_ep->musb;
-   	void __iomem *fifo = hw_ep->fifo;
- ***************
- *** 98,104 ****
-   /*
-    * Unload an endpoint's FIFO
-    */
- ! void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
-   {
-   	struct musb *musb = hw_ep->musb;
-   	void __iomem *fifo = hw_ep->fifo;
- --- 99,105 ----
-   /*
-    * Unload an endpoint's FIFO
-    */
- ! static void bfin_musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
-   {
-   	struct musb *musb = hw_ep->musb;
-   	void __iomem *fifo = hw_ep->fifo;
- ***************
- *** 414,421 ****
-   	}
-   	gpio_direction_output(musb->config->gpio_vrsel, 0);
-   
- ! 	usb_nop_xceiv_register();
- ! 	musb->xceiv = otg_get_transceiver();
-   	if (!musb->xceiv) {
-   		gpio_free(musb->config->gpio_vrsel);
-   		return -ENODEV;
- --- 415,422 ----
-   	}
-   	gpio_direction_output(musb->config->gpio_vrsel, 0);
-   
- ! 	usb_nop_xceiv_register(musb->id);
- ! 	musb->xceiv = otg_get_transceiver(musb->id);
-   	if (!musb->xceiv) {
-   		gpio_free(musb->config->gpio_vrsel);
-   		return -ENODEV;
- ***************
- *** 441,457 ****
-   	gpio_free(musb->config->gpio_vrsel);
-   
-   	otg_put_transceiver(musb->xceiv);
- ! 	usb_nop_xceiv_unregister();
-   	return 0;
-   }
-   
-   static const struct musb_platform_ops bfin_ops = {
-   	.init		= bfin_musb_init,
-   	.exit		= bfin_musb_exit,
-   
-   	.enable		= bfin_musb_enable,
-   	.disable	= bfin_musb_disable,
-   
-   	.set_mode	= bfin_musb_set_mode,
-   	.try_idle	= bfin_musb_try_idle,
-   
- --- 442,464 ----
-   	gpio_free(musb->config->gpio_vrsel);
-   
-   	otg_put_transceiver(musb->xceiv);
- ! 	usb_nop_xceiv_unregister(musb->id);
-   	return 0;
-   }
-   
-   static const struct musb_platform_ops bfin_ops = {
- + 	.fifo_mode	= 2,
- + 	.flags		= MUSB_GLUE_EP_ADDR_FLAT_MAPPING |
- + 				MUSB_GLUE_DMA_INVENTRA,
-   	.init		= bfin_musb_init,
-   	.exit		= bfin_musb_exit,
-   
-   	.enable		= bfin_musb_enable,
-   	.disable	= bfin_musb_disable,
-   
- + 	.read_fifo      = bfin_musb_read_fifo,
- + 	.write_fifo     = bfin_musb_write_fifo,
- + 
-   	.set_mode	= bfin_musb_set_mode,
-   	.try_idle	= bfin_musb_try_idle,
-   
- ***************
- *** 459,464 ****
- --- 466,474 ----
-   	.set_vbus	= bfin_musb_set_vbus,
-   
-   	.adjust_channel_params = bfin_musb_adjust_channel_params,
- + 
- + 	.dma_controller_create = inventra_dma_controller_create,
- + 	.dma_controller_destroy = inventra_dma_controller_destroy,
-   };
-   
-   static u64 bfin_dmamask = DMA_BIT_MASK(32);
- diff -crN linux-3.2.1_o/drivers/usb/musb/cppi41.c linux-3.2.1/drivers/usb/musb/cppi41.c
- *** linux-3.2.1_o/drivers/usb/musb/cppi41.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/drivers/usb/musb/cppi41.c	2014-05-15 13:25:15.058636190 +0900
- ***************
- *** 0 ****
- --- 1,1124 ----
- + /*
- +  * CPPI 4.1 support
- +  *
- +  * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
- +  *
- +  * Based on the PAL CPPI 4.1 implementation
- +  * Copyright (C) 1998-2006 Texas Instruments Incorporated
- +  *
- +  * This file contains the main implementation for CPPI 4.1 common peripherals,
- +  * including the DMA Controllers and the Queue Managers.
- +  *
- +  * This program is free software; you can distribute it and/or modify it
- +  * under the terms of the GNU General Public License (Version 2) as
- +  * published by the Free Software Foundation.
- +  *
- +  * This program is distributed in the hope it will be useful, but WITHOUT
- +  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- +  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- +  * for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License along
- +  * with this program; if not, write to the Free Software Foundation, Inc.,
- +  * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- +  *
- +  */
- + 
- + #include <linux/io.h>
- + #include <linux/init.h>
- + #include <linux/slab.h>
- + #include <linux/module.h>
- + #include <linux/dma-mapping.h>
- + 
- + #include "cppi41.h"
- + 
- + #undef	CPPI41_DEBUG
- + 
- + #ifdef	CPPI41_DEBUG
- + #define DBG(format, args...) printk(format, ##args)
- + #else
- + #define DBG(format, args...)
- + #endif
- + 
- + static struct {
- + 	void *virt_addr;
- + 	dma_addr_t phys_addr;
- + 	u32     size;
- + } linking_ram[CPPI41_NUM_QUEUE_MGR];
- + 
- + static u32 *allocated_queues[CPPI41_NUM_QUEUE_MGR];
- + 
- + /* First 32 packet descriptors are reserved for unallocated memory regions. */
- + static u32 next_desc_index[CPPI41_NUM_QUEUE_MGR] = { 1 << 5 };
- + static u8  next_mem_rgn[CPPI41_NUM_QUEUE_MGR];
- + 
- + static struct {
- + 	size_t rgn_size;
- + 	void *virt_addr;
- + 	dma_addr_t phys_addr;
- + 	struct cppi41_queue_obj queue_obj;
- + 	u8 mem_rgn;
- + 	u16 q_mgr;
- + 	u16 q_num;
- + 	u32 num_desc;
- + } dma_teardown[CPPI41_NUM_DMA_BLOCK];
- + 
- + struct cppi41_dma_sched_tbl_t {
- + 	u8      pos;
- + 	u8      dma_ch;
- + 	u8      is_tx;
- + 	u8      enb;
- + };
- + 
- + struct cppi41_dma_sched_tbl_t dma_sched_tbl[MAX_SCHED_TBL_ENTRY] = {
- + 	/*pos  dma_ch#  is_tx  enb/dis*/
- + 	{ 0,    0,      0,      1},
- + 	{ 1,    0,      1,      1},
- + 	{ 2,    1,      0,      1},
- + 	{ 3,    1,      1,      1},
- + 	{ 4,    2,      0,      1},
- + 	{ 5,    2,      1,      1},
- + 	{ 6,    3,      0,      1},
- + 	{ 7,    3,      1,      1}
- + };
- + 
- + struct cppi41_queue_mgr cppi41_queue_mgr[CPPI41_NUM_QUEUE_MGR];
- + EXPORT_SYMBOL(cppi41_queue_mgr);
- + 
- + struct cppi41_dma_block cppi41_dma_block[CPPI41_NUM_DMA_BLOCK];
- + EXPORT_SYMBOL(cppi41_dma_block);
- + /******************** CPPI 4.1 Functions (External Interface) *****************/
- + 
- + int cppi41_queue_mgr_init(u8 q_mgr, dma_addr_t rgn0_base, u16 rgn0_size)
- + {
- + 	void __iomem *q_mgr_regs;
- + 	void *ptr;
- + 
- + 	if (q_mgr >= cppi41_num_queue_mgr)
- + 		return -EINVAL;
- + 
- + 	q_mgr_regs = cppi41_queue_mgr[q_mgr].q_mgr_rgn_base;
- + 	ptr = dma_alloc_coherent(NULL, rgn0_size * 4,
- + 				 &linking_ram[q_mgr].phys_addr,
- + 				 GFP_KERNEL | GFP_DMA);
- + 	if (ptr == NULL) {
- + 		printk(KERN_ERR "ERROR: %s: Unable to allocate "
- + 		       "linking RAM.\n", __func__);
- + 		return -ENOMEM;
- + 	}
- + 	linking_ram[q_mgr].virt_addr = ptr;
- + 	linking_ram[q_mgr].size = rgn0_size * 4;
- + 
- + 	cppi_writel(linking_ram[q_mgr].phys_addr,
- + 			q_mgr_regs + QMGR_LINKING_RAM_RGN0_BASE_REG);
- + 	DBG("Linking RAM region 0 base @ %p, value: %x\n",
- + 	    q_mgr_regs + QMGR_LINKING_RAM_RGN0_BASE_REG,
- + 	    cppi_readl(q_mgr_regs + QMGR_LINKING_RAM_RGN0_BASE_REG));
- + 
- + 	cppi_writel(rgn0_size, q_mgr_regs + QMGR_LINKING_RAM_RGN0_SIZE_REG);
- + 	DBG("Linking RAM region 0 size @ %p, value: %x\n",
- + 	    q_mgr_regs + QMGR_LINKING_RAM_RGN0_SIZE_REG,
- + 	    cppi_readl(q_mgr_regs + QMGR_LINKING_RAM_RGN0_SIZE_REG));
- + 
- + 	ptr = kzalloc(BITS_TO_LONGS(cppi41_queue_mgr[q_mgr].num_queue) *
- + 			sizeof(long), GFP_KERNEL);
- + 	if (ptr == NULL) {
- + 		printk(KERN_ERR "ERROR: %s: Unable to allocate queue bitmap.\n",
- + 		       __func__);
- + 		dma_free_coherent(NULL, rgn0_size * 4,
- + 				  linking_ram[q_mgr].virt_addr,
- + 				  linking_ram[q_mgr].phys_addr);
- + 		return -ENOMEM;
- + 	}
- + 	allocated_queues[q_mgr] = ptr;
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(cppi41_queue_mgr_init);
- + 
- + int cppi41_queue_mgr_uninit(u8 q_mgr)
- + {
- + 	void __iomem *q_mgr_regs;
- + 
- + 	if (q_mgr >= cppi41_num_queue_mgr)
- + 		return -EINVAL;
- + 
- + 	q_mgr_regs = cppi41_queue_mgr[q_mgr].q_mgr_rgn_base;
- + 
- + 	/* free the Queue Mgr linking ram space */
- + 	cppi_writel(0,	q_mgr_regs + QMGR_LINKING_RAM_RGN0_BASE_REG);
- + 	cppi_writel(0, q_mgr_regs + QMGR_LINKING_RAM_RGN0_SIZE_REG);
- + 	dma_free_coherent(NULL, linking_ram[q_mgr].size,
- + 			linking_ram[q_mgr].virt_addr,
- + 			linking_ram[q_mgr].phys_addr);
- + 
- + 	/* free the allocated queues */
- + 	kfree(allocated_queues[q_mgr]);
- + 	return 0;
- + }
- + EXPORT_SYMBOL(cppi41_queue_mgr_uninit);
- + 
- + int cppi41_dma_sched_tbl_init(u8 dma_num, u8 q_mgr,
- + 			u32 *sched_tbl, u8 tbl_size)
- + {
- + 	struct cppi41_dma_block *dma_block;
- + 	int num_reg, k, i, val = 0;
- + 
- + 	dma_block = (struct cppi41_dma_block *)&cppi41_dma_block[dma_num];
- + 
- + 	num_reg = (tbl_size + 3) / 4;
- + 	for (k = i = 0; i < num_reg; i++) {
- + #if 0
- + 		for (val = j = 0; j < 4; j++, k++) {
- + 			val >>= 8;
- + 			if (k < tbl_size)
- + 				val |= sched_tbl[k] << 24;
- + 		}
- + #endif
- + 		val = sched_tbl[i];
- + 		cppi_writel(val, dma_block->sched_table_base +
- + 			DMA_SCHED_TABLE_WORD_REG(i));
- + 		DBG("DMA scheduler table @ %p, value written: %x\n",
- + 		dma_block->sched_table_base + DMA_SCHED_TABLE_WORD_REG(i),
- + 			val);
- + 	}
- + 	return 0;
- + }
- + EXPORT_SYMBOL(cppi41_dma_sched_tbl_init);
- + 
- + int cppi41_schedtbl_add_dma_ch(u8 dmanum, u8 qmgr, u8 dma_ch, u8 is_tx)
- + {
- + 	struct cppi41_dma_block *dma_block;
- + 	int num_ch, i, tbl_index = 0, j = 0, found = 0;
- + 	u32 val;
- + 
- + 	dma_block = (struct cppi41_dma_block *)&cppi41_dma_block[dmanum];
- + 
- + 	val = 0;
- + 	for (num_ch = 0, i = 0; i < MAX_SCHED_TBL_ENTRY; i++) {
- + 		if (!found && dma_sched_tbl[i].dma_ch == dma_ch &&
- + 			dma_sched_tbl[i].is_tx == is_tx &&
- + 			dma_sched_tbl[i].enb == 0) {
- + 			dma_sched_tbl[i].enb = 1;
- + 			found = 1;
- + 		}
- + 
- + 		if (dma_sched_tbl[i].enb) {
- + 			val |= ((dma_sched_tbl[i].dma_ch |
- + 				(dma_sched_tbl[i].is_tx ? 0 : (1<<7))) << j*8);
- + 			num_ch++;
- + 			j++;
- + 		}
- + 		if (num_ch % 4 == 0) {
- + 			cppi_writel(val, dma_block->sched_table_base +
- + 				DMA_SCHED_TABLE_WORD_REG(tbl_index));
- + 			tbl_index++;
- + 			val = j = 0;
- + 		}
- + 	}
- + 
- + 	if (num_ch % 4) {
- + 		cppi_writel(val, dma_block->sched_table_base +
- + 			DMA_SCHED_TABLE_WORD_REG(tbl_index));
- + 	}
- + 	return num_ch;
- + }
- + EXPORT_SYMBOL(cppi41_schedtbl_add_dma_ch);
- + 
- + int cppi41_schedtbl_remove_dma_ch(u8 dmanum, u8 qmgr, u8 dma_ch, u8 is_tx)
- + {
- + 	struct cppi41_dma_block *dma_block;
- + 	int num_ch, i, tbl_index = 0, j = 0, found = 0;
- + 	u32 val;
- + 
- + 	dma_block = (struct cppi41_dma_block *)&cppi41_dma_block[dmanum];
- + 
- + 	val = 0;
- + 	for (num_ch = 0, i = 0; i < MAX_SCHED_TBL_ENTRY; i++) {
- + 		if (!found && dma_sched_tbl[i].dma_ch == dma_ch &&
- + 			dma_sched_tbl[i].is_tx == is_tx &&
- + 			dma_sched_tbl[i].enb == 1) {
- + 			dma_sched_tbl[i].enb = 0;
- + 		}
- + 
- + 		if (dma_sched_tbl[i].enb) {
- + 			val |= ((dma_sched_tbl[i].dma_ch |
- + 				(dma_sched_tbl[i].is_tx ? 0 : (1<<7))) << j*8);
- + 			num_ch++;
- + 			j++;
- + 		}
- + 		if (num_ch % 4 == 0) {
- + 			cppi_writel(val, dma_block->sched_table_base +
- + 				DMA_SCHED_TABLE_WORD_REG(tbl_index));
- + 			tbl_index++;
- + 			val = j = 0;
- + 		}
- + 	}
- + 
- + 	if (num_ch % 4) {
- + 		cppi_writel(val, dma_block->sched_table_base +
- + 			DMA_SCHED_TABLE_WORD_REG(tbl_index));
- + 	}
- + 	return num_ch;
- + }
- + EXPORT_SYMBOL(cppi41_schedtbl_remove_dma_ch);
- + 
- + int cppi41_dma_block_init(u8 dma_num, u8 q_mgr, u8 num_order,
- + 				 u32 *sched_tbl, u8 tbl_size)
- + {
- + 	const struct cppi41_dma_block *dma_block;
- + 	unsigned num_desc, num_reg;
- + 	void *ptr;
- + 	int error, i;
- + 	u16 q_num;
- + 	u32 val;
- + 
- + 	if (dma_num >= cppi41_num_dma_block ||
- + 	    q_mgr >= cppi41_num_queue_mgr ||
- + 	    !tbl_size || sched_tbl == NULL)
- + 		return -EINVAL;
- + 
- + 	error = cppi41_queue_alloc(CPPI41_FREE_DESC_QUEUE |
- + 				   CPPI41_UNASSIGNED_QUEUE, q_mgr, &q_num);
- + 	if (error) {
- + 		printk(KERN_ERR "ERROR: %s: Unable to allocate teardown "
- + 		       "descriptor queue.\n", __func__);
- + 		return error;
- + 	}
- + 	DBG("Teardown descriptor queue %d in queue manager 0 "
- + 	    "allocated\n", q_num);
- + 
- + 	/*
- + 	 * Tell the hardware about the Teardown descriptor
- + 	 * queue manager and queue number.
- + 	 */
- + 	dma_block = &cppi41_dma_block[dma_num];
- + 	cppi_writel((q_mgr << DMA_TD_DESC_QMGR_SHIFT) |
- + 		     (q_num << DMA_TD_DESC_QNUM_SHIFT),
- + 		     dma_block->global_ctrl_base +
- + 		     DMA_TEARDOWN_FREE_DESC_CTRL_REG);
- + 	DBG("Teardown free descriptor control @ %p, value: %x\n",
- + 	    dma_block->global_ctrl_base + DMA_TEARDOWN_FREE_DESC_CTRL_REG,
- + 	    cppi_readl(dma_block->global_ctrl_base +
- + 			DMA_TEARDOWN_FREE_DESC_CTRL_REG));
- + 
- + 	num_desc = 1 << num_order;
- + 	dma_teardown[dma_num].rgn_size = num_desc *
- + 					 sizeof(struct cppi41_teardown_desc);
- + 
- + 	/* Pre-allocate teardown descriptors. */
- + 	ptr = dma_alloc_coherent(NULL, dma_teardown[dma_num].rgn_size,
- + 				 &dma_teardown[dma_num].phys_addr,
- + 				 GFP_KERNEL | GFP_DMA);
- + 	if (ptr == NULL) {
- + 		printk(KERN_ERR "ERROR: %s: Unable to allocate teardown "
- + 		       "descriptors.\n", __func__);
- + 		error = -ENOMEM;
- + 		goto free_queue;
- + 	}
- + 	dma_teardown[dma_num].virt_addr = ptr;
- + 
- + 	error = cppi41_mem_rgn_alloc(q_mgr, dma_teardown[dma_num].phys_addr, 5,
- + 				     num_order, &dma_teardown[dma_num].mem_rgn);
- + 	if (error) {
- + 		printk(KERN_ERR "ERROR: %s: Unable to allocate queue manager "
- + 		       "memory region for teardown descriptors.\n", __func__);
- + 		goto free_mem;
- + 	}
- + 
- + 	error = cppi41_queue_init(&dma_teardown[dma_num].queue_obj, 0, q_num);
- + 	if (error) {
- + 		printk(KERN_ERR "ERROR: %s: Unable to initialize teardown "
- + 		       "free descriptor queue.\n", __func__);
- + 		goto free_rgn;
- + 	}
- + 
- + 	dma_teardown[dma_num].q_num = q_num;
- + 	dma_teardown[dma_num].q_mgr = q_mgr;
- + 	dma_teardown[dma_num].num_desc = num_desc;
- + 	/*
- + 	 * Push all teardown descriptors to the free teardown queue
- + 	 * for the CPPI 4.1 system.
- + 	 */
- + 	cppi41_init_teardown_queue(dma_num);
- + 
- + 	/* Initialize the DMA scheduler. */
- + 	num_reg = (tbl_size + 3) / 4;
- + 	for (i = 0; i < num_reg; i++) {
- + 		val = sched_tbl[i];
- + 		cppi_writel(val, dma_block->sched_table_base +
- + 			     DMA_SCHED_TABLE_WORD_REG(i));
- + 		DBG("DMA scheduler table @ %p, value written: %x\n",
- + 		    dma_block->sched_table_base + DMA_SCHED_TABLE_WORD_REG(i),
- + 		    val);
- + 	}
- + 
- + 	cppi_writel((tbl_size - 1) << DMA_SCHED_LAST_ENTRY_SHIFT |
- + 		     DMA_SCHED_ENABLE_MASK,
- + 		     dma_block->sched_ctrl_base + DMA_SCHED_CTRL_REG);
- + 	DBG("DMA scheduler control @ %p, value: %x\n",
- + 	    dma_block->sched_ctrl_base + DMA_SCHED_CTRL_REG,
- + 	    cppi_readl(dma_block->sched_ctrl_base + DMA_SCHED_CTRL_REG));
- + 
- + 	return 0;
- + 
- + free_rgn:
- + 	cppi41_mem_rgn_free(q_mgr, dma_teardown[dma_num].mem_rgn);
- + free_mem:
- + 	dma_free_coherent(NULL, dma_teardown[dma_num].rgn_size,
- + 			  dma_teardown[dma_num].virt_addr,
- + 			  dma_teardown[dma_num].phys_addr);
- + free_queue:
- + 	cppi41_queue_free(q_mgr, q_num);
- + 	return error;
- + }
- + EXPORT_SYMBOL(cppi41_dma_block_init);
- + 
- + int cppi41_dma_block_uninit(u8 dma_num, u8 q_mgr, u8 num_order,
- + 				 u32 *sched_tbl, u8 tbl_size)
- + {
- + 	const struct cppi41_dma_block *dma_block;
- + 	unsigned num_reg;
- + 	int i;
- + 
- + 	/* popout all teardown descriptors */
- + 	cppi41_free_teardown_queue(dma_num);
- + 
- + 	/* free queue mgr region */
- + 	cppi41_mem_rgn_free(q_mgr, dma_teardown[dma_num].mem_rgn);
- + 	/* free the allocated teardown descriptors */
- + 	dma_free_coherent(NULL, dma_teardown[dma_num].rgn_size,
- + 			dma_teardown[dma_num].virt_addr,
- + 			dma_teardown[dma_num].phys_addr);
- + 
- + 	/* free the teardown queue*/
- + 	cppi41_queue_free(dma_teardown[dma_num].q_mgr,
- + 			dma_teardown[dma_num].q_num);
- + 
- + 	dma_block = (struct cppi41_dma_block *)&cppi41_dma_block[dma_num];
- + 	/* disable the dma schedular */
- + 	num_reg = (tbl_size + 3) / 4;
- + 	for (i = 0; i < num_reg; i++) {
- + 		cppi_writel(0, dma_block->sched_table_base +
- + 			     DMA_SCHED_TABLE_WORD_REG(i));
- + 		DBG("DMA scheduler table @ %p, value written: %x\n",
- + 		    dma_block->sched_table_base + DMA_SCHED_TABLE_WORD_REG(i),
- + 		    0);
- + 	}
- + 
- + 	cppi_writel(0,	dma_block->sched_ctrl_base + DMA_SCHED_CTRL_REG);
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(cppi41_dma_block_uninit);
- + /*
- +  * cppi41_mem_rgn_alloc - allocate a memory region within the queue manager
- +  */
- + int cppi41_mem_rgn_alloc(u8 q_mgr, dma_addr_t rgn_addr, u8 size_order,
- + 			 u8 num_order, u8 *mem_rgn)
- + {
- + 	void __iomem *desc_mem_regs;
- + 	u32 num_desc = 1 << num_order, index, ctrl;
- + 	int rgn;
- + 
- + 	DBG("%s called with rgn_addr = %08x, size_order = %d, num_order = %d\n",
- + 	    __func__, rgn_addr, size_order, num_order);
- + 
- + 	if (q_mgr >= cppi41_num_queue_mgr ||
- + 	    size_order < 5 || size_order > 13 ||
- + 	    num_order  < 5 || num_order  > 12 ||
- + 	    (rgn_addr & ((1 << size_order) - 1)))
- + 		return -EINVAL;
- + 
- + 	rgn = next_mem_rgn[q_mgr];
- + 	index = next_desc_index[q_mgr];
- + 	if (rgn >= CPPI41_MAX_MEM_RGN || index + num_desc > 0x4000)
- + 		return -ENOSPC;
- + 
- + 	next_mem_rgn[q_mgr] = rgn + 1;
- + 	next_desc_index[q_mgr] = index + num_desc;
- + 
- + 	desc_mem_regs = cppi41_queue_mgr[q_mgr].desc_mem_rgn_base;
- + 
- + 	/* Write the base register */
- + 	cppi_writel(rgn_addr, desc_mem_regs + QMGR_MEM_RGN_BASE_REG(rgn));
- + 	DBG("Descriptor region base @ %p, value: %x\n",
- + 	    desc_mem_regs + QMGR_MEM_RGN_BASE_REG(rgn),
- + 	    cppi_readl(desc_mem_regs + QMGR_MEM_RGN_BASE_REG(rgn)));
- + 
- + 	/* Write the control register */
- + 	ctrl = ((index << QMGR_MEM_RGN_INDEX_SHIFT) &
- + 		QMGR_MEM_RGN_INDEX_MASK) |
- + 	       (((size_order - 5) << QMGR_MEM_RGN_DESC_SIZE_SHIFT) &
- + 		QMGR_MEM_RGN_DESC_SIZE_MASK) |
- + 	       (((num_order - 5) << QMGR_MEM_RGN_SIZE_SHIFT) &
- + 		QMGR_MEM_RGN_SIZE_MASK);
- + 	cppi_writel(ctrl, desc_mem_regs + QMGR_MEM_RGN_CTRL_REG(rgn));
- + 	DBG("Descriptor region control @ %p, value: %x\n",
- + 	    desc_mem_regs + QMGR_MEM_RGN_CTRL_REG(rgn),
- + 	    cppi_readl(desc_mem_regs + QMGR_MEM_RGN_CTRL_REG(rgn)));
- + 
- + 	*mem_rgn = rgn;
- + 	return 0;
- + }
- + EXPORT_SYMBOL(cppi41_mem_rgn_alloc);
- + 
- + /*
- +  * cppi41_mem_rgn_free - free the memory region within the queue manager
- +  */
- + int cppi41_mem_rgn_free(u8 q_mgr, u8 mem_rgn)
- + {
- + 	void __iomem *desc_mem_regs;
- + 
- + 	DBG("%s called.\n", __func__);
- + 
- + 	if (q_mgr >= cppi41_num_queue_mgr || mem_rgn >= next_mem_rgn[q_mgr])
- + 		return -EINVAL;
- + 
- + 	desc_mem_regs = cppi41_queue_mgr[q_mgr].desc_mem_rgn_base;
- + 
- + 	if (cppi_readl(desc_mem_regs + QMGR_MEM_RGN_BASE_REG(mem_rgn)) == 0)
- + 		return -ENOENT;
- + 
- + 	cppi_writel(0, desc_mem_regs + QMGR_MEM_RGN_BASE_REG(mem_rgn));
- + 	cppi_writel(0, desc_mem_regs + QMGR_MEM_RGN_CTRL_REG(mem_rgn));
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(cppi41_mem_rgn_free);
- + 
- + /*
- +  * cppi41_tx_ch_init - initialize a CPPI 4.1 Tx channel object
- +  *
- +  * Verify the channel info (range checking, etc.) and store the channel
- +  * information within the object structure.
- +  */
- + int cppi41_tx_ch_init(struct cppi41_dma_ch_obj *tx_ch_obj,
- + 		      u8 dma_num, u8 ch_num)
- + {
- + 	if (dma_num >= cppi41_num_dma_block ||
- + 	    ch_num  >= cppi41_dma_block[dma_num].num_tx_ch)
- + 		return -EINVAL;
- + 
- + 	/* Populate the channel object structure */
- + 	tx_ch_obj->base_addr  = cppi41_dma_block[dma_num].ch_ctrl_stat_base +
- + 				DMA_CH_TX_GLOBAL_CFG_REG(ch_num);
- + 	tx_ch_obj->global_cfg = cppi_readl(tx_ch_obj->base_addr);
- + 	return 0;
- + }
- + EXPORT_SYMBOL(cppi41_tx_ch_init);
- + 
- + /*
- +  * cppi41_rx_ch_init - initialize a CPPI 4.1 Rx channel object
- +  *
- +  * Verify the channel info (range checking, etc.) and store the channel
- +  * information within the object structure.
- +  */
- + int cppi41_rx_ch_init(struct cppi41_dma_ch_obj *rx_ch_obj,
- + 		      u8 dma_num, u8 ch_num)
- + {
- + 	if (dma_num >= cppi41_num_dma_block ||
- + 	    ch_num  >= cppi41_dma_block[dma_num].num_rx_ch)
- + 		return -EINVAL;
- + 
- + 	/* Populate the channel object structure */
- + 	rx_ch_obj->base_addr  = cppi41_dma_block[dma_num].ch_ctrl_stat_base +
- + 				DMA_CH_RX_GLOBAL_CFG_REG(ch_num);
- + 	rx_ch_obj->global_cfg = cppi_readl(rx_ch_obj->base_addr);
- + 	return 0;
- + }
- + EXPORT_SYMBOL(cppi41_rx_ch_init);
- + 
- + /*
- +  * We have to cache the last written Rx/Tx channel global configration register
- +  * value due to its bits other than enable/teardown being write-only. Yet there
- +  * is a caveat related to caching the enable bit: this bit may be automatically
- +  * cleared as a result of teardown, so we can't trust its cached value!
- +  * When modifying the write only register fields, we're making use of the fact
- +  * that they read back as zeros, and not clearing them explicitly...
- +  */
- + 
- + /*
- +  * cppi41_dma_ch_default_queue - set CPPI 4.1 channel default completion queue
- +  */
- + void cppi41_dma_ch_default_queue(struct cppi41_dma_ch_obj *dma_ch_obj,
- + 				 u8 q_mgr, u16 q_num)
- + {
- + 	u32 val = dma_ch_obj->global_cfg;
- + 
- + 	/* Clear the fields to be modified. */
- + 	val &= ~(DMA_CH_TX_DEFAULT_QMGR_MASK | DMA_CH_TX_DEFAULT_QNUM_MASK |
- + 		 DMA_CH_TX_ENABLE_MASK);
- + 
- + 	/* Set the default completion queue. */
- + 	val |= ((q_mgr << DMA_CH_TX_DEFAULT_QMGR_SHIFT) &
- + 		DMA_CH_TX_DEFAULT_QMGR_MASK) |
- + 	       ((q_num << DMA_CH_TX_DEFAULT_QNUM_SHIFT) &
- + 		DMA_CH_TX_DEFAULT_QNUM_MASK);
- + 
- + 	/* Get the current state of the enable bit. */
- + 	dma_ch_obj->global_cfg = val |= cppi_readl(dma_ch_obj->base_addr);
- + 	cppi_writel(val, dma_ch_obj->base_addr);
- + 	DBG("Channel global configuration @ %p, value written: %x, "
- + 	    "value read: %x\n", dma_ch_obj->base_addr, val,
- + 	    cppi_readl(dma_ch_obj->base_addr));
- + 
- + }
- + EXPORT_SYMBOL(cppi41_dma_ch_default_queue);
- + 
- + /*
- +  * cppi41_rx_ch_configure - configure CPPI 4.1 Rx channel
- +  */
- + void cppi41_rx_ch_configure(struct cppi41_dma_ch_obj *rx_ch_obj,
- + 			    struct cppi41_rx_ch_cfg  *cfg)
- + {
- + 	void __iomem *base = rx_ch_obj->base_addr;
- + 	u32 val = cppi_readl(rx_ch_obj->base_addr);
- + 
- + 	val |= ((cfg->sop_offset << DMA_CH_RX_SOP_OFFSET_SHIFT) &
- + 		DMA_CH_RX_SOP_OFFSET_MASK) |
- + 	       ((cfg->default_desc_type << DMA_CH_RX_DEFAULT_DESC_TYPE_SHIFT) &
- + 		DMA_CH_RX_DEFAULT_DESC_TYPE_MASK) |
- + 	       ((cfg->retry_starved << DMA_CH_RX_ERROR_HANDLING_SHIFT) &
- + 		DMA_CH_RX_ERROR_HANDLING_MASK) |
- + 	       ((cfg->rx_queue.q_mgr << DMA_CH_RX_DEFAULT_RQ_QMGR_SHIFT) &
- + 		DMA_CH_RX_DEFAULT_RQ_QMGR_MASK) |
- + 	       ((cfg->rx_queue.q_num << DMA_CH_RX_DEFAULT_RQ_QNUM_SHIFT) &
- + 		DMA_CH_RX_DEFAULT_RQ_QNUM_MASK);
- + 
- + 	val &= ~(0x7 << DMA_CH_RX_MAX_BUF_CNT_SHIFT);
- + 	val |= (cfg->rx_max_buf_cnt << DMA_CH_RX_MAX_BUF_CNT_SHIFT);
- + 
- + 	rx_ch_obj->global_cfg = val;
- + 	cppi_writel(val, base);
- + 	DBG("Rx channel global configuration @ %p, value written: %x, "
- + 	    "value read: %x\n", base, val, cppi_readl(base));
- + 
- + 	base -= DMA_CH_RX_GLOBAL_CFG_REG(0);
- + 
- + 	/*
- + 	 * Set up the packet configuration register
- + 	 * based on the descriptor type...
- + 	 */
- + 	switch (cfg->default_desc_type) {
- + 	case DMA_CH_RX_DEFAULT_DESC_EMBED:
- + 		val = ((cfg->cfg.embed_pkt.fd_queue.q_mgr <<
- + 			DMA_CH_RX_EMBED_FDQ_QMGR_SHIFT) &
- + 		       DMA_CH_RX_EMBED_FDQ_QMGR_MASK) |
- + 		      ((cfg->cfg.embed_pkt.fd_queue.q_num <<
- + 			DMA_CH_RX_EMBED_FDQ_QNUM_SHIFT) &
- + 		       DMA_CH_RX_EMBED_FDQ_QNUM_MASK) |
- + 		      ((cfg->cfg.embed_pkt.num_buf_slot <<
- + 			DMA_CH_RX_EMBED_NUM_SLOT_SHIFT) &
- + 		       DMA_CH_RX_EMBED_NUM_SLOT_MASK) |
- + 		      ((cfg->cfg.embed_pkt.sop_slot_num <<
- + 			DMA_CH_RX_EMBED_SOP_SLOT_SHIFT) &
- + 		       DMA_CH_RX_EMBED_SOP_SLOT_MASK);
- + 
- + 		cppi_writel(val, base + DMA_CH_RX_EMBED_PKT_CFG_REG_B(0));
- + 		DBG("Rx channel embedded packet configuration B @ %p, "
- + 		    "value written: %x\n",
- + 		    base + DMA_CH_RX_EMBED_PKT_CFG_REG_B(0), val);
- + 
- + 		val = ((cfg->cfg.embed_pkt.free_buf_pool[0].b_pool <<
- + 			DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(0)) &
- + 		       DMA_CH_RX_EMBED_FBP_PNUM_MASK(0)) |
- + 		      ((cfg->cfg.embed_pkt.free_buf_pool[0].b_mgr <<
- + 			DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(0)) &
- + 		       DMA_CH_RX_EMBED_FBP_BMGR_MASK(0)) |
- + 		      ((cfg->cfg.embed_pkt.free_buf_pool[1].b_pool <<
- + 			DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(1)) &
- + 		       DMA_CH_RX_EMBED_FBP_PNUM_MASK(1)) |
- + 		      ((cfg->cfg.embed_pkt.free_buf_pool[1].b_mgr <<
- + 			DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(1)) &
- + 		       DMA_CH_RX_EMBED_FBP_BMGR_MASK(1)) |
- + 		      ((cfg->cfg.embed_pkt.free_buf_pool[2].b_pool <<
- + 			DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(2)) &
- + 		       DMA_CH_RX_EMBED_FBP_PNUM_MASK(2)) |
- + 		      ((cfg->cfg.embed_pkt.free_buf_pool[2].b_mgr <<
- + 			DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(2)) &
- + 		       DMA_CH_RX_EMBED_FBP_BMGR_MASK(2)) |
- + 		      ((cfg->cfg.embed_pkt.free_buf_pool[3].b_pool <<
- + 			DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(3)) &
- + 		       DMA_CH_RX_EMBED_FBP_PNUM_MASK(3)) |
- + 		      ((cfg->cfg.embed_pkt.free_buf_pool[3].b_mgr <<
- + 			DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(3)) &
- + 		       DMA_CH_RX_EMBED_FBP_BMGR_MASK(3));
- + 
- + 		cppi_writel(val, base + DMA_CH_RX_EMBED_PKT_CFG_REG_A(0));
- + 		DBG("Rx channel embedded packet configuration A @ %p, "
- + 		    "value written: %x\n",
- + 		    base + DMA_CH_RX_EMBED_PKT_CFG_REG_A(0), val);
- + 		break;
- + 	case DMA_CH_RX_DEFAULT_DESC_HOST:
- + 		val = ((cfg->cfg.host_pkt.fdb_queue[0].q_num <<
- + 			DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(0)) &
- + 		       DMA_CH_RX_HOST_FDQ_QNUM_MASK(0)) |
- + 		      ((cfg->cfg.host_pkt.fdb_queue[0].q_mgr <<
- + 			DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(0)) &
- + 		       DMA_CH_RX_HOST_FDQ_QMGR_MASK(0)) |
- + 		      ((cfg->cfg.host_pkt.fdb_queue[1].q_num <<
- + 			DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(1)) &
- + 		       DMA_CH_RX_HOST_FDQ_QNUM_MASK(1)) |
- + 		      ((cfg->cfg.host_pkt.fdb_queue[1].q_mgr <<
- + 			DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(1)) &
- + 		       DMA_CH_RX_HOST_FDQ_QMGR_MASK(1));
- + 
- + 		cppi_writel(val, base + DMA_CH_RX_HOST_PKT_CFG_REG_A(0));
- + 		DBG("Rx channel host packet configuration A @ %p, "
- + 		    "value written: %x\n",
- + 		    base + DMA_CH_RX_HOST_PKT_CFG_REG_A(0), val);
- + 
- + 		val = ((cfg->cfg.host_pkt.fdb_queue[2].q_num <<
- + 			DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(2)) &
- + 		       DMA_CH_RX_HOST_FDQ_QNUM_MASK(2)) |
- + 		      ((cfg->cfg.host_pkt.fdb_queue[2].q_mgr <<
- + 			DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(2)) &
- + 		       DMA_CH_RX_HOST_FDQ_QMGR_MASK(2)) |
- + 		      ((cfg->cfg.host_pkt.fdb_queue[3].q_num <<
- + 		       DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(3)) &
- + 		       DMA_CH_RX_HOST_FDQ_QNUM_MASK(3)) |
- + 		      ((cfg->cfg.host_pkt.fdb_queue[3].q_mgr <<
- + 			DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(3)) &
- + 		       DMA_CH_RX_HOST_FDQ_QMGR_MASK(3));
- + 
- + 		cppi_writel(val, base + DMA_CH_RX_HOST_PKT_CFG_REG_B(0));
- + 		DBG("Rx channel host packet configuration B @ %p, "
- + 		    "value written: %x\n",
- + 		    base + DMA_CH_RX_HOST_PKT_CFG_REG_B(0), val);
- + 		break;
- + 	case DMA_CH_RX_DEFAULT_DESC_MONO:
- + 		val = ((cfg->cfg.mono_pkt.fd_queue.q_num <<
- + 			DMA_CH_RX_MONO_FDQ_QNUM_SHIFT) &
- + 		       DMA_CH_RX_MONO_FDQ_QNUM_MASK) |
- + 		      ((cfg->cfg.mono_pkt.fd_queue.q_mgr <<
- + 			DMA_CH_RX_MONO_FDQ_QMGR_SHIFT) &
- + 		       DMA_CH_RX_MONO_FDQ_QMGR_MASK) |
- + 		      ((cfg->cfg.mono_pkt.sop_offset <<
- + 			DMA_CH_RX_MONO_SOP_OFFSET_SHIFT) &
- + 		       DMA_CH_RX_MONO_SOP_OFFSET_MASK);
- + 
- + 		cppi_writel(val, base + DMA_CH_RX_MONO_PKT_CFG_REG(0));
- + 		DBG("Rx channel monolithic packet configuration @ %p, "
- + 		    "value written: %x\n",
- + 		    base + DMA_CH_RX_MONO_PKT_CFG_REG(0), val);
- + 		break;
- + 	}
- + }
- + EXPORT_SYMBOL(cppi41_rx_ch_configure);
- + 
- + void cppi41_rx_ch_set_maxbufcnt(struct cppi41_dma_ch_obj *rx_ch_obj,
- + 			    u8 rx_max_buf_cnt)
- + {
- + 	void __iomem *base = rx_ch_obj->base_addr;
- + 	u32 val = cppi_readl(rx_ch_obj->base_addr);
- + 
- + 	val = rx_ch_obj->global_cfg;
- + 	val &= ~(0x7 << DMA_CH_RX_MAX_BUF_CNT_SHIFT);
- + 	val |= (rx_max_buf_cnt << DMA_CH_RX_MAX_BUF_CNT_SHIFT);
- + 
- + 	rx_ch_obj->global_cfg = val;
- + 	cppi_writel(val, base);
- + 
- + 	DBG("%s: rx-global-cfg @ %p, value written: %x, "
- + 	    "value read: %x\n", __func__, base, val, cppi_readl(base));
- + 
- + }
- + EXPORT_SYMBOL(cppi41_rx_ch_set_maxbufcnt);
- + /*
- +  * cppi41_dma_ch_teardown - teardown a given Tx/Rx channel
- +  */
- + void cppi41_dma_ch_teardown(struct cppi41_dma_ch_obj *dma_ch_obj)
- + {
- + 	u32 val = cppi_readl(dma_ch_obj->base_addr);
- + 
- + 	/* Initiate channel teardown. */
- + 	val |= dma_ch_obj->global_cfg & ~DMA_CH_TX_ENABLE_MASK;
- + 	dma_ch_obj->global_cfg = val |= DMA_CH_TX_TEARDOWN_MASK;
- + 	cppi_writel(val, dma_ch_obj->base_addr);
- + 	DBG("Tear down channel @ %p, value written: %x, value read: %x\n",
- + 	    dma_ch_obj->base_addr, val, cppi_readl(dma_ch_obj->base_addr));
- + }
- + EXPORT_SYMBOL(cppi41_dma_ch_teardown);
- + 
- + /*
- +  * cppi41_dma_ch_enable - enable Tx/Rx DMA channel in hardware
- +  *
- +  * Makes the channel ready for data transmission/reception.
- +  */
- + void cppi41_dma_ch_enable(struct cppi41_dma_ch_obj *dma_ch_obj)
- + {
- + 	u32 val = dma_ch_obj->global_cfg | DMA_CH_TX_ENABLE_MASK;
- + 
- + 	/* Teardown bit remains set after completion, so clear it now... */
- + 	dma_ch_obj->global_cfg = val &= ~DMA_CH_TX_TEARDOWN_MASK;
- + 	cppi_writel(val, dma_ch_obj->base_addr);
- + 	DBG("Enable channel @ %p, value written: %x, value read: %x\n",
- + 	    dma_ch_obj->base_addr, val, cppi_readl(dma_ch_obj->base_addr));
- + }
- + EXPORT_SYMBOL(cppi41_dma_ch_enable);
- + 
- + /*
- +  * cppi41_dma_ch_disable - disable Tx/Rx DMA channel in hardware
- +  */
- + void cppi41_dma_ch_disable(struct cppi41_dma_ch_obj *dma_ch_obj)
- + {
- + 	dma_ch_obj->global_cfg &= ~DMA_CH_TX_ENABLE_MASK;
- + 	cppi_writel(dma_ch_obj->global_cfg, dma_ch_obj->base_addr);
- + 	DBG("Disable channel @ %p, value written: %x, value read: %x\n",
- + 	    dma_ch_obj->base_addr, dma_ch_obj->global_cfg,
- + 	    cppi_readl(dma_ch_obj->base_addr));
- + }
- + EXPORT_SYMBOL(cppi41_dma_ch_disable);
- + 
- + void cppi41_init_teardown_queue(int dma_num)
- + {
- + 	dma_addr_t td_addr;
- + 	struct cppi41_teardown_desc *curr_td;
- + 	u32 num_desc = dma_teardown[dma_num].num_desc;
- + 	int i;
- + 
- + 	curr_td = dma_teardown[dma_num].virt_addr;
- + 	td_addr = dma_teardown[dma_num].phys_addr;
- + 
- + 	for (i = 0; i < num_desc; i++) {
- + 		cppi41_queue_push(&dma_teardown[dma_num].queue_obj, td_addr,
- + 				  sizeof(*curr_td), 0);
- + 		td_addr += sizeof(*curr_td);
- + 	}
- + }
- + EXPORT_SYMBOL(cppi41_init_teardown_queue);
- + 
- + void cppi41_free_teardown_queue(int dma_num)
- + {
- + 	unsigned long td_addr;
- + 	u32 num_desc = dma_teardown[dma_num].num_desc;
- + 
- + 	while (num_desc--) {
- + 		td_addr = cppi41_queue_pop(&dma_teardown[dma_num].queue_obj);
- + 
- + 		if (td_addr == 0)
- + 			break;
- + 	}
- + }
- + EXPORT_SYMBOL(cppi41_free_teardown_queue);
- + 
- + /**
- +  * alloc_queue - allocate a queue in the given range
- +  * @allocated:	pointer to the bitmap of the allocated queues
- +  * @excluded:	pointer to the bitmap of the queues excluded from allocation
- +  *		(optional)
- +  * @start:	starting queue number
- +  * @count:	number of queues available
- +  *
- +  * Returns queue number on success, -ENOSPC otherwise.
- +  */
- + static int alloc_queue(u32 *allocated, const u32 *excluded, unsigned start,
- + 		       unsigned count)
- + {
- + 	u32 bit, mask = 0;
- + 	int index = -1;
- + 
- + 	/*
- + 	 * We're starting the loop as if we've just wrapped around 32 bits
- + 	 * in order to save on preloading the bitmasks.
- + 	 */
- + 	for (bit = 0; count--; start++, bit <<= 1) {
- + 		/* Have we just wrapped around 32 bits? */
- + 		if (!bit) {
- + 			/* Start over with the next bitmask word */
- + 			bit = 1;
- + 			index++;
- + 			/* Have we just entered the loop? */
- + 			if (!index) {
- + 				/* Calculate the starting values */
- + 				bit <<= start & 0x1f;
- + 				index = start >> 5;
- + 			}
- + 			/*
- + 			 * Load the next word of the allocated bitmask OR'ing
- + 			 * it with the excluded bitmask if it's been passed.
- + 			 */
- + 			mask = allocated[index];
- + 			if (excluded != NULL)
- + 				mask |= excluded[index];
- + 		}
- + 		/*
- + 		 * If the bit in the combined bitmask is zero,
- + 		 * we've just found a free queue.
- + 		 */
- + 		if (!(mask & bit)) {
- + 			allocated[index] |= bit;
- + 			return start;
- + 		}
- + 	}
- + 	return -ENOSPC;
- + }
- + 
- + /*
- +  * cppi41_queue_alloc - allocate a queue of a given type in the queue manager
- +  */
- + int cppi41_queue_alloc(u8 type, u8 q_mgr, u16 *q_num)
- + {
- + 	int res = -ENOSPC;
- + 
- + 	if (q_mgr >= cppi41_num_queue_mgr)
- + 		return -EINVAL;
- + 
- + 	/* Mask out the unsupported queue types */
- + 	type &= cppi41_queue_mgr[q_mgr].queue_types;
- + 	/* First see if a free descriptor queue was requested... */
- + 	if (type & CPPI41_FREE_DESC_QUEUE)
- + 		res = alloc_queue(allocated_queues[q_mgr], NULL,
- + 				  cppi41_queue_mgr[q_mgr].base_fdq_num,  16);
- + 
- + 	/* Then see if a free descriptor/buffer queue was requested... */
- + 	if (res < 0 && (type & CPPI41_FREE_DESC_BUF_QUEUE))
- + 		res = alloc_queue(allocated_queues[q_mgr], NULL,
- + 				  cppi41_queue_mgr[q_mgr].base_fdbq_num, 16);
- + 
- + 	/* Last see if an unassigned queue was requested... */
- + 	if (res < 0 && (type & CPPI41_UNASSIGNED_QUEUE))
- + 		res = alloc_queue(allocated_queues[q_mgr],
- + 				  cppi41_queue_mgr[q_mgr].assigned, 0,
- + 				  cppi41_queue_mgr[q_mgr].num_queue);
- + 
- + 	/* See if any queue was allocated... */
- + 	if (res < 0)
- + 		return res;
- + 
- + 	/* Return the queue allocated */
- + 	*q_num = res;
- + 	return 0;
- + }
- + EXPORT_SYMBOL(cppi41_queue_alloc);
- + 
- + /*
- +  * cppi41_queue_free - free the given queue in the queue manager
- +  */
- + int cppi41_queue_free(u8 q_mgr, u16 q_num)
- + {
- + 	int index = q_num >> 5, bit = 1 << (q_num & 0x1f);
- + 
- + 	if (allocated_queues[q_mgr] != NULL) {
- + 		if (q_mgr >= cppi41_num_queue_mgr ||
- + 		    q_num >= cppi41_queue_mgr[q_mgr].num_queue ||
- + 		    !(allocated_queues[q_mgr][index] & bit))
- + 			return -EINVAL;
- + 		allocated_queues[q_mgr][index] &= ~bit;
- + 	}
- + 	return 0;
- + }
- + EXPORT_SYMBOL(cppi41_queue_free);
- + 
- + /*
- +  * cppi41_queue_init - initialize a CPPI 4.1 queue object
- +  */
- + int cppi41_queue_init(struct cppi41_queue_obj *queue_obj, u8 q_mgr, u16 q_num)
- + {
- + 	if (q_mgr >= cppi41_num_queue_mgr ||
- + 	    q_num >= cppi41_queue_mgr[q_mgr].num_queue)
- + 		return -EINVAL;
- + 
- + 	queue_obj->base_addr = cppi41_queue_mgr[q_mgr].q_mgmt_rgn_base +
- + 			       QMGR_QUEUE_STATUS_REG_A(q_num);
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(cppi41_queue_init);
- + 
- + /*
- +  * cppi41_queue_push - push a descriptor into the given queue
- +  */
- + void cppi41_queue_push(const struct cppi41_queue_obj *queue_obj, u32 desc_addr,
- + 		       u32 desc_size, u32 pkt_size)
- + {
- + 	u32 val;
- + 
- + 	/*
- + 	 * Write to the tail of the queue.
- + 	 * TODO: Can't think of a reason why a queue to head may be required.
- + 	 * If it is, the API may have to be extended.
- + 	 */
- + #if 0
- + 	/*
- + 	 * Also, can't understand why packet size is required to queue up a
- + 	 * descriptor. The spec says packet size *must* be written prior to
- + 	 * the packet write operation.
- + 	 */
- + 	if (pkt_size)
- + 		val = (pkt_size << QMGR_QUEUE_PKT_SIZE_SHIFT) &
- + 		      QMGR_QUEUE_PKT_SIZE_MASK;
- + 	cppi_writel(val, queue_obj->base_addr + QMGR_QUEUE_REG_C(0));
- + #endif
- + 
- + 	val = (((desc_size - 24) >> (2 - QMGR_QUEUE_DESC_SIZE_SHIFT)) &
- + 	       QMGR_QUEUE_DESC_SIZE_MASK) |
- + 	      (desc_addr & QMGR_QUEUE_DESC_PTR_MASK);
- + 
- + 	DBG("Pushing value %x to queue @ %p\n", val, queue_obj->base_addr);
- + 
- + 	cppi_writel(val, queue_obj->base_addr + QMGR_QUEUE_REG_D(0));
- + }
- + EXPORT_SYMBOL(cppi41_queue_push);
- + 
- + /*
- +  * cppi41_queue_pop - pop a descriptor from a given queue
- +  */
- + unsigned long cppi41_queue_pop(const struct cppi41_queue_obj *queue_obj)
- + {
- + 	u32 val = cppi_readl(queue_obj->base_addr + QMGR_QUEUE_REG_D(0));
- + 
- + 	DBG("Popping value %x from queue @ %p\n", val, queue_obj->base_addr);
- + 
- + 	return val & QMGR_QUEUE_DESC_PTR_MASK;
- + }
- + EXPORT_SYMBOL(cppi41_queue_pop);
- + 
- + /*
- +  * cppi41_get_teardown_info - extract information from a teardown descriptor
- +  */
- + int cppi41_get_teardown_info(unsigned long addr, u32 *info)
- + {
- + 	struct cppi41_teardown_desc *desc;
- + 	int dma_num;
- + 
- + 	for (dma_num = 0; dma_num < cppi41_num_dma_block; dma_num++)
- + 		if (addr >= dma_teardown[dma_num].phys_addr &&
- + 		    addr <  dma_teardown[dma_num].phys_addr +
- + 			    dma_teardown[dma_num].rgn_size)
- + 			break;
- + 
- + 	if (dma_num == cppi41_num_dma_block)
- + 		return -EINVAL;
- + 
- + 	desc = addr - dma_teardown[dma_num].phys_addr +
- + 	       dma_teardown[dma_num].virt_addr;
- + 
- + 	if ((desc->teardown_info & CPPI41_DESC_TYPE_MASK) !=
- + 	    (CPPI41_DESC_TYPE_TEARDOWN << CPPI41_DESC_TYPE_SHIFT))
- + 		return -EINVAL;
- + 
- + 	*info = desc->teardown_info;
- + #if 1
- + 	/* Hardware is not giving the current DMA number as of now. :-/ */
- + 	*info |= (dma_num << CPPI41_TEARDOWN_DMA_NUM_SHIFT) &
- + 		 CPPI41_TEARDOWN_DMA_NUM_MASK;
- + #else
- + 	dma_num = (desc->teardown_info & CPPI41_TEARDOWN_DMA_NUM_MASK) >>
- + 		 CPPI41_TEARDOWN_DMA_NUM_SHIFT;
- + #endif
- + 
- + 	cppi41_queue_push(&dma_teardown[dma_num].queue_obj, addr,
- + 			  sizeof(struct cppi41_teardown_desc), 0);
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(cppi41_get_teardown_info);
- + 
- + /*
- +  * cppi41_save_context - save regsiter context before going to suspend.
- +  */
- + void cppi41_save_context(u8 dma_num)
- + {
- + 	const struct cppi41_dma_block *dma_block;
- + 	struct cppi41_dma_regs *cppi41;
- + 	struct cppi41_queue_manager *qmgr;
- + 	void __iomem *q_mgr_regs, *desc_mem_regs;
- + 	u8 i, q_mgr = 0;
- + 
- + 	dma_block = (struct cppi41_dma_block *)&cppi41_dma_block[dma_num];
- + 	cppi41 = (struct cppi41_dma_regs *)&dma_block->cppi41_regs;
- + 	qmgr = &cppi41->qmgr;
- + 	q_mgr_regs = cppi41_queue_mgr[q_mgr].q_mgr_rgn_base;
- + 	desc_mem_regs = cppi41_queue_mgr[q_mgr].desc_mem_rgn_base;
- + 
- + 	/* popout all teardown descriptors */
- + 	cppi41_free_teardown_queue(dma_num);
- + 
- + 	cppi41->teardn_fdq_ctrl = cppi_readl(dma_block->global_ctrl_base +
- + 			DMA_TEARDOWN_FREE_DESC_CTRL_REG);
- + 	cppi41->emulation_ctrl = cppi_readl(dma_block->global_ctrl_base +
- + 			DMA_EMULATION_CTRL_REG);
- + 
- + 	qmgr->link_ram_rgn0_base = cppi_readl(q_mgr_regs +
- + 				QMGR_LINKING_RAM_RGN0_BASE_REG);
- + 	qmgr->link_ram_rgn0_size = cppi_readl(q_mgr_regs +
- + 				QMGR_LINKING_RAM_RGN0_SIZE_REG);
- + 	qmgr->link_ram_rgn1_base = cppi_readl(q_mgr_regs +
- + 				QMGR_LINKING_RAM_RGN1_BASE_REG);
- + 
- + 	for (i = 0 ; i < 8 ; i++) {
- + 		qmgr->memr_base[i] = cppi_readl(desc_mem_regs +
- + 				QMGR_MEM_RGN_BASE_REG(i));
- + 		qmgr->memr_ctrl[i] = cppi_readl(desc_mem_regs +
- + 				QMGR_MEM_RGN_CTRL_REG(i));
- + 	}
- + 
- + 	cppi41->sched_ctrl = cppi_readl(dma_block->sched_ctrl_base +
- + 				DMA_SCHED_CTRL_REG);
- + 
- + }
- + EXPORT_SYMBOL(cppi41_save_context);
- + 
- + /*
- +  * cppi41_restore_context - restore regsiter context after resume.
- +  */
- + void cppi41_restore_context(u8 dma_num, u32 *sched_tbl)
- + {
- + 	const struct cppi41_dma_block *dma_block;
- + 	struct cppi41_dma_regs *cppi41;
- + 	struct cppi41_queue_manager *qmgr;
- + 	void __iomem *q_mgr_regs, *desc_mem_regs;
- + 	unsigned num_reg;
- + 	u32 val;
- + 	u8 tbl_size;
- + 	u8 i, q_mgr = 0;
- + 
- + 	dma_block = (struct cppi41_dma_block *)&cppi41_dma_block[dma_num];
- + 	cppi41 = (struct cppi41_dma_regs *)&dma_block->cppi41_regs;
- + 	qmgr = &cppi41->qmgr;
- + 	q_mgr_regs = cppi41_queue_mgr[q_mgr].q_mgr_rgn_base;
- + 	desc_mem_regs = cppi41_queue_mgr[q_mgr].desc_mem_rgn_base;
- + 	tbl_size = dma_block->num_max_ch;
- + 
- + 	cppi_writel(cppi41->teardn_fdq_ctrl, dma_block->global_ctrl_base +
- + 			DMA_TEARDOWN_FREE_DESC_CTRL_REG);
- + 	cppi_writel(cppi41->emulation_ctrl, dma_block->global_ctrl_base +
- + 			DMA_EMULATION_CTRL_REG);
- + 
- + 	cppi_writel(qmgr->link_ram_rgn0_base, q_mgr_regs +
- + 				QMGR_LINKING_RAM_RGN0_BASE_REG);
- + 	cppi_writel(qmgr->link_ram_rgn0_size, q_mgr_regs +
- + 				QMGR_LINKING_RAM_RGN0_SIZE_REG);
- + 	cppi_writel(qmgr->link_ram_rgn1_base, q_mgr_regs +
- + 				QMGR_LINKING_RAM_RGN1_BASE_REG);
- + 
- + 	for (i = 0 ; i < 8 ; i++) {
- + 		cppi_writel(qmgr->memr_base[i], desc_mem_regs +
- + 				QMGR_MEM_RGN_BASE_REG(i));
- + 		cppi_writel(qmgr->memr_ctrl[i], desc_mem_regs +
- + 				QMGR_MEM_RGN_CTRL_REG(i));
- + 	}
- + 
- + 	/*
- + 	 * Push all teardown descriptors to the free teardown queue
- + 	 * for the CPPI 4.1 system.
- + 	 */
- + 	cppi41_init_teardown_queue(dma_num);
- + 
- + 	/* Initialize the DMA scheduler. */
- + 	num_reg = (tbl_size + 3) / 4;
- + 	for (i = 0; i < num_reg; i++) {
- + 		val = sched_tbl[i];
- + 		cppi_writel(val, dma_block->sched_table_base +
- + 			     DMA_SCHED_TABLE_WORD_REG(i));
- + 	}
- + 	cppi_writel(cppi41->sched_ctrl, dma_block->sched_ctrl_base +
- + 				DMA_SCHED_CTRL_REG);
- + }
- + EXPORT_SYMBOL(cppi41_restore_context);
- + 
- + MODULE_DESCRIPTION("TI CPPI 4.1 support");
- + MODULE_AUTHOR("MontaVista Software");
- + MODULE_LICENSE("GPL");
- diff -crN linux-3.2.1_o/drivers/usb/musb/cppi41_dma.c linux-3.2.1/drivers/usb/musb/cppi41_dma.c
- *** linux-3.2.1_o/drivers/usb/musb/cppi41_dma.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/drivers/usb/musb/cppi41_dma.c	2014-05-15 13:25:15.062607361 +0900
- ***************
- *** 0 ****
- --- 1,1855 ----
- + /*
- +  * Copyright (C) 2005-2006 by Texas Instruments
- +  * Copyright (c) 2008, MontaVista Software, Inc. <source@mvista.com>
- +  *
- +  * This file implements a DMA interface using TI's CPPI 4.1 DMA.
- +  *
- +  * This program is free software; you can distribute it and/or modify it
- +  * under the terms of the GNU General Public License (Version 2) as
- +  * published by the Free Software Foundation.
- +  *
- +  * This program is distributed in the hope it will be useful, but WITHOUT
- +  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- +  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- +  * for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License along
- +  * with this program; if not, write to the Free Software Foundation, Inc.,
- +  * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- +  *
- +  */
- + 
- + #include <linux/errno.h>
- + #include <linux/dma-mapping.h>
- + #include <linux/module.h>
- + 
- + #include "cppi41.h"
- + 
- + #include "musb_core.h"
- + #include "musb_dma.h"
- + #include "cppi41_dma.h"
- + 
- + /* Configuration */
- + #define USB_CPPI41_DESC_SIZE_SHIFT 6
- + #define USB_CPPI41_DESC_ALIGN	(1 << USB_CPPI41_DESC_SIZE_SHIFT)
- + #define USB_CPPI41_CH_NUM_PD	128	/* 4K bulk data at full speed */
- + #define USB_CPPI41_MAX_PD	(USB_CPPI41_CH_NUM_PD * (USB_CPPI41_NUM_CH+1))
- + 
- + #undef DEBUG_CPPI_TD
- + #undef USBDRV_DEBUG
- + 
- + #ifdef USBDRV_DEBUG
- + #define dprintk(x, ...) printk(x, ## __VA_ARGS__)
- + #else
- + #define dprintk(x, ...)
- + #endif
- + 
- + /*
- +  * Data structure definitions
- +  */
- + 
- + /*
- +  * USB Packet Descriptor
- +  */
- + struct usb_pkt_desc;
- + 
- + struct usb_pkt_desc {
- + 	/* Hardware descriptor fields from this point */
- + 	struct cppi41_host_pkt_desc hw_desc;	/* 40 bytes */
- + 	/* Protocol specific data */
- + 	dma_addr_t dma_addr;			/* offs:44 byte */
- + 	struct usb_pkt_desc *next_pd_ptr;	/* offs:48 byte*/
- + 	u8 ch_num;
- + 	u8 ep_num;
- + 	u8 eop;
- + 	u8 res1;				/* offs:52 */
- + 	u8 res2[12];				/* offs:64 */
- + };
- + 
- + /**
- +  * struct cppi41_channel - DMA Channel Control Structure
- +  *
- +  * Using the same for Tx/Rx.
- +  */
- + struct cppi41_channel {
- + 	struct dma_channel channel;
- + 
- + 	struct cppi41_dma_ch_obj dma_ch_obj; /* DMA channel object */
- + 	struct cppi41_queue src_queue;	/* Tx queue or Rx free descriptor/ */
- + 					/* buffer queue */
- + 	struct cppi41_queue_obj queue_obj; /* Tx queue object or Rx free */
- + 					/* descriptor/buffer queue object */
- + 
- + 	u32 tag_info;			/* Tx PD Tag Information field */
- + 
- + 	/* Which direction of which endpoint? */
- + 	struct musb_hw_ep *end_pt;
- + 	u8 transmit;
- + 	u8 ch_num;			/* Channel number of Tx/Rx 0..3 */
- + 
- + 	/* DMA mode: "transparent", RNDIS, CDC, or Generic RNDIS */
- + 	u8 dma_mode;
- + 	u8 autoreq;
- + 
- + 	/* Book keeping for the current transfer request */
- + 	dma_addr_t start_addr;
- + 	u32 length;
- + 	u32 curr_offset;
- + 	u16 pkt_size;
- + 	u8  transfer_mode;
- + 	u8  zlp_queued;
- + 	u8  inf_mode;
- + 	u8  tx_complete;
- + 	u8  rx_complete;
- + 	u8  hb_mult;
- + 	u8  txf_complete;
- + 	u8  txfifo_intr_enable;
- + 	u8  count;
- + 	struct usb_pkt_desc *curr_pd;
- + };
- + 
- + /**
- +  * struct cppi41 - CPPI 4.1 DMA Controller Object
- +  *
- +  * Encapsulates all book keeping and data structures pertaining to
- +  * the CPPI 1.4 DMA controller.
- +  */
- + struct cppi41 {
- + 	struct dma_controller controller;
- + 	struct musb *musb;
- + 
- + 	struct cppi41_channel tx_cppi_ch[USB_CPPI41_NUM_CH];
- + 	struct cppi41_channel rx_cppi_ch[USB_CPPI41_NUM_CH];
- + 	struct work_struct      txdma_work;
- + 	struct work_struct      rxdma_work;
- + 
- + 	struct usb_pkt_desc *pd_pool_head; /* Free PD pool head */
- + 	dma_addr_t pd_mem_phys;		/* PD memory physical address */
- + 	void *pd_mem;			/* PD memory pointer */
- + 	u8 pd_mem_rgn;			/* PD memory region number */
- + 
- + 	u16 teardownQNum;		/* Teardown completion queue number */
- + 	struct cppi41_queue_obj queue_obj; /* Teardown completion queue */
- + 					/* object */
- + 	u32 pkt_info;			/* Tx PD Packet Information field */
- + 	struct usb_cppi41_info *cppi_info; /* cppi channel information */
- + 	u8 en_bd_intr;			/* enable bd interrupt */
- + 	u32 automode_reg_offs;		/* USB_AUTOREQ_REG offset */
- + 	u32 teardown_reg_offs;		/* USB_TEARDOWN_REG offset */
- + 	u32 bd_size;
- + 	u8  inf_mode;
- + 	u8  txfifo_intr_enable;		/* txfifo empty interrupt logic */
- + };
- + 
- + struct usb_cppi41_info usb_cppi41_info[2];
- + EXPORT_SYMBOL(usb_cppi41_info);
- + static void rxdma_completion_work(struct work_struct *data);
- + 
- + #ifdef DEBUG_CPPI_TD
- + static void print_pd_list(struct usb_pkt_desc *pd_pool_head)
- + {
- + 	struct usb_pkt_desc *curr_pd = pd_pool_head;
- + 	int cnt = 0;
- + 
- + 	while (curr_pd != NULL) {
- + 		if (cnt % 8 == 0)
- + 			dprintk("\n%02x ", cnt);
- + 		cnt++;
- + 		dprintk(" %p", curr_pd);
- + 		curr_pd = curr_pd->next_pd_ptr;
- + 	}
- + 	dprintk("\n");
- + }
- + #endif
- + 
- + static struct usb_pkt_desc *usb_get_free_pd(struct cppi41 *cppi)
- + {
- + 	struct usb_pkt_desc *free_pd = cppi->pd_pool_head;
- + 
- + 	if (free_pd != NULL) {
- + 		cppi->pd_pool_head = free_pd->next_pd_ptr;
- + 		free_pd->next_pd_ptr = NULL;
- + 	}
- + 	return free_pd;
- + }
- + 
- + static void usb_put_free_pd(struct cppi41 *cppi, struct usb_pkt_desc *free_pd)
- + {
- + 	free_pd->next_pd_ptr = cppi->pd_pool_head;
- + 	cppi->pd_pool_head = free_pd;
- + }
- + 
- + /**
- +  * cppi41_controller_start - start DMA controller
- +  * @controller: the controller
- +  *
- +  * This function initializes the CPPI 4.1 Tx/Rx channels.
- +  */
- + static int __devinit cppi41_controller_start(struct dma_controller *controller)
- + {
- + 	struct cppi41 *cppi;
- + 	struct cppi41_channel *cppi_ch;
- + 	void __iomem *reg_base;
- + 	struct usb_pkt_desc *curr_pd;
- + 	unsigned long pd_addr;
- + 	int i;
- + 	struct usb_cppi41_info *cppi_info;
- + 	struct musb *musb;
- + 
- + 	cppi = container_of(controller, struct cppi41, controller);
- + 	cppi_info = cppi->cppi_info;
- + 	musb = cppi->musb;
- + 
- + 	if (cpu_is_ti816x() || cpu_is_am33xx()) {
- + 		cppi->automode_reg_offs = TI81XX_USB_AUTOREQ_REG;
- + 		cppi->teardown_reg_offs = TI81XX_USB_TEARDOWN_REG;
- + 	} else {
- + 		cppi->automode_reg_offs = USB_AUTOREQ_REG;
- + 		cppi->teardown_reg_offs = USB_TEARDOWN_REG;
- + 	}
- + 
- + 	/*
- + 	 * TODO: We may need to check USB_CPPI41_MAX_PD here since CPPI 4.1
- + 	 * requires the descriptor count to be a multiple of 2 ^ 5 (i.e. 32).
- + 	 * Similarly, the descriptor size should also be a multiple of 32.
- + 	 */
- + 
- + 	/*
- + 	 * Allocate free packet descriptor pool for all Tx/Rx endpoints --
- + 	 * dma_alloc_coherent()  will return a page aligned address, so our
- + 	 * alignment requirement will be honored.
- + 	 */
- + 	cppi->bd_size = USB_CPPI41_MAX_PD * sizeof(struct usb_pkt_desc);
- + 	cppi->pd_mem = dma_alloc_coherent(cppi->musb->controller,
- + 					  cppi->bd_size,
- + 					  &cppi->pd_mem_phys,
- + 					  GFP_KERNEL | GFP_DMA);
- + 	if (cppi->pd_mem == NULL) {
- + 		dev_dbg(musb->controller, "ERROR: packet descriptor memory allocation failed\n");
- + 		return 0;
- + 	}
- + 
- + 	if (cppi41_mem_rgn_alloc(cppi_info->q_mgr, cppi->pd_mem_phys,
- + 				 USB_CPPI41_DESC_SIZE_SHIFT,
- + 				 get_count_order(USB_CPPI41_MAX_PD),
- + 				 &cppi->pd_mem_rgn)) {
- + 		dev_dbg(musb->controller, "ERROR: queue manager memory region allocation "
- + 		    "failed\n");
- + 		goto free_pds;
- + 	}
- + 
- + 	/* Allocate the teardown completion queue */
- + 	if (cppi41_queue_alloc(CPPI41_UNASSIGNED_QUEUE,
- + 			       0, &cppi->teardownQNum)) {
- + 		dev_dbg(musb->controller, "ERROR: teardown completion queue allocation failed\n");
- + 		goto free_mem_rgn;
- + 	}
- + 	dev_dbg(musb->controller, "Allocated teardown completion queue %d in queue manager 0\n",
- + 	    cppi->teardownQNum);
- + 
- + 	if (cppi41_queue_init(&cppi->queue_obj, 0, cppi->teardownQNum)) {
- + 		dev_dbg(musb->controller, "ERROR: teardown completion queue initialization "
- + 		    "failed\n");
- + 		goto free_queue;
- + 	}
- + 
- + 	/*
- + 	 * "Slice" PDs one-by-one from the big chunk and
- + 	 * add them to the free pool.
- + 	 */
- + 	curr_pd = (struct usb_pkt_desc *)cppi->pd_mem;
- + 	pd_addr = cppi->pd_mem_phys;
- + 	for (i = 0; i < USB_CPPI41_MAX_PD; i++) {
- + 		curr_pd->dma_addr = pd_addr;
- + 
- + 		usb_put_free_pd(cppi, curr_pd);
- + 		curr_pd = (struct usb_pkt_desc *)((char *)curr_pd +
- + 						  USB_CPPI41_DESC_ALIGN);
- + 		pd_addr += USB_CPPI41_DESC_ALIGN;
- + 	}
- + 
- + 	/* Configure the Tx channels */
- + 	for (i = 0, cppi_ch = cppi->tx_cppi_ch;
- + 	     i < ARRAY_SIZE(cppi->tx_cppi_ch); ++i, ++cppi_ch) {
- + 		const struct cppi41_tx_ch *tx_info;
- + 
- + 		memset(cppi_ch, 0, sizeof(struct cppi41_channel));
- + 		cppi_ch->transmit = 1;
- + 		cppi_ch->ch_num = i;
- + 		cppi_ch->channel.private_data = cppi;
- + 
- + 		/*
- + 		 * Extract the CPPI 4.1 DMA Tx channel configuration and
- + 		 * construct/store the Tx PD tag info field for later use...
- + 		 */
- + 		tx_info = cppi41_dma_block[cppi_info->dma_block].tx_ch_info
- + 			  + cppi_info->ep_dma_ch[i];
- + 		cppi_ch->src_queue = tx_info->tx_queue[0];
- + 		cppi_ch->tag_info = (tx_info->port_num <<
- + 				     CPPI41_SRC_TAG_PORT_NUM_SHIFT) |
- + 				    (tx_info->ch_num <<
- + 				     CPPI41_SRC_TAG_CH_NUM_SHIFT) |
- + 				    (tx_info->sub_ch_num <<
- + 				     CPPI41_SRC_TAG_SUB_CH_NUM_SHIFT);
- + 	}
- + 
- + 	/* Configure the Rx channels */
- + 	for (i = 0, cppi_ch = cppi->rx_cppi_ch;
- + 	     i < ARRAY_SIZE(cppi->rx_cppi_ch); ++i, ++cppi_ch) {
- + 		memset(cppi_ch, 0, sizeof(struct cppi41_channel));
- + 		cppi_ch->ch_num = i;
- + 		cppi_ch->channel.private_data = cppi;
- + 	}
- + 
- + 	/* Construct/store Tx PD packet info field for later use */
- + 	cppi->pkt_info = (CPPI41_PKT_TYPE_USB << CPPI41_PKT_TYPE_SHIFT) |
- + 			 (CPPI41_RETURN_LINKED << CPPI41_RETURN_POLICY_SHIFT);
- + 
- + 	/* Do necessary configuartion in hardware to get started */
- + 	reg_base = cppi->musb->ctrl_base;
- + 
- + 	/* Disable auto request mode */
- + 	musb_writel(reg_base, cppi->automode_reg_offs, 0);
- + 
- + 	/* Disable the CDC/RNDIS modes */
- + 	musb_writel(reg_base, USB_TX_MODE_REG, 0);
- + 	musb_writel(reg_base, USB_RX_MODE_REG, 0);
- + 
- + 	return 1;
- + 
- +  free_queue:
- + 	if (cppi41_queue_free(0, cppi->teardownQNum))
- + 		dev_dbg(musb->controller, "ERROR: failed to free teardown completion queue\n");
- + 
- +  free_mem_rgn:
- + 	if (cppi41_mem_rgn_free(cppi_info->q_mgr, cppi->pd_mem_rgn))
- + 		dev_dbg(musb->controller, "ERROR: failed to free queue manager memory region\n");
- + 
- +  free_pds:
- + 	dma_free_coherent(cppi->musb->controller,
- + 			  cppi->bd_size,
- + 			  cppi->pd_mem, cppi->pd_mem_phys);
- + 
- + 	return 0;
- + }
- + 
- + /**
- +  * cppi41_controller_stop - stop DMA controller
- +  * @controller: the controller
- +  *
- +  * De-initialize the DMA Controller as necessary.
- +  */
- + static int cppi41_controller_stop(struct dma_controller *controller)
- + {
- + 	struct cppi41 *cppi;
- + 	void __iomem *reg_base;
- + 	struct usb_cppi41_info *cppi_info;
- + 	struct musb *musb;
- + 
- + 	cppi = container_of(controller, struct cppi41, controller);
- + 	cppi_info = cppi->cppi_info;
- + 	musb = cppi->musb;
- + 
- + 	/* Free the teardown completion queue */
- + 	if (cppi41_queue_free(cppi_info->q_mgr, cppi->teardownQNum))
- + 		dev_dbg(musb->controller, "ERROR: failed to free teardown completion queue\n");
- + 
- + 	/*
- + 	 * Free the packet descriptor region allocated
- + 	 * for all Tx/Rx channels.
- + 	 */
- + 	if (cppi41_mem_rgn_free(cppi_info->q_mgr, cppi->pd_mem_rgn))
- + 		dev_dbg(musb->controller, "ERROR: failed to free queue manager memory region\n");
- + 
- + 	dma_free_coherent(cppi->musb->controller, cppi->bd_size,
- + 			  cppi->pd_mem, cppi->pd_mem_phys);
- + 
- + 	cppi->pd_mem = 0;
- + 	cppi->pd_mem_phys = 0;
- + 	cppi->pd_pool_head = 0;
- + 	cppi->bd_size = 0;
- + 
- + 	reg_base = cppi->musb->ctrl_base;
- + 
- + 	/* Disable auto request mode */
- + 	musb_writel(reg_base, cppi->automode_reg_offs, 0);
- + 
- + 	/* Disable the CDC/RNDIS modes */
- + 	musb_writel(reg_base, USB_TX_MODE_REG, 0);
- + 	musb_writel(reg_base, USB_RX_MODE_REG, 0);
- + 
- + 	return 1;
- + }
- + 
- + /**
- +  * cppi41_channel_alloc - allocate a CPPI channel for DMA.
- +  * @controller: the controller
- +  * @ep:		the endpoint
- +  * @is_tx:	1 for Tx channel, 0 for Rx channel
- +  *
- +  * With CPPI, channels are bound to each transfer direction of a non-control
- +  * endpoint, so allocating (and deallocating) is mostly a way to notice bad
- +  * housekeeping on the software side.  We assume the IRQs are always active.
- +  */
- + static struct dma_channel *cppi41_channel_alloc(struct dma_controller
- + 						*controller,
- + 						struct musb_hw_ep *ep, u8 is_tx)
- + {
- + 	struct cppi41 *cppi;
- + 	struct cppi41_channel  *cppi_ch;
- + 	u32 ch_num, ep_num = ep->epnum;
- + 	struct usb_cppi41_info *cppi_info;
- + 	struct musb *musb;
- + 
- + 	cppi = container_of(controller, struct cppi41, controller);
- + 	cppi_info = cppi->cppi_info;
- + 	musb = cppi->musb;
- + 
- + 	/* Remember, ep_num: 1 .. Max_EP, and CPPI ch_num: 0 .. Max_EP - 1 */
- + 	ch_num = ep_num - 1;
- + 
- + 	if (ep_num > USB_CPPI41_NUM_CH) {
- + 		dev_dbg(musb->controller, "No %cx DMA channel for EP%d\n",
- + 		    is_tx ? 'T' : 'R', ep_num);
- + 		return NULL;
- + 	}
- + 
- + 	cppi_ch = (is_tx ? cppi->tx_cppi_ch : cppi->rx_cppi_ch) + ch_num;
- + 
- + 	/* As of now, just return the corresponding CPPI 4.1 channel handle */
- + 	if (is_tx) {
- + 		/* Initialize the CPPI 4.1 Tx DMA channel */
- + 		if (cppi41_tx_ch_init(&cppi_ch->dma_ch_obj,
- + 				      cppi_info->dma_block,
- + 				      cppi_info->ep_dma_ch[ch_num])) {
- + 			dev_dbg(musb->controller, "ERROR: cppi41_tx_ch_init failed for "
- + 			    "channel %d\n", ch_num);
- + 			return NULL;
- + 		}
- + 		/*
- + 		 * Teardown descriptors will be pushed to the dedicated
- + 		 * completion queue.
- + 		 */
- + 		cppi41_dma_ch_default_queue(&cppi_ch->dma_ch_obj,
- + 					    0, cppi->teardownQNum);
- + 	} else {
- + 		struct cppi41_rx_ch_cfg rx_cfg;
- + 		u8 q_mgr = cppi_info->q_mgr;
- + 		int i;
- + 
- + 		/* Initialize the CPPI 4.1 Rx DMA channel */
- + 		if (cppi41_rx_ch_init(&cppi_ch->dma_ch_obj,
- + 				      cppi_info->dma_block,
- + 				      cppi_info->ep_dma_ch[ch_num])) {
- + 			dev_dbg(musb->controller, "ERROR: cppi41_rx_ch_init failed\n");
- + 			return NULL;
- + 		}
- + 
- + 		if (cppi41_queue_alloc(CPPI41_FREE_DESC_BUF_QUEUE |
- + 				       CPPI41_UNASSIGNED_QUEUE,
- + 				       q_mgr, &cppi_ch->src_queue.q_num)) {
- + 			dev_dbg(musb->controller, "ERROR: cppi41_queue_alloc failed for "
- + 			    "free descriptor/buffer queue\n");
- + 			return NULL;
- + 		}
- + 		dev_dbg(musb->controller, "Allocated free descriptor/buffer queue %d in "
- + 		    "queue manager %d\n", cppi_ch->src_queue.q_num, q_mgr);
- + 
- + 		rx_cfg.default_desc_type = cppi41_rx_host_desc;
- + 		rx_cfg.sop_offset = 0;
- + 		rx_cfg.retry_starved = 1;
- + 		rx_cfg.rx_max_buf_cnt = 0;
- + 		rx_cfg.rx_queue.q_mgr = cppi_ch->src_queue.q_mgr = q_mgr;
- + 		rx_cfg.rx_queue.q_num = cppi_info->rx_comp_q[ch_num];
- + 		for (i = 0; i < 4; i++)
- + 			rx_cfg.cfg.host_pkt.fdb_queue[i] = cppi_ch->src_queue;
- + 		cppi41_rx_ch_configure(&cppi_ch->dma_ch_obj, &rx_cfg);
- + 	}
- + 
- + 	/* Initialize the CPPI 4.1 DMA source queue */
- + 	if (cppi41_queue_init(&cppi_ch->queue_obj, cppi_ch->src_queue.q_mgr,
- + 			       cppi_ch->src_queue.q_num)) {
- + 		dev_dbg(musb->controller, "ERROR: cppi41_queue_init failed for %s queue",
- + 		    is_tx ? "Tx" : "Rx free descriptor/buffer");
- + 		if (is_tx == 0 &&
- + 		    cppi41_queue_free(cppi_ch->src_queue.q_mgr,
- + 				      cppi_ch->src_queue.q_num))
- + 			dev_dbg(musb->controller, "ERROR: failed to free Rx descriptor/buffer "
- + 			    "queue\n");
- + 		 return NULL;
- + 	}
- + 
- + 	/* Enable the DMA channel */
- + 	cppi41_dma_ch_enable(&cppi_ch->dma_ch_obj);
- + 
- + 	if (cppi_ch->end_pt)
- + 		dev_dbg(musb->controller, "Re-allocating DMA %cx channel %d (%p)\n",
- + 		    is_tx ? 'T' : 'R', ch_num, cppi_ch);
- + 
- + 	cppi_ch->end_pt = ep;
- + 	cppi_ch->ch_num = ch_num;
- + 	cppi_ch->channel.status = MUSB_DMA_STATUS_FREE;
- + 	cppi_ch->channel.max_len = is_tx ?
- + 				CPPI41_TXDMA_MAXLEN : CPPI41_RXDMA_MAXLEN;
- + 
- + 	dev_dbg(musb->controller, "Allocated DMA %cx channel %d for EP%d\n", is_tx ? 'T' : 'R',
- + 	    ch_num, ep_num);
- + 
- + 	return &cppi_ch->channel;
- + }
- + 
- + /**
- +  * cppi41_channel_release - release a CPPI DMA channel
- +  * @channel: the channel
- +  */
- + static void cppi41_channel_release(struct dma_channel *channel)
- + {
- + 	struct cppi41_channel *cppi_ch;
- + 
- + 	/* REVISIT: for paranoia, check state and abort if needed... */
- + 	cppi_ch = container_of(channel, struct cppi41_channel, channel);
- + 
- + 	if (cppi_ch->end_pt == NULL)
- + 		printk(KERN_INFO "Releasing idle DMA channel %p\n", cppi_ch);
- + 
- + 	/* But for now, not its IRQ */
- + 	cppi_ch->end_pt = NULL;
- + 	channel->status = MUSB_DMA_STATUS_UNKNOWN;
- + 
- + 	cppi41_dma_ch_disable(&cppi_ch->dma_ch_obj);
- + 
- + 	/* De-allocate Rx free descriptior/buffer queue */
- + 	if (cppi_ch->transmit == 0 &&
- + 	    cppi41_queue_free(cppi_ch->src_queue.q_mgr,
- + 			      cppi_ch->src_queue.q_num))
- + 		printk(KERN_ERR "ERROR: failed to free Rx descriptor/buffer queue\n");
- + }
- + 
- + static void cppi41_mode_update(struct cppi41_channel *cppi_ch, u8 mode)
- + {
- + 	if (mode != cppi_ch->dma_mode) {
- + 		struct cppi41 *cppi = cppi_ch->channel.private_data;
- + 		void *__iomem reg_base = cppi->musb->ctrl_base;
- + 		u32 reg_val;
- + 		u8 ep_num = cppi_ch->ch_num + 1;
- + 
- + 		if (cppi_ch->transmit) {
- + 			reg_val = musb_readl(reg_base, USB_TX_MODE_REG);
- + 			reg_val &= ~USB_TX_MODE_MASK(ep_num);
- + 			reg_val |= mode << USB_TX_MODE_SHIFT(ep_num);
- + 			musb_writel(reg_base, USB_TX_MODE_REG, reg_val);
- + 		} else {
- + 			reg_val = musb_readl(reg_base, USB_RX_MODE_REG);
- + 			reg_val &= ~USB_RX_MODE_MASK(ep_num);
- + 			reg_val |= mode << USB_RX_MODE_SHIFT(ep_num);
- + 			musb_writel(reg_base, USB_RX_MODE_REG, reg_val);
- + 		}
- + 		cppi_ch->dma_mode = mode;
- + 	}
- + }
- + 
- + /*
- +  * CPPI 4.1 Tx:
- +  * ============
- +  * Tx is a lot more reasonable than Rx: RNDIS mode seems to behave well except
- +  * how it handles the exactly-N-packets case. It appears that there's a hiccup
- +  * in that case (maybe the DMA completes before a ZLP gets written?) boiling
- +  * down to not being able to rely on the XFER DMA writing any terminating zero
- +  * length packet before the next transfer is started...
- +  *
- +  * The generic RNDIS mode does not have this misfeature, so we prefer using it
- +  * instead.  We then send the terminating ZLP *explictly* using DMA instead of
- +  * doing it by PIO after an IRQ.
- +  *
- +  */
- + 
- + /**
- +  * cppi41_next_tx_segment - DMA write for the next chunk of a buffer
- +  * @tx_ch:	Tx channel
- +  *
- +  * Context: controller IRQ-locked
- +  */
- + static unsigned cppi41_next_tx_segment(struct cppi41_channel *tx_ch)
- + {
- + 	struct cppi41 *cppi = tx_ch->channel.private_data;
- + 	struct musb *musb = cppi->musb;
- + 	struct usb_pkt_desc *curr_pd;
- + 	u32 length = tx_ch->length - tx_ch->curr_offset;
- + 	u32 pkt_size = tx_ch->pkt_size;
- + 	unsigned num_pds, n;
- + 	struct usb_cppi41_info *cppi_info = cppi->cppi_info;
- + 	u16 q_mgr = cppi_info->q_mgr;
- + 	u16 tx_comp_q = cppi_info->tx_comp_q[tx_ch->ch_num];
- + 	u8 en_bd_intr = cppi->en_bd_intr;
- + 	u8 is_isoc = 0;
- + 	struct musb_hw_ep *hw_ep = cppi->musb->endpoints + tx_ch->end_pt->epnum;
- + 	int xfer_type = hw_ep->xfer_type;
- + 
- + 	/*
- + 	 * Tx can use the generic RNDIS mode where we can probably fit this
- + 	 * transfer in one PD and one IRQ.  The only time we would NOT want
- + 	 * to use it is when the hardware constraints prevent it...
- + 	 */
- + 	if ((pkt_size & 0x3f) == 0) {
- + 		num_pds  = length ? 1 : 0;
- + 		cppi41_mode_update(tx_ch, USB_GENERIC_RNDIS_MODE);
- + 	} else {
- + 		num_pds  = (length + pkt_size - 1) / pkt_size;
- + 		cppi41_mode_update(tx_ch, USB_TRANSPARENT_MODE);
- + 	}
- + 
- + 	pkt_size = length;
- + 	/*
- + 	 * If length of transmit buffer is 0 or a multiple of the endpoint size,
- + 	 * then send the zero length packet.
- + 	 */
- + 	if (!length || (tx_ch->transfer_mode && length % pkt_size == 0))
- + 		num_pds++;
- + 
- + 	dev_dbg(musb->controller, "TX DMA%u, %s, maxpkt %u, %u PDs, addr %#x, len %u\n",
- + 	    tx_ch->ch_num, tx_ch->dma_mode ? "accelerated" : "transparent",
- + 	    pkt_size, num_pds, tx_ch->start_addr + tx_ch->curr_offset, length);
- + 
- + 	if (xfer_type  == USB_ENDPOINT_XFER_ISOC)
- + 		is_isoc = 1;
- + 
- + 	if (is_isoc && cppi->txfifo_intr_enable && (length <= tx_ch->pkt_size))
- + 		tx_ch->txfifo_intr_enable = 1;
- + 
- + 	for (n = 0; n < num_pds; n++) {
- + 		struct cppi41_host_pkt_desc *hw_desc;
- + 
- + 		/* Get Tx host packet descriptor from the free pool */
- + 		curr_pd = usb_get_free_pd(cppi);
- + 		if (curr_pd == NULL) {
- + 			dev_dbg(musb->controller, "No Tx PDs\n");
- + 			break;
- + 		}
- + 
- + 		if (length < pkt_size)
- + 			pkt_size = length;
- + 
- + 		hw_desc = &curr_pd->hw_desc;
- + 		hw_desc->desc_info = (CPPI41_DESC_TYPE_HOST <<
- + 				      CPPI41_DESC_TYPE_SHIFT) | pkt_size;
- + 		hw_desc->tag_info = tx_ch->tag_info;
- + 		hw_desc->pkt_info = cppi->pkt_info;
- + 		hw_desc->pkt_info |= ((q_mgr << CPPI41_RETURN_QMGR_SHIFT) |
- + 				(tx_comp_q << CPPI41_RETURN_QNUM_SHIFT));
- + 
- + 		hw_desc->buf_ptr = tx_ch->start_addr + tx_ch->curr_offset;
- + 		hw_desc->buf_len = pkt_size;
- + 		hw_desc->next_desc_ptr = 0;
- + 		hw_desc->orig_buf_len = pkt_size;
- + 
- + 		curr_pd->ch_num = tx_ch->ch_num;
- + 		curr_pd->ep_num = tx_ch->end_pt->epnum;
- + 
- + 		tx_ch->curr_offset += pkt_size;
- + 		length -= pkt_size;
- + 
- + 		if (pkt_size == 0)
- + 			tx_ch->zlp_queued = 1;
- + 
- + 		if (en_bd_intr)
- + 			hw_desc->orig_buf_len |= CPPI41_PKT_INTR_FLAG;
- + 
- + 		dev_dbg(musb->controller, "TX PD %p: buf %08x, len %08x, pkt info %08x\n", curr_pd,
- + 		    hw_desc->buf_ptr, hw_desc->buf_len, hw_desc->pkt_info);
- + 
- + 		/* make sure descriptor details are updated to memory*/
- + 		dsb();
- + 
- + 		/* enable tx fifo empty interrupt */
- + 		if (tx_ch->txfifo_intr_enable) {
- + 			dev_dbg(musb->controller, "txs(%p %d) enable txFintr\n",
- + 				curr_pd, hw_desc->orig_buf_len &
- + 					~CPPI41_PKT_INTR_FLAG);
- + 			txfifoempty_int_enable(cppi->musb, curr_pd->ep_num);
- + 		}
- + 
- + 		cppi41_queue_push(&tx_ch->queue_obj, curr_pd->dma_addr,
- + 				  USB_CPPI41_DESC_ALIGN, pkt_size);
- + 	}
- + 
- + 	return n;
- + }
- + 
- + static void cppi41_autoreq_update(struct cppi41_channel *rx_ch, u8 autoreq)
- + {
- + 	struct cppi41 *cppi = rx_ch->channel.private_data;
- + 
- + 	if (is_host_active(cppi->musb) &&
- + 	    autoreq != rx_ch->autoreq) {
- + 		void *__iomem reg_base = cppi->musb->ctrl_base;
- + 		u32 reg_val = musb_readl(reg_base, cppi->automode_reg_offs);
- + 		u8 ep_num = rx_ch->ch_num + 1;
- + 
- + 		reg_val &= ~USB_RX_AUTOREQ_MASK(ep_num);
- + 		reg_val |= autoreq << USB_RX_AUTOREQ_SHIFT(ep_num);
- + 
- + 		musb_writel(reg_base, cppi->automode_reg_offs, reg_val);
- + 		rx_ch->autoreq = autoreq;
- + 	}
- + }
- + 
- + static void cppi41_set_ep_size(struct cppi41_channel *rx_ch, u32 pkt_size)
- + {
- + 	struct cppi41 *cppi = rx_ch->channel.private_data;
- + 	void *__iomem reg_base = cppi->musb->ctrl_base;
- + 	u8 ep_num = rx_ch->ch_num + 1;
- + 	u32 res = pkt_size % 64;
- + 
- + 	/* epsize register must be multiple of 64 */
- + 	pkt_size += res ? (64 - res) : res;
- + 
- + 	musb_writel(reg_base, USB_GENERIC_RNDIS_EP_SIZE_REG(ep_num), pkt_size);
- + }
- + 
- + /*
- +  * CPPI 4.1 Rx:
- +  * ============
- +  * Consider a 1KB bulk Rx buffer in two scenarios: (a) it's fed two 300 byte
- +  * packets back-to-back, and (b) it's fed two 512 byte packets back-to-back.
- +  * (Full speed transfers have similar scenarios.)
- +  *
- +  * The correct behavior for Linux is that (a) fills the buffer with 300 bytes,
- +  * and the next packet goes into a buffer that's queued later; while (b) fills
- +  * the buffer with 1024 bytes.  How to do that with accelerated DMA modes?
- +  *
- +  * Rx queues in RNDIS mode (one single BD) handle (a) correctly but (b) loses
- +  * BADLY because nothing (!) happens when that second packet fills the buffer,
- +  * much less when a third one arrives -- which makes it not a "true" RNDIS mode.
- +  * In the RNDIS protocol short-packet termination is optional, and it's fine if
- +  * the peripherals (not hosts!) pad the messages out to end of buffer. Standard
- +  * PCI host controller DMA descriptors implement that mode by default... which
- +  * is no accident.
- +  *
- +  * Generic RNDIS mode is the only way to reliably make both cases work.  This
- +  * mode is identical to the "normal" RNDIS mode except for the case where the
- +  * last packet of the segment matches the max USB packet size -- in this case,
- +  * the packet will be closed when a value (0x10000 max) in the Generic RNDIS
- +  * EP Size register is reached.  This mode will work for the network drivers
- +  * (CDC/RNDIS) as well as for the mass storage drivers where there is no short
- +  * packet.
- +  *
- +  * BUT we can only use non-transparent modes when USB packet size is a multiple
- +  * of 64 bytes. Let's see what happens when  this is not the case...
- +  *
- +  * Rx queues (2 BDs with 512 bytes each) have converse problems to RNDIS mode:
- +  * (b) is handled right but (a) loses badly.  DMA doesn't stop after receiving
- +  * a short packet and processes both of those PDs; so both packets are loaded
- +  * into the buffer (with 212 byte gap between them), and the next buffer queued
- +  * will NOT get its 300 bytes of data.  Even in the case when there should be
- +  * no short packets (URB_SHORT_NOT_OK is set), queueing several packets in the
- +  * host mode doesn't win us anything since we have to manually "prod" the Rx
- +  * process after each packet is received by setting ReqPkt bit in endpoint's
- +  * RXCSR; in the peripheral mode without short packets, queueing could be used
- +  * BUT we'll have to *teardown* the channel if a short packet still arrives in
- +  * the peripheral mode, and to "collect" the left-over packet descriptors from
- +  * the free descriptor/buffer queue in both cases...
- +  *
- +  * One BD at a time is the only way to make make both cases work reliably, with
- +  * software handling both cases correctly, at the significant penalty of needing
- +  * an IRQ per packet.  (The lack of I/O overlap can be slightly ameliorated by
- +  * enabling double buffering.)
- +  *
- +  * There seems to be no way to identify for sure the cases where the CDC mode
- +  * is appropriate...
- +  *
- +  */
- + 
- + /**
- +  * cppi41_next_rx_segment - DMA read for the next chunk of a buffer
- +  * @rx_ch:	Rx channel
- +  *
- +  * Context: controller IRQ-locked
- +  *
- +  * NOTE: In the transparent mode, we have to queue one packet at a time since:
- +  *	 - we must avoid starting reception of another packet after receiving
- +  *	   a short packet;
- +  *	 - in host mode we have to set ReqPkt bit in the endpoint's RXCSR after
- +  *	   receiving each packet but the last one... ugly!
- +  */
- + static unsigned cppi41_next_rx_segment(struct cppi41_channel *rx_ch)
- + {
- + 	struct cppi41 *cppi = rx_ch->channel.private_data;
- + 	struct musb *musb = cppi->musb;
- + 	struct usb_pkt_desc *curr_pd;
- + 	struct cppi41_host_pkt_desc *hw_desc;
- + 	u32 length = rx_ch->length - rx_ch->curr_offset;
- + 	u32 pkt_size = rx_ch->pkt_size;
- + 	u32 max_rx_transfer_size = 64 * 1024;
- + 	u32 i, n_bd , pkt_len;
- + 	struct usb_gadget_driver *gadget_driver;
- + 	u8 en_bd_intr = cppi->en_bd_intr, mode;
- + 
- + 	if (is_peripheral_active(cppi->musb)) {
- + 		/* TODO: temporary fix for CDC/RNDIS which needs to be in
- + 		 * GENERIC_RNDIS mode. Without this RNDIS gadget taking
- + 		 * more then 2K ms for a 64 byte pings.
- + 		 */
- + 		gadget_driver = cppi->musb->gadget_driver;
- + 
- + 		pkt_len = rx_ch->pkt_size;
- + 		mode = USB_GENERIC_RNDIS_MODE;
- + 		if (!strcmp(gadget_driver->driver.name, "g_file_storage") ||
- + 			!strcmp(gadget_driver->driver.name, "g_mass_storage")) {
- + 			if (cppi->inf_mode && length > pkt_len) {
- + 				pkt_len = 0;
- + 				length = length - rx_ch->pkt_size;
- + 				cppi41_rx_ch_set_maxbufcnt(&rx_ch->dma_ch_obj,
- + 					DMA_CH_RX_MAX_BUF_CNT_1);
- + 				rx_ch->inf_mode = 1;
- + 			} else {
- + 				max_rx_transfer_size = rx_ch->pkt_size;
- + 				mode = USB_TRANSPARENT_MODE;
- + 			}
- + 		} else
- + 			if (rx_ch->length < max_rx_transfer_size)
- + 				pkt_len = rx_ch->length;
- + 
- + 		if (mode != USB_TRANSPARENT_MODE)
- + 			cppi41_set_ep_size(rx_ch, pkt_len);
- + 		cppi41_mode_update(rx_ch, mode);
- + 	} else {
- + 		/*
- + 		 * Rx can use the generic RNDIS mode where we can
- + 		 * probably fit this transfer in one PD and one IRQ
- + 		 * (or two with a short packet).
- + 		 */
- + 		if (cppi->cppi_info->grndis_for_host_rx &&
- + 					(pkt_size & 0x3f) == 0) {
- + 			cppi41_mode_update(rx_ch, USB_GENERIC_RNDIS_MODE);
- + 			cppi41_autoreq_update(rx_ch, USB_AUTOREQ_ALL_BUT_EOP);
- + 
- + 			pkt_size = (length > 0x10000) ? 0x10000 : length;
- + 			cppi41_set_ep_size(rx_ch, pkt_size);
- + 			mode = USB_GENERIC_RNDIS_MODE;
- + 		} else {
- + 			cppi41_mode_update(rx_ch, USB_TRANSPARENT_MODE);
- + 			cppi41_autoreq_update(rx_ch, USB_NO_AUTOREQ);
- + 			max_rx_transfer_size = rx_ch->hb_mult * rx_ch->pkt_size;
- + 			mode = USB_TRANSPARENT_MODE;
- + 		}
- + 	}
- + 
- + 	dev_dbg(musb->controller, "RX DMA%u, %s, maxpkt %u, addr %#x, rec'd %u/%u\n",
- + 	    rx_ch->ch_num, rx_ch->dma_mode ? "accelerated" : "transparent",
- + 	    pkt_size, rx_ch->start_addr + rx_ch->curr_offset,
- + 	    rx_ch->curr_offset, rx_ch->length);
- + 
- + 	/* calculate number of bd required */
- + 	if (is_host_active(cppi->musb) && (mode == USB_TRANSPARENT_MODE))
- + 		n_bd = 1;
- + 	else
- + 		n_bd = (length + max_rx_transfer_size - 1)/max_rx_transfer_size;
- + 
- + 	for (i = 0; i < n_bd ; ++i) {
- + 		/* Get Rx packet descriptor from the free pool */
- + 		curr_pd = usb_get_free_pd(cppi);
- + 		if (curr_pd == NULL) {
- + 			/* Shouldn't ever happen! */
- + 			dev_dbg(musb->controller, "No Rx PDs\n");
- + 			goto sched;
- + 		}
- + 
- + 		pkt_len =
- + 		(length > max_rx_transfer_size) ? max_rx_transfer_size : length;
- + 
- + 		hw_desc = &curr_pd->hw_desc;
- + 		hw_desc->desc_info = (CPPI41_DESC_TYPE_HOST <<
- + 				      CPPI41_DESC_TYPE_SHIFT);
- + 		hw_desc->orig_buf_ptr = rx_ch->start_addr + rx_ch->curr_offset;
- + 		hw_desc->orig_buf_len = pkt_len;
- + 
- + 		/* buf_len field of buffer descriptor updated by dma
- + 		 * after reception of data is completed
- + 		 */
- + 		hw_desc->buf_len = 0;
- + 
- + 		curr_pd->ch_num = rx_ch->ch_num;
- + 		curr_pd->ep_num = rx_ch->end_pt->epnum;
- + 
- + 		curr_pd->eop = (length -= pkt_len) ? 0 : 1;
- + 		rx_ch->curr_offset += pkt_len;
- + 
- + 		if (en_bd_intr)
- + 			hw_desc->orig_buf_len |= CPPI41_PKT_INTR_FLAG;
- + 
- + 		/* make sure descriptor details are updated to memory*/
- + 		dsb();
- + 
- + 		/*
- + 		 * Push the free Rx packet descriptor
- + 		 * to the free descriptor/buffer queue.
- + 		 */
- + 		cppi41_queue_push(&rx_ch->queue_obj, curr_pd->dma_addr,
- + 			USB_CPPI41_DESC_ALIGN, 0);
- + 	}
- + 
- + sched:
- + 	/*
- + 	 * HCD arranged ReqPkt for the first packet.
- + 	 * We arrange it for all but the last one.
- + 	 */
- + 	if (is_host_active(cppi->musb) && rx_ch->channel.actual_len) {
- + 		void __iomem *epio = rx_ch->end_pt->regs;
- + 		u16 csr = musb_readw(epio, MUSB_RXCSR);
- + 
- + 		if (musb->datatog_fix) {
- + 			u8 curr_toggle;
- + 			curr_toggle = (csr & MUSB_RXCSR_H_DATATOGGLE) ? 1 : 0;
- + 
- + 			/* check if data toggle bit got out of sync */
- + 			if (curr_toggle == rx_ch->end_pt->prev_toggle) {
- + 				dev_dbg(musb->controller,
- + 				"Data toggle same as previous (=%d) on ep%d\n",
- + 					curr_toggle, rx_ch->end_pt->epnum);
- + 
- + 				csr |= MUSB_RXCSR_H_DATATOGGLE |
- + 					MUSB_RXCSR_H_WR_DATATOGGLE;
- + 				musb_writew(epio, MUSB_RXCSR, csr);
- + 
- + 				rx_ch->end_pt->prev_toggle = !curr_toggle;
- + 			} else {
- + 				rx_ch->end_pt->prev_toggle = curr_toggle;
- + 			}
- + 			csr = musb_readw(epio, MUSB_RXCSR);
- + 		}
- + 
- + 		csr |= MUSB_RXCSR_H_REQPKT | MUSB_RXCSR_H_WZC_BITS;
- + 		musb_writew(epio, MUSB_RXCSR, csr);
- + 	}
- + 
- + 	/* enable schedular if not enabled */
- + 	if (is_peripheral_active(cppi->musb) && (n_bd > 0))
- + 		cppi41_schedtbl_add_dma_ch(0, 0, rx_ch->ch_num, 0);
- + 	return 1;
- + }
- + 
- + /**
- +  * cppi41_channel_program - program channel for data transfer
- +  * @channel:	the channel
- +  * @maxpacket:	max packet size
- +  * @mode:	for Rx, 1 unless the USB protocol driver promised to treat
- +  *		all short reads as errors and kick in high level fault recovery;
- +  *		for Tx, 0 unless the protocol driver _requires_ short-packet
- +  *		termination mode
- +  * @dma_addr:	DMA address of buffer
- +  * @length:	length of buffer
- +  *
- +  * Context: controller IRQ-locked
- +  */
- + static int cppi41_channel_program(struct dma_channel *channel,	u16 maxpacket,
- + 				  u8 mode, dma_addr_t dma_addr, u32 length)
- + {
- + 	struct cppi41_channel *cppi_ch;
- + 	unsigned queued;
- + 
- + 	cppi_ch = container_of(channel, struct cppi41_channel, channel);
- + 
- + 	switch (channel->status) {
- + 	case MUSB_DMA_STATUS_BUS_ABORT:
- + 	case MUSB_DMA_STATUS_CORE_ABORT:
- + 		/* Fault IRQ handler should have handled cleanup */
- + 		WARNING("%cx DMA%d not cleaned up after abort!\n",
- + 			cppi_ch->transmit ? 'T' : 'R', cppi_ch->ch_num);
- + 		break;
- + 	case MUSB_DMA_STATUS_BUSY:
- + 		WARNING("Program active channel? %cx DMA%d\n",
- + 			cppi_ch->transmit ? 'T' : 'R', cppi_ch->ch_num);
- + 		break;
- + 	case MUSB_DMA_STATUS_UNKNOWN:
- + 		WARNING("%cx DMA%d not allocated!\n",
- + 		    cppi_ch->transmit ? 'T' : 'R', cppi_ch->ch_num);
- + 		return 0;
- + 	case MUSB_DMA_STATUS_FREE:
- + 		break;
- + 	}
- + 
- + 	channel->status = MUSB_DMA_STATUS_BUSY;
- + 
- + 	/* Set the transfer parameters, then queue up the first segment */
- + 	cppi_ch->start_addr = dma_addr;
- + 	cppi_ch->curr_offset = 0;
- + 	cppi_ch->hb_mult = (maxpacket >> 11) & 0x03;
- + 	cppi_ch->pkt_size = maxpacket & 0x7ff;
- + 	cppi_ch->length = length;
- + 	cppi_ch->transfer_mode = mode;
- + 	cppi_ch->zlp_queued = 0;
- + 	cppi_ch->channel.actual_len = 0;
- + 
- + 	/* Tx or Rx channel? */
- + 	if (cppi_ch->transmit)
- + 		queued = cppi41_next_tx_segment(cppi_ch);
- + 	else
- + 		queued = cppi41_next_rx_segment(cppi_ch);
- + 
- + 	return	queued > 0;
- + }
- + 
- + static struct usb_pkt_desc *usb_get_pd_ptr(struct cppi41 *cppi,
- + 					   unsigned long pd_addr)
- + {
- + 	if (pd_addr >= cppi->pd_mem_phys && pd_addr < cppi->pd_mem_phys +
- + 	    USB_CPPI41_MAX_PD * USB_CPPI41_DESC_ALIGN)
- + 		return pd_addr - cppi->pd_mem_phys + cppi->pd_mem;
- + 	else
- + 		return NULL;
- + }
- + 
- + static int usb_check_teardown(struct cppi41_channel *cppi_ch,
- + 			      unsigned long pd_addr)
- + {
- + 	u32 info;
- + 	struct cppi41 *cppi = cppi_ch->channel.private_data;
- + 	struct usb_cppi41_info *cppi_info = cppi->cppi_info;
- + 	struct musb *musb = cppi->musb;
- + 
- + 	if (cppi41_get_teardown_info(pd_addr, &info)) {
- + 		dev_dbg(musb->controller, "ERROR: not a teardown descriptor\n");
- + 		return 0;
- + 	}
- + 
- + 	if ((info & CPPI41_TEARDOWN_TX_RX_MASK) ==
- + 	    (!cppi_ch->transmit << CPPI41_TEARDOWN_TX_RX_SHIFT) &&
- + 	    (info & CPPI41_TEARDOWN_DMA_NUM_MASK) ==
- + 	    (cppi_info->dma_block << CPPI41_TEARDOWN_DMA_NUM_SHIFT) &&
- + 	    (info & CPPI41_TEARDOWN_CHAN_NUM_MASK) ==
- + 	    (cppi_info->ep_dma_ch[cppi_ch->ch_num] <<
- + 	     CPPI41_TEARDOWN_CHAN_NUM_SHIFT))
- + 		return 1;
- + 
- + 	dev_dbg(musb->controller, "ERROR: unexpected values in teardown descriptor\n");
- + 	return 0;
- + }
- + 
- + /*
- +  * We can't handle the channel teardown via the default completion queue in
- +  * context of the controller IRQ-locked, so we use the dedicated teardown
- +  * completion queue which we can just poll for a teardown descriptor, not
- +  * interfering with the Tx completion queue processing.
- +  */
- + static void usb_tx_ch_teardown(struct cppi41_channel *tx_ch)
- + {
- + 	struct cppi41 *cppi = tx_ch->channel.private_data;
- + 	struct musb *musb = cppi->musb;
- + 	void __iomem *reg_base = musb->ctrl_base;
- + 	u32 td_reg, timeout = 0xfffff;
- + 	u8 ep_num = tx_ch->ch_num + 1;
- + 	unsigned long pd_addr;
- + 	struct cppi41_queue_obj tx_queue_obj;
- + 	struct usb_cppi41_info *cppi_info;
- + 
- + 	/* Initiate teardown for Tx DMA channel */
- + 	cppi41_dma_ch_teardown(&tx_ch->dma_ch_obj);
- + 
- + 	/* Wait for a descriptor to be queued and pop it... */
- + 	do {
- + 		td_reg  = musb_readl(reg_base, cppi->teardown_reg_offs);
- + 		td_reg |= USB_TX_TDOWN_MASK(ep_num);
- + 		musb_writel(reg_base, cppi->teardown_reg_offs, td_reg);
- + 
- + 		pd_addr = cppi41_queue_pop(&cppi->queue_obj);
- + 	} while (!pd_addr && timeout--);
- + 
- + 	if (pd_addr) {
- + 
- + 		dev_dbg(musb->controller, "Descriptor (%08lx) popped from teardown completion "
- + 			"queue\n", pd_addr);
- + 
- + 		if (usb_check_teardown(tx_ch, pd_addr)) {
- + 			dev_dbg(musb->controller, "Teardown Desc (%lx) rcvd\n", pd_addr);
- + 		} else
- + 			ERR("Invalid PD(%08lx)popped from TearDn completion"
- + 				"queue\n", pd_addr);
- + 	} else {
- + 		if (timeout <= 0)
- + 			ERR("Teardown Desc not rcvd\n");
- + 	}
- + 
- + 	/* read the tx completion queue and remove
- + 	 * completion bd if any
- + 	 */
- + 	cppi_info = cppi->cppi_info;
- + 	if (cppi41_queue_init(&tx_queue_obj, cppi_info->q_mgr,
- + 			      cppi_info->tx_comp_q[tx_ch->ch_num])) {
- + 		ERR("ERROR: cppi41_queue_init failed for "
- + 		    "Tx completion queue");
- + 		return;
- + 	}
- + 
- + 	while ((pd_addr = cppi41_queue_pop(&tx_queue_obj)) != 0) {
- + 		struct usb_pkt_desc *curr_pd;
- + 
- + 		curr_pd = usb_get_pd_ptr(cppi, pd_addr);
- + 		if (curr_pd == NULL) {
- + 			ERR("Invalid PD popped from Tx completion queue\n");
- + 			continue;
- + 		}
- + 
- + 		dev_dbg(musb->controller, "Tx-PD(%p) popped from completion queue\n", curr_pd);
- + 		dev_dbg(musb->controller, "ch(%d)epnum(%d)len(%d)\n", curr_pd->ch_num,
- + 			curr_pd->ep_num, curr_pd->hw_desc.buf_len);
- + 
- + 		usb_put_free_pd(cppi, curr_pd);
- + 	}
- + }
- + 
- + /*
- +  * For Rx DMA channels, the situation is more complex: there's only a single
- +  * completion queue for all our needs, so we have to temporarily redirect the
- +  * completed descriptors to our teardown completion queue, with a possibility
- +  * of a completed packet landing there as well...
- +  */
- + static void usb_rx_ch_teardown(struct cppi41_channel *rx_ch)
- + {
- + 	struct cppi41 *cppi = rx_ch->channel.private_data;
- + 	struct musb *musb = cppi->musb;
- + 	struct usb_cppi41_info *cppi_info = cppi->cppi_info;
- + 	u32 timeout = 0xfffff, pd_addr;
- + 	struct cppi41_queue_obj rx_queue_obj;
- + 
- + 	cppi41_dma_ch_default_queue(&rx_ch->dma_ch_obj, 0, cppi->teardownQNum);
- + 
- + 	/* Initiate teardown for Rx DMA channel */
- + 	cppi41_dma_ch_teardown(&rx_ch->dma_ch_obj);
- + 
- + 	do {
- + 		struct usb_pkt_desc *curr_pd;
- + 		unsigned long pd_addr;
- + 
- + 		/* Wait for a descriptor to be queued and pop it... */
- + 		do {
- + 			pd_addr = cppi41_queue_pop(&cppi->queue_obj);
- + 		} while (!pd_addr && timeout--);
- + 
- + 		if (timeout <= 0 || !pd_addr) {
- + 			ERR("teardown Desc not found\n");
- + 			break;
- + 		}
- + 
- + 		dev_dbg(musb->controller, "Descriptor (%08lx) popped from teardown completion "
- + 			"queue\n", pd_addr);
- + 
- + 		/*
- + 		 * We might have popped a completed Rx PD, so check if the
- + 		 * physical address is within the PD region first.  If it's
- + 		 * not the case, it must be a teardown descriptor...
- + 		 * */
- + 		curr_pd = usb_get_pd_ptr(cppi, pd_addr);
- + 		if (curr_pd == NULL) {
- + 			if (usb_check_teardown(rx_ch, pd_addr))
- + 				break;
- + 			continue;
- + 		}
- + 
- + 		/* Paranoia: check if PD is from the right channel... */
- + 		if (curr_pd->ch_num != rx_ch->ch_num) {
- + 			ERR("Unexpected channel %d in Rx PD\n",
- + 			    curr_pd->ch_num);
- + 			continue;
- + 		}
- + 
- + 		/* Extract the buffer length from the completed PD */
- + 		rx_ch->channel.actual_len += curr_pd->hw_desc.buf_len;
- + 
- + 		/*
- + 		 * Return Rx PDs to the software list --
- + 		 * this is protected by critical section.
- + 		 */
- + 		usb_put_free_pd(cppi, curr_pd);
- + 	} while (0);
- + 
- + 	/* read the rx completion queue and remove
- + 	 * completion bd if any
- + 	 */
- + 	if (cppi41_queue_init(&rx_queue_obj, cppi_info->q_mgr,
- + 			      cppi_info->rx_comp_q[rx_ch->ch_num])) {
- + 		ERR("ERROR: cppi41_queue_init failed for "
- + 		    "Rx completion queue");
- + 		return;
- + 	}
- + 
- + 	while ((pd_addr = cppi41_queue_pop(&rx_queue_obj)) != 0) {
- + 		struct usb_pkt_desc *curr_pd;
- + 
- + 		curr_pd = usb_get_pd_ptr(cppi, pd_addr);
- + 		if (curr_pd == NULL) {
- + 			ERR("Invalid PD popped from Rx completion queue\n");
- + 			continue;
- + 		}
- + 
- + 		dev_dbg(musb->controller, "Rx-PD(%p) popped from completion queue\n", curr_pd);
- + 		dev_dbg(musb->controller, "ch(%d)epnum(%d)len(%d)\n", curr_pd->ch_num,
- + 			curr_pd->ep_num, curr_pd->hw_desc.buf_len);
- + 
- + 		usb_put_free_pd(cppi, curr_pd);
- + 	}
- + 
- + 	/* Now restore the default Rx completion queue... */
- + 	cppi41_dma_ch_default_queue(&rx_ch->dma_ch_obj, cppi_info->q_mgr,
- + 				    cppi_info->rx_comp_q[rx_ch->ch_num]);
- + }
- + 
- + /*
- +  * cppi41_channel_abort
- +  *
- +  * Context: controller IRQ-locked, endpoint selected.
- +  */
- + static int cppi41_channel_abort(struct dma_channel *channel)
- + {
- + 	struct cppi41 *cppi;
- + 	struct cppi41_channel *cppi_ch;
- + 	struct musb  *musb;
- + 	void __iomem *reg_base, *epio;
- + 	unsigned long pd_addr;
- + 	u32 csr, td_reg;
- + 	u8 ch_num, ep_num, i;
- + 
- + 	cppi_ch = container_of(channel, struct cppi41_channel, channel);
- + 	ch_num = cppi_ch->ch_num;
- + 	cppi = cppi_ch->channel.private_data;
- + 	musb = cppi->musb;
- + 
- + 	switch (channel->status) {
- + 	case MUSB_DMA_STATUS_BUS_ABORT:
- + 	case MUSB_DMA_STATUS_CORE_ABORT:
- + 		/* From Rx or Tx fault IRQ handler */
- + 	case MUSB_DMA_STATUS_BUSY:
- + 		/* The hardware needs shutting down... */
- + 		dprintk("%s: DMA busy, status = %x\n",
- + 			__func__, channel->status);
- + 		break;
- + 	case MUSB_DMA_STATUS_UNKNOWN:
- + 		dev_dbg(musb->controller, "%cx DMA%d not allocated\n",
- + 		    cppi_ch->transmit ? 'T' : 'R', ch_num);
- + 		/* FALLTHROUGH */
- + 	case MUSB_DMA_STATUS_FREE:
- + 		return 0;
- + 	}
- + 
- + 	reg_base = musb->ctrl_base;
- + 	epio = cppi_ch->end_pt->regs;
- + 	ep_num = ch_num + 1;
- + 
- + #ifdef DEBUG_CPPI_TD
- + 	printk("Before teardown:");
- + 	print_pd_list(cppi->pd_pool_head);
- + #endif
- + 
- + 	if (cppi_ch->transmit) {
- + 		dprintk("Tx channel teardown, cppi_ch = %p\n", cppi_ch);
- + 
- + 		/* disable the DMAreq before teardown */
- + 		csr  = musb_readw(epio, MUSB_TXCSR);
- + 		csr &= ~MUSB_TXCSR_DMAENAB;
- + 		musb_writew(epio, MUSB_TXCSR, csr);
- + 
- + 		cppi_ch->tx_complete = 0;
- + 		cppi_ch->txf_complete = 0;
- + 		/* Tear down Tx DMA channel */
- + 		usb_tx_ch_teardown(cppi_ch);
- + 
- + 		/* Issue CPPI FIFO teardown for Tx channel */
- + 		td_reg  = musb_readl(reg_base, cppi->teardown_reg_offs);
- + 		td_reg |= USB_TX_TDOWN_MASK(ep_num);
- + 		musb_writel(reg_base, cppi->teardown_reg_offs, td_reg);
- + 
- + 		/* Flush FIFO of the endpoint */
- + 		for (i = 0; i < 2; ++i) {
- + 			csr  = musb_readw(epio, MUSB_TXCSR);
- + 			if (csr & MUSB_TXCSR_TXPKTRDY) {
- + 				csr |= MUSB_TXCSR_FLUSHFIFO |
- + 					MUSB_TXCSR_H_WZC_BITS;
- + 				musb_writew(epio, MUSB_TXCSR, csr);
- + 			}
- + 		}
- + 	} else { /* Rx */
- + 		dprintk("Rx channel teardown, cppi_ch = %p\n", cppi_ch);
- + 
- + 		/* For host, ensure ReqPkt is never set again */
- + 		cppi41_autoreq_update(cppi_ch, USB_NO_AUTOREQ);
- + 
- + 		/* disable the DMAreq and remove reqpkt */
- + 		csr  = musb_readw(epio, MUSB_RXCSR);
- + 		dev_dbg(musb->controller,
- + 			"before rx-teardown: rxcsr %x rxcount %x\n", csr,
- + 			musb_readw(epio, MUSB_RXCOUNT));
- + 		/* 250usec delay to drain to cppi dma
- + 		 * pipe line */
- + 		udelay(250);
- + 
- + 		/* For host, clear (just) ReqPkt at end of current packet(s) */
- + 		if (is_host_active(cppi->musb))
- + 			csr &= ~MUSB_RXCSR_H_REQPKT;
- + 
- + 		csr &= ~MUSB_RXCSR_DMAENAB;
- + 		musb_writew(epio, MUSB_RXCSR, csr);
- + 		/* wait till xdma completes last 64 bytes transfer from
- + 		 * mentor fifo to internal cppi fifo and drain
- + 		 * cppi dma pipe line
- + 		 */
- + 		udelay(250);
- + 
- + 		/* Flush FIFO of the endpoint */
- + 		csr  = musb_readw(epio, MUSB_RXCSR);
- + 
- + 		if (csr & MUSB_RXCSR_RXPKTRDY)
- + 			csr |= MUSB_RXCSR_FLUSHFIFO;
- + 
- + 		csr |= MUSB_RXCSR_H_WZC_BITS;
- + 		musb_writew(epio, MUSB_RXCSR, csr);
- + 		musb_writew(epio, MUSB_RXCSR, csr);
- + 		csr  = musb_readw(epio, MUSB_RXCSR);
- + 
- + 		/* Issue CPPI FIFO teardown for Rx channel */
- + 		td_reg  = musb_readl(reg_base, cppi->teardown_reg_offs);
- + 		td_reg |= USB_RX_TDOWN_MASK(ep_num);
- + 		musb_writel(reg_base, cppi->teardown_reg_offs, td_reg);
- + 
- + 		/* Tear down Rx DMA channel */
- + 		usb_rx_ch_teardown(cppi_ch);
- + 
- + 		/*
- + 		 * NOTE: docs don't guarantee any of this works...  we expect
- + 		 * that if the USB core stops telling the CPPI core to pull
- + 		 * more data from it, then it'll be safe to flush current Rx
- + 		 * DMA state iff any pending FIFO transfer is done.
- + 		 */
- + 
- + 		/* For host, ensure ReqPkt is never set again */
- + 		cppi41_autoreq_update(cppi_ch, USB_NO_AUTOREQ);
- + 	}
- + 
- + 	/*
- + 	 * There might be PDs in the Rx/Tx source queue that were not consumed
- + 	 * by the DMA controller -- they need to be recycled properly.
- + 	 */
- + 	while ((pd_addr = cppi41_queue_pop(&cppi_ch->queue_obj)) != 0) {
- + 		struct usb_pkt_desc *curr_pd;
- + 
- + 		curr_pd = usb_get_pd_ptr(cppi, pd_addr);
- + 		if (curr_pd == NULL) {
- + 			ERR("Invalid PD popped from source queue\n");
- + 			continue;
- + 		}
- + 
- + 		/*
- + 		 * Return Rx/Tx PDs to the software list --
- + 		 * this is protected by critical section.
- + 		 */
- + 		dprintk("Returning PD %p to the free PD list\n", curr_pd);
- + 		usb_put_free_pd(cppi, curr_pd);
- + 	}
- + 
- + #ifdef DEBUG_CPPI_TD
- + 	printk("After teardown:");
- + 	print_pd_list(cppi->pd_pool_head);
- + #endif
- + 
- + 	/* Re-enable the DMA channel */
- + 	cppi41_dma_ch_enable(&cppi_ch->dma_ch_obj);
- + 
- + 	channel->status = MUSB_DMA_STATUS_FREE;
- + 
- + 	return 0;
- + }
- + 
- + void txdma_completion_work(struct work_struct *data)
- + {
- + 	struct cppi41 *cppi = container_of(data, struct cppi41, txdma_work);
- + 	struct cppi41_channel *tx_ch;
- + 	struct musb *musb = cppi->musb;
- + 	unsigned index;
- + 	u8 resched = 0;
- + 	unsigned long flags;
- + 
- + 	while (1) {
- + 		for (index = 0; index < USB_CPPI41_NUM_CH; index++) {
- + 			void __iomem *epio;
- + 			u16 csr;
- + 
- + 			tx_ch = &cppi->tx_cppi_ch[index];
- + 			if (tx_ch->tx_complete) {
- + 				/* Sometimes a EP can unregister from a DMA
- + 				 * channel while the data is still in the FIFO.
- + 				 * Probable reason a proper abort was not
- + 				 * called before taking such a step.
- + 				 * Protect against such cases.
- + 				 */
- + 				if (!tx_ch->end_pt) {
- + 					tx_ch->tx_complete = 0;
- + 					tx_ch->count = 0;
- + 					continue;
- + 				}
- + 
- + 				epio = tx_ch->end_pt->regs;
- + 				csr = musb_readw(epio, MUSB_TXCSR);
- + 
- + 				if (!tx_ch->txfifo_intr_enable &&
- + 					(csr & (MUSB_TXCSR_TXPKTRDY |
- + 					MUSB_TXCSR_FIFONOTEMPTY))) {
- + 					resched = 1;
- + 				} else {
- + 					if (tx_ch->count > 0) {
- + 						tx_ch->count--;
- + 						resched = 1;
- + 						continue;
- + 					}
- + 					tx_ch->channel.status =
- + 						MUSB_DMA_STATUS_FREE;
- + 					tx_ch->tx_complete = 0;
- + 					spin_lock_irqsave(&musb->lock, flags);
- + 					musb_dma_completion(musb, index+1, 1);
- + 					spin_unlock_irqrestore(&musb->lock,
- + 						flags);
- + 				}
- + 			}
- + 
- + 			if (!resched)
- + 				cond_resched();
- + 		}
- + 
- + 		if (resched) {
- + 			resched = 0;
- + 			cond_resched();
- + 		} else {
- + 			return ;
- + 		}
- + 	}
- + 
- + }
- + 
- + void cppi41_handle_txfifo_intr(struct musb *musb, u16 usbintr)
- + {
- + 	struct cppi41 *cppi;
- + 	struct cppi41_channel *tx_ch;
- + 	int index;
- + 
- + 	cppi = container_of(musb->dma_controller, struct cppi41, controller);
- + 	for (index = 0; (index < USB_CPPI41_NUM_CH) && usbintr; index++) {
- + 		if (usbintr & 1) {
- + 			tx_ch = &cppi->tx_cppi_ch[index];
- + 			if (tx_ch->txf_complete) {
- + 				/* disable txfifo empty interupt */
- + 				txfifoempty_int_disable(musb, index+1);
- + 				tx_ch->txf_complete = 0;
- + 				if (!tx_ch->txfifo_intr_enable)
- + 					dev_dbg(musb->controller,
- + 					"Bug, wrong TxFintr ep%d\n", index+1);
- + 				tx_ch->txfifo_intr_enable = 0;
- + 
- + 				tx_ch->channel.status =
- + 					MUSB_DMA_STATUS_FREE;
- + 
- + 				dev_dbg(musb->controller,
- + 					"txc: givback ep%d\n", index+1);
- + 				musb_dma_completion(musb, index+1, 1);
- + 			}
- + 		}
- + 		usbintr = usbintr >> 1;
- + 	}
- + }
- + EXPORT_SYMBOL(cppi41_handle_txfifo_intr);
- + 
- + /**
- +  * cppi41_dma_controller_create -
- +  * instantiate an object representing DMA controller.
- +  */
- + struct dma_controller * __devinit
- + cppi41_dma_controller_create(struct musb  *musb, void __iomem *mregs)
- + {
- + 	struct cppi41 *cppi;
- + 
- + 	cppi = kzalloc(sizeof *cppi, GFP_KERNEL);
- + 	if (!cppi)
- + 		return NULL;
- + 
- + 	/* Initialize the CPPI 4.1 DMA controller structure */
- + 	cppi->musb  = musb;
- + 	cppi->controller.start = cppi41_controller_start;
- + 	cppi->controller.stop  = cppi41_controller_stop;
- + 	cppi->controller.channel_alloc = cppi41_channel_alloc;
- + 	cppi->controller.channel_release = cppi41_channel_release;
- + 	cppi->controller.channel_program = cppi41_channel_program;
- + 	cppi->controller.channel_abort = cppi41_channel_abort;
- + 	cppi->cppi_info = (struct usb_cppi41_info *)&usb_cppi41_info[musb->id];;
- + 	cppi->en_bd_intr = cppi->cppi_info->bd_intr_ctrl;
- + 	cppi->txfifo_intr_enable = musb->txfifo_intr_enable;
- + 	INIT_WORK(&cppi->txdma_work, txdma_completion_work);
- + 	INIT_WORK(&cppi->rxdma_work, rxdma_completion_work);
- + 
- + 	/*
- + 	 * Extra IN token has been seen when a file is transferred from one MSC
- + 	 * device to other due to xDMA IP bug when multiple masters access
- + 	 * mentor controller register space.
- + 	 * As a software workaround use transparent mode and correct data toggle
- + 	 * when they go wrong.
- + 	 * This issue is expected to be fixed in RTL version post 0xD.
- + 	 * Since RTL version is not available to distinguish the fix, based on
- + 	 * soc revision the rxdma generic rndis shall be enabled/disabled by
- + 	 * platform driver as mentioned below
- + 	 * set cppi_info->grndis_for_host_rx = 1 to enable
- + 	 *			rxdma generic rndis mode
- + 	 * set cppi_info->grndis_for_host_rx = 0 and
- + 	 *	cppi->musb->datatog_fix = 0 to disable the rxdma generic rndis.
- + 	 */
- + 	if (cppi->cppi_info->grndis_for_host_rx)
- + 		cppi->musb->datatog_fix = 0;
- + 	else
- + 		cppi->musb->datatog_fix = 1;
- + 	dev_dbg(musb->controller, "musb%d: %s cppi41 rxdma grndis-mode\n",
- + 		musb->id, cppi->cppi_info->grndis_for_host_rx ? "enable" :
- + 			"disable");
- + 
- + 	/* enable infinite mode only for ti81xx silicon rev2 */
- + 	if (cpu_is_am33xx() || cpu_is_ti816x()) {
- + 		dev_dbg(musb->controller, "cppi41dma supports infinite mode\n");
- + 		cppi->inf_mode = 1;
- + 	}
- + 
- + 	return &cppi->controller;
- + }
- + EXPORT_SYMBOL(cppi41_dma_controller_create);
- + 
- + /**
- +  * cppi41_dma_controller_destroy -
- +  * destroy a previously instantiated DMA controller
- +  * @controller: the controller
- +  */
- + void cppi41_dma_controller_destroy(struct dma_controller *controller)
- + {
- + 	struct cppi41 *cppi;
- + 
- + 	cppi = container_of(controller, struct cppi41, controller);
- + 
- + 	/* Free the CPPI object */
- + 	kfree(cppi);
- + }
- + EXPORT_SYMBOL(cppi41_dma_controller_destroy);
- + 
- + static void usb_process_tx_queue(struct cppi41 *cppi, unsigned index)
- + {
- + 	struct cppi41_queue_obj tx_queue_obj;
- + 	unsigned long pd_addr;
- + 	struct usb_cppi41_info *cppi_info = cppi->cppi_info;
- + 	struct musb *musb = cppi->musb;
- + 
- + 	if (cppi41_queue_init(&tx_queue_obj, cppi_info->q_mgr,
- + 			      cppi_info->tx_comp_q[index])) {
- + 		dev_dbg(musb->controller, "ERROR: cppi41_queue_init failed for "
- + 		    "Tx completion queue");
- + 		return;
- + 	}
- + 
- + 	while ((pd_addr = cppi41_queue_pop(&tx_queue_obj)) != 0) {
- + 		struct usb_pkt_desc *curr_pd;
- + 		struct cppi41_channel *tx_ch;
- + 		u8 ch_num, ep_num;
- + 		u32 length;
- + 
- + 		curr_pd = usb_get_pd_ptr(cppi, pd_addr);
- + 		if (curr_pd == NULL) {
- + 			ERR("Invalid PD popped from Tx completion queue\n");
- + 			continue;
- + 		}
- + 
- + 		/* Extract the data from received packet descriptor */
- + 		ch_num = curr_pd->ch_num;
- + 		ep_num = curr_pd->ep_num;
- + 		length = curr_pd->hw_desc.buf_len;
- + 
- + 		tx_ch = &cppi->tx_cppi_ch[ch_num];
- + 		tx_ch->channel.actual_len += length;
- + 
- + 		/*
- + 		 * Return Tx PD to the software list --
- + 		 * this is protected by critical section
- + 		 */
- + 		usb_put_free_pd(cppi, curr_pd);
- + 
- + 		if ((tx_ch->curr_offset < tx_ch->length) ||
- + 		    (tx_ch->transfer_mode && !tx_ch->zlp_queued))
- + 			cppi41_next_tx_segment(tx_ch);
- + 		else if (tx_ch->channel.actual_len >= tx_ch->length) {
- + 			void __iomem *epio;
- + 			u16 csr;
- + 
- + 			/*
- + 			 * We get Tx DMA completion interrupt even when
- + 			 * data is still in FIFO and not moved out to
- + 			 * USB bus. As we program the next request we
- + 			 * flush out and old data in FIFO which affects
- + 			 * USB functionality. So far, we have obsered
- + 			 * failure with iperf.
- + 			 */
- + 			/* wait for tx fifo empty completion interrupt
- + 			 * if enabled other wise use the workthread
- + 			 * to poll fifo empty status
- + 			 */
- + 			epio = tx_ch->end_pt->regs;
- + 			csr = musb_readw(epio, MUSB_TXCSR);
- + 
- + 			if (tx_ch->txfifo_intr_enable) {
- + 				tx_ch->txf_complete = 1;
- + 				dev_dbg(musb->controller,
- + 				"wait for TxF-EmptyIntr ep%d\n", ep_num);
- + 			} else {
- + 				int residue;
- + 
- + 				residue = tx_ch->channel.actual_len %
- + 						tx_ch->pkt_size;
- + 
- + 				if (tx_ch->pkt_size > 128 && !residue) {
- + 					tx_ch->channel.status =
- + 						MUSB_DMA_STATUS_FREE;
- + 					musb_dma_completion(cppi->musb,
- + 						ep_num, 1);
- + 				} else {
- + 					tx_ch->tx_complete = 1;
- + 					tx_ch->count = 1;
- + 					schedule_work(&cppi->txdma_work);
- + 				}
- + 			}
- + 		}
- + 	}
- + }
- + 
- + static void usb_process_rx_bd(struct cppi41 *cppi,
- + 		struct usb_pkt_desc *curr_pd)
- + {
- + 	u8 en_bd_intr = cppi->en_bd_intr;
- + 	struct cppi41_channel *rx_ch;
- + 	u8 ch_num, ep_num;
- + 	struct musb *musb = cppi->musb;
- + 	u32 length = 0, orig_buf_len;
- + 
- + 	/* Extract the data from received packet descriptor */
- + 	length = curr_pd->hw_desc.desc_info & CPPI41_PKT_LEN_MASK;
- + 	ch_num = curr_pd->ch_num;
- + 	ep_num = curr_pd->ep_num;
- + 
- + 	/* the cppi41 dma will set received byte length as 1 when
- + 	 * zero length packet is received, fix this dummy byte by
- + 	 * setting acutal length received as zero
- + 	 */
- + 	if (curr_pd->hw_desc.pkt_info & CPPI41_ZLP)
- + 		length = 0;
- + 
- + 	rx_ch = &cppi->rx_cppi_ch[ch_num];
- + 	dev_dbg(musb->controller, "Rx complete: dma channel(%d) ep%d len %d\n",
- + 		ch_num, ep_num, length);
- + 
- + 	rx_ch->channel.actual_len += length;
- + 
- + 	if (curr_pd->eop) {
- + 		curr_pd->eop = 0;
- + 		/* disable the rx dma schedular */
- + 		if (is_peripheral_active(cppi->musb) && !cppi->inf_mode)
- + 			cppi41_schedtbl_remove_dma_ch(0, 0, ch_num, 0);
- + 	}
- + 
- + 	/*
- + 	 * Return Rx PD to the software list --
- + 	 * this is protected by critical section
- + 	 */
- + 	usb_put_free_pd(cppi, curr_pd);
- + 
- + 	orig_buf_len = curr_pd->hw_desc.orig_buf_len;
- + 	if (en_bd_intr)
- + 		orig_buf_len &= ~CPPI41_PKT_INTR_FLAG;
- + 
- + 	dev_dbg(musb->controller,
- + 		"curr_pd=%p, len=%d, origlen=%d,rxch(alen/len)=%d/%d\n",
- + 			curr_pd, length, orig_buf_len,
- + 			rx_ch->channel.actual_len, rx_ch->length);
- + 
- + 	if (unlikely(rx_ch->channel.actual_len >= rx_ch->length ||
- + 		     length < orig_buf_len)) {
- + 
- + #if defined(CONFIG_SOC_OMAPTI81XX) || defined(CONFIG_SOC_OMAPAM33XX)
- + 		struct musb_hw_ep *ep;
- + 		u8 isoc, next_seg = 0;
- + 
- + 		/* Workaround for early rx completion of
- + 		 * cppi41 dma in Generic RNDIS mode for ti81xx
- + 		 */
- + 		if (is_host_enabled(cppi->musb)) {
- + 			u32 pkt_size = rx_ch->pkt_size;
- + 			ep = cppi->musb->endpoints + ep_num;
- + 			isoc = musb_readb(ep->regs, MUSB_RXTYPE);
- + 			isoc = (isoc >> 4) & 0x1;
- + 
- + 			if (!isoc
- + 				&& (rx_ch->dma_mode == USB_GENERIC_RNDIS_MODE)
- + 				&& (rx_ch->channel.actual_len < rx_ch->length)
- + 				&& !(rx_ch->channel.actual_len % pkt_size))
- + 					next_seg = 1;
- + 		}
- + 		if (next_seg) {
- + 			rx_ch->curr_offset = rx_ch->channel.actual_len;
- + 			cppi41_next_rx_segment(rx_ch);
- + 		} else
- + #endif
- + 		{
- + 			rx_ch->channel.status = MUSB_DMA_STATUS_FREE;
- + 
- + 			if (rx_ch->inf_mode) {
- + 				cppi41_rx_ch_set_maxbufcnt(
- + 				&rx_ch->dma_ch_obj, 0);
- + 				rx_ch->inf_mode = 0;
- + 			}
- + 
- + 			/* Rx completion routine callback */
- + 			musb_dma_completion(cppi->musb, ep_num, 0);
- + 		}
- + 	} else {
- + 			if ((rx_ch->length - rx_ch->curr_offset) > 0)
- + 				cppi41_next_rx_segment(rx_ch);
- + 	}
- + }
- + 
- + static void rxdma_completion_work(struct work_struct *data)
- + {
- + 	struct cppi41 *cppi = container_of(data, struct cppi41, rxdma_work);
- + 	struct musb *musb = cppi->musb;
- + 	unsigned index;
- + 	u8 resched = 0;
- + 	unsigned long flags, length;
- + 	struct cppi41_channel *rx_ch;
- + 
- + 	while (1) {
- + 		for (index = 0; index < USB_CPPI41_NUM_CH; index++) {
- + 			rx_ch = &cppi->rx_cppi_ch[index];
- + 			if (rx_ch->rx_complete) {
- + 				/* Sometimes a EP can unregister from a DMA
- + 				 * channel while the data is still in the FIFO.
- + 				 * Probable reason a proper abort was not
- + 				 * called before taking such a step.
- + 				 */
- + 				if (!rx_ch->curr_pd) {
- + 					ERR("invalid curr_pd chnum%d\n", index);
- + 					continue;
- + 				}
- + 
- + 				length = rx_ch->curr_pd->hw_desc.desc_info &
- + 						CPPI41_PKT_LEN_MASK;
- + 				if (length == 0) {
- + 					resched = 1;
- + 					continue;
- + 				}
- + 				spin_lock_irqsave(&musb->lock, flags);
- + 				usb_process_rx_bd(cppi, rx_ch->curr_pd);
- + 				rx_ch->rx_complete = 0;
- + 				rx_ch->curr_pd = 0;
- + 				spin_unlock_irqrestore(&musb->lock, flags);
- + 			}
- + 		}
- + 
- + 		if (resched) {
- + 			resched = 0;
- + 			cond_resched();
- + 		} else
- + 			return ;
- + 	}
- + }
- + 
- + static void usb_process_rx_queue(struct cppi41 *cppi, unsigned index)
- + {
- + 	struct cppi41_queue_obj rx_queue_obj;
- + 	unsigned long pd_addr;
- + 	struct usb_cppi41_info *cppi_info = cppi->cppi_info;
- + 	struct musb *musb = cppi->musb;
- + 
- + 	if (cppi41_queue_init(&rx_queue_obj, cppi_info->q_mgr,
- + 			      cppi_info->rx_comp_q[index])) {
- + 		dev_dbg(musb->controller, "ERROR: cppi41_queue_init failed for Rx queue\n");
- + 		return;
- + 	}
- + 
- + 	while ((pd_addr = cppi41_queue_pop(&rx_queue_obj)) != 0) {
- + 		struct usb_pkt_desc *curr_pd;
- + 		struct cppi41_channel *rx_ch;
- + 		u8 ch_num, ep_num;
- + 		u32 length = 0, timeout = 50;
- + 
- + 		curr_pd = usb_get_pd_ptr(cppi, pd_addr);
- + 		if (curr_pd == NULL) {
- + 			ERR("Invalid PD popped from Rx completion queue\n");
- + 			continue;
- + 		}
- + 
- + 		/* This delay is required to overcome the dma race condition
- + 		 * where software reads buffer descriptor before being updated
- + 		 * by dma as buffer descriptor's writes by dma still pending in
- + 		 * interconnect bridge.
- + 		 */
- + 		while (timeout--) {
- + 			length = curr_pd->hw_desc.desc_info &
- + 					CPPI41_PKT_LEN_MASK;
- + 			if (length != 0)
- + 				break;
- + 			udelay(1);
- + 		}
- + 
- + 
- + 		/* Extract the data from received packet descriptor */
- + 		ch_num = curr_pd->ch_num;
- + 		ep_num = curr_pd->ep_num;
- + 		rx_ch = &cppi->rx_cppi_ch[ch_num];
- + 
- + 		if (length == 0) {
- + 			dev_dbg(musb->controller, "!Race condtion: rxBD still not"
- + 				"updated, poll rxBD update ch%d ep%d\n", ch_num,
- + 				ep_num);
- + 			rx_ch->rx_complete = 1;
- + 			rx_ch->curr_pd = curr_pd;
- + 			schedule_work(&cppi->rxdma_work);
- + 			continue;
- + 		}
- + 
- + 
- + 		usb_process_rx_bd(cppi, curr_pd);
- + 	}
- + }
- + 
- + /*
- +  * cppi41_completion - handle interrupts from the Tx/Rx completion queues
- +  *
- +  * NOTE: since we have to manually prod the Rx process in the transparent mode,
- +  *	 we certainly want to handle the Rx queues first.
- +  */
- + void cppi41_completion(struct musb *musb, u32 rx, u32 tx)
- + {
- + 	struct cppi41 *cppi;
- + 	unsigned index;
- + 
- + 	cppi = container_of(musb->dma_controller, struct cppi41, controller);
- + 
- + 	/* Process packet descriptors from the Rx queues */
- + 	for (index = 0; rx != 0; rx >>= 1, index++)
- + 		if (rx & 1)
- + 			usb_process_rx_queue(cppi, index);
- + 
- + 	/* Process packet descriptors from the Tx completion queues */
- + 	for (index = 0; tx != 0; tx >>= 1, index++)
- + 		if (tx & 1)
- + 			usb_process_tx_queue(cppi, index);
- + }
- + EXPORT_SYMBOL(cppi41_completion);
- + 
- + MODULE_DESCRIPTION("CPPI4.1 dma controller driver for musb");
- + MODULE_LICENSE("GPL v2");
- + 
- + static int __init cppi41_dma_init(void)
- + {
- + 	return 0;
- + }
- + module_init(cppi41_dma_init);
- + 
- + static void __exit cppi41_dma__exit(void)
- + {
- + }
- + module_exit(cppi41_dma__exit);
- diff -crN linux-3.2.1_o/drivers/usb/musb/cppi41_dma.h linux-3.2.1/drivers/usb/musb/cppi41_dma.h
- *** linux-3.2.1_o/drivers/usb/musb/cppi41_dma.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/drivers/usb/musb/cppi41_dma.h	2014-05-15 13:25:15.062607361 +0900
- ***************
- *** 0 ****
- --- 1,68 ----
- + /*
- +  * Copyright (C) 2005-2006 by Texas Instruments
- +  * Copyright (c) 2008, MontaVista Software, Inc. <source@mvista.com>
- +  *
- +  * This program is free software; you can distribute it and/or modify it
- +  * under the terms of the GNU General Public License (Version 2) as
- +  * published by the Free Software Foundation.
- +  *
- +  * This program is distributed in the hope it will be useful, but WITHOUT
- +  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- +  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- +  * for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License along
- +  * with this program; if not, write to the Free Software Foundation, Inc.,
- +  * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- +  *
- +  */
- + 
- + #ifndef _CPPI41_DMA_H_
- + #define _CPPI41_DMA_H_
- + #include <plat/usb.h>
- + 
- + /* USBSS RTL versions */
- + #define USBSS_RTL_VERSION_MASK	0xF
- + #define USBSS_RTL_VERSION_D	0xD
- + 
- + /**
- +  * struct usb_cppi41_info - CPPI 4.1 USB implementation details
- +  * @dma_block:	DMA block number
- +  * @ep_dma_ch:	DMA channel numbers used for EPs 1 .. Max_EP
- +  * @q_mgr:	queue manager number
- +  * @num_tx_comp_q: number of the Tx completion queues
- +  * @num_rx_comp_q: number of the Rx queues
- +  * @tx_comp_q:	pointer to the list of the Tx completion queue numbers
- +  * @rx_comp_q:	pointer to the list of the Rx queue numbers
- +  */
- + struct usb_cppi41_info {
- + 	u8 dma_block;
- + 	u8 ep_dma_ch[USB_CPPI41_NUM_CH];
- + 	u8 q_mgr;
- + 	u8 num_tx_comp_q;
- + 	u8 num_rx_comp_q;
- + 	u16 *tx_comp_q;
- + 	u16 *rx_comp_q;
- + 	u8 bd_intr_ctrl;
- + 	u8 grndis_for_host_rx;
- + 	u32 version;
- + };
- + 
- + extern struct usb_cppi41_info usb_cppi41_info[];
- + 
- + /**
- +  * cppi41_completion - Tx/Rx completion queue interrupt handling hook
- +  * @musb:	the controller
- +  * @rx:	bitmask having bit N set if Rx queue N is not empty
- +  * @tx:	bitmask having bit N set if Tx completion queue N is not empty
- +  */
- + void cppi41_completion(struct musb *musb, u32 rx, u32 tx);
- + 
- + /**
- +  * cppi41_handle_txfifo_intr - Handles tx fifo empty interupts
- +  * @musb:	the controller
- +  */
- + void cppi41_handle_txfifo_intr(struct musb *musb, u16 usbintr);
- + void txfifoempty_int_enable(struct musb *musb, u8 ep_num);
- + void txfifoempty_int_disable(struct musb *musb, u8 ep_num);
- + #endif	/* _CPPI41_DMA_H_ */
- diff -crN linux-3.2.1_o/drivers/usb/musb/cppi41.h linux-3.2.1/drivers/usb/musb/cppi41.h
- *** linux-3.2.1_o/drivers/usb/musb/cppi41.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/drivers/usb/musb/cppi41.h	2014-05-15 13:25:15.079322705 +0900
- ***************
- *** 0 ****
- --- 1,851 ----
- + /*
- +  * CPPI 4.1 definitions
- +  *
- +  * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
- +  *
- +  * This program is free software; you can distribute it and/or modify it
- +  * under the terms of the GNU General Public License (Version 2) as
- +  * published by the Free Software Foundation.
- +  *
- +  * This program is distributed in the hope it will be useful, but WITHOUT
- +  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- +  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- +  * for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License along
- +  * with this program; if not, write to the Free Software Foundation, Inc.,
- +  * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- +  *
- +  */
- + 
- + #include <linux/types.h>
- + 
- + /*
- +  * Queue Manager - Control Registers Region
- +  */
- + #define QMGR_REVISION_REG		0x00	/* Major and minor versions */
- + 						/* of the module */
- + #define QMGR_QUEUE_DIVERSION_REG	0x08	/* Queue Diversion register */
- + #define QMGR_FREE_DESC_BUF_STARVED_REG(n) (0x20 + ((n) << 2)) /* Free Desc./ */
- + 						/* Buffer Starvation Count */
- + #define QMGR_FREE_DESC_STARVED_REG(n)	(0x30 + ((n) << 2)) /* Free Desc. */
- + 						/* Starvation Count */
- + #define QMGR_LINKING_RAM_RGN0_BASE_REG	0x80	/* Linking RAM Region 0 Base */
- + 						/* Address */
- + #define QMGR_LINKING_RAM_RGN0_SIZE_REG	0x84	/* Linking RAM Region 0 Size */
- + #define QMGR_LINKING_RAM_RGN1_BASE_REG	0x88	/* Linking RAM Region 1 Base */
- + 						/* Address */
- + #define QMGR_QUEUE_PENDING_REG(n)	(0x90 + ((n) << 2)) /* Pending status */
- + 						/* for all queues */
- + 
- + /*
- +  * Queue Manager - Memory Region Registers
- +  */
- + #define QMGR_MEM_RGN_BASE_REG(r)	(0x00 + ((r) << 4))
- + #define QMGR_MEM_RGN_CTRL_REG(r)	(0x04 + ((r) << 4))
- + 
- + /* Memory Region R Control Register bits */
- + #define QMGR_MEM_RGN_INDEX_SHIFT	16
- + #define QMGR_MEM_RGN_INDEX_MASK		(0x3fff << QMGR_MEM_RGN_INDEX_SHIFT)
- + #define QMGR_MEM_RGN_DESC_SIZE_SHIFT	8
- + #define QMGR_MEM_RGN_DESC_SIZE_MASK	(0xf << QMGR_MEM_RGN_DESC_SIZE_SHIFT)
- + #define QMGR_MEM_RGN_SIZE_SHIFT		0
- + #define QMGR_MEM_RGN_SIZE_MASK		(7 << QMGR_MEM_RGN_SIZE_SHIFT)
- + 
- + /*
- +  * Queue Manager - Queues Region
- +  */
- + #define QMGR_QUEUE_REG_A(n)		(0x00 + ((n) << 4))
- + #define QMGR_QUEUE_REG_B(n)		(0x04 + ((n) << 4))
- + #define QMGR_QUEUE_REG_C(n)		(0x08 + ((n) << 4))
- + #define QMGR_QUEUE_REG_D(n)		(0x0C + ((n) << 4))
- + 
- + /* Queue N Register C bits */
- + #define QMGR_QUEUE_HEAD_TAIL_SHIFT	31
- + #define QMGR_QUEUE_HEAD_TAIL_MASK	(1 << QMGR_QUEUE_HEAD_TAIL_SHIFT)
- + #define QMGR_QUEUE_PKT_SIZE_SHIFT	0
- + #define QMGR_QUEUE_PKT_SIZE_MASK	(0x3fff << QMGR_QUEUE_PKT_SIZE_SHIFT)
- + /* Queue N Register D bits */
- + #define QMGR_QUEUE_DESC_PTR_SHIFT	5
- + #define QMGR_QUEUE_DESC_PTR_MASK	(0x7ffffff << QMGR_QUEUE_DESC_PTR_SHIFT)
- + #define QMGR_QUEUE_DESC_SIZE_SHIFT	0
- + #define QMGR_QUEUE_DESC_SIZE_MASK	(0x1f << QMGR_QUEUE_DESC_SIZE_SHIFT)
- + 
- + /*
- +  * Queue Manager - Queue Status Region
- +  */
- + #define QMGR_QUEUE_STATUS_REG_A(n)	(0x00 + ((n) << 4))
- + #define QMGR_QUEUE_STATUS_REG_B(n)	(0x04 + ((n) << 4))
- + #define QMGR_QUEUE_STATUS_REG_C(n)	(0x08 + ((n) << 4))
- + 
- + /*
- +  * DMA Controller - Global Control Registers Region
- +  */
- + #define DMA_REVISION_REG		0x00	/* Major and minor versions */
- + 						/* of the module */
- + #define DMA_TEARDOWN_FREE_DESC_CTRL_REG 0x04	/* Queue  manager and queue */
- + 						/* number for Teardown free */
- + 						/* descriptor queue */
- + #define DMA_EMULATION_CTRL_REG		0x08	/* Emulation control register */
- + 
- + /* Teardown Free Descriptor Queue Control Register bits */
- + #define DMA_TD_DESC_QMGR_SHIFT		12
- + #define DMA_TD_DESC_QMGR_MASK		(3 << DMA_TD_DESC_QMGR_SHIFT)
- + #define DMA_TD_DESC_QNUM_SHIFT		0
- + #define DMA_TD_DESC_QNUM_MASK		(0xfff << DMA_TD_DESC_QNUM_SHIFT)
- + 
- + /*
- +  * DMA Controller - Channel Control / Status Registers Region
- +  */
- + #define DMA_CH_TX_GLOBAL_CFG_REG(n)	 (0x00 + ((n) << 5))
- + #define DMA_CH_RX_GLOBAL_CFG_REG(n)	 (0x08 + ((n) << 5))
- + #define DMA_CH_RX_HOST_PKT_CFG_REG_A(n)  (0x0C + ((n) << 5))
- + #define DMA_CH_RX_HOST_PKT_CFG_REG_B(n)  (0x10 + ((n) << 5))
- + #define DMA_CH_RX_EMBED_PKT_CFG_REG_A(n) (0x14 + ((n) << 5))
- + #define DMA_CH_RX_EMBED_PKT_CFG_REG_B(n) (0x18 + ((n) << 5))
- + #define DMA_CH_RX_MONO_PKT_CFG_REG(n)	 (0x1C + ((n) << 5))
- + 
- + /* Tx Channel N Global Configuration Register bits */
- + #define DMA_CH_TX_ENABLE_SHIFT		31
- + #define DMA_CH_TX_ENABLE_MASK		(1 << DMA_CH_TX_ENABLE_SHIFT)
- + #define DMA_CH_TX_TEARDOWN_SHIFT	30
- + #define DMA_CH_TX_TEARDOWN_MASK		(1 << DMA_CH_TX_TEARDOWN_SHIFT)
- + #define DMA_CH_TX_DEFAULT_QMGR_SHIFT	12
- + #define DMA_CH_TX_DEFAULT_QMGR_MASK	(3 << DMA_CH_TX_DEFAULT_QMGR_SHIFT)
- + #define DMA_CH_TX_DEFAULT_QNUM_SHIFT	0
- + #define DMA_CH_TX_DEFAULT_QNUM_MASK	(0xfff << DMA_CH_TX_DEFAULT_QNUM_SHIFT)
- + 
- + /* Rx Channel N Global Configuration Register bits */
- + #define DMA_CH_RX_ENABLE_SHIFT		31
- + #define DMA_CH_RX_ENABLE_MASK		(1 << DMA_CH_RX_ENABLE_SHIFT)
- + #define DMA_CH_RX_TEARDOWN_SHIFT	30
- + #define DMA_CH_RX_TEARDOWN_MASK		(1 << DMA_CH_RX_TEARDOWN_SHIFT)
- + #define DMA_CH_RX_ERROR_HANDLING_SHIFT	24
- + #define DMA_CH_RX_ERROR_HANDLING_MASK	(1 << DMA_CH_RX_ERROR_HANDLING_SHIFT)
- + #define DMA_CH_RX_SOP_OFFSET_SHIFT	16
- + #define DMA_CH_RX_SOP_OFFSET_MASK	(0xff << DMA_CH_RX_SOP_OFFSET_SHIFT)
- + #define DMA_CH_RX_DEFAULT_DESC_TYPE_SHIFT 14
- + #define DMA_CH_RX_DEFAULT_DESC_TYPE_MASK  (3 << \
- + 					   DMA_CH_RX_DEFAULT_DESC_TYPE_SHIFT)
- + #define DMA_CH_RX_DEFAULT_DESC_EMBED	0
- + #define DMA_CH_RX_DEFAULT_DESC_HOST	1
- + #define DMA_CH_RX_DEFAULT_DESC_MONO	2
- + #define DMA_CH_RX_DEFAULT_RQ_QMGR_SHIFT 12
- + #define DMA_CH_RX_DEFAULT_RQ_QMGR_MASK	(3 << DMA_CH_RX_DEFAULT_RQ_QMGR_SHIFT)
- + #define DMA_CH_RX_DEFAULT_RQ_QNUM_SHIFT 0
- + #define DMA_CH_RX_DEFAULT_RQ_QNUM_MASK	(0xfff << \
- + 					 DMA_CH_RX_DEFAULT_RQ_QNUM_SHIFT)
- + #define DMA_CH_RX_MAX_BUF_CNT_SHIFT	26
- + #define	DMA_CH_RX_MAX_BUF_CNT_0		0
- + #define	DMA_CH_RX_MAX_BUF_CNT_1		1
- + #define	DMA_CH_RX_MAX_BUF_CNT_2		2
- + #define	DMA_CH_RX_MAX_BUF_CNT_3		3
- + 
- + /* Rx Channel N Host Packet Configuration Register A/B bits */
- + #define DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(n) (12 + 16 * ((n) & 1))
- + #define DMA_CH_RX_HOST_FDQ_QMGR_MASK(n)  (3 << DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(n))
- + #define DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(n) (0 + 16 * ((n) & 1))
- + #define DMA_CH_RX_HOST_FDQ_QNUM_MASK(n)  (0xfff << \
- + 					  DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(n))
- + 
- + /* Rx Channel N Embedded Packet Configuration Register A bits */
- + #define DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(n) (6 + 8 * (n))
- + #define DMA_CH_RX_EMBED_FBP_BMGR_MASK(n)  (3 << \
- + 					   DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(n))
- + #define DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(n) (0 + 8 * (n))
- + #define DMA_CH_RX_EMBED_FBP_PNUM_MASK(n)  (0x1f << \
- + 					   DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(n))
- + 
- + /* Rx Channel N Embedded Packet Configuration Register B bits */
- + #define DMA_CH_RX_EMBED_NUM_SLOT_SHIFT	24
- + #define DMA_CH_RX_EMBED_NUM_SLOT_MASK	(7 << DMA_CH_RX_EMBED_NUM_SLOT_SHIFT)
- + #define DMA_CH_RX_EMBED_SOP_SLOT_SHIFT	16
- + #define DMA_CH_RX_EMBED_SOP_SLOT_MASK	(7 << DMA_CH_RX_EMBED_SOP_SLOT_SHIFT)
- + #define DMA_CH_RX_EMBED_FDQ_QMGR_SHIFT	12
- + #define DMA_CH_RX_EMBED_FDQ_QMGR_MASK	(3 << DMA_CH_RX_EMBED_FDQ_QMGR_SHIFT)
- + #define DMA_CH_RX_EMBED_FDQ_QNUM_SHIFT	0
- + #define DMA_CH_RX_EMBED_FDQ_QNUM_MASK	(0xfff << \
- + 					 DMA_CH_RX_EMBED_FDQ_QNUM_SHIFT)
- + 
- + /* Rx Channel N Monolithic Packet Configuration Register bits */
- + #define DMA_CH_RX_MONO_SOP_OFFSET_SHIFT 16
- + #define DMA_CH_RX_MONO_SOP_OFFSET_MASK	(0xff << \
- + 					 DMA_CH_RX_MONO_SOP_OFFSET_SHIFT)
- + #define DMA_CH_RX_MONO_FDQ_QMGR_SHIFT	12
- + #define DMA_CH_RX_MONO_FDQ_QMGR_MASK	(3 << DMA_CH_RX_MONO_FDQ_QMGR_SHIFT)
- + #define DMA_CH_RX_MONO_FDQ_QNUM_SHIFT	0
- + #define DMA_CH_RX_MONO_FDQ_QNUM_MASK	(0xfff << DMA_CH_RX_MONO_FDQ_QNUM_SHIFT)
- + 
- + /*
- +  * DMA Scheduler - Control Region
- +  */
- + #define DMA_SCHED_CTRL_REG		0x00
- + 
- + /* DMA Scheduler Control Register bits */
- + #define DMA_SCHED_ENABLE_SHIFT		31
- + #define DMA_SCHED_ENABLE_MASK		(1 << DMA_SCHED_ENABLE_SHIFT)
- + #define DMA_SCHED_LAST_ENTRY_SHIFT	0
- + #define DMA_SCHED_LAST_ENTRY_MASK	(0xff << DMA_SCHED_LAST_ENTRY_SHIFT)
- + 
- + #define CPPI41_TXDMA_MAXLEN		(4 * 1024 * 1024 - 1)
- + #define CPPI41_RXDMA_MAXLEN		(64 * 1024)
- + 
- + /*
- +  * Queue Status register
- +  */
- + #define CPPI41_QSTATUS_REG0	0x90
- + #define CPPI41_QSTATUS_REG1	0x94
- + #define CPPI41_QSTATUS_REG2	0x98
- + #define CPPI41_QSTATUS_REG3	0x9c
- + #define CPPI41_QSTATUS_REG4	0xa0
- + 
- + /*
- +  * DMA Scheduler - Table Region
- +  */
- + #define DMA_SCHED_TABLE_WORD_REG(n)	((n) << 2)
- + #define MAX_SCHED_TBL_ENTRY     8
- + 
- + /*
- +  * CPPI 4.1 Host Packet Descriptor
- +  */
- + struct cppi41_host_pkt_desc {
- + 	u32 desc_info;		/* Descriptor type, protocol specific word */
- + 				/* count, packet length */
- + 	u32 tag_info;		/* Source tag (31:16), destination tag (15:0) */
- + 	u32 pkt_info;		/* Packet error state, type, protocol flags, */
- + 				/* return info, descriptor location */
- + 	u32 buf_len;		/* Number of valid data bytes in the buffer */
- + 	u32 buf_ptr;		/* Pointer to the buffer associated with */
- + 				/* this descriptor */
- + 	u32 next_desc_ptr;	/* Pointer to the next buffer descriptor */
- + 	u32 orig_buf_len;	/* Original buffer length */
- + 	u32 orig_buf_ptr;	/* Original buffer pointer */
- + 	u32 stk_comms_info[2];	/* Network stack private communications info */
- + };
- + 
- + /*
- +  * CPPI 4.1 Host Buffer Descriptor
- +  */
- + struct cppi41_host_buf_desc {
- + 	u32 reserved[2];
- + 	u32 buf_recl_info;	/* Return info, descriptor location */
- + 	u32 buf_len;		/* Number of valid data bytes in the buffer */
- + 	u32 buf_ptr;		/* Pointer to the buffer associated with */
- + 				/* this descriptor */
- + 	u32 next_desc_ptr;	/* Pointer to the next buffer descriptor */
- + 	u32 orig_buf_len;	/* Original buffer length */
- + 	u32 orig_buf_ptr;	/* Original buffer pointer */
- + };
- + 
- + #define CPPI41_DESC_TYPE_SHIFT		27
- + #define CPPI41_DESC_TYPE_MASK		(0x1f << CPPI41_DESC_TYPE_SHIFT)
- + #define CPPI41_DESC_TYPE_HOST		16
- + #define CPPI41_DESC_TYPE_MONOLITHIC	18
- + #define CPPI41_DESC_TYPE_TEARDOWN	19
- + #define CPPI41_PROT_VALID_WORD_CNT_SHIFT 22
- + #define CPPI41_PROT_VALID_WORD_CNT_MASK	(0x1f << CPPI41_PROT_WORD_CNT_SHIFT)
- + #define CPPI41_PKT_LEN_SHIFT		0
- + #define CPPI41_PKT_LEN_MASK		(0x1fffff << CPPI41_PKT_LEN_SHIFT)
- + 
- + #define CPPI41_PKT_ERROR_SHIFT		31
- + #define CPPI41_PKT_ERROR_MASK		(1 << CPPI41_PKT_ERROR_SHIFT)
- + #define CPPI41_PKT_TYPE_SHIFT		26
- + #define CPPI41_PKT_TYPE_MASK		(0x1f << CPPI41_PKT_TYPE_SHIFT)
- + #define CPPI41_PKT_TYPE_ATM_AAL5	0
- + #define CPPI41_PKT_TYPE_ATM_NULL_AAL	1
- + #define CPPI41_PKT_TYPE_ATM_OAM		2
- + #define CPPI41_PKT_TYPE_ATM_TRANSPARENT	3
- + #define CPPI41_PKT_TYPE_EFM		4
- + #define CPPI41_PKT_TYPE_USB		5
- + #define CPPI41_PKT_TYPE_GENERIC		6
- + #define CPPI41_PKT_TYPE_ETHERNET	7
- + #define CPPI41_ZLP			(1 << 19)
- + #define CPPI41_RETURN_POLICY_SHIFT	15
- + #define CPPI41_RETURN_POLICY_MASK	(1 << CPPI41_RETURN_POLICY_SHIFT)
- + #define CPPI41_RETURN_LINKED		0
- + #define CPPI41_RETURN_UNLINKED		1
- + #define CPPI41_ONCHIP_SHIFT		14
- + #define CPPI41_ONCHIP_MASK		(1 << CPPI41_ONCHIP_SHIFT)
- + #define CPPI41_RETURN_QMGR_SHIFT	12
- + #define CPPI41_RETURN_QMGR_MASK		(3 << CPPI41_RETURN_QMGR_SHIFT)
- + #define CPPI41_RETURN_QNUM_SHIFT	0
- + #define CPPI41_RETURN_QNUM_MASK		(0xfff << CPPI41_RETURN_QNUM_SHIFT)
- + 
- + #define CPPI41_SRC_TAG_PORT_NUM_SHIFT	27
- + #define CPPI41_SRC_TAG_PORT_NUM_MASK	(0x1f << CPPI41_SRC_TAG_PORT_NUM_SHIFT)
- + #define CPPI41_SRC_TAG_CH_NUM_SHIFT	21
- + #define CPPI41_SRC_TAG_CH_NUM_MASK	(0x3f << CPPI41_SRC_TAG_CH_NUM_SHIFT)
- + #define CPPI41_SRC_TAG_SUB_CH_NUM_SHIFT 16
- + #define CPPI41_SRC_TAG_SUB_CH_NUM_MASK	(0x1f << \
- + 					CPPI41_SRC_TAG_SUB_CH_NUM_SHIFT)
- + #define CPPI41_DEST_TAG_SHIFT		0
- + #define CPPI41_DEST_TAG_MASK		(0xffff << CPPI41_DEST_TAG_SHIFT)
- + #define CPPI41_PKT_INTR_FLAG		(1 << 31)
- + 
- + /*
- +  * CPPI 4.1 Teardown Descriptor
- +  */
- + struct cppi41_teardown_desc {
- + 	u32 teardown_info;	/* Teardown information */
- + 	u32 reserved[7];	/* 28 byte padding */
- + };
- + 
- + #define CPPI41_TEARDOWN_TX_RX_SHIFT	16
- + #define CPPI41_TEARDOWN_TX_RX_MASK	(1 << CPPI41_TEARDOWN_TX_RX_SHIFT)
- + #define CPPI41_TEARDOWN_DMA_NUM_SHIFT	10
- + #define CPPI41_TEARDOWN_DMA_NUM_MASK	(0x3f << CPPI41_TEARDOWN_DMA_NUM_SHIFT)
- + #define CPPI41_TEARDOWN_CHAN_NUM_SHIFT	0
- + #define CPPI41_TEARDOWN_CHAN_NUM_MASK	(0x3f << CPPI41_TEARDOWN_CHAN_NUM_SHIFT)
- + 
- + #define CPPI41_MAX_MEM_RGN		16
- + 
- + /* CPPI 4.1 configuration for AM3517 */
- + #define CPPI41_NUM_QUEUE_MGR		1	/* 4  max */
- + #define CPPI41_NUM_DMA_BLOCK		1	/* 64 max */
- + #define cppi41_num_queue_mgr	CPPI41_NUM_QUEUE_MGR
- + #define cppi41_num_dma_block	CPPI41_NUM_DMA_BLOCK
- + 
- + /**
- +  * struct cppi41_queue_manager - CPPI 4.1 DMA queue manager registers for
- +  * context save and restore.
- +  */
- + struct cppi41_queue_manager {
- + 	u32	link_ram_rgn0_base;
- + 	u32	link_ram_rgn0_size;
- + 	u32	link_ram_rgn1_base;
- + 
- + 	u32	memr_base[8];
- + 	u32	memr_ctrl[8];
- + };
- + 
- + /**
- +  * struct cppi41_dma_regs - CPPI 4.1 DMA registers for
- +  * context save and restore.
- +  */
- + struct cppi41_dma_regs {
- + 	u32	teardn_fdq_ctrl;
- + 	u32	emulation_ctrl;
- + 
- + 	/* CPPI DMA scheduler registers */
- + 	u32	sched_ctrl;
- + 
- + 	/* Queue manager registers */
- + 	struct cppi41_queue_manager qmgr;
- + };
- + 
- + /**
- +  * struct cppi41_queue - Queue Tuple
- +  *
- +  * The basic queue tuple in CPPI 4.1 used across all data structures
- +  * where a definition of a queue is required.
- +  */
- + struct cppi41_queue {
- + 	u8  q_mgr;		/* The queue manager number */
- + 	u16 q_num;		/* The queue number */
- + };
- + 
- + /**
- +  * struct cppi41_buf_pool - Buffer Pool Tuple
- +  *
- +  * The basic buffer pool tuple in CPPI 4.1 used across all data structures
- +  * where a definition of a buffer pool is required.
- +  */
- + struct cppi41_buf_pool {
- + 	u8  b_mgr;		/* The buffer manager number */
- + 	u16 b_pool;		/* The buffer pool number */
- + };
- + 
- + /**
- +  * struct cppi41_queue_mgr - Queue Manager information
- +  *
- +  * Contains the information about the queue manager which should be copied from
- +  * the hardware spec as is.
- +  */
- + struct cppi41_queue_mgr {
- + 	void __iomem *q_mgr_rgn_base; /* Base address of the Control region. */
- + 	void __iomem *desc_mem_rgn_base; /* Base address of the descriptor */
- + 				/* memory region. */
- + 	void __iomem *q_mgmt_rgn_base; /* Base address of the queues region. */
- + 	void __iomem *q_stat_rgn_base; /* Base address of the queue status */
- + 				/* region. */
- + 	u16 num_queue;		/* Number of the queues supported. */
- + 	u8 queue_types;		/* Bitmask of the supported queue types. */
- + 	u16 base_fdq_num;	/* The base free descriptor queue number. */
- + 				/* If present, there's always 16 such queues. */
- + 	u16 base_fdbq_num;	/* The base free descriptor/buffer queue */
- + 				/* number.  If present, there's always 16 */
- + 				/* such queues. */
- + 	const u32 *assigned;	/* Pointer to the bitmask of the pre-assigned */
- + 				/* queues. */
- + };
- + 
- + /* Queue type flags */
- + #define CPPI41_FREE_DESC_QUEUE		0x01
- + #define CPPI41_FREE_DESC_BUF_QUEUE	0x02
- + #define CPPI41_UNASSIGNED_QUEUE		0x04
- + 
- + /**
- +  * struct cppi41_embed_pkt_cfg - Rx Channel Embedded packet configuration
- +  *
- +  * An instance of this structure forms part of the Rx channel information
- +  * structure.
- +  */
- + struct cppi41_embed_pkt_cfg {
- + 	struct cppi41_queue fd_queue; /* Free Descriptor queue.*/
- + 	u8 num_buf_slot;	/* Number of buffer slots in the descriptor */
- + 	u8 sop_slot_num;	/* SOP buffer slot number. */
- + 	struct cppi41_buf_pool free_buf_pool[4]; /* Free Buffer pool. Element */
- + 				/* 0 used for the 1st Rx buffer, etc. */
- + };
- + 
- + /**
- +  * struct cppi41_host_pkt_cfg - Rx Channel Host Packet Configuration
- +  *
- +  * An instance of this structure forms part of the Rx channel information
- +  * structure.
- +  */
- + struct cppi41_host_pkt_cfg {
- + 	struct cppi41_queue fdb_queue[4]; /* Free Desc/Buffer queue. Element */
- + 				/* 0 used for 1st Rx buffer, etc. */
- + };
- + 
- + /**
- +  * struct cppi41_mono_pkt_cfg - Rx Channel Monolithic Packet Configuration
- +  *
- +  * An instance of this structure forms part of the Rx channel information
- +  * structure.
- +  */
- + struct cppi41_mono_pkt_cfg {
- + 	struct cppi41_queue fd_queue; /* Free descriptor queue */
- + 	u8 sop_offset;		/* Number of bytes to skip before writing */
- + 				/* payload */
- + };
- + 
- + enum cppi41_rx_desc_type {
- + 	cppi41_rx_embed_desc,
- + 	cppi41_rx_host_desc,
- + 	cppi41_rx_mono_desc,
- + };
- + 
- + /**
- +  * struct cppi41_rx_ch_cfg - Rx Channel Configuration
- +  *
- +  * Must be allocated and filled by the caller of cppi41_rx_ch_configure().
- +  *
- +  * The same channel can be configured to receive different descripor type
- +  * packets (not simaltaneously). When the Rx packets on a port need to be sent
- +  * to the SR, the channels default descriptor type is set to Embedded and the
- +  * Rx completion queue is set to the queue which CPU polls for input packets.
- +  * When in SR bypass mode, the same channel's default descriptor type will be
- +  * set to Host and the Rx completion queue set to one of the queues which host
- +  * can get interrupted on (via the Queuing proxy/accumulator). In this example,
- +  * the embedded mode configuration fetches free descriptor from the Free
- +  * descriptor queue (as defined by struct cppi41_embed_pkt_cfg) and host
- +  * mode configuration fetches free descriptors/buffers from the free descriptor/
- +  * buffer queue (as defined by struct cppi41_host_pkt_cfg).
- +  *
- +  * NOTE: There seems to be no separate configuration for teardown completion
- +  * descriptor. The assumption is rxQueue tuple is used for this purpose as well.
- +  */
- + struct cppi41_rx_ch_cfg {
- + 	enum cppi41_rx_desc_type default_desc_type; /* Describes which queue */
- + 				/* configuration is used for the free */
- + 				/* descriptors and/or buffers */
- + 	u8 sop_offset;		/* Number of bytes to skip in SOP buffer */
- + 				/* before writing payload */
- + 	u8 retry_starved;	/* 0 = Drop packet on descriptor/buffer */
- + 				/* starvartion, 1 = DMA retries FIFO block */
- + 				/* transfer at a later time */
- + 	u8 rx_max_buf_cnt;	/* The DMA ignores the SOP bit and closes up
- + 				 * a packet after a max_buf_cnt buffer has been
- + 				 * filled OR if the EOP field is set in the
- + 				 * info word 0
- + 				 */
- + 	struct cppi41_queue rx_queue; /* Rx complete packets queue */
- + 	union {
- + 		struct cppi41_host_pkt_cfg host_pkt; /* Host packet */
- + 				/* configuration. This defines where channel */
- + 				/* picks free descriptors from. */
- + 		struct cppi41_embed_pkt_cfg embed_pkt; /* Embedded packet */
- + 				/* configuration. This defines where channel */
- + 				/* picks free descriptors/buffers from. */
- + 				/* from. */
- + 		struct cppi41_mono_pkt_cfg mono_pkt; /* Monolithic packet */
- + 				/* configuration. This defines where channel */
- + 				/* picks free descriptors from. */
- + 	} cfg;			/* Union of packet configuration structures */
- + 				/* to be filled in depending on the */
- + 				/* defDescType field. */
- + };
- + 
- + /**
- +  * struct cppi41_tx_ch - Tx channel information
- +  *
- +  * NOTE: The queues that feed into the Tx channel are fixed at SoC design time.
- +  */
- + struct cppi41_tx_ch {
- + 	u8 port_num;		/* Port number. */
- + 	u8 ch_num;		/* Channel number within port. */
- + 	u8 sub_ch_num;		/* Sub-channel number within channel. */
- + 	u8 num_tx_queue;	/* Number of queues from which the channel */
- + 				/* can feed. */
- + 	struct cppi41_queue tx_queue[4]; /* List of queues from which the */
- + 				/* channel can feed. */
- + };
- + 
- + /**
- +  * struct cppi41_dma_block - CPPI 4.1 DMA configuration
- +  *
- +  * Configuration information for CPPI DMA functionality. Includes the Global
- +  * configuration, Channel configuration, and the Scheduler configuration.
- +  */
- + struct cppi41_dma_block {
- + 	void __iomem *global_ctrl_base; /* Base address of the Global Control */
- + 				/* registers. */
- + 	void __iomem *ch_ctrl_stat_base; /* Base address of the Channel */
- + 				/* Control/Status registers. */
- + 	void __iomem *sched_ctrl_base; /* Base address of the Scheduler */
- + 				/* Control register. */
- + 	void __iomem *sched_table_base; /* Base address of the Scheduler */
- + 				/* Table registers. */
- + 	u8 num_tx_ch;		/* Number of the Tx channels. */
- + 	u8 num_rx_ch;		/* Number of the Rx channels. */
- + 	u8 num_max_ch;		/* maximum dma channels */
- + 	const struct cppi41_tx_ch *tx_ch_info;
- + 	struct cppi41_dma_regs cppi41_regs; /* registers to save and restore */
- + };
- + 
- + extern struct cppi41_queue_mgr cppi41_queue_mgr[];
- + extern struct cppi41_dma_block cppi41_dma_block[];
- + 
- + /**
- +  * struct cppi41_dma_ch_obj - CPPI 4.1 DMA Channel object
- +  */
- + struct cppi41_dma_ch_obj {
- + 	void __iomem *base_addr; /* The address of the channel global */
- + 				/* configuration register */
- + 	u32 global_cfg;		/* Tx/Rx global configuration backed-up value */
- + };
- + 
- + /**
- +  * struct cppi41_queue_obj - CPPI 4.1 queue object
- +  */
- + struct cppi41_queue_obj {
- + 	void __iomem *base_addr; /* The base address of the queue management */
- + 				/* registers */
- + };
- + 
- + static inline u32 cppi_readl(const void __iomem *addr)
- + 	{ return readl(addr); }
- + static inline void cppi_writel(u32 data, void __iomem *addr)
- + 	{ writel(data, addr); }
- + /**
- +  * cppi41_queue_mgr_init - CPPI 4.1 queue manager initialization.
- +  * @q_mgr:	the queue manager to initialize
- +  * @rgn0_base:	linking RAM region 0 physical address
- +  * @rgn0_size:	linking RAM region 0 size in 32-bit words (0 to 0x3fff)
- +  *
- +  * Returns 0 on success, error otherwise.
- +  */
- + int cppi41_queue_mgr_init(u8 q_mgr, dma_addr_t rgn0_base, u16 rgn0_size);
- + 
- + /**
- +  * cppi41_queue_mgr_init - CPPI 4.1 queue manager un-initialization.
- +  * @q_mgr:	the queue manager to un-initialize
- +  * Returns 0 on success, error otherwise.
- +  */
- + int cppi41_queue_mgr_uninit(u8 q_mgr);
- + 
- + /*
- +  * CPPI 4.1 Queue Manager Memory Region Allocation and De-allocation APIs.
- +  */
- + 
- + /**
- +  * cppi41_mem_rgn_alloc - CPPI 4.1 queue manager memory region allocation.
- +  * @q_mgr:	the queue manager whose memory region to allocate
- +  * @rgn_addr:	physical address of the memory region
- +  * @size_order:	descriptor size as a power of two (between 5 and 13)
- +  * @num_order:	number of descriptors as a power of two (between 5 and 12)
- +  * @mem_rgn:	pointer to the index of the memory region allocated
- +  *
- +  * This function allocates a memory region within the queue manager
- +  * consisiting of the descriptors of paricular size and number.
- +  *
- +  * Returns 0 on success, error otherwise.
- +  */
- + int cppi41_mem_rgn_alloc(u8 q_mgr, dma_addr_t rgn_addr, u8 size_order,
- + 			 u8 num_order, u8 *mem_rgn);
- + 
- + /**
- +  * cppi41_mem_rgn_free - CPPI 4.1 queue manager memory region de-allocation.
- +  * @q_mgr:	the queue manager whose memory region was allocated
- +  * @mem_rgn:	index of the memory region
- +  *
- +  * This function frees the memory region allocated by cppi41_mem_rgn_alloc().
- +  *
- +  * Returns 0 on success, -EINVAL otherwise.
- +  */
- + int cppi41_mem_rgn_free(u8 q_mgr, u8 mem_rgn);
- + 
- + /**
- +  * cppi41_dma_block_init - CPPI 4.1 DMA block initialization.
- +  * @dma_num:	number of the DMA block
- +  * @q_mgr:	the queue manager in which to allocate the free teardown
- +  *		descriptor queue
- +  * @num_order:	number of teardown descriptors as a power of two (at least 5)
- +  * @sched_tbl:	the DMA scheduler table
- +  * @tbl_size:	number of entries in the DMA scheduler table
- +  *
- +  * This function frees the memory region allocated by cppi41_mem_rgn_alloc().
- +  *
- +  * Returns 0 on success, error otherwise.
- +  */
- + int cppi41_dma_block_init(u8 dma_num, u8 q_mgr, u8 num_order,
- + 				 u32 *sched_tbl, u8 tbl_size);
- + 
- + /**
- +  * cppi41_dma_block_init - CPPI 4.1 DMA block un-initialization.
- +  * @dma_num:	number of the DMA block
- +  * @q_mgr:	the queue manager in which to allocate the free teardown
- +  *		descriptor queue
- +  * @num_order:	number of teardown descriptors as a power of two (at least 5)
- +  * @sched_tbl:	the DMA scheduler table
- +  * @tbl_size:	number of entries in the DMA scheduler table
- +  *
- +  * Returns 0 on success, error otherwise.
- +  */
- + int cppi41_dma_block_uninit(u8 dma_num, u8 q_mgr, u8 num_order,
- + 				 u32 *sched_tbl, u8 tbl_size);
- + 
- + /*
- +  * CPPI 4.1 DMA Channel Management APIs
- +  */
- + 
- + /**
- +  * cppi41_tx_ch_init - initialize CPPI 4.1 transmit channel object
- +  * @tx_ch_obj:	pointer to Tx channel object
- +  * @dma_num:	DMA block to which this channel belongs
- +  * @ch_num:	DMA channel number
- +  *
- +  * Returns 0 if valid Tx channel, -EINVAL otherwise.
- +  */
- + int cppi41_tx_ch_init(struct cppi41_dma_ch_obj *tx_ch_obj,
- + 		      u8 dma_num, u8 ch_num);
- + 
- + /**
- +  * cppi41_rx_ch_init - initialize CPPI 4.1 receive channel object
- +  * @rx_ch_obj:	pointer to Rx channel object
- +  * @dma_num:	DMA block to which this channel belongs
- +  * @ch_num:	DMA channel number
- +  *
- +  * Returns 0 if valid Rx channel, -EINVAL otherwise.
- +  */
- + int cppi41_rx_ch_init(struct cppi41_dma_ch_obj *rx_ch_obj,
- + 		      u8 dma_num, u8 ch_num);
- + 
- + /**
- +  * cppi41_dma_ch_default_queue - set CPPI 4.1 channel default completion queue
- +  * @dma_ch_obj: pointer to DMA channel object
- +  * @q_mgr:	default queue manager
- +  * @q_num:	default queue number
- +  *
- +  * This function configures the specified channel.  The caller is required to
- +  * provide the default queue onto which the teardown descriptors will be queued.
- +  */
- + void cppi41_dma_ch_default_queue(struct cppi41_dma_ch_obj *dma_ch_obj,
- + 				 u8 q_mgr, u16 q_num);
- + 
- + /**
- +  * cppi41_rx_ch_configure - configure CPPI 4.1 receive channel
- +  * @rx_ch_obj:	pointer to Rx channel object
- +  * @cfg:	pointer to Rx channel configuration
- +  *
- +  * This function configures and opens the specified Rx channel.  The caller
- +  * is required to provide channel configuration information by initializing
- +  * a struct cppi41_rx_ch_cfg.
- +  */
- + void cppi41_rx_ch_configure(struct cppi41_dma_ch_obj *rx_ch_obj,
- + 			    struct cppi41_rx_ch_cfg  *cfg);
- + 
- + /**
- +  * cppi41_rx_ch_set_maxbufcnt - configure max rx buffer count
- +  * @rx_ch_obj:	pointer to Rx channel object
- +  * rx_max_buf_cnt: maximum rx buffer count
- +  *
- +  * This function configures the maximum rx buffer count in rx dma
- +  * global configuration register. The valid rx_max_buf_cnt value
- +  * must be 0 to 4.
- +  */
- + void cppi41_rx_ch_set_maxbufcnt(struct cppi41_dma_ch_obj *rx_ch_obj,
- + 			    u8 rx_max_buf_cnt);
- + /**
- +  * cppi41_dma_ch_enable - enable CPPI 4.1 Tx/Rx DMA channel
- +  * @dma_ch_obj:	pointer to DMA channel object
- +  *
- +  * This function enables  a specified Tx channel.  The caller is required to
- +  * provide a reference to a channel object initialized by an earlier call of
- +  * the cppi41_dma_ch_init() function.  After the successful completion of this
- +  * function, the Tx DMA channel will be active and ready for data transmission.
- +  */
- + void cppi41_dma_ch_enable(struct cppi41_dma_ch_obj *dma_ch_obj);
- + 
- + /**
- +  * cppi41_dma_ch_disable - disable CPPI 4.1 Tx/Rx DMA channel
- +  * @dma_ch_obj:	pointer to DMA channel object
- +  *
- +  * This function disables a specific Tx channel.  The caller is required to
- +  * provide a reference to a channel object initialized by an earlier call of
- +  * the cppi41_dma_ch_init() function.  After the successful completion of this
- +  * function, the Tx DMA channel will be deactived.
- +  */
- + void cppi41_dma_ch_disable(struct cppi41_dma_ch_obj *dma_ch_obj);
- + 
- + /**
- +  * cppi41_dma_ch_teardown - tear down CPPI 4.1 transmit channel
- +  * @dma_ch_obj:	pointer DMA channel object
- +  *
- +  * This function triggers the teardown of the given DMA channel.
- +  *
- +  * ATTENTION: Channel disable should not be called before the teardown is
- +  * completed as a disable will stop the DMA scheduling on the channel resulting
- +  * in the teardown complete event not being registered at all.
- +  *
- +  * NOTE: A successful channel teardown event is reported via queueing of a
- +  * teardown descriptor.
- +  *
- +  * This function just sets up for the teardown of the channel and returns. The
- +  * caller must detect the channel teardown event to assume that the channel is
- +  * disabled.
- +  *
- +  * See cppi41_get_teardown_info() for the teardown completion processing.
- +  */
- + void cppi41_dma_ch_teardown(struct cppi41_dma_ch_obj *dma_ch_obj);
- + 
- + /*
- +  * CPPI 4.1 Queue Allocation and De-allocation APIs.
- +  */
- + 
- + /**
- +  * cppi41_queue_alloc - allocate CPPI 4.1 queue
- +  * @type:	queue type bitmask
- +  * @q_mgr:	queue manager
- +  * @q_num:	pointer to the queue number
- +  *
- +  * Returns 0 if queue allocated, error otherwise.
- +  */
- + int cppi41_queue_alloc(u8 type, u8 q_mgr, u16 *q_num);
- + 
- + /**
- +  * cppi41_queue_free - de-allocate CPPI 4.1 queue
- +  * @q_mgr:	queue manager
- +  * @q_num:	queue number
- +  *
- +  * Returns 0 on success, -EINVAL otherwise.
- +  */
- + int cppi41_queue_free(u8 q_mgr, u16 q_num);
- + 
- + /*
- +  *  CPPI 4.1 Queue Management APIs
- +  */
- + 
- + /**
- +  * cppi41_queue_init - initialize CPPI 4.1 queue object
- +  * @queue_obj:	pointer to the queue object
- +  * @q_mgr:	queue manager
- +  * @q_num:	queue number
- +  *
- +  * Returns 0 if valid queue, -EINVAL otherwise.
- +  */
- + int cppi41_queue_init(struct cppi41_queue_obj *queue_obj, u8 q_mgr, u16 q_num);
- + 
- + /**
- +  * cppi41_queue_push - push to CPPI 4.1 queue
- +  * @queue_obj:	pointer to the queue object
- +  * @desc_addr:	descriptor physical address
- +  * @desc_size:	descriptor size
- +  * @pkt_size:	packet size
- +  *
- +  * This function is called to queue a descriptor onto a queue.
- +  * NOTE: pSize parameter is optional. Pass 0 in case not required.
- +  */
- + void cppi41_queue_push(const struct cppi41_queue_obj *queue_obj, u32 desc_addr,
- + 		       u32 desc_size, u32 pkt_size);
- + 
- + /**
- +  * cppi41_queue_pop - pop from CPPI 4.1 queue
- +  * @queue_obj:	pointer to the queue object
- +  *
- +  * This function is called to pop a single descriptor from the queue.
- +  *
- +  * Returns a packet descriptor's physical address.
- +  */
- + unsigned long cppi41_queue_pop(const struct cppi41_queue_obj *queue_obj);
- + 
- + /*
- +  * CPPI 4.1 Miscellaneous APIs
- +  */
- + 
- + /**
- +  * cppi41_get_teardown_info - CPPI 4.1 teardown completion processing function
- +  *
- +  * @addr:	physical address of teardown descriptor
- +  * @info:	pointer to the teardown information word
- +  *
- +  * This function is called to complete the teardown processing on a channel
- +  * and provides teardown information from the teardown descriptor passed to it.
- +  * It also recycles the teardown descriptor back to the teardown descriptor
- +  * queue.
- +  *
- +  * Returns 0 if valid descriptor, -EINVAL otherwise.
- +  */
- + int cppi41_get_teardown_info(unsigned long addr, u32 *info);
- + 
- + /**
- +  * cppi41_dma_sched_tbl_init
- +  */
- + int cppi41_dma_sched_tbl_init(u8 dma_num, u8 q_mgr,
- + 				u32 *sched_tbl, u8 tbl_size);
- + 
- + /**
- +  * cppi41_schedtbl_add_dma_ch - add a dma channel to schedular table
- +  *
- +  * @dmanum      Number of DMa block
- +  * @qmgr        Queue Manager Number
- +  * @dma_ch      dma channel number
- +  * @is_tx       transmit (is_tx=1) or recieve(is_tx=0)
- +  *
- +  * returns      number of channel in schedular table
- +  */
- + int cppi41_schedtbl_add_dma_ch(u8 dmanum, u8 qmgr, u8 dma_ch, u8 is_tx);
- + 
- + /**
- +  * cppi41_schedtbl_remove_dma_ch - remove a dma channel from schedular table
- +  *
- +  * @dmanum      Number of DMa block
- +  * @qmgr        Queue Manager Number
- +  * @dma_ch      dma channel number
- +  * @is_tx       transmit (is_tx=1) or recieve(is_tx=0)
- +  *
- +  * returns      number of channel in schedular table
- +  */
- + int cppi41_schedtbl_remove_dma_ch(u8 dmanum, u8 qmgr, u8 dma_ch, u8 is_tx);
- + 
- + /**
- +  * cppi41_init_teardown_queue
- +  */
- + void cppi41_init_teardown_queue(int dma_num);
- + 
- + /**
- +  * cppi41_free_teardown_queue
- +  */
- + void cppi41_free_teardown_queue(int dma_num);
- + 
- + /**
- +  * cppi41_save_context
- +  */
- + void cppi41_save_context(u8 dma_num);
- + 
- + /**
- +  * cppi41_restore_context
- +  */
- + void cppi41_restore_context(u8 dma_num, u32 *sched_tbl);
- diff -crN linux-3.2.1_o/drivers/usb/musb/cppi_dma.c linux-3.2.1/drivers/usb/musb/cppi_dma.c
- *** linux-3.2.1_o/drivers/usb/musb/cppi_dma.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/musb/cppi_dma.c	2014-05-15 13:25:15.079322705 +0900
- ***************
- *** 104,110 ****
-   	musb_writel(&tx->tx_complete, 0, ptr);
-   }
-   
- ! static void __init cppi_pool_init(struct cppi *cppi, struct cppi_channel *c)
-   {
-   	int	j;
-   
- --- 104,110 ----
-   	musb_writel(&tx->tx_complete, 0, ptr);
-   }
-   
- ! static void __devinit cppi_pool_init(struct cppi *cppi, struct cppi_channel *c)
-   {
-   	int	j;
-   
- ***************
- *** 149,155 ****
-   	c->last_processed = NULL;
-   }
-   
- ! static int __init cppi_controller_start(struct dma_controller *c)
-   {
-   	struct cppi	*controller;
-   	void __iomem	*tibase;
- --- 149,155 ----
-   	c->last_processed = NULL;
-   }
-   
- ! static int __devinit cppi_controller_start(struct dma_controller *c)
-   {
-   	struct cppi	*controller;
-   	void __iomem	*tibase;
- ***************
- *** 359,366 ****
-   {
-   	void __iomem			*base = c->controller->mregs;
-   	struct cppi_rx_stateram __iomem	*rx = c->state_ram;
-   
- ! 	musb_ep_select(base, c->index + 1);
-   
-   	dev_dbg(c->controller->musb->controller,
-   		"RX DMA%d%s: %d left, csr %04x, "
- --- 359,367 ----
-   {
-   	void __iomem			*base = c->controller->mregs;
-   	struct cppi_rx_stateram __iomem	*rx = c->state_ram;
- + 	struct musb		*musb = c->controller->musb;
-   
- ! 	musb_ep_select(musb, base, c->index + 1);
-   
-   	dev_dbg(c->controller->musb->controller,
-   		"RX DMA%d%s: %d left, csr %04x, "
- ***************
- *** 390,397 ****
-   {
-   	void __iomem			*base = c->controller->mregs;
-   	struct cppi_tx_stateram __iomem	*tx = c->state_ram;
-   
- ! 	musb_ep_select(base, c->index + 1);
-   
-   	dev_dbg(c->controller->musb->controller,
-   		"TX DMA%d%s: csr %04x, "
- --- 391,399 ----
-   {
-   	void __iomem			*base = c->controller->mregs;
-   	struct cppi_tx_stateram __iomem	*tx = c->state_ram;
- + 	struct musb		*musb = c->controller->musb;
-   
- ! 	musb_ep_select(musb, base, c->index + 1);
-   
-   	dev_dbg(c->controller->musb->controller,
-   		"TX DMA%d%s: csr %04x, "
- ***************
- *** 513,519 ****
-   		if (!(val & MUSB_RXCSR_H_REQPKT)) {
-   			val |= MUSB_RXCSR_H_REQPKT | MUSB_RXCSR_H_WZC_BITS;
-   			musb_writew(regs, MUSB_RXCSR, val);
- ! 			/* flush writebufer */
-   			val = musb_readw(regs, MUSB_RXCSR);
-   		}
-   	}
- --- 515,521 ----
-   		if (!(val & MUSB_RXCSR_H_REQPKT)) {
-   			val |= MUSB_RXCSR_H_REQPKT | MUSB_RXCSR_H_WZC_BITS;
-   			musb_writew(regs, MUSB_RXCSR, val);
- ! 			/* flush writebuffer */
-   			val = musb_readw(regs, MUSB_RXCSR);
-   		}
-   	}
- ***************
- *** 1117,1123 ****
-   			 */
-   			WARN_ON(rx->head);
-   		}
- ! 		musb_ep_select(cppi->mregs, rx->index + 1);
-   		csr = musb_readw(regs, MUSB_RXCSR);
-   		if (csr & MUSB_RXCSR_DMAENAB) {
-   			dev_dbg(musb->controller, "list%d %p/%p, last %llx%s, csr %04x\n",
- --- 1119,1125 ----
-   			 */
-   			WARN_ON(rx->head);
-   		}
- ! 		musb_ep_select(cppi->musb, cppi->mregs, rx->index + 1);
-   		csr = musb_readw(regs, MUSB_RXCSR);
-   		if (csr & MUSB_RXCSR_DMAENAB) {
-   			dev_dbg(musb->controller, "list%d %p/%p, last %llx%s, csr %04x\n",
- ***************
- *** 1315,1322 ****
-   }
-   
-   /* Instantiate a software object representing a DMA controller. */
- ! struct dma_controller *__init
- ! dma_controller_create(struct musb *musb, void __iomem *mregs)
-   {
-   	struct cppi		*controller;
-   	struct device		*dev = musb->controller;
- --- 1317,1324 ----
-   }
-   
-   /* Instantiate a software object representing a DMA controller. */
- ! struct dma_controller *__devinit
- ! cppi_dma_controller_create(struct musb *musb, void __iomem *mregs)
-   {
-   	struct cppi		*controller;
-   	struct device		*dev = musb->controller;
- ***************
- *** 1355,1361 ****
-   	if (irq > 0) {
-   		if (request_irq(irq, cppi_interrupt, 0, "cppi-dma", musb)) {
-   			dev_err(dev, "request_irq %d failed!\n", irq);
- ! 			dma_controller_destroy(&controller->controller);
-   			return NULL;
-   		}
-   		controller->irq = irq;
- --- 1357,1363 ----
-   	if (irq > 0) {
-   		if (request_irq(irq, cppi_interrupt, 0, "cppi-dma", musb)) {
-   			dev_err(dev, "request_irq %d failed!\n", irq);
- ! 			cppi_dma_controller_destroy(&controller->controller);
-   			return NULL;
-   		}
-   		controller->irq = irq;
- ***************
- *** 1363,1373 ****
-   
-   	return &controller->controller;
-   }
-   
-   /*
-    *  Destroy a previously-instantiated DMA controller.
-    */
- ! void dma_controller_destroy(struct dma_controller *c)
-   {
-   	struct cppi	*cppi;
-   
- --- 1365,1376 ----
-   
-   	return &controller->controller;
-   }
- + EXPORT_SYMBOL(cppi_dma_controller_create);
-   
-   /*
-    *  Destroy a previously-instantiated DMA controller.
-    */
- ! void cppi_dma_controller_destroy(struct dma_controller *c)
-   {
-   	struct cppi	*cppi;
-   
- ***************
- *** 1381,1386 ****
- --- 1384,1390 ----
-   
-   	kfree(cppi);
-   }
- + EXPORT_SYMBOL(cppi_dma_controller_destroy);
-   
-   /*
-    * Context: controller irqlocked, endpoint selected
- ***************
- *** 1428,1434 ****
-   	 * and caller should rely on us not changing it.
-   	 * peripheral code is safe ... check host too.
-   	 */
- ! 	musb_ep_select(mbase, cppi_ch->index + 1);
-   
-   	if (cppi_ch->transmit) {
-   		struct cppi_tx_stateram __iomem *tx_ram;
- --- 1432,1438 ----
-   	 * and caller should rely on us not changing it.
-   	 * peripheral code is safe ... check host too.
-   	 */
- ! 	musb_ep_select(controller->musb, mbase, cppi_ch->index + 1);
-   
-   	if (cppi_ch->transmit) {
-   		struct cppi_tx_stateram __iomem *tx_ram;
- ***************
- *** 1561,1563 ****
- --- 1565,1580 ----
-    * Power Management ... probably turn off cppi during suspend, restart;
-    * check state ram?  Clocking is presumably shared with usb core.
-    */
- + MODULE_DESCRIPTION("CPPI dma controller driver for musb");
- + MODULE_LICENSE("GPL v2");
- + 
- + static int __init cppi_dma_init(void)
- + {
- + 	return 0;
- + }
- + module_init(cppi_dma_init);
- + 
- + static void __exit cppi_dma__exit(void)
- + {
- + }
- + module_exit(cppi_dma__exit);
- diff -crN linux-3.2.1_o/drivers/usb/musb/da8xx.c linux-3.2.1/drivers/usb/musb/da8xx.c
- *** linux-3.2.1_o/drivers/usb/musb/da8xx.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/musb/da8xx.c	2014-05-15 13:25:15.082663686 +0900
- ***************
- *** 423,430 ****
-   	if (!rev)
-   		goto fail;
-   
- ! 	usb_nop_xceiv_register();
- ! 	musb->xceiv = otg_get_transceiver();
-   	if (!musb->xceiv)
-   		goto fail;
-   
- --- 423,430 ----
-   	if (!rev)
-   		goto fail;
-   
- ! 	usb_nop_xceiv_register(musb->id);
- ! 	musb->xceiv = otg_get_transceiver(musb->id);
-   	if (!musb->xceiv)
-   		goto fail;
-   
- ***************
- *** 458,469 ****
-   	phy_off();
-   
-   	otg_put_transceiver(musb->xceiv);
- ! 	usb_nop_xceiv_unregister();
-   
-   	return 0;
-   }
-   
-   static const struct musb_platform_ops da8xx_ops = {
-   	.init		= da8xx_musb_init,
-   	.exit		= da8xx_musb_exit,
-   
- --- 458,471 ----
-   	phy_off();
-   
-   	otg_put_transceiver(musb->xceiv);
- ! 	usb_nop_xceiv_unregister(musb->id);
-   
-   	return 0;
-   }
-   
-   static const struct musb_platform_ops da8xx_ops = {
- + 	.fifo_mode	= 2,
- + 	.flags		= MUSB_GLUE_EP_ADDR_FLAT_MAPPING,
-   	.init		= da8xx_musb_init,
-   	.exit		= da8xx_musb_exit,
-   
- ***************
- *** 474,479 ****
- --- 476,484 ----
-   	.try_idle	= da8xx_musb_try_idle,
-   
-   	.set_vbus	= da8xx_musb_set_vbus,
- + 
- + 	.read_fifo	= musb_read_fifo,
- + 	.write_fifo	= musb_write_fifo,
-   };
-   
-   static u64 da8xx_dmamask = DMA_BIT_MASK(32);
- diff -crN linux-3.2.1_o/drivers/usb/musb/davinci.c linux-3.2.1/drivers/usb/musb/davinci.c
- *** linux-3.2.1_o/drivers/usb/musb/davinci.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/musb/davinci.c	2014-05-15 13:25:15.082663686 +0900
- ***************
- *** 287,293 ****
-   	 * mask, state, "vector", and EOI registers.
-   	 */
-   	cppi = container_of(musb->dma_controller, struct cppi, controller);
- ! 	if (is_cppi_enabled() && musb->dma_controller && !cppi->irq)
-   		retval = cppi_interrupt(irq, __hci);
-   
-   	/* ack and handle non-CPPI interrupts */
- --- 287,293 ----
-   	 * mask, state, "vector", and EOI registers.
-   	 */
-   	cppi = container_of(musb->dma_controller, struct cppi, controller);
- ! 	if (is_cppi_enabled(musb) && musb->dma_controller && !cppi->irq)
-   		retval = cppi_interrupt(irq, __hci);
-   
-   	/* ack and handle non-CPPI interrupts */
- ***************
- *** 385,392 ****
-   	void __iomem	*tibase = musb->ctrl_base;
-   	u32		revision;
-   
- ! 	usb_nop_xceiv_register();
- ! 	musb->xceiv = otg_get_transceiver();
-   	if (!musb->xceiv)
-   		return -ENODEV;
-   
- --- 385,392 ----
-   	void __iomem	*tibase = musb->ctrl_base;
-   	u32		revision;
-   
- ! 	usb_nop_xceiv_register(musb->id);
- ! 	musb->xceiv = otg_get_transceiver(musb->id);
-   	if (!musb->xceiv)
-   		return -ENODEV;
-   
- ***************
- *** 446,452 ****
-   
-   fail:
-   	otg_put_transceiver(musb->xceiv);
- ! 	usb_nop_xceiv_unregister();
-   	return -ENODEV;
-   }
-   
- --- 446,452 ----
-   
-   fail:
-   	otg_put_transceiver(musb->xceiv);
- ! 	usb_nop_xceiv_unregister(musb->id);
-   	return -ENODEV;
-   }
-   
- ***************
- *** 495,506 ****
-   	phy_off();
-   
-   	otg_put_transceiver(musb->xceiv);
- ! 	usb_nop_xceiv_unregister();
-   
-   	return 0;
-   }
-   
-   static const struct musb_platform_ops davinci_ops = {
-   	.init		= davinci_musb_init,
-   	.exit		= davinci_musb_exit,
-   
- --- 495,508 ----
-   	phy_off();
-   
-   	otg_put_transceiver(musb->xceiv);
- ! 	usb_nop_xceiv_unregister(musb->id);
-   
-   	return 0;
-   }
-   
-   static const struct musb_platform_ops davinci_ops = {
- + 	.fifo_mode	= 2,
- + 	.flags		= MUSB_GLUE_EP_ADDR_FLAT_MAPPING | MUSB_GLUE_DMA_CPPI,
-   	.init		= davinci_musb_init,
-   	.exit		= davinci_musb_exit,
-   
- ***************
- *** 510,515 ****
- --- 512,523 ----
-   	.set_mode	= davinci_musb_set_mode,
-   
-   	.set_vbus	= davinci_musb_set_vbus,
- + 
- + 	.read_fifo	= musb_read_fifo,
- + 	.write_fifo	= musb_write_fifo,
- + 
- + 	.dma_controller_create = cppi_dma_controller_create,
- + 	.dma_controller_destroy = cppi_dma_controller_destroy,
-   };
-   
-   static u64 davinci_dmamask = DMA_BIT_MASK(32);
- diff -crN linux-3.2.1_o/drivers/usb/musb/Kconfig linux-3.2.1/drivers/usb/musb/Kconfig
- *** linux-3.2.1_o/drivers/usb/musb/Kconfig	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/musb/Kconfig	2014-05-15 13:25:15.082663686 +0900
- ***************
- *** 5,18 ****
-   
-   # (M)HDRC = (Multipoint) Highspeed Dual-Role Controller
-   config USB_MUSB_HDRC
-   	depends on USB && USB_GADGET
- - 	depends on (ARM || (BF54x && !BF544) || (BF52x && !BF522 && !BF523))
-   	select NOP_USB_XCEIV if (ARCH_DAVINCI || MACH_OMAP3EVM || BLACKFIN)
-   	select TWL4030_USB if MACH_OMAP_3430SDP
-   	select TWL6030_USB if MACH_OMAP_4430SDP || MACH_OMAP4_PANDA
-   	select USB_OTG_UTILS
-   	select USB_GADGET_DUALSPEED
- - 	tristate 'Inventra Highspeed Dual Role Controller (TI, ADI, ...)'
-   	help
-   	  Say Y here if your system has a dual role high speed USB
-   	  controller based on the Mentor Graphics silicon IP.  Then
- --- 5,18 ----
-   
-   # (M)HDRC = (Multipoint) Highspeed Dual-Role Controller
-   config USB_MUSB_HDRC
- + 	tristate 'Inventra Highspeed Dual Role Controller (TI, ADI, ...)'
-   	depends on USB && USB_GADGET
-   	select NOP_USB_XCEIV if (ARCH_DAVINCI || MACH_OMAP3EVM || BLACKFIN)
- + 	select NOP_USB_XCEIV if (SOC_OMAPTI81XX || SOC_OMAPAM33XX)
-   	select TWL4030_USB if MACH_OMAP_3430SDP
-   	select TWL6030_USB if MACH_OMAP_4430SDP || MACH_OMAP4_PANDA
-   	select USB_OTG_UTILS
-   	select USB_GADGET_DUALSPEED
-   	help
-   	  Say Y here if your system has a dual role high speed USB
-   	  controller based on the Mentor Graphics silicon IP.  Then
- ***************
- *** 31,110 ****
-   	  To compile this driver as a module, choose M here; the
-   	  module will be called "musb-hdrc".
-   
- ! choice
- ! 	prompt "Platform Glue Layer"
- ! 	depends on USB_MUSB_HDRC
-   
- ! config USB_MUSB_DAVINCI
-   	tristate "DaVinci"
- ! 	depends on ARCH_DAVINCI_DMx
-   
- ! config USB_MUSB_DA8XX
-   	tristate "DA8xx/OMAP-L1x"
- ! 	depends on ARCH_DAVINCI_DA8XX
-   
- ! config USB_MUSB_TUSB6010
-   	tristate "TUSB6010"
- ! 	depends on ARCH_OMAP
-   
- ! config USB_MUSB_OMAP2PLUS
-   	tristate "OMAP2430 and onwards"
- ! 	depends on ARCH_OMAP2PLUS
-   
- ! config USB_MUSB_AM35X
-   	tristate "AM35x"
- ! 	depends on ARCH_OMAP
-   
- ! config USB_MUSB_BLACKFIN
-   	tristate "Blackfin"
- ! 	depends on (BF54x && !BF544) || (BF52x && ! BF522 && !BF523)
-   
- ! config USB_MUSB_UX500
-   	tristate "U8500 and U5500"
- ! 	depends on (ARCH_U8500 && AB8500_USB)
-   
-   endchoice
-   
-   config MUSB_PIO_ONLY
-   	bool 'Disable DMA (always use PIO)'
- ! 	depends on USB_MUSB_HDRC
- ! 	default USB_MUSB_TUSB6010 || USB_MUSB_DA8XX || USB_MUSB_AM35X
-   	help
-   	  All data is copied between memory and FIFO by the CPU.
-   	  DMA controllers are ignored.
-   
- ! 	  Do not select 'n' here unless DMA support for your SOC or board
- ! 	  is unavailable (or unstable).  When DMA is enabled at compile time,
- ! 	  you can still disable it at run time using the "use_dma=n" module
- ! 	  parameter.
- ! 
- ! config USB_UX500_DMA
- ! 	bool
- ! 	depends on USB_MUSB_HDRC && !MUSB_PIO_ONLY
- ! 	default USB_MUSB_UX500
- ! 	help
- ! 	  Enable DMA transfers on UX500 platforms.
-   
-   config USB_INVENTRA_DMA
-   	bool
- ! 	depends on USB_MUSB_HDRC && !MUSB_PIO_ONLY
- ! 	default USB_MUSB_OMAP2PLUS || USB_MUSB_BLACKFIN
- ! 	help
- ! 	  Enable DMA transfers using Mentor's engine.
-   
-   config USB_TI_CPPI_DMA
-   	bool
- ! 	depends on USB_MUSB_HDRC && !MUSB_PIO_ONLY
- ! 	default USB_MUSB_DAVINCI
- ! 	help
- ! 	  Enable DMA transfers when TI CPPI DMA is available.
-   
-   config USB_TUSB_OMAP_DMA
-   	bool
- ! 	depends on USB_MUSB_HDRC && !MUSB_PIO_ONLY
- ! 	depends on USB_MUSB_TUSB6010
- ! 	depends on ARCH_OMAP
- ! 	default y
- ! 	help
- ! 	  Enable DMA transfers on TUSB 6010 when OMAP DMA is available.
-   
- --- 31,194 ----
-   	  To compile this driver as a module, choose M here; the
-   	  module will be called "musb-hdrc".
-   
- ! if USB_MUSB_HDRC
-   
- ! comment "Platform Glue Layer"
- ! 
- ! config USB_MUSB_DAVINCI_GLUE
- ! 	select USB_MUSB_DAVINCI
-   	tristate "DaVinci"
- ! 	depends on ARCH_DAVINCI_DMx && USB_MUSB_HDRC
-   
- ! config USB_MUSB_DA8XX_GLUE
- ! 	select USB_MUSB_DA8XX
-   	tristate "DA8xx/OMAP-L1x"
- ! 	depends on ARCH_DAVINCI_DA8XX && USB_MUSB_HDRC
-   
- ! config USB_MUSB_TUSB6010_GLUE
- ! 	select USB_MUSB_TUSB6010
-   	tristate "TUSB6010"
- ! 	depends on ARCH_OMAP && USB_MUSB_HDRC
-   
- ! config USB_MUSB_OMAP2PLUS_GLUE
- ! 	select USB_MUSB_OMAP2PLUS
-   	tristate "OMAP2430 and onwards"
- ! 	depends on ARCH_OMAP2PLUS && USB_MUSB_HDRC
-   
- ! config USB_MUSB_AM35X_GLUE
- ! 	select USB_MUSB_AM35X
-   	tristate "AM35x"
- ! 	depends on ARCH_OMAP && USB_MUSB_HDRC
-   
- ! config USB_MUSB_TI81XX_GLUE
- ! 	select USB_MUSB_TI81XX
- ! 	tristate "TI81XX onward"
- ! 	depends on (SOC_OMAPTI81XX || SOC_OMAPAM33XX) && USB_MUSB_HDRC
- ! 
- ! config USB_MUSB_BLACKFIN_GLUE
- ! 	select USB_MUSB_BLACKFIN
-   	tristate "Blackfin"
- ! 	depends on (BF54x && !BF544) || (BF52x && ! BF522 && !BF523) && USB_MUSB_HDRC
-   
- ! config USB_MUSB_UX500_GLUE
- ! 	select USB_MUSB_UX500
-   	tristate "U8500 and U5500"
- ! 	depends on (ARCH_U8500 && AB8500_USB) && USB_MUSB_HDRC
- ! 
- ! config USB_MUSB_DAVINCI
- ! 	bool
- ! 	default n
- ! config USB_MUSB_DA8XX
- ! 	bool
- ! 	default n
- ! config USB_MUSB_TUSB6010
- ! 	bool
- ! 	default n
- ! config USB_MUSB_OMAP2PLUS
- ! 	bool
- ! 	default n
- ! config USB_MUSB_AM35X
- ! 	bool
- ! 	default n
- ! config USB_MUSB_TI81XX
- ! 	bool
- ! 	default n
- ! config USB_MUSB_BLACKFIN
- ! 	bool
- ! 	default n
- ! config USB_MUSB_UX500
- ! 	bool
- ! 	default n
- ! 
- ! choice
- ! 	prompt 'MUSB DMA mode'
- ! 	depends on !MUSB_PIO_ONLY
- ! 	default USB_UX500_DMA_HW if USB_MUSB_UX500
- ! 	default USB_INVENTRA_DMA_HW if USB_MUSB_OMAP2PLUS || USB_MUSB_BLACKFIN
- ! 	default USB_TI_CPPI_DMA_HW if USB_MUSB_DAVINCI
- ! 	default USB_TUSB_OMAP_DMA_HW if USB_MUSB_TUSB6010
- ! 	default USB_TI_CPPI41_DMA_HW if USB_MUSB_DA8XX || USB_MUSB_AM35X || USB_MUSB_TI81XX
- ! 	help
- ! 	  Unfortunately, only one option can be enabled here. Ideally one
- ! 	  should be able to build all these drivers into one kernel to
- ! 	  allow using DMA on multiplatform kernels.
- ! 
- ! config USB_UX500_DMA_HW
- ! 	tristate 'ST Ericsson U8500 and U5500'
- ! 	select USB_UX500_DMA
- ! 	depends on USB_MUSB_UX500
- ! 	help
- ! 	  Enable DMA transfers on UX500 platforms.
- ! 
- ! config USB_INVENTRA_DMA_HW
- ! 	tristate 'Inventra'
- ! 	select USB_INVENTRA_DMA
- ! 	depends on (USB_MUSB_OMAP2PLUS || USB_MUSB_BLACKFIN) && !USB_MUSB_AM35X
- ! 	help
- ! 	  Enable DMA transfers using Mentor's engine.
- ! 
- ! config USB_TI_CPPI_DMA_HW
- ! 	tristate 'TI CPPI (Davinci)'
- ! 	select USB_TI_CPPI_DMA
- ! 	depends on USB_MUSB_DAVINCI
- ! 	help
- ! 	  Enable DMA transfers when TI CPPI DMA is available.
- ! 
- ! config USB_TI_CPPI41_DMA_HW
- ! 	tristate 'TI CPPI4.1'
- ! 	select USB_TI_CPPI41_DMA
- ! 	depends on USB_MUSB_DA8XX || USB_MUSB_AM35X || USB_MUSB_TI81XX
- ! 	select CPPI41
- ! 	help
- ! 	 Configure this option to include the CPPI 4.1 support,
- ! 	 The CPPI 4.1 DMA engine integrated with musb controller
- ! 	 accelarate the usb packet transmission and receception
- ! 	 to/from musb endpoints.
- ! 
- ! config USB_TUSB_OMAP_DMA_HW
- ! 	tristate 'TUSB 6010'
- ! 	select USB_TUSB_OMAP_DMA
- ! 	depends on USB_MUSB_TUSB6010
- ! 	depends on ARCH_OMAP
- ! 	help
- ! 	  Enable DMA transfers on TUSB 6010 when OMAP DMA is available.
-   
-   endchoice
-   
-   config MUSB_PIO_ONLY
-   	bool 'Disable DMA (always use PIO)'
- ! 	default USB_MUSB_TUSB6010 || USB_MUSB_DA8XX
-   	help
-   	  All data is copied between memory and FIFO by the CPU.
-   	  DMA controllers are ignored.
-   
- ! 	  Select 'y' here if DMA support for your SOC or board
- ! 	  is unavailable (or unstable). On CPPI 4.1 DMA based
- ! 	  systems (AM335x, AM35x, and AM180x) DMA support is
- ! 	  considered unstable and this option should be enabled
- ! 	  in production systems so that DMA is disabled, unless DMA
- ! 	  has been validated for all use cases. When DMA is enabled at
- ! 	  compile time, you can still disable it at run time using the
- ! 	  "use_dma=n" module parameter.
-   
-   config USB_INVENTRA_DMA
-   	bool
- ! 	default n
-   
-   config USB_TI_CPPI_DMA
-   	bool
- ! 	default n
- ! 
- ! config USB_TI_CPPI41_DMA
- ! 	bool
- ! 	default n
-   
-   config USB_TUSB_OMAP_DMA
-   	bool
- ! 	default n
- ! 
- ! config USB_UX500_DMA
- ! 	bool
- ! 	default n
-   
- + endif # USB_MUSB_HDRC
- diff -crN linux-3.2.1_o/drivers/usb/musb/Makefile linux-3.2.1/drivers/usb/musb/Makefile
- *** linux-3.2.1_o/drivers/usb/musb/Makefile	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/musb/Makefile	2014-05-15 13:25:15.082663686 +0900
- ***************
- *** 9,48 ****
-   musb_hdrc-y					+= musb_gadget_ep0.o musb_gadget.o
-   musb_hdrc-y					+= musb_virthub.o musb_host.o
-   musb_hdrc-$(CONFIG_DEBUG_FS)			+= musb_debugfs.o
- ! 
-   # Hardware Glue Layer
- ! obj-$(CONFIG_USB_MUSB_OMAP2PLUS)		+= omap2430.o
- ! obj-$(CONFIG_USB_MUSB_AM35X)			+= am35x.o
- ! obj-$(CONFIG_USB_MUSB_TUSB6010)			+= tusb6010.o
- ! obj-$(CONFIG_USB_MUSB_DAVINCI)			+= davinci.o
- ! obj-$(CONFIG_USB_MUSB_DA8XX)			+= da8xx.o
- ! obj-$(CONFIG_USB_MUSB_BLACKFIN)			+= blackfin.o
- ! obj-$(CONFIG_USB_MUSB_UX500)			+= ux500.o
-   
-   # the kconfig must guarantee that only one of the
-   # possible I/O schemes will be enabled at a time ...
-   # PIO only, or DMA (several potential schemes).
-   # though PIO is always there to back up DMA, and for ep0
-   
- ! ifneq ($(CONFIG_MUSB_PIO_ONLY),y)
- ! 
- !   ifeq ($(CONFIG_USB_INVENTRA_DMA),y)
- !     musb_hdrc-y			+= musbhsdma.o
- ! 
- !   else
- !     ifeq ($(CONFIG_USB_TI_CPPI_DMA),y)
- !       musb_hdrc-y		+= cppi_dma.o
- ! 
- !     else
- !       ifeq ($(CONFIG_USB_TUSB_OMAP_DMA),y)
- ! 	musb_hdrc-y		+= tusb6010_omap.o
- ! 
- !       else
- !         ifeq ($(CONFIG_USB_UX500_DMA),y)
- ! 	  musb_hdrc-y		+= ux500_dma.o
- ! 
- !         endif
- !       endif
- !     endif
- !   endif
- ! endif
- --- 9,33 ----
-   musb_hdrc-y					+= musb_gadget_ep0.o musb_gadget.o
-   musb_hdrc-y					+= musb_virthub.o musb_host.o
-   musb_hdrc-$(CONFIG_DEBUG_FS)			+= musb_debugfs.o
- ! musb_hdrc-$(CONFIG_PROC_FS)			+= musb_procfs.o
-   # Hardware Glue Layer
- ! obj-$(CONFIG_USB_MUSB_OMAP2PLUS_GLUE)		+= omap2430.o
- ! obj-$(CONFIG_USB_MUSB_AM35X_GLUE)		+= am35x.o
- ! obj-$(CONFIG_USB_MUSB_TI81XX_GLUE)		+= ti81xx.o
- ! obj-$(CONFIG_USB_MUSB_TUSB6010_GLUE)		+= tusb6010.o
- ! obj-$(CONFIG_USB_MUSB_DAVINCI_GLUE)			+= davinci.o
- ! obj-$(CONFIG_USB_MUSB_DA8XX_GLUE)			+= da8xx.o
- ! obj-$(CONFIG_USB_MUSB_BLACKFIN_GLUE)		+= blackfin.o
- ! obj-$(CONFIG_USB_MUSB_UX500_GLUE)			+= ux500.o
-   
-   # the kconfig must guarantee that only one of the
-   # possible I/O schemes will be enabled at a time ...
-   # PIO only, or DMA (several potential schemes).
-   # though PIO is always there to back up DMA, and for ep0
-   
- ! obj-$(CONFIG_USB_INVENTRA_DMA_HW)		+= musbhsdma.o
- ! obj-$(CONFIG_USB_TI_CPPI_DMA_HW)		+= cppi_dma.o
- ! obj-$(CONFIG_USB_TI_CPPI41_DMA_HW)		+= cppi41dma.o
- ! cppi41dma-y					+= cppi41.o cppi41_dma.o
- ! obj-$(CONFIG_USB_TUSB_OMAP_DMA_HW)		+= tusb6010_omap.o
- ! obj-$(CONFIG_USB_UX500_DMA_HW)			+= ux500_dma.o
- diff -crN linux-3.2.1_o/drivers/usb/musb/musb_core.c linux-3.2.1/drivers/usb/musb/musb_core.c
- *** linux-3.2.1_o/drivers/usb/musb/musb_core.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/musb/musb_core.c	2014-05-15 13:25:15.086916190 +0900
- ***************
- *** 102,108 ****
-   
-   #include "musb_core.h"
-   
- - #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
-   
-   
-   #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
- --- 102,107 ----
- ***************
- *** 120,125 ****
- --- 119,128 ----
-   MODULE_LICENSE("GPL");
-   MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
-   
- + u8 (*musb_readb)(const void __iomem *addr, unsigned offset);
- + EXPORT_SYMBOL_GPL(musb_readb);
- + void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data);
- + EXPORT_SYMBOL_GPL(musb_writeb);
-   
-   /*-------------------------------------------------------------------------*/
-   
- ***************
- *** 131,136 ****
- --- 134,177 ----
-   /*-------------------------------------------------------------------------*/
-   
-   #ifndef CONFIG_BLACKFIN
- + 
- + /*
- +  * TUSB6010 doesn't allow 8-bit access; 16-bit access is the minimum.
- +  */
- + static inline u8 __tusb_musb_readb(const void __iomem *addr, unsigned offset)
- + {
- + 	u16 tmp;
- + 	u8 val;
- + 
- + 	tmp = __raw_readw(addr + (offset & ~1));
- + 	if (offset & 1)
- + 		val = (tmp >> 8);
- + 	else
- + 		val = tmp & 0xff;
- + 
- + 	return val;
- + }
- + 
- + static inline void __tusb_musb_writeb(void __iomem *addr, unsigned offset,
- + 					u8 data)
- + {
- + 	u16 tmp;
- + 
- + 	tmp = __raw_readw(addr + (offset & ~1));
- + 	if (offset & 1)
- + 		tmp = (data << 8) | (tmp & 0xff);
- + 	else
- + 		tmp = (tmp & 0xff00) | data;
- + 
- + 	__raw_writew(tmp, addr + (offset & ~1));
- + }
- + 
- + static inline u8 __musb_readb(const void __iomem *addr, unsigned offset)
- + 	{ return readb(addr + offset); }
- + 
- + static inline void __musb_writeb(void __iomem *addr, unsigned offset, u8 data)
- + 	{ writeb(data, addr + offset); }
- + 
-   static int musb_ulpi_read(struct otg_transceiver *otg, u32 offset)
-   {
-   	void __iomem *addr = otg->io_priv;
- ***************
- *** 196,201 ****
- --- 237,248 ----
-   	return 0;
-   }
-   #else
- + static inline u8 __musb_readb(const void __iomem *addr, unsigned offset)
- + 	{ return (u8) (bfin_read16(addr + offset)); }
- + 
- + static inline void __musb_writeb(void __iomem *addr, unsigned offset, u8 data)
- + 	{ bfin_write16(addr + offset, (u16) data); }
- + 
-   #define musb_ulpi_read		NULL
-   #define musb_ulpi_write		NULL
-   #endif
- ***************
- *** 205,214 ****
-   	.write = musb_ulpi_write,
-   };
-   
- - /*-------------------------------------------------------------------------*/
- - 
- - #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN)
- - 
-   /*
-    * Load an endpoint's FIFO
-    */
- --- 252,257 ----
- ***************
- *** 249,256 ****
-   		writesb(fifo, src, len);
-   	}
-   }
-   
- - #if !defined(CONFIG_USB_MUSB_AM35X)
-   /*
-    * Unload an endpoint's FIFO
-    */
- --- 292,299 ----
-   		writesb(fifo, src, len);
-   	}
-   }
- + EXPORT_SYMBOL_GPL(musb_write_fifo);
-   
-   /*
-    * Unload an endpoint's FIFO
-    */
- ***************
- *** 289,298 ****
-   		readsb(fifo, dst, len);
-   	}
-   }
- ! #endif
- ! 
- ! #endif	/* normal PIO */
- ! 
-   
-   /*-------------------------------------------------------------------------*/
-   
- --- 332,338 ----
-   		readsb(fifo, dst, len);
-   	}
-   }
- ! EXPORT_SYMBOL_GPL(musb_read_fifo);
-   
-   /*-------------------------------------------------------------------------*/
-   
- ***************
- *** 318,334 ****
-   
-   void musb_load_testpacket(struct musb *musb)
-   {
- ! 	void __iomem	*regs = musb->endpoints[0].regs;
- ! 
- ! 	musb_ep_select(musb->mregs, 0);
- ! 	musb_write_fifo(musb->control_ep,
-   			sizeof(musb_test_packet), musb_test_packet);
- - 	musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
-   }
-   
-   /*-------------------------------------------------------------------------*/
-   
-   /*
-    * Handles OTG hnp timeouts, such as b_ase0_brst
-    */
-   void musb_otg_timer_func(unsigned long data)
- --- 358,377 ----
-   
-   void musb_load_testpacket(struct musb *musb)
-   {
- ! 	musb_ep_select(musb, musb->mregs, 0);
- ! 	musb->ops->write_fifo(musb->control_ep,
-   			sizeof(musb_test_packet), musb_test_packet);
-   }
-   
-   /*-------------------------------------------------------------------------*/
-   
-   /*
- +  * See also USB_OTG_1-3.pdf 6.6.5 Timers
- +  * REVISIT: Are the other timers done in the hardware?
- +  */
- + #define TB_ASE0_BRST		100	/* Min 3.125 ms */
- + 
- + /*
-    * Handles OTG hnp timeouts, such as b_ase0_brst
-    */
-   void musb_otg_timer_func(unsigned long data)
- ***************
- *** 344,355 ****
-   		musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
-   		musb->is_active = 0;
-   		break;
- - 	case OTG_STATE_A_SUSPEND:
-   	case OTG_STATE_A_WAIT_BCON:
- ! 		dev_dbg(musb->controller, "HNP: %s timeout\n",
- ! 			otg_state_string(musb->xceiv->state));
- ! 		musb_platform_set_vbus(musb, 0);
- ! 		musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
-   		break;
-   	default:
-   		dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
- --- 387,395 ----
-   		musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
-   		musb->is_active = 0;
-   		break;
-   	case OTG_STATE_A_WAIT_BCON:
- ! 		dev_dbg(musb->controller, "HNP: a_wait_bcon timeout; back to a_host\n");
- ! 		musb_hnp_stop(musb);
-   		break;
-   	default:
-   		dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
- ***************
- *** 360,366 ****
-   }
-   
-   /*
- !  * Stops the HNP transition. Caller must take care of locking.
-    */
-   void musb_hnp_stop(struct musb *musb)
-   {
- --- 400,406 ----
-   }
-   
-   /*
- !  * Stops the B-device HNP state. Caller must take care of locking.
-    */
-   void musb_hnp_stop(struct musb *musb)
-   {
- ***************
- *** 368,380 ****
-   	void __iomem	*mbase = musb->mregs;
-   	u8	reg;
-   
- - 	dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state));
- - 
-   	switch (musb->xceiv->state) {
-   	case OTG_STATE_A_PERIPHERAL:
-   		musb_g_disconnect(musb);
- ! 		dev_dbg(musb->controller, "HNP: back to %s\n",
- ! 			otg_state_string(musb->xceiv->state));
-   		break;
-   	case OTG_STATE_B_HOST:
-   		dev_dbg(musb->controller, "HNP: Disabling HR\n");
- --- 408,422 ----
-   	void __iomem	*mbase = musb->mregs;
-   	u8	reg;
-   
-   	switch (musb->xceiv->state) {
-   	case OTG_STATE_A_PERIPHERAL:
- + 	case OTG_STATE_A_WAIT_VFALL:
- + 	case OTG_STATE_A_WAIT_BCON:
- + 		dev_dbg(musb->controller, "HNP: Switching back to A-host\n");
-   		musb_g_disconnect(musb);
- ! 		musb->xceiv->state = OTG_STATE_A_IDLE;
- ! 		MUSB_HST_MODE(musb);
- ! 		musb->is_active = 0;
-   		break;
-   	case OTG_STATE_B_HOST:
-   		dev_dbg(musb->controller, "HNP: Disabling HR\n");
- ***************
- *** 427,433 ****
-   		handled = IRQ_HANDLED;
-   		dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state));
-   
- ! 		if (devctl & MUSB_DEVCTL_HM) {
-   			void __iomem *mbase = musb->mregs;
-   
-   			switch (musb->xceiv->state) {
- --- 469,475 ----
-   		handled = IRQ_HANDLED;
-   		dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state));
-   
- ! 		if (is_host_enabled(musb) && (devctl & MUSB_DEVCTL_HM)) {
-   			void __iomem *mbase = musb->mregs;
-   
-   			switch (musb->xceiv->state) {
- ***************
- *** 470,495 ****
-   		} else {
-   			switch (musb->xceiv->state) {
-   			case OTG_STATE_A_SUSPEND:
- ! 				/* possibly DISCONNECT is upcoming */
- ! 				musb->xceiv->state = OTG_STATE_A_HOST;
- ! 				usb_hcd_resume_root_hub(musb_to_hcd(musb));
-   				break;
-   			case OTG_STATE_B_WAIT_ACON:
-   			case OTG_STATE_B_PERIPHERAL:
- ! 				/* disconnect while suspended?  we may
- ! 				 * not get a disconnect irq...
- ! 				 */
- ! 				if ((devctl & MUSB_DEVCTL_VBUS)
-   						!= (3 << MUSB_DEVCTL_VBUS_SHIFT)
- ! 						) {
- ! 					musb->int_usb |= MUSB_INTR_DISCONNECT;
- ! 					musb->int_usb &= ~MUSB_INTR_SUSPEND;
- ! 					break;
-   				}
- - 				musb_g_resume(musb);
-   				break;
-   			case OTG_STATE_B_IDLE:
- ! 				musb->int_usb &= ~MUSB_INTR_SUSPEND;
-   				break;
-   			default:
-   				WARNING("bogus %s RESUME (%s)\n",
- --- 512,545 ----
-   		} else {
-   			switch (musb->xceiv->state) {
-   			case OTG_STATE_A_SUSPEND:
- ! 				if (is_host_enabled(musb)) {
- ! 					/* possibly DISCONNECT is upcoming */
- ! 					musb->xceiv->state = OTG_STATE_A_HOST;
- ! 					usb_hcd_resume_root_hub(
- ! 							musb_to_hcd(musb));
- ! 				}
-   				break;
-   			case OTG_STATE_B_WAIT_ACON:
-   			case OTG_STATE_B_PERIPHERAL:
- ! 				if (is_peripheral_enabled(musb)) {
- ! 					/* disconnect while suspended?  we may
- ! 					 * not get a disconnect irq...
- ! 					 */
- ! 					if ((devctl & MUSB_DEVCTL_VBUS)
-   						!= (3 << MUSB_DEVCTL_VBUS_SHIFT)
- ! 							) {
- ! 						musb->int_usb |=
- ! 							MUSB_INTR_DISCONNECT;
- ! 						musb->int_usb &=
- ! 							~MUSB_INTR_SUSPEND;
- ! 						break;
- ! 					}
- ! 					musb_g_resume(musb);
-   				}
-   				break;
-   			case OTG_STATE_B_IDLE:
- ! 				if (is_peripheral_enabled(musb))
- ! 					musb->int_usb &= ~MUSB_INTR_SUSPEND;
-   				break;
-   			default:
-   				WARNING("bogus %s RESUME (%s)\n",
- ***************
- *** 500,506 ****
-   	}
-   
-   	/* see manual for the order of the tests */
- ! 	if (int_usb & MUSB_INTR_SESSREQ) {
-   		void __iomem *mbase = musb->mregs;
-   
-   		if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
- --- 550,556 ----
-   	}
-   
-   	/* see manual for the order of the tests */
- ! 	if (is_host_enabled(musb) && (int_usb & MUSB_INTR_SESSREQ)) {
-   		void __iomem *mbase = musb->mregs;
-   
-   		if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
- ***************
- *** 528,534 ****
-   		handled = IRQ_HANDLED;
-   	}
-   
- ! 	if (int_usb & MUSB_INTR_VBUSERROR) {
-   		int	ignore = 0;
-   
-   		/* During connection as an A-Device, we may see a short
- --- 578,585 ----
-   		handled = IRQ_HANDLED;
-   	}
-   
- ! 	if (is_host_enabled(musb) && (int_usb & MUSB_INTR_VBUSERROR)) {
- ! 		struct usb_hcd *hcd = musb_to_hcd(musb);
-   		int	ignore = 0;
-   
-   		/* During connection as an A-Device, we may see a short
- ***************
- *** 568,573 ****
- --- 619,631 ----
-   				musb->port1_status |=
-   					  USB_PORT_STAT_OVERCURRENT
-   					| (USB_PORT_STAT_C_OVERCURRENT << 16);
- + 
- + 				if (hcd->status_urb)
- + 					usb_hcd_poll_rh_status(hcd);
- + 				else
- + 					usb_hcd_resume_root_hub(hcd);
- + 
- + 				MUSB_HST_MODE(musb);
-   			}
-   			break;
-   		default:
- ***************
- *** 604,625 ****
-   		handled = IRQ_HANDLED;
-   
-   		switch (musb->xceiv->state) {
- - 		case OTG_STATE_A_PERIPHERAL:
- - 			/* We also come here if the cable is removed, since
- - 			 * this silicon doesn't report ID-no-longer-grounded.
- - 			 *
- - 			 * We depend on T(a_wait_bcon) to shut us down, and
- - 			 * hope users don't do anything dicey during this
- - 			 * undesired detour through A_WAIT_BCON.
- - 			 */
- - 			musb_hnp_stop(musb);
- - 			usb_hcd_resume_root_hub(musb_to_hcd(musb));
- - 			musb_root_disconnect(musb);
- - 			musb_platform_try_idle(musb, jiffies
- - 					+ msecs_to_jiffies(musb->a_wait_bcon
- - 						? : OTG_TIME_A_WAIT_BCON));
- - 
- - 			break;
-   		case OTG_STATE_B_IDLE:
-   			if (!musb->is_active)
-   				break;
- --- 662,667 ----
- ***************
- *** 627,638 ****
-   			musb_g_suspend(musb);
-   			musb->is_active = is_otg_enabled(musb)
-   					&& musb->xceiv->gadget->b_hnp_enable;
- ! 			if (musb->is_active) {
-   				musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
-   				dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
-   				mod_timer(&musb->otg_timer, jiffies
- ! 					+ msecs_to_jiffies(
- ! 							OTG_TIME_B_ASE0_BRST));
-   			}
-   			break;
-   		case OTG_STATE_A_WAIT_BCON:
- --- 669,679 ----
-   			musb_g_suspend(musb);
-   			musb->is_active = is_otg_enabled(musb)
-   					&& musb->xceiv->gadget->b_hnp_enable;
- ! 			if (is_otg_enabled(musb) && musb->is_active) {
-   				musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
-   				dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
-   				mod_timer(&musb->otg_timer, jiffies
- ! 					+ msecs_to_jiffies(TB_ASE0_BRST));
-   			}
-   			break;
-   		case OTG_STATE_A_WAIT_BCON:
- ***************
- *** 649,654 ****
- --- 690,702 ----
-   			/* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
-   			dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
-   			break;
- + 		case OTG_STATE_A_PERIPHERAL:
- + 			/*
- + 			 * We cannot stop HNP here, devctl BDEVICE might be
- + 			 * still set.
- + 			 */
- + 			if (is_otg_enabled(musb))
- + 				break;
-   		default:
-   			/* "should not happen" */
-   			musb->is_active = 0;
- ***************
- *** 656,662 ****
-   		}
-   	}
-   
- ! 	if (int_usb & MUSB_INTR_CONNECT) {
-   		struct usb_hcd *hcd = musb_to_hcd(musb);
-   
-   		handled = IRQ_HANDLED;
- --- 704,710 ----
-   		}
-   	}
-   
- ! 	if (is_host_enabled(musb) && (int_usb & MUSB_INTR_CONNECT)) {
-   		struct usb_hcd *hcd = musb_to_hcd(musb);
-   
-   		handled = IRQ_HANDLED;
- ***************
- *** 665,677 ****
-   
-   		musb->ep0_stage = MUSB_EP0_START;
-   
- ! 		/* flush endpoints when transitioning from Device Mode */
- ! 		if (is_peripheral_active(musb)) {
- ! 			/* REVISIT HNP; just force disconnect */
- ! 		}
- ! 		musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask);
- ! 		musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe);
- ! 		musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
-   		musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
-   					|USB_PORT_STAT_HIGH_SPEED
-   					|USB_PORT_STAT_ENABLE
- --- 713,728 ----
-   
-   		musb->ep0_stage = MUSB_EP0_START;
-   
- ! 		if (is_otg_enabled(musb)) {
- ! 			/* flush endpoints when transitioning from DeviceMode */
- ! 			if (is_peripheral_active(musb)) {
- ! 				/* REVISIT HNP; just force disconnect */
- ! 			}
- ! 			musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask);
- ! 			musb_writew(musb->mregs, MUSB_INTRRXE,
- ! 						musb->epmask & 0xfffe);
- ! 			musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
- ! 		}
-   		musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
-   					|USB_PORT_STAT_HIGH_SPEED
-   					|USB_PORT_STAT_ENABLE
- ***************
- *** 683,705 ****
-   		if (devctl & MUSB_DEVCTL_LSDEV)
-   			musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
-   
-   		/* indicate new connection to OTG machine */
-   		switch (musb->xceiv->state) {
-   		case OTG_STATE_B_PERIPHERAL:
-   			if (int_usb & MUSB_INTR_SUSPEND) {
-   				dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
-   				int_usb &= ~MUSB_INTR_SUSPEND;
- - 				goto b_host;
-   			} else
-   				dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
-   			break;
-   		case OTG_STATE_B_WAIT_ACON:
- ! 			dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
- ! b_host:
-   			musb->xceiv->state = OTG_STATE_B_HOST;
-   			hcd->self.is_b_host = 1;
- - 			musb->ignore_disconnect = 0;
- - 			del_timer(&musb->otg_timer);
-   			break;
-   		default:
-   			if ((devctl & MUSB_DEVCTL_VBUS)
- --- 734,761 ----
-   		if (devctl & MUSB_DEVCTL_LSDEV)
-   			musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
-   
- + 		if (hcd->status_urb)
- + 			usb_hcd_poll_rh_status(hcd);
- + 		else
- + 			usb_hcd_resume_root_hub(hcd);
- + 
- + 		MUSB_HST_MODE(musb);
- + 
-   		/* indicate new connection to OTG machine */
-   		switch (musb->xceiv->state) {
-   		case OTG_STATE_B_PERIPHERAL:
-   			if (int_usb & MUSB_INTR_SUSPEND) {
-   				dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
- + 				musb->xceiv->state = OTG_STATE_B_HOST;
- + 				hcd->self.is_b_host = 1;
-   				int_usb &= ~MUSB_INTR_SUSPEND;
-   			} else
-   				dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
-   			break;
-   		case OTG_STATE_B_WAIT_ACON:
- ! 			dev_dbg(musb->controller, "HNP: Waiting to switch to b_host state\n");
-   			musb->xceiv->state = OTG_STATE_B_HOST;
-   			hcd->self.is_b_host = 1;
-   			break;
-   		default:
-   			if ((devctl & MUSB_DEVCTL_VBUS)
- ***************
- *** 710,722 ****
-   			break;
-   		}
-   
- - 		/* poke the root hub */
- - 		MUSB_HST_MODE(musb);
- - 		if (hcd->status_urb)
- - 			usb_hcd_poll_rh_status(hcd);
- - 		else
- - 			usb_hcd_resume_root_hub(hcd);
- - 
-   		dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
-   				otg_state_string(musb->xceiv->state), devctl);
-   	}
- --- 766,771 ----
- ***************
- *** 730,762 ****
-   		switch (musb->xceiv->state) {
-   		case OTG_STATE_A_HOST:
-   		case OTG_STATE_A_SUSPEND:
- ! 			usb_hcd_resume_root_hub(musb_to_hcd(musb));
- ! 			musb_root_disconnect(musb);
- ! 			if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
- ! 				musb_platform_try_idle(musb, jiffies
-   					+ msecs_to_jiffies(musb->a_wait_bcon));
-   			break;
-   		case OTG_STATE_B_HOST:
- ! 			/* REVISIT this behaves for "real disconnect"
- ! 			 * cases; make sure the other transitions from
- ! 			 * from B_HOST act right too.  The B_HOST code
- ! 			 * in hnp_stop() is currently not used...
- ! 			 */
- ! 			musb_root_disconnect(musb);
- ! 			musb_to_hcd(musb)->self.is_b_host = 0;
- ! 			musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
- ! 			MUSB_DEV_MODE(musb);
- ! 			musb_g_disconnect(musb);
-   			break;
-   		case OTG_STATE_A_PERIPHERAL:
- ! 			musb_hnp_stop(musb);
- ! 			musb_root_disconnect(musb);
-   			/* FALLTHROUGH */
-   		case OTG_STATE_B_WAIT_ACON:
-   			/* FALLTHROUGH */
-   		case OTG_STATE_B_PERIPHERAL:
-   		case OTG_STATE_B_IDLE:
- ! 			musb_g_disconnect(musb);
-   			break;
-   		default:
-   			WARNING("unhandled DISCONNECT transition (%s)\n",
- --- 779,816 ----
-   		switch (musb->xceiv->state) {
-   		case OTG_STATE_A_HOST:
-   		case OTG_STATE_A_SUSPEND:
- ! 			if (is_host_enabled(musb)) {
- ! 				usb_hcd_resume_root_hub(musb_to_hcd(musb));
- ! 				musb_root_disconnect(musb);
- ! 				if (musb->a_wait_bcon != 0 &&
- ! 						is_otg_enabled(musb))
- ! 					musb_platform_try_idle(musb, jiffies
-   					+ msecs_to_jiffies(musb->a_wait_bcon));
- + 			}
-   			break;
-   		case OTG_STATE_B_HOST:
- ! 			if (is_otg_enabled(musb))
- ! 				musb_hnp_stop(musb);
-   			break;
-   		case OTG_STATE_A_PERIPHERAL:
- ! 			if (is_otg_enabled(musb)) {
- ! 				musb_hnp_stop(musb);
- ! 				musb_root_disconnect(musb);
- ! 			}
-   			/* FALLTHROUGH */
-   		case OTG_STATE_B_WAIT_ACON:
- + 			if (!is_otg_enabled(musb))
- + 				break;
-   			/* FALLTHROUGH */
-   		case OTG_STATE_B_PERIPHERAL:
-   		case OTG_STATE_B_IDLE:
- ! 			if (is_peripheral_enabled(musb)) {
- ! 				printk(KERN_INFO "musb %s gadget disconnected.\n",
- ! 					musb->gadget_driver
- ! 					? musb->gadget_driver->driver.name
- ! 					: "");
- ! 				musb_g_disconnect(musb);
- ! 			}
-   			break;
-   		default:
-   			WARNING("unhandled DISCONNECT transition (%s)\n",
- ***************
- *** 770,776 ****
-   	 */
-   	if (int_usb & MUSB_INTR_RESET) {
-   		handled = IRQ_HANDLED;
- ! 		if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
-   			/*
-   			 * Looks like non-HS BABBLE can be ignored, but
-   			 * HS BABBLE is an error condition. For HS the solution
- --- 824,830 ----
-   	 */
-   	if (int_usb & MUSB_INTR_RESET) {
-   		handled = IRQ_HANDLED;
- ! 		if (is_host_enabled(musb) && (devctl & MUSB_DEVCTL_HM) != 0) {
-   			/*
-   			 * Looks like non-HS BABBLE can be ignored, but
-   			 * HS BABBLE is an error condition. For HS the solution
- ***************
- *** 784,819 ****
-   				ERR("Stopping host session -- babble\n");
-   				musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
-   			}
- ! 		} else if (is_peripheral_capable()) {
-   			dev_dbg(musb->controller, "BUS RESET as %s\n",
-   				otg_state_string(musb->xceiv->state));
-   			switch (musb->xceiv->state) {
-   			case OTG_STATE_A_SUSPEND:
- ! 				/* We need to ignore disconnect on suspend
- ! 				 * otherwise tusb 2.0 won't reconnect after a
- ! 				 * power cycle, which breaks otg compliance.
- ! 				 */
- ! 				musb->ignore_disconnect = 1;
- ! 				musb_g_reset(musb);
-   				/* FALLTHROUGH */
-   			case OTG_STATE_A_WAIT_BCON:	/* OPT TD.4.7-900ms */
- ! 				/* never use invalid T(a_wait_bcon) */
- ! 				dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
- ! 					otg_state_string(musb->xceiv->state),
- ! 					TA_WAIT_BCON(musb));
- ! 				mod_timer(&musb->otg_timer, jiffies
- ! 					+ msecs_to_jiffies(TA_WAIT_BCON(musb)));
-   				break;
-   			case OTG_STATE_A_PERIPHERAL:
- ! 				musb->ignore_disconnect = 0;
- ! 				del_timer(&musb->otg_timer);
- ! 				musb_g_reset(musb);
-   				break;
-   			case OTG_STATE_B_WAIT_ACON:
- ! 				dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
-   					otg_state_string(musb->xceiv->state));
- ! 				musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
- ! 				musb_g_reset(musb);
-   				break;
-   			case OTG_STATE_B_IDLE:
-   				musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
- --- 838,882 ----
-   				ERR("Stopping host session -- babble\n");
-   				musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
-   			}
- ! 		} else if (is_peripheral_enabled(musb)) {
-   			dev_dbg(musb->controller, "BUS RESET as %s\n",
-   				otg_state_string(musb->xceiv->state));
-   			switch (musb->xceiv->state) {
-   			case OTG_STATE_A_SUSPEND:
- ! 				if (is_otg_enabled(musb)) {
- ! 					/* We need to ignore disconnect on
- ! 					 * suspend otherwise tusb 2.0 won't
- ! 					 * reconnect after a power cycle,
- ! 					 * which breaks otg compliance.
- ! 					 */
- ! 					musb->ignore_disconnect = 1;
- ! 					musb_g_reset(musb);
- ! 				} else {
- ! 					break;
- ! 				}
-   				/* FALLTHROUGH */
-   			case OTG_STATE_A_WAIT_BCON:	/* OPT TD.4.7-900ms */
- ! 				if (is_otg_enabled(musb)) {
- ! 					dev_dbg(musb->controller,
- ! 					"HNP: Setting timer as %s\n",
- ! 					otg_state_string(musb->xceiv->state));
- ! 					mod_timer(&musb->otg_timer, jiffies
- ! 						+ msecs_to_jiffies(100));
- ! 				}
-   				break;
-   			case OTG_STATE_A_PERIPHERAL:
- ! 				if (is_otg_enabled(musb))
- ! 					musb_hnp_stop(musb);
-   				break;
-   			case OTG_STATE_B_WAIT_ACON:
- ! 				if (is_otg_enabled(musb)) {
- ! 					dev_dbg(musb->controller,
- ! 					"HNP: RESET (%s), to b_peripheral\n",
-   					otg_state_string(musb->xceiv->state));
- ! 					musb->xceiv->state =
- ! 						OTG_STATE_B_PERIPHERAL;
- ! 					musb_g_reset(musb);
- ! 				}
-   				break;
-   			case OTG_STATE_B_IDLE:
-   				musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
- ***************
- *** 906,912 ****
-   
-   	musb->is_active = 0;
-   	devctl = musb_readb(regs, MUSB_DEVCTL);
- - 	devctl &= ~MUSB_DEVCTL_SESSION;
-   
-   	if (is_otg_enabled(musb)) {
-   		/* session started after:
- --- 969,974 ----
- ***************
- *** 930,936 ****
-   	musb_platform_enable(musb);
-   	musb_writeb(regs, MUSB_DEVCTL, devctl);
-   }
- ! 
-   
-   static void musb_generic_disable(struct musb *musb)
-   {
- --- 992,998 ----
-   	musb_platform_enable(musb);
-   	musb_writeb(regs, MUSB_DEVCTL, devctl);
-   }
- ! EXPORT_SYMBOL(musb_start);
-   
-   static void musb_generic_disable(struct musb *musb)
-   {
- ***************
- *** 1000,1039 ****
-   /*-------------------------------------------------------------------------*/
-   
-   /*
- -  * The silicon either has hard-wired endpoint configurations, or else
- -  * "dynamic fifo" sizing.  The driver has support for both, though at this
- -  * writing only the dynamic sizing is very well tested.   Since we switched
- -  * away from compile-time hardware parameters, we can no longer rely on
- -  * dead code elimination to leave only the relevant one in the object file.
- -  *
- -  * We don't currently use dynamic fifo setup capability to do anything
- -  * more than selecting one of a bunch of predefined configurations.
- -  */
- - #if defined(CONFIG_USB_MUSB_TUSB6010)			\
- - 	|| defined(CONFIG_USB_MUSB_TUSB6010_MODULE)	\
- - 	|| defined(CONFIG_USB_MUSB_OMAP2PLUS)		\
- - 	|| defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE)	\
- - 	|| defined(CONFIG_USB_MUSB_AM35X)		\
- - 	|| defined(CONFIG_USB_MUSB_AM35X_MODULE)
- - static ushort __initdata fifo_mode = 4;
- - #elif defined(CONFIG_USB_MUSB_UX500)			\
- - 	|| defined(CONFIG_USB_MUSB_UX500_MODULE)
- - static ushort __initdata fifo_mode = 5;
- - #else
- - static ushort __initdata fifo_mode = 2;
- - #endif
- - 
- - /* "modprobe ... fifo_mode=1" etc */
- - module_param(fifo_mode, ushort, 0);
- - MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
- - 
- - /*
-    * tables defining fifo_mode values.  define more if you like.
-    * for host side, make sure both halves of ep1 are set up.
-    */
-   
-   /* mode 0 - fits in 2KB */
- ! static struct musb_fifo_cfg __initdata mode_0_cfg[] = {
-   { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, },
-   { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, },
-   { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
- --- 1062,1073 ----
-   /*-------------------------------------------------------------------------*/
-   
-   /*
-    * tables defining fifo_mode values.  define more if you like.
-    * for host side, make sure both halves of ep1 are set up.
-    */
-   
-   /* mode 0 - fits in 2KB */
- ! static struct musb_fifo_cfg mode_0_cfg[] = {
-   { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, },
-   { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, },
-   { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
- ***************
- *** 1042,1048 ****
-   };
-   
-   /* mode 1 - fits in 4KB */
- ! static struct musb_fifo_cfg __initdata mode_1_cfg[] = {
-   { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
-   { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
-   { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
- --- 1076,1082 ----
-   };
-   
-   /* mode 1 - fits in 4KB */
- ! static struct musb_fifo_cfg mode_1_cfg[] = {
-   { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
-   { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
-   { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
- ***************
- *** 1051,1057 ****
-   };
-   
-   /* mode 2 - fits in 4KB */
- ! static struct musb_fifo_cfg __initdata mode_2_cfg[] = {
-   { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, },
-   { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, },
-   { .hw_ep_num = 2, .style = FIFO_TX,   .maxpacket = 512, },
- --- 1085,1091 ----
-   };
-   
-   /* mode 2 - fits in 4KB */
- ! static struct musb_fifo_cfg mode_2_cfg[] = {
-   { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, },
-   { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, },
-   { .hw_ep_num = 2, .style = FIFO_TX,   .maxpacket = 512, },
- ***************
- *** 1061,1067 ****
-   };
-   
-   /* mode 3 - fits in 4KB */
- ! static struct musb_fifo_cfg __initdata mode_3_cfg[] = {
-   { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
-   { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
-   { .hw_ep_num = 2, .style = FIFO_TX,   .maxpacket = 512, },
- --- 1095,1101 ----
-   };
-   
-   /* mode 3 - fits in 4KB */
- ! static struct musb_fifo_cfg mode_3_cfg[] = {
-   { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
-   { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
-   { .hw_ep_num = 2, .style = FIFO_TX,   .maxpacket = 512, },
- ***************
- *** 1071,1083 ****
-   };
-   
-   /* mode 4 - fits in 16KB */
- ! static struct musb_fifo_cfg __initdata mode_4_cfg[] = {
- ! { .hw_ep_num =  1, .style = FIFO_TX,   .maxpacket = 512, },
- ! { .hw_ep_num =  1, .style = FIFO_RX,   .maxpacket = 512, },
- ! { .hw_ep_num =  2, .style = FIFO_TX,   .maxpacket = 512, },
- ! { .hw_ep_num =  2, .style = FIFO_RX,   .maxpacket = 512, },
- ! { .hw_ep_num =  3, .style = FIFO_TX,   .maxpacket = 512, },
- ! { .hw_ep_num =  3, .style = FIFO_RX,   .maxpacket = 512, },
-   { .hw_ep_num =  4, .style = FIFO_TX,   .maxpacket = 512, },
-   { .hw_ep_num =  4, .style = FIFO_RX,   .maxpacket = 512, },
-   { .hw_ep_num =  5, .style = FIFO_TX,   .maxpacket = 512, },
- --- 1105,1117 ----
-   };
-   
-   /* mode 4 - fits in 16KB */
- ! static struct musb_fifo_cfg mode_4_cfg[] = {
- ! { .hw_ep_num =  1, .style = FIFO_TX,   .maxpacket = 512,},
- ! { .hw_ep_num =  1, .style = FIFO_RX,   .maxpacket = 512,},
- ! { .hw_ep_num =  2, .style = FIFO_TX,   .maxpacket = 512,},
- ! { .hw_ep_num =  2, .style = FIFO_RX,   .maxpacket = 512,},
- ! { .hw_ep_num =  3, .style = FIFO_TX,   .maxpacket = 512,},
- ! { .hw_ep_num =  3, .style = FIFO_RX,   .maxpacket = 512,},
-   { .hw_ep_num =  4, .style = FIFO_TX,   .maxpacket = 512, },
-   { .hw_ep_num =  4, .style = FIFO_RX,   .maxpacket = 512, },
-   { .hw_ep_num =  5, .style = FIFO_TX,   .maxpacket = 512, },
- ***************
- *** 1101,1108 ****
-   { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
-   };
-   
-   /* mode 5 - fits in 8KB */
- ! static struct musb_fifo_cfg __initdata mode_5_cfg[] = {
-   { .hw_ep_num =  1, .style = FIFO_TX,   .maxpacket = 512, },
-   { .hw_ep_num =  1, .style = FIFO_RX,   .maxpacket = 512, },
-   { .hw_ep_num =  2, .style = FIFO_TX,   .maxpacket = 512, },
- --- 1135,1143 ----
-   { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
-   };
-   
- + 
-   /* mode 5 - fits in 8KB */
- ! static struct musb_fifo_cfg mode_5_cfg[] = {
-   { .hw_ep_num =  1, .style = FIFO_TX,   .maxpacket = 512, },
-   { .hw_ep_num =  1, .style = FIFO_RX,   .maxpacket = 512, },
-   { .hw_ep_num =  2, .style = FIFO_TX,   .maxpacket = 512, },
- ***************
- *** 1132,1144 ****
-   { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
-   };
-   
-   /*
-    * configure a fifo; for non-shared endpoints, this may be called
-    * once for a tx fifo and once for an rx fifo.
-    *
-    * returns negative errno or offset for next fifo.
-    */
- ! static int __init
-   fifo_setup(struct musb *musb, struct musb_hw_ep  *hw_ep,
-   		const struct musb_fifo_cfg *cfg, u16 offset)
-   {
- --- 1167,1210 ----
-   { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
-   };
-   
- + /* mode 6 - fits in 32KB */
- + static struct musb_fifo_cfg mode_6_cfg[] = {
- + { .hw_ep_num =  1, .style = FIFO_TX,   .maxpacket = 512, .mode = BUF_DOUBLE,},
- + { .hw_ep_num =  1, .style = FIFO_RX,   .maxpacket = 512, .mode = BUF_DOUBLE,},
- + { .hw_ep_num =  2, .style = FIFO_TX,   .maxpacket = 512, .mode = BUF_DOUBLE,},
- + { .hw_ep_num =  2, .style = FIFO_RX,   .maxpacket = 512, .mode = BUF_DOUBLE,},
- + { .hw_ep_num =  3, .style = FIFO_TX,   .maxpacket = 512, .mode = BUF_DOUBLE,},
- + { .hw_ep_num =  3, .style = FIFO_RX,   .maxpacket = 512, .mode = BUF_DOUBLE,},
- + { .hw_ep_num =  4, .style = FIFO_TX,   .maxpacket = 64, },
- + { .hw_ep_num =  4, .style = FIFO_RX,   .maxpacket = 64, },
- + { .hw_ep_num =  5, .style = FIFO_TX,   .maxpacket = 64, },
- + { .hw_ep_num =  5, .style = FIFO_RX,   .maxpacket = 64, },
- + { .hw_ep_num =  6, .style = FIFO_TX,   .maxpacket = 64, },
- + { .hw_ep_num =  6, .style = FIFO_RX,   .maxpacket = 64, },
- + { .hw_ep_num =  7, .style = FIFO_TX,   .maxpacket = 64, },
- + { .hw_ep_num =  7, .style = FIFO_RX,   .maxpacket = 64, },
- + { .hw_ep_num =  8, .style = FIFO_TX,   .maxpacket = 64, },
- + { .hw_ep_num =  8, .style = FIFO_RX,   .maxpacket = 64, },
- + { .hw_ep_num =  9, .style = FIFO_TX,   .maxpacket = 64, },
- + { .hw_ep_num =  9, .style = FIFO_RX,   .maxpacket = 64, },
- + { .hw_ep_num = 10, .style = FIFO_TX,   .maxpacket = 256, },
- + { .hw_ep_num = 10, .style = FIFO_RX,   .maxpacket = 64, },
- + { .hw_ep_num = 11, .style = FIFO_TX,   .maxpacket = 256, },
- + { .hw_ep_num = 11, .style = FIFO_RX,   .maxpacket = 64, },
- + { .hw_ep_num = 12, .style = FIFO_TX,   .maxpacket = 256, },
- + { .hw_ep_num = 12, .style = FIFO_RX,   .maxpacket = 64, },
- + { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
- + { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
- + { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
- + };
- + 
-   /*
-    * configure a fifo; for non-shared endpoints, this may be called
-    * once for a tx fifo and once for an rx fifo.
-    *
-    * returns negative errno or offset for next fifo.
-    */
- ! static int __devinit
-   fifo_setup(struct musb *musb, struct musb_hw_ep  *hw_ep,
-   		const struct musb_fifo_cfg *cfg, u16 offset)
-   {
- ***************
- *** 1170,1176 ****
-   	/* EP0 reserved endpoint for control, bidirectional;
-   	 * EP1 reserved for bulk, two unidirection halves.
-   	 */
- ! 	if (hw_ep->epnum == 1)
-   		musb->bulk_ep = hw_ep;
-   	/* REVISIT error check:  be sure ep0 can both rx and tx ... */
-   	switch (cfg->style) {
- --- 1236,1242 ----
-   	/* EP0 reserved endpoint for control, bidirectional;
-   	 * EP1 reserved for bulk, two unidirection halves.
-   	 */
- ! 	if (is_host_enabled(musb) && hw_ep->epnum == 1)
-   		musb->bulk_ep = hw_ep;
-   	/* REVISIT error check:  be sure ep0 can both rx and tx ... */
-   	switch (cfg->style) {
- ***************
- *** 1209,1234 ****
-   	return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
-   }
-   
- ! static struct musb_fifo_cfg __initdata ep0_cfg = {
-   	.style = FIFO_RXTX, .maxpacket = 64,
-   };
-   
- ! static int __init ep_config_from_table(struct musb *musb)
-   {
-   	const struct musb_fifo_cfg	*cfg;
-   	unsigned		i, n;
-   	int			offset;
-   	struct musb_hw_ep	*hw_ep = musb->endpoints;
-   
- ! 	if (musb->config->fifo_cfg) {
-   		cfg = musb->config->fifo_cfg;
-   		n = musb->config->fifo_cfg_size;
-   		goto done;
-   	}
-   
- ! 	switch (fifo_mode) {
-   	default:
- ! 		fifo_mode = 0;
-   		/* FALLTHROUGH */
-   	case 0:
-   		cfg = mode_0_cfg;
- --- 1275,1302 ----
-   	return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
-   }
-   
- ! static struct musb_fifo_cfg ep0_cfg = {
-   	.style = FIFO_RXTX, .maxpacket = 64,
-   };
-   
- ! int ep_config_from_table(struct musb *musb)
-   {
-   	const struct musb_fifo_cfg	*cfg;
-   	unsigned		i, n;
-   	int			offset;
-   	struct musb_hw_ep	*hw_ep = musb->endpoints;
-   
- ! 	if (musb->config->fifo_mode)
- ! 		musb->fifo_mode = musb->config->fifo_mode;
- ! 	else if (musb->config->fifo_cfg) {
-   		cfg = musb->config->fifo_cfg;
-   		n = musb->config->fifo_cfg_size;
-   		goto done;
-   	}
-   
- ! 	switch (musb->fifo_mode) {
-   	default:
- ! 		musb->fifo_mode = 0;
-   		/* FALLTHROUGH */
-   	case 0:
-   		cfg = mode_0_cfg;
- ***************
- *** 1254,1263 ****
-   		cfg = mode_5_cfg;
-   		n = ARRAY_SIZE(mode_5_cfg);
-   		break;
-   	}
-   
-   	printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
- ! 			musb_driver_name, fifo_mode);
-   
-   
-   done:
- --- 1322,1335 ----
-   		cfg = mode_5_cfg;
-   		n = ARRAY_SIZE(mode_5_cfg);
-   		break;
- + 	case 6:
- + 		cfg = mode_6_cfg;
- + 		n = ARRAY_SIZE(mode_6_cfg);
- + 		break;
-   	}
-   
-   	printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
- ! 			musb_driver_name, musb->fifo_mode);
-   
-   
-   done:
- ***************
- *** 1291,1310 ****
-   			n + 1, musb->config->num_eps * 2 - 1,
-   			offset, (1 << (musb->config->ram_bits + 2)));
-   
- ! 	if (!musb->bulk_ep) {
-   		pr_debug("%s: missing bulk\n", musb_driver_name);
-   		return -EINVAL;
-   	}
-   
-   	return 0;
-   }
- ! 
-   
-   /*
-    * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
-    * @param musb the controller
-    */
- ! static int __init ep_config_from_hw(struct musb *musb)
-   {
-   	u8 epnum = 0;
-   	struct musb_hw_ep *hw_ep;
- --- 1363,1382 ----
-   			n + 1, musb->config->num_eps * 2 - 1,
-   			offset, (1 << (musb->config->ram_bits + 2)));
-   
- ! 	if (is_host_enabled(musb) && !musb->bulk_ep) {
-   		pr_debug("%s: missing bulk\n", musb_driver_name);
-   		return -EINVAL;
-   	}
-   
-   	return 0;
-   }
- ! EXPORT_SYMBOL(ep_config_from_table);
-   
-   /*
-    * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
-    * @param musb the controller
-    */
- ! static int __devinit ep_config_from_hw(struct musb *musb)
-   {
-   	u8 epnum = 0;
-   	struct musb_hw_ep *hw_ep;
- ***************
- *** 1316,1322 ****
-   	/* FIXME pick up ep0 maxpacket size */
-   
-   	for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
- ! 		musb_ep_select(mbase, epnum);
-   		hw_ep = musb->endpoints + epnum;
-   
-   		ret = musb_read_fifosize(musb, hw_ep, epnum);
- --- 1388,1394 ----
-   	/* FIXME pick up ep0 maxpacket size */
-   
-   	for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
- ! 		musb_ep_select(musb, mbase, epnum);
-   		hw_ep = musb->endpoints + epnum;
-   
-   		ret = musb_read_fifosize(musb, hw_ep, epnum);
- ***************
- *** 1325,1344 ****
-   
-   		/* FIXME set up hw_ep->{rx,tx}_double_buffered */
-   
- ! 		/* pick an RX/TX endpoint for bulk */
- ! 		if (hw_ep->max_packet_sz_tx < 512
-   				|| hw_ep->max_packet_sz_rx < 512)
- ! 			continue;
-   
- ! 		/* REVISIT:  this algorithm is lazy, we should at least
- ! 		 * try to pick a double buffered endpoint.
- ! 		 */
- ! 		if (musb->bulk_ep)
- ! 			continue;
- ! 		musb->bulk_ep = hw_ep;
-   	}
-   
- ! 	if (!musb->bulk_ep) {
-   		pr_debug("%s: missing bulk\n", musb_driver_name);
-   		return -EINVAL;
-   	}
- --- 1397,1418 ----
-   
-   		/* FIXME set up hw_ep->{rx,tx}_double_buffered */
-   
- ! 		if (is_host_enabled(musb)) {
- ! 			/* pick an RX/TX endpoint for bulk */
- ! 			if (hw_ep->max_packet_sz_tx < 512
-   				|| hw_ep->max_packet_sz_rx < 512)
- ! 				continue;
-   
- ! 			/* REVISIT:  this algorithm is lazy, we should at least
- ! 			 * try to pick a double buffered endpoint.
- ! 			 */
- ! 			if (musb->bulk_ep)
- ! 				continue;
- ! 			musb->bulk_ep = hw_ep;
- ! 		}
-   	}
-   
- ! 	if (is_host_enabled(musb) && !musb->bulk_ep) {
-   		pr_debug("%s: missing bulk\n", musb_driver_name);
-   		return -EINVAL;
-   	}
- ***************
- *** 1351,1358 ****
-   /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
-    * configure endpoints, or take their config from silicon
-    */
- ! static int __init musb_core_init(u16 musb_type, struct musb *musb)
-   {
-   	u8 reg;
-   	char *type;
-   	char aInfo[90], aRevision[32], aDate[12];
- --- 1425,1434 ----
-   /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
-    * configure endpoints, or take their config from silicon
-    */
- ! static int __devinit musb_core_init(u16 musb_type, struct musb *musb)
-   {
- + 	struct device *dev = musb->controller;
- + 	struct musb_hdrc_platform_data *plat = dev->platform_data;
-   	u8 reg;
-   	char *type;
-   	char aInfo[90], aRevision[32], aDate[12];
- ***************
- *** 1398,1406 ****
-   		musb->is_multipoint = 0;
-   		type = "";
-   #ifndef	CONFIG_USB_OTG_BLACKLIST_HUB
- ! 		printk(KERN_ERR
- ! 			"%s: kernel must blacklist external hubs\n",
- ! 			musb_driver_name);
-   #endif
-   	}
-   
- --- 1474,1483 ----
-   		musb->is_multipoint = 0;
-   		type = "";
-   #ifndef	CONFIG_USB_OTG_BLACKLIST_HUB
- ! 		if (is_host_enabled(musb))
- ! 			printk(KERN_ERR
- ! 				"%s: kernel must blacklist external hubs\n",
- ! 				musb_driver_name);
-   #endif
-   	}
-   
- ***************
- *** 1431,1453 ****
-   	for (i = 0; i < musb->nr_endpoints; i++) {
-   		struct musb_hw_ep	*hw_ep = musb->endpoints + i;
-   
- ! 		hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
- ! #ifdef CONFIG_USB_MUSB_TUSB6010
- ! 		hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
- ! 		hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
- ! 		hw_ep->fifo_sync_va =
- ! 			musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
-   
- ! 		if (i == 0)
- ! 			hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
- ! 		else
- ! 			hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
- ! #endif
-   
- ! 		hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
- ! 		hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
- ! 		hw_ep->rx_reinit = 1;
- ! 		hw_ep->tx_reinit = 1;
-   
-   		if (hw_ep->max_packet_sz_tx) {
-   			dev_dbg(musb->controller,
- --- 1508,1538 ----
-   	for (i = 0; i < musb->nr_endpoints; i++) {
-   		struct musb_hw_ep	*hw_ep = musb->endpoints + i;
-   
- ! 		if (musb->ops->flags & MUSB_GLUE_TUSB_STYLE) {
- ! 			hw_ep->fifo = MUSB_TUSB_FIFO_OFFSET(i) + mbase;
- ! 			hw_ep->fifo_async = musb->async +
- ! 					0x400 + MUSB_TUSB_FIFO_OFFSET(i);
- ! 			hw_ep->fifo_sync = musb->sync +
- ! 					0x400 + MUSB_TUSB_FIFO_OFFSET(i);
- ! 			hw_ep->fifo_sync_va = musb->sync_va + 0x400 +
- ! 					MUSB_TUSB_FIFO_OFFSET(i);
-   
- ! 			if (i == 0)
- ! 				hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
- ! 			else
- ! 				hw_ep->conf = mbase + 0x400 +
- ! 						(((i - 1) & 0xf) << 2);
- ! 		} else {
- ! 			hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
- ! 		}
-   
- ! 		hw_ep->regs = MUSB_EP_OFFSET(musb, i, 0) + mbase;
- ! 		if (is_host_enabled(musb)) {
- ! 			hw_ep->target_regs =
- ! 					musb_read_target_reg_base(i, mbase);
- ! 			hw_ep->rx_reinit = 1;
- ! 			hw_ep->tx_reinit = 1;
- ! 		}
-   
-   		if (hw_ep->max_packet_sz_tx) {
-   			dev_dbg(musb->controller,
- ***************
- *** 1471,1479 ****
- --- 1556,1581 ----
-   			dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
-   	}
-   
- + 	if (!plat->config->mult_bulk_tx) {
- + 		musb->bulk_split = 0;
- + 		printk(KERN_DEBUG "%s.%d: bulk split disabled\n",
- + 			musb_driver_name, musb->id);
- + 	}
- + 	if (!plat->config->mult_bulk_rx) {
- + 		musb->bulk_combine = 0;
- + 		printk(KERN_DEBUG "%s.%d: bulk combine disabled\n",
- + 			musb_driver_name, musb->id);
- + 	}
- + 
-   	return 0;
-   }
-   
- + void musb_reinit(u16 musb_type, struct musb *musb)
- + {
- + 	musb_core_init(musb_type ? MUSB_CONTROLLER_MHDRC
- + 			: MUSB_CONTROLLER_HDRC, musb);
- + }
- + EXPORT_SYMBOL(musb_reinit);
-   /*-------------------------------------------------------------------------*/
-   
-   #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \
- ***************
- *** 1546,1559 ****
-   	ep_num = 1;
-   	while (reg) {
-   		if (reg & 1) {
- ! 			/* musb_ep_select(musb->mregs, ep_num); */
-   			/* REVISIT just retval = ep->rx_irq(...) */
-   			retval = IRQ_HANDLED;
-   			if (devctl & MUSB_DEVCTL_HM) {
- ! 				if (is_host_capable())
-   					musb_host_rx(musb, ep_num);
-   			} else {
- ! 				if (is_peripheral_capable())
-   					musb_g_rx(musb, ep_num);
-   			}
-   		}
- --- 1648,1661 ----
-   	ep_num = 1;
-   	while (reg) {
-   		if (reg & 1) {
- ! 			/* musb_ep_select(musb, musb->mregs, ep_num); */
-   			/* REVISIT just retval = ep->rx_irq(...) */
-   			retval = IRQ_HANDLED;
-   			if (devctl & MUSB_DEVCTL_HM) {
- ! 				if (is_host_enabled(musb))
-   					musb_host_rx(musb, ep_num);
-   			} else {
- ! 				if (is_peripheral_enabled(musb))
-   					musb_g_rx(musb, ep_num);
-   			}
-   		}
- ***************
- *** 1567,1580 ****
-   	ep_num = 1;
-   	while (reg) {
-   		if (reg & 1) {
- ! 			/* musb_ep_select(musb->mregs, ep_num); */
-   			/* REVISIT just retval |= ep->tx_irq(...) */
-   			retval = IRQ_HANDLED;
-   			if (devctl & MUSB_DEVCTL_HM) {
- ! 				if (is_host_capable())
-   					musb_host_tx(musb, ep_num);
-   			} else {
- ! 				if (is_peripheral_capable())
-   					musb_g_tx(musb, ep_num);
-   			}
-   		}
- --- 1669,1682 ----
-   	ep_num = 1;
-   	while (reg) {
-   		if (reg & 1) {
- ! 			/* musb_ep_select(musb, musb->mregs, ep_num); */
-   			/* REVISIT just retval |= ep->tx_irq(...) */
-   			retval = IRQ_HANDLED;
-   			if (devctl & MUSB_DEVCTL_HM) {
- ! 				if (is_host_enabled(musb))
-   					musb_host_tx(musb, ep_num);
-   			} else {
- ! 				if (is_peripheral_enabled(musb))
-   					musb_g_tx(musb, ep_num);
-   			}
-   		}
- ***************
- *** 1587,1598 ****
-   EXPORT_SYMBOL_GPL(musb_interrupt);
-   
-   #ifndef CONFIG_MUSB_PIO_ONLY
- - static int __initdata use_dma = 1;
- - 
- - /* "modprobe ... use_dma=0" etc */
- - module_param(use_dma, bool, 0);
- - MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
- - 
-   void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
-   {
-   	u8	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
- --- 1689,1694 ----
- ***************
- *** 1600,1639 ****
-   	/* called with controller lock already held */
-   
-   	if (!epnum) {
- ! #ifndef CONFIG_USB_TUSB_OMAP_DMA
- ! 		if (!is_cppi_enabled()) {
-   			/* endpoint 0 */
-   			if (devctl & MUSB_DEVCTL_HM)
-   				musb_h_ep0_irq(musb);
-   			else
-   				musb_g_ep0_irq(musb);
-   		}
- - #endif
-   	} else {
-   		/* endpoints 1..15 */
-   		if (transmit) {
-   			if (devctl & MUSB_DEVCTL_HM) {
- ! 				if (is_host_capable())
-   					musb_host_tx(musb, epnum);
-   			} else {
- ! 				if (is_peripheral_capable())
-   					musb_g_tx(musb, epnum);
-   			}
-   		} else {
-   			/* receive */
-   			if (devctl & MUSB_DEVCTL_HM) {
- ! 				if (is_host_capable())
-   					musb_host_rx(musb, epnum);
-   			} else {
- ! 				if (is_peripheral_capable())
-   					musb_g_rx(musb, epnum);
-   			}
-   		}
-   	}
-   }
- ! 
- ! #else
- ! #define use_dma			0
-   #endif
-   
-   /*-------------------------------------------------------------------------*/
- --- 1696,1732 ----
-   	/* called with controller lock already held */
-   
-   	if (!epnum) {
- ! 		if (!tusb_dma_omap(musb) && !is_cppi_enabled(musb)
- ! 				&& !is_cppi41_enabled(musb)) {
-   			/* endpoint 0 */
-   			if (devctl & MUSB_DEVCTL_HM)
-   				musb_h_ep0_irq(musb);
-   			else
-   				musb_g_ep0_irq(musb);
-   		}
-   	} else {
-   		/* endpoints 1..15 */
-   		if (transmit) {
-   			if (devctl & MUSB_DEVCTL_HM) {
- ! 				if (is_host_enabled(musb))
-   					musb_host_tx(musb, epnum);
-   			} else {
- ! 				if (is_peripheral_enabled(musb))
-   					musb_g_tx(musb, epnum);
-   			}
-   		} else {
-   			/* receive */
-   			if (devctl & MUSB_DEVCTL_HM) {
- ! 				if (is_host_enabled(musb))
-   					musb_host_rx(musb, epnum);
-   			} else {
- ! 				if (is_peripheral_enabled(musb))
-   					musb_g_rx(musb, epnum);
-   			}
-   		}
-   	}
-   }
- ! EXPORT_SYMBOL_GPL(musb_dma_completion);
-   #endif
-   
-   /*-------------------------------------------------------------------------*/
- ***************
- *** 1691,1698 ****
-   	}
-   
-   	spin_lock_irqsave(&musb->lock, flags);
- ! 	/* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
- ! 	musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
-   	if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
-   		musb->is_active = 0;
-   	musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
- --- 1784,1790 ----
-   	}
-   
-   	spin_lock_irqsave(&musb->lock, flags);
- ! 	musb->a_wait_bcon = val;
-   	if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
-   		musb->is_active = 0;
-   	musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
- ***************
- *** 1711,1723 ****
-   
-   	spin_lock_irqsave(&musb->lock, flags);
-   	val = musb->a_wait_bcon;
- - 	/* FIXME get_vbus_status() is normally #defined as false...
- - 	 * and is effectively TUSB-specific.
- - 	 */
-   	vbus = musb_platform_get_vbus_status(musb);
-   	spin_unlock_irqrestore(&musb->lock, flags);
-   
- ! 	return sprintf(buf, "Vbus %s, timeout %lu msec\n",
-   			vbus ? "on" : "off", val);
-   }
-   static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
- --- 1803,1812 ----
-   
-   	spin_lock_irqsave(&musb->lock, flags);
-   	val = musb->a_wait_bcon;
-   	vbus = musb_platform_get_vbus_status(musb);
-   	spin_unlock_irqrestore(&musb->lock, flags);
-   
- ! 	return sprintf(buf, "Vbus %s, timeout %lu\n",
-   			vbus ? "on" : "off", val);
-   }
-   static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
- ***************
- *** 1762,1771 ****
-   static void musb_irq_work(struct work_struct *data)
-   {
-   	struct musb *musb = container_of(data, struct musb, irq_work);
- - 	static int old_state;
-   
- ! 	if (musb->xceiv->state != old_state) {
- ! 		old_state = musb->xceiv->state;
-   		sysfs_notify(&musb->controller->kobj, NULL, "mode");
-   	}
-   }
- --- 1851,1859 ----
-   static void musb_irq_work(struct work_struct *data)
-   {
-   	struct musb *musb = container_of(data, struct musb, irq_work);
-   
- ! 	if (musb->xceiv->state != musb->old_state) {
- ! 		musb->old_state = musb->xceiv->state;
-   		sysfs_notify(&musb->controller->kobj, NULL, "mode");
-   	}
-   }
- ***************
- *** 1774,1780 ****
-    * Init support
-    */
-   
- ! static struct musb *__init
-   allocate_instance(struct device *dev,
-   		struct musb_hdrc_config *config, void __iomem *mbase)
-   {
- --- 1862,1868 ----
-    * Init support
-    */
-   
- ! static struct musb *__devinit
-   allocate_instance(struct device *dev,
-   		struct musb_hdrc_config *config, void __iomem *mbase)
-   {
- ***************
- *** 1782,1803 ****
-   	struct musb_hw_ep	*ep;
-   	int			epnum;
-   	struct usb_hcd	*hcd;
-   
- ! 	hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
- ! 	if (!hcd)
- ! 		return NULL;
- ! 	/* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
- ! 
- ! 	musb = hcd_to_musb(hcd);
- ! 	INIT_LIST_HEAD(&musb->control);
- ! 	INIT_LIST_HEAD(&musb->in_bulk);
- ! 	INIT_LIST_HEAD(&musb->out_bulk);
- ! 
- ! 	hcd->uses_new_polling = 1;
- ! 	hcd->has_tt = 1;
-   
- ! 	musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
- ! 	musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
-   	dev_set_drvdata(dev, musb);
-   	musb->mregs = mbase;
-   	musb->ctrl_base = mbase;
- --- 1870,1899 ----
-   	struct musb_hw_ep	*ep;
-   	int			epnum;
-   	struct usb_hcd	*hcd;
- + 	struct musb_hdrc_platform_data *plat = dev->platform_data;
-   
- ! 	if (plat->mode != MUSB_PERIPHERAL) {
- ! 		hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
- ! 		if (!hcd)
- ! 			return NULL;
- ! 		/* usbcore sets dev->driver_data to hcd, and sometimes uses
- ! 		 * that...
- ! 		 */
-   
- ! 		musb = hcd_to_musb(hcd);
- ! 		INIT_LIST_HEAD(&musb->control);
- ! 		INIT_LIST_HEAD(&musb->in_bulk);
- ! 		INIT_LIST_HEAD(&musb->out_bulk);
- ! 		INIT_LIST_HEAD(&musb->gb_list);
- ! 
- ! 		hcd->uses_new_polling = 1;
- ! 		hcd->has_tt = 1;
- ! 		musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
- ! 	} else {
- ! 		musb = kzalloc(sizeof *musb, GFP_KERNEL);
- ! 		if (!musb)
- ! 			return NULL;
- ! 	}
-   	dev_set_drvdata(dev, musb);
-   	musb->mregs = mbase;
-   	musb->ctrl_base = mbase;
- ***************
- *** 1827,1833 ****
-   	sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
-   #endif
-   
- ! 	musb_gadget_cleanup(musb);
-   
-   	if (musb->nIrq >= 0) {
-   		if (musb->irq_wake)
- --- 1923,1930 ----
-   	sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
-   #endif
-   
- ! 	if (is_peripheral_enabled(musb))
- ! 		musb_gadget_cleanup(musb);
-   
-   	if (musb->nIrq >= 0) {
-   		if (musb->irq_wake)
- ***************
- *** 1838,1847 ****
-   		struct dma_controller	*c = musb->dma_controller;
-   
-   		(void) c->stop(c);
- ! 		dma_controller_destroy(c);
-   	}
-   
- ! 	kfree(musb);
-   }
-   
-   /*
- --- 1935,1953 ----
-   		struct dma_controller	*c = musb->dma_controller;
-   
-   		(void) c->stop(c);
- ! 		musb->ops->dma_controller_destroy(c);
-   	}
-   
- ! 	if (is_otg_enabled(musb))
- ! 		del_timer_sync(&musb->otg_timer);
- ! 
- ! 	if (is_host_enabled(musb)) {
- ! 		if (musb->gb_queue)
- ! 			destroy_workqueue(musb->gb_queue);
- ! 		usb_put_hcd(musb_to_hcd(musb));
- ! 	} else {
- ! 		kfree(musb);
- ! 	}
-   }
-   
-   /*
- ***************
- *** 1852,1863 ****
-    * @mregs: virtual address of controller registers,
-    *	not yet corrected for platform-specific offsets
-    */
- ! static int __init
-   musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
-   {
-   	int			status;
-   	struct musb		*musb;
-   	struct musb_hdrc_platform_data *plat = dev->platform_data;
-   
-   	/* The driver might handle more features than the board; OK.
-   	 * Fail when the board needs a feature that's not enabled.
- --- 1958,1970 ----
-    * @mregs: virtual address of controller registers,
-    *	not yet corrected for platform-specific offsets
-    */
- ! static int __devinit
-   musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
-   {
-   	int			status;
-   	struct musb		*musb;
-   	struct musb_hdrc_platform_data *plat = dev->platform_data;
- + 	struct platform_device *pdev = to_platform_device(dev);
-   
-   	/* The driver might handle more features than the board; OK.
-   	 * Fail when the board needs a feature that's not enabled.
- ***************
- *** 1884,1889 ****
- --- 1991,2015 ----
-   	musb->board_set_power = plat->set_power;
-   	musb->min_power = plat->min_power;
-   	musb->ops = plat->platform_ops;
- + 	musb->id = pdev->id;
- + 	musb->first = 1;
- + 	if (is_host_enabled(musb))
- + 		spin_lock_init(&musb->gb_lock);
- + 
- + 	musb->fifo_mode = musb->ops->fifo_mode;
- + 
- + #ifndef CONFIG_MUSB_PIO_ONLY
- + 	musb->orig_dma_mask = dev->dma_mask;
- + #endif
- + 	if (musb->ops->flags & MUSB_GLUE_TUSB_STYLE) {
- + 		musb_readb = __tusb_musb_readb;
- + 		musb_writeb = __tusb_musb_writeb;
- + 	} else {
- + 		musb_readb = __musb_readb;
- + 		musb_writeb = __musb_writeb;
- + 	}
- + 
- + 	dev_info(dev, "dma type: %s\n", get_dma_name(musb));
-   
-   	/* The musb_platform_init() call:
-   	 *   - adjusts musb->mregs and musb->isr if needed,
- ***************
- *** 1912,1921 ****
-   	}
-   
-   #ifndef CONFIG_MUSB_PIO_ONLY
- ! 	if (use_dma && dev->dma_mask) {
-   		struct dma_controller	*c;
-   
- ! 		c = dma_controller_create(musb, musb->mregs);
-   		musb->dma_controller = c;
-   		if (c)
-   			(void) c->start(c);
- --- 2038,2052 ----
-   	}
-   
-   #ifndef CONFIG_MUSB_PIO_ONLY
- ! 	if (dev->dma_mask) {
-   		struct dma_controller	*c;
-   
- ! 		if (!musb->ops->dma_controller_create) {
- ! 			dev_err(dev, "no dma_controller_create for non-PIO mode!\n");
- ! 			status = -ENODEV;
- ! 			goto fail3;
- ! 		}
- ! 		c = musb->ops->dma_controller_create(musb, musb->mregs);
-   		musb->dma_controller = c;
-   		if (c)
-   			(void) c->start(c);
- ***************
- *** 1936,1943 ****
-   	if (status < 0)
-   		goto fail3;
-   
- - 	setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
- - 
-   	/* Init IRQ workqueue before request_irq */
-   	INIT_WORK(&musb->irq_work, musb_irq_work);
-   
- --- 2067,2072 ----
- ***************
- *** 1949,1960 ****
-   	}
-   	musb->nIrq = nIrq;
-   /* FIXME this handles wakeup irqs wrong */
- ! 	if (enable_irq_wake(nIrq) == 0) {
-   		musb->irq_wake = 1;
- ! 		device_init_wakeup(dev, 1);
- ! 	} else {
-   		musb->irq_wake = 0;
- ! 	}
-   
-   	/* host side needs more setup */
-   	if (is_host_enabled(musb)) {
- --- 2078,2089 ----
-   	}
-   	musb->nIrq = nIrq;
-   /* FIXME this handles wakeup irqs wrong */
- ! 	if (enable_irq_wake(nIrq) == 0)
-   		musb->irq_wake = 1;
- ! 	else
-   		musb->irq_wake = 0;
- ! 
- ! 	device_init_wakeup(dev, 1);
-   
-   	/* host side needs more setup */
-   	if (is_host_enabled(musb)) {
- ***************
- *** 1987,1993 ****
-   		musb->xceiv->state = OTG_STATE_A_IDLE;
-   
-   		status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
- ! 
-   		hcd->self.uses_pio_for_control = 1;
-   		dev_dbg(musb->controller, "%s mode, status %d, devctl %02x %c\n",
-   			"HOST", status,
- --- 2116,2122 ----
-   		musb->xceiv->state = OTG_STATE_A_IDLE;
-   
-   		status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
- ! 		device_set_wakeup_enable(dev, 0);
-   		hcd->self.uses_pio_for_control = 1;
-   		dev_dbg(musb->controller, "%s mode, status %d, devctl %02x %c\n",
-   			"HOST", status,
- ***************
- *** 2002,2007 ****
- --- 2131,2137 ----
-   		musb->xceiv->state = OTG_STATE_B_IDLE;
-   
-   		status = musb_gadget_setup(musb);
- + 		device_set_wakeup_enable(dev, 0);
-   
-   		dev_dbg(musb->controller, "%s mode, status %d, dev%02x\n",
-   			is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
- ***************
- *** 2034,2041 ****
- --- 2164,2193 ----
-   			? "DMA" : "PIO",
-   			musb->nIrq);
-   
- + 	if (status == 0) {
- + 		u8 drvbuf[19];
- + 		sprintf(drvbuf, "driver/musb_hdrc.%d", musb->id);
- + 		musb_debug_create(drvbuf, musb);
- + 	}
- + 
- + 	if (is_host_enabled(musb)) {
- + 		musb->gb_queue = create_singlethread_workqueue(dev_name(dev));
- + 		if (musb->gb_queue == NULL)
- + 			goto fail6;
- + 		/* Init giveback workqueue */
- + 		INIT_WORK(&musb->gb_work, musb_gb_work);
- + 	}
- + 
- + 	/* setup otg_timer */
- + 	if (is_otg_enabled(musb))
- + 		setup_timer(&musb->otg_timer, musb_otg_timer_func,
- + 						(unsigned long) musb);
-   	return 0;
-   
- + fail6:
- + 	if (is_host_enabled(musb))
- + 		destroy_workqueue(musb->gb_queue);
- + 
-   fail5:
-   	musb_exit_debugfs(musb);
-   
- ***************
- *** 2067,2086 ****
-   /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
-    * bridge to a platform device; this driver then suffices.
-    */
- ! 
- ! #ifndef CONFIG_MUSB_PIO_ONLY
- ! static u64	*orig_dma_mask;
- ! #endif
- ! 
- ! static int __init musb_probe(struct platform_device *pdev)
-   {
-   	struct device	*dev = &pdev->dev;
-   	int		irq = platform_get_irq_byname(pdev, "mc");
-   	int		status;
-   	struct resource	*iomem;
-   	void __iomem	*base;
-   
- - 	iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-   	if (!iomem || irq <= 0)
-   		return -ENODEV;
-   
- --- 2219,2247 ----
-   /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
-    * bridge to a platform device; this driver then suffices.
-    */
- ! static int __devinit musb_probe(struct platform_device *pdev)
-   {
-   	struct device	*dev = &pdev->dev;
-   	int		irq = platform_get_irq_byname(pdev, "mc");
-   	int		status;
-   	struct resource	*iomem;
-   	void __iomem	*base;
- + 	char	res_name[20];
- + 
- + 	if (pdev->id == -1)
- + 		strcpy(res_name, "mc");
- + 	else
- + 		sprintf(res_name, "musb%d-irq", pdev->id);
- + 	irq = platform_get_irq_byname(pdev, res_name);
- + 
- + 	if (pdev->id == -1)
- + 		iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- + 	else {
- + 		sprintf(res_name, "musb%d", pdev->id);
- + 		iomem = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- + 			res_name);
- + 	}
-   
-   	if (!iomem || irq <= 0)
-   		return -ENODEV;
-   
- ***************
- *** 2090,2099 ****
-   		return -ENOMEM;
-   	}
-   
- - #ifndef CONFIG_MUSB_PIO_ONLY
- - 	/* clobbered by use_dma=n */
- - 	orig_dma_mask = dev->dma_mask;
- - #endif
-   	status = musb_init_controller(dev, irq, base);
-   	if (status < 0)
-   		iounmap(base);
- --- 2251,2256 ----
- ***************
- *** 2105,2110 ****
- --- 2262,2268 ----
-   {
-   	struct musb	*musb = dev_to_musb(&pdev->dev);
-   	void __iomem	*ctrl_base = musb->ctrl_base;
- + 	u8 drvbuf[19];
-   
-   	/* this gets called on rmmod.
-   	 *  - Host mode: host may still be active
- ***************
- *** 2114,2133 ****
-   	pm_runtime_get_sync(musb->controller);
-   	musb_exit_debugfs(musb);
-   	musb_shutdown(pdev);
-   
-   	pm_runtime_put(musb->controller);
-   	musb_free(musb);
-   	iounmap(ctrl_base);
-   	device_init_wakeup(&pdev->dev, 0);
-   #ifndef CONFIG_MUSB_PIO_ONLY
- ! 	pdev->dev.dma_mask = orig_dma_mask;
-   #endif
-   	return 0;
-   }
-   
-   #ifdef	CONFIG_PM
-   
- ! static void musb_save_context(struct musb *musb)
-   {
-   	int i;
-   	void __iomem *musb_base = musb->mregs;
- --- 2272,2293 ----
-   	pm_runtime_get_sync(musb->controller);
-   	musb_exit_debugfs(musb);
-   	musb_shutdown(pdev);
- + 	sprintf(drvbuf, "driver/musb_hdrc.%d", musb->id);
- + 	musb_debug_delete(drvbuf, musb);
-   
-   	pm_runtime_put(musb->controller);
-   	musb_free(musb);
-   	iounmap(ctrl_base);
-   	device_init_wakeup(&pdev->dev, 0);
-   #ifndef CONFIG_MUSB_PIO_ONLY
- ! 	pdev->dev.dma_mask = musb->orig_dma_mask;
-   #endif
-   	return 0;
-   }
-   
-   #ifdef	CONFIG_PM
-   
- ! void musb_save_context(struct musb *musb)
-   {
-   	int i;
-   	void __iomem *musb_base = musb->mregs;
- ***************
- *** 2156,2161 ****
- --- 2316,2322 ----
-   		if (!epio)
-   			continue;
-   
- + 		musb_writeb(musb_base, MUSB_INDEX, i);
-   		musb->context.index_regs[i].txmaxp =
-   			musb_readw(epio, MUSB_TXMAXP);
-   		musb->context.index_regs[i].txcsr =
- ***************
- *** 2201,2208 ****
-   		}
-   	}
-   }
-   
- ! static void musb_restore_context(struct musb *musb)
-   {
-   	int i;
-   	void __iomem *musb_base = musb->mregs;
- --- 2362,2370 ----
-   		}
-   	}
-   }
- + EXPORT_SYMBOL(musb_save_context);
-   
- ! void musb_restore_context(struct musb *musb)
-   {
-   	int i;
-   	void __iomem *musb_base = musb->mregs;
- ***************
- *** 2231,2236 ****
- --- 2393,2399 ----
-   		if (!epio)
-   			continue;
-   
- + 		musb_writeb(musb_base, MUSB_INDEX, i);
-   		musb_writew(epio, MUSB_TXMAXP,
-   			musb->context.index_regs[i].txmaxp);
-   		musb_writew(epio, MUSB_TXCSR,
- ***************
- *** 2281,2297 ****
-   	}
-   	musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
-   }
-   
-   static int musb_suspend(struct device *dev)
-   {
-   	struct musb	*musb = dev_to_musb(dev);
-   	unsigned long	flags;
-   
-   	spin_lock_irqsave(&musb->lock, flags);
-   
-   	if (is_peripheral_active(musb)) {
- ! 		/* FIXME force disconnect unless we know USB will wake
- ! 		 * the system up quickly enough to respond ...
-   		 */
-   	} else if (is_host_active(musb)) {
-   		/* we know all the children are suspended; sometimes
- --- 2444,2463 ----
-   	}
-   	musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
-   }
- + EXPORT_SYMBOL(musb_restore_context);
-   
-   static int musb_suspend(struct device *dev)
-   {
-   	struct musb	*musb = dev_to_musb(dev);
-   	unsigned long	flags;
- + 	int ret = 0;
-   
-   	spin_lock_irqsave(&musb->lock, flags);
-   
-   	if (is_peripheral_active(musb)) {
- ! 		/*
- ! 		 * Don't allow system suspend while peripheral mode
- ! 		 * is actve and cable is connected to host.
-   		 */
-   	} else if (is_host_active(musb)) {
-   		/* we know all the children are suspended; sometimes
- ***************
- *** 2300,2306 ****
-   	}
-   
-   	spin_unlock_irqrestore(&musb->lock, flags);
- ! 	return 0;
-   }
-   
-   static int musb_resume_noirq(struct device *dev)
- --- 2466,2472 ----
-   	}
-   
-   	spin_unlock_irqrestore(&musb->lock, flags);
- ! 	return ret;
-   }
-   
-   static int musb_resume_noirq(struct device *dev)
- ***************
- *** 2324,2330 ****
-   static int musb_runtime_resume(struct device *dev)
-   {
-   	struct musb	*musb = dev_to_musb(dev);
- - 	static int	first = 1;
-   
-   	/*
-   	 * When pm_runtime_get_sync called for the first time in driver
- --- 2490,2495 ----
- ***************
- *** 2335,2343 ****
-   	 * Also context restore without save does not make
-   	 * any sense
-   	 */
- ! 	if (!first)
-   		musb_restore_context(musb);
- ! 	first = 0;
-   
-   	return 0;
-   }
- --- 2500,2510 ----
-   	 * Also context restore without save does not make
-   	 * any sense
-   	 */
- ! 	if (musb->first)
- ! 		musb->first = 0;
- ! 	else
-   		musb_restore_context(musb);
- ! 
-   
-   	return 0;
-   }
- ***************
- *** 2361,2366 ****
- --- 2528,2534 ----
-   		.owner		= THIS_MODULE,
-   		.pm		= MUSB_DEV_PM_OPS,
-   	},
- + 	.probe      = musb_probe,
-   	.remove		= __exit_p(musb_remove),
-   	.shutdown	= musb_shutdown,
-   };
- ***************
- *** 2377,2383 ****
-   		", "
-   		"otg (peripheral+host)",
-   		musb_driver_name);
- ! 	return platform_driver_probe(&musb_driver, musb_probe);
-   }
-   
-   /* make us init after usbcore and i2c (transceivers, regulators, etc)
- --- 2545,2551 ----
-   		", "
-   		"otg (peripheral+host)",
-   		musb_driver_name);
- ! 	return platform_driver_register(&musb_driver);
-   }
-   
-   /* make us init after usbcore and i2c (transceivers, regulators, etc)
- diff -crN linux-3.2.1_o/drivers/usb/musb/musb_core.h linux-3.2.1/drivers/usb/musb/musb_core.h
- *** linux-3.2.1_o/drivers/usb/musb/musb_core.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/musb/musb_core.h	2014-05-15 13:25:15.086916190 +0900
- ***************
- *** 39,46 ****
-   #include <linux/list.h>
-   #include <linux/interrupt.h>
-   #include <linux/errno.h>
- - #include <linux/timer.h>
- - #include <linux/clk.h>
-   #include <linux/device.h>
-   #include <linux/usb/ch9.h>
-   #include <linux/usb/gadget.h>
- --- 39,44 ----
- ***************
- *** 62,67 ****
- --- 60,68 ----
-   #define MUSB_HWVERS_1900	0x784
-   #define MUSB_HWVERS_2000	0x800
-   
- + extern u8 (*musb_readb)(const void __iomem *addr, unsigned offset);
- + extern void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data);
- + 
-   #include "musb_debug.h"
-   #include "musb_dma.h"
-   
- ***************
- *** 97,104 ****
-   
-   /****************************** PERIPHERAL ROLE *****************************/
-   
- - #define	is_peripheral_capable()	(1)
- - 
-   extern irqreturn_t musb_g_ep0_irq(struct musb *);
-   extern void musb_g_tx(struct musb *, u8);
-   extern void musb_g_rx(struct musb *, u8);
- --- 98,103 ----
- ***************
- *** 110,117 ****
-   
-   /****************************** HOST ROLE ***********************************/
-   
- - #define	is_host_capable()	(1)
- - 
-   extern irqreturn_t musb_h_ep0_irq(struct musb *);
-   extern void musb_host_tx(struct musb *, u8);
-   extern void musb_host_rx(struct musb *, u8);
- --- 109,114 ----
- ***************
- *** 146,160 ****
-   	MUSB_EP0_STAGE_ACKWAIT,		/* after zlp, before statusin */
-   } __attribute__ ((packed));
-   
- ! /*
- !  * OTG protocol constants.  See USB OTG 1.3 spec,
- !  * sections 5.5 "Device Timings" and 6.6.5 "Timers".
- !  */
-   #define OTG_TIME_A_WAIT_VRISE	100		/* msec (max) */
- ! #define OTG_TIME_A_WAIT_BCON	1100		/* min 1 second */
- ! #define OTG_TIME_A_AIDL_BDIS	200		/* min 200 msec */
- ! #define OTG_TIME_B_ASE0_BRST	100		/* min 3.125 ms */
- ! 
-   
-   /*************************** REGISTER ACCESS ********************************/
-   
- --- 143,152 ----
-   	MUSB_EP0_STAGE_ACKWAIT,		/* after zlp, before statusin */
-   } __attribute__ ((packed));
-   
- ! /* OTG protocol constants */
-   #define OTG_TIME_A_WAIT_VRISE	100		/* msec (max) */
- ! #define OTG_TIME_A_WAIT_BCON	0		/* 0=infinite; min 1000 msec */
- ! #define OTG_TIME_A_IDLE_BDIS	200		/* msec (min) */
-   
-   /*************************** REGISTER ACCESS ********************************/
-   
- ***************
- *** 162,195 ****
-    * directly with the "flat" model, or after setting up an index register.
-    */
-   
- ! #if defined(CONFIG_ARCH_DAVINCI) || defined(CONFIG_SOC_OMAP2430) \
- ! 		|| defined(CONFIG_SOC_OMAP3430) || defined(CONFIG_BLACKFIN) \
- ! 		|| defined(CONFIG_ARCH_OMAP4)
- ! /* REVISIT indexed access seemed to
- !  * misbehave (on DaVinci) for at least peripheral IN ...
- !  */
- ! #define	MUSB_FLAT_REG
- ! #endif
- ! 
- ! /* TUSB mapping: "flat" plus ep0 special cases */
- ! #if defined(CONFIG_USB_MUSB_TUSB6010) || \
- ! 	defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
- ! #define musb_ep_select(_mbase, _epnum) \
- ! 	musb_writeb((_mbase), MUSB_INDEX, (_epnum))
- ! #define	MUSB_EP_OFFSET			MUSB_TUSB_OFFSET
- ! 
- ! /* "flat" mapping: each endpoint has its own i/o address */
- ! #elif	defined(MUSB_FLAT_REG)
- ! #define musb_ep_select(_mbase, _epnum)	(((void)(_mbase)), ((void)(_epnum)))
- ! #define	MUSB_EP_OFFSET			MUSB_FLAT_OFFSET
- ! 
- ! /* "indexed" mapping: INDEX register controls register bank select */
- ! #else
- ! #define musb_ep_select(_mbase, _epnum) \
- ! 	musb_writeb((_mbase), MUSB_INDEX, (_epnum))
- ! #define	MUSB_EP_OFFSET			MUSB_INDEXED_OFFSET
- ! #endif
-   
-   /****************************** FUNCTIONS ********************************/
-   
-   #define MUSB_HST_MODE(_musb)\
- --- 154,165 ----
-    * directly with the "flat" model, or after setting up an index register.
-    */
-   
- ! #define musb_ep_select(_musb, _mbase, _epnum) do { \
- ! 	if (_musb->ops->flags & MUSB_GLUE_EP_ADDR_INDEXED_MAPPING) \
- ! 		musb_writeb((_mbase), MUSB_INDEX, (_epnum)); \
- !  } while (0)
-   
- + #define	MUSB_EP_OFFSET	MUSB_OFFSET
-   /****************************** FUNCTIONS ********************************/
-   
-   #define MUSB_HST_MODE(_musb)\
- ***************
- *** 204,235 ****
- --- 174,236 ----
-   
-   /******************************** TYPES *************************************/
-   
- + #define     MUSB_GLUE_TUSB_STYLE   0x0001
- + #define     MUSB_GLUE_EP_ADDR_FLAT_MAPPING	0x0002
- + #define     MUSB_GLUE_EP_ADDR_INDEXED_MAPPING	0x0004
- + #define		MUSB_GLUE_DMA_INVENTRA				0x0008
- + #define		MUSB_GLUE_DMA_CPPI					0x0010
- + #define		MUSB_GLUE_DMA_TUSB					0x0020
- + #define		MUSB_GLUE_DMA_UX500					0x0040
- + #define		MUSB_GLUE_DMA_CPPI41					0x0080
- + 
- + 
-   /**
-    * struct musb_platform_ops - Operations passed to musb_core by HW glue layer
- +  * @fifo_mode: which fifo_mode is taken by me
- +  * @flags:	each hw glue difference information will be here
-    * @init:	turns on clocks, sets up platform-specific registers, etc
-    * @exit:	undoes @init
- +  * @read_fifo: read data from musb fifo in PIO
- +  * @write_fifo: write data into musb fifo in PIO
-    * @set_mode:	forcefully changes operating mode
-    * @try_ilde:	tries to idle the IP
- +  * @get_hw_revision: get hardware revision
-    * @vbus_status: returns vbus status if possible
-    * @set_vbus:	forces vbus status
-    * @adjust_channel_params: pre check for standard dma channel_program func
- +  * @dma_controller_create: create dma controller for me
- +  * @dma_controller_destroy: destroy dma controller
-    */
-   struct musb_platform_ops {
- + 	short	fifo_mode;
- + 	unsigned short	flags;
-   	int	(*init)(struct musb *musb);
-   	int	(*exit)(struct musb *musb);
-   
-   	void	(*enable)(struct musb *musb);
-   	void	(*disable)(struct musb *musb);
-   
- + 	void (*read_fifo)(struct musb_hw_ep *hw_ep, u16 len, u8 *buf);
- + 	void (*write_fifo)(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf);
- + 
-   	int	(*set_mode)(struct musb *musb, u8 mode);
-   	void	(*try_idle)(struct musb *musb, unsigned long timeout);
-   
- + 	u16  (*get_hw_revision)(struct musb *musb);
- + 
-   	int	(*vbus_status)(struct musb *musb);
-   	void	(*set_vbus)(struct musb *musb, int on);
-   
-   	int	(*adjust_channel_params)(struct dma_channel *channel,
-   				u16 packet_sz, u8 *mode,
-   				dma_addr_t *dma_addr, u32 *len);
- + 	struct dma_controller* (*dma_controller_create)(struct musb *,
- + 		void __iomem *);
- + 	void (*dma_controller_destroy)(struct dma_controller *);
- + 	int (*simulate_babble_intr)(struct musb *musb);
- + 	void (*txfifoempty_intr_enable)(struct musb *musb, u8 ep_num);
- + 	void (*txfifoempty_intr_disable)(struct musb *musb, u8 ep_num);
- + 	void (*reinit)(u16 musb_type, struct musb *musb);
-   };
-   
-   /*
- ***************
- *** 242,251 ****
-   	void __iomem		*fifo;
-   	void __iomem		*regs;
-   
- ! #if defined(CONFIG_USB_MUSB_TUSB6010) || \
- ! 	defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
-   	void __iomem		*conf;
- - #endif
-   
-   	/* index in musb->endpoints[]  */
-   	u8			epnum;
- --- 243,250 ----
-   	void __iomem		*fifo;
-   	void __iomem		*regs;
-   
- ! 	/*Fixme: the following field is only used by tusb*/
-   	void __iomem		*conf;
-   
-   	/* index in musb->endpoints[]  */
-   	u8			epnum;
- ***************
- *** 260,272 ****
-   	struct dma_channel	*tx_channel;
-   	struct dma_channel	*rx_channel;
-   
- ! #if defined(CONFIG_USB_MUSB_TUSB6010) || \
- ! 	defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
- ! 	/* TUSB has "asynchronous" and "synchronous" dma modes */
-   	dma_addr_t		fifo_async;
-   	dma_addr_t		fifo_sync;
-   	void __iomem		*fifo_sync_va;
- - #endif
-   
-   	void __iomem		*target_regs;
-   
- --- 259,271 ----
-   	struct dma_channel	*tx_channel;
-   	struct dma_channel	*rx_channel;
-   
- ! 	/*
- ! 	 * TUSB has "asynchronous" and "synchronous" dma modes
- ! 	 * Fixme: the following three fields are only valid for TUSB.
- ! 	 * */
-   	dma_addr_t		fifo_async;
-   	dma_addr_t		fifo_sync;
-   	void __iomem		*fifo_sync_va;
-   
-   	void __iomem		*target_regs;
-   
- ***************
- *** 280,285 ****
- --- 279,287 ----
-   	/* peripheral side */
-   	struct musb_ep		ep_in;			/* TX */
-   	struct musb_ep		ep_out;			/* RX */
- + 
- + 	u8			prev_toggle;		/* Rx */
- + 	u8			xfer_type;
-   };
-   
-   static inline struct musb_request *next_in_request(struct musb_hw_ep *hw_ep)
- ***************
- *** 311,316 ****
- --- 313,319 ----
-   	u8 index, testmode;
-   
-   	u8 devctl, busctl, misc;
- + 	u32 otg_interfsel;
-   
-   	struct musb_csr_regs index_regs[MUSB_C_NUM_EPS];
-   };
- ***************
- *** 327,332 ****
- --- 330,338 ----
-   
-   	irqreturn_t		(*isr)(int, void *);
-   	struct work_struct	irq_work;
- + 	struct work_struct      work;
- + 	struct work_struct	otg_notifier_work;
- + 	u8                      enable_babble_work;
-   	u16			hwvers;
-   
-   /* this hub status bit is reserved by USB 2.0 and not seen by usbcore */
- ***************
- *** 350,356 ****
-   	struct list_head	in_bulk;	/* of musb_qh */
-   	struct list_head	out_bulk;	/* of musb_qh */
-   
- ! 	struct timer_list	otg_timer;
-   	struct notifier_block	nb;
-   
-   	struct dma_controller	*dma_controller;
- --- 356,366 ----
-   	struct list_head	in_bulk;	/* of musb_qh */
-   	struct list_head	out_bulk;	/* of musb_qh */
-   
- ! 	struct workqueue_struct *gb_queue;
- ! 	struct work_struct      gb_work;
- ! 	spinlock_t              gb_lock;
- ! 	struct list_head        gb_list;        /* of urbs */
- ! 
-   	struct notifier_block	nb;
-   
-   	struct dma_controller	*dma_controller;
- ***************
- *** 359,370 ****
-   	void __iomem		*ctrl_base;
-   	void __iomem		*mregs;
-   
- ! #if defined(CONFIG_USB_MUSB_TUSB6010) || \
- ! 	defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
-   	dma_addr_t		async;
-   	dma_addr_t		sync;
-   	void __iomem		*sync_va;
- - #endif
-   
-   	/* passed down from chip/board specific irq handlers */
-   	u8			int_usb;
- --- 369,378 ----
-   	void __iomem		*ctrl_base;
-   	void __iomem		*mregs;
-   
- ! 	/*Fixme: the three fields below are only used by tusb*/
-   	dma_addr_t		async;
-   	dma_addr_t		sync;
-   	void __iomem		*sync_va;
-   
-   	/* passed down from chip/board specific irq handlers */
-   	u8			int_usb;
- ***************
- *** 372,377 ****
- --- 380,386 ----
-   	u16			int_tx;
-   
-   	struct otg_transceiver	*xceiv;
- + 	u8			xceiv_event;
-   
-   	int nIrq;
-   	unsigned		irq_wake:1;
- ***************
- *** 454,459 ****
- --- 463,486 ----
-   #ifdef MUSB_CONFIG_PROC_FS
-   	struct proc_dir_entry *proc_entry;
-   #endif
- + 	/* id for multiple musb instances */
- + 	u8			id;
- + 	struct	timer_list	otg_workaround;
- + 	unsigned long		last_timer;
- + 	int			first;
- + 	int			old_state;
- + 	struct	timer_list	otg_timer;
- + 	u8			en_otg_timer;
- + 	u8			en_otgw_timer;
- + #ifndef CONFIG_MUSB_PIO_ONLY
- + 	u64			*orig_dma_mask;
- + #endif
- + 	short			fifo_mode;
- + 	u8			txfifo_intr_enable;
- + 	u8			datatog_fix;
- + 	u8			hw_babble_ctrl;
- + 	u8			sof_enabled;
- + 	u32			sof_cnt;
-   };
-   
-   static inline struct musb *gadget_to_musb(struct usb_gadget *g)
- ***************
- *** 496,502 ****
-   	u8 reg = 0;
-   
-   	/* read from core using indexed model */
- ! 	reg = musb_readb(mbase, MUSB_EP_OFFSET(epnum, MUSB_FIFOSIZE));
-   	/* 0's returned when no more endpoints */
-   	if (!reg)
-   		return -ENODEV;
- --- 523,529 ----
-   	u8 reg = 0;
-   
-   	/* read from core using indexed model */
- ! 	reg = musb_readb(mbase, MUSB_EP_OFFSET(musb, epnum, MUSB_FIFOSIZE));
-   	/* 0's returned when no more endpoints */
-   	if (!reg)
-   		return -ENODEV;
- ***************
- *** 544,549 ****
- --- 571,588 ----
-   
-   extern void musb_hnp_stop(struct musb *musb);
-   
- + static inline void txfifoempty_int_enable(struct musb *musb, u8 ep_num)
- + {
- + 	if (musb->ops->txfifoempty_intr_enable)
- + 		musb->ops->txfifoempty_intr_enable(musb, ep_num);
- + }
- + 
- + static inline void txfifoempty_int_disable(struct musb *musb, u8 ep_num)
- + {
- + 	if (musb->ops->txfifoempty_intr_disable)
- + 		musb->ops->txfifoempty_intr_disable(musb, ep_num);
- + }
- + 
-   static inline void musb_platform_set_vbus(struct musb *musb, int is_on)
-   {
-   	if (musb->ops->set_vbus)
- ***************
- *** 601,604 ****
- --- 640,687 ----
-   	return musb->ops->exit(musb);
-   }
-   
- + static inline u16 musb_platform_get_hw_revision(struct musb *musb)
- + {
- + 	if (!musb->ops->get_hw_revision)
- + 		return musb_readw(musb->mregs, MUSB_HWVERS);
- + 
- + 	return musb->ops->get_hw_revision(musb);
- + }
- + 
- + static inline int musb_simulate_babble_intr(struct musb *musb)
- + {
- + 	if (!musb->ops->simulate_babble_intr)
- + 		return -EINVAL;
- + 
- + 	return musb->ops->simulate_babble_intr(musb);
- + }
- + 
- + static inline const char *get_dma_name(struct musb *musb)
- + {
- + #ifdef CONFIG_MUSB_PIO_ONLY
- + 	return "pio";
- + #else
- + 	if (musb->ops->flags & MUSB_GLUE_DMA_INVENTRA)
- + 		return "dma-inventra";
- + 	else if (musb->ops->flags & MUSB_GLUE_DMA_CPPI)
- + 		return "dma-cppi3";
- + 	else if (musb->ops->flags & MUSB_GLUE_DMA_CPPI41)
- + 		return "dma-cppi41";
- + 	else if (musb->ops->flags & MUSB_GLUE_DMA_TUSB)
- + 		return "dma-tusb-omap";
- + 	else
- + 		return "?dma?";
- + #endif
- + }
- + extern void musb_reinit(u16 musb_type, struct musb *musb);
- + 
- + extern void musb_gb_work(struct work_struct *data);
- + /*-------------------------- ProcFS definitions ---------------------*/
- + 
- + struct proc_dir_entry;
- + 
- + extern struct proc_dir_entry *musb_debug_create(char *name, struct musb *data);
- + extern void musb_debug_delete(char *name, struct musb *data);
- + extern void musb_save_context(struct musb *musb);
- + extern void musb_restore_context(struct musb *musb);
-   #endif	/* __MUSB_CORE_H__ */
- diff -crN linux-3.2.1_o/drivers/usb/musb/musb_debugfs.c linux-3.2.1/drivers/usb/musb/musb_debugfs.c
- *** linux-3.2.1_o/drivers/usb/musb/musb_debugfs.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/musb/musb_debugfs.c	2014-05-15 13:25:15.086916190 +0900
- ***************
- *** 33,43 ****
-   
-   #include <linux/module.h>
-   #include <linux/kernel.h>
- - #include <linux/sched.h>
-   #include <linux/init.h>
- - #include <linux/list.h>
- - #include <linux/platform_device.h>
- - #include <linux/io.h>
-   #include <linux/debugfs.h>
-   #include <linux/seq_file.h>
-   
- --- 33,39 ----
- ***************
- *** 46,55 ****
-   #include "musb_core.h"
-   #include "musb_debug.h"
-   
- - #ifdef CONFIG_ARCH_DAVINCI
- - #include "davinci.h"
- - #endif
- - 
-   struct musb_register_map {
-   	char			*name;
-   	unsigned		offset;
- --- 42,47 ----
- ***************
- *** 111,117 ****
-   	{  }	/* Terminating Entry */
-   };
-   
- ! static struct dentry *musb_debugfs_root;
-   
-   static int musb_regdump_show(struct seq_file *s, void *unused)
-   {
- --- 103,109 ----
-   	{  }	/* Terminating Entry */
-   };
-   
- ! static struct dentry *musb_debugfs_root[2];
-   
-   static int musb_regdump_show(struct seq_file *s, void *unused)
-   {
- ***************
- *** 231,236 ****
- --- 223,229 ----
-   		test = MUSB_TEST_SE0_NAK;
-   
-   	musb_writeb(musb->mregs, MUSB_TESTMODE, test);
- + 	pr_info("%smusb%d: test-mode value %x\n", buf, musb->id, test);
-   
-   	return count;
-   }
- ***************
- *** 243,255 ****
-   	.release		= single_release,
-   };
-   
- ! int __init musb_init_debugfs(struct musb *musb)
-   {
-   	struct dentry		*root;
-   	struct dentry		*file;
-   	int			ret;
-   
- ! 	root = debugfs_create_dir("musb", NULL);
-   	if (IS_ERR(root)) {
-   		ret = PTR_ERR(root);
-   		goto err0;
- --- 236,248 ----
-   	.release		= single_release,
-   };
-   
- ! int __devinit musb_init_debugfs(struct musb *musb)
-   {
-   	struct dentry		*root;
-   	struct dentry		*file;
-   	int			ret;
-   
- ! 	root = debugfs_create_dir(dev_name(musb->controller), NULL);
-   	if (IS_ERR(root)) {
-   		ret = PTR_ERR(root);
-   		goto err0;
- ***************
- *** 269,275 ****
-   		goto err1;
-   	}
-   
- ! 	musb_debugfs_root = root;
-   
-   	return 0;
-   
- --- 262,268 ----
-   		goto err1;
-   	}
-   
- ! 	musb_debugfs_root[musb->id] = root;
-   
-   	return 0;
-   
- ***************
- *** 280,286 ****
-   	return ret;
-   }
-   
- ! void /* __init_or_exit */ musb_exit_debugfs(struct musb *musb)
-   {
- ! 	debugfs_remove_recursive(musb_debugfs_root);
-   }
- --- 273,279 ----
-   	return ret;
-   }
-   
- ! void /* __devinit_or_exit */ musb_exit_debugfs(struct musb *musb)
-   {
- ! 	debugfs_remove_recursive(musb_debugfs_root[musb->id]);
-   }
- diff -crN linux-3.2.1_o/drivers/usb/musb/musb_debug.h linux-3.2.1/drivers/usb/musb/musb_debug.h
- *** linux-3.2.1_o/drivers/usb/musb/musb_debug.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/musb/musb_debug.h	2014-05-15 13:25:15.090635849 +0900
- ***************
- *** 43,50 ****
-   #define ERR(fmt, args...) yprintk(KERN_ERR, fmt, ## args)
-   
-   #ifdef CONFIG_DEBUG_FS
- ! extern int musb_init_debugfs(struct musb *musb);
- ! extern void musb_exit_debugfs(struct musb *musb);
-   #else
-   static inline int musb_init_debugfs(struct musb *musb)
-   {
- --- 43,50 ----
-   #define ERR(fmt, args...) yprintk(KERN_ERR, fmt, ## args)
-   
-   #ifdef CONFIG_DEBUG_FS
- ! int musb_init_debugfs(struct musb *musb);
- ! void musb_exit_debugfs(struct musb *musb);
-   #else
-   static inline int musb_init_debugfs(struct musb *musb)
-   {
- diff -crN linux-3.2.1_o/drivers/usb/musb/musb_dma.h linux-3.2.1/drivers/usb/musb/musb_dma.h
- *** linux-3.2.1_o/drivers/usb/musb/musb_dma.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/musb/musb_dma.h	2014-05-15 13:25:15.090635849 +0900
- ***************
- *** 68,83 ****
-   #define	is_dma_capable()	(0)
-   #endif
-   
-   #ifdef CONFIG_USB_TI_CPPI_DMA
- ! #define	is_cppi_enabled()	1
-   #else
- ! #define	is_cppi_enabled()	0
-   #endif
-   
-   #ifdef CONFIG_USB_TUSB_OMAP_DMA
- ! #define tusb_dma_omap()			1
-   #else
- ! #define tusb_dma_omap()			0
-   #endif
-   
-   /* Anomaly 05000456 - USB Receive Interrupt Is Not Generated in DMA Mode 1
- --- 68,102 ----
-   #define	is_dma_capable()	(0)
-   #endif
-   
- + #ifdef CONFIG_USB_UX500_DMA
- + #define	is_ux500_dma(musb)	(musb->ops->flags & MUSB_GLUE_DMA_UX500)
- + #else
- + #define	is_ux500_dma(musb)	0
- + #endif
- + 
- + #ifdef CONFIG_USB_INVENTRA_DMA
- + #define	is_inventra_dma(musb)	(musb->ops->flags & MUSB_GLUE_DMA_INVENTRA)
- + #else
- + #define	is_inventra_dma(musb)	0
- + #endif
- + 
-   #ifdef CONFIG_USB_TI_CPPI_DMA
- ! #define	is_cppi_enabled(musb)	(musb->ops->flags & MUSB_GLUE_DMA_CPPI)
- ! 
- ! #else
- ! #define	is_cppi_enabled(musb)	0
- ! #endif
- ! 
- ! #ifdef CONFIG_USB_TI_CPPI41_DMA
- ! #define is_cppi41_enabled(musb)	(musb->ops->flags & MUSB_GLUE_DMA_CPPI41)
-   #else
- ! #define is_cppi41_enabled(musb)     0
-   #endif
-   
-   #ifdef CONFIG_USB_TUSB_OMAP_DMA
- ! #define tusb_dma_omap(musb)		(musb->ops->flags & MUSB_GLUE_DMA_TUSB)
-   #else
- ! #define tusb_dma_omap(musb)		0
-   #endif
-   
-   /* Anomaly 05000456 - USB Receive Interrupt Is Not Generated in DMA Mode 1
- ***************
- *** 178,186 ****
-   extern void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit);
-   
-   
- ! extern struct dma_controller *__init
- ! dma_controller_create(struct musb *, void __iomem *);
-   
- ! extern void dma_controller_destroy(struct dma_controller *);
-   
-   #endif	/* __MUSB_DMA_H__ */
- --- 197,268 ----
-   extern void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit);
-   
-   
- ! #ifdef CONFIG_USB_TI_CPPI_DMA
- ! extern struct dma_controller *__devinit
- ! cppi_dma_controller_create(struct musb *, void __iomem *);
- ! 
- ! extern void cppi_dma_controller_destroy(struct dma_controller *);
- ! #else
- ! static inline struct dma_controller *__devinit
- ! cppi_dma_controller_create(struct musb *musb, void __iomem *mregs)
- ! {
- ! 	return NULL;
- ! }
- ! 
- ! static inline void cppi_dma_controller_destroy(struct dma_controller *c)
- ! {
- ! }
- ! #endif
- ! 
- ! #ifdef CONFIG_USB_TI_CPPI41_DMA
- ! extern struct dma_controller *__devinit
- ! cppi41_dma_controller_create(struct musb *, void __iomem *);
- ! 
- ! extern void cppi41_dma_controller_destroy(struct dma_controller *);
- ! #else
- ! static inline struct dma_controller *__devinit
- ! cppi41_dma_controller_create(struct musb *musb, void __iomem *mregs)
- ! {
- ! 	return NULL;
- ! }
- ! 
- ! static inline void cppi41_dma_controller_destroy(struct dma_controller *c)
- ! {
- ! }
- ! #endif
- ! 
- ! #ifdef CONFIG_USB_INVENTRA_DMA
- ! extern struct dma_controller *__devinit
- ! inventra_dma_controller_create(struct musb *, void __iomem *);
- ! 
- ! extern void inventra_dma_controller_destroy(struct dma_controller *);
- ! #else
- ! static inline struct dma_controller *__devinit
- ! inventra_dma_controller_create(struct musb *musb, void __iomem *mregs)
- ! {
- ! 	return NULL;
- ! }
-   
- ! static inline void inventra_dma_controller_destroy(struct dma_controller *c)
- ! {
- ! }
- ! #endif
- ! 
- ! #ifdef CONFIG_USB_TUSB_OMAP_DMA
- ! extern struct dma_controller *__devinit
- ! tusb_dma_controller_create(struct musb *, void __iomem *);
- ! 
- ! extern void tusb_dma_controller_destroy(struct dma_controller *);
- ! #else
- ! static inline struct dma_controller *__devinit
- ! tusb_dma_controller_create(struct musb *musb, void __iomem *mregs)
- ! {
- ! 	return NULL;
- ! }
- ! 
- ! static inline void tusb_dma_controller_destroy(struct dma_controller *c)
- ! {
- ! }
- ! #endif
-   
-   #endif	/* __MUSB_DMA_H__ */
- diff -crN linux-3.2.1_o/drivers/usb/musb/musb_gadget.c linux-3.2.1/drivers/usb/musb/musb_gadget.c
- *** linux-3.2.1_o/drivers/usb/musb/musb_gadget.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/musb/musb_gadget.c	2014-05-15 13:25:15.090635849 +0900
- ***************
- *** 40,47 ****
-   #include <linux/smp.h>
-   #include <linux/spinlock.h>
-   #include <linux/delay.h>
- - #include <linux/moduleparam.h>
- - #include <linux/stat.h>
-   #include <linux/dma-mapping.h>
-   #include <linux/slab.h>
-   
- --- 40,45 ----
- ***************
- *** 278,285 ****
-   }
-   
-   
- - #ifdef CONFIG_USB_INVENTRA_DMA
- - 
-   /* Peripheral tx (IN) using Mentor DMA works as follows:
-   	Only mode 0 is used for transfers <= wPktSize,
-   	mode 1 is used for larger transfers,
- --- 276,281 ----
- ***************
- *** 310,317 ****
-    * upleveling from irq-per-packet to irq-per-buffer.
-    */
-   
- - #endif
- - 
-   /*
-    * An endpoint is transmitting data. This can be called either from
-    * the IRQ routine or from ep.queue() to kickstart a request on an
- --- 306,311 ----
- ***************
- *** 372,379 ****
-   
-   		/* MUSB_TXCSR_P_ISO is still set correctly */
-   
- ! #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
- ! 		{
-   			if (request_size < musb_ep->packet_sz)
-   				musb_ep->dma->desired_mode = 0;
-   			else
- --- 366,372 ----
-   
-   		/* MUSB_TXCSR_P_ISO is still set correctly */
-   
- ! 		if (is_inventra_dma(musb) || is_ux500_dma(musb)) {
-   			if (request_size < musb_ep->packet_sz)
-   				musb_ep->dma->desired_mode = 0;
-   			else
- ***************
- *** 410,458 ****
-   
-   				musb_writew(epio, MUSB_TXCSR, csr);
-   			}
- ! 		}
- ! 
- ! #elif defined(CONFIG_USB_TI_CPPI_DMA)
- ! 		/* program endpoint CSR first, then setup DMA */
- ! 		csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
- ! 		csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
- ! 		       MUSB_TXCSR_MODE;
- ! 		musb_writew(epio, MUSB_TXCSR,
- ! 			(MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN)
- ! 				| csr);
-   
- ! 		/* ensure writebuffer is empty */
- ! 		csr = musb_readw(epio, MUSB_TXCSR);
-   
- ! 		/* NOTE host side sets DMAENAB later than this; both are
- ! 		 * OK since the transfer dma glue (between CPPI and Mentor
- ! 		 * fifos) just tells CPPI it could start.  Data only moves
- ! 		 * to the USB TX fifo when both fifos are ready.
- ! 		 */
-   
- ! 		/* "mode" is irrelevant here; handle terminating ZLPs like
- ! 		 * PIO does, since the hardware RNDIS mode seems unreliable
- ! 		 * except for the last-packet-is-already-short case.
- ! 		 */
- ! 		use_dma = use_dma && c->channel_program(
- ! 				musb_ep->dma, musb_ep->packet_sz,
- ! 				0,
- ! 				request->dma + request->actual,
- ! 				request_size);
- ! 		if (!use_dma) {
- ! 			c->channel_release(musb_ep->dma);
- ! 			musb_ep->dma = NULL;
- ! 			csr &= ~MUSB_TXCSR_DMAENAB;
- ! 			musb_writew(epio, MUSB_TXCSR, csr);
- ! 			/* invariant: prequest->buf is non-null */
-   		}
- - #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
- - 		use_dma = use_dma && c->channel_program(
- - 				musb_ep->dma, musb_ep->packet_sz,
- - 				request->zero,
- - 				request->dma + request->actual,
- - 				request_size);
- - #endif
-   	}
-   #endif
-   
- --- 403,460 ----
-   
-   				musb_writew(epio, MUSB_TXCSR, csr);
-   			}
- ! 		} else if (is_cppi_enabled(musb) || is_cppi41_enabled(musb)) {
- ! 			/* program endpoint CSR first, then setup DMA */
- ! 			csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
- ! 
- ! 			if (request_size == 0)
- ! 				csr &= ~(MUSB_TXCSR_DMAENAB |
- ! 					MUSB_TXCSR_DMAMODE);
- ! 			else
- ! 				csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
- ! 				       MUSB_TXCSR_MODE;
- ! 			musb_writew(epio, MUSB_TXCSR,
- ! 				(MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN)
- ! 					| csr);
-   
- ! 			/* ensure writebuffer is empty */
- ! 			csr = musb_readw(epio, MUSB_TXCSR);
-   
- ! 			/* NOTE host side sets DMAENAB later than this; both are
- ! 			 * OK since the transfer dma glue (between CPPI & Mentor
- ! 			 * fifos) just tells CPPI it could start.  Data only
- ! 			 * moves to the USB TX fifo when both fifos are ready.
- ! 			 */
-   
- ! 			/* "mode" is irrelevant here; handle terminating ZLPs
- ! 			 * like PIO does, since the hardware RNDIS mode seems
- ! 			 * unreliable except for the last-packet-is-already-
- ! 			 * short case.
- ! 			 */
- ! 			/* for zero byte transfer use pio mode */
- ! 			if (request_size == 0)
- ! 				use_dma = 0;
- ! 			else {
- ! 				use_dma = use_dma && c->channel_program(
- ! 					musb_ep->dma, musb_ep->packet_sz,
- ! 					0,
- ! 					request->dma + request->actual,
- ! 					request_size);
- ! 				if (!use_dma) {
- ! 					c->channel_release(musb_ep->dma);
- ! 					musb_ep->dma = NULL;
- ! 					csr &= ~MUSB_TXCSR_DMAENAB;
- ! 					musb_writew(epio, MUSB_TXCSR, csr);
- ! 				/* invariant: prequest->buf is non-null */
- ! 				}
- ! 			}
- ! 		} else if (tusb_dma_omap(musb)) {
- ! 			use_dma = use_dma && c->channel_program(
- ! 					musb_ep->dma, musb_ep->packet_sz,
- ! 					request->zero,
- ! 					request->dma + request->actual,
- ! 					request_size);
-   		}
-   	}
-   #endif
-   
- ***************
- *** 463,469 ****
-   		 */
-   		unmap_dma_buffer(req, musb);
-   
- ! 		musb_write_fifo(musb_ep->hw_ep, fifo_count,
-   				(u8 *) (request->buf + request->actual));
-   		request->actual += fifo_count;
-   		csr |= MUSB_TXCSR_TXPKTRDY;
- --- 465,471 ----
-   		 */
-   		unmap_dma_buffer(req, musb);
-   
- ! 		musb->ops->write_fifo(musb_ep->hw_ep, fifo_count,
-   				(u8 *) (request->buf + request->actual));
-   		request->actual += fifo_count;
-   		csr |= MUSB_TXCSR_TXPKTRDY;
- ***************
- *** 494,500 ****
-   	void __iomem		*epio = musb->endpoints[epnum].regs;
-   	struct dma_channel	*dma;
-   
- ! 	musb_ep_select(mbase, epnum);
-   	req = next_request(musb_ep);
-   	request = &req->request;
-   
- --- 496,502 ----
-   	void __iomem		*epio = musb->endpoints[epnum].regs;
-   	struct dma_channel	*dma;
-   
- ! 	musb_ep_select(musb, mbase, epnum);
-   	req = next_request(musb_ep);
-   	request = &req->request;
-   
- ***************
- *** 555,565 ****
-   		if ((request->zero && request->length
-   			&& (request->length % musb_ep->packet_sz == 0)
-   			&& (request->actual == request->length))
- ! #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
- ! 			|| (is_dma && (!dma->desired_mode ||
- ! 				(request->actual &
- ! 					(musb_ep->packet_sz - 1))))
- ! #endif
-   		) {
-   			/*
-   			 * On DMA completion, FIFO may not be
- --- 557,565 ----
-   		if ((request->zero && request->length
-   			&& (request->length % musb_ep->packet_sz == 0)
-   			&& (request->actual == request->length))
- ! 			|| ((is_inventra_dma(musb) || is_ux500_dma(musb)) &&
- ! 			is_dma && (!dma->desired_mode || (request->actual &
- ! 			(musb_ep->packet_sz - 1))))
-   		) {
-   			/*
-   			 * On DMA completion, FIFO may not be
- ***************
- *** 590,597 ****
-   
-   /* ------------------------------------------------------------ */
-   
- - #ifdef CONFIG_USB_INVENTRA_DMA
- - 
-   /* Peripheral rx (OUT) using Mentor DMA works as follows:
-   	- Only mode 0 is used.
-   
- --- 590,595 ----
- ***************
- *** 619,626 ****
-    * Non-Mentor DMA engines can of course work differently.
-    */
-   
- - #endif
- - 
-   /*
-    * Context: controller locked, IRQs blocked, endpoint selected
-    */
- --- 617,622 ----
- ***************
- *** 655,661 ****
-   		return;
-   	}
-   
- ! 	if (is_cppi_enabled() && is_buffer_mapped(req)) {
-   		struct dma_controller	*c = musb->dma_controller;
-   		struct dma_channel	*channel = musb_ep->dma;
-   
- --- 651,658 ----
-   		return;
-   	}
-   
- ! 	if ((is_cppi_enabled(musb) || is_cppi41_enabled(musb)) &&
- ! 					is_buffer_mapped(req)) {
-   		struct dma_controller	*c = musb->dma_controller;
-   		struct dma_channel	*channel = musb_ep->dma;
-   
- ***************
- *** 697,704 ****
-   			use_mode_1 = 0;
-   
-   		if (request->actual < request->length) {
- ! #ifdef CONFIG_USB_INVENTRA_DMA
- ! 			if (is_buffer_mapped(req)) {
-   				struct dma_controller	*c;
-   				struct dma_channel	*channel;
-   				int			use_dma = 0;
- --- 694,700 ----
-   			use_mode_1 = 0;
-   
-   		if (request->actual < request->length) {
- ! 			if (is_buffer_mapped(req) && is_inventra_dma(musb)) {
-   				struct dma_controller	*c;
-   				struct dma_channel	*channel;
-   				int			use_dma = 0;
- ***************
- *** 775,782 ****
-   				if (use_dma)
-   					return;
-   			}
- ! #elif defined(CONFIG_USB_UX500_DMA)
- ! 			if ((is_buffer_mapped(req)) &&
-   				(request->actual < request->length)) {
-   
-   				struct dma_controller *c;
- --- 771,777 ----
-   				if (use_dma)
-   					return;
-   			}
- ! 			if (is_ux500_dma(musb) && (is_buffer_mapped(req)) &&
-   				(request->actual < request->length)) {
-   
-   				struct dma_controller *c;
- ***************
- *** 822,828 ****
-   
-   					return;
-   			}
- - #endif	/* Mentor's DMA */
-   
-   			fifo_count = request->length - request->actual;
-   			dev_dbg(musb->controller, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
- --- 817,822 ----
- ***************
- *** 832,839 ****
-   
-   			fifo_count = min_t(unsigned, len, fifo_count);
-   
- ! #ifdef	CONFIG_USB_TUSB_OMAP_DMA
- ! 			if (tusb_dma_omap() && is_buffer_mapped(req)) {
-   				struct dma_controller *c = musb->dma_controller;
-   				struct dma_channel *channel = musb_ep->dma;
-   				u32 dma_addr = request->dma + request->actual;
- --- 826,832 ----
-   
-   			fifo_count = min_t(unsigned, len, fifo_count);
-   
- ! 			if (tusb_dma_omap(musb) && is_buffer_mapped(req)) {
-   				struct dma_controller *c = musb->dma_controller;
-   				struct dma_channel *channel = musb_ep->dma;
-   				u32 dma_addr = request->dma + request->actual;
- ***************
- *** 847,853 ****
-   				if (ret)
-   					return;
-   			}
- ! #endif
-   			/*
-   			 * Unmap the dma buffer back to cpu if dma channel
-   			 * programming fails. This buffer is mapped if the
- --- 840,846 ----
-   				if (ret)
-   					return;
-   			}
- ! 
-   			/*
-   			 * Unmap the dma buffer back to cpu if dma channel
-   			 * programming fails. This buffer is mapped if the
- ***************
- *** 864,870 ****
-   				musb_writew(epio, MUSB_RXCSR, csr);
-   			}
-   
- ! 			musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
-   					(request->buf + request->actual));
-   			request->actual += fifo_count;
-   
- --- 857,863 ----
-   				musb_writew(epio, MUSB_RXCSR, csr);
-   			}
-   
- ! 			musb->ops->read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
-   					(request->buf + request->actual));
-   			request->actual += fifo_count;
-   
- ***************
- *** 903,909 ****
-   	else
-   		musb_ep = &hw_ep->ep_out;
-   
- ! 	musb_ep_select(mbase, epnum);
-   
-   	req = next_request(musb_ep);
-   	if (!req)
- --- 896,902 ----
-   	else
-   		musb_ep = &hw_ep->ep_out;
-   
- ! 	musb_ep_select(musb, mbase, epnum);
-   
-   	req = next_request(musb_ep);
-   	if (!req)
- ***************
- *** 959,999 ****
-   			musb_readw(epio, MUSB_RXCSR),
-   			musb_ep->dma->actual_len, request);
-   
- ! #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
- ! 	defined(CONFIG_USB_UX500_DMA)
- ! 		/* Autoclear doesn't clear RxPktRdy for short packets */
- ! 		if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered)
- ! 				|| (dma->actual_len
- ! 					& (musb_ep->packet_sz - 1))) {
- ! 			/* ack the read! */
- ! 			csr &= ~MUSB_RXCSR_RXPKTRDY;
- ! 			musb_writew(epio, MUSB_RXCSR, csr);
- ! 		}
-   
- ! 		/* incomplete, and not short? wait for next IN packet */
- ! 		if ((request->actual < request->length)
- ! 				&& (musb_ep->dma->actual_len
- ! 					== musb_ep->packet_sz)) {
- ! 			/* In double buffer case, continue to unload fifo if
- !  			 * there is Rx packet in FIFO.
- !  			 **/
- ! 			csr = musb_readw(epio, MUSB_RXCSR);
- ! 			if ((csr & MUSB_RXCSR_RXPKTRDY) &&
- ! 				hw_ep->rx_double_buffered)
- ! 				goto exit;
- ! 			return;
-   		}
- - #endif
-   		musb_g_giveback(musb_ep, request, 0);
-   
-   		req = next_request(musb_ep);
-   		if (!req)
-   			return;
-   	}
- - #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
- - 	defined(CONFIG_USB_UX500_DMA)
- - exit:
- - #endif
-   	/* Analyze request */
-   	rxstate(musb, req);
-   }
- --- 952,988 ----
-   			musb_readw(epio, MUSB_RXCSR),
-   			musb_ep->dma->actual_len, request);
-   
- ! 		if (is_inventra_dma(musb) || tusb_dma_omap(musb)
- ! 				|| is_ux500_dma(musb)) {
- ! 			/* Autoclear doesn't clear RxPktRdy for short packets */
- ! 			if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered)
- ! 					|| (dma->actual_len
- ! 						& (musb_ep->packet_sz - 1))) {
- ! 				/* ack the read! */
- ! 				csr &= ~MUSB_RXCSR_RXPKTRDY;
- ! 				musb_writew(epio, MUSB_RXCSR, csr);
- ! 			}
-   
- ! 			/* incomplete, and not short? wait for next IN packet */
- ! 			if ((request->actual < request->length)
- ! 					&& (musb_ep->dma->actual_len
- ! 						== musb_ep->packet_sz)) {
- ! 				/* In double buffer case, continue to unload
- ! 				 * fifo if there is Rx packet in FIFO.
- ! 				 **/
- ! 				csr = musb_readw(epio, MUSB_RXCSR);
- ! 				if ((csr & MUSB_RXCSR_RXPKTRDY) &&
- ! 					hw_ep->rx_double_buffered)
- ! 					rxstate(musb, to_musb_request(request));
- ! 				return;
- ! 			}
-   		}
-   		musb_g_giveback(musb_ep, request, 0);
-   
-   		req = next_request(musb_ep);
-   		if (!req)
-   			return;
-   	}
-   	/* Analyze request */
-   	rxstate(musb, req);
-   }
- ***************
- *** 1031,1036 ****
- --- 1020,1026 ----
-   		goto fail;
-   	}
-   	musb_ep->type = usb_endpoint_type(desc);
- + 	hw_ep->xfer_type = musb_ep->type;
-   
-   	/* check direction and (later) maxpacket size against endpoint */
-   	if (usb_endpoint_num(desc) != epnum)
- ***************
- *** 1061,1067 ****
-   	/* enable the interrupts for the endpoint, set the endpoint
-   	 * packet size (or fail), set the mode, clear the fifo
-   	 */
- ! 	musb_ep_select(mbase, epnum);
-   	if (usb_endpoint_dir_in(desc)) {
-   		u16 int_txe = musb_readw(mbase, MUSB_INTRTXE);
-   
- --- 1051,1057 ----
-   	/* enable the interrupts for the endpoint, set the endpoint
-   	 * packet size (or fail), set the mode, clear the fifo
-   	 */
- ! 	musb_ep_select(musb, mbase, epnum);
-   	if (usb_endpoint_dir_in(desc)) {
-   		u16 int_txe = musb_readw(mbase, MUSB_INTRTXE);
-   
- ***************
- *** 1200,1206 ****
-   	epio = musb->endpoints[epnum].regs;
-   
-   	spin_lock_irqsave(&musb->lock, flags);
- ! 	musb_ep_select(musb->mregs, epnum);
-   
-   	/* zero the endpoint sizes */
-   	if (musb_ep->is_in) {
- --- 1190,1196 ----
-   	epio = musb->endpoints[epnum].regs;
-   
-   	spin_lock_irqsave(&musb->lock, flags);
- ! 	musb_ep_select(musb, musb->mregs, epnum);
-   
-   	/* zero the endpoint sizes */
-   	if (musb_ep->is_in) {
- ***************
- *** 1279,1285 ****
-   		req->tx ? "TX/IN" : "RX/OUT",
-   		&req->request, req->request.length, req->epnum);
-   
- ! 	musb_ep_select(musb->mregs, req->epnum);
-   	if (req->tx)
-   		txstate(musb, req);
-   	else
- --- 1269,1275 ----
-   		req->tx ? "TX/IN" : "RX/OUT",
-   		&req->request, req->request.length, req->epnum);
-   
- ! 	musb_ep_select(musb, musb->mregs, req->epnum);
-   	if (req->tx)
-   		txstate(musb, req);
-   	else
- ***************
- *** 1373,1379 ****
-   	else if (is_dma_capable() && musb_ep->dma) {
-   		struct dma_controller	*c = musb->dma_controller;
-   
- ! 		musb_ep_select(musb->mregs, musb_ep->current_epnum);
-   		if (c->channel_abort)
-   			status = c->channel_abort(musb_ep->dma);
-   		else
- --- 1363,1369 ----
-   	else if (is_dma_capable() && musb_ep->dma) {
-   		struct dma_controller	*c = musb->dma_controller;
-   
- ! 		musb_ep_select(musb, musb->mregs, musb_ep->current_epnum);
-   		if (c->channel_abort)
-   			status = c->channel_abort(musb_ep->dma);
-   		else
- ***************
- *** 1421,1427 ****
-   		goto done;
-   	}
-   
- ! 	musb_ep_select(mbase, epnum);
-   
-   	request = next_request(musb_ep);
-   	if (value) {
- --- 1411,1417 ----
-   		goto done;
-   	}
-   
- ! 	musb_ep_select(musb, mbase, epnum);
-   
-   	request = next_request(musb_ep);
-   	if (value) {
- ***************
- *** 1509,1515 ****
-   
-   		spin_lock_irqsave(&musb->lock, flags);
-   
- ! 		musb_ep_select(mbase, epnum);
-   		/* FIXME return zero unless RXPKTRDY is set */
-   		retval = musb_readw(epio, MUSB_RXCOUNT);
-   
- --- 1499,1505 ----
-   
-   		spin_lock_irqsave(&musb->lock, flags);
-   
- ! 		musb_ep_select(musb, mbase, epnum);
-   		/* FIXME return zero unless RXPKTRDY is set */
-   		retval = musb_readw(epio, MUSB_RXCOUNT);
-   
- ***************
- *** 1531,1537 ****
-   	mbase = musb->mregs;
-   
-   	spin_lock_irqsave(&musb->lock, flags);
- ! 	musb_ep_select(mbase, (u8) epnum);
-   
-   	/* disable interrupts */
-   	int_txe = musb_readw(mbase, MUSB_INTRTXE);
- --- 1521,1527 ----
-   	mbase = musb->mregs;
-   
-   	spin_lock_irqsave(&musb->lock, flags);
- ! 	musb_ep_select(musb, mbase, (u8) epnum);
-   
-   	/* disable interrupts */
-   	int_txe = musb_readw(mbase, MUSB_INTRTXE);
- ***************
- *** 1764,1770 ****
-   }
-   
-   
- ! static void __init
-   init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
-   {
-   	struct musb_hw_ep	*hw_ep = musb->endpoints + epnum;
- --- 1754,1760 ----
-   }
-   
-   
- ! static void __devinit
-   init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
-   {
-   	struct musb_hw_ep	*hw_ep = musb->endpoints + epnum;
- ***************
- *** 1801,1807 ****
-    * Initialize the endpoints exposed to peripheral drivers, with backlinks
-    * to the rest of the driver state.
-    */
- ! static inline void __init musb_g_init_endpoints(struct musb *musb)
-   {
-   	u8			epnum;
-   	struct musb_hw_ep	*hw_ep;
- --- 1791,1797 ----
-    * Initialize the endpoints exposed to peripheral drivers, with backlinks
-    * to the rest of the driver state.
-    */
- ! static inline void __devinit musb_g_init_endpoints(struct musb *musb)
-   {
-   	u8			epnum;
-   	struct musb_hw_ep	*hw_ep;
- ***************
- *** 1834,1840 ****
-   /* called once during driver setup to initialize and link into
-    * the driver model; memory is zeroed.
-    */
- ! int __init musb_gadget_setup(struct musb *musb)
-   {
-   	int status;
-   
- --- 1824,1830 ----
-   /* called once during driver setup to initialize and link into
-    * the driver model; memory is zeroed.
-    */
- ! int __devinit musb_gadget_setup(struct musb *musb)
-   {
-   	int status;
-   
- ***************
- *** 1844,1850 ****
-   	 */
-   
-   	musb->g.ops = &musb_gadget_operations;
- ! 	musb->g.is_dualspeed = 1;
-   	musb->g.speed = USB_SPEED_UNKNOWN;
-   
-   	/* this "gadget" abstracts/virtualizes the controller */
- --- 1834,1840 ----
-   	 */
-   
-   	musb->g.ops = &musb_gadget_operations;
- ! 	musb->g.max_speed = USB_SPEED_HIGH;
-   	musb->g.speed = USB_SPEED_UNKNOWN;
-   
-   	/* this "gadget" abstracts/virtualizes the controller */
- ***************
- *** 1903,1909 ****
-   	unsigned long		flags;
-   	int			retval = -EINVAL;
-   
- ! 	if (driver->speed < USB_SPEED_HIGH)
-   		goto err0;
-   
-   	pm_runtime_get_sync(musb->controller);
- --- 1893,1899 ----
-   	unsigned long		flags;
-   	int			retval = -EINVAL;
-   
- ! 	if (driver->max_speed < USB_SPEED_HIGH)
-   		goto err0;
-   
-   	pm_runtime_get_sync(musb->controller);
- ***************
- *** 1941,1946 ****
- --- 1931,1937 ----
-   		 * ensures HdrcStart is indirectly called.
-   		 */
-   		retval = usb_add_hcd(musb_to_hcd(musb), -1, 0);
- + 		device_set_wakeup_enable(musb->controller, 0);
-   		if (retval < 0) {
-   			dev_dbg(musb->controller, "add_hcd failed, %d\n", retval);
-   			goto err2;
- ***************
- *** 1989,1995 ****
-   		for (i = 0, hw_ep = musb->endpoints;
-   				i < musb->nr_endpoints;
-   				i++, hw_ep++) {
- ! 			musb_ep_select(musb->mregs, i);
-   			if (hw_ep->is_shared_fifo /* || !epnum */) {
-   				nuke(&hw_ep->ep_in, -ESHUTDOWN);
-   			} else {
- --- 1980,1986 ----
-   		for (i = 0, hw_ep = musb->endpoints;
-   				i < musb->nr_endpoints;
-   				i++, hw_ep++) {
- ! 			musb_ep_select(musb, musb->mregs, i);
-   			if (hw_ep->is_shared_fifo /* || !epnum */) {
-   				nuke(&hw_ep->ep_in, -ESHUTDOWN);
-   			} else {
- ***************
- *** 2024,2030 ****
-   
-   	spin_lock_irqsave(&musb->lock, flags);
-   
- ! 	musb_hnp_stop(musb);
-   
-   	(void) musb_gadget_vbus_draw(&musb->g, 0);
-   
- --- 2015,2022 ----
-   
-   	spin_lock_irqsave(&musb->lock, flags);
-   
- ! 	if (is_otg_enabled(musb))
- ! 		musb_hnp_stop(musb);
-   
-   	(void) musb_gadget_vbus_draw(&musb->g, 0);
-   
- ***************
- *** 2049,2054 ****
- --- 2041,2047 ----
-   	if (!is_otg_enabled(musb))
-   		musb_stop(musb);
-   
- + 	musb->gadget_driver = NULL;
-   	pm_runtime_put(musb->controller);
-   
-   	return 0;
- ***************
- *** 2138,2154 ****
-   
-   	switch (musb->xceiv->state) {
-   	default:
- ! 		dev_dbg(musb->controller, "Unhandled disconnect %s, setting a_idle\n",
- ! 			otg_state_string(musb->xceiv->state));
- ! 		musb->xceiv->state = OTG_STATE_A_IDLE;
- ! 		MUSB_HST_MODE(musb);
- ! 		break;
-   	case OTG_STATE_A_PERIPHERAL:
- ! 		musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
- ! 		MUSB_HST_MODE(musb);
-   		break;
-   	case OTG_STATE_B_WAIT_ACON:
-   	case OTG_STATE_B_HOST:
-   	case OTG_STATE_B_PERIPHERAL:
-   	case OTG_STATE_B_IDLE:
-   		musb->xceiv->state = OTG_STATE_B_IDLE;
- --- 2131,2150 ----
-   
-   	switch (musb->xceiv->state) {
-   	default:
- ! 		if (is_otg_enabled(musb)) {
- ! 			dev_dbg(musb->controller, "Unhandled disconnect %s, setting a_idle\n",
- ! 				otg_state_string(musb->xceiv->state));
- ! 			musb->xceiv->state = OTG_STATE_A_IDLE;
- ! 			break;
- ! 		}
-   	case OTG_STATE_A_PERIPHERAL:
- ! 		if (is_otg_enabled(musb))
- ! 			musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
-   		break;
-   	case OTG_STATE_B_WAIT_ACON:
-   	case OTG_STATE_B_HOST:
- + 		if (!is_otg_enabled(musb))
- + 			break;
-   	case OTG_STATE_B_PERIPHERAL:
-   	case OTG_STATE_B_IDLE:
-   		musb->xceiv->state = OTG_STATE_B_IDLE;
- diff -crN linux-3.2.1_o/drivers/usb/musb/musb_gadget_ep0.c linux-3.2.1/drivers/usb/musb/musb_gadget_ep0.c
- *** linux-3.2.1_o/drivers/usb/musb/musb_gadget_ep0.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/musb/musb_gadget_ep0.c	2014-05-15 13:25:15.090635849 +0900
- ***************
- *** 37,43 ****
-   #include <linux/list.h>
-   #include <linux/timer.h>
-   #include <linux/spinlock.h>
- - #include <linux/init.h>
-   #include <linux/device.h>
-   #include <linux/interrupt.h>
-   
- --- 37,42 ----
- ***************
- *** 88,94 ****
-   	case USB_RECIP_DEVICE:
-   		result[0] = musb->is_self_powered << USB_DEVICE_SELF_POWERED;
-   		result[0] |= musb->may_wakeup << USB_DEVICE_REMOTE_WAKEUP;
- ! 		if (musb->g.is_otg) {
-   			result[0] |= musb->g.b_hnp_enable
-   				<< USB_DEVICE_B_HNP_ENABLE;
-   			result[0] |= musb->g.a_alt_hnp_support
- --- 87,93 ----
-   	case USB_RECIP_DEVICE:
-   		result[0] = musb->is_self_powered << USB_DEVICE_SELF_POWERED;
-   		result[0] |= musb->may_wakeup << USB_DEVICE_REMOTE_WAKEUP;
- ! 		if (is_otg_enabled(musb) && musb->g.is_otg) {
-   			result[0] |= musb->g.b_hnp_enable
-   				<< USB_DEVICE_B_HNP_ENABLE;
-   			result[0] |= musb->g.a_alt_hnp_support
- ***************
- *** 128,141 ****
-   			break;
-   		}
-   
- ! 		musb_ep_select(mbase, epnum);
-   		if (is_in)
-   			tmp = musb_readw(regs, MUSB_TXCSR)
-   						& MUSB_TXCSR_P_SENDSTALL;
-   		else
-   			tmp = musb_readw(regs, MUSB_RXCSR)
-   						& MUSB_RXCSR_P_SENDSTALL;
- ! 		musb_ep_select(mbase, 0);
-   
-   		result[0] = tmp ? 1 : 0;
-   		} break;
- --- 127,140 ----
-   			break;
-   		}
-   
- ! 		musb_ep_select(musb, mbase, epnum);
-   		if (is_in)
-   			tmp = musb_readw(regs, MUSB_TXCSR)
-   						& MUSB_TXCSR_P_SENDSTALL;
-   		else
-   			tmp = musb_readw(regs, MUSB_RXCSR)
-   						& MUSB_RXCSR_P_SENDSTALL;
- ! 		musb_ep_select(musb, mbase, 0);
-   
-   		result[0] = tmp ? 1 : 0;
-   		} break;
- ***************
- *** 152,158 ****
-   
-   		if (len > 2)
-   			len = 2;
- ! 		musb_write_fifo(&musb->endpoints[0], len, result);
-   	}
-   
-   	return handled;
- --- 151,157 ----
-   
-   		if (len > 2)
-   			len = 2;
- ! 		musb->ops->write_fifo(&musb->endpoints[0], len, result);
-   	}
-   
-   	return handled;
- ***************
- *** 283,289 ****
-   				if (musb_ep->wedged)
-   					break;
-   
- ! 				musb_ep_select(mbase, epnum);
-   				if (is_in) {
-   					csr  = musb_readw(regs, MUSB_TXCSR);
-   					csr |= MUSB_TXCSR_CLRDATATOG |
- --- 282,288 ----
-   				if (musb_ep->wedged)
-   					break;
-   
- ! 				musb_ep_select(musb, mbase, epnum);
-   				if (is_in) {
-   					csr  = musb_readw(regs, MUSB_TXCSR);
-   					csr |= MUSB_TXCSR_CLRDATATOG |
- ***************
- *** 309,315 ****
-   				}
-   
-   				/* select ep0 again */
- ! 				musb_ep_select(mbase, 0);
-   				} break;
-   			default:
-   				/* class, vendor, etc ... delegate */
- --- 308,314 ----
-   				}
-   
-   				/* select ep0 again */
- ! 				musb_ep_select(musb, mbase, 0);
-   				} break;
-   			default:
-   				/* class, vendor, etc ... delegate */
- ***************
- *** 391,410 ****
-   						musb->test_mode = true;
-   					break;
-   				case USB_DEVICE_B_HNP_ENABLE:
- ! 					if (!musb->g.is_otg)
- ! 						goto stall;
- ! 					musb->g.b_hnp_enable = 1;
- ! 					musb_try_b_hnp_enable(musb);
-   					break;
-   				case USB_DEVICE_A_HNP_SUPPORT:
- ! 					if (!musb->g.is_otg)
- ! 						goto stall;
- ! 					musb->g.a_hnp_support = 1;
-   					break;
-   				case USB_DEVICE_A_ALT_HNP_SUPPORT:
- ! 					if (!musb->g.is_otg)
- ! 						goto stall;
- ! 					musb->g.a_alt_hnp_support = 1;
-   					break;
-   				case USB_DEVICE_DEBUG_MODE:
-   					handled = 0;
- --- 390,415 ----
-   						musb->test_mode = true;
-   					break;
-   				case USB_DEVICE_B_HNP_ENABLE:
- ! 					if (is_otg_enabled(musb)) {
- ! 						if (!musb->g.is_otg)
- ! 							goto stall;
- ! 						musb->g.b_hnp_enable = 1;
- ! 						musb_try_b_hnp_enable(musb);
- ! 					}
-   					break;
-   				case USB_DEVICE_A_HNP_SUPPORT:
- ! 					if (is_otg_enabled(musb)) {
- ! 						if (!musb->g.is_otg)
- ! 							goto stall;
- ! 						musb->g.a_hnp_support = 1;
- ! 					}
-   					break;
-   				case USB_DEVICE_A_ALT_HNP_SUPPORT:
- ! 					if (is_otg_enabled(musb)) {
- ! 						if (!musb->g.is_otg)
- ! 							goto stall;
- ! 						musb->g.a_alt_hnp_support = 1;
- ! 					}
-   					break;
-   				case USB_DEVICE_DEBUG_MODE:
-   					handled = 0;
- ***************
- *** 442,448 ****
-   				if (!musb_ep->desc)
-   					break;
-   
- ! 				musb_ep_select(mbase, epnum);
-   				if (is_in) {
-   					csr = musb_readw(regs, MUSB_TXCSR);
-   					if (csr & MUSB_TXCSR_FIFONOTEMPTY)
- --- 447,453 ----
-   				if (!musb_ep->desc)
-   					break;
-   
- ! 				musb_ep_select(musb, mbase, epnum);
-   				if (is_in) {
-   					csr = musb_readw(regs, MUSB_TXCSR);
-   					if (csr & MUSB_TXCSR_FIFONOTEMPTY)
- ***************
- *** 461,467 ****
-   				}
-   
-   				/* select ep0 again */
- ! 				musb_ep_select(mbase, 0);
-   				handled = 1;
-   				} break;
-   
- --- 466,472 ----
-   				}
-   
-   				/* select ep0 again */
- ! 				musb_ep_select(musb, mbase, 0);
-   				handled = 1;
-   				} break;
-   
- ***************
- *** 506,513 ****
-   			req->status = -EOVERFLOW;
-   			count = len;
-   		}
- ! 		musb_read_fifo(&musb->endpoints[0], count, buf);
- ! 		req->actual += count;
-   		csr = MUSB_CSR0_P_SVDRXPKTRDY;
-   		if (count < 64 || req->actual == req->length) {
-   			musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
- --- 511,520 ----
-   			req->status = -EOVERFLOW;
-   			count = len;
-   		}
- ! 		if (count > 0) {
- ! 			musb->ops->read_fifo(&musb->endpoints[0], count, buf);
- ! 			req->actual += count;
- ! 		}
-   		csr = MUSB_CSR0_P_SVDRXPKTRDY;
-   		if (count < 64 || req->actual == req->length) {
-   			musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
- ***************
- *** 528,534 ****
-   			return;
-   		musb->ackpend = 0;
-   	}
- ! 	musb_ep_select(musb->mregs, 0);
-   	musb_writew(regs, MUSB_CSR0, csr);
-   }
-   
- --- 535,541 ----
-   			return;
-   		musb->ackpend = 0;
-   	}
- ! 	musb_ep_select(musb, musb->mregs, 0);
-   	musb_writew(regs, MUSB_CSR0, csr);
-   }
-   
- ***************
- *** 559,565 ****
-   	fifo_src = (u8 *) request->buf + request->actual;
-   	fifo_count = min((unsigned) MUSB_EP0_FIFOSIZE,
-   		request->length - request->actual);
- ! 	musb_write_fifo(&musb->endpoints[0], fifo_count, fifo_src);
-   	request->actual += fifo_count;
-   
-   	/* update the flags */
- --- 566,572 ----
-   	fifo_src = (u8 *) request->buf + request->actual;
-   	fifo_count = min((unsigned) MUSB_EP0_FIFOSIZE,
-   		request->length - request->actual);
- ! 	musb->ops->write_fifo(&musb->endpoints[0], fifo_count, fifo_src);
-   	request->actual += fifo_count;
-   
-   	/* update the flags */
- ***************
- *** 585,591 ****
-   	}
-   
-   	/* send it out, triggering a "txpktrdy cleared" irq */
- ! 	musb_ep_select(musb->mregs, 0);
-   	musb_writew(regs, MUSB_CSR0, csr);
-   }
-   
- --- 592,598 ----
-   	}
-   
-   	/* send it out, triggering a "txpktrdy cleared" irq */
- ! 	musb_ep_select(musb, musb->mregs, 0);
-   	musb_writew(regs, MUSB_CSR0, csr);
-   }
-   
- ***************
- *** 601,607 ****
-   	struct musb_request	*r;
-   	void __iomem		*regs = musb->control_ep->regs;
-   
- ! 	musb_read_fifo(&musb->endpoints[0], sizeof *req, (u8 *)req);
-   
-   	/* NOTE:  earlier 2.6 versions changed setup packets to host
-   	 * order, but now USB packets always stay in USB byte order.
- --- 608,614 ----
-   	struct musb_request	*r;
-   	void __iomem		*regs = musb->control_ep->regs;
-   
- ! 	musb->ops->read_fifo(&musb->endpoints[0], sizeof *req, (u8 *)req);
-   
-   	/* NOTE:  earlier 2.6 versions changed setup packets to host
-   	 * order, but now USB packets always stay in USB byte order.
- ***************
- *** 670,676 ****
-   	void __iomem	*regs = musb->endpoints[0].regs;
-   	irqreturn_t	retval = IRQ_NONE;
-   
- ! 	musb_ep_select(mbase, 0);	/* select ep0 */
-   	csr = musb_readw(regs, MUSB_CSR0);
-   	len = musb_readb(regs, MUSB_COUNT0);
-   
- --- 677,683 ----
-   	void __iomem	*regs = musb->endpoints[0].regs;
-   	irqreturn_t	retval = IRQ_NONE;
-   
- ! 	musb_ep_select(musb, mbase, 0);	/* select ep0 */
-   	csr = musb_readw(regs, MUSB_CSR0);
-   	len = musb_readb(regs, MUSB_COUNT0);
-   
- ***************
- *** 760,765 ****
- --- 767,775 ----
-   
-   			musb_writeb(mbase, MUSB_TESTMODE,
-   					musb->test_mode_nr);
- + 			if (MUSB_TEST_PACKET == musb->test_mode_nr)
- + 				musb_writew(musb->endpoints[0].regs,
- + 					MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
-   		}
-   		/* FALLTHROUGH */
-   
- ***************
- *** 880,886 ****
-   
-   			handled = forward_to_driver(musb, &setup);
-   			if (handled < 0) {
- ! 				musb_ep_select(mbase, 0);
-   stall:
-   				dev_dbg(musb->controller, "stall (%d)\n", handled);
-   				musb->ackpend |= MUSB_CSR0_P_SENDSTALL;
- --- 890,896 ----
-   
-   			handled = forward_to_driver(musb, &setup);
-   			if (handled < 0) {
- ! 				musb_ep_select(musb, mbase, 0);
-   stall:
-   				dev_dbg(musb->controller, "stall (%d)\n", handled);
-   				musb->ackpend |= MUSB_CSR0_P_SENDSTALL;
- ***************
- *** 975,981 ****
-   			ep->name, ep->is_in ? "IN/TX" : "OUT/RX",
-   			req->request.length);
-   
- ! 	musb_ep_select(musb->mregs, 0);
-   
-   	/* sequence #1, IN ... start writing the data */
-   	if (musb->ep0_state == MUSB_EP0_STAGE_TX)
- --- 985,991 ----
-   			ep->name, ep->is_in ? "IN/TX" : "OUT/RX",
-   			req->request.length);
-   
- ! 	musb_ep_select(musb, musb->mregs, 0);
-   
-   	/* sequence #1, IN ... start writing the data */
-   	if (musb->ep0_state == MUSB_EP0_STAGE_TX)
- ***************
- *** 1038,1044 ****
-   		goto cleanup;
-   	}
-   
- ! 	musb_ep_select(base, 0);
-   	csr = musb->ackpend;
-   
-   	switch (musb->ep0_state) {
- --- 1048,1054 ----
-   		goto cleanup;
-   	}
-   
- ! 	musb_ep_select(musb, base, 0);
-   	csr = musb->ackpend;
-   
-   	switch (musb->ep0_state) {
- diff -crN linux-3.2.1_o/drivers/usb/musb/musb_host.c linux-3.2.1/drivers/usb/musb/musb_host.c
- *** linux-3.2.1_o/drivers/usb/musb/musb_host.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/musb/musb_host.c	2014-05-15 13:25:15.094568420 +0900
- ***************
- *** 101,106 ****
- --- 101,130 ----
-   			struct urb *urb, int is_out,
-   			u8 *buf, u32 offset, u32 len);
-   
- + void push_queue(struct musb *musb, struct urb *urb)
- + {
- + 	spin_lock(&musb->gb_lock);
- + 	list_add_tail(&urb->giveback_list, &musb->gb_list);
- + 	spin_unlock(&musb->gb_lock);
- + }
- + 
- + struct urb *pop_queue(struct musb *musb)
- + {
- + 	struct urb *urb;
- + 	unsigned long flags;
- + 
- + 	spin_lock_irqsave(&musb->gb_lock, flags);
- + 	if (list_empty(&musb->gb_list)) {
- + 		spin_unlock_irqrestore(&musb->gb_lock, flags);
- + 		return NULL;
- + 	}
- + 	urb = list_entry(musb->gb_list.next, struct urb, giveback_list);
- + 	list_del(&urb->giveback_list);
- + 	spin_unlock_irqrestore(&musb->gb_lock, flags);
- + 
- + 	return urb;
- + }
- + 
-   /*
-    * Clear TX fifo. Needed to avoid BABBLE errors.
-    */
- ***************
- *** 109,130 ****
-   	struct musb	*musb = ep->musb;
-   	void __iomem	*epio = ep->regs;
-   	u16		csr;
- - 	u16		lastcsr = 0;
-   	int		retries = 1000;
-   
-   	csr = musb_readw(epio, MUSB_TXCSR);
- ! 	while (csr & MUSB_TXCSR_FIFONOTEMPTY) {
- ! 		if (csr != lastcsr)
- ! 			dev_dbg(musb->controller, "Host TX FIFONOTEMPTY csr: %02x\n", csr);
- ! 		lastcsr = csr;
-   		csr |= MUSB_TXCSR_FLUSHFIFO;
-   		musb_writew(epio, MUSB_TXCSR, csr);
-   		csr = musb_readw(epio, MUSB_TXCSR);
- ! 		if (WARN(retries-- < 1,
-   				"Could not flush host TX%d fifo: csr: %04x\n",
- ! 				ep->epnum, csr))
-   			return;
- ! 		mdelay(1);
-   	}
-   }
-   
- --- 133,158 ----
-   	struct musb	*musb = ep->musb;
-   	void __iomem	*epio = ep->regs;
-   	u16		csr;
-   	int		retries = 1000;
-   
-   	csr = musb_readw(epio, MUSB_TXCSR);
- ! 	while (csr & MUSB_TXCSR_TXPKTRDY) {
- ! 		if (!(csr & MUSB_TXCSR_FIFONOTEMPTY))
- ! 			return;
- ! 		else
- ! 			dev_dbg(musb->controller,
- ! 				"Host TX FIFONOTEMPTY csr: %02x\n", csr);
- ! 
-   		csr |= MUSB_TXCSR_FLUSHFIFO;
-   		musb_writew(epio, MUSB_TXCSR, csr);
-   		csr = musb_readw(epio, MUSB_TXCSR);
- ! 
- ! 		if (retries-- < 1) {
- ! 			dev_dbg(musb->controller,
-   				"Could not flush host TX%d fifo: csr: %04x\n",
- ! 					ep->epnum, csr);
-   			return;
- ! 		}
-   	}
-   }
-   
- ***************
- *** 178,184 ****
-   	/* NOTE: no locks here; caller should lock and select EP */
-   	txcsr = musb_readw(ep->regs, MUSB_TXCSR);
-   	txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS;
- ! 	if (is_cppi_enabled())
-   		txcsr |= MUSB_TXCSR_DMAMODE;
-   	musb_writew(ep->regs, MUSB_TXCSR, txcsr);
-   }
- --- 206,212 ----
-   	/* NOTE: no locks here; caller should lock and select EP */
-   	txcsr = musb_readw(ep->regs, MUSB_TXCSR);
-   	txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS;
- ! 	if (is_cppi_enabled(ep->musb) || is_cppi41_enabled(ep->musb))
-   		txcsr |= MUSB_TXCSR_DMAMODE;
-   	musb_writew(ep->regs, MUSB_TXCSR, txcsr);
-   }
- ***************
- *** 219,224 ****
- --- 247,253 ----
-   	/* initialize software qh state */
-   	qh->offset = 0;
-   	qh->segsize = 0;
- + 	hw_ep->xfer_type = qh->type;
-   
-   	/* gather right source of data */
-   	switch (qh->type) {
- ***************
- *** 292,306 ****
-   
-   		if (!hw_ep->tx_channel)
-   			musb_h_tx_start(hw_ep);
- ! 		else if (is_cppi_enabled() || tusb_dma_omap())
-   			musb_h_tx_dma_start(hw_ep);
-   	}
-   }
-   
-   /* Context: caller owns controller lock, IRQs are blocked */
-   static void musb_giveback(struct musb *musb, struct urb *urb, int status)
- - __releases(musb->lock)
- - __acquires(musb->lock)
-   {
-   	dev_dbg(musb->controller,
-   			"complete %p %pF (%d), dev%d ep%d%s, %d/%d\n",
- --- 321,334 ----
-   
-   		if (!hw_ep->tx_channel)
-   			musb_h_tx_start(hw_ep);
- ! 		else if (is_cppi_enabled(musb) || is_cppi41_enabled(musb)
- ! 				|| tusb_dma_omap(musb))
-   			musb_h_tx_dma_start(hw_ep);
-   	}
-   }
-   
-   /* Context: caller owns controller lock, IRQs are blocked */
-   static void musb_giveback(struct musb *musb, struct urb *urb, int status)
-   {
-   	dev_dbg(musb->controller,
-   			"complete %p %pF (%d), dev%d ep%d%s, %d/%d\n",
- ***************
- *** 311,341 ****
-   			urb->actual_length, urb->transfer_buffer_length
-   			);
-   
- - 	usb_hcd_unlink_urb_from_ep(musb_to_hcd(musb), urb);
- - 	spin_unlock(&musb->lock);
-   	usb_hcd_giveback_urb(musb_to_hcd(musb), urb, status);
- - 	spin_lock(&musb->lock);
-   }
-   
-   /* For bulk/interrupt endpoints only */
-   static inline void musb_save_toggle(struct musb_qh *qh, int is_in,
-   				    struct urb *urb)
-   {
-   	void __iomem		*epio = qh->hw_ep->regs;
-   	u16			csr;
-   
-   	/*
-   	 * FIXME: the current Mentor DMA code seems to have
-   	 * problems getting toggle correct.
-   	 */
-   
- ! 	if (is_in)
-   		csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE;
- ! 	else
-   		csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE;
-   
-   	usb_settoggle(urb->dev, qh->epnum, !is_in, csr ? 1 : 0);
-   }
-   
-   /*
-    * Advance this hardware endpoint's queue, completing the specified URB and
- --- 339,396 ----
-   			urb->actual_length, urb->transfer_buffer_length
-   			);
-   
-   	usb_hcd_giveback_urb(musb_to_hcd(musb), urb, status);
-   }
-   
-   /* For bulk/interrupt endpoints only */
-   static inline void musb_save_toggle(struct musb_qh *qh, int is_in,
-   				    struct urb *urb)
-   {
- + 	struct musb		*musb = qh->hw_ep->musb;
-   	void __iomem		*epio = qh->hw_ep->regs;
-   	u16			csr;
- + 	u8			curr_toggle;
-   
-   	/*
-   	 * FIXME: the current Mentor DMA code seems to have
-   	 * problems getting toggle correct.
-   	 */
-   
- ! 	if (is_in) {
-   		csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE;
- ! 		if (musb->datatog_fix) {
- ! 			curr_toggle = csr ? 1 : 0;
- ! 
- ! 			/* check if data toggle has gone out of sync */
- ! 			if (is_dma_capable() && qh->hw_ep->rx_channel &&
- ! 				curr_toggle == qh->hw_ep->prev_toggle) {
- ! 				dev_dbg(musb->controller,
- ! 				"Data toggle same as previous (=%d) on ep%d\n",
- ! 					curr_toggle, qh->hw_ep->epnum);
- ! 
- ! 				csr = musb_readw(epio, MUSB_RXCSR);
- ! 				csr |= MUSB_RXCSR_H_DATATOGGLE |
- ! 					MUSB_RXCSR_H_WR_DATATOGGLE;
- ! 				musb_writew(epio, MUSB_RXCSR, csr);
- ! 
- ! 				csr = 1;
- ! 			}
- ! 		}
- ! 	} else {
-   		csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE;
- + 	}
-   
-   	usb_settoggle(urb->dev, qh->epnum, !is_in, csr ? 1 : 0);
-   }
- + /* Used to complete urb giveback */
- + void musb_gb_work(struct work_struct *data)
- + {
- + 	struct musb *musb = container_of(data, struct musb, gb_work);
- + 	struct urb *urb;
- + 
- + 	while ((urb = pop_queue(musb)) != 0)
- + 		musb_giveback(musb, urb, 0);
- + }
-   
-   /*
-    * Advance this hardware endpoint's queue, completing the specified URB and
- ***************
- *** 366,385 ****
-   		break;
-   	}
-   
- ! 	qh->is_ready = 0;
- ! 	musb_giveback(musb, urb, status);
- ! 	qh->is_ready = ready;
-   
-   	/* reclaim resources (and bandwidth) ASAP; deschedule it, and
-   	 * invalidate qh as soon as list_empty(&hep->urb_list)
-   	 */
-   	if (list_empty(&qh->hep->urb_list)) {
-   		struct list_head	*head;
-   
- ! 		if (is_in)
-   			ep->rx_reinit = 1;
- ! 		else
-   			ep->tx_reinit = 1;
-   
-   		/* Clobber old pointers to this qh */
-   		musb_ep_set_qh(ep, is_in, NULL);
- --- 421,456 ----
-   		break;
-   	}
-   
- ! 	usb_hcd_unlink_urb_from_ep(musb_to_hcd(musb), urb);
-   
- + 	/* If URB completed with error then giveback first */
- + 	if (status != 0) {
- + 		qh->is_ready = 0;
- + 		spin_unlock(&musb->lock);
- + 		musb_giveback(musb, urb, status);
- + 		spin_lock(&musb->lock);
- + 		qh->is_ready = ready;
- + 	}
-   	/* reclaim resources (and bandwidth) ASAP; deschedule it, and
-   	 * invalidate qh as soon as list_empty(&hep->urb_list)
-   	 */
-   	if (list_empty(&qh->hep->urb_list)) {
-   		struct list_head	*head;
- + 		struct dma_controller	*dma = musb->dma_controller;
-   
- ! 		if (is_in) {
-   			ep->rx_reinit = 1;
- ! 			if (ep->rx_channel) {
- ! 				dma->channel_release(ep->rx_channel);
- ! 				ep->rx_channel = NULL;
- ! 			}
- ! 		} else {
-   			ep->tx_reinit = 1;
- + 			if (ep->tx_channel) {
- + 				dma->channel_release(ep->tx_channel);
- + 				ep->tx_channel = NULL;
- + 			}
- + 		}
-   
-   		/* Clobber old pointers to this qh */
-   		musb_ep_set_qh(ep, is_in, NULL);
- ***************
- *** 412,422 ****
-   		}
-   	}
-   
- ! 	if (qh != NULL && qh->is_ready) {
-   		dev_dbg(musb->controller, "... next ep%d %cX urb %p\n",
-   		    hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh));
-   		musb_start_urb(musb, is_in, qh);
-   	}
-   }
-   
-   static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr)
- --- 483,506 ----
-   		}
-   	}
-   
- ! 	/* we should not start next urb when current urb
- ! 	 * has failed, this is because stack will unlink/dequeue
- ! 	 * remaining urbs. Programming the next urb will endup in
- ! 	 * urb completion because of expected error (cause of current
- ! 	 * urb failure) interrupts and interfere with urb dequeue
- ! 	 * initiated by stack and cause a crash.
- ! 	 */
- ! 	if (status == 0 && qh != NULL && qh->is_ready) {
-   		dev_dbg(musb->controller, "... next ep%d %cX urb %p\n",
-   		    hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh));
-   		musb_start_urb(musb, is_in, qh);
-   	}
- + 
- + 	/* if URB is successfully completed then giveback in workqueue */
- + 	if (status == 0) {
- + 		push_queue(musb, urb);
- + 		queue_work(musb->gb_queue, &musb->gb_work);
- + 	}
-   }
-   
-   static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr)
- ***************
- *** 425,431 ****
-   	 * ignore dma (various models),
-   	 * leave toggle alone (may not have been saved yet)
-   	 */
- ! 	csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY;
-   	csr &= ~(MUSB_RXCSR_H_REQPKT
-   		| MUSB_RXCSR_H_AUTOREQ
-   		| MUSB_RXCSR_AUTOCLEAR);
- --- 509,516 ----
-   	 * ignore dma (various models),
-   	 * leave toggle alone (may not have been saved yet)
-   	 */
- ! 	if (csr & MUSB_RXCSR_RXPKTRDY)
- ! 		csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY;
-   	csr &= ~(MUSB_RXCSR_H_REQPKT
-   		| MUSB_RXCSR_H_AUTOREQ
-   		| MUSB_RXCSR_AUTOCLEAR);
- ***************
- *** 456,462 ****
-   	int			pipe = urb->pipe;
-   	void			*buffer = urb->transfer_buffer;
-   
- ! 	/* musb_ep_select(mbase, epnum); */
-   	rx_count = musb_readw(epio, MUSB_RXCOUNT);
-   	dev_dbg(musb->controller, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count,
-   			urb->transfer_buffer, qh->offset,
- --- 541,547 ----
-   	int			pipe = urb->pipe;
-   	void			*buffer = urb->transfer_buffer;
-   
- ! 	/* musb_ep_select(musb, mbase, epnum); */
-   	rx_count = musb_readw(epio, MUSB_RXCOUNT);
-   	dev_dbg(musb->controller, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count,
-   			urb->transfer_buffer, qh->offset,
- ***************
- *** 517,523 ****
-   			urb->status = -EREMOTEIO;
-   	}
-   
- ! 	musb_read_fifo(hw_ep, length, buf);
-   
-   	csr = musb_readw(epio, MUSB_RXCSR);
-   	csr |= MUSB_RXCSR_H_WZC_BITS;
- --- 602,608 ----
-   			urb->status = -EREMOTEIO;
-   	}
-   
- ! 	musb->ops->read_fifo(hw_ep, length, buf);
-   
-   	csr = musb_readw(epio, MUSB_RXCSR);
-   	csr |= MUSB_RXCSR_H_WZC_BITS;
- ***************
- *** 615,650 ****
-   	u16			csr;
-   	u8			mode;
-   
- ! #ifdef	CONFIG_USB_INVENTRA_DMA
- ! 	if (length > channel->max_len)
- ! 		length = channel->max_len;
-   
- ! 	csr = musb_readw(epio, MUSB_TXCSR);
- ! 	if (length > pkt_size) {
- ! 		mode = 1;
- ! 		csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB;
- ! 		/* autoset shouldn't be set in high bandwidth */
- ! 		if (qh->hb_mult == 1)
- ! 			csr |= MUSB_TXCSR_AUTOSET;
-   	} else {
- ! 		mode = 0;
- ! 		csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE);
- ! 		csr |= MUSB_TXCSR_DMAENAB; /* against programmer's guide */
- ! 	}
- ! 	channel->desired_mode = mode;
- ! 	musb_writew(epio, MUSB_TXCSR, csr);
- ! #else
- ! 	if (!is_cppi_enabled() && !tusb_dma_omap())
- ! 		return false;
-   
- ! 	channel->actual_len = 0;
-   
- ! 	/*
- ! 	 * TX uses "RNDIS" mode automatically but needs help
- ! 	 * to identify the zero-length-final-packet case.
- ! 	 */
- ! 	mode = (urb->transfer_flags & URB_ZERO_PACKET) ? 1 : 0;
- ! #endif
-   
-   	qh->segsize = length;
-   
- --- 700,737 ----
-   	u16			csr;
-   	u8			mode;
-   
- ! 	if (is_inventra_dma(hw_ep->musb)) {
- ! 		if (length > channel->max_len)
- ! 			length = channel->max_len;
-   
- ! 		csr = musb_readw(epio, MUSB_TXCSR);
- ! 		if (length > pkt_size) {
- ! 			mode = 1;
- ! 			csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB;
- ! 			/* autoset shouldn't be set in high bandwidth */
- ! 			if (qh->hb_mult == 1)
- ! 				csr |= MUSB_TXCSR_AUTOSET;
- ! 		} else {
- ! 			mode = 0;
- ! 			csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE);
- ! 			csr |= MUSB_TXCSR_DMAENAB; /* against progrmr's guide */
- ! 		}
- ! 		channel->desired_mode = mode;
- ! 		musb_writew(epio, MUSB_TXCSR, csr);
-   	} else {
- ! 		if (!is_cppi_enabled(hw_ep->musb)
- ! 			&& !is_cppi41_enabled(hw_ep->musb)
- ! 			&& !tusb_dma_omap(hw_ep->musb))
- ! 			return false;
-   
- ! 		channel->actual_len = 0;
-   
- ! 		/*
- ! 		 * TX uses "RNDIS" mode automatically but needs help
- ! 		 * to identify the zero-length-final-packet case.
- ! 		 */
- ! 		mode = (urb->transfer_flags & URB_ZERO_PACKET) ? 1 : 0;
- ! 	}
-   
-   	qh->segsize = length;
-   
- ***************
- *** 654,660 ****
-   	 */
-   	wmb();
-   
- ! 	if (!dma->channel_program(channel, pkt_size, mode,
-   			urb->transfer_dma + offset, length)) {
-   		dma->channel_release(channel);
-   		hw_ep->tx_channel = NULL;
- --- 741,748 ----
-   	 */
-   	wmb();
-   
- ! 	if (!dma->channel_program(channel, pkt_size |
- ! 			(qh->hb_mult << 11), mode,
-   			urb->transfer_dma + offset, length)) {
-   		dma->channel_release(channel);
-   		hw_ep->tx_channel = NULL;
- ***************
- *** 683,688 ****
- --- 771,778 ----
-   	void __iomem		*epio = hw_ep->regs;
-   	struct musb_qh		*qh = musb_ep_get_qh(hw_ep, !is_out);
-   	u16			packet_sz = qh->maxpacket;
- + 	u8			use_dma = 1;
- + 	u16			csr;
-   
-   	dev_dbg(musb->controller, "%s hw%d urb %p spd%d dev%d ep%d%s "
-   				"h_addr%02x h_port%02x bytes %d\n",
- ***************
- *** 692,702 ****
-   			qh->h_addr_reg, qh->h_port_reg,
-   			len);
-   
- ! 	musb_ep_select(mbase, epnum);
-   
-   	/* candidate for DMA? */
-   	dma_controller = musb->dma_controller;
- ! 	if (is_dma_capable() && epnum && dma_controller) {
-   		dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel;
-   		if (!dma_channel) {
-   			dma_channel = dma_controller->channel_alloc(
- --- 782,800 ----
-   			qh->h_addr_reg, qh->h_port_reg,
-   			len);
-   
- ! 	musb_ep_select(musb, mbase, epnum);
- ! 
- ! 	if (is_out && !len) {
- ! 		use_dma = 0;
- ! 		csr = musb_readw(epio, MUSB_TXCSR);
- ! 		csr &= ~MUSB_TXCSR_DMAENAB;
- ! 		musb_writew(epio, MUSB_TXCSR, csr);
- ! 		hw_ep->tx_channel = NULL;
- ! 	}
-   
-   	/* candidate for DMA? */
-   	dma_controller = musb->dma_controller;
- ! 	if (use_dma && is_dma_capable() && epnum && dma_controller) {
-   		dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel;
-   		if (!dma_channel) {
-   			dma_channel = dma_controller->channel_alloc(
- ***************
- *** 779,787 ****
-   					| ((hw_ep->max_packet_sz_tx /
-   						packet_sz) - 1) << 11);
-   			else
- ! 				musb_writew(epio, MUSB_TXMAXP,
- ! 						qh->maxpacket |
- ! 						((qh->hb_mult - 1) << 11));
-   			musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg);
-   		} else {
-   			musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg);
- --- 877,884 ----
-   					| ((hw_ep->max_packet_sz_tx /
-   						packet_sz) - 1) << 11);
-   			else
- ! 				musb_writew(epio, MUSB_TXMAXP, qh->maxpacket |
- ! 						(qh->hb_mult << 11));
-   			musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg);
-   		} else {
-   			musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg);
- ***************
- *** 803,809 ****
-   		if (load_count) {
-   			/* PIO to load FIFO */
-   			qh->segsize = load_count;
- ! 			musb_write_fifo(hw_ep, load_count, buf);
-   		}
-   
-   		/* re-enable interrupt */
- --- 900,906 ----
-   		if (load_count) {
-   			/* PIO to load FIFO */
-   			qh->segsize = load_count;
- ! 			musb->ops->write_fifo(hw_ep, load_count, buf);
-   		}
-   
-   		/* re-enable interrupt */
- ***************
- *** 828,836 ****
-   		} else {
-   			csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
-   
- ! 			if (csr & (MUSB_RXCSR_RXPKTRDY
- ! 					| MUSB_RXCSR_DMAENAB
- ! 					| MUSB_RXCSR_H_REQPKT))
-   				ERR("broken !rx_reinit, ep%d csr %04x\n",
-   						hw_ep->epnum, csr);
-   
- --- 925,933 ----
-   		} else {
-   			csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
-   
- ! 			if (csr & (MUSB_RXCSR_RXPKTRDY | (is_cppi_enabled(musb)
- ! 			|| is_cppi41_enabled(musb)) ? 0 : MUSB_RXCSR_DMAENAB
- ! 			| MUSB_RXCSR_H_REQPKT))
-   				ERR("broken !rx_reinit, ep%d csr %04x\n",
-   						hw_ep->epnum, csr);
-   
- ***************
- *** 840,846 ****
-   
-   		/* kick things off */
-   
- ! 		if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) {
-   			/* Candidate for DMA */
-   			dma_channel->actual_len = 0L;
-   			qh->segsize = len;
- --- 937,944 ----
-   
-   		/* kick things off */
-   
- ! 		if ((is_cppi_enabled(musb) || is_cppi41_enabled(musb) ||
- ! 			tusb_dma_omap(musb)) && dma_channel) {
-   			/* Candidate for DMA */
-   			dma_channel->actual_len = 0L;
-   			qh->segsize = len;
- ***************
- *** 849,860 ****
-   			musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
-   			csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
-   
-   			/*
-   			 * Unless caller treats short RX transfers as
-   			 * errors, we dare not queue multiple transfers.
-   			 */
-   			dma_ok = dma_controller->channel_program(dma_channel,
- ! 					packet_sz, !(urb->transfer_flags &
-   						     URB_SHORT_NOT_OK),
-   					urb->transfer_dma + offset,
-   					qh->segsize);
- --- 947,969 ----
-   			musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
-   			csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
-   
- + 			if (musb->datatog_fix) {
- + 				/*
- + 				 * Save the data toggle value which can be
- + 				 * compared later to see if data toggle goes
- + 				 * out of sync
- + 				 */
- + 				hw_ep->prev_toggle = (csr &
- + 					MUSB_RXCSR_H_DATATOGGLE) ? 1 : 0;
- + 			}
- + 
-   			/*
-   			 * Unless caller treats short RX transfers as
-   			 * errors, we dare not queue multiple transfers.
-   			 */
-   			dma_ok = dma_controller->channel_program(dma_channel,
- ! 					packet_sz | (qh->hb_mult << 11),
- ! 					 !(urb->transfer_flags &
-   						     URB_SHORT_NOT_OK),
-   					urb->transfer_dma + offset,
-   					qh->segsize);
- ***************
- *** 872,877 ****
- --- 981,1053 ----
-   	}
-   }
-   
- + /* Schedule next QH from musb->in_bulk/out_bulk and move the current qh to
- +  * the end; avoids starvation for other endpoints.
- +  */
- + static void musb_bulk_nak_timeout(struct musb *musb, struct musb_hw_ep *ep,
- + 	int is_in)
- + {
- + 	struct dma_channel	*dma;
- + 	struct urb		*urb;
- + 	void __iomem		*mbase = musb->mregs;
- + 	void __iomem		*epio = ep->regs;
- + 	struct musb_qh		*cur_qh, *next_qh;
- + 	u16			rx_csr, tx_csr;
- + 
- + 	musb_ep_select(musb, mbase, ep->epnum);
- + 	if (is_in) {
- + 		dma = is_dma_capable() ? ep->rx_channel : NULL;
- + 
- + 		/* clear nak timeout bit */
- + 		rx_csr = musb_readw(epio, MUSB_RXCSR);
- + 		rx_csr |= MUSB_RXCSR_H_WZC_BITS;
- + 		rx_csr &= ~MUSB_RXCSR_DATAERROR;
- + 		musb_writew(epio, MUSB_RXCSR, rx_csr);
- + 
- + 		cur_qh = first_qh(&musb->in_bulk);
- + 	} else {
- + 		dma = is_dma_capable() ? ep->tx_channel : NULL;
- + 
- + 		/* clear nak timeout bit */
- + 		tx_csr = musb_readw(epio, MUSB_TXCSR);
- + 		tx_csr |= MUSB_TXCSR_H_WZC_BITS;
- + 		tx_csr &= ~MUSB_TXCSR_H_NAKTIMEOUT;
- + 		musb_writew(epio, MUSB_TXCSR, tx_csr);
- + 
- + 		cur_qh = first_qh(&musb->out_bulk);
- + 	}
- + 	if (cur_qh) {
- + 		urb = next_urb(cur_qh);
- + 		if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
- + 			dma->status = MUSB_DMA_STATUS_CORE_ABORT;
- + 			musb->dma_controller->channel_abort(dma);
- + 			urb->actual_length += dma->actual_len;
- + 			dma->actual_len = 0L;
- + 		}
- + 		musb_save_toggle(cur_qh, is_in, urb);
- + 
- + 		if (is_in) {
- + 			/* move cur_qh to end of queue */
- + 			list_move_tail(&cur_qh->ring, &musb->in_bulk);
- + 
- + 			/* get the next qh from musb->in_bulk */
- + 			next_qh = first_qh(&musb->in_bulk);
- + 
- + 			/* set rx_reinit and schedule the next qh */
- + 			ep->rx_reinit = 1;
- + 		} else {
- + 			/* move cur_qh to end of queue */
- + 			list_move_tail(&cur_qh->ring, &musb->out_bulk);
- + 
- + 			/* get the next qh from musb->out_bulk */
- + 			next_qh = first_qh(&musb->out_bulk);
- + 
- + 			/* set tx_reinit and schedule the next qh */
- + 			ep->tx_reinit = 1;
- + 		}
- + 		musb_start_urb(musb, is_in, next_qh);
- + 	}
- + }
-   
-   /*
-    * Service the default endpoint (ep0) as host.
- ***************
- *** 894,900 ****
-   		if (fifo_count < len)
-   			urb->status = -EOVERFLOW;
-   
- ! 		musb_read_fifo(hw_ep, fifo_count, fifo_dest);
-   
-   		urb->actual_length += fifo_count;
-   		if (len < qh->maxpacket) {
- --- 1070,1076 ----
-   		if (fifo_count < len)
-   			urb->status = -EOVERFLOW;
-   
- ! 		musb->ops->read_fifo(hw_ep, fifo_count, fifo_dest);
-   
-   		urb->actual_length += fifo_count;
-   		if (len < qh->maxpacket) {
- ***************
- *** 933,939 ****
-   					fifo_count,
-   					(fifo_count == 1) ? "" : "s",
-   					fifo_dest);
- ! 			musb_write_fifo(hw_ep, fifo_count, fifo_dest);
-   
-   			urb->actual_length += fifo_count;
-   			more = true;
- --- 1109,1115 ----
-   					fifo_count,
-   					(fifo_count == 1) ? "" : "s",
-   					fifo_dest);
- ! 			musb->ops->write_fifo(hw_ep, fifo_count, fifo_dest);
-   
-   			urb->actual_length += fifo_count;
-   			more = true;
- ***************
- *** 968,974 ****
-   	/* ep0 only has one queue, "in" */
-   	urb = next_urb(qh);
-   
- ! 	musb_ep_select(mbase, 0);
-   	csr = musb_readw(epio, MUSB_CSR0);
-   	len = (csr & MUSB_CSR0_RXPKTRDY)
-   			? musb_readb(epio, MUSB_COUNT0)
- --- 1144,1150 ----
-   	/* ep0 only has one queue, "in" */
-   	urb = next_urb(qh);
-   
- ! 	musb_ep_select(musb, mbase, 0);
-   	csr = musb_readw(epio, MUSB_CSR0);
-   	len = (csr & MUSB_CSR0_RXPKTRDY)
-   			? musb_readb(epio, MUSB_COUNT0)
- ***************
- *** 1054,1059 ****
- --- 1230,1237 ----
-   			else
-   				csr = MUSB_CSR0_H_STATUSPKT
-   					| MUSB_CSR0_TXPKTRDY;
- + 			/* disable ping token in status phase */
- + 				csr |= MUSB_CSR0_H_DIS_PING;
-   
-   			/* flag status stage */
-   			musb->ep0_stage = MUSB_EP0_STATUS;
- ***************
- *** 1074,1081 ****
-   }
-   
-   
- - #ifdef CONFIG_USB_INVENTRA_DMA
- - 
-   /* Host side TX (OUT) using Mentor DMA works as follows:
-   	submit_urb ->
-   		- if queue was empty, Program Endpoint
- --- 1252,1257 ----
- ***************
- *** 1088,1095 ****
-   			short packets in mode 1.
-   */
-   
- - #endif
- - 
-   /* Service a Tx-Available or dma completion irq for the endpoint */
-   void musb_host_tx(struct musb *musb, u8 epnum)
-   {
- --- 1264,1269 ----
- ***************
- *** 1107,1113 ****
-   	struct dma_channel	*dma;
-   	bool			transfer_pending = false;
-   
- ! 	musb_ep_select(mbase, epnum);
-   	tx_csr = musb_readw(epio, MUSB_TXCSR);
-   
-   	/* with CPPI, DMA sometimes triggers "extra" irqs */
- --- 1281,1287 ----
-   	struct dma_channel	*dma;
-   	bool			transfer_pending = false;
-   
- ! 	musb_ep_select(musb, mbase, epnum);
-   	tx_csr = musb_readw(epio, MUSB_TXCSR);
-   
-   	/* with CPPI, DMA sometimes triggers "extra" irqs */
- ***************
- *** 1136,1155 ****
-   		status = -ETIMEDOUT;
-   
-   	} else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) {
- ! 		dev_dbg(musb->controller, "TX end=%d device not responding\n", epnum);
-   
- ! 		/* NOTE:  this code path would be a good place to PAUSE a
- ! 		 * transfer, if there's some other (nonperiodic) tx urb
- ! 		 * that could use this fifo.  (dma complicates it...)
- ! 		 * That's already done for bulk RX transfers.
- ! 		 *
- ! 		 * if (bulk && qh->ring.next != &musb->out_bulk), then
- ! 		 * we have a candidate... NAKing is *NOT* an error
- ! 		 */
- ! 		musb_ep_select(mbase, epnum);
- ! 		musb_writew(epio, MUSB_TXCSR,
- ! 				MUSB_TXCSR_H_WZC_BITS
- ! 				| MUSB_TXCSR_TXPKTRDY);
-   		return;
-   	}
-   
- --- 1310,1336 ----
-   		status = -ETIMEDOUT;
-   
-   	} else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) {
- ! 		if (USB_ENDPOINT_XFER_BULK == qh->type && qh->mux == 1
- ! 				&& !list_is_singular(&musb->out_bulk)) {
-   
- ! 			dev_dbg(musb->controller, "TX end %d NAK timeout\n", epnum);
- ! 			musb_bulk_nak_timeout(musb, hw_ep, 0);
- ! 		} else {
- ! 			dev_dbg(musb->controller, "TX end=%d device not responding\n", epnum);
- ! 
- ! 			/* NOTE: this code path would be a good place to PAUSE a
- ! 			 * transfer, if there's some other (nonperiodic) tx urb
- ! 			 * that could use this fifo.  (dma complicates it...)
- ! 			 * That's already done for bulk RX transfers.
- ! 			 *
- ! 			 * if (bulk && qh->ring.next != &musb->out_bulk), then
- ! 			 * we have a candidate... NAKing is *NOT* an error
- ! 			 */
- ! 			musb_ep_select(musb, mbase, epnum);
- ! 			musb_writew(epio, MUSB_TXCSR,
- ! 					MUSB_TXCSR_H_WZC_BITS
- ! 					| MUSB_TXCSR_TXPKTRDY);
- ! 		}
-   		return;
-   	}
-   
- ***************
- *** 1170,1176 ****
-   				| MUSB_TXCSR_H_NAKTIMEOUT
-   				);
-   
- ! 		musb_ep_select(mbase, epnum);
-   		musb_writew(epio, MUSB_TXCSR, tx_csr);
-   		/* REVISIT may need to clear FLUSHFIFO ... */
-   		musb_writew(epio, MUSB_TXCSR, tx_csr);
- --- 1351,1357 ----
-   				| MUSB_TXCSR_H_NAKTIMEOUT
-   				);
-   
- ! 		musb_ep_select(musb, mbase, epnum);
-   		musb_writew(epio, MUSB_TXCSR, tx_csr);
-   		/* REVISIT may need to clear FLUSHFIFO ... */
-   		musb_writew(epio, MUSB_TXCSR, tx_csr);
- ***************
- *** 1302,1308 ****
-   	} else if ((usb_pipeisoc(pipe) || transfer_pending) && dma) {
-   		if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb,
-   				offset, length)) {
- ! 			if (is_cppi_enabled() || tusb_dma_omap())
-   				musb_h_tx_dma_start(hw_ep);
-   			return;
-   		}
- --- 1483,1490 ----
-   	} else if ((usb_pipeisoc(pipe) || transfer_pending) && dma) {
-   		if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb,
-   				offset, length)) {
- ! 			if (is_cppi_enabled(musb) || is_cppi41_enabled(musb) ||
- ! 					tusb_dma_omap(musb))
-   				musb_h_tx_dma_start(hw_ep);
-   			return;
-   		}
- ***************
- *** 1322,1338 ****
-   		length = qh->maxpacket;
-   	/* Unmap the buffer so that CPU can use it */
-   	usb_hcd_unmap_urb_for_dma(musb_to_hcd(musb), urb);
- ! 	musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset);
-   	qh->segsize = length;
-   
- ! 	musb_ep_select(mbase, epnum);
-   	musb_writew(epio, MUSB_TXCSR,
-   			MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY);
-   }
-   
-   
- - #ifdef CONFIG_USB_INVENTRA_DMA
- - 
-   /* Host side RX (IN) using Mentor DMA works as follows:
-   	submit_urb ->
-   		- if queue was empty, ProgramEndpoint
- --- 1504,1518 ----
-   		length = qh->maxpacket;
-   	/* Unmap the buffer so that CPU can use it */
-   	usb_hcd_unmap_urb_for_dma(musb_to_hcd(musb), urb);
- ! 	musb->ops->write_fifo(hw_ep, length, urb->transfer_buffer + offset);
-   	qh->segsize = length;
-   
- ! 	musb_ep_select(musb, mbase, epnum);
-   	musb_writew(epio, MUSB_TXCSR,
-   			MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY);
-   }
-   
-   
-   /* Host side RX (IN) using Mentor DMA works as follows:
-   	submit_urb ->
-   		- if queue was empty, ProgramEndpoint
- ***************
- *** 1368,1419 ****
-    *	last packet of one URB's transfer.
-    */
-   
- - #endif
- - 
- - /* Schedule next QH from musb->in_bulk and move the current qh to
- -  * the end; avoids starvation for other endpoints.
- -  */
- - static void musb_bulk_rx_nak_timeout(struct musb *musb, struct musb_hw_ep *ep)
- - {
- - 	struct dma_channel	*dma;
- - 	struct urb		*urb;
- - 	void __iomem		*mbase = musb->mregs;
- - 	void __iomem		*epio = ep->regs;
- - 	struct musb_qh		*cur_qh, *next_qh;
- - 	u16			rx_csr;
- - 
- - 	musb_ep_select(mbase, ep->epnum);
- - 	dma = is_dma_capable() ? ep->rx_channel : NULL;
- - 
- - 	/* clear nak timeout bit */
- - 	rx_csr = musb_readw(epio, MUSB_RXCSR);
- - 	rx_csr |= MUSB_RXCSR_H_WZC_BITS;
- - 	rx_csr &= ~MUSB_RXCSR_DATAERROR;
- - 	musb_writew(epio, MUSB_RXCSR, rx_csr);
- - 
- - 	cur_qh = first_qh(&musb->in_bulk);
- - 	if (cur_qh) {
- - 		urb = next_urb(cur_qh);
- - 		if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
- - 			dma->status = MUSB_DMA_STATUS_CORE_ABORT;
- - 			musb->dma_controller->channel_abort(dma);
- - 			urb->actual_length += dma->actual_len;
- - 			dma->actual_len = 0L;
- - 		}
- - 		musb_save_toggle(cur_qh, 1, urb);
- - 
- - 		/* move cur_qh to end of queue */
- - 		list_move_tail(&cur_qh->ring, &musb->in_bulk);
- - 
- - 		/* get the next qh from musb->in_bulk */
- - 		next_qh = first_qh(&musb->in_bulk);
- - 
- - 		/* set rx_reinit and schedule the next qh */
- - 		ep->rx_reinit = 1;
- - 		musb_start_urb(musb, 1, next_qh);
- - 	}
- - }
- - 
-   /*
-    * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso,
-    * and high-bandwidth IN transfer cases.
- --- 1548,1553 ----
- ***************
- *** 1433,1439 ****
-   	u32			status;
-   	struct dma_channel	*dma;
-   
- ! 	musb_ep_select(mbase, epnum);
-   
-   	urb = next_urb(qh);
-   	dma = is_dma_capable() ? hw_ep->rx_channel : NULL;
- --- 1567,1573 ----
-   	u32			status;
-   	struct dma_channel	*dma;
-   
- ! 	musb_ep_select(musb, mbase, epnum);
-   
-   	urb = next_urb(qh);
-   	dma = is_dma_capable() ? hw_ep->rx_channel : NULL;
- ***************
- *** 1490,1499 ****
-   			if (usb_pipebulk(urb->pipe)
-   					&& qh->mux == 1
-   					&& !list_is_singular(&musb->in_bulk)) {
- ! 				musb_bulk_rx_nak_timeout(musb, hw_ep);
-   				return;
-   			}
- ! 			musb_ep_select(mbase, epnum);
-   			rx_csr |= MUSB_RXCSR_H_WZC_BITS;
-   			rx_csr &= ~MUSB_RXCSR_DATAERROR;
-   			musb_writew(epio, MUSB_RXCSR, rx_csr);
- --- 1624,1633 ----
-   			if (usb_pipebulk(urb->pipe)
-   					&& qh->mux == 1
-   					&& !list_is_singular(&musb->in_bulk)) {
- ! 				musb_bulk_nak_timeout(musb, hw_ep, 1);
-   				return;
-   			}
- ! 			musb_ep_select(musb, mbase, epnum);
-   			rx_csr |= MUSB_RXCSR_H_WZC_BITS;
-   			rx_csr &= ~MUSB_RXCSR_DATAERROR;
-   			musb_writew(epio, MUSB_RXCSR, rx_csr);
- ***************
- *** 1537,1544 ****
-   
-   	/* FIXME this is _way_ too much in-line logic for Mentor DMA */
-   
- ! #ifndef CONFIG_USB_INVENTRA_DMA
- ! 	if (rx_csr & MUSB_RXCSR_H_REQPKT)  {
-   		/* REVISIT this happened for a while on some short reads...
-   		 * the cleanup still needs investigation... looks bad...
-   		 * and also duplicates dma cleanup code above ... plus,
- --- 1671,1677 ----
-   
-   	/* FIXME this is _way_ too much in-line logic for Mentor DMA */
-   
- ! 	if (!is_inventra_dma(musb) && (rx_csr & MUSB_RXCSR_H_REQPKT))  {
-   		/* REVISIT this happened for a while on some short reads...
-   		 * the cleanup still needs investigation... looks bad...
-   		 * and also duplicates dma cleanup code above ... plus,
- ***************
- *** 1555,1565 ****
-   				xfer_len, dma ? ", dma" : "");
-   		rx_csr &= ~MUSB_RXCSR_H_REQPKT;
-   
- ! 		musb_ep_select(mbase, epnum);
-   		musb_writew(epio, MUSB_RXCSR,
-   				MUSB_RXCSR_H_WZC_BITS | rx_csr);
-   	}
- - #endif
-   	if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) {
-   		xfer_len = dma->actual_len;
-   
- --- 1688,1697 ----
-   				xfer_len, dma ? ", dma" : "");
-   		rx_csr &= ~MUSB_RXCSR_H_REQPKT;
-   
- ! 		musb_ep_select(musb, mbase, epnum);
-   		musb_writew(epio, MUSB_RXCSR,
-   				MUSB_RXCSR_H_WZC_BITS | rx_csr);
-   	}
-   	if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) {
-   		xfer_len = dma->actual_len;
-   
- ***************
- *** 1567,1575 ****
-   			| MUSB_RXCSR_H_AUTOREQ
-   			| MUSB_RXCSR_AUTOCLEAR
-   			| MUSB_RXCSR_RXPKTRDY);
-   		musb_writew(hw_ep->regs, MUSB_RXCSR, val);
-   
- - #ifdef CONFIG_USB_INVENTRA_DMA
-   		if (usb_pipeisoc(pipe)) {
-   			struct usb_iso_packet_descriptor *d;
-   
- --- 1699,1710 ----
-   			| MUSB_RXCSR_H_AUTOREQ
-   			| MUSB_RXCSR_AUTOCLEAR
-   			| MUSB_RXCSR_RXPKTRDY);
- + 
- + 		if (is_cppi_enabled(musb) || is_cppi41_enabled(musb))
- + 			val |= MUSB_RXCSR_DMAENAB;
- + 
-   		musb_writew(hw_ep->regs, MUSB_RXCSR, val);
-   
-   		if (usb_pipeisoc(pipe)) {
-   			struct usb_iso_packet_descriptor *d;
-   
- ***************
- *** 1584,1597 ****
-   
-   			if (++qh->iso_idx >= urb->number_of_packets)
-   				done = true;
- ! 			else
-   				done = false;
- ! 
-   		} else  {
- ! 		/* done if urb buffer is full or short packet is recd */
- ! 		done = (urb->actual_length + xfer_len >=
- ! 				urb->transfer_buffer_length
- ! 			|| dma->actual_len < qh->maxpacket);
-   		}
-   
-   		/* send IN token for next packet, without AUTOREQ */
- --- 1719,1751 ----
-   
-   			if (++qh->iso_idx >= urb->number_of_packets)
-   				done = true;
- ! 			else if (is_cppi_enabled(musb) ||
- ! 					is_cppi41_enabled(musb)) {
- ! 				struct dma_controller   *c;
- ! 				void *buf;
- ! 				u32 length, ret;
- ! 
- ! 				c = musb->dma_controller;
- ! 				buf = (void *)
- ! 					urb->iso_frame_desc[qh->iso_idx].offset
- ! 					+ (u32)urb->transfer_dma;
- ! 
- ! 				length =
- ! 					urb->iso_frame_desc[qh->iso_idx].length;
- ! 
- ! 				ret = c->channel_program(dma, qh->maxpacket |
- ! 						(qh->hb_mult << 11),
- ! 						0, (u32) buf, length);
-   				done = false;
- ! 			} else {
- ! 				done = false;
- ! 			}
-   		} else  {
- ! 			/* done if urb buffer is full or short packet is recd */
- ! 			done = (urb->actual_length + xfer_len >=
- ! 					urb->transfer_buffer_length
- ! 				|| dma->actual_len < qh->maxpacket
- ! 				|| dma->actual_len % qh->maxpacket);
-   		}
-   
-   		/* send IN token for next packet, without AUTOREQ */
- ***************
- *** 1601,1613 ****
-   				MUSB_RXCSR_H_WZC_BITS | val);
-   		}
-   
- ! 		dev_dbg(musb->controller, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum,
-   			done ? "off" : "reset",
-   			musb_readw(epio, MUSB_RXCSR),
-   			musb_readw(epio, MUSB_RXCOUNT));
- - #else
- - 		done = true;
- - #endif
-   	} else if (urb->status == -EINPROGRESS) {
-   		/* if no errors, be sure a packet is ready for unloading */
-   		if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) {
- --- 1755,1765 ----
-   				MUSB_RXCSR_H_WZC_BITS | val);
-   		}
-   
- ! 		dev_dbg(musb->controller,
- ! 			"ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum,
-   			done ? "off" : "reset",
-   			musb_readw(epio, MUSB_RXCSR),
-   			musb_readw(epio, MUSB_RXCOUNT));
-   	} else if (urb->status == -EINPROGRESS) {
-   		/* if no errors, be sure a packet is ready for unloading */
-   		if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) {
- ***************
- *** 1618,1631 ****
-   
-   /* SCRUB (RX) */
-   			/* do the proper sequence to abort the transfer */
- ! 			musb_ep_select(mbase, epnum);
-   			val &= ~MUSB_RXCSR_H_REQPKT;
-   			musb_writew(epio, MUSB_RXCSR, val);
-   			goto finish;
-   		}
-   
-   		/* we are expecting IN packets */
- - #ifdef CONFIG_USB_INVENTRA_DMA
-   		if (dma) {
-   			struct dma_controller	*c;
-   			u16			rx_count;
- --- 1770,1782 ----
-   
-   /* SCRUB (RX) */
-   			/* do the proper sequence to abort the transfer */
- ! 			musb_ep_select(musb, mbase, epnum);
-   			val &= ~MUSB_RXCSR_H_REQPKT;
-   			musb_writew(epio, MUSB_RXCSR, val);
-   			goto finish;
-   		}
-   
-   		/* we are expecting IN packets */
-   		if (dma) {
-   			struct dma_controller	*c;
-   			u16			rx_count;
- ***************
- *** 1729,1735 ****
-   			 * adjusted first...
-   			 */
-   			ret = c->channel_program(
- ! 				dma, qh->maxpacket,
-   				dma->desired_mode, buf, length);
-   
-   			if (!ret) {
- --- 1880,1886 ----
-   			 * adjusted first...
-   			 */
-   			ret = c->channel_program(
- ! 				dma, qh->maxpacket | ((qh->hb_mult - 1) << 11),
-   				dma->desired_mode, buf, length);
-   
-   			if (!ret) {
- ***************
- *** 1739,1745 ****
-   				/* REVISIT reset CSR */
-   			}
-   		}
- - #endif	/* Mentor DMA */
-   
-   		if (!dma) {
-   			/* Unmap the buffer so that CPU can use it */
- --- 1890,1895 ----
- ***************
- *** 1754,1761 ****
-   	urb->actual_length += xfer_len;
-   	qh->offset += xfer_len;
-   	if (done) {
- ! 		if (urb->status == -EINPROGRESS)
- ! 			urb->status = status;
-   		musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN);
-   	}
-   }
- --- 1904,1922 ----
-   	urb->actual_length += xfer_len;
-   	qh->offset += xfer_len;
-   	if (done) {
- ! 		if (urb->status == -EINPROGRESS) {
- ! 			/* If short packet is not expected any transfer length
- ! 			 * less than actual length is an error, hence
- ! 			 * set urb status to -EREMOTEIO
- ! 			 */
- ! 			if ((urb->status == -EINPROGRESS)
- ! 				&& (urb->transfer_flags & URB_SHORT_NOT_OK)
- ! 				&& (urb->actual_length
- ! 					< urb->transfer_buffer_length))
- ! 				urb->status = -EREMOTEIO;
- ! 			else
- ! 				urb->status = status;
- ! 		}
-   		musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN);
-   	}
-   }
- ***************
- *** 1849,1862 ****
-   		else
-   			head = &musb->out_bulk;
-   
- ! 		/* Enable bulk RX NAK timeout scheme when bulk requests are
-   		 * multiplexed.  This scheme doen't work in high speed to full
-   		 * speed scenario as NAK interrupts are not coming from a
-   		 * full speed device connected to a high speed device.
-   		 * NAK timeout interval is 8 (128 uframe or 16ms) for HS and
-   		 * 4 (8 frame or 8ms) for FS device.
-   		 */
- ! 		if (is_in && qh->dev)
-   			qh->intv_reg =
-   				(USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4;
-   		goto success;
- --- 2010,2023 ----
-   		else
-   			head = &musb->out_bulk;
-   
- ! 		/* Enable bulk RX/TX NAK timeout scheme when bulk requests are
-   		 * multiplexed.  This scheme doen't work in high speed to full
-   		 * speed scenario as NAK interrupts are not coming from a
-   		 * full speed device connected to a high speed device.
-   		 * NAK timeout interval is 8 (128 uframe or 16ms) for HS and
-   		 * 4 (8 frame or 8ms) for FS device.
-   		 */
- ! 		if (qh->dev)
-   			qh->intv_reg =
-   				(USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4;
-   		goto success;
- ***************
- *** 1904,1909 ****
- --- 2065,2072 ----
-   	qh = ret ? NULL : hep->hcpriv;
-   	if (qh)
-   		urb->hcpriv = qh;
- + 
- + 	INIT_LIST_HEAD(&urb->giveback_list);
-   	spin_unlock_irqrestore(&musb->lock, flags);
-   
-   	/* DMA mapping was already done, if needed, and this urb is on
- ***************
- *** 2081,2087 ****
-   	int			status = 0;
-   	u16			csr;
-   
- ! 	musb_ep_select(regs, hw_end);
-   
-   	if (is_dma_capable()) {
-   		struct dma_channel	*dma;
- --- 2244,2250 ----
-   	int			status = 0;
-   	u16			csr;
-   
- ! 	musb_ep_select(ep->musb, regs, hw_end);
-   
-   	if (is_dma_capable()) {
-   		struct dma_channel	*dma;
- ***************
- *** 2098,2104 ****
-   	}
-   
-   	/* turn off DMA requests, discard state, stop polling ... */
- ! 	if (is_in) {
-   		/* giveback saves bulk toggle */
-   		csr = musb_h_flush_rxfifo(ep, 0);
-   
- --- 2261,2267 ----
-   	}
-   
-   	/* turn off DMA requests, discard state, stop polling ... */
- ! 	if (is_in && ep->epnum) {
-   		/* giveback saves bulk toggle */
-   		csr = musb_h_flush_rxfifo(ep, 0);
-   
- ***************
- *** 2167,2174 ****
- --- 2330,2341 ----
-   			|| musb_ep_get_qh(qh->hw_ep, is_in) != qh) {
-   		int	ready = qh->is_ready;
-   
- + 		usb_hcd_unlink_urb_from_ep(musb_to_hcd(musb), urb);
- + 
-   		qh->is_ready = 0;
- + 		spin_unlock(&musb->lock);
-   		musb_giveback(musb, urb, 0);
- + 		spin_lock(&musb->lock);
-   		qh->is_ready = ready;
-   
-   		/* If nothing else (usually musb_giveback) is using it
- ***************
- *** 2229,2236 ****
-   		 * other transfers, and since !qh->is_ready nothing
-   		 * will activate any of these as it advances.
-   		 */
- ! 		while (!list_empty(&hep->urb_list))
- ! 			musb_giveback(musb, next_urb(qh), -ESHUTDOWN);
-   
-   		hep->hcpriv = NULL;
-   		list_del(&qh->ring);
- --- 2396,2408 ----
-   		 * other transfers, and since !qh->is_ready nothing
-   		 * will activate any of these as it advances.
-   		 */
- ! 		while (!list_empty(&hep->urb_list)) {
- ! 			urb = next_urb(qh);
- ! 			usb_hcd_unlink_urb_from_ep(musb_to_hcd(musb), urb);
- ! 			spin_unlock(&musb->lock);
- ! 			musb_giveback(musb, urb, -ESHUTDOWN);
- ! 			spin_lock(&musb->lock);
- ! 		}
-   
-   		hep->hcpriv = NULL;
-   		list_del(&qh->ring);
- ***************
- *** 2290,2296 ****
-   	}
-   
-   	if (musb->is_active) {
- ! 		WARNING("trying to suspend as %s while active\n",
-   				otg_state_string(musb->xceiv->state));
-   		return -EBUSY;
-   	} else
- --- 2462,2468 ----
-   	}
-   
-   	if (musb->is_active) {
- ! 		dev_dbg(musb->controller, "trying to suspend as %s while active\n",
-   				otg_state_string(musb->xceiv->state));
-   		return -EBUSY;
-   	} else
- ***************
- *** 2299,2305 ****
-   
-   static int musb_bus_resume(struct usb_hcd *hcd)
-   {
- - 	/* resuming child port does the work */
-   	return 0;
-   }
-   
- --- 2471,2476 ----
- diff -crN linux-3.2.1_o/drivers/usb/musb/musbhsdma.c linux-3.2.1/drivers/usb/musb/musbhsdma.c
- *** linux-3.2.1_o/drivers/usb/musb/musbhsdma.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/musb/musbhsdma.c	2014-05-15 13:25:15.094568420 +0900
- ***************
- *** 30,35 ****
- --- 30,36 ----
-    * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-    *
-    */
- + #include <linux/module.h>
-   #include <linux/device.h>
-   #include <linux/interrupt.h>
-   #include <linux/platform_device.h>
- ***************
- *** 205,218 ****
-   {
-   	struct musb_dma_channel *musb_channel = channel->private_data;
-   	void __iomem *mbase = musb_channel->controller->base;
- ! 
-   	u8 bchannel = musb_channel->idx;
-   	int offset;
-   	u16 csr;
-   
-   	if (channel->status == MUSB_DMA_STATUS_BUSY) {
-   		if (musb_channel->transmit) {
- ! 			offset = MUSB_EP_OFFSET(musb_channel->epnum,
-   						MUSB_TXCSR);
-   
-   			/*
- --- 206,219 ----
-   {
-   	struct musb_dma_channel *musb_channel = channel->private_data;
-   	void __iomem *mbase = musb_channel->controller->base;
- ! 	struct musb *musb = musb_channel->controller->private_data;
-   	u8 bchannel = musb_channel->idx;
-   	int offset;
-   	u16 csr;
-   
-   	if (channel->status == MUSB_DMA_STATUS_BUSY) {
-   		if (musb_channel->transmit) {
- ! 			offset = MUSB_EP_OFFSET(musb, musb_channel->epnum,
-   						MUSB_TXCSR);
-   
-   			/*
- ***************
- *** 225,231 ****
-   			csr &= ~MUSB_TXCSR_DMAMODE;
-   			musb_writew(mbase, offset, csr);
-   		} else {
- ! 			offset = MUSB_EP_OFFSET(musb_channel->epnum,
-   						MUSB_RXCSR);
-   
-   			csr = musb_readw(mbase, offset);
- --- 226,232 ----
-   			csr &= ~MUSB_TXCSR_DMAMODE;
-   			musb_writew(mbase, offset, csr);
-   		} else {
- ! 			offset = MUSB_EP_OFFSET(musb, musb_channel->epnum,
-   						MUSB_RXCSR);
-   
-   			csr = musb_readw(mbase, offset);
- ***************
- *** 336,342 ****
-   					    (musb_channel->max_packet_sz - 1)))
-   				    ) {
-   					u8  epnum  = musb_channel->epnum;
- ! 					int offset = MUSB_EP_OFFSET(epnum,
-   								    MUSB_TXCSR);
-   					u16 txcsr;
-   
- --- 337,343 ----
-   					    (musb_channel->max_packet_sz - 1)))
-   				    ) {
-   					u8  epnum  = musb_channel->epnum;
- ! 					int offset = MUSB_EP_OFFSET(musb, epnum,
-   								    MUSB_TXCSR);
-   					u16 txcsr;
-   
- ***************
- *** 344,350 ****
-   					 * The programming guide says that we
-   					 * must clear DMAENAB before DMAMODE.
-   					 */
- ! 					musb_ep_select(mbase, epnum);
-   					txcsr = musb_readw(mbase, offset);
-   					txcsr &= ~(MUSB_TXCSR_DMAENAB
-   							| MUSB_TXCSR_AUTOSET);
- --- 345,351 ----
-   					 * The programming guide says that we
-   					 * must clear DMAENAB before DMAMODE.
-   					 */
- ! 					musb_ep_select(musb, mbase, epnum);
-   					txcsr = musb_readw(mbase, offset);
-   					txcsr &= ~(MUSB_TXCSR_DMAENAB
-   							| MUSB_TXCSR_AUTOSET);
- ***************
- *** 366,372 ****
-   	return retval;
-   }
-   
- ! void dma_controller_destroy(struct dma_controller *c)
-   {
-   	struct musb_dma_controller *controller = container_of(c,
-   			struct musb_dma_controller, controller);
- --- 367,373 ----
-   	return retval;
-   }
-   
- ! void inventra_dma_controller_destroy(struct dma_controller *c)
-   {
-   	struct musb_dma_controller *controller = container_of(c,
-   			struct musb_dma_controller, controller);
- ***************
- *** 379,387 ****
-   
-   	kfree(controller);
-   }
-   
- ! struct dma_controller *__init
- ! dma_controller_create(struct musb *musb, void __iomem *base)
-   {
-   	struct musb_dma_controller *controller;
-   	struct device *dev = musb->controller;
- --- 380,389 ----
-   
-   	kfree(controller);
-   }
- + EXPORT_SYMBOL(inventra_dma_controller_destroy);
-   
- ! struct dma_controller *__devinit
- ! inventra_dma_controller_create(struct musb *musb, void __iomem *base)
-   {
-   	struct musb_dma_controller *controller;
-   	struct device *dev = musb->controller;
- ***************
- *** 411,417 ****
-   	if (request_irq(irq, dma_controller_irq, 0,
-   			dev_name(musb->controller), &controller->controller)) {
-   		dev_err(dev, "request_irq %d failed!\n", irq);
- ! 		dma_controller_destroy(&controller->controller);
-   
-   		return NULL;
-   	}
- --- 413,419 ----
-   	if (request_irq(irq, dma_controller_irq, 0,
-   			dev_name(musb->controller), &controller->controller)) {
-   		dev_err(dev, "request_irq %d failed!\n", irq);
- ! 		inventra_dma_controller_destroy(&controller->controller);
-   
-   		return NULL;
-   	}
- ***************
- *** 420,422 ****
- --- 422,439 ----
-   
-   	return &controller->controller;
-   }
- + EXPORT_SYMBOL(inventra_dma_controller_create);
- + 
- + MODULE_DESCRIPTION("MUSB Inventra dma controller driver");
- + MODULE_LICENSE("GPL v2");
- + 
- + static int __init inventra_dma_init(void)
- + {
- + 	return 0;
- + }
- + module_init(inventra_dma_init);
- + 
- + static void __exit inventra_dma__exit(void)
- + {
- + }
- + module_exit(inventra_dma__exit);
- diff -crN linux-3.2.1_o/drivers/usb/musb/musb_io.h linux-3.2.1/drivers/usb/musb/musb_io.h
- *** linux-3.2.1_o/drivers/usb/musb/musb_io.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/musb/musb_io.h	2014-05-15 13:25:15.094568420 +0900
- ***************
- *** 61,135 ****
-   /* NOTE:  these offsets are all in bytes */
-   
-   static inline u16 musb_readw(const void __iomem *addr, unsigned offset)
- ! 	{ return __raw_readw(addr + offset); }
-   
-   static inline u32 musb_readl(const void __iomem *addr, unsigned offset)
- ! 	{ return __raw_readl(addr + offset); }
-   
-   
-   static inline void musb_writew(void __iomem *addr, unsigned offset, u16 data)
- ! 	{ __raw_writew(data, addr + offset); }
-   
-   static inline void musb_writel(void __iomem *addr, unsigned offset, u32 data)
- ! 	{ __raw_writel(data, addr + offset); }
- ! 
- ! 
- ! #ifdef CONFIG_USB_MUSB_TUSB6010
- ! 
- ! /*
- !  * TUSB6010 doesn't allow 8-bit access; 16-bit access is the minimum.
- !  */
- ! static inline u8 musb_readb(const void __iomem *addr, unsigned offset)
- ! {
- ! 	u16 tmp;
- ! 	u8 val;
- ! 
- ! 	tmp = __raw_readw(addr + (offset & ~1));
- ! 	if (offset & 1)
- ! 		val = (tmp >> 8);
- ! 	else
- ! 		val = tmp & 0xff;
- ! 
- ! 	return val;
- ! }
- ! 
- ! static inline void musb_writeb(void __iomem *addr, unsigned offset, u8 data)
- ! {
- ! 	u16 tmp;
- ! 
- ! 	tmp = __raw_readw(addr + (offset & ~1));
- ! 	if (offset & 1)
- ! 		tmp = (data << 8) | (tmp & 0xff);
- ! 	else
- ! 		tmp = (tmp & 0xff00) | data;
- ! 
- ! 	__raw_writew(tmp, addr + (offset & ~1));
- ! }
- ! 
- ! #else
- ! 
- ! static inline u8 musb_readb(const void __iomem *addr, unsigned offset)
- ! 	{ return __raw_readb(addr + offset); }
- ! 
- ! static inline void musb_writeb(void __iomem *addr, unsigned offset, u8 data)
- ! 	{ __raw_writeb(data, addr + offset); }
- ! 
- ! #endif	/* CONFIG_USB_MUSB_TUSB6010 */
-   
-   #else
-   
- - static inline u8 musb_readb(const void __iomem *addr, unsigned offset)
- - 	{ return (u8) (bfin_read16(addr + offset)); }
- - 
-   static inline u16 musb_readw(const void __iomem *addr, unsigned offset)
-   	{ return bfin_read16(addr + offset); }
-   
-   static inline u32 musb_readl(const void __iomem *addr, unsigned offset)
-   	{ return (u32) (bfin_read16(addr + offset)); }
-   
- - static inline void musb_writeb(void __iomem *addr, unsigned offset, u8 data)
- - 	{ bfin_write16(addr + offset, (u16) data); }
- - 
-   static inline void musb_writew(void __iomem *addr, unsigned offset, u16 data)
-   	{ bfin_write16(addr + offset, data); }
-   
- --- 61,86 ----
-   /* NOTE:  these offsets are all in bytes */
-   
-   static inline u16 musb_readw(const void __iomem *addr, unsigned offset)
- ! 	{ return readw(addr + offset); }
-   
-   static inline u32 musb_readl(const void __iomem *addr, unsigned offset)
- ! 	{ return readl(addr + offset); }
-   
-   
-   static inline void musb_writew(void __iomem *addr, unsigned offset, u16 data)
- ! 	{ writew(data, addr + offset); }
-   
-   static inline void musb_writel(void __iomem *addr, unsigned offset, u32 data)
- ! 	{ writel(data, addr + offset); }
-   
-   #else
-   
-   static inline u16 musb_readw(const void __iomem *addr, unsigned offset)
-   	{ return bfin_read16(addr + offset); }
-   
-   static inline u32 musb_readl(const void __iomem *addr, unsigned offset)
-   	{ return (u32) (bfin_read16(addr + offset)); }
-   
-   static inline void musb_writew(void __iomem *addr, unsigned offset, u16 data)
-   	{ bfin_write16(addr + offset, data); }
-   
- diff -crN linux-3.2.1_o/drivers/usb/musb/musb_procfs.c linux-3.2.1/drivers/usb/musb/musb_procfs.c
- *** linux-3.2.1_o/drivers/usb/musb/musb_procfs.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/drivers/usb/musb/musb_procfs.c	2014-05-15 13:25:15.094568420 +0900
- ***************
- *** 0 ****
- --- 1,809 ----
- + /*
- +  * MUSB OTG driver debug support
- +  *
- +  * Copyright 2005 Mentor Graphics Corporation
- +  * Copyright (C) 2005-2006 by Texas Instruments
- +  * Copyright (C) 2006-2007 Nokia Corporation
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License
- +  * version 2 as published by the Free Software Foundation.
- +  *
- +  * This program is distributed in the hope that it will be useful, but
- +  * WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- +  * General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- +  * 02110-1301 USA
- +  *
- +  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- +  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- +  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- +  * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- +  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- +  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- +  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- +  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- +  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- +  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- +  *
- +  */
- + 
- + #include <linux/kernel.h>
- + #include <linux/proc_fs.h>
- + #include <linux/seq_file.h>
- + #include <linux/uaccess.h>	/* FIXME remove procfs writes */
- + #include <mach/hardware.h>
- + 
- + #include "musb_core.h"
- + 
- + #include "davinci.h"
- + 
- + static int dump_qh(struct musb_qh *qh, char *buf, unsigned max)
- + {
- + 	int				count;
- + 	int				tmp;
- + 	struct usb_host_endpoint	*hep = qh->hep;
- + 	struct urb			*urb;
- + 
- + 	count = snprintf(buf, max, "    qh %p dev%d ep%d%s max%d\n",
- + 			qh, qh->dev->devnum, qh->epnum,
- + 			({ char *s; switch (qh->type) {
- + 			case USB_ENDPOINT_XFER_BULK:
- + 				s = "-bulk"; break;
- + 			case USB_ENDPOINT_XFER_INT:
- + 				s = "-int"; break;
- + 			case USB_ENDPOINT_XFER_CONTROL:
- + 				s = ""; break;
- + 			default:
- + 				s = "iso"; break;
- + 			}; s; }),
- + 			qh->maxpacket);
- + 	if (count <= 0)
- + 		return 0;
- + 	buf += count;
- + 	max -= count;
- + 
- + 	list_for_each_entry(urb, &hep->urb_list, urb_list) {
- + 		tmp = snprintf(buf, max, "\t%s urb %p %d/%d\n",
- + 				usb_pipein(urb->pipe) ? "in" : "out",
- + 				urb, urb->actual_length,
- + 				urb->transfer_buffer_length);
- + 		if (tmp <= 0)
- + 			break;
- + 		tmp = min(tmp, (int)max);
- + 		count += tmp;
- + 		buf += tmp;
- + 		max -= tmp;
- + 	}
- + 	return count;
- + }
- + 
- + static int
- + dump_queue(struct list_head *q, char *buf, unsigned max)
- + {
- + 	int		count = 0;
- + 	struct musb_qh	*qh;
- + 
- + 	list_for_each_entry(qh, q, ring) {
- + 		int	tmp;
- + 
- + 		tmp = dump_qh(qh, buf, max);
- + 		if (tmp <= 0)
- + 			break;
- + 		tmp = min(tmp, (int)max);
- + 		count += tmp;
- + 		buf += tmp;
- + 		max -= tmp;
- + 	}
- + 	return count;
- + }
- + 
- + static int dump_ep(struct musb_ep *ep, char *buffer, unsigned max)
- + {
- + 	char		*buf = buffer;
- + 	int		code = 0;
- + 	void __iomem	*regs = ep->hw_ep->regs;
- + 	char		*mode = "1buf";
- + 
- + 	if (ep->is_in) {
- + 		if (ep->hw_ep->tx_double_buffered)
- + 			mode = "2buf";
- + 	} else {
- + 		if (ep->hw_ep->rx_double_buffered)
- + 			mode = "2buf";
- + 	}
- + 
- + 	do {
- + 		struct usb_request	*req;
- + 
- + 		code = snprintf(buf, max,
- + 				"\n%s (hw%d): %s%s, csr %04x maxp %04x\n",
- + 				ep->name, ep->current_epnum,
- + 				mode, ep->dma ? " dma" : "",
- + 				musb_readw(regs,
- + 					(ep->is_in || !ep->current_epnum)
- + 						? MUSB_TXCSR
- + 						: MUSB_RXCSR),
- + 				musb_readw(regs, ep->is_in
- + 						? MUSB_TXMAXP
- + 						: MUSB_RXMAXP)
- + 				);
- + 		if (code <= 0)
- + 			break;
- + 		code = min(code, (int) max);
- + 		buf += code;
- + 		max -= code;
- + 
- + 		if ((is_cppi_enabled(ep->musb) || is_cppi41_enabled(ep->musb))
- + 				&& ep->current_epnum) {
- + 			unsigned	cppi = ep->current_epnum - 1;
- + 			void __iomem	*base = ep->musb->ctrl_base;
- + 			unsigned	off1 = cppi << 2;
- + 			void __iomem	*ram = base;
- + 			char		tmp[16];
- + 
- + 			if (ep->is_in) {
- + 				ram += DAVINCI_TXCPPI_STATERAM_OFFSET(cppi);
- + 				tmp[0] = 0;
- + 			} else {
- + 				ram += DAVINCI_RXCPPI_STATERAM_OFFSET(cppi);
- + 				snprintf(tmp, sizeof tmp, "%d left, ",
- + 					musb_readl(base,
- + 					DAVINCI_RXCPPI_BUFCNT0_REG + off1));
- + 			}
- + 
- + 			code = snprintf(buf, max, "%cX DMA%d: %s"
- + 					"%08x %08x, %08x %08x; "
- + 					"%08x %08x %08x .. %08x\n",
- + 				ep->is_in ? 'T' : 'R',
- + 				ep->current_epnum - 1, tmp,
- + 				musb_readl(ram, 0 * 4),
- + 				musb_readl(ram, 1 * 4),
- + 				musb_readl(ram, 2 * 4),
- + 				musb_readl(ram, 3 * 4),
- + 				musb_readl(ram, 4 * 4),
- + 				musb_readl(ram, 5 * 4),
- + 				musb_readl(ram, 6 * 4),
- + 				musb_readl(ram, 7 * 4));
- + 			if (code <= 0)
- + 				break;
- + 			code = min(code, (int) max);
- + 			buf += code;
- + 			max -= code;
- + 		}
- + 
- + 		if (list_empty(&ep->req_list)) {
- + 			code = snprintf(buf, max, "\t(queue empty)\n");
- + 			if (code <= 0)
- + 				break;
- + 			code = min(code, (int) max);
- + 			buf += code;
- + 			max -= code;
- + 			break;
- + 		}
- + 		list_for_each_entry(req, &ep->req_list, list) {
- + 			code = snprintf(buf, max, "\treq %p, %s%s%d/%d\n",
- + 					req,
- + 					req->zero ? "zero, " : "",
- + 					req->short_not_ok ? "!short, " : "",
- + 					req->actual, req->length);
- + 			if (code <= 0)
- + 				break;
- + 			code = min(code, (int) max);
- + 			buf += code;
- + 			max -= code;
- + 		}
- + 	} while (0);
- + 	return buf - buffer;
- + }
- + 
- + static int
- + dump_end_info(struct musb *musb, u8 epnum, char *aBuffer, unsigned max)
- + {
- + 	int			code = 0;
- + 	char			*buf = aBuffer;
- + 	struct musb_hw_ep	*hw_ep = &musb->endpoints[epnum];
- + 
- + 	do {
- + 		musb_ep_select(musb, musb->mregs, epnum);
- + 		if (is_host_active(musb)) {
- + 			int		dump_rx, dump_tx;
- + 			void __iomem	*regs = hw_ep->regs;
- + 
- + 			/* TEMPORARY (!) until we have a real periodic
- + 			 * schedule tree ...
- + 			 */
- + 			if (!epnum) {
- + 				/* control is shared, uses RX queue
- + 				 * but (mostly) shadowed tx registers
- + 				 */
- + 				dump_tx = !list_empty(&musb->control);
- + 				dump_rx = 0;
- + 			} else if (hw_ep == musb->bulk_ep) {
- + 				dump_tx = !list_empty(&musb->out_bulk);
- + 				dump_rx = !list_empty(&musb->in_bulk);
- + 			} else if (hw_ep->in_qh || hw_ep->out_qh) {
- + 				if (hw_ep->in_qh)
- + 					dump_rx = 1;
- + 				else
- + 					dump_rx = 0;
- + 				dump_tx = !dump_rx;
- + 			} else
- + 				break;
- + 			/* END TEMPORARY */
- + 
- + 
- + 			if (dump_rx) {
- + 				code = snprintf(buf, max,
- + 					"\nRX%d: %s rxcsr %04x interval %02x "
- + 					"max %04x type %02x; "
- + 					"dev %d hub %d port %d"
- + 					"\n",
- + 					epnum,
- + 					hw_ep->rx_double_buffered
- + 						? "2buf" : "1buf",
- + 					musb_readw(regs, MUSB_RXCSR),
- + 					musb_readb(regs, MUSB_RXINTERVAL),
- + 					musb_readw(regs, MUSB_RXMAXP),
- + 					musb_readb(regs, MUSB_RXTYPE),
- + 					/* FIXME:  assumes multipoint */
- + 					musb_readb(musb->mregs,
- + 						MUSB_BUSCTL_OFFSET(epnum,
- + 						MUSB_RXFUNCADDR)),
- + 					musb_readb(musb->mregs,
- + 						MUSB_BUSCTL_OFFSET(epnum,
- + 						MUSB_RXHUBADDR)),
- + 					musb_readb(musb->mregs,
- + 						MUSB_BUSCTL_OFFSET(epnum,
- + 						MUSB_RXHUBPORT))
- + 					);
- + 				if (code <= 0)
- + 					break;
- + 				code = min(code, (int) max);
- + 				buf += code;
- + 				max -= code;
- + 
- + 				if ((is_cppi_enabled(musb) ||
- + 						is_cppi41_enabled(musb))
- + 						&& epnum
- + 						&& hw_ep->rx_channel) {
- + 					unsigned	cppi = epnum - 1;
- + 					unsigned	off1 = cppi << 2;
- + 					void __iomem	*base;
- + 					void __iomem	*ram;
- + 					char		tmp[16];
- + 
- + 					base = musb->ctrl_base;
- + 					ram = DAVINCI_RXCPPI_STATERAM_OFFSET(
- + 							cppi) + base;
- + 					snprintf(tmp, sizeof tmp, "%d left, ",
- + 						musb_readl(base,
- + 						DAVINCI_RXCPPI_BUFCNT0_REG
- + 								+ off1));
- + 
- + 					code = snprintf(buf, max,
- + 						"    rx dma%d: %s"
- + 						"%08x %08x, %08x %08x; "
- + 						"%08x %08x %08x .. %08x\n",
- + 						cppi, tmp,
- + 						musb_readl(ram, 0 * 4),
- + 						musb_readl(ram, 1 * 4),
- + 						musb_readl(ram, 2 * 4),
- + 						musb_readl(ram, 3 * 4),
- + 						musb_readl(ram, 4 * 4),
- + 						musb_readl(ram, 5 * 4),
- + 						musb_readl(ram, 6 * 4),
- + 						musb_readl(ram, 7 * 4));
- + 					if (code <= 0)
- + 						break;
- + 					code = min(code, (int) max);
- + 					buf += code;
- + 					max -= code;
- + 				}
- + 
- + 				if (hw_ep == musb->bulk_ep
- + 						&& !list_empty(
- + 							&musb->in_bulk)) {
- + 					code = dump_queue(&musb->in_bulk,
- + 							buf, max);
- + 					if (code <= 0)
- + 						break;
- + 					code = min(code, (int) max);
- + 					buf += code;
- + 					max -= code;
- + 				} else if (hw_ep->in_qh) {
- + 					code = dump_qh(hw_ep->in_qh,
- + 							buf, max);
- + 					if (code <= 0)
- + 						break;
- + 					code = min(code, (int) max);
- + 					buf += code;
- + 					max -= code;
- + 				}
- + 			}
- + 
- + 			if (dump_tx) {
- + 				code = snprintf(buf, max,
- + 					"\nTX%d: %s txcsr %04x interval %02x "
- + 					"max %04x type %02x; "
- + 					"dev %d hub %d port %d"
- + 					"\n",
- + 					epnum,
- + 					hw_ep->tx_double_buffered
- + 						? "2buf" : "1buf",
- + 					musb_readw(regs, MUSB_TXCSR),
- + 					musb_readb(regs, MUSB_TXINTERVAL),
- + 					musb_readw(regs, MUSB_TXMAXP),
- + 					musb_readb(regs, MUSB_TXTYPE),
- + 					/* FIXME:  assumes multipoint */
- + 					musb_readb(musb->mregs,
- + 						MUSB_BUSCTL_OFFSET(epnum,
- + 						MUSB_TXFUNCADDR)),
- + 					musb_readb(musb->mregs,
- + 						MUSB_BUSCTL_OFFSET(epnum,
- + 						MUSB_TXHUBADDR)),
- + 					musb_readb(musb->mregs,
- + 						MUSB_BUSCTL_OFFSET(epnum,
- + 						MUSB_TXHUBPORT))
- + 					);
- + 				if (code <= 0)
- + 					break;
- + 				code = min(code, (int) max);
- + 				buf += code;
- + 				max -= code;
- + 
- + 				if ((is_cppi_enabled(musb) ||
- + 						is_cppi41_enabled(musb))
- + 						&& epnum
- + 						&& hw_ep->tx_channel) {
- + 					unsigned	cppi = epnum - 1;
- + 					void __iomem	*base;
- + 					void __iomem	*ram;
- + 
- + 					base = musb->ctrl_base;
- + 					ram = DAVINCI_RXCPPI_STATERAM_OFFSET(
- + 							cppi) + base;
- + 					code = snprintf(buf, max,
- + 						"    tx dma%d: "
- + 						"%08x %08x, %08x %08x; "
- + 						"%08x %08x %08x .. %08x\n",
- + 						cppi,
- + 						musb_readl(ram, 0 * 4),
- + 						musb_readl(ram, 1 * 4),
- + 						musb_readl(ram, 2 * 4),
- + 						musb_readl(ram, 3 * 4),
- + 						musb_readl(ram, 4 * 4),
- + 						musb_readl(ram, 5 * 4),
- + 						musb_readl(ram, 6 * 4),
- + 						musb_readl(ram, 7 * 4));
- + 					if (code <= 0)
- + 						break;
- + 					code = min(code, (int) max);
- + 					buf += code;
- + 					max -= code;
- + 				}
- + 
- + 				if (hw_ep == musb->control_ep
- + 						&& !list_empty(
- + 							&musb->control)) {
- + 					code = dump_queue(&musb->control,
- + 							buf, max);
- + 					if (code <= 0)
- + 						break;
- + 					code = min(code, (int) max);
- + 					buf += code;
- + 					max -= code;
- + 				} else if (hw_ep == musb->bulk_ep
- + 						&& !list_empty(
- + 							&musb->out_bulk)) {
- + 					code = dump_queue(&musb->out_bulk,
- + 							buf, max);
- + 					if (code <= 0)
- + 						break;
- + 					code = min(code, (int) max);
- + 					buf += code;
- + 					max -= code;
- + 				} else if (hw_ep->out_qh) {
- + 					code = dump_qh(hw_ep->out_qh,
- + 							buf, max);
- + 					if (code <= 0)
- + 						break;
- + 					code = min(code, (int) max);
- + 					buf += code;
- + 					max -= code;
- + 				}
- + 			}
- + 		}
- + 		if (is_peripheral_active(musb)) {
- + 			code = 0;
- + 
- + 			if (hw_ep->ep_in.desc || !epnum) {
- + 				code = dump_ep(&hw_ep->ep_in, buf, max);
- + 				if (code <= 0)
- + 					break;
- + 				code = min(code, (int) max);
- + 				buf += code;
- + 				max -= code;
- + 			}
- + 			if (hw_ep->ep_out.desc) {
- + 				code = dump_ep(&hw_ep->ep_out, buf, max);
- + 				if (code <= 0)
- + 					break;
- + 				code = min(code, (int) max);
- + 				buf += code;
- + 				max -= code;
- + 			}
- + 		}
- + 	} while (0);
- + 
- + 	return buf - aBuffer;
- + }
- + 
- + /* Dump the current status and compile options.
- +  * @param musb the device driver instance
- +  * @param buffer where to dump the status; it must be big enough to hold the
- +  * result otherwise "BAD THINGS HAPPENS(TM)".
- +  */
- + static int dump_header_stats(struct musb *musb, char *buffer)
- + {
- + 	int code, count = 0;
- + 	const void __iomem *mbase = musb->mregs;
- + 
- + 	*buffer = 0;
- + 	count = sprintf(buffer, "Status: %sHDRC, Mode=%s "
- + 				"(Power=%02x, DevCtl=%02x)\n",
- + 			(musb->is_multipoint ? "M" : ""), MUSB_MODE(musb),
- + 			musb_readb(mbase, MUSB_POWER),
- + 			musb_readb(mbase, MUSB_DEVCTL));
- + 	if (count <= 0)
- + 		return 0;
- + 	buffer += count;
- + 
- + 	code = sprintf(buffer, "OTG state: %s; %sactive\n",
- + 			otg_state_string(musb->xceiv->state),
- + 			musb->is_active ? "" : "in");
- + 	if (code <= 0)
- + 		goto done;
- + 	buffer += code;
- + 	count += code;
- + 
- + 	code = sprintf(buffer,
- + 			"Options: "
- + #ifdef CONFIG_MUSB_PIO_ONLY
- + 			"pio"
- + #elif defined(CONFIG_USB_TI_CPPI_DMA)
- + 			"cppi-dma"
- + #elif defined(CONFIG_USB_INVENTRA_DMA)
- + 			"musb-dma"
- + #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
- + 			"tusb-omap-dma"
- + #else
- + 			"?dma?"
- + #endif
- + 			", "
- + 			"otg (peripheral+host)"
- + 			", [eps=%d]\n",
- + 		musb->nr_endpoints);
- + 	if (code <= 0)
- + 		goto done;
- + 	count += code;
- + 	buffer += code;
- + 
- + 	code = sprintf(buffer, "Peripheral address: %02x\n",
- + 			musb_readb(musb->ctrl_base, MUSB_FADDR));
- + 	if (code <= 0)
- + 		goto done;
- + 	buffer += code;
- + 	count += code;
- + 
- + 	code = sprintf(buffer, "Root port status: %08x\n",
- + 			musb->port1_status);
- + 	if (code <= 0)
- + 		goto done;
- + 	buffer += code;
- + 	count += code;
- + 
- + #ifdef	CONFIG_ARCH_DAVINCI
- + 	code = sprintf(buffer,
- + 			"DaVinci: ctrl=%02x stat=%1x phy=%03x\n"
- + 			"\trndis=%05x auto=%04x intsrc=%08x intmsk=%08x"
- + 			"\n",
- + 			musb_readl(musb->ctrl_base, DAVINCI_USB_CTRL_REG),
- + 			musb_readl(musb->ctrl_base, DAVINCI_USB_STAT_REG),
- + 			readl((void __force __iomem *)
- + 					IO_ADDRESS(USBPHY_CTL_PADDR)),
- + 			musb_readl(musb->ctrl_base, DAVINCI_RNDIS_REG),
- + 			musb_readl(musb->ctrl_base, DAVINCI_AUTOREQ_REG),
- + 			musb_readl(musb->ctrl_base,
- + 					DAVINCI_USB_INT_SOURCE_REG),
- + 			musb_readl(musb->ctrl_base,
- + 					DAVINCI_USB_INT_MASK_REG));
- + 	if (code <= 0)
- + 		goto done;
- + 	count += code;
- + 	buffer += code;
- + #endif	/* DAVINCI */
- + 
- + #ifdef CONFIG_USB_TUSB6010
- + 	code = sprintf(buffer,
- + 			"TUSB6010: devconf %08x, phy enable %08x drive %08x"
- + 			"\n\totg %03x timer %08x"
- + 			"\n\tprcm conf %08x mgmt %08x; int src %08x mask %08x"
- + 			"\n",
- + 			musb_readl(musb->ctrl_base, TUSB_DEV_CONF),
- + 			musb_readl(musb->ctrl_base, TUSB_PHY_OTG_CTRL_ENABLE),
- + 			musb_readl(musb->ctrl_base, TUSB_PHY_OTG_CTRL),
- + 			musb_readl(musb->ctrl_base, TUSB_DEV_OTG_STAT),
- + 			musb_readl(musb->ctrl_base, TUSB_DEV_OTG_TIMER),
- + 			musb_readl(musb->ctrl_base, TUSB_PRCM_CONF),
- + 			musb_readl(musb->ctrl_base, TUSB_PRCM_MNGMT),
- + 			musb_readl(musb->ctrl_base, TUSB_INT_SRC),
- + 			musb_readl(musb->ctrl_base, TUSB_INT_MASK));
- + 	if (code <= 0)
- + 		goto done;
- + 	count += code;
- + 	buffer += code;
- + #endif	/* DAVINCI */
- + 
- + 	if ((is_cppi_enabled(musb) || is_cppi41_enabled(musb))
- + 		&& musb->dma_controller) {
- + 		code = sprintf(buffer,
- + 				"CPPI: txcr=%d txsrc=%01x txena=%01x; "
- + 				"rxcr=%d rxsrc=%01x rxena=%01x "
- + 				"\n",
- + 				musb_readl(musb->ctrl_base,
- + 						DAVINCI_TXCPPI_CTRL_REG),
- + 				musb_readl(musb->ctrl_base,
- + 						DAVINCI_TXCPPI_RAW_REG),
- + 				musb_readl(musb->ctrl_base,
- + 						DAVINCI_TXCPPI_INTENAB_REG),
- + 				musb_readl(musb->ctrl_base,
- + 						DAVINCI_RXCPPI_CTRL_REG),
- + 				musb_readl(musb->ctrl_base,
- + 						DAVINCI_RXCPPI_RAW_REG),
- + 				musb_readl(musb->ctrl_base,
- + 						DAVINCI_RXCPPI_INTENAB_REG));
- + 		if (code <= 0)
- + 			goto done;
- + 		count += code;
- + 		buffer += code;
- + 	}
- + 
- + 	if (is_peripheral_enabled(musb)) {
- + 		code = sprintf(buffer, "Gadget driver: %s\n",
- + 				musb->gadget_driver
- + 					? musb->gadget_driver->driver.name
- + 					: "(none)");
- + 		if (code <= 0)
- + 			goto done;
- + 		count += code;
- + 		buffer += code;
- + 	}
- + 
- + done:
- + 	return count;
- + }
- + 
- + /* Write to ProcFS
- +  *
- +  * C soft-connect
- +  * c soft-disconnect
- +  * I enable HS
- +  * i disable HS
- +  * s stop session
- +  * F force session (OTG-unfriendly)
- +  * E rElinquish bus (OTG)
- +  * H request host mode
- +  * h cancel host request
- +  * T start sending TEST_PACKET
- +  * D<num> set/query the debug level
- +  */
- + static int musb_proc_write(struct file *file, const char __user *buffer,
- + 			unsigned long count, void *data)
- + {
- + 	char cmd;
- + 	u8 reg;
- + 	struct musb *musb = (struct musb *)data;
- + 	void __iomem *mbase = musb->mregs;
- + 
- + 	/* MOD_INC_USE_COUNT; */
- + 
- + 	if (unlikely(copy_from_user(&cmd, buffer, 1)))
- + 		return -EFAULT;
- + 
- + 	switch (cmd) {
- + 	case 'S':
- + 		if (mbase) {
- + 			reg = musb_readb(mbase, MUSB_POWER)
- + 					| MUSB_POWER_SUSPENDM;
- + 			musb_writeb(mbase, MUSB_POWER, reg);
- + 		}
- + 		break;
- + 
- + 	case 'C':
- + 		if (mbase) {
- + 			reg = musb_readb(mbase, MUSB_POWER)
- + 					| MUSB_POWER_SOFTCONN;
- + 			musb_writeb(mbase, MUSB_POWER, reg);
- + 		}
- + 		break;
- + 
- + 	case 'c':
- + 		if (mbase) {
- + 			reg = musb_readb(mbase, MUSB_POWER)
- + 					& ~MUSB_POWER_SOFTCONN;
- + 			musb_writeb(mbase, MUSB_POWER, reg);
- + 		}
- + 		break;
- + 
- + 	case 'I':
- + 		if (mbase) {
- + 			reg = musb_readb(mbase, MUSB_POWER)
- + 					| MUSB_POWER_HSENAB;
- + 			musb_writeb(mbase, MUSB_POWER, reg);
- + 		}
- + 		break;
- + 
- + 	case 'i':
- + 		if (mbase) {
- + 			reg = musb_readb(mbase, MUSB_POWER)
- + 					& ~MUSB_POWER_HSENAB;
- + 			musb_writeb(mbase, MUSB_POWER, reg);
- + 		}
- + 		break;
- + 
- + 	case 'F':
- + 		reg = musb_readb(mbase, MUSB_DEVCTL);
- + 		reg |= MUSB_DEVCTL_SESSION;
- + 		musb_writeb(mbase, MUSB_DEVCTL, reg);
- + 		break;
- + 
- + 	case 'H':
- + 		if (mbase) {
- + 			reg = musb_readb(mbase, MUSB_DEVCTL);
- + 			reg |= MUSB_DEVCTL_HR;
- + 			musb_writeb(mbase, MUSB_DEVCTL, reg);
- + 			/* MUSB_HST_MODE( ((struct musb*)data) ); */
- + 			/* WARNING("Host Mode\n"); */
- + 		}
- + 		break;
- + 
- + 	case 'h':
- + 		if (mbase) {
- + 			reg = musb_readb(mbase, MUSB_DEVCTL);
- + 			reg &= ~MUSB_DEVCTL_HR;
- + 			musb_writeb(mbase, MUSB_DEVCTL, reg);
- + 		}
- + 		break;
- + 
- + 	case 'T':
- + 		if (mbase) {
- + 			musb_load_testpacket(musb);
- + 			musb_writeb(mbase, MUSB_TESTMODE,
- + 					MUSB_TEST_PACKET);
- + 			musb_writew(musb->endpoints[0].regs,
- + 				MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
- + 			dev_dbg(musb->controller,
- + 				"musb:testmode sending test packet\n");
- + 		}
- + 		break;
- + 
- + 	case 'b':
- + 		/* generate software babble interrupt */
- + 		musb_simulate_babble_intr(musb);
- + 		break;
- + 
- + 	case 'K':
- + 		/* enable babble workaround */
- + 		musb->enable_babble_work = 1;
- + 		INFO("enabled babble workaround\n");
- + 		break;
- + 
- + 	case 'k':
- + 		/* disable babble workaround */
- + 		musb->enable_babble_work = 0;
- + 		INFO("disabled babble workaround\n");
- + 		break;
- + 
- + 	case '?':
- + 		INFO("?: you are seeing it\n");
- + 		INFO("S: suspend the usb bus\n");
- + 		INFO("C/c: soft connect enable/disable\n");
- + 		INFO("I/i: hispeed enable/disable\n");
- + 		INFO("F: force session start\n");
- + 		INFO("H: host mode\n");
- + 		INFO("T: start sending TEST_PACKET\n");
- + 		INFO("D: set/read dbug level\n");
- + 		INFO("K/k: enable/disable babble workaround\n");
- + 		INFO("b: generate software babble interrupt\n");
- + 		break;
- + 
- + 	default:
- + 		ERR("Command %c not implemented\n", cmd);
- + 		break;
- + 	}
- + 
- + 	musb_platform_try_idle(musb, 0);
- + 
- + 	return count;
- + }
- + 
- + static int musb_proc_read(char *page, char **start,
- + 			off_t off, int count, int *eof, void *data)
- + {
- + 	char *buffer = page;
- + 	int code = 0;
- + 	unsigned long	flags;
- + 	struct musb	*musb = data;
- + 	unsigned	epnum;
- + 
- + 	count -= off;
- + 	count -= 1;		/* for NUL at end */
- + 	if (count <= 0)
- + 		return -EINVAL;
- + 
- + 	spin_lock_irqsave(&musb->lock, flags);
- + 
- + 	code = dump_header_stats(musb, buffer);
- + 	if (code > 0) {
- + 		buffer += code;
- + 		count -= code;
- + 	}
- + 
- + 	/* generate the report for the end points */
- + 	/* REVISIT ... not unless something's connected! */
- + 	for (epnum = 0; count >= 0 && epnum < musb->nr_endpoints;
- + 			epnum++) {
- + 		code = dump_end_info(musb, epnum, buffer, count);
- + 		if (code > 0) {
- + 			buffer += code;
- + 			count -= code;
- + 		}
- + 	}
- + 
- + 	musb_platform_try_idle(musb, 0);
- + 
- + 	spin_unlock_irqrestore(&musb->lock, flags);
- + 	*eof = 1;
- + 
- + 	return buffer - page;
- + }
- + 
- + void musb_debug_delete(char *name, struct musb *musb)
- + {
- + 	if (musb->proc_entry)
- + 		remove_proc_entry(name, NULL);
- + }
- + 
- + struct proc_dir_entry *__devinit
- + musb_debug_create(char *name, struct musb *data)
- + {
- + 	struct proc_dir_entry	*pde;
- + 
- + 	/* FIXME convert everything to seq_file; then later, debugfs */
- + 
- + 	if (!name)
- + 		return NULL;
- + 
- + 	pde = create_proc_entry(name, S_IFREG | S_IRUGO | S_IWUSR, NULL);
- + 	data->proc_entry = pde;
- + 	if (pde) {
- + 		pde->data = data;
- + 		/* pde->owner = THIS_MODULE; */
- + 
- + 		pde->read_proc = musb_proc_read;
- + 		pde->write_proc = musb_proc_write;
- + 
- + 		pde->size = 0;
- + 
- + 		pr_debug("Registered /proc/%s\n", name);
- + 	} else {
- + 		pr_debug("Cannot create a valid proc file entry");
- + 	}
- + 
- + 	return pde;
- + }
- diff -crN linux-3.2.1_o/drivers/usb/musb/musb_regs.h linux-3.2.1/drivers/usb/musb/musb_regs.h
- *** linux-3.2.1_o/drivers/usb/musb/musb_regs.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/musb/musb_regs.h	2014-05-15 13:25:15.098844906 +0900
- ***************
- *** 202,207 ****
- --- 202,213 ----
-   #define MUSB_RXCSR_H_REQPKT		0x0020
-   #define MUSB_RXCSR_H_ERROR		0x0004
-   
- + /* MISC control register offs 0x61 */
- + #define MUSB_MISC_FORCE_TXIDLE		0x80
- + #define MUSB_MISC_SW_SESSION_CTRL	0x40
- + #define MUSB_MISC_STUCK_J		0x20
- + #define MUSB_MISC_RCV_DISABLE		0x04
- + 
-   /* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
-   #define MUSB_RXCSR_P_WZC_BITS	\
-   	(MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \
- ***************
- *** 234,251 ****
-   #define MUSB_TESTMODE		0x0F	/* 8 bit */
-   
-   /* Get offset for a given FIFO from musb->mregs */
- ! #if defined(CONFIG_USB_MUSB_TUSB6010) ||	\
- ! 	defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
- ! #define MUSB_FIFO_OFFSET(epnum)	(0x200 + ((epnum) * 0x20))
- ! #else
-   #define MUSB_FIFO_OFFSET(epnum)	(0x20 + ((epnum) * 4))
- - #endif
-   
-   /*
-    * Additional Control Registers
-    */
-   
-   #define MUSB_DEVCTL		0x60	/* 8 bit */
-   
-   /* These are always controlled through the INDEX register */
-   #define MUSB_TXFIFOSZ		0x62	/* 8-bit (see masks) */
- --- 240,254 ----
-   #define MUSB_TESTMODE		0x0F	/* 8 bit */
-   
-   /* Get offset for a given FIFO from musb->mregs */
- ! #define MUSB_TUSB_FIFO_OFFSET(epnum)	(0x200 + ((epnum) * 0x20))
-   #define MUSB_FIFO_OFFSET(epnum)	(0x20 + ((epnum) * 4))
-   
-   /*
-    * Additional Control Registers
-    */
-   
-   #define MUSB_DEVCTL		0x60	/* 8 bit */
- + #define MUSB_MISC		0x61	/* 8 bit babble control bits */
-   
-   /* These are always controlled through the INDEX register */
-   #define MUSB_TXFIFOSZ		0x62	/* 8-bit (see masks) */
- ***************
- *** 288,308 ****
-   #define MUSB_FIFOSIZE		0x0F
-   #define MUSB_CONFIGDATA		MUSB_FIFOSIZE	/* Re-used for EP0 */
-   
-   /* Offsets to endpoint registers in indexed model (using INDEX register) */
- ! #define MUSB_INDEXED_OFFSET(_epnum, _offset)	\
-   	(0x10 + (_offset))
-   
-   /* Offsets to endpoint registers in flat models */
- ! #define MUSB_FLAT_OFFSET(_epnum, _offset)	\
-   	(0x100 + (0x10*(_epnum)) + (_offset))
-   
- - #if defined(CONFIG_USB_MUSB_TUSB6010) ||	\
- - 	defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
- - /* TUSB6010 EP0 configuration register is special */
- - #define MUSB_TUSB_OFFSET(_epnum, _offset)	\
- - 	(0x10 + _offset)
-   #include "tusb6010.h"		/* Needed "only" for TUSB_EP0_CONF */
- - #endif
-   
-   #define MUSB_TXCSR_MODE			0x2000
-   
- --- 291,313 ----
-   #define MUSB_FIFOSIZE		0x0F
-   #define MUSB_CONFIGDATA		MUSB_FIFOSIZE	/* Re-used for EP0 */
-   
- + 
- + #if 0
-   /* Offsets to endpoint registers in indexed model (using INDEX register) */
- ! #define MUSB_INDEXED_OFFSET(_musb, _epnum, _offset)	\
-   	(0x10 + (_offset))
-   
-   /* Offsets to endpoint registers in flat models */
- ! #define MUSB_FLAT_OFFSET(_musb, _epnum, _offset)	\
-   	(0x100 + (0x10*(_epnum)) + (_offset))
- + #endif
- + 
- + #define MUSB_OFFSET(_musb, _epnum, _offset)	\
- + 	((_musb)->ops->flags & MUSB_GLUE_EP_ADDR_INDEXED_MAPPING ? \
- + 		(0x10 + (_offset)) : (0x100 + (0x10*(_epnum)) + (_offset)))
- + 
-   
-   #include "tusb6010.h"		/* Needed "only" for TUSB_EP0_CONF */
-   
-   #define MUSB_TXCSR_MODE			0x2000
-   
- ***************
- *** 506,516 ****
-   #define MUSB_TXCOUNT		0x28
-   
-   /* Offsets to endpoint registers in indexed model (using INDEX register) */
- ! #define MUSB_INDEXED_OFFSET(_epnum, _offset)	\
-   	(0x40 + (_offset))
-   
-   /* Offsets to endpoint registers in flat models */
- ! #define MUSB_FLAT_OFFSET(_epnum, _offset)	\
-   	(USB_OFFSET(USB_EP_NI0_TXMAXP) + (0x40 * (_epnum)) + (_offset))
-   
-   /* Not implemented - HW has separate Tx/Rx FIFO */
- --- 511,521 ----
-   #define MUSB_TXCOUNT		0x28
-   
-   /* Offsets to endpoint registers in indexed model (using INDEX register) */
- ! #define MUSB_INDEXED_OFFSET(_musb, _epnum, _offset)	\
-   	(0x40 + (_offset))
-   
-   /* Offsets to endpoint registers in flat models */
- ! #define MUSB_FLAT_OFFSET(_musb, _epnum, _offset)	\
-   	(USB_OFFSET(USB_EP_NI0_TXMAXP) + (0x40 * (_epnum)) + (_offset))
-   
-   /* Not implemented - HW has separate Tx/Rx FIFO */
- diff -crN linux-3.2.1_o/drivers/usb/musb/musb_virthub.c linux-3.2.1/drivers/usb/musb/musb_virthub.c
- *** linux-3.2.1_o/drivers/usb/musb/musb_virthub.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/musb/musb_virthub.c	2014-05-15 13:25:15.098844906 +0900
- ***************
- *** 82,98 ****
-   			musb->xceiv->state = OTG_STATE_A_SUSPEND;
-   			musb->is_active = is_otg_enabled(musb)
-   					&& musb->xceiv->host->b_hnp_enable;
- - 			if (musb->is_active)
- - 				mod_timer(&musb->otg_timer, jiffies
- - 					+ msecs_to_jiffies(
- - 						OTG_TIME_A_AIDL_BDIS));
-   			musb_platform_try_idle(musb, 0);
-   			break;
-   		case OTG_STATE_B_HOST:
- ! 			musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
- ! 			musb->is_active = is_otg_enabled(musb)
-   					&& musb->xceiv->host->b_hnp_enable;
- ! 			musb_platform_try_idle(musb, 0);
-   			break;
-   		default:
-   			dev_dbg(musb->controller, "bogus rh suspend? %s\n",
- --- 82,96 ----
-   			musb->xceiv->state = OTG_STATE_A_SUSPEND;
-   			musb->is_active = is_otg_enabled(musb)
-   					&& musb->xceiv->host->b_hnp_enable;
-   			musb_platform_try_idle(musb, 0);
-   			break;
-   		case OTG_STATE_B_HOST:
- ! 			if (is_otg_enabled(musb)) {
- ! 				musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
- ! 				musb->is_active = is_otg_enabled(musb)
-   					&& musb->xceiv->host->b_hnp_enable;
- ! 				musb_platform_try_idle(musb, 0);
- ! 			}
-   			break;
-   		default:
-   			dev_dbg(musb->controller, "bogus rh suspend? %s\n",
- ***************
- *** 116,122 ****
-   	u8		power;
-   	void __iomem	*mbase = musb->mregs;
-   
- ! 	if (musb->xceiv->state == OTG_STATE_B_IDLE) {
-   		dev_dbg(musb->controller, "HNP: Returning from HNP; no hub reset from b_idle\n");
-   		musb->port1_status &= ~USB_PORT_STAT_RESET;
-   		return;
- --- 114,120 ----
-   	u8		power;
-   	void __iomem	*mbase = musb->mregs;
-   
- ! 	if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE) {
-   		dev_dbg(musb->controller, "HNP: Returning from HNP; no hub reset from b_idle\n");
-   		musb->port1_status &= ~USB_PORT_STAT_RESET;
-   		return;
- ***************
- *** 186,200 ****
-   	musb->is_active = 0;
-   
-   	switch (musb->xceiv->state) {
- - 	case OTG_STATE_A_SUSPEND:
- - 		if (is_otg_enabled(musb)
- - 				&& musb->xceiv->host->b_hnp_enable) {
- - 			musb->xceiv->state = OTG_STATE_A_PERIPHERAL;
- - 			musb->g.is_a_peripheral = 1;
- - 			break;
- - 		}
- - 		/* FALLTHROUGH */
-   	case OTG_STATE_A_HOST:
-   		musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
-   		musb->is_active = 0;
-   		break;
- --- 184,191 ----
-   	musb->is_active = 0;
-   
-   	switch (musb->xceiv->state) {
-   	case OTG_STATE_A_HOST:
- + 	case OTG_STATE_A_SUSPEND:
-   		musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
-   		musb->is_active = 0;
-   		break;
- ***************
- *** 414,419 ****
- --- 405,414 ----
-   				goto error;
-   			}
-   			musb_writeb(musb->mregs, MUSB_TESTMODE, temp);
- + 			if (wIndex == 4) {
- + 				musb_writew(musb->endpoints[0].regs,
- + 					MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
- + 			}
-   			break;
-   		default:
-   			goto error;
- diff -crN linux-3.2.1_o/drivers/usb/musb/omap2430.c linux-3.2.1/drivers/usb/musb/omap2430.c
- *** linux-3.2.1_o/drivers/usb/musb/omap2430.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/musb/omap2430.c	2014-05-15 13:25:15.098844906 +0900
- ***************
- *** 29,35 ****
-   #include <linux/sched.h>
-   #include <linux/init.h>
-   #include <linux/list.h>
- - #include <linux/clk.h>
-   #include <linux/io.h>
-   #include <linux/platform_device.h>
-   #include <linux/dma-mapping.h>
- --- 29,34 ----
- ***************
- *** 96,101 ****
- --- 95,101 ----
-   	spin_unlock_irqrestore(&musb->lock, flags);
-   }
-   
- + #define MUSB_TIMEOUT_A_WAIT_BCON	1100
-   
-   static void omap2430_musb_try_idle(struct musb *musb, unsigned long timeout)
-   {
- ***************
- *** 228,248 ****
-   		unsigned long event, void *unused)
-   {
-   	struct musb	*musb = container_of(nb, struct musb, nb);
-   	struct device *dev = musb->controller;
-   	struct musb_hdrc_platform_data *pdata = dev->platform_data;
-   	struct omap_musb_board_data *data = pdata->board_data;
-   
- ! 	switch (event) {
-   	case USB_EVENT_ID:
-   		dev_dbg(musb->controller, "ID GND\n");
-   
- ! 		if (is_otg_enabled(musb)) {
- ! 			if (musb->gadget_driver) {
- ! 				pm_runtime_get_sync(musb->controller);
- ! 				otg_init(musb->xceiv);
- ! 				omap2430_musb_set_vbus(musb, 1);
- ! 			}
- ! 		} else {
-   			pm_runtime_get_sync(musb->controller);
-   			otg_init(musb->xceiv);
-   			omap2430_musb_set_vbus(musb, 1);
- --- 228,252 ----
-   		unsigned long event, void *unused)
-   {
-   	struct musb	*musb = container_of(nb, struct musb, nb);
- + 
- + 	musb->xceiv_event = event;
- + 	schedule_work(&musb->otg_notifier_work);
- + 
- + 	return 0;
- + }
- + 
- + static void musb_otg_notifier_work(struct work_struct *data_notifier_work)
- + {
- + 	struct musb *musb = container_of(data_notifier_work, struct musb, otg_notifier_work);
-   	struct device *dev = musb->controller;
-   	struct musb_hdrc_platform_data *pdata = dev->platform_data;
-   	struct omap_musb_board_data *data = pdata->board_data;
-   
- ! 	switch (musb->xceiv_event) {
-   	case USB_EVENT_ID:
-   		dev_dbg(musb->controller, "ID GND\n");
-   
- ! 		if (!is_otg_enabled(musb) || musb->gadget_driver) {
-   			pm_runtime_get_sync(musb->controller);
-   			otg_init(musb->xceiv);
-   			omap2430_musb_set_vbus(musb, 1);
- ***************
- *** 274,283 ****
-   		break;
-   	default:
-   		dev_dbg(musb->controller, "ID float\n");
- - 		return NOTIFY_DONE;
-   	}
- - 
- - 	return NOTIFY_OK;
-   }
-   
-   static int omap2430_musb_init(struct musb *musb)
- --- 278,284 ----
- ***************
- *** 291,302 ****
-   	 * up through ULPI.  TWL4030-family PMICs include one,
-   	 * which needs a driver, drivers aren't always needed.
-   	 */
- ! 	musb->xceiv = otg_get_transceiver();
-   	if (!musb->xceiv) {
-   		pr_err("HS USB OTG: no transceiver configured\n");
-   		return -ENODEV;
-   	}
-   
-   	status = pm_runtime_get_sync(dev);
-   	if (status < 0) {
-   		dev_err(dev, "pm_runtime_get_sync FAILED");
- --- 292,305 ----
-   	 * up through ULPI.  TWL4030-family PMICs include one,
-   	 * which needs a driver, drivers aren't always needed.
-   	 */
- ! 	musb->xceiv = otg_get_transceiver(musb->id);
-   	if (!musb->xceiv) {
-   		pr_err("HS USB OTG: no transceiver configured\n");
-   		return -ENODEV;
-   	}
-   
- + 	INIT_WORK(&musb->otg_notifier_work, musb_otg_notifier_work);
- + 
-   	status = pm_runtime_get_sync(dev);
-   	if (status < 0) {
-   		dev_err(dev, "pm_runtime_get_sync FAILED");
- ***************
- *** 329,340 ****
-   	if (status)
-   		dev_dbg(musb->controller, "notification register failed\n");
-   
-   	setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
-   
-   	return 0;
-   
-   err1:
- - 	pm_runtime_disable(dev);
-   	return status;
-   }
-   
- --- 332,343 ----
-   	if (status)
-   		dev_dbg(musb->controller, "notification register failed\n");
-   
- + 	musb->a_wait_bcon = MUSB_TIMEOUT_A_WAIT_BCON;
-   	setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
-   
-   	return 0;
-   
-   err1:
-   	return status;
-   }
-   
- ***************
- *** 350,369 ****
-   
-   	case USB_EVENT_ID:
-   		otg_init(musb->xceiv);
- ! 		if (data->interface_type == MUSB_INTERFACE_UTMI) {
- ! 			devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
- ! 			/* start the session */
- ! 			devctl |= MUSB_DEVCTL_SESSION;
- ! 			musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
- ! 			while (musb_readb(musb->mregs, MUSB_DEVCTL) &
- ! 						MUSB_DEVCTL_BDEVICE) {
- ! 				cpu_relax();
- ! 
- ! 				if (time_after(jiffies, timeout)) {
- ! 					dev_err(musb->controller,
- ! 					"configured as A device timeout");
- ! 					break;
- ! 				}
-   			}
-   		}
-   		break;
- --- 353,371 ----
-   
-   	case USB_EVENT_ID:
-   		otg_init(musb->xceiv);
- ! 		if (data->interface_type != MUSB_INTERFACE_UTMI)
- ! 			break;
- ! 		devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
- ! 		/* start the session */
- ! 		devctl |= MUSB_DEVCTL_SESSION;
- ! 		musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
- ! 		while (musb_readb(musb->mregs, MUSB_DEVCTL) &
- ! 				MUSB_DEVCTL_BDEVICE) {
- ! 			cpu_relax();
- ! 
- ! 			if (time_after(jiffies, timeout)) {
- ! 				dev_err(dev, "configured as A device timeout");
- ! 				break;
-   			}
-   		}
-   		break;
- ***************
- *** 394,402 ****
- --- 396,410 ----
-   }
-   
-   static const struct musb_platform_ops omap2430_ops = {
- + 	.fifo_mode	= 4,
- + 	.flags		= MUSB_GLUE_EP_ADDR_FLAT_MAPPING |
- + 				MUSB_GLUE_DMA_INVENTRA,
-   	.init		= omap2430_musb_init,
-   	.exit		= omap2430_musb_exit,
-   
- + 	.read_fifo      = musb_read_fifo,
- + 	.write_fifo     = musb_write_fifo,
- + 
-   	.set_mode	= omap2430_musb_set_mode,
-   	.try_idle	= omap2430_musb_try_idle,
-   
- ***************
- *** 404,409 ****
- --- 412,420 ----
-   
-   	.enable		= omap2430_musb_enable,
-   	.disable	= omap2430_musb_disable,
- + 
- + 	.dma_controller_create = inventra_dma_controller_create,
- + 	.dma_controller_destroy = inventra_dma_controller_destroy,
-   };
-   
-   static u64 omap2430_dmamask = DMA_BIT_MASK(32);
- ***************
- *** 421,432 ****
-   		goto err0;
-   	}
-   
- ! 	musb = platform_device_alloc("musb-hdrc", -1);
-   	if (!musb) {
-   		dev_err(&pdev->dev, "failed to allocate musb device\n");
-   		goto err1;
-   	}
-   
-   	musb->dev.parent		= &pdev->dev;
-   	musb->dev.dma_mask		= &omap2430_dmamask;
-   	musb->dev.coherent_dma_mask	= omap2430_dmamask;
- --- 432,444 ----
-   		goto err0;
-   	}
-   
- ! 	musb = platform_device_alloc("musb-hdrc", pdev->id);
-   	if (!musb) {
-   		dev_err(&pdev->dev, "failed to allocate musb device\n");
-   		goto err1;
-   	}
-   
- + 	ev_set_name(&pdev->dev, "musb-omap2430");
-   	musb->dev.parent		= &pdev->dev;
-   	musb->dev.dma_mask		= &omap2430_dmamask;
-   	musb->dev.coherent_dma_mask	= omap2430_dmamask;
- ***************
- *** 478,484 ****
-   	platform_device_del(glue->musb);
-   	platform_device_put(glue->musb);
-   	pm_runtime_put(&pdev->dev);
- - 	pm_runtime_disable(&pdev->dev);
-   	kfree(glue);
-   
-   	return 0;
- --- 490,495 ----
- ***************
- *** 491,496 ****
- --- 502,510 ----
-   	struct omap2430_glue		*glue = dev_get_drvdata(dev);
-   	struct musb			*musb = glue_to_musb(glue);
-   
- + 	musb->context.otg_interfsel = musb_readl(musb->mregs,
- + 						OTG_INTERFSEL);
- + 
-   	omap2430_low_level_exit(musb);
-   	otg_set_suspend(musb->xceiv, 1);
-   
- ***************
- *** 503,508 ****
- --- 517,525 ----
-   	struct musb			*musb = glue_to_musb(glue);
-   
-   	omap2430_low_level_init(musb);
- + 	musb_writel(musb->mregs, OTG_INTERFSEL,
- + 					musb->context.otg_interfsel);
- + 
-   	otg_set_suspend(musb->xceiv, 0);
-   
-   	return 0;
- diff -crN linux-3.2.1_o/drivers/usb/musb/ti81xx.c linux-3.2.1/drivers/usb/musb/ti81xx.c
- *** linux-3.2.1_o/drivers/usb/musb/ti81xx.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/drivers/usb/musb/ti81xx.c	2014-05-15 13:25:15.102588763 +0900
- ***************
- *** 0 ****
- --- 1,1884 ----
- + /*
- +  * Texas Instruments TI81XX "usb platform glue layer"
- +  *
- +  * Copyright (c) 2008, MontaVista Software, Inc. <source@mvista.com>
- +  *
- +  * Based on the DaVinci "glue layer" code.
- +  * Copyright (C) 2005-2006 by Texas Instruments
- +  *
- +  * This file is part of the Inventra Controller Driver for Linux.
- +  *
- +  * The Inventra Controller Driver for Linux is free software; you
- +  * can redistribute it and/or modify it under the terms of the GNU
- +  * General Public License version 2 as published by the Free Software
- +  * Foundation.
- +  *
- +  * The Inventra Controller Driver for Linux is distributed in
- +  * the hope that it will be useful, but WITHOUT ANY WARRANTY;
- +  * without even the implied warranty of MERCHANTABILITY or
- +  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
- +  * License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with The Inventra Controller Driver for Linux ; if not,
- +  * write to the Free Software Foundation, Inc., 59 Temple Place,
- +  * Suite 330, Boston, MA  02111-1307  USA
- +  *
- +  */
- + 
- + #include <linux/init.h>
- + #include <linux/io.h>
- + #include <linux/usb/otg.h>
- + #include <linux/platform_device.h>
- + #include <linux/dma-mapping.h>
- + #include <linux/module.h>
- + 
- + #include "cppi41.h"
- + #include "ti81xx.h"
- + 
- + #include "musb_core.h"
- + #include "cppi41_dma.h"
- + 
- + #ifdef CONFIG_PM
- + struct ti81xx_usbss_regs {
- + 	u32	sysconfig;
- + 
- + 	u32	irq_en_set;
- + 
- + #ifdef CONFIG_USB_TI_CPPI41_DMA
- + 	u32	irq_dma_th_tx0[4];
- + 	u32	irq_dma_th_rx0[4];
- + 	u32	irq_dma_th_tx1[4];
- + 	u32	irq_dma_th_rx1[4];
- + 	u32	irq_dma_en[2];
- + 
- + 	u32	irq_frame_th_tx0[4];
- + 	u32	irq_frame_th_rx0[4];
- + 	u32	irq_frame_th_tx1[4];
- + 	u32	irq_frame_th_rx1[4];
- + 	u32	irq_frame_en[2];
- + #endif
- + };
- + 
- + struct ti81xx_usb_regs {
- + 	u32	control;
- + 
- + 	u32	irq_en_set[2];
- + 
- + #ifdef CONFIG_USB_TI_CPPI41_DMA
- + 	u32	tx_mode;
- + 	u32	rx_mode;
- + 	u32	grndis_size[15];
- + 	u32	auto_req;
- + 	u32	teardn;
- + 	u32	th_xdma_idle;
- + #endif
- + 	u32	srp_fix;
- + 	u32	phy_utmi;
- + 	u32	mgc_utmi_loopback;
- + 	u32	mode;
- + };
- + #endif
- + 
- + #define BABBLE_WORKAROUND_1 0
- + #define BABBLE_WORKAROUND_2 1
- + #define BABBLE_WORKAROUND_3 2
- + 
- + #define BABBLE_WORKAROUND (BABBLE_WORKAROUND_2)
- + 
- + struct ti81xx_glue {
- + 	struct device *dev;
- + 	struct resource *mem_pa;	/* usbss memory resource */
- + 	void *mem_va;			/* ioremapped virtual address */
- + 	struct platform_device *musb[2];/* child musb pdevs */
- + 	u8	irq;			/* usbss irq */
- + 	u8	first;			/* ignore first call of resume */
- + 
- + #ifdef CONFIG_PM
- + 	struct ti81xx_usbss_regs usbss_regs;
- + 	struct ti81xx_usb_regs usb_regs[2];
- + #endif
- + };
- + 
- + static u64 musb_dmamask = DMA_BIT_MASK(32);
- + static void *usbss_virt_base;
- + static u8 usbss_init_done;
- + struct musb *gmusb[2];
- + 
- + u8 usbid_sw_ctrl;
- + #undef USB_TI81XX_DEBUG
- + 
- + #ifdef USB_TI81XX_DEBUG
- + #define	dprintk(x, ...) printk(x, ## __VA_ARGS__)
- + #else
- + #define dprintk(x, ...)
- + #endif
- + 
- + #ifdef CONFIG_USB_TI_CPPI41_DMA
- + static irqreturn_t cppi41dma_Interrupt(int irq, void *hci);
- + static u8 cppi41_init_done;
- + static void *cppi41_dma_base;
- + #define CPPI41_ADDR(offs) ((void *)((u32)cppi41_dma_base + (offs - 0x2000)))
- + #endif
- + 
- + extern void omap_ctrl_writel(u32 val, u16 offset);
- + extern u32 omap_ctrl_readl(u16 offset);
- + 
- + static inline u32 usbss_read(u32 offset)
- + {
- + 	if (!usbss_init_done)
- + 		return 0;
- + 	return readl(usbss_virt_base + offset);
- + }
- + 
- + static inline void usbss_write(u32 offset, u32 data)
- + {
- + 	if (!usbss_init_done)
- + 		return ;
- + 	writel(data, usbss_virt_base + offset);
- + }
- + 
- + static void usbotg_ss_init(void)
- + {
- + 	if (!usbss_init_done) {
- + 		usbss_init_done = 1;
- + 
- + 		/* clear any USBSS interrupts */
- + 		usbss_write(USBSS_IRQ_EOI, 0);
- + 		usbss_write(USBSS_IRQ_STATUS, usbss_read(USBSS_IRQ_STATUS));
- + 	}
- + }
- + static void usbotg_ss_uninit(void)
- + {
- + 	if (usbss_init_done) {
- + 		usbss_init_done = 0;
- + 		usbss_virt_base = 0;
- + 	}
- + }
- + void set_frame_threshold(struct musb *musb, u8 is_tx, u8 epnum, u8 value, u8 en_intr)
- + {
- + 	u32     base, reg_val, frame_intr = 0, frame_base = 0;
- + 	u32     offs = epnum/4*4;
- + 	u8      indx = (epnum % 4) * 8;
- + 
- + 	if (is_tx)
- + 		base = musb->id ? USBSS_IRQ_FRAME_THRESHOLD_TX1 :
- + 				USBSS_IRQ_FRAME_THRESHOLD_TX0;
- + 	else
- + 		base = musb->id ? USBSS_IRQ_FRAME_THRESHOLD_RX1 :
- + 				USBSS_IRQ_FRAME_THRESHOLD_RX0;
- + 
- + 	reg_val = usbss_read(base + offs);
- + 	reg_val &= ~(0xFF << indx);
- + 	reg_val |= (value << indx);
- + 	usbss_write(base + offs, reg_val);
- + 
- + 	if (en_intr) {
- + 		frame_base = musb->id ? USBSS_IRQ_FRAME_ENABLE_1 :
- + 			USBSS_IRQ_FRAME_ENABLE_0;
- + 		frame_intr = musb->id ? usbss_read(USBSS_IRQ_FRAME_ENABLE_0) :
- + 			usbss_read(USBSS_IRQ_FRAME_ENABLE_1);
- + 		frame_intr |= is_tx ? (1 << epnum) : (1 << (16 + epnum));
- + 		usbss_write(frame_base, frame_intr);
- + 		dev_dbg(musb->controller, "%s: framebase=%x, frame_intr=%x\n",
- + 			is_tx ? "tx" : "rx", frame_base, frame_intr);
- + 	}
- + }
- + 
- + void set_dma_threshold(struct musb *musb, u8 is_tx, u8 epnum, u8 value)
- + {
- + 	u32     base, reg_val;
- + 	u32     offs = epnum/4*4;
- + 	u8      indx = (epnum % 4) * 8;
- + 
- + 	if (musb->id == 0)
- + 		base = is_tx ? USBSS_IRQ_DMA_THRESHOLD_TX0 :
- + 				USBSS_IRQ_DMA_THRESHOLD_RX0;
- + 	else
- + 		base = is_tx ? USBSS_IRQ_DMA_THRESHOLD_TX1 :
- + 				USBSS_IRQ_DMA_THRESHOLD_RX1;
- + 
- + 	reg_val = usbss_read(base + offs);
- + 	reg_val &= ~(0xFF << indx);
- + 	reg_val |= (value << indx);
- + 	dev_dbg(musb->controller, "base=%x, offs=%x, indx=%d, reg_val = (%x)%x\n",
- + 		base, offs, indx, reg_val, usbss_read(base + offs));
- + 	usbss_write(base + offs, reg_val);
- + }
- + 
- + /* ti81xx specific read/write functions */
- + u16 ti81xx_musb_readw(const void __iomem *addr, unsigned offset)
- + {
- + 	u32 tmp;
- + 	u16 val;
- + 
- + 	tmp = readl(addr + (offset & ~3));
- + 
- + 	switch (offset & 0x3) {
- + 	case 0:
- + 		val = (tmp & 0xffff);
- + 		break;
- + 	case 1:
- + 		val = (tmp >> 8) & 0xffff;
- + 		break;
- + 	case 2:
- + 	case 3:
- + 	default:
- + 		val = (tmp >> 16) & 0xffff;
- + 		break;
- + 	}
- + 	return val;
- + }
- + 
- + void ti81xx_musb_writew(void __iomem *addr, unsigned offset, u16 data)
- + {
- + 	__raw_writew(data, addr + offset);
- + }
- + 
- + u8 ti81xx_musb_readb(const void __iomem *addr, unsigned offset)
- + {
- + 	u32 tmp;
- + 	u8 val;
- + 
- + 	tmp = readl(addr + (offset & ~3));
- + 
- + 	switch (offset & 0x3) {
- + 	case 0:
- + 		val = tmp & 0xff;
- + 		break;
- + 	case 1:
- + 		val = (tmp >> 8);
- + 		break;
- + 	case 2:
- + 		val = (tmp >> 16);
- + 		break;
- + 	case 3:
- + 	default:
- + 		val = (tmp >> 24);
- + 		break;
- + 	}
- + 	return val;
- + }
- + void ti81xx_musb_writeb(void __iomem *addr, unsigned offset, u8 data)
- + {
- + 	__raw_writeb(data, addr + offset);
- + }
- + 
- + #ifdef CONFIG_USB_TI_CPPI41_DMA
- + /*
- +  * CPPI 4.1 resources used for USB OTG controller module:
- +  *
- +  tx/rx completion queues for usb0 */
- + static u16 tx_comp_q[] = {93, 94, 95, 96, 97,
- + 				98, 99, 100, 101, 102,
- + 				103, 104, 105, 106, 107 };
- + 
- + static u16 rx_comp_q[] = {109, 110, 111, 112, 113,
- + 				114, 115, 116, 117, 118,
- + 				119, 120, 121, 122, 123 };
- + 
- + /* tx/rx completion queues for usb1 */
- + static u16 tx_comp_q1[] = {125, 126, 127, 128, 129,
- + 				 130, 131, 132, 133, 134,
- + 				 135, 136, 137, 138, 139 };
- + 
- + static u16 rx_comp_q1[] = {141, 142, 143, 144, 145,
- + 				 146, 147, 148, 149, 150,
- + 				 151, 152, 153, 154, 155 };
- + 
- + /* Fair scheduling */
- + u32 dma_sched_table[] = {
- + 	0x81018000, 0x83038202, 0x85058404, 0x87078606,
- + 	0x89098808, 0x8b0b8a0a, 0x8d0d8c0c, 0x8f0f8e0e,
- + 	0x91119010, 0x93139212, 0x95159414, 0x97179616,
- + 	0x99199818, 0x9b1b9a1a, 0x9d1d9c1c, 0x00009e1e,
- + };
- + 
- + /* cppi41 dma tx channel info */
- + static const struct cppi41_tx_ch tx_ch_info[] = {
- + 	[0] = {
- + 		.port_num	= 1,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 32} , {0, 33} }
- + 	},
- + 	[1] = {
- + 		.port_num	= 2,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 34} , {0, 35} }
- + 	},
- + 	[2] = {
- + 		.port_num	= 3,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 36} , {0, 37} }
- + 	},
- + 	[3] = {
- + 		.port_num	= 4,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 38} , {0, 39} }
- + 	},
- + 	[4] = {
- + 		.port_num	= 5,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 40} , {0, 41} }
- + 	},
- + 	[5] = {
- + 		.port_num	= 6,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 42} , {0, 43} }
- + 	},
- + 	[6] = {
- + 		.port_num	= 7,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 44} , {0, 45} }
- + 	},
- + 	[7] = {
- + 		.port_num	= 8,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 46} , {0, 47} }
- + 	},
- + 	[8] = {
- + 		.port_num	= 9,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 48} , {0, 49} }
- + 	},
- + 	[9] = {
- + 		.port_num	= 10,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 50} , {0, 51} }
- + 	},
- + 	[10] = {
- + 		.port_num	= 11,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 52} , {0, 53} }
- + 	},
- + 	[11] = {
- + 		.port_num	= 12,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 54} , {0, 55} }
- + 	},
- + 	[12] = {
- + 		.port_num	= 13,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 56} , {0, 57} }
- + 	},
- + 	[13] = {
- + 		.port_num	= 14,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 58} , {0, 59} }
- + 	},
- + 	[14] = {
- + 		.port_num	= 15,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 60} , {0, 61} }
- + 	},
- + 	[15] = {
- + 		.port_num	= 1,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 62} , {0, 63} }
- + 	},
- + 	[16] = {
- + 		.port_num	= 2,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 64} , {0, 65} }
- + 	},
- + 	[17] = {
- + 		.port_num	= 3,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 66} , {0, 67} }
- + 	},
- + 	[18] = {
- + 		.port_num	= 4,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 68} , {0, 69} }
- + 	},
- + 	[19] = {
- + 		.port_num	= 5,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 70} , {0, 71} }
- + 	},
- + 	[20] = {
- + 		.port_num	= 6,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 72} , {0, 73} }
- + 	},
- + 	[21] = {
- + 		.port_num	= 7,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 74} , {0, 75} }
- + 	},
- + 	[22] = {
- + 		.port_num	= 8,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 76} , {0, 77} }
- + 	},
- + 	[23] = {
- + 		.port_num	= 9,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 78} , {0, 79} }
- + 	},
- + 	[24] = {
- + 		.port_num	= 10,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 80} , {0, 81} }
- + 	},
- + 	[25] = {
- + 		.port_num	= 11,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 82} , {0, 83} }
- + 	},
- + 	[26] = {
- + 		.port_num	= 12,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 84} , {0, 85} }
- + 	},
- + 	[27] = {
- + 		.port_num	= 13,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 86} , {0, 87} }
- + 	},
- + 	[28] = {
- + 		.port_num	= 14,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 88} , {0, 89} }
- + 	},
- + 	[29] = {
- + 		.port_num	= 15,
- + 		.num_tx_queue	= 2,
- + 		.tx_queue	= { {0, 90} , {0, 91} }
- + 	}
- + };
- + 
- + /* Queues 0 to 66 are pre-assigned, others are spare */
- + static const u32 assigned_queues[] = {	0xffffffff, /* queue 0..31 */
- + 					0xffffffff, /* queue 32..63 */
- + 					0xffffffff, /* queue 64..95 */
- + 					0xffffffff, /* queue 96..127 */
- + 					0x0fffffff  /* queue 128..155 */
- + 					};
- + 
- + int __devinit cppi41_init(u8 id, u8 irq, int num_instances)
- + {
- + 	struct usb_cppi41_info *cppi_info = &usb_cppi41_info[id];
- + 	u16 numch, blknum, order;
- + 	u32 i;
- + 
- + 	/* init cppi info structure  */
- + 	cppi_info->dma_block = 0;
- + 	for (i = 0 ; i < USB_CPPI41_NUM_CH ; i++)
- + 		cppi_info->ep_dma_ch[i] = i + (15 * id);
- + 
- + 	cppi_info->q_mgr = 0;
- + 	cppi_info->num_tx_comp_q = 15;
- + 	cppi_info->num_rx_comp_q = 15;
- + 	cppi_info->tx_comp_q = id ? tx_comp_q1 : tx_comp_q;
- + 	cppi_info->rx_comp_q = id ? rx_comp_q1 : rx_comp_q;
- + 	cppi_info->bd_intr_ctrl = 1;
- + 	cppi_info->version = usbss_read(USBSS_REVISION);
- + 
- + 	if (cppi41_init_done)
- + 		return 0;
- + 
- + 	blknum = cppi_info->dma_block;
- + 
- + 	/* Queue manager information */
- + 	cppi41_queue_mgr[0].num_queue = 159;
- + 	cppi41_queue_mgr[0].queue_types = CPPI41_FREE_DESC_BUF_QUEUE |
- + 						CPPI41_UNASSIGNED_QUEUE;
- + 	cppi41_queue_mgr[0].base_fdbq_num = 0;
- + 	cppi41_queue_mgr[0].assigned = assigned_queues;
- + 
- + 	/* init DMA block */
- + 	cppi41_dma_block[0].num_tx_ch = 30;
- + 	cppi41_dma_block[0].num_rx_ch = 30;
- + 	cppi41_dma_block[0].tx_ch_info = tx_ch_info;
- + 
- + 	/* initilize cppi41 dma & Qmgr address */
- + 	cppi41_dma_base = ioremap(TI81XX_USB_CPPIDMA_BASE,
- + 					TI81XX_USB_CPPIDMA_LEN);
- + 
- + 	cppi41_queue_mgr[0].q_mgr_rgn_base = CPPI41_ADDR(QMGR_RGN_OFFS);
- + 	cppi41_queue_mgr[0].desc_mem_rgn_base = CPPI41_ADDR(QMRG_DESCRGN_OFFS);
- + 	cppi41_queue_mgr[0].q_mgmt_rgn_base = CPPI41_ADDR(QMGR_REG_OFFS);
- + 	cppi41_queue_mgr[0].q_stat_rgn_base = CPPI41_ADDR(QMGR_STAT_OFFS);
- + 	cppi41_dma_block[0].global_ctrl_base = CPPI41_ADDR(DMA_GLBCTRL_OFFS);
- + 	cppi41_dma_block[0].ch_ctrl_stat_base = CPPI41_ADDR(DMA_CHCTRL_OFFS);
- + 	cppi41_dma_block[0].sched_ctrl_base = CPPI41_ADDR(DMA_SCHED_OFFS);
- + 	cppi41_dma_block[0].sched_table_base = CPPI41_ADDR(DMA_SCHEDTBL_OFFS);
- + 
- + 	/* Initialize for Linking RAM region 0 alone */
- + 	cppi41_queue_mgr_init(cppi_info->q_mgr, 0, 0x3fff);
- + 
- + 	numch =  USB_CPPI41_NUM_CH * 2 * num_instances;
- + 	cppi41_dma_block[0].num_max_ch = numch;
- + 
- + 	order = get_count_order(numch);
- + 
- + 	/* TODO: check two teardown desc per channel (5 or 7 ?)*/
- + 	if (order < 5)
- + 		order = 5;
- + 
- + 	cppi41_dma_block_init(blknum, cppi_info->q_mgr, order,
- + 			dma_sched_table, numch);
- + 
- + 	/* attach to the IRQ */
- + 	if (request_irq(irq, cppi41dma_Interrupt, 0, "cppi41_dma", 0))
- + 		printk(KERN_INFO "request_irq %d failed!\n", irq);
- + 	else
- + 		printk(KERN_INFO "registerd cppi-dma Intr @ IRQ %d\n", irq);
- + 
- + 	cppi41_init_done = 1;
- + 
- + 	printk(KERN_INFO "Cppi41 Init Done Qmgr-base(%p) dma-base(%p)\n",
- + 		cppi41_queue_mgr[0].q_mgr_rgn_base,
- + 		cppi41_dma_block[0].global_ctrl_base);
- + 
- + 	/* enable all usbss the interrupts */
- + 	usbss_write(USBSS_IRQ_EOI, 0);
- + 	usbss_write(USBSS_IRQ_ENABLE_SET, USBSS_INTR_FLAGS);
- + 	usbss_write(USBSS_IRQ_DMA_ENABLE_0, 0xFFFeFFFe);
- + 
- + 	printk(KERN_INFO "Cppi41 Init Done\n");
- + 
- + 	return 0;
- + }
- + 
- + void cppi41_free(void)
- + {
- + 	u32 numch, blknum, order;
- + 	struct usb_cppi41_info *cppi_info = &usb_cppi41_info[0];
- + 
- + 	if (!cppi41_init_done)
- + 		return ;
- + 
- + 	numch = cppi41_dma_block[0].num_max_ch;
- + 	order = get_count_order(numch);
- + 	blknum = cppi_info->dma_block;
- + 
- + 	cppi41_dma_block_uninit(blknum, cppi_info->q_mgr, order,
- + 			dma_sched_table, numch);
- + 	cppi41_queue_mgr_uninit(cppi_info->q_mgr);
- + 
- + 	iounmap(cppi41_dma_base);
- + 	cppi41_dma_base = 0;
- + 	cppi41_init_done = 0;
- + }
- + 
- + int cppi41_disable_sched_rx(void)
- + {
- + 	cppi41_dma_sched_tbl_init(0, 0, dma_sched_table, 30);
- + 	return 0;
- + }
- + 
- + int cppi41_enable_sched_rx(void)
- + {
- + 	cppi41_dma_sched_tbl_init(0, 0, dma_sched_table, 30);
- + 	return 0;
- + }
- + 
- + /*
- +  * Because we don't set CTRL.UINT, it's "important" to:
- +  *	- not read/write INTRUSB/INTRUSBE (except during
- +  *	  initial setup, as a workaround);
- +  *	- use INTSET/INTCLR instead.
- +  */
- + 
- + void txfifoempty_intr_enable(struct musb *musb, u8 ep_num)
- + {
- + 	void __iomem *reg_base = musb->ctrl_base;
- + 	u32 coremask;
- + 
- + 	if (musb->txfifo_intr_enable) {
- + 		coremask = musb_readl(reg_base, USB_CORE_INTR_SET_REG);
- + 		coremask |= (1 << (ep_num + 16));
- + 		musb_writel(reg_base, USB_CORE_INTR_SET_REG, coremask);
- + 		dev_dbg(musb->controller, "enable txF intr ep%d coremask %x\n",
- + 			ep_num, coremask);
- + 	}
- + }
- + 
- + void txfifoempty_intr_disable(struct musb *musb, u8 ep_num)
- + {
- + 	void __iomem *reg_base = musb->ctrl_base;
- + 	u32 coremask;
- + 
- + 	if (musb->txfifo_intr_enable) {
- + 		coremask = (1 << (ep_num + 16));
- + 		musb_writel(reg_base, USB_CORE_INTR_CLEAR_REG, coremask);
- + 	}
- + }
- + 
- + #endif /* CONFIG_USB_TI_CPPI41_DMA */
- + 
- + void ti81xx_musb_enable_sof(struct musb *musb)
- + {
- + 	void __iomem *reg_base = musb->ctrl_base;
- + 
- + 	musb->sof_enabled = 1;
- + 	musb_writeb(musb->mregs, MUSB_INTRUSBE, MUSB_INTR_SOF |
- + 		musb_readb(musb->mregs, MUSB_INTRUSBE));
- + 	musb_writel(reg_base, USB_CORE_INTR_SET_REG, MUSB_INTR_SOF |
- + 		musb_readl(reg_base, USB_CORE_INTR_SET_REG));
- + }
- + 
- + void ti81xx_musb_disable_sof(struct musb *musb)
- + {
- + 	void __iomem *reg_base = musb->ctrl_base;
- + 	u8 intrusb;
- + 
- + 	intrusb = musb_readb(musb->mregs, MUSB_INTRUSBE);
- + 	intrusb &= ~MUSB_INTR_SOF;
- + 	musb_writeb(musb->mregs, MUSB_INTRUSBE, intrusb);
- + 	musb_writel(reg_base, USB_CORE_INTR_CLEAR_REG, MUSB_INTR_SOF);
- + 	musb->sof_enabled = 0;
- + }
- + 
- + /**
- +  * ti81xx_musb_enable - enable interrupts
- +  */
- + void ti81xx_musb_enable(struct musb *musb)
- + {
- + 	void __iomem *reg_base = musb->ctrl_base;
- + 	u32 epmask, coremask;
- + 
- + 	/* Workaround: setup IRQs through both register sets. */
- + 	epmask = ((musb->epmask & USB_TX_EP_MASK) << USB_INTR_TX_SHIFT) |
- + 	       ((musb->epmask & USB_RX_EP_MASK) << USB_INTR_RX_SHIFT);
- + 	coremask = (0x01ff << USB_INTR_USB_SHIFT);
- + 
- + 	coremask &= ~MUSB_INTR_SOF;
- + 
- + 	musb_writel(reg_base, USB_EP_INTR_SET_REG, epmask);
- + 	musb_writel(reg_base, USB_CORE_INTR_SET_REG, coremask);
- + 	/* Force the DRVVBUS IRQ so we can start polling for ID change. */
- + 	if (is_otg_enabled(musb))
- + 		musb_writel(reg_base, USB_CORE_INTR_SET_REG,
- + 			    USB_INTR_DRVVBUS << USB_INTR_USB_SHIFT);
- + }
- + 
- + /**
- +  * ti81xx_musb_disable - disable HDRC and flush interrupts
- +  */
- + void ti81xx_musb_disable(struct musb *musb)
- + {
- + 	void __iomem *reg_base = musb->ctrl_base;
- + 
- + 	musb_writel(reg_base, USB_CORE_INTR_CLEAR_REG, USB_INTR_USB_MASK);
- + 	musb_writel(reg_base, USB_EP_INTR_CLEAR_REG,
- + 			 USB_TX_INTR_MASK | USB_RX_INTR_MASK);
- + 	musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
- + 	musb_writel(reg_base, USB_IRQ_EOI, 0);
- + }
- + 
- + #define	POLL_SECONDS	2
- + 
- + static void otg_timer(unsigned long _musb)
- + {
- + 	struct musb		*musb = (void *)_musb;
- + 	void __iomem		*mregs = musb->mregs;
- + 	u8			devctl;
- + 	unsigned long		flags;
- + 
- + 	/* We poll because DaVinci's won't expose several OTG-critical
- + 	* status change events (from the transceiver) otherwise.
- + 	 */
- + 	devctl = musb_readb(mregs, MUSB_DEVCTL);
- + 	dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
- + 			otg_state_string(musb->xceiv->state));
- + 
- + 	spin_lock_irqsave(&musb->lock, flags);
- + 	switch (musb->xceiv->state) {
- + 	case OTG_STATE_A_WAIT_BCON:
- + 		devctl &= ~MUSB_DEVCTL_SESSION;
- + 		musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
- + 
- + 		devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
- + 		if (devctl & MUSB_DEVCTL_HM) {
- + 			musb->xceiv->state = OTG_STATE_A_IDLE;
- + 			MUSB_HST_MODE(musb);
- + 		} else {
- + 			musb->xceiv->state = OTG_STATE_B_IDLE;
- + 			MUSB_DEV_MODE(musb);
- + 			mod_timer(&musb->otg_workaround,
- + 					jiffies + POLL_SECONDS * HZ);
- + 		}
- + 		break;
- + 	case OTG_STATE_A_WAIT_VFALL:
- + 		/*
- + 		 * Wait till VBUS falls below SessionEnd (~0.2 V); the 1.3
- + 		 * RTL seems to mis-handle session "start" otherwise (or in
- + 		 * our case "recover"), in routine "VBUS was valid by the time
- + 		 * VBUSERR got reported during enumeration" cases.
- + 		 */
- + 		if (devctl & MUSB_DEVCTL_VBUS) {
- + 			mod_timer(&musb->otg_workaround,
- + 					jiffies + POLL_SECONDS * HZ);
- + 			break;
- + 		}
- + 		musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
- + 		musb_writel(musb->ctrl_base, USB_CORE_INTR_SET_REG,
- + 			    MUSB_INTR_VBUSERROR << USB_INTR_USB_SHIFT);
- + 		break;
- + 	case OTG_STATE_B_IDLE:
- + 		if (!is_peripheral_enabled(musb))
- + 			break;
- + 
- + 		/*
- + 		 * There's no ID-changed IRQ, so we have no good way to tell
- + 		 * when to switch to the A-Default state machine (by setting
- + 		 * the DEVCTL.SESSION flag).
- + 		 *
- + 		 * Workaround:  whenever we're in B_IDLE, try setting the
- + 		 * session flag every few seconds.  If it works, ID was
- + 		 * grounded and we're now in the A-Default state machine.
- + 		 *
- + 		 * NOTE: setting the session flag is _supposed_ to trigger
- + 		 * SRP but clearly it doesn't.
- + 		 */
- + 		devctl = musb_readb(mregs, MUSB_DEVCTL);
- + 		if (devctl & MUSB_DEVCTL_HM) {
- + 			musb->xceiv->state = OTG_STATE_A_IDLE;
- + 			break;
- + 		}
- + 
- + 		/* don't toggle SESSION flag if VBUS presents - connected
- + 		 * to Host already
- + 		 */
- + 		if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
- + 			break;
- + 
- + 		if ((devctl & MUSB_DEVCTL_SESSION) &&
- + 				!(devctl & MUSB_DEVCTL_BDEVICE))
- + 			devctl &= ~MUSB_DEVCTL_SESSION;
- + 		else
- + 			devctl |= MUSB_DEVCTL_SESSION;
- + 
- + 		mod_timer(&musb->otg_workaround,
- + 				jiffies + POLL_SECONDS * HZ);
- + 		musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
- + 		break;
- + 	default:
- + 		break;
- + 	}
- + 	spin_unlock_irqrestore(&musb->lock, flags);
- + }
- + 
- + void ti81xx_musb_try_idle(struct musb *musb, unsigned long timeout)
- + {
- + 	if (!is_otg_enabled(musb))
- + 		return;
- + 
- + 	if (timeout == 0)
- + 		timeout = jiffies + msecs_to_jiffies(3);
- + 
- + 	/* Never idle if active, or when VBUS timeout is not set as host */
- + 	if (musb->is_active || (musb->a_wait_bcon == 0 &&
- + 				musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
- + 		dev_dbg(musb->controller, "%s active, deleting timer\n",
- + 			otg_state_string(musb->xceiv->state));
- + 		del_timer(&musb->otg_workaround);
- + 		musb->last_timer = jiffies;
- + 		return;
- + 	}
- + 
- + 	if (time_after(musb->last_timer, timeout) &&
- + 					timer_pending(&musb->otg_workaround)) {
- + 		dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
- + 		return;
- + 	}
- + 	musb->last_timer = timeout;
- + 
- + 	dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
- + 	    otg_state_string(musb->xceiv->state),
- + 		jiffies_to_msecs(timeout - jiffies));
- + 	mod_timer(&musb->otg_workaround, timeout);
- + }
- + 
- + #ifdef CONFIG_USB_TI_CPPI41_DMA
- + static irqreturn_t cppi41dma_Interrupt(int irq, void *hci)
- + {
- + 	u32 intr_status;
- + 	irqreturn_t ret = IRQ_NONE;
- + 	u32 q_cmpl_status_0, q_cmpl_status_1, q_cmpl_status_2;
- + 	u32 usb0_tx_intr, usb0_rx_intr;
- + 	u32 usb1_tx_intr, usb1_rx_intr;
- + 	void *q_mgr_base = cppi41_queue_mgr[0].q_mgr_rgn_base;
- + 	unsigned long flags;
- + 
- + 	/*
- + 	 * CPPI 4.1 interrupts share the same IRQ and the EOI register but
- + 	 * don't get reflected in the interrupt source/mask registers.
- + 	 */
- + 	/*
- + 	 * Check for the interrupts from Tx/Rx completion queues; they
- + 	 * are level-triggered and will stay asserted until the queues
- + 	 * are emptied.  We're using the queue pending register 0 as a
- + 	 * substitute for the interrupt status register and reading it
- + 	 * directly for speed.
- + 	 */
- + 	intr_status = usbss_read(USBSS_IRQ_STATUS);
- + 
- + 	if (intr_status)
- + 		usbss_write(USBSS_IRQ_STATUS, intr_status);
- + 	else
- + 		printk(KERN_DEBUG "spurious usbss intr\n");
- + 
- + 	q_cmpl_status_0 = musb_readl(q_mgr_base, CPPI41_QSTATUS_REG2);
- + 	q_cmpl_status_1 = musb_readl(q_mgr_base, CPPI41_QSTATUS_REG3);
- + 	q_cmpl_status_2 = musb_readl(q_mgr_base, CPPI41_QSTATUS_REG4);
- + 
- + 	/* USB0 tx/rx completion */
- + 	/* usb0 tx completion interrupt for ep1..15 */
- + 	usb0_tx_intr = (q_cmpl_status_0 >> 29) |
- + 			((q_cmpl_status_1 & 0xFFF) << 3);
- + 	usb0_rx_intr = ((q_cmpl_status_1 & 0x07FFe000) >> 13);
- + 
- + 	usb1_tx_intr = (q_cmpl_status_1 >> 29) |
- + 			((q_cmpl_status_2 & 0xFFF) << 3);
- + 	usb1_rx_intr = ((q_cmpl_status_2 & 0x0fffe000) >> 13);
- + 
- + 	/* get proper musb handle based usb0/usb1 ctrl-id */
- + 
- + 	if (gmusb[0] && (usb0_tx_intr || usb0_rx_intr)) {
- + 		dev_dbg(gmusb[0]->controller, "CPPI 4.1 IRQ: Tx %x, Rx %x\n",
- + 			usb0_tx_intr, usb0_rx_intr);
- + 		spin_lock_irqsave(&gmusb[0]->lock, flags);
- + 		cppi41_completion(gmusb[0], usb0_rx_intr,
- + 					usb0_tx_intr);
- + 		spin_unlock_irqrestore(&gmusb[0]->lock, flags);
- + 		ret = IRQ_HANDLED;
- + 	}
- + 
- + 	if (gmusb[1] && (usb1_rx_intr || usb1_tx_intr)) {
- + 		dev_dbg(gmusb[1]->controller, "CPPI 4.1 IRQ: Tx %x, Rx %x\n",
- + 			usb1_tx_intr, usb1_rx_intr);
- + 		spin_lock_irqsave(&gmusb[1]->lock, flags);
- + 		cppi41_completion(gmusb[1], usb1_rx_intr,
- + 			usb1_tx_intr);
- + 		spin_unlock_irqrestore(&gmusb[1]->lock, flags);
- + 		ret = IRQ_HANDLED;
- + 	}
- + 	usbss_write(USBSS_IRQ_EOI, 0);
- + 
- + 	return ret;
- + }
- + #endif
- + 
- + int musb_simulate_babble(struct musb *musb)
- + {
- + 	void __iomem *reg_base = musb->ctrl_base;
- + 	void __iomem *mbase = musb->mregs;
- + 	struct device *dev = musb->controller;
- + 	struct musb_hdrc_platform_data *plat = dev->platform_data;
- + 	struct omap_musb_board_data *data = plat->board_data;
- + 	u8 reg;
- + 
- + 	/* during babble condition musb controller
- + 	 * remove the session
- + 	 */
- + 	if (!data->babble_ctrl) {
- + 		reg = musb_readb(mbase, MUSB_DEVCTL);
- + 		reg &= ~MUSB_DEVCTL_SESSION;
- + 		musb_writeb(mbase, MUSB_DEVCTL, reg);
- + 		mdelay(100);
- + 	}
- + 
- + 	/* generate s/w babble interrupt */
- + 	musb_writel(reg_base, USB_IRQ_STATUS_RAW_1, MUSB_INTR_BABBLE);
- + 	return 0;
- + }
- + EXPORT_SYMBOL(musb_simulate_babble);
- + 
- + void musb_babble_workaround(struct musb *musb)
- + {
- + 	void __iomem *reg_base = musb->ctrl_base;
- + 	struct device *dev = musb->controller;
- + 	struct musb_hdrc_platform_data *plat = dev->platform_data;
- + 	struct omap_musb_board_data *data = plat->board_data;
- + 
- + 	ERR("Babble: devtcl(%x)Restarting musb....\n",
- + 			 musb_readb(musb->mregs, MUSB_DEVCTL));
- + 
- + 	/* Reset the controller */
- + 	musb_writel(reg_base, USB_CTRL_REG, USB_SOFT_RESET_MASK);
- + 	while ((musb_readl(reg_base, USB_CTRL_REG) & 0x1))
- + 		cpu_relax();
- + 
- + 	/* Shutdown the on-chip PHY and its PLL. */
- + 	if (data->set_phy_power)
- + 		data->set_phy_power(musb->id, 0, false);
- + 	udelay(100);
- + 
- + 	musb_platform_set_mode(musb, MUSB_HOST);
- + 	udelay(100);
- + 
- + 	/* enable the usbphy */
- + 	if (data->set_phy_power)
- + 		data->set_phy_power(musb->id, 1, false);
- + 	mdelay(100);
- + 
- + 	/* re-setup the endpoint fifo addresses */
- + 	if (musb->ops->reinit)
- + 		musb->ops->reinit(plat->config->multipoint, musb);
- + 	musb_start(musb);
- + }
- + 
- + void musb_babble_hwfix(struct musb *musb)
- + {
- + 	int timeout = 10;
- + 	u8 temp, session_restart = 0;
- + 
- + 	/* wait for 320 clock cycles and check whether still babble
- + 	 * present on the bus */
- + 	udelay(6);
- + 
- + 	temp = musb_readb(musb->mregs, MUSB_MISC);
- + 	dev_dbg(musb->controller, "babble: MUSB MISC value %x\n", temp);
- + 
- + 	/* check line monitor flag to check whether babble is
- + 	 * due to noise
- + 	 */
- + 	dev_dbg(musb->controller, "STUCK_J is %s\n",
- + 		temp & MUSB_MISC_STUCK_J ? "set" : "reset");
- + 
- + 	if (temp & MUSB_MISC_STUCK_J) {
- + 		/* babble is due to noise, then set transmit idle (d7 bit)
- + 		 * to resume normal operation
- + 		 */
- + 		temp = musb_readb(musb->mregs, MUSB_MISC);
- + 		temp |= MUSB_MISC_FORCE_TXIDLE;
- + 		musb_writeb(musb->mregs, MUSB_MISC, temp);
- + 
- + 		/* wait till line monitor flag cleared */
- + 		dev_dbg(musb->controller, "Set TXIDLE, wait J to clear\n");
- + 		do {
- + 			temp = musb_readb(musb->mregs, MUSB_MISC);
- + 			udelay(1);
- + 		} while ((temp & MUSB_MISC_STUCK_J) && timeout--);
- + 
- + 		/* check whether stuck_at_j bit cleared */
- + 		temp = musb_readb(musb->mregs, MUSB_MISC);
- + 		if (temp & MUSB_MISC_STUCK_J) {
- + 			/* real babble condition is occured
- + 			 * restart the controller to start the
- + 			 * session again
- + 			 */
- + 			dev_dbg(musb->controller, "J not cleared, misc (%x)\n",
- + 				temp);
- + 
- + 			session_restart = 1;
- + 		} else {
- + 			pr_info("babble: controller shall resume normal\n");
- + 			/* check controller resumes normal operation
- + 			 * by checking sof occurs for few frames
- + 			 */
- + 			musb->sof_cnt = 2;
- + 			ti81xx_musb_enable_sof(musb);
- + 			udelay(280);
- + 			if (musb->sof_cnt) {
- + 				pr_info("babble: controller cannot resume\n");
- + 				session_restart = 1;
- + 			} else
- + 				pr_info("babble: controller resumed normal\n");
- + 			ti81xx_musb_disable_sof(musb);
- + 		}
- + 	} else
- + 		session_restart = 1;
- + 
- + 	if (session_restart) {
- + 		unsigned long flags;
- + 
- + 		dev_dbg(musb->controller, "babble: restart controller\n");
- + 		temp = musb_readb(musb->mregs, MUSB_DEVCTL);
- + 		temp &= ~MUSB_DEVCTL_SESSION;
- + 		musb_writeb(musb->mregs, MUSB_DEVCTL, temp);
- + 
- + 		 /* inform stack about disconnect of root hub */
- + 		spin_lock_irqsave(&musb->lock, flags);
- + 		musb->int_usb = MUSB_INTR_DISCONNECT;
- + 		musb_interrupt(musb);
- + 		spin_unlock_irqrestore(&musb->lock, flags);
- + 
- + 		/* restart the session */
- + 		musb_babble_workaround(musb);
- + 	}
- + }
- + 
- + static void evm_deferred_musb_restart(struct work_struct *work)
- + {
- + 	struct musb *musb =
- + 		container_of(work, struct musb, work);
- + 
- + 	if (musb->enable_babble_work == BABBLE_WORKAROUND_3) {
- + 		/* hw will not end the session  */
- + 		musb_babble_hwfix(musb);
- + 	} else {
- + 		ERR("deferred musb restart musbid(%d)\n", musb->id);
- + 		musb_babble_workaround(musb);
- + 	}
- + }
- + 
- + static irqreturn_t ti81xx_interrupt(int irq, void *hci)
- + {
- + 	struct musb  *musb = hci;
- + 	void __iomem *reg_base = musb->ctrl_base;
- + 	unsigned long flags;
- + 	irqreturn_t ret = IRQ_NONE;
- + 	u32 pend1 = 0, pend2 = 0;
- + 	u32 epintr, usbintr;
- + 	u8  is_babble = 0;
- + 
- + 	spin_lock_irqsave(&musb->lock, flags);
- + 
- + 	/* Acknowledge and handle non-CPPI interrupts */
- + 	/* Get endpoint interrupts */
- + 	epintr = musb_readl(reg_base, USB_EP_INTR_STATUS_REG);
- + 	musb->int_rx = (epintr & USB_RX_INTR_MASK) >> USB_INTR_RX_SHIFT;
- + 	musb->int_tx = (epintr & USB_TX_INTR_MASK) >> USB_INTR_TX_SHIFT;
- + 	if (epintr)
- + 		musb_writel(reg_base, USB_EP_INTR_STATUS_REG, epintr);
- + 
- + 	/* Get usb core interrupts */
- + 	usbintr = musb_readl(reg_base, USB_CORE_INTR_STATUS_REG);
- + 	if (!usbintr && !epintr) {
- + 		dev_dbg(musb->controller, "sprious interrupt\n");
- + 		goto eoi;
- + 	}
- + 
- + 	if (usbintr)
- + 		musb_writel(reg_base, USB_CORE_INTR_STATUS_REG, usbintr);
- + 	musb->int_usb =	(usbintr & USB_INTR_USB_MASK) >> USB_INTR_USB_SHIFT;
- + 
- + 	dev_dbg(musb->controller, "usbintr (%x) epintr(%x)\n", usbintr, epintr);
- + 
- + 	if (musb->int_usb & MUSB_INTR_SOF) {
- + 		if (musb->sof_enabled) {
- + 			if (musb->sof_cnt == 0)
- + 				ti81xx_musb_disable_sof(musb);
- + 			else
- + 				--musb->sof_cnt;
- + 		}
- + 		ret = IRQ_HANDLED;
- + 	}
- + 
- + 	if (musb->txfifo_intr_enable && (usbintr & USB_INTR_TXFIFO_MASK)) {
- + #ifdef CONFIG_USB_TI_CPPI41_DMA
- + 		dev_dbg(musb->controller,
- + 			"TxFIFOIntr %x\n", usbintr >> USB_INTR_TXFIFO_EMPTY);
- + 		cppi41_handle_txfifo_intr(musb,
- + 				usbintr >> USB_INTR_TXFIFO_EMPTY);
- + 		ret = IRQ_HANDLED;
- + #endif
- + 	}
- + 	usbintr &= ~USB_INTR_TXFIFO_MASK;
- + 
- + 	/*
- + 	 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
- + 	 * AM3517's missing ID change IRQ.  We need an ID change IRQ to
- + 	 * switch appropriately between halves of the OTG state machine.
- + 	 * Managing DEVCTL.SESSION per Mentor docs requires that we know its
- + 	 * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
- + 	 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
- + 	 */
- + 	if ((usbintr & MUSB_INTR_BABBLE) && is_otg_enabled(musb)
- + 		&& (musb->xceiv->state == OTG_STATE_A_HOST))
- + 		is_babble = 1;
- + 	else if ((usbintr & MUSB_INTR_BABBLE) && !is_otg_enabled(musb)
- + 		&& is_host_enabled(musb))
- + 			is_babble = 1;
- + 
- + 	if (is_babble) {
- + 		if (musb->enable_babble_work != BABBLE_WORKAROUND_3)
- + 			musb->int_usb = MUSB_INTR_DISCONNECT;
- + 
- + 		ERR("CAUTION: musb%d: Babble Interrupt Occured\n", musb->id);
- + 	}
- + 
- + 	if (usbintr & (USB_INTR_DRVVBUS << USB_INTR_USB_SHIFT)) {
- + 		int drvvbus = musb_readl(reg_base, USB_STAT_REG);
- + 		void __iomem *mregs = musb->mregs;
- + 		u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
- + 		int err;
- + 
- + 		err = is_host_enabled(musb) && (musb->int_usb &
- + 						MUSB_INTR_VBUSERROR);
- + 		if (err) {
- + 			/*
- + 			 * The Mentor core doesn't debounce VBUS as needed
- + 			 * to cope with device connect current spikes. This
- + 			 * means it's not uncommon for bus-powered devices
- + 			 * to get VBUS errors during enumeration.
- + 			 *
- + 			 * This is a workaround, but newer RTL from Mentor
- + 			 * seems to allow a better one: "re"-starting sessions
- + 			 * without waiting for VBUS to stop registering in
- + 			 * devctl.
- + 			 */
- + 			musb->int_usb &= ~MUSB_INTR_VBUSERROR;
- + 			musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
- + 			mod_timer(&musb->otg_workaround,
- + 						jiffies + POLL_SECONDS * HZ);
- + 			WARNING("VBUS error workaround (delay coming)\n");
- + 		} else if (is_host_enabled(musb) && drvvbus) {
- + 			if ((devctl & MUSB_DEVCTL_SESSION) &&
- + 				!(devctl & MUSB_DEVCTL_BDEVICE) &&
- + 				!(devctl & MUSB_DEVCTL_HM)) {
- + 				dev_dbg(musb->controller,
- + 					"Only micro-A plug is connected\n");
- + 			} else {
- + 				if (musb->is_active)
- + 					del_timer(&musb->otg_workaround);
- + 				else
- + 					musb->is_active = 1;
- + 
- + 				MUSB_HST_MODE(musb);
- + 				musb->xceiv->default_a = 1;
- + 				musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
- + 			}
- + 		} else {
- + 			musb->is_active = 0;
- + 			MUSB_DEV_MODE(musb);
- + 			musb->xceiv->default_a = 0;
- + 			musb->xceiv->state = OTG_STATE_B_IDLE;
- + 		}
- + 
- + 		/* NOTE: this must complete power-on within 100 ms. */
- + 		dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
- + 				drvvbus ? "on" : "off",
- + 				otg_state_string(musb->xceiv->state),
- + 				err ? " ERROR" : "",
- + 				devctl);
- + 		ret = IRQ_HANDLED;
- + 	}
- + 
- + 	if (musb->int_tx || musb->int_rx || musb->int_usb)
- + 		ret |= musb_interrupt(musb);
- + 
- +  eoi:
- + 	/* EOI needs to be written for the IRQ to be re-asserted. */
- + 	if (ret == IRQ_HANDLED || epintr || usbintr) {
- + 		/* write EOI */
- + 		musb_writel(reg_base, USB_IRQ_EOI, 1);
- + 	}
- + 
- + 	/* Poll for ID change */
- + 	if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
- + 		mod_timer(&musb->otg_workaround, jiffies + POLL_SECONDS * HZ);
- + 
- + 	spin_unlock_irqrestore(&musb->lock, flags);
- + 
- + 	if (ret != IRQ_HANDLED) {
- + 		if (epintr || usbintr)
- + 			/*
- + 			 * We sometimes get unhandled IRQs in the peripheral
- + 			 * mode from EP0 and SOF...
- + 			 */
- + 			dev_dbg(musb->controller, "Unhandled USB IRQ %08x-%08x\n",
- + 					 epintr, usbintr);
- + 		else if (printk_ratelimit())
- + 			/*
- + 			 * We've seen series of spurious interrupts in the
- + 			 * peripheral mode after USB reset and then after some
- + 			 * time a real interrupt storm starting...
- + 			 */
- + 			dev_dbg(musb->controller, "Spurious IRQ, CPPI 4.1 status %08x, %08x\n",
- + 					 pend1, pend2);
- + 	}
- + 
- + 	if (is_babble) {
- + 		if (musb->enable_babble_work)
- + 			schedule_work(&musb->work);
- + 		else {
- + 			musb_writeb(musb->mregs, MUSB_DEVCTL,
- + 				musb_readb(musb->mregs, MUSB_DEVCTL) |
- + 				MUSB_DEVCTL_SESSION);
- + 		}
- + 	}
- + 	return ret;
- + }
- + int ti81xx_musb_set_mode(struct musb *musb, u8 musb_mode)
- + {
- + 	void __iomem *reg_base = musb->ctrl_base;
- + 	u32 regval;
- + 
- + 	/* TODO: implement this using CONF0 */
- + 	if (musb_mode == MUSB_HOST) {
- + 		regval = musb_readl(reg_base, USB_MODE_REG);
- + 
- + 		regval &= ~USBMODE_USBID_HIGH;
- + 		if (usbid_sw_ctrl && cpu_is_ti816x())
- + 			regval |= USBMODE_USBID_MUXSEL;
- + 
- + 		musb_writel(reg_base, USB_MODE_REG, regval);
- + 		musb_writel(musb->ctrl_base, USB_PHY_UTMI_REG, 0x02);
- + 		dev_dbg(musb->controller, "host: value of mode reg=%x regval(%x)\n",
- + 			musb_readl(reg_base, USB_MODE_REG), regval);
- + 	} else if (musb_mode == MUSB_PERIPHERAL) {
- + 		/* TODO commmented writing 8 to USB_MODE_REG device
- + 			mode is not working */
- + 		regval = musb_readl(reg_base, USB_MODE_REG);
- + 
- + 		regval |= USBMODE_USBID_HIGH;
- + 		if (usbid_sw_ctrl && cpu_is_ti816x())
- + 			regval |= USBMODE_USBID_MUXSEL;
- + 
- + 		musb_writel(reg_base, USB_MODE_REG, regval);
- + 		dev_dbg(musb->controller, "device: value of mode reg=%x regval(%x)\n",
- + 			musb_readl(reg_base, USB_MODE_REG), regval);
- + 	} else if (musb_mode == MUSB_OTG) {
- + 		musb_writel(musb->ctrl_base, USB_PHY_UTMI_REG, 0x02);
- + 	} else
- + 		return -EIO;
- + 
- + 	return 0;
- + }
- + 
- + int ti81xx_musb_init(struct musb *musb)
- + {
- + 	void __iomem *reg_base = musb->ctrl_base;
- + 	struct device *dev = musb->controller;
- + 	struct musb_hdrc_platform_data *plat = dev->platform_data;
- + 	struct omap_musb_board_data *data = plat->board_data;
- + 	u32 rev;
- + 	u8 mode;
- + 
- + 	if (musb->id < 2)
- + 		gmusb[musb->id] = musb;
- + 
- + 	usb_nop_xceiv_register(musb->id);
- + 
- + 	musb->xceiv = otg_get_transceiver(musb->id);
- + 	if (!musb->xceiv)
- + 		return -ENODEV;
- + 
- + 	/* mentor is at offset of 0x400 in am3517/ti81xx */
- + 	musb->mregs += USB_MENTOR_CORE_OFFSET;
- + 
- + 	/* Returns zero if e.g. not clocked */
- + 	rev = musb_readl(reg_base, USB_REVISION_REG);
- + 	if (!rev)
- + 		return -ENODEV;
- + 
- + 	pr_info("MUSB%d controller's USBSS revision = %08x\n", musb->id, rev);
- + 
- + 	if (is_host_enabled(musb))
- + 		setup_timer(&musb->otg_workaround, otg_timer,
- + 					(unsigned long) musb);
- + 
- + 	/* Reset the controller */
- + 	musb_writel(reg_base, USB_CTRL_REG, USB_SOFT_RESET_MASK);
- + 
- + 	/* wait till reset bit clears */
- + 	while ((musb_readl(reg_base, USB_CTRL_REG) & 0x1))
- + 		cpu_relax();
- + 
- + 	/* Start the on-chip PHY and its PLL with PHYWKUP disabled */
- + 	if (data->set_phy_power)
- + 		data->set_phy_power(musb->id, 1, false);
- + 
- + 	musb->a_wait_bcon = A_WAIT_BCON_TIMEOUT;
- + 	musb->isr = ti81xx_interrupt;
- + 
- + 	if (cpu_is_ti816x())
- + 		usbid_sw_ctrl = 1;
- + 
- + 	if (is_otg_enabled(musb)) {
- + 		/* if usb-id contolled through software for ti816x then
- + 		 * configure the usb0 in peripheral mode and usb1 in
- + 		 * host mode
- + 		*/
- + 		if (usbid_sw_ctrl && cpu_is_ti816x())
- + 			mode = musb->id ? MUSB_HOST : MUSB_PERIPHERAL;
- + 		else
- + 			mode = MUSB_OTG;
- + 	} else
- + 		/* set musb controller to host mode */
- + 		mode = is_host_enabled(musb) ? MUSB_HOST : MUSB_PERIPHERAL;
- + 
- + 	/* set musb controller to host mode */
- + 	musb_platform_set_mode(musb, mode);
- + 
- + #ifdef CONFIG_USB_TI_CPPI41_DMA
- + 	musb->txfifo_intr_enable = 1;
- + 	if (musb->txfifo_intr_enable)
- + 		printk(KERN_DEBUG "TxFifo Empty intr enabled\n");
- + 	else
- + 		printk(KERN_DEBUG "TxFifo Empty intr disabled\n");
- + 
- + 	/* enable rxdma GRNDIS mode, as Extra IN token
- + 	 * issue fixed in PG2.0 RTL
- + 	 */
- + 	if (data->grndis_for_host_rx)
- + 		usb_cppi41_info[musb->id].grndis_for_host_rx = 1;
- + #endif
- + 	/* enable babble workaround */
- + 	INIT_WORK(&musb->work, evm_deferred_musb_restart);
- + 	musb->enable_babble_work = 0;
- + 
- + 	musb->enable_babble_work = BABBLE_WORKAROUND;
- + 	musb_writel(reg_base, USB_IRQ_EOI, 0);
- + 
- + 	if (data->babble_ctrl) {
- + 		u8 temp;
- + 		/* enable s/w controlled session bit during
- + 		 * babble condition
- + 		 */
- + 		temp = musb_readb(musb->mregs, MUSB_MISC);
- + 		temp |= MUSB_MISC_SW_SESSION_CTRL;
- + 		musb_writeb(musb->mregs, MUSB_MISC, temp);
- + 
- + 		musb->enable_babble_work = BABBLE_WORKAROUND_3;
- + 		pr_info("musb%d: Enabled SW babble control\n", musb->id);
- + 		dev_dbg(musb->controller, "musb.misc regval %x\n",
- + 			musb_readb(musb->mregs, MUSB_MISC));
- + 	}
- + 
- + 	return 0;
- + }
- + 
- + /* TI81xx supports only 32bit read operation */
- + void ti81xx_musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
- + {
- + 	void __iomem *fifo = hw_ep->fifo;
- + 	u32		val;
- + 	int		i;
- + 
- + 	/* Read for 32bit-aligned destination address */
- + 	if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
- + 		readsl(fifo, dst, len >> 2);
- + 		dst += len & ~0x03;
- + 		len &= 0x03;
- + 	}
- + 	/*
- + 	 * Now read the remaining 1 to 3 byte or complete length if
- + 	 * unaligned address.
- + 	 */
- + 	if (len > 4) {
- + 		for (i = 0; i < (len >> 2); i++) {
- + 			*(u32 *) dst = musb_readl(fifo, 0);
- + 			dst += 4;
- + 		}
- + 		len &= 0x03;
- + 	}
- + 	if (len > 0) {
- + 		val = musb_readl(fifo, 0);
- + 		memcpy(dst, &val, len);
- + 	}
- + }
- + 
- + int ti81xx_musb_exit(struct musb *musb)
- + {
- + 	struct device *dev = musb->controller;
- + 	struct musb_hdrc_platform_data *plat = dev->platform_data;
- + 	struct omap_musb_board_data *data = plat->board_data;
- + 
- + 	if (is_host_enabled(musb))
- + 		del_timer_sync(&musb->otg_workaround);
- + 
- + 	/* Shutdown the on-chip PHY and its PLL. */
- + 	if (data->set_phy_power)
- + 		data->set_phy_power(musb->id, 0, false);
- + 
- + 	otg_put_transceiver(musb->xceiv);
- + 	usb_nop_xceiv_unregister(musb->id);
- + 
- + 	return 0;
- + }
- + 
- + static struct musb_platform_ops ti81xx_ops = {
- + 	.fifo_mode	= 4,
- + 	.flags		= MUSB_GLUE_EP_ADDR_FLAT_MAPPING | MUSB_GLUE_DMA_CPPI41,
- + 	.init		= ti81xx_musb_init,
- + 	.exit		= ti81xx_musb_exit,
- + 
- + 	.enable		= ti81xx_musb_enable,
- + 	.disable	= ti81xx_musb_disable,
- + 
- + 	.try_idle	= ti81xx_musb_try_idle,
- + 	.set_mode	= ti81xx_musb_set_mode,
- + 
- + 	.read_fifo      = ti81xx_musb_read_fifo,
- + 	.write_fifo     = musb_write_fifo,
- + 
- + 	.dma_controller_create	= cppi41_dma_controller_create,
- + 	.dma_controller_destroy	= cppi41_dma_controller_destroy,
- + 	.simulate_babble_intr	= musb_simulate_babble,
- + #ifdef CONFIG_USB_TI_CPPI41_DMA
- + 	.txfifoempty_intr_enable = txfifoempty_intr_enable,
- + 	.txfifoempty_intr_disable = txfifoempty_intr_disable,
- + #endif
- + 	.reinit = musb_reinit,
- + };
- + 
- + static void __devexit ti81xx_delete_musb_pdev(struct ti81xx_glue *glue, u8 id)
- + {
- + 	platform_device_del(glue->musb[id]);
- + 	platform_device_put(glue->musb[id]);
- + }
- + 
- + static int __devinit ti81xx_create_musb_pdev(struct ti81xx_glue *glue, u8 id)
- + {
- + 	struct device *dev = glue->dev;
- + 	struct platform_device *pdev = to_platform_device(dev);
- + 	struct musb_hdrc_platform_data  *pdata = dev->platform_data;
- + 	struct omap_musb_board_data *bdata = pdata->board_data;
- + 	struct platform_device	*musb;
- + 	struct resource *res;
- + 	struct resource	resources[2];
- + 	char res_name[10];
- + 	int ret = 0;
- + 
- + 	/* get memory resource */
- + 	sprintf(res_name, "musb%d", id);
- + 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, res_name);
- + 	if (!res) {
- + 		dev_err(dev, "%s get mem resource failed\n", res_name);
- + 		ret = -ENODEV;
- + 		goto err0;
- + 	}
- + 	res->parent = NULL;
- + 	resources[0] = *res;
- + 
- + 	/* get irq resource */
- + 	sprintf(res_name, "musb%d-irq", id);
- + 	res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, res_name);
- + 	if (!res) {
- + 		dev_err(dev, "%s get irq resource failed\n", res_name);
- + 		ret = -ENODEV;
- + 		goto err0;
- + 	}
- + 	res->parent = NULL;
- + 	resources[1] = *res;
- + 
- + 	/* allocate the child platform device */
- + 	musb = platform_device_alloc("musb-hdrc", id);
- + 	if (!musb) {
- + 		dev_err(dev, "failed to allocate musb device\n");
- + 		goto err0;
- + 	}
- + 
- + 	musb->id			= id;
- + 	musb->dev.parent		= dev;
- + 	musb->dev.dma_mask		= &musb_dmamask;
- + 	musb->dev.coherent_dma_mask	= musb_dmamask;
- + 
- + 	glue->musb[id]			= musb;
- + 
- + 	pdata->platform_ops		= &ti81xx_ops;
- + 
- + 	ret = platform_device_add_resources(musb, resources, 2);
- + 	if (ret) {
- + 		dev_err(dev, "failed to add resources\n");
- + 		goto err1;
- + 	}
- + 
- + 	if (id == 0)
- + 		pdata->mode = bdata->mode & USB0PORT_MODEMASK;
- + 	else
- + 		pdata->mode = (bdata->mode & USB1PORT_MODEMASK)
- + 					>> USB1PORT_MODESHIFT;
- + 
- + 	dev_info(dev, "musb%d, board_mode=0x%x, plat_mode=0x%x\n",
- + 					id, bdata->mode, pdata->mode);
- + 
- + 	ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
- + 	if (ret) {
- + 		dev_err(dev, "failed to add platform_data\n");
- + 		goto err1;
- + 	}
- + 
- + 	ret = platform_device_add(musb);
- + 	if (ret) {
- + 		dev_err(dev, "failed to register musb device\n");
- + 		goto err1;
- + 	}
- + 
- + 	return 0;
- + 
- + err1:
- + 	platform_device_put(musb);
- + err0:
- + 	return ret;
- + }
- + 
- + static int __init ti81xx_probe(struct platform_device *pdev)
- + {
- + 	struct ti81xx_glue *glue;
- + 	struct device *dev = &pdev->dev;
- + 	struct musb_hdrc_platform_data *plat = dev->platform_data;
- + 	struct omap_musb_board_data *data = plat->board_data;
- + 	int ret = 0, i;
- + 	struct resource *res;
- + 
- + 	/* allocate glue */
- + 	glue = kzalloc(sizeof(*glue), GFP_KERNEL);
- + 	if (!glue) {
- + 		dev_err(&pdev->dev, "unable to allocate glue memory\n");
- + 		ret = -ENOMEM;
- + 		goto err0;
- + 	}
- + 
- + 	/* get memory resource */
- + 	glue->mem_pa = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- + 	if (!glue->mem_pa) {
- + 		dev_err(&pdev->dev, "failed to get usbss mem resourse\n");
- + 		ret = -ENODEV;
- + 		goto err1;
- + 	}
- + 
- + 	/* get memory resource */
- + 	res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "usbss-irq");
- + 	if (!res) {
- + 		dev_err(&pdev->dev, "failed to get usbss irq resourse\n");
- + 		ret = -ENODEV;
- + 		goto err1;
- + 	}
- + 	glue->irq = res->start;
- + 
- + 	/* iomap for usbss mem space */
- + 	glue->mem_va =
- + 		ioremap(glue->mem_pa->start, resource_size(glue->mem_pa));
- + 	if (!glue->mem_va) {
- + 		dev_err(&pdev->dev, "usbss ioremap failed\n");
- + 		ret = -ENOMEM;
- + 		goto err1;
- + 	}
- + 	usbss_virt_base = glue->mem_va;
- + 
- + 	glue->first = 1;
- + 	glue->dev = &pdev->dev;
- + 	platform_set_drvdata(pdev, glue);
- + 
- + 	/* enable clocks */
- + 	pm_runtime_enable(&pdev->dev);
- + 	ret = pm_runtime_get_sync(&pdev->dev);
- + 	if (ret < 0) {
- + 		dev_err(dev, "pm_runtime_get_sync FAILED");
- + 		goto err2;
- + 	}
- + 
- + 	/* usb subsystem init */
- + 	usbotg_ss_init();
- + 
- + 	/* clear any USBSS interrupts */
- + 	writel(0, glue->mem_va + USBSS_IRQ_EOI);
- + 	writel(readl(glue->mem_va + USBSS_IRQ_STATUS),
- + 					glue->mem_va + USBSS_IRQ_STATUS);
- + 
- + 	/* create the child platform device for mulitple instances of musb */
- + 	for (i = 0; i <= data->instances; ++i) {
- + #ifdef CONFIG_USB_TI_CPPI41_DMA
- + 		/* initialize the cppi41dma init */
- + 		cppi41_init(i, glue->irq, data->instances+1);
- + #endif
- + 		ret = ti81xx_create_musb_pdev(glue, i);
- + 		if (ret != 0)
- + 			goto err3;
- + 	}
- + 
- + 	return 0;
- + 
- + err3:
- + 	pm_runtime_put_sync(&pdev->dev);
- + err2:
- + 	pm_runtime_disable(&pdev->dev);
- + 	iounmap(glue->mem_va);
- + err1:
- + 	kfree(glue);
- + err0:
- + 	return ret;
- + }
- + 
- + static int __exit ti81xx_remove(struct platform_device *pdev)
- + {
- + 	struct ti81xx_glue *glue = platform_get_drvdata(pdev);
- + 	struct device *dev = &pdev->dev;
- + 	struct musb_hdrc_platform_data *plat = dev->platform_data;
- + 	struct omap_musb_board_data *data = plat->board_data;
- + 	int i;
- + 
- + 	pm_runtime_put_sync(&pdev->dev);
- + 	pm_runtime_disable(&pdev->dev);
- + 
- + 	/* delete the child platform device for mulitple instances of musb */
- + 	for (i = 0; i <= data->instances; ++i)
- + 		ti81xx_delete_musb_pdev(glue, i);
- + 
- + #ifdef CONFIG_USB_TI_CPPI41_DMA
- + 	cppi41_free();
- + #endif
- + 	/* iounmap */
- + 	iounmap(glue->mem_va);
- + 	usbotg_ss_uninit();
- + 
- + 	kfree(glue);
- + 
- + 	return 0;
- + }
- + 
- + #ifdef CONFIG_PM
- + static void ti81xx_save_context(struct ti81xx_glue *glue)
- + {
- + 	struct ti81xx_usbss_regs *usbss = &glue->usbss_regs;
- + 	u8 i, j;
- + 
- + 	/* save USBSS register */
- + 	usbss->irq_en_set = usbss_read(USBSS_IRQ_ENABLE_SET);
- + 
- + #ifdef CONFIG_USB_TI_CPPI41_DMA
- + 	for (i = 0 ; i < 4 ; i++) {
- + 		usbss->irq_dma_th_tx0[i] =
- + 			usbss_read(USBSS_IRQ_DMA_THRESHOLD_TX0 + (0x4 * i));
- + 		usbss->irq_dma_th_rx0[i] =
- + 			usbss_read(USBSS_IRQ_DMA_THRESHOLD_RX0 + (0x4 * i));
- + 		usbss->irq_dma_th_tx1[i] =
- + 			usbss_read(USBSS_IRQ_DMA_THRESHOLD_TX1 + (0x4 * i));
- + 		usbss->irq_dma_th_rx1[i] =
- + 			usbss_read(USBSS_IRQ_DMA_THRESHOLD_RX1 + (0x4 * i));
- + 
- + 		usbss->irq_frame_th_tx0[i] =
- + 			usbss_read(USBSS_IRQ_FRAME_THRESHOLD_TX0 + (0x4 * i));
- + 		usbss->irq_frame_th_rx0[i] =
- + 			usbss_read(USBSS_IRQ_FRAME_THRESHOLD_RX0 + (0x4 * i));
- + 		usbss->irq_frame_th_tx1[i] =
- + 			usbss_read(USBSS_IRQ_FRAME_THRESHOLD_TX1 + (0x4 * i));
- + 		usbss->irq_frame_th_rx1[i] =
- + 			usbss_read(USBSS_IRQ_FRAME_THRESHOLD_RX1 + (0x4 * i));
- + 	}
- + 	for (i = 0 ; i < 2 ; i++) {
- + 		usbss->irq_dma_en[i] =
- + 			usbss_read(USBSS_IRQ_DMA_ENABLE_0 + (0x4 * i));
- + 		usbss->irq_frame_en[i] =
- + 			usbss_read(USBSS_IRQ_FRAME_ENABLE_0 + (0x4 * i));
- + 	}
- + #endif
- + 	/* save usbX register */
- + 	for (i = 0 ; i < 2 ; i++) {
- + 		struct ti81xx_usb_regs *usb = &glue->usb_regs[i];
- + 		struct musb *musb = platform_get_drvdata(glue->musb[i]);
- + 		void __iomem *cbase = musb->ctrl_base;
- + 
- + 		/* disable the timers */
- + 		if (timer_pending(&musb->otg_workaround) &&
- + 					is_host_enabled(musb)) {
- + 			del_timer_sync(&musb->otg_workaround);
- + 			musb->en_otgw_timer = 1;
- + 		}
- + 
- + 		if (timer_pending(&musb->otg_timer) &&
- + 					is_otg_enabled(musb)) {
- + 			del_timer_sync(&musb->otg_timer);
- + 			musb->en_otg_timer = 1;
- + 		}
- + 
- + 		musb_save_context(musb);
- + 		usb->control = musb_readl(cbase, USB_CTRL_REG);
- + 
- + 		for (j = 0 ; j < 2 ; j++)
- + 			usb->irq_en_set[j] = musb_readl(cbase,
- + 					USB_IRQ_ENABLE_SET_0 + (0x4 * j));
- + #ifdef CONFIG_USB_TI_CPPI41_DMA
- + 		usb->tx_mode = musb_readl(cbase, USB_TX_MODE_REG);
- + 		usb->rx_mode = musb_readl(cbase, USB_RX_MODE_REG);
- + 
- + 		for (j = 0 ; j < 15 ; j++)
- + 			usb->grndis_size[j] = musb_readl(cbase,
- + 					USB_GENERIC_RNDIS_EP_SIZE_REG(j + 1));
- + 
- + 		usb->auto_req = musb_readl(cbase, TI81XX_USB_AUTOREQ_REG);
- + 		usb->teardn = musb_readl(cbase, TI81XX_USB_TEARDOWN_REG);
- + 		usb->th_xdma_idle = musb_readl(cbase, USB_TH_XDMA_IDLE_REG);
- + #endif
- + 		usb->srp_fix = musb_readl(cbase, USB_SRP_FIX_TIME_REG);
- + 		usb->phy_utmi = musb_readl(cbase, USB_PHY_UTMI_REG);
- + 		usb->mgc_utmi_loopback = musb_readl(cbase, USB_PHY_UTMI_LB_REG);
- + 		usb->mode = musb_readl(cbase, USB_MODE_REG);
- + 	}
- + #ifdef CONFIG_USB_TI_CPPI41_DMA
- + 	/* save CPPI4.1 DMA register for dma block 0 */
- + 	cppi41_save_context(0);
- + #endif
- + }
- + static void ti81xx_restore_context(struct ti81xx_glue *glue)
- + {
- + 	struct ti81xx_usbss_regs *usbss = &glue->usbss_regs;
- + 	u8 i, j;
- + 
- + 	/* restore USBSS register */
- + 	usbss_write(USBSS_IRQ_ENABLE_SET, usbss->irq_en_set);
- + 
- + #ifdef CONFIG_USB_TI_CPPI41_DMA
- + 	for (i = 0 ; i < 4 ; i++) {
- + 		usbss_write(USBSS_IRQ_DMA_THRESHOLD_TX0 + (0x4 * i),
- + 				usbss->irq_dma_th_tx0[i]);
- + 		usbss_write(USBSS_IRQ_DMA_THRESHOLD_RX0 + (0x4 * i),
- + 				usbss->irq_dma_th_rx0[i]);
- + 		usbss_write(USBSS_IRQ_DMA_THRESHOLD_TX1 + (0x4 * i),
- + 				usbss->irq_dma_th_tx1[i]);
- + 		usbss_write(USBSS_IRQ_DMA_THRESHOLD_RX1 + (0x4 * i),
- + 				usbss->irq_dma_th_rx1[i]);
- + 
- + 		usbss_write(USBSS_IRQ_FRAME_THRESHOLD_TX0 + (0x4 * i),
- + 				usbss->irq_frame_th_tx0[i]);
- + 		usbss_write(USBSS_IRQ_FRAME_THRESHOLD_RX0 + (0x4 * i),
- + 				usbss->irq_frame_th_rx0[i]);
- + 		usbss_write(USBSS_IRQ_FRAME_THRESHOLD_TX1 + (0x4 * i),
- + 				usbss->irq_frame_th_tx1[i]);
- + 		usbss_write(USBSS_IRQ_FRAME_THRESHOLD_RX1 + (0x4 * i),
- + 				usbss->irq_frame_th_rx1[i]);
- + 	}
- + 	for (i = 0 ; i < 2 ; i++) {
- + 		usbss_write(USBSS_IRQ_DMA_ENABLE_0 + (0x4 * i),
- + 				usbss->irq_dma_en[i]);
- + 		usbss_write(USBSS_IRQ_FRAME_ENABLE_0 + (0x4 * i),
- + 				usbss->irq_frame_en[i]);
- + 	}
- + #endif
- + 	/* restore usbX register */
- + 	for (i = 0 ; i < 2 ; i++) {
- + 		struct ti81xx_usb_regs *usb = &glue->usb_regs[i];
- + 		struct musb *musb = platform_get_drvdata(glue->musb[i]);
- + 		void __iomem *cbase = musb->ctrl_base;
- + 
- + 		musb_restore_context(musb);
- + 		musb_writel(cbase, USB_CTRL_REG, usb->control);
- + 
- + 		for (j = 0 ; j < 2 ; j++)
- + 			musb_writel(cbase, USB_IRQ_ENABLE_SET_0 + (0x4 * j),
- + 					usb->irq_en_set[j]);
- + 
- + #ifdef CONFIG_USB_TI_CPPI41_DMA
- + 		musb_writel(cbase, USB_TX_MODE_REG, usb->tx_mode);
- + 		musb_writel(cbase, USB_RX_MODE_REG, usb->rx_mode);
- + 
- + 		for (j = 0 ; j < 15 ; j++)
- + 			musb_writel(cbase, USB_GENERIC_RNDIS_EP_SIZE_REG(j + 1),
- + 					usb->grndis_size[j]);
- + 
- + 		musb_writel(cbase, TI81XX_USB_AUTOREQ_REG, usb->auto_req);
- + 		musb_writel(cbase, TI81XX_USB_TEARDOWN_REG, usb->teardn);
- + 		musb_writel(cbase, USB_TH_XDMA_IDLE_REG, usb->th_xdma_idle);
- + #endif
- + 		musb_writel(cbase, USB_SRP_FIX_TIME_REG, usb->srp_fix);
- + 		musb_writel(cbase, USB_PHY_UTMI_REG, usb->phy_utmi);
- + 		musb_writel(cbase, USB_PHY_UTMI_LB_REG, usb->mgc_utmi_loopback);
- + 		musb_writel(cbase, USB_MODE_REG, usb->mode);
- + 
- + 		/* reenable the timers */
- + 		if (musb->en_otgw_timer && is_host_enabled(musb)) {
- + 			mod_timer(&musb->otg_workaround,
- + 					jiffies + POLL_SECONDS * HZ);
- + 			musb->en_otgw_timer = 0;
- + 		}
- + 		if (musb->en_otg_timer && is_otg_enabled(musb)) {
- + 			mod_timer(&musb->otg_timer,
- + 					jiffies + POLL_SECONDS * HZ);
- + 			musb->en_otg_timer = 0;
- + 		}
- + 	}
- + #ifdef CONFIG_USB_TI_CPPI41_DMA
- + 	/* restore CPPI4.1 DMA register for dma block 0 */
- + 	cppi41_restore_context(0, dma_sched_table);
- + #endif
- + 	/* controller needs delay for successful resume */
- + 	msleep(200);
- + }
- + static int ti81xx_runtime_suspend(struct device *dev)
- + {
- + 	struct ti81xx_glue *glue = dev_get_drvdata(dev);
- + 	struct musb_hdrc_platform_data *plat = dev->platform_data;
- + 	struct omap_musb_board_data *data = plat->board_data;
- + 	struct platform_device *pdev;
- + 	int i;
- + 
- + 	/* save wrappers and cppi4.1 dma register */
- + 	ti81xx_save_context(glue);
- + 
- + 	/* Shutdown the on-chip PHY and its PLL.
- + 	 * Enable USB PHYWKUP only if enabled through sysfs.
- + 	 * By default USB PHYWKUP is  disabled
- + 	 */
- + 	if (data->set_phy_power) {
- + 		for (i = 0; i <= data->instances; ++i) {
- + 			pdev = glue->musb[i];
- + 			if (device_may_wakeup(&pdev->dev))
- + 				data->set_phy_power(i, 0, true);
- + 			else
- + 				data->set_phy_power(i, 0, false);
- + 		}
- + 	}
- + 
- + 	return 0;
- + }
- + 
- + static int ti81xx_runtime_resume(struct device *dev)
- + {
- + 	struct ti81xx_glue *glue = dev_get_drvdata(dev);
- + 	struct musb_hdrc_platform_data *plat = dev->platform_data;
- + 	struct omap_musb_board_data *data = plat->board_data;
- + 	int i;
- + 
- + 	/*
- + 	 * ignore first call of resume as all registers are not yet
- + 	 * initialized
- + 	 */
- + 	if (glue->first) {
- + 		glue->first = 0;
- + 		return 0;
- + 	}
- + 
- + 	/* Start the on-chip PHY and its PLL. */
- + 	for (i = 0; i <= data->instances; ++i) {
- + 		if (data->set_phy_power)
- + 			data->set_phy_power(i, 1, false);
- + 	}
- + 
- + 	/* restore wrappers and cppi4.1 dma register */
- + 	ti81xx_restore_context(glue);
- + 
- + 	return 0;
- + }
- + 
- + static const struct dev_pm_ops ti81xx_pm_ops = {
- + 	.runtime_suspend = ti81xx_runtime_suspend,
- + 	.runtime_resume	= ti81xx_runtime_resume,
- + };
- + 
- + #define DEV_PM_OPS	(&ti81xx_pm_ops)
- + #else
- + #define DEV_PM_OPS	NULL
- + #endif
- + 
- + static struct platform_driver ti81xx_musb_driver = {
- + 	.remove         = __exit_p(ti81xx_remove),
- + 	.driver         = {
- + 		.name   = "musb-ti81xx",
- + 		.pm	= DEV_PM_OPS,
- + 	},
- + };
- + 
- + MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
- + MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
- + MODULE_LICENSE("GPL v2");
- + 
- + static int __init ti81xx_glue_init(void)
- + {
- + 	return platform_driver_probe(&ti81xx_musb_driver, ti81xx_probe);
- + }
- + subsys_initcall(ti81xx_glue_init);
- + 
- + static void __exit ti81xx_glue_exit(void)
- + {
- + #ifdef CONFIG_USB_TI_CPPI41_DMA
- + 	/* free the usbss irq */
- + 	free_irq(TI81XX_IRQ_USBSS, 0);
- + #endif
- + 
- + 	/* disable the interrupts */
- + 	usbss_write(USBSS_IRQ_EOI, 0);
- + 	usbss_write(USBSS_IRQ_ENABLE_SET, 0);
- + 	usbss_write(USBSS_IRQ_DMA_ENABLE_0, 0);
- + 
- + 	/* unregister platform driver */
- + 	platform_driver_unregister(&ti81xx_musb_driver);
- + }
- + module_exit(ti81xx_glue_exit);
- diff -crN linux-3.2.1_o/drivers/usb/musb/ti81xx.h linux-3.2.1/drivers/usb/musb/ti81xx.h
- *** linux-3.2.1_o/drivers/usb/musb/ti81xx.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/drivers/usb/musb/ti81xx.h	2014-05-15 13:25:15.102588763 +0900
- ***************
- *** 0 ****
- --- 1,176 ----
- + /*
- +  * Copyright (C) 2005-2006 by Texas Instruments
- +  *
- +  * The Inventra Controller Driver for Linux is free software; you
- +  * can redistribute it and/or modify it under the terms of the GNU
- +  * General Public License version 2 as published by the Free Software
- +  * Foundation.
- +  */
- + 
- + #ifndef __MUSB_HDRDF_H__
- + #define __MUSB_HDRDF_H__
- + 
- + #define TI81XX_USB_CPPIDMA_BASE 0x47402000
- + #define TI81XX_USB_CPPIDMA_LEN  0x5FFF
- + #define TI81XX_IRQ_USBSS        17
- + 
- + /* Netra USB susbsystem register offsets */
- + #define USBSS_REVISION			0x0000
- + #define USBSS_SYSCONFIG			0x0010
- + /* USBSS EOI interrupt register */
- + #define USBSS_IRQ_EOI			0x0020
- + /* USBSS interrupt generation/status register */
- + #define USBSS_IRQ_STATUS_RAW		0x0024
- + /* USBSS interrupt status register */
- + #define USBSS_IRQ_STATUS		0x0028
- + /* USBSS interrupt enable register */
- + #define USBSS_IRQ_ENABLE_SET		0x002c
- + /* USBSS interrupt clear register */
- + #define USBSS_IRQ_ENABLE_CLEAR		0x0030
- + /* USB0: TxDMA 8bit tx completion interrupt pacing
- + 	threshold value for ep1..15 */
- + #define USBSS_IRQ_DMA_THRESHOLD_TX0	0x0100
- + /* USB0: RxDMA 8bit rx completion interrupt pacing
- + 	threshold value for ep1..15 */
- + #define USBSS_IRQ_DMA_THRESHOLD_RX0	0x0110
- + /* USB1: TxDMA 8bit tx completion interrupt pacing
- + 	threshold value for ep1..15 */
- + #define USBSS_IRQ_DMA_THRESHOLD_TX1	0x0120
- + /* USB1: RxDMA 8bit rx completion interrupt pacing
- + 	threshold value for ep1..15 */
- + #define USBSS_IRQ_DMA_THRESHOLD_RX1	0x0130
- + /* USB0: TxDMA threshold enable tx completion for ep1..ep15
- + 	RxDMA threshold enable rx completion for ep1..ep15 */
- + #define USBSS_IRQ_DMA_ENABLE_0		0x0140
- + /* USB1: TxDMA threshold enable for ep1..ep15
- + 	RxDMA threshold enable for ep1..ep15 */
- + #define USBSS_IRQ_DMA_ENABLE_1		0x0144
- + /* USB0: TxDMA Frame threshold for tx completion for ep1..ep15
- + 	RxDMA Frame threshold for rx completion for ep1..ep15 */
- + #define USBSS_IRQ_FRAME_THRESHOLD_TX0	0x0200
- + #define USBSS_IRQ_FRAME_THRESHOLD_RX0	0x0210
- + /* USB1: TxDMA Frame threshold for tx completion for ep1..ep15
- + 	RxDMA Frame threshold for rx completion for ep1..ep15 */
- + #define USBSS_IRQ_FRAME_THRESHOLD_TX1	0x0220
- + #define USBSS_IRQ_FRAME_THRESHOLD_RX1	0x0230
- + /* USB0: Frame threshold enable tx completion for ep1..ep15
- + 	Frame threshold enable rx completion for ep1..ep15 */
- + #define USBSS_IRQ_FRAME_ENABLE_0	0x0240
- + #define USBSS_IRQ_FRAME_ENABLE_1	0x0244
- + 
- + 
- + /* USB 2.0 OTG module registers */
- + #define USB_REVISION_REG        0x0000
- + #define USB_CTRL_REG            0x0014
- + #define USB_STAT_REG            0x0018
- + #define	USB_IRQ_MERGED_STATUS	0x0020
- + #define USB_IRQ_EOI		0x0024
- + #define	USB_IRQ_STATUS_RAW_0	0x0028
- + #define	USB_IRQ_STATUS_RAW_1	0x002c
- + #define	USB_IRQ_STATUS_0	0x0030
- + #define	USB_IRQ_STATUS_1	0x0034
- + #define	USB_IRQ_ENABLE_SET_0	0x0038
- + #define	USB_IRQ_ENABLE_SET_1	0x003c
- + #define	USB_IRQ_ENABLE_CLR_0	0x0040
- + #define	USB_IRQ_ENABLE_CLR_1	0x0044
- + 
- + #define USB_EP_INTR_SET_REG		(USB_IRQ_ENABLE_SET_0)
- + #define USB_CORE_INTR_SET_REG		(USB_IRQ_ENABLE_SET_1)
- + #define USB_EP_INTR_CLEAR_REG		(USB_IRQ_ENABLE_CLR_0)
- + #define USB_CORE_INTR_CLEAR_REG		(USB_IRQ_ENABLE_CLR_1)
- + #define USB_EP_INTR_STATUS_REG		(USB_IRQ_STATUS_0)
- + #define USB_CORE_INTR_STATUS_REG	(USB_IRQ_STATUS_1)
- + 
- + #define USB_GRNDIS_EPSIZE_OFFS	0X0080
- + #define USB_SRP_FIX_TIME_REG    0x00d4
- + #define USB_TH_XDMA_IDLE_REG    0x00dc
- + #define USB_PHY_UTMI_REG	0x00e0
- + #define USB_PHY_UTMI_LB_REG	0x00e4
- + #define USB_MODE_REG		0x00e8
- + 
- + #define QUEUE_THRESHOLD_INTR_ENABLE_REG 0xc0
- + #define QUEUE_63_THRESHOLD_REG  0xc4
- + #define QUEUE_63_THRESHOLD_INTR_CLEAR_REG 0xc8
- + #define QUEUE_65_THRESHOLD_REG  0xd4
- + #define QUEUE_65_THRESHOLD_INTR_CLEAR_REG 0xd8
- + 
- + /* Control register bits */
- + #define USB_SOFT_RESET_MASK     1
- + 
- + /* Mode register bits */
- + #define USB_MODE_SHIFT(n)       ((((n) - 1) << 1))
- + #define USB_MODE_MASK(n)        (3 << USB_MODE_SHIFT(n))
- + #define USB_RX_MODE_SHIFT(n)    USB_MODE_SHIFT(n)
- + #define USB_TX_MODE_SHIFT(n)    USB_MODE_SHIFT(n)
- + #define USB_RX_MODE_MASK(n)     USB_MODE_MASK(n)
- + #define USB_TX_MODE_MASK(n)     USB_MODE_MASK(n)
- + #define USB_TRANSPARENT_MODE    0
- + #define USB_RNDIS_MODE          1
- + #define USB_CDC_MODE            2
- + #define USB_GENERIC_RNDIS_MODE  3
- + 
- + /* AutoReq register bits */
- + #define USB_RX_AUTOREQ_SHIFT(n) (((n) - 1) << 1)
- + #define USB_RX_AUTOREQ_MASK(n)  (3 << USB_RX_AUTOREQ_SHIFT(n))
- + #define USB_NO_AUTOREQ          0
- + #define USB_AUTOREQ_ALL_BUT_EOP 1
- + #define USB_AUTOREQ_ALWAYS      3
- + 
- + /* Teardown register bits */
- + #define USB_TX_TDOWN_SHIFT(n)   (16 + (n))
- + #define USB_TX_TDOWN_MASK(n)    (1 << USB_TX_TDOWN_SHIFT(n))
- + #define USB_RX_TDOWN_SHIFT(n)   (n)
- + #define USB_RX_TDOWN_MASK(n)    (1 << USB_RX_TDOWN_SHIFT(n))
- + 
- + /* USB interrupt register bits */
- + #define USB_INTR_USB_SHIFT      0
- + #define USB_INTR_USB_MASK       (0x1ff << USB_INTR_USB_SHIFT) /* 8 Mentor */
- + #define USB_INTR_TXFIFO_MASK     (0xffff << 16)
- + #define USB_INTR_TXFIFO_EMPTY	17
- + 
- + 				/* interrupts and DRVVBUS interrupt */
- + #define USB_INTR_DRVVBUS        0x100
- + #define USB_INTR_RX_SHIFT       16
- + #define USB_INTR_TX_SHIFT       0
- + 
- + #define USB_MENTOR_CORE_OFFSET  0x400
- + #define USB_CPPI41_NUM_CH       15
- + 
- + #define MAX_MUSB_INSTANCE	2
- + /* CPPI 4.1 queue manager registers */
- + #define QMGR_PEND0_REG		0x4090
- + #define QMGR_PEND1_REG		0x4094
- + #define QMGR_PEND2_REG		0x4098
- + 
- + #define QMGR_RGN_OFFS		0x4000
- + #define QMRG_DESCRGN_OFFS	0x5000
- + #define QMGR_REG_OFFS		0x6000
- + #define QMGR_STAT_OFFS		0x7000
- + #define DMA_GLBCTRL_OFFS	0x2000
- + #define DMA_CHCTRL_OFFS		0x2800
- + #define DMA_SCHED_OFFS		0x3000
- + #define DMA_SCHEDTBL_OFFS	0x3800
- + 
- + #define USB_TX_EP_MASK		0xffff		/* EP0 + 15 Tx EPs */
- + #define USB_RX_EP_MASK		0xfffe		/* 15 Rx EPs */
- + 
- + #define USB_TX_INTR_MASK	(USB_TX_EP_MASK << USB_INTR_TX_SHIFT)
- + #define USB_RX_INTR_MASK	(USB_RX_EP_MASK << USB_INTR_RX_SHIFT)
- + 
- + #define A_WAIT_BCON_TIMEOUT	1100		/* in ms */
- + 
- + #define USBSS_INTR_RX_STARV	0x00000001
- + #define USBSS_INTR_PD_CMPL	0x00000004
- + #define USBSS_INTR_TX_CMPL	0x00000500
- + #define USBSS_INTR_RX_CMPL	0x00000A00
- + #define USBSS_INTR_FLAGS	(USBSS_INTR_PD_CMPL | USBSS_INTR_TX_CMPL \
- + 					| USBSS_INTR_RX_CMPL)
- + 
- + #define	USBMODE_USBID_MUXSEL	0x80
- + #define	USBMODE_USBID_HIGH	0x100
- + 
- + #define	USB0PORT_MODEMASK	0x0f
- + #define	USB1PORT_MODEMASK	0xf0
- + #define USB1PORT_MODESHIFT	4
- + extern void usb_nop_xceiv_register(int id);
- + #endif
- diff -crN linux-3.2.1_o/drivers/usb/musb/tusb6010.c linux-3.2.1/drivers/usb/musb/tusb6010.c
- *** linux-3.2.1_o/drivers/usb/musb/tusb6010.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/musb/tusb6010.c	2014-05-15 13:25:15.102588763 +0900
- ***************
- *** 40,50 ****
-    * Checks the revision. We need to use the DMA register as 3.0 does not
-    * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV.
-    */
- ! u8 tusb_get_revision(struct musb *musb)
-   {
-   	void __iomem	*tbase = musb->ctrl_base;
-   	u32		die_id;
- ! 	u8		rev;
-   
-   	rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;
-   	if (TUSB_REV_MAJOR(rev) == 3) {
- --- 40,50 ----
-    * Checks the revision. We need to use the DMA register as 3.0 does not
-    * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV.
-    */
- ! static u16 tusb_get_revision(struct musb *musb)
-   {
-   	void __iomem	*tbase = musb->ctrl_base;
-   	u32		die_id;
- ! 	u16		rev;
-   
-   	rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;
-   	if (TUSB_REV_MAJOR(rev) == 3) {
- ***************
- *** 56,66 ****
-   
-   	return rev;
-   }
-   
-   static int tusb_print_revision(struct musb *musb)
-   {
-   	void __iomem	*tbase = musb->ctrl_base;
- ! 	u8		rev;
-   
-   	rev = tusb_get_revision(musb);
-   
- --- 56,67 ----
-   
-   	return rev;
-   }
- + EXPORT_SYMBOL_GPL(tusb_get_revision);
-   
-   static int tusb_print_revision(struct musb *musb)
-   {
-   	void __iomem	*tbase = musb->ctrl_base;
- ! 	u16		rev;
-   
-   	rev = tusb_get_revision(musb);
-   
- ***************
- *** 171,177 ****
-   	}
-   }
-   
- ! void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
-   {
-   	struct musb *musb = hw_ep->musb;
-   	void __iomem	*ep_conf = hw_ep->conf;
- --- 172,179 ----
-   	}
-   }
-   
- ! static void tusb_musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
- ! 		const u8 *buf)
-   {
-   	struct musb *musb = hw_ep->musb;
-   	void __iomem	*ep_conf = hw_ep->conf;
- ***************
- *** 221,227 ****
-   		tusb_fifo_write_unaligned(fifo, buf, len);
-   }
-   
- ! void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
-   {
-   	struct musb *musb = hw_ep->musb;
-   	void __iomem	*ep_conf = hw_ep->conf;
- --- 223,229 ----
-   		tusb_fifo_write_unaligned(fifo, buf, len);
-   }
-   
- ! static void tusb_musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
-   {
-   	struct musb *musb = hw_ep->musb;
-   	void __iomem	*ep_conf = hw_ep->conf;
- ***************
- *** 854,860 ****
-   
-   		dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src);
-   		real_dma_src = ~real_dma_src & dma_src;
- ! 		if (tusb_dma_omap() && real_dma_src) {
-   			int	tx_source = (real_dma_src & 0xffff);
-   			int	i;
-   
- --- 856,862 ----
-   
-   		dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src);
-   		real_dma_src = ~real_dma_src & dma_src;
- ! 		if (tusb_dma_omap(musb) && real_dma_src) {
-   			int	tx_source = (real_dma_src & 0xffff);
-   			int	i;
-   
- ***************
- *** 1074,1081 ****
-   	void __iomem		*sync = NULL;
-   	int			ret;
-   
- ! 	usb_nop_xceiv_register();
- ! 	musb->xceiv = otg_get_transceiver();
-   	if (!musb->xceiv)
-   		return -ENODEV;
-   
- --- 1076,1083 ----
-   	void __iomem		*sync = NULL;
-   	int			ret;
-   
- ! 	usb_nop_xceiv_register(musb->id);
- ! 	musb->xceiv = otg_get_transceiver(musb->id);
-   	if (!musb->xceiv)
-   		return -ENODEV;
-   
- ***************
- *** 1128,1134 ****
-   			iounmap(sync);
-   
-   		otg_put_transceiver(musb->xceiv);
- ! 		usb_nop_xceiv_unregister();
-   	}
-   	return ret;
-   }
- --- 1130,1136 ----
-   			iounmap(sync);
-   
-   		otg_put_transceiver(musb->xceiv);
- ! 		usb_nop_xceiv_unregister(musb->id);
-   	}
-   	return ret;
-   }
- ***************
- *** 1144,1154 ****
-   	iounmap(musb->sync_va);
-   
-   	otg_put_transceiver(musb->xceiv);
- ! 	usb_nop_xceiv_unregister();
-   	return 0;
-   }
-   
-   static const struct musb_platform_ops tusb_ops = {
-   	.init		= tusb_musb_init,
-   	.exit		= tusb_musb_exit,
-   
- --- 1146,1159 ----
-   	iounmap(musb->sync_va);
-   
-   	otg_put_transceiver(musb->xceiv);
- ! 	usb_nop_xceiv_unregister(musb->id);
-   	return 0;
-   }
-   
-   static const struct musb_platform_ops tusb_ops = {
- + 	.fifo_mode	= 4,
- + 	.flags		= MUSB_GLUE_TUSB_STYLE |
- + 				MUSB_GLUE_EP_ADDR_INDEXED_MAPPING,
-   	.init		= tusb_musb_init,
-   	.exit		= tusb_musb_exit,
-   
- ***************
- *** 1158,1165 ****
- --- 1163,1177 ----
-   	.set_mode	= tusb_musb_set_mode,
-   	.try_idle	= tusb_musb_try_idle,
-   
- + 	.get_hw_revision	= tusb_get_revision,
- + 
-   	.vbus_status	= tusb_musb_vbus_status,
-   	.set_vbus	= tusb_musb_set_vbus,
- + 	.read_fifo	= tusb_musb_read_fifo,
- + 	.write_fifo	= tusb_musb_write_fifo,
- + 
- + 	.dma_controller_create = tusb_dma_controller_create,
- + 	.dma_controller_destroy = tusb_dma_controller_destroy,
-   };
-   
-   static u64 tusb_dmamask = DMA_BIT_MASK(32);
- diff -crN linux-3.2.1_o/drivers/usb/musb/tusb6010.h linux-3.2.1/drivers/usb/musb/tusb6010.h
- *** linux-3.2.1_o/drivers/usb/musb/tusb6010.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/musb/tusb6010.h	2014-05-15 13:25:15.102588763 +0900
- ***************
- *** 12,31 ****
-   #ifndef __TUSB6010_H__
-   #define __TUSB6010_H__
-   
- - extern u8 tusb_get_revision(struct musb *musb);
- - 
- - #ifdef CONFIG_USB_TUSB6010
- - #define musb_in_tusb()			1
- - #else
- - #define musb_in_tusb()			0
- - #endif
- - 
- - #ifdef CONFIG_USB_TUSB_OMAP_DMA
- - #define tusb_dma_omap()			1
- - #else
- - #define tusb_dma_omap()			0
- - #endif
- - 
-   /* VLYNQ control register. 32-bit at offset 0x000 */
-   #define TUSB_VLYNQ_CTRL			0x004
-   
- --- 12,17 ----
- diff -crN linux-3.2.1_o/drivers/usb/musb/tusb6010_omap.c linux-3.2.1/drivers/usb/musb/tusb6010_omap.c
- *** linux-3.2.1_o/drivers/usb/musb/tusb6010_omap.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/musb/tusb6010_omap.c	2014-05-15 13:25:15.106705759 +0900
- ***************
- *** 178,189 ****
-   			dma_unmap_single(dev, chdat->dma_addr,
-   						chdat->transfer_len,
-   						DMA_TO_DEVICE);
- ! 			musb_write_fifo(hw_ep, pio, buf);
-   		} else {
-   			dma_unmap_single(dev, chdat->dma_addr,
-   						chdat->transfer_len,
-   						DMA_FROM_DEVICE);
- ! 			musb_read_fifo(hw_ep, pio, buf);
-   		}
-   		channel->actual_len += pio;
-   	}
- --- 178,189 ----
-   			dma_unmap_single(dev, chdat->dma_addr,
-   						chdat->transfer_len,
-   						DMA_TO_DEVICE);
- ! 			musb->ops->write_fifo(hw_ep, pio, buf);
-   		} else {
-   			dma_unmap_single(dev, chdat->dma_addr,
-   						chdat->transfer_len,
-   						DMA_FROM_DEVICE);
- ! 			musb->ops->read_fifo(hw_ep, pio, buf);
-   		}
-   		channel->actual_len += pio;
-   	}
- ***************
- *** 211,217 ****
-   
-   		if (chdat->tx) {
-   			dev_dbg(musb->controller, "terminating short tx packet\n");
- ! 			musb_ep_select(mbase, chdat->epnum);
-   			csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
-   			csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY
-   				| MUSB_TXCSR_P_WZC_BITS;
- --- 211,217 ----
-   
-   		if (chdat->tx) {
-   			dev_dbg(musb->controller, "terminating short tx packet\n");
- ! 			musb_ep_select(musb, mbase, chdat->epnum);
-   			csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
-   			csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY
-   				| MUSB_TXCSR_P_WZC_BITS;
- ***************
- *** 386,399 ****
-   	 * Prepare MUSB for DMA transfer
-   	 */
-   	if (chdat->tx) {
- ! 		musb_ep_select(mbase, chdat->epnum);
-   		csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
-   		csr |= (MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB
-   			| MUSB_TXCSR_DMAMODE | MUSB_TXCSR_MODE);
-   		csr &= ~MUSB_TXCSR_P_UNDERRUN;
-   		musb_writew(hw_ep->regs, MUSB_TXCSR, csr);
-   	} else {
- ! 		musb_ep_select(mbase, chdat->epnum);
-   		csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
-   		csr |= MUSB_RXCSR_DMAENAB;
-   		csr &= ~(MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAMODE);
- --- 386,399 ----
-   	 * Prepare MUSB for DMA transfer
-   	 */
-   	if (chdat->tx) {
- ! 		musb_ep_select(musb, mbase, chdat->epnum);
-   		csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
-   		csr |= (MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB
-   			| MUSB_TXCSR_DMAMODE | MUSB_TXCSR_MODE);
-   		csr &= ~MUSB_TXCSR_P_UNDERRUN;
-   		musb_writew(hw_ep->regs, MUSB_TXCSR, csr);
-   	} else {
- ! 		musb_ep_select(musb, mbase, chdat->epnum);
-   		csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
-   		csr |= MUSB_RXCSR_DMAENAB;
-   		csr &= ~(MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAMODE);
- ***************
- *** 642,648 ****
-   	channel = NULL;
-   }
-   
- ! void dma_controller_destroy(struct dma_controller *c)
-   {
-   	struct tusb_omap_dma	*tusb_dma;
-   	int			i;
- --- 642,648 ----
-   	channel = NULL;
-   }
-   
- ! void tusb_dma_controller_destroy(struct dma_controller *c)
-   {
-   	struct tusb_omap_dma	*tusb_dma;
-   	int			i;
- ***************
- *** 661,669 ****
-   
-   	kfree(tusb_dma);
-   }
-   
- ! struct dma_controller *__init
- ! dma_controller_create(struct musb *musb, void __iomem *base)
-   {
-   	void __iomem		*tbase = musb->ctrl_base;
-   	struct tusb_omap_dma	*tusb_dma;
- --- 661,670 ----
-   
-   	kfree(tusb_dma);
-   }
- + EXPORT_SYMBOL(tusb_dma_controller_destroy);
-   
- ! struct dma_controller *__devinit
- ! tusb_dma_controller_create(struct musb *musb, void __iomem *base)
-   {
-   	void __iomem		*tbase = musb->ctrl_base;
-   	struct tusb_omap_dma	*tusb_dma;
- ***************
- *** 697,703 ****
-   	tusb_dma->controller.channel_program = tusb_omap_dma_program;
-   	tusb_dma->controller.channel_abort = tusb_omap_dma_abort;
-   
- ! 	if (tusb_get_revision(musb) >= TUSB_REV_30)
-   		tusb_dma->multichannel = 1;
-   
-   	for (i = 0; i < MAX_DMAREQ; i++) {
- --- 698,704 ----
-   	tusb_dma->controller.channel_program = tusb_omap_dma_program;
-   	tusb_dma->controller.channel_abort = tusb_omap_dma_abort;
-   
- ! 	if (musb_platform_get_hw_revision(musb) >= TUSB_REV_30)
-   		tusb_dma->multichannel = 1;
-   
-   	for (i = 0; i < MAX_DMAREQ; i++) {
- ***************
- *** 721,727 ****
-   	return &tusb_dma->controller;
-   
-   cleanup:
- ! 	dma_controller_destroy(&tusb_dma->controller);
-   out:
-   	return NULL;
-   }
- --- 722,743 ----
-   	return &tusb_dma->controller;
-   
-   cleanup:
- ! 	tusb_dma_controller_destroy(&tusb_dma->controller);
-   out:
-   	return NULL;
-   }
- + EXPORT_SYMBOL(tusb_dma_controller_create);
- + 
- + MODULE_DESCRIPTION("TUSB dma controller driver for musb");
- + MODULE_LICENSE("GPL v2");
- + 
- + static int __init tusb_dma_init(void)
- + {
- + 	return 0;
- + }
- + module_init(tusb_dma_init);
- + 
- + static void __exit tusb_dma__exit(void)
- + {
- + }
- + module_exit(tusb_dma__exit);
- diff -crN linux-3.2.1_o/drivers/usb/musb/ux500.c linux-3.2.1/drivers/usb/musb/ux500.c
- *** linux-3.2.1_o/drivers/usb/musb/ux500.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/musb/ux500.c	2014-05-15 13:25:15.106705759 +0900
- ***************
- *** 54,59 ****
- --- 54,60 ----
-   }
-   
-   static const struct musb_platform_ops ux500_ops = {
- + 	.fifo_mode	= 5,
-   	.init		= ux500_musb_init,
-   	.exit		= ux500_musb_exit,
-   };
- diff -crN linux-3.2.1_o/drivers/usb/musb/ux500_dma.c linux-3.2.1/drivers/usb/musb/ux500_dma.c
- *** linux-3.2.1_o/drivers/usb/musb/ux500_dma.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/musb/ux500_dma.c	2014-05-15 13:25:15.106705759 +0900
- ***************
- *** 37,43 ****
-   	struct dma_channel channel;
-   	struct ux500_dma_controller *controller;
-   	struct musb_hw_ep *hw_ep;
- - 	struct work_struct channel_work;
-   	struct dma_chan *dma_chan;
-   	unsigned int cur_len;
-   	dma_cookie_t cookie;
- --- 37,42 ----
- ***************
- *** 56,86 ****
-   	dma_addr_t phy_base;
-   };
-   
- - /* Work function invoked from DMA callback to handle tx transfers. */
- - static void ux500_tx_work(struct work_struct *data)
- - {
- - 	struct ux500_dma_channel *ux500_channel = container_of(data,
- - 		struct ux500_dma_channel, channel_work);
- - 	struct musb_hw_ep       *hw_ep = ux500_channel->hw_ep;
- - 	struct musb *musb = hw_ep->musb;
- - 	unsigned long flags;
- - 
- - 	dev_dbg(musb->controller, "DMA tx transfer done on hw_ep=%d\n",
- - 		hw_ep->epnum);
- - 
- - 	spin_lock_irqsave(&musb->lock, flags);
- - 	ux500_channel->channel.actual_len = ux500_channel->cur_len;
- - 	ux500_channel->channel.status = MUSB_DMA_STATUS_FREE;
- - 	musb_dma_completion(musb, hw_ep->epnum,
- - 				ux500_channel->is_tx);
- - 	spin_unlock_irqrestore(&musb->lock, flags);
- - }
- - 
-   /* Work function invoked from DMA callback to handle rx transfers. */
- ! static void ux500_rx_work(struct work_struct *data)
-   {
- ! 	struct ux500_dma_channel *ux500_channel = container_of(data,
- ! 		struct ux500_dma_channel, channel_work);
-   	struct musb_hw_ep       *hw_ep = ux500_channel->hw_ep;
-   	struct musb *musb = hw_ep->musb;
-   	unsigned long flags;
- --- 55,65 ----
-   	dma_addr_t phy_base;
-   };
-   
-   /* Work function invoked from DMA callback to handle rx transfers. */
- ! void ux500_dma_callback(void *private_data)
-   {
- ! 	struct dma_channel *channel = private_data;
- ! 	struct ux500_dma_channel *ux500_channel = channel->private_data;
-   	struct musb_hw_ep       *hw_ep = ux500_channel->hw_ep;
-   	struct musb *musb = hw_ep->musb;
-   	unsigned long flags;
- ***************
- *** 94,107 ****
-   	musb_dma_completion(musb, hw_ep->epnum,
-   		ux500_channel->is_tx);
-   	spin_unlock_irqrestore(&musb->lock, flags);
- - }
- - 
- - void ux500_dma_callback(void *private_data)
- - {
- - 	struct dma_channel *channel = (struct dma_channel *)private_data;
- - 	struct ux500_dma_channel *ux500_channel = channel->private_data;
-   
- - 	schedule_work(&ux500_channel->channel_work);
-   }
-   
-   static bool ux500_configure_channel(struct dma_channel *channel,
- --- 73,79 ----
- ***************
- *** 330,336 ****
-   	void **param_array;
-   	struct ux500_dma_channel *channel_array;
-   	u32 ch_count;
- - 	void (*musb_channel_work)(struct work_struct *);
-   	dma_cap_mask_t mask;
-   
-   	if ((data->num_rx_channels > UX500_MUSB_DMA_NUM_RX_CHANNELS) ||
- --- 302,307 ----
- ***************
- *** 347,353 ****
-   	channel_array = controller->rx_channel;
-   	ch_count = data->num_rx_channels;
-   	param_array = data->dma_rx_param_array;
- - 	musb_channel_work = ux500_rx_work;
-   
-   	for (dir = 0; dir < 2; dir++) {
-   		for (ch_num = 0; ch_num < ch_count; ch_num++) {
- --- 318,323 ----
- ***************
- *** 374,388 ****
-   				return -EBUSY;
-   			}
-   
- - 			INIT_WORK(&ux500_channel->channel_work,
- - 				musb_channel_work);
-   		}
-   
-   		/* Prepare the loop for TX channels */
-   		channel_array = controller->tx_channel;
-   		ch_count = data->num_tx_channels;
-   		param_array = data->dma_tx_param_array;
- - 		musb_channel_work = ux500_tx_work;
-   		is_tx = 1;
-   	}
-   
- --- 344,355 ----
- diff -crN linux-3.2.1_o/drivers/usb/otg/nop-usb-xceiv.c linux-3.2.1/drivers/usb/otg/nop-usb-xceiv.c
- *** linux-3.2.1_o/drivers/usb/otg/nop-usb-xceiv.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/otg/nop-usb-xceiv.c	2014-05-15 13:25:15.106705759 +0900
- ***************
- *** 37,60 ****
-   	struct device		*dev;
-   };
-   
- ! static struct platform_device *pd;
-   
- ! void usb_nop_xceiv_register(void)
-   {
- ! 	if (pd)
-   		return;
- ! 	pd = platform_device_register_simple("nop_usb_xceiv", -1, NULL, 0);
- ! 	if (!pd) {
-   		printk(KERN_ERR "Unable to register usb nop transceiver\n");
-   		return;
-   	}
-   }
-   EXPORT_SYMBOL(usb_nop_xceiv_register);
-   
- ! void usb_nop_xceiv_unregister(void)
-   {
- ! 	platform_device_unregister(pd);
- ! 	pd = NULL;
-   }
-   EXPORT_SYMBOL(usb_nop_xceiv_unregister);
-   
- --- 37,60 ----
-   	struct device		*dev;
-   };
-   
- ! static struct platform_device *pd[2] = {NULL, NULL};
-   
- ! void usb_nop_xceiv_register(int id)
-   {
- ! 	if (pd[id])
-   		return;
- ! 	pd[id] = platform_device_register_simple("nop_usb_xceiv", id, NULL, 0);
- ! 	if (!pd[id]) {
-   		printk(KERN_ERR "Unable to register usb nop transceiver\n");
-   		return;
-   	}
-   }
-   EXPORT_SYMBOL(usb_nop_xceiv_register);
-   
- ! void usb_nop_xceiv_unregister(int id)
-   {
- ! 	platform_device_unregister(pd[id]);
- ! 	pd[id] = NULL;
-   }
-   EXPORT_SYMBOL(usb_nop_xceiv_unregister);
-   
- ***************
- *** 122,127 ****
- --- 122,128 ----
-   	nop->otg.set_host	= nop_set_host;
-   	nop->otg.set_peripheral	= nop_set_peripheral;
-   	nop->otg.set_suspend	= nop_set_suspend;
- + 	nop->otg.id		= pdev->id;
-   
-   	err = otg_set_transceiver(&nop->otg);
-   	if (err) {
- ***************
- *** 144,150 ****
-   {
-   	struct nop_usb_xceiv *nop = platform_get_drvdata(pdev);
-   
- ! 	otg_set_transceiver(NULL);
-   
-   	platform_set_drvdata(pdev, NULL);
-   	kfree(nop);
- --- 145,151 ----
-   {
-   	struct nop_usb_xceiv *nop = platform_get_drvdata(pdev);
-   
- ! 	otg_reset_transceiver(&nop->otg);
-   
-   	platform_set_drvdata(pdev, NULL);
-   	kfree(nop);
- diff -crN linux-3.2.1_o/drivers/usb/otg/otg.c linux-3.2.1/drivers/usb/otg/otg.c
- *** linux-3.2.1_o/drivers/usb/otg/otg.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/otg/otg.c	2014-05-15 13:25:15.106705759 +0900
- ***************
- *** 15,21 ****
-   
-   #include <linux/usb/otg.h>
-   
- ! static struct otg_transceiver *xceiv;
-   
-   /**
-    * otg_get_transceiver - find the (single) OTG transceiver
- --- 15,21 ----
-   
-   #include <linux/usb/otg.h>
-   
- ! static struct otg_transceiver *xceiv[2];
-   
-   /**
-    * otg_get_transceiver - find the (single) OTG transceiver
- ***************
- *** 26,36 ****
-    *
-    * For use by USB host and peripheral drivers.
-    */
- ! struct otg_transceiver *otg_get_transceiver(void)
-   {
- ! 	if (xceiv)
- ! 		get_device(xceiv->dev);
- ! 	return xceiv;
-   }
-   EXPORT_SYMBOL(otg_get_transceiver);
-   
- --- 26,36 ----
-    *
-    * For use by USB host and peripheral drivers.
-    */
- ! struct otg_transceiver *otg_get_transceiver(int id)
-   {
- ! 	if (xceiv[id])
- ! 		get_device(xceiv[id]->dev);
- ! 	return xceiv[id];
-   }
-   EXPORT_SYMBOL(otg_get_transceiver);
-   
- ***************
- *** 59,71 ****
-    */
-   int otg_set_transceiver(struct otg_transceiver *x)
-   {
- ! 	if (xceiv && x)
-   		return -EBUSY;
- ! 	xceiv = x;
-   	return 0;
-   }
-   EXPORT_SYMBOL(otg_set_transceiver);
-   
-   const char *otg_state_string(enum usb_otg_state state)
-   {
-   	switch (state) {
- --- 59,88 ----
-    */
-   int otg_set_transceiver(struct otg_transceiver *x)
-   {
- ! 	if ( x && xceiv[x->id])
-   		return -EBUSY;
- ! 	xceiv[x->id] = x;
-   	return 0;
-   }
-   EXPORT_SYMBOL(otg_set_transceiver);
-   
- + 
- + /**
- +  * otg_set_transceiver - declare the (single) OTG transceiver
- +  * @x: the USB OTG transceiver to be used; or NULL
- +  *
- +  * This call is exclusively for use by transceiver drivers, which
- +  * coordinate the activities of drivers for host and peripheral
- +  * controllers, and in some cases for VBUS current regulation.
- +  */
- + int otg_reset_transceiver(struct otg_transceiver *x)
- + {
- + 	if (x && xceiv[x->id])
- + 		xceiv[x->id] = NULL;
- + 	return 0;
- + }
- + EXPORT_SYMBOL(otg_reset_transceiver);
- + 
-   const char *otg_state_string(enum usb_otg_state state)
-   {
-   	switch (state) {
- diff -crN linux-3.2.1_o/drivers/usb/renesas_usbhs/mod_gadget.c linux-3.2.1/drivers/usb/renesas_usbhs/mod_gadget.c
- *** linux-3.2.1_o/drivers/usb/renesas_usbhs/mod_gadget.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/renesas_usbhs/mod_gadget.c	2014-05-15 13:25:15.106705759 +0900
- ***************
- *** 755,761 ****
-   
-   	if (!driver		||
-   	    !driver->setup	||
- ! 	    driver->speed < USB_SPEED_FULL)
-   		return -EINVAL;
-   
-   	/* first hook up the driver ... */
- --- 755,761 ----
-   
-   	if (!driver		||
-   	    !driver->setup	||
- ! 	    driver->max_speed < USB_SPEED_FULL)
-   		return -EINVAL;
-   
-   	/* first hook up the driver ... */
- ***************
- *** 866,872 ****
-   	gpriv->gadget.dev.parent	= dev;
-   	gpriv->gadget.name		= "renesas_usbhs_udc";
-   	gpriv->gadget.ops		= &usbhsg_gadget_ops;
- ! 	gpriv->gadget.is_dualspeed	= 1;
-   	ret = device_register(&gpriv->gadget.dev);
-   	if (ret < 0)
-   		goto err_add_udc;
- --- 866,872 ----
-   	gpriv->gadget.dev.parent	= dev;
-   	gpriv->gadget.name		= "renesas_usbhs_udc";
-   	gpriv->gadget.ops		= &usbhsg_gadget_ops;
- ! 	gpriv->gadget.max_speed		= USB_SPEED_HIGH;
-   	ret = device_register(&gpriv->gadget.dev);
-   	if (ret < 0)
-   		goto err_add_udc;
- diff -crN linux-3.2.1_o/drivers/usb/serial/cp210x.c linux-3.2.1/drivers/usb/serial/cp210x.c
- *** linux-3.2.1_o/drivers/usb/serial/cp210x.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/serial/cp210x.c	2014-05-15 13:25:15.110892592 +0900
- ***************
- *** 92,98 ****
-   	{ USB_DEVICE(0x10C4, 0x818B) }, /* AVIT Research USB to TTL */
-   	{ USB_DEVICE(0x10C4, 0x819F) }, /* MJS USB Toslink Switcher */
-   	{ USB_DEVICE(0x10C4, 0x81A6) }, /* ThinkOptics WavIt */
- - 	{ USB_DEVICE(0x10C4, 0x81A9) }, /* Multiplex RC Interface */
-   	{ USB_DEVICE(0x10C4, 0x81AC) }, /* MSD Dash Hawk */
-   	{ USB_DEVICE(0x10C4, 0x81AD) }, /* INSYS USB Modem */
-   	{ USB_DEVICE(0x10C4, 0x81C8) }, /* Lipowsky Industrie Elektronik GmbH, Baby-JTAG */
- --- 92,97 ----
- diff -crN linux-3.2.1_o/drivers/usb/serial/omninet.c linux-3.2.1/drivers/usb/serial/omninet.c
- *** linux-3.2.1_o/drivers/usb/serial/omninet.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/serial/omninet.c	2014-05-15 13:25:15.110892592 +0900
- ***************
- *** 315,321 ****
-   	int room = 0; /* Default: no room */
-   
-   	/* FIXME: no consistent locking for write_urb_busy */
- ! 	if (!wport->write_urb_busy)
-   		room = wport->bulk_out_size - OMNINET_HEADERLEN;
-   
-   	dbg("%s - returns %d", __func__, room);
- --- 315,321 ----
-   	int room = 0; /* Default: no room */
-   
-   	/* FIXME: no consistent locking for write_urb_busy */
- ! 	if (wport->write_urb_busy)
-   		room = wport->bulk_out_size - OMNINET_HEADERLEN;
-   
-   	dbg("%s - returns %d", __func__, room);
- diff -crN linux-3.2.1_o/drivers/usb/serial/option.c linux-3.2.1/drivers/usb/serial/option.c
- *** linux-3.2.1_o/drivers/usb/serial/option.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/serial/option.c	2014-05-15 13:25:15.110892592 +0900
- ***************
- *** 476,485 ****
-   #define VIETTEL_VENDOR_ID			0x2262
-   #define VIETTEL_PRODUCT_VT1000			0x0002
-   
- - /* ZD Incorporated */
- - #define ZD_VENDOR_ID				0x0685
- - #define ZD_PRODUCT_7000				0x7000
- - 
-   /* some devices interfaces need special handling due to a number of reasons */
-   enum option_blacklist_reason {
-   		OPTION_BLACKLIST_NONE = 0,
- --- 476,481 ----
- ***************
- *** 1182,1188 ****
-   	{ USB_DEVICE(YUGA_VENDOR_ID, YUGA_PRODUCT_CLU528) },
-   	{ USB_DEVICE(YUGA_VENDOR_ID, YUGA_PRODUCT_CLU526) },
-   	{ USB_DEVICE_AND_INTERFACE_INFO(VIETTEL_VENDOR_ID, VIETTEL_PRODUCT_VT1000, 0xff, 0xff, 0xff) },
- - 	{ USB_DEVICE_AND_INTERFACE_INFO(ZD_VENDOR_ID, ZD_PRODUCT_7000, 0xff, 0xff, 0xff) },
-   	{ } /* Terminating entry */
-   };
-   MODULE_DEVICE_TABLE(usb, option_ids);
- --- 1178,1183 ----
- diff -crN linux-3.2.1_o/drivers/usb/storage/usb.c linux-3.2.1/drivers/usb/storage/usb.c
- *** linux-3.2.1_o/drivers/usb/storage/usb.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/usb/storage/usb.c	2014-05-15 13:25:15.110892592 +0900
- ***************
- *** 1073,1079 ****
-   	.id_table =	usb_storage_usb_ids,
-   	.supports_autosuspend = 1,
-   	.soft_unbind =	1,
- - 	.no_dynamic_id = 1,
-   };
-   
-   static int __init usb_stor_init(void)
- --- 1073,1078 ----
- diff -crN linux-3.2.1_o/drivers/video/backlight/Kconfig linux-3.2.1/drivers/video/backlight/Kconfig
- *** linux-3.2.1_o/drivers/video/backlight/Kconfig	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/video/backlight/Kconfig	2014-05-15 13:25:15.114583196 +0900
- ***************
- *** 342,347 ****
- --- 342,355 ----
-   	  If you have a AnalogicTech AAT2870 say Y to enable the
-   	  backlight driver.
-   
- + config BACKLIGHT_TLC59108
- + 	tristate "TLC59108 LCD Backlight Driver"
- + 	depends on I2C && BACKLIGHT_CLASS_DEVICE
- + 	default n
- + 	help
- + 	  If you have an LCD Panel with backlight control via TLC59108,
- + 	  say Y to enable its LCD control driver.
- + 
-   endif # BACKLIGHT_CLASS_DEVICE
-   
-   endif # BACKLIGHT_LCD_SUPPORT
- diff -crN linux-3.2.1_o/drivers/video/backlight/Makefile linux-3.2.1/drivers/video/backlight/Makefile
- *** linux-3.2.1_o/drivers/video/backlight/Makefile	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/video/backlight/Makefile	2014-05-15 13:25:15.114583196 +0900
- ***************
- *** 39,42 ****
- --- 39,43 ----
-   obj-$(CONFIG_BACKLIGHT_88PM860X) += 88pm860x_bl.o
-   obj-$(CONFIG_BACKLIGHT_PCF50633)	+= pcf50633-backlight.o
-   obj-$(CONFIG_BACKLIGHT_AAT2870) += aat2870_bl.o
- + obj-$(CONFIG_BACKLIGHT_TLC59108)	+= tlc59108.o
-   
- diff -crN linux-3.2.1_o/drivers/video/backlight/pwm_bl.c linux-3.2.1/drivers/video/backlight/pwm_bl.c
- *** linux-3.2.1_o/drivers/video/backlight/pwm_bl.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/video/backlight/pwm_bl.c	2014-05-15 13:25:15.114583196 +0900
- ***************
- *** 17,23 ****
-   #include <linux/fb.h>
-   #include <linux/backlight.h>
-   #include <linux/err.h>
- ! #include <linux/pwm.h>
-   #include <linux/pwm_backlight.h>
-   #include <linux/slab.h>
-   
- --- 17,23 ----
-   #include <linux/fb.h>
-   #include <linux/backlight.h>
-   #include <linux/err.h>
- ! #include <linux/pwm/pwm.h>
-   #include <linux/pwm_backlight.h>
-   #include <linux/slab.h>
-   
- ***************
- *** 49,61 ****
-   		brightness = pb->notify(pb->dev, brightness);
-   
-   	if (brightness == 0) {
- ! 		pwm_config(pb->pwm, 0, pb->period);
- ! 		pwm_disable(pb->pwm);
-   	} else {
-   		brightness = pb->lth_brightness +
-   			(brightness * (pb->period - pb->lth_brightness) / max);
- ! 		pwm_config(pb->pwm, brightness, pb->period);
- ! 		pwm_enable(pb->pwm);
-   	}
-   
-   	if (pb->notify_after)
- --- 49,62 ----
-   		brightness = pb->notify(pb->dev, brightness);
-   
-   	if (brightness == 0) {
- ! 		pwm_set_duty_ns(pb->pwm, 0);
- ! 		pwm_stop(pb->pwm);
-   	} else {
-   		brightness = pb->lth_brightness +
-   			(brightness * (pb->period - pb->lth_brightness) / max);
- ! 		pwm_set_period_ns(pb->pwm, pb->period);
- ! 		pwm_set_duty_ns(pb->pwm, brightness);
- ! 		pwm_start(pb->pwm);
-   	}
-   
-   	if (pb->notify_after)
- ***************
- *** 117,123 ****
-   		(data->pwm_period_ns / data->max_brightness);
-   	pb->dev = &pdev->dev;
-   
- ! 	pb->pwm = pwm_request(data->pwm_id, "backlight");
-   	if (IS_ERR(pb->pwm)) {
-   		dev_err(&pdev->dev, "unable to request PWM for backlight\n");
-   		ret = PTR_ERR(pb->pwm);
- --- 118,124 ----
-   		(data->pwm_period_ns / data->max_brightness);
-   	pb->dev = &pdev->dev;
-   
- ! 	pb->pwm = pwm_request(data->pwm_id, data->ch, "backlight");
-   	if (IS_ERR(pb->pwm)) {
-   		dev_err(&pdev->dev, "unable to request PWM for backlight\n");
-   		ret = PTR_ERR(pb->pwm);
- ***************
- *** 143,149 ****
-   	return 0;
-   
-   err_bl:
- ! 	pwm_free(pb->pwm);
-   err_pwm:
-   	kfree(pb);
-   err_alloc:
- --- 144,150 ----
-   	return 0;
-   
-   err_bl:
- ! 	pwm_release(pb->pwm);
-   err_pwm:
-   	kfree(pb);
-   err_alloc:
- ***************
- *** 159,167 ****
-   	struct pwm_bl_data *pb = dev_get_drvdata(&bl->dev);
-   
-   	backlight_device_unregister(bl);
- ! 	pwm_config(pb->pwm, 0, pb->period);
- ! 	pwm_disable(pb->pwm);
- ! 	pwm_free(pb->pwm);
-   	kfree(pb);
-   	if (data->exit)
-   		data->exit(&pdev->dev);
- --- 160,168 ----
-   	struct pwm_bl_data *pb = dev_get_drvdata(&bl->dev);
-   
-   	backlight_device_unregister(bl);
- ! 	pwm_set_duty_ns(pb->pwm, 0);
- ! 	pwm_stop(pb->pwm);
- ! 	pwm_release(pb->pwm);
-   	kfree(pb);
-   	if (data->exit)
-   		data->exit(&pdev->dev);
- ***************
- *** 177,186 ****
-   
-   	if (pb->notify)
-   		pb->notify(pb->dev, 0);
- ! 	pwm_config(pb->pwm, 0, pb->period);
- ! 	pwm_disable(pb->pwm);
- ! 	if (pb->notify_after)
- ! 		pb->notify_after(pb->dev, 0);
-   	return 0;
-   }
-   
- --- 178,185 ----
-   
-   	if (pb->notify)
-   		pb->notify(pb->dev, 0);
- ! 	pwm_set_duty_ns(pb->pwm, 0);
- ! 	pwm_stop(pb->pwm);
-   	return 0;
-   }
-   
- diff -crN linux-3.2.1_o/drivers/video/backlight/tlc59108.c linux-3.2.1/drivers/video/backlight/tlc59108.c
- *** linux-3.2.1_o/drivers/video/backlight/tlc59108.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/drivers/video/backlight/tlc59108.c	2014-05-15 13:25:15.114583196 +0900
- ***************
- *** 0 ****
- --- 1,170 ----
- + /*
- +  * ti81xxhdmi_tlc59108.c
- +  *
- +  * Copyright (C) 2011 Texas Instruments
- +  * Author: Senthil Natarajan
- +  *
- +  * tlc59108 HDMI Driver
- +  *
- +  * This program is free software; you can redistribute it and/or modify it
- +  * under the terms of the GNU General Public License version 2 as published by
- +  * the Free Software Foundation.
- +  *
- +  * This program is distributed in the hope that it will be useful, but WITHOUT
- +  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- +  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- +  * more details.
- +  *
- +  * You should have received a copy of the GNU General Public License along with
- +  * this program.  If not, see <http://www.gnu.org/licenses/>.
- +  * History:
- +  *
- +  * Senthil Natarajan<senthil.n@ti.com> July 2011 I2C driver for tlc59108
- +  *						 backlight control
- +  */
- + 
- + #include <linux/i2c.h>
- + #include <linux/kernel.h>
- + #include <linux/module.h>
- + #include <linux/backlight.h>
- + #include <linux/fb.h>
- + 
- + #define tlc59108_MODULE_NAME	"tlc59108"
- + #define TLC59108_MODE1   0x00
- + #define TLC59108_PWM2    0x04
- + #define TLC59108_LEDOUT0 0x0c
- + #define TLC59108_LEDOUT1 0x0d
- + #define TLC59108_MAX_BRIGHTNESS 0xFF
- + 
- + struct tlc59108_bl {
- + 	struct i2c_client *client;
- + 	struct backlight_device *bl;
- + };
- + 
- + static void tlc59108_bl_set_backlight(struct tlc59108_bl *data, int brightness)
- + {
- + 	/* Set Mode1 Register */
- + 	i2c_smbus_write_byte_data(data->client, TLC59108_MODE1, 0x00);
- + 
- + 	/* Set LEDOUT0 Register */
- + 	i2c_smbus_write_byte_data(data->client, TLC59108_LEDOUT0, 0x21);
- + 
- + 	/* Set Backlight Duty Cycle*/
- + 	i2c_smbus_write_byte_data(data->client, TLC59108_PWM2,
- + 				  brightness & 0xff);
- + }
- + 
- + static int tlc59108_bl_get_brightness(struct backlight_device *dev)
- + {
- + 	struct backlight_properties *props = &dev->props;
- + 
- + 	return props->brightness;
- + }
- + 
- + static int tlc59108_bl_update_status(struct backlight_device *dev)
- + {
- + 	struct backlight_properties *props = &dev->props;
- + 	struct tlc59108_bl *data = dev_get_drvdata(&dev->dev);
- + 	int brightness = props->brightness;
- + 
- + 	tlc59108_bl_set_backlight(data, brightness);
- + 
- + 	return 0;
- + }
- + 
- + static const struct backlight_ops bl_ops = {
- + 	.get_brightness		= tlc59108_bl_get_brightness,
- + 	.update_status		= tlc59108_bl_update_status,
- + };
- + 
- + static int tlc59108_probe(struct i2c_client *c, const struct i2c_device_id *id)
- + {
- + 	struct backlight_properties props;
- + 	struct tlc59108_bl *data = kzalloc(sizeof(struct tlc59108_bl),
- + 					   GFP_KERNEL);
- + 	int ret = 0;
- + 
- + 	if (!data)
- + 		return -ENOMEM;
- + 
- + 	i2c_set_clientdata(c, data);
- + 	data->client = c;
- + 
- + 	/* FIXME: This is definitely how it should be done.
- + 	 * Someone more familiar with the framework needs to make it proper
- + 	 */
- + 	if (cpu_is_am335x()) {
- + 		/* Set LED4 to always on in LEDOUT1 Register*/
- + 		ret = i2c_smbus_write_byte_data(data->client, TLC59108_LEDOUT1, 0x01);
- + 		if(ret < 0)
- + 			pr_err("Could not set LED4 to fully on\n");
- + 	}
- + 
- + 	memset(&props, 0, sizeof(struct backlight_properties));
- + 	props.max_brightness = TLC59108_MAX_BRIGHTNESS;
- + 	props.type = BACKLIGHT_RAW;
- + 	data->bl = backlight_device_register("tlc59108-bl", &c->dev, data,
- + 					     &bl_ops, &props);
- + 	if (IS_ERR(data->bl)) {
- + 		ret = PTR_ERR(data->bl);
- + 		goto err_reg;
- + 	}
- + 
- + 	data->bl->props.brightness = TLC59108_MAX_BRIGHTNESS;
- + 
- + 	backlight_update_status(data->bl);
- + 
- + 	return 0;
- + 
- + err_reg:
- + 	data->bl = NULL;
- + 	kfree(data);
- + 	return ret;
- + }
- + 
- + static int tlc59108_remove(struct i2c_client *c)
- + {
- + 	struct tlc59108_bl *data = i2c_get_clientdata(c);
- + 
- + 	backlight_device_unregister(data->bl);
- + 	data->bl = NULL;
- + 
- + 	kfree(data);
- + 
- + 	return 0;
- + }
- + 
- + /* I2C Device ID table */
- + static const struct i2c_device_id tlc59108_id[] = {
- + 	{ "tlc59108", 0 },
- + 	{ }
- + };
- + MODULE_DEVICE_TABLE(i2c, tlc59108_id);
- + 
- + /* I2C driver data */
- + static struct i2c_driver tlc59108_driver = {
- + 	.driver = {
- + 		.owner = THIS_MODULE,
- + 		.name = tlc59108_MODULE_NAME,
- + 	},
- + 	.probe = tlc59108_probe,
- + 	.remove = tlc59108_remove,
- + 	.id_table = tlc59108_id,
- + };
- + 
- + static int __init tlc59108_init(void)
- + {
- + 	return i2c_add_driver(&tlc59108_driver);
- + }
- + 
- + static void __exit tlc59108_exit(void)
- + {
- + 	i2c_del_driver(&tlc59108_driver);
- + }
- + 
- + module_init(tlc59108_init);
- + module_exit(tlc59108_exit);
- + 
- + MODULE_DESCRIPTION("LCD/Backlight control for TLC59108");
- + MODULE_AUTHOR("Senthil Natarajan <senthil.n@ti.com>");
- + MODULE_LICENSE("GPL v2");
- diff -crN linux-3.2.1_o/drivers/video/bf54x-lq043fb.c linux-3.2.1/drivers/video/bf54x-lq043fb.c
- *** linux-3.2.1_o/drivers/video/bf54x-lq043fb.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/video/bf54x-lq043fb.c	2014-05-15 13:25:15.118650298 +0900
- ***************
- *** 4,10 ****
-    * Author:       Michael Hennerich <hennerich@blackfin.uclinux.org>
-    *
-    * Created:
- !  * Description:  ADSP-BF54x Framebufer driver
-    *
-    *
-    * Modified:
- --- 4,10 ----
-    * Author:       Michael Hennerich <hennerich@blackfin.uclinux.org>
-    *
-    * Created:
- !  * Description:  ADSP-BF54x Framebuffer driver
-    *
-    *
-    * Modified:
- diff -crN linux-3.2.1_o/drivers/video/bfin-t350mcqb-fb.c linux-3.2.1/drivers/video/bfin-t350mcqb-fb.c
- *** linux-3.2.1_o/drivers/video/bfin-t350mcqb-fb.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/video/bfin-t350mcqb-fb.c	2014-05-15 13:25:15.118650298 +0900
- ***************
- *** 4,10 ****
-    * Author:       Michael Hennerich <hennerich@blackfin.uclinux.org>
-    *
-    * Created:
- !  * Description:  Blackfin LCD Framebufer driver
-    *
-    *
-    * Modified:
- --- 4,10 ----
-    * Author:       Michael Hennerich <hennerich@blackfin.uclinux.org>
-    *
-    * Created:
- !  * Description:  Blackfin LCD Framebuffer driver
-    *
-    *
-    * Modified:
- diff -crN linux-3.2.1_o/drivers/video/ckb/ckb_dvi.c linux-3.2.1/drivers/video/ckb/ckb_dvi.c
- *** linux-3.2.1_o/drivers/video/ckb/ckb_dvi.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/drivers/video/ckb/ckb_dvi.c	2014-05-15 13:25:15.118650298 +0900
- ***************
- *** 0 ****
- --- 1,464 ----
- + /*
- +  * CKB DVI driver that uses TFP410 I2C driver
- +  *
- +  * Copyright (C) 2013 Computex Co.Ltd.
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; version 2 of the License.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- +  *
- +  */
- +  
- + #include <linux/module.h>
- + #include <linux/kernel.h>
- + #include <linux/sched.h>
- + #include <linux/slab.h>
- + #include <linux/init.h>
- + #include <linux/io.h>
- + #include <linux/fs.h>
- + #include <linux/clk.h>
- + #include <linux/err.h>
- + #include <video/da8xx-fb.h>
- + #include <linux/platform_device.h>
- + #include <mach/devices.h>
- + #include <video/ckb_tfp410.h>
- + #include <video/ckb_dvi.h>
- + #include <video/ckb_video_modes.h>
- + 
- + #define MAX_EDID			128
- + 
- + /* device instance */
- + static struct class *ckb_dvi_dev_class;
- + struct ckb_dvi_device *ckb_dvi_dev=NULL;		/* single instance */
- + 
- + static int ckb_dvi_open(struct inode *inode, struct file *file)
- + {
- + 	if (ckb_dvi_dev == NULL){
- + 		printk("%s: no device found\n", CKB_DVI_NAME);
- + 		return -ENODEV;
- + 	}
- + 	file->private_data = ckb_dvi_dev;
- + 	return 0;
- + }
- + 
- + static int ckb_dvi_release(struct inode *inode, struct file *file)
- + {
- + 	file->private_data = NULL;
- + 	return 0;
- + }
- + 
- + static ssize_t ckb_dvi_info_show(struct device *dev, struct device_attribute *attr, char *buf)
- + {
- + 	return sprintf(buf, "%s\n", CKB_DVI_NAME);
- + }
- + 
- + static DEVICE_ATTR(ckb_dvi, 0666, ckb_dvi_info_show, NULL);
- + 
- + extern unsigned char *fb_do_probe_ddc_edid(struct i2c_adapter *adapter);
- + u8 *get_edid(struct i2c_adapter *adapter)
- + {
- + 	u8 *edid = NULL;
- + 	int i;
- + 	/* 3 retries */
- + 	for (i = 0; i < 3 && !edid; i++) {
- + 		edid = fb_do_probe_ddc_edid(adapter);
- + 	}
- + 	if(!edid)
- + 		pr_err("Could not read EDID from DVI device\n");
- + 	return edid;	
- + }
- + 
- + void get_monitor_specs(u8 *edid, struct fb_monspecs *specs)
- + {
- + 	fb_edid_to_monspecs(edid, specs);
- + 	if (edid[126] > 0)
- + 		fb_edid_add_monspecs(edid + 0x80, specs);
- + }
- + 
- + int get_dvi_info(struct fb_info *info)
- + {
- + 	struct i2c_adapter *adapter;
- + 	struct tfp410_priv *tfp;
- + 	u8 *edid;
- + 	if(!ckb_dvi_dev)
- + 		return 1;
- + 	
- + 	adapter = i2c_get_adapter(ckb_dvi_dev->plat_data->i2c_port);
- + 	if (!adapter) {
- + 		pr_err("failed to get adapter i2c%u\n", ckb_dvi_dev->plat_data->i2c_port);
- + 		return 1;
- + 	}
- + 	tfp = get_current_tfp410_device();
- + 	if(!tfp || tfp->tfp410_isconnected() == 0) 
- + 	{
- + 		return 1;
- + 	}
- + 	edid = get_edid(adapter);
- + 	if(!edid)
- + 	{
- + 		pr_err("Couldn't read EDID from device on adapter i2c%u\n", ckb_dvi_dev->plat_data->i2c_port);
- + 		return 2;
- + 	}
- + 	get_monitor_specs(edid, &info->monspecs);
- + 	
- + 	kfree(edid);
- + 	return 0;	
- + }
- + 
- + EXPORT_SYMBOL(get_dvi_info);
- + 
- + void display_resolution(struct fb_videomode *m)
- + {
- + #if 0
- + 	if(m->name)
- + 		printk("Name: %s ", m->name);
- + #endif
- + 	printk("%dx%d Clk: %luMHz (%d picosecs)\n",
- + 				m->xres, m->yres,
- + 				PICOS2KHZ(m->pixclock)/1000, m->pixclock);
- + }
- + 
- + int on_dvi_connector_plugged(struct ckb_dvi_device *dev_priv, struct i2c_adapter *adapter)
- + {
- + 	struct fb_monspecs *specs;
- + 	char duplicate[10];
- + 	struct fb_videomode *m, *temp;
- + #ifdef CONFIG_DISPLAY_UNSUPPORTED_DVI_RESOLUTIONS
- + 	int ignored_edid[MAX_EDID];
- + 	int ignored_count;
- + #endif
- + 	unsigned long clockMhz;
- + 	int max_tot_res;
- + 	u8 *edid;
- + 	int i, j;
- + 
- + 	printk("DVI device connected. Updating file %s\n", FBSET_DB_FILE);
- + 	printk("Resolutions upto %dx%d are supported (non-interlaced mode)\n", dev_priv->plat_data->max_xres, dev_priv->plat_data->max_yres);
- + 	/* include the supported modes in /etc/fb.modes */
- + 	edid = get_edid(adapter);
- + 	if(!edid)
- + 	{
- + 		printk("DVI: No EDID found\n");
- + 		return 1;
- + 	}
- + 	if(!create_video_mode_file())
- + 	{
- + 		return 1;
- + 	}
- + 	specs = kzalloc(sizeof(*specs), GFP_KERNEL);
- + 	if (specs == NULL) {
- + 		printk("DVI: Failed to allocate memory\n");
- + 		return 1;
- + 	}
- + 	max_tot_res = dev_priv->plat_data->max_yres * dev_priv->plat_data->max_xres;
- + 	get_monitor_specs(edid, specs);
- + #ifdef CONFIG_DISPLAY_DVI_RESOLUTIONS
- +     printk("*** Found the following supported resolutions ***\n");
- + #endif
- + #ifdef CONFIG_DISPLAY_UNSUPPORTED_DVI_RESOLUTIONS
- + 	ignored_count = 0;
- + #endif
- + 	for (i=0; i < specs->modedb_len; i++) 
- + 	{
- + 		m = &specs->modedb[i];
- + 		/* donot display unsupported resolution */
- + 		if (m->pixclock == 0)
- + 			goto _ignore;
- + 		/* skip resolutions that are not supported */
- + 		if (m->xres > dev_priv->plat_data->max_xres || m->yres > dev_priv->plat_data->max_yres)
- + 			goto _ignore;
- + 		if ((m->xres * m->yres) > max_tot_res)
- + 			goto _ignore;
- + 		if(m->vmode != FB_VMODE_NONINTERLACED)
- + 			goto _ignore;
- + 
- + 		/* check for duplicate modes */
- + 		duplicate[0] = 0;
- + 		clockMhz = PICOS2KHZ(m->pixclock)/1000; 
- + 		for(j=0; j<i; j++)
- + 		{
- + 			temp = &specs->modedb[j];
- + 			if(temp->xres == m->xres && temp->yres == m->yres
- + 					&& (PICOS2KHZ(temp->pixclock)/1000) == clockMhz)
- + 			{
- + 				/* check if it is an exact duplicate */
- + 				if(temp->pixclock ==  m->pixclock
- + 					&& temp->left_margin == m->left_margin
- + 					&& temp->right_margin == m->right_margin
- + 					&& temp->upper_margin == m->upper_margin
- + 					&& temp->lower_margin == m->lower_margin
- + 					&& temp->hsync_len == m->hsync_len
- + 					&& temp->vsync_len == m->vsync_len
- + 					&& temp->sync == m->sync)
- + 				{
- + 					/* exact duplicate */
- + 					goto _loop;
- + 				}
- + 				sprintf(duplicate, "-%d", i);
- + 				break;
- + 			}
- + 		}
- + 
- + #ifdef CONFIG_DISPLAY_DVI_RESOLUTIONS
- + 		display_resolution(m);
- + #endif
- + 		/* write to file */
- + 		append_video_mode("", m->xres, m->yres, duplicate, clockMhz,
- + 				m->pixclock, m->left_margin, m->right_margin, m->upper_margin, m->lower_margin,
- + 				m->hsync_len,  m->vsync_len, m->sync);
- + 
- + 		continue;
- + 
- + _ignore:
- + #ifdef CONFIG_DISPLAY_UNSUPPORTED_DVI_RESOLUTIONS
- + 		ignored_edid[ignored_count++] = i;
- + #endif
- + _loop:
- + 		continue;
- + 
- + 	}
- + 	dev_priv->connector_plugged = 1;
- + 	append_fb_mode();
- + 	close_video_mode_file();
- + #ifdef CONFIG_DISPLAY_DVI_RESOLUTIONS
- + 	printk("*** End ***\n");
- + #endif
- + #ifdef CONFIG_DISPLAY_UNSUPPORTED_DVI_RESOLUTIONS
- + 	if(ignored_count)
- + 	{
- +      	printk("***  Ignored the following resolutions ***\n");
- + 		for (i=0; i<ignored_count; i++) 
- + 		{
- + 			display_resolution(&specs->modedb[ignored_edid[i]]);
- + 		}
- + 		printk("*** End ***\n");
- + 	}
- + #endif
- + 	kfree(specs);
- + 	kfree(edid);
- + 	return 0;
- + }
- + 
- + void on_dvi_connector_pulled(struct ckb_dvi_device *dev_priv)
- + {
- + 	dev_priv->connector_plugged = 0;
- + 	printk("DVI device disconnected; Updating file %s\n", FBSET_DB_FILE);
- + 	create_video_mode_file();
- + 	append_fb_mode();
- + 	close_video_mode_file();
- + }
- + 
- + /* check the status to determine of the connector is plugged in/out */
- + static void check_dvi_connector_state(struct work_struct *work)
- + {
- + 	struct ckb_dvi_device *dev_priv = container_of(work, struct ckb_dvi_device,
- + 						    pluggedin_work);
- + 	volatile int connector_plugged;
- + 	struct i2c_adapter *adapter;
- + 	struct tfp410_priv *tfp;
- + 	adapter = i2c_get_adapter(dev_priv->plat_data->i2c_port);
- + 	if (!adapter) {
- + 		pr_err("failed to get adapter i2c%u\n", dev_priv->plat_data->i2c_port);
- + 		goto _out;
- + 	}
- + 	
- + 	tfp = get_current_tfp410_device();
- + 	if(tfp)
- + 		connector_plugged = tfp->tfp410_isconnected()?1:0;
- + 	else
- + 	{
- + 		printk("tfp410 device not found");
- + 		connector_plugged = 0;
- + 	}
- + 	
- + 	if(connector_plugged != dev_priv->connector_plugged)
- + 	{
- + 		if(connector_plugged)
- + 		{
- + 			if(on_dvi_connector_plugged(dev_priv, adapter))
- + 			{
- + 				goto _out;
- + 			}
- + 		}
- + 		else
- + 		{
- + 			on_dvi_connector_pulled(dev_priv);
- + 		}
- + 	}
- + 	
- + _out:
- + 	if (mod_timer(&ckb_dvi_dev->pluggedin_timer, jiffies + msecs_to_jiffies(ckb_dvi_dev->plat_data->connect_poll_interval)))
- + 	{ 
- + 		printk("%s: Error in timer\n", CKB_DVI_NAME);
- + 	}
- + }
- + 
- + static void ckb_connector_plugged_timer(unsigned long arg)
- + {
- + 	struct ckb_dvi_device *dev_priv = (struct ckb_dvi_device *)arg;
- + 	queue_work(dev_priv->wq, &dev_priv->pluggedin_work);
- + }
- + 
- + static int __devinit ckb_dvi_probe(struct platform_device *pdev)
- + {
- + 	int ret = 0;
- + 	if(ckb_dvi_dev)
- + 	{
- + 		dev_err(&pdev->dev, "%s driver can only be loaded once\n", CKB_DVI_NAME);
- + 		return -ENODEV;
- + 	}
- + 	ckb_dvi_dev = kzalloc(sizeof(struct ckb_dvi_device), GFP_KERNEL);
- + 	if (ckb_dvi_dev == NULL) {
- + 		dev_err(&pdev->dev, "failed to allocate memory\n");
- + 		return -ENOMEM;
- + 	}
- + 	if(!pdev->dev.platform_data) {
- + 		dev_err(&pdev->dev, "Platform data not provided\n");
- + 		return -ENODEV;
- + 	}
- + 
- + 	ckb_dvi_dev->pdev = pdev;
- + 	ckb_dvi_dev->plat_data = pdev->dev.platform_data;
- + 
- + 	/* register the device with the driver core */
- + 	ckb_dvi_dev->dev = device_create(ckb_dvi_dev_class, NULL,
- + 				     MKDEV(CKB_DVI_MAJOR,0), NULL,
- + 				     CKB_DVI_NAME);
- + 	if (IS_ERR(ckb_dvi_dev->dev)) {
- + 		ret = PTR_ERR(ckb_dvi_dev->dev);
- + 		goto err_free;
- + 	}
- + 
- + 	if (device_create_file(ckb_dvi_dev->dev, &dev_attr_ckb_dvi))
- + 	{
- + 		ret = -ENOMEM;
- + 		goto error_destroy;
- + 	}
- + 	platform_set_drvdata(pdev, ckb_dvi_dev);
- + 
- + 	/* start a timer to check for the pluggedin event */
- + 	ckb_dvi_dev->wq = alloc_workqueue("CKB_DVI",
- + 				       WQ_UNBOUND | WQ_NON_REENTRANT,
- + 				       1);
- + 	if (ckb_dvi_dev->wq == NULL) {
- + 		dev_err(&pdev->dev, "Failed to create workqueue\n");
- + 		ret = -ENOMEM;
- + 		goto error_destroy;
- + 	}
- + 	
- + 	ckb_dvi_dev->connector_plugged = 0;
- + 
- + 	INIT_WORK(&ckb_dvi_dev->pluggedin_work, check_dvi_connector_state);
- + 	setup_timer(&ckb_dvi_dev->pluggedin_timer, ckb_connector_plugged_timer,
- + 		    (unsigned long)ckb_dvi_dev);
- + 	ret = mod_timer(&ckb_dvi_dev->pluggedin_timer, jiffies + msecs_to_jiffies(ckb_dvi_dev->plat_data->connect_poll_interval));
- + 	if (ret)
- + 	{ 
- + 		dev_err(&pdev->dev, "Error in timer\n");
- + 		goto error_timer;
- + 	}
- + 
- + 	printk("CKB DVI driver with max resolution %dx%d\n",
- + 				ckb_dvi_dev->plat_data->max_xres, ckb_dvi_dev->plat_data->max_yres);
- + 	
- + 	return 0;
- + error_timer:
- + 	destroy_workqueue(ckb_dvi_dev->wq);
- + 	del_timer(&ckb_dvi_dev->pluggedin_timer);
- + error_destroy:
- + 	device_destroy(ckb_dvi_dev_class, MKDEV(CKB_DVI_MAJOR,0));
- + 	
- + err_free:
- + 	kfree(ckb_dvi_dev);
- + 	ckb_dvi_dev = NULL;
- + 	dev_err(&pdev->dev, "device not added\n");
- + 	return ret;
- + }
- + 
- + static int __devexit ckb_dvi_remove(struct platform_device *pdev)
- + {
- + 	if (ckb_dvi_dev == NULL)
- + 		return -ENODEV;
- + 
- + 	flush_workqueue(ckb_dvi_dev->wq);
- + 	destroy_workqueue(ckb_dvi_dev->wq);
- + 	del_timer(&ckb_dvi_dev->pluggedin_timer);
- + 
- + 	device_destroy(ckb_dvi_dev_class, MKDEV(CKB_DVI_MAJOR,0));
- + 	kfree(ckb_dvi_dev);
- + 	ckb_dvi_dev = NULL;
- + 	return 0;
- + }
- + 
- + static const struct file_operations ckb_dvi_fops = {
- + 	.owner		= THIS_MODULE,
- + 	.llseek		= no_llseek,
- + 	.read		= NULL,
- + 	.write		= NULL,
- + 	.open		= ckb_dvi_open,
- + 	.release	= ckb_dvi_release,
- + };
- + 
- + static struct platform_driver ckb_dvi_driver = {
- + 	.probe		= ckb_dvi_probe,
- + 	.remove		= __devexit_p(ckb_dvi_remove),
- + 	.driver		= {
- + 		.owner	= THIS_MODULE,
- + 		.name	= CKB_DVI_NAME,
- + 	},
- + };
- + 
- + static int __init ckb_dvi_init(void)
- + {
- + 	int res;
- + 	res = register_chrdev(CKB_DVI_MAJOR, CKB_DVI_NAME, &ckb_dvi_fops);
- + 	if (res)
- + 	{
- + 		printk(KERN_ERR "%s: Can't create device file\n", __FILE__);
- + 		goto out;
- + 	}
- + 	ckb_dvi_dev_class = class_create(THIS_MODULE, CKB_DVI_NAME);
- + 	if (IS_ERR(ckb_dvi_dev_class)) {
- + 		printk(KERN_ERR "%s: Can't create class\n", __FILE__);
- + 		res = PTR_ERR(ckb_dvi_dev_class);
- + 		goto out_unreg_chrdev;
- + 	}
- + 	res = platform_driver_register(&ckb_dvi_driver);
- + 	if(res)
- + 	{
- + 		printk(KERN_ERR "%s: Can't register driver\n", __FILE__);
- + 		goto out_unreg_class;
- + 	}
- + 	return 0;
- + 
- + out_unreg_class:
- + 	class_destroy(ckb_dvi_dev_class);
- + out_unreg_chrdev:
- + 	unregister_chrdev(CKB_DVI_MAJOR, CKB_DVI_NAME);
- + out:
- + 	printk(KERN_ERR "%s: Driver Initialization failed\n", __FILE__);
- + 	return res;	
- + }
- + 
- + static void __exit ckb_dvi_exit(void)
- + {
- + 	platform_driver_unregister(&ckb_dvi_driver);
- + 	class_destroy(ckb_dvi_dev_class);
- + 	unregister_chrdev(CKB_DVI_MAJOR, CKB_DVI_NAME);
- + }
- + 
- + arch_initcall(ckb_dvi_init);
- + module_exit(ckb_dvi_exit);
- + 
- + MODULE_DESCRIPTION("CKB DVI access driver");
- + MODULE_AUTHOR("Aiyappa M.S.");
- + MODULE_LICENSE("GPL");
- diff -crN linux-3.2.1_o/drivers/video/ckb/ckb_tfp410.c linux-3.2.1/drivers/video/ckb/ckb_tfp410.c
- *** linux-3.2.1_o/drivers/video/ckb/ckb_tfp410.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/drivers/video/ckb/ckb_tfp410.c	2014-05-15 13:25:15.118650298 +0900
- ***************
- *** 0 ****
- --- 1,361 ----
- + /*
- +  * TFP410 I2C driver
- +  *
- +  * Copyright (C) 2013 Computex Co.Ltd.
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; version 2 of the License.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- +  *
- +  */
- +   
- + #include <linux/module.h>
- + #include <linux/slab.h>
- + #include <linux/i2c.h>
- + #include <video/ckb_tfp410.h>
- + 
- + /* register definitions according to the TFP410 data sheet */
- + #define TFP410_VID		0x014C
- + #define TFP410_DID		0x0410
- + 
- + #define TFP410_VID_LO		0x00
- + #define TFP410_VID_HI		0x01
- + #define TFP410_DID_LO		0x02
- + #define TFP410_DID_HI		0x03
- + #define TFP410_REV		0x04
- + 
- + #define TFP410_CTL_1		0x08
- + #define TFP410_CTL_1_TDIS	(1<<6)
- + #define TFP410_CTL_1_VEN	(1<<5)
- + #define TFP410_CTL_1_HEN	(1<<4)
- + #define TFP410_CTL_1_DSEL	(1<<3)
- + #define TFP410_CTL_1_BSEL	(1<<2)
- + #define TFP410_CTL_1_EDGE	(1<<1)
- + #define TFP410_CTL_1_PD		(1<<0)
- + 
- + #define TFP410_CTL_2		0x09
- + #define TFP410_CTL_2_VLOW	(1<<7)
- + #define TFP410_CTL_2_MSEL_MASK	(0x7<<4)
- + #define TFP410_CTL_2_MSEL	(1<<4)
- + #define TFP410_CTL_2_TSEL	(1<<3)
- + #define TFP410_CTL_2_RSEN	(1<<2)
- + #define TFP410_CTL_2_HTPLG	(1<<1)
- + #define TFP410_CTL_2_MDI	(1<<0)
- + 
- + #define TFP410_CTL_3		0x0A
- + #define TFP410_CTL_3_DK_MASK	(0x7<<5)
- + #define TFP410_CTL_3_DK		(1<<5)
- + #define TFP410_CTL_3_DKEN	(1<<4)
- + #define TFP410_CTL_3_CTL_MASK	(0x7<<1)
- + #define TFP410_CTL_3_CTL	(1<<1)
- + 
- + #define TFP410_USERCFG		0x0B
- + 
- + #define TFP410_DE_DLY		0x32
- + 
- + #define TFP410_DE_CTL		0x33
- + #define TFP410_DE_CTL_DEGEN	(1<<6)
- + #define TFP410_DE_CTL_VSPOL	(1<<5)
- + #define TFP410_DE_CTL_HSPOL	(1<<4)
- + #define TFP410_DE_CTL_DEDLY8	(1<<0)
- + 
- + #define TFP410_DE_TOP		0x34
- + 
- + #define TFP410_DE_CNT_LO	0x36
- + #define TFP410_DE_CNT_HI	0x37
- + 
- + #define TFP410_DE_LIN_LO	0x38
- + #define TFP410_DE_LIN_HI	0x39
- + 
- + #define TFP410_H_RES_LO		0x3A
- + #define TFP410_H_RES_HI		0x3B
- + 
- + #define TFP410_V_RES_LO		0x3C
- + #define TFP410_V_RES_HI		0x3D
- + 
- + struct tfp410_priv *cur_ckb_tfp410_device=NULL;
- + 
- + struct tfp410_priv *get_current_tfp410_device()
- + {
- + 	return cur_ckb_tfp410_device;
- + }
- + 	 	
- + struct i2c_adapter *get_i2c_adapter(void)
- + {
- + 	if(cur_ckb_tfp410_device)
- + 		return cur_ckb_tfp410_device->client->adapter;
- + 	return 0;
- + }
- + 	 	 
- + bool tfp410_readb(struct i2c_client *client, int addr, uint8_t *ch)
- + {
- + 	struct i2c_adapter *adapter = client->adapter;
- + 	struct tfp410_priv *tfp = i2c_get_clientdata(client);
- + 	u8 out_buf[2];
- + 	u8 in_buf[2];
- + 
- + 	struct i2c_msg msgs[] = {
- + 		{
- + 			.addr = client->addr,
- + 			.flags = 0,
- + 			.len = 1,
- + 			.buf = out_buf,
- + 		},
- + 		{
- + 			.addr = client->addr,
- + 			.flags = I2C_M_RD,
- + 			.len = 1,
- + 			.buf = in_buf,
- + 		}
- + 	};
- + 
- + 	out_buf[0] = addr;
- + 	out_buf[1] = 0;
- + 
- + 	if (i2c_transfer(adapter, msgs, 2) == 2) {
- + 		*ch = in_buf[0];
- + 		return true;
- + 	};
- + 
- + 	dev_err(tfp->dev, "Unable to read register 0x%02x to %s:%d.\n",
- + 			  addr, adapter->name, client->addr);
- + 	return false;
- + }
- + 
- + static bool tfp410_writeb(struct i2c_client *client, int addr, uint8_t ch)
- + {
- + 	struct tfp410_priv *tfp = i2c_get_clientdata(client);
- + 	struct i2c_adapter *adapter = client->adapter;
- + 	uint8_t out_buf[2];
- + 	struct i2c_msg msg = {
- + 		.addr = client->addr,
- + 		.flags = 0,
- + 		.len = 2,
- + 		.buf = out_buf,
- + 	};
- + 
- + 	out_buf[0] = addr;
- + 	out_buf[1] = ch;
- + 
- + 	if (i2c_transfer(adapter, &msg, 1) == 1)
- + 		return true;
- + 
- + 	dev_err(tfp->dev, "Unable to write register 0x%02x to %s:%d.\n",
- + 			  addr, adapter->name, client->addr);
- + 	
- + 	return false;
- + }
- + 
- + static bool tfp410_detect(struct i2c_client *client)
- + {
- + 	uint8_t ctl2;
- + 	if (tfp410_readb(client, TFP410_CTL_2, &ctl2)) {
- + 		if (ctl2 & TFP410_CTL_2_RSEN)
- + 		{
- + 			return 1;	/* connected */
- + 		}
- + 	}
- + 	return 0;	/* disconnected */
- + }
- + 
- + static bool tfp410_read(int addr, uint8_t *ch)
- + {
- + 	if(cur_ckb_tfp410_device)
- + 		return tfp410_readb(cur_ckb_tfp410_device->client, addr, ch);
- + 	return 0;
- + }
- + 
- + static bool tfp410_write(int addr, uint8_t ch)
- + {
- + 	if(cur_ckb_tfp410_device)
- + 		return tfp410_writeb(cur_ckb_tfp410_device->client, addr, ch);
- + 	return 0;
- + }
- + 
- + static bool tfp410_isconnected(void)
- + {
- + 	if(cur_ckb_tfp410_device)
- + 		return tfp410_detect(cur_ckb_tfp410_device->client);
- + 	return 0;
- + }
- + 	
- + static int tfp410_getid(struct i2c_client *client, int addr)
- + {
- + 	uint8_t ch1, ch2;
- + 
- + 	if (tfp410_readb(client, addr+0, &ch1) &&
- + 	    tfp410_readb(client, addr+1, &ch2))
- + 		return ((ch2 << 8) & 0xFF00) | (ch1 & 0x00FF);
- + 
- + 	return -1;
- + }
- + 
- + /* set the tfp410 power state */
- + static void tfp410_setpower(struct i2c_client *client, int mode)
- + {
- + 	uint8_t ctl1;
- + 
- + 	if (!tfp410_readb(client, TFP410_CTL_1, &ctl1))
- + 		return;
- + 
- + 	if (mode == 1)		/* power on */
- + 		ctl1 |= TFP410_CTL_1_PD;
- + 	else
- + 		ctl1 &= ~TFP410_CTL_1_PD;
- + 
- + 	tfp410_writeb(client, TFP410_CTL_1, ctl1);
- + 	if (mode == 1)
- + 	{
- + 		if (!tfp410_readb(client, TFP410_CTL_2, &ctl1))
- + 			return;
- + 		tfp410_writeb(client, TFP410_CTL_2, (ctl1 & ~TFP410_CTL_2_MSEL_MASK) | (1 << 4) );
- + 	}
- + }
- + 
- + #if 0
- + static void tfp410_dump_regs(struct i2c_client *client)
- + {
- + 	uint8_t val, val2;
- + 
- + 	tfp410_readb(client, TFP410_REV, &val);
- + 	printk("TFP410_REV: 0x%02X\n", val);
- + 	tfp410_readb(client, TFP410_CTL_1, &val);
- + 	printk("TFP410_CTL1: 0x%02X\n", val);
- + 	tfp410_readb(client, TFP410_CTL_2, &val);
- + 	printk("TFP410_CTL2: 0x%02X\n", val);
- + 	tfp410_readb(client, TFP410_CTL_3, &val);
- + 	printk("TFP410_CTL3: 0x%02X\n", val);
- + 	tfp410_readb(client, TFP410_USERCFG, &val);
- + 	printk("TFP410_USERCFG: 0x%02X\n", val);
- + 	tfp410_readb(client, TFP410_DE_DLY, &val);
- + 	printk("TFP410_DE_DLY: 0x%02X\n", val);
- + 	tfp410_readb(client, TFP410_DE_CTL, &val);
- + 	printk("TFP410_DE_CTL: 0x%02X\n", val);
- + 	tfp410_readb(client, TFP410_DE_TOP, &val);
- + 	printk("TFP410_DE_TOP: 0x%02X\n", val);
- + 	tfp410_readb(client, TFP410_DE_CNT_LO, &val);
- + 	tfp410_readb(client, TFP410_DE_CNT_HI, &val2);
- + 	printk("TFP410_DE_CNT: 0x%02X%02X\n", val2, val);
- + 	tfp410_readb(client, TFP410_DE_LIN_LO, &val);
- + 	tfp410_readb(client, TFP410_DE_LIN_HI, &val2);
- + 	printk("TFP410_DE_LIN: 0x%02X%02X\n", val2, val);
- + 	tfp410_readb(client, TFP410_H_RES_LO, &val);
- + 	tfp410_readb(client, TFP410_H_RES_HI, &val2);
- + 	printk("TFP410_H_RES: 0x%02X%02X\n", val2, val);
- + 	tfp410_readb(client, TFP410_V_RES_LO, &val);
- + 	tfp410_readb(client, TFP410_V_RES_HI, &val2);
- + 	printk("TFP410_V_RES: 0x%02X%02X\n", val2, val);
- + }
- + #endif
- + 
- + static int __devinit tfp410_probe(struct i2c_client *client,
- + 				const struct i2c_device_id *ids)
- + {
- + 	/* this will detect the tfp410 chip on the specified i2c bus */
- + 	struct tfp410_priv *tfp;
- + 	struct tfp410_platform_data *pdata = client->dev.platform_data;
- + 	uint8_t ctl3;
- + 	int id;
- + 	tfp = devm_kzalloc(&client->dev, sizeof(*tfp), GFP_KERNEL);
- + 	if (!tfp)
- + 		return -ENOMEM;
- + 		
- + 	tfp->dev = &client->dev;
- + 	tfp410_setpower(client, 1);
- + 
- + 	if ((id = tfp410_getid(client, TFP410_VID_LO)) != TFP410_VID) {
- + 		dev_err(tfp->dev, "TFP410 not detected got VID %X: from %s "
- + 				"Slave %d.\n",
- + 			  id, client->adapter->name, client->addr);
- + 		goto out;
- + 	}
- + 
- + 	if ((id = tfp410_getid(client, TFP410_DID_LO)) != TFP410_DID) {
- + 		dev_err(tfp->dev, "TFP410 not detected got DID %X: from %s "
- + 				"Slave %d.\n",
- + 			  id, client->adapter->name, client->addr);
- + 		goto out;
- + 	}
- + 	
- + 	/* enable skew */
- + 	tfp410_readb(client, TFP410_CTL_3, &ctl3); 
- + 	tfp410_writeb(client, TFP410_CTL_3, 
- + 		ctl3 | TFP410_CTL_3_DKEN | (0x7<<5));
- + 	
- + 	tfp410_readb(client, TFP410_CTL_1, &ctl3);
- + 	tfp410_writeb(client, TFP410_CTL_1, 
- + 		(ctl3 & ~(TFP410_CTL_1_DSEL)) | TFP410_CTL_1_EDGE | TFP410_CTL_1_BSEL);
- + 	
- + //	tfp410_dump_regs(client);
- + 	
- + 	cur_ckb_tfp410_device = tfp;
- + 	cur_ckb_tfp410_device->tfp410_read = tfp410_read;
- + 	cur_ckb_tfp410_device->tfp410_write = tfp410_write;
- + 	cur_ckb_tfp410_device->tfp410_isconnected = tfp410_isconnected;
- + 	cur_ckb_tfp410_device->get_i2c_adapter = get_i2c_adapter;
- + 	
- + 	dev_info(tfp->dev, "TFP410 VID %#x DID %#x\n",
- + 			TFP410_VID, TFP410_DID);
- + 
- + 	i2c_set_clientdata(client, tfp);
- + 	tfp->client = client;
- + 	tfp->pdata = pdata;
- + 	
- + 	return 0;
- + out:
- + 	kfree(tfp);
- + 	return -1;
- + }
- + 
- + static int __devexit tfp410_remove(struct i2c_client *client)
- + {
- + 	struct tfp410_priv *tfp = i2c_get_clientdata(client);
- + 	cur_ckb_tfp410_device = NULL;
- + 	kfree(tfp);
- + 
- + 	return 0;
- + }
- + 
- + 
- + 
- + static const struct i2c_device_id tfp410_id_table[] = {
- + 	{"tfp410", 0xF0},
- + 	{/* end of list */}
- + };
- + MODULE_DEVICE_TABLE(i2c, tfp410_id_table);
- + 
- + static struct i2c_driver tfp410_driver = {
- + 	.driver		= {
- + 		.name	= "tfp410",
- + 	},
- + 	.id_table	= tfp410_id_table,
- + 	.probe		= tfp410_probe,
- + 	.remove		= __devexit_p(tfp410_remove),
- + };
- + 
- + 
- + static int __init tfp410_init(void)
- + {
- + 	return i2c_add_driver(&tfp410_driver);
- + }
- + subsys_initcall(tfp410_init);
- + 
- + static void __exit tfp410_exit(void)
- + {
- + 	i2c_del_driver(&tfp410_driver);
- + }
- + module_exit(tfp410_exit);
- + 
- + MODULE_AUTHOR("Aiyappa M.S.");
- + MODULE_DESCRIPTION("TFP410 chip i2c driver");
- + MODULE_LICENSE("GPL");
- + 
- diff -crN linux-3.2.1_o/drivers/video/ckb/ckb_video_modes.c linux-3.2.1/drivers/video/ckb/ckb_video_modes.c
- *** linux-3.2.1_o/drivers/video/ckb/ckb_video_modes.c	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/drivers/video/ckb/ckb_video_modes.c	2014-06-06 15:09:10.057218000 +0900
- ***************
- *** 0 ****
- --- 1,197 ----
- + /*
- +  * CKB DVI driver that uses TFP410 I2C driver
- +  *
- +  * Copyright (C) 2013 Computex Co.Ltd.
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; version 2 of the License.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- +  *
- +  */
- +  
- + #include <linux/module.h>
- + #include <linux/kernel.h>
- + #include <linux/sched.h>
- + #include <linux/slab.h>
- + #include <linux/init.h>
- + #include <linux/io.h>
- + #include <linux/fs.h>
- + #include <linux/clk.h>
- + #include <linux/err.h>
- + #include <linux/i2c.h>
- + #include <linux/delay.h>
- + #include <linux/fb.h>
- + #include <linux/platform_device.h>
- + #include <mach/devices.h>
- + #include <video/da8xx-fb.h>
- + #include <video/ckb_video_modes.h>
- + 
- + static struct file *vfile_fd = NULL;
- + static loff_t vfile_pos = 0;
- + static int g_mode_index = 0;
- + static struct da8xx_panel *g_fb_panels=NULL;
- + int g_fb_panels_size;
- + static int g_fb_bpp;
- + static char g_buffer[512];
- + static char g_synbuffer[512];
- + 
- + char *getSync(__u32 sync)
- + {
- + 	int len;
- + 	if(sync == 0)
- + 		return "None";
- + 
- + 	g_synbuffer[0] = 0;
- + 	if(sync & FB_SYNC_HOR_HIGH_ACT)
- + 		strcat(g_synbuffer, "FB_SYNC_HOR_HIGH_ACT | ");
- + 	if(sync & FB_SYNC_VERT_HIGH_ACT)
- + 		strcat(g_synbuffer, "FB_SYNC_VERT_HIGH_ACT | ");
- + 	if(sync & FB_SYNC_EXT)
- + 		strcat(g_synbuffer, "FB_SYNC_EXT | ");
- + 	if(sync & FB_SYNC_COMP_HIGH_ACT)
- + 		strcat(g_synbuffer, "FB_SYNC_COMP_HIGH_ACT | ");
- + 	if(sync & FB_SYNC_BROADCAST)
- + 		strcat(g_synbuffer, "FB_SYNC_BROADCAST | ");
- + 	if(sync & FB_SYNC_ON_GREEN)
- + 		strcat(g_synbuffer, "FB_SYNC_ON_GREEN | ");
- + 	
- + 	len = strlen(g_synbuffer);
- + 	if(!len)
- + 	{
- + 		return "Unknown";
- + 	}
- + 	g_synbuffer[len-3] = 0;
- + 	return g_synbuffer;
- + }
- + 
- + char create_video_mode_file()
- + {
- + 	static struct file *dir_fd;
- + 	int retry = 10;
- + 	if(vfile_fd != NULL)
- + 		filp_close(vfile_fd, NULL);
- + 
- + 	else
- + 	{
- + 		/* make sure /etc exists, this needed as this code is sometimes called before the FS is mounted */
- + 		dir_fd = filp_open(FBSET_DB_DIR, O_RDONLY, 0);
- + 		while(IS_ERR(dir_fd) && retry--)
- + 		{
- + 			mdelay(500);
- + 			dir_fd = filp_open(FBSET_DB_DIR, O_RDONLY, 0);
- + 		}
- + 		if(retry<0)
- + 			goto _failed;
- + 		/* directory exits */
- + 		filp_close(dir_fd, NULL);
- + 	}
- + 
- + 	vfile_fd = filp_open(FBSET_DB_FILE, O_CREAT | O_RDWR | O_TRUNC, 0);
- + 	if (IS_ERR(vfile_fd))
- + 	{
- + _failed:
- + 		printk("File %s could not be created\n", FBSET_DB_FILE);
- + 		vfile_fd = NULL;
- + 		return 0;
- +     }
- + 	g_mode_index = 0;
- + 	vfile_pos = 0;
- + 	return 1;
- + }
- + 
- + void close_video_mode_file()
- + {
- + 	if(vfile_fd != NULL)
- + 	{
- + 		filp_close(vfile_fd, NULL);
- + 		vfile_fd = NULL;
- +     }
- + }
- + 
- + void append_video_mode(const char *name, __u32 xres, __u32 yres, char *duplicate, __u32 clockMhz,
- + 			__u32 pixclock, __u32 left_margin, __u32 right_margin, __u32 upper_margin, __u32 lower_margin,
- + 			__u32 hsync_len,  __u32 vsync_len, 	__u32 sync)
- + {
- + 	sprintf(g_buffer, "mode "
- + #ifdef CONFIG_CKB_EASY_SWITCH_MODE
- + 		"\"%d\"\n"
- + #else
- + 		"\"%dx%d@%d%s%s\"\n"
- + #endif
- + 		"    #%dx%d%s%s\n"
- + 		"    #Clock=%dMHz (%d picosecs)\n" 
- + 		"    geometry %d %d %d %d %d\n"
- + 		"    timings %d %d %d %d %d %d %d\n"
- + 		"    #sync: %s\n"
- + 		"endmode\n\n",
- + #ifdef CONFIG_CKB_EASY_SWITCH_MODE
- + 			g_mode_index,
- + #else
- + 			xres, yres, clockMhz, duplicate, name,
- + #endif
- + 			xres, yres, duplicate, name,
- + 			clockMhz, pixclock,
- + 			xres, yres, xres, yres, g_fb_bpp,
- + 			pixclock, left_margin, right_margin, upper_margin, lower_margin, hsync_len,  vsync_len,
- + 			getSync(sync)
- + 		);
- + 
- + 	vfs_write(vfile_fd, g_buffer, strlen(g_buffer), &vfile_pos);
- + 	g_mode_index++;
- + 
- + }
- + 
- + void append_fb_mode()
- + {
- + 	struct da8xx_panel *lcdc_info;
- + 	int i;
- + 	
- + 	if(g_fb_panels)
- + 	{
- + 		if(vfile_fd == NULL)
- + 		{
- + 			vfile_fd = filp_open(FBSET_DB_FILE, O_CREAT | O_RDWR | O_APPEND, 0);
- + 			if (IS_ERR(vfile_fd))
- + 			{
- + 				printk("File %s could not be opened for writing\n", FBSET_DB_FILE);
- + 				vfile_fd = NULL;
- + 				return;
- + 			}
- + 			vfile_pos = 0;
- + 		}
- + 
- + 		for (i=0,lcdc_info=g_fb_panels; i<g_fb_panels_size; i++,lcdc_info++)
- + 		{
- + 
- + 			append_video_mode(lcdc_info->name, lcdc_info->width, lcdc_info->height,
- + 				" ", PICOS2KHZ(lcdc_info->pxl_clk)/1000, lcdc_info->pxl_clk,
- + 				lcdc_info->hbp, lcdc_info->hfp,
- + 					lcdc_info->vbp, lcdc_info->vfp, 
- + 					lcdc_info->hsw,  lcdc_info->vsw,
- + 					lcdc_info->sync);
- + 		}
- + 		
- + 	}
- + }
- + 
- + void set_fb_panel_info(struct da8xx_panel *fb_panels, int size, int bpp)
- + {
- + 	g_fb_panels = fb_panels;
- + 	g_fb_panels_size = size;
- + 	g_fb_bpp = bpp;
- + }
- + 
- + EXPORT_SYMBOL(create_video_mode_file);
- + EXPORT_SYMBOL(close_video_mode_file);
- + EXPORT_SYMBOL(append_video_mode);
- + EXPORT_SYMBOL(append_fb_mode);
- + EXPORT_SYMBOL(set_fb_panel_info);
- diff -crN linux-3.2.1_o/drivers/video/ckb/Makefile linux-3.2.1/drivers/video/ckb/Makefile
- *** linux-3.2.1_o/drivers/video/ckb/Makefile	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/drivers/video/ckb/Makefile	2014-05-15 13:25:15.122662428 +0900
- ***************
- *** 0 ****
- --- 1,4 ----
- + # Makefile for the Linux CKB LCD/DVI support.
- + 
- + obj-$(CONFIG_CKB_LCD_SUPPORT)     += ckb_video_modes.o
- + obj-$(CONFIG_CKB_DVI_SUPPORT)     += ckb_video_modes.o ckb_tfp410.o ckb_dvi.o
- \ No newline at end of file
- diff -crN linux-3.2.1_o/drivers/video/da8xx-fb.c linux-3.2.1/drivers/video/da8xx-fb.c
- *** linux-3.2.1_o/drivers/video/da8xx-fb.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/video/da8xx-fb.c	2014-05-15 13:25:15.122662428 +0900
- ***************
- *** 30,37 ****
- --- 30,51 ----
-   #include <linux/clk.h>
-   #include <linux/cpufreq.h>
-   #include <linux/console.h>
- + #include <linux/spinlock.h>
-   #include <linux/slab.h>
- + #include <linux/delay.h>
- + #include <linux/pm_runtime.h>
- + #include <linux/lcm.h>
-   #include <video/da8xx-fb.h>
- + #include <asm/mach-types.h>
- + #include <asm/div64.h>
- + 
- + #if defined(CONFIG_CKB_LCD_SUPPORT) || defined(CONFIG_CKB_DVI_SUPPORT)
- + #include <mach/ckb_3352_mem.h>
- + #include <video/ckb_video_modes.h>
- + #endif
- + #ifdef CONFIG_CKB_DVI_SUPPORT
- + #include <video/ckb_dvi.h>
- + #endif
-   
-   #define DRIVER_NAME "da8xx_lcdc"
-   
- ***************
- *** 82,87 ****
- --- 96,103 ----
-   #define LCD_V2_LIDD_CLK_EN		BIT(1)
-   #define LCD_V2_CORE_CLK_EN		BIT(0)
-   #define LCD_V2_LPP_B10			26
- + #define LCD_V2_TFT_24BPP_MODE		BIT(25)
- + #define LCD_V2_TFT_24BPP_UNPACK		BIT(26)
-   
-   /* LCD Raster Timing 2 Register */
-   #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x)	((x) << 16)
- ***************
- *** 126,131 ****
- --- 142,149 ----
-   #define RIGHT_MARGIN	64
-   #define UPPER_MARGIN	32
-   #define LOWER_MARGIN	32
- + #define WAIT_FOR_FRAME_DONE	true
- + #define NO_WAIT_FOR_FRAME_DONE	false
-   
-   static resource_size_t da8xx_fb_reg_base;
-   static struct resource *lcdc_regs;
- ***************
- *** 143,148 ****
- --- 161,167 ----
-   }
-   
-   struct da8xx_fb_par {
- + 	struct device *dev;
-   	resource_size_t p_palette_base;
-   	unsigned char *v_palette_base;
-   	dma_addr_t		vram_phys;
- ***************
- *** 159,172 ****
-   	wait_queue_head_t	vsync_wait;
-   	int			vsync_flag;
-   	int			vsync_timeout;
-   #ifdef CONFIG_CPU_FREQ
-   	struct notifier_block	freq_transition;
-   #endif
-   	void (*panel_power_ctrl)(int);
-   };
-   
-   /* Variable Screen Information */
- ! static struct fb_var_screeninfo da8xx_fb_var __devinitdata = {
-   	.xoffset = 0,
-   	.yoffset = 0,
-   	.transp = {0, 0, 0},
- --- 178,203 ----
-   	wait_queue_head_t	vsync_wait;
-   	int			vsync_flag;
-   	int			vsync_timeout;
- + 	spinlock_t		lock_for_chan_update;
- + 
- + 	/*
- + 	 * LCDC has 2 ping pong DMA channels, channel 0
- + 	 * and channel 1.
- + 	 */
- + 	unsigned int		which_dma_channel_done;
- + 	unsigned char dma_alloc;
-   #ifdef CONFIG_CPU_FREQ
-   	struct notifier_block	freq_transition;
- + 	unsigned int		lcd_fck_rate;
- + #endif
- + #if defined(CONFIG_CKB_LCD_SUPPORT) || defined(CONFIG_CKB_DVI_SUPPORT)
- + 	struct lcd_ctrl_config *lcd_cfg;
-   #endif
-   	void (*panel_power_ctrl)(int);
-   };
-   
-   /* Variable Screen Information */
- ! static struct fb_var_screeninfo da8xx_fb_var = {
-   	.xoffset = 0,
-   	.yoffset = 0,
-   	.transp = {0, 0, 0},
- ***************
- *** 174,180 ****
-   	.activate = 0,
-   	.height = -1,
-   	.width = -1,
- - 	.pixclock = 46666,	/* 46us - AUO display */
-   	.accel_flags = 0,
-   	.left_margin = LEFT_MARGIN,
-   	.right_margin = RIGHT_MARGIN,
- --- 205,210 ----
- ***************
- *** 195,217 ****
-   	.accel = FB_ACCEL_NONE
-   };
-   
- ! struct da8xx_panel {
- ! 	const char	name[25];	/* Full name <vendor>_<model> */
- ! 	unsigned short	width;
- ! 	unsigned short	height;
- ! 	int		hfp;		/* Horizontal front porch */
- ! 	int		hbp;		/* Horizontal back porch */
- ! 	int		hsw;		/* Horizontal Sync Pulse Width */
- ! 	int		vfp;		/* Vertical front porch */
- ! 	int		vbp;		/* Vertical back porch */
- ! 	int		vsw;		/* Vertical Sync Pulse Width */
- ! 	unsigned int	pxl_clk;	/* Pixel clock */
- ! 	unsigned char	invert_pxl_clk;	/* Invert Pixel clock */
- ! };
-   
-   static struct da8xx_panel known_lcd_panels[] = {
-   	/* Sharp LCD035Q3DG01 */
- ! 	[0] = {
-   		.name = "Sharp_LCD035Q3DG01",
-   		.width = 320,
-   		.height = 240,
- --- 225,284 ----
-   	.accel = FB_ACCEL_NONE
-   };
-   
- ! static vsync_callback_t vsync_cb_handler;
- ! static void *vsync_cb_arg;
-   
-   static struct da8xx_panel known_lcd_panels[] = {
- + #if defined(CONFIG_CKB_LCD_SUPPORT) || defined(CONFIG_CKB_DVI_SUPPORT)
- + #ifdef CONFIG_CKB_LCD_SUPPORT
- + 	/* Visionx KTM050AL02 */
- + 	{
- + 		.name = "Visionx_KTM050AL02",
- + 		.width = 800,
- + 		.height = 480,
- + 		.hfp = 40,
- + 		.hbp = 40,
- + 		.hsw = 48,
- + 		.vfp = 13,
- + 		.vbp = 29,
- + 		.vsw = 3,
- + 		.pxl_clk = 33000000,
- + 		.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
- + 	},
- + 	/* Kyocera TCG070WVLPAAFA_AA00 */
- + 	{
- + 		.name = "KyoceraTCG070WVLPAAFA_AA00",
- + 		.width = 800,						
- + 		.height = 480,
- + 		.pxl_clk = 33200000,
- + 		.hbp = 88,		/* left_margin */
- + 		.hfp = 40,		/* right_margin */
- + 		.vbp = 32,		/* upper_margin */
- + 		.vfp = 11,		/* lower_margin */
- + 		.hsw = 128,		/* hsync_len */
- + 		.vsw = 2,			/* vsync_len */
- + 		.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,     
- + 	},
- + #endif
- + #ifdef CONFIG_CKB_DVI_SUPPORT
- + 	/* Generic DVI monitor (This setting works for most monitors) */
- + 	{
- + 		.name = "Generic DVI panel",
- + 		.width = 800,
- + 		.height = 480,
- + 		.pxl_clk = 33000000,
- + 		.hbp = 40,
- + 		.hfp = 40,
- + 		.vbp = 29,
- + 		.vfp = 13,
- + 		.hsw = 48,
- + 		.vsw = 3,
- + 		.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
- + 	},
- + #endif
- + #else
-   	/* Sharp LCD035Q3DG01 */
- ! 	{
-   		.name = "Sharp_LCD035Q3DG01",
-   		.width = 320,
-   		.height = 240,
- ***************
- *** 222,243 ****
-   		.vbp = 2,
-   		.vsw = 0,
-   		.pxl_clk = 4608000,
- ! 		.invert_pxl_clk = 1,
-   	},
-   	/* Sharp LK043T1DG01 */
- ! 	[1] = {
-   		.name = "Sharp_LK043T1DG01",
-   		.width = 480,
-   		.height = 272,
-   		.hfp = 2,
-   		.hbp = 2,
-   		.hsw = 41,
- ! 		.vfp = 2,
- ! 		.vbp = 2,
-   		.vsw = 10,
-   		.pxl_clk = 7833600,
- ! 		.invert_pxl_clk = 0,
-   	},
-   };
-   
-   /* Enable the Raster Engine of the LCD Controller */
- --- 289,340 ----
-   		.vbp = 2,
-   		.vsw = 0,
-   		.pxl_clk = 4608000,
- ! 		.sync           = FB_SYNC_CLK_INVERT |
- ! 			FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-   	},
-   	/* Sharp LK043T1DG01 */
- ! 	{
-   		.name = "Sharp_LK043T1DG01",
-   		.width = 480,
-   		.height = 272,
-   		.hfp = 2,
-   		.hbp = 2,
-   		.hsw = 41,
- ! 		.vfp = 3,
- ! 		.vbp = 3,
-   		.vsw = 10,
-   		.pxl_clk = 7833600,
- ! 		.sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
- ! 	},
- ! 	/* ThreeFive S9700RTWV35TR */
- ! 	{
- ! 		.name = "TFC_S9700RTWV35TR_01B",
- ! 		.width = 800,
- ! 		.height = 480,
- ! 		.hfp = 39,
- ! 		.hbp = 39,
- ! 		.hsw = 47,
- ! 		.vfp = 13,
- ! 		.vbp = 29,
- ! 		.vsw = 2,
- ! 		.pxl_clk = 30000000,
- ! 		.sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
- ! 	},
- ! 	/* Newhaven Display */
- ! 	{
- ! 		.name = "NHD-4.3-ATXI#-T-1",
- ! 		.width = 480,
- ! 		.height = 272,
- ! 		.hfp = 8,
- ! 		.hbp = 43,
- ! 		.hsw = 4,
- ! 		.vfp = 4,
- ! 		.vbp = 12,
- ! 		.vsw = 10,
- ! 		.pxl_clk = 9000000,
- ! 		.sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-   	},
- + #endif
-   };
-   
-   /* Enable the Raster Engine of the LCD Controller */
- ***************
- *** 245,271 ****
-   {
-   	u32 reg;
-   
-   	/* Bring LCDC out of reset */
-   	if (lcd_revision == LCD_VERSION_2)
-   		lcdc_write(0, LCD_CLK_RESET_REG);
-   
-   	reg = lcdc_read(LCD_RASTER_CTRL_REG);
-   	if (!(reg & LCD_RASTER_ENABLE))
-   		lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
-   }
-   
-   /* Disable the Raster Engine of the LCD Controller */
- ! static inline void lcd_disable_raster(void)
-   {
-   	u32 reg;
-   
-   	reg = lcdc_read(LCD_RASTER_CTRL_REG);
-   	if (reg & LCD_RASTER_ENABLE)
-   		lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
-   
- ! 	if (lcd_revision == LCD_VERSION_2)
- ! 		/* Write 1 to reset LCDC */
- ! 		lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
-   }
-   
-   static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
- --- 342,399 ----
-   {
-   	u32 reg;
-   
- + 	/* Put LCDC in reset for several cycles */
- + 	if (lcd_revision == LCD_VERSION_2)
- + 		lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
- + 
- + 	mdelay(1);
- + 
-   	/* Bring LCDC out of reset */
-   	if (lcd_revision == LCD_VERSION_2)
-   		lcdc_write(0, LCD_CLK_RESET_REG);
-   
- + 	mdelay(1);
- + 
- + 	/* Above reset sequence doesnot reset register context */
-   	reg = lcdc_read(LCD_RASTER_CTRL_REG);
-   	if (!(reg & LCD_RASTER_ENABLE))
-   		lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
-   }
-   
-   /* Disable the Raster Engine of the LCD Controller */
- ! static inline void lcd_disable_raster(bool wait_for_frame_done)
-   {
-   	u32 reg;
- + 	u32 loop_cnt = 0;
- + 	u32 stat;
- + 	u32 i = 0;
- + 
- + 	if (wait_for_frame_done)
- + 		loop_cnt = 5000;
-   
-   	reg = lcdc_read(LCD_RASTER_CTRL_REG);
-   	if (reg & LCD_RASTER_ENABLE)
-   		lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
-   
- ! 	/* Wait for the current frame to complete */
- ! 	do {
- ! 		if (lcd_revision == LCD_VERSION_1)
- ! 			stat = lcdc_read(LCD_STAT_REG);
- ! 		else
- ! 			stat = lcdc_read(LCD_RAW_STAT_REG);
- ! 
- ! 		mdelay(1);
- ! 	} while (!(stat & BIT(0)) && (i++ < loop_cnt));
- ! 
- ! 	if (lcd_revision == LCD_VERSION_1)
- ! 		lcdc_write(stat, LCD_STAT_REG);
- ! 	else
- ! 		lcdc_write(stat, LCD_MASKED_STAT_REG);
- ! 
- ! 	if ((loop_cnt != 0) && (i >= loop_cnt)) {
- ! 		printk(KERN_ERR "LCD Controller timed out\n");
- ! 		return;
- ! 	}
-   }
-   
-   static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
- ***************
- *** 292,298 ****
-   		} else {
-   			reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
-   				LCD_V2_END_OF_FRAME0_INT_ENA |
- ! 				LCD_V2_END_OF_FRAME1_INT_ENA;
-   			lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
-   		}
-   		reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
- --- 420,427 ----
-   		} else {
-   			reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
-   				LCD_V2_END_OF_FRAME0_INT_ENA |
- ! 				LCD_V2_END_OF_FRAME1_INT_ENA |
- ! 				LCD_V2_UNDERFLOW_INT_ENA | LCD_SYNC_LOST;
-   			lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
-   		}
-   		reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
- ***************
- *** 329,336 ****
-   	lcd_enable_raster();
-   }
-   
- ! /* Configure the Burst Size of DMA */
- ! static int lcd_cfg_dma(int burst_size)
-   {
-   	u32 reg;
-   
- --- 458,465 ----
-   	lcd_enable_raster();
-   }
-   
- ! /* Configure the Burst Size and fifo threhold of DMA */
- ! static int lcd_cfg_dma(int burst_size,  int fifo_th)
-   {
-   	u32 reg;
-   
- ***************
- *** 354,359 ****
- --- 483,491 ----
-   	default:
-   		return -EINVAL;
-   	}
- + 
- + 	reg |= (fifo_th << 8);
- + 
-   	lcdc_write(reg, LCD_DMA_CTRL_REG);
-   
-   	return 0;
- ***************
- *** 374,385 ****
- --- 506,534 ----
-   		int front_porch)
-   {
-   	u32 reg;
- + 	
- + #if 1
- + 	/* fill low bits */
- + 	reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0x3ff;
- + 	reg |= ((back_porch & 0xff) << 24)
- + 	    | ((front_porch & 0xff) << 16)
- + 	    | ((pulse_width & 0x3f) << 10);
- + 	lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
-   
- + 	/* fill high bits */
- + 	reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0x07ffff00;
- + 	reg |= (((back_porch & 0x300)>>8) << 4)
- + 	    | (((front_porch & 0x300)>>8))
- + 	    | (((pulse_width & 0x3C0)>>6) << 27);
- + 	lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
- + #else
-   	reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf;
-   	reg |= ((back_porch & 0xff) << 24)
-   	    | ((front_porch & 0xff) << 16)
-   	    | ((pulse_width & 0x3f) << 10);
-   	lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
- + #endif	
- + 	
-   }
-   
-   static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
- ***************
- *** 394,400 ****
-   	lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
-   }
-   
- ! static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
-   {
-   	u32 reg;
-   	u32 reg_int;
- --- 543,550 ----
-   	lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
-   }
-   
- ! static int lcd_cfg_display(const struct lcd_ctrl_config *cfg,
- ! 		struct da8xx_panel *panel)
-   {
-   	u32 reg;
-   	u32 reg_int;
- ***************
- *** 447,458 ****
-   	else
-   		reg &= ~LCD_SYNC_EDGE;
-   
- ! 	if (cfg->invert_line_clock)
-   		reg |= LCD_INVERT_LINE_CLOCK;
-   	else
-   		reg &= ~LCD_INVERT_LINE_CLOCK;
-   
- ! 	if (cfg->invert_frm_clock)
-   		reg |= LCD_INVERT_FRAME_CLOCK;
-   	else
-   		reg &= ~LCD_INVERT_FRAME_CLOCK;
- --- 597,608 ----
-   	else
-   		reg &= ~LCD_SYNC_EDGE;
-   
- ! 	if (panel->sync & FB_SYNC_HOR_HIGH_ACT)
-   		reg |= LCD_INVERT_LINE_CLOCK;
-   	else
-   		reg &= ~LCD_INVERT_LINE_CLOCK;
-   
- ! 	if (panel->sync & FB_SYNC_VERT_HIGH_ACT)
-   		reg |= LCD_INVERT_FRAME_CLOCK;
-   	else
-   		reg &= ~LCD_INVERT_FRAME_CLOCK;
- ***************
- *** 510,515 ****
- --- 660,672 ----
-   	reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);
-   	if (raster_order)
-   		reg |= LCD_RASTER_ORDER;
- + 
- + 	if (bpp == 24)
- + 		reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE);
- + 	else if (bpp == 32)
- + 		reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE
- + 				| LCD_V2_TFT_24BPP_UNPACK);
- + 
-   	lcdc_write(reg, LCD_RASTER_CTRL_REG);
-   
-   	switch (bpp) {
- ***************
- *** 517,522 ****
- --- 674,681 ----
-   	case 2:
-   	case 4:
-   	case 16:
- + 	case 24:
- + 	case 32:
-   		par->palette_sz = 16 * 2;
-   		break;
-   
- ***************
- *** 575,580 ****
- --- 734,756 ----
-   			update_hw = 1;
-   			palette[0] = 0x4000;
-   		}
- + 	} else if (((info->var.bits_per_pixel == 32) && regno < 32) ||
- + 		    ((info->var.bits_per_pixel == 24) && regno < 24)) {
- + 		red >>= (24 - info->var.red.length);
- + 		red <<= info->var.red.offset;
- + 
- + 		green >>= (24 - info->var.green.length);
- + 		green <<= info->var.green.offset;
- + 
- + 		blue >>= (24 - info->var.blue.length);
- + 		blue <<= info->var.blue.offset;
- + 
- + 		par->pseudo_palette[regno] = red | green | blue;
- + 
- + 		if (palette[0] != 0x4000) {
- + 			update_hw = 1;
- + 			palette[0] = 0x4000;
- + 		}
-   	}
-   
-   	/* Update the palette in the h/w as needed. */
- ***************
- *** 587,593 ****
-   static void lcd_reset(struct da8xx_fb_par *par)
-   {
-   	/* Disable the Raster if previously Enabled */
- ! 	lcd_disable_raster();
-   
-   	/* DMA has to be disabled */
-   	lcdc_write(0, LCD_DMA_CTRL_REG);
- --- 763,769 ----
-   static void lcd_reset(struct da8xx_fb_par *par)
-   {
-   	/* Disable the Raster if previously Enabled */
- ! 	lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
-   
-   	/* DMA has to be disabled */
-   	lcdc_write(0, LCD_DMA_CTRL_REG);
- ***************
- *** 601,613 ****
-   	}
-   }
-   
-   static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
-   {
-   	unsigned int lcd_clk, div;
- - 
-   	lcd_clk = clk_get_rate(par->lcdc_clk);
-   	div = lcd_clk / par->pxl_clk;
- ! 
-   	/* Configure the LCD clock divisor. */
-   	lcdc_write(LCD_CLK_DIVISOR(div) |
-   			(LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);
- --- 777,857 ----
-   	}
-   }
-   
- + #if defined(CONFIG_LCD_CLOCK_CLOSEST_MATCH)
- + int get_clk_divider(struct da8xx_fb_par *par)
- + {
- + 	/* try to get a good value by calculating the best PLL clock and divider */
- + 	volatile int best_divider;
- + 	volatile int output_clock;
- + 	volatile unsigned long best_difference = 0xffffffff;
- + 	volatile int i, div;
- + 	volatile unsigned long difference;
- + 	volatile int dpll_clock;
- + 	volatile int dpll_divider;
- + 	/* check to see if the exact divider or divider+1 will give a nearest value */
- + 	/* The only way to get the precise clock is to alter DPLL clock */ 
- + 	/* check the CM_DIV_M2_DPLL_DISP Register */
- + 	int orig_rate = clk_get_rate(par->lcdc_clk);
- + 	volatile int found = 0;
- + 	for(i=1; i<=1; i++)
- + 	{
- + 		dpll_clock = orig_rate/i;
- + 		
- + 		/* calculate upper difference; the clock obtained here will be faster than what is requested */
- + 		div = dpll_clock / par->pxl_clk;
- + 		if(div>1)
- + 		{
- + 			output_clock = dpll_clock / div;
- + 			difference = output_clock - par->pxl_clk;
- + 			if(output_clock - par->pxl_clk <= best_difference)
- + 			{
- + 				best_difference = difference;
- + 				best_divider = div;
- + 				dpll_divider = i;
- + 				found = 1;
- + 			}
- + 		}
- + 		if(div>0)
- + 		{
- + 			/* calculate lower difference; the clock obtained here will be slower than what is requested */
- + 			output_clock = dpll_clock / (div+1);
- + 			difference = par->pxl_clk - output_clock;
- + 			if(par->pxl_clk - output_clock <= best_difference)
- + 			{
- + 				best_difference = difference;
- + 				best_divider = div+1;
- + 				dpll_divider = i;
- + 				found = 1;
- + 			}
- + 		}
- + 	}
- + 	if(found)
- + 	{
- + 		div = best_divider;
- + //		par->pxl_clk = best_output_clock;
- + 	}
- + 	else
- + 	{
- + 		div = clk_get_rate(par->lcdc_clk) / par->pxl_clk;
- + 	}
- + 	//printk("****div=%d, dpll_divider=%d", div, dpll_divider);
- + 	return div;
- + 	
- + }
- + #endif
- + 
-   static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
-   {
- + #if defined(CONFIG_LCD_CLOCK_CLOSEST_MATCH)
- + 	unsigned int div;
- + 	div = get_clk_divider(par);
- + 	//printk("***clock divider = %d\n", div);
- + #else
-   	unsigned int lcd_clk, div;
-   	lcd_clk = clk_get_rate(par->lcdc_clk);
-   	div = lcd_clk / par->pxl_clk;
- ! #endif
- ! 	
-   	/* Configure the LCD clock divisor. */
-   	lcdc_write(LCD_CLK_DIVISOR(div) |
-   			(LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);
- ***************
- *** 615,643 ****
-   	if (lcd_revision == LCD_VERSION_2)
-   		lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
-   				LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG);
- - 
-   }
-   
-   static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
- ! 		struct da8xx_panel *panel)
-   {
-   	u32 bpp;
-   	int ret = 0;
-   
- ! 	lcd_reset(par);
-   
-   	/* Calculate the divider */
-   	lcd_calc_clk_divider(par);
-   
- ! 	if (panel->invert_pxl_clk)
-   		lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) |
-   			LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
-   	else
-   		lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) &
-   			~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
-   
- ! 	/* Configure the DMA burst size. */
- ! 	ret = lcd_cfg_dma(cfg->dma_burst_sz);
-   	if (ret < 0)
-   		return ret;
-   
- --- 859,891 ----
-   	if (lcd_revision == LCD_VERSION_2)
-   		lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
-   				LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG);
-   }
-   
-   static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
- ! 		struct da8xx_panel *panel, unsigned char reset)
-   {
-   	u32 bpp;
-   	int ret = 0;
-   
- ! 	if(reset)
- ! 	{
- ! 		lcd_reset(par);
- ! 		
- ! 	}
-   
-   	/* Calculate the divider */
-   	lcd_calc_clk_divider(par);
-   
- ! 
- ! 	if (panel->sync & FB_SYNC_CLK_INVERT)
-   		lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) |
-   			LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
-   	else
-   		lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) &
-   			~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
-   
- ! 	/* Configure the DMA burst size and fifo threshold. */
- ! 	ret = lcd_cfg_dma(cfg->dma_burst_sz, cfg->fifo_th);
-   	if (ret < 0)
-   		return ret;
-   
- ***************
- *** 649,659 ****
-   	lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
-   
-   	/* Configure for disply */
- ! 	ret = lcd_cfg_display(cfg);
-   	if (ret < 0)
-   		return ret;
-   
- ! 	if (QVGA != cfg->p_disp_panel->panel_type)
-   		return -EINVAL;
-   
-   	if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
- --- 897,909 ----
-   	lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
-   
-   	/* Configure for disply */
- ! 	ret = lcd_cfg_display(cfg, panel);
-   	if (ret < 0)
-   		return ret;
-   
- ! 
- ! 	if ((QVGA != cfg->p_disp_panel->panel_type) &&
- ! 			(WVGA != cfg->p_disp_panel->panel_type))
-   		return -EINVAL;
-   
-   	if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
- ***************
- *** 676,681 ****
- --- 926,957 ----
-   	return 0;
-   }
-   
- + int register_vsync_cb(vsync_callback_t handler, void *arg, int idx)
- + {
- + 	if ((vsync_cb_handler == NULL) && (vsync_cb_arg == NULL)) {
- + 		vsync_cb_handler = handler;
- + 		vsync_cb_arg = arg;
- + 	} else {
- + 		return -EEXIST;
- + 	}
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(register_vsync_cb);
- + 
- + int unregister_vsync_cb(vsync_callback_t handler, void *arg, int idx)
- + {
- + 	if ((vsync_cb_handler == handler) && (vsync_cb_arg == arg)) {
- + 		vsync_cb_handler = NULL;
- + 		vsync_cb_arg = NULL;
- + 	} else {
- + 		return -ENXIO;
- + 	}
- + 
- + 	return 0;
- + }
- + EXPORT_SYMBOL(unregister_vsync_cb);
- + 
-   /* IRQ handler for version 2 of LCDC */
-   static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg)
-   {
- ***************
- *** 684,690 ****
-   	u32 reg_int;
-   
-   	if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
- ! 		lcd_disable_raster();
-   		lcdc_write(stat, LCD_MASKED_STAT_REG);
-   		lcd_enable_raster();
-   	} else if (stat & LCD_PL_LOAD_DONE) {
- --- 960,967 ----
-   	u32 reg_int;
-   
-   	if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
- ! 		printk(KERN_ERR "LCDC sync lost or underflow error occured\n");
- ! 		lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
-   		lcdc_write(stat, LCD_MASKED_STAT_REG);
-   		lcd_enable_raster();
-   	} else if (stat & LCD_PL_LOAD_DONE) {
- ***************
- *** 694,700 ****
-   		 * interrupt via the following write to the status register. If
-   		 * this is done after then one gets multiple PL done interrupts.
-   		 */
- ! 		lcd_disable_raster();
-   
-   		lcdc_write(stat, LCD_MASKED_STAT_REG);
-   
- --- 971,977 ----
-   		 * interrupt via the following write to the status register. If
-   		 * this is done after then one gets multiple PL done interrupts.
-   		 */
- ! 		lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
-   
-   		lcdc_write(stat, LCD_MASKED_STAT_REG);
-   
- ***************
- *** 709,729 ****
- --- 986,1012 ----
-   		lcdc_write(stat, LCD_MASKED_STAT_REG);
-   
-   		if (stat & LCD_END_OF_FRAME0) {
- + 			par->which_dma_channel_done = 0;
-   			lcdc_write(par->dma_start,
-   				   LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
-   			lcdc_write(par->dma_end,
-   				   LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
-   			par->vsync_flag = 1;
-   			wake_up_interruptible(&par->vsync_wait);
- + 			if (vsync_cb_handler)
- + 				vsync_cb_handler(vsync_cb_arg);
-   		}
-   
-   		if (stat & LCD_END_OF_FRAME1) {
- + 			par->which_dma_channel_done = 1;
-   			lcdc_write(par->dma_start,
-   				   LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
-   			lcdc_write(par->dma_end,
-   				   LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
-   			par->vsync_flag = 1;
-   			wake_up_interruptible(&par->vsync_wait);
- + 			if (vsync_cb_handler)
- + 				vsync_cb_handler(vsync_cb_arg);
-   		}
-   	}
-   
- ***************
- *** 739,747 ****
-   	u32 reg_ras;
-   
-   	if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
- ! 		lcd_disable_raster();
-   		lcdc_write(stat, LCD_STAT_REG);
-   		lcd_enable_raster();
-   	} else if (stat & LCD_PL_LOAD_DONE) {
-   		/*
-   		 * Must disable raster before changing state of any control bit.
- --- 1022,1033 ----
-   	u32 reg_ras;
-   
-   	if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
- ! 		printk(KERN_ERR "LCDC sync lost or underflow error occured\n");
- ! 		lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
- ! 		clk_disable(par->lcdc_clk);
-   		lcdc_write(stat, LCD_STAT_REG);
-   		lcd_enable_raster();
- + 		clk_enable(par->lcdc_clk);
-   	} else if (stat & LCD_PL_LOAD_DONE) {
-   		/*
-   		 * Must disable raster before changing state of any control bit.
- ***************
- *** 749,755 ****
-   		 * interrupt via the following write to the status register. If
-   		 * this is done after then one gets multiple PL done interrupts.
-   		 */
- ! 		lcd_disable_raster();
-   
-   		lcdc_write(stat, LCD_STAT_REG);
-   
- --- 1035,1041 ----
-   		 * interrupt via the following write to the status register. If
-   		 * this is done after then one gets multiple PL done interrupts.
-   		 */
- ! 		lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
-   
-   		lcdc_write(stat, LCD_STAT_REG);
-   
- ***************
- *** 822,827 ****
- --- 1108,1131 ----
-   		var->transp.offset = 0;
-   		var->transp.length = 0;
-   		break;
- + 	case 24:
- + 		var->red.offset = 16;
- + 		var->red.length = 8;
- + 		var->green.offset = 8;
- + 		var->green.length = 8;
- + 		var->blue.offset = 0;
- + 		var->blue.length = 8;
- + 		break;
- + 	case 32:
- + 		var->transp.offset = 24;
- + 		var->transp.length = 8;
- + 		var->red.offset = 16;
- + 		var->red.length = 8;
- + 		var->green.offset = 8;
- + 		var->green.length = 8;
- + 		var->blue.offset = 0;
- + 		var->blue.length = 8;
- + 		break;
-   	default:
-   		err = -EINVAL;
-   	}
- ***************
- *** 840,850 ****
-   	struct da8xx_fb_par *par;
-   
-   	par = container_of(nb, struct da8xx_fb_par, freq_transition);
- ! 	if (val == CPUFREQ_PRECHANGE) {
- ! 		lcd_disable_raster();
- ! 	} else if (val == CPUFREQ_POSTCHANGE) {
- ! 		lcd_calc_clk_divider(par);
- ! 		lcd_enable_raster();
-   	}
-   
-   	return 0;
- --- 1144,1155 ----
-   	struct da8xx_fb_par *par;
-   
-   	par = container_of(nb, struct da8xx_fb_par, freq_transition);
- ! 	if (val == CPUFREQ_POSTCHANGE) {
- ! 		if (par->lcd_fck_rate != clk_get_rate(par->lcdc_clk)) {
- ! 			lcd_disable_raster(WAIT_FOR_FRAME_DONE);
- ! 			lcd_calc_clk_divider(par);
- ! 			lcd_enable_raster();
- ! 		}
-   	}
-   
-   	return 0;
- ***************
- *** 878,884 ****
-   		if (par->panel_power_ctrl)
-   			par->panel_power_ctrl(0);
-   
- ! 		lcd_disable_raster();
-   		lcdc_write(0, LCD_RASTER_CTRL_REG);
-   
-   		/* disable DMA  */
- --- 1183,1189 ----
-   		if (par->panel_power_ctrl)
-   			par->panel_power_ctrl(0);
-   
- ! 		lcd_disable_raster(WAIT_FOR_FRAME_DONE);
-   		lcdc_write(0, LCD_RASTER_CTRL_REG);
-   
-   		/* disable DMA  */
- ***************
- *** 888,898 ****
-   		fb_dealloc_cmap(&info->cmap);
-   		dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
-   				  par->p_palette_base);
- ! 		dma_free_coherent(NULL, par->vram_size, par->vram_virt,
- ! 				  par->vram_phys);
-   		free_irq(par->irq, par);
- ! 		clk_disable(par->lcdc_clk);
- ! 		clk_put(par->lcdc_clk);
-   		framebuffer_release(info);
-   		iounmap((void __iomem *)da8xx_fb_reg_base);
-   		release_mem_region(lcdc_regs->start, resource_size(lcdc_regs));
- --- 1193,1211 ----
-   		fb_dealloc_cmap(&info->cmap);
-   		dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
-   				  par->p_palette_base);
- ! 		if(!par->dma_alloc)
- ! 		{
- ! 			iounmap((void __iomem *)par->vram_virt);
- ! 			release_mem_region(par->vram_phys, par->vram_size);
- ! 		}
- ! 		else
- ! 		{
- ! 			dma_free_coherent(NULL, par->vram_size, par->vram_virt,
- ! 					  par->vram_phys);
- ! 		}
-   		free_irq(par->irq, par);
- ! 		pm_runtime_put_sync(&dev->dev);
- ! 		pm_runtime_disable(&dev->dev);
-   		framebuffer_release(info);
-   		iounmap((void __iomem *)da8xx_fb_reg_base);
-   		release_mem_region(lcdc_regs->start, resource_size(lcdc_regs));
- ***************
- *** 931,936 ****
- --- 1244,1257 ----
-   	if (ret == 0)
-   		return -ETIMEDOUT;
-   
- + 	if (par->panel_power_ctrl) {
- + 		/* Switch off panel power and backlight */
- + 		par->panel_power_ctrl(0);
- + 
- + 		/* Switch on panel power and backlight */
- + 		par->panel_power_ctrl(1);
- + 	}
- + 
-   	return 0;
-   }
-   
- ***************
- *** 987,997 ****
-   
-   		lcd_enable_raster();
-   		break;
-   	case FB_BLANK_POWERDOWN:
-   		if (par->panel_power_ctrl)
-   			par->panel_power_ctrl(0);
-   
- ! 		lcd_disable_raster();
-   		break;
-   	default:
-   		ret = -EINVAL;
- --- 1308,1321 ----
-   
-   		lcd_enable_raster();
-   		break;
- + 	case FB_BLANK_NORMAL:
- + 	case FB_BLANK_VSYNC_SUSPEND:
- + 	case FB_BLANK_HSYNC_SUSPEND:
-   	case FB_BLANK_POWERDOWN:
-   		if (par->panel_power_ctrl)
-   			par->panel_power_ctrl(0);
-   
- ! 		lcd_disable_raster(WAIT_FOR_FRAME_DONE);
-   		break;
-   	default:
-   		ret = -EINVAL;
- ***************
- *** 1013,1018 ****
- --- 1337,1343 ----
-   	struct fb_fix_screeninfo    *fix = &fbi->fix;
-   	unsigned int end;
-   	unsigned int start;
- + 	unsigned long irq_flags;
-   
-   	if (var->xoffset != fbi->var.xoffset ||
-   			var->yoffset != fbi->var.yoffset) {
- ***************
- *** 1030,1041 ****
- --- 1355,1508 ----
-   			end	= start + fbi->var.yres * fix->line_length - 1;
-   			par->dma_start	= start;
-   			par->dma_end	= end;
- + 			spin_lock_irqsave(&par->lock_for_chan_update,
- + 					irq_flags);
- + 			if (par->which_dma_channel_done == 0) {
- + 				lcdc_write(par->dma_start,
- + 					   LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
- + 				lcdc_write(par->dma_end,
- + 					   LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
- + 			} else if (par->which_dma_channel_done == 1) {
- + 				lcdc_write(par->dma_start,
- + 					   LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
- + 				lcdc_write(par->dma_end,
- + 					   LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
- + 			}
- + 			spin_unlock_irqrestore(&par->lock_for_chan_update,
- + 					irq_flags);
-   		}
-   	}
-   
-   	return ret;
-   }
-   
- + #if defined(CONFIG_CKB_LCD_SUPPORT) || defined(CONFIG_CKB_DVI_SUPPORT)
- + int reinit_fb_device(struct fb_info *info, struct da8xx_panel *lcdc_info);
- + 
- + /*
- +  * Switch to a new mode. The parameters for it has been check already by
- +  * fb_check_var.
- +  */
- + static int fb_initialized = 0;
- + 
- + 
- + static int ckb_fb_set_par(struct fb_info *info)
- + {
- + 	volatile struct fb_var_screeninfo *var;
- + 	int i;
- + 	int matched_index;
- + #ifdef CONFIG_CKB_DVI_SUPPORT
- + 	volatile struct fb_videomode *mode;
- + 	volatile struct fb_videomode *m;
- + 	
- + 	volatile unsigned int best_pico_difference = 0xffffffff;
- + 	volatile unsigned int difference;
- + #endif
- + 	if(!fb_initialized)
- + 	{
- + 		/* driver not initialized yet */
- + 		return 0;
- + 	}
- + 	if(!info)
- + 	{
- + 		return -EINVAL;
- + 	}
- + 	var = &info->var;
- + 	if(!var)
- + 	{
- + 		return -EINVAL;
- + 	}
- + 
- + 	printk("Trying to set %dx%d @ %d...\n", var->xres, var->yres, var->pixclock);
- + #ifdef CONFIG_CKB_DVI_SUPPORT
- + 	/* check to see if a DVI monitor is connected and the mode is supported by it */
- + 	if(!get_dvi_info(info))
- + 	{
- + 		mode = NULL;
- + 		for (i=0; i < info->monspecs.modedb_len; i++) 
- + 		{
- + 			m = &info->monspecs.modedb[i];
- + 			if (m->pixclock == 0)
- + 				continue;
- + 			/* skip repeated pixel modes */
- + 			if (m->xres == var->xres && m->yres == var->yres)
- + 			{
- + 				/* find the best match for the pico secs */
- + 				if(m->pixclock < var->pixclock)
- + 				{
- + 					difference = var->pixclock - m->pixclock; 
- + 				}
- + 				else
- + 				{
- + 					difference = m->pixclock - var->pixclock;
- + 				}
- + 				if(difference < best_pico_difference)
- + 				{
- + 					/* closest match */
- + 					best_pico_difference = difference;
- + 					mode = m;
- + 				}
- + 			}
- + 		}
- + 		if(mode)
- + 		{
- + 			struct da8xx_panel dvi_panel;
- + 			/* fill the DVI mode structure */
- + 			dvi_panel.width = mode->xres;
- + 			dvi_panel.hbp = mode->left_margin;
- + 			dvi_panel.hfp = mode->right_margin;
- + 			dvi_panel.hsw = mode->hsync_len;
- + 			dvi_panel.height = mode->yres;
- + 			dvi_panel.vbp = mode->upper_margin;
- + 			dvi_panel.vfp = mode->lower_margin;
- + 			dvi_panel.vsw = mode->vsync_len;
- + 			
- + 			dvi_panel.pxl_clk = PICOS2KHZ(mode->pixclock) * 1000;
- + 			
- + 			printk("DVI %dx%d @ %dMHz (%d picosecs)\n",
- + 				dvi_panel.width, dvi_panel.height, dvi_panel.pxl_clk/1000000, mode->pixclock);
- + 				
- + 			reinit_fb_device(info, &dvi_panel);
- + 			return 0;
- + 		}
- + 	}
- + #endif
- + 
- + 	/* fall back to FB mode */
- + 	matched_index = -1;
- + 	for (i=0; i<ARRAY_SIZE(known_lcd_panels); i++)
- + 	{
- + 		/* check for a perfect match, otherwise use the last match */
- + 		if(var->xres == known_lcd_panels[i].width
- + 			&& var->yres == known_lcd_panels[i].height)
- + 		{
- + 			if(var->hsync_len == known_lcd_panels[i].hsw
- + 				&&	var->vsync_len == known_lcd_panels[i].vsw
- + 				&& var->right_margin == known_lcd_panels[i].hfp
- + 				&& var->left_margin  == known_lcd_panels[i].hbp
- + 				&& var->lower_margin == known_lcd_panels[i].vfp
- + 				&& var->upper_margin == known_lcd_panels[i].vbp)
- + 				{
- + 					break;
- + 				}
- + 			matched_index = i;
- + 		}
- + 	}
- + 	if (i != ARRAY_SIZE(known_lcd_panels)) {
- + 		printk("Done.\n");
- + 		reinit_fb_device(info, &known_lcd_panels[i]);
- + 		return 0;
- + 	}
- + 	if(matched_index != -1) {
- + 		printk("Perfect match not found. Resolution changed to supported panel.\n");
- + 		reinit_fb_device(info, &known_lcd_panels[matched_index]);
- + 		return 0;
- + 	}
- + 	pr_err("Display resolution not supported.\n");
- + 	return -EINVAL;
- + }
- + #endif
- + 
-   static struct fb_ops da8xx_fb_ops = {
-   	.owner = THIS_MODULE,
-   	.fb_check_var = fb_check_var,
- ***************
- *** 1046,1053 ****
- --- 1513,1620 ----
-   	.fb_copyarea = cfb_copyarea,
-   	.fb_imageblit = cfb_imageblit,
-   	.fb_blank = cfb_blank,
- + #if defined(CONFIG_CKB_LCD_SUPPORT) || defined(CONFIG_CKB_DVI_SUPPORT)
- + 	.fb_set_par = ckb_fb_set_par,
- + #endif
-   };
-   
- + /* Calculate and return pixel clock period in pico seconds */
- + static unsigned int da8xxfb_pixel_clk_period(struct da8xx_fb_par *par)
- + {
- + 	unsigned int lcd_clk, div;
- + 	unsigned int configured_pix_clk;
- + 	unsigned long long pix_clk_period_picosec = 1000000000000ULL;
- + 
- + 	lcd_clk = clk_get_rate(par->lcdc_clk);
- + 	//printk("*****LCD Clock rate = %d\n",  lcd_clk);
- + #if defined(CONFIG_LCD_CLOCK_CLOSEST_MATCH)
- + 	div = get_clk_divider(par);
- + #else
- + 	div = lcd_clk / par->pxl_clk;
- + #endif
- + 	configured_pix_clk = (lcd_clk / div);
- + 
- + 	do_div(pix_clk_period_picosec, configured_pix_clk);
- + 
- + 	return pix_clk_period_picosec;
- + }
- + 
- + #if defined(CONFIG_CKB_LCD_SUPPORT) || defined(CONFIG_CKB_DVI_SUPPORT)
- + int reinit_fb_device(struct fb_info *info, struct da8xx_panel *lcdc_info)
- + {
- + 	struct da8xx_fb_par *par;
- + 	struct device *dev;
- + 	struct da8xx_lcdc_platform_data *fb_pdata;
- + 	struct lcd_ctrl_config *lcd_cfg;
- + 	struct fb_info *da8xx_fb_info;
- + 
- + 	par = info->par;
- + 	dev = par->dev;
- + 	fb_pdata = dev->platform_data;
- + 	
- + 	da8xx_fb_info = dev_get_drvdata(dev);
- + 	lcd_cfg = (struct lcd_ctrl_config *)par->lcd_cfg;
- + 
- + 	par->pxl_clk = lcdc_info->pxl_clk;
- + 
- + 	/* disable the raster */		
- + 	lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
- + 
- + 	/* reinitialize the LCD */
- + 	if (lcd_init(par, lcd_cfg, lcdc_info, 0) < 0) {
- + 		dev_err(dev, "LCD controller reinit failed\n");
- + 		return -EFAULT;
- + 	}
- + 
- + 	da8xx_fb_fix.line_length   = (lcdc_info->width * lcd_cfg->bpp) / 8;
- + 	
- + 	par->dma_end   = par->dma_start + lcdc_info->height *
- + 		da8xx_fb_fix.line_length - 1;
- + 		
- + 	/* Initialize par */
- + 	da8xx_fb_info->var.bits_per_pixel = lcd_cfg->bpp;
- + 
- + 	da8xx_fb_var.xres = lcdc_info->width;
- + 	da8xx_fb_var.xres_virtual = lcdc_info->width;
- + 
- + 	da8xx_fb_var.yres         = lcdc_info->height;
- + 	da8xx_fb_var.yres_virtual = lcdc_info->height * LCD_NUM_BUFFERS;
- + 
- + 	da8xx_fb_var.grayscale =
- + 	    lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
- + 
- + 	da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp;
- + 
- + 	da8xx_fb_var.hsync_len = lcdc_info->hsw;
- + 	da8xx_fb_var.vsync_len = lcdc_info->vsw;
- + 
- + 	da8xx_fb_var.pixclock = da8xxfb_pixel_clk_period(par);
- + 	
- + 	da8xx_fb_var.right_margin = lcdc_info->hfp;
- + 	da8xx_fb_var.left_margin  = lcdc_info->hbp;
- + 	da8xx_fb_var.lower_margin = lcdc_info->vfp;
- + 	da8xx_fb_var.upper_margin = lcdc_info->vbp;
- + 
- + 	
- + 	/* Initialize fbinfo */
- + 	da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
- + 	da8xx_fb_info->fix = da8xx_fb_fix;
- + 	da8xx_fb_info->var = da8xx_fb_var;
- + 	da8xx_fb_info->fbops = &da8xx_fb_ops;
- + 
- + 	da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
- + 				FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
- + 
- + 	/* initialize var_screeninfo */
- + 	da8xx_fb_var.activate = FB_ACTIVATE_FORCE;
- + //	fb_set_var(da8xx_fb_info, &da8xx_fb_var);
- + 
- + 
- + 	lcd_enable_raster();
- + 	return 0;
- + }
- + #endif
- + 
-   static int __devinit fb_probe(struct platform_device *device)
-   {
-   	struct da8xx_lcdc_platform_data *fb_pdata =
- ***************
- *** 1059,1065 ****
-   	struct da8xx_fb_par *par;
-   	resource_size_t len;
-   	int ret, i;
- ! 
-   	if (fb_pdata == NULL) {
-   		dev_err(&device->dev, "Can not get platform data\n");
-   		return -ENOENT;
- --- 1626,1635 ----
-   	struct da8xx_fb_par *par;
-   	resource_size_t len;
-   	int ret, i;
- ! 	unsigned long ulcm;
- ! #if defined(CONFIG_CKB_LCD_SUPPORT) || defined(CONFIG_CKB_DVI_SUPPORT)
- ! 	fb_initialized = 0;
- ! #endif
-   	if (fb_pdata == NULL) {
-   		dev_err(&device->dev, "Can not get platform data\n");
-   		return -ENOENT;
- ***************
- *** 1090,1105 ****
-   		ret = -ENODEV;
-   		goto err_ioremap;
-   	}
- - 	ret = clk_enable(fb_clk);
- - 	if (ret)
- - 		goto err_clk_put;
-   
-   	/* Determine LCD IP Version */
-   	switch (lcdc_read(LCD_PID_REG)) {
-   	case 0x4C100102:
-   		lcd_revision = LCD_VERSION_1;
-   		break;
-   	case 0x4F200800:
-   		lcd_revision = LCD_VERSION_2;
-   		break;
-   	default:
- --- 1660,1677 ----
-   		ret = -ENODEV;
-   		goto err_ioremap;
-   	}
-   
- + 	pm_runtime_irq_safe(&device->dev);
- + 	pm_runtime_enable(&device->dev);
- + 	pm_runtime_get_sync(&device->dev);
- + 	
-   	/* Determine LCD IP Version */
-   	switch (lcdc_read(LCD_PID_REG)) {
-   	case 0x4C100102:
-   		lcd_revision = LCD_VERSION_1;
-   		break;
-   	case 0x4F200800:
- + 	case 0x4F201000:
-   		lcd_revision = LCD_VERSION_2;
-   		break;
-   	default:
- ***************
- *** 1120,1168 ****
-   	if (i == ARRAY_SIZE(known_lcd_panels)) {
-   		dev_err(&device->dev, "GLCD: No valid panel found\n");
-   		ret = -ENODEV;
- ! 		goto err_clk_disable;
-   	} else
-   		dev_info(&device->dev, "GLCD: Found %s panel\n",
-   					fb_pdata->type);
-   
-   	lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;
- ! 
-   	da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par),
-   					&device->dev);
-   	if (!da8xx_fb_info) {
-   		dev_dbg(&device->dev, "Memory allocation failed for fb_info\n");
-   		ret = -ENOMEM;
- ! 		goto err_clk_disable;
-   	}
- ! 
-   	par = da8xx_fb_info->par;
-   	par->lcdc_clk = fb_clk;
-   	par->pxl_clk = lcdc_info->pxl_clk;
-   	if (fb_pdata->panel_power_ctrl) {
-   		par->panel_power_ctrl = fb_pdata->panel_power_ctrl;
-   		par->panel_power_ctrl(1);
-   	}
-   
- ! 	if (lcd_init(par, lcd_cfg, lcdc_info) < 0) {
-   		dev_err(&device->dev, "lcd_init failed\n");
-   		ret = -EFAULT;
-   		goto err_release_fb;
-   	}
- - 
-   	/* allocate frame buffer */
-   	par->vram_size = lcdc_info->width * lcdc_info->height * lcd_cfg->bpp;
- ! 	par->vram_size = PAGE_ALIGN(par->vram_size/8);
-   	par->vram_size = par->vram_size * LCD_NUM_BUFFERS;
- ! 
- ! 	par->vram_virt = dma_alloc_coherent(NULL,
-   					    par->vram_size,
-   					    (resource_size_t *) &par->vram_phys,
-   					    GFP_KERNEL | GFP_DMA);
-   	if (!par->vram_virt) {
-   		dev_err(&device->dev,
-   			"GLCD: kmalloc for frame buffer failed\n");
-   		ret = -EINVAL;
- ! 		goto err_release_fb;
-   	}
-   
-   	da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt;
- --- 1692,1769 ----
-   	if (i == ARRAY_SIZE(known_lcd_panels)) {
-   		dev_err(&device->dev, "GLCD: No valid panel found\n");
-   		ret = -ENODEV;
- ! 		goto err_pm_runtime_disable;
-   	} else
-   		dev_info(&device->dev, "GLCD: Found %s panel\n",
-   					fb_pdata->type);
-   
-   	lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;
- ! 	
-   	da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par),
-   					&device->dev);
-   	if (!da8xx_fb_info) {
-   		dev_dbg(&device->dev, "Memory allocation failed for fb_info\n");
-   		ret = -ENOMEM;
- ! 		goto err_pm_runtime_disable;
-   	}
- ! 	
-   	par = da8xx_fb_info->par;
- + 	par->dev = &device->dev;
-   	par->lcdc_clk = fb_clk;
- + #ifdef CONFIG_CPU_FREQ
- + 	par->lcd_fck_rate = clk_get_rate(fb_clk);
- + #endif
-   	par->pxl_clk = lcdc_info->pxl_clk;
-   	if (fb_pdata->panel_power_ctrl) {
-   		par->panel_power_ctrl = fb_pdata->panel_power_ctrl;
-   		par->panel_power_ctrl(1);
-   	}
-   
- ! #if defined(CONFIG_CKB_LCD_SUPPORT) || defined(CONFIG_CKB_DVI_SUPPORT)
- ! 	par->lcd_cfg = lcd_cfg;
- ! 	if (lcd_init(par, lcd_cfg, lcdc_info, 0) < 0) {
- ! #else
- ! 	if (lcd_init(par, lcd_cfg, lcdc_info, 1) < 0) {
- ! #endif
-   		dev_err(&device->dev, "lcd_init failed\n");
-   		ret = -EFAULT;
-   		goto err_release_fb;
-   	}
-   	/* allocate frame buffer */
-   	par->vram_size = lcdc_info->width * lcdc_info->height * lcd_cfg->bpp;
- ! 	ulcm = lcm((lcdc_info->width * lcd_cfg->bpp)/8, PAGE_SIZE);
- ! 	
- ! 	par->vram_size = roundup(par->vram_size/8, ulcm);
-   	par->vram_size = par->vram_size * LCD_NUM_BUFFERS;
- ! 	
- ! 	if(fb_pdata->fb_mapped_physaddr != 0 && par->vram_size <= fb_pdata->fb_mapped_len)
- ! 	{
- ! 		/* use mapped address */
- ! 		par->vram_phys = fb_pdata->fb_mapped_physaddr;
- ! 		if (!request_mem_region(par->vram_phys, par->vram_size, "FB_mem"))
- ! 		{
- ! 			dev_err(&device->dev,
- ! 				"Memory request for FB failed\n");
- ! 			ret = -EFAULT;
- ! 			goto err_release_fb;
- ! 		}
- ! 		par->dma_alloc = 0;
- ! 		par->vram_virt = ioremap(par->vram_phys, par->vram_size);
- ! 	}
- ! 	else
- ! 	{
- ! 		/* map address from RAM */
- ! 		par->vram_virt = dma_alloc_coherent(NULL,
-   					    par->vram_size,
-   					    (resource_size_t *) &par->vram_phys,
-   					    GFP_KERNEL | GFP_DMA);
- + 		par->dma_alloc = 1;
- + 	}
-   	if (!par->vram_virt) {
-   		dev_err(&device->dev,
-   			"GLCD: kmalloc for frame buffer failed\n");
-   		ret = -EINVAL;
- ! 		goto err_release_fb_request;
-   	}
-   
-   	da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt;
- ***************
- *** 1209,1214 ****
- --- 1810,1822 ----
-   
-   	da8xx_fb_var.hsync_len = lcdc_info->hsw;
-   	da8xx_fb_var.vsync_len = lcdc_info->vsw;
- + 	
- + 	da8xx_fb_var.pixclock = da8xxfb_pixel_clk_period(par);
- + 
- + 	da8xx_fb_var.right_margin = lcdc_info->hfp;
- + 	da8xx_fb_var.left_margin  = lcdc_info->hbp;
- + 	da8xx_fb_var.lower_margin = lcdc_info->vfp;
- + 	da8xx_fb_var.upper_margin = lcdc_info->vbp;
-   
-   	/* Initialize fbinfo */
-   	da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
- ***************
- *** 1229,1238 ****
-   	fb_set_var(da8xx_fb_info, &da8xx_fb_var);
-   
-   	dev_set_drvdata(&device->dev, da8xx_fb_info);
- ! 
-   	/* initialize the vsync wait queue */
-   	init_waitqueue_head(&par->vsync_wait);
-   	par->vsync_timeout = HZ / 5;
-   
-   	/* Register the Frame Buffer  */
-   	if (register_framebuffer(da8xx_fb_info) < 0) {
- --- 1837,1848 ----
-   	fb_set_var(da8xx_fb_info, &da8xx_fb_var);
-   
-   	dev_set_drvdata(&device->dev, da8xx_fb_info);
- ! 	
-   	/* initialize the vsync wait queue */
-   	init_waitqueue_head(&par->vsync_wait);
-   	par->vsync_timeout = HZ / 5;
- + 	par->which_dma_channel_done = -1;
- + 	spin_lock_init(&par->lock_for_chan_update);
-   
-   	/* Register the Frame Buffer  */
-   	if (register_framebuffer(da8xx_fb_info) < 0) {
- ***************
- *** 1242,1247 ****
- --- 1852,1858 ----
-   		goto err_dealloc_cmap;
-   	}
-   
- + 
-   #ifdef CONFIG_CPU_FREQ
-   	ret = lcd_da8xx_cpufreq_register(par);
-   	if (ret) {
- ***************
- *** 1259,1271 ****
-   			DRIVER_NAME, par);
-   	if (ret)
-   		goto irq_freq;
-   	return 0;
-   
-   irq_freq:
-   #ifdef CONFIG_CPU_FREQ
-   	lcd_da8xx_cpufreq_deregister(par);
- - #endif
-   err_cpu_freq:
-   	unregister_framebuffer(da8xx_fb_info);
-   
-   err_dealloc_cmap:
- --- 1870,1889 ----
-   			DRIVER_NAME, par);
-   	if (ret)
-   		goto irq_freq;
- + 
- + #if defined(CONFIG_CKB_LCD_SUPPORT) || defined(CONFIG_CKB_DVI_SUPPORT)
- + 	fb_initialized = 1; 
- + 	set_fb_panel_info(known_lcd_panels, ARRAY_SIZE(known_lcd_panels), lcd_cfg->bpp);
- + 	append_fb_mode();
- + 	close_video_mode_file();
- + #endif
-   	return 0;
-   
-   irq_freq:
-   #ifdef CONFIG_CPU_FREQ
-   	lcd_da8xx_cpufreq_deregister(par);
-   err_cpu_freq:
- + #endif
-   	unregister_framebuffer(da8xx_fb_info);
-   
-   err_dealloc_cmap:
- ***************
- *** 1276,1293 ****
-   			  par->p_palette_base);
-   
-   err_release_fb_mem:
- ! 	dma_free_coherent(NULL, par->vram_size, par->vram_virt, par->vram_phys);
- ! 
-   err_release_fb:
-   	framebuffer_release(da8xx_fb_info);
-   
- ! err_clk_disable:
- ! 	clk_disable(fb_clk);
- ! 
- ! err_clk_put:
- ! 	clk_put(fb_clk);
-   
-   err_ioremap:
-   	iounmap((void __iomem *)da8xx_fb_reg_base);
-   
-   err_request_mem:
- --- 1894,1915 ----
-   			  par->p_palette_base);
-   
-   err_release_fb_mem:
- ! 	if(!par->dma_alloc)
- ! 		iounmap((void __iomem *)par->vram_virt);
- ! 	else
- ! 		dma_free_coherent(NULL, par->vram_size, par->vram_virt, par->vram_phys);
- ! err_release_fb_request:
- ! 	if(!par->dma_alloc)
- ! 		release_mem_region(par->vram_phys, par->vram_size);
-   err_release_fb:
-   	framebuffer_release(da8xx_fb_info);
-   
- ! err_pm_runtime_disable:
- ! 	pm_runtime_put_sync(&device->dev);
- ! 	pm_runtime_disable(&device->dev);
-   
-   err_ioremap:
- + 
-   	iounmap((void __iomem *)da8xx_fb_reg_base);
-   
-   err_request_mem:
- ***************
- *** 1297,1302 ****
- --- 1919,1982 ----
-   }
-   
-   #ifdef CONFIG_PM
- + 
- + struct lcdc_context {
- + 	u32 clk_enable;
- + 	u32 ctrl;
- + 	u32 dma_ctrl;
- + 	u32 raster_timing_0;
- + 	u32 raster_timing_1;
- + 	u32 raster_timing_2;
- + 	u32 int_enable_set;
- + 	u32 dma_frm_buf_base_addr_0;
- + 	u32 dma_frm_buf_ceiling_addr_0;
- + 	u32 dma_frm_buf_base_addr_1;
- + 	u32 dma_frm_buf_ceiling_addr_1;
- + 	u32 raster_ctrl;
- + } reg_context;
- + 
- + static void lcd_context_save(void)
- + {
- + 	reg_context.clk_enable = lcdc_read(LCD_CLK_ENABLE_REG);
- + 	reg_context.ctrl = lcdc_read(LCD_CTRL_REG);
- + 	reg_context.dma_ctrl = lcdc_read(LCD_DMA_CTRL_REG);
- + 	reg_context.raster_timing_0 = lcdc_read(LCD_RASTER_TIMING_0_REG);
- + 	reg_context.raster_timing_1 = lcdc_read(LCD_RASTER_TIMING_1_REG);
- + 	reg_context.raster_timing_2 = lcdc_read(LCD_RASTER_TIMING_2_REG);
- + 	reg_context.int_enable_set = lcdc_read(LCD_INT_ENABLE_SET_REG);
- + 	reg_context.dma_frm_buf_base_addr_0 =
- + 		lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
- + 	reg_context.dma_frm_buf_ceiling_addr_0 =
- + 		lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
- + 	reg_context.dma_frm_buf_base_addr_1 =
- + 		lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
- + 	reg_context.dma_frm_buf_ceiling_addr_1 =
- + 		lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
- + 	reg_context.raster_ctrl = lcdc_read(LCD_RASTER_CTRL_REG);
- + 	return;
- + }
- + 
- + static void lcd_context_restore(void)
- + {
- + 	lcdc_write(reg_context.clk_enable, LCD_CLK_ENABLE_REG);
- + 	lcdc_write(reg_context.ctrl, LCD_CTRL_REG);
- + 	lcdc_write(reg_context.dma_ctrl, LCD_DMA_CTRL_REG);
- + 	lcdc_write(reg_context.raster_timing_0, LCD_RASTER_TIMING_0_REG);
- + 	lcdc_write(reg_context.raster_timing_1, LCD_RASTER_TIMING_1_REG);
- + 	lcdc_write(reg_context.raster_timing_2, LCD_RASTER_TIMING_2_REG);
- + 	lcdc_write(reg_context.int_enable_set, LCD_INT_ENABLE_SET_REG);
- + 	lcdc_write(reg_context.dma_frm_buf_base_addr_0,
- + 			LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
- + 	lcdc_write(reg_context.dma_frm_buf_ceiling_addr_0,
- + 			LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
- + 	lcdc_write(reg_context.dma_frm_buf_base_addr_1,
- + 			LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
- + 	lcdc_write(reg_context.dma_frm_buf_ceiling_addr_1,
- + 			LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
- + 	lcdc_write(reg_context.raster_ctrl, LCD_RASTER_CTRL_REG);
- + 	return;
- + }
- + 
-   static int fb_suspend(struct platform_device *dev, pm_message_t state)
-   {
-   	struct fb_info *info = platform_get_drvdata(dev);
- ***************
- *** 1307,1314 ****
-   		par->panel_power_ctrl(0);
-   
-   	fb_set_suspend(info, 1);
- ! 	lcd_disable_raster();
- ! 	clk_disable(par->lcdc_clk);
-   	console_unlock();
-   
-   	return 0;
- --- 1987,1996 ----
-   		par->panel_power_ctrl(0);
-   
-   	fb_set_suspend(info, 1);
- ! 	lcd_disable_raster(WAIT_FOR_FRAME_DONE);
- ! 	lcd_context_save();
- ! 
- ! 	pm_runtime_put(&dev->dev);
-   	console_unlock();
-   
-   	return 0;
- ***************
- *** 1319,1329 ****
-   	struct da8xx_fb_par *par = info->par;
-   
-   	console_lock();
-   	if (par->panel_power_ctrl)
-   		par->panel_power_ctrl(1);
-   
- - 	clk_enable(par->lcdc_clk);
- - 	lcd_enable_raster();
-   	fb_set_suspend(info, 0);
-   	console_unlock();
-   
- --- 2001,2016 ----
-   	struct da8xx_fb_par *par = info->par;
-   
-   	console_lock();
- + 
- + 	pm_runtime_get_sync(&dev->dev);
- + 
- + 	msleep(1);
- + 	lcd_context_restore();
- + 	lcd_enable_raster();
- + 
-   	if (par->panel_power_ctrl)
-   		par->panel_power_ctrl(1);
-   
-   	fb_set_suspend(info, 0);
-   	console_unlock();
-   
- diff -crN linux-3.2.1_o/drivers/video/fb_ddc.c linux-3.2.1/drivers/video/fb_ddc.c
- *** linux-3.2.1_o/drivers/video/fb_ddc.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/video/fb_ddc.c	2014-05-15 13:25:15.122662428 +0900
- ***************
- *** 19,25 ****
- --- 19,29 ----
-   
-   #define DDC_ADDR	0x50
-   
- + #ifdef CONFIG_CKB_DVI_SUPPORT	
- + unsigned char *fb_do_probe_ddc_edid(struct i2c_adapter *adapter)
- + #else
-   static unsigned char *fb_do_probe_ddc_edid(struct i2c_adapter *adapter)
- + #endif
-   {
-   	unsigned char start = 0x0;
-   	unsigned char *buf = kmalloc(EDID_LENGTH, GFP_KERNEL);
- diff -crN linux-3.2.1_o/drivers/video/fbmem.c linux-3.2.1/drivers/video/fbmem.c
- *** linux-3.2.1_o/drivers/video/fbmem.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/video/fbmem.c	2014-05-15 13:25:15.122662428 +0900
- ***************
- *** 1913,1918 ****
- --- 1913,1920 ----
-   __setup("video=", video_setup);
-   #endif
-   
- + 
- + 
-       /*
-        *  Visible symbols for modules
-        */
- diff -crN linux-3.2.1_o/drivers/video/Kconfig linux-3.2.1/drivers/video/Kconfig
- *** linux-3.2.1_o/drivers/video/Kconfig	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/video/Kconfig	2014-05-15 13:25:15.126649862 +0900
- ***************
- *** 30,36 ****
-   config VIDEO_OUTPUT_CONTROL
-   	tristate "Lowlevel video output switch controls"
-   	help
- ! 	  This framework adds support for low-level control of the video 
-   	  output switch.
-   
-   menuconfig FB
- --- 30,36 ----
-   config VIDEO_OUTPUT_CONTROL
-   	tristate "Lowlevel video output switch controls"
-   	help
- ! 	  This framework adds support for low-level control of the video
-   	  output switch.
-   
-   menuconfig FB
- ***************
- *** 691,697 ****
-   	  BIOS routines contained in a ROM chip in HP PA-RISC based machines.
-   	  Enabling this option will implement the linux framebuffer device
-   	  using calls to the STI BIOS routines for initialisation.
- ! 	
-   	  If you enable this option, you will get a planar framebuffer device
-   	  /dev/fb which will work on the most common HP graphic cards of the
-   	  NGLE family, including the artist chips (in the 7xx and Bxxx series),
- --- 691,697 ----
-   	  BIOS routines contained in a ROM chip in HP PA-RISC based machines.
-   	  Enabling this option will implement the linux framebuffer device
-   	  using calls to the STI BIOS routines for initialisation.
- ! 
-   	  If you enable this option, you will get a planar framebuffer device
-   	  /dev/fb which will work on the most common HP graphic cards of the
-   	  NGLE family, including the artist chips (in the 7xx and Bxxx series),
- ***************
- *** 1132,1167 ****
-   	select FB_CFB_IMAGEBLIT
-   	select VGASTATE
-   	help
- ! 	  This driver supports the on-board graphics built in to the Intel 810 
-             and 815 chipsets.  Say Y if you have and plan to use such a board.
-   
-             To compile this driver as a module, choose M here: the
-   	  module will be called i810fb.
-   
- !           For more information, please read 
-   	  <file:Documentation/fb/intel810.txt>
-   
-   config FB_I810_GTF
-   	bool "use VESA Generalized Timing Formula"
-   	depends on FB_I810
-   	help
- ! 	  If you say Y, then the VESA standard, Generalized Timing Formula 
-             or GTF, will be used to calculate the required video timing values
- ! 	  per video mode.  Since the GTF allows nondiscrete timings 
-             (nondiscrete being a range of values as opposed to discrete being a
- !           set of values), you'll be able to use any combination of horizontal 
-   	  and vertical resolutions, and vertical refresh rates without having
-   	  to specify your own timing parameters.  This is especially useful
- ! 	  to maximize the performance of an aging display, or if you just 
- !           have a display with nonstandard dimensions. A VESA compliant 
-   	  monitor is recommended, but can still work with non-compliant ones.
- ! 	  If you need or want this, then select this option. The timings may 
- ! 	  not be compliant with Intel's recommended values. Use at your own 
-   	  risk.
-   
- !           If you say N, the driver will revert to discrete video timings 
-   	  using a set recommended by Intel in their documentation.
- !   
-             If unsure, say N.
-   
-   config FB_I810_I2C
- --- 1132,1167 ----
-   	select FB_CFB_IMAGEBLIT
-   	select VGASTATE
-   	help
- ! 	  This driver supports the on-board graphics built in to the Intel 810
-             and 815 chipsets.  Say Y if you have and plan to use such a board.
-   
-             To compile this driver as a module, choose M here: the
-   	  module will be called i810fb.
-   
- !           For more information, please read
-   	  <file:Documentation/fb/intel810.txt>
-   
-   config FB_I810_GTF
-   	bool "use VESA Generalized Timing Formula"
-   	depends on FB_I810
-   	help
- ! 	  If you say Y, then the VESA standard, Generalized Timing Formula
-             or GTF, will be used to calculate the required video timing values
- ! 	  per video mode.  Since the GTF allows nondiscrete timings
-             (nondiscrete being a range of values as opposed to discrete being a
- !           set of values), you'll be able to use any combination of horizontal
-   	  and vertical resolutions, and vertical refresh rates without having
-   	  to specify your own timing parameters.  This is especially useful
- ! 	  to maximize the performance of an aging display, or if you just
- !           have a display with nonstandard dimensions. A VESA compliant
-   	  monitor is recommended, but can still work with non-compliant ones.
- ! 	  If you need or want this, then select this option. The timings may
- ! 	  not be compliant with Intel's recommended values. Use at your own
-   	  risk.
-   
- !           If you say N, the driver will revert to discrete video timings
-   	  using a set recommended by Intel in their documentation.
- ! 
-             If unsure, say N.
-   
-   config FB_I810_I2C
- ***************
- *** 1279,1288 ****
-   	  G450/G550 secondary head and digital output are supported without
-   	  additional modules.
-   
- ! 	  The driver starts in monitor mode. You must use the matroxset tool 
- ! 	  (available at <ftp://platan.vc.cvut.cz/pub/linux/matrox-latest/>) to 
- ! 	  swap primary and secondary head outputs, or to change output mode.  
- ! 	  Secondary head driver always start in 640x480 resolution and you 
-   	  must use fbset to change it.
-   
-   	  Do not forget that second head supports only 16 and 32 bpp
- --- 1279,1288 ----
-   	  G450/G550 secondary head and digital output are supported without
-   	  additional modules.
-   
- ! 	  The driver starts in monitor mode. You must use the matroxset tool
- ! 	  (available at <ftp://platan.vc.cvut.cz/pub/linux/matrox-latest/>) to
- ! 	  swap primary and secondary head outputs, or to change output mode.
- ! 	  Secondary head driver always start in 640x480 resolution and you
-   	  must use fbset to change it.
-   
-   	  Do not forget that second head supports only 16 and 32 bpp
- ***************
- *** 1365,1371 ****
-   	select FB_DDC
-   	default y
-   	help
- ! 	  Say Y here if you want DDC/I2C support for your Radeon board. 
-   
-   config FB_RADEON_BACKLIGHT
-   	bool "Support for backlight control"
- --- 1365,1371 ----
-   	select FB_DDC
-   	default y
-   	help
- ! 	  Say Y here if you want DDC/I2C support for your Radeon board.
-   
-   config FB_RADEON_BACKLIGHT
-   	bool "Support for backlight control"
- ***************
- *** 1599,1605 ****
-   	select VGASTATE
-   	help
-   	  This driver supports notebooks with NeoMagic PCI chips.
- ! 	  Say Y if you have such a graphics card. 
-   
-   	  To compile this driver as a module, choose M here: the
-   	  module will be called neofb.
- --- 1599,1605 ----
-   	select VGASTATE
-   	help
-   	  This driver supports notebooks with NeoMagic PCI chips.
- ! 	  Say Y if you have such a graphics card.
-   
-   	  To compile this driver as a module, choose M here: the
-   	  module will be called neofb.
- ***************
- *** 1654,1660 ****
-   	select FB_CFB_COPYAREA
-   	select FB_CFB_IMAGEBLIT
-   	---help---
- ! 	  Say Y here if you have a 3Dfx Voodoo Graphics (Voodoo1/sst1) or 
-   	  Voodoo2 (cvg) based graphics card.
-   
-   	  To compile this driver as a module, choose M here: the
- --- 1654,1660 ----
-   	select FB_CFB_COPYAREA
-   	select FB_CFB_IMAGEBLIT
-   	---help---
- ! 	  Say Y here if you have a 3Dfx Voodoo Graphics (Voodoo1/sst1) or
-   	  Voodoo2 (cvg) based graphics card.
-   
-   	  To compile this driver as a module, choose M here: the
- ***************
- *** 2229,2235 ****
-   
-   config FB_DA8XX
-   	tristate "DA8xx/OMAP-L1xx Framebuffer support"
- ! 	depends on FB && ARCH_DAVINCI_DA8XX
-   	select FB_CFB_FILLRECT
-   	select FB_CFB_COPYAREA
-   	select FB_CFB_IMAGEBLIT
- --- 2229,2235 ----
-   
-   config FB_DA8XX
-   	tristate "DA8xx/OMAP-L1xx Framebuffer support"
- ! 	depends on FB && (ARCH_DAVINCI_DA8XX || SOC_OMAPAM33XX || ARCH_CKB)
-   	select FB_CFB_FILLRECT
-   	select FB_CFB_COPYAREA
-   	select FB_CFB_IMAGEBLIT
- diff -crN linux-3.2.1_o/drivers/video/Makefile linux-3.2.1/drivers/video/Makefile
- *** linux-3.2.1_o/drivers/video/Makefile	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/video/Makefile	2014-05-15 13:25:15.126649862 +0900
- ***************
- *** 13,19 ****
-   
-   obj-$(CONFIG_VT)		  += console/
-   obj-$(CONFIG_LOGO)		  += logo/
- ! obj-y				  += backlight/ display/
-   
-   obj-$(CONFIG_FB_CFB_FILLRECT)  += cfbfillrect.o
-   obj-$(CONFIG_FB_CFB_COPYAREA)  += cfbcopyarea.o
- --- 13,19 ----
-   
-   obj-$(CONFIG_VT)		  += console/
-   obj-$(CONFIG_LOGO)		  += logo/
- ! obj-y				  += backlight/ display/ ckb/
-   
-   obj-$(CONFIG_FB_CFB_FILLRECT)  += cfbfillrect.o
-   obj-$(CONFIG_FB_CFB_COPYAREA)  += cfbcopyarea.o
- ***************
- *** 136,141 ****
- --- 136,142 ----
-   obj-$(CONFIG_FB_SH_MOBILE_LCDC)	  += sh_mobile_lcdcfb.o
-   obj-$(CONFIG_FB_OMAP)             += omap/
-   obj-y                             += omap2/
- + obj-$(CONFIG_CKB_TFP410)          += ckb/
-   obj-$(CONFIG_XEN_FBDEV_FRONTEND)  += xen-fbfront.o
-   obj-$(CONFIG_FB_CARMINE)          += carminefb.o
-   obj-$(CONFIG_FB_MB862XX)	  += mb862xx/
- ***************
- *** 158,163 ****
- --- 159,165 ----
-   obj-$(CONFIG_FB_MX3)		  += mx3fb.o
-   obj-$(CONFIG_FB_DA8XX)		  += da8xx-fb.o
-   obj-$(CONFIG_FB_MXS)		  += mxsfb.o
- + obj-$(CONFIG_CKB_3352_HDMI)	  += ckb/
-   
-   # the test framebuffer is last
-   obj-$(CONFIG_FB_VIRTUAL)          += vfb.o
- diff -crN linux-3.2.1_o/drivers/video/offb.c linux-3.2.1/drivers/video/offb.c
- *** linux-3.2.1_o/drivers/video/offb.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/video/offb.c	2014-05-15 13:25:15.126649862 +0900
- ***************
- *** 100,131 ****
-   			  u_int transp, struct fb_info *info)
-   {
-   	struct offb_par *par = (struct offb_par *) info->par;
-   
- ! 	if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
- ! 		u32 *pal = info->pseudo_palette;
- ! 		u32 cr = red >> (16 - info->var.red.length);
- ! 		u32 cg = green >> (16 - info->var.green.length);
- ! 		u32 cb = blue >> (16 - info->var.blue.length);
- ! 		u32 value;
- ! 
- ! 		if (regno >= 16)
- ! 			return -EINVAL;
- ! 
- ! 		value = (cr << info->var.red.offset) |
- ! 			(cg << info->var.green.offset) |
- ! 			(cb << info->var.blue.offset);
- ! 		if (info->var.transp.length > 0) {
- ! 			u32 mask = (1 << info->var.transp.length) - 1;
- ! 			mask <<= info->var.transp.offset;
- ! 			value |= mask;
-   		}
- - 		pal[regno] = value;
- - 		return 0;
-   	}
-   
- - 	if (regno > 255)
- - 		return -EINVAL;
- - 
-   	red >>= 8;
-   	green >>= 8;
-   	blue >>= 8;
- --- 100,135 ----
-   			  u_int transp, struct fb_info *info)
-   {
-   	struct offb_par *par = (struct offb_par *) info->par;
- + 	int i, depth;
- + 	u32 *pal = info->pseudo_palette;
-   
- ! 	depth = info->var.bits_per_pixel;
- ! 	if (depth == 16)
- ! 		depth = (info->var.green.length == 5) ? 15 : 16;
- ! 
- ! 	if (regno > 255 ||
- ! 	    (depth == 16 && regno > 63) ||
- ! 	    (depth == 15 && regno > 31))
- ! 		return 1;
- ! 
- ! 	if (regno < 16) {
- ! 		switch (depth) {
- ! 		case 15:
- ! 			pal[regno] = (regno << 10) | (regno << 5) | regno;
- ! 			break;
- ! 		case 16:
- ! 			pal[regno] = (regno << 11) | (regno << 5) | regno;
- ! 			break;
- ! 		case 24:
- ! 			pal[regno] = (regno << 16) | (regno << 8) | regno;
- ! 			break;
- ! 		case 32:
- ! 			i = (regno << 8) | regno;
- ! 			pal[regno] = (i << 16) | i;
- ! 			break;
-   		}
-   	}
-   
-   	red >>= 8;
-   	green >>= 8;
-   	blue >>= 8;
- ***************
- *** 377,383 ****
-   				int pitch, unsigned long address,
-   				int foreign_endian, struct device_node *dp)
-   {
- ! 	unsigned long res_size = pitch * height;
-   	struct offb_par *par = &default_par;
-   	unsigned long res_start = address;
-   	struct fb_fix_screeninfo *fix;
- --- 381,387 ----
-   				int pitch, unsigned long address,
-   				int foreign_endian, struct device_node *dp)
-   {
- ! 	unsigned long res_size = pitch * height * (depth + 7) / 8;
-   	struct offb_par *par = &default_par;
-   	unsigned long res_start = address;
-   	struct fb_fix_screeninfo *fix;
- diff -crN linux-3.2.1_o/drivers/watchdog/omap_wdt.c linux-3.2.1/drivers/watchdog/omap_wdt.c
- *** linux-3.2.1_o/drivers/watchdog/omap_wdt.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/drivers/watchdog/omap_wdt.c	2014-05-15 13:25:15.126649862 +0900
- ***************
- *** 124,131 ****
-   	u32 pre_margin = GET_WLDR_VAL(timer_margin);
-   	void __iomem *base = wdev->base;
-   
- - 	pm_runtime_get_sync(wdev->dev);
- - 
-   	/* just count up at 32 KHz */
-   	while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
-   		cpu_relax();
- --- 124,129 ----
- ***************
- *** 133,140 ****
-   	__raw_writel(pre_margin, base + OMAP_WATCHDOG_LDR);
-   	while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
-   		cpu_relax();
- - 
- - 	pm_runtime_put_sync(wdev->dev);
-   }
-   
-   /*
- --- 131,136 ----
- ***************
- *** 164,171 ****
-   	omap_wdt_ping(wdev); /* trigger loading of new timeout value */
-   	omap_wdt_enable(wdev);
-   
- - 	pm_runtime_put_sync(wdev->dev);
- - 
-   	return nonseekable_open(inode, file);
-   }
-   
- --- 160,165 ----
- ***************
- *** 177,184 ****
-   	 *      Shut off the timer unless NOWAYOUT is defined.
-   	 */
-   #ifndef CONFIG_WATCHDOG_NOWAYOUT
- - 	pm_runtime_get_sync(wdev->dev);
- - 
-   	omap_wdt_disable(wdev);
-   
-   	pm_runtime_put_sync(wdev->dev);
- --- 171,176 ----
- ***************
- *** 197,207 ****
-   
-   	/* Refresh LOAD_TIME. */
-   	if (len) {
- - 		pm_runtime_get_sync(wdev->dev);
-   		spin_lock(&wdt_lock);
-   		omap_wdt_ping(wdev);
-   		spin_unlock(&wdt_lock);
- - 		pm_runtime_put_sync(wdev->dev);
-   	}
-   	return len;
-   }
- --- 189,197 ----
- ***************
- *** 233,250 ****
-   			return put_user(omap_prcm_get_reset_sources(),
-   					(int __user *)arg);
-   	case WDIOC_KEEPALIVE:
- - 		pm_runtime_get_sync(wdev->dev);
-   		spin_lock(&wdt_lock);
-   		omap_wdt_ping(wdev);
-   		spin_unlock(&wdt_lock);
- - 		pm_runtime_put_sync(wdev->dev);
-   		return 0;
-   	case WDIOC_SETTIMEOUT:
-   		if (get_user(new_margin, (int __user *)arg))
-   			return -EFAULT;
-   		omap_wdt_adjust_timeout(new_margin);
-   
- - 		pm_runtime_get_sync(wdev->dev);
-   		spin_lock(&wdt_lock);
-   		omap_wdt_disable(wdev);
-   		omap_wdt_set_timeout(wdev);
- --- 223,237 ----
- ***************
- *** 252,258 ****
-   
-   		omap_wdt_ping(wdev);
-   		spin_unlock(&wdt_lock);
- - 		pm_runtime_put_sync(wdev->dev);
-   		/* Fall */
-   	case WDIOC_GETTIMEOUT:
-   		return put_user(timer_margin, (int __user *)arg);
- --- 239,244 ----
- ***************
- *** 359,365 ****
-   	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
-   
-   	if (wdev->omap_wdt_users) {
- - 		pm_runtime_get_sync(wdev->dev);
-   		omap_wdt_disable(wdev);
-   		pm_runtime_put_sync(wdev->dev);
-   	}
- --- 345,350 ----
- ***************
- *** 398,404 ****
-   	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
-   
-   	if (wdev->omap_wdt_users) {
- - 		pm_runtime_get_sync(wdev->dev);
-   		omap_wdt_disable(wdev);
-   		pm_runtime_put_sync(wdev->dev);
-   	}
- --- 383,388 ----
- ***************
- *** 414,420 ****
-   		pm_runtime_get_sync(wdev->dev);
-   		omap_wdt_enable(wdev);
-   		omap_wdt_ping(wdev);
- - 		pm_runtime_put_sync(wdev->dev);
-   	}
-   
-   	return 0;
- --- 398,403 ----
- diff -crN linux-3.2.1_o/include/linux/can/platform/d_can.h linux-3.2.1/include/linux/can/platform/d_can.h
- *** linux-3.2.1_o/include/linux/can/platform/d_can.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/include/linux/can/platform/d_can.h	2014-05-15 13:25:15.143269777 +0900
- ***************
- *** 0 ****
- --- 1,40 ----
- + /*
- +  * D_CAN controller driver platform header
- +  *
- +  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- +  *
- +  * Bosch D_CAN controller is compliant to CAN protocol version 2.0 part A and B.
- +  * Bosch D_CAN user manual can be obtained from:
- +  * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/can/
- +  * d_can_users_manual_111.pdf
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #ifndef __CAN_PLATFORM_TI_D_CAN_H__
- + #define __CAN_PLATFORM_TI_D_CAN_H__
- + 
- + /**
- +  * struct d_can_platform_data - DCAN Platform Data
- +  *
- +  * @num_of_msg_objs:	Number of message objects
- +  * @dma_support:	DMA support is required/not
- +  * @ram_init:		DCAN RAM initialization
- +  *
- +  * Platform data structure to get all platform specific settings.
- +  * this structure also accounts the fact that the IP may have different
- +  * RAM and mailbox offsets for different SOC's
- +  */
- + struct d_can_platform_data {
- + 	u32 num_of_msg_objs;
- + 	bool dma_support;
- + 	void (*ram_init) (unsigned int, unsigned int);
- + };
- + #endif
- diff -crN linux-3.2.1_o/include/linux/cpsw.h linux-3.2.1/include/linux/cpsw.h
- *** linux-3.2.1_o/include/linux/cpsw.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/include/linux/cpsw.h	2014-05-15 13:25:15.143269777 +0900
- ***************
- *** 0 ****
- --- 1,63 ----
- + #ifndef __CPSW_H__
- + #define __CPSW_H__
- + 
- + #include <linux/if_ether.h>
- + 
- + enum {
- + 	CPSW_VERSION_1 = 0,    /* TI8148 */
- + 	CPSW_VERSION_2,        /* AM33XX */
- + };
- + 
- + struct cpsw_slave_data {
- + 	u32		slave_reg_ofs;
- + 	u32		sliver_reg_ofs;
- + 	const char	*phy_id;
- + 	int		phy_if;
- + 	u8		mac_addr[ETH_ALEN];
- + 	u32		dual_emac_reserved_vlan;
- + };
- + 
- + struct cpsw_platform_data {
- + 	u32	ss_reg_ofs;	/* Subsystem control register offset */
- + 	int	channels;	/* number of cpdma channels (symmetric) */
- + 	u32	cpdma_reg_ofs;	/* cpdma register offset */
- + 
- + 	int	slaves;		/* number of slave cpgmac ports */
- + 	struct cpsw_slave_data	*slave_data;
- + 	int	ethtool_slave;	/* Holds which slave attaches to ethtool */
- + 
- + 	u32	ale_reg_ofs;	/* address lookup engine reg offset */
- + 	int	ale_entries;	/* ale table size */
- + 
- + 	u32	host_port_reg_ofs; /* cpsw cpdma host port registers */
- + 
- + 	u32	hw_stats_reg_ofs;  /* cpsw hardware statistics counters */
- + 
- + 	u32	bd_ram_ofs;   /* embedded buffer descriptor RAM offset*/
- + 	u32	bd_ram_size;  /*buffer descriptor ram size */
- + 	u32	hw_ram_addr; /*if the HW address for BD RAM is different */
- + 
- + 	u32	cpts_reg_ofs;		/* cpts registers */
- + 	u32	cpts_active_slave;	/* time stamping slave */
- + 	u32	cpts_clock_mult; /* convert input clock ticks to nanoseconds */
- + 	u32	cpts_clock_shift; /* convert input clock ticks to nanoseconds */
- + 
- + 	u8	mac_addr[ETH_ALEN];
- + 
- + 	int	rx_descs;
- + 
- + 	void	(*phy_control)(bool enabled);
- + 
- + 	u32	mac_control;
- + 
- + 	u32	gigabit_en; /* Is gigabit capable AND enabled */
- + 	u32	rmii_en; /* Is RMII mode capable AND enabled */
- + 	u32	host_port_num; /* The port number for the host port */
- + 
- + 	bool	no_bd_ram; /* no embedded BD ram*/
- + 	u8	version;
- + 	u32	default_vlan; /* Default VLAN for Untagged packet handling*/
- + 	void (*save_mac_addr) (char *);		/* function for saving MAC address */
- + };
- + 
- + #endif /* __CPSW_H__ */
- diff -crN linux-3.2.1_o/include/linux/i2c/at24.h linux-3.2.1/include/linux/i2c/at24.h
- *** linux-3.2.1_o/include/linux/i2c/at24.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/include/linux/i2c/at24.h	2014-05-15 13:25:15.163265087 +0900
- ***************
- *** 27,32 ****
- --- 27,35 ----
-   
-   	void		(*setup)(struct memory_accessor *, void *context);
-   	void		*context;
- + #ifdef CONFIG_MACH_CKB_3352
- + 	void		(*unload)(void);
- + #endif
-   };
-   
-   #endif /* _LINUX_AT24_H */
- diff -crN linux-3.2.1_o/include/linux/i2c-omap.h linux-3.2.1/include/linux/i2c-omap.h
- *** linux-3.2.1_o/include/linux/i2c-omap.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/include/linux/i2c-omap.h	2014-05-15 13:25:15.179279002 +0900
- ***************
- *** 35,40 ****
- --- 35,41 ----
-   	u32		rev;
-   	u32		flags;
-   	void		(*set_mpu_wkup_lat)(struct device *dev, long set);
- + 	int		(*device_reset) (struct device *dev);
-   };
-   
-   #endif
- diff -crN linux-3.2.1_o/include/linux/input/ti_tsc.h linux-3.2.1/include/linux/input/ti_tsc.h
- *** linux-3.2.1_o/include/linux/input/ti_tsc.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/include/linux/input/ti_tsc.h	2014-05-15 13:25:15.183327289 +0900
- ***************
- *** 0 ****
- --- 1,18 ----
- + /**
- +  * struct tsc_data	Touchscreen wire configuration
- +  * @wires:		Wires refer to application modes
- +  *			i.e. 4/5/8 wire touchscreen support
- +  *			on the platform
- +  * @x_plate_resistance:	X plate resistance.
- +  * @steps_to_configure: The sequencer supports a total of
- +  *			16 programmable steps.
- +  *			A step configured to read a single
- +  *			co-ordinate value, can be applied
- +  *			more number of times for better results.
- +  */
- + 
- + struct tsc_data {
- + 	int wires;
- + 	int x_plate_resistance;
- + 	int steps_to_configure;
- + };
- diff -crN linux-3.2.1_o/include/linux/Kbuild linux-3.2.1/include/linux/Kbuild
- *** linux-3.2.1_o/include/linux/Kbuild	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/include/linux/Kbuild	2014-05-15 13:25:15.219049687 +0900
- ***************
- *** 258,263 ****
- --- 258,264 ----
-   header-y += net.h
-   header-y += net_dropmon.h
-   header-y += net_tstamp.h
- + header-y += net_switch_config.h
-   header-y += netdevice.h
-   header-y += netfilter.h
-   header-y += netfilter_arp.h
- diff -crN linux-3.2.1_o/include/linux/mfd/ti_tscadc.h linux-3.2.1/include/linux/mfd/ti_tscadc.h
- *** linux-3.2.1_o/include/linux/mfd/ti_tscadc.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/include/linux/mfd/ti_tscadc.h	2014-05-15 13:25:15.223261875 +0900
- ***************
- *** 0 ****
- --- 1,167 ----
- + /*
- +  * TI Touch Screen / ADC MFD driver
- +  *
- +  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #include <linux/mfd/core.h>
- + 
- + #define TSCADC_REG_RAWIRQSTATUS		0x024
- + #define TSCADC_REG_IRQSTATUS		0x028
- + #define TSCADC_REG_IRQENABLE		0x02C
- + #define TSCADC_REG_IRQCLR		0x030
- + #define TSCADC_REG_IRQWAKEUP		0x034
- + #define TSCADC_REG_CTRL			0x040
- + #define TSCADC_REG_ADCFSM		0x044
- + #define TSCADC_REG_CLKDIV		0x04C
- + #define TSCADC_REG_SE			0x054
- + #define TSCADC_REG_IDLECONFIG		0x058
- + #define TSCADC_REG_CHARGECONFIG		0x05C
- + #define TSCADC_REG_CHARGEDELAY		0x060
- + #define TSCADC_REG_STEPCONFIG(n)	(0x64 + ((n - 1) * 8))
- + #define TSCADC_REG_STEPDELAY(n)		(0x68 + ((n - 1) * 8))
- + #define TSCADC_REG_FIFO0CNT		0xE4
- + #define TSCADC_REG_FIFO0THR		0xE8
- + #define TSCADC_REG_FIFO1CNT		0xF0
- + #define TSCADC_REG_FIFO1THR		0xF4
- + #define TSCADC_REG_FIFO0		0x100
- + #define TSCADC_REG_FIFO1		0x200
- + 
- + /*	Register Bitfields	*/
- + /* IRQ wakeup enable */
- + #define TSCADC_IRQWKUP_ENB		BIT(0)
- + 
- + /* Step Enable */
- + #define TSCADC_STEPENB_MASK		(0x1FFFF << 0)
- + #define TSCADC_STEPENB(val)		((val) << 0)
- + #define TSCADC_STPENB_STEPENB		TSCADC_STEPENB(0x1FFFF)
- + #define TSCADC_STPENB_STEPENB_TC	TSCADC_STEPENB(0x1FFF)
- + #define TSCADC_ENB(val)			(1 << (val))
- + 
- + /* IRQ enable */
- + #define TSCADC_IRQENB_HW_PEN		BIT(0)
- + #define TSCADC_IRQENB_FIFO0THRES	BIT(2)
- + #define TSCADC_IRQENB_FIFO0OVRRUN	BIT(3)
- + #define TSCADC_IRQENB_FIFO0UNDRFLW	BIT(4)
- + #define TSCADC_IRQENB_FIFO1THRES	BIT(5)
- + #define TSCADC_IRQENB_FIFO1OVRRUN       BIT(6)
- + #define TSCADC_IRQENB_FIFO1UNDRFLW      BIT(7)
- + #define TSCADC_IRQENB_PENUP		BIT(9)
- + 
- + /* Step Configuration */
- + #define TSCADC_STEPCONFIG_MODE_MASK	(3 << 0)
- + #define TSCADC_STEPCONFIG_MODE(val)	((val) << 0)
- + #define TSCADC_STEPCONFIG_MODE_HWSYNC	TSCADC_STEPCONFIG_MODE(2)
- + #define TSCADC_STEPCONFIG_MODE_SWCNT	TSCADC_STEPCONFIG_MODE(1)
- + #define TSCADC_STEPCONFIG_AVG_MASK	(7 << 2)
- + #define TSCADC_STEPCONFIG_AVG(val)	((val) << 2)
- + #define TSCADC_STEPCONFIG_AVG_16	TSCADC_STEPCONFIG_AVG(4)
- + #define TSCADC_STEPCONFIG_XPP		BIT(5)
- + #define TSCADC_STEPCONFIG_XNN		BIT(6)
- + #define TSCADC_STEPCONFIG_YPP		BIT(7)
- + #define TSCADC_STEPCONFIG_YNN		BIT(8)
- + #define TSCADC_STEPCONFIG_XNP		BIT(9)
- + #define TSCADC_STEPCONFIG_YPN		BIT(10)
- + #define TSCADC_STEPCONFIG_INM_MASK	(0xF << 15)
- + #define TSCADC_STEPCONFIG_INM(val)	((val) << 15)
- + #define TSCADC_STEPCONFIG_INM_ADCREFM	TSCADC_STEPCONFIG_INM(8)
- + #define TSCADC_STEPCONFIG_INP_MASK	(0xF << 19)
- + #define TSCADC_STEPCONFIG_INP(val)	((val) << 19)
- + #define TSCADC_STEPCONFIG_INP_AN2	TSCADC_STEPCONFIG_INP(2)
- + #define TSCADC_STEPCONFIG_INP_AN3	TSCADC_STEPCONFIG_INP(3)
- + #define TSCADC_STEPCONFIG_INP_AN4	TSCADC_STEPCONFIG_INP(4)
- + #define TSCADC_STEPCONFIG_INP_ADCREFM	TSCADC_STEPCONFIG_INP(8)
- + #define TSCADC_STEPCONFIG_FIFO1		BIT(26)
- + 
- + /* Delay register */
- + #define TSCADC_STEPDELAY_OPEN_MASK	(0x3FFFF << 0)
- + #define TSCADC_STEPDELAY_OPEN(val)	((val) << 0)
- + #define TSCADC_STEPCONFIG_OPENDLY	TSCADC_STEPDELAY_OPEN(0x098)
- + #define TSCADC_STEPDELAY_SAMPLE_MASK	(0xFF << 24)
- + #define TSCADC_STEPDELAY_SAMPLE(val)	((val) << 24)
- + #define TSCADC_STEPCONFIG_SAMPLEDLY	TSCADC_STEPDELAY_SAMPLE(0)
- + 
- + /* Charge Config */
- + #define TSCADC_STEPCHARGE_RFP_MASK	(7 << 12)
- + #define TSCADC_STEPCHARGE_RFP(val)	((val) << 12)
- + #define TSCADC_STEPCHARGE_RFP_XPUL	TSCADC_STEPCHARGE_RFP(1)
- + #define TSCADC_STEPCHARGE_INM_MASK	(0xF << 15)
- + #define TSCADC_STEPCHARGE_INM(val)	((val) << 15)
- + #define TSCADC_STEPCHARGE_INM_AN1	TSCADC_STEPCHARGE_INM(1)
- + #define TSCADC_STEPCHARGE_INP_MASK	(0xF << 19)
- + #define TSCADC_STEPCHARGE_INP(val)	((val) << 19)
- + #define TSCADC_STEPCHARGE_INP_AN1	TSCADC_STEPCHARGE_INP(1)
- + #define TSCADC_STEPCHARGE_RFM_MASK	(3 << 23)
- + #define TSCADC_STEPCHARGE_RFM(val)	((val) << 23)
- + #define TSCADC_STEPCHARGE_RFM_XNUR	TSCADC_STEPCHARGE_RFM(1)
- + 
- + /* Charge delay */
- + #define TSCADC_CHARGEDLY_OPEN_MASK	(0x3FFFF << 0)
- + #define TSCADC_CHARGEDLY_OPEN(val)	((val) << 0)
- + #define TSCADC_CHARGEDLY_OPENDLY	TSCADC_CHARGEDLY_OPEN(1)
- + 
- + /* Control register */
- + #define TSCADC_CNTRLREG_TSCSSENB	BIT(0)
- + #define TSCADC_CNTRLREG_STEPID		BIT(1)
- + #define TSCADC_CNTRLREG_STEPCONFIGWRT	BIT(2)
- + #define TSCADC_CNTRLREG_POWERDOWN	BIT(4)
- + #define TSCADC_CNTRLREG_AFE_CTRL_MASK	(3 << 5)
- + #define TSCADC_CNTRLREG_AFE_CTRL(val)	((val) << 5)
- + #define TSCADC_CNTRLREG_4WIRE		TSCADC_CNTRLREG_AFE_CTRL(1)
- + #define TSCADC_CNTRLREG_5WIRE		TSCADC_CNTRLREG_AFE_CTRL(2)
- + #define TSCADC_CNTRLREG_8WIRE		TSCADC_CNTRLREG_AFE_CTRL(3)
- + #define TSCADC_CNTRLREG_TSCENB		BIT(7)
- + 
- + /* FIFO READ Register */
- + #define TSCADC_FIFOREAD_DATA_MASK	(0xfff << 0)
- + #define TSCADC_FIFOREAD_CHNLID_MASK	(0xf << 16)
- + 
- + /* Sequencer Status */
- + #define TSCADC_SEQ_STATUS		BIT(5)
- + 
- + #define ADC_CLK				3000000
- + #define TOTAL_STEPS			16
- + #define TOTAL_CHANNELS			8
- + #define FIFO1_THRESHOLD			19
- + 
- + /*
- +  * ADC runs at 3MHz, and it takes
- +  * 15 cycles to latch one data output.
- +  * Hence the idle time for ADC to
- +  * process one sample data would be
- +  * around 5 micro seconds.
- +  */
- + #define IDLE_TIMEOUT			5 /* microsec */
- + 
- + #define TSCADC_CELLS			2
- + 
- + struct mfd_tscadc_board {
- + 	struct tsc_data *tsc_init;
- + 	struct adc_data *adc_init;
- + };
- + 
- + struct ti_tscadc_dev {
- + 	struct device *dev;
- + 	void __iomem *tscadc_base;
- + 	int irq;
- + 	struct mfd_cell cells[TSCADC_CELLS];
- + 
- + 	/* tsc device */
- + 	struct tscadc *tsc;
- + 
- + 	/* adc device */
- + 	struct adc_device *adc;
- + 
- + 	/* Context save */
- + 	unsigned int irqstat;
- + 	unsigned int ctrl;
- + };
- diff -crN linux-3.2.1_o/include/linux/mfd/tps65217.h linux-3.2.1/include/linux/mfd/tps65217.h
- *** linux-3.2.1_o/include/linux/mfd/tps65217.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/include/linux/mfd/tps65217.h	2014-05-15 13:25:15.223261875 +0900
- ***************
- *** 0 ****
- --- 1,291 ----
- + /*
- +  * linux/mfd/tps65217.h
- +  *
- +  * Functions to access TPS65217 power management chip.
- +  *
- +  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #ifndef __LINUX_MFD_TPS65217_H
- + #define __LINUX_MFD_TPS65217_H
- + 
- + #include <linux/i2c.h>
- + #include <linux/regulator/driver.h>
- + #include <linux/regulator/machine.h>
- + 
- + /* I2C ID for TPS65217 part */
- + #define TPS65217_I2C_ID			0x24
- + 
- + /* All register addresses */
- + #define TPS65217_REG_CHIPID		0X00
- + #define TPS65217_REG_PPATH		0X01
- + #define TPS65217_REG_INT		0X02
- + #define TPS65217_REG_CHGCONFIG0		0X03
- + #define TPS65217_REG_CHGCONFIG1		0X04
- + #define TPS65217_REG_CHGCONFIG2		0X05
- + #define TPS65217_REG_CHGCONFIG3		0X06
- + #define TPS65217_REG_WLEDCTRL1		0X07
- + #define TPS65217_REG_WLEDCTRL2		0X08
- + #define TPS65217_REG_MUXCTRL		0X09
- + #define TPS65217_REG_STATUS		0X0A
- + #define TPS65217_REG_PASSWORD		0X0B
- + #define TPS65217_REG_PGOOD		0X0C
- + #define TPS65217_REG_DEFPG		0X0D
- + #define TPS65217_REG_DEFDCDC1		0X0E
- + #define TPS65217_REG_DEFDCDC2		0X0F
- + #define TPS65217_REG_DEFDCDC3		0X10
- + #define TPS65217_REG_DEFSLEW		0X11
- + #define TPS65217_REG_DEFLDO1		0X12
- + #define TPS65217_REG_DEFLDO2		0X13
- + #define TPS65217_REG_DEFLS1		0X14
- + #define TPS65217_REG_DEFLS2		0X15
- + #define TPS65217_REG_ENABLE		0X16
- + #define TPS65217_REG_DEFUVLO		0X18
- + #define TPS65217_REG_SEQ1		0X19
- + #define TPS65217_REG_SEQ2		0X1A
- + #define TPS65217_REG_SEQ3		0X1B
- + #define TPS65217_REG_SEQ4		0X1C
- + #define TPS65217_REG_SEQ5		0X1D
- + #define TPS65217_REG_SEQ6		0X1E
- + 
- + /* Register field definitions */
- + #define TPS65217_CHIPID_CHIP_MASK	0xF0
- + #define TPS65217_CHIPID_REV_MASK	0x0F
- + 
- + #define TPS65217_PPATH_ACSINK_ENABLE	BIT(7)
- + #define TPS65217_PPATH_USBSINK_ENABLE	BIT(6)
- + #define TPS65217_PPATH_AC_PW_ENABLE	BIT(5)
- + #define TPS65217_PPATH_USB_PW_ENABLE	BIT(4)
- + #define TPS65217_PPATH_AC_CURRENT_MASK	0x0C
- + #define TPS65217_PPATH_USB_CURRENT_MASK	0x03
- + 
- + #define TPS65217_INT_PBM		BIT(6)
- + #define TPS65217_INT_ACM		BIT(5)
- + #define TPS65217_INT_USBM		BIT(4)
- + #define TPS65217_INT_PBI		BIT(2)
- + #define TPS65217_INT_ACI		BIT(1)
- + #define TPS65217_INT_USBI		BIT(0)
- + 
- + #define TPS65217_CHGCONFIG0_TREG	BIT(7)
- + #define TPS65217_CHGCONFIG0_DPPM	BIT(6)
- + #define TPS65217_CHGCONFIG0_TSUSP	BIT(5)
- + #define TPS65217_CHGCONFIG0_TERMI	BIT(4)
- + #define TPS65217_CHGCONFIG0_ACTIVE	BIT(3)
- + #define TPS65217_CHGCONFIG0_CHGTOUT	BIT(2)
- + #define TPS65217_CHGCONFIG0_PCHGTOUT	BIT(1)
- + #define TPS65217_CHGCONFIG0_BATTEMP	BIT(0)
- + 
- + #define TPS65217_CHGCONFIG1_TMR_MASK	0xC0
- + #define TPS65217_CHGCONFIG1_TMR_ENABLE	BIT(5)
- + #define TPS65217_CHGCONFIG1_NTC_TYPE	BIT(4)
- + #define TPS65217_CHGCONFIG1_RESET	BIT(3)
- + #define TPS65217_CHGCONFIG1_TERM	BIT(2)
- + #define TPS65217_CHGCONFIG1_SUSP	BIT(1)
- + #define TPS65217_CHGCONFIG1_CHG_EN	BIT(0)
- + 
- + #define TPS65217_CHGCONFIG2_DYNTMR	BIT(7)
- + #define TPS65217_CHGCONFIG2_VPREGHG	BIT(6)
- + #define TPS65217_CHGCONFIG2_VOREG_MASK	0x30
- + 
- + #define TPS65217_CHGCONFIG3_ICHRG_MASK	0xC0
- + #define TPS65217_CHGCONFIG3_DPPMTH_MASK	0x30
- + #define TPS65217_CHGCONFIG2_PCHRGT	BIT(3)
- + #define TPS65217_CHGCONFIG2_TERMIF	0x06
- + #define TPS65217_CHGCONFIG2_TRANGE	BIT(0)
- + 
- + #define TPS65217_WLEDCTRL1_ISINK_ENABLE	BIT(3)
- + #define TPS65217_WLEDCTRL1_ISEL		BIT(2)
- + #define TPS65217_WLEDCTRL1_FDIM_MASK	0x03
- + 
- + #define TPS65217_WLEDCTRL2_DUTY_MASK	0x7F
- + 
- + #define TPS65217_MUXCTRL_MUX_MASK	0x07
- + 
- + #define TPS65217_STATUS_OFF		BIT(7)
- + #define TPS65217_STATUS_ACPWR		BIT(3)
- + #define TPS65217_STATUS_USBPWR		BIT(2)
- + #define TPS65217_STATUS_PB		BIT(0)
- + 
- + #define TPS65217_PASSWORD_REGS_UNLOCK	0x7D
- + 
- + #define TPS65217_PGOOD_LDO3_PG		BIT(6)
- + #define TPS65217_PGOOD_LDO4_PG		BIT(5)
- + #define TPS65217_PGOOD_DC1_PG		BIT(4)
- + #define TPS65217_PGOOD_DC2_PG		BIT(3)
- + #define TPS65217_PGOOD_DC3_PG		BIT(2)
- + #define TPS65217_PGOOD_LDO1_PG		BIT(1)
- + #define TPS65217_PGOOD_LDO2_PG		BIT(0)
- + 
- + #define TPS65217_DEFPG_LDO1PGM		BIT(3)
- + #define TPS65217_DEFPG_LDO2PGM		BIT(2)
- + #define TPS65217_DEFPG_PGDLY_MASK	0x03
- + 
- + #define TPS65217_DEFDCDCX_XADJX		BIT(7)
- + #define TPS65217_DEFDCDCX_DCDC_MASK	0x3F
- + 
- + #define TPS65217_DEFSLEW_GO		BIT(7)
- + #define TPS65217_DEFSLEW_GODSBL		BIT(6)
- + #define TPS65217_DEFSLEW_PFM_EN1	BIT(5)
- + #define TPS65217_DEFSLEW_PFM_EN2	BIT(4)
- + #define TPS65217_DEFSLEW_PFM_EN3	BIT(3)
- + #define TPS65217_DEFSLEW_SLEW_MASK	0x07
- + 
- + #define TPS65217_DEFLDO1_LDO1_MASK	0x0F
- + 
- + #define TPS65217_DEFLDO2_TRACK		BIT(6)
- + #define TPS65217_DEFLDO2_LDO2_MASK	0x3F
- + 
- + #define TPS65217_DEFLDO3_LDO3_EN	BIT(5)
- + #define TPS65217_DEFLDO3_LDO3_MASK	0x1F
- + 
- + #define TPS65217_DEFLDO4_LDO4_EN	BIT(5)
- + #define TPS65217_DEFLDO4_LDO4_MASK	0x1F
- + 
- + #define TPS65217_ENABLE_LS1_EN		BIT(6)
- + #define TPS65217_ENABLE_LS2_EN		BIT(5)
- + #define TPS65217_ENABLE_DC1_EN		BIT(4)
- + #define TPS65217_ENABLE_DC2_EN		BIT(3)
- + #define TPS65217_ENABLE_DC3_EN		BIT(2)
- + #define TPS65217_ENABLE_LDO1_EN		BIT(1)
- + #define TPS65217_ENABLE_LDO2_EN		BIT(0)
- + 
- + #define TPS65217_DEFUVLO_UVLOHYS	BIT(2)
- + #define TPS65217_DEFUVLO_UVLO_MASK	0x03
- + 
- + #define TPS65217_SEQ1_DC1_SEQ_MASK	0xF0
- + #define TPS65217_SEQ1_DC2_SEQ_MASK	0x0F
- + 
- + #define TPS65217_SEQ2_DC3_SEQ_MASK	0xF0
- + #define TPS65217_SEQ2_LDO1_SEQ_MASK	0x0F
- + 
- + #define TPS65217_SEQ3_LDO2_SEQ_MASK	0xF0
- + #define TPS65217_SEQ3_LDO3_SEQ_MASK	0x0F
- + 
- + #define TPS65217_SEQ4_LDO4_SEQ_MASK	0xF0
- + 
- + #define TPS65217_SEQ5_DLY1_MASK		0xC0
- + #define TPS65217_SEQ5_DLY2_MASK		0x30
- + #define TPS65217_SEQ5_DLY3_MASK		0x0C
- + #define TPS65217_SEQ5_DLY4_MASK		0x03
- + 
- + #define TPS65217_SEQ6_DLY5_MASK		0xC0
- + #define TPS65217_SEQ6_DLY6_MASK		0x30
- + #define TPS65217_SEQ6_SEQUP		BIT(2)
- + #define TPS65217_SEQ6_SEQDWN		BIT(1)
- + #define TPS65217_SEQ6_INSTDWN		BIT(0)
- + 
- + #define TPS65217_MAX_REGISTER		0x1E
- + #define TPS65217_PROTECT_NONE		0
- + #define TPS65217_PROTECT_L1		1
- + #define TPS65217_PROTECT_L2		2
- + 
- + 
- + enum tps65217_regulator_id {
- + 	/* DCDC's */
- + 	TPS65217_DCDC_1,
- + 	TPS65217_DCDC_2,
- + 	TPS65217_DCDC_3,
- + 	/* LDOs */
- + 	TPS65217_LDO_1,
- + 	TPS65217_LDO_2,
- + 	TPS65217_LDO_3,
- + 	TPS65217_LDO_4,
- + };
- + 
- + #define TPS65217_MAX_REG_ID		TPS65217_LDO_4
- + 
- + /* Number of step-down converters available */
- + #define TPS65217_NUM_DCDC		3
- + /* Number of LDO voltage regulators available */
- + #define TPS65217_NUM_LDO		4
- + /* Number of total regulators available */
- + #define TPS65217_NUM_REGULATOR		(TPS65217_NUM_DCDC + TPS65217_NUM_LDO)
- + 
- + /**
- +  * struct tps65217_board - packages regulator init data
- +  * @tps65217_regulator_data: regulator initialization values
- +  * @status_off: Set the PMIC to shutdown on PWR_EN toggle
- +  *
- +  * Board data may be used to initialize regulator.
- +  */
- + struct tps65217_board {
- + 	struct regulator_init_data *tps65217_init_data;
- + 	bool status_off;
- + };
- + 
- + struct tps65217_rdelay {
- + 	int ramp_delay;
- + };
- + 
- + /**
- +  * struct tps_info - packages regulator constraints
- +  * @name:		Voltage regulator name
- +  * @min_uV:		minimum micro volts
- +  * @max_uV:		minimum micro volts
- +  * @vsel_to_uv:		Function pointer to get voltage from selector
- +  * @uv_to_vsel:		Function pointer to get selector from voltage
- +  * @delay:		Set voltage delay in us
- +  * @table:		Table for non-uniform voltage step-size
- +  * @table_len:		Length of the voltage table
- +  * @enable_mask:	Regulator enable mask bits
- +  * @set_vout_reg:	Regulator output voltage set register
- +  * @set_vout_mask:	Regulator output voltage set mask
- +  *
- +  * This data is used to check the regualtor voltage limits while setting.
- +  */
- + struct tps_info {
- + 	const char *name;
- + 	int min_uV;
- + 	int max_uV;
- + 	int (*vsel_to_uv)(unsigned int vsel);
- + 	int (*uv_to_vsel)(int uV, unsigned int *vsel);
- + 	int delay;
- + 	const int *table;
- + 	unsigned int table_len;
- + 	unsigned int enable_mask;
- + 	unsigned int set_vout_reg;
- + 	unsigned int set_vout_mask;
- + };
- + 
- + /**
- +  * struct tps65217 - tps65217 sub-driver chip access routines
- +  *
- +  * Device data may be used to access the TPS65217 chip
- +  */
- + 
- + struct tps65217 {
- + 	struct device *dev;
- + 	struct tps65217_board *pdata;
- + 	struct regulator_desc desc[TPS65217_NUM_REGULATOR];
- + 	struct regulator_dev *rdev[TPS65217_NUM_REGULATOR];
- + 	struct tps_info *info[TPS65217_NUM_REGULATOR];
- + 	struct regmap *regmap;
- + 
- + 	/* Client devices */
- + 	struct platform_device *regulator_pdev[TPS65217_NUM_REGULATOR];
- + };
- + 
- + static inline struct tps65217 *dev_to_tps65217(struct device *dev)
- + {
- + 	return dev_get_drvdata(dev);
- + }
- + 
- + int tps65217_reg_read(struct tps65217 *tps, unsigned int reg,
- + 					unsigned int *val);
- + int tps65217_reg_write(struct tps65217 *tps, unsigned int reg,
- + 			unsigned int val, unsigned int level);
- + int tps65217_set_bits(struct tps65217 *tps, unsigned int reg,
- + 		unsigned int mask, unsigned int val, unsigned int level);
- + int tps65217_clear_bits(struct tps65217 *tps, unsigned int reg,
- + 		unsigned int mask, unsigned int level);
- + 
- + #endif /*  __LINUX_MFD_TPS65217_H */
- diff -crN linux-3.2.1_o/include/linux/mfd/tps65910.h linux-3.2.1/include/linux/mfd/tps65910.h
- *** linux-3.2.1_o/include/linux/mfd/tps65910.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/include/linux/mfd/tps65910.h	2014-05-15 13:25:15.267269214 +0900
- ***************
- *** 17,26 ****
- --- 17,33 ----
-   #ifndef __LINUX_MFD_TPS65910_H
-   #define __LINUX_MFD_TPS65910_H
-   
- + #include <linux/gpio.h>
- + #include <linux/regulator/machine.h>
- + 
-   /* TPS chip id list */
-   #define TPS65910			0
-   #define TPS65911			1
-   
- + /* I2C Slave Address 7-bit */
- + #define TPS65910_I2C_ID0 0x12 /* Smart Reflex */
- + #define TPS65910_I2C_ID1 0x2D /* general-purpose control */
- + 
-   /* TPS regulator type list */
-   #define REGULATOR_LDO			0
-   #define REGULATOR_DCDC			1
- ***************
- *** 740,745 ****
- --- 747,780 ----
-   #define TPS65910_GPIO_STS				BIT(1)
-   #define TPS65910_GPIO_SET				BIT(0)
-   
- + /* Regulator Index Definitions */
- + #define TPS65910_REG_VRTC				0
- + #define TPS65910_REG_VIO				1
- + #define TPS65910_REG_VDD1				2
- + #define TPS65910_REG_VDD2				3
- + #define TPS65910_REG_VDD3				4
- + #define TPS65910_REG_VDIG1				5
- + #define TPS65910_REG_VDIG2				6
- + #define TPS65910_REG_VPLL				7
- + #define TPS65910_REG_VDAC				8
- + #define TPS65910_REG_VAUX1				9
- + #define TPS65910_REG_VAUX2				10
- + #define TPS65910_REG_VAUX33				11
- + #define TPS65910_REG_VMMC				12
- + 
- + #define TPS65911_REG_VDDCTRL				4
- + #define TPS65911_REG_LDO1				5
- + #define TPS65911_REG_LDO2				6
- + #define TPS65911_REG_LDO3				7
- + #define TPS65911_REG_LDO4				8
- + #define TPS65911_REG_LDO5				9
- + #define TPS65911_REG_LDO6				10
- + #define TPS65911_REG_LDO7				11
- + #define TPS65911_REG_LDO8				12
- + 
- + /* Max number of TPS65910/11 regulators */
- + #define TPS65910_NUM_REGS				13
- + 
-   /**
-    * struct tps65910_board
-    * Board platform data may be used to initialize regulators.
- ***************
- *** 751,757 ****
-   	int irq_base;
-   	int vmbch_threshold;
-   	int vmbch2_threshold;
- ! 	struct regulator_init_data *tps65910_pmic_init_data;
-   };
-   
-   /**
- --- 786,792 ----
-   	int irq_base;
-   	int vmbch_threshold;
-   	int vmbch2_threshold;
- ! 	struct regulator_init_data *tps65910_pmic_init_data[TPS65910_NUM_REGS];
-   };
-   
-   /**
- diff -crN linux-3.2.1_o/include/linux/mmc/card.h linux-3.2.1/include/linux/mmc/card.h
- *** linux-3.2.1_o/include/linux/mmc/card.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/include/linux/mmc/card.h	2014-05-15 13:25:15.295328550 +0900
- ***************
- *** 206,211 ****
- --- 206,212 ----
-   #define MMC_STATE_HIGHSPEED_DDR (1<<4)		/* card is in high speed mode */
-   #define MMC_STATE_ULTRAHIGHSPEED (1<<5)		/* card is in ultra high speed mode */
-   #define MMC_CARD_SDXC		(1<<6)		/* card is SDXC */
- + #define MMC_CARD_REMOVED	(1<<7)		/* card has been removed */
-   	unsigned int		quirks; 	/* card quirks */
-   #define MMC_QUIRK_LENIENT_FN0	(1<<0)		/* allow SDIO FN0 writes outside of the VS CCCR range */
-   #define MMC_QUIRK_BLKSZ_FOR_BYTE_MODE (1<<1)	/* use func->cur_blksize */
- ***************
- *** 366,371 ****
- --- 367,373 ----
-   #define mmc_card_ddr_mode(c)	((c)->state & MMC_STATE_HIGHSPEED_DDR)
-   #define mmc_sd_card_uhs(c) ((c)->state & MMC_STATE_ULTRAHIGHSPEED)
-   #define mmc_card_ext_capacity(c) ((c)->state & MMC_CARD_SDXC)
- + #define mmc_card_removed(c)	((c) && ((c)->state & MMC_CARD_REMOVED))
-   
-   #define mmc_card_set_present(c)	((c)->state |= MMC_STATE_PRESENT)
-   #define mmc_card_set_readonly(c) ((c)->state |= MMC_STATE_READONLY)
- ***************
- *** 374,379 ****
- --- 376,382 ----
-   #define mmc_card_set_ddr_mode(c) ((c)->state |= MMC_STATE_HIGHSPEED_DDR)
-   #define mmc_sd_card_set_uhs(c) ((c)->state |= MMC_STATE_ULTRAHIGHSPEED)
-   #define mmc_card_set_ext_capacity(c) ((c)->state |= MMC_CARD_SDXC)
- + #define mmc_card_set_removed(c) ((c)->state |= MMC_CARD_REMOVED)
-   
-   /*
-    * Quirk add/remove for MMC products.
- ***************
- *** 455,461 ****
-   	struct device_driver drv;
-   	int (*probe)(struct mmc_card *);
-   	void (*remove)(struct mmc_card *);
- ! 	int (*suspend)(struct mmc_card *, pm_message_t);
-   	int (*resume)(struct mmc_card *);
-   };
-   
- --- 458,464 ----
-   	struct device_driver drv;
-   	int (*probe)(struct mmc_card *);
-   	void (*remove)(struct mmc_card *);
- ! 	int (*suspend)(struct mmc_card *);
-   	int (*resume)(struct mmc_card *);
-   };
-   
- diff -crN linux-3.2.1_o/include/linux/mmc/core.h linux-3.2.1/include/linux/mmc/core.h
- *** linux-3.2.1_o/include/linux/mmc/core.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/include/linux/mmc/core.h	2014-05-15 13:25:15.307343576 +0900
- ***************
- *** 180,185 ****
- --- 180,187 ----
-   
-   extern int mmc_flush_cache(struct mmc_card *);
-   
- + extern int mmc_detect_card_removed(struct mmc_host *host);
- + 
-   /**
-    *	mmc_claim_host - exclusively claim a host
-    *	@host: mmc host to claim
- diff -crN linux-3.2.1_o/include/linux/mmc/host.h linux-3.2.1/include/linux/mmc/host.h
- *** linux-3.2.1_o/include/linux/mmc/host.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/include/linux/mmc/host.h	2014-05-15 13:25:15.311324320 +0900
- ***************
- *** 213,218 ****
- --- 213,219 ----
-   #define MMC_CAP_WAIT_WHILE_BUSY	(1 << 9)	/* Waits while card is busy */
-   #define MMC_CAP_ERASE		(1 << 10)	/* Allow erase/trim commands */
-   #define MMC_CAP_1_8V_DDR	(1 << 11)	/* can support */
- + #define MMC_CAP2_DETECT_ON_ERR (1 << 8)        /* On I/O err check card removal */
-   						/* DDR mode at 1.8V */
-   #define MMC_CAP_1_2V_DDR	(1 << 12)	/* can support */
-   						/* DDR mode at 1.2V */
- ***************
- *** 297,302 ****
- --- 298,304 ----
-   	int			claim_cnt;	/* "claim" nesting count */
-   
-   	struct delayed_work	detect;
- + 	int			detect_change;	/* card detect flag */
-   
-   	const struct mmc_bus_ops *bus_ops;	/* current bus driver */
-   	unsigned int		bus_refs;	/* reference counter */
- diff -crN linux-3.2.1_o/include/linux/net_switch_config.h linux-3.2.1/include/linux/net_switch_config.h
- *** linux-3.2.1_o/include/linux/net_switch_config.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/include/linux/net_switch_config.h	2014-05-15 13:25:15.314662569 +0900
- ***************
- *** 0 ****
- --- 1,120 ----
- + /*
- +  * Texas Instruments Ethernet Switch Driver
- +  *
- +  * Copyright (C) 2012 Texas Instruments
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + /*
- +  * Userspace API for Switch Configuration
- +  */
- + 
- + #ifndef __NET_CONFIG_SWITCH_H__
- + #define __NET_CONFIG_SWITCH_H__
- + 
- + enum {
- + 	CONFIG_SWITCH_INVALID,
- + 	CONFIG_SWITCH_ADD_MULTICAST,
- + 	CONFIG_SWITCH_ADD_UNICAST,
- + 	CONFIG_SWITCH_ADD_OUI,
- + 	CONFIG_SWITCH_FIND_ADDR,
- + 	CONFIG_SWITCH_DEL_MULTICAST,
- + 	CONFIG_SWITCH_DEL_UNICAST,
- + 	CONFIG_SWITCH_ADD_VLAN,
- + 	CONFIG_SWITCH_FIND_VLAN,
- + 	CONFIG_SWITCH_DEL_VLAN,
- + 	CONFIG_SWITCH_SET_PORT_VLAN_CONFIG,
- + 	CONFIG_SWITCH_TIMEOUT,
- + 	CONFIG_SWITCH_DUMP,
- + 	CONFIG_SWITCH_SET_FLOW_CONTROL,
- + 	CONFIG_SWITCH_SET_PRIORITY_MAPPING,
- + 	CONFIG_SWITCH_PORT_STATISTICS_ENABLE,
- + 	CONFIG_SWITCH_CONFIG_DUMP,
- + 	CONFIG_SWITCH_RATELIMIT,
- + 	CONFIG_SWITCH_VID_INGRESS_CHECK,
- + 	CONFIG_SWITCH_ADD_UNKNOWN_VLAN_INFO,
- + 	CONFIG_SWITCH_802_1,
- + 	CONFIG_SWITCH_MACAUTH,
- + 	CONFIG_SWITCH_SET_PORT_CONFIG,
- + 	CONFIG_SWITCH_GET_PORT_CONFIG,
- + 	CONFIG_SWITCH_PORT_STATE,
- + 	CONFIG_SWITCH_RESET,
- + };
- + 
- + enum {
- + 	ADDR_TYPE_BROADCAST = 1,
- + 	ADDR_TYPE_MULTICAST,
- + 	ADDR_TYPE_UNICAST,
- + };
- + 
- + enum {
- + 	PORT_STATE_DISABLED = 0,
- + 	PORT_STATE_BLOCKED,
- + 	PORT_STATE_LEARN,
- + 	PORT_STATE_FORWARD,
- + };
- + 
- + struct net_switch_cmd {
- + 	unsigned int	port;
- + 	unsigned int	vid;		/* VLAN identifier */
- + 	unsigned int	prio_port;	/* port priority 0 -7 */
- + 	unsigned int	CFI_port;	/* port CFI  0 /1 */
- + 	unsigned int	mem_port;	/* port number 0 - 2 */
- + 	unsigned char	unreg_multi;	/* unreg multicast Egress Ports */
- + 	unsigned char	reg_multi;	/* register multicast Egress ports */
- + 	unsigned char	untag_port;	/* Untag ports */
- + 	unsigned char	addr[6];
- + 	unsigned int	flag;
- + 	unsigned int	blocked;
- + 	unsigned int	secure;
- + 	unsigned int	ageable;
- + 	unsigned int	ale_timeout;
- + 	unsigned char	aledump;	/* if 1 print ale table */
- + };
- + 
- + struct net_switch_port_cmd {
- + 	unsigned int	port;		/* Port number */
- + 	unsigned int	direction;	/* Tx -1 / Rx - 0 */
- + 	unsigned int	addr_type;	/* Address type BroadMulti/Uni cast */
- + 	unsigned int	limit;		/* multicast/broadcast limit */
- + 	unsigned int	vlan_ingress_check;
- + 	unsigned int	port_state;
- + 	unsigned int	vlan_port_mask;
- + 	unsigned char	drop_untagged;
- + 	unsigned char	enable;		/* 1-enable/0-Disable */
- + 	unsigned int	reg_multi_port_mask;
- + 	unsigned int	unknown_reg_multi_port_mask;
- + 	unsigned char	unknown_vlan_member;
- + };
- + 
- + struct net_switch_prio_cmd {
- + 	unsigned char port;
- + 	unsigned char prio_rx;
- + 	unsigned char prio_tx;
- + 	unsigned char prio_switch;
- + 	unsigned char hostRxCh;		/* packet with switch priority receive
- + 						on this channel */
- + 	unsigned char hostRxChSuper;	/* supervisory packet receive on
- + 						this channel */
- + };
- + 
- + struct net_switch_config {
- + 	unsigned int cmd;	/* API to be invoked by the kernel driver */
- + 	union {
- + 		struct net_switch_cmd switchcmd;
- + 		struct net_switch_port_cmd portcmd;
- + 		struct net_switch_prio_cmd priocmd;
- + 		char buf[4096];		/* Buffer for Ale Dump */
- + 	} cmd_data;
- + 	unsigned int ret_type;   /* Return  Success/Failure */
- + };
- + 
- + #endif /* __NET_CONFIG_SWITCH_H__*/
- diff -crN linux-3.2.1_o/include/linux/phy.h linux-3.2.1/include/linux/phy.h
- *** linux-3.2.1_o/include/linux/phy.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/include/linux/phy.h	2014-05-15 13:25:15.330771578 +0900
- ***************
- *** 496,501 ****
- --- 496,502 ----
-   	return phydev->drv->read_status(phydev);
-   }
-   
- + int genphy_config_init(struct phy_device *phydev);
-   int genphy_restart_aneg(struct phy_device *phydev);
-   int genphy_config_aneg(struct phy_device *phydev);
-   int genphy_update_link(struct phy_device *phydev);
- diff -crN linux-3.2.1_o/include/linux/platform_data/ti_adc.h linux-3.2.1/include/linux/platform_data/ti_adc.h
- *** linux-3.2.1_o/include/linux/platform_data/ti_adc.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/include/linux/platform_data/ti_adc.h	2014-05-15 13:25:15.335266514 +0900
- ***************
- *** 0 ****
- --- 1,9 ----
- + /**
- +  * struct adc_data	ADC Input information
- +  * @adc_channels:	Number of analog inputs
- +  *			available for ADC.
- +  */
- + 
- + struct adc_data {
- + 	int adc_channels;
- + };
- diff -crN linux-3.2.1_o/include/linux/pwm/ehrpwm.h linux-3.2.1/include/linux/pwm/ehrpwm.h
- *** linux-3.2.1_o/include/linux/pwm/ehrpwm.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/include/linux/pwm/ehrpwm.h	2014-05-15 13:25:15.335266514 +0900
- ***************
- *** 0 ****
- --- 1,188 ----
- + #ifndef __EHRPWM_H__
- + #define __EHRPWM_H__
- + 
- + #include <linux/pwm/pwm.h>
- + 
- + #define NCHAN 2
- + 
- + struct ehrpwm_pwm;
- + 
- + typedef int (*p_fcallback) (struct ehrpwm_pwm *, void *data);
- + 
- + struct et_int {
- + 	void *data;
- + 	p_fcallback pcallback;
- + };
- + 
- + struct tz_int {
- + 	void *data;
- + 	p_fcallback pcallback;
- + };
- + 
- + struct ehrpwm_context {
- + 	u32 tbctl;
- + 	u32 tbprd;
- + 	u32 hrcfg;
- + 	u32 aqctla;
- + 	u32 aqctlb;
- + 	u32 aqsfrc;
- + 	u32 aqcsfrc;
- + 	u32 cmpa;
- + 	u32 cmpb;
- + };
- + 
- + struct ehrpwm_pwm {
- + 	struct pwm_device pwm[NCHAN];
- + 	struct pwm_device_ops ops;
- + 	spinlock_t      lock;
- + 	struct clk      *clk;
- + 	void __iomem    *mmio_base;
- + 	unsigned short prescale_val;
- + 	int irq[2];
- + 	struct et_int st_etint;
- + 	struct tz_int st_tzint;
- + 	u8 version;
- + 	void __iomem *config_mem_base;
- + 	struct device *dev;
- + 	struct ehrpwm_context ctx;
- + };
- + 
- + enum tz_event {
- + 	TZ_ONE_SHOT_EVENT = 0,
- + 	TZ_CYCLE_BY_CYCLE,
- + 	TZ_OSHT_CBC,
- + 	TZ_DIS_EVT,
- + };
- + 
- + enum config_mask {
- + 	CONFIG_NS,
- + 	CONFIG_TICKS,
- + };
- + 
- + enum db_edge_delay {
- + 	RISING_EDGE_DELAY,
- + 	FALLING_EDGE_DELAY,
- + };
- + 
- + struct aq_config_params {
- + 	unsigned char ch;
- + 	unsigned char ctreqzro;
- + 	unsigned char ctreqprd;
- + 	unsigned char ctreqcmpaup;
- + 	unsigned char ctreqcmpadown;
- + 	unsigned char ctreqcmpbup;
- + 	unsigned char ctreqcmpbdown;
- + };
- + 
- + int ehrpwm_tb_set_prescalar_val(struct pwm_device *p, unsigned char
- + 	clkdiv, unsigned char hspclkdiv);
- + 
- + int ehrpwm_tb_config_sync(struct pwm_device *p, unsigned char phsen,
- + 	unsigned char syncosel);
- + 
- + int ehrpwm_tb_set_counter_mode(struct pwm_device *p, unsigned char
- + 	ctrmode, unsigned char phsdir);
- + 
- + int ehrpwm_tb_force_sync(struct pwm_device *p);
- + 
- + int ehrpwm_tb_set_periodload(struct pwm_device *p, unsigned char
- + 	       loadmode);
- + 
- + int ehrpwm_tb_read_status(struct pwm_device *p, unsigned short *val);
- + 
- + int ehrpwm_tb_read_counter(struct pwm_device *p, unsigned short *val);
- + 
- + int ehrpwm_tb_set_period(struct pwm_device *p,	unsigned short val);
- + 
- + int ehrpwm_tb_set_phase(struct pwm_device *p, unsigned short val);
- + 
- + int ehrpwm_cmp_set_cmp_ctl(struct pwm_device *p, unsigned char
- + 	       shdwamode, unsigned char shdwbmode, unsigned char loadamode,
- + 	unsigned char loadbmode);
- + 
- + int ehrpwm_cmp_set_cmp_val(struct pwm_device *p, unsigned char reg,
- + 	unsigned short val);
- + 
- + int ehrpwm_aq_set_act_ctrl(struct pwm_device *p,
- + 	       struct aq_config_params *cfg);
- + 
- + int ehrpwm_aq_set_one_shot_act(struct pwm_device  *p, unsigned char ch,
- + 	unsigned char act);
- + 
- + int ehrpwm_aq_ot_frc(struct pwm_device *p, unsigned char ch);
- + 
- + int ehrpwm_aq_set_csfrc_load_mode(struct pwm_device *p, unsigned char
- + 	       loadmode);
- + 
- + int ehrpwm_aq_continuous_frc(struct pwm_device *p, unsigned char ch,
- + 	unsigned char act);
- + 
- + int ehrpwm_db_get_max_delay(struct pwm_device *p,
- + 	       enum config_mask cfgmask, unsigned long *delay_val);
- + 
- + int ehrpwm_db_get_delay(struct pwm_device *p, unsigned char edge,
- + 	enum config_mask cfgmask, unsigned long *delay_val);
- + 
- + int ehrpwm_db_set_delay(struct pwm_device *p, unsigned char edge,
- + 		enum config_mask cfgmask, unsigned long delay);
- + 
- + int ehrpwm_db_set_mode(struct pwm_device *p, unsigned char inmode,
- + 		unsigned char polsel, unsigned char outmode);
- + 
- + int ehrpwm_pc_configure(struct pwm_device *p, unsigned char chpduty,
- + 		unsigned char chpfreq, unsigned char oshtwidth);
- + 
- + int ehrpwm_pc_en_dis(struct pwm_device *p, unsigned char chpen);
- + 
- + int ehrpwm_tz_sel_event(struct pwm_device *p, unsigned char input,
- + 	       enum tz_event evt);
- + 
- + int ehrpwm_tz_set_action(struct pwm_device *p, unsigned char ch,
- + 	unsigned char act);
- + 
- + int ehrpwm_tz_set_int_en_dis(struct pwm_device *p, enum tz_event event,
- + 		unsigned char int_en_dis);
- + 
- + int ehrpwm_tz_force_evt(struct pwm_device *p, enum tz_event event);
- + 
- + int ehrpwm_tz_read_status(struct pwm_device *p, unsigned short *status);
- + 
- + int ehrpwm_tz_clr_evt_status(struct pwm_device *p);
- + 
- + int ehrpwm_tz_clr_int_status(struct pwm_device *p);
- + 
- + int ehrpwm_et_set_sel_evt(struct pwm_device *p, unsigned char evt,
- + 		unsigned char prd);
- + 
- + int ehrpwm_et_int_en_dis(struct pwm_device *p, unsigned char en_dis);
- + 
- + int ehrpwm_et_read_evt_cnt(struct pwm_device *p, unsigned long *evtcnt);
- + 
- + int pwm_et_read_int_status(struct pwm_device *p,
- + 	unsigned long *status);
- + 
- + int ehrpwm_et_frc_int(struct pwm_device *p);
- + 
- + int ehrpwm_et_clr_int(struct pwm_device *p);
- + 
- + int ehrpwm_hr_set_phase(struct pwm_device *p, unsigned char val);
- + 
- + int ehrpwm_hr_set_cmpval(struct pwm_device *p, unsigned char val);
- + 
- + int ehrpwm_hr_config(struct pwm_device *p, unsigned char loadmode,
- + 		unsigned char ctlmode, unsigned char edgemode);
- + 
- + int ehrpwm_et_cb_register(struct pwm_device *p, void *data,
- + 	p_fcallback cb);
- + 
- + int ehrpwm_tz_cb_register(struct pwm_device *p, void *data,
- + 	p_fcallback cb);
- + 
- + int ehrpwm_pwm_suspend(struct pwm_device *p, enum
- + 	       config_mask config_mask,
- + 	       unsigned long val);
- + 
- + #define ENABLE 1
- + #define DISABLE 0
- + 
- + #endif
- diff -crN linux-3.2.1_o/include/linux/pwm/pwm.h linux-3.2.1/include/linux/pwm/pwm.h
- *** linux-3.2.1_o/include/linux/pwm/pwm.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/include/linux/pwm/pwm.h	2014-05-15 13:25:15.335266514 +0900
- ***************
- *** 0 ****
- --- 1,195 ----
- + /*
- +  * Copyright (C) 2011 Bill Gatliff < bgat@billgatliff.com>
- +  * Copyright (C) 2011 Arun Murthy <arun.murth@stericsson.com>
- +  *
- +  * This program is free software; you may redistribute and/or modify
- +  * it under the terms of the GNU General Public License version 2, as
- +  * published by the Free Software Foundation.
- +  *
- +  * This program is distributed in the hope that it will be useful, but
- +  * WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- +  * General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
- +  * USA
- +  */
- + #ifndef __LINUX_PWM_H
- + #define __LINUX_PWM_H
- + 
- + enum {
- + 	FLAG_REGISTERED		= 0,
- + 	FLAG_REQUESTED		= 1,
- + 	FLAG_STOP		= 2,
- + 	FLAG_RUNNING		= 3,
- + };
- + 
- + enum {
- + 	PWM_CONFIG_DUTY_TICKS	= 0,
- + 	PWM_CONFIG_PERIOD_TICKS	= 1,
- + 	PWM_CONFIG_POLARITY	= 2,
- + 	PWM_CONFIG_START	= 3,
- + 	PWM_CONFIG_STOP		= 4,
- + 
- + 	PWM_CONFIG_HANDLER	= 5,
- + 
- + 	PWM_CONFIG_DUTY_NS	= 6,
- + 	PWM_CONFIG_DUTY_PERCENT	= 7,
- + 	PWM_CONFIG_PERIOD_NS	= 8,
- + };
- + 
- + struct pwm_config;
- + struct pwm_device;
- + 
- + typedef int (*pwm_handler_t)(struct pwm_device *p, void *data);
- + typedef void (*pwm_callback_t)(struct pwm_device *p);
- + 
- + struct pwm_device_ops {
- + 	int	(*request)		(struct pwm_device *p);
- + 	void	(*release)		(struct pwm_device *p);
- + 	int	(*config)		(struct pwm_device *p,
- + 					 struct pwm_config *c);
- + 	int	(*config_nosleep)	(struct pwm_device *p,
- + 					 struct pwm_config *c);
- + 	int	(*synchronize)		(struct pwm_device *p,
- + 					 struct pwm_device *to_p);
- + 	int	(*unsynchronize)	(struct pwm_device *p,
- + 					 struct pwm_device *from_p);
- + 	int	(*set_callback)		(struct pwm_device *p,
- + 					 pwm_callback_t callback);
- + 	int	(*freq_transition_notifier_cb) (struct pwm_device *p);
- + };
- + 
- + struct pwm_config {
- + 	unsigned long config_mask;
- + 	unsigned long duty_ticks;
- + 	unsigned long period_ticks;
- + 	int polarity;
- + 
- + 	pwm_handler_t handler;
- + 
- + 	unsigned long duty_ns;
- + 	unsigned long period_ns;
- + 	int duty_percent;
- + };
- + 
- + struct pwm_device {
- + 	struct list_head list;
- + 
- + 	struct device *dev;
- + 	struct pwm_device_ops *ops;
- + 
- + 	void *data;
- + 
- + 	const char *label;
- + 	pid_t pid;
- + 
- + 	volatile unsigned long flags;
- + 
- + 	unsigned long tick_hz;
- + 
- + 	pwm_callback_t callback;
- + 
- + 	struct work_struct handler_work;
- + 	pwm_handler_t handler;
- + 	void *handler_data;
- + 
- + 	int active_high;
- + 	unsigned long period_ticks;
- + 	unsigned long duty_ticks;
- + 	unsigned long period_ns;
- + 	unsigned long duty_ns;
- + 	struct notifier_block freq_transition;
- + 	unsigned long max_period_ticks;
- + 	spinlock_t pwm_lock;
- + };
- + 
- + #include <linux/semaphore.h>
- + #include <linux/pwm/ehrpwm.h>
- + 
- + enum {
- + 	PWM_VERSION_0,
- + 	PWM_VERSION_1,
- + };
- + 
- + struct pwm_chan_attrib {
- + 	int max_freq;
- + 	bool inverse_pol;
- + };
- + 
- + #define PWM_CHANNEL NCHAN
- + 
- + struct pwmss_platform_data {
- + 	int channel_mask;
- + 	u8 version;
- + 	struct pwm_chan_attrib chan_attrib[PWM_CHANNEL];
- + };
- + 
- + struct pwm_device *pwm_request_byname(const char *name, const char *label);
- + struct pwm_device *pwm_request(const char *bus_id, int id, const char *label);
- + void pwm_release(struct pwm_device *p);
- + 
- + static inline int pwm_is_registered(struct pwm_device *p)
- + {
- + 	return test_bit(FLAG_REGISTERED, &p->flags);
- + }
- + 
- + static inline int pwm_is_requested(struct pwm_device *p)
- + {
- + 	return test_bit(FLAG_REQUESTED, &p->flags);
- + }
- + 
- + static inline int pwm_is_running(struct pwm_device *p)
- + {
- + 	return test_bit(FLAG_RUNNING, &p->flags);
- + }
- + 
- + static inline void pwm_set_drvdata(struct pwm_device *p, void *data)
- + {
- + 	p->data = data;
- + }
- + 
- + static inline void *pwm_get_drvdata(const struct pwm_device *p)
- + {
- + 	return p->data;
- + }
- + 
- + unsigned long pwm_ns_to_ticks(struct pwm_device *p, unsigned long nsecs);
- + unsigned long pwm_ticks_to_ns(struct pwm_device *p, unsigned long ticks);
- + 
- + int pwm_config_nosleep(struct pwm_device *p, struct pwm_config *c);
- + int pwm_config(struct pwm_device *p, struct pwm_config *c);
- + 
- + int pwm_set_period_ns(struct pwm_device *p, unsigned long period_ns);
- + unsigned long pwm_get_period_ns(struct pwm_device *p);
- + int pwm_set_duty_ns(struct pwm_device *p, unsigned long duty_ns);
- + unsigned long pwm_get_duty_ns(struct pwm_device *p);
- + int pwm_set_duty_percent(struct pwm_device *p, int percent);
- + int pwm_set_polarity(struct pwm_device *p, int active_high);
- + 
- + int pwm_start(struct pwm_device *p);
- + int pwm_stop(struct pwm_device *p);
- + 
- + int pwm_synchronize(struct pwm_device *p, struct pwm_device *to_p);
- + int pwm_unsynchronize(struct pwm_device *p, struct pwm_device *from_p);
- + int pwm_set_handler(struct pwm_device *p, pwm_handler_t handler, void *data);
- + 
- + int pwm_register(struct pwm_device *p, struct device *parent, int id);
- + int pwm_register_byname(struct pwm_device *p, struct device *parent,
- + 			const char *name);
- + int pwm_unregister(struct pwm_device *p);
- + 
- + #ifdef CONFIG_GPIO_PWM
- + struct pwm_device *gpio_pwm_create(int gpio);
- + int gpio_pwm_destroy(struct pwm_device *p);
- + #endif
- + int pwm_set_frequency(struct pwm_device *p, unsigned long freq);
- + unsigned long pwm_get_frequency(struct pwm_device *p);
- + int pwm_set_period_ticks(struct pwm_device *p,
- + 					unsigned long ticks);
- + unsigned long pwm_get_duty_percent(struct pwm_device *p);
- + int pwm_set_duty_ticks(struct pwm_device *p,
- + 					unsigned long ticks);
- + #endif
- diff -crN linux-3.2.1_o/include/linux/pwm_backlight.h linux-3.2.1/include/linux/pwm_backlight.h
- *** linux-3.2.1_o/include/linux/pwm_backlight.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/include/linux/pwm_backlight.h	2014-05-15 13:25:15.448571322 +0900
- ***************
- *** 7,13 ****
-   #include <linux/backlight.h>
-   
-   struct platform_pwm_backlight_data {
- ! 	int pwm_id;
-   	unsigned int max_brightness;
-   	unsigned int dft_brightness;
-   	unsigned int lth_brightness;
- --- 7,14 ----
-   #include <linux/backlight.h>
-   
-   struct platform_pwm_backlight_data {
- ! 	const char *pwm_id;
- ! 	int ch;
-   	unsigned int max_brightness;
-   	unsigned int dft_brightness;
-   	unsigned int lth_brightness;
- diff -crN linux-3.2.1_o/include/linux/random.h linux-3.2.1/include/linux/random.h
- *** linux-3.2.1_o/include/linux/random.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/include/linux/random.h	2014-05-15 13:25:15.467318011 +0900
- ***************
- *** 34,39 ****
- --- 34,63 ----
-   /* Clear the entropy pool and associated counters.  (Superuser only.) */
-   #define RNDCLEARPOOL	_IO( 'R', 0x06 )
-   
- + #ifdef CONFIG_FIPS_RNG
- + 
- + /* Size of seed value - equal to AES blocksize */
- + #define AES_BLOCK_SIZE_BYTES	16
- + #define SEED_SIZE_BYTES			AES_BLOCK_SIZE_BYTES
- + /* Size of AES key */
- + #define KEY_SIZE_BYTES		16
- + 
- + /* ioctl() structure used by FIPS 140-2 Tests */
- + struct rand_fips_test {
- + 	unsigned char key[KEY_SIZE_BYTES];			/* Input */
- + 	unsigned char datetime[SEED_SIZE_BYTES];	/* Input */
- + 	unsigned char seed[SEED_SIZE_BYTES];		/* Input */
- + 	unsigned char result[SEED_SIZE_BYTES];		/* Output */
- + };
- + 
- + /* FIPS 140-2 RNG Variable Seed Test. (Superuser only.) */
- + #define RNDFIPSVST	_IOWR('R', 0x10, struct rand_fips_test)
- + 
- + /* FIPS 140-2 RNG Monte Carlo Test. (Superuser only.) */
- + #define RNDFIPSMCT	_IOWR('R', 0x11, struct rand_fips_test)
- + 
- + #endif /* #ifdef CONFIG_FIPS_RNG */
- + 
-   struct rand_pool_info {
-   	int	entropy_count;
-   	int	buf_size;
- ***************
- *** 54,59 ****
- --- 78,87 ----
-   				 unsigned int value);
-   extern void add_interrupt_randomness(int irq);
-   
- + extern void random_input_words(__u32 *buf, size_t wordcount, int ent_count);
- + extern int random_input_wait(void);
- + #define HAS_RANDOM_INPUT_WAIT 1
- + 
-   extern void get_random_bytes(void *buf, int nbytes);
-   void generate_random_uuid(unsigned char uuid_out[16]);
-   
- diff -crN linux-3.2.1_o/include/linux/rcupdate.h linux-3.2.1/include/linux/rcupdate.h
- *** linux-3.2.1_o/include/linux/rcupdate.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/include/linux/rcupdate.h	2014-05-15 13:25:15.475330607 +0900
- ***************
- *** 800,812 ****
-   	return offset < 4096;
-   }
-   
-   static __always_inline
-   void __kfree_rcu(struct rcu_head *head, unsigned long offset)
-   {
-   	typedef void (*rcu_callback)(struct rcu_head *);
-   
- - 	BUILD_BUG_ON(!__builtin_constant_p(offset));
- - 
-   	/* See the kfree_rcu() header comment. */
-   	BUILD_BUG_ON(!__is_kfree_rcu_offset(offset));
-   
- --- 800,813 ----
-   	return offset < 4096;
-   }
-   
- + /*
- +  * Intended to be called only from the kfree_rcu() macro.
- +  */
-   static __always_inline
-   void __kfree_rcu(struct rcu_head *head, unsigned long offset)
-   {
-   	typedef void (*rcu_callback)(struct rcu_head *);
-   
-   	/* See the kfree_rcu() header comment. */
-   	BUILD_BUG_ON(!__is_kfree_rcu_offset(offset));
-   
- diff -crN linux-3.2.1_o/include/linux/regulator/driver.h linux-3.2.1/include/linux/regulator/driver.h
- *** linux-3.2.1_o/include/linux/regulator/driver.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/include/linux/regulator/driver.h	2014-05-15 13:25:15.556303551 +0900
- ***************
- *** 204,210 ****
-   	int deferred_disables;
-   
-   	void *reg_data;		/* regulator_dev data */
- ! 
-   #ifdef CONFIG_DEBUG_FS
-   	struct dentry *debugfs;
-   #endif
- --- 204,210 ----
-   	int deferred_disables;
-   
-   	void *reg_data;		/* regulator_dev data */
- !         int ignore_check_consumers;
-   #ifdef CONFIG_DEBUG_FS
-   	struct dentry *debugfs;
-   #endif
- diff -crN linux-3.2.1_o/include/linux/regulator/machine.h linux-3.2.1/include/linux/regulator/machine.h
- *** linux-3.2.1_o/include/linux/regulator/machine.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/include/linux/regulator/machine.h	2014-05-15 13:25:15.575261056 +0900
- ***************
- *** 169,175 ****
-    *               be usable.
-    * @num_consumer_supplies: Number of consumer device supplies.
-    * @consumer_supplies: Consumer device supply configuration.
- !  *
-    * @regulator_init: Callback invoked when the regulator has been registered.
-    * @driver_data: Data passed to regulator_init.
-    */
- --- 169,175 ----
-    *               be usable.
-    * @num_consumer_supplies: Number of consumer device supplies.
-    * @consumer_supplies: Consumer device supply configuration.
- !  * @ignore_check_consumers: If != 0, regulator_check_consumers() is disabled.
-    * @regulator_init: Callback invoked when the regulator has been registered.
-    * @driver_data: Data passed to regulator_init.
-    */
- ***************
- *** 181,186 ****
- --- 181,187 ----
-   	int num_consumer_supplies;
-   	struct regulator_consumer_supply *consumer_supplies;
-   
- +         int ignore_check_consumers;
-   	/* optional regulator machine specific init */
-   	int (*regulator_init)(void *driver_data);
-   	void *driver_data;	/* core does not touch this */
- diff -crN linux-3.2.1_o/include/linux/rtc/rtc-omap.h linux-3.2.1/include/linux/rtc/rtc-omap.h
- *** linux-3.2.1_o/include/linux/rtc/rtc-omap.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/include/linux/rtc/rtc-omap.h	2014-05-15 13:25:15.591270259 +0900
- ***************
- *** 0 ****
- --- 1,30 ----
- + /*
- +  * RTC-OMAP driver platform header
- +  *
- +  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #ifndef _LINUX_RTC_OMAP_H_
- + #define _LINUX_RTC_OMAP_H_
- + 
- + /**
- +  * struct omap_rtc_pdata - OMAP rtc Platform Data
- +  *
- +  * @pm_off:		Flag to specify whether the RTC is incharge of
- +  *			controlling the system/device power.
- +  * @wakeup_capable:	module supports wakeup from suspend with alarm events
- +  */
- + struct omap_rtc_pdata {
- + 	bool pm_off;
- + 	unsigned wakeup_capable:1;
- + };
- + #endif
- diff -crN linux-3.2.1_o/include/linux/sched.h linux-3.2.1/include/linux/sched.h
- *** linux-3.2.1_o/include/linux/sched.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/include/linux/sched.h	2014-05-15 13:25:15.607257438 +0900
- ***************
- *** 1302,1307 ****
- --- 1302,1312 ----
-   	unsigned sched_reset_on_fork:1;
-   	unsigned sched_contributes_to_load:1;
-   
- + #ifdef CONFIG_GENERIC_HARDIRQS
- + 	/* IRQ handler threads */
- + 	unsigned irq_thread:1;
- + #endif
- + 
-   	pid_t pid;
-   	pid_t tgid;
-   
- ***************
- *** 1410,1420 ****
-    * mempolicy */
-   	spinlock_t alloc_lock;
-   
- - #ifdef CONFIG_GENERIC_HARDIRQS
- - 	/* IRQ handler threads */
- - 	struct irqaction *irqaction;
- - #endif
- - 
-   	/* Protection of the PI data structures: */
-   	raw_spinlock_t pi_lock;
-   
- --- 1415,1420 ----
- diff -crN linux-3.2.1_o/include/linux/sockios.h linux-3.2.1/include/linux/sockios.h
- *** linux-3.2.1_o/include/linux/sockios.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/include/linux/sockios.h	2014-05-15 13:25:15.607257438 +0900
- ***************
- *** 127,132 ****
- --- 127,135 ----
-   /* hardware time stamping: parameters in linux/net_tstamp.h */
-   #define SIOCSHWTSTAMP   0x89b0
-   
- + /* Switch config calls: parameters in linux/net_switch_config.h */
- + #define SIOCSWITCHCONFIG    0x89c0
- + 
-   /* Device private ioctl calls */
-   
-   /*
- diff -crN linux-3.2.1_o/include/linux/syscalls.h linux-3.2.1/include/linux/syscalls.h
- *** linux-3.2.1_o/include/linux/syscalls.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/include/linux/syscalls.h	2014-05-15 13:25:15.707304578 +0900
- ***************
- *** 856,860 ****
- --- 856,862 ----
-   				      const struct iovec __user *rvec,
-   				      unsigned long riovcnt,
-   				      unsigned long flags);
- + asmlinkage long sys_ckb3352_change_mux(const char __user *pin_name, unsigned int mux_mode,
- + 				  unsigned int flags);
-   
-   #endif
- diff -crN linux-3.2.1_o/include/linux/usb/ch9.h linux-3.2.1/include/linux/usb/ch9.h
- *** linux-3.2.1_o/include/linux/usb/ch9.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/include/linux/usb/ch9.h	2014-05-15 13:25:15.739277411 +0900
- ***************
- *** 605,630 ****
-   } __attribute__ ((packed));
-   
-   #define USB_DT_SS_EP_COMP_SIZE		6
- - 
-   /* Bits 4:0 of bmAttributes if this is a bulk endpoint */
- ! static inline int
- ! usb_ss_max_streams(const struct usb_ss_ep_comp_descriptor *comp)
- ! {
- ! 	int		max_streams;
- ! 
- ! 	if (!comp)
- ! 		return 0;
- ! 
- ! 	max_streams = comp->bmAttributes & 0x1f;
- ! 
- ! 	if (!max_streams)
- ! 		return 0;
- ! 
- ! 	max_streams = 1 << max_streams;
- ! 
- ! 	return max_streams;
- ! }
- ! 
-   /* Bits 1:0 of bmAttributes if this is an isoc endpoint */
-   #define USB_SS_MULT(p)			(1 + ((p) & 0x3))
-   
- --- 605,612 ----
-   } __attribute__ ((packed));
-   
-   #define USB_DT_SS_EP_COMP_SIZE		6
-   /* Bits 4:0 of bmAttributes if this is a bulk endpoint */
- ! #define USB_SS_MAX_STREAMS(p)		(1 << ((p) & 0x1f))
-   /* Bits 1:0 of bmAttributes if this is an isoc endpoint */
-   #define USB_SS_MULT(p)			(1 + ((p) & 0x3))
-   
- diff -crN linux-3.2.1_o/include/linux/usb/gadget.h linux-3.2.1/include/linux/usb/gadget.h
- *** linux-3.2.1_o/include/linux/usb/gadget.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/include/linux/usb/gadget.h	2014-05-15 13:25:15.751342871 +0900
- ***************
- *** 477,484 ****
-    *	driver setup() requests
-    * @ep_list: List of other endpoints supported by the device.
-    * @speed: Speed of current connection to USB host.
- !  * @is_dualspeed: True if the controller supports both high and full speed
- !  *	operation.  If it does, the gadget driver must also support both.
-    * @is_otg: True if the USB device port uses a Mini-AB jack, so that the
-    *	gadget driver must provide a USB OTG descriptor.
-    * @is_a_peripheral: False unless is_otg, the "A" end of a USB cable
- --- 477,484 ----
-    *	driver setup() requests
-    * @ep_list: List of other endpoints supported by the device.
-    * @speed: Speed of current connection to USB host.
- !  * @max_speed: Maximal speed the UDC can handle.  UDC must support this
- !  *      and all slower speeds.
-    * @is_otg: True if the USB device port uses a Mini-AB jack, so that the
-    *	gadget driver must provide a USB OTG descriptor.
-    * @is_a_peripheral: False unless is_otg, the "A" end of a USB cable
- ***************
- *** 518,524 ****
-   	struct usb_ep			*ep0;
-   	struct list_head		ep_list;	/* of usb_ep */
-   	enum usb_device_speed		speed;
- ! 	unsigned			is_dualspeed:1;
-   	unsigned			is_otg:1;
-   	unsigned			is_a_peripheral:1;
-   	unsigned			b_hnp_enable:1;
- --- 518,524 ----
-   	struct usb_ep			*ep0;
-   	struct list_head		ep_list;	/* of usb_ep */
-   	enum usb_device_speed		speed;
- ! 	enum usb_device_speed		max_speed;
-   	unsigned			is_otg:1;
-   	unsigned			is_a_peripheral:1;
-   	unsigned			b_hnp_enable:1;
- ***************
- *** 549,555 ****
-   static inline int gadget_is_dualspeed(struct usb_gadget *g)
-   {
-   #ifdef CONFIG_USB_GADGET_DUALSPEED
- ! 	/* runtime test would check "g->is_dualspeed" ... that might be
-   	 * useful to work around hardware bugs, but is mostly pointless
-   	 */
-   	return 1;
- --- 549,555 ----
-   static inline int gadget_is_dualspeed(struct usb_gadget *g)
-   {
-   #ifdef CONFIG_USB_GADGET_DUALSPEED
- ! 	/* runtime test would check "g->max_speed" ... that might be
-   	 * useful to work around hardware bugs, but is mostly pointless
-   	 */
-   	return 1;
- ***************
- *** 567,573 ****
-   {
-   #ifdef CONFIG_USB_GADGET_SUPERSPEED
-   	/*
- ! 	 * runtime test would check "g->is_superspeed" ... that might be
-   	 * useful to work around hardware bugs, but is mostly pointless
-   	 */
-   	return 1;
- --- 567,573 ----
-   {
-   #ifdef CONFIG_USB_GADGET_SUPERSPEED
-   	/*
- ! 	 * runtime test would check "g->max_speed" ... that might be
-   	 * useful to work around hardware bugs, but is mostly pointless
-   	 */
-   	return 1;
- ***************
- *** 760,766 ****
-   /**
-    * struct usb_gadget_driver - driver for usb 'slave' devices
-    * @function: String describing the gadget's function
- !  * @speed: Highest speed the driver handles.
-    * @setup: Invoked for ep0 control requests that aren't handled by
-    *	the hardware level driver. Most calls must be handled by
-    *	the gadget driver, including descriptor and configuration
- --- 760,766 ----
-   /**
-    * struct usb_gadget_driver - driver for usb 'slave' devices
-    * @function: String describing the gadget's function
- !  * @max_speed: Highest speed the driver handles.
-    * @setup: Invoked for ep0 control requests that aren't handled by
-    *	the hardware level driver. Most calls must be handled by
-    *	the gadget driver, including descriptor and configuration
- ***************
- *** 824,830 ****
-    */
-   struct usb_gadget_driver {
-   	char			*function;
- ! 	enum usb_device_speed	speed;
-   	void			(*unbind)(struct usb_gadget *);
-   	int			(*setup)(struct usb_gadget *,
-   					const struct usb_ctrlrequest *);
- --- 824,830 ----
-    */
-   struct usb_gadget_driver {
-   	char			*function;
- ! 	enum usb_device_speed	max_speed;
-   	void			(*unbind)(struct usb_gadget *);
-   	int			(*setup)(struct usb_gadget *,
-   					const struct usb_ctrlrequest *);
- diff -crN linux-3.2.1_o/include/linux/usb/musb.h linux-3.2.1/include/linux/usb/musb.h
- *** linux-3.2.1_o/include/linux/usb/musb.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/include/linux/usb/musb.h	2014-05-15 13:25:15.795343575 +0900
- ***************
- *** 62,67 ****
- --- 62,68 ----
-   struct musb_hdrc_config {
-   	struct musb_fifo_cfg	*fifo_cfg;	/* board fifo configuration */
-   	unsigned		fifo_cfg_size;	/* size of the fifo configuration */
- + 	unsigned short		fifo_mode;	/* fifo mode to be selected */
-   
-   	/* MUSB configuration-specific details */
-   	unsigned	multipoint:1;	/* multipoint device */
- diff -crN linux-3.2.1_o/include/linux/usb/otg.h linux-3.2.1/include/linux/usb/otg.h
- *** linux-3.2.1_o/include/linux/usb/otg.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/include/linux/usb/otg.h	2014-05-15 13:25:15.807327468 +0900
- ***************
- *** 63,68 ****
- --- 63,69 ----
-   	struct device		*dev;
-   	const char		*label;
-   	unsigned int		 flags;
- + 	u8			id;
-   
-   	u8			default_a;
-   	enum usb_otg_state	state;
- ***************
- *** 116,132 ****
-   
-   /* for board-specific init logic */
-   extern int otg_set_transceiver(struct otg_transceiver *);
-   
-   #if defined(CONFIG_NOP_USB_XCEIV) || (defined(CONFIG_NOP_USB_XCEIV_MODULE) && defined(MODULE))
-   /* sometimes transceivers are accessed only through e.g. ULPI */
- ! extern void usb_nop_xceiv_register(void);
- ! extern void usb_nop_xceiv_unregister(void);
-   #else
- ! static inline void usb_nop_xceiv_register(void)
-   {
-   }
-   
- ! static inline void usb_nop_xceiv_unregister(void)
-   {
-   }
-   #endif
- --- 117,134 ----
-   
-   /* for board-specific init logic */
-   extern int otg_set_transceiver(struct otg_transceiver *);
- + extern int otg_reset_transceiver(struct otg_transceiver *);
-   
-   #if defined(CONFIG_NOP_USB_XCEIV) || (defined(CONFIG_NOP_USB_XCEIV_MODULE) && defined(MODULE))
-   /* sometimes transceivers are accessed only through e.g. ULPI */
- ! extern void usb_nop_xceiv_register(int id);
- ! extern void usb_nop_xceiv_unregister(int id);
-   #else
- ! static inline void usb_nop_xceiv_register(int id)
-   {
-   }
-   
- ! static inline void usb_nop_xceiv_unregister(int id)
-   {
-   }
-   #endif
- ***************
- *** 166,176 ****
-   
-   /* for usb host and peripheral controller drivers */
-   #ifdef CONFIG_USB_OTG_UTILS
- ! extern struct otg_transceiver *otg_get_transceiver(void);
-   extern void otg_put_transceiver(struct otg_transceiver *);
-   extern const char *otg_state_string(enum usb_otg_state state);
-   #else
- ! static inline struct otg_transceiver *otg_get_transceiver(void)
-   {
-   	return NULL;
-   }
- --- 168,178 ----
-   
-   /* for usb host and peripheral controller drivers */
-   #ifdef CONFIG_USB_OTG_UTILS
- ! extern struct otg_transceiver *otg_get_transceiver(int id);
-   extern void otg_put_transceiver(struct otg_transceiver *);
-   extern const char *otg_state_string(enum usb_otg_state state);
-   #else
- ! static inline struct otg_transceiver *otg_get_transceiver(int id)
-   {
-   	return NULL;
-   }
- diff -crN linux-3.2.1_o/include/linux/usb.h linux-3.2.1/include/linux/usb.h
- *** linux-3.2.1_o/include/linux/usb.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/include/linux/usb.h	2014-05-15 13:25:15.923329972 +0900
- ***************
- *** 1211,1216 ****
- --- 1211,1217 ----
-   	struct list_head urb_list;	/* list head for use by the urb's
-   					 * current owner */
-   	struct list_head anchor_list;	/* the URB may be anchored */
- + 	struct list_head giveback_list;	/* to postpone the giveback call */
-   	struct usb_anchor *anchor;
-   	struct usb_device *dev;		/* (in) pointer to associated device */
-   	struct usb_host_endpoint *ep;	/* (internal) pointer to endpoint */
- ***************
- *** 1221,1227 ****
-   	void *transfer_buffer;		/* (in) associated data buffer */
-   	dma_addr_t transfer_dma;	/* (in) dma addr for transfer_buffer */
-   	struct scatterlist *sg;		/* (in) scatter gather buffer list */
- - 	int num_mapped_sgs;		/* (internal) mapped sg entries */
-   	int num_sgs;			/* (in) number of entries in the sg list */
-   	u32 transfer_buffer_length;	/* (in) data buffer length */
-   	u32 actual_length;		/* (return) actual transfer length */
- --- 1222,1227 ----
- diff -crN linux-3.2.1_o/include/linux/vmalloc.h linux-3.2.1/include/linux/vmalloc.h
- *** linux-3.2.1_o/include/linux/vmalloc.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/include/linux/vmalloc.h	2014-05-15 13:25:15.927364699 +0900
- ***************
- *** 131,136 ****
- --- 131,137 ----
-    */
-   extern rwlock_t vmlist_lock;
-   extern struct vm_struct *vmlist;
- + extern __init void vm_area_add_early(struct vm_struct *vm);
-   extern __init void vm_area_register_early(struct vm_struct *vm, size_t align);
-   
-   #ifdef CONFIG_SMP
- diff -crN linux-3.2.1_o/include/linux/wl12xx.h linux-3.2.1/include/linux/wl12xx.h
- *** linux-3.2.1_o/include/linux/wl12xx.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/include/linux/wl12xx.h	2014-05-15 13:25:15.931300492 +0900
- ***************
- *** 54,59 ****
- --- 54,61 ----
-   	int board_ref_clock;
-   	int board_tcxo_clock;
-   	unsigned long platform_quirks;
- + 	int bt_enable_gpio;
- + 	int wlan_enable_gpio;
-   };
-   
-   /* Platform does not support level trigger interrupts */
- diff -crN linux-3.2.1_o/include/mtd/ckb_gpmc_cs1.h linux-3.2.1/include/mtd/ckb_gpmc_cs1.h
- *** linux-3.2.1_o/include/mtd/ckb_gpmc_cs1.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/include/mtd/ckb_gpmc_cs1.h	2014-05-15 13:25:15.935330706 +0900
- ***************
- *** 0 ****
- --- 1,58 ----
- + /*
- +  * Sharp LR35504 board : WRAM access header
- +  *
- +  * Copyright (C) 2013 Computex Co.Ltd.
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; version 2 of the License.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- +  *
- +  */
- + 
- + #ifndef __MTD_CKB_EMIF_CS5_H
- + #define __MTD_CKB_EMIF_CS5_H
- + 
- + #define CKB_GPMC_CS1_DEV_NAME			"gpmc_cs1"
- + #define CKB_GPMC_CS1_MAJOR				255
- + 
- + #define CKB_GPMC_CS1_BASE			0x09000000
- + 
- + /* Register offsets */
- + #define GPMC_CONFIG1_1	0x090
- + #define GPMC_CONFIG2_1	0x094
- + #define GPMC_CONFIG3_1	0x098
- + #define GPMC_CONFIG4_1	0x09c
- + #define GPMC_CONFIG5_1	0x0A0
- + #define GPMC_CONFIG6_1	0x0A4
- + #define GPMC_CONFIG7_1	0x0A8
- + 
- + 
- + #define DEVICESIZE_MASK		(0x3<<12)
- + 
- + 
- + struct ckb_gpmc_cs1_device {
- + 	struct platform_device *pdev;
- + 
- + 	unsigned long	phys_base;
- + 	unsigned long 	mem_size;
- + 	void __iomem	*mmio_base;
- + 	struct device *dev;
- + };
- + 
- + struct ckb_gpmc_cs1_dev {
- + 	struct ckb_gpmc_cs1_device *device;
- + };
- + 
- + #include  <mtd/ckb_gpmc_cs1_ioctl.h>
- + 
- + #endif /* __MTD_CKB_EMIF_CS5_H */
- + 
- diff -crN linux-3.2.1_o/include/mtd/ckb_gpmc_cs1_ioctl.h linux-3.2.1/include/mtd/ckb_gpmc_cs1_ioctl.h
- *** linux-3.2.1_o/include/mtd/ckb_gpmc_cs1_ioctl.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/include/mtd/ckb_gpmc_cs1_ioctl.h	2014-05-15 13:25:15.935330706 +0900
- ***************
- *** 0 ****
- --- 1,103 ----
- + /*
- +  * Sharp LR35504 board : WRAM access header
- +  *
- +  * Copyright (C) 2013 Computex Co.Ltd.
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; version 2 of the License.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- +  *
- +  */
- + 
- + #ifndef __MTD_CKB_EMIF_CS5_IOCTL_H
- + #define __MTD_CKB_EMIF_CS5_IOCTL_H
- + 
- + #define CKB_GPMC_CS1_IOCTL_SET_CONFIG1_REG 		_IOW('C', 1, int)
- + #define CKB_GPMC_CS1_IOCTL_GET_CONFIG1_REG 		_IOR('C', 2, int)
- + #define CKB_GPMC_CS1_IOCTL_SET_CONFIG2_REG 		_IOW('C', 3, int)
- + #define CKB_GPMC_CS1_IOCTL_GET_CONFIG2_REG 		_IOR('C', 4, int)
- + #define CKB_GPMC_CS1_IOCTL_SET_CONFIG3_REG 		_IOW('C', 5, int)
- + #define CKB_GPMC_CS1_IOCTL_GET_CONFIG3_REG 		_IOR('C', 6, int)
- + #define CKB_GPMC_CS1_IOCTL_SET_CONFIG4_REG 		_IOW('C', 7, int)
- + #define CKB_GPMC_CS1_IOCTL_GET_CONFIG4_REG 		_IOR('C', 8, int)
- + #define CKB_GPMC_CS1_IOCTL_SET_CONFIG5_REG 		_IOW('C', 9, int)
- + #define CKB_GPMC_CS1_IOCTL_GET_CONFIG5_REG 		_IOR('C', 10, int)
- + #define CKB_GPMC_CS1_IOCTL_SET_CONFIG6_REG 		_IOW('C', 11, int)
- + #define CKB_GPMC_CS1_IOCTL_GET_CONFIG6_REG 		_IOR('C', 12, int)
- + #define CKB_GPMC_CS1_IOCTL_SET_CONFIG7_REG 		_IOW('C', 13, int)
- + #define CKB_GPMC_CS1_IOCTL_GET_CONFIG7_REG 		_IOR('C', 14, int)
- + 
- + /* GPMC_CONFIG1 */
- + #define WRAPBURST				(0<<31)
- + #define READMULTIPLE			(0<<30)
- + #define READTYPE				(0<<29)
- + #define WRITEMULTIPLE			(0<<28)
- + #define WRITETYPE				(0<<27)
- + #define CLKACTIVATIONTIME		(0<<25)
- + #define ATTACHDDVICEPAGELENGTH	(0<<23)
- + #define WAITREADMONITORING		(0<<22)
- + #define WAITWRITEMONITORING		(0<<21)
- + #define WAITMONITORINGTIME		(0<<18)
- + #define WAITPINSELECT			(0<<16)
- + #define DEVICESIZE_8			(0x0<<12)
- + #define DEVICESIZE_16			(0x1<<12)
- + #define DEVICETYPE				(0x0<<10)
- + #define MUXADDDATA				(0x2<<8)
- + #define TIMEPARAGRANULARITY		(0<<4)
- + #define GPMCFCLKDIVIDER			0
- + 
- + /* GPMC_CONFIG2 */
- + #define CSWROFFTIME				(18<<16)
- + #define CSRDOFFTIME				(18<<8)
- + #define CEEXTRADELAY			(0<<7)
- + #define CSONTIME				1
- + 
- + /* GPMC_CONFIG3 */
- + #define ADVADMUXWROFFTIME		(0<<28)
- + #define ADVAADMUXRDOFFTIME		(0<<24)
- + #define ADVWROFFTIME			(5<<16)
- + #define ADVRDOFFTIME			(5<<8)
- + #define ADVEXTRADELAY			(0<<7)
- + #define ADVAADMUXONTIME			(0<<4)
- + #define ADVONTIME				2
- + 
- + /* GPMC_CONFIG4 */
- + #define WEOFFTIME				(16<<24)
- + #define WEEXTRADELAY			(0<<23)
- + #define WEONTIME				(8<<16)
- + #define OEAADMUXOFFTIME			(0<<13)
- + #define OEOFFTIME				(17<<8)
- + #define OEEXTRADELAY			(0<<7)
- + #define OEAADMUXONTIME			(0<<4)
- + #define OEONTIME				7
- + 	
- + /* GPMC_CONFIG5 */
- + #define PAGEBURSTACCESSTIME		(2<<24)
- + #define RDACCESSTIME			(16<<16)
- + #define WRCYCLETIME				(19<<8)
- + #define RDCYCLETIME				19 
- + 
- + /* GPMC_CONFIG6 */
- + #define WRACCESSTIME			(13 <<24)
- + #define WRDATAONADMUXBUS		(6 <<16)
- + #define CYCLE2CYCLEDELAY		(0<<8)
- + #define CYCLE2CYCLESAMECSEN		(0<<7)
- + #define CYCLE2CYCLEDIFFCSEN		(0<<6)
- + #define BUSTURNAROUND			1
- + 
- + /* GPMC_CONFIG7 */
- + #define MASKADDRESS				(0xF<<8)  		// 16MByte
- + #define CSVALID					(0x1<<6)
- + 
- + 
- + #endif /* __MTD_CKB_EMIF_CS5_IOCTL_H */
- + 
- diff -crN linux-3.2.1_o/include/video/ckb_dvi.h linux-3.2.1/include/video/ckb_dvi.h
- *** linux-3.2.1_o/include/video/ckb_dvi.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/include/video/ckb_dvi.h	2014-05-15 13:25:15.935330706 +0900
- ***************
- *** 0 ****
- --- 1,60 ----
- + /*
- +  * Header for CKB DVI driver
- +  *
- +  * Copyright (C) 2013 Computex Co.Ltd.
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; version 2 of the License.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- +  *
- +  */
- + 
- + #ifndef __CKB_DVI_H
- + #define __CKB_DVI_H
- + 
- + #define CKB_DVI_NAME			"ckb-dvi"
- + 
- + #include <linux/fb.h>
- + 
- + struct ckb_dvi_platform_data {
- + 	int max_xres;
- + 	int max_yres;
- + 	int connect_poll_interval;
- + 	int i2c_port;
- + };
- + 
- + struct ckb_dvi_device {
- + 	struct platform_device *pdev;
- + 	unsigned long	phys_base;
- + 	unsigned long 	mem_size;
- + 	struct device *dev;
- + 	struct workqueue_struct *wq;
- + 	struct work_struct pluggedin_work;
- + 	struct timer_list pluggedin_timer;
- + 	unsigned char connector_plugged;
- + 	struct ckb_dvi_platform_data *plat_data;
- + };
- + 
- + 
- + struct ckb_dvi_video_timings {
- + 	u16 x_res;
- + 	u16 y_res;
- + 	u16 hsw;	/* Horizontal synchronization pulse width */
- + 	u16 hfp;	/* Horizontal front porch */
- + 	u16 hbp;	/* Horizontal back porch */
- + 	u16 vsw;	/* Vertical synchronization pulse width */
- + 	u16 vfp;	/* Vertical front porch */
- + 	u16 vbp;	/* Vertical back porch */
- + };
- + 
- + int get_dvi_info(struct fb_info *info);
- + #endif /* __CKB_DVI_H */
- diff -crN linux-3.2.1_o/include/video/ckb_tfp410.h linux-3.2.1/include/video/ckb_tfp410.h
- *** linux-3.2.1_o/include/video/ckb_tfp410.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/include/video/ckb_tfp410.h	2014-05-15 13:25:15.935330706 +0900
- ***************
- *** 0 ****
- --- 1,49 ----
- + /*
- +  * Header for TFP410 I2C driver
- +  *
- +  * Copyright (C) 2013 Computex Co.Ltd.
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; version 2 of the License.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- +  *
- +  */
- + 
- + #ifndef __CKB_TFP410_H
- + #define __CKB_TFP410_H
- + 
- + struct omap_dss_device;
- + 
- + /**
- +  * struct tfp410_platform_data - panel driver configuration data
- +  * @i2c_bus_num: i2c bus id for the panel
- +  * @power_down_gpio: gpio number for PD pin (or -1 if not available)
- +  */
- + struct tfp410_platform_data {
- +        u16 i2c_bus_num;
- +        int power_down_gpio;
- + };
- + 
- + 
- + struct tfp410_priv {
- + 	 struct i2c_client *client;
- + 	 struct device *dev;
- + 	 struct tfp410_platform_data *pdata;
- + 	 bool (*tfp410_read)(int addr, uint8_t *ch);
- + 	 bool (*tfp410_write)(int addr, uint8_t ch);
- + 	 bool (*tfp410_isconnected)(void);
- + 	 struct i2c_adapter *(*get_i2c_adapter)(void);
- + };
- + 
- + struct tfp410_priv *get_current_tfp410_device(void);
- + 
- + #endif /* __CKB_TFP410_H */
- diff -crN linux-3.2.1_o/include/video/ckb_video_modes.h linux-3.2.1/include/video/ckb_video_modes.h
- *** linux-3.2.1_o/include/video/ckb_video_modes.h	1970-01-01 09:00:00.000000000 +0900
- --- linux-3.2.1/include/video/ckb_video_modes.h	2014-05-15 13:25:15.939272471 +0900
- ***************
- *** 0 ****
- --- 1,15 ----
- + #ifndef CKB_VIDEO_MODES_H
- + #define CKB_VIDEO_MODES_H
- + 
- + #define FBSET_DB_DIR			"/etc"
- + #define FBSET_DB_FILE			FBSET_DB_DIR"/fb.modes"
- + 
- + char create_video_mode_file(void);
- + void close_video_mode_file(void);
- + void append_video_mode(const char *name, __u32 xres, __u32 yres, char *duplicate, __u32 clockMhz,
- + 			__u32 pixclock, __u32 left_margin, __u32 right_margin, __u32 upper_margin, __u32 lower_margin,
- + 			__u32 hsync_len,  __u32 vsync_len, 	__u32 sync);
- + void append_fb_mode(void);
- + void set_fb_panel_info(struct da8xx_panel *da8xx_panels, int size, int bpp);
- + 
- + #endif
- diff -crN linux-3.2.1_o/include/video/da8xx-fb.h linux-3.2.1/include/video/da8xx-fb.h
- *** linux-3.2.1_o/include/video/da8xx-fb.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/include/video/da8xx-fb.h	2014-05-15 13:25:15.955285891 +0900
- ***************
- *** 13,19 ****
-   #define DA8XX_FB_H
-   
-   enum panel_type {
- ! 	QVGA = 0
-   };
-   
-   enum panel_shade {
- --- 13,20 ----
-   #define DA8XX_FB_H
-   
-   enum panel_type {
- ! 	QVGA = 0,
- ! 	WVGA,
-   };
-   
-   enum panel_shade {
- ***************
- *** 28,34 ****
-   };
-   
-   struct display_panel {
- ! 	enum panel_type panel_type; /* QVGA */
-   	int max_bpp;
-   	int min_bpp;
-   	enum panel_shade panel_shade;
- --- 29,35 ----
-   };
-   
-   struct display_panel {
- ! 	enum panel_type panel_type;
-   	int max_bpp;
-   	int min_bpp;
-   	enum panel_shade panel_shade;
- ***************
- *** 37,44 ****
-   struct da8xx_lcdc_platform_data {
-   	const char manu_name[10];
-   	void *controller_data;
- ! 	const char type[25];
-   	void (*panel_power_ctrl)(int);
-   };
-   
-   struct lcd_ctrl_config {
- --- 38,47 ----
-   struct da8xx_lcdc_platform_data {
-   	const char manu_name[10];
-   	void *controller_data;
- ! 	const char type[30];
-   	void (*panel_power_ctrl)(int);
- + 	unsigned long fb_mapped_physaddr;		/* Optional: FB mapped physical address */
- + 	unsigned long fb_mapped_len;			/* Optional: FB mapped length */
-   };
-   
-   struct lcd_ctrl_config {
- ***************
- *** 68,79 ****
-   	/* Mono 8-bit Mode: 1=D0-D7 or 0=D0-D3 */
-   	unsigned char mono_8bit_mode;
-   
- - 	/* Invert line clock */
- - 	unsigned char invert_line_clock;
- - 
- - 	/* Invert frame clock  */
- - 	unsigned char invert_frm_clock;
- - 
-   	/* Horizontal and Vertical Sync Edge: 0=rising 1=falling */
-   	unsigned char sync_edge;
-   
- --- 71,76 ----
- ***************
- *** 82,87 ****
- --- 79,87 ----
-   
-   	/* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
-   	unsigned char raster_order;
- + 
- + 	/* DMA FIFO threshold */
- + 	int fifo_th;
-   };
-   
-   struct lcd_sync_arg {
- ***************
- *** 90,95 ****
- --- 90,111 ----
-   	int pulse_width;
-   };
-   
- + 
- + struct da8xx_panel {
- + 	const char	name[30];	/* Full name <vendor>_<model> */
- + 	unsigned short	width;
- + 	unsigned short	height;
- + 	int		hfp;		/* Horizontal front porch */
- + 	int		hbp;		/* Horizontal back porch */
- + 	int		hsw;		/* Horizontal Sync Pulse Width */
- + 	int		vfp;		/* Vertical front porch */
- + 	int		vbp;		/* Vertical back porch */
- + 	int		vsw;		/* Vertical Sync Pulse Width */
- + 	unsigned int	pxl_clk;	/* Pixel clock */
- + 	unsigned char	sync;	/* Invert Pixel clock */
- + };
- + 
- + 
-   /* ioctls */
-   #define FBIOGET_CONTRAST	_IOR('F', 1, int)
-   #define FBIOPUT_CONTRAST	_IOW('F', 2, int)
- ***************
- *** 100,104 ****
- --- 116,127 ----
-   #define FBIPUT_HSYNC		_IOW('F', 9, int)
-   #define FBIPUT_VSYNC		_IOW('F', 10, int)
-   
- + /* Proprietary FB_SYNC_ flags */
- + #define FB_SYNC_CLK_INVERT 0x40000000
- + 
- + typedef void (*vsync_callback_t)(void *arg);
- + int register_vsync_cb(vsync_callback_t handler, void *arg, int idx);
- + int unregister_vsync_cb(vsync_callback_t handler, void *arg, int idx);
- + 
-   #endif  /* ifndef DA8XX_FB_H */
-   
- diff -crN linux-3.2.1_o/kernel/cgroup.c linux-3.2.1/kernel/cgroup.c
- *** linux-3.2.1_o/kernel/cgroup.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/kernel/cgroup.c	2014-05-15 13:25:15.991280081 +0900
- ***************
- *** 1175,1184 ****
-   
-   	/*
-   	 * If the 'all' option was specified select all the subsystems,
- ! 	 * otherwise if 'none', 'name=' and a subsystem name options
- ! 	 * were not specified, let's default to 'all'
-   	 */
- ! 	if (all_ss || (!one_ss && !opts->none && !opts->name)) {
-   		for (i = 0; i < CGROUP_SUBSYS_COUNT; i++) {
-   			struct cgroup_subsys *ss = subsys[i];
-   			if (ss == NULL)
- --- 1175,1184 ----
-   
-   	/*
-   	 * If the 'all' option was specified select all the subsystems,
- ! 	 * otherwise 'all, 'none' and a subsystem name options were not
- ! 	 * specified, let's default to 'all'
-   	 */
- ! 	if (all_ss || (!all_ss && !one_ss && !opts->none)) {
-   		for (i = 0; i < CGROUP_SUBSYS_COUNT; i++) {
-   			struct cgroup_subsys *ss = subsys[i];
-   			if (ss == NULL)
- diff -crN linux-3.2.1_o/kernel/exit.c linux-3.2.1/kernel/exit.c
- *** linux-3.2.1_o/kernel/exit.c	2014-05-15 09:39:09.857054710 +0900
- --- linux-3.2.1/kernel/exit.c	2014-05-15 13:25:16.011328477 +0900
- ***************
- *** 937,944 ****
-   		schedule();
-   	}
-   
- - 	exit_irq_thread();
- - 
-   	exit_signals(tsk);  /* sets PF_EXITING */
-   	/*
-   	 * tsk->flags are checked in the futex code to protect against
- --- 937,942 ----
- ***************
- *** 947,952 ****
- --- 945,952 ----
-   	smp_mb();
-   	raw_spin_unlock_wait(&tsk->pi_lock);
-   
- + 	exit_irq_thread();
- + 
-   	if (unlikely(in_atomic()))
-   		printk(KERN_INFO "note: %s[%d] exited with preempt_count %d\n",
-   				current->comm, task_pid_nr(current),
- diff -crN linux-3.2.1_o/kernel/irq/autoprobe.c linux-3.2.1/kernel/irq/autoprobe.c
- *** linux-3.2.1_o/kernel/irq/autoprobe.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/kernel/irq/autoprobe.c	2014-05-15 13:25:16.050904626 +0900
- ***************
- *** 53,59 ****
-   			if (desc->irq_data.chip->irq_set_type)
-   				desc->irq_data.chip->irq_set_type(&desc->irq_data,
-   							 IRQ_TYPE_PROBE);
- ! 			irq_startup(desc);
-   		}
-   		raw_spin_unlock_irq(&desc->lock);
-   	}
- --- 53,59 ----
-   			if (desc->irq_data.chip->irq_set_type)
-   				desc->irq_data.chip->irq_set_type(&desc->irq_data,
-   							 IRQ_TYPE_PROBE);
- ! 			irq_startup(desc, false);
-   		}
-   		raw_spin_unlock_irq(&desc->lock);
-   	}
- ***************
- *** 70,76 ****
-   		raw_spin_lock_irq(&desc->lock);
-   		if (!desc->action && irq_settings_can_probe(desc)) {
-   			desc->istate |= IRQS_AUTODETECT | IRQS_WAITING;
- ! 			if (irq_startup(desc))
-   				desc->istate |= IRQS_PENDING;
-   		}
-   		raw_spin_unlock_irq(&desc->lock);
- --- 70,76 ----
-   		raw_spin_lock_irq(&desc->lock);
-   		if (!desc->action && irq_settings_can_probe(desc)) {
-   			desc->istate |= IRQS_AUTODETECT | IRQS_WAITING;
- ! 			if (irq_startup(desc, false))
-   				desc->istate |= IRQS_PENDING;
-   		}
-   		raw_spin_unlock_irq(&desc->lock);
- diff -crN linux-3.2.1_o/kernel/irq/chip.c linux-3.2.1/kernel/irq/chip.c
- *** linux-3.2.1_o/kernel/irq/chip.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/kernel/irq/chip.c	2014-05-15 13:25:16.059349521 +0900
- ***************
- *** 157,175 ****
-   	irqd_set(&desc->irq_data, IRQD_IRQ_MASKED);
-   }
-   
- ! int irq_startup(struct irq_desc *desc)
-   {
-   	irq_state_clr_disabled(desc);
-   	desc->depth = 0;
-   
-   	if (desc->irq_data.chip->irq_startup) {
- ! 		int ret = desc->irq_data.chip->irq_startup(&desc->irq_data);
-   		irq_state_clr_masked(desc);
- ! 		return ret;
-   	}
- ! 
- ! 	irq_enable(desc);
- ! 	return 0;
-   }
-   
-   void irq_shutdown(struct irq_desc *desc)
- --- 157,178 ----
-   	irqd_set(&desc->irq_data, IRQD_IRQ_MASKED);
-   }
-   
- ! int irq_startup(struct irq_desc *desc, bool resend)
-   {
- + 	int ret = 0;
- + 
-   	irq_state_clr_disabled(desc);
-   	desc->depth = 0;
-   
-   	if (desc->irq_data.chip->irq_startup) {
- ! 		ret = desc->irq_data.chip->irq_startup(&desc->irq_data);
-   		irq_state_clr_masked(desc);
- ! 	} else {
- ! 		irq_enable(desc);
-   	}
- ! 	if (resend)
- ! 		check_irq_resend(desc, desc->irq_data.irq);
- ! 	return ret;
-   }
-   
-   void irq_shutdown(struct irq_desc *desc)
- ***************
- *** 625,631 ****
-   		irq_settings_set_noprobe(desc);
-   		irq_settings_set_norequest(desc);
-   		irq_settings_set_nothread(desc);
- ! 		irq_startup(desc);
-   	}
-   out:
-   	irq_put_desc_busunlock(desc, flags);
- --- 628,634 ----
-   		irq_settings_set_noprobe(desc);
-   		irq_settings_set_norequest(desc);
-   		irq_settings_set_nothread(desc);
- ! 		irq_startup(desc, true);
-   	}
-   out:
-   	irq_put_desc_busunlock(desc, flags);
- diff -crN linux-3.2.1_o/kernel/irq/handle.c linux-3.2.1/kernel/irq/handle.c
- *** linux-3.2.1_o/kernel/irq/handle.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/kernel/irq/handle.c	2014-05-15 13:25:16.063359769 +0900
- ***************
- *** 60,66 ****
-   	 * device interrupt, so no irq storm is lurking. If the
-   	 * RUNTHREAD bit is already set, nothing to do.
-   	 */
- ! 	if (test_bit(IRQTF_DIED, &action->thread_flags) ||
-   	    test_and_set_bit(IRQTF_RUNTHREAD, &action->thread_flags))
-   		return;
-   
- --- 60,66 ----
-   	 * device interrupt, so no irq storm is lurking. If the
-   	 * RUNTHREAD bit is already set, nothing to do.
-   	 */
- ! 	if ((action->thread->flags & PF_EXITING) ||
-   	    test_and_set_bit(IRQTF_RUNTHREAD, &action->thread_flags))
-   		return;
-   
- ***************
- *** 110,115 ****
- --- 110,127 ----
-   	 * threads_oneshot untouched and runs the thread another time.
-   	 */
-   	desc->threads_oneshot |= action->thread_mask;
- + 
- + 	/*
- + 	 * We increment the threads_active counter in case we wake up
- + 	 * the irq thread. The irq thread decrements the counter when
- + 	 * it returns from the handler or in the exit path and wakes
- + 	 * up waiters which are stuck in synchronize_irq() when the
- + 	 * active count becomes zero. synchronize_irq() is serialized
- + 	 * against this code (hard irq handler) via IRQS_INPROGRESS
- + 	 * like the finalize_oneshot() code. See comment above.
- + 	 */
- + 	atomic_inc(&desc->threads_active);
- + 
-   	wake_up_process(action->thread);
-   }
-   
- diff -crN linux-3.2.1_o/kernel/irq/internals.h linux-3.2.1/kernel/irq/internals.h
- *** linux-3.2.1_o/kernel/irq/internals.h	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/kernel/irq/internals.h	2014-05-15 13:25:16.067293986 +0900
- ***************
- *** 20,33 ****
-   /*
-    * Bits used by threaded handlers:
-    * IRQTF_RUNTHREAD - signals that the interrupt handler thread should run
- -  * IRQTF_DIED      - handler thread died
-    * IRQTF_WARNED    - warning "IRQ_WAKE_THREAD w/o thread_fn" has been printed
-    * IRQTF_AFFINITY  - irq thread is requested to adjust affinity
-    * IRQTF_FORCED_THREAD  - irq action is force threaded
-    */
-   enum {
-   	IRQTF_RUNTHREAD,
- - 	IRQTF_DIED,
-   	IRQTF_WARNED,
-   	IRQTF_AFFINITY,
-   	IRQTF_FORCED_THREAD,
- --- 20,31 ----
- ***************
- *** 67,73 ****
-   extern void __disable_irq(struct irq_desc *desc, unsigned int irq, bool susp);
-   extern void __enable_irq(struct irq_desc *desc, unsigned int irq, bool resume);
-   
- ! extern int irq_startup(struct irq_desc *desc);
-   extern void irq_shutdown(struct irq_desc *desc);
-   extern void irq_enable(struct irq_desc *desc);
-   extern void irq_disable(struct irq_desc *desc);
- --- 65,71 ----
-   extern void __disable_irq(struct irq_desc *desc, unsigned int irq, bool susp);
-   extern void __enable_irq(struct irq_desc *desc, unsigned int irq, bool resume);
-   
- ! extern int irq_startup(struct irq_desc *desc, bool resend);
-   extern void irq_shutdown(struct irq_desc *desc);
-   extern void irq_enable(struct irq_desc *desc);
-   extern void irq_disable(struct irq_desc *desc);
- diff -crN linux-3.2.1_o/kernel/irq/manage.c linux-3.2.1/kernel/irq/manage.c
- *** linux-3.2.1_o/kernel/irq/manage.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/kernel/irq/manage.c	2014-05-15 13:25:16.083305732 +0900
- ***************
- *** 645,651 ****
-    * is marked MASKED.
-    */
-   static void irq_finalize_oneshot(struct irq_desc *desc,
- ! 				 struct irqaction *action, bool force)
-   {
-   	if (!(desc->istate & IRQS_ONESHOT))
-   		return;
- --- 645,651 ----
-    * is marked MASKED.
-    */
-   static void irq_finalize_oneshot(struct irq_desc *desc,
- ! 				 struct irqaction *action)
-   {
-   	if (!(desc->istate & IRQS_ONESHOT))
-   		return;
- ***************
- *** 679,685 ****
-   	 * we would clear the threads_oneshot bit of this thread which
-   	 * was just set.
-   	 */
- ! 	if (!force && test_bit(IRQTF_RUNTHREAD, &action->thread_flags))
-   		goto out_unlock;
-   
-   	desc->threads_oneshot &= ~action->thread_mask;
- --- 679,685 ----
-   	 * we would clear the threads_oneshot bit of this thread which
-   	 * was just set.
-   	 */
- ! 	if (test_bit(IRQTF_RUNTHREAD, &action->thread_flags))
-   		goto out_unlock;
-   
-   	desc->threads_oneshot &= ~action->thread_mask;
- ***************
- *** 739,745 ****
-   
-   	local_bh_disable();
-   	ret = action->thread_fn(action->irq, action->dev_id);
- ! 	irq_finalize_oneshot(desc, action, false);
-   	local_bh_enable();
-   	return ret;
-   }
- --- 739,745 ----
-   
-   	local_bh_disable();
-   	ret = action->thread_fn(action->irq, action->dev_id);
- ! 	irq_finalize_oneshot(desc, action);
-   	local_bh_enable();
-   	return ret;
-   }
- ***************
- *** 755,764 ****
-   	irqreturn_t ret;
-   
-   	ret = action->thread_fn(action->irq, action->dev_id);
- ! 	irq_finalize_oneshot(desc, action, false);
-   	return ret;
-   }
-   
-   /*
-    * Interrupt handler thread
-    */
- --- 755,771 ----
-   	irqreturn_t ret;
-   
-   	ret = action->thread_fn(action->irq, action->dev_id);
- ! 	irq_finalize_oneshot(desc, action);
-   	return ret;
-   }
-   
- + static void wake_threads_waitq(struct irq_desc *desc)
- + {
- + 	if (atomic_dec_and_test(&desc->threads_active) &&
- + 	    waitqueue_active(&desc->wait_for_threads))
- + 		wake_up(&desc->wait_for_threads);
- + }
- + 
-   /*
-    * Interrupt handler thread
-    */
- ***************
- *** 771,827 ****
-   	struct irq_desc *desc = irq_to_desc(action->irq);
-   	irqreturn_t (*handler_fn)(struct irq_desc *desc,
-   			struct irqaction *action);
- - 	int wake;
-   
- ! 	if (force_irqthreads & test_bit(IRQTF_FORCED_THREAD,
-   					&action->thread_flags))
-   		handler_fn = irq_forced_thread_fn;
-   	else
-   		handler_fn = irq_thread_fn;
-   
-   	sched_setscheduler(current, SCHED_FIFO, &param);
- ! 	current->irqaction = action;
-   
-   	while (!irq_wait_for_interrupt(action)) {
-   
-   		irq_thread_check_affinity(desc, action);
-   
- ! 		atomic_inc(&desc->threads_active);
- ! 
- ! 		raw_spin_lock_irq(&desc->lock);
- ! 		if (unlikely(irqd_irq_disabled(&desc->irq_data))) {
- ! 			/*
- ! 			 * CHECKME: We might need a dedicated
- ! 			 * IRQ_THREAD_PENDING flag here, which
- ! 			 * retriggers the thread in check_irq_resend()
- ! 			 * but AFAICT IRQS_PENDING should be fine as it
- ! 			 * retriggers the interrupt itself --- tglx
- ! 			 */
- ! 			desc->istate |= IRQS_PENDING;
- ! 			raw_spin_unlock_irq(&desc->lock);
- ! 		} else {
- ! 			irqreturn_t action_ret;
- ! 
- ! 			raw_spin_unlock_irq(&desc->lock);
- ! 			action_ret = handler_fn(desc, action);
- ! 			if (!noirqdebug)
- ! 				note_interrupt(action->irq, desc, action_ret);
- ! 		}
- ! 
- ! 		wake = atomic_dec_and_test(&desc->threads_active);
-   
- ! 		if (wake && waitqueue_active(&desc->wait_for_threads))
- ! 			wake_up(&desc->wait_for_threads);
-   	}
-   
- - 	/* Prevent a stale desc->threads_oneshot */
- - 	irq_finalize_oneshot(desc, action, true);
- - 
-   	/*
- ! 	 * Clear irqaction. Otherwise exit_irq_thread() would make
-   	 * fuzz about an active irq thread going into nirvana.
-   	 */
- ! 	current->irqaction = NULL;
-   	return 0;
-   }
-   
- --- 778,818 ----
-   	struct irq_desc *desc = irq_to_desc(action->irq);
-   	irqreturn_t (*handler_fn)(struct irq_desc *desc,
-   			struct irqaction *action);
-   
- ! 	if (force_irqthreads && test_bit(IRQTF_FORCED_THREAD,
-   					&action->thread_flags))
-   		handler_fn = irq_forced_thread_fn;
-   	else
-   		handler_fn = irq_thread_fn;
-   
-   	sched_setscheduler(current, SCHED_FIFO, &param);
- ! 	current->irq_thread = 1;
-   
-   	while (!irq_wait_for_interrupt(action)) {
- + 		irqreturn_t action_ret;
-   
-   		irq_thread_check_affinity(desc, action);
-   
- ! 		action_ret = handler_fn(desc, action);
- ! 		if (!noirqdebug)
- ! 			note_interrupt(action->irq, desc, action_ret);
-   
- ! 		wake_threads_waitq(desc);
-   	}
-   
-   	/*
- ! 	 * This is the regular exit path. __free_irq() is stopping the
- ! 	 * thread via kthread_stop() after calling
- ! 	 * synchronize_irq(). So neither IRQTF_RUNTHREAD nor the
- ! 	 * oneshot mask bit can be set. We cannot verify that as we
- ! 	 * cannot touch the oneshot mask at this point anymore as
- ! 	 * __setup_irq() might have given out currents thread_mask
- ! 	 * again.
- ! 	 *
- ! 	 * Clear irq_thread. Otherwise exit_irq_thread() would make
-   	 * fuzz about an active irq thread going into nirvana.
-   	 */
- ! 	current->irq_thread = 0;
-   	return 0;
-   }
-   
- ***************
- *** 832,858 ****
-   {
-   	struct task_struct *tsk = current;
-   	struct irq_desc *desc;
-   
- ! 	if (!tsk->irqaction)
-   		return;
-   
-   	printk(KERN_ERR
-   	       "exiting task \"%s\" (%d) is an active IRQ thread (irq %d)\n",
- ! 	       tsk->comm ? tsk->comm : "", tsk->pid, tsk->irqaction->irq);
-   
- ! 	desc = irq_to_desc(tsk->irqaction->irq);
-   
-   	/*
- ! 	 * Prevent a stale desc->threads_oneshot. Must be called
- ! 	 * before setting the IRQTF_DIED flag.
-   	 */
- ! 	irq_finalize_oneshot(desc, tsk->irqaction, true);
-   
- ! 	/*
- ! 	 * Set the THREAD DIED flag to prevent further wakeups of the
- ! 	 * soon to be gone threaded handler.
- ! 	 */
- ! 	set_bit(IRQTF_DIED, &tsk->irqaction->flags);
-   }
-   
-   static void irq_setup_forced_threading(struct irqaction *new)
- --- 823,850 ----
-   {
-   	struct task_struct *tsk = current;
-   	struct irq_desc *desc;
- + 	struct irqaction *action;
-   
- ! 	if (!tsk->irq_thread)
-   		return;
-   
- + 	action = kthread_data(tsk);
- + 
-   	printk(KERN_ERR
-   	       "exiting task \"%s\" (%d) is an active IRQ thread (irq %d)\n",
- ! 	       tsk->comm ? tsk->comm : "", tsk->pid, action->irq);
-   
- ! 	desc = irq_to_desc(action->irq);
-   
-   	/*
- ! 	 * If IRQTF_RUNTHREAD is set, we need to decrement
- ! 	 * desc->threads_active and wake possible waiters.
-   	 */
- ! 	if (test_and_clear_bit(IRQTF_RUNTHREAD, &action->thread_flags))
- ! 		wake_threads_waitq(desc);
-   
- ! 	/* Prevent a stale desc->threads_oneshot */
- ! 	irq_finalize_oneshot(desc, action);
-   }
-   
-   static void irq_setup_forced_threading(struct irqaction *new)
- ***************
- *** 985,990 ****
- --- 977,987 ----
-   
-   		/* add new interrupt at end of irq queue */
-   		do {
- + 			/*
- + 			 * Or all existing action->thread_mask bits,
- + 			 * so we can find the next zero bit for this
- + 			 * new action.
- + 			 */
-   			thread_mask |= old->thread_mask;
-   			old_ptr = &old->next;
-   			old = *old_ptr;
- ***************
- *** 993,1006 ****
-   	}
-   
-   	/*
- ! 	 * Setup the thread mask for this irqaction. Unlikely to have
- ! 	 * 32 resp 64 irqs sharing one line, but who knows.
-   	 */
- ! 	if (new->flags & IRQF_ONESHOT && thread_mask == ~0UL) {
- ! 		ret = -EBUSY;
- ! 		goto out_mask;
-   	}
- - 	new->thread_mask = 1 << ffz(thread_mask);
-   
-   	if (!shared) {
-   		init_waitqueue_head(&desc->wait_for_threads);
- --- 990,1030 ----
-   	}
-   
-   	/*
- ! 	 * Setup the thread mask for this irqaction for ONESHOT. For
- ! 	 * !ONESHOT irqs the thread mask is 0 so we can avoid a
- ! 	 * conditional in irq_wake_thread().
-   	 */
- ! 	if (new->flags & IRQF_ONESHOT) {
- ! 		/*
- ! 		 * Unlikely to have 32 resp 64 irqs sharing one line,
- ! 		 * but who knows.
- ! 		 */
- ! 		if (thread_mask == ~0UL) {
- ! 			ret = -EBUSY;
- ! 			goto out_mask;
- ! 		}
- ! 		/*
- ! 		 * The thread_mask for the action is or'ed to
- ! 		 * desc->thread_active to indicate that the
- ! 		 * IRQF_ONESHOT thread handler has been woken, but not
- ! 		 * yet finished. The bit is cleared when a thread
- ! 		 * completes. When all threads of a shared interrupt
- ! 		 * line have completed desc->threads_active becomes
- ! 		 * zero and the interrupt line is unmasked. See
- ! 		 * handle.c:irq_wake_thread() for further information.
- ! 		 *
- ! 		 * If no thread is woken by primary (hard irq context)
- ! 		 * interrupt handlers, then desc->threads_active is
- ! 		 * also checked for zero to unmask the irq line in the
- ! 		 * affected hard irq flow handlers
- ! 		 * (handle_[fasteoi|level]_irq).
- ! 		 *
- ! 		 * The new action gets the first zero bit of
- ! 		 * thread_mask assigned. See the loop above which or's
- ! 		 * all existing action->thread_mask bits.
- ! 		 */
- ! 		new->thread_mask = 1 << ffz(thread_mask);
-   	}
-   
-   	if (!shared) {
-   		init_waitqueue_head(&desc->wait_for_threads);
- ***************
- *** 1027,1033 ****
-   			desc->istate |= IRQS_ONESHOT;
-   
-   		if (irq_settings_can_autoenable(desc))
- ! 			irq_startup(desc);
-   		else
-   			/* Undo nested disables: */
-   			desc->depth = 1;
- --- 1051,1057 ----
-   			desc->istate |= IRQS_ONESHOT;
-   
-   		if (irq_settings_can_autoenable(desc))
- ! 			irq_startup(desc, true);
-   		else
-   			/* Undo nested disables: */
-   			desc->depth = 1;
- ***************
- *** 1103,1110 ****
-   		struct task_struct *t = new->thread;
-   
-   		new->thread = NULL;
- ! 		if (likely(!test_bit(IRQTF_DIED, &new->thread_flags)))
- ! 			kthread_stop(t);
-   		put_task_struct(t);
-   	}
-   out_mput:
- --- 1127,1133 ----
-   		struct task_struct *t = new->thread;
-   
-   		new->thread = NULL;
- ! 		kthread_stop(t);
-   		put_task_struct(t);
-   	}
-   out_mput:
- ***************
- *** 1214,1221 ****
-   #endif
-   
-   	if (action->thread) {
- ! 		if (!test_bit(IRQTF_DIED, &action->thread_flags))
- ! 			kthread_stop(action->thread);
-   		put_task_struct(action->thread);
-   	}
-   
- --- 1237,1243 ----
-   #endif
-   
-   	if (action->thread) {
- ! 		kthread_stop(action->thread);
-   		put_task_struct(action->thread);
-   	}
-   
- diff -crN linux-3.2.1_o/kernel/pid.c linux-3.2.1/kernel/pid.c
- *** linux-3.2.1_o/kernel/pid.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/kernel/pid.c	2014-05-15 13:25:16.091355683 +0900
- ***************
- *** 428,433 ****
- --- 428,434 ----
-   {
-   	return find_task_by_pid_ns(vnr, current->nsproxy->pid_ns);
-   }
- + EXPORT_SYMBOL(find_task_by_vpid);
-   
-   struct pid *get_task_pid(struct task_struct *task, enum pid_type type)
-   {
- diff -crN linux-3.2.1_o/mm/vmalloc.c linux-3.2.1/mm/vmalloc.c
- *** linux-3.2.1_o/mm/vmalloc.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/mm/vmalloc.c	2014-05-15 13:25:16.107341631 +0900
- ***************
- *** 1118,1123 ****
- --- 1118,1149 ----
-   EXPORT_SYMBOL(vm_map_ram);
-   
-   /**
- +  * vm_area_add_early - add vmap area early during boot
- +  * @vm: vm_struct to add
- +  *
- +  * This function is used to add fixed kernel vm area to vmlist before
- +  * vmalloc_init() is called.  @vm->addr, @vm->size, and @vm->flags
- +  * should contain proper values and the other fields should be zero.
- +  *
- +  * DO NOT USE THIS FUNCTION UNLESS YOU KNOW WHAT YOU'RE DOING.
- +  */
- + void __init vm_area_add_early(struct vm_struct *vm)
- + {
- + 	struct vm_struct *tmp, **p;
- + 
- + 	BUG_ON(vmap_initialized);
- + 	for (p = &vmlist; (tmp = *p) != NULL; p = &tmp->next) {
- + 		if (tmp->addr >= vm->addr) {
- + 			BUG_ON(tmp->addr < vm->addr + vm->size);
- + 			break;
- + 		} else
- + 			BUG_ON(tmp->addr + tmp->size > vm->addr);
- + 	}
- + 	vm->next = *p;
- + 	*p = vm;
- + }
- + 
- + /**
-    * vm_area_register_early - register vmap area early during boot
-    * @vm: vm_struct to register
-    * @align: requested alignment
- ***************
- *** 1139,1146 ****
-   
-   	vm->addr = (void *)addr;
-   
- ! 	vm->next = vmlist;
- ! 	vmlist = vm;
-   }
-   
-   void __init vmalloc_init(void)
- --- 1165,1171 ----
-   
-   	vm->addr = (void *)addr;
-   
- ! 	vm_area_add_early(vm);
-   }
-   
-   void __init vmalloc_init(void)
- diff -crN linux-3.2.1_o/net/sched/sch_generic.c linux-3.2.1/net/sched/sch_generic.c
- *** linux-3.2.1_o/net/sched/sch_generic.c	2012-01-13 04:42:45.000000000 +0900
- --- linux-3.2.1/net/sched/sch_generic.c	2014-05-15 13:25:16.119272621 +0900
- ***************
- *** 251,258 ****
- --- 251,260 ----
-   			}
-   
-   			if (some_queue_timedout) {
- + #ifndef CONFIG_MACH_CKB_3352
-   				WARN_ONCE(1, KERN_INFO "NETDEV WATCHDOG: %s (%s): transmit queue %u timed out\n",
-   				       dev->name, netdev_drivername(dev), i);
- + #endif
-   				dev->netdev_ops->ndo_tx_timeout(dev);
-   			}
-   			if (!mod_timer(&dev->watchdog_timer,
--- 0 ----
diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-3352/patches/linux-3.2.1-001-20141126.patch buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-3352/patches/linux-3.2.1-001-20141126.patch
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-3352/patches/linux-3.2.1-001-20141126.patch	1970-01-01 09:00:00.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-3352/patches/linux-3.2.1-001-20141126.patch	2014-11-26 18:45:30.000000000 +0900
***************
*** 0 ****
--- 1,106701 ----
+ diff -crN linux-3.2.1_o/arch/arm/common/edma.c linux-3.2.1/arch/arm/common/edma.c
+ *** linux-3.2.1_o/arch/arm/common/edma.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/common/edma.c	2014-11-25 13:19:14.615064578 +0900
+ ***************
+ *** 0 ****
+ --- 1,1741 ----
+ + /*
+ +  * EDMA3 Driver
+ +  *
+ +  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + #include <linux/kernel.h>
+ + #include <linux/init.h>
+ + #include <linux/module.h>
+ + #include <linux/interrupt.h>
+ + #include <linux/platform_device.h>
+ + #include <linux/slab.h>
+ + #include <linux/io.h>
+ + #include <linux/err.h>
+ + #include <linux/pm_runtime.h>
+ + 
+ + #include <mach/edma.h>
+ + 
+ + /* Offsets matching "struct edmacc_param" */
+ + #define PARM_OPT		0x00
+ + #define PARM_SRC		0x04
+ + #define PARM_A_B_CNT		0x08
+ + #define PARM_DST		0x0c
+ + #define PARM_SRC_DST_BIDX	0x10
+ + #define PARM_LINK_BCNTRLD	0x14
+ + #define PARM_SRC_DST_CIDX	0x18
+ + #define PARM_CCNT		0x1c
+ + 
+ + #define PARM_SIZE		0x20
+ + 
+ + /* Offsets for EDMA CC global channel registers and their shadows */
+ + #define SH_ER		0x00	/* 64 bits */
+ + #define SH_ECR		0x08	/* 64 bits */
+ + #define SH_ESR		0x10	/* 64 bits */
+ + #define SH_CER		0x18	/* 64 bits */
+ + #define SH_EER		0x20	/* 64 bits */
+ + #define SH_EECR		0x28	/* 64 bits */
+ + #define SH_EESR		0x30	/* 64 bits */
+ + #define SH_SER		0x38	/* 64 bits */
+ + #define SH_SECR		0x40	/* 64 bits */
+ + #define SH_IER		0x50	/* 64 bits */
+ + #define SH_IECR		0x58	/* 64 bits */
+ + #define SH_IESR		0x60	/* 64 bits */
+ + #define SH_IPR		0x68	/* 64 bits */
+ + #define SH_ICR		0x70	/* 64 bits */
+ + #define SH_IEVAL	0x78
+ + #define SH_QER		0x80
+ + #define SH_QEER		0x84
+ + #define SH_QEECR	0x88
+ + #define SH_QEESR	0x8c
+ + #define SH_QSER		0x90
+ + #define SH_QSECR	0x94
+ + #define SH_SIZE		0x200
+ + 
+ + /* Offsets for EDMA CC global registers */
+ + #define EDMA_REV	0x0000
+ + #define EDMA_CCCFG	0x0004
+ + #define EDMA_QCHMAP	0x0200	/* 8 registers */
+ + #define EDMA_DMAQNUM	0x0240	/* 8 registers (4 on OMAP-L1xx) */
+ + #define EDMA_QDMAQNUM	0x0260
+ + #define EDMA_QUETCMAP	0x0280
+ + #define EDMA_QUEPRI	0x0284
+ + #define EDMA_EMR	0x0300	/* 64 bits */
+ + #define EDMA_EMCR	0x0308	/* 64 bits */
+ + #define EDMA_QEMR	0x0310
+ + #define EDMA_QEMCR	0x0314
+ + #define EDMA_CCERR	0x0318
+ + #define EDMA_CCERRCLR	0x031c
+ + #define EDMA_EEVAL	0x0320
+ + #define EDMA_DRAE	0x0340	/* 4 x 64 bits*/
+ + #define EDMA_QRAE	0x0380	/* 4 registers */
+ + #define EDMA_QUEEVTENTRY	0x0400	/* 2 x 16 registers */
+ + #define EDMA_QSTAT	0x0600	/* 2 registers */
+ + #define EDMA_QWMTHRA	0x0620
+ + #define EDMA_QWMTHRB	0x0624
+ + #define EDMA_CCSTAT	0x0640
+ + 
+ + #define EDMA_M		0x1000	/* global channel registers */
+ + #define EDMA_ECR	0x1008
+ + #define EDMA_ECRH	0x100C
+ + #define EDMA_SHADOW0	0x2000	/* 4 regions shadowing global channels */
+ + #define EDMA_PARM	0x4000	/* 128 param entries */
+ + 
+ + #define PARM_OFFSET(param_no)	(EDMA_PARM + ((param_no) << 5))
+ + 
+ + #define EDMA_DCHMAP	0x0100  /* 64 registers */
+ + #define CHMAP_EXIST	BIT(24)
+ + 
+ + 
+ + /*function that maps the cross bar events to channels */
+ + int (*xbar_event_to_channel_map)(unsigned event, unsigned *channel,
+ + 			struct event_to_channel_map *xbar_event_map) = NULL;
+ + 
+ + /*****************************************************************************/
+ + 
+ + static void __iomem *edmacc_regs_base[EDMA_MAX_CC];
+ + 
+ + static inline unsigned int edma_read(unsigned ctlr, int offset)
+ + {
+ + 	return (unsigned int)__raw_readl(edmacc_regs_base[ctlr] + offset);
+ + }
+ + 
+ + static inline void edma_write(unsigned ctlr, int offset, int val)
+ + {
+ + 	__raw_writel(val, edmacc_regs_base[ctlr] + offset);
+ + }
+ + static inline void edma_modify(unsigned ctlr, int offset, unsigned and,
+ + 		unsigned or)
+ + {
+ + 	unsigned val = edma_read(ctlr, offset);
+ + 	val &= and;
+ + 	val |= or;
+ + 	edma_write(ctlr, offset, val);
+ + }
+ + static inline void edma_and(unsigned ctlr, int offset, unsigned and)
+ + {
+ + 	unsigned val = edma_read(ctlr, offset);
+ + 	val &= and;
+ + 	edma_write(ctlr, offset, val);
+ + }
+ + static inline void edma_or(unsigned ctlr, int offset, unsigned or)
+ + {
+ + 	unsigned val = edma_read(ctlr, offset);
+ + 	val |= or;
+ + 	edma_write(ctlr, offset, val);
+ + }
+ + static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i)
+ + {
+ + 	return edma_read(ctlr, offset + (i << 2));
+ + }
+ + static inline unsigned int edma_read_array2(unsigned ctlr, int offset, int i,
+ + 		int j)
+ + {
+ + 	return edma_read(ctlr, offset + ((i*2 + j) << 2));
+ + }
+ + static inline void edma_write_array(unsigned ctlr, int offset, int i,
+ + 		unsigned val)
+ + {
+ + 	edma_write(ctlr, offset + (i << 2), val);
+ + }
+ + static inline void edma_modify_array(unsigned ctlr, int offset, int i,
+ + 		unsigned and, unsigned or)
+ + {
+ + 	edma_modify(ctlr, offset + (i << 2), and, or);
+ + }
+ + static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or)
+ + {
+ + 	edma_or(ctlr, offset + (i << 2), or);
+ + }
+ + static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j,
+ + 		unsigned or)
+ + {
+ + 	edma_or(ctlr, offset + ((i*2 + j) << 2), or);
+ + }
+ + static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j,
+ + 		unsigned val)
+ + {
+ + 	edma_write(ctlr, offset + ((i*2 + j) << 2), val);
+ + }
+ + static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset)
+ + {
+ + 	return edma_read(ctlr, EDMA_SHADOW0 + offset);
+ + }
+ + static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset,
+ + 		int i)
+ + {
+ + 	return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2));
+ + }
+ + static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val)
+ + {
+ + 	edma_write(ctlr, EDMA_SHADOW0 + offset, val);
+ + }
+ + static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i,
+ + 		unsigned val)
+ + {
+ + 	edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val);
+ + }
+ + static inline unsigned int edma_parm_read(unsigned ctlr, int offset,
+ + 		int param_no)
+ + {
+ + 	return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5));
+ + }
+ + static inline void edma_parm_write(unsigned ctlr, int offset, int param_no,
+ + 		unsigned val)
+ + {
+ + 	edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val);
+ + }
+ + static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no,
+ + 		unsigned and, unsigned or)
+ + {
+ + 	edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or);
+ + }
+ + static inline void edma_parm_and(unsigned ctlr, int offset, int param_no,
+ + 		unsigned and)
+ + {
+ + 	edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and);
+ + }
+ + static inline void edma_parm_or(unsigned ctlr, int offset, int param_no,
+ + 		unsigned or)
+ + {
+ + 	edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or);
+ + }
+ + 
+ + static inline void set_bits(int offset, int len, unsigned long *p)
+ + {
+ + 	for (; len > 0; len--)
+ + 		set_bit(offset + (len - 1), p);
+ + }
+ + 
+ + static inline void clear_bits(int offset, int len, unsigned long *p)
+ + {
+ + 	for (; len > 0; len--)
+ + 		clear_bit(offset + (len - 1), p);
+ + }
+ + 
+ + /*****************************************************************************/
+ + 
+ + struct edma *edma_cc[EDMA_MAX_CC];
+ + static int arch_num_cc;
+ + 
+ + /* dummy param set used to (re)initialize parameter RAM slots */
+ + static const struct edmacc_param dummy_paramset = {
+ + 	.link_bcntrld = 0xffff,
+ + 	.ccnt = 1,
+ + };
+ + 
+ + /*****************************************************************************/
+ + 
+ + static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
+ + 		enum dma_event_q queue_no)
+ + {
+ + 	int bit = (ch_no & 0x7) * 4;
+ + 
+ + 	/* default to low priority queue */
+ + 	if (queue_no == EVENTQ_DEFAULT)
+ + 		queue_no = edma_cc[ctlr]->default_queue;
+ + 
+ + 	queue_no &= 7;
+ + 	edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3),
+ + 			~(0x7 << bit), queue_no << bit);
+ + }
+ + 
+ + static void __init map_queue_tc(unsigned ctlr, int queue_no, int tc_no)
+ + {
+ + 	int bit = queue_no * 4;
+ + 	edma_modify(ctlr, EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit));
+ + }
+ + 
+ + static void __init assign_priority_to_queue(unsigned ctlr, int queue_no,
+ + 		int priority)
+ + {
+ + 	int bit = queue_no * 4;
+ + 	edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit),
+ + 			((priority & 0x7) << bit));
+ + }
+ + 
+ + /**
+ +  * map_dmach_param - Maps channel number to param entry number
+ +  *
+ +  * This maps the dma channel number to param entry numberter. In
+ +  * other words using the DMA channel mapping registers a param entry
+ +  * can be mapped to any channel
+ +  *
+ +  * Callers are responsible for ensuring the channel mapping logic is
+ +  * included in that particular EDMA variant (Eg : dm646x)
+ +  *
+ +  */
+ + static void __init map_dmach_param(unsigned ctlr)
+ + {
+ + 	int i;
+ + 	for (i = 0; i < EDMA_MAX_DMACH; i++)
+ + 		edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5));
+ + }
+ + 
+ + static inline void
+ + setup_dma_interrupt(unsigned lch,
+ + 	void (*callback)(unsigned channel, u16 ch_status, void *data),
+ + 	void *data)
+ + {
+ + 	unsigned ctlr;
+ + 
+ + 	ctlr = EDMA_CTLR(lch);
+ + 	lch = EDMA_CHAN_SLOT(lch);
+ + 
+ + 	if (!callback)
+ + 		edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5,
+ + 				BIT(lch & 0x1f));
+ + 
+ + 	edma_cc[ctlr]->intr_data[lch].callback = callback;
+ + 	edma_cc[ctlr]->intr_data[lch].data = data;
+ + 
+ + 	if (callback) {
+ + 		edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5,
+ + 				BIT(lch & 0x1f));
+ + 		edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5,
+ + 				BIT(lch & 0x1f));
+ + 	}
+ + }
+ + 
+ + static int irq2ctlr(int irq)
+ + {
+ + 	if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end)
+ + 		return 0;
+ + 	else if (irq >= edma_cc[1]->irq_res_start &&
+ + 		irq <= edma_cc[1]->irq_res_end)
+ + 		return 1;
+ + 
+ + 	return -1;
+ + }
+ + 
+ + /******************************************************************************
+ +  *
+ +  * DMA interrupt handler
+ +  *
+ +  *****************************************************************************/
+ + static irqreturn_t dma_irq_handler(int irq, void *data)
+ + {
+ + 	int ctlr;
+ + 	u32 sh_ier;
+ + 	u32 sh_ipr;
+ + 	u32 bank;
+ + 
+ + 	ctlr = irq2ctlr(irq);
+ + 	if (ctlr < 0)
+ + 		return IRQ_NONE;
+ + 
+ + 	dev_dbg(data, "dma_irq_handler\n");
+ + 
+ + 	sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 0);
+ + 	if (!sh_ipr) {
+ + 		sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 1);
+ + 		if (!sh_ipr)
+ + 			return IRQ_NONE;
+ + 		sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 1);
+ + 		bank = 1;
+ + 	} else {
+ + 		sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 0);
+ + 		bank = 0;
+ + 	}
+ + 
+ + 	do {
+ + 		u32 slot;
+ + 		u32 channel;
+ + 
+ + 		dev_dbg(data, "IPR%d %08x\n", bank, sh_ipr);
+ + 
+ + 		slot = __ffs(sh_ipr);
+ + 		sh_ipr &= ~(BIT(slot));
+ + 
+ + 		if (sh_ier & BIT(slot)) {
+ + 			channel = (bank << 5) | slot;
+ + 			/* Clear the corresponding IPR bits */
+ + 			edma_shadow0_write_array(ctlr, SH_ICR, bank,
+ + 					BIT(slot));
+ + 			if (edma_cc[ctlr]->intr_data[channel].callback)
+ + 				edma_cc[ctlr]->intr_data[channel].callback(
+ + 					channel, DMA_COMPLETE,
+ + 					edma_cc[ctlr]->intr_data[channel].data);
+ + 
+ + 
+ + 		}
+ + 	} while (sh_ipr);
+ + 
+ + 	edma_shadow0_write(ctlr, SH_IEVAL, 1);
+ + 	return IRQ_HANDLED;
+ + }
+ + 
+ + /******************************************************************************
+ +  *
+ +  * DMA error interrupt handler
+ +  *
+ +  *****************************************************************************/
+ + static irqreturn_t dma_ccerr_handler(int irq, void *data)
+ + {
+ + 	int i;
+ + 	int ctlr;
+ + 	unsigned int cnt = 0;
+ + 
+ + 	ctlr = irq2ctlr(irq);
+ + 	if (ctlr < 0)
+ + 		return IRQ_NONE;
+ + 
+ + 	dev_dbg(data, "dma_ccerr_handler\n");
+ + 
+ + 	if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
+ + 	    (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
+ + 	    (edma_read(ctlr, EDMA_QEMR) == 0) &&
+ + 	    (edma_read(ctlr, EDMA_CCERR) == 0))
+ + 		return IRQ_NONE;
+ + 
+ + 	while (1) {
+ + 		int j = -1;
+ + 		if (edma_read_array(ctlr, EDMA_EMR, 0))
+ + 			j = 0;
+ + 		else if (edma_read_array(ctlr, EDMA_EMR, 1))
+ + 			j = 1;
+ + 		if (j >= 0) {
+ + 			dev_dbg(data, "EMR%d %08x\n", j,
+ + 					edma_read_array(ctlr, EDMA_EMR, j));
+ + 			for (i = 0; i < 32; i++) {
+ + 				int k = (j << 5) + i;
+ + 				if (edma_read_array(ctlr, EDMA_EMR, j) &
+ + 							BIT(i)) {
+ + 					/* Clear the corresponding EMR bits */
+ + 					edma_write_array(ctlr, EDMA_EMCR, j,
+ + 							BIT(i));
+ + 					/* Clear any SER */
+ + 					edma_shadow0_write_array(ctlr, SH_SECR,
+ + 								j, BIT(i));
+ + 					if (edma_cc[ctlr]->intr_data[k].
+ + 								callback) {
+ + 						edma_cc[ctlr]->intr_data[k].
+ + 						callback(k,
+ + 						DMA_CC_ERROR,
+ + 						edma_cc[ctlr]->intr_data
+ + 						[k].data);
+ + 					}
+ + 				}
+ + 			}
+ + 		} else if (edma_read(ctlr, EDMA_QEMR)) {
+ + 			dev_dbg(data, "QEMR %02x\n",
+ + 				edma_read(ctlr, EDMA_QEMR));
+ + 			for (i = 0; i < 8; i++) {
+ + 				if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) {
+ + 					/* Clear the corresponding IPR bits */
+ + 					edma_write(ctlr, EDMA_QEMCR, BIT(i));
+ + 					edma_shadow0_write(ctlr, SH_QSECR,
+ + 								BIT(i));
+ + 
+ + 					/* NOTE:  not reported!! */
+ + 				}
+ + 			}
+ + 		} else if (edma_read(ctlr, EDMA_CCERR)) {
+ + 			dev_dbg(data, "CCERR %08x\n",
+ + 				edma_read(ctlr, EDMA_CCERR));
+ + 			/* FIXME:  CCERR.BIT(16) ignored!  much better
+ + 			 * to just write CCERRCLR with CCERR value...
+ + 			 */
+ + 			for (i = 0; i < 8; i++) {
+ + 				if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) {
+ + 					/* Clear the corresponding IPR bits */
+ + 					edma_write(ctlr, EDMA_CCERRCLR, BIT(i));
+ + 
+ + 					/* NOTE:  not reported!! */
+ + 				}
+ + 			}
+ + 		}
+ + 		if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
+ + 		    (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
+ + 		    (edma_read(ctlr, EDMA_QEMR) == 0) &&
+ + 		    (edma_read(ctlr, EDMA_CCERR) == 0))
+ + 			break;
+ + 		cnt++;
+ + 		if (cnt > 10)
+ + 			break;
+ + 	}
+ + 	edma_write(ctlr, EDMA_EEVAL, 1);
+ + 	return IRQ_HANDLED;
+ + }
+ + 
+ + /*-----------------------------------------------------------------------*/
+ + 
+ + static int reserve_contiguous_slots(int ctlr, unsigned int id,
+ + 				     unsigned int num_slots,
+ + 				     unsigned int start_slot)
+ + {
+ + 	int i, j;
+ + 	unsigned int count = num_slots;
+ + 	int stop_slot = start_slot;
+ + 	DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY);
+ + 
+ + 	for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) {
+ + 		j = EDMA_CHAN_SLOT(i);
+ + 		if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) {
+ + 			/* Record our current beginning slot */
+ + 			if (count == num_slots)
+ + 				stop_slot = i;
+ + 
+ + 			count--;
+ + 			set_bit(j, tmp_inuse);
+ + 
+ + 			if (count == 0)
+ + 				break;
+ + 		} else {
+ + 			clear_bit(j, tmp_inuse);
+ + 
+ + 			if (id == EDMA_CONT_PARAMS_FIXED_EXACT) {
+ + 				stop_slot = i;
+ + 				break;
+ + 			} else {
+ + 				count = num_slots;
+ + 			}
+ + 		}
+ + 	}
+ + 
+ + 	/*
+ + 	 * We have to clear any bits that we set
+ + 	 * if we run out parameter RAM slots, i.e we do find a set
+ + 	 * of contiguous parameter RAM slots but do not find the exact number
+ + 	 * requested as we may reach the total number of parameter RAM slots
+ + 	 */
+ + 	if (i == edma_cc[ctlr]->num_slots)
+ + 		stop_slot = i;
+ + 
+ + 	for (j = start_slot; j < stop_slot; j++)
+ + 		if (test_bit(j, tmp_inuse))
+ + 			clear_bit(j, edma_cc[ctlr]->edma_inuse);
+ + 
+ + 	if (count)
+ + 		return -EBUSY;
+ + 
+ + 	for (j = i - num_slots + 1; j <= i; ++j)
+ + 		memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(j),
+ + 			&dummy_paramset, PARM_SIZE);
+ + 
+ + 	return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1);
+ + }
+ + 
+ + static int prepare_unused_channel_list(struct device *dev, void *data)
+ + {
+ + 	struct platform_device *pdev = to_platform_device(dev);
+ + 	int i, ctlr;
+ + 
+ + 	for (i = 0; i < pdev->num_resources; i++) {
+ + 		if ((pdev->resource[i].flags & IORESOURCE_DMA) &&
+ + 				(int)pdev->resource[i].start >= 0) {
+ + 			ctlr = EDMA_CTLR(pdev->resource[i].start);
+ + 			/* confirm the range */
+ + 			if (EDMA_CHAN_SLOT(pdev->resource[i].start <
+ + 							EDMA_MAX_DMACH))
+ + 				clear_bit(
+ + 					EDMA_CHAN_SLOT(pdev->resource[i].start),
+ + 						edma_cc[ctlr]->edma_unused);
+ + 		}
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /*-----------------------------------------------------------------------*/
+ + 
+ + static bool unused_chan_list_done;
+ + 
+ + /* Resource alloc/free:  dma channels, parameter RAM slots */
+ + 
+ + /**
+ +  * edma_alloc_channel - allocate DMA channel and paired parameter RAM
+ +  * @channel: specific channel to allocate; negative for "any unmapped channel"
+ +  * @callback: optional; to be issued on DMA completion or errors
+ +  * @data: passed to callback
+ +  * @eventq_no: an EVENTQ_* constant, used to choose which Transfer
+ +  *	Controller (TC) executes requests using this channel.  Use
+ +  *	EVENTQ_DEFAULT unless you really need a high priority queue.
+ +  *
+ +  * This allocates a DMA channel and its associated parameter RAM slot.
+ +  * The parameter RAM is initialized to hold a dummy transfer.
+ +  *
+ +  * Normal use is to pass a specific channel number as @channel, to make
+ +  * use of hardware events mapped to that channel.  When the channel will
+ +  * be used only for software triggering or event chaining, channels not
+ +  * mapped to hardware events (or mapped to unused events) are preferable.
+ +  *
+ +  * DMA transfers start from a channel using edma_start(), or by
+ +  * chaining.  When the transfer described in that channel's parameter RAM
+ +  * slot completes, that slot's data may be reloaded through a link.
+ +  *
+ +  * DMA errors are only reported to the @callback associated with the
+ +  * channel driving that transfer, but transfer completion callbacks can
+ +  * be sent to another channel under control of the TCC field in
+ +  * the option word of the transfer's parameter RAM set.  Drivers must not
+ +  * use DMA transfer completion callbacks for channels they did not allocate.
+ +  * (The same applies to TCC codes used in transfer chaining.)
+ +  *
+ +  * Returns the number of the channel, else negative errno.
+ +  */
+ + int edma_alloc_channel(int channel,
+ + 		void (*callback)(unsigned channel, u16 ch_status, void *data),
+ + 		void *data,
+ + 		enum dma_event_q eventq_no)
+ + {
+ + 	unsigned i, done = 0, ctlr = 0;
+ + 	int ret = 0;
+ + 
+ + 	if (!unused_chan_list_done) {
+ + 		/*
+ + 		 * Scan all the platform devices to find out the EDMA channels
+ + 		 * used and clear them in the unused list, making the rest
+ + 		 * available for ARM usage.
+ + 		 */
+ + 		ret = bus_for_each_dev(&platform_bus_type, NULL, NULL,
+ + 				prepare_unused_channel_list);
+ + 		if (ret < 0)
+ + 			return ret;
+ + 
+ + 		unused_chan_list_done = true;
+ + 	}
+ + 
+ + 	if (channel >= 0) {
+ + 			ctlr = EDMA_CTLR(channel);
+ + 			channel = EDMA_CHAN_SLOT(channel);
+ + 			if (xbar_event_to_channel_map) {
+ + 				ret = xbar_event_to_channel_map(channel,
+ + 						&channel, edma_cc[ctlr]->
+ + 						xbar_event_mapping);
+ + 				if (ret != 0)
+ + 					return ret;
+ + 			}
+ + 	}
+ + 
+ + 	if (channel < 0) {
+ + 		for (i = 0; i < arch_num_cc; i++) {
+ + 			channel = 0;
+ + 			for (;;) {
+ + 				channel = find_next_bit(edma_cc[i]->edma_unused,
+ + 						edma_cc[i]->num_channels,
+ + 						channel);
+ + 				if (channel == edma_cc[i]->num_channels)
+ + 					break;
+ + 				if (!test_and_set_bit(channel,
+ + 						edma_cc[i]->edma_inuse)) {
+ + 					done = 1;
+ + 					ctlr = i;
+ + 					break;
+ + 				}
+ + 				channel++;
+ + 			}
+ + 			if (done)
+ + 				break;
+ + 		}
+ + 		if (!done)
+ + 			return -ENOMEM;
+ + 	} else if (channel >= edma_cc[ctlr]->num_channels) {
+ + 		return -EINVAL;
+ + 	} else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) {
+ + 		return -EBUSY;
+ + 	}
+ + 
+ + 	/* ensure access through shadow region 0 */
+ + 	edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
+ + 
+ + 	/* ensure no events are pending */
+ + 	edma_stop(EDMA_CTLR_CHAN(ctlr, channel));
+ + 	memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
+ + 			&dummy_paramset, PARM_SIZE);
+ + 
+ + 	if (callback)
+ + 		setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel),
+ + 					callback, data);
+ + 
+ + 	map_dmach_queue(ctlr, channel, eventq_no);
+ + 
+ + 	return EDMA_CTLR_CHAN(ctlr, channel);
+ + }
+ + EXPORT_SYMBOL(edma_alloc_channel);
+ + 
+ + 
+ + /**
+ +  * edma_free_channel - deallocate DMA channel
+ +  * @channel: dma channel returned from edma_alloc_channel()
+ +  *
+ +  * This deallocates the DMA channel and associated parameter RAM slot
+ +  * allocated by edma_alloc_channel().
+ +  *
+ +  * Callers are responsible for ensuring the channel is inactive, and
+ +  * will not be reactivated by linking, chaining, or software calls to
+ +  * edma_start().
+ +  */
+ + void edma_free_channel(unsigned channel)
+ + {
+ + 	unsigned ctlr;
+ + 
+ + 	ctlr = EDMA_CTLR(channel);
+ + 	channel = EDMA_CHAN_SLOT(channel);
+ + 
+ + 	if (channel >= edma_cc[ctlr]->num_channels)
+ + 		return;
+ + 
+ + 	setup_dma_interrupt(channel, NULL, NULL);
+ + 	/* REVISIT should probably take out of shadow region 0 */
+ + 
+ + 	memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
+ + 			&dummy_paramset, PARM_SIZE);
+ + 	clear_bit(channel, edma_cc[ctlr]->edma_inuse);
+ + }
+ + EXPORT_SYMBOL(edma_free_channel);
+ + 
+ + /**
+ +  * edma_alloc_slot - allocate DMA parameter RAM
+ +  * @slot: specific slot to allocate; negative for "any unused slot"
+ +  *
+ +  * This allocates a parameter RAM slot, initializing it to hold a
+ +  * dummy transfer.  Slots allocated using this routine have not been
+ +  * mapped to a hardware DMA channel, and will normally be used by
+ +  * linking to them from a slot associated with a DMA channel.
+ +  *
+ +  * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
+ +  * slots may be allocated on behalf of DSP firmware.
+ +  *
+ +  * Returns the number of the slot, else negative errno.
+ +  */
+ + int edma_alloc_slot(unsigned ctlr, int slot)
+ + {
+ + 	if (slot >= 0)
+ + 		slot = EDMA_CHAN_SLOT(slot);
+ + 
+ + 	if (slot < 0) {
+ + 		slot = edma_cc[ctlr]->num_channels;
+ + 		for (;;) {
+ + 			slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse,
+ + 					edma_cc[ctlr]->num_slots, slot);
+ + 			if (slot == edma_cc[ctlr]->num_slots)
+ + 				return -ENOMEM;
+ + 			if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse))
+ + 				break;
+ + 		}
+ + 	} else if (slot < edma_cc[ctlr]->num_channels ||
+ + 			slot >= edma_cc[ctlr]->num_slots) {
+ + 		return -EINVAL;
+ + 	} else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) {
+ + 		return -EBUSY;
+ + 	}
+ + 
+ + 	memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
+ + 			&dummy_paramset, PARM_SIZE);
+ + 
+ + 	return EDMA_CTLR_CHAN(ctlr, slot);
+ + }
+ + EXPORT_SYMBOL(edma_alloc_slot);
+ + 
+ + /**
+ +  * edma_free_slot - deallocate DMA parameter RAM
+ +  * @slot: parameter RAM slot returned from edma_alloc_slot()
+ +  *
+ +  * This deallocates the parameter RAM slot allocated by edma_alloc_slot().
+ +  * Callers are responsible for ensuring the slot is inactive, and will
+ +  * not be activated.
+ +  */
+ + void edma_free_slot(unsigned slot)
+ + {
+ + 	unsigned ctlr;
+ + 
+ + 	ctlr = EDMA_CTLR(slot);
+ + 	slot = EDMA_CHAN_SLOT(slot);
+ + 
+ + 	if (slot < edma_cc[ctlr]->num_channels ||
+ + 		slot >= edma_cc[ctlr]->num_slots)
+ + 		return;
+ + 
+ + 	memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
+ + 			&dummy_paramset, PARM_SIZE);
+ + 	clear_bit(slot, edma_cc[ctlr]->edma_inuse);
+ + }
+ + EXPORT_SYMBOL(edma_free_slot);
+ + 
+ + 
+ + /**
+ +  * edma_alloc_cont_slots- alloc contiguous parameter RAM slots
+ +  * The API will return the starting point of a set of
+ +  * contiguous parameter RAM slots that have been requested
+ +  *
+ +  * @id: can only be EDMA_CONT_PARAMS_ANY or EDMA_CONT_PARAMS_FIXED_EXACT
+ +  * or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
+ +  * @count: number of contiguous Paramter RAM slots
+ +  * @slot  - the start value of Parameter RAM slot that should be passed if id
+ +  * is EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
+ +  *
+ +  * If id is EDMA_CONT_PARAMS_ANY then the API starts looking for a set of
+ +  * contiguous Parameter RAM slots from parameter RAM 64 in the case of
+ +  * DaVinci SOCs and 32 in the case of DA8xx SOCs.
+ +  *
+ +  * If id is EDMA_CONT_PARAMS_FIXED_EXACT then the API starts looking for a
+ +  * set of contiguous parameter RAM slots from the "slot" that is passed as an
+ +  * argument to the API.
+ +  *
+ +  * If id is EDMA_CONT_PARAMS_FIXED_NOT_EXACT then the API initially tries
+ +  * starts looking for a set of contiguous parameter RAMs from the "slot"
+ +  * that is passed as an argument to the API. On failure the API will try to
+ +  * find a set of contiguous Parameter RAM slots from the remaining Parameter
+ +  * RAM slots
+ +  */
+ + int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
+ + {
+ + 	/*
+ + 	 * The start slot requested should be greater than
+ + 	 * the number of channels and lesser than the total number
+ + 	 * of slots
+ + 	 */
+ + 	if ((id != EDMA_CONT_PARAMS_ANY) &&
+ + 		(slot < edma_cc[ctlr]->num_channels ||
+ + 		slot >= edma_cc[ctlr]->num_slots))
+ + 		return -EINVAL;
+ + 
+ + 	/*
+ + 	 * The number of parameter RAM slots requested cannot be less than 1
+ + 	 * and cannot be more than the number of slots minus the number of
+ + 	 * channels
+ + 	 */
+ + 	if (count < 1 || count >
+ + 		(edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels))
+ + 		return -EINVAL;
+ + 
+ + 	switch (id) {
+ + 	case EDMA_CONT_PARAMS_ANY:
+ + 		return reserve_contiguous_slots(ctlr, id, count,
+ + 						 edma_cc[ctlr]->num_channels);
+ + 	case EDMA_CONT_PARAMS_FIXED_EXACT:
+ + 	case EDMA_CONT_PARAMS_FIXED_NOT_EXACT:
+ + 		return reserve_contiguous_slots(ctlr, id, count, slot);
+ + 	default:
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + }
+ + EXPORT_SYMBOL(edma_alloc_cont_slots);
+ + 
+ + /**
+ +  * edma_free_cont_slots - deallocate DMA parameter RAM slots
+ +  * @slot: first parameter RAM of a set of parameter RAM slots to be freed
+ +  * @count: the number of contiguous parameter RAM slots to be freed
+ +  *
+ +  * This deallocates the parameter RAM slots allocated by
+ +  * edma_alloc_cont_slots.
+ +  * Callers/applications need to keep track of sets of contiguous
+ +  * parameter RAM slots that have been allocated using the edma_alloc_cont_slots
+ +  * API.
+ +  * Callers are responsible for ensuring the slots are inactive, and will
+ +  * not be activated.
+ +  */
+ + int edma_free_cont_slots(unsigned slot, int count)
+ + {
+ + 	unsigned ctlr, slot_to_free;
+ + 	int i;
+ + 
+ + 	ctlr = EDMA_CTLR(slot);
+ + 	slot = EDMA_CHAN_SLOT(slot);
+ + 
+ + 	if (slot < edma_cc[ctlr]->num_channels ||
+ + 		slot >= edma_cc[ctlr]->num_slots ||
+ + 		count < 1)
+ + 		return -EINVAL;
+ + 
+ + 	for (i = slot; i < slot + count; ++i) {
+ + 		ctlr = EDMA_CTLR(i);
+ + 		slot_to_free = EDMA_CHAN_SLOT(i);
+ + 
+ + 		memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free),
+ + 			&dummy_paramset, PARM_SIZE);
+ + 		clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse);
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(edma_free_cont_slots);
+ + 
+ + /*-----------------------------------------------------------------------*/
+ + 
+ + /* Parameter RAM operations (i) -- read/write partial slots */
+ + 
+ + /**
+ +  * edma_set_src - set initial DMA source address in parameter RAM slot
+ +  * @slot: parameter RAM slot being configured
+ +  * @src_port: physical address of source (memory, controller FIFO, etc)
+ +  * @addressMode: INCR, except in very rare cases
+ +  * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
+ +  *	width to use when addressing the fifo (e.g. W8BIT, W32BIT)
+ +  *
+ +  * Note that the source address is modified during the DMA transfer
+ +  * according to edma_set_src_index().
+ +  */
+ + void edma_set_src(unsigned slot, dma_addr_t src_port,
+ + 				enum address_mode mode, enum fifo_width width)
+ + {
+ + 	unsigned ctlr;
+ + 
+ + 	ctlr = EDMA_CTLR(slot);
+ + 	slot = EDMA_CHAN_SLOT(slot);
+ + 
+ + 	if (slot < edma_cc[ctlr]->num_slots) {
+ + 		unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
+ + 
+ + 		if (mode) {
+ + 			/* set SAM and program FWID */
+ + 			i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8));
+ + 		} else {
+ + 			/* clear SAM */
+ + 			i &= ~SAM;
+ + 		}
+ + 		edma_parm_write(ctlr, PARM_OPT, slot, i);
+ + 
+ + 		/* set the source port address
+ + 		   in source register of param structure */
+ + 		edma_parm_write(ctlr, PARM_SRC, slot, src_port);
+ + 	}
+ + }
+ + EXPORT_SYMBOL(edma_set_src);
+ + 
+ + /**
+ +  * edma_set_dest - set initial DMA destination address in parameter RAM slot
+ +  * @slot: parameter RAM slot being configured
+ +  * @dest_port: physical address of destination (memory, controller FIFO, etc)
+ +  * @addressMode: INCR, except in very rare cases
+ +  * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
+ +  *	width to use when addressing the fifo (e.g. W8BIT, W32BIT)
+ +  *
+ +  * Note that the destination address is modified during the DMA transfer
+ +  * according to edma_set_dest_index().
+ +  */
+ + void edma_set_dest(unsigned slot, dma_addr_t dest_port,
+ + 				 enum address_mode mode, enum fifo_width width)
+ + {
+ + 	unsigned ctlr;
+ + 
+ + 	ctlr = EDMA_CTLR(slot);
+ + 	slot = EDMA_CHAN_SLOT(slot);
+ + 
+ + 	if (slot < edma_cc[ctlr]->num_slots) {
+ + 		unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
+ + 
+ + 		if (mode) {
+ + 			/* set DAM and program FWID */
+ + 			i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8));
+ + 		} else {
+ + 			/* clear DAM */
+ + 			i &= ~DAM;
+ + 		}
+ + 		edma_parm_write(ctlr, PARM_OPT, slot, i);
+ + 		/* set the destination port address
+ + 		   in dest register of param structure */
+ + 		edma_parm_write(ctlr, PARM_DST, slot, dest_port);
+ + 	}
+ + }
+ + EXPORT_SYMBOL(edma_set_dest);
+ + 
+ + /**
+ +  * edma_get_position - returns the current transfer points
+ +  * @slot: parameter RAM slot being examined
+ +  * @src: pointer to source port position
+ +  * @dst: pointer to destination port position
+ +  *
+ +  * Returns current source and destination addresses for a particular
+ +  * parameter RAM slot.  Its channel should not be active when this is called.
+ +  */
+ + void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst)
+ + {
+ + 	struct edmacc_param temp;
+ + 	unsigned ctlr;
+ + 
+ + 	ctlr = EDMA_CTLR(slot);
+ + 	slot = EDMA_CHAN_SLOT(slot);
+ + 
+ + 	edma_read_slot(EDMA_CTLR_CHAN(ctlr, slot), &temp);
+ + 	if (src != NULL)
+ + 		*src = temp.src;
+ + 	if (dst != NULL)
+ + 		*dst = temp.dst;
+ + }
+ + EXPORT_SYMBOL(edma_get_position);
+ + 
+ + /**
+ +  * edma_set_src_index - configure DMA source address indexing
+ +  * @slot: parameter RAM slot being configured
+ +  * @src_bidx: byte offset between source arrays in a frame
+ +  * @src_cidx: byte offset between source frames in a block
+ +  *
+ +  * Offsets are specified to support either contiguous or discontiguous
+ +  * memory transfers, or repeated access to a hardware register, as needed.
+ +  * When accessing hardware registers, both offsets are normally zero.
+ +  */
+ + void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx)
+ + {
+ + 	unsigned ctlr;
+ + 
+ + 	ctlr = EDMA_CTLR(slot);
+ + 	slot = EDMA_CHAN_SLOT(slot);
+ + 
+ + 	if (slot < edma_cc[ctlr]->num_slots) {
+ + 		edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
+ + 				0xffff0000, src_bidx);
+ + 		edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
+ + 				0xffff0000, src_cidx);
+ + 	}
+ + }
+ + EXPORT_SYMBOL(edma_set_src_index);
+ + 
+ + /**
+ +  * edma_set_dest_index - configure DMA destination address indexing
+ +  * @slot: parameter RAM slot being configured
+ +  * @dest_bidx: byte offset between destination arrays in a frame
+ +  * @dest_cidx: byte offset between destination frames in a block
+ +  *
+ +  * Offsets are specified to support either contiguous or discontiguous
+ +  * memory transfers, or repeated access to a hardware register, as needed.
+ +  * When accessing hardware registers, both offsets are normally zero.
+ +  */
+ + void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx)
+ + {
+ + 	unsigned ctlr;
+ + 
+ + 	ctlr = EDMA_CTLR(slot);
+ + 	slot = EDMA_CHAN_SLOT(slot);
+ + 
+ + 	if (slot < edma_cc[ctlr]->num_slots) {
+ + 		edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
+ + 				0x0000ffff, dest_bidx << 16);
+ + 		edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
+ + 				0x0000ffff, dest_cidx << 16);
+ + 	}
+ + }
+ + EXPORT_SYMBOL(edma_set_dest_index);
+ + 
+ + /**
+ +  * edma_set_transfer_params - configure DMA transfer parameters
+ +  * @slot: parameter RAM slot being configured
+ +  * @acnt: how many bytes per array (at least one)
+ +  * @bcnt: how many arrays per frame (at least one)
+ +  * @ccnt: how many frames per block (at least one)
+ +  * @bcnt_rld: used only for A-Synchronized transfers; this specifies
+ +  *	the value to reload into bcnt when it decrements to zero
+ +  * @sync_mode: ASYNC or ABSYNC
+ +  *
+ +  * See the EDMA3 documentation to understand how to configure and link
+ +  * transfers using the fields in PaRAM slots.  If you are not doing it
+ +  * all at once with edma_write_slot(), you will use this routine
+ +  * plus two calls each for source and destination, setting the initial
+ +  * address and saying how to index that address.
+ +  *
+ +  * An example of an A-Synchronized transfer is a serial link using a
+ +  * single word shift register.  In that case, @acnt would be equal to
+ +  * that word size; the serial controller issues a DMA synchronization
+ +  * event to transfer each word, and memory access by the DMA transfer
+ +  * controller will be word-at-a-time.
+ +  *
+ +  * An example of an AB-Synchronized transfer is a device using a FIFO.
+ +  * In that case, @acnt equals the FIFO width and @bcnt equals its depth.
+ +  * The controller with the FIFO issues DMA synchronization events when
+ +  * the FIFO threshold is reached, and the DMA transfer controller will
+ +  * transfer one frame to (or from) the FIFO.  It will probably use
+ +  * efficient burst modes to access memory.
+ +  */
+ + void edma_set_transfer_params(unsigned slot,
+ + 		u16 acnt, u16 bcnt, u16 ccnt,
+ + 		u16 bcnt_rld, enum sync_dimension sync_mode)
+ + {
+ + 	unsigned ctlr;
+ + 
+ + 	ctlr = EDMA_CTLR(slot);
+ + 	slot = EDMA_CHAN_SLOT(slot);
+ + 
+ + 	if (slot < edma_cc[ctlr]->num_slots) {
+ + 		edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot,
+ + 				0x0000ffff, bcnt_rld << 16);
+ + 		if (sync_mode == ASYNC)
+ + 			edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM);
+ + 		else
+ + 			edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM);
+ + 		/* Set the acount, bcount, ccount registers */
+ + 		edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt);
+ + 		edma_parm_write(ctlr, PARM_CCNT, slot, ccnt);
+ + 	}
+ + }
+ + EXPORT_SYMBOL(edma_set_transfer_params);
+ + 
+ + /**
+ +  * edma_link - link one parameter RAM slot to another
+ +  * @from: parameter RAM slot originating the link
+ +  * @to: parameter RAM slot which is the link target
+ +  *
+ +  * The originating slot should not be part of any active DMA transfer.
+ +  */
+ + void edma_link(unsigned from, unsigned to)
+ + {
+ + 	unsigned ctlr_from, ctlr_to;
+ + 
+ + 	ctlr_from = EDMA_CTLR(from);
+ + 	from = EDMA_CHAN_SLOT(from);
+ + 	ctlr_to = EDMA_CTLR(to);
+ + 	to = EDMA_CHAN_SLOT(to);
+ + 
+ + 	if (from >= edma_cc[ctlr_from]->num_slots)
+ + 		return;
+ + 	if (to >= edma_cc[ctlr_to]->num_slots)
+ + 		return;
+ + 	edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000,
+ + 				PARM_OFFSET(to));
+ + }
+ + EXPORT_SYMBOL(edma_link);
+ + 
+ + /**
+ +  * edma_unlink - cut link from one parameter RAM slot
+ +  * @from: parameter RAM slot originating the link
+ +  *
+ +  * The originating slot should not be part of any active DMA transfer.
+ +  * Its link is set to 0xffff.
+ +  */
+ + void edma_unlink(unsigned from)
+ + {
+ + 	unsigned ctlr;
+ + 
+ + 	ctlr = EDMA_CTLR(from);
+ + 	from = EDMA_CHAN_SLOT(from);
+ + 
+ + 	if (from >= edma_cc[ctlr]->num_slots)
+ + 		return;
+ + 	edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff);
+ + }
+ + EXPORT_SYMBOL(edma_unlink);
+ + 
+ + /*-----------------------------------------------------------------------*/
+ + 
+ + /* Parameter RAM operations (ii) -- read/write whole parameter sets */
+ + 
+ + /**
+ +  * edma_write_slot - write parameter RAM data for slot
+ +  * @slot: number of parameter RAM slot being modified
+ +  * @param: data to be written into parameter RAM slot
+ +  *
+ +  * Use this to assign all parameters of a transfer at once.  This
+ +  * allows more efficient setup of transfers than issuing multiple
+ +  * calls to set up those parameters in small pieces, and provides
+ +  * complete control over all transfer options.
+ +  */
+ + void edma_write_slot(unsigned slot, const struct edmacc_param *param)
+ + {
+ + 	unsigned ctlr;
+ + 
+ + 	ctlr = EDMA_CTLR(slot);
+ + 	slot = EDMA_CHAN_SLOT(slot);
+ + 
+ + 	if (slot >= edma_cc[ctlr]->num_slots)
+ + 		return;
+ + 	memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param,
+ + 			PARM_SIZE);
+ + }
+ + EXPORT_SYMBOL(edma_write_slot);
+ + 
+ + /**
+ +  * edma_read_slot - read parameter RAM data from slot
+ +  * @slot: number of parameter RAM slot being copied
+ +  * @param: where to store copy of parameter RAM data
+ +  *
+ +  * Use this to read data from a parameter RAM slot, perhaps to
+ +  * save them as a template for later reuse.
+ +  */
+ + void edma_read_slot(unsigned slot, struct edmacc_param *param)
+ + {
+ + 	unsigned ctlr;
+ + 
+ + 	ctlr = EDMA_CTLR(slot);
+ + 	slot = EDMA_CHAN_SLOT(slot);
+ + 
+ + 	if (slot >= edma_cc[ctlr]->num_slots)
+ + 		return;
+ + 	memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
+ + 			PARM_SIZE);
+ + }
+ + EXPORT_SYMBOL(edma_read_slot);
+ + 
+ + /*-----------------------------------------------------------------------*/
+ + 
+ + /* Various EDMA channel control operations */
+ + 
+ + /**
+ +  * edma_pause - pause dma on a channel
+ +  * @channel: on which edma_start() has been called
+ +  *
+ +  * This temporarily disables EDMA hardware events on the specified channel,
+ +  * preventing them from triggering new transfers on its behalf
+ +  */
+ + void edma_pause(unsigned channel)
+ + {
+ + 	unsigned ctlr;
+ + 
+ + 	ctlr = EDMA_CTLR(channel);
+ + 	channel = EDMA_CHAN_SLOT(channel);
+ + 
+ + 	if (channel < edma_cc[ctlr]->num_channels) {
+ + 		unsigned int mask = BIT(channel & 0x1f);
+ + 
+ + 		edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask);
+ + 	}
+ + }
+ + EXPORT_SYMBOL(edma_pause);
+ + 
+ + /**
+ +  * edma_resume - resumes dma on a paused channel
+ +  * @channel: on which edma_pause() has been called
+ +  *
+ +  * This re-enables EDMA hardware events on the specified channel.
+ +  */
+ + void edma_resume(unsigned channel)
+ + {
+ + 	unsigned ctlr;
+ + 
+ + 	ctlr = EDMA_CTLR(channel);
+ + 	channel = EDMA_CHAN_SLOT(channel);
+ + 
+ + 	if (channel < edma_cc[ctlr]->num_channels) {
+ + 		unsigned int mask = BIT(channel & 0x1f);
+ + 
+ + 		edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask);
+ + 	}
+ + }
+ + EXPORT_SYMBOL(edma_resume);
+ + 
+ + /**
+ +  * edma_start - start dma on a channel
+ +  * @channel: channel being activated
+ +  *
+ +  * Channels with event associations will be triggered by their hardware
+ +  * events, and channels without such associations will be triggered by
+ +  * software.  (At this writing there is no interface for using software
+ +  * triggers except with channels that don't support hardware triggers.)
+ +  *
+ +  * Returns zero on success, else negative errno.
+ +  */
+ + int edma_start(unsigned channel)
+ + {
+ + 	unsigned ctlr;
+ + 
+ + 	ctlr = EDMA_CTLR(channel);
+ + 	channel = EDMA_CHAN_SLOT(channel);
+ + 
+ + 	if (channel < edma_cc[ctlr]->num_channels) {
+ + 		int j = channel >> 5;
+ + 		unsigned int mask = BIT(channel & 0x1f);
+ + 
+ + 		/* EDMA channels without event association */
+ + 		if (test_bit(channel, edma_cc[ctlr]->edma_unused)) {
+ + 			pr_debug("EDMA: ESR%d %08x\n", j,
+ + 				edma_shadow0_read_array(ctlr, SH_ESR, j));
+ + 			edma_shadow0_write_array(ctlr, SH_ESR, j, mask);
+ + 			return 0;
+ + 		}
+ + 
+ + 		/* EDMA channel with event association */
+ + 		pr_debug("EDMA: ER%d %08x\n", j,
+ + 			edma_shadow0_read_array(ctlr, SH_ER, j));
+ + 		/* Clear any pending event or error */
+ + 		edma_write_array(ctlr, EDMA_ECR, j, mask);
+ + 		edma_write_array(ctlr, EDMA_EMCR, j, mask);
+ + 		/* Clear any SER */
+ + 		edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
+ + 		edma_shadow0_write_array(ctlr, SH_EESR, j, mask);
+ + 		pr_debug("EDMA: EER%d %08x\n", j,
+ + 			edma_shadow0_read_array(ctlr, SH_EER, j));
+ + 		return 0;
+ + 	}
+ + 
+ + 	return -EINVAL;
+ + }
+ + EXPORT_SYMBOL(edma_start);
+ + 
+ + /**
+ +  * edma_stop - stops dma on the channel passed
+ +  * @channel: channel being deactivated
+ +  *
+ +  * When @lch is a channel, any active transfer is paused and
+ +  * all pending hardware events are cleared.  The current transfer
+ +  * may not be resumed, and the channel's Parameter RAM should be
+ +  * reinitialized before being reused.
+ +  */
+ + void edma_stop(unsigned channel)
+ + {
+ + 	unsigned ctlr;
+ + 
+ + 	ctlr = EDMA_CTLR(channel);
+ + 	channel = EDMA_CHAN_SLOT(channel);
+ + 
+ + 	if (channel < edma_cc[ctlr]->num_channels) {
+ + 		int j = channel >> 5;
+ + 		unsigned int mask = BIT(channel & 0x1f);
+ + 
+ + 		edma_shadow0_write_array(ctlr, SH_EECR, j, mask);
+ + 		edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
+ + 		edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
+ + 		edma_write_array(ctlr, EDMA_EMCR, j, mask);
+ + 
+ + 		pr_debug("EDMA: EER%d %08x\n", j,
+ + 				edma_shadow0_read_array(ctlr, SH_EER, j));
+ + 
+ + 		/* REVISIT:  consider guarding against inappropriate event
+ + 		 * chaining by overwriting with dummy_paramset.
+ + 		 */
+ + 	}
+ + }
+ + EXPORT_SYMBOL(edma_stop);
+ + 
+ + /******************************************************************************
+ +  *
+ +  * It cleans ParamEntry qand bring back EDMA to initial state if media has
+ +  * been removed before EDMA has finished.It is usedful for removable media.
+ +  * Arguments:
+ +  *      ch_no     - channel no
+ +  *
+ +  * Return: zero on success, or corresponding error no on failure
+ +  *
+ +  * FIXME this should not be needed ... edma_stop() should suffice.
+ +  *
+ +  *****************************************************************************/
+ + 
+ + void edma_clean_channel(unsigned channel)
+ + {
+ + 	unsigned ctlr;
+ + 
+ + 	ctlr = EDMA_CTLR(channel);
+ + 	channel = EDMA_CHAN_SLOT(channel);
+ + 
+ + 	if (channel < edma_cc[ctlr]->num_channels) {
+ + 		int j = (channel >> 5);
+ + 		unsigned int mask = BIT(channel & 0x1f);
+ + 
+ + 		pr_debug("EDMA: EMR%d %08x\n", j,
+ + 				edma_read_array(ctlr, EDMA_EMR, j));
+ + 		edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
+ + 		/* Clear the corresponding EMR bits */
+ + 		edma_write_array(ctlr, EDMA_EMCR, j, mask);
+ + 		/* Clear any SER */
+ + 		edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
+ + 		edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
+ + 	}
+ + }
+ + EXPORT_SYMBOL(edma_clean_channel);
+ + 
+ + /*
+ +  * edma_clear_event - clear an outstanding event on the DMA channel
+ +  * Arguments:
+ +  *	channel - channel number
+ +  */
+ + void edma_clear_event(unsigned channel)
+ + {
+ + 	unsigned ctlr;
+ + 
+ + 	ctlr = EDMA_CTLR(channel);
+ + 	channel = EDMA_CHAN_SLOT(channel);
+ + 
+ + 	if (channel >= edma_cc[ctlr]->num_channels)
+ + 		return;
+ + 	if (channel < 32)
+ + 		edma_write(ctlr, EDMA_ECR, BIT(channel));
+ + 	else
+ + 		edma_write(ctlr, EDMA_ECRH, BIT(channel - 32));
+ + }
+ + EXPORT_SYMBOL(edma_clear_event);
+ + 
+ + /*-----------------------------------------------------------------------*/
+ + 
+ + static int __init edma_probe(struct platform_device *pdev)
+ + {
+ + 	struct edma_soc_info	*info = pdev->dev.platform_data;
+ + 	const s8		(*queue_priority_mapping)[2];
+ + 	const s8		(*queue_tc_mapping)[2];
+ + 	int			i, j, off, ln, found = 0;
+ + 	int			status = -1;
+ + 	const s16		(*rsv_chans)[2];
+ + 	const s16		(*rsv_slots)[2];
+ + 	int			irq[EDMA_MAX_CC] = {0, 0};
+ + 	int			err_irq[EDMA_MAX_CC] = {0, 0};
+ + 	struct resource		*r[EDMA_MAX_CC] = {NULL};
+ + 	resource_size_t		len[EDMA_MAX_CC];
+ + 	char			res_name[10];
+ + 	char			irq_name[10];
+ + 
+ + 	if (!info)
+ + 		return -ENODEV;
+ + 
+ + 	pm_runtime_enable(&pdev->dev);
+ + 	pm_runtime_get_sync(&pdev->dev);
+ + 
+ + 	for (j = 0; j < EDMA_MAX_CC; j++) {
+ + 		sprintf(res_name, "edma_cc%d", j);
+ + 		r[j] = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ + 						res_name);
+ + 		if (!r[j]) {
+ + 			if (found)
+ + 				break;
+ + 			else
+ + 				return -ENODEV;
+ + 		} else {
+ + 			found = 1;
+ + 		}
+ + 
+ + 		len[j] = resource_size(r[j]);
+ + 
+ + 		r[j] = request_mem_region(r[j]->start, len[j],
+ + 			dev_name(&pdev->dev));
+ + 		if (!r[j]) {
+ + 			status = -EBUSY;
+ + 			goto fail1;
+ + 		}
+ + 
+ + 		edmacc_regs_base[j] = ioremap(r[j]->start, len[j]);
+ + 		if (!edmacc_regs_base[j]) {
+ + 			status = -EBUSY;
+ + 			goto fail1;
+ + 		}
+ + 
+ + 		edma_cc[j] = kzalloc(sizeof(struct edma), GFP_KERNEL);
+ + 		if (!edma_cc[j]) {
+ + 			status = -ENOMEM;
+ + 			goto fail1;
+ + 		}
+ + 
+ + 		edma_cc[j]->num_channels = min_t(unsigned, info[j].n_channel,
+ + 							EDMA_MAX_DMACH);
+ + 		edma_cc[j]->num_slots = min_t(unsigned, info[j].n_slot,
+ + 							EDMA_MAX_PARAMENTRY);
+ + 		edma_cc[j]->num_cc = min_t(unsigned, info[j].n_cc, EDMA_MAX_CC);
+ + 		edma_cc[j]->num_region = min_t(unsigned, info[j].n_region,
+ + 							EDMA_MAX_REGION);
+ + 
+ + 		edma_cc[j]->bkp_prm_set = kzalloc((sizeof(struct edmacc_param) *
+ + 						edma_cc[j]->num_slots),
+ + 						GFP_KERNEL);
+ + 		if (!edma_cc[j]->bkp_prm_set) {
+ + 			status = -ENOMEM;
+ + 			dev_err(&pdev->dev, "err: mem alloc bkp_prm_set\n");
+ + 			goto fail1;
+ + 		}
+ + 
+ + 		edma_cc[j]->bkp_ch_map = kzalloc((sizeof(unsigned int) *
+ + 						edma_cc[j]->num_channels),
+ + 						GFP_KERNEL);
+ + 		if (!edma_cc[j]->bkp_ch_map) {
+ + 			status = -ENOMEM;
+ + 			dev_err(&pdev->dev, "err: mem alloc bkp_ch_map\n");
+ + 			goto fail1;
+ + 		}
+ + 
+ + 		edma_cc[j]->bkp_que_num = kzalloc((sizeof(unsigned int) * 8),
+ + 								GFP_KERNEL);
+ + 		if (!edma_cc[j]->bkp_que_num) {
+ + 			status = -ENOMEM;
+ + 			dev_err(&pdev->dev, "err: mem alloc bkp_que_num\n");
+ + 			goto fail1;
+ + 		}
+ + 
+ + 		edma_cc[j]->bkp_drae = kzalloc((sizeof(unsigned int) *
+ + 							edma_cc[j]->num_region),
+ + 							GFP_KERNEL);
+ + 		if (!edma_cc[j]->bkp_drae) {
+ + 			status = -ENOMEM;
+ + 			dev_err(&pdev->dev, "err: mem alloc bkp_drae\n");
+ + 			goto fail1;
+ + 		}
+ + 
+ + 		edma_cc[j]->bkp_draeh = kzalloc((sizeof(unsigned int) *
+ + 							edma_cc[j]->num_region),
+ + 							GFP_KERNEL);
+ + 		if (!edma_cc[j]->bkp_draeh) {
+ + 			status = -ENOMEM;
+ + 			dev_err(&pdev->dev, "err: mem alloc bkp_draeh\n");
+ + 			goto fail1;
+ + 		}
+ + 
+ + 		edma_cc[j]->bkp_qrae = kzalloc((sizeof(unsigned int) *
+ + 							edma_cc[j]->num_region),
+ + 							GFP_KERNEL);
+ + 		if (!edma_cc[j]->bkp_qrae) {
+ + 			status = -ENOMEM;
+ + 			dev_err(&pdev->dev, "err: mem alloc bkp_qrae\n");
+ + 			goto fail1;
+ + 		}
+ + 
+ + 		edma_cc[j]->default_queue = info[j].default_queue;
+ + 		if (!edma_cc[j]->default_queue)
+ + 			edma_cc[j]->default_queue = EVENTQ_1;
+ + 
+ + 		dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n",
+ + 			edmacc_regs_base[j]);
+ + 
+ + 		for (i = 0; i < edma_cc[j]->num_slots; i++)
+ + 			memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i),
+ + 					&dummy_paramset, PARM_SIZE);
+ + 
+ + 		/* Mark all channels as unused */
+ + 		memset(edma_cc[j]->edma_unused, 0xff,
+ + 			sizeof(edma_cc[j]->edma_unused));
+ + 
+ + 		/* Clear the reserved channels in unused list */
+ + 		rsv_chans = info[j].rsv_chans;
+ + 		if (rsv_chans) {
+ + 			for (i = 0; rsv_chans[i][0] != -1; i++) {
+ + 				off = rsv_chans[i][0];
+ + 				ln = rsv_chans[i][1];
+ + 				/* confirm the range */
+ + 				if ((off+ln) < EDMA_MAX_DMACH)
+ + 					clear_bits(off, ln,
+ + 						edma_cc[j]->edma_unused);
+ + 			}
+ + 		}
+ + 
+ + 		/* Set the reserved channels/slots in inuse list */
+ + 		rsv_slots = info[j].rsv_slots;
+ + 		if (rsv_slots) {
+ + 			for (i = 0; rsv_slots[i][0] != -1; i++) {
+ + 				off = rsv_slots[i][0];
+ + 				ln = rsv_slots[i][1];
+ + 				set_bits(off, ln, edma_cc[j]->edma_inuse);
+ + 			}
+ + 		}
+ + 
+ + 		sprintf(irq_name, "edma%d", j);
+ + 		irq[j] = platform_get_irq_byname(pdev, irq_name);
+ + 		edma_cc[j]->irq_res_start = irq[j];
+ + 		status = request_irq(irq[j], dma_irq_handler, 0, "edma",
+ + 					&pdev->dev);
+ + 		if (status < 0) {
+ + 			dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
+ + 				irq[j], status);
+ + 			goto fail;
+ + 		}
+ + 
+ + 		sprintf(irq_name, "edma%d_err", j);
+ + 		err_irq[j] = platform_get_irq_byname(pdev, irq_name);
+ + 		edma_cc[j]->irq_res_end = err_irq[j];
+ + 		status = request_irq(err_irq[j], dma_ccerr_handler, 0,
+ + 					"edma_error", &pdev->dev);
+ + 		if (status < 0) {
+ + 			dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
+ + 				err_irq[j], status);
+ + 			goto fail;
+ + 		}
+ + 
+ + 		/* Everything lives on transfer controller 1 until otherwise
+ + 		 * specified. This way, long transfers on the low priority queue
+ + 		 * started by the codec engine will not cause audio defects.
+ + 		 */
+ + 		for (i = 0; i < edma_cc[j]->num_channels; i++)
+ + 			map_dmach_queue(j, i, EVENTQ_1);
+ + 
+ + 		queue_tc_mapping = info[j].queue_tc_mapping;
+ + 		queue_priority_mapping = info[j].queue_priority_mapping;
+ + 
+ + 		/* Event queue to TC mapping */
+ + 		for (i = 0; queue_tc_mapping[i][0] != -1; i++)
+ + 			map_queue_tc(j, queue_tc_mapping[i][0],
+ + 					queue_tc_mapping[i][1]);
+ + 
+ + 		/* Event queue priority mapping */
+ + 		for (i = 0; queue_priority_mapping[i][0] != -1; i++)
+ + 			assign_priority_to_queue(j,
+ + 						queue_priority_mapping[i][0],
+ + 						queue_priority_mapping[i][1]);
+ + 
+ + 		/* Map the channel to param entry if channel mapping logic
+ + 		 * exist
+ + 		 */
+ + 		if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST)
+ + 			map_dmach_param(j);
+ + 
+ + 		for (i = 0; i < info[j].n_region; i++) {
+ + 			edma_write_array2(j, EDMA_DRAE, i, 0, 0x0);
+ + 			edma_write_array2(j, EDMA_DRAE, i, 1, 0x0);
+ + 			edma_write_array(j, EDMA_QRAE, i, 0x0);
+ + 		}
+ + 
+ + 		edma_cc[j]->is_xbar = info[j].is_xbar;
+ + 
+ + 		if (edma_cc[j]->is_xbar) {
+ + 			edma_cc[j]->num_events = info[j].n_events;
+ + 			edma_cc[j]->xbar_event_mapping =
+ + 						info[j].xbar_event_mapping;
+ + 			xbar_event_to_channel_map = info[j].map_xbar_channel;
+ + 		}
+ + 
+ + 		arch_num_cc++;
+ + 	}
+ + 
+ + 	return 0;
+ + 
+ + fail:
+ + 	for (i = 0; i < EDMA_MAX_CC; i++) {
+ + 		if (err_irq[i])
+ + 			free_irq(err_irq[i], &pdev->dev);
+ + 		if (irq[i])
+ + 			free_irq(irq[i], &pdev->dev);
+ + 	}
+ + fail1:
+ + 	for (i = 0; i < EDMA_MAX_CC; i++) {
+ + 		if (r[i])
+ + 			release_mem_region(r[i]->start, len[i]);
+ + 		if (edmacc_regs_base[i])
+ + 			iounmap(edmacc_regs_base[i]);
+ + 		kfree(edma_cc[i]);
+ + 	}
+ + 	pm_runtime_put_sync(&pdev->dev);
+ + 	pm_runtime_disable(&pdev->dev);
+ + 	return status;
+ + }
+ + 
+ + #ifdef CONFIG_PM
+ + static int edma3_suspend(struct platform_device *pdev, pm_message_t state)
+ + {
+ + 	int i, j;
+ + 
+ + 	for (i = 0; i < arch_num_cc; i++) {
+ + 		/* backup channel data */
+ + 		for (j = 0; j < edma_cc[i]->num_channels; j++) {
+ + 			edma_cc[i]->bkp_ch_map[j] = edma_read_array(i,
+ + 							EDMA_DCHMAP, j);
+ + 		}
+ + 
+ + 		/* backup DMA Queue Number */
+ + 		for (j = 0; j < 8; j++) {
+ + 			edma_cc[i]->bkp_que_num[j] = edma_read_array(i,
+ + 							EDMA_DMAQNUM, j);
+ + 		}
+ + 
+ + 		for (j = 0; j < edma_cc[i]->num_region; j++) {
+ + 			/* backup DMA DMA Region Access Enable data */
+ + 			edma_cc[i]->bkp_drae[j] = edma_read_array2(i,
+ + 							EDMA_DRAE, j, 0);
+ + 			edma_cc[i]->bkp_draeh[j] = edma_read_array2(i,
+ + 							EDMA_DRAE, j, 1);
+ + 
+ + 			/* backup DMA QDMA Region Access Enable data */
+ + 			edma_cc[i]->bkp_qrae[j] = edma_read_array(i,
+ + 							EDMA_QRAE, j);
+ + 		}
+ + 
+ + 		/* backup DMA shadow Event Set data */
+ + 		edma_cc[i]->bkp_sh_esr = edma_shadow0_read_array(i, SH_ESR, 0);
+ + 		edma_cc[i]->bkp_sh_esrh = edma_shadow0_read_array(i, SH_ESR, 1);
+ + 
+ + 		/* backup DMA Shadow Event Enable Set data */
+ + 		edma_cc[i]->bkp_sh_eesr = edma_shadow0_read_array(i,
+ + 							SH_EER, 0);
+ + 		edma_cc[i]->bkp_sh_eesrh = edma_shadow0_read_array(i,
+ + 							SH_EER, 1);
+ + 
+ + 		/* backup DMA Shadow Interrupt Enable Set data */
+ + 		edma_cc[i]->bkp_sh_iesr = edma_shadow0_read_array(i,
+ + 							SH_IER, 0);
+ + 		edma_cc[i]->bkp_sh_iesrh = edma_shadow0_read_array(i,
+ + 							SH_IER, 1);
+ + 
+ + 		edma_cc[i]->bkp_que_tc_map = edma_read(i, EDMA_QUETCMAP);
+ + 
+ + 		/* backup DMA Queue Priority data */
+ + 		edma_cc[i]->bkp_que_pri = edma_read(i, EDMA_QUEPRI);
+ + 
+ + 		/* backup paramset */
+ + 		for (j = 0; j < edma_cc[i]->num_slots; j++) {
+ + 			memcpy_fromio(&edma_cc[i]->bkp_prm_set[j],
+ + 				edmacc_regs_base[i] + PARM_OFFSET(j),
+ + 				PARM_SIZE);
+ + 		}
+ + 	}
+ + 
+ + 	pm_runtime_put_sync(&pdev->dev);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static int edma3_resume(struct platform_device *pdev)
+ + {
+ + 	int i, j;
+ + 
+ + 	pm_runtime_get_sync(&pdev->dev);
+ + 
+ + 	for (i = 0; i < arch_num_cc; i++) {
+ + 
+ + 		/* restore channel data */
+ + 		for (j = 0; j < edma_cc[i]->num_channels; j++) {
+ + 			edma_write_array(i, EDMA_DCHMAP, j,
+ + 						edma_cc[i]->bkp_ch_map[j]);
+ + 		}
+ + 
+ + 		/* restore DMA Queue Number */
+ + 		for (j = 0; j < 8; j++) {
+ + 			edma_write_array(i, EDMA_DMAQNUM, j,
+ + 						edma_cc[i]->bkp_que_num[j]);
+ + 		}
+ + 
+ + 		for (j = 0; j < edma_cc[i]->num_region; j++) {
+ + 			/* restore DMA DMA Region Access Enable data */
+ + 			edma_write_array2(i, EDMA_DRAE, j, 0,
+ + 						edma_cc[i]->bkp_drae[j]);
+ + 			edma_write_array2(i, EDMA_DRAE, j, 1,
+ + 						edma_cc[i]->bkp_draeh[j]);
+ + 
+ + 			/* restore DMA QDMA Region Access Enable data */
+ + 			edma_write_array(i, EDMA_QRAE, j,
+ + 						edma_cc[i]->bkp_qrae[j]);
+ + 		}
+ + 
+ + 		/* restore DMA shadow Event Set data */
+ + 		edma_shadow0_write_array(i, SH_ESR, 0, edma_cc[i]->bkp_sh_esr);
+ + 		edma_shadow0_write_array(i, SH_ESR, 1, edma_cc[i]->bkp_sh_esrh);
+ + 
+ + 		/* restore DMA Shadow Event Enable Set data */
+ + 		edma_shadow0_write_array(i, SH_EESR, 0,
+ + 						edma_cc[i]->bkp_sh_eesr);
+ + 		edma_shadow0_write_array(i, SH_EESR, 1,
+ + 						edma_cc[i]->bkp_sh_eesrh);
+ + 
+ + 		/* restore DMA Shadow Interrupt Enable Set data */
+ + 		edma_shadow0_write_array(i, SH_IESR, 0,
+ + 						edma_cc[i]->bkp_sh_iesr);
+ + 		edma_shadow0_write_array(i, SH_IESR, 1,
+ + 						edma_cc[i]->bkp_sh_iesrh);
+ + 
+ + 		edma_write(i, EDMA_QUETCMAP, edma_cc[i]->bkp_que_tc_map);
+ + 
+ + 		/* restore DMA Queue Priority data */
+ + 		edma_write(i, EDMA_QUEPRI, edma_cc[i]->bkp_que_pri);
+ + 
+ + 		/* restore paramset */
+ + 		for (j = 0; j < edma_cc[i]->num_slots; j++) {
+ + 			memcpy_toio(edmacc_regs_base[i] + PARM_OFFSET(j),
+ + 				&edma_cc[i]->bkp_prm_set[j], PARM_SIZE);
+ + 		}
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ + 
+ + #else
+ + #define edma3_suspend	NULL
+ + #define edma3_resume		NULL
+ + #endif
+ + 
+ + static struct platform_driver edma_driver = {
+ + 	.driver.name	= "edma",
+ + 	.suspend	= edma3_suspend,
+ + 	.resume		= edma3_resume,
+ + };
+ + 
+ + static int __init edma_init(void)
+ + {
+ + 	return platform_driver_probe(&edma_driver, edma_probe);
+ + }
+ + subsys_initcall(edma_init);
+ diff -crN linux-3.2.1_o/arch/arm/common/Makefile linux-3.2.1/arch/arm/common/Makefile
+ *** linux-3.2.1_o/arch/arm/common/Makefile	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/arch/arm/common/Makefile	2014-11-25 13:19:14.628036189 +0900
+ ***************
+ *** 17,19 ****
+ --- 17,20 ----
+   obj-$(CONFIG_ARCH_IXP23XX)	+= uengine.o
+   obj-$(CONFIG_PCI_HOST_ITE8152)  += it8152.o
+   obj-$(CONFIG_ARM_TIMER_SP804)	+= timer-sp.o
+ + obj-$(CONFIG_OMAP3_EDMA)	+= edma.o
+ diff -crN linux-3.2.1_o/arch/arm/include/asm/device.h linux-3.2.1/arch/arm/include/asm/device.h
+ *** linux-3.2.1_o/arch/arm/include/asm/device.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/arch/arm/include/asm/device.h	2014-11-25 13:19:14.727075656 +0900
+ ***************
+ *** 18,24 ****
+   struct omap_device;
+   
+   struct pdev_archdata {
+ ! #ifdef CONFIG_ARCH_OMAP
+   	struct omap_device *od;
+   #endif
+   };
+ --- 18,24 ----
+   struct omap_device;
+   
+   struct pdev_archdata {
+ ! #if defined(CONFIG_ARCH_OMAP) || defined(CONFIG_ARCH_CKB)
+   	struct omap_device *od;
+   #endif
+   };
+ diff -crN linux-3.2.1_o/arch/arm/include/asm/pmu.h linux-3.2.1/arch/arm/include/asm/pmu.h
+ *** linux-3.2.1_o/arch/arm/include/asm/pmu.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/arch/arm/include/asm/pmu.h	2014-11-25 13:19:14.740639275 +0900
+ ***************
+ *** 27,39 ****
+   /*
+    * struct arm_pmu_platdata - ARM PMU platform data
+    *
+ !  * @handle_irq: an optional handler which will be called from the interrupt and
+ !  * passed the address of the low level handler, and can be used to implement
+ !  * any platform specific handling before or after calling it.
+    */
+   struct arm_pmu_platdata {
+   	irqreturn_t (*handle_irq)(int irq, void *dev,
+   				  irq_handler_t pmu_handler);
+   };
+   
+   #ifdef CONFIG_CPU_HAS_PMU
+ --- 27,48 ----
+   /*
+    * struct arm_pmu_platdata - ARM PMU platform data
+    *
+ !  * @handle_irq: an optional handler which will be called from the
+ !  *	interrupt and passed the address of the low level handler,
+ !  *	and can be used to implement any platform specific handling
+ !  *	before or after calling it.
+ !  * @enable_irq: an optional handler which will be called after
+ !  *	request_irq and be used to handle some platform specific
+ !  *	irq enablement
+ !  * @disable_irq: an optional handler which will be called before
+ !  *	free_irq and be used to handle some platform specific
+ !  *	irq disablement
+    */
+   struct arm_pmu_platdata {
+   	irqreturn_t (*handle_irq)(int irq, void *dev,
+   				  irq_handler_t pmu_handler);
+ + 	void (*enable_irq)(int irq);
+ + 	void (*disable_irq)(int irq);
+   };
+   
+   #ifdef CONFIG_CPU_HAS_PMU
+ diff -crN linux-3.2.1_o/arch/arm/include/asm/setup.h linux-3.2.1/arch/arm/include/asm/setup.h
+ *** linux-3.2.1_o/arch/arm/include/asm/setup.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/arch/arm/include/asm/setup.h	2014-11-25 13:19:14.743611737 +0900
+ ***************
+ *** 43,48 ****
+ --- 43,52 ----
+   	__u32	start;	/* physical start address */
+   };
+   
+ + 
+ + /* FB TAG */
+ + #define ATAG_FB		0x54411002
+ + 
+   /* VGA text type displays */
+   #define ATAG_VIDEOTEXT	0x54410003
+   
+ ***************
+ *** 225,230 ****
+ --- 229,239 ----
+   extern void early_print(const char *str, ...);
+   extern void dump_machine_table(void);
+   
+ + #ifdef CONFIG_MACH_CKB_3352
+ + extern int ckb_add_fbaddr(phys_addr_t start, phys_addr_t size);
+ + extern int ckb_add_vpifaddr(phys_addr_t start, phys_addr_t size);
+ + #endif
+ + 
+   #endif  /*  __KERNEL__  */
+   
+   #endif
+ diff -crN linux-3.2.1_o/arch/arm/include/asm/unistd.h linux-3.2.1/arch/arm/include/asm/unistd.h
+ *** linux-3.2.1_o/arch/arm/include/asm/unistd.h	2014-11-25 13:15:16.579360537 +0900
+ --- linux-3.2.1/arch/arm/include/asm/unistd.h	2014-11-25 13:19:14.765013614 +0900
+ ***************
+ *** 404,409 ****
+ --- 404,410 ----
+   #define __NR_setns			(__NR_SYSCALL_BASE+375)
+   #define __NR_process_vm_readv		(__NR_SYSCALL_BASE+376)
+   #define __NR_process_vm_writev		(__NR_SYSCALL_BASE+377)
+ + #define __NR_ckb3352_change_mux		(__NR_SYSCALL_BASE+378)
+   
+   /*
+    * The following SWIs are ARM private.
+ diff -crN linux-3.2.1_o/arch/arm/Kconfig linux-3.2.1/arch/arm/Kconfig
+ *** linux-3.2.1_o/arch/arm/Kconfig	2014-11-25 13:15:16.551456648 +0900
+ --- linux-3.2.1/arch/arm/Kconfig	2014-11-25 13:19:14.795074348 +0900
+ ***************
+ *** 938,949 ****
+ --- 938,963 ----
+   	select ARCH_REQUIRE_GPIOLIB
+   	select ARCH_HAS_CPUFREQ
+   	select CLKSRC_MMIO
+ + 	select GENERIC_ALLOCATOR
+   	select GENERIC_CLOCKEVENTS
+   	select HAVE_SCHED_CLOCK
+   	select ARCH_HAS_HOLES_MEMORYMODEL
+   	help
+   	  Support for TI's OMAP platform (OMAP1/2/3/4).
+   
+ + config ARCH_CKB
+ + 	bool "CKB (Computex Kumikomi Board)"
+ + 	select HAVE_CLK
+ + 	select ARCH_REQUIRE_GPIOLIB
+ + 	select ARCH_HAS_CPUFREQ
+ + 	select CLKSRC_MMIO
+ + 	select GENERIC_ALLOCATOR
+ + 	select GENERIC_CLOCKEVENTS
+ + 	select HAVE_SCHED_CLOCK
+ + 	select ARCH_HAS_HOLES_MEMORYMODEL
+ + 	help
+ + 	  Support for Computex Kumikomi Board.
+ + 
+   config PLAT_SPEAR
+   	bool "ST SPEAr"
+   	select ARM_AMBA
+ ***************
+ *** 988,993 ****
+ --- 1002,1009 ----
+   
+   source "arch/arm/mach-bcmring/Kconfig"
+   
+ + source "arch/arm/mach-ckb_3352/Kconfig"
+ + 
+   source "arch/arm/mach-clps711x/Kconfig"
+   
+   source "arch/arm/mach-cns3xxx/Kconfig"
+ ***************
+ *** 1035,1040 ****
+ --- 1051,1057 ----
+   source "arch/arm/mach-netx/Kconfig"
+   
+   source "arch/arm/mach-nomadik/Kconfig"
+ + 
+   source "arch/arm/plat-nomadik/Kconfig"
+   
+   source "arch/arm/plat-omap/Kconfig"
+ diff -crN linux-3.2.1_o/arch/arm/Kconfig.debug linux-3.2.1/arch/arm/Kconfig.debug
+ *** linux-3.2.1_o/arch/arm/Kconfig.debug	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/arch/arm/Kconfig.debug	2014-11-25 13:19:14.816998712 +0900
+ ***************
+ *** 271,274 ****
+ --- 271,280 ----
+   	help
+   	  Perform tests of kprobes API and instruction set simulation.
+   
+ + config DEBUG_JTAG_ENABLE
+ + 	bool "Enable JTAG clock for debugger connectivity"
+ + 	help
+ + 	 Say Y here if you want to enable the JTAG clock to enable
+ + 	 connectivity to a debugger
+ + 
+   endmenu
+ diff -crN linux-3.2.1_o/arch/arm/kernel/calls.S linux-3.2.1/arch/arm/kernel/calls.S
+ *** linux-3.2.1_o/arch/arm/kernel/calls.S	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/arch/arm/kernel/calls.S	2014-11-25 13:19:14.825045240 +0900
+ ***************
+ *** 387,392 ****
+ --- 387,393 ----
+   /* 375 */	CALL(sys_setns)
+   		CALL(sys_process_vm_readv)
+   		CALL(sys_process_vm_writev)
+ + 		CALL(sys_ckb3352_change_mux)
+   #ifndef syscalls_counted
+   .equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls
+   #define syscalls_counted
+ diff -crN linux-3.2.1_o/arch/arm/kernel/setup.c linux-3.2.1/arch/arm/kernel/setup.c
+ *** linux-3.2.1_o/arch/arm/kernel/setup.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/arch/arm/kernel/setup.c	2014-11-25 13:19:14.832518413 +0900
+ ***************
+ *** 640,645 ****
+ --- 640,654 ----
+   
+   __tagtable(ATAG_MEM, parse_tag_mem32);
+   
+ + #ifdef CONFIG_MACH_CKB_3352
+ + static int __init parse_tag_fb(const struct tag *tag)
+ + {
+ + 	return ckb_add_fbaddr(tag->u.mem.start, tag->u.mem.size);
+ + }
+ + 
+ + __tagtable(ATAG_FB, parse_tag_fb);
+ + #endif
+ + 
+   #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
+   struct screen_info screen_info = {
+    .orig_video_lines	= 30,
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/am33xx-smartreflex-class2.c linux-3.2.1/arch/arm/mach-ckb_3352/am33xx-smartreflex-class2.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/am33xx-smartreflex-class2.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/am33xx-smartreflex-class2.c	2014-11-25 13:34:02.060693000 +0900
+ ***************
+ *** 0 ****
+ --- 1,1055 ----
+ + /*
+ +  * SmartReflex Voltage Control driver
+ +  *
+ +  * Copyright (C) 2012 Texas Instruments, Inc. - http://www.ti.com/
+ +  * Author: Greg Guyotte <gguyotte@ti.com> (modified for AM33xx)
+ +  *
+ +  * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
+ +  * Author: AnilKumar Ch <anilkumar@ti.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #include <linux/kernel.h>
+ + #include <linux/init.h>
+ + #include <linux/module.h>
+ + #include <linux/interrupt.h>
+ + #include <linux/clk.h>
+ + #include <linux/io.h>
+ + #include <linux/debugfs.h>
+ + #include <linux/slab.h>
+ + #include <linux/regulator/consumer.h>
+ + #include <linux/cpufreq.h>
+ + #include <linux/opp.h>
+ + 
+ + #include <plat/common.h>
+ + #include <plat/smartreflex.h>
+ + 
+ + #include "control.h"
+ + #include "voltage.h"
+ + 
+ + #define CLK_NAME_LEN		40
+ + 
+ + static inline void sr_write_reg(struct am33xx_sr *sr, int offset, u32 value,
+ + 					u32 srid)
+ + {
+ + 	writel(value, sr->sen[srid].base + offset);
+ + }
+ + 
+ + static inline void sr_modify_reg(struct am33xx_sr *sr, int offset, u32 mask,
+ + 				u32 value, u32 srid)
+ + {
+ + 	u32 reg_val;
+ + 
+ + 	reg_val = readl(sr->sen[srid].base + offset);
+ + 	reg_val &= ~mask;
+ + 	reg_val |= (value&mask);
+ + 
+ + 	writel(reg_val, sr->sen[srid].base + offset);
+ + }
+ + 
+ + static inline u32 sr_read_reg(struct am33xx_sr *sr, int offset, u32 srid)
+ + {
+ + 	return readl(sr->sen[srid].base + offset);
+ + }
+ + 
+ + static void cal_reciprocal(u32 sensor, u32 *sengain, u32 *rnsen) {
+ +          u32 gn, rn, mul;
+ + 
+ +          for (gn = 0; gn < GAIN_MAXLIMIT; gn++) {
+ +                  mul = 1 << (gn + 8);
+ +                  rn = mul / sensor;
+ +                  if (rn < R_MAXLIMIT) {
+ +                          *sengain = gn;
+ +                          *rnsen = rn;
+ +                  }
+ +          }
+ + }
+ + 
+ + static u32 cal_test_nvalue(u32 sennval, u32 senpval) {
+ +          u32 senpgain=0, senngain=0;
+ +          u32 rnsenp=0, rnsenn=0;
+ + 
+ +          /* Calculating the gain and reciprocal of the SenN and SenP values */
+ +          cal_reciprocal(senpval, &senpgain, &rnsenp);
+ +          cal_reciprocal(sennval, &senngain, &rnsenn);
+ + 
+ +          return (senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
+ +                  (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
+ +                  (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
+ +                  (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT);
+ + }
+ + 
+ + static unsigned int sr_adjust_efuse_nvalue(unsigned int opp_no,
+ +                                                  unsigned int orig_opp_nvalue,
+ +                                                  unsigned int mv_delta) {
+ +          unsigned int new_opp_nvalue;
+ +          unsigned int senp_gain, senn_gain, rnsenp, rnsenn, pnt_delta, nnt_delta;
+ +          unsigned int new_senn, new_senp, senn, senp;
+ + 
+ +          /* calculate SenN and SenP from the efuse value */
+ +          senp_gain = ((orig_opp_nvalue >> 20) & 0xf);
+ +          senn_gain = ((orig_opp_nvalue >> 16) & 0xf);
+ +          rnsenp = ((orig_opp_nvalue >> 8) & 0xff);
+ +          rnsenn = (orig_opp_nvalue & 0xff);
+ + 
+ +          senp = ((1<<(senp_gain+8))/(rnsenp));
+ +          senn = ((1<<(senn_gain+8))/(rnsenn));
+ + 
+ +          /* calculate the voltage delta */
+ +          pnt_delta = (26 * mv_delta)/10;
+ +          nnt_delta = (3 * mv_delta);
+ + 
+ +          /* now lets add the voltage delta to the sensor values */
+ +          new_senn = senn + nnt_delta;
+ +          new_senp = senp + pnt_delta;
+ + 
+ +          new_opp_nvalue = cal_test_nvalue(new_senn, new_senp);
+ + 
+ +          printk("Compensating OPP%d for %dmV Orig nvalue:0x%x New nvalue:0x%x \n",
+ +                          opp_no, mv_delta, orig_opp_nvalue, new_opp_nvalue);
+ + 
+ +          return new_opp_nvalue;
+ + }
+ + 
+ + /* irq_sr_reenable - Re-enable SR interrupts (triggered by delayed work queue)
+ +  * @work:	pointer to work_struct embedded in am33xx_sr_sensor struct
+ +  *
+ +  * While servicing the IRQ, this function is added to the delayed work queue.
+ +  * This gives time for the voltage change to settle before we re-enable
+ +  * the interrupt.
+ +  */
+ + static void irq_sr_reenable(struct work_struct *work)
+ + {
+ +         u32 srid;
+ + 	struct am33xx_sr_sensor *sens;
+ +         struct am33xx_sr *sr;
+ + 
+ +         sens = container_of((void *)work, struct am33xx_sr_sensor,
+ +                 work_reenable);
+ + 
+ +         srid = sens->sr_id;
+ + 
+ +         sr = container_of((void *)sens, struct am33xx_sr, sen[srid]);
+ + 
+ +         dev_dbg(&sr->pdev->dev, "%s: SR %d\n", __func__, srid);
+ + 
+ +         /* Must clear IRQ status */
+ +         sens->irq_status = 0;
+ + 
+ +         /* Re-enable the interrupt */
+ + 	sr_modify_reg(sr, IRQENABLE_SET, IRQENABLE_MCUBOUNDSINT,
+ + 		IRQENABLE_MCUBOUNDSINT, srid);
+ + 
+ + 	/* Restart the module after voltage set */
+ + 	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE,
+ + 		SRCONFIG_SRENABLE, srid);
+ + }
+ + 
+ + /* get_errvolt - get error voltage from SR error register
+ +  * @sr:		contains SR driver data
+ +  * @srid:	contains the srid, indicates which SR moduel lswe are using
+ +  *
+ +  * Read the error from SENSOR error register and then convert
+ +  * to voltage delta, return value is the voltage delta in micro
+ +  * volt.
+ +  */
+ + static int get_errvolt(struct am33xx_sr *sr, s32 srid)
+ + {
+ +         struct am33xx_sr_sensor *sens;
+ + 	int senerror_reg;
+ + 	s32 uvoltage;
+ + 	s8 terror;
+ + 
+ +         sens = &sr->sen[srid];
+ + 
+ + 	senerror_reg = sr_read_reg(sr, SENERROR_V2, srid);
+ + 	senerror_reg = (senerror_reg & 0x0000FF00);
+ + 	terror = (s8)(senerror_reg >> 8);
+ + 
+ +         /* math defined in SR functional spec */
+ + 	uvoltage = ((terror) * sr->uvoltage_step_size) >> 7;
+ + 	uvoltage = uvoltage * sens->opp_data[sens->curr_opp].e2v_gain;
+ + 
+ + 	return uvoltage;
+ + }
+ + 
+ + /* set_voltage - Schedule task for setting the voltage
+ +  * @work:	pointer to the work structure
+ +  *
+ +  * Voltage is set based on previous voltage and calculated
+ +  * voltage error.
+ +  *
+ +  * Generic voltage regulator set voltage is used for changing
+ +  * the voltage to new value.  Could potentially use voltdm_scale
+ +  * but at time of testing voltdm was not populated with volt_data.
+ +  *
+ +  * Disabling the module before changing the voltage, this is
+ +  * needed for not generating interrupt during voltage change,
+ +  * enabling after voltage change. This will also take care of
+ +  * resetting the SR registers.
+ +  */
+ + static void set_voltage(struct work_struct *work)
+ + {
+ + 	struct am33xx_sr *sr;
+ + 	int prev_volt, new_volt, i, ret;
+ + 	s32 delta_v;
+ + 
+ + 	sr = container_of((void *)work, struct am33xx_sr, work);
+ + 
+ +         for (i = 0; i < sr->no_of_sens; i++) {
+ +                 if (sr->sen[i].irq_status != 1)
+ +                         continue;
+ + 
+ +                 /* Get the current voltage from PMIC */
+ +                 prev_volt = regulator_get_voltage(sr->sen[i].reg);
+ + 
+ +                 if (prev_volt < 0) {
+ +                         dev_err(&sr->pdev->dev,
+ +                                 "%s: SR %d: regulator_get_voltage error %d\n",
+ +                                 __func__, i, prev_volt);
+ + 
+ +                         goto reenable;
+ +                 }
+ + 
+ +         	delta_v = get_errvolt(sr, i);
+ +                 new_volt = prev_volt + delta_v;
+ + 
+ +                 /* this is the primary output for debugging SR activity */
+ +                 dev_dbg(&sr->pdev->dev,
+ +                         "%s: SR %d: prev volt=%d, delta_v=%d, req_volt=%d\n",
+ +                          __func__, i, prev_volt, delta_v, new_volt);
+ + 
+ + 	        /* Clear the counter, SR module disable */
+ + 	        sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE,
+ + 			~SRCONFIG_SRENABLE, i);
+ + 
+ +                 if (delta_v != 0) {
+ + 	                ret = regulator_set_voltage(sr->sen[i].reg, new_volt,
+ +                                 new_volt + sr->uvoltage_step_size);
+ + 
+ +                         if (ret < 0)
+ +                                 dev_err(&sr->pdev->dev,
+ +                                 "%s: regulator_set_voltage failed! (err %d)\n",
+ +                                 __func__, ret);
+ +                 }
+ + reenable:
+ +                 /* allow time for voltage to settle before re-enabling SR
+ +                    module and interrupt */
+ +                 schedule_delayed_work(&sr->sen[i].work_reenable,
+ +                         msecs_to_jiffies(sr->irq_delay));
+ +         }
+ + }
+ + 
+ + /* sr_class2_irq - sr irq handling
+ +  * @irq:	Number of the irq serviced
+ +  * @data:	data contains the SR driver structure
+ +  *
+ +  * Smartreflex IRQ handling for class2 IP, once the IRQ handler
+ +  * is here then disable the interrupt and re-enable after some
+ +  * time. This is the work around for handling both interrupts,
+ +  * while one got satisfied with the voltage change but not the
+ +  * other. The same logic helps the case where PMIC cannot set
+ +  * the exact voltage requested by SR IP
+ +  *
+ +  * Schedule work only if both interrupts are serviced
+ +  *
+ +  * Note that same irq handler is used for both the interrupts,
+ +  * needed for decision making for voltage change
+ +  */
+ + static irqreturn_t sr_class2_irq(int irq, void *data)
+ + {
+ + 	u32 srid;
+ +         struct am33xx_sr *sr;
+ +         struct am33xx_sr_sensor *sr_sensor = (struct am33xx_sr_sensor *)data;
+ + 
+ +         srid = sr_sensor->sr_id;
+ + 
+ +         sr = container_of(data, struct am33xx_sr, sen[srid]);
+ + 
+ + 	sr->sen[srid].irq_status = 1;
+ + 
+ + 	/* Clear MCUBounds Interrupt */
+ + 	sr_modify_reg(sr, IRQSTATUS, IRQSTATUS_MCBOUNDSINT,
+ + 			IRQSTATUS_MCBOUNDSINT, srid);
+ + 
+ + 	/* Disable the interrupt and re-enable in set_voltage() */
+ + 	sr_modify_reg(sr, IRQENABLE_CLR, IRQENABLE_MCUBOUNDSINT,
+ + 			IRQENABLE_MCUBOUNDSINT, srid);
+ + 
+ +         /* Causes set_voltage() to get called at a later time.  Set_voltage()
+ +            will check the irq_status flags to determine which SR needs to
+ +            be serviced.  This was previously done with schedule_work, but
+ +            I observed a crash in set_voltage() when changing OPPs on weak
+ +            silicon, which may have been related to insufficient voltage
+ +            settling time for OPP change.  This additional delay avoids the
+ +            crash. */
+ +         schedule_delayed_work(&sr->work,
+ +                         msecs_to_jiffies(250));
+ + 
+ + 	return IRQ_HANDLED;
+ + }
+ + 
+ + static int sr_clk_enable(struct am33xx_sr *sr, u32 srid)
+ + {
+ + 	if (clk_enable(sr->sen[srid].fck) != 0) {
+ + 		dev_err(&sr->pdev->dev, "%s: Could not enable sr_fck\n",
+ + 					__func__);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static int sr_clk_disable(struct am33xx_sr *sr, u32 srid)
+ + {
+ + 	clk_disable(sr->sen[srid].fck);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static inline int sr_set_nvalues(struct am33xx_sr *sr, u32 srid)
+ + {
+ +         int i;
+ +         struct am33xx_sr_sensor *sens = &sr->sen[srid];
+ + 
+ +         for (i = 0; i < sens->no_of_opps; i++) {
+ +         	/* Read nTarget value form EFUSE register*/
+ + 	        sens->opp_data[i].nvalue = readl(AM33XX_CTRL_REGADDR
+ + 			(sens->opp_data[i].efuse_offs)) & 0xFFFFFF;
+ + 
+ +                 /* validate nTarget value */
+ +                 if (sens->opp_data[i].nvalue == 0)
+ +                         return -EINVAL;
+ + 
+ +                 /* adjust nTarget based on margin in mv */
+ +                 sens->opp_data[i].adj_nvalue = sr_adjust_efuse_nvalue(i,
+ +                         sens->opp_data[i].nvalue,
+ +                         sens->opp_data[i].margin);
+ + 
+ +                 dev_dbg(&sr->pdev->dev,
+ +                         "NValueReciprocal value (from efuse) = %08x\n",
+ +                         sens->opp_data[i].nvalue);
+ + 
+ +                 dev_dbg(&sr->pdev->dev,
+ +                         "Adjusted NValueReciprocal value = %08x\n",
+ +                         sens->opp_data[i].adj_nvalue);
+ +         }
+ + 	return 0;
+ + }
+ + 
+ + /* sr_configure - Configure SR module to work in Error generator mode
+ +  * @sr:		contains SR driver data
+ +  * @srid:	contains the srid, specify whether it is CORE or MPU
+ +  *
+ +  * Configure the corresponding values to SR module registers for
+ +  * operating SR module in Error Generator mode.
+ +  */
+ + static void sr_configure(struct am33xx_sr *sr, u32 srid)
+ + {
+ +         struct am33xx_sr_sensor *sens = &sr->sen[srid];
+ + 
+ + 	/* Configuring the SR module with clock length, enabling the
+ + 	 * error generator, enable SR module, enable individual N and P
+ + 	 * sensors
+ + 	 */
+ + 	sr_write_reg(sr, SRCONFIG, (SRCLKLENGTH_125MHZ_SYSCLK |
+ + 		SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN |
+ + 		(sens->senn_en << SRCONFIG_SENNENABLE_V2_SHIFT) |
+ + 		(sens->senp_en << SRCONFIG_SENPENABLE_V2_SHIFT)),
+ + 		srid);
+ + 
+ + 	/* Configuring the Error Generator */
+ + 	sr_modify_reg(sr, ERRCONFIG_V2, (SR_ERRWEIGHT_MASK |
+ + 		SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
+ + 		((sens->opp_data[sens->curr_opp].err_weight <<
+ +                         ERRCONFIG_ERRWEIGHT_SHIFT) |
+ + 		(sens->opp_data[sens->curr_opp].err_maxlimit <<
+ +                         ERRCONFIG_ERRMAXLIMIT_SHIFT) |
+ + 		(sens->opp_data[sens->curr_opp].err_minlimit <<
+ +                         ERRCONFIG_ERRMINLIMIT_SHIFT)),
+ + 		srid);
+ + }
+ + 
+ + /* sr_enable - Enable SR module
+ +  * @sr:		contains SR driver data
+ +  * @srid:	contains the srid, specify whether it is CORE or MPU
+ +  *
+ +  * Enable SR module by writing nTarget values to corresponding SR
+ +  * NVALUERECIPROCAL register, enable the interrupt and enable SR
+ +  */
+ + static void sr_enable(struct am33xx_sr *sr, u32 srid)
+ + {
+ +         struct am33xx_sr_sensor *sens;
+ + 
+ +         sens = &sr->sen[srid];
+ + 
+ + 	/* Check if SR is already enabled. If yes do nothing */
+ + 	if (sr_read_reg(sr, SRCONFIG, srid) & SRCONFIG_SRENABLE)
+ + 		return;
+ + 
+ + 	if (sens->opp_data[sens->curr_opp].nvalue == 0)
+ + 		dev_err(&sr->pdev->dev,
+ +                         "%s: OPP doesn't support SmartReflex\n", __func__);
+ + 
+ + 	/* Writing the nReciprocal value to the register */
+ + 	sr_write_reg(sr, NVALUERECIPROCAL,
+ +                 sens->opp_data[sens->curr_opp].adj_nvalue, srid);
+ + 
+ + 	/* Enable the interrupt */
+ + 	sr_modify_reg(sr, IRQENABLE_SET, IRQENABLE_MCUBOUNDSINT,
+ + 				IRQENABLE_MCUBOUNDSINT, srid);
+ + 
+ + 	/* SRCONFIG - enable SR */
+ + 	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE,
+ + 				SRCONFIG_SRENABLE, srid);
+ + }
+ + 
+ + /* sr_disable - Disable SR module
+ +  * @sr:		contains SR driver data
+ +  * @srid:	contains the srid, specify whether it is CORE or MPU
+ +  *
+ +  * Disable SR module by disabling the interrupt and Smartreflex module
+ +  */
+ + static void sr_disable(struct am33xx_sr *sr, u32 srid)
+ + {
+ + 	/* Disable the interrupt */
+ + 	sr_modify_reg(sr, IRQENABLE_CLR, IRQENABLE_MCUBOUNDSINT,
+ + 				IRQENABLE_MCUBOUNDSINT, srid);
+ + 
+ + 	/* SRCONFIG - disable SR */
+ + 	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE,
+ + 				~SRCONFIG_SRENABLE, srid);
+ + }
+ + 
+ + /* sr_start_vddautocomp - Start VDD auto compensation
+ +  * @sr:		contains SR driver data
+ +  *
+ +  * This is the starting point for AVS enable from user space.
+ +  * Also used to re-enable SR after OPP change.
+ +  */
+ + static void sr_start_vddautocomp(struct am33xx_sr *sr)
+ + {
+ + 	int i;
+ + 
+ + 	if ((sr->sen[SR_CORE].opp_data[0].nvalue == 0) ||
+ +                 (sr->sen[SR_MPU].opp_data[0].nvalue == 0)) {
+ + 		dev_err(&sr->pdev->dev, "SR module not enabled, nTarget"
+ + 					" values are not found\n");
+ + 		return;
+ + 	}
+ + 
+ + 	if (sr->autocomp_active == 1) {
+ + 		dev_warn(&sr->pdev->dev, "SR VDD autocomp already active\n");
+ + 		return;
+ + 	}
+ + 
+ + 	for (i = 0; i < sr->no_of_sens; i++) {
+ +                	/* Read current regulator value and voltage */
+ + 	        sr->sen[i].init_volt_mv = regulator_get_voltage(sr->sen[i].reg);
+ + 
+ +                 dev_dbg(&sr->pdev->dev, "%s: regulator %d, init_volt = %d\n",
+ +                         __func__, i, sr->sen[i].init_volt_mv);
+ + 
+ + 		if (sr_clk_enable(sr, i))
+ +                         return;
+ + 		sr_configure(sr, i);
+ + 		sr_enable(sr, i);
+ + 	}
+ + 
+ + 	sr->autocomp_active = 1;
+ + }
+ + 
+ + /* sr_stop_vddautocomp - Stop VDD auto compensation
+ +  * @sr:		contains SR driver data
+ +  *
+ +  * This is the ending point during SR disable from user space.
+ +  * Also used to disable SR after OPP change.
+ +  */
+ + static void sr_stop_vddautocomp(struct am33xx_sr *sr)
+ + {
+ + 	int i;
+ + 
+ + 	if (sr->autocomp_active == 0) {
+ + 		dev_warn(&sr->pdev->dev, "SR VDD autocomp is not active\n");
+ + 		return;
+ + 	}
+ + 
+ +         /* cancel bottom half interrupt handlers that haven't run yet */
+ + 	cancel_delayed_work_sync(&sr->work);
+ + 
+ + 	for (i = 0; i < sr->no_of_sens; i++) {
+ +                 /* cancel any outstanding SR IRQ re-enables on work queue */
+ +                 cancel_delayed_work_sync(&sr->sen[i].work_reenable);
+ + 		sr_disable(sr, i);
+ + 		sr_clk_disable(sr, i);
+ + 	}
+ + 
+ + 	sr->autocomp_active = 0;
+ + }
+ + 
+ + /* am33xx_sr_autocomp_show - Store user input value and stop SR
+ +  * @data:		contains SR driver data
+ +  * @val:		pointer to store autocomp_active status
+ +  *
+ +  * This is the Debug Fs enteries to show whether SR is enabled
+ +  * or disabled
+ +  */
+ + static int am33xx_sr_autocomp_show(void *data, u64 *val)
+ + {
+ + 	struct am33xx_sr *sr_info = (struct am33xx_sr *) data;
+ + 
+ + 	*val = (u64) sr_info->autocomp_active;
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static int am33xx_sr_margin_show(void *data, u64 *val)
+ + {
+ +         struct am33xx_sr_opp_data *sr_opp_data = (struct am33xx_sr_opp_data *)data;
+ + 
+ + 	*val = (u64) sr_opp_data->margin;
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static int am33xx_sr_margin_update(void *data, u64 val)
+ + {
+ +         struct am33xx_sr_opp_data *sr_opp_data =
+ +                 (struct am33xx_sr_opp_data *)data;
+ +         struct am33xx_sr_sensor *sr_sensor;
+ +         struct am33xx_sr *sr_info;
+ + 
+ +         /* work back to the sr_info pointer */
+ +         sr_sensor = container_of((void *)sr_opp_data, struct am33xx_sr_sensor,
+ +                 opp_data[sr_opp_data->opp_id]);
+ + 
+ +         sr_info = container_of((void *)sr_sensor, struct am33xx_sr,
+ +                 sen[sr_sensor->sr_id]);
+ + 
+ +         /* store the value of margin */
+ +         sr_opp_data->margin = (s32)val;
+ + 
+ +         dev_warn(&sr_info->pdev->dev, "%s: new margin=%d, srid=%d, opp=%d\n",
+ +                 __func__, sr_opp_data->margin, sr_sensor->sr_id,
+ +                 sr_opp_data->opp_id);
+ + 
+ +         /* updata ntarget values based upon new margin */
+ +         if (sr_set_nvalues(sr_info, sr_sensor->sr_id) == -EINVAL)
+ +                 dev_err(&sr_info->pdev->dev,
+ +                         "%s: Zero NValue read from EFUSE\n", __func__);
+ + 
+ +         /* restart SmartReflex to adapt to new values */
+ +         sr_stop_vddautocomp(sr_info);
+ +         sr_start_vddautocomp(sr_info);
+ + 
+ +         return 0;
+ + }
+ + 
+ + /* am33xx_sr_autocomp_store - Store user input and start SR
+ +  * @data:		contains SR driver data
+ +  * @val:		contains the value pased by user
+ +  *
+ +  * This is the Debug Fs enteries to store user input and
+ +  * enable smartreflex.
+ +  */
+ + static int am33xx_sr_autocomp_store(void *data, u64 val)
+ + {
+ + 	struct am33xx_sr *sr_info = (struct am33xx_sr *) data;
+ + 
+ + 	/* Sanity check */
+ + 	if (val && (val != 1)) {
+ + 		dev_warn(&sr_info->pdev->dev, "%s: Invalid argument %llu\n",
+ + 		        __func__, val);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	if (!val) {
+ +                 sr_info->disabled_by_user = 1;
+ + 		sr_stop_vddautocomp(sr_info);
+ +         }
+ + 	else {
+ +                 sr_info->disabled_by_user = 0;
+ + 		sr_start_vddautocomp(sr_info);
+ +         }
+ + 
+ + 	return 0;
+ + }
+ + 
+ + DEFINE_SIMPLE_ATTRIBUTE(sr_fops, am33xx_sr_autocomp_show,
+ + 		am33xx_sr_autocomp_store, "%llu\n");
+ + 
+ + /* sr_curr_volt_show - Show current voltage value
+ +  * @data:		contains SR driver data
+ +  * @val:		pointer to store current voltage value
+ +  *
+ +  * Read the current voltage value and display the same on console
+ +  * This is used in debugfs entries
+ +  */
+ + static int am33xx_sr_curr_volt_show(void *data, u64 *val)
+ + {
+ + 	struct am33xx_sr_sensor *sr_sensor = (struct am33xx_sr_sensor *) data;
+ + 
+ + 	*val = (u64) regulator_get_voltage(sr_sensor->reg);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + DEFINE_SIMPLE_ATTRIBUTE(curr_volt_fops, am33xx_sr_curr_volt_show,
+ + 		NULL, "%llu\n");
+ + 
+ + DEFINE_SIMPLE_ATTRIBUTE(margin_fops, am33xx_sr_margin_show,
+ + 		am33xx_sr_margin_update, "%llu\n");
+ + 
+ + #ifdef CONFIG_DEBUG_FS
+ + /* sr_debugfs_entries - Create debugfs entries
+ +  * @sr_info:		contains SR driver data
+ +  *
+ +  * Create debugfs entries, which is exposed to user for knowing
+ +  * the current status. Some of the parameters can change during
+ +  * run time
+ +  */
+ + static int sr_debugfs_entries(struct am33xx_sr *sr_info)
+ + {
+ +         struct am33xx_sr_sensor *sens;
+ + 	struct dentry *dbg_dir, *sen_dir, *opp_dir;
+ + 	int i, j;
+ + 
+ + 	dbg_dir = debugfs_create_dir("smartreflex", NULL);
+ + 	if (IS_ERR(dbg_dir)) {
+ + 		dev_err(&sr_info->pdev->dev, "%s: Unable to create debugfs"
+ + 				" directory\n", __func__);
+ + 		return PTR_ERR(dbg_dir);
+ + 	}
+ + 
+ + 	(void) debugfs_create_file("autocomp", S_IRUGO | S_IWUGO, dbg_dir,
+ + 				(void *)sr_info, &sr_fops);
+ +         (void) debugfs_create_u32("interrupt_delay", S_IRUGO | S_IWUGO,
+ + 				dbg_dir, &sr_info->irq_delay);
+ + 
+ + 	for (i = 0; i < sr_info->no_of_sens; i++) {
+ +                 sens = &sr_info->sen[i];
+ + 		sen_dir = debugfs_create_dir(sens->name, dbg_dir);
+ + 		if (IS_ERR(sen_dir)) {
+ + 			dev_err(&sr_info->pdev->dev, "%s: Unable to create"
+ + 				" debugfs directory\n", __func__);
+ + 			return PTR_ERR(sen_dir);
+ + 		}
+ + 
+ +                 (void)debugfs_create_u32("initial_voltage", S_IRUGO, sen_dir,
+ + 				&sens->init_volt_mv);
+ + 	        (void)debugfs_create_file("current_voltage", S_IRUGO, sen_dir,
+ + 				(void *)sens, &curr_volt_fops);
+ + 
+ +                 for (j = 0; j < sr_info->sen[i].no_of_opps; j++) {
+ +                         char tmp[20];
+ + 
+ +                         sprintf(&tmp[0], "opp%d", j);
+ +                         opp_dir = debugfs_create_dir(tmp, sen_dir);
+ +                         if (IS_ERR(opp_dir)) {
+ +         			dev_err(&sr_info->pdev->dev,
+ +                                         "%s: Unable to create debugfs directory\n",
+ +                                         __func__);
+ +         			return PTR_ERR(opp_dir);
+ +         		}
+ + 
+ +                         (void)debugfs_create_file("margin", S_IRUGO | S_IWUGO,
+ + 	        	       opp_dir, (void *)&sens->opp_data[j],
+ +                                &margin_fops);
+ +                         (void)debugfs_create_x32("err2voltgain",
+ +                                S_IRUGO | S_IWUGO,
+ +         		       opp_dir,
+ +                                &sens->opp_data[j].e2v_gain);
+ +         		(void)debugfs_create_x32("nvalue", S_IRUGO,
+ +         		       opp_dir,
+ +                                &sens->opp_data[j].nvalue);
+ +                         (void)debugfs_create_x32("adj_nvalue", S_IRUGO,
+ +         		       opp_dir,
+ +                                &sens->opp_data[j].adj_nvalue);
+ +                 }
+ + 	}
+ + 	return 0;
+ + }
+ + #else
+ + static int sr_debugfs_entries(struct am33xx_sr *sr_info)
+ + {
+ + 	return 0;
+ + }
+ + #endif
+ + 
+ + #ifdef CONFIG_CPU_FREQ
+ + 
+ + /* Find and return current OPP.  This should change to use system APIs,
+ +    but voltdm is not currently populated, and opp APIs are also not working. */
+ + static int get_current_opp(struct am33xx_sr *sr, u32 srid, u32 freq)  {
+ +         int i;
+ + 
+ +         for (i = 0; i < sr->sen[srid].no_of_opps; i++) {
+ +                 if (sr->sen[srid].opp_data[i].frequency == freq)
+ +                         return i;
+ +         }
+ + 
+ +         return -EINVAL;
+ + }
+ + 
+ + static int am33xx_sr_cpufreq_transition(struct notifier_block *nb,
+ + 					  unsigned long val, void *data)
+ + {
+ +         struct am33xx_sr *sr;
+ +         struct cpufreq_freqs *cpu;
+ + 
+ + 	sr = container_of(nb, struct am33xx_sr, freq_transition);
+ + 
+ +         /* We are required to disable SR while OPP change is occurring */
+ + 	if (val == CPUFREQ_PRECHANGE) {
+ +                 dev_dbg(&sr->pdev->dev, "%s: prechange\n", __func__);
+ +                 sr_stop_vddautocomp(sr);
+ + 	} else if (val == CPUFREQ_POSTCHANGE) {
+ +                 cpu = (struct cpufreq_freqs *)data;
+ +                 dev_dbg(&sr->pdev->dev,
+ +                         "%s: postchange, cpu=%d, old=%d, new=%d\n",
+ +                         __func__, cpu->cpu, cpu->old, cpu->new);
+ + 
+ +                 /* update current OPP */
+ +                 sr->sen[SR_MPU].curr_opp = get_current_opp(sr, SR_MPU,
+ +                         cpu->new*1000);
+ +                 if (sr->sen[SR_MPU].curr_opp == -EINVAL) {
+ +                         dev_err(&sr->pdev->dev, "%s: cannot determine opp\n",
+ +                                 __func__);
+ +                         return -EINVAL;
+ +                 }
+ + 
+ +                 dev_dbg(&sr->pdev->dev, "%s: postchange, new opp=%d\n",
+ +                         __func__, sr->sen[SR_MPU].curr_opp);
+ + 
+ +                 /* this handles the case when the user has disabled SR via
+ +                    debugfs, therefore we do not want to enable SR */
+ +                 if (sr->disabled_by_user == 0)
+ +                         sr_start_vddautocomp(sr);
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static inline int am33xx_sr_cpufreq_register(struct am33xx_sr *sr)
+ + {
+ +         sr->freq_transition.notifier_call = am33xx_sr_cpufreq_transition;
+ + 
+ + 	return cpufreq_register_notifier(&sr->freq_transition,
+ + 					 CPUFREQ_TRANSITION_NOTIFIER);
+ + }
+ + 
+ + static inline void am33xx_sr_cpufreq_deregister(struct am33xx_sr *sr)
+ + {
+ + 	cpufreq_unregister_notifier(&sr->freq_transition,
+ + 				    CPUFREQ_TRANSITION_NOTIFIER);
+ + }
+ + 
+ + #endif
+ + 
+ + static int __init am33xx_sr_probe(struct platform_device *pdev)
+ + {
+ + 	struct am33xx_sr *sr_info;
+ + 	struct am33xx_sr_platform_data *pdata;
+ + 	struct resource *res[MAX_SENSORS];
+ + 	int irq;
+ + 	int ret;
+ + 	int i,j;
+ + 
+ + 	sr_info = kzalloc(sizeof(struct am33xx_sr), GFP_KERNEL);
+ + 	if (!sr_info) {
+ + 		dev_err(&pdev->dev, "%s: unable to allocate sr_info\n",
+ + 					__func__);
+ + 		return -ENOMEM;
+ + 	}
+ + 
+ + 	pdata = pdev->dev.platform_data;
+ + 	if (!pdata) {
+ + 		dev_err(&pdev->dev, "%s: platform data missing\n", __func__);
+ + 		ret = -EINVAL;
+ + 		goto err_free_sr_info;
+ + 	}
+ + 
+ + 	sr_info->pdev = pdev;
+ + 	sr_info->sen[SR_CORE].name = "smartreflex0";
+ + 	sr_info->sen[SR_MPU].name = "smartreflex1";
+ + 	sr_info->ip_type = pdata->ip_type;
+ +         sr_info->irq_delay = pdata->irq_delay;
+ +         sr_info->no_of_sens = pdata->no_of_sens;
+ +         sr_info->no_of_vds = pdata->no_of_vds;
+ + 	sr_info->uvoltage_step_size = pdata->vstep_size_uv;
+ + 	sr_info->autocomp_active = false;
+ +         sr_info->disabled_by_user = false;
+ + 
+ + 	for (i = 0; i < sr_info->no_of_sens; i++) {
+ +                 u32 curr_freq=0;
+ + 
+ +                 sr_info->sen[i].reg_name = pdata->vd_name[i];
+ + 
+ +                 /* this should be determined from voltdm or opp layer, but
+ +                    those approaches are not working */
+ +                 sr_info->sen[i].no_of_opps = pdata->sr_sdata[i].no_of_opps;
+ +                 sr_info->sen[i].sr_id = i;
+ + 
+ +                 /* Reading per OPP Values */
+ +                 for (j = 0; j < sr_info->sen[i].no_of_opps; j++) {
+ +         		sr_info->sen[i].opp_data[j].efuse_offs =
+ +                                 pdata->sr_sdata[i].sr_opp_data[j].efuse_offs;
+ +                         sr_info->sen[i].opp_data[j].e2v_gain =
+ +                                 pdata->sr_sdata[i].sr_opp_data[j].e2v_gain;
+ +         		sr_info->sen[i].opp_data[j].err_weight =
+ +                                 pdata->sr_sdata[i].sr_opp_data[j].err_weight;
+ +         		sr_info->sen[i].opp_data[j].err_minlimit =
+ +                                 pdata->sr_sdata[i].sr_opp_data[j].err_minlimit;
+ +         		sr_info->sen[i].opp_data[j].err_maxlimit =
+ +                                 pdata->sr_sdata[i].sr_opp_data[j].err_maxlimit;
+ +                         sr_info->sen[i].opp_data[j].margin =
+ +                                 pdata->sr_sdata[i].sr_opp_data[j].margin;
+ +                         sr_info->sen[i].opp_data[j].nominal_volt =
+ +                                 pdata->sr_sdata[i].sr_opp_data[j].nominal_volt;
+ +                         sr_info->sen[i].opp_data[j].frequency =
+ +                                 pdata->sr_sdata[i].sr_opp_data[j].frequency;
+ +                         sr_info->sen[i].opp_data[j].opp_id = j;
+ +                 }
+ + 
+ +                 if (i == SR_MPU) {
+ +                         /* hardcoded CPU NR */
+ +                         curr_freq = cpufreq_get(0);
+ + 
+ +                         /* update current OPP */
+ +                         sr_info->sen[i].curr_opp = get_current_opp(sr_info, i,
+ +                                         curr_freq*1000);
+ +                         if (sr_info->sen[i].curr_opp == -EINVAL) {
+ +                                 dev_err(&sr_info->pdev->dev,
+ +                                         "%s: cannot determine opp\n",__func__);
+ +                                 ret = -EINVAL;
+ +                                 goto err_free_sr_info;
+ +                         }
+ +                 } else {
+ +                         sr_info->sen[i].curr_opp =
+ +                                 pdata->sr_sdata[i].default_opp;
+ +                 }
+ + 
+ +                 dev_dbg(&pdev->dev,
+ +                         "%s: SR%d, curr_opp=%d, no_of_opps=%d, step_size=%d\n",
+ +                         __func__, i, sr_info->sen[i].curr_opp,
+ +                         sr_info->sen[i].no_of_opps,
+ +                         sr_info->uvoltage_step_size);
+ + 
+ +                 ret = sr_set_nvalues(sr_info, i);
+ +                 if (ret == -EINVAL) {
+ +                         dev_err(&sr_info->pdev->dev,
+ +                                 "%s: Zero NValue read from EFUSE\n", __func__);
+ +                         goto err_free_sr_info;
+ +                 }
+ + 
+ +                 INIT_DELAYED_WORK(&sr_info->sen[i].work_reenable,
+ +                         irq_sr_reenable);
+ + 
+ + 		sr_info->res_name[i] = kzalloc(CLK_NAME_LEN + 1, GFP_KERNEL);
+ + 
+ + 		/* resources */
+ + 		res[i] = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ + 					sr_info->sen[i].name);
+ + 		if (!res[i]) {
+ + 			dev_err(&pdev->dev, "%s: no mem resource\n", __func__);
+ + 			ret = -ENOENT;
+ + 			goto err_free_mem;
+ + 		}
+ + 
+ + 		irq = platform_get_irq_byname(pdev, sr_info->sen[i].name);
+ + 		if (irq < 0) {
+ + 			dev_err(&pdev->dev, "Can't get interrupt resource\n");
+ + 			ret = irq;
+ + 			goto err_free_mem;
+ + 		}
+ + 		sr_info->sen[i].irq = irq;
+ + 
+ + 		res[i] = request_mem_region(res[i]->start,
+ + 				resource_size(res[i]), pdev->name);
+ + 		if (!res[i]) {
+ + 			dev_err(&pdev->dev, "can't request mem region\n");
+ + 			ret = -EBUSY;
+ + 			goto err_free_mem;
+ + 		}
+ + 
+ + 		sr_info->sen[i].base = ioremap(res[i]->start,
+ + 				resource_size(res[i]));
+ + 		if (!sr_info->sen[i].base) {
+ + 			dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
+ + 			ret = -ENOMEM;
+ + 			goto err_release_mem;
+ + 		}
+ + 
+ + 		strcat(sr_info->res_name[i], sr_info->sen[i].name);
+ + 		strcat(sr_info->res_name[i], "_fck");
+ + 
+ + 		sr_info->sen[i].fck = clk_get(NULL, sr_info->res_name[i]);
+ + 		if (IS_ERR(sr_info->sen[i].fck)) {
+ + 			dev_err(&pdev->dev, "%s: Could not get sr fck\n",
+ + 						__func__);
+ + 			ret = PTR_ERR(sr_info->sen[i].fck);
+ + 			goto err_unmap;
+ + 		}
+ + 
+ + 		ret = request_irq(sr_info->sen[i].irq, sr_class2_irq,
+ + 			IRQF_DISABLED, sr_info->sen[i].name,
+ +                         (void *)&sr_info->sen[i]);
+ + 		if (ret) {
+ + 			dev_err(&pdev->dev, "%s: Could not install SR ISR\n",
+ + 						__func__);
+ + 			goto err_put_clock;
+ + 		}
+ + 
+ + 		sr_info->sen[i].senn_en = pdata->sr_sdata[i].senn_mod;
+ + 		sr_info->sen[i].senp_en = pdata->sr_sdata[i].senp_mod;
+ + 
+ +                 sr_info->sen[i].reg =
+ +                         regulator_get(NULL, sr_info->sen[i].reg_name);
+ +                	if (IS_ERR(sr_info->sen[i].reg)) {
+ +                         ret = -EINVAL;
+ + 	                goto err_free_irq;
+ +                 }
+ + 
+ +                	/* Read current regulator value and voltage */
+ + 	        sr_info->sen[i].init_volt_mv =
+ +                         regulator_get_voltage(sr_info->sen[i].reg);
+ + 
+ +                 dev_dbg(&pdev->dev, "%s: regulator %d, init_volt = %d\n",
+ +                         __func__, i, sr_info->sen[i].init_volt_mv);
+ + 	} /* for() */
+ + 
+ +         /* set_voltage() will be used as the bottom half IRQ handler */
+ + 	INIT_DELAYED_WORK(&sr_info->work, set_voltage);
+ + 
+ + #ifdef CONFIG_CPU_FREQ
+ + 	ret = am33xx_sr_cpufreq_register(sr_info);
+ + 	if (ret) {
+ + 		dev_err(&pdev->dev, "failed to register cpufreq\n");
+ + 		goto err_reg_put;
+ + 	}
+ + #endif
+ + 
+ + 	/* debugfs entries */
+ + 	ret = sr_debugfs_entries(sr_info);
+ + 	if (ret)
+ + 		dev_warn(&pdev->dev, "%s: Debugfs entries are not created\n",
+ + 						__func__);
+ + 
+ + 	platform_set_drvdata(pdev, sr_info);
+ + 
+ + 	dev_info(&pdev->dev, "%s: Driver initialized\n", __func__);
+ + 
+ +         /* disabled_by_user used to ensure SR doesn't come on via CPUFREQ
+ +            scaling if user has disabled SR via debugfs on enable_on_init */
+ + 	if (pdata->enable_on_init)
+ + 		sr_start_vddautocomp(sr_info);
+ +         else
+ +                 sr_info->disabled_by_user = 1;
+ + 
+ + 	return ret;
+ + 
+ + #ifdef CONFIG_CPU_FREQ
+ + 	am33xx_sr_cpufreq_deregister(sr_info);
+ + #endif
+ + 
+ + err_reg_put:
+ +         i--; /* back up i by one to walk back through the for loop */
+ +         regulator_put(sr_info->sen[i].reg);
+ + err_free_irq:
+ + 	free_irq(sr_info->sen[i].irq, (void *)sr_info);
+ + err_put_clock:
+ + 	clk_put(sr_info->sen[i].fck);
+ + err_unmap:
+ + 	iounmap(sr_info->sen[i].base);
+ + err_release_mem:
+ + 	release_mem_region(res[i]->start, resource_size(res[i]));
+ + err_free_mem:
+ +         kfree(sr_info->res_name[i]);
+ +         /* unwind back through the for loop */
+ +         if (i != 0) {
+ +                 goto err_reg_put;
+ +         }
+ + 
+ + err_free_sr_info:
+ + 	kfree(sr_info);
+ + 	return ret;
+ + }
+ + 
+ + static int __devexit am33xx_sr_remove(struct platform_device *pdev)
+ + {
+ + 	struct am33xx_sr *sr_info;
+ + 	struct resource *res[MAX_SENSORS];
+ + 	int irq;
+ + 	int i;
+ + 
+ + 	sr_info = dev_get_drvdata(&pdev->dev);
+ + 	if (!sr_info) {
+ + 		dev_err(&pdev->dev, "%s: sr_info missing\n", __func__);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	if (sr_info->autocomp_active)
+ + 		sr_stop_vddautocomp(sr_info);
+ + 
+ + #ifdef CONFIG_CPU_FREQ
+ + 	am33xx_sr_cpufreq_deregister(sr_info);
+ + #endif
+ + 
+ + 	for (i = 0; i < sr_info->no_of_sens; i++) {
+ +                 regulator_put(sr_info->sen[i].reg);
+ +                 irq = platform_get_irq_byname(pdev, sr_info->sen[i].name);
+ + 		free_irq(irq, (void *)sr_info);
+ + 		clk_put(sr_info->sen[i].fck);
+ + 		iounmap(sr_info->sen[i].base);
+ + 		res[i] = platform_get_resource_byname(pdev,
+ + 				IORESOURCE_MEM, sr_info->sen[i].name);
+ + 		release_mem_region(res[i]->start, resource_size(res[i]));
+ +                 kfree(sr_info->res_name[i]);
+ + 	}
+ + 
+ + 	kfree(sr_info);
+ + 
+ +         dev_info(&pdev->dev, "%s: SR has been removed\n", __func__);
+ + 	return 0;
+ + }
+ + 
+ + static struct platform_driver smartreflex_driver = {
+ + 	.driver		= {
+ + 		.name	= "smartreflex",
+ + 		.owner	= THIS_MODULE,
+ + 	},
+ + 	.remove		= am33xx_sr_remove,
+ + };
+ + 
+ + static int __init sr_init(void)
+ + {
+ + 	int ret;
+ + 
+ + 	ret = platform_driver_probe(&smartreflex_driver, am33xx_sr_probe);
+ + 	if (ret) {
+ + 		pr_err("%s: platform driver register failed\n", __func__);
+ + 		return ret;
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static void __exit sr_exit(void)
+ + {
+ + 	platform_driver_unregister(&smartreflex_driver);
+ + }
+ + late_initcall(sr_init);
+ + module_exit(sr_exit);
+ + 
+ + MODULE_DESCRIPTION("AM33XX Smartreflex Class2 Driver");
+ + MODULE_LICENSE("GPL");
+ + MODULE_ALIAS("platform:" DRIVER_NAME);
+ + MODULE_AUTHOR("Texas Instruments Inc");
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/board-ckb-3352.c linux-3.2.1/arch/arm/mach-ckb_3352/board-ckb-3352.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/board-ckb-3352.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/board-ckb-3352.c	2014-11-25 13:34:30.159300000 +0900
+ ***************
+ *** 0 ****
+ --- 1,2564 ----
+ + /*
+ +  * Code for AM335X EVM.
+ +  *
+ +  * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + #include <linux/kernel.h>
+ + #include <linux/init.h>
+ + #include <linux/i2c.h>
+ + #include <linux/module.h>
+ + #include <linux/i2c/at24.h>
+ + #include <linux/phy.h>
+ + #include <linux/gpio.h>
+ + #include <linux/gpio_keys.h>
+ + #include <linux/input.h>
+ + #include <linux/mtd/mtd.h>
+ + #include <linux/mtd/nand.h>
+ + #include <linux/mtd/partitions.h>
+ + #include <linux/mtd/physmap.h>
+ + #include <linux/platform_device.h>
+ + #include <linux/clk.h>
+ + #include <linux/err.h>
+ + #include <linux/export.h>
+ + #include <linux/ethtool.h>
+ + #include <linux/mfd/tps65217.h>
+ + #include <linux/reboot.h>
+ + #include <linux/pwm/pwm.h>
+ + #include <linux/rtc/rtc-omap.h>
+ + #include <linux/opp.h>
+ + #include <linux/i2c/tsc2007.h>
+ + #include <linux/irq.h>
+ + #include <video/omapdss.h>
+ + #include <linux/rtc/rtc-omap.h>
+ + #ifdef CONFIG_SUPPORT_GPMC_CS1_MEM
+ + #include <mtd/ckb_gpmc_cs1.h>
+ + #endif
+ + #include <mach/ckb_3352.h>
+ + 
+ + /* LCD controller is similar to DA8xx */
+ + #if defined(CONFIG_CKB_LCD_SUPPORT) || defined(CONFIG_CKB_DVI_SUPPORT)
+ + #include <video/da8xx-fb.h>
+ + #endif
+ + 
+ + #include <mach/hardware.h>
+ + 
+ + #include <asm/mach-types.h>
+ + #include <asm/mach/arch.h>
+ + #include <asm/mach/map.h>
+ + 
+ + #include <plat/omap_device.h>
+ + #include <plat/irqs.h>
+ + #include <plat/board.h>
+ + #include <plat/common.h>
+ + #include <plat/lcdc.h>
+ + #include <plat/usb.h>
+ + #include <plat/mmc.h>
+ + //#include <plat/emif.h>
+ + #include <plat/gpmc.h>
+ + 
+ + #include "cpuidle33xx.h"
+ + #include "mux.h"
+ + #include "devices.h"
+ + #include "hsmmc.h"
+ + #include <mach/devices.h>
+ + 
+ + #ifdef CONFIG_CKB_DVI_SUPPORT
+ + #include <video/ckb_dvi.h>
+ + #endif
+ + #ifdef CONFIG_CKB_EXTCN_SPIDEV_SPI1
+ + #include <linux/spi/spi.h>
+ + #endif
+ + #ifdef CONFIG_CKB_EXTCN_ADC
+ + #include <linux/platform_data/ti_adc.h>
+ + #include <linux/mfd/ti_tscadc.h>
+ + #endif
+ + 
+ + #ifdef CONFIG_SUPPORT_CMJ100
+ + #include <linux/cm-j100.h>
+ + #endif
+ + 
+ + #define DISP_PLL_CLK		300000000
+ + 
+ + /* Convert GPIO signal to GPIO pin number */
+ + #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
+ + 
+ + /* AM335X EVM Phy ID and Debug Registers */
+ + #define AM335X_EVM_PHY_ID		0x221611
+ + #define AM335X_EVM_PHY_MASK		0xfffffffe
+ + 
+ + #define CKB_LAN_RST_PIN			GPIO_TO_PIN(3, 1)
+ + #define CKB_LCD_PWR_PIN		GPIO_TO_PIN(3, 7)
+ + #define CKB_LCD_BL_PIN		GPIO_TO_PIN(3, 8)
+ + #define CKB_BL_TPS_PIN			GPIO_TO_PIN(3, 19)
+ + #define DA8xx_TS_PENIRQ_GPIO	GPIO_TO_PIN(3, 17)
+ + #define DA8xx_RTCIRQ_GPIO		GPIO_TO_PIN(3, 18)
+ + 
+ + /* various memory sizes */
+ + #define FLASH_SIZE_16M		SZ_16M	/* NOR flash (16 Meg aligned) */
+ + #define FLASH_SIZE_SDPV1	SZ_64M	/* NOR flash (64 Meg aligned) */
+ + #define FLASH_SIZE_SDPV2	SZ_128M	/* NOR flash (256 Meg aligned) */
+ + 
+ + /* LCD backlight platform Data */
+ + #define AM335X_BACKLIGHT_MAX_BRIGHTNESS        100
+ + #define AM335X_BACKLIGHT_DEFAULT_BRIGHTNESS    100
+ + #define AM335X_PWM_PERIOD_NANO_SECONDS        (5000 * 10)
+ + 
+ + #define AM335XEVM_WLAN_PMENA_GPIO	GPIO_TO_PIN(1, 30)
+ + #define AM335XEVM_WLAN_IRQ_GPIO		GPIO_TO_PIN(3, 17)
+ + 
+ + #ifdef CONFIG_SUPPORT_CMJ100
+ + #define CKB_WLAN_EN				GPIO_TO_PIN(0, 30)
+ + #define CKB_WLAN_IRQ			GPIO_TO_PIN(0, 31)
+ + #endif
+ + 
+ + #define CKB_LED1_PIN			GPIO_TO_PIN(0, 19)
+ + #define CKB_LED2_PIN			GPIO_TO_PIN(0, 20)
+ + 
+ + 
+ + #define SET_GPIO_TO_OUTPUT(p, val)	\
+ + 	if (gpio_request(p, "gpio_x") || gpio_direction_output(p, val)) { \
+ + 		pr_warning("Error initializing the GPIO %d\n", p); \
+ + 	}\
+ + 	gpio_free(p);
+ + 
+ + #define SET_GPIO_TO_INPUT(p)	\
+ + 	if (gpio_request(p, "gpio_x") || gpio_direction_input(p)) { \
+ + 		pr_warning("Error initializing the GPIO %d\n", p); \
+ + 	}\
+ + 	gpio_free(p);
+ + 
+ + unsigned long FB_DATA_ADDRESS = 0;
+ + unsigned long FB_DATA_VADDRESS = 0;
+ + unsigned long FB_MAP_SIZE = 0;
+ + 
+ + /* module pin mux structure */
+ + struct pinmux_config {
+ + 	const char *string_name; /* signal name format */
+ + 	int val; /* Options for the mux register value */
+ + };
+ + 
+ + #if defined(CONFIG_CKB_TSC2007_TOUCH_PANEL) || defined(CONFIG_CKB_RTC)
+ + /* I2C device index */
+ + enum {
+ + #ifdef CONFIG_CKB_TSC2007_TOUCH_PANEL
+ + 	CKB_TSC_DEV_INDEX,
+ + #endif
+ + #ifdef CONFIG_CKB_RTC
+ + 	CKB_RTC_DEV_INDEX,
+ + #endif
+ + };
+ + #endif
+ + 
+ + 
+ + typedef enum {
+ + 	CKB_EMAC_MAC_OFFSET,
+ + //	CKB_SDIO_MAC_OFFSET,
+ + 	TOTAL_EMAC_NUMS
+ + }CKB_MAC_OFFSET;
+ + 
+ + /*
+ + * @pin_mux - single module pin-mux structure which defines pin-mux
+ + *			details for all its pins.
+ + */
+ + static void setup_pin_mux(struct pinmux_config *pin_mux)
+ + {
+ + 	int i;
+ + 
+ + 	for (i = 0; pin_mux->string_name != NULL; pin_mux++)
+ + 		omap_mux_init_signal(pin_mux->string_name, pin_mux->val);
+ + 
+ + }
+ + 
+ + static struct mtd_partition ckb_norflash_partition[] = {
+ + 	{
+ + 		.name           = "loader.bin",
+ + 		.offset         = 0,
+ + 		.size           = SZ_128K,
+ + 		.mask_flags     = MTD_WRITEABLE,
+ + 	},
+ + 	{
+ + 		.name           = "U-Boot",
+ + 		.offset         = MTDPART_OFS_APPEND,
+ + 		.size           = SZ_256K+SZ_128K,
+ + 		.mask_flags     = 0,
+ + 	},
+ + 	{
+ + 		.name           = "LCD Logo image",
+ + 		.offset         = MTDPART_OFS_APPEND,
+ + 		.size           = SZ_256K+SZ_128K,
+ + 		.mask_flags     = 0,
+ + 	},
+ + 	{
+ + 		.name           = "U-Boot environment",
+ + 		.offset         = MTDPART_OFS_APPEND,
+ + 		.size           = SZ_128K,
+ + 		.mask_flags     = 0,
+ + 	},
+ + 	{
+ + 		.name           = "Kernel",
+ + 		.offset         = MTDPART_OFS_APPEND,
+ + 		.size           = SZ_1M*14,
+ + 		.mask_flags     = 0,
+ + 	},
+ + 	{
+ + 		.name           = "Settings",
+ + 		.offset         = MTDPART_OFS_APPEND,
+ + 		.size           = MTDPART_SIZ_FULL,
+ + 		.mask_flags     = 0,
+ + 	},
+ + };
+ + 
+ + 
+ + static struct physmap_flash_data ckb_norflash_data = {
+ + 	.width		= 2,
+ + 	.parts		= ckb_norflash_partition,
+ + 	.nr_parts	= ARRAY_SIZE(ckb_norflash_partition),
+ + };
+ + 
+ + 
+ + static struct pinmux_config ckb_nor_pins[] = {
+ + 	{"gpmc_ad0.gpmc_ad0",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
+ + 	{"gpmc_ad1.gpmc_ad1",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
+ + 	{"gpmc_ad2.gpmc_ad2",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
+ + 	{"gpmc_ad3.gpmc_ad3",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
+ + 	{"gpmc_ad4.gpmc_ad4",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
+ + 	{"gpmc_ad5.gpmc_ad5",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
+ + 	{"gpmc_ad6.gpmc_ad6",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
+ + 	{"gpmc_ad7.gpmc_ad7",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
+ + 	{"gpmc_ad8.gpmc_ad8",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
+ + 	{"gpmc_ad9.gpmc_ad9",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
+ + 	{"gpmc_ad10.gpmc_ad10",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
+ + 	{"gpmc_ad11.gpmc_ad11",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
+ + 	{"gpmc_ad12.gpmc_ad12",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
+ + 	{"gpmc_ad13.gpmc_ad13",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
+ + 	{"gpmc_ad14.gpmc_ad14",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
+ + 	{"gpmc_ad15.gpmc_ad15",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
+ + 	/* for GPIO port */
+ + 	{"gpmc_a4.gpio1_20", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
+ + 	{"gpmc_a5.gpio1_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
+ + 	{"gpmc_a6.gpio1_22", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
+ + 	{"gpmc_a7.gpio1_23", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
+ + 	{"gpmc_a8.gpio1_24", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
+ + 	{"gpmc_a9.gpio1_25", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
+ + 	{"gpmc_a10.gpio1_26", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
+ + 	{NULL, 0},
+ + };
+ + 
+ + 
+ + 
+ + #include "common.h"
+ + 
+ + 
+ + static struct omap2_hsmmc_info mmc_sdcard __initdata = {
+ + 	.mmc            = 1,
+ + 	.caps           = MMC_CAP_4_BIT_DATA,
+ + 	.gpio_cd        = GPIO_TO_PIN(0, 6),
+ + 	.gpio_wp        = -EINVAL,
+ + 	.ocr_mask       = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3V3 */
+ + };
+ + 
+ + #ifdef CONFIG_SUPPORT_CMJ100
+ + 
+ + static struct omap2_hsmmc_info mmc_cmj100 __initdata = {
+ + 	.mmc            = 3,
+ + 	.name			= "cm-j100",
+ + 	.caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE,
+ + 	.nonremovable	= true,
+ + 	.gpio_cd        = -EINVAL,
+ + 	.gpio_wp        = -EINVAL,
+ + 	.ocr_mask       = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3V3 */
+ + };
+ + 
+ + static int cmj100_sdio_set_power(struct device *dev, int slot, int power_on, int vdd)
+ + {
+ + 	return cmj100_set_power(power_on);
+ + }
+ + 
+ + static struct pinmux_config cmj100_wl_pins[] = {
+ + 	{"gpmc_a1.mmc2_dat0", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
+ + 	{"gpmc_a2.mmc2_dat1", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
+ + 	{"gpmc_a3.mmc2_dat2", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
+ + 	{"gpmc_ben1.mmc2_dat3", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
+ + 	{"gpmc_csn3.mmc2_cmd", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
+ + 	{"gpmc_clk.mmc2_clk", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
+ + 	{"gpmc_wait0.gpio0_30", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
+ + 	{"gpmc_wpn.gpio0_31", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+ + 	{NULL, 0},
+ + };
+ + 
+ + static struct cmj100_platform_data wlan_data __initdata = {
+ + 	.wlan_en_gpio = CKB_WLAN_EN,
+ + 	.wlan_irq_gpio = CKB_WLAN_IRQ,
+ + 	.board_ref_clock = CMJ100_REFCLOCK_38_XTAL,
+ + 	.irq = -1,
+ + 	.trigger_rising = 1, /* rising edge */
+ + };
+ + 
+ + 
+ + static void ckb_cmj100_init(void)
+ + {
+ + 	struct device *dev;
+ + 	struct omap_mmc_platform_data *pdata;
+ + 
+ + 	setup_pin_mux(cmj100_wl_pins);
+ + 	
+ + 	if (gpio_request(CKB_WLAN_EN, "wl_en") ||
+ + 			gpio_direction_output(CKB_WLAN_EN, 0))
+ + 		pr_warning("Error initializing the wl_en GPIO %d\n",
+ + 					CKB_WLAN_EN);
+ + 		
+ + 	if (gpio_request(CKB_WLAN_IRQ, "wl_irq") ||
+ + 			gpio_direction_input(CKB_WLAN_IRQ))
+ + 		pr_warning("Error initializing the wl_irq GPIO %d\n",
+ + 					CKB_WLAN_IRQ);
+ + 	
+ + 	omap_init_hsmmc(&mmc_cmj100);
+ + 		
+ + 	if (cmj100_set_platform_data(&wlan_data))
+ + 		pr_err("Error setting cmj100 data\n");
+ + 
+ + 	dev = mmc_cmj100.dev;
+ + 	if (!dev) {
+ + 		pr_err("cm-j100 initialization failed\n");
+ + 		goto out;
+ + 	}
+ + 
+ + 	pdata = dev->platform_data;
+ + 	if (!pdata) {
+ + 		pr_err("Platform data of cm-j100 not set\n");
+ + 		goto out;
+ + 	}
+ + 
+ + 	pdata->slots[0].set_power = cmj100_sdio_set_power;
+ + 
+ + out:
+ + 	return;
+ + }
+ + #endif
+ + 
+ + 
+ + #if defined(CONFIG_CKB_LCD_SUPPORT) || defined(CONFIG_CKB_DVI_SUPPORT)
+ + /* Module pin mux for LCDC */
+ + static struct pinmux_config lcdc_pin_mux[] = {
+ + 	{"lcd_data0.lcd_data0",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ + 						       | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW},
+ + 	{"lcd_data1.lcd_data1",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ + 						       | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW},
+ + 	{"lcd_data2.lcd_data2",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ + 						       | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW},
+ + 	{"lcd_data3.lcd_data3",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ + 						       | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW},
+ + 	{"lcd_data4.lcd_data4",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ + 						       | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW},
+ + 	{"lcd_data5.lcd_data5",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ + 						       | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW},
+ + 	{"lcd_data6.lcd_data6",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ + 						       | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW},
+ + 	{"lcd_data7.lcd_data7",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ + 						       | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW},
+ + 	{"lcd_data8.lcd_data8",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ + 						       | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW},
+ + 	{"lcd_data9.lcd_data9",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ + 						       | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW},
+ + 	{"lcd_data10.lcd_data10",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ + 						       | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW},
+ + 	{"lcd_data11.lcd_data11",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ + 						       | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW},
+ + 	{"lcd_data12.lcd_data12",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ + 						       | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW},
+ + 	{"lcd_data13.lcd_data13",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ + 						       | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW},
+ + 	{"lcd_data14.lcd_data14",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ + 						       | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW},
+ + 	{"lcd_data15.lcd_data15",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ + 						       | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW},
+ + 	{"lcd_vsync.lcd_vsync",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_SLEWCTRL_SLOW},
+ + 	{"lcd_hsync.lcd_hsync",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_SLEWCTRL_SLOW},
+ + 	{"lcd_pclk.lcd_pclk",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_SLEWCTRL_SLOW},
+ + 	{"lcd_ac_bias_en.lcd_ac_bias_en", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_SLEWCTRL_SLOW},
+ + 	{NULL, 0},
+ + };
+ + #endif
+ + 
+ + #if defined(CONFIG_CKB_LCD_SUPPORT)
+ + static struct pinmux_config lcdpwr_pin_mux[] = {
+ + 	{"emu0.gpio3_7", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT_PULLUP},		/* LCDC Pwr pin */
+ + 	{"emu1.gpio3_8", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT_PULLUP},		/* Backlight pin */
+ + 	{"mcasp0_fsr.gpio3_19", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT_PULLUP},	/* TPS pin */
+ + 	{NULL, 0},
+ + };
+ + #endif
+ + 
+ + /* Module pin mux for rgmii1 */
+ + static struct pinmux_config rgmii1_pin_mux[] = {
+ + 	{"mii1_txen.rgmii1_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
+ + 	{"mii1_rxdv.rgmii1_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
+ + 	{"mii1_txd3.rgmii1_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
+ + 	{"mii1_txd2.rgmii1_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
+ + 	{"mii1_txd1.rgmii1_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
+ + 	{"mii1_txd0.rgmii1_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
+ + 	{"mii1_txclk.rgmii1_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
+ + 	{"mii1_rxclk.rgmii1_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
+ + 	{"mii1_rxd3.rgmii1_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
+ + 	{"mii1_rxd2.rgmii1_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
+ + 	{"mii1_rxd1.rgmii1_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
+ + 	{"mii1_rxd0.rgmii1_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
+ + 	{"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ + 	{"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
+ + 	//{"mii1_col.gpio3_0", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLDOWN},	/* IRQ */
+ + 	{"mii1_crs.gpio3_1", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT_PULLUP},	/* reset pin */
+ + 	{NULL, 0},
+ + };
+ + 
+ + 
+ + //AM33XX_SLEWCTRL_SLOW
+ + static struct pinmux_config i2c0_pin_mux[] = {
+ + 	{"i2c0_sda.i2c0_sda",    OMAP_MUX_MODE0 | AM33XX_INPUT_EN | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW },
+ + 	{"i2c0_scl.i2c0_scl",   OMAP_MUX_MODE0 | AM33XX_INPUT_EN | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW },
+ + 	{NULL, 0},
+ + };
+ + 
+ + /* Module pin mux for mmc0 */
+ + static struct pinmux_config mmc0_common_pin_mux[] = {
+ + 	{"mmc0_dat3.mmc0_dat3",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ + 	{"mmc0_dat2.mmc0_dat2",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ + 	{"mmc0_dat1.mmc0_dat1",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ + 	{"mmc0_dat0.mmc0_dat0",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ + 	{"mmc0_clk.mmc0_clk",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ + 	{"mmc0_cmd.mmc0_cmd",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ + 	{NULL, 0},
+ + };
+ + 
+ + static struct pinmux_config mmc0_cd_only_pin_mux[] = {
+ + 	{"spi0_cs1.gpio0_6",  OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
+ + 	{NULL, 0},
+ + };
+ + 
+ + /* pinmux for usb0 drvvbus */
+ + static struct pinmux_config usb0_pin_mux[] = {
+ + 	{"usb0_drvvbus.usb0_drvvbus",    OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
+ + 	{"mii1_rxerr.gpio3_2", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLDOWN},	/* USB fault */
+ + 	{NULL, 0},
+ + };
+ + 
+ + /* pinmux for usb1 drvvbus */
+ + static struct pinmux_config usb1_pin_mux[] = {
+ + 	{"usb1_drvvbus.usb1_drvvbus",    OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
+ + 	{NULL, 0},
+ + };
+ + 
+ + 
+ + /* TPS65217 voltage regulator support */
+ + 
+ + /* 1.8V */
+ + static struct regulator_consumer_supply tps65217_dcdc1_consumers[] = {
+ + 	{
+ + 		.supply = "vdds_osc",
+ + 	},
+ + 	{
+ + 		.supply = "vdds_pll_ddr",
+ + 	},
+ + 	{
+ + 		.supply = "vdds_pll_mpu",
+ + 	},
+ + 	{
+ + 		.supply = "vdds_pll_core_lcd",
+ + 	},
+ + 	{
+ + 		.supply = "vdds_sram_mpu_bb",
+ + 	},
+ + 	{
+ + 		.supply = "vdds_sram_core_bg",
+ + 	},
+ + 	{
+ + 		.supply = "vdda_usb0_1p8v",
+ + 	},
+ + 	{
+ + 		.supply = "vdds_ddr",
+ + 	},
+ + 	{
+ + 		.supply = "vdds",
+ + 	},
+ + 	{
+ + 		.supply = "vdds_hvx_1p8v",
+ + 	},
+ + 	{
+ + 		.supply = "vdda_adc",
+ + 	},
+ + 	{
+ + 		.supply = "ddr2",
+ + 	},
+ + };
+ + 
+ + /* 1.1V */
+ + static struct regulator_consumer_supply tps65217_dcdc2_consumers[] = {
+ + 	{
+ + 		.supply = "vdd_mpu",
+ + 	},
+ + };
+ + 
+ + /* 1.1V */
+ + static struct regulator_consumer_supply tps65217_dcdc3_consumers[] = {
+ + 	{
+ + 		.supply = "vdd_core",
+ + 	},
+ + };
+ + 
+ + /* 1.8V LDO */
+ + static struct regulator_consumer_supply tps65217_ldo1_consumers[] = {
+ + 	{
+ + 		.supply = "vdds_rtc",
+ + 	},
+ + };
+ + 
+ + /* 3.3V LDO */
+ + static struct regulator_consumer_supply tps65217_ldo2_consumers[] = {
+ + 	{
+ + 		.supply = "vdds_any_pn",
+ + 	},
+ + };
+ + 
+ + /* 3.3V LDO */
+ + static struct regulator_consumer_supply tps65217_ldo3_consumers[] = {
+ + 	{
+ + 		.supply = "vdds_hvx_ldo3_3p3v",
+ + 	},
+ + 	{
+ + 		.supply = "vdda_usb0_3p3v",
+ + 	},
+ + };
+ + 
+ + /* 3.3V LDO */
+ + static struct regulator_consumer_supply tps65217_ldo4_consumers[] = {
+ + 	{
+ + 		.supply = "vdds_hvx_ldo4_3p3v",
+ + 	},
+ + };
+ + 
+ + static struct tps65217_rdelay dcdc2_ramp_delay = {
+ + 	.ramp_delay = 70000,
+ + };
+ + 
+ + static struct regulator_init_data tps65217_regulator_data[] = {
+ + 	/* dcdc1 */
+ + 	{
+ + 		.constraints = {
+ + 			.min_uV = 900000,
+ + 			.max_uV = 1800000,
+ + 			.boot_on = 1,
+ + 			.always_on = 1,
+ + 		},
+ + 		.num_consumer_supplies = ARRAY_SIZE(tps65217_dcdc1_consumers),
+ + 		.consumer_supplies = tps65217_dcdc1_consumers,
+ + 	},
+ + 
+ + 	/* dcdc2 */
+ + 	{
+ + 		.constraints = {
+ + 			.min_uV = 900000,
+ + 			.max_uV = 3300000,
+ + 			.valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
+ + 				REGULATOR_CHANGE_STATUS),
+ + 			.boot_on = 1,
+ + 			.always_on = 1,
+ + 		},
+ + 		.num_consumer_supplies = ARRAY_SIZE(tps65217_dcdc2_consumers),
+ + 		.consumer_supplies = tps65217_dcdc2_consumers,
+ + 		.driver_data = &dcdc2_ramp_delay,
+ + 		.ignore_check_consumers = 1,
+ + 	},
+ + 
+ + 	/* dcdc3 */
+ + 	{
+ + 		.constraints = {
+ + 			.min_uV = 900000,
+ + 			.max_uV = 1500000,
+ + 			.valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
+ + 				REGULATOR_CHANGE_STATUS),
+ + 			.boot_on = 1,
+ + 			.always_on = 1,
+ + 		},
+ + 		.num_consumer_supplies = ARRAY_SIZE(tps65217_dcdc3_consumers),
+ + 		.consumer_supplies = tps65217_dcdc3_consumers,
+ + 		.ignore_check_consumers = 1,
+ + 	},
+ + 
+ + 	/* ldo1 */
+ + 	{
+ + 		.constraints = {
+ + 			.min_uV = 1000000,
+ + 			.max_uV = 3300000,
+ + 			.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ + 			.boot_on = 1,
+ + 			.always_on = 1,
+ + 		},
+ + 		.num_consumer_supplies = ARRAY_SIZE(tps65217_ldo1_consumers),
+ + 		.consumer_supplies = tps65217_ldo1_consumers,
+ + 	},
+ + 
+ + 	/* ldo2 */
+ + 	{
+ + 		.constraints = {
+ + 			.min_uV = 900000,
+ + 			.max_uV = 3300000,
+ + 			.valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
+ + 				REGULATOR_CHANGE_STATUS),
+ + 			.boot_on = 1,
+ + 			.always_on = 1,
+ + 		},
+ + 		.num_consumer_supplies = ARRAY_SIZE(tps65217_ldo2_consumers),
+ + 		.consumer_supplies = tps65217_ldo2_consumers,
+ + 	},
+ + 
+ + 	/* ldo3 */
+ + 	{
+ + 		.constraints = {
+ + 			.min_uV = 1800000,
+ + 			.max_uV = 3300000,
+ + 			.valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
+ + 				REGULATOR_CHANGE_STATUS),
+ + 			.boot_on = 1,
+ + 			.always_on = 1,
+ + 		},
+ + 		.num_consumer_supplies = ARRAY_SIZE(tps65217_ldo3_consumers),
+ + 		.consumer_supplies = tps65217_ldo3_consumers,
+ + 	},
+ + 
+ + 	/* ldo4 */
+ + 	{
+ + 		.constraints = {
+ + 			.min_uV = 1800000,
+ + 			.max_uV = 3300000,
+ + 			.valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
+ + 				REGULATOR_CHANGE_STATUS),
+ + 			.boot_on = 1,
+ + 			.always_on = 1,
+ + 		},
+ + 		.num_consumer_supplies = ARRAY_SIZE(tps65217_ldo4_consumers),
+ + 		.consumer_supplies = tps65217_ldo4_consumers,
+ + 	},
+ + };
+ + 
+ + static struct tps65217_board ckb_tps65217_info = {
+ + 	.tps65217_init_data = &tps65217_regulator_data[0],
+ + 	.status_off = true,
+ + };
+ + 
+ + int conf_disp_pll(int rate)
+ + {
+ + 	struct clk *disp_pll;
+ + 	int ret = -EINVAL;
+ + 
+ + 	disp_pll = clk_get(NULL, "dpll_disp_ck");
+ + 	if (IS_ERR(disp_pll)) {
+ + 		pr_err("Cannot clk_get disp_pll\n");
+ + 		goto out;
+ + 	}
+ + 	ret = clk_set_rate(disp_pll, rate);
+ + 	clk_put(disp_pll);
+ + out:
+ + 	return ret;
+ + }
+ + 
+ + #ifdef CONFIG_SUPPORT_CKB_LED
+ + /* pinmux for led device */
+ + static struct pinmux_config ckb_led_pinmux[] = {
+ + 	{"xdma_event_intr0.gpio0_19", OMAP_MUX_MODE7},
+ + 	{"xdma_event_intr1.gpio0_20", OMAP_MUX_MODE7},
+ + 	{NULL, 0},
+ + };
+ + 
+ + static struct gpio_led ckb_leds[] = {
+ + 	{
+ + 		.name			= "led1",
+ + 		//.default_trigger	= "heartbeat",
+ + 		.default_trigger	= "default-on",
+ + 		.gpio			= CKB_LED1_PIN,
+ + 		//.active_low		= 1,
+ + 	},
+ + 	{
+ + 		.name			= "led2",
+ + 		.default_trigger	= "default-on",
+ + 		.gpio			= CKB_LED2_PIN,
+ + 	},
+ + };
+ + 
+ + static struct gpio_led_platform_data ckb_leds_data = {
+ + 	.num_leds	= ARRAY_SIZE(ckb_leds),
+ + 	.leds		= ckb_leds,
+ + };
+ + 
+ + static struct platform_device ckb_gpio_leds = {
+ + 	.name	= "leds-gpio",
+ + 	.id	= -1,
+ + 	.dev	= {
+ + 		.platform_data = &ckb_leds_data,
+ + 	},
+ + };
+ + 
+ + static void gpio_led_init(void)
+ + {
+ + 	int err;
+ + 	
+ + 	setup_pin_mux(ckb_led_pinmux);
+ + 	err = platform_device_register(&ckb_gpio_leds);
+ + 	if (err)
+ + 		pr_err("failed to register gpio led device\n");
+ + }
+ + #endif
+ + 
+ + #ifdef CONFIG_CKB_TSC2007_TOUCH_PANEL
+ + static struct pinmux_config ckb_touchpanel_pin_mux[] = {
+ + 	{"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},		/* TP Pen IRQ */
+ + 	{NULL, 0},
+ + };
+ + 
+ + int tsc2007_get_pendown_state(void)
+ + {
+ + 	return !gpio_get_value(DA8xx_TS_PENIRQ_GPIO);
+ + }
+ + 
+ + static struct tsc2007_platform_data tsc2007_info = {
+ + 	.model			= 2007,
+ + 	.x_plate_ohms		= 180,
+ + 	.get_pendown_state = tsc2007_get_pendown_state,
+ + };
+ + #endif
+ + 
+ + #ifdef CONFIG_CKB_RTC
+ + static struct pinmux_config ckb_rtc_pin_mux[] = {
+ + 	{"mcasp0_aclkr.gpio3_18", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},		/* RTC IRQ */
+ + 	{NULL, 0},
+ + };
+ + #endif
+ + 
+ + /* global variables to store EEPROM function call params */
+ + struct memory_accessor *g_at24i2c_mem_acc = NULL;
+ + void *g_g_at24i2c_context;
+ + 
+ + /* retrieves the mac address from EEPROM
+ + 	offset : Index of the MAC address structure on EEPROM
+ + 	mac_addr : MAC address (6 bytes)
+ + */
+ + u_char get_mac_address(CKB_MAC_OFFSET offset, char *mac_addr)
+ + {
+ + 	size_t len;
+ + 	ckb_3352_eeprom_mac_address mac;
+ + 	int addr;
+ + 	if(offset>=TOTAL_EMAC_NUMS)
+ + 	{
+ + 		printk("Wrong offset specified for MAC address\n");
+ + 		return 1;
+ + 	}
+ + 	if(!g_at24i2c_mem_acc)
+ + 	{
+ + 		printk("No EEPROM device found. Unable to read MAC address\n");
+ + 		return 2;
+ + 	}
+ + 	len = sizeof(ckb_3352_eeprom_mac_address);
+ + 	addr = ((int)g_g_at24i2c_context)+(offset*len);
+ + 	
+ + 	/* read data */
+ + 	if((!g_at24i2c_mem_acc->read) || g_at24i2c_mem_acc->read(g_at24i2c_mem_acc, (char*)&mac, addr, len) != len)
+ + 	{
+ + 		printk("Unable to read MAC address from EEPROM\n");
+ + 		return 3;
+ + 	}
+ + 	/* check the header */
+ + 	if(mac.id!=CKB_3352_MAC_HEADER)
+ + 	{
+ + 		printk("MAC address header mismatch on EEPROM\n");
+ + 		return 4;
+ + 	}
+ + 	pr_info("Read MAC addr from EEPROM: %pM\n", mac.mac);
+ + 	/* copy the mac address */
+ + 	memcpy(mac_addr, mac.mac, ETH_ALEN);
+ + 	return 0;
+ + }
+ + 
+ + /* writes the MAC address to NAND flash
+ + 	offset : Index of the MAC address structure on EEPROM
+ + 	mac_addr : MAC address (6 bytes)
+ + */
+ + u_char save_mac_address(CKB_MAC_OFFSET offset, char *mac_addr)
+ + {
+ + 	ckb_3352_eeprom_mac_address mac;
+ + 	size_t len;
+ + 	int addr;
+ + 
+ + 	if(offset>=TOTAL_EMAC_NUMS)
+ + 	{
+ + 		printk("Wrong offset specified for MAC address\n");
+ + 		return 1;
+ + 	}
+ + 	if(!g_at24i2c_mem_acc)
+ + 	{
+ + 		printk("No EEPROM device found. Unable to read MAC address\n");
+ + 		return 2;
+ + 	}
+ + 	len = sizeof(ckb_3352_eeprom_mac_address);
+ + 	addr = ((int)g_g_at24i2c_context)+(offset*len);
+ + 	/* update new mac address in the buffer */
+ + 	mac.id = CKB_3352_MAC_HEADER;
+ + 	memcpy(mac.mac, mac_addr, ETH_ALEN);
+ + 	pr_info("Writing MAC addr to EEPROM: %pM\n", mac_addr);
+ + 	/* write data */
+ + 	if((!g_at24i2c_mem_acc->write) || g_at24i2c_mem_acc->write(g_at24i2c_mem_acc, (char*)&mac, addr, len) != len)
+ + 	{
+ + 		pr_err("Unable to Write MAC address to EEPROM\n");
+ + 		return 3;
+ + 	}
+ + 	/* Verify */
+ + 	if((!g_at24i2c_mem_acc->read) || g_at24i2c_mem_acc->read(g_at24i2c_mem_acc, (char*)&mac, addr, len) != len)
+ + 	{
+ + 		pr_err("Unable to read MAC address from EEPROM for verifying\n");
+ + 		return 3;
+ + 	}
+ + 	if(mac.id!=CKB_3352_MAC_HEADER || memcmp(mac.mac, mac_addr, ETH_ALEN))
+ + 	{
+ + 		pr_err("MAC addr: Data mismatch during verification\n");
+ + 		return 3;
+ + 	}
+ + 	pr_info("MAC addr written successfully\n");
+ + 	return 0;
+ + }
+ + 
+ + void save_mac_addr(char *mac_addr)
+ + {
+ + 	save_mac_address(CKB_EMAC_MAC_OFFSET, mac_addr);
+ + }
+ + 
+ + /* dummy function to store EEPROM function call params */
+ + void board_at24i2c_setup(struct memory_accessor *mem_acc, void *context)
+ + {
+ + 	/* store the pointer for later use */
+ + 	g_at24i2c_mem_acc = mem_acc;
+ + 	g_g_at24i2c_context = context;
+ + }
+ + 
+ + void  board_at24i2c_unload(void)
+ + {
+ + 	g_at24i2c_mem_acc = NULL;
+ + }
+ + 
+ + static struct at24_platform_data m24c01_eeprom_info = {
+ + 	.byte_len	= SZ_1K / 8,
+ + 	.page_size	= 16,
+ + 	.flags		= 0,
+ + 	.setup		= board_at24i2c_setup,
+ + 	.unload		= board_at24i2c_unload,
+ + };
+ + 
+ + static struct i2c_board_info __initdata am335x_i2c0_boardinfo[] = {
+ + #ifdef CONFIG_CKB_TSC2007_TOUCH_PANEL
+ + 	[CKB_TSC_DEV_INDEX]={
+ + 		I2C_BOARD_INFO("tsc2007", (0x90>>1)),
+ + 		.type		= "tsc2007",
+ + 		.platform_data	= &tsc2007_info,
+ + 		.irq = 0,
+ + 	},
+ + #endif
+ + #ifdef CONFIG_CKB_RTC
+ + 	[CKB_RTC_DEV_INDEX]={
+ + 		I2C_BOARD_INFO("s35390a", 0x30),
+ + 		.irq	= 0,
+ + 	},
+ + #endif
+ + 	{
+ + 		I2C_BOARD_INFO("tps65217", TPS65217_I2C_ID),
+ + 		.platform_data  = &ckb_tps65217_info,
+ + 	},
+ + 	{
+ + 		I2C_BOARD_INFO("24c01", 0x51),
+ + 		.platform_data = &m24c01_eeprom_info,
+ + 	},
+ + #ifdef CONFIG_CKB_3352_AUDIO
+ + 	{
+ + 		I2C_BOARD_INFO("tlv320aic3x", 0x1b),
+ + 	},
+ + #endif
+ + #ifdef CONFIG_CKB_DVI_SUPPORT
+ + 	{
+ + 		I2C_BOARD_INFO("tfp410", 0x38),
+ + 	},
+ + #endif
+ + 
+ + };
+ + 
+ + #ifdef CONFIG_CKB_3352_AUDIO
+ + 
+ + static u8 am335x_iis_serializer_direction1[] = {
+ + 	INACTIVE_MODE,	INACTIVE_MODE,	TX_MODE,	RX_MODE,
+ + 	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,
+ + 	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,
+ + 	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,
+ + };
+ + 
+ + static struct snd_platform_data am335x_evm_snd_data1 = {
+ + 	.tx_dma_offset	= 0x46400000,	/* McASP1 */
+ + 	.rx_dma_offset	= 0x46400000,
+ + 	.op_mode	= DAVINCI_MCASP_IIS_MODE,
+ + 	.num_serializer	= ARRAY_SIZE(am335x_iis_serializer_direction1),
+ + 	.tdm_slots	= 2,
+ + 	.serial_dir	= am335x_iis_serializer_direction1,
+ + 	.asp_chan_q	= EVENTQ_2,
+ + 	.version	= MCASP_VERSION_3,
+ + 	.txnumevt	= 1,
+ + 	.rxnumevt	= 1,
+ + };
+ + #endif
+ + 
+ + static void __init ckb_i2c_init(void)
+ + {
+ + 	setup_pin_mux(i2c0_pin_mux);
+ + 
+ + #ifdef CONFIG_CKB_TSC2007_TOUCH_PANEL
+ + 	setup_pin_mux(ckb_touchpanel_pin_mux);
+ + 
+ + 	if (gpio_request(DA8xx_TS_PENIRQ_GPIO, "TS Pen IRQ"))
+ + 		pr_err("Error initializing TS Pen IRQ gpio\n");
+ + 	gpio_direction_input(DA8xx_TS_PENIRQ_GPIO);
+ + 
+ + 	gpio_free(DA8xx_TS_PENIRQ_GPIO);
+ + 
+ + 	am335x_i2c0_boardinfo[CKB_TSC_DEV_INDEX].irq = gpio_to_irq(DA8xx_TS_PENIRQ_GPIO);
+ + 	irq_set_irq_type(am335x_i2c0_boardinfo[CKB_TSC_DEV_INDEX].irq, IRQF_TRIGGER_FALLING);
+ + #endif
+ + 
+ + #ifdef CONFIG_CKB_RTC
+ + 
+ + 	setup_pin_mux(ckb_rtc_pin_mux);
+ + 	if (gpio_request(DA8xx_RTCIRQ_GPIO, "RTC IRQ"))
+ + 		pr_err("Error initializing RTC IRQ gpio\n");
+ + 	gpio_direction_input(DA8xx_RTCIRQ_GPIO);
+ + 
+ + 	gpio_free(DA8xx_RTCIRQ_GPIO);
+ + 
+ + 	am335x_i2c0_boardinfo[CKB_RTC_DEV_INDEX].irq = gpio_to_irq(DA8xx_RTCIRQ_GPIO);
+ + 	irq_set_irq_type(am335x_i2c0_boardinfo[CKB_RTC_DEV_INDEX].irq, IRQF_TRIGGER_FALLING);
+ + #endif
+ + 
+ + 	omap_register_i2c_bus(1, 48, am335x_i2c0_boardinfo,
+ + 				ARRAY_SIZE(am335x_i2c0_boardinfo));
+ + }
+ + 
+ + 
+ + static struct omap_musb_board_data musb_board_data = {
+ + 	.interface_type	= MUSB_INTERFACE_ULPI,
+ + 	/*
+ + 	 * mode[0:3] = USB0PORT's mode
+ + 	 * mode[4:7] = USB1PORT's mode
+ + 	 * CKB 3352 has USB0 and USB1 in host mode.
+ + 	 */
+ + 	.mode           = (MUSB_HOST << 4) | MUSB_HOST,
+ + 	.power		= 500,
+ + 	.instances	= 1,
+ + };
+ + 
+ + static void usb0_init(void)
+ + {
+ + 	setup_pin_mux(usb0_pin_mux);
+ + 	return;
+ + }
+ + 
+ + static void usb1_init(void)
+ + {
+ + 	setup_pin_mux(usb1_pin_mux);
+ + 	return;
+ + }
+ + 
+ + #ifdef CONFIG_SUPPORT_GPMC_CS1_MEM
+ + static struct pinmux_config cs1_mux_enable[] = {
+ + 	{"gpmc_csn1.gpmc_csn1",    OMAP_MUX_MODE0 | AM33XX_PULL_UP},
+ + 	{NULL, 0},
+ + };
+ + 
+ + void gpmc_cs1_mux_enable(void)
+ + {
+ + 	/* CS1 */
+ + 	printk("Setting GPMC CS1 mux\n");
+ + 	setup_pin_mux(cs1_mux_enable);
+ + 	/* WEn and OEn are configured while configuring NOR flash */
+ + }
+ + 
+ + 
+ + static struct resource ckb_emif_CS1_resource[] = {
+ + 	{
+ + 		.start	= CKB_GPMC_CS1_BASE,
+ + 		.end	= CKB_GPMC_CS1_BASE + SZ_128,		/* 128 bytes are accessible */
+ + 		.flags	= IORESOURCE_MEM,
+ + 	},
+ + };
+ + 
+ + struct platform_device ckb_emif_CS1_device = {
+ + 	.name          = CKB_GPMC_CS1_DEV_NAME,
+ + 	.num_resources = ARRAY_SIZE(ckb_emif_CS1_resource),
+ + 	.resource      = ckb_emif_CS1_resource,
+ + };
+ + 
+ + static inline void ckb_setup_ex_cn_cs1(void)
+ + {
+ + 	platform_device_register(&ckb_emif_CS1_device);
+ + }
+ + #endif
+ + 
+ + static struct omap_rtc_pdata am335x_rtc_info = {
+ + 	.pm_off		= true,
+ + #ifdef CONFIG_CKB_SUSPEND_SUPPORT
+ + 	.wakeup_capable	= 1,
+ + #else
+ + 	.wakeup_capable	= 0,
+ + #endif
+ + };
+ + 
+ + static void am335x_rtc_init(void)
+ + {
+ + 	void __iomem *base;
+ + 	struct clk *clk;
+ + 	struct omap_hwmod *oh;
+ + 	struct platform_device *pdev;
+ + 	char *dev_name = "am33xx-rtc";
+ + 
+ + 	clk = clk_get(NULL, "rtc_fck");
+ + 	if (IS_ERR(clk)) {
+ + 		pr_err("rtc : Failed to get RTC clock\n");
+ + 		return;
+ + 	}
+ + 
+ + 	if (clk_enable(clk)) {
+ + 		pr_err("rtc: Clock Enable Failed\n");
+ + 		return;
+ + 	}
+ + 
+ + 	base = ioremap(AM33XX_RTC_BASE, SZ_4K);
+ + 
+ + 	if (WARN_ON(!base))
+ + 		return;
+ + 
+ + 	/* Unlock the rtc's registers */
+ + 	writel(0x83e70b13, base + 0x6c);
+ + 	writel(0x95a4f1e0, base + 0x70);
+ + 
+ + 	/*
+ + 	 * Enable the 32K OSc
+ + 	 * TODO: Need a better way to handle this
+ + 	 * Since we want the clock to be running before mmc init
+ + 	 * we need to do it before the rtc probe happens
+ + 	 */
+ + 	writel(0x48, base + 0x54);
+ + 
+ + 	iounmap(base);
+ + 
+ + 	clk_disable(clk);
+ + 	clk_put(clk);
+ + 
+ + 	oh = omap_hwmod_lookup("rtc");
+ + 	if (!oh) {
+ + 		pr_err("could not look up %s\n", "rtc");
+ + 		return;
+ + 	}
+ + 
+ + 	pdev = omap_device_build(dev_name, -1, oh, &am335x_rtc_info,
+ + 			sizeof(struct omap_rtc_pdata), NULL, 0, 0);
+ + 	WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
+ + 			dev_name, oh->name);
+ + }
+ + 
+ + unsigned flash_gpios[] = { GPIO_TO_PIN(1,20), GPIO_TO_PIN(1,21), GPIO_TO_PIN(1,22), GPIO_TO_PIN(1,23),
+ + 							GPIO_TO_PIN(1,24), GPIO_TO_PIN(1,25), GPIO_TO_PIN(1,26)};
+ + static struct resource ckb_norflash_resource[] = {
+ + 	{
+ + 		/* other fields will be filled later */
+ + 		.name  = "cfi_probe",
+ + 		.flags	= IORESOURCE_MEM,
+ + 	},
+ + 	{
+ + 		.start = (unsigned long)flash_gpios,
+ +  		.end   = ARRAY_SIZE(flash_gpios),
+ + 		.flags = IORESOURCE_IRQ,
+ + 	}
+ + };
+ + 
+ + struct platform_device ckb_norflash_device = {
+ + 	.name          = "gpio-addr-flash",
+ + 	.dev           = { .platform_data = &ckb_norflash_data, },
+ + 	.num_resources = ARRAY_SIZE(ckb_norflash_resource),
+ + 	.resource      = ckb_norflash_resource,
+ + };
+ + 
+ + void board_gpmc_init(void)
+ + {
+ + 	struct gpmc_devices_info gpmc_device[1] = {
+ + 		{ NULL, 0 },
+ + 	};
+ + 
+ + 	gpmc_device[0].pdata = &ckb_norflash_data;
+ + 	gpmc_device[0].flag = GPMC_DEVICE_NOR;
+ + 
+ + 	omap_init_gpmc(gpmc_device, sizeof(gpmc_device));
+ + }
+ + 
+ + static void
+ + board_nor_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs)
+ + {
+ + 	int err;
+ + 
+ + 	/* Configure start address and size of NOR device */
+ + 	err = gpmc_cs_request(cs, FLASH_SIZE_16M - 1,
+ + 			(unsigned long *)&ckb_norflash_resource[0].start);
+ + 	ckb_norflash_resource[0].end = ckb_norflash_resource[0].start
+ + 				+ SZ_128K - 1;
+ + 	if (err < 0) {
+ + 		pr_err("NOR: Can't request GPMC CS\n");
+ + 		return;
+ + 	}
+ + 	if (platform_device_register(&ckb_norflash_device) < 0)
+ + 		pr_err("Unable to register NOR device\n");
+ + 	
+ + }
+ + 
+ + void ckb_setup_nor(void)
+ + {
+ + 	setup_pin_mux(ckb_nor_pins);
+ + 	board_gpmc_init();
+ + }
+ + 
+ + 
+ + static void rgmii1_init(void)
+ + {
+ + 	setup_pin_mux(rgmii1_pin_mux);
+ + 
+ + 	gpio_set_value_cansleep(CKB_LAN_RST_PIN, 0);
+ + 	/* issue a reset */
+ + 	if (gpio_request(CKB_LAN_RST_PIN, "LAN reset")) {
+ + 		pr_warning("Cannot open GPIO %d\n",
+ + 					CKB_LAN_RST_PIN);
+ + 	}
+ + 	else {
+ + 		/* reset the LAN chip */
+ + 		gpio_direction_output(CKB_LAN_RST_PIN, 0);
+ + 		mdelay(15);
+ + 		gpio_set_value(CKB_LAN_RST_PIN, 1);
+ + 		mdelay(1);
+ + 	}
+ + 	return;
+ + }
+ + 
+ + static void mmc0_init(void)
+ + {
+ + 	setup_pin_mux(mmc0_common_pin_mux);
+ + 	setup_pin_mux(mmc0_cd_only_pin_mux);
+ + 	omap_init_hsmmc(&mmc_sdcard);
+ + }
+ + 
+ + #ifdef CONFIG_PHYLIB
+ + volatile int reg_104 = 0x9090;
+ + volatile int reg_105 = 0x0000;
+ + 
+ + static int am33xx_evm_tx_clk_dly_phy_fixup(struct phy_device *phydev)
+ + {
+ + 	int val;
+ + 
+ + 	/* min rx data delay */
+ + 	phy_write(phydev, 0x0b, 0x8105);
+ + 	//phy_write(phydev, 0x0c, 0xFFFFa);
+ + 	phy_write(phydev, 0x0c, reg_105);
+ + 	
+ + 	/* max rx/tx clock delay, min rx/tx control delay */
+ + 
+ + 	phy_write(phydev, 0x0b, 0x8104);
+ + 	phy_write(phydev, 0x0c, reg_104);	//163~182/ 207~222
+ + 
+ + 	//phy_write(phydev, 0x0c, 0xf0f0);	//163~182/ 207~222
+ + 	//phy_write(phydev, 0x0c, 0x70f0);   // 151~188/ 219~234
+ + 	//phy_write(phydev, 0x0c, 0x7777); - NG
+ + 	//phy_write(phydev, 0x0c, 007x70);  - Ping OK, iperf NG
+ + 	//phy_write(phydev, 0x0c, 0x70A0);	//170~     226
+ + 	//phy_write(phydev, 0x0c, 0x8080);	//170~     226
+ + 	//phy_write(phydev, 0x0c, 0x8080);	//163~182/ 207~222
+ + 	//phy_write(phydev, 0x0c, 0x9950);	//163~182/ 207~222
+ + 	
+ + 	phy_write(phydev, 0x0b, 0x104);
+ + 	val =  phy_read(phydev, 0x0d);
+ + 	
+ + 	phy_write(phydev, 0x0b, 0x0105);
+ + 	val =  phy_read(phydev, 0x0d);
+ + 	
+ + 	return 0;
+ + }
+ + #endif
+ + 
+ + #if defined(CONFIG_CKB_LCD_SUPPORT) || defined(CONFIG_CKB_DVI_SUPPORT)
+ + static const struct display_panel ckb_disp_panel = {
+ + 	QVGA,
+ + 	16,
+ + 	16,
+ + 	COLOR_ACTIVE,
+ + };
+ + 
+ + static struct lcd_ctrl_config lcd_cfg = {
+ + 	&ckb_disp_panel,
+ + 	.ac_bias		= 255,
+ + 	.ac_bias_intrpt		= 0,
+ + 	.dma_burst_sz		= 16,
+ + 	.bpp			= 16,
+ + 	.fdd			= 255,
+ + 	.tft_alt_mode		= 0,
+ + 	.stn_565_mode		= 0,
+ + 	.mono_8bit_mode		= 0,
+ + 	.sync_edge		= 0,
+ + 	.sync_ctrl		= 1,
+ + 	.raster_order		= 0,
+ + 	.fifo_th		= 6,
+ + };
+ + #endif
+ + 
+ + #ifdef CONFIG_CKB_LCD_SUPPORT
+ + /* val: 0 - Backlight and LCD display off
+ + 		1 - Backlight and LCD display on
+ + 		2 - Backlight off
+ + */
+ + static void ckb_panel_power_ctrl(int val)
+ + {
+ + 	/* backlight */
+ + 	if(val==0 || val==2)
+ + 	{
+ + 		/* turn off */
+ + 		gpio_set_value(CKB_LCD_BL_PIN, 0);
+ + 		gpio_set_value(CKB_BL_TPS_PIN, 0);
+ + 	}
+ + 	else if(val==1)
+ + 	{
+ + 		/* turn on */
+ + 		gpio_set_value(CKB_LCD_BL_PIN, 1);
+ + 		gpio_set_value(CKB_BL_TPS_PIN, 1);
+ + 	}
+ + 	/* lcd power */
+ + 	if(val==0 || val==1)
+ + 		gpio_set_value(CKB_LCD_PWR_PIN, val);
+ + }
+ + #endif
+ + 
+ + #if defined(CONFIG_CKB_LCD_SUPPORT) || defined(CONFIG_CKB_DVI_SUPPORT)
+ + struct da8xx_lcdc_platform_data da8xx_pdata = {
+ + #ifdef CONFIG_CKB_LCD_01
+ + 	.manu_name		= "Visionx",
+ + 	.type			= "Visionx_KTM050AL02",
+ + #endif
+ + #ifdef CONFIG_CKB_LCD_02
+ + 	.manu_name		= "Kyocera",
+ + 	.type			= "KyoceraTCG070WVLPAAFA_AA00",
+ + #endif
+ + 	
+ + #ifdef CONFIG_CKB_LCD_SUPPORT
+ + 	.panel_power_ctrl = ckb_panel_power_ctrl,
+ + #endif
+ + #if !defined(CONFIG_CKB_LCD_SUPPORT) && defined(CONFIG_CKB_DVI_SUPPORT)
+ + 	.manu_name		= "NONE",
+ + 	.type			= "Generic DVI panel",
+ + #endif
+ + 	.controller_data	= &lcd_cfg,
+ + };
+ + 
+ + static void lcdc_init(void)
+ + {
+ + #ifdef CONFIG_CKB_LCD_SUPPORT
+ + 	int status;
+ + #endif
+ + 	setup_pin_mux(lcdc_pin_mux);
+ + 
+ + 	if (conf_disp_pll(DISP_PLL_CLK)) {
+ + 		pr_info("Failed configure display PLL, not attempting to"
+ + 				"register LCDC\n");
+ + 		return;
+ + 	}
+ + 
+ + #ifdef CONFIG_CKB_LCD_SUPPORT
+ + 	setup_pin_mux(lcdpwr_pin_mux);
+ + 	
+ + 	status = gpio_request(CKB_LCD_BL_PIN, "lcd bl\n");
+ + 	if (status < 0)
+ + 		return;
+ + 
+ + 	status = gpio_request(CKB_BL_TPS_PIN, "BL TPS\n");
+ + 	if (status < 0)
+ + 	{
+ + 		gpio_free(CKB_LCD_BL_PIN);
+ + 		return;
+ + 	}
+ + 
+ + 	status = gpio_request(CKB_LCD_PWR_PIN, "lcd pwr\n");
+ + 	if (status < 0) {
+ + 		gpio_free(CKB_LCD_BL_PIN);
+ + 		gpio_free(CKB_BL_TPS_PIN);
+ + 		return;
+ + 	}
+ + 
+ + 	/* set backlight and LCD to output and turn them on */
+ + 	gpio_direction_output(CKB_LCD_BL_PIN, 1);
+ + 	gpio_direction_output(CKB_BL_TPS_PIN, 1);
+ + 	gpio_direction_output(CKB_LCD_PWR_PIN, 1);
+ + #endif
+ + 
+ + 	da8xx_pdata.fb_mapped_physaddr = FB_DATA_ADDRESS;
+ + 	da8xx_pdata.fb_mapped_len = FB_MAP_SIZE;
+ + 	if (am33xx_register_lcdc(&da8xx_pdata))
+ + 		pr_info("Failed to register LCDC device\n");
+ + 
+ + 	return;
+ + }
+ + #endif
+ + 
+ + #ifdef CONFIG_CKB_DVI_SUPPORT
+ + struct ckb_dvi_platform_data dvi_data = {
+ + 	/* 3352 LCD controller supports upto WXGA (1366x768) */
+ + 	.max_xres = 1366,
+ + 	.max_yres = 768,
+ + 	.connect_poll_interval = 500,					/* 500 ms */
+ + 	.i2c_port = 1,
+ + };
+ + 
+ + struct platform_device ckb_dvi_device = {
+ + 	.name          = CKB_DVI_NAME,
+ + 	.dev = {
+ + 		.platform_data	= &dvi_data,
+ + 	},
+ + };
+ + #endif
+ + 
+ + #ifdef CONFIG_CKB_3352_AUDIO
+ + 
+ + static u8 am335x_iis_serializer_direction1[] = {
+ + 	INACTIVE_MODE,	INACTIVE_MODE,	TX_MODE,	RX_MODE,
+ + 	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,
+ + 	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,
+ + 	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,
+ + };
+ + 
+ + static struct snd_platform_data am335x_evm_snd_data1 = {
+ + 	.tx_dma_offset	= 0x46400000,	/* McASP1 */
+ + 	.rx_dma_offset	= 0x46400000,
+ + 	.op_mode	= DAVINCI_MCASP_IIS_MODE,
+ + 	.num_serializer	= ARRAY_SIZE(am335x_iis_serializer_direction1),
+ + 	.tdm_slots	= 2,
+ + 	.serial_dir	= am335x_iis_serializer_direction1,
+ + 	.asp_chan_q	= EVENTQ_2,
+ + 	.version	= MCASP_VERSION_3,
+ + 	.txnumevt	= 1,
+ + 	.rxnumevt	= 1,
+ + };
+ + #endif
+ + 
+ + #ifdef CONFIG_CKB_EXTCN_I2C1
+ + static struct pinmux_config extcn_i2c1_pin_mux[] = {
+ + 	{"uart0_ctsn.i2c1_sda", OMAP_MUX_MODE3 | AM33XX_INPUT_EN | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW },
+ + 	{"uart0_rtsn.i2c1_scl", OMAP_MUX_MODE3 | AM33XX_INPUT_EN | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW },
+ + 	{NULL, 0},
+ + };
+ + 
+ + static struct i2c_board_info __initdata am335x_i2c1_boardinfo[] = {
+ + };
+ + #endif
+ + 
+ + #ifdef CONFIG_CKB_EXTCN_UART4
+ + static struct pinmux_config extcn_uart4_pin_mux[] = {
+ + 	{"uart0_ctsn.uart4_rxd", OMAP_MUX_MODE1 | AM33XX_INPUT_EN | AM33XX_PULL_DISA },
+ + 	{"uart0_rtsn.uart4_txd", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT
+ + 						       | AM33XX_PULL_DISA | AM33XX_SLEWCTRL_SLOW },
+ + 	{NULL, 0},
+ + };
+ + #endif
+ + 
+ + 
+ + #ifdef CONFIG_CKB_EXTCN_CAN1
+ + static struct pinmux_config d_can_gp_pin_mux[] = {
+ + 	{"uart0_ctsn.d_can1_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
+ + 	{"uart0_rtsn.d_can1_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
+ + 	{NULL, 0},
+ + };
+ + 
+ + static void d_can_init(void)
+ + {
+ + 	setup_pin_mux(d_can_gp_pin_mux);
+ + 	am33xx_d_can_init(1);
+ + }
+ + #endif
+ + 
+ + #ifdef CONFIG_CKB_EXTCN_SPIDEV_SPI1
+ + static struct pinmux_config extcn_spi1_pin_mux[] = {
+ + 	{"mcasp0_aclkx.spi1_sclk", OMAP_MUX_MODE3 |  AM33XX_PULL_ENBL
+ + 							| AM33XX_INPUT_EN },
+ + 	{"mcasp0_fsx.spi1_d0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
+ + 							| AM33XX_PULL_UP | AM33XX_INPUT_EN},
+ + 	{"mcasp0_axr0.spi1_d1", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
+ + 							| AM33XX_INPUT_EN },
+ + 	{"mcasp0_ahclkr.spi1_cs0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
+ + 							| AM33XX_PULL_UP | AM33XX_INPUT_EN},
+ + 	{NULL, 0},
+ + };
+ + 
+ + static struct spi_board_info am335x_spi1_slave_info[] = {
+ + 	{
+ + 		.modalias      = "spidev",
+ + 		.irq           = -1,
+ + 		.max_speed_hz  = 12000000,
+ + 		.bus_num       = 2,
+ + 		.chip_select   = 0,
+ + 	},
+ + };
+ + #endif
+ + 
+ + #ifdef CONFIG_CKB_EHRPWM0
+ + static struct pinmux_config ckb_ehrpwm_pin_mux[] = {
+ + 	{"mcasp0_aclkx.ehrpwm0A", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT },
+ + 	{"mcasp0_fsx.ehrpwm0B", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT },
+ + };
+ + 
+ + static struct pwmss_platform_data  ehrpwm_pdata0 = {
+ + 	.version = PWM_VERSION_1,
+ + };
+ + 
+ + #define HAPTICS_MAX_FREQ 250
+ + void ckb_ehrpwm_init()
+ + {
+ + 	setup_pin_mux(ckb_ehrpwm_pin_mux);
+ + 	ehrpwm_pdata0.chan_attrib[1].max_freq = HAPTICS_MAX_FREQ;
+ + 	am33xx_register_ehrpwm(0, &ehrpwm_pdata0);
+ + 	//am33xx_register_ecap(0, &ehrpwm_pdata0);
+ + }
+ + 
+ + #endif
+ + 
+ + static struct pinmux_config extcn_pin_mux[] = {
+ + #ifdef CONFIG_CKB_EX_CN_PIN2_LCD_DATA12
+ + 	{"lcd_data12.lcd_data12",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN2_A16
+ + 	{"lcd_data12.gpmc_a16",	OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN2_EQEP1A_IN
+ + 	{"lcd_data12.eQEP1A_in", OMAP_MUX_MODE2 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN2_MCASP0_ACLKR
+ + 	{"lcd_data12.mcasp0_aclkr",	OMAP_MUX_MODE3 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN2_MCAP0_AXR2
+ + 	{"lcd_data12.mcasp0_axr2",	OMAP_MUX_MODE4 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN2_PR1_MII0_RXLINK
+ + 	{"lcd_data12.pr1_mii0_rxlink",	OMAP_MUX_MODE5 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN2_UART4_CTS
+ + 	{"lcd_data12.uart4_ctsn",	OMAP_MUX_MODE6 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN2_OGPIO
+ + 	{"lcd_data12.gpio0_8",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN2_IGPIO
+ + 	{"lcd_data12.gpio0_8",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + 
+ + #ifdef CONFIG_CKB_EX_CN_PIN4_LCD_DATA13
+ + 	{"lcd_data13.lcd_data13",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN4_A17
+ + 	{"lcd_data13.gpmc_a17",	OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN4_EQEP1B_IN
+ + 	{"lcd_data13.eQEP1B_in", OMAP_MUX_MODE2 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN4_MCASP0_FSR
+ + 	{"lcd_data13.mcasp0_fsr",	OMAP_MUX_MODE3 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN4_MCAP0_AXR3
+ + 	{"lcd_data13.mcasp0_axr3",	OMAP_MUX_MODE4 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN2_PR1_MII0_RXER
+ + 	{"lcd_data13.pr1_mii0_rxer",	OMAP_MUX_MODE5 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN4_UART4_RTS
+ + 	{"lcd_data13.uart4_rtsn",	OMAP_MUX_MODE6 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN4_OGPIO
+ + 	{"lcd_data13.gpio0_9",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN4_IGPIO
+ + 	{"lcd_data13.gpio0_9",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + 
+ + #ifdef CONFIG_CKB_EX_CN_PIN6_MCASP0_AHCLKR
+ + 	{"mcasp0_ahclkr.mcasp0_ahclkr",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN6_EHRPWM0_SYNCI
+ + 	{"mcasp0_ahclkr.ehrpwm0_synci", OMAP_MUX_MODE1 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN6_MCASP0_AXR2
+ + 	{"mcasp0_ahclkr.mcasp0_axr2", OMAP_MUX_MODE2 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN6_SPI1_CS0
+ + 	{"mcasp0_ahclkr.spi1_cs0",	OMAP_MUX_MODE3 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN6_ECAP2_IN_PWM2_OUT
+ + 	{"mcasp0_ahclkr.ecap2_in_pwm2_out",	OMAP_MUX_MODE4 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN6_PR1_PRU0_PRU_R30_3
+ + 	{"mcasp0_ahclkr.pr1_pru0_pru_r30_3",	OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN6_PR1_PRU0_PRU_R31_3
+ + 	{"mcasp0_ahclkr.pr1_pru0_pru_r31_3",	OMAP_MUX_MODE6 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN6_OGPIO
+ + 	{"mcasp0_ahclkr.gpio3_17",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN6_IGPIO
+ + 	{"mcasp0_ahclkr.gpio3_17",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + 
+ + #ifdef CONFIG_CKB_EX_CN_PIN10_MCASP0_FSR
+ + 	{"mcasp0_fsr.mcasp0_fsr",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN10_EQEP0B_IN
+ + 	{"mcasp0_fsr.eQEP0B_in", OMAP_MUX_MODE1 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN10_MCASP0_AXR3
+ + 	{"mcasp0_fsr.mcasp0_axr3",	OMAP_MUX_MODE2 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN10_MCASP1_FSX
+ + 	{"mcasp0_fsr.mcasp1_fsx",	OMAP_MUX_MODE3 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN10_EMU2
+ + 	{"mcasp0_fsr.EMU2",	OMAP_MUX_MODE4 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN10_PR1_PRU0_PRU_R30_5
+ + 	{"mcasp0_fsr.pr1_pru0_pru_r30_5",	OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN10_PR1_PRU0_PRU_R31_5
+ + 	{"mcasp0_fsr.pr1_pru0_pru_r31_5",	OMAP_MUX_MODE6 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN10_OGPIO
+ + 	{"mcasp0_fsr.gpio3_19",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN10_IGPIO
+ + 	{"mcasp0_fsr.gpio3_19",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + 	
+ + #ifdef CONFIG_CKB_EX_CN_PIN13_AD1
+ + 	{"gpmc_ad1.gpmc_ad1",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN13_MMC1_DAT1
+ + 	{"gpmc_ad1.mmc1_dat1", OMAP_MUX_MODE1 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN13_OGPIO
+ + 	{"gpmc_ad1.gpio1_1",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN13_IGPIO
+ + 	{"gpmc_ad1.gpio1_1",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + 	
+ + #ifdef CONFIG_CKB_EX_CN_PIN14_AD0
+ + 	{"gpmc_ad0.gpmc_ad0",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN14_MMC1_DAT0
+ + 	{"gpmc_ad0.mmc1_dat0", OMAP_MUX_MODE1 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN14_OGPIO
+ + 	{"gpmc_ad0.gpio1_0",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN14_IGPIO
+ + 	{"gpmc_ad0.gpio1_0",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + 	
+ + #ifdef CONFIG_CKB_EX_CN_PIN15_AD3
+ + 	{"gpmc_ad3.gpmc_ad3",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN15_MMC1_DAT3
+ + 	{"gpmc_ad3.mmc1_dat3", OMAP_MUX_MODE1 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN15_OGPIO
+ + 	{"gpmc_ad3.gpio1_3",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN15_IGPIO
+ + 	{"gpmc_ad3.gpio1_3",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + 
+ + #ifdef CONFIG_CKB_EX_CN_PIN16_AD2
+ + 	{"gpmc_ad2.gpmc_ad2",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN16_MMC1_DAT2
+ + 	{"gpmc_ad2.mmc1_dat2", OMAP_MUX_MODE1 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN16_OGPIO
+ + 	{"gpmc_ad2.gpio1_2",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN16_IGPIO
+ + 	{"gpmc_ad2.gpio1_2",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + 
+ + #ifdef CONFIG_CKB_EX_CN_PIN17_AD5
+ + 	{"gpmc_ad5.gpmc_ad5",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN17_MMC1_DAT5
+ + 	{"gpmc_ad5.mmc1_dat5", OMAP_MUX_MODE1 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN17_OGPIO
+ + 	{"gpmc_ad5.gpio1_5",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN17_IGPIO
+ + 	{"gpmc_ad5.gpio1_5",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + 
+ + #ifdef CONFIG_CKB_EX_CN_PIN18_AD4
+ + 	{"gpmc_ad4.gpmc_ad4",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN18_MMC1_DAT4
+ + 	{"gpmc_ad4.mmc1_dat4", OMAP_MUX_MODE1 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN18_OGPIO
+ + 	{"gpmc_ad4.gpio1_4",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN18_IGPIO
+ + 	{"gpmc_ad4.gpio1_4",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + 
+ + #ifdef CONFIG_CKB_EX_CN_PIN19_AD7
+ + 	{"gpmc_ad7.gpmc_ad7",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN19_MMC1_DAT7
+ + 	{"gpmc_ad7.mmc1_dat7", OMAP_MUX_MODE1 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN19_OGPIO
+ + 	{"gpmc_ad7.gpio1_7",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN19_IGPIO
+ + 	{"gpmc_ad7.gpio1_7",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + 
+ + #ifdef CONFIG_CKB_EX_CN_PIN20_AD6
+ + 	{"gpmc_ad6.gpmc_ad6",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN20_MMC1_DAT6
+ + 	{"gpmc_ad6.mmc1_dat6", OMAP_MUX_MODE1 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN20_OGPIO
+ + 	{"gpmc_ad6.gpio1_6",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN20_IGPIO
+ + 	{"gpmc_ad6.gpio1_6",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + 
+ + #ifdef CONFIG_CKB_EX_CN_PIN21_GPMC_CSN1
+ + 	{"gpmc_csn1.gpmc_csn1",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN21_GPMC_CLK
+ + 	{"gpmc_csn1.gpmc_clk",	OMAP_MUX_MODE1 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN21_MMC1_CLK
+ + 	{"gpmc_csn1.mmc1_clk", OMAP_MUX_MODE2 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN21_PR1_EDIO_DATA_IN6
+ + 	{"mcasp0_fsr.pr1_edio_data_in6",	OMAP_MUX_MODE3 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN21_PR1_EDIO_DATA_OUT6
+ + 	{"mcasp0_fsr.pr1_edio_data_out6",	OMAP_MUX_MODE4 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN21_PR1_PRU1_PRU_R30_12
+ + 	{"mcasp0_fsr.pr1_pru1_pru_r30_12",	OMAP_MUX_MODE4 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN21_PR1_PRU1_PRU_R31_12
+ + 	{"mcasp0_fsr.pr1_pru1_pru_r31_12",	OMAP_MUX_MODE4 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN21_OGPIO
+ + 	{"gpmc_csn1.gpio1_30",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN21_IGPIO
+ + 	{"gpmc_csn1.gpio1_30",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + 
+ + #ifdef CONFIG_CKB_EX_CN_PIN22_XDMA_EVENT_INTR0
+ + 	{"xdma_event_intr0.xdma_event_intr0",	OMAP_MUX_MODE0 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN22_TIM4
+ + 	{"xdma_event_intr0.timer4", OMAP_MUX_MODE2 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN22_CLKOUT1
+ + 	{"xdma_event_intr0.clkout1",	OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN22_SPI1_CS1
+ + 	{"xdma_event_intr0.spi1_cs1",	OMAP_MUX_MODE4 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN22_PR1_PRU1_PRU_R31_16
+ + 	{"xdma_event_intr0.pr1_pru1_pru_r31_16",	OMAP_MUX_MODE5 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN22_EMU2
+ + 	{"xdma_event_intr0.EMU2",	OMAP_MUX_MODE6 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN22_OGPIO
+ + 	{"xdma_event_intr0.gpio0_19",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN22_IGPIO
+ + 	{"xdma_event_intr0.gpio0_19",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + 
+ + #ifdef CONFIG_CKB_EX_CN_PIN23_GPMC_WEN
+ + 	{"gpmc_wen.gpmc_wen", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN23_TIM6
+ + 	{"gpmc_wen.timer6", OMAP_MUX_MODE2 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN23_OGPIO
+ + 	{"gpmc_wen.gpio2_4",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN23_IGPIO
+ + 	{"gpmc_wen.gpio2_4",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + 
+ + #ifdef CONFIG_CKB_EX_CN_PIN24_XDMA_EVENT_INTR1
+ + 	{"xdma_event_intr1.xdma_event_intr1",	OMAP_MUX_MODE0 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN24_TCLKIN
+ + 	{"xdma_event_intr1.tclkin", OMAP_MUX_MODE2 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN24_CLKOUT2
+ + 	{"xdma_event_intr1.clkout2",	OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN24_TIM7
+ + 	{"xdma_event_intr1.timer7",	OMAP_MUX_MODE4 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN24_PR1_PRU0_PRU_R31_16
+ + 	{"xdma_event_intr1.pr1_pru0_pru_r31_16",	OMAP_MUX_MODE5 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN24_EMU3
+ + 	{"xdma_event_intr1.EMU3",	OMAP_MUX_MODE6 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN24_OGPIO
+ + 	{"xdma_event_intr1.gpio0_20",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN24_IGPIO
+ + 	{"xdma_event_intr1.gpio0_20",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + 
+ + #ifdef CONFIG_CKB_EX_CN_PIN25_GPMC_OEN_REN
+ + 	{"gpmc_oen_ren.gpmc_oen_ren",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN25_TIM7
+ + 	{"gpmc_oen_ren.timer7",	OMAP_MUX_MODE2 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN25_OGPIO
+ + 	{"gpmc_oen_ren.gpio2_3",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN25_IGPIO
+ + 	{"gpmc_oen_ren.gpio2_3",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + 
+ + #ifdef CONFIG_CKB_EX_CN_PIN26_UART0_CTSN
+ + 	{"uart0_ctsn.uart0_ctsn",	OMAP_MUX_MODE0 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN26_UART4_RXD
+ + 	{"uart0_ctsn.uart4_rxd", OMAP_MUX_MODE1 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN26_DCAN1_TX
+ + 	{"uart0_ctsn.d_can1_tx",	OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN26_I2C1_SDA
+ + 	{"uart0_ctsn.i2c1_sda",	OMAP_MUX_MODE3 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN26_SPI1_D0
+ + 	{"uart0_ctsn.spi1_d0",	OMAP_MUX_MODE4 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN26_TIM7
+ + 	{"uart0_ctsn.timer7",	OMAP_MUX_MODE5 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN26_PR1_EDC_SYNC0_OUT
+ + 	{"uart0_ctsn.pr1_edc_sync0_out",	OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN26_OGPIO
+ + 	{"uart0_ctsn.gpio1_8",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN26_IGPIO
+ + 	{"uart0_ctsn.gpio1_8",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + 
+ + #ifdef CONFIG_CKB_EX_CN_PIN27_GPMC_ADVN_ALE
+ + 	{"gpmc_advn_ale.gpmc_advn_ale",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN27_TIM4
+ + 	{"gpmc_advn_ale.timer4",	OMAP_MUX_MODE2 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN27_OGPIO
+ + 	{"gpmc_advn_ale.gpio2_2",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN27_IGPIO
+ + 	{"gpmc_advn_ale.gpio2_2",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + 
+ + #ifdef CONFIG_CKB_EX_CN_PIN28_UART0_RTSN
+ + 	{"uart0_rtsn.uart0_rtsn",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN28_UART4_TXD
+ + 	{"uart0_rtsn.uart4_txd", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN28_DCAN1_RX
+ + 	{"uart0_rtsn.d_can1_rx",	OMAP_MUX_MODE2 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN28_I2C1_SCL
+ + 	{"uart0_rtsn.i2c1_scl",	OMAP_MUX_MODE3 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN28_SPI1_D1
+ + 	{"uart0_rtsn.spi1_d1",	OMAP_MUX_MODE4 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN28_SPI1_CS0
+ + 	{"uart0_rtsn.spi1_cs0",	OMAP_MUX_MODE5 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN28_PR1_EDC_SYNC1_OUT
+ + 	{"uart0_rtsn.pr1_edc_sync1_out",	OMAP_MUX_MODE6 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN28_OGPIO
+ + 	{"uart0_rtsn.gpio1_9",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN28_IGPIO
+ + 	{"uart0_rtsn.gpio1_9",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + 
+ + #ifdef CONFIG_CKB_EX_CN_PIN29_GPMC_A1
+ + 	{"gpmc_a1.gpmc_a1",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN29_MII2_RXDV
+ + 	{"gpmc_a1.mii2_rxdv", OMAP_MUX_MODE1 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN29_RGMII2_RCTL
+ + 	{"gpmc_a1.rgmii2_rctl",	OMAP_MUX_MODE2 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN29_MMC2_D0
+ + 	{"gpmc_a1.mmc2_dat0",	OMAP_MUX_MODE3 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN29_GPMC_A17
+ + 	{"gpmc_a1.gpmc_a17",	OMAP_MUX_MODE4 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN29_PR1_MII1_TXD3
+ + 	{"gpmc_a1.pr1_mii1_txd3",	OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN29_EHRPWM0_SYNCO
+ + 	{"gpmc_a1.ehrpwm0_synco",	OMAP_MUX_MODE6 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN29_OGPIO
+ + 	{"gpmc_a1.gpio1_17",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN29_IGPIO
+ + 	{"gpmc_a1.gpio1_17",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + 
+ + #ifdef CONFIG_CKB_EX_CN_PIN30_ECAP0_IN_PWM0_OUT
+ + 	{"ecap0_in_pwm0_out.ecap0_in_pwm0_out",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN30_UART3_TXD
+ + 	{"ecap0_in_pwm0_out.uart3_txd", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN30_SPI1_CS1
+ + 	{"ecap0_in_pwm0_out.spi1_cs1",	OMAP_MUX_MODE2 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN30_PR1_ECAP0_ECAP_CAPIN_APWM_O
+ + 	{"ecap0_in_pwm0_out.pr1_ecap0_ecap_capin_apwm_o",	OMAP_MUX_MODE3 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN30_SPI1_SCK
+ + 	{"ecap0_in_pwm0_out.spi1_sclk",	OMAP_MUX_MODE4 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN30_MMC0_SDWP
+ + 	{"ecap0_in_pwm0_out.mmc0_sdwp",	OMAP_MUX_MODE5 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN30_XDMA_EVENT_INTR2
+ + 	{"ecap0_in_pwm0_out.xdma_event_intr2",	OMAP_MUX_MODE6 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN30_OGPIO
+ + 	{"ecap0_in_pwm0_out.gpio0_7",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN30_IGPIO
+ + 	{"ecap0_in_pwm0_out.gpio0_7",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + 
+ + #ifdef CONFIG_CKB_EX_CN_PIN31_MCASP0_AXR0
+ + 	{"mcasp0_axr0.mcasp0_axr0",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN31_EHRPWM0_TRIPZONE_INPUT
+ + 	{"mcasp0_axr0.ehrpwm0_tripzone_input", OMAP_MUX_MODE1 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN31_SPI1_D1
+ + 	{"mcasp0_axr0.spi1_d1", OMAP_MUX_MODE3 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN31_MMC2_SDCD
+ + 	{"mcasp0_axr0.mmc2_sdcd",	OMAP_MUX_MODE4 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN31_PR1_PRU0_PRU_R30_2
+ + 	{"mcasp0_axr0.pr1_pru0_pru_r30_2",	OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN31_PR1_PRU0_PRU_R31_2
+ + 	{"mcasp0_axr0.pr1_pru0_pru_r31_2",	OMAP_MUX_MODE6 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN31_OGPIO
+ + 	{"mcasp0_axr0.gpio3_16",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN31_IGPIO
+ + 	{"mcasp0_axr0.gpio3_16",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + 
+ + #ifdef CONFIG_CKB_EX_CN_PIN33_MCASP0_AXR1
+ + 	{"mcasp0_axr1.mcasp0_axr1",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN33_EQEP0_INDEX
+ + 	{"mcasp0_axr1.eQEP0_index", OMAP_MUX_MODE1 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN33_MCASP1_AXR0
+ + 	{"mcasp0_axr1.mcasp1_axr0",	OMAP_MUX_MODE3 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN33_EMU3
+ + 	{"mcasp0_axr1.EMU3",	OMAP_MUX_MODE4 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN33_PR1_PRU0_PRU_R30_6
+ + 	{"mcasp0_axr1.pr1_pru0_pru_r30_6",	OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN33_PR1_PRU0_PRU_R31_6
+ + 	{"mcasp0_axr1.pr1_pru0_pru_r31_6",	OMAP_MUX_MODE6 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN33_OGPIO
+ + 	{"mcasp0_axr1.gpio3_20",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN33_IGPIO
+ + 	{"mcasp0_axr1.gpio3_20",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + 
+ + #ifdef CONFIG_CKB_EX_CN_PIN34_MCASP0_AHCLKX
+ + 	{"mcasp0_ahclkx.mcasp0_ahclkx",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN34_EQEP0_STROBE
+ + 	{"mcasp0_ahclkx.eQEP0_strobe", OMAP_MUX_MODE1 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN34_MCASP0_AXR3
+ + 	{"mcasp0_ahclkx.mcasp0_axr3",	OMAP_MUX_MODE2 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN34_MCASP1_AXR1
+ + 	{"mcasp0_ahclkx.mcasp1_axr1",	OMAP_MUX_MODE3 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN34_EMU4
+ + 	{"mcasp0_ahclkx.EMU4",	OMAP_MUX_MODE4 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN34_PR1_PRU0_PRU_R30_7
+ + 	{"mcasp0_ahclkx.pr1_pru0_pru_r30_7",	OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN34_PR1_PRU0_PRU_R31_7
+ + 	{"mcasp0_ahclkx.pr1_pru0_pru_r31_7",	OMAP_MUX_MODE6 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN34_OGPIO
+ + 	{"mcasp0_ahclkx.gpio3_21",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN34_IGPIO
+ + 	{"mcasp0_ahclkx.gpio3_21",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + 	
+ + #ifdef CONFIG_CKB_EX_CN_PIN36_MCASP0_ACLKX
+ + 	{"mcasp0_aclkx.mcasp0_aclkx",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN36_EHRPWM0A
+ + 	{"mcasp0_aclkx.ehrpwm0A", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN36_SPI1_SCLK
+ + 	{"mcasp0_aclkx.spi1_sclk",	OMAP_MUX_MODE3 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN36_MMC0_SDCD
+ + 	{"mcasp0_aclkx.mmc0_sdcd",	OMAP_MUX_MODE4 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN36_PR1_PRU0_PRU_R30_0
+ + 	{"mcasp0_aclkx.pr1_pru0_pru_r30_0",	OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN36_PR1_PRU0_PRU_R31_0
+ + 	{"mcasp0_aclkx.pr1_pru0_pru_r31_0",	OMAP_MUX_MODE6 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN36_OGPIO
+ + 	{"mcasp0_aclkx.gpio3_14",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN36_IGPIO
+ + 	{"mcasp0_aclkx.gpio3_14",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + 
+ + #ifdef CONFIG_CKB_EX_CN_PIN38_MCASP0_FSX
+ + 	{"mcasp0_fsx.mcasp0_fsx",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN38_EHRPWM0B
+ + 	{"mcasp0_fsx.ehrpwm0B", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN38_SPI1_D0
+ + 	{"mcasp0_fsx.spi1_d0",	OMAP_MUX_MODE3 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN38_MMC1_SDCD
+ + 	{"mcasp0_fsx.mmc1_sdcd",	OMAP_MUX_MODE4 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN38_PR1_PRU0_PRU_R30_1
+ + 	{"mcasp0_fsx.pr1_pru0_pru_r30_1",	OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN38_PR1_PRU0_PRU_R31_1
+ + 	{"mcasp0_fsx.pr1_pru0_pru_r31_1",	OMAP_MUX_MODE6 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN38_OGPIO
+ + 	{"mcasp0_fsx.gpio3_15",	OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN38_IGPIO
+ + 	{"mcasp0_fsx.gpio3_15",	OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + 	{NULL, 0},
+ + };
+ + 
+ + static struct pinmux_config wlan_cn_pin_mux[] = {
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN24_UART1_TXD
+ + 	{"uart1_txd.uart1_txd",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN24_MMC2_SDWP
+ + 	{"uart1_txd.mmc2_sdwp",	OMAP_MUX_MODE1 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN24_DCAN1_TX
+ + 	{"uart1_txd.dcan1_rx",	OMAP_MUX_MODE2 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN24_I2C1_SCL
+ + 	{"uart1_txd.i2c1_scl",	OMAP_MUX_MODE3 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN24_PR1_UART0_TXD
+ + 	{"uart1_txd.pr1_uart0_txd",	OMAP_MUX_MODE5 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN24_PR1_PRU0_PRU_R31_16
+ + 	{"uart1_txd.pr1_pru0_pru_r31_16", OMAP_MUX_MODE6 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN24_OGPIO
+ + 	{"uart1_txd.gpio0_15", OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN24_IGPIO
+ + 	{"uart1_txd.gpio0_15", OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + 
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN26_UART1_RXD
+ + 	{"uart1_rxd.uart1_rxd",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN26_MMC1_SDWP
+ + 	{"uart1_rxd.mmc1_sdwp",	OMAP_MUX_MODE1 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN26_DCAN0_TX
+ + 	{"uart1_rxd.dcan1_tx",	OMAP_MUX_MODE2 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN26_I2C1_SDA
+ + 	{"uart1_rxd.i2c1_sda",	OMAP_MUX_MODE3 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN26_PR1_UART0_RXD
+ + 	{"uart1_rxd.pr1_uart0_rxd",	OMAP_MUX_MODE5 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN26_PR1_PRU1_PRU_R31_16
+ + 	{"uart1_rxd.pr1_pru1_pru_r31_16", OMAP_MUX_MODE6 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN26_OGPIO
+ + 	{"uart1_rxd.gpio0_14", OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN26_IGPIO
+ + 	{"uart1_rxd.gpio0_14", OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + 
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN28_UART1_CTSN
+ + 	{"uart1_ctsn.uart1_ctsn",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN28_TIMER6
+ + 	{"uart1_ctsn.timer6",	OMAP_MUX_MODE1 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN28_DCAN0_TX
+ + 	{"uart1_ctsn.dcan0_tx",	OMAP_MUX_MODE2 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN28_I2C2_SDA
+ + 	{"uart1_ctsn.i2c2_sda",	OMAP_MUX_MODE3 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN28_SPI1_CS0
+ + 	{"uart1_ctsn.spi1_cs0",	OMAP_MUX_MODE4 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN28_PR1_UART0_CTS_N
+ + 	{"uart1_ctsn.pr1_uart0_cts_n",	OMAP_MUX_MODE5 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN28_PR1_EDC_LATCH0_IN
+ + 	{"uart1_ctsn.pr1_edc_latch0_in", OMAP_MUX_MODE6 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN28_OGPIO
+ + 	{"uart1_ctsn.gpio0_12", OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN28_IGPIO
+ + 	{"uart1_ctsn.gpio0_12", OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + 	
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN30_UART1_RTSN
+ + 	{"uart1_rtsn.uart1_rtsn",	OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN30_TIMER5
+ + 	{"uart1_rtsn.timer5",	OMAP_MUX_MODE1 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN30_DCAN0_RX
+ + 	{"uart1_rtsn.dcan0_rx",	OMAP_MUX_MODE2 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN30_I2C2_SCL
+ + 	{"uart1_rtsn.i2c2_scl",	OMAP_MUX_MODE3 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN30_SPI1_CS1
+ + 	{"uart1_rtsn.spi1_cs1",	OMAP_MUX_MODE4 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN30_PR1_UART0_RTS_N
+ + 	{"uart1_rtsn.pr1_uart0_rts_n",	OMAP_MUX_MODE5 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN30_PR1_EDC_LATCH1_IN
+ + 	{"uart1_rtsn.pr1_edc_latch1_in", OMAP_MUX_MODE6 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN30_OGPIO
+ + 	{"uart1_rtsn.gpio0_13", OMAP_MUX_MODE7 | AM33XX_PULL_DISA},
+ + #endif
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN30_IGPIO
+ + 	{"uart1_rtsn.gpio0_13", OMAP_MUX_MODE7 | AM33XX_INPUT_EN | AM33XX_PULL_DISA},
+ + #endif
+ + 
+ + 	{NULL, 0},
+ + };
+ + 
+ + 
+ + void configure_extcn_gpio_mode(void)
+ + {
+ + #ifdef CONFIG_CKB_EX_CN_PIN2_OGPIO
+ + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(0, 8), 0);
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN2_IGPIO
+ + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(0, 8));
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN4_OGPIO
+ + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(0, 9), 0);
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN4_IGPIO
+ + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(0, 9));
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN6_OGPIO
+ + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(3, 17), 0);
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN6_IGPIO
+ + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(3, 17));
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN10_OGPIO
+ + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(3, 19), 0);
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN10_IGPIO
+ + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(3, 19));
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN13_OGPIO
+ + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(1, 1), 0);
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN13_IGPIO
+ + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(1, 1));
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN14_OGPIO
+ + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(1, 0), 0);
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN14_IGPIO
+ + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(1, 0));
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN15_OGPIO
+ + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(1, 3), 0);
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN15_IGPIO
+ + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(1, 3));
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN16_OGPIO
+ + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(1, 2), 0);
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN16_IGPIO
+ + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(1, 2));
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN17_OGPIO
+ + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(1, 5), 0);
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN17_IGPIO
+ + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(1, 5));
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN18_OGPIO
+ + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(1, 4), 0);
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN18_IGPIO
+ + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(1, 4));
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN19_OGPIO
+ + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(1, 7), 0);
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN19_IGPIO
+ + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(1, 7));
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN20_OGPIO
+ + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(1, 6), 0);
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN20_IGPIO
+ + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(1, 6));
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN21_OGPIO
+ + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(1, 30), 0);
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN21_IGPIO
+ + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(1, 30));
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN22_OGPIO
+ + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(0, 19), 0);
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN22_IGPIO
+ + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(0, 19));
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN23_OGPIO
+ + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(2, 4), 0);
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN23_IGPIO
+ + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(2, 4));
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN24_OGPIO
+ + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(0, 20), 0);
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN24_IGPIO
+ + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(0, 20));
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN25_OGPIO
+ + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(2, 3), 0);
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN25_IGPIO
+ + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(2, 3));
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN26_OGPIO
+ + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(1, 8), 0);
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN26_IGPIO
+ + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(1, 8));
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN27_OGPIO
+ + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(2, 2), 0);
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN27_IGPIO
+ + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(2, 2));
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN28_OGPIO
+ + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(1, 9), 0);
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN28_IGPIO
+ + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(1, 9));
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN29_OGPIO
+ + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(1, 17), 0);
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN29_IGPIO
+ + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(1, 17));
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN30_OGPIO
+ + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(0, 7), 0);
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN30_IGPIO
+ + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(0, 7));
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN31_OGPIO
+ + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(3, 16), 0);
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN31_IGPIO
+ + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(3, 16));
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN33_OGPIO
+ + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(3, 20), 0);
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN33_IGPIO
+ + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(3, 20));
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN34_OGPIO
+ + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(3, 21), 0);
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN34_IGPIO
+ + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(3, 21));
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN36_OGPIO
+ + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(3, 14), 0);
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN36_IGPIO
+ + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(3, 14));
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN38_OGPIO
+ + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(3, 15), 0);
+ + #endif
+ + #ifdef CONFIG_CKB_EX_CN_PIN38_IGPIO
+ + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(3, 15));
+ + #endif
+ + }
+ + 
+ + void configure_wlan_cn_gpio_mode(void)
+ + {
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN24_OGPIO
+ + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(0, 15), 0);
+ + #endif
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN24_IGPIO
+ + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(0, 15));
+ + #endif
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN26_OGPIO
+ + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(0, 14), 0);
+ + #endif
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN26_IGPIO
+ + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(0, 14));
+ + #endif
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN28_OGPIO
+ + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(0, 12), 0);
+ + #endif
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN28_IGPIO
+ + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(0, 12));
+ + #endif
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN30_OGPIO
+ + 	SET_GPIO_TO_OUTPUT(GPIO_TO_PIN(0, 13), 0);
+ + #endif
+ + #ifdef CONFIG_CKB_WLAN_CN_PIN30_IGPIO
+ + 	SET_GPIO_TO_INPUT(GPIO_TO_PIN(0, 13));
+ + #endif
+ + }
+ + 
+ + 
+ + #ifdef CONFIG_CKB_EXTCN_ADC
+ + int am33xx_register_mfd_tscadc(struct mfd_tscadc_board *pdata);
+ + 
+ + static struct adc_data am335x_adc_data = {
+ + 	.adc_channels = 8,
+ + };
+ + 
+ + static struct mfd_tscadc_board tscadc = {
+ +     .adc_init = &am335x_adc_data,
+ + };
+ + #endif
+ + 
+ + void __iomem *am33xx_emif_base;
+ + 
+ + void __iomem * __init am33xx_get_mem_ctlr(void)
+ + {
+ + 
+ + 	am33xx_emif_base = ioremap(AM33XX_EMIF0_BASE, SZ_32K);
+ + 
+ + 	if (!am33xx_emif_base)
+ + 		pr_warning("%s: Unable to map DDR2 controller",	__func__);
+ + 
+ + 	return am33xx_emif_base;
+ + }
+ + 
+ + void __iomem *am33xx_get_ram_base(void)
+ + {
+ + 	return am33xx_emif_base;
+ + }
+ + 
+ + void __iomem *am33xx_gpio0_base;
+ + 
+ + void __iomem *am33xx_get_gpio0_base(void)
+ + {
+ + 	am33xx_gpio0_base = ioremap(AM33XX_GPIO0_BASE, SZ_4K);
+ + 
+ + 	return am33xx_gpio0_base;
+ + }
+ + 
+ + static struct resource am33xx_cpuidle_resources[] = {
+ + 	{
+ + 		.start		= AM33XX_EMIF0_BASE,
+ + 		.end		= AM33XX_EMIF0_BASE + SZ_32K - 1,
+ + 		.flags		= IORESOURCE_MEM,
+ + 	},
+ + };
+ + 
+ + /* AM33XX devices support DDR2 power down */
+ + static struct am33xx_cpuidle_config am33xx_cpuidle_pdata = {
+ + 	.ddr2_pdown	= 1,
+ + };
+ + 
+ + static struct platform_device am33xx_cpuidle_device = {
+ + 	.name			= "cpuidle-am33xx",
+ + 	.num_resources		= ARRAY_SIZE(am33xx_cpuidle_resources),
+ + 	.resource		= am33xx_cpuidle_resources,
+ + 	.dev = {
+ + 		.platform_data	= &am33xx_cpuidle_pdata,
+ + 	},
+ + };
+ + 
+ + static void __init ckb_cpuidle_init(void)
+ + {
+ + 	int ret;
+ + 
+ + 	am33xx_cpuidle_pdata.emif_base = am33xx_get_mem_ctlr();
+ + 
+ + 	ret = platform_device_register(&am33xx_cpuidle_device);
+ + 
+ + 	if (ret)
+ + 		pr_warning("AM33XX cpuidle registration failed\n");
+ + 
+ + }
+ + 
+ + void ckb_setup_lan(void)
+ + {
+ + 	char macaddr[ETH_ALEN];
+ + 
+ + 	/* 1st get the MAC address from EEPROM */
+ + 	if (get_mac_address(CKB_EMAC_MAC_OFFSET, macaddr) != 0) {
+ + 		pr_warning("Couldn't get MAC address from EEPROM\n");
+ + 	}
+ + 	am33xx_cpsw_init(AM33XX_CPSW_MODE_RGMII, macaddr, &save_mac_addr);
+ + }
+ + 
+ + static void __init ckb3352_init(void)
+ + {
+ + 	pr_info("The board is CKB 3352 with DDR3");
+ + 
+ + 	ckb_cpuidle_init();
+ + 	am33xx_mux_init(NULL);
+ + 	omap_serial_init();
+ + 
+ + 	ckb_i2c_init();
+ + 	omap_sdrc_init(NULL, NULL);
+ + 	usb_musb_init(&musb_board_data);
+ + 			 
+ + 	usb0_init();
+ + 	usb1_init();
+ + 	
+ + 	/* init mmc controller */
+ + 	omap2_hsmmc_init();
+ + 	mmc0_init();
+ + #ifdef CONFIG_SUPPORT_CMJ100
+ + 	ckb_cmj100_init();
+ + #endif
+ + 	rgmii1_init();
+ + #if defined(CONFIG_CKB_LCD_SUPPORT) || defined(CONFIG_CKB_DVI_SUPPORT)
+ + 	lcdc_init();
+ + #endif
+ + #ifdef CONFIG_CKB_DVI_SUPPORT
+ + 	if (platform_device_register(&ckb_dvi_device))
+ + 		pr_warning("CKB DVI device registration failed\n");
+ + #endif
+ + #ifdef CONFIG_SUPPORT_CKB_LED
+ + 	gpio_led_init();
+ + #endif
+ + 	/* TPS65217 regulator has full constraints */
+ + 	regulator_has_full_constraints();
+ + 
+ + #ifdef CONFIG_PHYLIB
+ + 	/* Atheros Tx Clk delay Phy fixup */
+ + 	phy_register_fixup_for_uid(AM335X_EVM_PHY_ID, AM335X_EVM_PHY_MASK,
+ + 				   am33xx_evm_tx_clk_dly_phy_fixup);
+ + #endif
+ + 	/* SmartReflex also requires board information. */
+ + 	am33xx_sr_init();
+ + #ifdef CONFIG_SUPPORT_GPMC_CS1_MEM
+ + 	gpmc_cs1_mux_enable();
+ + 	ckb_setup_ex_cn_cs1();
+ + #endif	
+ + 	ckb_setup_nor();
+ + 	am335x_rtc_init();
+ + 	
+ + #ifdef CONFIG_CKB_EXTCN_I2C1
+ + 	setup_pin_mux(extcn_i2c1_pin_mux);
+ + 	omap_register_i2c_bus(2, 48, am335x_i2c1_boardinfo,
+ + 				ARRAY_SIZE(am335x_i2c1_boardinfo));
+ + #endif
+ + #ifdef CONFIG_CKB_EXTCN_UART4
+ + 	setup_pin_mux(extcn_uart4_pin_mux);
+ + #endif
+ + #ifdef CONFIG_CKB_EXTCN_CAN1
+ + 	d_can_init();
+ + #endif
+ + #ifdef CONFIG_CKB_EXTCN_GPIO_2628
+ + 	setup_pin_mux(extcn_gp1_8_9_pin_mux);
+ + #endif
+ + #ifdef CONFIG_CKB_EXTCN_SPIDEV_SPI1
+ + 	setup_pin_mux(extcn_spi1_pin_mux);
+ + 	spi_register_board_info(am335x_spi1_slave_info,
+ + 			ARRAY_SIZE(am335x_spi1_slave_info));
+ + #endif
+ + #ifdef CONFIG_CKB_EXTCN_ADC
+ + 	if (am33xx_register_mfd_tscadc(&tscadc))
+ + 		pr_err("failed to register touchscreen device\n");
+ + #endif
+ + 	setup_pin_mux(extcn_pin_mux);
+ + 	configure_extcn_gpio_mode();
+ + 	setup_pin_mux(wlan_cn_pin_mux);
+ + 	configure_wlan_cn_gpio_mode();
+ + 
+ + #ifdef CONFIG_CKB_EHRPWM0
+ + 	ckb_ehrpwm_init();
+ + #endif
+ + 
+ + 	/* Create an alias for icss clock */
+ + 	if (clk_add_alias("pruss", NULL, "pruss_uart_gclk", NULL))
+ + 		pr_warn("failed to create an alias: icss_uart_gclk --> pruss\n");
+ + 	/* Create an alias for gfx/sgx clock */
+ + 	if (clk_add_alias("sgx_ck", NULL, "gfx_fclk", NULL))
+ + 		pr_warn("failed to create an alias: gfx_fclk --> sgx_ck\n");
+ + }
+ + 
+ + static int ckb_late_init(void)
+ + {
+ + 	board_nor_init(ckb_norflash_partition, ARRAY_SIZE(ckb_norflash_partition), 0);
+ + 	ckb_setup_lan();
+ + 	return 0;
+ + }
+ + late_initcall(ckb_late_init);
+ + 
+ + 
+ + int ckb_add_fbaddr(phys_addr_t start, phys_addr_t size)
+ + {
+ + 	FB_DATA_ADDRESS = start;
+ + 	FB_MAP_SIZE = size;
+ + 	return 0;
+ + }
+ + 
+ + static void __init ckb3352_map_io(void)
+ + {
+ + 	omap2_set_globals_am33xx();
+ + 	omapam33xx_map_common_io();
+ + 	if(FB_MAP_SIZE != 0)
+ + 	{
+ + 		/* map FB */
+ + 		struct map_desc io_desc;
+ + 		
+ + 		io_desc.pfn = __phys_to_pfn(FB_DATA_ADDRESS);
+ + 		io_desc.virtual = (unsigned long)__va(FB_DATA_ADDRESS);
+ + 		io_desc.length = FB_MAP_SIZE;
+ + 		io_desc.type = MT_DEVICE;
+ + 	
+ + 		iotable_init(&io_desc,	1);
+ + #if 0
+ + 		FB_DATA_VADDRESS = (unsigned long)ioremap(FB_DATA_ADDRESS, FB_MAP_SIZE);
+ + 		if(!FB_DATA_VADDRESS)
+ + 		{
+ + 			printk("Error: FB adress couldn't be mapped\n");
+ + 			FB_DATA_ADDRESS = 0;
+ + 		}
+ + #else
+ + 		FB_DATA_VADDRESS = io_desc.virtual;
+ + #endif
+ + 	}
+ + }
+ + 
+ + asmlinkage long sys_ckb3352_change_mux(const char __user *pin_name, unsigned int mux_mode,
+ + 				  unsigned int flags)
+ + {
+ + 	if(mux_mode < 0 || mux_mode > 7 || flags <= 7)
+ + 		return -1;
+ + 	
+ + 	if(omap_mux_init_signal(pin_name, mux_mode | flags) != 0)
+ + 	{
+ + 		printk("Error: Setting mux %s filed\n", pin_name);
+ + 		return -2;
+ + 	}
+ + 	return 0;
+ + }
+ + 
+ + MACHINE_START(CKB_3352, "Computex Kumikomi Board CKB-3352")
+ + 	/* Maintainer: Computex Co., Ltd. www.computex.co.jp */
+ + 	.atag_offset	= 0x100,
+ + 	.map_io		= ckb3352_map_io,
+ + 	.init_early	= am33xx_init_early,
+ + 	.init_irq	= ti81xx_init_irq,
+ + 	.handle_irq     = omap3_intc_handle_irq,
+ + 	.timer		= &omap3_am33xx_timer,
+ + 	.init_machine	= ckb3352_init,
+ + MACHINE_END
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/clkt_clksel.c linux-3.2.1/arch/arm/mach-ckb_3352/clkt_clksel.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/clkt_clksel.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/clkt_clksel.c	2014-11-25 13:19:14.847019297 +0900
+ ***************
+ *** 0 ****
+ --- 1,509 ----
+ + /*
+ +  * clkt_clksel.c - OMAP2/3/4 clksel clock functions
+ +  *
+ +  * Copyright (C) 2005-2008 Texas Instruments, Inc.
+ +  * Copyright (C) 2004-2010 Nokia Corporation
+ +  *
+ +  * Contacts:
+ +  * Richard Woodruff <r-woodruff2@ti.com>
+ +  * Paul Walmsley
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  *
+ +  *
+ +  * clksel clocks are clocks that do not have a fixed parent, or that
+ +  * can divide their parent's rate, or possibly both at the same time, based
+ +  * on the contents of a hardware register bitfield.
+ +  *
+ +  * All of the various mux and divider settings can be encoded into
+ +  * struct clksel* data structures, and then these can be autogenerated
+ +  * from some hardware database for each new chip generation.  This
+ +  * should avoid the need to write, review, and validate a lot of new
+ +  * clock code for each new chip, since it can be exported from the SoC
+ +  * design flow.  This is now done on OMAP4.
+ +  *
+ +  * The fusion of mux and divider clocks is a software creation.  In
+ +  * hardware reality, the multiplexer (parent selection) and the
+ +  * divider exist separately.  XXX At some point these clksel clocks
+ +  * should be split into "divider" clocks and "mux" clocks to better
+ +  * match the hardware.
+ +  *
+ +  * (The name "clksel" comes from the name of the corresponding
+ +  * register field in the OMAP2/3 family of SoCs.)
+ +  *
+ +  * XXX Currently these clocks are only used in the OMAP2/3/4 code, but
+ +  * many of the OMAP1 clocks should be convertible to use this
+ +  * mechanism.
+ +  */
+ + #undef DEBUG
+ + 
+ + #include <linux/kernel.h>
+ + #include <linux/errno.h>
+ + #include <linux/clk.h>
+ + #include <linux/io.h>
+ + 
+ + #include <plat/clock.h>
+ + 
+ + #include "clock.h"
+ + 
+ + /* Private functions */
+ + 
+ + /**
+ +  * _get_clksel_by_parent() - return clksel struct for a given clk & parent
+ +  * @clk: OMAP struct clk ptr to inspect
+ +  * @src_clk: OMAP struct clk ptr of the parent clk to search for
+ +  *
+ +  * Scan the struct clksel array associated with the clock to find
+ +  * the element associated with the supplied parent clock address.
+ +  * Returns a pointer to the struct clksel on success or NULL on error.
+ +  */
+ + static const struct clksel *_get_clksel_by_parent(struct clk *clk,
+ + 						  struct clk *src_clk)
+ + {
+ + 	const struct clksel *clks;
+ + 
+ + 	for (clks = clk->clksel; clks->parent; clks++)
+ + 		if (clks->parent == src_clk)
+ + 			break; /* Found the requested parent */
+ + 
+ + 	if (!clks->parent) {
+ + 		/* This indicates a data problem */
+ + 		WARN(1, "clock: Could not find parent clock %s in clksel array "
+ + 		     "of clock %s\n", src_clk->name, clk->name);
+ + 		return NULL;
+ + 	}
+ + 
+ + 	return clks;
+ + }
+ + 
+ + /**
+ +  * _get_div_and_fieldval() - find the new clksel divisor and field value to use
+ +  * @src_clk: planned new parent struct clk *
+ +  * @clk: struct clk * that is being reparented
+ +  * @field_val: pointer to a u32 to contain the register data for the divisor
+ +  *
+ +  * Given an intended new parent struct clk * @src_clk, and the struct
+ +  * clk * @clk to the clock that is being reparented, find the
+ +  * appropriate rate divisor for the new clock (returned as the return
+ +  * value), and the corresponding register bitfield data to program to
+ +  * reach that divisor (returned in the u32 pointed to by @field_val).
+ +  * Returns 0 on error, or returns the newly-selected divisor upon
+ +  * success (in this latter case, the corresponding register bitfield
+ +  * value is passed back in the variable pointed to by @field_val)
+ +  */
+ + static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
+ + 				u32 *field_val)
+ + {
+ + 	const struct clksel *clks;
+ + 	const struct clksel_rate *clkr, *max_clkr = NULL;
+ + 	u8 max_div = 0;
+ + 
+ + 	clks = _get_clksel_by_parent(clk, src_clk);
+ + 	if (!clks)
+ + 		return 0;
+ + 
+ + 	/*
+ + 	 * Find the highest divisor (e.g., the one resulting in the
+ + 	 * lowest rate) to use as the default.  This should avoid
+ + 	 * clock rates that are too high for the device.  XXX A better
+ + 	 * solution here would be to try to determine if there is a
+ + 	 * divisor matching the original clock rate before the parent
+ + 	 * switch, and if it cannot be found, to fall back to the
+ + 	 * highest divisor.
+ + 	 */
+ + 	for (clkr = clks->rates; clkr->div; clkr++) {
+ + 		if (!(clkr->flags & cpu_mask))
+ + 			continue;
+ + 
+ + 		if (clkr->div > max_div) {
+ + 			max_div = clkr->div;
+ + 			max_clkr = clkr;
+ + 		}
+ + 	}
+ + 
+ + 	if (max_div == 0) {
+ + 		/* This indicates an error in the clksel data */
+ + 		WARN(1, "clock: Could not find divisor for clock %s parent %s"
+ + 		     "\n", clk->name, src_clk->parent->name);
+ + 		return 0;
+ + 	}
+ + 
+ + 	*field_val = max_clkr->val;
+ + 
+ + 	return max_div;
+ + }
+ + 
+ + /**
+ +  * _write_clksel_reg() - program a clock's clksel register in hardware
+ +  * @clk: struct clk * to program
+ +  * @v: clksel bitfield value to program (with LSB at bit 0)
+ +  *
+ +  * Shift the clksel register bitfield value @v to its appropriate
+ +  * location in the clksel register and write it in.  This function
+ +  * will ensure that the write to the clksel_reg reaches its
+ +  * destination before returning -- important since PRM and CM register
+ +  * accesses can be quite slow compared to ARM cycles -- but does not
+ +  * take into account any time the hardware might take to switch the
+ +  * clock source.
+ +  */
+ + static void _write_clksel_reg(struct clk *clk, u32 field_val)
+ + {
+ + 	u32 v;
+ + 
+ + 	v = __raw_readl(clk->clksel_reg);
+ + 	v &= ~clk->clksel_mask;
+ + 	v |= field_val << __ffs(clk->clksel_mask);
+ + 	__raw_writel(v, clk->clksel_reg);
+ + 
+ + 	v = __raw_readl(clk->clksel_reg); /* OCP barrier */
+ + }
+ + 
+ + /**
+ +  * _clksel_to_divisor() - turn clksel field value into integer divider
+ +  * @clk: OMAP struct clk to use
+ +  * @field_val: register field value to find
+ +  *
+ +  * Given a struct clk of a rate-selectable clksel clock, and a register field
+ +  * value to search for, find the corresponding clock divisor.  The register
+ +  * field value should be pre-masked and shifted down so the LSB is at bit 0
+ +  * before calling.  Returns 0 on error or returns the actual integer divisor
+ +  * upon success.
+ +  */
+ + static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
+ + {
+ + 	const struct clksel *clks;
+ + 	const struct clksel_rate *clkr;
+ + 
+ + 	clks = _get_clksel_by_parent(clk, clk->parent);
+ + 	if (!clks)
+ + 		return 0;
+ + 
+ + 	for (clkr = clks->rates; clkr->div; clkr++) {
+ + 		if (!(clkr->flags & cpu_mask))
+ + 			continue;
+ + 
+ + 		if (clkr->val == field_val)
+ + 			break;
+ + 	}
+ + 
+ + 	if (!clkr->div) {
+ + 		/* This indicates a data error */
+ + 		WARN(1, "clock: Could not find fieldval %d for clock %s parent "
+ + 		     "%s\n", field_val, clk->name, clk->parent->name);
+ + 		return 0;
+ + 	}
+ + 
+ + 	return clkr->div;
+ + }
+ + 
+ + /**
+ +  * _divisor_to_clksel() - turn clksel integer divisor into a field value
+ +  * @clk: OMAP struct clk to use
+ +  * @div: integer divisor to search for
+ +  *
+ +  * Given a struct clk of a rate-selectable clksel clock, and a clock
+ +  * divisor, find the corresponding register field value.  Returns the
+ +  * register field value _before_ left-shifting (i.e., LSB is at bit
+ +  * 0); or returns 0xFFFFFFFF (~0) upon error.
+ +  */
+ + static u32 _divisor_to_clksel(struct clk *clk, u32 div)
+ + {
+ + 	const struct clksel *clks;
+ + 	const struct clksel_rate *clkr;
+ + 
+ + 	/* should never happen */
+ + 	WARN_ON(div == 0);
+ + 
+ + 	clks = _get_clksel_by_parent(clk, clk->parent);
+ + 	if (!clks)
+ + 		return ~0;
+ + 
+ + 	for (clkr = clks->rates; clkr->div; clkr++) {
+ + 		if (!(clkr->flags & cpu_mask))
+ + 			continue;
+ + 
+ + 		if (clkr->div == div)
+ + 			break;
+ + 	}
+ + 
+ + 	if (!clkr->div) {
+ + 		pr_err("clock: Could not find divisor %d for clock %s parent "
+ + 		       "%s\n", div, clk->name, clk->parent->name);
+ + 		return ~0;
+ + 	}
+ + 
+ + 	return clkr->val;
+ + }
+ + 
+ + /**
+ +  * _read_divisor() - get current divisor applied to parent clock (from hdwr)
+ +  * @clk: OMAP struct clk to use.
+ +  *
+ +  * Read the current divisor register value for @clk that is programmed
+ +  * into the hardware, convert it into the actual divisor value, and
+ +  * return it; or return 0 on error.
+ +  */
+ + static u32 _read_divisor(struct clk *clk)
+ + {
+ + 	u32 v;
+ + 
+ + 	if (!clk->clksel || !clk->clksel_mask)
+ + 		return 0;
+ + 
+ + 	v = __raw_readl(clk->clksel_reg);
+ + 	v &= clk->clksel_mask;
+ + 	v >>= __ffs(clk->clksel_mask);
+ + 
+ + 	return _clksel_to_divisor(clk, v);
+ + }
+ + 
+ + /* Public functions */
+ + 
+ + /**
+ +  * omap2_clksel_round_rate_div() - find divisor for the given clock and rate
+ +  * @clk: OMAP struct clk to use
+ +  * @target_rate: desired clock rate
+ +  * @new_div: ptr to where we should store the divisor
+ +  *
+ +  * Finds 'best' divider value in an array based on the source and target
+ +  * rates.  The divider array must be sorted with smallest divider first.
+ +  * This function is also used by the DPLL3 M2 divider code.
+ +  *
+ +  * Returns the rounded clock rate or returns 0xffffffff on error.
+ +  */
+ + u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
+ + 				u32 *new_div)
+ + {
+ + 	unsigned long test_rate;
+ + 	const struct clksel *clks;
+ + 	const struct clksel_rate *clkr;
+ + 	u32 last_div = 0;
+ + 
+ + 	if (!clk->clksel || !clk->clksel_mask)
+ + 		return ~0;
+ + 
+ + 	pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
+ + 		 clk->name, target_rate);
+ + 
+ + 	*new_div = 1;
+ + 
+ + 	clks = _get_clksel_by_parent(clk, clk->parent);
+ + 	if (!clks)
+ + 		return ~0;
+ + 
+ + 	for (clkr = clks->rates; clkr->div; clkr++) {
+ + 		if (!(clkr->flags & cpu_mask))
+ + 			continue;
+ + 
+ + 		/* Sanity check */
+ + 		if (clkr->div <= last_div)
+ + 			pr_err("clock: clksel_rate table not sorted "
+ + 			       "for clock %s", clk->name);
+ + 
+ + 		last_div = clkr->div;
+ + 
+ + 		test_rate = clk->parent->rate / clkr->div;
+ + 
+ + 		if (test_rate <= target_rate)
+ + 			break; /* found it */
+ + 	}
+ + 
+ + 	if (!clkr->div) {
+ + 		pr_err("clock: Could not find divisor for target "
+ + 		       "rate %ld for clock %s parent %s\n", target_rate,
+ + 		       clk->name, clk->parent->name);
+ + 		return ~0;
+ + 	}
+ + 
+ + 	*new_div = clkr->div;
+ + 
+ + 	pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div,
+ + 		 (clk->parent->rate / clkr->div));
+ + 
+ + 	return clk->parent->rate / clkr->div;
+ + }
+ + 
+ + /*
+ +  * Clocktype interface functions to the OMAP clock code
+ +  * (i.e., those used in struct clk field function pointers, etc.)
+ +  */
+ + 
+ + /**
+ +  * omap2_init_clksel_parent() - set a clksel clk's parent field from the hdwr
+ +  * @clk: OMAP clock struct ptr to use
+ +  *
+ +  * Given a pointer @clk to a source-selectable struct clk, read the
+ +  * hardware register and determine what its parent is currently set
+ +  * to.  Update @clk's .parent field with the appropriate clk ptr.  No
+ +  * return value.
+ +  */
+ + void omap2_init_clksel_parent(struct clk *clk)
+ + {
+ + 	const struct clksel *clks;
+ + 	const struct clksel_rate *clkr;
+ + 	u32 r, found = 0;
+ + 
+ + 	if (!clk->clksel || !clk->clksel_mask)
+ + 		return;
+ + 
+ + 	r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
+ + 	r >>= __ffs(clk->clksel_mask);
+ + 
+ + 	for (clks = clk->clksel; clks->parent && !found; clks++) {
+ + 		for (clkr = clks->rates; clkr->div && !found; clkr++) {
+ + 			if (!(clkr->flags & cpu_mask))
+ + 				continue;
+ + 
+ + 			if (clkr->val == r) {
+ + 				if (clk->parent != clks->parent) {
+ + 					pr_debug("clock: inited %s parent "
+ + 						 "to %s (was %s)\n",
+ + 						 clk->name, clks->parent->name,
+ + 						 ((clk->parent) ?
+ + 						  clk->parent->name : "NULL"));
+ + 					clk_reparent(clk, clks->parent);
+ + 				};
+ + 				found = 1;
+ + 			}
+ + 		}
+ + 	}
+ + 
+ + 	/* This indicates a data error */
+ + 	WARN(!found, "clock: %s: init parent: could not find regval %0x\n",
+ + 	     clk->name, r);
+ + 
+ + 	return;
+ + }
+ + 
+ + /**
+ +  * omap2_clksel_recalc() - function ptr to pass via struct clk .recalc field
+ +  * @clk: struct clk *
+ +  *
+ +  * This function is intended to be called only by the clock framework.
+ +  * Each clksel clock should have its struct clk .recalc field set to this
+ +  * function.  Returns the clock's current rate, based on its parent's rate
+ +  * and its current divisor setting in the hardware.
+ +  */
+ + unsigned long omap2_clksel_recalc(struct clk *clk)
+ + {
+ + 	unsigned long rate;
+ + 	u32 div = 0;
+ + 
+ + 	div = _read_divisor(clk);
+ + 	if (div == 0)
+ + 		return clk->rate;
+ + 
+ + 	rate = clk->parent->rate / div;
+ + 
+ + 	pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n", clk->name,
+ + 		 rate, div);
+ + 
+ + 	return rate;
+ + }
+ + 
+ + /**
+ +  * omap2_clksel_round_rate() - find rounded rate for the given clock and rate
+ +  * @clk: OMAP struct clk to use
+ +  * @target_rate: desired clock rate
+ +  *
+ +  * This function is intended to be called only by the clock framework.
+ +  * Finds best target rate based on the source clock and possible dividers.
+ +  * rates. The divider array must be sorted with smallest divider first.
+ +  *
+ +  * Returns the rounded clock rate or returns 0xffffffff on error.
+ +  */
+ + long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
+ + {
+ + 	u32 new_div;
+ + 
+ + 	return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
+ + }
+ + 
+ + /**
+ +  * omap2_clksel_set_rate() - program clock rate in hardware
+ +  * @clk: struct clk * to program rate
+ +  * @rate: target rate to program
+ +  *
+ +  * This function is intended to be called only by the clock framework.
+ +  * Program @clk's rate to @rate in the hardware.  The clock can be
+ +  * either enabled or disabled when this happens, although if the clock
+ +  * is enabled, some downstream devices may glitch or behave
+ +  * unpredictably when the clock rate is changed - this depends on the
+ +  * hardware. This function does not currently check the usecount of
+ +  * the clock, so if multiple drivers are using the clock, and the rate
+ +  * is changed, they will all be affected without any notification.
+ +  * Returns -EINVAL upon error, or 0 upon success.
+ +  */
+ + int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
+ + {
+ + 	u32 field_val, validrate, new_div = 0;
+ + 
+ + 	if (!clk->clksel || !clk->clksel_mask)
+ + 		return -EINVAL;
+ + 
+ + 	validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
+ + 	if (validrate != rate)
+ + 		return -EINVAL;
+ + 
+ + 	field_val = _divisor_to_clksel(clk, new_div);
+ + 	if (field_val == ~0)
+ + 		return -EINVAL;
+ + 
+ + 	_write_clksel_reg(clk, field_val);
+ + 
+ + 	clk->rate = clk->parent->rate / new_div;
+ + 
+ + 	pr_debug("clock: %s: set rate to %ld\n", clk->name, clk->rate);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /*
+ +  * Clksel parent setting function - not passed in struct clk function
+ +  * pointer - instead, the OMAP clock code currently assumes that any
+ +  * parent-setting clock is a clksel clock, and calls
+ +  * omap2_clksel_set_parent() by default
+ +  */
+ + 
+ + /**
+ +  * omap2_clksel_set_parent() - change a clock's parent clock
+ +  * @clk: struct clk * of the child clock
+ +  * @new_parent: struct clk * of the new parent clock
+ +  *
+ +  * This function is intended to be called only by the clock framework.
+ +  * Change the parent clock of clock @clk to @new_parent.  This is
+ +  * intended to be used while @clk is disabled.  This function does not
+ +  * currently check the usecount of the clock, so if multiple drivers
+ +  * are using the clock, and the parent is changed, they will all be
+ +  * affected without any notification.  Returns -EINVAL upon error, or
+ +  * 0 upon success.
+ +  */
+ + int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent)
+ + {
+ + 	u32 field_val = 0;
+ + 	u32 parent_div;
+ + 
+ + 	if (!clk->clksel || !clk->clksel_mask)
+ + 		return -EINVAL;
+ + 
+ + 	parent_div = _get_div_and_fieldval(new_parent, clk, &field_val);
+ + 	if (!parent_div)
+ + 		return -EINVAL;
+ + 
+ + 	_write_clksel_reg(clk, field_val);
+ + 
+ + 	clk_reparent(clk, new_parent);
+ + 
+ + 	/* CLKSEL clocks follow their parents' rates, divided by a divisor */
+ + 	clk->rate = new_parent->rate;
+ + 
+ + 	if (parent_div > 0)
+ + 		clk->rate /= parent_div;
+ + 
+ + 	pr_debug("clock: %s: set parent to %s (new rate %ld)\n",
+ + 		 clk->name, clk->parent->name, clk->rate);
+ + 
+ + 	return 0;
+ + }
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/clkt_dpll.c linux-3.2.1/arch/arm/mach-ckb_3352/clkt_dpll.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/clkt_dpll.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/clkt_dpll.c	2014-11-25 13:19:14.851889393 +0900
+ ***************
+ *** 0 ****
+ --- 1,328 ----
+ + /*
+ +  * OMAP2/3/4 DPLL clock functions
+ +  *
+ +  * Copyright (C) 2005-2008 Texas Instruments, Inc.
+ +  * Copyright (C) 2004-2010 Nokia Corporation
+ +  *
+ +  * Contacts:
+ +  * Richard Woodruff <r-woodruff2@ti.com>
+ +  * Paul Walmsley
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + #undef DEBUG
+ + 
+ + #include <linux/kernel.h>
+ + #include <linux/errno.h>
+ + #include <linux/clk.h>
+ + #include <linux/io.h>
+ + 
+ + #include <asm/div64.h>
+ + 
+ + #include <plat/clock.h>
+ + 
+ + #include "clock.h"
+ + #include "cm-regbits-34xx.h"
+ + 
+ + /* DPLL rate rounding: minimum DPLL multiplier, divider values */
+ + #define DPLL_MIN_MULTIPLIER		2
+ + #define DPLL_MIN_DIVIDER		1
+ + 
+ + /* Possible error results from _dpll_test_mult */
+ + #define DPLL_MULT_UNDERFLOW		-1
+ + 
+ + /*
+ +  * Scale factor to mitigate roundoff errors in DPLL rate rounding.
+ +  * The higher the scale factor, the greater the risk of arithmetic overflow,
+ +  * but the closer the rounded rate to the target rate.  DPLL_SCALE_FACTOR
+ +  * must be a power of DPLL_SCALE_BASE.
+ +  */
+ + #define DPLL_SCALE_FACTOR		64
+ + #define DPLL_SCALE_BASE			2
+ + #define DPLL_ROUNDING_VAL		((DPLL_SCALE_BASE / 2) * \
+ + 					 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
+ + 
+ + /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
+ + #define OMAP3430_DPLL_FINT_BAND1_MIN	750000
+ + #define OMAP3430_DPLL_FINT_BAND1_MAX	2100000
+ + #define OMAP3430_DPLL_FINT_BAND2_MIN	7500000
+ + #define OMAP3430_DPLL_FINT_BAND2_MAX	21000000
+ + 
+ + /*
+ +  * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
+ +  * From device data manual section 4.3 "DPLL and DLL Specifications".
+ +  */
+ + #define OMAP3PLUS_DPLL_FINT_JTYPE_MIN	500000
+ + #define OMAP3PLUS_DPLL_FINT_JTYPE_MAX	2500000
+ + #define OMAP3PLUS_DPLL_FINT_MIN		32000
+ + #define OMAP3PLUS_DPLL_FINT_MAX		52000000
+ + 
+ + /* _dpll_test_fint() return codes */
+ + #define DPLL_FINT_UNDERFLOW		-1
+ + #define DPLL_FINT_INVALID		-2
+ + 
+ + /* Private functions */
+ + 
+ + /*
+ +  * _dpll_test_fint - test whether an Fint value is valid for the DPLL
+ +  * @clk: DPLL struct clk to test
+ +  * @n: divider value (N) to test
+ +  *
+ +  * Tests whether a particular divider @n will result in a valid DPLL
+ +  * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
+ +  * Correction".  Returns 0 if OK, -1 if the enclosing loop can terminate
+ +  * (assuming that it is counting N upwards), or -2 if the enclosing loop
+ +  * should skip to the next iteration (again assuming N is increasing).
+ +  */
+ + static int _dpll_test_fint(struct clk *clk, u8 n)
+ + {
+ + 	struct dpll_data *dd;
+ + 	long fint, fint_min, fint_max;
+ + 	int ret = 0;
+ + 
+ + 	dd = clk->dpll_data;
+ + 
+ + 	/* DPLL divider must result in a valid jitter correction val */
+ + 	fint = clk->parent->rate / n;
+ + 
+ + 	if (dd->flags & DPLL_J_TYPE) {
+ + 		fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN;
+ + 		fint_max = OMAP3PLUS_DPLL_FINT_JTYPE_MAX;
+ + 	} else {
+ + 		fint_min = OMAP3PLUS_DPLL_FINT_MIN;
+ + 		fint_max = OMAP3PLUS_DPLL_FINT_MAX;
+ + 	}
+ + 
+ + 	if (fint < fint_min) {
+ + 		pr_debug("rejecting n=%d due to Fint failure, "
+ + 			 "lowering max_divider\n", n);
+ + 		dd->max_divider = n;
+ + 		ret = DPLL_FINT_UNDERFLOW;
+ + 	} else if (fint > fint_max) {
+ + 		pr_debug("rejecting n=%d due to Fint failure, "
+ + 			 "boosting min_divider\n", n);
+ + 		dd->min_divider = n;
+ + 		ret = DPLL_FINT_INVALID;
+ + 	}
+ + 
+ + 	return ret;
+ + }
+ + 
+ + static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
+ + 					    unsigned int m, unsigned int n)
+ + {
+ + 	unsigned long long num;
+ + 
+ + 	num = (unsigned long long)parent_rate * m;
+ + 	do_div(num, n);
+ + 	return num;
+ + }
+ + 
+ + /*
+ +  * _dpll_test_mult - test a DPLL multiplier value
+ +  * @m: pointer to the DPLL m (multiplier) value under test
+ +  * @n: current DPLL n (divider) value under test
+ +  * @new_rate: pointer to storage for the resulting rounded rate
+ +  * @target_rate: the desired DPLL rate
+ +  * @parent_rate: the DPLL's parent clock rate
+ +  *
+ +  * This code tests a DPLL multiplier value, ensuring that the
+ +  * resulting rate will not be higher than the target_rate, and that
+ +  * the multiplier value itself is valid for the DPLL.  Initially, the
+ +  * integer pointed to by the m argument should be prescaled by
+ +  * multiplying by DPLL_SCALE_FACTOR.  The code will replace this with
+ +  * a non-scaled m upon return.  This non-scaled m will result in a
+ +  * new_rate as close as possible to target_rate (but not greater than
+ +  * target_rate) given the current (parent_rate, n, prescaled m)
+ +  * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
+ +  * non-scaled m attempted to underflow, which can allow the calling
+ +  * function to bail out early; or 0 upon success.
+ +  */
+ + static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
+ + 			   unsigned long target_rate,
+ + 			   unsigned long parent_rate)
+ + {
+ + 	int r = 0, carry = 0;
+ + 
+ + 	/* Unscale m and round if necessary */
+ + 	if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
+ + 		carry = 1;
+ + 	*m = (*m / DPLL_SCALE_FACTOR) + carry;
+ + 
+ + 	/*
+ + 	 * The new rate must be <= the target rate to avoid programming
+ + 	 * a rate that is impossible for the hardware to handle
+ + 	 */
+ + 	*new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
+ + 	if (*new_rate > target_rate) {
+ + 		(*m)--;
+ + 		*new_rate = 0;
+ + 	}
+ + 
+ + 	/* Guard against m underflow */
+ + 	if (*m < DPLL_MIN_MULTIPLIER) {
+ + 		*m = DPLL_MIN_MULTIPLIER;
+ + 		*new_rate = 0;
+ + 		r = DPLL_MULT_UNDERFLOW;
+ + 	}
+ + 
+ + 	if (*new_rate == 0)
+ + 		*new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
+ + 
+ + 	return r;
+ + }
+ + 
+ + /* Public functions */
+ + 
+ + void omap2_init_dpll_parent(struct clk *clk)
+ + {
+ + 	u32 v;
+ + 	struct dpll_data *dd;
+ + 
+ + 	dd = clk->dpll_data;
+ + 	if (!dd)
+ + 		return;
+ + 
+ + 	v = __raw_readl(dd->control_reg);
+ + 	v &= dd->enable_mask;
+ + 	v >>= __ffs(dd->enable_mask);
+ + 
+ + 	/* Reparent the struct clk in case the dpll is in bypass */
+ + 	if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
+ + 	    v == OMAP3XXX_EN_DPLL_FRBYPASS ||
+ + 	    v == OMAP4XXX_EN_DPLL_MNBYPASS)
+ + 		clk_reparent(clk, dd->clk_bypass);
+ + 	
+ + 	return;
+ + }
+ + 
+ + /**
+ +  * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
+ +  * @clk: struct clk * of a DPLL
+ +  *
+ +  * DPLLs can be locked or bypassed - basically, enabled or disabled.
+ +  * When locked, the DPLL output depends on the M and N values.  When
+ +  * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock
+ +  * or sys_clk.  Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
+ +  * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively
+ +  * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
+ +  * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is
+ +  * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
+ +  * if the clock @clk is not a DPLL.
+ +  */
+ + u32 omap2_get_dpll_rate(struct clk *clk)
+ + {
+ + 	long long dpll_clk;
+ + 	u32 dpll_mult, dpll_div, v;
+ + 	struct dpll_data *dd;
+ + 
+ + 	dd = clk->dpll_data;
+ + 	if (!dd)
+ + 		return 0;
+ + 
+ + 	/* Return bypass rate if DPLL is bypassed */
+ + 	v = __raw_readl(dd->control_reg);
+ + 	v &= dd->enable_mask;
+ + 	v >>= __ffs(dd->enable_mask);
+ + 
+ + 	if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
+ + 	    v == OMAP3XXX_EN_DPLL_FRBYPASS ||
+ + 	    v == OMAP4XXX_EN_DPLL_MNBYPASS)
+ + 		return dd->clk_bypass->rate;
+ + 	
+ + 	v = __raw_readl(dd->mult_div1_reg);
+ + 	dpll_mult = v & dd->mult_mask;
+ + 	dpll_mult >>= __ffs(dd->mult_mask);
+ + 	dpll_div = v & dd->div1_mask;
+ + 	dpll_div >>= __ffs(dd->div1_mask);
+ + 
+ + 	dpll_clk = (long long)dd->clk_ref->rate * dpll_mult;
+ + 	do_div(dpll_clk, dpll_div + 1);
+ + 
+ + 	return dpll_clk;
+ + }
+ + 
+ + /* DPLL rate rounding code */
+ + 
+ + /**
+ +  * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
+ +  * @clk: struct clk * for a DPLL
+ +  * @target_rate: desired DPLL clock rate
+ +  *
+ +  * Given a DPLL and a desired target rate, round the target rate to a
+ +  * possible, programmable rate for this DPLL.  Attempts to select the
+ +  * minimum possible n.  Stores the computed (m, n) in the DPLL's
+ +  * dpll_data structure so set_rate() will not need to call this
+ +  * (expensive) function again.  Returns ~0 if the target rate cannot
+ +  * be rounded, or the rounded rate upon success.
+ +  */
+ + long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
+ + {
+ + 	int m, n, r, scaled_max_m;
+ + 	unsigned long scaled_rt_rp;
+ + 	unsigned long new_rate = 0;
+ + 	struct dpll_data *dd;
+ + 
+ + 	if (!clk || !clk->dpll_data)
+ + 		return ~0;
+ + 
+ + 	dd = clk->dpll_data;
+ + 
+ + 	pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n",
+ + 		 clk->name, target_rate);
+ + 
+ + 	scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR);
+ + 	scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
+ + 
+ + 	dd->last_rounded_rate = 0;
+ + 
+ + 	for (n = dd->min_divider; n <= dd->max_divider; n++) {
+ + 
+ + 		/* Is the (input clk, divider) pair valid for the DPLL? */
+ + 		r = _dpll_test_fint(clk, n);
+ + 		if (r == DPLL_FINT_UNDERFLOW)
+ + 			break;
+ + 		else if (r == DPLL_FINT_INVALID)
+ + 			continue;
+ + 
+ + 		/* Compute the scaled DPLL multiplier, based on the divider */
+ + 		m = scaled_rt_rp * n;
+ + 
+ + 		/*
+ + 		 * Since we're counting n up, a m overflow means we
+ + 		 * can bail out completely (since as n increases in
+ + 		 * the next iteration, there's no way that m can
+ + 		 * increase beyond the current m)
+ + 		 */
+ + 		if (m > scaled_max_m)
+ + 			break;
+ + 
+ + 		r = _dpll_test_mult(&m, n, &new_rate, target_rate,
+ + 				    dd->clk_ref->rate);
+ + 
+ + 		/* m can't be set low enough for this n - try with a larger n */
+ + 		if (r == DPLL_MULT_UNDERFLOW)
+ + 			continue;
+ + 
+ + 		pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n",
+ + 			 clk->name, m, n, new_rate);
+ + 
+ + 		if (target_rate == new_rate) {
+ + 			dd->last_rounded_m = m;
+ + 			dd->last_rounded_n = n;
+ + 			dd->last_rounded_rate = target_rate;
+ + 			break;
+ + 		}
+ + 	}
+ + 
+ + 	if (target_rate != new_rate) {
+ + 		pr_debug("clock: %s: cannot round to rate %ld\n", clk->name,
+ + 			 target_rate);
+ + 		return ~0;
+ + 	}
+ + 
+ + 	return target_rate;
+ + }
+ + 
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/clock33xx_data.c linux-3.2.1/arch/arm/mach-ckb_3352/clock33xx_data.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/clock33xx_data.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/clock33xx_data.c	2014-11-25 13:19:14.851889393 +0900
+ ***************
+ *** 0 ****
+ --- 1,2254 ----
+ + /*
+ +  * AM33XX Clock data
+ +  *
+ +  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #include <linux/kernel.h>
+ + #include <linux/list.h>
+ + #include <linux/clk.h>
+ + #include <plat/clkdev_omap.h>
+ + 
+ + #include "control.h"
+ + #include "clock.h"
+ + #include "clock33xx.h"
+ + #include "cm.h"
+ + #include "cm33xx.h"
+ + #include "cm-regbits-33xx.h"
+ + #include "prm.h"
+ + 
+ + /* Modulemode control */
+ + #define AM33XX_MODULEMODE_HWCTRL	0
+ + #define AM33XX_MODULEMODE_SWCTRL	1
+ + 
+ + /* Root clocks */
+ + static struct clk clk_32768_ck = {
+ + 	.name		= "clk_32768_ck",
+ + 	.rate		= 32768,
+ + 	.ops		= &clkops_null,
+ + };
+ + 
+ + /* On-Chip 32KHz RC OSC */
+ + static struct clk clk_rc32k_ck = {
+ + 	.name		= "clk_rc32k_ck",
+ + 	.rate		= 32000,
+ + 	.ops		= &clkops_null,
+ + };
+ + 
+ + /* Crystal input clks */
+ + static struct clk virt_19_2m_ck = {
+ + 	.name		= "virt_19_2m_ck",
+ + 	.rate		= 19200000,
+ + 	.ops		= &clkops_null,
+ + };
+ + 
+ + static struct clk virt_24m_ck = {
+ + 	.name		= "virt_24m_ck",
+ + 	.rate		= 24000000,
+ + 	.ops		= &clkops_null,
+ + };
+ + 
+ + static struct clk virt_25m_ck = {
+ + 	.name		= "virt_25m_ck",
+ + 	.rate		= 25000000,
+ + 	.ops		= &clkops_null,
+ + };
+ + 
+ + static struct clk virt_26m_ck = {
+ + 	.name		= "virt_26m_ck",
+ + 	.rate		= 26000000,
+ + 	.ops		= &clkops_null,
+ + };
+ + 
+ + static struct clk tclkin_ck = {
+ + 	.name		= "tclkin_ck",
+ + 	.rate		= 12000000,
+ + 	.ops		= &clkops_null,
+ + };
+ + 
+ + static const struct clksel_rate div_1_0_rates[] = {
+ + 	{ .div = 1, .val = 0, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 0 },
+ + };
+ + 
+ + static const struct clksel_rate div_1_1_rates[] = {
+ + 	{ .div = 1, .val = 1, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 0 },
+ + };
+ + 
+ + static const struct clksel_rate div_1_2_rates[] = {
+ + 	{ .div = 1, .val = 2, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 0 },
+ + };
+ + 
+ + static const struct clksel_rate div_1_3_rates[] = {
+ + 	{ .div = 1, .val = 3, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 0 },
+ + };
+ + 
+ + static const struct clksel_rate div_1_4_rates[] = {
+ + 	{ .div = 1, .val = 4, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 0 },
+ + };
+ + 
+ + static const struct clksel_rate div31_1to31_rates[] = {
+ + 	{ .div = 1, .val = 1, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 2, .val = 2, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 3, .val = 3, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 4, .val = 4, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 5, .val = 5, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 6, .val = 6, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 7, .val = 7, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 8, .val = 8, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 9, .val = 9, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 10, .val = 10, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 11, .val = 11, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 12, .val = 12, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 13, .val = 13, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 14, .val = 14, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 15, .val = 15, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 16, .val = 16, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 17, .val = 17, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 18, .val = 18, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 19, .val = 19, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 20, .val = 20, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 21, .val = 21, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 22, .val = 22, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 23, .val = 23, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 24, .val = 24, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 25, .val = 25, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 26, .val = 26, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 27, .val = 27, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 28, .val = 28, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 29, .val = 29, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 30, .val = 30, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 31, .val = 31, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 0 },
+ + };
+ + 
+ + /* Oscillator clock */
+ + /* 19.2, 24, 25 or 26 MHz */
+ + static const struct clksel sys_clkin_sel[] = {
+ + 	{ .parent = &virt_19_2m_ck, .rates = div_1_0_rates },
+ + 	{ .parent = &virt_24m_ck, .rates = div_1_1_rates },
+ + 	{ .parent = &virt_25m_ck, .rates = div_1_2_rates },
+ + 	{ .parent = &virt_26m_ck, .rates = div_1_3_rates },
+ + 	{ .parent = NULL },
+ + };
+ + 
+ + /* sys_clk_in */
+ + static struct clk sys_clkin_ck = {
+ + 	.name		= "sys_clkin_ck",
+ + 	.parent		= &virt_24m_ck,
+ + 	.init		= &omap2_init_clksel_parent,
+ + 	.clksel_reg	= AM33XX_CTRL_REGADDR(0x40),	/* CONTROL_STATUS */
+ + 	.clksel_mask	= (0x3 << 22),
+ + 	.clksel		= sys_clkin_sel,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &omap2_clksel_recalc,
+ + };
+ + 
+ + /* DPLL_CORE */
+ + static struct dpll_data dpll_core_dd = {
+ + 	.mult_div1_reg	= AM33XX_CM_CLKSEL_DPLL_CORE,
+ + 	.clk_bypass	= &sys_clkin_ck,
+ + 	.clk_ref	= &sys_clkin_ck,
+ + 	.control_reg	= AM33XX_CM_CLKMODE_DPLL_CORE,
+ + 	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ + 	.idlest_reg	= AM33XX_CM_IDLEST_DPLL_CORE,
+ + 	.mult_mask	= AM33XX_DPLL_MULT_MASK,
+ + 	.div1_mask	= AM33XX_DPLL_DIV_MASK,
+ + 	.enable_mask	= AM33XX_DPLL_EN_MASK,
+ + 	.idlest_mask	= AM33XX_ST_DPLL_CLK_MASK,
+ + 	.max_multiplier	= AM33XX_MAX_DPLL_MULT,
+ + 	.max_divider	= AM33XX_MAX_DPLL_DIV,
+ + 	.min_divider	= 1,
+ + };
+ + 
+ + /* CLKDCOLDO output */
+ + static struct clk dpll_core_ck = {
+ + 	.name		= "dpll_core_ck",
+ + 	.parent		= &sys_clkin_ck,
+ + 	.dpll_data	= &dpll_core_dd,
+ + 	.init		= &omap2_init_dpll_parent,
+ + 	.ops		= &clkops_omap3_core_dpll_ops,
+ + 	.recalc		= &omap3_dpll_recalc,
+ + };
+ + 
+ + static struct clk dpll_core_x2_ck = {
+ + 	.name		= "dpll_core_x2_ck",
+ + 	.parent		= &dpll_core_ck,
+ + 	.flags		= CLOCK_CLKOUTX2,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &omap3_clkoutx2_recalc,
+ + };
+ + 
+ + 
+ + static const struct clksel dpll_core_m4_div[] = {
+ + 	{ .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
+ + 	{ .parent = NULL },
+ + };
+ + 
+ + static struct clk dpll_core_m4_ck = {
+ + 	.name		= "dpll_core_m4_ck",
+ + 	.parent		= &dpll_core_x2_ck,
+ + 	.clksel		= dpll_core_m4_div,
+ + 	.clksel_reg	= AM33XX_CM_DIV_M4_DPLL_CORE,
+ + 	.clksel_mask	= AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &omap2_clksel_recalc,
+ + 	.round_rate	= &omap2_clksel_round_rate,
+ + 	.set_rate	= &omap2_clksel_set_rate,
+ + };
+ + 
+ + static const struct clksel dpll_core_m5_div[] = {
+ + 	{ .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
+ + 	{ .parent = NULL },
+ + };
+ + 
+ + static struct clk dpll_core_m5_ck = {
+ + 	.name		= "dpll_core_m5_ck",
+ + 	.parent		= &dpll_core_x2_ck,
+ + 	.clksel		= dpll_core_m5_div,
+ + 	.clksel_reg	= AM33XX_CM_DIV_M5_DPLL_CORE,
+ + 	.clksel_mask	= AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &omap2_clksel_recalc,
+ + 	.round_rate	= &omap2_clksel_round_rate,
+ + 	.set_rate	= &omap2_clksel_set_rate,
+ + };
+ + 
+ + static const struct clksel dpll_core_m6_div[] = {
+ + 	{ .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
+ + 	{ .parent = NULL },
+ + };
+ + 
+ + static struct clk dpll_core_m6_ck = {
+ + 	.name		= "dpll_core_m6_ck",
+ + 	.parent		= &dpll_core_x2_ck,
+ + 	.clksel		= dpll_core_m6_div,
+ + 	.clksel_reg	= AM33XX_CM_DIV_M6_DPLL_CORE,
+ + 	.clksel_mask	= AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &omap2_clksel_recalc,
+ + 	.round_rate	= &omap2_clksel_round_rate,
+ + 	.set_rate	= &omap2_clksel_set_rate,
+ + };
+ + 
+ + static struct clk sysclk1_ck = {
+ + 	.name		= "sysclk1_ck",
+ + 	.parent		= &dpll_core_m4_ck,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk sysclk2_ck = {
+ + 	.name		= "sysclk2_ck",
+ + 	.parent		= &dpll_core_m5_ck,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk core_clk_out = {
+ + 	.name		= "core_clk_out",
+ + 	.parent		= &dpll_core_m4_ck,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + /* DPLL_MPU */
+ + static struct dpll_data dpll_mpu_dd = {
+ + 	.mult_div1_reg	= AM33XX_CM_CLKSEL_DPLL_MPU,
+ + 	.clk_bypass	= &sys_clkin_ck,
+ + 	.clk_ref	= &sys_clkin_ck,
+ + 	.control_reg	= AM33XX_CM_CLKMODE_DPLL_MPU,
+ + 	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ + 	.idlest_reg	= AM33XX_CM_IDLEST_DPLL_MPU,
+ + 	.mult_mask	= AM33XX_DPLL_MULT_MASK,
+ + 	.div1_mask	= AM33XX_DPLL_DIV_MASK,
+ + 	.enable_mask	= AM33XX_DPLL_EN_MASK,
+ + 	.idlest_mask	= AM33XX_ST_DPLL_CLK_MASK,
+ + 	.max_multiplier	= AM33XX_MAX_DPLL_MULT,
+ + 	.max_divider	= AM33XX_MAX_DPLL_DIV,
+ + 	.min_divider	= 1,
+ + };
+ + 
+ + /* CLKOUT: fdpll/M2 */
+ + static struct clk dpll_mpu_ck = {
+ + 	.name		= "dpll_mpu_ck",
+ + 	.parent		= &sys_clkin_ck,
+ + 	.dpll_data	= &dpll_mpu_dd,
+ + 	.init		= &omap2_init_dpll_parent,
+ + 	.ops		= &clkops_omap3_noncore_dpll_ops,
+ + 	.recalc		= &omap3_dpll_recalc,
+ + 	.round_rate	= &omap2_dpll_round_rate,
+ + 	.set_rate	= &omap3_noncore_dpll_set_rate,
+ + };
+ + 
+ + /*
+ +  * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
+ +  * and ALT_CLK1/2)
+ +  */
+ + static const struct clksel dpll_mpu_m2_div[] = {
+ + 	{ .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
+ + 	{ .parent = NULL },
+ + };
+ + 
+ + static struct clk dpll_mpu_m2_ck = {
+ + 	.name		= "dpll_mpu_m2_ck",
+ + 	.parent		= &dpll_mpu_ck,
+ + 	.clksel		= dpll_mpu_m2_div,
+ + 	.clksel_reg	= AM33XX_CM_DIV_M2_DPLL_MPU,
+ + 	.clksel_mask	= AM33XX_DPLL_CLKOUT_DIV_MASK,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &omap2_clksel_recalc,
+ + 	.round_rate	= &omap2_clksel_round_rate,
+ + 	.set_rate	= &omap2_clksel_set_rate,
+ + };
+ + 
+ + static struct clk mpu_fck = {
+ + 	.name		= "mpu_fck",
+ + 	.clkdm_name	= "mpu_clkdm",
+ + 	.parent		= &dpll_mpu_m2_ck,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.enable_reg	= AM33XX_CM_MPU_MPU_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.recalc		= &followparent_recalc,
+ + 	.flags		= ENABLE_ON_INIT,
+ + };
+ + 
+ + /* DPLL_DDR */
+ + static struct dpll_data dpll_ddr_dd = {
+ + 	.mult_div1_reg	= AM33XX_CM_CLKSEL_DPLL_DDR,
+ + 	.clk_bypass	= &sys_clkin_ck,
+ + 	.clk_ref	= &sys_clkin_ck,
+ + 	.control_reg	= AM33XX_CM_CLKMODE_DPLL_DDR,
+ + 	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ + 	.idlest_reg	= AM33XX_CM_IDLEST_DPLL_DDR,
+ + 	.mult_mask	= AM33XX_DPLL_MULT_MASK,
+ + 	.div1_mask	= AM33XX_DPLL_DIV_MASK,
+ + 	.enable_mask	= AM33XX_DPLL_EN_MASK,
+ + 	.idlest_mask	= AM33XX_ST_DPLL_CLK_MASK,
+ + 	.max_multiplier	= AM33XX_MAX_DPLL_MULT,
+ + 	.max_divider	= AM33XX_MAX_DPLL_DIV,
+ + 	.min_divider	= 1,
+ + };
+ + 
+ + /* CLKOUT: fdpll/M2 */
+ + static struct clk dpll_ddr_ck = {
+ + 	.name		= "dpll_ddr_ck",
+ + 	.parent		= &sys_clkin_ck,
+ + 	.dpll_data	= &dpll_ddr_dd,
+ + 	.init		= &omap2_init_dpll_parent,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &omap3_dpll_recalc,
+ + };
+ + 
+ + /*
+ +  * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
+ +  * and ALT_CLK1/2)
+ +  */
+ + static const struct clksel dpll_ddr_m2_div[] = {
+ + 	{ .parent = &dpll_ddr_ck, .rates = div31_1to31_rates },
+ + 	{ .parent = NULL },
+ + };
+ + 
+ + static struct clk dpll_ddr_m2_ck = {
+ + 	.name		= "dpll_ddr_m2_ck",
+ + 	.parent		= &dpll_ddr_ck,
+ + 	.clksel		= dpll_ddr_m2_div,
+ + 	.clksel_reg	= AM33XX_CM_DIV_M2_DPLL_DDR,
+ + 	.clksel_mask	= AM33XX_DPLL_CLKOUT_DIV_MASK,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &omap2_clksel_recalc,
+ + 	.round_rate	= &omap2_clksel_round_rate,
+ + 	.set_rate	= &omap2_clksel_set_rate,
+ + };
+ + 
+ + static struct clk ddr_pll_clk = {
+ + 	.name		= "ddr_pll_clk",
+ + 	.parent		= &dpll_ddr_m2_ck,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk emif_fck = {
+ + 	.name		= "emif_fck",
+ + 	.clkdm_name	= "l3_clkdm",
+ + 	.parent		= &ddr_pll_clk,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.enable_reg	= AM33XX_CM_PER_EMIF_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.fixed_div	= 2,
+ + 	.recalc		= &omap_fixed_divisor_recalc,
+ + 	.flags		= ENABLE_ON_INIT,
+ + };
+ + 
+ + /* DPLL_DISP */
+ + static struct dpll_data dpll_disp_dd = {
+ + 	.mult_div1_reg	= AM33XX_CM_CLKSEL_DPLL_DISP,
+ + 	.clk_bypass	= &sys_clkin_ck,
+ + 	.clk_ref	= &sys_clkin_ck,
+ + 	.control_reg	= AM33XX_CM_CLKMODE_DPLL_DISP,
+ + 	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ + 	.idlest_reg	= AM33XX_CM_IDLEST_DPLL_DISP,
+ + 	.mult_mask	= AM33XX_DPLL_MULT_MASK,
+ + 	.div1_mask	= AM33XX_DPLL_DIV_MASK,
+ + 	.enable_mask	= AM33XX_DPLL_EN_MASK,
+ + 	.idlest_mask	= AM33XX_ST_DPLL_CLK_MASK,
+ + 	.max_multiplier	= AM33XX_MAX_DPLL_MULT,
+ + 	.max_divider	= AM33XX_MAX_DPLL_DIV,
+ + 	.min_divider	= 1,
+ + };
+ + 
+ + /* CLKOUT: fdpll/M2 */
+ + static struct clk dpll_disp_ck = {
+ + 	.name		= "dpll_disp_ck",
+ + 	.parent		= &sys_clkin_ck,
+ + 	.dpll_data	= &dpll_disp_dd,
+ + 	.init		= &omap2_init_dpll_parent,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &omap3_dpll_recalc,
+ + 	.round_rate	= &omap2_dpll_round_rate,
+ + 	.set_rate	= &omap3_noncore_dpll_set_rate,
+ + };
+ + 
+ + /*
+ +  * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
+ +  * and ALT_CLK1/2)
+ +  */
+ + static const struct clksel dpll_disp_m2_div[] = {
+ + 	{ .parent = &dpll_disp_ck, .rates = div31_1to31_rates },
+ + 	{ .parent = NULL },
+ + };
+ + 
+ + static struct clk dpll_disp_m2_ck = {
+ + 	.name		= "dpll_disp_m2_ck",
+ + 	.parent		= &dpll_disp_ck,
+ + 	.clksel		= dpll_disp_m2_div,
+ + 	.clksel_reg	= AM33XX_CM_DIV_M2_DPLL_DISP,
+ + 	.clksel_mask	= AM33XX_DPLL_CLKOUT_DIV_MASK,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &omap2_clksel_recalc,
+ + 	.round_rate	= &omap2_clksel_round_rate,
+ + 	.set_rate	= &omap2_clksel_set_rate,
+ + };
+ + 
+ + static struct clk disp_pll_clk = {
+ + 	.name		= "disp_pll_clk",
+ + 	.parent		= &dpll_disp_m2_ck,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + /* DPLL_PER */
+ + static struct dpll_data dpll_per_dd = {
+ + 	.mult_div1_reg	= AM33XX_CM_CLKSEL_DPLL_PERIPH,
+ + 	.clk_bypass	= &sys_clkin_ck,
+ + 	.clk_ref	= &sys_clkin_ck,
+ + 	.control_reg	= AM33XX_CM_CLKMODE_DPLL_PER,
+ + 	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ + 	.idlest_reg	= AM33XX_CM_IDLEST_DPLL_PER,
+ + 	.mult_mask	= AM33XX_DPLL_MULT_PERIPH_MASK,
+ + 	.div1_mask	= AM33XX_DPLL_PER_DIV_MASK,
+ + 	.enable_mask	= AM33XX_DPLL_EN_MASK,
+ + 	.idlest_mask	= AM33XX_ST_DPLL_CLK_MASK,
+ + 	.max_multiplier	= AM33XX_MAX_DPLL_MULT,
+ + 	.max_divider	= AM33XX_MAX_DPLL_DIV,
+ + 	.min_divider	= 1,
+ + 	.flags		= DPLL_J_TYPE,
+ + };
+ + 
+ + /* CLKDCOLDO */
+ + static struct clk dpll_per_ck = {
+ + 	.name		= "dpll_per_ck",
+ + 	.parent		= &sys_clkin_ck,
+ + 	.dpll_data	= &dpll_per_dd,
+ + 	.init		= &omap2_init_dpll_parent,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &omap3_dpll_recalc,
+ + 	.round_rate	= &omap2_dpll_round_rate,
+ + 	.set_rate	= &omap3_noncore_dpll_set_rate,
+ + };
+ + 
+ + /* CLKOUT: fdpll/M2 */
+ + static const struct clksel dpll_per_m2_div[] = {
+ + 	{ .parent = &dpll_per_ck, .rates = div31_1to31_rates },
+ + 	{ .parent = NULL },
+ + };
+ + 
+ + static struct clk dpll_per_m2_ck = {
+ + 	.name		= "dpll_per_m2_ck",
+ + 	.parent		= &dpll_per_ck,
+ + 	.clksel		= dpll_per_m2_div,
+ + 	.clksel_reg	= AM33XX_CM_DIV_M2_DPLL_PER,
+ + 	.clksel_mask	= AM33XX_DPLL_CLKOUT_DIV_MASK,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &omap2_clksel_recalc,
+ + 	.round_rate	= &omap2_clksel_round_rate,
+ + 	.set_rate	= &omap2_clksel_set_rate,
+ + };
+ + 
+ + static struct clk per_192mhz_clk = {
+ + 	.name		= "per_192mhz_clk",
+ + 	.parent		= &dpll_per_m2_ck,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk usb_pll_clk = {
+ + 	.name		= "usb_pll_clk",
+ + 	.parent		= &dpll_per_ck,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk core_100mhz_ck = {
+ + 	.name		= "core_100mhz_ck",
+ + 	.parent		= &sysclk1_ck,
+ + 	.ops		= &clkops_null,
+ + 	.fixed_div	= 2,
+ + 	.recalc		= &omap_fixed_divisor_recalc,
+ + };
+ + 
+ + static struct clk l3_aon_gclk = {
+ + 	.name		= "l3_aon_gclk",
+ + 	.parent		= &sysclk1_ck,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk l4_wkup_aon_gclk = {
+ + 	.name		= "l4_wkup_aon_gclk",
+ + 	.clkdm_name	= "l4_wkup_aon_clkdm",
+ + 	.parent		= &sysclk1_ck,
+ + 	.enable_reg	= AM33XX_CM_L4_WKUP_AON_CLKSTCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_null,
+ + 	.fixed_div	= 2,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk l3_gclk = {
+ + 	.name		= "l3_gclk",
+ + 	.parent		= &sysclk1_ck,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk l3_ick = {
+ + 	.name		= "l3_ick",
+ + 	.clkdm_name	= "l3_clkdm",
+ + 	.parent		= &l3_gclk,
+ + 	.enable_reg	= AM33XX_CM_PER_L3_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.flags		= ENABLE_ON_INIT,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk l3_instr_ick = {
+ + 	.name		= "l3_instr_ick",
+ + 	.clkdm_name	= "l3_clkdm",
+ + 	.parent		= &l3_gclk,
+ + 	.enable_reg	= AM33XX_CM_PER_L3_INSTR_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.flags		= ENABLE_ON_INIT,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk l4_wkup_gclk = {
+ + 	.name		= "l4_wkup_gclk",
+ + 	.parent		= &sysclk1_ck,
+ + 	.ops		= &clkops_null,
+ + 	.fixed_div	= 2,
+ + 	.recalc		= &omap_fixed_divisor_recalc,
+ + };
+ + 
+ + static struct clk l4hs_gclk = {
+ + 	.name		= "l4hs_gclk",
+ + 	.parent		= &sysclk1_ck,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk gfx_l3_gclk = {
+ + 	.name		= "gfx_l3_gclk",
+ + 	.clkdm_name	= "gfx_l3_clkdm",
+ + 	.parent		= &sysclk1_ck,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk debug_clka_gclk = {
+ + 	.name		= "debug_clka_gclk",
+ + 	.parent		= &sysclk1_ck,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk l4_rtc_gclk = {
+ + 	.name		= "l4_rtc_gclk",
+ + 	.parent		= &sysclk1_ck,
+ + 	.ops		= &clkops_null,
+ + 	.fixed_div	= 2,
+ + 	.recalc		= &omap_fixed_divisor_recalc,
+ + };
+ + 
+ + static struct clk rtc_ick = {
+ + 	.name		= "rtc_ick",
+ + 	.parent		= &l4_rtc_gclk,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk l3s_gclk = {
+ + 	.name		= "l3s_gclk",
+ + 	.parent		= &core_100mhz_ck,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk l4fw_gclk = {
+ + 	.name		= "l4fw_gclk",
+ + 	.parent		= &core_100mhz_ck,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk l4ls_gclk = {
+ + 	.name		= "l4ls_gclk",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &core_100mhz_ck,
+ + 	.enable_reg	= AM33XX_CM_PER_L4LS_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk clk_24mhz = {
+ + 	.name		= "clk_24mhz",
+ + 	.parent		= &per_192mhz_clk,
+ + 	.fixed_div	= 8,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &omap_fixed_divisor_recalc,
+ + };
+ + 
+ + static struct clk l4_cefuse_gclk = {
+ + 	.name		= "l4_cefsue_gclk",
+ + 	.parent		= &core_100mhz_ck,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk cefuse_iclk = {
+ + 	.name		= "cefuse_iclk",
+ + 	.clkdm_name	= "l4_cefuse_clkdm",
+ + 	.parent		= &l4_cefuse_gclk,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk cefuse_fck = {
+ + 	.name		= "cefuse_fck",
+ + 	.clkdm_name	= "l4_cefuse_clkdm",
+ + 	.parent		= &sys_clkin_ck,
+ + 	.enable_reg	= AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk sysclk_div_ck = {
+ + 	.name		= "sysclk_div_ck",
+ + 	.parent		= &dpll_core_m4_ck,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk adc_tsc_fck = {
+ + 	.name		= "adc_tsc_fck",
+ + 	.clkdm_name	= "l4_wkup_clkdm",
+ + 	.parent		= &sys_clkin_ck,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk adc_tsc_ick = {
+ + 	.name		= "adc_tsc_ick",
+ + 	.clkdm_name	= "l4_wkup_clkdm",
+ + 	.parent		= &l4_wkup_gclk,
+ + 	.enable_reg	= AM33XX_CM_WKUP_ADC_TSC_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk aes0_fck = {
+ + 	.name		= "aes0_fck",
+ + 	.clkdm_name	= "l3_clkdm",
+ + 	.parent		= &l3_gclk,
+ + 	.enable_reg	= AM33XX_CM_PER_AES0_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + /*
+ +  * clkdiv32 is generated from fixed division of 732.4219
+ +  */
+ + static struct clk clkdiv32k_ick = {
+ + 	.name		= "clkdiv32k_ick",
+ + 	.clkdm_name	= "clk_24mhz_clkdm",
+ + 	.rate		= 32768,
+ + 	.parent		= &clk_24mhz,
+ + 	.enable_reg	= AM33XX_CM_PER_CLKDIV32K_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + };
+ + 
+ + static struct clk clk_32khz_ck = {
+ + 	.name		= "clk_32khz_ck",
+ + 	.clkdm_name	= "clk_24mhz_clkdm",
+ + 	.parent		= &clkdiv32k_ick,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk control_fck = {
+ + 	.name		= "control_fck",
+ + 	.clkdm_name	= "l4_wkup_clkdm",
+ + 	.parent		= &l4_wkup_gclk,
+ + 	.enable_reg	= AM33XX_CM_WKUP_CONTROL_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk dcan0_ick = {
+ + 	.name		= "dcan0_ick",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &l4ls_gclk,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk dcan0_fck = {
+ + 	.name		= "dcan0_fck",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &sys_clkin_ck,
+ + 	.enable_reg	= AM33XX_CM_PER_DCAN0_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk dcan1_ick = {
+ + 	.name		= "dcan1_ick",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &l4ls_gclk,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk dcan1_fck = {
+ + 	.name		= "dcan1_fck",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &sys_clkin_ck,
+ + 	.enable_reg	= AM33XX_CM_PER_DCAN1_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk debugss_ick = {
+ + 	.name		= "debugss_ick",
+ + 	.clkdm_name	= "l3_aon_clkdm",
+ + 	.parent		= &l3_aon_gclk,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.enable_reg	= AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk elm_fck = {
+ + 	.name		= "elm_fck",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &l4ls_gclk,
+ + 	.enable_reg	= AM33XX_CM_PER_ELM_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk emif_fw_fck = {
+ + 	.name		= "emif_fw_fck",
+ + 	.clkdm_name	= "l4fw_clkdm",
+ + 	.parent		= &l4fw_gclk,
+ + 	.enable_reg	= AM33XX_CM_PER_EMIF_FW_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk epwmss0_fck = {
+ + 	.name		= "epwmss0_fck",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &l4ls_gclk,
+ + 	.enable_reg	= AM33XX_CM_PER_EPWMSS0_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk epwmss1_fck = {
+ + 	.name		= "epwmss1_fck",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &l4ls_gclk,
+ + 	.enable_reg	= AM33XX_CM_PER_EPWMSS1_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk epwmss2_fck = {
+ + 	.name		= "epwmss2_fck",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &l4ls_gclk,
+ + 	.enable_reg	= AM33XX_CM_PER_EPWMSS2_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk gpmc_fck = {
+ + 	.name		= "gpmc_fck",
+ + 	.clkdm_name	= "l3s_clkdm",
+ + 	.parent		= &l3s_gclk,
+ + 	.enable_reg	= AM33XX_CM_PER_GPMC_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk i2c1_ick = {
+ + 	.name		= "i2c1_ick",
+ + 	.clkdm_name	= "l4_wkup_clkdm",
+ + 	.parent		= &l4_wkup_gclk,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk i2c1_fck = {
+ + 	.name		= "i2c1_fck",
+ + 	.clkdm_name	= "l4_wkup_clkdm",
+ + 	.parent		= &per_192mhz_clk,
+ + 	.enable_reg	= AM33XX_CM_WKUP_I2C0_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.fixed_div	= 4,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &omap_fixed_divisor_recalc,
+ + };
+ + 
+ + static struct clk i2c2_ick = {
+ + 	.name		= "i2c2_ick",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &l4ls_gclk,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk i2c2_fck = {
+ + 	.name		= "i2c2_fck",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &per_192mhz_clk,
+ + 	.enable_reg	= AM33XX_CM_PER_I2C1_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.fixed_div	= 4,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &omap_fixed_divisor_recalc,
+ + };
+ + 
+ + static struct clk i2c3_ick = {
+ + 	.name		= "i2c3_ick",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &l4ls_gclk,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk i2c3_fck = {
+ + 	.name		= "i2c3_fck",
+ + 	.parent		= &per_192mhz_clk,
+ + 	.enable_reg	= AM33XX_CM_PER_I2C2_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.fixed_div	= 4,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &omap_fixed_divisor_recalc,
+ + };
+ + 
+ + static struct clk ieee5000_fck = {
+ + 	.name		= "ieee5000_fck",
+ + 	.clkdm_name	= "l3s_clkdm",
+ + 	.parent		= &l3s_gclk,
+ + 	.enable_reg	= AM33XX_CM_PER_IEEE5000_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk l4hs_ick = {
+ + 	.name		= "l4hs_ick",
+ + 	.clkdm_name	= "l4hs_clkdm",
+ + 	.parent		= &l4hs_gclk,
+ + 	.enable_reg	= AM33XX_CM_PER_L4HS_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.flags		= ENABLE_ON_INIT,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk l4wkup_ick = {
+ + 	.name		= "l4wkup_ick",
+ + 	.clkdm_name	= "l4_wkup_aon_clkdm",
+ + 	.parent		= &l4_wkup_aon_gclk,
+ + 	.enable_reg	= AM33XX_CM_L4_WKUP_AON_CLKSTCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.flags		= ENABLE_ON_INIT,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk l4fw_ick = {
+ + 	.name		= "l4fw_ick",
+ + 	.clkdm_name	= "l4fw_clkdm",
+ + 	.parent		= &core_100mhz_ck,
+ + 	.enable_reg	= AM33XX_CM_PER_L4FW_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.flags		= ENABLE_ON_INIT,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk l4ls_ick = {
+ + 	.name		= "l4ls_ick",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &l4ls_gclk,
+ + 	.enable_reg	= AM33XX_CM_PER_L4LS_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.flags		= ENABLE_ON_INIT,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk mailbox0_fck = {
+ + 	.name		= "mailbox0_fck",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &l4ls_gclk,
+ + 	.enable_reg	= AM33XX_CM_PER_MAILBOX0_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk mcasp0_ick = {
+ + 	.name		= "mcasp0_ick",
+ + 	.parent		= &l3s_gclk,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk mcasp0_fck = {
+ + 	.name		= "mcasp0_fck",
+ + 	.clkdm_name	= "l3s_clkdm",
+ + 	.parent		= &sys_clkin_ck,
+ + 	.enable_reg	= AM33XX_CM_PER_MCASP0_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk mcasp1_ick = {
+ + 	.name		= "mcasp1_ick",
+ + 	.parent		= &l3s_gclk,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk mcasp1_fck = {
+ + 	.name		= "mcasp1_fck",
+ + 	.clkdm_name	= "l3s_clkdm",
+ + 	.parent		= &sys_clkin_ck,
+ + 	.enable_reg	= AM33XX_CM_PER_MCASP1_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk mlb_fck = {
+ + 	.name		= "mlb_fck",
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.enable_reg	= AM33XX_CM_PER_MLB_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.clkdm_name	= "l3_clkdm",
+ + 	.parent		= &sysclk_div_ck,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk mmu_fck = {
+ + 	.name		= "mmu_fck",
+ + 	.clkdm_name	= "gfx_l3_clkdm",
+ + 	.parent		= &gfx_l3_gclk,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.enable_reg	= AM33XX_CM_GFX_MMUDATA_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk ocmcram_ick = {
+ + 	.name		= "ocmcram_ick",
+ + 	.clkdm_name	= "l3_clkdm",
+ + 	.parent		= &l3_gclk,
+ + 	.enable_reg	= AM33XX_CM_PER_OCMCRAM_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk ocpwp_fck = {
+ + 	.name		= "ocpwp_fck",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &l4ls_gclk,
+ + 	.enable_reg	= AM33XX_CM_PER_OCPWP_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk pka_fck = {
+ + 	.name		= "pka_fck",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &l4ls_gclk,
+ + 	.enable_reg	= AM33XX_CM_PER_PKA_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk rng_fck = {
+ + 	.name		= "rng_fck",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &l4ls_gclk,
+ + 	.enable_reg	= AM33XX_CM_PER_RNG_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk rtc_fck = {
+ + 	.name		= "rtc_fck",
+ + 	.clkdm_name	= "l4_rtc_clkdm",
+ + 	.parent		= &clk_32768_ck,
+ + 	.enable_reg	= AM33XX_CM_RTC_RTC_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk sha0_fck = {
+ + 	.name		= "sha0_fck",
+ + 	.clkdm_name	= "l3_clkdm",
+ + 	.parent		= &l3_gclk,
+ + 	.enable_reg	= AM33XX_CM_PER_SHA0_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk smartreflex0_ick = {
+ + 	.name		= "smartreflex0_ick",
+ + 	.parent		= &l4_wkup_gclk,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk smartreflex0_fck = {
+ + 	.name		= "smartreflex0_fck",
+ + 	.clkdm_name	= "l4_wkup_clkdm",
+ + 	.parent		= &sys_clkin_ck,
+ + 	.enable_reg	= AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk smartreflex1_ick = {
+ + 	.name		= "smartreflex1_ick",
+ + 	.parent		= &l4_wkup_gclk,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk smartreflex1_fck = {
+ + 	.name		= "smartreflex1_fck",
+ + 	.clkdm_name	= "l4_wkup_clkdm",
+ + 	.parent		= &sys_clkin_ck,
+ + 	.enable_reg	= AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk spi0_ick = {
+ + 	.name		= "spi0_ick",
+ + 	.parent		= &l4ls_gclk,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk spi0_fck = {
+ + 	.name		= "spi0_fck",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &per_192mhz_clk,
+ + 	.enable_reg	= AM33XX_CM_PER_SPI0_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.fixed_div	= 4,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &omap_fixed_divisor_recalc,
+ + };
+ + 
+ + static struct clk spi1_ick = {
+ + 	.name		= "spi1_ick",
+ + 	.parent		= &l4ls_gclk,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk spi1_fck = {
+ + 	.name		= "spi1_fck",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &per_192mhz_clk,
+ + 	.enable_reg	= AM33XX_CM_PER_SPI1_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.fixed_div	= 4,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &omap_fixed_divisor_recalc,
+ + };
+ + 
+ + static struct clk spinlock_fck = {
+ + 	.name		= "spinlock_fck",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &l4ls_gclk,
+ + 	.enable_reg	= AM33XX_CM_PER_SPINLOCK_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk clk_32khz_timer = {
+ + 	.name		= "clk_32khz_timer",
+ + 	.parent		= &clk_32khz_ck,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + /* Timers */
+ + 
+ + /* Secure Timer: Used only to disable the clocks and for completeness */
+ + static const struct clksel timer0_clkmux_sel[] = {
+ + 	{ .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
+ + 	{ .parent = &clk_32khz_ck, .rates = div_1_1_rates },
+ + 	{ .parent = &sys_clkin_ck, .rates = div_1_2_rates },
+ + 	{ .parent = &tclkin_ck, .rates = div_1_3_rates },
+ + 	{ .parent = NULL },
+ + };
+ + 
+ + static struct clk timer0_ick = {
+ + 	.name		= "timer0_ick",
+ + 	.parent		= &l4_wkup_gclk,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk timer0_fck = {
+ + 	.name		= "timer0_fck",
+ + 	.clkdm_name	= "l4_wkup_clkdm",
+ + 	.parent		= &clk_rc32k_ck,
+ + 	.clksel		= timer0_clkmux_sel,
+ + 	.enable_reg	= AM33XX_CM_WKUP_TIMER0_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.clksel_reg	= AM33XX_CTRL_REGADDR(0x01BC),
+ + 	.clksel_mask	= (0x3 << 4),
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static const struct clksel timer1_clkmux_sel[] = {
+ + 	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
+ + 	{ .parent = &clk_32khz_ck, .rates = div_1_1_rates },
+ + 	{ .parent = &tclkin_ck, .rates = div_1_2_rates },
+ + 	{ .parent = &clk_rc32k_ck, .rates = div_1_3_rates },
+ + 	{ .parent = &clk_32768_ck, .rates = div_1_4_rates },
+ + 	{ .parent = NULL },
+ + };
+ + 
+ + static struct clk timer1_ick = {
+ + 	.name		= "timer1_ick",
+ + 	.parent		= &l4_wkup_gclk,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk timer1_fck = {
+ + 	.name		= "timer1_fck",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &sys_clkin_ck,
+ + 	.init		= &omap2_init_clksel_parent,
+ + 	.clksel		= timer1_clkmux_sel,
+ + 	.enable_reg	= AM33XX_CM_WKUP_TIMER1_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.clksel_reg	= AM33XX_CLKSEL_TIMER1MS_CLK,
+ + 	.clksel_mask	= AM33XX_CLKSEL_0_2_MASK,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &omap2_clksel_recalc,
+ + };
+ + 
+ + static const struct clksel timer2_to_7_clk_sel[] = {
+ + 	{ .parent = &tclkin_ck, .rates = div_1_0_rates },
+ + 	{ .parent = &sys_clkin_ck, .rates = div_1_1_rates },
+ + 	{ .parent = &clk_32khz_timer, .rates = div_1_2_rates },
+ + 	{ .parent = NULL },
+ + };
+ + 
+ + static struct clk timer2_ick = {
+ + 	.name		= "timer2_ick",
+ + 	.parent		= &l4ls_gclk,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk timer2_fck = {
+ + 	.name		= "timer2_fck",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &sys_clkin_ck,
+ + 	.init		= &omap2_init_clksel_parent,
+ + 	.clksel		= timer2_to_7_clk_sel,
+ + 	.enable_reg	= AM33XX_CM_PER_TIMER2_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.clksel_reg	= AM33XX_CLKSEL_TIMER2_CLK,
+ + 	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &omap2_clksel_recalc,
+ + };
+ + 
+ + static struct clk timer3_ick = {
+ + 	.name		= "timer3_ick",
+ + 	.parent		= &l4ls_gclk,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk timer3_fck = {
+ + 	.name		= "timer3_fck",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &sys_clkin_ck,
+ + 	.init		= &am33xx_init_timer_parent,
+ + 	.clksel		= timer2_to_7_clk_sel,
+ + 	.enable_reg	= AM33XX_CM_PER_TIMER3_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.clksel_reg	= AM33XX_CLKSEL_TIMER3_CLK,
+ + 	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &omap2_clksel_recalc,
+ + };
+ + 
+ + static struct clk timer4_ick = {
+ + 	.name		= "timer4_ick",
+ + 	.parent		= &l4ls_gclk,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk timer4_fck = {
+ + 	.name		= "timer4_fck",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &sys_clkin_ck,
+ + 	.init		= &omap2_init_clksel_parent,
+ + 	.clksel		= timer2_to_7_clk_sel,
+ + 	.enable_reg	= AM33XX_CM_PER_TIMER4_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.clksel_reg	= AM33XX_CLKSEL_TIMER4_CLK,
+ + 	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &omap2_clksel_recalc,
+ + };
+ + 
+ + static struct clk timer5_ick = {
+ + 	.name		= "timer5_ick",
+ + 	.parent		= &l4ls_gclk,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk timer5_fck = {
+ + 	.name		= "timer5_fck",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &sys_clkin_ck,
+ + 	.init		= &omap2_init_clksel_parent,
+ + 	.clksel		= timer2_to_7_clk_sel,
+ + 	.enable_reg	= AM33XX_CM_PER_TIMER5_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.clksel_reg	= AM33XX_CLKSEL_TIMER5_CLK,
+ + 	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &omap2_clksel_recalc,
+ + };
+ + 
+ + static struct clk timer6_ick = {
+ + 	.name		= "timer6_ick",
+ + 	.parent		= &l4ls_gclk,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk timer6_fck = {
+ + 	.name		= "timer6_fck",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &sys_clkin_ck,
+ + 	.init		= &am33xx_init_timer_parent,
+ + 	.clksel		= timer2_to_7_clk_sel,
+ + 	.enable_reg	= AM33XX_CM_PER_TIMER6_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.clksel_reg	= AM33XX_CLKSEL_TIMER6_CLK,
+ + 	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &omap2_clksel_recalc,
+ + };
+ + 
+ + static struct clk timer7_ick = {
+ + 	.name		= "timer7_ick",
+ + 	.parent		= &l4ls_gclk,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk timer7_fck = {
+ + 	.name		= "timer7_fck",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &sys_clkin_ck,
+ + 	.init		= &omap2_init_clksel_parent,
+ + 	.clksel		= timer2_to_7_clk_sel,
+ + 	.enable_reg	= AM33XX_CM_PER_TIMER7_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.clksel_reg	= AM33XX_CLKSEL_TIMER7_CLK,
+ + 	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &omap2_clksel_recalc,
+ + };
+ + 
+ + static struct clk tpcc_ick = {
+ + 	.name		= "tpcc_ick",
+ + 	.clkdm_name	= "l3_clkdm",
+ + 	.parent		= &l3_gclk,
+ + 	.enable_reg	= AM33XX_CM_PER_TPCC_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk tptc0_ick = {
+ + 	.name		= "tptc0_ick",
+ + 	.parent		= &l3_gclk,
+ + 	.clkdm_name	= "l3_clkdm",
+ + 	.enable_reg	= AM33XX_CM_PER_TPTC0_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk tptc1_ick = {
+ + 	.name		= "tptc1_ick",
+ + 	.clkdm_name	= "l3_clkdm",
+ + 	.parent		= &l3_gclk,
+ + 	.enable_reg	= AM33XX_CM_PER_TPTC1_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk tptc2_ick = {
+ + 	.name		= "tptc2_ick",
+ + 	.clkdm_name	= "l3_clkdm",
+ + 	.parent		= &l3_gclk,
+ + 	.enable_reg	= AM33XX_CM_PER_TPTC2_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk uart1_ick = {
+ + 	.name		= "uart1_ick",
+ + 	.parent		= &l4_wkup_gclk,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk uart1_fck = {
+ + 	.name		= "uart1_fck",
+ + 	.clkdm_name	= "l4_wkup_clkdm",
+ + 	.parent		= &per_192mhz_clk,
+ + 	.enable_reg	= AM33XX_CM_WKUP_UART0_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.fixed_div	= 4,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &omap_fixed_divisor_recalc,
+ + };
+ + 
+ + static struct clk uart2_ick = {
+ + 	.name		= "uart2_ick",
+ + 	.parent		= &l4ls_gclk,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk uart2_fck = {
+ + 	.name		= "uart2_fck",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &per_192mhz_clk,
+ + 	.enable_reg	= AM33XX_CM_PER_UART1_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.fixed_div	= 4,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &omap_fixed_divisor_recalc,
+ + };
+ + 
+ + static struct clk uart3_ick = {
+ + 	.name		= "uart3_ick",
+ + 	.parent		= &l4ls_gclk,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk uart3_fck = {
+ + 	.name		= "uart3_fck",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &per_192mhz_clk,
+ + 	.enable_reg	= AM33XX_CM_PER_UART2_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.fixed_div	= 4,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &omap_fixed_divisor_recalc,
+ + };
+ + 
+ + static struct clk uart4_ick = {
+ + 	.name		= "uart4_ick",
+ + 	.parent		= &l4ls_gclk,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk uart4_fck = {
+ + 	.name		= "uart4_fck",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &per_192mhz_clk,
+ + 	.enable_reg	= AM33XX_CM_PER_UART3_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.fixed_div	= 4,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &omap_fixed_divisor_recalc,
+ + };
+ + 
+ + static struct clk uart5_ick = {
+ + 	.name		= "uart5_ick",
+ + 	.parent		= &l4ls_gclk,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk uart5_fck = {
+ + 	.name		= "uart5_fck",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &per_192mhz_clk,
+ + 	.enable_reg	= AM33XX_CM_PER_UART4_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.fixed_div	= 4,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &omap_fixed_divisor_recalc,
+ + };
+ + 
+ + static struct clk uart6_ick = {
+ + 	.name		= "uart6_ick",
+ + 	.parent		= &l4ls_gclk,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk uart6_fck = {
+ + 	.name		= "uart6_fck",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &per_192mhz_clk,
+ + 	.enable_reg	= AM33XX_CM_PER_UART5_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.fixed_div	= 4,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &omap_fixed_divisor_recalc,
+ + };
+ + 
+ + static struct clk wkup_m3_fck = {
+ + 	.name		= "wkup_m3_fck",
+ + 	.clkdm_name	= "l4_wkup_aon_clkdm",
+ + 	.parent		= &l4_wkup_aon_gclk,
+ + 	.enable_reg	= AM33XX_CM_WKUP_WKUP_M3_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk cpsw_250mhz_clk = {
+ + 	.name		= "cpsw_250mhz_clk",
+ + 	.clkdm_name	= "l4hs_clkdm",
+ + 	.parent		= &sysclk2_ck,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk cpsw_125mhz_gclk = {
+ + 	.name		= "cpsw_125mhz_gclk",
+ + 	.clkdm_name	= "cpsw_125mhz_clkdm",
+ + 	.parent		= &sysclk2_ck,
+ + 	.ops		= &clkops_null,
+ + 	.fixed_div	= 2,
+ + 	.recalc		= &omap_fixed_divisor_recalc,
+ + };
+ + 
+ + /*
+ +  * TODO: As per clock tree @OPP50 /2 is used, but there is not register
+ +  * to configure this. @ normal OPP, /5 is used - 250MHz/5 = 50MHz
+ +  */
+ + static struct clk cpsw_50mhz_clk = {
+ + 	.name		= "cpsw_50mhz_clk",
+ + 	.clkdm_name	= "l4hs_clkdm",
+ + 	.parent		= &sysclk2_ck,
+ + 	.ops		= &clkops_null,
+ + 	.fixed_div	= 5,
+ + 	.recalc		= &omap_fixed_divisor_recalc,
+ + };
+ + 
+ + static struct clk cpsw_5mhz_clk = {
+ + 	.name		= "cpsw_5mhz_clk",
+ + 	.clkdm_name	= "l4hs_clkdm",
+ + 	.parent		= &cpsw_50mhz_clk,
+ + 	.ops		= &clkops_null,
+ + 	.fixed_div	= 10,
+ + 	.recalc		= &omap_fixed_divisor_recalc,
+ + };
+ + 
+ + static struct clk cpgmac0_ick = {
+ + 	.name		= "cpgmac0_ick",
+ + 	.clkdm_name	= "cpsw_125mhz_clkdm",
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.enable_reg	= AM33XX_CM_PER_CPGMAC0_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.parent		= &cpsw_125mhz_gclk,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static const struct clksel cpsw_cpts_rft_clkmux_sel[] = {
+ + 	{ .parent = &sysclk2_ck, .rates = div_1_0_rates },
+ + 	{ .parent = &sysclk1_ck, .rates = div_1_1_rates },
+ + 	{ .parent = NULL },
+ + };
+ + 
+ + static struct clk cpsw_cpts_rft_clk = {
+ + 	.name		= "cpsw_cpts_rft_clk",
+ + 	.clkdm_name	= "l3_clkdm",
+ + 	.parent		= &sysclk2_ck,
+ + 	.clksel		= cpsw_cpts_rft_clkmux_sel,
+ + 	.clksel_reg	= AM33XX_CM_CPTS_RFT_CLKSEL,
+ + 	.clksel_mask	= AM33XX_CLKSEL_0_0_MASK,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk usbotg_ick = {
+ + 	.name		= "usbotg_ick",
+ + 	.clkdm_name	= "l3s_clkdm",
+ + 	.parent		= &l3s_gclk,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.enable_reg	= AM33XX_CM_PER_USB0_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk usbotg_fck = {
+ + 	.name		= "usbotg_fck",
+ + 	.clkdm_name	= "l3s_clkdm",
+ + 	.parent		= &usb_pll_clk,
+ + 	.enable_reg	= AM33XX_CM_CLKDCOLDO_DPLL_PER,
+ + 	.enable_bit	= AM33XX_ST_DPLL_CLKDCOLDO_SHIFT,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + /* gpio */
+ + static const struct clksel gpio0_dbclk_mux_sel[] = {
+ + 	{ .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
+ + 	{ .parent = &clk_32768_ck, .rates = div_1_1_rates },
+ + 	{ .parent = &clk_32khz_timer, .rates = div_1_2_rates },
+ + 	{ .parent = NULL },
+ + };
+ + 
+ + static struct clk gpio0_dbclk_mux_ck = {
+ + 	.name		= "gpio0_dbclk_mux_ck",
+ + 	.clkdm_name	= "l4_wkup_clkdm",
+ + 	.parent		= &clk_rc32k_ck,
+ + 	.init		= &omap2_init_clksel_parent,
+ + 	.clksel		= gpio0_dbclk_mux_sel,
+ + 	.clksel_reg	= AM33XX_CLKSEL_GPIO0_DBCLK,
+ + 	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &omap2_clksel_recalc,
+ + };
+ + 
+ + static struct clk gpio0_dbclk = {
+ + 	.name		= "gpio0_dbclk",
+ + 	.clkdm_name	= "l4_wkup_clkdm",
+ + 	.parent		= &gpio0_dbclk_mux_ck,
+ + 	.enable_reg	= AM33XX_CM_WKUP_GPIO0_CLKCTRL,
+ + 	.enable_bit	= AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk gpio0_ick = {
+ + 	.name		= "gpio0_ick",
+ + 	.clkdm_name	= "l4_wkup_clkdm",
+ + 	.parent		= &l4_wkup_gclk,
+ + 	.enable_reg	= AM33XX_CM_WKUP_GPIO0_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk gpio1_dbclk = {
+ + 	.name		= "gpio1_dbclk",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &clkdiv32k_ick,
+ + 	.enable_reg	= AM33XX_CM_PER_GPIO1_CLKCTRL,
+ + 	.enable_bit	= AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk gpio1_ick = {
+ + 	.name		= "gpio1_ick",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &l4ls_gclk,
+ + 	.enable_reg	= AM33XX_CM_PER_GPIO1_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk gpio2_dbclk = {
+ + 	.name		= "gpio2_dbclk",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &clkdiv32k_ick,
+ + 	.enable_reg	= AM33XX_CM_PER_GPIO2_CLKCTRL,
+ + 	.enable_bit	= AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk gpio2_ick = {
+ + 	.name		= "gpio2_ick",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &l4ls_gclk,
+ + 	.enable_reg	= AM33XX_CM_PER_GPIO2_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk gpio3_dbclk = {
+ + 	.name		= "gpio3_dbclk",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &clkdiv32k_ick,
+ + 	.enable_reg	= AM33XX_CM_PER_GPIO3_CLKCTRL,
+ + 	.enable_bit	= AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk gpio3_ick = {
+ + 	.name		= "gpio3_ick",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &l4ls_gclk,
+ + 	.enable_reg	= AM33XX_CM_PER_GPIO3_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static const struct clksel pruss_ocp_clk_mux_sel[] = {
+ + 	{ .parent = &l3_gclk, .rates = div_1_0_rates },
+ + 	{ .parent = &disp_pll_clk, .rates = div_1_1_rates },
+ + 	{ .parent = NULL },
+ + };
+ + 
+ + static struct clk pruss_ocp_gclk = {
+ + 	.name		= "pruss_ocp_gclk",
+ + 	.parent		= &l3_gclk,
+ + 	.init		= &omap2_init_clksel_parent,
+ + 	.clksel		= pruss_ocp_clk_mux_sel,
+ + 	.clksel_reg	= AM33XX_CLKSEL_PRUSS_OCP_CLK,
+ + 	.clksel_mask	= AM33XX_CLKSEL_0_0_MASK,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk pruss_iep_gclk = {
+ + 	.name		= "pruss_iep_gclk",
+ + 	.clkdm_name	= "pruss_ocp_clkdm",
+ + 	.parent		= &l3_gclk,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk pruss_uart_gclk = {
+ + 	.name		= "pruss_uart_gclk",
+ + 	.clkdm_name	= "pruss_ocp_clkdm",
+ + 	.parent		= &per_192mhz_clk,
+ + 	.enable_reg	= AM33XX_CM_PER_PRUSS_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk lcdc_ick = {
+ + 	.name		= "lcdc_ick",
+ + 	.clkdm_name	= "l3_clkdm",
+ + 	.parent		= &sysclk1_ck,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static const struct clksel lcd_clk_mux_sel[] = {
+ + 	{ .parent = &disp_pll_clk, .rates = div_1_0_rates },
+ + 	{ .parent = &sysclk2_ck, .rates = div_1_1_rates },
+ + 	{ .parent = &per_192mhz_clk, .rates = div_1_2_rates },
+ + 	{ .parent = NULL },
+ + };
+ + 
+ + static struct clk lcd_gclk = {
+ + 	.name		= "lcd_gclk",
+ + 	.parent		= &disp_pll_clk,
+ + 	.init		= &omap2_init_clksel_parent,
+ + 	.clksel		= lcd_clk_mux_sel,
+ + 	.clksel_reg	= AM33XX_CLKSEL_LCDC_PIXEL_CLK,
+ + 	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk lcdc_fck = {
+ + 	.name		= "lcdc_fck",
+ + 	.clkdm_name	= "lcdc_clkdm",
+ + 	.parent		= &lcd_gclk,
+ + 	.enable_reg	= AM33XX_CM_PER_LCDC_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk mmc_clk = {
+ + 	.name		= "mmc_clk",
+ + 	.parent		= &per_192mhz_clk,
+ + 	.ops		= &clkops_null,
+ + 	.fixed_div	= 2,
+ + 	.recalc		= &omap_fixed_divisor_recalc,
+ + };
+ + 
+ + static struct clk mmc0_ick = {
+ + 	.name		= "mmc0_ick",
+ + 	.parent		= &l4ls_gclk,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk mmc0_fck = {
+ + 	.name		= "mmc0_fck",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &mmc_clk,
+ + 	.enable_reg	= AM33XX_CM_PER_MMC0_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk mmc1_ick = {
+ + 	.name		= "mmc1_ick",
+ + 	.parent		= &l4ls_gclk,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk mmc1_fck = {
+ + 	.name		= "mmc1_fck",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.parent		= &mmc_clk,
+ + 	.enable_reg	= AM33XX_CM_PER_MMC1_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk mmc2_ick = {
+ + 	.name		= "mmc2_ick",
+ + 	.parent		= &l4ls_gclk,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk mmc2_fck = {
+ + 	.name		= "mmc2_fck",
+ + 	.clkdm_name	= "l3s_clkdm",
+ + 	.parent		= &mmc_clk,
+ + 	.enable_reg	= AM33XX_CM_PER_MMC2_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static const struct clksel gfx_clksel_sel[] = {
+ + 	{ .parent = &sysclk1_ck, .rates = div_1_0_rates },
+ + 	{ .parent = &per_192mhz_clk, .rates = div_1_1_rates },
+ + 	{ .parent = NULL },
+ + };
+ + 
+ + static struct clk gfx_fclk_clksel_ck = {
+ + 	.name		= "gfx_fclk_clksel_ck",
+ + 	.parent		= &sysclk1_ck,
+ + 	.clksel		= gfx_clksel_sel,
+ + 	.ops		= &clkops_null,
+ + 	.clksel_reg	= AM33XX_CLKSEL_GFX_FCLK,
+ + 	.clksel_mask	= AM33XX_CLKSEL_GFX_FCLK_MASK,
+ + 	.recalc		= &omap2_clksel_recalc,
+ + };
+ + 
+ + static const struct clksel_rate div_1_0_2_1_rates[] = {
+ + 	{ .div = 1, .val = 0, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 2, .val = 1, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 0 },
+ + };
+ + 
+ + static const struct clksel gfx_div_sel[] = {
+ + 	{ .parent = &gfx_fclk_clksel_ck, .rates = div_1_0_2_1_rates },
+ + 	{ .parent = NULL },
+ + };
+ + 
+ + static struct clk gfx_ick = {
+ + 	.name		= "gfx_ick",
+ + 	.clkdm_name	= "gfx_l3_clkdm",
+ + 	.parent		= &gfx_l3_gclk,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk gfx_fclk = {
+ + 	.name		= "gfx_fclk",
+ + 	.clkdm_name	= "gfx_l3_clkdm",
+ + 	.parent		= &gfx_fclk_clksel_ck,
+ + 	.clksel		= gfx_div_sel,
+ + 	.enable_reg	= AM33XX_CM_GFX_GFX_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.clksel_reg	= AM33XX_CLKSEL_GFX_FCLK,
+ + 	.clksel_mask	= AM33XX_CLKSEL_0_0_MASK,
+ + 	.recalc		= &omap2_clksel_recalc,
+ + 	.round_rate	= &omap2_clksel_round_rate,
+ + 	.set_rate	= &omap2_clksel_set_rate,
+ + 	.ops		= &clkops_omap2_dflt,
+ + };
+ + 
+ + static const struct clksel sysclkout_pre_sel[] = {
+ + 	{ .parent = &clk_32768_ck, .rates = div_1_0_rates },
+ + 	{ .parent = &l3_gclk, .rates = div_1_1_rates },
+ + 	{ .parent = &ddr_pll_clk, .rates = div_1_2_rates },
+ + 	{ .parent = &per_192mhz_clk, .rates = div_1_3_rates },
+ + 	{ .parent = &lcd_gclk, .rates = div_1_4_rates },
+ + 	{ .parent = NULL },
+ + };
+ + 
+ + static struct clk sysclkout_pre_ck = {
+ + 	.name		= "sysclkout_pre_ck",
+ + 	.parent		= &clk_32768_ck,
+ + 	.init		= &omap2_init_clksel_parent,
+ + 	.clksel		= sysclkout_pre_sel,
+ + 	.clksel_reg	= AM33XX_CM_CLKOUT_CTRL,
+ + 	.clksel_mask	= AM33XX_CLKOUT2SOURCE_MASK,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &omap2_clksel_recalc,
+ + };
+ + 
+ + /* Divide by 8 clock rates with default clock is 1/1*/
+ + static const struct clksel_rate div8_rates[] = {
+ + 	{ .div = 1, .val = 0, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 2, .val = 1, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 3, .val = 2, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 4, .val = 3, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 5, .val = 4, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 6, .val = 5, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 7, .val = 6, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 8, .val = 7, .flags = RATE_IN_AM33XX },
+ + 	{ .div = 0 },
+ + };
+ + 
+ + static const struct clksel clkout2_div[] = {
+ + 	{ .parent = &sysclkout_pre_ck, .rates = div8_rates },
+ + 	{ .parent = NULL },
+ + };
+ + 
+ + static struct clk clkout2_ck = {
+ + 	.name		= "clkout2_ck",
+ + 	.parent		= &sysclkout_pre_ck,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.clksel		= clkout2_div,
+ + 	.clksel_reg	= AM33XX_CM_CLKOUT_CTRL,
+ + 	.clksel_mask	= AM33XX_CLKOUT2DIV_MASK,
+ + 	.enable_reg	= AM33XX_CM_CLKOUT_CTRL,
+ + 	.enable_bit	= AM33XX_CLKOUT2EN_SHIFT,
+ + 	.recalc		= &omap2_clksel_recalc,
+ + 	.round_rate	= &omap2_clksel_round_rate,
+ + 	.set_rate	= &omap2_clksel_set_rate,
+ + };
+ + 
+ + static struct clk vtp_clk = {
+ + 	.name		= "vtp_clk",
+ + 	.parent		= &sys_clkin_ck,
+ + 	.ops		= &clkops_null,
+ + 	.fixed_div	= 2,
+ + 	.recalc		= &omap_fixed_divisor_recalc,
+ + };
+ + 
+ + static const struct clksel wdt_clkmux_sel[] = {
+ + 	{ .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
+ + 	{ .parent = &clk_32khz_ck, .rates = div_1_1_rates },
+ + 	{ .parent = NULL },
+ + };
+ + 
+ + static struct clk wdt0_ick = {
+ + 	.name		= "wdt0_ick",
+ + 	.parent		= &l4_wkup_gclk,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk wdt0_fck = {
+ + 	.name		= "wdt0_fck",
+ + 	.clkdm_name	= "l4_wkup_clkdm",
+ + 	.parent		= &clk_rc32k_ck,
+ + 	.clksel		= wdt_clkmux_sel,
+ + 	.enable_reg	= AM33XX_CM_WKUP_WDT0_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk wdt1_ick = {
+ + 	.name		= "wdt1_ick",
+ + 	.parent		= &l4_wkup_gclk,
+ + 	.ops		= &clkops_null,
+ + 	.recalc		= &followparent_recalc,
+ + };
+ + 
+ + static struct clk wdt1_fck = {
+ + 	.name		= "wdt1_fck",
+ + 	.clkdm_name	= "l4_wkup_clkdm",
+ + 	.parent		= &clk_32khz_ck,
+ + 	.init		= &am33xx_init_timer_parent,
+ + 	.clksel		= wdt_clkmux_sel,
+ + 	.enable_reg	= AM33XX_CM_WKUP_WDT1_CLKCTRL,
+ + 	.enable_bit	= AM33XX_MODULEMODE_SWCTRL,
+ + 	.clksel_reg	= AM33XX_CLKSEL_WDT1_CLK,
+ + 	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.recalc		= &omap2_clksel_recalc,
+ + };
+ + 
+ + /*
+ +  * Provides clock definitions for enabling bits for Time base module in
+ +  * PWMSS ctrl register.
+ +  */
+ + 
+ + static struct clk ehrpwm0_tbclk = {
+ + 	.name		= "ehrpwm0_tbclk",
+ + 	.enable_reg	= AM33XX_CONTROL_PWMSS_CTRL,
+ + 	.enable_bit	= AM33XX_PWMSS0_TBCLKEN,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.flags		= ENABLE_ON_INIT,
+ + };
+ + 
+ + static struct clk ehrpwm1_tbclk = {
+ + 	.name		= "ehrpwm1_tbclk",
+ + 	.enable_reg	= AM33XX_CONTROL_PWMSS_CTRL,
+ + 	.enable_bit	= AM33XX_PWMSS1_TBCLKEN,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.flags		= ENABLE_ON_INIT,
+ + };
+ + 
+ + static struct clk ehrpwm2_tbclk = {
+ + 	.name		= "ehrpwm2_tbclk",
+ + 	.enable_reg	= AM33XX_CONTROL_PWMSS_CTRL,
+ + 	.enable_bit	= AM33XX_PWMSS2_TBCLKEN,
+ + 	.ops		= &clkops_omap2_dflt,
+ + 	.flags		= ENABLE_ON_INIT,
+ + };
+ + 
+ + 
+ + /*
+ +  * clkdev
+ +  */
+ + static struct omap_clk am33xx_clks[] = {
+ + 	CLK(NULL,	"clk_32768_ck",		&clk_32768_ck,	CK_AM33XX),
+ + 	CLK(NULL,	"clk_32khz_ck",		&clk_32khz_ck,	CK_AM33XX),
+ + 	CLK(NULL,	"clk_rc32k_ck",		&clk_rc32k_ck,	CK_AM33XX),
+ + 	CLK(NULL,	"virt_19_2m_ck",	&virt_19_2m_ck,	CK_AM33XX),
+ + 	CLK(NULL,	"virt_24m_ck",		&virt_24m_ck,	CK_AM33XX),
+ + 	CLK(NULL,	"virt_25m_ck",		&virt_25m_ck,	CK_AM33XX),
+ + 	CLK(NULL,	"virt_26m_ck",		&virt_26m_ck,	CK_AM33XX),
+ + 	CLK(NULL,	"sys_clkin_ck",		&sys_clkin_ck,	CK_AM33XX),
+ + 	CLK(NULL,	"tclkin_ck",		&tclkin_ck,	CK_AM33XX),
+ + 	CLK(NULL,	"dpll_core_ck",		&dpll_core_ck,		CK_AM33XX),
+ + 	CLK(NULL,	"dpll_core_x2_ck",	&dpll_core_x2_ck,	CK_AM33XX),
+ + 	CLK(NULL,	"dpll_core_m4_ck",	&dpll_core_m4_ck,	CK_AM33XX),
+ + 	CLK(NULL,	"dpll_core_m5_ck",	&dpll_core_m5_ck,	CK_AM33XX),
+ + 	CLK(NULL,	"dpll_core_m6_ck",	&dpll_core_m6_ck,	CK_AM33XX),
+ + 	CLK(NULL,	"sysclk1_ck",		&sysclk1_ck,	CK_AM33XX),
+ + 	CLK(NULL,	"sysclk2_ck",		&sysclk2_ck,	CK_AM33XX),
+ + 	CLK(NULL,	"core_clk_out",		&core_clk_out,	CK_AM33XX),
+ + 	CLK(NULL,	"clk_32khz_timer",	&clk_32khz_timer, CK_AM33XX),
+ + 	CLK(NULL,	"dpll_mpu_ck",		&dpll_mpu_ck,		CK_AM33XX),
+ + 	CLK(NULL,	"dpll_mpu_m2_ck",	&dpll_mpu_m2_ck,	CK_AM33XX),
+ + 	CLK(NULL,	"mpu_ck",		&mpu_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"dpll_ddr_ck",		&dpll_ddr_ck,		CK_AM33XX),
+ + 	CLK(NULL,	"dpll_ddr_m2_ck",	&dpll_ddr_m2_ck,	CK_AM33XX),
+ + 	CLK(NULL,	"ddr_pll_clk",		&ddr_pll_clk,	CK_AM33XX),
+ + 	CLK(NULL,	"emif_fck",		&emif_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"emif_fw_fck",		&emif_fw_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"dpll_disp_ck",		&dpll_disp_ck,		CK_AM33XX),
+ + 	CLK(NULL,	"dpll_disp_m2_ck",	&dpll_disp_m2_ck,	CK_AM33XX),
+ + 	CLK(NULL,	"disp_pll_clk",		&disp_pll_clk,		CK_AM33XX),
+ + 	CLK(NULL,	"dpll_per_ck",		&dpll_per_ck,	CK_AM33XX),
+ + 	CLK(NULL,	"dpll_per_m2_ck",	&dpll_per_m2_ck,	CK_AM33XX),
+ + 	CLK(NULL,	"per_192mhz_clk",	&per_192mhz_clk,	CK_AM33XX),
+ + 	CLK(NULL,	"usb_pll_clk",		&usb_pll_clk,		CK_AM33XX),
+ + 	CLK(NULL,	"core_100mhz_ck",	&core_100mhz_ck,	CK_AM33XX),
+ + 	CLK(NULL,	"l3_ick",		&l3_ick,	CK_AM33XX),
+ + 	CLK(NULL,	"l3_instr_ick",		&l3_instr_ick,	CK_AM33XX),
+ + 	CLK(NULL,	"adc_tsc_fck",		&adc_tsc_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"adc_tsc_ick",		&adc_tsc_ick,	CK_AM33XX),
+ + 	CLK(NULL,	"aes0_fck",		&aes0_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"l4_cefuse_gclk",	&l4_cefuse_gclk, CK_AM33XX),
+ + 	CLK(NULL,	"cefuse_fck",		&cefuse_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"cefuse_iclk",		&cefuse_iclk,	CK_AM33XX),
+ + 	CLK(NULL,	"clkdiv32k_ick",	&clkdiv32k_ick,	CK_AM33XX),
+ + 	CLK(NULL,	"control_fck",		&control_fck,	CK_AM33XX),
+ + 	CLK("cpsw.0",	NULL,			&cpgmac0_ick,	CK_AM33XX),
+ + 	CLK("d_can.0",	"fck",			&dcan0_fck,	CK_AM33XX),
+ + 	CLK("d_can.1",	"fck",			&dcan1_fck,	CK_AM33XX),
+ + 	CLK("d_can.0",	"ick",			&dcan0_ick,	CK_AM33XX),
+ + 	CLK("d_can.1",	"ick",			&dcan1_ick,	CK_AM33XX),
+ + 	CLK(NULL,	"debugss_ick",		&debugss_ick,	CK_AM33XX),
+ + 	CLK(NULL,	"elm_fck",		&elm_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"epwmss0_fck",		&epwmss0_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"epwmss1_fck",		&epwmss1_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"epwmss2_fck",		&epwmss2_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"gpio0_ick",		&gpio0_ick,	CK_AM33XX),
+ + 	CLK(NULL,	"gpio1_ick",		&gpio1_ick,	CK_AM33XX),
+ + 	CLK(NULL,	"gpio2_ick",		&gpio2_ick,	CK_AM33XX),
+ + 	CLK(NULL,	"gpio3_ick",		&gpio3_ick,	CK_AM33XX),
+ + 	CLK(NULL,	"gpmc_fck",		&gpmc_fck,	CK_AM33XX),
+ + 	CLK("omap_i2c.1",	"fck",		&i2c1_fck,	CK_AM33XX),
+ + 	CLK("omap_i2c.1",	"ick",		&i2c1_ick,	CK_AM33XX),
+ + 	CLK("omap_i2c.2",	"fck",		&i2c2_fck,	CK_AM33XX),
+ + 	CLK("omap_i2c.2",	"ick",		&i2c2_ick,	CK_AM33XX),
+ + 	CLK("omap_i2c.3",	"fck",		&i2c3_fck,	CK_AM33XX),
+ + 	CLK("omap_i2c.3",	"ick",		&i2c3_ick,	CK_AM33XX),
+ + 	CLK(NULL,	"pruss_ocp_gclk",	&pruss_ocp_gclk,	CK_AM33XX),
+ + 	CLK(NULL,	"pruss_uart_gclk",	&pruss_uart_gclk,	CK_AM33XX),
+ + 	CLK(NULL,	"pruss_iep_gclk",	&pruss_iep_gclk,	CK_AM33XX),
+ + 	CLK(NULL,	"ieee5000_fck",		&ieee5000_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"l4hs_ick",		&l4hs_ick,	CK_AM33XX),
+ + 	CLK(NULL,	"l4wkup_ick",		&l4wkup_ick,	CK_AM33XX),
+ + 	CLK(NULL,	"l4fw_ick",		&l4fw_ick,	CK_AM33XX),
+ + 	CLK(NULL,	"l4ls_ick",		&l4ls_ick,	CK_AM33XX),
+ + 	CLK("da8xx_lcdc.0",	NULL,		&lcdc_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"mailbox0_fck",		&mailbox0_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"mcasp1_ick",		&mcasp0_ick,	CK_AM33XX),
+ + 	CLK("davinci-mcasp.0",	NULL,		&mcasp0_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"mcasp2_ick",		&mcasp1_ick,	CK_AM33XX),
+ + 	CLK("davinci-mcasp.1",	NULL,		&mcasp1_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"mlb_fck",		&mlb_fck,	CK_AM33XX),
+ + 	CLK("omap_hsmmc.0",	"ick",		&mmc0_ick,	CK_AM33XX),
+ + 	CLK("omap_hsmmc.1",	"ick",		&mmc1_ick,	CK_AM33XX),
+ + 	CLK("omap_hsmmc.2",	"ick",		&mmc2_ick,	CK_AM33XX),
+ + 	CLK("omap_hsmmc.0",	"fck",		&mmc0_fck,	CK_AM33XX),
+ + 	CLK("omap_hsmmc.1",	"fck",		&mmc1_fck,	CK_AM33XX),
+ + 	CLK("omap_hsmmc.2",	"fck",		&mmc2_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"mmu_fck",		&mmu_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"ocmcram_ick",		&ocmcram_ick,	CK_AM33XX),
+ + 	CLK(NULL,	"ocpwp_fck",		&ocpwp_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"pka_fck",		&pka_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"rng_fck",		&rng_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"rtc_fck",		&rtc_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"rtc_ick",		&rtc_ick,	CK_AM33XX),
+ + 	CLK(NULL,	"sha0_fck",		&sha0_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"smartreflex0_fck",	&smartreflex0_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"smartreflex0_ick",	&smartreflex0_ick,	CK_AM33XX),
+ + 	CLK(NULL,	"smartreflex1_fck",	&smartreflex1_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"smartreflex1_ick",	&smartreflex1_ick,	CK_AM33XX),
+ + 	CLK("omap2_mcspi.1",	"fck",		&spi0_fck,	CK_AM33XX),
+ + 	CLK("omap2_mcspi.2",	"fck",		&spi1_fck,	CK_AM33XX),
+ + 	CLK("omap2_mcspi.1",	"ick",		&spi0_ick,	CK_AM33XX),
+ + 	CLK("omap2_mcspi.2",	"ick",		&spi1_ick,	CK_AM33XX),
+ + 	CLK(NULL,	"spinlock_fck",		&spinlock_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"gpt0_fck",		&timer0_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"gpt1_fck",		&timer1_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"gpt2_fck",		&timer2_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"gpt3_fck",		&timer3_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"gpt4_fck",		&timer4_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"gpt5_fck",		&timer5_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"gpt6_fck",		&timer6_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"gpt7_fck",		&timer7_fck,	CK_AM33XX),
+ + 	CLK("da8xx_lcdc.0",	"lcdc_ick",	&lcdc_ick,	CK_AM33XX),
+ + 	CLK(NULL,	"tpcc_ick",		&tpcc_ick,	CK_AM33XX),
+ + 	CLK(NULL,	"tptc0_ick",		&tptc0_ick,	CK_AM33XX),
+ + 	CLK(NULL,	"tptc1_ick",		&tptc1_ick,	CK_AM33XX),
+ + 	CLK(NULL,	"tptc2_ick",		&tptc2_ick,	CK_AM33XX),
+ + 	CLK(NULL,	"uart1_fck",		&uart1_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"uart2_fck",		&uart2_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"uart3_fck",		&uart3_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"uart4_fck",		&uart4_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"uart5_fck",		&uart5_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"uart6_fck",		&uart6_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"uart1_ick",		&uart1_ick,	CK_AM33XX),
+ + 	CLK(NULL,	"uart2_ick",		&uart2_ick,	CK_AM33XX),
+ + 	CLK(NULL,	"uart3_ick",		&uart3_ick,	CK_AM33XX),
+ + 	CLK(NULL,	"uart4_ick",		&uart4_ick,	CK_AM33XX),
+ + 	CLK(NULL,	"uart5_ick",		&uart5_ick,	CK_AM33XX),
+ + 	CLK(NULL,	"uart6_ick",		&uart6_ick,	CK_AM33XX),
+ + 	CLK(NULL,	"usbotg_ick",		&usbotg_ick,	CK_AM33XX),
+ + 	CLK(NULL,	"usbotg_fck",		&usbotg_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"wdt0_ick",		&wdt0_ick,	CK_AM33XX),
+ + 	CLK(NULL,	"wdt0_fck",		&wdt0_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"wdt1_ick",		&wdt1_ick,	CK_AM33XX),
+ + 	CLK(NULL,	"wdt1_fck",		&wdt1_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"wkup_m3_fck",		&wkup_m3_fck,	CK_AM33XX),
+ + 	CLK(NULL,	"l3_aon_gclk",		&l3_aon_gclk,		CK_AM33XX),
+ + 	CLK(NULL,	"l4_wkup_aon_gclk",	&l4_wkup_aon_gclk,	CK_AM33XX),
+ + 	CLK(NULL,	"l4_rtc_gclk",		&l4_rtc_gclk,		CK_AM33XX),
+ + 	CLK(NULL,	"l3_gclk",		&l3_gclk,		CK_AM33XX),
+ + 	CLK(NULL,	"gfx_l3_gclk",		&gfx_l3_gclk,		CK_AM33XX),
+ + 	CLK(NULL,	"l4_wkup_gclk",		&l4_wkup_gclk,		CK_AM33XX),
+ + 	CLK(NULL,	"l4hs_gclk",		&l4hs_gclk,		CK_AM33XX),
+ + 	CLK(NULL,	"l3s_gclk",		&l3s_gclk,		CK_AM33XX),
+ + 	CLK(NULL,	"l4fw_gclk",		&l4fw_gclk,		CK_AM33XX),
+ + 	CLK(NULL,	"l4ls_gclk",		&l4ls_gclk,		CK_AM33XX),
+ + 	CLK(NULL,	"debug_clka_gclk",	&debug_clka_gclk,	CK_AM33XX),
+ + 	CLK(NULL,	"clk_24mhz",		&clk_24mhz,		CK_AM33XX),
+ + 	CLK(NULL,	"sysclk_div_ck",	&sysclk_div_ck,		CK_AM33XX),
+ + 	CLK(NULL,	"cpsw_250mhz_clk",	&cpsw_250mhz_clk,	CK_AM33XX),
+ + 	CLK(NULL,	"cpsw_125mhz_gclk",	&cpsw_125mhz_gclk,	CK_AM33XX),
+ + 	CLK(NULL,	"cpsw_50mhz_clk",	&cpsw_50mhz_clk,	CK_AM33XX),
+ + 	CLK(NULL,	"cpsw_5mhz_clk",	&cpsw_5mhz_clk,		CK_AM33XX),
+ + 	CLK(NULL,	"cpsw_cpts_rft_clk",	&cpsw_cpts_rft_clk,	CK_AM33XX),
+ + 	CLK(NULL,	"gpio0_dbclk_mux_ck",	&gpio0_dbclk_mux_ck,	CK_AM33XX),
+ + 	CLK(NULL,	"gpio0_dbclk",		&gpio0_dbclk,		CK_AM33XX),
+ + 	CLK(NULL,	"gpio1_dbclk",		&gpio1_dbclk,		CK_AM33XX),
+ + 	CLK(NULL,	"gpio2_dbclk",		&gpio2_dbclk,		CK_AM33XX),
+ + 	CLK(NULL,	"gpio3_dbclk",		&gpio3_dbclk,		CK_AM33XX),
+ + 	CLK(NULL,	"lcd_gclk",		&lcd_gclk,		CK_AM33XX),
+ + 	CLK(NULL,	"mmc_clk",		&mmc_clk,		CK_AM33XX),
+ + 	CLK(NULL,	"gfx_fclk_clksel_ck",	&gfx_fclk_clksel_ck,	CK_AM33XX),
+ + 	CLK(NULL,	"gfx_fclk",		&gfx_fclk,		CK_AM33XX),
+ + 	CLK(NULL,	"gfx_ick",		&gfx_ick,		CK_AM33XX),
+ + 	CLK(NULL,	"sysclkout_pre_ck",	&sysclkout_pre_ck,	CK_AM33XX),
+ + 	CLK(NULL,	"clkout2_ck",		&clkout2_ck,		CK_AM33XX),
+ + 	CLK(NULL,	"gpt0_ick",		&timer0_ick,		CK_AM33XX),
+ + 	CLK(NULL,	"gpt1_ick",		&timer1_ick,		CK_AM33XX),
+ + 	CLK(NULL,	"gpt2_ick",		&timer2_ick,		CK_AM33XX),
+ + 	CLK(NULL,	"gpt3_ick",		&timer3_ick,		CK_AM33XX),
+ + 	CLK(NULL,	"gpt4_ick",		&timer4_ick,		CK_AM33XX),
+ + 	CLK(NULL,	"gpt5_ick",		&timer5_ick,		CK_AM33XX),
+ + 	CLK(NULL,	"gpt6_ick",		&timer6_ick,		CK_AM33XX),
+ + 	CLK(NULL,	"gpt7_ick",		&timer7_ick,		CK_AM33XX),
+ + 	CLK(NULL,	"vtp_clk",		&vtp_clk,		CK_AM33XX),
+ + 	CLK(NULL,	"ehrpwm0_tbclk",	&ehrpwm0_tbclk,	CK_AM33XX),
+ + 	CLK(NULL,	"ehrpwm1_tbclk",	&ehrpwm1_tbclk,	CK_AM33XX),
+ + 	CLK(NULL,	"ehrpwm2_tbclk",	&ehrpwm2_tbclk,	CK_AM33XX),
+ + };
+ + 
+ + int __init am33xx_clk_init(void)
+ + {
+ + 	struct omap_clk *c;
+ + 	u32 cpu_clkflg;
+ + 
+ + 	cpu_mask = RATE_IN_AM33XX;
+ + 	cpu_clkflg = CK_AM33XX;
+ + 	
+ + 	clk_init(&omap2_clk_functions);
+ + 
+ + 	for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++)
+ + 		clk_preinit(c->lk.clk);
+ + 
+ + 	for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++)
+ + 		if (c->cpu & cpu_clkflg) {
+ + 			clkdev_add(&c->lk);
+ + 			clk_register(c->lk.clk);
+ + 			omap2_init_clk_clkdm(c->lk.clk);
+ + 		}
+ + 
+ + 	recalculate_root_clocks();
+ + 
+ + 	/*
+ + 	 * Only enable those clocks we will need, let the drivers
+ + 	 * enable other clocks as necessary
+ + 	 */
+ + 	clk_enable_init_clocks();
+ + 
+ + 	return 0;
+ + }
+ + 
+ + 
+ + 
+ + /* Common clock code */
+ + 
+ + /*
+ +  * Switch the MPU rate if specified on cmdline.  We cannot do this
+ +  * early until cmdline is parsed.  XXX This should be removed from the
+ +  * clock code and handled by the OPP layer code in the near future.
+ +  */
+ + static int __init omap3xxx_clk_arch_init(void)
+ + {
+ + 	int ret;
+ + 
+ + 	ret = omap2_clk_switch_mpurate_at_boot("dpll1_ck");
+ + 	if (!ret)
+ + 		omap2_clk_print_new_rates("osc_sys_ck", "core_ck", "arm_fck");
+ + 
+ + 	return ret;
+ + }
+ + 
+ + arch_initcall(omap3xxx_clk_arch_init);
+ + 
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/clock33xx.h linux-3.2.1/arch/arm/mach-ckb_3352/clock33xx.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/clock33xx.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/clock33xx.h	2014-11-25 13:19:14.856957256 +0900
+ ***************
+ *** 0 ****
+ --- 1,42 ----
+ + /*
+ +  * AM33XX clock function prototypes and macros.
+ +  *
+ +  * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK33XX_H
+ + #define __ARCH_ARM_MACH_OMAP2_CLOCK33XX_H
+ + 
+ + #define AM33XX_MAX_DPLL_MULT  2047
+ + #define AM33XX_MAX_DPLL_DIV   128
+ + 
+ + 
+ + int am33xx_clk_init(void);
+ + 
+ + /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
+ +      physically present, in such a case HWMOD enabling of
+ +      clock would be failure with default parent. And timer
+ +      probe thinks clock is already enabled, this leads to
+ +      crash upon accessing timer 3 & 6 registers in probe.
+ +      Fix by setting parent of both these timers to master
+ +      oscillator clock.
+ +    WDT1: On reset, RC Osc 32K clock is sourced to WDT1 module,
+ +      which is non-accurate clock-source and results into inaccuracy
+ +      with timer ticking.
+ +      The solution is to switch the input functional clock-source to
+ +      per_32k clock.
+ +  */
+ + static inline void am33xx_init_timer_parent(struct clk *clk)
+ + {
+ + 	omap2_clksel_set_parent(clk, clk->parent);
+ + }
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/clock.c linux-3.2.1/arch/arm/mach-ckb_3352/clock.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/clock.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/clock.c	2014-11-25 13:19:14.856957256 +0900
+ ***************
+ *** 0 ****
+ --- 1,492 ----
+ + /*
+ +  *  linux/arch/arm/mach-omap2/clock.c
+ +  *
+ +  *  Copyright (C) 2005-2008 Texas Instruments, Inc.
+ +  *  Copyright (C) 2004-2010 Nokia Corporation
+ +  *
+ +  *  Contacts:
+ +  *  Richard Woodruff <r-woodruff2@ti.com>
+ +  *  Paul Walmsley
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + #undef DEBUG
+ + 
+ + #include <linux/kernel.h>
+ + #include <linux/list.h>
+ + #include <linux/errno.h>
+ + #include <linux/err.h>
+ + #include <linux/delay.h>
+ + #include <linux/clk.h>
+ + #include <linux/io.h>
+ + #include <linux/bitops.h>
+ + #include <trace/events/power.h>
+ + 
+ + #include <asm/cpu.h>
+ + #include <plat/clock.h>
+ + #include "clockdomain.h"
+ + #include <plat/cpu.h>
+ + #include <plat/prcm.h>
+ + 
+ + #include "clock.h"
+ + #include "cm2xxx_3xxx.h"
+ + #include "cm-regbits-34xx.h"
+ + 
+ + u16 cpu_mask;
+ + 
+ + /*
+ +  * clkdm_control: if true, then when a clock is enabled in the
+ +  * hardware, its clockdomain will first be enabled; and when a clock
+ +  * is disabled in the hardware, its clockdomain will be disabled
+ +  * afterwards.
+ +  */
+ + static bool clkdm_control = true;
+ + 
+ + /*
+ +  * OMAP2+ specific clock functions
+ +  */
+ + 
+ + /* Private functions */
+ + 
+ + /**
+ +  * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE
+ +  * @clk: struct clk * belonging to the module
+ +  *
+ +  * If the necessary clocks for the OMAP hardware IP block that
+ +  * corresponds to clock @clk are enabled, then wait for the module to
+ +  * indicate readiness (i.e., to leave IDLE).  This code does not
+ +  * belong in the clock code and will be moved in the medium term to
+ +  * module-dependent code.  No return value.
+ +  */
+ + static void _omap2_module_wait_ready(struct clk *clk)
+ + {
+ + 	void __iomem *companion_reg, *idlest_reg;
+ + 	u8 other_bit, idlest_bit, idlest_val;
+ + 
+ + 	/* Not all modules have multiple clocks that their IDLEST depends on */
+ + 	if (clk->ops->find_companion) {
+ + 		clk->ops->find_companion(clk, &companion_reg, &other_bit);
+ + 		if (!(__raw_readl(companion_reg) & (1 << other_bit)))
+ + 			return;
+ + 	}
+ + 
+ + 	clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val);
+ + 
+ + 	omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), idlest_val,
+ + 			     clk->name);
+ + }
+ + 
+ + /* Public functions */
+ + 
+ + /**
+ +  * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
+ +  * @clk: OMAP clock struct ptr to use
+ +  *
+ +  * Convert a clockdomain name stored in a struct clk 'clk' into a
+ +  * clockdomain pointer, and save it into the struct clk.  Intended to be
+ +  * called during clk_register().  No return value.
+ +  */
+ + void omap2_init_clk_clkdm(struct clk *clk)
+ + {
+ + 	struct clockdomain *clkdm;
+ + 
+ + 	if (!clk->clkdm_name)
+ + 		return;
+ + 
+ + 	clkdm = clkdm_lookup(clk->clkdm_name);
+ + 	if (clkdm) {
+ + 		pr_debug("clock: associated clk %s to clkdm %s\n",
+ + 			 clk->name, clk->clkdm_name);
+ + 		clk->clkdm = clkdm;
+ + 	} else {
+ + 		pr_debug("clock: could not associate clk %s to "
+ + 			 "clkdm %s\n", clk->name, clk->clkdm_name);
+ + 	}
+ + }
+ + 
+ + /**
+ +  * omap2_clk_disable_clkdm_control - disable clkdm control on clk enable/disable
+ +  *
+ +  * Prevent the OMAP clock code from calling into the clockdomain code
+ +  * when a hardware clock in that clockdomain is enabled or disabled.
+ +  * Intended to be called at init time from omap*_clk_init().  No
+ +  * return value.
+ +  */
+ + void __init omap2_clk_disable_clkdm_control(void)
+ + {
+ + 	clkdm_control = false;
+ + }
+ + 
+ + /**
+ +  * omap2_clk_dflt_find_companion - find companion clock to @clk
+ +  * @clk: struct clk * to find the companion clock of
+ +  * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in
+ +  * @other_bit: u8 ** to return the companion clock bit shift in
+ +  *
+ +  * Note: We don't need special code here for INVERT_ENABLE for the
+ +  * time being since INVERT_ENABLE only applies to clocks enabled by
+ +  * CM_CLKEN_PLL
+ +  *
+ +  * Convert CM_ICLKEN* <-> CM_FCLKEN*.  This conversion assumes it's
+ +  * just a matter of XORing the bits.
+ +  *
+ +  * Some clocks don't have companion clocks.  For example, modules with
+ +  * only an interface clock (such as MAILBOXES) don't have a companion
+ +  * clock.  Right now, this code relies on the hardware exporting a bit
+ +  * in the correct companion register that indicates that the
+ +  * nonexistent 'companion clock' is active.  Future patches will
+ +  * associate this type of code with per-module data structures to
+ +  * avoid this issue, and remove the casts.  No return value.
+ +  */
+ + void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
+ + 				   u8 *other_bit)
+ + {
+ + 	u32 r;
+ + 
+ + 	/*
+ + 	 * Convert CM_ICLKEN* <-> CM_FCLKEN*.  This conversion assumes
+ + 	 * it's just a matter of XORing the bits.
+ + 	 */
+ + 	r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN));
+ + 
+ + 	*other_reg = (__force void __iomem *)r;
+ + 	*other_bit = clk->enable_bit;
+ + }
+ + 
+ + int omap2_dflt_clk_enable(struct clk *clk)
+ + {
+ + 	u32 v;
+ + 
+ + 	if (unlikely(clk->enable_reg == NULL)) {
+ + 		pr_err("clock.c: Enable for %s without enable code\n",
+ + 		       clk->name);
+ + 		return 0; /* REVISIT: -EINVAL */
+ + 	}
+ + 
+ + 	v = __raw_readl(clk->enable_reg);
+ + 	if (clk->flags & INVERT_ENABLE)
+ + 		v &= ~(1 << clk->enable_bit);
+ + 	else
+ + 		v |= (1 << clk->enable_bit);
+ + 	__raw_writel(v, clk->enable_reg);
+ + 	v = __raw_readl(clk->enable_reg); /* OCP barrier */
+ + 
+ + 	if (clk->ops->find_idlest)
+ + 		_omap2_module_wait_ready(clk);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + void omap2_dflt_clk_disable(struct clk *clk)
+ + {
+ + 	u32 v;
+ + 
+ + 	if (!clk->enable_reg) {
+ + 		/*
+ + 		 * 'Independent' here refers to a clock which is not
+ + 		 * controlled by its parent.
+ + 		 */
+ + 		printk(KERN_ERR "clock: clk_disable called on independent "
+ + 		       "clock %s which has no enable_reg\n", clk->name);
+ + 		return;
+ + 	}
+ + 
+ + 	v = __raw_readl(clk->enable_reg);
+ + 	if (clk->flags & INVERT_ENABLE)
+ + 		v |= (1 << clk->enable_bit);
+ + 	else
+ + 		v &= ~(1 << clk->enable_bit);
+ + 	__raw_writel(v, clk->enable_reg);
+ + 	/* No OCP barrier needed here since it is a disable operation */
+ + }
+ + 
+ + const struct clkops clkops_omap2_dflt = {
+ + 	.enable		= omap2_dflt_clk_enable,
+ + 	.disable	= omap2_dflt_clk_disable,
+ + };
+ + 
+ + /**
+ +  * omap2_clk_disable - disable a clock, if the system is not using it
+ +  * @clk: struct clk * to disable
+ +  *
+ +  * Decrements the usecount on struct clk @clk.  If there are no users
+ +  * left, call the clkops-specific clock disable function to disable it
+ +  * in hardware.  If the clock is part of a clockdomain (which they all
+ +  * should be), request that the clockdomain be disabled.  (It too has
+ +  * a usecount, and so will not be disabled in the hardware until it no
+ +  * longer has any users.)  If the clock has a parent clock (most of
+ +  * them do), then call ourselves, recursing on the parent clock.  This
+ +  * can cause an entire branch of the clock tree to be powered off by
+ +  * simply disabling one clock.  Intended to be called with the clockfw_lock
+ +  * spinlock held.  No return value.
+ +  */
+ + void omap2_clk_disable(struct clk *clk)
+ + {
+ + 	if (clk->usecount == 0) {
+ + 		WARN(1, "clock: %s: omap2_clk_disable() called, but usecount "
+ + 		     "already 0?", clk->name);
+ + 		return;
+ + 	}
+ + 
+ + 	pr_debug("clock: %s: decrementing usecount\n", clk->name);
+ + 
+ + 	clk->usecount--;
+ + 
+ + 	if (clk->usecount > 0)
+ + 		return;
+ + 
+ + 	pr_debug("clock: %s: disabling in hardware\n", clk->name);
+ + 
+ + 	if (clk->ops && clk->ops->disable) {
+ + 		trace_clock_disable(clk->name, 0, smp_processor_id());
+ + 		clk->ops->disable(clk);
+ + 	}
+ + 
+ + 	if (clkdm_control && clk->clkdm)
+ + 		clkdm_clk_disable(clk->clkdm, clk);
+ + 
+ + 	if (clk->parent)
+ + 		omap2_clk_disable(clk->parent);
+ + }
+ + 
+ + /**
+ +  * omap2_clk_enable - request that the system enable a clock
+ +  * @clk: struct clk * to enable
+ +  *
+ +  * Increments the usecount on struct clk @clk.  If there were no users
+ +  * previously, then recurse up the clock tree, enabling all of the
+ +  * clock's parents and all of the parent clockdomains, and finally,
+ +  * enabling @clk's clockdomain, and @clk itself.  Intended to be
+ +  * called with the clockfw_lock spinlock held.  Returns 0 upon success
+ +  * or a negative error code upon failure.
+ +  */
+ + int omap2_clk_enable(struct clk *clk)
+ + {
+ + 	int ret;
+ + 
+ + 	pr_debug("clock: %s: incrementing usecount\n", clk->name);
+ + 
+ + 	clk->usecount++;
+ + 
+ + 	if (clk->usecount > 1)
+ + 		return 0;
+ + 
+ + 	pr_debug("clock: %s: enabling in hardware\n", clk->name);
+ + 
+ + 	if (clk->parent) {
+ + 		ret = omap2_clk_enable(clk->parent);
+ + 		if (ret) {
+ + 			WARN(1, "clock: %s: could not enable parent %s: %d\n",
+ + 			     clk->name, clk->parent->name, ret);
+ + 			goto oce_err1;
+ + 		}
+ + 	}
+ + 
+ + 	if (clkdm_control && clk->clkdm) {
+ + 		ret = clkdm_clk_enable(clk->clkdm, clk);
+ + 		if (ret) {
+ + 			WARN(1, "clock: %s: could not enable clockdomain %s: "
+ + 			     "%d\n", clk->name, clk->clkdm->name, ret);
+ + 			goto oce_err2;
+ + 		}
+ + 	}
+ + 
+ + 	if (clk->ops && clk->ops->enable) {
+ + 		trace_clock_enable(clk->name, 1, smp_processor_id());
+ + 		ret = clk->ops->enable(clk);
+ + 		if (ret) {
+ + 			WARN(1, "clock: %s: could not enable: %d\n",
+ + 			     clk->name, ret);
+ + 			goto oce_err3;
+ + 		}
+ + 	}
+ + 
+ + 	return 0;
+ + 
+ + oce_err3:
+ + 	if (clkdm_control && clk->clkdm)
+ + 		clkdm_clk_disable(clk->clkdm, clk);
+ + oce_err2:
+ + 	if (clk->parent)
+ + 		omap2_clk_disable(clk->parent);
+ + oce_err1:
+ + 	clk->usecount--;
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /* Given a clock and a rate apply a clock specific rounding function */
+ + long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
+ + {
+ + 	if (clk->round_rate)
+ + 		return clk->round_rate(clk, rate);
+ + 
+ + 	return clk->rate;
+ + }
+ + 
+ + /* Set the clock rate for a clock source */
+ + int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
+ + {
+ + 	int ret = -EINVAL;
+ + 
+ + 	pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
+ + 
+ + 	/* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
+ + 	if (clk->set_rate) {
+ + 		trace_clock_set_rate(clk->name, rate, smp_processor_id());
+ + 		ret = clk->set_rate(clk, rate);
+ + 	}
+ + 
+ + 	return ret;
+ + }
+ + 
+ + int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
+ + {
+ + 	if (!clk->clksel)
+ + 		return -EINVAL;
+ + 
+ + 	if (clk->parent == new_parent)
+ + 		return 0;
+ + 
+ + 	return omap2_clksel_set_parent(clk, new_parent);
+ + }
+ + 
+ + /* OMAP3/4 non-CORE DPLL clkops */
+ + 
+ + const struct clkops clkops_omap3_noncore_dpll_ops = {
+ + 	.enable		= omap3_noncore_dpll_enable,
+ + 	.disable	= omap3_noncore_dpll_disable,
+ + 	.allow_idle	= omap3_dpll_allow_idle,
+ + 	.deny_idle	= omap3_dpll_deny_idle,
+ + };
+ + 
+ + const struct clkops clkops_omap3_core_dpll_ops = {
+ + 	.allow_idle	= omap3_dpll_allow_idle,
+ + 	.deny_idle	= omap3_dpll_deny_idle,
+ + };
+ + 
+ + /*
+ +  * OMAP2+ clock reset and init functions
+ +  */
+ + 
+ + #ifdef CONFIG_OMAP_RESET_CLOCKS
+ + void omap2_clk_disable_unused(struct clk *clk)
+ + {
+ + 	u32 regval32, v;
+ + 
+ + 	v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
+ + 
+ + 	regval32 = __raw_readl(clk->enable_reg);
+ + 	if ((regval32 & (1 << clk->enable_bit)) == v)
+ + 		return;
+ + 
+ + 	pr_debug("Disabling unused clock \"%s\"\n", clk->name);
+ + 	clk->ops->disable(clk);
+ + 	
+ + 	if (clk->clkdm != NULL)
+ + 		pwrdm_clkdm_state_switch(clk->clkdm);
+ + }
+ + #endif
+ + 
+ + /**
+ +  * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument
+ +  * @mpurate_ck_name: clk name of the clock to change rate
+ +  *
+ +  * Change the ARM MPU clock rate to the rate specified on the command
+ +  * line, if one was specified.  @mpurate_ck_name should be
+ +  * "virt_prcm_set" on OMAP2xxx and "dpll1_ck" on OMAP34xx/OMAP36xx.
+ +  * XXX Does not handle voltage scaling - on OMAP2xxx this is currently
+ +  * handled by the virt_prcm_set clock, but this should be handled by
+ +  * the OPP layer.  XXX This is intended to be handled by the OPP layer
+ +  * code in the near future and should be removed from the clock code.
+ +  * Returns -EINVAL if 'mpurate' is zero or if clk_set_rate() rejects
+ +  * the rate, -ENOENT if the struct clk referred to by @mpurate_ck_name
+ +  * cannot be found, or 0 upon success.
+ +  */
+ + int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name)
+ + {
+ + 	struct clk *mpurate_ck;
+ + 	int r;
+ + 
+ + 	if (!mpurate)
+ + 		return -EINVAL;
+ + 
+ + 	mpurate_ck = clk_get(NULL, mpurate_ck_name);
+ + 	if (WARN(IS_ERR(mpurate_ck), "Failed to get %s.\n", mpurate_ck_name))
+ + 		return -ENOENT;
+ + 
+ + 	r = clk_set_rate(mpurate_ck, mpurate);
+ + 	if (IS_ERR_VALUE(r)) {
+ + 		WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n",
+ + 		     mpurate_ck->name, mpurate, r);
+ + 		clk_put(mpurate_ck);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	calibrate_delay();
+ + 	recalculate_root_clocks();
+ + 
+ + 	clk_put(mpurate_ck);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * omap2_clk_print_new_rates - print summary of current clock tree rates
+ +  * @hfclkin_ck_name: clk name for the off-chip HF oscillator
+ +  * @core_ck_name: clk name for the on-chip CORE_CLK
+ +  * @mpu_ck_name: clk name for the ARM MPU clock
+ +  *
+ +  * Prints a short message to the console with the HFCLKIN oscillator
+ +  * rate, the rate of the CORE clock, and the rate of the ARM MPU clock.
+ +  * Called by the boot-time MPU rate switching code.   XXX This is intended
+ +  * to be handled by the OPP layer code in the near future and should be
+ +  * removed from the clock code.  No return value.
+ +  */
+ + void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name,
+ + 				      const char *core_ck_name,
+ + 				      const char *mpu_ck_name)
+ + {
+ + 	struct clk *hfclkin_ck, *core_ck, *mpu_ck;
+ + 	unsigned long hfclkin_rate;
+ + 
+ + 	mpu_ck = clk_get(NULL, mpu_ck_name);
+ + 	if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name))
+ + 		return;
+ + 
+ + 	core_ck = clk_get(NULL, core_ck_name);
+ + 	if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name))
+ + 		return;
+ + 
+ + 	hfclkin_ck = clk_get(NULL, hfclkin_ck_name);
+ + 	if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name))
+ + 		return;
+ + 
+ + 	hfclkin_rate = clk_get_rate(hfclkin_ck);
+ + 
+ + 	pr_info("Switched to new clocking rate (Crystal/Core/MPU): "
+ + 		"%ld.%01ld/%ld/%ld MHz\n",
+ + 		(hfclkin_rate / 1000000),
+ + 		((hfclkin_rate / 100000) % 10),
+ + 		(clk_get_rate(core_ck) / 1000000),
+ + 		(clk_get_rate(mpu_ck) / 1000000));
+ + }
+ + 
+ + /* Common data */
+ + 
+ + struct clk_functions omap2_clk_functions = {
+ + 	.clk_enable		= omap2_clk_enable,
+ + 	.clk_disable		= omap2_clk_disable,
+ + 	.clk_round_rate		= omap2_clk_round_rate,
+ + 	.clk_set_rate		= omap2_clk_set_rate,
+ + 	.clk_set_parent		= omap2_clk_set_parent,
+ + 	.clk_disable_unused	= omap2_clk_disable_unused,
+ + #ifdef CONFIG_CPU_FREQ
+ + 	/* These will be removed when the OPP code is integrated */
+ + 	.clk_init_cpufreq_table	= omap2_clk_init_cpufreq_table,
+ + 	.clk_exit_cpufreq_table	= omap2_clk_exit_cpufreq_table,
+ + #endif
+ + };
+ + 
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/clock_common_data.c linux-3.2.1/arch/arm/mach-ckb_3352/clock_common_data.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/clock_common_data.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/clock_common_data.c	2014-11-25 13:19:14.856957256 +0900
+ ***************
+ *** 0 ****
+ --- 1,45 ----
+ + /*
+ +  *  linux/arch/arm/mach-omap2/clock_common_data.c
+ +  *
+ +  *  Copyright (C) 2005-2009 Texas Instruments, Inc.
+ +  *  Copyright (C) 2004-2009 Nokia Corporation
+ +  *
+ +  *  Contacts:
+ +  *  Richard Woodruff <r-woodruff2@ti.com>
+ +  *  Paul Walmsley
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  *
+ +  * This file contains clock data that is common to both the OMAP2xxx and
+ +  * OMAP3xxx clock definition files.
+ +  */
+ + 
+ + #include "clock.h"
+ + 
+ + /* clksel_rate data common to 24xx/343x */
+ + const struct clksel_rate gpt_32k_rates[] = {
+ + 	 { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_3XXX },
+ + 	 { .div = 0 }
+ + };
+ + 
+ + const struct clksel_rate gpt_sys_rates[] = {
+ + 	 { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_3XXX },
+ + 	 { .div = 0 }
+ + };
+ + 
+ + const struct clksel_rate gfx_l3_rates[] = {
+ + 	{ .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_3XXX },
+ + 	{ .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_3XXX },
+ + 	{ .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_3XXX },
+ + 	{ .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_3XXX },
+ + 	{ .div = 0 }
+ + };
+ + 
+ + const struct clksel_rate dsp_ick_rates[] = {
+ + 	{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
+ + 	{ .div = 2, .val = 2, .flags = RATE_IN_24XX },
+ + 	{ .div = 3, .val = 3, .flags = RATE_IN_243X },
+ + 	{ .div = 0 },
+ + };
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/clockdomain44xx.c linux-3.2.1/arch/arm/mach-ckb_3352/clockdomain44xx.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/clockdomain44xx.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/clockdomain44xx.c	2014-11-25 13:19:14.856957256 +0900
+ ***************
+ *** 0 ****
+ --- 1,61 ----
+ + /*
+ +  * OMAP4 clockdomain control
+ +  *
+ +  * Copyright (C) 2008-2010 Texas Instruments, Inc.
+ +  * Copyright (C) 2008-2010 Nokia Corporation
+ +  *
+ +  * Derived from mach-omap2/clockdomain.c written by Paul Walmsley
+ +  * Rajendra Nayak <rnayak@ti.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #include <linux/kernel.h>
+ + #include "clockdomain.h"
+ + #include "cminst44xx.h"
+ + #include "cm44xx.h"
+ + 
+ + static int omap4_clkdm_sleep(struct clockdomain *clkdm)
+ + {
+ + 	omap4_cminst_clkdm_force_sleep(clkdm->prcm_partition,
+ + 					clkdm->cm_inst, clkdm->clkdm_offs);
+ + 	return 0;
+ + }
+ + 
+ + static int omap4_clkdm_wakeup(struct clockdomain *clkdm)
+ + {
+ + 	omap4_cminst_clkdm_force_wakeup(clkdm->prcm_partition,
+ + 					clkdm->cm_inst, clkdm->clkdm_offs);
+ + 	return 0;
+ + }
+ + 
+ + 
+ + static int omap4_clkdm_clk_enable(struct clockdomain *clkdm)
+ + {
+ + 	if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
+ + 		return omap4_clkdm_wakeup(clkdm);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static int omap4_clkdm_clk_disable(struct clockdomain *clkdm)
+ + {
+ + 	bool hwsup = false;
+ + 
+ + 	hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
+ + 					clkdm->cm_inst, clkdm->clkdm_offs);
+ + 
+ + 	if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP))
+ + 		omap4_clkdm_sleep(clkdm);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + struct clkdm_ops am33xx_clkdm_operations = {
+ + 	.clkdm_sleep		= omap4_clkdm_sleep,
+ + 	.clkdm_wakeup		= omap4_clkdm_wakeup,
+ + 	.clkdm_clk_enable	= omap4_clkdm_clk_enable,
+ + 	.clkdm_clk_disable	= omap4_clkdm_clk_disable,
+ + };
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/clockdomain.c linux-3.2.1/arch/arm/mach-ckb_3352/clockdomain.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/clockdomain.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/clockdomain.c	2014-11-25 13:19:14.860948680 +0900
+ ***************
+ *** 0 ****
+ --- 1,1012 ----
+ + /*
+ +  * OMAP2/3/4 clockdomain framework functions
+ +  *
+ +  * Copyright (C) 2008-2011 Texas Instruments, Inc.
+ +  * Copyright (C) 2008-2011 Nokia Corporation
+ +  *
+ +  * Written by Paul Walmsley and Jouni Högander
+ +  * Added OMAP4 specific support by Abhijit Pagare <abhijitpagare@ti.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + #undef DEBUG
+ + 
+ + #include <linux/kernel.h>
+ + #include <linux/device.h>
+ + #include <linux/list.h>
+ + #include <linux/errno.h>
+ + #include <linux/string.h>
+ + #include <linux/delay.h>
+ + #include <linux/clk.h>
+ + #include <linux/limits.h>
+ + #include <linux/err.h>
+ + 
+ + #include <linux/io.h>
+ + 
+ + #include <linux/bitops.h>
+ + 
+ + #include <plat/clock.h>
+ + #include "clockdomain.h"
+ + 
+ + /* clkdm_list contains all registered struct clockdomains */
+ + static LIST_HEAD(clkdm_list);
+ + 
+ + /* array of clockdomain deps to be added/removed when clkdm in hwsup mode */
+ + static struct clkdm_autodep *autodeps;
+ + 
+ + static struct clkdm_ops *arch_clkdm;
+ + 
+ + /* Private functions */
+ + 
+ + static struct clockdomain *_clkdm_lookup(const char *name)
+ + {
+ + 	struct clockdomain *clkdm, *temp_clkdm;
+ + 
+ + 	if (!name)
+ + 		return NULL;
+ + 
+ + 	clkdm = NULL;
+ + 
+ + 	list_for_each_entry(temp_clkdm, &clkdm_list, node) {
+ + 		if (!strcmp(name, temp_clkdm->name)) {
+ + 			clkdm = temp_clkdm;
+ + 			break;
+ + 		}
+ + 	}
+ + 
+ + 	return clkdm;
+ + }
+ + 
+ + /**
+ +  * _clkdm_register - register a clockdomain
+ +  * @clkdm: struct clockdomain * to register
+ +  *
+ +  * Adds a clockdomain to the internal clockdomain list.
+ +  * Returns -EINVAL if given a null pointer, -EEXIST if a clockdomain is
+ +  * already registered by the provided name, or 0 upon success.
+ +  */
+ + static int _clkdm_register(struct clockdomain *clkdm)
+ + {
+ + 	struct powerdomain *pwrdm;
+ + 
+ + 	if (!clkdm || !clkdm->name)
+ + 		return -EINVAL;
+ + 
+ + 	pwrdm = pwrdm_lookup(clkdm->pwrdm.name);
+ + 	if (!pwrdm) {
+ + 		pr_err("clockdomain: %s: powerdomain %s does not exist\n",
+ + 			clkdm->name, clkdm->pwrdm.name);
+ + 		return -EINVAL;
+ + 	}
+ + 	clkdm->pwrdm.ptr = pwrdm;
+ + 
+ + 	/* Verify that the clockdomain is not already registered */
+ + 	if (_clkdm_lookup(clkdm->name))
+ + 		return -EEXIST;
+ + 
+ + 	list_add(&clkdm->node, &clkdm_list);
+ + 
+ + 	pwrdm_add_clkdm(pwrdm, clkdm);
+ + 
+ + 	spin_lock_init(&clkdm->lock);
+ + 
+ + 	pr_debug("clockdomain: registered %s\n", clkdm->name);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /* _clkdm_deps_lookup - look up the specified clockdomain in a clkdm list */
+ + static struct clkdm_dep *_clkdm_deps_lookup(struct clockdomain *clkdm,
+ + 					    struct clkdm_dep *deps)
+ + {
+ + 	struct clkdm_dep *cd;
+ + 
+ + 	if (!clkdm || !deps)
+ + 		return ERR_PTR(-EINVAL);
+ + 
+ + 	for (cd = deps; cd->clkdm_name; cd++) {
+ + 		if (!cd->clkdm && cd->clkdm_name)
+ + 			cd->clkdm = _clkdm_lookup(cd->clkdm_name);
+ + 
+ + 		if (cd->clkdm == clkdm)
+ + 			break;
+ + 	}
+ + 
+ + 	if (!cd->clkdm_name)
+ + 		return ERR_PTR(-ENOENT);
+ + 
+ + 	return cd;
+ + }
+ + 
+ + /*
+ +  * _autodep_lookup - resolve autodep clkdm names to clkdm pointers; store
+ +  * @autodep: struct clkdm_autodep * to resolve
+ +  *
+ +  * Resolve autodep clockdomain names to clockdomain pointers via
+ +  * clkdm_lookup() and store the pointers in the autodep structure.  An
+ +  * "autodep" is a clockdomain sleep/wakeup dependency that is
+ +  * automatically added and removed whenever clocks in the associated
+ +  * clockdomain are enabled or disabled (respectively) when the
+ +  * clockdomain is in hardware-supervised mode.	Meant to be called
+ +  * once at clockdomain layer initialization, since these should remain
+ +  * fixed for a particular architecture.  No return value.
+ +  *
+ +  * XXX autodeps are deprecated and should be removed at the earliest
+ +  * opportunity
+ +  */
+ + static void _autodep_lookup(struct clkdm_autodep *autodep)
+ + {
+ + 	struct clockdomain *clkdm;
+ + 
+ + 	if (!autodep)
+ + 		return;
+ + 
+ + 	clkdm = clkdm_lookup(autodep->clkdm.name);
+ + 	if (!clkdm) {
+ + 		pr_err("clockdomain: autodeps: clockdomain %s does not exist\n",
+ + 			 autodep->clkdm.name);
+ + 		clkdm = ERR_PTR(-ENOENT);
+ + 	}
+ + 	autodep->clkdm.ptr = clkdm;
+ + }
+ + 
+ + /*
+ +  * _clkdm_add_autodeps - add auto sleepdeps/wkdeps to clkdm upon clock enable
+ +  * @clkdm: struct clockdomain *
+ +  *
+ +  * Add the "autodep" sleep & wakeup dependencies to clockdomain 'clkdm'
+ +  * in hardware-supervised mode.  Meant to be called from clock framework
+ +  * when a clock inside clockdomain 'clkdm' is enabled.	No return value.
+ +  *
+ +  * XXX autodeps are deprecated and should be removed at the earliest
+ +  * opportunity
+ +  */
+ + void _clkdm_add_autodeps(struct clockdomain *clkdm)
+ + {
+ + 	struct clkdm_autodep *autodep;
+ + 
+ + 	if (!autodeps || clkdm->flags & CLKDM_NO_AUTODEPS)
+ + 		return;
+ + 
+ + 	for (autodep = autodeps; autodep->clkdm.ptr; autodep++) {
+ + 		if (IS_ERR(autodep->clkdm.ptr))
+ + 			continue;
+ + 
+ + 		pr_debug("clockdomain: adding %s sleepdep/wkdep for "
+ + 			 "clkdm %s\n", autodep->clkdm.ptr->name,
+ + 			 clkdm->name);
+ + 
+ + 		clkdm_add_sleepdep(clkdm, autodep->clkdm.ptr);
+ + 		clkdm_add_wkdep(clkdm, autodep->clkdm.ptr);
+ + 	}
+ + }
+ + 
+ + /*
+ +  * _clkdm_add_autodeps - remove auto sleepdeps/wkdeps from clkdm
+ +  * @clkdm: struct clockdomain *
+ +  *
+ +  * Remove the "autodep" sleep & wakeup dependencies from clockdomain 'clkdm'
+ +  * in hardware-supervised mode.  Meant to be called from clock framework
+ +  * when a clock inside clockdomain 'clkdm' is disabled.  No return value.
+ +  *
+ +  * XXX autodeps are deprecated and should be removed at the earliest
+ +  * opportunity
+ +  */
+ + void _clkdm_del_autodeps(struct clockdomain *clkdm)
+ + {
+ + 	struct clkdm_autodep *autodep;
+ + 
+ + 	if (!autodeps || clkdm->flags & CLKDM_NO_AUTODEPS)
+ + 		return;
+ + 
+ + 	for (autodep = autodeps; autodep->clkdm.ptr; autodep++) {
+ + 		if (IS_ERR(autodep->clkdm.ptr))
+ + 			continue;
+ + 
+ + 		pr_debug("clockdomain: removing %s sleepdep/wkdep for "
+ + 			 "clkdm %s\n", autodep->clkdm.ptr->name,
+ + 			 clkdm->name);
+ + 
+ + 		clkdm_del_sleepdep(clkdm, autodep->clkdm.ptr);
+ + 		clkdm_del_wkdep(clkdm, autodep->clkdm.ptr);
+ + 	}
+ + }
+ + 
+ + /**
+ +  * _resolve_clkdm_deps() - resolve clkdm_names in @clkdm_deps to clkdms
+ +  * @clkdm: clockdomain that we are resolving dependencies for
+ +  * @clkdm_deps: ptr to array of struct clkdm_deps to resolve
+ +  *
+ +  * Iterates through @clkdm_deps, looking up the struct clockdomain named by
+ +  * clkdm_name and storing the clockdomain pointer in the struct clkdm_dep.
+ +  * No return value.
+ +  */
+ + static void _resolve_clkdm_deps(struct clockdomain *clkdm,
+ + 				struct clkdm_dep *clkdm_deps)
+ + {
+ + 	struct clkdm_dep *cd;
+ + 
+ + 	for (cd = clkdm_deps; cd && cd->clkdm_name; cd++) {
+ + 		if (cd->clkdm)
+ + 			continue;
+ + 		cd->clkdm = _clkdm_lookup(cd->clkdm_name);
+ + 
+ + 		WARN(!cd->clkdm, "clockdomain: %s: could not find clkdm %s while resolving dependencies - should never happen",
+ + 		     clkdm->name, cd->clkdm_name);
+ + 	}
+ + }
+ + 
+ + /* Public functions */
+ + 
+ + /**
+ +  * clkdm_register_platform_funcs - register clockdomain implementation fns
+ +  * @co: func pointers for arch specific implementations
+ +  *
+ +  * Register the list of function pointers used to implement the
+ +  * clockdomain functions on different OMAP SoCs.  Should be called
+ +  * before any other clkdm_register*() function.  Returns -EINVAL if
+ +  * @co is null, -EEXIST if platform functions have already been
+ +  * registered, or 0 upon success.
+ +  */
+ + int clkdm_register_platform_funcs(struct clkdm_ops *co)
+ + {
+ + 	if (!co)
+ + 		return -EINVAL;
+ + 
+ + 	if (arch_clkdm)
+ + 		return -EEXIST;
+ + 
+ + 	arch_clkdm = co;
+ + 
+ + 	return 0;
+ + };
+ + 
+ + /**
+ +  * clkdm_register_clkdms - register SoC clockdomains
+ +  * @cs: pointer to an array of struct clockdomain to register
+ +  *
+ +  * Register the clockdomains available on a particular OMAP SoC.  Must
+ +  * be called after clkdm_register_platform_funcs().  May be called
+ +  * multiple times.  Returns -EACCES if called before
+ +  * clkdm_register_platform_funcs(); -EINVAL if the argument @cs is
+ +  * null; or 0 upon success.
+ +  */
+ + int clkdm_register_clkdms(struct clockdomain **cs)
+ + {
+ + 	struct clockdomain **c = NULL;
+ + 
+ + 	if (!arch_clkdm)
+ + 		return -EACCES;
+ + 
+ + 	if (!cs)
+ + 		return -EINVAL;
+ + 
+ + 	for (c = cs; *c; c++)
+ + 		_clkdm_register(*c);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * clkdm_register_autodeps - register autodeps (if required)
+ +  * @ia: pointer to a static array of struct clkdm_autodep to register
+ +  *
+ +  * Register clockdomain "automatic dependencies."  These are
+ +  * clockdomain wakeup and sleep dependencies that are automatically
+ +  * added whenever the first clock inside a clockdomain is enabled, and
+ +  * removed whenever the last clock inside a clockdomain is disabled.
+ +  * These are currently only used on OMAP3 devices, and are deprecated,
+ +  * since they waste energy.  However, until the OMAP2/3 IP block
+ +  * enable/disable sequence can be converted to match the OMAP4
+ +  * sequence, they are needed.
+ +  *
+ +  * Must be called only after all of the SoC clockdomains are
+ +  * registered, since the function will resolve autodep clockdomain
+ +  * names into clockdomain pointers.
+ +  *
+ +  * The struct clkdm_autodep @ia array must be static, as this function
+ +  * does not copy the array elements.
+ +  *
+ +  * Returns -EACCES if called before any clockdomains have been
+ +  * registered, -EINVAL if called with a null @ia argument, -EEXIST if
+ +  * autodeps have already been registered, or 0 upon success.
+ +  */
+ + int clkdm_register_autodeps(struct clkdm_autodep *ia)
+ + {
+ + 	struct clkdm_autodep *a = NULL;
+ + 
+ + 	if (list_empty(&clkdm_list))
+ + 		return -EACCES;
+ + 
+ + 	if (!ia)
+ + 		return -EINVAL;
+ + 
+ + 	if (autodeps)
+ + 		return -EEXIST;
+ + 
+ + 	autodeps = ia;
+ + 	for (a = autodeps; a->clkdm.ptr; a++)
+ + 		_autodep_lookup(a);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * clkdm_complete_init - set up the clockdomain layer
+ +  *
+ +  * Put all clockdomains into software-supervised mode; PM code should
+ +  * later enable hardware-supervised mode as appropriate.  Must be
+ +  * called after clkdm_register_clkdms().  Returns -EACCES if called
+ +  * before clkdm_register_clkdms(), or 0 upon success.
+ +  */
+ + int clkdm_complete_init(void)
+ + {
+ + 	struct clockdomain *clkdm;
+ + 
+ + 	if (list_empty(&clkdm_list))
+ + 		return -EACCES;
+ + 
+ + 	list_for_each_entry(clkdm, &clkdm_list, node) {
+ + 		if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
+ + 			clkdm_wakeup(clkdm);
+ + 		else if (clkdm->flags & CLKDM_CAN_DISABLE_AUTO)
+ + 			clkdm_deny_idle(clkdm);
+ + 
+ + 		_resolve_clkdm_deps(clkdm, clkdm->wkdep_srcs);
+ + 		clkdm_clear_all_wkdeps(clkdm);
+ + 
+ + 		_resolve_clkdm_deps(clkdm, clkdm->sleepdep_srcs);
+ + 		clkdm_clear_all_sleepdeps(clkdm);
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * clkdm_lookup - look up a clockdomain by name, return a pointer
+ +  * @name: name of clockdomain
+ +  *
+ +  * Find a registered clockdomain by its name @name.  Returns a pointer
+ +  * to the struct clockdomain if found, or NULL otherwise.
+ +  */
+ + struct clockdomain *clkdm_lookup(const char *name)
+ + {
+ + 	struct clockdomain *clkdm, *temp_clkdm;
+ + 
+ + 	if (!name)
+ + 		return NULL;
+ + 
+ + 	clkdm = NULL;
+ + 
+ + 	list_for_each_entry(temp_clkdm, &clkdm_list, node) {
+ + 		if (!strcmp(name, temp_clkdm->name)) {
+ + 			clkdm = temp_clkdm;
+ + 			break;
+ + 		}
+ + 	}
+ + 
+ + 	return clkdm;
+ + }
+ + 
+ + /**
+ +  * clkdm_for_each - call function on each registered clockdomain
+ +  * @fn: callback function *
+ +  *
+ +  * Call the supplied function @fn for each registered clockdomain.
+ +  * The callback function @fn can return anything but 0 to bail
+ +  * out early from the iterator.  The callback function is called with
+ +  * the clkdm_mutex held, so no clockdomain structure manipulation
+ +  * functions should be called from the callback, although hardware
+ +  * clockdomain control functions are fine.  Returns the last return
+ +  * value of the callback function, which should be 0 for success or
+ +  * anything else to indicate failure; or -EINVAL if the function pointer
+ +  * is null.
+ +  */
+ + int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user),
+ + 			void *user)
+ + {
+ + 	struct clockdomain *clkdm;
+ + 	int ret = 0;
+ + 
+ + 	if (!fn)
+ + 		return -EINVAL;
+ + 
+ + 	list_for_each_entry(clkdm, &clkdm_list, node) {
+ + 		ret = (*fn)(clkdm, user);
+ + 		if (ret)
+ + 			break;
+ + 	}
+ + 
+ + 	return ret;
+ + }
+ + 
+ + 
+ + /**
+ +  * clkdm_get_pwrdm - return a ptr to the pwrdm that this clkdm resides in
+ +  * @clkdm: struct clockdomain *
+ +  *
+ +  * Return a pointer to the struct powerdomain that the specified clockdomain
+ +  * @clkdm exists in, or returns NULL if @clkdm is NULL.
+ +  */
+ + struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm)
+ + {
+ + 	if (!clkdm)
+ + 		return NULL;
+ + 
+ + 	return clkdm->pwrdm.ptr;
+ + }
+ + 
+ + 
+ + /* Hardware clockdomain control */
+ + 
+ + /**
+ +  * clkdm_add_wkdep - add a wakeup dependency from clkdm2 to clkdm1
+ +  * @clkdm1: wake this struct clockdomain * up (dependent)
+ +  * @clkdm2: when this struct clockdomain * wakes up (source)
+ +  *
+ +  * When the clockdomain represented by @clkdm2 wakes up, wake up
+ +  * @clkdm1. Implemented in hardware on the OMAP, this feature is
+ +  * designed to reduce wakeup latency of the dependent clockdomain @clkdm1.
+ +  * Returns -EINVAL if presented with invalid clockdomain pointers,
+ +  * -ENOENT if @clkdm2 cannot wake up clkdm1 in hardware, or 0 upon
+ +  * success.
+ +  */
+ + int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
+ + {
+ + 	struct clkdm_dep *cd;
+ + 	int ret = 0;
+ + 
+ + 	if (!clkdm1 || !clkdm2)
+ + 		return -EINVAL;
+ + 
+ + 	cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
+ + 	if (IS_ERR(cd))
+ + 		ret = PTR_ERR(cd);
+ + 
+ + 	if (!arch_clkdm || !arch_clkdm->clkdm_add_wkdep)
+ + 		ret = -EINVAL;
+ + 
+ + 	if (ret) {
+ + 		pr_debug("clockdomain: hardware cannot set/clear wake up of "
+ + 			 "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
+ + 		return ret;
+ + 	}
+ + 
+ + 	if (atomic_inc_return(&cd->wkdep_usecount) == 1) {
+ + 		pr_debug("clockdomain: hardware will wake up %s when %s wakes "
+ + 			 "up\n", clkdm1->name, clkdm2->name);
+ + 
+ + 		ret = arch_clkdm->clkdm_add_wkdep(clkdm1, clkdm2);
+ + 	}
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * clkdm_del_wkdep - remove a wakeup dependency from clkdm2 to clkdm1
+ +  * @clkdm1: wake this struct clockdomain * up (dependent)
+ +  * @clkdm2: when this struct clockdomain * wakes up (source)
+ +  *
+ +  * Remove a wakeup dependency causing @clkdm1 to wake up when @clkdm2
+ +  * wakes up.  Returns -EINVAL if presented with invalid clockdomain
+ +  * pointers, -ENOENT if @clkdm2 cannot wake up clkdm1 in hardware, or
+ +  * 0 upon success.
+ +  */
+ + int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
+ + {
+ + 	struct clkdm_dep *cd;
+ + 	int ret = 0;
+ + 
+ + 	if (!clkdm1 || !clkdm2)
+ + 		return -EINVAL;
+ + 
+ + 	cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
+ + 	if (IS_ERR(cd))
+ + 		ret = PTR_ERR(cd);
+ + 
+ + 	if (!arch_clkdm || !arch_clkdm->clkdm_del_wkdep)
+ + 		ret = -EINVAL;
+ + 
+ + 	if (ret) {
+ + 		pr_debug("clockdomain: hardware cannot set/clear wake up of "
+ + 			 "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
+ + 		return ret;
+ + 	}
+ + 
+ + 	if (atomic_dec_return(&cd->wkdep_usecount) == 0) {
+ + 		pr_debug("clockdomain: hardware will no longer wake up %s "
+ + 			 "after %s wakes up\n", clkdm1->name, clkdm2->name);
+ + 
+ + 		ret = arch_clkdm->clkdm_del_wkdep(clkdm1, clkdm2);
+ + 	}
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * clkdm_read_wkdep - read wakeup dependency state from clkdm2 to clkdm1
+ +  * @clkdm1: wake this struct clockdomain * up (dependent)
+ +  * @clkdm2: when this struct clockdomain * wakes up (source)
+ +  *
+ +  * Return 1 if a hardware wakeup dependency exists wherein @clkdm1 will be
+ +  * awoken when @clkdm2 wakes up; 0 if dependency is not set; -EINVAL
+ +  * if either clockdomain pointer is invalid; or -ENOENT if the hardware
+ +  * is incapable.
+ +  *
+ +  * REVISIT: Currently this function only represents software-controllable
+ +  * wakeup dependencies.  Wakeup dependencies fixed in hardware are not
+ +  * yet handled here.
+ +  */
+ + int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
+ + {
+ + 	struct clkdm_dep *cd;
+ + 	int ret = 0;
+ + 
+ + 	if (!clkdm1 || !clkdm2)
+ + 		return -EINVAL;
+ + 
+ + 	cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
+ + 	if (IS_ERR(cd))
+ + 		ret = PTR_ERR(cd);
+ + 
+ + 	if (!arch_clkdm || !arch_clkdm->clkdm_read_wkdep)
+ + 		ret = -EINVAL;
+ + 
+ + 	if (ret) {
+ + 		pr_debug("clockdomain: hardware cannot set/clear wake up of "
+ + 			 "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
+ + 		return ret;
+ + 	}
+ + 
+ + 	/* XXX It's faster to return the atomic wkdep_usecount */
+ + 	return arch_clkdm->clkdm_read_wkdep(clkdm1, clkdm2);
+ + }
+ + 
+ + /**
+ +  * clkdm_clear_all_wkdeps - remove all wakeup dependencies from target clkdm
+ +  * @clkdm: struct clockdomain * to remove all wakeup dependencies from
+ +  *
+ +  * Remove all inter-clockdomain wakeup dependencies that could cause
+ +  * @clkdm to wake.  Intended to be used during boot to initialize the
+ +  * PRCM to a known state, after all clockdomains are put into swsup idle
+ +  * and woken up.  Returns -EINVAL if @clkdm pointer is invalid, or
+ +  * 0 upon success.
+ +  */
+ + int clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
+ + {
+ + 	if (!clkdm)
+ + 		return -EINVAL;
+ + 
+ + 	if (!arch_clkdm || !arch_clkdm->clkdm_clear_all_wkdeps)
+ + 		return -EINVAL;
+ + 
+ + 	return arch_clkdm->clkdm_clear_all_wkdeps(clkdm);
+ + }
+ + 
+ + /**
+ +  * clkdm_add_sleepdep - add a sleep dependency from clkdm2 to clkdm1
+ +  * @clkdm1: prevent this struct clockdomain * from sleeping (dependent)
+ +  * @clkdm2: when this struct clockdomain * is active (source)
+ +  *
+ +  * Prevent @clkdm1 from automatically going inactive (and then to
+ +  * retention or off) if @clkdm2 is active.  Returns -EINVAL if
+ +  * presented with invalid clockdomain pointers or called on a machine
+ +  * that does not support software-configurable hardware sleep
+ +  * dependencies, -ENOENT if the specified dependency cannot be set in
+ +  * hardware, or 0 upon success.
+ +  */
+ + int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
+ + {
+ + 	struct clkdm_dep *cd;
+ + 	int ret = 0;
+ + 
+ + 	if (!clkdm1 || !clkdm2)
+ + 		return -EINVAL;
+ + 
+ + 	cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs);
+ + 	if (IS_ERR(cd))
+ + 		ret = PTR_ERR(cd);
+ + 
+ + 	if (!arch_clkdm || !arch_clkdm->clkdm_add_sleepdep)
+ + 		ret = -EINVAL;
+ + 
+ + 	if (ret) {
+ + 		pr_debug("clockdomain: hardware cannot set/clear sleep "
+ + 			 "dependency affecting %s from %s\n", clkdm1->name,
+ + 			 clkdm2->name);
+ + 		return ret;
+ + 	}
+ + 
+ + 	if (atomic_inc_return(&cd->sleepdep_usecount) == 1) {
+ + 		pr_debug("clockdomain: will prevent %s from sleeping if %s "
+ + 			 "is active\n", clkdm1->name, clkdm2->name);
+ + 
+ + 		ret = arch_clkdm->clkdm_add_sleepdep(clkdm1, clkdm2);
+ + 	}
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * clkdm_del_sleepdep - remove a sleep dependency from clkdm2 to clkdm1
+ +  * @clkdm1: prevent this struct clockdomain * from sleeping (dependent)
+ +  * @clkdm2: when this struct clockdomain * is active (source)
+ +  *
+ +  * Allow @clkdm1 to automatically go inactive (and then to retention or
+ +  * off), independent of the activity state of @clkdm2.  Returns -EINVAL
+ +  * if presented with invalid clockdomain pointers or called on a machine
+ +  * that does not support software-configurable hardware sleep dependencies,
+ +  * -ENOENT if the specified dependency cannot be cleared in hardware, or
+ +  * 0 upon success.
+ +  */
+ + int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
+ + {
+ + 	struct clkdm_dep *cd;
+ + 	int ret = 0;
+ + 
+ + 	if (!clkdm1 || !clkdm2)
+ + 		return -EINVAL;
+ + 
+ + 	cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs);
+ + 	if (IS_ERR(cd))
+ + 		ret = PTR_ERR(cd);
+ + 
+ + 	if (!arch_clkdm || !arch_clkdm->clkdm_del_sleepdep)
+ + 		ret = -EINVAL;
+ + 
+ + 	if (ret) {
+ + 		pr_debug("clockdomain: hardware cannot set/clear sleep "
+ + 			 "dependency affecting %s from %s\n", clkdm1->name,
+ + 			 clkdm2->name);
+ + 		return ret;
+ + 	}
+ + 
+ + 	if (atomic_dec_return(&cd->sleepdep_usecount) == 0) {
+ + 		pr_debug("clockdomain: will no longer prevent %s from "
+ + 			 "sleeping if %s is active\n", clkdm1->name,
+ + 			 clkdm2->name);
+ + 
+ + 		ret = arch_clkdm->clkdm_del_sleepdep(clkdm1, clkdm2);
+ + 	}
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * clkdm_read_sleepdep - read sleep dependency state from clkdm2 to clkdm1
+ +  * @clkdm1: prevent this struct clockdomain * from sleeping (dependent)
+ +  * @clkdm2: when this struct clockdomain * is active (source)
+ +  *
+ +  * Return 1 if a hardware sleep dependency exists wherein @clkdm1 will
+ +  * not be allowed to automatically go inactive if @clkdm2 is active;
+ +  * 0 if @clkdm1's automatic power state inactivity transition is independent
+ +  * of @clkdm2's; -EINVAL if either clockdomain pointer is invalid or called
+ +  * on a machine that does not support software-configurable hardware sleep
+ +  * dependencies; or -ENOENT if the hardware is incapable.
+ +  *
+ +  * REVISIT: Currently this function only represents software-controllable
+ +  * sleep dependencies.	Sleep dependencies fixed in hardware are not
+ +  * yet handled here.
+ +  */
+ + int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
+ + {
+ + 	struct clkdm_dep *cd;
+ + 	int ret = 0;
+ + 
+ + 	if (!clkdm1 || !clkdm2)
+ + 		return -EINVAL;
+ + 
+ + 	cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs);
+ + 	if (IS_ERR(cd))
+ + 		ret = PTR_ERR(cd);
+ + 
+ + 	if (!arch_clkdm || !arch_clkdm->clkdm_read_sleepdep)
+ + 		ret = -EINVAL;
+ + 
+ + 	if (ret) {
+ + 		pr_debug("clockdomain: hardware cannot set/clear sleep "
+ + 			 "dependency affecting %s from %s\n", clkdm1->name,
+ + 			 clkdm2->name);
+ + 		return ret;
+ + 	}
+ + 
+ + 	/* XXX It's faster to return the atomic sleepdep_usecount */
+ + 	return arch_clkdm->clkdm_read_sleepdep(clkdm1, clkdm2);
+ + }
+ + 
+ + /**
+ +  * clkdm_clear_all_sleepdeps - remove all sleep dependencies from target clkdm
+ +  * @clkdm: struct clockdomain * to remove all sleep dependencies from
+ +  *
+ +  * Remove all inter-clockdomain sleep dependencies that could prevent
+ +  * @clkdm from idling.  Intended to be used during boot to initialize the
+ +  * PRCM to a known state, after all clockdomains are put into swsup idle
+ +  * and woken up.  Returns -EINVAL if @clkdm pointer is invalid, or
+ +  * 0 upon success.
+ +  */
+ + int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
+ + {
+ + 	if (!clkdm)
+ + 		return -EINVAL;
+ + 
+ + 	if (!arch_clkdm || !arch_clkdm->clkdm_clear_all_sleepdeps)
+ + 		return -EINVAL;
+ + 
+ + 	return arch_clkdm->clkdm_clear_all_sleepdeps(clkdm);
+ + }
+ + 
+ + /**
+ +  * clkdm_sleep - force clockdomain sleep transition
+ +  * @clkdm: struct clockdomain *
+ +  *
+ +  * Instruct the CM to force a sleep transition on the specified
+ +  * clockdomain @clkdm.  Returns -EINVAL if @clkdm is NULL or if
+ +  * clockdomain does not support software-initiated sleep; 0 upon
+ +  * success.
+ +  */
+ + int clkdm_sleep(struct clockdomain *clkdm)
+ + {
+ + 	int ret;
+ + 	unsigned long flags;
+ + 
+ + 	if (!clkdm)
+ + 		return -EINVAL;
+ + 
+ + 	if (!(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
+ + 		pr_debug("clockdomain: %s does not support forcing "
+ + 			 "sleep via software\n", clkdm->name);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	if (!arch_clkdm || !arch_clkdm->clkdm_sleep)
+ + 		return -EINVAL;
+ + 
+ + 	pr_debug("clockdomain: forcing sleep on %s\n", clkdm->name);
+ + 
+ + 	spin_lock_irqsave(&clkdm->lock, flags);
+ + 	clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
+ + 	ret = arch_clkdm->clkdm_sleep(clkdm);
+ + 	spin_unlock_irqrestore(&clkdm->lock, flags);
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * clkdm_wakeup - force clockdomain wakeup transition
+ +  * @clkdm: struct clockdomain *
+ +  *
+ +  * Instruct the CM to force a wakeup transition on the specified
+ +  * clockdomain @clkdm.  Returns -EINVAL if @clkdm is NULL or if the
+ +  * clockdomain does not support software-controlled wakeup; 0 upon
+ +  * success.
+ +  */
+ + int clkdm_wakeup(struct clockdomain *clkdm)
+ + {
+ + 	int ret;
+ + 	unsigned long flags;
+ + 
+ + 	if (!clkdm)
+ + 		return -EINVAL;
+ + 
+ + 	if (!(clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) {
+ + 		pr_debug("clockdomain: %s does not support forcing "
+ + 			 "wakeup via software\n", clkdm->name);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	if (!arch_clkdm || !arch_clkdm->clkdm_wakeup)
+ + 		return -EINVAL;
+ + 
+ + 	pr_debug("clockdomain: forcing wakeup on %s\n", clkdm->name);
+ + 
+ + 	spin_lock_irqsave(&clkdm->lock, flags);
+ + 	clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
+ + 	ret = arch_clkdm->clkdm_wakeup(clkdm);
+ + 	ret |= pwrdm_state_switch(clkdm->pwrdm.ptr);
+ + 	spin_unlock_irqrestore(&clkdm->lock, flags);
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * clkdm_allow_idle - enable hwsup idle transitions for clkdm
+ +  * @clkdm: struct clockdomain *
+ +  *
+ +  * Allow the hardware to automatically switch the clockdomain @clkdm into
+ +  * active or idle states, as needed by downstream clocks.  If the
+ +  * clockdomain has any downstream clocks enabled in the clock
+ +  * framework, wkdep/sleepdep autodependencies are added; this is so
+ +  * device drivers can read and write to the device.  No return value.
+ +  */
+ + void clkdm_allow_idle(struct clockdomain *clkdm)
+ + {
+ + 	unsigned long flags;
+ + 
+ + 	if (!clkdm)
+ + 		return;
+ + 
+ + 	if (!(clkdm->flags & CLKDM_CAN_ENABLE_AUTO)) {
+ + 		pr_debug("clock: automatic idle transitions cannot be enabled "
+ + 			 "on clockdomain %s\n", clkdm->name);
+ + 		return;
+ + 	}
+ + 
+ + 	if (!arch_clkdm || !arch_clkdm->clkdm_allow_idle)
+ + 		return;
+ + 
+ + 	pr_debug("clockdomain: enabling automatic idle transitions for %s\n",
+ + 		 clkdm->name);
+ + 
+ + 	spin_lock_irqsave(&clkdm->lock, flags);
+ + 	clkdm->_flags |= _CLKDM_FLAG_HWSUP_ENABLED;
+ + 	arch_clkdm->clkdm_allow_idle(clkdm);
+ + 	pwrdm_clkdm_state_switch(clkdm);
+ + 	spin_unlock_irqrestore(&clkdm->lock, flags);
+ + }
+ + 
+ + /**
+ +  * clkdm_deny_idle - disable hwsup idle transitions for clkdm
+ +  * @clkdm: struct clockdomain *
+ +  *
+ +  * Prevent the hardware from automatically switching the clockdomain
+ +  * @clkdm into inactive or idle states.  If the clockdomain has
+ +  * downstream clocks enabled in the clock framework, wkdep/sleepdep
+ +  * autodependencies are removed.  No return value.
+ +  */
+ + void clkdm_deny_idle(struct clockdomain *clkdm)
+ + {
+ + 	unsigned long flags;
+ + 
+ + 	if (!clkdm)
+ + 		return;
+ + 
+ + 	if (!(clkdm->flags & CLKDM_CAN_DISABLE_AUTO)) {
+ + 		pr_debug("clockdomain: automatic idle transitions cannot be "
+ + 			 "disabled on %s\n", clkdm->name);
+ + 		return;
+ + 	}
+ + 
+ + 	if (!arch_clkdm || !arch_clkdm->clkdm_deny_idle)
+ + 		return;
+ + 
+ + 	pr_debug("clockdomain: disabling automatic idle transitions for %s\n",
+ + 		 clkdm->name);
+ + 
+ + 	spin_lock_irqsave(&clkdm->lock, flags);
+ + 	clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
+ + 	arch_clkdm->clkdm_deny_idle(clkdm);
+ + 	pwrdm_state_switch(clkdm->pwrdm.ptr);
+ + 	spin_unlock_irqrestore(&clkdm->lock, flags);
+ + }
+ + 
+ + /**
+ +  * clkdm_in_hwsup - is clockdomain @clkdm have hardware-supervised idle enabled?
+ +  * @clkdm: struct clockdomain *
+ +  *
+ +  * Returns true if clockdomain @clkdm currently has
+ +  * hardware-supervised idle enabled, or false if it does not or if
+ +  * @clkdm is NULL.  It is only valid to call this function after
+ +  * clkdm_init() has been called.  This function does not actually read
+ +  * bits from the hardware; it instead tests an in-memory flag that is
+ +  * changed whenever the clockdomain code changes the auto-idle mode.
+ +  */
+ + bool clkdm_in_hwsup(struct clockdomain *clkdm)
+ + {
+ + 	bool ret;
+ + 	unsigned long flags;
+ + 
+ + 	if (!clkdm)
+ + 		return false;
+ + 
+ + 	spin_lock_irqsave(&clkdm->lock, flags);
+ + 	ret = (clkdm->_flags & _CLKDM_FLAG_HWSUP_ENABLED) ? true : false;
+ + 	spin_unlock_irqrestore(&clkdm->lock, flags);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /* Clockdomain-to-clock/hwmod framework interface code */
+ + 
+ + static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
+ + {
+ + 	unsigned long flags;
+ + 
+ + 	if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_enable)
+ + 		return -EINVAL;
+ + 
+ + 	/*
+ + 	 * For arch's with no autodeps, clkcm_clk_enable
+ + 	 * should be called for every clock instance or hwmod that is
+ + 	 * enabled, so the clkdm can be force woken up.
+ + 	 */
+ + 	if ((atomic_inc_return(&clkdm->usecount) > 1) && autodeps)
+ + 		return 0;
+ + 
+ + 	spin_lock_irqsave(&clkdm->lock, flags);
+ + 	arch_clkdm->clkdm_clk_enable(clkdm);
+ + 	pwrdm_wait_transition(clkdm->pwrdm.ptr);
+ + 	pwrdm_clkdm_state_switch(clkdm);
+ + 	spin_unlock_irqrestore(&clkdm->lock, flags);
+ + 
+ + 	pr_debug("clockdomain: clkdm %s: enabled\n", clkdm->name);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm)
+ + {
+ + 	unsigned long flags;
+ + 
+ + 	if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
+ + 		return -EINVAL;
+ + 
+ + 	if (atomic_read(&clkdm->usecount) == 0) {
+ + 		WARN_ON(1); /* underflow */
+ + 		return -ERANGE;
+ + 	}
+ + 
+ + 	if (atomic_dec_return(&clkdm->usecount) > 0)
+ + 		return 0;
+ + 
+ + 	spin_lock_irqsave(&clkdm->lock, flags);
+ + 	arch_clkdm->clkdm_clk_disable(clkdm);
+ + 	pwrdm_clkdm_state_switch(clkdm);
+ + 	spin_unlock_irqrestore(&clkdm->lock, flags);
+ + 
+ + 	pr_debug("clockdomain: clkdm %s: disabled\n", clkdm->name);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * clkdm_clk_enable - add an enabled downstream clock to this clkdm
+ +  * @clkdm: struct clockdomain *
+ +  * @clk: struct clk * of the enabled downstream clock
+ +  *
+ +  * Increment the usecount of the clockdomain @clkdm and ensure that it
+ +  * is awake before @clk is enabled.  Intended to be called by
+ +  * clk_enable() code.  If the clockdomain is in software-supervised
+ +  * idle mode, force the clockdomain to wake.  If the clockdomain is in
+ +  * hardware-supervised idle mode, add clkdm-pwrdm autodependencies, to
+ +  * ensure that devices in the clockdomain can be read from/written to
+ +  * by on-chip processors.  Returns -EINVAL if passed null pointers;
+ +  * returns 0 upon success or if the clockdomain is in hwsup idle mode.
+ +  */
+ + int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
+ + {
+ + 	/*
+ + 	 * XXX Rewrite this code to maintain a list of enabled
+ + 	 * downstream clocks for debugging purposes?
+ + 	 */
+ + 
+ + 	if (!clk)
+ + 		return -EINVAL;
+ + 
+ + 	return _clkdm_clk_hwmod_enable(clkdm);
+ + }
+ + 
+ + /**
+ +  * clkdm_clk_disable - remove an enabled downstream clock from this clkdm
+ +  * @clkdm: struct clockdomain *
+ +  * @clk: struct clk * of the disabled downstream clock
+ +  *
+ +  * Decrement the usecount of this clockdomain @clkdm when @clk is
+ +  * disabled.  Intended to be called by clk_disable() code.  If the
+ +  * clockdomain usecount goes to 0, put the clockdomain to sleep
+ +  * (software-supervised mode) or remove the clkdm autodependencies
+ +  * (hardware-supervised mode).  Returns -EINVAL if passed null
+ +  * pointers; -ERANGE if the @clkdm usecount underflows; or returns 0
+ +  * upon success or if the clockdomain is in hwsup idle mode.
+ +  */
+ + int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
+ + {
+ + 	/*
+ + 	 * XXX Rewrite this code to maintain a list of enabled
+ + 	 * downstream clocks for debugging purposes?
+ + 	 */
+ + 
+ + 	if (!clk)
+ + 		return -EINVAL;
+ + 
+ + 	return _clkdm_clk_hwmod_disable(clkdm);
+ + }
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/clockdomain.h linux-3.2.1/arch/arm/mach-ckb_3352/clockdomain.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/clockdomain.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/clockdomain.h	2014-11-25 13:19:14.860948680 +0900
+ ***************
+ *** 0 ****
+ --- 1,210 ----
+ + /*
+ +  * arch/arm/plat-omap/include/mach/clockdomain.h
+ +  *
+ +  * OMAP2/3 clockdomain framework functions
+ +  *
+ +  * Copyright (C) 2008 Texas Instruments, Inc.
+ +  * Copyright (C) 2008-2011 Nokia Corporation
+ +  *
+ +  * Paul Walmsley
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAIN_H
+ + #define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAIN_H
+ + 
+ + #include <linux/init.h>
+ + #include <linux/spinlock.h>
+ + 
+ + #include "powerdomain.h"
+ + #include <plat/clock.h>
+ + #include <plat/omap_hwmod.h>
+ + #include <plat/cpu.h>
+ + 
+ + /*
+ +  * Clockdomain flags
+ +  *
+ +  * XXX Document CLKDM_CAN_* flags
+ +  *
+ +  * CLKDM_NO_AUTODEPS: Prevent "autodeps" from being added/removed from this
+ +  *     clockdomain.  (Currently, this applies to OMAP3 clockdomains only.)
+ +  */
+ + #define CLKDM_CAN_FORCE_SLEEP			(1 << 0)
+ + #define CLKDM_CAN_FORCE_WAKEUP			(1 << 1)
+ + #define CLKDM_CAN_ENABLE_AUTO			(1 << 2)
+ + #define CLKDM_CAN_DISABLE_AUTO			(1 << 3)
+ + #define CLKDM_NO_AUTODEPS			(1 << 4)
+ + 
+ + #define CLKDM_CAN_HWSUP		(CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO)
+ + #define CLKDM_CAN_SWSUP		(CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP)
+ + #define CLKDM_CAN_HWSUP_SWSUP	(CLKDM_CAN_SWSUP | CLKDM_CAN_HWSUP)
+ + 
+ + /**
+ +  * struct clkdm_autodep - clkdm deps to add when entering/exiting hwsup mode
+ +  * @clkdm: clockdomain to add wkdep+sleepdep on - set name member only
+ +  *
+ +  * A clockdomain that should have wkdeps and sleepdeps added when a
+ +  * clockdomain should stay active in hwsup mode; and conversely,
+ +  * removed when the clockdomain should be allowed to go inactive in
+ +  * hwsup mode.
+ +  *
+ +  * Autodeps are deprecated and should be removed after
+ +  * omap_hwmod-based fine-grained module idle control is added.
+ +  */
+ + struct clkdm_autodep {
+ + 	union {
+ + 		const char *name;
+ + 		struct clockdomain *ptr;
+ + 	} clkdm;
+ + };
+ + 
+ + /**
+ +  * struct clkdm_dep - encode dependencies between clockdomains
+ +  * @clkdm_name: clockdomain name
+ +  * @clkdm: pointer to the struct clockdomain of @clkdm_name
+ +  * @wkdep_usecount: Number of wakeup dependencies causing this clkdm to wake
+ +  * @sleepdep_usecount: Number of sleep deps that could prevent clkdm from idle
+ +  *
+ +  * Statically defined.  @clkdm is resolved from @clkdm_name at runtime and
+ +  * should not be pre-initialized.
+ +  *
+ +  * XXX Should also include hardware (fixed) dependencies.
+ +  */
+ + struct clkdm_dep {
+ + 	const char *clkdm_name;
+ + 	struct clockdomain *clkdm;
+ + 	atomic_t wkdep_usecount;
+ + 	atomic_t sleepdep_usecount;
+ + };
+ + 
+ + /* Possible flags for struct clockdomain._flags */
+ + #define _CLKDM_FLAG_HWSUP_ENABLED		BIT(0)
+ + 
+ + /**
+ +  * struct clockdomain - OMAP clockdomain
+ +  * @name: clockdomain name
+ +  * @pwrdm: powerdomain containing this clockdomain
+ +  * @clktrctrl_reg: CLKSTCTRL reg for the given clock domain
+ +  * @clktrctrl_mask: CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg
+ +  * @flags: Clockdomain capability flags
+ +  * @_flags: Flags for use only by internal clockdomain code
+ +  * @dep_bit: Bit shift of this clockdomain's PM_WKDEP/CM_SLEEPDEP bit
+ +  * @prcm_partition: (OMAP4 only) PRCM partition ID for this clkdm's registers
+ +  * @cm_inst: (OMAP4 only) CM instance register offset
+ +  * @clkdm_offs: (OMAP4 only) CM clockdomain register offset
+ +  * @wkdep_srcs: Clockdomains that can be told to wake this powerdomain up
+ +  * @sleepdep_srcs: Clockdomains that can be told to keep this clkdm from inact
+ +  * @usecount: Usecount tracking
+ +  * @node: list_head to link all clockdomains together
+ +  *
+ +  * @prcm_partition should be a macro from mach-omap2/prcm44xx.h (OMAP4 only)
+ +  * @cm_inst should be a macro ending in _INST from the OMAP4 CM instance
+ +  *     definitions (OMAP4 only)
+ +  * @clkdm_offs should be a macro ending in _CDOFFS from the OMAP4 CM instance
+ +  *     definitions (OMAP4 only)
+ +  */
+ + struct clockdomain {
+ + 	const char *name;
+ + 	union {
+ + 		const char *name;
+ + 		struct powerdomain *ptr;
+ + 	} pwrdm;
+ + 	const u16 clktrctrl_mask;
+ + 	const u8 flags;
+ + 	u8 _flags;
+ + 	const u8 dep_bit;
+ + 	const u8 prcm_partition;
+ + 	const s16 cm_inst;
+ + 	const u16 clkdm_offs;
+ + 	struct clkdm_dep *wkdep_srcs;
+ + 	struct clkdm_dep *sleepdep_srcs;
+ + 	atomic_t usecount;
+ + 	struct list_head node;
+ + 	spinlock_t lock;
+ + };
+ + 
+ + /**
+ +  * struct clkdm_ops - Arch specific function implementations
+ +  * @clkdm_add_wkdep: Add a wakeup dependency between clk domains
+ +  * @clkdm_del_wkdep: Delete a wakeup dependency between clk domains
+ +  * @clkdm_read_wkdep: Read wakeup dependency state between clk domains
+ +  * @clkdm_clear_all_wkdeps: Remove all wakeup dependencies from the clk domain
+ +  * @clkdm_add_sleepdep: Add a sleep dependency between clk domains
+ +  * @clkdm_del_sleepdep: Delete a sleep dependency between clk domains
+ +  * @clkdm_read_sleepdep: Read sleep dependency state between clk domains
+ +  * @clkdm_clear_all_sleepdeps: Remove all sleep dependencies from the clk domain
+ +  * @clkdm_sleep: Force a clockdomain to sleep
+ +  * @clkdm_wakeup: Force a clockdomain to wakeup
+ +  * @clkdm_allow_idle: Enable hw supervised idle transitions for clock domain
+ +  * @clkdm_deny_idle: Disable hw supervised idle transitions for clock domain
+ +  * @clkdm_clk_enable: Put the clkdm in right state for a clock enable
+ +  * @clkdm_clk_disable: Put the clkdm in right state for a clock disable
+ +  */
+ + struct clkdm_ops {
+ + 	int	(*clkdm_add_wkdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+ + 	int	(*clkdm_del_wkdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+ + 	int	(*clkdm_read_wkdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+ + 	int	(*clkdm_clear_all_wkdeps)(struct clockdomain *clkdm);
+ + 	int	(*clkdm_add_sleepdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+ + 	int	(*clkdm_del_sleepdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+ + 	int	(*clkdm_read_sleepdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+ + 	int	(*clkdm_clear_all_sleepdeps)(struct clockdomain *clkdm);
+ + 	int	(*clkdm_sleep)(struct clockdomain *clkdm);
+ + 	int	(*clkdm_wakeup)(struct clockdomain *clkdm);
+ + 	void	(*clkdm_allow_idle)(struct clockdomain *clkdm);
+ + 	void	(*clkdm_deny_idle)(struct clockdomain *clkdm);
+ + 	int	(*clkdm_clk_enable)(struct clockdomain *clkdm);
+ + 	int	(*clkdm_clk_disable)(struct clockdomain *clkdm);
+ + };
+ + 
+ + int clkdm_register_platform_funcs(struct clkdm_ops *co);
+ + int clkdm_register_autodeps(struct clkdm_autodep *ia);
+ + int clkdm_register_clkdms(struct clockdomain **c);
+ + int clkdm_complete_init(void);
+ + 
+ + struct clockdomain *clkdm_lookup(const char *name);
+ + 
+ + int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user),
+ + 			void *user);
+ + struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm);
+ + 
+ + int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+ + int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+ + int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+ + int clkdm_clear_all_wkdeps(struct clockdomain *clkdm);
+ + int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+ + int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+ + int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+ + int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm);
+ + 
+ + void clkdm_allow_idle(struct clockdomain *clkdm);
+ + void clkdm_deny_idle(struct clockdomain *clkdm);
+ + bool clkdm_in_hwsup(struct clockdomain *clkdm);
+ + 
+ + int clkdm_wakeup(struct clockdomain *clkdm);
+ + int clkdm_sleep(struct clockdomain *clkdm);
+ + 
+ + int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
+ + int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
+ + 
+ + extern void __init omap242x_clockdomains_init(void);
+ + extern void __init omap243x_clockdomains_init(void);
+ + extern void __init am33xx_clockdomains_init(void);
+ + extern void __init omap44xx_clockdomains_init(void);
+ + extern void _clkdm_add_autodeps(struct clockdomain *clkdm);
+ + extern void _clkdm_del_autodeps(struct clockdomain *clkdm);
+ + 
+ + extern struct clkdm_ops omap3_clkdm_operations;
+ + extern struct clkdm_ops omap4_clkdm_operations;
+ + extern struct clkdm_ops am33xx_clkdm_operations;
+ + 
+ + extern struct clkdm_dep gfx_24xx_wkdeps[];
+ + extern struct clkdm_dep dsp_24xx_wkdeps[];
+ + extern struct clockdomain wkup_common_clkdm;
+ + extern struct clockdomain prm_common_clkdm;
+ + extern struct clockdomain cm_common_clkdm;
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/clockdomains33xx_data.c linux-3.2.1/arch/arm/mach-ckb_3352/clockdomains33xx_data.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/clockdomains33xx_data.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/clockdomains33xx_data.c	2014-11-25 13:19:14.864252130 +0900
+ ***************
+ *** 0 ****
+ --- 1,232 ----
+ + /*
+ +  * AM33XX Clock Domain data.
+ +  *
+ +  * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #include <linux/kernel.h>
+ + #include <linux/io.h>
+ + 
+ + #include "prcm44xx.h"
+ + #include "clockdomain.h"
+ + #include "cm.h"
+ + #include "cm33xx.h"
+ + #include "cm-regbits-33xx.h"
+ + 
+ + static struct clockdomain l4ls_am33xx_clkdm = {
+ + 	.name		= "l4ls_clkdm",
+ + 	.pwrdm		= { .name = "per_pwrdm" },
+ + 	.cm_inst	= AM33XX_CM_PER_MOD,
+ + 	.prcm_partition	= AM33XX_PRM_PARTITION,
+ + 	.clkdm_offs	= AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET,
+ + 	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
+ + 	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
+ + };
+ + 
+ + static struct clockdomain l3s_am33xx_clkdm = {
+ + 	.name		= "l3s_clkdm",
+ + 	.pwrdm		= { .name = "per_pwrdm" },
+ + 	.cm_inst	= AM33XX_CM_PER_MOD,
+ + 	.prcm_partition	= AM33XX_PRM_PARTITION,
+ + 	.clkdm_offs	= AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET,
+ + 	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
+ + 	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
+ + };
+ + 
+ + static struct clockdomain l4fw_am33xx_clkdm = {
+ + 	.name		= "l4fw_clkdm",
+ + 	.pwrdm		= { .name = "per_pwrdm" },
+ + 	.cm_inst	= AM33XX_CM_PER_MOD,
+ + 	.prcm_partition	= AM33XX_PRM_PARTITION,
+ + 	.clkdm_offs	= AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET,
+ + 	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
+ + 	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
+ + };
+ + 
+ + static struct clockdomain l3_am33xx_clkdm = {
+ + 	.name		= "l3_clkdm",
+ + 	.pwrdm		= { .name = "per_pwrdm" },
+ + 	.cm_inst	= AM33XX_CM_PER_MOD,
+ + 	.prcm_partition	= AM33XX_PRM_PARTITION,
+ + 	.clkdm_offs	= AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET,
+ + 	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
+ + 	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
+ + };
+ + 
+ + static struct clockdomain l4hs_am33xx_clkdm = {
+ + 	.name		= "l4hs_clkdm",
+ + 	.pwrdm		= { .name = "per_pwrdm" },
+ + 	.cm_inst	= AM33XX_CM_PER_MOD,
+ + 	.prcm_partition	= AM33XX_PRM_PARTITION,
+ + 	.clkdm_offs	= AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET,
+ + 	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
+ + 	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
+ + };
+ + 
+ + static struct clockdomain ocpwp_l3_am33xx_clkdm = {
+ + 	.name		= "ocpwp_l3_clkdm",
+ + 	.pwrdm		= { .name = "per_pwrdm" },
+ + 	.cm_inst	= AM33XX_CM_PER_MOD,
+ + 	.prcm_partition	= AM33XX_PRM_PARTITION,
+ + 	.clkdm_offs	= AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET,
+ + 	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
+ + 	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
+ + };
+ + 
+ + static struct clockdomain pruss_ocp_am33xx_clkdm = {
+ + 	.name		= "pruss_ocp_clkdm",
+ + 	.pwrdm		= { .name = "per_pwrdm" },
+ + 	.cm_inst	= AM33XX_CM_PER_MOD,
+ + 	.prcm_partition	= AM33XX_PRM_PARTITION,
+ + 	.clkdm_offs	= AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET,
+ + 	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
+ + 	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
+ + };
+ + 
+ + static struct clockdomain cpsw_125mhz_am33xx_clkdm = {
+ + 	.name		= "cpsw_125mhz_clkdm",
+ + 	.pwrdm		= { .name = "per_pwrdm" },
+ + 	.cm_inst	= AM33XX_CM_PER_MOD,
+ + 	.prcm_partition	= AM33XX_PRM_PARTITION,
+ + 	.clkdm_offs	= AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET,
+ + 	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
+ + 	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
+ + };
+ + 
+ + static struct clockdomain lcdc_am33xx_clkdm = {
+ + 	.name		= "lcdc_clkdm",
+ + 	.pwrdm		= { .name = "per_pwrdm" },
+ + 	.cm_inst	= AM33XX_CM_PER_MOD,
+ + 	.prcm_partition	= AM33XX_PRM_PARTITION,
+ + 	.clkdm_offs	= AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET,
+ + 	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
+ + 	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
+ + };
+ + 
+ + static struct clockdomain clk_24mhz_am33xx_clkdm = {
+ + 	.name		= "clk_24mhz_clkdm",
+ + 	.pwrdm		= { .name = "per_pwrdm" },
+ + 	.cm_inst	= AM33XX_CM_PER_MOD,
+ + 	.prcm_partition	= AM33XX_PRM_PARTITION,
+ + 	.clkdm_offs	= AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET,
+ + 	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
+ + 	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
+ + };
+ + 
+ + static struct clockdomain l4_wkup_am33xx_clkdm = {
+ + 	.name		= "l4_wkup_clkdm",
+ + 	.pwrdm		= { .name = "wkup_pwrdm" },
+ + 	.cm_inst	= AM33XX_CM_WKUP_MOD,
+ + 	.prcm_partition	= AM33XX_PRM_PARTITION,
+ + 	.clkdm_offs	= AM33XX_CM_WKUP_CLKSTCTRL_OFFSET,
+ + 	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
+ + 	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
+ + };
+ + 
+ + static struct clockdomain l3_aon_am33xx_clkdm = {
+ + 	.name		= "l3_aon_clkdm",
+ + 	.pwrdm		= { .name = "wkup_pwrdm" },
+ + 	.cm_inst	= AM33XX_CM_WKUP_MOD,
+ + 	.prcm_partition	= AM33XX_PRM_PARTITION,
+ + 	.clkdm_offs	= AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET,
+ + 	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
+ + 	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
+ + };
+ + 
+ + static struct clockdomain l4_wkup_aon_am33xx_clkdm = {
+ + 	.name		= "l4_wkup_aon_clkdm",
+ + 	.pwrdm		= { .name = "wkup_pwrdm" },
+ + 	.cm_inst	= AM33XX_CM_WKUP_MOD,
+ + 	.prcm_partition	= AM33XX_PRM_PARTITION,
+ + 	.clkdm_offs	= AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET,
+ + 	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
+ + 	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
+ + };
+ + 
+ + static struct clockdomain mpu_am33xx_clkdm = {
+ + 	.name		= "mpu_clkdm",
+ + 	.pwrdm		= { .name = "mpu_pwrdm" },
+ + 	.cm_inst	= AM33XX_CM_MPU_MOD,
+ + 	.prcm_partition	= AM33XX_PRM_PARTITION,
+ + 	.clkdm_offs	= AM33XX_CM_MPU_CLKSTCTRL_OFFSET,
+ + 	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
+ + 	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
+ + };
+ + 
+ + static struct clockdomain l4_rtc_am33xx_clkdm = {
+ + 	.name		= "l4_rtc_clkdm",
+ + 	.pwrdm		= { .name = "rtc_pwrdm" },
+ + 	.cm_inst	= AM33XX_CM_RTC_MOD,
+ + 	.prcm_partition	= AM33XX_PRM_PARTITION,
+ + 	.clkdm_offs	= AM33XX_CM_RTC_CLKSTCTRL_OFFSET,
+ + 	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
+ + 	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
+ + };
+ + 
+ + static struct clockdomain gfx_l3_am33xx_clkdm = {
+ + 	.name		= "gfx_l3_clkdm",
+ + 	.pwrdm		= { .name = "gfx_pwrdm" },
+ + 	.cm_inst	= AM33XX_CM_GFX_MOD,
+ + 	.prcm_partition	= AM33XX_PRM_PARTITION,
+ + 	.clkdm_offs	= AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET,
+ + 	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
+ + 	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
+ + };
+ + 
+ + static struct clockdomain gfx_l4ls_gfx_am33xx_clkdm = {
+ + 	.name		= "gfx_l4ls_gfx_clkdm",
+ + 	.pwrdm		= { .name = "gfx_pwrdm" },
+ + 	.cm_inst	= AM33XX_CM_GFX_MOD,
+ + 	.prcm_partition	= AM33XX_PRM_PARTITION,
+ + 	.clkdm_offs	= AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET,
+ + 	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
+ + 	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
+ + };
+ + 
+ + static struct clockdomain l4_cefuse_am33xx_clkdm = {
+ + 	.name		= "l4_cefuse_clkdm",
+ + 	.pwrdm		= { .name = "cefuse_pwrdm" },
+ + 	.cm_inst	= AM33XX_CM_CEFUSE_MOD,
+ + 	.prcm_partition	= AM33XX_PRM_PARTITION,
+ + 	.clkdm_offs	= AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET,
+ + 	.clktrctrl_mask	= AM33XX_CLKTRCTRL_MASK,
+ + 	.flags		= (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
+ + };
+ + 
+ + static struct clockdomain *clockdomains_am33xx[] __initdata = {
+ + 	&l4ls_am33xx_clkdm,
+ + 	&l3s_am33xx_clkdm,
+ + 	&l4fw_am33xx_clkdm,
+ + 	&l3_am33xx_clkdm,
+ + 	&l4hs_am33xx_clkdm,
+ + 	&ocpwp_l3_am33xx_clkdm,
+ + 	&pruss_ocp_am33xx_clkdm,
+ + 	&cpsw_125mhz_am33xx_clkdm,
+ + 	&lcdc_am33xx_clkdm,
+ + 	&clk_24mhz_am33xx_clkdm,
+ + 	&l4_wkup_am33xx_clkdm,
+ + 	&l3_aon_am33xx_clkdm,
+ + 	&l4_wkup_aon_am33xx_clkdm,
+ + 	&mpu_am33xx_clkdm,
+ + 	&l4_rtc_am33xx_clkdm,
+ + 	&gfx_l3_am33xx_clkdm,
+ + 	&gfx_l4ls_gfx_am33xx_clkdm,
+ + 	&l4_cefuse_am33xx_clkdm,
+ + 	NULL,
+ + };
+ + 
+ + void __init am33xx_clockdomains_init(void)
+ + {
+ + 	clkdm_register_platform_funcs(&am33xx_clkdm_operations);
+ + 	clkdm_register_clkdms(clockdomains_am33xx);
+ + 	clkdm_complete_init();
+ + }
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/clock.h linux-3.2.1/arch/arm/mach-ckb_3352/clock.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/clock.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/clock.h	2014-11-25 13:19:14.864252130 +0900
+ ***************
+ *** 0 ****
+ --- 1,125 ----
+ + /*
+ +  *  linux/arch/arm/mach-omap2/clock.h
+ +  *
+ +  *  Copyright (C) 2005-2009 Texas Instruments, Inc.
+ +  *  Copyright (C) 2004-2011 Nokia Corporation
+ +  *
+ +  *  Contacts:
+ +  *  Richard Woodruff <r-woodruff2@ti.com>
+ +  *  Paul Walmsley
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
+ + #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
+ + 
+ + #include <linux/kernel.h>
+ + 
+ + #include <plat/clock.h>
+ + 
+ + /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
+ + #define CORE_CLK_SRC_32K		0x0
+ + #define CORE_CLK_SRC_DPLL		0x1
+ + #define CORE_CLK_SRC_DPLL_X2		0x2
+ + 
+ + /* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */
+ + #define OMAP2XXX_EN_DPLL_LPBYPASS		0x1
+ + #define OMAP2XXX_EN_DPLL_FRBYPASS		0x2
+ + #define OMAP2XXX_EN_DPLL_LOCKED			0x3
+ + 
+ + /* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
+ + #define OMAP3XXX_EN_DPLL_LPBYPASS		0x5
+ + #define OMAP3XXX_EN_DPLL_FRBYPASS		0x6
+ + #define OMAP3XXX_EN_DPLL_LOCKED			0x7
+ + 
+ + /* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
+ + #define OMAP4XXX_EN_DPLL_MNBYPASS		0x4
+ + 
+ + /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
+ + #define DPLL_LOW_POWER_STOP	0x1
+ + #define DPLL_LOW_POWER_BYPASS	0x5
+ + #define DPLL_LOCKED		0x7
+ + 
+ + /* DPLL Type and DCO Selection Flags */
+ + #define DPLL_J_TYPE		0x1
+ + 
+ + int omap2_clk_enable(struct clk *clk);
+ + void omap2_clk_disable(struct clk *clk);
+ + long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
+ + int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
+ + int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
+ + long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
+ + unsigned long omap3_dpll_recalc(struct clk *clk);
+ + unsigned long omap3_clkoutx2_recalc(struct clk *clk);
+ + void omap3_dpll_allow_idle(struct clk *clk);
+ + void omap3_dpll_deny_idle(struct clk *clk);
+ + u32 omap3_dpll_autoidle_read(struct clk *clk);
+ + int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
+ + int omap3_noncore_dpll_enable(struct clk *clk);
+ + void omap3_noncore_dpll_disable(struct clk *clk);
+ + int omap4_dpllmx_gatectrl_read(struct clk *clk);
+ + void omap4_dpllmx_allow_gatectrl(struct clk *clk);
+ + void omap4_dpllmx_deny_gatectrl(struct clk *clk);
+ + long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate);
+ + unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk);
+ + 
+ + #ifdef CONFIG_OMAP_RESET_CLOCKS
+ + void omap2_clk_disable_unused(struct clk *clk);
+ + #else
+ + #define omap2_clk_disable_unused	NULL
+ + #endif
+ + 
+ + void omap2_init_clk_clkdm(struct clk *clk);
+ + void __init omap2_clk_disable_clkdm_control(void);
+ + 
+ + /* clkt_clksel.c public functions */
+ + u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
+ + 				u32 *new_div);
+ + void omap2_init_clksel_parent(struct clk *clk);
+ + unsigned long omap2_clksel_recalc(struct clk *clk);
+ + long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
+ + int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
+ + int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent);
+ + 
+ + u32 omap2_get_dpll_rate(struct clk *clk);
+ + void omap2_init_dpll_parent(struct clk *clk);
+ + 
+ + int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
+ + 
+ + 
+ + 
+ + void omap3_clk_prepare_for_reboot(void);
+ + 
+ + int omap2_dflt_clk_enable(struct clk *clk);
+ + void omap2_dflt_clk_disable(struct clk *clk);
+ + void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
+ + 				   u8 *other_bit);
+ + int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
+ + void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
+ + 			       const char *core_ck_name,
+ + 			       const char *mpu_ck_name);
+ + 
+ + extern u16 cpu_mask;
+ + 
+ + extern const struct clkops clkops_dummy;
+ + extern const struct clkops clkops_omap2_dflt;
+ + 
+ + extern struct clk_functions omap2_clk_functions;
+ + extern struct clk *vclk, *sclk;
+ + 
+ + extern const struct clksel_rate gpt_32k_rates[];
+ + extern const struct clksel_rate gpt_sys_rates[];
+ + extern const struct clksel_rate gfx_l3_rates[];
+ + extern const struct clksel_rate dsp_ick_rates[];
+ + 
+ + #define omap2_clk_init_cpufreq_table	0
+ + #define omap2_clk_exit_cpufreq_table	0
+ + 
+ + extern const struct clkops clkops_omap3_noncore_dpll_ops;
+ + extern const struct clkops clkops_omap3_core_dpll_ops;
+ + extern const struct clkops clkops_omap4_dpllmx_ops;
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/cm2xxx_3xxx.h linux-3.2.1/arch/arm/mach-ckb_3352/cm2xxx_3xxx.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/cm2xxx_3xxx.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/cm2xxx_3xxx.h	2014-11-25 13:19:14.864252130 +0900
+ ***************
+ *** 0 ****
+ --- 1,147 ----
+ + /*
+ +  * OMAP2/3 Clock Management (CM) register definitions
+ +  *
+ +  * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ +  * Copyright (C) 2007-2010 Nokia Corporation
+ +  * Paul Walmsley
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  *
+ +  * The CM hardware modules on the OMAP2/3 are quite similar to each
+ +  * other.  The CM modules/instances on OMAP4 are quite different, so
+ +  * they are handled in a separate file.
+ +  */
+ + #ifndef __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H
+ + #define __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H
+ + 
+ + #include "prcm-common.h"
+ + 
+ + #define OMAP34XX_CM_REGADDR(module, reg)				\
+ + 			OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
+ + 
+ + 
+ + /*
+ +  * OMAP3-specific global CM registers
+ +  * Use cm_{read,write}_reg() with these registers.
+ +  * These registers appear once per CM module.
+ +  */
+ + 
+ + #define OMAP3430_CM_REVISION		OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000)
+ + #define OMAP3430_CM_SYSCONFIG		OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
+ + #define OMAP3430_CM_POLCTRL		OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
+ + 
+ + #define OMAP3_CM_CLKOUT_CTRL_OFFSET	0x0070
+ + #define OMAP3430_CM_CLKOUT_CTRL		OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
+ + 
+ + /*
+ +  * Module specific CM register offsets from CM_BASE + domain offset
+ +  * Use cm_{read,write}_mod_reg() with these registers.
+ +  * These register offsets generally appear in more than one PRCM submodule.
+ +  */
+ + 
+ + /* Common between OMAP2 and OMAP3 */
+ + 
+ + #define CM_FCLKEN					0x0000
+ + #define CM_FCLKEN1					CM_FCLKEN
+ + #define CM_CLKEN					CM_FCLKEN
+ + #define CM_ICLKEN					0x0010
+ + #define CM_ICLKEN1					CM_ICLKEN
+ + #define CM_ICLKEN2					0x0014
+ + #define CM_ICLKEN3					0x0018
+ + #define CM_IDLEST					0x0020
+ + #define CM_IDLEST1					CM_IDLEST
+ + #define CM_IDLEST2					0x0024
+ + #define CM_AUTOIDLE					0x0030
+ + #define CM_AUTOIDLE1					CM_AUTOIDLE
+ + #define CM_AUTOIDLE2					0x0034
+ + #define CM_AUTOIDLE3					0x0038
+ + #define CM_CLKSEL					0x0040
+ + #define CM_CLKSEL1					CM_CLKSEL
+ + #define CM_CLKSEL2					0x0044
+ + #define OMAP2_CM_CLKSTCTRL				0x0048
+ + 
+ + /* OMAP2-specific register offsets */
+ + 
+ + #define OMAP24XX_CM_FCLKEN2				0x0004
+ + #define OMAP24XX_CM_ICLKEN4				0x001c
+ + #define OMAP24XX_CM_AUTOIDLE4				0x003c
+ + 
+ + #define OMAP2430_CM_IDLEST3				0x0028
+ + 
+ + /* OMAP3-specific register offsets */
+ + 
+ + #define OMAP3430_CM_CLKEN_PLL				0x0004
+ + #define OMAP3430ES2_CM_CLKEN2				0x0004
+ + #define OMAP3430ES2_CM_FCLKEN3				0x0008
+ + #define OMAP3430_CM_IDLEST_PLL				CM_IDLEST2
+ + #define OMAP3430_CM_AUTOIDLE_PLL			CM_AUTOIDLE2
+ + #define OMAP3430ES2_CM_AUTOIDLE2_PLL			CM_AUTOIDLE2
+ + #define OMAP3430_CM_CLKSEL1				CM_CLKSEL
+ + #define OMAP3430_CM_CLKSEL1_PLL				CM_CLKSEL
+ + #define OMAP3430_CM_CLKSEL2_PLL				CM_CLKSEL2
+ + #define OMAP3430_CM_SLEEPDEP				CM_CLKSEL2
+ + #define OMAP3430_CM_CLKSEL3				OMAP2_CM_CLKSTCTRL
+ + #define OMAP3430_CM_CLKSTST				0x004c
+ + #define OMAP3430ES2_CM_CLKSEL4				0x004c
+ + #define OMAP3430ES2_CM_CLKSEL5				0x0050
+ + #define OMAP3430_CM_CLKSEL2_EMU				0x0050
+ + #define OMAP3430_CM_CLKSEL3_EMU				0x0054
+ + 
+ + 
+ + /* CM_IDLEST bit field values to indicate deasserted IdleReq */
+ + 
+ + #define OMAP24XX_CM_IDLEST_VAL				0
+ + #define OMAP34XX_CM_IDLEST_VAL				1
+ + 
+ + 
+ + /* Clock management domain register get/set */
+ + 
+ + #ifndef __ASSEMBLER__
+ + 
+ + extern u32 omap2_cm_read_mod_reg(s16 module, u16 idx);
+ + extern void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx);
+ + extern u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
+ + 
+ + extern u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx);
+ + extern u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx);
+ + 
+ + extern bool omap2_cm_is_clkdm_in_hwsup(s16 module, u32 mask);
+ + extern void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask);
+ + extern void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
+ + 
+ + extern void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask);
+ + extern void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
+ + extern void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask);
+ + extern void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask);
+ + 
+ + extern int am33xx_cm_wait_module_ready(u16 inst, u16 clkctrl_reg);
+ + extern void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 clkdm, u32 mask);
+ + extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 clkdm, u32 mask);
+ + extern void am33xx_cm_clkdm_force_sleep(s16 inst, u16 clkdm, u32 mask);
+ + extern void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 clkdm, u32 mask);
+ + 
+ + #endif
+ + 
+ + /* CM register bits shared between 24XX and 3430 */
+ + 
+ + /* CM_CLKSEL_GFX */
+ + #define OMAP_CLKSEL_GFX_SHIFT				0
+ + #define OMAP_CLKSEL_GFX_MASK				(0x7 << 0)
+ + 
+ + /* CM_ICLKEN_GFX */
+ + #define OMAP_EN_GFX_SHIFT				0
+ + #define OMAP_EN_GFX_MASK				(1 << 0)
+ + 
+ + /* CM_IDLEST_GFX */
+ + #define OMAP_ST_GFX_MASK				(1 << 0)
+ + 
+ + 
+ + /* Function prototypes */
+ + # ifndef __ASSEMBLER__
+ + extern void omap3_cm_save_context(void);
+ + extern void omap3_cm_restore_context(void);
+ + # endif
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/cm33xx.h linux-3.2.1/arch/arm/mach-ckb_3352/cm33xx.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/cm33xx.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/cm33xx.h	2014-11-25 13:19:14.864252130 +0900
+ ***************
+ *** 0 ****
+ --- 1,377 ----
+ + /*
+ +  * AM33XX CM instance offset macros
+ +  *
+ +  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H
+ + #define __ARCH_ARM_MACH_OMAP2_CM_33XX_H
+ + 
+ + #include "common.h"
+ + 
+ + #include "cm.h"
+ + #include "cm-regbits-33xx.h"
+ + #include "cm33xx.h"
+ + 
+ + /* CM base address */
+ + #define AM33XX_CM_BASE		0x44e00000
+ + 
+ + #define AM33XX_CM_REGADDR(inst, reg)				\
+ + 	AM33XX_L4_WK_IO_ADDRESS(AM33XX_CM_BASE + (inst) + (reg))
+ + 
+ + /* CM instances */
+ + #define AM33XX_CM_PER_MOD		0x0000
+ + #define AM33XX_CM_WKUP_MOD		0x0400
+ + #define AM33XX_CM_DPLL_MOD		0x0500
+ + #define AM33XX_CM_MPU_MOD		0x0600
+ + #define AM33XX_CM_DEVICE_MOD		0x0700
+ + #define AM33XX_CM_RTC_MOD		0x0800
+ + #define AM33XX_CM_GFX_MOD		0x0900
+ + #define AM33XX_CM_CEFUSE_MOD		0x0A00
+ + 
+ + /* CM */
+ + 
+ + /* CM.PER_CM register offsets */
+ + #define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET		0x0000
+ + #define AM33XX_CM_PER_L4LS_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0000)
+ + #define AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET		0x0004
+ + #define AM33XX_CM_PER_L3S_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0004)
+ + #define AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET		0x0008
+ + #define AM33XX_CM_PER_L4FW_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0008)
+ + #define AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET		0x000c
+ + #define AM33XX_CM_PER_L3_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x000c)
+ + #define AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET		0x0014
+ + #define AM33XX_CM_PER_CPGMAC0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0014)
+ + #define AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET		0x0018
+ + #define AM33XX_CM_PER_LCDC_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0018)
+ + #define AM33XX_CM_PER_USB0_CLKCTRL_OFFSET		0x001c
+ + #define AM33XX_CM_PER_USB0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x001c)
+ + #define AM33XX_CM_PER_MLB_CLKCTRL_OFFSET		0x0020
+ + #define AM33XX_CM_PER_MLB_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0020)
+ + #define AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET		0x0024
+ + #define AM33XX_CM_PER_TPTC0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0024)
+ + #define AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET		0x0028
+ + #define AM33XX_CM_PER_EMIF_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0028)
+ + #define AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET		0x002c
+ + #define AM33XX_CM_PER_OCMCRAM_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x002c)
+ + #define AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET		0x0030
+ + #define AM33XX_CM_PER_GPMC_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0030)
+ + #define AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET		0x0034
+ + #define AM33XX_CM_PER_MCASP0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0034)
+ + #define AM33XX_CM_PER_UART5_CLKCTRL_OFFSET		0x0038
+ + #define AM33XX_CM_PER_UART5_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0038)
+ + #define AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET		0x003c
+ + #define AM33XX_CM_PER_MMC0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x003c)
+ + #define AM33XX_CM_PER_ELM_CLKCTRL_OFFSET		0x0040
+ + #define AM33XX_CM_PER_ELM_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0040)
+ + #define AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET		0x0044
+ + #define AM33XX_CM_PER_I2C2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0044)
+ + #define AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET		0x0048
+ + #define AM33XX_CM_PER_I2C1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0048)
+ + #define AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET		0x004c
+ + #define AM33XX_CM_PER_SPI0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x004c)
+ + #define AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET		0x0050
+ + #define AM33XX_CM_PER_SPI1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0050)
+ + #define AM33XX_CM_PER_SPI2_CLKCTRL_OFFSET		0x0054
+ + #define AM33XX_CM_PER_SPI2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0054)
+ + #define AM33XX_CM_PER_SPI3_CLKCTRL_OFFSET		0x0058
+ + #define AM33XX_CM_PER_SPI3_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0058)
+ + #define AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET		0x0060
+ + #define AM33XX_CM_PER_L4LS_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0060)
+ + #define AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET		0x0064
+ + #define AM33XX_CM_PER_L4FW_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0064)
+ + #define AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET		0x0068
+ + #define AM33XX_CM_PER_MCASP1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0068)
+ + #define AM33XX_CM_PER_UART1_CLKCTRL_OFFSET		0x006c
+ + #define AM33XX_CM_PER_UART1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x006c)
+ + #define AM33XX_CM_PER_UART2_CLKCTRL_OFFSET		0x0070
+ + #define AM33XX_CM_PER_UART2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0070)
+ + #define AM33XX_CM_PER_UART3_CLKCTRL_OFFSET		0x0074
+ + #define AM33XX_CM_PER_UART3_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0074)
+ + #define AM33XX_CM_PER_UART4_CLKCTRL_OFFSET		0x0078
+ + #define AM33XX_CM_PER_UART4_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0078)
+ + #define AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET		0x007c
+ + #define AM33XX_CM_PER_TIMER7_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x007c)
+ + #define AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET		0x0080
+ + #define AM33XX_CM_PER_TIMER2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0080)
+ + #define AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET		0x0084
+ + #define AM33XX_CM_PER_TIMER3_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0084)
+ + #define AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET		0x0088
+ + #define AM33XX_CM_PER_TIMER4_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0088)
+ + #define AM33XX_CM_PER_MCASP2_CLKCTRL_OFFSET		0x008c
+ + #define AM33XX_CM_PER_MCASP2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x008c)
+ + #define AM33XX_CM_PER_RNG_CLKCTRL_OFFSET		0x0090
+ + #define AM33XX_CM_PER_RNG_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0090)
+ + #define AM33XX_CM_PER_AES0_CLKCTRL_OFFSET		0x0094
+ + #define AM33XX_CM_PER_AES0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0094)
+ + #define AM33XX_CM_PER_AES1_CLKCTRL_OFFSET		0x0098
+ + #define AM33XX_CM_PER_AES1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0098)
+ + #define AM33XX_CM_PER_DES_CLKCTRL_OFFSET		0x009c
+ + #define AM33XX_CM_PER_DES_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x009c)
+ + #define AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET		0x00a0
+ + #define AM33XX_CM_PER_SHA0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a0)
+ + #define AM33XX_CM_PER_PKA_CLKCTRL_OFFSET		0x00a4
+ + #define AM33XX_CM_PER_PKA_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a4)
+ + #define AM33XX_CM_PER_GPIO6_CLKCTRL_OFFSET		0x00a8
+ + #define AM33XX_CM_PER_GPIO6_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a8)
+ + #define AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET		0x00ac
+ + #define AM33XX_CM_PER_GPIO1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ac)
+ + #define AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET		0x00b0
+ + #define AM33XX_CM_PER_GPIO2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b0)
+ + #define AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET		0x00b4
+ + #define AM33XX_CM_PER_GPIO3_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b4)
+ + #define AM33XX_CM_PER_GPIO4_CLKCTRL_OFFSET		0x00b8
+ + #define AM33XX_CM_PER_GPIO4_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b8)
+ + #define AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET		0x00bc
+ + #define AM33XX_CM_PER_TPCC_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00bc)
+ + #define AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET		0x00c0
+ + #define AM33XX_CM_PER_DCAN0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c0)
+ + #define AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET		0x00c4
+ + #define AM33XX_CM_PER_DCAN1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c4)
+ + #define AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET		0x00cc
+ + #define AM33XX_CM_PER_EPWMSS1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00cc)
+ + #define AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET		0x00d0
+ + #define AM33XX_CM_PER_EMIF_FW_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d0)
+ + #define AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET		0x00d4
+ + #define AM33XX_CM_PER_EPWMSS0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d4)
+ + #define AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET		0x00d8
+ + #define AM33XX_CM_PER_EPWMSS2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d8)
+ + #define AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET		0x00dc
+ + #define AM33XX_CM_PER_L3_INSTR_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00dc)
+ + #define AM33XX_CM_PER_L3_CLKCTRL_OFFSET			0x00e0
+ + #define AM33XX_CM_PER_L3_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e0)
+ + #define AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET		0x00e4
+ + #define AM33XX_CM_PER_IEEE5000_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e4)
+ + #define AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET		0x00e8
+ + #define AM33XX_CM_PER_PRUSS_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e8)
+ + #define AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET		0x00ec
+ + #define AM33XX_CM_PER_TIMER5_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ec)
+ + #define AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET		0x00f0
+ + #define AM33XX_CM_PER_TIMER6_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f0)
+ + #define AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET		0x00f4
+ + #define AM33XX_CM_PER_MMC1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f4)
+ + #define AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET		0x00f8
+ + #define AM33XX_CM_PER_MMC2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f8)
+ + #define AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET		0x00fc
+ + #define AM33XX_CM_PER_TPTC1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00fc)
+ + #define AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET		0x0100
+ + #define AM33XX_CM_PER_TPTC2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0100)
+ + #define AM33XX_CM_PER_GPIO5_CLKCTRL_OFFSET		0x0104
+ + #define AM33XX_CM_PER_GPIO5_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0104)
+ + #define AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET		0x010c
+ + #define AM33XX_CM_PER_SPINLOCK_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x010c)
+ + #define AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET		0x0110
+ + #define AM33XX_CM_PER_MAILBOX0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0110)
+ + #define AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET		0x011c
+ + #define AM33XX_CM_PER_L4HS_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x011c)
+ + #define AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET		0x0120
+ + #define AM33XX_CM_PER_L4HS_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0120)
+ + #define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL_OFFSET		0x0124
+ + #define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0124)
+ + #define AM33XX_CM_PER_SLV_EXPS_CLKCTRL_OFFSET		0x0128
+ + #define AM33XX_CM_PER_SLV_EXPS_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0128)
+ + #define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET		0x012c
+ + #define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL		AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x012c)
+ + #define AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET		0x0130
+ + #define AM33XX_CM_PER_OCPWP_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0130)
+ + #define AM33XX_CM_PER_MAILBOX1_CLKCTRL_OFFSET		0x0134
+ + #define AM33XX_CM_PER_MAILBOX1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0134)
+ + #define AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET		0x0140
+ + #define AM33XX_CM_PER_PRUSS_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0140)
+ + #define AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET		0x0144
+ + #define AM33XX_CM_PER_CPSW_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0144)
+ + #define AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET		0x0148
+ + #define AM33XX_CM_PER_LCDC_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0148)
+ + #define AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET		0x014c
+ + #define AM33XX_CM_PER_CLKDIV32K_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x014c)
+ + #define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET	0x0150
+ + #define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL		AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0150)
+ + 
+ + /* CM.WKUP_CM register offsets */
+ + #define AM33XX_CM_WKUP_CLKSTCTRL_OFFSET			0x0000
+ + #define AM33XX_CM_WKUP_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0000)
+ + #define AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET		0x0004
+ + #define AM33XX_CM_WKUP_CONTROL_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0004)
+ + #define AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET		0x0008
+ + #define AM33XX_CM_WKUP_GPIO0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0008)
+ + #define AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET		0x000c
+ + #define AM33XX_CM_WKUP_L4WKUP_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x000c)
+ + #define AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET		0x0010
+ + #define AM33XX_CM_WKUP_TIMER0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0010)
+ + #define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET		0x0014
+ + #define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0014)
+ + #define AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET		0x0018
+ + #define AM33XX_CM_L3_AON_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0018)
+ + #define AM33XX_CM_AUTOIDLE_DPLL_MPU_OFFSET		0x001c
+ + #define AM33XX_CM_AUTOIDLE_DPLL_MPU			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x001c)
+ + #define AM33XX_CM_IDLEST_DPLL_MPU_OFFSET		0x0020
+ + #define AM33XX_CM_IDLEST_DPLL_MPU			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0020)
+ + #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET	0x0024
+ + #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0024)
+ + #define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET	0x0028
+ + #define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0028)
+ + #define AM33XX_CM_CLKSEL_DPLL_MPU_OFFSET		0x002c
+ + #define AM33XX_CM_CLKSEL_DPLL_MPU			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x002c)
+ + #define AM33XX_CM_AUTOIDLE_DPLL_DDR_OFFSET		0x0030
+ + #define AM33XX_CM_AUTOIDLE_DPLL_DDR			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0030)
+ + #define AM33XX_CM_IDLEST_DPLL_DDR_OFFSET		0x0034
+ + #define AM33XX_CM_IDLEST_DPLL_DDR			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0034)
+ + #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET	0x0038
+ + #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0038)
+ + #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET	0x003c
+ + #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x003c)
+ + #define AM33XX_CM_CLKSEL_DPLL_DDR_OFFSET		0x0040
+ + #define AM33XX_CM_CLKSEL_DPLL_DDR			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0040)
+ + #define AM33XX_CM_AUTOIDLE_DPLL_DISP_OFFSET		0x0044
+ + #define AM33XX_CM_AUTOIDLE_DPLL_DISP			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0044)
+ + #define AM33XX_CM_IDLEST_DPLL_DISP_OFFSET		0x0048
+ + #define AM33XX_CM_IDLEST_DPLL_DISP			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0048)
+ + #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP_OFFSET	0x004c
+ + #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x004c)
+ + #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP_OFFSET	0x0050
+ + #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0050)
+ + #define AM33XX_CM_CLKSEL_DPLL_DISP_OFFSET		0x0054
+ + #define AM33XX_CM_CLKSEL_DPLL_DISP			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0054)
+ + #define AM33XX_CM_AUTOIDLE_DPLL_CORE_OFFSET		0x0058
+ + #define AM33XX_CM_AUTOIDLE_DPLL_CORE			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0058)
+ + #define AM33XX_CM_IDLEST_DPLL_CORE_OFFSET		0x005c
+ + #define AM33XX_CM_IDLEST_DPLL_CORE			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x005c)
+ + #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET	0x0060
+ + #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0060)
+ + #define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET	0x0064
+ + #define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0064)
+ + #define AM33XX_CM_CLKSEL_DPLL_CORE_OFFSET		0x0068
+ + #define AM33XX_CM_CLKSEL_DPLL_CORE			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0068)
+ + #define AM33XX_CM_AUTOIDLE_DPLL_PER_OFFSET		0x006c
+ + #define AM33XX_CM_AUTOIDLE_DPLL_PER			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x006c)
+ + #define AM33XX_CM_IDLEST_DPLL_PER_OFFSET		0x0070
+ + #define AM33XX_CM_IDLEST_DPLL_PER			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0070)
+ + #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET	0x0074
+ + #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0074)
+ + #define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET	0x0078
+ + #define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0078)
+ + #define AM33XX_CM_CLKDCOLDO_DPLL_PER_OFFSET		0x007c
+ + #define AM33XX_CM_CLKDCOLDO_DPLL_PER			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x007c)
+ + #define AM33XX_CM_DIV_M4_DPLL_CORE_OFFSET		0x0080
+ + #define AM33XX_CM_DIV_M4_DPLL_CORE			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0080)
+ + #define AM33XX_CM_DIV_M5_DPLL_CORE_OFFSET		0x0084
+ + #define AM33XX_CM_DIV_M5_DPLL_CORE			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0084)
+ + #define AM33XX_CM_CLKMODE_DPLL_MPU_OFFSET		0x0088
+ + #define AM33XX_CM_CLKMODE_DPLL_MPU			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0088)
+ + #define AM33XX_CM_CLKMODE_DPLL_PER_OFFSET		0x008c
+ + #define AM33XX_CM_CLKMODE_DPLL_PER			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x008c)
+ + #define AM33XX_CM_CLKMODE_DPLL_CORE_OFFSET		0x0090
+ + #define AM33XX_CM_CLKMODE_DPLL_CORE			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0090)
+ + #define AM33XX_CM_CLKMODE_DPLL_DDR_OFFSET		0x0094
+ + #define AM33XX_CM_CLKMODE_DPLL_DDR			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0094)
+ + #define AM33XX_CM_CLKMODE_DPLL_DISP_OFFSET		0x0098
+ + #define AM33XX_CM_CLKMODE_DPLL_DISP			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0098)
+ + #define AM33XX_CM_CLKSEL_DPLL_PERIPH_OFFSET		0x009c
+ + #define AM33XX_CM_CLKSEL_DPLL_PERIPH			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x009c)
+ + #define AM33XX_CM_DIV_M2_DPLL_DDR_OFFSET		0x00a0
+ + #define AM33XX_CM_DIV_M2_DPLL_DDR			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a0)
+ + #define AM33XX_CM_DIV_M2_DPLL_DISP_OFFSET		0x00a4
+ + #define AM33XX_CM_DIV_M2_DPLL_DISP			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a4)
+ + #define AM33XX_CM_DIV_M2_DPLL_MPU_OFFSET		0x00a8
+ + #define AM33XX_CM_DIV_M2_DPLL_MPU			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a8)
+ + #define AM33XX_CM_DIV_M2_DPLL_PER_OFFSET		0x00ac
+ + #define AM33XX_CM_DIV_M2_DPLL_PER			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00ac)
+ + #define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET		0x00b0
+ + #define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b0)
+ + #define AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET		0x00b4
+ + #define AM33XX_CM_WKUP_UART0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b4)
+ + #define AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET		0x00b8
+ + #define AM33XX_CM_WKUP_I2C0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b8)
+ + #define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET		0x00bc
+ + #define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00bc)
+ + #define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET	0x00c0
+ + #define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c0)
+ + #define AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET		0x00c4
+ + #define AM33XX_CM_WKUP_TIMER1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c4)
+ + #define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET	0x00c8
+ + #define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c8)
+ + #define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET		0x00cc
+ + #define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00cc)
+ + #define AM33XX_CM_WKUP_WDT0_CLKCTRL_OFFSET		0x00d0
+ + #define AM33XX_CM_WKUP_WDT0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d0)
+ + #define AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET		0x00d4
+ + #define AM33XX_CM_WKUP_WDT1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d4)
+ + #define AM33XX_CM_DIV_M6_DPLL_CORE_OFFSET		0x00d8
+ + #define AM33XX_CM_DIV_M6_DPLL_CORE			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d8)
+ + 
+ + /* CM.DPLL_CM register offsets */
+ + #define AM33XX_CLKSEL_TIMER7_CLK_OFFSET			0x0004
+ + #define AM33XX_CLKSEL_TIMER7_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0004)
+ + #define AM33XX_CLKSEL_TIMER2_CLK_OFFSET			0x0008
+ + #define AM33XX_CLKSEL_TIMER2_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0008)
+ + #define AM33XX_CLKSEL_TIMER3_CLK_OFFSET			0x000c
+ + #define AM33XX_CLKSEL_TIMER3_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x000c)
+ + #define AM33XX_CLKSEL_TIMER4_CLK_OFFSET			0x0010
+ + #define AM33XX_CLKSEL_TIMER4_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0010)
+ + #define AM33XX_CM_MAC_CLKSEL_OFFSET			0x0014
+ + #define AM33XX_CM_MAC_CLKSEL				AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0014)
+ + #define AM33XX_CLKSEL_TIMER5_CLK_OFFSET			0x0018
+ + #define AM33XX_CLKSEL_TIMER5_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0018)
+ + #define AM33XX_CLKSEL_TIMER6_CLK_OFFSET			0x001c
+ + #define AM33XX_CLKSEL_TIMER6_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x001c)
+ + #define AM33XX_CM_CPTS_RFT_CLKSEL_OFFSET		0x0020
+ + #define AM33XX_CM_CPTS_RFT_CLKSEL			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0020)
+ + #define AM33XX_CLKSEL_TIMER1MS_CLK_OFFSET		0x0028
+ + #define AM33XX_CLKSEL_TIMER1MS_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0028)
+ + #define AM33XX_CLKSEL_GFX_FCLK_OFFSET			0x002c
+ + #define AM33XX_CLKSEL_GFX_FCLK				AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x002c)
+ + #define AM33XX_CLKSEL_PRUSS_OCP_CLK_OFFSET		0x0030
+ + #define AM33XX_CLKSEL_PRUSS_OCP_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0030)
+ + #define AM33XX_CLKSEL_LCDC_PIXEL_CLK_OFFSET		0x0034
+ + #define AM33XX_CLKSEL_LCDC_PIXEL_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0034)
+ + #define AM33XX_CLKSEL_WDT1_CLK_OFFSET			0x0038
+ + #define AM33XX_CLKSEL_WDT1_CLK				AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0038)
+ + #define AM33XX_CLKSEL_GPIO0_DBCLK_OFFSET		0x003c
+ + #define AM33XX_CLKSEL_GPIO0_DBCLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x003c)
+ + 
+ + /* CM.MPU_CM register offsets */
+ + #define AM33XX_CM_MPU_CLKSTCTRL_OFFSET			0x0000
+ + #define AM33XX_CM_MPU_CLKSTCTRL				AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0000)
+ + #define AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET		0x0004
+ + #define AM33XX_CM_MPU_MPU_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0004)
+ + 
+ + /* CM.DEVICE_CM register offsets */
+ + #define AM33XX_CM_CLKOUT_CTRL_OFFSET			0x0000
+ + #define AM33XX_CM_CLKOUT_CTRL				AM33XX_CM_REGADDR(AM33XX_CM_DEVICE_MOD, 0x0000)
+ + 
+ + /* CM.RTC_CM register offsets */
+ + #define AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET		0x0000
+ + #define AM33XX_CM_RTC_RTC_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0000)
+ + #define AM33XX_CM_RTC_CLKSTCTRL_OFFSET			0x0004
+ + #define AM33XX_CM_RTC_CLKSTCTRL				AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0004)
+ + 
+ + /* CM.GFX_CM register offsets */
+ + #define AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET		0x0000
+ + #define AM33XX_CM_GFX_L3_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0000)
+ + #define AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET		0x0004
+ + #define AM33XX_CM_GFX_GFX_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0004)
+ + #define AM33XX_CM_GFX_BITBLT_CLKCTRL_OFFSET		0x0008
+ + #define AM33XX_CM_GFX_BITBLT_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0008)
+ + #define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET	0x000c
+ + #define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1		AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x000c)
+ + #define AM33XX_CM_GFX_MMUCFG_CLKCTRL_OFFSET		0x0010
+ + #define AM33XX_CM_GFX_MMUCFG_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0010)
+ + #define AM33XX_CM_GFX_MMUDATA_CLKCTRL_OFFSET		0x0014
+ + #define AM33XX_CM_GFX_MMUDATA_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0014)
+ + 
+ + /* CM.CEFUSE_CM register offsets */
+ + #define AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET		0x0000
+ + #define AM33XX_CM_CEFUSE_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0000)
+ + #define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET		0x0020
+ + #define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0020)
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/cm44xx.h linux-3.2.1/arch/arm/mach-ckb_3352/cm44xx.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/cm44xx.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/cm44xx.h	2014-11-25 13:19:14.867996012 +0900
+ ***************
+ *** 0 ****
+ --- 1,26 ----
+ + /*
+ +  * OMAP4 Clock Management (CM) definitions
+ +  *
+ +  * Copyright (C) 2007-2011 Texas Instruments, Inc.
+ +  * Copyright (C) 2007-2009 Nokia Corporation
+ +  *
+ +  * Written by Paul Walmsley
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  *
+ +  * OMAP4 has two separate CM blocks, CM1 and CM2.  This file contains
+ +  * macros and function prototypes that are applicable to both.
+ +  */
+ + #ifndef __ARCH_ASM_MACH_OMAP2_CM44XX_H
+ + #define __ARCH_ASM_MACH_OMAP2_CM44XX_H
+ + 
+ + 
+ + #include "prcm-common.h"
+ + #include "cm.h"
+ + 
+ + #define OMAP4_CM_CLKSTCTRL				0x0000
+ + #define OMAP4_CM_STATICDEP				0x0004
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/cm.h linux-3.2.1/arch/arm/mach-ckb_3352/cm.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/cm.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/cm.h	2014-11-25 13:19:14.867996012 +0900
+ ***************
+ *** 0 ****
+ --- 1,25 ----
+ + /*
+ +  * OMAP2+ Clock Management prototypes
+ +  *
+ +  * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ +  * Copyright (C) 2007-2009 Nokia Corporation
+ +  *
+ +  * Written by Paul Walmsley
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + #ifndef __ARCH_ASM_MACH_OMAP2_CM_H
+ + #define __ARCH_ASM_MACH_OMAP2_CM_H
+ + 
+ + /*
+ +  * MAX_MODULE_READY_TIME: max duration in microseconds to wait for the
+ +  * PRCM to request that a module exit the inactive state in the case of
+ +  * OMAP2 & 3.
+ +  * In the case of OMAP4 this is the max duration in microseconds for the
+ +  * module to reach the functionnal state from an inactive state.
+ +  */
+ + #define MAX_MODULE_READY_TIME		2000
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/cminst33xx.h linux-3.2.1/arch/arm/mach-ckb_3352/cminst33xx.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/cminst33xx.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/cminst33xx.h	2014-11-25 13:19:14.867996012 +0900
+ ***************
+ *** 0 ****
+ --- 1,63 ----
+ + /*
+ +  * am33xx Clock Management (CM) function prototypes
+ +  *
+ +  * Copyright (C) 2010 Nokia Corporation
+ +  * Paul Walmsley
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + #ifndef __ARCH_ASM_MACH_OMAP2_CMINST33XX_H
+ + #define __ARCH_ASM_MACH_OMAP2_CMINST33XX_H
+ + 
+ + extern bool am33xx_cminst_is_clkdm_in_hwsup(s16 inst, u16 cdoffs);
+ + extern void am33xx_cminst_clkdm_enable_hwsup(s16 inst, u16 cdoffs);
+ + extern void am33xx_cminst_clkdm_disable_hwsup(s16 inst, u16 cdoffs);
+ + extern void am33xx_cminst_clkdm_force_sleep(s16 inst, u16 cdoffs);
+ + extern void am33xx_cminst_clkdm_force_wakeup(s16 inst, u16 cdoffs);
+ + 
+ + extern int am33xx_cminst_wait_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs);
+ + 
+ + #ifdef CONFIG_SOC_OMAPAM33XX
+ + extern int am33xx_cminst_wait_module_idle(u16 inst, s16 cdoffs,
+ + 					 u16 clkctrl_offs);
+ + 
+ + extern void am33xx_cminst_module_enable(u8 mode, u16 inst, s16 cdoffs,
+ + 				       u16 clkctrl_offs);
+ + extern void am33xx_cminst_module_disable(u16 inst, s16 cdoffs,
+ + 					u16 clkctrl_offs);
+ + 
+ + #else
+ + 
+ + static inline int am33xx_cminst_wait_module_idle(u16 inst, s16 cdoffs,
+ + 					u16 clkctrl_offs)
+ + {
+ + 	return 0;
+ + }
+ + 
+ + static inline void am33xx_cminst_module_enable(u8 mode, u16 inst,
+ + 				s16 cdoffs, u16 clkctrl_offs)
+ + {
+ + }
+ + 
+ + static inline void am33xx_cminst_module_disable(u16 inst, s16 cdoffs,
+ + 				 u16 clkctrl_offs)
+ + {
+ + }
+ + 
+ + #endif
+ + 
+ + /*
+ +  * In an ideal world, we would not export these low-level functions,
+ +  * but this will probably take some time to fix properly
+ +  */
+ + extern u32 am33xx_cminst_read_inst_reg(s16 inst, u16 idx);
+ + extern void am33xx_cminst_write_inst_reg(u32 val, s16 inst, u16 idx);
+ + extern u32 am33xx_cminst_rmw_inst_reg_bits(u32 mask, u32 bits,
+ + 					   s16 inst, s16 idx);
+ + extern u32 am33xx_cminst_set_inst_reg_bits(u32 bits, s16 inst, s16 idx);
+ + extern u32 am33xx_cminst_clear_inst_reg_bits(u32 bits, s16 inst, s16 idx);
+ + extern u32 am33xx_cminst_read_inst_reg_bits(u16 inst, s16 idx, u32 mask);
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/cminst44xx.c linux-3.2.1/arch/arm/mach-ckb_3352/cminst44xx.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/cminst44xx.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/cminst44xx.c	2014-11-25 13:19:14.867996012 +0900
+ ***************
+ *** 0 ****
+ --- 1,317 ----
+ + /*
+ +  * OMAP4 CM instance functions
+ +  *
+ +  * Copyright (C) 2009 Nokia Corporation
+ +  * Copyright (C) 2011 Texas Instruments, Inc.
+ +  * Paul Walmsley
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  *
+ +  * This is needed since CM instances can be in the PRM, PRCM_MPU, CM1,
+ +  * or CM2 hardware modules.  For example, the EMU_CM CM instance is in
+ +  * the PRM hardware module.  What a mess...
+ +  */
+ + 
+ + #include <linux/kernel.h>
+ + #include <linux/types.h>
+ + #include <linux/errno.h>
+ + #include <linux/err.h>
+ + #include <linux/io.h>
+ + 
+ + #include "common.h"
+ + 
+ + #include "cm.h"
+ + #include "cm44xx.h"
+ + #include "cminst44xx.h"
+ + #include "cm-regbits-34xx.h"
+ + #include "cm-regbits-44xx.h"
+ + #include "prcm44xx.h"
+ + //#include "prm44xx.h"
+ + #include "prm33xx.h"
+ + 
+ + /*
+ +  * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield:
+ +  *
+ +  *   0x0 func:     Module is fully functional, including OCP
+ +  *   0x1 trans:    Module is performing transition: wakeup, or sleep, or sleep
+ +  *                 abortion
+ +  *   0x2 idle:     Module is in Idle mode (only OCP part). It is functional if
+ +  *                 using separate functional clock
+ +  *   0x3 disabled: Module is disabled and cannot be accessed
+ +  *
+ +  */
+ + #define CLKCTRL_IDLEST_FUNCTIONAL		0x0
+ + #define CLKCTRL_IDLEST_INTRANSITION		0x1
+ + #define CLKCTRL_IDLEST_INTERFACE_IDLE		0x2
+ + #define CLKCTRL_IDLEST_DISABLED			0x3
+ + 
+ + static u32 **_cm_bases;
+ + static u32 max_cm_partitions;
+ + 
+ + static u32 *am33xx_cm_bases[] = {
+ + 	[OMAP4430_INVALID_PRCM_PARTITION]	= 0,
+ + 	[AM33XX_PRM_PARTITION]			= AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRM_BASE),
+ + };
+ + 
+ + /* Private functions */
+ + 
+ + /**
+ +  * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield
+ +  * @part: PRCM partition ID that the CM_CLKCTRL register exists in
+ +  * @inst: CM instance register offset (*_INST macro)
+ +  * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ +  * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
+ +  *
+ +  * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to
+ +  * bit 0.
+ +  */
+ + static u32 _clkctrl_idlest(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
+ + {
+ + 	u32 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
+ + 	v &= OMAP4430_IDLEST_MASK;
+ + 	v >>= OMAP4430_IDLEST_SHIFT;
+ + 	return v;
+ + }
+ + 
+ + /**
+ +  * _is_module_ready - can module registers be accessed without causing an abort?
+ +  * @part: PRCM partition ID that the CM_CLKCTRL register exists in
+ +  * @inst: CM instance register offset (*_INST macro)
+ +  * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ +  * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
+ +  *
+ +  * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either
+ +  * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise.
+ +  */
+ + static bool _is_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
+ + {
+ + 	u32 v;
+ + 
+ + 	v = _clkctrl_idlest(part, inst, cdoffs, clkctrl_offs);
+ + 
+ + 	return (v == CLKCTRL_IDLEST_FUNCTIONAL ||
+ + 		v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false;
+ + }
+ + 
+ + /* Public functions */
+ + 
+ + /* Read a register in a CM instance */
+ + u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx)
+ + {
+ + 	BUG_ON(part >= max_cm_partitions ||
+ + 	       part == OMAP4430_INVALID_PRCM_PARTITION ||
+ + 	       !_cm_bases[part]);
+ + 	return __raw_readl(_cm_bases[part] + ((inst + idx)/sizeof(u32)));
+ + }
+ + 
+ + /* Write into a register in a CM instance */
+ + void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
+ + {
+ + 	BUG_ON(part >= max_cm_partitions ||
+ + 	       part == OMAP4430_INVALID_PRCM_PARTITION ||
+ + 	       !_cm_bases[part]);
+ + 	__raw_writel(val, _cm_bases[part] + ((inst + idx)/sizeof(u32)));
+ + }
+ + 
+ + 
+ + /*
+ +  *
+ +  */
+ + 
+ + /**
+ +  * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield
+ +  * @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted)
+ +  * @part: PRCM partition ID that the CM_CLKSTCTRL register exists in
+ +  * @inst: CM instance register offset (*_INST macro)
+ +  * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ +  *
+ +  * @c must be the unshifted value for CLKTRCTRL - i.e., this function
+ +  * will handle the shift itself.
+ +  */
+ + static void _clktrctrl_write(u8 c, u8 part, s16 inst, u16 cdoffs)
+ + {
+ + 	u32 v;
+ + 
+ + 	v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL);
+ + 	v &= ~OMAP4430_CLKTRCTRL_MASK;
+ + 	v |= c << OMAP4430_CLKTRCTRL_SHIFT;
+ + 	omap4_cminst_write_inst_reg(v, part, inst, cdoffs + OMAP4_CM_CLKSTCTRL);
+ + }
+ + 
+ + /**
+ +  * omap4_cminst_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode?
+ +  * @part: PRCM partition ID that the CM_CLKSTCTRL register exists in
+ +  * @inst: CM instance register offset (*_INST macro)
+ +  * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ +  *
+ +  * Returns true if the clockdomain referred to by (@part, @inst, @cdoffs)
+ +  * is in hardware-supervised idle mode, or 0 otherwise.
+ +  */
+ + bool omap4_cminst_is_clkdm_in_hwsup(u8 part, s16 inst, u16 cdoffs)
+ + {
+ + 	u32 v;
+ + 
+ + 	v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL);
+ + 	v &= OMAP4430_CLKTRCTRL_MASK;
+ + 	v >>= OMAP4430_CLKTRCTRL_SHIFT;
+ + 
+ + 	return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false;
+ + }
+ + 
+ + /**
+ +  * omap4_cminst_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode
+ +  * @part: PRCM partition ID that the clockdomain registers exist in
+ +  * @inst: CM instance register offset (*_INST macro)
+ +  * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ +  *
+ +  * Put a clockdomain referred to by (@part, @inst, @cdoffs) into
+ +  * hardware-supervised idle mode.  No return value.
+ +  */
+ + void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs)
+ + {
+ + 	_clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, part, inst, cdoffs);
+ + }
+ + 
+ + /**
+ +  * omap4_cminst_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode
+ +  * @part: PRCM partition ID that the clockdomain registers exist in
+ +  * @inst: CM instance register offset (*_INST macro)
+ +  * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ +  *
+ +  * Put a clockdomain referred to by (@part, @inst, @cdoffs) into
+ +  * software-supervised idle mode, i.e., controlled manually by the
+ +  * Linux OMAP clockdomain code.  No return value.
+ +  */
+ + void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs)
+ + {
+ + 	_clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, part, inst, cdoffs);
+ + }
+ + 
+ + /**
+ +  * omap4_cminst_clkdm_force_sleep - try to put a clockdomain into idle
+ +  * @part: PRCM partition ID that the clockdomain registers exist in
+ +  * @inst: CM instance register offset (*_INST macro)
+ +  * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ +  *
+ +  * Put a clockdomain referred to by (@part, @inst, @cdoffs) into idle
+ +  * No return value.
+ +  */
+ + void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs)
+ + {
+ + 	_clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, part, inst, cdoffs);
+ + }
+ + 
+ + /**
+ +  * omap4_cminst_clkdm_force_sleep - try to take a clockdomain out of idle
+ +  * @part: PRCM partition ID that the clockdomain registers exist in
+ +  * @inst: CM instance register offset (*_INST macro)
+ +  * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ +  *
+ +  * Take a clockdomain referred to by (@part, @inst, @cdoffs) out of idle,
+ +  * waking it up.  No return value.
+ +  */
+ + void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs)
+ + {
+ + 	_clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs);
+ + }
+ + 
+ + /*
+ +  *
+ +  */
+ + 
+ + /**
+ +  * omap4_cminst_wait_module_ready - wait for a module to be in 'func' state
+ +  * @part: PRCM partition ID that the CM_CLKCTRL register exists in
+ +  * @inst: CM instance register offset (*_INST macro)
+ +  * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ +  * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
+ +  *
+ +  * Wait for the module IDLEST to be functional. If the idle state is in any
+ +  * the non functional state (trans, idle or disabled), module and thus the
+ +  * sysconfig cannot be accessed and will probably lead to an "imprecise
+ +  * external abort"
+ +  */
+ + int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs,
+ + 				   u16 clkctrl_offs)
+ + {
+ + 	int i = 0;
+ + 
+ + 	omap_test_timeout(_is_module_ready(part, inst, cdoffs, clkctrl_offs),
+ + 			  MAX_MODULE_READY_TIME, i);
+ + 
+ + 	return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
+ + }
+ + 
+ + /**
+ +  * omap4_cminst_wait_module_idle - wait for a module to be in 'disabled'
+ +  * state
+ +  * @part: PRCM partition ID that the CM_CLKCTRL register exists in
+ +  * @inst: CM instance register offset (*_INST macro)
+ +  * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ +  * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
+ +  *
+ +  * Wait for the module IDLEST to be disabled. Some PRCM transition,
+ +  * like reset assertion or parent clock de-activation must wait the
+ +  * module to be fully disabled.
+ +  */
+ + int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
+ + {
+ + 	int i = 0;
+ + 
+ + 	if (!clkctrl_offs)
+ + 		return 0;
+ + 
+ + 	omap_test_timeout((_clkctrl_idlest(part, inst, cdoffs, clkctrl_offs) ==
+ + 			   CLKCTRL_IDLEST_DISABLED),
+ + 			  MAX_MODULE_READY_TIME, i);
+ + 
+ + 	return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
+ + }
+ + 
+ + /**
+ +  * omap4_cminst_module_enable - Enable the modulemode inside CLKCTRL
+ +  * @mode: Module mode (SW or HW)
+ +  * @part: PRCM partition ID that the CM_CLKCTRL register exists in
+ +  * @inst: CM instance register offset (*_INST macro)
+ +  * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ +  * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
+ +  *
+ +  * No return value.
+ +  */
+ + void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs,
+ + 			    u16 clkctrl_offs)
+ + {
+ + 	u32 v;
+ + 
+ + 	v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
+ + 	v &= ~OMAP4430_MODULEMODE_MASK;
+ + 	v |= mode << OMAP4430_MODULEMODE_SHIFT;
+ + 	omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs);
+ + }
+ + 
+ + /**
+ +  * omap4_cminst_module_disable - Disable the module inside CLKCTRL
+ +  * @part: PRCM partition ID that the CM_CLKCTRL register exists in
+ +  * @inst: CM instance register offset (*_INST macro)
+ +  * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ +  * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
+ +  *
+ +  * No return value.
+ +  */
+ + void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
+ + 			     u16 clkctrl_offs)
+ + {
+ + 	u32 v;
+ + 
+ + 	v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
+ + 	v &= ~OMAP4430_MODULEMODE_MASK;
+ + 	omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs);
+ + }
+ + 
+ + void __init omap44xx_cminst_init(void)
+ + {
+ + 	_cm_bases = am33xx_cm_bases;
+ + 	max_cm_partitions = ARRAY_SIZE(am33xx_cm_bases);
+ + }
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/cminst44xx.h linux-3.2.1/arch/arm/mach-ckb_3352/cminst44xx.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/cminst44xx.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/cminst44xx.h	2014-11-25 13:19:14.867996012 +0900
+ ***************
+ *** 0 ****
+ --- 1,39 ----
+ + /*
+ +  * OMAP4 Clock Management (CM) function prototypes
+ +  *
+ +  * Copyright (C) 2010 Nokia Corporation
+ +  * Paul Walmsley
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + #ifndef __ARCH_ASM_MACH_OMAP2_CMINST44XX_H
+ + #define __ARCH_ASM_MACH_OMAP2_CMINST44XX_H
+ + 
+ + extern bool omap4_cminst_is_clkdm_in_hwsup(u8 part, s16 inst, u16 cdoffs);
+ + extern void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs);
+ + extern void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs);
+ + extern void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs);
+ + extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs);
+ + 
+ + extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
+ + 
+ + extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs,
+ + 					 u16 clkctrl_offs);
+ + 
+ + extern void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs,
+ + 				       u16 clkctrl_offs);
+ + extern void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
+ + 					u16 clkctrl_offs);
+ + 
+ + 
+ + /*
+ +  * In an ideal world, we would not export these low-level functions,
+ +  * but this will probably take some time to fix properly
+ +  */
+ + extern u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx);
+ + extern void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx);
+ + 
+ + extern void __init omap44xx_cminst_init(void);
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/cm-regbits-33xx.h linux-3.2.1/arch/arm/mach-ckb_3352/cm-regbits-33xx.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/cm-regbits-33xx.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/cm-regbits-33xx.h	2014-11-25 13:19:14.872994625 +0900
+ ***************
+ *** 0 ****
+ --- 1,683 ----
+ + /*
+ +  * AM33XX Power Management register bits
+ +  *
+ +  * This file is automatically generated from the AM33XX hardware databases.
+ +  *
+ +  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + 
+ + #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
+ + #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
+ + 
+ + /*
+ +  * Used by CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_DDR, CM_AUTOIDLE_DPLL_DISP,
+ +  * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER
+ +  */
+ + #define AM33XX_AUTO_DPLL_MODE_SHIFT			0
+ + #define AM33XX_AUTO_DPLL_MODE_MASK			(0x7 << 0)
+ + 
+ + /* Used by CM_WKUP_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT		14
+ + #define AM33XX_CLKACTIVITY_ADC_FCLK_MASK		(1 << 16)
+ + 
+ + /* Used by CM_PER_L4LS_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT		11
+ + #define AM33XX_CLKACTIVITY_CAN_CLK_MASK			(1 << 11)
+ + 
+ + /* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT		4
+ + #define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK		(1 << 4)
+ + 
+ + /* Used by CM_PER_CPSW_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT	4
+ + #define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK	(1 << 4)
+ + 
+ + /* Used by CM_PER_L4HS_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT	4
+ + #define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK	(1 << 4)
+ + 
+ + /* Used by CM_PER_L4HS_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT	5
+ + #define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK		(1 << 5)
+ + 
+ + /* Used by CM_PER_L4HS_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT		6
+ + #define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK		(1 << 6)
+ + 
+ + /* Used by CM_PER_L3_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT		6
+ + #define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK		(1 << 6)
+ + 
+ + /* Used by CM_CEFUSE_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT	9
+ + #define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK	(1 << 9)
+ + 
+ + /* Used by CM_L3_AON_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT		2
+ + #define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK		(1 << 2)
+ + 
+ + /* Used by CM_L3_AON_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT		4
+ + #define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK		(1 << 4)
+ + 
+ + /* Used by CM_PER_L3_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT		2
+ + #define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK		(1 << 2)
+ + 
+ + /* Used by CM_GFX_L3_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT		9
+ + #define AM33XX_CLKACTIVITY_GFX_FCLK_MASK		(1 << 9)
+ + 
+ + /* Used by CM_GFX_L3_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT		8
+ + #define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK		(1 << 8)
+ + 
+ + /* Used by CM_WKUP_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT		8
+ + #define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK		(1 << 8)
+ + 
+ + /* Used by CM_PER_L4LS_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT		19
+ + #define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK		(1 << 19)
+ + 
+ + /* Used by CM_PER_L4LS_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT		20
+ + #define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK		(1 << 20)
+ + 
+ + /* Used by CM_PER_L4LS_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT		21
+ + #define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK		(1 << 21)
+ + 
+ + /* Used by CM_PER_L4LS_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT		22
+ + #define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK		(1 << 22)
+ + 
+ + /* Used by CM_PER_L4LS_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT		26
+ + #define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK		(1 << 26)
+ + 
+ + /* Used by CM_PER_L4LS_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT		18
+ + #define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK		(1 << 18)
+ + 
+ + /* Used by CM_WKUP_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT		11
+ + #define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK		(1 << 11)
+ + 
+ + /* Used by CM_PER_L4LS_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT		24
+ + #define AM33XX_CLKACTIVITY_I2C_FCLK_MASK		(1 << 24)
+ + 
+ + /* Used by CM_PER_PRUSS_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT		5
+ + #define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK		(1 << 5)
+ + 
+ + /* Used by CM_PER_PRUSS_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT		4
+ + #define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK		(1 << 4)
+ + 
+ + /* Used by CM_PER_PRUSS_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT	6
+ + #define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK		(1 << 6)
+ + 
+ + /* Used by CM_PER_L3S_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT		3
+ + #define AM33XX_CLKACTIVITY_L3S_GCLK_MASK		(1 << 3)
+ + 
+ + /* Used by CM_L3_AON_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT		3
+ + #define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK		(1 << 3)
+ + 
+ + /* Used by CM_PER_L3_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT		4
+ + #define AM33XX_CLKACTIVITY_L3_GCLK_MASK			(1 << 4)
+ + 
+ + /* Used by CM_PER_L4FW_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT		8
+ + #define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK		(1 << 8)
+ + 
+ + /* Used by CM_PER_L4HS_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT		3
+ + #define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK		(1 << 3)
+ + 
+ + /* Used by CM_PER_L4LS_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT		8
+ + #define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK		(1 << 8)
+ + 
+ + /* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */
+ + #define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT		8
+ + #define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK		(1 << 8)
+ + 
+ + /* Used by CM_CEFUSE_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT	8
+ + #define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK		(1 << 8)
+ + 
+ + /* Used by CM_RTC_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT		8
+ + #define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK		(1 << 8)
+ + 
+ + /* Used by CM_L4_WKUP_AON_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT	2
+ + #define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK	(1 << 2)
+ + 
+ + /* Used by CM_WKUP_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT		2
+ + #define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK		(1 << 2)
+ + 
+ + /* Used by CM_PER_L4LS_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT		17
+ + #define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK		(1 << 17)
+ + 
+ + /* Used by CM_PER_LCDC_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT	4
+ + #define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK	(1 << 4)
+ + 
+ + /* Used by CM_PER_LCDC_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT	5
+ + #define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK	(1 << 5)
+ + 
+ + /* Used by CM_PER_L3_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT		7
+ + #define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK		(1 << 7)
+ + 
+ + /* Used by CM_PER_L3_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT		3
+ + #define AM33XX_CLKACTIVITY_MMC_FCLK_MASK		(1 << 3)
+ + 
+ + /* Used by CM_MPU_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT		2
+ + #define AM33XX_CLKACTIVITY_MPU_CLK_MASK			(1 << 2)
+ + 
+ + /* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT		4
+ + #define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK		(1 << 4)
+ + 
+ + /* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT		5
+ + #define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK		(1 << 5)
+ + 
+ + /* Used by CM_RTC_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT		9
+ + #define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK		(1 << 9)
+ + 
+ + /* Used by CM_PER_L4LS_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT		25
+ + #define AM33XX_CLKACTIVITY_SPI_GCLK_MASK		(1 << 25)
+ + 
+ + /* Used by CM_WKUP_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT		3
+ + #define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK		(1 << 3)
+ + 
+ + /* Used by CM_WKUP_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT		10
+ + #define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK		(1 << 10)
+ + 
+ + /* Used by CM_WKUP_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT		13
+ + #define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK		(1 << 13)
+ + 
+ + /* Used by CM_PER_L4LS_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT		14
+ + #define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK		(1 << 14)
+ + 
+ + /* Used by CM_PER_L4LS_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT		15
+ + #define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK		(1 << 15)
+ + 
+ + /* Used by CM_PER_L4LS_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT		16
+ + #define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK		(1 << 16)
+ + 
+ + /* Used by CM_PER_L4LS_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT		27
+ + #define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK		(1 << 27)
+ + 
+ + /* Used by CM_PER_L4LS_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT		28
+ + #define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK		(1 << 28)
+ + 
+ + /* Used by CM_PER_L4LS_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT		13
+ + #define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK		(1 << 13)
+ + 
+ + /* Used by CM_WKUP_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT		12
+ + #define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK		(1 << 12)
+ + 
+ + /* Used by CM_PER_L4LS_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT		10
+ + #define AM33XX_CLKACTIVITY_UART_GFCLK_MASK		(1 << 10)
+ + 
+ + /* Used by CM_WKUP_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT		9
+ + #define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK		(1 << 9)
+ + 
+ + /* Used by CM_WKUP_CLKSTCTRL */
+ + #define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT		4
+ + #define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK		(1 << 4)
+ + 
+ + /* Used by CLKSEL_GFX_FCLK */
+ + #define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT		0
+ + #define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK			(1 << 0)
+ + 
+ + /* Used by CM_CLKOUT_CTRL */
+ + #define AM33XX_CLKOUT2DIV_SHIFT				3
+ + #define AM33XX_CLKOUT2DIV_MASK				(0x05 << 3)
+ + 
+ + /* Used by CM_CLKOUT_CTRL */
+ + #define AM33XX_CLKOUT2EN_SHIFT				7
+ + #define AM33XX_CLKOUT2EN_MASK				(1 << 7)
+ + 
+ + /* Used by CM_CLKOUT_CTRL */
+ + #define AM33XX_CLKOUT2SOURCE_SHIFT			0
+ + #define AM33XX_CLKOUT2SOURCE_MASK			(0x02 << 0)
+ + 
+ + /*
+ +  * Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK,
+ +  * CLKSEL_TIMER3_CLK, CLKSEL_TIMER4_CLK, CLKSEL_TIMER5_CLK, CLKSEL_TIMER6_CLK,
+ +  * CLKSEL_TIMER7_CLK
+ +  */
+ + #define AM33XX_CLKSEL_SHIFT				0
+ + #define AM33XX_CLKSEL_MASK				(0x01 << 0)
+ + 
+ + /*
+ +  * Renamed from CLKSEL Used by CLKSEL_PRUSS_OCP_CLK, CLKSEL_WDT1_CLK,
+ +  * CM_CPTS_RFT_CLKSEL
+ +  */
+ + #define AM33XX_CLKSEL_0_0_SHIFT				0
+ + #define AM33XX_CLKSEL_0_0_MASK				(1 << 0)
+ + 
+ + #define AM33XX_CLKSEL_0_1_SHIFT				0
+ + #define AM33XX_CLKSEL_0_1_MASK				(3 << 0)
+ + 
+ + /* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */
+ + #define AM33XX_CLKSEL_0_2_SHIFT				0
+ + #define AM33XX_CLKSEL_0_2_MASK				(7 << 0)
+ + 
+ + /* Used by CLKSEL_GFX_FCLK */
+ + #define AM33XX_CLKSEL_GFX_FCLK_SHIFT			1
+ + #define AM33XX_CLKSEL_GFX_FCLK_MASK			(1 << 1)
+ + 
+ + /*
+ +  * Used by CM_MPU_CLKSTCTRL, CM_RTC_CLKSTCTRL, CM_PER_CLK_24MHZ_CLKSTCTRL,
+ +  * CM_PER_CPSW_CLKSTCTRL, CM_PER_PRUSS_CLKSTCTRL, CM_PER_L3S_CLKSTCTRL,
+ +  * CM_PER_L3_CLKSTCTRL, CM_PER_L4FW_CLKSTCTRL, CM_PER_L4HS_CLKSTCTRL,
+ +  * CM_PER_L4LS_CLKSTCTRL, CM_PER_LCDC_CLKSTCTRL, CM_PER_OCPWP_L3_CLKSTCTRL,
+ +  * CM_L3_AON_CLKSTCTRL, CM_L4_WKUP_AON_CLKSTCTRL, CM_WKUP_CLKSTCTRL,
+ +  * CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL
+ +  */
+ + #define AM33XX_CLKTRCTRL_SHIFT				0
+ + #define AM33XX_CLKTRCTRL_MASK				(0x3 << 0)
+ + 
+ + /*
+ +  * Used by CM_SSC_DELTAMSTEP_DPLL_CORE, CM_SSC_DELTAMSTEP_DPLL_DDR,
+ +  * CM_SSC_DELTAMSTEP_DPLL_DISP, CM_SSC_DELTAMSTEP_DPLL_MPU,
+ +  * CM_SSC_DELTAMSTEP_DPLL_PER
+ +  */
+ + #define AM33XX_DELTAMSTEP_SHIFT				0
+ + #define AM33XX_DELTAMSTEP_MASK				(0x19 << 0)
+ + 
+ + /* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */
+ + #define AM33XX_DPLL_BYP_CLKSEL_SHIFT			23
+ + #define AM33XX_DPLL_BYP_CLKSEL_MASK			(1 << 23)
+ + 
+ + /* Used by CM_CLKDCOLDO_DPLL_PER */
+ + #define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT		8
+ + #define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK		(1 << 8)
+ + 
+ + /* Used by CM_CLKDCOLDO_DPLL_PER */
+ + #define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT		12
+ + #define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK			(1 << 12)
+ + 
+ + /* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
+ + #define AM33XX_DPLL_CLKOUT_DIV_SHIFT			0
+ + #define AM33XX_DPLL_CLKOUT_DIV_MASK			(0x1f << 0)
+ + 
+ + /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */
+ + #define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT		0
+ + #define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK			(0x06 << 0)
+ + 
+ + /* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
+ + #define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT		5
+ + #define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK		(1 << 5)
+ + 
+ + /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */
+ + #define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT	7
+ + #define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK		(1 << 7)
+ + 
+ + /*
+ +  * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU,
+ +  * CM_DIV_M2_DPLL_PER
+ +  */
+ + #define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT		8
+ + #define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK		(1 << 8)
+ + 
+ + /*
+ +  * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP,
+ +  * CM_CLKSEL_DPLL_MPU
+ +  */
+ + #define AM33XX_DPLL_DIV_SHIFT				0
+ + #define AM33XX_DPLL_DIV_MASK				(0x7f << 0)
+ + 
+ + #define AM33XX_DPLL_PER_DIV_MASK			(0xff << 0)
+ + 
+ + /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */
+ + #define AM33XX_DPLL_DIV_0_7_SHIFT			0
+ + #define AM33XX_DPLL_DIV_0_7_MASK			(0x07 << 0)
+ + 
+ + /*
+ +  * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
+ +  * CM_CLKMODE_DPLL_MPU
+ +  */
+ + #define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT			8
+ + #define AM33XX_DPLL_DRIFTGUARD_EN_MASK			(1 << 8)
+ + 
+ + /*
+ +  * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
+ +  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
+ +  */
+ + #define AM33XX_DPLL_EN_SHIFT				0
+ + #define AM33XX_DPLL_EN_MASK				(0x7 << 0)
+ + 
+ + /*
+ +  * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
+ +  * CM_CLKMODE_DPLL_MPU
+ +  */
+ + #define AM33XX_DPLL_LPMODE_EN_SHIFT			10
+ + #define AM33XX_DPLL_LPMODE_EN_MASK			(1 << 10)
+ + 
+ + /*
+ +  * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP,
+ +  * CM_CLKSEL_DPLL_MPU
+ +  */
+ + #define AM33XX_DPLL_MULT_SHIFT				8
+ + #define AM33XX_DPLL_MULT_MASK				(0x7ff << 8)
+ + 
+ + /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */
+ + #define AM33XX_DPLL_MULT_PERIPH_SHIFT			8
+ + #define AM33XX_DPLL_MULT_PERIPH_MASK			(0xfff << 8)
+ + 
+ + /*
+ +  * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
+ +  * CM_CLKMODE_DPLL_MPU
+ +  */
+ + #define AM33XX_DPLL_REGM4XEN_SHIFT			11
+ + #define AM33XX_DPLL_REGM4XEN_MASK			(1 << 11)
+ + 
+ + /* Used by CM_CLKSEL_DPLL_PERIPH */
+ + #define AM33XX_DPLL_SD_DIV_SHIFT			24
+ + #define AM33XX_DPLL_SD_DIV_MASK				(24, 31)
+ + 
+ + /*
+ +  * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
+ +  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
+ +  */
+ + #define AM33XX_DPLL_SSC_ACK_SHIFT			13
+ + #define AM33XX_DPLL_SSC_ACK_MASK			(1 << 13)
+ + 
+ + /*
+ +  * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
+ +  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
+ +  */
+ + #define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT		14
+ + #define AM33XX_DPLL_SSC_DOWNSPREAD_MASK			(1 << 14)
+ + 
+ + /*
+ +  * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
+ +  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
+ +  */
+ + #define AM33XX_DPLL_SSC_EN_SHIFT			12
+ + #define AM33XX_DPLL_SSC_EN_MASK				(1 << 12)
+ + 
+ + /* Used by CM_DIV_M4_DPLL_CORE */
+ + #define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT		0
+ + #define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK		(0x1f << 0)
+ + 
+ + /* Used by CM_DIV_M4_DPLL_CORE */
+ + #define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT		5
+ + #define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK		(1 << 5)
+ + 
+ + /* Used by CM_DIV_M4_DPLL_CORE */
+ + #define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT	8
+ + #define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK		(1 << 8)
+ + 
+ + /* Used by CM_DIV_M4_DPLL_CORE */
+ + #define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT		12
+ + #define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK		(1 << 12)
+ + 
+ + /* Used by CM_DIV_M5_DPLL_CORE */
+ + #define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT		0
+ + #define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK		(0x1f << 0)
+ + 
+ + /* Used by CM_DIV_M5_DPLL_CORE */
+ + #define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT		5
+ + #define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK		(1 << 5)
+ + 
+ + /* Used by CM_DIV_M5_DPLL_CORE */
+ + #define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT	8
+ + #define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK		(1 << 8)
+ + 
+ + /* Used by CM_DIV_M5_DPLL_CORE */
+ + #define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT		12
+ + #define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK		(1 << 12)
+ + 
+ + /* Used by CM_DIV_M6_DPLL_CORE */
+ + #define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT		0
+ + #define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK		(0x04 << 0)
+ + 
+ + /* Used by CM_DIV_M6_DPLL_CORE */
+ + #define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT		5
+ + #define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK		(1 << 5)
+ + 
+ + /* Used by CM_DIV_M6_DPLL_CORE */
+ + #define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT	8
+ + #define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK		(1 << 8)
+ + 
+ + /* Used by CM_DIV_M6_DPLL_CORE */
+ + #define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT		12
+ + #define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK		(1 << 12)
+ + 
+ + /*
+ +  * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
+ +  * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL,
+ +  * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL,
+ +  * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL,
+ +  * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL,
+ +  * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL,
+ +  * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL,
+ +  * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL,
+ +  * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL,
+ +  * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL,
+ +  * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL,
+ +  * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL,
+ +  * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL,
+ +  * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL,
+ +  * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
+ +  * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL,
+ +  * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL,
+ +  * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL,
+ +  * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL,
+ +  * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL,
+ +  * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL,
+ +  * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
+ +  * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL,
+ +  * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL,
+ +  * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL,
+ +  * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL,
+ +  * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL,
+ +  * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL,
+ +  * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL,
+ +  * CM_WKUP_WDT1_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL,
+ +  * CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL
+ +  */
+ + #define AM33XX_IDLEST_SHIFT				16
+ + #define AM33XX_IDLEST_MASK				(0x3 << 16)
+ + #define AM33XX_IDLEST_VAL				0x3
+ + 
+ + /* Used by CM_MAC_CLKSEL */
+ + #define AM33XX_MII_CLK_SEL_SHIFT			2
+ + #define AM33XX_MII_CLK_SEL_MASK				(1 << 2)
+ + 
+ + /*
+ +  * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
+ +  * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU,
+ +  * CM_SSC_MODFREQDIV_DPLL_PER
+ +  */
+ + #define AM33XX_MODFREQDIV_EXPONENT_SHIFT		8
+ + #define AM33XX_MODFREQDIV_EXPONENT_MASK			(0x10 << 8)
+ + 
+ + /*
+ +  * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
+ +  * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU,
+ +  * CM_SSC_MODFREQDIV_DPLL_PER
+ +  */
+ + #define AM33XX_MODFREQDIV_MANTISSA_SHIFT		0
+ + #define AM33XX_MODFREQDIV_MANTISSA_MASK			(0x06 << 0)
+ + 
+ + /*
+ +  * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
+ +  * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL,
+ +  * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL,
+ +  * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL,
+ +  * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL,
+ +  * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL,
+ +  * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL,
+ +  * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL,
+ +  * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL,
+ +  * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL,
+ +  * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL,
+ +  * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL,
+ +  * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL,
+ +  * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL,
+ +  * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
+ +  * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL,
+ +  * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL,
+ +  * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL,
+ +  * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL,
+ +  * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL,
+ +  * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL,
+ +  * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
+ +  * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL,
+ +  * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL,
+ +  * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL,
+ +  * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL,
+ +  * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL,
+ +  * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL,
+ +  * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL,
+ +  * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL,
+ +  * CM_GFX_GFX_CLKCTRL, CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL,
+ +  * CM_CEFUSE_CEFUSE_CLKCTRL
+ +  */
+ + #define AM33XX_MODULEMODE_SHIFT				0
+ + #define AM33XX_MODULEMODE_MASK				(0x3 << 0)
+ + 
+ + /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
+ + #define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT			30
+ + #define AM33XX_OPTCLK_DEBUG_CLKA_MASK			(1 << 30)
+ + 
+ + /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
+ + #define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT		19
+ + #define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK			(1 << 19)
+ + 
+ + /* Used by CM_WKUP_GPIO0_CLKCTRL */
+ + #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT		18
+ + #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK		(1 << 18)
+ + 
+ + /* Used by CM_PER_GPIO1_CLKCTRL */
+ + #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT		18
+ + #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK		(1 << 18)
+ + 
+ + /* Used by CM_PER_GPIO2_CLKCTRL */
+ + #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT		18
+ + #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK		(1 << 18)
+ + 
+ + /* Used by CM_PER_GPIO3_CLKCTRL */
+ + #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT		18
+ + #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK		(1 << 18)
+ + 
+ + /* Used by CM_PER_GPIO4_CLKCTRL */
+ + #define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT		18
+ + #define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK		(1 << 18)
+ + 
+ + /* Used by CM_PER_GPIO5_CLKCTRL */
+ + #define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT		18
+ + #define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK		(1 << 18)
+ + 
+ + /* Used by CM_PER_GPIO6_CLKCTRL */
+ + #define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT		18
+ + #define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK		(1 << 18)
+ + 
+ + /*
+ +  * Used by CM_MPU_MPU_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, CM_PER_PRUSS_CLKCTRL,
+ +  * CM_PER_IEEE5000_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MLB_CLKCTRL,
+ +  * CM_PER_MSTR_EXPS_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
+ +  * CM_PER_SPARE_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
+ +  * CM_PER_TPTC2_CLKCTRL, CM_PER_USB0_CLKCTRL, CM_WKUP_DEBUGSS_CLKCTRL,
+ +  * CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL
+ +  */
+ + #define AM33XX_STBYST_SHIFT				18
+ + #define AM33XX_STBYST_MASK				(1 << 18)
+ + 
+ + /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
+ + #define AM33XX_STM_PMD_CLKDIVSEL_SHIFT			27
+ + #define AM33XX_STM_PMD_CLKDIVSEL_MASK			(0x29 << 27)
+ + 
+ + /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
+ + #define AM33XX_STM_PMD_CLKSEL_SHIFT			22
+ + #define AM33XX_STM_PMD_CLKSEL_MASK			(0x23 << 22)
+ + 
+ + /*
+ +  * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
+ +  * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
+ +  */
+ + #define AM33XX_ST_DPLL_CLK_SHIFT			0
+ + #define AM33XX_ST_DPLL_CLK_MASK				(1 << 0)
+ + 
+ + /* Used by CM_CLKDCOLDO_DPLL_PER */
+ + #define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT			8
+ + #define AM33XX_ST_DPLL_CLKDCOLDO_MASK			(1 << 8)
+ + 
+ + /*
+ +  * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU,
+ +  * CM_DIV_M2_DPLL_PER
+ +  */
+ + #define AM33XX_ST_DPLL_CLKOUT_SHIFT			9
+ + #define AM33XX_ST_DPLL_CLKOUT_MASK			(1 << 9)
+ + 
+ + /* Used by CM_DIV_M4_DPLL_CORE */
+ + #define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT		9
+ + #define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK		(1 << 9)
+ + 
+ + /* Used by CM_DIV_M5_DPLL_CORE */
+ + #define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT		9
+ + #define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK		(1 << 9)
+ + 
+ + /* Used by CM_DIV_M6_DPLL_CORE */
+ + #define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT		9
+ + #define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK		(1 << 9)
+ + 
+ + /*
+ +  * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
+ +  * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
+ +  */
+ + #define AM33XX_ST_MN_BYPASS_SHIFT			8
+ + #define AM33XX_ST_MN_BYPASS_MASK			(1 << 8)
+ + 
+ + /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
+ + #define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT			24
+ + #define AM33XX_TRC_PMD_CLKDIVSEL_MASK			(0x26 << 24)
+ + 
+ + /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
+ + #define AM33XX_TRC_PMD_CLKSEL_SHIFT			20
+ + #define AM33XX_TRC_PMD_CLKSEL_MASK			(0x21 << 20)
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/cm-regbits-34xx.h linux-3.2.1/arch/arm/mach-ckb_3352/cm-regbits-34xx.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/cm-regbits-34xx.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/cm-regbits-34xx.h	2014-11-25 13:19:14.872994625 +0900
+ ***************
+ *** 0 ****
+ --- 1,812 ----
+ + #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
+ + #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
+ + 
+ + /*
+ +  * OMAP3430 Clock Management register bits
+ +  *
+ +  * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ +  * Copyright (C) 2007-2008 Nokia Corporation
+ +  *
+ +  * Written by Paul Walmsley
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + /* Bits shared between registers */
+ + 
+ + /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
+ + #define OMAP3430ES2_EN_MMC3_MASK			(1 << 30)
+ + #define OMAP3430ES2_EN_MMC3_SHIFT			30
+ + #define OMAP3430_EN_MSPRO_MASK				(1 << 23)
+ + #define OMAP3430_EN_MSPRO_SHIFT				23
+ + #define OMAP3430_EN_HDQ_MASK				(1 << 22)
+ + #define OMAP3430_EN_HDQ_SHIFT				22
+ + #define OMAP3430ES1_EN_FSHOSTUSB_MASK			(1 << 5)
+ + #define OMAP3430ES1_EN_FSHOSTUSB_SHIFT			5
+ + #define OMAP3430ES1_EN_D2D_MASK				(1 << 3)
+ + #define OMAP3430ES1_EN_D2D_SHIFT			3
+ + #define OMAP3430_EN_SSI_MASK				(1 << 0)
+ + #define OMAP3430_EN_SSI_SHIFT				0
+ + 
+ + /* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */
+ + #define OMAP3430ES2_EN_USBTLL_SHIFT			2
+ + #define OMAP3430ES2_EN_USBTLL_MASK			(1 << 2)
+ + 
+ + /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
+ + #define OMAP3430_EN_WDT2_MASK				(1 << 5)
+ + #define OMAP3430_EN_WDT2_SHIFT				5
+ + 
+ + /* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */
+ + #define OMAP3430_EN_CAM_MASK				(1 << 0)
+ + #define OMAP3430_EN_CAM_SHIFT				0
+ + 
+ + /* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */
+ + #define OMAP3430_EN_WDT3_MASK				(1 << 12)
+ + #define OMAP3430_EN_WDT3_SHIFT				12
+ + 
+ + /* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */
+ + #define OMAP3430_OVERRIDE_ENABLE_MASK			(1 << 19)
+ + 
+ + 
+ + /* Bits specific to each register */
+ + 
+ + /* CM_FCLKEN_IVA2 */
+ + #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK		(1 << 0)
+ + #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT		0
+ + 
+ + /* CM_CLKEN_PLL_IVA2 */
+ + #define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT		8
+ + #define OMAP3430_IVA2_DPLL_RAMPTIME_MASK		(0x3 << 8)
+ + #define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT		4
+ + #define OMAP3430_IVA2_DPLL_FREQSEL_MASK			(0xf << 4)
+ + #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT		3
+ + #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK		(1 << 3)
+ + #define OMAP3430_EN_IVA2_DPLL_SHIFT			0
+ + #define OMAP3430_EN_IVA2_DPLL_MASK			(0x7 << 0)
+ + 
+ + /* CM_IDLEST_IVA2 */
+ + #define OMAP3430_ST_IVA2_MASK				(1 << 0)
+ + 
+ + /* CM_IDLEST_PLL_IVA2 */
+ + #define OMAP3430_ST_IVA2_CLK_SHIFT			0
+ + #define OMAP3430_ST_IVA2_CLK_MASK			(1 << 0)
+ + 
+ + /* CM_AUTOIDLE_PLL_IVA2 */
+ + #define OMAP3430_AUTO_IVA2_DPLL_SHIFT			0
+ + #define OMAP3430_AUTO_IVA2_DPLL_MASK			(0x7 << 0)
+ + 
+ + /* CM_CLKSEL1_PLL_IVA2 */
+ + #define OMAP3430_IVA2_CLK_SRC_SHIFT			19
+ + #define OMAP3430_IVA2_CLK_SRC_MASK			(0x3 << 19)
+ + #define OMAP3430_IVA2_DPLL_MULT_SHIFT			8
+ + #define OMAP3430_IVA2_DPLL_MULT_MASK			(0x7ff << 8)
+ + #define OMAP3430_IVA2_DPLL_DIV_SHIFT			0
+ + #define OMAP3430_IVA2_DPLL_DIV_MASK			(0x7f << 0)
+ + 
+ + /* CM_CLKSEL2_PLL_IVA2 */
+ + #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT		0
+ + #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK		(0x1f << 0)
+ + 
+ + /* CM_CLKSTCTRL_IVA2 */
+ + #define OMAP3430_CLKTRCTRL_IVA2_SHIFT			0
+ + #define OMAP3430_CLKTRCTRL_IVA2_MASK			(0x3 << 0)
+ + 
+ + /* CM_CLKSTST_IVA2 */
+ + #define OMAP3430_CLKACTIVITY_IVA2_SHIFT			0
+ + #define OMAP3430_CLKACTIVITY_IVA2_MASK			(1 << 0)
+ + 
+ + /* CM_REVISION specific bits */
+ + 
+ + /* CM_SYSCONFIG specific bits */
+ + 
+ + /* CM_CLKEN_PLL_MPU */
+ + #define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT		8
+ + #define OMAP3430_MPU_DPLL_RAMPTIME_MASK			(0x3 << 8)
+ + #define OMAP3430_MPU_DPLL_FREQSEL_SHIFT			4
+ + #define OMAP3430_MPU_DPLL_FREQSEL_MASK			(0xf << 4)
+ + #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT		3
+ + #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK		(1 << 3)
+ + #define OMAP3430_EN_MPU_DPLL_SHIFT			0
+ + #define OMAP3430_EN_MPU_DPLL_MASK			(0x7 << 0)
+ + 
+ + /* CM_IDLEST_MPU */
+ + #define OMAP3430_ST_MPU_MASK				(1 << 0)
+ + 
+ + /* CM_IDLEST_PLL_MPU */
+ + #define OMAP3430_ST_MPU_CLK_SHIFT			0
+ + #define OMAP3430_ST_MPU_CLK_MASK			(1 << 0)
+ + 
+ + /* CM_AUTOIDLE_PLL_MPU */
+ + #define OMAP3430_AUTO_MPU_DPLL_SHIFT			0
+ + #define OMAP3430_AUTO_MPU_DPLL_MASK			(0x7 << 0)
+ + 
+ + /* CM_CLKSEL1_PLL_MPU */
+ + #define OMAP3430_MPU_CLK_SRC_SHIFT			19
+ + #define OMAP3430_MPU_CLK_SRC_MASK			(0x3 << 19)
+ + #define OMAP3430_MPU_DPLL_MULT_SHIFT			8
+ + #define OMAP3430_MPU_DPLL_MULT_MASK			(0x7ff << 8)
+ + #define OMAP3430_MPU_DPLL_DIV_SHIFT			0
+ + #define OMAP3430_MPU_DPLL_DIV_MASK			(0x7f << 0)
+ + 
+ + /* CM_CLKSEL2_PLL_MPU */
+ + #define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT		0
+ + #define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK		(0x1f << 0)
+ + 
+ + /* CM_CLKSTCTRL_MPU */
+ + #define OMAP3430_CLKTRCTRL_MPU_SHIFT			0
+ + #define OMAP3430_CLKTRCTRL_MPU_MASK			(0x3 << 0)
+ + 
+ + /* CM_CLKSTST_MPU */
+ + #define OMAP3430_CLKACTIVITY_MPU_SHIFT			0
+ + #define OMAP3430_CLKACTIVITY_MPU_MASK			(1 << 0)
+ + 
+ + /* CM_FCLKEN1_CORE specific bits */
+ + #define OMAP3430_EN_MODEM_MASK				(1 << 31)
+ + #define OMAP3430_EN_MODEM_SHIFT				31
+ + 
+ + /* CM_ICLKEN1_CORE specific bits */
+ + #define OMAP3430_EN_ICR_MASK				(1 << 29)
+ + #define OMAP3430_EN_ICR_SHIFT				29
+ + #define OMAP3430_EN_AES2_MASK				(1 << 28)
+ + #define OMAP3430_EN_AES2_SHIFT				28
+ + #define OMAP3430_EN_SHA12_MASK				(1 << 27)
+ + #define OMAP3430_EN_SHA12_SHIFT				27
+ + #define OMAP3430_EN_DES2_MASK				(1 << 26)
+ + #define OMAP3430_EN_DES2_SHIFT				26
+ + #define OMAP3430ES1_EN_FAC_MASK				(1 << 8)
+ + #define OMAP3430ES1_EN_FAC_SHIFT			8
+ + #define OMAP3430_EN_MAILBOXES_MASK			(1 << 7)
+ + #define OMAP3430_EN_MAILBOXES_SHIFT			7
+ + #define OMAP3430_EN_OMAPCTRL_MASK			(1 << 6)
+ + #define OMAP3430_EN_OMAPCTRL_SHIFT			6
+ + #define OMAP3430_EN_SAD2D_MASK				(1 << 3)
+ + #define OMAP3430_EN_SAD2D_SHIFT				3
+ + #define OMAP3430_EN_SDRC_MASK				(1 << 1)
+ + #define OMAP3430_EN_SDRC_SHIFT				1
+ + 
+ + /* AM35XX specific CM_ICLKEN1_CORE bits */
+ + #define AM35XX_EN_IPSS_MASK				(1 << 4)
+ + #define AM35XX_EN_IPSS_SHIFT				4
+ + #define AM35XX_EN_UART4_MASK				(1 << 23)
+ + #define AM35XX_EN_UART4_SHIFT				23
+ + 
+ + /* CM_ICLKEN2_CORE */
+ + #define OMAP3430_EN_PKA_MASK				(1 << 4)
+ + #define OMAP3430_EN_PKA_SHIFT				4
+ + #define OMAP3430_EN_AES1_MASK				(1 << 3)
+ + #define OMAP3430_EN_AES1_SHIFT				3
+ + #define OMAP3430_EN_RNG_MASK				(1 << 2)
+ + #define OMAP3430_EN_RNG_SHIFT				2
+ + #define OMAP3430_EN_SHA11_MASK				(1 << 1)
+ + #define OMAP3430_EN_SHA11_SHIFT				1
+ + #define OMAP3430_EN_DES1_MASK				(1 << 0)
+ + #define OMAP3430_EN_DES1_SHIFT				0
+ + 
+ + /* CM_ICLKEN3_CORE */
+ + #define OMAP3430_EN_MAD2D_SHIFT				3
+ + #define OMAP3430_EN_MAD2D_MASK				(1 << 3)
+ + 
+ + /* CM_FCLKEN3_CORE specific bits */
+ + #define OMAP3430ES2_EN_TS_SHIFT				1
+ + #define OMAP3430ES2_EN_TS_MASK				(1 << 1)
+ + #define OMAP3430ES2_EN_CPEFUSE_SHIFT			0
+ + #define OMAP3430ES2_EN_CPEFUSE_MASK			(1 << 0)
+ + 
+ + /* CM_IDLEST1_CORE specific bits */
+ + #define OMAP3430ES2_ST_MMC3_SHIFT			30
+ + #define OMAP3430ES2_ST_MMC3_MASK			(1 << 30)
+ + #define OMAP3430_ST_ICR_SHIFT				29
+ + #define OMAP3430_ST_ICR_MASK				(1 << 29)
+ + #define OMAP3430_ST_AES2_SHIFT				28
+ + #define OMAP3430_ST_AES2_MASK				(1 << 28)
+ + #define OMAP3430_ST_SHA12_SHIFT				27
+ + #define OMAP3430_ST_SHA12_MASK				(1 << 27)
+ + #define OMAP3430_ST_DES2_SHIFT				26
+ + #define OMAP3430_ST_DES2_MASK				(1 << 26)
+ + #define OMAP3430_ST_MSPRO_SHIFT				23
+ + #define OMAP3430_ST_MSPRO_MASK				(1 << 23)
+ + #define OMAP3430_ST_HDQ_SHIFT				22
+ + #define OMAP3430_ST_HDQ_MASK				(1 << 22)
+ + #define OMAP3430ES1_ST_FAC_SHIFT			8
+ + #define OMAP3430ES1_ST_FAC_MASK				(1 << 8)
+ + #define OMAP3430ES2_ST_SSI_IDLE_SHIFT			8
+ + #define OMAP3430ES2_ST_SSI_IDLE_MASK			(1 << 8)
+ + #define OMAP3430_ST_MAILBOXES_SHIFT			7
+ + #define OMAP3430_ST_MAILBOXES_MASK			(1 << 7)
+ + #define OMAP3430_ST_OMAPCTRL_SHIFT			6
+ + #define OMAP3430_ST_OMAPCTRL_MASK			(1 << 6)
+ + #define OMAP3430_ST_SDMA_SHIFT				2
+ + #define OMAP3430_ST_SDMA_MASK				(1 << 2)
+ + #define OMAP3430_ST_SDRC_SHIFT				1
+ + #define OMAP3430_ST_SDRC_MASK				(1 << 1)
+ + #define OMAP3430_ST_SSI_STDBY_SHIFT			0
+ + #define OMAP3430_ST_SSI_STDBY_MASK			(1 << 0)
+ + 
+ + /* AM35xx specific CM_IDLEST1_CORE bits */
+ + #define AM35XX_ST_IPSS_SHIFT				5
+ + #define AM35XX_ST_IPSS_MASK 				(1 << 5)
+ + 
+ + /* CM_IDLEST2_CORE */
+ + #define OMAP3430_ST_PKA_SHIFT				4
+ + #define OMAP3430_ST_PKA_MASK				(1 << 4)
+ + #define OMAP3430_ST_AES1_SHIFT				3
+ + #define OMAP3430_ST_AES1_MASK				(1 << 3)
+ + #define OMAP3430_ST_RNG_SHIFT				2
+ + #define OMAP3430_ST_RNG_MASK				(1 << 2)
+ + #define OMAP3430_ST_SHA11_SHIFT				1
+ + #define OMAP3430_ST_SHA11_MASK				(1 << 1)
+ + #define OMAP3430_ST_DES1_SHIFT				0
+ + #define OMAP3430_ST_DES1_MASK				(1 << 0)
+ + 
+ + /* CM_IDLEST3_CORE */
+ + #define OMAP3430ES2_ST_USBTLL_SHIFT			2
+ + #define OMAP3430ES2_ST_USBTLL_MASK			(1 << 2)
+ + #define OMAP3430ES2_ST_CPEFUSE_SHIFT			0
+ + #define OMAP3430ES2_ST_CPEFUSE_MASK			(1 << 0)
+ + 
+ + /* CM_AUTOIDLE1_CORE */
+ + #define OMAP3430_AUTO_MODEM_MASK			(1 << 31)
+ + #define OMAP3430_AUTO_MODEM_SHIFT			31
+ + #define OMAP3430ES2_AUTO_MMC3_MASK			(1 << 30)
+ + #define OMAP3430ES2_AUTO_MMC3_SHIFT			30
+ + #define OMAP3430ES2_AUTO_ICR_MASK			(1 << 29)
+ + #define OMAP3430ES2_AUTO_ICR_SHIFT			29
+ + #define OMAP3430_AUTO_AES2_MASK				(1 << 28)
+ + #define OMAP3430_AUTO_AES2_SHIFT			28
+ + #define OMAP3430_AUTO_SHA12_MASK			(1 << 27)
+ + #define OMAP3430_AUTO_SHA12_SHIFT			27
+ + #define OMAP3430_AUTO_DES2_MASK				(1 << 26)
+ + #define OMAP3430_AUTO_DES2_SHIFT			26
+ + #define OMAP3430_AUTO_MMC2_MASK				(1 << 25)
+ + #define OMAP3430_AUTO_MMC2_SHIFT			25
+ + #define OMAP3430_AUTO_MMC1_MASK				(1 << 24)
+ + #define OMAP3430_AUTO_MMC1_SHIFT			24
+ + #define OMAP3430_AUTO_MSPRO_MASK			(1 << 23)
+ + #define OMAP3430_AUTO_MSPRO_SHIFT			23
+ + #define OMAP3430_AUTO_HDQ_MASK				(1 << 22)
+ + #define OMAP3430_AUTO_HDQ_SHIFT				22
+ + #define OMAP3430_AUTO_MCSPI4_MASK			(1 << 21)
+ + #define OMAP3430_AUTO_MCSPI4_SHIFT			21
+ + #define OMAP3430_AUTO_MCSPI3_MASK			(1 << 20)
+ + #define OMAP3430_AUTO_MCSPI3_SHIFT			20
+ + #define OMAP3430_AUTO_MCSPI2_MASK			(1 << 19)
+ + #define OMAP3430_AUTO_MCSPI2_SHIFT			19
+ + #define OMAP3430_AUTO_MCSPI1_MASK			(1 << 18)
+ + #define OMAP3430_AUTO_MCSPI1_SHIFT			18
+ + #define OMAP3430_AUTO_I2C3_MASK				(1 << 17)
+ + #define OMAP3430_AUTO_I2C3_SHIFT			17
+ + #define OMAP3430_AUTO_I2C2_MASK				(1 << 16)
+ + #define OMAP3430_AUTO_I2C2_SHIFT			16
+ + #define OMAP3430_AUTO_I2C1_MASK				(1 << 15)
+ + #define OMAP3430_AUTO_I2C1_SHIFT			15
+ + #define OMAP3430_AUTO_UART2_MASK			(1 << 14)
+ + #define OMAP3430_AUTO_UART2_SHIFT			14
+ + #define OMAP3430_AUTO_UART1_MASK			(1 << 13)
+ + #define OMAP3430_AUTO_UART1_SHIFT			13
+ + #define OMAP3430_AUTO_GPT11_MASK			(1 << 12)
+ + #define OMAP3430_AUTO_GPT11_SHIFT			12
+ + #define OMAP3430_AUTO_GPT10_MASK			(1 << 11)
+ + #define OMAP3430_AUTO_GPT10_SHIFT			11
+ + #define OMAP3430_AUTO_MCBSP5_MASK			(1 << 10)
+ + #define OMAP3430_AUTO_MCBSP5_SHIFT			10
+ + #define OMAP3430_AUTO_MCBSP1_MASK			(1 << 9)
+ + #define OMAP3430_AUTO_MCBSP1_SHIFT			9
+ + #define OMAP3430ES1_AUTO_FAC_MASK			(1 << 8)
+ + #define OMAP3430ES1_AUTO_FAC_SHIFT			8
+ + #define OMAP3430_AUTO_MAILBOXES_MASK			(1 << 7)
+ + #define OMAP3430_AUTO_MAILBOXES_SHIFT			7
+ + #define OMAP3430_AUTO_OMAPCTRL_MASK			(1 << 6)
+ + #define OMAP3430_AUTO_OMAPCTRL_SHIFT			6
+ + #define OMAP3430ES1_AUTO_FSHOSTUSB_MASK			(1 << 5)
+ + #define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT		5
+ + #define OMAP3430_AUTO_HSOTGUSB_MASK			(1 << 4)
+ + #define OMAP3430_AUTO_HSOTGUSB_SHIFT			4
+ + #define OMAP3430ES1_AUTO_D2D_MASK			(1 << 3)
+ + #define OMAP3430ES1_AUTO_D2D_SHIFT			3
+ + #define OMAP3430_AUTO_SAD2D_MASK			(1 << 3)
+ + #define OMAP3430_AUTO_SAD2D_SHIFT			3
+ + #define OMAP3430_AUTO_SSI_MASK				(1 << 0)
+ + #define OMAP3430_AUTO_SSI_SHIFT				0
+ + 
+ + /* CM_AUTOIDLE2_CORE */
+ + #define OMAP3430_AUTO_PKA_MASK				(1 << 4)
+ + #define OMAP3430_AUTO_PKA_SHIFT				4
+ + #define OMAP3430_AUTO_AES1_MASK				(1 << 3)
+ + #define OMAP3430_AUTO_AES1_SHIFT			3
+ + #define OMAP3430_AUTO_RNG_MASK				(1 << 2)
+ + #define OMAP3430_AUTO_RNG_SHIFT				2
+ + #define OMAP3430_AUTO_SHA11_MASK			(1 << 1)
+ + #define OMAP3430_AUTO_SHA11_SHIFT			1
+ + #define OMAP3430_AUTO_DES1_MASK				(1 << 0)
+ + #define OMAP3430_AUTO_DES1_SHIFT			0
+ + 
+ + /* CM_AUTOIDLE3_CORE */
+ + #define	OMAP3430ES2_AUTO_USBHOST			(1 << 0)
+ + #define	OMAP3430ES2_AUTO_USBHOST_SHIFT			0
+ + #define	OMAP3430ES2_AUTO_USBTLL				(1 << 2)
+ + #define OMAP3430ES2_AUTO_USBTLL_SHIFT			2
+ + #define OMAP3430ES2_AUTO_USBTLL_MASK			(1 << 2)
+ + #define OMAP3430_AUTO_MAD2D_SHIFT			3
+ + #define OMAP3430_AUTO_MAD2D_MASK			(1 << 3)
+ + 
+ + /* CM_CLKSEL_CORE */
+ + #define OMAP3430_CLKSEL_SSI_SHIFT			8
+ + #define OMAP3430_CLKSEL_SSI_MASK			(0xf << 8)
+ + #define OMAP3430_CLKSEL_GPT11_MASK			(1 << 7)
+ + #define OMAP3430_CLKSEL_GPT11_SHIFT			7
+ + #define OMAP3430_CLKSEL_GPT10_MASK			(1 << 6)
+ + #define OMAP3430_CLKSEL_GPT10_SHIFT			6
+ + #define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT		4
+ + #define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK		(0x3 << 4)
+ + #define OMAP3430_CLKSEL_L4_SHIFT			2
+ + #define OMAP3430_CLKSEL_L4_MASK				(0x3 << 2)
+ + #define OMAP3430_CLKSEL_L3_SHIFT			0
+ + #define OMAP3430_CLKSEL_L3_MASK				(0x3 << 0)
+ + #define OMAP3630_CLKSEL_96M_SHIFT			12
+ + #define OMAP3630_CLKSEL_96M_MASK			(0x3 << 12)
+ + 
+ + /* CM_CLKSTCTRL_CORE */
+ + #define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT			4
+ + #define OMAP3430ES1_CLKTRCTRL_D2D_MASK			(0x3 << 4)
+ + #define OMAP3430_CLKTRCTRL_L4_SHIFT			2
+ + #define OMAP3430_CLKTRCTRL_L4_MASK			(0x3 << 2)
+ + #define OMAP3430_CLKTRCTRL_L3_SHIFT			0
+ + #define OMAP3430_CLKTRCTRL_L3_MASK			(0x3 << 0)
+ + 
+ + /* CM_CLKSTST_CORE */
+ + #define OMAP3430ES1_CLKACTIVITY_D2D_SHIFT		2
+ + #define OMAP3430ES1_CLKACTIVITY_D2D_MASK		(1 << 2)
+ + #define OMAP3430_CLKACTIVITY_L4_SHIFT			1
+ + #define OMAP3430_CLKACTIVITY_L4_MASK			(1 << 1)
+ + #define OMAP3430_CLKACTIVITY_L3_SHIFT			0
+ + #define OMAP3430_CLKACTIVITY_L3_MASK			(1 << 0)
+ + 
+ + /* CM_FCLKEN_GFX */
+ + #define OMAP3430ES1_EN_3D_MASK				(1 << 2)
+ + #define OMAP3430ES1_EN_3D_SHIFT				2
+ + #define OMAP3430ES1_EN_2D_MASK				(1 << 1)
+ + #define OMAP3430ES1_EN_2D_SHIFT				1
+ + 
+ + /* CM_ICLKEN_GFX specific bits */
+ + 
+ + /* CM_IDLEST_GFX specific bits */
+ + 
+ + /* CM_CLKSEL_GFX specific bits */
+ + 
+ + /* CM_SLEEPDEP_GFX specific bits */
+ + 
+ + /* CM_CLKSTCTRL_GFX */
+ + #define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT			0
+ + #define OMAP3430ES1_CLKTRCTRL_GFX_MASK			(0x3 << 0)
+ + 
+ + /* CM_CLKSTST_GFX */
+ + #define OMAP3430ES1_CLKACTIVITY_GFX_SHIFT		0
+ + #define OMAP3430ES1_CLKACTIVITY_GFX_MASK		(1 << 0)
+ + 
+ + /* CM_FCLKEN_SGX */
+ + #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT		1
+ + #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK		(1 << 1)
+ + 
+ + /* CM_IDLEST_SGX */
+ + #define OMAP3430ES2_ST_SGX_SHIFT			1
+ + #define OMAP3430ES2_ST_SGX_MASK				(1 << 1)
+ + 
+ + /* CM_ICLKEN_SGX */
+ + #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT		0
+ + #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK		(1 << 0)
+ + 
+ + /* CM_CLKSEL_SGX */
+ + #define OMAP3430ES2_CLKSEL_SGX_SHIFT			0
+ + #define OMAP3430ES2_CLKSEL_SGX_MASK			(0x7 << 0)
+ + 
+ + /* CM_CLKSTCTRL_SGX */
+ + #define OMAP3430ES2_CLKTRCTRL_SGX_SHIFT			0
+ + #define OMAP3430ES2_CLKTRCTRL_SGX_MASK			(0x3 << 0)
+ + 
+ + /* CM_CLKSTST_SGX */
+ + #define OMAP3430ES2_CLKACTIVITY_SGX_SHIFT		0
+ + #define OMAP3430ES2_CLKACTIVITY_SGX_MASK		(1 << 0)
+ + 
+ + /* CM_FCLKEN_WKUP specific bits */
+ + #define OMAP3430ES2_EN_USIMOCP_SHIFT			9
+ + #define OMAP3430ES2_EN_USIMOCP_MASK			(1 << 9)
+ + 
+ + /* CM_ICLKEN_WKUP specific bits */
+ + #define OMAP3430_EN_WDT1_MASK				(1 << 4)
+ + #define OMAP3430_EN_WDT1_SHIFT				4
+ + #define OMAP3430_EN_32KSYNC_MASK			(1 << 2)
+ + #define OMAP3430_EN_32KSYNC_SHIFT			2
+ + 
+ + /* CM_IDLEST_WKUP specific bits */
+ + #define OMAP3430ES2_ST_USIMOCP_SHIFT			9
+ + #define OMAP3430ES2_ST_USIMOCP_MASK			(1 << 9)
+ + #define OMAP3430_ST_WDT2_SHIFT				5
+ + #define OMAP3430_ST_WDT2_MASK				(1 << 5)
+ + #define OMAP3430_ST_WDT1_SHIFT				4
+ + #define OMAP3430_ST_WDT1_MASK				(1 << 4)
+ + #define OMAP3430_ST_32KSYNC_SHIFT			2
+ + #define OMAP3430_ST_32KSYNC_MASK			(1 << 2)
+ + 
+ + /* CM_AUTOIDLE_WKUP */
+ + #define OMAP3430ES2_AUTO_USIMOCP_MASK			(1 << 9)
+ + #define OMAP3430ES2_AUTO_USIMOCP_SHIFT			9
+ + #define OMAP3430_AUTO_WDT2_MASK				(1 << 5)
+ + #define OMAP3430_AUTO_WDT2_SHIFT			5
+ + #define OMAP3430_AUTO_WDT1_MASK				(1 << 4)
+ + #define OMAP3430_AUTO_WDT1_SHIFT			4
+ + #define OMAP3430_AUTO_GPIO1_MASK			(1 << 3)
+ + #define OMAP3430_AUTO_GPIO1_SHIFT			3
+ + #define OMAP3430_AUTO_32KSYNC_MASK			(1 << 2)
+ + #define OMAP3430_AUTO_32KSYNC_SHIFT			2
+ + #define OMAP3430_AUTO_GPT12_MASK			(1 << 1)
+ + #define OMAP3430_AUTO_GPT12_SHIFT			1
+ + #define OMAP3430_AUTO_GPT1_MASK				(1 << 0)
+ + #define OMAP3430_AUTO_GPT1_SHIFT			0
+ + 
+ + /* CM_CLKSEL_WKUP */
+ + #define OMAP3430ES2_CLKSEL_USIMOCP_MASK			(0xf << 3)
+ + #define OMAP3430_CLKSEL_RM_SHIFT			1
+ + #define OMAP3430_CLKSEL_RM_MASK				(0x3 << 1)
+ + #define OMAP3430_CLKSEL_GPT1_SHIFT			0
+ + #define OMAP3430_CLKSEL_GPT1_MASK			(1 << 0)
+ + 
+ + /* CM_CLKEN_PLL */
+ + #define OMAP3430_PWRDN_EMU_PERIPH_SHIFT			31
+ + #define OMAP3430_PWRDN_CAM_SHIFT			30
+ + #define OMAP3430_PWRDN_DSS1_SHIFT			29
+ + #define OMAP3430_PWRDN_TV_SHIFT				28
+ + #define OMAP3430_PWRDN_96M_SHIFT			27
+ + #define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT		24
+ + #define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK		(0x3 << 24)
+ + #define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT		20
+ + #define OMAP3430_PERIPH_DPLL_FREQSEL_MASK		(0xf << 20)
+ + #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT	19
+ + #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK		(1 << 19)
+ + #define OMAP3430_EN_PERIPH_DPLL_SHIFT			16
+ + #define OMAP3430_EN_PERIPH_DPLL_MASK			(0x7 << 16)
+ + #define OMAP3430_PWRDN_EMU_CORE_SHIFT			12
+ + #define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT		8
+ + #define OMAP3430_CORE_DPLL_RAMPTIME_MASK		(0x3 << 8)
+ + #define OMAP3430_CORE_DPLL_FREQSEL_SHIFT		4
+ + #define OMAP3430_CORE_DPLL_FREQSEL_MASK			(0xf << 4)
+ + #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT		3
+ + #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK		(1 << 3)
+ + #define OMAP3430_EN_CORE_DPLL_SHIFT			0
+ + #define OMAP3430_EN_CORE_DPLL_MASK			(0x7 << 0)
+ + 
+ + /* CM_CLKEN2_PLL */
+ + #define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT	10
+ + #define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK		(0x3 << 8)
+ + #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT		4
+ + #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK		(0xf << 4)
+ + #define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT	3
+ + #define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT		0
+ + #define OMAP3430ES2_EN_PERIPH2_DPLL_MASK		(0x7 << 0)
+ + 
+ + /* CM_IDLEST_CKGEN */
+ + #define OMAP3430_ST_54M_CLK_MASK			(1 << 5)
+ + #define OMAP3430_ST_12M_CLK_MASK			(1 << 4)
+ + #define OMAP3430_ST_48M_CLK_MASK			(1 << 3)
+ + #define OMAP3430_ST_96M_CLK_MASK			(1 << 2)
+ + #define OMAP3430_ST_PERIPH_CLK_SHIFT			1
+ + #define OMAP3430_ST_PERIPH_CLK_MASK			(1 << 1)
+ + #define OMAP3430_ST_CORE_CLK_SHIFT			0
+ + #define OMAP3430_ST_CORE_CLK_MASK			(1 << 0)
+ + 
+ + /* CM_IDLEST2_CKGEN */
+ + #define OMAP3430ES2_ST_USIM_CLK_SHIFT			2
+ + #define OMAP3430ES2_ST_USIM_CLK_MASK			(1 << 2)
+ + #define OMAP3430ES2_ST_120M_CLK_SHIFT			1
+ + #define OMAP3430ES2_ST_120M_CLK_MASK			(1 << 1)
+ + #define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT		0
+ + #define OMAP3430ES2_ST_PERIPH2_CLK_MASK			(1 << 0)
+ + 
+ + /* CM_AUTOIDLE_PLL */
+ + #define OMAP3430_AUTO_PERIPH_DPLL_SHIFT			3
+ + #define OMAP3430_AUTO_PERIPH_DPLL_MASK			(0x7 << 3)
+ + #define OMAP3430_AUTO_CORE_DPLL_SHIFT			0
+ + #define OMAP3430_AUTO_CORE_DPLL_MASK			(0x7 << 0)
+ + 
+ + /* CM_AUTOIDLE2_PLL */
+ + #define OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT		0
+ + #define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK		(0x7 << 0)
+ + 
+ + /* CM_CLKSEL1_PLL */
+ + /* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */
+ + #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT		27
+ + #define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK		(0x1f << 27)
+ + #define OMAP3430_CORE_DPLL_MULT_SHIFT			16
+ + #define OMAP3430_CORE_DPLL_MULT_MASK			(0x7ff << 16)
+ + #define OMAP3430_CORE_DPLL_DIV_SHIFT			8
+ + #define OMAP3430_CORE_DPLL_DIV_MASK			(0x7f << 8)
+ + #define OMAP3430_SOURCE_96M_SHIFT			6
+ + #define OMAP3430_SOURCE_96M_MASK			(1 << 6)
+ + #define OMAP3430_SOURCE_54M_SHIFT			5
+ + #define OMAP3430_SOURCE_54M_MASK			(1 << 5)
+ + #define OMAP3430_SOURCE_48M_SHIFT			3
+ + #define OMAP3430_SOURCE_48M_MASK			(1 << 3)
+ + 
+ + /* CM_CLKSEL2_PLL */
+ + #define OMAP3430_PERIPH_DPLL_MULT_SHIFT			8
+ + #define OMAP3430_PERIPH_DPLL_MULT_MASK			(0x7ff << 8)
+ + #define OMAP3630_PERIPH_DPLL_MULT_MASK			(0xfff << 8)
+ + #define OMAP3430_PERIPH_DPLL_DIV_SHIFT			0
+ + #define OMAP3430_PERIPH_DPLL_DIV_MASK			(0x7f << 0)
+ + #define OMAP3630_PERIPH_DPLL_DCO_SEL_SHIFT		21
+ + #define OMAP3630_PERIPH_DPLL_DCO_SEL_MASK		(0x7 << 21)
+ + #define OMAP3630_PERIPH_DPLL_SD_DIV_SHIFT		24
+ + #define OMAP3630_PERIPH_DPLL_SD_DIV_MASK		(0xff << 24)
+ + 
+ + /* CM_CLKSEL3_PLL */
+ + #define OMAP3430_DIV_96M_SHIFT				0
+ + #define OMAP3430_DIV_96M_MASK				(0x1f << 0)
+ + #define OMAP3630_DIV_96M_MASK				(0x3f << 0)
+ + 
+ + /* CM_CLKSEL4_PLL */
+ + #define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT		8
+ + #define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK		(0x7ff << 8)
+ + #define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT		0
+ + #define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK		(0x7f << 0)
+ + 
+ + /* CM_CLKSEL5_PLL */
+ + #define OMAP3430ES2_DIV_120M_SHIFT			0
+ + #define OMAP3430ES2_DIV_120M_MASK			(0x1f << 0)
+ + 
+ + /* CM_CLKOUT_CTRL */
+ + #define OMAP3430_CLKOUT2_EN_SHIFT			7
+ + #define OMAP3430_CLKOUT2_EN_MASK			(1 << 7)
+ + #define OMAP3430_CLKOUT2_DIV_SHIFT			3
+ + #define OMAP3430_CLKOUT2_DIV_MASK			(0x7 << 3)
+ + #define OMAP3430_CLKOUT2SOURCE_SHIFT			0
+ + #define OMAP3430_CLKOUT2SOURCE_MASK			(0x3 << 0)
+ + 
+ + /* CM_FCLKEN_DSS */
+ + #define OMAP3430_EN_TV_MASK				(1 << 2)
+ + #define OMAP3430_EN_TV_SHIFT				2
+ + #define OMAP3430_EN_DSS2_MASK				(1 << 1)
+ + #define OMAP3430_EN_DSS2_SHIFT				1
+ + #define OMAP3430_EN_DSS1_MASK				(1 << 0)
+ + #define OMAP3430_EN_DSS1_SHIFT				0
+ + 
+ + /* CM_ICLKEN_DSS */
+ + #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_MASK		(1 << 0)
+ + #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT		0
+ + 
+ + /* CM_IDLEST_DSS */
+ + #define OMAP3430ES2_ST_DSS_IDLE_SHIFT			1
+ + #define OMAP3430ES2_ST_DSS_IDLE_MASK			(1 << 1)
+ + #define OMAP3430ES2_ST_DSS_STDBY_SHIFT			0
+ + #define OMAP3430ES2_ST_DSS_STDBY_MASK			(1 << 0)
+ + #define OMAP3430ES1_ST_DSS_SHIFT			0
+ + #define OMAP3430ES1_ST_DSS_MASK				(1 << 0)
+ + 
+ + /* CM_AUTOIDLE_DSS */
+ + #define OMAP3430_AUTO_DSS_MASK				(1 << 0)
+ + #define OMAP3430_AUTO_DSS_SHIFT				0
+ + 
+ + /* CM_CLKSEL_DSS */
+ + #define OMAP3430_CLKSEL_TV_SHIFT			8
+ + #define OMAP3430_CLKSEL_TV_MASK				(0x1f << 8)
+ + #define OMAP3630_CLKSEL_TV_MASK				(0x3f << 8)
+ + #define OMAP3430_CLKSEL_DSS1_SHIFT			0
+ + #define OMAP3430_CLKSEL_DSS1_MASK			(0x1f << 0)
+ + #define OMAP3630_CLKSEL_DSS1_MASK			(0x3f << 0)
+ + 
+ + /* CM_SLEEPDEP_DSS specific bits */
+ + 
+ + /* CM_CLKSTCTRL_DSS */
+ + #define OMAP3430_CLKTRCTRL_DSS_SHIFT			0
+ + #define OMAP3430_CLKTRCTRL_DSS_MASK			(0x3 << 0)
+ + 
+ + /* CM_CLKSTST_DSS */
+ + #define OMAP3430_CLKACTIVITY_DSS_SHIFT			0
+ + #define OMAP3430_CLKACTIVITY_DSS_MASK			(1 << 0)
+ + 
+ + /* CM_FCLKEN_CAM specific bits */
+ + #define OMAP3430_EN_CSI2_MASK				(1 << 1)
+ + #define OMAP3430_EN_CSI2_SHIFT				1
+ + 
+ + /* CM_ICLKEN_CAM specific bits */
+ + 
+ + /* CM_IDLEST_CAM */
+ + #define OMAP3430_ST_CAM_MASK				(1 << 0)
+ + 
+ + /* CM_AUTOIDLE_CAM */
+ + #define OMAP3430_AUTO_CAM_MASK				(1 << 0)
+ + #define OMAP3430_AUTO_CAM_SHIFT				0
+ + 
+ + /* CM_CLKSEL_CAM */
+ + #define OMAP3430_CLKSEL_CAM_SHIFT			0
+ + #define OMAP3430_CLKSEL_CAM_MASK			(0x1f << 0)
+ + #define OMAP3630_CLKSEL_CAM_MASK			(0x3f << 0)
+ + 
+ + /* CM_SLEEPDEP_CAM specific bits */
+ + 
+ + /* CM_CLKSTCTRL_CAM */
+ + #define OMAP3430_CLKTRCTRL_CAM_SHIFT			0
+ + #define OMAP3430_CLKTRCTRL_CAM_MASK			(0x3 << 0)
+ + 
+ + /* CM_CLKSTST_CAM */
+ + #define OMAP3430_CLKACTIVITY_CAM_SHIFT			0
+ + #define OMAP3430_CLKACTIVITY_CAM_MASK			(1 << 0)
+ + 
+ + /* CM_FCLKEN_PER specific bits */
+ + 
+ + /* CM_ICLKEN_PER specific bits */
+ + 
+ + /* CM_IDLEST_PER */
+ + #define OMAP3430_ST_WDT3_SHIFT				12
+ + #define OMAP3430_ST_WDT3_MASK				(1 << 12)
+ + #define OMAP3430_ST_MCBSP4_SHIFT			2
+ + #define OMAP3430_ST_MCBSP4_MASK				(1 << 2)
+ + #define OMAP3430_ST_MCBSP3_SHIFT			1
+ + #define OMAP3430_ST_MCBSP3_MASK				(1 << 1)
+ + #define OMAP3430_ST_MCBSP2_SHIFT			0
+ + #define OMAP3430_ST_MCBSP2_MASK				(1 << 0)
+ + 
+ + /* CM_AUTOIDLE_PER */
+ + #define OMAP3630_AUTO_UART4_MASK			(1 << 18)
+ + #define OMAP3630_AUTO_UART4_SHIFT			18
+ + #define OMAP3430_AUTO_GPIO6_MASK			(1 << 17)
+ + #define OMAP3430_AUTO_GPIO6_SHIFT			17
+ + #define OMAP3430_AUTO_GPIO5_MASK			(1 << 16)
+ + #define OMAP3430_AUTO_GPIO5_SHIFT			16
+ + #define OMAP3430_AUTO_GPIO4_MASK			(1 << 15)
+ + #define OMAP3430_AUTO_GPIO4_SHIFT			15
+ + #define OMAP3430_AUTO_GPIO3_MASK			(1 << 14)
+ + #define OMAP3430_AUTO_GPIO3_SHIFT			14
+ + #define OMAP3430_AUTO_GPIO2_MASK			(1 << 13)
+ + #define OMAP3430_AUTO_GPIO2_SHIFT			13
+ + #define OMAP3430_AUTO_WDT3_MASK				(1 << 12)
+ + #define OMAP3430_AUTO_WDT3_SHIFT			12
+ + #define OMAP3430_AUTO_UART3_MASK			(1 << 11)
+ + #define OMAP3430_AUTO_UART3_SHIFT			11
+ + #define OMAP3430_AUTO_GPT9_MASK				(1 << 10)
+ + #define OMAP3430_AUTO_GPT9_SHIFT			10
+ + #define OMAP3430_AUTO_GPT8_MASK				(1 << 9)
+ + #define OMAP3430_AUTO_GPT8_SHIFT			9
+ + #define OMAP3430_AUTO_GPT7_MASK				(1 << 8)
+ + #define OMAP3430_AUTO_GPT7_SHIFT			8
+ + #define OMAP3430_AUTO_GPT6_MASK				(1 << 7)
+ + #define OMAP3430_AUTO_GPT6_SHIFT			7
+ + #define OMAP3430_AUTO_GPT5_MASK				(1 << 6)
+ + #define OMAP3430_AUTO_GPT5_SHIFT			6
+ + #define OMAP3430_AUTO_GPT4_MASK				(1 << 5)
+ + #define OMAP3430_AUTO_GPT4_SHIFT			5
+ + #define OMAP3430_AUTO_GPT3_MASK				(1 << 4)
+ + #define OMAP3430_AUTO_GPT3_SHIFT			4
+ + #define OMAP3430_AUTO_GPT2_MASK				(1 << 3)
+ + #define OMAP3430_AUTO_GPT2_SHIFT			3
+ + #define OMAP3430_AUTO_MCBSP4_MASK			(1 << 2)
+ + #define OMAP3430_AUTO_MCBSP4_SHIFT			2
+ + #define OMAP3430_AUTO_MCBSP3_MASK			(1 << 1)
+ + #define OMAP3430_AUTO_MCBSP3_SHIFT			1
+ + #define OMAP3430_AUTO_MCBSP2_MASK			(1 << 0)
+ + #define OMAP3430_AUTO_MCBSP2_SHIFT			0
+ + 
+ + /* CM_CLKSEL_PER */
+ + #define OMAP3430_CLKSEL_GPT9_MASK			(1 << 7)
+ + #define OMAP3430_CLKSEL_GPT9_SHIFT			7
+ + #define OMAP3430_CLKSEL_GPT8_MASK			(1 << 6)
+ + #define OMAP3430_CLKSEL_GPT8_SHIFT			6
+ + #define OMAP3430_CLKSEL_GPT7_MASK			(1 << 5)
+ + #define OMAP3430_CLKSEL_GPT7_SHIFT			5
+ + #define OMAP3430_CLKSEL_GPT6_MASK			(1 << 4)
+ + #define OMAP3430_CLKSEL_GPT6_SHIFT			4
+ + #define OMAP3430_CLKSEL_GPT5_MASK			(1 << 3)
+ + #define OMAP3430_CLKSEL_GPT5_SHIFT			3
+ + #define OMAP3430_CLKSEL_GPT4_MASK			(1 << 2)
+ + #define OMAP3430_CLKSEL_GPT4_SHIFT			2
+ + #define OMAP3430_CLKSEL_GPT3_MASK			(1 << 1)
+ + #define OMAP3430_CLKSEL_GPT3_SHIFT			1
+ + #define OMAP3430_CLKSEL_GPT2_MASK			(1 << 0)
+ + #define OMAP3430_CLKSEL_GPT2_SHIFT			0
+ + 
+ + /* CM_SLEEPDEP_PER specific bits */
+ + #define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2_MASK		(1 << 2)
+ + 
+ + /* CM_CLKSTCTRL_PER */
+ + #define OMAP3430_CLKTRCTRL_PER_SHIFT			0
+ + #define OMAP3430_CLKTRCTRL_PER_MASK			(0x3 << 0)
+ + 
+ + /* CM_CLKSTST_PER */
+ + #define OMAP3430_CLKACTIVITY_PER_SHIFT			0
+ + #define OMAP3430_CLKACTIVITY_PER_MASK			(1 << 0)
+ + 
+ + /* CM_CLKSEL1_EMU */
+ + #define OMAP3430_DIV_DPLL4_SHIFT			24
+ + #define OMAP3430_DIV_DPLL4_MASK				(0x1f << 24)
+ + #define OMAP3630_DIV_DPLL4_MASK				(0x3f << 24)
+ + #define OMAP3430_DIV_DPLL3_SHIFT			16
+ + #define OMAP3430_DIV_DPLL3_MASK				(0x1f << 16)
+ + #define OMAP3430_CLKSEL_TRACECLK_SHIFT			11
+ + #define OMAP3430_CLKSEL_TRACECLK_MASK			(0x7 << 11)
+ + #define OMAP3430_CLKSEL_PCLK_SHIFT			8
+ + #define OMAP3430_CLKSEL_PCLK_MASK			(0x7 << 8)
+ + #define OMAP3430_CLKSEL_PCLKX2_SHIFT			6
+ + #define OMAP3430_CLKSEL_PCLKX2_MASK			(0x3 << 6)
+ + #define OMAP3430_CLKSEL_ATCLK_SHIFT			4
+ + #define OMAP3430_CLKSEL_ATCLK_MASK			(0x3 << 4)
+ + #define OMAP3430_TRACE_MUX_CTRL_SHIFT			2
+ + #define OMAP3430_TRACE_MUX_CTRL_MASK			(0x3 << 2)
+ + #define OMAP3430_MUX_CTRL_SHIFT				0
+ + #define OMAP3430_MUX_CTRL_MASK				(0x3 << 0)
+ + 
+ + /* CM_CLKSTCTRL_EMU */
+ + #define OMAP3430_CLKTRCTRL_EMU_SHIFT			0
+ + #define OMAP3430_CLKTRCTRL_EMU_MASK			(0x3 << 0)
+ + 
+ + /* CM_CLKSTST_EMU */
+ + #define OMAP3430_CLKACTIVITY_EMU_SHIFT			0
+ + #define OMAP3430_CLKACTIVITY_EMU_MASK			(1 << 0)
+ + 
+ + /* CM_CLKSEL2_EMU specific bits */
+ + #define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT		8
+ + #define OMAP3430_CORE_DPLL_EMU_MULT_MASK		(0x7ff << 8)
+ + #define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT		0
+ + #define OMAP3430_CORE_DPLL_EMU_DIV_MASK			(0x7f << 0)
+ + 
+ + /* CM_CLKSEL3_EMU specific bits */
+ + #define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT		8
+ + #define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK		(0x7ff << 8)
+ + #define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT		0
+ + #define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK		(0x7f << 0)
+ + 
+ + /* CM_POLCTRL */
+ + #define OMAP3430_CLKOUT2_POL_MASK			(1 << 0)
+ + 
+ + /* CM_IDLEST_NEON */
+ + #define OMAP3430_ST_NEON_MASK				(1 << 0)
+ + 
+ + /* CM_CLKSTCTRL_NEON */
+ + #define OMAP3430_CLKTRCTRL_NEON_SHIFT			0
+ + #define OMAP3430_CLKTRCTRL_NEON_MASK			(0x3 << 0)
+ + 
+ + /* CM_FCLKEN_USBHOST */
+ + #define OMAP3430ES2_EN_USBHOST2_SHIFT			1
+ + #define OMAP3430ES2_EN_USBHOST2_MASK			(1 << 1)
+ + #define OMAP3430ES2_EN_USBHOST1_SHIFT			0
+ + #define OMAP3430ES2_EN_USBHOST1_MASK			(1 << 0)
+ + 
+ + /* CM_ICLKEN_USBHOST */
+ + #define OMAP3430ES2_EN_USBHOST_SHIFT			0
+ + #define OMAP3430ES2_EN_USBHOST_MASK			(1 << 0)
+ + 
+ + /* CM_IDLEST_USBHOST */
+ + #define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT		1
+ + #define OMAP3430ES2_ST_USBHOST_IDLE_MASK		(1 << 1)
+ + #define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT		0
+ + #define OMAP3430ES2_ST_USBHOST_STDBY_MASK		(1 << 0)
+ + 
+ + /* CM_AUTOIDLE_USBHOST */
+ + #define OMAP3430ES2_AUTO_USBHOST_SHIFT			0
+ + #define OMAP3430ES2_AUTO_USBHOST_MASK			(1 << 0)
+ + 
+ + /* CM_SLEEPDEP_USBHOST */
+ + #define OMAP3430ES2_EN_MPU_SHIFT			1
+ + #define OMAP3430ES2_EN_MPU_MASK				(1 << 1)
+ + #define OMAP3430ES2_EN_IVA2_SHIFT			2
+ + #define OMAP3430ES2_EN_IVA2_MASK			(1 << 2)
+ + 
+ + /* CM_CLKSTCTRL_USBHOST */
+ + #define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT		0
+ + #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK		(3 << 0)
+ + 
+ + /* CM_CLKSTST_USBHOST */
+ + #define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT		0
+ + #define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK		(1 << 0)
+ + 
+ + /*
+ +  *
+ +  */
+ + 
+ + /* OMAP3XXX CM_CLKSTCTRL_*.CLKTRCTRL_* register bit values */
+ + #define OMAP34XX_CLKSTCTRL_DISABLE_AUTO		0x0
+ + #define OMAP34XX_CLKSTCTRL_FORCE_SLEEP		0x1
+ + #define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP		0x2
+ + #define OMAP34XX_CLKSTCTRL_ENABLE_AUTO		0x3
+ + 
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/cm-regbits-44xx.h linux-3.2.1/arch/arm/mach-ckb_3352/cm-regbits-44xx.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/cm-regbits-44xx.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/cm-regbits-44xx.h	2014-11-25 13:19:14.876754319 +0900
+ ***************
+ *** 0 ****
+ --- 1,1445 ----
+ + /*
+ +  * OMAP44xx Clock Management register bits
+ +  *
+ +  * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ +  * Copyright (C) 2009-2010 Nokia Corporation
+ +  *
+ +  * Paul Walmsley (paul@pwsan.com)
+ +  * Rajendra Nayak (rnayak@ti.com)
+ +  * Benoit Cousson (b-cousson@ti.com)
+ +  *
+ +  * This file is automatically generated from the OMAP hardware databases.
+ +  * We respectfully ask that any modifications to this file be coordinated
+ +  * with the public linux-omap@vger.kernel.org mailing list and the
+ +  * authors above to ensure that the autogeneration scripts are kept
+ +  * up-to-date with the file contents.
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
+ + #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
+ + 
+ + /* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
+ + #define OMAP4430_ABE_DYNDEP_SHIFT				3
+ + #define OMAP4430_ABE_DYNDEP_MASK				(1 << 3)
+ + 
+ + /*
+ +  * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
+ +  * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
+ +  */
+ + #define OMAP4430_ABE_STATDEP_SHIFT				3
+ + #define OMAP4430_ABE_STATDEP_MASK				(1 << 3)
+ + 
+ + /* Used by CM_L4CFG_DYNAMICDEP */
+ + #define OMAP4430_ALWONCORE_DYNDEP_SHIFT				16
+ + #define OMAP4430_ALWONCORE_DYNDEP_MASK				(1 << 16)
+ + 
+ + /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
+ + #define OMAP4430_ALWONCORE_STATDEP_SHIFT			16
+ + #define OMAP4430_ALWONCORE_STATDEP_MASK				(1 << 16)
+ + 
+ + /*
+ +  * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE,
+ +  * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU,
+ +  * CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB
+ +  */
+ + #define OMAP4430_AUTO_DPLL_MODE_SHIFT				0
+ + #define OMAP4430_AUTO_DPLL_MODE_MASK				(0x7 << 0)
+ + 
+ + /* Used by CM_L4CFG_DYNAMICDEP */
+ + #define OMAP4430_CEFUSE_DYNDEP_SHIFT				17
+ + #define OMAP4430_CEFUSE_DYNDEP_MASK				(1 << 17)
+ + 
+ + /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
+ + #define OMAP4430_CEFUSE_STATDEP_SHIFT				17
+ + #define OMAP4430_CEFUSE_STATDEP_MASK				(1 << 17)
+ + 
+ + /* Used by CM1_ABE_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT		13
+ + #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK			(1 << 13)
+ + 
+ + /* Used by CM1_ABE_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT		12
+ + #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK		(1 << 12)
+ + 
+ + /* Used by CM_WKUP_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT			9
+ + #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK			(1 << 9)
+ + 
+ + /* Used by CM1_ABE_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT			11
+ + #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK			(1 << 11)
+ + 
+ + /* Used by CM1_ABE_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT			8
+ + #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK			(1 << 8)
+ + 
+ + /* Used by CM_MEMIF_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT		11
+ + #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK			(1 << 11)
+ + 
+ + /* Used by CM_MEMIF_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT		12
+ + #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK		(1 << 12)
+ + 
+ + /* Used by CM_MEMIF_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT		13
+ + #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK		(1 << 13)
+ + 
+ + /* Used by CM_CAM_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT		9
+ + #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK		(1 << 9)
+ + 
+ + /* Used by CM_ALWON_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_SHIFT		12
+ + #define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_MASK		(1 << 12)
+ + 
+ + /* Used by CM_EMU_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT		9
+ + #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK		(1 << 9)
+ + 
+ + /* Used by CM_L4CFG_CLKSTCTRL */
+ + #define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_SHIFT		9
+ + #define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_MASK			(1 << 9)
+ + 
+ + /* Used by CM_CEFUSE_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT		9
+ + #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK		(1 << 9)
+ + 
+ + /* Used by CM_MEMIF_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT			9
+ + #define OMAP4430_CLKACTIVITY_DLL_CLK_MASK			(1 << 9)
+ + 
+ + /* Used by CM_L4PER_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT			9
+ + #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK			(1 << 9)
+ + 
+ + /* Used by CM_L4PER_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT			10
+ + #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK			(1 << 10)
+ + 
+ + /* Used by CM_L4PER_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT			11
+ + #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK			(1 << 11)
+ + 
+ + /* Used by CM_L4PER_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT			12
+ + #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK			(1 << 12)
+ + 
+ + /* Used by CM_L4PER_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT			13
+ + #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK			(1 << 13)
+ + 
+ + /* Used by CM_L4PER_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT			14
+ + #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK			(1 << 14)
+ + 
+ + /* Used by CM_DSS_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT		10
+ + #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK		(1 << 10)
+ + 
+ + /* Used by CM_DSS_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT			9
+ + #define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK			(1 << 9)
+ + 
+ + /* Used by CM_DUCATI_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT			8
+ + #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK			(1 << 8)
+ + 
+ + /* Used by CM_EMU_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT			8
+ + #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK			(1 << 8)
+ + 
+ + /* Used by CM_CAM_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT			10
+ + #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK			(1 << 10)
+ + 
+ + /* Used by CM_L4PER_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT		15
+ + #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK		(1 << 15)
+ + 
+ + /* Used by CM1_ABE_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT		10
+ + #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK		(1 << 10)
+ + 
+ + /* Used by CM_DSS_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT		11
+ + #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK		(1 << 11)
+ + 
+ + /* Used by CM_L3INIT_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT		20
+ + #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK		(1 << 20)
+ + 
+ + /* Used by CM_L3INIT_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT		26
+ + #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK			(1 << 26)
+ + 
+ + /* Used by CM_L3INIT_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT		21
+ + #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK		(1 << 21)
+ + 
+ + /* Used by CM_L3INIT_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT		27
+ + #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK			(1 << 27)
+ + 
+ + /* Used by CM_L3INIT_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT		13
+ + #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK		(1 << 13)
+ + 
+ + /* Used by CM_L3INIT_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT		12
+ + #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK		(1 << 12)
+ + 
+ + /* Used by CM_L3INIT_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT		28
+ + #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK		(1 << 28)
+ + 
+ + /* Used by CM_L3INIT_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT		29
+ + #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK		(1 << 29)
+ + 
+ + /* Used by CM_L3INIT_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT		11
+ + #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK		(1 << 11)
+ + 
+ + /* Used by CM_L3INIT_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT		16
+ + #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK		(1 << 16)
+ + 
+ + /* Used by CM_L3INIT_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT		17
+ + #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK		(1 << 17)
+ + 
+ + /* Used by CM_L3INIT_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT		18
+ + #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK		(1 << 18)
+ + 
+ + /* Used by CM_L3INIT_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT		19
+ + #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK		(1 << 19)
+ + 
+ + /* Used by CM_CAM_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT			8
+ + #define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK			(1 << 8)
+ + 
+ + /* Used by CM_IVAHD_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT		8
+ + #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK		(1 << 8)
+ + 
+ + /* Used by CM_D2D_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT		10
+ + #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK		(1 << 10)
+ + 
+ + /* Used by CM_L3_1_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT			8
+ + #define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK			(1 << 8)
+ + 
+ + /* Used by CM_L3_2_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT			8
+ + #define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK			(1 << 8)
+ + 
+ + /* Used by CM_D2D_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT			8
+ + #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK			(1 << 8)
+ + 
+ + /* Used by CM_SDMA_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT			8
+ + #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK			(1 << 8)
+ + 
+ + /* Used by CM_DSS_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT			8
+ + #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK			(1 << 8)
+ + 
+ + /* Used by CM_MEMIF_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT		8
+ + #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK			(1 << 8)
+ + 
+ + /* Used by CM_GFX_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT			8
+ + #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK			(1 << 8)
+ + 
+ + /* Used by CM_L3INIT_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT		8
+ + #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK			(1 << 8)
+ + 
+ + /* Used by CM_L3INSTR_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT		8
+ + #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK		(1 << 8)
+ + 
+ + /* Used by CM_L4SEC_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT		8
+ + #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK		(1 << 8)
+ + 
+ + /* Used by CM_ALWON_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT			8
+ + #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK			(1 << 8)
+ + 
+ + /* Used by CM_CEFUSE_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT		8
+ + #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK		(1 << 8)
+ + 
+ + /* Used by CM_L4CFG_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT			8
+ + #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK			(1 << 8)
+ + 
+ + /* Used by CM_D2D_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT			9
+ + #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK			(1 << 9)
+ + 
+ + /* Used by CM_L3INIT_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT		9
+ + #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK			(1 << 9)
+ + 
+ + /* Used by CM_L4PER_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT			8
+ + #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK			(1 << 8)
+ + 
+ + /* Used by CM_L4SEC_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT		9
+ + #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK		(1 << 9)
+ + 
+ + /* Used by CM_WKUP_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT		12
+ + #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK			(1 << 12)
+ + 
+ + /* Used by CM_MPU_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT			8
+ + #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK			(1 << 8)
+ + 
+ + /* Used by CM1_ABE_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT		9
+ + #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK			(1 << 9)
+ + 
+ + /* Used by CM_L4PER_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT		16
+ + #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK		(1 << 16)
+ + 
+ + /* Used by CM_L4PER_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT		17
+ + #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK			(1 << 17)
+ + 
+ + /* Used by CM_L4PER_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT		18
+ + #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK			(1 << 18)
+ + 
+ + /* Used by CM_L4PER_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT		19
+ + #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK			(1 << 19)
+ + 
+ + /* Used by CM_L4PER_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT		25
+ + #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK		(1 << 25)
+ + 
+ + /* Used by CM_L4PER_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT		20
+ + #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK		(1 << 20)
+ + 
+ + /* Used by CM_L4PER_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT		21
+ + #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK		(1 << 21)
+ + 
+ + /* Used by CM_L4PER_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT		22
+ + #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK		(1 << 22)
+ + 
+ + /* Used by CM_L4PER_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT		24
+ + #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK			(1 << 24)
+ + 
+ + /* Used by CM_MEMIF_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT			10
+ + #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK			(1 << 10)
+ + 
+ + /* Used by CM_GFX_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT			9
+ + #define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK			(1 << 9)
+ + 
+ + /* Used by CM_ALWON_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT		11
+ + #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK		(1 << 11)
+ + 
+ + /* Used by CM_ALWON_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT		10
+ + #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK			(1 << 10)
+ + 
+ + /* Used by CM_ALWON_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT		9
+ + #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK			(1 << 9)
+ + 
+ + /* Used by CM_WKUP_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT			8
+ + #define OMAP4430_CLKACTIVITY_SYS_CLK_MASK			(1 << 8)
+ + 
+ + /* Used by CM_TESLA_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT		8
+ + #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK		(1 << 8)
+ + 
+ + /* Used by CM_L3INIT_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT		22
+ + #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK			(1 << 22)
+ + 
+ + /* Used by CM_L3INIT_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT		23
+ + #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK			(1 << 23)
+ + 
+ + /* Used by CM_L3INIT_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT		24
+ + #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK			(1 << 24)
+ + 
+ + /* Used by CM_L3INIT_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT		10
+ + #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK		(1 << 10)
+ + 
+ + /* Used by CM_L3INIT_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT			14
+ + #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK			(1 << 14)
+ + 
+ + /* Used by CM_L3INIT_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT		15
+ + #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK		(1 << 15)
+ + 
+ + /* Used by CM_WKUP_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT			10
+ + #define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK			(1 << 10)
+ + 
+ + /* Used by CM_L3INIT_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT		30
+ + #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK			(1 << 30)
+ + 
+ + /* Used by CM_L3INIT_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT		25
+ + #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK		(1 << 25)
+ + 
+ + /* Used by CM_WKUP_CLKSTCTRL */
+ + #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT		11
+ + #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK		(1 << 11)
+ + 
+ + /* Used by CM_WKUP_CLKSTCTRL */
+ + #define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_SHIFT		13
+ + #define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_MASK			(1 << 13)
+ + 
+ + /*
+ +  * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL,
+ +  * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
+ +  * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MMC6_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
+ +  * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL,
+ +  * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL,
+ +  * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL,
+ +  * CM_WKUP_TIMER1_CLKCTRL
+ +  */
+ + #define OMAP4430_CLKSEL_SHIFT					24
+ + #define OMAP4430_CLKSEL_MASK					(1 << 24)
+ + 
+ + /*
+ +  * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL,
+ +  * CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ, CM_L4_WKUP_CLKSEL
+ +  */
+ + #define OMAP4430_CLKSEL_0_0_SHIFT				0
+ + #define OMAP4430_CLKSEL_0_0_MASK				(1 << 0)
+ + 
+ + /* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */
+ + #define OMAP4430_CLKSEL_0_1_SHIFT				0
+ + #define OMAP4430_CLKSEL_0_1_MASK				(0x3 << 0)
+ + 
+ + /* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */
+ + #define OMAP4430_CLKSEL_24_25_SHIFT				24
+ + #define OMAP4430_CLKSEL_24_25_MASK				(0x3 << 24)
+ + 
+ + /* Used by CM_L3INIT_USB_OTG_CLKCTRL */
+ + #define OMAP4430_CLKSEL_60M_SHIFT				24
+ + #define OMAP4430_CLKSEL_60M_MASK				(1 << 24)
+ + 
+ + /* Used by CM_MPU_MPU_CLKCTRL */
+ + #define OMAP4460_CLKSEL_ABE_DIV_MODE_SHIFT			25
+ + #define OMAP4460_CLKSEL_ABE_DIV_MODE_MASK			(1 << 25)
+ + 
+ + /* Used by CM1_ABE_AESS_CLKCTRL */
+ + #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT				24
+ + #define OMAP4430_CLKSEL_AESS_FCLK_MASK				(1 << 24)
+ + 
+ + /* Used by CM_CLKSEL_CORE */
+ + #define OMAP4430_CLKSEL_CORE_SHIFT				0
+ + #define OMAP4430_CLKSEL_CORE_MASK				(1 << 0)
+ + 
+ + /* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */
+ + #define OMAP4430_CLKSEL_CORE_1_1_SHIFT				1
+ + #define OMAP4430_CLKSEL_CORE_1_1_MASK				(1 << 1)
+ + 
+ + /* Used by CM_WKUP_USIM_CLKCTRL */
+ + #define OMAP4430_CLKSEL_DIV_SHIFT				24
+ + #define OMAP4430_CLKSEL_DIV_MASK				(1 << 24)
+ + 
+ + /* Used by CM_MPU_MPU_CLKCTRL */
+ + #define OMAP4460_CLKSEL_EMIF_DIV_MODE_SHIFT			24
+ + #define OMAP4460_CLKSEL_EMIF_DIV_MODE_MASK			(1 << 24)
+ + 
+ + /* Used by CM_CAM_FDIF_CLKCTRL */
+ + #define OMAP4430_CLKSEL_FCLK_SHIFT				24
+ + #define OMAP4430_CLKSEL_FCLK_MASK				(0x3 << 24)
+ + 
+ + /* Used by CM_L4PER_MCBSP4_CLKCTRL */
+ + #define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT			25
+ + #define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK			(1 << 25)
+ + 
+ + /*
+ +  * Renamed from CLKSEL_INTERNAL_SOURCE Used by CM1_ABE_DMIC_CLKCTRL,
+ +  * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
+ +  * CM1_ABE_MCBSP3_CLKCTRL
+ +  */
+ + #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT	26
+ + #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK	(0x3 << 26)
+ + 
+ + /* Used by CM_CLKSEL_CORE */
+ + #define OMAP4430_CLKSEL_L3_SHIFT				4
+ + #define OMAP4430_CLKSEL_L3_MASK					(1 << 4)
+ + 
+ + /* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
+ + #define OMAP4430_CLKSEL_L3_SHADOW_SHIFT				2
+ + #define OMAP4430_CLKSEL_L3_SHADOW_MASK				(1 << 2)
+ + 
+ + /* Used by CM_CLKSEL_CORE */
+ + #define OMAP4430_CLKSEL_L4_SHIFT				8
+ + #define OMAP4430_CLKSEL_L4_MASK					(1 << 8)
+ + 
+ + /* Used by CM_CLKSEL_ABE */
+ + #define OMAP4430_CLKSEL_OPP_SHIFT				0
+ + #define OMAP4430_CLKSEL_OPP_MASK				(0x3 << 0)
+ + 
+ + /* Used by CM_EMU_DEBUGSS_CLKCTRL */
+ + #define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT			27
+ + #define OMAP4430_CLKSEL_PMD_STM_CLK_MASK			(0x7 << 27)
+ + 
+ + /* Used by CM_EMU_DEBUGSS_CLKCTRL */
+ + #define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT			24
+ + #define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK			(0x7 << 24)
+ + 
+ + /* Used by CM_GFX_GFX_CLKCTRL */
+ + #define OMAP4430_CLKSEL_SGX_FCLK_SHIFT				24
+ + #define OMAP4430_CLKSEL_SGX_FCLK_MASK				(1 << 24)
+ + 
+ + /*
+ +  * Used by CM1_ABE_DMIC_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL,
+ +  * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL
+ +  */
+ + #define OMAP4430_CLKSEL_SOURCE_SHIFT				24
+ + #define OMAP4430_CLKSEL_SOURCE_MASK				(0x3 << 24)
+ + 
+ + /* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */
+ + #define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT			24
+ + #define OMAP4430_CLKSEL_SOURCE_24_24_MASK			(1 << 24)
+ + 
+ + /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
+ + #define OMAP4430_CLKSEL_UTMI_P1_SHIFT				24
+ + #define OMAP4430_CLKSEL_UTMI_P1_MASK				(1 << 24)
+ + 
+ + /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
+ + #define OMAP4430_CLKSEL_UTMI_P2_SHIFT				25
+ + #define OMAP4430_CLKSEL_UTMI_P2_MASK				(1 << 25)
+ + 
+ + /*
+ +  * Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL,
+ +  * CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL,
+ +  * CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL,
+ +  * CM_L3INIT_CLKSTCTRL, CM_L3INSTR_CLKSTCTRL, CM_L3_1_CLKSTCTRL,
+ +  * CM_L3_2_CLKSTCTRL, CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL,
+ +  * CM_L4SEC_CLKSTCTRL, CM_MEMIF_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_SDMA_CLKSTCTRL,
+ +  * CM_TESLA_CLKSTCTRL, CM_WKUP_CLKSTCTRL
+ +  */
+ + #define OMAP4430_CLKTRCTRL_SHIFT				0
+ + #define OMAP4430_CLKTRCTRL_MASK					(0x3 << 0)
+ + 
+ + /* Used by CM_EMU_OVERRIDE_DPLL_CORE */
+ + #define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT			0
+ + #define OMAP4430_CORE_DPLL_EMU_DIV_MASK				(0x7f << 0)
+ + 
+ + /* Used by CM_EMU_OVERRIDE_DPLL_CORE */
+ + #define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT			8
+ + #define OMAP4430_CORE_DPLL_EMU_MULT_MASK			(0x7ff << 8)
+ + 
+ + /* Used by REVISION_CM1, REVISION_CM2 */
+ + #define OMAP4430_CUSTOM_SHIFT					6
+ + #define OMAP4430_CUSTOM_MASK					(0x3 << 6)
+ + 
+ + /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
+ + #define OMAP4430_D2D_DYNDEP_SHIFT				18
+ + #define OMAP4430_D2D_DYNDEP_MASK				(1 << 18)
+ + 
+ + /* Used by CM_MPU_STATICDEP */
+ + #define OMAP4430_D2D_STATDEP_SHIFT				18
+ + #define OMAP4430_D2D_STATDEP_MASK				(1 << 18)
+ + 
+ + /* Used by CM_CLKSEL_DPLL_MPU */
+ + #define OMAP4460_DCC_COUNT_MAX_SHIFT				24
+ + #define OMAP4460_DCC_COUNT_MAX_MASK				(0xff << 24)
+ + 
+ + /* Used by CM_CLKSEL_DPLL_MPU */
+ + #define OMAP4460_DCC_EN_SHIFT					22
+ + #define OMAP4460_DCC_EN_MASK					(1 << 22)
+ + 
+ + /*
+ +  * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
+ +  * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA,
+ +  * CM_SSC_DELTAMSTEP_DPLL_MPU, CM_SSC_DELTAMSTEP_DPLL_PER,
+ +  * CM_SSC_DELTAMSTEP_DPLL_UNIPRO, CM_SSC_DELTAMSTEP_DPLL_USB
+ +  */
+ + #define OMAP4430_DELTAMSTEP_SHIFT				0
+ + #define OMAP4430_DELTAMSTEP_MASK				(0xfffff << 0)
+ + 
+ + /* Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_USB */
+ + #define OMAP4460_DELTAMSTEP_0_20_SHIFT				0
+ + #define OMAP4460_DELTAMSTEP_0_20_MASK				(0x1fffff << 0)
+ + 
+ + /* Used by CM_DLL_CTRL */
+ + #define OMAP4430_DLL_OVERRIDE_SHIFT				0
+ + #define OMAP4430_DLL_OVERRIDE_MASK				(1 << 0)
+ + 
+ + /* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */
+ + #define OMAP4430_DLL_OVERRIDE_2_2_SHIFT				2
+ + #define OMAP4430_DLL_OVERRIDE_2_2_MASK				(1 << 2)
+ + 
+ + /* Used by CM_SHADOW_FREQ_CONFIG1 */
+ + #define OMAP4430_DLL_RESET_SHIFT				3
+ + #define OMAP4430_DLL_RESET_MASK					(1 << 3)
+ + 
+ + /*
+ +  * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
+ +  * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
+ +  * CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB
+ +  */
+ + #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT				23
+ + #define OMAP4430_DPLL_BYP_CLKSEL_MASK				(1 << 23)
+ + 
+ + /* Used by CM_CLKDCOLDO_DPLL_USB */
+ + #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT			8
+ + #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK			(1 << 8)
+ + 
+ + /* Used by CM_CLKSEL_DPLL_CORE */
+ + #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT			20
+ + #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK			(1 << 20)
+ + 
+ + /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
+ + #define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT			0
+ + #define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK			(0x1f << 0)
+ + 
+ + /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
+ + #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT			5
+ + #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK			(1 << 5)
+ + 
+ + /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
+ + #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT			8
+ + #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK			(1 << 8)
+ + 
+ + /* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
+ + #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT			10
+ + #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK			(1 << 10)
+ + 
+ + /*
+ +  * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
+ +  * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
+ +  */
+ + #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT				0
+ + #define OMAP4430_DPLL_CLKOUT_DIV_MASK				(0x1f << 0)
+ + 
+ + /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */
+ + #define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT			0
+ + #define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK			(0x7f << 0)
+ + 
+ + /*
+ +  * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
+ +  * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
+ +  */
+ + #define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT			5
+ + #define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK			(1 << 5)
+ + 
+ + /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */
+ + #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT		7
+ + #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK		(1 << 7)
+ + 
+ + /*
+ +  * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
+ +  * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
+ +  */
+ + #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT			8
+ + #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK			(1 << 8)
+ + 
+ + /* Used by CM_SHADOW_FREQ_CONFIG1 */
+ + #define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT			8
+ + #define OMAP4430_DPLL_CORE_DPLL_EN_MASK				(0x7 << 8)
+ + 
+ + /* Used by CM_SHADOW_FREQ_CONFIG1 */
+ + #define OMAP4430_DPLL_CORE_M2_DIV_SHIFT				11
+ + #define OMAP4430_DPLL_CORE_M2_DIV_MASK				(0x1f << 11)
+ + 
+ + /* Used by CM_SHADOW_FREQ_CONFIG2 */
+ + #define OMAP4430_DPLL_CORE_M5_DIV_SHIFT				3
+ + #define OMAP4430_DPLL_CORE_M5_DIV_MASK				(0x1f << 3)
+ + 
+ + /*
+ +  * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
+ +  * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
+ +  * CM_CLKSEL_DPLL_UNIPRO
+ +  */
+ + #define OMAP4430_DPLL_DIV_SHIFT					0
+ + #define OMAP4430_DPLL_DIV_MASK					(0x7f << 0)
+ + 
+ + /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */
+ + #define OMAP4430_DPLL_DIV_0_7_SHIFT				0
+ + #define OMAP4430_DPLL_DIV_0_7_MASK				(0xff << 0)
+ + 
+ + /*
+ +  * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
+ +  * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
+ +  */
+ + #define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT			8
+ + #define OMAP4430_DPLL_DRIFTGUARD_EN_MASK			(1 << 8)
+ + 
+ + /* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */
+ + #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT			3
+ + #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK			(1 << 3)
+ + 
+ + /*
+ +  * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
+ +  * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
+ +  * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
+ +  */
+ + #define OMAP4430_DPLL_EN_SHIFT					0
+ + #define OMAP4430_DPLL_EN_MASK					(0x7 << 0)
+ + 
+ + /*
+ +  * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
+ +  * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
+ +  * CM_CLKMODE_DPLL_UNIPRO
+ +  */
+ + #define OMAP4430_DPLL_LPMODE_EN_SHIFT				10
+ + #define OMAP4430_DPLL_LPMODE_EN_MASK				(1 << 10)
+ + 
+ + /*
+ +  * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
+ +  * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
+ +  * CM_CLKSEL_DPLL_UNIPRO
+ +  */
+ + #define OMAP4430_DPLL_MULT_SHIFT				8
+ + #define OMAP4430_DPLL_MULT_MASK					(0x7ff << 8)
+ + 
+ + /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */
+ + #define OMAP4430_DPLL_MULT_USB_SHIFT				8
+ + #define OMAP4430_DPLL_MULT_USB_MASK				(0xfff << 8)
+ + 
+ + /*
+ +  * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
+ +  * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
+ +  * CM_CLKMODE_DPLL_UNIPRO
+ +  */
+ + #define OMAP4430_DPLL_REGM4XEN_SHIFT				11
+ + #define OMAP4430_DPLL_REGM4XEN_MASK				(1 << 11)
+ + 
+ + /* Used by CM_CLKSEL_DPLL_USB */
+ + #define OMAP4430_DPLL_SD_DIV_SHIFT				24
+ + #define OMAP4430_DPLL_SD_DIV_MASK				(0xff << 24)
+ + 
+ + /*
+ +  * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
+ +  * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
+ +  * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
+ +  */
+ + #define OMAP4430_DPLL_SSC_ACK_SHIFT				13
+ + #define OMAP4430_DPLL_SSC_ACK_MASK				(1 << 13)
+ + 
+ + /*
+ +  * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
+ +  * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
+ +  * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
+ +  */
+ + #define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT			14
+ + #define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK			(1 << 14)
+ + 
+ + /*
+ +  * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
+ +  * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
+ +  * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
+ +  */
+ + #define OMAP4430_DPLL_SSC_EN_SHIFT				12
+ + #define OMAP4430_DPLL_SSC_EN_MASK				(1 << 12)
+ + 
+ + /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
+ + #define OMAP4430_DSS_DYNDEP_SHIFT				8
+ + #define OMAP4430_DSS_DYNDEP_MASK				(1 << 8)
+ + 
+ + /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
+ + #define OMAP4430_DSS_STATDEP_SHIFT				8
+ + #define OMAP4430_DSS_STATDEP_MASK				(1 << 8)
+ + 
+ + /* Used by CM_L3_2_DYNAMICDEP */
+ + #define OMAP4430_DUCATI_DYNDEP_SHIFT				0
+ + #define OMAP4430_DUCATI_DYNDEP_MASK				(1 << 0)
+ + 
+ + /* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
+ + #define OMAP4430_DUCATI_STATDEP_SHIFT				0
+ + #define OMAP4430_DUCATI_STATDEP_MASK				(1 << 0)
+ + 
+ + /* Used by CM_SHADOW_FREQ_CONFIG1 */
+ + #define OMAP4430_FREQ_UPDATE_SHIFT				0
+ + #define OMAP4430_FREQ_UPDATE_MASK				(1 << 0)
+ + 
+ + /* Used by REVISION_CM1, REVISION_CM2 */
+ + #define OMAP4430_FUNC_SHIFT					16
+ + #define OMAP4430_FUNC_MASK					(0xfff << 16)
+ + 
+ + /* Used by CM_L3_2_DYNAMICDEP */
+ + #define OMAP4430_GFX_DYNDEP_SHIFT				10
+ + #define OMAP4430_GFX_DYNDEP_MASK				(1 << 10)
+ + 
+ + /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
+ + #define OMAP4430_GFX_STATDEP_SHIFT				10
+ + #define OMAP4430_GFX_STATDEP_MASK				(1 << 10)
+ + 
+ + /* Used by CM_SHADOW_FREQ_CONFIG2 */
+ + #define OMAP4430_GPMC_FREQ_UPDATE_SHIFT				0
+ + #define OMAP4430_GPMC_FREQ_UPDATE_MASK				(1 << 0)
+ + 
+ + /*
+ +  * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
+ +  * CM_DIV_M4_DPLL_PER
+ +  */
+ + #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT			0
+ + #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK			(0x1f << 0)
+ + 
+ + /*
+ +  * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
+ +  * CM_DIV_M4_DPLL_PER
+ +  */
+ + #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT		5
+ + #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK		(1 << 5)
+ + 
+ + /*
+ +  * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
+ +  * CM_DIV_M4_DPLL_PER
+ +  */
+ + #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT		8
+ + #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK		(1 << 8)
+ + 
+ + /*
+ +  * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
+ +  * CM_DIV_M4_DPLL_PER
+ +  */
+ + #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT			12
+ + #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK			(1 << 12)
+ + 
+ + /*
+ +  * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
+ +  * CM_DIV_M5_DPLL_PER
+ +  */
+ + #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT			0
+ + #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK			(0x1f << 0)
+ + 
+ + /*
+ +  * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
+ +  * CM_DIV_M5_DPLL_PER
+ +  */
+ + #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT		5
+ + #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK		(1 << 5)
+ + 
+ + /*
+ +  * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
+ +  * CM_DIV_M5_DPLL_PER
+ +  */
+ + #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT		8
+ + #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK		(1 << 8)
+ + 
+ + /*
+ +  * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
+ +  * CM_DIV_M5_DPLL_PER
+ +  */
+ + #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT			12
+ + #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK			(1 << 12)
+ + 
+ + /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
+ + #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT			0
+ + #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK			(0x1f << 0)
+ + 
+ + /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
+ + #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT		5
+ + #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK		(1 << 5)
+ + 
+ + /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
+ + #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT		8
+ + #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK		(1 << 8)
+ + 
+ + /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
+ + #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT			12
+ + #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK			(1 << 12)
+ + 
+ + /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
+ + #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT			0
+ + #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK			(0x1f << 0)
+ + 
+ + /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
+ + #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT		5
+ + #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK		(1 << 5)
+ + 
+ + /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
+ + #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT		8
+ + #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK		(1 << 8)
+ + 
+ + /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
+ + #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT			12
+ + #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK			(1 << 12)
+ + 
+ + /*
+ +  * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL,
+ +  * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
+ +  * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL,
+ +  * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
+ +  * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
+ +  * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
+ +  * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
+ +  * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
+ +  * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
+ +  * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
+ +  * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
+ +  * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
+ +  * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
+ +  * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
+ +  * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
+ +  * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
+ +  * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
+ +  * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL,
+ +  * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL,
+ +  * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
+ +  * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
+ +  * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
+ +  * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
+ +  * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
+ +  * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
+ +  * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
+ +  * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
+ +  * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL,
+ +  * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL,
+ +  * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL,
+ +  * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL,
+ +  * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL,
+ +  * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL,
+ +  * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
+ +  * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
+ +  * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
+ +  * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
+ +  * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL,
+ +  * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
+ +  * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
+ +  * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
+ +  * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL,
+ +  * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL,
+ +  * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL,
+ +  * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
+ +  */
+ + #define OMAP4430_IDLEST_SHIFT					16
+ + #define OMAP4430_IDLEST_MASK					(0x3 << 16)
+ + 
+ + /* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
+ + #define OMAP4430_ISS_DYNDEP_SHIFT				9
+ + #define OMAP4430_ISS_DYNDEP_MASK				(1 << 9)
+ + 
+ + /*
+ +  * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
+ +  * CM_TESLA_STATICDEP
+ +  */
+ + #define OMAP4430_ISS_STATDEP_SHIFT				9
+ + #define OMAP4430_ISS_STATDEP_MASK				(1 << 9)
+ + 
+ + /* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
+ + #define OMAP4430_IVAHD_DYNDEP_SHIFT				2
+ + #define OMAP4430_IVAHD_DYNDEP_MASK				(1 << 2)
+ + 
+ + /*
+ +  * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
+ +  * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_L3INIT_STATICDEP,
+ +  * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
+ +  */
+ + #define OMAP4430_IVAHD_STATDEP_SHIFT				2
+ + #define OMAP4430_IVAHD_STATDEP_MASK				(1 << 2)
+ + 
+ + /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
+ + #define OMAP4430_L3INIT_DYNDEP_SHIFT				7
+ + #define OMAP4430_L3INIT_DYNDEP_MASK				(1 << 7)
+ + 
+ + /*
+ +  * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_MPU_STATICDEP,
+ +  * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
+ +  */
+ + #define OMAP4430_L3INIT_STATDEP_SHIFT				7
+ + #define OMAP4430_L3INIT_STATDEP_MASK				(1 << 7)
+ + 
+ + /*
+ +  * Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
+ +  * CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
+ +  */
+ + #define OMAP4430_L3_1_DYNDEP_SHIFT				5
+ + #define OMAP4430_L3_1_DYNDEP_MASK				(1 << 5)
+ + 
+ + /*
+ +  * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
+ +  * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
+ +  * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
+ +  * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
+ +  */
+ + #define OMAP4430_L3_1_STATDEP_SHIFT				5
+ + #define OMAP4430_L3_1_STATDEP_MASK				(1 << 5)
+ + 
+ + /*
+ +  * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP,
+ +  * CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP, CM_IVAHD_DYNAMICDEP,
+ +  * CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
+ +  * CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP
+ +  */
+ + #define OMAP4430_L3_2_DYNDEP_SHIFT				6
+ + #define OMAP4430_L3_2_DYNDEP_MASK				(1 << 6)
+ + 
+ + /*
+ +  * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
+ +  * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
+ +  * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
+ +  * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
+ +  */
+ + #define OMAP4430_L3_2_STATDEP_SHIFT				6
+ + #define OMAP4430_L3_2_STATDEP_MASK				(1 << 6)
+ + 
+ + /* Used by CM_L3_1_DYNAMICDEP */
+ + #define OMAP4430_L4CFG_DYNDEP_SHIFT				12
+ + #define OMAP4430_L4CFG_DYNDEP_MASK				(1 << 12)
+ + 
+ + /*
+ +  * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
+ +  * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
+ +  */
+ + #define OMAP4430_L4CFG_STATDEP_SHIFT				12
+ + #define OMAP4430_L4CFG_STATDEP_MASK				(1 << 12)
+ + 
+ + /* Used by CM_L3_2_DYNAMICDEP */
+ + #define OMAP4430_L4PER_DYNDEP_SHIFT				13
+ + #define OMAP4430_L4PER_DYNDEP_MASK				(1 << 13)
+ + 
+ + /*
+ +  * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
+ +  * CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
+ +  */
+ + #define OMAP4430_L4PER_STATDEP_SHIFT				13
+ + #define OMAP4430_L4PER_STATDEP_MASK				(1 << 13)
+ + 
+ + /* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
+ + #define OMAP4430_L4SEC_DYNDEP_SHIFT				14
+ + #define OMAP4430_L4SEC_DYNDEP_MASK				(1 << 14)
+ + 
+ + /*
+ +  * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
+ +  * CM_SDMA_STATICDEP
+ +  */
+ + #define OMAP4430_L4SEC_STATDEP_SHIFT				14
+ + #define OMAP4430_L4SEC_STATDEP_MASK				(1 << 14)
+ + 
+ + /* Used by CM_L4CFG_DYNAMICDEP */
+ + #define OMAP4430_L4WKUP_DYNDEP_SHIFT				15
+ + #define OMAP4430_L4WKUP_DYNDEP_MASK				(1 << 15)
+ + 
+ + /*
+ +  * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
+ +  * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
+ +  */
+ + #define OMAP4430_L4WKUP_STATDEP_SHIFT				15
+ + #define OMAP4430_L4WKUP_STATDEP_MASK				(1 << 15)
+ + 
+ + /*
+ +  * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
+ +  * CM_MPU_DYNAMICDEP
+ +  */
+ + #define OMAP4430_MEMIF_DYNDEP_SHIFT				4
+ + #define OMAP4430_MEMIF_DYNDEP_MASK				(1 << 4)
+ + 
+ + /*
+ +  * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
+ +  * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
+ +  * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
+ +  * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
+ +  */
+ + #define OMAP4430_MEMIF_STATDEP_SHIFT				4
+ + #define OMAP4430_MEMIF_STATDEP_MASK				(1 << 4)
+ + 
+ + /*
+ +  * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
+ +  * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
+ +  * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER,
+ +  * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
+ +  */
+ + #define OMAP4430_MODFREQDIV_EXPONENT_SHIFT			8
+ + #define OMAP4430_MODFREQDIV_EXPONENT_MASK			(0x7 << 8)
+ + 
+ + /*
+ +  * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
+ +  * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
+ +  * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER,
+ +  * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
+ +  */
+ + #define OMAP4430_MODFREQDIV_MANTISSA_SHIFT			0
+ + #define OMAP4430_MODFREQDIV_MANTISSA_MASK			(0x7f << 0)
+ + 
+ + /*
+ +  * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL,
+ +  * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
+ +  * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL,
+ +  * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
+ +  * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
+ +  * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
+ +  * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
+ +  * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
+ +  * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
+ +  * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
+ +  * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
+ +  * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
+ +  * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
+ +  * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
+ +  * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
+ +  * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
+ +  * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
+ +  * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL,
+ +  * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL,
+ +  * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
+ +  * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
+ +  * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
+ +  * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
+ +  * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
+ +  * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
+ +  * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
+ +  * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
+ +  * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL,
+ +  * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL,
+ +  * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL,
+ +  * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL,
+ +  * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL,
+ +  * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL,
+ +  * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
+ +  * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
+ +  * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
+ +  * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
+ +  * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL,
+ +  * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
+ +  * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
+ +  * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
+ +  * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL,
+ +  * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL,
+ +  * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL,
+ +  * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
+ +  */
+ + #define OMAP4430_MODULEMODE_SHIFT				0
+ + #define OMAP4430_MODULEMODE_MASK				(0x3 << 0)
+ + 
+ + /* Used by CM_L4CFG_DYNAMICDEP */
+ + #define OMAP4460_MPU_DYNDEP_SHIFT				19
+ + #define OMAP4460_MPU_DYNDEP_MASK				(1 << 19)
+ + 
+ + /* Used by CM_DSS_DSS_CLKCTRL */
+ + #define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT			9
+ + #define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK			(1 << 9)
+ + 
+ + /* Used by CM_WKUP_BANDGAP_CLKCTRL */
+ + #define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT			8
+ + #define OMAP4430_OPTFCLKEN_BGAP_32K_MASK			(1 << 8)
+ + 
+ + /* Used by CM_ALWON_USBPHY_CLKCTRL */
+ + #define OMAP4430_OPTFCLKEN_CLK32K_SHIFT				8
+ + #define OMAP4430_OPTFCLKEN_CLK32K_MASK				(1 << 8)
+ + 
+ + /* Used by CM_CAM_ISS_CLKCTRL */
+ + #define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT			8
+ + #define OMAP4430_OPTFCLKEN_CTRLCLK_MASK				(1 << 8)
+ + 
+ + /*
+ +  * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL,
+ +  * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL,
+ +  * CM_WKUP_GPIO1_CLKCTRL
+ +  */
+ + #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT				8
+ + #define OMAP4430_OPTFCLKEN_DBCLK_MASK				(1 << 8)
+ + 
+ + /* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */
+ + #define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT			8
+ + #define OMAP4430_OPTFCLKEN_DLL_CLK_MASK				(1 << 8)
+ + 
+ + /* Used by CM_DSS_DSS_CLKCTRL */
+ + #define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT				8
+ + #define OMAP4430_OPTFCLKEN_DSSCLK_MASK				(1 << 8)
+ + 
+ + /* Used by CM_WKUP_USIM_CLKCTRL */
+ + #define OMAP4430_OPTFCLKEN_FCLK_SHIFT				8
+ + #define OMAP4430_OPTFCLKEN_FCLK_MASK				(1 << 8)
+ + 
+ + /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
+ + #define OMAP4430_OPTFCLKEN_FCLK0_SHIFT				8
+ + #define OMAP4430_OPTFCLKEN_FCLK0_MASK				(1 << 8)
+ + 
+ + /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
+ + #define OMAP4430_OPTFCLKEN_FCLK1_SHIFT				9
+ + #define OMAP4430_OPTFCLKEN_FCLK1_MASK				(1 << 9)
+ + 
+ + /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
+ + #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT				10
+ + #define OMAP4430_OPTFCLKEN_FCLK2_MASK				(1 << 10)
+ + 
+ + /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
+ + #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT			15
+ + #define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK			(1 << 15)
+ + 
+ + /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
+ + #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT		13
+ + #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK			(1 << 13)
+ + 
+ + /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
+ + #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT		14
+ + #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK			(1 << 14)
+ + 
+ + /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
+ + #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT			11
+ + #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK			(1 << 11)
+ + 
+ + /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
+ + #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT			12
+ + #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK			(1 << 12)
+ + 
+ + /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
+ + #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT			8
+ + #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK			(1 << 8)
+ + 
+ + /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
+ + #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT		9
+ + #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK			(1 << 9)
+ + 
+ + /* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */
+ + #define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT			8
+ + #define OMAP4430_OPTFCLKEN_PHY_48M_MASK				(1 << 8)
+ + 
+ + /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
+ + #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT			10
+ + #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK			(1 << 10)
+ + 
+ + /* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */
+ + #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT		11
+ + #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK		(1 << 11)
+ + 
+ + /* Used by CM_DSS_DSS_CLKCTRL */
+ + #define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT			10
+ + #define OMAP4430_OPTFCLKEN_SYS_CLK_MASK				(1 << 10)
+ + 
+ + /* Used by CM_WKUP_BANDGAP_CLKCTRL */
+ + #define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT			8
+ + #define OMAP4460_OPTFCLKEN_TS_FCLK_MASK				(1 << 8)
+ + 
+ + /* Used by CM_DSS_DSS_CLKCTRL */
+ + #define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT				11
+ + #define OMAP4430_OPTFCLKEN_TV_CLK_MASK				(1 << 11)
+ + 
+ + /* Used by CM_L3INIT_UNIPRO1_CLKCTRL */
+ + #define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT			8
+ + #define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK			(1 << 8)
+ + 
+ + /* Used by CM_L3INIT_USB_TLL_CLKCTRL */
+ + #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT			8
+ + #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK			(1 << 8)
+ + 
+ + /* Used by CM_L3INIT_USB_TLL_CLKCTRL */
+ + #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT			9
+ + #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK			(1 << 9)
+ + 
+ + /* Used by CM_L3INIT_USB_TLL_CLKCTRL */
+ + #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT			10
+ + #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK			(1 << 10)
+ + 
+ + /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
+ + #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT			8
+ + #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK			(1 << 8)
+ + 
+ + /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
+ + #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT			9
+ + #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK			(1 << 9)
+ + 
+ + /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
+ + #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT			10
+ + #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK			(1 << 10)
+ + 
+ + /* Used by CM_L3INIT_USB_OTG_CLKCTRL */
+ + #define OMAP4430_OPTFCLKEN_XCLK_SHIFT				8
+ + #define OMAP4430_OPTFCLKEN_XCLK_MASK				(1 << 8)
+ + 
+ + /* Used by CM_EMU_OVERRIDE_DPLL_CORE */
+ + #define OMAP4430_OVERRIDE_ENABLE_SHIFT				19
+ + #define OMAP4430_OVERRIDE_ENABLE_MASK				(1 << 19)
+ + 
+ + /* Used by CM_CLKSEL_ABE */
+ + #define OMAP4430_PAD_CLKS_GATE_SHIFT				8
+ + #define OMAP4430_PAD_CLKS_GATE_MASK				(1 << 8)
+ + 
+ + /* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */
+ + #define OMAP4430_PERF_CURRENT_SHIFT				0
+ + #define OMAP4430_PERF_CURRENT_MASK				(0xff << 0)
+ + 
+ + /*
+ +  * Used by CM_CORE_DVFS_PERF1, CM_CORE_DVFS_PERF2, CM_CORE_DVFS_PERF3,
+ +  * CM_CORE_DVFS_PERF4, CM_IVA_DVFS_PERF_ABE, CM_IVA_DVFS_PERF_IVAHD,
+ +  * CM_IVA_DVFS_PERF_TESLA
+ +  */
+ + #define OMAP4430_PERF_REQ_SHIFT					0
+ + #define OMAP4430_PERF_REQ_MASK					(0xff << 0)
+ + 
+ + /* Used by CM_RESTORE_ST */
+ + #define OMAP4430_PHASE1_COMPLETED_SHIFT				0
+ + #define OMAP4430_PHASE1_COMPLETED_MASK				(1 << 0)
+ + 
+ + /* Used by CM_RESTORE_ST */
+ + #define OMAP4430_PHASE2A_COMPLETED_SHIFT			1
+ + #define OMAP4430_PHASE2A_COMPLETED_MASK				(1 << 1)
+ + 
+ + /* Used by CM_RESTORE_ST */
+ + #define OMAP4430_PHASE2B_COMPLETED_SHIFT			2
+ + #define OMAP4430_PHASE2B_COMPLETED_MASK				(1 << 2)
+ + 
+ + /* Used by CM_EMU_DEBUGSS_CLKCTRL */
+ + #define OMAP4430_PMD_STM_MUX_CTRL_SHIFT				20
+ + #define OMAP4430_PMD_STM_MUX_CTRL_MASK				(0x3 << 20)
+ + 
+ + /* Used by CM_EMU_DEBUGSS_CLKCTRL */
+ + #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT			22
+ + #define OMAP4430_PMD_TRACE_MUX_CTRL_MASK			(0x3 << 22)
+ + 
+ + /* Used by CM_DYN_DEP_PRESCAL */
+ + #define OMAP4430_PRESCAL_SHIFT					0
+ + #define OMAP4430_PRESCAL_MASK					(0x3f << 0)
+ + 
+ + /* Used by REVISION_CM1, REVISION_CM2 */
+ + #define OMAP4430_R_RTL_SHIFT					11
+ + #define OMAP4430_R_RTL_MASK					(0x1f << 11)
+ + 
+ + /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL */
+ + #define OMAP4430_SAR_MODE_SHIFT					4
+ + #define OMAP4430_SAR_MODE_MASK					(1 << 4)
+ + 
+ + /* Used by CM_SCALE_FCLK */
+ + #define OMAP4430_SCALE_FCLK_SHIFT				0
+ + #define OMAP4430_SCALE_FCLK_MASK				(1 << 0)
+ + 
+ + /* Used by REVISION_CM1, REVISION_CM2 */
+ + #define OMAP4430_SCHEME_SHIFT					30
+ + #define OMAP4430_SCHEME_MASK					(0x3 << 30)
+ + 
+ + /* Used by CM_L4CFG_DYNAMICDEP */
+ + #define OMAP4430_SDMA_DYNDEP_SHIFT				11
+ + #define OMAP4430_SDMA_DYNDEP_MASK				(1 << 11)
+ + 
+ + /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
+ + #define OMAP4430_SDMA_STATDEP_SHIFT				11
+ + #define OMAP4430_SDMA_STATDEP_MASK				(1 << 11)
+ + 
+ + /* Used by CM_CLKSEL_ABE */
+ + #define OMAP4430_SLIMBUS_CLK_GATE_SHIFT				10
+ + #define OMAP4430_SLIMBUS_CLK_GATE_MASK				(1 << 10)
+ + 
+ + /*
+ +  * Used by CM1_ABE_AESS_CLKCTRL, CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL,
+ +  * CM_D2D_SAD2D_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL,
+ +  * CM_DUCATI_DUCATI_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL,
+ +  * CM_IVAHD_IVAHD_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
+ +  * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
+ +  * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
+ +  * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
+ +  * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
+ +  * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL,
+ +  * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
+ +  * CM_TESLA_TESLA_CLKCTRL
+ +  */
+ + #define OMAP4430_STBYST_SHIFT					18
+ + #define OMAP4430_STBYST_MASK					(1 << 18)
+ + 
+ + /*
+ +  * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY,
+ +  * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER,
+ +  * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB
+ +  */
+ + #define OMAP4430_ST_DPLL_CLK_SHIFT				0
+ + #define OMAP4430_ST_DPLL_CLK_MASK				(1 << 0)
+ + 
+ + /* Used by CM_CLKDCOLDO_DPLL_USB */
+ + #define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT			9
+ + #define OMAP4430_ST_DPLL_CLKDCOLDO_MASK				(1 << 9)
+ + 
+ + /*
+ +  * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
+ +  * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
+ +  */
+ + #define OMAP4430_ST_DPLL_CLKOUT_SHIFT				9
+ + #define OMAP4430_ST_DPLL_CLKOUT_MASK				(1 << 9)
+ + 
+ + /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
+ + #define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT			9
+ + #define OMAP4430_ST_DPLL_CLKOUTHIF_MASK				(1 << 9)
+ + 
+ + /* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
+ + #define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT				11
+ + #define OMAP4430_ST_DPLL_CLKOUTX2_MASK				(1 << 11)
+ + 
+ + /*
+ +  * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
+ +  * CM_DIV_M4_DPLL_PER
+ +  */
+ + #define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT			9
+ + #define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK			(1 << 9)
+ + 
+ + /*
+ +  * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
+ +  * CM_DIV_M5_DPLL_PER
+ +  */
+ + #define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT			9
+ + #define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK			(1 << 9)
+ + 
+ + /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
+ + #define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT			9
+ + #define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK			(1 << 9)
+ + 
+ + /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
+ + #define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT			9
+ + #define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK			(1 << 9)
+ + 
+ + /*
+ +  * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY,
+ +  * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER,
+ +  * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB
+ +  */
+ + #define OMAP4430_ST_MN_BYPASS_SHIFT				8
+ + #define OMAP4430_ST_MN_BYPASS_MASK				(1 << 8)
+ + 
+ + /* Used by CM_SYS_CLKSEL */
+ + #define OMAP4430_SYS_CLKSEL_SHIFT				0
+ + #define OMAP4430_SYS_CLKSEL_MASK				(0x7 << 0)
+ + 
+ + /* Used by CM_L4CFG_DYNAMICDEP */
+ + #define OMAP4430_TESLA_DYNDEP_SHIFT				1
+ + #define OMAP4430_TESLA_DYNDEP_MASK				(1 << 1)
+ + 
+ + /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
+ + #define OMAP4430_TESLA_STATDEP_SHIFT				1
+ + #define OMAP4430_TESLA_STATDEP_MASK				(1 << 1)
+ + 
+ + /*
+ +  * Used by CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP,
+ +  * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
+ +  * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
+ +  */
+ + #define OMAP4430_WINDOWSIZE_SHIFT				24
+ + #define OMAP4430_WINDOWSIZE_MASK				(0xf << 24)
+ + 
+ + /* Used by REVISION_CM1, REVISION_CM2 */
+ + #define OMAP4430_X_MAJOR_SHIFT					8
+ + #define OMAP4430_X_MAJOR_MASK					(0x7 << 8)
+ + 
+ + /* Used by REVISION_CM1, REVISION_CM2 */
+ + #define OMAP4430_Y_MINOR_SHIFT					0
+ + #define OMAP4430_Y_MINOR_MASK					(0x3f << 0)
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/common.c linux-3.2.1/arch/arm/mach-ckb_3352/common.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/common.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/common.c	2014-11-26 18:43:10.160806000 +0900
+ ***************
+ *** 0 ****
+ --- 1,325 ----
+ + /*
+ +  * linux/arch/arm/mach-omap2/common.c
+ +  *
+ +  * Code common to all OMAP2+ machines.
+ +  *
+ +  * Copyright (C) 2009 Texas Instruments
+ +  * Copyright (C) 2010 Nokia Corporation
+ +  * Tony Lindgren <tony@atomide.com>
+ +  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + #include <linux/kernel.h>
+ + #include <linux/init.h>
+ + #include <linux/clk.h>
+ + #include <linux/io.h>
+ + #include <linux/module.h>
+ + 
+ + #include <asm/cputype.h>
+ + 
+ + #include <plat/cpu.h>
+ + 
+ + #include "common.h"
+ + #include <plat/board.h>
+ + #include <plat/mux.h>
+ + 
+ + #include <plat/clock.h>
+ + 
+ + #include "sdrc.h"
+ + #include "control.h"
+ + 
+ + /* Global address base setup code */
+ + 
+ + 
+ + static void __init __omap2_set_globals(struct omap_globals *omap2_globals)
+ + {
+ + 	omap2_set_globals_tap(omap2_globals);
+ + 	omap2_set_globals_sdrc(omap2_globals);
+ + 	omap2_set_globals_control(omap2_globals);
+ + 	omap2_set_globals_prcm(omap2_globals);
+ + }
+ + 
+ + #define AM33XX_TAP_BASE		(AM33XX_CTRL_BASE + \
+ + 				TI81XX_CONTROL_DEVICE_ID - 0x204)
+ + 
+ + static struct omap_globals am33xx_globals = {
+ + 	.class  = AM335X_CLASS,
+ + 	.tap    = AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE),
+ + 	.ctrl   = AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
+ + 	.prm    = AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE),
+ + 	.cm     = AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE),
+ + };
+ + 
+ + void __init omap2_set_globals_am33xx(void)
+ + {
+ + 	__omap2_set_globals(&am33xx_globals);
+ + }
+ + 
+ + void __init am33xx_map_io(void)
+ + {
+ + 	omapam33xx_map_common_io();
+ + }
+ + 
+ + 
+ + static unsigned int omap_revision;
+ + static const char *cpu_rev;
+ + u32 omap_features;
+ + 
+ + unsigned int omap_rev(void)
+ + {
+ + 	return omap_revision;
+ + }
+ + EXPORT_SYMBOL(omap_rev);
+ + 
+ + int omap_type(void)
+ + {
+ + 	u32 val = 0;
+ + 
+ + 	val = omap_ctrl_readl(AM33XX_CONTROL_STATUS_OFF);
+ + 	val &= OMAP2_DEVICETYPE_MASK;
+ + 	val >>= 8;
+ + 
+ + out:
+ + 	return val;
+ + }
+ + EXPORT_SYMBOL(omap_type);
+ + 
+ + 
+ + /*----------------------------------------------------------------------------*/
+ + 
+ + #define OMAP_TAP_IDCODE		0x0204
+ + #define OMAP_TAP_DIE_ID_0	0x0218
+ + #define OMAP_TAP_DIE_ID_1	0x021C
+ + #define OMAP_TAP_DIE_ID_2	0x0220
+ + #define OMAP_TAP_DIE_ID_3	0x0224
+ + 
+ + #define OMAP_TAP_DIE_ID_44XX_0	0x0200
+ + #define OMAP_TAP_DIE_ID_44XX_1	0x0208
+ + #define OMAP_TAP_DIE_ID_44XX_2	0x020c
+ + #define OMAP_TAP_DIE_ID_44XX_3	0x0210
+ + 
+ + #define read_tap_reg(reg)	__raw_readl(tap_base  + (reg))
+ + 
+ + static void __iomem *tap_base;
+ + static u16 tap_prod_id;
+ + 
+ + 
+ + #define OMAP3_SHOW_FEATURE(feat)		\
+ + 	if (omap3_has_ ##feat())		\
+ + 		printk(#feat" ");
+ + 
+ + static void __init omap3_cpuinfo(void)
+ + {
+ + 	const char *cpu_name;
+ + 
+ + 	/*
+ + 	 * OMAP3430 and OMAP3530 are assumed to be same.
+ + 	 *
+ + 	 * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
+ + 	 * on available features. Upon detection, update the CPU id
+ + 	 * and CPU class bits.
+ + 	 */
+ + 	cpu_name =  "AM335X";
+ + 	
+ + 	/* Print verbose information */
+ + 	pr_info("%s ES%s (", cpu_name, cpu_rev);
+ + 
+ + 	OMAP3_SHOW_FEATURE(l2cache);
+ + 	OMAP3_SHOW_FEATURE(iva);
+ + 	OMAP3_SHOW_FEATURE(sgx);
+ + 	OMAP3_SHOW_FEATURE(neon);
+ + 	OMAP3_SHOW_FEATURE(isp);
+ + 	OMAP3_SHOW_FEATURE(192mhz_clk);
+ + 
+ + 	printk(")\n");
+ + }
+ + 
+ + #define OMAP3_CHECK_FEATURE(status,feat)				\
+ + 	if (((status & OMAP3_ ##feat## _MASK) 				\
+ + 		>> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { 	\
+ + 		omap_features |= OMAP3_HAS_ ##feat;			\
+ + 	}
+ + 
+ + void __init am33xx_check_features(void)
+ + {
+ + 	u32 status;
+ + 
+ + 	omap_features = OMAP3_HAS_NEON;
+ + 
+ + 	status = omap_ctrl_readl(AM33XX_DEV_FEATURE);
+ + 	if (status & AM33XX_SGX_MASK)
+ + 		omap_features |= OMAP3_HAS_SGX;
+ + 
+ + 	omap3_cpuinfo();
+ + }
+ + 
+ + void __init omap3xxx_check_revision(void)
+ + {
+ + 	u32 cpuid, idcode;
+ + 	u16 hawkeye;
+ + 	u8 rev;
+ + 
+ + 	/*
+ + 	 * We cannot access revision registers on ES1.0.
+ + 	 * If the processor type is Cortex-A8 and the revision is 0x0
+ + 	 * it means its Cortex r0p0 which is 3430 ES1.0.
+ + 	 */
+ + 	cpuid = read_cpuid(CPUID_ID);
+ + 	if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
+ + 		omap_revision = OMAP3430_REV_ES1_0;
+ + 		cpu_rev = "1.0";
+ + 		return;
+ + 	}
+ + 
+ + 	/*
+ + 	 * Detection for 34xx ES2.0 and above can be done with just
+ + 	 * hawkeye and rev. See TRM 1.5.2 Device Identification.
+ + 	 * Note that rev does not map directly to our defined processor
+ + 	 * revision numbers as ES1.0 uses value 0.
+ + 	 */
+ + 	idcode = read_tap_reg(OMAP_TAP_IDCODE);
+ + 	hawkeye = (idcode >> 12) & 0xffff;
+ + 	rev = (idcode >> 28) & 0xff;
+ + 
+ + 	switch (hawkeye) {
+ + 	case 0xb7ae:
+ + 		/* Handle 34xx/35xx devices */
+ + 		switch (rev) {
+ + 		case 0: /* Take care of early samples */
+ + 		case 1:
+ + 			omap_revision = OMAP3430_REV_ES2_0;
+ + 			cpu_rev = "2.0";
+ + 			break;
+ + 		case 2:
+ + 			omap_revision = OMAP3430_REV_ES2_1;
+ + 			cpu_rev = "2.1";
+ + 			break;
+ + 		case 3:
+ + 			omap_revision = OMAP3430_REV_ES3_0;
+ + 			cpu_rev = "3.0";
+ + 			break;
+ + 		case 4:
+ + 			omap_revision = OMAP3430_REV_ES3_1;
+ + 			cpu_rev = "3.1";
+ + 			break;
+ + 		case 7:
+ + 		/* FALLTHROUGH */
+ + 		default:
+ + 			/* Use the latest known revision as default */
+ + 			omap_revision = OMAP3430_REV_ES3_1_2;
+ + 			cpu_rev = "3.1.2";
+ + 		}
+ + 		break;
+ + 	case 0xb868:
+ + 		/*
+ + 		 * Handle OMAP/AM 3505/3517 devices
+ + 		 *
+ + 		 * Set the device to be OMAP3517 here. Actual device
+ + 		 * is identified later based on the features.
+ + 		 */
+ + 		switch (rev) {
+ + 		case 0:
+ + 			omap_revision = OMAP3517_REV_ES1_0;
+ + 			cpu_rev = "1.0";
+ + 			break;
+ + 		case 1:
+ + 		/* FALLTHROUGH */
+ + 		default:
+ + 			omap_revision = OMAP3517_REV_ES1_1;
+ + 			cpu_rev = "1.1";
+ + 		}
+ + 		break;
+ + 	case 0xb891:
+ + 		/* Handle 36xx devices */
+ + 
+ + 		switch(rev) {
+ + 		case 0: /* Take care of early samples */
+ + 			omap_revision = OMAP3630_REV_ES1_0;
+ + 			cpu_rev = "1.0";
+ + 			break;
+ + 		case 1:
+ + 			omap_revision = OMAP3630_REV_ES1_1;
+ + 			cpu_rev = "1.1";
+ + 			break;
+ + 		case 2:
+ + 		/* FALLTHROUGH */
+ + 		default:
+ + 			omap_revision = OMAP3630_REV_ES1_2;
+ + 			cpu_rev = "1.2";
+ + 		}
+ + 		break;
+ + 	case 0xb81e:
+ + 		switch (rev) {
+ + 		case 0:
+ + 			omap_revision = TI8168_REV_ES1_0;
+ + 			cpu_rev = "1.0";
+ + 			break;
+ + 		case 1:
+ + 		/* FALLTHROUGH */
+ + 		default:
+ + 			omap_revision = TI8168_REV_ES1_1;
+ + 			cpu_rev = "1.1";
+ + 			break;
+ + 		}
+ + 		break;
+ + 	case 0xb944:
+ + 		switch (rev) {
+ + 		case 0:
+ + 			omap_revision = AM335X_REV_ES1_0;
+ + 			cpu_rev = "1.0";
+ + 			break;
+ + 		case 1:
+ + 			omap_revision = AM335X_REV_ES2_0;
+ + 			cpu_rev = "2.0";
+ + 			break;
+ + 		case 2:
+ + 		default: /* fallback */
+ + 			omap_revision = AM335X_REV_ES2_1;
+ + 			cpu_rev = "2.1";
+ + 			break;
+ + 		}
+ + 		break;
+ + 	case 0xb8f2:
+ + 		switch (rev) {
+ + 		case 0:
+ + 		/* FALLTHROUGH */
+ + 		case 1:
+ + 			omap_revision = TI8148_REV_ES1_0;
+ + 			cpu_rev = "1.0";
+ + 			break;
+ + 		case 2:
+ + 			omap_revision = TI8148_REV_ES2_0;
+ + 			cpu_rev = "2.0";
+ + 			break;
+ + 		case 3:
+ + 		/* FALLTHROUGH */
+ + 		default:
+ + 			omap_revision = TI8148_REV_ES2_1;
+ + 			cpu_rev = "2.1";
+ + 			break;
+ + 		}
+ + 		break;
+ + 	default:
+ + 		/* Unknown default to latest silicon rev as default */
+ + 		omap_revision = OMAP3630_REV_ES1_2;
+ + 		cpu_rev = "1.2";
+ + 		pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
+ + 	}
+ + }
+ + 
+ + /*
+ +  * Set up things for map_io and processor detection later on. Gets called
+ +  * pretty much first thing from board init. For multi-omap, this gets
+ +  * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
+ +  * detect the exact revision later on in omap2_detect_revision() once map_io
+ +  * is done.
+ +  */
+ + void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
+ + {
+ + 	omap_revision = omap2_globals->class;
+ + 	tap_base = omap2_globals->tap;
+ + 	tap_prod_id = 0x0208;
+ + }
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/common.h linux-3.2.1/arch/arm/mach-ckb_3352/common.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/common.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/common.h	2014-11-25 13:19:14.971039560 +0900
+ ***************
+ *** 0 ****
+ --- 1,186 ----
+ + /*
+ +  * Header for code common to all OMAP2+ machines.
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify it
+ +  * under the terms of the GNU General Public License as published by the
+ +  * Free Software Foundation; either version 2 of the License, or (at your
+ +  * option) any later version.
+ +  *
+ +  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ +  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ +  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ +  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ +  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ +  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ +  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ +  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ +  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ +  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ +  *
+ +  * You should have received a copy of the  GNU General Public License along
+ +  * with this program; if not, write  to the Free Software Foundation, Inc.,
+ +  * 675 Mass Ave, Cambridge, MA 02139, USA.
+ +  */
+ + 
+ + #ifndef __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
+ + #define __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
+ + #ifndef __ASSEMBLER__
+ + 
+ + #include <linux/delay.h>
+ + #include <plat/common.h>
+ + #include <asm/proc-fns.h>
+ + 
+ + #ifdef CONFIG_SOC_OMAPAM33XX
+ + extern void omapam33xx_map_common_io(void);
+ + #else
+ + static inline void omapam33xx_map_common_io(void)
+ + {
+ + }
+ + #endif
+ + 
+ + 
+ + extern void omap2_init_common_infrastructure(void);
+ + 
+ + extern struct sys_timer omap2_timer;
+ + extern struct sys_timer omap3_timer;
+ + extern struct sys_timer omap3_secure_timer;
+ + extern struct sys_timer omap3_am33xx_timer;
+ + extern struct sys_timer omap4_timer;
+ + 
+ + void omap2420_init_early(void);
+ + void omap2430_init_early(void);
+ + void omap3430_init_early(void);
+ + void omap35xx_init_early(void);
+ + void omap3630_init_early(void);
+ + void omap3_init_early(void);	/* Do not use this one */
+ + void am35xx_init_early(void);
+ + void am33xx_init_early(void);
+ + void omap4430_init_early(void);
+ + 
+ + /*
+ +  * IO bases for various OMAP processors
+ +  * Except the tap base, rest all the io bases
+ +  * listed are physical addresses.
+ +  */
+ + struct omap_globals {
+ + 	u32		class;		/* OMAP class to detect */
+ + 	void __iomem	*tap;		/* Control module ID code */
+ + 	void __iomem	*sdrc;           /* SDRAM Controller */
+ + 	void __iomem	*sms;            /* SDRAM Memory Scheduler */
+ + 	void __iomem	*ctrl;           /* System Control Module */
+ + 	void __iomem	*ctrl_pad;	/* PAD Control Module */
+ + 	void __iomem	*prm;            /* Power and Reset Management */
+ + 	void __iomem	*cm;             /* Clock Management */
+ + 	void __iomem	*cm2;
+ + };
+ + 
+ + void omap2_set_globals_am33xx(void);
+ + 
+ + /* These get called from omap2_set_globals_xxxx(), do not call these */
+ + void omap2_set_globals_tap(struct omap_globals *);
+ + void omap2_set_globals_sdrc(struct omap_globals *);
+ + void omap2_set_globals_control(struct omap_globals *);
+ + void omap2_set_globals_prcm(struct omap_globals *);
+ + 
+ + void am33xx_map_io(void);
+ + void omap4_map_io(void);
+ + void ti81xx_map_io(void);
+ + 
+ + /**
+ +  * omap_test_timeout - busy-loop, testing a condition
+ +  * @cond: condition to test until it evaluates to true
+ +  * @timeout: maximum number of microseconds in the timeout
+ +  * @index: loop index (integer)
+ +  *
+ +  * Loop waiting for @cond to become true or until at least @timeout
+ +  * microseconds have passed.  To use, define some integer @index in the
+ +  * calling code.  After running, if @index == @timeout, then the loop has
+ +  * timed out.
+ +  */
+ + #define omap_test_timeout(cond, timeout, index)			\
+ + ({								\
+ + 	for (index = 0; index < timeout; index++) {		\
+ + 		if (cond)					\
+ + 			break;					\
+ + 		udelay(1);					\
+ + 	}							\
+ + })
+ + 
+ + extern struct device *omap2_get_mpuss_device(void);
+ + extern struct device *omap2_get_iva_device(void);
+ + extern struct device *omap2_get_l3_device(void);
+ + extern struct device *omap4_get_dsp_device(void);
+ + 
+ + void omap3_init_irq(void);
+ + void ti81xx_init_irq(void);
+ + extern int omap_irq_pending(void);
+ + void omap3_intc_suspend(void);
+ + void omap3_intc_handle_irq(struct pt_regs *regs);
+ + 
+ + #ifdef CONFIG_CACHE_L2X0
+ + extern void __iomem *omap4_get_l2cache_base(void);
+ + #endif
+ + 
+ + #ifdef CONFIG_SMP
+ + extern void __iomem *omap4_get_scu_base(void);
+ + #else
+ + static inline void __iomem *omap4_get_scu_base(void)
+ + {
+ + 	return NULL;
+ + }
+ + #endif
+ + 
+ + extern void __init gic_init_irq(void);
+ + extern void omap_smc1(u32 fn, u32 arg);
+ + extern void __iomem *omap4_get_sar_ram_base(void);
+ + extern void omap_do_wfi(void);
+ + 
+ + #ifdef CONFIG_SMP
+ + /* Needed for secondary core boot */
+ + extern void omap_secondary_startup(void);
+ + extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
+ + extern void omap_auxcoreboot_addr(u32 cpu_addr);
+ + extern u32 omap_read_auxcoreboot0(void);
+ + #endif
+ + 
+ + #if defined(CONFIG_SMP) && defined(CONFIG_PM)
+ + extern int omap4_mpuss_init(void);
+ + extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state);
+ + extern int omap4_finish_suspend(unsigned long cpu_state);
+ + extern void omap4_cpu_resume(void);
+ + extern int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state);
+ + extern u32 omap4_mpuss_read_prev_context_state(void);
+ + #else
+ + static inline int omap4_enter_lowpower(unsigned int cpu,
+ + 					unsigned int power_state)
+ + {
+ + 	cpu_do_idle();
+ + 	return 0;
+ + }
+ + 
+ + static inline int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
+ + {
+ + 	cpu_do_idle();
+ + 	return 0;
+ + }
+ + 
+ + static inline int omap4_mpuss_init(void)
+ + {
+ + 	return 0;
+ + }
+ + 
+ + static inline int omap4_finish_suspend(unsigned long cpu_state)
+ + {
+ + 	return 0;
+ + }
+ + 
+ + static inline void omap4_cpu_resume(void)
+ + {}
+ + 
+ + static inline u32 omap4_mpuss_read_prev_context_state(void)
+ + {
+ + 	return 0;
+ + }
+ + #endif
+ + #endif /* __ASSEMBLER__ */
+ + #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/control.c linux-3.2.1/arch/arm/mach-ckb_3352/control.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/control.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/control.c	2014-11-25 13:19:14.971039560 +0900
+ ***************
+ *** 0 ****
+ --- 1,212 ----
+ + /*
+ +  * OMAP2/3 System Control Module register access
+ +  *
+ +  * Copyright (C) 2007 Texas Instruments, Inc.
+ +  * Copyright (C) 2007 Nokia Corporation
+ +  *
+ +  * Written by Paul Walmsley
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + #undef DEBUG
+ + 
+ + #include <linux/kernel.h>
+ + #include <linux/module.h>
+ + #include <linux/io.h>
+ + 
+ + #include "common.h"
+ + #include <plat/sdrc.h>
+ + 
+ + #include "cm-regbits-34xx.h"
+ + #include "prm-regbits-34xx.h"
+ + #include "prm2xxx_3xxx.h"
+ + #include "cm2xxx_3xxx.h"
+ + #include "sdrc.h"
+ + #include "pm.h"
+ + #include "control.h"
+ + 
+ + /* Used by omap3_ctrl_save_padconf() */
+ + #define START_PADCONF_SAVE		0x2
+ + #define PADCONF_SAVE_DONE		0x1
+ + 
+ + static void __iomem *omap2_ctrl_base;
+ + static void __iomem *omap4_ctrl_pad_base;
+ + 
+ + #if defined(CONFIG_PM)
+ + struct omap3_scratchpad {
+ + 	u32 boot_config_ptr;
+ + 	u32 public_restore_ptr;
+ + 	u32 secure_ram_restore_ptr;
+ + 	u32 sdrc_module_semaphore;
+ + 	u32 prcm_block_offset;
+ + 	u32 sdrc_block_offset;
+ + };
+ + 
+ + struct omap3_scratchpad_prcm_block {
+ + 	u32 prm_clksrc_ctrl;
+ + 	u32 prm_clksel;
+ + 	u32 cm_clksel_core;
+ + 	u32 cm_clksel_wkup;
+ + 	u32 cm_clken_pll;
+ + 	u32 cm_autoidle_pll;
+ + 	u32 cm_clksel1_pll;
+ + 	u32 cm_clksel2_pll;
+ + 	u32 cm_clksel3_pll;
+ + 	u32 cm_clken_pll_mpu;
+ + 	u32 cm_autoidle_pll_mpu;
+ + 	u32 cm_clksel1_pll_mpu;
+ + 	u32 cm_clksel2_pll_mpu;
+ + 	u32 prcm_block_size;
+ + };
+ + 
+ + struct omap3_scratchpad_sdrc_block {
+ + 	u16 sysconfig;
+ + 	u16 cs_cfg;
+ + 	u16 sharing;
+ + 	u16 err_type;
+ + 	u32 dll_a_ctrl;
+ + 	u32 dll_b_ctrl;
+ + 	u32 power;
+ + 	u32 cs_0;
+ + 	u32 mcfg_0;
+ + 	u16 mr_0;
+ + 	u16 emr_1_0;
+ + 	u16 emr_2_0;
+ + 	u16 emr_3_0;
+ + 	u32 actim_ctrla_0;
+ + 	u32 actim_ctrlb_0;
+ + 	u32 rfr_ctrl_0;
+ + 	u32 cs_1;
+ + 	u32 mcfg_1;
+ + 	u16 mr_1;
+ + 	u16 emr_1_1;
+ + 	u16 emr_2_1;
+ + 	u16 emr_3_1;
+ + 	u32 actim_ctrla_1;
+ + 	u32 actim_ctrlb_1;
+ + 	u32 rfr_ctrl_1;
+ + 	u16 dcdl_1_ctrl;
+ + 	u16 dcdl_2_ctrl;
+ + 	u32 flags;
+ + 	u32 block_size;
+ + };
+ + 
+ + void *omap3_secure_ram_storage;
+ + 
+ + /*
+ +  * This is used to store ARM registers in SDRAM before attempting
+ +  * an MPU OFF. The save and restore happens from the SRAM sleep code.
+ +  * The address is stored in scratchpad, so that it can be used
+ +  * during the restore path.
+ +  */
+ + u32 omap3_arm_context[128];
+ + 
+ + struct omap3_control_regs {
+ + 	u32 sysconfig;
+ + 	u32 devconf0;
+ + 	u32 mem_dftrw0;
+ + 	u32 mem_dftrw1;
+ + 	u32 msuspendmux_0;
+ + 	u32 msuspendmux_1;
+ + 	u32 msuspendmux_2;
+ + 	u32 msuspendmux_3;
+ + 	u32 msuspendmux_4;
+ + 	u32 msuspendmux_5;
+ + 	u32 sec_ctrl;
+ + 	u32 devconf1;
+ + 	u32 csirxfe;
+ + 	u32 iva2_bootaddr;
+ + 	u32 iva2_bootmod;
+ + 	u32 debobs_0;
+ + 	u32 debobs_1;
+ + 	u32 debobs_2;
+ + 	u32 debobs_3;
+ + 	u32 debobs_4;
+ + 	u32 debobs_5;
+ + 	u32 debobs_6;
+ + 	u32 debobs_7;
+ + 	u32 debobs_8;
+ + 	u32 prog_io0;
+ + 	u32 prog_io1;
+ + 	u32 dss_dpll_spreading;
+ + 	u32 core_dpll_spreading;
+ + 	u32 per_dpll_spreading;
+ + 	u32 usbhost_dpll_spreading;
+ + 	u32 pbias_lite;
+ + 	u32 temp_sensor;
+ + 	u32 sramldo4;
+ + 	u32 sramldo5;
+ + 	u32 csi;
+ + 	u32 padconf_sys_nirq;
+ + };
+ + 
+ + static struct omap3_control_regs control_context;
+ + #endif /* CONFIG_PM */
+ + 
+ + #define OMAP_CTRL_REGADDR(reg)		(omap2_ctrl_base + (reg))
+ + #define OMAP4_CTRL_PAD_REGADDR(reg)	(omap4_ctrl_pad_base + (reg))
+ + 
+ + void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
+ + {
+ + 	if (omap2_globals->ctrl)
+ + 		omap2_ctrl_base = omap2_globals->ctrl;
+ + 
+ + 	if (omap2_globals->ctrl_pad)
+ + 		omap4_ctrl_pad_base = omap2_globals->ctrl_pad;
+ + }
+ + 
+ + void __iomem *omap_ctrl_base_get(void)
+ + {
+ + 	return omap2_ctrl_base;
+ + }
+ + 
+ + u8 omap_ctrl_readb(u16 offset)
+ + {
+ + 	return __raw_readb(OMAP_CTRL_REGADDR(offset));
+ + }
+ + 
+ + u16 omap_ctrl_readw(u16 offset)
+ + {
+ + 	return __raw_readw(OMAP_CTRL_REGADDR(offset));
+ + }
+ + 
+ + u32 omap_ctrl_readl(u16 offset)
+ + {
+ + 	return __raw_readl(OMAP_CTRL_REGADDR(offset));
+ + }
+ + 
+ + void omap_ctrl_writeb(u8 val, u16 offset)
+ + {
+ + 	__raw_writeb(val, OMAP_CTRL_REGADDR(offset));
+ + }
+ + 
+ + void omap_ctrl_writew(u16 val, u16 offset)
+ + {
+ + 	__raw_writew(val, OMAP_CTRL_REGADDR(offset));
+ + }
+ + 
+ + void omap_ctrl_writel(u32 val, u16 offset)
+ + {
+ + 	__raw_writel(val, OMAP_CTRL_REGADDR(offset));
+ + }
+ + EXPORT_SYMBOL_GPL(omap_ctrl_writel);
+ + 
+ + /*
+ +  * On OMAP4 control pad are not addressable from control
+ +  * core base. So the common omap_ctrl_read/write APIs breaks
+ +  * Hence export separate APIs to manage the omap4 pad control
+ +  * registers. This APIs will work only for OMAP4
+ +  */
+ + 
+ + u32 omap4_ctrl_pad_readl(u16 offset)
+ + {
+ + 	return __raw_readl(OMAP4_CTRL_PAD_REGADDR(offset));
+ + }
+ + 
+ + void omap4_ctrl_pad_writel(u32 val, u16 offset)
+ + {
+ + 	__raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset));
+ + }
+ + 
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/control.h linux-3.2.1/arch/arm/mach-ckb_3352/control.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/control.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/control.h	2014-11-25 13:19:14.971039560 +0900
+ ***************
+ *** 0 ****
+ --- 1,432 ----
+ + /*
+ +  * arch/arm/mach-ckb_3352/control.h
+ +  *
+ +  * CKB 3352 System Control Module definitions
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation.
+ +  */
+ + 
+ + #ifndef __ARCH_ARM_MACH_CKB_3352_CONTROL_H
+ + #define __ARCH_ARM_MACH_CKB_3352_CONTROL_H
+ + 
+ + #include <mach/io.h>
+ + 
+ + #ifndef __ASSEMBLY__
+ + #define OMAP343X_CTRL_REGADDR(reg)					\
+ + 		OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
+ + #define AM33XX_CTRL_REGADDR(reg)					\
+ + 		AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
+ + #else
+ + #define OMAP343X_CTRL_REGADDR(reg)					\
+ + 		OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
+ + #define AM33XX_CTRL_REGADDR(reg)					\
+ + 		AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
+ + #endif /* __ASSEMBLY__ */
+ + 
+ + /*
+ +  * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for
+ +  * OMAP24XX and OMAP34XX.
+ +  */
+ + 
+ + /* Control submodule offsets */
+ + 
+ + #define OMAP2_CONTROL_INTERFACE		0x000
+ + #define OMAP2_CONTROL_PADCONFS		0x030
+ + #define OMAP2_CONTROL_GENERAL		0x270
+ + #define OMAP343X_CONTROL_MEM_WKUP	0x600
+ + #define OMAP343X_CONTROL_PADCONFS_WKUP	0xa00
+ + #define OMAP343X_CONTROL_GENERAL_WKUP	0xa60
+ + 
+ + /* TI81XX spefic control submodules */
+ + #define TI81XX_CONTROL_DEVCONF		0x600
+ + 
+ + /* TI81XX CONTROL_DEVCONF register offsets */
+ + #define TI81XX_CONTROL_MAC_ID0_LO       (TI81XX_CONTROL_DEVCONF + 0x030)
+ + #define TI81XX_CONTROL_MAC_ID0_HI       (TI81XX_CONTROL_DEVCONF + 0x034)
+ + #define TI81XX_CONTROL_MAC_ID1_LO       (TI81XX_CONTROL_DEVCONF + 0x038)
+ + #define TI81XX_CONTROL_MAC_ID1_HI       (TI81XX_CONTROL_DEVCONF + 0x03c)
+ + 
+ + /* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
+ + 
+ + #define OMAP2_CONTROL_SYSCONFIG		(OMAP2_CONTROL_INTERFACE + 0x10)
+ + 
+ + /* CONTROL_GENERAL register offsets common to OMAP2 & 3 */
+ + #define OMAP2_CONTROL_DEVCONF0		(OMAP2_CONTROL_GENERAL + 0x0004)
+ + #define OMAP2_CONTROL_MSUSPENDMUX_0	(OMAP2_CONTROL_GENERAL + 0x0020)
+ + #define OMAP2_CONTROL_MSUSPENDMUX_1	(OMAP2_CONTROL_GENERAL + 0x0024)
+ + #define OMAP2_CONTROL_MSUSPENDMUX_2	(OMAP2_CONTROL_GENERAL + 0x0028)
+ + #define OMAP2_CONTROL_MSUSPENDMUX_3	(OMAP2_CONTROL_GENERAL + 0x002c)
+ + #define OMAP2_CONTROL_MSUSPENDMUX_4	(OMAP2_CONTROL_GENERAL + 0x0030)
+ + #define OMAP2_CONTROL_MSUSPENDMUX_5	(OMAP2_CONTROL_GENERAL + 0x0034)
+ + #define OMAP2_CONTROL_SEC_CTRL		(OMAP2_CONTROL_GENERAL + 0x0040)
+ + #define OMAP2_CONTROL_RPUB_KEY_H_0	(OMAP2_CONTROL_GENERAL + 0x0090)
+ + #define OMAP2_CONTROL_RPUB_KEY_H_1	(OMAP2_CONTROL_GENERAL + 0x0094)
+ + #define OMAP2_CONTROL_RPUB_KEY_H_2	(OMAP2_CONTROL_GENERAL + 0x0098)
+ + #define OMAP2_CONTROL_RPUB_KEY_H_3	(OMAP2_CONTROL_GENERAL + 0x009c)
+ + 
+ + /* 242x-only CONTROL_GENERAL register offsets */
+ + #define OMAP242X_CONTROL_DEVCONF	OMAP2_CONTROL_DEVCONF0 /* match TRM */
+ + #define OMAP242X_CONTROL_OCM_RAM_PERM	(OMAP2_CONTROL_GENERAL + 0x0068)
+ + 
+ + /* 243x-only CONTROL_GENERAL register offsets */
+ + /* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */
+ + #define OMAP243X_CONTROL_DEVCONF1	(OMAP2_CONTROL_GENERAL + 0x0078)
+ + #define OMAP243X_CONTROL_CSIRXFE	(OMAP2_CONTROL_GENERAL + 0x007c)
+ + #define OMAP243X_CONTROL_IVA2_BOOTADDR	(OMAP2_CONTROL_GENERAL + 0x0190)
+ + #define OMAP243X_CONTROL_IVA2_BOOTMOD	(OMAP2_CONTROL_GENERAL + 0x0194)
+ + #define OMAP243X_CONTROL_IVA2_GEMCFG	(OMAP2_CONTROL_GENERAL + 0x0198)
+ + #define OMAP243X_CONTROL_PBIAS_LITE	(OMAP2_CONTROL_GENERAL + 0x0230)
+ + 
+ + /* 24xx-only CONTROL_GENERAL register offsets */
+ + #define OMAP24XX_CONTROL_DEBOBS		(OMAP2_CONTROL_GENERAL + 0x0000)
+ + #define OMAP24XX_CONTROL_EMU_SUPPORT	(OMAP2_CONTROL_GENERAL + 0x0008)
+ + #define OMAP24XX_CONTROL_SEC_TEST	(OMAP2_CONTROL_GENERAL + 0x0044)
+ + #define OMAP24XX_CONTROL_PSA_CTRL	(OMAP2_CONTROL_GENERAL + 0x0048)
+ + #define OMAP24XX_CONTROL_PSA_CMD	(OMAP2_CONTROL_GENERAL + 0x004c)
+ + #define OMAP24XX_CONTROL_PSA_VALUE	(OMAP2_CONTROL_GENERAL + 0x0050)
+ + #define OMAP24XX_CONTROL_SEC_EMU	(OMAP2_CONTROL_GENERAL + 0x0060)
+ + #define OMAP24XX_CONTROL_SEC_TAP	(OMAP2_CONTROL_GENERAL + 0x0064)
+ + #define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD	(OMAP2_CONTROL_GENERAL + 0x006c)
+ + #define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD	(OMAP2_CONTROL_GENERAL + 0x0070)
+ + #define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD	(OMAP2_CONTROL_GENERAL + 0x0074)
+ + #define OMAP24XX_CONTROL_SEC_STATUS		(OMAP2_CONTROL_GENERAL + 0x0080)
+ + #define OMAP24XX_CONTROL_SEC_ERR_STATUS		(OMAP2_CONTROL_GENERAL + 0x0084)
+ + #define OMAP24XX_CONTROL_STATUS			(OMAP2_CONTROL_GENERAL + 0x0088)
+ + #define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS	(OMAP2_CONTROL_GENERAL + 0x008c)
+ + #define OMAP24XX_CONTROL_RAND_KEY_0	(OMAP2_CONTROL_GENERAL + 0x00a0)
+ + #define OMAP24XX_CONTROL_RAND_KEY_1	(OMAP2_CONTROL_GENERAL + 0x00a4)
+ + #define OMAP24XX_CONTROL_RAND_KEY_2	(OMAP2_CONTROL_GENERAL + 0x00a8)
+ + #define OMAP24XX_CONTROL_RAND_KEY_3	(OMAP2_CONTROL_GENERAL + 0x00ac)
+ + #define OMAP24XX_CONTROL_CUST_KEY_0	(OMAP2_CONTROL_GENERAL + 0x00b0)
+ + #define OMAP24XX_CONTROL_CUST_KEY_1	(OMAP2_CONTROL_GENERAL + 0x00b4)
+ + #define OMAP24XX_CONTROL_TEST_KEY_0	(OMAP2_CONTROL_GENERAL + 0x00c0)
+ + #define OMAP24XX_CONTROL_TEST_KEY_1	(OMAP2_CONTROL_GENERAL + 0x00c4)
+ + #define OMAP24XX_CONTROL_TEST_KEY_2	(OMAP2_CONTROL_GENERAL + 0x00c8)
+ + #define OMAP24XX_CONTROL_TEST_KEY_3	(OMAP2_CONTROL_GENERAL + 0x00cc)
+ + #define OMAP24XX_CONTROL_TEST_KEY_4	(OMAP2_CONTROL_GENERAL + 0x00d0)
+ + #define OMAP24XX_CONTROL_TEST_KEY_5	(OMAP2_CONTROL_GENERAL + 0x00d4)
+ + #define OMAP24XX_CONTROL_TEST_KEY_6	(OMAP2_CONTROL_GENERAL + 0x00d8)
+ + #define OMAP24XX_CONTROL_TEST_KEY_7	(OMAP2_CONTROL_GENERAL + 0x00dc)
+ + #define OMAP24XX_CONTROL_TEST_KEY_8	(OMAP2_CONTROL_GENERAL + 0x00e0)
+ + #define OMAP24XX_CONTROL_TEST_KEY_9	(OMAP2_CONTROL_GENERAL + 0x00e4)
+ + 
+ + #define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0)
+ + 
+ + /* 34xx-only CONTROL_GENERAL register offsets */
+ + #define OMAP343X_CONTROL_PADCONF_OFF	(OMAP2_CONTROL_GENERAL + 0x0000)
+ + #define OMAP343X_CONTROL_MEM_DFTRW0	(OMAP2_CONTROL_GENERAL + 0x0008)
+ + #define OMAP343X_CONTROL_MEM_DFTRW1	(OMAP2_CONTROL_GENERAL + 0x000c)
+ + #define OMAP343X_CONTROL_DEVCONF1	(OMAP2_CONTROL_GENERAL + 0x0068)
+ + #define OMAP343X_CONTROL_CSIRXFE		(OMAP2_CONTROL_GENERAL + 0x006c)
+ + #define OMAP343X_CONTROL_SEC_STATUS		(OMAP2_CONTROL_GENERAL + 0x0070)
+ + #define OMAP343X_CONTROL_SEC_ERR_STATUS		(OMAP2_CONTROL_GENERAL + 0x0074)
+ + #define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG	(OMAP2_CONTROL_GENERAL + 0x0078)
+ + #define OMAP343X_CONTROL_STATUS			(OMAP2_CONTROL_GENERAL + 0x0080)
+ + #define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS	(OMAP2_CONTROL_GENERAL + 0x0084)
+ + #define OMAP343X_CONTROL_RPUB_KEY_H_4	(OMAP2_CONTROL_GENERAL + 0x00a0)
+ + #define OMAP343X_CONTROL_RAND_KEY_0	(OMAP2_CONTROL_GENERAL + 0x00a8)
+ + #define OMAP343X_CONTROL_RAND_KEY_1	(OMAP2_CONTROL_GENERAL + 0x00ac)
+ + #define OMAP343X_CONTROL_RAND_KEY_2	(OMAP2_CONTROL_GENERAL + 0x00b0)
+ + #define OMAP343X_CONTROL_RAND_KEY_3	(OMAP2_CONTROL_GENERAL + 0x00b4)
+ + #define OMAP343X_CONTROL_TEST_KEY_0	(OMAP2_CONTROL_GENERAL + 0x00c8)
+ + #define OMAP343X_CONTROL_TEST_KEY_1	(OMAP2_CONTROL_GENERAL + 0x00cc)
+ + #define OMAP343X_CONTROL_TEST_KEY_2	(OMAP2_CONTROL_GENERAL + 0x00d0)
+ + #define OMAP343X_CONTROL_TEST_KEY_3	(OMAP2_CONTROL_GENERAL + 0x00d4)
+ + #define OMAP343X_CONTROL_TEST_KEY_4	(OMAP2_CONTROL_GENERAL + 0x00d8)
+ + #define OMAP343X_CONTROL_TEST_KEY_5	(OMAP2_CONTROL_GENERAL + 0x00dc)
+ + #define OMAP343X_CONTROL_TEST_KEY_6	(OMAP2_CONTROL_GENERAL + 0x00e0)
+ + #define OMAP343X_CONTROL_TEST_KEY_7	(OMAP2_CONTROL_GENERAL + 0x00e4)
+ + #define OMAP343X_CONTROL_TEST_KEY_8	(OMAP2_CONTROL_GENERAL + 0x00e8)
+ + #define OMAP343X_CONTROL_TEST_KEY_9	(OMAP2_CONTROL_GENERAL + 0x00ec)
+ + #define OMAP343X_CONTROL_TEST_KEY_10	(OMAP2_CONTROL_GENERAL + 0x00f0)
+ + #define OMAP343X_CONTROL_TEST_KEY_11	(OMAP2_CONTROL_GENERAL + 0x00f4)
+ + #define OMAP343X_CONTROL_TEST_KEY_12	(OMAP2_CONTROL_GENERAL + 0x00f8)
+ + #define OMAP343X_CONTROL_TEST_KEY_13	(OMAP2_CONTROL_GENERAL + 0x00fc)
+ + #define OMAP343X_CONTROL_FUSE_OPP1_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110)
+ + #define OMAP343X_CONTROL_FUSE_OPP2_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114)
+ + #define OMAP343X_CONTROL_FUSE_OPP3_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118)
+ + #define OMAP343X_CONTROL_FUSE_OPP4_VDD1 (OMAP2_CONTROL_GENERAL + 0x011c)
+ + #define OMAP343X_CONTROL_FUSE_OPP5_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120)
+ + #define OMAP343X_CONTROL_FUSE_OPP1_VDD2 (OMAP2_CONTROL_GENERAL + 0x0124)
+ + #define OMAP343X_CONTROL_FUSE_OPP2_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128)
+ + #define OMAP343X_CONTROL_FUSE_OPP3_VDD2 (OMAP2_CONTROL_GENERAL + 0x012c)
+ + #define OMAP343X_CONTROL_FUSE_SR        (OMAP2_CONTROL_GENERAL + 0x0130)
+ + #define OMAP343X_CONTROL_IVA2_BOOTADDR	(OMAP2_CONTROL_GENERAL + 0x0190)
+ + #define OMAP343X_CONTROL_IVA2_BOOTMOD	(OMAP2_CONTROL_GENERAL + 0x0194)
+ + #define OMAP343X_CONTROL_DEBOBS(i)	(OMAP2_CONTROL_GENERAL + 0x01B0 \
+ + 					+ ((i) >> 1) * 4 + (!((i) & 1)) * 2)
+ + #define OMAP343X_CONTROL_PROG_IO0	(OMAP2_CONTROL_GENERAL + 0x01D4)
+ + #define OMAP343X_CONTROL_PROG_IO1	(OMAP2_CONTROL_GENERAL + 0x01D8)
+ + #define OMAP343X_CONTROL_DSS_DPLL_SPREADING	(OMAP2_CONTROL_GENERAL + 0x01E0)
+ + #define OMAP343X_CONTROL_CORE_DPLL_SPREADING	(OMAP2_CONTROL_GENERAL + 0x01E4)
+ + #define OMAP343X_CONTROL_PER_DPLL_SPREADING	(OMAP2_CONTROL_GENERAL + 0x01E8)
+ + #define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING	(OMAP2_CONTROL_GENERAL + 0x01EC)
+ + #define OMAP343X_CONTROL_PBIAS_LITE	(OMAP2_CONTROL_GENERAL + 0x02B0)
+ + #define OMAP343X_CONTROL_TEMP_SENSOR	(OMAP2_CONTROL_GENERAL + 0x02B4)
+ + #define OMAP343X_CONTROL_SRAMLDO4	(OMAP2_CONTROL_GENERAL + 0x02B8)
+ + #define OMAP343X_CONTROL_SRAMLDO5	(OMAP2_CONTROL_GENERAL + 0x02C0)
+ + #define OMAP343X_CONTROL_CSI		(OMAP2_CONTROL_GENERAL + 0x02C4)
+ + 
+ + /* OMAP3630 only CONTROL_GENERAL register offsets */
+ + #define OMAP3630_CONTROL_FUSE_OPP1G_VDD1        (OMAP2_CONTROL_GENERAL + 0x0110)
+ + #define OMAP3630_CONTROL_FUSE_OPP50_VDD1        (OMAP2_CONTROL_GENERAL + 0x0114)
+ + #define OMAP3630_CONTROL_FUSE_OPP100_VDD1       (OMAP2_CONTROL_GENERAL + 0x0118)
+ + #define OMAP3630_CONTROL_FUSE_OPP120_VDD1       (OMAP2_CONTROL_GENERAL + 0x0120)
+ + #define OMAP3630_CONTROL_FUSE_OPP50_VDD2        (OMAP2_CONTROL_GENERAL + 0x0128)
+ + #define OMAP3630_CONTROL_FUSE_OPP100_VDD2       (OMAP2_CONTROL_GENERAL + 0x012C)
+ + 
+ + /* OMAP44xx control efuse offsets */
+ + #define OMAP44XX_CONTROL_FUSE_IVA_OPP50		0x22C
+ + #define OMAP44XX_CONTROL_FUSE_IVA_OPP100	0x22F
+ + #define OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO	0x232
+ + #define OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO	0x235
+ + #define OMAP44XX_CONTROL_FUSE_MPU_OPP50		0x240
+ + #define OMAP44XX_CONTROL_FUSE_MPU_OPP100	0x243
+ + #define OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO	0x246
+ + #define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO	0x249
+ + #define OMAP44XX_CONTROL_FUSE_CORE_OPP50	0x254
+ + #define OMAP44XX_CONTROL_FUSE_CORE_OPP100	0x257
+ + 
+ + /* AM35XX only CONTROL_GENERAL register offsets */
+ + #define AM35XX_CONTROL_MSUSPENDMUX_6    (OMAP2_CONTROL_GENERAL + 0x0038)
+ + #define AM35XX_CONTROL_DEVCONF2         (OMAP2_CONTROL_GENERAL + 0x0310)
+ + #define AM35XX_CONTROL_DEVCONF3         (OMAP2_CONTROL_GENERAL + 0x0314)
+ + #define AM35XX_CONTROL_CBA_PRIORITY     (OMAP2_CONTROL_GENERAL + 0x0320)
+ + #define AM35XX_CONTROL_LVL_INTR_CLEAR   (OMAP2_CONTROL_GENERAL + 0x0324)
+ + #define AM35XX_CONTROL_IP_SW_RESET      (OMAP2_CONTROL_GENERAL + 0x0328)
+ + #define AM35XX_CONTROL_IPSS_CLK_CTRL    (OMAP2_CONTROL_GENERAL + 0x032C)
+ + 
+ + /* 34xx PADCONF register offsets */
+ + #define OMAP343X_PADCONF_ETK(i)		(OMAP2_CONTROL_PADCONFS + 0x5a8 + \
+ + 						(i)*2)
+ + #define OMAP343X_PADCONF_ETK_CLK	OMAP343X_PADCONF_ETK(0)
+ + #define OMAP343X_PADCONF_ETK_CTL	OMAP343X_PADCONF_ETK(1)
+ + #define OMAP343X_PADCONF_ETK_D0		OMAP343X_PADCONF_ETK(2)
+ + #define OMAP343X_PADCONF_ETK_D1		OMAP343X_PADCONF_ETK(3)
+ + #define OMAP343X_PADCONF_ETK_D2		OMAP343X_PADCONF_ETK(4)
+ + #define OMAP343X_PADCONF_ETK_D3		OMAP343X_PADCONF_ETK(5)
+ + #define OMAP343X_PADCONF_ETK_D4		OMAP343X_PADCONF_ETK(6)
+ + #define OMAP343X_PADCONF_ETK_D5		OMAP343X_PADCONF_ETK(7)
+ + #define OMAP343X_PADCONF_ETK_D6		OMAP343X_PADCONF_ETK(8)
+ + #define OMAP343X_PADCONF_ETK_D7		OMAP343X_PADCONF_ETK(9)
+ + #define OMAP343X_PADCONF_ETK_D8		OMAP343X_PADCONF_ETK(10)
+ + #define OMAP343X_PADCONF_ETK_D9		OMAP343X_PADCONF_ETK(11)
+ + #define OMAP343X_PADCONF_ETK_D10	OMAP343X_PADCONF_ETK(12)
+ + #define OMAP343X_PADCONF_ETK_D11	OMAP343X_PADCONF_ETK(13)
+ + #define OMAP343X_PADCONF_ETK_D12	OMAP343X_PADCONF_ETK(14)
+ + #define OMAP343X_PADCONF_ETK_D13	OMAP343X_PADCONF_ETK(15)
+ + #define OMAP343X_PADCONF_ETK_D14	OMAP343X_PADCONF_ETK(16)
+ + #define OMAP343X_PADCONF_ETK_D15	OMAP343X_PADCONF_ETK(17)
+ + 
+ + /* 34xx GENERAL_WKUP regist offsets */
+ + #define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \
+ + 						0x008 + (i))
+ + #define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008)
+ + #define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C)
+ + #define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010)
+ + #define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
+ + #define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
+ + 
+ + /* 36xx-only RTA - Retention till Access control registers and bits */
+ + #define OMAP36XX_CONTROL_MEM_RTA_CTRL	0x40C
+ + #define OMAP36XX_RTA_DISABLE		0x0
+ + 
+ + /* 34xx D2D idle-related pins, handled by PM core */
+ + #define OMAP3_PADCONF_SAD2D_MSTANDBY   0x250
+ + #define OMAP3_PADCONF_SAD2D_IDLEACK    0x254
+ + 
+ + /* TI81XX CONTROL_DEVCONF register offsets */
+ + #define TI81XX_CONTROL_DEVICE_ID	(TI81XX_CONTROL_DEVCONF + 0x000)
+ + 
+ + /*
+ +  * REVISIT: This list of registers is not comprehensive - there are more
+ +  * that should be added.
+ +  */
+ + 
+ + /*
+ +  * Control module register bit defines - these should eventually go into
+ +  * their own regbits file.  Some of these will be complicated, depending
+ +  * on the device type (general-purpose, emulator, test, secure, bad, other)
+ +  * and the security mode (secure, non-secure, don't care)
+ +  */
+ + /* CONTROL_DEVCONF0 bits */
+ + #define OMAP2_MMCSDIO1ADPCLKISEL	(1 << 24) /* MMC1 loop back clock */
+ + #define OMAP24XX_USBSTANDBYCTRL		(1 << 15)
+ + #define OMAP2_MCBSP2_CLKS_MASK		(1 << 6)
+ + #define OMAP2_MCBSP1_FSR_MASK		(1 << 4)
+ + #define OMAP2_MCBSP1_CLKR_MASK		(1 << 3)
+ + #define OMAP2_MCBSP1_CLKS_MASK		(1 << 2)
+ + 
+ + /* CONTROL_DEVCONF1 bits */
+ + #define OMAP243X_MMC1_ACTIVE_OVERWRITE	(1 << 31)
+ + #define OMAP2_MMCSDIO2ADPCLKISEL	(1 << 6) /* MMC2 loop back clock */
+ + #define OMAP2_MCBSP5_CLKS_MASK		(1 << 4) /* > 242x */
+ + #define OMAP2_MCBSP4_CLKS_MASK		(1 << 2) /* > 242x */
+ + #define OMAP2_MCBSP3_CLKS_MASK		(1 << 0) /* > 242x */
+ + 
+ + /* CONTROL_STATUS bits */
+ + #define OMAP2_DEVICETYPE_MASK		(0x7 << 8)
+ + #define OMAP2_SYSBOOT_5_MASK		(1 << 5)
+ + #define OMAP2_SYSBOOT_4_MASK		(1 << 4)
+ + #define OMAP2_SYSBOOT_3_MASK		(1 << 3)
+ + #define OMAP2_SYSBOOT_2_MASK		(1 << 2)
+ + #define OMAP2_SYSBOOT_1_MASK		(1 << 1)
+ + #define OMAP2_SYSBOOT_0_MASK		(1 << 0)
+ + 
+ + /* CONTROL_PBIAS_LITE bits */
+ + #define OMAP343X_PBIASLITESUPPLY_HIGH1	(1 << 15)
+ + #define OMAP343X_PBIASLITEVMODEERROR1	(1 << 11)
+ + #define OMAP343X_PBIASSPEEDCTRL1	(1 << 10)
+ + #define OMAP343X_PBIASLITEPWRDNZ1	(1 << 9)
+ + #define OMAP343X_PBIASLITEVMODE1	(1 << 8)
+ + #define OMAP343X_PBIASLITESUPPLY_HIGH0	(1 << 7)
+ + #define OMAP343X_PBIASLITEVMODEERROR0	(1 << 3)
+ + #define OMAP2_PBIASSPEEDCTRL0		(1 << 2)
+ + #define OMAP2_PBIASLITEPWRDNZ0		(1 << 1)
+ + #define OMAP2_PBIASLITEVMODE0		(1 << 0)
+ + 
+ + /* CONTROL_PROG_IO1 bits */
+ + #define OMAP3630_PRG_SDMMC1_SPEEDCTRL	(1 << 20)
+ + 
+ + /* CONTROL_IVA2_BOOTMOD bits */
+ + #define OMAP3_IVA2_BOOTMOD_SHIFT	0
+ + #define OMAP3_IVA2_BOOTMOD_MASK		(0xf << 0)
+ + #define OMAP3_IVA2_BOOTMOD_IDLE		(0x1 << 0)
+ + 
+ + /* CONTROL_PADCONF_X bits */
+ + #define OMAP3_PADCONF_WAKEUPEVENT0	(1 << 15)
+ + #define OMAP3_PADCONF_WAKEUPENABLE0	(1 << 14)
+ + 
+ + #define OMAP343X_SCRATCHPAD_ROM		(OMAP343X_CTRL_BASE + 0x860)
+ + #define OMAP343X_SCRATCHPAD		(OMAP343X_CTRL_BASE + 0x910)
+ + #define OMAP343X_SCRATCHPAD_ROM_OFFSET	0x19C
+ + #define OMAP343X_SCRATCHPAD_REGADDR(reg)	OMAP2_L4_IO_ADDRESS(\
+ + 						OMAP343X_SCRATCHPAD + reg)
+ + 
+ + /* AM35XX_CONTROL_IPSS_CLK_CTRL bits */
+ + #define AM35XX_USBOTG_VBUSP_CLK_SHIFT   0
+ + #define AM35XX_CPGMAC_VBUSP_CLK_SHIFT   1
+ + #define AM35XX_VPFE_VBUSP_CLK_SHIFT     2
+ + #define AM35XX_HECC_VBUSP_CLK_SHIFT     3
+ + #define AM35XX_USBOTG_FCLK_SHIFT        8
+ + #define AM35XX_CPGMAC_FCLK_SHIFT        9
+ + #define AM35XX_VPFE_FCLK_SHIFT          10
+ + 
+ + /*AM35XX CONTROL_LVL_INTR_CLEAR bits*/
+ + #define AM35XX_CPGMAC_C0_MISC_PULSE_CLR	BIT(0)
+ + #define AM35XX_CPGMAC_C0_RX_PULSE_CLR	BIT(1)
+ + #define AM35XX_CPGMAC_C0_RX_THRESH_CLR	BIT(2)
+ + #define AM35XX_CPGMAC_C0_TX_PULSE_CLR	BIT(3)
+ + #define AM35XX_USBOTGSS_INT_CLR		BIT(4)
+ + #define AM35XX_VPFE_CCDC_VD0_INT_CLR	BIT(5)
+ + #define AM35XX_VPFE_CCDC_VD1_INT_CLR	BIT(6)
+ + #define AM35XX_VPFE_CCDC_VD2_INT_CLR	BIT(7)
+ + 
+ + /*AM35XX CONTROL_IP_SW_RESET bits*/
+ + #define AM35XX_USBOTGSS_SW_RST		BIT(0)
+ + #define AM35XX_CPGMACSS_SW_RST		BIT(1)
+ + #define AM35XX_VPFE_VBUSP_SW_RST	BIT(2)
+ + #define AM35XX_HECC_SW_RST		BIT(3)
+ + #define AM35XX_VPFE_PCLK_SW_RST		BIT(4)
+ + 
+ + /* AM33XX CONTROL_STATUS bits */
+ + #define AM33XX_SYSBOOT0			(0xff << 0)
+ + #define AM33XX_DEVTYPE			(1 << 8)
+ + #define AM33XX_GPMC_CS0_BW		(1 << 16)
+ + #define AM33XX_GPMC_CS0_WAITEN		(1 << 17)
+ + #define AM33XX_GPMC_CS0_ADMUX		(0x3 << 18)
+ + #define AM33XX_SYSBOOT1			(0x3 << 22)
+ + 
+ + /*
+ +  * CONTROL AM33XX STATUS register to identify boot-time configurations
+ +  */
+ + #define AM33XX_CONTROL_STATUS_OFF	0x040
+ + #define AM33XX_CONTROL_STATUS		AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE + \
+ + 						AM33XX_CONTROL_STATUS_OFF)
+ + #define AM33XX_DEV_FEATURE		0x604
+ + #define AM33XX_SGX_SHIFT		29
+ + #define AM33XX_SGX_MASK			(1 << AM33XX_SGX_SHIFT)
+ + 
+ + /*
+ +  * CONTROL AM33XX GMII_SEL register for MII mode selection
+ +  */
+ + #define AM33XX_CONTROL_GMII_SEL_OFFSET	0x650
+ + #define AM33XX_RGMII_DISABLE_INT_DLY	(BIT(4) | BIT(5))
+ + #define AM33XX_MII_MODE_EN		0x0
+ + #define AM33XX_RMII_MODE_EN		((1 << 0) | (1 << 2))
+ + #define AM33XX_RGMII_MODE_EN		((0x2 << 0) | (0x2 << 2) | \
+ + 					(AM33XX_RGMII_DISABLE_INT_DLY))
+ + 
+ + /*
+ +  * CONTROL AM33XX PWMSS_CTRL register to enable time base clock Enable
+ +  */
+ + 
+ + #define AM33XX_CONTROL_PWMSS_CTRL_OFS	0x664
+ + #define AM33XX_PWMSS0_TBCLKEN		0x0
+ + #define AM33XX_PWMSS1_TBCLKEN		0x1
+ + #define AM33XX_PWMSS2_TBCLKEN		0x2
+ + #define AM33XX_CONTROL_PWMSS_CTRL	AM33XX_L4_WK_IO_ADDRESS( \
+ + 		AM33XX_CTRL_BASE + AM33XX_CONTROL_PWMSS_CTRL_OFS)
+ + 
+ + /*
+ +  * CONTROL OMAP STATUS register to identify OMAP3 features
+ +  */
+ + #define OMAP3_CONTROL_OMAP_STATUS	0x044c
+ + 
+ + #define OMAP3_SGX_SHIFT			13
+ + #define OMAP3_SGX_MASK			(3 << OMAP3_SGX_SHIFT)
+ + #define		FEAT_SGX_FULL		0
+ + #define		FEAT_SGX_HALF		1
+ + #define		FEAT_SGX_NONE		2
+ + 
+ + #define OMAP3_IVA_SHIFT			12
+ + #define OMAP3_IVA_MASK			(1 << OMAP3_IVA_SHIFT)
+ + #define		FEAT_IVA		0
+ + #define		FEAT_IVA_NONE		1
+ + 
+ + #define OMAP3_L2CACHE_SHIFT		10
+ + #define OMAP3_L2CACHE_MASK		(3 << OMAP3_L2CACHE_SHIFT)
+ + #define		FEAT_L2CACHE_NONE	0
+ + #define		FEAT_L2CACHE_64KB	1
+ + #define		FEAT_L2CACHE_128KB	2
+ + #define		FEAT_L2CACHE_256KB	3
+ + 
+ + #define OMAP3_ISP_SHIFT			5
+ + #define OMAP3_ISP_MASK			(1 << OMAP3_ISP_SHIFT)
+ + #define		FEAT_ISP		0
+ + #define		FEAT_ISP_NONE		1
+ + 
+ + #define OMAP3_NEON_SHIFT		4
+ + #define OMAP3_NEON_MASK			(1 << OMAP3_NEON_SHIFT)
+ + #define		FEAT_NEON		0
+ + #define		FEAT_NEON_NONE		1
+ + 
+ + 
+ + #ifndef __ASSEMBLY__
+ + extern void __iomem *omap_ctrl_base_get(void);
+ + extern u8 omap_ctrl_readb(u16 offset);
+ + extern u16 omap_ctrl_readw(u16 offset);
+ + extern u32 omap_ctrl_readl(u16 offset);
+ + extern u32 omap4_ctrl_pad_readl(u16 offset);
+ + extern void omap_ctrl_writeb(u8 val, u16 offset);
+ + extern void omap_ctrl_writew(u16 val, u16 offset);
+ + extern void omap_ctrl_writel(u32 val, u16 offset);
+ + extern void omap4_ctrl_pad_writel(u32 val, u16 offset);
+ + 
+ + extern void omap3_save_scratchpad_contents(void);
+ + extern void omap3_clear_scratchpad_contents(void);
+ + extern void omap3_restore(void);
+ + extern void omap3_restore_es3(void);
+ + extern void omap3_restore_3630(void);
+ + extern u32 omap3_arm_context[128];
+ + extern void omap3_control_save_context(void);
+ + extern void omap3_control_restore_context(void);
+ + extern void omap3_ctrl_write_boot_mode(u8 bootmode);
+ + extern void omap3630_ctrl_disable_rta(void);
+ + extern int omap3_ctrl_save_padconf(void);
+ + #endif	/* __ASSEMBLY__ */
+ + 
+ + #endif /* __ARCH_ARM_MACH_CKB_3352_CONTROL_H */
+ + 
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/cpuidle33xx.c linux-3.2.1/arch/arm/mach-ckb_3352/cpuidle33xx.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/cpuidle33xx.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/cpuidle33xx.c	2014-11-25 13:19:14.971039560 +0900
+ ***************
+ *** 0 ****
+ --- 1,179 ----
+ + /*
+ +  * CPU idle for AM33XX SoCs
+ +  *
+ +  * Copyright (C) 2011 Texas Instruments Incorporated. http://www.ti.com/
+ +  *
+ +  * Derived from Davinci CPU idle code
+ +  * (arch/arm/mach-davinci/cpuidle.c)
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #include <linux/kernel.h>
+ + #include <linux/module.h>
+ + #include <linux/init.h>
+ + #include <linux/io.h>
+ + #include <linux/platform_device.h>
+ + #include <linux/cpuidle.h>
+ + #include <linux/sched.h>
+ + #include <asm/proc-fns.h>
+ + 
+ + #include <plat/emif.h>
+ + 
+ + #include "cpuidle33xx.h"
+ + 
+ + #define AM33XX_CPUIDLE_MAX_STATES	2
+ + 
+ + struct am33xx_ops {
+ + 	void (*enter) (u32 flags);
+ + 	void (*exit) (u32 flags);
+ + 	u32 flags;
+ + };
+ + 
+ + /* fields in am33xx_ops.flags */
+ + #define AM33XX_CPUIDLE_FLAGS_DDR2_PWDN	BIT(0)
+ + 
+ + static struct cpuidle_driver am33xx_idle_driver = {
+ + 	.name	= "cpuidle-am33xx",
+ + 	.owner	= THIS_MODULE,
+ + };
+ + 
+ + static DEFINE_PER_CPU(struct cpuidle_device, am33xx_cpuidle_device);
+ + static void __iomem *emif_base;
+ + 
+ + static void am33xx_save_ddr_power(int enter, bool pdown)
+ + {
+ + 	u32 val;
+ + 
+ + 	val = __raw_readl(emif_base + EMIF4_0_SDRAM_MGMT_CTRL);
+ + 
+ + 	/* TODO: Choose the mode based on memory type */
+ + 	if (enter)
+ + 		val = SELF_REFRESH_ENABLE(64);
+ + 	else
+ + 		val = SELF_REFRESH_DISABLE;
+ + 
+ + 	__raw_writel(val, emif_base + EMIF4_0_SDRAM_MGMT_CTRL);
+ + }
+ + 
+ + static void am33xx_c2state_enter(u32 flags)
+ + {
+ + 	am33xx_save_ddr_power(1, !!(flags & AM33XX_CPUIDLE_FLAGS_DDR2_PWDN));
+ + }
+ + 
+ + static void am33xx_c2state_exit(u32 flags)
+ + {
+ + 	am33xx_save_ddr_power(0, !!(flags & AM33XX_CPUIDLE_FLAGS_DDR2_PWDN));
+ + }
+ + 
+ + static struct am33xx_ops am33xx_states[AM33XX_CPUIDLE_MAX_STATES] = {
+ + 	[1] = {
+ + 		.enter	= am33xx_c2state_enter,
+ + 		.exit	= am33xx_c2state_exit,
+ + 	},
+ + };
+ + 
+ + /* Actual code that puts the SoC in different idle states */
+ + static int am33xx_enter_idle(struct cpuidle_device *dev,
+ + 				struct cpuidle_driver *drv, int index)
+ + {
+ + 	struct cpuidle_state_usage *state_usage = &dev->states_usage[index];
+ + 	struct am33xx_ops *ops = cpuidle_get_statedata(state_usage);
+ + 	struct timeval before, after;
+ + 	int idle_time;
+ + 
+ + 	local_irq_disable();
+ + 	do_gettimeofday(&before);
+ + 
+ + 	if (ops && ops->enter)
+ + 		ops->enter(ops->flags);
+ + 
+ + 	/* Wait for interrupt state */
+ + 	cpu_do_idle();
+ + 	if (ops && ops->exit)
+ + 		ops->exit(ops->flags);
+ + 
+ + 	do_gettimeofday(&after);
+ + 	local_irq_enable();
+ + 	idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
+ + 			(after.tv_usec - before.tv_usec);
+ + 
+ + 	dev->last_residency = idle_time;
+ + 
+ + 	return index;
+ + }
+ + 
+ + static int __init am33xx_cpuidle_probe(struct platform_device *pdev)
+ + {
+ + 	int ret;
+ + 	struct cpuidle_device *device;
+ + 	struct cpuidle_driver *driver = &am33xx_idle_driver;
+ + 	struct am33xx_cpuidle_config *pdata = pdev->dev.platform_data;
+ + 
+ + 	device = &per_cpu(am33xx_cpuidle_device, smp_processor_id());
+ + 
+ + 	if (!pdata) {
+ + 		dev_err(&pdev->dev, "cannot get platform data\n");
+ + 		return -ENOENT;
+ + 	}
+ + 
+ + 	emif_base = pdata->emif_base;
+ + 
+ + 	/* Wait for interrupt state */
+ + 	driver->states[0].enter = am33xx_enter_idle;
+ + 	driver->states[0].exit_latency = 1;
+ + 	driver->states[0].target_residency = 10000;
+ + 	driver->states[0].flags = CPUIDLE_FLAG_TIME_VALID;
+ + 	strcpy(driver->states[0].name, "WFI");
+ + 	strcpy(driver->states[0].desc, "Wait for interrupt");
+ + 
+ + 	/* Wait for interrupt and DDR self refresh state */
+ + 	driver->states[1].enter = am33xx_enter_idle;
+ + 	driver->states[1].exit_latency = 100;
+ + 	driver->states[1].target_residency = 10000;
+ + 	driver->states[1].flags = CPUIDLE_FLAG_TIME_VALID;
+ + 	strcpy(driver->states[1].name, "DDR SR");
+ + 	strcpy(driver->states[1].desc, "WFI and DDR Self Refresh");
+ + 	if (pdata->ddr2_pdown)
+ + 		am33xx_states[1].flags |= AM33XX_CPUIDLE_FLAGS_DDR2_PWDN;
+ + 	cpuidle_set_statedata(&device->states_usage[1], &am33xx_states[1]);
+ + 
+ + 	device->state_count = AM33XX_CPUIDLE_MAX_STATES;
+ + 	driver->state_count = AM33XX_CPUIDLE_MAX_STATES;
+ + 
+ + 	ret = cpuidle_register_driver(&am33xx_idle_driver);
+ + 	if (ret) {
+ + 		dev_err(&pdev->dev, "failed to register driver\n");
+ + 		return ret;
+ + 	}
+ + 
+ + 	ret = cpuidle_register_device(device);
+ + 	if (ret) {
+ + 		dev_err(&pdev->dev, "failed to register device\n");
+ + 		cpuidle_unregister_driver(&am33xx_idle_driver);
+ + 		return ret;
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static struct platform_driver am33xx_cpuidle_driver = {
+ + 	.driver = {
+ + 		.name	= "cpuidle-am33xx",
+ + 		.owner	= THIS_MODULE,
+ + 	},
+ + };
+ + 
+ + static int __init am33xx_cpuidle_init(void)
+ + {
+ + 	return platform_driver_probe(&am33xx_cpuidle_driver,
+ + 						am33xx_cpuidle_probe);
+ + }
+ + device_initcall(am33xx_cpuidle_init);
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/cpuidle33xx.h linux-3.2.1/arch/arm/mach-ckb_3352/cpuidle33xx.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/cpuidle33xx.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/cpuidle33xx.h	2014-11-25 13:19:14.971039560 +0900
+ ***************
+ *** 0 ****
+ --- 1,24 ----
+ + /*
+ +  * TI AM33XX cpuidle platform support
+ +  *
+ +  * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #ifndef _AM33XX_CPUIDLE_H
+ + #define _AM33XX_CPUIDLE_H
+ + 
+ + struct am33xx_cpuidle_config {
+ + 	u32 ddr2_pdown;
+ + 	void __iomem *emif_base;
+ + };
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/devices.c linux-3.2.1/arch/arm/mach-ckb_3352/devices.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/devices.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/devices.c	2014-11-26 18:43:01.630318000 +0900
+ ***************
+ *** 0 ****
+ --- 1,1284 ----
+ + /*
+ +  * linux/arch/arm/mach-omap2/devices.c
+ +  *
+ +  * OMAP2 platform device setup/initialization
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; either version 2 of the License, or
+ +  * (at your option) any later version.
+ +  */
+ + #include <linux/gpio.h>
+ + #include <linux/kernel.h>
+ + #include <linux/init.h>
+ + #include <linux/platform_device.h>
+ + #include <linux/io.h>
+ + #include <linux/clk.h>
+ + #include <linux/err.h>
+ + #include <linux/export.h>
+ + #include <linux/slab.h>
+ + #include <linux/of.h>
+ + #include <linux/davinci_emac.h>
+ + #include <linux/cpsw.h>
+ + #include <linux/etherdevice.h>
+ + #include <linux/dma-mapping.h>
+ + #include <linux/can/platform/d_can.h>
+ + #include <linux/platform_data/uio_pruss.h>
+ + #include <linux/pwm/pwm.h>
+ + 
+ + #include <mach/hardware.h>
+ + #include <mach/irqs.h>
+ + #include <asm/mach-types.h>
+ + #include <asm/mach/map.h>
+ + #include <asm/pmu.h>
+ + 
+ + #ifdef	CONFIG_OMAP3_EDMA
+ + #include <mach/edma.h>
+ + #endif
+ + 
+ + 
+ + 
+ + #include <plat/board.h>
+ + #include <plat/mmc.h>
+ + #include <plat/dma.h>
+ + #include <plat/omap_hwmod.h>
+ + #include <plat/omap_device.h>
+ + #include <plat/am33xx.h>
+ + #include <plat/config_pwm.h>
+ + #include <plat/cpu.h>
+ + #include <plat/gpmc.h>
+ + #include <plat/smartreflex.h>
+ + #include <plat/am33xx.h>
+ + 
+ + /* LCD controller similar DA8xx */
+ + #include <video/da8xx-fb.h>
+ + 
+ + #include "mux.h"
+ + #include "control.h"
+ + #include "devices.h"
+ + #include "omap_opp_data.h"
+ + 
+ + #define L3_MODULES_MAX_LEN 12
+ + #define L3_MODULES 3
+ + 
+ + static unsigned int   am33xx_evmid;
+ + 
+ + /*
+ +  * am33xx_evmid_fillup - set up board evmid
+ +  * @evmid - evm id which needs to be configured
+ +  *
+ +  * This function is called to configure board evm id.
+ +  * IA Motor Control EVM needs special setting of MAC PHY Id.
+ +  * This function is called when IA Motor Control EVM is detected
+ +  * during boot-up.
+ +  */
+ + void am33xx_evmid_fillup(unsigned int evmid)
+ + {
+ +        am33xx_evmid = evmid;
+ +        return;
+ + }
+ + 
+ + static int __init omap3_l3_init(void)
+ + {
+ + 	int l;
+ + 	struct omap_hwmod *oh;
+ + 	struct platform_device *pdev;
+ + 	char oh_name[L3_MODULES_MAX_LEN];
+ + 
+ + 	l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
+ + 
+ + 	oh = omap_hwmod_lookup(oh_name);
+ + 
+ + 	if (!oh)
+ + 		pr_err("could not look up %s\n", oh_name);
+ + 
+ + 	pdev = omap_device_build("omap_l3_smx", 0, oh, NULL, 0,
+ + 							   NULL, 0, 0);
+ + 
+ + 	WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
+ + 
+ + 	return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
+ + }
+ + postcore_initcall(omap3_l3_init);
+ + 
+ + #if defined(CONFIG_CKB_LCD_SUPPORT) || defined(CONFIG_CKB_DVI_SUPPORT)
+ + int __init am33xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
+ + {
+ + 	int id = 0;
+ + 	struct platform_device *pdev;
+ + 	struct omap_hwmod *oh;
+ + 	char *oh_name = "lcdc";
+ + 	char *dev_name = "da8xx_lcdc";
+ + 
+ + 	oh = omap_hwmod_lookup(oh_name);
+ + 	if (!oh) {
+ + 		pr_err("Could not look up LCD%d hwmod\n", id);
+ + 		return -ENODEV;
+ + 	}
+ + 
+ + 	pdev = omap_device_build(dev_name, id, oh, pdata,
+ + 			sizeof(struct da8xx_lcdc_platform_data), NULL, 0, 0);
+ + 	if (IS_ERR(pdev)) {
+ + 		WARN(1, "Can't build omap_device for %s:%s.\n",
+ + 			dev_name, oh->name);
+ + 		return PTR_ERR(pdev);
+ + 	}
+ + 	return 0;
+ + }
+ + #endif
+ + 
+ + #ifdef CONFIG_CKB_3352_AUDIO
+ + int __init am335x_register_mcasp(struct snd_platform_data *pdata, int ctrl_nr)
+ + {
+ + 	int l;
+ + 	struct omap_hwmod *oh;
+ + 	struct platform_device *pdev;
+ + 	char oh_name[12];
+ + 	char *dev_name = "davinci-mcasp";
+ + 
+ + 	l = snprintf(oh_name, 12, "mcasp%d", ctrl_nr);
+ + 
+ + 	oh = omap_hwmod_lookup(oh_name);
+ + 	if (!oh) {
+ + 		pr_err("could not look up %s\n", oh_name);
+ + 		return -ENODEV;
+ + 	}
+ + 
+ + 	pdev = omap_device_build(dev_name, ctrl_nr, oh, pdata,
+ + 			sizeof(struct snd_platform_data), NULL, 0, 0);
+ + 	WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
+ + 			dev_name, oh->name);
+ + 	return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
+ + }
+ + 
+ + 
+ + 
+ + 
+ + 
+ + 
+ + #endif
+ + 
+ + #ifdef CONFIG_CKB_3352_AUDIO
+ + struct platform_device am33xx_pcm_device = {
+ + 	.name		= "davinci-pcm-audio",
+ + 	.id		= -1,
+ + };
+ + 
+ + static void am33xx_init_pcm(void)
+ + {
+ + 	platform_device_register(&am33xx_pcm_device);
+ + }
+ + #endif
+ + 
+ + static struct resource omap3isp_resources[] = {
+ + 	{
+ + 		.start		= OMAP3430_ISP_BASE,
+ + 		.end		= OMAP3430_ISP_END,
+ + 		.flags		= IORESOURCE_MEM,
+ + 	},
+ + 	{
+ + 		.start		= OMAP3430_ISP_CCP2_BASE,
+ + 		.end		= OMAP3430_ISP_CCP2_END,
+ + 		.flags		= IORESOURCE_MEM,
+ + 	},
+ + 	{
+ + 		.start		= OMAP3430_ISP_CCDC_BASE,
+ + 		.end		= OMAP3430_ISP_CCDC_END,
+ + 		.flags		= IORESOURCE_MEM,
+ + 	},
+ + 	{
+ + 		.start		= OMAP3430_ISP_HIST_BASE,
+ + 		.end		= OMAP3430_ISP_HIST_END,
+ + 		.flags		= IORESOURCE_MEM,
+ + 	},
+ + 	{
+ + 		.start		= OMAP3430_ISP_H3A_BASE,
+ + 		.end		= OMAP3430_ISP_H3A_END,
+ + 		.flags		= IORESOURCE_MEM,
+ + 	},
+ + 	{
+ + 		.start		= OMAP3430_ISP_PREV_BASE,
+ + 		.end		= OMAP3430_ISP_PREV_END,
+ + 		.flags		= IORESOURCE_MEM,
+ + 	},
+ + 	{
+ + 		.start		= OMAP3430_ISP_RESZ_BASE,
+ + 		.end		= OMAP3430_ISP_RESZ_END,
+ + 		.flags		= IORESOURCE_MEM,
+ + 	},
+ + 	{
+ + 		.start		= OMAP3430_ISP_SBL_BASE,
+ + 		.end		= OMAP3430_ISP_SBL_END,
+ + 		.flags		= IORESOURCE_MEM,
+ + 	},
+ + 	{
+ + 		.start		= OMAP3430_ISP_CSI2A_REGS1_BASE,
+ + 		.end		= OMAP3430_ISP_CSI2A_REGS1_END,
+ + 		.flags		= IORESOURCE_MEM,
+ + 	},
+ + 	{
+ + 		.start		= OMAP3430_ISP_CSIPHY2_BASE,
+ + 		.end		= OMAP3430_ISP_CSIPHY2_END,
+ + 		.flags		= IORESOURCE_MEM,
+ + 	},
+ + 	{
+ + 		.start		= OMAP3630_ISP_CSI2A_REGS2_BASE,
+ + 		.end		= OMAP3630_ISP_CSI2A_REGS2_END,
+ + 		.flags		= IORESOURCE_MEM,
+ + 	},
+ + 	{
+ + 		.start		= OMAP3630_ISP_CSI2C_REGS1_BASE,
+ + 		.end		= OMAP3630_ISP_CSI2C_REGS1_END,
+ + 		.flags		= IORESOURCE_MEM,
+ + 	},
+ + 	{
+ + 		.start		= OMAP3630_ISP_CSIPHY1_BASE,
+ + 		.end		= OMAP3630_ISP_CSIPHY1_END,
+ + 		.flags		= IORESOURCE_MEM,
+ + 	},
+ + 	{
+ + 		.start		= OMAP3630_ISP_CSI2C_REGS2_BASE,
+ + 		.end		= OMAP3630_ISP_CSI2C_REGS2_END,
+ + 		.flags		= IORESOURCE_MEM,
+ + 	},
+ + 	{
+ + 		.start		= INT_34XX_CAM_IRQ,
+ + 		.flags		= IORESOURCE_IRQ,
+ + 	}
+ + };
+ + 
+ + static struct platform_device omap3isp_device = {
+ + 	.name		= "omap3isp",
+ + 	.id		= -1,
+ + 	.num_resources	= ARRAY_SIZE(omap3isp_resources),
+ + 	.resource	= omap3isp_resources,
+ + };
+ + 
+ + int omap3_init_camera(struct isp_platform_data *pdata)
+ + {
+ + 	omap3isp_device.dev.platform_data = pdata;
+ + 	return platform_device_register(&omap3isp_device);
+ + }
+ + 
+ + static inline void omap_init_mbox(void)
+ + {
+ + 	struct omap_hwmod *oh;
+ + 	struct platform_device *pdev;
+ + 
+ + 	oh = omap_hwmod_lookup("mailbox");
+ + 	if (!oh) {
+ + 		pr_err("%s: unable to find hwmod\n", __func__);
+ + 		return;
+ + 	}
+ + 
+ + 	pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0, NULL, 0, 0);
+ + 	WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n",
+ + 						__func__, PTR_ERR(pdev));
+ + }
+ + static inline void omap_init_sti(void) {}
+ + 
+ + #if defined(CONFIG_SND_OMAP_SOC_MCPDM) || \
+ + 		defined(CONFIG_SND_OMAP_SOC_MCPDM_MODULE)
+ + 
+ + static void omap_init_mcpdm(void)
+ + {
+ + 	struct omap_hwmod *oh;
+ + 	struct platform_device *pdev;
+ + 
+ + 	oh = omap_hwmod_lookup("mcpdm");
+ + 	if (!oh) {
+ + 		printk(KERN_ERR "Could not look up mcpdm hw_mod\n");
+ + 		return;
+ + 	}
+ + 
+ + 	pdev = omap_device_build("omap-mcpdm", -1, oh, NULL, 0, NULL, 0, 0);
+ + 	WARN(IS_ERR(pdev), "Can't build omap_device for omap-mcpdm.\n");
+ + }
+ + #else
+ + static inline void omap_init_mcpdm(void) {}
+ + #endif
+ + 
+ + #if defined(CONFIG_SND_OMAP_SOC_DMIC) || \
+ + 		defined(CONFIG_SND_OMAP_SOC_DMIC_MODULE)
+ + 
+ + static void omap_init_dmic(void)
+ + {
+ + 	struct omap_hwmod *oh;
+ + 	struct platform_device *pdev;
+ + 
+ + 	oh = omap_hwmod_lookup("dmic");
+ + 	if (!oh) {
+ + 		printk(KERN_ERR "Could not look up mcpdm hw_mod\n");
+ + 		return;
+ + 	}
+ + 
+ + 	pdev = omap_device_build("omap-dmic", -1, oh, NULL, 0, NULL, 0, 0);
+ + 	WARN(IS_ERR(pdev), "Can't build omap_device for omap-dmic.\n");
+ + }
+ + #else
+ + static inline void omap_init_dmic(void) {}
+ + #endif
+ + 
+ + #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
+ + 
+ + #include <plat/mcspi.h>
+ + 
+ + static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
+ + {
+ + 	struct platform_device *pdev;
+ + 	char *name = "omap2_mcspi";
+ + 	struct omap2_mcspi_platform_config *pdata;
+ + 	static int spi_num;
+ + 	struct omap2_mcspi_dev_attr *mcspi_attrib = oh->dev_attr;
+ + 
+ + 	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
+ + 	if (!pdata) {
+ + 		pr_err("Memory allocation for McSPI device failed\n");
+ + 		return -ENOMEM;
+ + 	}
+ + 
+ + 	pdata->num_cs = mcspi_attrib->num_chipselect;
+ + 	switch (oh->class->rev) {
+ + 	case OMAP2_MCSPI_REV:
+ + 	case OMAP3_MCSPI_REV:
+ + 			pdata->regs_offset = 0;
+ + 			break;
+ + 	case OMAP4_MCSPI_REV:
+ + 			pdata->regs_offset = OMAP4_MCSPI_REG_OFFSET;
+ + 			break;
+ + 	default:
+ + 			pr_err("Invalid McSPI Revision value\n");
+ + 			return -EINVAL;
+ + 	}
+ + 
+ + 	spi_num++;
+ + 	pdev = omap_device_build(name, spi_num, oh, pdata,
+ + 				sizeof(*pdata),	NULL, 0, 0);
+ + 	WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s\n",
+ + 				name, oh->name);
+ + 	kfree(pdata);
+ + 	return 0;
+ + }
+ + 
+ + static void omap_init_mcspi(void)
+ + {
+ + 	omap_hwmod_for_each_by_class("mcspi", omap_mcspi_init, NULL);
+ + }
+ + 
+ + #else
+ + static inline void omap_init_mcspi(void) {}
+ + #endif
+ + 
+ + int __init omap_init_elm(void)
+ + {
+ + 	int id = -1;
+ + 	struct platform_device *pdev;
+ + 	struct omap_hwmod *oh;
+ + 	char *oh_name = "elm";
+ + 	char *name = "omap2_elm";
+ + 
+ + 	oh = omap_hwmod_lookup(oh_name);
+ + 	if (!oh) {
+ + 		pr_err("Could not look up %s\n", oh_name);
+ + 		return -ENODEV;
+ + 	}
+ + 
+ + 	pdev = omap_device_build(name, id, oh, NULL, 0, NULL, 0, 0);
+ + 
+ + 	if (IS_ERR(pdev)) {
+ + 		WARN(1, "Can't build omap_device for %s:%s.\n",
+ + 						name, oh->name);
+ + 		return PTR_ERR(pdev);
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ + 
+ + #ifdef CONFIG_CKB_EHRPWM0
+ + #define PWM_STR_LEN 10
+ + int __init am33xx_register_ecap(int id, struct pwmss_platform_data *pdata)
+ + {
+ + 	struct platform_device *pdev;
+ + 	struct omap_hwmod *oh;
+ + 	char *oh_name = "ecap";
+ + 	char dev_name[PWM_STR_LEN];
+ + 
+ + 	sprintf(dev_name, "ecap.%d", id);
+ + 
+ + 	oh = omap_hwmod_lookup(dev_name);
+ + 	if (!oh) {
+ + 		pr_err("Could not look up %s hwmod\n", dev_name);
+ + 		return -ENODEV;
+ + 	}
+ + 
+ + 	pdev = omap_device_build(oh_name, id, oh, pdata,
+ + 			sizeof(*pdata), NULL, 0, 0);
+ + 
+ + 	if (IS_ERR(pdev)) {
+ + 		WARN(1, "Can't build omap_device for %s:%s.\n",
+ + 			dev_name, oh->name);
+ + 		return PTR_ERR(pdev);
+ + 	}
+ + 	return 0;
+ + }
+ + 
+ + int __init am33xx_register_ehrpwm(int id, struct pwmss_platform_data *pdata)
+ + {
+ + 	struct platform_device *pdev;
+ + 	struct omap_hwmod *oh;
+ + 	char *oh_name = "ehrpwm";
+ + 	char dev_name[PWM_STR_LEN];
+ + 
+ + 	sprintf(dev_name, "ehrpwm.%d", id);
+ + 
+ + 	oh = omap_hwmod_lookup(dev_name);
+ + 	if (!oh) {
+ + 		pr_err("Could not look up %s hwmod\n", dev_name);
+ + 		return -ENODEV;
+ + 	}
+ + 
+ + 	pdev = omap_device_build(oh_name, id, oh, pdata,
+ + 			sizeof(*pdata), NULL, 0, 0);
+ + 
+ + 	if (IS_ERR(pdev)) {
+ + 		WARN(1, "Can't build omap_device for %s:%s.\n",
+ + 			dev_name, oh->name);
+ + 		return PTR_ERR(pdev);
+ + 	}
+ + 	return 0;
+ + }
+ + #endif
+ + 
+ + #if defined(CONFIG_CRYPTO_DEV_OMAP4_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP4_SHAM_MODULE)
+ + static void __init omap_init_sham(void)
+ + {
+ + 	struct omap_hwmod *oh;
+ + 	struct platform_device *pdev;
+ + 
+ + 	oh = omap_hwmod_lookup("sha0");
+ + 	if (!oh)
+ + 		return;
+ + 
+ + 	pdev = omap_device_build("omap4-sham", -1, oh, NULL, 0, NULL, 0, 0);
+ + 	WARN(IS_ERR(pdev), "Can't build omap_device for omap-sham\n");
+ + }
+ + #else
+ + static inline void omap_init_sham(void) { }
+ + #endif
+ + #if defined(CONFIG_CRYPTO_DEV_OMAP4_AES) || defined(CONFIG_CRYPTO_DEV_OMAP4_AES_MODULE)
+ + static void __init omap_init_aes(void)
+ + {
+ + 	struct omap_hwmod *oh;
+ + 	struct platform_device *pdev;
+ + 
+ + 	oh = omap_hwmod_lookup("aes0");
+ + 	if (!oh)
+ + 		return;
+ + 
+ + 	pdev = omap_device_build("omap4-aes", -1, oh, NULL, 0, NULL, 0, 0);
+ + 	WARN(IS_ERR(pdev), "Can't build omap_device for omap-aes\n");
+ + }
+ + #else
+ + static inline void omap_init_aes(void) { }
+ + #endif
+ + 
+ + 
+ + /*-------------------------------------------------------------------------*/
+ + 
+ + #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
+ + #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430)
+ + #define OMAP_HDQ_BASE	0x480B2000
+ + #endif
+ + static struct resource omap_hdq_resources[] = {
+ + 	{
+ + 		.start		= OMAP_HDQ_BASE,
+ + 		.end		= OMAP_HDQ_BASE + 0x1C,
+ + 		.flags		= IORESOURCE_MEM,
+ + 	},
+ + 	{
+ + 		.start		= INT_24XX_HDQ_IRQ,
+ + 		.flags		= IORESOURCE_IRQ,
+ + 	},
+ + };
+ + static struct platform_device omap_hdq_dev = {
+ + 	.name = "omap_hdq",
+ + 	.id = 0,
+ + 	.dev = {
+ + 		.platform_data = NULL,
+ + 	},
+ + 	.num_resources	= ARRAY_SIZE(omap_hdq_resources),
+ + 	.resource	= omap_hdq_resources,
+ + };
+ + static inline void omap_hdq_init(void)
+ + {
+ + 	(void) platform_device_register(&omap_hdq_dev);
+ + }
+ + #else
+ + static inline void omap_hdq_init(void) {}
+ + #endif
+ + 
+ + /*---------------------------------------------------------------------------*/
+ + 
+ + #if defined(CONFIG_VIDEO_OMAP2_VOUT) || \
+ + 	defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE)
+ + #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
+ + static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = {
+ + };
+ + #else
+ + static struct resource omap_vout_resource[2] = {
+ + };
+ + #endif
+ + 
+ + static struct platform_device omap_vout_device = {
+ + 	.name		= "omap_vout",
+ + 	.num_resources	= ARRAY_SIZE(omap_vout_resource),
+ + 	.resource 	= &omap_vout_resource[0],
+ + 	.id		= -1,
+ + };
+ + static void omap_init_vout(void)
+ + {
+ + 	if (platform_device_register(&omap_vout_device) < 0)
+ + 		printk(KERN_ERR "Unable to register OMAP-VOUT device\n");
+ + }
+ + #else
+ + static inline void omap_init_vout(void) {}
+ + #endif
+ + 
+ + #if defined(CONFIG_SOC_OMAPAM33XX) && defined(CONFIG_OMAP3_EDMA)
+ + 
+ + #define AM33XX_SCM_BASE_EDMA		0x00000f90
+ + 
+ + static const s16 am33xx_dma_rsv_chans[][2] = {
+ + 	/* (offset, number) */
+ + 	{0, 2},
+ + 	{14, 2},
+ + 	{26, 6},
+ + 	{48, 4},
+ + 	{56, 8},
+ + 	{-1, -1}
+ + };
+ + 
+ + static const s16 am33xx_dma_rsv_slots[][2] = {
+ + 	/* (offset, number) */
+ + 	{0, 2},
+ + 	{14, 2},
+ + 	{26, 6},
+ + 	{48, 4},
+ + 	{56, 8},
+ + 	{64, 127},
+ + 	{-1, -1}
+ + };
+ + 
+ + /* Three Transfer Controllers on AM33XX */
+ + static const s8 am33xx_queue_tc_mapping[][2] = {
+ + 	/* {event queue no, TC no} */
+ + 	{0, 0},
+ + 	{1, 1},
+ + 	{2, 2},
+ + 	{-1, -1}
+ + };
+ + 
+ + static const s8 am33xx_queue_priority_mapping[][2] = {
+ + 	/* {event queue no, Priority} */
+ + 	{0, 0},
+ + 	{1, 1},
+ + 	{2, 2},
+ + 	{-1, -1}
+ + };
+ + 
+ + static struct event_to_channel_map am33xx_xbar_event_mapping[] = {
+ + 	/* {xbar event no, Channel} */
+ + 	{1, 12},	/* SDTXEVT1 -> MMCHS2 */
+ + 	{2, 13},	/* SDRXEVT1 -> MMCHS2 */
+ + 	{3, -1},
+ + 	{4, -1},
+ + 	{5, -1},
+ + 	{6, -1},
+ + 	{7, -1},
+ + 	{8, -1},
+ + 	{9, -1},
+ + 	{10, -1},
+ + 	{11, -1},
+ + 	{12, -1},
+ + 	{13, -1},
+ + 	{14, -1},
+ + 	{15, -1},
+ + 	{16, -1},
+ + 	{17, -1},
+ + 	{18, -1},
+ + 	{19, -1},
+ + 	{20, -1},
+ + 	{21, -1},
+ + 	{22, -1},
+ + 	{23, -1},
+ + 	{24, -1},
+ + 	{25, -1},
+ + 	{26, -1},
+ + 	{27, -1},
+ + 	{28, -1},
+ + 	{29, -1},
+ + 	{30, -1},
+ + 	{31, -1},
+ + 	{-1, -1}
+ + };
+ + 
+ + /**
+ +  * map_xbar_event_to_channel - maps a crossbar event to a DMA channel
+ +  * according to the configuration provided
+ +  * @event: the event number for which mapping is required
+ +  * @channel: channel being activated
+ +  * @xbar_event_mapping: array that has the event to channel map
+ +  *
+ +  * Events that are routed by default are not mapped. Only events that
+ +  * are crossbar mapped are routed to available channels according to
+ +  * the configuration provided
+ +  *
+ +  * Returns zero on success, else negative errno.
+ +  */
+ + int map_xbar_event_to_channel(unsigned int event, unsigned int *channel,
+ + 			struct event_to_channel_map *xbar_event_mapping)
+ + {
+ + 	unsigned int ctrl = 0;
+ + 	unsigned int xbar_evt_no = 0;
+ + 	unsigned int val = 0;
+ + 	unsigned int offset = 0;
+ + 	unsigned int mask = 0;
+ + 
+ + 	ctrl = EDMA_CTLR(event);
+ + 	xbar_evt_no = event - (edma_cc[ctrl]->num_channels);
+ + 
+ + 	if (event < edma_cc[ctrl]->num_channels) {
+ + 		*channel = event;
+ + 	} else if (event < edma_cc[ctrl]->num_events) {
+ + 		*channel = xbar_event_mapping[xbar_evt_no].channel_no;
+ + 		/* confirm the range */
+ + 		if (*channel < EDMA_MAX_DMACH)
+ + 			clear_bit(*channel, edma_cc[ctrl]->edma_unused);
+ + 		offset = (*channel)/4;
+ + 		offset *= 4;
+ + 		val = (unsigned int)__raw_readl(AM33XX_CTRL_REGADDR(
+ + 					AM33XX_SCM_BASE_EDMA + offset));
+ + 		mask = *channel & 0x3;
+ + 		mask <<= 3;
+ + 		val &= ~(0xFF << mask);
+ + 		val |= xbar_event_mapping[xbar_evt_no].xbar_event_no << mask;
+ + 		__raw_writel(val,
+ + 			AM33XX_CTRL_REGADDR(AM33XX_SCM_BASE_EDMA + offset));
+ + 		return 0;
+ + 	} else {
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static struct edma_soc_info am33xx_edma_info[] = {
+ + 	{
+ + 		.n_channel		= 64,
+ + 		.n_region		= 4,
+ + 		.n_slot			= 256,
+ + 		.n_tc			= 3,
+ + 		.n_cc			= 1,
+ + 		.rsv_chans		= am33xx_dma_rsv_chans,
+ + 		.rsv_slots		= am33xx_dma_rsv_slots,
+ + 		.queue_tc_mapping	= am33xx_queue_tc_mapping,
+ + 		.queue_priority_mapping	= am33xx_queue_priority_mapping,
+ + 		.is_xbar		= 1,
+ + 		.n_events		= 95,
+ + 		.xbar_event_mapping	= am33xx_xbar_event_mapping,
+ + 		.map_xbar_channel	= map_xbar_event_to_channel,
+ + 	},
+ + };
+ + 
+ + static int __init am33xx_register_edma(void)
+ + {
+ + 	int i, l;
+ + 	struct omap_hwmod *oh[4];
+ + 	struct platform_device *pdev;
+ + 	struct edma_soc_info *pdata = am33xx_edma_info;
+ + 	char oh_name[8];
+ + 
+ + 	oh[0] = omap_hwmod_lookup("tpcc");
+ + 	if (!oh[0]) {
+ + 		pr_err("could not look up %s\n", "tpcc");
+ + 		return -ENODEV;
+ + 	}
+ + 
+ + 	for (i = 0; i < 3; i++) {
+ + 		l = snprintf(oh_name, 8, "tptc%d", i);
+ + 
+ + 		oh[i+1] = omap_hwmod_lookup(oh_name);
+ + 		if (!oh[i+1]) {
+ + 			pr_err("could not look up %s\n", oh_name);
+ + 			return -ENODEV;
+ + 		}
+ + 	}
+ + 
+ + 	pdev = omap_device_build_ss("edma", 0, oh, 4, pdata, sizeof(*pdata),
+ + 								NULL, 0, 0);
+ + 
+ + 	WARN(IS_ERR(pdev), "could not build omap_device for edma\n");
+ + 
+ + 	return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
+ + 
+ + }
+ + 
+ + #else
+ + static inline void am33xx_register_edma(void) {}
+ + #endif
+ + 
+ + #if defined (CONFIG_SOC_OMAPAM33XX)
+ + struct uio_pruss_pdata am335x_pruss_uio_pdata = {
+ + 	.pintc_base	= 0x20000,
+ + };
+ + 
+ + static struct resource am335x_pruss_resources[] = {
+ + 	{
+ + 		.start	= AM33XX_ICSS_BASE,
+ + 		.end	= AM33XX_ICSS_BASE + AM33XX_ICSS_LEN,
+ + 		.flags	= IORESOURCE_MEM,
+ + 	},
+ + 	{
+ + 		.start	= AM33XX_IRQ_ICSS0_0,
+ + 		.end	= AM33XX_IRQ_ICSS0_0,
+ + 		.flags	= IORESOURCE_IRQ,
+ + 	},
+ + 	{
+ + 		.start	= AM33XX_IRQ_ICSS0_1,
+ + 		.end	= AM33XX_IRQ_ICSS0_1,
+ + 		.flags	= IORESOURCE_IRQ,
+ + 	},
+ + 	{
+ + 		.start	= AM33XX_IRQ_ICSS0_2,
+ + 		.end	= AM33XX_IRQ_ICSS0_2,
+ + 		.flags	= IORESOURCE_IRQ,
+ + 	},
+ + 	{
+ + 		.start	= AM33XX_IRQ_ICSS0_3,
+ + 		.end	= AM33XX_IRQ_ICSS0_3,
+ + 		.flags	= IORESOURCE_IRQ,
+ + 	},
+ + 	{
+ + 		.start	= AM33XX_IRQ_ICSS0_4,
+ + 		.end	= AM33XX_IRQ_ICSS0_4,
+ + 		.flags	= IORESOURCE_IRQ,
+ + 	},
+ + 	{
+ + 		.start	= AM33XX_IRQ_ICSS0_5,
+ + 		.end	= AM33XX_IRQ_ICSS0_5,
+ + 		.flags	= IORESOURCE_IRQ,
+ + 	},
+ + 	{
+ + 		.start	= AM33XX_IRQ_ICSS0_6,
+ + 		.end	= AM33XX_IRQ_ICSS0_6,
+ + 		.flags	= IORESOURCE_IRQ,
+ + 	},
+ + 	{
+ + 		.start	= AM33XX_IRQ_ICSS0_7,
+ + 		.end	= AM33XX_IRQ_ICSS0_7,
+ + 		.flags	= IORESOURCE_IRQ,
+ + 	},
+ + };
+ + 
+ + static struct platform_device am335x_pruss_uio_dev = {
+ + 	.name		= "pruss_uio",
+ + 	.id		= -1,
+ + 	.num_resources	= ARRAY_SIZE(am335x_pruss_resources),
+ + 	.resource	= am335x_pruss_resources,
+ + 	.dev	 =	{
+ + 		.coherent_dma_mask = 0xffffffff,
+ + 	}
+ + };
+ + 
+ + int __init am335x_register_pruss_uio(struct uio_pruss_pdata *config)
+ + {
+ + 	am335x_pruss_uio_dev.dev.platform_data = config;
+ + 	return platform_device_register(&am335x_pruss_uio_dev);
+ + }
+ + 
+ + static struct platform_device am335x_sgx = {
+ + 	.name	= "sgx",
+ + 	.id	= -1,
+ + };
+ + 
+ + #endif
+ + 
+ + #ifdef CONFIG_AM33XX_SMARTREFLEX
+ + 
+ + /* smartreflex platform data */
+ + 
+ + /* The values below are based upon silicon characterization data.
+ +  * Each OPP and sensor combination potentially has different values.
+ +  * The values of ERR2VOLT_GAIN and ERR_MIN_LIMIT also change based on
+ +  * the PMIC step size.  Values have been given to cover the AM335 EVM
+ +  * (12.5mV step) and the Beaglebone (25mV step).  If the step
+ +  * size changes, you should update these values, and don't forget to
+ +  * change the step size in the platform data structure, am33xx_sr_pdata.
+ +  */
+ + 
+ + #define AM33XX_SR0_OPP50_CNTRL_OFFSET          0x07B8
+ + #define AM33XX_SR0_OPP50_EVM_ERR2VOLT_GAIN     0xC
+ + #define AM33XX_SR0_OPP50_EVM_ERR_MIN_LIMIT     0xF5
+ + #define AM33XX_SR0_OPP50_BB_ERR2VOLT_GAIN      0x6
+ + #define AM33XX_SR0_OPP50_BB_ERR_MIN_LIMIT      0xEA
+ + #define AM33XX_SR0_OPP50_ERR_MAX_LIMIT         0x2
+ + #define AM33XX_SR0_OPP50_ERR_WEIGHT             0x4
+ + #define AM33XX_SR0_OPP50_MARGIN                 0
+ + 
+ + #define AM33XX_SR0_OPP100_CNTRL_OFFSET         0x07BC
+ + #define AM33XX_SR0_OPP100_EVM_ERR2VOLT_GAIN     0x12
+ + #define AM33XX_SR0_OPP100_EVM_ERR_MIN_LIMIT    0xF8
+ + #define AM33XX_SR0_OPP100_BB_ERR2VOLT_GAIN      0x9
+ + #define AM33XX_SR0_OPP100_BB_ERR_MIN_LIMIT     0xF1
+ + #define AM33XX_SR0_OPP100_ERR_MAX_LIMIT                0x2
+ + #define AM33XX_SR0_OPP100_ERR_WEIGHT            0x4
+ + #define AM33XX_SR0_OPP100_MARGIN                0
+ + 
+ + #define AM33XX_SR1_OPP50_CNTRL_OFFSET          0x0770
+ + #define AM33XX_SR1_OPP50_EVM_ERR2VOLT_GAIN     0x5
+ + #define AM33XX_SR1_OPP50_EVM_ERR_MIN_LIMIT     0xE6
+ + #define AM33XX_SR1_OPP50_BB_ERR2VOLT_GAIN      0x2
+ + #define AM33XX_SR1_OPP50_BB_ERR_MIN_LIMIT      0xC0
+ + #define AM33XX_SR1_OPP50_ERR_MAX_LIMIT         0x2
+ + #define AM33XX_SR1_OPP50_ERR_WEIGHT             0x4
+ + #define AM33XX_SR1_OPP50_MARGIN                 0
+ + 
+ + #define AM33XX_SR1_OPP100_CNTRL_OFFSET         0x0774
+ + #define AM33XX_SR1_OPP100_EVM_ERR2VOLT_GAIN    0x8
+ + #define AM33XX_SR1_OPP100_EVM_ERR_MIN_LIMIT    0xF0
+ + #define AM33XX_SR1_OPP100_BB_ERR2VOLT_GAIN     0x4
+ + #define AM33XX_SR1_OPP100_BB_ERR_MIN_LIMIT     0xDF
+ + #define AM33XX_SR1_OPP100_ERR_MAX_LIMIT                0x2
+ + #define AM33XX_SR1_OPP100_ERR_WEIGHT            0x4
+ + #define AM33XX_SR1_OPP100_MARGIN                0
+ + 
+ + #define AM33XX_SR1_OPP120_CNTRL_OFFSET         0x0778
+ + #define AM33XX_SR1_OPP120_EVM_ERR2VOLT_GAIN    0xB
+ + #define AM33XX_SR1_OPP120_EVM_ERR_MIN_LIMIT    0xF4
+ + #define AM33XX_SR1_OPP120_BB_ERR2VOLT_GAIN     0x5
+ + #define AM33XX_SR1_OPP120_BB_ERR_MIN_LIMIT     0xE6
+ + #define AM33XX_SR1_OPP120_ERR_MAX_LIMIT                0x2
+ + #define AM33XX_SR1_OPP120_ERR_WEIGHT            0x4
+ + #define AM33XX_SR1_OPP120_MARGIN                0
+ + 
+ + #define AM33XX_SR1_OPPTURBO_CNTRL_OFFSET        0x077C
+ + #define AM33XX_SR1_OPPTURBO_EVM_ERR2VOLT_GAIN  0xC
+ + #define AM33XX_SR1_OPPTURBO_EVM_ERR_MIN_LIMIT  0xF5
+ + #define AM33XX_SR1_OPPTURBO_BB_ERR2VOLT_GAIN   0x6
+ + #define AM33XX_SR1_OPPTURBO_BB_ERR_MIN_LIMIT   0xEA
+ + #define AM33XX_SR1_OPPTURBO_ERR_MAX_LIMIT      0x2
+ + #define AM33XX_SR1_OPPTURBO_ERR_WEIGHT          0x4
+ + #define AM33XX_SR1_OPPTURBO_MARGIN              0
+ + 
+ + static struct am33xx_sr_opp_data sr1_opp_data[] = {
+ +         {
+ +                 .efuse_offs    = AM33XX_SR1_OPP50_CNTRL_OFFSET,
+ +                .e2v_gain       = AM33XX_SR1_OPP50_EVM_ERR2VOLT_GAIN,
+ +                .err_minlimit   = AM33XX_SR1_OPP50_EVM_ERR_MIN_LIMIT,
+ +                .err_maxlimit   = AM33XX_SR1_OPP50_ERR_MAX_LIMIT,
+ +                .err_weight     = AM33XX_SR1_OPP50_ERR_WEIGHT,
+ +                 .margin         = AM33XX_SR1_OPP50_MARGIN,
+ +                 .nominal_volt   = AM33XX_VDD_MPU_OPP50_UV,
+ +                 .frequency      = AM33XX_VDD_MPU_275_FREQ,
+ +         },
+ +         {
+ +                 .efuse_offs    = AM33XX_SR1_OPP100_CNTRL_OFFSET,
+ +                .e2v_gain       = AM33XX_SR1_OPP100_EVM_ERR2VOLT_GAIN,
+ +                .err_minlimit   = AM33XX_SR1_OPP100_EVM_ERR_MIN_LIMIT,
+ +                .err_maxlimit   = AM33XX_SR1_OPP100_ERR_MAX_LIMIT,
+ +                .err_weight     = AM33XX_SR1_OPP100_ERR_WEIGHT,
+ +                 .margin         = AM33XX_SR1_OPP100_MARGIN,
+ +                 .nominal_volt   = AM33XX_VDD_MPU_OPP100_UV,
+ +                 .frequency      = AM33XX_VDD_MPU_500_FREQ,
+ +         },
+ +         {
+ +                 .efuse_offs    = AM33XX_SR1_OPP120_CNTRL_OFFSET,
+ +                .e2v_gain       = AM33XX_SR1_OPP120_EVM_ERR2VOLT_GAIN,
+ +                .err_minlimit   = AM33XX_SR1_OPP120_EVM_ERR_MIN_LIMIT,
+ +                .err_maxlimit   = AM33XX_SR1_OPP120_ERR_MAX_LIMIT,
+ +                .err_weight     = AM33XX_SR1_OPP120_ERR_WEIGHT,
+ +                 .margin         = AM33XX_SR1_OPP120_MARGIN,
+ +                 .nominal_volt   = AM33XX_VDD_MPU_OPP120_UV,
+ +                 .frequency      = AM33XX_VDD_MPU_600_FREQ,
+ +         },
+ +         {
+ +                 .efuse_offs    = AM33XX_SR1_OPPTURBO_CNTRL_OFFSET,
+ +                .e2v_gain       = AM33XX_SR1_OPPTURBO_EVM_ERR2VOLT_GAIN,
+ +                .err_minlimit   = AM33XX_SR1_OPPTURBO_EVM_ERR_MIN_LIMIT,
+ +                .err_maxlimit   = AM33XX_SR1_OPPTURBO_ERR_MAX_LIMIT,
+ +                .err_weight     = AM33XX_SR1_OPPTURBO_ERR_WEIGHT,
+ +                 .margin         = AM33XX_SR1_OPPTURBO_MARGIN,
+ +                 .nominal_volt   = AM33XX_VDD_MPU_OPPTURBO_UV,
+ +                 .frequency      = AM33XX_VDD_MPU_720_FREQ,
+ +         },
+ + };
+ + 
+ + static struct am33xx_sr_opp_data sr0_opp_data[] = {
+ +         {
+ +                 .efuse_offs    = AM33XX_SR0_OPP50_CNTRL_OFFSET,
+ +                .e2v_gain       = AM33XX_SR0_OPP50_EVM_ERR2VOLT_GAIN,
+ +                .err_minlimit   = AM33XX_SR0_OPP50_EVM_ERR_MIN_LIMIT,
+ +                .err_maxlimit   = AM33XX_SR0_OPP50_ERR_MAX_LIMIT,
+ +                .err_weight     = AM33XX_SR0_OPP50_ERR_WEIGHT,
+ +                 .margin         = AM33XX_SR0_OPP50_MARGIN,
+ +                 .nominal_volt   = AM33XX_VDD_CORE_OPP50_UV,
+ +         },
+ +         {
+ +                 .efuse_offs    = AM33XX_SR0_OPP100_CNTRL_OFFSET,
+ +                .e2v_gain       = AM33XX_SR0_OPP100_EVM_ERR2VOLT_GAIN,
+ +                .err_minlimit   = AM33XX_SR0_OPP100_EVM_ERR_MIN_LIMIT,
+ +                .err_maxlimit   = AM33XX_SR0_OPP100_ERR_MAX_LIMIT,
+ +                .err_weight     = AM33XX_SR0_OPP100_ERR_WEIGHT,
+ +                 .margin         = AM33XX_SR0_OPP100_MARGIN,
+ +                 .nominal_volt   = AM33XX_VDD_CORE_OPP100_UV,
+ +         },
+ + };
+ + 
+ + static struct am33xx_sr_sdata sr_sensor_data[] = {
+ +        {
+ +                 .sr_opp_data    = sr0_opp_data,
+ +                 /* note that OPP50 is NOT used in Linux kernel for AM335x */
+ +                 .no_of_opps     = 0x2,
+ +                 .default_opp    = 0x1,
+ +                .senn_mod       = 0x1,
+ +                .senp_mod       = 0x1,
+ +        },
+ +        {
+ +                .sr_opp_data    = sr1_opp_data,
+ +                 /* the opp data below should be determined
+ +                    dynamically during SR probe */
+ +                 .no_of_opps     = 0x4,
+ +                 .default_opp    = 0x3,
+ +                .senn_mod       = 0x1,
+ +                .senp_mod       = 0x1,
+ +        },
+ + };
+ + 
+ + static struct am33xx_sr_platform_data am33xx_sr_pdata = {
+ +        .vd_name[0]             = "vdd_core",
+ +         .vd_name[1]             = "vdd_mpu",
+ +        .ip_type                = 2,
+ +         .irq_delay              = 1000,
+ +        .no_of_vds              = 2,
+ +        .no_of_sens             = ARRAY_SIZE(sr_sensor_data),
+ +        .vstep_size_uv          = 12500,
+ +        .enable_on_init         = true,
+ +        .sr_sdata               = sr_sensor_data,
+ + };
+ + 
+ + static struct resource am33xx_sr_resources[] = {
+ +        {
+ +                .name   =       "smartreflex0",
+ +                .start  =       AM33XX_SR0_BASE,
+ +                .end    =       AM33XX_SR0_BASE + SZ_4K - 1,
+ +                .flags  =       IORESOURCE_MEM,
+ +        },
+ +        {
+ +                .name   =       "smartreflex0",
+ +                .start  =       AM33XX_IRQ_SMARTREFLEX0,
+ +                .end    =       AM33XX_IRQ_SMARTREFLEX0,
+ +                .flags  =       IORESOURCE_IRQ,
+ +        },
+ +        {
+ +                .name   =       "smartreflex1",
+ +                .start  =       AM33XX_SR1_BASE,
+ +                .end    =       AM33XX_SR1_BASE + SZ_4K - 1,
+ +                .flags  =       IORESOURCE_MEM,
+ +        },
+ +        {
+ +                .name   =       "smartreflex1",
+ +                .start  =       AM33XX_IRQ_SMARTREFLEX1,
+ +                .end    =       AM33XX_IRQ_SMARTREFLEX1,
+ +                .flags  =       IORESOURCE_IRQ,
+ +        },
+ + };
+ + 
+ + /* VCORE for SR regulator init */
+ + static struct platform_device am33xx_sr_device = {
+ +        .name           = "smartreflex",
+ +        .id             = -1,
+ +        .num_resources  = ARRAY_SIZE(am33xx_sr_resources),
+ +        .resource       = am33xx_sr_resources,
+ +        .dev = {
+ +                .platform_data = &am33xx_sr_pdata,
+ +        },
+ + };
+ + 
+ + void __init am33xx_sr_init(void)
+ + {
+ + 
+ + 	u32 rev, val, max_freq;
+ + 
+ + 	rev = omap_rev();
+ + 	switch (rev) {
+ + 	case AM335X_REV_ES1_0:
+ + 		break;
+ + 	case AM335X_REV_ES2_0:
+ + 	case AM335X_REV_ES2_1:
+ + 	default: /* fallback */
+ + 		/* modify the frequency */
+ + 		sr1_opp_data[0].frequency = AM33XX_VDD_MPU_300_FREQ;
+ + 		sr1_opp_data[1].frequency = AM33XX_VDD_MPU_600_FREQ;
+ + 		sr1_opp_data[2].frequency = AM33XX_VDD_MPU_720_FREQ;
+ + 		sr1_opp_data[3].frequency = AM33XX_VDD_MPU_800_FREQ;
+ + 		break;
+ + 	}
+ +     if (platform_device_register(&am33xx_sr_device))
+ + 		printk(KERN_ERR "failed to register am33xx_sr device\n");
+ + 	else
+ + 		printk(KERN_INFO "registered am33xx_sr device\n");
+ + }
+ + #else
+ + inline void am33xx_sr_init(void) {}
+ + #endif
+ + 
+ + /*-------------------------------------------------------------------------*/
+ + 
+ + static int __init omap2_init_devices(void)
+ + {
+ + 	/*
+ + 	 * please keep these calls, and their implementations above,
+ + 	 * in alphabetical order so they're easier to sort through.
+ + 	 */
+ + 	omap_init_mcpdm();
+ + 	omap_init_dmic();
+ + 	omap_init_mbox();
+ + 	omap_init_mcspi();
+ + 	omap_hdq_init();
+ + 	omap_init_sti();
+ + 	omap_init_sham();
+ + 	omap_init_aes();
+ + 	omap_init_vout();
+ + 	am33xx_register_edma();
+ + 
+ + #if defined (CONFIG_SOC_OMAPAM33XX)
+ + 	am335x_register_pruss_uio(&am335x_pruss_uio_pdata);
+ + 	if (omap3_has_sgx())
+ + 		platform_device_register(&am335x_sgx);
+ + #endif
+ + #ifdef CONFIG_CKB_3352_AUDIO
+ + 	am335x_register_mcasp();
+ + 	am33xx_init_pcm();
+ + #endif
+ + 	return 0;
+ + }
+ + arch_initcall(omap2_init_devices);
+ + 
+ + #define AM33XX_EMAC_MDIO_FREQ		(1000000)
+ + /* Port Vlan IDs for Dual Mac Mode */
+ + #define CPSW_PORT_VLAN_SLAVE_0		2
+ + #define CPSW_PORT_VLAN_SLAVE_1		3
+ + 
+ + /* TODO : Verify the offsets */
+ + static struct cpsw_slave_data am33xx_cpsw_slaves = {
+ + 		.slave_reg_ofs  = 0x200,
+ + 		.sliver_reg_ofs = 0xd80,
+ + 		.phy_id		= "0:00",
+ + 		.dual_emac_reserved_vlan = CPSW_PORT_VLAN_SLAVE_0,
+ + };
+ + 
+ + static struct cpsw_platform_data am33xx_cpsw_pdata = {
+ + 	.ss_reg_ofs		= 0x1200,
+ + 	.channels		= 8,
+ + 	.cpdma_reg_ofs		= 0x800,
+ + 	.slaves			= 1,
+ + 	.slave_data		= &am33xx_cpsw_slaves,
+ + 	.ale_reg_ofs		= 0xd00,
+ + 	.ale_entries		= 1024,
+ + 	.host_port_reg_ofs      = 0x108,
+ + 	.hw_stats_reg_ofs       = 0x900,
+ + 	.cpts_reg_ofs		= 0xc00,
+ + 	.cpts_clock_mult	= 0x80000000,
+ + 	.cpts_clock_shift	= 29,
+ + 	.bd_ram_ofs		= 0x2000,
+ + 	.bd_ram_size		= SZ_8K,
+ + 	.rx_descs               = 64,
+ + 	.mac_control            = BIT(5), /* MIIEN */
+ + 	.gigabit_en		= 1,
+ + 	.host_port_num		= 0,
+ + 	.no_bd_ram		= false,
+ + 	.version		= CPSW_VERSION_2,
+ + };
+ + 
+ + static struct mdio_platform_data am33xx_cpsw_mdiopdata = {
+ + 	.bus_freq       = AM33XX_EMAC_MDIO_FREQ,
+ + };
+ + 
+ + int am33xx_cpsw_init(enum am33xx_cpsw_mac_mode mode, unsigned char *mac_id, void (*save_mac_addr) (char *))
+ + {
+ + 	struct omap_hwmod *oh;
+ + 	struct platform_device *pdev;
+ + 	u32 gmii_sel;
+ + 	u32 i;
+ + 
+ + 	/* Read MACID0 from eeprom */
+ + 	for (i = 0; i < ETH_ALEN; i++)
+ + 		am33xx_cpsw_slaves.mac_addr[i] = mac_id[i];
+ + 	
+ + 	switch (mode) {
+ + 	case AM33XX_CPSW_MODE_MII:
+ + 		gmii_sel = AM33XX_MII_MODE_EN;
+ + 		break;
+ + 	case AM33XX_CPSW_MODE_RMII:
+ + 		gmii_sel = AM33XX_RMII_MODE_EN;
+ + 		break;
+ + 	case AM33XX_CPSW_MODE_RGMII:
+ + 		gmii_sel = AM33XX_RGMII_MODE_EN;
+ + 		break;
+ + 	default:
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	writel(gmii_sel, AM33XX_CTRL_REGADDR(AM33XX_CONTROL_GMII_SEL_OFFSET));
+ + 
+ + 	memcpy(am33xx_cpsw_pdata.mac_addr,
+ + 			am33xx_cpsw_slaves.mac_addr, ETH_ALEN);
+ + 
+ + 	am33xx_cpsw_pdata.save_mac_addr = save_mac_addr;
+ + 
+ + 	oh = omap_hwmod_lookup("mdio");
+ + 	if (!oh) {
+ + 		pr_err("could not find cpgmac0 hwmod data\n");
+ + 		return -ENODEV;
+ + 	}
+ + 
+ + 	pdev = omap_device_build("davinci_mdio", 0, oh, &am33xx_cpsw_mdiopdata,
+ + 			sizeof(am33xx_cpsw_mdiopdata), NULL, 0, 0);
+ + 	if (IS_ERR(pdev))
+ + 		pr_err("could not build omap_device for cpsw\n");
+ + 
+ + 	oh = omap_hwmod_lookup("cpgmac0");
+ + 	if (!oh) {
+ + 		pr_err("could not find cpgmac0 hwmod data\n");
+ + 		return -ENODEV;
+ + 	}
+ + 
+ + 	pdev = omap_device_build("cpsw", -1, oh, &am33xx_cpsw_pdata,
+ + 			sizeof(am33xx_cpsw_pdata), NULL, 0, 0);
+ + 	if (IS_ERR(pdev))
+ + 		pr_err("could not build omap_device for cpsw\n");
+ + 
+ + 	return 0;
+ + }
+ + 
+ + #define AM33XX_DCAN_NUM_MSG_OBJS		64
+ + #define AM33XX_DCAN_RAMINIT_OFFSET		0x644
+ + #define AM33XX_DCAN_RAMINIT_START(n)		(0x1 << n)
+ + 
+ + static void d_can_hw_raminit(unsigned int instance, unsigned int enable)
+ + {
+ + 	u32 val;
+ + 
+ + 	/* Read the value */
+ + 	val = readl(AM33XX_CTRL_REGADDR(AM33XX_DCAN_RAMINIT_OFFSET));
+ + 	if (enable) {
+ + 		/* Set to "1" */
+ + 		val &= ~AM33XX_DCAN_RAMINIT_START(instance);
+ + 		val |= AM33XX_DCAN_RAMINIT_START(instance);
+ + 		writel(val, AM33XX_CTRL_REGADDR(AM33XX_DCAN_RAMINIT_OFFSET));
+ + 	} else {
+ + 		/* Set to "0" */
+ + 		val &= ~AM33XX_DCAN_RAMINIT_START(instance);
+ + 		writel(val, AM33XX_CTRL_REGADDR(AM33XX_DCAN_RAMINIT_OFFSET));
+ + 	}
+ + }
+ + 
+ + /* dcan dev_attr */
+ + static struct d_can_platform_data am33xx_dcan_info = {
+ + 	.num_of_msg_objs	= AM33XX_DCAN_NUM_MSG_OBJS,
+ + 	.ram_init		= d_can_hw_raminit,
+ + 	.dma_support		= false,
+ + };
+ + 
+ + void am33xx_d_can_init(unsigned int instance)
+ + {
+ + 	struct omap_hwmod *oh;
+ + 	struct platform_device *pdev;
+ + 	char oh_name[L3_MODULES_MAX_LEN];
+ + 
+ + 	/* Copy string name to oh_name buffer */
+ + 	snprintf(oh_name, L3_MODULES_MAX_LEN, "d_can%d", instance);
+ + 
+ + 	oh = omap_hwmod_lookup(oh_name);
+ + 	if (!oh) {
+ + 		pr_err("could not find %s hwmod data\n", oh_name);
+ + 		return;
+ + 	}
+ + 
+ + 	pdev = omap_device_build("d_can", instance, oh, &am33xx_dcan_info,
+ + 			sizeof(am33xx_dcan_info), NULL, 0, 0);
+ + 	if (IS_ERR(pdev))
+ + 		pr_err("could not build omap_device for %s\n", oh_name);
+ + }
+ + 
+ + #if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
+ + static int __init omap_init_wdt(void)
+ + {
+ + 	int id = -1;
+ + 	struct platform_device *pdev;
+ + 	struct omap_hwmod *oh;
+ + 	char *oh_name = "wd_timer2";
+ + 	char *dev_name = "omap_wdt";
+ + 
+ + 	oh = omap_hwmod_lookup(oh_name);
+ + 	if (!oh) {
+ + 		pr_err("Could not look up wd_timer%d hwmod\n", id);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	pdev = omap_device_build(dev_name, id, oh, NULL, 0, NULL, 0, 0);
+ + 	WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
+ + 				dev_name, oh->name);
+ + 	return 0;
+ + }
+ + subsys_initcall(omap_init_wdt);
+ + #endif
+ + 
+ + int __init omap_init_gpmc(struct gpmc_devices_info *pdata, int pdata_len)
+ + {
+ + 	struct omap_hwmod *oh;
+ + 	struct platform_device *pdev;
+ + 	char *name = "omap-gpmc";
+ + 	char *oh_name = "gpmc";
+ + 
+ + 	oh = omap_hwmod_lookup(oh_name);
+ + 	if (!oh) {
+ + 		pr_err("Could not look up %s\n", oh_name);
+ + 		return -ENODEV;
+ + 	}
+ + 
+ + 	pdev = omap_device_build(name, -1, oh, pdata,
+ + 					pdata_len, NULL, 0, 0);
+ + 	if (IS_ERR(pdev)) {
+ + 		WARN(1, "Can't build omap_device for %s:%s.\n",
+ + 						name, oh->name);
+ + 		return PTR_ERR(pdev);
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ + 
+ + #ifdef CONFIG_CKB_EXTCN_ADC
+ + #include <linux/mfd/ti_tscadc.h>
+ + int __init am33xx_register_mfd_tscadc(struct mfd_tscadc_board *pdata)
+ + {
+ + 	int id = -1;
+ + 	struct platform_device *pdev;
+ + 	struct omap_hwmod *oh;
+ + 	char *oh_name = "adc_tsc";
+ + 	char *dev_name = "ti_tscadc";
+ + 
+ + 	oh = omap_hwmod_lookup(oh_name);
+ + 	if (!oh) {
+ + 		pr_err("Could not look up TSCADC%d hwmod\n", id);
+ + 		return -ENODEV;
+ + 	}
+ + 
+ + 	pdev = omap_device_build(dev_name, id, oh, pdata,
+ + 			sizeof(struct mfd_tscadc_board), NULL, 0, 0);
+ + 
+ + 	WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
+ + 			dev_name, oh->name);
+ + 	return 0;
+ + }
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/devices.h linux-3.2.1/arch/arm/mach-ckb_3352/devices.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/devices.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/devices.h	2014-11-25 13:19:14.977005260 +0900
+ ***************
+ *** 0 ****
+ --- 1,29 ----
+ + /*
+ +  * arch/arm/mach-omap2/devices.h
+ +  *
+ +  * OMAP2 platform device setup/initialization
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; either version 2 of the License, or
+ +  * (at your option) any later version.
+ +  */
+ + 
+ + #ifndef __ARCH_ARM_MACH_OMAP_DEVICES_H
+ + #define __ARCH_ARM_MACH_OMAP_DEVICES_H
+ + 
+ + struct isp_platform_data;
+ + int omap3_init_camera(struct isp_platform_data *pdata);
+ + #if defined(CONFIG_SND_AM335X_SOC_EVM) || defined(CONFIG_SND_AM335X_SOC_EVM_MODULE)
+ + int __init am335x_register_mcasp(struct snd_platform_data *pdata, int ctrl_nr);
+ + #endif
+ + extern int __init am33xx_register_ecap(int id,
+ + 		struct pwmss_platform_data *pdata);
+ + extern int __init am33xx_register_ehrpwm(int id,
+ + 		struct pwmss_platform_data *pdata);
+ + extern int __init omap_init_elm(void);
+ + 
+ + void am33xx_sr_init(void);
+ + void am33xx_d_can_init(unsigned int instance);
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/display.c linux-3.2.1/arch/arm/mach-ckb_3352/display.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/display.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/display.c	2014-11-25 13:19:14.980479929 +0900
+ ***************
+ *** 0 ****
+ --- 1,261 ----
+ + /*
+ +  * OMAP2plus display device setup / initialization.
+ +  *
+ +  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ +  *	Senthilvadivu Guruswamy
+ +  *	Sumit Semwal
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #include <linux/string.h>
+ + #include <linux/kernel.h>
+ + #include <linux/init.h>
+ + #include <linux/platform_device.h>
+ + #include <linux/io.h>
+ + #include <linux/clk.h>
+ + #include <linux/err.h>
+ + #include <linux/delay.h>
+ + 
+ + #include <video/omapdss.h>
+ + #include <plat/omap_hwmod.h>
+ + #include <plat/omap_device.h>
+ + #include <plat/omap-pm.h>
+ + #include "common.h"
+ + 
+ + #include "control.h"
+ + #include "display.h"
+ + 
+ + #define DISPC_CONTROL		0x0040
+ + #define DISPC_CONTROL2		0x0238
+ + #define DISPC_IRQSTATUS		0x0018
+ + 
+ + #define DSS_SYSCONFIG		0x10
+ + #define DSS_SYSSTATUS		0x14
+ + #define DSS_CONTROL		0x40
+ + #define DSS_SDI_CONTROL		0x44
+ + #define DSS_PLL_CONTROL		0x48
+ + 
+ + #define LCD_EN_MASK		(0x1 << 0)
+ + #define DIGIT_EN_MASK		(0x1 << 1)
+ + 
+ + #define FRAMEDONE_IRQ_SHIFT	0
+ + #define EVSYNC_EVEN_IRQ_SHIFT	2
+ + #define EVSYNC_ODD_IRQ_SHIFT	3
+ + #define FRAMEDONE2_IRQ_SHIFT	22
+ + #define FRAMEDONETV_IRQ_SHIFT	24
+ + 
+ + /*
+ +  * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
+ +  *     reset before deciding that something has gone wrong
+ +  */
+ + #define FRAMEDONE_IRQ_TIMEOUT		100
+ + 
+ + static struct platform_device omap_display_device = {
+ + 	.name          = "omapdss",
+ + 	.id            = -1,
+ + 	.dev            = {
+ + 		.platform_data = NULL,
+ + 	},
+ + };
+ + 
+ + struct omap_dss_hwmod_data {
+ + 	const char *oh_name;
+ + 	const char *dev_name;
+ + 	const int id;
+ + };
+ + 
+ + static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initdata = {
+ + 	{ "dss_hdmi", "omapdss_hdmi", -1 },
+ + };
+ + 
+ + static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
+ + {
+ + 	return 0;
+ + }
+ + 
+ + static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
+ + {
+ + }
+ + 
+ + int __init omap_display_init(struct omap_dss_board_info *board_data)
+ + {
+ + 	int r = 0;
+ + 	struct omap_hwmod *oh;
+ + 	struct platform_device *pdev;
+ + 	int i, oh_count;
+ + 	struct omap_display_platform_data pdata;
+ + 	const struct omap_dss_hwmod_data *curr_dss_hwmod;
+ + 
+ + 	memset(&pdata, 0, sizeof(pdata));
+ + 
+ + 	curr_dss_hwmod = omap3_dss_hwmod_data;
+ + 	oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
+ + 	
+ + 	if (board_data->dsi_enable_pads == NULL)
+ + 		board_data->dsi_enable_pads = omap_dsi_enable_pads;
+ + 	if (board_data->dsi_disable_pads == NULL)
+ + 		board_data->dsi_disable_pads = omap_dsi_disable_pads;
+ + 
+ + 	pdata.board_data = board_data;
+ + 	pdata.board_data->get_context_loss_count =
+ + 		omap_pm_get_dev_context_loss_count;
+ + 
+ + 	for (i = 0; i < oh_count; i++) {
+ + 		oh = omap_hwmod_lookup(curr_dss_hwmod[i].oh_name);
+ + 		if (!oh) {
+ + 			pr_err("Could not look up %s\n",
+ + 				curr_dss_hwmod[i].oh_name);
+ + 			return -ENODEV;
+ + 		}
+ + 
+ + 		pdev = omap_device_build(curr_dss_hwmod[i].dev_name,
+ + 				curr_dss_hwmod[i].id, oh, &pdata,
+ + 				sizeof(struct omap_display_platform_data),
+ + 				NULL, 0, 0);
+ + 
+ + 		if (WARN((IS_ERR(pdev)), "Could not build omap_device for %s\n",
+ + 				curr_dss_hwmod[i].oh_name))
+ + 			return -ENODEV;
+ + 	}
+ + 	omap_display_device.dev.platform_data = board_data;
+ + 
+ + 	r = platform_device_register(&omap_display_device);
+ + 	if (r < 0)
+ + 		printk(KERN_ERR "Unable to register OMAP-Display device\n");
+ + 
+ + 	return r;
+ + }
+ + 
+ + static void dispc_disable_outputs(void)
+ + {
+ + 	u32 v, irq_mask = 0;
+ + 	bool lcd_en, digit_en, lcd2_en = false;
+ + 	int i;
+ + 	struct omap_dss_dispc_dev_attr *da;
+ + 	struct omap_hwmod *oh;
+ + 
+ + 	oh = omap_hwmod_lookup("dss_dispc");
+ + 	if (!oh) {
+ + 		WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
+ + 		return;
+ + 	}
+ + 
+ + 	if (!oh->dev_attr) {
+ + 		pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
+ + 		return;
+ + 	}
+ + 
+ + 	da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
+ + 
+ + 	/* store value of LCDENABLE and DIGITENABLE bits */
+ + 	v = omap_hwmod_read(oh, DISPC_CONTROL);
+ + 	lcd_en = v & LCD_EN_MASK;
+ + 	digit_en = v & DIGIT_EN_MASK;
+ + 
+ + 	/* store value of LCDENABLE for LCD2 */
+ + 	if (da->manager_count > 2) {
+ + 		v = omap_hwmod_read(oh, DISPC_CONTROL2);
+ + 		lcd2_en = v & LCD_EN_MASK;
+ + 	}
+ + 
+ + 	if (!(lcd_en | digit_en | lcd2_en))
+ + 		return; /* no managers currently enabled */
+ + 
+ + 	/*
+ + 	 * If any manager was enabled, we need to disable it before
+ + 	 * DSS clocks are disabled or DISPC module is reset
+ + 	 */
+ + 	if (lcd_en)
+ + 		irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;
+ + 
+ + 	if (digit_en) {
+ + 		if (da->has_framedonetv_irq) {
+ + 			irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
+ + 		} else {
+ + 			irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
+ + 				1 << EVSYNC_ODD_IRQ_SHIFT;
+ + 		}
+ + 	}
+ + 
+ + 	if (lcd2_en)
+ + 		irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
+ + 
+ + 	/*
+ + 	 * clear any previous FRAMEDONE, FRAMEDONETV,
+ + 	 * EVSYNC_EVEN/ODD or FRAMEDONE2 interrupts
+ + 	 */
+ + 	omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
+ + 
+ + 	/* disable LCD and TV managers */
+ + 	v = omap_hwmod_read(oh, DISPC_CONTROL);
+ + 	v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
+ + 	omap_hwmod_write(v, oh, DISPC_CONTROL);
+ + 
+ + 	/* disable LCD2 manager */
+ + 	if (da->manager_count > 2) {
+ + 		v = omap_hwmod_read(oh, DISPC_CONTROL2);
+ + 		v &= ~LCD_EN_MASK;
+ + 		omap_hwmod_write(v, oh, DISPC_CONTROL2);
+ + 	}
+ + 
+ + 	i = 0;
+ + 	while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
+ + 	       irq_mask) {
+ + 		i++;
+ + 		if (i > FRAMEDONE_IRQ_TIMEOUT) {
+ + 			pr_err("didn't get FRAMEDONE1/2 or TV interrupt\n");
+ + 			break;
+ + 		}
+ + 		mdelay(1);
+ + 	}
+ + }
+ + 
+ + #define MAX_MODULE_SOFTRESET_WAIT	10000
+ + int omap_dss_reset(struct omap_hwmod *oh)
+ + {
+ + 	struct omap_hwmod_opt_clk *oc;
+ + 	int c = 0;
+ + 	int i, r;
+ + 
+ + 	if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
+ + 		pr_err("dss_core: hwmod data doesn't contain reset data\n");
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
+ + 		if (oc->_clk)
+ + 			clk_enable(oc->_clk);
+ + 
+ + 	dispc_disable_outputs();
+ + 
+ + 	/*
+ + 	 * clear DSS_CONTROL register to switch DSS clock sources to
+ + 	 * PRCM clock, if any
+ + 	 */
+ + 	omap_hwmod_write(0x0, oh, DSS_CONTROL);
+ + 
+ + 	omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
+ + 				& SYSS_RESETDONE_MASK),
+ + 			MAX_MODULE_SOFTRESET_WAIT, c);
+ + 
+ + 	if (c == MAX_MODULE_SOFTRESET_WAIT)
+ + 		pr_warning("dss_core: waiting for reset to finish failed\n");
+ + 	else
+ + 		pr_debug("dss_core: softreset done\n");
+ + 
+ + 	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
+ + 		if (oc->_clk)
+ + 			clk_disable(oc->_clk);
+ + 
+ + 	r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
+ + 
+ + 	return r;
+ + }
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/display.h linux-3.2.1/arch/arm/mach-ckb_3352/display.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/display.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/display.h	2014-11-25 13:19:14.980479929 +0900
+ ***************
+ *** 0 ****
+ --- 1,29 ----
+ + /*
+ +  * display.h - OMAP2+ integration-specific DSS header
+ +  *
+ +  * Copyright (C) 2011 Texas Instruments, Inc.
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify it
+ +  * under the terms of the GNU General Public License version 2 as published by
+ +  * the Free Software Foundation.
+ +  *
+ +  * This program is distributed in the hope that it will be useful, but WITHOUT
+ +  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ +  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ +  * more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License along with
+ +  * this program.  If not, see <http://www.gnu.org/licenses/>.
+ +  */
+ + 
+ + #ifndef __ARCH_ARM_MACH_OMAP2_DISPLAY_H
+ + #define __ARCH_ARM_MACH_OMAP2_DISPLAY_H
+ + 
+ + #include <linux/kernel.h>
+ + 
+ + struct omap_dss_dispc_dev_attr {
+ + 	u8	manager_count;
+ + 	bool	has_framedonetv_irq;
+ + };
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/dma.c linux-3.2.1/arch/arm/mach-ckb_3352/dma.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/dma.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/dma.c	2014-11-25 13:19:14.980479929 +0900
+ ***************
+ *** 0 ****
+ --- 1,283 ----
+ + /*
+ +  * OMAP2+ DMA driver
+ +  *
+ +  * Copyright (C) 2003 - 2008 Nokia Corporation
+ +  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
+ +  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
+ +  * Graphics DMA and LCD DMA graphics tranformations
+ +  * by Imre Deak <imre.deak@nokia.com>
+ +  * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
+ +  * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
+ +  *
+ +  * Copyright (C) 2009 Texas Instruments
+ +  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ +  *
+ +  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ +  * Converted DMA library into platform driver
+ +  *	- G, Manjunath Kondaiah <manjugk@ti.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #include <linux/err.h>
+ + #include <linux/io.h>
+ + #include <linux/slab.h>
+ + #include <linux/module.h>
+ + #include <linux/init.h>
+ + #include <linux/device.h>
+ + 
+ + #include <plat/omap_hwmod.h>
+ + #include <plat/omap_device.h>
+ + #include <plat/dma.h>
+ + 
+ + #define OMAP2_DMA_STRIDE	0x60
+ + 
+ + static u32 errata;
+ + static u8 dma_stride;
+ + 
+ + static struct omap_dma_dev_attr *d;
+ + 
+ + static enum omap_reg_offsets dma_common_ch_start, dma_common_ch_end;
+ + 
+ + static u16 reg_map[] = {
+ + 	[REVISION]		= 0x00,
+ + 	[GCR]			= 0x78,
+ + 	[IRQSTATUS_L0]		= 0x08,
+ + 	[IRQSTATUS_L1]		= 0x0c,
+ + 	[IRQSTATUS_L2]		= 0x10,
+ + 	[IRQSTATUS_L3]		= 0x14,
+ + 	[IRQENABLE_L0]		= 0x18,
+ + 	[IRQENABLE_L1]		= 0x1c,
+ + 	[IRQENABLE_L2]		= 0x20,
+ + 	[IRQENABLE_L3]		= 0x24,
+ + 	[SYSSTATUS]		= 0x28,
+ + 	[OCP_SYSCONFIG]		= 0x2c,
+ + 	[CAPS_0]		= 0x64,
+ + 	[CAPS_2]		= 0x6c,
+ + 	[CAPS_3]		= 0x70,
+ + 	[CAPS_4]		= 0x74,
+ + 
+ + 	/* Common register offsets */
+ + 	[CCR]			= 0x80,
+ + 	[CLNK_CTRL]		= 0x84,
+ + 	[CICR]			= 0x88,
+ + 	[CSR]			= 0x8c,
+ + 	[CSDP]			= 0x90,
+ + 	[CEN]			= 0x94,
+ + 	[CFN]			= 0x98,
+ + 	[CSEI]			= 0xa4,
+ + 	[CSFI]			= 0xa8,
+ + 	[CDEI]			= 0xac,
+ + 	[CDFI]			= 0xb0,
+ + 	[CSAC]			= 0xb4,
+ + 	[CDAC]			= 0xb8,
+ + 
+ + 	/* Channel specific register offsets */
+ + 	[CSSA]			= 0x9c,
+ + 	[CDSA]			= 0xa0,
+ + 	[CCEN]			= 0xbc,
+ + 	[CCFN]			= 0xc0,
+ + 	[COLOR]			= 0xc4,
+ + 
+ + 	/* OMAP4 specific registers */
+ + 	[CDP]			= 0xd0,
+ + 	[CNDP]			= 0xd4,
+ + 	[CCDN]			= 0xd8,
+ + };
+ + 
+ + static void __iomem *dma_base;
+ + static inline void dma_write(u32 val, int reg, int lch)
+ + {
+ + 	u8  stride;
+ + 	u32 offset;
+ + 
+ + 	stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
+ + 	offset = reg_map[reg] + (stride * lch);
+ + 	__raw_writel(val, dma_base + offset);
+ + }
+ + 
+ + static inline u32 dma_read(int reg, int lch)
+ + {
+ + 	u8 stride;
+ + 	u32 offset, val;
+ + 
+ + 	stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
+ + 	offset = reg_map[reg] + (stride * lch);
+ + 	val = __raw_readl(dma_base + offset);
+ + 	return val;
+ + }
+ + 
+ + static inline void omap2_disable_irq_lch(int lch)
+ + {
+ + 	u32 val;
+ + 
+ + 	val = dma_read(IRQENABLE_L0, lch);
+ + 	val &= ~(1 << lch);
+ + 	dma_write(val, IRQENABLE_L0, lch);
+ + }
+ + 
+ + static void omap2_clear_dma(int lch)
+ + {
+ + 	int i = dma_common_ch_start;
+ + 
+ + 	for (; i <= dma_common_ch_end; i += 1)
+ + 		dma_write(0, i, lch);
+ + }
+ + 
+ + static void omap2_show_dma_caps(void)
+ + {
+ + 	u8 revision = dma_read(REVISION, 0) & 0xff;
+ + 	printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
+ + 				revision >> 4, revision & 0xf);
+ + 	return;
+ + }
+ + 
+ + static u32 configure_dma_errata(void)
+ + {
+ + 
+ + 	/*
+ + 	 * Errata applicable for OMAP2430ES1.0 and all omap2420
+ + 	 *
+ + 	 * I.
+ + 	 * Erratum ID: Not Available
+ + 	 * Inter Frame DMA buffering issue DMA will wrongly
+ + 	 * buffer elements if packing and bursting is enabled. This might
+ + 	 * result in data gets stalled in FIFO at the end of the block.
+ + 	 * Workaround: DMA channels must have BUFFERING_DISABLED bit set to
+ + 	 * guarantee no data will stay in the DMA FIFO in case inter frame
+ + 	 * buffering occurs
+ + 	 *
+ + 	 * II.
+ + 	 * Erratum ID: Not Available
+ + 	 * DMA may hang when several channels are used in parallel
+ + 	 * In the following configuration, DMA channel hanging can occur:
+ + 	 * a. Channel i, hardware synchronized, is enabled
+ + 	 * b. Another channel (Channel x), software synchronized, is enabled.
+ + 	 * c. Channel i is disabled before end of transfer
+ + 	 * d. Channel i is reenabled.
+ + 	 * e. Steps 1 to 4 are repeated a certain number of times.
+ + 	 * f. A third channel (Channel y), software synchronized, is enabled.
+ + 	 * Channel x and Channel y may hang immediately after step 'f'.
+ + 	 * Workaround:
+ + 	 * For any channel used - make sure NextLCH_ID is set to the value j.
+ + 	 */
+ + 	if (cpu_is_omap2420() || (cpu_is_omap2430() &&
+ + 				(omap_type() == OMAP2430_REV_ES1_0))) {
+ + 
+ + 		SET_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING);
+ + 		SET_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS);
+ + 	}
+ + 
+ + 	/*
+ + 	 * Erratum ID: i378: OMAP2+: sDMA Channel is not disabled
+ + 	 * after a transaction error.
+ + 	 * Workaround: SW should explicitely disable the channel.
+ + 	 */
+ + 	SET_DMA_ERRATA(DMA_ERRATA_i378);
+ + 
+ + 	/*
+ + 	 * Erratum ID: i541: sDMA FIFO draining does not finish
+ + 	 * If sDMA channel is disabled on the fly, sDMA enters standby even
+ + 	 * through FIFO Drain is still in progress
+ + 	 * Workaround: Put sDMA in NoStandby more before a logical channel is
+ + 	 * disabled, then put it back to SmartStandby right after the channel
+ + 	 * finishes FIFO draining.
+ + 	 */
+ + 	SET_DMA_ERRATA(DMA_ERRATA_i541);
+ + 
+ + 	/*
+ + 	 * Erratum ID: i88 : Special programming model needed to disable DMA
+ + 	 * before end of block.
+ + 	 * Workaround: software must ensure that the DMA is configured in No
+ + 	 * Standby mode(DMAx_OCP_SYSCONFIG.MIDLEMODE = "01")
+ + 	 */
+ + 	if (omap_type() == OMAP3430_REV_ES1_0)
+ + 		SET_DMA_ERRATA(DMA_ERRATA_i88);
+ + 
+ + 	/*
+ + 	 * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
+ + 	 * read before the DMA controller finished disabling the channel.
+ + 	 */
+ + 	SET_DMA_ERRATA(DMA_ERRATA_3_3);
+ + 
+ + 	/*
+ + 	 * Erratum ID: Not Available
+ + 	 * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
+ + 	 * after secure sram context save and restore.
+ + 	 * Work around: Hence we need to manually clear those IRQs to avoid
+ + 	 * spurious interrupts. This affects only secure devices.
+ + 	 */
+ + 	if (omap_type() != OMAP2_DEVICE_TYPE_GP)
+ + 		SET_DMA_ERRATA(DMA_ROMCODE_BUG);
+ + 
+ + 	return errata;
+ + }
+ + 
+ + /* One time initializations */
+ + static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
+ + {
+ + 	struct platform_device			*pdev;
+ + 	struct omap_system_dma_plat_info	*p;
+ + 	struct resource				*mem;
+ + 	char					*name = "omap_dma_system";
+ + 
+ + 	dma_stride		= OMAP2_DMA_STRIDE;
+ + 	dma_common_ch_start	= CSDP;
+ + 	dma_common_ch_end = CCFN;
+ + 
+ + 	p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL);
+ + 	if (!p) {
+ + 		pr_err("%s: Unable to allocate pdata for %s:%s\n",
+ + 			__func__, name, oh->name);
+ + 		return -ENOMEM;
+ + 	}
+ + 
+ + 	p->dma_attr		= (struct omap_dma_dev_attr *)oh->dev_attr;
+ + 	p->disable_irq_lch	= omap2_disable_irq_lch;
+ + 	p->show_dma_caps	= omap2_show_dma_caps;
+ + 	p->clear_dma		= omap2_clear_dma;
+ + 	p->dma_write		= dma_write;
+ + 	p->dma_read		= dma_read;
+ + 
+ + 	p->clear_lch_regs	= NULL;
+ + 
+ + 	p->errata		= configure_dma_errata();
+ + 
+ + 	pdev = omap_device_build(name, 0, oh, p, sizeof(*p), NULL, 0, 0);
+ + 	kfree(p);
+ + 	if (IS_ERR(pdev)) {
+ + 		pr_err("%s: Can't build omap_device for %s:%s.\n",
+ + 			__func__, name, oh->name);
+ + 		return PTR_ERR(pdev);
+ + 	}
+ + 
+ + 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ + 	if (!mem) {
+ + 		dev_err(&pdev->dev, "%s: no mem resource\n", __func__);
+ + 		return -EINVAL;
+ + 	}
+ + 	dma_base = ioremap(mem->start, resource_size(mem));
+ + 	if (!dma_base) {
+ + 		dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
+ + 		return -ENOMEM;
+ + 	}
+ + 
+ + 	d = oh->dev_attr;
+ + 	d->chan = kzalloc(sizeof(struct omap_dma_lch) *
+ + 					(d->lch_count), GFP_KERNEL);
+ + 
+ + 	if (!d->chan) {
+ + 		dev_err(&pdev->dev, "%s: kzalloc fail\n", __func__);
+ + 		return -ENOMEM;
+ + 	}
+ + 	return 0;
+ + }
+ + 
+ + static int __init omap2_system_dma_init(void)
+ + {
+ + 	return omap_hwmod_for_each_by_class("dma",
+ + 			omap2_system_dma_init_dev, NULL);
+ + }
+ + arch_initcall(omap2_system_dma_init);
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/dpll3xxx.c linux-3.2.1/arch/arm/mach-ckb_3352/dpll3xxx.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/dpll3xxx.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/dpll3xxx.c	2014-11-25 13:19:14.983536785 +0900
+ ***************
+ *** 0 ****
+ --- 1,574 ----
+ + /*
+ +  * OMAP3/4 - specific DPLL control functions
+ +  *
+ +  * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ +  * Copyright (C) 2009-2010 Nokia Corporation
+ +  *
+ +  * Written by Paul Walmsley
+ +  * Testing and integration fixes by Jouni Högander
+ +  *
+ +  * 36xx support added by Vishwanath BS, Richard Woodruff, and Nishanth
+ +  * Menon
+ +  *
+ +  * Parts of this code are based on code written by
+ +  * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #include <linux/kernel.h>
+ + #include <linux/device.h>
+ + #include <linux/list.h>
+ + #include <linux/errno.h>
+ + #include <linux/delay.h>
+ + #include <linux/clk.h>
+ + #include <linux/io.h>
+ + #include <linux/bitops.h>
+ + #include <linux/clkdev.h>
+ + 
+ + #include <plat/cpu.h>
+ + #include <plat/clock.h>
+ + 
+ + #include "clock.h"
+ + #include "cm2xxx_3xxx.h"
+ + 
+ + /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
+ + #define DPLL_AUTOIDLE_DISABLE			0x0
+ + #define DPLL_AUTOIDLE_LOW_POWER_STOP		0x1
+ + 
+ + #define MAX_DPLL_WAIT_TRIES		1000000
+ + 
+ + /* Private functions */
+ + 
+ + /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
+ + static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
+ + {
+ + 	const struct dpll_data *dd;
+ + 	u32 v;
+ + 
+ + 	dd = clk->dpll_data;
+ + 
+ + 	v = __raw_readl(dd->control_reg);
+ + 	v &= ~dd->enable_mask;
+ + 	v |= clken_bits << __ffs(dd->enable_mask);
+ + 	__raw_writel(v, dd->control_reg);
+ + }
+ + 
+ + /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
+ + static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
+ + {
+ + 	const struct dpll_data *dd;
+ + 	int i = 0;
+ + 	int ret = -EINVAL;
+ + 
+ + 	dd = clk->dpll_data;
+ + 
+ + 	state <<= __ffs(dd->idlest_mask);
+ + 
+ + 	while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
+ + 	       i < MAX_DPLL_WAIT_TRIES) {
+ + 		i++;
+ + 		udelay(1);
+ + 	}
+ + 
+ + 	if (i == MAX_DPLL_WAIT_TRIES) {
+ + 		printk(KERN_ERR "clock: %s failed transition to '%s'\n",
+ + 		       clk->name, (state) ? "locked" : "bypassed");
+ + 	} else {
+ + 		pr_debug("clock: %s transition to '%s' in %d loops\n",
+ + 			 clk->name, (state) ? "locked" : "bypassed", i);
+ + 
+ + 		ret = 0;
+ + 	}
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /*
+ +  * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
+ +  * @clk: pointer to a DPLL struct clk
+ +  *
+ +  * Instructs a non-CORE DPLL to lock.  Waits for the DPLL to report
+ +  * readiness before returning.  Will save and restore the DPLL's
+ +  * autoidle state across the enable, per the CDP code.  If the DPLL
+ +  * locked successfully, return 0; if the DPLL did not lock in the time
+ +  * allotted, or DPLL3 was passed in, return -EINVAL.
+ +  */
+ + static int _omap3_noncore_dpll_lock(struct clk *clk)
+ + {
+ + 	u8 ai;
+ + 	int r;
+ + 
+ + 	pr_debug("clock: locking DPLL %s\n", clk->name);
+ + 
+ + 	ai = omap3_dpll_autoidle_read(clk);
+ + 
+ + 	if (ai)
+ + 		omap3_dpll_deny_idle(clk);
+ + 
+ + 	_omap3_dpll_write_clken(clk, DPLL_LOCKED);
+ + 
+ + 	r = _omap3_wait_dpll_status(clk, 1);
+ + 
+ + 	if (ai)
+ + 		omap3_dpll_allow_idle(clk);
+ + 
+ + 	return r;
+ + }
+ + 
+ + /*
+ +  * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
+ +  * @clk: pointer to a DPLL struct clk
+ +  *
+ +  * Instructs a non-CORE DPLL to enter low-power bypass mode.  In
+ +  * bypass mode, the DPLL's rate is set equal to its parent clock's
+ +  * rate.  Waits for the DPLL to report readiness before returning.
+ +  * Will save and restore the DPLL's autoidle state across the enable,
+ +  * per the CDP code.  If the DPLL entered bypass mode successfully,
+ +  * return 0; if the DPLL did not enter bypass in the time allotted, or
+ +  * DPLL3 was passed in, or the DPLL does not support low-power bypass,
+ +  * return -EINVAL.
+ +  */
+ + static int _omap3_noncore_dpll_bypass(struct clk *clk)
+ + {
+ + 	int r;
+ + 	u8 ai;
+ + 
+ + 	if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
+ + 		return -EINVAL;
+ + 
+ + 	pr_debug("clock: configuring DPLL %s for low-power bypass\n",
+ + 		 clk->name);
+ + 
+ + 	ai = omap3_dpll_autoidle_read(clk);
+ + 
+ + 	_omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
+ + 
+ + 	r = _omap3_wait_dpll_status(clk, 0);
+ + 
+ + 	if (ai)
+ + 		omap3_dpll_allow_idle(clk);
+ + 
+ + 	return r;
+ + }
+ + 
+ + /*
+ +  * _omap3_noncore_dpll_stop - instruct a DPLL to stop
+ +  * @clk: pointer to a DPLL struct clk
+ +  *
+ +  * Instructs a non-CORE DPLL to enter low-power stop. Will save and
+ +  * restore the DPLL's autoidle state across the stop, per the CDP
+ +  * code.  If DPLL3 was passed in, or the DPLL does not support
+ +  * low-power stop, return -EINVAL; otherwise, return 0.
+ +  */
+ + static int _omap3_noncore_dpll_stop(struct clk *clk)
+ + {
+ + 	u8 ai;
+ + 
+ + 	if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
+ + 		return -EINVAL;
+ + 
+ + 	pr_debug("clock: stopping DPLL %s\n", clk->name);
+ + 
+ + 	ai = omap3_dpll_autoidle_read(clk);
+ + 
+ + 	_omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
+ + 
+ + 	if (ai)
+ + 		omap3_dpll_allow_idle(clk);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * _lookup_dco - Lookup DCO used by j-type DPLL
+ +  * @clk: pointer to a DPLL struct clk
+ +  * @dco: digital control oscillator selector
+ +  * @m: DPLL multiplier to set
+ +  * @n: DPLL divider to set
+ +  *
+ +  * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
+ +  *
+ +  * XXX This code is not needed for 3430/AM35xx; can it be optimized
+ +  * out in non-multi-OMAP builds for those chips?
+ +  */
+ + static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n)
+ + {
+ + 	unsigned long fint, clkinp; /* watch out for overflow */
+ + 
+ + 	clkinp = clk->parent->rate;
+ + 	fint = (clkinp / n) * m;
+ + 
+ + 	if (fint < 1000000000)
+ + 		*dco = 2;
+ + 	else
+ + 		*dco = 4;
+ + }
+ + 
+ + /**
+ +  * _lookup_sddiv - Calculate sigma delta divider for j-type DPLL
+ +  * @clk: pointer to a DPLL struct clk
+ +  * @sd_div: target sigma-delta divider
+ +  * @m: DPLL multiplier to set
+ +  * @n: DPLL divider to set
+ +  *
+ +  * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
+ +  *
+ +  * XXX This code is not needed for 3430/AM35xx; can it be optimized
+ +  * out in non-multi-OMAP builds for those chips?
+ +  */
+ + static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n)
+ + {
+ + 	unsigned long clkinp, sd; /* watch out for overflow */
+ + 	int mod1, mod2;
+ + 
+ + 	clkinp = clk->parent->rate;
+ + 
+ + 	/*
+ + 	 * target sigma-delta to near 250MHz
+ + 	 * sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)]
+ + 	 */
+ + 	clkinp /= 100000; /* shift from MHz to 10*Hz for 38.4 and 19.2 */
+ + 	mod1 = (clkinp * m) % (250 * n);
+ + 	sd = (clkinp * m) / (250 * n);
+ + 	mod2 = sd % 10;
+ + 	sd /= 10;
+ + 
+ + 	if (mod1 || mod2)
+ + 		sd++;
+ + 	*sd_div = sd;
+ + }
+ + 
+ + /*
+ +  * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly
+ +  * @clk: struct clk * of DPLL to set
+ +  * @m: DPLL multiplier to set
+ +  * @n: DPLL divider to set
+ +  * @freqsel: FREQSEL value to set
+ +  *
+ +  * Program the DPLL with the supplied M, N values, and wait for the DPLL to
+ +  * lock..  Returns -EINVAL upon error, or 0 upon success.
+ +  */
+ + static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
+ + {
+ + 	struct dpll_data *dd = clk->dpll_data;
+ + 	u8 dco, sd_div;
+ + 	u32 v;
+ + 
+ + 	/* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
+ + 	_omap3_noncore_dpll_bypass(clk);
+ + 
+ + 	/* Set DPLL multiplier, divider */
+ + 	v = __raw_readl(dd->mult_div1_reg);
+ + 	v &= ~(dd->mult_mask | dd->div1_mask);
+ + 	v |= m << __ffs(dd->mult_mask);
+ + 	v |= (n - 1) << __ffs(dd->div1_mask);
+ + 
+ + 	/* Configure dco and sd_div for dplls that have these fields */
+ + 	if (dd->dco_mask) {
+ + 		_lookup_dco(clk, &dco, m, n);
+ + 		v &= ~(dd->dco_mask);
+ + 		v |= dco << __ffs(dd->dco_mask);
+ + 	}
+ + 	if (dd->sddiv_mask) {
+ + 		_lookup_sddiv(clk, &sd_div, m, n);
+ + 		v &= ~(dd->sddiv_mask);
+ + 		v |= sd_div << __ffs(dd->sddiv_mask);
+ + 	}
+ + 
+ + 	__raw_writel(v, dd->mult_div1_reg);
+ + 
+ + 	/* We let the clock framework set the other output dividers later */
+ + 
+ + 	/* REVISIT: Set ramp-up delay? */
+ + 
+ + 	_omap3_noncore_dpll_lock(clk);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /* Public functions */
+ + 
+ + /**
+ +  * omap3_dpll_recalc - recalculate DPLL rate
+ +  * @clk: DPLL struct clk
+ +  *
+ +  * Recalculate and propagate the DPLL rate.
+ +  */
+ + unsigned long omap3_dpll_recalc(struct clk *clk)
+ + {
+ + 	return omap2_get_dpll_rate(clk);
+ + }
+ + 
+ + /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
+ + 
+ + /**
+ +  * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
+ +  * @clk: pointer to a DPLL struct clk
+ +  *
+ +  * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
+ +  * The choice of modes depends on the DPLL's programmed rate: if it is
+ +  * the same as the DPLL's parent clock, it will enter bypass;
+ +  * otherwise, it will enter lock.  This code will wait for the DPLL to
+ +  * indicate readiness before returning, unless the DPLL takes too long
+ +  * to enter the target state.  Intended to be used as the struct clk's
+ +  * enable function.  If DPLL3 was passed in, or the DPLL does not
+ +  * support low-power stop, or if the DPLL took too long to enter
+ +  * bypass or lock, return -EINVAL; otherwise, return 0.
+ +  */
+ + int omap3_noncore_dpll_enable(struct clk *clk)
+ + {
+ + 	int r;
+ + 	struct dpll_data *dd;
+ + 
+ + 	dd = clk->dpll_data;
+ + 	if (!dd)
+ + 		return -EINVAL;
+ + 
+ + 	if (clk->rate == dd->clk_bypass->rate) {
+ + 		WARN_ON(clk->parent != dd->clk_bypass);
+ + 		r = _omap3_noncore_dpll_bypass(clk);
+ + 	} else {
+ + 		WARN_ON(clk->parent != dd->clk_ref);
+ + 		r = _omap3_noncore_dpll_lock(clk);
+ + 	}
+ + 	/*
+ + 	 *FIXME: this is dubious - if clk->rate has changed, what about
+ + 	 * propagating?
+ + 	 */
+ + 	if (!r)
+ + 		clk->rate = (clk->recalc) ? clk->recalc(clk) :
+ + 			omap2_get_dpll_rate(clk);
+ + 
+ + 	return r;
+ + }
+ + 
+ + /**
+ +  * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop
+ +  * @clk: pointer to a DPLL struct clk
+ +  *
+ +  * Instructs a non-CORE DPLL to enter low-power stop.  This function is
+ +  * intended for use in struct clkops.  No return value.
+ +  */
+ + void omap3_noncore_dpll_disable(struct clk *clk)
+ + {
+ + 	_omap3_noncore_dpll_stop(clk);
+ + }
+ + 
+ + 
+ + /* Non-CORE DPLL rate set code */
+ + 
+ + /**
+ +  * omap3_noncore_dpll_set_rate - set non-core DPLL rate
+ +  * @clk: struct clk * of DPLL to set
+ +  * @rate: rounded target rate
+ +  *
+ +  * Set the DPLL CLKOUT to the target rate.  If the DPLL can enter
+ +  * low-power bypass, and the target rate is the bypass source clock
+ +  * rate, then configure the DPLL for bypass.  Otherwise, round the
+ +  * target rate if it hasn't been done already, then program and lock
+ +  * the DPLL.  Returns -EINVAL upon error, or 0 upon success.
+ +  */
+ + int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
+ + {
+ + 	struct clk *new_parent = NULL;
+ + 	unsigned long hw_rate;
+ + 	u16 freqsel = 0;
+ + 	struct dpll_data *dd;
+ + 	int ret;
+ + 
+ + 	if (!clk || !rate)
+ + 		return -EINVAL;
+ + 
+ + 	dd = clk->dpll_data;
+ + 	if (!dd)
+ + 		return -EINVAL;
+ + 
+ + 	hw_rate = (clk->recalc) ? clk->recalc(clk) : omap2_get_dpll_rate(clk);
+ + 	if (rate == hw_rate)
+ + 		return 0;
+ + 
+ + 	/*
+ + 	 * Ensure both the bypass and ref clocks are enabled prior to
+ + 	 * doing anything; we need the bypass clock running to reprogram
+ + 	 * the DPLL.
+ + 	 */
+ + 	omap2_clk_enable(dd->clk_bypass);
+ + 	omap2_clk_enable(dd->clk_ref);
+ + 
+ + 	if (dd->clk_bypass->rate == rate &&
+ + 	    (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
+ + 		pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
+ + 
+ + 		ret = _omap3_noncore_dpll_bypass(clk);
+ + 		if (!ret)
+ + 			new_parent = dd->clk_bypass;
+ + 	} else {
+ + 		if (dd->last_rounded_rate != rate)
+ + 			rate = clk->round_rate(clk, rate);
+ + 
+ + 		if (dd->last_rounded_rate == 0)
+ + 			return -EINVAL;
+ + 
+ + 		pr_debug("clock: %s: set rate: locking rate to %lu.\n",
+ + 			 clk->name, rate);
+ + 
+ + 		ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
+ + 						 dd->last_rounded_n, freqsel);
+ + 		if (!ret)
+ + 			new_parent = dd->clk_ref;
+ + 	}
+ + 	if (!ret) {
+ + 		/*
+ + 		 * Switch the parent clock in the hierarchy, and make sure
+ + 		 * that the new parent's usecount is correct.  Note: we
+ + 		 * enable the new parent before disabling the old to avoid
+ + 		 * any unnecessary hardware disable->enable transitions.
+ + 		 */
+ + 		if (clk->usecount) {
+ + 			omap2_clk_enable(new_parent);
+ + 			omap2_clk_disable(clk->parent);
+ + 		}
+ + 		clk_reparent(clk, new_parent);
+ + 		clk->rate = rate;
+ + 	}
+ + 	omap2_clk_disable(dd->clk_ref);
+ + 	omap2_clk_disable(dd->clk_bypass);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /* DPLL autoidle read/set code */
+ + 
+ + /**
+ +  * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
+ +  * @clk: struct clk * of the DPLL to read
+ +  *
+ +  * Return the DPLL's autoidle bits, shifted down to bit 0.  Returns
+ +  * -EINVAL if passed a null pointer or if the struct clk does not
+ +  * appear to refer to a DPLL.
+ +  */
+ + u32 omap3_dpll_autoidle_read(struct clk *clk)
+ + {
+ + 	const struct dpll_data *dd;
+ + 	u32 v;
+ + 
+ + 	if (!clk || !clk->dpll_data)
+ + 		return -EINVAL;
+ + 
+ + 	dd = clk->dpll_data;
+ + 
+ + 	if (!dd->autoidle_reg)
+ + 		return -EINVAL;
+ + 
+ + 	v = __raw_readl(dd->autoidle_reg);
+ + 	v &= dd->autoidle_mask;
+ + 	v >>= __ffs(dd->autoidle_mask);
+ + 
+ + 	return v;
+ + }
+ + 
+ + /**
+ +  * omap3_dpll_allow_idle - enable DPLL autoidle bits
+ +  * @clk: struct clk * of the DPLL to operate on
+ +  *
+ +  * Enable DPLL automatic idle control.  This automatic idle mode
+ +  * switching takes effect only when the DPLL is locked, at least on
+ +  * OMAP3430.  The DPLL will enter low-power stop when its downstream
+ +  * clocks are gated.  No return value.
+ +  */
+ + void omap3_dpll_allow_idle(struct clk *clk)
+ + {
+ + 	const struct dpll_data *dd;
+ + 	u32 v;
+ + 
+ + 	if (!clk || !clk->dpll_data)
+ + 		return;
+ + 
+ + 	dd = clk->dpll_data;
+ + 
+ + 	if (!dd->autoidle_reg) {
+ + 		pr_debug("clock: DPLL %s: autoidle not supported\n",
+ + 			clk->name);
+ + 		return;
+ + 	}
+ + 
+ + 	/*
+ + 	 * REVISIT: CORE DPLL can optionally enter low-power bypass
+ + 	 * by writing 0x5 instead of 0x1.  Add some mechanism to
+ + 	 * optionally enter this mode.
+ + 	 */
+ + 	v = __raw_readl(dd->autoidle_reg);
+ + 	v &= ~dd->autoidle_mask;
+ + 	v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
+ + 	__raw_writel(v, dd->autoidle_reg);
+ + 
+ + }
+ + 
+ + /**
+ +  * omap3_dpll_deny_idle - prevent DPLL from automatically idling
+ +  * @clk: struct clk * of the DPLL to operate on
+ +  *
+ +  * Disable DPLL automatic idle control.  No return value.
+ +  */
+ + void omap3_dpll_deny_idle(struct clk *clk)
+ + {
+ + 	const struct dpll_data *dd;
+ + 	u32 v;
+ + 
+ + 	if (!clk || !clk->dpll_data)
+ + 		return;
+ + 
+ + 	dd = clk->dpll_data;
+ + 
+ + 	if (!dd->autoidle_reg) {
+ + 		pr_debug("clock: DPLL %s: autoidle not supported\n",
+ + 			clk->name);
+ + 		return;
+ + 	}
+ + 
+ + 	v = __raw_readl(dd->autoidle_reg);
+ + 	v &= ~dd->autoidle_mask;
+ + 	v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
+ + 	__raw_writel(v, dd->autoidle_reg);
+ + 
+ + }
+ + 
+ + /* Clock control for DPLL outputs */
+ + 
+ + /**
+ +  * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
+ +  * @clk: DPLL output struct clk
+ +  *
+ +  * Using parent clock DPLL data, look up DPLL state.  If locked, set our
+ +  * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
+ +  */
+ + unsigned long omap3_clkoutx2_recalc(struct clk *clk)
+ + {
+ + 	const struct dpll_data *dd;
+ + 	unsigned long rate;
+ + 	u32 v;
+ + 	struct clk *pclk;
+ + 
+ + 	/* Walk up the parents of clk, looking for a DPLL */
+ + 	pclk = clk->parent;
+ + 	while (pclk && !pclk->dpll_data)
+ + 		pclk = pclk->parent;
+ + 
+ + 	/* clk does not have a DPLL as a parent? */
+ + 	WARN_ON(!pclk);
+ + 
+ + 	dd = pclk->dpll_data;
+ + 
+ + 	WARN_ON(!dd->enable_mask);
+ + 
+ + 	v = __raw_readl(dd->control_reg) & dd->enable_mask;
+ + 	v >>= __ffs(dd->enable_mask);
+ + 	if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
+ + 		rate = clk->parent->rate;
+ + 	else
+ + 		rate = clk->parent->rate * 2;
+ + 	return rate;
+ + }
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/gpio.c linux-3.2.1/arch/arm/mach-ckb_3352/gpio.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/gpio.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/gpio.c	2014-11-25 13:19:14.983536785 +0900
+ ***************
+ *** 0 ****
+ --- 1,128 ----
+ + /*
+ +  * OMAP2+ specific gpio initialization
+ +  *
+ +  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ +  *
+ +  * Author:
+ +  *	Charulatha V <charu@ti.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #include <linux/gpio.h>
+ + #include <linux/err.h>
+ + #include <linux/slab.h>
+ + #include <linux/interrupt.h>
+ + 
+ + #include <plat/omap_hwmod.h>
+ + #include <plat/omap_device.h>
+ + 
+ + static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
+ + {
+ + 	struct platform_device *pdev;
+ + 	struct omap_gpio_platform_data *pdata;
+ + 	struct omap_gpio_dev_attr *dev_attr;
+ + 	char *name = "omap_gpio";
+ + 	int id;
+ + 
+ + 	/*
+ + 	 * extract the device id from name field available in the
+ + 	 * hwmod database and use the same for constructing ids for
+ + 	 * gpio devices.
+ + 	 * CAUTION: Make sure the name in the hwmod database does
+ + 	 * not change. If changed, make corresponding change here
+ + 	 * or make use of static variable mechanism to handle this.
+ + 	 */
+ + 	sscanf(oh->name, "gpio%d", &id);
+ + 
+ + 	pdata = kzalloc(sizeof(struct omap_gpio_platform_data), GFP_KERNEL);
+ + 	if (!pdata) {
+ + 		pr_err("gpio%d: Memory allocation failed\n", id);
+ + 		return -ENOMEM;
+ + 	}
+ + 
+ + 	dev_attr = (struct omap_gpio_dev_attr *)oh->dev_attr;
+ + 	pdata->bank_width = dev_attr->bank_width;
+ + 	pdata->dbck_flag = dev_attr->dbck_flag;
+ + 	pdata->virtual_irq_start = IH_GPIO_BASE + 32 * (id - 1);
+ + 
+ + 	pdata->regs = kzalloc(sizeof(struct omap_gpio_reg_offs), GFP_KERNEL);
+ + 	if (!pdata) {
+ + 		pr_err("gpio%d: Memory allocation failed\n", id);
+ + 		return -ENOMEM;
+ + 	}
+ + 
+ + 	switch (oh->class->rev) {
+ + 	case 0:
+ + 	case 1:
+ + 		pdata->bank_type = METHOD_GPIO_24XX;
+ + 		pdata->regs->revision = OMAP24XX_GPIO_REVISION;
+ + 		pdata->regs->direction = OMAP24XX_GPIO_OE;
+ + 		pdata->regs->datain = OMAP24XX_GPIO_DATAIN;
+ + 		pdata->regs->dataout = OMAP24XX_GPIO_DATAOUT;
+ + 		pdata->regs->set_dataout = OMAP24XX_GPIO_SETDATAOUT;
+ + 		pdata->regs->clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT;
+ + 		pdata->regs->irqstatus = OMAP24XX_GPIO_IRQSTATUS1;
+ + 		pdata->regs->irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2;
+ + 		pdata->regs->irqenable = OMAP24XX_GPIO_IRQENABLE1;
+ + 		pdata->regs->set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1;
+ + 		pdata->regs->clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1;
+ + 		pdata->regs->debounce = OMAP24XX_GPIO_DEBOUNCE_VAL;
+ + 		pdata->regs->debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN;
+ + 		break;
+ + 	case 2:
+ + 		pdata->bank_type = METHOD_GPIO_44XX;
+ + 		pdata->regs->revision = OMAP4_GPIO_REVISION;
+ + 		pdata->regs->direction = OMAP4_GPIO_OE;
+ + 		pdata->regs->datain = OMAP4_GPIO_DATAIN;
+ + 		pdata->regs->dataout = OMAP4_GPIO_DATAOUT;
+ + 		pdata->regs->set_dataout = OMAP4_GPIO_SETDATAOUT;
+ + 		pdata->regs->clr_dataout = OMAP4_GPIO_CLEARDATAOUT;
+ + 		pdata->regs->irqstatus = OMAP4_GPIO_IRQSTATUS0;
+ + 		pdata->regs->irqstatus2 = OMAP4_GPIO_IRQSTATUS1;
+ + 		pdata->regs->irqenable = OMAP4_GPIO_IRQSTATUSSET0;
+ + 		pdata->regs->set_irqenable = OMAP4_GPIO_IRQSTATUSSET0;
+ + 		pdata->regs->clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0;
+ + 		pdata->regs->debounce = OMAP4_GPIO_DEBOUNCINGTIME;
+ + 		pdata->regs->debounce_en = OMAP4_GPIO_DEBOUNCENABLE;
+ + 		break;
+ + 	default:
+ + 		WARN(1, "Invalid gpio bank_type\n");
+ + 		kfree(pdata);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	pdev = omap_device_build(name, id - 1, oh, pdata,
+ + 				sizeof(*pdata),	NULL, 0, false);
+ + 	kfree(pdata);
+ + 
+ + 	if (IS_ERR(pdev)) {
+ + 		WARN(1, "Can't build omap_device for %s:%s.\n",
+ + 					name, oh->name);
+ + 		return PTR_ERR(pdev);
+ + 	}
+ + 
+ + 	omap_device_disable_idle_on_suspend(pdev);
+ + 
+ + 	gpio_bank_count++;
+ + 	return 0;
+ + }
+ + 
+ + /*
+ +  * gpio_init needs to be done before
+ +  * machine_init functions access gpio APIs.
+ +  * Hence gpio_init is a postcore_initcall.
+ +  */
+ + static int __init omap2_gpio_init(void)
+ + {
+ + 	return omap_hwmod_for_each_by_class("gpio", omap2_gpio_dev_init,
+ + 						NULL);
+ + }
+ + postcore_initcall(omap2_gpio_init);
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/gpmc.c linux-3.2.1/arch/arm/mach-ckb_3352/gpmc.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/gpmc.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/gpmc.c	2014-11-25 13:19:14.987396928 +0900
+ ***************
+ *** 0 ****
+ --- 1,1033 ----
+ + /*
+ +  * GPMC support functions
+ +  *
+ +  * Copyright (C) 2005-2006 Nokia Corporation
+ +  *
+ +  * Author: Juha Yrjola
+ +  *
+ +  * Copyright (C) 2009 Texas Instruments
+ +  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + #undef DEBUG
+ + 
+ + #include <linux/platform_device.h>
+ + 
+ + #include <linux/irq.h>
+ + #include <linux/kernel.h>
+ + #include <linux/init.h>
+ + #include <linux/err.h>
+ + #include <linux/clk.h>
+ + #include <linux/ioport.h>
+ + #include <linux/spinlock.h>
+ + #include <linux/io.h>
+ + #include <linux/module.h>
+ + #include <linux/interrupt.h>
+ + #include <linux/pm_runtime.h>
+ + 
+ + #include <asm/mach-types.h>
+ + #include <plat/gpmc.h>
+ + 
+ + #include <plat/sdrc.h>
+ + 
+ + /* GPMC register offsets */
+ + #define GPMC_REVISION		0x00
+ + #define GPMC_SYSCONFIG		0x10
+ + #define GPMC_SYSSTATUS		0x14
+ + #define GPMC_IRQSTATUS		0x18
+ + #define GPMC_IRQENABLE		0x1c
+ + #define GPMC_TIMEOUT_CONTROL	0x40
+ + #define GPMC_ERR_ADDRESS	0x44
+ + #define GPMC_ERR_TYPE		0x48
+ + #define GPMC_CONFIG		0x50
+ + #define GPMC_STATUS		0x54
+ + #define GPMC_PREFETCH_CONFIG1	0x1e0
+ + #define GPMC_PREFETCH_CONFIG2	0x1e4
+ + #define GPMC_PREFETCH_CONTROL	0x1ec
+ + #define GPMC_PREFETCH_STATUS	0x1f0
+ + #define GPMC_ECC_CONFIG		0x1f4
+ + #define GPMC_ECC_CONTROL	0x1f8
+ + #define GPMC_ECC_SIZE_CONFIG	0x1fc
+ + #define GPMC_ECC1_RESULT        0x200
+ + #define GPMC_ECC_BCH_RESULT_0	0x240
+ + 
+ + #define GPMC_SYSCONF_SIDLEMODE	(2<<3)
+ + #define GPMC_SYSCONF_SOFTRESET	(0<<1)
+ + #define GPMC_SYSCONF_AUTOIDLE	(0)
+ + 
+ + #define GPMC_CS0_OFFSET		0x60
+ + #define GPMC_CS_SIZE		0x30
+ + 
+ + #define GPMC_MEM_START		0x00000000
+ + #define GPMC_MEM_END		0x3FFFFFFF
+ + #define BOOT_ROM_SPACE		0x100000	/* 1MB */
+ + 
+ + #define GPMC_CHUNK_SHIFT	24		/* 16 MB */
+ + #define GPMC_SECTION_SHIFT	28		/* 128 MB */
+ + 
+ + #define CS_NUM_SHIFT		24
+ + #define ENABLE_PREFETCH		(0x1 << 7)
+ + #define DMA_MPU_MODE		2
+ + 
+ + /* Structure to save gpmc cs context */
+ + struct gpmc_cs_config {
+ + 	u32 config1;
+ + 	u32 config2;
+ + 	u32 config3;
+ + 	u32 config4;
+ + 	u32 config5;
+ + 	u32 config6;
+ + 	u32 config7;
+ + 	int is_valid;
+ + };
+ + 
+ + /*
+ +  * Structure to save/restore gpmc context
+ +  * to support core off on OMAP3
+ +  */
+ + struct omap3_gpmc_regs {
+ + 	u32 sysconfig;
+ + 	u32 irqenable;
+ + 	u32 timeout_ctrl;
+ + 	u32 config;
+ + 	u32 prefetch_config1;
+ + 	u32 prefetch_config2;
+ + 	u32 prefetch_control;
+ + 	struct gpmc_cs_config cs_context[GPMC_CS_NUM];
+ + };
+ + 
+ + 
+ + #define	DRIVER_NAME	"omap-gpmc"
+ + 
+ + struct gpmc {
+ + 	struct device	*dev;
+ + 	void __iomem	*io_base;
+ + 	unsigned long	phys_base;
+ + 	u32		memsize;
+ + 	unsigned int	cs_map;
+ + 	int		ecc_used;
+ + 	spinlock_t	mem_lock;
+ + 	struct resource	mem_root;
+ + 	struct resource	cs_mem[GPMC_CS_NUM];
+ + };
+ + 
+ + static struct gpmc *gpmc;
+ + 
+ + static void gpmc_write_reg(int idx, u32 val)
+ + {
+ + 	writel(val, gpmc->io_base + idx);
+ + }
+ + 
+ + static u32 gpmc_read_reg(int idx)
+ + {
+ + 	return readl(gpmc->io_base + idx);
+ + }
+ + 
+ + static void gpmc_cs_write_byte(int cs, int idx, u8 val)
+ + {
+ + 	void __iomem *reg_addr;
+ + 
+ + 	reg_addr = gpmc->io_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
+ + 	writeb(val, reg_addr);
+ + }
+ + 
+ + static u8 gpmc_cs_read_byte(int cs, int idx)
+ + {
+ + 	void __iomem *reg_addr;
+ + 
+ + 	reg_addr = gpmc->io_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
+ + 	return readb(reg_addr);
+ + }
+ + 
+ + void gpmc_cs_write_reg(int cs, int idx, u32 val)
+ + {
+ + 	void __iomem *reg_addr;
+ + 
+ + 	if (!gpmc) {
+ + 		pr_err("%s invoked without initializing GPMC\n", __func__);
+ + 		return;
+ + 	}
+ + 
+ + 	reg_addr = gpmc->io_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
+ + 	writel(val, reg_addr);
+ + }
+ + 
+ + u32 gpmc_cs_read_reg(int cs, int idx)
+ + {
+ + 	void __iomem *reg_addr;
+ + 
+ + 	if (!gpmc) {
+ + 		pr_err("%s invoked without initializing GPMC\n", __func__);
+ + 		return 0;
+ + 	}
+ + 
+ + 	reg_addr = gpmc->io_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
+ + 	return readl(reg_addr);
+ + }
+ + 
+ + static struct clk *gpmc_l3_clk;
+ + 
+ + static void __devinit gpmc_clk_init(struct device *dev)
+ + {
+ + 	char *ck = NULL;
+ + 
+ + 	ck = "gpmc_fck";
+ + 	
+ + 	if (WARN_ON(!ck))
+ + 		return;
+ + 
+ + 	gpmc_l3_clk = clk_get(NULL, ck);
+ + 	if (IS_ERR(gpmc_l3_clk)) {
+ + 		printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
+ + 		BUG();
+ + 	}
+ + 
+ + 	pm_runtime_enable(dev);
+ + 	pm_runtime_get_sync(dev);
+ + }
+ + 
+ + /* TODO: Add support for gpmc_fck to clock framework and use it */
+ + unsigned long gpmc_get_fclk_period(void)
+ + {
+ + 	unsigned long rate = clk_get_rate(gpmc_l3_clk);
+ + 
+ + 	if (rate == 0) {
+ + 		printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
+ + 		return 0;
+ + 	}
+ + 
+ + 	rate /= 1000;
+ + 	rate = 1000000000 / rate;	/* In picoseconds */
+ + 
+ + 	return rate;
+ + }
+ + 
+ + unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
+ + {
+ + 	unsigned long tick_ps;
+ + 
+ + 	/* Calculate in picosecs to yield more exact results */
+ + 	tick_ps = gpmc_get_fclk_period();
+ + 
+ + 	return (time_ns * 1000 + tick_ps - 1) / tick_ps;
+ + }
+ + 
+ + unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
+ + {
+ + 	unsigned long tick_ps;
+ + 
+ + 	/* Calculate in picosecs to yield more exact results */
+ + 	tick_ps = gpmc_get_fclk_period();
+ + 
+ + 	return (time_ps + tick_ps - 1) / tick_ps;
+ + }
+ + 
+ + unsigned int gpmc_ticks_to_ns(unsigned int ticks)
+ + {
+ + 	return ticks * gpmc_get_fclk_period() / 1000;
+ + }
+ + 
+ + unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
+ + {
+ + 	unsigned long ticks = gpmc_ns_to_ticks(time_ns);
+ + 
+ + 	return ticks * gpmc_get_fclk_period() / 1000;
+ + }
+ + 
+ + #ifdef DEBUG
+ + static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
+ + 			       int time, const char *name)
+ + #else
+ + static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
+ + 			       int time)
+ + #endif
+ + {
+ + 	u32 l;
+ + 	int ticks, mask, nr_bits;
+ + 
+ + 	if (time == 0)
+ + 		ticks = 0;
+ + 	else
+ + 		ticks = gpmc_ns_to_ticks(time);
+ + 	nr_bits = end_bit - st_bit + 1;
+ + 	if (ticks >= 1 << nr_bits) {
+ + #ifdef DEBUG
+ + 		printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
+ + 				cs, name, time, ticks, 1 << nr_bits);
+ + #endif
+ + 		return -1;
+ + 	}
+ + 
+ + 	mask = (1 << nr_bits) - 1;
+ + 	l = gpmc_cs_read_reg(cs, reg);
+ + #ifdef DEBUG
+ + 	printk(KERN_INFO
+ + 		"GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
+ + 	       cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
+ + 			(l >> st_bit) & mask, time);
+ + #endif
+ + 	l &= ~(mask << st_bit);
+ + 	l |= ticks << st_bit;
+ + 	gpmc_cs_write_reg(cs, reg, l);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + #ifdef DEBUG
+ + #define GPMC_SET_ONE(reg, st, end, field) \
+ + 	if (set_gpmc_timing_reg(cs, (reg), (st), (end),		\
+ + 			t->field, #field) < 0)			\
+ + 		return -1
+ + #else
+ + #define GPMC_SET_ONE(reg, st, end, field) \
+ + 	if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
+ + 		return -1
+ + #endif
+ + 
+ + int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
+ + {
+ + 	int div;
+ + 	u32 l;
+ + 
+ + 	l = sync_clk + (gpmc_get_fclk_period() - 1);
+ + 	div = l / gpmc_get_fclk_period();
+ + 	if (div > 4)
+ + 		return -1;
+ + 	if (div <= 0)
+ + 		div = 1;
+ + 
+ + 	return div;
+ + }
+ + 
+ + int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
+ + {
+ + 	int div;
+ + 	u32 l;
+ + 
+ + 	div = gpmc_cs_calc_divider(cs, t->sync_clk);
+ + 	if (div < 0)
+ + 		return -1;
+ + 
+ + 	GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
+ + 	GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
+ + 	GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
+ + 
+ + 	GPMC_SET_ONE(GPMC_CS_CONFIG3,  0,  3, adv_on);
+ + 	GPMC_SET_ONE(GPMC_CS_CONFIG3,  8, 12, adv_rd_off);
+ + 	GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
+ + 
+ + 	GPMC_SET_ONE(GPMC_CS_CONFIG4,  0,  3, oe_on);
+ + 	GPMC_SET_ONE(GPMC_CS_CONFIG4,  8, 12, oe_off);
+ + 	GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
+ + 	GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
+ + 
+ + 	GPMC_SET_ONE(GPMC_CS_CONFIG5,  0,  4, rd_cycle);
+ + 	GPMC_SET_ONE(GPMC_CS_CONFIG5,  8, 12, wr_cycle);
+ + 	GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
+ + 
+ + 	GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
+ + 
+ + 	GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
+ + 	GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
+ + 	
+ + 	/* caller is expected to have initialized CONFIG1 to cover
+ + 	 * at least sync vs async
+ + 	 */
+ + 	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
+ + 	if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
+ + #ifdef DEBUG
+ + 		printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
+ + 				cs, (div * gpmc_get_fclk_period()) / 1000, div);
+ + #endif
+ + 		l &= ~0x03;
+ + 		l |= (div - 1);
+ + 		gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
+ + {
+ + 	u32 l;
+ + 	u32 mask;
+ + 
+ + 	mask = (1 << GPMC_SECTION_SHIFT) - size;
+ + 	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
+ + 	l &= ~0x3f;
+ + 	l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
+ + 	l &= ~(0x0f << 8);
+ + 	l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
+ + 	l |= GPMC_CONFIG7_CSVALID;
+ + 	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
+ + }
+ + 
+ + static void gpmc_cs_disable_mem(int cs)
+ + {
+ + 	u32 l;
+ + 
+ + 	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
+ + 	l &= ~GPMC_CONFIG7_CSVALID;
+ + 	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
+ + }
+ + 
+ + static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
+ + {
+ + 	u32 l;
+ + 	u32 mask;
+ + 
+ + 	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
+ + 	*base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
+ + 	mask = (l >> 8) & 0x0f;
+ + 	*size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
+ + 
+ + 	*base = 0x8000000;
+ + 	*size = 0x10000000;
+ + }
+ + 
+ + static int gpmc_cs_mem_enabled(int cs)
+ + {
+ + 	u32 l;
+ + 
+ + 	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
+ + 	return l & GPMC_CONFIG7_CSVALID;
+ + }
+ + 
+ + int gpmc_cs_set_reserved(int cs, int reserved)
+ + {
+ + 	if (cs > GPMC_CS_NUM)
+ + 		return -ENODEV;
+ + 
+ + 	gpmc->cs_map &= ~(1 << cs);
+ + 	gpmc->cs_map |= (reserved ? 1 : 0) << cs;
+ + 
+ + 	return 0;
+ + }
+ + 
+ + int gpmc_cs_reserved(int cs)
+ + {
+ + 	if (cs > GPMC_CS_NUM)
+ + 		return -ENODEV;
+ + 
+ + 	return gpmc->cs_map & (1 << cs);
+ + }
+ + 
+ + static unsigned long gpmc_mem_align(unsigned long size)
+ + {
+ + 	int order;
+ + 
+ + 	size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
+ + 	order = GPMC_CHUNK_SHIFT - 1;
+ + 	do {
+ + 		size >>= 1;
+ + 		order++;
+ + 	} while (size);
+ + 	size = 1 << order;
+ + 	return size;
+ + }
+ + 
+ + static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
+ + {
+ + 	struct resource	*res = &gpmc->cs_mem[cs];
+ + 	int r;
+ + 
+ + 	size = gpmc_mem_align(size);
+ + 	spin_lock(&gpmc->mem_lock);
+ + 	res->start = base;
+ + 	res->end = base + size - 1;
+ + 	r = request_resource(&gpmc->mem_root, res);
+ + 	spin_unlock(&gpmc->mem_lock);
+ + 
+ + 	return r;
+ + }
+ + 
+ + int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
+ + {
+ + 	struct resource *res = &gpmc->cs_mem[cs];
+ + 	int r = -1;
+ + 
+ + 	if (cs > GPMC_CS_NUM)
+ + 		return -ENODEV;
+ + 
+ + 	size = gpmc_mem_align(size);
+ + 	if (size > (1 << GPMC_SECTION_SHIFT))
+ + 		return -ENOMEM;
+ + 
+ + 	spin_lock(&gpmc->mem_lock);
+ + 	if (gpmc_cs_reserved(cs)) {
+ + 		r = -EBUSY;
+ + 		goto out;
+ + 	}
+ + 	if (gpmc_cs_mem_enabled(cs))
+ + 		r = adjust_resource(res, res->start & ~(size - 1), size);
+ + 	if (r < 0)
+ + 		r = allocate_resource(&gpmc->mem_root, res, size, 0, ~0,
+ + 				      size, NULL, NULL);
+ + 	if (r < 0)
+ + 		goto out;
+ + 
+ + 	gpmc_cs_enable_mem(cs, res->start, resource_size(res));
+ + 	*base = res->start;
+ + 	gpmc_cs_set_reserved(cs, 1);
+ + out:
+ + 	spin_unlock(&gpmc->mem_lock);
+ + 	return r;
+ + }
+ + EXPORT_SYMBOL(gpmc_cs_request);
+ + 
+ + void gpmc_cs_free(int cs)
+ + {
+ + 	spin_lock(&gpmc->mem_lock);
+ + 	if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) {
+ + 		printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
+ + 		BUG();
+ + 		spin_unlock(&gpmc->mem_lock);
+ + 		return;
+ + 	}
+ + 	gpmc_cs_disable_mem(cs);
+ + 	release_resource(&gpmc->cs_mem[cs]);
+ + 	gpmc_cs_set_reserved(cs, 0);
+ + 	spin_unlock(&gpmc->mem_lock);
+ + }
+ + EXPORT_SYMBOL(gpmc_cs_free);
+ + 
+ + /**
+ +  * gpmc_read_status - read access request to get the different gpmc status
+ +  * @cmd: command type
+ +  * @return status
+ +  */
+ + int gpmc_read_status(int cmd)
+ + {
+ + 	int	status = -EINVAL;
+ + 	u32	regval = 0;
+ + 
+ + 	switch (cmd) {
+ + 	case GPMC_GET_IRQ_STATUS:
+ + 		status = gpmc_read_reg(GPMC_IRQSTATUS);
+ + 		break;
+ + 
+ + 	case GPMC_PREFETCH_FIFO_CNT:
+ + 		regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
+ + 		status = GPMC_PREFETCH_STATUS_FIFO_CNT(regval);
+ + 		break;
+ + 
+ + 	case GPMC_PREFETCH_COUNT:
+ + 		regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
+ + 		status = GPMC_PREFETCH_STATUS_COUNT(regval);
+ + 		break;
+ + 
+ + 	case GPMC_STATUS_BUFFER:
+ + 		regval = gpmc_read_reg(GPMC_STATUS);
+ + 		/* 1 : buffer is available to write */
+ + 		status = regval & GPMC_STATUS_BUFF_EMPTY;
+ + 		break;
+ + 
+ + 	default:
+ + 		printk(KERN_ERR "gpmc_read_status: Not supported\n");
+ + 	}
+ + 	return status;
+ + }
+ + EXPORT_SYMBOL(gpmc_read_status);
+ + 
+ + /**
+ +  * gpmc_cs_configure - write request to configure gpmc
+ +  * @cs: chip select number
+ +  * @cmd: command type
+ +  * @wval: value to write
+ +  * @return status of the operation
+ +  */
+ + int gpmc_cs_configure(int cs, int cmd, int wval)
+ + {
+ + 	int err = 0;
+ + 	u32 regval = 0;
+ + 
+ + 	switch (cmd) {
+ + 	case GPMC_ENABLE_IRQ:
+ + 		gpmc_write_reg(GPMC_IRQENABLE, wval);
+ + 		break;
+ + 
+ + 	case GPMC_SET_IRQ_STATUS:
+ + 		gpmc_write_reg(GPMC_IRQSTATUS, wval);
+ + 		break;
+ + 
+ + 	case GPMC_CONFIG_WP:
+ + 		regval = gpmc_read_reg(GPMC_CONFIG);
+ + 		if (wval)
+ + 			regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
+ + 		else
+ + 			regval |= GPMC_CONFIG_WRITEPROTECT;  /* WP is OFF */
+ + 		gpmc_write_reg(GPMC_CONFIG, regval);
+ + 		break;
+ + 
+ + 	case GPMC_CONFIG_RDY_BSY:
+ + 		regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
+ + 		if (wval)
+ + 			regval |= WR_RD_PIN_MONITORING;
+ + 		else
+ + 			regval &= ~WR_RD_PIN_MONITORING;
+ + 		gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
+ + 		break;
+ + 
+ + 	case GPMC_CONFIG_DEV_SIZE:
+ + 		regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
+ + 		regval |= GPMC_CONFIG1_DEVICESIZE(wval);
+ + 		gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
+ + 		break;
+ + 
+ + 	case GPMC_CONFIG_DEV_TYPE:
+ + 		regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
+ + 		regval |= GPMC_CONFIG1_DEVICETYPE(wval);
+ + 		if (wval == GPMC_DEVICETYPE_NOR)
+ + 			regval |= GPMC_CONFIG1_MUXADDDATA;
+ + 		gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
+ + 		break;
+ + 
+ + 	default:
+ + 		printk(KERN_ERR "gpmc_configure_cs: Not supported\n");
+ + 		err = -EINVAL;
+ + 	}
+ + 
+ + 	return err;
+ + }
+ + EXPORT_SYMBOL(gpmc_cs_configure);
+ + 
+ + /**
+ +  * gpmc_nand_read - nand specific read access request
+ +  * @cs: chip select number
+ +  * @cmd: command type
+ +  */
+ + int gpmc_nand_read(int cs, int cmd)
+ + {
+ + 	int rval = -EINVAL;
+ + 
+ + 	switch (cmd) {
+ + 	case GPMC_NAND_DATA:
+ + 		rval = gpmc_cs_read_byte(cs, GPMC_CS_NAND_DATA);
+ + 		break;
+ + 
+ + 	default:
+ + 		printk(KERN_ERR "gpmc_read_nand_ctrl: Not supported\n");
+ + 	}
+ + 	return rval;
+ + }
+ + EXPORT_SYMBOL(gpmc_nand_read);
+ + 
+ + /**
+ +  * gpmc_nand_write - nand specific write request
+ +  * @cs: chip select number
+ +  * @cmd: command type
+ +  * @wval: value to write
+ +  */
+ + int gpmc_nand_write(int cs, int cmd, int wval)
+ + {
+ + 	int err = 0;
+ + 
+ + 	switch (cmd) {
+ + 	case GPMC_NAND_COMMAND:
+ + 		gpmc_cs_write_byte(cs, GPMC_CS_NAND_COMMAND, wval);
+ + 		break;
+ + 
+ + 	case GPMC_NAND_ADDRESS:
+ + 		gpmc_cs_write_byte(cs, GPMC_CS_NAND_ADDRESS, wval);
+ + 		break;
+ + 
+ + 	case GPMC_NAND_DATA:
+ + 		gpmc_cs_write_byte(cs, GPMC_CS_NAND_DATA, wval);
+ + 
+ + 	default:
+ + 		printk(KERN_ERR "gpmc_write_nand_ctrl: Not supported\n");
+ + 		err = -EINVAL;
+ + 	}
+ + 	return err;
+ + }
+ + EXPORT_SYMBOL(gpmc_nand_write);
+ + 
+ + 
+ + 
+ + /**
+ +  * gpmc_prefetch_enable - configures and starts prefetch transfer
+ +  * @cs: cs (chip select) number
+ +  * @fifo_th: fifo threshold to be used for read/ write
+ +  * @dma_mode: dma mode enable (1) or disable (0)
+ +  * @u32_count: number of bytes to be transferred
+ +  * @is_write: prefetch read(0) or write post(1) mode
+ +  */
+ + int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
+ + 				unsigned int u32_count, int is_write)
+ + {
+ + 
+ + 	if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) {
+ + 		pr_err("gpmc: fifo threshold is not supported\n");
+ + 		return -1;
+ + 	} else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
+ + 		/* Set the amount of bytes to be prefetched */
+ + 		gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
+ + 
+ + 		/* Set dma/mpu mode, the prefetch read / post write and
+ + 		 * enable the engine. Set which cs is has requested for.
+ + 		 */
+ + 		gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) |
+ + 					PREFETCH_FIFOTHRESHOLD(fifo_th) |
+ + 					ENABLE_PREFETCH |
+ + 					(dma_mode << DMA_MPU_MODE) |
+ + 					(0x1 & is_write)));
+ + 
+ + 		/*  Start the prefetch engine */
+ + 		gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1);
+ + 	} else {
+ + 		return -EBUSY;
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(gpmc_prefetch_enable);
+ + 
+ + /**
+ +  * gpmc_prefetch_reset - disables and stops the prefetch engine
+ +  */
+ + int gpmc_prefetch_reset(int cs)
+ + {
+ + 	u32 config1;
+ + 
+ + 	/* check if the same module/cs is trying to reset */
+ + 	config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
+ + 	if (((config1 >> CS_NUM_SHIFT) & 0x7) != cs)
+ + 		return -EINVAL;
+ + 
+ + 	/* Stop the PFPW engine */
+ + 	gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0);
+ + 
+ + 	/* Reset/disable the PFPW engine */
+ + 	gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x0);
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(gpmc_prefetch_reset);
+ + 
+ + static void __devinit gpmc_mem_init(void)
+ + {
+ + 	int cs;
+ + 	unsigned long boot_rom_space = 0;
+ + 
+ + 	/* never allocate the first page, to facilitate bug detection;
+ + 	 * even if we didn't boot from ROM.
+ + 	 */
+ + 	boot_rom_space = BOOT_ROM_SPACE;
+ + 	/* In apollon the CS0 is mapped as 0x0000 0000 */
+ + 	if (machine_is_omap_apollon())
+ + 		boot_rom_space = 0;
+ + 	gpmc->mem_root.start = GPMC_MEM_START + boot_rom_space;
+ + 	gpmc->mem_root.end = GPMC_MEM_END;
+ + 
+ + 	/* Reserve all regions that has been set up by bootloader */
+ + 	for (cs = 0; cs < GPMC_CS_NUM; cs++) {
+ + 		u32 base, size;
+ + 
+ + 		if (!gpmc_cs_mem_enabled(cs))
+ + 			continue;
+ + 		gpmc_cs_get_memconf(cs, &base, &size);
+ + 		if (gpmc_cs_insert_mem(cs, base, size) < 0)
+ + 			BUG();
+ + 	}
+ + }
+ + 
+ + struct device *gpmc_dev;
+ + 
+ + static int __devinit gpmc_probe(struct platform_device *pdev)
+ + {
+ + 	u32 l;
+ + 	int ret = -EINVAL;
+ + 	struct resource *res = NULL;
+ + 	struct gpmc_devices_info *gpmc_device = pdev->dev.platform_data;
+ + 	void *p;
+ + 
+ + 	/* XXX: This should go away with HWMOD & runtime PM adaptation */
+ + 	gpmc_clk_init(&pdev->dev);
+ + 
+ + 	gpmc_dev = &pdev->dev;
+ + 
+ + 	gpmc = devm_kzalloc(&pdev->dev, sizeof(struct gpmc), GFP_KERNEL);
+ + 	if (!gpmc)
+ + 		return -ENOMEM;
+ + 
+ + 	gpmc->dev = &pdev->dev;
+ + 
+ + 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ + 	if (!res) {
+ + 		ret = -ENOENT;
+ + 		dev_err(gpmc->dev, "Failed to get resource: memory\n");
+ + 		goto err_res;
+ + 	}
+ + 	gpmc->phys_base = res->start;
+ + 	gpmc->memsize = resource_size(res);
+ + 
+ + 	if (request_mem_region(gpmc->phys_base,
+ + 		gpmc->memsize, DRIVER_NAME) == NULL) {
+ + 		ret = -ENOMEM;
+ + 		dev_err(gpmc->dev, "Failed to request memory region\n");
+ + 		goto err_mem;
+ + 	}
+ + 
+ + 	gpmc->io_base = ioremap(gpmc->phys_base, gpmc->memsize);
+ + 	if (!gpmc->io_base) {
+ + 		ret = -ENOMEM;
+ + 		dev_err(gpmc->dev, "Failed to ioremap memory\n");
+ + 		goto err_remap;
+ + 	}
+ + 
+ + 	gpmc->ecc_used = -EINVAL;
+ + 	spin_lock_init(&gpmc->mem_lock);
+ + 	platform_set_drvdata(pdev, gpmc);
+ + 
+ + 	gpmc_write_reg(GPMC_SYSCONFIG, GPMC_SYSCONF_SIDLEMODE
+ + 						| GPMC_SYSCONF_SOFTRESET
+ + 						| GPMC_SYSCONF_AUTOIDLE);
+ + 
+ + 	l = gpmc_read_reg(GPMC_REVISION);
+ + 	dev_info(gpmc->dev, "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
+ + 
+ + 	gpmc_mem_init();
+ + 
+ + 	return 0;
+ + 
+ + err_remap:
+ + 	release_mem_region(gpmc->phys_base, gpmc->memsize);
+ + err_mem:
+ + err_res:
+ + 	devm_kfree(&pdev->dev, gpmc);
+ + 	return ret;
+ + }
+ + 
+ + static int __devexit gpmc_remove(struct platform_device *pdev)
+ + {
+ + 	struct gpmc *gpmc = platform_get_drvdata(pdev);
+ + 
+ + 	platform_set_drvdata(pdev, NULL);
+ + 	iounmap(gpmc->io_base);
+ + 	release_mem_region(gpmc->phys_base, gpmc->memsize);
+ + 	devm_kfree(&pdev->dev, gpmc);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static struct platform_driver gpmc_driver = {
+ + 	.probe		= gpmc_probe,
+ + 	.remove		= __devexit_p(gpmc_remove),
+ + 	.driver		= {
+ + 		.name	= DRIVER_NAME,
+ + 		.owner	= THIS_MODULE,
+ + 	},
+ + };
+ + 
+ + module_platform_driver(gpmc_driver);
+ + 
+ + int gpmc_suspend(void)
+ + {
+ + 	omap3_gpmc_save_context();
+ + 	pm_runtime_put_sync(gpmc_dev);
+ + 	return 0;
+ + }
+ + 
+ + int gpmc_resume(void)
+ + {
+ + 	pm_runtime_get_sync(gpmc_dev);
+ + 	omap3_gpmc_restore_context();
+ + 	return 0;
+ + }
+ + 
+ + static struct omap3_gpmc_regs gpmc_context;
+ + 
+ + void omap3_gpmc_save_context(void)
+ + {
+ + 	int i;
+ + 
+ + 	gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
+ + 	gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
+ + 	gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
+ + 	gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
+ + 	gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
+ + 	gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
+ + 	gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
+ + 	for (i = 0; i < GPMC_CS_NUM; i++) {
+ + 		gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
+ + 		if (gpmc_context.cs_context[i].is_valid) {
+ + 			gpmc_context.cs_context[i].config1 =
+ + 				gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
+ + 			gpmc_context.cs_context[i].config2 =
+ + 				gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
+ + 			gpmc_context.cs_context[i].config3 =
+ + 				gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
+ + 			gpmc_context.cs_context[i].config4 =
+ + 				gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
+ + 			gpmc_context.cs_context[i].config5 =
+ + 				gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
+ + 			gpmc_context.cs_context[i].config6 =
+ + 				gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
+ + 			gpmc_context.cs_context[i].config7 =
+ + 				gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
+ + 		}
+ + 	}
+ + }
+ + 
+ + void omap3_gpmc_restore_context(void)
+ + {
+ + 	int i;
+ + 
+ + 	gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
+ + 	gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
+ + 	gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
+ + 	gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
+ + 	gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
+ + 	gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
+ + 	gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
+ + 	for (i = 0; i < GPMC_CS_NUM; i++) {
+ + 		if (gpmc_context.cs_context[i].is_valid) {
+ + 			gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
+ + 				gpmc_context.cs_context[i].config1);
+ + 			gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
+ + 				gpmc_context.cs_context[i].config2);
+ + 			gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
+ + 				gpmc_context.cs_context[i].config3);
+ + 			gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
+ + 				gpmc_context.cs_context[i].config4);
+ + 			gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
+ + 				gpmc_context.cs_context[i].config5);
+ + 			gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
+ + 				gpmc_context.cs_context[i].config6);
+ + 			gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
+ + 				gpmc_context.cs_context[i].config7);
+ + 		}
+ + 	}
+ + }
+ + 
+ + /**
+ +  * gpmc_enable_hwecc - enable hardware ecc functionality
+ +  * @ecc_type: ecc type e.g. Hamming, BCH
+ +  * @cs: chip select number
+ +  * @mode: read/write mode
+ +  * @dev_width: device bus width(1 for x16, 0 for x8)
+ +  * @ecc_size: bytes for which ECC will be generated
+ +  */
+ + int gpmc_enable_hwecc(int ecc_type, int cs, int mode,
+ + 			int dev_width, int ecc_size)
+ + {
+ + 	unsigned int bch_mod = 0, bch_wrapmode = 0, eccsize1 = 0, eccsize0 = 0;
+ + 	unsigned int ecc_conf_val = 0, ecc_size_conf_val = 0;
+ + 
+ + 	switch (mode) {
+ + 	case GPMC_ECC_READ:
+ + 		if (ecc_type == OMAP_ECC_BCH4_CODE_HW) {
+ + 			eccsize1 = 0xD; eccsize0 = 0x48;
+ + 			bch_mod = 0;
+ + 			bch_wrapmode = 0x09;
+ + 		} else if (ecc_type == OMAP_ECC_BCH8_CODE_HW) {
+ + 			eccsize1 = 0x2; eccsize0 = 0x1A;
+ + 			bch_mod = 1;
+ + 			bch_wrapmode = 0x01;
+ + 		} else
+ + 			eccsize1 = ((ecc_size >> 1) - 1);
+ + 		break;
+ + 	case GPMC_ECC_READSYN:
+ + 		break;
+ + 	case GPMC_ECC_WRITE:
+ + 		if (ecc_type == OMAP_ECC_BCH4_CODE_HW) {
+ + 			eccsize1 = 0x20; eccsize0 = 0x00;
+ + 			bch_mod = 0;
+ + 			bch_wrapmode = 0x06;
+ + 		} else if (ecc_type == OMAP_ECC_BCH8_CODE_HW) {
+ + 			eccsize1 = 0x00; eccsize0 = 0x00;
+ + 			bch_mod = 1;
+ + 			bch_wrapmode = 0x01;
+ + 		} else
+ + 			eccsize1 = ((ecc_size >> 1) - 1);
+ + 		break;
+ + 	default:
+ + 		printk(KERN_INFO "Error: Unrecognized Mode[%d]!\n", mode);
+ + 		break;
+ + 	}
+ + 
+ + 	/* clear ecc and enable bits */
+ + 	if ((ecc_type == OMAP_ECC_BCH4_CODE_HW) ||
+ + 		(ecc_type == OMAP_ECC_BCH8_CODE_HW)) {
+ + 		gpmc_write_reg(GPMC_ECC_CONTROL, 0x00000001);
+ + 		ecc_size_conf_val = (eccsize1 << 22) | (eccsize0 << 12);
+ + 		ecc_conf_val = ((0x01 << 16) | (bch_mod << 12)
+ + 			| (bch_wrapmode << 8) | (dev_width << 7)
+ + 			| (0x00 << 4) | (cs << 1) | (0x1));
+ + 	} else {
+ + 		gpmc_write_reg(GPMC_ECC_CONTROL, 0x00000101);
+ + 		ecc_size_conf_val = (eccsize1 << 22) | 0x0000000F;
+ + 		ecc_conf_val = (dev_width << 7) | (cs << 1) | (0x1);
+ + 	}
+ + 
+ + 	gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, ecc_size_conf_val);
+ + 	gpmc_write_reg(GPMC_ECC_CONFIG, ecc_conf_val);
+ + 	gpmc_write_reg(GPMC_ECC_CONTROL, 0x00000101);
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(gpmc_enable_hwecc);
+ + 
+ + /**
+ +  * gpmc_calculate_ecc - generate non-inverted ecc bytes
+ +  * @ecc_type: ecc type e.g. Hamming, BCH
+ +  * @cs: chip select number
+ +  * @dat: data pointer over which ecc is computed
+ +  * @ecc_code: ecc code buffer
+ +  *
+ +  * Using non-inverted ECC is considered ugly since writing a blank
+ +  * page (padding) will clear the ECC bytes. This is not a problem as long
+ +  * no one is trying to write data on the seemingly unused page. Reading
+ +  * an erased page will produce an ECC mismatch between generated and read
+ +  * ECC bytes that has to be dealt with separately.
+ +  */
+ + int gpmc_calculate_ecc(int ecc_type, int cs,
+ + 		const u_char *dat, u_char *ecc_code)
+ + {
+ + 	unsigned int reg;
+ + 	unsigned int val1 = 0x0, val2 = 0x0;
+ + 	unsigned int val3 = 0x0, val4 = 0x0;
+ + 	int i;
+ + 
+ + 	if ((ecc_type == OMAP_ECC_BCH4_CODE_HW) ||
+ + 		(ecc_type == OMAP_ECC_BCH8_CODE_HW)) {
+ + 		for (i = 0; i < 1; i++) {
+ + 			/*
+ + 			 * Reading HW ECC_BCH_Results
+ + 			 * 0x240-0x24C, 0x250-0x25C, 0x260-0x26C, 0x270-0x27C
+ + 			 */
+ + 			reg =  GPMC_ECC_BCH_RESULT_0 + (0x10 * i);
+ + 			val1 = gpmc_read_reg(reg);
+ + 			val2 = gpmc_read_reg(reg + 4);
+ + 			if (ecc_type == OMAP_ECC_BCH8_CODE_HW) {
+ + 				val3 = gpmc_read_reg(reg + 8);
+ + 				val4 = gpmc_read_reg(reg + 12);
+ + 
+ + 				*ecc_code++ = (val4 & 0xFF);
+ + 				*ecc_code++ = ((val3 >> 24) & 0xFF);
+ + 				*ecc_code++ = ((val3 >> 16) & 0xFF);
+ + 				*ecc_code++ = ((val3 >> 8) & 0xFF);
+ + 				*ecc_code++ = (val3 & 0xFF);
+ + 				*ecc_code++ = ((val2 >> 24) & 0xFF);
+ + 			}
+ + 			*ecc_code++ = ((val2 >> 16) & 0xFF);
+ + 			*ecc_code++ = ((val2 >> 8) & 0xFF);
+ + 			*ecc_code++ = (val2 & 0xFF);
+ + 			*ecc_code++ = ((val1 >> 24) & 0xFF);
+ + 			*ecc_code++ = ((val1 >> 16) & 0xFF);
+ + 			*ecc_code++ = ((val1 >> 8) & 0xFF);
+ + 			*ecc_code++ = (val1 & 0xFF);
+ + 		}
+ + 	} else {
+ + 		/* read ecc result */
+ + 		val1 = gpmc_read_reg(GPMC_ECC1_RESULT);
+ + 		*ecc_code++ = val1;          /* P128e, ..., P1e */
+ + 		*ecc_code++ = val1 >> 16;    /* P128o, ..., P1o */
+ + 		/* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
+ + 		*ecc_code++ = ((val1 >> 8) & 0x0f) | ((val1 >> 20) & 0xf0);
+ + 	}
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(gpmc_calculate_ecc);
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/hsmmc.c linux-3.2.1/arch/arm/mach-ckb_3352/hsmmc.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/hsmmc.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/hsmmc.c	2014-11-25 13:19:14.987396928 +0900
+ ***************
+ *** 0 ****
+ --- 1,309 ----
+ + /*
+ +  * linux/arch/arm/mach-omap2/hsmmc.c
+ +  *
+ +  * Copyright (C) 2007-2008 Texas Instruments
+ +  * Copyright (C) 2008 Nokia Corporation
+ +  * Author: Texas Instruments
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + #include <linux/kernel.h>
+ + #include <linux/slab.h>
+ + #include <linux/string.h>
+ + #include <linux/delay.h>
+ + #include <linux/gpio.h>
+ + #include <mach/hardware.h>
+ + #include <plat/mmc.h>
+ + #include <plat/omap-pm.h>
+ + #include <plat/mux.h>
+ + #include <plat/omap_device.h>
+ + 
+ + #include "mux.h"
+ + #include "hsmmc.h"
+ + #include "control.h"
+ + 
+ + #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
+ + 
+ + static u16 control_pbias_offset;
+ + static u16 control_devconf1_offset;
+ + 
+ + #define HSMMC_NAME_LEN	9
+ + 
+ + #if defined(CONFIG_PM)
+ + 
+ + static int hsmmc_get_context_loss(struct device *dev)
+ + {
+ + 	return omap_pm_get_dev_context_loss_count(dev);
+ + }
+ + 
+ + #else
+ + #define hsmmc_get_context_loss NULL
+ + #endif
+ + 
+ + static void omap_hsmmc1_before_set_reg(struct device *dev, int slot,
+ + 				  int power_on, int vdd)
+ + {
+ + 	u32 reg, prog_io;
+ + 	struct omap_mmc_platform_data *mmc = dev->platform_data;
+ + 
+ + 	if (mmc->slots[0].remux)
+ + 		mmc->slots[0].remux(dev, slot, power_on);
+ + 
+ + 	/*
+ + 	 * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
+ + 	 * card with Vcc regulator (from twl4030 or whatever).  OMAP has both
+ + 	 * 1.8V and 3.0V modes, controlled by the PBIAS register.
+ + 	 *
+ + 	 * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
+ + 	 * is most naturally TWL VSIM; those pins also use PBIAS.
+ + 	 *
+ + 	 * FIXME handle VMMC1A as needed ...
+ + 	 */
+ + 	if (power_on) {
+ + 		if (mmc->slots[0].internal_clock) {
+ + 			reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+ + 			reg |= OMAP2_MMCSDIO1ADPCLKISEL;
+ + 			omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
+ + 		}
+ + 
+ + 		reg = omap_ctrl_readl(control_pbias_offset);
+ + 		reg |= OMAP2_PBIASSPEEDCTRL0;
+ + 		reg &= ~OMAP2_PBIASLITEPWRDNZ0;
+ + 		omap_ctrl_writel(reg, control_pbias_offset);
+ + 	} else {
+ + 		reg = omap_ctrl_readl(control_pbias_offset);
+ + 		reg &= ~OMAP2_PBIASLITEPWRDNZ0;
+ + 		omap_ctrl_writel(reg, control_pbias_offset);
+ + 	}
+ + }
+ + 
+ + static void omap_hsmmc1_after_set_reg(struct device *dev, int slot,
+ + 				 int power_on, int vdd)
+ + {
+ + 	u32 reg;
+ + 
+ + 	/* 100ms delay required for PBIAS configuration */
+ + 	msleep(100);
+ + 
+ + 	if (power_on) {
+ + 		reg = omap_ctrl_readl(control_pbias_offset);
+ + 		reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
+ + 		if ((1 << vdd) <= MMC_VDD_165_195)
+ + 			reg &= ~OMAP2_PBIASLITEVMODE0;
+ + 		else
+ + 			reg |= OMAP2_PBIASLITEVMODE0;
+ + 		omap_ctrl_writel(reg, control_pbias_offset);
+ + 	} else {
+ + 		reg = omap_ctrl_readl(control_pbias_offset);
+ + 		reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
+ + 			OMAP2_PBIASLITEVMODE0);
+ + 		omap_ctrl_writel(reg, control_pbias_offset);
+ + 	}
+ + }
+ + 
+ + static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc)
+ + {
+ + 	u32 reg;
+ + 
+ + 	if (mmc->slots[0].internal_clock) {
+ + 		reg = omap_ctrl_readl(control_devconf1_offset);
+ + 		reg |= OMAP2_MMCSDIO2ADPCLKISEL;
+ + 		omap_ctrl_writel(reg, control_devconf1_offset);
+ + 	}
+ + }
+ + 
+ + static void hsmmc23_before_set_reg(struct device *dev, int slot,
+ + 				   int power_on, int vdd)
+ + {
+ + 	struct omap_mmc_platform_data *mmc = dev->platform_data;
+ + 
+ + 	if (mmc->slots[0].remux)
+ + 		mmc->slots[0].remux(dev, slot, power_on);
+ + 
+ + 	if (power_on)
+ + 		hsmmc2_select_input_clk_src(mmc);
+ + }
+ + 
+ + 
+ + static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
+ + 							int vdd)
+ + {
+ + 	return 0;
+ + }
+ + 
+ + static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
+ + 					struct omap_mmc_platform_data *mmc)
+ + {
+ + 	char *hc_name;
+ + 
+ + 	hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
+ + 	if (!hc_name) {
+ + 		pr_err("Cannot allocate memory for controller slot name\n");
+ + 		kfree(hc_name);
+ + 		return -ENOMEM;
+ + 	}
+ + 
+ + 	mmc->version = MMC_CTRL_VERSION_2;
+ + 
+ + 	if (c->name)
+ + 		strncpy(hc_name, c->name, HSMMC_NAME_LEN);
+ + 	else
+ + 		snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
+ + 								c->mmc, 1);
+ + 	mmc->slots[0].name = hc_name;
+ + 	mmc->nr_slots = 1;
+ + 	mmc->slots[0].caps = c->caps;
+ + 	mmc->slots[0].pm_caps = c->pm_caps;
+ + 	mmc->slots[0].internal_clock = !c->ext_clock;
+ + 	mmc->dma_mask = 0xffffffff;
+ + 	mmc->reg_offset = 0;
+ + 
+ + 	mmc->get_context_loss_count = hsmmc_get_context_loss;
+ + 
+ + 	mmc->slots[0].switch_pin = c->gpio_cd;
+ + 	mmc->slots[0].gpio_wp = c->gpio_wp;
+ + 
+ + 	mmc->slots[0].remux = c->remux;
+ + 	mmc->slots[0].init_card = c->init_card;
+ + 
+ + 	if (c->cover_only)
+ + 		mmc->slots[0].cover = 1;
+ + 
+ + 	if (c->nonremovable)
+ + 		mmc->slots[0].nonremovable = 1;
+ + 
+ + 	if (c->power_saving)
+ + 		mmc->slots[0].power_saving = 1;
+ + 
+ + 	if (c->no_off)
+ + 		mmc->slots[0].no_off = 1;
+ + 
+ + 	if (c->no_off_init)
+ + 		mmc->slots[0].no_regulator_off_init = c->no_off_init;
+ + 
+ + 	if (c->vcc_aux_disable_is_sleep)
+ + 		mmc->slots[0].vcc_aux_disable_is_sleep = 1;
+ + 
+ + 	/*
+ + 	 * NOTE:  MMC slots should have a Vcc regulator set up.
+ + 	 * This may be from a TWL4030-family chip, another
+ + 	 * controllable regulator, or a fixed supply.
+ + 	 *
+ + 	 * temporary HACK: ocr_mask instead of fixed supply
+ + 	 */
+ + 	mmc->slots[0].ocr_mask = c->ocr_mask;
+ + 
+ + 	mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
+ + 
+ + 	switch (c->mmc) {
+ + 	case 1:
+ + 		if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
+ + 			mmc->slots[0].before_set_reg =
+ + 					omap_hsmmc1_before_set_reg;
+ + 			mmc->slots[0].after_set_reg =
+ + 					omap_hsmmc1_after_set_reg;
+ + 		}
+ + 		mmc->slots[0].set_power = nop_mmc_set_power;
+ + 		break;
+ + 	case 2:
+ + 		mmc->slots[0].set_power = nop_mmc_set_power;
+ + 
+ + 		if (c->ext_clock)
+ + 			c->transceiver = 1;
+ + 		if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
+ + 			c->caps &= ~MMC_CAP_8_BIT_DATA;
+ + 			c->caps |= MMC_CAP_4_BIT_DATA;
+ + 		}
+ + 		/* FALLTHROUGH */
+ + 	case 3:
+ + 		if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
+ + 			/* off-chip level shifting, or none */
+ + 			mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
+ + 			mmc->slots[0].after_set_reg = NULL;
+ + 		}
+ + 		break;
+ + 	case 4:
+ + 	case 5:
+ + 		mmc->slots[0].before_set_reg = NULL;
+ + 		mmc->slots[0].after_set_reg = NULL;
+ + 		break;
+ + 	default:
+ + 		pr_err("MMC%d configuration not supported!\n", c->mmc);
+ + 		kfree(hc_name);
+ + 		return -ENODEV;
+ + 	}
+ + 	return 0;
+ + }
+ + 
+ + #define MAX_OMAP_MMC_HWMOD_NAME_LEN		16
+ + 
+ + void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo)
+ + {
+ + 	struct omap_hwmod *oh;
+ + 	struct platform_device *pdev;
+ + 	char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
+ + 	struct omap_mmc_platform_data *mmc_data;
+ + 	struct omap_mmc_dev_attr *mmc_dev_attr;
+ + 	char *name;
+ + 	int l;
+ + 	int ctrl_nr;
+ + 
+ + 	mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
+ + 	if (!mmc_data) {
+ + 		pr_err("Cannot allocate memory for mmc device!\n");
+ + 		goto done;
+ + 	}
+ + 
+ + 	if (omap_hsmmc_pdata_init(hsmmcinfo, mmc_data) < 0) {
+ + 		pr_err("%s fails!\n", __func__);
+ + 		goto done;
+ + 	}
+ + 
+ + 	ctrl_nr = hsmmcinfo->mmc;
+ + 	name = "omap_hsmmc";
+ + 
+ + 	
+ + 	
+ + 	l = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
+ + 		     "mmc%d", ctrl_nr);
+ + 	
+ + 	WARN(l >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
+ + 	     "String buffer overflow in MMC%d device setup\n", ctrl_nr);
+ + 	oh = omap_hwmod_lookup(oh_name);
+ + 	if (!oh) {
+ + 		pr_err("Could not look up %s\n", oh_name);
+ + 		kfree(mmc_data->slots[0].name);
+ + 		goto done;
+ + 	}
+ + 
+ + 	if (oh->dev_attr != NULL) {
+ + 		mmc_dev_attr = oh->dev_attr;
+ + 		mmc_data->controller_flags = mmc_dev_attr->flags;
+ + 	}
+ + 
+ + 	pdev = omap_device_build(name, ctrl_nr - 1, oh, mmc_data,
+ + 		sizeof(struct omap_mmc_platform_data), NULL, 0, false);
+ + 	if (IS_ERR(pdev)) {
+ + 		WARN(1, "Can't build omap_device for %s:%s.\n", name, oh->name);
+ + 		kfree(mmc_data->slots[0].name);
+ + 		goto done;
+ + 	}
+ + 	/*
+ + 	 * return device handle to board setup code
+ + 	 * required to populate for regulator framework structure
+ + 	 */
+ + 	hsmmcinfo->dev = &pdev->dev;
+ + 
+ + done:
+ + 	kfree(mmc_data);
+ + }
+ + 
+ + void __init omap2_hsmmc_init()
+ + {
+ + 	control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
+ + 	control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
+ + }
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/hsmmc.h linux-3.2.1/arch/arm/mach-ckb_3352/hsmmc.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/hsmmc.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/hsmmc.h	2014-11-25 13:19:14.991017085 +0900
+ ***************
+ *** 0 ****
+ --- 1,49 ----
+ + /*
+ +  * MMC definitions for OMAP2
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + struct mmc_card;
+ + 
+ + struct omap2_hsmmc_info {
+ + 	u8	mmc;		/* controller 1/2/3 */
+ + 	u32	caps;		/* 4/8 wires and any additional host
+ + 				 * capabilities OR'd (ref. linux/mmc/host.h) */
+ + 	u32	pm_caps;	/* PM capabilities */
+ + 	bool	transceiver;	/* MMC-2 option */
+ + 	bool	ext_clock;	/* use external pin for input clock */
+ + 	bool	cover_only;	/* No card detect - just cover switch */
+ + 	bool	nonremovable;	/* Nonremovable e.g. eMMC */
+ + 	bool	power_saving;	/* Try to sleep or power off when possible */
+ + 	bool	no_off;		/* power_saving and power is not to go off */
+ + 	bool	no_off_init;	/* no power off when not in MMC sleep state */
+ + 	bool	vcc_aux_disable_is_sleep; /* Regulator off remapped to sleep */
+ + 	int	gpio_cd;	/* or -EINVAL */
+ + 	int	gpio_wp;	/* or -EINVAL */
+ + 	char	*name;		/* or NULL for default */
+ + 	struct device *dev;	/* returned: pointer to mmc adapter */
+ + 	int	ocr_mask;	/* temporary HACK */
+ + 	/* Remux (pad configuration) when powering on/off */
+ + 	void (*remux)(struct device *dev, int slot, int power_on);
+ + 	/* init some special card */
+ + 	void (*init_card)(struct mmc_card *card);
+ + };
+ + 
+ + #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
+ + 
+ + void omap2_hsmmc_init(void);
+ + void omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo);
+ + 
+ + #else
+ + 
+ + static inline void omap2_hsmmc_init(void)
+ + {
+ + }
+ + 
+ + void omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo)
+ + {
+ + }
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/hwspinlock.c linux-3.2.1/arch/arm/mach-ckb_3352/hwspinlock.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/hwspinlock.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/hwspinlock.c	2014-11-25 13:19:14.991017085 +0900
+ ***************
+ *** 0 ****
+ --- 1,60 ----
+ + /*
+ +  * OMAP hardware spinlock device initialization
+ +  *
+ +  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
+ +  *
+ +  * Contact: Simon Que <sque@ti.com>
+ +  *          Hari Kanigeri <h-kanigeri2@ti.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License
+ +  * version 2 as published by the Free Software Foundation.
+ +  *
+ +  * This program is distributed in the hope that it will be useful, but
+ +  * WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ +  * General Public License for more details.
+ +  */
+ + 
+ + #include <linux/kernel.h>
+ + #include <linux/init.h>
+ + #include <linux/err.h>
+ + #include <linux/hwspinlock.h>
+ + 
+ + #include <plat/omap_hwmod.h>
+ + #include <plat/omap_device.h>
+ + 
+ + static struct hwspinlock_pdata omap_hwspinlock_pdata __initdata = {
+ + 	.base_id = 0,
+ + };
+ + 
+ + int __init hwspinlocks_init(void)
+ + {
+ + 	int retval = 0;
+ + 	struct omap_hwmod *oh;
+ + 	struct platform_device *pdev;
+ + 	const char *oh_name = "spinlock";
+ + 	const char *dev_name = "omap_hwspinlock";
+ + 
+ + 	/*
+ + 	 * Hwmod lookup will fail in case our platform doesn't support the
+ + 	 * hardware spinlock module, so it is safe to run this initcall
+ + 	 * on all omaps
+ + 	 */
+ + 	oh = omap_hwmod_lookup(oh_name);
+ + 	if (oh == NULL)
+ + 		return -EINVAL;
+ + 
+ + 	pdev = omap_device_build(dev_name, 0, oh, &omap_hwspinlock_pdata,
+ + 				sizeof(struct hwspinlock_pdata),
+ + 				NULL, 0, false);
+ + 	if (IS_ERR(pdev)) {
+ + 		pr_err("Can't build omap_device for %s:%s\n", dev_name,
+ + 								oh_name);
+ + 		retval = PTR_ERR(pdev);
+ + 	}
+ + 
+ + 	return retval;
+ + }
+ + /* early board code might need to reserve specific hwspinlock instances */
+ + postcore_initcall(hwspinlocks_init);
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/i2c.c linux-3.2.1/arch/arm/mach-ckb_3352/i2c.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/i2c.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/i2c.c	2014-11-25 13:19:14.991017085 +0900
+ ***************
+ *** 0 ****
+ --- 1,107 ----
+ + /*
+ +  * Helper module for board specific I2C bus registration
+ +  *
+ +  * Copyright (C) 2009 Nokia Corporation.
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License
+ +  * version 2 as published by the Free Software Foundation.
+ +  *
+ +  * This program is distributed in the hope that it will be useful, but
+ +  * WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ +  * General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ +  * 02110-1301 USA
+ +  *
+ +  */
+ + 
+ + #include <plat/cpu.h>
+ + #include <plat/i2c.h>
+ + #include "common.h"
+ + #include <plat/omap_hwmod.h>
+ + 
+ + #include "mux.h"
+ + 
+ + /* In register I2C_CON, Bit 15 is the I2C enable bit */
+ + #define I2C_EN					BIT(15)
+ + #define OMAP2_I2C_CON_OFFSET			0x24
+ + #define OMAP4_I2C_CON_OFFSET			0xA4
+ + 
+ + /* Maximum microseconds to wait for OMAP module to softreset */
+ + #define MAX_MODULE_SOFTRESET_WAIT	10000
+ + 
+ + void __init omap2_i2c_mux_pins(int bus_id)
+ + {
+ + 	char mux_name[sizeof("i2c2_scl.i2c2_scl")];
+ + 
+ + 	/* First I2C bus is not muxable */
+ + 	if (bus_id == 1)
+ + 		return;
+ + 
+ + 	sprintf(mux_name, "i2c%i_scl.i2c%i_scl", bus_id, bus_id);
+ + 	omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
+ + 	sprintf(mux_name, "i2c%i_sda.i2c%i_sda", bus_id, bus_id);
+ + 	omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
+ + }
+ + 
+ + /**
+ +  * omap_i2c_reset - reset the omap i2c module.
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * The i2c moudle in omap2, omap3 had a special sequence to reset. The
+ +  * sequence is:
+ +  * - Disable the I2C.
+ +  * - Write to SOFTRESET bit.
+ +  * - Enable the I2C.
+ +  * - Poll on the RESETDONE bit.
+ +  * The sequence is implemented in below function. This is called for 2420,
+ +  * 2430 and omap3.
+ +  */
+ + int omap_i2c_reset(struct omap_hwmod *oh)
+ + {
+ + 	u32 v;
+ + 	u16 i2c_con;
+ + 	int c = 0;
+ + 
+ + 	if (oh->class->rev == OMAP_I2C_IP_VERSION_2) {
+ + 		i2c_con = OMAP4_I2C_CON_OFFSET;
+ + 	} else if (oh->class->rev == OMAP_I2C_IP_VERSION_1) {
+ + 		i2c_con = OMAP2_I2C_CON_OFFSET;
+ + 	} else {
+ + 		WARN(1, "Cannot reset I2C block %s: unsupported revision\n",
+ + 		     oh->name);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	/* Disable I2C */
+ + 	v = omap_hwmod_read(oh, i2c_con);
+ + 	v &= ~I2C_EN;
+ + 	omap_hwmod_write(v, oh, i2c_con);
+ + 
+ + 	/* Write to the SOFTRESET bit */
+ + 	omap_hwmod_softreset(oh);
+ + 
+ + 	/* Enable I2C */
+ + 	v = omap_hwmod_read(oh, i2c_con);
+ + 	v |= I2C_EN;
+ + 	omap_hwmod_write(v, oh, i2c_con);
+ + 
+ + 	/* Poll on RESETDONE bit */
+ + 	omap_test_timeout((omap_hwmod_read(oh,
+ + 				oh->class->sysc->syss_offs)
+ + 				& SYSS_RESETDONE_MASK),
+ + 				MAX_MODULE_SOFTRESET_WAIT, c);
+ + 
+ + 	if (c == MAX_MODULE_SOFTRESET_WAIT)
+ + 		pr_warning("%s: %s: softreset failed (waited %d usec)\n",
+ + 			__func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
+ + 	else
+ + 		pr_debug("%s: %s: softreset in %d usec\n", __func__,
+ + 			oh->name, c);
+ + 
+ + 	return 0;
+ + }
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/asp.h linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/asp.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/asp.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/asp.h	2014-11-25 13:19:14.991017085 +0900
+ ***************
+ *** 0 ****
+ --- 1,139 ----
+ + /*
+ +  * <asm/hardware/asp.h> - DaVinci Audio Serial Port support
+ +  */
+ + #ifndef __ASM_HARDWARE_MCASP_H
+ + #define __ASM_HARDWARE_MCASP_H
+ + 
+ + #include <mach/irqs.h>
+ + #include <mach/edma.h>
+ + 
+ + /* Bases of dm644x and dm355 register banks */
+ + #define DAVINCI_ASP0_BASE	0x01E02000
+ + #define DAVINCI_ASP1_BASE	0x01E04000
+ + 
+ + /* Bases of dm365 register banks */
+ + #define DAVINCI_DM365_ASP0_BASE	0x01D02000
+ + 
+ + /* Bases of dm646x register banks */
+ + #define	DAVINCI_DM646X_MCASP0_REG_BASE		0x01D01000
+ + #define DAVINCI_DM646X_MCASP1_REG_BASE		0x01D01800
+ + 
+ + /* Bases of da850/da830 McASP0  register banks */
+ + #define DAVINCI_DA8XX_MCASP0_REG_BASE	0x01D00000
+ + 
+ + /* Bases of da830 McASP1 register banks */
+ + #define DAVINCI_DA830_MCASP1_REG_BASE	0x01D04000
+ + 
+ + /* EDMA channels of dm644x and dm355 */
+ + #define DAVINCI_DMA_ASP0_TX	2
+ + #define DAVINCI_DMA_ASP0_RX	3
+ + #define DAVINCI_DMA_ASP1_TX	8
+ + #define DAVINCI_DMA_ASP1_RX	9
+ + 
+ + /* EDMA channels of dm646x */
+ + #define	DAVINCI_DM646X_DMA_MCASP0_AXEVT0	6
+ + #define	DAVINCI_DM646X_DMA_MCASP0_AREVT0	9
+ + #define	DAVINCI_DM646X_DMA_MCASP1_AXEVT1	12
+ + 
+ + /* EDMA channels of da850/da830 McASP0 */
+ + #define	DAVINCI_DA8XX_DMA_MCASP0_AREVT	0
+ + #define	DAVINCI_DA8XX_DMA_MCASP0_AXEVT	1
+ + 
+ + /* EDMA channels of da830 McASP1 */
+ + #define	DAVINCI_DA830_DMA_MCASP1_AREVT	2
+ + #define	DAVINCI_DA830_DMA_MCASP1_AXEVT	3
+ + 
+ + /* Interrupts */
+ + #define DAVINCI_ASP0_RX_INT	IRQ_MBRINT
+ + #define DAVINCI_ASP0_TX_INT	IRQ_MBXINT
+ + #define DAVINCI_ASP1_RX_INT	IRQ_MBRINT
+ + #define DAVINCI_ASP1_TX_INT	IRQ_MBXINT
+ + 
+ + struct snd_platform_data {
+ + 	u32 tx_dma_offset;
+ + 	u32 rx_dma_offset;
+ + 	enum dma_event_q asp_chan_q;	/* event queue number for ASP channel */
+ + 	enum dma_event_q ram_chan_q;	/* event queue number for RAM channel */
+ + 	unsigned int codec_fmt;
+ + 	/*
+ + 	 * Allowing this is more efficient and eliminates left and right swaps
+ + 	 * caused by underruns, but will swap the left and right channels
+ + 	 * when compared to previous behavior.
+ + 	 */
+ + 	unsigned enable_channel_combine:1;
+ + 	unsigned sram_size_playback;
+ + 	unsigned sram_size_capture;
+ + 
+ + 	/*
+ + 	 * If McBSP peripheral gets the clock from an external pin,
+ + 	 * there are three chooses, that are MCBSP_CLKX, MCBSP_CLKR
+ + 	 * and MCBSP_CLKS.
+ + 	 * Depending on different hardware connections it is possible
+ + 	 * to use this setting to change the behaviour of McBSP
+ + 	 * driver. The dm365_clk_input_pin enum is available for dm365
+ + 	 */
+ + 	int clk_input_pin;
+ + 
+ + 	/*
+ + 	 * This flag works when both clock and FS are outputs for the cpu
+ + 	 * and makes clock more accurate (FS is not symmetrical and the
+ + 	 * clock is very fast.
+ + 	 * The clock becoming faster is named
+ + 	 * i2s continuous serial clock (I2S_SCK) and it is an externally
+ + 	 * visible bit clock.
+ + 	 *
+ + 	 * first line : WordSelect
+ + 	 * second line : ContinuousSerialClock
+ + 	 * third line: SerialData
+ + 	 *
+ + 	 * SYMMETRICAL APPROACH:
+ + 	 *   _______________________          LEFT
+ + 	 * _|         RIGHT         |______________________|
+ + 	 *     _   _         _   _   _   _         _   _
+ + 	 *   _| |_| |_ x16 _| |_| |_| |_| |_ x16 _| |_| |_
+ + 	 *     _   _         _   _   _   _         _   _
+ + 	 *   _/ \_/ \_ ... _/ \_/ \_/ \_/ \_ ... _/ \_/ \_
+ + 	 *    \_/ \_/       \_/ \_/ \_/ \_/       \_/ \_/
+ + 	 *
+ + 	 * ACCURATE CLOCK APPROACH:
+ + 	 *   ______________          LEFT
+ + 	 * _|     RIGHT    |_______________________________|
+ + 	 *     _         _   _         _   _   _   _   _   _
+ + 	 *   _| |_ x16 _| |_| |_ x16 _| |_| |_| |_| |_| |_| |
+ + 	 *     _         _   _          _      dummy cycles
+ + 	 *   _/ \_ ... _/ \_/ \_  ... _/ \__________________
+ + 	 *    \_/       \_/ \_/        \_/
+ + 	 *
+ + 	 */
+ + 	bool i2s_accurate_sck;
+ + 
+ + 	/* McASP specific fields */
+ + 	int tdm_slots;
+ + 	u8 op_mode;
+ + 	u8 num_serializer;
+ + 	u8 *serial_dir;
+ + 	u8 version;
+ + 	u8 txnumevt;
+ + 	u8 rxnumevt;
+ + };
+ + 
+ + enum {
+ + 	MCASP_VERSION_1 = 0,	/* DM646x */
+ + 	MCASP_VERSION_2,	/* DA8xx/OMAPL1x */
+ + 	MCASP_VERSION_3,	/* AM33xx */
+ + };
+ + 
+ + enum dm365_clk_input_pin {
+ + 	MCBSP_CLKR = 0,		/* DM365 */
+ + 	MCBSP_CLKS,
+ + };
+ + 
+ + #define INACTIVE_MODE	0
+ + #define TX_MODE		1
+ + #define RX_MODE		2
+ + 
+ + #define DAVINCI_MCASP_IIS_MODE	0
+ + #define DAVINCI_MCASP_DIT_MODE	1
+ + 
+ + 
+ + #endif /* __ASM_HARDWARE_MCASP_H */
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/barriers.h linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/barriers.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/barriers.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/barriers.h	2014-11-25 13:19:14.991017085 +0900
+ ***************
+ *** 0 ****
+ --- 1,31 ----
+ + /*
+ +  * OMAP memory barrier header.
+ +  *
+ +  * Copyright (C) 2011 Texas Instruments, Inc.
+ +  *  Santosh Shilimkar <santosh.shilimkar@ti.com>
+ +  *  Richard Woodruff <r-woodruff2@ti.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ +  */
+ + 
+ + #ifndef __MACH_BARRIERS_H
+ + #define __MACH_BARRIERS_H
+ + 
+ + extern void omap_bus_sync(void);
+ + 
+ + #define rmb()		dsb()
+ + #define wmb()		do { dsb(); outer_sync(); omap_bus_sync(); } while (0)
+ + #define mb()		wmb()
+ + 
+ + #endif	/* __MACH_BARRIERS_H */
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/ckb_3352.h linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/ckb_3352.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/ckb_3352.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/ckb_3352.h	2014-11-25 13:19:14.995356189 +0900
+ ***************
+ *** 0 ****
+ --- 1,31 ----
+ + /*
+ +  * Header containing CKB info
+ +  *
+ +  * Copyright (C) 2013 Computex Co.Ltd.
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; version 2 of the License.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ +  *
+ +  */
+ +  
+ + #ifndef __ASM_MACH_CKB_3352_H
+ + #define __ASM_MACH_CKB_3352_H
+ + 
+ + typedef struct {
+ + 	unsigned char id;
+ + 	unsigned char mac[ETH_ALEN];
+ + }ckb_3352_eeprom_mac_address;
+ + 
+ + #define CKB_3352_MAC_HEADER		0x5A
+ + 
+ + #endif  /*  __ASM_MACH_CKB_3352_H */
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/ckb_3352_mem.h linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/ckb_3352_mem.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/ckb_3352_mem.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/ckb_3352_mem.h	2014-11-25 13:19:14.995356189 +0900
+ ***************
+ *** 0 ****
+ --- 1,28 ----
+ + /*
+ +  * Header containing CKB memory info
+ +  *
+ +  * Copyright (C) 2013 Computex Co.Ltd.
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; version 2 of the License.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ +  *
+ +  */
+ +  
+ + #ifndef __ASM_MACH_CKB_3352_MEM_H
+ + #define __ASM_MACH_CKB_3352_MEM_H
+ + 
+ + extern unsigned long FB_DATA_ADDRESS;
+ + extern unsigned long FB_DATA_VADDRESS;
+ + extern unsigned long FB_MAP_SIZE;
+ + 
+ + #endif  /*  __ASM_MACH_CKB_3352_MEM_H */
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/debug-macro.S linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/debug-macro.S
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/debug-macro.S	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/debug-macro.S	2014-11-25 13:19:14.995356189 +0900
+ ***************
+ *** 0 ****
+ --- 1,169 ----
+ + /* arch/arm/mach-omap2/include/mach/debug-macro.S
+ +  *
+ +  * Debugging macro include header
+ +  *
+ +  *  Copyright (C) 1994-1999 Russell King
+ +  *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  *
+ + */
+ + 
+ + #include <linux/serial_reg.h>
+ + 
+ + #include <plat/serial.h>
+ + 
+ + #define UART_OFFSET(addr)	((addr) & 0x00ffffff)
+ + 
+ + 		.pushsection .data
+ + omap_uart_phys:	.word	0
+ + omap_uart_virt:	.word	0
+ + omap_uart_lsr:	.word	0
+ + 		.popsection
+ + 
+ + 		/*
+ + 		 * Note that this code won't work if the bootloader passes
+ + 		 * a wrong machine ID number in r1. To debug, just hardcode
+ + 		 * the desired UART phys and virt addresses temporarily into
+ + 		 * the omap_uart_phys and omap_uart_virt above.
+ + 		 */
+ + 		.macro	addruart, rp, rv, tmp
+ + 
+ + 		/* Use omap_uart_phys/virt if already configured */
+ + 10:		adr	\rp, 99f		@ get effective addr of 99f
+ + 		ldr	\rv, [\rp]		@ get absolute addr of 99f
+ + 		sub	\rv, \rv, \rp		@ offset between the two
+ + 		ldr	\rp, [\rp, #4]		@ abs addr of omap_uart_phys
+ + 		sub	\tmp, \rp, \rv		@ make it effective
+ + 		ldr	\rp, [\tmp, #0]		@ omap_uart_phys
+ + 		ldr	\rv, [\tmp, #4]		@ omap_uart_virt
+ + 		cmp	\rp, #0			@ is port configured?
+ + 		cmpne	\rv, #0
+ + 		bne	100f			@ already configured
+ + 
+ + 		/* Check the debug UART configuration set in uncompress.h */
+ + 		mov	\rp, pc
+ + 		ldr	\rv, =OMAP_UART_INFO_OFS
+ + 		and	\rp, \rp, #0xff000000
+ + 		ldr	\rp, [\rp, \rv]
+ + 
+ + 		/* Select the UART to use based on the UART1 scratchpad value */
+ + 		cmp	\rp, #0			@ no port configured?
+ + 		beq	21f			@ if none, try to use UART1
+ + 		cmp	\rp, #OMAP2UART1	@ OMAP2/3/4UART1
+ + 		beq	21f			@ configure OMAP2/3/4UART1
+ + 		cmp	\rp, #OMAP2UART2	@ OMAP2/3/4UART2
+ + 		beq	22f			@ configure OMAP2/3/4UART2
+ + 		cmp	\rp, #OMAP2UART3	@ only on 24xx
+ + 		beq	23f			@ configure OMAP2UART3
+ + 		cmp	\rp, #OMAP3UART3	@ only on 34xx
+ + 		beq	33f			@ configure OMAP3UART3
+ + 		cmp	\rp, #OMAP4UART3	@ only on 44xx
+ + 		beq	43f			@ configure OMAP4UART3
+ + 		cmp	\rp, #OMAP3UART4	@ only on 36xx
+ + 		beq	34f			@ configure OMAP3UART4
+ + 		cmp	\rp, #OMAP4UART4	@ only on 44xx
+ + 		beq	44f			@ configure OMAP4UART4
+ + 		cmp	\rp, #TI81XXUART1	@ ti81Xx UART offsets different
+ + 		beq	81f			@ configure UART1
+ + 		cmp	\rp, #TI81XXUART2	@ ti81Xx UART offsets different
+ + 		beq	82f			@ configure UART2
+ + 		cmp	\rp, #TI81XXUART3	@ ti81Xx UART offsets different
+ + 		beq	83f			@ configure UART3
+ + 		cmp	\rp, #AM33XXUART1	@ AM33XX UART offsets different
+ + 		beq	84f			@ configure UART1
+ + 		cmp	\rp, #AM33XXUART4	@ AM33XX UART offsets different
+ + 		beq	85f			@ configure UART1
+ + 		cmp	\rp, #ZOOM_UART		@ only on zoom2/3
+ + 		beq	95f			@ configure ZOOM_UART
+ + 
+ + 		/* Configure the UART offset from the phys/virt base */
+ + 21:		mov	\rp, #UART_OFFSET(OMAP2_UART1_BASE)	@ omap2/3/4
+ + 		b	98f
+ + 22:		mov	\rp, #UART_OFFSET(OMAP2_UART2_BASE)	@ omap2/3/4
+ + 		b	98f
+ + 23:		mov	\rp, #UART_OFFSET(OMAP2_UART3_BASE)
+ + 		b	98f
+ + 33:		mov	\rp, #UART_OFFSET(OMAP3_UART1_BASE)
+ + 		add	\rp, \rp, #0x00fb0000
+ + 		add	\rp, \rp, #0x00006000		@ OMAP3_UART3_BASE
+ + 		b	98f
+ + 34:		mov	\rp, #UART_OFFSET(OMAP3_UART1_BASE)
+ + 		add	\rp, \rp, #0x00fb0000
+ + 		add	\rp, \rp, #0x00028000		@ OMAP3_UART4_BASE
+ + 		b	98f
+ + 43:		mov	\rp, #UART_OFFSET(OMAP4_UART3_BASE)
+ + 		b	98f
+ + 44:		mov	\rp, #UART_OFFSET(OMAP4_UART4_BASE)
+ + 		b	98f
+ + 81:		mov	\rp, #UART_OFFSET(TI81XX_UART1_BASE)
+ + 		b	98f
+ + 82:		mov	\rp, #UART_OFFSET(TI81XX_UART2_BASE)
+ + 		b	98f
+ + 83:		mov	\rp, #UART_OFFSET(TI81XX_UART3_BASE)
+ + 		b	98f
+ + 84:		ldr	\rp, =AM33XX_UART1_BASE
+ + 		and	\rp, \rp, #0x00ffffff
+ + 		b	97f
+ + 85:		ldr	\rp, =UART_OFFSET(AM33XX_UART4_BASE)
+ + 		b	98f
+ + 95:		ldr	\rp, =ZOOM_UART_BASE
+ + 		str	\rp, [\tmp, #0]		@ omap_uart_phys
+ + 		ldr	\rp, =ZOOM_UART_VIRT
+ + 		str	\rp, [\tmp, #4]		@ omap_uart_virt
+ + 		mov	\rp, #(UART_LSR << ZOOM_PORT_SHIFT)
+ + 		str	\rp, [\tmp, #8]		@ omap_uart_lsr
+ + 		b	10b
+ + 
+ + 		/* AM33XX: Store both phys and virt address for the uart */
+ + 97:		add	\rp, \rp, #0x44000000	@ phys base
+ + 		str	\rp, [\tmp, #0]		@ omap_uart_phys
+ + 		sub	\rp, \rp, #0x44000000	@ phys base
+ + 		add	\rp, \rp, #0xf9000000	@ virt base
+ + 		str	\rp, [\tmp, #4]		@ omap_uart_virt
+ + 		mov	\rp, #(UART_LSR << OMAP_PORT_SHIFT)
+ + 		str	\rp, [\tmp, #8]		@ omap_uart_lsr
+ + 
+ + 		b	10b
+ + 
+ + 		/* Store both phys and virt address for the uart */
+ + 98:		add	\rp, \rp, #0x48000000	@ phys base
+ + 		str	\rp, [\tmp, #0]		@ omap_uart_phys
+ + 		sub	\rp, \rp, #0x48000000	@ phys base
+ + 		add	\rp, \rp, #0xfa000000	@ virt base
+ + 		str	\rp, [\tmp, #4]		@ omap_uart_virt
+ + 		mov	\rp, #(UART_LSR << OMAP_PORT_SHIFT)
+ + 		str	\rp, [\tmp, #8]		@ omap_uart_lsr
+ + 
+ + 		b	10b
+ + 
+ + 		.align
+ + 99:		.word	.
+ + 		.word	omap_uart_phys
+ + 		.ltorg
+ + 
+ + 100:		/* Pass the UART_LSR reg address */
+ + 		ldr	\tmp, [\tmp, #8]	@ omap_uart_lsr
+ + 		add	\rp, \rp, \tmp
+ + 		add	\rv, \rv, \tmp
+ + 		.endm
+ + 
+ + 		.macro	senduart,rd,rx
+ + 		orr	\rd, \rd, \rx, lsl #24	@ preserve LSR reg offset
+ + 		bic	\rx, \rx, #0xff		@ get base (THR) reg address
+ + 		strb	\rd, [\rx]		@ send lower byte of rd
+ + 		orr	\rx, \rx, \rd, lsr #24	@ restore original rx (LSR)
+ + 		bic	\rd, \rd, #(0xff << 24)	@ restore original rd
+ + 		.endm
+ + 
+ + 		.macro	busyuart,rd,rx
+ + 1001:		ldrb	\rd, [\rx]		@ rx contains UART_LSR address
+ + 		and	\rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
+ + 		teq	\rd, #(UART_LSR_TEMT | UART_LSR_THRE)
+ + 		bne	1001b
+ + 		.endm
+ + 
+ + 		.macro	waituart,rd,rx
+ + 		.endm
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/devices.h linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/devices.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/devices.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/devices.h	2014-11-25 13:19:14.995356189 +0900
+ ***************
+ *** 0 ****
+ --- 1,27 ----
+ + /*
+ +  * Header for CKB 
+ +  *
+ +  * Copyright (C) 2013 Computex Co.Ltd.
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; version 2 of the License.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ +  *
+ +  */
+ +  
+ + #ifndef __ASM_ARCH_DEVICES_H
+ + #define __ASM_ARCH_DEVICES_H
+ + 
+ + #define CKB_EMIF_CS5_MAJOR		255
+ + #define CKB_DVI_MAJOR			254
+ + 
+ + #endif  /*  __ASM_ARCH_DEVICES_H */
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/edma.h linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/edma.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/edma.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/edma.h	2014-11-25 13:19:14.995356189 +0900
+ ***************
+ *** 0 ****
+ --- 1,250 ----
+ + /*
+ +  * TI EDMA3 definitions
+ +  *
+ +  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + /*
+ +  * This EDMA3 programming framework exposes two basic kinds of resource:
+ +  *
+ +  *  Channel	Triggers transfers, usually from a hardware event but
+ +  *		also manually or by "chaining" from DMA completions.
+ +  *		Each channel is coupled to a Parameter RAM (PaRAM) slot.
+ +  *
+ +  *  Slot	Each PaRAM slot holds a DMA transfer descriptor (PaRAM
+ +  *		"set"), source and destination addresses, a link to a
+ +  *		next PaRAM slot (if any), options for the transfer, and
+ +  *		instructions for updating those addresses.  There are
+ +  *		more than twice as many slots as event channels.
+ +  *
+ +  * Each PaRAM set describes a sequence of transfers, either for one large
+ +  * buffer or for several discontiguous smaller buffers.  An EDMA transfer
+ +  * is driven only from a channel, which performs the transfers specified
+ +  * in its PaRAM slot until there are no more transfers.  When that last
+ +  * transfer completes, the "link" field may be used to reload the channel's
+ +  * PaRAM slot with a new transfer descriptor.
+ +  *
+ +  * The EDMA Channel Controller (CC) maps requests from channels into physical
+ +  * Transfer Controller (TC) requests when the channel triggers (by hardware
+ +  * or software events, or by chaining).  The two physical DMA channels provided
+ +  * by the TCs are thus shared by many logical channels.
+ +  *
+ +  * EDMA hardware also has a "QDMA" mechanism which is not currently
+ +  * supported through this interface.  (DSP firmware uses it though.)
+ +  */
+ + 
+ + #ifndef EDMA_H_
+ + #define EDMA_H_
+ + 
+ + /* PaRAM slots are laid out like this */
+ + struct edmacc_param {
+ + 	unsigned int opt;
+ + 	unsigned int src;
+ + 	unsigned int a_b_cnt;
+ + 	unsigned int dst;
+ + 	unsigned int src_dst_bidx;
+ + 	unsigned int link_bcntrld;
+ + 	unsigned int src_dst_cidx;
+ + 	unsigned int ccnt;
+ + };
+ + 
+ + /* fields in edmacc_param.opt */
+ + #define SAM		BIT(0)
+ + #define DAM		BIT(1)
+ + #define SYNCDIM		BIT(2)
+ + #define STATIC		BIT(3)
+ + #define EDMA_FWID	(0x07 << 8)
+ + #define TCCMODE		BIT(11)
+ + #define EDMA_TCC(t)	((t) << 12)
+ + #define TCINTEN		BIT(20)
+ + #define ITCINTEN	BIT(21)
+ + #define TCCHEN		BIT(22)
+ + #define ITCCHEN		BIT(23)
+ + 
+ + #define TRWORD (0x7<<2)
+ + #define PAENTRY (0x1ff<<5)
+ + 
+ + /*ch_status paramater of callback function possible values*/
+ + #define DMA_COMPLETE 1
+ + #define DMA_CC_ERROR 2
+ + #define DMA_TC0_ERROR 3
+ + #define DMA_TC1_ERROR 4
+ + #define DMA_TC2_ERROR 5
+ + #define DMA_TC3_ERROR 6
+ + 
+ + enum address_mode {
+ + 	INCR = 0,
+ + 	FIFO = 1
+ + };
+ + 
+ + enum fifo_width {
+ + 	W8BIT = 0,
+ + 	W16BIT = 1,
+ + 	W32BIT = 2,
+ + 	W64BIT = 3,
+ + 	W128BIT = 4,
+ + 	W256BIT = 5
+ + };
+ + 
+ + enum dma_event_q {
+ + 	EVENTQ_0 = 0,
+ + 	EVENTQ_1 = 1,
+ + 	EVENTQ_2 = 2,
+ + 	EVENTQ_3 = 3,
+ + 	EVENTQ_DEFAULT = -1
+ + };
+ + 
+ + enum sync_dimension {
+ + 	ASYNC = 0,
+ + 	ABSYNC = 1
+ + };
+ + 
+ + #define EDMA_CTLR_CHAN(ctlr, chan)	(((ctlr) << 16) | (chan))
+ + #define EDMA_CTLR(i)			((i) >> 16)
+ + #define EDMA_CHAN_SLOT(i)		((i) & 0xffff)
+ + 
+ + #define EDMA_CHANNEL_ANY		-1	/* for edma_alloc_channel() */
+ + #define EDMA_SLOT_ANY			-1	/* for edma_alloc_slot() */
+ + #define EDMA_CONT_PARAMS_ANY		 1001
+ + #define EDMA_CONT_PARAMS_FIXED_EXACT	 1002
+ + #define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
+ + 
+ + #define EDMA_MAX_DMACH           64
+ + #define EDMA_MAX_PARAMENTRY     512
+ + #define EDMA_MAX_CC               2
+ + #define EDMA_MAX_REGION           4
+ + 
+ + 
+ + /* Mapping of crossbar event numbers to actual DMA channels*/
+ + struct event_to_channel_map {
+ + 	unsigned        xbar_event_no;
+ + 	int		channel_no;
+ + };
+ + 
+ + /* actual number of DMA channels and slots on this silicon */
+ + struct edma {
+ + 	/* how many dma resources of each type */
+ + 	unsigned	num_channels;
+ + 	unsigned	num_region;
+ + 	unsigned	num_slots;
+ + 	unsigned	num_tc;
+ + 	unsigned	num_cc;
+ + 	enum dma_event_q	default_queue;
+ + 
+ + 	/* list of channels with no even trigger; terminated by "-1" */
+ + 	const s8	*noevent;
+ + 
+ + 	/* The edma_inuse bit for each PaRAM slot is clear unless the
+ + 	 * channel is in use ... by ARM or DSP, for QDMA, or whatever.
+ + 	 */
+ + 	DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
+ + 
+ + 	/* The edma_unused bit for each channel is clear unless
+ + 	 * it is not being used on this platform. It uses a bit
+ + 	 * of SOC-specific initialization code.
+ + 	 */
+ + 	DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH);
+ + 
+ + 	unsigned	irq_res_start;
+ + 	unsigned	irq_res_end;
+ + 
+ + 	struct dma_interrupt_data {
+ + 		void (*callback)(unsigned channel, unsigned short ch_status,
+ + 				void *data);
+ + 		void *data;
+ + 	} intr_data[EDMA_MAX_DMACH];
+ + 
+ + 	unsigned	is_xbar;
+ + 	unsigned	num_events;
+ + 	struct event_to_channel_map	*xbar_event_mapping;
+ + 
+ + 	/* suspend/resume backup parameters */
+ + 	struct edmacc_param *bkp_prm_set;
+ + 	unsigned int *bkp_ch_map;		/* 64 registers */
+ + 	unsigned int *bkp_que_num;		/* 8 registers */
+ + 	unsigned int *bkp_drae;
+ + 	unsigned int *bkp_draeh;
+ + 	unsigned int *bkp_qrae;
+ + 	unsigned int bkp_sh_esr;
+ + 	unsigned int bkp_sh_esrh;
+ + 	unsigned int bkp_sh_eesr;
+ + 	unsigned int bkp_sh_eesrh;
+ + 	unsigned int bkp_sh_iesr;
+ + 	unsigned int bkp_sh_iesrh;
+ + 	unsigned int bkp_que_tc_map;
+ + 	unsigned int bkp_que_pri;
+ + };
+ + 
+ + extern struct edma *edma_cc[EDMA_MAX_CC];
+ + 
+ + /* alloc/free DMA channels and their dedicated parameter RAM slots */
+ + int edma_alloc_channel(int channel,
+ + 	void (*callback)(unsigned channel, u16 ch_status, void *data),
+ + 	void *data, enum dma_event_q);
+ + void edma_free_channel(unsigned channel);
+ + 
+ + /* alloc/free parameter RAM slots */
+ + int edma_alloc_slot(unsigned ctlr, int slot);
+ + void edma_free_slot(unsigned slot);
+ + 
+ + /* alloc/free a set of contiguous parameter RAM slots */
+ + int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count);
+ + int edma_free_cont_slots(unsigned slot, int count);
+ + 
+ + /* calls that operate on part of a parameter RAM slot */
+ + void edma_set_src(unsigned slot, dma_addr_t src_port,
+ + 				enum address_mode mode, enum fifo_width);
+ + void edma_set_dest(unsigned slot, dma_addr_t dest_port,
+ + 				 enum address_mode mode, enum fifo_width);
+ + void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst);
+ + void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx);
+ + void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx);
+ + void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt,
+ + 		u16 bcnt_rld, enum sync_dimension sync_mode);
+ + void edma_link(unsigned from, unsigned to);
+ + void edma_unlink(unsigned from);
+ + 
+ + /* calls that operate on an entire parameter RAM slot */
+ + void edma_write_slot(unsigned slot, const struct edmacc_param *params);
+ + void edma_read_slot(unsigned slot, struct edmacc_param *params);
+ + 
+ + /* channel control operations */
+ + int edma_start(unsigned channel);
+ + void edma_stop(unsigned channel);
+ + void edma_clean_channel(unsigned channel);
+ + void edma_clear_event(unsigned channel);
+ + void edma_pause(unsigned channel);
+ + void edma_resume(unsigned channel);
+ + 
+ + /* platform_data for EDMA driver */
+ + struct edma_soc_info {
+ + 
+ + 	/* how many dma resources of each type */
+ + 	unsigned	n_channel;
+ + 	unsigned	n_region;
+ + 	unsigned	n_slot;
+ + 	unsigned	n_tc;
+ + 	unsigned	n_cc;
+ + 	enum dma_event_q	default_queue;
+ + 
+ + 	const s16	(*rsv_chans)[2];
+ + 	const s16	(*rsv_slots)[2];
+ + 	const s8	(*queue_tc_mapping)[2];
+ + 	const s8	(*queue_priority_mapping)[2];
+ + 	unsigned	is_xbar;
+ + 	unsigned	n_events;
+ + 	struct event_to_channel_map    *xbar_event_mapping;
+ + 	int		(*map_xbar_channel)(unsigned event, unsigned *channel,
+ + 				struct event_to_channel_map *xbar_event_map);
+ + };
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/entry-macro.S linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/entry-macro.S
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/entry-macro.S	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/entry-macro.S	2014-11-25 13:19:14.999879408 +0900
+ ***************
+ *** 0 ****
+ --- 1,55 ----
+ + /*
+ +  * arch/arm/plat-omap/include/mach/entry-macro.S
+ +  *
+ +  * Low-level IRQ helper macros for OMAP-based platforms
+ +  *
+ +  * Copyright (C) 2009 Texas Instruments
+ +  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ +  *
+ +  * This file is licensed under  the terms of the GNU General Public
+ +  * License version 2. This program is licensed "as is" without any
+ +  * warranty of any kind, whether express or implied.
+ +  */
+ +  #include <mach/hardware.h>
+ + #include <mach/io.h>
+ + #include <mach/irqs.h>
+ + #include <asm/hardware/gic.h>
+ + 
+ + #include <plat/omap34xx.h>
+ + 
+ + #include <plat/multi.h>
+ + 
+ + #define OMAP3_IRQ_BASE		OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
+ + #define INTCPS_SIR_IRQ_OFFSET	0x0040	/* omap2/3 active interrupt offset */
+ + #define	ACTIVEIRQ_MASK		0x7f	/* omap2/3 active interrupt bits */
+ + 
+ + 		.macro	disable_fiq
+ + 		.endm
+ + 
+ + 		.macro  arch_ret_to_user, tmp1, tmp2
+ + 		.endm
+ + 
+ + /*
+ +  * Optimized irq functions for omap2, 3 and 4
+ +  */
+ + 
+ + 		.macro  get_irqnr_preamble, base, tmp
+ + 		ldr	\base, =OMAP3_IRQ_BASE
+ + 		.endm
+ + 
+ + 		/* Check the pending interrupts. Note that base already set */
+ + 		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
+ + 		ldr	\irqnr, [\base, #0x98] /* IRQ pending reg 1 */
+ + 		cmp	\irqnr, #0x0
+ + 		bne	9999f
+ + 		ldr	\irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
+ + 		cmp	\irqnr, #0x0
+ + 		bne	9999f
+ + 		ldr	\irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
+ + 		cmp	\irqnr, #0x0
+ + 9999:
+ + 		ldrne	\irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
+ + 		and	\irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
+ + 
+ + 		.endm
+ + 
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/gpio.h linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/gpio.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/gpio.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/gpio.h	2014-11-25 13:19:14.999879408 +0900
+ ***************
+ *** 0 ****
+ --- 1,5 ----
+ + /*
+ +  * arch/arm/mach-omap2/include/mach/gpio.h
+ +  */
+ + 
+ + #include <plat/gpio.h>
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/hardware.h linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/hardware.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/hardware.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/hardware.h	2014-11-25 13:19:14.999879408 +0900
+ ***************
+ *** 0 ****
+ --- 1,7 ----
+ + /*
+ +  * arch/arm/mach-omap2/include/mach/hardware.h
+ +  */
+ + 
+ + #include <plat/hardware.h>
+ + #define AM3352_GPMC_BASE		0x50000000
+ + #define CKB_GPMC_CS1_BASE		0x09000000
+ \ No newline at end of file
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/io.h linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/io.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/io.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/io.h	2014-11-25 13:19:14.999879408 +0900
+ ***************
+ *** 0 ****
+ --- 1,5 ----
+ + /*
+ +  * arch/arm/mach-omap2/include/mach/io.h
+ +  */
+ + 
+ + #include <plat/io.h>
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/irqs.h linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/irqs.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/irqs.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/irqs.h	2014-11-25 13:19:14.999879408 +0900
+ ***************
+ *** 0 ****
+ --- 1,5 ----
+ + /*
+ +  * arch/arm/mach-omap2/include/mach/irqs.h
+ +  */
+ + 
+ + #include <plat/irqs.h>
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/memory.h linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/memory.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/memory.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/memory.h	2014-11-25 13:19:14.999879408 +0900
+ ***************
+ *** 0 ****
+ --- 1,22 ----
+ + /*
+ +  * Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; version 2 of the License.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ +  *
+ +  */
+ + #ifndef __ASM_ARCH_CKB_MEMORY_H
+ + #define __ASM_ARCH_CKB_MEMORY_H
+ + 
+ + 
+ + #endif /* __ASM_ARCH_CKB_MEMORY_H */
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/omap-secure.h linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/omap-secure.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/omap-secure.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/omap-secure.h	2014-11-25 13:19:15.003029836 +0900
+ ***************
+ *** 0 ****
+ --- 1,57 ----
+ + /*
+ +  * omap-secure.h: OMAP Secure infrastructure header.
+ +  *
+ +  * Copyright (C) 2011 Texas Instruments, Inc.
+ +  *	Santosh Shilimkar <santosh.shilimkar@ti.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + #ifndef OMAP_ARCH_OMAP_SECURE_H
+ + #define OMAP_ARCH_OMAP_SECURE_H
+ + 
+ + /* Monitor error code */
+ + #define  API_HAL_RET_VALUE_NS2S_CONVERSION_ERROR	0xFFFFFFFE
+ + #define  API_HAL_RET_VALUE_SERVICE_UNKNWON		0xFFFFFFFF
+ + 
+ + /* HAL API error codes */
+ + #define  API_HAL_RET_VALUE_OK		0x00
+ + #define  API_HAL_RET_VALUE_FAIL		0x01
+ + 
+ + /* Secure HAL API flags */
+ + #define FLAG_START_CRITICAL		0x4
+ + #define FLAG_IRQFIQ_MASK		0x3
+ + #define FLAG_IRQ_ENABLE			0x2
+ + #define FLAG_FIQ_ENABLE			0x1
+ + #define NO_FLAG				0x0
+ + 
+ + /* Maximum Secure memory storage size */
+ + #define OMAP_SECURE_RAM_STORAGE	(88 * SZ_1K)
+ + 
+ + /* Secure low power HAL API index */
+ + #define OMAP4_HAL_SAVESECURERAM_INDEX	0x1a
+ + #define OMAP4_HAL_SAVEHW_INDEX		0x1b
+ + #define OMAP4_HAL_SAVEALL_INDEX		0x1c
+ + #define OMAP4_HAL_SAVEGIC_INDEX		0x1d
+ + 
+ + /* Secure Monitor mode APIs */
+ + #define OMAP4_MON_SCU_PWR_INDEX		0x108
+ + #define OMAP4_MON_L2X0_DBG_CTRL_INDEX	0x100
+ + #define OMAP4_MON_L2X0_CTRL_INDEX	0x102
+ + #define OMAP4_MON_L2X0_AUXCTRL_INDEX	0x109
+ + #define OMAP4_MON_L2X0_PREFETCH_INDEX	0x113
+ + 
+ + /* Secure PPA(Primary Protected Application) APIs */
+ + #define OMAP4_PPA_L2_POR_INDEX		0x23
+ + #define OMAP4_PPA_CPU_ACTRL_SMP_INDEX	0x25
+ + 
+ + #ifndef __ASSEMBLER__
+ + 
+ + extern u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs,
+ + 				u32 arg1, u32 arg2, u32 arg3, u32 arg4);
+ + extern u32 omap_smc2(u32 id, u32 falg, u32 pargs);
+ + extern phys_addr_t omap_secure_ram_mempool_base(void);
+ + 
+ + #endif /* __ASSEMBLER__ */
+ + #endif /* OMAP_ARCH_OMAP_SECURE_H */
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/smp.h linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/smp.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/smp.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/smp.h	2014-11-25 13:19:15.003029836 +0900
+ ***************
+ *** 0 ****
+ --- 1,5 ----
+ + /*
+ +  * arch/arm/mach-omap2/include/mach/smp.h
+ +  */
+ + 
+ + #include <plat/smp.h>
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/sram.h linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/sram.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/sram.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/sram.h	2014-11-25 13:19:15.003029836 +0900
+ ***************
+ *** 0 ****
+ --- 1,14 ----
+ + /*
+ +  * arch/arm/mach-omap2/include/mach/sram.h
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #ifndef __ARCH_ARM_SRAM_H
+ + #define __ARCH_ARM_SRAM_H
+ + 
+ + #include <plat/sram.h>
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/system.h linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/system.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/system.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/system.h	2014-11-25 13:19:15.003029836 +0900
+ ***************
+ *** 0 ****
+ --- 1,5 ----
+ + /*
+ +  * arch/arm/mach-omap2/include/mach/system.h
+ +  */
+ + 
+ + #include <plat/system.h>
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/timex.h linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/timex.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/timex.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/timex.h	2014-11-25 13:19:15.003029836 +0900
+ ***************
+ *** 0 ****
+ --- 1,5 ----
+ + /*
+ +  * arch/arm/mach-omap2/include/mach/timex.h
+ +  */
+ + 
+ + #include <plat/timex.h>
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/uncompress.h linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/uncompress.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/uncompress.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/uncompress.h	2014-11-25 13:19:15.003029836 +0900
+ ***************
+ *** 0 ****
+ --- 1,5 ----
+ + /*
+ +  * arch/arm/mach-omap2/include/mach/uncompress.h
+ +  */
+ + 
+ + #include <plat/uncompress.h>
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/vmalloc.h linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/vmalloc.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/include/mach/vmalloc.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/include/mach/vmalloc.h	2014-11-25 13:19:15.003029836 +0900
+ ***************
+ *** 0 ****
+ --- 1,6 ----
+ + #ifndef __ASM_ARCH_VMALLOC_H
+ + #define __ASM_ARCH_VMALLOC_H
+ + 
+ + #define VMALLOC_END	  (0xff000000UL)
+ + 
+ + #endif  /*  __ASM_ARCH_VMALLOC_H */
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/io.c linux-3.2.1/arch/arm/mach-ckb_3352/io.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/io.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/io.c	2014-11-25 13:19:15.003029836 +0900
+ ***************
+ *** 0 ****
+ --- 1,215 ----
+ + /*
+ +  * linux/arch/arm/mach-omap2/io.c
+ +  *
+ +  * OMAP2 I/O mapping code
+ +  *
+ +  * Copyright (C) 2005 Nokia Corporation
+ +  * Copyright (C) 2007-2009 Texas Instruments
+ +  *
+ +  * Author:
+ +  *	Juha Yrjola <juha.yrjola@nokia.com>
+ +  *	Syed Khasim <x0khasim@ti.com>
+ +  *
+ +  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + #include <linux/module.h>
+ + #include <linux/kernel.h>
+ + #include <linux/init.h>
+ + #include <linux/io.h>
+ + #include <linux/clk.h>
+ + #include <linux/omapfb.h>
+ + 
+ + #include <asm/tlb.h>
+ + 
+ + #include <asm/mach/map.h>
+ + 
+ + #include <plat/sram.h>
+ + #include <plat/sdrc.h>
+ + #include <plat/serial.h>
+ + 
+ + #include "clock.h"
+ + #include "clock33xx.h"
+ + 
+ + #include "common.h"
+ + #include <plat/omap-pm.h>
+ + #include "voltage.h"
+ + #include "powerdomain.h"
+ + #include "prminst44xx.h"
+ + #include "cminst44xx.h"
+ + 
+ + #include "clockdomain.h"
+ + #include <plat/omap_hwmod.h>
+ + #include <plat/multi.h>
+ + #include "common.h"
+ + 
+ + #include <mach/ckb_3352_mem.h>
+ + 
+ + #ifdef CONFIG_SOC_OMAPAM33XX
+ + static struct map_desc omapam33xx_io_desc[] __initdata = {
+ + 	{
+ + 		.virtual	= L4_34XX_VIRT,
+ + 		.pfn		= __phys_to_pfn(L4_34XX_PHYS),
+ + 		.length		= L4_34XX_SIZE,
+ + 		.type		= MT_DEVICE
+ + 	},
+ + 	{
+ + 		.virtual	= L4_WK_AM33XX_VIRT,
+ + 		.pfn		= __phys_to_pfn(L4_WK_AM33XX_PHYS),
+ + 		.length		= L4_WK_AM33XX_SIZE,
+ + 		.type		= MT_DEVICE
+ + 	},
+ + };
+ + #endif
+ + 
+ + #ifdef CONFIG_SOC_OMAPAM33XX
+ + void __init omapam33xx_map_common_io(void)
+ + {
+ + 	iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
+ + }
+ + #endif
+ + 
+ + /*
+ +  * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
+ +  *
+ +  * Sets the CORE DPLL3 M2 divider to the same value that it's at
+ +  * currently.  This has the effect of setting the SDRC SDRAM AC timing
+ +  * registers to the values currently defined by the kernel.  Currently
+ +  * only defined for OMAP3; will return 0 if called on OMAP2.  Returns
+ +  * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
+ +  * or passes along the return value of clk_set_rate().
+ +  */
+ + static int __init _omap2_init_reprogram_sdrc(void)
+ + {
+ + 	struct clk *dpll3_m2_ck;
+ + 	int v = -EINVAL;
+ + 	long rate;
+ + 
+ + 	dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
+ + 	if (IS_ERR(dpll3_m2_ck))
+ + 		return -EINVAL;
+ + 
+ + 	rate = clk_get_rate(dpll3_m2_ck);
+ + 	pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
+ + 	v = clk_set_rate(dpll3_m2_ck, rate);
+ + 	if (v)
+ + 		pr_err("dpll3_m2_clk rate change failed: %d\n", v);
+ + 
+ + 	clk_put(dpll3_m2_ck);
+ + 
+ + 	return v;
+ + }
+ + 
+ + static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
+ + {
+ + 	return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
+ + }
+ + 
+ + static void __init omap_common_init_early(void)
+ + {
+ + 	omap_init_consistent_dma_size();
+ + }
+ + 
+ + static void __init omap_hwmod_init_postsetup(void)
+ + {
+ + 	u8 postsetup_state;
+ + 
+ + 	/* Set the default postsetup state for all hwmods */
+ + #ifdef CONFIG_PM_RUNTIME
+ + 	postsetup_state = _HWMOD_STATE_IDLE;
+ + #else
+ + 	postsetup_state = _HWMOD_STATE_ENABLED;
+ + #endif
+ + 	omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
+ + 
+ + 	/*
+ + 	 * Set the default postsetup state for unusual modules (like
+ + 	 * MPU WDT).
+ + 	 *
+ + 	 * The postsetup_state is not actually used until
+ + 	 * omap_hwmod_late_init(), so boards that desire full watchdog
+ + 	 * coverage of kernel initialization can reprogram the
+ + 	 * postsetup_state between the calls to
+ + 	 * omap2_init_common_infra() and omap_sdrc_init().
+ + 	 *
+ + 	 * XXX ideally we could detect whether the MPU WDT was currently
+ + 	 * enabled here and make this conditional
+ + 	 */
+ + 	postsetup_state = _HWMOD_STATE_DISABLED;
+ + 	omap_hwmod_for_each_by_class("wd_timer",
+ + 				     _set_hwmod_postsetup_state,
+ + 				     &postsetup_state);
+ + 
+ + 	omap_pm_if_early_init();
+ + }
+ + 
+ + void __init am33xx_init_early(void)
+ + {
+ + 	omap2_set_globals_am33xx();
+ + 	omap3xxx_check_revision();
+ + 	am33xx_check_features();
+ + 	omap_common_init_early();
+ + 	am33xx_voltagedomains_init();
+ + 	omap44xx_prminst_init();
+ + 	am33xx_powerdomains_init();
+ + 	omap44xx_cminst_init();
+ + 	am33xx_clockdomains_init();
+ + 	am33xx_hwmod_init();
+ + 	omap_hwmod_init_postsetup();
+ + 	am33xx_clk_init();
+ + }
+ + 
+ + 
+ + void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
+ + 				      struct omap_sdrc_params *sdrc_cs1)
+ + {
+ + 	omap_sram_init();
+ + 
+ + 	if (omap3_has_sdrc()) {
+ + 		omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
+ + 		_omap2_init_reprogram_sdrc();
+ + 	}
+ + }
+ + 
+ + /*
+ +  * NOTE: Please use ioremap + __raw_read/write where possible instead of these
+ +  */
+ + 
+ + u8 omap_readb(u32 pa)
+ + {
+ + 	return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
+ + }
+ + EXPORT_SYMBOL(omap_readb);
+ + 
+ + u16 omap_readw(u32 pa)
+ + {
+ + 	return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
+ + }
+ + EXPORT_SYMBOL(omap_readw);
+ + 
+ + u32 omap_readl(u32 pa)
+ + {
+ + 	return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
+ + }
+ + EXPORT_SYMBOL(omap_readl);
+ + 
+ + void omap_writeb(u8 v, u32 pa)
+ + {
+ + 	__raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
+ + }
+ + EXPORT_SYMBOL(omap_writeb);
+ + 
+ + void omap_writew(u16 v, u32 pa)
+ + {
+ + 	__raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
+ + }
+ + EXPORT_SYMBOL(omap_writew);
+ + 
+ + void omap_writel(u32 v, u32 pa)
+ + {
+ + 	__raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
+ + }
+ + EXPORT_SYMBOL(omap_writel);
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/irq.c linux-3.2.1/arch/arm/mach-ckb_3352/irq.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/irq.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/irq.c	2014-11-25 13:19:15.003029836 +0900
+ ***************
+ *** 0 ****
+ --- 1,239 ----
+ + /*
+ +  * linux/arch/arm/mach-omap2/irq.c
+ +  *
+ +  * Interrupt handler for OMAP2 boards.
+ +  *
+ +  * Copyright (C) 2005 Nokia Corporation
+ +  * Author: Paul Mundt <paul.mundt@nokia.com>
+ +  *
+ +  * This file is subject to the terms and conditions of the GNU General Public
+ +  * License. See the file "COPYING" in the main directory of this archive
+ +  * for more details.
+ +  */
+ + #include <linux/kernel.h>
+ + #include <linux/init.h>
+ + #include <linux/interrupt.h>
+ + #include <linux/io.h>
+ + #include <mach/hardware.h>
+ + #include <asm/exception.h>
+ + #include <asm/mach/irq.h>
+ + 
+ + 
+ + /* selected INTC register offsets */
+ + 
+ + #define INTC_REVISION		0x0000
+ + #define INTC_SYSCONFIG		0x0010
+ + #define INTC_SYSSTATUS		0x0014
+ + #define INTC_SIR		0x0040
+ + #define INTC_CONTROL		0x0048
+ + #define INTC_PROTECTION		0x004C
+ + #define INTC_IDLE		0x0050
+ + #define INTC_THRESHOLD		0x0068
+ + #define INTC_MIR0		0x0084
+ + #define INTC_MIR_CLEAR0		0x0088
+ + #define INTC_MIR_SET0		0x008c
+ + #define INTC_PENDING_IRQ0	0x0098
+ + /* Number of IRQ state bits in each MIR register */
+ + #define IRQ_BITS_PER_REG	32
+ + 
+ + #define OMAP2_IRQ_BASE		OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
+ + #define OMAP3_IRQ_BASE		OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
+ + #define INTCPS_SIR_IRQ_OFFSET	0x0040	/* omap2/3 active interrupt offset */
+ + #define ACTIVEIRQ_MASK		0x7f	/* omap2/3 active interrupt bits */
+ + 
+ + /*
+ +  * OMAP2 has a number of different interrupt controllers, each interrupt
+ +  * controller is identified as its own "bank". Register definitions are
+ +  * fairly consistent for each bank, but not all registers are implemented
+ +  * for each bank.. when in doubt, consult the TRM.
+ +  */
+ + static struct omap_irq_bank {
+ + 	void __iomem *base_reg;
+ + 	unsigned int nr_irqs;
+ + 	unsigned int nr_regs_req;
+ + } __attribute__ ((aligned(4))) irq_banks[] = {
+ + 	{
+ + 		/* MPU INTC */
+ + 		.nr_irqs	= 96,
+ + 		.nr_regs_req	= 3,
+ + 	},
+ + };
+ + 
+ + /* Structure to save interrupt controller context */
+ + struct omap3_intc_regs {
+ + 	u32 sysconfig;
+ + 	u32 protection;
+ + 	u32 idle;
+ + 	u32 threshold;
+ + 	u32 ilr[INTCPS_MAX_NR_IRQS];
+ + 	u32 mir[INTCPS_MAX_NR_REGS_REQ];
+ + };
+ + 
+ + /* INTC bank register get/set */
+ + 
+ + static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
+ + {
+ + 	__raw_writel(val, bank->base_reg + reg);
+ + }
+ + 
+ + static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
+ + {
+ + 	return __raw_readl(bank->base_reg + reg);
+ + }
+ + 
+ + /* XXX: FIQ and additional INTC support (only MPU at the moment) */
+ + static void omap_ack_irq(struct irq_data *d)
+ + {
+ + 	intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
+ + }
+ + 
+ + static void omap_mask_ack_irq(struct irq_data *d)
+ + {
+ + 	irq_gc_mask_disable_reg(d);
+ + 	omap_ack_irq(d);
+ + }
+ + 
+ + static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
+ + {
+ + 	unsigned long tmp;
+ + 
+ + 	tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
+ + 	printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
+ + 			 "(revision %ld.%ld) with %d interrupts\n",
+ + 			 bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
+ + 
+ + 	tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
+ + 	tmp |= 1 << 1;	/* soft reset */
+ + 	intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);
+ + 
+ + 	while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
+ + 		/* Wait for reset to complete */;
+ + 
+ + 	/* Enable autoidle */
+ + 	intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
+ + }
+ + 
+ + int omap_irq_pending(void)
+ + {
+ + 	int i;
+ + 
+ + 	for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
+ + 		struct omap_irq_bank *bank = irq_banks + i;
+ + 		int irq;
+ + 
+ + 		for (irq = 0; irq < bank->nr_irqs; irq += 32)
+ + 			if (intc_bank_read_reg(bank, INTC_PENDING_IRQ0 +
+ + 					       ((irq >> 5) << 5)))
+ + 				return 1;
+ + 	}
+ + 	return 0;
+ + }
+ + 
+ + static __init void
+ + omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
+ + {
+ + 	struct irq_chip_generic *gc;
+ + 	struct irq_chip_type *ct;
+ + 
+ + 	gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
+ + 					handle_level_irq);
+ + 	ct = gc->chip_types;
+ + 	ct->chip.irq_ack = omap_mask_ack_irq;
+ + 	ct->chip.irq_mask = irq_gc_mask_disable_reg;
+ + 	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
+ + 	ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;
+ + 
+ + 	ct->regs.ack = INTC_CONTROL;
+ + 	ct->regs.enable = INTC_MIR_CLEAR0;
+ + 	ct->regs.disable = INTC_MIR_SET0;
+ + 	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
+ + 				IRQ_NOREQUEST | IRQ_NOPROBE, 0);
+ + }
+ + 
+ + static void __init omap_init_irq(u32 base, int nr_irqs)
+ + {
+ + 	void __iomem *omap_irq_base;
+ + 	unsigned long nr_of_irqs = 0;
+ + 	unsigned int nr_banks = 0;
+ + 	int i, j;
+ + 
+ + 	omap_irq_base = ioremap(base, SZ_4K);
+ + 	if (WARN_ON(!omap_irq_base))
+ + 		return;
+ + 
+ + 	for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
+ + 		struct omap_irq_bank *bank = irq_banks + i;
+ + 
+ + 		bank->nr_irqs = nr_irqs;
+ + 		bank->nr_regs_req = 0;
+ + 
+ + 		/* Static mapping, never released */
+ + 		bank->base_reg = ioremap(base, SZ_4K);
+ + 		if (!bank->base_reg) {
+ + 			printk(KERN_ERR "Could not ioremap irq bank%i\n", i);
+ + 			continue;
+ + 		}
+ + 
+ + 		omap_irq_bank_init_one(bank);
+ + 
+ + 		for (j = 0; j < bank->nr_irqs; j += 32) {
+ + 			omap_alloc_gc(bank->base_reg + j, j, 32);
+ + 			bank->nr_regs_req++;
+ + 		}
+ + 
+ + 		nr_of_irqs += bank->nr_irqs;
+ + 		nr_banks++;
+ + 	}
+ + 
+ + 	printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
+ + 	       nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
+ + }
+ + 
+ + void __init omap3_init_irq(void)
+ + {
+ + 	omap_init_irq(OMAP34XX_IC_BASE, 96);
+ + }
+ + 
+ + void __init ti81xx_init_irq(void)
+ + {
+ + 	omap_init_irq(OMAP34XX_IC_BASE, 128);
+ + }
+ + 
+ + static inline void omap_intc_handle_irq(void __iomem *base_addr,
+ + 		unsigned int no_regs_req, struct pt_regs *regs)
+ + {
+ + 	u32 irqnr = 0;
+ + 
+ + 	do {
+ + 		int i = 0;
+ + 
+ + 		for (i = 0; i < no_regs_req; i++) {
+ + 			irqnr = readl_relaxed(base_addr + 0x98 + (0x20 * i));
+ + 			if (irqnr)
+ + 				goto out;
+ + 		}
+ + 
+ + out:
+ + 		if (!irqnr)
+ + 			break;
+ + 
+ + 		irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);
+ + 		irqnr &= ACTIVEIRQ_MASK;
+ + 
+ + 		if (irqnr)
+ + 			handle_IRQ(irqnr, regs);
+ + 	} while (irqnr);
+ + }
+ + 
+ + void omap3_intc_suspend(void)
+ + {
+ + 	/* A pending interrupt would prevent OMAP from entering suspend */
+ + 	omap_ack_irq(0);
+ + }
+ + 
+ + asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs)
+ + {
+ + 	void __iomem *base_addr = OMAP3_IRQ_BASE;
+ + 	omap_intc_handle_irq(base_addr, irq_banks[0].nr_regs_req, regs);
+ + }
+ + 
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/Kconfig linux-3.2.1/arch/arm/mach-ckb_3352/Kconfig
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/Kconfig	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/Kconfig	2014-11-25 13:52:44.037867000 +0900
+ ***************
+ *** 0 ****
+ --- 1,1244 ----
+ + if ARCH_CKB
+ + 
+ + config SOC_OMAPAM33XX
+ + 	bool
+ + 
+ + config MACH_CKB_3352
+ + 	bool "CKB 3352 board"
+ + 	default y
+ + 	select OMAP_PACKAGE_CBB
+ + 	select NEED_MACH_MEMORY_H
+ + 	select SOC_OMAPAM33XX
+ + 	select CPU_V7
+ + 	select CLKDEV_LOOKUP
+ + 	select GENERIC_IRQ_CHIP
+ + 	select USE_OF
+ + 	select PROC_DEVICETREE
+ + 	select USB_ARCH_HAS_EHCI
+ + 	select ARM_L1_CACHE_SHIFT_6
+ + 	select ARCH_HAS_OPP
+ + 	select PM_OPP if PM
+ + 	select ARM_CPU_SUSPEND if PM
+ + 	select MULTI_IRQ_HANDLER
+ + 	select AEABI
+ + 	select REGULATOR
+ + 	select PM_RUNTIME
+ + 	select VFP
+ + 	select NEON
+ + 	select SERIAL_OMAP
+ + 	select SERIAL_OMAP_CONSOLE
+ + 	select I2C
+ + 	select I2C_OMAP
+ + 	select HAVE_PWM
+ + 
+ + config CKB_SUSPEND_SUPPORT
+ + 	bool "Suspend support"
+ + 
+ + 
+ + config CKB_TSC2007_TOUCH_PANEL
+ + 	bool
+ + 
+ + config CKB_RTC
+ + 	bool
+ + 
+ + config CKB_LCD_SUPPORT
+ + 	bool "Support LCD"
+ + 	depends on MACH_CKB_3352
+ + 	select FB_DA8XX
+ + 		
+ + choice
+ + 	prompt "Select LCD board"
+ + 	depends on CKB_LCD_SUPPORT
+ + 	help
+ + 	  Select LCD board with peripherals. 
+ + 
+ + config CKB_LCD_01
+ + 	bool "CKB LCD-01"
+ + 	select CKB_TSC2007_TOUCH_PANEL
+ + 	select CKB_RTC
+ + 	help
+ + 	  Support for Computex CKB LCD_01 LCD board (Visionx KTM050AL02).
+ + 	  	  	
+ + config CKB_LCD_02
+ + 	bool "CKB LCD-02"
+ + 	select CKB_TSC2007_TOUCH_PANEL
+ + 	help
+ + 	  Support for Computex CKB LCD_02 LCD board (Kyocera TCG070WVLPAAFA_AA00).
+ + endchoice
+ + 
+ + config CKB_DVI_SUPPORT
+ + 	bool "Support DVI"
+ + 	depends on MACH_CKB_3352
+ + 	select FB_DA8XX
+ + 	select FB_DDC
+ + 	select FB_MODE_HELPERS
+ + 	help
+ + 		Select this option to add DVI support on CKB 3352.
+ + 
+ + config DISPLAY_DVI_RESOLUTIONS
+ + 	bool "Display DVI resolutions when a device is connected"
+ + 	depends on CKB_DVI_SUPPORT
+ + 	help
+ + 	Select this option to display the DVI resolution read from the
+ + 	device on the terminal. Some resolutions may not be supported.
+ + 	The file /etc/fb.modes will have a list of resolutions that are
+ + 	be supported.
+ + 
+ + config DISPLAY_UNSUPPORTED_DVI_RESOLUTIONS
+ + 	bool "Display DVI unsupported resolutions"
+ + 	depends on DISPLAY_DVI_RESOLUTIONS
+ + 	help
+ + 	Select this option to display the DVI resolution that have been
+ + 	ignored because of incompatibility.
+ + 
+ + config LCD_CLOCK_CLOSEST_MATCH
+ + 	bool "Compute best match for LCD/DVI output clock"
+ + 	depends on CKB_LCD_SUPPORT || CKB_DVI_SUPPORT
+ + 	help
+ + 	This option finds the best matching output clock for LCD/DVI
+ + 	and uses it.
+ + 
+ + config CKB_EASY_SWITCH_MODE
+ + 	bool "Use numbers instead of names in /etc/fb.modes"
+ + 	depends on CKB_LCD_SUPPORT || CKB_DVI_SUPPORT
+ + 	help
+ + 	  This option makes it easier to switch the LCD configuration bootloader.
+ + 	  Instead of "fbset <mode_name>", "fbset <number>" can be used.
+ + 	  <number> will be shorter than <mode_name>.
+ + 
+ + config OMAP_PACKAGE_CBB
+ +        bool
+ + 
+ + config SUPPORT_CMJ100
+ + 	bool "CM-J100 WLAN card support"
+ + 	depends on MACH_CKB_3352
+ + 	help
+ + 	  Select this option to add support for CM-J100 WLAN card.
+ + 
+ + config SUPPORT_CKB_LED
+ + 	bool "Support on-board LEDs"
+ + 	depends on MACH_CKB_3352
+ + 	help
+ + 	  Select this option to add support for on-baord LEDs. 
+ + 
+ + config SUPPORT_GPMC_CS1_MEM
+ + 	bool "Support GPMC CS1 mem on EX_CN"
+ + 	depends on MACH_CKB_3352
+ + 	help
+ + 	  Select this option to add support for GPMC CS1 mem device on EX_CN.
+ + 	
+ + menu "EX_CN devices/ pin multiplex options"
+ + 	depends on MACH_CKB_3352
+ + 		
+ + 		
+ + comment "EX_CN devices"
+ + comment "!!! Do not connect LCD board !!!"
+ + 	depends on !CKB_LCD_SUPPORT
+ + 
+ + config CKB_EXTCN_26_28
+ + 	bool "Devices on Pins 26,28 (I2C1, UART4, CAN1)"
+ + 
+ + choice
+ + 	bool "Pin 26,28 device"
+ + 	depends on CKB_EXTCN_26_28
+ + 	help
+ + 	  Choose which peripheral to use. 
+ + 	  
+ + config CKB_EXTCN_I2C1
+ + 	bool "I2C1"
+ + 	help
+ + 	  Select this to use I2C1 on Pin26 and Pin28.
+ + 	  
+ + config CKB_EXTCN_UART4
+ + 	bool "UART4"
+ + 	help
+ + 	  Select this to use UART4 on Pin26 and Pin28
+ + 
+ + config CKB_EXTCN_CAN1
+ + 	bool "CAN1"
+ + 	help
+ + 	  Select this to use CAN1 on Pin26 and Pin28
+ + 
+ + endchoice
+ + 
+ + menu "Disable LCD support to enable devices on Pins 6,31,36,38 (spidev1, eHRPWM0)"
+ + 	depends on CKB_LCD_SUPPORT
+ + endmenu
+ + 
+ + config CKB_EXTCN_6_31_36_38
+ + 	bool "Devices on Pins 6,31,36,38 (spidev1, eHRPWM0)"
+ + 	depends on !CKB_LCD_SUPPORT
+ + 
+ + choice
+ + 	bool "Pin 6,26,36,38 device"
+ + 	depends on CKB_EXTCN_6_31_36_38
+ + 	help
+ + 	  Choose which peripheral to use. 
+ + 	  
+ + config CKB_EXTCN_SPIDEV_SPI1
+ + 	bool "spidev1 (Pins 6,31,36,38)"
+ + 	help
+ + 	  Select this to use SPI1 on EX_CN
+ + 	  
+ + config CKB_EHRPWM0
+ + 	bool "eHRPWM0 (Pins 36,38)"
+ + 	help
+ + 	  Select this to use eHRPWM0 on EX_CN
+ + endchoice	
+ + 
+ + config CKB_EXTCN_ADC
+ + 	bool "ADC (Pins 3,5,7)"
+ + 	select MFD_TI_AM335X_TSCADC
+ + 	help
+ + 	  ADC on EX_CN
+ + 
+ + comment "EX_CN pin multiplex"
+ + 
+ + menu "Disable LCD support to enable Pin2 multiplex options"
+ + 	depends on CKB_LCD_SUPPORT
+ + endmenu
+ + 
+ + choice
+ + 	prompt "Pin2"
+ + 	depends on !CKB_LCD_SUPPORT
+ + 	help
+ + 	  The LCD board shoudn't be connected as this is multiplexed with LCD data lines.
+ + 
+ + config CKB_EX_CN_PIN2_LCD_DATA12
+ + 	bool "LCD_DATA12"
+ + 
+ + config CKB_EX_CN_PIN2_A16
+ + 	bool "A16"
+ + 
+ + config CKB_EX_CN_PIN2_EQEP1A_IN
+ + 	bool "EQEP1A_IN"
+ + 
+ + config CKB_EX_CN_PIN2_MCASP0_ACLKR
+ + 	bool "MCASP0_ACLKR"
+ + 
+ + config CKB_EX_CN_PIN2_MCAP0_AXR2
+ + 	bool "MCAP0_AXR2"
+ + 	
+ + config CKB_EX_CN_PIN2_PR1_MII0_RXLINK
+ + 	bool "PR1_MII0_RXLINK"
+ + 
+ + config CKB_EX_CN_PIN2_UART4_CTS
+ + 	bool "UART4_CTS"
+ + 
+ + config CKB_EX_CN_PIN2_OGPIO
+ + 	bool "GPIO output (GPIO0_8)"
+ + 
+ + config CKB_EX_CN_PIN2_IGPIO
+ + 	bool "GPIO input (GPIO0_8)"
+ + 
+ + endchoice
+ + 
+ + menu "Disable LCD support to enable Pin4 multiplex options"
+ + 	depends on CKB_LCD_SUPPORT
+ + endmenu
+ + 
+ + choice 
+ + 	prompt "Pin4"
+ + 	depends on !CKB_LCD_SUPPORT
+ + 	help
+ + 	  The LCD board shoudn't be connected as this is multiplexed with LCD data lines.
+ + 	  
+ + config CKB_EX_CN_PIN4_LCD_DATA13
+ + 	bool "LCD_DATA13"
+ + 	
+ + config CKB_EX_CN_PIN4_A17
+ + 	bool "A17"
+ + 
+ + config CKB_EX_CN_PIN4_EQEP1B_IN
+ + 	bool "EQEP1B_IN"
+ + 
+ + config CKB_EX_CN_PIN4_MCASP0_FSR
+ + 	bool "MCASP0_FSR"
+ + 
+ + config CKB_EX_CN_PIN4_MCAP0_AXR3
+ + 	bool "MCAP0_AXR3"
+ + 
+ + config CKB_EX_CN_PIN2_PR1_MII0_RXER
+ + 	bool "PR1_MII0_RXER"
+ + 	
+ + config CKB_EX_CN_PIN4_UART4_RTS
+ + 	bool "UART4_RTS"
+ + 	
+ + config CKB_EX_CN_PIN4_OGPIO
+ + 	bool "GPIO output (GPIO0_9)"
+ + 
+ + config CKB_EX_CN_PIN4_IGPIO
+ + 	bool "GPIO input (GPIO0_9)"
+ + 
+ + endchoice
+ + 
+ + menu "Disable LCD support and spidev1 to enable Pin6 multiplex options"
+ + 	depends on CKB_LCD_SUPPORT || CKB_EXTCN_SPIDEV_SPI1
+ + endmenu
+ + 
+ + choice
+ + 	prompt "Pin6"
+ + 	depends on !CKB_LCD_SUPPORT && !CKB_EXTCN_SPIDEV_SPI1
+ + 	help
+ + 	  The LCD board shoudn't be connected as this is multiplexed with TP IRQ.
+ + 	  Yes, 'shoud not be connected'. 
+ + 
+ + config CKB_EX_CN_PIN6_MCASP0_AHCLKR
+ + 	bool "MCASP0_AHCLKR"
+ + 
+ + config CKB_EX_CN_PIN6_EHRPWM0_SYNCI
+ + 	bool "EHRPWM0_SYNCI"
+ + 	
+ + config CKB_EX_CN_PIN6_MCASP0_AXR2
+ + 	bool "MCASP0_AXR2"
+ + 
+ + config CKB_EX_CN_PIN6_SPI1_CS0
+ + 	bool "SPI1_CS0"
+ + 
+ + config CKB_EX_CN_PIN6_ECAP2_IN_PWM2_OUT
+ + 	bool "ECAP2_IN_PWM2_OUT"
+ + 	
+ + config CKB_EX_CN_PIN6_PR1_PRU0_PRU_R30_3
+ + 	bool "PR1_PRU0_PRU_R30_3"
+ + 
+ + config CKB_EX_CN_PIN6_PR1_PRU0_PRU_R31_3
+ + 	bool "PR1_PRU0_PRU_R31_3"
+ + 
+ + config CKB_EX_CN_PIN6_OGPIO
+ + 	bool "GPIO output (GPIO3_17)"
+ + 
+ + config CKB_EX_CN_PIN6_IGPIO
+ + 	bool "GPIO input (GPIO3_17)"
+ + 
+ + endchoice
+ + 
+ + 
+ + menu "Disable LCD support to enable Pin10 multiplex options"
+ + 	depends on CKB_LCD_SUPPORT
+ + endmenu
+ + 
+ + choice 
+ + 	prompt "Pin10"
+ + 	depends on !CKB_LCD_SUPPORT
+ + 	help
+ + 	 Choose multiplex options.
+ + 	 
+ + config CKB_EX_CN_PIN10_MCASP0_FSR
+ + 	bool "MCASP0_FSR"
+ + 
+ + config CKB_EX_CN_PIN10_EQEP0B_IN
+ + 	bool "EQEP0B_IN"
+ + 
+ + config CKB_EX_CN_PIN10_MCASP0_AXR3
+ + 	bool "MCASP0_AXR3"
+ + 
+ + config CKB_EX_CN_PIN10_MCASP1_FSX
+ + 	bool "MCASP1_FSX"
+ + 
+ + config CKB_EX_CN_PIN10_EMU2
+ + 	bool "PIN10_EMU2"
+ + 	
+ + config CKB_EX_CN_PIN10_PR1_PRU0_PRU_R30_5
+ + 	bool "PR1_PRU0_PRU_R30_5"
+ + 	
+ + config CKB_EX_CN_PIN10_PR1_PRU0_PRU_R31_5
+ + 	bool "PR1_PRU0_PRU_R31_5"
+ + 
+ + config CKB_EX_CN_PIN10_OGPIO
+ + 	bool "GPIO output (GPIO3_19)"
+ + 
+ + config CKB_EX_CN_PIN10_IGPIO
+ + 	bool "GPIO intput (GPIO3_19)"
+ + 
+ + endchoice
+ + 
+ + # Pins 13~20, Pins 23, Pin 25 are used by NOR flash
+ + # for now USED_BY_NOR_FLASH is used to mask this menuconfig option...
+ + 
+ + choice 
+ + 	prompt "Pin13"
+ + 	depends on USED_BY_NOR_FLASH
+ + 	help
+ + 	 Choose multiplex options.
+ + 
+ + config CKB_EX_CN_PIN13_AD1
+ + 	bool "AD1"
+ + 
+ + config CKB_EX_CN_PIN13_MMC1_DAT1
+ + 	bool "MMC1_DAT1"
+ + 
+ + config CKB_EX_CN_PIN13_OGPIO
+ + 	bool "GPIO output (GPIO1_1)"
+ + 
+ + config CKB_EX_CN_PIN13_IGPIO
+ + 	bool "GPIO input (GPIO1_1)"
+ + 
+ + endchoice
+ + 
+ + choice 
+ + 	prompt "Pin14"
+ + 	depends on USED_BY_NOR_FLASH
+ + 	help
+ + 	 Choose multiplex options.
+ + 
+ + config CKB_EX_CN_PIN14_AD0
+ + 	bool "AD0"
+ + 
+ + config CKB_EX_CN_PIN14_MMC1_DAT0
+ + 	bool "MMC1_DAT0"
+ + 	
+ + config CKB_EX_CN_PIN14_OGPIO
+ + 	bool "GPIO output (GPIO1_0)"
+ + 
+ + config CKB_EX_CN_PIN14_IGPIO
+ + 	bool "GPIO input (GPIO1_0)"
+ + 
+ + endchoice
+ + 
+ + choice 
+ + 	prompt "Pin15"
+ + 	depends on USED_BY_NOR_FLASH
+ + 	help
+ + 	 Choose multiplex options.
+ + 
+ + config CKB_EX_CN_PIN15_AD3
+ + 	bool "AD3"
+ + 
+ + config CKB_EX_CN_PIN15_MMC1_DAT3
+ + 	bool "MMC1_DAT3"
+ + 	
+ + config CKB_EX_CN_PIN15_OGPIO
+ + 	bool "GPIO output (GPIO1_3)"
+ + 
+ + config CKB_EX_CN_PIN15_IGPIO
+ + 	bool "GPIO input (GPIO1_3)"
+ + 
+ + endchoice
+ + 
+ + choice 
+ + 	prompt "Pin16"
+ + 	depends on USED_BY_NOR_FLASH
+ + 	help
+ + 	 Choose multiplex options.
+ + 
+ + config CKB_EX_CN_PIN16_AD2
+ + 	bool "AD2"
+ + 
+ + config CKB_EX_CN_PIN16_MMC1_DAT2
+ + 	bool "MMC1_DAT2"
+ + 	
+ + config CKB_EX_CN_PIN16_OGPIO
+ + 	bool "GPIO output (GPIO1_2)"
+ + 
+ + config CKB_EX_CN_PIN16_IGPIO
+ + 	bool "GPIO input (GPIO1_2)"
+ + 
+ + endchoice
+ + 
+ + choice 
+ + 	prompt "Pin17"
+ + 	depends on USED_BY_NOR_FLASH
+ + 	help
+ + 	 Choose multiplex options.
+ + 
+ + config CKB_EX_CN_PIN17_AD5
+ + 	bool "AD5"
+ + 
+ + config CKB_EX_CN_PIN17_MMC1_DAT5
+ + 	bool "MMC1_DAT5"
+ + 	
+ + config CKB_EX_CN_PIN17_OGPIO
+ + 	bool "GPIO output (GPIO1_5)"
+ + 
+ + config CKB_EX_CN_PIN17_IGPIO
+ + 	bool "GPIO input (GPIO1_5)"
+ + 
+ + endchoice
+ + 
+ + choice 
+ + 	prompt "Pin18"
+ + 	depends on USED_BY_NOR_FLASH
+ + 	help
+ + 	 Choose multiplex options.
+ + 
+ + config CKB_EX_CN_PIN18_AD4
+ + 	bool "AD4"
+ + 
+ + config CKB_EX_CN_PIN18_MMC1_DAT4
+ + 	bool "MMC1_DAT4"
+ + 	
+ + config CKB_EX_CN_PIN18_OGPIO
+ + 	bool "GPIO output (GPIO1_4)"
+ + 
+ + config CKB_EX_CN_PIN18_IGPIO
+ + 	bool "GPIO input (GPIO1_4)"
+ + 
+ + endchoice
+ + 
+ + choice 
+ + 	prompt "Pin19"
+ + 	depends on USED_BY_NOR_FLASH
+ + 	help
+ + 	 Choose multiplex options.
+ + 
+ + config CKB_EX_CN_PIN19_AD7
+ + 	bool "AD7"
+ + 
+ + config CKB_EX_CN_PIN19_MMC1_DAT7
+ + 	bool "MMC1_DAT7"
+ + 	
+ + config CKB_EX_CN_PIN19_OGPIO
+ + 	bool "GPIO output (GPIO1_7)"
+ + 
+ + config CKB_EX_CN_PIN19_IGPIO
+ + 	bool "GPIO input (GPIO1_7)"
+ + 
+ + endchoice
+ + 
+ + choice 
+ + 	prompt "Pin20"
+ + 	depends on USED_BY_NOR_FLASH
+ + 	help
+ + 	 Choose multiplex options.
+ + 
+ + config CKB_EX_CN_PIN20_AD6
+ + 	bool "AD6"
+ + 
+ + config CKB_EX_CN_PIN20_MMC1_DAT6
+ + 	bool "MMC1_DAT6"
+ + 	
+ + config CKB_EX_CN_PIN20_OGPIO
+ + 	bool "GPIO output (GPIO1_6)"
+ + 
+ + config CKB_EX_CN_PIN20_IGPIO
+ + 	bool "GPIO input (GPIO1_6)"
+ + 
+ + endchoice
+ + 
+ + menu "Disable Support GPMC CS1 mem to enable Pin21 multiplex options"
+ + 	depends on SUPPORT_GPMC_CS1_MEM
+ + endmenu
+ + 
+ + choice 
+ + 	prompt "Pin21"
+ + 	depends on !SUPPORT_GPMC_CS1_MEM
+ + 	help
+ + 	 Choose multiplex options.
+ + 
+ + config CKB_EX_CN_PIN21_GPMC_CSN1
+ + 	bool "GPMC_CSN1"
+ + 
+ + config CKB_EX_CN_PIN21_GPMC_CLK
+ + 	bool "GPMC_CLK"
+ + 
+ + config CKB_EX_CN_PIN21_MMC1_CLK
+ + 	bool "MMC1_CLK"
+ + 
+ + config CKB_EX_CN_PIN21_PR1_EDIO_DATA_IN6
+ + 	bool "PR1_EDIO_DATA_IN6"
+ + 
+ + config CKB_EX_CN_PIN21_PR1_EDIO_DATA_OUT6
+ + 	bool "PR1_EDIO_DATA_OUT6"
+ + 	
+ + config CKB_EX_CN_PIN21_PR1_PRU1_PRU_R30_12
+ + 	bool "PR1_PRU1_PRU_R30_12"
+ + 
+ + config CKB_EX_CN_PIN21_PR1_PRU1_PRU_R31_12
+ + 	bool "PR1_PRU1_PRU_R31_12"
+ + 
+ + config CKB_EX_CN_PIN21_OGPIO
+ + 	bool "GPIO output (GPIO1_30)"
+ + 
+ + config CKB_EX_CN_PIN21_IGPIO
+ + 	bool "GPIO input (GPIO1_30)"
+ + 
+ + endchoice
+ + 
+ + menu "Disable on-board LED support to enable Pin22 multiplex options"
+ + 	depends on SUPPORT_CKB_LED
+ + endmenu
+ + 
+ + choice 
+ + 	prompt "Pin22"
+ + 	depends on !SUPPORT_CKB_LED
+ + 	help
+ + 	 Choose multiplex options.
+ + 	 
+ + config CKB_EX_CN_PIN22_XDMA_EVENT_INTR0
+ + 	bool "XDMA_EVENT_INTR0"
+ + 	
+ + config CKB_EX_CN_PIN22_TIM4
+ + 	bool "TIM4"
+ + 
+ + config CKB_EX_CN_PIN22_CLKOUT1
+ + 	bool "CLKOUT1"
+ + 	
+ + config CKB_EX_CN_PIN22_SPI1_CS1
+ + 	bool "SPI1_CS1"
+ + 
+ + config CKB_EX_CN_PIN22_PR1_PRU1_PRU_R31_16
+ + 	bool "PR1_PRU1_PRU_R31_16"
+ + 	
+ + config CKB_EX_CN_PIN22_EMU2
+ + 	bool "EMU2"
+ + 		
+ + config CKB_EX_CN_PIN22_OGPIO
+ + 	bool "GPIO output (GPIO0_19)"
+ + 
+ + config CKB_EX_CN_PIN22_IGPIO
+ + 	bool "GPIO input (GPIO0_19)"
+ + 
+ + endchoice
+ + 
+ + choice
+ + 	prompt "Pin23"
+ + 	depends on USED_BY_NOR_FLASH
+ + 	help
+ + 	 Choose multiplex options.
+ + 	 
+ + config CKB_EX_CN_PIN23_GPMC_WEN
+ + 	bool "GPMC_WEN"
+ + 
+ + config CKB_EX_CN_PIN23_TIM6
+ + 	bool "TIM6"
+ + 
+ + config CKB_EX_CN_PIN23_OGPIO
+ + 	bool "GPIO output (GPIO2_4)"
+ + 
+ + config CKB_EX_CN_PIN23_IGPIO
+ + 	bool "GPIO input (GPIO2_4)"
+ + 
+ + endchoice
+ + 
+ + menu "Disable on-board LED support to enable Pin24 multiplex options"
+ + 	depends on SUPPORT_CKB_LED
+ + endmenu
+ + 
+ + choice 
+ + 	prompt "Pin24"
+ + 	depends on !SUPPORT_CKB_LED
+ + 	help
+ + 	 Choose multiplex options.
+ + 	 
+ + config CKB_EX_CN_PIN24_XDMA_EVENT_INTR1
+ + 	bool "XDMA_EVENT_INTR1"
+ + 
+ + config CKB_EX_CN_PIN24_TCLKIN
+ + 	bool "TCLKIN"
+ + 
+ + config CKB_EX_CN_PIN24_CLKOUT2
+ + 	bool "CLKOUT2"
+ + 
+ + config CKB_EX_CN_PIN24_TIM7
+ + 	bool "TIM7"
+ + 
+ + config CKB_EX_CN_PIN24_PR1_PRU0_PRU_R31_16
+ + 	bool "PR1_PRU0_PRU_R31_16"
+ + 	
+ + config CKB_EX_CN_PIN24_EMU3
+ + 	bool "EMU3"
+ + 
+ + config CKB_EX_CN_PIN24_OGPIO
+ + 	bool "GPIO output (GPIO0_20)"
+ + 
+ + config CKB_EX_CN_PIN24_IGPIO
+ + 	bool "GPIO input (GPIO0_20)"
+ + 
+ + endchoice
+ + 
+ + choice
+ + 	prompt "Pin25"
+ + 	depends on USED_BY_NOR_FLASH
+ + 	help
+ + 	 Choose multiplex options.
+ + 	 
+ + config CKB_EX_CN_PIN25_GPMC_OEN_REN
+ + 	bool "GPMC_OEN_REN"
+ + 
+ + config CKB_EX_CN_PIN25_TIM7
+ + 	bool "TIM7"
+ + 
+ + config CKB_EX_CN_PIN25_OGPIO
+ + 	bool "GPIO output (GPIO2_3)"
+ + 
+ + config CKB_EX_CN_PIN25_IGPIO
+ + 	bool "GPIO input (GPIO2_3)"
+ + 
+ + endchoice
+ + 
+ + menu "Disable devices on Pin26 to enable Pin26 multiplex options"
+ + 	depends on CKB_EXTCN_26_28
+ + endmenu
+ + 
+ + choice 
+ + 	prompt "Pin26"
+ + 	depends on !CKB_EXTCN_26_28
+ + 	help
+ + 	  Choose multiplex options. 
+ + 
+ + config CKB_EX_CN_PIN26_UART0_CTSN
+ + 	bool "UART0_CTSN"
+ + 	
+ + config CKB_EX_CN_PIN26_UART4_RXD
+ + 	bool "UART4_RXD"
+ + 	
+ + config CKB_EX_CN_PIN26_DCAN1_TX
+ + 	bool "DCAN1_TX"
+ + 		  
+ + config CKB_EX_CN_PIN26_I2C1_SDA
+ + 	bool "I2C1_SDA"
+ + 
+ + config CKB_EX_CN_PIN26_SPI1_D0
+ + 	bool "SPI1_D0"
+ + 
+ + config CKB_EX_CN_PIN26_TIM7
+ + 	bool "TIM7"
+ + 
+ + config CKB_EX_CN_PIN26_PR1_EDC_SYNC0_OUT
+ + 	bool "PR1_EDC_SYNC0_OUT"
+ + 
+ + config CKB_EX_CN_PIN26_OGPIO
+ + 	bool "GPIO output (GPIO1_8)"
+ + 
+ + config CKB_EX_CN_PIN26_IGPIO
+ + 	bool "GPIO input (GPIO1_8)"
+ + 
+ + endchoice
+ + 
+ + choice
+ + 	prompt "Pin27"
+ + 	help
+ + 	 Choose multiplex options.
+ + 	 
+ + config CKB_EX_CN_PIN27_GPMC_ADVN_ALE
+ + 	bool "GPMC_ADVN_ALE"
+ + 
+ + config CKB_EX_CN_PIN27_TIM4
+ + 	bool "TIM4"
+ + 
+ + config CKB_EX_CN_PIN27_OGPIO
+ + 	bool "GPIO output (GPIO2_2)"
+ + 
+ + config CKB_EX_CN_PIN27_IGPIO
+ + 	bool "GPIO input (GPIO2_2)"
+ + 
+ + endchoice
+ + 
+ + menu "Disable devices on Pin28 to enable Pin28 multiplex options"
+ + 	depends on CKB_EXTCN_26_28
+ + endmenu
+ + 
+ + choice 
+ + 	prompt "Pin28"
+ + 	depends on !CKB_EXTCN_26_28
+ + 	help
+ + 	  Choose multiplex options. 
+ + 
+ + config CKB_EX_CN_PIN28_UART0_RTSN
+ + 	bool "UART0_RTSN"
+ + 
+ + config CKB_EX_CN_PIN28_UART4_TXD
+ + 	bool "UART4_TXD"
+ + 	
+ + config CKB_EX_CN_PIN28_DCAN1_RX
+ + 	bool "DCAN1_RX"
+ + 		  
+ + config CKB_EX_CN_PIN28_I2C1_SCL
+ + 	bool "I2C1_SCL"
+ + 
+ + config CKB_EX_CN_PIN28_SPI1_D1
+ + 	bool "SPI1_D1"
+ + 
+ + config CKB_EX_CN_PIN28_SPI1_CS0
+ + 	bool "SPI1_CS0"
+ + 
+ + config CKB_EX_CN_PIN28_PR1_EDC_SYNC1_OUT
+ + 	bool "PR1_EDC_SYNC1_OUT"
+ + 	
+ + config CKB_EX_CN_PIN28_OGPIO
+ + 	bool "GPIO output (GPIO1_9)"
+ + 
+ + config CKB_EX_CN_PIN28_IGPIO
+ + 	bool "GPIO input (GPIO1_9)"
+ + 
+ + endchoice
+ + 
+ + menu "Disable CM-J100 WLAN card support to enable Pin29 multiplex options"
+ + 	depends on SUPPORT_CMJ100
+ + endmenu
+ + 
+ + choice
+ + 	prompt "Pin29"
+ + 	depends on !SUPPORT_CMJ100
+ + 	help
+ + 	 Choose multiplex options.
+ + 	 
+ + config CKB_EX_CN_PIN29_GPMC_A1
+ + 	bool "GPMC_A1"
+ + 
+ + config CKB_EX_CN_PIN29_MII2_RXDV
+ + 	bool "MII2_RXDV"
+ + 
+ + config CKB_EX_CN_PIN29_RGMII2_RCTL
+ + 	bool "RGMII2_RCTL"
+ + 		
+ + config CKB_EX_CN_PIN29_MMC2_D0
+ + 	bool "MMC2_D0"
+ + 
+ + config CKB_EX_CN_PIN29_GPMC_A17
+ + 	bool "GPMC_A17"
+ + 
+ + config CKB_EX_CN_PIN29_PR1_MII1_TXD3
+ + 	bool "PR1_MII1_TXD3"
+ + 
+ + config CKB_EX_CN_PIN29_EHRPWM0_SYNCO
+ + 	bool "EHRPWM0_SYNCO"
+ + 	
+ + config CKB_EX_CN_PIN29_OGPIO
+ + 	bool "GPIO output (GPIO1_17)"
+ + 
+ + config CKB_EX_CN_PIN29_IGPIO
+ + 	bool "GPIO input (GPIO1_17)"
+ + 
+ + endchoice
+ + 
+ + choice 
+ + 	prompt "Pin30"
+ + 	help
+ + 	  Choose multiplex options. 
+ + 
+ + config CKB_EX_CN_PIN30_ECAP0_IN_PWM0_OUT
+ + 	bool "ECAP0_IN_PWM0_OUT"
+ + 
+ + config CKB_EX_CN_PIN30_UART3_TXD
+ + 	bool "UART3_TXD"
+ + 
+ + config CKB_EX_CN_PIN30_SPI1_CS1
+ + 	bool "SPI1_CS1"
+ + 	
+ + config CKB_EX_CN_PIN30_PR1_ECAP0_ECAP_CAPIN_APWM_O
+ + 	bool "PR1_ECAP0_ECAP_CAPIN_APWM_O"
+ + 
+ + config CKB_EX_CN_PIN30_SPI1_SCK
+ + 	bool "SPI1_SCK"
+ + 
+ + config CKB_EX_CN_PIN30_MMC0_SDWP
+ + 	bool "MMC0_SDWP"
+ + 	
+ + config CKB_EX_CN_PIN30_XDMA_EVENT_INTR2
+ + 	bool "XDMA_EVENT_INTR2"
+ + 	
+ + config CKB_EX_CN_PIN30_OGPIO
+ + 	bool "GPIO output (GPIO0_7)"
+ + 
+ + config CKB_EX_CN_PIN30_IGPIO
+ + 	bool "GPIO input (GPIO0_7)"
+ + 
+ + endchoice
+ + 
+ + menu "Disable LCD support and spidev1 to enable Pin31 multiplex options"
+ + 	depends on CKB_LCD_SUPPORT && CKB_EXTCN_SPIDEV_SPI1
+ + endmenu
+ + 
+ + choice 
+ + 	prompt "Pin31"
+ + 	depends on !CKB_LCD_SUPPORT && !CKB_EXTCN_SPIDEV_SPI1
+ + 	help
+ + 	  Choose multiplex options. 
+ + 
+ + config CKB_EX_CN_PIN31_MCASP0_AXR0
+ + 	bool "MCASP0_AXR0"
+ + 
+ + config CKB_EX_CN_PIN31_EHRPWM0_TRIPZONE_INPUT
+ + 	bool "EHRPWM0_TRIPZONE_INPUT"
+ + 	
+ + config CKB_EX_CN_PIN31_SPI1_D1
+ + 	bool "SPI1_D1"
+ + 	
+ + config CKB_EX_CN_PIN31_MMC2_SDCD
+ + 	bool "MMC2_SDCD"
+ + 
+ + config CKB_EX_CN_PIN31_PR1_PRU0_PRU_R30_2
+ + 	bool "PR1_PRU0_PRU_R30_2"
+ + 
+ + config CKB_EX_CN_PIN31_PR1_PRU0_PRU_R31_2
+ + 	bool "PR1_PRU0_PRU_R31_2"
+ + 
+ + config CKB_EX_CN_PIN31_OGPIO
+ + 	bool "GPIO output (GPIO3_16)"
+ + 
+ + config CKB_EX_CN_PIN31_IGPIO
+ + 	bool "GPIO input (GPIO3_16)"
+ + 
+ + endchoice
+ + 
+ + choice 
+ + 	prompt "Pin33"
+ + 	help
+ + 	  Choose multiplex options. 
+ + 
+ + config CKB_EX_CN_PIN33_MCASP0_AXR1
+ + 	bool "MCASP0_AXR1"
+ + 
+ + config CKB_EX_CN_PIN33_EQEP0_INDEX
+ + 	bool "EQEP0_INDEX"
+ + 
+ + config CKB_EX_CN_PIN33_MCASP1_AXR0
+ + 	bool "MCASP1_AXR0"
+ + 
+ + config CKB_EX_CN_PIN33_EMU3
+ + 	bool "EMU3"
+ + 	
+ + config CKB_EX_CN_PIN33_PR1_PRU0_PRU_R30_6
+ + 	bool "PR1_PRU0_PRU_R30_6"
+ + 
+ + config CKB_EX_CN_PIN33_PR1_PRU0_PRU_R31_6
+ + 	bool "PR1_PRU0_PRU_R31_6"
+ + 	
+ + config CKB_EX_CN_PIN33_OGPIO
+ + 	bool "GPIO output (GPIO3_20)"
+ + 
+ + config CKB_EX_CN_PIN33_IGPIO
+ + 	bool "GPIO input (GPIO3_20)"
+ + 
+ + endchoice
+ + 
+ + choice 
+ + 	prompt "Pin34"
+ + 	help
+ + 	  Choose multiplex options. 
+ + 
+ + config CKB_EX_CN_PIN34_MCASP0_AHCLKX
+ + 	bool "MCASP0_AHCLKX"
+ + 
+ + config CKB_EX_CN_PIN34_EQEP0_STROBE
+ + 	bool "EQEP0_STROBE"
+ + 
+ + config CKB_EX_CN_PIN34_MCASP0_AXR3
+ + 	bool "MCASP0_AXR3"
+ + 
+ + config CKB_EX_CN_PIN34_MCASP1_AXR1
+ + 	bool "MCASP1_AXR1"
+ + 	
+ + config CKB_EX_CN_PIN34_EMU4
+ + 	bool "EMU4"
+ + 
+ + config CKB_EX_CN_PIN34_PR1_PRU0_PRU_R30_7
+ + 	bool "PR1_PRU0_PRU_R30_7"
+ + 	
+ + config CKB_EX_CN_PIN34_PR1_PRU0_PRU_R31_7
+ + 	bool "PR1_PRU0_PRU_R31_7"
+ + 
+ + config CKB_EX_CN_PIN34_OGPIO
+ + 	bool "GPIO output (GPIO3_21)"
+ + 
+ + config CKB_EX_CN_PIN34_IGPIO
+ + 	bool "GPIO input (GPIO3_21)"
+ + 
+ + endchoice
+ + 
+ + menu "Disable LCD support, spidev1 and eHRPWM0 to enable Pin36 multiplex options"
+ + 	depends on CKB_LCD_SUPPORT || CKB_EXTCN_SPIDEV_SPI1 || CKB_EHRPWM0
+ + endmenu
+ + 
+ + choice 
+ + 	prompt "Pin36"
+ + 	depends on !CKB_LCD_SUPPORT && !CKB_EXTCN_SPIDEV_SPI1 && !CKB_EHRPWM0
+ + 	help
+ + 	  Choose multiplex options. 
+ + 
+ + config CKB_EX_CN_PIN36_MCASP0_ACLKX
+ + 	bool "MCASP0_ACLKX"
+ + 
+ + config CKB_EX_CN_PIN36_EHRPWM0A
+ + 	bool "EHRPWM0A"
+ + 
+ + config CKB_EX_CN_PIN36_SPI1_SCLK
+ + 	bool "SPI1_SCLK"
+ + 	
+ + config CKB_EX_CN_PIN36_MMC0_SDCD
+ + 	bool "MMC0_SDCD"
+ + 	
+ + config CKB_EX_CN_PIN36_PR1_PRU0_PRU_R30_0
+ + 	bool "PR1_PRU0_PRU_R30_0"
+ + 
+ + config CKB_EX_CN_PIN36_PR1_PRU0_PRU_R31_0
+ + 	bool "PR1_PRU0_PRU_R31_0"
+ + 
+ + config CKB_EX_CN_PIN36_OGPIO
+ + 	bool "GPIO output (GPIO3_14)"
+ + 
+ + config CKB_EX_CN_PIN36_IGPIO
+ + 	bool "GPIO input (GPIO3_14)"
+ + 
+ + endchoice
+ + 
+ + menu "Disable LCD support, spidev and eHRPWM0 to enable Pin38 multiplex options"
+ + 	depends on CKB_LCD_SUPPORT || CKB_EXTCN_SPIDEV_SPI1 || CKB_EHRPWM0
+ + endmenu
+ + 
+ + choice 
+ + 	prompt "Pin38"
+ + 	depends on !CKB_LCD_SUPPORT && !CKB_EXTCN_SPIDEV_SPI1 && !CKB_EHRPWM0
+ + 	help
+ + 	  Choose multiplex options. 
+ + 
+ + config CKB_EX_CN_PIN38_MCASP0_FSX
+ + 	bool "MCASP0_FSX"
+ + 
+ + config CKB_EX_CN_PIN38_EHRPWM0B
+ + 	bool "EHRPWM0B"
+ + 	
+ + config CKB_EX_CN_PIN38_SPI1_D0
+ + 	bool "SPI1_D0"
+ + 	
+ + config CKB_EX_CN_PIN38_MMC1_SDCD
+ + 	bool "MMC1_SDCD"
+ + 
+ + config CKB_EX_CN_PIN38_PR1_PRU0_PRU_R30_1
+ + 	bool "PR1_PRU0_PRU_R30_1"
+ + 
+ + config CKB_EX_CN_PIN38_PR1_PRU0_PRU_R31_1
+ + 	bool "PR1_PRU0_PRU_R31_1"
+ + 
+ + config CKB_EX_CN_PIN38_OGPIO
+ + 	bool "GPIO output (GPIO3_15)"
+ + 
+ + config CKB_EX_CN_PIN38_IGPIO
+ + 	bool "GPIO input (GPIO3_15)"
+ + 
+ + endchoice
+ + 
+ + endmenu
+ + 
+ + menu "WLAN_CN multiplex options"
+ + 	depends on MACH_CKB_3352
+ + 
+ + choice 
+ + 	prompt "Pin24"
+ + 	help
+ + 	  Choose multiplex options. 
+ + 
+ + config CKB_WLAN_CN_PIN24_UART1_TXD
+ + 	bool "UART1_TXD"
+ + 
+ + config CKB_WLAN_CN_PIN24_MMC2_SDWP
+ + 	bool "MMC2_SDWP"
+ + 
+ + config CKB_WLAN_CN_PIN24_DCAN1_TX
+ + 	bool "DCAN1_TX"
+ + 
+ + config CKB_WLAN_CN_PIN24_I2C1_SCL
+ + 	bool "I2C1_SCL"
+ + 
+ + config CKB_WLAN_CN_PIN24_PR1_UART0_TXD
+ + 	bool "PR1_UART0_TXD"
+ + 
+ + config CKB_WLAN_CN_PIN24_PR1_PRU0_PRU_R31_16
+ + 	bool "PR1_PRU0_PRU_R31_16"
+ + 	
+ + config CKB_WLAN_CN_PIN24_OGPIO
+ + 	bool "GPIO output (GPIO0_15)"
+ + 
+ + config CKB_WLAN_CN_PIN24_IGPIO
+ + 	bool "GPIO input (GPIO0_15)"
+ + 
+ + endchoice
+ + 
+ + choice 
+ + 	prompt "Pin26"
+ + 	help
+ + 	  Choose multiplex options. 
+ + 
+ + config CKB_WLAN_CN_PIN26_UART1_RXD
+ + 	bool "UART1_RXD"
+ + 
+ + config CKB_WLAN_CN_PIN26_MMC1_SDWP
+ + 	bool "MMC1_SDWP"
+ + 
+ + config CKB_WLAN_CN_PIN26_DCAN0_TX
+ + 	bool "DCAN0_TX"
+ + 
+ + config CKB_WLAN_CN_PIN26_I2C1_SDA
+ + 	bool "I2C1_SDA"
+ + 
+ + config CKB_WLAN_CN_PIN26_PR1_UART0_RXD
+ + 	bool "PR1_UART0_RXD"
+ + 
+ + config CKB_WLAN_CN_PIN26_PR1_PRU1_PRU_R31_16
+ + 	bool "PR1_PRU1_PRU_R31_16"
+ + 	
+ + config CKB_WLAN_CN_PIN26_OGPIO
+ + 	bool "GPIO output (GPIO0_14)"
+ + 
+ + config CKB_WLAN_CN_PIN26_IGPIO
+ + 	bool "GPIO input (GPIO0_14)"
+ + 
+ + endchoice
+ + 
+ + choice 
+ + 	prompt "Pin28"
+ + 	help
+ + 	  Choose multiplex options. 
+ + 
+ + config CKB_WLAN_CN_PIN28_UART1_CTSN
+ + 	bool "UART1_CTSN"
+ + 
+ + config CKB_WLAN_CN_PIN28_TIMER6
+ + 	bool "TIMER6"
+ + 
+ + config CKB_WLAN_CN_PIN28_DCAN0_TX
+ + 	bool "DCAN0_TX"
+ + 
+ + config CKB_WLAN_CN_PIN28_I2C2_SDA
+ + 	bool "I2C2_SDA"
+ + 	
+ + config CKB_WLAN_CN_PIN28_SPI1_CS0
+ + 	bool "SPI_CS0"
+ + 
+ + config CKB_WLAN_CN_PIN28_PR1_UART0_CTS_N
+ + 	bool "PR1_UART0_CTS_N"
+ + 
+ + config CKB_WLAN_CN_PIN28_PR1_EDC_LATCH0_IN
+ + 	bool "PR1_EDC_LATCH0_IN"
+ + 	
+ + config CKB_WLAN_CN_PIN28_OGPIO
+ + 	bool "GPIO output (GPIO0_12)"
+ + 
+ + config CKB_WLAN_CN_PIN28_IGPIO
+ + 	bool "GPIO input (GPIO0_12)"
+ + 
+ + endchoice
+ + 
+ + choice 
+ + 	prompt "Pin30"
+ + 	help
+ + 	  Choose multiplex options. 
+ + 
+ + config CKB_WLAN_CN_PIN30_UART1_RTSN
+ + 	bool "UART1_RTSN"
+ + 
+ + config CKB_WLAN_CN_PIN30_TIMER5
+ + 	bool "TIMER5"
+ + 
+ + config CKB_WLAN_CN_PIN30_DCAN0_RX
+ + 	bool "DCAN0_RX"
+ + 
+ + config CKB_WLAN_CN_PIN30_I2C2_SCL
+ + 	bool "I2C2_SCL"
+ + 	
+ + config CKB_WLAN_CN_PIN30_SPI1_CS1
+ + 	bool "SPI_CS1"
+ + 
+ + config CKB_WLAN_CN_PIN30_PR1_UART0_RTS_N
+ + 	bool "PR1_UART0_RTS_N"
+ + 
+ + config CKB_WLAN_CN_PIN30_PR1_EDC_LATCH1_IN
+ + 	bool "PR1_EDC_LATCH1_IN"
+ + 	
+ + config CKB_WLAN_CN_PIN30_OGPIO
+ + 	bool "GPIO output (GPIO0_13)"
+ + 
+ + config CKB_WLAN_CN_PIN30_IGPIO
+ + 	bool "GPIO input (GPIO0_13)"
+ + 
+ + endchoice
+ + 
+ + endmenu
+ + 
+ + config OMAP3_EDMA
+ + 	bool "OMAP3 EDMA support"
+ + 	default n
+ + 	help
+ + 	  Select this option if EDMA is used
+ + 
+ + config AM33XX_SMARTREFLEX
+ + 	bool "AM33XX SmartReflex support"
+ + 	depends on (SOC_OMAPAM33XX) && PM
+ + 	help
+ + 	  Say Y if you want to enable SmartReflex.
+ + 
+ + 	  SmartReflex can perform continuous dynamic voltage
+ + 	  scaling around the nominal operating point voltage
+ + 	  according to silicon characteristics and operating
+ + 	  conditions. Enabling SmartReflex reduces active power
+ + 	  consumption.
+ + 
+ + 	  Please note, that by default SmartReflex is enabled.
+ +           To disable the automatic voltage compensation for
+ +           vdd mpu and vdd core from user space, user must
+ +           write 1 to /debug/smartreflex/autocomp.
+ + 
+ + 	  Optionally autocompensation can be disabled in the kernel
+ + 	  by default during system init via the enable_on_init flag
+ + 	  which an be passed as platform data to the smartreflex driver.
+ + 
+ + config OMAP_RESET_CLOCKS
+ + 	bool "Reset unused clocks during boot"
+ + 	help
+ + 	  Say Y if you want to reset unused clocks during boot.
+ + 	  This option saves power, but assumes all drivers are
+ + 	  using the clock framework. Broken drivers that do not
+ + 	  yet use clock framework may not work with this option.
+ + 	  If you are booting from another operating system, you
+ + 	  probably do not want this option enabled until your
+ + 	  device drivers work properly.
+ + 
+ + config OMAP_MUX
+ + 	bool "OMAP multiplexing support"
+ + 	depends on ARCH_CKB
+ + 	default y
+ + 	help
+ + 	  Pin multiplexing support for OMAP boards. If your bootloader
+ + 	  sets the multiplexing correctly, say N. Otherwise, or if unsure,
+ + 	  say Y.
+ + 
+ + config OMAP_MUX_DEBUG
+ + 	bool "Multiplexing debug output"
+ + 	depends on OMAP_MUX
+ + 	help
+ + 	  Makes the multiplexing functions print out a lot of debug info.
+ + 	  This is useful if you want to find out the correct values of the
+ + 	  multiplexing registers.
+ + 
+ + config OMAP_IOMMU_IVA2
+ + 	bool
+ + 
+ + config OMAP_32K_TIMER
+ + 	bool "Use 32KHz timer"
+ + 	help
+ + 	  Select this option if you want to enable the OMAP 32KHz timer.
+ + 	  This timer saves power compared to the OMAP_MPU_TIMER, and has
+ + 	  support for no tick during idle. The 32KHz timer provides less
+ + 	  intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
+ + 	  currently only available for OMAP16XX, 24XX, 34XX and OMAP4.
+ + 
+ + 
+ + config OMAP_32K_TIMER_HZ
+ + 	int "Kernel internal timer frequency for 32KHz timer"
+ + 	range 32 1024
+ + 	depends on OMAP_32K_TIMER
+ + 	default "128"
+ + 	help
+ + 	  Kernel internal timer frequency should be a divisor of 32768,
+ + 	  such as 64 or 128.
+ + 
+ + config CKB_SUSPEND_SUPPORT
+ + 	bool "Support suspend (Not tested)"
+ + 	depends on MACH_CKB_3352
+ + 	depends on SUSPEND
+ + 	default n
+ + 	help
+ + 	  This feature is still under development. 
+ + 
+ + 
+ + config TI_PM_DISABLE_VT_SWITCH
+ + 	bool "Disable PM Console Switch"
+ + 	depends on CKB_SUSPEND_SUPPORT
+ + 	default y
+ + 	help
+ + 	  This option disables the default PM VT switch behavior for TI devices.
+ + 	  Some platforms hang during suspend due to a failed attempt to
+ + 	  perform the VT switch.  The VT switch is unnecessary on many platforms.
+ + 
+ + endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/mailbox.c linux-3.2.1/arch/arm/mach-ckb_3352/mailbox.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/mailbox.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/mailbox.c	2014-11-25 13:19:15.008943215 +0900
+ ***************
+ *** 0 ****
+ --- 1,432 ----
+ + /*
+ +  * Mailbox reservation modules for OMAP2/3
+ +  *
+ +  * Copyright (C) 2006-2009 Nokia Corporation
+ +  * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
+ +  *        and  Paul Mundt
+ +  *
+ +  * This file is subject to the terms and conditions of the GNU General Public
+ +  * License.  See the file "COPYING" in the main directory of this archive
+ +  * for more details.
+ +  */
+ + 
+ + #include <linux/module.h>
+ + #include <linux/clk.h>
+ + #include <linux/err.h>
+ + #include <linux/platform_device.h>
+ + #include <linux/io.h>
+ + #include <linux/pm_runtime.h>
+ + #include <plat/mailbox.h>
+ + #include <mach/irqs.h>
+ + 
+ + #define MAILBOX_REVISION		0x000
+ + #define MAILBOX_MESSAGE(m)		(0x040 + 0x4 * (m))
+ + #define MAILBOX_FIFOSTATUS(m)		(0x080 + 0x4 * (m))
+ + #define MAILBOX_MSGSTATUS(m)		(0x0c0 + 0x4 * (m))
+ + #define MAILBOX_IRQSTATUS(u)		(0x100 + 0x8 * (u))
+ + #define MAILBOX_IRQENABLE(u)		(0x104 + 0x8 * (u))
+ + 
+ + #define OMAP4_MAILBOX_IRQSTATUS(u)	(0x104 + 0x10 * (u))
+ + #define OMAP4_MAILBOX_IRQENABLE(u)	(0x108 + 0x10 * (u))
+ + #define OMAP4_MAILBOX_IRQENABLE_CLR(u)	(0x10c + 0x10 * (u))
+ + 
+ + #define MAILBOX_IRQ_NEWMSG(m)		(1 << (2 * (m)))
+ + #define MAILBOX_IRQ_NOTFULL(m)		(1 << (2 * (m) + 1))
+ + 
+ + /* TODO: This can and should be based on #users and #sub-modules */
+ + #define MBOX_REG_SIZE			0x120
+ + 
+ + #define OMAP4_MBOX_REG_SIZE		0x130
+ + 
+ + #define AM33XX_MBOX_REG_SIZE		0x140
+ + 
+ + #define MBOX_NR_REGS			(MBOX_REG_SIZE / sizeof(u32))
+ + #define OMAP4_MBOX_NR_REGS		(OMAP4_MBOX_REG_SIZE / sizeof(u32))
+ + #define AM33XX_MBOX_NR_REGS		(AM33XX_MBOX_REG_SIZE / sizeof(u32))
+ + 
+ + static void __iomem *mbox_base;
+ + 
+ + struct omap_mbox2_fifo {
+ + 	unsigned long msg;
+ + 	unsigned long fifo_stat;
+ + 	unsigned long msg_stat;
+ + };
+ + 
+ + struct omap_mbox2_priv {
+ + 	struct omap_mbox2_fifo tx_fifo;
+ + 	struct omap_mbox2_fifo rx_fifo;
+ + 	unsigned long irqenable;
+ + 	unsigned long irqstatus;
+ + 	u32 newmsg_bit;
+ + 	u32 notfull_bit;
+ + 	u32 ctx[OMAP4_MBOX_NR_REGS];
+ + 	unsigned long irqdisable;
+ + };
+ + 
+ + static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
+ + 				  omap_mbox_type_t irq);
+ + 
+ + static inline unsigned int mbox_read_reg(size_t ofs)
+ + {
+ + 	return __raw_readl(mbox_base + ofs);
+ + }
+ + 
+ + static inline void mbox_write_reg(u32 val, size_t ofs)
+ + {
+ + 	__raw_writel(val, mbox_base + ofs);
+ + }
+ + 
+ + /* Mailbox H/W preparations */
+ + static int omap2_mbox_startup(struct omap_mbox *mbox)
+ + {
+ + 	u32 l;
+ + 
+ + 	pm_runtime_enable(mbox->dev->parent);
+ + 	pm_runtime_get_sync(mbox->dev->parent);
+ + 
+ + 	l = mbox_read_reg(MAILBOX_REVISION);
+ + 	pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
+ + 
+ + 	omap2_mbox_enable_irq(mbox, IRQ_RX);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static void omap2_mbox_shutdown(struct omap_mbox *mbox)
+ + {
+ + 	pm_runtime_put_sync(mbox->dev->parent);
+ + 	pm_runtime_disable(mbox->dev->parent);
+ + }
+ + 
+ + /* Mailbox FIFO handle functions */
+ + static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
+ + {
+ + 	struct omap_mbox2_fifo *fifo =
+ + 		&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
+ + 	return (mbox_msg_t) mbox_read_reg(fifo->msg);
+ + }
+ + 
+ + static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
+ + {
+ + 	struct omap_mbox2_fifo *fifo =
+ + 		&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
+ + 	mbox_write_reg(msg, fifo->msg);
+ + }
+ + 
+ + static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
+ + {
+ + 	struct omap_mbox2_fifo *fifo =
+ + 		&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
+ + 	return (mbox_read_reg(fifo->msg_stat) == 0);
+ + }
+ + 
+ + static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
+ + {
+ + 	struct omap_mbox2_fifo *fifo =
+ + 		&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
+ + 	return mbox_read_reg(fifo->fifo_stat);
+ + }
+ + 
+ + static int omap2_mbox_fifo_needs_flush(struct omap_mbox *mbox)
+ + {
+ + 	struct omap_mbox2_fifo *fifo =
+ + 		&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
+ + 	return (mbox_read_reg(fifo->msg_stat) == 0);
+ + }
+ + 
+ + static mbox_msg_t omap2_mbox_fifo_readback(struct omap_mbox *mbox)
+ + {
+ + 	struct omap_mbox2_fifo *fifo =
+ + 		&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
+ + 	return (mbox_msg_t) mbox_read_reg(fifo->msg);
+ + }
+ + 
+ + /* Mailbox IRQ handle functions */
+ + static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
+ + 		omap_mbox_type_t irq)
+ + {
+ + 	struct omap_mbox2_priv *p = mbox->priv;
+ + 	u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
+ + 
+ + 	l = mbox_read_reg(p->irqenable);
+ + 	l |= bit;
+ + 	mbox_write_reg(l, p->irqenable);
+ + }
+ + 
+ + static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
+ + 		omap_mbox_type_t irq)
+ + {
+ + 	struct omap_mbox2_priv *p = mbox->priv;
+ + 	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
+ + 
+ + 	if (!cpu_is_omap44xx() && !cpu_is_am33xx())
+ + 		bit = mbox_read_reg(p->irqdisable) & ~bit;
+ + 
+ + 	mbox_write_reg(bit, p->irqdisable);
+ + }
+ + 
+ + static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
+ + 		omap_mbox_type_t irq)
+ + {
+ + 	struct omap_mbox2_priv *p = mbox->priv;
+ + 	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
+ + 
+ + 	mbox_write_reg(bit, p->irqstatus);
+ + 
+ + 	/* Flush posted write for irq status to avoid spurious interrupts */
+ + 	mbox_read_reg(p->irqstatus);
+ + }
+ + 
+ + static int omap2_mbox_is_irq(struct omap_mbox *mbox,
+ + 		omap_mbox_type_t irq)
+ + {
+ + 	struct omap_mbox2_priv *p = mbox->priv;
+ + 	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
+ + 	u32 enable = mbox_read_reg(p->irqenable);
+ + 	u32 status = mbox_read_reg(p->irqstatus);
+ + 
+ + 	return (int)(enable & status & bit);
+ + }
+ + 
+ + static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
+ + {
+ + 	int i;
+ + 	struct omap_mbox2_priv *p = mbox->priv;
+ + 	int nr_regs;
+ + 	if (cpu_is_omap44xx())
+ + 		nr_regs = OMAP4_MBOX_NR_REGS;
+ + 	else
+ + 		nr_regs = MBOX_NR_REGS;
+ + 	for (i = 0; i < nr_regs; i++) {
+ + 		p->ctx[i] = mbox_read_reg(i * sizeof(u32));
+ + 
+ + 		dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
+ + 			i, p->ctx[i]);
+ + 	}
+ + }
+ + 
+ + static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
+ + {
+ + 	int i;
+ + 	struct omap_mbox2_priv *p = mbox->priv;
+ + 	int nr_regs;
+ + 	if (cpu_is_omap44xx())
+ + 		nr_regs = OMAP4_MBOX_NR_REGS;
+ + 	else
+ + 		nr_regs = MBOX_NR_REGS;
+ + 	for (i = 0; i < nr_regs; i++) {
+ + 		mbox_write_reg(p->ctx[i], i * sizeof(u32));
+ + 
+ + 		dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
+ + 			i, p->ctx[i]);
+ + 	}
+ + }
+ + 
+ + static struct omap_mbox_ops omap2_mbox_ops = {
+ + 	.type			= OMAP_MBOX_TYPE2,
+ + 	.startup		= omap2_mbox_startup,
+ + 	.shutdown		= omap2_mbox_shutdown,
+ + 	.fifo_read		= omap2_mbox_fifo_read,
+ + 	.fifo_write		= omap2_mbox_fifo_write,
+ + 	.fifo_empty		= omap2_mbox_fifo_empty,
+ + 	.fifo_full		= omap2_mbox_fifo_full,
+ + 	.fifo_needs_flush	= omap2_mbox_fifo_needs_flush,
+ + 	.fifo_readback		= omap2_mbox_fifo_readback,
+ + 	.enable_irq		= omap2_mbox_enable_irq,
+ + 	.disable_irq		= omap2_mbox_disable_irq,
+ + 	.ack_irq		= omap2_mbox_ack_irq,
+ + 	.is_irq			= omap2_mbox_is_irq,
+ + 	.save_ctx		= omap2_mbox_save_ctx,
+ + 	.restore_ctx		= omap2_mbox_restore_ctx,
+ + };
+ + 
+ + /*
+ +  * MAILBOX 0: ARM -> DSP,
+ +  * MAILBOX 1: ARM <- DSP.
+ +  * MAILBOX 2: ARM -> IVA,
+ +  * MAILBOX 3: ARM <- IVA.
+ +  */
+ + 
+ + /* FIXME: the following structs should be filled automatically by the user id */
+ + 
+ + /* DSP */
+ + static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
+ + 	.tx_fifo = {
+ + 		.msg		= MAILBOX_MESSAGE(0),
+ + 		.fifo_stat	= MAILBOX_FIFOSTATUS(0),
+ + 	},
+ + 	.rx_fifo = {
+ + 		.msg		= MAILBOX_MESSAGE(1),
+ + 		.msg_stat	= MAILBOX_MSGSTATUS(1),
+ + 	},
+ + 	.irqenable	= MAILBOX_IRQENABLE(0),
+ + 	.irqstatus	= MAILBOX_IRQSTATUS(0),
+ + 	.notfull_bit	= MAILBOX_IRQ_NOTFULL(0),
+ + 	.newmsg_bit	= MAILBOX_IRQ_NEWMSG(1),
+ + 	.irqdisable	= MAILBOX_IRQENABLE(0),
+ + };
+ + 
+ + struct omap_mbox mbox_dsp_info = {
+ + 	.name	= "dsp",
+ + 	.ops	= &omap2_mbox_ops,
+ + 	.priv	= &omap2_mbox_dsp_priv,
+ + };
+ + 
+ + struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL };
+ + 
+ + /* IVA */
+ + static struct omap_mbox2_priv omap2_mbox_iva_priv = {
+ + 	.tx_fifo = {
+ + 		.msg		= MAILBOX_MESSAGE(2),
+ + 		.fifo_stat	= MAILBOX_FIFOSTATUS(2),
+ + 	},
+ + 	.rx_fifo = {
+ + 		.msg		= MAILBOX_MESSAGE(3),
+ + 		.msg_stat	= MAILBOX_MSGSTATUS(3),
+ + 	},
+ + 	.irqenable	= MAILBOX_IRQENABLE(3),
+ + 	.irqstatus	= MAILBOX_IRQSTATUS(3),
+ + 	.notfull_bit	= MAILBOX_IRQ_NOTFULL(2),
+ + 	.newmsg_bit	= MAILBOX_IRQ_NEWMSG(3),
+ + 	.irqdisable	= MAILBOX_IRQENABLE(3),
+ + };
+ + 
+ + static struct omap_mbox mbox_iva_info = {
+ + 	.name	= "iva",
+ + 	.ops	= &omap2_mbox_ops,
+ + 	.priv	= &omap2_mbox_iva_priv,
+ + };
+ + 
+ + struct omap_mbox *omap2_mboxes[] = { &mbox_dsp_info, &mbox_iva_info, NULL };
+ + 
+ + /* A8 -> Wakeup-M3 */
+ + static struct omap_mbox2_priv omap2_mbox_m3_priv = {
+ + 	.tx_fifo = {
+ + 		.msg		= MAILBOX_MESSAGE(0),
+ + 		.fifo_stat	= MAILBOX_FIFOSTATUS(0),
+ + 		.msg_stat	= MAILBOX_MSGSTATUS(0),
+ + 	},
+ + 	/* TODO: No M3->A8 so this needs to be removed */
+ + 	.rx_fifo = {
+ + 		.msg		= MAILBOX_MESSAGE(1),
+ + 		.msg_stat	= MAILBOX_MSGSTATUS(1),
+ + 	},
+ + 	.irqenable	= OMAP4_MAILBOX_IRQENABLE(3),
+ + 	.irqstatus	= OMAP4_MAILBOX_IRQSTATUS(3),
+ + 	.notfull_bit	= MAILBOX_IRQ_NOTFULL(0),
+ + 	.newmsg_bit	= MAILBOX_IRQ_NEWMSG(0),
+ + 	.irqdisable	= OMAP4_MAILBOX_IRQENABLE_CLR(3),
+ + };
+ + 
+ + struct omap_mbox wkup_m3_info = {
+ + 	.name	= "wkup_m3",
+ + 	.ops	= &omap2_mbox_ops,
+ + 	.priv	= &omap2_mbox_m3_priv,
+ + };
+ + 
+ + struct omap_mbox *am33xx_mboxes[] = { &wkup_m3_info, NULL };
+ + 
+ + /* OMAP4 */
+ + static struct omap_mbox2_priv omap2_mbox_1_priv = {
+ + 	.tx_fifo = {
+ + 		.msg		= MAILBOX_MESSAGE(0),
+ + 		.fifo_stat	= MAILBOX_FIFOSTATUS(0),
+ + 	},
+ + 	.rx_fifo = {
+ + 		.msg		= MAILBOX_MESSAGE(1),
+ + 		.msg_stat	= MAILBOX_MSGSTATUS(1),
+ + 	},
+ + 	.irqenable	= OMAP4_MAILBOX_IRQENABLE(0),
+ + 	.irqstatus	= OMAP4_MAILBOX_IRQSTATUS(0),
+ + 	.notfull_bit	= MAILBOX_IRQ_NOTFULL(0),
+ + 	.newmsg_bit	= MAILBOX_IRQ_NEWMSG(1),
+ + 	.irqdisable	= OMAP4_MAILBOX_IRQENABLE_CLR(0),
+ + };
+ + 
+ + struct omap_mbox mbox_1_info = {
+ + 	.name	= "mailbox-1",
+ + 	.ops	= &omap2_mbox_ops,
+ + 	.priv	= &omap2_mbox_1_priv,
+ + };
+ + 
+ + static struct omap_mbox2_priv omap2_mbox_2_priv = {
+ + 	.tx_fifo = {
+ + 		.msg		= MAILBOX_MESSAGE(3),
+ + 		.fifo_stat	= MAILBOX_FIFOSTATUS(3),
+ + 	},
+ + 	.rx_fifo = {
+ + 		.msg		= MAILBOX_MESSAGE(2),
+ + 		.msg_stat	= MAILBOX_MSGSTATUS(2),
+ + 	},
+ + 	.irqenable	= OMAP4_MAILBOX_IRQENABLE(0),
+ + 	.irqstatus	= OMAP4_MAILBOX_IRQSTATUS(0),
+ + 	.notfull_bit	= MAILBOX_IRQ_NOTFULL(3),
+ + 	.newmsg_bit	= MAILBOX_IRQ_NEWMSG(2),
+ + 	.irqdisable     = OMAP4_MAILBOX_IRQENABLE_CLR(0),
+ + };
+ + 
+ + struct omap_mbox mbox_2_info = {
+ + 	.name	= "mailbox-2",
+ + 	.ops	= &omap2_mbox_ops,
+ + 	.priv	= &omap2_mbox_2_priv,
+ + };
+ + 
+ + struct omap_mbox *omap4_mboxes[] = { &mbox_1_info, &mbox_2_info, NULL };
+ + 
+ + static int __devinit omap2_mbox_probe(struct platform_device *pdev)
+ + {
+ + 	struct resource *mem;
+ + 	int ret;
+ + 	struct omap_mbox **list;
+ + 
+ + 	list = am33xx_mboxes;
+ + 
+ + 	list[0]->irq = platform_get_irq(pdev, 0);
+ + 	
+ + 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ + 	mbox_base = ioremap(mem->start, resource_size(mem));
+ + 	if (!mbox_base)
+ + 		return -ENOMEM;
+ + 
+ + 	ret = omap_mbox_register(&pdev->dev, list);
+ + 	if (ret) {
+ + 		iounmap(mbox_base);
+ + 		return ret;
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static int __devexit omap2_mbox_remove(struct platform_device *pdev)
+ + {
+ + 	omap_mbox_unregister();
+ + 	iounmap(mbox_base);
+ + 	return 0;
+ + }
+ + 
+ + static struct platform_driver omap2_mbox_driver = {
+ + 	.probe = omap2_mbox_probe,
+ + 	.remove = __devexit_p(omap2_mbox_remove),
+ + 	.driver = {
+ + 		.name = "omap-mailbox",
+ + 	},
+ + };
+ + 
+ + static int __init omap2_mbox_init(void)
+ + {
+ + 	return platform_driver_register(&omap2_mbox_driver);
+ + }
+ + 
+ + static void __exit omap2_mbox_exit(void)
+ + {
+ + 	platform_driver_unregister(&omap2_mbox_driver);
+ + }
+ + 
+ + device_initcall(omap2_mbox_init);
+ + module_exit(omap2_mbox_exit);
+ + 
+ + MODULE_LICENSE("GPL v2");
+ + MODULE_DESCRIPTION("omap mailbox: omap2/3/4 architecture specific functions");
+ + MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>");
+ + MODULE_AUTHOR("Paul Mundt");
+ + MODULE_ALIAS("platform:omap2-mailbox");
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/Makefile linux-3.2.1/arch/arm/mach-ckb_3352/Makefile
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/Makefile	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/Makefile	2014-11-25 14:08:28.404881000 +0900
+ ***************
+ *** 0 ****
+ --- 1,115 ----
+ + #
+ + # Makefile for the linux kernel.
+ + #
+ + 
+ + # Common support
+ + obj-y := io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
+ + 	 common.o gpio.o dma.o wd_timer.o display.o
+ + 
+ + omap-2-3-common				= irq.o sdrc.o
+ + hwmod-common				= omap_hwmod.o \
+ + 					  omap_hwmod_common_data.o
+ + clock-common				= clock.o clock_common_data.o \
+ + 					  clkt_dpll.o clkt_clksel.o
+ + 
+ + obj-y += $(omap-2-3-common) $(hwmod-common)
+ + 
+ + # SMP support ONLY available for OMAP4
+ + obj-$(CONFIG_HOTPLUG_CPU)		+= omap-hotplug.o
+ + 
+ + plus_sec := $(call as-instr,.arch_extension sec,+sec)
+ + AFLAGS_omap-headsmp.o			:=-Wa,-march=armv7-a$(plus_sec)
+ + AFLAGS_omap-smc.o			:=-Wa,-march=armv7-a$(plus_sec)
+ + 
+ + # Functions loaded to SRAM
+ + obj-y		+= sram34xx.o
+ + 
+ + obj-$(CONFIG_PM_DEBUG)			+= pm-debug.o
+ + 
+ + AFLAGS_sram242x.o			:=-Wa,-march=armv6
+ + AFLAGS_sram243x.o			:=-Wa,-march=armv6
+ + AFLAGS_sram34xx.o			:=-Wa,-march=armv7-a
+ + 
+ + # Pin multiplexing
+ + obj-y           += mux33xx.o
+ + 
+ + obj-y		+= mailbox.o
+ + 
+ + # OPP table initialization
+ + ifeq ($(CONFIG_PM_OPP),y)
+ + obj-y					+= opp.o
+ + obj-y		+= opp3xxx_data.o
+ + endif
+ + 
+ + # Power Management
+ + ifeq ($(CONFIG_PM),y)
+ + 					   
+ + obj-$(CONFIG_SOC_OMAPAM33XX)		+= cpuidle33xx.o pm33xx.o \
+ + 					   sleep33xx.o
+ + 
+ + obj-$(CONFIG_AM33XX_SMARTREFLEX)        += am33xx-smartreflex-class2.o
+ + 
+ + AFLAGS_sleep33xx.o			:=-Wa,-march=armv7-a$(plus_sec)
+ + 
+ + ifeq ($(CONFIG_PM_VERBOSE),y)
+ + CFLAGS_pm_bus.o				+= -DDEBUG
+ + endif
+ + 
+ + endif
+ + 
+ + # PRCM
+ + obj-y		+=  prcm.o prm2xxx_3xxx.o vc3xxx_data.o vp3xxx_data.o
+ + obj-$(CONFIG_SOC_OMAPAM33XX)		+= cminst44xx.o
+ + 
+ + # XXX The presence of cm2xxx_3xxx.o on the line below is temporary and
+ + # will be removed once the OMAP4 part of the codebase is converted to
+ + # use OMAP4-specific PRCM functions.
+ + 
+ + # OMAP voltage domains
+ + voltagedomain-common			:= voltage.o vc.o vp.o
+ + obj-y		+= $(voltagedomain-common) \
+ + 					   voltagedomains33xx_data.o
+ + 
+ + # OMAP powerdomain framework
+ + powerdomain-common			+= powerdomain.o powerdomain-common.o
+ + obj-y		+= $(powerdomain-common) \
+ + 					   powerdomains3xxx_data.o \
+ + 					   powerdomains2xxx_3xxx_data.o
+ + obj-$(CONFIG_SOC_OMAPAM33XX)		+= prminst44xx.o \
+ + 					   powerdomain44xx.o \
+ + 					   powerdomains33xx_data.o
+ + 
+ + # PRCM clockdomain control
+ + obj-y		+= clockdomain.o
+ + obj-$(CONFIG_SOC_OMAPAM33XX)		+= clockdomain44xx.o \
+ + 					   clockdomains33xx_data.o
+ + 
+ + # Clock framework
+ + obj-y		+= $(clock-common) dpll3xxx.o clock33xx_data.o
+ + 
+ + # hwmod data
+ + obj-y		+= omap_hwmod_2xxx_3xxx_ipblock_data.o \
+ + 					   
+ + 					  
+ + obj-$(CONFIG_SOC_OMAPAM33XX)		+= omap_hwmod_33xx_data.o
+ + 
+ + # L3 interconnect
+ + obj-y		+= omap_l3_smx.o
+ + 
+ + i2c-omap-$(CONFIG_I2C_OMAP)		:= i2c.o
+ + obj-y					+= $(i2c-omap-m) $(i2c-omap-y)
+ + 
+ + # Specific board support
+ + obj-y				+= board-ckb-3352.o
+ + 
+ + # Platform specific device init code
+ + 
+ + omap-hsmmc-$(CONFIG_MMC_OMAP_HS)	:= hsmmc.o
+ + obj-y					+= $(omap-hsmmc-m) $(omap-hsmmc-y)
+ + 
+ + 
+ + obj-y					+= usb-musb.o
+ + obj-y					+= omap_phy_internal.o
+ + 
+ + dobj-y					+= usb-host.o
+ + 
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/Makefile.boot linux-3.2.1/arch/arm/mach-ckb_3352/Makefile.boot
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/Makefile.boot	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/Makefile.boot	2014-11-25 13:19:15.008943215 +0900
+ ***************
+ *** 0 ****
+ --- 1,3 ----
+ +   zreladdr-y		+= 0x80008000
+ + params_phys-y		:= 0x80000100
+ + initrd_phys-y		:= 0x80800000
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/mux33xx.c linux-3.2.1/arch/arm/mach-ckb_3352/mux33xx.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/mux33xx.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/mux33xx.c	2014-11-25 13:19:15.012844683 +0900
+ ***************
+ *** 0 ****
+ --- 1,1235 ----
+ + /*
+ +  * AM33XX mux data
+ +  *
+ +  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ +  *
+ +  * Derived from: arch/arm/mach-omap2/mux34xx.c Original copyright follows:
+ +  *
+ +  * Copyright (C) 2009 Nokia
+ +  * Copyright (C) 2009 Texas Instruments
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #include <linux/module.h>
+ + #include <linux/init.h>
+ + #include <linux/io.h>
+ + #include <linux/debugfs.h>
+ + #include <linux/slab.h>
+ + #include <linux/seq_file.h>
+ + #include <linux/uaccess.h>
+ + #include <linux/gpio.h>
+ + #include <linux/interrupt.h>
+ + #include <linux/suspend.h>
+ + 
+ + #include "cm33xx.h"
+ + #include "control.h"
+ + #include "mux.h"
+ + 
+ + #ifdef CONFIG_OMAP_MUX
+ + 
+ + #define _AM33XX_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7)		\
+ + {									\
+ + 	.reg_offset	= (AM33XX_CONTROL_PADCONF_##M0##_OFFSET),	\
+ + 	.gpio		= (g),						\
+ + 	.muxnames	= { m0, m1, m2, m3, m4, m5, m6, m7 },		\
+ + }
+ + 
+ + /* AM33XX pin mux super set */
+ + static struct omap_mux am33xx_muxmodes[] = {
+ + 	_AM33XX_MUXENTRY(GPMC_AD0, 0,
+ + 		"gpmc_ad0", "mmc1_dat0", NULL, NULL,
+ + 		NULL, NULL, NULL, "gpio1_0"),
+ + 	_AM33XX_MUXENTRY(GPMC_AD1, 0,
+ + 		"gpmc_ad1", "mmc1_dat1", NULL, NULL,
+ + 		NULL, NULL, NULL, "gpio1_1"),
+ + 	_AM33XX_MUXENTRY(GPMC_AD2, 0,
+ + 		"gpmc_ad2", "mmc1_dat2", NULL, NULL,
+ + 		NULL, NULL, NULL, "gpio1_2"),
+ + 	_AM33XX_MUXENTRY(GPMC_AD3, 0,
+ + 		"gpmc_ad3", "mmc1_dat3", NULL, NULL,
+ + 		NULL, NULL, NULL, "gpio1_3"),
+ + 	_AM33XX_MUXENTRY(GPMC_AD4, 0,
+ + 		"gpmc_ad4", "mmc1_dat4", NULL, NULL,
+ + 		NULL, NULL, NULL, "gpio1_4"),
+ + 	_AM33XX_MUXENTRY(GPMC_AD5, 0,
+ + 		"gpmc_ad5", "mmc1_dat5", NULL, NULL,
+ + 		NULL, NULL, NULL, "gpio1_5"),
+ + 	_AM33XX_MUXENTRY(GPMC_AD6, 0,
+ + 		"gpmc_ad6", "mmc1_dat6", NULL, NULL,
+ + 		NULL, NULL, NULL, "gpio1_6"),
+ + 	_AM33XX_MUXENTRY(GPMC_AD7, 0,
+ + 		"gpmc_ad7", "mmc1_dat7", NULL, NULL,
+ + 		NULL, NULL, NULL, "gpio1_7"),
+ + 	_AM33XX_MUXENTRY(GPMC_AD8, 0,
+ + 		"gpmc_ad8", "lcd_data16", "mmc1_dat0", "mmc2_dat4",
+ + 		NULL, NULL, NULL, "gpio0_22"),
+ + 	_AM33XX_MUXENTRY(GPMC_AD9, 0,
+ + 		"gpmc_ad9", "lcd_data17", "mmc1_dat1", "mmc2_dat5",
+ + 		"ehrpwm2B", NULL, NULL, "gpio0_23"),
+ + 	_AM33XX_MUXENTRY(GPMC_AD10, 0,
+ + 		"gpmc_ad10", "lcd_data18", "mmc1_dat2", "mmc2_dat6",
+ + 		NULL, NULL, NULL, "gpio0_26"),
+ + 	_AM33XX_MUXENTRY(GPMC_AD11, 0,
+ + 		"gpmc_ad11", "lcd_data19", "mmc1_dat3", "mmc2_dat7",
+ + 		NULL, NULL, NULL, "gpio0_27"),
+ + 	_AM33XX_MUXENTRY(GPMC_AD12, 0,
+ + 		"gpmc_ad12", "lcd_data20", "mmc1_dat4", "mmc2_dat0",
+ + 		NULL, NULL, NULL, "gpio1_12"),
+ + 	_AM33XX_MUXENTRY(GPMC_AD13, 0,
+ + 		"gpmc_ad13", "lcd_data21", "mmc1_dat5", "mmc2_dat1",
+ + 		NULL, NULL, NULL, "gpio1_13"),
+ + 	_AM33XX_MUXENTRY(GPMC_AD14, 0,
+ + 		"gpmc_ad14", "lcd_data22", "mmc1_dat6", "mmc2_dat2",
+ + 		NULL, NULL, NULL, "gpio1_14"),
+ + 	_AM33XX_MUXENTRY(GPMC_AD15, 0,
+ + 		"gpmc_ad15", "lcd_data23", "mmc1_dat7", "mmc2_dat3",
+ + 		NULL, NULL, NULL, "gpio1_15"),
+ + 	_AM33XX_MUXENTRY(GPMC_A0, 0,
+ + 		"gpmc_a0", "mii2_txen", "rgmii2_tctl", "rmii2_txen",
+ + 		NULL, NULL, NULL, "gpio1_16"),
+ + 	_AM33XX_MUXENTRY(GPMC_A1, 0,
+ + 		"gpmc_a1", "mii2_rxdv", "rgmii2_rctl", "mmc2_dat0",
+ + 		"gpmc_a17", "pr1_mii1_txd3", "ehrpwm0_synco", "gpio1_17"),
+ + 	_AM33XX_MUXENTRY(GPMC_A2, 0,
+ + 		"gpmc_a2", "mii2_txd3", "rgmii2_td3", "mmc2_dat1",
+ + 		NULL, NULL, NULL, "gpio1_18"),
+ + 	_AM33XX_MUXENTRY(GPMC_A3, 0,
+ + 		"gpmc_a3", "mii2_txd2", "rgmii2_td2", "mmc2_dat2",
+ + 		NULL, NULL, NULL, "gpio1_19"),
+ + 	_AM33XX_MUXENTRY(GPMC_A4, 0,
+ + 		"gpmc_a4", "mii2_txd1", "rgmii2_td1", "rmii2_txd1",
+ + 		"gpmc_a20", NULL, NULL, "gpio1_20"),
+ + 	_AM33XX_MUXENTRY(GPMC_A5, 0,
+ + 		"gpmc_a5", "mii2_txd0", "rgmii2_td0", "rmii2_txd0",
+ + 		"gpmc_a21", NULL, NULL, "gpio1_21"),
+ + 	_AM33XX_MUXENTRY(GPMC_A6, 0,
+ + 		"gpmc_a6", "mii2_txclk", "rgmii2_tclk", "mmc2_dat4",
+ + 		"gpmc_a22", NULL, NULL, "gpio1_22"),
+ + 	_AM33XX_MUXENTRY(GPMC_A7, 0,
+ + 		"gpmc_a7", "mii2_rxclk", "rgmii2_rclk", "mmc2_dat5",
+ + 		NULL, NULL, NULL, "gpio1_23"),
+ + 	_AM33XX_MUXENTRY(GPMC_A8, 0,
+ + 		"gpmc_a8", "mii2_rxd3", "rgmii2_rd3", "mmc2_dat6",
+ + 		NULL, NULL, "mcasp0_aclkx", "gpio1_24"),
+ + 	_AM33XX_MUXENTRY(GPMC_A9, 0,
+ + 		"gpmc_a9", "mii2_rxd2", "rgmii2_rd2", "mmc2_dat7",
+ + 		NULL, NULL, "mcasp0_fsx", "gpio1_25"),
+ + 	_AM33XX_MUXENTRY(GPMC_A10, 0,
+ + 		"gpmc_a10", "mii2_rxd1", "rgmii2_rd1", "rmii2_rxd1",
+ + 		NULL, NULL, "mcasp0_axr0", "gpio1_26"),
+ + 	_AM33XX_MUXENTRY(GPMC_A11, 0,
+ + 		"gpmc_a11", "mii2_rxd0", "rgmii2_rd0", "rmii2_rxd0",
+ + 		NULL, NULL, "mcasp0_axr1", "gpio1_27"),
+ + 	_AM33XX_MUXENTRY(GPMC_WAIT0, 0,
+ + 		"gpmc_wait0", "mii2_crs", NULL, "rmii2_crs_dv",
+ + 		"mmc1_sdcd", NULL, NULL, "gpio0_30"),
+ + 	_AM33XX_MUXENTRY(GPMC_WPN, 0,
+ + 		"gpmc_wpn", "mii2_rxerr", NULL, "rmii2_rxerr",
+ + 		"mmc2_sdcd", NULL, NULL, "gpio0_31"),
+ + 	_AM33XX_MUXENTRY(GPMC_BEN1, 0,
+ + 		"gpmc_ben1", "mii2_col", NULL, "mmc2_dat3",
+ + 		NULL, NULL, "mcasp0_aclkr", "gpio1_28"),
+ + 	_AM33XX_MUXENTRY(GPMC_CSN0, 0,
+ + 		"gpmc_csn0", NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, "gpio1_29"),
+ + 	_AM33XX_MUXENTRY(GPMC_CSN1, 0,
+ + 		"gpmc_csn1", "gpmc_clk", "mmc1_clk", "pr1_edio_data_in6",
+ + 		"pr1_edio_data_out6", "pr1_pru1_pru_r30_12", "pr1_pru1_pru_r31_12", "gpio1_30"),
+ + 	_AM33XX_MUXENTRY(GPMC_CSN2, 0,
+ + 		"gpmc_csn2", NULL, "mmc1_cmd", NULL,
+ + 		NULL, NULL, NULL, "gpio1_31"),
+ + 	_AM33XX_MUXENTRY(GPMC_CSN3, 0,
+ + 		"gpmc_csn3", NULL, NULL, "mmc2_cmd",
+ + 		NULL, NULL, NULL, "gpio2_0"),
+ + 	_AM33XX_MUXENTRY(GPMC_CLK, 0,
+ + 		"gpmc_clk", "lcd_memory_clk_mux", NULL, "mmc2_clk",
+ + 		NULL, NULL, "mcasp0_fsr", "gpio2_1"),
+ + 	_AM33XX_MUXENTRY(GPMC_ADVN_ALE, 0,
+ + 		"gpmc_advn_ale", NULL, "timer4", NULL,
+ + 		NULL, NULL, NULL, "gpio2_2"),
+ + 	_AM33XX_MUXENTRY(GPMC_OEN_REN, 0,
+ + 		"gpmc_oen_ren", NULL, "timer7", NULL,
+ + 		NULL, NULL, NULL, "gpio2_3"),
+ + 	_AM33XX_MUXENTRY(GPMC_WEN, 0,
+ + 		"gpmc_wen", NULL, "timer6", NULL,
+ + 		NULL, NULL, NULL, "gpio2_4"),
+ + 	_AM33XX_MUXENTRY(GPMC_BEN0_CLE, 0,
+ + 		"gpmc_ben0_cle", NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, "gpio2_5"),
+ + 	_AM33XX_MUXENTRY(LCD_DATA0, 0,
+ + 		"lcd_data0", "gpmc_a0", NULL, NULL,
+ + 		NULL, NULL, NULL, "gpio2_6"),
+ + 	_AM33XX_MUXENTRY(LCD_DATA1, 0,
+ + 		"lcd_data1", "gpmc_a1", NULL, NULL,
+ + 		NULL, NULL, NULL, "gpio2_7"),
+ + 	_AM33XX_MUXENTRY(LCD_DATA2, 0,
+ + 		"lcd_data2", "gpmc_a2", NULL, NULL,
+ + 		NULL, NULL, NULL, "gpio2_8"),
+ + 	_AM33XX_MUXENTRY(LCD_DATA3, 0,
+ + 		"lcd_data3", "gpmc_a3", NULL, NULL,
+ + 		NULL, NULL, NULL, "gpio2_9"),
+ + 	_AM33XX_MUXENTRY(LCD_DATA4, 0,
+ + 		"lcd_data4", "gpmc_a4", NULL, NULL,
+ + 		NULL, NULL, NULL, "gpio2_10"),
+ + 	_AM33XX_MUXENTRY(LCD_DATA5, 0,
+ + 		"lcd_data5", "gpmc_a5", NULL, NULL,
+ + 		NULL, NULL, NULL, "gpio2_11"),
+ + 	_AM33XX_MUXENTRY(LCD_DATA6, 0,
+ + 		"lcd_data6", "gpmc_a6", NULL, NULL,
+ + 		NULL, NULL, NULL, "gpio2_12"),
+ + 	_AM33XX_MUXENTRY(LCD_DATA7, 0,
+ + 		"lcd_data7", "gpmc_a7", NULL, NULL,
+ + 		NULL, NULL, NULL, "gpio2_13"),
+ + 	_AM33XX_MUXENTRY(LCD_DATA8, 0,
+ + 		"lcd_data8", "gpmc_a12", NULL, "mcasp0_aclkx",
+ + 		NULL, NULL, "uart2_ctsn", "gpio2_14"),
+ + 	_AM33XX_MUXENTRY(LCD_DATA9, 0,
+ + 		"lcd_data9", "gpmc_a13", NULL, "mcasp0_fsx",
+ + 		NULL, NULL, "uart2_rtsn", "gpio2_15"),
+ + 	_AM33XX_MUXENTRY(LCD_DATA10, 0,
+ + 		"lcd_data10", "gpmc_a14", NULL, "mcasp0_axr0",
+ + 		NULL, NULL, NULL, "gpio2_16"),
+ + 	_AM33XX_MUXENTRY(LCD_DATA11, 0,
+ + 		"lcd_data11", "gpmc_a15", NULL, "mcasp0_ahclkr",
+ + 		"mcasp0_axr2", NULL, NULL, "gpio2_17"),
+ + 	_AM33XX_MUXENTRY(LCD_DATA12, 0,
+ + 		"lcd_data12", "gpmc_a16", "eQEP1A_in", "mcasp0_aclkr",
+ + 		"mcasp0_axr2", "pr1_mii0_rxlink", "uart4_ctsn", "gpio0_8"),
+ + 	_AM33XX_MUXENTRY(LCD_DATA13, 0,
+ + 		"lcd_data13", "gpmc_a17", "eQEP1B_in", "mcasp0_fsr",
+ + 		"mcasp0_axr3", "pr1_mii0_rxer", "uart4_rtsn", "gpio0_9"),
+ + 	_AM33XX_MUXENTRY(LCD_DATA14, 0,
+ + 		"lcd_data14", "gpmc_a18", NULL, "mcasp0_axr1",
+ + 		NULL, NULL, NULL, "gpio0_10"),
+ + 	_AM33XX_MUXENTRY(LCD_DATA15, 0,
+ + 		"lcd_data15", "gpmc_a19", NULL, "mcasp0_ahclkx",
+ + 		"mcasp0_axr3", NULL, NULL, "gpio0_11"),
+ + 	_AM33XX_MUXENTRY(LCD_VSYNC, 0,
+ + 		"lcd_vsync", NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, "gpio2_22"),
+ + 	_AM33XX_MUXENTRY(LCD_HSYNC, 0,
+ + 		"lcd_hsync", NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, "gpio2_23"),
+ + 	_AM33XX_MUXENTRY(LCD_PCLK, 0,
+ + 		"lcd_pclk", NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, "gpio2_24"),
+ + 	_AM33XX_MUXENTRY(LCD_AC_BIAS_EN, 0,
+ + 		"lcd_ac_bias_en", NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, "gpio2_25"),
+ + 	_AM33XX_MUXENTRY(MMC0_DAT3, 0,
+ + 		"mmc0_dat3", NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, "gpio2_26"),
+ + 	_AM33XX_MUXENTRY(MMC0_DAT2, 0,
+ + 		"mmc0_dat2", NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, "gpio2_27"),
+ + 	_AM33XX_MUXENTRY(MMC0_DAT1, 0,
+ + 		"mmc0_dat1", NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, "gpio2_28"),
+ + 	_AM33XX_MUXENTRY(MMC0_DAT0, 0,
+ + 		"mmc0_dat0", NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, "gpio2_29"),
+ + 	_AM33XX_MUXENTRY(MMC0_CLK, 0,
+ + 		"mmc0_clk", NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, "gpio2_30"),
+ + 	_AM33XX_MUXENTRY(MMC0_CMD, 0,
+ + 		"mmc0_cmd", NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, "gpio2_31"),
+ + 	_AM33XX_MUXENTRY(MII1_COL, 0,
+ + 		"mii1_col", "rmii2_refclk", "spi1_sclk", NULL,
+ + 		"mcasp1_axr2", "mmc2_dat3", "mcasp0_axr2", "gpio3_0"),
+ + 	_AM33XX_MUXENTRY(MII1_CRS, 0,
+ + 		"mii1_crs", "rmii1_crs_dv", "spi1_d0", "i2c1_sda",
+ + 		"mcasp1_aclkx", NULL, NULL, "gpio3_1"),
+ + 	_AM33XX_MUXENTRY(MII1_RXERR, 0,
+ + 		"mii1_rxerr", "rmii1_rxerr", "spi1_d1", "i2c1_scl",
+ + 		"mcasp1_fsx", NULL, NULL, "gpio3_2"),
+ + 	_AM33XX_MUXENTRY(MII1_TXEN, 0,
+ + 		"mii1_txen", "rmii1_txen", "rgmii1_tctl", NULL,
+ + 		"mcasp1_axr0", NULL, "mmc2_cmd", "gpio3_3"),
+ + 	_AM33XX_MUXENTRY(MII1_RXDV, 0,
+ + 		"mii1_rxdv", NULL, "rgmii1_rctl", NULL,
+ + 		"mcasp1_aclx", "mmc2_dat0", "mcasp0_aclkr", "gpio3_4"),
+ + 	_AM33XX_MUXENTRY(MII1_TXD3, 0,
+ + 		"mii1_txd3", NULL, "rgmii1_td3", NULL,
+ + 		"mcasp1_fsx", "mmc2_dat1", "mcasp0_fsr", "gpio0_16"),
+ + 	_AM33XX_MUXENTRY(MII1_TXD2, 0,
+ + 		"mii1_txd2", NULL, "rgmii1_td2", NULL,
+ + 		"mcasp1_axr0", "mmc2_dat2", "mcasp0_ahclkx", "gpio0_17"),
+ + 	_AM33XX_MUXENTRY(MII1_TXD1, 0,
+ + 		"mii1_txd1", "rmii1_txd1", "rgmii1_td1", "mcasp1_fsr",
+ + 		"mcasp1_axr1", NULL, "mmc1_cmd", "gpio0_21"),
+ + 	_AM33XX_MUXENTRY(MII1_TXD0, 0,
+ + 		"mii1_txd0", "rmii1_txd0", "rgmii1_td0", "mcasp1_axr2",
+ + 		"mcasp1_aclkr", NULL, "mmc1_clk", "gpio0_28"),
+ + 	_AM33XX_MUXENTRY(MII1_TXCLK, 0,
+ + 		"mii1_txclk", NULL, "rgmii1_tclk", "mmc0_dat7",
+ + 		"mmc1_dat0", NULL, "mcasp0_aclkx", "gpio3_9"),
+ + 	_AM33XX_MUXENTRY(MII1_RXCLK, 0,
+ + 		"mii1_rxclk", NULL, "rgmii1_rclk", "mmc0_dat6",
+ + 		"mmc1_dat1", NULL, "mcasp0_fsx", "gpio3_10"),
+ + 	_AM33XX_MUXENTRY(MII1_RXD3, 0,
+ + 		"mii1_rxd3", NULL, "rgmii1_rd3", "mmc0_dat5",
+ + 		"mmc1_dat2", NULL, "mcasp0_axr0", "gpio2_18"),
+ + 	_AM33XX_MUXENTRY(MII1_RXD2, 0,
+ + 		"mii1_rxd2", NULL, "rgmii1_rd2", "mmc0_dat4",
+ + 		"mmc1_dat3", NULL, "mcasp0_axr1", "gpio2_19"),
+ + 	_AM33XX_MUXENTRY(MII1_RXD1, 0,
+ + 		"mii1_rxd1", "rmii1_rxd1", "rgmii1_rd1", "mcasp1_axr3",
+ + 		"mcasp1_fsr", NULL, "mmc2_clk", "gpio2_20"),
+ + 	_AM33XX_MUXENTRY(MII1_RXD0, 0,
+ + 		"mii1_rxd0", "rmii1_rxd0", "rgmii1_rd0", "mcasp1_ahclkx",
+ + 		"mcasp1_ahclkr", "mcasp1_aclkr", "mcasp0_axr3", "gpio2_21"),
+ + 	_AM33XX_MUXENTRY(MII1_REFCLK, 0,
+ + 		"rmii1_refclk", NULL, "spi1_cs0", NULL,
+ + 		"mcasp1_axr3", "mmc0_pow", "mcasp1_ahclkx", "gpio0_29"),
+ + 	_AM33XX_MUXENTRY(MDIO_DATA, 0,
+ + 		"mdio_data", NULL, NULL, NULL,
+ + 		"mmc0_sdcd", "mmc1_cmd", "mmc2_cmd", "gpio0_0"),
+ + 	_AM33XX_MUXENTRY(MDIO_CLK, 0,
+ + 		"mdio_clk", NULL, NULL, NULL,
+ + 		"mmc0_sdwp", "mmc1_clk", "mmc2_clk", "gpio0_1"),
+ + 	_AM33XX_MUXENTRY(SPI0_SCLK, 0,
+ + 		"spi0_sclk", "uart2_rxd", "i2c2_sda", NULL,
+ + 		NULL, NULL, NULL, "gpio0_2"),
+ + 	_AM33XX_MUXENTRY(SPI0_D0, 0,
+ + 		"spi0_d0", "uart2_txd", "i2c2_scl", NULL,
+ + 		NULL, NULL, NULL, "gpio0_3"),
+ + 	_AM33XX_MUXENTRY(SPI0_D1, 0,
+ + 		"spi0_d1", "mmc1_sdwp", "i2c1_sda", NULL,
+ + 		NULL, NULL, NULL, "gpio0_4"),
+ + 	_AM33XX_MUXENTRY(SPI0_CS0, 0,
+ + 		"spi0_cs0", "mmc2_sdwp", "i2c1_scl", NULL,
+ + 		NULL, NULL, NULL, "gpio0_5"),
+ + 	_AM33XX_MUXENTRY(SPI0_CS1, 0,
+ + 		"spi0_cs1", "uart3_rxd", NULL, "mmc0_pow",
+ + 		NULL, "mmc0_sdcd", NULL, "gpio0_6"),
+ + 	_AM33XX_MUXENTRY(ECAP0_IN_PWM0_OUT, 0,
+ + 		"ecap0_in_pwm0_out", "uart3_txd", "spi1_cs1", "pr1_ecap0_ecap_capin_apwm_o",
+ + 		"spi1_sclk", "mmc0_sdwp", "xdma_event_intr2", "gpio0_7"),
+ + 	_AM33XX_MUXENTRY(UART0_CTSN, 0,
+ + 		"uart0_ctsn", "uart4_rxd", "d_can1_tx", "i2c1_sda",
+ + 		"spi1_d0", "timer7", "pr1_edc_sync0_out", "gpio1_8"),
+ + 	_AM33XX_MUXENTRY(UART0_RTSN, 0,
+ + 		"uart0_rtsn", "uart4_txd", "d_can1_rx", "i2c1_scl",
+ + 		"spi1_d1", "spi1_cs0", "pr1_edc_sync1_out", "gpio1_9"),
+ + 	_AM33XX_MUXENTRY(UART0_RXD, 0,
+ + 		"uart0_rxd", "spi1_cs0", "d_can0_tx", "i2c2_sda",
+ + 		NULL, NULL, NULL, "gpio1_10"),
+ + 	_AM33XX_MUXENTRY(UART0_TXD, 0,
+ + 		"uart0_txd", "spi1_cs1", "d_can0_rx", "i2c2_scl",
+ + 		NULL, NULL, NULL, "gpio1_11"),
+ + 	_AM33XX_MUXENTRY(UART1_CTSN, 0,
+ + 		"uart1_ctsn", "timer6", "dcan0_tx", "i2c2_sda",
+ + 		"spi1_cs0", "pr1_uart0_cts_n", "pr1_edc_latch0_in", "gpio0_12"),
+ + 	_AM33XX_MUXENTRY(UART1_RTSN, 0,
+ + 	"uart1_rtsn", "timer5", "dcan0_rx", "i2c2_scl",
+ + 		"spi1_cs1", "pr1_uart0_rts_n", "pr1_edc_latch1_in", "gpio0_13"),
+ + 	_AM33XX_MUXENTRY(UART1_RXD, 0,
+ + 		"uart1_rxd", "mmc1_sdwp", "dcan1_tx", "i2c1_sda",
+ + 		NULL, "pr1_uart0_rxd", "pr1_pru1_pru_r31_16", "gpio0_14"),
+ + 	_AM33XX_MUXENTRY(UART1_TXD, 0,
+ + 		"uart1_txd", "mmc2_sdwp", "dcan1_rx", "i2c1_scl",
+ + 		NULL, "pr1_uart0_txd", "pr1_pru0_pru_r31_16", "gpio0_15"),
+ + 	_AM33XX_MUXENTRY(I2C0_SDA, 0,
+ + 		"i2c0_sda", NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, "gpio3_5"),
+ + 	_AM33XX_MUXENTRY(I2C0_SCL, 0,
+ + 		"i2c0_scl", NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, "gpio3_6"),
+ + 	_AM33XX_MUXENTRY(MCASP0_ACLKX, 0,
+ + 		"mcasp0_aclkx", "ehrpwm0A", NULL, "spi1_sclk",
+ + 		"mmc0_sdcd", "pr1_pru0_pru_r30_0", "pr1_pru0_pru_r31_0", "gpio3_14"),
+ + 	_AM33XX_MUXENTRY(MCASP0_FSX, 0,
+ + 		"mcasp0_fsx", "ehrpwm0B", NULL, "spi1_d0",
+ + 		"mmc1_sdcd", "pr1_pru0_pru_r30_1", "pr1_pru0_pru_r31_1", "gpio3_15"),
+ + 	_AM33XX_MUXENTRY(MCASP0_AXR0, 0,
+ + 		"mcasp0_axr0", "ehrpwm0_tripzone_input", NULL, "spi1_d1",
+ + 		"mmc2_sdcd", "pr1_pru0_pru_r30_2", "pr1_pru0_pru_r31_2", "gpio3_16"),
+ + 	_AM33XX_MUXENTRY(MCASP0_AHCLKR, 0,
+ + 		"mcasp0_ahclkr", "ehrpwm0_synci", "mcasp0_axr2", "spi1_cs0",
+ + 		"ecap2_in_pwm2_out", "pr1_pru0_pru_r30_3", "pr1_pru0_pru_r31_3", "gpio3_17"),
+ + 	_AM33XX_MUXENTRY(MCASP0_ACLKR, 0,
+ + 		"mcasp0_aclkr", NULL, "mcasp0_axr2", "mcasp1_aclkx",
+ + 		"mmc0_sdwp", NULL, NULL, "gpio3_18"),
+ + 	_AM33XX_MUXENTRY(MCASP0_FSR, 0,
+ + 		"mcasp0_fsr", "eQEP0B_in", "mcasp0_axr3", "mcasp1_fsx",
+ + 		"EMU2", "pr1_pru0_pru_r30_5", "pr1_pru0_pru_r31_5", "gpio3_19"),
+ + 	_AM33XX_MUXENTRY(MCASP0_AXR1, 0,
+ + 		"mcasp0_axr1", "eQEP0_index", NULL, "mcasp1_axr0",
+ + 		"EMU3", "pr1_pru0_pru_r30_6", "pr1_pru0_pru_r31_6", "gpio3_20"),
+ + 	_AM33XX_MUXENTRY(MCASP0_AHCLKX, 0,
+ + 		"mcasp0_ahclkx", "eQEP0_strobe", "mcasp0_axr3", "mcasp1_axr1",
+ + 		"EMU4", "pr1_pru0_pru_r30_7", "pr1_pru0_pru_r31_7", "gpio3_21"),
+ + 	_AM33XX_MUXENTRY(XDMA_EVENT_INTR0, 0,
+ + 		"xdma_event_intr0", NULL, "timer4", "clkout1",
+ + 		"spi1_cs1", "pr1_pru1_pru_r31_16", "EMU2", "gpio0_19"),
+ + 	_AM33XX_MUXENTRY(XDMA_EVENT_INTR1, 0,
+ + 		"xdma_event_intr1", NULL, "tclkin", "clkout2",
+ + 		"timer7", "pr1_pru0_pru_r31_16", "EMU3", "gpio0_20"),
+ + 	_AM33XX_MUXENTRY(WARMRSTN, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(PWRONRSTN, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(NMIN, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(XTALIN, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(XTALOUT, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(TMS, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(TDI, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(TDO, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(TCK, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(TRSTN, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(EMU0, 0,
+ + 		"emu0", NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, "gpio3_7"),
+ + 	_AM33XX_MUXENTRY(EMU1, 0,
+ + 		"emu1", NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, "gpio3_8"),
+ + 	_AM33XX_MUXENTRY(RTC_XTALIN, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(RTC_XTALOUT, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(RTC_PWRONRSTN, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(PMIC_POWER_EN, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(EXT_WAKEUP, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(USB0_DRVVBUS, 0,
+ + 		"usb0_drvvbus", NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, "gpio0_18"),
+ + 	_AM33XX_MUXENTRY(USB1_DRVVBUS, 0,
+ + 		"usb1_drvvbus", NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, "gpio3_13"),
+ + 	_AM33XX_MUXENTRY(DDR_RESETN, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_CSN0, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_CKE, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_CK, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_CKN, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_CASN, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_RASN, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_WEN, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_BA0, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_BA1, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_BA2, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_A0, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_A1, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_A2, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_A3, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_A4, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_A5, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_A6, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_A7, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_A8, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_A9, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_A10, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_A11, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_A12, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_A13, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_A14, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_A15, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_ODT, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_D0, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_D1, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_D2, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_D3, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_D4, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_D5, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_D6, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_D7, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_D8, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_D9, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_D10, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_D11, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_D12, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_D13, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_D14, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_D15, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_DQM0, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_DQM1, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_DQS0, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_DQSN0, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_DQS1, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_DQSN1, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_VREF, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(DDR_VTP, 0,
+ + 		NULL, NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(AIN0, 0,
+ + 		"ain0", NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(AIN1, 0,
+ + 		"ain1", NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(AIN2, 0,
+ + 		"ain2", NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(AIN3, 0,
+ + 		"ain3", NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(VREFP, 0,
+ + 		"vrefp", NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	_AM33XX_MUXENTRY(VREFN, 0,
+ + 		"vrefn", NULL, NULL, NULL,
+ + 		NULL, NULL, NULL, NULL),
+ + 	{ .reg_offset = OMAP_MUX_TERMINATOR },
+ + };
+ + 
+ + int __init am33xx_mux_init(struct omap_board_mux *board_subset)
+ + {
+ + 	return omap_mux_init("core", 0, AM33XX_CONTROL_PADCONF_MUX_PBASE,
+ + 			AM33XX_CONTROL_PADCONF_MUX_SIZE, am33xx_muxmodes,
+ + 			NULL, board_subset, NULL);
+ + }
+ + 
+ + #ifdef CONFIG_SUSPEND
+ + struct am33xx_padconf_regs {
+ + 	u16 offset;
+ + 	u32 val;
+ + };
+ + 
+ + static struct am33xx_padconf_regs am33xx_lp_padconf[] = {
+ + 	{.offset = AM33XX_CONTROL_GMII_SEL_OFFSET},
+ + 	{.offset = AM33XX_CONTROL_PADCONF_GPMC_A0_OFFSET},
+ + 	{.offset = AM33XX_CONTROL_PADCONF_GPMC_A1_OFFSET},
+ + 	{.offset = AM33XX_CONTROL_PADCONF_GPMC_A2_OFFSET},
+ + 	{.offset = AM33XX_CONTROL_PADCONF_GPMC_A3_OFFSET},
+ + 	{.offset = AM33XX_CONTROL_PADCONF_GPMC_A4_OFFSET},
+ + 	{.offset = AM33XX_CONTROL_PADCONF_GPMC_A5_OFFSET},
+ + 	{.offset = AM33XX_CONTROL_PADCONF_GPMC_A6_OFFSET},
+ + 	{.offset = AM33XX_CONTROL_PADCONF_GPMC_A7_OFFSET},
+ + 	{.offset = AM33XX_CONTROL_PADCONF_GPMC_A8_OFFSET},
+ + 	{.offset = AM33XX_CONTROL_PADCONF_GPMC_A9_OFFSET},
+ + 	{.offset = AM33XX_CONTROL_PADCONF_GPMC_A10_OFFSET},
+ + 	{.offset = AM33XX_CONTROL_PADCONF_GPMC_A11_OFFSET},
+ + 	{.offset = AM33XX_CONTROL_PADCONF_GPMC_WAIT0_OFFSET},
+ + 	{.offset = AM33XX_CONTROL_PADCONF_GPMC_WPN_OFFSET},
+ + 	{.offset = AM33XX_CONTROL_PADCONF_GPMC_BEN1_OFFSET},
+ + 	{.offset = AM33XX_CONTROL_PADCONF_MII1_COL_OFFSET},
+ + 	{.offset = AM33XX_CONTROL_PADCONF_MII1_CRS_OFFSET},
+ + 	{.offset = AM33XX_CONTROL_PADCONF_MII1_RXERR_OFFSET},
+ + 	{.offset = AM33XX_CONTROL_PADCONF_MII1_TXEN_OFFSET},
+ + 	{.offset = AM33XX_CONTROL_PADCONF_MII1_RXDV_OFFSET},
+ + 	{.offset = AM33XX_CONTROL_PADCONF_MII1_TXD3_OFFSET},
+ + 	{.offset = AM33XX_CONTROL_PADCONF_MII1_TXD2_OFFSET},
+ + 	{.offset = AM33XX_CONTROL_PADCONF_MII1_TXD1_OFFSET},
+ + 	{.offset = AM33XX_CONTROL_PADCONF_MII1_TXD0_OFFSET},
+ + 	{.offset = AM33XX_CONTROL_PADCONF_MII1_TXCLK_OFFSET},
+ + 	{.offset = AM33XX_CONTROL_PADCONF_MII1_RXCLK_OFFSET},
+ + 	{.offset = AM33XX_CONTROL_PADCONF_MII1_RXD3_OFFSET},
+ + 	{.offset = AM33XX_CONTROL_PADCONF_MII1_RXD2_OFFSET},
+ + 	{.offset = AM33XX_CONTROL_PADCONF_MII1_RXD1_OFFSET},
+ + 	{.offset = AM33XX_CONTROL_PADCONF_MII1_RXD0_OFFSET},
+ + 	{.offset = AM33XX_CONTROL_PADCONF_MII1_REFCLK_OFFSET},
+ + 	{.offset = AM33XX_CONTROL_PADCONF_MDIO_DATA_OFFSET},
+ + 	{.offset = AM33XX_CONTROL_PADCONF_MDIO_CLK_OFFSET},
+ + };
+ + #endif /* CONFIG_SUSPEND */
+ + 
+ + struct susp_io_pad_conf {
+ + 	u32 enabled;
+ + 	u32 val;
+ + };
+ + 
+ + static u32 susp_io_pad_conf_enabled;
+ + static struct susp_io_pad_conf pad_array[MAX_IO_PADCONF];
+ + 
+ + struct standby_gpio_pad_struct {
+ + 	u32 enabled;
+ + 	u32 gpio_request_success;
+ + 	u32 pin_val;
+ + 	u32 trigger;
+ + 	u32 gpio_pin;
+ + 	u32 curr_pin_mux;
+ + };
+ + 
+ + static struct standby_gpio_pad_struct standby_gpio_array[MAX_IO_PADCONF];
+ + 
+ + /*
+ +  * Expected input: 1/0
+ +  * Example: "echo 1 > enable_suspend_io_pad_conf" enables IO PAD Config
+ +  */
+ + static int susp_io_pad_enable_set(void *data, u64 val)
+ + {
+ + 	u32 *enabled = data;
+ + 
+ + 	*enabled = val & 0x1;
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static int susp_io_pad_enable_get(void *data, u64 *val)
+ + {
+ + 	u32 *enabled = data;
+ + 
+ + 	*val = *enabled;
+ + 
+ + 	return 0;
+ + }
+ + 
+ + DEFINE_SIMPLE_ATTRIBUTE(susp_io_pad_enable_fops, susp_io_pad_enable_get,
+ + 			susp_io_pad_enable_set, "%llx\n");
+ + 
+ + static unsigned int am335x_pin_mux_addr_to_skip[] = {
+ + 	0x9bc,
+ + 	0x9c4, 0x9c8, 0x9cc,
+ + 	0x9ec,
+ + 	0x9f0, 0x9f4,
+ + 	0xa08, 0xa0c,
+ + 	0xa10, 0xa14, 0xa18,
+ + 	0xa20, 0xa24, 0xa28, 0xa2c,
+ + 	0xa30,
+ + };
+ + 
+ + static int susp_io_pad_status_show(struct seq_file *s, void *unused)
+ + {
+ + 	struct omap_mux *mux_arr = &am33xx_muxmodes[0];
+ + 	u32 *enabled = s->private;
+ + 	int i;
+ + 
+ + 	if (!*enabled) {
+ + 		pr_err("%s: IO PAD Configuration is not enabled\n", __func__);
+ + 		return 0;
+ + 	}
+ + 
+ + 	for (i = 0; i < MAX_IO_PADCONF;) {
+ + 		int off, j, addr_match = 0;
+ + 
+ + 		if (pad_array[i].enabled) {
+ + 			int mode = pad_array[i].val & OMAP_MUX_MODE7;
+ + 			seq_printf(s, "%s.%s (0x%08x = 0x%02x)\n",
+ + 				mux_arr->muxnames[0], mux_arr->muxnames[mode],
+ + 				(unsigned int)(AM33XX_CONTROL_PADCONF_MUX_PBASE
+ + 				+ mux_arr->reg_offset),
+ + 				pad_array[i].val);
+ + 		}
+ + 
+ + 		i++;
+ + 
+ + 		/*
+ + 		 * AM335x pin-mux register offset sequence is broken, meaning
+ + 		 * there is no pin-mux setting at some offset and at some
+ + 		 * offsets, the modes are not supposed to be changed. Because
+ + 		 * of this, the "am33xx_muxmodes" array above will not have any
+ + 		 * values at these indexes. Hence the pad_array &
+ + 		 * am33xx_muxmodes array will be out of sync at these index.
+ + 		 * Handle missing pin-mux entries accordingly by using a special
+ + 		 * array that indicate these offsets.
+ + 		 */
+ + 		off = ((i * 4) + 0x800);
+ + 		for (j = 0; j < ARRAY_SIZE(am335x_pin_mux_addr_to_skip); j++) {
+ + 			if (off == am335x_pin_mux_addr_to_skip[j]) {
+ + 				addr_match = 1;
+ + 				break;
+ + 			}
+ + 		}
+ + 		if (addr_match == 0)
+ + 			mux_arr++;
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /*
+ +  * Expected input: pinmux_name=<value1>
+ +  *	pinmux_name = Pin-mux name that is to be setup during suspend with value
+ +  *		<value1>. Pin-mux name should be in "mode0_name.function_name"
+ +  *		format. Internally the pin-mux offset is calculated from the
+ +  *		pin-mux names. Invalid pin-mux names and values are ignored.
+ +  *		Remember, NO spaces anywhere in the input.
+ +  *
+ +  * Example:
+ +  *	  echo mcasp0_aclkx.gpio3_14=0x27 > suspend_pad_conf
+ +  *		stores 0x27 as the value to be written to the pinmux (with
+ +  *		mode0_name.function_name as mcasp0_aclkx.gpio3_14) when entering
+ +  *		suspend
+ +  */
+ + static ssize_t susp_io_pad_write(struct file *file,
+ + 					 const char __user *user_buf,
+ + 					 size_t count, loff_t *ppos)
+ + {
+ + 	struct seq_file *seqf;
+ + 	u32 *enabled, val;
+ + 	char *export_string, *token, *name;
+ + 
+ + 	seqf = file->private_data;
+ + 	enabled = seqf->private;
+ + 
+ + 	if (!*enabled) {
+ + 		pr_err("%s: IO PAD Configuration is not enabled\n", __func__);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	export_string = kzalloc(count + 1, GFP_KERNEL);
+ + 	if (!export_string)
+ + 		return -ENOMEM;
+ + 
+ + 	if (copy_from_user(export_string, user_buf, count)) {
+ + 		kfree(export_string);
+ + 		return -EFAULT;
+ + 	}
+ + 
+ + 	token = export_string;
+ + 	name = strsep(&token, "=");
+ + 	if (name) {
+ + 		struct omap_mux_partition *partition = NULL;
+ + 		struct omap_mux *mux = NULL;
+ + 		int mux_index, mux_mode;
+ + 		int res;
+ + 
+ + 		mux_mode = omap_mux_get_by_name(name, &partition, &mux);
+ + 		if (mux_mode < 0) {
+ + 			pr_err("%s: Invalid mux name (%s). Ignoring the"
+ + 					" value\n", __func__, name);
+ + 			goto err_out;
+ + 		}
+ + 
+ + 		res = kstrtouint(token, 0, &val);
+ + 		if (res < 0) {
+ + 			pr_err("%s: Invalid value (%s). Ignoring\n",
+ + 						__func__, token);
+ + 			goto err_out;
+ + 		}
+ + 
+ + 		mux_index = (mux->reg_offset -
+ + 			AM33XX_CONTROL_PADCONF_GPMC_AD0_OFFSET) / 4;
+ + 
+ + 		if (mux_index > MAX_IO_PADCONF) {
+ + 			pr_err("%s: Invalid index (0x%x). Ignoring\n",
+ + 						__func__, mux_index);
+ + 			goto err_out;
+ + 		}
+ + 
+ + 		pad_array[mux_index].enabled = true;
+ + 		pad_array[mux_index].val = val;
+ + 	} else {
+ + 		pr_err("%s: Invalid mux name (%s). Ignoring the entry\n",
+ + 						__func__, export_string);
+ + 	}
+ + 
+ + err_out:
+ + 	*ppos += count;
+ + 	kfree(export_string);
+ + 	return count;
+ + }
+ + 
+ + static int susp_io_pad_open(struct inode *inode, struct file *file)
+ + {
+ + 	return single_open(file, susp_io_pad_status_show, inode->i_private);
+ + }
+ + 
+ + static const struct file_operations susp_io_pad_fops = {
+ + 	.open		= susp_io_pad_open,
+ + 	.read		= seq_read,
+ + 	.write		= susp_io_pad_write,
+ + 	.release	= single_release,
+ + };
+ + 
+ + static int standby_gpio_status_show(struct seq_file *s, void *unused)
+ + {
+ + 	struct omap_mux *mux_arr = &am33xx_muxmodes[0];
+ + 
+ + 	int i;
+ + 
+ + 	for (i = 0; i < MAX_IO_PADCONF;) {
+ + 		int off, j, addr_match = 0;
+ + 		char *trigger;
+ + 
+ + 		if (standby_gpio_array[i].enabled) {
+ + 			switch (standby_gpio_array[i].trigger) {
+ + 			case IRQF_TRIGGER_RISING:
+ + 				trigger = "rising";
+ + 				break;
+ + 
+ + 			case IRQF_TRIGGER_FALLING:
+ + 				trigger = "falling";
+ + 				break;
+ + 
+ + 			case IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING:
+ + 			/* fall through */
+ + 			default:
+ + 				trigger = "falling_rising";
+ + 				break;
+ + 			}
+ + 
+ + 			seq_printf(s, "%s.%s (0x%08x = 0x%02x), trigger = %s\n",
+ + 				mux_arr->muxnames[0],
+ + 				mux_arr->muxnames[OMAP_MUX_MODE7],
+ + 				(unsigned int)(AM33XX_CONTROL_PADCONF_MUX_PBASE
+ + 				+ mux_arr->reg_offset),
+ + 				standby_gpio_array[i].pin_val,
+ + 				trigger);
+ + 
+ + 
+ + 		}
+ + 
+ + 		/*
+ + 		 * AM335x pin-mux register offset sequence is broken, meaning
+ + 		 * there is no pin-mux setting at some offset and at some
+ + 		 * offsets, the modes are not supposed to be changed. Because
+ + 		 * of this, the "am33xx_muxmodes" array above will not have any
+ + 		 * values at these indexes. Hence the standby_gpio_array &
+ + 		 * am33xx_muxmodes array will be out of sync at these index.
+ + 		 * Handle missing pin-mux entries accordingly by using a special
+ + 		 * array that indicate these offsets.
+ + 		 */
+ + 
+ + 		i++;
+ + 		off = ((i * 4) + 0x800);
+ + 		for (j = 0; j < ARRAY_SIZE(am335x_pin_mux_addr_to_skip); j++) {
+ + 			if (off == am335x_pin_mux_addr_to_skip[j]) {
+ + 				addr_match = 1;
+ + 				break;
+ + 			}
+ + 		}
+ + 		if (addr_match == 0)
+ + 			mux_arr++;
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /*
+ +  * Expected input: pinmux_name=<value1>,<trigger>
+ +  *	pinmux_name = Pin-mux name that is to be setup as gpio during standby
+ +  *		suspend with gpio interrupt trigger mode as per <trigger> field
+ +  *		with value <value1>.
+ +  *		Pin-mux name should be in "mode0_name.mode7_function_name"
+ +  *		format. Internally the pin-mux offset is calculated from the
+ +  *		pin-mux names. Invalid pin-mux names and values are ignored.
+ +  *		Remember,
+ +  *			- No spaces anywhere in the input.
+ +  *			- <value1> field is a must
+ +  *			- <trigger> field is a must and must be one of "rising",
+ +  *			  "falling"
+ +  *
+ +  * Example:
+ +  *	  echo uart0_rxd.gpio1_10=0x27,rising > standby_gpio_pad_conf
+ +  *		sets up uart0_rxd.gpio1_10 for gpio mode with interrupt trigger
+ +  *		as rising and pin-mux value as 0x27 when entering standby mode.
+ +  */
+ + static ssize_t standby_gpio_pad_write(struct file *file,
+ + 					 const char __user *user_buf,
+ + 					 size_t count, loff_t *ppos)
+ + {
+ + 	u32 trigger;
+ + 	char *export_string, *token, *name;
+ + 
+ + 	export_string = kzalloc(count + 1, GFP_KERNEL);
+ + 	if (!export_string)
+ + 		return -ENOMEM;
+ + 
+ + 	if (copy_from_user(export_string, user_buf, count)) {
+ + 		kfree(export_string);
+ + 		return -EFAULT;
+ + 	}
+ + 
+ + 	export_string[count-1] = '\0';   /* force null terminator */
+ + 	token = export_string;
+ + 	name = strsep(&token, "=");
+ + 	if (name) {
+ + 		struct omap_mux_partition *partition = NULL;
+ + 		struct omap_mux *mux = NULL;
+ + 		int mux_index, mux_mode, gpio_bank, gpio_pin, res, pin_val;
+ + 		char *gpio_name;
+ + 
+ + 		mux_mode = omap_mux_get_by_name(name, &partition, &mux);
+ + 		if (mux_mode < 0) {
+ + 			pr_err("%s: Invalid mux name (%s). Ignoring the"
+ + 					" value\n", __func__, name);
+ + 			goto err_out;
+ + 		}
+ + 
+ + 		name = strsep(&token, ",");
+ + 		if (!name) {
+ + 			pr_err("%s: Invalid value (%s). Ignoring\n",
+ + 				__func__, token);
+ + 			goto err_out;
+ + 		}
+ + 
+ + 		res = kstrtouint(name, 0, &pin_val);
+ + 		if (res < 0) {
+ + 			pr_err("%s: Invalid pin mux value (%s). Ignoring\n",
+ + 						__func__, token);
+ + 			goto err_out;
+ + 		}
+ + 
+ + 		if (token && !strncmp("rising", token, 6)) {
+ + 			trigger = IRQF_TRIGGER_RISING;
+ + 		} else if (token && !strncmp("falling", token, 7)) {
+ + 			trigger = IRQF_TRIGGER_FALLING;
+ + 		} else {
+ + 			pr_err("%s: Invalid trigger (%s). Defaulting to"
+ + 					" falling_rising\n", __func__, token);
+ + 			trigger = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
+ + 		}
+ + 
+ + 		/* confirm whether a gpio pin exists here */
+ + 		gpio_name = mux->muxnames[OMAP_MUX_MODE7];
+ + 
+ + 		if (!gpio_name) {
+ + 			pr_err("%s: Invalid mux name (%s)\n", __func__, name);
+ + 			goto err_out;
+ + 		} else if (strncmp(gpio_name, "gpio", 4)) {
+ + 			pr_err("%s: Invalid mux name found (%s)\n",
+ + 					__func__, gpio_name);
+ + 			goto err_out;
+ + 		}
+ + 
+ + 		/*
+ + 		 * parse the string name and get the gpio bank & pin number.
+ + 		 * gpio_name will be in the format of "gpioX_Y" where
+ + 		 *	X = bank
+ + 		 *	Y = pin number
+ + 		 */
+ + 		gpio_bank = *(gpio_name + 4) - '0';
+ + 
+ + 		gpio_name += 6;
+ + 		res = kstrtoint(gpio_name, 10, &gpio_pin);
+ + 		if (res < 0) {
+ + 			pr_err("%s: Invalid gpio pin number (%s). Ignoring\n",
+ + 				__func__, gpio_name);
+ + 			goto err_out;
+ + 		}
+ + 
+ + 		mux_index = (mux->reg_offset -
+ + 			AM33XX_CONTROL_PADCONF_GPMC_AD0_OFFSET) / 4;
+ + 
+ + 		if (mux_index > MAX_IO_PADCONF) {
+ + 			pr_err("%s: Invalid index (0x%x). Ignoring\n",
+ + 						__func__, mux_index);
+ + 			goto err_out;
+ + 		}
+ + 
+ + 		standby_gpio_array[mux_index].enabled = true;
+ + 		standby_gpio_array[mux_index].pin_val = pin_val;
+ + 		standby_gpio_array[mux_index].trigger = trigger;
+ + 		standby_gpio_array[mux_index].gpio_pin =
+ + 						((gpio_bank * 32) + gpio_pin);
+ + 	} else {
+ + 		pr_err("%s: Invalid mux name (%s). Ignoring the entry\n",
+ + 						__func__, export_string);
+ + 	}
+ + 
+ + err_out:
+ + 	*ppos += count;
+ + 	kfree(export_string);
+ + 	return count;
+ + }
+ + 
+ + static int standby_gpio_pad_open(struct inode *inode, struct file *file)
+ + {
+ + 	return single_open(file, standby_gpio_status_show, inode->i_private);
+ + }
+ + 
+ + static const struct file_operations standby_gpio_pad_conf_fops = {
+ + 	.open		= standby_gpio_pad_open,
+ + 	.read		= seq_read,
+ + 	.write		= standby_gpio_pad_write,
+ + 	.release	= single_release,
+ + };
+ + 
+ + void am33xx_mux_dbg_create_entry(struct dentry *mux_dbg_dir)
+ + {
+ + 	struct dentry *mux_dbg_suspend_io_conf_dir;
+ + 
+ + 	if (!mux_dbg_dir)
+ + 		return;
+ + 
+ + 	/*
+ + 	 * create a directory by the name suspend_io_pad_conf in
+ + 	 * <debugfs-mount-dir>/<mux_dbg_dir>/
+ + 	 */
+ + 	mux_dbg_suspend_io_conf_dir = debugfs_create_dir("suspend_io_pad_conf",
+ + 								mux_dbg_dir);
+ + 	if (!mux_dbg_suspend_io_conf_dir)
+ + 		return;
+ + 
+ + 	memset(pad_array, 0, sizeof(pad_array));
+ + 
+ + 	(void)debugfs_create_file("enable_suspend_io_pad_conf",
+ + 						S_IRUGO | S_IWUSR,
+ + 						mux_dbg_suspend_io_conf_dir,
+ + 						&susp_io_pad_conf_enabled,
+ + 						&susp_io_pad_enable_fops);
+ + 	(void)debugfs_create_file("suspend_pad_conf", S_IRUGO | S_IWUSR,
+ + 						mux_dbg_suspend_io_conf_dir,
+ + 						&susp_io_pad_conf_enabled,
+ + 						&susp_io_pad_fops);
+ + 	(void)debugfs_create_file("standby_gpio_pad_conf", S_IRUGO | S_IWUSR,
+ + 						mux_dbg_dir,
+ + 						&susp_io_pad_conf_enabled,
+ + 						&standby_gpio_pad_conf_fops);
+ + }
+ + 
+ + void am33xx_setup_pinmux_on_suspend(void)
+ + {
+ + 	u32 reg_off, i;
+ + 
+ + 	if (susp_io_pad_conf_enabled == 1) {
+ + 		reg_off = AM33XX_CONTROL_PADCONF_GPMC_AD0_OFFSET;
+ + 		for (i = 0; i < MAX_IO_PADCONF; reg_off += 4, i++) {
+ + 			if (pad_array[i].enabled)
+ + 				writel(pad_array[i].val,
+ + 						AM33XX_CTRL_REGADDR(reg_off));
+ + 		}
+ + 	}
+ + }
+ + 
+ + static u32 am33xx_lp_padconf_complete[MAX_IO_PADCONF];
+ + 
+ + void am335x_save_padconf(void)
+ + {
+ + 	struct am33xx_padconf_regs *temp = am33xx_lp_padconf;
+ + 	u32 reg_off;
+ + 	int i;
+ + 	if (susp_io_pad_conf_enabled == 1) {
+ + 		i = AM33XX_CONTROL_PADCONF_GPMC_AD0_OFFSET;
+ + 		reg_off = 0;
+ + 
+ + 		for (; i < AM33XX_CONTROL_PADCONF_MUX_SIZE; i += 4, reg_off++)
+ + 			am33xx_lp_padconf_complete[reg_off] =
+ + 						readl(AM33XX_CTRL_REGADDR(i));
+ + 	} else {
+ + 		for (i = 0; i < ARRAY_SIZE(am33xx_lp_padconf); i++, temp++)
+ + 			temp->val = readl(AM33XX_CTRL_REGADDR(temp->offset));
+ + 	}
+ + }
+ + 
+ + void am335x_restore_padconf(void)
+ + {
+ + 	struct am33xx_padconf_regs *temp = am33xx_lp_padconf;
+ + 	u32 reg_off;
+ + 	int i;
+ + 	if (susp_io_pad_conf_enabled == 1) {
+ + 		i = AM33XX_CONTROL_PADCONF_GPMC_AD0_OFFSET;
+ + 		reg_off = 0;
+ + 		for (; i < AM33XX_CONTROL_PADCONF_MUX_SIZE; i += 4, reg_off++)
+ + 			writel(am33xx_lp_padconf_complete[reg_off],
+ + 							AM33XX_CTRL_REGADDR(i));
+ + 	} else {
+ + 		for (i = 0; i < ARRAY_SIZE(am33xx_lp_padconf); i++, temp++)
+ + 			writel(temp->val, AM33XX_CTRL_REGADDR(temp->offset));
+ + 	}
+ + }
+ + 
+ + /*
+ +  * Dummy GPIO interrupt Handler
+ +  */
+ + static irqreturn_t gpio_irq(int irq, void *dev_id)
+ + {
+ + 	return IRQ_HANDLED;
+ + }
+ + 
+ + void am33xx_standby_setup(unsigned int state)
+ + {
+ + 	u32 reg_off, i;
+ + 
+ + 	if (state != PM_SUSPEND_STANDBY)
+ + 		return;
+ + 
+ + 	writel(0x2, AM33XX_CM_PER_GPIO1_CLKCTRL);
+ + 	writel(0x2, AM33XX_CM_PER_GPIO2_CLKCTRL);
+ + 	writel(0x2, AM33XX_CM_PER_GPIO3_CLKCTRL);
+ + 
+ + 	reg_off = AM33XX_CONTROL_PADCONF_GPMC_AD0_OFFSET;
+ + 	for (i = 0; i < MAX_IO_PADCONF; reg_off += 4, i++) {
+ + 		if (standby_gpio_array[i].enabled) {
+ + 			int ret, reg_val, irq;
+ + 			u32 gpio_pin = standby_gpio_array[i].gpio_pin;
+ + 
+ + 			reg_val = readl(AM33XX_CTRL_REGADDR(reg_off));
+ + 			standby_gpio_array[i].curr_pin_mux = reg_val;
+ + 			reg_val = standby_gpio_array[i].pin_val;
+ + 			writel(reg_val, AM33XX_CTRL_REGADDR(reg_off));
+ + 
+ + 			ret = gpio_request(gpio_pin, "pm_standby");
+ + 			if (ret) {
+ + 				pr_err("%s: Error in gpio request (%d)\n",
+ + 						__func__, ret);
+ + 				continue;
+ + 			}
+ + 			irq = gpio_to_irq(gpio_pin);
+ + 			if (irq < 0) {
+ + 				gpio_free(gpio_pin);
+ + 				pr_err("%s: gpio_to_irq failed (%d)\n",
+ + 								__func__, irq);
+ + 				continue;
+ + 			}
+ + 			ret = request_irq(irq, gpio_irq,
+ + 						standby_gpio_array[i].trigger,
+ + 						"pm_standby", NULL);
+ + 			if (ret) {
+ + 				gpio_free(gpio_pin);
+ + 				pr_err("%s: interrupt request failed (%d)\n",
+ + 								__func__, ret);
+ + 				continue;
+ + 			}
+ + 
+ + 			standby_gpio_array[i].gpio_request_success = true;
+ + 		}
+ + 	}
+ + 
+ + }
+ + 
+ + void am33xx_standby_release(unsigned int state)
+ + {
+ + 	u32 reg_off, i;
+ + 
+ + 	if (state != PM_SUSPEND_STANDBY)
+ + 		return;
+ + 
+ + 	reg_off = AM33XX_CONTROL_PADCONF_GPMC_AD0_OFFSET;
+ + 	for (i = 0; i < MAX_IO_PADCONF; reg_off += 4, i++) {
+ + 		u32 gpio_pin = standby_gpio_array[i].gpio_pin;
+ + 
+ + 		if (standby_gpio_array[i].enabled) {
+ + 			writel(standby_gpio_array[i].curr_pin_mux,
+ + 						AM33XX_CTRL_REGADDR(reg_off));
+ + 
+ + 			if (standby_gpio_array[i].gpio_request_success ==
+ + 									true) {
+ + 				int irq;
+ + 
+ + 				irq = gpio_to_irq(gpio_pin);
+ + 				gpio_free(gpio_pin);
+ + 				free_irq(irq, 0);
+ + 			}
+ + 		}
+ + 	}
+ + }
+ + 
+ + #else
+ + int __init am33xx_mux_init(struct omap_board_mux *board_subset)
+ + {
+ + 	return 0;
+ + }
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/mux33xx.h linux-3.2.1/arch/arm/mach-ckb_3352/mux33xx.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/mux33xx.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/mux33xx.h	2014-11-25 13:19:15.012844683 +0900
+ ***************
+ *** 0 ****
+ --- 1,257 ----
+ + /*
+ +  * AM33XX pad control register macros.
+ +  *
+ +  * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #ifndef __ARCH_ARM_MACH_OMAP2_MUX335X_H
+ + #define __ARCH_ARM_MACH_OMAP2_MUX335X_H
+ + 
+ + #define AM33XX_CONTROL_PADCONF_MUX_PBASE			0x44E10000LU
+ + 
+ + /* If pin is not defined as input, pull would get disabled.
+ +  * If defined as input, flags supplied will determine pull on/off.
+ +  */
+ + #define AM33XX_MUX(mode0, mux_value)					\
+ + {									\
+ + 	.reg_offset	= (AM33XX_CONTROL_PADCONF_##mode0##_OFFSET),	\
+ + 	.value		= (((mux_value) & AM33XX_INPUT_EN) ? (mux_value)\
+ + 				: ((mux_value) | AM33XX_PULL_DISA)),	\
+ + }
+ + 
+ + /*
+ +  * AM33XX CONTROL_PADCONF* register offsets for pin-muxing
+ +  *
+ +  * Add AM33XX_CONTROL_PADCONF_MUX_PBASE to these values to get the
+ +  * absolute addresses. The macro names below are mode-0 names of
+ +  * corresponding pins.
+ +  */
+ + 
+ + #define AM33XX_CONTROL_PADCONF_GPMC_AD0_OFFSET			0x0800
+ + #define AM33XX_CONTROL_PADCONF_GPMC_AD1_OFFSET			0x0804
+ + #define AM33XX_CONTROL_PADCONF_GPMC_AD2_OFFSET			0x0808
+ + #define AM33XX_CONTROL_PADCONF_GPMC_AD3_OFFSET			0x080C
+ + #define AM33XX_CONTROL_PADCONF_GPMC_AD4_OFFSET			0x0810
+ + #define AM33XX_CONTROL_PADCONF_GPMC_AD5_OFFSET			0x0814
+ + #define AM33XX_CONTROL_PADCONF_GPMC_AD6_OFFSET			0x0818
+ + #define AM33XX_CONTROL_PADCONF_GPMC_AD7_OFFSET			0x081C
+ + #define AM33XX_CONTROL_PADCONF_GPMC_AD8_OFFSET			0x0820
+ + #define AM33XX_CONTROL_PADCONF_GPMC_AD9_OFFSET			0x0824
+ + #define AM33XX_CONTROL_PADCONF_GPMC_AD10_OFFSET			0x0828
+ + #define AM33XX_CONTROL_PADCONF_GPMC_AD11_OFFSET			0x082C
+ + #define AM33XX_CONTROL_PADCONF_GPMC_AD12_OFFSET			0x0830
+ + #define AM33XX_CONTROL_PADCONF_GPMC_AD13_OFFSET			0x0834
+ + #define AM33XX_CONTROL_PADCONF_GPMC_AD14_OFFSET			0x0838
+ + #define AM33XX_CONTROL_PADCONF_GPMC_AD15_OFFSET			0x083C
+ + #define AM33XX_CONTROL_PADCONF_GPMC_A0_OFFSET			0x0840
+ + #define AM33XX_CONTROL_PADCONF_GPMC_A1_OFFSET			0x0844
+ + #define AM33XX_CONTROL_PADCONF_GPMC_A2_OFFSET			0x0848
+ + #define AM33XX_CONTROL_PADCONF_GPMC_A3_OFFSET			0x084C
+ + #define AM33XX_CONTROL_PADCONF_GPMC_A4_OFFSET			0x0850
+ + #define AM33XX_CONTROL_PADCONF_GPMC_A5_OFFSET			0x0854
+ + #define AM33XX_CONTROL_PADCONF_GPMC_A6_OFFSET			0x0858
+ + #define AM33XX_CONTROL_PADCONF_GPMC_A7_OFFSET			0x085C
+ + #define AM33XX_CONTROL_PADCONF_GPMC_A8_OFFSET			0x0860
+ + #define AM33XX_CONTROL_PADCONF_GPMC_A9_OFFSET			0x0864
+ + #define AM33XX_CONTROL_PADCONF_GPMC_A10_OFFSET			0x0868
+ + #define AM33XX_CONTROL_PADCONF_GPMC_A11_OFFSET			0x086C
+ + #define AM33XX_CONTROL_PADCONF_GPMC_WAIT0_OFFSET		0x0870
+ + #define AM33XX_CONTROL_PADCONF_GPMC_WPN_OFFSET			0x0874
+ + #define AM33XX_CONTROL_PADCONF_GPMC_BEN1_OFFSET			0x0878
+ + #define AM33XX_CONTROL_PADCONF_GPMC_CSN0_OFFSET			0x087C
+ + #define AM33XX_CONTROL_PADCONF_GPMC_CSN1_OFFSET			0x0880
+ + #define AM33XX_CONTROL_PADCONF_GPMC_CSN2_OFFSET			0x0884
+ + #define AM33XX_CONTROL_PADCONF_GPMC_CSN3_OFFSET			0x0888
+ + #define AM33XX_CONTROL_PADCONF_GPMC_CLK_OFFSET			0x088C
+ + #define AM33XX_CONTROL_PADCONF_GPMC_ADVN_ALE_OFFSET		0x0890
+ + #define AM33XX_CONTROL_PADCONF_GPMC_OEN_REN_OFFSET		0x0894
+ + #define AM33XX_CONTROL_PADCONF_GPMC_WEN_OFFSET			0x0898
+ + #define AM33XX_CONTROL_PADCONF_GPMC_BEN0_CLE_OFFSET		0x089C
+ + #define AM33XX_CONTROL_PADCONF_LCD_DATA0_OFFSET			0x08A0
+ + #define AM33XX_CONTROL_PADCONF_LCD_DATA1_OFFSET			0x08A4
+ + #define AM33XX_CONTROL_PADCONF_LCD_DATA2_OFFSET			0x08A8
+ + #define AM33XX_CONTROL_PADCONF_LCD_DATA3_OFFSET			0x08AC
+ + #define AM33XX_CONTROL_PADCONF_LCD_DATA4_OFFSET			0x08B0
+ + #define AM33XX_CONTROL_PADCONF_LCD_DATA5_OFFSET			0x08B4
+ + #define AM33XX_CONTROL_PADCONF_LCD_DATA6_OFFSET			0x08B8
+ + #define AM33XX_CONTROL_PADCONF_LCD_DATA7_OFFSET			0x08BC
+ + #define AM33XX_CONTROL_PADCONF_LCD_DATA8_OFFSET			0x08C0
+ + #define AM33XX_CONTROL_PADCONF_LCD_DATA9_OFFSET			0x08C4
+ + #define AM33XX_CONTROL_PADCONF_LCD_DATA10_OFFSET		0x08C8
+ + #define AM33XX_CONTROL_PADCONF_LCD_DATA11_OFFSET		0x08CC
+ + #define AM33XX_CONTROL_PADCONF_LCD_DATA12_OFFSET		0x08D0
+ + #define AM33XX_CONTROL_PADCONF_LCD_DATA13_OFFSET		0x08D4
+ + #define AM33XX_CONTROL_PADCONF_LCD_DATA14_OFFSET		0x08D8
+ + #define AM33XX_CONTROL_PADCONF_LCD_DATA15_OFFSET		0x08DC
+ + #define AM33XX_CONTROL_PADCONF_LCD_VSYNC_OFFSET			0x08E0
+ + #define AM33XX_CONTROL_PADCONF_LCD_HSYNC_OFFSET			0x08E4
+ + #define AM33XX_CONTROL_PADCONF_LCD_PCLK_OFFSET			0x08E8
+ + #define AM33XX_CONTROL_PADCONF_LCD_AC_BIAS_EN_OFFSET		0x08EC
+ + #define AM33XX_CONTROL_PADCONF_MMC0_DAT3_OFFSET			0x08F0
+ + #define AM33XX_CONTROL_PADCONF_MMC0_DAT2_OFFSET			0x08F4
+ + #define AM33XX_CONTROL_PADCONF_MMC0_DAT1_OFFSET			0x08F8
+ + #define AM33XX_CONTROL_PADCONF_MMC0_DAT0_OFFSET			0x08FC
+ + #define AM33XX_CONTROL_PADCONF_MMC0_CLK_OFFSET			0x0900
+ + #define AM33XX_CONTROL_PADCONF_MMC0_CMD_OFFSET			0x0904
+ + #define AM33XX_CONTROL_PADCONF_MII1_COL_OFFSET			0x0908
+ + #define AM33XX_CONTROL_PADCONF_MII1_CRS_OFFSET			0x090C
+ + #define AM33XX_CONTROL_PADCONF_MII1_RXERR_OFFSET		0x0910
+ + #define AM33XX_CONTROL_PADCONF_MII1_TXEN_OFFSET			0x0914
+ + #define AM33XX_CONTROL_PADCONF_MII1_RXDV_OFFSET			0x0918
+ + #define AM33XX_CONTROL_PADCONF_MII1_TXD3_OFFSET			0x091C
+ + #define AM33XX_CONTROL_PADCONF_MII1_TXD2_OFFSET			0x0920
+ + #define AM33XX_CONTROL_PADCONF_MII1_TXD1_OFFSET			0x0924
+ + #define AM33XX_CONTROL_PADCONF_MII1_TXD0_OFFSET			0x0928
+ + #define AM33XX_CONTROL_PADCONF_MII1_TXCLK_OFFSET		0x092C
+ + #define AM33XX_CONTROL_PADCONF_MII1_RXCLK_OFFSET		0x0930
+ + #define AM33XX_CONTROL_PADCONF_MII1_RXD3_OFFSET			0x0934
+ + #define AM33XX_CONTROL_PADCONF_MII1_RXD2_OFFSET			0x0938
+ + #define AM33XX_CONTROL_PADCONF_MII1_RXD1_OFFSET			0x093C
+ + #define AM33XX_CONTROL_PADCONF_MII1_RXD0_OFFSET			0x0940
+ + #define AM33XX_CONTROL_PADCONF_MII1_REFCLK_OFFSET		0x0944
+ + #define AM33XX_CONTROL_PADCONF_MDIO_DATA_OFFSET			0x0948
+ + #define AM33XX_CONTROL_PADCONF_MDIO_CLK_OFFSET			0x094C
+ + #define AM33XX_CONTROL_PADCONF_SPI0_SCLK_OFFSET			0x0950
+ + #define AM33XX_CONTROL_PADCONF_SPI0_D0_OFFSET			0x0954
+ + #define AM33XX_CONTROL_PADCONF_SPI0_D1_OFFSET			0x0958
+ + #define AM33XX_CONTROL_PADCONF_SPI0_CS0_OFFSET			0x095C
+ + #define AM33XX_CONTROL_PADCONF_SPI0_CS1_OFFSET			0x0960
+ + #define AM33XX_CONTROL_PADCONF_ECAP0_IN_PWM0_OUT_OFFSET		0x0964
+ + #define AM33XX_CONTROL_PADCONF_UART0_CTSN_OFFSET		0x0968
+ + #define AM33XX_CONTROL_PADCONF_UART0_RTSN_OFFSET		0x096C
+ + #define AM33XX_CONTROL_PADCONF_UART0_RXD_OFFSET			0x0970
+ + #define AM33XX_CONTROL_PADCONF_UART0_TXD_OFFSET			0x0974
+ + #define AM33XX_CONTROL_PADCONF_UART1_CTSN_OFFSET		0x0978
+ + #define AM33XX_CONTROL_PADCONF_UART1_RTSN_OFFSET		0x097C
+ + #define AM33XX_CONTROL_PADCONF_UART1_RXD_OFFSET			0x0980
+ + #define AM33XX_CONTROL_PADCONF_UART1_TXD_OFFSET			0x0984
+ + #define AM33XX_CONTROL_PADCONF_I2C0_SDA_OFFSET			0x0988
+ + #define AM33XX_CONTROL_PADCONF_I2C0_SCL_OFFSET			0x098C
+ + #define AM33XX_CONTROL_PADCONF_MCASP0_ACLKX_OFFSET		0x0990
+ + #define AM33XX_CONTROL_PADCONF_MCASP0_FSX_OFFSET		0x0994
+ + #define AM33XX_CONTROL_PADCONF_MCASP0_AXR0_OFFSET		0x0998
+ + #define AM33XX_CONTROL_PADCONF_MCASP0_AHCLKR_OFFSET		0x099C
+ + #define AM33XX_CONTROL_PADCONF_MCASP0_ACLKR_OFFSET		0x09A0
+ + #define AM33XX_CONTROL_PADCONF_MCASP0_FSR_OFFSET		0x09A4
+ + #define AM33XX_CONTROL_PADCONF_MCASP0_AXR1_OFFSET		0x09A8
+ + #define AM33XX_CONTROL_PADCONF_MCASP0_AHCLKX_OFFSET		0x09AC
+ + #define AM33XX_CONTROL_PADCONF_XDMA_EVENT_INTR0_OFFSET		0x09B0
+ + #define AM33XX_CONTROL_PADCONF_XDMA_EVENT_INTR1_OFFSET		0x09B4
+ + #define AM33XX_CONTROL_PADCONF_WARMRSTN_OFFSET			0x09B8
+ + #define AM33XX_CONTROL_PADCONF_PWRONRSTN_OFFSET			0x09BC
+ + #define AM33XX_CONTROL_PADCONF_NMIN_OFFSET			0x09C0
+ + #define AM33XX_CONTROL_PADCONF_XTALIN_OFFSET			0x09C4
+ + #define AM33XX_CONTROL_PADCONF_XTALOUT_OFFSET			0x09C8
+ + #define AM33XX_CONTROL_PADCONF_TMS_OFFSET			0x09D0
+ + #define AM33XX_CONTROL_PADCONF_TDI_OFFSET			0x09D4
+ + #define AM33XX_CONTROL_PADCONF_TDO_OFFSET			0x09D8
+ + #define AM33XX_CONTROL_PADCONF_TCK_OFFSET			0x09DC
+ + #define AM33XX_CONTROL_PADCONF_TRSTN_OFFSET			0x09E0
+ + #define AM33XX_CONTROL_PADCONF_EMU0_OFFSET			0x09E4
+ + #define AM33XX_CONTROL_PADCONF_EMU1_OFFSET			0x09E8
+ + #define AM33XX_CONTROL_PADCONF_RTC_XTALIN_OFFSET		0x09EC
+ + #define AM33XX_CONTROL_PADCONF_RTC_XTALOUT_OFFSET		0x09F0
+ + #define AM33XX_CONTROL_PADCONF_RTC_PWRONRSTN_OFFSET		0x09F8
+ + #define AM33XX_CONTROL_PADCONF_EXT_WAKEUP_OFFSET		0x0A00
+ + #define AM33XX_CONTROL_PADCONF_PMIC_POWER_EN_OFFSET		0x09F4
+ + #define AM33XX_CONTROL_PADCONF_RTC_KALDO_ENN_OFFSET		0x0A04
+ + #define AM33XX_CONTROL_PADCONF_USB0_DM_OFFSET			0x0A08
+ + #define AM33XX_CONTROL_PADCONF_USB0_DP_OFFSET		        0x0A0C
+ + #define AM33XX_CONTROL_PADCONF_USB0_CE_OFFSET		        0x0A10
+ + #define AM33XX_CONTROL_PADCONF_USB0_ID_OFFSET		        0x0A14
+ + #define AM33XX_CONTROL_PADCONF_USB0_VBUS_OFFSET			0x0A18
+ + #define AM33XX_CONTROL_PADCONF_USB0_DRVVBUS_OFFSET		0x0A1C
+ + #define AM33XX_CONTROL_PADCONF_USB1_DM_OFFSET			0x0A20
+ + #define AM33XX_CONTROL_PADCONF_USB1_DP_OFFSET		        0x0A24
+ + #define AM33XX_CONTROL_PADCONF_USB1_CE_OFFSET		        0x0A28
+ + #define AM33XX_CONTROL_PADCONF_USB1_ID_OFFSET		        0x0A2C
+ + #define AM33XX_CONTROL_PADCONF_USB1_VBUS_OFFSET			0x0A30
+ + #define AM33XX_CONTROL_PADCONF_USB1_DRVVBUS_OFFSET		0x0A34
+ + #define AM33XX_CONTROL_PADCONF_DDR_RESETN_OFFSET		0x0A38
+ + #define AM33XX_CONTROL_PADCONF_DDR_CSN0_OFFSET			0x0A3C
+ + #define AM33XX_CONTROL_PADCONF_DDR_CKE_OFFSET			0x0A40
+ + #define AM33XX_CONTROL_PADCONF_DDR_CK_OFFSET			0x0A44
+ + #define AM33XX_CONTROL_PADCONF_DDR_CKN_OFFSET			0x0A48
+ + #define AM33XX_CONTROL_PADCONF_DDR_CASN_OFFSET			0x0A4C
+ + #define AM33XX_CONTROL_PADCONF_DDR_RASN_OFFSET			0x0A50
+ + #define AM33XX_CONTROL_PADCONF_DDR_WEN_OFFSET			0x0A54
+ + #define AM33XX_CONTROL_PADCONF_DDR_BA0_OFFSET			0x0A58
+ + #define AM33XX_CONTROL_PADCONF_DDR_BA1_OFFSET			0x0A5C
+ + #define AM33XX_CONTROL_PADCONF_DDR_BA2_OFFSET			0x0A60
+ + #define AM33XX_CONTROL_PADCONF_DDR_A0_OFFSET			0x0A64
+ + #define AM33XX_CONTROL_PADCONF_DDR_A1_OFFSET			0x0A68
+ + #define AM33XX_CONTROL_PADCONF_DDR_A2_OFFSET			0x0A6C
+ + #define AM33XX_CONTROL_PADCONF_DDR_A3_OFFSET			0x0A70
+ + #define AM33XX_CONTROL_PADCONF_DDR_A4_OFFSET			0x0A74
+ + #define AM33XX_CONTROL_PADCONF_DDR_A5_OFFSET			0x0A78
+ + #define AM33XX_CONTROL_PADCONF_DDR_A6_OFFSET			0x0A7C
+ + #define AM33XX_CONTROL_PADCONF_DDR_A7_OFFSET			0x0A80
+ + #define AM33XX_CONTROL_PADCONF_DDR_A8_OFFSET			0x0A84
+ + #define AM33XX_CONTROL_PADCONF_DDR_A9_OFFSET			0x0A88
+ + #define AM33XX_CONTROL_PADCONF_DDR_A10_OFFSET			0x0A8C
+ + #define AM33XX_CONTROL_PADCONF_DDR_A11_OFFSET			0x0A90
+ + #define AM33XX_CONTROL_PADCONF_DDR_A12_OFFSET			0x0A94
+ + #define AM33XX_CONTROL_PADCONF_DDR_A13_OFFSET			0x0A98
+ + #define AM33XX_CONTROL_PADCONF_DDR_A14_OFFSET			0x0A9C
+ + #define AM33XX_CONTROL_PADCONF_DDR_A15_OFFSET			0x0AA0
+ + #define AM33XX_CONTROL_PADCONF_DDR_ODT_OFFSET			0x0AA4
+ + #define AM33XX_CONTROL_PADCONF_DDR_D0_OFFSET			0x0AA8
+ + #define AM33XX_CONTROL_PADCONF_DDR_D1_OFFSET			0x0AAC
+ + #define AM33XX_CONTROL_PADCONF_DDR_D2_OFFSET			0x0AB0
+ + #define AM33XX_CONTROL_PADCONF_DDR_D3_OFFSET			0x0AB4
+ + #define AM33XX_CONTROL_PADCONF_DDR_D4_OFFSET			0x0AB8
+ + #define AM33XX_CONTROL_PADCONF_DDR_D5_OFFSET			0x0ABC
+ + #define AM33XX_CONTROL_PADCONF_DDR_D6_OFFSET			0x0AC0
+ + #define AM33XX_CONTROL_PADCONF_DDR_D7_OFFSET			0x0AC4
+ + #define AM33XX_CONTROL_PADCONF_DDR_D8_OFFSET			0x0AC8
+ + #define AM33XX_CONTROL_PADCONF_DDR_D9_OFFSET			0x0ACC
+ + #define AM33XX_CONTROL_PADCONF_DDR_D10_OFFSET			0x0AD0
+ + #define AM33XX_CONTROL_PADCONF_DDR_D11_OFFSET			0x0AD4
+ + #define AM33XX_CONTROL_PADCONF_DDR_D12_OFFSET			0x0AD8
+ + #define AM33XX_CONTROL_PADCONF_DDR_D13_OFFSET			0x0ADC
+ + #define AM33XX_CONTROL_PADCONF_DDR_D14_OFFSET			0x0AE0
+ + #define AM33XX_CONTROL_PADCONF_DDR_D15_OFFSET			0x0AE4
+ + #define AM33XX_CONTROL_PADCONF_DDR_DQM0_OFFSET			0x0AE8
+ + #define AM33XX_CONTROL_PADCONF_DDR_DQM1_OFFSET			0x0AEC
+ + #define AM33XX_CONTROL_PADCONF_DDR_DQS0_OFFSET			0x0AF0
+ + #define AM33XX_CONTROL_PADCONF_DDR_DQSN0_OFFSET			0x0AF4
+ + #define AM33XX_CONTROL_PADCONF_DDR_DQS1_OFFSET			0x0AF8
+ + #define AM33XX_CONTROL_PADCONF_DDR_DQSN1_OFFSET			0x0AFC
+ + #define AM33XX_CONTROL_PADCONF_DDR_VREF_OFFSET			0x0B00
+ + #define AM33XX_CONTROL_PADCONF_DDR_VTP_OFFSET			0x0B04
+ + #define AM33XX_CONTROL_PADCONF_AIN3_OFFSET			0x0B20
+ + #define AM33XX_CONTROL_PADCONF_AIN2_OFFSET			0x0B24
+ + #define AM33XX_CONTROL_PADCONF_AIN1_OFFSET			0x0B28
+ + #define AM33XX_CONTROL_PADCONF_AIN0_OFFSET			0x0B2C
+ + #define AM33XX_CONTROL_PADCONF_VREFP_OFFSET			0x0B30
+ + #define AM33XX_CONTROL_PADCONF_VREFN_OFFSET			0x0B34
+ + 
+ + #define AM33XX_CONTROL_PADCONF_MUX_SIZE				\
+ + 		(AM33XX_CONTROL_PADCONF_VREFN_OFFSET + 0x4)
+ + 
+ + #define MAX_IO_PADCONF	((AM33XX_CONTROL_PADCONF_MUX_SIZE -	\
+ + 				AM33XX_CONTROL_PADCONF_GPMC_AD0_OFFSET) / 4)
+ + 
+ + #ifndef __ASSEMBLER__
+ + void am335x_save_padconf(void);
+ + void am335x_restore_padconf(void);
+ + 
+ + struct dentry;
+ + void am33xx_mux_dbg_create_entry(struct dentry *mux_dbg_dir);
+ + void am33xx_setup_pinmux_on_suspend(void);
+ + 
+ + void am33xx_standby_setup(unsigned int state);
+ + void am33xx_standby_release(unsigned int state);
+ + 
+ + #endif
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/mux.c linux-3.2.1/arch/arm/mach-ckb_3352/mux.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/mux.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/mux.c	2014-11-25 13:19:15.016985425 +0900
+ ***************
+ *** 0 ****
+ --- 1,1208 ----
+ + /*
+ +  * linux/arch/arm/mach-omap2/mux.c
+ +  *
+ +  * OMAP2, OMAP3 and OMAP4 pin multiplexing configurations
+ +  *
+ +  * Copyright (C) 2004 - 2010 Texas Instruments Inc.
+ +  * Copyright (C) 2003 - 2008 Nokia Corporation
+ +  *
+ +  * Written by Tony Lindgren
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; either version 2 of the License, or
+ +  * (at your option) any later version.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ +  *
+ +  */
+ + #include <linux/kernel.h>
+ + #include <linux/init.h>
+ + #include <linux/io.h>
+ + #include <linux/list.h>
+ + #include <linux/slab.h>
+ + #include <linux/ctype.h>
+ + #include <linux/debugfs.h>
+ + #include <linux/seq_file.h>
+ + #include <linux/uaccess.h>
+ + #include <linux/irq.h>
+ + #include <linux/interrupt.h>
+ + 
+ + #include <asm/system.h>
+ + 
+ + #include <plat/omap_hwmod.h>
+ + 
+ + #include "control.h"
+ + #include "mux.h"
+ + #include "prm.h"
+ + 
+ + #define OMAP_MUX_BASE_OFFSET		0x30	/* Offset from CTRL_BASE */
+ + #define OMAP_MUX_BASE_SZ		0x5ca
+ + 
+ + struct omap_mux_entry {
+ + 	struct omap_mux		mux;
+ + 	struct list_head	node;
+ + };
+ + 
+ + static LIST_HEAD(mux_partitions);
+ + static DEFINE_MUTEX(muxmode_mutex);
+ + 
+ + struct omap_mux_partition *omap_mux_get(const char *name)
+ + {
+ + 	struct omap_mux_partition *partition;
+ + 
+ + 	list_for_each_entry(partition, &mux_partitions, node) {
+ + 		if (!strcmp(name, partition->name))
+ + 			return partition;
+ + 	}
+ + 
+ + 	return NULL;
+ + }
+ + 
+ + u16 omap_mux_read(struct omap_mux_partition *partition, u16 reg)
+ + {
+ + 	if (partition->flags & OMAP_MUX_REG_8BIT)
+ + 		return __raw_readb(partition->base + reg);
+ + 	else
+ + 		return __raw_readw(partition->base + reg);
+ + }
+ + 
+ + void omap_mux_write(struct omap_mux_partition *partition, u16 val,
+ + 			   u16 reg)
+ + {
+ + 	if (partition->flags & OMAP_MUX_REG_8BIT)
+ + 		__raw_writeb(val, partition->base + reg);
+ + 	else
+ + 		__raw_writew(val, partition->base + reg);
+ + }
+ + 
+ + void omap_mux_write_array(struct omap_mux_partition *partition,
+ + 				 struct omap_board_mux *board_mux)
+ + {
+ + 	if (!board_mux)
+ + 		return;
+ + 
+ + 	while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) {
+ + 		omap_mux_write(partition, board_mux->value,
+ + 			       board_mux->reg_offset);
+ + 		board_mux++;
+ + 	}
+ + }
+ + 
+ + #ifdef CONFIG_OMAP_MUX
+ + 
+ + static char *omap_mux_options;
+ + 
+ + static int _omap_mux_init_gpio(struct omap_mux_partition *partition,
+ + 				      int gpio, int val)
+ + {
+ + 	struct omap_mux_entry *e;
+ + 	struct omap_mux *gpio_mux = NULL;
+ + 	u16 old_mode;
+ + 	u16 mux_mode;
+ + 	int found = 0;
+ + 	struct list_head *muxmodes = &partition->muxmodes;
+ + 
+ + 	if (!gpio)
+ + 		return -EINVAL;
+ + 
+ + 	list_for_each_entry(e, muxmodes, node) {
+ + 		struct omap_mux *m = &e->mux;
+ + 		if (gpio == m->gpio) {
+ + 			gpio_mux = m;
+ + 			found++;
+ + 		}
+ + 	}
+ + 
+ + 	if (found == 0) {
+ + 		pr_err("%s: Could not set gpio%i\n", __func__, gpio);
+ + 		return -ENODEV;
+ + 	}
+ + 
+ + 	if (found > 1) {
+ + 		pr_info("%s: Multiple gpio paths (%d) for gpio%i\n", __func__,
+ + 			found, gpio);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	old_mode = omap_mux_read(partition, gpio_mux->reg_offset);
+ + 	mux_mode = val & ~(OMAP_MUX_NR_MODES - 1);
+ + 	if (partition->flags & OMAP_MUX_GPIO_IN_MODE3)
+ + 		mux_mode |= OMAP_MUX_MODE3;
+ + 	else
+ + 		mux_mode |= OMAP_MUX_MODE4;
+ + 	pr_debug("%s: Setting signal %s.gpio%i 0x%04x -> 0x%04x\n", __func__,
+ + 		 gpio_mux->muxnames[0], gpio, old_mode, mux_mode);
+ + 	omap_mux_write(partition, mux_mode, gpio_mux->reg_offset);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + int omap_mux_init_gpio(int gpio, int val)
+ + {
+ + 	struct omap_mux_partition *partition;
+ + 	int ret;
+ + 
+ + 	list_for_each_entry(partition, &mux_partitions, node) {
+ + 		ret = _omap_mux_init_gpio(partition, gpio, val);
+ + 		if (!ret)
+ + 			return ret;
+ + 	}
+ + 
+ + 	return -ENODEV;
+ + }
+ + 
+ + static int _omap_mux_get_by_name(struct omap_mux_partition *partition,
+ + 					const char *muxname,
+ + 					struct omap_mux **found_mux)
+ + {
+ + 	struct omap_mux *mux = NULL;
+ + 	struct omap_mux_entry *e;
+ + 	const char *mode_name;
+ + 	int found = 0, found_mode = 0, mode0_len = 0;
+ + 	struct list_head *muxmodes = &partition->muxmodes;
+ + 
+ + 	mode_name = strchr(muxname, '.');
+ + 	if (mode_name) {
+ + 		mode0_len = strlen(muxname) - strlen(mode_name);
+ + 		mode_name++;
+ + 	} else {
+ + 		mode_name = muxname;
+ + 	}
+ + 
+ + 	list_for_each_entry(e, muxmodes, node) {
+ + 		char *m0_entry;
+ + 		int i;
+ + 
+ + 		mux = &e->mux;
+ + 		m0_entry = mux->muxnames[0];
+ + 
+ + 		/* First check for full name in mode0.muxmode format */
+ + 		if (mode0_len && strncmp(muxname, m0_entry, mode0_len))
+ + 			continue;
+ + 
+ + 		/* Then check for muxmode only */
+ + 		for (i = 0; i < OMAP_MUX_NR_MODES; i++) {
+ + 			char *mode_cur = mux->muxnames[i];
+ + 
+ + 			if (!mode_cur)
+ + 				continue;
+ + 
+ + 			if (!strcmp(mode_name, mode_cur)) {
+ + 				*found_mux = mux;
+ + 				found++;
+ + 				found_mode = i;
+ + 			}
+ + 		}
+ + 	}
+ + 
+ + 	if (found == 1) {
+ + 		return found_mode;
+ + 	}
+ + 
+ + 	if (found > 1) {
+ + 		pr_err("%s: Multiple signal paths (%i) for %s\n", __func__,
+ + 		       found, muxname);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	pr_err("%s: Could not find signal %s\n", __func__, muxname);
+ + 
+ + 	return -ENODEV;
+ + }
+ + 
+ + int omap_mux_get_by_name(const char *muxname,
+ + 			struct omap_mux_partition **found_partition,
+ + 			struct omap_mux **found_mux)
+ + {
+ + 	struct omap_mux_partition *partition;
+ + 
+ + 	list_for_each_entry(partition, &mux_partitions, node) {
+ + 		struct omap_mux *mux = NULL;
+ + 		int mux_mode = _omap_mux_get_by_name(partition, muxname, &mux);
+ + 		if (mux_mode < 0)
+ + 			continue;
+ + 
+ + 		*found_partition = partition;
+ + 		*found_mux = mux;
+ + 
+ + 		return mux_mode;
+ + 	}
+ + 
+ + 	return -ENODEV;
+ + }
+ + 
+ + int omap_mux_init_signal(const char *muxname, int val)
+ + {
+ + 	struct omap_mux_partition *partition = NULL;
+ + 	struct omap_mux *mux = NULL;
+ + 	u16 old_mode;
+ + 	int mux_mode;
+ + 
+ + 	mux_mode = omap_mux_get_by_name(muxname, &partition, &mux);
+ + 	if (mux_mode < 0)
+ + 		return mux_mode;
+ + 
+ + 	old_mode = omap_mux_read(partition, mux->reg_offset);
+ + 	mux_mode |= val;
+ + 	pr_debug("%s: Setting signal %s 0x%04x -> 0x%04x\n",
+ + 			 __func__, muxname, old_mode, mux_mode);
+ + 	omap_mux_write(partition, mux_mode, mux->reg_offset);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + struct omap_hwmod_mux_info *
+ + omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads)
+ + {
+ + 	struct omap_hwmod_mux_info *hmux;
+ + 	int i, nr_pads_dynamic = 0;
+ + 
+ + 	if (!bpads || nr_pads < 1)
+ + 		return NULL;
+ + 
+ + 	hmux = kzalloc(sizeof(struct omap_hwmod_mux_info), GFP_KERNEL);
+ + 	if (!hmux)
+ + 		goto err1;
+ + 
+ + 	hmux->nr_pads = nr_pads;
+ + 
+ + 	hmux->pads = kzalloc(sizeof(struct omap_device_pad) *
+ + 				nr_pads, GFP_KERNEL);
+ + 	if (!hmux->pads)
+ + 		goto err2;
+ + 
+ + 	for (i = 0; i < hmux->nr_pads; i++) {
+ + 		struct omap_mux_partition *partition;
+ + 		struct omap_device_pad *bpad = &bpads[i], *pad = &hmux->pads[i];
+ + 		struct omap_mux *mux;
+ + 		int mux_mode;
+ + 
+ + 		mux_mode = omap_mux_get_by_name(bpad->name, &partition, &mux);
+ + 		if (mux_mode < 0)
+ + 			goto err3;
+ + 		if (!pad->partition)
+ + 			pad->partition = partition;
+ + 		if (!pad->mux)
+ + 			pad->mux = mux;
+ + 
+ + 		pad->name = kzalloc(strlen(bpad->name) + 1, GFP_KERNEL);
+ + 		if (!pad->name) {
+ + 			int j;
+ + 
+ + 			for (j = i - 1; j >= 0; j--)
+ + 				kfree(hmux->pads[j].name);
+ + 			goto err3;
+ + 		}
+ + 		strcpy(pad->name, bpad->name);
+ + 
+ + 		pad->flags = bpad->flags;
+ + 		pad->enable = bpad->enable;
+ + 		pad->idle = bpad->idle;
+ + 		pad->off = bpad->off;
+ + 
+ + 		if (pad->flags &
+ + 		    (OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP))
+ + 			nr_pads_dynamic++;
+ + 
+ + 		pr_debug("%s: Initialized %s\n", __func__, pad->name);
+ + 	}
+ + 
+ + 	if (!nr_pads_dynamic)
+ + 		return hmux;
+ + 
+ + 	/*
+ + 	 * Add pads that need dynamic muxing into a separate list
+ + 	 */
+ + 
+ + 	hmux->nr_pads_dynamic = nr_pads_dynamic;
+ + 	hmux->pads_dynamic = kzalloc(sizeof(struct omap_device_pad *) *
+ + 					nr_pads_dynamic, GFP_KERNEL);
+ + 	if (!hmux->pads_dynamic) {
+ + 		pr_err("%s: Could not allocate dynamic pads\n", __func__);
+ + 		return hmux;
+ + 	}
+ + 
+ + 	nr_pads_dynamic = 0;
+ + 	for (i = 0; i < hmux->nr_pads; i++) {
+ + 		struct omap_device_pad *pad = &hmux->pads[i];
+ + 
+ + 		if (pad->flags &
+ + 		    (OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP)) {
+ + 			pr_debug("%s: pad %s tagged dynamic\n",
+ + 					__func__, pad->name);
+ + 			hmux->pads_dynamic[nr_pads_dynamic] = pad;
+ + 			nr_pads_dynamic++;
+ + 		}
+ + 	}
+ + 
+ + 	return hmux;
+ + 
+ + err3:
+ + 	kfree(hmux->pads);
+ + err2:
+ + 	kfree(hmux);
+ + err1:
+ + 	pr_err("%s: Could not allocate device mux entry\n", __func__);
+ + 
+ + 	return NULL;
+ + }
+ + 
+ + /**
+ +  * omap_hwmod_mux_scan_wakeups - omap hwmod scan wakeup pads
+ +  * @hmux: Pads for a hwmod
+ +  * @mpu_irqs: MPU irq array for a hwmod
+ +  *
+ +  * Scans the wakeup status of pads for a single hwmod.  If an irq
+ +  * array is defined for this mux, the parser will call the registered
+ +  * ISRs for corresponding pads, otherwise the parser will stop at the
+ +  * first wakeup active pad and return.  Returns true if there is a
+ +  * pending and non-served wakeup event for the mux, otherwise false.
+ +  */
+ + static bool omap_hwmod_mux_scan_wakeups(struct omap_hwmod_mux_info *hmux,
+ + 		struct omap_hwmod_irq_info *mpu_irqs)
+ + {
+ + 	int i, irq;
+ + 	unsigned int val;
+ + 	u32 handled_irqs = 0;
+ + 
+ + 	for (i = 0; i < hmux->nr_pads_dynamic; i++) {
+ + 		struct omap_device_pad *pad = hmux->pads_dynamic[i];
+ + 
+ + 		if (!(pad->flags & OMAP_DEVICE_PAD_WAKEUP) ||
+ + 		    !(pad->idle & OMAP_WAKEUP_EN))
+ + 			continue;
+ + 
+ + 		val = omap_mux_read(pad->partition, pad->mux->reg_offset);
+ + 		if (!(val & OMAP_WAKEUP_EVENT))
+ + 			continue;
+ + 
+ + 		if (!hmux->irqs)
+ + 			return true;
+ + 
+ + 		irq = hmux->irqs[i];
+ + 		/* make sure we only handle each irq once */
+ + 		if (handled_irqs & 1 << irq)
+ + 			continue;
+ + 
+ + 		handled_irqs |= 1 << irq;
+ + 
+ + 		generic_handle_irq(mpu_irqs[irq].irq);
+ + 	}
+ + 
+ + 	return false;
+ + }
+ + 
+ + /**
+ +  * _omap_hwmod_mux_handle_irq - Process wakeup events for a single hwmod
+ +  *
+ +  * Checks a single hwmod for every wakeup capable pad to see if there is an
+ +  * active wakeup event. If this is the case, call the corresponding ISR.
+ +  */
+ + static int _omap_hwmod_mux_handle_irq(struct omap_hwmod *oh, void *data)
+ + {
+ + 	if (!oh->mux || !oh->mux->enabled)
+ + 		return 0;
+ + 	if (omap_hwmod_mux_scan_wakeups(oh->mux, oh->mpu_irqs))
+ + 		generic_handle_irq(oh->mpu_irqs[0].irq);
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * omap_hwmod_mux_handle_irq - Process pad wakeup irqs.
+ +  *
+ +  * Calls a function for each registered omap_hwmod to check
+ +  * pad wakeup statuses.
+ +  */
+ + static irqreturn_t omap_hwmod_mux_handle_irq(int irq, void *unused)
+ + {
+ + 	omap_hwmod_for_each(_omap_hwmod_mux_handle_irq, NULL);
+ + 	return IRQ_HANDLED;
+ + }
+ + 
+ + /* Assumes the calling function takes care of locking */
+ + void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
+ + {
+ + 	int i;
+ + 
+ + 	/* Runtime idling of dynamic pads */
+ + 	if (state == _HWMOD_STATE_IDLE && hmux->enabled) {
+ + 		for (i = 0; i < hmux->nr_pads_dynamic; i++) {
+ + 			struct omap_device_pad *pad = hmux->pads_dynamic[i];
+ + 			int val = -EINVAL;
+ + 
+ + 			val = pad->idle;
+ + 			omap_mux_write(pad->partition, val,
+ + 					pad->mux->reg_offset);
+ + 		}
+ + 
+ + 		return;
+ + 	}
+ + 
+ + 	/* Runtime enabling of dynamic pads */
+ + 	if ((state == _HWMOD_STATE_ENABLED) && hmux->pads_dynamic
+ + 					&& hmux->enabled) {
+ + 		for (i = 0; i < hmux->nr_pads_dynamic; i++) {
+ + 			struct omap_device_pad *pad = hmux->pads_dynamic[i];
+ + 			int val = -EINVAL;
+ + 
+ + 			val = pad->enable;
+ + 			omap_mux_write(pad->partition, val,
+ + 					pad->mux->reg_offset);
+ + 		}
+ + 
+ + 		return;
+ + 	}
+ + 
+ + 	/* Enabling or disabling of all pads */
+ + 	for (i = 0; i < hmux->nr_pads; i++) {
+ + 		struct omap_device_pad *pad = &hmux->pads[i];
+ + 		int flags, val = -EINVAL;
+ + 
+ + 		flags = pad->flags;
+ + 
+ + 		switch (state) {
+ + 		case _HWMOD_STATE_ENABLED:
+ + 			val = pad->enable;
+ + 			pr_debug("%s: Enabling %s %x\n", __func__,
+ + 					pad->name, val);
+ + 			break;
+ + 		case _HWMOD_STATE_DISABLED:
+ + 			/* Use safe mode unless OMAP_DEVICE_PAD_REMUX */
+ + 			if (flags & OMAP_DEVICE_PAD_REMUX)
+ + 				val = pad->off;
+ + 			else
+ + 				val = OMAP_MUX_MODE7;
+ + 			pr_debug("%s: Disabling %s %x\n", __func__,
+ + 					pad->name, val);
+ + 			break;
+ + 		default:
+ + 			/* Nothing to be done */
+ + 			break;
+ + 		};
+ + 
+ + 		if (val >= 0) {
+ + 			omap_mux_write(pad->partition, val,
+ + 					pad->mux->reg_offset);
+ + 			pad->flags = flags;
+ + 		}
+ + 	}
+ + 
+ + 	if (state == _HWMOD_STATE_ENABLED)
+ + 		hmux->enabled = true;
+ + 	else
+ + 		hmux->enabled = false;
+ + }
+ + 
+ + #ifdef CONFIG_DEBUG_FS
+ + 
+ + #define OMAP_MUX_MAX_NR_FLAGS	10
+ + #define OMAP_MUX_TEST_FLAG(val, mask)				\
+ + 	if (((val) & (mask)) == (mask)) {			\
+ + 		i++;						\
+ + 		flags[i] =  #mask;				\
+ + 	}
+ + 
+ + /* REVISIT: Add checking for non-optimal mux settings */
+ + static inline void omap_mux_decode(struct seq_file *s, u16 val)
+ + {
+ + 	char *flags[OMAP_MUX_MAX_NR_FLAGS];
+ + 	char mode[sizeof("OMAP_MUX_MODE") + 1];
+ + 	int i = -1;
+ + 
+ + 	sprintf(mode, "OMAP_MUX_MODE%d", val & 0x7);
+ + 	i++;
+ + 	flags[i] = mode;
+ + 
+ + 	OMAP_MUX_TEST_FLAG(val, OMAP_PIN_OFF_WAKEUPENABLE);
+ + 	if (val & OMAP_OFF_EN) {
+ + 		if (!(val & OMAP_OFFOUT_EN)) {
+ + 			if (!(val & OMAP_OFF_PULL_UP)) {
+ + 				OMAP_MUX_TEST_FLAG(val,
+ + 					OMAP_PIN_OFF_INPUT_PULLDOWN);
+ + 			} else {
+ + 				OMAP_MUX_TEST_FLAG(val,
+ + 					OMAP_PIN_OFF_INPUT_PULLUP);
+ + 			}
+ + 		} else {
+ + 			if (!(val & OMAP_OFFOUT_VAL)) {
+ + 				OMAP_MUX_TEST_FLAG(val,
+ + 					OMAP_PIN_OFF_OUTPUT_LOW);
+ + 			} else {
+ + 				OMAP_MUX_TEST_FLAG(val,
+ + 					OMAP_PIN_OFF_OUTPUT_HIGH);
+ + 			}
+ + 		}
+ + 	}
+ + 
+ + 	if (val & OMAP_INPUT_EN) {
+ + 		if (val & OMAP_PULL_ENA) {
+ + 			if (!(val & OMAP_PULL_UP)) {
+ + 				OMAP_MUX_TEST_FLAG(val,
+ + 					OMAP_PIN_INPUT_PULLDOWN);
+ + 			} else {
+ + 				OMAP_MUX_TEST_FLAG(val, OMAP_PIN_INPUT_PULLUP);
+ + 			}
+ + 		} else {
+ + 			OMAP_MUX_TEST_FLAG(val, OMAP_PIN_INPUT);
+ + 		}
+ + 	} else {
+ + 		i++;
+ + 		flags[i] = "OMAP_PIN_OUTPUT";
+ + 	}
+ + 
+ + 	do {
+ + 		seq_printf(s, "%s", flags[i]);
+ + 		if (i > 0)
+ + 			seq_printf(s, " | ");
+ + 	} while (i-- > 0);
+ + }
+ + 
+ + static inline void am33xx_mux_decode(struct seq_file *s, u16 val)
+ + {
+ + 	char *flags[OMAP_MUX_MAX_NR_FLAGS];
+ + 	char mode[sizeof("OMAP_MUX_MODE") + 1];
+ + 	int i , j;
+ + 
+ + 	i = j = 0;
+ + 	sprintf(mode, "OMAP_MUX_MODE%d", val & 0x7);
+ + 	flags[i] = mode;
+ + 
+ + 	if (val & AM33XX_INPUT_EN) {
+ + 		j = 1;
+ + 		if (val & AM33XX_PULL_DISA) {
+ + 			OMAP_MUX_TEST_FLAG(val, AM33XX_PIN_INPUT);
+ + 		} else if (!(val & AM33XX_PULL_UP)) {
+ + 			OMAP_MUX_TEST_FLAG(val, AM33XX_PIN_INPUT_PULLDOWN);
+ + 		} else {
+ + 			OMAP_MUX_TEST_FLAG(val, AM33XX_PIN_INPUT_PULLUP);
+ + 		}
+ + 	}
+ + 	if (val & AM33XX_SLEWCTRL_SLOW) {
+ + 		j = 1;
+ + 		OMAP_MUX_TEST_FLAG(val, AM33XX_SLEWCTRL_SLOW);
+ + 	} else if (!(val & AM33XX_INPUT_EN)) {
+ + 		if (val & AM33XX_PIN_OUTPUT_PULLUP) {
+ + 			j = 1;
+ + 			OMAP_MUX_TEST_FLAG(val, AM33XX_PIN_OUTPUT_PULLUP);
+ + 		} else if (val & AM33XX_PULL_DISA) {
+ + 			j = 1;
+ + 			OMAP_MUX_TEST_FLAG(val, AM33XX_PULL_DISA);
+ + 		}
+ + 	}
+ + 	if (j == 0)
+ + 		OMAP_MUX_TEST_FLAG(val, AM33XX_PIN_OUTPUT);
+ + 
+ + 	for (j = 0; j <= i; j++) {
+ + 		seq_printf(s, "%s", flags[j]);
+ + 		if (j != i)
+ + 			seq_printf(s, " | ");
+ + 	}
+ + }
+ + 
+ + #define OMAP_MUX_DEFNAME_LEN	32
+ + 
+ + static int omap_mux_dbg_board_show(struct seq_file *s, void *unused)
+ + {
+ + 	struct omap_mux_partition *partition = s->private;
+ + 	struct omap_mux_entry *e;
+ + 	u8 omap_gen = omap_rev() >> 28;
+ + 
+ + 	list_for_each_entry(e, &partition->muxmodes, node) {
+ + 		struct omap_mux *m = &e->mux;
+ + 		char m0_def[OMAP_MUX_DEFNAME_LEN];
+ + 		char *m0_name = m->muxnames[0];
+ + 		u16 val;
+ + 		int i, mode;
+ + 
+ + 		if (!m0_name)
+ + 			continue;
+ + 
+ + 		/* REVISIT: Needs to be updated if mode0 names get longer */
+ + 		for (i = 0; i < OMAP_MUX_DEFNAME_LEN; i++) {
+ + 			if (m0_name[i] == '\0') {
+ + 				m0_def[i] = m0_name[i];
+ + 				break;
+ + 			}
+ + 			m0_def[i] = toupper(m0_name[i]);
+ + 		}
+ + 		val = omap_mux_read(partition, m->reg_offset);
+ + 		mode = val & OMAP_MUX_MODE7;
+ + 		if (mode != 0)
+ + 			seq_printf(s, "/* %s */\n", m->muxnames[mode]);
+ + 
+ + 		/*
+ + 		 * XXX: Might be revisited to support differences across
+ + 		 * same OMAP generation.
+ + 		 */
+ + 		seq_printf(s, "OMAP%d_MUX(%s, ", omap_gen, m0_def);
+ + 		if (cpu_is_am335x())
+ + 			am33xx_mux_decode(s, val);
+ + 		else
+ + 			omap_mux_decode(s, val);
+ + 		seq_printf(s, "),\n");
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static int omap_mux_dbg_board_open(struct inode *inode, struct file *file)
+ + {
+ + 	return single_open(file, omap_mux_dbg_board_show, inode->i_private);
+ + }
+ + 
+ + static const struct file_operations omap_mux_dbg_board_fops = {
+ + 	.open		= omap_mux_dbg_board_open,
+ + 	.read		= seq_read,
+ + 	.llseek		= seq_lseek,
+ + 	.release	= single_release,
+ + };
+ + 
+ + static struct omap_mux_partition *omap_mux_get_partition(struct omap_mux *mux)
+ + {
+ + 	struct omap_mux_partition *partition;
+ + 
+ + 	list_for_each_entry(partition, &mux_partitions, node) {
+ + 		struct list_head *muxmodes = &partition->muxmodes;
+ + 		struct omap_mux_entry *e;
+ + 
+ + 		list_for_each_entry(e, muxmodes, node) {
+ + 			struct omap_mux *m = &e->mux;
+ + 
+ + 			if (m == mux)
+ + 				return partition;
+ + 		}
+ + 	}
+ + 
+ + 	return NULL;
+ + }
+ + 
+ + static int omap_mux_dbg_signal_show(struct seq_file *s, void *unused)
+ + {
+ + 	struct omap_mux *m = s->private;
+ + 	struct omap_mux_partition *partition;
+ + 	const char *none = "NA";
+ + 	u16 val;
+ + 	int mode;
+ + 
+ + 	partition = omap_mux_get_partition(m);
+ + 	if (!partition)
+ + 		return 0;
+ + 
+ + 	val = omap_mux_read(partition, m->reg_offset);
+ + 	mode = val & OMAP_MUX_MODE7;
+ + 
+ + 	seq_printf(s, "name: %s.%s (0x%08x/0x%03x = 0x%04x), b %s, t %s\n",
+ + 			m->muxnames[0], m->muxnames[mode],
+ + 			partition->phys + m->reg_offset, m->reg_offset, val,
+ + 			m->balls[0] ? m->balls[0] : none,
+ + 			m->balls[1] ? m->balls[1] : none);
+ + 	seq_printf(s, "mode: ");
+ + 	if (cpu_is_am335x())
+ + 		am33xx_mux_decode(s, val);
+ + 	else
+ + 		omap_mux_decode(s, val);
+ + 	seq_printf(s, "\n");
+ + 	seq_printf(s, "signals: %s | %s | %s | %s | %s | %s | %s | %s\n",
+ + 			m->muxnames[0] ? m->muxnames[0] : none,
+ + 			m->muxnames[1] ? m->muxnames[1] : none,
+ + 			m->muxnames[2] ? m->muxnames[2] : none,
+ + 			m->muxnames[3] ? m->muxnames[3] : none,
+ + 			m->muxnames[4] ? m->muxnames[4] : none,
+ + 			m->muxnames[5] ? m->muxnames[5] : none,
+ + 			m->muxnames[6] ? m->muxnames[6] : none,
+ + 			m->muxnames[7] ? m->muxnames[7] : none);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + #define OMAP_MUX_MAX_ARG_CHAR  7
+ + 
+ + static ssize_t omap_mux_dbg_signal_write(struct file *file,
+ + 					 const char __user *user_buf,
+ + 					 size_t count, loff_t *ppos)
+ + {
+ + 	char buf[OMAP_MUX_MAX_ARG_CHAR];
+ + 	struct seq_file *seqf;
+ + 	struct omap_mux *m;
+ + 	unsigned long val;
+ + 	int buf_size, ret;
+ + 	struct omap_mux_partition *partition;
+ + 
+ + 	if (count > OMAP_MUX_MAX_ARG_CHAR)
+ + 		return -EINVAL;
+ + 
+ + 	memset(buf, 0, sizeof(buf));
+ + 	buf_size = min(count, sizeof(buf) - 1);
+ + 
+ + 	if (copy_from_user(buf, user_buf, buf_size))
+ + 		return -EFAULT;
+ + 
+ + 	ret = strict_strtoul(buf, 0x10, &val);
+ + 	if (ret < 0)
+ + 		return ret;
+ + 
+ + 	if (val > 0xffff)
+ + 		return -EINVAL;
+ + 
+ + 	seqf = file->private_data;
+ + 	m = seqf->private;
+ + 
+ + 	partition = omap_mux_get_partition(m);
+ + 	if (!partition)
+ + 		return -ENODEV;
+ + 
+ + 	omap_mux_write(partition, (u16)val, m->reg_offset);
+ + 	*ppos += count;
+ + 
+ + 	return count;
+ + }
+ + 
+ + static int omap_mux_dbg_signal_open(struct inode *inode, struct file *file)
+ + {
+ + 	return single_open(file, omap_mux_dbg_signal_show, inode->i_private);
+ + }
+ + 
+ + static const struct file_operations omap_mux_dbg_signal_fops = {
+ + 	.open		= omap_mux_dbg_signal_open,
+ + 	.read		= seq_read,
+ + 	.write		= omap_mux_dbg_signal_write,
+ + 	.llseek		= seq_lseek,
+ + 	.release	= single_release,
+ + };
+ + 
+ + static struct dentry *mux_dbg_dir;
+ + 
+ + static void omap_mux_dbg_create_entry(
+ + 				struct omap_mux_partition *partition,
+ + 				struct dentry *mux_dbg_dir)
+ + {
+ + 	struct omap_mux_entry *e;
+ + 
+ + 	list_for_each_entry(e, &partition->muxmodes, node) {
+ + 		struct omap_mux *m = &e->mux;
+ + 
+ + 		(void)debugfs_create_file(m->muxnames[0], S_IWUSR, mux_dbg_dir,
+ + 					  m, &omap_mux_dbg_signal_fops);
+ + 	}
+ + }
+ + 
+ + static void omap_mux_dbg_init(void)
+ + {
+ + 	struct omap_mux_partition *partition;
+ + 	static struct dentry *mux_dbg_board_dir;
+ + 
+ + 	mux_dbg_dir = debugfs_create_dir("omap_mux", NULL);
+ + 	if (!mux_dbg_dir)
+ + 		return;
+ + 
+ + 	mux_dbg_board_dir = debugfs_create_dir("board", mux_dbg_dir);
+ + 	if (!mux_dbg_board_dir)
+ + 		return;
+ + 
+ + 	list_for_each_entry(partition, &mux_partitions, node) {
+ + 		omap_mux_dbg_create_entry(partition, mux_dbg_dir);
+ + 		(void)debugfs_create_file(partition->name, S_IRUGO,
+ + 					  mux_dbg_board_dir, partition,
+ + 					  &omap_mux_dbg_board_fops);
+ + 	}
+ + }
+ + 
+ + #else
+ + static inline void omap_mux_dbg_init(void)
+ + {
+ + }
+ + #endif	/* CONFIG_DEBUG_FS */
+ + 
+ + static void omap_mux_free_names(struct omap_mux *m)
+ + {
+ + 	int i;
+ + 
+ + 	for (i = 0; i < OMAP_MUX_NR_MODES; i++)
+ + 		kfree(m->muxnames[i]);
+ + 
+ + #ifdef CONFIG_DEBUG_FS
+ + 	for (i = 0; i < OMAP_MUX_NR_SIDES; i++)
+ + 		kfree(m->balls[i]);
+ + #endif
+ + 
+ + }
+ + 
+ + /* Free all data except for GPIO pins unless CONFIG_DEBUG_FS is set */
+ + static int omap_mux_late_init(void)
+ + {
+ + 	struct omap_mux_partition *partition;
+ + 	int ret;
+ + 
+ + 	list_for_each_entry(partition, &mux_partitions, node) {
+ + 		struct omap_mux_entry *e, *tmp;
+ + 		list_for_each_entry_safe(e, tmp, &partition->muxmodes, node) {
+ + 			struct omap_mux *m = &e->mux;
+ + 			u16 mode = omap_mux_read(partition, m->reg_offset);
+ + 
+ + 			if (OMAP_MODE_GPIO(mode))
+ + 				continue;
+ + 
+ + #ifndef CONFIG_DEBUG_FS
+ + 			mutex_lock(&muxmode_mutex);
+ + 			list_del(&e->node);
+ + 			mutex_unlock(&muxmode_mutex);
+ + 			omap_mux_free_names(m);
+ + 			kfree(m);
+ + #endif
+ + 		}
+ + 	}
+ + #if 0	/* this will fail anyway becasue PCM is not registerd */
+ + 	printk("IRQ num %d\n", omap_prcm_event_to_irq("io"));
+ + 
+ + 	ret = request_irq(omap_prcm_event_to_irq("io"),
+ + 		omap_hwmod_mux_handle_irq, IRQF_SHARED | IRQF_NO_SUSPEND,
+ + 			"hwmod_io", omap_mux_late_init);
+ + 
+ + 	if (ret)
+ + 		pr_warning("mux: Failed to setup hwmod io irq %d\n", ret);
+ + #endif
+ + 	omap_mux_dbg_init();
+ + 
+ + 	return 0;
+ + }
+ + late_initcall(omap_mux_late_init);
+ + 
+ + static void omap_mux_package_fixup(struct omap_mux *p,
+ + 					struct omap_mux *superset)
+ + {
+ + 	while (p->reg_offset !=  OMAP_MUX_TERMINATOR) {
+ + 		struct omap_mux *s = superset;
+ + 		int found = 0;
+ + 
+ + 		while (s->reg_offset != OMAP_MUX_TERMINATOR) {
+ + 			if (s->reg_offset == p->reg_offset) {
+ + 				*s = *p;
+ + 				found++;
+ + 				break;
+ + 			}
+ + 			s++;
+ + 		}
+ + 		if (!found)
+ + 			pr_err("%s: Unknown entry offset 0x%x\n", __func__,
+ + 			       p->reg_offset);
+ + 		p++;
+ + 	}
+ + }
+ + 
+ + #ifdef CONFIG_DEBUG_FS
+ + 
+ + static void omap_mux_package_init_balls(struct omap_ball *b,
+ + 				struct omap_mux *superset)
+ + {
+ + 	while (b->reg_offset != OMAP_MUX_TERMINATOR) {
+ + 		struct omap_mux *s = superset;
+ + 		int found = 0;
+ + 
+ + 		while (s->reg_offset != OMAP_MUX_TERMINATOR) {
+ + 			if (s->reg_offset == b->reg_offset) {
+ + 				s->balls[0] = b->balls[0];
+ + 				s->balls[1] = b->balls[1];
+ + 				found++;
+ + 				break;
+ + 			}
+ + 			s++;
+ + 		}
+ + 		if (!found)
+ + 			pr_err("%s: Unknown ball offset 0x%x\n", __func__,
+ + 			       b->reg_offset);
+ + 		b++;
+ + 	}
+ + }
+ + 
+ + #else	/* CONFIG_DEBUG_FS */
+ + 
+ + static inline void omap_mux_package_init_balls(struct omap_ball *b,
+ + 					struct omap_mux *superset)
+ + {
+ + }
+ + 
+ + #endif	/* CONFIG_DEBUG_FS */
+ + 
+ + static int omap_mux_setup(char *options)
+ + {
+ + 	if (!options)
+ + 		return 0;
+ + 
+ + 	omap_mux_options = options;
+ + 
+ + 	return 1;
+ + }
+ + __setup("omap_mux=", omap_mux_setup);
+ + 
+ + /*
+ +  * Note that the omap_mux=some.signal1=0x1234,some.signal2=0x1234
+ +  * cmdline options only override the bootloader values.
+ +  * During development, please enable CONFIG_DEBUG_FS, and use the
+ +  * signal specific entries under debugfs.
+ +  */
+ + static void omap_mux_set_cmdline_signals(void)
+ + {
+ + 	char *options, *next_opt, *token;
+ + 
+ + 	if (!omap_mux_options)
+ + 		return;
+ + 
+ + 	options = kstrdup(omap_mux_options, GFP_KERNEL);
+ + 	if (!options)
+ + 		return;
+ + 
+ + 	next_opt = options;
+ + 
+ + 	while ((token = strsep(&next_opt, ",")) != NULL) {
+ + 		char *keyval, *name;
+ + 		unsigned long val;
+ + 
+ + 		keyval = token;
+ + 		name = strsep(&keyval, "=");
+ + 		if (name) {
+ + 			int res;
+ + 
+ + 			res = strict_strtoul(keyval, 0x10, &val);
+ + 			if (res < 0)
+ + 				continue;
+ + 
+ + 			omap_mux_init_signal(name, (u16)val);
+ + 		}
+ + 	}
+ + 
+ + 	kfree(options);
+ + }
+ + 
+ + static int omap_mux_copy_names(struct omap_mux *src,
+ + 				      struct omap_mux *dst)
+ + {
+ + 	int i;
+ + 
+ + 	for (i = 0; i < OMAP_MUX_NR_MODES; i++) {
+ + 		if (src->muxnames[i]) {
+ + 			dst->muxnames[i] = kstrdup(src->muxnames[i],
+ + 						   GFP_KERNEL);
+ + 			if (!dst->muxnames[i])
+ + 				goto free;
+ + 		}
+ + 	}
+ + 
+ + #ifdef CONFIG_DEBUG_FS
+ + 	for (i = 0; i < OMAP_MUX_NR_SIDES; i++) {
+ + 		if (src->balls[i]) {
+ + 			dst->balls[i] = kstrdup(src->balls[i], GFP_KERNEL);
+ + 			if (!dst->balls[i])
+ + 				goto free;
+ + 		}
+ + 	}
+ + #endif
+ + 
+ + 	return 0;
+ + 
+ + free:
+ + 	omap_mux_free_names(dst);
+ + 	return -ENOMEM;
+ + 
+ + }
+ + 
+ + #endif	/* CONFIG_OMAP_MUX */
+ + 
+ + static struct omap_mux *omap_mux_get_by_gpio(
+ + 				struct omap_mux_partition *partition,
+ + 				int gpio)
+ + {
+ + 	struct omap_mux_entry *e;
+ + 	struct omap_mux *ret = NULL;
+ + 
+ + 	list_for_each_entry(e, &partition->muxmodes, node) {
+ + 		struct omap_mux *m = &e->mux;
+ + 		if (m->gpio == gpio) {
+ + 			ret = m;
+ + 			break;
+ + 		}
+ + 	}
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /* Needed for dynamic muxing of GPIO pins for off-idle */
+ + u16 omap_mux_get_gpio(int gpio)
+ + {
+ + 	struct omap_mux_partition *partition;
+ + 	struct omap_mux *m = NULL;
+ + 
+ + 	list_for_each_entry(partition, &mux_partitions, node) {
+ + 		m = omap_mux_get_by_gpio(partition, gpio);
+ + 		if (m)
+ + 			return omap_mux_read(partition, m->reg_offset);
+ + 	}
+ + 
+ + 	if (!m || m->reg_offset == OMAP_MUX_TERMINATOR)
+ + 		pr_err("%s: Could not get gpio%i\n", __func__, gpio);
+ + 
+ + 	return OMAP_MUX_TERMINATOR;
+ + }
+ + 
+ + /* Needed for dynamic muxing of GPIO pins for off-idle */
+ + void omap_mux_set_gpio(u16 val, int gpio)
+ + {
+ + 	struct omap_mux_partition *partition;
+ + 	struct omap_mux *m = NULL;
+ + 
+ + 	list_for_each_entry(partition, &mux_partitions, node) {
+ + 		m = omap_mux_get_by_gpio(partition, gpio);
+ + 		if (m) {
+ + 			omap_mux_write(partition, val, m->reg_offset);
+ + 			return;
+ + 		}
+ + 	}
+ + 
+ + 	if (!m || m->reg_offset == OMAP_MUX_TERMINATOR)
+ + 		pr_err("%s: Could not set gpio%i\n", __func__, gpio);
+ + }
+ + 
+ + static struct omap_mux * omap_mux_list_add(
+ + 					struct omap_mux_partition *partition,
+ + 					struct omap_mux *src)
+ + {
+ + 	struct omap_mux_entry *entry;
+ + 	struct omap_mux *m;
+ + 
+ + 	entry = kzalloc(sizeof(struct omap_mux_entry), GFP_KERNEL);
+ + 	if (!entry)
+ + 		return NULL;
+ + 
+ + 	m = &entry->mux;
+ + 	entry->mux = *src;
+ + 
+ + #ifdef CONFIG_OMAP_MUX
+ + 	if (omap_mux_copy_names(src, m)) {
+ + 		kfree(entry);
+ + 		return NULL;
+ + 	}
+ + #endif
+ + 
+ + 	mutex_lock(&muxmode_mutex);
+ + 	list_add_tail(&entry->node, &partition->muxmodes);
+ + 	mutex_unlock(&muxmode_mutex);
+ + 
+ + 	return m;
+ + }
+ + 
+ + /*
+ +  * Note if CONFIG_OMAP_MUX is not selected, we will only initialize
+ +  * the GPIO to mux offset mapping that is needed for dynamic muxing
+ +  * of GPIO pins for off-idle.
+ +  */
+ + static void omap_mux_init_list(struct omap_mux_partition *partition,
+ + 				      struct omap_mux *superset)
+ + {
+ + 	while (superset->reg_offset !=  OMAP_MUX_TERMINATOR) {
+ + 		struct omap_mux *entry;
+ + 
+ + #ifdef CONFIG_OMAP_MUX
+ + 		if (!superset->muxnames || !superset->muxnames[0]) {
+ + 			superset++;
+ + 			continue;
+ + 		}
+ + #else
+ + 		/* Skip pins that are not muxed as GPIO by bootloader */
+ + 		if (!OMAP_MODE_GPIO(omap_mux_read(partition,
+ + 				    superset->reg_offset))) {
+ + 			superset++;
+ + 			continue;
+ + 		}
+ + #endif
+ + 
+ + 		entry = omap_mux_list_add(partition, superset);
+ + 		if (!entry) {
+ + 			pr_err("%s: Could not add entry\n", __func__);
+ + 			return;
+ + 		}
+ + 		superset++;
+ + 	}
+ + }
+ + 
+ + #ifdef CONFIG_OMAP_MUX
+ + 
+ + static void omap_mux_init_package(struct omap_mux *superset,
+ + 				  struct omap_mux *package_subset,
+ + 				  struct omap_ball *package_balls)
+ + {
+ + 	if (package_subset)
+ + 		omap_mux_package_fixup(package_subset, superset);
+ + 	if (package_balls)
+ + 		omap_mux_package_init_balls(package_balls, superset);
+ + }
+ + 
+ + static void omap_mux_init_signals(struct omap_mux_partition *partition,
+ + 				  struct omap_board_mux *board_mux)
+ + {
+ + 	omap_mux_set_cmdline_signals();
+ + 	omap_mux_write_array(partition, board_mux);
+ + }
+ + 
+ + #else
+ + 
+ + static void omap_mux_init_package(struct omap_mux *superset,
+ + 				  struct omap_mux *package_subset,
+ + 				  struct omap_ball *package_balls)
+ + {
+ + }
+ + 
+ + static void omap_mux_init_signals(struct omap_mux_partition *partition,
+ + 				  struct omap_board_mux *board_mux)
+ + {
+ + }
+ + 
+ + #endif
+ + 
+ + static u32 mux_partitions_cnt;
+ + 
+ + int omap_mux_init(const char *name, u32 flags,
+ + 			 u32 mux_pbase, u32 mux_size,
+ + 			 struct omap_mux *superset,
+ + 			 struct omap_mux *package_subset,
+ + 			 struct omap_board_mux *board_mux,
+ + 			 struct omap_ball *package_balls)
+ + {
+ + 	struct omap_mux_partition *partition;
+ + 
+ + 	partition = kzalloc(sizeof(struct omap_mux_partition), GFP_KERNEL);
+ + 	if (!partition)
+ + 		return -ENOMEM;
+ + 
+ + 	partition->name = name;
+ + 	partition->flags = flags;
+ + 	partition->size = mux_size;
+ + 	partition->phys = mux_pbase;
+ + 	partition->base = ioremap(mux_pbase, mux_size);
+ + 	if (!partition->base) {
+ + 		pr_err("%s: Could not ioremap mux partition at 0x%08x\n",
+ + 			__func__, partition->phys);
+ + 		kfree(partition);
+ + 		return -ENODEV;
+ + 	}
+ + 
+ + 	INIT_LIST_HEAD(&partition->muxmodes);
+ + 
+ + 	list_add_tail(&partition->node, &mux_partitions);
+ + 	mux_partitions_cnt++;
+ + 	pr_info("%s: Add partition: #%d: %s, flags: %x\n", __func__,
+ + 		mux_partitions_cnt, partition->name, partition->flags);
+ + 
+ + 	omap_mux_init_package(superset, package_subset, package_balls);
+ + 	omap_mux_init_list(partition, superset);
+ + 	omap_mux_init_signals(partition, board_mux);
+ + 
+ + 	return 0;
+ + }
+ + 
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/mux.h linux-3.2.1/arch/arm/mach-ckb_3352/mux.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/mux.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/mux.h	2014-11-25 13:19:15.016985425 +0900
+ ***************
+ *** 0 ****
+ --- 1,370 ----
+ + /*
+ +  * Copyright (C) 2009 Nokia
+ +  * Copyright (C) 2009-2010 Texas Instruments
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #include "mux33xx.h"
+ + 
+ + #define OMAP_MUX_TERMINATOR	0xffff
+ + 
+ + /* 34xx mux mode options for each pin. See TRM for options */
+ + #define OMAP_MUX_MODE0      0
+ + #define OMAP_MUX_MODE1      1
+ + #define OMAP_MUX_MODE2      2
+ + #define OMAP_MUX_MODE3      3
+ + #define OMAP_MUX_MODE4      4
+ + #define OMAP_MUX_MODE5      5
+ + #define OMAP_MUX_MODE6      6
+ + #define OMAP_MUX_MODE7      7
+ + 
+ + /* 24xx/34xx mux bit defines */
+ + #define OMAP_PULL_ENA			(1 << 3)
+ + #define OMAP_PULL_UP			(1 << 4)
+ + #define OMAP_ALTELECTRICALSEL		(1 << 5)
+ + 
+ + /* 34xx specific mux bit defines */
+ + #define OMAP_INPUT_EN			(1 << 8)
+ + #define OMAP_OFF_EN			(1 << 9)
+ + #define OMAP_OFFOUT_EN			(1 << 10)
+ + #define OMAP_OFFOUT_VAL			(1 << 11)
+ + #define OMAP_OFF_PULL_EN		(1 << 12)
+ + #define OMAP_OFF_PULL_UP		(1 << 13)
+ + #define OMAP_WAKEUP_EN			(1 << 14)
+ + 
+ + /* 44xx specific mux bit defines */
+ + #define OMAP_WAKEUP_EVENT		(1 << 15)
+ + 
+ + /* am33xx specific mux bit defines */
+ + #define AM33XX_SLEWCTRL_FAST		(0 << 6)
+ + #define AM33XX_SLEWCTRL_SLOW		(1 << 6)
+ + #define AM33XX_INPUT_EN			(1 << 5)
+ + #define AM33XX_PULL_UP			(1 << 4)
+ + /* bit 3: 0 - enable, 1 - disable for pull enable */
+ + #define AM33XX_PULL_DISA		(1 << 3)
+ + #define AM33XX_PULL_ENBL		(0 << 3)
+ + 
+ + /* Definition of output pin could have pull disabled, but
+ +  * this has not been done due to two reasons
+ +  * 1. AM33XX_MUX will take care of it
+ +  * 2. If pull was disabled for out macro, combining out & in pull on macros
+ +  *    would disable pull resistor and AM33XX_MUX cannot take care of the
+ +  *    correct pull setting and unintentionally pull would get disabled
+ +  */
+ + #define	AM33XX_PIN_OUTPUT		(0)
+ + #define	AM33XX_PIN_OUTPUT_PULLUP	(AM33XX_PULL_UP)
+ + #define	AM33XX_PIN_INPUT		(AM33XX_INPUT_EN | AM33XX_PULL_DISA)
+ + #define	AM33XX_PIN_INPUT_PULLUP		(AM33XX_INPUT_EN | AM33XX_PULL_UP)
+ + #define	AM33XX_PIN_INPUT_PULLDOWN	(AM33XX_INPUT_EN)
+ + 
+ + /* Active pin states */
+ + #define OMAP_PIN_OUTPUT			0
+ + #define OMAP_PIN_INPUT			OMAP_INPUT_EN
+ + #define OMAP_PIN_INPUT_PULLUP		(OMAP_PULL_ENA | OMAP_INPUT_EN \
+ + 						| OMAP_PULL_UP)
+ + #define OMAP_PIN_INPUT_PULLDOWN		(OMAP_PULL_ENA | OMAP_INPUT_EN)
+ + 
+ + /* Off mode states */
+ + #define OMAP_PIN_OFF_NONE		0
+ + #define OMAP_PIN_OFF_OUTPUT_HIGH	(OMAP_OFF_EN | OMAP_OFFOUT_EN \
+ + 						| OMAP_OFFOUT_VAL)
+ + #define OMAP_PIN_OFF_OUTPUT_LOW		(OMAP_OFF_EN | OMAP_OFFOUT_EN)
+ + #define OMAP_PIN_OFF_INPUT_PULLUP	(OMAP_OFF_EN | OMAP_OFF_PULL_EN \
+ + 						| OMAP_OFF_PULL_UP)
+ + #define OMAP_PIN_OFF_INPUT_PULLDOWN	(OMAP_OFF_EN | OMAP_OFF_PULL_EN)
+ + #define OMAP_PIN_OFF_WAKEUPENABLE	OMAP_WAKEUP_EN
+ + 
+ + #define OMAP_MODE_GPIO(x)	(((x) & OMAP_MUX_MODE7) == OMAP_MUX_MODE4)
+ + 
+ + /* Flags for omapX_mux_init */
+ + #define OMAP_PACKAGE_MASK		0xffff
+ + #define OMAP_PACKAGE_CBS		8		/* 547-pin 0.40 0.40 */
+ + #define OMAP_PACKAGE_CBL		7		/* 547-pin 0.40 0.40 */
+ + #define OMAP_PACKAGE_CBP		6		/* 515-pin 0.40 0.50 */
+ + #define OMAP_PACKAGE_CUS		5		/* 423-pin 0.65 */
+ + #define OMAP_PACKAGE_CBB		4		/* 515-pin 0.40 0.50 */
+ + #define OMAP_PACKAGE_CBC		3		/* 515-pin 0.50 0.65 */
+ + #define OMAP_PACKAGE_ZAC		2		/* 24xx 447-pin POP */
+ + #define OMAP_PACKAGE_ZAF		1		/* 2420 447-pin SIP */
+ + 
+ + 
+ + #define OMAP_MUX_NR_MODES		8		/* Available modes */
+ + #define OMAP_MUX_NR_SIDES		2		/* Bottom & top */
+ + 
+ + /*
+ +  * omap_mux_init flags definition:
+ +  *
+ +  * OMAP_MUX_REG_8BIT: Ensure that access to padconf is done in 8 bits.
+ +  * The default value is 16 bits.
+ +  * OMAP_MUX_GPIO_IN_MODE3: The GPIO is selected in mode3.
+ +  * The default is mode4.
+ +  */
+ + #define OMAP_MUX_REG_8BIT		(1 << 0)
+ + #define OMAP_MUX_GPIO_IN_MODE3		(1 << 1)
+ + 
+ + /**
+ +  * struct omap_board_data - board specific device data
+ +  * @id: instance id
+ +  * @flags: additional flags for platform init code
+ +  * @pads: array of device specific pads
+ +  * @pads_cnt: ARRAY_SIZE() of pads
+ +  */
+ + struct omap_board_data {
+ + 	int			id;
+ + 	u32			flags;
+ + 	struct omap_device_pad	*pads;
+ + 	int			pads_cnt;
+ + };
+ + 
+ + /**
+ +  * struct mux_partition - contain partition related information
+ +  * @name: name of the current partition
+ +  * @flags: flags specific to this partition
+ +  * @phys: physical address
+ +  * @size: partition size
+ +  * @base: virtual address after ioremap
+ +  * @muxmodes: list of nodes that belong to a partition
+ +  * @node: list node for the partitions linked list
+ +  */
+ + struct omap_mux_partition {
+ + 	const char		*name;
+ + 	u32			flags;
+ + 	u32			phys;
+ + 	u32			size;
+ + 	void __iomem		*base;
+ + 	struct list_head	muxmodes;
+ + 	struct list_head	node;
+ + };
+ + 
+ + /**
+ +  * struct omap_mux - data for omap mux register offset and it's value
+ +  * @reg_offset:	mux register offset from the mux base
+ +  * @gpio:	GPIO number
+ +  * @muxnames:	available signal modes for a ball
+ +  * @balls:	available balls on the package
+ +  * @partition:	mux partition
+ +  */
+ + struct omap_mux {
+ + 	u16	reg_offset;
+ + 	u16	gpio;
+ + #ifdef CONFIG_OMAP_MUX
+ + 	char	*muxnames[OMAP_MUX_NR_MODES];
+ + #ifdef CONFIG_DEBUG_FS
+ + 	char	*balls[OMAP_MUX_NR_SIDES];
+ + #endif
+ + #endif
+ + };
+ + 
+ + /**
+ +  * struct omap_ball - data for balls on omap package
+ +  * @reg_offset:	mux register offset from the mux base
+ +  * @balls:	available balls on the package
+ +  */
+ + struct omap_ball {
+ + 	u16	reg_offset;
+ + 	char	*balls[OMAP_MUX_NR_SIDES];
+ + };
+ + 
+ + /**
+ +  * struct omap_board_mux - data for initializing mux registers
+ +  * @reg_offset:	mux register offset from the mux base
+ +  * @mux_value:	desired mux value to set
+ +  */
+ + struct omap_board_mux {
+ + 	u16	reg_offset;
+ + 	u16	value;
+ + };
+ + 
+ + #define OMAP_DEVICE_PAD_REMUX		BIT(1)	/* Dynamically remux a pad,
+ + 						   needs enable, idle and off
+ + 						   values */
+ + #define OMAP_DEVICE_PAD_WAKEUP		BIT(0)	/* Pad is wake-up capable */
+ + 
+ + /**
+ +  * struct omap_device_pad - device specific pad configuration
+ +  * @name:		signal name
+ +  * @flags:		pad specific runtime flags
+ +  * @enable:		runtime value for a pad
+ +  * @idle:		idle value for a pad
+ +  * @off:		off value for a pad, defaults to safe mode
+ +  * @partition:		mux partition
+ +  * @mux:		mux register
+ +  */
+ + struct omap_device_pad {
+ + 	char				*name;
+ + 	u8				flags;
+ + 	u16				enable;
+ + 	u16				idle;
+ + 	u16				off;
+ + 	struct omap_mux_partition	*partition;
+ + 	struct omap_mux			*mux;
+ + };
+ + 
+ + struct omap_hwmod_mux_info;
+ + 
+ + #define OMAP_MUX_STATIC(signal, mode)					\
+ + {									\
+ + 	.name	= (signal),						\
+ + 	.enable	= (mode),						\
+ + }
+ + 
+ + #if defined(CONFIG_OMAP_MUX)
+ + 
+ + /**
+ +  * omap_mux_init_gpio - initialize a signal based on the GPIO number
+ +  * @gpio:		GPIO number
+ +  * @val:		Options for the mux register value
+ +  */
+ + int omap_mux_init_gpio(int gpio, int val);
+ + 
+ + /**
+ +  * omap_mux_init_signal - initialize a signal based on the signal name
+ +  * @muxname:		Mux name in mode0_name.signal_name format
+ +  * @val:		Options for the mux register value
+ +  */
+ + int omap_mux_init_signal(const char *muxname, int val);
+ + 
+ + /**
+ +  * omap_hwmod_mux_init - initialize hwmod specific mux data
+ +  * @bpads:		Board specific device signal names
+ +  * @nr_pads:		Number of signal names for the device
+ +  */
+ + extern struct omap_hwmod_mux_info *
+ + omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads);
+ + 
+ + /**
+ +  * omap_hwmod_mux - omap hwmod specific pin muxing
+ +  * @hmux:		Pads for a hwmod
+ +  * @state:		Desired _HWMOD_STATE
+ +  *
+ +  * Called only from omap_hwmod.c, do not use.
+ +  */
+ + void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state);
+ + 
+ + #else
+ + 
+ + static inline int omap_mux_init_gpio(int gpio, int val)
+ + {
+ + 	return 0;
+ + }
+ + static inline int omap_mux_init_signal(char *muxname, int val)
+ + {
+ + 	return 0;
+ + }
+ + 
+ + static inline struct omap_hwmod_mux_info *
+ + omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads)
+ + {
+ + 	return NULL;
+ + }
+ + 
+ + static inline void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
+ + {
+ + }
+ + 
+ + static struct omap_board_mux *board_mux __initdata __maybe_unused;
+ + 
+ + #endif
+ + 
+ + /**
+ +  * omap_mux_get_gpio() - get mux register value based on GPIO number
+ +  * @gpio:		GPIO number
+ +  *
+ +  */
+ + u16 omap_mux_get_gpio(int gpio);
+ + 
+ + /**
+ +  * omap_mux_set_gpio() - set mux register value based on GPIO number
+ +  * @val:		New mux register value
+ +  * @gpio:		GPIO number
+ +  *
+ +  */
+ + void omap_mux_set_gpio(u16 val, int gpio);
+ + 
+ + /**
+ +  * omap_mux_get() - get a mux partition by name
+ +  * @name:		Name of the mux partition
+ +  *
+ +  */
+ + struct omap_mux_partition *omap_mux_get(const char *name);
+ + 
+ + /**
+ +  * omap_mux_read() - read mux register
+ +  * @partition:		Mux partition
+ +  * @mux_offset:		Offset of the mux register
+ +  *
+ +  */
+ + u16 omap_mux_read(struct omap_mux_partition *p, u16 mux_offset);
+ + 
+ + /**
+ +  * omap_mux_write() - write mux register
+ +  * @partition:		Mux partition
+ +  * @val:		New mux register value
+ +  * @mux_offset:		Offset of the mux register
+ +  *
+ +  * This should be only needed for dynamic remuxing of non-gpio signals.
+ +  */
+ + void omap_mux_write(struct omap_mux_partition *p, u16 val, u16 mux_offset);
+ + 
+ + /**
+ +  * omap_mux_write_array() - write an array of mux registers
+ +  * @partition:		Mux partition
+ +  * @board_mux:		Array of mux registers terminated by MAP_MUX_TERMINATOR
+ +  *
+ +  * This should be only needed for dynamic remuxing of non-gpio signals.
+ +  */
+ + void omap_mux_write_array(struct omap_mux_partition *p,
+ + 			  struct omap_board_mux *board_mux);
+ + 
+ + /**
+ +  * omap2420_mux_init() - initialize mux system with board specific set
+ +  * @board_mux:		Board specific mux table
+ +  * @flags:		OMAP package type used for the board
+ +  */
+ + int omap2420_mux_init(struct omap_board_mux *board_mux, int flags);
+ + 
+ + /**
+ +  * omap2430_mux_init() - initialize mux system with board specific set
+ +  * @board_mux:		Board specific mux table
+ +  * @flags:		OMAP package type used for the board
+ +  */
+ + int omap2430_mux_init(struct omap_board_mux *board_mux, int flags);
+ + 
+ + /**
+ +  * omap3_mux_init() - initialize mux system with board specific set
+ +  * @board_mux:		Board specific mux table
+ +  * @flags:		OMAP package type used for the board
+ +  */
+ + int omap3_mux_init(struct omap_board_mux *board_mux, int flags);
+ + 
+ + /**
+ +  * omap4_mux_init() - initialize mux system with board specific set
+ +  * @board_subset:	Board specific mux table
+ +  * @board_wkup_subset:	Board specific mux table for wakeup instance
+ +  * @flags:		OMAP package type used for the board
+ +  */
+ + int omap4_mux_init(struct omap_board_mux *board_subset,
+ + 	struct omap_board_mux *board_wkup_subset, int flags);
+ + 
+ + /**
+ +  * am33xx_mux_init() - initialize mux system along with board specific set
+ +  * @board_mux:		Board specific mux table
+ +  */
+ + int am33xx_mux_init(struct omap_board_mux *board_mux);
+ + 
+ + /**
+ +  * omap_mux_init - private mux init function, do not call
+ +  */
+ + int omap_mux_init(const char *name, u32 flags,
+ + 		  u32 mux_pbase, u32 mux_size,
+ + 		  struct omap_mux *superset,
+ + 		  struct omap_mux *package_subset,
+ + 		  struct omap_board_mux *board_mux,
+ + 		  struct omap_ball *package_balls);
+ + 
+ + int omap_mux_get_by_name(const char *muxname,
+ + 			struct omap_mux_partition **found_partition,
+ + 			struct omap_mux **found_mux);
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_hwmod_2xxx_3xxx_ipblock_data.c linux-3.2.1/arch/arm/mach-ckb_3352/omap_hwmod_2xxx_3xxx_ipblock_data.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_hwmod_2xxx_3xxx_ipblock_data.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/omap_hwmod_2xxx_3xxx_ipblock_data.c	2014-11-25 13:19:15.016985425 +0900
+ ***************
+ *** 0 ****
+ --- 1,325 ----
+ + /*
+ +  * omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3
+ +  *
+ +  * Copyright (C) 2011 Nokia Corporation
+ +  * Paul Walmsley
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + #include <plat/omap_hwmod.h>
+ + #include <plat/serial.h>
+ + #include <plat/dma.h>
+ + #include <plat/common.h>
+ + 
+ + #include <mach/irqs.h>
+ + 
+ + #include "omap_hwmod_common_data.h"
+ + 
+ + /* UART */
+ + 
+ + static struct omap_hwmod_class_sysconfig omap2_uart_sysc = {
+ + 	.rev_offs	= 0x50,
+ + 	.sysc_offs	= 0x54,
+ + 	.syss_offs	= 0x58,
+ + 	.sysc_flags	= (SYSC_HAS_SIDLEMODE |
+ + 			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ + 			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+ + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ + 	.sysc_fields	= &omap_hwmod_sysc_type1,
+ + };
+ + 
+ + struct omap_hwmod_class omap2_uart_class = {
+ + 	.name	= "uart",
+ + 	.sysc	= &omap2_uart_sysc,
+ + };
+ + 
+ + /*
+ +  * 'dss' class
+ +  * display sub-system
+ +  */
+ + 
+ + static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
+ + 	.rev_offs	= 0x0000,
+ + 	.sysc_offs	= 0x0010,
+ + 	.syss_offs	= 0x0014,
+ + 	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+ + 			   SYSS_HAS_RESET_STATUS),
+ + 	.sysc_fields	= &omap_hwmod_sysc_type1,
+ + };
+ + 
+ + struct omap_hwmod_class omap2_dss_hwmod_class = {
+ + 	.name	= "dss",
+ + 	.sysc	= &omap2_dss_sysc,
+ + 	.reset	= omap_dss_reset,
+ + };
+ + 
+ + /*
+ +  * 'dispc' class
+ +  * display controller
+ +  */
+ + 
+ + static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
+ + 	.rev_offs	= 0x0000,
+ + 	.sysc_offs	= 0x0010,
+ + 	.syss_offs	= 0x0014,
+ + 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
+ + 			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ + 			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+ + 	.sysc_fields	= &omap_hwmod_sysc_type1,
+ + };
+ + 
+ + struct omap_hwmod_class omap2_dispc_hwmod_class = {
+ + 	.name	= "dispc",
+ + 	.sysc	= &omap2_dispc_sysc,
+ + };
+ + 
+ + /*
+ +  * 'rfbi' class
+ +  * remote frame buffer interface
+ +  */
+ + 
+ + static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = {
+ + 	.rev_offs	= 0x0000,
+ + 	.sysc_offs	= 0x0010,
+ + 	.syss_offs	= 0x0014,
+ + 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ + 			   SYSC_HAS_AUTOIDLE),
+ + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ + 	.sysc_fields	= &omap_hwmod_sysc_type1,
+ + };
+ + 
+ + struct omap_hwmod_class omap2_rfbi_hwmod_class = {
+ + 	.name	= "rfbi",
+ + 	.sysc	= &omap2_rfbi_sysc,
+ + };
+ + 
+ + /*
+ +  * 'venc' class
+ +  * video encoder
+ +  */
+ + 
+ + struct omap_hwmod_class omap2_venc_hwmod_class = {
+ + 	.name = "venc",
+ + };
+ + 
+ + 
+ + /* Common DMA request line data */
+ + struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {
+ + 	{ .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
+ + 	{ .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
+ + 	{ .dma_req = -1 }
+ + };
+ + 
+ + struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {
+ + 	{ .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
+ + 	{ .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
+ + 	{ .dma_req = -1 }
+ + };
+ + 
+ + struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {
+ + 	{ .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
+ + 	{ .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
+ + 	{ .dma_req = -1 }
+ + };
+ + 
+ + struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {
+ + 	{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
+ + 	{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
+ + 	{ .dma_req = -1 }
+ + };
+ + 
+ + struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {
+ + 	{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
+ + 	{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
+ + 	{ .dma_req = -1 }
+ + };
+ + 
+ + struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = {
+ + 	{ .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
+ + 	{ .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
+ + 	{ .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
+ + 	{ .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
+ + 	{ .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
+ + 	{ .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
+ + 	{ .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
+ + 	{ .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
+ + 	{ .dma_req = -1 }
+ + };
+ + 
+ + struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = {
+ + 	{ .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
+ + 	{ .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
+ + 	{ .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
+ + 	{ .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
+ + 	{ .dma_req = -1 }
+ + };
+ + 
+ + struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = {
+ + 	{ .name = "rx", .dma_req = 32 },
+ + 	{ .name = "tx", .dma_req = 31 },
+ + 	{ .dma_req = -1 }
+ + };
+ + 
+ + struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = {
+ + 	{ .name = "rx", .dma_req = 34 },
+ + 	{ .name = "tx", .dma_req = 33 },
+ + 	{ .dma_req = -1 }
+ + };
+ + 
+ + struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = {
+ + 	{ .name = "rx", .dma_req = 18 },
+ + 	{ .name = "tx", .dma_req = 17 },
+ + 	{ .dma_req = -1 }
+ + };
+ + 
+ + /* Other IP block data */
+ + 
+ + 
+ + /*
+ +  * omap_hwmod class data
+ +  */
+ + 
+ + struct omap_hwmod_class l3_hwmod_class = {
+ + 	.name = "l3"
+ + };
+ + 
+ + struct omap_hwmod_class l4_hwmod_class = {
+ + 	.name = "l4"
+ + };
+ + 
+ + struct omap_hwmod_class mpu_hwmod_class = {
+ + 	.name = "mpu"
+ + };
+ + 
+ + struct omap_hwmod_class iva_hwmod_class = {
+ + 	.name = "iva"
+ + };
+ + 
+ + /* Common MPU IRQ line data */
+ + 
+ + struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = {
+ + 	{ .irq = 37, },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = {
+ + 	{ .irq = 38, },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = {
+ + 	{ .irq = 39, },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = {
+ + 	{ .irq = 40, },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = {
+ + 	{ .irq = 41, },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = {
+ + 	{ .irq = 42, },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = {
+ + 	{ .irq = 43, },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = {
+ + 	{ .irq = 44, },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = {
+ + 	{ .irq = 45, },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = {
+ + 	{ .irq = 46, },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = {
+ + 	{ .irq = 47, },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = {
+ + 	{ .irq = INT_24XX_UART1_IRQ, },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = {
+ + 	{ .irq = INT_24XX_UART2_IRQ, },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = {
+ + 	{ .irq = INT_24XX_UART3_IRQ, },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + struct omap_hwmod_irq_info omap2_dispc_irqs[] = {
+ + 	{ .irq = 25 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = {
+ + 	{ .irq = INT_24XX_I2C1_IRQ, },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = {
+ + 	{ .irq = INT_24XX_I2C2_IRQ, },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + struct omap_hwmod_irq_info omap2_gpio1_irqs[] = {
+ + 	{ .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + struct omap_hwmod_irq_info omap2_gpio2_irqs[] = {
+ + 	{ .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + struct omap_hwmod_irq_info omap2_gpio3_irqs[] = {
+ + 	{ .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + struct omap_hwmod_irq_info omap2_gpio4_irqs[] = {
+ + 	{ .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + struct omap_hwmod_irq_info omap2_dma_system_irqs[] = {
+ + 	{ .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
+ + 	{ .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
+ + 	{ .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
+ + 	{ .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = {
+ + 	{ .irq = 65 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
+ + 	{ .irq = 66 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_hwmod_33xx_data.c linux-3.2.1/arch/arm/mach-ckb_3352/omap_hwmod_33xx_data.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_hwmod_33xx_data.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/omap_hwmod_33xx_data.c	2014-11-25 13:19:15.024034500 +0900
+ ***************
+ *** 0 ****
+ --- 1,3742 ----
+ + /*
+ +  * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
+ +  *
+ +  * Copyright (C) {2011} Texas Instruments Incorporated - http://www.ti.com/
+ +  *
+ +  * This file is automatically generated from the AM33XX hardware databases.
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #include <linux/io.h>
+ + #include <linux/slab.h>
+ + #include <linux/err.h>
+ + #include <linux/errno.h>
+ + 
+ + #include <plat/omap_hwmod.h>
+ + #include <plat/cpu.h>
+ + #include <plat/gpio.h>
+ + #include <plat/dma.h>
+ + #include <plat/mmc.h>
+ + #include <plat/mcspi.h>
+ + #include <plat/i2c.h>
+ + #include <plat/clock.h>
+ + #include <plat/prcm.h>
+ + 
+ + #include "omap_hwmod_common_data.h"
+ + #include "control.h"
+ + #include "cm33xx.h"
+ + #include "prm33xx.h"
+ + #include "common.h"
+ + #include "wd_timer.h"
+ + 
+ + /* Backward references (IPs with Bus Master capability) */
+ + static struct omap_hwmod am33xx_mpu_hwmod;
+ + static struct omap_hwmod am33xx_l3_main_hwmod;
+ + static struct omap_hwmod am33xx_l3slow_hwmod;
+ + static struct omap_hwmod am33xx_l4wkup_hwmod;
+ + static struct omap_hwmod am33xx_l4per_hwmod;
+ + static struct omap_hwmod am33xx_uart1_hwmod;
+ + static struct omap_hwmod am33xx_uart2_hwmod;
+ + static struct omap_hwmod am33xx_uart3_hwmod;
+ + static struct omap_hwmod am33xx_uart4_hwmod;
+ + static struct omap_hwmod am33xx_uart5_hwmod;
+ + static struct omap_hwmod am33xx_uart6_hwmod;
+ + static struct omap_hwmod am33xx_timer0_hwmod;
+ + static struct omap_hwmod am33xx_timer1_hwmod;
+ + static struct omap_hwmod am33xx_timer2_hwmod;
+ + static struct omap_hwmod am33xx_timer3_hwmod;
+ + static struct omap_hwmod am33xx_timer4_hwmod;
+ + static struct omap_hwmod am33xx_timer5_hwmod;
+ + static struct omap_hwmod am33xx_timer6_hwmod;
+ + static struct omap_hwmod am33xx_timer7_hwmod;
+ + static struct omap_hwmod am33xx_wd_timer1_hwmod;
+ + static struct omap_hwmod am33xx_tpcc_hwmod;
+ + static struct omap_hwmod am33xx_tptc0_hwmod;
+ + static struct omap_hwmod am33xx_tptc1_hwmod;
+ + static struct omap_hwmod am33xx_tptc2_hwmod;
+ + static struct omap_hwmod am33xx_dcan0_hwmod;
+ + static struct omap_hwmod am33xx_dcan1_hwmod;
+ + static struct omap_hwmod am33xx_gpio0_hwmod;
+ + static struct omap_hwmod am33xx_gpio1_hwmod;
+ + static struct omap_hwmod am33xx_gpio2_hwmod;
+ + static struct omap_hwmod am33xx_gpio3_hwmod;
+ + static struct omap_hwmod am33xx_i2c1_hwmod;
+ + static struct omap_hwmod am33xx_i2c2_hwmod;
+ + static struct omap_hwmod am33xx_i2c3_hwmod;
+ + static struct omap_hwmod am33xx_usbss_hwmod;
+ + static struct omap_hwmod am33xx_mmc0_hwmod;
+ + static struct omap_hwmod am33xx_mmc1_hwmod;
+ + static struct omap_hwmod am33xx_mmc2_hwmod;
+ + static struct omap_hwmod am33xx_spi0_hwmod;
+ + static struct omap_hwmod am33xx_spi1_hwmod;
+ + static struct omap_hwmod am33xx_elm_hwmod;
+ + static struct omap_hwmod am33xx_adc_tsc_hwmod;
+ + static struct omap_hwmod am33xx_aes0_hwmod;
+ + static struct omap_hwmod am33xx_rtc_hwmod;
+ + static struct omap_hwmod am33xx_sha0_hwmod;
+ + static struct omap_hwmod am33xx_mcasp0_hwmod;
+ + static struct omap_hwmod am33xx_mcasp1_hwmod;
+ + static struct omap_hwmod am33xx_ehrpwm0_hwmod;
+ + static struct omap_hwmod am33xx_ehrpwm1_hwmod;
+ + static struct omap_hwmod am33xx_ehrpwm2_hwmod;
+ + static struct omap_hwmod am33xx_ecap0_hwmod;
+ + static struct omap_hwmod am33xx_ecap1_hwmod;
+ + static struct omap_hwmod am33xx_ecap2_hwmod;
+ + static struct omap_hwmod am33xx_gpmc_hwmod;
+ + static struct omap_hwmod am33xx_lcdc_hwmod;
+ + static struct omap_hwmod am33xx_mailbox_hwmod;
+ + static struct omap_hwmod am33xx_cpgmac0_hwmod;
+ + static struct omap_hwmod am33xx_mdio_hwmod;
+ + static struct omap_hwmod am33xx_rng_hwmod;
+ + 
+ + /*
+ +  * ERRATA: (Yet to conform from IP team)
+ +  * As per the observation, in order to disable the cpsw clock/module
+ +  * from already enabled state, module level reset assertion is
+ +  * required; without reset the clock/module won't enter into
+ +  * idle state at all.
+ +  * Also, as per observation (have not conformed yet), we have to
+ +  * assert reset signal for all cpsw (4) submodules.
+ +  */
+ + 
+ + /* OCP SYSSTATUS bit shifts/masks */
+ + #define SOFT_RESETDONE_SHIFT		0
+ + #define SOFT_RESETDONE_MASK		(1 << SOFT_RESETDONE_SHIFT)
+ + 
+ + #define MAX_MODULE_SOFTRESET_WAIT	10000
+ + 
+ + static int am33xx_cpgmac_reset(struct omap_hwmod *oh)
+ + {
+ + 	int i;
+ + 	int ret = 0;
+ + 
+ + 	pr_debug("%s: resetting via Module SOFTRESET bit\n", oh->name);
+ + 
+ + 	for (i = 0; i < oh->slaves_cnt; i++) {
+ + 		int c = 0;
+ + 		void __iomem *va_start;
+ + 		struct omap_hwmod_ocp_if *os;
+ + 		struct omap_hwmod_addr_space *mem;
+ + 
+ + 		os = oh->slaves[i];
+ + 		/* FIXME: Only first instance's OCP_RST is asserted */
+ + 		mem = &os->addr[0];
+ + 
+ + 		va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
+ + 		if (!va_start) {
+ + 			pr_err("%s: Could not ioremap (%x)\n",
+ + 					oh->name, mem->pa_start);
+ + 			ret = -ENOMEM;
+ + 			break;
+ + 		}
+ + 		/* Assert reset signal */
+ + 		writel(1, va_start + oh->class->sysc->rst_offs);
+ + 		omap_test_timeout(((readl(va_start + oh->class->sysc->rst_offs)
+ + 					& SOFT_RESETDONE_MASK) == 0),
+ + 				MAX_MODULE_SOFTRESET_WAIT, c);
+ + 
+ + 		if (c == MAX_MODULE_SOFTRESET_WAIT) {
+ + 			pr_warning("%s: softreset failed (waited %d usec)\n",
+ + 					oh->name, MAX_MODULE_SOFTRESET_WAIT);
+ + 			ret = -ETIMEDOUT;
+ + 		}
+ + 	}
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /*
+ +  * Interconnects hwmod structures
+ +  * hwmods that compose the global AM33XX OCP interconnect
+ +  */
+ + 
+ + /* MPU -> L3_SLOW Peripheral interface */
+ + static struct omap_hwmod_ocp_if am33xx_mpu__l3_slow = {
+ + 	.master 	= &am33xx_mpu_hwmod,
+ + 	.slave		= &am33xx_l3slow_hwmod,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + /* L3 SLOW -> L4_PER Peripheral interface */
+ + static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_per = {
+ + 	.master 	= &am33xx_l3slow_hwmod,
+ + 	.slave		= &am33xx_l4per_hwmod,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + /* L3 SLOW -> L4_WKUP Peripheral interface */
+ + static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_wkup = {
+ + 	.master 	= &am33xx_l3slow_hwmod,
+ + 	.slave		= &am33xx_l4wkup_hwmod,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + /* Master interfaces on the L4_WKUP interconnect */
+ + static struct omap_hwmod_ocp_if *am33xx_l3_slow_masters[] = {
+ + 	&am33xx_l3_slow__l4_per,
+ + 	&am33xx_l3_slow__l4_wkup,
+ + };
+ + 
+ + /* Slave interfaces on the L3_SLOW interconnect */
+ + static struct omap_hwmod_ocp_if *am33xx_l3_slow_slaves[] = {
+ + 	&am33xx_mpu__l3_slow,
+ + };
+ + 
+ + static struct omap_hwmod am33xx_l3slow_hwmod = {
+ + 	.name		= "l3_slow",
+ + 	.class		= &l3_hwmod_class,
+ + 	.clkdm_name	= "l3s_clkdm",
+ + 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ + 	.masters	= am33xx_l3_slow_masters,
+ + 	.masters_cnt	= ARRAY_SIZE(am33xx_l3_slow_masters),
+ + 	.slaves		= am33xx_l3_slow_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_l3_slow_slaves),
+ + };
+ + 
+ + /* L4 PER -> DCAN0 */
+ + static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = {
+ + 	{
+ + 		.pa_start	= 0x481CC000,
+ + 		.pa_end		= 0x481CC000 + SZ_4K - 1,
+ + 		.flags		= ADDR_TYPE_RT
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
+ + 	.master		= &am33xx_l4per_hwmod,
+ + 	.slave		= &am33xx_dcan0_hwmod,
+ + 	.clk		= "dcan0_ick",
+ + 	.addr		= am33xx_dcan0_addrs,
+ + 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+ + };
+ + 
+ + /* L4 PER -> DCAN1 */
+ + static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = {
+ + 	{
+ + 		.pa_start	= 0x481D0000,
+ + 		.pa_end		= 0x481D0000 + SZ_4K - 1,
+ + 		.flags		= ADDR_TYPE_RT
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
+ + 	.master		= &am33xx_l4per_hwmod,
+ + 	.slave		= &am33xx_dcan1_hwmod,
+ + 	.clk		= "dcan1_ick",
+ + 	.addr		= am33xx_dcan1_addrs,
+ + 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+ + };
+ + 
+ + /* L4 PER -> GPIO2 */
+ + static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
+ + 	{
+ + 		.pa_start	= 0x4804C000,
+ + 		.pa_end		= 0x4804C000 + SZ_4K - 1,
+ + 		.flags		= ADDR_TYPE_RT,
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
+ + 	.master		= &am33xx_l4per_hwmod,
+ + 	.slave		= &am33xx_gpio1_hwmod,
+ + 	.clk		= "l4ls_gclk",
+ + 	.addr		= am33xx_gpio1_addrs,
+ + 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+ + };
+ + 
+ + /* L4 PER -> GPIO3 */
+ + static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
+ + 	{
+ + 		.pa_start	= 0x481AC000,
+ + 		.pa_end		= 0x481AC000 + SZ_4K - 1,
+ + 		.flags		= ADDR_TYPE_RT,
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
+ + 	.master		= &am33xx_l4per_hwmod,
+ + 	.slave		= &am33xx_gpio2_hwmod,
+ + 	.clk		= "l4ls_gclk",
+ + 	.addr		= am33xx_gpio2_addrs,
+ + 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+ + };
+ + 
+ + /* L4 PER -> GPIO4 */
+ + static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
+ + 	{
+ + 		.pa_start	= 0x481AE000,
+ + 		.pa_end		= 0x481AE000 + SZ_4K - 1,
+ + 		.flags		= ADDR_TYPE_RT,
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
+ + 	.master		= &am33xx_l4per_hwmod,
+ + 	.slave		= &am33xx_gpio3_hwmod,
+ + 	.clk		= "l4ls_gclk",
+ + 	.addr		= am33xx_gpio3_addrs,
+ + 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+ + };
+ + 
+ + /* Master interfaces on the L4_PER interconnect */
+ + static struct omap_hwmod_ocp_if *am33xx_l4_per_masters[] = {
+ + 	&am33xx_l4_per__dcan0,
+ + 	&am33xx_l4_per__dcan1,
+ + 	&am33xx_l4_per__gpio1,
+ + 	&am33xx_l4_per__gpio2,
+ + 	&am33xx_l4_per__gpio3,
+ + };
+ + 
+ + /* Slave interfaces on the L4_PER interconnect */
+ + static struct omap_hwmod_ocp_if *am33xx_l4_per_slaves[] = {
+ + 	&am33xx_l3_slow__l4_per,
+ + };
+ + 
+ + static struct omap_hwmod am33xx_l4per_hwmod = {
+ + 	.name		= "l4_per",
+ + 	.class		= &l4_hwmod_class,
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ + 	.masters	= am33xx_l4_per_masters,
+ + 	.masters_cnt	= ARRAY_SIZE(am33xx_l4_per_masters),
+ + 	.slaves		= am33xx_l4_per_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_l4_per_slaves),
+ + };
+ + 
+ + /* L4 WKUP -> I2C1 */
+ + static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
+ + 	{
+ + 		.pa_start	= 0x44E0B000,
+ + 		.pa_end		= 0x44E0B000 + SZ_4K - 1,
+ + 		.flags		= ADDR_TYPE_RT,
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if am33xx_l4_wkup_i2c1 = {
+ + 	.master		= &am33xx_l4wkup_hwmod,
+ + 	.slave		= &am33xx_i2c1_hwmod,
+ + 	.addr		= am33xx_i2c1_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + /* L4 WKUP -> GPIO1 */
+ + static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
+ + 	{
+ + 		.pa_start	= 0x44E07000,
+ + 		.pa_end		= 0x44E07000 + SZ_4K - 1,
+ + 		.flags		= ADDR_TYPE_RT,
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
+ + 	.master		= &am33xx_l4wkup_hwmod,
+ + 	.slave		= &am33xx_gpio0_hwmod,
+ + 	.clk		= "l4ls_gclk",
+ + 	.addr		= am33xx_gpio0_addrs,
+ + 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+ + };
+ + 
+ + /* Master interfaces on the L4_WKUP interconnect */
+ + static struct omap_hwmod_ocp_if *am33xx_l4_wkup_masters[] = {
+ + 	&am33xx_l4_wkup__gpio0,
+ + };
+ + /* Slave interfaces on the L4_WKUP interconnect */
+ + static struct omap_hwmod_ocp_if *am33xx_l4_wkup_slaves[] = {
+ + 	&am33xx_l3_slow__l4_wkup,
+ + };
+ + 
+ + static struct omap_hwmod am33xx_l4wkup_hwmod = {
+ + 	.name		= "l4_wkup",
+ + 	.class		= &l4_hwmod_class,
+ + 	.clkdm_name	= "l4_wkup_clkdm",
+ + 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ + 	.masters	= am33xx_l4_wkup_masters,
+ + 	.masters_cnt	= ARRAY_SIZE(am33xx_l4_wkup_masters),
+ + 	.slaves		= am33xx_l4_wkup_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_l4_wkup_slaves),
+ + };
+ + 
+ + /* adc_tsc */
+ + static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
+ + 	.rev_offs	= 0x00,
+ + 	.sysc_offs	= 0x10,
+ + 	.sysc_flags	= SYSC_HAS_SIDLEMODE,
+ + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ + 			SIDLE_SMART_WKUP),
+ + 	.sysc_fields	= &omap_hwmod_sysc_type2,
+ + };
+ + 
+ + static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
+ + 	.name		= "adc_tsc",
+ + 	.sysc		= &am33xx_adc_tsc_sysc,
+ + };
+ + 
+ + /* L4 WKUP -> ADC_TSC */
+ + static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
+ + 	{
+ + 		.pa_start	= 0x44E0D000,
+ + 		.pa_end		= 0x44E0D000 + SZ_8K - 1,
+ + 		.flags		= ADDR_TYPE_RT
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if am33xx_l4_wkup_adc_tsc = {
+ + 	.master		= &am33xx_l4wkup_hwmod,
+ + 	.slave		= &am33xx_adc_tsc_hwmod,
+ + 	.clk		= "adc_tsc_ick",
+ + 	.addr		= am33xx_adc_tsc_addrs,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_adc_tsc_slaves[] = {
+ + 	&am33xx_l4_wkup_adc_tsc,
+ + };
+ + 
+ + static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
+ + 	{ .irq = 16 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod am33xx_adc_tsc_hwmod = {
+ + 	.name		= "adc_tsc",
+ + 	.class		= &am33xx_adc_tsc_hwmod_class,
+ + 	.clkdm_name	= "l4_wkup_clkdm",
+ + 	.mpu_irqs	= am33xx_adc_tsc_irqs,
+ + 	.main_clk	= "adc_tsc_fck",
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.slaves		= am33xx_adc_tsc_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_adc_tsc_slaves),
+ + };
+ + 
+ + /* 'aes' class */
+ + static struct omap_hwmod_class_sysconfig am33xx_aes_sysc = {
+ + 	.rev_offs	= 0x80,
+ + 	.sysc_offs	= 0x84,
+ + 	.syss_offs	= 0x88,
+ + 	.sysc_flags	= SYSS_HAS_RESET_STATUS,
+ + };
+ + 
+ + static struct omap_hwmod_class am33xx_aes_hwmod_class = {
+ + 	.name		= "aes",
+ + 	.sysc		= &am33xx_aes_sysc,
+ + };
+ + 
+ + /* aes0 */
+ + static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
+ + 	{ .irq = 102 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod_dma_info am33xx_aes0_dma[] = {
+ + 	{ .dma_req = AM33XX_DMA_AESEIP36T0_DOUT },
+ + 	{ .dma_req = AM33XX_DMA_AESEIP36T0_DIN },
+ + 	{ .dma_req = -1 }
+ + };
+ + 
+ + static struct omap_hwmod_addr_space am33xx_aes0_addrs[] = {
+ + 	{
+ + 		.pa_start	= 0x53500000,
+ + 		.pa_end		= 0x53500000 + SZ_1M - 1,
+ + 		.flags		= ADDR_TYPE_RT
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
+ + 	.master		= &am33xx_l3_main_hwmod,
+ + 	.slave		= &am33xx_aes0_hwmod,
+ + 	.clk		= "aes0_fck",
+ + 	.addr		= am33xx_aes0_addrs,
+ + 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_aes0_slaves[] = {
+ + 	&am33xx_l3_main__aes0,
+ + };
+ + 
+ + static struct omap_hwmod am33xx_aes0_hwmod = {
+ + 	.name		= "aes0",
+ + 	.class		= &am33xx_aes_hwmod_class,
+ + 	.clkdm_name	= "l3_clkdm",
+ + 	.mpu_irqs	= am33xx_aes0_irqs,
+ + 	.sdma_reqs	= am33xx_aes0_dma,
+ + 	.main_clk	= "aes0_fck",
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.slaves		= am33xx_aes0_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_aes0_slaves),
+ + };
+ + 
+ + /* cefuse */
+ + static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
+ + 	.name		= "cefuse",
+ + };
+ + 
+ + static struct omap_hwmod am33xx_cefuse_hwmod = {
+ + 	.name		= "cefuse",
+ + 	.class		= &am33xx_cefuse_hwmod_class,
+ + 	.clkdm_name	= "l4_cefuse_clkdm",
+ + 	.main_clk	= "cefuse_fck",
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + };
+ + 
+ + /* clkdiv32k */
+ + static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
+ + 	.name		= "clkdiv32k",
+ + };
+ + 
+ + static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
+ + 	.name		= "clkdiv32k",
+ + 	.class		= &am33xx_clkdiv32k_hwmod_class,
+ + 	.clkdm_name	= "clk_24mhz_clkdm",
+ + 	.main_clk	= "clkdiv32k_ick",
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ + };
+ + 
+ + /* control */
+ + static struct omap_hwmod_class am33xx_control_hwmod_class = {
+ + 	.name		= "control",
+ + };
+ + 
+ + static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
+ + 	{ .irq = 8 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod am33xx_control_hwmod = {
+ + 	.name		= "control",
+ + 	.class		= &am33xx_control_hwmod_class,
+ + 	.clkdm_name	= "l4_wkup_clkdm",
+ + 	.mpu_irqs	= am33xx_control_irqs,
+ + 	.main_clk	= "control_fck",
+ + 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + };
+ + 
+ + /* cpgmac0 */
+ + static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
+ + 	.rev_offs	= 0x0,
+ + 	.sysc_offs	= 0x8,
+ + 	.syss_offs	= 0x4,
+ + 	.rst_offs	= 0x8,
+ + 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
+ + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
+ + 			MSTANDBY_NO),
+ + 	.sysc_fields	= &omap_hwmod_sysc_type3,
+ + };
+ + 
+ + static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
+ + 	.name		= "cpsw",
+ + 	.sysc		= &am33xx_cpgmac_sysc,
+ + 	.reset		= am33xx_cpgmac_reset,
+ + };
+ + 
+ + /* Used by driver */
+ + struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
+ + 	/* cpsw ss */
+ + 	{
+ + 		.pa_start	= 0x4A100000,
+ + 		.pa_end		= 0x4A100000 + SZ_2K - 1,
+ + 		.flags		= ADDR_MAP_ON_INIT,
+ + 	},
+ + 	/* cpsw wr */
+ + 	{
+ + 		.pa_start	= 0x4A101200,
+ + 		.pa_end		= 0x4A101200 + SZ_256 - 1,
+ + 		.flags		= ADDR_TYPE_RT,
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + struct omap_hwmod_ocp_if am33xx_l3_main__cpgmac0 = {
+ + 	.master		= &am33xx_l3_main_hwmod,
+ + 	.slave		= &am33xx_cpgmac0_hwmod,
+ + 	.addr		= am33xx_cpgmac0_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + struct omap_hwmod_addr_space am33xx_cpsw_sl1_addr_space[] = {
+ + 	/* cpsw sl1 */
+ + 	{
+ + 		.pa_start	= 0x4A100D84,
+ + 		.pa_end		= 0x4A100D84 + SZ_32 - 1,
+ + 		.flags		= ADDR_TYPE_RT,
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + struct omap_hwmod_ocp_if am33xx_l3_main__cpsw_sl1 = {
+ + 	.master		= &am33xx_l3_main_hwmod,
+ + 	.slave		= &am33xx_cpgmac0_hwmod,
+ + 	.addr		= am33xx_cpsw_sl1_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + struct omap_hwmod_addr_space am33xx_cpsw_sl2_addr_space[] = {
+ + 	/* cpsw sl2 */
+ + 	{
+ + 		.pa_start	= 0x4A100DC4,
+ + 		.pa_end		= 0x4A100DC4 + SZ_32 - 1,
+ + 		.flags		= ADDR_TYPE_RT,
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + struct omap_hwmod_ocp_if am33xx_l3_main__cpsw_sl2 = {
+ + 	.master		= &am33xx_l3_main_hwmod,
+ + 	.slave		= &am33xx_cpgmac0_hwmod,
+ + 	.addr		= am33xx_cpsw_sl2_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + struct omap_hwmod_addr_space am33xx_cpsw_cpdma_addr_space[] = {
+ + 	/* cpsw cpdma */
+ + 	{
+ + 		.pa_start	= 0x4A100814,
+ + 		.pa_end		= 0x4A100814 + SZ_32 - 1,
+ + 		.flags		= ADDR_TYPE_RT,
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + struct omap_hwmod_ocp_if am33xx_l3_main__cpsw_cpdma = {
+ + 	.master		= &am33xx_l3_main_hwmod,
+ + 	.slave		= &am33xx_cpgmac0_hwmod,
+ + 	.addr		= am33xx_cpsw_cpdma_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_cpgmac0_slaves[] = {
+ + 	&am33xx_l3_main__cpgmac0,
+ + 	&am33xx_l3_main__cpsw_sl1,
+ + 	&am33xx_l3_main__cpsw_sl2,
+ + 	&am33xx_l3_main__cpsw_cpdma,
+ + };
+ + 
+ + static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
+ + 	{ .name = "c0_rx_thresh_pend", .irq = 40 },
+ + 	{ .name = "c0_rx_pend", .irq = 93 },
+ + 	{ .name = "c0_tx_pend", .irq = 94 },
+ + 	{ .name = "c0_misc_pend", .irq = 43 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod am33xx_cpgmac0_hwmod = {
+ + 	.name		= "cpgmac0",
+ + 	.class		= &am33xx_cpgmac0_hwmod_class,
+ + 	.clkdm_name	= "cpsw_125mhz_clkdm",
+ + 	.mpu_irqs	= am33xx_cpgmac0_irqs,
+ + 	.main_clk	= "cpgmac0_ick",
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.slaves		= am33xx_cpgmac0_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_cpgmac0_slaves),
+ + 	.flags		= (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
+ + 				HWMOD_SWSUP_RESET_BEFORE_IDLE),
+ + };
+ + 
+ + /* mdio class */
+ + static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
+ + 	.name		= "davinci_mdio",
+ + };
+ + 
+ + struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
+ + 	{
+ + 		.pa_start	= 0x4A101000,
+ + 		.pa_end		= 0x4A101000 + SZ_256 - 1,
+ + 		.flags		= ADDR_MAP_ON_INIT,
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
+ + 	.master		= &am33xx_cpgmac0_hwmod,
+ + 	.slave		= &am33xx_mdio_hwmod,
+ + 	.addr		= am33xx_mdio_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_mdio_slaves[] = {
+ + 	&am33xx_cpgmac0__mdio,
+ + };
+ + 
+ + static struct omap_hwmod am33xx_mdio_hwmod = {
+ + 	.name		= "mdio",
+ + 	.class		= &am33xx_mdio_hwmod_class,
+ + 	.clkdm_name	= "cpsw_125mhz_clkdm",
+ + 	.main_clk	= "cpgmac0_ick",
+ + 	.slaves		= am33xx_mdio_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_mdio_slaves),
+ + };
+ + 
+ + /* 'dcan' class */
+ + static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
+ + 	.name		= "d_can",
+ + };
+ + 
+ + /* dcan0 slave ports */
+ + static struct omap_hwmod_ocp_if *am33xx_dcan0_slaves[] = {
+ + 	&am33xx_l4_per__dcan0,
+ + };
+ + 
+ + /* dcan0 */
+ + static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
+ + 	{ .name = "d_can_ms", .irq = 52 },
+ + 	{ .name = "d_can_mo", .irq = 53 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod am33xx_dcan0_hwmod = {
+ + 	.name		= "d_can0",
+ + 	.class		= &am33xx_dcan_hwmod_class,
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.mpu_irqs	= am33xx_dcan0_irqs,
+ + 	.main_clk	= "dcan0_fck",
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.slaves		= am33xx_dcan0_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_dcan0_slaves),
+ + };
+ + 
+ + /* dcan1 slave ports */
+ + static struct omap_hwmod_ocp_if *am33xx_dcan1_slaves[] = {
+ + 	&am33xx_l4_per__dcan1,
+ + };
+ + 
+ + /* dcan1 */
+ + static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
+ + 	{ .name = "d_can_ms", .irq = 55 },
+ + 	{ .name = "d_can_mo", .irq = 56 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod am33xx_dcan1_hwmod = {
+ + 	.name		= "d_can1",
+ + 	.class		= &am33xx_dcan_hwmod_class,
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.mpu_irqs	= am33xx_dcan1_irqs,
+ + 	.main_clk	= "dcan1_fck",
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.slaves		= am33xx_dcan1_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_dcan1_slaves),
+ + };
+ + 
+ + /* debugss */
+ + static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
+ + 	.name		= "debugss",
+ + };
+ + 
+ + static struct omap_hwmod am33xx_debugss_hwmod = {
+ + 	.name		= "debugss",
+ + 	.class		= &am33xx_debugss_hwmod_class,
+ + 	.clkdm_name	= "l3_aon_clkdm",
+ + 	.main_clk	= "debugss_ick",
+ + #ifdef CONFIG_DEBUG_JTAG_ENABLE
+ + 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ + #endif
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + };
+ + 
+ + /* elm */
+ + static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
+ + 	.rev_offs	= 0x0000,
+ + 	.sysc_offs	= 0x0010,
+ + 	.syss_offs	= 0x0014,
+ + 	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ + 			SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+ + 			SYSS_HAS_RESET_STATUS),
+ + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ + 	.sysc_fields	= &omap_hwmod_sysc_type1,
+ + };
+ + 
+ + static struct omap_hwmod_class am33xx_elm_hwmod_class = {
+ + 	.name		= "elm",
+ + 	.sysc		= &am33xx_elm_sysc,
+ + };
+ + 
+ + static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
+ + 	{ .irq = 4 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
+ + 	{
+ + 		.pa_start	= 0x48080000,
+ + 		.pa_end		= 0x48080000 + SZ_8K - 1,
+ + 		.flags		= ADDR_TYPE_RT
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + struct omap_hwmod_ocp_if am33xx_l4_core__elm = {
+ + 	.master		= &am33xx_l4per_hwmod,
+ + 	.slave		= &am33xx_elm_hwmod,
+ + 	.addr		= am33xx_elm_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_elm_slaves[] = {
+ + 	&am33xx_l4_core__elm,
+ + };
+ + 
+ + static struct omap_hwmod am33xx_elm_hwmod = {
+ + 	.name		= "elm",
+ + 	.class		= &am33xx_elm_hwmod_class,
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.mpu_irqs	= am33xx_elm_irqs,
+ + 	.main_clk	= "elm_fck",
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.slaves		= am33xx_elm_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_elm_slaves),
+ + };
+ + 
+ + /* emif_fw */
+ + static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
+ + 	.name		= "emif_fw",
+ + };
+ + 
+ + static struct omap_hwmod am33xx_emif_fw_hwmod = {
+ + 	.name		= "emif_fw",
+ + 	.class		= &am33xx_emif_fw_hwmod_class,
+ + 	.clkdm_name	= "l4fw_clkdm",
+ + 	.main_clk	= "emif_fw_fck",
+ + 	.flags		= HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + };
+ + 
+ + /* 'epwmss' class */
+ + static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
+ + 	.rev_offs	= 0x0,
+ + 	.sysc_offs	= 0x4,
+ + 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
+ + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ + 			SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+ + 			MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+ + 	.sysc_fields	= &omap_hwmod_sysc_type2,
+ + };
+ + 
+ + static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
+ + 	.name		= "epwmss",
+ + 	.sysc		= &am33xx_epwmss_sysc,
+ + };
+ + 
+ + /* ehrpwm0 */
+ + static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
+ + 	{ .irq		= 86 },
+ + 	{ .irq		= 58 },
+ + 	{ .irq		= -1 }
+ + };
+ + 
+ + struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
+ + /*
+ +  * Splitting the resources to handle access of PWMSS config space and module
+ +  * specific part independently
+ +  */
+ + 	{
+ + 		.pa_start	= 0x48300000,
+ + 		.pa_end		= 0x48300000 + SZ_16 - 1,
+ + 		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT
+ + 	},
+ + 	{
+ + 		.pa_start	= 0x48300000 + SZ_512,
+ + 		.pa_end		= 0x48300000 + SZ_512 + SZ_256 - 1,
+ + 		.flags		= ADDR_TYPE_RT
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + struct omap_hwmod_ocp_if am33xx_l4_core__ehrpwm0 = {
+ + 	.master		= &am33xx_l4per_hwmod,
+ + 	.slave		= &am33xx_ehrpwm0_hwmod,
+ + 	.addr		= am33xx_ehrpwm0_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_ehrpwm0_slaves[] = {
+ + 	&am33xx_l4_core__ehrpwm0,
+ + };
+ + 
+ + static struct omap_hwmod_opt_clk ehrpwm0_opt_clks[] = {
+ + 	{ .role = "tbclk", .clk = "ehrpwm0_tbclk" },
+ + };
+ + 
+ + static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
+ + 	.name		= "ehrpwm.0",
+ + 	.mpu_irqs	= am33xx_ehrpwm0_irqs,
+ + 	.class		= &am33xx_epwmss_hwmod_class,
+ + 	.main_clk	= "epwmss0_fck",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.slaves		= am33xx_ehrpwm0_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_ehrpwm0_slaves),
+ + 	.opt_clks	= ehrpwm0_opt_clks,
+ + 	.opt_clks_cnt	= ARRAY_SIZE(ehrpwm0_opt_clks),
+ + };
+ + 
+ + /* ehrpwm1 */
+ + static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
+ + 	{ .irq		= 87 },
+ + 	{ .irq		= 59 },
+ + 	{ .irq		= -1 }
+ + };
+ + 
+ + struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
+ + /*
+ +  * Splitting the resources to handle access of PWMSS config space and module
+ +  * specific part independently
+ +  */
+ + 	{
+ + 		.pa_start	= 0x48302000,
+ + 		.pa_end		= 0x48302000 + SZ_16 - 1,
+ + 		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT
+ + 	},
+ + 	{
+ + 		.pa_start	= 0x48302000 + SZ_512,
+ + 		.pa_end		= 0x48302000 + SZ_512 + SZ_256 - 1,
+ + 		.flags		= ADDR_TYPE_RT
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + struct omap_hwmod_ocp_if am33xx_l4_core__ehrpwm1 = {
+ + 	.master		= &am33xx_l4per_hwmod,
+ + 	.slave		= &am33xx_ehrpwm1_hwmod,
+ + 	.addr		= am33xx_ehrpwm1_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_ehrpwm1_slaves[] = {
+ + 	&am33xx_l4_core__ehrpwm1,
+ + };
+ + 
+ + static struct omap_hwmod_opt_clk ehrpwm1_opt_clks[] = {
+ + 	{ .role = "tbclk", .clk = "ehrpwm1_tbclk" },
+ + };
+ + 
+ + static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
+ + 	.name		= "ehrpwm.1",
+ + 	.mpu_irqs	= am33xx_ehrpwm1_irqs,
+ + 	.class		= &am33xx_epwmss_hwmod_class,
+ + 	.main_clk	= "epwmss1_fck",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.slaves		= am33xx_ehrpwm1_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_ehrpwm1_slaves),
+ + 	.opt_clks	= ehrpwm1_opt_clks,
+ + 	.opt_clks_cnt	= ARRAY_SIZE(ehrpwm1_opt_clks),
+ + };
+ + 
+ + /* ehrpwm2 */
+ + static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
+ + 	{ .irq		= 39 },
+ + 	{ .irq		= 60 },
+ + 	{ .irq		= -1 }
+ + };
+ + 
+ + struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
+ + /*
+ +  * Splitting the resources to handle access of PWMSS config space and module
+ +  * specific part independently
+ +  */
+ + 	{
+ + 		.pa_start	= 0x48304000,
+ + 		.pa_end		= 0x48304000 + SZ_16 - 1,
+ + 		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT
+ + 	},
+ + 	{
+ + 		.pa_start	= 0x48304000 + SZ_512,
+ + 		.pa_end		= 0x48304000 + SZ_512 + SZ_256 - 1,
+ + 		.flags		= ADDR_TYPE_RT
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + struct omap_hwmod_ocp_if am33xx_l4_core__ehrpwm2 = {
+ + 	.master		= &am33xx_l4per_hwmod,
+ + 	.slave		= &am33xx_ehrpwm2_hwmod,
+ + 	.addr		= am33xx_ehrpwm2_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_ehrpwm2_slaves[] = {
+ + 	&am33xx_l4_core__ehrpwm2,
+ + };
+ + 
+ + static struct omap_hwmod_opt_clk ehrpwm2_opt_clks[] = {
+ + 	{ .role = "tbclk", .clk = "ehrpwm2_tbclk" },
+ + };
+ + 
+ + static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
+ + 	.name		= "ehrpwm.2",
+ + 	.mpu_irqs	= am33xx_ehrpwm2_irqs,
+ + 	.class		= &am33xx_epwmss_hwmod_class,
+ + 	.main_clk	= "epwmss2_fck",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.slaves		= am33xx_ehrpwm2_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_ehrpwm2_slaves),
+ + 	.opt_clks	= ehrpwm2_opt_clks,
+ + 	.opt_clks_cnt	= ARRAY_SIZE(ehrpwm2_opt_clks),
+ + };
+ + 
+ + /* ecap0 */
+ + static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
+ + 	{ .irq		= 31 },
+ + 	{ .irq		= -1 }
+ + };
+ + 
+ + struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
+ + /*
+ +  * Splitting the resources to handle access of PWMSS config space and module
+ +  * specific part independently
+ +  */
+ + 	{
+ + 		.pa_start	= 0x48300000,
+ + 		.pa_end		= 0x48300000 + SZ_16 - 1,
+ + 		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT
+ + 	},
+ + 	{
+ + 		.pa_start	= 0x48300000 + SZ_256,
+ + 		.pa_end		= 0x48300000 + SZ_256 + SZ_256 - 1,
+ + 		.flags		= ADDR_TYPE_RT
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + struct omap_hwmod_ocp_if am33xx_l4_core__ecap0 = {
+ + 	.master		= &am33xx_l4per_hwmod,
+ + 	.slave		= &am33xx_ecap0_hwmod,
+ + 	.addr		= am33xx_ecap0_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_ecap0_slaves[] = {
+ + 	&am33xx_l4_core__ecap0,
+ + };
+ + 
+ + static struct omap_hwmod am33xx_ecap0_hwmod = {
+ + 	.name		= "ecap.0",
+ + 	.mpu_irqs	= am33xx_ecap0_irqs,
+ + 	.class		= &am33xx_epwmss_hwmod_class,
+ + 	.main_clk	= "epwmss0_fck",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.slaves		= am33xx_ecap0_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_ecap0_slaves),
+ + };
+ + 
+ + /* ecap1 */
+ + static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
+ + 	{ .irq		= 47 },
+ + 	{ .irq		= -1 }
+ + };
+ + 
+ + struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
+ + /*
+ +  * Splitting the resources to handle access of PWMSS config space and module
+ +  * specific part independently
+ +  */
+ + 	{
+ + 		.pa_start	= 0x48302000,
+ + 		.pa_end		= 0x48302000 + SZ_16 - 1,
+ + 		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT
+ + 	},
+ + 	{
+ + 		.pa_start	= 0x48302000 + SZ_256,
+ + 		.pa_end		= 0x48302000 + SZ_256 + SZ_256 - 1,
+ + 		.flags		= ADDR_TYPE_RT
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + struct omap_hwmod_ocp_if am33xx_l4_core__ecap1 = {
+ + 	.master		= &am33xx_l4per_hwmod,
+ + 	.slave		= &am33xx_ecap1_hwmod,
+ + 	.addr		= am33xx_ecap1_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_ecap1_slaves[] = {
+ + 	&am33xx_l4_core__ecap1,
+ + };
+ + 
+ + static struct omap_hwmod am33xx_ecap1_hwmod = {
+ + 	.name		= "ecap.1",
+ + 	.mpu_irqs	= am33xx_ecap1_irqs,
+ + 	.class		= &am33xx_epwmss_hwmod_class,
+ + 	.main_clk	= "epwmss1_fck",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.slaves		= am33xx_ecap1_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_ecap1_slaves),
+ + };
+ + 
+ + /* ecap2 */
+ + static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
+ + 	{ .irq		= 61 },
+ + 	{ .irq		= -1 }
+ + };
+ + 
+ + struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
+ + /*
+ +  * Splitting the resources to handle access of PWMSS config space and module
+ +  * specific part independently
+ +  */
+ + 	{
+ + 		.pa_start	= 0x48304000,
+ + 		.pa_end		= 0x48304000 + SZ_16 - 1,
+ + 		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT
+ + 	},
+ + 	{
+ + 		.pa_start	= 0x48304000 + SZ_256,
+ + 		.pa_end		= 0x48304000 + SZ_256 + SZ_256 - 1,
+ + 		.flags		= ADDR_TYPE_RT
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + struct omap_hwmod_ocp_if am33xx_l4_core__ecap2 = {
+ + 	.master		= &am33xx_l4per_hwmod,
+ + 	.slave		= &am33xx_ecap2_hwmod,
+ + 	.addr		= am33xx_ecap2_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_ecap2_slaves[] = {
+ + 	&am33xx_l4_core__ecap2,
+ + };
+ + 
+ + static struct omap_hwmod am33xx_ecap2_hwmod = {
+ + 	.name		= "ecap.2",
+ + 	.mpu_irqs	= am33xx_ecap2_irqs,
+ + 	.class		= &am33xx_epwmss_hwmod_class,
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.main_clk	= "epwmss2_fck",
+ + 	.slaves		= am33xx_ecap2_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_ecap2_slaves),
+ + };
+ + 
+ + static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
+ + 	.rev_offs	= 0x0000,
+ + 	.sysc_offs	= 0x0010,
+ + 	.syss_offs	= 0x0114,
+ + 	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
+ + 			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ + 			   SYSS_HAS_RESET_STATUS),
+ + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ + 			SIDLE_SMART_WKUP),
+ + 	.sysc_fields	= &omap_hwmod_sysc_type1,
+ + };
+ + 
+ + /* 'gpio' class */
+ + static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
+ + 	.name		= "gpio",
+ + 	.sysc		= &am33xx_gpio_sysc,
+ + 	.rev		= 2,
+ + };
+ + 
+ + static struct omap_gpio_dev_attr gpio_dev_attr = {
+ + 	.bank_width	= 32,
+ + 	.dbck_flag	= true,
+ + };
+ + 
+ + /* gpio0 */
+ + static struct omap_hwmod_ocp_if *am33xx_gpio0_slaves[] = {
+ + 	&am33xx_l4_wkup__gpio0,
+ + };
+ + 
+ + static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
+ + 	{ .role = "dbclk", .clk = "gpio0_dbclk" },
+ + };
+ + 
+ + static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
+ + 	{ .irq = 96 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod am33xx_gpio0_hwmod = {
+ + 	.name		= "gpio1",
+ + 	.class		= &am33xx_gpio_hwmod_class,
+ + 	.clkdm_name	= "l4_wkup_clkdm",
+ + 	.mpu_irqs	= am33xx_gpio0_irqs,
+ + 	.main_clk	= "gpio0_ick",
+ + 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET | HWMOD_INIT_NO_RESET,
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.opt_clks	= gpio0_opt_clks,
+ + 	.opt_clks_cnt	= ARRAY_SIZE(gpio0_opt_clks),
+ + 	.dev_attr	= &gpio_dev_attr,
+ + 	.slaves		= am33xx_gpio0_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_gpio0_slaves),
+ + };
+ + 
+ + /* gpio1 */
+ + static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
+ + 	{ .irq = 98 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_gpio1_slaves[] = {
+ + 	&am33xx_l4_per__gpio1,
+ + };
+ + 
+ + static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
+ + 	{ .role = "dbclk", .clk = "gpio1_dbclk" },
+ + };
+ + 
+ + static struct omap_hwmod am33xx_gpio1_hwmod = {
+ + 	.name		= "gpio2",
+ + 	.class		= &am33xx_gpio_hwmod_class,
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.mpu_irqs	= am33xx_gpio1_irqs,
+ + 	.main_clk	= "gpio1_ick",
+ + 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.opt_clks	= gpio1_opt_clks,
+ + 	.opt_clks_cnt	= ARRAY_SIZE(gpio1_opt_clks),
+ + 	.dev_attr	= &gpio_dev_attr,
+ + 	.slaves		= am33xx_gpio1_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_gpio1_slaves),
+ + };
+ + 
+ + /* gpio2 */
+ + static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
+ + 	{ .irq = 32 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_gpio2_slaves[] = {
+ + 	&am33xx_l4_per__gpio2,
+ + };
+ + 
+ + static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
+ + 	{ .role = "dbclk", .clk = "gpio2_dbclk" },
+ + };
+ + 
+ + static struct omap_hwmod am33xx_gpio2_hwmod = {
+ + 	.name		= "gpio3",
+ + 	.class		= &am33xx_gpio_hwmod_class,
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.mpu_irqs	= am33xx_gpio2_irqs,
+ + 	.main_clk	= "gpio2_ick",
+ + 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.opt_clks	= gpio2_opt_clks,
+ + 	.opt_clks_cnt	= ARRAY_SIZE(gpio2_opt_clks),
+ + 	.dev_attr	= &gpio_dev_attr,
+ + 	.slaves		= am33xx_gpio2_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_gpio2_slaves),
+ + };
+ + 
+ + /* gpio3 */
+ + static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
+ + 	{ .irq = 62 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_gpio3_slaves[] = {
+ + 	&am33xx_l4_per__gpio3,
+ + };
+ + 
+ + static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
+ + 	{ .role = "dbclk", .clk = "gpio3_dbclk" },
+ + };
+ + 
+ + static struct omap_hwmod am33xx_gpio3_hwmod = {
+ + 	.name		= "gpio4",
+ + 	.class		= &am33xx_gpio_hwmod_class,
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.mpu_irqs	= am33xx_gpio3_irqs,
+ + 	.main_clk	= "gpio3_ick",
+ + #if defined(CONFIG_CKB_LCD_SUPPORT)
+ + 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET | HWMOD_INIT_NO_RESET, /* this is needed for backlight and LCD */
+ + #else
+ + 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ + #endif
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.opt_clks	= gpio3_opt_clks,
+ + 	.opt_clks_cnt	= ARRAY_SIZE(gpio3_opt_clks),
+ + 	.dev_attr	= &gpio_dev_attr,
+ + 	.slaves		= am33xx_gpio3_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_gpio3_slaves),
+ + };
+ + 
+ + /* gpmc */
+ + static struct omap_hwmod_class_sysconfig gpmc_sysc = {
+ + 	.rev_offs	= 0x0,
+ + 	.sysc_offs	= 0x10,
+ + 	.syss_offs	= 0x14,
+ + 	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+ + 			SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ + 	.sysc_fields	= &omap_hwmod_sysc_type1,
+ + };
+ + 
+ + static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
+ + 	.name		= "gpmc",
+ + 	.sysc		= &gpmc_sysc,
+ + };
+ + 
+ + struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
+ + 	{
+ + 		.pa_start	= 0x50000000,
+ + 		.pa_end		= 0x50000000 + SZ_8K - 1,
+ + 		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + struct omap_hwmod_ocp_if am33xx_l3_main__gpmc = {
+ + 	.master		= &am33xx_l3_main_hwmod,
+ + 	.slave		= &am33xx_gpmc_hwmod,
+ + 	.addr		= am33xx_gpmc_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_gpmc_slaves[] = {
+ + 	&am33xx_l3_main__gpmc,
+ + };
+ + 
+ + static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = {
+ + 	{ .irq = 100 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod am33xx_gpmc_hwmod = {
+ + 	.name		= "gpmc",
+ + 	.class		= &am33xx_gpmc_hwmod_class,
+ + 	.clkdm_name	= "l3s_clkdm",
+ + 	.mpu_irqs	= am33xx_gpmc_irqs,
+ + 	.main_clk	= "gpmc_fck",
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.slaves		= am33xx_gpmc_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_gpmc_slaves),
+ + 	.flags		= (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
+ + 				HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ + };
+ + 
+ + /* 'i2c' class */
+ + static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
+ + 	.sysc_offs	= 0x0010,
+ + 	.syss_offs	= 0x0090,
+ + 	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+ + 			SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+ + 			SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ + 			SIDLE_SMART_WKUP),
+ + 	.sysc_fields	= &omap_hwmod_sysc_type1,
+ + };
+ + 
+ + static struct omap_i2c_dev_attr i2c_dev_attr = {
+ + 	.flags		= OMAP_I2C_FLAG_BUS_SHIFT_NONE |
+ + 					OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
+ + };
+ + 
+ + static struct omap_hwmod_class i2c_class = {
+ + 	.name		= "i2c",
+ + 	.sysc		= &am33xx_i2c_sysc,
+ + 	.rev		= OMAP_I2C_IP_VERSION_2,
+ + 	.reset		= &omap_i2c_reset,
+ + };
+ + 
+ + /* I2C1 */
+ + static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
+ + 	{ .irq = 70 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
+ + 	{ .name = "tx", .dma_req = 0, },
+ + 	{ .name = "rx", .dma_req = 0, },
+ + 	{ .dma_req = -1 }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_i2c1_slaves[] = {
+ + 	&am33xx_l4_wkup_i2c1,
+ + };
+ + 
+ + static struct omap_hwmod am33xx_i2c1_hwmod = {
+ + 	.name		= "i2c1",
+ + 	.class		= &i2c_class,
+ + 	.clkdm_name	= "l4_wkup_clkdm",
+ + 	.mpu_irqs	= i2c1_mpu_irqs,
+ + 	.main_clk	= "i2c1_fck",
+ + 	.sdma_reqs	= i2c1_edma_reqs,
+ + 	.flags		= HWMOD_16BIT_REG,
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.dev_attr	= &i2c_dev_attr,
+ + 	.slaves		= am33xx_i2c1_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_i2c1_slaves),
+ + };
+ + 
+ + /* i2c2 */
+ + static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
+ + 	{
+ + 		.pa_start	= 0x4802A000,
+ + 		.pa_end		= 0x4802A000 + SZ_4K - 1,
+ + 		.flags		= ADDR_TYPE_RT,
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if am335_l4_per_i2c2 = {
+ + 	.master		= &am33xx_l4per_hwmod,
+ + 	.slave		= &am33xx_i2c2_hwmod,
+ + 	.addr		= am33xx_i2c2_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
+ + 	{ .irq = 71 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
+ + 	{ .name = "tx", .dma_req = 0, },
+ + 	{ .name = "rx", .dma_req = 0, },
+ + 	{ .dma_req = -1 }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_i2c2_slaves[] = {
+ + 	&am335_l4_per_i2c2,
+ + };
+ + 
+ + static struct omap_hwmod am33xx_i2c2_hwmod = {
+ + 	.name		= "i2c2",
+ + 	.class		= &i2c_class,
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.mpu_irqs	= i2c2_mpu_irqs,
+ + 	.main_clk	= "i2c2_fck",
+ + 	.sdma_reqs	= i2c2_edma_reqs,
+ + 	.flags		= HWMOD_16BIT_REG,
+ + 	.prcm		= {
+ + 		.omap4 = {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.dev_attr	= &i2c_dev_attr,
+ + 	.slaves		= am33xx_i2c2_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_i2c2_slaves),
+ + };
+ + 
+ + /* I2C3 */
+ + static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
+ + 	{
+ + 		.pa_start	= 0x4819C000,
+ + 		.pa_end		= 0x4819C000 + SZ_4K - 1,
+ + 		.flags		= ADDR_TYPE_RT
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if am335_l4_per_i2c3 = {
+ + 	.master		= &am33xx_l4per_hwmod,
+ + 	.slave		= &am33xx_i2c3_hwmod,
+ + 	.addr		= am33xx_i2c3_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_i2c3_slaves[] = {
+ + 	&am335_l4_per_i2c3,
+ + };
+ + 
+ + static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
+ + 	{ .name = "tx", .dma_req = 0, },
+ + 	{ .name = "rx", .dma_req = 0, },
+ + 	{ .dma_req = -1 }
+ + };
+ + 
+ + static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
+ + 	{ .irq = 30 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod am33xx_i2c3_hwmod = {
+ + 	.name		= "i2c3",
+ + 	.class		= &i2c_class,
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.mpu_irqs	= i2c3_mpu_irqs,
+ + 	.main_clk	= "i2c3_fck",
+ + 	.sdma_reqs	= i2c3_edma_reqs,
+ + 	.flags		= HWMOD_16BIT_REG,
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.dev_attr	= &i2c_dev_attr,
+ + 	.slaves		= am33xx_i2c3_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_i2c3_slaves),
+ + };
+ + 
+ + 
+ + /* ieee5000 */
+ + static struct omap_hwmod_class am33xx_ieee5000_hwmod_class = {
+ + 	.name		= "ieee5000",
+ + };
+ + 
+ + static struct omap_hwmod am33xx_ieee5000_hwmod = {
+ + 	.name		= "ieee5000",
+ + 	.class		= &am33xx_ieee5000_hwmod_class,
+ + 	.clkdm_name	= "l3s_clkdm",
+ + 	.main_clk	= "ieee5000_fck",
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + };
+ + 
+ + 
+ + /* 'l3' class */
+ + static struct omap_hwmod_class am33xx_l3_hwmod_class = {
+ + 	.name		= "l3",
+ + };
+ + 
+ + /* l4_hs */
+ + static struct omap_hwmod am33xx_l4_hs_hwmod = {
+ + 	.name		= "l4_hs",
+ + 	.class		= &am33xx_l3_hwmod_class,
+ + 	.clkdm_name	= "l4hs_clkdm",
+ + 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + };
+ + 
+ + /* l3_instr */
+ + static struct omap_hwmod am33xx_l3_instr_hwmod = {
+ + 	.name		= "l3_instr",
+ + 	.class		= &am33xx_l3_hwmod_class,
+ + 	.clkdm_name	= "l3_clkdm",
+ + 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + };
+ + 
+ + /* l3_main */
+ + static struct omap_hwmod am33xx_l3_main_hwmod = {
+ + 	.name		= "l3_main",
+ + 	.class		= &am33xx_l3_hwmod_class,
+ + 	.clkdm_name	= "l3_clkdm",
+ + 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + };
+ + 
+ + /* 'l4fw' class */
+ + static struct omap_hwmod_class am33xx_l4fw_hwmod_class = {
+ + 	.name		= "l4fw",
+ + };
+ + 
+ + /* l4fw */
+ + static struct omap_hwmod am33xx_l4fw_hwmod = {
+ + 	.name		= "l4fw",
+ + 	.class		= &am33xx_l4fw_hwmod_class,
+ + 	.clkdm_name	= "l4fw_clkdm",
+ + 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + };
+ + 
+ + /* 'l4ls' class */
+ + static struct omap_hwmod_class am33xx_l4ls_hwmod_class = {
+ + 	.name		= "l4ls",
+ + };
+ + 
+ + /* l4ls */
+ + static struct omap_hwmod am33xx_l4ls_hwmod = {
+ + 	.name		= "l4ls",
+ + 	.class		= &am33xx_l4ls_hwmod_class,
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.main_clk	= "l4ls_gclk",
+ + 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + };
+ + 
+ + /* lcdc */
+ + static struct omap_hwmod_class_sysconfig lcdc_sysc = {
+ + 	.rev_offs	= 0x0,
+ + 	.sysc_offs	= 0x54,
+ + 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
+ + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ + 	.sysc_fields	= &omap_hwmod_sysc_type2,
+ + };
+ + 
+ + static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
+ + 	.name		= "lcdc",
+ + 	.sysc		= &lcdc_sysc,
+ + };
+ + 
+ + static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
+ + 	{ .irq = 36 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
+ + 	{
+ + 		.pa_start	= 0x4830E000,
+ + 		.pa_end		= 0x4830E000 + SZ_8K - 1,
+ + 		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
+ + 	.master		= &am33xx_l3_main_hwmod,
+ + 	.slave		= &am33xx_lcdc_hwmod,
+ + 	.addr		= am33xx_lcdc_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_lcdc_slaves[] = {
+ + 	&am33xx_l3_main__lcdc,
+ + };
+ + 
+ + static struct omap_hwmod am33xx_lcdc_hwmod = {
+ + 	.name		= "lcdc",
+ + 	.class		= &am33xx_lcdc_hwmod_class,
+ + 	.clkdm_name	= "lcdc_clkdm",
+ + 	.mpu_irqs	= am33xx_lcdc_irqs,
+ + 	.main_clk	= "lcdc_fck",
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.slaves		= am33xx_lcdc_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_lcdc_slaves),
+ + #if defined(CONFIG_CKB_LCD_SUPPORT) || defined(CONFIG_CKB_DVI_SUPPORT)
+ + 	.flags		= HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,				/* LCD clock shouldn't be reset or stopped */
+ + #else
+ + 	.flags		= (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
+ + #endif
+ + };
+ + 
+ + /*
+ +  * 'mailbox' class
+ +  * mailbox module allowing communication between the on-chip processors using a
+ +  * queued mailbox-interrupt mechanism.
+ +  */
+ + 
+ + static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
+ + 	.rev_offs	= 0x0000,
+ + 	.sysc_offs	= 0x0010,
+ + 	.sysc_flags	= (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+ + 			SYSC_HAS_SOFTRESET),
+ + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ + 	.sysc_fields	= &omap_hwmod_sysc_type2,
+ + };
+ + 
+ + static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
+ + 	.name	= "mailbox",
+ + 	.sysc	= &am33xx_mailbox_sysc,
+ + };
+ + 
+ + static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
+ + 	{ .irq = 77 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
+ + 	{
+ + 		.pa_start	= 0x480C8000,
+ + 		.pa_end		= 0x480C8000 + (SZ_4K - 1),
+ + 		.flags		= ADDR_TYPE_RT
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + /* l4_cfg -> mailbox */
+ + static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
+ + 	.master		= &am33xx_l4per_hwmod,
+ + 	.slave		= &am33xx_mailbox_hwmod,
+ + 	.addr		= am33xx_mailbox_addrs,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_mailbox_slaves[] = {
+ + 	&am33xx_l4_per__mailbox,
+ + };
+ + 
+ + static struct omap_hwmod am33xx_mailbox_hwmod = {
+ + 	.name		= "mailbox",
+ + 	.class		= &am33xx_mailbox_hwmod_class,
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.mpu_irqs	= am33xx_mailbox_irqs,
+ + 	.main_clk	= "mailbox0_fck",
+ + 	.prcm = {
+ + 		.omap4 = {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.slaves		= am33xx_mailbox_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_mailbox_slaves),
+ + };
+ + 
+ + /* 'mcasp' class */
+ + 
+ + static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
+ + 	.rev_offs	= 0x0,
+ + 	.sysc_offs	= 0x4,
+ + 	.sysc_flags	= SYSC_HAS_SIDLEMODE,
+ + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ + 	.sysc_fields	= &omap_hwmod_sysc_type3,
+ + };
+ + 
+ + static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
+ + 	.name	= "mcasp",
+ + 	.sysc	= &am33xx_mcasp_sysc,
+ + };
+ + 
+ + /* mcasp0 */
+ + static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
+ + 	{ .name = "ax", .irq = 80, },
+ + 	{ .name = "ar", .irq = 81, },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = {
+ + 	{ .name = "tx", .dma_req = AM33XX_DMA_MCASP0_X, },
+ + 	{ .name = "rx", .dma_req = AM33XX_DMA_MCASP0_R, },
+ + 	{ .dma_req = -1 }
+ + };
+ + 
+ + static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
+ + 	{
+ + 		.pa_start	= 0x48038000,
+ + 		.pa_end		= 0x48038000 + (SZ_1K * 12) - 1,
+ + 		.flags		= ADDR_TYPE_RT
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if am33xx_l3_slow__mcasp0 = {
+ + 	.master		= &am33xx_l3slow_hwmod,
+ + 	.slave		= &am33xx_mcasp0_hwmod,
+ + 	.clk		= "mcasp0_ick",
+ + 	.addr		= am33xx_mcasp0_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_mcasp0_slaves[] = {
+ + 	&am33xx_l3_slow__mcasp0,
+ + };
+ + 
+ + static struct omap_hwmod am33xx_mcasp0_hwmod = {
+ + 	.name		= "mcasp0",
+ + 	.class		= &am33xx_mcasp_hwmod_class,
+ + 	.clkdm_name	= "l3s_clkdm",
+ + 	.mpu_irqs	= am33xx_mcasp0_irqs,
+ + 	.sdma_reqs	= am33xx_mcasp0_edma_reqs,
+ + 	.main_clk	= "mcasp0_fck",
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.slaves		= am33xx_mcasp0_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_mcasp0_slaves),
+ + };
+ + 
+ + /* mcasp1 */
+ + static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
+ + 	{ .name = "ax", .irq = 82, },
+ + 	{ .name = "ar", .irq = 83, },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = {
+ + 	{ .name = "tx", .dma_req = AM33XX_DMA_MCASP1_X, },
+ + 	{ .name = "rx", .dma_req = AM33XX_DMA_MCASP1_R, },
+ + 	{ .dma_req = -1 }
+ + };
+ + 
+ + 
+ + static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
+ + 	{
+ + 		.pa_start	= 0x4803C000,
+ + 		.pa_end		= 0x4803C000 + (SZ_1K * 12) - 1,
+ + 		.flags		= ADDR_TYPE_RT
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if am33xx_l3_slow__mcasp1 = {
+ + 	.master		= &am33xx_l3slow_hwmod,
+ + 	.slave		= &am33xx_mcasp1_hwmod,
+ + 	.clk		= "mcasp1_ick",
+ + 	.addr		= am33xx_mcasp1_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_mcasp1_slaves[] = {
+ + 	&am33xx_l3_slow__mcasp1,
+ + };
+ + 
+ + static struct omap_hwmod am33xx_mcasp1_hwmod = {
+ + 	.name		= "mcasp1",
+ + 	.class		= &am33xx_mcasp_hwmod_class,
+ + 	.clkdm_name	= "l3s_clkdm",
+ + 	.mpu_irqs	= am33xx_mcasp1_irqs,
+ + 	.sdma_reqs	= am33xx_mcasp1_edma_reqs,
+ + 	.main_clk	= "mcasp1_fck",
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.slaves		= am33xx_mcasp1_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_mcasp1_slaves),
+ + };
+ + 
+ + /* 'mmc' class */
+ + static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
+ + 	.rev_offs	= 0x1fc,
+ + 	.sysc_offs	= 0x10,
+ + 	.syss_offs	= 0x14,
+ + 	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ + 			SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ + 			SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+ + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ + 	.sysc_fields	= &omap_hwmod_sysc_type1,
+ + };
+ + 
+ + static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
+ + 	.name		= "mmc",
+ + 	.sysc		= &am33xx_mmc_sysc,
+ + };
+ + 
+ + /* mmc0 */
+ + static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
+ + 	{ .irq = 64 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
+ + 	{ .name = "tx", .dma_req = 24, },
+ + 	{ .name = "rx", .dma_req = 25, },
+ + 	{ .dma_req = -1 }
+ + };
+ + 
+ + static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
+ + 	{
+ + 		.pa_start	= 0x48060100,
+ + 		.pa_end		= 0x48060100 + SZ_4K - 1,
+ + 		.flags		= ADDR_TYPE_RT,
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if am33xx_l4ls__mmc0 = {
+ + 	.master		= &am33xx_l4ls_hwmod,
+ + 	.slave		= &am33xx_mmc0_hwmod,
+ + 	.clk		= "mmc0_ick",
+ + 	.addr		= am33xx_mmc0_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_mmc0_slaves[] = {
+ + 	&am33xx_l4ls__mmc0,
+ + };
+ + 
+ + static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
+ + 	.flags		= OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+ + };
+ + 
+ + static struct omap_hwmod am33xx_mmc0_hwmod = {
+ + 	.name		= "mmc1",
+ + 	.class		= &am33xx_mmc_hwmod_class,
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.mpu_irqs	= am33xx_mmc0_irqs,
+ + 	.main_clk	= "mmc0_fck",
+ + 	.sdma_reqs	= am33xx_mmc0_edma_reqs,
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.dev_attr	= &am33xx_mmc0_dev_attr,
+ + 	.slaves		= am33xx_mmc0_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_mmc0_slaves),
+ + };
+ + 
+ + /* mmc1 */
+ + static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
+ + 	{ .irq = 28 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
+ + 	{ .name = "tx", .dma_req = 2, },
+ + 	{ .name = "rx", .dma_req = 3, },
+ + 	{ .dma_req = -1 }
+ + };
+ + 
+ + static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
+ + 	{
+ + 		.pa_start	= 0x481D8100,
+ + 		.pa_end		= 0x481D8100 + SZ_4K - 1,
+ + 		.flags		= ADDR_TYPE_RT,
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if am33xx_l4ls__mmc1 = {
+ + 	.master		= &am33xx_l4ls_hwmod,
+ + 	.slave		= &am33xx_mmc1_hwmod,
+ + 	.clk		= "mmc1_ick",
+ + 	.addr		= am33xx_mmc1_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_mmc1_slaves[] = {
+ + 	&am33xx_l4ls__mmc1,
+ + };
+ + 
+ + static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
+ + 	.flags		= OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+ + };
+ + 
+ + static struct omap_hwmod am33xx_mmc1_hwmod = {
+ + 	.name		= "mmc2",
+ + 	.class		= &am33xx_mmc_hwmod_class,
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.mpu_irqs	= am33xx_mmc1_irqs,
+ + 	.main_clk	= "mmc1_fck",
+ + 	.sdma_reqs	= am33xx_mmc1_edma_reqs,
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.dev_attr	= &am33xx_mmc1_dev_attr,
+ + 	.slaves		= am33xx_mmc1_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_mmc1_slaves),
+ + };
+ + 
+ + /* mmc2 */
+ + static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
+ + 	{ .irq = 29 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
+ + 	{ .name = "tx", .dma_req = 64, },
+ + 	{ .name = "rx", .dma_req = 65, },
+ + 	{ .dma_req = -1 }
+ + };
+ + 
+ + static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
+ + 	{
+ + 		.pa_start	= 0x47810100,
+ + 		.pa_end		= 0x47810100 + SZ_64K - 1,
+ + 		.flags		= ADDR_TYPE_RT,
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if am33xx_l3_main__mmc2 = {
+ + 	.master		= &am33xx_l3_main_hwmod,
+ + 	.slave		= &am33xx_mmc2_hwmod,
+ + 	.clk		= "mmc2_ick",
+ + 	.addr		= am33xx_mmc2_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_mmc2_slaves[] = {
+ + 	&am33xx_l3_main__mmc2,
+ + };
+ + 
+ + static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
+ + 	.flags		= OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+ + };
+ + static struct omap_hwmod am33xx_mmc2_hwmod = {
+ + 	.name		= "mmc3",
+ + 	.class		= &am33xx_mmc_hwmod_class,
+ + 	.clkdm_name	= "l3s_clkdm",
+ + 	.mpu_irqs	= am33xx_mmc2_irqs,
+ + 	.main_clk	= "mmc2_fck",
+ + 	.sdma_reqs	= am33xx_mmc2_edma_reqs,
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.dev_attr	= &am33xx_mmc2_dev_attr,
+ + 	.slaves		= am33xx_mmc2_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_mmc2_slaves),
+ + };
+ + 
+ + /* Master interfaces on the MPU interconnect */
+ + static struct omap_hwmod_ocp_if *am33xx_l3_mpu_masters[] = {
+ + 	&am33xx_mpu__l3_slow,
+ + };
+ + 
+ + /* mpu */
+ + static struct omap_hwmod am33xx_mpu_hwmod = {
+ + 	.name		= "mpu",
+ + 	.class		= &mpu_hwmod_class,
+ + 	.clkdm_name	= "mpu_clkdm",
+ + 	.main_clk	= "mpu_fck",
+ + 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.masters	= am33xx_l3_mpu_masters,
+ + 	.masters_cnt	= ARRAY_SIZE(am33xx_l3_mpu_masters),
+ + };
+ + 
+ + /* ocmcram */
+ + static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
+ + 	.name = "ocmcram",
+ + };
+ + 
+ + static struct omap_hwmod am33xx_ocmcram_hwmod = {
+ + 	.name		= "ocmcram",
+ + 	.class		= &am33xx_ocmcram_hwmod_class,
+ + 	.clkdm_name	= "l3_clkdm",
+ + 	.main_clk	= "ocmcram_ick",
+ + 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + };
+ + 
+ + /* ocpwp */
+ + static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
+ + 	.name		= "ocpwp",
+ + };
+ + 
+ + static struct omap_hwmod am33xx_ocpwp_hwmod = {
+ + 	.name		= "ocpwp",
+ + 	.class		= &am33xx_ocpwp_hwmod_class,
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.main_clk	= "ocpwp_fck",
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + };
+ + 
+ + static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
+ + 	.rev_offs	= 0x74,
+ + 	.sysc_offs	= 0x78,
+ + 	.sysc_flags	= SYSC_HAS_SIDLEMODE,
+ + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ + 			SIDLE_SMART_WKUP),
+ + 	.sysc_fields	= &omap_hwmod_sysc_type3,
+ + };
+ + 
+ + /* rtc */
+ + static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
+ + 	.name		= "rtc",
+ + 	.sysc		= &am33xx_rtc_sysc,
+ + };
+ + 
+ + static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
+ + 	{ .irq = 75 },
+ + 	{ .irq = 76 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod_addr_space am33xx_rtc_addrs[] = {
+ + 	{
+ + 		.pa_start	= 0x44E3E000,
+ + 		.pa_end		= 0x44E3E000 + SZ_4K - 1,
+ + 		.flags		= ADDR_TYPE_RT
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if am33xx_l4_wkup_rtc = {
+ + 	.master		= &am33xx_l4wkup_hwmod,
+ + 	.slave		= &am33xx_rtc_hwmod,
+ + 	.clk		= "rtc_ick",
+ + 	.addr		= am33xx_rtc_addrs,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_adc_rtc_slaves[] = {
+ + 	&am33xx_l4_wkup_rtc,
+ + };
+ + 
+ + static struct omap_hwmod am33xx_rtc_hwmod = {
+ + 	.name		= "rtc",
+ + 	.class		= &am33xx_rtc_hwmod_class,
+ + 	.clkdm_name	= "l4_rtc_clkdm",
+ + 	.mpu_irqs	= am33xx_rtc_irqs,
+ + 	.main_clk	= "rtc_fck",
+ + 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), /* ??? */
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.slaves		= am33xx_adc_rtc_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_adc_rtc_slaves),
+ + };
+ + 
+ + /* sha0 */
+ + static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
+ + 	.rev_offs	= 0x100,
+ + 	.sysc_offs	= 0x110,
+ + 	.syss_offs	= 0x114,
+ + 	.sysc_flags	= SYSS_HAS_RESET_STATUS,
+ + };
+ + 
+ + static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
+ + 	.name		= "sha0",
+ + 	.sysc		= &am33xx_sha0_sysc,
+ + };
+ + 
+ + static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
+ + 	{ .irq = AM33XX_IRQ_SHAEIP57t0_P },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod_dma_info am33xx_sha0_dma[] = {
+ + 	{ .dma_req = AM33XX_DMA_SHAEIP57T0_DIN },
+ + 	{ .dma_req = -1 }
+ + };
+ + 
+ + struct omap_hwmod_addr_space am33xx_sha0_addr_space[] = {
+ + 	{
+ + 		.pa_start	= 0x53100000,
+ + 		.pa_end		= 0x53100000 + SZ_1M - 1,
+ + 		.flags		= ADDR_TYPE_RT,
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + struct omap_hwmod_ocp_if am33xx_l3_core__sha0 = {
+ + 	.master		= &am33xx_l3_main_hwmod,
+ + 	.slave		= &am33xx_sha0_hwmod,
+ + 	.clk		= "sha0_fck",
+ + 	.addr		= am33xx_sha0_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_sha0_slaves[] = {
+ + 	&am33xx_l3_core__sha0,
+ + };
+ + 
+ + static struct omap_hwmod am33xx_sha0_hwmod = {
+ + 	.name		= "sha0",
+ + 	.class		= &am33xx_sha0_hwmod_class,
+ + 	.clkdm_name	= "l3_clkdm",
+ + 	.mpu_irqs	= am33xx_sha0_irqs,
+ + 	.sdma_reqs	= am33xx_sha0_dma,
+ + 	.main_clk	= "sha0_fck",
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.slaves		= am33xx_sha0_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_sha0_slaves),
+ + };
+ + 
+ + /* 'smartreflex' class */
+ + static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
+ + 	.name		= "smartreflex",
+ + };
+ + 
+ + /* smartreflex0 */
+ + static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
+ + 	{ .irq = 120 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod am33xx_smartreflex0_hwmod = {
+ + 	.name		= "smartreflex0",
+ + 	.class		= &am33xx_smartreflex_hwmod_class,
+ + 	.clkdm_name	= "l4_wkup_clkdm",
+ + 	.mpu_irqs	= am33xx_smartreflex0_irqs,
+ + 	.main_clk	= "smartreflex0_fck",
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + };
+ + 
+ + /* smartreflex1 */
+ + static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
+ + 	{ .irq = 121 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod am33xx_smartreflex1_hwmod = {
+ + 	.name		= "smartreflex1",
+ + 	.class		= &am33xx_smartreflex_hwmod_class,
+ + 	.clkdm_name	= "l4_wkup_clkdm",
+ + 	.mpu_irqs	= am33xx_smartreflex1_irqs,
+ + 	.main_clk	= "smartreflex1_fck",
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + };
+ + 
+ + /* 'spi' class */
+ + static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
+ + 	.rev_offs	= 0x0000,
+ + 	.sysc_offs	= 0x0110,
+ + 	.syss_offs	= 0x0114,
+ + 	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ + 			SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+ + 			SYSS_HAS_RESET_STATUS),
+ + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ + 	.sysc_fields	= &omap_hwmod_sysc_type1,
+ + };
+ + 
+ + static struct omap_hwmod_class am33xx_spi_hwmod_class = {
+ + 	.name		= "mcspi",
+ + 	.sysc		= &am33xx_mcspi_sysc,
+ + 	.rev		= OMAP4_MCSPI_REV,
+ + };
+ + 
+ + /* spi0 */
+ + static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
+ + 	{ .irq = 65 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = {
+ + 	{ .name = "rx0", .dma_req = 17 },
+ + 	{ .name = "tx0", .dma_req = 16 },
+ + 	{ .name = "rx1", .dma_req = 19 },
+ + 	{ .name = "tx1", .dma_req = 18 },
+ + 	{ .dma_req = -1 }
+ + };
+ + 
+ + struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
+ + 	{
+ + 		.pa_start	= 0x48030000,
+ + 		.pa_end		= 0x48030000 + SZ_1K - 1,
+ + 		.flags		= ADDR_TYPE_RT,
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + struct omap_hwmod_ocp_if am33xx_l4_core__mcspi0 = {
+ + 	.master		= &am33xx_l4per_hwmod,
+ + 	.slave		= &am33xx_spi0_hwmod,
+ + 	.clk		= "spi0_ick",
+ + 	.addr		= am33xx_mcspi0_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_mcspi0_slaves[] = {
+ + 	&am33xx_l4_core__mcspi0,
+ + };
+ + 
+ + struct omap2_mcspi_dev_attr mcspi_attrib = {
+ + 	.num_chipselect	= 2,
+ + };
+ + static struct omap_hwmod am33xx_spi0_hwmod = {
+ + 	.name		= "spi0",
+ + 	.class		= &am33xx_spi_hwmod_class,
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.mpu_irqs	= am33xx_spi0_irqs,
+ + 	.main_clk	= "spi0_fck",
+ + 	.sdma_reqs	= am33xx_mcspi0_edma_reqs,
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.dev_attr	= &mcspi_attrib,
+ + 	.slaves		= am33xx_mcspi0_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_mcspi0_slaves),
+ + };
+ + 
+ + /* spi1 */
+ + static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
+ + 	{ .irq = 125 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = {
+ + 	{ .name = "rx0", .dma_req = 43 },
+ + 	{ .name = "tx0", .dma_req = 42 },
+ + 	{ .name = "rx1", .dma_req = 45 },
+ + 	{ .name = "tx1", .dma_req = 44 },
+ + 	{ .dma_req = -1 }
+ + };
+ + 
+ + struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
+ + 	{
+ + 		.pa_start	= 0x481A0000,
+ + 		.pa_end		= 0x481A0000 + SZ_1K - 1,
+ + 		.flags		= ADDR_TYPE_RT,
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + struct omap_hwmod_ocp_if am33xx_l4_core__mcspi1 = {
+ + 	.master		= &am33xx_l4per_hwmod,
+ + 	.slave		= &am33xx_spi1_hwmod,
+ + 	.clk		= "spi1_ick",
+ + 	.addr		= am33xx_mcspi1_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_mcspi1_slaves[] = {
+ + 	&am33xx_l4_core__mcspi1,
+ + };
+ + static struct omap_hwmod am33xx_spi1_hwmod = {
+ + 	.name		= "spi1",
+ + 	.class		= &am33xx_spi_hwmod_class,
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.mpu_irqs	= am33xx_spi1_irqs,
+ + 	.main_clk	= "spi1_fck",
+ + 	.sdma_reqs	= am33xx_mcspi1_edma_reqs,
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.dev_attr	= &mcspi_attrib,
+ + 	.slaves		= am33xx_mcspi1_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_mcspi1_slaves),
+ + };
+ + 
+ + /* spinlock */
+ + static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
+ + 	.name		= "spinlock",
+ + };
+ + 
+ + static struct omap_hwmod am33xx_spinlock_hwmod = {
+ + 	.name		= "spinlock",
+ + 	.class		= &am33xx_spinlock_hwmod_class,
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.main_clk	= "spinlock_fck",
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + };
+ + 
+ + /* 'timer 0 & 2-7' class */
+ + static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
+ + 	.rev_offs	= 0x0000,
+ + 	.sysc_offs	= 0x0010,
+ + 	.syss_offs	= 0x0014,
+ + 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+ + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ + 			SIDLE_SMART_WKUP),
+ + 	.sysc_fields	= &omap_hwmod_sysc_type2,
+ + };
+ + 
+ + static struct omap_hwmod_class am33xx_timer_hwmod_class = {
+ + 	.name		= "timer",
+ + 	.sysc		= &am33xx_timer_sysc,
+ + };
+ + 
+ + /* timer0 */
+ + /* l4 wkup -> timer0 interface */
+ + static struct omap_hwmod_addr_space am33xx_timer0_addr_space[] = {
+ + 	{
+ + 		.pa_start	= 0x44E05000,
+ + 		.pa_end		= 0x44E05000 + SZ_1K - 1,
+ + 		.flags		= ADDR_TYPE_RT
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if am33xx_l4wkup__timer0 = {
+ + 	.master		= &am33xx_l4wkup_hwmod,
+ + 	.slave		= &am33xx_timer0_hwmod,
+ + 	.clk		= "timer0_ick",
+ + 	.addr		= am33xx_timer0_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_timer0_slaves[] = {
+ + 	&am33xx_l4wkup__timer0,
+ + };
+ + 
+ + static struct omap_hwmod_irq_info am33xx_timer0_irqs[] = {
+ + 	{ .irq = 66 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod am33xx_timer0_hwmod = {
+ + 	.name		= "timer0",
+ + 	.class		= &am33xx_timer_hwmod_class,
+ + 	.clkdm_name	= "l4_wkup_clkdm",
+ + 	.mpu_irqs	= am33xx_timer0_irqs,
+ + 	.main_clk	= "timer0_fck",
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.slaves		= am33xx_timer0_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_timer0_slaves),
+ + 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ + };
+ + 
+ + /* timer1 1ms */
+ + static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
+ + 	.rev_offs	= 0x0000,
+ + 	.sysc_offs	= 0x0010,
+ + 	.syss_offs	= 0x0014,
+ + 	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ + 			SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+ + 			SYSS_HAS_RESET_STATUS),
+ + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ + 	.sysc_fields	= &omap_hwmod_sysc_type1,
+ + };
+ + 
+ + static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
+ + 	.name		= "timer",
+ + 	.sysc		= &am33xx_timer1ms_sysc,
+ + };
+ + 
+ + /* l4 wkup -> timer1 interface */
+ + static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
+ + 	{
+ + 		.pa_start	= 0x44E31000,
+ + 		.pa_end		= 0x44E31000 + SZ_1K - 1,
+ + 		.flags		= ADDR_TYPE_RT
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if am33xx_l4wkup__timer1 = {
+ + 	.master		= &am33xx_l4wkup_hwmod,
+ + 	.slave		= &am33xx_timer1_hwmod,
+ + 	.clk		= "timer1_ick",
+ + 	.addr		= am33xx_timer1_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_timer1_slaves[] = {
+ + 	&am33xx_l4wkup__timer1,
+ + };
+ + 
+ + static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
+ + 	{ .irq = 67 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod am33xx_timer1_hwmod = {
+ + 	.name		= "timer1",
+ + 	.class		= &am33xx_timer1ms_hwmod_class,
+ + 	.clkdm_name	= "l4_wkup_clkdm",
+ + 	.mpu_irqs	= am33xx_timer1_irqs,
+ + 	.main_clk	= "timer1_fck",
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.slaves		= am33xx_timer1_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_timer1_slaves),
+ + };
+ + 
+ + /* timer2 */
+ + /* l4 per -> timer2 interface */
+ + static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
+ + 	{
+ + 		.pa_start	= 0x48040000,
+ + 		.pa_end		= 0x48040000 + SZ_1K - 1,
+ + 		.flags		= ADDR_TYPE_RT
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if am33xx_l4per__timer2 = {
+ + 	.master		= &am33xx_l4per_hwmod,
+ + 	.slave		= &am33xx_timer2_hwmod,
+ + 	.clk		= "timer2_ick",
+ + 	.addr		= am33xx_timer2_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_timer2_slaves[] = {
+ + 	&am33xx_l4per__timer2,
+ + };
+ + 
+ + static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
+ + 	{ .irq = 68 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod am33xx_timer2_hwmod = {
+ + 	.name		= "timer2",
+ + 	.class		= &am33xx_timer_hwmod_class,
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.mpu_irqs	= am33xx_timer2_irqs,
+ + 	.main_clk	= "timer2_fck",
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.slaves		= am33xx_timer2_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_timer2_slaves),
+ + };
+ + 
+ + /* timer3 */
+ + /* l4 per -> timer3 interface */
+ + static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
+ + 	{
+ + 		.pa_start	= 0x48042000,
+ + 		.pa_end		= 0x48042000 + SZ_1K - 1,
+ + 		.flags		= ADDR_TYPE_RT
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if am33xx_l4per__timer3 = {
+ + 	.master		= &am33xx_l4per_hwmod,
+ + 	.slave		= &am33xx_timer3_hwmod,
+ + 	.clk		= "timer3_ick",
+ + 	.addr		= am33xx_timer3_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_timer3_slaves[] = {
+ + 	&am33xx_l4per__timer3,
+ + };
+ + 
+ + static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
+ + 	{ .irq = 69 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod am33xx_timer3_hwmod = {
+ + 	.name		= "timer3",
+ + 	.class		= &am33xx_timer_hwmod_class,
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.mpu_irqs	= am33xx_timer3_irqs,
+ + 	.main_clk	= "timer3_fck",
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.slaves		= am33xx_timer3_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_timer3_slaves),
+ + };
+ + 
+ + /* timer4 */
+ + /* l4 per -> timer4 interface */
+ + static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
+ + 	{
+ + 		.pa_start	= 0x48044000,
+ + 		.pa_end		= 0x48044000 + SZ_1K - 1,
+ + 		.flags		= ADDR_TYPE_RT
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if am33xx_l4per__timer4 = {
+ + 	.master		= &am33xx_l4per_hwmod,
+ + 	.slave		= &am33xx_timer4_hwmod,
+ + 	.clk		= "timer4_ick",
+ + 	.addr		= am33xx_timer4_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_timer4_slaves[] = {
+ + 	&am33xx_l4per__timer4,
+ + };
+ + 
+ + static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
+ + 	{ .irq = 92 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod am33xx_timer4_hwmod = {
+ + 	.name		= "timer4",
+ + 	.class		= &am33xx_timer_hwmod_class,
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.mpu_irqs	= am33xx_timer4_irqs,
+ + 	.main_clk	= "timer4_fck",
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.slaves		= am33xx_timer4_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_timer4_slaves),
+ + };
+ + 
+ + /* timer5 */
+ + /* l4 per -> timer5 interface */
+ + static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
+ + 	{
+ + 		.pa_start	= 0x48046000,
+ + 		.pa_end		= 0x48046000 + SZ_1K - 1,
+ + 		.flags		= ADDR_TYPE_RT
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if am33xx_l4per__timer5 = {
+ + 	.master		= &am33xx_l4per_hwmod,
+ + 	.slave		= &am33xx_timer5_hwmod,
+ + 	.clk		= "timer5_ick",
+ + 	.addr		= am33xx_timer5_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_timer5_slaves[] = {
+ + 	&am33xx_l4per__timer5,
+ + };
+ + 
+ + static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
+ + 	{ .irq = 93 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod am33xx_timer5_hwmod = {
+ + 	.name		= "timer5",
+ + 	.class		= &am33xx_timer_hwmod_class,
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.mpu_irqs	= am33xx_timer5_irqs,
+ + 	.main_clk	= "timer5_fck",
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.slaves		= am33xx_timer5_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_timer5_slaves),
+ + };
+ + 
+ + /* timer6 */
+ + /* l4 per -> timer6 interface */
+ + static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
+ + 	{
+ + 		.pa_start	= 0x48048000,
+ + 		.pa_end		= 0x48048000 + SZ_1K - 1,
+ + 		.flags		= ADDR_TYPE_RT
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if am33xx_l4per__timer6 = {
+ + 	.master		= &am33xx_l4per_hwmod,
+ + 	.slave		= &am33xx_timer6_hwmod,
+ + 	.clk		= "timer6_ick",
+ + 	.addr		= am33xx_timer6_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_timer6_slaves[] = {
+ + 	&am33xx_l4per__timer6,
+ + };
+ + 
+ + static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
+ + 	{ .irq = 94 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod am33xx_timer6_hwmod = {
+ + 	.name		= "timer6",
+ + 	.class		= &am33xx_timer_hwmod_class,
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.mpu_irqs	= am33xx_timer6_irqs,
+ + 	.main_clk	= "timer6_fck",
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.slaves		= am33xx_timer6_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_timer6_slaves),
+ + };
+ + 
+ + /* timer7 */
+ + /* l4 per -> timer7 interface */
+ + static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
+ + 	{
+ + 		.pa_start	= 0x4804A000,
+ + 		.pa_end		= 0x4804A000 + SZ_1K - 1,
+ + 		.flags		= ADDR_TYPE_RT
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if am33xx_l4per__timer7 = {
+ + 	.master		= &am33xx_l4per_hwmod,
+ + 	.slave		= &am33xx_timer7_hwmod,
+ + 	.clk		= "timer7_ick",
+ + 	.addr		= am33xx_timer7_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_timer7_slaves[] = {
+ + 	&am33xx_l4per__timer7,
+ + };
+ + 
+ + static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
+ + 	{ .irq = 95 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod am33xx_timer7_hwmod = {
+ + 	.name		= "timer7",
+ + 	.class		= &am33xx_timer_hwmod_class,
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.mpu_irqs	= am33xx_timer7_irqs,
+ + 	.main_clk	= "timer7_fck",
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.slaves		= am33xx_timer7_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_timer7_slaves),
+ + };
+ + 
+ + /* tpcc */
+ + #define AM33XX_TPCC_BASE		0x49000000
+ + #define AM33XX_TPTC0_BASE		0x49800000
+ + #define AM33XX_TPTC1_BASE		0x49900000
+ + #define AM33XX_TPTC2_BASE		0x49a00000
+ + 
+ + /* 'tpcc' class */
+ + static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
+ + 	.name		= "tpcc",
+ + };
+ + 
+ + static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
+ + 	{ .name	= "edma0", .irq = 12 },
+ + 	{ .name = "edma0_mperr", .irq = 13, },
+ + 	{ .name	= "edma0_err", .irq = 14 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
+ + 	{
+ + 		.name		= "edma_cc0",
+ + 		.pa_start	= AM33XX_TPCC_BASE,
+ + 		.pa_end		= AM33XX_TPCC_BASE + SZ_32K - 1,
+ + 		.flags		= ADDR_TYPE_RT
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
+ + 	.master		= &am33xx_l3_main_hwmod,
+ + 	.slave		= &am33xx_tpcc_hwmod,
+ + 	.addr		= am33xx_tpcc_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_tpcc_slaves[] = {
+ + 	&am33xx_l3_main__tpcc,
+ + };
+ + 
+ + static struct omap_hwmod am33xx_tpcc_hwmod = {
+ + 	.name		= "tpcc",
+ + 	.class		= &am33xx_tpcc_hwmod_class,
+ + 	.clkdm_name	= "l3_clkdm",
+ + 	.mpu_irqs	= am33xx_tpcc_irqs,
+ + 	.main_clk	= "tpcc_ick",
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.slaves		= am33xx_tpcc_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_tpcc_slaves),
+ + };
+ + 
+ + static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
+ + 	.rev_offs	= 0x0,
+ + 	.sysc_offs	= 0x10,
+ + 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ + 			SYSC_HAS_MIDLEMODE),
+ + 	.idlemodes	= (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
+ + 	.sysc_fields	= &omap_hwmod_sysc_type2,
+ + };
+ + 
+ + /* 'tptc' class */
+ + static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
+ + 	.name		= "tptc",
+ + 	.sysc		= &am33xx_tptc_sysc,
+ + };
+ + 
+ + /* tptc0 */
+ + static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
+ + 	{ .irq = 112 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
+ + 	{
+ + 		.name		= "edma_tc0",
+ + 		.pa_start	= AM33XX_TPTC0_BASE,
+ + 		.pa_end		= AM33XX_TPTC0_BASE + SZ_8K - 1,
+ + 		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
+ + 	.master		= &am33xx_l3_main_hwmod,
+ + 	.slave		= &am33xx_tptc0_hwmod,
+ + 	.addr		= am33xx_tptc0_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_tptc0_slaves[] = {
+ + 	&am33xx_l3_main__tptc0,
+ + };
+ + 
+ + static struct omap_hwmod am33xx_tptc0_hwmod = {
+ + 	.name		= "tptc0",
+ + 	.class		= &am33xx_tptc_hwmod_class,
+ + 	.clkdm_name	= "l3_clkdm",
+ + 	.mpu_irqs	= am33xx_tptc0_irqs,
+ + 	.main_clk	= "tptc0_ick",
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.slaves		= am33xx_tptc0_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_tptc0_slaves),
+ + 	.flags		= (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
+ + };
+ + 
+ + /* tptc1 */
+ + static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
+ + 	{ .irq = 113 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
+ + 	{
+ + 		.name		= "edma_tc1",
+ + 		.pa_start	= AM33XX_TPTC1_BASE,
+ + 		.pa_end		= AM33XX_TPTC1_BASE + SZ_8K - 1,
+ + 		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
+ + 	.master		= &am33xx_l3_main_hwmod,
+ + 	.slave		= &am33xx_tptc1_hwmod,
+ + 	.addr		= am33xx_tptc1_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_tptc1_slaves[] = {
+ + 	&am33xx_l3_main__tptc1,
+ + };
+ + 
+ + static struct omap_hwmod am33xx_tptc1_hwmod = {
+ + 	.name		= "tptc1",
+ + 	.class		= &am33xx_tptc_hwmod_class,
+ + 	.clkdm_name	= "l3_clkdm",
+ + 	.mpu_irqs	= am33xx_tptc1_irqs,
+ + 	.main_clk	= "tptc1_ick",
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.slaves		= am33xx_tptc1_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_tptc1_slaves),
+ + 	.flags		= (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
+ + };
+ + 
+ + /* tptc2 */
+ + static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
+ + 	{ .irq = 114 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
+ + 	{
+ + 		.name		= "edma_tc2",
+ + 		.pa_start	= AM33XX_TPTC2_BASE,
+ + 		.pa_end		= AM33XX_TPTC2_BASE + SZ_8K - 1,
+ + 		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
+ + 	.master		= &am33xx_l3_main_hwmod,
+ + 	.slave		= &am33xx_tptc2_hwmod,
+ + 	.addr		= am33xx_tptc2_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_tptc2_slaves[] = {
+ + 	&am33xx_l3_main__tptc2,
+ + };
+ + 
+ + static struct omap_hwmod am33xx_tptc2_hwmod = {
+ + 	.name		= "tptc2",
+ + 	.class		= &am33xx_tptc_hwmod_class,
+ + 	.clkdm_name	= "l3_clkdm",
+ + 	.mpu_irqs	= am33xx_tptc2_irqs,
+ + 	.main_clk	= "tptc2_ick",
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.slaves		= am33xx_tptc2_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_tptc2_slaves),
+ + 	.flags		= (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
+ + };
+ + 
+ + /* 'uart' class */
+ + static struct omap_hwmod_class_sysconfig uart_sysc = {
+ + 	.rev_offs	= 0x50,
+ + 	.sysc_offs	= 0x54,
+ + 	.syss_offs	= 0x58,
+ + 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
+ + 			SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ + 			SIDLE_SMART_WKUP),
+ + 	.sysc_fields	= &omap_hwmod_sysc_type1,
+ + };
+ + 
+ + static struct omap_hwmod_class uart_class = {
+ + 	.name		= "uart",
+ + 	.sysc		= &uart_sysc,
+ + };
+ + 
+ + /* uart1 */
+ + static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
+ + 	{ .name = "tx",	.dma_req = 26, },
+ + 	{ .name = "rx",	.dma_req = 27, },
+ + 	{ .dma_req = -1 }
+ + };
+ + 
+ + static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
+ + 	{
+ + 		.pa_start	= 0x44E09000,
+ + 		.pa_end		= 0x44E09000 + SZ_8K - 1,
+ + 		.flags		= ADDR_TYPE_RT,
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
+ + 	.master		= &am33xx_l4wkup_hwmod,
+ + 	.slave		= &am33xx_uart1_hwmod,
+ + 	.clk		= "uart1_ick",
+ + 	.addr		= am33xx_uart1_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
+ + 	{ .irq = 72 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_uart1_slaves[] = {
+ + 	&am33xx_l4_wkup__uart1,
+ + };
+ + 
+ + static struct omap_hwmod am33xx_uart1_hwmod = {
+ + 	.name		= "uart1",
+ + 	.class		= &uart_class,
+ + 	.clkdm_name	= "l4_wkup_clkdm",
+ + 	.mpu_irqs	= am33xx_uart1_irqs,
+ + 	.main_clk	= "uart1_fck",
+ + 	.sdma_reqs	= uart1_edma_reqs,
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.slaves		= am33xx_uart1_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_uart1_slaves),
+ + };
+ + 
+ + /* uart2 */
+ + static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
+ + 	{
+ + 		.pa_start	= 0x48022000,
+ + 		.pa_end		= 0x48022000 + SZ_8K - 1,
+ + 		.flags		= ADDR_TYPE_RT,
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
+ + 	.slave		= &am33xx_uart2_hwmod,
+ + 	.clk		= "uart2_ick",
+ + 	.addr		= am33xx_uart2_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
+ + 	{ .irq = 73 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_uart2_slaves[] = {
+ + 	&am33xx_l4_ls__uart2,
+ + };
+ + 
+ + static struct omap_hwmod am33xx_uart2_hwmod = {
+ + 	.name		= "uart2",
+ + 	.class		= &uart_class,
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.mpu_irqs	= am33xx_uart2_irqs,
+ + 	.main_clk	= "uart2_fck",
+ + 	.sdma_reqs	= uart1_edma_reqs,
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.slaves		= am33xx_uart2_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_uart2_slaves),
+ + };
+ + 
+ + /* uart3 */
+ + static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
+ + 	{ .name = "tx",	.dma_req = 30, },
+ + 	{ .name = "rx",	.dma_req = 31, },
+ + 	{ .dma_req = -1 }
+ + };
+ + 
+ + static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
+ + 	{
+ + 		.pa_start	= 0x48024000,
+ + 		.pa_end		= 0x48024000 + SZ_8K - 1,
+ + 		.flags		= ADDR_TYPE_RT,
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
+ + 	.slave		= &am33xx_uart3_hwmod,
+ + 	.clk		= "uart3_ick",
+ + 	.addr		= am33xx_uart3_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
+ + 	{ .irq = 74 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_uart3_slaves[] = {
+ + 	&am33xx_l4_ls__uart3,
+ + };
+ + 
+ + static struct omap_hwmod am33xx_uart3_hwmod = {
+ + 	.name		= "uart3",
+ + 	.class		= &uart_class,
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.mpu_irqs	= am33xx_uart3_irqs,
+ + 	.main_clk	= "uart3_fck",
+ + 	.sdma_reqs	= uart3_edma_reqs,
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.slaves		= am33xx_uart3_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_uart3_slaves),
+ + };
+ + 
+ + /* uart4 */
+ + static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
+ + 	{
+ + 		.pa_start	= 0x481A6000,
+ + 		.pa_end		= 0x481A6000 + SZ_8K - 1,
+ + 		.flags		= ADDR_TYPE_RT,
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
+ + 	.slave		= &am33xx_uart4_hwmod,
+ + 	.clk		= "uart4_ick",
+ + 	.addr		= am33xx_uart4_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
+ + 	{ .irq = 44 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_uart4_slaves[] = {
+ + 	&am33xx_l4_ls__uart4,
+ + };
+ + 
+ + static struct omap_hwmod am33xx_uart4_hwmod = {
+ + 	.name		= "uart4",
+ + 	.class		= &uart_class,
+ + 	.mpu_irqs	= am33xx_uart4_irqs,
+ + 	.main_clk	= "uart4_fck",
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.sdma_reqs	= uart1_edma_reqs,
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.slaves		= am33xx_uart4_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_uart4_slaves),
+ + };
+ + 
+ + /* uart5 */
+ + static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
+ + 	{
+ + 		.pa_start	= 0x481A8000,
+ + 		.pa_end		= 0x481A8000 + SZ_8K - 1,
+ + 		.flags		= ADDR_TYPE_RT,
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
+ + 	.slave		= &am33xx_uart5_hwmod,
+ + 	.clk		= "uart5_ick",
+ + 	.addr		= am33xx_uart5_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
+ + 	{ .irq = 45 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_uart5_slaves[] = {
+ + 	&am33xx_l4_ls__uart5,
+ + };
+ + 
+ + static struct omap_hwmod am33xx_uart5_hwmod = {
+ + 	.name		= "uart5",
+ + 	.class		= &uart_class,
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.mpu_irqs	= am33xx_uart5_irqs,
+ + 	.main_clk	= "uart5_fck",
+ + 	.sdma_reqs	= uart1_edma_reqs,
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.slaves		= am33xx_uart5_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_uart5_slaves),
+ + };
+ + 
+ + /* uart6 */
+ + static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
+ + 	{
+ + 		.pa_start	= 0x481AA000,
+ + 		.pa_end		= 0x481AA000 + SZ_8K - 1,
+ + 		.flags		= ADDR_TYPE_RT,
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
+ + 	.slave		= &am33xx_uart6_hwmod,
+ + 	.clk		= "uart6_ick",
+ + 	.addr		= am33xx_uart6_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
+ + 	{ .irq = 46 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_uart6_slaves[] = {
+ + 	&am33xx_l4_ls__uart6,
+ + };
+ + 
+ + static struct omap_hwmod am33xx_uart6_hwmod = {
+ + 	.name		= "uart6",
+ + 	.class		= &uart_class,
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.mpu_irqs	= am33xx_uart6_irqs,
+ + 	.main_clk	= "uart6_fck",
+ + 	.sdma_reqs	= uart1_edma_reqs,
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.slaves		= am33xx_uart6_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_uart6_slaves),
+ + };
+ + 
+ + /* 'wd_timer' class */
+ + static struct omap_hwmod_class_sysconfig wdt_sysc = {
+ + 	.rev_offs	= 0x0,
+ + 	.sysc_offs	= 0x10,
+ + 	.syss_offs	= 0x14,
+ + 	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
+ + 			SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ + 			SIDLE_SMART_WKUP),
+ + 	.sysc_fields	= &omap_hwmod_sysc_type1,
+ + };
+ + 
+ + static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
+ + 	.name		= "wd_timer",
+ + 	.sysc		= &wdt_sysc,
+ + 	.pre_shutdown	= &omap2_wd_timer_disable,
+ + };
+ + 
+ + static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
+ + 	{
+ + 		.pa_start	= 0x44E35000,
+ + 		.pa_end		= 0x44E35000 + SZ_4K - 1,
+ + 		.flags		= ADDR_TYPE_RT
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + /* l4_wkup -> wd_timer1 */
+ + static struct omap_hwmod_ocp_if am33xx_l4wkup__wd_timer1 = {
+ + 	.master		= &am33xx_l4wkup_hwmod,
+ + 	.slave		= &am33xx_wd_timer1_hwmod,
+ + 	.addr		= am33xx_wd_timer1_addrs,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_wd_timer1_slaves[] = {
+ + 	&am33xx_l4wkup__wd_timer1,
+ + };
+ + 
+ + /*
+ +  * TODO: device.c file uses hardcoded name for watchdog timer
+ +  * driver "wd_timer2, so we are also using same name as of now...
+ +  */
+ + static struct omap_hwmod am33xx_wd_timer1_hwmod = {
+ + 	.name		= "wd_timer2",
+ + 	.class		= &am33xx_wd_timer_hwmod_class,
+ + 	.clkdm_name	= "l4_wkup_clkdm",
+ + 	.flags		= HWMOD_SWSUP_SIDLE,
+ + 	.main_clk	= "wdt1_fck",
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.slaves		= am33xx_wd_timer1_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_wd_timer1_slaves),
+ + };
+ + 
+ + /* wkup_m3 */
+ + static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
+ + 	.name		= "wkup_m3",
+ + };
+ + 
+ + static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
+ + 	{ .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
+ + };
+ + 
+ + static struct omap_hwmod am33xx_wkup_m3_hwmod = {
+ + 	.name		= "wkup_m3",
+ + 	.class		= &am33xx_wkup_m3_hwmod_class,
+ + 	.clkdm_name	= "l4_wkup_aon_clkdm",
+ + 	.main_clk	= "wkup_m3_fck",
+ + 	.flags		= HWMOD_INIT_NO_RESET,	/* Keep hardreset asserted */
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
+ + 			.rstctrl_offs	= AM33XX_RM_WKUP_RSTCTRL_OFFSET,
+ + 			.rstst_offs	= AM33XX_RM_WKUP_RSTST_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.rst_lines	= am33xx_wkup_m3_resets,
+ + 	.rst_lines_cnt	= ARRAY_SIZE(am33xx_wkup_m3_resets),
+ + };
+ + 
+ + /* usbss */
+ + /* L3 SLOW -> USBSS interface */
+ + static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
+ + 	{
+ + 		.name		= "usbss",
+ + 		.pa_start	= 0x47400000,
+ + 		.pa_end		= 0x47400000 + SZ_4K - 1,
+ + 		.flags		= ADDR_TYPE_RT
+ + 	},
+ + 	{
+ + 		.name		= "musb0",
+ + 		.pa_start	= 0x47401000,
+ + 		.pa_end		= 0x47401000 + SZ_2K - 1,
+ + 		.flags		= ADDR_TYPE_RT
+ + 	},
+ + 	{
+ + 		.name		= "musb1",
+ + 		.pa_start	= 0x47401800,
+ + 		.pa_end		= 0x47401800 + SZ_2K - 1,
+ + 		.flags		= ADDR_TYPE_RT
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
+ + 	.rev_offs	= 0x0,
+ + 	.sysc_offs	= 0x10,
+ + 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
+ + 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ + 			MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+ + 	.sysc_fields	= &omap_hwmod_sysc_type2,
+ + };
+ + 
+ + static struct omap_hwmod_class am33xx_usbotg_class = {
+ + 	.name		= "usbotg",
+ + 	.sysc		= &am33xx_usbhsotg_sysc,
+ + };
+ + 
+ + static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
+ + 	{ .name = "usbss-irq", .irq = 17, },
+ + 	{ .name = "musb0-irq", .irq = 18, },
+ + 	{ .name = "musb1-irq", .irq = 19, },
+ + 	{ .irq = -1, },
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if am33xx_l3_slow__usbss = {
+ + 	.master		= &am33xx_l3slow_hwmod,
+ + 	.slave		= &am33xx_usbss_hwmod,
+ + 	.clk		= "usbotg_ick",
+ + 	.addr		= am33xx_usbss_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + 	.flags		= OCPIF_SWSUP_IDLE,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_usbss_slaves[] = {
+ + 	&am33xx_l3_slow__usbss,
+ + };
+ + 
+ + static struct omap_hwmod am33xx_usbss_hwmod = {
+ + 	.name		= "usb_otg_hs",
+ + 	.class		= &am33xx_usbotg_class,
+ + 	.clkdm_name	= "l3s_clkdm",
+ + 	.mpu_irqs	= am33xx_usbss_mpu_irqs,
+ + 	.main_clk	= "usbotg_fck",
+ + 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.slaves		= am33xx_usbss_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_usbss_slaves),
+ + 	.class		= &am33xx_usbotg_class,
+ + 	.flags		= (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
+ + };
+ + 
+ + /* gfx */
+ + /* Pseudo hwmod for reset control purpose only */
+ + static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
+ + 	.name	= "gfx",
+ + };
+ + 
+ + static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
+ + 	{ .name = "gfx", .rst_shift = 0, .st_shift = 0 },
+ + };
+ + 
+ + static struct omap_hwmod am33xx_gfx_hwmod = {
+ + 	.name		= "gfx",
+ + 	.class		= &am33xx_gfx_hwmod_class,
+ + 	.clkdm_name	= "gfx_l3_clkdm",
+ + 	.main_clk	= "gfx_fclk",
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
+ + 			.rstctrl_offs	= AM33XX_RM_GFX_RSTCTRL_OFFSET,
+ + 			.rstst_offs	= AM33XX_RM_GFX_RSTST_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.rst_lines	= am33xx_gfx_resets,
+ + 	.rst_lines_cnt	= ARRAY_SIZE(am33xx_gfx_resets),
+ + };
+ + 
+ + /* PRUSS */
+ + /* Pseudo hwmod for reset control purpose only */
+ + static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
+ + 	.name	= "pruss",
+ + };
+ + 
+ + static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
+ + 	{ .name = "pruss", .rst_shift = 1 },
+ + };
+ + 
+ + static struct omap_hwmod am33xx_pruss_hwmod = {
+ + 	.name		= "pruss",
+ + 	.class		= &am33xx_pruss_hwmod_class,
+ + 	.clkdm_name	= "pruss_ocp_clkdm",
+ + 	.main_clk	= "pruss_uart_gclk",
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET,
+ + 			.rstctrl_offs	= AM33XX_RM_PER_RSTCTRL_OFFSET,
+ + 			.rstst_offs	= AM33XX_RM_PER_RSTST_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.rst_lines	= am33xx_pruss_resets,
+ + 	.rst_lines_cnt	= ARRAY_SIZE(am33xx_pruss_resets),
+ + };
+ + 
+ + /* rng */
+ + static struct omap_hwmod_sysc_fields omap3_rng_sysc_fields = {
+ + 	.sidle_shift	= 3,
+ + 	.autoidle_shift	= 0,
+ + };
+ + 
+ + static struct omap_hwmod_class_sysconfig am33xx_rng_sysc = {
+ + 	.rev_offs	= 0x1fe0,
+ + 	.sysc_offs	= 0x1fe4,
+ + 	.rst_offs	= 0x1ff0,
+ + 	.sysc_flags	= SYSC_HAS_AUTOIDLE,
+ + 	.sysc_fields	= &omap3_rng_sysc_fields,
+ + };
+ + 
+ + static struct omap_hwmod_class am33xx_rng_hwmod_class = {
+ + 	.name		= "rng",
+ + 	.sysc		= &am33xx_rng_sysc,
+ + };
+ + 
+ + static struct omap_hwmod_irq_info am33xx_rng_irqs[] = {
+ + 	{ .irq = 111 },
+ + 	{ .irq = -1 }
+ + };
+ + 
+ + struct omap_hwmod_addr_space am33xx_rng_addr_space[] = {
+ + 	{
+ + 		.pa_start	= 0x48310000,
+ + 		.pa_end		= 0x48310000 + SZ_8K - 1,
+ + 		.flags		= ADDR_TYPE_RT,
+ + 	},
+ + 	{ }
+ + };
+ + 
+ + struct omap_hwmod_ocp_if am33xx_l4per__rng = {
+ + 	.master		= &am33xx_l4per_hwmod,
+ + 	.slave		= &am33xx_rng_hwmod,
+ + 	.clk		= "rng_fck",
+ + 	.addr		= am33xx_rng_addr_space,
+ + 	.user		= OCP_USER_MPU,
+ + };
+ + 
+ + static struct omap_hwmod_ocp_if *am33xx_rng_slaves[] = {
+ + 	&am33xx_l4per__rng,
+ + };
+ + 
+ + static struct omap_hwmod am33xx_rng_hwmod = {
+ + 	.name		= "rng",
+ + 	.class		= &am33xx_rng_hwmod_class,
+ + 	.clkdm_name	= "l4ls_clkdm",
+ + 	.mpu_irqs	= am33xx_rng_irqs,
+ + 	.main_clk	= "rng_fck",
+ + 	.prcm		= {
+ + 		.omap4	= {
+ + 			.clkctrl_offs	= AM33XX_CM_PER_RNG_CLKCTRL_OFFSET,
+ + 			.modulemode	= MODULEMODE_SWCTRL,
+ + 		},
+ + 	},
+ + 	.slaves		= am33xx_rng_slaves,
+ + 	.slaves_cnt	= ARRAY_SIZE(am33xx_rng_slaves),
+ + };
+ + 
+ + static __initdata struct omap_hwmod *am33xx_hwmods[] = {
+ + 	/* l3 class */
+ + 	&am33xx_l3_instr_hwmod,
+ + 	&am33xx_l3_main_hwmod,
+ + 	/* l3s class */
+ + 	&am33xx_l3slow_hwmod,
+ + 	/* l4hs class */
+ + 	&am33xx_l4_hs_hwmod,
+ + 	/* l4fw class */
+ + 	&am33xx_l4fw_hwmod,
+ + 	/* l4ls class */
+ + 	&am33xx_l4ls_hwmod,
+ + 	/* l4per class */
+ + 	&am33xx_l4per_hwmod,
+ + 	/* l4wkup class */
+ + 	&am33xx_l4wkup_hwmod,
+ + 	/* clkdiv32k class */
+ + 	&am33xx_clkdiv32k_hwmod,
+ + 	/* mpu class */
+ + 	&am33xx_mpu_hwmod,
+ + 	/* adc_tsc class */
+ + 	&am33xx_adc_tsc_hwmod,
+ + 	/* aes class */
+ + 	&am33xx_aes0_hwmod,
+ + 	/* cefuse class */
+ + 	&am33xx_cefuse_hwmod,
+ + 	/* control class */
+ + 	&am33xx_control_hwmod,
+ + 	/* dcan class */
+ + 	&am33xx_dcan0_hwmod,
+ + 	&am33xx_dcan1_hwmod,
+ + 	/* debugss class */
+ + 	&am33xx_debugss_hwmod,
+ + 	/* elm class */
+ + 	&am33xx_elm_hwmod,
+ + 	/* emif_fw class */
+ + 	&am33xx_emif_fw_hwmod,
+ + 	/* epwmss class */
+ + 	&am33xx_ehrpwm0_hwmod,
+ + 	&am33xx_ehrpwm1_hwmod,
+ + 	&am33xx_ehrpwm2_hwmod,
+ + 	&am33xx_ecap0_hwmod,
+ + 	&am33xx_ecap1_hwmod,
+ + 	&am33xx_ecap2_hwmod,
+ + 	/* gpio class */
+ + 	&am33xx_gpio0_hwmod,
+ + 	&am33xx_gpio1_hwmod,
+ + 	&am33xx_gpio2_hwmod,
+ + 	&am33xx_gpio3_hwmod,
+ + 	/* gpmc class */
+ + 	&am33xx_gpmc_hwmod,
+ + 	/* i2c class */
+ + 	&am33xx_i2c1_hwmod,
+ + 	&am33xx_i2c2_hwmod,
+ + 	&am33xx_i2c3_hwmod,
+ + 	/* ieee5000 class */
+ + 	&am33xx_ieee5000_hwmod,
+ + 	/* mailbox class */
+ + 	&am33xx_mailbox_hwmod,
+ + 	/* mcasp class */
+ + 	&am33xx_mcasp0_hwmod,
+ + 	&am33xx_mcasp1_hwmod,
+ + 	/* mmc class */
+ + 	&am33xx_mmc0_hwmod,
+ + 	&am33xx_mmc1_hwmod,
+ + 	&am33xx_mmc2_hwmod,
+ + 	/* ocmcram class */
+ + 	&am33xx_ocmcram_hwmod,
+ + 	/* ocpwp class */
+ + 	&am33xx_ocpwp_hwmod,
+ + 	/* rtc class */
+ + 	&am33xx_rtc_hwmod,
+ + 	/* sha0 class */
+ + 	&am33xx_sha0_hwmod,
+ + 	/* smartreflex class */
+ + 	&am33xx_smartreflex0_hwmod,
+ + 	&am33xx_smartreflex1_hwmod,
+ + 	/* spi class */
+ + 	&am33xx_spi0_hwmod,
+ + 	&am33xx_spi1_hwmod,
+ + 	/* spinlock class */
+ + 	&am33xx_spinlock_hwmod,
+ + 	/* uart class */
+ + 	&am33xx_uart1_hwmod,
+ + 	&am33xx_uart2_hwmod,
+ + 	&am33xx_uart3_hwmod,
+ + 	&am33xx_uart4_hwmod,
+ + 	&am33xx_uart5_hwmod,
+ + 	&am33xx_uart6_hwmod,
+ + 	/* timer class */
+ + 	&am33xx_timer0_hwmod,
+ + 	&am33xx_timer1_hwmod,
+ + 	&am33xx_timer2_hwmod,
+ + 	&am33xx_timer3_hwmod,
+ + 	&am33xx_timer4_hwmod,
+ + 	&am33xx_timer5_hwmod,
+ + 	&am33xx_timer6_hwmod,
+ + 	&am33xx_timer7_hwmod,
+ + 	/* wkup_m3 class */
+ + 	&am33xx_wkup_m3_hwmod,
+ + 	/* wd_timer class */
+ + 	&am33xx_wd_timer1_hwmod,
+ + 	/* usbss hwmod */
+ + 	&am33xx_usbss_hwmod,
+ + 	/* cpgmac0 class */
+ + 	&am33xx_cpgmac0_hwmod,
+ + 	/* mdio class */
+ + 	&am33xx_mdio_hwmod,
+ + 	/* tptc class */
+ + 	&am33xx_tptc0_hwmod,
+ + 	&am33xx_tptc1_hwmod,
+ + 	&am33xx_tptc2_hwmod,
+ + 	/* tpcc class */
+ + 	&am33xx_tpcc_hwmod,
+ + 	/* LCDC class */
+ + 	&am33xx_lcdc_hwmod,
+ + 	/* gfx/sgx */
+ + 	&am33xx_gfx_hwmod,
+ + 	/* pruss */
+ + 	&am33xx_pruss_hwmod,
+ + 	/* rng */
+ + 	&am33xx_rng_hwmod,
+ + 	NULL,
+ + };
+ + 
+ + int __init am33xx_hwmod_init(void)
+ + {
+ + 	return omap_hwmod_register(am33xx_hwmods);
+ + }
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_hwmod.c linux-3.2.1/arch/arm/mach-ckb_3352/omap_hwmod.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_hwmod.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/omap_hwmod.c	2014-11-25 13:19:15.027074032 +0900
+ ***************
+ *** 0 ****
+ --- 1,2788 ----
+ + /*
+ +  * omap_hwmod implementation for OMAP2/3/4
+ +  *
+ +  * Copyright (C) 2009-2011 Nokia Corporation
+ +  * Copyright (C) 2011 Texas Instruments, Inc.
+ +  *
+ +  * Paul Walmsley, Benoît Cousson, Kevin Hilman
+ +  *
+ +  * Created in collaboration with (alphabetical order): Thara Gopinath,
+ +  * Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari Poussa, Anand
+ +  * Sawant, Santosh Shilimkar, Richard Woodruff
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  *
+ +  * Introduction
+ +  * ------------
+ +  * One way to view an OMAP SoC is as a collection of largely unrelated
+ +  * IP blocks connected by interconnects.  The IP blocks include
+ +  * devices such as ARM processors, audio serial interfaces, UARTs,
+ +  * etc.  Some of these devices, like the DSP, are created by TI;
+ +  * others, like the SGX, largely originate from external vendors.  In
+ +  * TI's documentation, on-chip devices are referred to as "OMAP
+ +  * modules."  Some of these IP blocks are identical across several
+ +  * OMAP versions.  Others are revised frequently.
+ +  *
+ +  * These OMAP modules are tied together by various interconnects.
+ +  * Most of the address and data flow between modules is via OCP-based
+ +  * interconnects such as the L3 and L4 buses; but there are other
+ +  * interconnects that distribute the hardware clock tree, handle idle
+ +  * and reset signaling, supply power, and connect the modules to
+ +  * various pads or balls on the OMAP package.
+ +  *
+ +  * OMAP hwmod provides a consistent way to describe the on-chip
+ +  * hardware blocks and their integration into the rest of the chip.
+ +  * This description can be automatically generated from the TI
+ +  * hardware database.  OMAP hwmod provides a standard, consistent API
+ +  * to reset, enable, idle, and disable these hardware blocks.  And
+ +  * hwmod provides a way for other core code, such as the Linux device
+ +  * code or the OMAP power management and address space mapping code,
+ +  * to query the hardware database.
+ +  *
+ +  * Using hwmod
+ +  * -----------
+ +  * Drivers won't call hwmod functions directly.  That is done by the
+ +  * omap_device code, and in rare occasions, by custom integration code
+ +  * in arch/arm/ *omap*.  The omap_device code includes functions to
+ +  * build a struct platform_device using omap_hwmod data, and that is
+ +  * currently how hwmod data is communicated to drivers and to the
+ +  * Linux driver model.  Most drivers will call omap_hwmod functions only
+ +  * indirectly, via pm_runtime*() functions.
+ +  *
+ +  * From a layering perspective, here is where the OMAP hwmod code
+ +  * fits into the kernel software stack:
+ +  *
+ +  *            +-------------------------------+
+ +  *            |      Device driver code       |
+ +  *            |      (e.g., drivers/)         |
+ +  *            +-------------------------------+
+ +  *            |      Linux driver model       |
+ +  *            |     (platform_device /        |
+ +  *            |  platform_driver data/code)   |
+ +  *            +-------------------------------+
+ +  *            | OMAP core-driver integration  |
+ +  *            |(arch/arm/mach-omap2/devices.c)|
+ +  *            +-------------------------------+
+ +  *            |      omap_device code         |
+ +  *            | (../plat-omap/omap_device.c)  |
+ +  *            +-------------------------------+
+ +  *   ---->    |    omap_hwmod code/data       |    <-----
+ +  *            | (../mach-omap2/omap_hwmod*)   |
+ +  *            +-------------------------------+
+ +  *            | OMAP clock/PRCM/register fns  |
+ +  *            | (__raw_{read,write}l, clk*)   |
+ +  *            +-------------------------------+
+ +  *
+ +  * Device drivers should not contain any OMAP-specific code or data in
+ +  * them.  They should only contain code to operate the IP block that
+ +  * the driver is responsible for.  This is because these IP blocks can
+ +  * also appear in other SoCs, either from TI (such as DaVinci) or from
+ +  * other manufacturers; and drivers should be reusable across other
+ +  * platforms.
+ +  *
+ +  * The OMAP hwmod code also will attempt to reset and idle all on-chip
+ +  * devices upon boot.  The goal here is for the kernel to be
+ +  * completely self-reliant and independent from bootloaders.  This is
+ +  * to ensure a repeatable configuration, both to ensure consistent
+ +  * runtime behavior, and to make it easier for others to reproduce
+ +  * bugs.
+ +  *
+ +  * OMAP module activity states
+ +  * ---------------------------
+ +  * The hwmod code considers modules to be in one of several activity
+ +  * states.  IP blocks start out in an UNKNOWN state, then once they
+ +  * are registered via the hwmod code, proceed to the REGISTERED state.
+ +  * Once their clock names are resolved to clock pointers, the module
+ +  * enters the CLKS_INITED state; and finally, once the module has been
+ +  * reset and the integration registers programmed, the INITIALIZED state
+ +  * is entered.  The hwmod code will then place the module into either
+ +  * the IDLE state to save power, or in the case of a critical system
+ +  * module, the ENABLED state.
+ +  *
+ +  * OMAP core integration code can then call omap_hwmod*() functions
+ +  * directly to move the module between the IDLE, ENABLED, and DISABLED
+ +  * states, as needed.  This is done during both the PM idle loop, and
+ +  * in the OMAP core integration code's implementation of the PM runtime
+ +  * functions.
+ +  *
+ +  * References
+ +  * ----------
+ +  * This is a partial list.
+ +  * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064)
+ +  * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090)
+ +  * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108)
+ +  * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140)
+ +  * - Open Core Protocol Specification 2.2
+ +  *
+ +  * To do:
+ +  * - handle IO mapping
+ +  * - bus throughput & module latency measurement code
+ +  *
+ +  * XXX add tests at the beginning of each function to ensure the hwmod is
+ +  * in the appropriate state
+ +  * XXX error return values should be checked to ensure that they are
+ +  * appropriate
+ +  */
+ + #undef DEBUG
+ + 
+ + #include <linux/kernel.h>
+ + #include <linux/errno.h>
+ + #include <linux/io.h>
+ + #include <linux/clk.h>
+ + #include <linux/delay.h>
+ + #include <linux/err.h>
+ + #include <linux/list.h>
+ + #include <linux/mutex.h>
+ + #include <linux/spinlock.h>
+ + #include <linux/slab.h>
+ + 
+ + #include "common.h"
+ + #include <plat/cpu.h>
+ + #include "clockdomain.h"
+ + #include "powerdomain.h"
+ + #include <plat/clock.h>
+ + #include <plat/omap_hwmod.h>
+ + #include <plat/prcm.h>
+ + 
+ + //#include "cm2xxx_3xxx.h"
+ + #include "cminst44xx.h"
+ + #include "prm2xxx_3xxx.h"
+ + #include "prm33xx.h"
+ + #include "prminst44xx.h"
+ + #include "mux.h"
+ + 
+ + /* Maximum microseconds to wait for OMAP module to softreset */
+ + #define MAX_MODULE_SOFTRESET_WAIT	10000
+ + 
+ + /* Name of the OMAP hwmod for the MPU */
+ + #define MPU_INITIATOR_NAME		"mpu"
+ + 
+ + /* omap_hwmod_list contains all registered struct omap_hwmods */
+ + static LIST_HEAD(omap_hwmod_list);
+ + 
+ + /* mpu_oh: used to add/remove MPU initiator from sleepdep list */
+ + static struct omap_hwmod *mpu_oh;
+ + 
+ + 
+ + /* Private functions */
+ + 
+ + /**
+ +  * _update_sysc_cache - return the module OCP_SYSCONFIG register, keep copy
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * Load the current value of the hwmod OCP_SYSCONFIG register into the
+ +  * struct omap_hwmod for later use.  Returns -EINVAL if the hwmod has no
+ +  * OCP_SYSCONFIG register or 0 upon success.
+ +  */
+ + static int _update_sysc_cache(struct omap_hwmod *oh)
+ + {
+ + 	if (!oh->class->sysc) {
+ + 		WARN(1, "omap_hwmod: %s: cannot read OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	/* XXX ensure module interface clock is up */
+ + 
+ + 	oh->_sysc_cache = omap_hwmod_read(oh, oh->class->sysc->sysc_offs);
+ + 
+ + 	if (!(oh->class->sysc->sysc_flags & SYSC_NO_CACHE))
+ + 		oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED;
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * _write_sysconfig - write a value to the module's OCP_SYSCONFIG register
+ +  * @v: OCP_SYSCONFIG value to write
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * Write @v into the module class' OCP_SYSCONFIG register, if it has
+ +  * one.  No return value.
+ +  */
+ + static void _write_sysconfig(u32 v, struct omap_hwmod *oh)
+ + {
+ + 	if (!oh->class->sysc) {
+ + 		WARN(1, "omap_hwmod: %s: cannot write OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name);
+ + 		return;
+ + 	}
+ + 
+ + 	/* XXX ensure module interface clock is up */
+ + 
+ + 	/* Module might have lost context, always update cache and register */
+ + 	oh->_sysc_cache = v;
+ + 	omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs);
+ + }
+ + 
+ + /**
+ +  * _set_master_standbymode: set the OCP_SYSCONFIG MIDLEMODE field in @v
+ +  * @oh: struct omap_hwmod *
+ +  * @standbymode: MIDLEMODE field bits
+ +  * @v: pointer to register contents to modify
+ +  *
+ +  * Update the master standby mode bits in @v to be @standbymode for
+ +  * the @oh hwmod.  Does not write to the hardware.  Returns -EINVAL
+ +  * upon error or 0 upon success.
+ +  */
+ + static int _set_master_standbymode(struct omap_hwmod *oh, u8 standbymode,
+ + 				   u32 *v)
+ + {
+ + 	u32 mstandby_mask;
+ + 	u8 mstandby_shift;
+ + 
+ + 	if (!oh->class->sysc ||
+ + 	    !(oh->class->sysc->sysc_flags & SYSC_HAS_MIDLEMODE))
+ + 		return -EINVAL;
+ + 
+ + 	if (!oh->class->sysc->sysc_fields) {
+ + 		WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	mstandby_shift = oh->class->sysc->sysc_fields->midle_shift;
+ + 	mstandby_mask = (0x3 << mstandby_shift);
+ + 
+ + 	*v &= ~mstandby_mask;
+ + 	*v |= __ffs(standbymode) << mstandby_shift;
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * _set_slave_idlemode: set the OCP_SYSCONFIG SIDLEMODE field in @v
+ +  * @oh: struct omap_hwmod *
+ +  * @idlemode: SIDLEMODE field bits
+ +  * @v: pointer to register contents to modify
+ +  *
+ +  * Update the slave idle mode bits in @v to be @idlemode for the @oh
+ +  * hwmod.  Does not write to the hardware.  Returns -EINVAL upon error
+ +  * or 0 upon success.
+ +  */
+ + static int _set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode, u32 *v)
+ + {
+ + 	u32 sidle_mask;
+ + 	u8 sidle_shift;
+ + 
+ + 	if (!oh->class->sysc ||
+ + 	    !(oh->class->sysc->sysc_flags & SYSC_HAS_SIDLEMODE))
+ + 		return -EINVAL;
+ + 
+ + 	if (!oh->class->sysc->sysc_fields) {
+ + 		WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	sidle_shift = oh->class->sysc->sysc_fields->sidle_shift;
+ + 	sidle_mask = (0x3 << sidle_shift);
+ + 
+ + 	*v &= ~sidle_mask;
+ + 	*v |= __ffs(idlemode) << sidle_shift;
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * _set_clockactivity: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v
+ +  * @oh: struct omap_hwmod *
+ +  * @clockact: CLOCKACTIVITY field bits
+ +  * @v: pointer to register contents to modify
+ +  *
+ +  * Update the clockactivity mode bits in @v to be @clockact for the
+ +  * @oh hwmod.  Used for additional powersaving on some modules.  Does
+ +  * not write to the hardware.  Returns -EINVAL upon error or 0 upon
+ +  * success.
+ +  */
+ + static int _set_clockactivity(struct omap_hwmod *oh, u8 clockact, u32 *v)
+ + {
+ + 	u32 clkact_mask;
+ + 	u8  clkact_shift;
+ + 
+ + 	if (!oh->class->sysc ||
+ + 	    !(oh->class->sysc->sysc_flags & SYSC_HAS_CLOCKACTIVITY))
+ + 		return -EINVAL;
+ + 
+ + 	if (!oh->class->sysc->sysc_fields) {
+ + 		WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	clkact_shift = oh->class->sysc->sysc_fields->clkact_shift;
+ + 	clkact_mask = (0x3 << clkact_shift);
+ + 
+ + 	*v &= ~clkact_mask;
+ + 	*v |= clockact << clkact_shift;
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * _set_softreset: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v
+ +  * @oh: struct omap_hwmod *
+ +  * @v: pointer to register contents to modify
+ +  *
+ +  * Set the SOFTRESET bit in @v for hwmod @oh.  Returns -EINVAL upon
+ +  * error or 0 upon success.
+ +  */
+ + static int _set_softreset(struct omap_hwmod *oh, u32 *v)
+ + {
+ + 	u32 softrst_mask;
+ + 
+ + 	if (!oh->class->sysc ||
+ + 	    !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET))
+ + 		return -EINVAL;
+ + 
+ + 	if (!oh->class->sysc->sysc_fields) {
+ + 		WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift);
+ + 
+ + 	*v |= softrst_mask;
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * _set_module_autoidle: set the OCP_SYSCONFIG AUTOIDLE field in @v
+ +  * @oh: struct omap_hwmod *
+ +  * @autoidle: desired AUTOIDLE bitfield value (0 or 1)
+ +  * @v: pointer to register contents to modify
+ +  *
+ +  * Update the module autoidle bit in @v to be @autoidle for the @oh
+ +  * hwmod.  The autoidle bit controls whether the module can gate
+ +  * internal clocks automatically when it isn't doing anything; the
+ +  * exact function of this bit varies on a per-module basis.  This
+ +  * function does not write to the hardware.  Returns -EINVAL upon
+ +  * error or 0 upon success.
+ +  */
+ + static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle,
+ + 				u32 *v)
+ + {
+ + 	u32 autoidle_mask;
+ + 	u8 autoidle_shift;
+ + 
+ + 	if (!oh->class->sysc ||
+ + 	    !(oh->class->sysc->sysc_flags & SYSC_HAS_AUTOIDLE))
+ + 		return -EINVAL;
+ + 
+ + 	if (!oh->class->sysc->sysc_fields) {
+ + 		WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	autoidle_shift = oh->class->sysc->sysc_fields->autoidle_shift;
+ + 	autoidle_mask = (0x1 << autoidle_shift);
+ + 
+ + 	*v &= ~autoidle_mask;
+ + 	*v |= autoidle << autoidle_shift;
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * _set_idle_ioring_wakeup - enable/disable IO pad wakeup on hwmod idle for mux
+ +  * @oh: struct omap_hwmod *
+ +  * @set_wake: bool value indicating to set (true) or clear (false) wakeup enable
+ +  *
+ +  * Set or clear the I/O pad wakeup flag in the mux entries for the
+ +  * hwmod @oh.  This function changes the @oh->mux->pads_dynamic array
+ +  * in memory.  If the hwmod is currently idled, and the new idle
+ +  * values don't match the previous ones, this function will also
+ +  * update the SCM PADCTRL registers.  Otherwise, if the hwmod is not
+ +  * currently idled, this function won't touch the hardware: the new
+ +  * mux settings are written to the SCM PADCTRL registers when the
+ +  * hwmod is idled.  No return value.
+ +  */
+ + static void _set_idle_ioring_wakeup(struct omap_hwmod *oh, bool set_wake)
+ + {
+ + 	struct omap_device_pad *pad;
+ + 	bool change = false;
+ + 	u16 prev_idle;
+ + 	int j;
+ + 
+ + 	if (!oh->mux || !oh->mux->enabled)
+ + 		return;
+ + 
+ + 	for (j = 0; j < oh->mux->nr_pads_dynamic; j++) {
+ + 		pad = oh->mux->pads_dynamic[j];
+ + 
+ + 		if (!(pad->flags & OMAP_DEVICE_PAD_WAKEUP))
+ + 			continue;
+ + 
+ + 		prev_idle = pad->idle;
+ + 
+ + 		if (set_wake)
+ + 			pad->idle |= OMAP_WAKEUP_EN;
+ + 		else
+ + 			pad->idle &= ~OMAP_WAKEUP_EN;
+ + 
+ + 		if (prev_idle != pad->idle)
+ + 			change = true;
+ + 	}
+ + 
+ + 	if (change && oh->_state == _HWMOD_STATE_IDLE)
+ + 		omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE);
+ + }
+ + 
+ + /**
+ +  * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * Allow the hardware module @oh to send wakeups.  Returns -EINVAL
+ +  * upon error or 0 upon success.
+ +  */
+ + static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
+ + {
+ + 	if (!oh->class->sysc ||
+ + 	    !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) ||
+ + 	      (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) ||
+ + 	      (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)))
+ + 		return -EINVAL;
+ + 
+ + 	if (!oh->class->sysc->sysc_fields) {
+ + 		WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)
+ + 		*v |= 0x1 << oh->class->sysc->sysc_fields->enwkup_shift;
+ + 
+ + 	if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
+ + 		_set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
+ + 	if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
+ + 		_set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
+ + 
+ + 	/* XXX test pwrdm_get_wken for this hwmod's subsystem */
+ + 
+ + 	oh->_int_flags |= _HWMOD_WAKEUP_ENABLED;
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * _disable_wakeup: clear OCP_SYSCONFIG.ENAWAKEUP bit in the hardware
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * Prevent the hardware module @oh to send wakeups.  Returns -EINVAL
+ +  * upon error or 0 upon success.
+ +  */
+ + static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
+ + {
+ + 	if (!oh->class->sysc ||
+ + 	    !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) ||
+ + 	      (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) ||
+ + 	      (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)))
+ + 		return -EINVAL;
+ + 
+ + 	if (!oh->class->sysc->sysc_fields) {
+ + 		WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)
+ + 		*v &= ~(0x1 << oh->class->sysc->sysc_fields->enwkup_shift);
+ + 
+ + 	if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
+ + 		_set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v);
+ + 	if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
+ + 		_set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
+ + 
+ + 	/* XXX test pwrdm_get_wken for this hwmod's subsystem */
+ + 
+ + 	oh->_int_flags &= ~_HWMOD_WAKEUP_ENABLED;
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * _add_initiator_dep: prevent @oh from smart-idling while @init_oh is active
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * Prevent the hardware module @oh from entering idle while the
+ +  * hardare module initiator @init_oh is active.  Useful when a module
+ +  * will be accessed by a particular initiator (e.g., if a module will
+ +  * be accessed by the IVA, there should be a sleepdep between the IVA
+ +  * initiator and the module).  Only applies to modules in smart-idle
+ +  * mode.  If the clockdomain is marked as not needing autodeps, return
+ +  * 0 without doing anything.  Otherwise, returns -EINVAL upon error or
+ +  * passes along clkdm_add_sleepdep() value upon success.
+ +  */
+ + static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
+ + {
+ + 	if (!oh->_clk)
+ + 		return -EINVAL;
+ + 
+ + 	if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS)
+ + 		return 0;
+ + 
+ + 	return clkdm_add_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm);
+ + }
+ + 
+ + /**
+ +  * _del_initiator_dep: allow @oh to smart-idle even if @init_oh is active
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * Allow the hardware module @oh to enter idle while the hardare
+ +  * module initiator @init_oh is active.  Useful when a module will not
+ +  * be accessed by a particular initiator (e.g., if a module will not
+ +  * be accessed by the IVA, there should be no sleepdep between the IVA
+ +  * initiator and the module).  Only applies to modules in smart-idle
+ +  * mode.  If the clockdomain is marked as not needing autodeps, return
+ +  * 0 without doing anything.  Returns -EINVAL upon error or passes
+ +  * along clkdm_del_sleepdep() value upon success.
+ +  */
+ + static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
+ + {
+ + 	if (!oh->_clk)
+ + 		return -EINVAL;
+ + 
+ + 	if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS)
+ + 		return 0;
+ + 
+ + 	return clkdm_del_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm);
+ + }
+ + 
+ + /**
+ +  * _init_main_clk - get a struct clk * for the the hwmod's main functional clk
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * Called from _init_clocks().  Populates the @oh _clk (main
+ +  * functional clock pointer) if a main_clk is present.  Returns 0 on
+ +  * success or -EINVAL on error.
+ +  */
+ + static int _init_main_clk(struct omap_hwmod *oh)
+ + {
+ + 	int ret = 0;
+ + 
+ + 	if (!oh->main_clk)
+ + 		return 0;
+ + 
+ + 	oh->_clk = omap_clk_get_by_name(oh->main_clk);
+ + 	if (!oh->_clk) {
+ + 		pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n",
+ + 			   oh->name, oh->main_clk);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	if (!oh->_clk->clkdm)
+ + 		pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n",
+ + 			   oh->main_clk, oh->_clk->name);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * _init_interface_clks - get a struct clk * for the the hwmod's interface clks
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * Called from _init_clocks().  Populates the @oh OCP slave interface
+ +  * clock pointers.  Returns 0 on success or -EINVAL on error.
+ +  */
+ + static int _init_interface_clks(struct omap_hwmod *oh)
+ + {
+ + 	struct clk *c;
+ + 	int i;
+ + 	int ret = 0;
+ + 
+ + 	if (oh->slaves_cnt == 0)
+ + 		return 0;
+ + 
+ + 	for (i = 0; i < oh->slaves_cnt; i++) {
+ + 		struct omap_hwmod_ocp_if *os = oh->slaves[i];
+ + 
+ + 		if (!os->clk)
+ + 			continue;
+ + 
+ + 		c = omap_clk_get_by_name(os->clk);
+ + 		if (!c) {
+ + 			pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n",
+ + 				   oh->name, os->clk);
+ + 			ret = -EINVAL;
+ + 		}
+ + 		os->_clk = c;
+ + 	}
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * _init_opt_clk - get a struct clk * for the the hwmod's optional clocks
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * Called from _init_clocks().  Populates the @oh omap_hwmod_opt_clk
+ +  * clock pointers.  Returns 0 on success or -EINVAL on error.
+ +  */
+ + static int _init_opt_clks(struct omap_hwmod *oh)
+ + {
+ + 	struct omap_hwmod_opt_clk *oc;
+ + 	struct clk *c;
+ + 	int i;
+ + 	int ret = 0;
+ + 
+ + 	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) {
+ + 		c = omap_clk_get_by_name(oc->clk);
+ + 		if (!c) {
+ + 			pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n",
+ + 				   oh->name, oc->clk);
+ + 			ret = -EINVAL;
+ + 		}
+ + 		oc->_clk = c;
+ + 	}
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * _enable_clocks - enable hwmod main clock and interface clocks
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * Enables all clocks necessary for register reads and writes to succeed
+ +  * on the hwmod @oh.  Returns 0.
+ +  */
+ + static int _enable_clocks(struct omap_hwmod *oh)
+ + {
+ + 	int i;
+ + 
+ + 	pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name);
+ + 
+ + 	if (oh->_clk)
+ + 		clk_enable(oh->_clk);
+ + 
+ + 	if (oh->slaves_cnt > 0) {
+ + 		for (i = 0; i < oh->slaves_cnt; i++) {
+ + 			struct omap_hwmod_ocp_if *os = oh->slaves[i];
+ + 			struct clk *c = os->_clk;
+ + 
+ + 			if (c && (os->flags & OCPIF_SWSUP_IDLE))
+ + 				clk_enable(c);
+ + 		}
+ + 	}
+ + 
+ + 	/* The opt clocks are controlled by the device driver. */
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * _disable_clocks - disable hwmod main clock and interface clocks
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * Disables the hwmod @oh main functional and interface clocks.  Returns 0.
+ +  */
+ + static int _disable_clocks(struct omap_hwmod *oh)
+ + {
+ + 	int i;
+ + 
+ + 	pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name);
+ + 
+ + 	if (oh->_clk)
+ + 		clk_disable(oh->_clk);
+ + 
+ + 	if (oh->slaves_cnt > 0) {
+ + 		for (i = 0; i < oh->slaves_cnt; i++) {
+ + 			struct omap_hwmod_ocp_if *os = oh->slaves[i];
+ + 			struct clk *c = os->_clk;
+ + 
+ + 			if (c && (os->flags & OCPIF_SWSUP_IDLE))
+ + 				clk_disable(c);
+ + 		}
+ + 	}
+ + 
+ + 	/* The opt clocks are controlled by the device driver. */
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static void _enable_optional_clocks(struct omap_hwmod *oh)
+ + {
+ + 	struct omap_hwmod_opt_clk *oc;
+ + 	int i;
+ + 
+ + 	pr_debug("omap_hwmod: %s: enabling optional clocks\n", oh->name);
+ + 
+ + 	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
+ + 		if (oc->_clk) {
+ + 			pr_debug("omap_hwmod: enable %s:%s\n", oc->role,
+ + 				 oc->_clk->name);
+ + 			clk_enable(oc->_clk);
+ + 		}
+ + }
+ + 
+ + static void _disable_optional_clocks(struct omap_hwmod *oh)
+ + {
+ + 	struct omap_hwmod_opt_clk *oc;
+ + 	int i;
+ + 
+ + 	pr_debug("omap_hwmod: %s: disabling optional clocks\n", oh->name);
+ + 
+ + 	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
+ + 		if (oc->_clk) {
+ + 			pr_debug("omap_hwmod: disable %s:%s\n", oc->role,
+ + 				 oc->_clk->name);
+ + 			clk_disable(oc->_clk);
+ + 		}
+ + }
+ + 
+ + /**
+ +  * _enable_module - enable CLKCTRL modulemode on OMAP4
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * Enables the PRCM module mode related to the hwmod @oh.
+ +  * No return value.
+ +  */
+ + static void _enable_module(struct omap_hwmod *oh)
+ + {
+ + 	if (!oh->clkdm || !oh->prcm.omap4.modulemode)
+ + 		return;
+ + 
+ + 	pr_debug("omap_hwmod: %s: _enable_module: %d\n",
+ + 			oh->name, oh->prcm.omap4.modulemode);
+ + 
+ + 	omap4_cminst_module_enable(oh->prcm.omap4.modulemode,
+ + 			oh->clkdm->prcm_partition,
+ + 			oh->clkdm->cm_inst,
+ + 			oh->clkdm->clkdm_offs,
+ + 			oh->prcm.omap4.clkctrl_offs);
+ + }
+ + 
+ + /**
+ +  * _omap4_wait_target_disable - wait for a module to be disabled on OMAP4
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * Wait for a module @oh to enter slave idle.  Returns 0 if the module
+ +  * does not have an IDLEST bit or if the module successfully enters
+ +  * slave idle; otherwise, pass along the return value of the
+ +  * appropriate *_cm*_wait_module_idle() function.
+ +  */
+ + static int _omap4_wait_target_disable(struct omap_hwmod *oh)
+ + {
+ + 	if (!oh)
+ + 		return -EINVAL;
+ + 
+ + 	if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
+ + 		return 0;
+ + 
+ + 	if (oh->flags & HWMOD_NO_IDLEST)
+ + 		return 0;
+ + 
+ + 	return omap4_cminst_wait_module_idle(oh->clkdm->prcm_partition,
+ + 					     oh->clkdm->cm_inst,
+ + 					     oh->clkdm->clkdm_offs,
+ + 					     oh->prcm.omap4.clkctrl_offs);
+ + }
+ + 
+ + /**
+ +  * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * Disable the PRCM module mode related to the hwmod @oh.
+ +  * Return EINVAL if the modulemode is not supported and 0 in case of success.
+ +  */
+ + static int _omap4_disable_module(struct omap_hwmod *oh)
+ + {
+ + 	int v;
+ + 
+ + 	if (!oh->clkdm || !oh->prcm.omap4.modulemode)
+ + 		return -EINVAL;
+ + 
+ + 	pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__);
+ + 
+ + 	omap4_cminst_module_disable(oh->clkdm->prcm_partition,
+ + 			oh->clkdm->cm_inst,
+ + 			oh->clkdm->clkdm_offs,
+ + 			oh->prcm.omap4.clkctrl_offs);
+ + 
+ + 	v = _omap4_wait_target_disable(oh);
+ + 	if (v)
+ + 		pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
+ + 				oh->name);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh
+ +  * @oh: struct omap_hwmod *oh
+ +  *
+ +  * Count and return the number of MPU IRQs associated with the hwmod
+ +  * @oh.  Used to allocate struct resource data.  Returns 0 if @oh is
+ +  * NULL.
+ +  */
+ + static int _count_mpu_irqs(struct omap_hwmod *oh)
+ + {
+ + 	struct omap_hwmod_irq_info *ohii;
+ + 	int i = 0;
+ + 
+ + 	if (!oh || !oh->mpu_irqs)
+ + 		return 0;
+ + 
+ + 	do {
+ + 		ohii = &oh->mpu_irqs[i++];
+ + 	} while (ohii->irq != -1);
+ + 
+ + 	return i-1;
+ + }
+ + 
+ + /**
+ +  * _count_sdma_reqs - count the number of SDMA request lines associated with @oh
+ +  * @oh: struct omap_hwmod *oh
+ +  *
+ +  * Count and return the number of SDMA request lines associated with
+ +  * the hwmod @oh.  Used to allocate struct resource data.  Returns 0
+ +  * if @oh is NULL.
+ +  */
+ + static int _count_sdma_reqs(struct omap_hwmod *oh)
+ + {
+ + 	struct omap_hwmod_dma_info *ohdi;
+ + 	int i = 0;
+ + 
+ + 	if (!oh || !oh->sdma_reqs)
+ + 		return 0;
+ + 
+ + 	do {
+ + 		ohdi = &oh->sdma_reqs[i++];
+ + 	} while (ohdi->dma_req != -1);
+ + 
+ + 	return i-1;
+ + }
+ + 
+ + /**
+ +  * _count_ocp_if_addr_spaces - count the number of address space entries for @oh
+ +  * @oh: struct omap_hwmod *oh
+ +  *
+ +  * Count and return the number of address space ranges associated with
+ +  * the hwmod @oh.  Used to allocate struct resource data.  Returns 0
+ +  * if @oh is NULL.
+ +  */
+ + static int _count_ocp_if_addr_spaces(struct omap_hwmod_ocp_if *os)
+ + {
+ + 	struct omap_hwmod_addr_space *mem;
+ + 	int i = 0;
+ + 
+ + 	if (!os || !os->addr)
+ + 		return 0;
+ + 
+ + 	do {
+ + 		mem = &os->addr[i++];
+ + 	} while (mem->pa_start != mem->pa_end);
+ + 
+ + 	return i-1;
+ + }
+ + 
+ + /**
+ +  * _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * Returns the array index of the OCP slave port that the MPU
+ +  * addresses the device on, or -EINVAL upon error or not found.
+ +  */
+ + static int __init _find_mpu_port_index(struct omap_hwmod *oh)
+ + {
+ + 	int i;
+ + 	int found = 0;
+ + 
+ + 	if (!oh || oh->slaves_cnt == 0)
+ + 		return -EINVAL;
+ + 
+ + 	for (i = 0; i < oh->slaves_cnt; i++) {
+ + 		struct omap_hwmod_ocp_if *os = oh->slaves[i];
+ + 
+ + 		if (os->user & OCP_USER_MPU) {
+ + 			found = 1;
+ + 			break;
+ + 		}
+ + 	}
+ + 
+ + 	if (found)
+ + 		pr_debug("omap_hwmod: %s: MPU OCP slave port ID  %d\n",
+ + 			 oh->name, i);
+ + 	else
+ + 		pr_debug("omap_hwmod: %s: no MPU OCP slave port found\n",
+ + 			 oh->name);
+ + 
+ + 	return (found) ? i : -EINVAL;
+ + }
+ + 
+ + /**
+ +  * _find_mpu_rt_base - find hwmod register target base addr accessible by MPU
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * Return the virtual address of the base of the register target of
+ +  * device @oh, or NULL on error.
+ +  */
+ + static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
+ + {
+ + 	struct omap_hwmod_ocp_if *os;
+ + 	struct omap_hwmod_addr_space *mem;
+ + 	int i = 0, found = 0;
+ + 	void __iomem *va_start;
+ + 
+ + 	if (!oh || oh->slaves_cnt == 0)
+ + 		return NULL;
+ + 
+ + 	os = oh->slaves[index];
+ + 
+ + 	if (!os->addr)
+ + 		return NULL;
+ + 
+ + 	do {
+ + 		mem = &os->addr[i++];
+ + 		if (mem->flags & ADDR_TYPE_RT)
+ + 			found = 1;
+ + 	} while (!found && mem->pa_start != mem->pa_end);
+ + 
+ + 	if (found) {
+ + 		va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
+ + 		if (!va_start) {
+ + 			pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name);
+ + 			return NULL;
+ + 		}
+ + 		pr_debug("omap_hwmod: %s: MPU register target at va %p\n",
+ + 			 oh->name, va_start);
+ + 	} else {
+ + 		pr_debug("omap_hwmod: %s: no MPU register target found\n",
+ + 			 oh->name);
+ + 	}
+ + 
+ + 	return (found) ? va_start : NULL;
+ + }
+ + 
+ + /**
+ +  * _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * If module is marked as SWSUP_SIDLE, force the module out of slave
+ +  * idle; otherwise, configure it for smart-idle.  If module is marked
+ +  * as SWSUP_MSUSPEND, force the module out of master standby;
+ +  * otherwise, configure it for smart-standby.  No return value.
+ +  */
+ + static void _enable_sysc(struct omap_hwmod *oh)
+ + {
+ + 	u8 idlemode, sf;
+ + 	u32 v;
+ + 
+ + 	if (!oh->class->sysc)
+ + 		return;
+ + 
+ + 	v = oh->_sysc_cache;
+ + 	sf = oh->class->sysc->sysc_flags;
+ + 
+ + 	if (sf & SYSC_HAS_SIDLEMODE) {
+ + 		idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ?
+ + 			HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART;
+ + 		_set_slave_idlemode(oh, idlemode, &v);
+ + 	}
+ + 
+ + 	if (sf & SYSC_HAS_MIDLEMODE) {
+ + 		if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
+ + 			idlemode = HWMOD_IDLEMODE_NO;
+ + 		} else {
+ + 			if (sf & SYSC_HAS_ENAWAKEUP)
+ + 				_enable_wakeup(oh, &v);
+ + 			if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
+ + 				idlemode = HWMOD_IDLEMODE_SMART_WKUP;
+ + 			else
+ + 				idlemode = HWMOD_IDLEMODE_SMART;
+ + 		}
+ + 		_set_master_standbymode(oh, idlemode, &v);
+ + 	}
+ + 
+ + 	/*
+ + 	 * XXX The clock framework should handle this, by
+ + 	 * calling into this code.  But this must wait until the
+ + 	 * clock structures are tagged with omap_hwmod entries
+ + 	 */
+ + 	if ((oh->flags & HWMOD_SET_DEFAULT_CLOCKACT) &&
+ + 	    (sf & SYSC_HAS_CLOCKACTIVITY))
+ + 		_set_clockactivity(oh, oh->class->sysc->clockact, &v);
+ + 
+ + 	/* If slave is in SMARTIDLE, also enable wakeup */
+ + 	if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE))
+ + 		_enable_wakeup(oh, &v);
+ + 
+ + 	_write_sysconfig(v, oh);
+ + 
+ + 	/*
+ + 	 * Set the autoidle bit only after setting the smartidle bit
+ + 	 * Setting this will not have any impact on the other modules.
+ + 	 */
+ + 	if (sf & SYSC_HAS_AUTOIDLE) {
+ + 		idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ?
+ + 			0 : 1;
+ + 		_set_module_autoidle(oh, idlemode, &v);
+ + 		_write_sysconfig(v, oh);
+ + 	}
+ + }
+ + 
+ + /**
+ +  * _idle_sysc - try to put a module into idle via OCP_SYSCONFIG
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * If module is marked as SWSUP_SIDLE, force the module into slave
+ +  * idle; otherwise, configure it for smart-idle.  If module is marked
+ +  * as SWSUP_MSUSPEND, force the module into master standby; otherwise,
+ +  * configure it for smart-standby.  No return value.
+ +  */
+ + static void _idle_sysc(struct omap_hwmod *oh)
+ + {
+ + 	u8 idlemode, sf;
+ + 	u32 v;
+ + 
+ + 	if (!oh->class->sysc)
+ + 		return;
+ + 
+ + 	v = oh->_sysc_cache;
+ + 	sf = oh->class->sysc->sysc_flags;
+ + 
+ + 	if (sf & SYSC_HAS_SIDLEMODE) {
+ + 		idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ?
+ + 			HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART;
+ + 		_set_slave_idlemode(oh, idlemode, &v);
+ + 	}
+ + 
+ + 	if (sf & SYSC_HAS_MIDLEMODE) {
+ + 		if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
+ + 			idlemode = HWMOD_IDLEMODE_FORCE;
+ + 		} else {
+ + 			if (sf & SYSC_HAS_ENAWAKEUP)
+ + 				_enable_wakeup(oh, &v);
+ + 			if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
+ + 				idlemode = HWMOD_IDLEMODE_SMART_WKUP;
+ + 			else
+ + 				idlemode = HWMOD_IDLEMODE_SMART;
+ + 		}
+ + 		_set_master_standbymode(oh, idlemode, &v);
+ + 	}
+ + 
+ + 	/* If slave is in SMARTIDLE, also enable wakeup */
+ + 	if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE))
+ + 		_enable_wakeup(oh, &v);
+ + 
+ + 	_write_sysconfig(v, oh);
+ + }
+ + 
+ + /**
+ +  * _shutdown_sysc - force a module into idle via OCP_SYSCONFIG
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * Force the module into slave idle and master suspend. No return
+ +  * value.
+ +  */
+ + static void _shutdown_sysc(struct omap_hwmod *oh)
+ + {
+ + 	u32 v;
+ + 	u8 sf;
+ + 
+ + 	if (!oh->class->sysc)
+ + 		return;
+ + 
+ + 	v = oh->_sysc_cache;
+ + 	sf = oh->class->sysc->sysc_flags;
+ + 
+ + 	if (sf & SYSC_HAS_SIDLEMODE)
+ + 		_set_slave_idlemode(oh, HWMOD_IDLEMODE_FORCE, &v);
+ + 
+ + 	if (sf & SYSC_HAS_MIDLEMODE)
+ + 		_set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v);
+ + 
+ + 	if (sf & SYSC_HAS_AUTOIDLE)
+ + 		_set_module_autoidle(oh, 1, &v);
+ + 
+ + 	_write_sysconfig(v, oh);
+ + }
+ + 
+ + /**
+ +  * _lookup - find an omap_hwmod by name
+ +  * @name: find an omap_hwmod by name
+ +  *
+ +  * Return a pointer to an omap_hwmod by name, or NULL if not found.
+ +  */
+ + static struct omap_hwmod *_lookup(const char *name)
+ + {
+ + 	struct omap_hwmod *oh, *temp_oh;
+ + 
+ + 	oh = NULL;
+ + 
+ + 	list_for_each_entry(temp_oh, &omap_hwmod_list, node) {
+ + 		if (!strcmp(name, temp_oh->name)) {
+ + 			oh = temp_oh;
+ + 			break;
+ + 		}
+ + 	}
+ + 
+ + 	return oh;
+ + }
+ + /**
+ +  * _init_clkdm - look up a clockdomain name, store pointer in omap_hwmod
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * Convert a clockdomain name stored in a struct omap_hwmod into a
+ +  * clockdomain pointer, and save it into the struct omap_hwmod.
+ +  * return -EINVAL if clkdm_name does not exist or if the lookup failed.
+ +  */
+ + static int _init_clkdm(struct omap_hwmod *oh)
+ + {
+ + 	if (!oh->clkdm_name) {
+ + 		pr_warning("omap_hwmod: %s: no clkdm_name\n", oh->name);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	oh->clkdm = clkdm_lookup(oh->clkdm_name);
+ + 	if (!oh->clkdm) {
+ + 		pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n",
+ + 			oh->name, oh->clkdm_name);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	pr_debug("omap_hwmod: %s: associated to clkdm %s\n",
+ + 		oh->name, oh->clkdm_name);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * _init_clocks - clk_get() all clocks associated with this hwmod. Retrieve as
+ +  * well the clockdomain.
+ +  * @oh: struct omap_hwmod *
+ +  * @data: not used; pass NULL
+ +  *
+ +  * Called by omap_hwmod_setup_*() (after omap2_clk_init()).
+ +  * Resolves all clock names embedded in the hwmod.  Returns 0 on
+ +  * success, or a negative error code on failure.
+ +  */
+ + static int _init_clocks(struct omap_hwmod *oh, void *data)
+ + {
+ + 	int ret = 0;
+ + 
+ + 	if (oh->_state != _HWMOD_STATE_REGISTERED)
+ + 		return 0;
+ + 
+ + 	pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name);
+ + 
+ + 	ret |= _init_main_clk(oh);
+ + 	ret |= _init_interface_clks(oh);
+ + 	ret |= _init_opt_clks(oh);
+ + 	ret |= _init_clkdm(oh);
+ + 
+ + 	if (!ret)
+ + 		oh->_state = _HWMOD_STATE_CLKS_INITED;
+ + 	else
+ + 		pr_warning("omap_hwmod: %s: cannot _init_clocks\n", oh->name);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * _wait_target_ready - wait for a module to leave slave idle
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * Wait for a module @oh to leave slave idle.  Returns 0 if the module
+ +  * does not have an IDLEST bit or if the module successfully leaves
+ +  * slave idle; otherwise, pass along the return value of the
+ +  * appropriate *_cm*_wait_module_ready() function.
+ +  */
+ + static int _wait_target_ready(struct omap_hwmod *oh)
+ + {
+ + 	struct omap_hwmod_ocp_if *os;
+ + 	int ret;
+ + 
+ + 	if (!oh)
+ + 		return -EINVAL;
+ + 
+ + 	if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
+ + 		return 0;
+ + 
+ + 	os = oh->slaves[oh->_mpu_port_index];
+ + 
+ + 	if (oh->flags & HWMOD_NO_IDLEST)
+ + 		return 0;
+ + 
+ + 	/* XXX check module SIDLEMODE */
+ + 
+ + 	/* XXX check clock enable states */
+ + 
+ + 	if (!oh->clkdm)
+ + 		return -EINVAL;
+ + 
+ + 	ret = omap4_cminst_wait_module_ready(oh->clkdm->prcm_partition,
+ + 					     oh->clkdm->cm_inst,
+ + 					     oh->clkdm->clkdm_offs,
+ + 					     oh->prcm.omap4.clkctrl_offs);
+ + 	
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * _lookup_hardreset - fill register bit info for this hwmod/reset line
+ +  * @oh: struct omap_hwmod *
+ +  * @name: name of the reset line in the context of this hwmod
+ +  * @ohri: struct omap_hwmod_rst_info * that this function will fill in
+ +  *
+ +  * Return the bit position of the reset line that match the
+ +  * input name. Return -ENOENT if not found.
+ +  */
+ + static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name,
+ + 			    struct omap_hwmod_rst_info *ohri)
+ + {
+ + 	int i;
+ + 
+ + 	for (i = 0; i < oh->rst_lines_cnt; i++) {
+ + 		const char *rst_line = oh->rst_lines[i].name;
+ + 		if (!strcmp(rst_line, name)) {
+ + 			ohri->rst_shift = oh->rst_lines[i].rst_shift;
+ + 			ohri->st_shift = oh->rst_lines[i].st_shift;
+ + 			pr_debug("omap_hwmod: %s: %s: %s: rst %d st %d\n",
+ + 				 oh->name, __func__, rst_line, ohri->rst_shift,
+ + 				 ohri->st_shift);
+ + 
+ + 			return 0;
+ + 		}
+ + 	}
+ + 
+ + 	return -ENOENT;
+ + }
+ + 
+ + /**
+ +  * _assert_hardreset - assert the HW reset line of submodules
+ +  * contained in the hwmod module.
+ +  * @oh: struct omap_hwmod *
+ +  * @name: name of the reset line to lookup and assert
+ +  *
+ +  * Some IP like dsp, ipu or iva contain processor that require
+ +  * an HW reset line to be assert / deassert in order to enable fully
+ +  * the IP.
+ +  */
+ + static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
+ + {
+ + 	struct omap_hwmod_rst_info ohri;
+ + 	u8 ret;
+ + 
+ + 	if (!oh)
+ + 		return -EINVAL;
+ + 
+ + 	ret = _lookup_hardreset(oh, name, &ohri);
+ + 	if (IS_ERR_VALUE(ret))
+ + 		return ret;
+ + 
+ + 	/*
+ + 	 * In order to use omap4 prm code for am33xx family of devices,
+ + 	 * first check cpu_is_am33xx here.
+ + 	 *
+ + 	 * Note: cpu_is_omap34xx is true for am33xx device as well.
+ + 	 */
+ + 	return omap4_prminst_assert_hardreset(ohri.rst_shift,
+ + 				  oh->clkdm->pwrdm.ptr->prcm_partition,
+ + 				  oh->clkdm->pwrdm.ptr->prcm_offs,
+ + 				  oh->prcm.omap4.rstctrl_offs);
+ + 	
+ + }
+ + 
+ + /**
+ +  * _deassert_hardreset - deassert the HW reset line of submodules contained
+ +  * in the hwmod module.
+ +  * @oh: struct omap_hwmod *
+ +  * @name: name of the reset line to look up and deassert
+ +  *
+ +  * Some IP like dsp, ipu or iva contain processor that require
+ +  * an HW reset line to be assert / deassert in order to enable fully
+ +  * the IP.
+ +  */
+ + static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
+ + {
+ + 	struct omap_hwmod_rst_info ohri;
+ + 	int ret;
+ + 
+ + 	if (!oh)
+ + 		return -EINVAL;
+ + 
+ + 	ret = _lookup_hardreset(oh, name, &ohri);
+ + 	if (IS_ERR_VALUE(ret))
+ + 		return ret;
+ + 
+ + 	/*
+ + 	 * In order to use omap4 prm code for am33xx family of devices,
+ + 	 * first check cpu_is_am33xx here.
+ + 	 *
+ + 	 * Note: cpu_is_omap34xx is true for am33xx device as well.
+ + 	 */
+ + 	ret = omap4_prminst_deassert_hardreset(ohri.rst_shift,
+ + 			  ohri.st_shift,
+ + 			  oh->clkdm->pwrdm.ptr->prcm_partition,
+ + 			  oh->clkdm->pwrdm.ptr->prcm_offs,
+ + 			  oh->prcm.omap4.rstctrl_offs,
+ + 			  oh->prcm.omap4.rstst_offs);
+ + 	
+ + 	if (ret == -EBUSY)
+ + 		pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * _read_hardreset - read the HW reset line state of submodules
+ +  * contained in the hwmod module
+ +  * @oh: struct omap_hwmod *
+ +  * @name: name of the reset line to look up and read
+ +  *
+ +  * Return the state of the reset line.
+ +  */
+ + static int _read_hardreset(struct omap_hwmod *oh, const char *name)
+ + {
+ + 	struct omap_hwmod_rst_info ohri;
+ + 	u8 ret;
+ + 
+ + 	if (!oh)
+ + 		return -EINVAL;
+ + 
+ + 	ret = _lookup_hardreset(oh, name, &ohri);
+ + 	if (IS_ERR_VALUE(ret))
+ + 		return ret;
+ + 
+ + 	/*
+ + 	 * In order to use omap4 prm code for am33xx family of devices,
+ + 	 * first check cpu_is_am33xx here.
+ + 	 *
+ + 	 * Note: cpu_is_omap34xx is true for am33xx device as well.
+ + 	 */
+ + 	return omap4_prminst_is_hardreset_asserted(ohri.rst_shift,
+ + 			  oh->clkdm->pwrdm.ptr->prcm_partition,
+ + 			  oh->clkdm->pwrdm.ptr->prcm_offs,
+ + 			  oh->prcm.omap4.rstctrl_offs);
+ + }
+ + 
+ + /**
+ +  * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit.  hwmod must be
+ +  * enabled for this to work.  Returns -EINVAL if the hwmod cannot be
+ +  * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if
+ +  * the module did not reset in time, or 0 upon success.
+ +  *
+ +  * In OMAP3 a specific SYSSTATUS register is used to get the reset status.
+ +  * Starting in OMAP4, some IPs do not have SYSSTATUS registers and instead
+ +  * use the SYSCONFIG softreset bit to provide the status.
+ +  *
+ +  * Note that some IP like McBSP do have reset control but don't have
+ +  * reset status.
+ +  */
+ + static int _ocp_softreset(struct omap_hwmod *oh)
+ + {
+ + 	u32 v;
+ + 	int c = 0;
+ + 	int ret = 0;
+ + 
+ + 	if (!oh->class->sysc ||
+ + 	    !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET))
+ + 		return -EINVAL;
+ + 
+ + 	/* clocks must be on for this operation */
+ + 	if (oh->_state != _HWMOD_STATE_ENABLED) {
+ + 		pr_warning("omap_hwmod: %s: reset can only be entered from "
+ + 			   "enabled state\n", oh->name);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	/* For some modules, all optionnal clocks need to be enabled as well */
+ + 	if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)
+ + 		_enable_optional_clocks(oh);
+ + 
+ + 	pr_debug("omap_hwmod: %s: resetting via OCP SOFTRESET\n", oh->name);
+ + 
+ + 	v = oh->_sysc_cache;
+ + 	ret = _set_softreset(oh, &v);
+ + 	if (ret)
+ + 		goto dis_opt_clks;
+ + 	_write_sysconfig(v, oh);
+ + 
+ + 	if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)
+ + 		omap_test_timeout((omap_hwmod_read(oh,
+ + 						    oh->class->sysc->syss_offs)
+ + 				   & SYSS_RESETDONE_MASK),
+ + 				  MAX_MODULE_SOFTRESET_WAIT, c);
+ + 	else if (oh->class->sysc->sysc_flags & SYSC_HAS_RESET_STATUS)
+ + 		omap_test_timeout(!(omap_hwmod_read(oh,
+ + 						     oh->class->sysc->sysc_offs)
+ + 				   & SYSC_TYPE2_SOFTRESET_MASK),
+ + 				  MAX_MODULE_SOFTRESET_WAIT, c);
+ + 
+ + 	if (c == MAX_MODULE_SOFTRESET_WAIT)
+ + 		pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n",
+ + 			   oh->name, MAX_MODULE_SOFTRESET_WAIT);
+ + 	else
+ + 		pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c);
+ + 
+ + 	/*
+ + 	 * XXX add _HWMOD_STATE_WEDGED for modules that don't come back from
+ + 	 * _wait_target_ready() or _reset()
+ + 	 */
+ + 
+ + 	ret = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
+ + 
+ + dis_opt_clks:
+ + 	if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)
+ + 		_disable_optional_clocks(oh);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * _reset - reset an omap_hwmod
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * Resets an omap_hwmod @oh.  The default software reset mechanism for
+ +  * most OMAP IP blocks is triggered via the OCP_SYSCONFIG.SOFTRESET
+ +  * bit.  However, some hwmods cannot be reset via this method: some
+ +  * are not targets and therefore have no OCP header registers to
+ +  * access; others (like the IVA) have idiosyncratic reset sequences.
+ +  * So for these relatively rare cases, custom reset code can be
+ +  * supplied in the struct omap_hwmod_class .reset function pointer.
+ +  * Passes along the return value from either _reset() or the custom
+ +  * reset function - these must return -EINVAL if the hwmod cannot be
+ +  * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if
+ +  * the module did not reset in time, or 0 upon success.
+ +  */
+ + static int _reset(struct omap_hwmod *oh)
+ + {
+ + 	int ret;
+ + 
+ + 	pr_debug("omap_hwmod: %s: resetting\n", oh->name);
+ + 
+ + 	ret = (oh->class->reset) ? oh->class->reset(oh) : _ocp_softreset(oh);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * _enable - enable an omap_hwmod
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * Enables an omap_hwmod @oh such that the MPU can access the hwmod's
+ +  * register target.  Returns -EINVAL if the hwmod is in the wrong
+ +  * state or passes along the return value of _wait_target_ready().
+ +  */
+ + static int _enable(struct omap_hwmod *oh)
+ + {
+ + 	int r;
+ + 	int hwsup = 0;
+ + 
+ + 	pr_debug("omap_hwmod: %s: enabling\n", oh->name);
+ + 
+ + 	/*
+ + 	 * hwmods with HWMOD_INIT_NO_IDLE flag set are left
+ + 	 * in enabled state at init.
+ + 	 * Now that someone is really trying to enable them,
+ + 	 * just ensure that the hwmod mux is set.
+ + 	 */
+ + 	if (oh->_int_flags & _HWMOD_SKIP_ENABLE) {
+ + 		/*
+ + 		 * If the caller has mux data populated, do the mux'ing
+ + 		 * which wouldn't have been done as part of the _enable()
+ + 		 * done during setup.
+ + 		 */
+ + 		if (oh->mux)
+ + 			omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
+ + 
+ + 		oh->_int_flags &= ~_HWMOD_SKIP_ENABLE;
+ + 		return 0;
+ + 	}
+ + 
+ + 	if (oh->_state != _HWMOD_STATE_INITIALIZED &&
+ + 	    oh->_state != _HWMOD_STATE_IDLE &&
+ + 	    oh->_state != _HWMOD_STATE_DISABLED) {
+ + 		WARN(1, "omap_hwmod: %s: enabled state can only be entered "
+ + 		     "from initialized, idle, or disabled state\n", oh->name);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	/* Mux pins for device runtime if populated */
+ + 	if (oh->mux && (!oh->mux->enabled ||
+ + 			((oh->_state == _HWMOD_STATE_IDLE) &&
+ + 			 oh->mux->pads_dynamic)))
+ + 		omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
+ + 
+ + 	_add_initiator_dep(oh, mpu_oh);
+ + 
+ + 	if (oh->clkdm) {
+ + 		/*
+ + 		 * A clockdomain must be in SW_SUP before enabling
+ + 		 * completely the module. The clockdomain can be set
+ + 		 * in HW_AUTO only when the module become ready.
+ + 		 */
+ + 		hwsup = clkdm_in_hwsup(oh->clkdm);
+ + 	}
+ + 
+ + 	_enable_clocks(oh);
+ + 	_enable_module(oh);
+ + 
+ + 	/*
+ + 	 * If an IP contains only one HW reset line, then de-assert it in order
+ + 	 * to allow the module state transition. Otherwise the PRCM will return
+ + 	 * Intransition status, and the init will failed.
+ + 	 *
+ + 	 * TODO: Based on observation, on module enable sate, we can safely
+ + 	 *	assert the reset signal here (irrespective of idlemode state).
+ + 	 */
+ + 	if ((oh->_state == _HWMOD_STATE_INITIALIZED ||
+ + 	     oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1)
+ + 		_deassert_hardreset(oh, oh->rst_lines[0].name);
+ + 
+ + 	r = _wait_target_ready(oh);
+ + 	if (!r) {
+ + 		/*
+ + 		 * Set the clockdomain to HW_AUTO only if the target is ready,
+ + 		 * assuming that the previous state was HW_AUTO
+ + 		 */
+ + 		if (oh->clkdm && hwsup)
+ + 			clkdm_allow_idle(oh->clkdm);
+ + 
+ + 		oh->_state = _HWMOD_STATE_ENABLED;
+ + 
+ + 		/* Access the sysconfig only if the target is ready */
+ + 		if (oh->class->sysc) {
+ + 			if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED))
+ + 				_update_sysc_cache(oh);
+ + 			_enable_sysc(oh);
+ + 		}
+ + 	} else {
+ + 		_disable_clocks(oh);
+ + 		pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n",
+ + 			 oh->name, r);
+ + 
+ + 	}
+ + 
+ + 	return r;
+ + }
+ + 
+ + /**
+ +  * _idle - idle an omap_hwmod
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * Idles an omap_hwmod @oh.  This should be called once the hwmod has
+ +  * no further work.  Returns -EINVAL if the hwmod is in the wrong
+ +  * state or returns 0.
+ +  */
+ + static int _idle(struct omap_hwmod *oh)
+ + {
+ + 	pr_debug("omap_hwmod: %s: idling\n", oh->name);
+ + 
+ + 	if (oh->_state != _HWMOD_STATE_ENABLED) {
+ + 		WARN(1, "omap_hwmod: %s: idle state can only be entered from "
+ + 		     "enabled state\n", oh->name);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	/*
+ + 	 * FIXME: Due to AM33XX CPSW IP integration bug, it is required
+ + 	 * to assert ocp reset signal to the module before disabling it.
+ + 	 */
+ + 	if (oh->flags & HWMOD_SWSUP_RESET_BEFORE_IDLE)
+ + 		_reset(oh);
+ + 
+ + 	if (oh->class->sysc)
+ + 		_idle_sysc(oh);
+ + 	_del_initiator_dep(oh, mpu_oh);
+ + 
+ + 	_omap4_disable_module(oh);
+ + 
+ + 	/*
+ + 	 * The module must be in idle mode before disabling any parents
+ + 	 * clocks. Otherwise, the parent clock might be disabled before
+ + 	 * the module transition is done, and thus will prevent the
+ + 	 * transition to complete properly.
+ + 	 */
+ + 	_disable_clocks(oh);
+ + 	
+ + 	/* Mux pins for device idle if populated */
+ + 	if (oh->mux && oh->mux->pads_dynamic)
+ + 		omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE);
+ + 
+ + 	oh->_state = _HWMOD_STATE_IDLE;
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * omap_hwmod_set_ocp_autoidle - set the hwmod's OCP autoidle bit
+ +  * @oh: struct omap_hwmod *
+ +  * @autoidle: desired AUTOIDLE bitfield value (0 or 1)
+ +  *
+ +  * Sets the IP block's OCP autoidle bit in hardware, and updates our
+ +  * local copy. Intended to be used by drivers that require
+ +  * direct manipulation of the AUTOIDLE bits.
+ +  * Returns -EINVAL if @oh is null or is not in the ENABLED state, or passes
+ +  * along the return value from _set_module_autoidle().
+ +  *
+ +  * Any users of this function should be scrutinized carefully.
+ +  */
+ + int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle)
+ + {
+ + 	u32 v;
+ + 	int retval = 0;
+ + 	unsigned long flags;
+ + 
+ + 	if (!oh || oh->_state != _HWMOD_STATE_ENABLED)
+ + 		return -EINVAL;
+ + 
+ + 	spin_lock_irqsave(&oh->_lock, flags);
+ + 
+ + 	v = oh->_sysc_cache;
+ + 
+ + 	retval = _set_module_autoidle(oh, autoidle, &v);
+ + 
+ + 	if (!retval)
+ + 		_write_sysconfig(v, oh);
+ + 
+ + 	spin_unlock_irqrestore(&oh->_lock, flags);
+ + 
+ + 	return retval;
+ + }
+ + 
+ + /**
+ +  * _shutdown - shutdown an omap_hwmod
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * Shut down an omap_hwmod @oh.  This should be called when the driver
+ +  * used for the hwmod is removed or unloaded or if the driver is not
+ +  * used by the system.  Returns -EINVAL if the hwmod is in the wrong
+ +  * state or returns 0.
+ +  */
+ + static int _shutdown(struct omap_hwmod *oh)
+ + {
+ + 	int ret;
+ + 	u8 prev_state;
+ + 
+ + 	if (oh->_state != _HWMOD_STATE_IDLE &&
+ + 	    oh->_state != _HWMOD_STATE_ENABLED) {
+ + 		WARN(1, "omap_hwmod: %s: disabled state can only be entered "
+ + 		     "from idle, or enabled state\n", oh->name);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	pr_debug("omap_hwmod: %s: disabling\n", oh->name);
+ + 
+ + 	if (oh->class->pre_shutdown) {
+ + 		prev_state = oh->_state;
+ + 		if (oh->_state == _HWMOD_STATE_IDLE)
+ + 			_enable(oh);
+ + 		ret = oh->class->pre_shutdown(oh);
+ + 		if (ret) {
+ + 			if (prev_state == _HWMOD_STATE_IDLE)
+ + 				_idle(oh);
+ + 			return ret;
+ + 		}
+ + 	}
+ + 
+ + 	if (oh->class->sysc) {
+ + 		if (oh->_state == _HWMOD_STATE_IDLE)
+ + 			_enable(oh);
+ + 		_shutdown_sysc(oh);
+ + 	}
+ + 
+ + 	/* clocks and deps are already disabled in idle */
+ + 	if (oh->_state == _HWMOD_STATE_ENABLED) {
+ + 		_del_initiator_dep(oh, mpu_oh);
+ + 		/* XXX what about the other system initiators here? dma, dsp */
+ + 		_omap4_disable_module(oh);
+ + 		_disable_clocks(oh);
+ + 	}
+ + 	/* XXX Should this code also force-disable the optional clocks? */
+ + 
+ + 	/*
+ + 	 * If an IP contains only one HW reset line, then assert it
+ + 	 * after disabling the clocks and before shutting down the IP.
+ + 	 */
+ + 	if (oh->rst_lines_cnt == 1)
+ + 		_assert_hardreset(oh, oh->rst_lines[0].name);
+ + 
+ + 	/* Mux pins to safe mode or use populated off mode values */
+ + 	if (oh->mux)
+ + 		omap_hwmod_mux(oh->mux, _HWMOD_STATE_DISABLED);
+ + 
+ + 	oh->_state = _HWMOD_STATE_DISABLED;
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * _setup - do initial configuration of omap_hwmod
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh
+ +  * OCP_SYSCONFIG register.  Returns 0.
+ +  */
+ + static int _setup(struct omap_hwmod *oh, void *data)
+ + {
+ + 	int i, r;
+ + 	u8 postsetup_state;
+ + 
+ + 	if (oh->_state != _HWMOD_STATE_CLKS_INITED)
+ + 		return 0;
+ + 
+ + 	/* Set iclk autoidle mode */
+ + 	if (oh->slaves_cnt > 0) {
+ + 		for (i = 0; i < oh->slaves_cnt; i++) {
+ + 			struct omap_hwmod_ocp_if *os = oh->slaves[i];
+ + 			struct clk *c = os->_clk;
+ + 
+ + 			if (!c)
+ + 				continue;
+ + 
+ + 			if (os->flags & OCPIF_SWSUP_IDLE) {
+ + 				/* XXX omap_iclk_deny_idle(c); */
+ + 			} else {
+ + 				/* XXX omap_iclk_allow_idle(c); */
+ + 				clk_enable(c);
+ + 			}
+ + 		}
+ + 	}
+ + 
+ + 	oh->_state = _HWMOD_STATE_INITIALIZED;
+ + 
+ + 	/*
+ + 	 * In the case of hwmod with hardreset that should not be
+ + 	 * de-assert at boot time, we have to keep the module
+ + 	 * initialized, because we cannot enable it properly with the
+ + 	 * reset asserted. Exit without warning because that behavior is
+ + 	 * expected.
+ + 	 */
+ + 	if ((oh->flags & HWMOD_INIT_NO_RESET) && oh->rst_lines_cnt == 1)
+ + 		return 0;
+ + 
+ + 	r = _enable(oh);
+ + 	if (r) {
+ + 		pr_warning("omap_hwmod: %s: cannot be enabled (%d)\n",
+ + 			   oh->name, oh->_state);
+ + 		return 0;
+ + 	}
+ + 
+ + 	if (!(oh->flags & HWMOD_INIT_NO_RESET)) {
+ + 		_reset(oh);
+ + 
+ + 		/*
+ + 		 * OCP_SYSCONFIG bits need to be reprogrammed after a softreset.
+ + 		 * The _enable() function should be split to
+ + 		 * avoid the rewrite of the OCP_SYSCONFIG register.
+ + 		 */
+ + 		if (oh->class->sysc) {
+ + 			_update_sysc_cache(oh);
+ + 			_enable_sysc(oh);
+ + 		}
+ + 	}
+ + 
+ + 	postsetup_state = oh->_postsetup_state;
+ + 	if (postsetup_state == _HWMOD_STATE_UNKNOWN)
+ + 		postsetup_state = _HWMOD_STATE_ENABLED;
+ + 
+ + 	/*
+ + 	 * XXX HWMOD_INIT_NO_IDLE does not belong in hwmod data -
+ + 	 * it should be set by the core code as a runtime flag during startup
+ + 	 */
+ + 	if ((oh->flags & HWMOD_INIT_NO_IDLE) &&
+ + 	    (postsetup_state == _HWMOD_STATE_IDLE)) {
+ + 		oh->_int_flags |= _HWMOD_SKIP_ENABLE;
+ + 		postsetup_state = _HWMOD_STATE_ENABLED;
+ + 	}
+ + 
+ + 	if (postsetup_state == _HWMOD_STATE_IDLE)
+ + 		_idle(oh);
+ + 	else if (postsetup_state == _HWMOD_STATE_DISABLED)
+ + 		_shutdown(oh);
+ + 	else if (postsetup_state != _HWMOD_STATE_ENABLED)
+ + 		WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n",
+ + 		     oh->name, postsetup_state);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * _register - register a struct omap_hwmod
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * Registers the omap_hwmod @oh.  Returns -EEXIST if an omap_hwmod
+ +  * already has been registered by the same name; -EINVAL if the
+ +  * omap_hwmod is in the wrong state, if @oh is NULL, if the
+ +  * omap_hwmod's class field is NULL; if the omap_hwmod is missing a
+ +  * name, or if the omap_hwmod's class is missing a name; or 0 upon
+ +  * success.
+ +  *
+ +  * XXX The data should be copied into bootmem, so the original data
+ +  * should be marked __initdata and freed after init.  This would allow
+ +  * unneeded omap_hwmods to be freed on multi-OMAP configurations.  Note
+ +  * that the copy process would be relatively complex due to the large number
+ +  * of substructures.
+ +  */
+ + static int __init _register(struct omap_hwmod *oh)
+ + {
+ + 	int ms_id;
+ + 
+ + 	if (!oh || !oh->name || !oh->class || !oh->class->name ||
+ + 	    (oh->_state != _HWMOD_STATE_UNKNOWN))
+ + 		return -EINVAL;
+ + 
+ + 	pr_debug("omap_hwmod: %s: registering\n", oh->name);
+ + 
+ + 	if (_lookup(oh->name))
+ + 		return -EEXIST;
+ + 
+ + 	ms_id = _find_mpu_port_index(oh);
+ + 	if (!IS_ERR_VALUE(ms_id))
+ + 		oh->_mpu_port_index = ms_id;
+ + 	else
+ + 		oh->_int_flags |= _HWMOD_NO_MPU_PORT;
+ + 
+ + 	list_add_tail(&oh->node, &omap_hwmod_list);
+ + 
+ + 	spin_lock_init(&oh->_lock);
+ + 
+ + 	oh->_state = _HWMOD_STATE_REGISTERED;
+ + 
+ + 	/*
+ + 	 * XXX Rather than doing a strcmp(), this should test a flag
+ + 	 * set in the hwmod data, inserted by the autogenerator code.
+ + 	 */
+ + 	if (!strcmp(oh->name, MPU_INITIATOR_NAME))
+ + 		mpu_oh = oh;
+ + 
+ + 	return 0;
+ + }
+ + 
+ + 
+ + /* Public functions */
+ + 
+ + u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs)
+ + {
+ + 	if (oh->flags & HWMOD_16BIT_REG)
+ + 		return __raw_readw(oh->_mpu_rt_va + reg_offs);
+ + 	else
+ + 		return __raw_readl(oh->_mpu_rt_va + reg_offs);
+ + }
+ + 
+ + void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs)
+ + {
+ + 	if (oh->flags & HWMOD_16BIT_REG)
+ + 		__raw_writew(v, oh->_mpu_rt_va + reg_offs);
+ + 	else
+ + 		__raw_writel(v, oh->_mpu_rt_va + reg_offs);
+ + }
+ + 
+ + /**
+ +  * omap_hwmod_softreset - reset a module via SYSCONFIG.SOFTRESET bit
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * This is a public function exposed to drivers. Some drivers may need to do
+ +  * some settings before and after resetting the device.  Those drivers after
+ +  * doing the necessary settings could use this function to start a reset by
+ +  * setting the SYSCONFIG.SOFTRESET bit.
+ +  */
+ + int omap_hwmod_softreset(struct omap_hwmod *oh)
+ + {
+ + 	u32 v;
+ + 	int ret;
+ + 
+ + 	if (!oh || !(oh->_sysc_cache))
+ + 		return -EINVAL;
+ + 
+ + 	v = oh->_sysc_cache;
+ + 	ret = _set_softreset(oh, &v);
+ + 	if (ret)
+ + 		goto error;
+ + 	_write_sysconfig(v, oh);
+ + 
+ + error:
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * omap_hwmod_set_master_standbymode - set the hwmod's OCP master standbymode
+ +  * @oh: struct omap_hwmod *
+ +  * @standbymode: MSTANDBY field bits (shifted to bit 0)
+ +  *
+ +  * Sets the IP block's OCP master staandby mode in hardware, and updates our
+ +  * local copy.  Intended to be used by drivers that have some erratum
+ +  * that requires direct manipulation of the MSTANDBY bits.  Returns
+ +  * -EINVAL if @oh is null, or passes along the return value from
+ +  * _set_master_standbymode().
+ +  *
+ +  */
+ + int omap_hwmod_set_master_standbymode(struct omap_hwmod *oh, u8 standbymode)
+ + {
+ + 	u32 v;
+ + 	int retval = 0;
+ + 
+ + 	if (!oh)
+ + 		return -EINVAL;
+ + 
+ + 	v = oh->_sysc_cache;
+ + 
+ + 	retval = _set_master_standbymode(oh, standbymode, &v);
+ + 	if (!retval)
+ + 		_write_sysconfig(v, oh);
+ + 
+ + 	return retval;
+ + }
+ + 
+ + /**
+ +  * omap_hwmod_set_slave_idlemode - set the hwmod's OCP slave idlemode
+ +  * @oh: struct omap_hwmod *
+ +  * @idlemode: SIDLEMODE field bits (shifted to bit 0)
+ +  *
+ +  * Sets the IP block's OCP slave idlemode in hardware, and updates our
+ +  * local copy.  Intended to be used by drivers that have some erratum
+ +  * that requires direct manipulation of the SIDLEMODE bits.  Returns
+ +  * -EINVAL if @oh is null, or passes along the return value from
+ +  * _set_slave_idlemode().
+ +  *
+ +  * XXX Does this function have any current users?  If not, we should
+ +  * remove it; it is better to let the rest of the hwmod code handle this.
+ +  * Any users of this function should be scrutinized carefully.
+ +  */
+ + int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode)
+ + {
+ + 	u32 v;
+ + 	int retval = 0;
+ + 
+ + 	if (!oh)
+ + 		return -EINVAL;
+ + 
+ + 	v = oh->_sysc_cache;
+ + 
+ + 	retval = _set_slave_idlemode(oh, idlemode, &v);
+ + 	if (!retval)
+ + 		_write_sysconfig(v, oh);
+ + 
+ + 	return retval;
+ + }
+ + 
+ + /**
+ +  * omap_hwmod_lookup - look up a registered omap_hwmod by name
+ +  * @name: name of the omap_hwmod to look up
+ +  *
+ +  * Given a @name of an omap_hwmod, return a pointer to the registered
+ +  * struct omap_hwmod *, or NULL upon error.
+ +  */
+ + struct omap_hwmod *omap_hwmod_lookup(const char *name)
+ + {
+ + 	struct omap_hwmod *oh;
+ + 
+ + 	if (!name)
+ + 		return NULL;
+ + 
+ + 	oh = _lookup(name);
+ + 
+ + 	return oh;
+ + }
+ + 
+ + /**
+ +  * omap_hwmod_for_each - call function for each registered omap_hwmod
+ +  * @fn: pointer to a callback function
+ +  * @data: void * data to pass to callback function
+ +  *
+ +  * Call @fn for each registered omap_hwmod, passing @data to each
+ +  * function.  @fn must return 0 for success or any other value for
+ +  * failure.  If @fn returns non-zero, the iteration across omap_hwmods
+ +  * will stop and the non-zero return value will be passed to the
+ +  * caller of omap_hwmod_for_each().  @fn is called with
+ +  * omap_hwmod_for_each() held.
+ +  */
+ + int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
+ + 			void *data)
+ + {
+ + 	struct omap_hwmod *temp_oh;
+ + 	int ret = 0;
+ + 
+ + 	if (!fn)
+ + 		return -EINVAL;
+ + 
+ + 	list_for_each_entry(temp_oh, &omap_hwmod_list, node) {
+ + 		ret = (*fn)(temp_oh, data);
+ + 		if (ret)
+ + 			break;
+ + 	}
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * omap_hwmod_register - register an array of hwmods
+ +  * @ohs: pointer to an array of omap_hwmods to register
+ +  *
+ +  * Intended to be called early in boot before the clock framework is
+ +  * initialized.  If @ohs is not null, will register all omap_hwmods
+ +  * listed in @ohs that are valid for this chip.  Returns 0.
+ +  */
+ + int __init omap_hwmod_register(struct omap_hwmod **ohs)
+ + {
+ + 	int r, i;
+ + 
+ + 	if (!ohs)
+ + 		return 0;
+ + 
+ + 	i = 0;
+ + 	do {
+ + 		r = _register(ohs[i]);
+ + 		WARN(r, "omap_hwmod: %s: _register returned %d\n", ohs[i]->name,
+ + 		     r);
+ + 	} while (ohs[++i]);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /*
+ +  * _populate_mpu_rt_base - populate the virtual address for a hwmod
+ +  *
+ +  * Must be called only from omap_hwmod_setup_*() so ioremap works properly.
+ +  * Assumes the caller takes care of locking if needed.
+ +  */
+ + static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data)
+ + {
+ + 	if (oh->_state != _HWMOD_STATE_REGISTERED)
+ + 		return 0;
+ + 
+ + 	if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
+ + 		return 0;
+ + 
+ + 	oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * omap_hwmod_setup_one - set up a single hwmod
+ +  * @oh_name: const char * name of the already-registered hwmod to set up
+ +  *
+ +  * Must be called after omap2_clk_init().  Resolves the struct clk
+ +  * names to struct clk pointers for each registered omap_hwmod.  Also
+ +  * calls _setup() on each hwmod.  Returns -EINVAL upon error or 0 upon
+ +  * success.
+ +  */
+ + int __init omap_hwmod_setup_one(const char *oh_name)
+ + {
+ + 	struct omap_hwmod *oh;
+ + 	int r;
+ + 
+ + 	pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__);
+ + 
+ + 	if (!mpu_oh) {
+ + 		pr_err("omap_hwmod: %s: cannot setup_one: MPU initiator hwmod %s not yet registered\n",
+ + 		       oh_name, MPU_INITIATOR_NAME);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	oh = _lookup(oh_name);
+ + 	if (!oh) {
+ + 		WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh)
+ + 		omap_hwmod_setup_one(MPU_INITIATOR_NAME);
+ + 
+ + 	r = _populate_mpu_rt_base(oh, NULL);
+ + 	if (IS_ERR_VALUE(r)) {
+ + 		WARN(1, "omap_hwmod: %s: couldn't set mpu_rt_base\n", oh_name);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	r = _init_clocks(oh, NULL);
+ + 	if (IS_ERR_VALUE(r)) {
+ + 		WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh_name);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	_setup(oh, NULL);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * omap_hwmod_setup - do some post-clock framework initialization
+ +  *
+ +  * Must be called after omap2_clk_init().  Resolves the struct clk names
+ +  * to struct clk pointers for each registered omap_hwmod.  Also calls
+ +  * _setup() on each hwmod.  Returns 0 upon success.
+ +  */
+ + static int __init omap_hwmod_setup_all(void)
+ + {
+ + 	int r;
+ + 
+ + 	if (!mpu_oh) {
+ + 		pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n",
+ + 		       __func__, MPU_INITIATOR_NAME);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	r = omap_hwmod_for_each(_populate_mpu_rt_base, NULL);
+ + 
+ + 	r = omap_hwmod_for_each(_init_clocks, NULL);
+ + 	WARN(IS_ERR_VALUE(r),
+ + 	     "omap_hwmod: %s: _init_clocks failed\n", __func__);
+ + 
+ + 	omap_hwmod_for_each(_setup, NULL);
+ + 
+ + 	return 0;
+ + }
+ + core_initcall(omap_hwmod_setup_all);
+ + 
+ + /**
+ +  * omap_hwmod_enable - enable an omap_hwmod
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * Enable an omap_hwmod @oh.  Intended to be called by omap_device_enable().
+ +  * Returns -EINVAL on error or passes along the return value from _enable().
+ +  */
+ + int omap_hwmod_enable(struct omap_hwmod *oh)
+ + {
+ + 	int r;
+ + 	unsigned long flags;
+ + 
+ + 	if (!oh)
+ + 		return -EINVAL;
+ + 
+ + 	spin_lock_irqsave(&oh->_lock, flags);
+ + 	r = _enable(oh);
+ + 	spin_unlock_irqrestore(&oh->_lock, flags);
+ + 
+ + 	return r;
+ + }
+ + 
+ + /**
+ +  * omap_hwmod_idle - idle an omap_hwmod
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * Idle an omap_hwmod @oh.  Intended to be called by omap_device_idle().
+ +  * Returns -EINVAL on error or passes along the return value from _idle().
+ +  */
+ + int omap_hwmod_idle(struct omap_hwmod *oh)
+ + {
+ + 	unsigned long flags;
+ + 
+ + 	if (!oh)
+ + 		return -EINVAL;
+ + 
+ + 	spin_lock_irqsave(&oh->_lock, flags);
+ + 	_idle(oh);
+ + 	spin_unlock_irqrestore(&oh->_lock, flags);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * omap_hwmod_shutdown - shutdown an omap_hwmod
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * Shutdown an omap_hwmod @oh.  Intended to be called by
+ +  * omap_device_shutdown().  Returns -EINVAL on error or passes along
+ +  * the return value from _shutdown().
+ +  */
+ + int omap_hwmod_shutdown(struct omap_hwmod *oh)
+ + {
+ + 	unsigned long flags;
+ + 
+ + 	if (!oh)
+ + 		return -EINVAL;
+ + 
+ + 	spin_lock_irqsave(&oh->_lock, flags);
+ + 	_shutdown(oh);
+ + 	spin_unlock_irqrestore(&oh->_lock, flags);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * omap_hwmod_enable_clocks - enable main_clk, all interface clocks
+ +  * @oh: struct omap_hwmod *oh
+ +  *
+ +  * Intended to be called by the omap_device code.
+ +  */
+ + int omap_hwmod_enable_clocks(struct omap_hwmod *oh)
+ + {
+ + 	unsigned long flags;
+ + 
+ + 	spin_lock_irqsave(&oh->_lock, flags);
+ + 	_enable_clocks(oh);
+ + 	spin_unlock_irqrestore(&oh->_lock, flags);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * omap_hwmod_disable_clocks - disable main_clk, all interface clocks
+ +  * @oh: struct omap_hwmod *oh
+ +  *
+ +  * Intended to be called by the omap_device code.
+ +  */
+ + int omap_hwmod_disable_clocks(struct omap_hwmod *oh)
+ + {
+ + 	unsigned long flags;
+ + 
+ + 	spin_lock_irqsave(&oh->_lock, flags);
+ + 	_disable_clocks(oh);
+ + 	spin_unlock_irqrestore(&oh->_lock, flags);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * omap_hwmod_ocp_barrier - wait for posted writes against the hwmod to complete
+ +  * @oh: struct omap_hwmod *oh
+ +  *
+ +  * Intended to be called by drivers and core code when all posted
+ +  * writes to a device must complete before continuing further
+ +  * execution (for example, after clearing some device IRQSTATUS
+ +  * register bits)
+ +  *
+ +  * XXX what about targets with multiple OCP threads?
+ +  */
+ + void omap_hwmod_ocp_barrier(struct omap_hwmod *oh)
+ + {
+ + 	BUG_ON(!oh);
+ + 
+ + 	if (!oh->class->sysc || !oh->class->sysc->sysc_flags) {
+ + 		WARN(1, "omap_device: %s: OCP barrier impossible due to "
+ + 		      "device configuration\n", oh->name);
+ + 		return;
+ + 	}
+ + 
+ + 	/*
+ + 	 * Forces posted writes to complete on the OCP thread handling
+ + 	 * register writes
+ + 	 */
+ + 	omap_hwmod_read(oh, oh->class->sysc->sysc_offs);
+ + }
+ + 
+ + /**
+ +  * omap_hwmod_reset - reset the hwmod
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * Under some conditions, a driver may wish to reset the entire device.
+ +  * Called from omap_device code.  Returns -EINVAL on error or passes along
+ +  * the return value from _reset().
+ +  */
+ + int omap_hwmod_reset(struct omap_hwmod *oh)
+ + {
+ + 	int r;
+ + 	unsigned long flags;
+ + 
+ + 	if (!oh)
+ + 		return -EINVAL;
+ + 
+ + 	spin_lock_irqsave(&oh->_lock, flags);
+ + 	r = _reset(oh);
+ + 	spin_unlock_irqrestore(&oh->_lock, flags);
+ + 
+ + 	return r;
+ + }
+ + 
+ + /**
+ +  * omap_hwmod_count_resources - count number of struct resources needed by hwmod
+ +  * @oh: struct omap_hwmod *
+ +  * @res: pointer to the first element of an array of struct resource to fill
+ +  *
+ +  * Count the number of struct resource array elements necessary to
+ +  * contain omap_hwmod @oh resources.  Intended to be called by code
+ +  * that registers omap_devices.  Intended to be used to determine the
+ +  * size of a dynamically-allocated struct resource array, before
+ +  * calling omap_hwmod_fill_resources().  Returns the number of struct
+ +  * resource array elements needed.
+ +  *
+ +  * XXX This code is not optimized.  It could attempt to merge adjacent
+ +  * resource IDs.
+ +  *
+ +  */
+ + int omap_hwmod_count_resources(struct omap_hwmod *oh)
+ + {
+ + 	int ret, i;
+ + 
+ + 	ret = _count_mpu_irqs(oh) + _count_sdma_reqs(oh);
+ + 
+ + 	for (i = 0; i < oh->slaves_cnt; i++)
+ + 		ret += _count_ocp_if_addr_spaces(oh->slaves[i]);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * omap_hwmod_fill_resources - fill struct resource array with hwmod data
+ +  * @oh: struct omap_hwmod *
+ +  * @res: pointer to the first element of an array of struct resource to fill
+ +  *
+ +  * Fill the struct resource array @res with resource data from the
+ +  * omap_hwmod @oh.  Intended to be called by code that registers
+ +  * omap_devices.  See also omap_hwmod_count_resources().  Returns the
+ +  * number of array elements filled.
+ +  */
+ + int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
+ + {
+ + 	int i, j, mpu_irqs_cnt, sdma_reqs_cnt;
+ + 	int r = 0;
+ + 
+ + 	/* For each IRQ, DMA, memory area, fill in array.*/
+ + 
+ + 	mpu_irqs_cnt = _count_mpu_irqs(oh);
+ + 	for (i = 0; i < mpu_irqs_cnt; i++) {
+ + 		(res + r)->name = (oh->mpu_irqs + i)->name;
+ + 		(res + r)->start = (oh->mpu_irqs + i)->irq;
+ + 		(res + r)->end = (oh->mpu_irqs + i)->irq;
+ + 		(res + r)->flags = IORESOURCE_IRQ;
+ + 		r++;
+ + 	}
+ + 
+ + 	sdma_reqs_cnt = _count_sdma_reqs(oh);
+ + 	for (i = 0; i < sdma_reqs_cnt; i++) {
+ + 		(res + r)->name = (oh->sdma_reqs + i)->name;
+ + 		(res + r)->start = (oh->sdma_reqs + i)->dma_req;
+ + 		(res + r)->end = (oh->sdma_reqs + i)->dma_req;
+ + 		(res + r)->flags = IORESOURCE_DMA;
+ + 		r++;
+ + 	}
+ + 
+ + 	for (i = 0; i < oh->slaves_cnt; i++) {
+ + 		struct omap_hwmod_ocp_if *os;
+ + 		int addr_cnt;
+ + 
+ + 		os = oh->slaves[i];
+ + 		addr_cnt = _count_ocp_if_addr_spaces(os);
+ + 
+ + 		for (j = 0; j < addr_cnt; j++) {
+ + 			(res + r)->name = (os->addr + j)->name;
+ + 			(res + r)->start = (os->addr + j)->pa_start;
+ + 			(res + r)->end = (os->addr + j)->pa_end;
+ + 			(res + r)->flags = IORESOURCE_MEM;
+ + 			r++;
+ + 		}
+ + 	}
+ + 
+ + 	return r;
+ + }
+ + 
+ + /**
+ +  * omap_hwmod_get_pwrdm - return pointer to this module's main powerdomain
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * Return the powerdomain pointer associated with the OMAP module
+ +  * @oh's main clock.  If @oh does not have a main clk, return the
+ +  * powerdomain associated with the interface clock associated with the
+ +  * module's MPU port. (XXX Perhaps this should use the SDMA port
+ +  * instead?)  Returns NULL on error, or a struct powerdomain * on
+ +  * success.
+ +  */
+ + struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh)
+ + {
+ + 	struct clk *c;
+ + 
+ + 	if (!oh)
+ + 		return NULL;
+ + 
+ + 	if (oh->_clk) {
+ + 		c = oh->_clk;
+ + 	} else {
+ + 		if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
+ + 			return NULL;
+ + 		c = oh->slaves[oh->_mpu_port_index]->_clk;
+ + 	}
+ + 
+ + 	if (!c->clkdm)
+ + 		return NULL;
+ + 
+ + 	return c->clkdm->pwrdm.ptr;
+ + 
+ + }
+ + 
+ + /**
+ +  * omap_hwmod_get_mpu_rt_va - return the module's base address (for the MPU)
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * Returns the virtual address corresponding to the beginning of the
+ +  * module's register target, in the address range that is intended to
+ +  * be used by the MPU.  Returns the virtual address upon success or NULL
+ +  * upon error.
+ +  */
+ + void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh)
+ + {
+ + 	if (!oh)
+ + 		return NULL;
+ + 
+ + 	if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
+ + 		return NULL;
+ + 
+ + 	if (oh->_state == _HWMOD_STATE_UNKNOWN)
+ + 		return NULL;
+ + 
+ + 	return oh->_mpu_rt_va;
+ + }
+ + 
+ + /**
+ +  * omap_hwmod_add_initiator_dep - add sleepdep from @init_oh to @oh
+ +  * @oh: struct omap_hwmod *
+ +  * @init_oh: struct omap_hwmod * (initiator)
+ +  *
+ +  * Add a sleep dependency between the initiator @init_oh and @oh.
+ +  * Intended to be called by DSP/Bridge code via platform_data for the
+ +  * DSP case; and by the DMA code in the sDMA case.  DMA code, *Bridge
+ +  * code needs to add/del initiator dependencies dynamically
+ +  * before/after accessing a device.  Returns the return value from
+ +  * _add_initiator_dep().
+ +  *
+ +  * XXX Keep a usecount in the clockdomain code
+ +  */
+ + int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh,
+ + 				 struct omap_hwmod *init_oh)
+ + {
+ + 	return _add_initiator_dep(oh, init_oh);
+ + }
+ + 
+ + /*
+ +  * XXX what about functions for drivers to save/restore ocp_sysconfig
+ +  * for context save/restore operations?
+ +  */
+ + 
+ + /**
+ +  * omap_hwmod_del_initiator_dep - remove sleepdep from @init_oh to @oh
+ +  * @oh: struct omap_hwmod *
+ +  * @init_oh: struct omap_hwmod * (initiator)
+ +  *
+ +  * Remove a sleep dependency between the initiator @init_oh and @oh.
+ +  * Intended to be called by DSP/Bridge code via platform_data for the
+ +  * DSP case; and by the DMA code in the sDMA case.  DMA code, *Bridge
+ +  * code needs to add/del initiator dependencies dynamically
+ +  * before/after accessing a device.  Returns the return value from
+ +  * _del_initiator_dep().
+ +  *
+ +  * XXX Keep a usecount in the clockdomain code
+ +  */
+ + int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh,
+ + 				 struct omap_hwmod *init_oh)
+ + {
+ + 	return _del_initiator_dep(oh, init_oh);
+ + }
+ + 
+ + /**
+ +  * omap_hwmod_enable_wakeup - allow device to wake up the system
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * Sets the module OCP socket ENAWAKEUP bit to allow the module to
+ +  * send wakeups to the PRCM.  Eventually this should sets PRCM wakeup
+ +  * registers to cause the PRCM to receive wakeup events from the
+ +  * module.  Does not set any wakeup routing registers beyond this
+ +  * point - if the module is to wake up any other module or subsystem,
+ +  * that must be set separately.  Called by omap_device code.  Returns
+ +  * -EINVAL on error or 0 upon success.
+ +  */
+ + int omap_hwmod_enable_wakeup(struct omap_hwmod *oh)
+ + {
+ + 	unsigned long flags;
+ + 	u32 v;
+ + 
+ + 	if (!oh->class->sysc ||
+ + 	    !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP))
+ + 		return -EINVAL;
+ + 
+ + 	spin_lock_irqsave(&oh->_lock, flags);
+ + 	v = oh->_sysc_cache;
+ + 	_enable_wakeup(oh, &v);
+ + 	_write_sysconfig(v, oh);
+ + 	_set_idle_ioring_wakeup(oh, true);
+ + 	spin_unlock_irqrestore(&oh->_lock, flags);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * omap_hwmod_disable_wakeup - prevent device from waking the system
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * Clears the module OCP socket ENAWAKEUP bit to prevent the module
+ +  * from sending wakeups to the PRCM.  Eventually this should clear
+ +  * PRCM wakeup registers to cause the PRCM to ignore wakeup events
+ +  * from the module.  Does not set any wakeup routing registers beyond
+ +  * this point - if the module is to wake up any other module or
+ +  * subsystem, that must be set separately.  Called by omap_device
+ +  * code.  Returns -EINVAL on error or 0 upon success.
+ +  */
+ + int omap_hwmod_disable_wakeup(struct omap_hwmod *oh)
+ + {
+ + 	unsigned long flags;
+ + 	u32 v;
+ + 
+ + 	if (!oh->class->sysc ||
+ + 	    !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP))
+ + 		return -EINVAL;
+ + 
+ + 	spin_lock_irqsave(&oh->_lock, flags);
+ + 	v = oh->_sysc_cache;
+ + 	_disable_wakeup(oh, &v);
+ + 	_write_sysconfig(v, oh);
+ + 	_set_idle_ioring_wakeup(oh, false);
+ + 	spin_unlock_irqrestore(&oh->_lock, flags);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * omap_hwmod_assert_hardreset - assert the HW reset line of submodules
+ +  * contained in the hwmod module.
+ +  * @oh: struct omap_hwmod *
+ +  * @name: name of the reset line to lookup and assert
+ +  *
+ +  * Some IP like dsp, ipu or iva contain processor that require
+ +  * an HW reset line to be assert / deassert in order to enable fully
+ +  * the IP.  Returns -EINVAL if @oh is null or if the operation is not
+ +  * yet supported on this OMAP; otherwise, passes along the return value
+ +  * from _assert_hardreset().
+ +  */
+ + int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name)
+ + {
+ + 	int ret;
+ + 	unsigned long flags;
+ + 
+ + 	if (!oh)
+ + 		return -EINVAL;
+ + 
+ + 	spin_lock_irqsave(&oh->_lock, flags);
+ + 	ret = _assert_hardreset(oh, name);
+ + 	spin_unlock_irqrestore(&oh->_lock, flags);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * omap_hwmod_deassert_hardreset - deassert the HW reset line of submodules
+ +  * contained in the hwmod module.
+ +  * @oh: struct omap_hwmod *
+ +  * @name: name of the reset line to look up and deassert
+ +  *
+ +  * Some IP like dsp, ipu or iva contain processor that require
+ +  * an HW reset line to be assert / deassert in order to enable fully
+ +  * the IP.  Returns -EINVAL if @oh is null or if the operation is not
+ +  * yet supported on this OMAP; otherwise, passes along the return value
+ +  * from _deassert_hardreset().
+ +  */
+ + int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name)
+ + {
+ + 	int ret;
+ + 	unsigned long flags;
+ + 
+ + 	if (!oh)
+ + 		return -EINVAL;
+ + 
+ + 	spin_lock_irqsave(&oh->_lock, flags);
+ + 	ret = _deassert_hardreset(oh, name);
+ + 	spin_unlock_irqrestore(&oh->_lock, flags);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * omap_hwmod_read_hardreset - read the HW reset line state of submodules
+ +  * contained in the hwmod module
+ +  * @oh: struct omap_hwmod *
+ +  * @name: name of the reset line to look up and read
+ +  *
+ +  * Return the current state of the hwmod @oh's reset line named @name:
+ +  * returns -EINVAL upon parameter error or if this operation
+ +  * is unsupported on the current OMAP; otherwise, passes along the return
+ +  * value from _read_hardreset().
+ +  */
+ + int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name)
+ + {
+ + 	int ret;
+ + 	unsigned long flags;
+ + 
+ + 	if (!oh)
+ + 		return -EINVAL;
+ + 
+ + 	spin_lock_irqsave(&oh->_lock, flags);
+ + 	ret = _read_hardreset(oh, name);
+ + 	spin_unlock_irqrestore(&oh->_lock, flags);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + 
+ + /**
+ +  * omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname
+ +  * @classname: struct omap_hwmod_class name to search for
+ +  * @fn: callback function pointer to call for each hwmod in class @classname
+ +  * @user: arbitrary context data to pass to the callback function
+ +  *
+ +  * For each omap_hwmod of class @classname, call @fn.
+ +  * If the callback function returns something other than
+ +  * zero, the iterator is terminated, and the callback function's return
+ +  * value is passed back to the caller.  Returns 0 upon success, -EINVAL
+ +  * if @classname or @fn are NULL, or passes back the error code from @fn.
+ +  */
+ + int omap_hwmod_for_each_by_class(const char *classname,
+ + 				 int (*fn)(struct omap_hwmod *oh,
+ + 					   void *user),
+ + 				 void *user)
+ + {
+ + 	struct omap_hwmod *temp_oh;
+ + 	int ret = 0;
+ + 
+ + 	if (!classname || !fn)
+ + 		return -EINVAL;
+ + 
+ + 	pr_debug("omap_hwmod: %s: looking for modules of class %s\n",
+ + 		 __func__, classname);
+ + 
+ + 	list_for_each_entry(temp_oh, &omap_hwmod_list, node) {
+ + 		if (!strcmp(temp_oh->class->name, classname)) {
+ + 			pr_debug("omap_hwmod: %s: %s: calling callback fn\n",
+ + 				 __func__, temp_oh->name);
+ + 			ret = (*fn)(temp_oh, user);
+ + 			if (ret)
+ + 				break;
+ + 		}
+ + 	}
+ + 
+ + 	if (ret)
+ + 		pr_debug("omap_hwmod: %s: iterator terminated early: %d\n",
+ + 			 __func__, ret);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * omap_hwmod_set_postsetup_state - set the post-_setup() state for this hwmod
+ +  * @oh: struct omap_hwmod *
+ +  * @state: state that _setup() should leave the hwmod in
+ +  *
+ +  * Sets the hwmod state that @oh will enter at the end of _setup()
+ +  * (called by omap_hwmod_setup_*()).  Only valid to call between
+ +  * calling omap_hwmod_register() and omap_hwmod_setup_*().  Returns
+ +  * 0 upon success or -EINVAL if there is a problem with the arguments
+ +  * or if the hwmod is in the wrong state.
+ +  */
+ + int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state)
+ + {
+ + 	int ret;
+ + 	unsigned long flags;
+ + 
+ + 	if (!oh)
+ + 		return -EINVAL;
+ + 
+ + 	if (state != _HWMOD_STATE_DISABLED &&
+ + 	    state != _HWMOD_STATE_ENABLED &&
+ + 	    state != _HWMOD_STATE_IDLE)
+ + 		return -EINVAL;
+ + 
+ + 	spin_lock_irqsave(&oh->_lock, flags);
+ + 
+ + 	if (oh->_state != _HWMOD_STATE_REGISTERED) {
+ + 		ret = -EINVAL;
+ + 		goto ohsps_unlock;
+ + 	}
+ + 
+ + 	oh->_postsetup_state = state;
+ + 	ret = 0;
+ + 
+ + ohsps_unlock:
+ + 	spin_unlock_irqrestore(&oh->_lock, flags);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * omap_hwmod_get_context_loss_count - get lost context count
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * Query the powerdomain of of @oh to get the context loss
+ +  * count for this device.
+ +  *
+ +  * Returns the context loss count of the powerdomain assocated with @oh
+ +  * upon success, or zero if no powerdomain exists for @oh.
+ +  */
+ + int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh)
+ + {
+ + 	struct powerdomain *pwrdm;
+ + 	int ret = 0;
+ + 
+ + 	pwrdm = omap_hwmod_get_pwrdm(oh);
+ + 	if (pwrdm)
+ + 		ret = pwrdm_get_context_loss_count(pwrdm);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * omap_hwmod_no_setup_reset - prevent a hwmod from being reset upon setup
+ +  * @oh: struct omap_hwmod *
+ +  *
+ +  * Prevent the hwmod @oh from being reset during the setup process.
+ +  * Intended for use by board-*.c files on boards with devices that
+ +  * cannot tolerate being reset.  Must be called before the hwmod has
+ +  * been set up.  Returns 0 upon success or negative error code upon
+ +  * failure.
+ +  */
+ + int omap_hwmod_no_setup_reset(struct omap_hwmod *oh)
+ + {
+ + 	if (!oh)
+ + 		return -EINVAL;
+ + 
+ + 	if (oh->_state != _HWMOD_STATE_REGISTERED) {
+ + 		pr_err("omap_hwmod: %s: cannot prevent setup reset; in wrong state\n",
+ + 			oh->name);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	oh->flags |= HWMOD_INIT_NO_RESET;
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * omap_hwmod_pad_route_irq - route an I/O pad wakeup to a particular MPU IRQ
+ +  * @oh: struct omap_hwmod * containing hwmod mux entries
+ +  * @pad_idx: array index in oh->mux of the hwmod mux entry to route wakeup
+ +  * @irq_idx: the hwmod mpu_irqs array index of the IRQ to trigger on wakeup
+ +  *
+ +  * When an I/O pad wakeup arrives for the dynamic or wakeup hwmod mux
+ +  * entry number @pad_idx for the hwmod @oh, trigger the interrupt
+ +  * service routine for the hwmod's mpu_irqs array index @irq_idx.  If
+ +  * this function is not called for a given pad_idx, then the ISR
+ +  * associated with @oh's first MPU IRQ will be triggered when an I/O
+ +  * pad wakeup occurs on that pad.  Note that @pad_idx is the index of
+ +  * the _dynamic or wakeup_ entry: if there are other entries not
+ +  * marked with OMAP_DEVICE_PAD_WAKEUP or OMAP_DEVICE_PAD_REMUX, these
+ +  * entries are NOT COUNTED in the dynamic pad index.  This function
+ +  * must be called separately for each pad that requires its interrupt
+ +  * to be re-routed this way.  Returns -EINVAL if there is an argument
+ +  * problem or if @oh does not have hwmod mux entries or MPU IRQs;
+ +  * returns -ENOMEM if memory cannot be allocated; or 0 upon success.
+ +  *
+ +  * XXX This function interface is fragile.  Rather than using array
+ +  * indexes, which are subject to unpredictable change, it should be
+ +  * using hwmod IRQ names, and some other stable key for the hwmod mux
+ +  * pad records.
+ +  */
+ + int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx)
+ + {
+ + 	int nr_irqs;
+ + 
+ + 	might_sleep();
+ + 
+ + 	if (!oh || !oh->mux || !oh->mpu_irqs || pad_idx < 0 ||
+ + 	    pad_idx >= oh->mux->nr_pads_dynamic)
+ + 		return -EINVAL;
+ + 
+ + 	/* Check the number of available mpu_irqs */
+ + 	for (nr_irqs = 0; oh->mpu_irqs[nr_irqs].irq >= 0; nr_irqs++)
+ + 		;
+ + 
+ + 	if (irq_idx >= nr_irqs)
+ + 		return -EINVAL;
+ + 
+ + 	if (!oh->mux->irqs) {
+ + 		/* XXX What frees this? */
+ + 		oh->mux->irqs = kzalloc(sizeof(int) * oh->mux->nr_pads_dynamic,
+ + 			GFP_KERNEL);
+ + 		if (!oh->mux->irqs)
+ + 			return -ENOMEM;
+ + 	}
+ + 	oh->mux->irqs[pad_idx] = irq_idx;
+ + 
+ + 	return 0;
+ + }
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_hwmod_common_data.c linux-3.2.1/arch/arm/mach-ckb_3352/omap_hwmod_common_data.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_hwmod_common_data.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/omap_hwmod_common_data.c	2014-11-25 13:19:15.027074032 +0900
+ ***************
+ *** 0 ****
+ --- 1,77 ----
+ + /*
+ +  * omap_hwmod common data structures
+ +  *
+ +  * Copyright (C) 2010 Texas Instruments, Inc.
+ +  * Thara Gopinath <thara@ti.com>
+ +  * Benoît Cousson
+ +  *
+ +  * Copyright (C) 2010 Nokia Corporation
+ +  * Paul Walmsley
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  *
+ +  * This data/structures are to be used while defining OMAP on-chip module
+ +  * data and their integration with other OMAP modules and Linux.
+ +  */
+ + 
+ + #include <plat/omap_hwmod.h>
+ + 
+ + #include "omap_hwmod_common_data.h"
+ + 
+ + /**
+ +  * struct omap_hwmod_sysc_type1 - TYPE1 sysconfig scheme.
+ +  *
+ +  * To be used by hwmod structure to specify the sysconfig offsets
+ +  * if the device ip is compliant with the original PRCM protocol
+ +  * defined for OMAP2420.
+ +  */
+ + struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1 = {
+ + 	.midle_shift	= SYSC_TYPE1_MIDLEMODE_SHIFT,
+ + 	.clkact_shift	= SYSC_TYPE1_CLOCKACTIVITY_SHIFT,
+ + 	.sidle_shift	= SYSC_TYPE1_SIDLEMODE_SHIFT,
+ + 	.enwkup_shift	= SYSC_TYPE1_ENAWAKEUP_SHIFT,
+ + 	.srst_shift	= SYSC_TYPE1_SOFTRESET_SHIFT,
+ + 	.autoidle_shift	= SYSC_TYPE1_AUTOIDLE_SHIFT,
+ + };
+ + 
+ + /**
+ +  * struct omap_hwmod_sysc_type2 - TYPE2 sysconfig scheme.
+ +  *
+ +  * To be used by hwmod structure to specify the sysconfig offsets if the
+ +  * device ip is compliant with the new PRCM protocol defined for new
+ +  * OMAP4 IPs.
+ +  */
+ + struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2 = {
+ + 	.midle_shift	= SYSC_TYPE2_MIDLEMODE_SHIFT,
+ + 	.sidle_shift	= SYSC_TYPE2_SIDLEMODE_SHIFT,
+ + 	.srst_shift	= SYSC_TYPE2_SOFTRESET_SHIFT,
+ + };
+ + 
+ + /**
+ +  * struct omap_hwmod_sysc_type3 - TYPE3 sysconfig scheme.
+ +  * Used by some IPs on AM33xx
+ +  */
+ + struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3 = {
+ + 	.midle_shift	= SYSC_TYPE3_MIDLEMODE_SHIFT,
+ + 	.sidle_shift	= SYSC_TYPE3_SIDLEMODE_SHIFT,
+ + };
+ + 
+ + /**
+ +  * struct omap_hwmod_sysc_type4 - TYPE4 sysconfig scheme.
+ +  * Used by some IPs on AM33xx
+ +  */
+ + struct omap_hwmod_sysc_fields omap_hwmod_sysc_type4 = {
+ + 	.midle_shift	= SYSC_TYPE4_MIDLEMODE_SHIFT,
+ + 	.clkact_shift	= SYSC_TYPE4_CLOCKACTIVITY_SHIFT,
+ + 	.sidle_shift	= SYSC_TYPE4_SIDLEMODE_SHIFT,
+ + 	.enwkup_shift	= SYSC_TYPE4_ENAWAKEUP_SHIFT,
+ + 	.srst_shift	= SYSC_TYPE4_SOFTRESET_SHIFT,
+ + 	.autoidle_shift	= SYSC_TYPE4_AUTOIDLE_SHIFT,
+ + };
+ + 
+ + struct omap_dss_dispc_dev_attr omap2_3_dss_dispc_dev_attr = {
+ + 	.manager_count		= 2,
+ + 	.has_framedonetv_irq	= 0
+ + };
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_hwmod_common_data.h linux-3.2.1/arch/arm/mach-ckb_3352/omap_hwmod_common_data.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_hwmod_common_data.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/omap_hwmod_common_data.h	2014-11-25 13:19:15.027074032 +0900
+ ***************
+ *** 0 ****
+ --- 1,118 ----
+ + /*
+ +  * omap_hwmod_common_data.h - OMAP hwmod common macros and declarations
+ +  *
+ +  * Copyright (C) 2010-2011 Nokia Corporation
+ +  * Paul Walmsley
+ +  *
+ +  * Copyright (C) 2010-2011 Texas Instruments, Inc.
+ +  * Benoît Cousson
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + #ifndef __ARCH_ARM_MACH_OMAP2_OMAP_HWMOD_COMMON_DATA_H
+ + #define __ARCH_ARM_MACH_OMAP2_OMAP_HWMOD_COMMON_DATA_H
+ + 
+ + #include <plat/omap_hwmod.h>
+ + 
+ + #include "display.h"
+ + 
+ + /* Common address space across OMAP2xxx */
+ + extern struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[];
+ + extern struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[];
+ + extern struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[];
+ + extern struct omap_hwmod_addr_space omap2xxx_timer2_addrs[];
+ + extern struct omap_hwmod_addr_space omap2xxx_timer3_addrs[];
+ + extern struct omap_hwmod_addr_space omap2xxx_timer4_addrs[];
+ + extern struct omap_hwmod_addr_space omap2xxx_timer5_addrs[];
+ + extern struct omap_hwmod_addr_space omap2xxx_timer6_addrs[];
+ + extern struct omap_hwmod_addr_space omap2xxx_timer7_addrs[];
+ + extern struct omap_hwmod_addr_space omap2xxx_timer8_addrs[];
+ + extern struct omap_hwmod_addr_space omap2xxx_timer9_addrs[];
+ + extern struct omap_hwmod_addr_space omap2xxx_timer12_addrs[];
+ + extern struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[];
+ + 
+ + /* Common address space across OMAP2xxx/3xxx */
+ + extern struct omap_hwmod_addr_space omap2_i2c1_addr_space[];
+ + extern struct omap_hwmod_addr_space omap2_i2c2_addr_space[];
+ + extern struct omap_hwmod_addr_space omap2_dss_addrs[];
+ + extern struct omap_hwmod_addr_space omap2_dss_dispc_addrs[];
+ + extern struct omap_hwmod_addr_space omap2_dss_rfbi_addrs[];
+ + extern struct omap_hwmod_addr_space omap2_dss_venc_addrs[];
+ + extern struct omap_hwmod_addr_space omap2_timer10_addrs[];
+ + extern struct omap_hwmod_addr_space omap2_timer11_addrs[];
+ + extern struct omap_hwmod_addr_space omap2430_mmc1_addr_space[];
+ + extern struct omap_hwmod_addr_space omap2430_mmc2_addr_space[];
+ + extern struct omap_hwmod_addr_space omap2_mcspi1_addr_space[];
+ + extern struct omap_hwmod_addr_space omap2_mcspi2_addr_space[];
+ + extern struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[];
+ + extern struct omap_hwmod_addr_space omap2_dma_system_addrs[];
+ + extern struct omap_hwmod_addr_space omap2_mailbox_addrs[];
+ + extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[];
+ + 
+ + /* Common IP block data across OMAP2xxx */
+ + extern struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[];
+ + extern struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[];
+ + 
+ + /* Common IP block data */
+ + extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[];
+ + extern struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[];
+ + extern struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[];
+ + extern struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[];
+ + extern struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[];
+ + extern struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[];
+ + extern struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[];
+ + extern struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[];
+ + extern struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[];
+ + 
+ + /* Common IP block data on OMAP2430/OMAP3 */
+ + extern struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[];
+ + 
+ + /* Common IP block data across OMAP2/3 */
+ + extern struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[];
+ + extern struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[];
+ + extern struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[];
+ + extern struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[];
+ + extern struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[];
+ + extern struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[];
+ + extern struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[];
+ + extern struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[];
+ + extern struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[];
+ + extern struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[];
+ + extern struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[];
+ + extern struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[];
+ + extern struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[];
+ + extern struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[];
+ + extern struct omap_hwmod_irq_info omap2_dispc_irqs[];
+ + extern struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[];
+ + extern struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[];
+ + extern struct omap_hwmod_irq_info omap2_gpio1_irqs[];
+ + extern struct omap_hwmod_irq_info omap2_gpio2_irqs[];
+ + extern struct omap_hwmod_irq_info omap2_gpio3_irqs[];
+ + extern struct omap_hwmod_irq_info omap2_gpio4_irqs[];
+ + extern struct omap_hwmod_irq_info omap2_dma_system_irqs[];
+ + extern struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[];
+ + extern struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[];
+ + 
+ + /* OMAP hwmod classes - forward declarations */
+ + extern struct omap_hwmod_class l3_hwmod_class;
+ + extern struct omap_hwmod_class l4_hwmod_class;
+ + extern struct omap_hwmod_class mpu_hwmod_class;
+ + extern struct omap_hwmod_class iva_hwmod_class;
+ + extern struct omap_hwmod_class omap2_uart_class;
+ + extern struct omap_hwmod_class omap2_dss_hwmod_class;
+ + extern struct omap_hwmod_class omap2_dispc_hwmod_class;
+ + extern struct omap_hwmod_class omap2_rfbi_hwmod_class;
+ + extern struct omap_hwmod_class omap2_venc_hwmod_class;
+ + 
+ + extern struct omap_hwmod_class omap2xxx_timer_hwmod_class;
+ + extern struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class;
+ + extern struct omap_hwmod_class omap2xxx_gpio_hwmod_class;
+ + extern struct omap_hwmod_class omap2xxx_dma_hwmod_class;
+ + extern struct omap_hwmod_class omap2xxx_mailbox_hwmod_class;
+ + extern struct omap_hwmod_class omap2xxx_mcspi_class;
+ + 
+ + extern struct omap_dss_dispc_dev_attr omap2_3_dss_dispc_dev_attr;
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_l3_smx.c linux-3.2.1/arch/arm/mach-ckb_3352/omap_l3_smx.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_l3_smx.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/omap_l3_smx.c	2014-11-25 13:19:15.031005511 +0900
+ ***************
+ *** 0 ****
+ --- 1,296 ----
+ + /*
+ +  * OMAP3XXX L3 Interconnect Driver
+ +  *
+ +  * Copyright (C) 2011 Texas Corporation
+ +  *	Felipe Balbi <balbi@ti.com>
+ +  *	Santosh Shilimkar <santosh.shilimkar@ti.com>
+ +  *	Sricharan <r.sricharan@ti.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; either version 2 of the License, or
+ +  * (at your option) any later version.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+ +  * USA
+ +  */
+ + 
+ + #include <linux/kernel.h>
+ + #include <linux/slab.h>
+ + #include <linux/platform_device.h>
+ + #include <linux/interrupt.h>
+ + #include <linux/io.h>
+ + #include "omap_l3_smx.h"
+ + 
+ + static inline u64 omap3_l3_readll(void __iomem *base, u16 reg)
+ + {
+ + 	return __raw_readll(base + reg);
+ + }
+ + 
+ + static inline void omap3_l3_writell(void __iomem *base, u16 reg, u64 value)
+ + {
+ + 	__raw_writell(value, base + reg);
+ + }
+ + 
+ + static inline enum omap3_l3_code omap3_l3_decode_error_code(u64 error)
+ + {
+ + 	return (error & 0x0f000000) >> L3_ERROR_LOG_CODE;
+ + }
+ + 
+ + static inline u32 omap3_l3_decode_addr(u64 error_addr)
+ + {
+ + 	return error_addr & 0xffffffff;
+ + }
+ + 
+ + static inline unsigned omap3_l3_decode_cmd(u64 error)
+ + {
+ + 	return (error & 0x07) >> L3_ERROR_LOG_CMD;
+ + }
+ + 
+ + static inline enum omap3_l3_initiator_id omap3_l3_decode_initid(u64 error)
+ + {
+ + 	return (error & 0xff00) >> L3_ERROR_LOG_INITID;
+ + }
+ + 
+ + static inline unsigned omap3_l3_decode_req_info(u64 error)
+ + {
+ + 	return (error >> 32) & 0xffff;
+ + }
+ + 
+ + static char *omap3_l3_code_string(u8 code)
+ + {
+ + 	switch (code) {
+ + 	case OMAP_L3_CODE_NOERROR:
+ + 		return "No Error";
+ + 	case OMAP_L3_CODE_UNSUP_CMD:
+ + 		return "Unsupported Command";
+ + 	case OMAP_L3_CODE_ADDR_HOLE:
+ + 		return "Address Hole";
+ + 	case OMAP_L3_CODE_PROTECT_VIOLATION:
+ + 		return "Protection Violation";
+ + 	case OMAP_L3_CODE_IN_BAND_ERR:
+ + 		return "In-band Error";
+ + 	case OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT:
+ + 		return "Request Timeout Not Accepted";
+ + 	case OMAP_L3_CODE_REQ_TOUT_NO_RESP:
+ + 		return "Request Timeout, no response";
+ + 	default:
+ + 		return "UNKNOWN error";
+ + 	}
+ + }
+ + 
+ + static char *omap3_l3_initiator_string(u8 initid)
+ + {
+ + 	switch (initid) {
+ + 	case OMAP_L3_LCD:
+ + 		return "LCD";
+ + 	case OMAP_L3_SAD2D:
+ + 		return "SAD2D";
+ + 	case OMAP_L3_IA_MPU_SS_1:
+ + 	case OMAP_L3_IA_MPU_SS_2:
+ + 	case OMAP_L3_IA_MPU_SS_3:
+ + 	case OMAP_L3_IA_MPU_SS_4:
+ + 	case OMAP_L3_IA_MPU_SS_5:
+ + 		return "MPU";
+ + 	case OMAP_L3_IA_IVA_SS_1:
+ + 	case OMAP_L3_IA_IVA_SS_2:
+ + 	case OMAP_L3_IA_IVA_SS_3:
+ + 		return "IVA_SS";
+ + 	case OMAP_L3_IA_IVA_SS_DMA_1:
+ + 	case OMAP_L3_IA_IVA_SS_DMA_2:
+ + 	case OMAP_L3_IA_IVA_SS_DMA_3:
+ + 	case OMAP_L3_IA_IVA_SS_DMA_4:
+ + 	case OMAP_L3_IA_IVA_SS_DMA_5:
+ + 	case OMAP_L3_IA_IVA_SS_DMA_6:
+ + 		return "IVA_SS_DMA";
+ + 	case OMAP_L3_IA_SGX:
+ + 		return "SGX";
+ + 	case OMAP_L3_IA_CAM_1:
+ + 	case OMAP_L3_IA_CAM_2:
+ + 	case OMAP_L3_IA_CAM_3:
+ + 		return "CAM";
+ + 	case OMAP_L3_IA_DAP:
+ + 		return "DAP";
+ + 	case OMAP_L3_SDMA_WR_1:
+ + 	case OMAP_L3_SDMA_WR_2:
+ + 		return "SDMA_WR";
+ + 	case OMAP_L3_SDMA_RD_1:
+ + 	case OMAP_L3_SDMA_RD_2:
+ + 	case OMAP_L3_SDMA_RD_3:
+ + 	case OMAP_L3_SDMA_RD_4:
+ + 		return "SDMA_RD";
+ + 	case OMAP_L3_USBOTG:
+ + 		return "USB_OTG";
+ + 	case OMAP_L3_USBHOST:
+ + 		return "USB_HOST";
+ + 	default:
+ + 		return "UNKNOWN Initiator";
+ + 	}
+ + }
+ + 
+ + /*
+ +  * omap3_l3_block_irq - handles a register block's irq
+ +  * @l3: struct omap3_l3 *
+ +  * @base: register block base address
+ +  * @error: L3_ERROR_LOG register of our block
+ +  *
+ +  * Called in hard-irq context. Caller should take care of locking
+ +  *
+ +  * OMAP36xx TRM gives, on page 2001, Figure 9-10, the Typical Error
+ +  * Analysis Sequence, we are following that sequence here, please
+ +  * refer to that Figure for more information on the subject.
+ +  */
+ + static irqreturn_t omap3_l3_block_irq(struct omap3_l3 *l3,
+ + 					u64 error, int error_addr)
+ + {
+ + 	u8 code = omap3_l3_decode_error_code(error);
+ + 	u8 initid = omap3_l3_decode_initid(error);
+ + 	u8 multi = error & L3_ERROR_LOG_MULTI;
+ + 	u32 address = omap3_l3_decode_addr(error_addr);
+ + 
+ + 	WARN(true, "%s seen by %s %s at address %x\n",
+ + 			omap3_l3_code_string(code),
+ + 			omap3_l3_initiator_string(initid),
+ + 			multi ? "Multiple Errors" : "", address);
+ + 
+ + 	return IRQ_HANDLED;
+ + }
+ + 
+ + static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
+ + {
+ + 	struct omap3_l3 *l3 = _l3;
+ + 	u64 status, clear;
+ + 	u64 error;
+ + 	u64 error_addr;
+ + 	u64 err_source = 0;
+ + 	void __iomem *base;
+ + 	int int_type;
+ + 	irqreturn_t ret = IRQ_NONE;
+ + 
+ + 	int_type = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
+ + 	if (!int_type) {
+ + 		status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_0);
+ + 		/*
+ + 		 * if we have a timeout error, there's nothing we can
+ + 		 * do besides rebooting the board. So let's BUG on any
+ + 		 * of such errors and handle the others. timeout error
+ + 		 * is severe and not expected to occur.
+ + 		 */
+ + 		BUG_ON(status & L3_STATUS_0_TIMEOUT_MASK);
+ + 	} else {
+ + 		status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_1);
+ + 		/* No timeout error for debug sources */
+ + 	}
+ + 
+ + 	/* identify the error source */
+ + 	err_source = __ffs(status);
+ + 
+ + 	base = l3->rt + omap3_l3_bases[int_type][err_source];
+ + 	error = omap3_l3_readll(base, L3_ERROR_LOG);
+ + 	if (error) {
+ + 		error_addr = omap3_l3_readll(base, L3_ERROR_LOG_ADDR);
+ + 		ret |= omap3_l3_block_irq(l3, error, error_addr);
+ + 	}
+ + 
+ + 	/* Clear the status register */
+ + 	clear = (L3_AGENT_STATUS_CLEAR_IA << int_type) |
+ + 		L3_AGENT_STATUS_CLEAR_TA;
+ + 	omap3_l3_writell(base, L3_AGENT_STATUS, clear);
+ + 
+ + 	/* clear the error log register */
+ + 	omap3_l3_writell(base, L3_ERROR_LOG, error);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + static int __init omap3_l3_probe(struct platform_device *pdev)
+ + {
+ + 	struct omap3_l3 *l3;
+ + 	struct resource *res;
+ + 	int ret;
+ + 
+ + 	l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
+ + 	if (!l3)
+ + 		return -ENOMEM;
+ + 
+ + 	platform_set_drvdata(pdev, l3);
+ + 
+ + 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ + 	if (!res) {
+ + 		dev_err(&pdev->dev, "couldn't find resource\n");
+ + 		ret = -ENODEV;
+ + 		goto err0;
+ + 	}
+ + 	l3->rt = ioremap(res->start, resource_size(res));
+ + 	if (!l3->rt) {
+ + 		dev_err(&pdev->dev, "ioremap failed\n");
+ + 		ret = -ENOMEM;
+ + 		goto err0;
+ + 	}
+ + 
+ + 	l3->debug_irq = platform_get_irq(pdev, 0);
+ + 	ret = request_irq(l3->debug_irq, omap3_l3_app_irq,
+ + 		IRQF_DISABLED | IRQF_TRIGGER_RISING,
+ + 		"l3-debug-irq", l3);
+ + 	if (ret) {
+ + 		dev_err(&pdev->dev, "couldn't request debug irq\n");
+ + 		goto err1;
+ + 	}
+ + 
+ + 	l3->app_irq = platform_get_irq(pdev, 1);
+ + 	ret = request_irq(l3->app_irq, omap3_l3_app_irq,
+ + 		IRQF_DISABLED | IRQF_TRIGGER_RISING,
+ + 		"l3-app-irq", l3);
+ + 	if (ret) {
+ + 		dev_err(&pdev->dev, "couldn't request app irq\n");
+ + 		goto err2;
+ + 	}
+ + 
+ + 	return 0;
+ + 
+ + err2:
+ + 	free_irq(l3->debug_irq, l3);
+ + err1:
+ + 	iounmap(l3->rt);
+ + err0:
+ + 	kfree(l3);
+ + 	return ret;
+ + }
+ + 
+ + static int __exit omap3_l3_remove(struct platform_device *pdev)
+ + {
+ + 	struct omap3_l3         *l3 = platform_get_drvdata(pdev);
+ + 
+ + 	free_irq(l3->app_irq, l3);
+ + 	free_irq(l3->debug_irq, l3);
+ + 	iounmap(l3->rt);
+ + 	kfree(l3);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static struct platform_driver omap3_l3_driver = {
+ + 	.remove         = __exit_p(omap3_l3_remove),
+ + 	.driver         = {
+ + 	.name   = "omap_l3_smx",
+ + 	},
+ + };
+ + 
+ + static int __init omap3_l3_init(void)
+ + {
+ + 	return platform_driver_probe(&omap3_l3_driver, omap3_l3_probe);
+ + }
+ + postcore_initcall_sync(omap3_l3_init);
+ + 
+ + static void __exit omap3_l3_exit(void)
+ + {
+ + 	platform_driver_unregister(&omap3_l3_driver);
+ + }
+ + module_exit(omap3_l3_exit);
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_l3_smx.h linux-3.2.1/arch/arm/mach-ckb_3352/omap_l3_smx.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_l3_smx.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/omap_l3_smx.h	2014-11-25 13:19:15.031005511 +0900
+ ***************
+ *** 0 ****
+ --- 1,338 ----
+ + /*
+ +  * OMAP3XXX L3 Interconnect Driver header
+ +  *
+ +  * Copyright (C) 2011 Texas Corporation
+ +  *	Felipe Balbi <balbi@ti.com>
+ +  *	Santosh Shilimkar <santosh.shilimkar@ti.com>
+ +  *	sricharan <r.sricharan@ti.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; either version 2 of the License, or
+ +  * (at your option) any later version.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+ +  * USA
+ +  */
+ + #ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
+ + #define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
+ + 
+ + /* Register definitions. All 64-bit wide */
+ + #define L3_COMPONENT			0x000
+ + #define L3_CORE				0x018
+ + #define L3_AGENT_CONTROL		0x020
+ + #define L3_AGENT_STATUS			0x028
+ + #define L3_ERROR_LOG			0x058
+ + 
+ + #define L3_ERROR_LOG_MULTI		(1 << 31)
+ + #define L3_ERROR_LOG_SECONDARY		(1 << 30)
+ + 
+ + #define L3_ERROR_LOG_ADDR		0x060
+ + 
+ + /* Register definitions for Sideband Interconnect */
+ + #define L3_SI_CONTROL			0x020
+ + #define L3_SI_FLAG_STATUS_0		0x510
+ + 
+ + static const u64 shift = 1;
+ + 
+ + #define L3_STATUS_0_MPUIA_BRST		(shift << 0)
+ + #define L3_STATUS_0_MPUIA_RSP		(shift << 1)
+ + #define L3_STATUS_0_MPUIA_INBAND	(shift << 2)
+ + #define L3_STATUS_0_IVAIA_BRST		(shift << 6)
+ + #define L3_STATUS_0_IVAIA_RSP		(shift << 7)
+ + #define L3_STATUS_0_IVAIA_INBAND	(shift << 8)
+ + #define L3_STATUS_0_SGXIA_BRST		(shift << 9)
+ + #define L3_STATUS_0_SGXIA_RSP		(shift << 10)
+ + #define L3_STATUS_0_SGXIA_MERROR	(shift << 11)
+ + #define L3_STATUS_0_CAMIA_BRST		(shift << 12)
+ + #define L3_STATUS_0_CAMIA_RSP		(shift << 13)
+ + #define L3_STATUS_0_CAMIA_INBAND	(shift << 14)
+ + #define L3_STATUS_0_DISPIA_BRST		(shift << 15)
+ + #define L3_STATUS_0_DISPIA_RSP		(shift << 16)
+ + #define L3_STATUS_0_DMARDIA_BRST	(shift << 18)
+ + #define L3_STATUS_0_DMARDIA_RSP		(shift << 19)
+ + #define L3_STATUS_0_DMAWRIA_BRST	(shift << 21)
+ + #define L3_STATUS_0_DMAWRIA_RSP		(shift << 22)
+ + #define L3_STATUS_0_USBOTGIA_BRST	(shift << 24)
+ + #define L3_STATUS_0_USBOTGIA_RSP	(shift << 25)
+ + #define L3_STATUS_0_USBOTGIA_INBAND	(shift << 26)
+ + #define L3_STATUS_0_USBHOSTIA_BRST	(shift << 27)
+ + #define L3_STATUS_0_USBHOSTIA_INBAND	(shift << 28)
+ + #define L3_STATUS_0_SMSTA_REQ		(shift << 48)
+ + #define L3_STATUS_0_GPMCTA_REQ		(shift << 49)
+ + #define L3_STATUS_0_OCMRAMTA_REQ	(shift << 50)
+ + #define L3_STATUS_0_OCMROMTA_REQ	(shift << 51)
+ + #define L3_STATUS_0_IVATA_REQ		(shift << 54)
+ + #define L3_STATUS_0_SGXTA_REQ		(shift << 55)
+ + #define L3_STATUS_0_SGXTA_SERROR	(shift << 56)
+ + #define L3_STATUS_0_GPMCTA_SERROR	(shift << 57)
+ + #define L3_STATUS_0_L4CORETA_REQ	(shift << 58)
+ + #define L3_STATUS_0_L4PERTA_REQ		(shift << 59)
+ + #define L3_STATUS_0_L4EMUTA_REQ		(shift << 60)
+ + #define L3_STATUS_0_MAD2DTA_REQ		(shift << 61)
+ + 
+ + #define L3_STATUS_0_TIMEOUT_MASK	(L3_STATUS_0_MPUIA_BRST		\
+ + 					| L3_STATUS_0_MPUIA_RSP		\
+ + 					| L3_STATUS_0_IVAIA_BRST	\
+ + 					| L3_STATUS_0_IVAIA_RSP		\
+ + 					| L3_STATUS_0_SGXIA_BRST	\
+ + 					| L3_STATUS_0_SGXIA_RSP		\
+ + 					| L3_STATUS_0_CAMIA_BRST	\
+ + 					| L3_STATUS_0_CAMIA_RSP		\
+ + 					| L3_STATUS_0_DISPIA_BRST	\
+ + 					| L3_STATUS_0_DISPIA_RSP	\
+ + 					| L3_STATUS_0_DMARDIA_BRST	\
+ + 					| L3_STATUS_0_DMARDIA_RSP	\
+ + 					| L3_STATUS_0_DMAWRIA_BRST	\
+ + 					| L3_STATUS_0_DMAWRIA_RSP	\
+ + 					| L3_STATUS_0_USBOTGIA_BRST	\
+ + 					| L3_STATUS_0_USBOTGIA_RSP	\
+ + 					| L3_STATUS_0_USBHOSTIA_BRST	\
+ + 					| L3_STATUS_0_SMSTA_REQ		\
+ + 					| L3_STATUS_0_GPMCTA_REQ	\
+ + 					| L3_STATUS_0_OCMRAMTA_REQ	\
+ + 					| L3_STATUS_0_OCMROMTA_REQ	\
+ + 					| L3_STATUS_0_IVATA_REQ		\
+ + 					| L3_STATUS_0_SGXTA_REQ		\
+ + 					| L3_STATUS_0_L4CORETA_REQ	\
+ + 					| L3_STATUS_0_L4PERTA_REQ	\
+ + 					| L3_STATUS_0_L4EMUTA_REQ	\
+ + 					| L3_STATUS_0_MAD2DTA_REQ)
+ + 
+ + #define L3_SI_FLAG_STATUS_1		0x530
+ + 
+ + #define L3_STATUS_1_MPU_DATAIA		(1 << 0)
+ + #define L3_STATUS_1_DAPIA0		(1 << 3)
+ + #define L3_STATUS_1_DAPIA1		(1 << 4)
+ + #define L3_STATUS_1_IVAIA		(1 << 6)
+ + 
+ + #define L3_PM_ERROR_LOG			0x020
+ + #define L3_PM_CONTROL			0x028
+ + #define L3_PM_ERROR_CLEAR_SINGLE	0x030
+ + #define L3_PM_ERROR_CLEAR_MULTI		0x038
+ + #define L3_PM_REQ_INFO_PERMISSION(n)	(0x048 + (0x020 * n))
+ + #define L3_PM_READ_PERMISSION(n)	(0x050 + (0x020 * n))
+ + #define L3_PM_WRITE_PERMISSION(n)	(0x058 + (0x020 * n))
+ + #define L3_PM_ADDR_MATCH(n)		(0x060 + (0x020 * n))
+ + 
+ + /* L3 error log bit fields. Common for IA and TA */
+ + #define L3_ERROR_LOG_CODE		24
+ + #define L3_ERROR_LOG_INITID		8
+ + #define L3_ERROR_LOG_CMD		0
+ + 
+ + /* L3 agent status bit fields. */
+ + #define L3_AGENT_STATUS_CLEAR_IA	0x10000000
+ + #define L3_AGENT_STATUS_CLEAR_TA	0x01000000
+ + 
+ + #define OMAP34xx_IRQ_L3_APP		10
+ + #define L3_APPLICATION_ERROR		0x0
+ + #define L3_DEBUG_ERROR			0x1
+ + 
+ + enum omap3_l3_initiator_id {
+ + 	/* LCD has 1 ID */
+ + 	OMAP_L3_LCD = 29,
+ + 	/* SAD2D has 1 ID */
+ + 	OMAP_L3_SAD2D = 28,
+ + 	/* MPU has 5 IDs */
+ + 	OMAP_L3_IA_MPU_SS_1 = 27,
+ + 	OMAP_L3_IA_MPU_SS_2 = 26,
+ + 	OMAP_L3_IA_MPU_SS_3 = 25,
+ + 	OMAP_L3_IA_MPU_SS_4 = 24,
+ + 	OMAP_L3_IA_MPU_SS_5 = 23,
+ + 	/* IVA2.2 SS has 3 IDs*/
+ + 	OMAP_L3_IA_IVA_SS_1 = 22,
+ + 	OMAP_L3_IA_IVA_SS_2 = 21,
+ + 	OMAP_L3_IA_IVA_SS_3 = 20,
+ + 	/* IVA 2.2 SS DMA has 6 IDS */
+ + 	OMAP_L3_IA_IVA_SS_DMA_1 = 19,
+ + 	OMAP_L3_IA_IVA_SS_DMA_2 = 18,
+ + 	OMAP_L3_IA_IVA_SS_DMA_3 = 17,
+ + 	OMAP_L3_IA_IVA_SS_DMA_4 = 16,
+ + 	OMAP_L3_IA_IVA_SS_DMA_5 = 15,
+ + 	OMAP_L3_IA_IVA_SS_DMA_6 = 14,
+ + 	/* SGX has 1 ID */
+ + 	OMAP_L3_IA_SGX = 13,
+ + 	/* CAM has 3 ID */
+ + 	OMAP_L3_IA_CAM_1 = 12,
+ + 	OMAP_L3_IA_CAM_2 = 11,
+ + 	OMAP_L3_IA_CAM_3 = 10,
+ + 	/* DAP has 1 ID */
+ + 	OMAP_L3_IA_DAP = 9,
+ + 	/* SDMA WR has 2 IDs */
+ + 	OMAP_L3_SDMA_WR_1 = 8,
+ + 	OMAP_L3_SDMA_WR_2 = 7,
+ + 	/* SDMA RD has 4 IDs */
+ + 	OMAP_L3_SDMA_RD_1 = 6,
+ + 	OMAP_L3_SDMA_RD_2 = 5,
+ + 	OMAP_L3_SDMA_RD_3 = 4,
+ + 	OMAP_L3_SDMA_RD_4 = 3,
+ + 	/* HSUSB OTG has 1 ID */
+ + 	OMAP_L3_USBOTG = 2,
+ + 	/* HSUSB HOST has 1 ID */
+ + 	OMAP_L3_USBHOST = 1,
+ + };
+ + 
+ + enum omap3_l3_code {
+ + 	OMAP_L3_CODE_NOERROR = 0,
+ + 	OMAP_L3_CODE_UNSUP_CMD = 1,
+ + 	OMAP_L3_CODE_ADDR_HOLE = 2,
+ + 	OMAP_L3_CODE_PROTECT_VIOLATION = 3,
+ + 	OMAP_L3_CODE_IN_BAND_ERR = 4,
+ + 	/* codes 5 and 6 are reserved */
+ + 	OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT = 7,
+ + 	OMAP_L3_CODE_REQ_TOUT_NO_RESP = 8,
+ + 	/* codes 9 - 15 are also reserved */
+ + };
+ + 
+ + struct omap3_l3 {
+ + 	struct device *dev;
+ + 	struct clk *ick;
+ + 
+ + 	/* memory base*/
+ + 	void __iomem *rt;
+ + 
+ + 	int debug_irq;
+ + 	int app_irq;
+ + 
+ + 	/* true when and inband functional error occurs */
+ + 	unsigned inband:1;
+ + };
+ + 
+ + /* offsets for l3 agents in order with the Flag status register */
+ + static unsigned int omap3_l3_app_bases[] = {
+ + 	/* MPU IA */
+ + 	0x1400,
+ + 	0x1400,
+ + 	0x1400,
+ + 	/* RESERVED */
+ + 	0,
+ + 	0,
+ + 	0,
+ + 	/* IVA 2.2 IA */
+ + 	0x1800,
+ + 	0x1800,
+ + 	0x1800,
+ + 	/* SGX IA */
+ + 	0x1c00,
+ + 	0x1c00,
+ + 	/* RESERVED */
+ + 	0,
+ + 	/* CAMERA IA */
+ + 	0x5800,
+ + 	0x5800,
+ + 	0x5800,
+ + 	/* DISPLAY IA */
+ + 	0x5400,
+ + 	0x5400,
+ + 	/* RESERVED */
+ + 	0,
+ + 	/*SDMA RD IA */
+ + 	0x4c00,
+ + 	0x4c00,
+ + 	/* RESERVED */
+ + 	0,
+ + 	/* SDMA WR IA */
+ + 	0x5000,
+ + 	0x5000,
+ + 	/* RESERVED */
+ + 	0,
+ + 	/* USB OTG IA */
+ + 	0x4400,
+ + 	0x4400,
+ + 	0x4400,
+ + 	/* USB HOST IA */
+ + 	0x4000,
+ + 	0x4000,
+ + 	/* RESERVED */
+ + 	0,
+ + 	0,
+ + 	0,
+ + 	0,
+ + 	/* SAD2D IA */
+ + 	0x3000,
+ + 	0x3000,
+ + 	0x3000,
+ + 	/* RESERVED */
+ + 	0,
+ + 	0,
+ + 	0,
+ + 	0,
+ + 	0,
+ + 	0,
+ + 	0,
+ + 	0,
+ + 	0,
+ + 	0,
+ + 	0,
+ + 	0,
+ + 	/* SMA TA */
+ + 	0x2000,
+ + 	/* GPMC TA */
+ + 	0x2400,
+ + 	/* OCM RAM TA */
+ + 	0x2800,
+ + 	/* OCM ROM TA */
+ + 	0x2C00,
+ + 	/* L4 CORE TA */
+ + 	0x6800,
+ + 	/* L4 PER TA */
+ + 	0x6c00,
+ + 	/* IVA 2.2 TA */
+ + 	0x6000,
+ + 	/* SGX TA */
+ + 	0x6400,
+ + 	/* L4 EMU TA */
+ + 	0x7000,
+ + 	/* GPMC TA */
+ + 	0x2400,
+ + 	/* L4 CORE TA */
+ + 	0x6800,
+ + 	/* L4 PER TA */
+ + 	0x6c00,
+ + 	/* L4 EMU TA */
+ + 	0x7000,
+ + 	/* MAD2D TA */
+ + 	0x3400,
+ + 	/* RESERVED */
+ + 	0,
+ + 	0,
+ + };
+ + 
+ + static unsigned int omap3_l3_debug_bases[] = {
+ + 	/* MPU DATA IA */
+ + 	0x1400,
+ + 	/* RESERVED */
+ + 	0,
+ + 	0,
+ + 	/* DAP IA */
+ + 	0x5c00,
+ + 	0x5c00,
+ + 	/* RESERVED */
+ + 	0,
+ + 	/* IVA 2.2 IA */
+ + 	0x1800,
+ + 	/* REST RESERVED */
+ + };
+ + 
+ + static u32 *omap3_l3_bases[] = {
+ + 	omap3_l3_app_bases,
+ + 	omap3_l3_debug_bases,
+ + };
+ + 
+ + /*
+ +  * REVISIT define __raw_readll/__raw_writell here, but move them to
+ +  * <asm/io.h> at some point
+ +  */
+ + #define __raw_writell(v, a)	(__chk_io_ptr(a), \
+ + 				*(volatile u64 __force *)(a) = (v))
+ + #define __raw_readll(a)		(__chk_io_ptr(a), \
+ + 				*(volatile u64 __force *)(a))
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_opp_data.h linux-3.2.1/arch/arm/mach-ckb_3352/omap_opp_data.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_opp_data.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/omap_opp_data.h	2014-11-26 18:42:49.705636000 +0900
+ ***************
+ *** 0 ****
+ --- 1,151 ----
+ + /*
+ +  * OMAP SoC specific OPP Data helpers
+ +  *
+ +  * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/
+ +  *	Nishanth Menon
+ +  *	Kevin Hilman
+ +  * Copyright (C) 2010 Nokia Corporation.
+ +  *      Eduardo Valentin
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + #ifndef __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H
+ + #define __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H
+ + 
+ + #include <plat/omap_hwmod.h>
+ + 
+ + #include "voltage.h"
+ + 
+ + /*
+ +  * *BIG FAT WARNING*:
+ +  * USE the following ONLY in opp data initialization common to an SoC.
+ +  * DO NOT USE these in board files/pm core etc.
+ +  */
+ + 
+ + /**
+ +  * struct omap_opp_def - OMAP OPP Definition
+ +  * @hwmod_name:	Name of the hwmod for this domain
+ +  * @freq:	Frequency in hertz corresponding to this OPP
+ +  * @u_volt:	Nominal voltage in microvolts corresponding to this OPP
+ +  * @default_available:	True/false - is this OPP available by default
+ +  *
+ +  * OMAP SOCs have a standard set of tuples consisting of frequency and voltage
+ +  * pairs that the device will support per voltage domain. This is called
+ +  * Operating Points or OPP. The actual definitions of OMAP Operating Points
+ +  * varies over silicon within the same family of devices. For a specific
+ +  * domain, you can have a set of {frequency, voltage} pairs and this is denoted
+ +  * by an array of omap_opp_def. As the kernel boots and more information is
+ +  * available, a set of these are activated based on the precise nature of
+ +  * device the kernel boots up on. It is interesting to remember that each IP
+ +  * which belongs to a voltage domain may define their own set of OPPs on top
+ +  * of this - but this is handled by the appropriate driver.
+ +  */
+ + struct omap_opp_def {
+ + 	char *hwmod_name;
+ + 
+ + 	unsigned long freq;
+ + 	unsigned long u_volt;
+ + 
+ + 	bool default_available;
+ + };
+ + 
+ + /*
+ +  * Initialization wrapper used to define an OPP for OMAP variants.
+ +  */
+ + #define OPP_INITIALIZER(_hwmod_name, _enabled, _freq, _uv)	\
+ + {								\
+ + 	.hwmod_name	= _hwmod_name,				\
+ + 	.default_available	= _enabled,			\
+ + 	.freq		= _freq,				\
+ + 	.u_volt		= _uv,					\
+ + }
+ + 
+ + /*
+ +  * Initialization wrapper used to define SmartReflex process data
+ +  * XXX Is this needed?  Just use C99 initializers in data files?
+ +  */
+ + #define VOLT_DATA_DEFINE(_v_nom, _efuse_offs, _errminlimit, _errgain)  \
+ + {								       \
+ + 	.volt_nominal	= _v_nom,				       \
+ + 	.sr_efuse_offs	= _efuse_offs,				       \
+ + 	.sr_errminlimit = _errminlimit,				       \
+ + 	.vp_errgain	= _errgain				       \
+ + }
+ + 
+ + /* Use this to initialize the default table */
+ + extern int __init omap_init_opp_table(struct omap_opp_def *opp_def,
+ + 		u32 opp_def_size);
+ + 
+ + 
+ + extern struct omap_volt_data omap34xx_vddmpu_volt_data[];
+ + extern struct omap_volt_data omap34xx_vddcore_volt_data[];
+ + extern struct omap_volt_data omap36xx_vddmpu_volt_data[];
+ + extern struct omap_volt_data omap36xx_vddcore_volt_data[];
+ + 
+ + extern struct omap_volt_data omap44xx_vdd_mpu_volt_data[];
+ + extern struct omap_volt_data omap44xx_vdd_iva_volt_data[];
+ + extern struct omap_volt_data omap44xx_vdd_core_volt_data[];
+ + 
+ + 
+ + /*
+ +  * Errata 1.0.15: OPP50 Operation on MPU Domain is Not Supported.
+ +  *
+ +  * To minimize power consumption, the ARM Cortex-A8 may be operated at
+ +  * the lower frequency defined by OPP50, but the respective voltage
+ +  * domain VDD_MPU must be operated as defined by OPP100. So MPU OPP50
+ +  * definition is modified to 275MHz, 1.1V.
+ +  */
+ + #if 0
+ + #define AM33XX_VDD_MPU_OPP50_UV		950000
+ + #else
+ + #define AM33XX_VDD_MPU_OPP50_UV		1100000
+ + #endif
+ + #define AM33XX_VDD_MPU_OPP100_UV	1100000
+ + #define AM33XX_VDD_MPU_OPP120_UV	1200000
+ + #define AM33XX_VDD_MPU_OPPTURBO_UV	1260000
+ + #define AM33XX_VDD_MPU_OPPNITRO_UV	1325000
+ + 
+ + #define AM33XX_VDD_MPU_275_FREQ		275000000
+ + #define AM33XX_VDD_MPU_300_FREQ		300000000
+ + #define AM33XX_VDD_MPU_500_FREQ		500000000
+ + #define AM33XX_VDD_MPU_600_FREQ		600000000
+ + #define AM33XX_VDD_MPU_720_FREQ		720000000
+ + #define AM33XX_VDD_MPU_800_FREQ		800000000			/* Turbo */
+ + #define AM33XX_VDD_MPU_1000_FREQ	1000000000			/* Nitro */
+ + 
+ + #define AM33XX_VDD_CORE_OPP50_UV        950000
+ + #define AM33XX_VDD_CORE_OPP100_UV       1100000
+ + 
+ + #define OPP_50_300_INDEX	0
+ + #define OPP_100_300_INDEX	1
+ + #define OPP_100_600_INDEX	2
+ + #define OPP_120_720_INDEX	3
+ + #define OPP_TURBO_800_INDEX	4
+ + #define OPP_NITRO_1GHZ_INDEX	5
+ + 
+ + /* From AM335x TRM, SPRUH73H, Section 9.3.50 */
+ + #define AM33XX_EFUSE_SMA_OFFSET	0x7fc
+ + 
+ + /*
+ +  * Bits [12:0] are OPP Disabled bits,
+ +  * 1 = OPP is disabled and not available,
+ +  * 0 = OPP available.
+ +  */
+ + #define MAX_FREQ_MASK		0x1fff
+ + #define MAX_FREQ_SHFT		0
+ + 
+ + #define OPP_50_300MHZ_BIT		(0x1 << 4)
+ + #define OPP_100_300MHZ_BIT		(0x1 << 5)
+ + #define OPP_100_600MHZ_BIT		(0x1 << 6)
+ + #define OPP_120_720MHZ_BIT		(0x1 << 7)
+ + #define OPP_TURBO_800MHZ_BIT	(0x1 << 8)
+ + #define OPP_NITRO_1GHZ_BIT		(0x1 << 9)
+ + 
+ + #endif		/* __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H */
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_phy_internal.c linux-3.2.1/arch/arm/mach-ckb_3352/omap_phy_internal.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_phy_internal.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/omap_phy_internal.c	2014-11-25 13:19:15.031005511 +0900
+ ***************
+ *** 0 ****
+ --- 1,79 ----
+ + /*
+ +   * This file configures the internal USB PHY in OMAP4430. Used
+ +   * with TWL6030 transceiver and MUSB on OMAP4430.
+ +   *
+ +   * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
+ +   * This program is free software; you can redistribute it and/or modify
+ +   * it under the terms of the GNU General Public License as published by
+ +   * the Free Software Foundation; either version 2 of the License, or
+ +   * (at your option) any later version.
+ +   *
+ +   * Author: Hema HK <hemahk@ti.com>
+ +   *
+ +   * This program is distributed in the hope that it will be useful,
+ +   * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +   * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +   * GNU General Public License for more details.
+ +   *
+ +   * You should have received a copy of the GNU General Public License
+ +   * along with this program; if not, write to the Free Software
+ +   * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ +   *
+ +   */
+ + 
+ + #include <linux/types.h>
+ + #include <linux/delay.h>
+ + #include <linux/clk.h>
+ + #include <linux/io.h>
+ + #include <linux/err.h>
+ + #include <linux/usb.h>
+ + 
+ + #include <plat/usb.h>
+ + #include <plat/am33xx.h>
+ + #include "control.h"
+ + 
+ + /* OMAP control module register for UTMI PHY */
+ + #define CONTROL_DEV_CONF		0x300
+ + #define PHY_PD				0x1
+ + 
+ + #define USBOTGHS_CONTROL		0x33c
+ + #define	AVALID				BIT(0)
+ + #define	BVALID				BIT(1)
+ + #define	VBUSVALID			BIT(2)
+ + #define	SESSEND				BIT(3)
+ + #define	IDDIG				BIT(4)
+ + 
+ + void ti81xx_musb_phy_power(u8 id, u8 on , bool wkup)
+ + {
+ + 	void __iomem *scm_base = NULL;
+ + 	u32 usbphycfg;
+ + 	u32 usbwkupctrl = 0;
+ + 
+ + 	scm_base = ioremap(AM33XX_SCM_BASE, SZ_2K);
+ + 
+ + 	if (!scm_base) {
+ + 		pr_err("system control module ioremap failed\n");
+ + 		return;
+ + 	}
+ + 
+ + 	usbphycfg = __raw_readl(scm_base + (id ? USBCTRL1 : USBCTRL0));
+ + 	usbwkupctrl = readl(scm_base + USBWKUPCTRL);
+ + 
+ + 	if (on) {
+ + 		usbphycfg &= ~(USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN);
+ + 		usbphycfg |= (USBPHY_OTGVDET_EN | USBPHY_OTGSESSEND_EN);
+ + 		usbwkupctrl = AM33XX_USB_WKUP_CTRL_DISABLE;
+ + 	} else {
+ + 		usbphycfg |= USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN;
+ + 		if (wkup)
+ + 			usbwkupctrl |= id ? AM33XX_USB1_WKUP_CTRL_ENABLE :
+ + 							AM33XX_USB0_WKUP_CTRL_ENABLE;
+ + 		else
+ + 			usbwkupctrl &= id ? ~AM33XX_USB1_WKUP_CTRL_ENABLE :
+ + 							~AM33XX_USB0_WKUP_CTRL_ENABLE;
+ + 	}
+ + 	__raw_writel(usbphycfg, scm_base + (id ? USBCTRL1 : USBCTRL0));
+ + 	writel(usbwkupctrl , scm_base + USBWKUPCTRL);
+ + 
+ + 	iounmap(scm_base);
+ + }
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_twl.c linux-3.2.1/arch/arm/mach-ckb_3352/omap_twl.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/omap_twl.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/omap_twl.c	2014-11-25 13:19:15.035467867 +0900
+ ***************
+ *** 0 ****
+ --- 1,263 ----
+ + /**
+ +  * OMAP and TWL PMIC specific intializations.
+ +  *
+ +  * Copyright (C) 2010 Texas Instruments Incorporated.
+ +  * Thara Gopinath
+ +  * Copyright (C) 2009 Texas Instruments Incorporated.
+ +  * Nishanth Menon
+ +  * Copyright (C) 2009 Nokia Corporation
+ +  * Paul Walmsley
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #include <linux/err.h>
+ + #include <linux/io.h>
+ + #include <linux/kernel.h>
+ + #include <linux/i2c/twl.h>
+ + 
+ + #include "voltage.h"
+ + 
+ + #include "pm.h"
+ + 
+ + #define OMAP3_SRI2C_SLAVE_ADDR		0x12
+ + #define OMAP3_VDD_MPU_SR_CONTROL_REG	0x00
+ + #define OMAP3_VDD_CORE_SR_CONTROL_REG	0x01
+ + #define OMAP3_VP_CONFIG_ERROROFFSET	0x00
+ + #define OMAP3_VP_VSTEPMIN_VSTEPMIN	0x1
+ + #define OMAP3_VP_VSTEPMAX_VSTEPMAX	0x04
+ + #define OMAP3_VP_VLIMITTO_TIMEOUT_US	200
+ + 
+ + #define OMAP3430_VP1_VLIMITTO_VDDMIN	0x14
+ + #define OMAP3430_VP1_VLIMITTO_VDDMAX	0x42
+ + #define OMAP3430_VP2_VLIMITTO_VDDMIN	0x18
+ + #define OMAP3430_VP2_VLIMITTO_VDDMAX	0x2c
+ + 
+ + #define OMAP3630_VP1_VLIMITTO_VDDMIN	0x18
+ + #define OMAP3630_VP1_VLIMITTO_VDDMAX	0x3c
+ + #define OMAP3630_VP2_VLIMITTO_VDDMIN	0x18
+ + #define OMAP3630_VP2_VLIMITTO_VDDMAX	0x30
+ + 
+ + #define OMAP4_SRI2C_SLAVE_ADDR		0x12
+ + #define OMAP4_VDD_MPU_SR_VOLT_REG	0x55
+ + #define OMAP4_VDD_MPU_SR_CMD_REG	0x56
+ + #define OMAP4_VDD_IVA_SR_VOLT_REG	0x5B
+ + #define OMAP4_VDD_IVA_SR_CMD_REG	0x5C
+ + #define OMAP4_VDD_CORE_SR_VOLT_REG	0x61
+ + #define OMAP4_VDD_CORE_SR_CMD_REG	0x62
+ + 
+ + #define OMAP4_VP_CONFIG_ERROROFFSET	0x00
+ + #define OMAP4_VP_VSTEPMIN_VSTEPMIN	0x01
+ + #define OMAP4_VP_VSTEPMAX_VSTEPMAX	0x04
+ + #define OMAP4_VP_VLIMITTO_TIMEOUT_US	200
+ + 
+ + #define OMAP4_VP_MPU_VLIMITTO_VDDMIN	0xA
+ + #define OMAP4_VP_MPU_VLIMITTO_VDDMAX	0x39
+ + #define OMAP4_VP_IVA_VLIMITTO_VDDMIN	0xA
+ + #define OMAP4_VP_IVA_VLIMITTO_VDDMAX	0x2D
+ + #define OMAP4_VP_CORE_VLIMITTO_VDDMIN	0xA
+ + #define OMAP4_VP_CORE_VLIMITTO_VDDMAX	0x28
+ + 
+ + static bool is_offset_valid;
+ + static u8 smps_offset;
+ + /*
+ +  * Flag to ensure Smartreflex bit in TWL
+ +  * being cleared in board file is not overwritten.
+ +  */
+ + static bool __initdata twl_sr_enable_autoinit;
+ + 
+ + #define TWL4030_DCDC_GLOBAL_CFG        0x06
+ + #define REG_SMPS_OFFSET         0xE0
+ + #define SMARTREFLEX_ENABLE     BIT(3)
+ + 
+ + static unsigned long twl4030_vsel_to_uv(const u8 vsel)
+ + {
+ + 	return (((vsel * 125) + 6000)) * 100;
+ + }
+ + 
+ + static u8 twl4030_uv_to_vsel(unsigned long uv)
+ + {
+ + 	return DIV_ROUND_UP(uv - 600000, 12500);
+ + }
+ + 
+ + static unsigned long twl6030_vsel_to_uv(const u8 vsel)
+ + {
+ + 	/*
+ + 	 * In TWL6030 depending on the value of SMPS_OFFSET
+ + 	 * efuse register the voltage range supported in
+ + 	 * standard mode can be either between 0.6V - 1.3V or
+ + 	 * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
+ + 	 * is programmed to all 0's where as starting from
+ + 	 * TWL6030 ES1.1 the efuse is programmed to 1
+ + 	 */
+ + 	if (!is_offset_valid) {
+ + 		twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset,
+ + 				REG_SMPS_OFFSET);
+ + 		is_offset_valid = true;
+ + 	}
+ + 
+ + 	if (!vsel)
+ + 		return 0;
+ + 	/*
+ + 	 * There is no specific formula for voltage to vsel
+ + 	 * conversion above 1.3V. There are special hardcoded
+ + 	 * values for voltages above 1.3V. Currently we are
+ + 	 * hardcoding only for 1.35 V which is used for 1GH OPP for
+ + 	 * OMAP4430.
+ + 	 */
+ + 	if (vsel == 0x3A)
+ + 		return 1350000;
+ + 
+ + 	if (smps_offset & 0x8)
+ + 		return ((((vsel - 1) * 1266) + 70900)) * 10;
+ + 	else
+ + 		return ((((vsel - 1) * 1266) + 60770)) * 10;
+ + }
+ + 
+ + static u8 twl6030_uv_to_vsel(unsigned long uv)
+ + {
+ + 	/*
+ + 	 * In TWL6030 depending on the value of SMPS_OFFSET
+ + 	 * efuse register the voltage range supported in
+ + 	 * standard mode can be either between 0.6V - 1.3V or
+ + 	 * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
+ + 	 * is programmed to all 0's where as starting from
+ + 	 * TWL6030 ES1.1 the efuse is programmed to 1
+ + 	 */
+ + 	if (!is_offset_valid) {
+ + 		twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset,
+ + 				REG_SMPS_OFFSET);
+ + 		is_offset_valid = true;
+ + 	}
+ + 
+ + 	if (!uv)
+ + 		return 0x00;
+ + 	/*
+ + 	 * There is no specific formula for voltage to vsel
+ + 	 * conversion above 1.3V. There are special hardcoded
+ + 	 * values for voltages above 1.3V. Currently we are
+ + 	 * hardcoding only for 1.35 V which is used for 1GH OPP for
+ + 	 * OMAP4430.
+ + 	 */
+ + 	if (uv > twl6030_vsel_to_uv(0x39)) {
+ + 		if (uv == 1350000)
+ + 			return 0x3A;
+ + 		pr_err("%s:OUT OF RANGE! non mapped vsel for %ld Vs max %ld\n",
+ + 			__func__, uv, twl6030_vsel_to_uv(0x39));
+ + 		return 0x3A;
+ + 	}
+ + 
+ + 	if (smps_offset & 0x8)
+ + 		return DIV_ROUND_UP(uv - 709000, 12660) + 1;
+ + 	else
+ + 		return DIV_ROUND_UP(uv - 607700, 12660) + 1;
+ + }
+ + 
+ + static struct omap_voltdm_pmic omap3_mpu_pmic = {
+ + 	.slew_rate		= 4000,
+ + 	.step_size		= 12500,
+ + 	.on_volt		= 1200000,
+ + 	.onlp_volt		= 1000000,
+ + 	.ret_volt		= 975000,
+ + 	.off_volt		= 600000,
+ + 	.volt_setup_time	= 0xfff,
+ + 	.vp_erroroffset		= OMAP3_VP_CONFIG_ERROROFFSET,
+ + 	.vp_vstepmin		= OMAP3_VP_VSTEPMIN_VSTEPMIN,
+ + 	.vp_vstepmax		= OMAP3_VP_VSTEPMAX_VSTEPMAX,
+ + 	.vp_vddmin		= OMAP3430_VP1_VLIMITTO_VDDMIN,
+ + 	.vp_vddmax		= OMAP3430_VP1_VLIMITTO_VDDMAX,
+ + 	.vp_timeout_us		= OMAP3_VP_VLIMITTO_TIMEOUT_US,
+ + 	.i2c_slave_addr		= OMAP3_SRI2C_SLAVE_ADDR,
+ + 	.volt_reg_addr		= OMAP3_VDD_MPU_SR_CONTROL_REG,
+ + 	.i2c_high_speed		= true,
+ + 	.vsel_to_uv		= twl4030_vsel_to_uv,
+ + 	.uv_to_vsel		= twl4030_uv_to_vsel,
+ + };
+ + 
+ + static struct omap_voltdm_pmic omap3_core_pmic = {
+ + 	.slew_rate		= 4000,
+ + 	.step_size		= 12500,
+ + 	.on_volt                = 1200000,
+ + 	.onlp_volt              = 1000000,
+ + 	.ret_volt               = 975000,
+ + 	.off_volt               = 600000,
+ + 	.volt_setup_time        = 0xfff,
+ + 	.vp_erroroffset		= OMAP3_VP_CONFIG_ERROROFFSET,
+ + 	.vp_vstepmin		= OMAP3_VP_VSTEPMIN_VSTEPMIN,
+ + 	.vp_vstepmax		= OMAP3_VP_VSTEPMAX_VSTEPMAX,
+ + 	.vp_vddmin		= OMAP3430_VP2_VLIMITTO_VDDMIN,
+ + 	.vp_vddmax		= OMAP3430_VP2_VLIMITTO_VDDMAX,
+ + 	.vp_timeout_us		= OMAP3_VP_VLIMITTO_TIMEOUT_US,
+ + 	.i2c_slave_addr		= OMAP3_SRI2C_SLAVE_ADDR,
+ + 	.volt_reg_addr		= OMAP3_VDD_CORE_SR_CONTROL_REG,
+ + 	.i2c_high_speed		= true,
+ + 	.vsel_to_uv		= twl4030_vsel_to_uv,
+ + 	.uv_to_vsel		= twl4030_uv_to_vsel,
+ + };
+ + 
+ + static struct omap_voltdm_pmic omap4_mpu_pmic = {
+ + 	.slew_rate		= 4000,
+ + 	.step_size		= 12660,
+ + 	.on_volt		= 1375000,
+ + 	.onlp_volt		= 1375000,
+ + 	.ret_volt		= 830000,
+ + 	.off_volt		= 0,
+ + 	.volt_setup_time	= 0,
+ + 	.vp_erroroffset		= OMAP4_VP_CONFIG_ERROROFFSET,
+ + 	.vp_vstepmin		= OMAP4_VP_VSTEPMIN_VSTEPMIN,
+ + 	.vp_vstepmax		= OMAP4_VP_VSTEPMAX_VSTEPMAX,
+ + 	.vp_vddmin		= OMAP4_VP_MPU_VLIMITTO_VDDMIN,
+ + 	.vp_vddmax		= OMAP4_VP_MPU_VLIMITTO_VDDMAX,
+ + 	.vp_timeout_us		= OMAP4_VP_VLIMITTO_TIMEOUT_US,
+ + 	.i2c_slave_addr		= OMAP4_SRI2C_SLAVE_ADDR,
+ + 	.volt_reg_addr		= OMAP4_VDD_MPU_SR_VOLT_REG,
+ + 	.cmd_reg_addr		= OMAP4_VDD_MPU_SR_CMD_REG,
+ + 	.i2c_high_speed		= true,
+ + 	.vsel_to_uv		= twl6030_vsel_to_uv,
+ + 	.uv_to_vsel		= twl6030_uv_to_vsel,
+ + };
+ + 
+ + static struct omap_voltdm_pmic omap4_iva_pmic = {
+ + 	.slew_rate		= 4000,
+ + 	.step_size		= 12660,
+ + 	.on_volt		= 1188000,
+ + 	.onlp_volt		= 1188000,
+ + 	.ret_volt		= 830000,
+ + 	.off_volt		= 0,
+ + 	.volt_setup_time	= 0,
+ + 	.vp_erroroffset		= OMAP4_VP_CONFIG_ERROROFFSET,
+ + 	.vp_vstepmin		= OMAP4_VP_VSTEPMIN_VSTEPMIN,
+ + 	.vp_vstepmax		= OMAP4_VP_VSTEPMAX_VSTEPMAX,
+ + 	.vp_vddmin		= OMAP4_VP_IVA_VLIMITTO_VDDMIN,
+ + 	.vp_vddmax		= OMAP4_VP_IVA_VLIMITTO_VDDMAX,
+ + 	.vp_timeout_us		= OMAP4_VP_VLIMITTO_TIMEOUT_US,
+ + 	.i2c_slave_addr		= OMAP4_SRI2C_SLAVE_ADDR,
+ + 	.volt_reg_addr		= OMAP4_VDD_IVA_SR_VOLT_REG,
+ + 	.cmd_reg_addr		= OMAP4_VDD_IVA_SR_CMD_REG,
+ + 	.i2c_high_speed		= true,
+ + 	.vsel_to_uv		= twl6030_vsel_to_uv,
+ + 	.uv_to_vsel		= twl6030_uv_to_vsel,
+ + };
+ + 
+ + static struct omap_voltdm_pmic omap4_core_pmic = {
+ + 	.slew_rate		= 4000,
+ + 	.step_size		= 12660,
+ + 	.on_volt		= 1200000,
+ + 	.onlp_volt		= 1200000,
+ + 	.ret_volt		= 830000,
+ + 	.off_volt		= 0,
+ + 	.volt_setup_time	= 0,
+ + 	.vp_erroroffset		= OMAP4_VP_CONFIG_ERROROFFSET,
+ + 	.vp_vstepmin		= OMAP4_VP_VSTEPMIN_VSTEPMIN,
+ + 	.vp_vstepmax		= OMAP4_VP_VSTEPMAX_VSTEPMAX,
+ + 	.vp_vddmin		= OMAP4_VP_CORE_VLIMITTO_VDDMIN,
+ + 	.vp_vddmax		= OMAP4_VP_CORE_VLIMITTO_VDDMAX,
+ + 	.vp_timeout_us		= OMAP4_VP_VLIMITTO_TIMEOUT_US,
+ + 	.i2c_slave_addr		= OMAP4_SRI2C_SLAVE_ADDR,
+ + 	.volt_reg_addr		= OMAP4_VDD_CORE_SR_VOLT_REG,
+ + 	.cmd_reg_addr		= OMAP4_VDD_CORE_SR_CMD_REG,
+ + 	.vsel_to_uv		= twl6030_vsel_to_uv,
+ + 	.uv_to_vsel		= twl6030_uv_to_vsel,
+ + };
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/opp3xxx_data.c linux-3.2.1/arch/arm/mach-ckb_3352/opp3xxx_data.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/opp3xxx_data.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/opp3xxx_data.c	2014-11-25 14:00:32.640669000 +0900
+ ***************
+ *** 0 ****
+ --- 1,152 ----
+ + /*
+ +  * OMAP3 OPP table definitions.
+ +  *
+ +  * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/
+ +  *	Nishanth Menon
+ +  *	Kevin Hilman
+ +  * Copyright (C) 2010-2011 Nokia Corporation.
+ +  *      Eduardo Valentin
+ +  *      Paul Walmsley
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #include <linux/kernel.h>
+ + #include <linux/init.h>
+ + #include <linux/module.h>
+ + #include <linux/interrupt.h>
+ + #include <linux/clk.h>
+ + #include <linux/io.h>
+ + #include <linux/debugfs.h>
+ + #include <linux/slab.h>
+ + #include <linux/regulator/consumer.h>
+ + #include <linux/cpufreq.h>
+ + #include <linux/opp.h>
+ + 
+ + #include <plat/cpu.h>
+ + 
+ + #include "control.h"
+ + #include "omap_opp_data.h"
+ + #include "pm.h"
+ + 
+ + static struct omap_opp_def __initdata am33xx_es1_0_opp_def_list[] = {
+ + 	/* MPU OPP1 - OPP50 */
+ + 	OPP_INITIALIZER("mpu", true,  AM33XX_VDD_MPU_275_FREQ, AM33XX_VDD_MPU_OPP50_UV),
+ + 	/* MPU OPP2 - OPP100 */
+ + 	OPP_INITIALIZER("mpu", true,  AM33XX_VDD_MPU_500_FREQ, AM33XX_VDD_MPU_OPP100_UV),
+ + 	/* MPU OPP3 - OPP120 */
+ + 	OPP_INITIALIZER("mpu", true,  AM33XX_VDD_MPU_600_FREQ, AM33XX_VDD_MPU_OPP120_UV),
+ + 	/* MPU OPP4 - OPPTurbo */
+ + 	OPP_INITIALIZER("mpu", true,  AM33XX_VDD_MPU_720_FREQ, AM33XX_VDD_MPU_OPPTURBO_UV),
+ + };
+ + 
+ + static struct omap_opp_def __initdata am33xx_es2_0_opp_def_list[] = {
+ + 	/* MPU OPP1 - OPP50 */
+ + 	OPP_INITIALIZER("mpu", true,  AM33XX_VDD_MPU_300_FREQ, AM33XX_VDD_MPU_OPP50_UV),
+ + 	/* MPU OPP2 - OPP100 */
+ + 	OPP_INITIALIZER("mpu", true,  AM33XX_VDD_MPU_600_FREQ, AM33XX_VDD_MPU_OPP100_UV),
+ + 	/* MPU OPP3 - OPP120 */
+ + 	OPP_INITIALIZER("mpu", true,  AM33XX_VDD_MPU_720_FREQ, AM33XX_VDD_MPU_OPP120_UV),
+ + 	/* MPU OPP4 - OPPTurbo */
+ + 	OPP_INITIALIZER("mpu", true, AM33XX_VDD_MPU_800_FREQ, AM33XX_VDD_MPU_OPPTURBO_UV),
+ + };
+ + 
+ + static struct omap_opp_def __initdata am33xx_es2_1_opp_list[] = {
+ + 	/* MPU OPP1 - OPP50-300MHz */
+ + 	OPP_INITIALIZER("mpu", false,  AM33XX_VDD_MPU_300_FREQ, AM33XX_VDD_MPU_OPP50_UV),
+ + 	/* MPU OPP1 - OPP100-300MHz (used for ZCE) */
+ + 	OPP_INITIALIZER("mpu", false,  AM33XX_VDD_MPU_300_FREQ, AM33XX_VDD_MPU_OPP100_UV),
+ + 	/* MPU OPP2 - OPP100 */
+ + 	OPP_INITIALIZER("mpu", false,  AM33XX_VDD_MPU_600_FREQ, AM33XX_VDD_MPU_OPP100_UV),
+ + 	/* MPU OPP3 - OPP120 */
+ + 	OPP_INITIALIZER("mpu", false,  AM33XX_VDD_MPU_720_FREQ, AM33XX_VDD_MPU_OPP120_UV),
+ + 	/* MPU OPP3 - OPPTurbo */
+ + 	OPP_INITIALIZER("mpu", false, AM33XX_VDD_MPU_800_FREQ, AM33XX_VDD_MPU_OPPTURBO_UV),
+ + 	/* MPU OPP4 - OPPNitro */
+ + 	OPP_INITIALIZER("mpu", false, AM33XX_VDD_MPU_1000_FREQ, AM33XX_VDD_MPU_OPPNITRO_UV),
+ + };
+ + 
+ + /**
+ +  * omap3_opp_init() - initialize omap3 opp table
+ +  */
+ + int __init omap3_opp_init(void)
+ + {
+ + 	int r = -ENODEV;
+ + 	u32 rev, val, max_freq;
+ + 
+ + 	rev = omap_rev();
+ + 	switch (rev) {
+ + 	case AM335X_REV_ES1_0:
+ + 		r = omap_init_opp_table(am33xx_es1_0_opp_def_list,
+ + 			ARRAY_SIZE(am33xx_es1_0_opp_def_list));
+ + 		break;
+ + 
+ + 	case AM335X_REV_ES2_1:
+ + 		/*
+ + 		 * First read efuse sma reg to detect package type and
+ + 		 * supported frequency
+ + 		 */
+ + 		val =
+ + 		readl(AM33XX_CTRL_REGADDR(AM33XX_EFUSE_SMA_OFFSET));
+ + 
+ + 		if (!(val & MAX_FREQ_MASK)) {
+ + 			/*
+ + 			* if mpu max freq is not populated, fall back to
+ + 			* PG 2.0 OPP settings.
+ + 			*/
+ + 			r =
+ + 			omap_init_opp_table(am33xx_es2_0_opp_def_list,
+ + 				ARRAY_SIZE(am33xx_es2_0_opp_def_list));
+ + 			break;
+ + 		}
+ + 
+ + 		/*
+ + 		 * 1 = OPP is disabled and not available,
+ + 		 * 0 = OPP available.
+ + 		 */
+ + 		max_freq = (~val & MAX_FREQ_MASK);
+ + 
+ + 		if (max_freq & OPP_50_300MHZ_BIT)
+ + 			am33xx_es2_1_opp_list[OPP_50_300_INDEX].
+ + 				default_available = true;
+ + 
+ + 		if (max_freq & OPP_100_300MHZ_BIT)
+ + 			am33xx_es2_1_opp_list[OPP_100_300_INDEX].
+ + 				default_available = true;
+ + 
+ + 		if (max_freq & OPP_100_600MHZ_BIT)
+ + 			am33xx_es2_1_opp_list[OPP_100_600_INDEX].
+ + 				default_available = true;
+ + 
+ + 		if (max_freq & OPP_120_720MHZ_BIT)
+ + 			am33xx_es2_1_opp_list[OPP_120_720_INDEX].
+ + 				default_available = true;
+ + 
+ + 		if (max_freq & OPP_TURBO_800MHZ_BIT)
+ + 			am33xx_es2_1_opp_list[OPP_TURBO_800_INDEX].
+ + 				default_available = true;
+ + 
+ + 		if (max_freq & OPP_NITRO_1GHZ_BIT)
+ + 			am33xx_es2_1_opp_list[OPP_NITRO_1GHZ_INDEX].
+ + 				default_available = true;
+ + 
+ + 		r = omap_init_opp_table(am33xx_es2_1_opp_list,
+ + 			ARRAY_SIZE(am33xx_es2_1_opp_list));
+ + 		break;
+ + 
+ + 	case AM335X_REV_ES2_0:
+ + 	/* FALLTHROUGH */
+ + 	default:
+ + 		r = omap_init_opp_table(am33xx_es2_0_opp_def_list,
+ + 			ARRAY_SIZE(am33xx_es2_0_opp_def_list));
+ + 	}
+ + 	return r;
+ + }
+ + device_initcall(omap3_opp_init);
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/opp.c linux-3.2.1/arch/arm/mach-ckb_3352/opp.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/opp.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/opp.c	2014-11-25 13:19:15.035467867 +0900
+ ***************
+ *** 0 ****
+ --- 1,93 ----
+ + /*
+ +  * OMAP SoC specific OPP wrapper function
+ +  *
+ +  * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/
+ +  *	Nishanth Menon
+ +  *	Kevin Hilman
+ +  * Copyright (C) 2010 Nokia Corporation.
+ +  *      Eduardo Valentin
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + #include <linux/module.h>
+ + #include <linux/opp.h>
+ + 
+ + #include <plat/omap_device.h>
+ + 
+ + #include "omap_opp_data.h"
+ + 
+ + /* Temp variable to allow multiple calls */
+ + static u8 __initdata omap_table_init;
+ + 
+ + /**
+ +  * omap_init_opp_table() - Initialize opp table as per the CPU type
+ +  * @opp_def:		opp default list for this silicon
+ +  * @opp_def_size:	number of opp entries for this silicon
+ +  *
+ +  * Register the initial OPP table with the OPP library based on the CPU
+ +  * type. This is meant to be used only by SoC specific registration.
+ +  */
+ + int __init omap_init_opp_table(struct omap_opp_def *opp_def,
+ + 		u32 opp_def_size)
+ + {
+ + 	int i, r;
+ + 
+ + 	if (!opp_def || !opp_def_size) {
+ + 		pr_err("%s: invalid params!\n", __func__);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	/*
+ + 	 * Initialize only if not already initialized even if the previous
+ + 	 * call failed, because, no reason we'd succeed again.
+ + 	 */
+ + 	if (omap_table_init)
+ + 		return -EEXIST;
+ + 	omap_table_init = 1;
+ + 
+ + 	/* Lets now register with OPP library */
+ + 	for (i = 0; i < opp_def_size; i++) {
+ + 		struct omap_hwmod *oh;
+ + 		struct device *dev;
+ + 
+ + 		if (!opp_def->hwmod_name) {
+ + 			pr_err("%s: NULL name of omap_hwmod, failing [%d].\n",
+ + 				__func__, i);
+ + 			return -EINVAL;
+ + 		}
+ + 		oh = omap_hwmod_lookup(opp_def->hwmod_name);
+ + 		if (!oh || !oh->od) {
+ + 			pr_warn("%s: no hwmod or odev for %s, [%d] "
+ + 				"cannot add OPPs.\n", __func__,
+ + 				opp_def->hwmod_name, i);
+ + 			return -EINVAL;
+ + 		}
+ + 		dev = &oh->od->pdev->dev;
+ + 
+ + 		r = opp_add(dev, opp_def->freq, opp_def->u_volt);
+ + 		if (r) {
+ + 			dev_err(dev, "%s: add OPP %ld failed for %s [%d] "
+ + 				"result=%d\n",
+ + 			       __func__, opp_def->freq,
+ + 			       opp_def->hwmod_name, i, r);
+ + 		} else {
+ + 			if (!opp_def->default_available)
+ + 				r = opp_disable(dev, opp_def->freq);
+ + 			if (r)
+ + 				dev_err(dev, "%s: disable %ld failed for %s "
+ + 					"[%d] result=%d\n",
+ + 					__func__, opp_def->freq,
+ + 					opp_def->hwmod_name, i, r);
+ + 		}
+ + 		opp_def++;
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/pm33xx.c linux-3.2.1/arch/arm/mach-ckb_3352/pm33xx.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/pm33xx.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/pm33xx.c	2014-11-25 14:01:26.944775000 +0900
+ ***************
+ *** 0 ****
+ --- 1,681 ----
+ + /*
+ +  * AM33XX Power Management Routines
+ +  *
+ +  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #include <linux/kernel.h>
+ + #include <linux/init.h>
+ + #include <linux/clk.h>
+ + #include <linux/console.h>
+ + #include <linux/err.h>
+ + #include <linux/firmware.h>
+ + #include <linux/io.h>
+ + #include <linux/platform_device.h>
+ + #include <linux/sched.h>
+ + #include <linux/suspend.h>
+ + #include <linux/completion.h>
+ + #include <linux/pm_runtime.h>
+ + 
+ + #include <plat/prcm.h>
+ + #include <plat/mailbox.h>
+ + #include <plat/sram.h>
+ + #include <plat/omap_hwmod.h>
+ + #include <plat/omap_device.h>
+ + #include <plat/emif.h>
+ + 
+ + #include <asm/suspend.h>
+ + #include <asm/proc-fns.h>
+ + #include <asm/sizes.h>
+ + 
+ + #include "pm.h"
+ + #include "cm33xx.h"
+ + #include "pm33xx.h"
+ + #include "control.h"
+ + #include "clockdomain.h"
+ + #include "powerdomain.h"
+ + 
+ + void (*am33xx_do_wfi_sram)(u32 *);
+ + 
+ + #define DS_MODE		DS0_ID	/* DS0/1_ID */
+ + #define MODULE_DISABLE	0x0
+ + #define MODULE_ENABLE	0x2
+ + 
+ + #define GEN_PURP_EVM		0
+ + #define IND_AUT_MTR_EVM		1
+ + #define BEAGLE_BONE_OLD		2
+ + #define BEAGLE_BONE_A3		3
+ + #define EVM_SK				4
+ + #define GEN_PURP_DDR3_EVM	5
+ + 
+ + #ifdef CONFIG_SUSPEND
+ + void __iomem *ipc_regs;
+ + void __iomem *m3_eoi;
+ + void __iomem *m3_code;
+ + u32 suspend_cfg_param_list[SUSPEND_CFG_PARAMS_END];
+ + 
+ + bool enable_deep_sleep = true;
+ + static suspend_state_t suspend_state = PM_SUSPEND_ON;
+ + 
+ + static struct device *mpu_dev;
+ + static struct omap_mbox *m3_mbox;
+ + static struct powerdomain *cefuse_pwrdm, *gfx_pwrdm, *per_pwrdm;
+ + static struct clockdomain *gfx_l3_clkdm, *gfx_l4ls_clkdm;
+ + 
+ + static int m3_state = M3_STATE_UNKNOWN;
+ + static int m3_version = M3_VERSION_UNKNOWN;
+ + 
+ + static int am33xx_ipc_cmd(struct a8_wkup_m3_ipc_data *);
+ + static int am33xx_verify_lp_state(int);
+ + static void am33xx_m3_state_machine_reset(void);
+ + 
+ + static DECLARE_COMPLETION(a8_m3_sync);
+ + 
+ + static int am33xx_pm_prepare_late(void)
+ + {
+ + 	int ret = 0;
+ + 
+ + 	am335x_save_padconf();
+ + 	am33xx_setup_pinmux_on_suspend();
+ + 	am33xx_standby_setup(suspend_state);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + static void am33xx_pm_finish(void)
+ + {
+ + 	am33xx_standby_release(suspend_state);
+ + 	am335x_restore_padconf();
+ + }
+ + 
+ + static int am33xx_do_sram_idle(long unsigned int state)
+ + {
+ + 	am33xx_do_wfi_sram(&suspend_cfg_param_list[0]);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static int am33xx_pm_suspend(void)
+ + {
+ + 	int state, ret = 0;
+ + 
+ + 	struct omap_hwmod *gpmc_oh, *usb_oh, *gpio1_oh;
+ + 
+ + 	usb_oh		= omap_hwmod_lookup("usb_otg_hs");
+ + 	gpmc_oh		= omap_hwmod_lookup("gpmc");
+ + 	gpio1_oh	= omap_hwmod_lookup("gpio1");	/* WKUP domain GPIO */
+ + 
+ + 	omap_hwmod_enable(usb_oh);
+ + 	omap_hwmod_enable(gpmc_oh);
+ + 
+ + 	/*
+ + 	 * Keep USB module enabled during standby
+ + 	 * to enable USB remote wakeup
+ + 	 * Note: This will result in hard-coding USB state
+ + 	 * during standby
+ + 	 */
+ + 	if (suspend_state != PM_SUSPEND_STANDBY)
+ + 		omap_hwmod_idle(usb_oh);
+ + 
+ + 	omap_hwmod_idle(gpmc_oh);
+ + 
+ + 	/*
+ + 	 * Disable the GPIO module. This ensure that
+ + 	 * only sWAKEUP interrupts to Cortex-M3 get generated
+ + 	 *
+ + 	 * XXX: EVM_SK uses a GPIO0 pin for VTP control
+ + 	 * in suspend and hence we can't do this for EVM_SK
+ + 	 * alone. The side-effect of this is that GPIO wakeup
+ + 	 * might have issues. Refer to commit 672639b for the
+ + 	 * details
+ + 	 */
+ + 	/*
+ + 	 * Keep GPIO0 module enabled during standby to
+ + 	 * support wakeup via GPIO0 keys.
+ + 	 */
+ + 	if ((suspend_cfg_param_list[EVM_ID] != EVM_SK) &&
+ + 			(suspend_state != PM_SUSPEND_STANDBY))
+ + 		omap_hwmod_idle(gpio1_oh);
+ + 	/*
+ + 	 * Update Suspend_State value to be used in sleep33xx.S to keep
+ + 	 * GPIO0 module enabled during standby for EVM-SK
+ + 	 */
+ + 	if (suspend_state == PM_SUSPEND_STANDBY)
+ + 		suspend_cfg_param_list[SUSPEND_STATE] = PM_STANDBY;
+ + 	else
+ + 		suspend_cfg_param_list[SUSPEND_STATE] = PM_DS0;
+ + 
+ + 	/*
+ + 	 * Keep Touchscreen module enabled during standby
+ + 	 * to enable wakeup from standby.
+ + 	 */
+ + 	if (suspend_state == PM_SUSPEND_STANDBY)
+ + 		writel(0x2, AM33XX_CM_WKUP_ADC_TSC_CLKCTRL);
+ + 
+ + 	if (gfx_l3_clkdm && gfx_l4ls_clkdm) {
+ + 		clkdm_sleep(gfx_l3_clkdm);
+ + 		clkdm_sleep(gfx_l4ls_clkdm);
+ + 	}
+ + 
+ + 	/* Try to put GFX to sleep */
+ + 	if (gfx_pwrdm)
+ + 		pwrdm_set_next_pwrst(gfx_pwrdm, PWRDM_POWER_OFF);
+ + 	else
+ + 		pr_err("Could not program GFX to low power state\n");
+ + 
+ + 	omap3_intc_suspend();
+ + 
+ + 	writel(0x0, AM33XX_CM_MPU_MPU_CLKCTRL);
+ + 
+ + 	ret = cpu_suspend(0, am33xx_do_sram_idle);
+ + 
+ + 	writel(0x2, AM33XX_CM_MPU_MPU_CLKCTRL);
+ + 
+ + 	if (gfx_pwrdm) {
+ + 		state = pwrdm_read_pwrst(gfx_pwrdm);
+ + 		if (state != PWRDM_POWER_OFF)
+ + 			pr_err("GFX domain did not transition to low power state\n");
+ + 		else
+ + 			pr_info("GFX domain entered low power state\n");
+ + 	}
+ + 
+ + 	/* XXX: Why do we need to wakeup the clockdomains? */
+ + 	if(gfx_l3_clkdm && gfx_l4ls_clkdm) {
+ + 		clkdm_wakeup(gfx_l3_clkdm);
+ + 		clkdm_wakeup(gfx_l4ls_clkdm);
+ + 	}
+ + 
+ + 	/*
+ + 	 * Touchscreen module was enabled during standby
+ + 	 * Disable it here.
+ + 	 */
+ + 	if (suspend_state == PM_SUSPEND_STANDBY)
+ + 		writel(0x0, AM33XX_CM_WKUP_ADC_TSC_CLKCTRL);
+ + 
+ + 	/*
+ + 	 * Put USB module to idle on resume from standby
+ + 	 */
+ + 	if (suspend_state == PM_SUSPEND_STANDBY)
+ + 		omap_hwmod_idle(usb_oh);
+ + 
+ + 	ret = am33xx_verify_lp_state(ret);
+ + 
+ + 	/*
+ + 	 * Enable the GPIO module. Once the driver is
+ + 	 * fully adapted to runtime PM this will go away
+ + 	 */
+ + 	/*
+ + 	 * During standby, GPIO was not disabled. Hence no
+ + 	 * need to enable it here.
+ + 	 */
+ + 	if ((suspend_cfg_param_list[EVM_ID] != EVM_SK) &&
+ + 			(suspend_state != PM_SUSPEND_STANDBY))
+ + 		omap_hwmod_enable(gpio1_oh);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + static int am33xx_pm_enter(suspend_state_t unused)
+ + {
+ + 	int ret = 0;
+ + 
+ + 	switch (suspend_state) {
+ + 	case PM_SUSPEND_STANDBY:
+ + 	case PM_SUSPEND_MEM:
+ + 		ret = am33xx_pm_suspend();
+ + 		break;
+ + 	default:
+ + 		ret = -EINVAL;
+ + 	}
+ + 
+ + 	return ret;
+ + }
+ + 
+ + static int am33xx_pm_begin(suspend_state_t state)
+ + {
+ + 	int ret = 0;
+ + 	int state_id = 0;
+ + 
+ + 	disable_hlt();
+ + 
+ + 	switch (state) {
+ + 	case PM_SUSPEND_STANDBY:
+ + 		state_id = 0xb;
+ + 		break;
+ + 	case PM_SUSPEND_MEM:
+ + 		state_id = 0x3;
+ + 		break;
+ + 	}
+ + 
+ + 	/*
+ + 	 * Populate the resume address as part of IPC data
+ + 	 * The offset to be added comes from sleep33xx.S
+ + 	 * Add 4 bytes to ensure that resume happens from
+ + 	 * the word *after* the word which holds the resume offset
+ + 	 */
+ + 	am33xx_lp_ipc.resume_addr = (DS_RESUME_BASE + am33xx_resume_offset + 4);
+ + 	am33xx_lp_ipc.sleep_mode  = state_id;
+ + 	am33xx_lp_ipc.ipc_data1	  = DS_IPC_DEFAULT;
+ + 	am33xx_lp_ipc.ipc_data2   = DS_IPC_DEFAULT;
+ + 
+ + 	am33xx_ipc_cmd(&am33xx_lp_ipc);
+ + 
+ + 	m3_state = M3_STATE_MSG_FOR_LP;
+ + 
+ + 	omap_mbox_enable_irq(m3_mbox, IRQ_RX);
+ + 
+ + 	ret = omap_mbox_msg_send(m3_mbox, 0xABCDABCD);
+ + 	if (ret) {
+ + 		pr_err("A8<->CM3 MSG for LP failed\n");
+ + 		am33xx_m3_state_machine_reset();
+ + 		ret = -1;
+ + 	}
+ + 
+ + 	if (!wait_for_completion_timeout(&a8_m3_sync, msecs_to_jiffies(5000))) {
+ + 		pr_err("A8<->CM3 sync failure\n");
+ + 		am33xx_m3_state_machine_reset();
+ + 		ret = -1;
+ + 	} else {
+ + 		pr_debug("Message sent for entering %s\n",
+ + 			(DS_MODE == DS0_ID ? "DS0" : "DS1"));
+ + 		omap_mbox_disable_irq(m3_mbox, IRQ_RX);
+ + 	}
+ + 
+ + 	suspend_state = state;
+ + 	return ret;
+ + }
+ + 
+ + static void am33xx_m3_state_machine_reset(void)
+ + {
+ + 	int ret = 0;
+ + 
+ + 	am33xx_lp_ipc.resume_addr = 0x0;
+ + 	am33xx_lp_ipc.sleep_mode  = 0xe;
+ + 	am33xx_lp_ipc.ipc_data1	  = DS_IPC_DEFAULT;
+ + 	am33xx_lp_ipc.ipc_data2   = DS_IPC_DEFAULT;
+ + 
+ + 	am33xx_ipc_cmd(&am33xx_lp_ipc);
+ + 
+ + 	m3_state = M3_STATE_MSG_FOR_RESET;
+ + 
+ + 	ret = omap_mbox_msg_send(m3_mbox, 0xABCDABCD);
+ + 	if (!ret) {
+ + 		pr_debug("Message sent for resetting M3 state machine\n");
+ + 		if (!wait_for_completion_timeout(&a8_m3_sync, msecs_to_jiffies(5000)))
+ + 			pr_err("A8<->CM3 sync failure\n");
+ + 	} else {
+ + 		pr_err("Could not reset M3 state machine!!!\n");
+ + 		m3_state = M3_STATE_UNKNOWN;
+ + 	}
+ + }
+ + 
+ + static void am33xx_pm_end(void)
+ + {
+ + 	suspend_state = PM_SUSPEND_ON;
+ + 
+ + 	omap_mbox_enable_irq(m3_mbox, IRQ_RX);
+ + 
+ + 	am33xx_m3_state_machine_reset();
+ + 
+ + 	enable_hlt();
+ + 
+ + 	return;
+ + }
+ + 
+ + static int am33xx_pm_valid(suspend_state_t state)
+ + {
+ + 	switch (state) {
+ + 	case PM_SUSPEND_STANDBY:
+ + 	case PM_SUSPEND_MEM:
+ + 		return 1;
+ + 	default:
+ + 		return 0;
+ + 	}
+ + }
+ + 
+ + static const struct platform_suspend_ops am33xx_pm_ops = {
+ + 	.begin		= am33xx_pm_begin,
+ + 	.end		= am33xx_pm_end,
+ + 	.enter		= am33xx_pm_enter,
+ + 	.valid		= am33xx_pm_valid,
+ + 	.prepare	= am33xx_pm_prepare_late,
+ + 	.finish		= am33xx_pm_finish,
+ + };
+ + 
+ + int am33xx_ipc_cmd(struct a8_wkup_m3_ipc_data *data)
+ + {
+ + 	writel(data->resume_addr, ipc_regs);
+ + 	writel(data->sleep_mode, ipc_regs + 0x4);
+ + 	writel(data->ipc_data1, ipc_regs + 0x8);
+ + 	writel(data->ipc_data2, ipc_regs + 0xc);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /* return 0 if no reset M3 needed, 1 otherwise */
+ + static int am33xx_verify_lp_state(int core_suspend_stat)
+ + {
+ + 	int status, ret = 0;
+ + 
+ + 	if (core_suspend_stat) {
+ + 		pr_err("Kernel core reported suspend failure\n");
+ + 		ret = -1;
+ + 		goto clear_old_status;
+ + 	}
+ + 
+ + 	status = readl(ipc_regs + 0x4);
+ + 	status &= 0xffff0000;
+ + 
+ + 	if (status == 0x0) {
+ + 		pr_info("Successfully transitioned all domains to low power state\n");
+ + 		if (am33xx_lp_ipc.sleep_mode == DS0_ID)
+ + 			per_pwrdm->ret_logic_off_counter++;
+ + 		goto clear_old_status;
+ + 	} else if (status == 0x10000) {
+ + 		pr_err("Could not enter low power state\n"
+ + 			"Please check for active clocks in PER domain\n");
+ + 		ret = -1;
+ + 		goto clear_old_status;
+ + 	} else {
+ + 		pr_err("Something is terribly wrong :(\nStatus = %0x\n",
+ + 				status);
+ + 		ret = -1;
+ + 	}
+ + 
+ + clear_old_status:
+ + 	/* After decoding write back the bad status */
+ + 	status = readl(ipc_regs + 0x4);
+ + 	status &= 0xffff0000;
+ + 	status |= 0x10000;
+ + 	writel(status, ipc_regs + 0x4);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /*
+ +  * Dummy notifier for the mailbox
+ +  * TODO: Can this be completely removed?
+ +  */
+ + int wkup_m3_mbox_msg(struct notifier_block *self, unsigned long len, void *msg)
+ + {
+ + 	return 0;
+ + }
+ + 
+ + static struct notifier_block wkup_m3_mbox_notifier = {
+ + 	.notifier_call = wkup_m3_mbox_msg,
+ + };
+ + 
+ + static irqreturn_t wkup_m3_txev_handler(int irq, void *unused)
+ + {
+ + 	writel(0x1, m3_eoi);
+ + 
+ + 	if (m3_state == M3_STATE_RESET) {
+ + 		m3_state = M3_STATE_INITED;
+ + 		m3_version = readl(ipc_regs + 0x8);
+ + 		m3_version &= 0x0000ffff;
+ + 		if (m3_version == M3_VERSION_UNKNOWN) {
+ + 			pr_warning("Unable to read CM3 firmware version\n");
+ + 		} else {
+ + 			pr_info("Cortex M3 Firmware Version = 0x%x\n",
+ + 							m3_version);
+ + 		}
+ + 	} else if (m3_state == M3_STATE_MSG_FOR_RESET) {
+ + 		m3_state = M3_STATE_INITED;
+ + 		omap_mbox_msg_rx_flush(m3_mbox);
+ + 		if (m3_mbox->ops->ack_irq)
+ + 			m3_mbox->ops->ack_irq(m3_mbox, IRQ_RX);
+ + 		complete(&a8_m3_sync);
+ + 	} else if (m3_state == M3_STATE_MSG_FOR_LP) {
+ + 		omap_mbox_msg_rx_flush(m3_mbox);
+ + 		if (m3_mbox->ops->ack_irq)
+ + 			m3_mbox->ops->ack_irq(m3_mbox, IRQ_RX);
+ + 		complete(&a8_m3_sync);
+ + 	} else if (m3_state == M3_STATE_UNKNOWN) {
+ + 		pr_err("IRQ %d with CM3 in unknown state\n", irq);
+ + 		omap_mbox_msg_rx_flush(m3_mbox);
+ + 		if (m3_mbox->ops->ack_irq)
+ + 			m3_mbox->ops->ack_irq(m3_mbox, IRQ_RX);
+ + 		return IRQ_NONE;
+ + 	}
+ + 
+ + 	writel(0x0, m3_eoi);
+ + 
+ + 	return IRQ_HANDLED;
+ + }
+ + 
+ + /* Initiliaze WKUP_M3, load the binary blob and let it run */
+ + static int wkup_m3_init(void)
+ + {
+ + 	struct clk *m3_clk;
+ + 	struct omap_hwmod *wkup_m3_oh;
+ + 	const struct firmware *firmware;
+ + 	int ret = 0;
+ + 	int ipc_reg_r = 0;
+ + 
+ + 	wkup_m3_oh = omap_hwmod_lookup("wkup_m3");
+ + 
+ + 	if (!wkup_m3_oh) {
+ + 		pr_err("%s: could not find omap_hwmod\n", __func__);
+ + 		ret = -ENODEV;
+ + 		goto exit;
+ + 	}
+ + 
+ + 	ipc_regs = ioremap(A8_M3_IPC_REGS, 0x4*8);
+ + 	if (!ipc_regs) {
+ + 		pr_err("Could not ioremap the IPC area\b");
+ + 		ret = -ENOMEM;
+ + 		goto exit;
+ + 	}
+ + 
+ + 	m3_eoi = ioremap(M3_TXEV_EOI, 0x4);
+ + 	if (!m3_eoi) {
+ + 		pr_err("Could not ioremap the EOI register\n");
+ + 		ret = -ENOMEM;
+ + 		goto err1;
+ + 	}
+ + 
+ + 	/* Reserve the MBOX for sending messages to M3 */
+ + 	m3_mbox = omap_mbox_get("wkup_m3", &wkup_m3_mbox_notifier);
+ + 	if (IS_ERR(m3_mbox)) {
+ + 		pr_err("Could not reserve mailbox for A8->M3 IPC\n");
+ + 		ret = -ENODEV;
+ + 		goto err2;
+ + 	}
+ + 
+ + 	/* Enable access to the M3 code and data area from A8 */
+ + 	m3_clk = clk_get(NULL, "wkup_m3_fck");
+ + 	if (IS_ERR(m3_clk)) {
+ + 		pr_err("%s failed to enable WKUP_M3 clock\n", __func__);
+ + 		goto err3;
+ + 	}
+ + 
+ + 	if (clk_enable(m3_clk)) {
+ + 		pr_err("%s WKUP_M3: clock enable Failed\n", __func__);
+ + 		goto err4;
+ + 	}
+ + 
+ + 	m3_code = ioremap(M3_UMEM, SZ_16K);
+ + 	if (!m3_code) {
+ + 		pr_err("%s Could not ioremap M3 code space\n", __func__);
+ + 		ret = -ENOMEM;
+ + 		goto err5;
+ + 	}
+ + 
+ + 	pr_info("Trying to load am335x-pm-firmware.bin (60 secs timeout)\n");
+ + 
+ + 	ret = request_firmware(&firmware, "am335x-pm-firmware.bin", mpu_dev);
+ + 	if (ret < 0) {
+ + 		dev_err(mpu_dev, "request_firmware failed\n");
+ + 		goto err6;
+ + 	} else {
+ + 		memcpy(m3_code, firmware->data, firmware->size);
+ + 		pr_info("Copied the M3 firmware to UMEM\n");
+ + 	}
+ + 
+ + 	ret = request_irq(AM33XX_IRQ_M3_M3SP_TXEV, wkup_m3_txev_handler,
+ + 			  IRQF_DISABLED, "wkup_m3_txev", NULL);
+ + 	if (ret) {
+ + 		pr_err("%s request_irq failed for 0x%x\n", __func__,
+ + 			AM33XX_IRQ_M3_M3SP_TXEV);
+ + 		goto err6;
+ + 	}
+ + 
+ + 	m3_state = M3_STATE_RESET;
+ + 
+ + 	/*
+ + 	 * Invalidate M3 firmware version before hardreset.
+ + 	 * Write invalid version in lower 4 nibbles of parameter
+ + 	 * register (ipc_regs + 0x8).
+ + 	 */
+ + 	ipc_reg_r = readl(ipc_regs + 0x8);
+ + 	ipc_reg_r &= 0xffff0000;
+ + 	m3_version |= ipc_reg_r;
+ + 	writel(m3_version, ipc_regs + 0x8);
+ + 
+ + 	ret = omap_hwmod_deassert_hardreset(wkup_m3_oh, "wkup_m3");
+ + 	if (ret) {
+ + 		pr_err("Could not deassert the reset for WKUP_M3\n");
+ + 		goto err6;
+ + 	} else {
+ + 		return 0;
+ + 	}
+ + 
+ + err6:
+ + 	release_firmware(firmware);
+ + 	iounmap(m3_code);
+ + err5:
+ + 	clk_disable(m3_clk);
+ + err4:
+ + 	clk_put(m3_clk);
+ + err3:
+ + 	omap_mbox_put(m3_mbox, &wkup_m3_mbox_notifier);
+ + err2:
+ + 	iounmap(m3_eoi);
+ + err1:
+ + 	iounmap(ipc_regs);
+ + exit:
+ + 	return ret;
+ + }
+ + 
+ + /*
+ +  * Initiate sleep transition for other clockdomains, if
+ +  * they are not used
+ +  */
+ + static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
+ + {
+ + 	if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
+ + 			atomic_read(&clkdm->usecount) == 0)
+ + 		clkdm_sleep(clkdm);
+ + 	return 0;
+ + }
+ + #endif /* CONFIG_SUSPEND */
+ + 
+ + /*
+ +  * Push the minimal suspend-resume code to SRAM
+ +  */
+ + void am33xx_push_sram_idle(void)
+ + {
+ + 	am33xx_do_wfi_sram = (void *)omap_sram_push
+ + 					(am33xx_do_wfi, am33xx_do_wfi_sz);
+ + }
+ + 
+ + static int __init am33xx_pm_init(void)
+ + {
+ + #ifdef CONFIG_CKB_SUSPEND_SUPPORT
+ + 	int ret;
+ + #ifdef CONFIG_SUSPEND
+ + 	void __iomem *base;
+ + 	u32 reg;
+ + 	u32 evm_id;
+ + 
+ + #endif
+ + 	
+ + 	pr_info("Power Management for AM33XX family\n");
+ + 
+ + #ifdef CONFIG_SUSPEND
+ + /* Read SDRAM_CONFIG register to determine Memory Type */
+ + 	base = am33xx_get_ram_base();
+ + 	reg = readl(base + EMIF4_0_SDRAM_CONFIG);
+ + 	reg = (reg & SDRAM_TYPE_MASK) >> SDRAM_TYPE_SHIFT;
+ + 	suspend_cfg_param_list[MEMORY_TYPE] = reg;
+ + 
+ + /*
+ +  * vtp_ctrl register value for DDR2 and DDR3 as suggested
+ +  * by h/w team
+ +  */
+ + 	if (reg == MEM_TYPE_DDR2)
+ + 		suspend_cfg_param_list[SUSP_VTP_CTRL_VAL] = SUSP_VTP_CTRL_DDR2;
+ + 	else
+ + 		suspend_cfg_param_list[SUSP_VTP_CTRL_VAL] = SUSP_VTP_CTRL_DDR3;
+ + 
+ + 
+ + 	/* Get Board Id */
+ + 	//suspend_cfg_param_list[EVM_ID] = BEAGLE_BONE_A3;
+ + 	suspend_cfg_param_list[EVM_ID] = EVM_SK;
+ + 
+ + 	/* CPU Revision */
+ + 	reg = omap_rev();
+ + 	if (reg >= AM335X_REV_ES2_0)
+ + 		suspend_cfg_param_list[CPU_REV] = CPU_REV_2;
+ + 	else
+ + 		suspend_cfg_param_list[CPU_REV] = CPU_REV_1;
+ + 
+ + 	(void) clkdm_for_each(clkdms_setup, NULL);
+ + 
+ + 	/* CEFUSE domain should be turned off post bootup */
+ + 	cefuse_pwrdm = pwrdm_lookup("cefuse_pwrdm");
+ + 	if (cefuse_pwrdm == NULL)
+ + 		pr_err("Failed to get cefuse_pwrdm\n");
+ + 	else
+ + 		pwrdm_set_next_pwrst(cefuse_pwrdm, PWRDM_POWER_OFF);
+ + 
+ + 	gfx_pwrdm = pwrdm_lookup("gfx_pwrdm");
+ + 	if (gfx_pwrdm == NULL)
+ + 		pr_err("Failed to get gfx_pwrdm\n");
+ + 
+ + 	per_pwrdm = pwrdm_lookup("per_pwrdm");
+ + 	if (per_pwrdm == NULL)
+ + 		pr_err("Failed to get per_pwrdm\n");
+ + 
+ + 	gfx_l3_clkdm = clkdm_lookup("gfx_l3_clkdm");
+ + 	if (gfx_l3_clkdm == NULL)
+ + 		pr_err("Failed to get gfx_l3_clkdm\n");
+ + 
+ + 	gfx_l4ls_clkdm = clkdm_lookup("gfx_l4ls_gfx_clkdm");
+ + 	if (gfx_l4ls_clkdm == NULL)
+ + 		pr_err("Failed to get gfx_l4ls_gfx_clkdm\n");
+ + 
+ + 	mpu_dev = omap_device_get_by_hwmod_name("mpu");
+ + 
+ + 	if (!mpu_dev) {
+ + 		pr_warning("%s: unable to get the mpu device\n", __func__);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	ret = wkup_m3_init();
+ + 
+ + 	if (ret) {
+ + 		pr_err("Could not initialise WKUP_M3. "
+ + 			"Power management will be compromised\n");
+ + 		enable_deep_sleep = false;
+ + 	}
+ + 
+ + 	if (enable_deep_sleep)
+ + 		suspend_set_ops(&am33xx_pm_ops);
+ + #endif /* CONFIG_SUSPEND */
+ + 
+ + 	return ret;
+ + #else
+ + 	return 0;
+ + #endif
+ + }
+ + late_initcall(am33xx_pm_init);
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/pm33xx.h linux-3.2.1/arch/arm/mach-ckb_3352/pm33xx.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/pm33xx.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/pm33xx.h	2014-11-25 13:19:15.038952183 +0900
+ ***************
+ *** 0 ****
+ --- 1,88 ----
+ + /*
+ +  * AM33XX Power Management Routines
+ +  *
+ +  * Copyright (C) 2012 Texas Instruments Inc.
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #ifndef __ARCH_ARM_MACH_OMAP2_PM33XX_H
+ + #define __ARCH_ARM_MACH_OMAP2_PM33XX_H
+ + 
+ + #include <mach/hardware.h>	/* XXX Is this the right one to include? */
+ + #include "control.h"
+ + #include "mux33xx.h"
+ + 
+ + #ifndef __ASSEMBLER__
+ + extern void __iomem *am33xx_get_ram_base(void);
+ + 
+ + /*
+ +  * This enum is used to index the array passed to suspend routine with
+ +  * parameters that vary across DDR2 and DDR3 sleep sequence.
+ +  *
+ +  * Since these are used to load into registers by suspend code,
+ +  * entries here must always be in sync with the suspend code
+ +  * in arm/mach-omap2/sleep33xx.S
+ +  */
+ + enum suspend_cfg_params {
+ + 	MEMORY_TYPE = 0,
+ + 	SUSP_VTP_CTRL_VAL,
+ + 	EVM_ID,
+ + 	CPU_REV,
+ + 	SUSPEND_STATE,
+ + 	SUSPEND_CFG_PARAMS_END /* Must be the last entry */
+ + };
+ + 
+ + struct a8_wkup_m3_ipc_data {
+ + 	int resume_addr;
+ + 	int sleep_mode;
+ + 	int ipc_data1;
+ + 	int ipc_data2;
+ + } am33xx_lp_ipc;
+ + 
+ + #endif /* ASSEMBLER */
+ + 
+ + #define M3_TXEV_EOI			(AM33XX_CTRL_BASE + 0x1324)
+ + #define A8_M3_IPC_REGS			(AM33XX_CTRL_BASE + 0x1328)
+ + #define DS_RESUME_BASE			0x40300000
+ + #define DS_IPC_DEFAULT			0xffffffff
+ + #define M3_UMEM				0x44D00000
+ + 
+ + #define	DS0_ID				0x3
+ + #define DS1_ID				0x5
+ + 
+ + #define M3_STATE_UNKNOWN		-1
+ + #define M3_STATE_RESET			0
+ + #define M3_STATE_INITED			1
+ + #define M3_STATE_MSG_FOR_LP		2
+ + #define M3_STATE_MSG_FOR_RESET		3
+ + 
+ + #define VTP_CTRL_READY		(0x1 << 5)
+ + #define VTP_CTRL_ENABLE		(0x1 << 6)
+ + #define VTP_CTRL_LOCK_EN	(0x1 << 4)
+ + #define VTP_CTRL_START_EN	(0x1)
+ + 
+ + #define DDR_IO_CTRL		(AM33XX_CTRL_BASE + 0x0E04)
+ + #define VTP0_CTRL_REG		(AM33XX_CTRL_BASE + 0x0E0C)
+ + #define DDR_CMD0_IOCTRL		(AM33XX_CTRL_BASE + 0x1404)
+ + #define DDR_CMD1_IOCTRL		(AM33XX_CTRL_BASE + 0x1408)
+ + #define DDR_CMD2_IOCTRL		(AM33XX_CTRL_BASE + 0x140C)
+ + #define DDR_DATA0_IOCTRL	(AM33XX_CTRL_BASE + 0x1440)
+ + #define DDR_DATA1_IOCTRL	(AM33XX_CTRL_BASE + 0x1444)
+ + 
+ + #define MEM_TYPE_DDR2		2
+ + 
+ + #define SUSP_VTP_CTRL_DDR2	0x10117
+ + #define SUSP_VTP_CTRL_DDR3	0x0
+ + 
+ + #define CPU_REV_1		1
+ + #define CPU_REV_2		2
+ + 
+ + #define M3_VERSION_UNKNOWN		0x0000ffff
+ + 
+ + #define PM_DS0			0
+ + #define PM_STANDBY		1
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/pm.c linux-3.2.1/arch/arm/mach-ckb_3352/pm.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/pm.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/pm.c	2014-11-25 13:19:15.038952183 +0900
+ ***************
+ *** 0 ****
+ --- 1,225 ----
+ + /*
+ +  * pm.c - Common OMAP2+ power management-related code
+ +  *
+ +  * Copyright (C) 2010 Texas Instruments, Inc.
+ +  * Copyright (C) 2010 Nokia Corporation
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #include <linux/kernel.h>
+ + #include <linux/init.h>
+ + #include <linux/io.h>
+ + #include <linux/err.h>
+ + #include <linux/opp.h>
+ + #include <linux/export.h>
+ + 
+ + #include <plat/omap-pm.h>
+ + #include <plat/omap_device.h>
+ + #include "common.h"
+ + 
+ + #include "voltage.h"
+ + #include "powerdomain.h"
+ + #include "clockdomain.h"
+ + #include "pm.h"
+ + #include "twl-common.h"
+ + 
+ + static struct omap_device_pm_latency *pm_lats;
+ + 
+ + static int _init_omap_device(char *name)
+ + {
+ + 	struct omap_hwmod *oh;
+ + 	struct platform_device *pdev;
+ + 
+ + 	oh = omap_hwmod_lookup(name);
+ + 	if (WARN(!oh, "%s: could not find omap_hwmod for %s\n",
+ + 		 __func__, name))
+ + 		return -ENODEV;
+ + 
+ + 	pdev = omap_device_build(oh->name, 0, oh, NULL, 0, pm_lats, 0, false);
+ + 	if (WARN(IS_ERR(pdev), "%s: could not build omap_device for %s\n",
+ + 		 __func__, name))
+ + 		return -ENODEV;
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /*
+ +  * Build omap_devices for processors and bus.
+ +  */
+ + static void omap2_init_processor_devices(void)
+ + {
+ + 	_init_omap_device("mpu");
+ + 	if (omap3_has_iva())
+ + 		_init_omap_device("iva");
+ + 
+ + 	_init_omap_device("l3_main");
+ + }
+ + 
+ + /* Types of sleep_switch used in omap_set_pwrdm_state */
+ + #define FORCEWAKEUP_SWITCH	0
+ + #define LOWPOWERSTATE_SWITCH	1
+ + 
+ + /*
+ +  * This sets pwrdm state (other than mpu & core. Currently only ON &
+ +  * RET are supported.
+ +  */
+ + int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
+ + {
+ + 	u32 cur_state;
+ + 	int sleep_switch = -1;
+ + 	int ret = 0;
+ + 	int hwsup = 0;
+ + 
+ + 	if (pwrdm == NULL || IS_ERR(pwrdm))
+ + 		return -EINVAL;
+ + 
+ + 	while (!(pwrdm->pwrsts & (1 << state))) {
+ + 		if (state == PWRDM_POWER_OFF)
+ + 			return ret;
+ + 		state--;
+ + 	}
+ + 
+ + 	cur_state = pwrdm_read_next_pwrst(pwrdm);
+ + 	if (cur_state == state)
+ + 		return ret;
+ + 
+ + 	if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
+ + 		if ((pwrdm_read_pwrst(pwrdm) > state) &&
+ + 			(pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE)) {
+ + 			sleep_switch = LOWPOWERSTATE_SWITCH;
+ + 		} else {
+ + 			hwsup = clkdm_in_hwsup(pwrdm->pwrdm_clkdms[0]);
+ + 			clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
+ + 			sleep_switch = FORCEWAKEUP_SWITCH;
+ + 		}
+ + 	}
+ + 
+ + 	ret = pwrdm_set_next_pwrst(pwrdm, state);
+ + 	if (ret) {
+ + 		pr_err("%s: unable to set state of powerdomain: %s\n",
+ + 		       __func__, pwrdm->name);
+ + 		goto err;
+ + 	}
+ + 
+ + 	switch (sleep_switch) {
+ + 	case FORCEWAKEUP_SWITCH:
+ + 		if (hwsup)
+ + 			clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
+ + 		else
+ + 			clkdm_sleep(pwrdm->pwrdm_clkdms[0]);
+ + 		break;
+ + 	case LOWPOWERSTATE_SWITCH:
+ + 		pwrdm_set_lowpwrstchange(pwrdm);
+ + 		break;
+ + 	default:
+ + 		return ret;
+ + 	}
+ + 
+ + 	pwrdm_state_switch(pwrdm);
+ + err:
+ + 	return ret;
+ + }
+ + 
+ + /*
+ +  * This API is to be called during init to set the various voltage
+ +  * domains to the voltage as per the opp table. Typically we boot up
+ +  * at the nominal voltage. So this function finds out the rate of
+ +  * the clock associated with the voltage domain, finds out the correct
+ +  * opp entry and sets the voltage domain to the voltage specified
+ +  * in the opp entry
+ +  */
+ + static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
+ + 					 const char *oh_name)
+ + {
+ + 	struct voltagedomain *voltdm;
+ + 	struct clk *clk;
+ + 	struct opp *opp;
+ + 	unsigned long freq, bootup_volt;
+ + 	struct device *dev;
+ + 
+ + 	if (!vdd_name || !clk_name || !oh_name) {
+ + 		pr_err("%s: invalid parameters\n", __func__);
+ + 		goto exit;
+ + 	}
+ + 
+ + 	dev = omap_device_get_by_hwmod_name(oh_name);
+ + 	if (IS_ERR(dev)) {
+ + 		pr_err("%s: Unable to get dev pointer for hwmod %s\n",
+ + 			__func__, oh_name);
+ + 		goto exit;
+ + 	}
+ + 
+ + 	voltdm = voltdm_lookup(vdd_name);
+ + 	if (IS_ERR(voltdm)) {
+ + 		pr_err("%s: unable to get vdd pointer for vdd_%s\n",
+ + 			__func__, vdd_name);
+ + 		goto exit;
+ + 	}
+ + 
+ + 	clk =  clk_get(NULL, clk_name);
+ + 	if (IS_ERR(clk)) {
+ + 		pr_err("%s: unable to get clk %s\n", __func__, clk_name);
+ + 		goto exit;
+ + 	}
+ + 
+ + 	freq = clk->rate;
+ + 	clk_put(clk);
+ + 
+ + 	opp = opp_find_freq_ceil(dev, &freq);
+ + 	if (IS_ERR(opp)) {
+ + 		pr_err("%s: unable to find boot up OPP for vdd_%s\n",
+ + 			__func__, vdd_name);
+ + 		goto exit;
+ + 	}
+ + 
+ + 	bootup_volt = opp_get_voltage(opp);
+ + 	if (!bootup_volt) {
+ + 		pr_err("%s: unable to find voltage corresponding "
+ + 			"to the bootup OPP for vdd_%s\n", __func__, vdd_name);
+ + 		goto exit;
+ + 	}
+ + 
+ + 	voltdm_scale(voltdm, bootup_volt);
+ + 	return 0;
+ + 
+ + exit:
+ + 	pr_err("%s: unable to set vdd_%s\n", __func__, vdd_name);
+ + 	return -EINVAL;
+ + }
+ + 
+ + static void __init omap3_init_voltages(void)
+ + {
+ + 	if (!cpu_is_omap34xx() || cpu_is_am33xx())
+ + 		return;
+ + 
+ + 	omap2_set_init_voltage("mpu_iva", "dpll1_ck", "mpu");
+ + 	omap2_set_init_voltage("core", "l3_ick", "l3_main");
+ + }
+ + 
+ + static int __init omap2_common_pm_init(void)
+ + {
+ + 	if (!of_have_populated_dt())
+ + 		omap2_init_processor_devices();
+ + 	omap_pm_if_init();
+ + 
+ + 	return 0;
+ + }
+ + postcore_initcall(omap2_common_pm_init);
+ + 
+ + static int __init omap2_common_pm_late_init(void)
+ + {
+ + 	/* Init the voltage layer */
+ + 	omap_voltage_late_init();
+ + 
+ + 	/* Initialize the voltages */
+ + 	omap3_init_voltages();
+ + 	
+ + 	/* Smartreflex device init */
+ + 	omap_devinit_smartreflex();
+ + 
+ + 	return 0;
+ + }
+ + late_initcall(omap2_common_pm_late_init);
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/pm-debug.c linux-3.2.1/arch/arm/mach-ckb_3352/pm-debug.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/pm-debug.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/pm-debug.c	2014-11-25 13:19:15.038952183 +0900
+ ***************
+ *** 0 ****
+ --- 1,278 ----
+ + /*
+ +  * OMAP Power Management debug routines
+ +  *
+ +  * Copyright (C) 2005 Texas Instruments, Inc.
+ +  * Copyright (C) 2006-2008 Nokia Corporation
+ +  *
+ +  * Written by:
+ +  * Richard Woodruff <r-woodruff2@ti.com>
+ +  * Tony Lindgren
+ +  * Juha Yrjola
+ +  * Amit Kucheria <amit.kucheria@nokia.com>
+ +  * Igor Stoppa <igor.stoppa@nokia.com>
+ +  * Jouni Hogander
+ +  *
+ +  * Based on pm.c for omap2
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #include <linux/kernel.h>
+ + #include <linux/sched.h>
+ + #include <linux/clk.h>
+ + #include <linux/err.h>
+ + #include <linux/io.h>
+ + #include <linux/module.h>
+ + #include <linux/slab.h>
+ + 
+ + #include <plat/clock.h>
+ + #include <plat/board.h>
+ + #include "powerdomain.h"
+ + #include "clockdomain.h"
+ + #include <plat/dmtimer.h>
+ + #include <plat/omap-pm.h>
+ + 
+ + #include "cm2xxx_3xxx.h"
+ + #include "prm2xxx_3xxx.h"
+ + #include "pm.h"
+ + 
+ + u32 enable_off_mode;
+ + 
+ + #ifdef CONFIG_DEBUG_FS
+ + #include <linux/debugfs.h>
+ + #include <linux/seq_file.h>
+ + 
+ + static int pm_dbg_init_done;
+ + 
+ + static int pm_dbg_init(void);
+ + 
+ + enum {
+ + 	DEBUG_FILE_COUNTERS = 0,
+ + 	DEBUG_FILE_TIMERS,
+ + };
+ + 
+ + static const char pwrdm_state_names[][PWRDM_MAX_PWRSTS] = {
+ + 	"OFF",
+ + 	"RET",
+ + 	"INA",
+ + 	"ON"
+ + };
+ + 
+ + void pm_dbg_update_time(struct powerdomain *pwrdm, int prev)
+ + {
+ + 	s64 t;
+ + 
+ + 	if (!pm_dbg_init_done)
+ + 		return ;
+ + 
+ + 	/* Update timer for previous state */
+ + 	t = sched_clock();
+ + 
+ + 	pwrdm->state_timer[prev] += t - pwrdm->timer;
+ + 
+ + 	pwrdm->timer = t;
+ + }
+ + 
+ + static int clkdm_dbg_show_counter(struct clockdomain *clkdm, void *user)
+ + {
+ + 	struct seq_file *s = (struct seq_file *)user;
+ + 
+ + 	if (strcmp(clkdm->name, "emu_clkdm") == 0 ||
+ + 		strcmp(clkdm->name, "wkup_clkdm") == 0 ||
+ + 		strncmp(clkdm->name, "dpll", 4) == 0)
+ + 		return 0;
+ + 
+ + 	seq_printf(s, "%s->%s (%d)", clkdm->name,
+ + 			clkdm->pwrdm.ptr->name,
+ + 			atomic_read(&clkdm->usecount));
+ + 	seq_printf(s, "\n");
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static int pwrdm_dbg_show_counter(struct powerdomain *pwrdm, void *user)
+ + {
+ + 	struct seq_file *s = (struct seq_file *)user;
+ + 	int i;
+ + 
+ + 	if (strcmp(pwrdm->name, "emu_pwrdm") == 0 ||
+ + 		strcmp(pwrdm->name, "wkup_pwrdm") == 0 ||
+ + 		strncmp(pwrdm->name, "dpll", 4) == 0)
+ + 		return 0;
+ + 
+ + 	if (pwrdm->state != pwrdm_read_pwrst(pwrdm))
+ + 		printk(KERN_ERR "pwrdm state mismatch(%s) %d != %d\n",
+ + 			pwrdm->name, pwrdm->state, pwrdm_read_pwrst(pwrdm));
+ + 
+ + 	seq_printf(s, "%s (%s)", pwrdm->name,
+ + 			pwrdm_state_names[pwrdm->state]);
+ + 	for (i = 0; i < PWRDM_MAX_PWRSTS; i++)
+ + 		seq_printf(s, ",%s:%d", pwrdm_state_names[i],
+ + 			pwrdm->state_counter[i]);
+ + 
+ + 	seq_printf(s, ",RET-LOGIC-OFF:%d", pwrdm->ret_logic_off_counter);
+ + 	for (i = 0; i < pwrdm->banks; i++)
+ + 		seq_printf(s, ",RET-MEMBANK%d-OFF:%d", i + 1,
+ + 				pwrdm->ret_mem_off_counter[i]);
+ + 
+ + 	seq_printf(s, "\n");
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static int pwrdm_dbg_show_timer(struct powerdomain *pwrdm, void *user)
+ + {
+ + 	struct seq_file *s = (struct seq_file *)user;
+ + 	int i;
+ + 
+ + 	if (strcmp(pwrdm->name, "emu_pwrdm") == 0 ||
+ + 		strcmp(pwrdm->name, "wkup_pwrdm") == 0 ||
+ + 		strncmp(pwrdm->name, "dpll", 4) == 0)
+ + 		return 0;
+ + 
+ + 	pwrdm_state_switch(pwrdm);
+ + 
+ + 	seq_printf(s, "%s (%s)", pwrdm->name,
+ + 		pwrdm_state_names[pwrdm->state]);
+ + 
+ + 	for (i = 0; i < 4; i++)
+ + 		seq_printf(s, ",%s:%lld", pwrdm_state_names[i],
+ + 			pwrdm->state_timer[i]);
+ + 
+ + 	seq_printf(s, "\n");
+ + 	return 0;
+ + }
+ + 
+ + static int pm_dbg_show_counters(struct seq_file *s, void *unused)
+ + {
+ + 	pwrdm_for_each(pwrdm_dbg_show_counter, s);
+ + 	clkdm_for_each(clkdm_dbg_show_counter, s);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static int pm_dbg_show_timers(struct seq_file *s, void *unused)
+ + {
+ + 	pwrdm_for_each(pwrdm_dbg_show_timer, s);
+ + 	return 0;
+ + }
+ + 
+ + static int pm_dbg_open(struct inode *inode, struct file *file)
+ + {
+ + 	switch ((int)inode->i_private) {
+ + 	case DEBUG_FILE_COUNTERS:
+ + 		return single_open(file, pm_dbg_show_counters,
+ + 			&inode->i_private);
+ + 	case DEBUG_FILE_TIMERS:
+ + 	default:
+ + 		return single_open(file, pm_dbg_show_timers,
+ + 			&inode->i_private);
+ + 	};
+ + }
+ + 
+ + static const struct file_operations debug_fops = {
+ + 	.open           = pm_dbg_open,
+ + 	.read           = seq_read,
+ + 	.llseek         = seq_lseek,
+ + 	.release        = single_release,
+ + };
+ + 
+ + static int pwrdm_suspend_get(void *data, u64 *val)
+ + {
+ + 	int ret = -EINVAL;
+ + 
+ + 	*val = ret;
+ + 
+ + 	if (ret >= 0)
+ + 		return 0;
+ + 	return *val;
+ + }
+ + 
+ + static int pwrdm_suspend_set(void *data, u64 val)
+ + {
+ + 	return -EINVAL;
+ + }
+ + 
+ + DEFINE_SIMPLE_ATTRIBUTE(pwrdm_suspend_fops, pwrdm_suspend_get,
+ + 			pwrdm_suspend_set, "%llu\n");
+ + 
+ + static int __init pwrdms_setup(struct powerdomain *pwrdm, void *dir)
+ + {
+ + 	int i;
+ + 	s64 t;
+ + 	struct dentry *d;
+ + 
+ + 	t = sched_clock();
+ + 
+ + 	for (i = 0; i < 4; i++)
+ + 		pwrdm->state_timer[i] = 0;
+ + 
+ + 	pwrdm->timer = t;
+ + 
+ + 	if (strncmp(pwrdm->name, "dpll", 4) == 0)
+ + 		return 0;
+ + 
+ + 	d = debugfs_create_dir(pwrdm->name, (struct dentry *)dir);
+ + 
+ + 	(void) debugfs_create_file("suspend", S_IRUGO|S_IWUSR, d,
+ + 			(void *)pwrdm, &pwrdm_suspend_fops);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static int option_get(void *data, u64 *val)
+ + {
+ + 	u32 *option = data;
+ + 
+ + 	*val = *option;
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static int option_set(void *data, u64 val)
+ + {
+ + 	u32 *option = data;
+ + 
+ + 	*option = val;
+ + 
+ + 	if (option == &enable_off_mode) {
+ + 		if (val)
+ + 			omap_pm_enable_off_mode();
+ + 		else
+ + 			omap_pm_disable_off_mode();
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ + 
+ + DEFINE_SIMPLE_ATTRIBUTE(pm_dbg_option_fops, option_get, option_set, "%llu\n");
+ + 
+ + static int __init pm_dbg_init(void)
+ + {
+ + 	struct dentry *d;
+ + 
+ + 	if (pm_dbg_init_done)
+ + 		return 0;
+ + 
+ + 	d = debugfs_create_dir("pm_debug", NULL);
+ + 	if (IS_ERR(d))
+ + 		return PTR_ERR(d);
+ + 
+ + 	(void) debugfs_create_file("count", S_IRUGO,
+ + 		d, (void *)DEBUG_FILE_COUNTERS, &debug_fops);
+ + 	(void) debugfs_create_file("time", S_IRUGO,
+ + 		d, (void *)DEBUG_FILE_TIMERS, &debug_fops);
+ + 
+ + 	pwrdm_for_each(pwrdms_setup, (void *)d);
+ + 
+ + 	(void) debugfs_create_file("enable_off_mode", S_IRUGO | S_IWUSR, d,
+ + 				   &enable_off_mode, &pm_dbg_option_fops);
+ + 	pm_dbg_init_done = 1;
+ + 
+ + 	return 0;
+ + }
+ + arch_initcall(pm_dbg_init);
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/pm.h linux-3.2.1/arch/arm/mach-ckb_3352/pm.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/pm.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/pm.h	2014-11-25 13:19:15.038952183 +0900
+ ***************
+ *** 0 ****
+ --- 1,124 ----
+ + /*
+ +  * OMAP2/3 Power Management Routines
+ +  *
+ +  * Copyright (C) 2008 Nokia Corporation
+ +  * Jouni Hogander
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + #ifndef __ARCH_ARM_MACH_OMAP2_PM_H
+ + #define __ARCH_ARM_MACH_OMAP2_PM_H
+ + 
+ + #include <linux/err.h>
+ + 
+ + #include "powerdomain.h"
+ + 
+ + extern void *omap3_secure_ram_storage;
+ + extern void omap3_pm_off_mode_enable(int);
+ + extern void omap_sram_idle(void);
+ + extern int omap3_can_sleep(void);
+ + extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
+ + extern int omap3_idle_init(void);
+ + extern int omap4_idle_init(void);
+ + 
+ + #if defined(CONFIG_PM_OPP)
+ + extern int omap3_opp_init(void);
+ + extern int omap4_opp_init(void);
+ + #else
+ + static inline int omap3_opp_init(void)
+ + {
+ + 	return -EINVAL;
+ + }
+ + static inline int omap4_opp_init(void)
+ + {
+ + 	return -EINVAL;
+ + }
+ + #endif
+ + 
+ + /*
+ +  * cpuidle mach specific parameters
+ +  *
+ +  * The board code can override the default C-states definition using
+ +  * omap3_pm_init_cpuidle
+ +  */
+ + struct cpuidle_params {
+ + 	u32 exit_latency;	/* exit_latency = sleep + wake-up latencies */
+ + 	u32 target_residency;
+ + 	u8 valid;		/* validates the C-state */
+ + };
+ + 
+ + #if defined(CONFIG_PM) && defined(CONFIG_CPU_IDLE)
+ + extern void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params);
+ + #else
+ + static
+ + inline void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
+ + {
+ + }
+ + #endif
+ + 
+ + extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
+ + extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
+ + 
+ + #ifdef CONFIG_PM_DEBUG
+ + extern u32 enable_off_mode;
+ + #else
+ + #define enable_off_mode 0
+ + #endif
+ + 
+ + #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
+ + extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev);
+ + #else
+ + #define pm_dbg_update_time(pwrdm, prev) do {} while (0);
+ + #endif /* CONFIG_PM_DEBUG */
+ + 
+ + /* 24xx */
+ + extern void omap24xx_idle_loop_suspend(void);
+ + extern unsigned int omap24xx_idle_loop_suspend_sz;
+ + 
+ + extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl,
+ + 					void __iomem *sdrc_power);
+ + extern unsigned int omap24xx_cpu_suspend_sz;
+ + 
+ + /* 3xxx */
+ + extern void omap34xx_cpu_suspend(int save_state);
+ + 
+ + /* save_secure_ram_context function pointer and size, for copy to SRAM */
+ + extern int save_secure_ram_context(u32 *addr);
+ + extern unsigned int save_secure_ram_context_sz;
+ + 
+ + extern void omap3_save_scratchpad_contents(void);
+ + 
+ + /* 33xx */
+ + /* am33xx_do_wfi function pointer and size, for copy to SRAM */
+ + extern void am33xx_do_wfi(void);
+ + extern unsigned int am33xx_do_wfi_sz;
+ + extern unsigned int am33xx_resume_offset;
+ + /* ... and its pointer from SRAM after copy */
+ + extern void (*am33xx_do_wfi_sram)(u32 *);
+ + /* The resume location */
+ + extern void am33xx_resume_vector(void);
+ + 
+ + #define PM_RTA_ERRATUM_i608		(1 << 0)
+ + #define PM_SDRC_WAKEUP_ERRATUM_i583	(1 << 1)
+ + 
+ + #if defined(CONFIG_PM)
+ + extern u16 pm34xx_errata;
+ + #define IS_PM34XX_ERRATUM(id)		(pm34xx_errata & (id))
+ + extern void enable_omap3630_toggle_l2_on_restore(void);
+ + #endif		/* defined(CONFIG_PM) */
+ + 
+ + #ifdef CONFIG_OMAP_SMARTREFLEX
+ + extern int omap_devinit_smartreflex(void);
+ + extern void omap_enable_smartreflex_on_init(void);
+ + #else
+ + static inline int omap_devinit_smartreflex(void)
+ + {
+ + 	return -EINVAL;
+ + }
+ + 
+ + static inline void omap_enable_smartreflex_on_init(void) {}
+ + #endif
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/powerdomain44xx.c linux-3.2.1/arch/arm/mach-ckb_3352/powerdomain44xx.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/powerdomain44xx.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/powerdomain44xx.c	2014-11-25 13:19:15.038952183 +0900
+ ***************
+ *** 0 ****
+ --- 1,225 ----
+ + /*
+ +  * OMAP4 powerdomain control
+ +  *
+ +  * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ +  * Copyright (C) 2007-2009 Nokia Corporation
+ +  *
+ +  * Derived from mach-omap2/powerdomain.c written by Paul Walmsley
+ +  * Rajendra Nayak <rnayak@ti.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #include <linux/io.h>
+ + #include <linux/errno.h>
+ + #include <linux/delay.h>
+ + 
+ + #include "powerdomain.h"
+ + #include <plat/prcm.h>
+ + #include "prm2xxx_3xxx.h"
+ + #include "prm44xx.h"
+ + #include "prminst44xx.h"
+ + #include "prm-regbits-44xx.h"
+ + 
+ + static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
+ + {
+ + 	omap4_prminst_rmw_inst_reg_bits(OMAP_POWERSTATE_MASK,
+ + 					(pwrst << OMAP_POWERSTATE_SHIFT),
+ + 					pwrdm->prcm_partition,
+ + 					pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+ + 	return 0;
+ + }
+ + 
+ + static int omap4_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
+ + {
+ + 	u32 v;
+ + 
+ + 	v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+ + 					pwrdm->pwrstctrl_offs);
+ + 	v &= OMAP_POWERSTATE_MASK;
+ + 	v >>= OMAP_POWERSTATE_SHIFT;
+ + 
+ + 	return v;
+ + }
+ + 
+ + static int omap4_pwrdm_read_pwrst(struct powerdomain *pwrdm)
+ + {
+ + 	u32 v;
+ + 
+ + 	v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+ + 					pwrdm->pwrstst_offs);
+ + 	v &= OMAP_POWERSTATEST_MASK;
+ + 	v >>= OMAP_POWERSTATEST_SHIFT;
+ + 
+ + 	return v;
+ + }
+ + 
+ + static int omap4_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
+ + {
+ + 	u32 v;
+ + 
+ + 	v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+ + 					pwrdm->pwrstst_offs);
+ + 	v &= OMAP4430_LASTPOWERSTATEENTERED_MASK;
+ + 	v >>= OMAP4430_LASTPOWERSTATEENTERED_SHIFT;
+ + 
+ + 	return v;
+ + }
+ + 
+ + static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
+ + {
+ + 	omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK,
+ + 					(1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT),
+ + 					pwrdm->prcm_partition,
+ + 					pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+ + 	return 0;
+ + }
+ + 
+ + static int omap4_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
+ + {
+ + 	omap4_prminst_rmw_inst_reg_bits(OMAP4430_LASTPOWERSTATEENTERED_MASK,
+ + 					OMAP4430_LASTPOWERSTATEENTERED_MASK,
+ + 					pwrdm->prcm_partition,
+ + 					pwrdm->prcm_offs, pwrdm->pwrstst_offs);
+ + 	return 0;
+ + }
+ + 
+ + static int omap4_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
+ + {
+ + 	u32 v;
+ + 
+ + 	v = pwrst << __ffs(OMAP4430_LOGICRETSTATE_MASK);
+ + 	omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v,
+ + 					pwrdm->prcm_partition, pwrdm->prcm_offs,
+ + 					pwrdm->pwrstctrl_offs);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static int omap4_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
+ + 				    u8 pwrst)
+ + {
+ + 	u32 m;
+ + 
+ + 	m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
+ + 
+ + 	omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
+ + 					pwrdm->prcm_partition, pwrdm->prcm_offs,
+ + 					pwrdm->pwrstctrl_offs);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
+ + 				     u8 pwrst)
+ + {
+ + 	u32 m;
+ + 
+ + 	m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
+ + 
+ + 	omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
+ + 					pwrdm->prcm_partition, pwrdm->prcm_offs,
+ + 					OMAP4_PM_PWSTCTRL);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static int omap4_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
+ + {
+ + 	u32 v;
+ + 
+ + 	v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+ + 					pwrdm->pwrstst_offs);
+ + 	v &= OMAP4430_LOGICSTATEST_MASK;
+ + 	v >>= OMAP4430_LOGICSTATEST_SHIFT;
+ + 
+ + 	return v;
+ + }
+ + 
+ + static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
+ + {
+ + 	u32 v;
+ + 
+ + 	v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+ + 					OMAP4_PM_PWSTCTRL);
+ + 	v &= OMAP4430_LOGICRETSTATE_MASK;
+ + 	v >>= OMAP4430_LOGICRETSTATE_SHIFT;
+ + 
+ + 	return v;
+ + }
+ + 
+ + static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
+ + {
+ + 	u32 m, v;
+ + 
+ + 	m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
+ + 
+ + 	v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+ + 					pwrdm->pwrstst_offs);
+ + 	v &= m;
+ + 	v >>= __ffs(m);
+ + 
+ + 	return v;
+ + }
+ + 
+ + static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
+ + {
+ + 	u32 m, v;
+ + 
+ + 	m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
+ + 
+ + 	v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+ + 					pwrdm->pwrstctrl_offs);
+ + 	v &= m;
+ + 	v >>= __ffs(m);
+ + 
+ + 	return v;
+ + }
+ + 
+ + static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
+ + {
+ + 	u32 c = 0;
+ + 
+ + 	/*
+ + 	 * REVISIT: pwrdm_wait_transition() may be better implemented
+ + 	 * via a callback and a periodic timer check -- how long do we expect
+ + 	 * powerdomain transitions to take?
+ + 	 */
+ + 
+ + 	/* XXX Is this udelay() value meaningful? */
+ + 	while ((omap4_prminst_read_inst_reg(pwrdm->prcm_partition,
+ + 					    pwrdm->prcm_offs,
+ + 					    pwrdm->pwrstst_offs) &
+ + 		OMAP_INTRANSITION_MASK) &&
+ + 	       (c++ < PWRDM_TRANSITION_BAILOUT))
+ + 		udelay(1);
+ + 
+ + 	if (c > PWRDM_TRANSITION_BAILOUT) {
+ + 		printk(KERN_ERR "powerdomain: waited too long for "
+ + 		       "powerdomain %s to complete transition\n", pwrdm->name);
+ + 		return -EAGAIN;
+ + 	}
+ + 
+ + 	pr_debug("powerdomain: completed transition in %d loops\n", c);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + struct pwrdm_ops omap4_pwrdm_operations = {
+ + 	.pwrdm_set_next_pwrst	= omap4_pwrdm_set_next_pwrst,
+ + 	.pwrdm_read_next_pwrst	= omap4_pwrdm_read_next_pwrst,
+ + 	.pwrdm_read_pwrst	= omap4_pwrdm_read_pwrst,
+ + 	.pwrdm_read_prev_pwrst	= omap4_pwrdm_read_prev_pwrst,
+ + 	.pwrdm_set_lowpwrstchange	= omap4_pwrdm_set_lowpwrstchange,
+ + 	.pwrdm_clear_all_prev_pwrst	= omap4_pwrdm_clear_all_prev_pwrst,
+ + 	.pwrdm_set_logic_retst	= omap4_pwrdm_set_logic_retst,
+ + 	.pwrdm_read_logic_pwrst	= omap4_pwrdm_read_logic_pwrst,
+ + 	.pwrdm_read_logic_retst	= omap4_pwrdm_read_logic_retst,
+ + 	.pwrdm_read_mem_pwrst	= omap4_pwrdm_read_mem_pwrst,
+ + 	.pwrdm_read_mem_retst	= omap4_pwrdm_read_mem_retst,
+ + 	.pwrdm_set_mem_onst	= omap4_pwrdm_set_mem_onst,
+ + 	.pwrdm_set_mem_retst	= omap4_pwrdm_set_mem_retst,
+ + 	.pwrdm_wait_transition	= omap4_pwrdm_wait_transition,
+ + };
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/powerdomain.c linux-3.2.1/arch/arm/mach-ckb_3352/powerdomain.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/powerdomain.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/powerdomain.c	2014-11-25 13:19:15.042940848 +0900
+ ***************
+ *** 0 ****
+ --- 1,1066 ----
+ + /*
+ +  * OMAP powerdomain control
+ +  *
+ +  * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
+ +  * Copyright (C) 2007-2011 Nokia Corporation
+ +  *
+ +  * Written by Paul Walmsley
+ +  * Added OMAP4 specific support by Abhijit Pagare <abhijitpagare@ti.com>
+ +  * State counting code by Tero Kristo <tero.kristo@nokia.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + #undef DEBUG
+ + 
+ + #include <linux/kernel.h>
+ + #include <linux/types.h>
+ + #include <linux/list.h>
+ + #include <linux/errno.h>
+ + #include <linux/string.h>
+ + #include <trace/events/power.h>
+ + 
+ + #include "cm2xxx_3xxx.h"
+ + #include "prcm44xx.h"
+ + #include "cm44xx.h"
+ + #include "prm2xxx_3xxx.h"
+ + 
+ + #include <asm/cpu.h>
+ + #include <plat/cpu.h>
+ + #include "powerdomain.h"
+ + #include "clockdomain.h"
+ + #include <plat/prcm.h>
+ + 
+ + #include "pm.h"
+ + 
+ + #define PWRDM_TRACE_STATES_FLAG	(1<<31)
+ + 
+ + enum {
+ + 	PWRDM_STATE_NOW = 0,
+ + 	PWRDM_STATE_PREV,
+ + };
+ + 
+ + 
+ + /* pwrdm_list contains all registered struct powerdomains */
+ + static LIST_HEAD(pwrdm_list);
+ + 
+ + static struct pwrdm_ops *arch_pwrdm;
+ + 
+ + /* Private functions */
+ + 
+ + static struct powerdomain *_pwrdm_lookup(const char *name)
+ + {
+ + 	struct powerdomain *pwrdm, *temp_pwrdm;
+ + 
+ + 	pwrdm = NULL;
+ + 
+ + 	list_for_each_entry(temp_pwrdm, &pwrdm_list, node) {
+ + 		if (!strcmp(name, temp_pwrdm->name)) {
+ + 			pwrdm = temp_pwrdm;
+ + 			break;
+ + 		}
+ + 	}
+ + 
+ + 	return pwrdm;
+ + }
+ + 
+ + /**
+ +  * _pwrdm_register - register a powerdomain
+ +  * @pwrdm: struct powerdomain * to register
+ +  *
+ +  * Adds a powerdomain to the internal powerdomain list.  Returns
+ +  * -EINVAL if given a null pointer, -EEXIST if a powerdomain is
+ +  * already registered by the provided name, or 0 upon success.
+ +  */
+ + static int _pwrdm_register(struct powerdomain *pwrdm)
+ + {
+ + 	int i;
+ + 	struct voltagedomain *voltdm;
+ + 
+ + 	if (!pwrdm || !pwrdm->name)
+ + 		return -EINVAL;
+ + 
+ + 	if (_pwrdm_lookup(pwrdm->name))
+ + 		return -EEXIST;
+ + 
+ + 	voltdm = voltdm_lookup(pwrdm->voltdm.name);
+ + 	if (!voltdm) {
+ + 		pr_err("powerdomain: %s: voltagedomain %s does not exist\n",
+ + 		       pwrdm->name, pwrdm->voltdm.name);
+ + 		return -EINVAL;
+ + 	}
+ + 	pwrdm->voltdm.ptr = voltdm;
+ + 	INIT_LIST_HEAD(&pwrdm->voltdm_node);
+ + 	voltdm_add_pwrdm(voltdm, pwrdm);
+ + 
+ + 	list_add(&pwrdm->node, &pwrdm_list);
+ + 
+ + 	/* Initialize the powerdomain's state counter */
+ + 	for (i = 0; i < PWRDM_MAX_PWRSTS; i++)
+ + 		pwrdm->state_counter[i] = 0;
+ + 
+ + 	pwrdm->ret_logic_off_counter = 0;
+ + 	for (i = 0; i < pwrdm->banks; i++)
+ + 		pwrdm->ret_mem_off_counter[i] = 0;
+ + 
+ + 	pwrdm_wait_transition(pwrdm);
+ + 	pwrdm->state = pwrdm_read_pwrst(pwrdm);
+ + 	pwrdm->state_counter[pwrdm->state] = 1;
+ + 
+ + 	pr_debug("powerdomain: registered %s\n", pwrdm->name);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static void _update_logic_membank_counters(struct powerdomain *pwrdm)
+ + {
+ + 	int i;
+ + 	u8 prev_logic_pwrst, prev_mem_pwrst;
+ + 
+ + 	prev_logic_pwrst = pwrdm_read_prev_logic_pwrst(pwrdm);
+ + 	if ((pwrdm->pwrsts_logic_ret == PWRSTS_OFF_RET) &&
+ + 	    (prev_logic_pwrst == PWRDM_POWER_OFF))
+ + 		pwrdm->ret_logic_off_counter++;
+ + 
+ + 	for (i = 0; i < pwrdm->banks; i++) {
+ + 		prev_mem_pwrst = pwrdm_read_prev_mem_pwrst(pwrdm, i);
+ + 
+ + 		if ((pwrdm->pwrsts_mem_ret[i] == PWRSTS_OFF_RET) &&
+ + 		    (prev_mem_pwrst == PWRDM_POWER_OFF))
+ + 			pwrdm->ret_mem_off_counter[i]++;
+ + 	}
+ + }
+ + 
+ + static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
+ + {
+ + 
+ + 	int prev, state, trace_state = 0;
+ + 
+ + 	if (pwrdm == NULL)
+ + 		return -EINVAL;
+ + 
+ + 	state = pwrdm_read_pwrst(pwrdm);
+ + 
+ + 	switch (flag) {
+ + 	case PWRDM_STATE_NOW:
+ + 		prev = pwrdm->state;
+ + 		break;
+ + 	case PWRDM_STATE_PREV:
+ + 		prev = pwrdm_read_prev_pwrst(pwrdm);
+ + 		if (pwrdm->state != prev)
+ + 			pwrdm->state_counter[prev]++;
+ + 		if (prev == PWRDM_POWER_RET)
+ + 			_update_logic_membank_counters(pwrdm);
+ + 		/*
+ + 		 * If the power domain did not hit the desired state,
+ + 		 * generate a trace event with both the desired and hit states
+ + 		 */
+ + 		if (state != prev) {
+ + 			trace_state = (PWRDM_TRACE_STATES_FLAG |
+ + 				       ((state & OMAP_POWERSTATE_MASK) << 8) |
+ + 				       ((prev & OMAP_POWERSTATE_MASK) << 0));
+ + 			trace_power_domain_target(pwrdm->name, trace_state,
+ + 						  smp_processor_id());
+ + 		}
+ + 		break;
+ + 	default:
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	if (state != prev)
+ + 		pwrdm->state_counter[state]++;
+ + 
+ + 	pm_dbg_update_time(pwrdm, prev);
+ + 
+ + 	pwrdm->state = state;
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static int _pwrdm_pre_transition_cb(struct powerdomain *pwrdm, void *unused)
+ + {
+ + 	pwrdm_clear_all_prev_pwrst(pwrdm);
+ + 	_pwrdm_state_switch(pwrdm, PWRDM_STATE_NOW);
+ + 	return 0;
+ + }
+ + 
+ + static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused)
+ + {
+ + 	_pwrdm_state_switch(pwrdm, PWRDM_STATE_PREV);
+ + 	return 0;
+ + }
+ + 
+ + /* Public functions */
+ + 
+ + /**
+ +  * pwrdm_register_platform_funcs - register powerdomain implementation fns
+ +  * @po: func pointers for arch specific implementations
+ +  *
+ +  * Register the list of function pointers used to implement the
+ +  * powerdomain functions on different OMAP SoCs.  Should be called
+ +  * before any other pwrdm_register*() function.  Returns -EINVAL if
+ +  * @po is null, -EEXIST if platform functions have already been
+ +  * registered, or 0 upon success.
+ +  */
+ + int pwrdm_register_platform_funcs(struct pwrdm_ops *po)
+ + {
+ + 	if (!po)
+ + 		return -EINVAL;
+ + 
+ + 	if (arch_pwrdm)
+ + 		return -EEXIST;
+ + 
+ + 	arch_pwrdm = po;
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * pwrdm_register_pwrdms - register SoC powerdomains
+ +  * @ps: pointer to an array of struct powerdomain to register
+ +  *
+ +  * Register the powerdomains available on a particular OMAP SoC.  Must
+ +  * be called after pwrdm_register_platform_funcs().  May be called
+ +  * multiple times.  Returns -EACCES if called before
+ +  * pwrdm_register_platform_funcs(); -EINVAL if the argument @ps is
+ +  * null; or 0 upon success.
+ +  */
+ + int pwrdm_register_pwrdms(struct powerdomain **ps)
+ + {
+ + 	struct powerdomain **p = NULL;
+ + 
+ + 	if (!arch_pwrdm)
+ + 		return -EEXIST;
+ + 
+ + 	if (!ps)
+ + 		return -EINVAL;
+ + 
+ + 	for (p = ps; *p; p++)
+ + 		_pwrdm_register(*p);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * pwrdm_complete_init - set up the powerdomain layer
+ +  *
+ +  * Do whatever is necessary to initialize registered powerdomains and
+ +  * powerdomain code.  Currently, this programs the next power state
+ +  * for each powerdomain to ON.  This prevents powerdomains from
+ +  * unexpectedly losing context or entering high wakeup latency modes
+ +  * with non-power-management-enabled kernels.  Must be called after
+ +  * pwrdm_register_pwrdms().  Returns -EACCES if called before
+ +  * pwrdm_register_pwrdms(), or 0 upon success.
+ +  */
+ + int pwrdm_complete_init(void)
+ + {
+ + 	struct powerdomain *temp_p;
+ + 
+ + 	if (list_empty(&pwrdm_list))
+ + 		return -EACCES;
+ + 
+ + 	list_for_each_entry(temp_p, &pwrdm_list, node)
+ + 		pwrdm_set_next_pwrst(temp_p, PWRDM_POWER_ON);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * pwrdm_lookup - look up a powerdomain by name, return a pointer
+ +  * @name: name of powerdomain
+ +  *
+ +  * Find a registered powerdomain by its name @name.  Returns a pointer
+ +  * to the struct powerdomain if found, or NULL otherwise.
+ +  */
+ + struct powerdomain *pwrdm_lookup(const char *name)
+ + {
+ + 	struct powerdomain *pwrdm;
+ + 
+ + 	if (!name)
+ + 		return NULL;
+ + 
+ + 	pwrdm = _pwrdm_lookup(name);
+ + 
+ + 	return pwrdm;
+ + }
+ + 
+ + /**
+ +  * pwrdm_for_each - call function on each registered clockdomain
+ +  * @fn: callback function *
+ +  *
+ +  * Call the supplied function @fn for each registered powerdomain.
+ +  * The callback function @fn can return anything but 0 to bail out
+ +  * early from the iterator.  Returns the last return value of the
+ +  * callback function, which should be 0 for success or anything else
+ +  * to indicate failure; or -EINVAL if the function pointer is null.
+ +  */
+ + int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
+ + 		   void *user)
+ + {
+ + 	struct powerdomain *temp_pwrdm;
+ + 	int ret = 0;
+ + 
+ + 	if (!fn)
+ + 		return -EINVAL;
+ + 
+ + 	list_for_each_entry(temp_pwrdm, &pwrdm_list, node) {
+ + 		ret = (*fn)(temp_pwrdm, user);
+ + 		if (ret)
+ + 			break;
+ + 	}
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * pwrdm_add_clkdm - add a clockdomain to a powerdomain
+ +  * @pwrdm: struct powerdomain * to add the clockdomain to
+ +  * @clkdm: struct clockdomain * to associate with a powerdomain
+ +  *
+ +  * Associate the clockdomain @clkdm with a powerdomain @pwrdm.  This
+ +  * enables the use of pwrdm_for_each_clkdm().  Returns -EINVAL if
+ +  * presented with invalid pointers; -ENOMEM if memory could not be allocated;
+ +  * or 0 upon success.
+ +  */
+ + int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
+ + {
+ + 	int i;
+ + 	int ret = -EINVAL;
+ + 
+ + 	if (!pwrdm || !clkdm)
+ + 		return -EINVAL;
+ + 
+ + 	pr_debug("powerdomain: associating clockdomain %s with powerdomain "
+ + 		 "%s\n", clkdm->name, pwrdm->name);
+ + 
+ + 	for (i = 0; i < PWRDM_MAX_CLKDMS; i++) {
+ + 		if (!pwrdm->pwrdm_clkdms[i])
+ + 			break;
+ + #ifdef DEBUG
+ + 		if (pwrdm->pwrdm_clkdms[i] == clkdm) {
+ + 			ret = -EINVAL;
+ + 			goto pac_exit;
+ + 		}
+ + #endif
+ + 	}
+ + 
+ + 	if (i == PWRDM_MAX_CLKDMS) {
+ + 		pr_debug("powerdomain: increase PWRDM_MAX_CLKDMS for "
+ + 			 "pwrdm %s clkdm %s\n", pwrdm->name, clkdm->name);
+ + 		WARN_ON(1);
+ + 		ret = -ENOMEM;
+ + 		goto pac_exit;
+ + 	}
+ + 
+ + 	pwrdm->pwrdm_clkdms[i] = clkdm;
+ + 
+ + 	ret = 0;
+ + 
+ + pac_exit:
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * pwrdm_del_clkdm - remove a clockdomain from a powerdomain
+ +  * @pwrdm: struct powerdomain * to add the clockdomain to
+ +  * @clkdm: struct clockdomain * to associate with a powerdomain
+ +  *
+ +  * Dissociate the clockdomain @clkdm from the powerdomain
+ +  * @pwrdm. Returns -EINVAL if presented with invalid pointers; -ENOENT
+ +  * if @clkdm was not associated with the powerdomain, or 0 upon
+ +  * success.
+ +  */
+ + int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
+ + {
+ + 	int ret = -EINVAL;
+ + 	int i;
+ + 
+ + 	if (!pwrdm || !clkdm)
+ + 		return -EINVAL;
+ + 
+ + 	pr_debug("powerdomain: dissociating clockdomain %s from powerdomain "
+ + 		 "%s\n", clkdm->name, pwrdm->name);
+ + 
+ + 	for (i = 0; i < PWRDM_MAX_CLKDMS; i++)
+ + 		if (pwrdm->pwrdm_clkdms[i] == clkdm)
+ + 			break;
+ + 
+ + 	if (i == PWRDM_MAX_CLKDMS) {
+ + 		pr_debug("powerdomain: clkdm %s not associated with pwrdm "
+ + 			 "%s ?!\n", clkdm->name, pwrdm->name);
+ + 		ret = -ENOENT;
+ + 		goto pdc_exit;
+ + 	}
+ + 
+ + 	pwrdm->pwrdm_clkdms[i] = NULL;
+ + 
+ + 	ret = 0;
+ + 
+ + pdc_exit:
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * pwrdm_for_each_clkdm - call function on each clkdm in a pwrdm
+ +  * @pwrdm: struct powerdomain * to iterate over
+ +  * @fn: callback function *
+ +  *
+ +  * Call the supplied function @fn for each clockdomain in the powerdomain
+ +  * @pwrdm.  The callback function can return anything but 0 to bail
+ +  * out early from the iterator.  Returns -EINVAL if presented with
+ +  * invalid pointers; or passes along the last return value of the
+ +  * callback function, which should be 0 for success or anything else
+ +  * to indicate failure.
+ +  */
+ + int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
+ + 			 int (*fn)(struct powerdomain *pwrdm,
+ + 				   struct clockdomain *clkdm))
+ + {
+ + 	int ret = 0;
+ + 	int i;
+ + 
+ + 	if (!fn)
+ + 		return -EINVAL;
+ + 
+ + 	for (i = 0; i < PWRDM_MAX_CLKDMS && !ret; i++)
+ + 		ret = (*fn)(pwrdm, pwrdm->pwrdm_clkdms[i]);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * pwrdm_get_voltdm - return a ptr to the voltdm that this pwrdm resides in
+ +  * @pwrdm: struct powerdomain *
+ +  *
+ +  * Return a pointer to the struct voltageomain that the specified powerdomain
+ +  * @pwrdm exists in.
+ +  */
+ + struct voltagedomain *pwrdm_get_voltdm(struct powerdomain *pwrdm)
+ + {
+ + 	return pwrdm->voltdm.ptr;
+ + }
+ + 
+ + /**
+ +  * pwrdm_get_mem_bank_count - get number of memory banks in this powerdomain
+ +  * @pwrdm: struct powerdomain *
+ +  *
+ +  * Return the number of controllable memory banks in powerdomain @pwrdm,
+ +  * starting with 1.  Returns -EINVAL if the powerdomain pointer is null.
+ +  */
+ + int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm)
+ + {
+ + 	if (!pwrdm)
+ + 		return -EINVAL;
+ + 
+ + 	return pwrdm->banks;
+ + }
+ + 
+ + /**
+ +  * pwrdm_set_next_pwrst - set next powerdomain power state
+ +  * @pwrdm: struct powerdomain * to set
+ +  * @pwrst: one of the PWRDM_POWER_* macros
+ +  *
+ +  * Set the powerdomain @pwrdm's next power state to @pwrst.  The powerdomain
+ +  * may not enter this state immediately if the preconditions for this state
+ +  * have not been satisfied.  Returns -EINVAL if the powerdomain pointer is
+ +  * null or if the power state is invalid for the powerdomin, or returns 0
+ +  * upon success.
+ +  */
+ + int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
+ + {
+ + 	int ret = -EINVAL;
+ + 
+ + 	if (!pwrdm)
+ + 		return -EINVAL;
+ + 
+ + 	if (!(pwrdm->pwrsts & (1 << pwrst)))
+ + 		return -EINVAL;
+ + 
+ + 	pr_debug("powerdomain: setting next powerstate for %s to %0x\n",
+ + 		 pwrdm->name, pwrst);
+ + 
+ + 	if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst) {
+ + 		/* Trace the pwrdm desired target state */
+ + 		trace_power_domain_target(pwrdm->name, pwrst,
+ + 					  smp_processor_id());
+ + 		/* Program the pwrdm desired target state */
+ + 		ret = arch_pwrdm->pwrdm_set_next_pwrst(pwrdm, pwrst);
+ + 	}
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * pwrdm_read_next_pwrst - get next powerdomain power state
+ +  * @pwrdm: struct powerdomain * to get power state
+ +  *
+ +  * Return the powerdomain @pwrdm's next power state.  Returns -EINVAL
+ +  * if the powerdomain pointer is null or returns the next power state
+ +  * upon success.
+ +  */
+ + int pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
+ + {
+ + 	int ret = -EINVAL;
+ + 
+ + 	if (!pwrdm)
+ + 		return -EINVAL;
+ + 
+ + 	if (arch_pwrdm && arch_pwrdm->pwrdm_read_next_pwrst)
+ + 		ret = arch_pwrdm->pwrdm_read_next_pwrst(pwrdm);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * pwrdm_read_pwrst - get current powerdomain power state
+ +  * @pwrdm: struct powerdomain * to get power state
+ +  *
+ +  * Return the powerdomain @pwrdm's current power state.	Returns -EINVAL
+ +  * if the powerdomain pointer is null or returns the current power state
+ +  * upon success.
+ +  */
+ + int pwrdm_read_pwrst(struct powerdomain *pwrdm)
+ + {
+ + 	int ret = -EINVAL;
+ + 
+ + 	if (!pwrdm)
+ + 		return -EINVAL;
+ + 
+ + 	if (arch_pwrdm && arch_pwrdm->pwrdm_read_pwrst)
+ + 		ret = arch_pwrdm->pwrdm_read_pwrst(pwrdm);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * pwrdm_read_prev_pwrst - get previous powerdomain power state
+ +  * @pwrdm: struct powerdomain * to get previous power state
+ +  *
+ +  * Return the powerdomain @pwrdm's previous power state.  Returns -EINVAL
+ +  * if the powerdomain pointer is null or returns the previous power state
+ +  * upon success.
+ +  */
+ + int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
+ + {
+ + 	int ret = -EINVAL;
+ + 
+ + 	if (!pwrdm)
+ + 		return -EINVAL;
+ + 
+ + 	if (arch_pwrdm && arch_pwrdm->pwrdm_read_prev_pwrst)
+ + 		ret = arch_pwrdm->pwrdm_read_prev_pwrst(pwrdm);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * pwrdm_set_logic_retst - set powerdomain logic power state upon retention
+ +  * @pwrdm: struct powerdomain * to set
+ +  * @pwrst: one of the PWRDM_POWER_* macros
+ +  *
+ +  * Set the next power state @pwrst that the logic portion of the
+ +  * powerdomain @pwrdm will enter when the powerdomain enters retention.
+ +  * This will be either RETENTION or OFF, if supported.  Returns
+ +  * -EINVAL if the powerdomain pointer is null or the target power
+ +  * state is not not supported, or returns 0 upon success.
+ +  */
+ + int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
+ + {
+ + 	int ret = -EINVAL;
+ + 
+ + 	if (!pwrdm)
+ + 		return -EINVAL;
+ + 
+ + 	if (!(pwrdm->pwrsts_logic_ret & (1 << pwrst)))
+ + 		return -EINVAL;
+ + 
+ + 	pr_debug("powerdomain: setting next logic powerstate for %s to %0x\n",
+ + 		 pwrdm->name, pwrst);
+ + 
+ + 	if (arch_pwrdm && arch_pwrdm->pwrdm_set_logic_retst)
+ + 		ret = arch_pwrdm->pwrdm_set_logic_retst(pwrdm, pwrst);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * pwrdm_set_mem_onst - set memory power state while powerdomain ON
+ +  * @pwrdm: struct powerdomain * to set
+ +  * @bank: memory bank number to set (0-3)
+ +  * @pwrst: one of the PWRDM_POWER_* macros
+ +  *
+ +  * Set the next power state @pwrst that memory bank @bank of the
+ +  * powerdomain @pwrdm will enter when the powerdomain enters the ON
+ +  * state.  @bank will be a number from 0 to 3, and represents different
+ +  * types of memory, depending on the powerdomain.  Returns -EINVAL if
+ +  * the powerdomain pointer is null or the target power state is not
+ +  * not supported for this memory bank, -EEXIST if the target memory
+ +  * bank does not exist or is not controllable, or returns 0 upon
+ +  * success.
+ +  */
+ + int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
+ + {
+ + 	int ret = -EINVAL;
+ + 
+ + 	if (!pwrdm)
+ + 		return -EINVAL;
+ + 
+ + 	if (pwrdm->banks < (bank + 1))
+ + 		return -EEXIST;
+ + 
+ + 	if (!(pwrdm->pwrsts_mem_on[bank] & (1 << pwrst)))
+ + 		return -EINVAL;
+ + 
+ + 	pr_debug("powerdomain: setting next memory powerstate for domain %s "
+ + 		 "bank %0x while pwrdm-ON to %0x\n", pwrdm->name, bank, pwrst);
+ + 
+ + 	if (arch_pwrdm && arch_pwrdm->pwrdm_set_mem_onst)
+ + 		ret = arch_pwrdm->pwrdm_set_mem_onst(pwrdm, bank, pwrst);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * pwrdm_set_mem_retst - set memory power state while powerdomain in RET
+ +  * @pwrdm: struct powerdomain * to set
+ +  * @bank: memory bank number to set (0-3)
+ +  * @pwrst: one of the PWRDM_POWER_* macros
+ +  *
+ +  * Set the next power state @pwrst that memory bank @bank of the
+ +  * powerdomain @pwrdm will enter when the powerdomain enters the
+ +  * RETENTION state.  Bank will be a number from 0 to 3, and represents
+ +  * different types of memory, depending on the powerdomain.  @pwrst
+ +  * will be either RETENTION or OFF, if supported.  Returns -EINVAL if
+ +  * the powerdomain pointer is null or the target power state is not
+ +  * not supported for this memory bank, -EEXIST if the target memory
+ +  * bank does not exist or is not controllable, or returns 0 upon
+ +  * success.
+ +  */
+ + int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
+ + {
+ + 	int ret = -EINVAL;
+ + 
+ + 	if (!pwrdm)
+ + 		return -EINVAL;
+ + 
+ + 	if (pwrdm->banks < (bank + 1))
+ + 		return -EEXIST;
+ + 
+ + 	if (!(pwrdm->pwrsts_mem_ret[bank] & (1 << pwrst)))
+ + 		return -EINVAL;
+ + 
+ + 	pr_debug("powerdomain: setting next memory powerstate for domain %s "
+ + 		 "bank %0x while pwrdm-RET to %0x\n", pwrdm->name, bank, pwrst);
+ + 
+ + 	if (arch_pwrdm && arch_pwrdm->pwrdm_set_mem_retst)
+ + 		ret = arch_pwrdm->pwrdm_set_mem_retst(pwrdm, bank, pwrst);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * pwrdm_read_logic_pwrst - get current powerdomain logic retention power state
+ +  * @pwrdm: struct powerdomain * to get current logic retention power state
+ +  *
+ +  * Return the power state that the logic portion of powerdomain @pwrdm
+ +  * will enter when the powerdomain enters retention.  Returns -EINVAL
+ +  * if the powerdomain pointer is null or returns the logic retention
+ +  * power state upon success.
+ +  */
+ + int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
+ + {
+ + 	int ret = -EINVAL;
+ + 
+ + 	if (!pwrdm)
+ + 		return -EINVAL;
+ + 
+ + 	if (arch_pwrdm && arch_pwrdm->pwrdm_read_logic_pwrst)
+ + 		ret = arch_pwrdm->pwrdm_read_logic_pwrst(pwrdm);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * pwrdm_read_prev_logic_pwrst - get previous powerdomain logic power state
+ +  * @pwrdm: struct powerdomain * to get previous logic power state
+ +  *
+ +  * Return the powerdomain @pwrdm's previous logic power state.  Returns
+ +  * -EINVAL if the powerdomain pointer is null or returns the previous
+ +  * logic power state upon success.
+ +  */
+ + int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
+ + {
+ + 	int ret = -EINVAL;
+ + 
+ + 	if (!pwrdm)
+ + 		return -EINVAL;
+ + 
+ + 	if (arch_pwrdm && arch_pwrdm->pwrdm_read_prev_logic_pwrst)
+ + 		ret = arch_pwrdm->pwrdm_read_prev_logic_pwrst(pwrdm);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * pwrdm_read_logic_retst - get next powerdomain logic power state
+ +  * @pwrdm: struct powerdomain * to get next logic power state
+ +  *
+ +  * Return the powerdomain pwrdm's logic power state.  Returns -EINVAL
+ +  * if the powerdomain pointer is null or returns the next logic
+ +  * power state upon success.
+ +  */
+ + int pwrdm_read_logic_retst(struct powerdomain *pwrdm)
+ + {
+ + 	int ret = -EINVAL;
+ + 
+ + 	if (!pwrdm)
+ + 		return -EINVAL;
+ + 
+ + 	if (arch_pwrdm && arch_pwrdm->pwrdm_read_logic_retst)
+ + 		ret = arch_pwrdm->pwrdm_read_logic_retst(pwrdm);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * pwrdm_read_mem_pwrst - get current memory bank power state
+ +  * @pwrdm: struct powerdomain * to get current memory bank power state
+ +  * @bank: memory bank number (0-3)
+ +  *
+ +  * Return the powerdomain @pwrdm's current memory power state for bank
+ +  * @bank.  Returns -EINVAL if the powerdomain pointer is null, -EEXIST if
+ +  * the target memory bank does not exist or is not controllable, or
+ +  * returns the current memory power state upon success.
+ +  */
+ + int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
+ + {
+ + 	int ret = -EINVAL;
+ + 
+ + 	if (!pwrdm)
+ + 		return ret;
+ + 
+ + 	if (pwrdm->banks < (bank + 1))
+ + 		return ret;
+ + 
+ + 	if (pwrdm->flags & PWRDM_HAS_MPU_QUIRK)
+ + 		bank = 1;
+ + 
+ + 	if (arch_pwrdm && arch_pwrdm->pwrdm_read_mem_pwrst)
+ + 		ret = arch_pwrdm->pwrdm_read_mem_pwrst(pwrdm, bank);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * pwrdm_read_prev_mem_pwrst - get previous memory bank power state
+ +  * @pwrdm: struct powerdomain * to get previous memory bank power state
+ +  * @bank: memory bank number (0-3)
+ +  *
+ +  * Return the powerdomain @pwrdm's previous memory power state for
+ +  * bank @bank.  Returns -EINVAL if the powerdomain pointer is null,
+ +  * -EEXIST if the target memory bank does not exist or is not
+ +  * controllable, or returns the previous memory power state upon
+ +  * success.
+ +  */
+ + int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
+ + {
+ + 	int ret = -EINVAL;
+ + 
+ + 	if (!pwrdm)
+ + 		return ret;
+ + 
+ + 	if (pwrdm->banks < (bank + 1))
+ + 		return ret;
+ + 
+ + 	if (pwrdm->flags & PWRDM_HAS_MPU_QUIRK)
+ + 		bank = 1;
+ + 
+ + 	if (arch_pwrdm && arch_pwrdm->pwrdm_read_prev_mem_pwrst)
+ + 		ret = arch_pwrdm->pwrdm_read_prev_mem_pwrst(pwrdm, bank);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * pwrdm_read_mem_retst - get next memory bank power state
+ +  * @pwrdm: struct powerdomain * to get mext memory bank power state
+ +  * @bank: memory bank number (0-3)
+ +  *
+ +  * Return the powerdomain pwrdm's next memory power state for bank
+ +  * x.  Returns -EINVAL if the powerdomain pointer is null, -EEXIST if
+ +  * the target memory bank does not exist or is not controllable, or
+ +  * returns the next memory power state upon success.
+ +  */
+ + int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
+ + {
+ + 	int ret = -EINVAL;
+ + 
+ + 	if (!pwrdm)
+ + 		return ret;
+ + 
+ + 	if (pwrdm->banks < (bank + 1))
+ + 		return ret;
+ + 
+ + 	if (arch_pwrdm && arch_pwrdm->pwrdm_read_mem_retst)
+ + 		ret = arch_pwrdm->pwrdm_read_mem_retst(pwrdm, bank);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * pwrdm_clear_all_prev_pwrst - clear previous powerstate register for a pwrdm
+ +  * @pwrdm: struct powerdomain * to clear
+ +  *
+ +  * Clear the powerdomain's previous power state register @pwrdm.
+ +  * Clears the entire register, including logic and memory bank
+ +  * previous power states.  Returns -EINVAL if the powerdomain pointer
+ +  * is null, or returns 0 upon success.
+ +  */
+ + int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
+ + {
+ + 	int ret = -EINVAL;
+ + 
+ + 	if (!pwrdm)
+ + 		return ret;
+ + 
+ + 	/*
+ + 	 * XXX should get the powerdomain's current state here;
+ + 	 * warn & fail if it is not ON.
+ + 	 */
+ + 
+ + 	pr_debug("powerdomain: clearing previous power state reg for %s\n",
+ + 		 pwrdm->name);
+ + 
+ + 	if (arch_pwrdm && arch_pwrdm->pwrdm_clear_all_prev_pwrst)
+ + 		ret = arch_pwrdm->pwrdm_clear_all_prev_pwrst(pwrdm);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * pwrdm_enable_hdwr_sar - enable automatic hardware SAR for a pwrdm
+ +  * @pwrdm: struct powerdomain *
+ +  *
+ +  * Enable automatic context save-and-restore upon power state change
+ +  * for some devices in the powerdomain @pwrdm.  Warning: this only
+ +  * affects a subset of devices in a powerdomain; check the TRM
+ +  * closely.  Returns -EINVAL if the powerdomain pointer is null or if
+ +  * the powerdomain does not support automatic save-and-restore, or
+ +  * returns 0 upon success.
+ +  */
+ + int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
+ + {
+ + 	int ret = -EINVAL;
+ + 
+ + 	if (!pwrdm)
+ + 		return ret;
+ + 
+ + 	if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR))
+ + 		return ret;
+ + 
+ + 	pr_debug("powerdomain: %s: setting SAVEANDRESTORE bit\n",
+ + 		 pwrdm->name);
+ + 
+ + 	if (arch_pwrdm && arch_pwrdm->pwrdm_enable_hdwr_sar)
+ + 		ret = arch_pwrdm->pwrdm_enable_hdwr_sar(pwrdm);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * pwrdm_disable_hdwr_sar - disable automatic hardware SAR for a pwrdm
+ +  * @pwrdm: struct powerdomain *
+ +  *
+ +  * Disable automatic context save-and-restore upon power state change
+ +  * for some devices in the powerdomain @pwrdm.  Warning: this only
+ +  * affects a subset of devices in a powerdomain; check the TRM
+ +  * closely.  Returns -EINVAL if the powerdomain pointer is null or if
+ +  * the powerdomain does not support automatic save-and-restore, or
+ +  * returns 0 upon success.
+ +  */
+ + int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
+ + {
+ + 	int ret = -EINVAL;
+ + 
+ + 	if (!pwrdm)
+ + 		return ret;
+ + 
+ + 	if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR))
+ + 		return ret;
+ + 
+ + 	pr_debug("powerdomain: %s: clearing SAVEANDRESTORE bit\n",
+ + 		 pwrdm->name);
+ + 
+ + 	if (arch_pwrdm && arch_pwrdm->pwrdm_disable_hdwr_sar)
+ + 		ret = arch_pwrdm->pwrdm_disable_hdwr_sar(pwrdm);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * pwrdm_has_hdwr_sar - test whether powerdomain supports hardware SAR
+ +  * @pwrdm: struct powerdomain *
+ +  *
+ +  * Returns 1 if powerdomain @pwrdm supports hardware save-and-restore
+ +  * for some devices, or 0 if it does not.
+ +  */
+ + bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm)
+ + {
+ + 	return (pwrdm && pwrdm->flags & PWRDM_HAS_HDWR_SAR) ? 1 : 0;
+ + }
+ + 
+ + /**
+ +  * pwrdm_set_lowpwrstchange - Request a low power state change
+ +  * @pwrdm: struct powerdomain *
+ +  *
+ +  * Allows a powerdomain to transtion to a lower power sleep state
+ +  * from an existing sleep state without waking up the powerdomain.
+ +  * Returns -EINVAL if the powerdomain pointer is null or if the
+ +  * powerdomain does not support LOWPOWERSTATECHANGE, or returns 0
+ +  * upon success.
+ +  */
+ + int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
+ + {
+ + 	int ret = -EINVAL;
+ + 
+ + 	if (!pwrdm)
+ + 		return -EINVAL;
+ + 
+ + 	if (!(pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE))
+ + 		return -EINVAL;
+ + 
+ + 	pr_debug("powerdomain: %s: setting LOWPOWERSTATECHANGE bit\n",
+ + 		 pwrdm->name);
+ + 
+ + 	if (arch_pwrdm && arch_pwrdm->pwrdm_set_lowpwrstchange)
+ + 		ret = arch_pwrdm->pwrdm_set_lowpwrstchange(pwrdm);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * pwrdm_wait_transition - wait for powerdomain power transition to finish
+ +  * @pwrdm: struct powerdomain * to wait for
+ +  *
+ +  * If the powerdomain @pwrdm is in the process of a state transition,
+ +  * spin until it completes the power transition, or until an iteration
+ +  * bailout value is reached. Returns -EINVAL if the powerdomain
+ +  * pointer is null, -EAGAIN if the bailout value was reached, or
+ +  * returns 0 upon success.
+ +  */
+ + int pwrdm_wait_transition(struct powerdomain *pwrdm)
+ + {
+ + 	int ret = -EINVAL;
+ + 
+ + 	if (!pwrdm)
+ + 		return -EINVAL;
+ + 
+ + 	if (arch_pwrdm && arch_pwrdm->pwrdm_wait_transition)
+ + 		ret = arch_pwrdm->pwrdm_wait_transition(pwrdm);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + int pwrdm_state_switch(struct powerdomain *pwrdm)
+ + {
+ + 	return _pwrdm_state_switch(pwrdm, PWRDM_STATE_NOW);
+ + }
+ + 
+ + int pwrdm_clkdm_state_switch(struct clockdomain *clkdm)
+ + {
+ + 	if (clkdm != NULL && clkdm->pwrdm.ptr != NULL) {
+ + 		pwrdm_wait_transition(clkdm->pwrdm.ptr);
+ + 		return pwrdm_state_switch(clkdm->pwrdm.ptr);
+ + 	}
+ + 
+ + 	return -EINVAL;
+ + }
+ + 
+ + int pwrdm_pre_transition(void)
+ + {
+ + 	pwrdm_for_each(_pwrdm_pre_transition_cb, NULL);
+ + 	return 0;
+ + }
+ + 
+ + int pwrdm_post_transition(void)
+ + {
+ + 	pwrdm_for_each(_pwrdm_post_transition_cb, NULL);
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * pwrdm_get_context_loss_count - get powerdomain's context loss count
+ +  * @pwrdm: struct powerdomain * to wait for
+ +  *
+ +  * Context loss count is the sum of powerdomain off-mode counter, the
+ +  * logic off counter and the per-bank memory off counter.  Returns negative
+ +  * (and WARNs) upon error, otherwise, returns the context loss count.
+ +  */
+ + int pwrdm_get_context_loss_count(struct powerdomain *pwrdm)
+ + {
+ + 	int i, count;
+ + 
+ + 	if (!pwrdm) {
+ + 		WARN(1, "powerdomain: %s: pwrdm is null\n", __func__);
+ + 		return -ENODEV;
+ + 	}
+ + 
+ + 	count = pwrdm->state_counter[PWRDM_POWER_OFF];
+ + 	count += pwrdm->ret_logic_off_counter;
+ + 
+ + 	for (i = 0; i < pwrdm->banks; i++)
+ + 		count += pwrdm->ret_mem_off_counter[i];
+ + 
+ + 	/*
+ + 	 * Context loss count has to be a non-negative value. Clear the sign
+ + 	 * bit to get a value range from 0 to INT_MAX.
+ + 	 */
+ + 	count &= INT_MAX;
+ + 
+ + 	pr_debug("powerdomain: %s: context loss count = %d\n",
+ + 		 pwrdm->name, count);
+ + 
+ + 	return count;
+ + }
+ + 
+ + /**
+ +  * pwrdm_can_ever_lose_context - can this powerdomain ever lose context?
+ +  * @pwrdm: struct powerdomain *
+ +  *
+ +  * Given a struct powerdomain * @pwrdm, returns 1 if the powerdomain
+ +  * can lose either memory or logic context or if @pwrdm is invalid, or
+ +  * returns 0 otherwise.  This function is not concerned with how the
+ +  * powerdomain registers are programmed (i.e., to go off or not); it's
+ +  * concerned with whether it's ever possible for this powerdomain to
+ +  * go off while some other part of the chip is active.  This function
+ +  * assumes that every powerdomain can go to either ON or INACTIVE.
+ +  */
+ + bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm)
+ + {
+ + 	int i;
+ + 
+ + 	if (IS_ERR_OR_NULL(pwrdm)) {
+ + 		pr_debug("powerdomain: %s: invalid powerdomain pointer\n",
+ + 			 __func__);
+ + 		return 1;
+ + 	}
+ + 
+ + 	if (pwrdm->pwrsts & PWRSTS_OFF)
+ + 		return 1;
+ + 
+ + 	if (pwrdm->pwrsts & PWRSTS_RET) {
+ + 		if (pwrdm->pwrsts_logic_ret & PWRSTS_OFF)
+ + 			return 1;
+ + 
+ + 		for (i = 0; i < pwrdm->banks; i++)
+ + 			if (pwrdm->pwrsts_mem_ret[i] & PWRSTS_OFF)
+ + 				return 1;
+ + 	}
+ + 
+ + 	for (i = 0; i < pwrdm->banks; i++)
+ + 		if (pwrdm->pwrsts_mem_on[i] & PWRSTS_OFF)
+ + 			return 1;
+ + 
+ + 	return 0;
+ + }
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/powerdomain-common.c linux-3.2.1/arch/arm/mach-ckb_3352/powerdomain-common.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/powerdomain-common.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/powerdomain-common.c	2014-11-25 13:19:15.042940848 +0900
+ ***************
+ *** 0 ****
+ --- 1,109 ----
+ + /*
+ +  * Common powerdomain framework functions
+ +  *
+ +  * Copyright (C) 2010-2011 Texas Instruments, Inc.
+ +  * Copyright (C) 2010 Nokia Corporation
+ +  *
+ +  * Derived from mach-omap2/powerdomain.c written by Paul Walmsley
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #include <linux/errno.h>
+ + #include <linux/kernel.h>
+ + #include "pm.h"
+ + #include "cm.h"
+ + #include "cm-regbits-34xx.h"
+ + #include "cm-regbits-44xx.h"
+ + #include "prm-regbits-34xx.h"
+ + #include "prm-regbits-44xx.h"
+ + 
+ + /*
+ +  * OMAP3 and OMAP4 specific register bit initialisations
+ +  * Notice that the names here are not according to each power
+ +  * domain but the bit mapping used applies to all of them
+ +  */
+ + /* OMAP3 and OMAP4 Memory Onstate Masks (common across all power domains) */
+ + #define OMAP_MEM0_ONSTATE_MASK OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK
+ + #define OMAP_MEM1_ONSTATE_MASK OMAP3430_L1FLATMEMONSTATE_MASK
+ + #define OMAP_MEM2_ONSTATE_MASK OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK
+ + #define OMAP_MEM3_ONSTATE_MASK OMAP3430_L2FLATMEMONSTATE_MASK
+ + #define OMAP_MEM4_ONSTATE_MASK OMAP4430_OCP_NRET_BANK_ONSTATE_MASK
+ + 
+ + /* OMAP3 and OMAP4 Memory Retstate Masks (common across all power domains) */
+ + #define OMAP_MEM0_RETSTATE_MASK OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK
+ + #define OMAP_MEM1_RETSTATE_MASK OMAP3430_L1FLATMEMRETSTATE_MASK
+ + #define OMAP_MEM2_RETSTATE_MASK OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK
+ + #define OMAP_MEM3_RETSTATE_MASK OMAP3430_L2FLATMEMRETSTATE_MASK
+ + #define OMAP_MEM4_RETSTATE_MASK OMAP4430_OCP_NRET_BANK_RETSTATE_MASK
+ + 
+ + /* OMAP3 and OMAP4 Memory Status bits */
+ + #define OMAP_MEM0_STATEST_MASK OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK
+ + #define OMAP_MEM1_STATEST_MASK OMAP3430_L1FLATMEMSTATEST_MASK
+ + #define OMAP_MEM2_STATEST_MASK OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK
+ + #define OMAP_MEM3_STATEST_MASK OMAP3430_L2FLATMEMSTATEST_MASK
+ + #define OMAP_MEM4_STATEST_MASK OMAP4430_OCP_NRET_BANK_STATEST_MASK
+ + 
+ + /* Common Internal functions used across OMAP rev's*/
+ + u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank)
+ + {
+ + 	switch (bank) {
+ + 	case 0:
+ + 		return OMAP_MEM0_ONSTATE_MASK;
+ + 	case 1:
+ + 		return OMAP_MEM1_ONSTATE_MASK;
+ + 	case 2:
+ + 		return OMAP_MEM2_ONSTATE_MASK;
+ + 	case 3:
+ + 		return OMAP_MEM3_ONSTATE_MASK;
+ + 	case 4:
+ + 		return OMAP_MEM4_ONSTATE_MASK;
+ + 	default:
+ + 		WARN_ON(1); /* should never happen */
+ + 		return -EEXIST;
+ + 	}
+ + 	return 0;
+ + }
+ + 
+ + u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank)
+ + {
+ + 	switch (bank) {
+ + 	case 0:
+ + 		return OMAP_MEM0_RETSTATE_MASK;
+ + 	case 1:
+ + 		return OMAP_MEM1_RETSTATE_MASK;
+ + 	case 2:
+ + 		return OMAP_MEM2_RETSTATE_MASK;
+ + 	case 3:
+ + 		return OMAP_MEM3_RETSTATE_MASK;
+ + 	case 4:
+ + 		return OMAP_MEM4_RETSTATE_MASK;
+ + 	default:
+ + 		WARN_ON(1); /* should never happen */
+ + 		return -EEXIST;
+ + 	}
+ + 	return 0;
+ + }
+ + 
+ + u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank)
+ + {
+ + 	switch (bank) {
+ + 	case 0:
+ + 		return OMAP_MEM0_STATEST_MASK;
+ + 	case 1:
+ + 		return OMAP_MEM1_STATEST_MASK;
+ + 	case 2:
+ + 		return OMAP_MEM2_STATEST_MASK;
+ + 	case 3:
+ + 		return OMAP_MEM3_STATEST_MASK;
+ + 	case 4:
+ + 		return OMAP_MEM4_STATEST_MASK;
+ + 	default:
+ + 		WARN_ON(1); /* should never happen */
+ + 		return -EEXIST;
+ + 	}
+ + 	return 0;
+ + }
+ + 
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/powerdomain.h linux-3.2.1/arch/arm/mach-ckb_3352/powerdomain.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/powerdomain.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/powerdomain.h	2014-11-25 13:19:15.042940848 +0900
+ ***************
+ *** 0 ****
+ --- 1,242 ----
+ + /*
+ +  * OMAP2/3/4 powerdomain control
+ +  *
+ +  * Copyright (C) 2007-2008, 2010 Texas Instruments, Inc.
+ +  * Copyright (C) 2007-2011 Nokia Corporation
+ +  *
+ +  * Paul Walmsley
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  *
+ +  * XXX This should be moved to the mach-omap2/ directory at the earliest
+ +  * opportunity.
+ +  */
+ + 
+ + #ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H
+ + #define __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H
+ + 
+ + #include <linux/types.h>
+ + #include <linux/list.h>
+ + 
+ + #include <linux/atomic.h>
+ + 
+ + #include <plat/cpu.h>
+ + 
+ + #include "voltage.h"
+ + 
+ + /* Powerdomain basic power states */
+ + #define PWRDM_POWER_OFF		0x0
+ + #define PWRDM_POWER_RET		0x1
+ + #define PWRDM_POWER_INACTIVE	0x2
+ + #define PWRDM_POWER_ON		0x3
+ + 
+ + #define PWRDM_MAX_PWRSTS	4
+ + 
+ + /* Powerdomain allowable state bitfields */
+ + #define PWRSTS_ON		(1 << PWRDM_POWER_ON)
+ + #define PWRSTS_INACTIVE		(1 << PWRDM_POWER_INACTIVE)
+ + #define PWRSTS_RET		(1 << PWRDM_POWER_RET)
+ + #define PWRSTS_OFF		(1 << PWRDM_POWER_OFF)
+ + 
+ + #define PWRSTS_OFF_ON		(PWRSTS_OFF | PWRSTS_ON)
+ + #define PWRSTS_OFF_RET		(PWRSTS_OFF | PWRSTS_RET)
+ + #define PWRSTS_RET_ON		(PWRSTS_RET | PWRSTS_ON)
+ + #define PWRSTS_OFF_RET_ON	(PWRSTS_OFF_RET | PWRSTS_ON)
+ + 
+ + 
+ + /* Powerdomain flags */
+ + #define PWRDM_HAS_HDWR_SAR	(1 << 0) /* hardware save-and-restore support */
+ + #define PWRDM_HAS_MPU_QUIRK	(1 << 1) /* MPU pwr domain has MEM bank 0 bits
+ + 					  * in MEM bank 1 position. This is
+ + 					  * true for OMAP3430
+ + 					  */
+ + #define PWRDM_HAS_LOWPOWERSTATECHANGE	(1 << 2) /*
+ + 						  * support to transition from a
+ + 						  * sleep state to a lower sleep
+ + 						  * state without waking up the
+ + 						  * powerdomain
+ + 						  */
+ + 
+ + /*
+ +  * Number of memory banks that are power-controllable.	On OMAP4430, the
+ +  * maximum is 5.
+ +  */
+ + #define PWRDM_MAX_MEM_BANKS	5
+ + 
+ + /*
+ +  * Maximum number of clockdomains that can be associated with a powerdomain.
+ +  * CORE powerdomain on AM33XX is the worst case
+ +  */
+ + #define PWRDM_MAX_CLKDMS	11
+ + 
+ + /* XXX A completely arbitrary number. What is reasonable here? */
+ + #define PWRDM_TRANSITION_BAILOUT 100000
+ + 
+ + struct clockdomain;
+ + struct powerdomain;
+ + 
+ + /**
+ +  * struct powerdomain - OMAP powerdomain
+ +  * @name: Powerdomain name
+ +  * @voltdm: voltagedomain containing this powerdomain
+ +  * @prcm_offs: the address offset from CM_BASE/PRM_BASE
+ +  * @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs
+ +  * @pwrsts: Possible powerdomain power states
+ +  * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION
+ +  * @flags: Powerdomain flags
+ +  * @banks: Number of software-controllable memory banks in this powerdomain
+ +  * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION
+ +  * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON
+ +  * @pwrdm_clkdms: Clockdomains in this powerdomain
+ +  * @node: list_head linking all powerdomains
+ +  * @voltdm_node: list_head linking all powerdomains in a voltagedomain
+ +  * @pwrstctrl_offs: XXX_PWRSTCTRL reg offset from prcm_offs
+ +  * @pwrstst_offs: XXX_PWRSTST reg offset from prcm_offs
+ +  * @state:
+ +  * @state_counter:
+ +  * @timer:
+ +  * @state_timer:
+ +  *
+ +  * @prcm_partition possible values are defined in mach-omap2/prcm44xx.h.
+ +  */
+ + struct powerdomain {
+ + 	const char *name;
+ + 	union {
+ + 		const char *name;
+ + 		struct voltagedomain *ptr;
+ + 	} voltdm;
+ + 	const s16 prcm_offs;
+ + 	const u8 pwrsts;
+ + 	const u8 pwrsts_logic_ret;
+ + 	const u8 flags;
+ + 	const u8 banks;
+ + 	const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
+ + 	const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
+ + 	const u8 prcm_partition;
+ + 	struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
+ + 	struct list_head node;
+ + 	struct list_head voltdm_node;
+ + 	int state;
+ + 	unsigned state_counter[PWRDM_MAX_PWRSTS];
+ + 	unsigned ret_logic_off_counter;
+ + 	unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];
+ + 
+ + 	u8 pwrstctrl_offs;
+ + 	u8 pwrstst_offs;
+ + #ifdef CONFIG_PM_DEBUG
+ + 	s64 timer;
+ + 	s64 state_timer[PWRDM_MAX_PWRSTS];
+ + #endif
+ + };
+ + 
+ + /**
+ +  * struct pwrdm_ops - Arch specific function implementations
+ +  * @pwrdm_set_next_pwrst: Set the target power state for a pd
+ +  * @pwrdm_read_next_pwrst: Read the target power state set for a pd
+ +  * @pwrdm_read_pwrst: Read the current power state of a pd
+ +  * @pwrdm_read_prev_pwrst: Read the prev power state entered by the pd
+ +  * @pwrdm_set_logic_retst: Set the logic state in RET for a pd
+ +  * @pwrdm_set_mem_onst: Set the Memory state in ON for a pd
+ +  * @pwrdm_set_mem_retst: Set the Memory state in RET for a pd
+ +  * @pwrdm_read_logic_pwrst: Read the current logic state of a pd
+ +  * @pwrdm_read_prev_logic_pwrst: Read the previous logic state entered by a pd
+ +  * @pwrdm_read_logic_retst: Read the logic state in RET for a pd
+ +  * @pwrdm_read_mem_pwrst: Read the current memory state of a pd
+ +  * @pwrdm_read_prev_mem_pwrst: Read the previous memory state entered by a pd
+ +  * @pwrdm_read_mem_retst: Read the memory state in RET for a pd
+ +  * @pwrdm_clear_all_prev_pwrst: Clear all previous power states logged for a pd
+ +  * @pwrdm_enable_hdwr_sar: Enable Hardware Save-Restore feature for the pd
+ +  * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd
+ +  * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep
+ +  * @pwrdm_wait_transition: Wait for a pd state transition to complete
+ +  */
+ + struct pwrdm_ops {
+ + 	int	(*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst);
+ + 	int	(*pwrdm_read_next_pwrst)(struct powerdomain *pwrdm);
+ + 	int	(*pwrdm_read_pwrst)(struct powerdomain *pwrdm);
+ + 	int	(*pwrdm_read_prev_pwrst)(struct powerdomain *pwrdm);
+ + 	int	(*pwrdm_set_logic_retst)(struct powerdomain *pwrdm, u8 pwrst);
+ + 	int	(*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
+ + 	int	(*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
+ + 	int	(*pwrdm_read_logic_pwrst)(struct powerdomain *pwrdm);
+ + 	int	(*pwrdm_read_prev_logic_pwrst)(struct powerdomain *pwrdm);
+ + 	int	(*pwrdm_read_logic_retst)(struct powerdomain *pwrdm);
+ + 	int	(*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
+ + 	int	(*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
+ + 	int	(*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank);
+ + 	int	(*pwrdm_clear_all_prev_pwrst)(struct powerdomain *pwrdm);
+ + 	int	(*pwrdm_enable_hdwr_sar)(struct powerdomain *pwrdm);
+ + 	int	(*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm);
+ + 	int	(*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm);
+ + 	int	(*pwrdm_wait_transition)(struct powerdomain *pwrdm);
+ + };
+ + 
+ + int pwrdm_register_platform_funcs(struct pwrdm_ops *custom_funcs);
+ + int pwrdm_register_pwrdms(struct powerdomain **pwrdm_list);
+ + int pwrdm_complete_init(void);
+ + 
+ + struct powerdomain *pwrdm_lookup(const char *name);
+ + 
+ + int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
+ + 			void *user);
+ + int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
+ + 			void *user);
+ + 
+ + int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
+ + int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
+ + int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
+ + 			 int (*fn)(struct powerdomain *pwrdm,
+ + 				   struct clockdomain *clkdm));
+ + struct voltagedomain *pwrdm_get_voltdm(struct powerdomain *pwrdm);
+ + 
+ + int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
+ + 
+ + int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
+ + int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
+ + int pwrdm_read_pwrst(struct powerdomain *pwrdm);
+ + int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
+ + int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
+ + 
+ + int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
+ + int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
+ + int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
+ + 
+ + int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
+ + int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
+ + int pwrdm_read_logic_retst(struct powerdomain *pwrdm);
+ + int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
+ + int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
+ + int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
+ + 
+ + int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
+ + int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
+ + bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
+ + 
+ + int pwrdm_wait_transition(struct powerdomain *pwrdm);
+ + 
+ + int pwrdm_state_switch(struct powerdomain *pwrdm);
+ + int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
+ + int pwrdm_pre_transition(void);
+ + int pwrdm_post_transition(void);
+ + int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
+ + int pwrdm_get_context_loss_count(struct powerdomain *pwrdm);
+ + bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
+ + 
+ + extern void am33xx_powerdomains_init(void);
+ + 
+ + 
+ + extern struct pwrdm_ops omap3_pwrdm_operations;
+ + extern struct pwrdm_ops omap4_pwrdm_operations;
+ + 
+ + /* Common Internal functions used across OMAP rev's */
+ + extern u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank);
+ + extern u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank);
+ + extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank);
+ + 
+ + extern struct powerdomain wkup_omap2_pwrdm;
+ + extern struct powerdomain gfx_omap2_pwrdm;
+ + 
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/powerdomains2xxx_3xxx_data.c linux-3.2.1/arch/arm/mach-ckb_3352/powerdomains2xxx_3xxx_data.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/powerdomains2xxx_3xxx_data.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/powerdomains2xxx_3xxx_data.c	2014-11-25 13:19:15.042940848 +0900
+ ***************
+ *** 0 ****
+ --- 1,65 ----
+ + /*
+ +  * OMAP2/3 common powerdomain definitions
+ +  *
+ +  * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
+ +  * Copyright (C) 2007-2011 Nokia Corporation
+ +  *
+ +  * Paul Walmsley, Jouni Högander
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + /*
+ +  * The names for the DSP/IVA2 powerdomains are confusing.
+ +  *
+ +  * Most OMAP chips have an on-board DSP.
+ +  *
+ +  * On the 2420, this is a 'C55 DSP called, simply, the DSP.  Its
+ +  * powerdomain is called the "DSP power domain."  On the 2430, the
+ +  * on-board DSP is a 'C64 DSP, now called (along with its hardware
+ +  * accelerators) the IVA2 or IVA2.1.  Its powerdomain is still called
+ +  * the "DSP power domain." On the 3430, the DSP is a 'C64 DSP like the
+ +  * 2430, also known as the IVA2; but its powerdomain is now called the
+ +  * "IVA2 power domain."
+ +  *
+ +  * The 2420 also has something called the IVA, which is a separate ARM
+ +  * core, and has nothing to do with the DSP/IVA2.
+ +  *
+ +  * Ideally the DSP/IVA2 could just be the same powerdomain, but the PRCM
+ +  * address offset is different between the C55 and C64 DSPs.
+ +  */
+ + 
+ + #include "powerdomain.h"
+ + 
+ + #include "prcm-common.h"
+ + #include "prm.h"
+ + 
+ + /* OMAP2/3-common powerdomains */
+ + 
+ + /*
+ +  * The GFX powerdomain is not present on 3430ES2, but currently we do not
+ +  * have a macro to filter it out at compile-time.
+ +  */
+ + struct powerdomain gfx_omap2_pwrdm = {
+ + 	.name		  = "gfx_pwrdm",
+ + 	.prcm_offs	  = GFX_MOD,
+ + 	.pwrsts		  = PWRSTS_OFF_RET_ON,
+ + 	.pwrsts_logic_ret = PWRSTS_RET,
+ + 	.banks		  = 1,
+ + 	.pwrsts_mem_ret	  = {
+ + 		[0] = PWRSTS_RET, /* MEMRETSTATE */
+ + 	},
+ + 	.pwrsts_mem_on	  = {
+ + 		[0] = PWRSTS_ON,  /* MEMONSTATE */
+ + 	},
+ + 	.voltdm           = { .name = "core" },
+ + };
+ + 
+ + struct powerdomain wkup_omap2_pwrdm = {
+ + 	.name		= "wkup_pwrdm",
+ + 	.prcm_offs	= WKUP_MOD,
+ + 	.pwrsts		= PWRSTS_ON,
+ + 	.voltdm         = { .name = "wakeup" },
+ + };
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/powerdomains2xxx_3xxx_data.h linux-3.2.1/arch/arm/mach-ckb_3352/powerdomains2xxx_3xxx_data.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/powerdomains2xxx_3xxx_data.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/powerdomains2xxx_3xxx_data.h	2014-11-25 13:19:15.042940848 +0900
+ ***************
+ *** 0 ****
+ --- 1,22 ----
+ + /*
+ +  * OMAP2/3 common powerdomains - prototypes
+ +  *
+ +  * Copyright (C) 2008 Texas Instruments, Inc.
+ +  * Copyright (C) 2008-2010 Nokia Corporation
+ +  *
+ +  * Paul Walmsley
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAINS2XXX_3XXX_DATA_H
+ + #define __ARCH_ARM_MACH_OMAP2_POWERDOMAINS2XXX_3XXX_DATA_H
+ + 
+ + #include "powerdomain.h"
+ + 
+ + extern struct powerdomain gfx_omap2_pwrdm;
+ + extern struct powerdomain wkup_omap2_pwrdm;
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/powerdomains33xx_data.c linux-3.2.1/arch/arm/mach-ckb_3352/powerdomains33xx_data.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/powerdomains33xx_data.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/powerdomains33xx_data.c	2014-11-25 13:19:15.047478510 +0900
+ ***************
+ *** 0 ****
+ --- 1,134 ----
+ + /*
+ +  * AM33XX Power domains framework
+ +  *
+ +  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #include <linux/kernel.h>
+ + #include <linux/init.h>
+ + 
+ + #include "powerdomain.h"
+ + #include "prcm-common.h"
+ + #include "prm33xx.h"
+ + #include "prcm44xx.h"
+ + 
+ + static struct powerdomain gfx_33xx_pwrdm = {
+ + 	.name			= "gfx_pwrdm",
+ + 	.voltdm			= { .name = "core" },
+ + 	.prcm_partition		= AM33XX_PRM_PARTITION,
+ + 	.prcm_offs		= AM33XX_PRM_GFX_MOD,
+ + 	.pwrsts			= PWRSTS_OFF_ON,
+ + 	.pwrsts_logic_ret	= PWRSTS_OFF_RET,
+ + 	.pwrstctrl_offs		= AM33XX_PM_GFX_PWRSTCTRL_OFFSET,
+ + 	.pwrstst_offs		= AM33XX_PM_GFX_PWRSTST_OFFSET,
+ + 	.flags			= PWRDM_HAS_LOWPOWERSTATECHANGE,
+ + 	.banks			= 1,
+ + 	.pwrsts_mem_ret		= {
+ + 		[0]	= PWRSTS_OFF_RET,	/* gfx_mem */
+ + 	},
+ + 	.pwrsts_mem_on		= {
+ + 		[0]	= PWRSTS_ON,		/* gfx_mem */
+ + 	},
+ + };
+ + 
+ + static struct powerdomain rtc_33xx_pwrdm = {
+ + 	.name			= "rtc_pwrdm",
+ + 	.voltdm			= { .name = "rtc" },
+ + 	.prcm_partition		= AM33XX_PRM_PARTITION,
+ + 	.prcm_offs		= AM33XX_PRM_RTC_MOD,
+ + 	.pwrsts			= PWRSTS_ON,
+ + 	.pwrstctrl_offs		= AM33XX_PM_RTC_PWRSTCTRL_OFFSET,
+ + 	.pwrstst_offs		= AM33XX_PM_RTC_PWRSTST_OFFSET,
+ + };
+ + 
+ + static struct powerdomain wkup_33xx_pwrdm = {
+ + 	.name			= "wkup_pwrdm",
+ + 	.voltdm			= { .name = "core" },
+ + 	.prcm_partition		= AM33XX_PRM_PARTITION,
+ + 	.prcm_offs		= AM33XX_PRM_WKUP_MOD,
+ + 	.pwrsts			= PWRSTS_ON,
+ + 	.pwrstctrl_offs		= AM33XX_PM_WKUP_PWRSTCTRL_OFFSET,
+ + 	.pwrstst_offs		= AM33XX_PM_WKUP_PWRSTST_OFFSET,
+ + };
+ + 
+ + static struct powerdomain per_33xx_pwrdm = {
+ + 	.name			= "per_pwrdm",
+ + 	.voltdm			= { .name = "core" },
+ + 	.prcm_partition		= AM33XX_PRM_PARTITION,
+ + 	.prcm_offs		= AM33XX_PRM_PER_MOD,
+ + 	.pwrsts			= PWRSTS_OFF_RET_ON,
+ + 	.pwrsts_logic_ret	= PWRSTS_OFF_RET,
+ + 	.pwrstctrl_offs		= AM33XX_PM_PER_PWRSTCTRL_OFFSET,
+ + 	.pwrstst_offs		= AM33XX_PM_PER_PWRSTST_OFFSET,
+ + 	.flags			= PWRDM_HAS_LOWPOWERSTATECHANGE,
+ + 	.banks			= 3,
+ + 	.pwrsts_mem_ret		= {
+ + 		[0]	= PWRSTS_OFF_RET,	/* pruss_mem */
+ + 		[1]	= PWRSTS_OFF_RET,	/* per_mem */
+ + 		[2]	= PWRSTS_OFF_RET,	/* ram_mem */
+ + 	},
+ + 	.pwrsts_mem_on		= {
+ + 		[0]	= PWRSTS_ON,		/* pruss_mem */
+ + 		[1]	= PWRSTS_ON,		/* per_mem */
+ + 		[2]	= PWRSTS_ON,		/* ram_mem */
+ + 	},
+ + };
+ + 
+ + static struct powerdomain mpu_33xx_pwrdm = {
+ + 	.name			= "mpu_pwrdm",
+ + 	.voltdm			= { .name = "mpu" },
+ + 	.prcm_partition		= AM33XX_PRM_PARTITION,
+ + 	.prcm_offs		= AM33XX_PRM_MPU_MOD,
+ + 	.pwrsts			= PWRSTS_OFF_RET_ON,
+ + 	.pwrsts_logic_ret	= PWRSTS_OFF_RET,
+ + 	.pwrstctrl_offs		= AM33XX_PM_MPU_PWRSTCTRL_OFFSET,
+ + 	.pwrstst_offs		= AM33XX_PM_MPU_PWRSTST_OFFSET,
+ + 	.flags			= PWRDM_HAS_LOWPOWERSTATECHANGE,
+ + 	.banks			= 3,
+ + 	.pwrsts_mem_ret		= {
+ + 		[0]	= PWRSTS_OFF_RET,	/* mpu_l1 */
+ + 		[1]	= PWRSTS_OFF_RET,	/* mpu_l2 */
+ + 		[2]	= PWRSTS_OFF_RET,	/* mpu_ram */
+ + 	},
+ + 	.pwrsts_mem_on		= {
+ + 		[0]	= PWRSTS_ON,		/* mpu_l1 */
+ + 		[1]	= PWRSTS_ON,		/* mpu_l2 */
+ + 		[2]	= PWRSTS_ON,		/* mpu_ram */
+ + 	},
+ + };
+ + 
+ + static struct powerdomain cefuse_33xx_pwrdm = {
+ + 	.name			= "cefuse_pwrdm",
+ + 	.voltdm			= { .name = "core" },
+ + 	.prcm_partition		= AM33XX_PRM_PARTITION,
+ + 	.prcm_offs		= AM33XX_PRM_CEFUSE_MOD,
+ + 	.pwrsts			= PWRSTS_OFF_ON,
+ + 	.pwrstctrl_offs		= AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET,
+ + 	.pwrstst_offs		= AM33XX_PM_CEFUSE_PWRSTST_OFFSET,
+ + };
+ + 
+ + static struct powerdomain *powerdomains_am33xx[] __initdata = {
+ + 	&gfx_33xx_pwrdm,
+ + 	&rtc_33xx_pwrdm,
+ + 	&wkup_33xx_pwrdm,
+ + 	&per_33xx_pwrdm,
+ + 	&mpu_33xx_pwrdm,
+ + 	&cefuse_33xx_pwrdm,
+ + 	NULL,
+ + };
+ + 
+ + void __init am33xx_powerdomains_init(void)
+ + {
+ + 	pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
+ + 	pwrdm_register_pwrdms(powerdomains_am33xx);
+ + 	pwrdm_complete_init();
+ + }
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/powerdomains3xxx_data.c linux-3.2.1/arch/arm/mach-ckb_3352/powerdomains3xxx_data.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/powerdomains3xxx_data.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/powerdomains3xxx_data.c	2014-11-25 13:19:15.047478510 +0900
+ ***************
+ *** 0 ****
+ --- 1,293 ----
+ + /*
+ +  * OMAP3 powerdomain definitions
+ +  *
+ +  * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
+ +  * Copyright (C) 2007-2011 Nokia Corporation
+ +  *
+ +  * Paul Walmsley, Jouni Högander
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #include <linux/kernel.h>
+ + #include <linux/init.h>
+ + 
+ + #include <plat/cpu.h>
+ + 
+ + #include "powerdomain.h"
+ + #include "powerdomains2xxx_3xxx_data.h"
+ + 
+ + #include "prcm-common.h"
+ + #include "prm2xxx_3xxx.h"
+ + #include "prm-regbits-34xx.h"
+ + #include "cm2xxx_3xxx.h"
+ + #include "cm-regbits-34xx.h"
+ + 
+ + /*
+ +  * 34XX-specific powerdomains, dependencies
+ +  */
+ + 
+ + /*
+ +  * Powerdomains
+ +  */
+ + 
+ + static struct powerdomain iva2_pwrdm = {
+ + 	.name		  = "iva2_pwrdm",
+ + 	.prcm_offs	  = OMAP3430_IVA2_MOD,
+ + 	.pwrsts		  = PWRSTS_OFF_RET_ON,
+ + 	.pwrsts_logic_ret = PWRSTS_OFF_RET,
+ + 	.banks		  = 4,
+ + 	.pwrsts_mem_ret	  = {
+ + 		[0] = PWRSTS_OFF_RET,
+ + 		[1] = PWRSTS_OFF_RET,
+ + 		[2] = PWRSTS_OFF_RET,
+ + 		[3] = PWRSTS_OFF_RET,
+ + 	},
+ + 	.pwrsts_mem_on	  = {
+ + 		[0] = PWRSTS_ON,
+ + 		[1] = PWRSTS_ON,
+ + 		[2] = PWRSTS_OFF_ON,
+ + 		[3] = PWRSTS_ON,
+ + 	},
+ + 	.voltdm           = { .name = "mpu_iva" },
+ + };
+ + 
+ + static struct powerdomain mpu_3xxx_pwrdm = {
+ + 	.name		  = "mpu_pwrdm",
+ + 	.prcm_offs	  = MPU_MOD,
+ + 	.pwrsts		  = PWRSTS_OFF_RET_ON,
+ + 	.pwrsts_logic_ret = PWRSTS_OFF_RET,
+ + 	.flags		  = PWRDM_HAS_MPU_QUIRK,
+ + 	.banks		  = 1,
+ + 	.pwrsts_mem_ret	  = {
+ + 		[0] = PWRSTS_OFF_RET,
+ + 	},
+ + 	.pwrsts_mem_on	  = {
+ + 		[0] = PWRSTS_OFF_ON,
+ + 	},
+ + 	.voltdm           = { .name = "mpu_iva" },
+ + };
+ + 
+ + /*
+ +  * The USBTLL Save-and-Restore mechanism is broken on
+ +  * 3430s up to ES3.0 and 3630ES1.0. Hence this feature
+ +  * needs to be disabled on these chips.
+ +  * Refer: 3430 errata ID i459 and 3630 errata ID i579
+ +  *
+ +  * Note: setting the SAR flag could help for errata ID i478
+ +  *  which applies to 3430 <= ES3.1, but since the SAR feature
+ +  *  is broken, do not use it.
+ +  */
+ + static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
+ + 	.name		  = "core_pwrdm",
+ + 	.prcm_offs	  = CORE_MOD,
+ + 	.pwrsts		  = PWRSTS_OFF_RET_ON,
+ + 	.pwrsts_logic_ret = PWRSTS_OFF_RET,
+ + 	.banks		  = 2,
+ + 	.pwrsts_mem_ret	  = {
+ + 		[0] = PWRSTS_OFF_RET,	 /* MEM1RETSTATE */
+ + 		[1] = PWRSTS_OFF_RET,	 /* MEM2RETSTATE */
+ + 	},
+ + 	.pwrsts_mem_on	  = {
+ + 		[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
+ + 		[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
+ + 	},
+ + 	.voltdm           = { .name = "core" },
+ + };
+ + 
+ + static struct powerdomain core_3xxx_es3_1_pwrdm = {
+ + 	.name		  = "core_pwrdm",
+ + 	.prcm_offs	  = CORE_MOD,
+ + 	.pwrsts		  = PWRSTS_OFF_RET_ON,
+ + 	.pwrsts_logic_ret = PWRSTS_OFF_RET,
+ + 	/*
+ + 	 * Setting the SAR flag for errata ID i478 which applies
+ + 	 *  to 3430 <= ES3.1
+ + 	 */
+ + 	.flags		  = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
+ + 	.banks		  = 2,
+ + 	.pwrsts_mem_ret	  = {
+ + 		[0] = PWRSTS_OFF_RET,	 /* MEM1RETSTATE */
+ + 		[1] = PWRSTS_OFF_RET,	 /* MEM2RETSTATE */
+ + 	},
+ + 	.pwrsts_mem_on	  = {
+ + 		[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
+ + 		[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
+ + 	},
+ + 	.voltdm           = { .name = "core" },
+ + };
+ + 
+ + static struct powerdomain dss_pwrdm = {
+ + 	.name		  = "dss_pwrdm",
+ + 	.prcm_offs	  = OMAP3430_DSS_MOD,
+ + 	.pwrsts		  = PWRSTS_OFF_RET_ON,
+ + 	.pwrsts_logic_ret = PWRSTS_RET,
+ + 	.banks		  = 1,
+ + 	.pwrsts_mem_ret	  = {
+ + 		[0] = PWRSTS_RET, /* MEMRETSTATE */
+ + 	},
+ + 	.pwrsts_mem_on	  = {
+ + 		[0] = PWRSTS_ON,  /* MEMONSTATE */
+ + 	},
+ + 	.voltdm           = { .name = "core" },
+ + };
+ + 
+ + /*
+ +  * Although the 34XX TRM Rev K Table 4-371 notes that retention is a
+ +  * possible SGX powerstate, the SGX device itself does not support
+ +  * retention.
+ +  */
+ + static struct powerdomain sgx_pwrdm = {
+ + 	.name		  = "sgx_pwrdm",
+ + 	.prcm_offs	  = OMAP3430ES2_SGX_MOD,
+ + 	/* XXX This is accurate for 3430 SGX, but what about GFX? */
+ + 	.pwrsts		  = PWRSTS_OFF_ON,
+ + 	.pwrsts_logic_ret = PWRSTS_RET,
+ + 	.banks		  = 1,
+ + 	.pwrsts_mem_ret	  = {
+ + 		[0] = PWRSTS_RET, /* MEMRETSTATE */
+ + 	},
+ + 	.pwrsts_mem_on	  = {
+ + 		[0] = PWRSTS_ON,  /* MEMONSTATE */
+ + 	},
+ + 	.voltdm           = { .name = "core" },
+ + };
+ + 
+ + static struct powerdomain cam_pwrdm = {
+ + 	.name		  = "cam_pwrdm",
+ + 	.prcm_offs	  = OMAP3430_CAM_MOD,
+ + 	.pwrsts		  = PWRSTS_OFF_RET_ON,
+ + 	.pwrsts_logic_ret = PWRSTS_RET,
+ + 	.banks		  = 1,
+ + 	.pwrsts_mem_ret	  = {
+ + 		[0] = PWRSTS_RET, /* MEMRETSTATE */
+ + 	},
+ + 	.pwrsts_mem_on	  = {
+ + 		[0] = PWRSTS_ON,  /* MEMONSTATE */
+ + 	},
+ + 	.voltdm           = { .name = "core" },
+ + };
+ + 
+ + static struct powerdomain per_pwrdm = {
+ + 	.name		  = "per_pwrdm",
+ + 	.prcm_offs	  = OMAP3430_PER_MOD,
+ + 	.pwrsts		  = PWRSTS_OFF_RET_ON,
+ + 	.pwrsts_logic_ret = PWRSTS_OFF_RET,
+ + 	.banks		  = 1,
+ + 	.pwrsts_mem_ret	  = {
+ + 		[0] = PWRSTS_RET, /* MEMRETSTATE */
+ + 	},
+ + 	.pwrsts_mem_on	  = {
+ + 		[0] = PWRSTS_ON,  /* MEMONSTATE */
+ + 	},
+ + 	.voltdm           = { .name = "core" },
+ + };
+ + 
+ + static struct powerdomain emu_pwrdm = {
+ + 	.name		= "emu_pwrdm",
+ + 	.prcm_offs	= OMAP3430_EMU_MOD,
+ + 	.voltdm           = { .name = "core" },
+ + };
+ + 
+ + static struct powerdomain neon_pwrdm = {
+ + 	.name		  = "neon_pwrdm",
+ + 	.prcm_offs	  = OMAP3430_NEON_MOD,
+ + 	.pwrsts		  = PWRSTS_OFF_RET_ON,
+ + 	.pwrsts_logic_ret = PWRSTS_RET,
+ + 	.voltdm           = { .name = "mpu_iva" },
+ + };
+ + 
+ + static struct powerdomain usbhost_pwrdm = {
+ + 	.name		  = "usbhost_pwrdm",
+ + 	.prcm_offs	  = OMAP3430ES2_USBHOST_MOD,
+ + 	.pwrsts		  = PWRSTS_OFF_RET_ON,
+ + 	.pwrsts_logic_ret = PWRSTS_RET,
+ + 	/*
+ + 	 * REVISIT: Enabling usb host save and restore mechanism seems to
+ + 	 * leave the usb host domain permanently in ACTIVE mode after
+ + 	 * changing the usb host power domain state from OFF to active once.
+ + 	 * Disabling for now.
+ + 	 */
+ + 	/*.flags	  = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */
+ + 	.banks		  = 1,
+ + 	.pwrsts_mem_ret	  = {
+ + 		[0] = PWRSTS_RET, /* MEMRETSTATE */
+ + 	},
+ + 	.pwrsts_mem_on	  = {
+ + 		[0] = PWRSTS_ON,  /* MEMONSTATE */
+ + 	},
+ + 	.voltdm           = { .name = "core" },
+ + };
+ + 
+ + static struct powerdomain dpll1_pwrdm = {
+ + 	.name		= "dpll1_pwrdm",
+ + 	.prcm_offs	= MPU_MOD,
+ + 	.voltdm           = { .name = "mpu_iva" },
+ + };
+ + 
+ + static struct powerdomain dpll2_pwrdm = {
+ + 	.name		= "dpll2_pwrdm",
+ + 	.prcm_offs	= OMAP3430_IVA2_MOD,
+ + 	.voltdm           = { .name = "mpu_iva" },
+ + };
+ + 
+ + static struct powerdomain dpll3_pwrdm = {
+ + 	.name		= "dpll3_pwrdm",
+ + 	.prcm_offs	= PLL_MOD,
+ + 	.voltdm           = { .name = "core" },
+ + };
+ + 
+ + static struct powerdomain dpll4_pwrdm = {
+ + 	.name		= "dpll4_pwrdm",
+ + 	.prcm_offs	= PLL_MOD,
+ + 	.voltdm           = { .name = "core" },
+ + };
+ + 
+ + static struct powerdomain dpll5_pwrdm = {
+ + 	.name		= "dpll5_pwrdm",
+ + 	.prcm_offs	= PLL_MOD,
+ + 	.voltdm           = { .name = "core" },
+ + };
+ + 
+ + /* As powerdomains are added or removed above, this list must also be changed */
+ + static struct powerdomain *powerdomains_omap3430_common[] __initdata = {
+ + 	&wkup_omap2_pwrdm,
+ + 	&iva2_pwrdm,
+ + 	&mpu_3xxx_pwrdm,
+ + 	&neon_pwrdm,
+ + 	&cam_pwrdm,
+ + 	&dss_pwrdm,
+ + 	&per_pwrdm,
+ + 	&emu_pwrdm,
+ + 	&dpll1_pwrdm,
+ + 	&dpll2_pwrdm,
+ + 	&dpll3_pwrdm,
+ + 	&dpll4_pwrdm,
+ + 	NULL
+ + };
+ + 
+ + static struct powerdomain *powerdomains_omap3430es1[] __initdata = {
+ + 	&gfx_omap2_pwrdm,
+ + 	&core_3xxx_pre_es3_1_pwrdm,
+ + 	NULL
+ + };
+ + 
+ + /* also includes 3630ES1.0 */
+ + static struct powerdomain *powerdomains_omap3430es2_es3_0[] __initdata = {
+ + 	&core_3xxx_pre_es3_1_pwrdm,
+ + 	&sgx_pwrdm,
+ + 	&usbhost_pwrdm,
+ + 	&dpll5_pwrdm,
+ + 	NULL
+ + };
+ + 
+ + /* also includes 3630ES1.1+ */
+ + static struct powerdomain *powerdomains_omap3430es3_1plus[] __initdata = {
+ + 	&core_3xxx_es3_1_pwrdm,
+ + 	&sgx_pwrdm,
+ + 	&usbhost_pwrdm,
+ + 	&dpll5_pwrdm,
+ + 	NULL
+ + };
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/prcm44xx.h linux-3.2.1/arch/arm/mach-ckb_3352/prcm44xx.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/prcm44xx.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/prcm44xx.h	2014-11-25 13:19:15.047478510 +0900
+ ***************
+ *** 0 ****
+ --- 1,44 ----
+ + /*
+ +  * OMAP4 PRCM definitions
+ +  *
+ +  * Copyright (C) 2010 Texas Instruments, Inc.
+ +  * Copyright (C) 2010 Nokia Corporation
+ +  *
+ +  * Paul Walmsley
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  *
+ +  * This file contains macros and functions that are common to all of
+ +  * the PRM/CM/PRCM blocks on the OMAP4 devices: PRM, CM1, CM2,
+ +  * PRCM_MPU, SCRM
+ +  */
+ + 
+ + #ifndef __ARCH_ARM_MACH_OMAP2_PRCM44XX_H
+ + #define __ARCH_ARM_MACH_OMAP2_PRCM44XX_H
+ + 
+ + /*
+ +  * OMAP4 PRCM partition IDs
+ +  *
+ +  * The numbers and order are arbitrary, but 0 is reserved for the
+ +  * 'invalid' partition in case someone forgets to add a
+ +  * .prcm_partition field.
+ +  */
+ + #define OMAP4430_INVALID_PRCM_PARTITION		0
+ + #define OMAP4430_PRM_PARTITION			1
+ + #define OMAP4430_CM1_PARTITION			2
+ + #define OMAP4430_CM2_PARTITION			3
+ + #define OMAP4430_SCRM_PARTITION			4
+ + #define OMAP4430_PRCM_MPU_PARTITION		5
+ + /* AM33XX PRCM is closer to OMAP4, so try to reuse all API's */
+ + #define AM33XX_PRM_PARTITION			1
+ + 
+ + /*
+ +  * OMAP4_MAX_PRCM_PARTITIONS: set to the highest value of the PRCM partition
+ +  * IDs, plus one
+ +  */
+ + #define OMAP4_MAX_PRCM_PARTITIONS		6
+ + 
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/prcm.c linux-3.2.1/arch/arm/mach-ckb_3352/prcm.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/prcm.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/prcm.c	2014-11-25 13:19:15.047478510 +0900
+ ***************
+ *** 0 ****
+ --- 1,142 ----
+ + /*
+ +  * linux/arch/arm/mach-omap2/prcm.c
+ +  *
+ +  * OMAP 24xx Power Reset and Clock Management (PRCM) functions
+ +  *
+ +  * Copyright (C) 2005 Nokia Corporation
+ +  *
+ +  * Written by Tony Lindgren <tony.lindgren@nokia.com>
+ +  *
+ +  * Copyright (C) 2007 Texas Instruments, Inc.
+ +  * Rajendra Nayak <rnayak@ti.com>
+ +  *
+ +  * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
+ +  * Upgraded with OMAP4 support by Abhijit Pagare <abhijitpagare@ti.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #include <linux/kernel.h>
+ + #include <linux/init.h>
+ + #include <linux/clk.h>
+ + #include <linux/io.h>
+ + #include <linux/delay.h>
+ + #include <linux/export.h>
+ + 
+ + #include <mach/system.h>
+ + #include "common.h"
+ + #include <plat/prcm.h>
+ + #include <plat/irqs.h>
+ + 
+ + #include "clock.h"
+ + //#include "clock2xxx.h"
+ + #include "cm2xxx_3xxx.h"
+ + #include "prm2xxx_3xxx.h"
+ + //#include "prm44xx.h"
+ + #include "prm33xx.h"
+ + #include "prminst44xx.h"
+ + #include "prm-regbits-24xx.h"
+ + #include "prm-regbits-44xx.h"
+ + #include "control.h"
+ + 
+ + void __iomem *prm_base;
+ + void __iomem *cm_base;
+ + void __iomem *cm2_base;
+ + 
+ + #define MAX_MODULE_ENABLE_WAIT		100000
+ + 
+ + 
+ + /* Resets clock rates and reboots the system. Only called from system.h */
+ + static void omap_prcm_arch_reset(char mode, const char *cmd)
+ + {
+ + 	s16 prcm_offs = 0;
+ + 
+ + 	prcm_offs = AM33XX_PRM_DEVICE_MOD;
+ + 	omap2_prm_set_mod_reg_bits(OMAP4430_RST_GLOBAL_COLD_SW_MASK,
+ + 				prcm_offs, AM33XX_PRM_RSTCTRL_OFFSET);
+ + 	
+ + 	/*
+ + 	 * As per Errata i520, in some cases, user will not be able to
+ + 	 * access DDR memory after warm-reset.
+ + 	 * This situation occurs while the warm-reset happens during a read
+ + 	 * access to DDR memory. In that particular condition, DDR memory
+ + 	 * does not respond to a corrupted read command due to the warm
+ + 	 * reset occurrence but SDRC is waiting for read completion.
+ + 	 * SDRC is not sensitive to the warm reset, but the interconnect is
+ + 	 * reset on the fly, thus causing a misalignment between SDRC logic,
+ + 	 * interconnect logic and DDR memory state.
+ + 	 * WORKAROUND:
+ + 	 * Steps to perform before a Warm reset is trigged:
+ + 	 * 1. enable self-refresh on idle request
+ + 	 * 2. put SDRC in idle
+ + 	 * 3. wait until SDRC goes to idle
+ + 	 * 4. generate SW reset (Global SW reset)
+ + 	 *
+ + 	 * Steps to be performed after warm reset occurs (in bootloader):
+ + 	 * if HW warm reset is the source, apply below steps before any
+ + 	 * accesses to SDRAM:
+ + 	 * 1. Reset SMS and SDRC and wait till reset is complete
+ + 	 * 2. Re-initialize SMS, SDRC and memory
+ + 	 *
+ + 	 * NOTE: Above work around is required only if arch reset is implemented
+ + 	 * using Global SW reset(GLOBAL_SW_RST). DPLL3 reset does not need
+ + 	 * the WA since it resets SDRC as well as part of cold reset.
+ + 	 */
+ + 
+ + 	/* XXX should be moved to some OMAP2/3 specific code */
+ + 	omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
+ + 				   OMAP2_RM_RSTCTRL);
+ + 	omap2_prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */
+ + }
+ + 
+ + void (*arch_reset)(char, const char *) = omap_prcm_arch_reset;
+ + 
+ + /**
+ +  * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
+ +  * @reg: physical address of module IDLEST register
+ +  * @mask: value to mask against to determine if the module is active
+ +  * @idlest: idle state indicator (0 or 1) for the clock
+ +  * @name: name of the clock (for printk)
+ +  *
+ +  * Returns 1 if the module indicated readiness in time, or 0 if it
+ +  * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
+ +  *
+ +  * XXX This function is deprecated.  It should be removed once the
+ +  * hwmod conversion is complete.
+ +  */
+ + int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
+ + 				const char *name)
+ + {
+ + 	int i = 0;
+ + 	int ena = 0;
+ + 
+ + 	if (idlest)
+ + 		ena = 0;
+ + 	else
+ + 		ena = mask;
+ + 
+ + 	/* Wait for lock */
+ + 	omap_test_timeout(((__raw_readl(reg) & mask) == ena),
+ + 			  MAX_MODULE_ENABLE_WAIT, i);
+ + 
+ + 	if (i < MAX_MODULE_ENABLE_WAIT)
+ + 		pr_debug("cm: Module associated with clock %s ready after %d "
+ + 			 "loops\n", name, i);
+ + 	else
+ + 		pr_err("cm: Module associated with clock %s didn't enable in "
+ + 		       "%d tries\n", name, MAX_MODULE_ENABLE_WAIT);
+ + 
+ + 	return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
+ + };
+ + 
+ + void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
+ + {
+ + 	if (omap2_globals->prm)
+ + 		prm_base = omap2_globals->prm;
+ + 	if (omap2_globals->cm)
+ + 		cm_base = omap2_globals->cm;
+ + 	if (omap2_globals->cm2)
+ + 		cm2_base = omap2_globals->cm2;
+ + }
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/prcm-common.h linux-3.2.1/arch/arm/mach-ckb_3352/prcm-common.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/prcm-common.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/prcm-common.h	2014-11-25 13:19:15.050993430 +0900
+ ***************
+ *** 0 ****
+ --- 1,489 ----
+ + #ifndef __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
+ + #define __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
+ + 
+ + /*
+ +  * OMAP2/3 PRCM base and module definitions
+ +  *
+ +  * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc.
+ +  * Copyright (C) 2007-2009 Nokia Corporation
+ +  *
+ +  * Written by Paul Walmsley
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + /* Module offsets from both CM_BASE & PRM_BASE */
+ + 
+ + /*
+ +  * Offsets that are the same on 24xx and 34xx
+ +  *
+ +  * Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is
+ +  * CCR_MOD on 3430; and GFX_MOD only exists < 3430ES2.
+ +  */
+ + #define OCP_MOD						0x000
+ + #define MPU_MOD						0x100
+ + #define CORE_MOD					0x200
+ + #define GFX_MOD						0x300
+ + #define WKUP_MOD					0x400
+ + #define PLL_MOD						0x500
+ + 
+ + 
+ + /* Chip-specific module offsets */
+ + #define OMAP24XX_GR_MOD					OCP_MOD
+ + #define OMAP24XX_DSP_MOD				0x800
+ + 
+ + #define OMAP2430_MDM_MOD				0xc00
+ + 
+ + /* IVA2 module is < base on 3430 */
+ + #define OMAP3430_IVA2_MOD				-0x800
+ + #define OMAP3430ES2_SGX_MOD				GFX_MOD
+ + #define OMAP3430_CCR_MOD				PLL_MOD
+ + #define OMAP3430_DSS_MOD				0x600
+ + #define OMAP3430_CAM_MOD				0x700
+ + #define OMAP3430_PER_MOD				0x800
+ + #define OMAP3430_EMU_MOD				0x900
+ + #define OMAP3430_GR_MOD					0xa00
+ + #define OMAP3430_NEON_MOD				0xb00
+ + #define OMAP3430ES2_USBHOST_MOD				0xc00
+ + 
+ + /* 24XX register bits shared between CM & PRM registers */
+ + 
+ + /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
+ + #define OMAP2420_EN_MMC_SHIFT				26
+ + #define OMAP2420_EN_MMC_MASK				(1 << 26)
+ + #define OMAP24XX_EN_UART2_SHIFT				22
+ + #define OMAP24XX_EN_UART2_MASK				(1 << 22)
+ + #define OMAP24XX_EN_UART1_SHIFT				21
+ + #define OMAP24XX_EN_UART1_MASK				(1 << 21)
+ + #define OMAP24XX_EN_MCSPI2_SHIFT			18
+ + #define OMAP24XX_EN_MCSPI2_MASK				(1 << 18)
+ + #define OMAP24XX_EN_MCSPI1_SHIFT			17
+ + #define OMAP24XX_EN_MCSPI1_MASK				(1 << 17)
+ + #define OMAP24XX_EN_MCBSP2_SHIFT			16
+ + #define OMAP24XX_EN_MCBSP2_MASK				(1 << 16)
+ + #define OMAP24XX_EN_MCBSP1_SHIFT			15
+ + #define OMAP24XX_EN_MCBSP1_MASK				(1 << 15)
+ + #define OMAP24XX_EN_GPT12_SHIFT				14
+ + #define OMAP24XX_EN_GPT12_MASK				(1 << 14)
+ + #define OMAP24XX_EN_GPT11_SHIFT				13
+ + #define OMAP24XX_EN_GPT11_MASK				(1 << 13)
+ + #define OMAP24XX_EN_GPT10_SHIFT				12
+ + #define OMAP24XX_EN_GPT10_MASK				(1 << 12)
+ + #define OMAP24XX_EN_GPT9_SHIFT				11
+ + #define OMAP24XX_EN_GPT9_MASK				(1 << 11)
+ + #define OMAP24XX_EN_GPT8_SHIFT				10
+ + #define OMAP24XX_EN_GPT8_MASK				(1 << 10)
+ + #define OMAP24XX_EN_GPT7_SHIFT				9
+ + #define OMAP24XX_EN_GPT7_MASK				(1 << 9)
+ + #define OMAP24XX_EN_GPT6_SHIFT				8
+ + #define OMAP24XX_EN_GPT6_MASK				(1 << 8)
+ + #define OMAP24XX_EN_GPT5_SHIFT				7
+ + #define OMAP24XX_EN_GPT5_MASK				(1 << 7)
+ + #define OMAP24XX_EN_GPT4_SHIFT				6
+ + #define OMAP24XX_EN_GPT4_MASK				(1 << 6)
+ + #define OMAP24XX_EN_GPT3_SHIFT				5
+ + #define OMAP24XX_EN_GPT3_MASK				(1 << 5)
+ + #define OMAP24XX_EN_GPT2_SHIFT				4
+ + #define OMAP24XX_EN_GPT2_MASK				(1 << 4)
+ + #define OMAP2420_EN_VLYNQ_SHIFT				3
+ + #define OMAP2420_EN_VLYNQ_MASK				(1 << 3)
+ + 
+ + /* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
+ + #define OMAP2430_EN_GPIO5_SHIFT				10
+ + #define OMAP2430_EN_GPIO5_MASK				(1 << 10)
+ + #define OMAP2430_EN_MCSPI3_SHIFT			9
+ + #define OMAP2430_EN_MCSPI3_MASK				(1 << 9)
+ + #define OMAP2430_EN_MMCHS2_SHIFT			8
+ + #define OMAP2430_EN_MMCHS2_MASK				(1 << 8)
+ + #define OMAP2430_EN_MMCHS1_SHIFT			7
+ + #define OMAP2430_EN_MMCHS1_MASK				(1 << 7)
+ + #define OMAP24XX_EN_UART3_SHIFT				2
+ + #define OMAP24XX_EN_UART3_MASK				(1 << 2)
+ + #define OMAP24XX_EN_USB_SHIFT				0
+ + #define OMAP24XX_EN_USB_MASK				(1 << 0)
+ + 
+ + /* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
+ + #define OMAP2430_EN_MDM_INTC_SHIFT			11
+ + #define OMAP2430_EN_MDM_INTC_MASK			(1 << 11)
+ + #define OMAP2430_EN_USBHS_SHIFT				6
+ + #define OMAP2430_EN_USBHS_MASK				(1 << 6)
+ + 
+ + /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
+ + #define OMAP2420_ST_MMC_SHIFT				26
+ + #define OMAP2420_ST_MMC_MASK				(1 << 26)
+ + #define OMAP24XX_ST_UART2_SHIFT				22
+ + #define OMAP24XX_ST_UART2_MASK				(1 << 22)
+ + #define OMAP24XX_ST_UART1_SHIFT				21
+ + #define OMAP24XX_ST_UART1_MASK				(1 << 21)
+ + #define OMAP24XX_ST_MCSPI2_SHIFT			18
+ + #define OMAP24XX_ST_MCSPI2_MASK				(1 << 18)
+ + #define OMAP24XX_ST_MCSPI1_SHIFT			17
+ + #define OMAP24XX_ST_MCSPI1_MASK				(1 << 17)
+ + #define OMAP24XX_ST_MCBSP2_SHIFT			16
+ + #define OMAP24XX_ST_MCBSP2_MASK				(1 << 16)
+ + #define OMAP24XX_ST_MCBSP1_SHIFT			15
+ + #define OMAP24XX_ST_MCBSP1_MASK				(1 << 15)
+ + #define OMAP24XX_ST_GPT12_SHIFT				14
+ + #define OMAP24XX_ST_GPT12_MASK				(1 << 14)
+ + #define OMAP24XX_ST_GPT11_SHIFT				13
+ + #define OMAP24XX_ST_GPT11_MASK				(1 << 13)
+ + #define OMAP24XX_ST_GPT10_SHIFT				12
+ + #define OMAP24XX_ST_GPT10_MASK				(1 << 12)
+ + #define OMAP24XX_ST_GPT9_SHIFT				11
+ + #define OMAP24XX_ST_GPT9_MASK				(1 << 11)
+ + #define OMAP24XX_ST_GPT8_SHIFT				10
+ + #define OMAP24XX_ST_GPT8_MASK				(1 << 10)
+ + #define OMAP24XX_ST_GPT7_SHIFT				9
+ + #define OMAP24XX_ST_GPT7_MASK				(1 << 9)
+ + #define OMAP24XX_ST_GPT6_SHIFT				8
+ + #define OMAP24XX_ST_GPT6_MASK				(1 << 8)
+ + #define OMAP24XX_ST_GPT5_SHIFT				7
+ + #define OMAP24XX_ST_GPT5_MASK				(1 << 7)
+ + #define OMAP24XX_ST_GPT4_SHIFT				6
+ + #define OMAP24XX_ST_GPT4_MASK				(1 << 6)
+ + #define OMAP24XX_ST_GPT3_SHIFT				5
+ + #define OMAP24XX_ST_GPT3_MASK				(1 << 5)
+ + #define OMAP24XX_ST_GPT2_SHIFT				4
+ + #define OMAP24XX_ST_GPT2_MASK				(1 << 4)
+ + #define OMAP2420_ST_VLYNQ_SHIFT				3
+ + #define OMAP2420_ST_VLYNQ_MASK				(1 << 3)
+ + 
+ + /* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */
+ + #define OMAP2430_ST_MDM_INTC_SHIFT			11
+ + #define OMAP2430_ST_MDM_INTC_MASK			(1 << 11)
+ + #define OMAP2430_ST_GPIO5_SHIFT				10
+ + #define OMAP2430_ST_GPIO5_MASK				(1 << 10)
+ + #define OMAP2430_ST_MCSPI3_SHIFT			9
+ + #define OMAP2430_ST_MCSPI3_MASK				(1 << 9)
+ + #define OMAP2430_ST_MMCHS2_SHIFT			8
+ + #define OMAP2430_ST_MMCHS2_MASK				(1 << 8)
+ + #define OMAP2430_ST_MMCHS1_SHIFT			7
+ + #define OMAP2430_ST_MMCHS1_MASK				(1 << 7)
+ + #define OMAP2430_ST_USBHS_SHIFT				6
+ + #define OMAP2430_ST_USBHS_MASK				(1 << 6)
+ + #define OMAP24XX_ST_UART3_SHIFT				2
+ + #define OMAP24XX_ST_UART3_MASK				(1 << 2)
+ + #define OMAP24XX_ST_USB_SHIFT				0
+ + #define OMAP24XX_ST_USB_MASK				(1 << 0)
+ + 
+ + /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
+ + #define OMAP24XX_EN_GPIOS_SHIFT				2
+ + #define OMAP24XX_EN_GPIOS_MASK				(1 << 2)
+ + #define OMAP24XX_EN_GPT1_SHIFT				0
+ + #define OMAP24XX_EN_GPT1_MASK				(1 << 0)
+ + 
+ + /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
+ + #define OMAP24XX_ST_GPIOS_SHIFT				2
+ + #define OMAP24XX_ST_GPIOS_MASK				(1 << 2)
+ + #define OMAP24XX_ST_GPT1_SHIFT				0
+ + #define OMAP24XX_ST_GPT1_MASK				(1 << 0)
+ + 
+ + /* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
+ + #define OMAP2430_ST_MDM_SHIFT				0
+ + #define OMAP2430_ST_MDM_MASK				(1 << 0)
+ + 
+ + 
+ + /* 3430 register bits shared between CM & PRM registers */
+ + 
+ + /* CM_REVISION, PRM_REVISION shared bits */
+ + #define OMAP3430_REV_SHIFT				0
+ + #define OMAP3430_REV_MASK				(0xff << 0)
+ + 
+ + /* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */
+ + #define OMAP3430_AUTOIDLE_MASK				(1 << 0)
+ + 
+ + /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
+ + #define OMAP3430_EN_MMC3_MASK				(1 << 30)
+ + #define OMAP3430_EN_MMC3_SHIFT				30
+ + #define OMAP3430_EN_MMC2_MASK				(1 << 25)
+ + #define OMAP3430_EN_MMC2_SHIFT				25
+ + #define OMAP3430_EN_MMC1_MASK				(1 << 24)
+ + #define OMAP3430_EN_MMC1_SHIFT				24
+ + #define OMAP3430_EN_UART4_MASK				(1 << 23)
+ + #define OMAP3430_EN_UART4_SHIFT				23
+ + #define OMAP3430_EN_MCSPI4_MASK				(1 << 21)
+ + #define OMAP3430_EN_MCSPI4_SHIFT			21
+ + #define OMAP3430_EN_MCSPI3_MASK				(1 << 20)
+ + #define OMAP3430_EN_MCSPI3_SHIFT			20
+ + #define OMAP3430_EN_MCSPI2_MASK				(1 << 19)
+ + #define OMAP3430_EN_MCSPI2_SHIFT			19
+ + #define OMAP3430_EN_MCSPI1_MASK				(1 << 18)
+ + #define OMAP3430_EN_MCSPI1_SHIFT			18
+ + #define OMAP3430_EN_I2C3_MASK				(1 << 17)
+ + #define OMAP3430_EN_I2C3_SHIFT				17
+ + #define OMAP3430_EN_I2C2_MASK				(1 << 16)
+ + #define OMAP3430_EN_I2C2_SHIFT				16
+ + #define OMAP3430_EN_I2C1_MASK				(1 << 15)
+ + #define OMAP3430_EN_I2C1_SHIFT				15
+ + #define OMAP3430_EN_UART2_MASK				(1 << 14)
+ + #define OMAP3430_EN_UART2_SHIFT				14
+ + #define OMAP3430_EN_UART1_MASK				(1 << 13)
+ + #define OMAP3430_EN_UART1_SHIFT				13
+ + #define OMAP3430_EN_GPT11_MASK				(1 << 12)
+ + #define OMAP3430_EN_GPT11_SHIFT				12
+ + #define OMAP3430_EN_GPT10_MASK				(1 << 11)
+ + #define OMAP3430_EN_GPT10_SHIFT				11
+ + #define OMAP3430_EN_MCBSP5_MASK				(1 << 10)
+ + #define OMAP3430_EN_MCBSP5_SHIFT			10
+ + #define OMAP3430_EN_MCBSP1_MASK				(1 << 9)
+ + #define OMAP3430_EN_MCBSP1_SHIFT			9
+ + #define OMAP3430_EN_FSHOSTUSB_MASK			(1 << 5)
+ + #define OMAP3430_EN_FSHOSTUSB_SHIFT			5
+ + #define OMAP3430_EN_D2D_MASK				(1 << 3)
+ + #define OMAP3430_EN_D2D_SHIFT				3
+ + 
+ + /* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
+ + #define OMAP3430_EN_HSOTGUSB_MASK			(1 << 4)
+ + #define OMAP3430_EN_HSOTGUSB_SHIFT			4
+ + 
+ + /* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */
+ + #define OMAP3430_ST_MMC3_SHIFT				30
+ + #define OMAP3430_ST_MMC3_MASK				(1 << 30)
+ + #define OMAP3430_ST_MMC2_SHIFT				25
+ + #define OMAP3430_ST_MMC2_MASK				(1 << 25)
+ + #define OMAP3430_ST_MMC1_SHIFT				24
+ + #define OMAP3430_ST_MMC1_MASK				(1 << 24)
+ + #define OMAP3430_ST_MCSPI4_SHIFT			21
+ + #define OMAP3430_ST_MCSPI4_MASK				(1 << 21)
+ + #define OMAP3430_ST_MCSPI3_SHIFT			20
+ + #define OMAP3430_ST_MCSPI3_MASK				(1 << 20)
+ + #define OMAP3430_ST_MCSPI2_SHIFT			19
+ + #define OMAP3430_ST_MCSPI2_MASK				(1 << 19)
+ + #define OMAP3430_ST_MCSPI1_SHIFT			18
+ + #define OMAP3430_ST_MCSPI1_MASK				(1 << 18)
+ + #define OMAP3430_ST_I2C3_SHIFT				17
+ + #define OMAP3430_ST_I2C3_MASK				(1 << 17)
+ + #define OMAP3430_ST_I2C2_SHIFT				16
+ + #define OMAP3430_ST_I2C2_MASK				(1 << 16)
+ + #define OMAP3430_ST_I2C1_SHIFT				15
+ + #define OMAP3430_ST_I2C1_MASK				(1 << 15)
+ + #define OMAP3430_ST_UART2_SHIFT				14
+ + #define OMAP3430_ST_UART2_MASK				(1 << 14)
+ + #define OMAP3430_ST_UART1_SHIFT				13
+ + #define OMAP3430_ST_UART1_MASK				(1 << 13)
+ + #define OMAP3430_ST_GPT11_SHIFT				12
+ + #define OMAP3430_ST_GPT11_MASK				(1 << 12)
+ + #define OMAP3430_ST_GPT10_SHIFT				11
+ + #define OMAP3430_ST_GPT10_MASK				(1 << 11)
+ + #define OMAP3430_ST_MCBSP5_SHIFT			10
+ + #define OMAP3430_ST_MCBSP5_MASK				(1 << 10)
+ + #define OMAP3430_ST_MCBSP1_SHIFT			9
+ + #define OMAP3430_ST_MCBSP1_MASK				(1 << 9)
+ + #define OMAP3430ES1_ST_FSHOSTUSB_SHIFT			5
+ + #define OMAP3430ES1_ST_FSHOSTUSB_MASK			(1 << 5)
+ + #define OMAP3430ES1_ST_HSOTGUSB_SHIFT			4
+ + #define OMAP3430ES1_ST_HSOTGUSB_MASK			(1 << 4)
+ + #define OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT		5
+ + #define OMAP3430ES2_ST_HSOTGUSB_IDLE_MASK		(1 << 5)
+ + #define OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT		4
+ + #define OMAP3430ES2_ST_HSOTGUSB_STDBY_MASK		(1 << 4)
+ + #define OMAP3430_ST_D2D_SHIFT				3
+ + #define OMAP3430_ST_D2D_MASK				(1 << 3)
+ + 
+ + /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
+ + #define OMAP3430_EN_GPIO1_MASK				(1 << 3)
+ + #define OMAP3430_EN_GPIO1_SHIFT				3
+ + #define OMAP3430_EN_GPT12_MASK				(1 << 1)
+ + #define OMAP3430_EN_GPT12_SHIFT				1
+ + #define OMAP3430_EN_GPT1_MASK				(1 << 0)
+ + #define OMAP3430_EN_GPT1_SHIFT				0
+ + 
+ + /* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */
+ + #define OMAP3430_EN_SR2_MASK				(1 << 7)
+ + #define OMAP3430_EN_SR2_SHIFT				7
+ + #define OMAP3430_EN_SR1_MASK				(1 << 6)
+ + #define OMAP3430_EN_SR1_SHIFT				6
+ + 
+ + /* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
+ + #define OMAP3430_EN_GPT12_MASK				(1 << 1)
+ + #define OMAP3430_EN_GPT12_SHIFT				1
+ + 
+ + /* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */
+ + #define OMAP3430_ST_SR2_SHIFT				7
+ + #define OMAP3430_ST_SR2_MASK				(1 << 7)
+ + #define OMAP3430_ST_SR1_SHIFT				6
+ + #define OMAP3430_ST_SR1_MASK				(1 << 6)
+ + #define OMAP3430_ST_GPIO1_SHIFT				3
+ + #define OMAP3430_ST_GPIO1_MASK				(1 << 3)
+ + #define OMAP3430_ST_GPT12_SHIFT				1
+ + #define OMAP3430_ST_GPT12_MASK				(1 << 1)
+ + #define OMAP3430_ST_GPT1_SHIFT				0
+ + #define OMAP3430_ST_GPT1_MASK				(1 << 0)
+ + 
+ + /*
+ +  * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM,
+ +  * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX,
+ +  * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits
+ +  */
+ + #define OMAP3430_EN_MPU_MASK				(1 << 1)
+ + #define OMAP3430_EN_MPU_SHIFT				1
+ + 
+ + /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */
+ + 
+ + #define OMAP3630_EN_UART4_MASK				(1 << 18)
+ + #define OMAP3630_EN_UART4_SHIFT				18
+ + #define OMAP3430_EN_GPIO6_MASK				(1 << 17)
+ + #define OMAP3430_EN_GPIO6_SHIFT				17
+ + #define OMAP3430_EN_GPIO5_MASK				(1 << 16)
+ + #define OMAP3430_EN_GPIO5_SHIFT				16
+ + #define OMAP3430_EN_GPIO4_MASK				(1 << 15)
+ + #define OMAP3430_EN_GPIO4_SHIFT				15
+ + #define OMAP3430_EN_GPIO3_MASK				(1 << 14)
+ + #define OMAP3430_EN_GPIO3_SHIFT				14
+ + #define OMAP3430_EN_GPIO2_MASK				(1 << 13)
+ + #define OMAP3430_EN_GPIO2_SHIFT				13
+ + #define OMAP3430_EN_UART3_MASK				(1 << 11)
+ + #define OMAP3430_EN_UART3_SHIFT				11
+ + #define OMAP3430_EN_GPT9_MASK				(1 << 10)
+ + #define OMAP3430_EN_GPT9_SHIFT				10
+ + #define OMAP3430_EN_GPT8_MASK				(1 << 9)
+ + #define OMAP3430_EN_GPT8_SHIFT				9
+ + #define OMAP3430_EN_GPT7_MASK				(1 << 8)
+ + #define OMAP3430_EN_GPT7_SHIFT				8
+ + #define OMAP3430_EN_GPT6_MASK				(1 << 7)
+ + #define OMAP3430_EN_GPT6_SHIFT				7
+ + #define OMAP3430_EN_GPT5_MASK				(1 << 6)
+ + #define OMAP3430_EN_GPT5_SHIFT				6
+ + #define OMAP3430_EN_GPT4_MASK				(1 << 5)
+ + #define OMAP3430_EN_GPT4_SHIFT				5
+ + #define OMAP3430_EN_GPT3_MASK				(1 << 4)
+ + #define OMAP3430_EN_GPT3_SHIFT				4
+ + #define OMAP3430_EN_GPT2_MASK				(1 << 3)
+ + #define OMAP3430_EN_GPT2_SHIFT				3
+ + 
+ + /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */
+ + /* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits
+ +  * be ST_* bits instead? */
+ + #define OMAP3430_EN_MCBSP4_MASK				(1 << 2)
+ + #define OMAP3430_EN_MCBSP4_SHIFT			2
+ + #define OMAP3430_EN_MCBSP3_MASK				(1 << 1)
+ + #define OMAP3430_EN_MCBSP3_SHIFT			1
+ + #define OMAP3430_EN_MCBSP2_MASK				(1 << 0)
+ + #define OMAP3430_EN_MCBSP2_SHIFT			0
+ + 
+ + /* CM_IDLEST_PER, PM_WKST_PER shared bits */
+ + #define OMAP3630_ST_UART4_SHIFT				18
+ + #define OMAP3630_ST_UART4_MASK				(1 << 18)
+ + #define OMAP3430_ST_GPIO6_SHIFT				17
+ + #define OMAP3430_ST_GPIO6_MASK				(1 << 17)
+ + #define OMAP3430_ST_GPIO5_SHIFT				16
+ + #define OMAP3430_ST_GPIO5_MASK				(1 << 16)
+ + #define OMAP3430_ST_GPIO4_SHIFT				15
+ + #define OMAP3430_ST_GPIO4_MASK				(1 << 15)
+ + #define OMAP3430_ST_GPIO3_SHIFT				14
+ + #define OMAP3430_ST_GPIO3_MASK				(1 << 14)
+ + #define OMAP3430_ST_GPIO2_SHIFT				13
+ + #define OMAP3430_ST_GPIO2_MASK				(1 << 13)
+ + #define OMAP3430_ST_UART3_SHIFT				11
+ + #define OMAP3430_ST_UART3_MASK				(1 << 11)
+ + #define OMAP3430_ST_GPT9_SHIFT				10
+ + #define OMAP3430_ST_GPT9_MASK				(1 << 10)
+ + #define OMAP3430_ST_GPT8_SHIFT				9
+ + #define OMAP3430_ST_GPT8_MASK				(1 << 9)
+ + #define OMAP3430_ST_GPT7_SHIFT				8
+ + #define OMAP3430_ST_GPT7_MASK				(1 << 8)
+ + #define OMAP3430_ST_GPT6_SHIFT				7
+ + #define OMAP3430_ST_GPT6_MASK				(1 << 7)
+ + #define OMAP3430_ST_GPT5_SHIFT				6
+ + #define OMAP3430_ST_GPT5_MASK				(1 << 6)
+ + #define OMAP3430_ST_GPT4_SHIFT				5
+ + #define OMAP3430_ST_GPT4_MASK				(1 << 5)
+ + #define OMAP3430_ST_GPT3_SHIFT				4
+ + #define OMAP3430_ST_GPT3_MASK				(1 << 4)
+ + #define OMAP3430_ST_GPT2_SHIFT				3
+ + #define OMAP3430_ST_GPT2_MASK				(1 << 3)
+ + 
+ + /* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */
+ + #define OMAP3430_EN_CORE_SHIFT				0
+ + #define OMAP3430_EN_CORE_MASK				(1 << 0)
+ + 
+ + 
+ + /*
+ +  * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP
+ +  * submodule to exit hardreset
+ +  */
+ + #define MAX_MODULE_HARDRESET_WAIT		10000
+ + 
+ + # ifndef __ASSEMBLER__
+ + extern void __iomem *prm_base;
+ + extern void __iomem *cm_base;
+ + extern void __iomem *cm2_base;
+ + 
+ + /**
+ +  * struct omap_prcm_irq - describes a PRCM interrupt bit
+ +  * @name: a short name describing the interrupt type, e.g. "wkup" or "io"
+ +  * @offset: the bit shift of the interrupt inside the IRQ{ENABLE,STATUS} regs
+ +  * @priority: should this interrupt be handled before @priority=false IRQs?
+ +  *
+ +  * Describes interrupt bits inside the PRM_IRQ{ENABLE,STATUS}_MPU* registers.
+ +  * On systems with multiple PRM MPU IRQ registers, the bitfields read from
+ +  * the registers are concatenated, so @offset could be > 31 on these systems -
+ +  * see omap_prm_irq_handler() for more details.  I/O ring interrupts should
+ +  * have @priority set to true.
+ +  */
+ + struct omap_prcm_irq {
+ + 	const char *name;
+ + 	unsigned int offset;
+ + 	bool priority;
+ + };
+ + 
+ + /**
+ +  * struct omap_prcm_irq_setup - PRCM interrupt controller details
+ +  * @ack: PRM register offset for the first PRM_IRQSTATUS_MPU register
+ +  * @mask: PRM register offset for the first PRM_IRQENABLE_MPU register
+ +  * @nr_regs: number of PRM_IRQ{STATUS,ENABLE}_MPU* registers
+ +  * @nr_irqs: number of entries in the @irqs array
+ +  * @irqs: ptr to an array of PRCM interrupt bits (see @nr_irqs)
+ +  * @irq: MPU IRQ asserted when a PRCM interrupt arrives
+ +  * @read_pending_irqs: fn ptr to determine if any PRCM IRQs are pending
+ +  * @ocp_barrier: fn ptr to force buffered PRM writes to complete
+ +  * @save_and_clear_irqen: fn ptr to save and clear IRQENABLE regs
+ +  * @restore_irqen: fn ptr to save and clear IRQENABLE regs
+ +  * @saved_mask: IRQENABLE regs are saved here during suspend
+ +  * @priority_mask: 1 bit per IRQ, set to 1 if omap_prcm_irq.priority = true
+ +  * @base_irq: base dynamic IRQ number, returned from irq_alloc_descs() in init
+ +  * @suspended: set to true after Linux suspend code has called our ->prepare()
+ +  * @suspend_save_flag: set to true after IRQ masks have been saved and disabled
+ +  *
+ +  * @saved_mask, @priority_mask, @base_irq, @suspended, and
+ +  * @suspend_save_flag are populated dynamically, and are not to be
+ +  * specified in static initializers.
+ +  */
+ + struct omap_prcm_irq_setup {
+ + 	u16 ack;
+ + 	u16 mask;
+ + 	u8 nr_regs;
+ + 	u8 nr_irqs;
+ + 	const struct omap_prcm_irq *irqs;
+ + 	int irq;
+ + 	void (*read_pending_irqs)(unsigned long *events);
+ + 	void (*ocp_barrier)(void);
+ + 	void (*save_and_clear_irqen)(u32 *saved_mask);
+ + 	void (*restore_irqen)(u32 *saved_mask);
+ + 	u32 *saved_mask;
+ + 	u32 *priority_mask;
+ + 	int base_irq;
+ + 	bool suspended;
+ + 	bool suspend_save_flag;
+ + };
+ + 
+ + /* OMAP_PRCM_IRQ: convenience macro for creating struct omap_prcm_irq records */
+ + #define OMAP_PRCM_IRQ(_name, _offset, _priority) {	\
+ + 	.name = _name,					\
+ + 	.offset = _offset,				\
+ + 	.priority = _priority				\
+ + 	}
+ + 
+ + extern void omap_prcm_irq_cleanup(void);
+ + extern int omap_prcm_register_chain_handler(
+ + 	struct omap_prcm_irq_setup *irq_setup);
+ + extern int omap_prcm_event_to_irq(const char *event);
+ + extern void omap_prcm_irq_prepare(void);
+ + extern void omap_prcm_irq_complete(void);
+ + 
+ + # endif
+ + 
+ + #endif
+ + 
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/prm2xxx_3xxx.c linux-3.2.1/arch/arm/mach-ckb_3352/prm2xxx_3xxx.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/prm2xxx_3xxx.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/prm2xxx_3xxx.c	2014-11-25 13:19:15.050993430 +0900
+ ***************
+ *** 0 ****
+ --- 1,221 ----
+ + /*
+ +  * OMAP2/3 PRM module functions
+ +  *
+ +  * Copyright (C) 2010-2011 Texas Instruments, Inc.
+ +  * Copyright (C) 2010 Nokia Corporation
+ +  * Benoît Cousson
+ +  * Paul Walmsley
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #include <linux/kernel.h>
+ + #include <linux/errno.h>
+ + #include <linux/err.h>
+ + #include <linux/io.h>
+ + 
+ + #include "common.h"
+ + #include <plat/cpu.h>
+ + #include <plat/prcm.h>
+ + 
+ + #include "vp.h"
+ + 
+ + #include "prm2xxx_3xxx.h"
+ + #include "cm2xxx_3xxx.h"
+ + #include "prm-regbits-24xx.h"
+ + #include "prm-regbits-34xx.h"
+ + 
+ + static const struct omap_prcm_irq omap3_prcm_irqs[] = {
+ + 	OMAP_PRCM_IRQ("wkup",	0,	0),
+ + 	OMAP_PRCM_IRQ("io",	9,	1),
+ + };
+ + 
+ + static struct omap_prcm_irq_setup omap3_prcm_irq_setup = {
+ + 	.ack			= OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
+ + 	.mask			= OMAP3_PRM_IRQENABLE_MPU_OFFSET,
+ + 	.nr_regs		= 1,
+ + 	.irqs			= omap3_prcm_irqs,
+ + 	.nr_irqs		= ARRAY_SIZE(omap3_prcm_irqs),
+ + 	.irq			= INT_34XX_PRCM_MPU_IRQ,
+ + 	.read_pending_irqs	= &omap3xxx_prm_read_pending_irqs,
+ + 	.ocp_barrier		= &omap3xxx_prm_ocp_barrier,
+ + 	.save_and_clear_irqen	= &omap3xxx_prm_save_and_clear_irqen,
+ + 	.restore_irqen		= &omap3xxx_prm_restore_irqen,
+ + };
+ + 
+ + u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
+ + {
+ + 	return __raw_readl(prm_base + module + idx);
+ + }
+ + 
+ + void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
+ + {
+ + 	__raw_writel(val, prm_base + module + idx);
+ + }
+ + 
+ + /* Read-modify-write a register in a PRM module. Caller must lock */
+ + u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
+ + {
+ + 	u32 v;
+ + 
+ + 	v = omap2_prm_read_mod_reg(module, idx);
+ + 	v &= ~mask;
+ + 	v |= bits;
+ + 	omap2_prm_write_mod_reg(v, module, idx);
+ + 
+ + 	return v;
+ + }
+ + 
+ + /* Read a PRM register, AND it, and shift the result down to bit 0 */
+ + u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
+ + {
+ + 	u32 v;
+ + 
+ + 	v = omap2_prm_read_mod_reg(domain, idx);
+ + 	v &= mask;
+ + 	v >>= __ffs(mask);
+ + 
+ + 	return v;
+ + }
+ + 
+ + u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
+ + {
+ + 	return omap2_prm_rmw_mod_reg_bits(bits, bits, module, idx);
+ + }
+ + 
+ + u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
+ + {
+ + 	return omap2_prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
+ + }
+ + 
+ + 
+ + /* PRM VP */
+ + 
+ + /*
+ +  * struct omap3_vp - OMAP3 VP register access description.
+ +  * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
+ +  */
+ + struct omap3_vp {
+ + 	u32 tranxdone_status;
+ + };
+ + 
+ + static struct omap3_vp omap3_vp[] = {
+ + 	[OMAP3_VP_VDD_MPU_ID] = {
+ + 		.tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK,
+ + 	},
+ + 	[OMAP3_VP_VDD_CORE_ID] = {
+ + 		.tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK,
+ + 	},
+ + };
+ + 
+ + #define MAX_VP_ID ARRAY_SIZE(omap3_vp);
+ + 
+ + u32 omap3_prm_vp_check_txdone(u8 vp_id)
+ + {
+ + 	struct omap3_vp *vp = &omap3_vp[vp_id];
+ + 	u32 irqstatus;
+ + 
+ + 	irqstatus = omap2_prm_read_mod_reg(OCP_MOD,
+ + 					   OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
+ + 	return irqstatus & vp->tranxdone_status;
+ + }
+ + 
+ + void omap3_prm_vp_clear_txdone(u8 vp_id)
+ + {
+ + 	struct omap3_vp *vp = &omap3_vp[vp_id];
+ + 
+ + 	omap2_prm_write_mod_reg(vp->tranxdone_status,
+ + 				OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
+ + }
+ + 
+ + u32 omap3_prm_vcvp_read(u8 offset)
+ + {
+ + 	return omap2_prm_read_mod_reg(OMAP3430_GR_MOD, offset);
+ + }
+ + 
+ + void omap3_prm_vcvp_write(u32 val, u8 offset)
+ + {
+ + 	omap2_prm_write_mod_reg(val, OMAP3430_GR_MOD, offset);
+ + }
+ + 
+ + u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
+ + {
+ + 	return omap2_prm_rmw_mod_reg_bits(mask, bits, OMAP3430_GR_MOD, offset);
+ + }
+ + 
+ + /**
+ +  * omap3xxx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
+ +  * @events: ptr to a u32, preallocated by caller
+ +  *
+ +  * Read PRM_IRQSTATUS_MPU bits, AND'ed with the currently-enabled PRM
+ +  * MPU IRQs, and store the result into the u32 pointed to by @events.
+ +  * No return value.
+ +  */
+ + void omap3xxx_prm_read_pending_irqs(unsigned long *events)
+ + {
+ + 	u32 mask, st;
+ + 
+ + 	/* XXX Can the mask read be avoided (e.g., can it come from RAM?) */
+ + 	mask = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
+ + 	st = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
+ + 
+ + 	events[0] = mask & st;
+ + }
+ + 
+ + /**
+ +  * omap3xxx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
+ +  *
+ +  * Force any buffered writes to the PRM IP block to complete.  Needed
+ +  * by the PRM IRQ handler, which reads and writes directly to the IP
+ +  * block, to avoid race conditions after acknowledging or clearing IRQ
+ +  * bits.  No return value.
+ +  */
+ + void omap3xxx_prm_ocp_barrier(void)
+ + {
+ + 	omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
+ + }
+ + 
+ + /**
+ +  * omap3xxx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU reg
+ +  * @saved_mask: ptr to a u32 array to save IRQENABLE bits
+ +  *
+ +  * Save the PRM_IRQENABLE_MPU register to @saved_mask.  @saved_mask
+ +  * must be allocated by the caller.  Intended to be used in the PRM
+ +  * interrupt handler suspend callback.  The OCP barrier is needed to
+ +  * ensure the write to disable PRM interrupts reaches the PRM before
+ +  * returning; otherwise, spurious interrupts might occur.  No return
+ +  * value.
+ +  */
+ + void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask)
+ + {
+ + 	saved_mask[0] = omap2_prm_read_mod_reg(OCP_MOD,
+ + 					       OMAP3_PRM_IRQENABLE_MPU_OFFSET);
+ + 	omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
+ + 
+ + 	/* OCP barrier */
+ + 	omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
+ + }
+ + 
+ + /**
+ +  * omap3xxx_prm_restore_irqen - set PRM_IRQENABLE_MPU register from args
+ +  * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
+ +  *
+ +  * Restore the PRM_IRQENABLE_MPU register from @saved_mask.  Intended
+ +  * to be used in the PRM interrupt handler resume callback to restore
+ +  * values saved by omap3xxx_prm_save_and_clear_irqen().  No OCP
+ +  * barrier should be needed here; any pending PRM interrupts will fire
+ +  * once the writes reach the PRM.  No return value.
+ +  */
+ + void omap3xxx_prm_restore_irqen(u32 *saved_mask)
+ + {
+ + 	omap2_prm_write_mod_reg(saved_mask[0], OCP_MOD,
+ + 				OMAP3_PRM_IRQENABLE_MPU_OFFSET);
+ + }
+ + 
+ + static int __init omap3xxx_prcm_init(void)
+ + {
+ + 	return 0;
+ + }
+ + subsys_initcall(omap3xxx_prcm_init);
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/prm2xxx_3xxx.h linux-3.2.1/arch/arm/mach-ckb_3352/prm2xxx_3xxx.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/prm2xxx_3xxx.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/prm2xxx_3xxx.h	2014-11-25 13:19:15.050993430 +0900
+ ***************
+ *** 0 ****
+ --- 1,379 ----
+ + /*
+ +  * OMAP2/3 Power/Reset Management (PRM) register definitions
+ +  *
+ +  * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc.
+ +  * Copyright (C) 2008-2010 Nokia Corporation
+ +  * Paul Walmsley
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  *
+ +  * The PRM hardware modules on the OMAP2/3 are quite similar to each
+ +  * other.  The PRM on OMAP4 has a new register layout, and is handled
+ +  * in a separate file.
+ +  */
+ + #ifndef __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H
+ + #define __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H
+ + 
+ + #include "prcm-common.h"
+ + #include "prm.h"
+ + 
+ + #define OMAP2420_PRM_REGADDR(module, reg)				\
+ + 		OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
+ + #define OMAP2430_PRM_REGADDR(module, reg)				\
+ + 		OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
+ + #define OMAP34XX_PRM_REGADDR(module, reg)				\
+ + 		OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
+ + 
+ + 
+ + /*
+ +  * OMAP2-specific global PRM registers
+ +  * Use __raw_{read,write}l() with these registers.
+ +  *
+ +  * With a few exceptions, these are the register names beginning with
+ +  * PRCM_* on 24xx.  (The exceptions are the IRQSTATUS and IRQENABLE
+ +  * bits.)
+ +  *
+ +  */
+ + 
+ + #define OMAP2_PRCM_REVISION_OFFSET	0x0000
+ + #define OMAP2420_PRCM_REVISION		OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000)
+ + #define OMAP2_PRCM_SYSCONFIG_OFFSET	0x0010
+ + #define OMAP2420_PRCM_SYSCONFIG		OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010)
+ + 
+ + #define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET	0x0018
+ + #define OMAP2420_PRCM_IRQSTATUS_MPU	OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018)
+ + #define OMAP2_PRCM_IRQENABLE_MPU_OFFSET	0x001c
+ + #define OMAP2420_PRCM_IRQENABLE_MPU	OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c)
+ + 
+ + #define OMAP2_PRCM_VOLTCTRL_OFFSET	0x0050
+ + #define OMAP2420_PRCM_VOLTCTRL		OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050)
+ + #define OMAP2_PRCM_VOLTST_OFFSET	0x0054
+ + #define OMAP2420_PRCM_VOLTST		OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054)
+ + #define OMAP2_PRCM_CLKSRC_CTRL_OFFSET	0x0060
+ + #define OMAP2420_PRCM_CLKSRC_CTRL	OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060)
+ + #define OMAP2_PRCM_CLKOUT_CTRL_OFFSET	0x0070
+ + #define OMAP2420_PRCM_CLKOUT_CTRL	OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070)
+ + #define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET	0x0078
+ + #define OMAP2420_PRCM_CLKEMUL_CTRL	OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078)
+ + #define OMAP2_PRCM_CLKCFG_CTRL_OFFSET	0x0080
+ + #define OMAP2420_PRCM_CLKCFG_CTRL	OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080)
+ + #define OMAP2_PRCM_CLKCFG_STATUS_OFFSET	0x0084
+ + #define OMAP2420_PRCM_CLKCFG_STATUS	OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084)
+ + #define OMAP2_PRCM_VOLTSETUP_OFFSET	0x0090
+ + #define OMAP2420_PRCM_VOLTSETUP		OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090)
+ + #define OMAP2_PRCM_CLKSSETUP_OFFSET	0x0094
+ + #define OMAP2420_PRCM_CLKSSETUP		OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094)
+ + #define OMAP2_PRCM_POLCTRL_OFFSET	0x0098
+ + #define OMAP2420_PRCM_POLCTRL		OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098)
+ + 
+ + #define OMAP2430_PRCM_REVISION		OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000)
+ + #define OMAP2430_PRCM_SYSCONFIG		OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010)
+ + 
+ + #define OMAP2430_PRCM_IRQSTATUS_MPU	OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018)
+ + #define OMAP2430_PRCM_IRQENABLE_MPU	OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c)
+ + 
+ + #define OMAP2430_PRCM_VOLTCTRL		OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050)
+ + #define OMAP2430_PRCM_VOLTST		OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054)
+ + #define OMAP2430_PRCM_CLKSRC_CTRL	OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060)
+ + #define OMAP2430_PRCM_CLKOUT_CTRL	OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070)
+ + #define OMAP2430_PRCM_CLKEMUL_CTRL	OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078)
+ + #define OMAP2430_PRCM_CLKCFG_CTRL	OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080)
+ + #define OMAP2430_PRCM_CLKCFG_STATUS	OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084)
+ + #define OMAP2430_PRCM_VOLTSETUP		OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090)
+ + #define OMAP2430_PRCM_CLKSSETUP		OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094)
+ + #define OMAP2430_PRCM_POLCTRL		OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098)
+ + 
+ + /*
+ +  * OMAP3-specific global PRM registers
+ +  * Use __raw_{read,write}l() with these registers.
+ +  *
+ +  * With a few exceptions, these are the register names beginning with
+ +  * PRM_* on 34xx.  (The exceptions are the IRQSTATUS and IRQENABLE
+ +  * bits.)
+ +  */
+ + 
+ + #define OMAP3_PRM_REVISION_OFFSET	0x0004
+ + #define OMAP3430_PRM_REVISION		OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
+ + #define OMAP3_PRM_SYSCONFIG_OFFSET	0x0014
+ + #define OMAP3430_PRM_SYSCONFIG		OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
+ + 
+ + #define OMAP3_PRM_IRQSTATUS_MPU_OFFSET	0x0018
+ + #define OMAP3430_PRM_IRQSTATUS_MPU	OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
+ + #define OMAP3_PRM_IRQENABLE_MPU_OFFSET	0x001c
+ + #define OMAP3430_PRM_IRQENABLE_MPU	OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
+ + 
+ + 
+ + #define OMAP3_PRM_VC_SMPS_SA_OFFSET	0x0020
+ + #define OMAP3430_PRM_VC_SMPS_SA		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
+ + #define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET	0x0024
+ + #define OMAP3430_PRM_VC_SMPS_VOL_RA	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
+ + #define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET	0x0028
+ + #define OMAP3430_PRM_VC_SMPS_CMD_RA	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
+ + #define OMAP3_PRM_VC_CMD_VAL_0_OFFSET	0x002c
+ + #define OMAP3430_PRM_VC_CMD_VAL_0	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
+ + #define OMAP3_PRM_VC_CMD_VAL_1_OFFSET	0x0030
+ + #define OMAP3430_PRM_VC_CMD_VAL_1	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
+ + #define OMAP3_PRM_VC_CH_CONF_OFFSET	0x0034
+ + #define OMAP3430_PRM_VC_CH_CONF		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
+ + #define OMAP3_PRM_VC_I2C_CFG_OFFSET	0x0038
+ + #define OMAP3430_PRM_VC_I2C_CFG		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
+ + #define OMAP3_PRM_VC_BYPASS_VAL_OFFSET	0x003c
+ + #define OMAP3430_PRM_VC_BYPASS_VAL	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
+ + #define OMAP3_PRM_RSTCTRL_OFFSET	0x0050
+ + #define OMAP3430_PRM_RSTCTRL		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
+ + #define OMAP3_PRM_RSTTIME_OFFSET	0x0054
+ + #define OMAP3430_PRM_RSTTIME		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
+ + #define OMAP3_PRM_RSTST_OFFSET	0x0058
+ + #define OMAP3430_PRM_RSTST		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
+ + #define OMAP3_PRM_VOLTCTRL_OFFSET	0x0060
+ + #define OMAP3430_PRM_VOLTCTRL		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
+ + #define OMAP3_PRM_SRAM_PCHARGE_OFFSET	0x0064
+ + #define OMAP3430_PRM_SRAM_PCHARGE	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
+ + #define OMAP3_PRM_CLKSRC_CTRL_OFFSET	0x0070
+ + #define OMAP3430_PRM_CLKSRC_CTRL	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
+ + #define OMAP3_PRM_VOLTSETUP1_OFFSET	0x0090
+ + #define OMAP3430_PRM_VOLTSETUP1		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
+ + #define OMAP3_PRM_VOLTOFFSET_OFFSET	0x0094
+ + #define OMAP3430_PRM_VOLTOFFSET		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
+ + #define OMAP3_PRM_CLKSETUP_OFFSET	0x0098
+ + #define OMAP3430_PRM_CLKSETUP		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
+ + #define OMAP3_PRM_POLCTRL_OFFSET	0x009c
+ + #define OMAP3430_PRM_POLCTRL		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
+ + #define OMAP3_PRM_VOLTSETUP2_OFFSET	0x00a0
+ + #define OMAP3430_PRM_VOLTSETUP2		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
+ + #define OMAP3_PRM_VP1_CONFIG_OFFSET	0x00b0
+ + #define OMAP3430_PRM_VP1_CONFIG		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
+ + #define OMAP3_PRM_VP1_VSTEPMIN_OFFSET	0x00b4
+ + #define OMAP3430_PRM_VP1_VSTEPMIN	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
+ + #define OMAP3_PRM_VP1_VSTEPMAX_OFFSET	0x00b8
+ + #define OMAP3430_PRM_VP1_VSTEPMAX	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
+ + #define OMAP3_PRM_VP1_VLIMITTO_OFFSET	0x00bc
+ + #define OMAP3430_PRM_VP1_VLIMITTO	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
+ + #define OMAP3_PRM_VP1_VOLTAGE_OFFSET	0x00c0
+ + #define OMAP3430_PRM_VP1_VOLTAGE	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
+ + #define OMAP3_PRM_VP1_STATUS_OFFSET	0x00c4
+ + #define OMAP3430_PRM_VP1_STATUS		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
+ + #define OMAP3_PRM_VP2_CONFIG_OFFSET	0x00d0
+ + #define OMAP3430_PRM_VP2_CONFIG		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
+ + #define OMAP3_PRM_VP2_VSTEPMIN_OFFSET	0x00d4
+ + #define OMAP3430_PRM_VP2_VSTEPMIN	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
+ + #define OMAP3_PRM_VP2_VSTEPMAX_OFFSET	0x00d8
+ + #define OMAP3430_PRM_VP2_VSTEPMAX	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
+ + #define OMAP3_PRM_VP2_VLIMITTO_OFFSET	0x00dc
+ + #define OMAP3430_PRM_VP2_VLIMITTO	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
+ + #define OMAP3_PRM_VP2_VOLTAGE_OFFSET	0x00e0
+ + #define OMAP3430_PRM_VP2_VOLTAGE	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
+ + #define OMAP3_PRM_VP2_STATUS_OFFSET	0x00e4
+ + #define OMAP3430_PRM_VP2_STATUS		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
+ + 
+ + #define OMAP3_PRM_CLKSEL_OFFSET	0x0040
+ + #define OMAP3430_PRM_CLKSEL		OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
+ + #define OMAP3_PRM_CLKOUT_CTRL_OFFSET	0x0070
+ + #define OMAP3430_PRM_CLKOUT_CTRL	OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
+ + 
+ + /*
+ +  * Module specific PRM register offsets from PRM_BASE + domain offset
+ +  *
+ +  * Use prm_{read,write}_mod_reg() with these registers.
+ +  *
+ +  * With a few exceptions, these are the register names beginning with
+ +  * {PM,RM}_* on both OMAP2/3 SoC families..  (The exceptions are the
+ +  * IRQSTATUS and IRQENABLE bits.)
+ +  */
+ + 
+ + /* Register offsets appearing on both OMAP2 and OMAP3 */
+ + 
+ + #define OMAP2_RM_RSTCTRL				0x0050
+ + #define OMAP2_RM_RSTTIME				0x0054
+ + #define OMAP2_RM_RSTST					0x0058
+ + #define OMAP2_PM_PWSTCTRL				0x00e0
+ + #define OMAP2_PM_PWSTST					0x00e4
+ + 
+ + #define PM_WKEN						0x00a0
+ + #define PM_WKEN1					PM_WKEN
+ + #define PM_WKST						0x00b0
+ + #define PM_WKST1					PM_WKST
+ + #define PM_WKDEP					0x00c8
+ + #define PM_EVGENCTRL					0x00d4
+ + #define PM_EVGENONTIM					0x00d8
+ + #define PM_EVGENOFFTIM					0x00dc
+ + 
+ + /* OMAP2xxx specific register offsets */
+ + #define OMAP24XX_PM_WKEN2				0x00a4
+ + #define OMAP24XX_PM_WKST2				0x00b4
+ + 
+ + #define OMAP24XX_PRCM_IRQSTATUS_DSP			0x00f0	/* IVA mod */
+ + #define OMAP24XX_PRCM_IRQENABLE_DSP			0x00f4	/* IVA mod */
+ + #define OMAP24XX_PRCM_IRQSTATUS_IVA			0x00f8
+ + #define OMAP24XX_PRCM_IRQENABLE_IVA			0x00fc
+ + 
+ + /* OMAP3 specific register offsets */
+ + #define OMAP3430ES2_PM_WKEN3				0x00f0
+ + #define OMAP3430ES2_PM_WKST3				0x00b8
+ + 
+ + #define OMAP3430_PM_MPUGRPSEL				0x00a4
+ + #define OMAP3430_PM_MPUGRPSEL1				OMAP3430_PM_MPUGRPSEL
+ + #define OMAP3430ES2_PM_MPUGRPSEL3			0x00f8
+ + 
+ + #define OMAP3430_PM_IVAGRPSEL				0x00a8
+ + #define OMAP3430_PM_IVAGRPSEL1				OMAP3430_PM_IVAGRPSEL
+ + #define OMAP3430ES2_PM_IVAGRPSEL3			0x00f4
+ + 
+ + #define OMAP3430_PM_PREPWSTST				0x00e8
+ + 
+ + #define OMAP3430_PRM_IRQSTATUS_IVA2			0x00f8
+ + #define OMAP3430_PRM_IRQENABLE_IVA2			0x00fc
+ + 
+ + 
+ + #ifndef __ASSEMBLER__
+ + /* Power/reset management domain register get/set */
+ + extern u32 omap2_prm_read_mod_reg(s16 module, u16 idx);
+ + extern void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx);
+ + extern u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
+ + extern u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx);
+ + extern u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx);
+ + extern u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask);
+ + 
+ + /* OMAP3-specific VP functions */
+ + u32 omap3_prm_vp_check_txdone(u8 vp_id);
+ + void omap3_prm_vp_clear_txdone(u8 vp_id);
+ + 
+ + /*
+ +  * OMAP3 access functions for voltage controller (VC) and
+ +  * voltage proccessor (VP) in the PRM.
+ +  */
+ + extern u32 omap3_prm_vcvp_read(u8 offset);
+ + extern void omap3_prm_vcvp_write(u32 val, u8 offset);
+ + extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
+ + 
+ + /* PRM interrupt-related functions */
+ + extern void omap3xxx_prm_read_pending_irqs(unsigned long *events);
+ + extern void omap3xxx_prm_ocp_barrier(void);
+ + extern void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask);
+ + extern void omap3xxx_prm_restore_irqen(u32 *saved_mask);
+ + 
+ + #endif
+ + 
+ + /*
+ +  * Bits common to specific registers
+ +  *
+ +  * The 3430 register and bit names are generally used,
+ +  * since they tend to make more sense
+ +  */
+ + 
+ + /* PM_EVGENONTIM_MPU */
+ + /* Named PM_EVEGENONTIM_MPU on the 24XX */
+ + #define OMAP_ONTIMEVAL_SHIFT				0
+ + #define OMAP_ONTIMEVAL_MASK				(0xffffffff << 0)
+ + 
+ + /* PM_EVGENOFFTIM_MPU */
+ + /* Named PM_EVEGENOFFTIM_MPU on the 24XX */
+ + #define OMAP_OFFTIMEVAL_SHIFT				0
+ + #define OMAP_OFFTIMEVAL_MASK				(0xffffffff << 0)
+ + 
+ + /* PRM_CLKSETUP and PRCM_VOLTSETUP */
+ + /* Named PRCM_CLKSSETUP on the 24XX */
+ + #define OMAP_SETUP_TIME_SHIFT				0
+ + #define OMAP_SETUP_TIME_MASK				(0xffff << 0)
+ + 
+ + /* PRM_CLKSRC_CTRL */
+ + /* Named PRCM_CLKSRC_CTRL on the 24XX */
+ + #define OMAP_SYSCLKDIV_SHIFT				6
+ + #define OMAP_SYSCLKDIV_MASK				(0x3 << 6)
+ + #define OMAP_AUTOEXTCLKMODE_SHIFT			3
+ + #define OMAP_AUTOEXTCLKMODE_MASK			(0x3 << 3)
+ + #define OMAP_SYSCLKSEL_SHIFT				0
+ + #define OMAP_SYSCLKSEL_MASK				(0x3 << 0)
+ + 
+ + /* PM_EVGENCTRL_MPU */
+ + #define OMAP_OFFLOADMODE_SHIFT				3
+ + #define OMAP_OFFLOADMODE_MASK				(0x3 << 3)
+ + #define OMAP_ONLOADMODE_SHIFT				1
+ + #define OMAP_ONLOADMODE_MASK				(0x3 << 1)
+ + #define OMAP_ENABLE_MASK				(1 << 0)
+ + 
+ + /* PRM_RSTTIME */
+ + /* Named RM_RSTTIME_WKUP on the 24xx */
+ + #define OMAP_RSTTIME2_SHIFT				8
+ + #define OMAP_RSTTIME2_MASK				(0x1f << 8)
+ + #define OMAP_RSTTIME1_SHIFT				0
+ + #define OMAP_RSTTIME1_MASK				(0xff << 0)
+ + 
+ + /* PRM_RSTCTRL */
+ + /* Named RM_RSTCTRL_WKUP on the 24xx */
+ + /* 2420 calls RST_DPLL3 'RST_DPLL' */
+ + #define OMAP_RST_DPLL3_MASK				(1 << 2)
+ + #define OMAP_RST_GS_MASK				(1 << 1)
+ + 
+ + 
+ + /*
+ +  * Bits common to module-shared registers
+ +  *
+ +  * Not all registers of a particular type support all of these bits -
+ +  * check TRM if you are unsure
+ +  */
+ + 
+ + /*
+ +  * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is
+ +  *	 called 'COREWKUP_RST'
+ +  *
+ +  * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
+ +  *	 RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
+ +  */
+ + #define OMAP_COREDOMAINWKUP_RST_MASK			(1 << 3)
+ + 
+ + /*
+ +  * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
+ +  *
+ +  * 2430: RM_RSTST_MDM
+ +  *
+ +  * 3430: RM_RSTST_CORE, RM_RSTST_EMU
+ +  */
+ + #define OMAP_DOMAINWKUP_RST_MASK			(1 << 2)
+ + 
+ + /*
+ +  * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
+ +  *	 On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'.
+ +  *
+ +  * 2430: RM_RSTST_MDM
+ +  *
+ +  * 3430: RM_RSTST_CORE, RM_RSTST_EMU
+ +  */
+ + #define OMAP_GLOBALWARM_RST_MASK			(1 << 1)
+ + #define OMAP_GLOBALCOLD_RST_MASK			(1 << 0)
+ + 
+ + /*
+ +  * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
+ +  *	 2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP"
+ +  *
+ +  * 2430: PM_WKDEP_MDM
+ +  *
+ +  * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
+ +  *	 PM_WKDEP_PER
+ +  */
+ + #define OMAP_EN_WKUP_SHIFT				4
+ + #define OMAP_EN_WKUP_MASK				(1 << 4)
+ + 
+ + /*
+ +  * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
+ +  *	 PM_PWSTCTRL_DSP
+ +  *
+ +  * 2430: PM_PWSTCTRL_MDM
+ +  *
+ +  * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
+ +  *	 PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
+ +  *	 PM_PWSTCTRL_NEON
+ +  */
+ + #define OMAP_LOGICRETSTATE_MASK				(1 << 2)
+ + 
+ + 
+ + /*
+ +  * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP
+ +  * submodule to exit hardreset
+ +  */
+ + #define MAX_MODULE_HARDRESET_WAIT		10000
+ + 
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/prm33xx.h linux-3.2.1/arch/arm/mach-ckb_3352/prm33xx.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/prm33xx.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/prm33xx.h	2014-11-25 13:19:15.050993430 +0900
+ ***************
+ *** 0 ****
+ --- 1,118 ----
+ + /*
+ +  * AM33XX PRM instance offset macros
+ +  *
+ +  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #ifndef __ARCH_ARM_MACH_OMAP2_PRM33XX_H
+ + #define __ARCH_ARM_MACH_OMAP2_PRM33XX_H
+ + 
+ + #include "prcm-common.h"
+ + #include "prm.h"
+ + 
+ + #define AM33XX_PRM_BASE               0x44E00000
+ + 
+ + #define AM33XX_PRM_REGADDR(inst, reg)                         \
+ + 	AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRM_BASE + (inst) + (reg))
+ + 
+ + /* PRM instances */
+ + #define AM33XX_PRM_OCP_SOCKET_MOD	0x0B00
+ + #define AM33XX_PRM_PER_MOD		0x0C00
+ + #define AM33XX_PRM_WKUP_MOD		0x0D00
+ + #define AM33XX_PRM_MPU_MOD		0x0E00
+ + #define AM33XX_PRM_DEVICE_MOD		0x0F00
+ + #define AM33XX_PRM_RTC_MOD		0x1000
+ + #define AM33XX_PRM_GFX_MOD		0x1100
+ + #define AM33XX_PRM_CEFUSE_MOD		0x1200
+ + 
+ + /* PRM */
+ + 
+ + /* PRM.OCP_SOCKET_PRM register offsets */
+ + #define AM33XX_REVISION_PRM_OFFSET		0x0000
+ + #define AM33XX_REVISION_PRM			AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0000)
+ + #define AM33XX_PRM_IRQSTATUS_MPU_OFFSET		0x0004
+ + #define AM33XX_PRM_IRQSTATUS_MPU		AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0004)
+ + #define AM33XX_PRM_IRQENABLE_MPU_OFFSET		0x0008
+ + #define AM33XX_PRM_IRQENABLE_MPU		AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0008)
+ + #define AM33XX_PRM_IRQSTATUS_M3_OFFSET		0x000c
+ + #define AM33XX_PRM_IRQSTATUS_M3			AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x000c)
+ + #define AM33XX_PRM_IRQENABLE_M3_OFFSET		0x0010
+ + #define AM33XX_PRM_IRQENABLE_M3			AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0010)
+ + 
+ + /* PRM.PER_PRM register offsets */
+ + #define AM33XX_RM_PER_RSTCTRL_OFFSET		0x0000
+ + #define AM33XX_RM_PER_RSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0000)
+ + #define AM33XX_RM_PER_RSTST_OFFSET		0x0004
+ + #define AM33XX_RM_PER_RSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0004)
+ + #define AM33XX_PM_PER_PWRSTST_OFFSET		0x0008
+ + #define AM33XX_PM_PER_PWRSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0008)
+ + #define AM33XX_PM_PER_PWRSTCTRL_OFFSET		0x000c
+ + #define AM33XX_PM_PER_PWRSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x000c)
+ + 
+ + /* PRM.WKUP_PRM register offsets */
+ + #define AM33XX_RM_WKUP_RSTCTRL_OFFSET		0x0000
+ + #define AM33XX_RM_WKUP_RSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0000)
+ + #define AM33XX_PM_WKUP_PWRSTCTRL_OFFSET		0x0004
+ + #define AM33XX_PM_WKUP_PWRSTCTRL		AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0004)
+ + #define AM33XX_PM_WKUP_PWRSTST_OFFSET		0x0008
+ + #define AM33XX_PM_WKUP_PWRSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0008)
+ + #define AM33XX_RM_WKUP_RSTST_OFFSET		0x000c
+ + #define AM33XX_RM_WKUP_RSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x000c)
+ + 
+ + /* PRM.MPU_PRM register offsets */
+ + #define AM33XX_PM_MPU_PWRSTCTRL_OFFSET		0x0000
+ + #define AM33XX_PM_MPU_PWRSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0000)
+ + #define AM33XX_PM_MPU_PWRSTST_OFFSET		0x0004
+ + #define AM33XX_PM_MPU_PWRSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0004)
+ + #define AM33XX_RM_MPU_RSTST_OFFSET		0x0008
+ + #define AM33XX_RM_MPU_RSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0008)
+ + 
+ + /* PRM.DEVICE_PRM register offsets */
+ + #define AM33XX_PRM_RSTCTRL_OFFSET		0x0000
+ + #define AM33XX_PRM_RSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0000)
+ + #define AM33XX_PRM_RSTTIME_OFFSET		0x0004
+ + #define AM33XX_PRM_RSTTIME			AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0004)
+ + #define AM33XX_PRM_RSTST_OFFSET			0x0008
+ + #define AM33XX_PRM_RSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0008)
+ + #define AM33XX_PRM_SRAM_COUNT_OFFSET		0x000c
+ + #define AM33XX_PRM_SRAM_COUNT			AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x000c)
+ + #define AM33XX_PRM_LDO_SRAM_CORE_SETUP_OFFSET	0x0010
+ + #define AM33XX_PRM_LDO_SRAM_CORE_SETUP		AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0010)
+ + #define AM33XX_PRM_LDO_SRAM_CORE_CTRL_OFFSET	0x0014
+ + #define AM33XX_PRM_LDO_SRAM_CORE_CTRL		AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0014)
+ + #define AM33XX_PRM_LDO_SRAM_MPU_SETUP_OFFSET	0x0018
+ + #define AM33XX_PRM_LDO_SRAM_MPU_SETUP		AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0018)
+ + #define AM33XX_PRM_LDO_SRAM_MPU_CTRL_OFFSET	0x001c
+ + #define AM33XX_PRM_LDO_SRAM_MPU_CTRL		AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x001c)
+ + 
+ + /* PRM.RTC_PRM register offsets */
+ + #define AM33XX_PM_RTC_PWRSTCTRL_OFFSET		0x0000
+ + #define AM33XX_PM_RTC_PWRSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_RTC_MOD, 0x0000)
+ + #define AM33XX_PM_RTC_PWRSTST_OFFSET		0x0004
+ + #define AM33XX_PM_RTC_PWRSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_RTC_MOD, 0x0004)
+ + 
+ + /* PRM.GFX_PRM register offsets */
+ + #define AM33XX_PM_GFX_PWRSTCTRL_OFFSET		0x0000
+ + #define AM33XX_PM_GFX_PWRSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0000)
+ + #define AM33XX_RM_GFX_RSTCTRL_OFFSET		0x0004
+ + #define AM33XX_RM_GFX_RSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0004)
+ + #define AM33XX_PM_GFX_PWRSTST_OFFSET		0x0010
+ + #define AM33XX_PM_GFX_PWRSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0010)
+ + #define AM33XX_RM_GFX_RSTST_OFFSET		0x0014
+ + #define AM33XX_RM_GFX_RSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0014)
+ + 
+ + /* PRM.CEFUSE_PRM register offsets */
+ + #define AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET	0x0000
+ + #define AM33XX_PM_CEFUSE_PWRSTCTRL		AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0000)
+ + #define AM33XX_PM_CEFUSE_PWRSTST_OFFSET		0x0004
+ + #define AM33XX_PM_CEFUSE_PWRSTST		AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004)
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/prm44xx.h linux-3.2.1/arch/arm/mach-ckb_3352/prm44xx.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/prm44xx.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/prm44xx.h	2014-11-25 13:19:15.055289303 +0900
+ ***************
+ *** 0 ****
+ --- 1,774 ----
+ + /*
+ +  * OMAP44xx PRM instance offset macros
+ +  *
+ +  * Copyright (C) 2009-2011 Texas Instruments, Inc.
+ +  * Copyright (C) 2009-2010 Nokia Corporation
+ +  *
+ +  * Paul Walmsley (paul@pwsan.com)
+ +  * Rajendra Nayak (rnayak@ti.com)
+ +  * Benoit Cousson (b-cousson@ti.com)
+ +  *
+ +  * This file is automatically generated from the OMAP hardware databases.
+ +  * We respectfully ask that any modifications to this file be coordinated
+ +  * with the public linux-omap@vger.kernel.org mailing list and the
+ +  * authors above to ensure that the autogeneration scripts are kept
+ +  * up-to-date with the file contents.
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  *
+ +  * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
+ +  *     or "OMAP4430".
+ +  */
+ + 
+ + #ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H
+ + #define __ARCH_ARM_MACH_OMAP2_PRM44XX_H
+ + 
+ + #include "prcm-common.h"
+ + #include "prm.h"
+ + 
+ + #define OMAP4430_PRM_BASE		0x4a306000
+ + 
+ + #define OMAP44XX_PRM_REGADDR(inst, reg)				\
+ + 	OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg))
+ + 
+ + 
+ + /* PRM instances */
+ + #define OMAP4430_PRM_OCP_SOCKET_INST	0x0000
+ + #define OMAP4430_PRM_CKGEN_INST		0x0100
+ + #define OMAP4430_PRM_MPU_INST		0x0300
+ + #define OMAP4430_PRM_TESLA_INST		0x0400
+ + #define OMAP4430_PRM_ABE_INST		0x0500
+ + #define OMAP4430_PRM_ALWAYS_ON_INST	0x0600
+ + #define OMAP4430_PRM_CORE_INST		0x0700
+ + #define OMAP4430_PRM_IVAHD_INST		0x0f00
+ + #define OMAP4430_PRM_CAM_INST		0x1000
+ + #define OMAP4430_PRM_DSS_INST		0x1100
+ + #define OMAP4430_PRM_GFX_INST		0x1200
+ + #define OMAP4430_PRM_L3INIT_INST	0x1300
+ + #define OMAP4430_PRM_L4PER_INST		0x1400
+ + #define OMAP4430_PRM_CEFUSE_INST	0x1600
+ + #define OMAP4430_PRM_WKUP_INST		0x1700
+ + #define OMAP4430_PRM_WKUP_CM_INST	0x1800
+ + #define OMAP4430_PRM_EMU_INST		0x1900
+ + #define OMAP4430_PRM_EMU_CM_INST	0x1a00
+ + #define OMAP4430_PRM_DEVICE_INST	0x1b00
+ + #define OMAP4430_PRM_INSTR_INST		0x1f00
+ + 
+ + /* PRM clockdomain register offsets (from instance start) */
+ + #define OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS	0x0000
+ + #define OMAP4430_PRM_EMU_CM_EMU_CDOFFS		0x0000
+ + 
+ + /* OMAP4 specific register offsets */
+ + #define OMAP4_RM_RSTCTRL				0x0000
+ + #define OMAP4_RM_RSTTIME				0x0004
+ + #define OMAP4_RM_RSTST					0x0008
+ + #define OMAP4_PM_PWSTCTRL				0x0000
+ + #define OMAP4_PM_PWSTST					0x0004
+ + 
+ + 
+ + /* PRM */
+ + 
+ + /* PRM.OCP_SOCKET_PRM register offsets */
+ + #define OMAP4_REVISION_PRM_OFFSET			0x0000
+ + #define OMAP4430_REVISION_PRM				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0000)
+ + #define OMAP4_PRM_IRQSTATUS_MPU_OFFSET			0x0010
+ + #define OMAP4430_PRM_IRQSTATUS_MPU			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0010)
+ + #define OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET		0x0014
+ + #define OMAP4430_PRM_IRQSTATUS_MPU_2			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0014)
+ + #define OMAP4_PRM_IRQENABLE_MPU_OFFSET			0x0018
+ + #define OMAP4430_PRM_IRQENABLE_MPU			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0018)
+ + #define OMAP4_PRM_IRQENABLE_MPU_2_OFFSET		0x001c
+ + #define OMAP4430_PRM_IRQENABLE_MPU_2			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x001c)
+ + #define OMAP4_PRM_IRQSTATUS_DUCATI_OFFSET		0x0020
+ + #define OMAP4430_PRM_IRQSTATUS_DUCATI			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0020)
+ + #define OMAP4_PRM_IRQENABLE_DUCATI_OFFSET		0x0028
+ + #define OMAP4430_PRM_IRQENABLE_DUCATI			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0028)
+ + #define OMAP4_PRM_IRQSTATUS_TESLA_OFFSET		0x0030
+ + #define OMAP4430_PRM_IRQSTATUS_TESLA			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0030)
+ + #define OMAP4_PRM_IRQENABLE_TESLA_OFFSET		0x0038
+ + #define OMAP4430_PRM_IRQENABLE_TESLA			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0038)
+ + #define OMAP4_CM_PRM_PROFILING_CLKCTRL_OFFSET		0x0040
+ + #define OMAP4430_CM_PRM_PROFILING_CLKCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0040)
+ + 
+ + /* PRM.CKGEN_PRM register offsets */
+ + #define OMAP4_CM_ABE_DSS_SYS_CLKSEL_OFFSET		0x0000
+ + #define OMAP4430_CM_ABE_DSS_SYS_CLKSEL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0000)
+ + #define OMAP4_CM_L4_WKUP_CLKSEL_OFFSET			0x0008
+ + #define OMAP4430_CM_L4_WKUP_CLKSEL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0008)
+ + #define OMAP4_CM_ABE_PLL_REF_CLKSEL_OFFSET		0x000c
+ + #define OMAP4430_CM_ABE_PLL_REF_CLKSEL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x000c)
+ + #define OMAP4_CM_SYS_CLKSEL_OFFSET			0x0010
+ + #define OMAP4430_CM_SYS_CLKSEL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0010)
+ + 
+ + /* PRM.MPU_PRM register offsets */
+ + #define OMAP4_PM_MPU_PWRSTCTRL_OFFSET			0x0000
+ + #define OMAP4430_PM_MPU_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0000)
+ + #define OMAP4_PM_MPU_PWRSTST_OFFSET			0x0004
+ + #define OMAP4430_PM_MPU_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0004)
+ + #define OMAP4_RM_MPU_RSTST_OFFSET			0x0014
+ + #define OMAP4430_RM_MPU_RSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0014)
+ + #define OMAP4_RM_MPU_MPU_CONTEXT_OFFSET			0x0024
+ + #define OMAP4430_RM_MPU_MPU_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0024)
+ + 
+ + /* PRM.TESLA_PRM register offsets */
+ + #define OMAP4_PM_TESLA_PWRSTCTRL_OFFSET			0x0000
+ + #define OMAP4430_PM_TESLA_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0000)
+ + #define OMAP4_PM_TESLA_PWRSTST_OFFSET			0x0004
+ + #define OMAP4430_PM_TESLA_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0004)
+ + #define OMAP4_RM_TESLA_RSTCTRL_OFFSET			0x0010
+ + #define OMAP4430_RM_TESLA_RSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0010)
+ + #define OMAP4_RM_TESLA_RSTST_OFFSET			0x0014
+ + #define OMAP4430_RM_TESLA_RSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0014)
+ + #define OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET		0x0024
+ + #define OMAP4430_RM_TESLA_TESLA_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0024)
+ + 
+ + /* PRM.ABE_PRM register offsets */
+ + #define OMAP4_PM_ABE_PWRSTCTRL_OFFSET			0x0000
+ + #define OMAP4430_PM_ABE_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0000)
+ + #define OMAP4_PM_ABE_PWRSTST_OFFSET			0x0004
+ + #define OMAP4430_PM_ABE_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0004)
+ + #define OMAP4_RM_ABE_AESS_CONTEXT_OFFSET		0x002c
+ + #define OMAP4430_RM_ABE_AESS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x002c)
+ + #define OMAP4_PM_ABE_PDM_WKDEP_OFFSET			0x0030
+ + #define OMAP4430_PM_ABE_PDM_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0030)
+ + #define OMAP4_RM_ABE_PDM_CONTEXT_OFFSET			0x0034
+ + #define OMAP4430_RM_ABE_PDM_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0034)
+ + #define OMAP4_PM_ABE_DMIC_WKDEP_OFFSET			0x0038
+ + #define OMAP4430_PM_ABE_DMIC_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0038)
+ + #define OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET		0x003c
+ + #define OMAP4430_RM_ABE_DMIC_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x003c)
+ + #define OMAP4_PM_ABE_MCASP_WKDEP_OFFSET			0x0040
+ + #define OMAP4430_PM_ABE_MCASP_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0040)
+ + #define OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET		0x0044
+ + #define OMAP4430_RM_ABE_MCASP_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0044)
+ + #define OMAP4_PM_ABE_MCBSP1_WKDEP_OFFSET		0x0048
+ + #define OMAP4430_PM_ABE_MCBSP1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0048)
+ + #define OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET		0x004c
+ + #define OMAP4430_RM_ABE_MCBSP1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x004c)
+ + #define OMAP4_PM_ABE_MCBSP2_WKDEP_OFFSET		0x0050
+ + #define OMAP4430_PM_ABE_MCBSP2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0050)
+ + #define OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET		0x0054
+ + #define OMAP4430_RM_ABE_MCBSP2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0054)
+ + #define OMAP4_PM_ABE_MCBSP3_WKDEP_OFFSET		0x0058
+ + #define OMAP4430_PM_ABE_MCBSP3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0058)
+ + #define OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET		0x005c
+ + #define OMAP4430_RM_ABE_MCBSP3_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x005c)
+ + #define OMAP4_PM_ABE_SLIMBUS_WKDEP_OFFSET		0x0060
+ + #define OMAP4430_PM_ABE_SLIMBUS_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0060)
+ + #define OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET		0x0064
+ + #define OMAP4430_RM_ABE_SLIMBUS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0064)
+ + #define OMAP4_PM_ABE_TIMER5_WKDEP_OFFSET		0x0068
+ + #define OMAP4430_PM_ABE_TIMER5_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0068)
+ + #define OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET		0x006c
+ + #define OMAP4430_RM_ABE_TIMER5_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x006c)
+ + #define OMAP4_PM_ABE_TIMER6_WKDEP_OFFSET		0x0070
+ + #define OMAP4430_PM_ABE_TIMER6_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0070)
+ + #define OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET		0x0074
+ + #define OMAP4430_RM_ABE_TIMER6_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0074)
+ + #define OMAP4_PM_ABE_TIMER7_WKDEP_OFFSET		0x0078
+ + #define OMAP4430_PM_ABE_TIMER7_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0078)
+ + #define OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET		0x007c
+ + #define OMAP4430_RM_ABE_TIMER7_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x007c)
+ + #define OMAP4_PM_ABE_TIMER8_WKDEP_OFFSET		0x0080
+ + #define OMAP4430_PM_ABE_TIMER8_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0080)
+ + #define OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET		0x0084
+ + #define OMAP4430_RM_ABE_TIMER8_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0084)
+ + #define OMAP4_PM_ABE_WDT3_WKDEP_OFFSET			0x0088
+ + #define OMAP4430_PM_ABE_WDT3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0088)
+ + #define OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET		0x008c
+ + #define OMAP4430_RM_ABE_WDT3_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x008c)
+ + 
+ + /* PRM.ALWAYS_ON_PRM register offsets */
+ + #define OMAP4_RM_ALWON_MDMINTC_CONTEXT_OFFSET		0x0024
+ + #define OMAP4430_RM_ALWON_MDMINTC_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0024)
+ + #define OMAP4_PM_ALWON_SR_MPU_WKDEP_OFFSET		0x0028
+ + #define OMAP4430_PM_ALWON_SR_MPU_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0028)
+ + #define OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET		0x002c
+ + #define OMAP4430_RM_ALWON_SR_MPU_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x002c)
+ + #define OMAP4_PM_ALWON_SR_IVA_WKDEP_OFFSET		0x0030
+ + #define OMAP4430_PM_ALWON_SR_IVA_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0030)
+ + #define OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET		0x0034
+ + #define OMAP4430_RM_ALWON_SR_IVA_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0034)
+ + #define OMAP4_PM_ALWON_SR_CORE_WKDEP_OFFSET		0x0038
+ + #define OMAP4430_PM_ALWON_SR_CORE_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0038)
+ + #define OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET		0x003c
+ + #define OMAP4430_RM_ALWON_SR_CORE_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x003c)
+ + 
+ + /* PRM.CORE_PRM register offsets */
+ + #define OMAP4_PM_CORE_PWRSTCTRL_OFFSET			0x0000
+ + #define OMAP4430_PM_CORE_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0000)
+ + #define OMAP4_PM_CORE_PWRSTST_OFFSET			0x0004
+ + #define OMAP4430_PM_CORE_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0004)
+ + #define OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET		0x0024
+ + #define OMAP4430_RM_L3_1_L3_1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0024)
+ + #define OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET		0x0124
+ + #define OMAP4430_RM_L3_2_L3_2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0124)
+ + #define OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET		0x012c
+ + #define OMAP4430_RM_L3_2_GPMC_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x012c)
+ + #define OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET		0x0134
+ + #define OMAP4430_RM_L3_2_OCMC_RAM_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0134)
+ + #define OMAP4_RM_DUCATI_RSTCTRL_OFFSET			0x0210
+ + #define OMAP4430_RM_DUCATI_RSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0210)
+ + #define OMAP4_RM_DUCATI_RSTST_OFFSET			0x0214
+ + #define OMAP4430_RM_DUCATI_RSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0214)
+ + #define OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET		0x0224
+ + #define OMAP4430_RM_DUCATI_DUCATI_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0224)
+ + #define OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET		0x0324
+ + #define OMAP4430_RM_SDMA_SDMA_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0324)
+ + #define OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET		0x0424
+ + #define OMAP4430_RM_MEMIF_DMM_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0424)
+ + #define OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET		0x042c
+ + #define OMAP4430_RM_MEMIF_EMIF_FW_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x042c)
+ + #define OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET		0x0434
+ + #define OMAP4430_RM_MEMIF_EMIF_1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0434)
+ + #define OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET		0x043c
+ + #define OMAP4430_RM_MEMIF_EMIF_2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x043c)
+ + #define OMAP4_RM_MEMIF_DLL_CONTEXT_OFFSET		0x0444
+ + #define OMAP4430_RM_MEMIF_DLL_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0444)
+ + #define OMAP4_RM_MEMIF_EMIF_H1_CONTEXT_OFFSET		0x0454
+ + #define OMAP4430_RM_MEMIF_EMIF_H1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0454)
+ + #define OMAP4_RM_MEMIF_EMIF_H2_CONTEXT_OFFSET		0x045c
+ + #define OMAP4430_RM_MEMIF_EMIF_H2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x045c)
+ + #define OMAP4_RM_MEMIF_DLL_H_CONTEXT_OFFSET		0x0464
+ + #define OMAP4430_RM_MEMIF_DLL_H_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0464)
+ + #define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET		0x0524
+ + #define OMAP4430_RM_D2D_SAD2D_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0524)
+ + #define OMAP4_RM_D2D_MODEM_ICR_CONTEXT_OFFSET		0x052c
+ + #define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x052c)
+ + #define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET		0x0534
+ + #define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0534)
+ + #define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET		0x0624
+ + #define OMAP4430_RM_L4CFG_L4_CFG_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0624)
+ + #define OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET		0x062c
+ + #define OMAP4430_RM_L4CFG_HW_SEM_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x062c)
+ + #define OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET		0x0634
+ + #define OMAP4430_RM_L4CFG_MAILBOX_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0634)
+ + #define OMAP4_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET		0x063c
+ + #define OMAP4430_RM_L4CFG_SAR_ROM_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x063c)
+ + #define OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET		0x0724
+ + #define OMAP4430_RM_L3INSTR_L3_3_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0724)
+ + #define OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET	0x072c
+ + #define OMAP4430_RM_L3INSTR_L3_INSTR_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x072c)
+ + #define OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET		0x0744
+ + #define OMAP4430_RM_L3INSTR_OCP_WP1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0744)
+ + 
+ + /* PRM.IVAHD_PRM register offsets */
+ + #define OMAP4_PM_IVAHD_PWRSTCTRL_OFFSET			0x0000
+ + #define OMAP4430_PM_IVAHD_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0000)
+ + #define OMAP4_PM_IVAHD_PWRSTST_OFFSET			0x0004
+ + #define OMAP4430_PM_IVAHD_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0004)
+ + #define OMAP4_RM_IVAHD_RSTCTRL_OFFSET			0x0010
+ + #define OMAP4430_RM_IVAHD_RSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0010)
+ + #define OMAP4_RM_IVAHD_RSTST_OFFSET			0x0014
+ + #define OMAP4430_RM_IVAHD_RSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0014)
+ + #define OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET		0x0024
+ + #define OMAP4430_RM_IVAHD_IVAHD_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0024)
+ + #define OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET		0x002c
+ + #define OMAP4430_RM_IVAHD_SL2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x002c)
+ + 
+ + /* PRM.CAM_PRM register offsets */
+ + #define OMAP4_PM_CAM_PWRSTCTRL_OFFSET			0x0000
+ + #define OMAP4430_PM_CAM_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0000)
+ + #define OMAP4_PM_CAM_PWRSTST_OFFSET			0x0004
+ + #define OMAP4430_PM_CAM_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0004)
+ + #define OMAP4_RM_CAM_ISS_CONTEXT_OFFSET			0x0024
+ + #define OMAP4430_RM_CAM_ISS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0024)
+ + #define OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET		0x002c
+ + #define OMAP4430_RM_CAM_FDIF_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x002c)
+ + 
+ + /* PRM.DSS_PRM register offsets */
+ + #define OMAP4_PM_DSS_PWRSTCTRL_OFFSET			0x0000
+ + #define OMAP4430_PM_DSS_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0000)
+ + #define OMAP4_PM_DSS_PWRSTST_OFFSET			0x0004
+ + #define OMAP4430_PM_DSS_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0004)
+ + #define OMAP4_PM_DSS_DSS_WKDEP_OFFSET			0x0020
+ + #define OMAP4430_PM_DSS_DSS_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0020)
+ + #define OMAP4_RM_DSS_DSS_CONTEXT_OFFSET			0x0024
+ + #define OMAP4430_RM_DSS_DSS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0024)
+ + #define OMAP4_RM_DSS_DEISS_CONTEXT_OFFSET		0x002c
+ + #define OMAP4430_RM_DSS_DEISS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x002c)
+ + 
+ + /* PRM.GFX_PRM register offsets */
+ + #define OMAP4_PM_GFX_PWRSTCTRL_OFFSET			0x0000
+ + #define OMAP4430_PM_GFX_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0000)
+ + #define OMAP4_PM_GFX_PWRSTST_OFFSET			0x0004
+ + #define OMAP4430_PM_GFX_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0004)
+ + #define OMAP4_RM_GFX_GFX_CONTEXT_OFFSET			0x0024
+ + #define OMAP4430_RM_GFX_GFX_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0024)
+ + 
+ + /* PRM.L3INIT_PRM register offsets */
+ + #define OMAP4_PM_L3INIT_PWRSTCTRL_OFFSET		0x0000
+ + #define OMAP4430_PM_L3INIT_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0000)
+ + #define OMAP4_PM_L3INIT_PWRSTST_OFFSET			0x0004
+ + #define OMAP4430_PM_L3INIT_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0004)
+ + #define OMAP4_PM_L3INIT_MMC1_WKDEP_OFFSET		0x0028
+ + #define OMAP4430_PM_L3INIT_MMC1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0028)
+ + #define OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET		0x002c
+ + #define OMAP4430_RM_L3INIT_MMC1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x002c)
+ + #define OMAP4_PM_L3INIT_MMC2_WKDEP_OFFSET		0x0030
+ + #define OMAP4430_PM_L3INIT_MMC2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0030)
+ + #define OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET		0x0034
+ + #define OMAP4430_RM_L3INIT_MMC2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0034)
+ + #define OMAP4_PM_L3INIT_HSI_WKDEP_OFFSET		0x0038
+ + #define OMAP4430_PM_L3INIT_HSI_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0038)
+ + #define OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET		0x003c
+ + #define OMAP4430_RM_L3INIT_HSI_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x003c)
+ + #define OMAP4_PM_L3INIT_UNIPRO1_WKDEP_OFFSET		0x0040
+ + #define OMAP4430_PM_L3INIT_UNIPRO1_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0040)
+ + #define OMAP4_RM_L3INIT_UNIPRO1_CONTEXT_OFFSET		0x0044
+ + #define OMAP4430_RM_L3INIT_UNIPRO1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0044)
+ + #define OMAP4_PM_L3INIT_USB_HOST_WKDEP_OFFSET		0x0058
+ + #define OMAP4430_PM_L3INIT_USB_HOST_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0058)
+ + #define OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET		0x005c
+ + #define OMAP4430_RM_L3INIT_USB_HOST_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x005c)
+ + #define OMAP4_PM_L3INIT_USB_OTG_WKDEP_OFFSET		0x0060
+ + #define OMAP4430_PM_L3INIT_USB_OTG_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0060)
+ + #define OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET		0x0064
+ + #define OMAP4430_RM_L3INIT_USB_OTG_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0064)
+ + #define OMAP4_PM_L3INIT_USB_TLL_WKDEP_OFFSET		0x0068
+ + #define OMAP4430_PM_L3INIT_USB_TLL_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0068)
+ + #define OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET		0x006c
+ + #define OMAP4430_RM_L3INIT_USB_TLL_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x006c)
+ + #define OMAP4_RM_L3INIT_P1500_CONTEXT_OFFSET		0x007c
+ + #define OMAP4430_RM_L3INIT_P1500_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x007c)
+ + #define OMAP4_RM_L3INIT_EMAC_CONTEXT_OFFSET		0x0084
+ + #define OMAP4430_RM_L3INIT_EMAC_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0084)
+ + #define OMAP4_PM_L3INIT_SATA_WKDEP_OFFSET		0x0088
+ + #define OMAP4430_PM_L3INIT_SATA_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0088)
+ + #define OMAP4_RM_L3INIT_SATA_CONTEXT_OFFSET		0x008c
+ + #define OMAP4430_RM_L3INIT_SATA_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x008c)
+ + #define OMAP4_RM_L3INIT_TPPSS_CONTEXT_OFFSET		0x0094
+ + #define OMAP4430_RM_L3INIT_TPPSS_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0094)
+ + #define OMAP4_PM_L3INIT_PCIESS_WKDEP_OFFSET		0x0098
+ + #define OMAP4430_PM_L3INIT_PCIESS_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0098)
+ + #define OMAP4_RM_L3INIT_PCIESS_CONTEXT_OFFSET		0x009c
+ + #define OMAP4430_RM_L3INIT_PCIESS_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x009c)
+ + #define OMAP4_RM_L3INIT_CCPTX_CONTEXT_OFFSET		0x00ac
+ + #define OMAP4430_RM_L3INIT_CCPTX_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00ac)
+ + #define OMAP4_PM_L3INIT_XHPI_WKDEP_OFFSET		0x00c0
+ + #define OMAP4430_PM_L3INIT_XHPI_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c0)
+ + #define OMAP4_RM_L3INIT_XHPI_CONTEXT_OFFSET		0x00c4
+ + #define OMAP4430_RM_L3INIT_XHPI_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c4)
+ + #define OMAP4_PM_L3INIT_MMC6_WKDEP_OFFSET		0x00c8
+ + #define OMAP4430_PM_L3INIT_MMC6_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c8)
+ + #define OMAP4_RM_L3INIT_MMC6_CONTEXT_OFFSET		0x00cc
+ + #define OMAP4430_RM_L3INIT_MMC6_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00cc)
+ + #define OMAP4_PM_L3INIT_USB_HOST_FS_WKDEP_OFFSET	0x00d0
+ + #define OMAP4430_PM_L3INIT_USB_HOST_FS_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00d0)
+ + #define OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET	0x00d4
+ + #define OMAP4430_RM_L3INIT_USB_HOST_FS_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00d4)
+ + #define OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET	0x00e4
+ + #define OMAP4430_RM_L3INIT_USBPHYOCP2SCP_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00e4)
+ + 
+ + /* PRM.L4PER_PRM register offsets */
+ + #define OMAP4_PM_L4PER_PWRSTCTRL_OFFSET			0x0000
+ + #define OMAP4430_PM_L4PER_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0000)
+ + #define OMAP4_PM_L4PER_PWRSTST_OFFSET			0x0004
+ + #define OMAP4430_PM_L4PER_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0004)
+ + #define OMAP4_RM_L4PER_ADC_CONTEXT_OFFSET		0x0024
+ + #define OMAP4430_RM_L4PER_ADC_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0024)
+ + #define OMAP4_PM_L4PER_DMTIMER10_WKDEP_OFFSET		0x0028
+ + #define OMAP4430_PM_L4PER_DMTIMER10_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0028)
+ + #define OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET		0x002c
+ + #define OMAP4430_RM_L4PER_DMTIMER10_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x002c)
+ + #define OMAP4_PM_L4PER_DMTIMER11_WKDEP_OFFSET		0x0030
+ + #define OMAP4430_PM_L4PER_DMTIMER11_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0030)
+ + #define OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET		0x0034
+ + #define OMAP4430_RM_L4PER_DMTIMER11_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0034)
+ + #define OMAP4_PM_L4PER_DMTIMER2_WKDEP_OFFSET		0x0038
+ + #define OMAP4430_PM_L4PER_DMTIMER2_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0038)
+ + #define OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET		0x003c
+ + #define OMAP4430_RM_L4PER_DMTIMER2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x003c)
+ + #define OMAP4_PM_L4PER_DMTIMER3_WKDEP_OFFSET		0x0040
+ + #define OMAP4430_PM_L4PER_DMTIMER3_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0040)
+ + #define OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET		0x0044
+ + #define OMAP4430_RM_L4PER_DMTIMER3_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0044)
+ + #define OMAP4_PM_L4PER_DMTIMER4_WKDEP_OFFSET		0x0048
+ + #define OMAP4430_PM_L4PER_DMTIMER4_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0048)
+ + #define OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET		0x004c
+ + #define OMAP4430_RM_L4PER_DMTIMER4_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x004c)
+ + #define OMAP4_PM_L4PER_DMTIMER9_WKDEP_OFFSET		0x0050
+ + #define OMAP4430_PM_L4PER_DMTIMER9_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0050)
+ + #define OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET		0x0054
+ + #define OMAP4430_RM_L4PER_DMTIMER9_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0054)
+ + #define OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET		0x005c
+ + #define OMAP4430_RM_L4PER_ELM_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x005c)
+ + #define OMAP4_PM_L4PER_GPIO2_WKDEP_OFFSET		0x0060
+ + #define OMAP4430_PM_L4PER_GPIO2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0060)
+ + #define OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET		0x0064
+ + #define OMAP4430_RM_L4PER_GPIO2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0064)
+ + #define OMAP4_PM_L4PER_GPIO3_WKDEP_OFFSET		0x0068
+ + #define OMAP4430_PM_L4PER_GPIO3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0068)
+ + #define OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET		0x006c
+ + #define OMAP4430_RM_L4PER_GPIO3_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x006c)
+ + #define OMAP4_PM_L4PER_GPIO4_WKDEP_OFFSET		0x0070
+ + #define OMAP4430_PM_L4PER_GPIO4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0070)
+ + #define OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET		0x0074
+ + #define OMAP4430_RM_L4PER_GPIO4_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0074)
+ + #define OMAP4_PM_L4PER_GPIO5_WKDEP_OFFSET		0x0078
+ + #define OMAP4430_PM_L4PER_GPIO5_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0078)
+ + #define OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET		0x007c
+ + #define OMAP4430_RM_L4PER_GPIO5_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x007c)
+ + #define OMAP4_PM_L4PER_GPIO6_WKDEP_OFFSET		0x0080
+ + #define OMAP4430_PM_L4PER_GPIO6_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0080)
+ + #define OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET		0x0084
+ + #define OMAP4430_RM_L4PER_GPIO6_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0084)
+ + #define OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET		0x008c
+ + #define OMAP4430_RM_L4PER_HDQ1W_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x008c)
+ + #define OMAP4_PM_L4PER_HECC1_WKDEP_OFFSET		0x0090
+ + #define OMAP4430_PM_L4PER_HECC1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0090)
+ + #define OMAP4_RM_L4PER_HECC1_CONTEXT_OFFSET		0x0094
+ + #define OMAP4430_RM_L4PER_HECC1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0094)
+ + #define OMAP4_PM_L4PER_HECC2_WKDEP_OFFSET		0x0098
+ + #define OMAP4430_PM_L4PER_HECC2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0098)
+ + #define OMAP4_RM_L4PER_HECC2_CONTEXT_OFFSET		0x009c
+ + #define OMAP4430_RM_L4PER_HECC2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x009c)
+ + #define OMAP4_PM_L4PER_I2C1_WKDEP_OFFSET		0x00a0
+ + #define OMAP4430_PM_L4PER_I2C1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a0)
+ + #define OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET		0x00a4
+ + #define OMAP4430_RM_L4PER_I2C1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a4)
+ + #define OMAP4_PM_L4PER_I2C2_WKDEP_OFFSET		0x00a8
+ + #define OMAP4430_PM_L4PER_I2C2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a8)
+ + #define OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET		0x00ac
+ + #define OMAP4430_RM_L4PER_I2C2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00ac)
+ + #define OMAP4_PM_L4PER_I2C3_WKDEP_OFFSET		0x00b0
+ + #define OMAP4430_PM_L4PER_I2C3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b0)
+ + #define OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET		0x00b4
+ + #define OMAP4430_RM_L4PER_I2C3_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b4)
+ + #define OMAP4_PM_L4PER_I2C4_WKDEP_OFFSET		0x00b8
+ + #define OMAP4430_PM_L4PER_I2C4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b8)
+ + #define OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET		0x00bc
+ + #define OMAP4430_RM_L4PER_I2C4_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00bc)
+ + #define OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET		0x00c0
+ + #define OMAP4430_RM_L4PER_L4_PER_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00c0)
+ + #define OMAP4_PM_L4PER_MCASP2_WKDEP_OFFSET		0x00d0
+ + #define OMAP4430_PM_L4PER_MCASP2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d0)
+ + #define OMAP4_RM_L4PER_MCASP2_CONTEXT_OFFSET		0x00d4
+ + #define OMAP4430_RM_L4PER_MCASP2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d4)
+ + #define OMAP4_PM_L4PER_MCASP3_WKDEP_OFFSET		0x00d8
+ + #define OMAP4430_PM_L4PER_MCASP3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d8)
+ + #define OMAP4_RM_L4PER_MCASP3_CONTEXT_OFFSET		0x00dc
+ + #define OMAP4430_RM_L4PER_MCASP3_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00dc)
+ + #define OMAP4_PM_L4PER_MCBSP4_WKDEP_OFFSET		0x00e0
+ + #define OMAP4430_PM_L4PER_MCBSP4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00e0)
+ + #define OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET		0x00e4
+ + #define OMAP4430_RM_L4PER_MCBSP4_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00e4)
+ + #define OMAP4_RM_L4PER_MGATE_CONTEXT_OFFSET		0x00ec
+ + #define OMAP4430_RM_L4PER_MGATE_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00ec)
+ + #define OMAP4_PM_L4PER_MCSPI1_WKDEP_OFFSET		0x00f0
+ + #define OMAP4430_PM_L4PER_MCSPI1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f0)
+ + #define OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET		0x00f4
+ + #define OMAP4430_RM_L4PER_MCSPI1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f4)
+ + #define OMAP4_PM_L4PER_MCSPI2_WKDEP_OFFSET		0x00f8
+ + #define OMAP4430_PM_L4PER_MCSPI2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f8)
+ + #define OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET		0x00fc
+ + #define OMAP4430_RM_L4PER_MCSPI2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00fc)
+ + #define OMAP4_PM_L4PER_MCSPI3_WKDEP_OFFSET		0x0100
+ + #define OMAP4430_PM_L4PER_MCSPI3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0100)
+ + #define OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET		0x0104
+ + #define OMAP4430_RM_L4PER_MCSPI3_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0104)
+ + #define OMAP4_PM_L4PER_MCSPI4_WKDEP_OFFSET		0x0108
+ + #define OMAP4430_PM_L4PER_MCSPI4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0108)
+ + #define OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET		0x010c
+ + #define OMAP4430_RM_L4PER_MCSPI4_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x010c)
+ + #define OMAP4_PM_L4PER_MMCSD3_WKDEP_OFFSET		0x0120
+ + #define OMAP4430_PM_L4PER_MMCSD3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0120)
+ + #define OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET		0x0124
+ + #define OMAP4430_RM_L4PER_MMCSD3_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0124)
+ + #define OMAP4_PM_L4PER_MMCSD4_WKDEP_OFFSET		0x0128
+ + #define OMAP4430_PM_L4PER_MMCSD4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0128)
+ + #define OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET		0x012c
+ + #define OMAP4430_RM_L4PER_MMCSD4_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x012c)
+ + #define OMAP4_RM_L4PER_MSPROHG_CONTEXT_OFFSET		0x0134
+ + #define OMAP4430_RM_L4PER_MSPROHG_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0134)
+ + #define OMAP4_PM_L4PER_SLIMBUS2_WKDEP_OFFSET		0x0138
+ + #define OMAP4430_PM_L4PER_SLIMBUS2_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0138)
+ + #define OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET		0x013c
+ + #define OMAP4430_RM_L4PER_SLIMBUS2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x013c)
+ + #define OMAP4_PM_L4PER_UART1_WKDEP_OFFSET		0x0140
+ + #define OMAP4430_PM_L4PER_UART1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0140)
+ + #define OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET		0x0144
+ + #define OMAP4430_RM_L4PER_UART1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0144)
+ + #define OMAP4_PM_L4PER_UART2_WKDEP_OFFSET		0x0148
+ + #define OMAP4430_PM_L4PER_UART2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0148)
+ + #define OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET		0x014c
+ + #define OMAP4430_RM_L4PER_UART2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x014c)
+ + #define OMAP4_PM_L4PER_UART3_WKDEP_OFFSET		0x0150
+ + #define OMAP4430_PM_L4PER_UART3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0150)
+ + #define OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET		0x0154
+ + #define OMAP4430_RM_L4PER_UART3_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0154)
+ + #define OMAP4_PM_L4PER_UART4_WKDEP_OFFSET		0x0158
+ + #define OMAP4430_PM_L4PER_UART4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0158)
+ + #define OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET		0x015c
+ + #define OMAP4430_RM_L4PER_UART4_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x015c)
+ + #define OMAP4_PM_L4PER_MMCSD5_WKDEP_OFFSET		0x0160
+ + #define OMAP4430_PM_L4PER_MMCSD5_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0160)
+ + #define OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET		0x0164
+ + #define OMAP4430_RM_L4PER_MMCSD5_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0164)
+ + #define OMAP4_PM_L4PER_I2C5_WKDEP_OFFSET		0x0168
+ + #define OMAP4430_PM_L4PER_I2C5_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0168)
+ + #define OMAP4_RM_L4PER_I2C5_CONTEXT_OFFSET		0x016c
+ + #define OMAP4430_RM_L4PER_I2C5_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x016c)
+ + #define OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET		0x01a4
+ + #define OMAP4430_RM_L4SEC_AES1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01a4)
+ + #define OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET		0x01ac
+ + #define OMAP4430_RM_L4SEC_AES2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01ac)
+ + #define OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET		0x01b4
+ + #define OMAP4430_RM_L4SEC_DES3DES_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01b4)
+ + #define OMAP4_RM_L4SEC_PKAEIP29_CONTEXT_OFFSET		0x01bc
+ + #define OMAP4430_RM_L4SEC_PKAEIP29_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01bc)
+ + #define OMAP4_RM_L4SEC_RNG_CONTEXT_OFFSET		0x01c4
+ + #define OMAP4430_RM_L4SEC_RNG_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01c4)
+ + #define OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET		0x01cc
+ + #define OMAP4430_RM_L4SEC_SHA2MD51_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01cc)
+ + #define OMAP4_RM_L4SEC_CRYPTODMA_CONTEXT_OFFSET		0x01dc
+ + #define OMAP4430_RM_L4SEC_CRYPTODMA_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01dc)
+ + 
+ + /* PRM.CEFUSE_PRM register offsets */
+ + #define OMAP4_PM_CEFUSE_PWRSTCTRL_OFFSET		0x0000
+ + #define OMAP4430_PM_CEFUSE_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0000)
+ + #define OMAP4_PM_CEFUSE_PWRSTST_OFFSET			0x0004
+ + #define OMAP4430_PM_CEFUSE_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0004)
+ + #define OMAP4_RM_CEFUSE_CEFUSE_CONTEXT_OFFSET		0x0024
+ + #define OMAP4430_RM_CEFUSE_CEFUSE_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0024)
+ + 
+ + /* PRM.WKUP_PRM register offsets */
+ + #define OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET		0x0024
+ + #define OMAP4430_RM_WKUP_L4WKUP_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0024)
+ + #define OMAP4_RM_WKUP_WDT1_CONTEXT_OFFSET		0x002c
+ + #define OMAP4430_RM_WKUP_WDT1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x002c)
+ + #define OMAP4_PM_WKUP_WDT2_WKDEP_OFFSET			0x0030
+ + #define OMAP4430_PM_WKUP_WDT2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0030)
+ + #define OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET		0x0034
+ + #define OMAP4430_RM_WKUP_WDT2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0034)
+ + #define OMAP4_PM_WKUP_GPIO1_WKDEP_OFFSET		0x0038
+ + #define OMAP4430_PM_WKUP_GPIO1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0038)
+ + #define OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET		0x003c
+ + #define OMAP4430_RM_WKUP_GPIO1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x003c)
+ + #define OMAP4_PM_WKUP_TIMER1_WKDEP_OFFSET		0x0040
+ + #define OMAP4430_PM_WKUP_TIMER1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0040)
+ + #define OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET		0x0044
+ + #define OMAP4430_RM_WKUP_TIMER1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0044)
+ + #define OMAP4_PM_WKUP_TIMER12_WKDEP_OFFSET		0x0048
+ + #define OMAP4430_PM_WKUP_TIMER12_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0048)
+ + #define OMAP4_RM_WKUP_TIMER12_CONTEXT_OFFSET		0x004c
+ + #define OMAP4430_RM_WKUP_TIMER12_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x004c)
+ + #define OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET		0x0054
+ + #define OMAP4430_RM_WKUP_SYNCTIMER_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0054)
+ + #define OMAP4_PM_WKUP_USIM_WKDEP_OFFSET			0x0058
+ + #define OMAP4430_PM_WKUP_USIM_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0058)
+ + #define OMAP4_RM_WKUP_USIM_CONTEXT_OFFSET		0x005c
+ + #define OMAP4430_RM_WKUP_USIM_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x005c)
+ + #define OMAP4_RM_WKUP_SARRAM_CONTEXT_OFFSET		0x0064
+ + #define OMAP4430_RM_WKUP_SARRAM_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0064)
+ + #define OMAP4_PM_WKUP_KEYBOARD_WKDEP_OFFSET		0x0078
+ + #define OMAP4430_PM_WKUP_KEYBOARD_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0078)
+ + #define OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET		0x007c
+ + #define OMAP4430_RM_WKUP_KEYBOARD_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x007c)
+ + #define OMAP4_PM_WKUP_RTC_WKDEP_OFFSET			0x0080
+ + #define OMAP4430_PM_WKUP_RTC_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0080)
+ + #define OMAP4_RM_WKUP_RTC_CONTEXT_OFFSET		0x0084
+ + #define OMAP4430_RM_WKUP_RTC_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0084)
+ + 
+ + /* PRM.WKUP_CM register offsets */
+ + #define OMAP4_CM_WKUP_CLKSTCTRL_OFFSET			0x0000
+ + #define OMAP4430_CM_WKUP_CLKSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0000)
+ + #define OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET		0x0020
+ + #define OMAP4430_CM_WKUP_L4WKUP_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0020)
+ + #define OMAP4_CM_WKUP_WDT1_CLKCTRL_OFFSET		0x0028
+ + #define OMAP4430_CM_WKUP_WDT1_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0028)
+ + #define OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET		0x0030
+ + #define OMAP4430_CM_WKUP_WDT2_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0030)
+ + #define OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET		0x0038
+ + #define OMAP4430_CM_WKUP_GPIO1_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0038)
+ + #define OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET		0x0040
+ + #define OMAP4430_CM_WKUP_TIMER1_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0040)
+ + #define OMAP4_CM_WKUP_TIMER12_CLKCTRL_OFFSET		0x0048
+ + #define OMAP4430_CM_WKUP_TIMER12_CLKCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0048)
+ + #define OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET		0x0050
+ + #define OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0050)
+ + #define OMAP4_CM_WKUP_USIM_CLKCTRL_OFFSET		0x0058
+ + #define OMAP4430_CM_WKUP_USIM_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0058)
+ + #define OMAP4_CM_WKUP_SARRAM_CLKCTRL_OFFSET		0x0060
+ + #define OMAP4430_CM_WKUP_SARRAM_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0060)
+ + #define OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET		0x0078
+ + #define OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0078)
+ + #define OMAP4_CM_WKUP_RTC_CLKCTRL_OFFSET		0x0080
+ + #define OMAP4430_CM_WKUP_RTC_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0080)
+ + #define OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET		0x0088
+ + #define OMAP4430_CM_WKUP_BANDGAP_CLKCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0088)
+ + 
+ + /* PRM.EMU_PRM register offsets */
+ + #define OMAP4_PM_EMU_PWRSTCTRL_OFFSET			0x0000
+ + #define OMAP4430_PM_EMU_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0000)
+ + #define OMAP4_PM_EMU_PWRSTST_OFFSET			0x0004
+ + #define OMAP4430_PM_EMU_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0004)
+ + #define OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET		0x0024
+ + #define OMAP4430_RM_EMU_DEBUGSS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0024)
+ + 
+ + /* PRM.EMU_CM register offsets */
+ + #define OMAP4_CM_EMU_CLKSTCTRL_OFFSET			0x0000
+ + #define OMAP4430_CM_EMU_CLKSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0000)
+ + #define OMAP4_CM_EMU_DYNAMICDEP_OFFSET			0x0008
+ + #define OMAP4430_CM_EMU_DYNAMICDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0008)
+ + #define OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET		0x0020
+ + #define OMAP4430_CM_EMU_DEBUGSS_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0020)
+ + 
+ + /* PRM.DEVICE_PRM register offsets */
+ + #define OMAP4_PRM_RSTCTRL_OFFSET			0x0000
+ + #define OMAP4430_PRM_RSTCTRL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0000)
+ + #define OMAP4_PRM_RSTST_OFFSET				0x0004
+ + #define OMAP4430_PRM_RSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0004)
+ + #define OMAP4_PRM_RSTTIME_OFFSET			0x0008
+ + #define OMAP4430_PRM_RSTTIME				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0008)
+ + #define OMAP4_PRM_CLKREQCTRL_OFFSET			0x000c
+ + #define OMAP4430_PRM_CLKREQCTRL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x000c)
+ + #define OMAP4_PRM_VOLTCTRL_OFFSET			0x0010
+ + #define OMAP4430_PRM_VOLTCTRL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0010)
+ + #define OMAP4_PRM_PWRREQCTRL_OFFSET			0x0014
+ + #define OMAP4430_PRM_PWRREQCTRL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0014)
+ + #define OMAP4_PRM_PSCON_COUNT_OFFSET			0x0018
+ + #define OMAP4430_PRM_PSCON_COUNT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0018)
+ + #define OMAP4_PRM_IO_COUNT_OFFSET			0x001c
+ + #define OMAP4430_PRM_IO_COUNT				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x001c)
+ + #define OMAP4_PRM_IO_PMCTRL_OFFSET			0x0020
+ + #define OMAP4430_PRM_IO_PMCTRL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0020)
+ + #define OMAP4_PRM_VOLTSETUP_WARMRESET_OFFSET		0x0024
+ + #define OMAP4430_PRM_VOLTSETUP_WARMRESET		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0024)
+ + #define OMAP4_PRM_VOLTSETUP_CORE_OFF_OFFSET		0x0028
+ + #define OMAP4430_PRM_VOLTSETUP_CORE_OFF			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0028)
+ + #define OMAP4_PRM_VOLTSETUP_MPU_OFF_OFFSET		0x002c
+ + #define OMAP4430_PRM_VOLTSETUP_MPU_OFF			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x002c)
+ + #define OMAP4_PRM_VOLTSETUP_IVA_OFF_OFFSET		0x0030
+ + #define OMAP4430_PRM_VOLTSETUP_IVA_OFF			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0030)
+ + #define OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET	0x0034
+ + #define OMAP4430_PRM_VOLTSETUP_CORE_RET_SLEEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0034)
+ + #define OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET	0x0038
+ + #define OMAP4430_PRM_VOLTSETUP_MPU_RET_SLEEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0038)
+ + #define OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET	0x003c
+ + #define OMAP4430_PRM_VOLTSETUP_IVA_RET_SLEEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x003c)
+ + #define OMAP4_PRM_VP_CORE_CONFIG_OFFSET			0x0040
+ + #define OMAP4430_PRM_VP_CORE_CONFIG			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0040)
+ + #define OMAP4_PRM_VP_CORE_STATUS_OFFSET			0x0044
+ + #define OMAP4430_PRM_VP_CORE_STATUS			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0044)
+ + #define OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET		0x0048
+ + #define OMAP4430_PRM_VP_CORE_VLIMITTO			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0048)
+ + #define OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET		0x004c
+ + #define OMAP4430_PRM_VP_CORE_VOLTAGE			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x004c)
+ + #define OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET		0x0050
+ + #define OMAP4430_PRM_VP_CORE_VSTEPMAX			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0050)
+ + #define OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET		0x0054
+ + #define OMAP4430_PRM_VP_CORE_VSTEPMIN			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0054)
+ + #define OMAP4_PRM_VP_MPU_CONFIG_OFFSET			0x0058
+ + #define OMAP4430_PRM_VP_MPU_CONFIG			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0058)
+ + #define OMAP4_PRM_VP_MPU_STATUS_OFFSET			0x005c
+ + #define OMAP4430_PRM_VP_MPU_STATUS			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x005c)
+ + #define OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET		0x0060
+ + #define OMAP4430_PRM_VP_MPU_VLIMITTO			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0060)
+ + #define OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET			0x0064
+ + #define OMAP4430_PRM_VP_MPU_VOLTAGE			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0064)
+ + #define OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET		0x0068
+ + #define OMAP4430_PRM_VP_MPU_VSTEPMAX			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0068)
+ + #define OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET		0x006c
+ + #define OMAP4430_PRM_VP_MPU_VSTEPMIN			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x006c)
+ + #define OMAP4_PRM_VP_IVA_CONFIG_OFFSET			0x0070
+ + #define OMAP4430_PRM_VP_IVA_CONFIG			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0070)
+ + #define OMAP4_PRM_VP_IVA_STATUS_OFFSET			0x0074
+ + #define OMAP4430_PRM_VP_IVA_STATUS			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0074)
+ + #define OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET		0x0078
+ + #define OMAP4430_PRM_VP_IVA_VLIMITTO			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0078)
+ + #define OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET			0x007c
+ + #define OMAP4430_PRM_VP_IVA_VOLTAGE			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x007c)
+ + #define OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET		0x0080
+ + #define OMAP4430_PRM_VP_IVA_VSTEPMAX			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0080)
+ + #define OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET		0x0084
+ + #define OMAP4430_PRM_VP_IVA_VSTEPMIN			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0084)
+ + #define OMAP4_PRM_VC_SMPS_SA_OFFSET			0x0088
+ + #define OMAP4430_PRM_VC_SMPS_SA				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0088)
+ + #define OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET		0x008c
+ + #define OMAP4430_PRM_VC_VAL_SMPS_RA_VOL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x008c)
+ + #define OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET		0x0090
+ + #define OMAP4430_PRM_VC_VAL_SMPS_RA_CMD			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0090)
+ + #define OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET		0x0094
+ + #define OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0094)
+ + #define OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET		0x0098
+ + #define OMAP4430_PRM_VC_VAL_CMD_VDD_MPU_L		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0098)
+ + #define OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET		0x009c
+ + #define OMAP4430_PRM_VC_VAL_CMD_VDD_IVA_L		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x009c)
+ + #define OMAP4_PRM_VC_VAL_BYPASS_OFFSET			0x00a0
+ + #define OMAP4430_PRM_VC_VAL_BYPASS			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a0)
+ + #define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET			0x00a4
+ + #define OMAP4430_PRM_VC_CFG_CHANNEL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a4)
+ + #define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET		0x00a8
+ + #define OMAP4430_PRM_VC_CFG_I2C_MODE			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a8)
+ + #define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET			0x00ac
+ + #define OMAP4430_PRM_VC_CFG_I2C_CLK			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ac)
+ + #define OMAP4_PRM_SRAM_COUNT_OFFSET			0x00b0
+ + #define OMAP4430_PRM_SRAM_COUNT				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b0)
+ + #define OMAP4_PRM_SRAM_WKUP_SETUP_OFFSET		0x00b4
+ + #define OMAP4430_PRM_SRAM_WKUP_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b4)
+ + #define OMAP4_PRM_LDO_SRAM_CORE_SETUP_OFFSET		0x00b8
+ + #define OMAP4430_PRM_LDO_SRAM_CORE_SETUP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b8)
+ + #define OMAP4_PRM_LDO_SRAM_CORE_CTRL_OFFSET		0x00bc
+ + #define OMAP4430_PRM_LDO_SRAM_CORE_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00bc)
+ + #define OMAP4_PRM_LDO_SRAM_MPU_SETUP_OFFSET		0x00c0
+ + #define OMAP4430_PRM_LDO_SRAM_MPU_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c0)
+ + #define OMAP4_PRM_LDO_SRAM_MPU_CTRL_OFFSET		0x00c4
+ + #define OMAP4430_PRM_LDO_SRAM_MPU_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c4)
+ + #define OMAP4_PRM_LDO_SRAM_IVA_SETUP_OFFSET		0x00c8
+ + #define OMAP4430_PRM_LDO_SRAM_IVA_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c8)
+ + #define OMAP4_PRM_LDO_SRAM_IVA_CTRL_OFFSET		0x00cc
+ + #define OMAP4430_PRM_LDO_SRAM_IVA_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00cc)
+ + #define OMAP4_PRM_LDO_ABB_MPU_SETUP_OFFSET		0x00d0
+ + #define OMAP4430_PRM_LDO_ABB_MPU_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d0)
+ + #define OMAP4_PRM_LDO_ABB_MPU_CTRL_OFFSET		0x00d4
+ + #define OMAP4430_PRM_LDO_ABB_MPU_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d4)
+ + #define OMAP4_PRM_LDO_ABB_IVA_SETUP_OFFSET		0x00d8
+ + #define OMAP4430_PRM_LDO_ABB_IVA_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d8)
+ + #define OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET		0x00dc
+ + #define OMAP4430_PRM_LDO_ABB_IVA_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00dc)
+ + #define OMAP4_PRM_LDO_BANDGAP_SETUP_OFFSET		0x00e0
+ + #define OMAP4430_PRM_LDO_BANDGAP_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e0)
+ + #define OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET		0x00e4
+ + #define OMAP4430_PRM_DEVICE_OFF_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e4)
+ + #define OMAP4_PRM_PHASE1_CNDP_OFFSET			0x00e8
+ + #define OMAP4430_PRM_PHASE1_CNDP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e8)
+ + #define OMAP4_PRM_PHASE2A_CNDP_OFFSET			0x00ec
+ + #define OMAP4430_PRM_PHASE2A_CNDP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ec)
+ + #define OMAP4_PRM_PHASE2B_CNDP_OFFSET			0x00f0
+ + #define OMAP4430_PRM_PHASE2B_CNDP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f0)
+ + #define OMAP4_PRM_MODEM_IF_CTRL_OFFSET			0x00f4
+ + #define OMAP4430_PRM_MODEM_IF_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f4)
+ + #define OMAP4_PRM_VC_ERRST_OFFSET			0x00f8
+ + #define OMAP4430_PRM_VC_ERRST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8)
+ + 
+ + /* Function prototypes */
+ + # ifndef __ASSEMBLER__
+ + 
+ + extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx);
+ + extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx);
+ + extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
+ + 
+ + /* OMAP4-specific VP functions */
+ + u32 omap4_prm_vp_check_txdone(u8 vp_id);
+ + void omap4_prm_vp_clear_txdone(u8 vp_id);
+ + 
+ + /*
+ +  * OMAP4 access functions for voltage controller (VC) and
+ +  * voltage proccessor (VP) in the PRM.
+ +  */
+ + extern u32 omap4_prm_vcvp_read(u8 offset);
+ + extern void omap4_prm_vcvp_write(u32 val, u8 offset);
+ + extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
+ + 
+ + /* PRM interrupt-related functions */
+ + extern void omap44xx_prm_read_pending_irqs(unsigned long *events);
+ + extern void omap44xx_prm_ocp_barrier(void);
+ + extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
+ + extern void omap44xx_prm_restore_irqen(u32 *saved_mask);
+ + 
+ + # endif
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/prm.h linux-3.2.1/arch/arm/mach-ckb_3352/prm.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/prm.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/prm.h	2014-11-25 13:19:15.055289303 +0900
+ ***************
+ *** 0 ****
+ --- 1,56 ----
+ + /*
+ +  * OMAP2/3/4 Power/Reset Management (PRM) bitfield definitions
+ +  *
+ +  * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ +  * Copyright (C) 2010 Nokia Corporation
+ +  *
+ +  * Paul Walmsley
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + #ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
+ + #define __ARCH_ARM_MACH_OMAP2_PRM_H
+ + 
+ + #include "prcm-common.h"
+ + 
+ + /*
+ +  * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP
+ +  *
+ +  * 2430: PM_PWSTST_MDM
+ +  *
+ +  * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
+ +  *	 PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
+ +  *	 PM_PWSTST_NEON
+ +  */
+ + #define OMAP_INTRANSITION_MASK				(1 << 20)
+ + 
+ + 
+ + /*
+ +  * 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP
+ +  *
+ +  * 2430: PM_PWSTST_MDM
+ +  *
+ +  * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
+ +  *	 PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
+ +  *	 PM_PWSTST_NEON
+ +  */
+ + #define OMAP_POWERSTATEST_SHIFT				0
+ + #define OMAP_POWERSTATEST_MASK				(0x3 << 0)
+ + 
+ + /*
+ +  * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
+ +  *       PM_PWSTCTRL_DSP, PM_PWSTST_MPU
+ +  *
+ +  * 2430: PM_PWSTCTRL_MDM shared bits
+ +  *
+ +  * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE,
+ +  *	 PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
+ +  *	 PM_PWSTCTRL_NEON shared bits
+ +  */
+ + #define OMAP_POWERSTATE_SHIFT				0
+ + #define OMAP_POWERSTATE_MASK				(0x3 << 0)
+ + 
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/prminst33xx.h linux-3.2.1/arch/arm/mach-ckb_3352/prminst33xx.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/prminst33xx.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/prminst33xx.h	2014-11-25 13:19:15.055289303 +0900
+ ***************
+ *** 0 ****
+ --- 1,29 ----
+ + /*
+ +  * AM33XX Power/Reset Management (PRM) function prototypes
+ +  *
+ +  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #ifndef __ARCH_ASM_MACH_OMAP2_PRMINST33XX_H
+ + #define __ARCH_ASM_MACH_OMAP2_PRMINST33XX_H
+ + 
+ + extern u32 am33xx_prminst_read_inst_reg(s16 inst, u16 idx);
+ + extern void am33xx_prminst_write_inst_reg(u32 val, s16 inst, u16 idx);
+ + extern u32 am33xx_prminst_rmw_inst_reg_bits(u32 mask, u32 bits,
+ + 					   s16 inst, s16 idx);
+ + extern u32 am33xx_prminst_is_hardreset_asserted(s16 domain, s16 idx, u32 mask);
+ + extern int am33xx_prminst_assert_hardreset(s16 prm_mod, u8 shift);
+ + extern int am33xx_prminst_deassert_hardreset(s16 prm_mod, u8 rst_shift,
+ + 					u8 st_shift);
+ + extern void am33xx_prm_global_warm_sw_reset(void);
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/prminst44xx.c linux-3.2.1/arch/arm/mach-ckb_3352/prminst44xx.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/prminst44xx.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/prminst44xx.c	2014-11-25 13:19:15.055289303 +0900
+ ***************
+ *** 0 ****
+ --- 1,166 ----
+ + /*
+ +  * OMAP4 PRM instance functions
+ +  *
+ +  * Copyright (C) 2009 Nokia Corporation
+ +  * Copyright (C) 2011 Texas Instruments, Inc.
+ +  * Paul Walmsley
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #include <linux/kernel.h>
+ + #include <linux/types.h>
+ + #include <linux/errno.h>
+ + #include <linux/err.h>
+ + #include <linux/io.h>
+ + 
+ + #include "common.h"
+ + 
+ + //#include "prm44xx.h"
+ + #include "prm33xx.h"
+ + #include "prminst44xx.h"
+ + #include "prm-regbits-44xx.h"
+ + #include "prcm44xx.h"
+ + //#include "prcm_mpu44xx.h"
+ + 
+ + static u32 **_prm_bases;
+ + static u32 max_prm_partitions;
+ + 
+ + static u32 *am33xx_prm_bases[] = {
+ + 	[OMAP4430_INVALID_PRCM_PARTITION]	= 0,
+ + 	[AM33XX_PRM_PARTITION]			= AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRM_BASE),
+ + };
+ + 
+ + /* Read a register in a PRM instance */
+ + u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
+ + {
+ + 	BUG_ON(part >= max_prm_partitions ||
+ + 	       part == OMAP4430_INVALID_PRCM_PARTITION ||
+ + 	       !_prm_bases[part]);
+ + 	return __raw_readl(_prm_bases[part] + ((inst + idx)/sizeof(u32)));
+ + }
+ + 
+ + /* Write into a register in a PRM instance */
+ + void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
+ + {
+ + 	BUG_ON(part >= max_prm_partitions ||
+ + 	       part == OMAP4430_INVALID_PRCM_PARTITION ||
+ + 	       !_prm_bases[part]);
+ + 	__raw_writel(val, _prm_bases[part] + ((inst + idx)/sizeof(u32)));
+ + }
+ + 
+ + /* Read-modify-write a register in PRM. Caller must lock */
+ + u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
+ + 				    u16 idx)
+ + {
+ + 	u32 v;
+ + 
+ + 	v = omap4_prminst_read_inst_reg(part, inst, idx);
+ + 	v &= ~mask;
+ + 	v |= bits;
+ + 	omap4_prminst_write_inst_reg(v, part, inst, idx);
+ + 
+ + 	return v;
+ + }
+ + 
+ + /*
+ +  * Address offset (in bytes) between the reset control and the reset
+ +  * status registers: 4 bytes on OMAP4
+ +  */
+ + #define OMAP4_RST_CTRL_ST_OFFSET		4
+ + 
+ + /**
+ +  * omap4_prminst_is_hardreset_asserted - read the HW reset line state of
+ +  * submodules contained in the hwmod module
+ +  * @rstctrl_reg: RM_RSTCTRL register address for this module
+ +  * @shift: register bit shift corresponding to the reset line to check
+ +  *
+ +  * Returns 1 if the (sub)module hardreset line is currently asserted,
+ +  * 0 if the (sub)module hardreset line is not currently asserted, or
+ +  * -EINVAL upon parameter error.
+ +  */
+ + int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
+ + 					u16 rstctrl_offs)
+ + {
+ + 	u32 v;
+ + 
+ + 	v = omap4_prminst_read_inst_reg(part, inst, rstctrl_offs);
+ + 	v &= 1 << shift;
+ + 	v >>= shift;
+ + 
+ + 	return v;
+ + }
+ + 
+ + /**
+ +  * omap4_prminst_assert_hardreset - assert the HW reset line of a submodule
+ +  * @rstctrl_reg: RM_RSTCTRL register address for this module
+ +  * @shift: register bit shift corresponding to the reset line to assert
+ +  *
+ +  * Some IPs like dsp, ipu or iva contain processors that require an HW
+ +  * reset line to be asserted / deasserted in order to fully enable the
+ +  * IP.  These modules may have multiple hard-reset lines that reset
+ +  * different 'submodules' inside the IP block.  This function will
+ +  * place the submodule into reset.  Returns 0 upon success or -EINVAL
+ +  * upon an argument error.
+ +  */
+ + int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
+ + 				   u16 rstctrl_offs)
+ + {
+ + 	u32 mask = 1 << shift;
+ + 
+ + 	omap4_prminst_rmw_inst_reg_bits(mask, mask, part, inst, rstctrl_offs);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * omap4_prminst_deassert_hardreset - deassert a submodule hardreset line and
+ +  * wait
+ +  * @rstctrl_reg: RM_RSTCTRL register address for this module
+ +  * @shift: register bit shift corresponding to the reset line to deassert
+ +  * @st_shift: register bit shift corresponding to the reset line to deassert
+ +  *
+ +  * Some IPs like dsp, ipu or iva contain processors that require an HW
+ +  * reset line to be asserted / deasserted in order to fully enable the
+ +  * IP.  These modules may have multiple hard-reset lines that reset
+ +  * different 'submodules' inside the IP block.  This function will
+ +  * take the submodule out of reset and wait until the PRCM indicates
+ +  * that the reset has completed before returning.  Returns 0 upon success or
+ +  * -EINVAL upon an argument error, -EEXIST if the submodule was already out
+ +  * of reset, or -EBUSY if the submodule did not exit reset promptly.
+ +  */
+ + int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part,
+ + 				s16 inst, u16 rstctrl_offs, u16 rstst_offs)
+ + {
+ + 	int c;
+ + 
+ + 	rstst_offs = rstst_offs ? rstst_offs :
+ + 			(rstctrl_offs + OMAP4_RST_CTRL_ST_OFFSET);
+ + 	st_shift = st_shift ? st_shift : shift;
+ + 
+ + 	/* Check the current status to avoid de-asserting the line twice */
+ + 	if (omap4_prminst_is_hardreset_asserted(shift, part, inst,
+ + 						rstctrl_offs) == 0)
+ + 		return -EEXIST;
+ + 
+ + 	/* Clear the reset status by writing 1 to the status bit */
+ + 	omap4_prminst_rmw_inst_reg_bits(0xffffffff, (1 << st_shift), part, inst,
+ + 					rstst_offs);
+ + 	/* de-assert the reset control line */
+ + 	omap4_prminst_rmw_inst_reg_bits((1 << shift), 0, part, inst, rstctrl_offs);
+ + 	/* wait the status to be set */
+ + 	omap_test_timeout(omap4_prminst_is_hardreset_asserted(st_shift,
+ + 					part, inst, rstst_offs),
+ + 			  MAX_MODULE_HARDRESET_WAIT, c);
+ + 
+ + 	return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
+ + }
+ + 
+ + 
+ + void __init omap44xx_prminst_init(void)
+ + {
+ + 	_prm_bases = am33xx_prm_bases;
+ + 	max_prm_partitions = ARRAY_SIZE(am33xx_prm_bases);
+ + }
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/prminst44xx.h linux-3.2.1/arch/arm/mach-ckb_3352/prminst44xx.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/prminst44xx.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/prminst44xx.h	2014-11-25 13:19:15.059580881 +0900
+ ***************
+ *** 0 ****
+ --- 1,31 ----
+ + /*
+ +  * OMAP4 Power/Reset Management (PRM) function prototypes
+ +  *
+ +  * Copyright (C) 2010 Nokia Corporation
+ +  * Copyright (C) 2011 Texas Instruments, Inc.
+ +  * Paul Walmsley
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + #ifndef __ARCH_ASM_MACH_OMAP2_PRMINST44XX_H
+ + #define __ARCH_ASM_MACH_OMAP2_PRMINST44XX_H
+ + 
+ + /*
+ +  * In an ideal world, we would not export these low-level functions,
+ +  * but this will probably take some time to fix properly
+ +  */
+ + extern u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx);
+ + extern void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx);
+ + extern u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part,
+ + 					   s16 inst, u16 idx);
+ + 
+ + extern int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
+ + 					       u16 rstctrl_offs);
+ + extern int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
+ + 					  u16 rstctrl_offs);
+ + extern int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part,
+ + 				s16 inst, u16 rstctrl_offs, u16 rstst_offs);
+ + extern void __init omap44xx_prminst_init(void);
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/prm-regbits-24xx.h linux-3.2.1/arch/arm/mach-ckb_3352/prm-regbits-24xx.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/prm-regbits-24xx.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/prm-regbits-24xx.h	2014-11-25 13:19:15.059580881 +0900
+ ***************
+ *** 0 ****
+ --- 1,283 ----
+ + #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H
+ + #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H
+ + 
+ + /*
+ +  * OMAP24XX Power/Reset Management register bits
+ +  *
+ +  * Copyright (C) 2007 Texas Instruments, Inc.
+ +  * Copyright (C) 2007 Nokia Corporation
+ +  *
+ +  * Written by Paul Walmsley
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #include "prm2xxx_3xxx.h"
+ + 
+ + /* Bits shared between registers */
+ + 
+ + /* PRCM_IRQSTATUS_MPU, PM_IRQSTATUS_DSP, PRCM_IRQSTATUS_IVA shared bits */
+ + #define OMAP24XX_VOLTTRANS_ST_MASK			(1 << 2)
+ + #define OMAP24XX_WKUP2_ST_MASK				(1 << 1)
+ + #define OMAP24XX_WKUP1_ST_MASK				(1 << 0)
+ + 
+ + /* PRCM_IRQENABLE_MPU, PM_IRQENABLE_DSP, PRCM_IRQENABLE_IVA shared bits */
+ + #define OMAP24XX_VOLTTRANS_EN_MASK			(1 << 2)
+ + #define OMAP24XX_WKUP2_EN_MASK				(1 << 1)
+ + #define OMAP24XX_WKUP1_EN_MASK				(1 << 0)
+ + 
+ + /* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */
+ + #define OMAP24XX_EN_MPU_SHIFT				1
+ + #define OMAP24XX_EN_MPU_MASK				(1 << 1)
+ + #define OMAP24XX_EN_CORE_SHIFT 				0
+ + #define OMAP24XX_EN_CORE_MASK				(1 << 0)
+ + 
+ + /*
+ +  * PM_PWSTCTRL_MPU, PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM
+ +  * shared bits
+ +  */
+ + #define OMAP24XX_MEMONSTATE_SHIFT			10
+ + #define OMAP24XX_MEMONSTATE_MASK			(0x3 << 10)
+ + #define OMAP24XX_MEMRETSTATE_MASK			(1 << 3)
+ + 
+ + /* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM shared bits */
+ + #define OMAP24XX_FORCESTATE_MASK			(1 << 18)
+ + 
+ + /*
+ +  * PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP,
+ +  * PM_PWSTST_MDM shared bits
+ +  */
+ + #define OMAP24XX_CLKACTIVITY_MASK			(1 << 19)
+ + 
+ + /* PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_DSP shared bits */
+ + #define OMAP24XX_LASTSTATEENTERED_SHIFT			4
+ + #define OMAP24XX_LASTSTATEENTERED_MASK			(0x3 << 4)
+ + 
+ + /* PM_PWSTST_MPU and PM_PWSTST_DSP shared bits */
+ + #define OMAP2430_MEMSTATEST_SHIFT			10
+ + #define OMAP2430_MEMSTATEST_MASK			(0x3 << 10)
+ + 
+ + /* PM_PWSTST_GFX, PM_PWSTST_DSP, PM_PWSTST_MDM shared bits */
+ + #define OMAP24XX_POWERSTATEST_SHIFT			0
+ + #define OMAP24XX_POWERSTATEST_MASK			(0x3 << 0)
+ + 
+ + 
+ + /* Bits specific to each register */
+ + 
+ + /* PRCM_REVISION */
+ + #define OMAP24XX_REV_SHIFT				0
+ + #define OMAP24XX_REV_MASK				(0xff << 0)
+ + 
+ + /* PRCM_SYSCONFIG */
+ + #define OMAP24XX_AUTOIDLE_MASK				(1 << 0)
+ + 
+ + /* PRCM_IRQSTATUS_MPU specific bits */
+ + #define OMAP2430_DPLL_RECAL_ST_MASK			(1 << 6)
+ + #define OMAP24XX_TRANSITION_ST_MASK			(1 << 5)
+ + #define OMAP24XX_EVGENOFF_ST_MASK			(1 << 4)
+ + #define OMAP24XX_EVGENON_ST_MASK			(1 << 3)
+ + 
+ + /* PRCM_IRQENABLE_MPU specific bits */
+ + #define OMAP2430_DPLL_RECAL_EN_MASK			(1 << 6)
+ + #define OMAP24XX_TRANSITION_EN_MASK			(1 << 5)
+ + #define OMAP24XX_EVGENOFF_EN_MASK			(1 << 4)
+ + #define OMAP24XX_EVGENON_EN_MASK			(1 << 3)
+ + 
+ + /* PRCM_VOLTCTRL */
+ + #define OMAP24XX_AUTO_EXTVOLT_MASK			(1 << 15)
+ + #define OMAP24XX_FORCE_EXTVOLT_MASK			(1 << 14)
+ + #define OMAP24XX_SETOFF_LEVEL_SHIFT			12
+ + #define OMAP24XX_SETOFF_LEVEL_MASK			(0x3 << 12)
+ + #define OMAP24XX_MEMRETCTRL_MASK			(1 << 8)
+ + #define OMAP24XX_SETRET_LEVEL_SHIFT			6
+ + #define OMAP24XX_SETRET_LEVEL_MASK			(0x3 << 6)
+ + #define OMAP24XX_VOLT_LEVEL_SHIFT			0
+ + #define OMAP24XX_VOLT_LEVEL_MASK			(0x3 << 0)
+ + 
+ + /* PRCM_VOLTST */
+ + #define OMAP24XX_ST_VOLTLEVEL_SHIFT			0
+ + #define OMAP24XX_ST_VOLTLEVEL_MASK			(0x3 << 0)
+ + 
+ + /* PRCM_CLKSRC_CTRL specific bits */
+ + 
+ + /* PRCM_CLKOUT_CTRL */
+ + #define OMAP2420_CLKOUT2_EN_SHIFT			15
+ + #define OMAP2420_CLKOUT2_EN_MASK			(1 << 15)
+ + #define OMAP2420_CLKOUT2_DIV_SHIFT			11
+ + #define OMAP2420_CLKOUT2_DIV_MASK			(0x7 << 11)
+ + #define OMAP2420_CLKOUT2_SOURCE_SHIFT			8
+ + #define OMAP2420_CLKOUT2_SOURCE_MASK			(0x3 << 8)
+ + #define OMAP24XX_CLKOUT_EN_SHIFT			7
+ + #define OMAP24XX_CLKOUT_EN_MASK				(1 << 7)
+ + #define OMAP24XX_CLKOUT_DIV_SHIFT			3
+ + #define OMAP24XX_CLKOUT_DIV_MASK			(0x7 << 3)
+ + #define OMAP24XX_CLKOUT_SOURCE_SHIFT			0
+ + #define OMAP24XX_CLKOUT_SOURCE_MASK			(0x3 << 0)
+ + 
+ + /* PRCM_CLKEMUL_CTRL */
+ + #define OMAP24XX_EMULATION_EN_SHIFT			0
+ + #define OMAP24XX_EMULATION_EN_MASK			(1 << 0)
+ + 
+ + /* PRCM_CLKCFG_CTRL */
+ + #define OMAP24XX_VALID_CONFIG_MASK			(1 << 0)
+ + 
+ + /* PRCM_CLKCFG_STATUS */
+ + #define OMAP24XX_CONFIG_STATUS_MASK			(1 << 0)
+ + 
+ + /* PRCM_VOLTSETUP specific bits */
+ + 
+ + /* PRCM_CLKSSETUP specific bits */
+ + 
+ + /* PRCM_POLCTRL */
+ + #define OMAP2420_CLKOUT2_POL_MASK			(1 << 10)
+ + #define OMAP24XX_CLKOUT_POL_MASK			(1 << 9)
+ + #define OMAP24XX_CLKREQ_POL_MASK			(1 << 8)
+ + #define OMAP2430_USE_POWEROK_MASK			(1 << 2)
+ + #define OMAP2430_POWEROK_POL_MASK			(1 << 1)
+ + #define OMAP24XX_EXTVOL_POL_MASK			(1 << 0)
+ + 
+ + /* RM_RSTST_MPU specific bits */
+ + /* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */
+ + 
+ + /* PM_WKDEP_MPU specific bits */
+ + #define OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT		5
+ + #define OMAP2430_PM_WKDEP_MPU_EN_MDM_MASK		(1 << 5)
+ + #define OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT		2
+ + #define OMAP24XX_PM_WKDEP_MPU_EN_DSP_MASK		(1 << 2)
+ + 
+ + /* PM_EVGENCTRL_MPU specific bits */
+ + 
+ + /* PM_EVEGENONTIM_MPU specific bits */
+ + 
+ + /* PM_EVEGENOFFTIM_MPU specific bits */
+ + 
+ + /* PM_PWSTCTRL_MPU specific bits */
+ + #define OMAP2430_FORCESTATE_MASK			(1 << 18)
+ + 
+ + /* PM_PWSTST_MPU specific bits */
+ + /* INTRANSITION, CLKACTIVITY, POWERSTATE, MEMSTATEST are 2430 only */
+ + 
+ + /* PM_WKEN1_CORE specific bits */
+ + 
+ + /* PM_WKEN2_CORE specific bits */
+ + 
+ + /* PM_WKST1_CORE specific bits*/
+ + 
+ + /* PM_WKST2_CORE specific bits */
+ + 
+ + /* PM_WKDEP_CORE specific bits*/
+ + #define OMAP2430_PM_WKDEP_CORE_EN_MDM_MASK		(1 << 5)
+ + #define OMAP24XX_PM_WKDEP_CORE_EN_GFX_MASK		(1 << 3)
+ + #define OMAP24XX_PM_WKDEP_CORE_EN_DSP_MASK		(1 << 2)
+ + 
+ + /* PM_PWSTCTRL_CORE specific bits */
+ + #define OMAP24XX_MEMORYCHANGE_MASK			(1 << 20)
+ + #define OMAP24XX_MEM3ONSTATE_SHIFT			14
+ + #define OMAP24XX_MEM3ONSTATE_MASK			(0x3 << 14)
+ + #define OMAP24XX_MEM2ONSTATE_SHIFT			12
+ + #define OMAP24XX_MEM2ONSTATE_MASK			(0x3 << 12)
+ + #define OMAP24XX_MEM1ONSTATE_SHIFT			10
+ + #define OMAP24XX_MEM1ONSTATE_MASK			(0x3 << 10)
+ + #define OMAP24XX_MEM3RETSTATE_MASK			(1 << 5)
+ + #define OMAP24XX_MEM2RETSTATE_MASK			(1 << 4)
+ + #define OMAP24XX_MEM1RETSTATE_MASK			(1 << 3)
+ + 
+ + /* PM_PWSTST_CORE specific bits */
+ + #define OMAP24XX_MEM3STATEST_SHIFT			14
+ + #define OMAP24XX_MEM3STATEST_MASK			(0x3 << 14)
+ + #define OMAP24XX_MEM2STATEST_SHIFT			12
+ + #define OMAP24XX_MEM2STATEST_MASK			(0x3 << 12)
+ + #define OMAP24XX_MEM1STATEST_SHIFT			10
+ + #define OMAP24XX_MEM1STATEST_MASK			(0x3 << 10)
+ + 
+ + /* RM_RSTCTRL_GFX */
+ + #define OMAP24XX_GFX_RST_MASK				(1 << 0)
+ + 
+ + /* RM_RSTST_GFX specific bits */
+ + #define OMAP24XX_GFX_SW_RST_MASK			(1 << 4)
+ + 
+ + /* PM_PWSTCTRL_GFX specific bits */
+ + 
+ + /* PM_WKDEP_GFX specific bits */
+ + /* 2430 often calls EN_WAKEUP "EN_WKUP" */
+ + 
+ + /* RM_RSTCTRL_WKUP specific bits */
+ + 
+ + /* RM_RSTTIME_WKUP specific bits */
+ + 
+ + /* RM_RSTST_WKUP specific bits */
+ + /* 2430 calls EXTWMPU_RST "EXTWARM_RST" and GLOBALWMPU_RST "GLOBALWARM_RST" */
+ + #define OMAP24XX_EXTWMPU_RST_MASK			(1 << 6)
+ + #define OMAP24XX_SECU_WD_RST_MASK			(1 << 5)
+ + #define OMAP24XX_MPU_WD_RST_MASK			(1 << 4)
+ + #define OMAP24XX_SECU_VIOL_RST_MASK			(1 << 3)
+ + 
+ + /* PM_WKEN_WKUP specific bits */
+ + 
+ + /* PM_WKST_WKUP specific bits */
+ + 
+ + /* RM_RSTCTRL_DSP */
+ + #define OMAP2420_RST_IVA_MASK				(1 << 8)
+ + #define OMAP24XX_RST2_DSP_MASK				(1 << 1)
+ + #define OMAP24XX_RST1_DSP_MASK				(1 << 0)
+ + 
+ + /* RM_RSTST_DSP specific bits */
+ + /* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" */
+ + #define OMAP2420_IVA_SW_RST_MASK			(1 << 8)
+ + #define OMAP24XX_DSP_SW_RST2_MASK			(1 << 5)
+ + #define OMAP24XX_DSP_SW_RST1_MASK			(1 << 4)
+ + 
+ + /* PM_WKDEP_DSP specific bits */
+ + 
+ + /* PM_PWSTCTRL_DSP specific bits */
+ + /* 2430 only: MEMONSTATE, MEMRETSTATE */
+ + #define OMAP2420_MEMIONSTATE_SHIFT			12
+ + #define OMAP2420_MEMIONSTATE_MASK			(0x3 << 12)
+ + #define OMAP2420_MEMIRETSTATE_MASK			(1 << 4)
+ + 
+ + /* PM_PWSTST_DSP specific bits */
+ + /* MEMSTATEST is 2430 only */
+ + #define OMAP2420_MEMISTATEST_SHIFT			12
+ + #define OMAP2420_MEMISTATEST_MASK			(0x3 << 12)
+ + 
+ + /* PRCM_IRQSTATUS_DSP specific bits */
+ + 
+ + /* PRCM_IRQENABLE_DSP specific bits */
+ + 
+ + /* RM_RSTCTRL_MDM */
+ + /* 2430 only */
+ + #define OMAP2430_PWRON1_MDM_MASK			(1 << 1)
+ + #define OMAP2430_RST1_MDM_MASK				(1 << 0)
+ + 
+ + /* RM_RSTST_MDM specific bits */
+ + /* 2430 only */
+ + #define OMAP2430_MDM_SECU_VIOL_MASK			(1 << 6)
+ + #define OMAP2430_MDM_SW_PWRON1_MASK			(1 << 5)
+ + #define OMAP2430_MDM_SW_RST1_MASK			(1 << 4)
+ + 
+ + /* PM_WKEN_MDM */
+ + /* 2430 only */
+ + #define OMAP2430_PM_WKEN_MDM_EN_MDM_MASK		(1 << 0)
+ + 
+ + /* PM_WKST_MDM specific bits */
+ + /* 2430 only */
+ + 
+ + /* PM_WKDEP_MDM specific bits */
+ + /* 2430 only */
+ + 
+ + /* PM_PWSTCTRL_MDM specific bits */
+ + /* 2430 only */
+ + #define OMAP2430_KILLDOMAINWKUP_MASK			(1 << 19)
+ + 
+ + /* PM_PWSTST_MDM specific bits */
+ + /* 2430 only */
+ + 
+ + /* PRCM_IRQSTATUS_IVA */
+ + /* 2420 only */
+ + 
+ + /* PRCM_IRQENABLE_IVA */
+ + /* 2420 only */
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/prm-regbits-33xx.h linux-3.2.1/arch/arm/mach-ckb_3352/prm-regbits-33xx.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/prm-regbits-33xx.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/prm-regbits-33xx.h	2014-11-25 13:19:15.059580881 +0900
+ ***************
+ *** 0 ****
+ --- 1,357 ----
+ + /*
+ +  * AM33XX Power Management register bits
+ +  *
+ +  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H
+ + #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H
+ + 
+ + #include "prm.h"
+ + 
+ + /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+ + #define AM33XX_ABBOFF_ACT_EXPORT_SHIFT			1
+ + #define AM33XX_ABBOFF_ACT_EXPORT_MASK			(1 << 1)
+ + 
+ + /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+ + #define AM33XX_ABBOFF_SLEEP_EXPORT_SHIFT		2
+ + #define AM33XX_ABBOFF_SLEEP_EXPORT_MASK			(1 << 2)
+ + 
+ + /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+ + #define AM33XX_AIPOFF_SHIFT				8
+ + #define AM33XX_AIPOFF_MASK				(1 << 8)
+ + 
+ + /* Used by PM_WKUP_PWRSTST */
+ + #define AM33XX_DEBUGSS_MEM_STATEST_SHIFT		17
+ + #define AM33XX_DEBUGSS_MEM_STATEST_MASK			(0x3 << 17)
+ + 
+ + /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+ + #define AM33XX_DISABLE_RTA_EXPORT_SHIFT			0
+ + #define AM33XX_DISABLE_RTA_EXPORT_MASK			(1 << 0)
+ + 
+ + /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+ + #define AM33XX_DPLL_CORE_RECAL_EN_SHIFT			12
+ + #define AM33XX_DPLL_CORE_RECAL_EN_MASK			(1 << 12)
+ + 
+ + /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+ + #define AM33XX_DPLL_CORE_RECAL_ST_SHIFT			12
+ + #define AM33XX_DPLL_CORE_RECAL_ST_MASK			(1 << 12)
+ + 
+ + /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+ + #define AM33XX_DPLL_DDR_RECAL_EN_SHIFT			14
+ + #define AM33XX_DPLL_DDR_RECAL_EN_MASK			(1 << 14)
+ + 
+ + /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+ + #define AM33XX_DPLL_DDR_RECAL_ST_SHIFT			14
+ + #define AM33XX_DPLL_DDR_RECAL_ST_MASK			(1 << 14)
+ + 
+ + /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+ + #define AM33XX_DPLL_DISP_RECAL_EN_SHIFT			15
+ + #define AM33XX_DPLL_DISP_RECAL_EN_MASK			(1 << 15)
+ + 
+ + /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+ + #define AM33XX_DPLL_DISP_RECAL_ST_SHIFT			13
+ + #define AM33XX_DPLL_DISP_RECAL_ST_MASK			(1 << 13)
+ + 
+ + /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+ + #define AM33XX_DPLL_MPU_RECAL_EN_SHIFT			11
+ + #define AM33XX_DPLL_MPU_RECAL_EN_MASK			(1 << 11)
+ + 
+ + /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+ + #define AM33XX_DPLL_MPU_RECAL_ST_SHIFT			11
+ + #define AM33XX_DPLL_MPU_RECAL_ST_MASK			(1 << 11)
+ + 
+ + /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+ + #define AM33XX_DPLL_PER_RECAL_EN_SHIFT			13
+ + #define AM33XX_DPLL_PER_RECAL_EN_MASK			(1 << 13)
+ + 
+ + /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+ + #define AM33XX_DPLL_PER_RECAL_ST_SHIFT			15
+ + #define AM33XX_DPLL_PER_RECAL_ST_MASK			(1 << 15)
+ + 
+ + /* Used by RM_WKUP_RSTST */
+ + #define AM33XX_EMULATION_M3_RST_SHIFT			6
+ + #define AM33XX_EMULATION_M3_RST_MASK			(1 << 6)
+ + 
+ + /* Used by RM_MPU_RSTST */
+ + #define AM33XX_EMULATION_MPU_RST_SHIFT			5
+ + #define AM33XX_EMULATION_MPU_RST_MASK			(1 << 5)
+ + 
+ + /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+ + #define AM33XX_ENFUNC1_EXPORT_SHIFT			3
+ + #define AM33XX_ENFUNC1_EXPORT_MASK			(1 << 3)
+ + 
+ + /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+ + #define AM33XX_ENFUNC3_EXPORT_SHIFT			5
+ + #define AM33XX_ENFUNC3_EXPORT_MASK			(1 << 5)
+ + 
+ + /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+ + #define AM33XX_ENFUNC4_SHIFT				6
+ + #define AM33XX_ENFUNC4_MASK				(1 << 6)
+ + 
+ + /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+ + #define AM33XX_ENFUNC5_SHIFT				7
+ + #define AM33XX_ENFUNC5_MASK				(1 << 7)
+ + 
+ + /* Used by PRM_RSTST */
+ + #define AM33XX_EXTERNAL_WARM_RST_SHIFT			5
+ + #define AM33XX_EXTERNAL_WARM_RST_MASK			(1 << 5)
+ + 
+ + /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+ + #define AM33XX_FORCEWKUP_EN_SHIFT			10
+ + #define AM33XX_FORCEWKUP_EN_MASK			(1 << 10)
+ + 
+ + /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+ + #define AM33XX_FORCEWKUP_ST_SHIFT			10
+ + #define AM33XX_FORCEWKUP_ST_MASK			(1 << 10)
+ + 
+ + /* Used by PM_GFX_PWRSTCTRL */
+ + #define AM33XX_GFX_MEM_ONSTATE_SHIFT			17
+ + #define AM33XX_GFX_MEM_ONSTATE_MASK			(0x3 << 17)
+ + 
+ + /* Used by PM_GFX_PWRSTCTRL */
+ + #define AM33XX_GFX_MEM_RETSTATE_SHIFT			6
+ + #define AM33XX_GFX_MEM_RETSTATE_MASK			(1 << 6)
+ + 
+ + /* Used by PM_GFX_PWRSTST */
+ + #define AM33XX_GFX_MEM_STATEST_SHIFT			4
+ + #define AM33XX_GFX_MEM_STATEST_MASK			(0x3 << 4)
+ + 
+ + /* Used by RM_GFX_RSTCTRL, RM_GFX_RSTST */
+ + #define AM33XX_GFX_RST_SHIFT				0
+ + #define AM33XX_GFX_RST_MASK				(1 << 0)
+ + 
+ + /* Used by PRM_RSTST */
+ + #define AM33XX_GLOBAL_COLD_RST_SHIFT			0
+ + #define AM33XX_GLOBAL_COLD_RST_MASK			(1 << 0)
+ + 
+ + /* Used by PRM_RSTST */
+ + #define AM33XX_GLOBAL_WARM_SW_RST_SHIFT			1
+ + #define AM33XX_GLOBAL_WARM_SW_RST_MASK			(1 << 1)
+ + 
+ + /* Used by RM_WKUP_RSTST */
+ + #define AM33XX_ICECRUSHER_M3_RST_SHIFT			7
+ + #define AM33XX_ICECRUSHER_M3_RST_MASK			(1 << 7)
+ + 
+ + /* Used by RM_MPU_RSTST */
+ + #define AM33XX_ICECRUSHER_MPU_RST_SHIFT			6
+ + #define AM33XX_ICECRUSHER_MPU_RST_MASK			(1 << 6)
+ + 
+ + /* Used by PRM_RSTST */
+ + #define AM33XX_ICEPICK_RST_SHIFT			9
+ + #define AM33XX_ICEPICK_RST_MASK				(1 << 9)
+ + 
+ + /* Used by RM_PER_RSTCTRL */
+ + #define AM33XX_ICSS_LRST_SHIFT				1
+ + #define AM33XX_ICSS_LRST_MASK				(1 << 1)
+ + 
+ + /* Used by PM_PER_PWRSTCTRL */
+ + #define AM33XX_ICSS_MEM_ONSTATE_SHIFT			5
+ + #define AM33XX_ICSS_MEM_ONSTATE_MASK			(0x3 << 5)
+ + 
+ + /* Used by PM_PER_PWRSTCTRL */
+ + #define AM33XX_ICSS_MEM_RETSTATE_SHIFT			7
+ + #define AM33XX_ICSS_MEM_RETSTATE_MASK			(1 << 7)
+ + 
+ + /* Used by PM_PER_PWRSTST */
+ + #define AM33XX_ICSS_MEM_STATEST_SHIFT			23
+ + #define AM33XX_ICSS_MEM_STATEST_MASK			(0x3 << 23)
+ + 
+ + /*
+ +  * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST,
+ +  * PM_WKUP_PWRSTST, PM_RTC_PWRSTST
+ +  */
+ + #define AM33XX_INTRANSITION_SHIFT			20
+ + #define AM33XX_INTRANSITION_MASK			(1 << 20)
+ + 
+ + /* Used by PM_CEFUSE_PWRSTST */
+ + #define AM33XX_LASTPOWERSTATEENTERED_SHIFT		24
+ + #define AM33XX_LASTPOWERSTATEENTERED_MASK		(0x3 << 24)
+ + 
+ + /* Used by PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_RTC_PWRSTCTRL */
+ + #define AM33XX_LOGICRETSTATE_SHIFT			2
+ + #define AM33XX_LOGICRETSTATE_MASK			(1 << 2)
+ + 
+ + /* Renamed from LOGICRETSTATE Used by PM_PER_PWRSTCTRL, PM_WKUP_PWRSTCTRL */
+ + #define AM33XX_LOGICRETSTATE_3_3_SHIFT			3
+ + #define AM33XX_LOGICRETSTATE_3_3_MASK			(1 << 3)
+ + 
+ + /*
+ +  * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST,
+ +  * PM_WKUP_PWRSTST, PM_RTC_PWRSTST
+ +  */
+ + #define AM33XX_LOGICSTATEST_SHIFT			2
+ + #define AM33XX_LOGICSTATEST_MASK			(1 << 2)
+ + 
+ + /*
+ +  * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL,
+ +  * PM_MPU_PWRSTCTRL, PM_WKUP_PWRSTCTRL, PM_RTC_PWRSTCTRL
+ +  */
+ + #define AM33XX_LOWPOWERSTATECHANGE_SHIFT		4
+ + #define AM33XX_LOWPOWERSTATECHANGE_MASK			(1 << 4)
+ + 
+ + /* Used by PM_MPU_PWRSTCTRL */
+ + #define AM33XX_MPU_L1_ONSTATE_SHIFT			18
+ + #define AM33XX_MPU_L1_ONSTATE_MASK			(0x3 << 18)
+ + 
+ + /* Used by PM_MPU_PWRSTCTRL */
+ + #define AM33XX_MPU_L1_RETSTATE_SHIFT			22
+ + #define AM33XX_MPU_L1_RETSTATE_MASK			(1 << 22)
+ + 
+ + /* Used by PM_MPU_PWRSTST */
+ + #define AM33XX_MPU_L1_STATEST_SHIFT			6
+ + #define AM33XX_MPU_L1_STATEST_MASK			(0x3 << 6)
+ + 
+ + /* Used by PM_MPU_PWRSTCTRL */
+ + #define AM33XX_MPU_L2_ONSTATE_SHIFT			20
+ + #define AM33XX_MPU_L2_ONSTATE_MASK			(0x3 << 20)
+ + 
+ + /* Used by PM_MPU_PWRSTCTRL */
+ + #define AM33XX_MPU_L2_RETSTATE_SHIFT			23
+ + #define AM33XX_MPU_L2_RETSTATE_MASK			(1 << 23)
+ + 
+ + /* Used by PM_MPU_PWRSTST */
+ + #define AM33XX_MPU_L2_STATEST_SHIFT			8
+ + #define AM33XX_MPU_L2_STATEST_MASK			(0x3 << 8)
+ + 
+ + /* Used by PM_MPU_PWRSTCTRL */
+ + #define AM33XX_MPU_RAM_ONSTATE_SHIFT			16
+ + #define AM33XX_MPU_RAM_ONSTATE_MASK			(0x3 << 16)
+ + 
+ + /* Used by PM_MPU_PWRSTCTRL */
+ + #define AM33XX_MPU_RAM_RETSTATE_SHIFT			24
+ + #define AM33XX_MPU_RAM_RETSTATE_MASK			(1 << 24)
+ + 
+ + /* Used by PM_MPU_PWRSTST */
+ + #define AM33XX_MPU_RAM_STATEST_SHIFT			4
+ + #define AM33XX_MPU_RAM_STATEST_MASK			(0x3 << 4)
+ + 
+ + /* Used by PRM_RSTST */
+ + #define AM33XX_MPU_SECURITY_VIOL_RST_SHIFT		2
+ + #define AM33XX_MPU_SECURITY_VIOL_RST_MASK		(1 << 2)
+ + 
+ + /* Used by PRM_SRAM_COUNT */
+ + #define AM33XX_PCHARGECNT_VALUE_SHIFT			0
+ + #define AM33XX_PCHARGECNT_VALUE_MASK			(0x3f << 0)
+ + 
+ + /* Used by RM_PER_RSTCTRL */
+ + #define AM33XX_PCI_LRST_SHIFT				0
+ + #define AM33XX_PCI_LRST_MASK				(1 << 0)
+ + 
+ + /* Renamed from PCI_LRST Used by RM_PER_RSTST */
+ + #define AM33XX_PCI_LRST_5_5_SHIFT			5
+ + #define AM33XX_PCI_LRST_5_5_MASK			(1 << 5)
+ + 
+ + /* Used by PM_PER_PWRSTCTRL */
+ + #define AM33XX_PER_MEM_ONSTATE_SHIFT			25
+ + #define AM33XX_PER_MEM_ONSTATE_MASK			(0x3 << 25)
+ + 
+ + /* Used by PM_PER_PWRSTCTRL */
+ + #define AM33XX_PER_MEM_RETSTATE_SHIFT			29
+ + #define AM33XX_PER_MEM_RETSTATE_MASK			(1 << 29)
+ + 
+ + /* Used by PM_PER_PWRSTST */
+ + #define AM33XX_PER_MEM_STATEST_SHIFT			17
+ + #define AM33XX_PER_MEM_STATEST_MASK			(0x3 << 17)
+ + 
+ + /*
+ +  * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL,
+ +  * PM_MPU_PWRSTCTRL
+ +  */
+ + #define AM33XX_POWERSTATE_SHIFT				0
+ + #define AM33XX_POWERSTATE_MASK				(0x3 << 0)
+ + 
+ + /* Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST */
+ + #define AM33XX_POWERSTATEST_SHIFT			0
+ + #define AM33XX_POWERSTATEST_MASK			(0x3 << 0)
+ + 
+ + /* Used by PM_PER_PWRSTCTRL */
+ + #define AM33XX_RAM_MEM_ONSTATE_SHIFT			30
+ + #define AM33XX_RAM_MEM_ONSTATE_MASK			(0x3 << 30)
+ + 
+ + /* Used by PM_PER_PWRSTCTRL */
+ + #define AM33XX_RAM_MEM_RETSTATE_SHIFT			27
+ + #define AM33XX_RAM_MEM_RETSTATE_MASK			(1 << 27)
+ + 
+ + /* Used by PM_PER_PWRSTST */
+ + #define AM33XX_RAM_MEM_STATEST_SHIFT			21
+ + #define AM33XX_RAM_MEM_STATEST_MASK			(0x3 << 21)
+ + 
+ + /* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
+ + #define AM33XX_RETMODE_ENABLE_SHIFT			0
+ + #define AM33XX_RETMODE_ENABLE_MASK			(1 << 0)
+ + 
+ + /* Used by REVISION_PRM */
+ + #define AM33XX_REV_SHIFT				0
+ + #define AM33XX_REV_MASK					(0xff << 0)
+ + 
+ + /* Used by PRM_RSTTIME */
+ + #define AM33XX_RSTTIME1_SHIFT				0
+ + #define AM33XX_RSTTIME1_MASK				(0xff << 0)
+ + 
+ + /* Used by PRM_RSTTIME */
+ + #define AM33XX_RSTTIME2_SHIFT				8
+ + #define AM33XX_RSTTIME2_MASK				(0x1f << 8)
+ + 
+ + /* Used by PRM_RSTCTRL */
+ + #define AM33XX_RST_GLOBAL_COLD_SW_SHIFT			1
+ + #define AM33XX_RST_GLOBAL_COLD_SW_MASK			(1 << 1)
+ + 
+ + /* Used by PRM_RSTCTRL */
+ + #define AM33XX_RST_GLOBAL_WARM_SW_SHIFT			0
+ + #define AM33XX_RST_GLOBAL_WARM_SW_MASK			(1 << 0)
+ + 
+ + /* Used by PRM_SRAM_COUNT */
+ + #define AM33XX_SLPCNT_VALUE_SHIFT			16
+ + #define AM33XX_SLPCNT_VALUE_MASK			(0xff << 16)
+ + 
+ + /* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
+ + #define AM33XX_SRAMLDO_STATUS_SHIFT			8
+ + #define AM33XX_SRAMLDO_STATUS_MASK			(1 << 8)
+ + 
+ + /* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
+ + #define AM33XX_SRAM_IN_TRANSITION_SHIFT			9
+ + #define AM33XX_SRAM_IN_TRANSITION_MASK			(1 << 9)
+ + 
+ + /* Used by PRM_SRAM_COUNT */
+ + #define AM33XX_STARTUP_COUNT_SHIFT			24
+ + #define AM33XX_STARTUP_COUNT_MASK			(0xff << 24)
+ + 
+ + /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+ + #define AM33XX_TRANSITION_EN_SHIFT			8
+ + #define AM33XX_TRANSITION_EN_MASK			(1 << 8)
+ + 
+ + /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+ + #define AM33XX_TRANSITION_ST_SHIFT			8
+ + #define AM33XX_TRANSITION_ST_MASK			(1 << 8)
+ + 
+ + /* Used by PRM_SRAM_COUNT */
+ + #define AM33XX_VSETUPCNT_VALUE_SHIFT			8
+ + #define AM33XX_VSETUPCNT_VALUE_MASK			(0xff << 8)
+ + 
+ + /* Used by PRM_RSTST */
+ + #define AM33XX_WDT0_RST_SHIFT				3
+ + #define AM33XX_WDT0_RST_MASK				(1 << 3)
+ + 
+ + /* Used by PRM_RSTST */
+ + #define AM33XX_WDT1_RST_SHIFT				4
+ + #define AM33XX_WDT1_RST_MASK				(1 << 4)
+ + 
+ + /* Used by RM_WKUP_RSTCTRL */
+ + #define AM33XX_WKUP_M3_LRST_SHIFT			3
+ + #define AM33XX_WKUP_M3_LRST_MASK			(1 << 3)
+ + 
+ + /* Renamed from WKUP_M3_LRST Used by RM_WKUP_RSTST */
+ + #define AM33XX_WKUP_M3_LRST_5_5_SHIFT			5
+ + #define AM33XX_WKUP_M3_LRST_5_5_MASK			(1 << 5)
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/prm-regbits-34xx.h linux-3.2.1/arch/arm/mach-ckb_3352/prm-regbits-34xx.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/prm-regbits-34xx.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/prm-regbits-34xx.h	2014-11-25 13:19:15.059580881 +0900
+ ***************
+ *** 0 ****
+ --- 1,600 ----
+ + /*
+ +  * OMAP3430 Power/Reset Management register bits
+ +  *
+ +  * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ +  * Copyright (C) 2007-2008 Nokia Corporation
+ +  *
+ +  * Written by Paul Walmsley
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
+ + #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
+ + 
+ + 
+ + #include "prm2xxx_3xxx.h"
+ + 
+ + /* Shared register bits */
+ + 
+ + /* PRM_VC_CMD_VAL_0, PRM_VC_CMD_VAL_1 shared bits */
+ + #define OMAP3430_ON_SHIFT				24
+ + #define OMAP3430_ON_MASK				(0xff << 24)
+ + #define OMAP3430_ONLP_SHIFT				16
+ + #define OMAP3430_ONLP_MASK				(0xff << 16)
+ + #define OMAP3430_RET_SHIFT				8
+ + #define OMAP3430_RET_MASK				(0xff << 8)
+ + #define OMAP3430_OFF_SHIFT				0
+ + #define OMAP3430_OFF_MASK				(0xff << 0)
+ + 
+ + /* PRM_VP1_CONFIG, PRM_VP2_CONFIG shared bits */
+ + #define OMAP3430_ERROROFFSET_SHIFT			24
+ + #define OMAP3430_ERROROFFSET_MASK			(0xff << 24)
+ + #define OMAP3430_ERRORGAIN_SHIFT			16
+ + #define OMAP3430_ERRORGAIN_MASK				(0xff << 16)
+ + #define OMAP3430_INITVOLTAGE_SHIFT			8
+ + #define OMAP3430_INITVOLTAGE_MASK			(0xff << 8)
+ + #define OMAP3430_TIMEOUTEN_MASK				(1 << 3)
+ + #define OMAP3430_INITVDD_MASK				(1 << 2)
+ + #define OMAP3430_FORCEUPDATE_MASK			(1 << 1)
+ + #define OMAP3430_VPENABLE_MASK				(1 << 0)
+ + 
+ + /* PRM_VP1_VSTEPMIN, PRM_VP2_VSTEPMIN shared bits */
+ + #define OMAP3430_SMPSWAITTIMEMIN_SHIFT			8
+ + #define OMAP3430_SMPSWAITTIMEMIN_MASK			(0xffff << 8)
+ + #define OMAP3430_VSTEPMIN_SHIFT				0
+ + #define OMAP3430_VSTEPMIN_MASK				(0xff << 0)
+ + 
+ + /* PRM_VP1_VSTEPMAX, PRM_VP2_VSTEPMAX shared bits */
+ + #define OMAP3430_SMPSWAITTIMEMAX_SHIFT			8
+ + #define OMAP3430_SMPSWAITTIMEMAX_MASK			(0xffff << 8)
+ + #define OMAP3430_VSTEPMAX_SHIFT				0
+ + #define OMAP3430_VSTEPMAX_MASK				(0xff << 0)
+ + 
+ + /* PRM_VP1_VLIMITTO, PRM_VP2_VLIMITTO shared bits */
+ + #define OMAP3430_VDDMAX_SHIFT				24
+ + #define OMAP3430_VDDMAX_MASK				(0xff << 24)
+ + #define OMAP3430_VDDMIN_SHIFT				16
+ + #define OMAP3430_VDDMIN_MASK				(0xff << 16)
+ + #define OMAP3430_TIMEOUT_SHIFT				0
+ + #define OMAP3430_TIMEOUT_MASK				(0xffff << 0)
+ + 
+ + /* PRM_VP1_VOLTAGE, PRM_VP2_VOLTAGE shared bits */
+ + #define OMAP3430_VPVOLTAGE_SHIFT			0
+ + #define OMAP3430_VPVOLTAGE_MASK				(0xff << 0)
+ + 
+ + /* PRM_VP1_STATUS, PRM_VP2_STATUS shared bits */
+ + #define OMAP3430_VPINIDLE_MASK				(1 << 0)
+ + 
+ + /* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */
+ + #define OMAP3430_EN_PER_SHIFT				7
+ + #define OMAP3430_EN_PER_MASK				(1 << 7)
+ + 
+ + /* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */
+ + #define OMAP3430_MEMORYCHANGE_MASK			(1 << 3)
+ + 
+ + /* PM_PWSTST_IVA2, PM_PWSTST_CORE shared bits */
+ + #define OMAP3430_LOGICSTATEST_MASK			(1 << 2)
+ + 
+ + /* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */
+ + #define OMAP3430_LASTLOGICSTATEENTERED_MASK		(1 << 2)
+ + 
+ + /*
+ +  * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE,
+ +  * PM_PREPWSTST_GFX, PM_PREPWSTST_DSS, PM_PREPWSTST_CAM,
+ +  * PM_PREPWSTST_PER, PM_PREPWSTST_NEON shared bits
+ +  */
+ + #define OMAP3430_LASTPOWERSTATEENTERED_SHIFT		0
+ + #define OMAP3430_LASTPOWERSTATEENTERED_MASK		(0x3 << 0)
+ + 
+ + /* PRM_IRQSTATUS_IVA2, PRM_IRQSTATUS_MPU shared bits */
+ + #define OMAP3430_WKUP_ST_MASK				(1 << 0)
+ + 
+ + /* PRM_IRQENABLE_IVA2, PRM_IRQENABLE_MPU shared bits */
+ + #define OMAP3430_WKUP_EN_MASK				(1 << 0)
+ + 
+ + /* PM_MPUGRPSEL1_CORE, PM_IVA2GRPSEL1_CORE shared bits */
+ + #define OMAP3430_GRPSEL_MMC2_MASK			(1 << 25)
+ + #define OMAP3430_GRPSEL_MMC1_MASK			(1 << 24)
+ + #define OMAP3430_GRPSEL_MCSPI4_MASK			(1 << 21)
+ + #define OMAP3430_GRPSEL_MCSPI3_MASK			(1 << 20)
+ + #define OMAP3430_GRPSEL_MCSPI2_MASK			(1 << 19)
+ + #define OMAP3430_GRPSEL_MCSPI1_MASK			(1 << 18)
+ + #define OMAP3430_GRPSEL_I2C3_SHIFT			17
+ + #define OMAP3430_GRPSEL_I2C3_MASK			(1 << 17)
+ + #define OMAP3430_GRPSEL_I2C2_SHIFT			16
+ + #define OMAP3430_GRPSEL_I2C2_MASK			(1 << 16)
+ + #define OMAP3430_GRPSEL_I2C1_SHIFT			15
+ + #define OMAP3430_GRPSEL_I2C1_MASK			(1 << 15)
+ + #define OMAP3430_GRPSEL_UART2_MASK			(1 << 14)
+ + #define OMAP3430_GRPSEL_UART1_MASK			(1 << 13)
+ + #define OMAP3430_GRPSEL_GPT11_MASK			(1 << 12)
+ + #define OMAP3430_GRPSEL_GPT10_MASK			(1 << 11)
+ + #define OMAP3430_GRPSEL_MCBSP5_MASK			(1 << 10)
+ + #define OMAP3430_GRPSEL_MCBSP1_MASK			(1 << 9)
+ + #define OMAP3430_GRPSEL_HSOTGUSB_MASK			(1 << 4)
+ + #define OMAP3430_GRPSEL_D2D_MASK			(1 << 3)
+ + 
+ + /*
+ +  * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM,
+ +  * PM_PWSTCTRL_PER shared bits
+ +  */
+ + #define OMAP3430_MEMONSTATE_SHIFT			16
+ + #define OMAP3430_MEMONSTATE_MASK			(0x3 << 16)
+ + #define OMAP3430_MEMRETSTATE_MASK			(1 << 8)
+ + 
+ + /* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */
+ + #define OMAP3630_GRPSEL_UART4_MASK			(1 << 18)
+ + #define OMAP3430_GRPSEL_GPIO6_MASK			(1 << 17)
+ + #define OMAP3430_GRPSEL_GPIO5_MASK			(1 << 16)
+ + #define OMAP3430_GRPSEL_GPIO4_MASK			(1 << 15)
+ + #define OMAP3430_GRPSEL_GPIO3_MASK			(1 << 14)
+ + #define OMAP3430_GRPSEL_GPIO2_MASK			(1 << 13)
+ + #define OMAP3430_GRPSEL_UART3_MASK			(1 << 11)
+ + #define OMAP3430_GRPSEL_GPT9_MASK			(1 << 10)
+ + #define OMAP3430_GRPSEL_GPT8_MASK			(1 << 9)
+ + #define OMAP3430_GRPSEL_GPT7_MASK			(1 << 8)
+ + #define OMAP3430_GRPSEL_GPT6_MASK			(1 << 7)
+ + #define OMAP3430_GRPSEL_GPT5_MASK			(1 << 6)
+ + #define OMAP3430_GRPSEL_GPT4_MASK			(1 << 5)
+ + #define OMAP3430_GRPSEL_GPT3_MASK			(1 << 4)
+ + #define OMAP3430_GRPSEL_GPT2_MASK			(1 << 3)
+ + #define OMAP3430_GRPSEL_MCBSP4_MASK			(1 << 2)
+ + #define OMAP3430_GRPSEL_MCBSP3_MASK			(1 << 1)
+ + #define OMAP3430_GRPSEL_MCBSP2_MASK			(1 << 0)
+ + 
+ + /* PM_MPUGRPSEL_WKUP, PM_IVA2GRPSEL_WKUP shared bits */
+ + #define OMAP3430_GRPSEL_IO_MASK				(1 << 8)
+ + #define OMAP3430_GRPSEL_SR2_MASK			(1 << 7)
+ + #define OMAP3430_GRPSEL_SR1_MASK			(1 << 6)
+ + #define OMAP3430_GRPSEL_GPIO1_MASK			(1 << 3)
+ + #define OMAP3430_GRPSEL_GPT12_MASK			(1 << 1)
+ + #define OMAP3430_GRPSEL_GPT1_MASK			(1 << 0)
+ + 
+ + /* Bits specific to each register */
+ + 
+ + /* RM_RSTCTRL_IVA2 */
+ + #define OMAP3430_RST3_IVA2_MASK				(1 << 2)
+ + #define OMAP3430_RST2_IVA2_MASK				(1 << 1)
+ + #define OMAP3430_RST1_IVA2_MASK				(1 << 0)
+ + 
+ + /* RM_RSTST_IVA2 specific bits */
+ + #define OMAP3430_EMULATION_VSEQ_RST_MASK		(1 << 13)
+ + #define OMAP3430_EMULATION_VHWA_RST_MASK		(1 << 12)
+ + #define OMAP3430_EMULATION_IVA2_RST_MASK		(1 << 11)
+ + #define OMAP3430_IVA2_SW_RST3_MASK			(1 << 10)
+ + #define OMAP3430_IVA2_SW_RST2_MASK			(1 << 9)
+ + #define OMAP3430_IVA2_SW_RST1_MASK			(1 << 8)
+ + 
+ + /* PM_WKDEP_IVA2 specific bits */
+ + 
+ + /* PM_PWSTCTRL_IVA2 specific bits */
+ + #define OMAP3430_L2FLATMEMONSTATE_SHIFT			22
+ + #define OMAP3430_L2FLATMEMONSTATE_MASK			(0x3 << 22)
+ + #define OMAP3430_SHAREDL2CACHEFLATONSTATE_SHIFT		20
+ + #define OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK		(0x3 << 20)
+ + #define OMAP3430_L1FLATMEMONSTATE_SHIFT			18
+ + #define OMAP3430_L1FLATMEMONSTATE_MASK			(0x3 << 18)
+ + #define OMAP3430_SHAREDL1CACHEFLATONSTATE_SHIFT		16
+ + #define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK		(0x3 << 16)
+ + #define OMAP3430_L2FLATMEMRETSTATE_MASK			(1 << 11)
+ + #define OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK		(1 << 10)
+ + #define OMAP3430_L1FLATMEMRETSTATE_MASK			(1 << 9)
+ + #define OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK		(1 << 8)
+ + 
+ + /* PM_PWSTST_IVA2 specific bits */
+ + #define OMAP3430_L2FLATMEMSTATEST_SHIFT			10
+ + #define OMAP3430_L2FLATMEMSTATEST_MASK			(0x3 << 10)
+ + #define OMAP3430_SHAREDL2CACHEFLATSTATEST_SHIFT		8
+ + #define OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK		(0x3 << 8)
+ + #define OMAP3430_L1FLATMEMSTATEST_SHIFT			6
+ + #define OMAP3430_L1FLATMEMSTATEST_MASK			(0x3 << 6)
+ + #define OMAP3430_SHAREDL1CACHEFLATSTATEST_SHIFT		4
+ + #define OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK		(0x3 << 4)
+ + 
+ + /* PM_PREPWSTST_IVA2 specific bits */
+ + #define OMAP3430_LASTL2FLATMEMSTATEENTERED_SHIFT		10
+ + #define OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK			(0x3 << 10)
+ + #define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_SHIFT	8
+ + #define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK		(0x3 << 8)
+ + #define OMAP3430_LASTL1FLATMEMSTATEENTERED_SHIFT		6
+ + #define OMAP3430_LASTL1FLATMEMSTATEENTERED_MASK			(0x3 << 6)
+ + #define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_SHIFT	4
+ + #define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_MASK		(0x3 << 4)
+ + 
+ + /* PRM_IRQSTATUS_IVA2 specific bits */
+ + #define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST_MASK	(1 << 2)
+ + #define OMAP3430_FORCEWKUP_ST_MASK			(1 << 1)
+ + 
+ + /* PRM_IRQENABLE_IVA2 specific bits */
+ + #define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN_MASK	(1 << 2)
+ + #define OMAP3430_FORCEWKUP_EN_MASK				(1 << 1)
+ + 
+ + /* PRM_REVISION specific bits */
+ + 
+ + /* PRM_SYSCONFIG specific bits */
+ + 
+ + /* PRM_IRQSTATUS_MPU specific bits */
+ + #define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT		25
+ + #define OMAP3430ES2_SND_PERIPH_DPLL_ST_MASK		(1 << 25)
+ + #define OMAP3430_VC_TIMEOUTERR_ST_MASK			(1 << 24)
+ + #define OMAP3430_VC_RAERR_ST_MASK			(1 << 23)
+ + #define OMAP3430_VC_SAERR_ST_MASK			(1 << 22)
+ + #define OMAP3430_VP2_TRANXDONE_ST_MASK			(1 << 21)
+ + #define OMAP3430_VP2_EQVALUE_ST_MASK			(1 << 20)
+ + #define OMAP3430_VP2_NOSMPSACK_ST_MASK			(1 << 19)
+ + #define OMAP3430_VP2_MAXVDD_ST_MASK			(1 << 18)
+ + #define OMAP3430_VP2_MINVDD_ST_MASK			(1 << 17)
+ + #define OMAP3430_VP2_OPPCHANGEDONE_ST_MASK		(1 << 16)
+ + #define OMAP3430_VP1_TRANXDONE_ST_MASK			(1 << 15)
+ + #define OMAP3430_VP1_EQVALUE_ST_MASK			(1 << 14)
+ + #define OMAP3430_VP1_NOSMPSACK_ST_MASK			(1 << 13)
+ + #define OMAP3430_VP1_MAXVDD_ST_MASK			(1 << 12)
+ + #define OMAP3430_VP1_MINVDD_ST_MASK			(1 << 11)
+ + #define OMAP3430_VP1_OPPCHANGEDONE_ST_MASK		(1 << 10)
+ + #define OMAP3430_IO_ST_MASK				(1 << 9)
+ + #define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_MASK	(1 << 8)
+ + #define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT	8
+ + #define OMAP3430_MPU_DPLL_ST_MASK			(1 << 7)
+ + #define OMAP3430_MPU_DPLL_ST_SHIFT			7
+ + #define OMAP3430_PERIPH_DPLL_ST_MASK			(1 << 6)
+ + #define OMAP3430_PERIPH_DPLL_ST_SHIFT			6
+ + #define OMAP3430_CORE_DPLL_ST_MASK			(1 << 5)
+ + #define OMAP3430_CORE_DPLL_ST_SHIFT			5
+ + #define OMAP3430_TRANSITION_ST_MASK			(1 << 4)
+ + #define OMAP3430_EVGENOFF_ST_MASK			(1 << 3)
+ + #define OMAP3430_EVGENON_ST_MASK			(1 << 2)
+ + #define OMAP3430_FS_USB_WKUP_ST_MASK			(1 << 1)
+ + 
+ + /* PRM_IRQENABLE_MPU specific bits */
+ + #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT		25
+ + #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_MASK		(1 << 25)
+ + #define OMAP3430_VC_TIMEOUTERR_EN_MASK				(1 << 24)
+ + #define OMAP3430_VC_RAERR_EN_MASK				(1 << 23)
+ + #define OMAP3430_VC_SAERR_EN_MASK				(1 << 22)
+ + #define OMAP3430_VP2_TRANXDONE_EN_MASK				(1 << 21)
+ + #define OMAP3430_VP2_EQVALUE_EN_MASK				(1 << 20)
+ + #define OMAP3430_VP2_NOSMPSACK_EN_MASK				(1 << 19)
+ + #define OMAP3430_VP2_MAXVDD_EN_MASK				(1 << 18)
+ + #define OMAP3430_VP2_MINVDD_EN_MASK				(1 << 17)
+ + #define OMAP3430_VP2_OPPCHANGEDONE_EN_MASK			(1 << 16)
+ + #define OMAP3430_VP1_TRANXDONE_EN_MASK				(1 << 15)
+ + #define OMAP3430_VP1_EQVALUE_EN_MASK				(1 << 14)
+ + #define OMAP3430_VP1_NOSMPSACK_EN_MASK				(1 << 13)
+ + #define OMAP3430_VP1_MAXVDD_EN_MASK				(1 << 12)
+ + #define OMAP3430_VP1_MINVDD_EN_MASK				(1 << 11)
+ + #define OMAP3430_VP1_OPPCHANGEDONE_EN_MASK			(1 << 10)
+ + #define OMAP3430_IO_EN_MASK					(1 << 9)
+ + #define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_MASK	(1 << 8)
+ + #define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT	8
+ + #define OMAP3430_MPU_DPLL_RECAL_EN_MASK				(1 << 7)
+ + #define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT			7
+ + #define OMAP3430_PERIPH_DPLL_RECAL_EN_MASK			(1 << 6)
+ + #define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT			6
+ + #define OMAP3430_CORE_DPLL_RECAL_EN_MASK			(1 << 5)
+ + #define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT			5
+ + #define OMAP3430_TRANSITION_EN_MASK				(1 << 4)
+ + #define OMAP3430_EVGENOFF_EN_MASK				(1 << 3)
+ + #define OMAP3430_EVGENON_EN_MASK				(1 << 2)
+ + #define OMAP3430_FS_USB_WKUP_EN_MASK				(1 << 1)
+ + 
+ + /* RM_RSTST_MPU specific bits */
+ + #define OMAP3430_EMULATION_MPU_RST_MASK			(1 << 11)
+ + 
+ + /* PM_WKDEP_MPU specific bits */
+ + #define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT		5
+ + #define OMAP3430_PM_WKDEP_MPU_EN_DSS_MASK		(1 << 5)
+ + #define OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT		2
+ + #define OMAP3430_PM_WKDEP_MPU_EN_IVA2_MASK		(1 << 2)
+ + 
+ + /* PM_EVGENCTRL_MPU */
+ + #define OMAP3430_OFFLOADMODE_SHIFT			3
+ + #define OMAP3430_OFFLOADMODE_MASK			(0x3 << 3)
+ + #define OMAP3430_ONLOADMODE_SHIFT			1
+ + #define OMAP3430_ONLOADMODE_MASK			(0x3 << 1)
+ + #define OMAP3430_ENABLE_MASK				(1 << 0)
+ + 
+ + /* PM_EVGENONTIM_MPU */
+ + #define OMAP3430_ONTIMEVAL_SHIFT			0
+ + #define OMAP3430_ONTIMEVAL_MASK				(0xffffffff << 0)
+ + 
+ + /* PM_EVGENOFFTIM_MPU */
+ + #define OMAP3430_OFFTIMEVAL_SHIFT			0
+ + #define OMAP3430_OFFTIMEVAL_MASK			(0xffffffff << 0)
+ + 
+ + /* PM_PWSTCTRL_MPU specific bits */
+ + #define OMAP3430_L2CACHEONSTATE_SHIFT			16
+ + #define OMAP3430_L2CACHEONSTATE_MASK			(0x3 << 16)
+ + #define OMAP3430_L2CACHERETSTATE_MASK			(1 << 8)
+ + #define OMAP3430_LOGICL1CACHERETSTATE_MASK		(1 << 2)
+ + 
+ + /* PM_PWSTST_MPU specific bits */
+ + #define OMAP3430_L2CACHESTATEST_SHIFT			6
+ + #define OMAP3430_L2CACHESTATEST_MASK			(0x3 << 6)
+ + #define OMAP3430_LOGICL1CACHESTATEST_MASK		(1 << 2)
+ + 
+ + /* PM_PREPWSTST_MPU specific bits */
+ + #define OMAP3430_LASTL2CACHESTATEENTERED_SHIFT		6
+ + #define OMAP3430_LASTL2CACHESTATEENTERED_MASK		(0x3 << 6)
+ + #define OMAP3430_LASTLOGICL1CACHESTATEENTERED_MASK	(1 << 2)
+ + 
+ + /* RM_RSTCTRL_CORE */
+ + #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK		(1 << 1)
+ + #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK		(1 << 0)
+ + 
+ + /* RM_RSTST_CORE specific bits */
+ + #define OMAP3430_MODEM_SECURITY_VIOL_RST_MASK		(1 << 10)
+ + #define OMAP3430_RM_RSTST_CORE_MODEM_SW_RSTPWRON_MASK	(1 << 9)
+ + #define OMAP3430_RM_RSTST_CORE_MODEM_SW_RST_MASK	(1 << 8)
+ + 
+ + /* PM_WKEN1_CORE specific bits */
+ + 
+ + /* PM_MPUGRPSEL1_CORE specific bits */
+ + #define OMAP3430_GRPSEL_FSHOSTUSB_MASK			(1 << 5)
+ + 
+ + /* PM_IVA2GRPSEL1_CORE specific bits */
+ + 
+ + /* PM_WKST1_CORE specific bits */
+ + 
+ + /* PM_PWSTCTRL_CORE specific bits */
+ + #define OMAP3430_MEM2ONSTATE_SHIFT			18
+ + #define OMAP3430_MEM2ONSTATE_MASK			(0x3 << 18)
+ + #define OMAP3430_MEM1ONSTATE_SHIFT			16
+ + #define OMAP3430_MEM1ONSTATE_MASK			(0x3 << 16)
+ + #define OMAP3430_MEM2RETSTATE_MASK			(1 << 9)
+ + #define OMAP3430_MEM1RETSTATE_MASK			(1 << 8)
+ + 
+ + /* PM_PWSTST_CORE specific bits */
+ + #define OMAP3430_MEM2STATEST_SHIFT			6
+ + #define OMAP3430_MEM2STATEST_MASK			(0x3 << 6)
+ + #define OMAP3430_MEM1STATEST_SHIFT			4
+ + #define OMAP3430_MEM1STATEST_MASK			(0x3 << 4)
+ + 
+ + /* PM_PREPWSTST_CORE specific bits */
+ + #define OMAP3430_LASTMEM2STATEENTERED_SHIFT		6
+ + #define OMAP3430_LASTMEM2STATEENTERED_MASK		(0x3 << 6)
+ + #define OMAP3430_LASTMEM1STATEENTERED_SHIFT		4
+ + #define OMAP3430_LASTMEM1STATEENTERED_MASK		(0x3 << 4)
+ + 
+ + /* RM_RSTST_GFX specific bits */
+ + 
+ + /* PM_WKDEP_GFX specific bits */
+ + #define OMAP3430_PM_WKDEP_GFX_EN_IVA2_MASK		(1 << 2)
+ + 
+ + /* PM_PWSTCTRL_GFX specific bits */
+ + 
+ + /* PM_PWSTST_GFX specific bits */
+ + 
+ + /* PM_PREPWSTST_GFX specific bits */
+ + 
+ + /* PM_WKEN_WKUP specific bits */
+ + #define OMAP3430_EN_IO_CHAIN_MASK			(1 << 16)
+ + #define OMAP3430_EN_IO_MASK				(1 << 8)
+ + #define OMAP3430_EN_GPIO1_MASK				(1 << 3)
+ + 
+ + /* PM_MPUGRPSEL_WKUP specific bits */
+ + 
+ + /* PM_IVA2GRPSEL_WKUP specific bits */
+ + 
+ + /* PM_WKST_WKUP specific bits */
+ + #define OMAP3430_ST_IO_CHAIN_MASK			(1 << 16)
+ + #define OMAP3430_ST_IO_MASK				(1 << 8)
+ + 
+ + /* PRM_CLKSEL */
+ + #define OMAP3430_SYS_CLKIN_SEL_SHIFT			0
+ + #define OMAP3430_SYS_CLKIN_SEL_MASK			(0x7 << 0)
+ + 
+ + /* PRM_CLKOUT_CTRL */
+ + #define OMAP3430_CLKOUT_EN_MASK				(1 << 7)
+ + #define OMAP3430_CLKOUT_EN_SHIFT			7
+ + 
+ + /* RM_RSTST_DSS specific bits */
+ + 
+ + /* PM_WKEN_DSS */
+ + #define OMAP3430_PM_WKEN_DSS_EN_DSS_MASK		(1 << 0)
+ + 
+ + /* PM_WKDEP_DSS specific bits */
+ + #define OMAP3430_PM_WKDEP_DSS_EN_IVA2_MASK		(1 << 2)
+ + 
+ + /* PM_PWSTCTRL_DSS specific bits */
+ + 
+ + /* PM_PWSTST_DSS specific bits */
+ + 
+ + /* PM_PREPWSTST_DSS specific bits */
+ + 
+ + /* RM_RSTST_CAM specific bits */
+ + 
+ + /* PM_WKDEP_CAM specific bits */
+ + #define OMAP3430_PM_WKDEP_CAM_EN_IVA2_MASK		(1 << 2)
+ + 
+ + /* PM_PWSTCTRL_CAM specific bits */
+ + 
+ + /* PM_PWSTST_CAM specific bits */
+ + 
+ + /* PM_PREPWSTST_CAM specific bits */
+ + 
+ + /* PM_PWSTCTRL_USBHOST specific bits */
+ + #define OMAP3430ES2_SAVEANDRESTORE_SHIFT		4
+ + 
+ + /* RM_RSTST_PER specific bits */
+ + 
+ + /* PM_WKEN_PER specific bits */
+ + 
+ + /* PM_MPUGRPSEL_PER specific bits */
+ + 
+ + /* PM_IVA2GRPSEL_PER specific bits */
+ + 
+ + /* PM_WKST_PER specific bits */
+ + 
+ + /* PM_WKDEP_PER specific bits */
+ + #define OMAP3430_PM_WKDEP_PER_EN_IVA2_MASK		(1 << 2)
+ + 
+ + /* PM_PWSTCTRL_PER specific bits */
+ + 
+ + /* PM_PWSTST_PER specific bits */
+ + 
+ + /* PM_PREPWSTST_PER specific bits */
+ + 
+ + /* RM_RSTST_EMU specific bits */
+ + 
+ + /* PM_PWSTST_EMU specific bits */
+ + 
+ + /* PRM_VC_SMPS_SA */
+ + #define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT		16
+ + #define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK		(0x7f << 16)
+ + #define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT		0
+ + #define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK		(0x7f << 0)
+ + 
+ + /* PRM_VC_SMPS_VOL_RA */
+ + #define OMAP3430_VOLRA1_SHIFT				16
+ + #define OMAP3430_VOLRA1_MASK				(0xff << 16)
+ + #define OMAP3430_VOLRA0_SHIFT				0
+ + #define OMAP3430_VOLRA0_MASK				(0xff << 0)
+ + 
+ + /* PRM_VC_SMPS_CMD_RA */
+ + #define OMAP3430_CMDRA1_SHIFT				16
+ + #define OMAP3430_CMDRA1_MASK				(0xff << 16)
+ + #define OMAP3430_CMDRA0_SHIFT				0
+ + #define OMAP3430_CMDRA0_MASK				(0xff << 0)
+ + 
+ + /* PRM_VC_CMD_VAL_0 specific bits */
+ + #define OMAP3430_VC_CMD_ON_SHIFT			24
+ + #define OMAP3430_VC_CMD_ON_MASK				(0xFF << 24)
+ + #define OMAP3430_VC_CMD_ONLP_SHIFT			16
+ + #define OMAP3430_VC_CMD_ONLP_MASK			(0xFF << 16)
+ + #define OMAP3430_VC_CMD_RET_SHIFT			8
+ + #define OMAP3430_VC_CMD_RET_MASK			(0xFF << 8)
+ + #define OMAP3430_VC_CMD_OFF_SHIFT			0
+ + #define OMAP3430_VC_CMD_OFF_MASK			(0xFF << 0)
+ + 
+ + /* PRM_VC_CMD_VAL_1 specific bits */
+ + 
+ + /* PRM_VC_CH_CONF */
+ + #define OMAP3430_CMD1_MASK				(1 << 20)
+ + #define OMAP3430_RACEN1_MASK				(1 << 19)
+ + #define OMAP3430_RAC1_MASK				(1 << 18)
+ + #define OMAP3430_RAV1_MASK				(1 << 17)
+ + #define OMAP3430_PRM_VC_CH_CONF_SA1_MASK		(1 << 16)
+ + #define OMAP3430_CMD0_MASK				(1 << 4)
+ + #define OMAP3430_RACEN0_MASK				(1 << 3)
+ + #define OMAP3430_RAC0_MASK				(1 << 2)
+ + #define OMAP3430_RAV0_MASK				(1 << 1)
+ + #define OMAP3430_PRM_VC_CH_CONF_SA0_MASK		(1 << 0)
+ + 
+ + /* PRM_VC_I2C_CFG */
+ + #define OMAP3430_HSMASTER_MASK				(1 << 5)
+ + #define OMAP3430_SREN_MASK				(1 << 4)
+ + #define OMAP3430_HSEN_MASK				(1 << 3)
+ + #define OMAP3430_MCODE_SHIFT				0
+ + #define OMAP3430_MCODE_MASK				(0x7 << 0)
+ + 
+ + /* PRM_VC_BYPASS_VAL */
+ + #define OMAP3430_VALID_MASK				(1 << 24)
+ + #define OMAP3430_DATA_SHIFT				16
+ + #define OMAP3430_DATA_MASK				(0xff << 16)
+ + #define OMAP3430_REGADDR_SHIFT				8
+ + #define OMAP3430_REGADDR_MASK				(0xff << 8)
+ + #define OMAP3430_SLAVEADDR_SHIFT			0
+ + #define OMAP3430_SLAVEADDR_MASK				(0x7f << 0)
+ + 
+ + /* PRM_RSTCTRL */
+ + #define OMAP3430_RST_DPLL3_MASK				(1 << 2)
+ + #define OMAP3430_RST_GS_MASK				(1 << 1)
+ + 
+ + /* PRM_RSTTIME */
+ + #define OMAP3430_RSTTIME2_SHIFT				8
+ + #define OMAP3430_RSTTIME2_MASK				(0x1f << 8)
+ + #define OMAP3430_RSTTIME1_SHIFT				0
+ + #define OMAP3430_RSTTIME1_MASK				(0xff << 0)
+ + 
+ + /* PRM_RSTST */
+ + #define OMAP3430_ICECRUSHER_RST_MASK			(1 << 10)
+ + #define OMAP3430_ICEPICK_RST_MASK			(1 << 9)
+ + #define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_MASK		(1 << 8)
+ + #define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_MASK		(1 << 7)
+ + #define OMAP3430_EXTERNAL_WARM_RST_MASK			(1 << 6)
+ + #define OMAP3430_SECURE_WD_RST_MASK			(1 << 5)
+ + #define OMAP3430_MPU_WD_RST_MASK			(1 << 4)
+ + #define OMAP3430_SECURITY_VIOL_RST_MASK			(1 << 3)
+ + #define OMAP3430_GLOBAL_SW_RST_MASK			(1 << 1)
+ + #define OMAP3430_GLOBAL_COLD_RST_MASK			(1 << 0)
+ + 
+ + /* PRM_VOLTCTRL */
+ + #define OMAP3430_SEL_VMODE_MASK				(1 << 4)
+ + #define OMAP3430_SEL_OFF_MASK				(1 << 3)
+ + #define OMAP3430_AUTO_OFF_MASK				(1 << 2)
+ + #define OMAP3430_AUTO_RET_MASK				(1 << 1)
+ + #define OMAP3430_AUTO_SLEEP_MASK			(1 << 0)
+ + 
+ + /* PRM_SRAM_PCHARGE */
+ + #define OMAP3430_PCHARGE_TIME_SHIFT			0
+ + #define OMAP3430_PCHARGE_TIME_MASK			(0xff << 0)
+ + 
+ + /* PRM_CLKSRC_CTRL */
+ + #define OMAP3430_SYSCLKDIV_SHIFT			6
+ + #define OMAP3430_SYSCLKDIV_MASK				(0x3 << 6)
+ + #define OMAP3430_AUTOEXTCLKMODE_SHIFT			3
+ + #define OMAP3430_AUTOEXTCLKMODE_MASK			(0x3 << 3)
+ + #define OMAP3430_SYSCLKSEL_SHIFT			0
+ + #define OMAP3430_SYSCLKSEL_MASK				(0x3 << 0)
+ + 
+ + /* PRM_VOLTSETUP1 */
+ + #define OMAP3430_SETUP_TIME2_SHIFT			16
+ + #define OMAP3430_SETUP_TIME2_MASK			(0xffff << 16)
+ + #define OMAP3430_SETUP_TIME1_SHIFT			0
+ + #define OMAP3430_SETUP_TIME1_MASK			(0xffff << 0)
+ + 
+ + /* PRM_VOLTOFFSET */
+ + #define OMAP3430_OFFSET_TIME_SHIFT			0
+ + #define OMAP3430_OFFSET_TIME_MASK			(0xffff << 0)
+ + 
+ + /* PRM_CLKSETUP */
+ + #define OMAP3430_SETUP_TIME_SHIFT			0
+ + #define OMAP3430_SETUP_TIME_MASK			(0xffff << 0)
+ + 
+ + /* PRM_POLCTRL */
+ + #define OMAP3430_OFFMODE_POL_MASK			(1 << 3)
+ + #define OMAP3430_CLKOUT_POL_MASK			(1 << 2)
+ + #define OMAP3430_CLKREQ_POL_MASK			(1 << 1)
+ + #define OMAP3430_EXTVOL_POL_MASK			(1 << 0)
+ + 
+ + /* PRM_VOLTSETUP2 */
+ + #define OMAP3430_OFFMODESETUPTIME_SHIFT			0
+ + #define OMAP3430_OFFMODESETUPTIME_MASK			(0xffff << 0)
+ + 
+ + /* PRM_VP1_CONFIG specific bits */
+ + 
+ + /* PRM_VP1_VSTEPMIN specific bits */
+ + 
+ + /* PRM_VP1_VSTEPMAX specific bits */
+ + 
+ + /* PRM_VP1_VLIMITTO specific bits */
+ + 
+ + /* PRM_VP1_VOLTAGE specific bits */
+ + 
+ + /* PRM_VP1_STATUS specific bits */
+ + 
+ + /* PRM_VP2_CONFIG specific bits */
+ + 
+ + /* PRM_VP2_VSTEPMIN specific bits */
+ + 
+ + /* PRM_VP2_VSTEPMAX specific bits */
+ + 
+ + /* PRM_VP2_VLIMITTO specific bits */
+ + 
+ + /* PRM_VP2_VOLTAGE specific bits */
+ + 
+ + /* PRM_VP2_STATUS specific bits */
+ + 
+ + /* RM_RSTST_NEON specific bits */
+ + 
+ + /* PM_WKDEP_NEON specific bits */
+ + 
+ + /* PM_PWSTCTRL_NEON specific bits */
+ + 
+ + /* PM_PWSTST_NEON specific bits */
+ + 
+ + /* PM_PREPWSTST_NEON specific bits */
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/prm-regbits-44xx.h linux-3.2.1/arch/arm/mach-ckb_3352/prm-regbits-44xx.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/prm-regbits-44xx.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/prm-regbits-44xx.h	2014-11-25 13:19:15.072006029 +0900
+ ***************
+ *** 0 ****
+ --- 1,2327 ----
+ + /*
+ +  * OMAP44xx Power Management register bits
+ +  *
+ +  * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ +  * Copyright (C) 2009-2010 Nokia Corporation
+ +  *
+ +  * Paul Walmsley (paul@pwsan.com)
+ +  * Rajendra Nayak (rnayak@ti.com)
+ +  * Benoit Cousson (b-cousson@ti.com)
+ +  *
+ +  * This file is automatically generated from the OMAP hardware databases.
+ +  * We respectfully ask that any modifications to this file be coordinated
+ +  * with the public linux-omap@vger.kernel.org mailing list and the
+ +  * authors above to ensure that the autogeneration scripts are kept
+ +  * up-to-date with the file contents.
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H
+ + #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H
+ + 
+ + 
+ + /*
+ +  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
+ +  * PRM_LDO_SRAM_MPU_SETUP
+ +  */
+ + #define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT				1
+ + #define OMAP4430_ABBOFF_ACT_EXPORT_MASK					(1 << 1)
+ + 
+ + /*
+ +  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
+ +  * PRM_LDO_SRAM_MPU_SETUP
+ +  */
+ + #define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT				2
+ + #define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK				(1 << 2)
+ + 
+ + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+ + #define OMAP4430_ABB_IVA_DONE_EN_SHIFT					31
+ + #define OMAP4430_ABB_IVA_DONE_EN_MASK					(1 << 31)
+ + 
+ + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+ + #define OMAP4430_ABB_IVA_DONE_ST_SHIFT					31
+ + #define OMAP4430_ABB_IVA_DONE_ST_MASK					(1 << 31)
+ + 
+ + /* Used by PRM_IRQENABLE_MPU_2 */
+ + #define OMAP4430_ABB_MPU_DONE_EN_SHIFT					7
+ + #define OMAP4430_ABB_MPU_DONE_EN_MASK					(1 << 7)
+ + 
+ + /* Used by PRM_IRQSTATUS_MPU_2 */
+ + #define OMAP4430_ABB_MPU_DONE_ST_SHIFT					7
+ + #define OMAP4430_ABB_MPU_DONE_ST_MASK					(1 << 7)
+ + 
+ + /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
+ + #define OMAP4430_ACTIVE_FBB_SEL_SHIFT					2
+ + #define OMAP4430_ACTIVE_FBB_SEL_MASK					(1 << 2)
+ + 
+ + /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
+ + #define OMAP4430_ACTIVE_RBB_SEL_SHIFT					1
+ + #define OMAP4430_ACTIVE_RBB_SEL_MASK					(1 << 1)
+ + 
+ + /* Used by PM_ABE_PWRSTCTRL */
+ + #define OMAP4430_AESSMEM_ONSTATE_SHIFT					16
+ + #define OMAP4430_AESSMEM_ONSTATE_MASK					(0x3 << 16)
+ + 
+ + /* Used by PM_ABE_PWRSTCTRL */
+ + #define OMAP4430_AESSMEM_RETSTATE_SHIFT					8
+ + #define OMAP4430_AESSMEM_RETSTATE_MASK					(1 << 8)
+ + 
+ + /* Used by PM_ABE_PWRSTST */
+ + #define OMAP4430_AESSMEM_STATEST_SHIFT					4
+ + #define OMAP4430_AESSMEM_STATEST_MASK					(0x3 << 4)
+ + 
+ + /*
+ +  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
+ +  * PRM_LDO_SRAM_MPU_SETUP
+ +  */
+ + #define OMAP4430_AIPOFF_SHIFT						8
+ + #define OMAP4430_AIPOFF_MASK						(1 << 8)
+ + 
+ + /* Used by PRM_VOLTCTRL */
+ + #define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT				0
+ + #define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK				(0x3 << 0)
+ + 
+ + /* Used by PRM_VOLTCTRL */
+ + #define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT				4
+ + #define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK				(0x3 << 4)
+ + 
+ + /* Used by PRM_VOLTCTRL */
+ + #define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT				2
+ + #define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK				(0x3 << 2)
+ + 
+ + /* Used by PRM_VC_ERRST */
+ + #define OMAP4430_BYPS_RA_ERR_SHIFT					25
+ + #define OMAP4430_BYPS_RA_ERR_MASK					(1 << 25)
+ + 
+ + /* Used by PRM_VC_ERRST */
+ + #define OMAP4430_BYPS_SA_ERR_SHIFT					24
+ + #define OMAP4430_BYPS_SA_ERR_MASK					(1 << 24)
+ + 
+ + /* Used by PRM_VC_ERRST */
+ + #define OMAP4430_BYPS_TIMEOUT_ERR_SHIFT					26
+ + #define OMAP4430_BYPS_TIMEOUT_ERR_MASK					(1 << 26)
+ + 
+ + /* Used by PRM_RSTST */
+ + #define OMAP4430_C2C_RST_SHIFT						10
+ + #define OMAP4430_C2C_RST_MASK						(1 << 10)
+ + 
+ + /* Used by PM_CAM_PWRSTCTRL */
+ + #define OMAP4430_CAM_MEM_ONSTATE_SHIFT					16
+ + #define OMAP4430_CAM_MEM_ONSTATE_MASK					(0x3 << 16)
+ + 
+ + /* Used by PM_CAM_PWRSTST */
+ + #define OMAP4430_CAM_MEM_STATEST_SHIFT					4
+ + #define OMAP4430_CAM_MEM_STATEST_MASK					(0x3 << 4)
+ + 
+ + /* Used by PRM_CLKREQCTRL */
+ + #define OMAP4430_CLKREQ_COND_SHIFT					0
+ + #define OMAP4430_CLKREQ_COND_MASK					(0x7 << 0)
+ + 
+ + /* Used by PRM_VC_VAL_SMPS_RA_CMD */
+ + #define OMAP4430_CMDRA_VDD_CORE_L_SHIFT					0
+ + #define OMAP4430_CMDRA_VDD_CORE_L_MASK					(0xff << 0)
+ + 
+ + /* Used by PRM_VC_VAL_SMPS_RA_CMD */
+ + #define OMAP4430_CMDRA_VDD_IVA_L_SHIFT					8
+ + #define OMAP4430_CMDRA_VDD_IVA_L_MASK					(0xff << 8)
+ + 
+ + /* Used by PRM_VC_VAL_SMPS_RA_CMD */
+ + #define OMAP4430_CMDRA_VDD_MPU_L_SHIFT					16
+ + #define OMAP4430_CMDRA_VDD_MPU_L_MASK					(0xff << 16)
+ + 
+ + /* Used by PRM_VC_CFG_CHANNEL */
+ + #define OMAP4430_CMD_VDD_CORE_L_SHIFT					4
+ + #define OMAP4430_CMD_VDD_CORE_L_MASK					(1 << 4)
+ + 
+ + /* Used by PRM_VC_CFG_CHANNEL */
+ + #define OMAP4430_CMD_VDD_IVA_L_SHIFT					12
+ + #define OMAP4430_CMD_VDD_IVA_L_MASK					(1 << 12)
+ + 
+ + /* Used by PRM_VC_CFG_CHANNEL */
+ + #define OMAP4430_CMD_VDD_MPU_L_SHIFT					17
+ + #define OMAP4430_CMD_VDD_MPU_L_MASK					(1 << 17)
+ + 
+ + /* Used by PM_CORE_PWRSTCTRL */
+ + #define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT				18
+ + #define OMAP4430_CORE_OCMRAM_ONSTATE_MASK				(0x3 << 18)
+ + 
+ + /* Used by PM_CORE_PWRSTCTRL */
+ + #define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT				9
+ + #define OMAP4430_CORE_OCMRAM_RETSTATE_MASK				(1 << 9)
+ + 
+ + /* Used by PM_CORE_PWRSTST */
+ + #define OMAP4430_CORE_OCMRAM_STATEST_SHIFT				6
+ + #define OMAP4430_CORE_OCMRAM_STATEST_MASK				(0x3 << 6)
+ + 
+ + /* Used by PM_CORE_PWRSTCTRL */
+ + #define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT				16
+ + #define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK				(0x3 << 16)
+ + 
+ + /* Used by PM_CORE_PWRSTCTRL */
+ + #define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT				8
+ + #define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK				(1 << 8)
+ + 
+ + /* Used by PM_CORE_PWRSTST */
+ + #define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT				4
+ + #define OMAP4430_CORE_OTHER_BANK_STATEST_MASK				(0x3 << 4)
+ + 
+ + /* Used by REVISION_PRM */
+ + #define OMAP4430_CUSTOM_SHIFT						6
+ + #define OMAP4430_CUSTOM_MASK						(0x3 << 6)
+ + 
+ + /* Used by PRM_VC_VAL_BYPASS */
+ + #define OMAP4430_DATA_SHIFT						16
+ + #define OMAP4430_DATA_MASK						(0xff << 16)
+ + 
+ + /* Used by PRM_DEVICE_OFF_CTRL */
+ + #define OMAP4430_DEVICE_OFF_ENABLE_SHIFT				0
+ + #define OMAP4430_DEVICE_OFF_ENABLE_MASK					(1 << 0)
+ + 
+ + /* Used by PRM_VC_CFG_I2C_MODE */
+ + #define OMAP4430_DFILTEREN_SHIFT					6
+ + #define OMAP4430_DFILTEREN_MASK						(1 << 6)
+ + 
+ + /*
+ +  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
+ +  * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP
+ +  */
+ + #define OMAP4430_DISABLE_RTA_EXPORT_SHIFT				0
+ + #define OMAP4430_DISABLE_RTA_EXPORT_MASK				(1 << 0)
+ + 
+ + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */
+ + #define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT				4
+ + #define OMAP4430_DPLL_ABE_RECAL_EN_MASK					(1 << 4)
+ + 
+ + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */
+ + #define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT				4
+ + #define OMAP4430_DPLL_ABE_RECAL_ST_MASK					(1 << 4)
+ + 
+ + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+ + #define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT				0
+ + #define OMAP4430_DPLL_CORE_RECAL_EN_MASK				(1 << 0)
+ + 
+ + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+ + #define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT				0
+ + #define OMAP4430_DPLL_CORE_RECAL_ST_MASK				(1 << 0)
+ + 
+ + /* Used by PRM_IRQENABLE_MPU */
+ + #define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT				6
+ + #define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK				(1 << 6)
+ + 
+ + /* Used by PRM_IRQSTATUS_MPU */
+ + #define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT				6
+ + #define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK				(1 << 6)
+ + 
+ + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */
+ + #define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT				2
+ + #define OMAP4430_DPLL_IVA_RECAL_EN_MASK					(1 << 2)
+ + 
+ + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */
+ + #define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT				2
+ + #define OMAP4430_DPLL_IVA_RECAL_ST_MASK					(1 << 2)
+ + 
+ + /* Used by PRM_IRQENABLE_MPU */
+ + #define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT				1
+ + #define OMAP4430_DPLL_MPU_RECAL_EN_MASK					(1 << 1)
+ + 
+ + /* Used by PRM_IRQSTATUS_MPU */
+ + #define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT				1
+ + #define OMAP4430_DPLL_MPU_RECAL_ST_MASK					(1 << 1)
+ + 
+ + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+ + #define OMAP4430_DPLL_PER_RECAL_EN_SHIFT				3
+ + #define OMAP4430_DPLL_PER_RECAL_EN_MASK					(1 << 3)
+ + 
+ + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+ + #define OMAP4430_DPLL_PER_RECAL_ST_SHIFT				3
+ + #define OMAP4430_DPLL_PER_RECAL_ST_MASK					(1 << 3)
+ + 
+ + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+ + #define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT				7
+ + #define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK				(1 << 7)
+ + 
+ + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+ + #define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT				7
+ + #define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK				(1 << 7)
+ + 
+ + /* Used by PM_DSS_PWRSTCTRL */
+ + #define OMAP4430_DSS_MEM_ONSTATE_SHIFT					16
+ + #define OMAP4430_DSS_MEM_ONSTATE_MASK					(0x3 << 16)
+ + 
+ + /* Used by PM_DSS_PWRSTCTRL */
+ + #define OMAP4430_DSS_MEM_RETSTATE_SHIFT					8
+ + #define OMAP4430_DSS_MEM_RETSTATE_MASK					(1 << 8)
+ + 
+ + /* Used by PM_DSS_PWRSTST */
+ + #define OMAP4430_DSS_MEM_STATEST_SHIFT					4
+ + #define OMAP4430_DSS_MEM_STATEST_MASK					(0x3 << 4)
+ + 
+ + /* Used by PM_CORE_PWRSTCTRL */
+ + #define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT				20
+ + #define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK				(0x3 << 20)
+ + 
+ + /* Used by PM_CORE_PWRSTCTRL */
+ + #define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT				10
+ + #define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK				(1 << 10)
+ + 
+ + /* Used by PM_CORE_PWRSTST */
+ + #define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT				8
+ + #define OMAP4430_DUCATI_L2RAM_STATEST_MASK				(0x3 << 8)
+ + 
+ + /* Used by PM_CORE_PWRSTCTRL */
+ + #define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT				22
+ + #define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK				(0x3 << 22)
+ + 
+ + /* Used by PM_CORE_PWRSTCTRL */
+ + #define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT				11
+ + #define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK				(1 << 11)
+ + 
+ + /* Used by PM_CORE_PWRSTST */
+ + #define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT				10
+ + #define OMAP4430_DUCATI_UNICACHE_STATEST_MASK				(0x3 << 10)
+ + 
+ + /* Used by PRM_DEVICE_OFF_CTRL */
+ + #define OMAP4460_EMIF1_OFFWKUP_DISABLE_SHIFT				8
+ + #define OMAP4460_EMIF1_OFFWKUP_DISABLE_MASK				(1 << 8)
+ + 
+ + /* Used by PRM_DEVICE_OFF_CTRL */
+ + #define OMAP4460_EMIF2_OFFWKUP_DISABLE_SHIFT				9
+ + #define OMAP4460_EMIF2_OFFWKUP_DISABLE_MASK				(1 << 9)
+ + 
+ + /* Used by RM_MPU_RSTST */
+ + #define OMAP4430_EMULATION_RST_SHIFT					0
+ + #define OMAP4430_EMULATION_RST_MASK					(1 << 0)
+ + 
+ + /* Used by RM_DUCATI_RSTST */
+ + #define OMAP4430_EMULATION_RST1ST_SHIFT					3
+ + #define OMAP4430_EMULATION_RST1ST_MASK					(1 << 3)
+ + 
+ + /* Used by RM_DUCATI_RSTST */
+ + #define OMAP4430_EMULATION_RST2ST_SHIFT					4
+ + #define OMAP4430_EMULATION_RST2ST_MASK					(1 << 4)
+ + 
+ + /* Used by RM_IVAHD_RSTST */
+ + #define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT				3
+ + #define OMAP4430_EMULATION_SEQ1_RST1ST_MASK				(1 << 3)
+ + 
+ + /* Used by RM_IVAHD_RSTST */
+ + #define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT				4
+ + #define OMAP4430_EMULATION_SEQ2_RST2ST_MASK				(1 << 4)
+ + 
+ + /* Used by PM_EMU_PWRSTCTRL */
+ + #define OMAP4430_EMU_BANK_ONSTATE_SHIFT					16
+ + #define OMAP4430_EMU_BANK_ONSTATE_MASK					(0x3 << 16)
+ + 
+ + /* Used by PM_EMU_PWRSTST */
+ + #define OMAP4430_EMU_BANK_STATEST_SHIFT					4
+ + #define OMAP4430_EMU_BANK_STATEST_MASK					(0x3 << 4)
+ + 
+ + /*
+ +  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
+ +  * PRM_LDO_SRAM_MPU_SETUP
+ +  */
+ + #define OMAP4430_ENFUNC1_EXPORT_SHIFT					3
+ + #define OMAP4430_ENFUNC1_EXPORT_MASK					(1 << 3)
+ + 
+ + /*
+ +  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
+ +  * PRM_LDO_SRAM_MPU_SETUP
+ +  */
+ + #define OMAP4430_ENFUNC3_EXPORT_SHIFT					5
+ + #define OMAP4430_ENFUNC3_EXPORT_MASK					(1 << 5)
+ + 
+ + /*
+ +  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
+ +  * PRM_LDO_SRAM_MPU_SETUP
+ +  */
+ + #define OMAP4430_ENFUNC4_SHIFT						6
+ + #define OMAP4430_ENFUNC4_MASK						(1 << 6)
+ + 
+ + /*
+ +  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
+ +  * PRM_LDO_SRAM_MPU_SETUP
+ +  */
+ + #define OMAP4430_ENFUNC5_SHIFT						7
+ + #define OMAP4430_ENFUNC5_MASK						(1 << 7)
+ + 
+ + /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
+ + #define OMAP4430_ERRORGAIN_SHIFT					16
+ + #define OMAP4430_ERRORGAIN_MASK						(0xff << 16)
+ + 
+ + /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
+ + #define OMAP4430_ERROROFFSET_SHIFT					24
+ + #define OMAP4430_ERROROFFSET_MASK					(0xff << 24)
+ + 
+ + /* Used by PRM_RSTST */
+ + #define OMAP4430_EXTERNAL_WARM_RST_SHIFT				5
+ + #define OMAP4430_EXTERNAL_WARM_RST_MASK					(1 << 5)
+ + 
+ + /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
+ + #define OMAP4430_FORCEUPDATE_SHIFT					1
+ + #define OMAP4430_FORCEUPDATE_MASK					(1 << 1)
+ + 
+ + /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */
+ + #define OMAP4430_FORCEUPDATEWAIT_SHIFT					8
+ + #define OMAP4430_FORCEUPDATEWAIT_MASK					(0xffffff << 8)
+ + 
+ + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_TESLA */
+ + #define OMAP4430_FORCEWKUP_EN_SHIFT					10
+ + #define OMAP4430_FORCEWKUP_EN_MASK					(1 << 10)
+ + 
+ + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_TESLA */
+ + #define OMAP4430_FORCEWKUP_ST_SHIFT					10
+ + #define OMAP4430_FORCEWKUP_ST_MASK					(1 << 10)
+ + 
+ + /* Used by REVISION_PRM */
+ + #define OMAP4430_FUNC_SHIFT						16
+ + #define OMAP4430_FUNC_MASK						(0xfff << 16)
+ + 
+ + /* Used by PM_GFX_PWRSTCTRL */
+ + #define OMAP4430_GFX_MEM_ONSTATE_SHIFT					16
+ + #define OMAP4430_GFX_MEM_ONSTATE_MASK					(0x3 << 16)
+ + 
+ + /* Used by PM_GFX_PWRSTST */
+ + #define OMAP4430_GFX_MEM_STATEST_SHIFT					4
+ + #define OMAP4430_GFX_MEM_STATEST_MASK					(0x3 << 4)
+ + 
+ + /* Used by PRM_RSTST */
+ + #define OMAP4430_GLOBAL_COLD_RST_SHIFT					0
+ + #define OMAP4430_GLOBAL_COLD_RST_MASK					(1 << 0)
+ + 
+ + /* Used by PRM_RSTST */
+ + #define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT				1
+ + #define OMAP4430_GLOBAL_WARM_SW_RST_MASK				(1 << 1)
+ + 
+ + /* Used by PRM_IO_PMCTRL */
+ + #define OMAP4430_GLOBAL_WUEN_SHIFT					16
+ + #define OMAP4430_GLOBAL_WUEN_MASK					(1 << 16)
+ + 
+ + /* Used by PRM_VC_CFG_I2C_MODE */
+ + #define OMAP4430_HSMCODE_SHIFT						0
+ + #define OMAP4430_HSMCODE_MASK						(0x7 << 0)
+ + 
+ + /* Used by PRM_VC_CFG_I2C_MODE */
+ + #define OMAP4430_HSMODEEN_SHIFT						3
+ + #define OMAP4430_HSMODEEN_MASK						(1 << 3)
+ + 
+ + /* Used by PRM_VC_CFG_I2C_CLK */
+ + #define OMAP4430_HSSCLH_SHIFT						16
+ + #define OMAP4430_HSSCLH_MASK						(0xff << 16)
+ + 
+ + /* Used by PRM_VC_CFG_I2C_CLK */
+ + #define OMAP4430_HSSCLL_SHIFT						24
+ + #define OMAP4430_HSSCLL_MASK						(0xff << 24)
+ + 
+ + /* Used by PM_IVAHD_PWRSTCTRL */
+ + #define OMAP4430_HWA_MEM_ONSTATE_SHIFT					16
+ + #define OMAP4430_HWA_MEM_ONSTATE_MASK					(0x3 << 16)
+ + 
+ + /* Used by PM_IVAHD_PWRSTCTRL */
+ + #define OMAP4430_HWA_MEM_RETSTATE_SHIFT					8
+ + #define OMAP4430_HWA_MEM_RETSTATE_MASK					(1 << 8)
+ + 
+ + /* Used by PM_IVAHD_PWRSTST */
+ + #define OMAP4430_HWA_MEM_STATEST_SHIFT					4
+ + #define OMAP4430_HWA_MEM_STATEST_MASK					(0x3 << 4)
+ + 
+ + /* Used by RM_MPU_RSTST */
+ + #define OMAP4430_ICECRUSHER_MPU_RST_SHIFT				1
+ + #define OMAP4430_ICECRUSHER_MPU_RST_MASK				(1 << 1)
+ + 
+ + /* Used by RM_DUCATI_RSTST */
+ + #define OMAP4430_ICECRUSHER_RST1ST_SHIFT				5
+ + #define OMAP4430_ICECRUSHER_RST1ST_MASK					(1 << 5)
+ + 
+ + /* Used by RM_DUCATI_RSTST */
+ + #define OMAP4430_ICECRUSHER_RST2ST_SHIFT				6
+ + #define OMAP4430_ICECRUSHER_RST2ST_MASK					(1 << 6)
+ + 
+ + /* Used by RM_IVAHD_RSTST */
+ + #define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT				5
+ + #define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK				(1 << 5)
+ + 
+ + /* Used by RM_IVAHD_RSTST */
+ + #define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT				6
+ + #define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK				(1 << 6)
+ + 
+ + /* Used by PRM_RSTST */
+ + #define OMAP4430_ICEPICK_RST_SHIFT					9
+ + #define OMAP4430_ICEPICK_RST_MASK					(1 << 9)
+ + 
+ + /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
+ + #define OMAP4430_INITVDD_SHIFT						2
+ + #define OMAP4430_INITVDD_MASK						(1 << 2)
+ + 
+ + /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
+ + #define OMAP4430_INITVOLTAGE_SHIFT					8
+ + #define OMAP4430_INITVOLTAGE_MASK					(0xff << 8)
+ + 
+ + /*
+ +  * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST,
+ +  * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST,
+ +  * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
+ +  */
+ + #define OMAP4430_INTRANSITION_SHIFT					20
+ + #define OMAP4430_INTRANSITION_MASK					(1 << 20)
+ + 
+ + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+ + #define OMAP4430_IO_EN_SHIFT						9
+ + #define OMAP4430_IO_EN_MASK						(1 << 9)
+ + 
+ + /* Used by PRM_IO_PMCTRL */
+ + #define OMAP4430_IO_ON_STATUS_SHIFT					5
+ + #define OMAP4430_IO_ON_STATUS_MASK					(1 << 5)
+ + 
+ + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+ + #define OMAP4430_IO_ST_SHIFT						9
+ + #define OMAP4430_IO_ST_MASK						(1 << 9)
+ + 
+ + /* Used by PRM_IO_PMCTRL */
+ + #define OMAP4430_ISOCLK_OVERRIDE_SHIFT					0
+ + #define OMAP4430_ISOCLK_OVERRIDE_MASK					(1 << 0)
+ + 
+ + /* Used by PRM_IO_PMCTRL */
+ + #define OMAP4430_ISOCLK_STATUS_SHIFT					1
+ + #define OMAP4430_ISOCLK_STATUS_MASK					(1 << 1)
+ + 
+ + /* Used by PRM_IO_PMCTRL */
+ + #define OMAP4430_ISOOVR_EXTEND_SHIFT					4
+ + #define OMAP4430_ISOOVR_EXTEND_MASK					(1 << 4)
+ + 
+ + /* Used by PRM_IO_COUNT */
+ + #define OMAP4430_ISO_2_ON_TIME_SHIFT					0
+ + #define OMAP4430_ISO_2_ON_TIME_MASK					(0xff << 0)
+ + 
+ + /* Used by PM_L3INIT_PWRSTCTRL */
+ + #define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT				16
+ + #define OMAP4430_L3INIT_BANK1_ONSTATE_MASK				(0x3 << 16)
+ + 
+ + /* Used by PM_L3INIT_PWRSTCTRL */
+ + #define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT				8
+ + #define OMAP4430_L3INIT_BANK1_RETSTATE_MASK				(1 << 8)
+ + 
+ + /* Used by PM_L3INIT_PWRSTST */
+ + #define OMAP4430_L3INIT_BANK1_STATEST_SHIFT				4
+ + #define OMAP4430_L3INIT_BANK1_STATEST_MASK				(0x3 << 4)
+ + 
+ + /*
+ +  * Used by PM_ABE_PWRSTST, PM_CORE_PWRSTST, PM_IVAHD_PWRSTST,
+ +  * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
+ +  */
+ + #define OMAP4430_LASTPOWERSTATEENTERED_SHIFT				24
+ + #define OMAP4430_LASTPOWERSTATEENTERED_MASK				(0x3 << 24)
+ + 
+ + /*
+ +  * Used by PM_ABE_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL,
+ +  * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL,
+ +  * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL
+ +  */
+ + #define OMAP4430_LOGICRETSTATE_SHIFT					2
+ + #define OMAP4430_LOGICRETSTATE_MASK					(1 << 2)
+ + 
+ + /*
+ +  * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST,
+ +  * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST,
+ +  * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
+ +  */
+ + #define OMAP4430_LOGICSTATEST_SHIFT					2
+ + #define OMAP4430_LOGICSTATEST_MASK					(1 << 2)
+ + 
+ + /*
+ +  * Used by RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT,
+ +  * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT,
+ +  * RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT, RM_ABE_TIMER5_CONTEXT,
+ +  * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT,
+ +  * RM_ABE_WDT3_CONTEXT, RM_ALWON_MDMINTC_CONTEXT, RM_ALWON_SR_CORE_CONTEXT,
+ +  * RM_ALWON_SR_IVA_CONTEXT, RM_ALWON_SR_MPU_CONTEXT, RM_CAM_FDIF_CONTEXT,
+ +  * RM_CAM_ISS_CONTEXT, RM_CEFUSE_CEFUSE_CONTEXT, RM_D2D_SAD2D_CONTEXT,
+ +  * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT,
+ +  * RM_DUCATI_DUCATI_CONTEXT, RM_EMU_DEBUGSS_CONTEXT, RM_GFX_GFX_CONTEXT,
+ +  * RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT, RM_L3INIT_CCPTX_CONTEXT,
+ +  * RM_L3INIT_EMAC_CONTEXT, RM_L3INIT_P1500_CONTEXT, RM_L3INIT_PCIESS_CONTEXT,
+ +  * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT,
+ +  * RM_L3INIT_USBPHYOCP2SCP_CONTEXT, RM_L3INIT_XHPI_CONTEXT,
+ +  * RM_L3INSTR_L3_3_CONTEXT, RM_L3INSTR_L3_INSTR_CONTEXT,
+ +  * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_L3_2_CONTEXT,
+ +  * RM_L3_2_OCMC_RAM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT,
+ +  * RM_L4PER_ADC_CONTEXT, RM_L4PER_DMTIMER10_CONTEXT,
+ +  * RM_L4PER_DMTIMER11_CONTEXT, RM_L4PER_DMTIMER2_CONTEXT,
+ +  * RM_L4PER_DMTIMER3_CONTEXT, RM_L4PER_DMTIMER4_CONTEXT,
+ +  * RM_L4PER_DMTIMER9_CONTEXT, RM_L4PER_ELM_CONTEXT, RM_L4PER_HDQ1W_CONTEXT,
+ +  * RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, RM_L4PER_I2C2_CONTEXT,
+ +  * RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, RM_L4PER_I2C5_CONTEXT,
+ +  * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCASP2_CONTEXT, RM_L4PER_MCASP3_CONTEXT,
+ +  * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, RM_L4PER_MCSPI2_CONTEXT,
+ +  * RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, RM_L4PER_MGATE_CONTEXT,
+ +  * RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, RM_L4PER_MMCSD5_CONTEXT,
+ +  * RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT,
+ +  * RM_L4SEC_PKAEIP29_CONTEXT, RM_MEMIF_DLL_CONTEXT, RM_MEMIF_DLL_H_CONTEXT,
+ +  * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT,
+ +  * RM_MEMIF_EMIF_FW_CONTEXT, RM_MPU_MPU_CONTEXT, RM_TESLA_TESLA_CONTEXT,
+ +  * RM_WKUP_GPIO1_CONTEXT, RM_WKUP_KEYBOARD_CONTEXT, RM_WKUP_L4WKUP_CONTEXT,
+ +  * RM_WKUP_RTC_CONTEXT, RM_WKUP_SARRAM_CONTEXT, RM_WKUP_SYNCTIMER_CONTEXT,
+ +  * RM_WKUP_TIMER12_CONTEXT, RM_WKUP_TIMER1_CONTEXT, RM_WKUP_USIM_CONTEXT,
+ +  * RM_WKUP_WDT1_CONTEXT, RM_WKUP_WDT2_CONTEXT
+ +  */
+ + #define OMAP4430_LOSTCONTEXT_DFF_SHIFT					0
+ + #define OMAP4430_LOSTCONTEXT_DFF_MASK					(1 << 0)
+ + 
+ + /*
+ +  * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_D2D_SAD2D_CONTEXT,
+ +  * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DSS_CONTEXT, RM_DUCATI_DUCATI_CONTEXT,
+ +  * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT,
+ +  * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_USB_HOST_CONTEXT,
+ +  * RM_L3INIT_USB_HOST_FS_CONTEXT, RM_L3INIT_USB_OTG_CONTEXT,
+ +  * RM_L3INIT_USB_TLL_CONTEXT, RM_L3INSTR_L3_3_CONTEXT,
+ +  * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_GPMC_CONTEXT,
+ +  * RM_L3_2_L3_2_CONTEXT, RM_L4CFG_HW_SEM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT,
+ +  * RM_L4CFG_MAILBOX_CONTEXT, RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT,
+ +  * RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT,
+ +  * RM_L4PER_I2C1_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT,
+ +  * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT,
+ +  * RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT,
+ +  * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT,
+ +  * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT,
+ +  * RM_MEMIF_EMIF_FW_CONTEXT, RM_MEMIF_EMIF_H1_CONTEXT,
+ +  * RM_MEMIF_EMIF_H2_CONTEXT, RM_SDMA_SDMA_CONTEXT, RM_TESLA_TESLA_CONTEXT
+ +  */
+ + #define OMAP4430_LOSTCONTEXT_RFF_SHIFT					1
+ + #define OMAP4430_LOSTCONTEXT_RFF_MASK					(1 << 1)
+ + 
+ + /* Used by RM_ABE_AESS_CONTEXT */
+ + #define OMAP4430_LOSTMEM_AESSMEM_SHIFT					8
+ + #define OMAP4430_LOSTMEM_AESSMEM_MASK					(1 << 8)
+ + 
+ + /* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */
+ + #define OMAP4430_LOSTMEM_CAM_MEM_SHIFT					8
+ + #define OMAP4430_LOSTMEM_CAM_MEM_MASK					(1 << 8)
+ + 
+ + /* Used by RM_L3INSTR_OCP_WP1_CONTEXT */
+ + #define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT				8
+ + #define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK				(1 << 8)
+ + 
+ + /* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_MEMIF_DMM_CONTEXT */
+ + #define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT			9
+ + #define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK			(1 << 9)
+ + 
+ + /* Used by RM_L3_2_OCMC_RAM_CONTEXT */
+ + #define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT				8
+ + #define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK				(1 << 8)
+ + 
+ + /*
+ +  * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_MEMIF_DMM_CONTEXT,
+ +  * RM_SDMA_SDMA_CONTEXT
+ +  */
+ + #define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT				8
+ + #define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK				(1 << 8)
+ + 
+ + /* Used by RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT */
+ + #define OMAP4430_LOSTMEM_DSS_MEM_SHIFT					8
+ + #define OMAP4430_LOSTMEM_DSS_MEM_MASK					(1 << 8)
+ + 
+ + /* Used by RM_DUCATI_DUCATI_CONTEXT */
+ + #define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT				9
+ + #define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK				(1 << 9)
+ + 
+ + /* Used by RM_DUCATI_DUCATI_CONTEXT */
+ + #define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT				8
+ + #define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK				(1 << 8)
+ + 
+ + /* Used by RM_EMU_DEBUGSS_CONTEXT */
+ + #define OMAP4430_LOSTMEM_EMU_BANK_SHIFT					8
+ + #define OMAP4430_LOSTMEM_EMU_BANK_MASK					(1 << 8)
+ + 
+ + /* Used by RM_GFX_GFX_CONTEXT */
+ + #define OMAP4430_LOSTMEM_GFX_MEM_SHIFT					8
+ + #define OMAP4430_LOSTMEM_GFX_MEM_MASK					(1 << 8)
+ + 
+ + /* Used by RM_IVAHD_IVAHD_CONTEXT */
+ + #define OMAP4430_LOSTMEM_HWA_MEM_SHIFT					10
+ + #define OMAP4430_LOSTMEM_HWA_MEM_MASK					(1 << 10)
+ + 
+ + /*
+ +  * Used by RM_L3INIT_CCPTX_CONTEXT, RM_L3INIT_EMAC_CONTEXT,
+ +  * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT,
+ +  * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_PCIESS_CONTEXT, RM_L3INIT_SATA_CONTEXT,
+ +  * RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT,
+ +  * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_XHPI_CONTEXT
+ +  */
+ + #define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT				8
+ + #define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK				(1 << 8)
+ + 
+ + /* Used by RM_MPU_MPU_CONTEXT */
+ + #define OMAP4430_LOSTMEM_MPU_L1_SHIFT					8
+ + #define OMAP4430_LOSTMEM_MPU_L1_MASK					(1 << 8)
+ + 
+ + /* Used by RM_MPU_MPU_CONTEXT */
+ + #define OMAP4430_LOSTMEM_MPU_L2_SHIFT					9
+ + #define OMAP4430_LOSTMEM_MPU_L2_MASK					(1 << 9)
+ + 
+ + /* Used by RM_MPU_MPU_CONTEXT */
+ + #define OMAP4430_LOSTMEM_MPU_RAM_SHIFT					10
+ + #define OMAP4430_LOSTMEM_MPU_RAM_MASK					(1 << 10)
+ + 
+ + /*
+ +  * Used by RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT,
+ +  * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT,
+ +  * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT
+ +  */
+ + #define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT				8
+ + #define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK				(1 << 8)
+ + 
+ + /*
+ +  * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT,
+ +  * RM_ABE_MCBSP3_CONTEXT, RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT
+ +  */
+ + #define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT				8
+ + #define OMAP4430_LOSTMEM_PERIHPMEM_MASK					(1 << 8)
+ + 
+ + /*
+ +  * Used by RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_UART1_CONTEXT,
+ +  * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT,
+ +  * RM_L4SEC_CRYPTODMA_CONTEXT
+ +  */
+ + #define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT				8
+ + #define OMAP4430_LOSTMEM_RETAINED_BANK_MASK				(1 << 8)
+ + 
+ + /* Used by RM_IVAHD_SL2_CONTEXT */
+ + #define OMAP4430_LOSTMEM_SL2_MEM_SHIFT					8
+ + #define OMAP4430_LOSTMEM_SL2_MEM_MASK					(1 << 8)
+ + 
+ + /* Used by RM_IVAHD_IVAHD_CONTEXT */
+ + #define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT					8
+ + #define OMAP4430_LOSTMEM_TCM1_MEM_MASK					(1 << 8)
+ + 
+ + /* Used by RM_IVAHD_IVAHD_CONTEXT */
+ + #define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT					9
+ + #define OMAP4430_LOSTMEM_TCM2_MEM_MASK					(1 << 9)
+ + 
+ + /* Used by RM_TESLA_TESLA_CONTEXT */
+ + #define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT				10
+ + #define OMAP4430_LOSTMEM_TESLA_EDMA_MASK				(1 << 10)
+ + 
+ + /* Used by RM_TESLA_TESLA_CONTEXT */
+ + #define OMAP4430_LOSTMEM_TESLA_L1_SHIFT					8
+ + #define OMAP4430_LOSTMEM_TESLA_L1_MASK					(1 << 8)
+ + 
+ + /* Used by RM_TESLA_TESLA_CONTEXT */
+ + #define OMAP4430_LOSTMEM_TESLA_L2_SHIFT					9
+ + #define OMAP4430_LOSTMEM_TESLA_L2_MASK					(1 << 9)
+ + 
+ + /* Used by RM_WKUP_SARRAM_CONTEXT */
+ + #define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT				8
+ + #define OMAP4430_LOSTMEM_WKUP_BANK_MASK					(1 << 8)
+ + 
+ + /*
+ +  * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL,
+ +  * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_IVAHD_PWRSTCTRL,
+ +  * PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL
+ +  */
+ + #define OMAP4430_LOWPOWERSTATECHANGE_SHIFT				4
+ + #define OMAP4430_LOWPOWERSTATECHANGE_MASK				(1 << 4)
+ + 
+ + /* Used by PRM_MODEM_IF_CTRL */
+ + #define OMAP4430_MODEM_READY_SHIFT					1
+ + #define OMAP4430_MODEM_READY_MASK					(1 << 1)
+ + 
+ + /* Used by PRM_MODEM_IF_CTRL */
+ + #define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT				9
+ + #define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK				(1 << 9)
+ + 
+ + /* Used by PRM_MODEM_IF_CTRL */
+ + #define OMAP4430_MODEM_SLEEP_ST_SHIFT					16
+ + #define OMAP4430_MODEM_SLEEP_ST_MASK					(1 << 16)
+ + 
+ + /* Used by PRM_MODEM_IF_CTRL */
+ + #define OMAP4430_MODEM_WAKE_IRQ_SHIFT					8
+ + #define OMAP4430_MODEM_WAKE_IRQ_MASK					(1 << 8)
+ + 
+ + /* Used by PM_MPU_PWRSTCTRL */
+ + #define OMAP4430_MPU_L1_ONSTATE_SHIFT					16
+ + #define OMAP4430_MPU_L1_ONSTATE_MASK					(0x3 << 16)
+ + 
+ + /* Used by PM_MPU_PWRSTCTRL */
+ + #define OMAP4430_MPU_L1_RETSTATE_SHIFT					8
+ + #define OMAP4430_MPU_L1_RETSTATE_MASK					(1 << 8)
+ + 
+ + /* Used by PM_MPU_PWRSTST */
+ + #define OMAP4430_MPU_L1_STATEST_SHIFT					4
+ + #define OMAP4430_MPU_L1_STATEST_MASK					(0x3 << 4)
+ + 
+ + /* Used by PM_MPU_PWRSTCTRL */
+ + #define OMAP4430_MPU_L2_ONSTATE_SHIFT					18
+ + #define OMAP4430_MPU_L2_ONSTATE_MASK					(0x3 << 18)
+ + 
+ + /* Used by PM_MPU_PWRSTCTRL */
+ + #define OMAP4430_MPU_L2_RETSTATE_SHIFT					9
+ + #define OMAP4430_MPU_L2_RETSTATE_MASK					(1 << 9)
+ + 
+ + /* Used by PM_MPU_PWRSTST */
+ + #define OMAP4430_MPU_L2_STATEST_SHIFT					6
+ + #define OMAP4430_MPU_L2_STATEST_MASK					(0x3 << 6)
+ + 
+ + /* Used by PM_MPU_PWRSTCTRL */
+ + #define OMAP4430_MPU_RAM_ONSTATE_SHIFT					20
+ + #define OMAP4430_MPU_RAM_ONSTATE_MASK					(0x3 << 20)
+ + 
+ + /* Used by PM_MPU_PWRSTCTRL */
+ + #define OMAP4430_MPU_RAM_RETSTATE_SHIFT					10
+ + #define OMAP4430_MPU_RAM_RETSTATE_MASK					(1 << 10)
+ + 
+ + /* Used by PM_MPU_PWRSTST */
+ + #define OMAP4430_MPU_RAM_STATEST_SHIFT					8
+ + #define OMAP4430_MPU_RAM_STATEST_MASK					(0x3 << 8)
+ + 
+ + /* Used by PRM_RSTST */
+ + #define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT				2
+ + #define OMAP4430_MPU_SECURITY_VIOL_RST_MASK				(1 << 2)
+ + 
+ + /* Used by PRM_RSTST */
+ + #define OMAP4430_MPU_WDT_RST_SHIFT					3
+ + #define OMAP4430_MPU_WDT_RST_MASK					(1 << 3)
+ + 
+ + /* Used by PM_L4PER_PWRSTCTRL */
+ + #define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT				18
+ + #define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK				(0x3 << 18)
+ + 
+ + /* Used by PM_L4PER_PWRSTCTRL */
+ + #define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT			9
+ + #define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK				(1 << 9)
+ + 
+ + /* Used by PM_L4PER_PWRSTST */
+ + #define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT				6
+ + #define OMAP4430_NONRETAINED_BANK_STATEST_MASK				(0x3 << 6)
+ + 
+ + /* Used by PM_CORE_PWRSTCTRL */
+ + #define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT				24
+ + #define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK				(0x3 << 24)
+ + 
+ + /* Used by PM_CORE_PWRSTCTRL */
+ + #define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT				12
+ + #define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK				(1 << 12)
+ + 
+ + /* Used by PM_CORE_PWRSTST */
+ + #define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT				12
+ + #define OMAP4430_OCP_NRET_BANK_STATEST_MASK				(0x3 << 12)
+ + 
+ + /*
+ +  * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
+ +  * PRM_VC_VAL_CMD_VDD_MPU_L
+ +  */
+ + #define OMAP4430_OFF_SHIFT						0
+ + #define OMAP4430_OFF_MASK						(0xff << 0)
+ + 
+ + /*
+ +  * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
+ +  * PRM_VC_VAL_CMD_VDD_MPU_L
+ +  */
+ + #define OMAP4430_ON_SHIFT						24
+ + #define OMAP4430_ON_MASK						(0xff << 24)
+ + 
+ + /*
+ +  * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
+ +  * PRM_VC_VAL_CMD_VDD_MPU_L
+ +  */
+ + #define OMAP4430_ONLP_SHIFT						16
+ + #define OMAP4430_ONLP_MASK						(0xff << 16)
+ + 
+ + /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
+ + #define OMAP4430_OPP_CHANGE_SHIFT					2
+ + #define OMAP4430_OPP_CHANGE_MASK					(1 << 2)
+ + 
+ + /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
+ + #define OMAP4430_OPP_SEL_SHIFT						0
+ + #define OMAP4430_OPP_SEL_MASK						(0x3 << 0)
+ + 
+ + /* Used by PRM_SRAM_COUNT */
+ + #define OMAP4430_PCHARGECNT_VALUE_SHIFT					0
+ + #define OMAP4430_PCHARGECNT_VALUE_MASK					(0x3f << 0)
+ + 
+ + /* Used by PRM_PSCON_COUNT */
+ + #define OMAP4430_PCHARGE_TIME_SHIFT					0
+ + #define OMAP4430_PCHARGE_TIME_MASK					(0xff << 0)
+ + 
+ + /* Used by PM_ABE_PWRSTCTRL */
+ + #define OMAP4430_PERIPHMEM_ONSTATE_SHIFT				20
+ + #define OMAP4430_PERIPHMEM_ONSTATE_MASK					(0x3 << 20)
+ + 
+ + /* Used by PM_ABE_PWRSTCTRL */
+ + #define OMAP4430_PERIPHMEM_RETSTATE_SHIFT				10
+ + #define OMAP4430_PERIPHMEM_RETSTATE_MASK				(1 << 10)
+ + 
+ + /* Used by PM_ABE_PWRSTST */
+ + #define OMAP4430_PERIPHMEM_STATEST_SHIFT				8
+ + #define OMAP4430_PERIPHMEM_STATEST_MASK					(0x3 << 8)
+ + 
+ + /* Used by PRM_PHASE1_CNDP */
+ + #define OMAP4430_PHASE1_CNDP_SHIFT					0
+ + #define OMAP4430_PHASE1_CNDP_MASK					(0xffffffff << 0)
+ + 
+ + /* Used by PRM_PHASE2A_CNDP */
+ + #define OMAP4430_PHASE2A_CNDP_SHIFT					0
+ + #define OMAP4430_PHASE2A_CNDP_MASK					(0xffffffff << 0)
+ + 
+ + /* Used by PRM_PHASE2B_CNDP */
+ + #define OMAP4430_PHASE2B_CNDP_SHIFT					0
+ + #define OMAP4430_PHASE2B_CNDP_MASK					(0xffffffff << 0)
+ + 
+ + /* Used by PRM_PSCON_COUNT */
+ + #define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT				8
+ + #define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK				(0xff << 8)
+ + 
+ + /*
+ +  * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL,
+ +  * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_EMU_PWRSTCTRL, PM_GFX_PWRSTCTRL,
+ +  * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL,
+ +  * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL
+ +  */
+ + #define OMAP4430_POWERSTATE_SHIFT					0
+ + #define OMAP4430_POWERSTATE_MASK					(0x3 << 0)
+ + 
+ + /*
+ +  * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST,
+ +  * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST,
+ +  * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
+ +  */
+ + #define OMAP4430_POWERSTATEST_SHIFT					0
+ + #define OMAP4430_POWERSTATEST_MASK					(0x3 << 0)
+ + 
+ + /* Used by PRM_PWRREQCTRL */
+ + #define OMAP4430_PWRREQ_COND_SHIFT					0
+ + #define OMAP4430_PWRREQ_COND_MASK					(0x3 << 0)
+ + 
+ + /* Used by PRM_VC_CFG_CHANNEL */
+ + #define OMAP4430_RACEN_VDD_CORE_L_SHIFT					3
+ + #define OMAP4430_RACEN_VDD_CORE_L_MASK					(1 << 3)
+ + 
+ + /* Used by PRM_VC_CFG_CHANNEL */
+ + #define OMAP4430_RACEN_VDD_IVA_L_SHIFT					11
+ + #define OMAP4430_RACEN_VDD_IVA_L_MASK					(1 << 11)
+ + 
+ + /* Used by PRM_VC_CFG_CHANNEL */
+ + #define OMAP4430_RACEN_VDD_MPU_L_SHIFT					20
+ + #define OMAP4430_RACEN_VDD_MPU_L_MASK					(1 << 20)
+ + 
+ + /* Used by PRM_VC_CFG_CHANNEL */
+ + #define OMAP4430_RAC_VDD_CORE_L_SHIFT					2
+ + #define OMAP4430_RAC_VDD_CORE_L_MASK					(1 << 2)
+ + 
+ + /* Used by PRM_VC_CFG_CHANNEL */
+ + #define OMAP4430_RAC_VDD_IVA_L_SHIFT					10
+ + #define OMAP4430_RAC_VDD_IVA_L_MASK					(1 << 10)
+ + 
+ + /* Used by PRM_VC_CFG_CHANNEL */
+ + #define OMAP4430_RAC_VDD_MPU_L_SHIFT					19
+ + #define OMAP4430_RAC_VDD_MPU_L_MASK					(1 << 19)
+ + 
+ + /*
+ +  * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
+ +  * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
+ +  * PRM_VOLTSETUP_MPU_RET_SLEEP
+ +  */
+ + #define OMAP4430_RAMP_DOWN_COUNT_SHIFT					16
+ + #define OMAP4430_RAMP_DOWN_COUNT_MASK					(0x3f << 16)
+ + 
+ + /*
+ +  * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
+ +  * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
+ +  * PRM_VOLTSETUP_MPU_RET_SLEEP
+ +  */
+ + #define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT				24
+ + #define OMAP4430_RAMP_DOWN_PRESCAL_MASK					(0x3 << 24)
+ + 
+ + /*
+ +  * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
+ +  * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
+ +  * PRM_VOLTSETUP_MPU_RET_SLEEP
+ +  */
+ + #define OMAP4430_RAMP_UP_COUNT_SHIFT					0
+ + #define OMAP4430_RAMP_UP_COUNT_MASK					(0x3f << 0)
+ + 
+ + /*
+ +  * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
+ +  * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
+ +  * PRM_VOLTSETUP_MPU_RET_SLEEP
+ +  */
+ + #define OMAP4430_RAMP_UP_PRESCAL_SHIFT					8
+ + #define OMAP4430_RAMP_UP_PRESCAL_MASK					(0x3 << 8)
+ + 
+ + /* Used by PRM_VC_CFG_CHANNEL */
+ + #define OMAP4430_RAV_VDD_CORE_L_SHIFT					1
+ + #define OMAP4430_RAV_VDD_CORE_L_MASK					(1 << 1)
+ + 
+ + /* Used by PRM_VC_CFG_CHANNEL */
+ + #define OMAP4430_RAV_VDD_IVA_L_SHIFT					9
+ + #define OMAP4430_RAV_VDD_IVA_L_MASK					(1 << 9)
+ + 
+ + /* Used by PRM_VC_CFG_CHANNEL */
+ + #define OMAP4430_RAV_VDD_MPU_L_SHIFT					18
+ + #define OMAP4430_RAV_VDD_MPU_L_MASK					(1 << 18)
+ + 
+ + /* Used by PRM_VC_VAL_BYPASS */
+ + #define OMAP4430_REGADDR_SHIFT						8
+ + #define OMAP4430_REGADDR_MASK						(0xff << 8)
+ + 
+ + /*
+ +  * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
+ +  * PRM_VC_VAL_CMD_VDD_MPU_L
+ +  */
+ + #define OMAP4430_RET_SHIFT						8
+ + #define OMAP4430_RET_MASK						(0xff << 8)
+ + 
+ + /* Used by PM_L4PER_PWRSTCTRL */
+ + #define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT				16
+ + #define OMAP4430_RETAINED_BANK_ONSTATE_MASK				(0x3 << 16)
+ + 
+ + /* Used by PM_L4PER_PWRSTCTRL */
+ + #define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT				8
+ + #define OMAP4430_RETAINED_BANK_RETSTATE_MASK				(1 << 8)
+ + 
+ + /* Used by PM_L4PER_PWRSTST */
+ + #define OMAP4430_RETAINED_BANK_STATEST_SHIFT				4
+ + #define OMAP4430_RETAINED_BANK_STATEST_MASK				(0x3 << 4)
+ + 
+ + /*
+ +  * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
+ +  * PRM_LDO_SRAM_MPU_CTRL
+ +  */
+ + #define OMAP4430_RETMODE_ENABLE_SHIFT					0
+ + #define OMAP4430_RETMODE_ENABLE_MASK					(1 << 0)
+ + 
+ + /* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */
+ + #define OMAP4430_RST1_SHIFT						0
+ + #define OMAP4430_RST1_MASK						(1 << 0)
+ + 
+ + /* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */
+ + #define OMAP4430_RST1ST_SHIFT						0
+ + #define OMAP4430_RST1ST_MASK						(1 << 0)
+ + 
+ + /* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */
+ + #define OMAP4430_RST2_SHIFT						1
+ + #define OMAP4430_RST2_MASK						(1 << 1)
+ + 
+ + /* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */
+ + #define OMAP4430_RST2ST_SHIFT						1
+ + #define OMAP4430_RST2ST_MASK						(1 << 1)
+ + 
+ + /* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL */
+ + #define OMAP4430_RST3_SHIFT						2
+ + #define OMAP4430_RST3_MASK						(1 << 2)
+ + 
+ + /* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST */
+ + #define OMAP4430_RST3ST_SHIFT						2
+ + #define OMAP4430_RST3ST_MASK						(1 << 2)
+ + 
+ + /* Used by PRM_RSTTIME */
+ + #define OMAP4430_RSTTIME1_SHIFT						0
+ + #define OMAP4430_RSTTIME1_MASK						(0x3ff << 0)
+ + 
+ + /* Used by PRM_RSTTIME */
+ + #define OMAP4430_RSTTIME2_SHIFT						10
+ + #define OMAP4430_RSTTIME2_MASK						(0x1f << 10)
+ + 
+ + /* Used by PRM_RSTCTRL */
+ + #define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT				1
+ + #define OMAP4430_RST_GLOBAL_COLD_SW_MASK				(1 << 1)
+ + 
+ + /* Used by PRM_RSTCTRL */
+ + #define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT				0
+ + #define OMAP4430_RST_GLOBAL_WARM_SW_MASK				(1 << 0)
+ + 
+ + /* Used by REVISION_PRM */
+ + #define OMAP4430_R_RTL_SHIFT						11
+ + #define OMAP4430_R_RTL_MASK						(0x1f << 11)
+ + 
+ + /* Used by PRM_VC_CFG_CHANNEL */
+ + #define OMAP4430_SA_VDD_CORE_L_SHIFT					0
+ + #define OMAP4430_SA_VDD_CORE_L_MASK					(1 << 0)
+ + 
+ + /* Renamed from SA_VDD_CORE_L Used by PRM_VC_SMPS_SA */
+ + #define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT				0
+ + #define OMAP4430_SA_VDD_CORE_L_0_6_MASK					(0x7f << 0)
+ + 
+ + /* Used by PRM_VC_CFG_CHANNEL */
+ + #define OMAP4430_SA_VDD_IVA_L_SHIFT					8
+ + #define OMAP4430_SA_VDD_IVA_L_MASK					(1 << 8)
+ + 
+ + /* Renamed from SA_VDD_IVA_L Used by PRM_VC_SMPS_SA */
+ + #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT			8
+ + #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK			(0x7f << 8)
+ + 
+ + /* Used by PRM_VC_CFG_CHANNEL */
+ + #define OMAP4430_SA_VDD_MPU_L_SHIFT					16
+ + #define OMAP4430_SA_VDD_MPU_L_MASK					(1 << 16)
+ + 
+ + /* Renamed from SA_VDD_MPU_L Used by PRM_VC_SMPS_SA */
+ + #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT			16
+ + #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK			(0x7f << 16)
+ + 
+ + /* Used by REVISION_PRM */
+ + #define OMAP4430_SCHEME_SHIFT						30
+ + #define OMAP4430_SCHEME_MASK						(0x3 << 30)
+ + 
+ + /* Used by PRM_VC_CFG_I2C_CLK */
+ + #define OMAP4430_SCLH_SHIFT						0
+ + #define OMAP4430_SCLH_MASK						(0xff << 0)
+ + 
+ + /* Used by PRM_VC_CFG_I2C_CLK */
+ + #define OMAP4430_SCLL_SHIFT						8
+ + #define OMAP4430_SCLL_MASK						(0xff << 8)
+ + 
+ + /* Used by PRM_RSTST */
+ + #define OMAP4430_SECURE_WDT_RST_SHIFT					4
+ + #define OMAP4430_SECURE_WDT_RST_MASK					(1 << 4)
+ + 
+ + /* Used by PM_IVAHD_PWRSTCTRL */
+ + #define OMAP4430_SL2_MEM_ONSTATE_SHIFT					18
+ + #define OMAP4430_SL2_MEM_ONSTATE_MASK					(0x3 << 18)
+ + 
+ + /* Used by PM_IVAHD_PWRSTCTRL */
+ + #define OMAP4430_SL2_MEM_RETSTATE_SHIFT					9
+ + #define OMAP4430_SL2_MEM_RETSTATE_MASK					(1 << 9)
+ + 
+ + /* Used by PM_IVAHD_PWRSTST */
+ + #define OMAP4430_SL2_MEM_STATEST_SHIFT					6
+ + #define OMAP4430_SL2_MEM_STATEST_MASK					(0x3 << 6)
+ + 
+ + /* Used by PRM_VC_VAL_BYPASS */
+ + #define OMAP4430_SLAVEADDR_SHIFT					0
+ + #define OMAP4430_SLAVEADDR_MASK						(0x7f << 0)
+ + 
+ + /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
+ + #define OMAP4430_SLEEP_RBB_SEL_SHIFT					3
+ + #define OMAP4430_SLEEP_RBB_SEL_MASK					(1 << 3)
+ + 
+ + /* Used by PRM_SRAM_COUNT */
+ + #define OMAP4430_SLPCNT_VALUE_SHIFT					16
+ + #define OMAP4430_SLPCNT_VALUE_MASK					(0xff << 16)
+ + 
+ + /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
+ + #define OMAP4430_SMPSWAITTIMEMAX_SHIFT					8
+ + #define OMAP4430_SMPSWAITTIMEMAX_MASK					(0xffff << 8)
+ + 
+ + /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
+ + #define OMAP4430_SMPSWAITTIMEMIN_SHIFT					8
+ + #define OMAP4430_SMPSWAITTIMEMIN_MASK					(0xffff << 8)
+ + 
+ + /* Used by PRM_VC_ERRST */
+ + #define OMAP4430_SMPS_RA_ERR_CORE_SHIFT					1
+ + #define OMAP4430_SMPS_RA_ERR_CORE_MASK					(1 << 1)
+ + 
+ + /* Used by PRM_VC_ERRST */
+ + #define OMAP4430_SMPS_RA_ERR_IVA_SHIFT					9
+ + #define OMAP4430_SMPS_RA_ERR_IVA_MASK					(1 << 9)
+ + 
+ + /* Used by PRM_VC_ERRST */
+ + #define OMAP4430_SMPS_RA_ERR_MPU_SHIFT					17
+ + #define OMAP4430_SMPS_RA_ERR_MPU_MASK					(1 << 17)
+ + 
+ + /* Used by PRM_VC_ERRST */
+ + #define OMAP4430_SMPS_SA_ERR_CORE_SHIFT					0
+ + #define OMAP4430_SMPS_SA_ERR_CORE_MASK					(1 << 0)
+ + 
+ + /* Used by PRM_VC_ERRST */
+ + #define OMAP4430_SMPS_SA_ERR_IVA_SHIFT					8
+ + #define OMAP4430_SMPS_SA_ERR_IVA_MASK					(1 << 8)
+ + 
+ + /* Used by PRM_VC_ERRST */
+ + #define OMAP4430_SMPS_SA_ERR_MPU_SHIFT					16
+ + #define OMAP4430_SMPS_SA_ERR_MPU_MASK					(1 << 16)
+ + 
+ + /* Used by PRM_VC_ERRST */
+ + #define OMAP4430_SMPS_TIMEOUT_ERR_CORE_SHIFT				2
+ + #define OMAP4430_SMPS_TIMEOUT_ERR_CORE_MASK				(1 << 2)
+ + 
+ + /* Used by PRM_VC_ERRST */
+ + #define OMAP4430_SMPS_TIMEOUT_ERR_IVA_SHIFT				10
+ + #define OMAP4430_SMPS_TIMEOUT_ERR_IVA_MASK				(1 << 10)
+ + 
+ + /* Used by PRM_VC_ERRST */
+ + #define OMAP4430_SMPS_TIMEOUT_ERR_MPU_SHIFT				18
+ + #define OMAP4430_SMPS_TIMEOUT_ERR_MPU_MASK				(1 << 18)
+ + 
+ + /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
+ + #define OMAP4430_SR2EN_SHIFT						0
+ + #define OMAP4430_SR2EN_MASK						(1 << 0)
+ + 
+ + /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
+ + #define OMAP4430_SR2_IN_TRANSITION_SHIFT				6
+ + #define OMAP4430_SR2_IN_TRANSITION_MASK					(1 << 6)
+ + 
+ + /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
+ + #define OMAP4430_SR2_STATUS_SHIFT					3
+ + #define OMAP4430_SR2_STATUS_MASK					(0x3 << 3)
+ + 
+ + /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
+ + #define OMAP4430_SR2_WTCNT_VALUE_SHIFT					8
+ + #define OMAP4430_SR2_WTCNT_VALUE_MASK					(0xff << 8)
+ + 
+ + /*
+ +  * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
+ +  * PRM_LDO_SRAM_MPU_CTRL
+ +  */
+ + #define OMAP4430_SRAMLDO_STATUS_SHIFT					8
+ + #define OMAP4430_SRAMLDO_STATUS_MASK					(1 << 8)
+ + 
+ + /*
+ +  * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
+ +  * PRM_LDO_SRAM_MPU_CTRL
+ +  */
+ + #define OMAP4430_SRAM_IN_TRANSITION_SHIFT				9
+ + #define OMAP4430_SRAM_IN_TRANSITION_MASK				(1 << 9)
+ + 
+ + /* Used by PRM_VC_CFG_I2C_MODE */
+ + #define OMAP4430_SRMODEEN_SHIFT						4
+ + #define OMAP4430_SRMODEEN_MASK						(1 << 4)
+ + 
+ + /* Used by PRM_VOLTSETUP_WARMRESET */
+ + #define OMAP4430_STABLE_COUNT_SHIFT					0
+ + #define OMAP4430_STABLE_COUNT_MASK					(0x3f << 0)
+ + 
+ + /* Used by PRM_VOLTSETUP_WARMRESET */
+ + #define OMAP4430_STABLE_PRESCAL_SHIFT					8
+ + #define OMAP4430_STABLE_PRESCAL_MASK					(0x3 << 8)
+ + 
+ + /* Used by PRM_LDO_BANDGAP_SETUP */
+ + #define OMAP4430_STARTUP_COUNT_SHIFT					0
+ + #define OMAP4430_STARTUP_COUNT_MASK					(0xff << 0)
+ + 
+ + /* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */
+ + #define OMAP4430_STARTUP_COUNT_24_31_SHIFT				24
+ + #define OMAP4430_STARTUP_COUNT_24_31_MASK				(0xff << 24)
+ + 
+ + /* Used by PM_IVAHD_PWRSTCTRL */
+ + #define OMAP4430_TCM1_MEM_ONSTATE_SHIFT					20
+ + #define OMAP4430_TCM1_MEM_ONSTATE_MASK					(0x3 << 20)
+ + 
+ + /* Used by PM_IVAHD_PWRSTCTRL */
+ + #define OMAP4430_TCM1_MEM_RETSTATE_SHIFT				10
+ + #define OMAP4430_TCM1_MEM_RETSTATE_MASK					(1 << 10)
+ + 
+ + /* Used by PM_IVAHD_PWRSTST */
+ + #define OMAP4430_TCM1_MEM_STATEST_SHIFT					8
+ + #define OMAP4430_TCM1_MEM_STATEST_MASK					(0x3 << 8)
+ + 
+ + /* Used by PM_IVAHD_PWRSTCTRL */
+ + #define OMAP4430_TCM2_MEM_ONSTATE_SHIFT					22
+ + #define OMAP4430_TCM2_MEM_ONSTATE_MASK					(0x3 << 22)
+ + 
+ + /* Used by PM_IVAHD_PWRSTCTRL */
+ + #define OMAP4430_TCM2_MEM_RETSTATE_SHIFT				11
+ + #define OMAP4430_TCM2_MEM_RETSTATE_MASK					(1 << 11)
+ + 
+ + /* Used by PM_IVAHD_PWRSTST */
+ + #define OMAP4430_TCM2_MEM_STATEST_SHIFT					10
+ + #define OMAP4430_TCM2_MEM_STATEST_MASK					(0x3 << 10)
+ + 
+ + /* Used by RM_TESLA_RSTST */
+ + #define OMAP4430_TESLASS_EMU_RSTST_SHIFT				2
+ + #define OMAP4430_TESLASS_EMU_RSTST_MASK					(1 << 2)
+ + 
+ + /* Used by RM_TESLA_RSTST */
+ + #define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT				3
+ + #define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK				(1 << 3)
+ + 
+ + /* Used by PM_TESLA_PWRSTCTRL */
+ + #define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT				20
+ + #define OMAP4430_TESLA_EDMA_ONSTATE_MASK				(0x3 << 20)
+ + 
+ + /* Used by PM_TESLA_PWRSTCTRL */
+ + #define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT				10
+ + #define OMAP4430_TESLA_EDMA_RETSTATE_MASK				(1 << 10)
+ + 
+ + /* Used by PM_TESLA_PWRSTST */
+ + #define OMAP4430_TESLA_EDMA_STATEST_SHIFT				8
+ + #define OMAP4430_TESLA_EDMA_STATEST_MASK				(0x3 << 8)
+ + 
+ + /* Used by PM_TESLA_PWRSTCTRL */
+ + #define OMAP4430_TESLA_L1_ONSTATE_SHIFT					16
+ + #define OMAP4430_TESLA_L1_ONSTATE_MASK					(0x3 << 16)
+ + 
+ + /* Used by PM_TESLA_PWRSTCTRL */
+ + #define OMAP4430_TESLA_L1_RETSTATE_SHIFT				8
+ + #define OMAP4430_TESLA_L1_RETSTATE_MASK					(1 << 8)
+ + 
+ + /* Used by PM_TESLA_PWRSTST */
+ + #define OMAP4430_TESLA_L1_STATEST_SHIFT					4
+ + #define OMAP4430_TESLA_L1_STATEST_MASK					(0x3 << 4)
+ + 
+ + /* Used by PM_TESLA_PWRSTCTRL */
+ + #define OMAP4430_TESLA_L2_ONSTATE_SHIFT					18
+ + #define OMAP4430_TESLA_L2_ONSTATE_MASK					(0x3 << 18)
+ + 
+ + /* Used by PM_TESLA_PWRSTCTRL */
+ + #define OMAP4430_TESLA_L2_RETSTATE_SHIFT				9
+ + #define OMAP4430_TESLA_L2_RETSTATE_MASK					(1 << 9)
+ + 
+ + /* Used by PM_TESLA_PWRSTST */
+ + #define OMAP4430_TESLA_L2_STATEST_SHIFT					6
+ + #define OMAP4430_TESLA_L2_STATEST_MASK					(0x3 << 6)
+ + 
+ + /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
+ + #define OMAP4430_TIMEOUT_SHIFT						0
+ + #define OMAP4430_TIMEOUT_MASK						(0xffff << 0)
+ + 
+ + /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
+ + #define OMAP4430_TIMEOUTEN_SHIFT					3
+ + #define OMAP4430_TIMEOUTEN_MASK						(1 << 3)
+ + 
+ + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+ + #define OMAP4430_TRANSITION_EN_SHIFT					8
+ + #define OMAP4430_TRANSITION_EN_MASK					(1 << 8)
+ + 
+ + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+ + #define OMAP4430_TRANSITION_ST_SHIFT					8
+ + #define OMAP4430_TRANSITION_ST_MASK					(1 << 8)
+ + 
+ + /* Used by PRM_VC_VAL_BYPASS */
+ + #define OMAP4430_VALID_SHIFT						24
+ + #define OMAP4430_VALID_MASK						(1 << 24)
+ + 
+ + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+ + #define OMAP4430_VC_BYPASSACK_EN_SHIFT					14
+ + #define OMAP4430_VC_BYPASSACK_EN_MASK					(1 << 14)
+ + 
+ + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+ + #define OMAP4430_VC_BYPASSACK_ST_SHIFT					14
+ + #define OMAP4430_VC_BYPASSACK_ST_MASK					(1 << 14)
+ + 
+ + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+ + #define OMAP4430_VC_CORE_VPACK_EN_SHIFT					22
+ + #define OMAP4430_VC_CORE_VPACK_EN_MASK					(1 << 22)
+ + 
+ + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+ + #define OMAP4430_VC_CORE_VPACK_ST_SHIFT					22
+ + #define OMAP4430_VC_CORE_VPACK_ST_MASK					(1 << 22)
+ + 
+ + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+ + #define OMAP4430_VC_IVA_VPACK_EN_SHIFT					30
+ + #define OMAP4430_VC_IVA_VPACK_EN_MASK					(1 << 30)
+ + 
+ + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+ + #define OMAP4430_VC_IVA_VPACK_ST_SHIFT					30
+ + #define OMAP4430_VC_IVA_VPACK_ST_MASK					(1 << 30)
+ + 
+ + /* Used by PRM_IRQENABLE_MPU_2 */
+ + #define OMAP4430_VC_MPU_VPACK_EN_SHIFT					6
+ + #define OMAP4430_VC_MPU_VPACK_EN_MASK					(1 << 6)
+ + 
+ + /* Used by PRM_IRQSTATUS_MPU_2 */
+ + #define OMAP4430_VC_MPU_VPACK_ST_SHIFT					6
+ + #define OMAP4430_VC_MPU_VPACK_ST_MASK					(1 << 6)
+ + 
+ + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+ + #define OMAP4430_VC_RAERR_EN_SHIFT					12
+ + #define OMAP4430_VC_RAERR_EN_MASK					(1 << 12)
+ + 
+ + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+ + #define OMAP4430_VC_RAERR_ST_SHIFT					12
+ + #define OMAP4430_VC_RAERR_ST_MASK					(1 << 12)
+ + 
+ + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+ + #define OMAP4430_VC_SAERR_EN_SHIFT					11
+ + #define OMAP4430_VC_SAERR_EN_MASK					(1 << 11)
+ + 
+ + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+ + #define OMAP4430_VC_SAERR_ST_SHIFT					11
+ + #define OMAP4430_VC_SAERR_ST_MASK					(1 << 11)
+ + 
+ + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+ + #define OMAP4430_VC_TOERR_EN_SHIFT					13
+ + #define OMAP4430_VC_TOERR_EN_MASK					(1 << 13)
+ + 
+ + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+ + #define OMAP4430_VC_TOERR_ST_SHIFT					13
+ + #define OMAP4430_VC_TOERR_ST_MASK					(1 << 13)
+ + 
+ + /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
+ + #define OMAP4430_VDDMAX_SHIFT						24
+ + #define OMAP4430_VDDMAX_MASK						(0xff << 24)
+ + 
+ + /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
+ + #define OMAP4430_VDDMIN_SHIFT						16
+ + #define OMAP4430_VDDMIN_MASK						(0xff << 16)
+ + 
+ + /* Used by PRM_VOLTCTRL */
+ + #define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT				12
+ + #define OMAP4430_VDD_CORE_I2C_DISABLE_MASK				(1 << 12)
+ + 
+ + /* Used by PRM_RSTST */
+ + #define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT				8
+ + #define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK				(1 << 8)
+ + 
+ + /* Used by PRM_VOLTCTRL */
+ + #define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT				14
+ + #define OMAP4430_VDD_IVA_I2C_DISABLE_MASK				(1 << 14)
+ + 
+ + /* Used by PRM_VOLTCTRL */
+ + #define OMAP4430_VDD_IVA_PRESENCE_SHIFT					9
+ + #define OMAP4430_VDD_IVA_PRESENCE_MASK					(1 << 9)
+ + 
+ + /* Used by PRM_RSTST */
+ + #define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT				7
+ + #define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK				(1 << 7)
+ + 
+ + /* Used by PRM_VOLTCTRL */
+ + #define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT				13
+ + #define OMAP4430_VDD_MPU_I2C_DISABLE_MASK				(1 << 13)
+ + 
+ + /* Used by PRM_VOLTCTRL */
+ + #define OMAP4430_VDD_MPU_PRESENCE_SHIFT					8
+ + #define OMAP4430_VDD_MPU_PRESENCE_MASK					(1 << 8)
+ + 
+ + /* Used by PRM_RSTST */
+ + #define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT				6
+ + #define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK				(1 << 6)
+ + 
+ + /* Used by PRM_VC_ERRST */
+ + #define OMAP4430_VFSM_RA_ERR_CORE_SHIFT					4
+ + #define OMAP4430_VFSM_RA_ERR_CORE_MASK					(1 << 4)
+ + 
+ + /* Used by PRM_VC_ERRST */
+ + #define OMAP4430_VFSM_RA_ERR_IVA_SHIFT					12
+ + #define OMAP4430_VFSM_RA_ERR_IVA_MASK					(1 << 12)
+ + 
+ + /* Used by PRM_VC_ERRST */
+ + #define OMAP4430_VFSM_RA_ERR_MPU_SHIFT					20
+ + #define OMAP4430_VFSM_RA_ERR_MPU_MASK					(1 << 20)
+ + 
+ + /* Used by PRM_VC_ERRST */
+ + #define OMAP4430_VFSM_SA_ERR_CORE_SHIFT					3
+ + #define OMAP4430_VFSM_SA_ERR_CORE_MASK					(1 << 3)
+ + 
+ + /* Used by PRM_VC_ERRST */
+ + #define OMAP4430_VFSM_SA_ERR_IVA_SHIFT					11
+ + #define OMAP4430_VFSM_SA_ERR_IVA_MASK					(1 << 11)
+ + 
+ + /* Used by PRM_VC_ERRST */
+ + #define OMAP4430_VFSM_SA_ERR_MPU_SHIFT					19
+ + #define OMAP4430_VFSM_SA_ERR_MPU_MASK					(1 << 19)
+ + 
+ + /* Used by PRM_VC_ERRST */
+ + #define OMAP4430_VFSM_TIMEOUT_ERR_CORE_SHIFT				5
+ + #define OMAP4430_VFSM_TIMEOUT_ERR_CORE_MASK				(1 << 5)
+ + 
+ + /* Used by PRM_VC_ERRST */
+ + #define OMAP4430_VFSM_TIMEOUT_ERR_IVA_SHIFT				13
+ + #define OMAP4430_VFSM_TIMEOUT_ERR_IVA_MASK				(1 << 13)
+ + 
+ + /* Used by PRM_VC_ERRST */
+ + #define OMAP4430_VFSM_TIMEOUT_ERR_MPU_SHIFT				21
+ + #define OMAP4430_VFSM_TIMEOUT_ERR_MPU_MASK				(1 << 21)
+ + 
+ + /* Used by PRM_VC_VAL_SMPS_RA_VOL */
+ + #define OMAP4430_VOLRA_VDD_CORE_L_SHIFT					0
+ + #define OMAP4430_VOLRA_VDD_CORE_L_MASK					(0xff << 0)
+ + 
+ + /* Used by PRM_VC_VAL_SMPS_RA_VOL */
+ + #define OMAP4430_VOLRA_VDD_IVA_L_SHIFT					8
+ + #define OMAP4430_VOLRA_VDD_IVA_L_MASK					(0xff << 8)
+ + 
+ + /* Used by PRM_VC_VAL_SMPS_RA_VOL */
+ + #define OMAP4430_VOLRA_VDD_MPU_L_SHIFT					16
+ + #define OMAP4430_VOLRA_VDD_MPU_L_MASK					(0xff << 16)
+ + 
+ + /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
+ + #define OMAP4430_VPENABLE_SHIFT						0
+ + #define OMAP4430_VPENABLE_MASK						(1 << 0)
+ + 
+ + /* Used by PRM_VP_CORE_STATUS, PRM_VP_IVA_STATUS, PRM_VP_MPU_STATUS */
+ + #define OMAP4430_VPINIDLE_SHIFT						0
+ + #define OMAP4430_VPINIDLE_MASK						(1 << 0)
+ + 
+ + /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */
+ + #define OMAP4430_VPVOLTAGE_SHIFT					0
+ + #define OMAP4430_VPVOLTAGE_MASK						(0xff << 0)
+ + 
+ + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+ + #define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT				20
+ + #define OMAP4430_VP_CORE_EQVALUE_EN_MASK				(1 << 20)
+ + 
+ + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+ + #define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT				20
+ + #define OMAP4430_VP_CORE_EQVALUE_ST_MASK				(1 << 20)
+ + 
+ + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+ + #define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT				18
+ + #define OMAP4430_VP_CORE_MAXVDD_EN_MASK					(1 << 18)
+ + 
+ + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+ + #define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT				18
+ + #define OMAP4430_VP_CORE_MAXVDD_ST_MASK					(1 << 18)
+ + 
+ + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+ + #define OMAP4430_VP_CORE_MINVDD_EN_SHIFT				17
+ + #define OMAP4430_VP_CORE_MINVDD_EN_MASK					(1 << 17)
+ + 
+ + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+ + #define OMAP4430_VP_CORE_MINVDD_ST_SHIFT				17
+ + #define OMAP4430_VP_CORE_MINVDD_ST_MASK					(1 << 17)
+ + 
+ + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+ + #define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT				19
+ + #define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK				(1 << 19)
+ + 
+ + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+ + #define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT				19
+ + #define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK				(1 << 19)
+ + 
+ + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+ + #define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT				16
+ + #define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK				(1 << 16)
+ + 
+ + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+ + #define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT				16
+ + #define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK				(1 << 16)
+ + 
+ + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+ + #define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT				21
+ + #define OMAP4430_VP_CORE_TRANXDONE_EN_MASK				(1 << 21)
+ + 
+ + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+ + #define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT				21
+ + #define OMAP4430_VP_CORE_TRANXDONE_ST_MASK				(1 << 21)
+ + 
+ + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+ + #define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT				28
+ + #define OMAP4430_VP_IVA_EQVALUE_EN_MASK					(1 << 28)
+ + 
+ + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+ + #define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT				28
+ + #define OMAP4430_VP_IVA_EQVALUE_ST_MASK					(1 << 28)
+ + 
+ + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+ + #define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT					26
+ + #define OMAP4430_VP_IVA_MAXVDD_EN_MASK					(1 << 26)
+ + 
+ + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+ + #define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT					26
+ + #define OMAP4430_VP_IVA_MAXVDD_ST_MASK					(1 << 26)
+ + 
+ + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+ + #define OMAP4430_VP_IVA_MINVDD_EN_SHIFT					25
+ + #define OMAP4430_VP_IVA_MINVDD_EN_MASK					(1 << 25)
+ + 
+ + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+ + #define OMAP4430_VP_IVA_MINVDD_ST_SHIFT					25
+ + #define OMAP4430_VP_IVA_MINVDD_ST_MASK					(1 << 25)
+ + 
+ + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+ + #define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT				27
+ + #define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK				(1 << 27)
+ + 
+ + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+ + #define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT				27
+ + #define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK				(1 << 27)
+ + 
+ + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+ + #define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT				24
+ + #define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK				(1 << 24)
+ + 
+ + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+ + #define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT				24
+ + #define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK				(1 << 24)
+ + 
+ + /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+ + #define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT				29
+ + #define OMAP4430_VP_IVA_TRANXDONE_EN_MASK				(1 << 29)
+ + 
+ + /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+ + #define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT				29
+ + #define OMAP4430_VP_IVA_TRANXDONE_ST_MASK				(1 << 29)
+ + 
+ + /* Used by PRM_IRQENABLE_MPU_2 */
+ + #define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT				4
+ + #define OMAP4430_VP_MPU_EQVALUE_EN_MASK					(1 << 4)
+ + 
+ + /* Used by PRM_IRQSTATUS_MPU_2 */
+ + #define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT				4
+ + #define OMAP4430_VP_MPU_EQVALUE_ST_MASK					(1 << 4)
+ + 
+ + /* Used by PRM_IRQENABLE_MPU_2 */
+ + #define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT					2
+ + #define OMAP4430_VP_MPU_MAXVDD_EN_MASK					(1 << 2)
+ + 
+ + /* Used by PRM_IRQSTATUS_MPU_2 */
+ + #define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT					2
+ + #define OMAP4430_VP_MPU_MAXVDD_ST_MASK					(1 << 2)
+ + 
+ + /* Used by PRM_IRQENABLE_MPU_2 */
+ + #define OMAP4430_VP_MPU_MINVDD_EN_SHIFT					1
+ + #define OMAP4430_VP_MPU_MINVDD_EN_MASK					(1 << 1)
+ + 
+ + /* Used by PRM_IRQSTATUS_MPU_2 */
+ + #define OMAP4430_VP_MPU_MINVDD_ST_SHIFT					1
+ + #define OMAP4430_VP_MPU_MINVDD_ST_MASK					(1 << 1)
+ + 
+ + /* Used by PRM_IRQENABLE_MPU_2 */
+ + #define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT				3
+ + #define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK				(1 << 3)
+ + 
+ + /* Used by PRM_IRQSTATUS_MPU_2 */
+ + #define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT				3
+ + #define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK				(1 << 3)
+ + 
+ + /* Used by PRM_IRQENABLE_MPU_2 */
+ + #define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT				0
+ + #define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK				(1 << 0)
+ + 
+ + /* Used by PRM_IRQSTATUS_MPU_2 */
+ + #define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT				0
+ + #define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK				(1 << 0)
+ + 
+ + /* Used by PRM_IRQENABLE_MPU_2 */
+ + #define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT				5
+ + #define OMAP4430_VP_MPU_TRANXDONE_EN_MASK				(1 << 5)
+ + 
+ + /* Used by PRM_IRQSTATUS_MPU_2 */
+ + #define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT				5
+ + #define OMAP4430_VP_MPU_TRANXDONE_ST_MASK				(1 << 5)
+ + 
+ + /* Used by PRM_SRAM_COUNT */
+ + #define OMAP4430_VSETUPCNT_VALUE_SHIFT					8
+ + #define OMAP4430_VSETUPCNT_VALUE_MASK					(0xff << 8)
+ + 
+ + /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
+ + #define OMAP4430_VSTEPMAX_SHIFT						0
+ + #define OMAP4430_VSTEPMAX_MASK						(0xff << 0)
+ + 
+ + /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
+ + #define OMAP4430_VSTEPMIN_SHIFT						0
+ + #define OMAP4430_VSTEPMIN_MASK						(0xff << 0)
+ + 
+ + /* Used by PRM_MODEM_IF_CTRL */
+ + #define OMAP4430_WAKE_MODEM_SHIFT					0
+ + #define OMAP4430_WAKE_MODEM_MASK					(1 << 0)
+ + 
+ + /* Used by PM_DSS_DSS_WKDEP */
+ + #define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT				1
+ + #define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK				(1 << 1)
+ + 
+ + /* Used by PM_DSS_DSS_WKDEP */
+ + #define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_DISPC_MPU_MASK					(1 << 0)
+ + 
+ + /* Used by PM_DSS_DSS_WKDEP */
+ + #define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT				3
+ + #define OMAP4430_WKUPDEP_DISPC_SDMA_MASK				(1 << 3)
+ + 
+ + /* Used by PM_DSS_DSS_WKDEP */
+ + #define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT				2
+ + #define OMAP4430_WKUPDEP_DISPC_TESLA_MASK				(1 << 2)
+ + 
+ + /* Used by PM_ABE_DMIC_WKDEP */
+ + #define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT				7
+ + #define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK				(1 << 7)
+ + 
+ + /* Used by PM_ABE_DMIC_WKDEP */
+ + #define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT				6
+ + #define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK				(1 << 6)
+ + 
+ + /* Used by PM_ABE_DMIC_WKDEP */
+ + #define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_ABE_DMIC_WKDEP */
+ + #define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT				2
+ + #define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK				(1 << 2)
+ + 
+ + /* Used by PM_L4PER_DMTIMER10_WKDEP */
+ + #define OMAP4430_WKUPDEP_DMTIMER10_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_L4PER_DMTIMER11_WKDEP */
+ + #define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_SHIFT				1
+ + #define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK				(1 << 1)
+ + 
+ + /* Used by PM_L4PER_DMTIMER11_WKDEP */
+ + #define OMAP4430_WKUPDEP_DMTIMER11_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_L4PER_DMTIMER2_WKDEP */
+ + #define OMAP4430_WKUPDEP_DMTIMER2_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_L4PER_DMTIMER3_WKDEP */
+ + #define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_SHIFT				1
+ + #define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK				(1 << 1)
+ + 
+ + /* Used by PM_L4PER_DMTIMER3_WKDEP */
+ + #define OMAP4430_WKUPDEP_DMTIMER3_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_L4PER_DMTIMER4_WKDEP */
+ + #define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_SHIFT				1
+ + #define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK				(1 << 1)
+ + 
+ + /* Used by PM_L4PER_DMTIMER4_WKDEP */
+ + #define OMAP4430_WKUPDEP_DMTIMER4_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_L4PER_DMTIMER9_WKDEP */
+ + #define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_SHIFT				1
+ + #define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK				(1 << 1)
+ + 
+ + /* Used by PM_L4PER_DMTIMER9_WKDEP */
+ + #define OMAP4430_WKUPDEP_DMTIMER9_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_DSS_DSS_WKDEP */
+ + #define OMAP4430_WKUPDEP_DSI1_DUCATI_SHIFT				5
+ + #define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK				(1 << 5)
+ + 
+ + /* Used by PM_DSS_DSS_WKDEP */
+ + #define OMAP4430_WKUPDEP_DSI1_MPU_SHIFT					4
+ + #define OMAP4430_WKUPDEP_DSI1_MPU_MASK					(1 << 4)
+ + 
+ + /* Used by PM_DSS_DSS_WKDEP */
+ + #define OMAP4430_WKUPDEP_DSI1_SDMA_SHIFT				7
+ + #define OMAP4430_WKUPDEP_DSI1_SDMA_MASK					(1 << 7)
+ + 
+ + /* Used by PM_DSS_DSS_WKDEP */
+ + #define OMAP4430_WKUPDEP_DSI1_TESLA_SHIFT				6
+ + #define OMAP4430_WKUPDEP_DSI1_TESLA_MASK				(1 << 6)
+ + 
+ + /* Used by PM_DSS_DSS_WKDEP */
+ + #define OMAP4430_WKUPDEP_DSI2_DUCATI_SHIFT				9
+ + #define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK				(1 << 9)
+ + 
+ + /* Used by PM_DSS_DSS_WKDEP */
+ + #define OMAP4430_WKUPDEP_DSI2_MPU_SHIFT					8
+ + #define OMAP4430_WKUPDEP_DSI2_MPU_MASK					(1 << 8)
+ + 
+ + /* Used by PM_DSS_DSS_WKDEP */
+ + #define OMAP4430_WKUPDEP_DSI2_SDMA_SHIFT				11
+ + #define OMAP4430_WKUPDEP_DSI2_SDMA_MASK					(1 << 11)
+ + 
+ + /* Used by PM_DSS_DSS_WKDEP */
+ + #define OMAP4430_WKUPDEP_DSI2_TESLA_SHIFT				10
+ + #define OMAP4430_WKUPDEP_DSI2_TESLA_MASK				(1 << 10)
+ + 
+ + /* Used by PM_WKUP_GPIO1_WKDEP */
+ + #define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_SHIFT			1
+ + #define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK				(1 << 1)
+ + 
+ + /* Used by PM_WKUP_GPIO1_WKDEP */
+ + #define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_WKUP_GPIO1_WKDEP */
+ + #define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_SHIFT				6
+ + #define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK				(1 << 6)
+ + 
+ + /* Used by PM_L4PER_GPIO2_WKDEP */
+ + #define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_SHIFT			1
+ + #define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK				(1 << 1)
+ + 
+ + /* Used by PM_L4PER_GPIO2_WKDEP */
+ + #define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_L4PER_GPIO2_WKDEP */
+ + #define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_SHIFT				6
+ + #define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK				(1 << 6)
+ + 
+ + /* Used by PM_L4PER_GPIO3_WKDEP */
+ + #define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_L4PER_GPIO3_WKDEP */
+ + #define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_SHIFT				6
+ + #define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK				(1 << 6)
+ + 
+ + /* Used by PM_L4PER_GPIO4_WKDEP */
+ + #define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_L4PER_GPIO4_WKDEP */
+ + #define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_SHIFT				6
+ + #define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK				(1 << 6)
+ + 
+ + /* Used by PM_L4PER_GPIO5_WKDEP */
+ + #define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_L4PER_GPIO5_WKDEP */
+ + #define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_SHIFT				6
+ + #define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK				(1 << 6)
+ + 
+ + /* Used by PM_L4PER_GPIO6_WKDEP */
+ + #define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_L4PER_GPIO6_WKDEP */
+ + #define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_SHIFT				6
+ + #define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK				(1 << 6)
+ + 
+ + /* Used by PM_DSS_DSS_WKDEP */
+ + #define OMAP4430_WKUPDEP_HDMIDMA_SDMA_SHIFT				19
+ + #define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK				(1 << 19)
+ + 
+ + /* Used by PM_DSS_DSS_WKDEP */
+ + #define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_SHIFT				13
+ + #define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK				(1 << 13)
+ + 
+ + /* Used by PM_DSS_DSS_WKDEP */
+ + #define OMAP4430_WKUPDEP_HDMIIRQ_MPU_SHIFT				12
+ + #define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK				(1 << 12)
+ + 
+ + /* Used by PM_DSS_DSS_WKDEP */
+ + #define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_SHIFT				14
+ + #define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK				(1 << 14)
+ + 
+ + /* Used by PM_L4PER_HECC1_WKDEP */
+ + #define OMAP4430_WKUPDEP_HECC1_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_HECC1_MPU_MASK					(1 << 0)
+ + 
+ + /* Used by PM_L4PER_HECC2_WKDEP */
+ + #define OMAP4430_WKUPDEP_HECC2_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_HECC2_MPU_MASK					(1 << 0)
+ + 
+ + /* Used by PM_L3INIT_HSI_WKDEP */
+ + #define OMAP4430_WKUPDEP_HSI_DSP_TESLA_SHIFT				6
+ + #define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK				(1 << 6)
+ + 
+ + /* Used by PM_L3INIT_HSI_WKDEP */
+ + #define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_SHIFT				1
+ + #define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK				(1 << 1)
+ + 
+ + /* Used by PM_L3INIT_HSI_WKDEP */
+ + #define OMAP4430_WKUPDEP_HSI_MCU_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_L4PER_I2C1_WKDEP */
+ + #define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_SHIFT				7
+ + #define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK				(1 << 7)
+ + 
+ + /* Used by PM_L4PER_I2C1_WKDEP */
+ + #define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_SHIFT				1
+ + #define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK				(1 << 1)
+ + 
+ + /* Used by PM_L4PER_I2C1_WKDEP */
+ + #define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_L4PER_I2C2_WKDEP */
+ + #define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_SHIFT				7
+ + #define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK				(1 << 7)
+ + 
+ + /* Used by PM_L4PER_I2C2_WKDEP */
+ + #define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_SHIFT				1
+ + #define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK				(1 << 1)
+ + 
+ + /* Used by PM_L4PER_I2C2_WKDEP */
+ + #define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_L4PER_I2C3_WKDEP */
+ + #define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_SHIFT				7
+ + #define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK				(1 << 7)
+ + 
+ + /* Used by PM_L4PER_I2C3_WKDEP */
+ + #define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_SHIFT				1
+ + #define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK				(1 << 1)
+ + 
+ + /* Used by PM_L4PER_I2C3_WKDEP */
+ + #define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_L4PER_I2C4_WKDEP */
+ + #define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_SHIFT				7
+ + #define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK				(1 << 7)
+ + 
+ + /* Used by PM_L4PER_I2C4_WKDEP */
+ + #define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_SHIFT				1
+ + #define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK				(1 << 1)
+ + 
+ + /* Used by PM_L4PER_I2C4_WKDEP */
+ + #define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_L4PER_I2C5_WKDEP */
+ + #define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_SHIFT				7
+ + #define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK				(1 << 7)
+ + 
+ + /* Used by PM_L4PER_I2C5_WKDEP */
+ + #define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_WKUP_KEYBOARD_WKDEP */
+ + #define OMAP4430_WKUPDEP_KEYBOARD_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_ABE_MCASP_WKDEP */
+ + #define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_SHIFT				7
+ + #define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK				(1 << 7)
+ + 
+ + /* Used by PM_ABE_MCASP_WKDEP */
+ + #define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_SHIFT				6
+ + #define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK				(1 << 6)
+ + 
+ + /* Used by PM_ABE_MCASP_WKDEP */
+ + #define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_ABE_MCASP_WKDEP */
+ + #define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_SHIFT				2
+ + #define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK				(1 << 2)
+ + 
+ + /* Used by PM_L4PER_MCASP2_WKDEP */
+ + #define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_SHIFT				7
+ + #define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK				(1 << 7)
+ + 
+ + /* Used by PM_L4PER_MCASP2_WKDEP */
+ + #define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_SHIFT				6
+ + #define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK				(1 << 6)
+ + 
+ + /* Used by PM_L4PER_MCASP2_WKDEP */
+ + #define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_L4PER_MCASP2_WKDEP */
+ + #define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_SHIFT				2
+ + #define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK				(1 << 2)
+ + 
+ + /* Used by PM_L4PER_MCASP3_WKDEP */
+ + #define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_SHIFT				7
+ + #define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK				(1 << 7)
+ + 
+ + /* Used by PM_L4PER_MCASP3_WKDEP */
+ + #define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_SHIFT				6
+ + #define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK				(1 << 6)
+ + 
+ + /* Used by PM_L4PER_MCASP3_WKDEP */
+ + #define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_L4PER_MCASP3_WKDEP */
+ + #define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_SHIFT				2
+ + #define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK				(1 << 2)
+ + 
+ + /* Used by PM_ABE_MCBSP1_WKDEP */
+ + #define OMAP4430_WKUPDEP_MCBSP1_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_ABE_MCBSP1_WKDEP */
+ + #define OMAP4430_WKUPDEP_MCBSP1_SDMA_SHIFT				3
+ + #define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK				(1 << 3)
+ + 
+ + /* Used by PM_ABE_MCBSP1_WKDEP */
+ + #define OMAP4430_WKUPDEP_MCBSP1_TESLA_SHIFT				2
+ + #define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK				(1 << 2)
+ + 
+ + /* Used by PM_ABE_MCBSP2_WKDEP */
+ + #define OMAP4430_WKUPDEP_MCBSP2_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_ABE_MCBSP2_WKDEP */
+ + #define OMAP4430_WKUPDEP_MCBSP2_SDMA_SHIFT				3
+ + #define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK				(1 << 3)
+ + 
+ + /* Used by PM_ABE_MCBSP2_WKDEP */
+ + #define OMAP4430_WKUPDEP_MCBSP2_TESLA_SHIFT				2
+ + #define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK				(1 << 2)
+ + 
+ + /* Used by PM_ABE_MCBSP3_WKDEP */
+ + #define OMAP4430_WKUPDEP_MCBSP3_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_ABE_MCBSP3_WKDEP */
+ + #define OMAP4430_WKUPDEP_MCBSP3_SDMA_SHIFT				3
+ + #define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK				(1 << 3)
+ + 
+ + /* Used by PM_ABE_MCBSP3_WKDEP */
+ + #define OMAP4430_WKUPDEP_MCBSP3_TESLA_SHIFT				2
+ + #define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK				(1 << 2)
+ + 
+ + /* Used by PM_L4PER_MCBSP4_WKDEP */
+ + #define OMAP4430_WKUPDEP_MCBSP4_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_L4PER_MCBSP4_WKDEP */
+ + #define OMAP4430_WKUPDEP_MCBSP4_SDMA_SHIFT				3
+ + #define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK				(1 << 3)
+ + 
+ + /* Used by PM_L4PER_MCBSP4_WKDEP */
+ + #define OMAP4430_WKUPDEP_MCBSP4_TESLA_SHIFT				2
+ + #define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK				(1 << 2)
+ + 
+ + /* Used by PM_L4PER_MCSPI1_WKDEP */
+ + #define OMAP4430_WKUPDEP_MCSPI1_DUCATI_SHIFT				1
+ + #define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK				(1 << 1)
+ + 
+ + /* Used by PM_L4PER_MCSPI1_WKDEP */
+ + #define OMAP4430_WKUPDEP_MCSPI1_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_L4PER_MCSPI1_WKDEP */
+ + #define OMAP4430_WKUPDEP_MCSPI1_SDMA_SHIFT				3
+ + #define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK				(1 << 3)
+ + 
+ + /* Used by PM_L4PER_MCSPI1_WKDEP */
+ + #define OMAP4430_WKUPDEP_MCSPI1_TESLA_SHIFT				2
+ + #define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK				(1 << 2)
+ + 
+ + /* Used by PM_L4PER_MCSPI2_WKDEP */
+ + #define OMAP4430_WKUPDEP_MCSPI2_DUCATI_SHIFT				1
+ + #define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK				(1 << 1)
+ + 
+ + /* Used by PM_L4PER_MCSPI2_WKDEP */
+ + #define OMAP4430_WKUPDEP_MCSPI2_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_L4PER_MCSPI2_WKDEP */
+ + #define OMAP4430_WKUPDEP_MCSPI2_SDMA_SHIFT				3
+ + #define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK				(1 << 3)
+ + 
+ + /* Used by PM_L4PER_MCSPI3_WKDEP */
+ + #define OMAP4430_WKUPDEP_MCSPI3_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_L4PER_MCSPI3_WKDEP */
+ + #define OMAP4430_WKUPDEP_MCSPI3_SDMA_SHIFT				3
+ + #define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK				(1 << 3)
+ + 
+ + /* Used by PM_L4PER_MCSPI4_WKDEP */
+ + #define OMAP4430_WKUPDEP_MCSPI4_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_L4PER_MCSPI4_WKDEP */
+ + #define OMAP4430_WKUPDEP_MCSPI4_SDMA_SHIFT				3
+ + #define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK				(1 << 3)
+ + 
+ + /* Used by PM_L3INIT_MMC1_WKDEP */
+ + #define OMAP4430_WKUPDEP_MMC1_DUCATI_SHIFT				1
+ + #define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK				(1 << 1)
+ + 
+ + /* Used by PM_L3INIT_MMC1_WKDEP */
+ + #define OMAP4430_WKUPDEP_MMC1_MPU_SHIFT					0
+ + #define OMAP4430_WKUPDEP_MMC1_MPU_MASK					(1 << 0)
+ + 
+ + /* Used by PM_L3INIT_MMC1_WKDEP */
+ + #define OMAP4430_WKUPDEP_MMC1_SDMA_SHIFT				3
+ + #define OMAP4430_WKUPDEP_MMC1_SDMA_MASK					(1 << 3)
+ + 
+ + /* Used by PM_L3INIT_MMC1_WKDEP */
+ + #define OMAP4430_WKUPDEP_MMC1_TESLA_SHIFT				2
+ + #define OMAP4430_WKUPDEP_MMC1_TESLA_MASK				(1 << 2)
+ + 
+ + /* Used by PM_L3INIT_MMC2_WKDEP */
+ + #define OMAP4430_WKUPDEP_MMC2_DUCATI_SHIFT				1
+ + #define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK				(1 << 1)
+ + 
+ + /* Used by PM_L3INIT_MMC2_WKDEP */
+ + #define OMAP4430_WKUPDEP_MMC2_MPU_SHIFT					0
+ + #define OMAP4430_WKUPDEP_MMC2_MPU_MASK					(1 << 0)
+ + 
+ + /* Used by PM_L3INIT_MMC2_WKDEP */
+ + #define OMAP4430_WKUPDEP_MMC2_SDMA_SHIFT				3
+ + #define OMAP4430_WKUPDEP_MMC2_SDMA_MASK					(1 << 3)
+ + 
+ + /* Used by PM_L3INIT_MMC2_WKDEP */
+ + #define OMAP4430_WKUPDEP_MMC2_TESLA_SHIFT				2
+ + #define OMAP4430_WKUPDEP_MMC2_TESLA_MASK				(1 << 2)
+ + 
+ + /* Used by PM_L3INIT_MMC6_WKDEP */
+ + #define OMAP4430_WKUPDEP_MMC6_DUCATI_SHIFT				1
+ + #define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK				(1 << 1)
+ + 
+ + /* Used by PM_L3INIT_MMC6_WKDEP */
+ + #define OMAP4430_WKUPDEP_MMC6_MPU_SHIFT					0
+ + #define OMAP4430_WKUPDEP_MMC6_MPU_MASK					(1 << 0)
+ + 
+ + /* Used by PM_L3INIT_MMC6_WKDEP */
+ + #define OMAP4430_WKUPDEP_MMC6_TESLA_SHIFT				2
+ + #define OMAP4430_WKUPDEP_MMC6_TESLA_MASK				(1 << 2)
+ + 
+ + /* Used by PM_L4PER_MMCSD3_WKDEP */
+ + #define OMAP4430_WKUPDEP_MMCSD3_DUCATI_SHIFT				1
+ + #define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK				(1 << 1)
+ + 
+ + /* Used by PM_L4PER_MMCSD3_WKDEP */
+ + #define OMAP4430_WKUPDEP_MMCSD3_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_L4PER_MMCSD3_WKDEP */
+ + #define OMAP4430_WKUPDEP_MMCSD3_SDMA_SHIFT				3
+ + #define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK				(1 << 3)
+ + 
+ + /* Used by PM_L4PER_MMCSD4_WKDEP */
+ + #define OMAP4430_WKUPDEP_MMCSD4_DUCATI_SHIFT				1
+ + #define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK				(1 << 1)
+ + 
+ + /* Used by PM_L4PER_MMCSD4_WKDEP */
+ + #define OMAP4430_WKUPDEP_MMCSD4_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_L4PER_MMCSD4_WKDEP */
+ + #define OMAP4430_WKUPDEP_MMCSD4_SDMA_SHIFT				3
+ + #define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK				(1 << 3)
+ + 
+ + /* Used by PM_L4PER_MMCSD5_WKDEP */
+ + #define OMAP4430_WKUPDEP_MMCSD5_DUCATI_SHIFT				1
+ + #define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK				(1 << 1)
+ + 
+ + /* Used by PM_L4PER_MMCSD5_WKDEP */
+ + #define OMAP4430_WKUPDEP_MMCSD5_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_L4PER_MMCSD5_WKDEP */
+ + #define OMAP4430_WKUPDEP_MMCSD5_SDMA_SHIFT				3
+ + #define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK				(1 << 3)
+ + 
+ + /* Used by PM_L3INIT_PCIESS_WKDEP */
+ + #define OMAP4430_WKUPDEP_PCIESS_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_PCIESS_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_L3INIT_PCIESS_WKDEP */
+ + #define OMAP4430_WKUPDEP_PCIESS_TESLA_SHIFT				2
+ + #define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK				(1 << 2)
+ + 
+ + /* Used by PM_ABE_PDM_WKDEP */
+ + #define OMAP4430_WKUPDEP_PDM_DMA_SDMA_SHIFT				7
+ + #define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK				(1 << 7)
+ + 
+ + /* Used by PM_ABE_PDM_WKDEP */
+ + #define OMAP4430_WKUPDEP_PDM_DMA_TESLA_SHIFT				6
+ + #define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK				(1 << 6)
+ + 
+ + /* Used by PM_ABE_PDM_WKDEP */
+ + #define OMAP4430_WKUPDEP_PDM_IRQ_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_ABE_PDM_WKDEP */
+ + #define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_SHIFT				2
+ + #define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK				(1 << 2)
+ + 
+ + /* Used by PM_WKUP_RTC_WKDEP */
+ + #define OMAP4430_WKUPDEP_RTC_MPU_SHIFT					0
+ + #define OMAP4430_WKUPDEP_RTC_MPU_MASK					(1 << 0)
+ + 
+ + /* Used by PM_L3INIT_SATA_WKDEP */
+ + #define OMAP4430_WKUPDEP_SATA_MPU_SHIFT					0
+ + #define OMAP4430_WKUPDEP_SATA_MPU_MASK					(1 << 0)
+ + 
+ + /* Used by PM_L3INIT_SATA_WKDEP */
+ + #define OMAP4430_WKUPDEP_SATA_TESLA_SHIFT				2
+ + #define OMAP4430_WKUPDEP_SATA_TESLA_MASK				(1 << 2)
+ + 
+ + /* Used by PM_ABE_SLIMBUS_WKDEP */
+ + #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT			7
+ + #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK				(1 << 7)
+ + 
+ + /* Used by PM_ABE_SLIMBUS_WKDEP */
+ + #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_SHIFT			6
+ + #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK			(1 << 6)
+ + 
+ + /* Used by PM_ABE_SLIMBUS_WKDEP */
+ + #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_ABE_SLIMBUS_WKDEP */
+ + #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_SHIFT			2
+ + #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK			(1 << 2)
+ + 
+ + /* Used by PM_L4PER_SLIMBUS2_WKDEP */
+ + #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_SHIFT			7
+ + #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK				(1 << 7)
+ + 
+ + /* Used by PM_L4PER_SLIMBUS2_WKDEP */
+ + #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_SHIFT			6
+ + #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK			(1 << 6)
+ + 
+ + /* Used by PM_L4PER_SLIMBUS2_WKDEP */
+ + #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_L4PER_SLIMBUS2_WKDEP */
+ + #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_SHIFT			2
+ + #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK			(1 << 2)
+ + 
+ + /* Used by PM_ALWON_SR_CORE_WKDEP */
+ + #define OMAP4430_WKUPDEP_SR_CORE_DUCATI_SHIFT				1
+ + #define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK				(1 << 1)
+ + 
+ + /* Used by PM_ALWON_SR_CORE_WKDEP */
+ + #define OMAP4430_WKUPDEP_SR_CORE_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_ALWON_SR_IVA_WKDEP */
+ + #define OMAP4430_WKUPDEP_SR_IVA_DUCATI_SHIFT				1
+ + #define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK				(1 << 1)
+ + 
+ + /* Used by PM_ALWON_SR_IVA_WKDEP */
+ + #define OMAP4430_WKUPDEP_SR_IVA_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_ALWON_SR_MPU_WKDEP */
+ + #define OMAP4430_WKUPDEP_SR_MPU_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_WKUP_TIMER12_WKDEP */
+ + #define OMAP4430_WKUPDEP_TIMER12_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_TIMER12_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_WKUP_TIMER1_WKDEP */
+ + #define OMAP4430_WKUPDEP_TIMER1_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_TIMER1_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_ABE_TIMER5_WKDEP */
+ + #define OMAP4430_WKUPDEP_TIMER5_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_TIMER5_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_ABE_TIMER5_WKDEP */
+ + #define OMAP4430_WKUPDEP_TIMER5_TESLA_SHIFT				2
+ + #define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK				(1 << 2)
+ + 
+ + /* Used by PM_ABE_TIMER6_WKDEP */
+ + #define OMAP4430_WKUPDEP_TIMER6_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_TIMER6_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_ABE_TIMER6_WKDEP */
+ + #define OMAP4430_WKUPDEP_TIMER6_TESLA_SHIFT				2
+ + #define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK				(1 << 2)
+ + 
+ + /* Used by PM_ABE_TIMER7_WKDEP */
+ + #define OMAP4430_WKUPDEP_TIMER7_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_TIMER7_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_ABE_TIMER7_WKDEP */
+ + #define OMAP4430_WKUPDEP_TIMER7_TESLA_SHIFT				2
+ + #define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK				(1 << 2)
+ + 
+ + /* Used by PM_ABE_TIMER8_WKDEP */
+ + #define OMAP4430_WKUPDEP_TIMER8_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_TIMER8_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_ABE_TIMER8_WKDEP */
+ + #define OMAP4430_WKUPDEP_TIMER8_TESLA_SHIFT				2
+ + #define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK				(1 << 2)
+ + 
+ + /* Used by PM_L4PER_UART1_WKDEP */
+ + #define OMAP4430_WKUPDEP_UART1_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_UART1_MPU_MASK					(1 << 0)
+ + 
+ + /* Used by PM_L4PER_UART1_WKDEP */
+ + #define OMAP4430_WKUPDEP_UART1_SDMA_SHIFT				3
+ + #define OMAP4430_WKUPDEP_UART1_SDMA_MASK				(1 << 3)
+ + 
+ + /* Used by PM_L4PER_UART2_WKDEP */
+ + #define OMAP4430_WKUPDEP_UART2_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_UART2_MPU_MASK					(1 << 0)
+ + 
+ + /* Used by PM_L4PER_UART2_WKDEP */
+ + #define OMAP4430_WKUPDEP_UART2_SDMA_SHIFT				3
+ + #define OMAP4430_WKUPDEP_UART2_SDMA_MASK				(1 << 3)
+ + 
+ + /* Used by PM_L4PER_UART3_WKDEP */
+ + #define OMAP4430_WKUPDEP_UART3_DUCATI_SHIFT				1
+ + #define OMAP4430_WKUPDEP_UART3_DUCATI_MASK				(1 << 1)
+ + 
+ + /* Used by PM_L4PER_UART3_WKDEP */
+ + #define OMAP4430_WKUPDEP_UART3_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_UART3_MPU_MASK					(1 << 0)
+ + 
+ + /* Used by PM_L4PER_UART3_WKDEP */
+ + #define OMAP4430_WKUPDEP_UART3_SDMA_SHIFT				3
+ + #define OMAP4430_WKUPDEP_UART3_SDMA_MASK				(1 << 3)
+ + 
+ + /* Used by PM_L4PER_UART3_WKDEP */
+ + #define OMAP4430_WKUPDEP_UART3_TESLA_SHIFT				2
+ + #define OMAP4430_WKUPDEP_UART3_TESLA_MASK				(1 << 2)
+ + 
+ + /* Used by PM_L4PER_UART4_WKDEP */
+ + #define OMAP4430_WKUPDEP_UART4_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_UART4_MPU_MASK					(1 << 0)
+ + 
+ + /* Used by PM_L4PER_UART4_WKDEP */
+ + #define OMAP4430_WKUPDEP_UART4_SDMA_SHIFT				3
+ + #define OMAP4430_WKUPDEP_UART4_SDMA_MASK				(1 << 3)
+ + 
+ + /* Used by PM_L3INIT_UNIPRO1_WKDEP */
+ + #define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_SHIFT				1
+ + #define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK				(1 << 1)
+ + 
+ + /* Used by PM_L3INIT_UNIPRO1_WKDEP */
+ + #define OMAP4430_WKUPDEP_UNIPRO1_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_L3INIT_USB_HOST_WKDEP */
+ + #define OMAP4430_WKUPDEP_USB_HOST_DUCATI_SHIFT				1
+ + #define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK				(1 << 1)
+ + 
+ + /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */
+ + #define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_SHIFT			1
+ + #define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK			(1 << 1)
+ + 
+ + /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */
+ + #define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_L3INIT_USB_HOST_WKDEP */
+ + #define OMAP4430_WKUPDEP_USB_HOST_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_L3INIT_USB_OTG_WKDEP */
+ + #define OMAP4430_WKUPDEP_USB_OTG_DUCATI_SHIFT				1
+ + #define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK				(1 << 1)
+ + 
+ + /* Used by PM_L3INIT_USB_OTG_WKDEP */
+ + #define OMAP4430_WKUPDEP_USB_OTG_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_L3INIT_USB_TLL_WKDEP */
+ + #define OMAP4430_WKUPDEP_USB_TLL_DUCATI_SHIFT				1
+ + #define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK				(1 << 1)
+ + 
+ + /* Used by PM_L3INIT_USB_TLL_WKDEP */
+ + #define OMAP4430_WKUPDEP_USB_TLL_MPU_SHIFT				0
+ + #define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK				(1 << 0)
+ + 
+ + /* Used by PM_WKUP_USIM_WKDEP */
+ + #define OMAP4430_WKUPDEP_USIM_MPU_SHIFT					0
+ + #define OMAP4430_WKUPDEP_USIM_MPU_MASK					(1 << 0)
+ + 
+ + /* Used by PM_WKUP_USIM_WKDEP */
+ + #define OMAP4430_WKUPDEP_USIM_SDMA_SHIFT				3
+ + #define OMAP4430_WKUPDEP_USIM_SDMA_MASK					(1 << 3)
+ + 
+ + /* Used by PM_WKUP_WDT2_WKDEP */
+ + #define OMAP4430_WKUPDEP_WDT2_DUCATI_SHIFT				1
+ + #define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK				(1 << 1)
+ + 
+ + /* Used by PM_WKUP_WDT2_WKDEP */
+ + #define OMAP4430_WKUPDEP_WDT2_MPU_SHIFT					0
+ + #define OMAP4430_WKUPDEP_WDT2_MPU_MASK					(1 << 0)
+ + 
+ + /* Used by PM_ABE_WDT3_WKDEP */
+ + #define OMAP4430_WKUPDEP_WDT3_MPU_SHIFT					0
+ + #define OMAP4430_WKUPDEP_WDT3_MPU_MASK					(1 << 0)
+ + 
+ + /* Used by PM_L3INIT_HSI_WKDEP */
+ + #define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_SHIFT				8
+ + #define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK				(1 << 8)
+ + 
+ + /* Used by PM_L3INIT_XHPI_WKDEP */
+ + #define OMAP4430_WKUPDEP_XHPI_DUCATI_SHIFT				1
+ + #define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK				(1 << 1)
+ + 
+ + /* Used by PRM_IO_PMCTRL */
+ + #define OMAP4430_WUCLK_CTRL_SHIFT					8
+ + #define OMAP4430_WUCLK_CTRL_MASK					(1 << 8)
+ + 
+ + /* Used by PRM_IO_PMCTRL */
+ + #define OMAP4430_WUCLK_STATUS_SHIFT					9
+ + #define OMAP4430_WUCLK_STATUS_MASK					(1 << 9)
+ + 
+ + /* Used by REVISION_PRM */
+ + #define OMAP4430_X_MAJOR_SHIFT						8
+ + #define OMAP4430_X_MAJOR_MASK						(0x7 << 8)
+ + 
+ + /* Used by REVISION_PRM */
+ + #define OMAP4430_Y_MINOR_SHIFT						0
+ + #define OMAP4430_Y_MINOR_MASK						(0x3f << 0)
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/scrm44xx.h linux-3.2.1/arch/arm/mach-ckb_3352/scrm44xx.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/scrm44xx.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/scrm44xx.h	2014-11-25 13:19:15.075039939 +0900
+ ***************
+ *** 0 ****
+ --- 1,175 ----
+ + /*
+ +  * OMAP44xx SCRM registers and bitfields
+ +  *
+ +  * Copyright (C) 2010 Texas Instruments, Inc.
+ +  *
+ +  * Benoit Cousson (b-cousson@ti.com)
+ +  *
+ +  * This file is automatically generated from the OMAP hardware databases.
+ +  * We respectfully ask that any modifications to this file be coordinated
+ +  * with the public linux-omap@vger.kernel.org mailing list and the
+ +  * authors above to ensure that the autogeneration scripts are kept
+ +  * up-to-date with the file contents.
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #ifndef __ARCH_ARM_MACH_OMAP2_SCRM_44XX_H
+ + #define __ARCH_ARM_MACH_OMAP2_SCRM_44XX_H
+ + 
+ + #define OMAP4_SCRM_BASE				0x4a30a000
+ + 
+ + #define OMAP44XX_SCRM_REGADDR(reg)	\
+ + 		OMAP2_L4_IO_ADDRESS(OMAP4_SCRM_BASE + (reg))
+ + 
+ + /* Registers offset */
+ + #define OMAP4_SCRM_REVISION_SCRM_OFFSET		0x0000
+ + #define OMAP4_SCRM_REVISION_SCRM		OMAP44XX_SCRM_REGADDR(0x0000)
+ + #define OMAP4_SCRM_CLKSETUPTIME_OFFSET		0x0100
+ + #define OMAP4_SCRM_CLKSETUPTIME			OMAP44XX_SCRM_REGADDR(0x0100)
+ + #define OMAP4_SCRM_PMICSETUPTIME_OFFSET		0x0104
+ + #define OMAP4_SCRM_PMICSETUPTIME		OMAP44XX_SCRM_REGADDR(0x0104)
+ + #define OMAP4_SCRM_ALTCLKSRC_OFFSET		0x0110
+ + #define OMAP4_SCRM_ALTCLKSRC			OMAP44XX_SCRM_REGADDR(0x0110)
+ + #define OMAP4_SCRM_MODEMCLKM_OFFSET		0x0118
+ + #define OMAP4_SCRM_MODEMCLKM			OMAP44XX_SCRM_REGADDR(0x0118)
+ + #define OMAP4_SCRM_D2DCLKM_OFFSET		0x011c
+ + #define OMAP4_SCRM_D2DCLKM			OMAP44XX_SCRM_REGADDR(0x011c)
+ + #define OMAP4_SCRM_EXTCLKREQ_OFFSET		0x0200
+ + #define OMAP4_SCRM_EXTCLKREQ			OMAP44XX_SCRM_REGADDR(0x0200)
+ + #define OMAP4_SCRM_ACCCLKREQ_OFFSET		0x0204
+ + #define OMAP4_SCRM_ACCCLKREQ			OMAP44XX_SCRM_REGADDR(0x0204)
+ + #define OMAP4_SCRM_PWRREQ_OFFSET		0x0208
+ + #define OMAP4_SCRM_PWRREQ			OMAP44XX_SCRM_REGADDR(0x0208)
+ + #define OMAP4_SCRM_AUXCLKREQ0_OFFSET		0x0210
+ + #define OMAP4_SCRM_AUXCLKREQ0			OMAP44XX_SCRM_REGADDR(0x0210)
+ + #define OMAP4_SCRM_AUXCLKREQ1_OFFSET		0x0214
+ + #define OMAP4_SCRM_AUXCLKREQ1			OMAP44XX_SCRM_REGADDR(0x0214)
+ + #define OMAP4_SCRM_AUXCLKREQ2_OFFSET		0x0218
+ + #define OMAP4_SCRM_AUXCLKREQ2			OMAP44XX_SCRM_REGADDR(0x0218)
+ + #define OMAP4_SCRM_AUXCLKREQ3_OFFSET		0x021c
+ + #define OMAP4_SCRM_AUXCLKREQ3			OMAP44XX_SCRM_REGADDR(0x021c)
+ + #define OMAP4_SCRM_AUXCLKREQ4_OFFSET		0x0220
+ + #define OMAP4_SCRM_AUXCLKREQ4			OMAP44XX_SCRM_REGADDR(0x0220)
+ + #define OMAP4_SCRM_AUXCLKREQ5_OFFSET		0x0224
+ + #define OMAP4_SCRM_AUXCLKREQ5			OMAP44XX_SCRM_REGADDR(0x0224)
+ + #define OMAP4_SCRM_D2DCLKREQ_OFFSET		0x0234
+ + #define OMAP4_SCRM_D2DCLKREQ			OMAP44XX_SCRM_REGADDR(0x0234)
+ + #define OMAP4_SCRM_AUXCLK0_OFFSET		0x0310
+ + #define OMAP4_SCRM_AUXCLK0			OMAP44XX_SCRM_REGADDR(0x0310)
+ + #define OMAP4_SCRM_AUXCLK1_OFFSET		0x0314
+ + #define OMAP4_SCRM_AUXCLK1			OMAP44XX_SCRM_REGADDR(0x0314)
+ + #define OMAP4_SCRM_AUXCLK2_OFFSET		0x0318
+ + #define OMAP4_SCRM_AUXCLK2			OMAP44XX_SCRM_REGADDR(0x0318)
+ + #define OMAP4_SCRM_AUXCLK3_OFFSET		0x031c
+ + #define OMAP4_SCRM_AUXCLK3			OMAP44XX_SCRM_REGADDR(0x031c)
+ + #define OMAP4_SCRM_AUXCLK4_OFFSET		0x0320
+ + #define OMAP4_SCRM_AUXCLK4			OMAP44XX_SCRM_REGADDR(0x0320)
+ + #define OMAP4_SCRM_AUXCLK5_OFFSET		0x0324
+ + #define OMAP4_SCRM_AUXCLK5			OMAP44XX_SCRM_REGADDR(0x0324)
+ + #define OMAP4_SCRM_RSTTIME_OFFSET		0x0400
+ + #define OMAP4_SCRM_RSTTIME			OMAP44XX_SCRM_REGADDR(0x0400)
+ + #define OMAP4_SCRM_MODEMRSTCTRL_OFFSET		0x0418
+ + #define OMAP4_SCRM_MODEMRSTCTRL			OMAP44XX_SCRM_REGADDR(0x0418)
+ + #define OMAP4_SCRM_D2DRSTCTRL_OFFSET		0x041c
+ + #define OMAP4_SCRM_D2DRSTCTRL			OMAP44XX_SCRM_REGADDR(0x041c)
+ + #define OMAP4_SCRM_EXTPWRONRSTCTRL_OFFSET	0x0420
+ + #define OMAP4_SCRM_EXTPWRONRSTCTRL		OMAP44XX_SCRM_REGADDR(0x0420)
+ + #define OMAP4_SCRM_EXTWARMRSTST_OFFSET		0x0510
+ + #define OMAP4_SCRM_EXTWARMRSTST			OMAP44XX_SCRM_REGADDR(0x0510)
+ + #define OMAP4_SCRM_APEWARMRSTST_OFFSET		0x0514
+ + #define OMAP4_SCRM_APEWARMRSTST			OMAP44XX_SCRM_REGADDR(0x0514)
+ + #define OMAP4_SCRM_MODEMWARMRSTST_OFFSET	0x0518
+ + #define OMAP4_SCRM_MODEMWARMRSTST		OMAP44XX_SCRM_REGADDR(0x0518)
+ + #define OMAP4_SCRM_D2DWARMRSTST_OFFSET		0x051c
+ + #define OMAP4_SCRM_D2DWARMRSTST			OMAP44XX_SCRM_REGADDR(0x051c)
+ + 
+ + /* Registers shifts and masks */
+ + 
+ + /* REVISION_SCRM */
+ + #define OMAP4_REV_SHIFT				0
+ + #define OMAP4_REV_MASK				(0xff << 0)
+ + 
+ + /* CLKSETUPTIME */
+ + #define OMAP4_DOWNTIME_SHIFT			16
+ + #define OMAP4_DOWNTIME_MASK			(0x3f << 16)
+ + #define OMAP4_SETUPTIME_SHIFT			0
+ + #define OMAP4_SETUPTIME_MASK			(0xfff << 0)
+ + 
+ + /* PMICSETUPTIME */
+ + #define OMAP4_WAKEUPTIME_SHIFT			16
+ + #define OMAP4_WAKEUPTIME_MASK			(0x3f << 16)
+ + #define OMAP4_SLEEPTIME_SHIFT			0
+ + #define OMAP4_SLEEPTIME_MASK			(0x3f << 0)
+ + 
+ + /* ALTCLKSRC */
+ + #define OMAP4_ENABLE_EXT_SHIFT			3
+ + #define OMAP4_ENABLE_EXT_MASK			(1 << 3)
+ + #define OMAP4_ENABLE_INT_SHIFT			2
+ + #define OMAP4_ENABLE_INT_MASK			(1 << 2)
+ + #define OMAP4_ALTCLKSRC_MODE_SHIFT		0
+ + #define OMAP4_ALTCLKSRC_MODE_MASK		(0x3 << 0)
+ + 
+ + /* MODEMCLKM */
+ + #define OMAP4_CLK_32KHZ_SHIFT			0
+ + #define OMAP4_CLK_32KHZ_MASK			(1 << 0)
+ + 
+ + /* D2DCLKM */
+ + #define OMAP4_SYSCLK_SHIFT			1
+ + #define OMAP4_SYSCLK_MASK			(1 << 1)
+ + 
+ + /* EXTCLKREQ */
+ + #define OMAP4_POLARITY_SHIFT			0
+ + #define OMAP4_POLARITY_MASK			(1 << 0)
+ + 
+ + /* AUXCLKREQ0 */
+ + #define OMAP4_MAPPING_SHIFT			2
+ + #define OMAP4_MAPPING_MASK			(0x7 << 2)
+ + #define OMAP4_ACCURACY_SHIFT			1
+ + #define OMAP4_ACCURACY_MASK			(1 << 1)
+ + 
+ + /* AUXCLK0 */
+ + #define OMAP4_CLKDIV_SHIFT			16
+ + #define OMAP4_CLKDIV_MASK			(0xf << 16)
+ + #define OMAP4_DISABLECLK_SHIFT			9
+ + #define OMAP4_DISABLECLK_MASK			(1 << 9)
+ + #define OMAP4_ENABLE_SHIFT			8
+ + #define OMAP4_ENABLE_MASK			(1 << 8)
+ + #define OMAP4_SRCSELECT_SHIFT			1
+ + #define OMAP4_SRCSELECT_MASK			(0x3 << 1)
+ + 
+ + /* RSTTIME */
+ + #define OMAP4_RSTTIME_SHIFT			0
+ + #define OMAP4_RSTTIME_MASK			(0xf << 0)
+ + 
+ + /* MODEMRSTCTRL */
+ + #define OMAP4_WARMRST_SHIFT			1
+ + #define OMAP4_WARMRST_MASK			(1 << 1)
+ + #define OMAP4_COLDRST_SHIFT			0
+ + #define OMAP4_COLDRST_MASK			(1 << 0)
+ + 
+ + /* EXTPWRONRSTCTRL */
+ + #define OMAP4_PWRONRST_SHIFT			1
+ + #define OMAP4_PWRONRST_MASK			(1 << 1)
+ + #define OMAP4_ENABLE_EXTPWRONRSTCTRL_SHIFT	0
+ + #define OMAP4_ENABLE_EXTPWRONRSTCTRL_MASK	(1 << 0)
+ + 
+ + /* EXTWARMRSTST */
+ + #define OMAP4_EXTWARMRSTST_SHIFT		0
+ + #define OMAP4_EXTWARMRSTST_MASK			(1 << 0)
+ + 
+ + /* APEWARMRSTST */
+ + #define OMAP4_APEWARMRSTST_SHIFT		1
+ + #define OMAP4_APEWARMRSTST_MASK			(1 << 1)
+ + 
+ + /* MODEMWARMRSTST */
+ + #define OMAP4_MODEMWARMRSTST_SHIFT		2
+ + #define OMAP4_MODEMWARMRSTST_MASK		(1 << 2)
+ + 
+ + /* D2DWARMRSTST */
+ + #define OMAP4_D2DWARMRSTST_SHIFT		3
+ + #define OMAP4_D2DWARMRSTST_MASK			(1 << 3)
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/sdrc.c linux-3.2.1/arch/arm/mach-ckb_3352/sdrc.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/sdrc.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/sdrc.c	2014-11-25 13:19:15.075039939 +0900
+ ***************
+ *** 0 ****
+ --- 1,178 ----
+ + /*
+ +  * SMS/SDRC (SDRAM controller) common code for OMAP2/3
+ +  *
+ +  * Copyright (C) 2005, 2008 Texas Instruments Inc.
+ +  * Copyright (C) 2005, 2008 Nokia Corporation
+ +  *
+ +  * Tony Lindgren <tony@atomide.com>
+ +  * Paul Walmsley
+ +  * Richard Woodruff <r-woodruff2@ti.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + #undef DEBUG
+ + 
+ + #include <linux/module.h>
+ + #include <linux/kernel.h>
+ + #include <linux/device.h>
+ + #include <linux/list.h>
+ + #include <linux/errno.h>
+ + #include <linux/delay.h>
+ + #include <linux/clk.h>
+ + #include <linux/io.h>
+ + 
+ + #include "common.h"
+ + #include <plat/clock.h>
+ + #include <plat/sram.h>
+ + 
+ + #include <plat/sdrc.h>
+ + #include "sdrc.h"
+ + 
+ + static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1;
+ + 
+ + void __iomem *omap2_sdrc_base;
+ + void __iomem *omap2_sms_base;
+ + 
+ + struct omap2_sms_regs {
+ + 	u32	sms_sysconfig;
+ + };
+ + 
+ + static struct omap2_sms_regs sms_context;
+ + 
+ + /* SDRC_POWER register bits */
+ + #define SDRC_POWER_EXTCLKDIS_SHIFT		3
+ + #define SDRC_POWER_PWDENA_SHIFT			2
+ + #define SDRC_POWER_PAGEPOLICY_SHIFT		0
+ + 
+ + /**
+ +  * omap2_sms_save_context - Save SMS registers
+ +  *
+ +  * Save SMS registers that need to be restored after off mode.
+ +  */
+ + void omap2_sms_save_context(void)
+ + {
+ + 	sms_context.sms_sysconfig = sms_read_reg(SMS_SYSCONFIG);
+ + }
+ + 
+ + /**
+ +  * omap2_sms_restore_context - Restore SMS registers
+ +  *
+ +  * Restore SMS registers that need to be Restored after off mode.
+ +  */
+ + void omap2_sms_restore_context(void)
+ + {
+ + 	sms_write_reg(sms_context.sms_sysconfig, SMS_SYSCONFIG);
+ + }
+ + 
+ + /**
+ +  * omap2_sdrc_get_params - return SDRC register values for a given clock rate
+ +  * @r: SDRC clock rate (in Hz)
+ +  * @sdrc_cs0: chip select 0 ram timings **
+ +  * @sdrc_cs1: chip select 1 ram timings **
+ +  *
+ +  * Return pre-calculated values for the SDRC_ACTIM_CTRLA,
+ +  *  SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in sdrc_cs[01]
+ +  *  structs,for a given SDRC clock rate 'r'.
+ +  * These parameters control various timing delays in the SDRAM controller
+ +  *  that are expressed in terms of the number of SDRC clock cycles to
+ +  *  wait; hence the clock rate dependency.
+ +  *
+ +  * Supports 2 different timing parameters for both chip selects.
+ +  *
+ +  * Note 1: the sdrc_init_params_cs[01] must be sorted rate descending.
+ +  * Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same size
+ +  *  as sdrc_init_params_cs_0.
+ +  *
+ +  * Fills in the struct omap_sdrc_params * for each chip select.
+ +  * Returns 0 upon success or -1 upon failure.
+ +  */
+ + int omap2_sdrc_get_params(unsigned long r,
+ + 			  struct omap_sdrc_params **sdrc_cs0,
+ + 			  struct omap_sdrc_params **sdrc_cs1)
+ + {
+ + 	struct omap_sdrc_params *sp0, *sp1;
+ + 
+ + 	if (!sdrc_init_params_cs0)
+ + 		return -1;
+ + 
+ + 	sp0 = sdrc_init_params_cs0;
+ + 	sp1 = sdrc_init_params_cs1;
+ + 
+ + 	while (sp0->rate && sp0->rate != r) {
+ + 		sp0++;
+ + 		if (sdrc_init_params_cs1)
+ + 			sp1++;
+ + 	}
+ + 
+ + 	if (!sp0->rate)
+ + 		return -1;
+ + 
+ + 	*sdrc_cs0 = sp0;
+ + 	*sdrc_cs1 = sp1;
+ + 	return 0;
+ + }
+ + 
+ + 
+ + void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals)
+ + {
+ + 	if (omap2_globals->sdrc)
+ + 		omap2_sdrc_base = omap2_globals->sdrc;
+ + 	if (omap2_globals->sms)
+ + 		omap2_sms_base = omap2_globals->sms;
+ + }
+ + 
+ + /**
+ +  * omap2_sdrc_init - initialize SMS, SDRC devices on boot
+ +  * @sdrc_cs[01]: pointers to a null-terminated list of struct omap_sdrc_params
+ +  *  Support for 2 chip selects timings
+ +  *
+ +  * Turn on smart idle modes for SDRAM scheduler and controller.
+ +  * Program a known-good configuration for the SDRC to deal with buggy
+ +  * bootloaders.
+ +  */
+ + void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
+ + 			    struct omap_sdrc_params *sdrc_cs1)
+ + {
+ + 	u32 l;
+ + 
+ + 	l = sms_read_reg(SMS_SYSCONFIG);
+ + 	l &= ~(0x3 << 3);
+ + 	l |= (0x2 << 3);
+ + 	sms_write_reg(l, SMS_SYSCONFIG);
+ + 
+ + 	l = sdrc_read_reg(SDRC_SYSCONFIG);
+ + 	l &= ~(0x3 << 3);
+ + 	l |= (0x2 << 3);
+ + 	sdrc_write_reg(l, SDRC_SYSCONFIG);
+ + 
+ + 	sdrc_init_params_cs0 = sdrc_cs0;
+ + 	sdrc_init_params_cs1 = sdrc_cs1;
+ + 
+ + 	/* XXX Enable SRFRONIDLEREQ here also? */
+ + 	/*
+ + 	 * PWDENA should not be set due to 34xx erratum 1.150 - PWDENA
+ + 	 * can cause random memory corruption
+ + 	 */
+ + 	l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
+ + 		(1 << SDRC_POWER_PAGEPOLICY_SHIFT);
+ + 	sdrc_write_reg(l, SDRC_POWER);
+ + 	omap2_sms_save_context();
+ + }
+ + 
+ + void omap2_sms_write_rot_control(u32 val, unsigned ctx)
+ + {
+ + 	sms_write_reg(val, SMS_ROT_CONTROL(ctx));
+ + }
+ + 
+ + void omap2_sms_write_rot_size(u32 val, unsigned ctx)
+ + {
+ + 	sms_write_reg(val, SMS_ROT_SIZE(ctx));
+ + }
+ + 
+ + void omap2_sms_write_rot_physical_ba(u32 val, unsigned ctx)
+ + {
+ + 	sms_write_reg(val, SMS_ROT_PHYSICAL_BA(ctx));
+ + }
+ + 
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/sdrc.h linux-3.2.1/arch/arm/mach-ckb_3352/sdrc.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/sdrc.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/sdrc.h	2014-11-25 13:19:15.075039939 +0900
+ ***************
+ *** 0 ****
+ --- 1,70 ----
+ + #ifndef __ARCH_ARM_MACH_OMAP2_SDRC_H
+ + #define __ARCH_ARM_MACH_OMAP2_SDRC_H
+ + 
+ + /*
+ +  * OMAP2 SDRC register definitions
+ +  *
+ +  * Copyright (C) 2007 Texas Instruments, Inc.
+ +  * Copyright (C) 2007 Nokia Corporation
+ +  *
+ +  * Written by Paul Walmsley
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + #undef DEBUG
+ + 
+ + #include <plat/sdrc.h>
+ + 
+ + #ifndef __ASSEMBLER__
+ + 
+ + #include <linux/io.h>
+ + 
+ + extern void __iomem *omap2_sdrc_base;
+ + extern void __iomem *omap2_sms_base;
+ + 
+ + #define OMAP_SDRC_REGADDR(reg)			(omap2_sdrc_base + (reg))
+ + #define OMAP_SMS_REGADDR(reg)			(omap2_sms_base + (reg))
+ + 
+ + /* SDRC global register get/set */
+ + 
+ + static inline void sdrc_write_reg(u32 val, u16 reg)
+ + {
+ + 	__raw_writel(val, OMAP_SDRC_REGADDR(reg));
+ + }
+ + 
+ + static inline u32 sdrc_read_reg(u16 reg)
+ + {
+ + 	return __raw_readl(OMAP_SDRC_REGADDR(reg));
+ + }
+ + 
+ + /* SMS global register get/set */
+ + 
+ + static inline void sms_write_reg(u32 val, u16 reg)
+ + {
+ + 	__raw_writel(val, OMAP_SMS_REGADDR(reg));
+ + }
+ + 
+ + static inline u32 sms_read_reg(u16 reg)
+ + {
+ + 	return __raw_readl(OMAP_SMS_REGADDR(reg));
+ + }
+ + #else
+ + #define OMAP34XX_SDRC_REGADDR(reg)					\
+ + 			OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
+ + #endif	/* __ASSEMBLER__ */
+ + 
+ + /* Minimum frequency that the SDRC DLL can lock at */
+ + #define MIN_SDRC_DLL_LOCK_FREQ		83000000
+ + 
+ + /* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */
+ + #define SDRC_MPURATE_BASE_SHIFT		9
+ + 
+ + /*
+ +  * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at
+ +  * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize
+ +  */
+ + #define SDRC_MPURATE_LOOPS		96
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/serial.c linux-3.2.1/arch/arm/mach-ckb_3352/serial.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/serial.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/serial.c	2014-11-25 13:19:15.075039939 +0900
+ ***************
+ *** 0 ****
+ --- 1,299 ----
+ + /*
+ +  * arch/arm/mach-omap2/serial.c
+ +  *
+ +  * OMAP2 serial support.
+ +  *
+ +  * Copyright (C) 2005-2008 Nokia Corporation
+ +  * Author: Paul Mundt <paul.mundt@nokia.com>
+ +  *
+ +  * Major rework for PM support by Kevin Hilman
+ +  *
+ +  * Based off of arch/arm/mach-omap/omap1/serial.c
+ +  *
+ +  * Copyright (C) 2009 Texas Instruments
+ +  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
+ +  *
+ +  * This file is subject to the terms and conditions of the GNU General Public
+ +  * License. See the file "COPYING" in the main directory of this archive
+ +  * for more details.
+ +  */
+ + #include <linux/kernel.h>
+ + #include <linux/init.h>
+ + #include <linux/clk.h>
+ + #include <linux/io.h>
+ + #include <linux/delay.h>
+ + #include <linux/platform_device.h>
+ + #include <linux/slab.h>
+ + #include <linux/pm_runtime.h>
+ + #include <linux/console.h>
+ + 
+ + #include <plat/omap-serial.h>
+ + #include "common.h"
+ + #include <plat/board.h>
+ + #include <plat/dma.h>
+ + #include <plat/omap_hwmod.h>
+ + #include <plat/omap_device.h>
+ + #include <plat/omap-pm.h>
+ + 
+ + #include "prm2xxx_3xxx.h"
+ + #include "pm.h"
+ + #include "cm2xxx_3xxx.h"
+ + #include "prm-regbits-34xx.h"
+ + #include "control.h"
+ + #include "mux.h"
+ + 
+ + /*
+ +  * NOTE: By default the serial auto_suspend timeout is disabled as it causes
+ +  * lost characters over the serial ports. This means that the UART clocks will
+ +  * stay on until power/autosuspend_delay is set for the uart from sysfs.
+ +  * This also causes that any deeper omap sleep states are blocked.
+ +  */
+ + #define DEFAULT_AUTOSUSPEND_DELAY	-1
+ + 
+ + #define MAX_UART_HWMOD_NAME_LEN		16
+ + 
+ + struct omap_uart_state {
+ + 	int num;
+ + 	int can_sleep;
+ + 
+ + 	struct list_head node;
+ + 	struct omap_hwmod *oh;
+ + 	struct platform_device *pdev;
+ + };
+ + 
+ + static LIST_HEAD(uart_list);
+ + static u8 num_uarts;
+ + static u8 console_uart_id = -1;
+ + static u8 no_console_suspend;
+ + static u8 uart_debug;
+ + 
+ + #define DEFAULT_RXDMA_POLLRATE		1	/* RX DMA polling rate (us) */
+ + #define DEFAULT_RXDMA_BUFSIZE		4096	/* RX DMA buffer size */
+ + #define DEFAULT_RXDMA_TIMEOUT		(3 * HZ)/* RX DMA timeout (jiffies) */
+ + 
+ + static struct omap_uart_port_info omap_serial_default_info[] __initdata = {
+ + 	{
+ + 		.dma_enabled	= false,
+ + 		.dma_rx_buf_size = DEFAULT_RXDMA_BUFSIZE,
+ + 		.dma_rx_poll_rate = DEFAULT_RXDMA_POLLRATE,
+ + 		.dma_rx_timeout = DEFAULT_RXDMA_TIMEOUT,
+ + 		.autosuspend_timeout = DEFAULT_AUTOSUSPEND_DELAY,
+ + 	},
+ + };
+ + 
+ + #ifdef CONFIG_PM
+ + static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable)
+ + {
+ + 	struct omap_device *od = to_omap_device(pdev);
+ + 
+ + 	if (!od)
+ + 		return;
+ + 
+ + 	if (enable)
+ + 		omap_hwmod_enable_wakeup(od->hwmods[0]);
+ + 	else
+ + 		omap_hwmod_disable_wakeup(od->hwmods[0]);
+ + }
+ + 
+ + /*
+ +  * Errata i291: [UART]:Cannot Acknowledge Idle Requests
+ +  * in Smartidle Mode When Configured for DMA Operations.
+ +  * WA: configure uart in force idle mode.
+ +  */
+ + static void omap_uart_set_noidle(struct platform_device *pdev)
+ + {
+ + 	struct omap_device *od = to_omap_device(pdev);
+ + 
+ + 	omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_NO);
+ + }
+ + 
+ + static void omap_uart_set_forceidle(struct platform_device *pdev)
+ + {
+ + 	struct omap_device *od = to_omap_device(pdev);
+ + 
+ + 	omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_FORCE);
+ + }
+ + 
+ + #else
+ + static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable)
+ + {}
+ + static void omap_uart_set_noidle(struct platform_device *pdev) {}
+ + static void omap_uart_set_forceidle(struct platform_device *pdev) {}
+ + #endif /* CONFIG_PM */
+ + 
+ + char *cmdline_find_option(char *str)
+ + {
+ + 	extern char *saved_command_line;
+ + 
+ + 	return strstr(saved_command_line, str);
+ + }
+ + 
+ + static int __init omap_serial_early_init(void)
+ + {
+ + 	do {
+ + 		char oh_name[MAX_UART_HWMOD_NAME_LEN];
+ + 		struct omap_hwmod *oh;
+ + 		struct omap_uart_state *uart;
+ + 		char uart_name[MAX_UART_HWMOD_NAME_LEN];
+ + 
+ + 		snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN,
+ + 			 "uart%d", num_uarts + 1);
+ + 		oh = omap_hwmod_lookup(oh_name);
+ + 		if (!oh)
+ + 			break;
+ + 
+ + 		uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL);
+ + 		if (WARN_ON(!uart))
+ + 			return -ENODEV;
+ + 
+ + 		uart->oh = oh;
+ + 		uart->num = num_uarts++;
+ + 		list_add_tail(&uart->node, &uart_list);
+ + 		snprintf(uart_name, MAX_UART_HWMOD_NAME_LEN,
+ + 				"%s%d", OMAP_SERIAL_NAME, uart->num);
+ + 
+ + 		if (cmdline_find_option(uart_name)) {
+ + 			console_uart_id = uart->num;
+ + 
+ + 			if (console_loglevel >= 10) {
+ + 				uart_debug = true;
+ + 				pr_info("%s used as console in debug mode"
+ + 						" uart%d clocks will not be"
+ + 						" gated", uart_name, uart->num);
+ + 			}
+ + 
+ + 			if (cmdline_find_option("no_console_suspend"))
+ + 				no_console_suspend = true;
+ + 
+ + 			/*
+ + 			 * omap-uart can be used for earlyprintk logs
+ + 			 * So if omap-uart is used as console then prevent
+ + 			 * uart reset and idle to get logs from omap-uart
+ + 			 * until uart console driver is available to take
+ + 			 * care for console messages.
+ + 			 * Idling or resetting omap-uart while printing logs
+ + 			 * early boot logs can stall the boot-up.
+ + 			 */
+ + 			oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET;
+ + 		}
+ + 	} while (1);
+ + 
+ + 	return 0;
+ + }
+ + core_initcall(omap_serial_early_init);
+ + 
+ + /**
+ +  * omap_serial_init_port() - initialize single serial port
+ +  * @bdata: port specific board data pointer
+ +  * @info: platform specific data pointer
+ +  *
+ +  * This function initialies serial driver for given port only.
+ +  * Platforms can call this function instead of omap_serial_init()
+ +  * if they don't plan to use all available UARTs as serial ports.
+ +  *
+ +  * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
+ +  * use only one of the two.
+ +  */
+ + void __init omap_serial_init_port(struct omap_board_data *bdata,
+ + 			struct omap_uart_port_info *info)
+ + {
+ + 	struct omap_uart_state *uart;
+ + 	struct omap_hwmod *oh;
+ + 	struct platform_device *pdev;
+ + 	void *pdata = NULL;
+ + 	u32 pdata_size = 0;
+ + 	char *name;
+ + 	struct omap_uart_port_info omap_up;
+ + 
+ + 	if (WARN_ON(!bdata))
+ + 		return;
+ + 	if (WARN_ON(bdata->id < 0))
+ + 		return;
+ + 	if (WARN_ON(bdata->id >= num_uarts))
+ + 		return;
+ + 
+ + 	list_for_each_entry(uart, &uart_list, node)
+ + 		if (bdata->id == uart->num)
+ + 			break;
+ + 	if (!info)
+ + 		info = omap_serial_default_info;
+ + 
+ + 	oh = uart->oh;
+ + 	name = DRIVER_NAME;
+ + 
+ + 	omap_up.dma_enabled = info->dma_enabled;
+ + 	omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
+ + 	omap_up.flags = UPF_BOOT_AUTOCONF;
+ + 	omap_up.get_context_loss_count = omap_pm_get_dev_context_loss_count;
+ + 	omap_up.set_forceidle = omap_uart_set_forceidle;
+ + 	omap_up.set_noidle = omap_uart_set_noidle;
+ + 	omap_up.enable_wakeup = omap_uart_enable_wakeup;
+ + 	omap_up.dma_rx_buf_size = info->dma_rx_buf_size;
+ + 	omap_up.dma_rx_timeout = info->dma_rx_timeout;
+ + 	omap_up.dma_rx_poll_rate = info->dma_rx_poll_rate;
+ + 	omap_up.autosuspend_timeout = info->autosuspend_timeout;
+ + 
+ + 	/* Enable the MDR1 Errata i202 for OMAP2430/3xxx/44xx */
+ + 	omap_up.errata |= UART_ERRATA_i202_MDR1_ACCESS;
+ + 
+ + 	pdata = &omap_up;
+ + 	pdata_size = sizeof(struct omap_uart_port_info);
+ + 
+ + 	if (WARN_ON(!oh))
+ + 		return;
+ + 
+ + 	pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size,
+ + 				 NULL, 0, false);
+ + 	WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n",
+ + 	     name, oh->name);
+ + 
+ + 	if ((console_uart_id == bdata->id) && no_console_suspend)
+ + 		omap_device_disable_idle_on_suspend(pdev);
+ + 
+ + 	oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
+ + 
+ + 	uart->pdev = pdev;
+ + 
+ + 	oh->dev_attr = uart;
+ + 
+ + 	if (bdata->pads	&& !uart_debug)
+ + 		device_init_wakeup(&pdev->dev, true);
+ + }
+ + 
+ + /**
+ +  * omap_serial_board_init() - initialize all supported serial ports
+ +  * @info: platform specific data pointer
+ +  *
+ +  * Initializes all available UARTs as serial ports. Platforms
+ +  * can call this function when they want to have default behaviour
+ +  * for serial ports (e.g initialize them all as serial ports).
+ +  */
+ + void __init omap_serial_board_init(struct omap_uart_port_info *info)
+ + {
+ + 	struct omap_uart_state *uart;
+ + 	struct omap_board_data bdata;
+ + 
+ + 	list_for_each_entry(uart, &uart_list, node) {
+ + 		bdata.id = uart->num;
+ + 		bdata.flags = 0;
+ + 		bdata.pads = NULL;
+ + 		bdata.pads_cnt = 0;
+ + 
+ + 		if (!info)
+ + 			omap_serial_init_port(&bdata, NULL);
+ + 		else
+ + 			omap_serial_init_port(&bdata, &info[uart->num]);
+ + 	}
+ + }
+ + 
+ + /**
+ +  * omap_serial_init() - initialize all supported serial ports
+ +  *
+ +  * Initializes all available UARTs.
+ +  * Platforms can call this function when they want to have default behaviour
+ +  * for serial ports (e.g initialize them all as serial ports).
+ +  */
+ + void __init omap_serial_init(void)
+ + {
+ + 	omap_serial_board_init(NULL);
+ + }
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/sleep33xx.S linux-3.2.1/arch/arm/mach-ckb_3352/sleep33xx.S
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/sleep33xx.S	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/sleep33xx.S	2014-11-25 13:19:15.079528500 +0900
+ ***************
+ *** 0 ****
+ --- 1,919 ----
+ + 
+ + /*
+ +  * Low level suspend code for AM33XX SoCs
+ +  *
+ +  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #include <linux/linkage.h>
+ + #include <linux/init.h>
+ + #include <asm/memory.h>
+ + #include <asm/assembler.h>
+ + #include <mach/io.h>
+ + 
+ + #include <plat/emif.h>
+ + #include <plat/sram.h>
+ + #include <plat/gpio.h>
+ + 
+ + #include "cm33xx.h"
+ + #include "pm33xx.h"
+ + #include "prm33xx.h"
+ + #include "control.h"
+ + 
+ + /*
+ +  * We should probably pass in the virtual address of PRCM, Control and EMIF
+ +  * along with the physical addresses, load it into the registers
+ +  * and then continue.
+ +  *
+ +  * This routine is executed from internal RAM and expects the memory type and
+ +  * other DDR configuration values which are different across different memory
+ +  * types to be passed in r0 _strictly_ in following order:
+ +  * 1) memory_type [r0]
+ +  * 2) susp_vtp_ctrl_val [r1]
+ +  * 3) evm_id [r2]
+ +  * 4) cpu_rev [r3]
+ +  * 5) suspend_state[r4]
+ +  *
+ +  * The code loads these values taking r0 value as reference to the array in
+ +  * registers starting from r0, i,e memory_type goes to r0 and susp_vtp_ctrl_val
+ +  * goes to r1 and so on. These are then saved into memory locations before
+ +  * proceeding with the sleep sequence and hence registers r0,r1 can still be
+ +  * used in the rest of the sleep code.
+ +  *
+ +  * mem_type is used to decide different suspend-resume sequences for DDR2
+ +  * and DDR3.
+ +  * cpu_rev is used to have/skip certain steps selectively for PG2.0 suspend-resume
+ +  * sequence like switching to LVCMOS mode is not required for PG2.0.
+ +  */
+ + 	.align 3
+ + ENTRY(am33xx_do_wfi)
+ + 	stmfd	sp!, {r4 - r11, lr}	@ save registers on stack
+ + 
+ + 	.macro	pll_bypass, name, clk_mode_addr, idlest_addr, pll_mode
+ + pll_bypass_\name:
+ + 	ldr	r0, \clk_mode_addr
+ + 	ldr	r1, [r0]
+ + 	str	r1, clk_mode_\pll_mode
+ + 	bic	r1, r1, #(7 << 0)
+ + 	orr	r1, r1, #0x5
+ + 	str	r1, [r0]
+ + 	ldr	r0, \idlest_addr
+ + wait_pll_bypass_\name:
+ + 	ldr	r1, [r0]
+ + 	tst	r1, #0x0
+ + 	bne	wait_pll_bypass_\name
+ + 	.endm
+ + 
+ + 	.macro	pll_lock, name, clk_mode_addr, idlest_addr, pll_mode
+ + pll_lock_\name:
+ + 	ldr	r0, \clk_mode_addr
+ + 	ldr	r1, clk_mode_\pll_mode
+ + 	str	r1, [r0]
+ + 	and	r1, r1, #0x7
+ + 	cmp	r1, #0x7
+ + 	bne	pll_mode_restored_\name
+ + 	ldr	r0, \idlest_addr
+ + wait_pll_lock_\name:
+ + 	ldr	r1, [r0]
+ + 	ands	r1, #0x1
+ + 	beq	wait_pll_lock_\name
+ + pll_mode_restored_\name:
+ + 	nop
+ + 	.endm
+ + 
+ + 	.macro	ddr_self_refresh, num
+ + ddr_self_refresh_\num:
+ + 	add	r1, r0, #EMIF4_0_SDRAM_MGMT_CTRL
+ + 	ldr	r2, [r1]
+ + 	orr	r2, r2, #0xa0		@ a reasonable delay for entering SR
+ + 	str	r2, [r1, #0]
+ + 	str	r2, [r1, #4]		@ write to shadow register also
+ + 
+ + 	ldr	r2, ddr_start		@ do a dummy access to DDR
+ + 	ldr	r3, [r2, #0]
+ + 	ldr	r3, [r1, #0]
+ + 	orr	r3, r3, #0x200		@ now set the LP MODE to Self-Refresh
+ + 	str	r3, [r1, #0]
+ + 
+ + 	mov	r1, #0x1000		@ Give some time for system to enter SR
+ + wait_sr_\num:
+ + 	subs	r1, r1, #1
+ + 	bne	wait_sr_\num
+ + 	.endm
+ + 
+ + 	.macro	wait_sdram_config ,num
+ + wait_sdram_config_\num:
+ + 	mov	r0, #0x100
+ + wait_sc_\num:
+ + 	subs	r0, r0 ,#1
+ + 	bne	wait_sc_\num
+ + 	.endm
+ + 
+ + 	mov	r8, r0			@ same arg list passed to us
+ + 
+ + 	/* EMIF config for low power mode */
+ + 	ldr	r0, emif_addr_func
+ + 	blx	r0
+ + 
+ + 	str	r0, emif_addr_virt
+ + 
+ + 	ldr	r0, gpio0_addr_func
+ + 	blx	r0
+ + 
+ + 	str	r0, gpio0_addr_virt
+ + 
+ + 	/* This ensures isb */
+ + 	ldr	r0, dcache_flush
+ + 	blx	r0
+ + 
+ + 	/* Same as v7_flush_icache_all - saving a branch */
+ + 	mov	r0, #0
+ + 	mcr	p15, 0, r0, c7, c5, 0	@ I+BTB cache invalidate
+ + 
+ + 	ldm	r8, {r0-r4}		@ gather values passed
+ + 
+ + 	/* Save the values passed */
+ + 	str	r0, mem_type
+ + 	str	r1, susp_vtp_ctrl_val
+ + 	str	r2, evm_id
+ + 	str	r3, cpu_rev
+ + 	str	r4, suspend_state
+ + 
+ + 	ldr	r0, emif_addr_virt
+ + 
+ + 	/* Save EMIF configuration */
+ + 	ldr	r1, [r0, #EMIF4_0_SDRAM_CONFIG]
+ + 	str	r1, emif_sdcfg_val
+ + 	ldr	r1, [r0, #EMIF4_0_SDRAM_REF_CTRL]
+ + 	str	r1, emif_ref_ctrl_val
+ + 	ldr	r1, [r0, #EMIF4_0_SDRAM_TIM_1]
+ + 	str	r1, emif_timing1_val
+ + 	ldr	r1, [r0, #EMIF4_0_SDRAM_TIM_2]
+ + 	str	r1, emif_timing2_val
+ + 	ldr	r1, [r0, #EMIF4_0_SDRAM_TIM_3]
+ + 	str	r1, emif_timing3_val
+ + 	ldr	r1, [r0, #EMIF4_0_SDRAM_MGMT_CTRL]
+ + 	str	r1, emif_pmcr_val
+ + 	ldr	r1, [r0, #EMIF4_0_SDRAM_MGMT_CTRL_SHADOW]
+ + 	str	r1, emif_pmcr_shdw_val
+ + 	ldr	r1, [r0, #EMIF4_0_ZQ_CONFIG]
+ + 	str	r1, emif_zqcfg_val
+ + 	ldr	r1, [r0, #EMIF4_0_DDR_PHY_CTRL_1]
+ + 	str	r1, emif_rd_lat_val
+ + 
+ + 	/* Ensure that all the writes to DDR leave the A8 */
+ + 	dsb
+ + 	dmb
+ + 	isb
+ + 
+ + 	/* Different sleep sequences for DDR2 and DDR3 */
+ + 	ldr	r6, mem_type
+ + 	cmp	r6, #MEM_TYPE_DDR2
+ + 	beq	ddr2_susp_seq
+ + 
+ + 	/* DDR3 suspend sequence */
+ + 
+ + 	/* For DDR3, hold DDR_RESET high via control module */
+ + 	ldr	r2, virt_ddr_io_ctrl
+ + 	ldr	r1, [r2]
+ + 	mov	r3,#1
+ + 	mov	r3,r3,lsl #31
+ + 	orr	r1,r1,r3		@ set ddr3_rst_def_val
+ + 	str	r1, [r2]
+ + 
+ + 	ddr_self_refresh	1
+ + 
+ + 	/* Weak pull down for macro DATA0 */
+ + 	ldr	r1, virt_ddr_data0_ioctrl
+ + 	ldr	r2, susp_io_pull_data
+ + 	str	r2, [r1]
+ + 
+ + 	/* Weak pull down for macro DATA1 */
+ + 	ldr	r1, virt_ddr_data1_ioctrl
+ + 	ldr	r2, susp_io_pull_data
+ + 	str	r2, [r1]
+ + 
+ + 	/* Weak pull down for macro CMD0 */
+ + 	ldr	r1, virt_ddr_cmd0_ioctrl
+ + 	ldr	r2, susp_io_pull_cmd1
+ + 	str	r2, [r1]
+ + 
+ + 	/* Weak pull down for macro CMD1 */
+ + 	ldr	r1, virt_ddr_cmd1_ioctrl
+ + 	ldr	r2, susp_io_pull_cmd1
+ + 	str	r2, [r1]
+ + 
+ + 	/*
+ + 	 * Weak pull down for macro CMD2
+ + 	 * exception: keep DDR_RESET pullup
+ + 	 */
+ + 	ldr	r1, virt_ddr_cmd2_ioctrl
+ + 	ldr	r2, susp_io_pull_cmd2
+ + 	str	r2, [r1]
+ + 
+ + 	/* mddr mode selection not required for PG2.0 */
+ + 	ldr	r6, cpu_rev
+ + 	cmp	r6, #CPU_REV_2
+ + 	beq	mddr_modesel_skip
+ + 
+ + 	/* Put IO in mDDR (cmos) mode */
+ + 	ldr	r0, virt_ddr_io_ctrl
+ + 	ldr	r1, [r0]
+ + 	mov	r2, #(0x1 << 28)
+ + 	orr	r3,r2,r1
+ + 	str	r3, [r0]
+ + 
+ + mddr_modesel_skip:
+ + 	/* Disable EMIF at this point */
+ + 	ldr	r1, virt_emif_clkctrl
+ + 	ldr	r2, [r1]
+ + 	bic	r2, r2, #(3 << 0)
+ + 	str	r2, [r1]
+ + 
+ + 	ldr	r1, virt_emif_clkctrl
+ + wait_emif_disable3:
+ + 	ldr	r2, [r1]
+ + 	ldr	r3, module_disabled_val
+ + 	cmp	r2, r3
+ + 	bne	wait_emif_disable3
+ + 
+ + 	/* Disable VTP */
+ + 	ldr	r1, virt_ddr_vtp_ctrl
+ + 	ldr	r2, susp_vtp_ctrl_val
+ + 	str	r2, [r1]
+ + 
+ + 	/* Enable SRAM LDO ret mode */
+ + 	ldr	r0, virt_sram_ldo_addr
+ + 	ldr	r1, [r0]
+ + 	orr	r1, #1
+ + 	str	r1, [r0]
+ + 
+ + 	b	put_pll_bypass
+ + 
+ + ddr2_susp_seq:
+ + 	ddr_self_refresh	2
+ + 
+ + 	/* Disable EMIF at this point */
+ + 	ldr	r1, virt_emif_clkctrl
+ + 	ldr	r2, [r1]
+ + 	bic	r2, r2, #(3 << 0)
+ + 	str	r2, [r1]
+ + 
+ + 	ldr	r1, virt_emif_clkctrl
+ + wait_emif_disable:
+ + 	ldr	r2, [r1]
+ + 	ldr	r3, module_disabled_val
+ + 	cmp	r2, r3
+ + 	bne	wait_emif_disable
+ + 
+ + 	/* DDR3 reset override and mDDR mode selection */
+ + 	ldr	r0, virt_ddr_io_ctrl
+ + 	mov	r1, #(0x9 << 28)
+ + 	str	r1, [r0]
+ + 
+ + 	/* Weak pull down for DQ, DM */
+ + 	ldr	r1, virt_ddr_io_pull1
+ + 	ldr	r2, susp_io_pull_data
+ + 	str	r2, [r1]
+ + 
+ + 	ldr	r1, virt_ddr_io_pull2
+ + 	ldr	r2, susp_io_pull_data
+ + 	str	r2, [r1]
+ + 
+ + 	/* Disable VTP */
+ + 	ldr	r1, virt_ddr_vtp_ctrl
+ + 	ldr	r2, susp_vtp_ctrl_val
+ + 	str	r2, [r1]
+ + 
+ + 	/* Enable SRAM LDO ret mode */
+ + 	ldr	r0, virt_sram_ldo_addr
+ + 	ldr	r1, [r0]
+ + 	orr	r1, #1
+ + 	str	r1, [r0]
+ + 
+ + put_pll_bypass:
+ + 	/* Put the PLLs in bypass mode */
+ + 	pll_bypass	core, virt_core_clk_mode, virt_core_idlest, core_val
+ + 	pll_bypass	ddr, virt_ddr_clk_mode, virt_ddr_idlest, ddr_val
+ + 	pll_bypass	disp, virt_disp_clk_mode, virt_disp_idlest, disp_val
+ + 	pll_bypass	per, virt_per_clk_mode, virt_per_idlest, per_val
+ + 	pll_bypass	mpu, virt_mpu_clk_mode, virt_mpu_idlest, mpu_val
+ + 
+ + 	dsb
+ + 	dmb
+ + 	isb
+ + 
+ + 	wfi
+ + 	nop
+ + 	nop
+ + 	nop
+ + 	nop
+ + 	nop
+ + 	nop
+ + 	nop
+ + 	nop
+ + 	nop
+ + 	nop
+ + 	nop
+ + 	nop
+ + 	nop
+ + 
+ + 	/* We come here in case of an abort */
+ + 
+ + 	/* Relock the PLLs */
+ + 	pll_lock	mpu_abt, virt_mpu_clk_mode, virt_mpu_idlest, mpu_val
+ + 	pll_lock	per_abt, virt_per_clk_mode, virt_per_idlest, per_val
+ + 	pll_lock	disp_abt, virt_disp_clk_mode, virt_disp_idlest, disp_val
+ + 	pll_lock	ddr_abt, virt_ddr_clk_mode, virt_ddr_idlest, ddr_val
+ + 	pll_lock	core_abt, virt_core_clk_mode, virt_core_idlest, core_val
+ + 
+ + 	ldr	r6, mem_type
+ + 	cmp	r6, #MEM_TYPE_DDR2
+ + 	beq	ddr2_resume_seq_abt
+ + 
+ + 	/* DDR3 resume path */
+ + 
+ + 	/* Disable SRAM LDO ret mode */
+ + 	ldr	r0, virt_sram_ldo_addr
+ + 	ldr	r1, [r0]
+ + 	bic	r1, #1
+ + 	str	r1, [r0]
+ + 
+ + 	/* Enable EMIF */
+ + 	ldr	r1, virt_emif_clkctrl
+ + 	mov	r2, #0x2
+ + 	str	r2, [r1]
+ + wait_emif_enable3:
+ + 	ldr	r3, [r1]
+ + 	cmp	r2, r3
+ + 	bne	wait_emif_enable3
+ + 
+ + 	/* mddr mode selection not required for PG2.0 */
+ + 	ldr	r6, cpu_rev
+ + 	cmp	r6, #CPU_REV_2
+ + 	beq	config_vtp_abt3
+ + 
+ + 	/* Take out IO of mDDR mode */
+ + 	ldr	r0, virt_ddr_io_ctrl
+ + 	ldr	r1, [r0]
+ + 	bic	r1, r1, #(1 << 28)
+ + 	str	r1, [r0]
+ + 
+ + 	/* Enable VTP */
+ + config_vtp_abt3:
+ + 	ldr	r0, virt_ddr_vtp_ctrl
+ + 	ldr	r1, [r0]
+ + 	mov	r2, #0x0	@ clear the register
+ + 	str	r2, [r0]
+ + 	mov	r2, #0x6	@ write the filter value
+ + 	str	r2, [r0]
+ + 
+ + 	ldr	r1, [r0]
+ + 	ldr	r2, vtp_enable	@ set the enable bit
+ + 	orr	r2, r2, r1
+ + 	str	r2, [r0]
+ + 
+ + 	ldr	r1, [r0]	@ toggle the CLRZ bit
+ + 	bic	r1, #1
+ + 	str	r1, [r0]
+ + 
+ + 	ldr	r1, [r0]
+ + 	orr	r1, #1
+ + 	str	r1, [r0]
+ + 
+ + poll_vtp_ready_abt3:
+ + 	ldr	r1, [r0]	@ poll for VTP ready
+ + 	tst	r1, #(1 << 5)
+ + 	beq	poll_vtp_ready_abt3
+ + 
+ + 	/* Disable the pull for CMD2 */
+ + 	ldr	r1, virt_ddr_cmd2_ioctrl
+ + 	ldr	r2, resume_io_pull_cmd
+ + 	str	r2, [r1]
+ + 	/* Disable the pull for CMD1 */
+ + 	ldr	r1, virt_ddr_cmd1_ioctrl
+ + 	ldr	r2, resume_io_pull_cmd
+ + 	str	r2, [r1]
+ + 	/* Disable the pull for CMD0 */
+ + 	ldr	r1, virt_ddr_cmd0_ioctrl
+ + 	ldr	r2, resume_io_pull_cmd
+ + 	str	r2, [r1]
+ + 	/* Disable the pull for DATA1 */
+ + 	ldr	r1, virt_ddr_data1_ioctrl
+ + 	ldr	r2, resume_io_pull_data
+ + 	str	r2, [r1]
+ + 	/* Disable the pull for DATA0 */
+ + 	ldr	r1, virt_ddr_data0_ioctrl
+ + 	ldr	r2, resume_io_pull_data
+ + 	str	r2, [r1]
+ + 
+ + 	wait_sdram_config	1
+ + 
+ + 	/* Disable EMIF self-refresh */
+ + 	ldr	r0, emif_addr_virt
+ + 	add	r0, r0, #EMIF4_0_SDRAM_MGMT_CTRL
+ + 	ldr	r1, [r0]
+ + 	bic	r1, r1, #(0x7 << 8)
+ + 	str	r1, [r0]
+ + 	str	r1, [r0, #4]
+ + 
+ + 	/* For DDR3, make DDR_RESET low via control module */
+ + 	ldr	r0, virt_ddr_io_ctrl
+ + 	ldr	r1, [r0]
+ + 	bic	r1, r1, #(1 << 31)
+ + 	str	r1, [r0]
+ + 
+ + 	b	return_to_ddr_abt
+ + 
+ + 	/* DDR2 resume path */
+ + ddr2_resume_seq_abt:
+ + 	/* Disable SRAM LDO ret mode */
+ + 	ldr	r0, virt_sram_ldo_addr
+ + 	ldr	r1, [r0]
+ + 	bic	r1, #1
+ + 	str	r1, [r0]
+ + 
+ + 	/* Restore the pull for DQ, DM */
+ + 	ldr	r1, virt_ddr_io_pull1
+ + 	ldr	r2, resume_io_pull_data
+ + 	str	r2, [r1]
+ + 
+ + 	ldr	r1, virt_ddr_io_pull2
+ + 	ldr	r2, resume_io_pull_data
+ + 	str	r2, [r1]
+ + 
+ + 	/* Enable EMIF */
+ + 	ldr	r1, virt_emif_clkctrl
+ + 	mov	r2, #0x2
+ + 	str	r2, [r1]
+ + wait_emif_enable:
+ + 	ldr	r3, [r1]
+ + 	cmp	r2, r3
+ + 	bne	wait_emif_enable
+ + 
+ + 	/* Enable VTP */
+ + config_vtp_abt:
+ + 	ldr	r0, virt_ddr_vtp_ctrl
+ + 	ldr	r1, [r0]
+ + 	mov	r2, #0x0	@ clear the register
+ + 	str	r2, [r0]
+ + 	mov	r2, #0x6	@ write the filter value
+ + 	str	r2, [r0]
+ + 
+ + 	ldr	r1, [r0]
+ + 	ldr	r2, vtp_enable	@ set the enable bit
+ + 	orr	r2, r2, r1
+ + 	str	r2, [r0]
+ + 
+ + 	ldr	r1, [r0]	@ toggle the CLRZ bit
+ + 	bic	r1, #1
+ + 	str	r1, [r0]
+ + 
+ + 	ldr	r1, [r0]
+ + 	orr	r1, #1
+ + 	str	r1, [r0]
+ + 
+ + poll_vtp_ready_abt:
+ + 	ldr	r1, [r0]	@ poll for VTP ready
+ + 	tst	r1, #(1 << 5)
+ + 	beq	poll_vtp_ready_abt
+ + 
+ + 	/* DDR3 reset override and mDDR mode clear */
+ + 	ldr	r0, virt_ddr_io_ctrl
+ + 	mov	r1, #0
+ + 	str	r1, [r0]
+ + 
+ + emif_self_refresh_dis:
+ + 	/* Disable EMIF self-refresh */
+ + 	ldr	r0, emif_addr_virt
+ + 	add	r0, r0, #EMIF4_0_SDRAM_MGMT_CTRL
+ + 	ldr	r1, [r0]
+ + 	bic	r1, r1, #(0x7 << 8)
+ + 	str	r1, [r0]
+ + 	str	r1, [r0, #4]
+ + 
+ + /*
+ +  * A write to SDRAM CONFIG register triggers
+ +  * an init sequence and hence it must be done
+ +  * at the end
+ +  */
+ + 	ldr r0,	emif_addr_virt
+ + 	add r0,	r0, #EMIF4_0_SDRAM_CONFIG
+ + 	ldr r4,	emif_sdcfg_val
+ + 	str r4,	[r0]
+ + 
+ + 	mov r0,	#0x2000
+ + wait_loop4:
+ + 	subs	r0, r0, #1
+ + 	bne	wait_loop4
+ + 
+ + return_to_ddr_abt:
+ + 	mov	r0, #7
+ + 	ldmfd	sp!, {r4 - r11, pc}	@ restore regs and return
+ + 
+ + ENTRY(am33xx_resume_offset)
+ + 	.word . - am33xx_do_wfi
+ + 
+ + ENTRY(am33xx_resume_from_deep_sleep)
+ + 	/* Take the PLLs out of LP_BYPASS */
+ + 	pll_lock	mpu, phys_mpu_clk_mode, phys_mpu_idlest, mpu_val
+ + 	pll_lock	per, phys_per_clk_mode, phys_per_idlest, per_val
+ + 	pll_lock	disp, phys_disp_clk_mode, phys_disp_idlest, disp_val
+ + 	pll_lock	ddr, phys_ddr_clk_mode, phys_ddr_idlest, ddr_val
+ + 	pll_lock	core, phys_core_clk_mode, phys_core_idlest, core_val
+ + 
+ + 	ldr	r6, mem_type
+ + 	cmp	r6, #MEM_TYPE_DDR2
+ + 	beq	ddr2_resume_seq
+ + 
+ + 	/* DDR3 resume path */
+ + 
+ + 	/* Disable SRAM LDO ret mode */
+ + 	ldr	r0, phys_sram_ldo_addr
+ + 	ldr	r1, [r0]
+ + 	bic	r1, #1
+ + 	str	r1, [r0]
+ + 
+ + 	/* TODO: Put EMIF enable here */
+ + 
+ + 	/* mddr mode selection not required for PG2.0 */
+ + 	ldr	r6, cpu_rev
+ + 	cmp	r6, #CPU_REV_2
+ + 	beq	config_vtp3
+ + 
+ + 	/* Take out IO of mDDR mode */
+ + 	ldr	r0, phys_ddr_io_ctrl
+ + 	ldr	r1, [r0]
+ + 	bic	r1, r1, #(1 << 28)
+ + 	str	r1, [r0]
+ + 
+ + config_vtp3:
+ + 	ldr	r0, phys_ddr_vtp_ctrl
+ + 	ldr	r1, [r0]
+ + 	mov	r2, #0x0	@ clear the register
+ + 	str	r2, [r0]
+ + 	mov	r2, #0x6	@ write the filter value
+ + 	str	r2, [r0]
+ + 
+ + 	ldr	r1, [r0]
+ + 	ldr	r2, vtp_enable	@ set the enable bit
+ + 	orr	r2, r2, r1
+ + 	str	r2, [r0]
+ + 
+ + 	ldr	r1, [r0]	@ toggle the CLRZ bit
+ + 	bic	r1, #1
+ + 	str	r1, [r0]
+ + 
+ + 	ldr	r1, [r0]
+ + 	orr	r1, #1
+ + 	str	r1, [r0]
+ + poll_vtp_ready3:
+ + 	ldr	r1, [r0]	@ poll for VTP ready
+ + 	tst	r1, #(1 << 5)
+ + 	beq	poll_vtp_ready3
+ + 
+ + 	/* Disable the pull for CMD2 */
+ + 	ldr	r1, phys_ddr_cmd2_ioctrl
+ + 	ldr	r2, resume_io_pull_cmd
+ + 	str	r2, [r1]
+ + 	/* Disable the pull for CMD1 */
+ + 	ldr	r1, phys_ddr_cmd1_ioctrl
+ + 	ldr	r2, resume_io_pull_cmd
+ + 	str	r2, [r1]
+ + 	/* Disable the pull for CMD0 */
+ + 	ldr	r1, phys_ddr_cmd0_ioctrl
+ + 	ldr	r2, resume_io_pull_cmd
+ + 	str	r2, [r1]
+ + 	/* Disable the pull for DATA1 */
+ + 	ldr	r1, phys_ddr_data1_ioctrl
+ + 	ldr	r2, resume_io_pull_data
+ + 	str	r2, [r1]
+ + 	/* Disable the pull for DATA0 */
+ + 	ldr	r1, phys_ddr_data0_ioctrl
+ + 	ldr	r2, resume_io_pull_data
+ + 	str	r2, [r1]
+ + 
+ + 	wait_sdram_config	2
+ + 
+ + 	b	config_emif_timings
+ + 
+ + 	/* DDR2 resume path */
+ + ddr2_resume_seq:
+ + 	/* Disable SRAM LDO ret mode */
+ + 	ldr	r0, phys_sram_ldo_addr
+ + 	ldr	r1, [r0]
+ + 	bic	r1, #1
+ + 	str	r1, [r0]
+ + 
+ + 	/* Restore the pull for DQ, DM */
+ + 	ldr	r1, phys_ddr_io_pull1
+ + 	ldr	r2, resume_io_pull_data
+ + 	str	r2, [r1]
+ + 
+ + 	ldr	r1, phys_ddr_io_pull2
+ + 	ldr	r2, resume_io_pull_data
+ + 	str	r2, [r1]
+ + 
+ + config_vtp:
+ + 	ldr	r0, phys_ddr_vtp_ctrl
+ + 	ldr	r1, [r0]
+ + 	mov	r2, #0x0	@ clear the register
+ + 	str	r2, [r0]
+ + 	mov	r2, #0x6	@ write the filter value
+ + 	str	r2, [r0]
+ + 
+ + 	ldr	r1, [r0]
+ + 	ldr	r2, vtp_enable	@ set the enable bit
+ + 	orr	r2, r2, r1
+ + 	str	r2, [r0]
+ + 
+ + 	ldr	r1, [r0]	@ toggle the CLRZ bit
+ + 	bic	r1, #1
+ + 	str	r1, [r0]
+ + 
+ + 	ldr	r1, [r0]
+ + 	orr	r1, #1
+ + 	str	r1, [r0]
+ + 
+ + poll_vtp_ready:
+ + 	ldr	r1, [r0]	@ poll for VTP ready
+ + 	tst	r1, #(1 << 5)
+ + 	beq	poll_vtp_ready
+ + 
+ + 	/* DDR3 reset override and mDDR mode clear */
+ + 	ldr	r0, phys_ddr_io_ctrl
+ + 	mov	r1, #0
+ + 	str	r1, [r0]
+ + 
+ + config_emif_timings:
+ + 	ldr	r3, emif_phys_addr
+ + 	ldr	r4, emif_rd_lat_val
+ + rd_lat:
+ + 	str	r4, [r3, #EMIF4_0_DDR_PHY_CTRL_1]
+ + 	str	r4, [r3, #EMIF4_0_DDR_PHY_CTRL_1_SHADOW]
+ + timing1:
+ + 	ldr	r4, emif_timing1_val
+ + 	str	r4, [r3, #EMIF4_0_SDRAM_TIM_1]
+ + 	str	r4, [r3, #EMIF4_0_SDRAM_TIM_1_SHADOW]
+ + timing2:
+ + 	ldr	r4, emif_timing2_val
+ + 	str	r4, [r3, #EMIF4_0_SDRAM_TIM_2]
+ + 	str	r4, [r3, #EMIF4_0_SDRAM_TIM_2_SHADOW]
+ + timing3:
+ + 	ldr	r4, emif_timing3_val
+ + 	str	r4, [r3, #EMIF4_0_SDRAM_TIM_3]
+ + 	str	r4, [r3, #EMIF4_0_SDRAM_TIM_3_SHADOW]
+ + sdram_ref_ctrl:
+ + 	ldr	r4, emif_ref_ctrl_val
+ + 	str	r4, [r3, #EMIF4_0_SDRAM_REF_CTRL]
+ + 	str	r4, [r3, #EMIF4_0_SDRAM_REF_CTRL_SHADOW]
+ + pmcr:
+ + 	ldr	r4, emif_pmcr_val
+ + 	str	r4, [r3, #EMIF4_0_SDRAM_MGMT_CTRL]
+ + pmcr_shdw:
+ + 	ldr	r4, emif_pmcr_shdw_val
+ + 	str	r4, [r3, #EMIF4_0_SDRAM_MGMT_CTRL_SHADOW]
+ + 
+ + 	/*
+ + 	 * Output impedence calib needed only for DDR3
+ + 	 * but since the initial state of this will be
+ + 	 * disabled for DDR2 no harm in restoring the
+ + 	 * old configuration
+ + 	 */
+ + zqcfg:
+ + 	ldr	r4, emif_zqcfg_val
+ + 	str	r4, [r3, #EMIF4_0_ZQ_CONFIG]
+ + 
+ + 	/* Write to SDRAM_CONFIG only for DDR2 */
+ + 	ldr	r6, mem_type
+ + 	cmp	r6, #MEM_TYPE_DDR2
+ + 	beq	ddr2_sdcfg
+ + 
+ + 	/* For DDR3, make DDR_RESET low via control module */
+ + 	ldr	r0, phys_ddr_io_ctrl
+ + 	ldr	r1, [r0]
+ + 	bic	r1, r1, #(1 << 31)
+ + 	str	r1, [r0]
+ + 
+ + 	b	return_to_ddr
+ + 
+ + 	/*
+ + 	 * A write to SDRAM CONFIG register triggers
+ + 	 * an init sequence and hence it must be done
+ + 	 * at the end for DDR2
+ + 	 */
+ + ddr2_sdcfg:
+ + 	ldr	r4, emif_sdcfg_val
+ + 	str	r4, [r3, #EMIF4_0_SDRAM_CONFIG]
+ + 
+ + return_to_ddr:
+ + 	/* Back from la-la-land. Kill some time for sanity to settle in */
+ + 	mov	r0, #0x1000
+ + wait_loop2:
+ + 	subs	r0, r0, #1
+ + 	bne	wait_loop2
+ + 
+ + 	/* We are back. Branch to the common CPU resume routine */
+ + ENTRY(am33xx_resume_vector)
+ + 	ldr	pc, resume_addr
+ + 
+ + /*
+ +  * Local variables
+ +  */
+ + 
+ + dcache_flush:
+ + 	.word   v7_flush_dcache_all
+ + resume_addr:
+ + 	.word	cpu_resume - PAGE_OFFSET + 0x80000000
+ + 
+ + emif_addr_func:
+ + 	.word	am33xx_get_ram_base
+ + emif_phys_addr:
+ + 	.word	AM33XX_EMIF0_BASE
+ + 
+ + gpio0_addr_func:
+ + 	.word	am33xx_get_gpio0_base
+ + gpio0_phys_addr:
+ + 	.word	AM33XX_GPIO0_BASE
+ + 
+ + ddr_start:
+ + 	.word	PAGE_OFFSET
+ + 
+ + virt_mpu_idlest:
+ + 	.word	AM33XX_CM_IDLEST_DPLL_MPU
+ + virt_mpu_clk_mode:
+ + 	.word	AM33XX_CM_CLKMODE_DPLL_MPU
+ + 
+ + phys_pll_mod:
+ + 	.word	AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD
+ + phys_mpu_clk_mode:
+ + 	.word	AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + AM33XX_CM_CLKMODE_DPLL_MPU_OFFSET
+ + phys_mpu_idlest:
+ + 	.word	AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + AM33XX_CM_IDLEST_DPLL_MPU_OFFSET
+ + 
+ + virt_core_idlest:
+ + 	.word	AM33XX_CM_IDLEST_DPLL_CORE
+ + virt_core_clk_mode:
+ + 	.word	AM33XX_CM_CLKMODE_DPLL_CORE
+ + phys_core_clk_mode:
+ + 	.word	AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + AM33XX_CM_CLKMODE_DPLL_CORE_OFFSET
+ + phys_core_idlest:
+ + 	.word	AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + AM33XX_CM_IDLEST_DPLL_CORE_OFFSET
+ + 
+ + virt_per_idlest:
+ + 	.word	AM33XX_CM_IDLEST_DPLL_PER
+ + virt_per_clk_mode:
+ + 	.word	AM33XX_CM_CLKMODE_DPLL_PER
+ + phys_per_clk_mode:
+ + 	.word	AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + AM33XX_CM_CLKMODE_DPLL_PER_OFFSET
+ + phys_per_idlest:
+ + 	.word	AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + AM33XX_CM_IDLEST_DPLL_PER_OFFSET
+ + 
+ + virt_disp_idlest:
+ + 	.word	AM33XX_CM_IDLEST_DPLL_DISP
+ + virt_disp_clk_mode:
+ + 	.word	AM33XX_CM_CLKMODE_DPLL_DISP
+ + phys_disp_clk_mode:
+ + 	.word	AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + AM33XX_CM_CLKMODE_DPLL_DISP_OFFSET
+ + phys_disp_idlest:
+ + 	.word	AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + AM33XX_CM_IDLEST_DPLL_DISP_OFFSET
+ + 
+ + virt_ddr_idlest:
+ + 	.word	AM33XX_CM_IDLEST_DPLL_DDR
+ + virt_ddr_clk_mode:
+ + 	.word	AM33XX_CM_CLKMODE_DPLL_DDR
+ + phys_ddr_clk_mode:
+ + 	.word	AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + AM33XX_CM_CLKMODE_DPLL_DDR_OFFSET
+ + phys_ddr_idlest:
+ + 	.word	AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + AM33XX_CM_IDLEST_DPLL_DDR_OFFSET
+ + 
+ + virt_sram_ldo_addr:
+ + 	.word	AM33XX_PRM_LDO_SRAM_MPU_CTRL
+ + phys_sram_ldo_addr:
+ + 	.word	AM33XX_PRM_BASE + AM33XX_PRM_DEVICE_MOD + AM33XX_PRM_LDO_SRAM_MPU_CTRL_OFFSET
+ + 
+ + virt_gpio0_clkctrl:
+ + 	.word	AM33XX_CM_WKUP_GPIO0_CLKCTRL
+ + phys_gpio0_clkctrl:
+ + 	.word	AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET
+ + 
+ + virt_emif_clkctrl:
+ + 	.word	AM33XX_CM_PER_EMIF_CLKCTRL
+ + phys_emif_clkctrl:
+ + 	.word	AM33XX_CM_BASE + AM33XX_CM_PER_MOD + AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET
+ + module_disabled_val:
+ + 	.word	0x30000
+ + 
+ + /* DDR related stuff */
+ + virt_ddr_io_ctrl:
+ + 	.word	AM33XX_CTRL_REGADDR(0x0E04)
+ + phys_ddr_io_ctrl:
+ + 	.word	DDR_IO_CTRL
+ + virt_ddr_vtp_ctrl:
+ + 	.word	AM33XX_CTRL_REGADDR(0x0E0C)
+ + phys_ddr_vtp_ctrl:
+ + 	.word	VTP0_CTRL_REG
+ + virt_ddr_cmd0_ioctrl:
+ + 	.word	AM33XX_CTRL_REGADDR(0x1404)
+ + phys_ddr_cmd0_ioctrl:
+ + 	.word	DDR_CMD0_IOCTRL
+ + virt_ddr_cmd1_ioctrl:
+ + 	.word	AM33XX_CTRL_REGADDR(0x1408)
+ + phys_ddr_cmd1_ioctrl:
+ + 	.word	DDR_CMD1_IOCTRL
+ + virt_ddr_cmd2_ioctrl:
+ + 	.word	AM33XX_CTRL_REGADDR(0x140C)
+ + phys_ddr_cmd2_ioctrl:
+ + 	.word	DDR_CMD2_IOCTRL
+ + virt_ddr_data0_ioctrl:
+ + 	.word	AM33XX_CTRL_REGADDR(0x1440)
+ + phys_ddr_data0_ioctrl:
+ + 	.word	DDR_DATA0_IOCTRL
+ + virt_ddr_data1_ioctrl:
+ + 	.word	AM33XX_CTRL_REGADDR(0x1444)
+ + phys_ddr_data1_ioctrl:
+ + 	.word	DDR_DATA1_IOCTRL
+ + vtp_enable:
+ + 	.word	VTP_CTRL_ENABLE
+ + 
+ + virt_ddr_io_pull1:
+ + 	.word	AM33XX_CTRL_REGADDR(0x1440)
+ + phys_ddr_io_pull1:
+ + 	.word	AM33XX_CTRL_BASE + (0x1440)
+ + virt_ddr_io_pull2:
+ + 	.word	AM33XX_CTRL_REGADDR(0x1444)
+ + phys_ddr_io_pull2:
+ + 	.word	AM33XX_CTRL_BASE + (0x1444)
+ + virt_ddr_io_pull3:
+ + 	.word	AM33XX_CTRL_REGADDR(0x1448)
+ + phys_ddr_io_pull3:
+ + 	.word	AM33XX_CTRL_BASE + (0x1448)
+ + 
+ + susp_io_pull_data:
+ + 	.word	0x3FF00003
+ + susp_io_pull_cmd1:
+ + 	.word   0xFFE0018B
+ + susp_io_pull_cmd2:
+ + 	.word   0xFFA0098B
+ + 
+ + resume_io_pull_data:
+ + 	.word	0x18B
+ + resume_io_pull_cmd:
+ + 	.word	0x18B
+ + 
+ + susp_vtp_ctrl_val:
+ + 	.word	0xDEADBEEF
+ + mem_type:
+ + 	.word	0xDEADBEEF
+ + evm_id:
+ + 	.word	0xDEADBEEF
+ + cpu_rev:
+ + 	.word	0xDEADBEEF
+ + suspend_state:
+ + 	.word	0xDEADBEEF
+ + emif_addr_virt:
+ + 	.word	0xDEADBEEF
+ + gpio0_addr_virt:
+ + 	.word	0xDEADBEEF
+ + emif_rd_lat_val:
+ + 	.word	0xDEADBEEF
+ + emif_timing1_val:
+ + 	.word	0xDEADBEEF
+ + emif_timing2_val:
+ + 	.word	0xDEADBEEF
+ + emif_timing3_val:
+ + 	.word	0xDEADBEEF
+ + emif_sdcfg_val:
+ + 	.word	0xDEADBEEF
+ + emif_ref_ctrl_val:
+ + 	.word	0xDEADBEEF
+ + emif_zqcfg_val:
+ + 	.word	0xDEADBEEF
+ + emif_pmcr_val:
+ + 	.word	0xDEADBEEF
+ + emif_pmcr_shdw_val:
+ + 	.word	0xDEADBEEF
+ + 
+ + /* PLL CLKMODE before suspend */
+ + clk_mode_mpu_val:
+ + 	.word	0xDEADBEEF
+ + clk_mode_per_val:
+ + 	.word	0xDEADBEEF
+ + clk_mode_disp_val:
+ + 	.word	0xDEADBEEF
+ + clk_mode_ddr_val:
+ + 	.word	0xDEADBEEF
+ + clk_mode_core_val:
+ + 	.word	0xDEADBEEF
+ + 
+ + ENTRY(am33xx_do_wfi_sz)
+ + 	.word	. - am33xx_do_wfi
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/smartreflex.h linux-3.2.1/arch/arm/mach-ckb_3352/smartreflex.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/smartreflex.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/smartreflex.h	2014-11-25 13:19:15.079528500 +0900
+ ***************
+ *** 0 ****
+ --- 1,246 ----
+ + /*
+ +  * OMAP Smartreflex Defines and Routines
+ +  *
+ +  * Author: Thara Gopinath	<thara@ti.com>
+ +  *
+ +  * Copyright (C) 2010 Texas Instruments, Inc.
+ +  * Thara Gopinath <thara@ti.com>
+ +  *
+ +  * Copyright (C) 2008 Nokia Corporation
+ +  * Kalle Jokiniemi
+ +  *
+ +  * Copyright (C) 2007 Texas Instruments, Inc.
+ +  * Lesly A M <x0080970@ti.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #ifndef __ASM_ARM_OMAP_SMARTREFLEX_H
+ + #define __ASM_ARM_OMAP_SMARTREFLEX_H
+ + 
+ + #include <linux/platform_device.h>
+ + 
+ + #include "voltage.h"
+ + 
+ + /*
+ +  * Different Smartreflex IPs version. The v1 is the 65nm version used in
+ +  * OMAP3430. The v2 is the update for the 45nm version of the IP
+ +  * used in OMAP3630 and OMAP4430
+ +  */
+ + #define SR_TYPE_V1	1
+ + #define SR_TYPE_V2	2
+ + 
+ + /* SMART REFLEX REG ADDRESS OFFSET */
+ + #define SRCONFIG		0x00
+ + #define SRSTATUS		0x04
+ + #define SENVAL			0x08
+ + #define SENMIN			0x0C
+ + #define SENMAX			0x10
+ + #define SENAVG			0x14
+ + #define AVGWEIGHT		0x18
+ + #define NVALUERECIPROCAL	0x1c
+ + #define SENERROR_V1		0x20
+ + #define ERRCONFIG_V1		0x24
+ + #define IRQ_EOI			0x20
+ + #define IRQSTATUS_RAW		0x24
+ + #define IRQSTATUS		0x28
+ + #define IRQENABLE_SET		0x2C
+ + #define IRQENABLE_CLR		0x30
+ + #define SENERROR_V2		0x34
+ + #define ERRCONFIG_V2		0x38
+ + 
+ + /* Bit/Shift Positions */
+ + 
+ + /* SRCONFIG */
+ + #define SRCONFIG_ACCUMDATA_SHIFT	22
+ + #define SRCONFIG_SRCLKLENGTH_SHIFT	12
+ + #define SRCONFIG_SENNENABLE_V1_SHIFT	5
+ + #define SRCONFIG_SENPENABLE_V1_SHIFT	3
+ + #define SRCONFIG_SENNENABLE_V2_SHIFT	1
+ + #define SRCONFIG_SENPENABLE_V2_SHIFT	0
+ + #define SRCONFIG_CLKCTRL_SHIFT		0
+ + 
+ + #define SRCONFIG_ACCUMDATA_MASK		(0x3ff << 22)
+ + 
+ + #define SRCONFIG_SRENABLE		BIT(11)
+ + #define SRCONFIG_SENENABLE		BIT(10)
+ + #define SRCONFIG_ERRGEN_EN		BIT(9)
+ + #define SRCONFIG_MINMAXAVG_EN		BIT(8)
+ + #define SRCONFIG_DELAYCTRL		BIT(2)
+ + 
+ + /* AVGWEIGHT */
+ + #define AVGWEIGHT_SENPAVGWEIGHT_SHIFT	2
+ + #define AVGWEIGHT_SENNAVGWEIGHT_SHIFT	0
+ + 
+ + /* NVALUERECIPROCAL */
+ + #define NVALUERECIPROCAL_SENPGAIN_SHIFT	20
+ + #define NVALUERECIPROCAL_SENNGAIN_SHIFT	16
+ + #define NVALUERECIPROCAL_RNSENP_SHIFT	8
+ + #define NVALUERECIPROCAL_RNSENN_SHIFT	0
+ + 
+ + /* ERRCONFIG */
+ + #define ERRCONFIG_ERRWEIGHT_SHIFT	16
+ + #define ERRCONFIG_ERRMAXLIMIT_SHIFT	8
+ + #define ERRCONFIG_ERRMINLIMIT_SHIFT	0
+ + 
+ + #define SR_ERRWEIGHT_MASK		(0x07 << 16)
+ + #define SR_ERRMAXLIMIT_MASK		(0xff << 8)
+ + #define SR_ERRMINLIMIT_MASK		(0xff << 0)
+ + 
+ + #define ERRCONFIG_VPBOUNDINTEN_V1	BIT(31)
+ + #define ERRCONFIG_VPBOUNDINTST_V1	BIT(30)
+ + #define	ERRCONFIG_MCUACCUMINTEN		BIT(29)
+ + #define ERRCONFIG_MCUACCUMINTST		BIT(28)
+ + #define	ERRCONFIG_MCUVALIDINTEN		BIT(27)
+ + #define ERRCONFIG_MCUVALIDINTST		BIT(26)
+ + #define ERRCONFIG_MCUBOUNDINTEN		BIT(25)
+ + #define	ERRCONFIG_MCUBOUNDINTST		BIT(24)
+ + #define	ERRCONFIG_MCUDISACKINTEN	BIT(23)
+ + #define ERRCONFIG_VPBOUNDINTST_V2	BIT(23)
+ + #define ERRCONFIG_MCUDISACKINTST	BIT(22)
+ + #define ERRCONFIG_VPBOUNDINTEN_V2	BIT(22)
+ + 
+ + #define ERRCONFIG_STATUS_V1_MASK	(ERRCONFIG_VPBOUNDINTST_V1 | \
+ + 					ERRCONFIG_MCUACCUMINTST | \
+ + 					ERRCONFIG_MCUVALIDINTST | \
+ + 					ERRCONFIG_MCUBOUNDINTST | \
+ + 					ERRCONFIG_MCUDISACKINTST)
+ + /* IRQSTATUS */
+ + #define IRQSTATUS_MCUACCUMINT		BIT(3)
+ + #define IRQSTATUS_MCVALIDINT		BIT(2)
+ + #define IRQSTATUS_MCBOUNDSINT		BIT(1)
+ + #define IRQSTATUS_MCUDISABLEACKINT	BIT(0)
+ + 
+ + /* IRQENABLE_SET and IRQENABLE_CLEAR */
+ + #define IRQENABLE_MCUACCUMINT		BIT(3)
+ + #define IRQENABLE_MCUVALIDINT		BIT(2)
+ + #define IRQENABLE_MCUBOUNDSINT		BIT(1)
+ + #define IRQENABLE_MCUDISABLEACKINT	BIT(0)
+ + 
+ + /* Common Bit values */
+ + 
+ + #define SRCLKLENGTH_12MHZ_SYSCLK	0x3c
+ + #define SRCLKLENGTH_13MHZ_SYSCLK	0x41
+ + #define SRCLKLENGTH_19MHZ_SYSCLK	0x60
+ + #define SRCLKLENGTH_26MHZ_SYSCLK	0x82
+ + #define SRCLKLENGTH_38MHZ_SYSCLK	0xC0
+ + 
+ + /*
+ +  * 3430 specific values. Maybe these should be passed from board file or
+ +  * pmic structures.
+ +  */
+ + #define OMAP3430_SR_ACCUMDATA		0x1f4
+ + 
+ + #define OMAP3430_SR1_SENPAVGWEIGHT	0x03
+ + #define OMAP3430_SR1_SENNAVGWEIGHT	0x03
+ + 
+ + #define OMAP3430_SR2_SENPAVGWEIGHT	0x01
+ + #define OMAP3430_SR2_SENNAVGWEIGHT	0x01
+ + 
+ + #define OMAP3430_SR_ERRWEIGHT		0x04
+ + #define OMAP3430_SR_ERRMAXLIMIT		0x02
+ + 
+ + /**
+ +  * struct omap_sr_pmic_data - Strucutre to be populated by pmic code to pass
+ +  *				pmic specific info to smartreflex driver
+ +  *
+ +  * @sr_pmic_init:	API to initialize smartreflex on the PMIC side.
+ +  */
+ + struct omap_sr_pmic_data {
+ + 	void (*sr_pmic_init) (void);
+ + };
+ + 
+ + #ifdef CONFIG_OMAP_SMARTREFLEX
+ + /*
+ +  * The smart reflex driver supports CLASS1 CLASS2 and CLASS3 SR.
+ +  * The smartreflex class driver should pass the class type.
+ +  * Should be used to populate the class_type field of the
+ +  * omap_smartreflex_class_data structure.
+ +  */
+ + #define SR_CLASS1	0x1
+ + #define SR_CLASS2	0x2
+ + #define SR_CLASS3	0x3
+ + 
+ + /**
+ +  * struct omap_sr_class_data - Smartreflex class driver info
+ +  *
+ +  * @enable:		API to enable a particular class smaartreflex.
+ +  * @disable:		API to disable a particular class smartreflex.
+ +  * @configure:		API to configure a particular class smartreflex.
+ +  * @notify:		API to notify the class driver about an event in SR.
+ +  *			Not needed for class3.
+ +  * @notify_flags:	specify the events to be notified to the class driver
+ +  * @class_type:		specify which smartreflex class.
+ +  *			Can be used by the SR driver to take any class
+ +  *			based decisions.
+ +  */
+ + struct omap_sr_class_data {
+ + 	int (*enable)(struct voltagedomain *voltdm);
+ + 	int (*disable)(struct voltagedomain *voltdm, int is_volt_reset);
+ + 	int (*configure)(struct voltagedomain *voltdm);
+ + 	int (*notify)(struct voltagedomain *voltdm, u32 status);
+ + 	u8 notify_flags;
+ + 	u8 class_type;
+ + };
+ + 
+ + /**
+ +  * struct omap_sr_nvalue_table	- Smartreflex n-target value info
+ +  *
+ +  * @efuse_offs:	The offset of the efuse where n-target values are stored.
+ +  * @nvalue:	The n-target value.
+ +  */
+ + struct omap_sr_nvalue_table {
+ + 	u32 efuse_offs;
+ + 	u32 nvalue;
+ + };
+ + 
+ + /**
+ +  * struct omap_sr_data - Smartreflex platform data.
+ +  *
+ +  * @ip_type:		Smartreflex IP type.
+ +  * @senp_mod:		SENPENABLE value for the sr
+ +  * @senn_mod:		SENNENABLE value for sr
+ +  * @nvalue_count:	Number of distinct nvalues in the nvalue table
+ +  * @enable_on_init:	whether this sr module needs to enabled at
+ +  *			boot up or not.
+ +  * @nvalue_table:	table containing the  efuse offsets and nvalues
+ +  *			corresponding to them.
+ +  * @voltdm:		Pointer to the voltage domain associated with the SR
+ +  */
+ + struct omap_sr_data {
+ + 	int				ip_type;
+ + 	u32				senp_mod;
+ + 	u32				senn_mod;
+ + 	int				nvalue_count;
+ + 	bool				enable_on_init;
+ + 	struct omap_sr_nvalue_table	*nvalue_table;
+ + 	struct voltagedomain		*voltdm;
+ + };
+ + 
+ + /* Smartreflex module enable/disable interface */
+ + void omap_sr_enable(struct voltagedomain *voltdm);
+ + void omap_sr_disable(struct voltagedomain *voltdm);
+ + void omap_sr_disable_reset_volt(struct voltagedomain *voltdm);
+ + 
+ + /* API to register the pmic specific data with the smartreflex driver. */
+ + void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data);
+ + 
+ + /* Smartreflex driver hooks to be called from Smartreflex class driver */
+ + int sr_enable(struct voltagedomain *voltdm, unsigned long volt);
+ + void sr_disable(struct voltagedomain *voltdm);
+ + int sr_configure_errgen(struct voltagedomain *voltdm);
+ + int sr_configure_minmax(struct voltagedomain *voltdm);
+ + 
+ + /* API to register the smartreflex class driver with the smartreflex driver */
+ + int sr_register_class(struct omap_sr_class_data *class_data);
+ + #else
+ + static inline void omap_sr_enable(struct voltagedomain *voltdm) {}
+ + static inline void omap_sr_disable(struct voltagedomain *voltdm) {}
+ + static inline void omap_sr_disable_reset_volt(
+ + 		struct voltagedomain *voltdm) {}
+ + static inline void omap_sr_register_pmic(
+ + 		struct omap_sr_pmic_data *pmic_data) {}
+ + #endif
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/sram34xx.S linux-3.2.1/arch/arm/mach-ckb_3352/sram34xx.S
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/sram34xx.S	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/sram34xx.S	2014-11-25 13:19:15.079528500 +0900
+ ***************
+ *** 0 ****
+ --- 1,346 ----
+ + /*
+ +  * linux/arch/arm/mach-omap3/sram.S
+ +  *
+ +  * Omap3 specific functions that need to be run in internal SRAM
+ +  *
+ +  * Copyright (C) 2004, 2007, 2008 Texas Instruments, Inc.
+ +  * Copyright (C) 2008 Nokia Corporation
+ +  *
+ +  * Rajendra Nayak <rnayak@ti.com>
+ +  * Richard Woodruff <r-woodruff2@ti.com>
+ +  * Paul Walmsley
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation; either version 2 of
+ +  * the License, or (at your option) any later version.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ +  * MA 02111-1307 USA
+ +  */
+ + #include <linux/linkage.h>
+ + #include <asm/assembler.h>
+ + #include <mach/hardware.h>
+ + 
+ + #include <mach/io.h>
+ + 
+ + #include "sdrc.h"
+ + #include "cm2xxx_3xxx.h"
+ + 
+ + /*
+ +  * This file needs be built unconditionally as ARM to interoperate correctly
+ +  * with non-Thumb-2-capable firmware.
+ +  */
+ + 	.arm
+ + 
+ + 	.text
+ + 
+ + /* r1 parameters */
+ + #define SDRC_NO_UNLOCK_DLL		0x0
+ + #define SDRC_UNLOCK_DLL			0x1
+ + 
+ + /* SDRC_DLLA_CTRL bit settings */
+ + #define FIXEDDELAY_SHIFT		24
+ + #define FIXEDDELAY_MASK			(0xff << FIXEDDELAY_SHIFT)
+ + #define DLLIDLE_MASK			0x4
+ + 
+ + /*
+ +  * SDRC_DLLA_CTRL default values: TI hardware team indicates that
+ +  * FIXEDDELAY should be initialized to 0xf.  This apparently was
+ +  * empirically determined during process testing, so no derivation
+ +  * was provided.
+ +  */
+ + #define FIXEDDELAY_DEFAULT		(0x0f << FIXEDDELAY_SHIFT)
+ + 
+ + /* SDRC_DLLA_STATUS bit settings */
+ + #define LOCKSTATUS_MASK			0x4
+ + 
+ + /* SDRC_POWER bit settings */
+ + #define SRFRONIDLEREQ_MASK		0x40
+ + 
+ + /* CM_IDLEST1_CORE bit settings */
+ + #define ST_SDRC_MASK			0x2
+ + 
+ + /* CM_ICLKEN1_CORE bit settings */
+ + #define EN_SDRC_MASK			0x2
+ + 
+ + /* CM_CLKSEL1_PLL bit settings */
+ + #define CORE_DPLL_CLKOUT_DIV_SHIFT	0x1b
+ + 
+ + /*
+ +  * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
+ +  *
+ +  * Params passed in registers:
+ +  *  r0 = new M2 divider setting (only 1 and 2 supported right now)
+ +  *  r1 = unlock SDRC DLL? (1 = yes, 0 = no).  Only unlock DLL for
+ +  *      SDRC rates < 83MHz
+ +  *  r2 = number of MPU cycles to wait for SDRC to stabilize after
+ +  *      reprogramming the SDRC when switching to a slower MPU speed
+ +  *  r3 = increasing SDRC rate? (1 = yes, 0 = no)
+ +  *
+ +  * Params passed via the stack. The needed params will be copied in SRAM
+ +  *  before use by the code in SRAM (SDRAM is not accessible during SDRC
+ +  *  reconfiguration):
+ +  *  new SDRC_RFR_CTRL_0 register contents
+ +  *  new SDRC_ACTIM_CTRL_A_0 register contents
+ +  *  new SDRC_ACTIM_CTRL_B_0 register contents
+ +  *  new SDRC_MR_0 register value
+ +  *  new SDRC_RFR_CTRL_1 register contents
+ +  *  new SDRC_ACTIM_CTRL_A_1 register contents
+ +  *  new SDRC_ACTIM_CTRL_B_1 register contents
+ +  *  new SDRC_MR_1 register value
+ +  *
+ +  * If the param SDRC_RFR_CTRL_1 is 0, the parameters are not programmed into
+ +  * the SDRC CS1 registers
+ +  *
+ +  * NOTE: This code no longer attempts to program the SDRC AC timing and MR
+ +  * registers.  This is because the code currently cannot ensure that all
+ +  * L3 initiators (e.g., sDMA, IVA, DSS DISPC, etc.) are not accessing the
+ +  * SDRAM when the registers are written.  If the registers are changed while
+ +  * an initiator is accessing SDRAM, memory can be corrupted and/or the SDRC
+ +  * may enter an unpredictable state.  In the future, the intent is to
+ +  * re-enable this code in cases where we can ensure that no initiators are
+ +  * touching the SDRAM.  Until that time, users who know that their use case
+ +  * can satisfy the above requirement can enable the CONFIG_OMAP3_SDRC_AC_TIMING
+ +  * option.
+ +  *
+ +  * Richard Woodruff notes that any changes to this code must be carefully
+ +  * audited and tested to ensure that they don't cause a TLB miss while
+ +  * the SDRAM is inaccessible.  Such a situation will crash the system
+ +  * since it will cause the ARM MMU to attempt to walk the page tables.
+ +  * These crashes may be intermittent.
+ +  */
+ + 	.align	3
+ + ENTRY(omap3_sram_configure_core_dpll)
+ + 	stmfd	sp!, {r1-r12, lr}	@ store regs to stack
+ + 
+ + 					@ pull the extra args off the stack
+ + 					@  and store them in SRAM
+ + 
+ + /*
+ +  * PC-relative stores are deprecated in ARMv7 and lead to undefined behaviour
+ +  * in Thumb-2: use a r7 as a base instead.
+ +  * Be careful not to clobber r7 when maintaing this file.
+ +  */
+ +  THUMB(	adr	r7, omap3_sram_configure_core_dpll			)
+ + 	.macro strtext Rt:req, label:req
+ +  ARM(	str	\Rt, \label						)
+ +  THUMB(	str	\Rt, [r7, \label - omap3_sram_configure_core_dpll]	)
+ + 	.endm
+ + 
+ + 	ldr	r4, [sp, #52]
+ + 	strtext	r4, omap_sdrc_rfr_ctrl_0_val
+ + 	ldr	r4, [sp, #56]
+ + 	strtext	r4, omap_sdrc_actim_ctrl_a_0_val
+ + 	ldr	r4, [sp, #60]
+ + 	strtext	r4, omap_sdrc_actim_ctrl_b_0_val
+ + 	ldr	r4, [sp, #64]
+ + 	strtext	r4, omap_sdrc_mr_0_val
+ + 	ldr	r4, [sp, #68]
+ + 	strtext	r4, omap_sdrc_rfr_ctrl_1_val
+ + 	cmp	r4, #0			@ if SDRC_RFR_CTRL_1 is 0,
+ + 	beq	skip_cs1_params		@  do not use cs1 params
+ + 	ldr	r4, [sp, #72]
+ + 	strtext	r4, omap_sdrc_actim_ctrl_a_1_val
+ + 	ldr	r4, [sp, #76]
+ + 	strtext	r4, omap_sdrc_actim_ctrl_b_1_val
+ + 	ldr	r4, [sp, #80]
+ + 	strtext	r4, omap_sdrc_mr_1_val
+ + skip_cs1_params:
+ + 	mrc	p15, 0, r8, c1, c0, 0	@ read ctrl register
+ + 	bic	r10, r8, #0x800		@ clear Z-bit, disable branch prediction
+ + 	mcr	p15, 0, r10, c1, c0, 0	@ write ctrl register
+ + 	dsb				@ flush buffered writes to interconnect
+ + 	isb				@ prevent speculative exec past here
+ + 	cmp	r3, #1			@ if increasing SDRC clk rate,
+ + 	bleq	configure_sdrc		@ program the SDRC regs early (for RFR)
+ + 	cmp	r1, #SDRC_UNLOCK_DLL	@ set the intended DLL state
+ + 	bleq	unlock_dll
+ + 	blne	lock_dll
+ + 	bl	sdram_in_selfrefresh	@ put SDRAM in self refresh, idle SDRC
+ + 	bl 	configure_core_dpll	@ change the DPLL3 M2 divider
+ + 	mov	r12, r2
+ + 	bl	wait_clk_stable		@ wait for SDRC to stabilize
+ + 	bl	enable_sdrc		@ take SDRC out of idle
+ + 	cmp	r1, #SDRC_UNLOCK_DLL	@ wait for DLL status to change
+ + 	bleq	wait_dll_unlock
+ + 	blne	wait_dll_lock
+ + 	cmp	r3, #1			@ if increasing SDRC clk rate,
+ + 	beq	return_to_sdram		@ return to SDRAM code, otherwise,
+ + 	bl	configure_sdrc		@ reprogram SDRC regs now
+ + return_to_sdram:
+ + 	mcr	p15, 0, r8, c1, c0, 0	@ restore ctrl register
+ + 	isb				@ prevent speculative exec past here
+ + 	mov 	r0, #0 			@ return value
+ + 	ldmfd	sp!, {r1-r12, pc}	@ restore regs and return
+ + unlock_dll:
+ + 	ldr	r11, omap3_sdrc_dlla_ctrl
+ + 	ldr	r12, [r11]
+ + 	bic	r12, r12, #FIXEDDELAY_MASK
+ + 	orr	r12, r12, #FIXEDDELAY_DEFAULT
+ + 	orr	r12, r12, #DLLIDLE_MASK
+ + 	str	r12, [r11]		@ (no OCP barrier needed)
+ + 	bx	lr
+ + lock_dll:
+ + 	ldr	r11, omap3_sdrc_dlla_ctrl
+ + 	ldr	r12, [r11]
+ + 	bic	r12, r12, #DLLIDLE_MASK
+ + 	str	r12, [r11]		@ (no OCP barrier needed)
+ + 	bx	lr
+ + sdram_in_selfrefresh:
+ + 	ldr	r11, omap3_sdrc_power	@ read the SDRC_POWER register
+ + 	ldr	r12, [r11]		@ read the contents of SDRC_POWER
+ + 	mov	r9, r12			@ keep a copy of SDRC_POWER bits
+ + 	orr 	r12, r12, #SRFRONIDLEREQ_MASK	@ enable self refresh on idle
+ + 	str 	r12, [r11]		@ write back to SDRC_POWER register
+ + 	ldr	r12, [r11]		@ posted-write barrier for SDRC
+ + idle_sdrc:
+ + 	ldr	r11, omap3_cm_iclken1_core	@ read the CM_ICLKEN1_CORE reg
+ + 	ldr	r12, [r11]
+ + 	bic	r12, r12, #EN_SDRC_MASK		@ disable iclk bit for SDRC
+ + 	str 	r12, [r11]
+ + wait_sdrc_idle:
+ + 	ldr 	r11, omap3_cm_idlest1_core
+ + 	ldr 	r12, [r11]
+ + 	and 	r12, r12, #ST_SDRC_MASK		@ check for SDRC idle
+ + 	cmp 	r12, #ST_SDRC_MASK
+ + 	bne 	wait_sdrc_idle
+ + 	bx 	lr
+ + configure_core_dpll:
+ + 	ldr 	r11, omap3_cm_clksel1_pll
+ + 	ldr	r12, [r11]
+ + 	ldr	r10, core_m2_mask_val	@ modify m2 for core dpll
+ + 	and	r12, r12, r10
+ + 	orr	r12, r12, r0, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
+ + 	str	r12, [r11]
+ + 	ldr	r12, [r11]		@ posted-write barrier for CM
+ + 	bx	lr
+ + wait_clk_stable:
+ + 	subs 	r12, r12, #1
+ + 	bne	wait_clk_stable
+ + 	bx	lr
+ + enable_sdrc:
+ + 	ldr 	r11, omap3_cm_iclken1_core
+ + 	ldr	r12, [r11]
+ + 	orr 	r12, r12, #EN_SDRC_MASK		@ enable iclk bit for SDRC
+ + 	str 	r12, [r11]
+ + wait_sdrc_idle1:
+ + 	ldr 	r11, omap3_cm_idlest1_core
+ + 	ldr	r12, [r11]
+ + 	and 	r12, r12, #ST_SDRC_MASK
+ + 	cmp	r12, #0
+ + 	bne	wait_sdrc_idle1
+ + restore_sdrc_power_val:
+ + 	ldr	r11, omap3_sdrc_power
+ + 	str	r9, [r11]		@ restore SDRC_POWER, no barrier needed
+ + 	bx	lr
+ + wait_dll_lock:
+ + 	ldr	r11, omap3_sdrc_dlla_status
+ + 	ldr	r12, [r11]
+ + 	and 	r12, r12, #LOCKSTATUS_MASK
+ + 	cmp	r12, #LOCKSTATUS_MASK
+ + 	bne	wait_dll_lock
+ + 	bx	lr
+ + wait_dll_unlock:
+ + 	ldr	r11, omap3_sdrc_dlla_status
+ + 	ldr	r12, [r11]
+ + 	and	r12, r12, #LOCKSTATUS_MASK
+ + 	cmp	r12, #0x0
+ + 	bne	wait_dll_unlock
+ + 	bx	lr
+ + configure_sdrc:
+ + 	ldr	r12, omap_sdrc_rfr_ctrl_0_val	@ fetch value from SRAM
+ + 	ldr	r11, omap3_sdrc_rfr_ctrl_0	@ fetch addr from SRAM
+ + 	str	r12, [r11]			@ store
+ + #ifdef CONFIG_OMAP3_SDRC_AC_TIMING
+ + 	ldr	r12, omap_sdrc_actim_ctrl_a_0_val
+ + 	ldr	r11, omap3_sdrc_actim_ctrl_a_0
+ + 	str	r12, [r11]
+ + 	ldr	r12, omap_sdrc_actim_ctrl_b_0_val
+ + 	ldr	r11, omap3_sdrc_actim_ctrl_b_0
+ + 	str	r12, [r11]
+ + 	ldr	r12, omap_sdrc_mr_0_val
+ + 	ldr	r11, omap3_sdrc_mr_0
+ + 	str	r12, [r11]
+ + #endif
+ + 	ldr	r12, omap_sdrc_rfr_ctrl_1_val
+ + 	cmp	r12, #0			@ if SDRC_RFR_CTRL_1 is 0,
+ + 	beq	skip_cs1_prog		@  do not program cs1 params
+ + 	ldr	r11, omap3_sdrc_rfr_ctrl_1
+ + 	str	r12, [r11]
+ + #ifdef CONFIG_OMAP3_SDRC_AC_TIMING
+ + 	ldr	r12, omap_sdrc_actim_ctrl_a_1_val
+ + 	ldr	r11, omap3_sdrc_actim_ctrl_a_1
+ + 	str	r12, [r11]
+ + 	ldr	r12, omap_sdrc_actim_ctrl_b_1_val
+ + 	ldr	r11, omap3_sdrc_actim_ctrl_b_1
+ + 	str	r12, [r11]
+ + 	ldr	r12, omap_sdrc_mr_1_val
+ + 	ldr	r11, omap3_sdrc_mr_1
+ + 	str	r12, [r11]
+ + #endif
+ + skip_cs1_prog:
+ + 	ldr	r12, [r11]		@ posted-write barrier for SDRC
+ + 	bx	lr
+ + 
+ + 	.align
+ + omap3_sdrc_power:
+ + 	.word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
+ + omap3_cm_clksel1_pll:
+ + 	.word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
+ + omap3_cm_idlest1_core:
+ + 	.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
+ + omap3_cm_iclken1_core:
+ + 	.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
+ + 
+ + omap3_sdrc_rfr_ctrl_0:
+ + 	.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
+ + omap3_sdrc_rfr_ctrl_1:
+ + 	.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_1)
+ + omap3_sdrc_actim_ctrl_a_0:
+ + 	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
+ + omap3_sdrc_actim_ctrl_a_1:
+ + 	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_1)
+ + omap3_sdrc_actim_ctrl_b_0:
+ + 	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
+ + omap3_sdrc_actim_ctrl_b_1:
+ + 	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_1)
+ + omap3_sdrc_mr_0:
+ + 	.word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
+ + omap3_sdrc_mr_1:
+ + 	.word OMAP34XX_SDRC_REGADDR(SDRC_MR_1)
+ + omap_sdrc_rfr_ctrl_0_val:
+ + 	.word 0xDEADBEEF
+ + omap_sdrc_rfr_ctrl_1_val:
+ + 	.word 0xDEADBEEF
+ + omap_sdrc_actim_ctrl_a_0_val:
+ + 	.word 0xDEADBEEF
+ + omap_sdrc_actim_ctrl_a_1_val:
+ + 	.word 0xDEADBEEF
+ + omap_sdrc_actim_ctrl_b_0_val:
+ + 	.word 0xDEADBEEF
+ + omap_sdrc_actim_ctrl_b_1_val:
+ + 	.word 0xDEADBEEF
+ + omap_sdrc_mr_0_val:
+ + 	.word 0xDEADBEEF
+ + omap_sdrc_mr_1_val:
+ + 	.word 0xDEADBEEF
+ + 
+ + omap3_sdrc_dlla_status:
+ + 	.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
+ + omap3_sdrc_dlla_ctrl:
+ + 	.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
+ + core_m2_mask_val:
+ + 	.word 0x07FFFFFF
+ + ENDPROC(omap3_sram_configure_core_dpll)
+ + 
+ + ENTRY(omap3_sram_configure_core_dpll_sz)
+ + 	.word	. - omap3_sram_configure_core_dpll
+ + 
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/timer.c linux-3.2.1/arch/arm/mach-ckb_3352/timer.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/timer.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/timer.c	2014-11-25 13:19:15.083271041 +0900
+ ***************
+ *** 0 ****
+ --- 1,563 ----
+ + /*
+ +  * linux/arch/arm/mach-omap2/timer.c
+ +  *
+ +  * OMAP2 GP timer support.
+ +  *
+ +  * Copyright (C) 2009 Nokia Corporation
+ +  *
+ +  * Update to use new clocksource/clockevent layers
+ +  * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
+ +  * Copyright (C) 2007 MontaVista Software, Inc.
+ +  *
+ +  * Original driver:
+ +  * Copyright (C) 2005 Nokia Corporation
+ +  * Author: Paul Mundt <paul.mundt@nokia.com>
+ +  *         Juha Yrjölä <juha.yrjola@nokia.com>
+ +  * OMAP Dual-mode timer framework support by Timo Teras
+ +  *
+ +  * Some parts based off of TI's 24xx code:
+ +  *
+ +  * Copyright (C) 2004-2009 Texas Instruments, Inc.
+ +  *
+ +  * Roughly modelled after the OMAP1 MPU timer code.
+ +  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ +  *
+ +  * This file is subject to the terms and conditions of the GNU General Public
+ +  * License. See the file "COPYING" in the main directory of this archive
+ +  * for more details.
+ +  */
+ + #include <linux/init.h>
+ + #include <linux/time.h>
+ + #include <linux/interrupt.h>
+ + #include <linux/err.h>
+ + #include <linux/clk.h>
+ + #include <linux/delay.h>
+ + #include <linux/irq.h>
+ + #include <linux/clocksource.h>
+ + #include <linux/clockchips.h>
+ + #include <linux/slab.h>
+ + 
+ + #include <asm/mach/time.h>
+ + #include <plat/dmtimer.h>
+ + #include <asm/localtimer.h>
+ + #include <asm/sched_clock.h>
+ + #include "common.h"
+ + #include <plat/omap_hwmod.h>
+ + #include <plat/omap_device.h>
+ + #include <plat/omap-pm.h>
+ + #include <plat/clock.h>
+ + 
+ + #include "clockdomain.h"
+ + #include "powerdomain.h"
+ + #include "cm2xxx_3xxx.h"
+ + #include "cminst44xx.h"
+ + 
+ + /* Parent clocks, eventually these will come from the clock framework */
+ + 
+ + #define OMAP2_MPU_SOURCE	"sys_ck"
+ + #define OMAP3_MPU_SOURCE	OMAP2_MPU_SOURCE
+ + #define OMAP4_MPU_SOURCE	"sys_clkin_ck"
+ + #define OMAP2_32K_SOURCE	"func_32k_ck"
+ + #define OMAP3_32K_SOURCE	"omap_32k_fck"
+ + #define OMAP4_32K_SOURCE	"sys_32k_ck"
+ + #define AM33XX_RTC32K_SOURCE	"clk_32768_ck"
+ + 
+ + #ifdef CONFIG_OMAP_32K_TIMER
+ + #define OMAP2_CLKEV_SOURCE	OMAP2_32K_SOURCE
+ + #define OMAP3_CLKEV_SOURCE	OMAP3_32K_SOURCE
+ + #define OMAP4_CLKEV_SOURCE	OMAP4_32K_SOURCE
+ + #define OMAP3_SECURE_TIMER	12
+ + #else
+ + #define OMAP2_CLKEV_SOURCE	OMAP2_MPU_SOURCE
+ + #define OMAP3_CLKEV_SOURCE	OMAP3_MPU_SOURCE
+ + #define OMAP4_CLKEV_SOURCE	OMAP4_MPU_SOURCE
+ + #define OMAP3_SECURE_TIMER	1
+ + #endif
+ + 
+ + /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
+ + #define MAX_GPTIMER_ID		12
+ + 
+ + static u32 sys_timer_reserved;
+ + 
+ + /* Clockevent code */
+ + 
+ + static struct omap_dm_timer clkev;
+ + static struct clock_event_device clockevent_gpt;
+ + 
+ + static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
+ + {
+ + 	struct clock_event_device *evt = &clockevent_gpt;
+ + 
+ + 	__omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
+ + 
+ + 	evt->event_handler(evt);
+ + 	return IRQ_HANDLED;
+ + }
+ + 
+ + static struct irqaction omap2_gp_timer_irq = {
+ + 	.name		= "gp timer",
+ + 	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+ + 	.handler	= omap2_gp_timer_interrupt,
+ + };
+ + 
+ + static int omap2_gp_timer_set_next_event(unsigned long cycles,
+ + 					 struct clock_event_device *evt)
+ + {
+ + 	__omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
+ + 						0xffffffff - cycles, 1);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
+ + 				    struct clock_event_device *evt)
+ + {
+ + 	u32 period;
+ + 
+ + 	__omap_dm_timer_stop(&clkev, 1, clkev.rate);
+ + 
+ + 	switch (mode) {
+ + 	case CLOCK_EVT_MODE_PERIODIC:
+ + 		period = clkev.rate / HZ;
+ + 		period -= 1;
+ + 		/* Looks like we need to first set the load value separately */
+ + 		__omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
+ + 					0xffffffff - period, 1);
+ + 		__omap_dm_timer_load_start(&clkev,
+ + 					OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
+ + 						0xffffffff - period, 1);
+ + 		break;
+ + 	case CLOCK_EVT_MODE_ONESHOT:
+ + 		break;
+ + 	case CLOCK_EVT_MODE_UNUSED:
+ + 	case CLOCK_EVT_MODE_SHUTDOWN:
+ + 	case CLOCK_EVT_MODE_RESUME:
+ + 		break;
+ + 	}
+ + }
+ + 
+ + static struct clock_event_device clockevent_gpt = {
+ + 	.name		= "gp timer",
+ + 	.features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+ + 	.shift		= 32,
+ + 	.set_next_event	= omap2_gp_timer_set_next_event,
+ + 	.set_mode	= omap2_gp_timer_set_mode,
+ + };
+ + 
+ + static int _is_timer_idle(struct omap_hwmod *oh)
+ + {
+ + 	int ret;
+ + 
+ + 	if (!oh->clkdm)
+ + 		return -EINVAL;
+ + 	ret = omap4_cminst_wait_module_ready(oh->clkdm->prcm_partition,
+ + 			oh->clkdm->cm_inst,
+ + 			oh->clkdm->clkdm_offs,
+ + 			oh->prcm.omap4.clkctrl_offs);
+ + 	return ret;
+ + }
+ + 
+ + static int omap_dm_timer_switch_src(struct omap_hwmod *oh,
+ + 		struct omap_dm_timer *timer, const char *fck_source)
+ + {
+ + 	struct clk *src, *cur_parent;
+ + 	int res;
+ + 
+ + 	src = clk_get(NULL, fck_source);
+ + 	if (IS_ERR(src))
+ + 		return -EINVAL;
+ + 
+ + 	/* Reserve HW/clock-tree default source for fallback */
+ + 	cur_parent = clk_get_parent(timer->fclk);
+ + 
+ + 	/* Switch to configured source */
+ + 	res = __omap_dm_timer_set_source(timer->fclk, src);
+ + 	if (IS_ERR_VALUE(res))
+ + 		pr_warning("%s: timer%i cannot set source\n",
+ + 				__func__, timer->id);
+ + 
+ + 	/* Check whether timer module is went into idle state */
+ + 	res = _is_timer_idle(oh);
+ + 	if (res && cur_parent) {
+ + 		/* Fallback to default timer source */
+ + 		pr_warning("%s: Switching to HW default clocksource(%s) for "
+ + 				"timer%i, this may impact timekeeping in low "
+ + 				"power state\n",
+ + 				__func__, cur_parent->name, timer->id);
+ + 
+ + 		res = __omap_dm_timer_set_source(timer->fclk, cur_parent);
+ + 		if (IS_ERR_VALUE(res))
+ + 			pr_warning("%s: timer%i cannot set source\n",
+ + 					__func__, timer->id);
+ + 	}
+ + 	clk_put(src);
+ + 
+ + 	return res;
+ + }
+ + 
+ + static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
+ + 						int gptimer_id,
+ + 						const char *fck_source)
+ + {
+ + 	char name[10]; /* 10 = sizeof("gptXX_Xck0") */
+ + 	struct omap_hwmod *oh;
+ + 	size_t size;
+ + 	int res = 0;
+ + 
+ + 	sprintf(name, "timer%d", gptimer_id);
+ + 	omap_hwmod_setup_one(name);
+ + 	oh = omap_hwmod_lookup(name);
+ + 	if (!oh)
+ + 		return -ENODEV;
+ + 
+ + 	timer->irq = oh->mpu_irqs[0].irq;
+ + 	timer->id = gptimer_id;
+ + 	timer->phys_base = oh->slaves[0]->addr->pa_start;
+ + 	size = oh->slaves[0]->addr->pa_end - timer->phys_base;
+ + 
+ + 	/* Static mapping, never released */
+ + 	timer->io_base = ioremap(timer->phys_base, size);
+ + 	if (!timer->io_base)
+ + 		return -ENXIO;
+ + 
+ + 	/* After the dmtimer is using hwmod these clocks won't be needed */
+ + 	sprintf(name, "gpt%d_fck", gptimer_id);
+ + 	timer->fclk = clk_get(NULL, name);
+ + 	if (IS_ERR(timer->fclk))
+ + 		return -ENODEV;
+ + 
+ + 	sprintf(name, "gpt%d_ick", gptimer_id);
+ + 	timer->iclk = clk_get(NULL, name);
+ + 	if (IS_ERR(timer->iclk)) {
+ + 		clk_put(timer->fclk);
+ + 		return -ENODEV;
+ + 	}
+ + 
+ + 	omap_hwmod_enable(oh);
+ + 
+ + 	sys_timer_reserved |= (1 << (gptimer_id));
+ + 
+ + 	if (gptimer_id != 12) {
+ + 		res = omap_dm_timer_switch_src(oh, timer, fck_source);
+ + 	}
+ + 	__omap_dm_timer_init_regs(timer);
+ + 	__omap_dm_timer_reset(timer, 1, 1);
+ + 	timer->posted = 1;
+ + 
+ + 	timer->rate = clk_get_rate(timer->fclk);
+ + 
+ + 	timer->reserved = 1;
+ + 
+ + 	return res;
+ + }
+ + 
+ + static void __init omap2_gp_clockevent_init(int gptimer_id,
+ + 						const char *fck_source)
+ + {
+ + 	int res;
+ + 
+ + 	res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
+ + 	BUG_ON(res);
+ + 
+ + 	omap2_gp_timer_irq.dev_id = (void *)&clkev;
+ + 	setup_irq(clkev.irq, &omap2_gp_timer_irq);
+ + 
+ + 	__omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
+ + 
+ + 	clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
+ + 				     clockevent_gpt.shift);
+ + 	clockevent_gpt.max_delta_ns =
+ + 		clockevent_delta2ns(0xffffffff, &clockevent_gpt);
+ + 	clockevent_gpt.min_delta_ns =
+ + 		clockevent_delta2ns(3, &clockevent_gpt);
+ + 		/* Timer internal resynch latency. */
+ + 
+ + 	clockevent_gpt.cpumask = cpumask_of(0);
+ + 	clockevents_register_device(&clockevent_gpt);
+ + 
+ + 	pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
+ + 		gptimer_id, clkev.rate);
+ + }
+ + 
+ + /* Clocksource code */
+ + 
+ + #ifdef CONFIG_OMAP_32K_TIMER
+ + /*
+ +  * When 32k-timer is enabled, don't use GPTimer for clocksource
+ +  * instead, just leave default clocksource which uses the 32k
+ +  * sync counter.  See clocksource setup in plat-omap/counter_32k.c
+ +  */
+ + 
+ + static void __init omap2_gp_clocksource_init(int unused, const char *dummy)
+ + {
+ + 	omap_init_clocksource_32k();
+ + }
+ + 
+ + #else
+ + 
+ + static struct omap_dm_timer clksrc;
+ + 
+ + /*
+ +  * clocksource
+ +  */
+ + static DEFINE_CLOCK_DATA(cd);
+ + static cycle_t clocksource_read_cycles(struct clocksource *cs)
+ + {
+ + 	return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1);
+ + }
+ + 
+ + static struct clocksource clocksource_gpt = {
+ + 	.name		= "gp timer",
+ + 	.rating		= 300,
+ + 	.read		= clocksource_read_cycles,
+ + 	.mask		= CLOCKSOURCE_MASK(32),
+ + 	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
+ + };
+ + 
+ + static void notrace dmtimer_update_sched_clock(void)
+ + {
+ + 	u32 cyc;
+ + 
+ + 	cyc = __omap_dm_timer_read_counter(&clksrc, 1);
+ + 
+ + 	update_sched_clock(&cd, cyc, (u32)~0);
+ + }
+ + 
+ + unsigned long long notrace sched_clock(void)
+ + {
+ + 	u32 cyc = 0;
+ + 
+ + 	if (clksrc.reserved)
+ + 		cyc = __omap_dm_timer_read_counter(&clksrc, 1);
+ + 
+ + 	return cyc_to_sched_clock(&cd, cyc, (u32)~0);
+ + }
+ + 
+ + /* Setup free-running counter for clocksource */
+ + static void __init omap2_gp_clocksource_init(int gptimer_id,
+ + 						const char *fck_source)
+ + {
+ + 	int res;
+ + 
+ + 	res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source);
+ + 	BUG_ON(res);
+ + 
+ + 	pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
+ + 		gptimer_id, clksrc.rate);
+ + 
+ + 	__omap_dm_timer_load_start(&clksrc,
+ + 			OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
+ + 	init_sched_clock(&cd, dmtimer_update_sched_clock, 32, clksrc.rate);
+ + 
+ + 	if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
+ + 		pr_err("Could not register clocksource %s\n",
+ + 			clocksource_gpt.name);
+ + }
+ + #endif
+ + 
+ + static void omap_dmtimer_resume(void)
+ + {
+ + 	char name[10];
+ + 	struct omap_hwmod *oh;
+ + 
+ + 	sprintf(name, "timer%d", clkev.id);
+ + 	oh = omap_hwmod_lookup(name);
+ + 	if (!oh)
+ + 		return;
+ + 
+ + 	omap_hwmod_enable(oh);
+ + 	__omap_dm_timer_load_start(&clkev,
+ + 			OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
+ + 	__omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
+ + }
+ + 
+ + static void omap_dmtimer_suspend(void)
+ + {
+ + 	char name[10];
+ + 	struct omap_hwmod *oh;
+ + 
+ + 	sprintf(name, "timer%d", clkev.id);
+ + 	oh = omap_hwmod_lookup(name);
+ + 	if (!oh)
+ + 		return;
+ + 
+ + 	omap_hwmod_idle(oh);
+ + }
+ + 
+ + #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src,			\
+ + 				clksrc_nr, clksrc_src)			\
+ + static void __init omap##name##_timer_init(void)			\
+ + {									\
+ + 	omap2_gp_clockevent_init((clkev_nr), clkev_src);		\
+ + 	omap2_gp_clocksource_init((clksrc_nr), clksrc_src);		\
+ + }
+ + 
+ + #define OMAP_SYS_TIMER(name)						\
+ + struct sys_timer omap##name##_timer = {					\
+ + 	.init		= omap##name##_timer_init,			\
+ + 	.suspend	= omap_dmtimer_suspend,				\
+ + 	.resume		= omap_dmtimer_resume,				\
+ + };
+ + 
+ + OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
+ + OMAP_SYS_TIMER(3)
+ + OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
+ + 			2, OMAP3_MPU_SOURCE)
+ + OMAP_SYS_TIMER(3_secure)
+ + OMAP_SYS_TIMER_INIT(3_am33xx, 2, OMAP4_MPU_SOURCE, 1, AM33XX_RTC32K_SOURCE)
+ + OMAP_SYS_TIMER(3_am33xx)
+ + 
+ + 
+ + /**
+ +  * omap2_dm_timer_set_src - change the timer input clock source
+ +  * @pdev:	timer platform device pointer
+ +  * @source:	array index of parent clock source
+ +  */
+ + static int omap2_dm_timer_set_src(struct platform_device *pdev, int source)
+ + {
+ + 	int ret;
+ + 	struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
+ + 	struct clk *fclk, *parent;
+ + 	char *parent_name = NULL;
+ + 
+ + 	fclk = clk_get(&pdev->dev, "fck");
+ + 	if (IS_ERR_OR_NULL(fclk)) {
+ + 		dev_err(&pdev->dev, "%s: %d: clk_get() FAILED\n",
+ + 				__func__, __LINE__);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	switch (source) {
+ + 	case OMAP_TIMER_SRC_SYS_CLK:
+ + 		parent_name = "sys_ck";
+ + 		break;
+ + 
+ + 	case OMAP_TIMER_SRC_32_KHZ:
+ + 		parent_name = "32k_ck";
+ + 		break;
+ + 
+ + 	case OMAP_TIMER_SRC_EXT_CLK:
+ + 		if (pdata->timer_ip_version == OMAP_TIMER_IP_VERSION_1) {
+ + 			parent_name = "alt_ck";
+ + 			break;
+ + 		}
+ + 		dev_err(&pdev->dev, "%s: %d: invalid clk src.\n",
+ + 			__func__, __LINE__);
+ + 		clk_put(fclk);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	parent = clk_get(&pdev->dev, parent_name);
+ + 	if (IS_ERR_OR_NULL(parent)) {
+ + 		dev_err(&pdev->dev, "%s: %d: clk_get() %s FAILED\n",
+ + 			__func__, __LINE__, parent_name);
+ + 		clk_put(fclk);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	ret = clk_set_parent(fclk, parent);
+ + 	if (IS_ERR_VALUE(ret)) {
+ + 		dev_err(&pdev->dev, "%s: clk_set_parent() to %s FAILED\n",
+ + 			__func__, parent_name);
+ + 		ret = -EINVAL;
+ + 	}
+ + 
+ + 	clk_put(parent);
+ + 	clk_put(fclk);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * omap_timer_init - build and register timer device with an
+ +  * associated timer hwmod
+ +  * @oh:	timer hwmod pointer to be used to build timer device
+ +  * @user:	parameter that can be passed from calling hwmod API
+ +  *
+ +  * Called by omap_hwmod_for_each_by_class to register each of the timer
+ +  * devices present in the system. The number of timer devices is known
+ +  * by parsing through the hwmod database for a given class name. At the
+ +  * end of function call memory is allocated for timer device and it is
+ +  * registered to the framework ready to be proved by the driver.
+ +  */
+ + static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
+ + {
+ + 	int id;
+ + 	int ret = 0;
+ + 	char *name = "omap_timer";
+ + 	struct dmtimer_platform_data *pdata;
+ + 	struct platform_device *pdev;
+ + 	struct omap_timer_capability_dev_attr *timer_dev_attr;
+ + 	struct powerdomain *pwrdm;
+ + 
+ + 	pr_debug("%s: %s\n", __func__, oh->name);
+ + 
+ + 	/* on secure device, do not register secure timer */
+ + 	timer_dev_attr = oh->dev_attr;
+ + 	if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr)
+ + 		if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE)
+ + 			return ret;
+ + 
+ + 	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
+ + 	if (!pdata) {
+ + 		pr_err("%s: No memory for [%s]\n", __func__, oh->name);
+ + 		return -ENOMEM;
+ + 	}
+ + 
+ + 	/*
+ + 	 * Extract the IDs from name field in hwmod database
+ + 	 * and use the same for constructing ids' for the
+ + 	 * timer devices. In a way, we are avoiding usage of
+ + 	 * static variable witin the function to do the same.
+ + 	 * CAUTION: We have to be careful and make sure the
+ + 	 * name in hwmod database does not change in which case
+ + 	 * we might either make corresponding change here or
+ + 	 * switch back static variable mechanism.
+ + 	 */
+ + 	sscanf(oh->name, "timer%2d", &id);
+ + 
+ + 	pdata->set_timer_src = omap2_dm_timer_set_src;
+ + 	pdata->timer_ip_version = oh->class->rev;
+ + 
+ + 	/* Mark clocksource and clockevent timers as reserved */
+ + 	if ((sys_timer_reserved & (0x1 << id)))
+ + 		pdata->reserved = 1;
+ + 
+ + 	pwrdm = omap_hwmod_get_pwrdm(oh);
+ + 	pdata->loses_context = pwrdm_can_ever_lose_context(pwrdm);
+ + #ifdef CONFIG_PM
+ + 	pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
+ + #endif
+ + 	pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
+ + 				 NULL, 0, 0);
+ + 
+ + 	if (IS_ERR(pdev)) {
+ + 		pr_err("%s: Can't build omap_device for %s: %s.\n",
+ + 			__func__, name, oh->name);
+ + 		ret = -EINVAL;
+ + 	}
+ + 
+ + 	kfree(pdata);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * omap2_dm_timer_init - top level regular device initialization
+ +  *
+ +  * Uses dedicated hwmod api to parse through hwmod database for
+ +  * given class name and then build and register the timer device.
+ +  */
+ + static int __init omap2_dm_timer_init(void)
+ + {
+ + 	int ret;
+ + 
+ + 	ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL);
+ + 	if (unlikely(ret)) {
+ + 		pr_err("%s: device registration failed.\n", __func__);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ + arch_initcall(omap2_dm_timer_init);
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/twl-common.h linux-3.2.1/arch/arm/mach-ckb_3352/twl-common.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/twl-common.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/twl-common.h	2014-11-25 13:19:15.083271041 +0900
+ ***************
+ *** 0 ****
+ --- 1,55 ----
+ + #ifndef __OMAP_PMIC_COMMON__
+ + #define __OMAP_PMIC_COMMON__
+ + 
+ + #include <plat/irqs.h>
+ + 
+ + #define TWL_COMMON_PDATA_USB		(1 << 0)
+ + #define TWL_COMMON_PDATA_BCI		(1 << 1)
+ + #define TWL_COMMON_PDATA_MADC		(1 << 2)
+ + #define TWL_COMMON_PDATA_AUDIO		(1 << 3)
+ + 
+ + /* Common LDO regulators for TWL4030/TWL6030 */
+ + #define TWL_COMMON_REGULATOR_VDAC	(1 << 0)
+ + #define TWL_COMMON_REGULATOR_VAUX1	(1 << 1)
+ + #define TWL_COMMON_REGULATOR_VAUX2	(1 << 2)
+ + #define TWL_COMMON_REGULATOR_VAUX3	(1 << 3)
+ + 
+ + /* TWL6030 LDO regulators */
+ + #define TWL_COMMON_REGULATOR_VMMC	(1 << 4)
+ + #define TWL_COMMON_REGULATOR_VPP	(1 << 5)
+ + #define TWL_COMMON_REGULATOR_VUSIM	(1 << 6)
+ + #define TWL_COMMON_REGULATOR_VANA	(1 << 7)
+ + #define TWL_COMMON_REGULATOR_VCXIO	(1 << 8)
+ + #define TWL_COMMON_REGULATOR_VUSB	(1 << 9)
+ + #define TWL_COMMON_REGULATOR_CLK32KG	(1 << 10)
+ + 
+ + /* TWL4030 LDO regulators */
+ + #define TWL_COMMON_REGULATOR_VPLL1	(1 << 4)
+ + #define TWL_COMMON_REGULATOR_VPLL2	(1 << 5)
+ + 
+ + 
+ + struct twl4030_platform_data;
+ + 
+ + void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq,
+ + 		    struct twl4030_platform_data *pmic_data);
+ + void omap_pmic_late_init(void);
+ + 
+ + static inline void omap2_pmic_init(const char *pmic_type,
+ + 				   struct twl4030_platform_data *pmic_data)
+ + {
+ + 	omap_pmic_init(2, 2600, pmic_type, INT_24XX_SYS_NIRQ, pmic_data);
+ + }
+ + 
+ + static inline void omap3_pmic_init(const char *pmic_type,
+ + 				   struct twl4030_platform_data *pmic_data)
+ + {
+ + 	omap_pmic_init(1, 2600, pmic_type, INT_34XX_SYS_NIRQ, pmic_data);
+ + }
+ + 
+ + void omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
+ + 			   u32 pdata_flags, u32 regulators_flags);
+ + 
+ + void omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
+ + 			   u32 pdata_flags, u32 regulators_flags);
+ + 
+ + #endif /* __OMAP_PMIC_COMMON__ */
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/usb-host.c linux-3.2.1/arch/arm/mach-ckb_3352/usb-host.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/usb-host.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/usb-host.c	2014-11-25 13:19:15.083271041 +0900
+ ***************
+ *** 0 ****
+ --- 1,348 ----
+ + /*
+ +  * usb-host.c - OMAP USB Host
+ +  *
+ +  * This file will contain the board specific details for the
+ +  * Synopsys EHCI/OHCI host controller on OMAP3430 and onwards
+ +  *
+ +  * Copyright (C) 2007-2011 Texas Instruments
+ +  * Author: Vikram Pandita <vikram.pandita@ti.com>
+ +  * Author: Keshava Munegowda <keshava_mgowda@ti.com>
+ +  *
+ +  * Generalization by:
+ +  * Felipe Balbi <balbi@ti.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #include <linux/types.h>
+ + #include <linux/errno.h>
+ + #include <linux/delay.h>
+ + #include <linux/platform_device.h>
+ + #include <linux/slab.h>
+ + #include <linux/dma-mapping.h>
+ + 
+ + #include <asm/io.h>
+ + 
+ + #include <mach/hardware.h>
+ + #include <mach/irqs.h>
+ + #include <plat/usb.h>
+ + #include <plat/omap_device.h>
+ + 
+ + #include "mux.h"
+ + 
+ + #ifdef CONFIG_MFD_OMAP_USB_HOST
+ + 
+ + #define OMAP_USBHS_DEVICE	"usbhs_omap"
+ + #define	USBHS_UHH_HWMODNAME	"usb_host_hs"
+ + #define USBHS_TLL_HWMODNAME	"usb_tll_hs"
+ + 
+ + static struct usbhs_omap_platform_data		usbhs_data;
+ + static struct ehci_hcd_omap_platform_data	ehci_data;
+ + static struct ohci_hcd_omap_platform_data	ohci_data;
+ + 
+ + static struct omap_device_pm_latency omap_uhhtll_latency[] = {
+ + 	  {
+ + 		.deactivate_func = omap_device_idle_hwmods,
+ + 		.activate_func	 = omap_device_enable_hwmods,
+ + 		.flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+ + 	  },
+ + };
+ + 
+ + /* MUX settings for EHCI pins */
+ + /*
+ +  * setup_ehci_io_mux - initialize IO pad mux for USBHOST
+ +  */
+ + static void setup_ehci_io_mux(const enum usbhs_omap_port_mode *port_mode)
+ + {
+ + 	switch (port_mode[0]) {
+ + 	case OMAP_EHCI_PORT_MODE_PHY:
+ + 		omap_mux_init_signal("hsusb1_stp", OMAP_PIN_OUTPUT);
+ + 		omap_mux_init_signal("hsusb1_clk", OMAP_PIN_OUTPUT);
+ + 		omap_mux_init_signal("hsusb1_dir", OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb1_nxt", OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb1_data0", OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb1_data1", OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb1_data2", OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb1_data3", OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb1_data4", OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb1_data5", OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb1_data6", OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb1_data7", OMAP_PIN_INPUT_PULLDOWN);
+ + 		break;
+ + 	case OMAP_EHCI_PORT_MODE_TLL:
+ + 		omap_mux_init_signal("hsusb1_tll_stp",
+ + 			OMAP_PIN_INPUT_PULLUP);
+ + 		omap_mux_init_signal("hsusb1_tll_clk",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb1_tll_dir",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb1_tll_nxt",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb1_tll_data0",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb1_tll_data1",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb1_tll_data2",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb1_tll_data3",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb1_tll_data4",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb1_tll_data5",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb1_tll_data6",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb1_tll_data7",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		break;
+ + 	case OMAP_USBHS_PORT_MODE_UNUSED:
+ + 		/* FALLTHROUGH */
+ + 	default:
+ + 		break;
+ + 	}
+ + 
+ + 	switch (port_mode[1]) {
+ + 	case OMAP_EHCI_PORT_MODE_PHY:
+ + 		omap_mux_init_signal("hsusb2_stp", OMAP_PIN_OUTPUT);
+ + 		omap_mux_init_signal("hsusb2_clk", OMAP_PIN_OUTPUT);
+ + 		omap_mux_init_signal("hsusb2_dir", OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb2_nxt", OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb2_data0",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb2_data1",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb2_data2",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb2_data3",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb2_data4",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb2_data5",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb2_data6",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb2_data7",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		break;
+ + 	case OMAP_EHCI_PORT_MODE_TLL:
+ + 		omap_mux_init_signal("hsusb2_tll_stp",
+ + 			OMAP_PIN_INPUT_PULLUP);
+ + 		omap_mux_init_signal("hsusb2_tll_clk",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb2_tll_dir",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb2_tll_nxt",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb2_tll_data0",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb2_tll_data1",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb2_tll_data2",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb2_tll_data3",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb2_tll_data4",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb2_tll_data5",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb2_tll_data6",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb2_tll_data7",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		break;
+ + 	case OMAP_USBHS_PORT_MODE_UNUSED:
+ + 		/* FALLTHROUGH */
+ + 	default:
+ + 		break;
+ + 	}
+ + 
+ + 	switch (port_mode[2]) {
+ + 	case OMAP_EHCI_PORT_MODE_PHY:
+ + 		printk(KERN_WARNING "Port3 can't be used in PHY mode\n");
+ + 		break;
+ + 	case OMAP_EHCI_PORT_MODE_TLL:
+ + 		omap_mux_init_signal("hsusb3_tll_stp",
+ + 			OMAP_PIN_INPUT_PULLUP);
+ + 		omap_mux_init_signal("hsusb3_tll_clk",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb3_tll_dir",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb3_tll_nxt",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb3_tll_data0",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb3_tll_data1",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb3_tll_data2",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb3_tll_data3",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb3_tll_data4",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb3_tll_data5",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb3_tll_data6",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("hsusb3_tll_data7",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		break;
+ + 	case OMAP_USBHS_PORT_MODE_UNUSED:
+ + 		/* FALLTHROUGH */
+ + 	default:
+ + 		break;
+ + 	}
+ + 
+ + 	return;
+ + }
+ + 
+ + static void setup_ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
+ + {
+ + 	switch (port_mode[0]) {
+ + 	case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
+ + 	case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
+ + 	case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
+ + 	case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
+ + 		omap_mux_init_signal("mm1_rxdp",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("mm1_rxdm",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		/* FALLTHROUGH */
+ + 	case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
+ + 	case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
+ + 		omap_mux_init_signal("mm1_rxrcv",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		/* FALLTHROUGH */
+ + 	case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
+ + 	case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
+ + 		omap_mux_init_signal("mm1_txen_n", OMAP_PIN_OUTPUT);
+ + 		/* FALLTHROUGH */
+ + 	case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
+ + 	case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
+ + 		omap_mux_init_signal("mm1_txse0",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("mm1_txdat",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		break;
+ + 	case OMAP_USBHS_PORT_MODE_UNUSED:
+ + 		/* FALLTHROUGH */
+ + 	default:
+ + 		break;
+ + 	}
+ + 	switch (port_mode[1]) {
+ + 	case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
+ + 	case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
+ + 	case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
+ + 	case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
+ + 		omap_mux_init_signal("mm2_rxdp",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("mm2_rxdm",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		/* FALLTHROUGH */
+ + 	case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
+ + 	case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
+ + 		omap_mux_init_signal("mm2_rxrcv",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		/* FALLTHROUGH */
+ + 	case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
+ + 	case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
+ + 		omap_mux_init_signal("mm2_txen_n", OMAP_PIN_OUTPUT);
+ + 		/* FALLTHROUGH */
+ + 	case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
+ + 	case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
+ + 		omap_mux_init_signal("mm2_txse0",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("mm2_txdat",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		break;
+ + 	case OMAP_USBHS_PORT_MODE_UNUSED:
+ + 		/* FALLTHROUGH */
+ + 	default:
+ + 		break;
+ + 	}
+ + 	switch (port_mode[2]) {
+ + 	case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
+ + 	case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
+ + 	case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
+ + 	case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
+ + 		omap_mux_init_signal("mm3_rxdp",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("mm3_rxdm",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		/* FALLTHROUGH */
+ + 	case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
+ + 	case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
+ + 		omap_mux_init_signal("mm3_rxrcv",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		/* FALLTHROUGH */
+ + 	case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
+ + 	case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
+ + 		omap_mux_init_signal("mm3_txen_n", OMAP_PIN_OUTPUT);
+ + 		/* FALLTHROUGH */
+ + 	case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
+ + 	case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
+ + 		omap_mux_init_signal("mm3_txse0",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		omap_mux_init_signal("mm3_txdat",
+ + 			OMAP_PIN_INPUT_PULLDOWN);
+ + 		break;
+ + 	case OMAP_USBHS_PORT_MODE_UNUSED:
+ + 		/* FALLTHROUGH */
+ + 	default:
+ + 		break;
+ + 	}
+ + }
+ + 
+ + void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
+ + {
+ + 	struct omap_hwmod	*oh[2];
+ + 	struct omap_device	*od;
+ + 	int			bus_id = -1;
+ + 	int			i;
+ + 
+ + 	for (i = 0; i < OMAP3_HS_USB_PORTS; i++) {
+ + 		usbhs_data.port_mode[i] = pdata->port_mode[i];
+ + 		ohci_data.port_mode[i] = pdata->port_mode[i];
+ + 		ehci_data.port_mode[i] = pdata->port_mode[i];
+ + 		ehci_data.reset_gpio_port[i] = pdata->reset_gpio_port[i];
+ + 		ehci_data.regulator[i] = pdata->regulator[i];
+ + 	}
+ + 	ehci_data.phy_reset = pdata->phy_reset;
+ + 	ohci_data.es2_compatibility = pdata->es2_compatibility;
+ + 	usbhs_data.ehci_data = &ehci_data;
+ + 	usbhs_data.ohci_data = &ohci_data;
+ + 
+ + 	setup_ehci_io_mux(pdata->port_mode);
+ + 	setup_ohci_io_mux(pdata->port_mode);
+ + 	
+ + 	oh[0] = omap_hwmod_lookup(USBHS_UHH_HWMODNAME);
+ + 	if (!oh[0]) {
+ + 		pr_err("Could not look up %s\n", USBHS_UHH_HWMODNAME);
+ + 		return;
+ + 	}
+ + 
+ + 	oh[1] = omap_hwmod_lookup(USBHS_TLL_HWMODNAME);
+ + 	if (!oh[1]) {
+ + 		pr_err("Could not look up %s\n", USBHS_TLL_HWMODNAME);
+ + 		return;
+ + 	}
+ + 
+ + 	od = omap_device_build_ss(OMAP_USBHS_DEVICE, bus_id, oh, 2,
+ + 				(void *)&usbhs_data, sizeof(usbhs_data),
+ + 				omap_uhhtll_latency,
+ + 				ARRAY_SIZE(omap_uhhtll_latency), false);
+ + 	if (IS_ERR(od)) {
+ + 		pr_err("Could not build hwmod devices %s,%s\n",
+ + 			USBHS_UHH_HWMODNAME, USBHS_TLL_HWMODNAME);
+ + 		return;
+ + 	}
+ + }
+ + 
+ + #else
+ + 
+ + void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
+ + {
+ + }
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/usb-musb.c linux-3.2.1/arch/arm/mach-ckb_3352/usb-musb.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/usb-musb.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/usb-musb.c	2014-11-25 13:19:15.083271041 +0900
+ ***************
+ *** 0 ****
+ --- 1,115 ----
+ + /*
+ +  * linux/arch/arm/mach-omap2/usb-musb.c
+ +  *
+ +  * This file will contain the board specific details for the
+ +  * MENTOR USB OTG controller on OMAP3430
+ +  *
+ +  * Copyright (C) 2007-2008 Texas Instruments
+ +  * Copyright (C) 2008 Nokia Corporation
+ +  * Author: Vikram Pandita
+ +  *
+ +  * Generalization by:
+ +  * Felipe Balbi <felipe.balbi@nokia.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #include <linux/types.h>
+ + #include <linux/errno.h>
+ + #include <linux/delay.h>
+ + #include <linux/platform_device.h>
+ + #include <linux/clk.h>
+ + #include <linux/dma-mapping.h>
+ + #include <linux/io.h>
+ + 
+ + #include <linux/usb/musb.h>
+ + 
+ + #include <mach/hardware.h>
+ + #include <mach/irqs.h>
+ + #include <plat/usb.h>
+ + #include <plat/omap_device.h>
+ + #include "mux.h"
+ + 
+ + static struct musb_hdrc_config musb_config = {
+ + 	.fifo_mode	= 4,
+ + 	.multipoint	= 1,
+ + 	.dyn_fifo	= 1,
+ + 	.num_eps	= 16,
+ + 	.ram_bits	= 12,
+ + };
+ + 
+ + static struct musb_hdrc_platform_data musb_plat[] = {
+ + 	{
+ + 		.config         = &musb_config,
+ + 		.clock          = "ick",
+ + 	},
+ + 	{
+ + 		.config         = &musb_config,
+ + 		.clock          = "ick",
+ + 	},
+ + };
+ + 
+ + static u64 musb_dmamask = DMA_BIT_MASK(32);
+ + 
+ + static struct omap_musb_board_data musb_default_board_data = {
+ + 	.interface_type		= MUSB_INTERFACE_ULPI,
+ + 	.mode			= MUSB_OTG,
+ + 	.power			= 100,
+ + };
+ + 
+ + void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
+ + {
+ + 	struct omap_hwmod		*oh;
+ + 	struct platform_device		*pdev;
+ + 	struct device			*dev;
+ + 	int				bus_id = -1;
+ + 	const char			*oh_name, *name;
+ + 	struct omap_musb_board_data	*board_data;
+ + 
+ + 	if (musb_board_data)
+ + 		board_data = musb_board_data;
+ + 	else
+ + 		board_data = &musb_default_board_data;
+ + 
+ + 	/*
+ + 	 * REVISIT: This line can be removed once all the platforms using
+ + 	 * musb_core.c have been converted to use use clkdev.
+ + 	 */
+ + 	musb_plat[0].clock = "ick";
+ + 	musb_plat[0].board_data = board_data;
+ + 	musb_plat[0].power = board_data->power >> 1;
+ + 	musb_plat[0].mode = board_data->mode;
+ + 	musb_plat[0].extvbus = board_data->extvbus;
+ + 
+ + 	board_data->set_phy_power = ti81xx_musb_phy_power;
+ + 	oh_name = "usb_otg_hs";
+ + 	name = "musb-ti81xx";
+ + 	board_data->grndis_for_host_rx = 0;
+ + 	board_data->babble_ctrl = 0;
+ + 	if (omap_rev() >= AM335X_REV_ES2_0) {
+ + 		board_data->grndis_for_host_rx = 1;
+ + 		board_data->babble_ctrl = 1;
+ + 	}
+ + 
+ +         oh = omap_hwmod_lookup(oh_name);
+ +         if (WARN(!oh, "%s: could not find omap_hwmod for %s\n",
+ +                  __func__, oh_name))
+ +                 return;
+ + 
+ + 	pdev = omap_device_build(name, bus_id, oh, &musb_plat,
+ + 			       sizeof(musb_plat), NULL, 0, false);
+ + 	if (IS_ERR(pdev)) {
+ + 		pr_err("Could not build omap_device for %s %s\n",
+ + 						name, oh_name);
+ + 		return;
+ + 	}
+ + 
+ + 	dev = &pdev->dev;
+ + 	get_device(dev);
+ + 	dev->dma_mask = &musb_dmamask;
+ + 	dev->coherent_dma_mask = musb_dmamask;
+ + 	put_device(dev);
+ + 
+ + }
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/vc3xxx_data.c linux-3.2.1/arch/arm/mach-ckb_3352/vc3xxx_data.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/vc3xxx_data.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/vc3xxx_data.c	2014-11-25 13:19:15.087044268 +0900
+ ***************
+ *** 0 ****
+ --- 1,72 ----
+ + /*
+ +  * OMAP3 Voltage Controller (VC) data
+ +  *
+ +  * Copyright (C) 2007, 2010 Texas Instruments, Inc.
+ +  * Rajendra Nayak <rnayak@ti.com>
+ +  * Lesly A M <x0080970@ti.com>
+ +  * Thara Gopinath <thara@ti.com>
+ +  *
+ +  * Copyright (C) 2008, 2011 Nokia Corporation
+ +  * Kalle Jokiniemi
+ +  * Paul Walmsley
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + #include <linux/io.h>
+ + #include <linux/err.h>
+ + #include <linux/init.h>
+ + 
+ + #include "common.h"
+ + 
+ + #include "prm-regbits-34xx.h"
+ + #include "voltage.h"
+ + 
+ + #include "vc.h"
+ + 
+ + /*
+ +  * VC data common to 34xx/36xx chips
+ +  * XXX This stuff presumably belongs in the vc3xxx.c or vc.c file.
+ +  */
+ + static struct omap_vc_common omap3_vc_common = {
+ + 	.bypass_val_reg	 = OMAP3_PRM_VC_BYPASS_VAL_OFFSET,
+ + 	.data_shift	 = OMAP3430_DATA_SHIFT,
+ + 	.slaveaddr_shift = OMAP3430_SLAVEADDR_SHIFT,
+ + 	.regaddr_shift	 = OMAP3430_REGADDR_SHIFT,
+ + 	.valid		 = OMAP3430_VALID_MASK,
+ + 	.cmd_on_shift	 = OMAP3430_VC_CMD_ON_SHIFT,
+ + 	.cmd_on_mask	 = OMAP3430_VC_CMD_ON_MASK,
+ + 	.cmd_onlp_shift	 = OMAP3430_VC_CMD_ONLP_SHIFT,
+ + 	.cmd_ret_shift	 = OMAP3430_VC_CMD_RET_SHIFT,
+ + 	.cmd_off_shift	 = OMAP3430_VC_CMD_OFF_SHIFT,
+ + 	.i2c_cfg_hsen_mask = OMAP3430_HSEN_MASK,
+ + 	.i2c_cfg_reg	 = OMAP3_PRM_VC_I2C_CFG_OFFSET,
+ + 	.i2c_mcode_mask	 = OMAP3430_MCODE_MASK,
+ + };
+ + 
+ + struct omap_vc_channel omap3_vc_mpu = {
+ + 	.common = &omap3_vc_common,
+ + 	.smps_sa_reg	 = OMAP3_PRM_VC_SMPS_SA_OFFSET,
+ + 	.smps_volra_reg	 = OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET,
+ + 	.smps_cmdra_reg	 = OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET,
+ + 	.cfg_channel_reg = OMAP3_PRM_VC_CH_CONF_OFFSET,
+ + 	.cmdval_reg = OMAP3_PRM_VC_CMD_VAL_0_OFFSET,
+ + 	.smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA0_MASK,
+ + 	.smps_volra_mask = OMAP3430_VOLRA0_MASK,
+ + 	.smps_cmdra_mask = OMAP3430_CMDRA0_MASK,
+ + 	.cfg_channel_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT,
+ + };
+ + 
+ + struct omap_vc_channel omap3_vc_core = {
+ + 	.common = &omap3_vc_common,
+ + 	.smps_sa_reg	 = OMAP3_PRM_VC_SMPS_SA_OFFSET,
+ + 	.smps_volra_reg	 = OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET,
+ + 	.smps_cmdra_reg	 = OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET,
+ + 	.cfg_channel_reg = OMAP3_PRM_VC_CH_CONF_OFFSET,
+ + 	.cmdval_reg = OMAP3_PRM_VC_CMD_VAL_1_OFFSET,
+ + 	.smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA1_MASK,
+ + 	.smps_volra_mask = OMAP3430_VOLRA1_MASK,
+ + 	.smps_cmdra_mask = OMAP3430_CMDRA1_MASK,
+ + 	.cfg_channel_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT,
+ + };
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/vc.c linux-3.2.1/arch/arm/mach-ckb_3352/vc.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/vc.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/vc.c	2014-11-25 13:19:15.087044268 +0900
+ ***************
+ *** 0 ****
+ --- 1,346 ----
+ + /*
+ +  * OMAP Voltage Controller (VC) interface
+ +  *
+ +  * Copyright (C) 2011 Texas Instruments, Inc.
+ +  *
+ +  * This file is licensed under the terms of the GNU General Public
+ +  * License version 2. This program is licensed "as is" without any
+ +  * warranty of any kind, whether express or implied.
+ +  */
+ + #include <linux/kernel.h>
+ + #include <linux/delay.h>
+ + #include <linux/init.h>
+ + 
+ + #include <plat/cpu.h>
+ + 
+ + #include "voltage.h"
+ + #include "vc.h"
+ + #include "prm-regbits-34xx.h"
+ + #include "prm-regbits-44xx.h"
+ + //#include "prm44xx.h"
+ + 
+ + /**
+ +  * struct omap_vc_channel_cfg - describe the cfg_channel bitfield
+ +  * @sa: bit for slave address
+ +  * @rav: bit for voltage configuration register
+ +  * @rac: bit for command configuration register
+ +  * @racen: enable bit for RAC
+ +  * @cmd: bit for command value set selection
+ +  *
+ +  * Channel configuration bits, common for OMAP3+
+ +  * OMAP3 register: PRM_VC_CH_CONF
+ +  * OMAP4 register: PRM_VC_CFG_CHANNEL
+ +  * OMAP5 register: PRM_VC_SMPS_<voltdm>_CONFIG
+ +  */
+ + struct omap_vc_channel_cfg {
+ + 	u8 sa;
+ + 	u8 rav;
+ + 	u8 rac;
+ + 	u8 racen;
+ + 	u8 cmd;
+ + };
+ + 
+ + static struct omap_vc_channel_cfg vc_default_channel_cfg = {
+ + 	.sa    = BIT(0),
+ + 	.rav   = BIT(1),
+ + 	.rac   = BIT(2),
+ + 	.racen = BIT(3),
+ + 	.cmd   = BIT(4),
+ + };
+ + 
+ + /*
+ +  * On OMAP3+, all VC channels have the above default bitfield
+ +  * configuration, except the OMAP4 MPU channel.  This appears
+ +  * to be a freak accident as every other VC channel has the
+ +  * default configuration, thus creating a mutant channel config.
+ +  */
+ + static struct omap_vc_channel_cfg vc_mutant_channel_cfg = {
+ + 	.sa    = BIT(0),
+ + 	.rav   = BIT(2),
+ + 	.rac   = BIT(3),
+ + 	.racen = BIT(4),
+ + 	.cmd   = BIT(1),
+ + };
+ + 
+ + static struct omap_vc_channel_cfg *vc_cfg_bits;
+ + #define CFG_CHANNEL_MASK 0x1f
+ + 
+ + /**
+ +  * omap_vc_config_channel - configure VC channel to PMIC mappings
+ +  * @voltdm: pointer to voltagdomain defining the desired VC channel
+ +  *
+ +  * Configures the VC channel to PMIC mappings for the following
+ +  * PMIC settings
+ +  * - i2c slave address (SA)
+ +  * - voltage configuration address (RAV)
+ +  * - command configuration address (RAC) and enable bit (RACEN)
+ +  * - command values for ON, ONLP, RET and OFF (CMD)
+ +  *
+ +  * This function currently only allows flexible configuration of the
+ +  * non-default channel.  Starting with OMAP4, there are more than 2
+ +  * channels, with one defined as the default (on OMAP4, it's MPU.)
+ +  * Only the non-default channel can be configured.
+ +  */
+ + static int omap_vc_config_channel(struct voltagedomain *voltdm)
+ + {
+ + 	struct omap_vc_channel *vc = voltdm->vc;
+ + 
+ + 	/*
+ + 	 * For default channel, the only configurable bit is RACEN.
+ + 	 * All others must stay at zero (see function comment above.)
+ + 	 */
+ + 	if (vc->flags & OMAP_VC_CHANNEL_DEFAULT)
+ + 		vc->cfg_channel &= vc_cfg_bits->racen;
+ + 
+ + 	voltdm->rmw(CFG_CHANNEL_MASK << vc->cfg_channel_sa_shift,
+ + 		    vc->cfg_channel << vc->cfg_channel_sa_shift,
+ + 		    vc->cfg_channel_reg);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /* Voltage scale and accessory APIs */
+ + int omap_vc_pre_scale(struct voltagedomain *voltdm,
+ + 		      unsigned long target_volt,
+ + 		      u8 *target_vsel, u8 *current_vsel)
+ + {
+ + 	struct omap_vc_channel *vc = voltdm->vc;
+ + 	u32 vc_cmdval;
+ + 
+ + 	/* Check if sufficient pmic info is available for this vdd */
+ + 	if (!voltdm->pmic) {
+ + 		pr_err("%s: Insufficient pmic info to scale the vdd_%s\n",
+ + 			__func__, voltdm->name);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	if (!voltdm->pmic->uv_to_vsel) {
+ + 		pr_err("%s: PMIC function to convert voltage in uV to"
+ + 			"vsel not registered. Hence unable to scale voltage"
+ + 			"for vdd_%s\n", __func__, voltdm->name);
+ + 		return -ENODATA;
+ + 	}
+ + 
+ + 	if (!voltdm->read || !voltdm->write) {
+ + 		pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+ + 			__func__, voltdm->name);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	*target_vsel = voltdm->pmic->uv_to_vsel(target_volt);
+ + 	*current_vsel = voltdm->pmic->uv_to_vsel(voltdm->nominal_volt);
+ + 
+ + 	/* Setting the ON voltage to the new target voltage */
+ + 	vc_cmdval = voltdm->read(vc->cmdval_reg);
+ + 	vc_cmdval &= ~vc->common->cmd_on_mask;
+ + 	vc_cmdval |= (*target_vsel << vc->common->cmd_on_shift);
+ + 	voltdm->write(vc_cmdval, vc->cmdval_reg);
+ + 
+ + 	omap_vp_update_errorgain(voltdm, target_volt);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + void omap_vc_post_scale(struct voltagedomain *voltdm,
+ + 			unsigned long target_volt,
+ + 			u8 target_vsel, u8 current_vsel)
+ + {
+ + 	u32 smps_steps = 0, smps_delay = 0;
+ + 
+ + 	smps_steps = abs(target_vsel - current_vsel);
+ + 	/* SMPS slew rate / step size. 2us added as buffer. */
+ + 	smps_delay = ((smps_steps * voltdm->pmic->step_size) /
+ + 			voltdm->pmic->slew_rate) + 2;
+ + 	udelay(smps_delay);
+ + }
+ + 
+ + /* vc_bypass_scale - VC bypass method of voltage scaling */
+ + int omap_vc_bypass_scale(struct voltagedomain *voltdm,
+ + 			 unsigned long target_volt)
+ + {
+ + 	struct omap_vc_channel *vc = voltdm->vc;
+ + 	u32 loop_cnt = 0, retries_cnt = 0;
+ + 	u32 vc_valid, vc_bypass_val_reg, vc_bypass_value;
+ + 	u8 target_vsel, current_vsel;
+ + 	int ret;
+ + 
+ + 	ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, &current_vsel);
+ + 	if (ret)
+ + 		return ret;
+ + 
+ + 	vc_valid = vc->common->valid;
+ + 	vc_bypass_val_reg = vc->common->bypass_val_reg;
+ + 	vc_bypass_value = (target_vsel << vc->common->data_shift) |
+ + 		(vc->volt_reg_addr << vc->common->regaddr_shift) |
+ + 		(vc->i2c_slave_addr << vc->common->slaveaddr_shift);
+ + 
+ + 	voltdm->write(vc_bypass_value, vc_bypass_val_reg);
+ + 	voltdm->write(vc_bypass_value | vc_valid, vc_bypass_val_reg);
+ + 
+ + 	vc_bypass_value = voltdm->read(vc_bypass_val_reg);
+ + 	/*
+ + 	 * Loop till the bypass command is acknowledged from the SMPS.
+ + 	 * NOTE: This is legacy code. The loop count and retry count needs
+ + 	 * to be revisited.
+ + 	 */
+ + 	while (!(vc_bypass_value & vc_valid)) {
+ + 		loop_cnt++;
+ + 
+ + 		if (retries_cnt > 10) {
+ + 			pr_warning("%s: Retry count exceeded\n", __func__);
+ + 			return -ETIMEDOUT;
+ + 		}
+ + 
+ + 		if (loop_cnt > 50) {
+ + 			retries_cnt++;
+ + 			loop_cnt = 0;
+ + 			udelay(10);
+ + 		}
+ + 		vc_bypass_value = voltdm->read(vc_bypass_val_reg);
+ + 	}
+ + 
+ + 	omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel);
+ + 	return 0;
+ + }
+ + 
+ + static void __init omap3_vfsm_init(struct voltagedomain *voltdm)
+ + {
+ + 	/*
+ + 	 * Voltage Manager FSM parameters init
+ + 	 * XXX This data should be passed in from the board file
+ + 	 */
+ + 	voltdm->write(OMAP3_CLKSETUP, OMAP3_PRM_CLKSETUP_OFFSET);
+ + 	voltdm->write(OMAP3_VOLTOFFSET, OMAP3_PRM_VOLTOFFSET_OFFSET);
+ + 	voltdm->write(OMAP3_VOLTSETUP2, OMAP3_PRM_VOLTSETUP2_OFFSET);
+ + }
+ + 
+ + static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
+ + {
+ + 	static bool is_initialized;
+ + 
+ + 	if (is_initialized)
+ + 		return;
+ + 
+ + 	omap3_vfsm_init(voltdm);
+ + 
+ + 	is_initialized = true;
+ + }
+ + 
+ + /**
+ +  * omap_vc_i2c_init - initialize I2C interface to PMIC
+ +  * @voltdm: voltage domain containing VC data
+ +  *
+ +  * Use PMIC supplied seetings for I2C high-speed mode and
+ +  * master code (if set) and program the VC I2C configuration
+ +  * register.
+ +  *
+ +  * The VC I2C configuration is common to all VC channels,
+ +  * so this function only configures I2C for the first VC
+ +  * channel registers.  All other VC channels will use the
+ +  * same configuration.
+ +  */
+ + static void __init omap_vc_i2c_init(struct voltagedomain *voltdm)
+ + {
+ + 	struct omap_vc_channel *vc = voltdm->vc;
+ + 	static bool initialized;
+ + 	static bool i2c_high_speed;
+ + 	u8 mcode;
+ + 
+ + 	if (initialized) {
+ + 		if (voltdm->pmic->i2c_high_speed != i2c_high_speed)
+ + 			pr_warn("%s: I2C config for all channels must match.",
+ + 				__func__);
+ + 		return;
+ + 	}
+ + 
+ + 	i2c_high_speed = voltdm->pmic->i2c_high_speed;
+ + 	if (i2c_high_speed)
+ + 		voltdm->rmw(vc->common->i2c_cfg_hsen_mask,
+ + 			    vc->common->i2c_cfg_hsen_mask,
+ + 			    vc->common->i2c_cfg_reg);
+ + 
+ + 	mcode = voltdm->pmic->i2c_mcode;
+ + 	if (mcode)
+ + 		voltdm->rmw(vc->common->i2c_mcode_mask,
+ + 			    mcode << __ffs(vc->common->i2c_mcode_mask),
+ + 			    vc->common->i2c_cfg_reg);
+ + 
+ + 	initialized = true;
+ + }
+ + 
+ + void __init omap_vc_init_channel(struct voltagedomain *voltdm)
+ + {
+ + 	struct omap_vc_channel *vc = voltdm->vc;
+ + 	u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
+ + 	u32 val;
+ + 
+ + 	if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) {
+ + 		pr_err("%s: missing PMIC for vdd_%s.\n",
+ + 		       __func__, voltdm->name);
+ + 		return;
+ + 	}
+ + 
+ + 	if (!voltdm->read || !voltdm->write) {
+ + 		pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+ + 			__func__, voltdm->name);
+ + 		return;
+ + 	}
+ + 
+ + 	vc->cfg_channel = 0;
+ + 	if (vc->flags & OMAP_VC_CHANNEL_CFG_MUTANT)
+ + 		vc_cfg_bits = &vc_mutant_channel_cfg;
+ + 	else
+ + 		vc_cfg_bits = &vc_default_channel_cfg;
+ + 
+ + 	/* get PMIC/board specific settings */
+ + 	vc->i2c_slave_addr = voltdm->pmic->i2c_slave_addr;
+ + 	vc->volt_reg_addr = voltdm->pmic->volt_reg_addr;
+ + 	vc->cmd_reg_addr = voltdm->pmic->cmd_reg_addr;
+ + 	vc->setup_time = voltdm->pmic->volt_setup_time;
+ + 
+ + 	/* Configure the i2c slave address for this VC */
+ + 	voltdm->rmw(vc->smps_sa_mask,
+ + 		    vc->i2c_slave_addr << __ffs(vc->smps_sa_mask),
+ + 		    vc->smps_sa_reg);
+ + 	vc->cfg_channel |= vc_cfg_bits->sa;
+ + 
+ + 	/*
+ + 	 * Configure the PMIC register addresses.
+ + 	 */
+ + 	voltdm->rmw(vc->smps_volra_mask,
+ + 		    vc->volt_reg_addr << __ffs(vc->smps_volra_mask),
+ + 		    vc->smps_volra_reg);
+ + 	vc->cfg_channel |= vc_cfg_bits->rav;
+ + 
+ + 	if (vc->cmd_reg_addr) {
+ + 		voltdm->rmw(vc->smps_cmdra_mask,
+ + 			    vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask),
+ + 			    vc->smps_cmdra_reg);
+ + 		vc->cfg_channel |= vc_cfg_bits->rac | vc_cfg_bits->racen;
+ + 	}
+ + 
+ + 	/* Set up the on, inactive, retention and off voltage */
+ + 	on_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->on_volt);
+ + 	onlp_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->onlp_volt);
+ + 	ret_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->ret_volt);
+ + 	off_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->off_volt);
+ + 	val = ((on_vsel << vc->common->cmd_on_shift) |
+ + 	       (onlp_vsel << vc->common->cmd_onlp_shift) |
+ + 	       (ret_vsel << vc->common->cmd_ret_shift) |
+ + 	       (off_vsel << vc->common->cmd_off_shift));
+ + 	voltdm->write(val, vc->cmdval_reg);
+ + 	vc->cfg_channel |= vc_cfg_bits->cmd;
+ + 
+ + 	/* Channel configuration */
+ + 	omap_vc_config_channel(voltdm);
+ + 
+ + 	/* Configure the setup times */
+ + 	voltdm->rmw(voltdm->vfsm->voltsetup_mask,
+ + 		    vc->setup_time << __ffs(voltdm->vfsm->voltsetup_mask),
+ + 		    voltdm->vfsm->voltsetup_reg);
+ + 
+ + 	omap_vc_i2c_init(voltdm);
+ + 
+ + 	omap3_vc_init_channel(voltdm);
+ + }
+ + 
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/vc.h linux-3.2.1/arch/arm/mach-ckb_3352/vc.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/vc.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/vc.h	2014-11-25 13:19:15.087044268 +0900
+ ***************
+ *** 0 ****
+ --- 1,125 ----
+ + /*
+ +  * OMAP3/4 Voltage Controller (VC) structure and macro definitions
+ +  *
+ +  * Copyright (C) 2007, 2010 Texas Instruments, Inc.
+ +  * Rajendra Nayak <rnayak@ti.com>
+ +  * Lesly A M <x0080970@ti.com>
+ +  * Thara Gopinath <thara@ti.com>
+ +  *
+ +  * Copyright (C) 2008, 2011 Nokia Corporation
+ +  * Kalle Jokiniemi
+ +  * Paul Walmsley
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License version
+ +  * 2 as published by the Free Software Foundation.
+ +  */
+ + #ifndef __ARCH_ARM_MACH_OMAP2_VC_H
+ + #define __ARCH_ARM_MACH_OMAP2_VC_H
+ + 
+ + #include <linux/kernel.h>
+ + 
+ + struct voltagedomain;
+ + 
+ + /**
+ +  * struct omap_vc_common - per-VC register/bitfield data
+ +  * @cmd_on_mask: ON bitmask in PRM_VC_CMD_VAL* register
+ +  * @valid: VALID bitmask in PRM_VC_BYPASS_VAL register
+ +  * @bypass_val_reg: Offset of PRM_VC_BYPASS_VAL reg from PRM start
+ +  * @data_shift: DATA field shift in PRM_VC_BYPASS_VAL register
+ +  * @slaveaddr_shift: SLAVEADDR field shift in PRM_VC_BYPASS_VAL register
+ +  * @regaddr_shift: REGADDR field shift in PRM_VC_BYPASS_VAL register
+ +  * @cmd_on_shift: ON field shift in PRM_VC_CMD_VAL_* register
+ +  * @cmd_onlp_shift: ONLP field shift in PRM_VC_CMD_VAL_* register
+ +  * @cmd_ret_shift: RET field shift in PRM_VC_CMD_VAL_* register
+ +  * @cmd_off_shift: OFF field shift in PRM_VC_CMD_VAL_* register
+ +  * @i2c_cfg_reg: I2C configuration register offset
+ +  * @i2c_cfg_hsen_mask: high-speed mode bit field mask in I2C config register
+ +  * @i2c_mcode_mask: MCODE field mask for I2C config register
+ +  *
+ +  * XXX One of cmd_on_mask and cmd_on_shift are not needed
+ +  * XXX VALID should probably be a shift, not a mask
+ +  */
+ + struct omap_vc_common {
+ + 	u32 cmd_on_mask;
+ + 	u32 valid;
+ + 	u8 bypass_val_reg;
+ + 	u8 data_shift;
+ + 	u8 slaveaddr_shift;
+ + 	u8 regaddr_shift;
+ + 	u8 cmd_on_shift;
+ + 	u8 cmd_onlp_shift;
+ + 	u8 cmd_ret_shift;
+ + 	u8 cmd_off_shift;
+ + 	u8 i2c_cfg_reg;
+ + 	u8 i2c_cfg_hsen_mask;
+ + 	u8 i2c_mcode_mask;
+ + };
+ + 
+ + /* omap_vc_channel.flags values */
+ + #define OMAP_VC_CHANNEL_DEFAULT BIT(0)
+ + #define OMAP_VC_CHANNEL_CFG_MUTANT BIT(1)
+ + 
+ + /**
+ +  * struct omap_vc_channel - VC per-instance data
+ +  * @i2c_slave_addr: I2C slave address of PMIC for this VC channel
+ +  * @volt_reg_addr: voltage configuration register address
+ +  * @cmd_reg_addr: command configuration register address
+ +  * @setup_time: setup time (in sys_clk cycles) of regulator for this channel
+ +  * @cfg_channel: current value of VC channel configuration register
+ +  * @i2c_high_speed: whether or not to use I2C high-speed mode
+ +  *
+ +  * @common: pointer to VC common data for this platform
+ +  * @smps_sa_mask: i2c slave address bitmask in the PRM_VC_SMPS_SA register
+ +  * @smps_volra_mask: VOLRA* bitmask in the PRM_VC_VOL_RA register
+ +  * @smps_cmdra_mask: CMDRA* bitmask in the PRM_VC_CMD_RA register
+ +  * @cmdval_reg: register for on/ret/off voltage level values for this channel
+ +  * @smps_sa_reg: Offset of PRM_VC_SMPS_SA reg from PRM start
+ +  * @smps_volra_reg: Offset of PRM_VC_SMPS_VOL_RA reg from PRM start
+ +  * @smps_cmdra_reg: Offset of PRM_VC_SMPS_CMD_RA reg from PRM start
+ +  * @cfg_channel_reg: VC channel configuration register
+ +  * @cfg_channel_sa_shift: bit shift for slave address cfg_channel register
+ +  * @flags: VC channel-specific flags (optional)
+ +  */
+ + struct omap_vc_channel {
+ + 	/* channel state */
+ + 	u16 i2c_slave_addr;
+ + 	u16 volt_reg_addr;
+ + 	u16 cmd_reg_addr;
+ + 	u16 setup_time;
+ + 	u8 cfg_channel;
+ + 	bool i2c_high_speed;
+ + 
+ + 	/* register access data */
+ + 	const struct omap_vc_common *common;
+ + 	u32 smps_sa_mask;
+ + 	u32 smps_volra_mask;
+ + 	u32 smps_cmdra_mask;
+ + 	u8 cmdval_reg;
+ + 	u8 smps_sa_reg;
+ + 	u8 smps_volra_reg;
+ + 	u8 smps_cmdra_reg;
+ + 	u8 cfg_channel_reg;
+ + 	u8 cfg_channel_sa_shift;
+ + 	u8 flags;
+ + };
+ + 
+ + extern struct omap_vc_channel omap3_vc_mpu;
+ + extern struct omap_vc_channel omap3_vc_core;
+ + 
+ + extern struct omap_vc_channel omap4_vc_mpu;
+ + extern struct omap_vc_channel omap4_vc_iva;
+ + extern struct omap_vc_channel omap4_vc_core;
+ + 
+ + void omap_vc_init_channel(struct voltagedomain *voltdm);
+ + int omap_vc_pre_scale(struct voltagedomain *voltdm,
+ + 		      unsigned long target_volt,
+ + 		      u8 *target_vsel, u8 *current_vsel);
+ + void omap_vc_post_scale(struct voltagedomain *voltdm,
+ + 			unsigned long target_volt,
+ + 			u8 target_vsel, u8 current_vsel);
+ + int omap_vc_bypass_scale(struct voltagedomain *voltdm,
+ + 			 unsigned long target_volt);
+ + 
+ + #endif
+ + 
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/voltage.c linux-3.2.1/arch/arm/mach-ckb_3352/voltage.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/voltage.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/voltage.c	2014-11-25 13:19:15.087044268 +0900
+ ***************
+ *** 0 ****
+ --- 1,431 ----
+ + /*
+ +  * OMAP3/OMAP4 Voltage Management Routines
+ +  *
+ +  * Author: Thara Gopinath	<thara@ti.com>
+ +  *
+ +  * Copyright (C) 2007 Texas Instruments, Inc.
+ +  * Rajendra Nayak <rnayak@ti.com>
+ +  * Lesly A M <x0080970@ti.com>
+ +  *
+ +  * Copyright (C) 2008, 2011 Nokia Corporation
+ +  * Kalle Jokiniemi
+ +  * Paul Walmsley
+ +  *
+ +  * Copyright (C) 2010 Texas Instruments, Inc.
+ +  * Thara Gopinath <thara@ti.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #include <linux/delay.h>
+ + #include <linux/io.h>
+ + #include <linux/err.h>
+ + #include <linux/export.h>
+ + #include <linux/debugfs.h>
+ + #include <linux/slab.h>
+ + #include <linux/clk.h>
+ + 
+ + #include "common.h"
+ + 
+ + #include "prm-regbits-34xx.h"
+ + #include "prm-regbits-44xx.h"
+ + //#include "prm44xx.h"
+ + #include "prcm44xx.h"
+ + #include "prminst44xx.h"
+ + #include "control.h"
+ + 
+ + #include "voltage.h"
+ + #include "powerdomain.h"
+ + 
+ + #include "vc.h"
+ + #include "vp.h"
+ + 
+ + static LIST_HEAD(voltdm_list);
+ + 
+ + /* Public functions */
+ + /**
+ +  * voltdm_get_voltage() - Gets the current non-auto-compensated voltage
+ +  * @voltdm:	pointer to the voltdm for which current voltage info is needed
+ +  *
+ +  * API to get the current non-auto-compensated voltage for a voltage domain.
+ +  * Returns 0 in case of error else returns the current voltage.
+ +  */
+ + unsigned long voltdm_get_voltage(struct voltagedomain *voltdm)
+ + {
+ + 	if (!voltdm || IS_ERR(voltdm)) {
+ + 		pr_warning("%s: VDD specified does not exist!\n", __func__);
+ + 		return 0;
+ + 	}
+ + 
+ + 	return voltdm->nominal_volt;
+ + }
+ + 
+ + /**
+ +  * voltdm_scale() - API to scale voltage of a particular voltage domain.
+ +  * @voltdm: pointer to the voltage domain which is to be scaled.
+ +  * @target_volt: The target voltage of the voltage domain
+ +  *
+ +  * This API should be called by the kernel to do the voltage scaling
+ +  * for a particular voltage domain during DVFS.
+ +  */
+ + int voltdm_scale(struct voltagedomain *voltdm,
+ + 		 unsigned long target_volt)
+ + {
+ + 	int ret;
+ + 
+ + 	if (!voltdm || IS_ERR(voltdm)) {
+ + 		pr_warning("%s: VDD specified does not exist!\n", __func__);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	if (!voltdm->scale) {
+ + 		pr_err("%s: No voltage scale API registered for vdd_%s\n",
+ + 			__func__, voltdm->name);
+ + 		return -ENODATA;
+ + 	}
+ + 
+ + 	ret = voltdm->scale(voltdm, target_volt);
+ + 	if (!ret)
+ + 		voltdm->nominal_volt = target_volt;
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * voltdm_reset() - Resets the voltage of a particular voltage domain
+ +  *		    to that of the current OPP.
+ +  * @voltdm: pointer to the voltage domain whose voltage is to be reset.
+ +  *
+ +  * This API finds out the correct voltage the voltage domain is supposed
+ +  * to be at and resets the voltage to that level. Should be used especially
+ +  * while disabling any voltage compensation modules.
+ +  */
+ + void voltdm_reset(struct voltagedomain *voltdm)
+ + {
+ + 	unsigned long target_volt;
+ + 
+ + 	if (!voltdm || IS_ERR(voltdm)) {
+ + 		pr_warning("%s: VDD specified does not exist!\n", __func__);
+ + 		return;
+ + 	}
+ + 
+ + 	target_volt = voltdm_get_voltage(voltdm);
+ + 	if (!target_volt) {
+ + 		pr_err("%s: unable to find current voltage for vdd_%s\n",
+ + 			__func__, voltdm->name);
+ + 		return;
+ + 	}
+ + 
+ + 	voltdm_scale(voltdm, target_volt);
+ + }
+ + 
+ + /**
+ +  * omap_voltage_get_volttable() - API to get the voltage table associated with a
+ +  *				particular voltage domain.
+ +  * @voltdm:	pointer to the VDD for which the voltage table is required
+ +  * @volt_data:	the voltage table for the particular vdd which is to be
+ +  *		populated by this API
+ +  *
+ +  * This API populates the voltage table associated with a VDD into the
+ +  * passed parameter pointer. Returns the count of distinct voltages
+ +  * supported by this vdd.
+ +  *
+ +  */
+ + void omap_voltage_get_volttable(struct voltagedomain *voltdm,
+ + 				struct omap_volt_data **volt_data)
+ + {
+ + 	if (!voltdm || IS_ERR(voltdm)) {
+ + 		pr_warning("%s: VDD specified does not exist!\n", __func__);
+ + 		return;
+ + 	}
+ + 
+ + 	*volt_data = voltdm->volt_data;
+ + }
+ + 
+ + /**
+ +  * omap_voltage_get_voltdata() - API to get the voltage table entry for a
+ +  *				particular voltage
+ +  * @voltdm:	pointer to the VDD whose voltage table has to be searched
+ +  * @volt:	the voltage to be searched in the voltage table
+ +  *
+ +  * This API searches through the voltage table for the required voltage
+ +  * domain and tries to find a matching entry for the passed voltage volt.
+ +  * If a matching entry is found volt_data is populated with that entry.
+ +  * This API searches only through the non-compensated voltages int the
+ +  * voltage table.
+ +  * Returns pointer to the voltage table entry corresponding to volt on
+ +  * success. Returns -ENODATA if no voltage table exisits for the passed voltage
+ +  * domain or if there is no matching entry.
+ +  */
+ + struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
+ + 						 unsigned long volt)
+ + {
+ + 	int i;
+ + 
+ + 	if (!voltdm || IS_ERR(voltdm)) {
+ + 		pr_warning("%s: VDD specified does not exist!\n", __func__);
+ + 		return ERR_PTR(-EINVAL);
+ + 	}
+ + 
+ + 	if (!voltdm->volt_data) {
+ + 		pr_warning("%s: voltage table does not exist for vdd_%s\n",
+ + 			__func__, voltdm->name);
+ + 		return ERR_PTR(-ENODATA);
+ + 	}
+ + 
+ + 	for (i = 0; voltdm->volt_data[i].volt_nominal != 0; i++) {
+ + 		if (voltdm->volt_data[i].volt_nominal == volt)
+ + 			return &voltdm->volt_data[i];
+ + 	}
+ + 
+ + 	pr_notice("%s: Unable to match the current voltage with the voltage"
+ + 		"table for vdd_%s\n", __func__, voltdm->name);
+ + 
+ + 	return ERR_PTR(-ENODATA);
+ + }
+ + 
+ + /**
+ +  * omap_voltage_register_pmic() - API to register PMIC specific data
+ +  * @voltdm:	pointer to the VDD for which the PMIC specific data is
+ +  *		to be registered
+ +  * @pmic:	the structure containing pmic info
+ +  *
+ +  * This API is to be called by the SOC/PMIC file to specify the
+ +  * pmic specific info as present in omap_voltdm_pmic structure.
+ +  */
+ + int omap_voltage_register_pmic(struct voltagedomain *voltdm,
+ + 			       struct omap_voltdm_pmic *pmic)
+ + {
+ + 	if (!voltdm || IS_ERR(voltdm)) {
+ + 		pr_warning("%s: VDD specified does not exist!\n", __func__);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	voltdm->pmic = pmic;
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * omap_change_voltscale_method() - API to change the voltage scaling method.
+ +  * @voltdm:	pointer to the VDD whose voltage scaling method
+ +  *		has to be changed.
+ +  * @voltscale_method:	the method to be used for voltage scaling.
+ +  *
+ +  * This API can be used by the board files to change the method of voltage
+ +  * scaling between vpforceupdate and vcbypass. The parameter values are
+ +  * defined in voltage.h
+ +  */
+ + void omap_change_voltscale_method(struct voltagedomain *voltdm,
+ + 				  int voltscale_method)
+ + {
+ + 	if (!voltdm || IS_ERR(voltdm)) {
+ + 		pr_warning("%s: VDD specified does not exist!\n", __func__);
+ + 		return;
+ + 	}
+ + 
+ + 	switch (voltscale_method) {
+ + 	case VOLTSCALE_VPFORCEUPDATE:
+ + 		voltdm->scale = omap_vp_forceupdate_scale;
+ + 		return;
+ + 	case VOLTSCALE_VCBYPASS:
+ + 		voltdm->scale = omap_vc_bypass_scale;
+ + 		return;
+ + 	default:
+ + 		pr_warning("%s: Trying to change the method of voltage scaling"
+ + 			"to an unsupported one!\n", __func__);
+ + 	}
+ + }
+ + 
+ + /**
+ +  * omap_voltage_late_init() - Init the various voltage parameters
+ +  *
+ +  * This API is to be called in the later stages of the
+ +  * system boot to init the voltage controller and
+ +  * voltage processors.
+ +  */
+ + int __init omap_voltage_late_init(void)
+ + {
+ + 	struct voltagedomain *voltdm;
+ + 
+ + 	if (list_empty(&voltdm_list)) {
+ + 		pr_err("%s: Voltage driver support not added\n",
+ + 			__func__);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	list_for_each_entry(voltdm, &voltdm_list, node) {
+ + 		struct clk *sys_ck;
+ + 
+ + 		if (!voltdm->scalable)
+ + 			continue;
+ + 
+ + 		sys_ck = clk_get(NULL, voltdm->sys_clk.name);
+ + 		if (IS_ERR(sys_ck)) {
+ + 			pr_warning("%s: Could not get sys clk.\n", __func__);
+ + 			return -EINVAL;
+ + 		}
+ + 		voltdm->sys_clk.rate = clk_get_rate(sys_ck);
+ + 		WARN_ON(!voltdm->sys_clk.rate);
+ + 		clk_put(sys_ck);
+ + 
+ + 		if (voltdm->vc) {
+ + 			voltdm->scale = omap_vc_bypass_scale;
+ + 			omap_vc_init_channel(voltdm);
+ + 		}
+ + 
+ + 		if (voltdm->vp) {
+ + 			voltdm->scale = omap_vp_forceupdate_scale;
+ + 			omap_vp_init(voltdm);
+ + 		}
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static struct voltagedomain *_voltdm_lookup(const char *name)
+ + {
+ + 	struct voltagedomain *voltdm, *temp_voltdm;
+ + 
+ + 	voltdm = NULL;
+ + 
+ + 	list_for_each_entry(temp_voltdm, &voltdm_list, node) {
+ + 		if (!strcmp(name, temp_voltdm->name)) {
+ + 			voltdm = temp_voltdm;
+ + 			break;
+ + 		}
+ + 	}
+ + 
+ + 	return voltdm;
+ + }
+ + 
+ + /**
+ +  * voltdm_add_pwrdm - add a powerdomain to a voltagedomain
+ +  * @voltdm: struct voltagedomain * to add the powerdomain to
+ +  * @pwrdm: struct powerdomain * to associate with a voltagedomain
+ +  *
+ +  * Associate the powerdomain @pwrdm with a voltagedomain @voltdm.  This
+ +  * enables the use of voltdm_for_each_pwrdm().  Returns -EINVAL if
+ +  * presented with invalid pointers; -ENOMEM if memory could not be allocated;
+ +  * or 0 upon success.
+ +  */
+ + int voltdm_add_pwrdm(struct voltagedomain *voltdm, struct powerdomain *pwrdm)
+ + {
+ + 	if (!voltdm || !pwrdm)
+ + 		return -EINVAL;
+ + 
+ + 	pr_debug("voltagedomain: associating powerdomain %s with voltagedomain "
+ + 		 "%s\n", pwrdm->name, voltdm->name);
+ + 
+ + 	list_add(&pwrdm->voltdm_node, &voltdm->pwrdm_list);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * voltdm_for_each_pwrdm - call function for each pwrdm in a voltdm
+ +  * @voltdm: struct voltagedomain * to iterate over
+ +  * @fn: callback function *
+ +  *
+ +  * Call the supplied function @fn for each powerdomain in the
+ +  * voltagedomain @voltdm.  Returns -EINVAL if presented with invalid
+ +  * pointers; or passes along the last return value of the callback
+ +  * function, which should be 0 for success or anything else to
+ +  * indicate failure.
+ +  */
+ + int voltdm_for_each_pwrdm(struct voltagedomain *voltdm,
+ + 			  int (*fn)(struct voltagedomain *voltdm,
+ + 				    struct powerdomain *pwrdm))
+ + {
+ + 	struct powerdomain *pwrdm;
+ + 	int ret = 0;
+ + 
+ + 	if (!fn)
+ + 		return -EINVAL;
+ + 
+ + 	list_for_each_entry(pwrdm, &voltdm->pwrdm_list, voltdm_node)
+ + 		ret = (*fn)(voltdm, pwrdm);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * voltdm_for_each - call function on each registered voltagedomain
+ +  * @fn: callback function *
+ +  *
+ +  * Call the supplied function @fn for each registered voltagedomain.
+ +  * The callback function @fn can return anything but 0 to bail out
+ +  * early from the iterator.  Returns the last return value of the
+ +  * callback function, which should be 0 for success or anything else
+ +  * to indicate failure; or -EINVAL if the function pointer is null.
+ +  */
+ + int voltdm_for_each(int (*fn)(struct voltagedomain *voltdm, void *user),
+ + 		    void *user)
+ + {
+ + 	struct voltagedomain *temp_voltdm;
+ + 	int ret = 0;
+ + 
+ + 	if (!fn)
+ + 		return -EINVAL;
+ + 
+ + 	list_for_each_entry(temp_voltdm, &voltdm_list, node) {
+ + 		ret = (*fn)(temp_voltdm, user);
+ + 		if (ret)
+ + 			break;
+ + 	}
+ + 
+ + 	return ret;
+ + }
+ + 
+ + static int _voltdm_register(struct voltagedomain *voltdm)
+ + {
+ + 	if (!voltdm || !voltdm->name)
+ + 		return -EINVAL;
+ + 
+ + 	INIT_LIST_HEAD(&voltdm->pwrdm_list);
+ + 	list_add(&voltdm->node, &voltdm_list);
+ + 
+ + 	pr_debug("voltagedomain: registered %s\n", voltdm->name);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * voltdm_lookup - look up a voltagedomain by name, return a pointer
+ +  * @name: name of voltagedomain
+ +  *
+ +  * Find a registered voltagedomain by its name @name.  Returns a pointer
+ +  * to the struct voltagedomain if found, or NULL otherwise.
+ +  */
+ + struct voltagedomain *voltdm_lookup(const char *name)
+ + {
+ + 	struct voltagedomain *voltdm ;
+ + 
+ + 	if (!name)
+ + 		return NULL;
+ + 
+ + 	voltdm = _voltdm_lookup(name);
+ + 
+ + 	return voltdm;
+ + }
+ + 
+ + /**
+ +  * voltdm_init - set up the voltagedomain layer
+ +  * @voltdm_list: array of struct voltagedomain pointers to register
+ +  *
+ +  * Loop through the array of voltagedomains @voltdm_list, registering all
+ +  * that are available on the current CPU. If voltdm_list is supplied
+ +  * and not null, all of the referenced voltagedomains will be
+ +  * registered.  No return value.
+ +  */
+ + void voltdm_init(struct voltagedomain **voltdms)
+ + {
+ + 	struct voltagedomain **v;
+ + 
+ + 	if (voltdms) {
+ + 		for (v = voltdms; *v; v++)
+ + 			_voltdm_register(*v);
+ + 	}
+ + }
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/voltagedomains33xx_data.c linux-3.2.1/arch/arm/mach-ckb_3352/voltagedomains33xx_data.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/voltagedomains33xx_data.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/voltagedomains33xx_data.c	2014-11-25 13:19:15.091037484 +0900
+ ***************
+ *** 0 ****
+ --- 1,43 ----
+ + /*
+ +  * AM33XX voltage domain data
+ +  *
+ +  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #include <linux/kernel.h>
+ + #include <linux/init.h>
+ + 
+ + #include "voltage.h"
+ + 
+ + static struct voltagedomain am33xx_voltdm_mpu = {
+ + 	.name		= "mpu",
+ + };
+ + 
+ + static struct voltagedomain am33xx_voltdm_core = {
+ + 	.name		= "core",
+ + };
+ + 
+ + static struct voltagedomain am33xx_voltdm_rtc = {
+ + 	.name		= "rtc",
+ + };
+ + 
+ + static struct voltagedomain *voltagedomains_am33xx[] __initdata = {
+ + 	&am33xx_voltdm_mpu,
+ + 	&am33xx_voltdm_core,
+ + 	&am33xx_voltdm_rtc,
+ + 	NULL,
+ + };
+ + 
+ + void __init am33xx_voltagedomains_init(void)
+ + {
+ + 	voltdm_init(voltagedomains_am33xx);
+ + }
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/voltage.h linux-3.2.1/arch/arm/mach-ckb_3352/voltage.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/voltage.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/voltage.h	2014-11-25 14:01:56.127444000 +0900
+ ***************
+ *** 0 ****
+ --- 1,170 ----
+ + /*
+ +  * OMAP Voltage Management Routines
+ +  *
+ +  * Author: Thara Gopinath	<thara@ti.com>
+ +  *
+ +  * Copyright (C) 2009 Texas Instruments, Inc.
+ +  * Thara Gopinath <thara@ti.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #ifndef __ARCH_ARM_MACH_OMAP2_VOLTAGE_H
+ + #define __ARCH_ARM_MACH_OMAP2_VOLTAGE_H
+ + 
+ + #include <linux/err.h>
+ + 
+ + #include "vc.h"
+ + #include "vp.h"
+ + 
+ + struct powerdomain;
+ + 
+ + /* XXX document */
+ + #define VOLTSCALE_VPFORCEUPDATE		1
+ + #define VOLTSCALE_VCBYPASS		2
+ + 
+ + /*
+ +  * OMAP3 GENERIC setup times. Revisit to see if these needs to be
+ +  * passed from board or PMIC file
+ +  */
+ + #define OMAP3_CLKSETUP		0xff
+ + #define OMAP3_VOLTOFFSET	0xff
+ + #define OMAP3_VOLTSETUP2	0xff
+ + 
+ + /**
+ +  * struct omap_vfsm_instance - per-voltage manager FSM register/bitfield
+ +  * data
+ +  * @voltsetup_mask: SETUP_TIME* bitmask in the PRM_VOLTSETUP* register
+ +  * @voltsetup_reg: register offset of PRM_VOLTSETUP from PRM base
+ +  *
+ +  * XXX What about VOLTOFFSET/VOLTCTRL?
+ +  */
+ + struct omap_vfsm_instance {
+ + 	u32 voltsetup_mask;
+ + 	u8 voltsetup_reg;
+ + };
+ + 
+ + /**
+ +  * struct voltagedomain - omap voltage domain global structure.
+ +  * @name: Name of the voltage domain which can be used as a unique identifier.
+ +  * @scalable: Whether or not this voltage domain is scalable
+ +  * @node: list_head linking all voltage domains
+ +  * @pwrdm_list: list_head linking all powerdomains in this voltagedomain
+ +  * @vc: pointer to VC channel associated with this voltagedomain
+ +  * @vp: pointer to VP associated with this voltagedomain
+ +  * @read: read a VC/VP register
+ +  * @write: write a VC/VP register
+ +  * @read: read-modify-write a VC/VP register
+ +  * @sys_clk: system clock name/frequency, used for various timing calculations
+ +  * @scale: function used to scale the voltage of the voltagedomain
+ +  * @nominal_volt: current nominal voltage for this voltage domain
+ +  * @volt_data: voltage table having the distinct voltages supported
+ +  *             by the domain and other associated per voltage data.
+ +  */
+ + struct voltagedomain {
+ + 	char *name;
+ + 	bool scalable;
+ + 	struct list_head node;
+ + 	struct list_head pwrdm_list;
+ + 	struct omap_vc_channel *vc;
+ + 	const struct omap_vfsm_instance *vfsm;
+ + 	struct omap_vp_instance *vp;
+ + 	struct omap_voltdm_pmic *pmic;
+ + 
+ + 	/* VC/VP register access functions: SoC specific */
+ + 	u32 (*read) (u8 offset);
+ + 	void (*write) (u32 val, u8 offset);
+ + 	u32 (*rmw)(u32 mask, u32 bits, u8 offset);
+ + 
+ + 	union {
+ + 		const char *name;
+ + 		u32 rate;
+ + 	} sys_clk;
+ + 
+ + 	int (*scale) (struct voltagedomain *voltdm,
+ + 		      unsigned long target_volt);
+ + 
+ + 	u32 nominal_volt;
+ + 	struct omap_volt_data *volt_data;
+ + };
+ + 
+ + /**
+ +  * struct omap_volt_data - Omap voltage specific data.
+ +  * @voltage_nominal:	The possible voltage value in uV
+ +  * @sr_efuse_offs:	The offset of the efuse register(from system
+ +  *			control module base address) from where to read
+ +  *			the n-target value for the smartreflex module.
+ +  * @sr_errminlimit:	Error min limit value for smartreflex. This value
+ +  *			differs at differnet opp and thus is linked
+ +  *			with voltage.
+ +  * @vp_errorgain:	Error gain value for the voltage processor. This
+ +  *			field also differs according to the voltage/opp.
+ +  */
+ + struct omap_volt_data {
+ + 	u32	volt_nominal;
+ + 	u32	sr_efuse_offs;
+ + 	u8	sr_errminlimit;
+ + 	u8	vp_errgain;
+ + };
+ + 
+ + /**
+ +  * struct omap_voltdm_pmic - PMIC specific data required by voltage driver.
+ +  * @slew_rate:	PMIC slew rate (in uv/us)
+ +  * @step_size:	PMIC voltage step size (in uv)
+ +  * @i2c_slave_addr: I2C slave address of PMIC
+ +  * @volt_reg_addr: voltage configuration register address
+ +  * @cmd_reg_addr: command (on, on-LP, ret, off) configuration register address
+ +  * @i2c_high_speed: whether VC uses I2C high-speed mode to PMIC
+ +  * @i2c_mcode: master code value for I2C high-speed preamble transmission
+ +  * @vsel_to_uv:	PMIC API to convert vsel value to actual voltage in uV.
+ +  * @uv_to_vsel:	PMIC API to convert voltage in uV to vsel value.
+ +  */
+ + struct omap_voltdm_pmic {
+ + 	int slew_rate;
+ + 	int step_size;
+ + 	u32 on_volt;
+ + 	u32 onlp_volt;
+ + 	u32 ret_volt;
+ + 	u32 off_volt;
+ + 	u16 volt_setup_time;
+ + 	u16 i2c_slave_addr;
+ + 	u16 volt_reg_addr;
+ + 	u16 cmd_reg_addr;
+ + 	u8 vp_erroroffset;
+ + 	u8 vp_vstepmin;
+ + 	u8 vp_vstepmax;
+ + 	u8 vp_vddmin;
+ + 	u8 vp_vddmax;
+ + 	u8 vp_timeout_us;
+ + 	bool i2c_high_speed;
+ + 	u8 i2c_mcode;
+ + 	unsigned long (*vsel_to_uv) (const u8 vsel);
+ + 	u8 (*uv_to_vsel) (unsigned long uV);
+ + };
+ + 
+ + void omap_voltage_get_volttable(struct voltagedomain *voltdm,
+ + 		struct omap_volt_data **volt_data);
+ + struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
+ + 		unsigned long volt);
+ + int omap_voltage_register_pmic(struct voltagedomain *voltdm,
+ + 			       struct omap_voltdm_pmic *pmic);
+ + void omap_change_voltscale_method(struct voltagedomain *voltdm,
+ + 		int voltscale_method);
+ + int omap_voltage_late_init(void);
+ + 
+ + extern void am33xx_voltagedomains_init(void);
+ + 
+ + struct voltagedomain *voltdm_lookup(const char *name);
+ + void voltdm_init(struct voltagedomain **voltdm_list);
+ + int voltdm_add_pwrdm(struct voltagedomain *voltdm, struct powerdomain *pwrdm);
+ + int voltdm_for_each(int (*fn)(struct voltagedomain *voltdm, void *user),
+ + 		    void *user);
+ + int voltdm_for_each_pwrdm(struct voltagedomain *voltdm,
+ + 			  int (*fn)(struct voltagedomain *voltdm,
+ + 				    struct powerdomain *pwrdm));
+ + int voltdm_scale(struct voltagedomain *voltdm, unsigned long target_volt);
+ + void voltdm_reset(struct voltagedomain *voltdm);
+ + unsigned long voltdm_get_voltage(struct voltagedomain *voltdm);
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/vp3xxx_data.c linux-3.2.1/arch/arm/mach-ckb_3352/vp3xxx_data.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/vp3xxx_data.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/vp3xxx_data.c	2014-11-25 13:19:15.096009681 +0900
+ ***************
+ *** 0 ****
+ --- 1,79 ----
+ + /*
+ +  * OMAP3 Voltage Processor (VP) data
+ +  *
+ +  * Copyright (C) 2007, 2010 Texas Instruments, Inc.
+ +  * Rajendra Nayak <rnayak@ti.com>
+ +  * Lesly A M <x0080970@ti.com>
+ +  * Thara Gopinath <thara@ti.com>
+ +  *
+ +  * Copyright (C) 2008, 2011 Nokia Corporation
+ +  * Kalle Jokiniemi
+ +  * Paul Walmsley
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #include <linux/io.h>
+ + #include <linux/err.h>
+ + #include <linux/init.h>
+ + 
+ + #include "common.h"
+ + 
+ + #include "prm-regbits-34xx.h"
+ + #include "voltage.h"
+ + 
+ + #include "vp.h"
+ + #include "prm2xxx_3xxx.h"
+ + 
+ + static const struct omap_vp_ops omap3_vp_ops = {
+ + 	.check_txdone = omap3_prm_vp_check_txdone,
+ + 	.clear_txdone = omap3_prm_vp_clear_txdone,
+ + };
+ + 
+ + /*
+ +  * VP data common to 34xx/36xx chips
+ +  * XXX This stuff presumably belongs in the vp3xxx.c or vp.c file.
+ +  */
+ + static const struct omap_vp_common omap3_vp_common = {
+ + 	.vpconfig_erroroffset_mask = OMAP3430_ERROROFFSET_MASK,
+ + 	.vpconfig_errorgain_mask = OMAP3430_ERRORGAIN_MASK,
+ + 	.vpconfig_initvoltage_mask = OMAP3430_INITVOLTAGE_MASK,
+ + 	.vpconfig_timeouten = OMAP3430_TIMEOUTEN_MASK,
+ + 	.vpconfig_initvdd = OMAP3430_INITVDD_MASK,
+ + 	.vpconfig_forceupdate = OMAP3430_FORCEUPDATE_MASK,
+ + 	.vpconfig_vpenable = OMAP3430_VPENABLE_MASK,
+ + 	.vstepmin_smpswaittimemin_shift = OMAP3430_SMPSWAITTIMEMIN_SHIFT,
+ + 	.vstepmax_smpswaittimemax_shift = OMAP3430_SMPSWAITTIMEMAX_SHIFT,
+ + 	.vstepmin_stepmin_shift = OMAP3430_VSTEPMIN_SHIFT,
+ + 	.vstepmax_stepmax_shift = OMAP3430_VSTEPMAX_SHIFT,
+ + 	.vlimitto_vddmin_shift = OMAP3430_VDDMIN_SHIFT,
+ + 	.vlimitto_vddmax_shift = OMAP3430_VDDMAX_SHIFT,
+ + 	.vlimitto_timeout_shift = OMAP3430_TIMEOUT_SHIFT,
+ + 	.vpvoltage_mask = OMAP3430_VPVOLTAGE_MASK,
+ + 
+ + 	.ops = &omap3_vp_ops,
+ + };
+ + 
+ + struct omap_vp_instance omap3_vp_mpu = {
+ + 	.id = OMAP3_VP_VDD_MPU_ID,
+ + 	.common = &omap3_vp_common,
+ + 	.vpconfig = OMAP3_PRM_VP1_CONFIG_OFFSET,
+ + 	.vstepmin = OMAP3_PRM_VP1_VSTEPMIN_OFFSET,
+ + 	.vstepmax = OMAP3_PRM_VP1_VSTEPMAX_OFFSET,
+ + 	.vlimitto = OMAP3_PRM_VP1_VLIMITTO_OFFSET,
+ + 	.vstatus = OMAP3_PRM_VP1_STATUS_OFFSET,
+ + 	.voltage = OMAP3_PRM_VP1_VOLTAGE_OFFSET,
+ + };
+ + 
+ + struct omap_vp_instance omap3_vp_core = {
+ + 	.id = OMAP3_VP_VDD_CORE_ID,
+ + 	.common = &omap3_vp_common,
+ + 	.vpconfig = OMAP3_PRM_VP2_CONFIG_OFFSET,
+ + 	.vstepmin = OMAP3_PRM_VP2_VSTEPMIN_OFFSET,
+ + 	.vstepmax = OMAP3_PRM_VP2_VSTEPMAX_OFFSET,
+ + 	.vlimitto = OMAP3_PRM_VP2_VLIMITTO_OFFSET,
+ + 	.vstatus = OMAP3_PRM_VP2_STATUS_OFFSET,
+ + 	.voltage = OMAP3_PRM_VP2_VOLTAGE_OFFSET,
+ + };
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/vp.c linux-3.2.1/arch/arm/mach-ckb_3352/vp.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/vp.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/vp.c	2014-11-25 13:19:15.096009681 +0900
+ ***************
+ *** 0 ****
+ --- 1,284 ----
+ + #include <linux/kernel.h>
+ + #include <linux/init.h>
+ + 
+ + #include "common.h"
+ + 
+ + #include "voltage.h"
+ + #include "vp.h"
+ + #include "prm-regbits-34xx.h"
+ + #include "prm-regbits-44xx.h"
+ + //#include "prm44xx.h"
+ + 
+ + static u32 _vp_set_init_voltage(struct voltagedomain *voltdm, u32 volt)
+ + {
+ + 	struct omap_vp_instance *vp = voltdm->vp;
+ + 	u32 vpconfig;
+ + 	char vsel;
+ + 
+ + 	vsel = voltdm->pmic->uv_to_vsel(volt);
+ + 
+ + 	vpconfig = voltdm->read(vp->vpconfig);
+ + 	vpconfig &= ~(vp->common->vpconfig_initvoltage_mask |
+ + 		      vp->common->vpconfig_forceupdate |
+ + 		      vp->common->vpconfig_initvdd);
+ + 	vpconfig |= vsel << __ffs(vp->common->vpconfig_initvoltage_mask);
+ + 	voltdm->write(vpconfig, vp->vpconfig);
+ + 
+ + 	/* Trigger initVDD value copy to voltage processor */
+ + 	voltdm->write((vpconfig | vp->common->vpconfig_initvdd),
+ + 		       vp->vpconfig);
+ + 
+ + 	/* Clear initVDD copy trigger bit */
+ + 	voltdm->write(vpconfig, vp->vpconfig);
+ + 
+ + 	return vpconfig;
+ + }
+ + 
+ + /* Generic voltage init functions */
+ + void __init omap_vp_init(struct voltagedomain *voltdm)
+ + {
+ + 	struct omap_vp_instance *vp = voltdm->vp;
+ + 	u32 val, sys_clk_rate, timeout, waittime;
+ + 	u32 vddmin, vddmax, vstepmin, vstepmax;
+ + 
+ + 	if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) {
+ + 		pr_err("%s: missing PMIC for vdd_%s.\n",
+ + 		       __func__, voltdm->name);
+ + 		return;
+ + 	}
+ + 
+ + 	if (!voltdm->read || !voltdm->write) {
+ + 		pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+ + 			__func__, voltdm->name);
+ + 		return;
+ + 	}
+ + 
+ + 	vp->enabled = false;
+ + 
+ + 	/* Divide to avoid overflow */
+ + 	sys_clk_rate = voltdm->sys_clk.rate / 1000;
+ + 
+ + 	timeout = (sys_clk_rate * voltdm->pmic->vp_timeout_us) / 1000;
+ + 	vddmin = voltdm->pmic->vp_vddmin;
+ + 	vddmax = voltdm->pmic->vp_vddmax;
+ + 
+ + 	waittime = ((voltdm->pmic->step_size / voltdm->pmic->slew_rate) *
+ + 		    sys_clk_rate) / 1000;
+ + 	vstepmin = voltdm->pmic->vp_vstepmin;
+ + 	vstepmax = voltdm->pmic->vp_vstepmax;
+ + 
+ + 	/*
+ + 	 * VP_CONFIG: error gain is not set here, it will be updated
+ + 	 * on each scale, based on OPP.
+ + 	 */
+ + 	val = (voltdm->pmic->vp_erroroffset <<
+ + 	       __ffs(voltdm->vp->common->vpconfig_erroroffset_mask)) |
+ + 		vp->common->vpconfig_timeouten;
+ + 	voltdm->write(val, vp->vpconfig);
+ + 
+ + 	/* VSTEPMIN */
+ + 	val = (waittime << vp->common->vstepmin_smpswaittimemin_shift) |
+ + 		(vstepmin <<  vp->common->vstepmin_stepmin_shift);
+ + 	voltdm->write(val, vp->vstepmin);
+ + 
+ + 	/* VSTEPMAX */
+ + 	val = (vstepmax << vp->common->vstepmax_stepmax_shift) |
+ + 		(waittime << vp->common->vstepmax_smpswaittimemax_shift);
+ + 	voltdm->write(val, vp->vstepmax);
+ + 
+ + 	/* VLIMITTO */
+ + 	val = (vddmax << vp->common->vlimitto_vddmax_shift) |
+ + 		(vddmin << vp->common->vlimitto_vddmin_shift) |
+ + 		(timeout <<  vp->common->vlimitto_timeout_shift);
+ + 	voltdm->write(val, vp->vlimitto);
+ + }
+ + 
+ + int omap_vp_update_errorgain(struct voltagedomain *voltdm,
+ + 			     unsigned long target_volt)
+ + {
+ + 	struct omap_volt_data *volt_data;
+ + 
+ + 	if (!voltdm->vp)
+ + 		return -EINVAL;
+ + 
+ + 	/* Get volt_data corresponding to target_volt */
+ + 	volt_data = omap_voltage_get_voltdata(voltdm, target_volt);
+ + 	if (IS_ERR(volt_data))
+ + 		return -EINVAL;
+ + 
+ + 	/* Setting vp errorgain based on the voltage */
+ + 	voltdm->rmw(voltdm->vp->common->vpconfig_errorgain_mask,
+ + 		    volt_data->vp_errgain <<
+ + 		    __ffs(voltdm->vp->common->vpconfig_errorgain_mask),
+ + 		    voltdm->vp->vpconfig);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /* VP force update method of voltage scaling */
+ + int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
+ + 			      unsigned long target_volt)
+ + {
+ + 	struct omap_vp_instance *vp = voltdm->vp;
+ + 	u32 vpconfig;
+ + 	u8 target_vsel, current_vsel;
+ + 	int ret, timeout = 0;
+ + 
+ + 	ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, &current_vsel);
+ + 	if (ret)
+ + 		return ret;
+ + 
+ + 	/*
+ + 	 * Clear all pending TransactionDone interrupt/status. Typical latency
+ + 	 * is <3us
+ + 	 */
+ + 	while (timeout++ < VP_TRANXDONE_TIMEOUT) {
+ + 		vp->common->ops->clear_txdone(vp->id);
+ + 		if (!vp->common->ops->check_txdone(vp->id))
+ + 			break;
+ + 		udelay(1);
+ + 	}
+ + 	if (timeout >= VP_TRANXDONE_TIMEOUT) {
+ + 		pr_warning("%s: vdd_%s TRANXDONE timeout exceeded."
+ + 			"Voltage change aborted", __func__, voltdm->name);
+ + 		return -ETIMEDOUT;
+ + 	}
+ + 
+ + 	vpconfig = _vp_set_init_voltage(voltdm, target_volt);
+ + 
+ + 	/* Force update of voltage */
+ + 	voltdm->write(vpconfig | vp->common->vpconfig_forceupdate,
+ + 		      voltdm->vp->vpconfig);
+ + 
+ + 	/*
+ + 	 * Wait for TransactionDone. Typical latency is <200us.
+ + 	 * Depends on SMPSWAITTIMEMIN/MAX and voltage change
+ + 	 */
+ + 	timeout = 0;
+ + 	omap_test_timeout(vp->common->ops->check_txdone(vp->id),
+ + 			  VP_TRANXDONE_TIMEOUT, timeout);
+ + 	if (timeout >= VP_TRANXDONE_TIMEOUT)
+ + 		pr_err("%s: vdd_%s TRANXDONE timeout exceeded."
+ + 			"TRANXDONE never got set after the voltage update\n",
+ + 			__func__, voltdm->name);
+ + 
+ + 	omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel);
+ + 
+ + 	/*
+ + 	 * Disable TransactionDone interrupt , clear all status, clear
+ + 	 * control registers
+ + 	 */
+ + 	timeout = 0;
+ + 	while (timeout++ < VP_TRANXDONE_TIMEOUT) {
+ + 		vp->common->ops->clear_txdone(vp->id);
+ + 		if (!vp->common->ops->check_txdone(vp->id))
+ + 			break;
+ + 		udelay(1);
+ + 	}
+ + 
+ + 	if (timeout >= VP_TRANXDONE_TIMEOUT)
+ + 		pr_warning("%s: vdd_%s TRANXDONE timeout exceeded while trying"
+ + 			"to clear the TRANXDONE status\n",
+ + 			__func__, voltdm->name);
+ + 
+ + 	/* Clear force bit */
+ + 	voltdm->write(vpconfig, vp->vpconfig);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * omap_vp_enable() - API to enable a particular VP
+ +  * @voltdm:	pointer to the VDD whose VP is to be enabled.
+ +  *
+ +  * This API enables a particular voltage processor. Needed by the smartreflex
+ +  * class drivers.
+ +  */
+ + void omap_vp_enable(struct voltagedomain *voltdm)
+ + {
+ + 	struct omap_vp_instance *vp;
+ + 	u32 vpconfig, volt;
+ + 
+ + 	if (!voltdm || IS_ERR(voltdm)) {
+ + 		pr_warning("%s: VDD specified does not exist!\n", __func__);
+ + 		return;
+ + 	}
+ + 
+ + 	vp = voltdm->vp;
+ + 	if (!voltdm->read || !voltdm->write) {
+ + 		pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+ + 			__func__, voltdm->name);
+ + 		return;
+ + 	}
+ + 
+ + 	/* If VP is already enabled, do nothing. Return */
+ + 	if (vp->enabled)
+ + 		return;
+ + 
+ + 	volt = voltdm_get_voltage(voltdm);
+ + 	if (!volt) {
+ + 		pr_warning("%s: unable to find current voltage for %s\n",
+ + 			   __func__, voltdm->name);
+ + 		return;
+ + 	}
+ + 
+ + 	vpconfig = _vp_set_init_voltage(voltdm, volt);
+ + 
+ + 	/* Enable VP */
+ + 	vpconfig |= vp->common->vpconfig_vpenable;
+ + 	voltdm->write(vpconfig, vp->vpconfig);
+ + 
+ + 	vp->enabled = true;
+ + }
+ + 
+ + /**
+ +  * omap_vp_disable() - API to disable a particular VP
+ +  * @voltdm:	pointer to the VDD whose VP is to be disabled.
+ +  *
+ +  * This API disables a particular voltage processor. Needed by the smartreflex
+ +  * class drivers.
+ +  */
+ + void omap_vp_disable(struct voltagedomain *voltdm)
+ + {
+ + 	struct omap_vp_instance *vp;
+ + 	u32 vpconfig;
+ + 	int timeout;
+ + 
+ + 	if (!voltdm || IS_ERR(voltdm)) {
+ + 		pr_warning("%s: VDD specified does not exist!\n", __func__);
+ + 		return;
+ + 	}
+ + 
+ + 	vp = voltdm->vp;
+ + 	if (!voltdm->read || !voltdm->write) {
+ + 		pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+ + 			__func__, voltdm->name);
+ + 		return;
+ + 	}
+ + 
+ + 	/* If VP is already disabled, do nothing. Return */
+ + 	if (!vp->enabled) {
+ + 		pr_warning("%s: Trying to disable VP for vdd_%s when"
+ + 			"it is already disabled\n", __func__, voltdm->name);
+ + 		return;
+ + 	}
+ + 
+ + 	/* Disable VP */
+ + 	vpconfig = voltdm->read(vp->vpconfig);
+ + 	vpconfig &= ~vp->common->vpconfig_vpenable;
+ + 	voltdm->write(vpconfig, vp->vpconfig);
+ + 
+ + 	/*
+ + 	 * Wait for VP idle Typical latency is <2us. Maximum latency is ~100us
+ + 	 */
+ + 	omap_test_timeout((voltdm->read(vp->vstatus)),
+ + 			  VP_IDLE_TIMEOUT, timeout);
+ + 
+ + 	if (timeout >= VP_IDLE_TIMEOUT)
+ + 		pr_warning("%s: vdd_%s idle timedout\n",
+ + 			__func__, voltdm->name);
+ + 
+ + 	vp->enabled = false;
+ + 
+ + 	return;
+ + }
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/vp.h linux-3.2.1/arch/arm/mach-ckb_3352/vp.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/vp.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/vp.h	2014-11-25 13:19:15.096009681 +0900
+ ***************
+ *** 0 ****
+ --- 1,128 ----
+ + /*
+ +  * OMAP3/4 Voltage Processor (VP) structure and macro definitions
+ +  *
+ +  * Copyright (C) 2007, 2010 Texas Instruments, Inc.
+ +  * Rajendra Nayak <rnayak@ti.com>
+ +  * Lesly A M <x0080970@ti.com>
+ +  * Thara Gopinath <thara@ti.com>
+ +  *
+ +  * Copyright (C) 2008, 2011 Nokia Corporation
+ +  * Kalle Jokiniemi
+ +  * Paul Walmsley
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License version
+ +  * 2 as published by the Free Software Foundation.
+ +  */
+ + #ifndef __ARCH_ARM_MACH_OMAP2_VP_H
+ + #define __ARCH_ARM_MACH_OMAP2_VP_H
+ + 
+ + #include <linux/kernel.h>
+ + 
+ + struct voltagedomain;
+ + 
+ + /*
+ +  * Voltage Processor (VP) identifiers
+ +  */
+ + #define OMAP3_VP_VDD_MPU_ID 0
+ + #define OMAP3_VP_VDD_CORE_ID 1
+ + #define OMAP4_VP_VDD_CORE_ID 0
+ + #define OMAP4_VP_VDD_IVA_ID 1
+ + #define OMAP4_VP_VDD_MPU_ID 2
+ + 
+ + /* XXX document */
+ + #define VP_IDLE_TIMEOUT		200
+ + #define VP_TRANXDONE_TIMEOUT	300
+ + 
+ + /**
+ +  * struct omap_vp_ops - per-VP operations
+ +  * @check_txdone: check for VP transaction done
+ +  * @clear_txdone: clear VP transaction done status
+ +  */
+ + struct omap_vp_ops {
+ + 	u32 (*check_txdone)(u8 vp_id);
+ + 	void (*clear_txdone)(u8 vp_id);
+ + };
+ + 
+ + /**
+ +  * struct omap_vp_common - register data common to all VDDs
+ +  * @vpconfig_erroroffset_mask: ERROROFFSET bitmask in the PRM_VP*_CONFIG reg
+ +  * @vpconfig_errorgain_mask: ERRORGAIN bitmask in the PRM_VP*_CONFIG reg
+ +  * @vpconfig_initvoltage_mask: INITVOLTAGE bitmask in the PRM_VP*_CONFIG reg
+ +  * @vpconfig_timeouten: TIMEOUT bitmask in the PRM_VP*_CONFIG reg
+ +  * @vpconfig_initvdd: INITVDD bitmask in the PRM_VP*_CONFIG reg
+ +  * @vpconfig_forceupdate: FORCEUPDATE bitmask in the PRM_VP*_CONFIG reg
+ +  * @vpconfig_vpenable: VPENABLE bitmask in the PRM_VP*_CONFIG reg
+ +  * @vpconfig_erroroffset_shift: ERROROFFSET field shift in PRM_VP*_CONFIG reg
+ +  * @vpconfig_errorgain_shift: ERRORGAIN field shift in PRM_VP*_CONFIG reg
+ +  * @vpconfig_initvoltage_shift: INITVOLTAGE field shift in PRM_VP*_CONFIG reg
+ +  * @vstepmin_stepmin_shift: VSTEPMIN field shift in the PRM_VP*_VSTEPMIN reg
+ +  * @vstepmin_smpswaittimemin_shift: SMPSWAITTIMEMIN field shift in PRM_VP*_VSTEPMIN reg
+ +  * @vstepmax_stepmax_shift: VSTEPMAX field shift in the PRM_VP*_VSTEPMAX reg
+ +  * @vstepmax_smpswaittimemax_shift: SMPSWAITTIMEMAX field shift in PRM_VP*_VSTEPMAX reg
+ +  * @vlimitto_vddmin_shift: VDDMIN field shift in PRM_VP*_VLIMITTO reg
+ +  * @vlimitto_vddmax_shift: VDDMAX field shift in PRM_VP*_VLIMITTO reg
+ +  * @vlimitto_timeout_shift: TIMEOUT field shift in PRM_VP*_VLIMITTO reg
+ +  * @vpvoltage_mask: VPVOLTAGE field mask in PRM_VP*_VOLTAGE reg
+ +  */
+ + struct omap_vp_common {
+ + 	u32 vpconfig_erroroffset_mask;
+ + 	u32 vpconfig_errorgain_mask;
+ + 	u32 vpconfig_initvoltage_mask;
+ + 	u8 vpconfig_timeouten;
+ + 	u8 vpconfig_initvdd;
+ + 	u8 vpconfig_forceupdate;
+ + 	u8 vpconfig_vpenable;
+ + 	u8 vstepmin_stepmin_shift;
+ + 	u8 vstepmin_smpswaittimemin_shift;
+ + 	u8 vstepmax_stepmax_shift;
+ + 	u8 vstepmax_smpswaittimemax_shift;
+ + 	u8 vlimitto_vddmin_shift;
+ + 	u8 vlimitto_vddmax_shift;
+ + 	u8 vlimitto_timeout_shift;
+ + 	u8 vpvoltage_mask;
+ + 
+ + 	const struct omap_vp_ops *ops;
+ + };
+ + 
+ + /**
+ +  * struct omap_vp_instance - VP register offsets (per-VDD)
+ +  * @common: pointer to struct omap_vp_common * for this SoC
+ +  * @vpconfig: PRM_VP*_CONFIG reg offset from PRM start
+ +  * @vstepmin: PRM_VP*_VSTEPMIN reg offset from PRM start
+ +  * @vlimitto: PRM_VP*_VLIMITTO reg offset from PRM start
+ +  * @vstatus: PRM_VP*_VSTATUS reg offset from PRM start
+ +  * @voltage: PRM_VP*_VOLTAGE reg offset from PRM start
+ +  * @id: Unique identifier for VP instance.
+ +  * @enabled: flag to keep track of whether vp is enabled or not
+ +  *
+ +  * XXX vp_common is probably not needed since it is per-SoC
+ +  */
+ + struct omap_vp_instance {
+ + 	const struct omap_vp_common *common;
+ + 	u8 vpconfig;
+ + 	u8 vstepmin;
+ + 	u8 vstepmax;
+ + 	u8 vlimitto;
+ + 	u8 vstatus;
+ + 	u8 voltage;
+ + 	u8 id;
+ + 	bool enabled;
+ + };
+ + 
+ + extern struct omap_vp_instance omap3_vp_mpu;
+ + extern struct omap_vp_instance omap3_vp_core;
+ + 
+ + extern struct omap_vp_instance omap4_vp_mpu;
+ + extern struct omap_vp_instance omap4_vp_iva;
+ + extern struct omap_vp_instance omap4_vp_core;
+ + 
+ + void omap_vp_init(struct voltagedomain *voltdm);
+ + void omap_vp_enable(struct voltagedomain *voltdm);
+ + void omap_vp_disable(struct voltagedomain *voltdm);
+ + int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
+ + 			      unsigned long target_volt);
+ + int omap_vp_update_errorgain(struct voltagedomain *voltdm,
+ + 			     unsigned long target_volt);
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/wd_timer.c linux-3.2.1/arch/arm/mach-ckb_3352/wd_timer.c
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/wd_timer.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/wd_timer.c	2014-11-25 13:19:15.099021935 +0900
+ ***************
+ *** 0 ****
+ --- 1,56 ----
+ + /*
+ +  * OMAP2+ MPU WD_TIMER-specific code
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; either version 2 of the License, or
+ +  * (at your option) any later version.
+ +  */
+ + 
+ + #include <linux/kernel.h>
+ + #include <linux/io.h>
+ + #include <linux/err.h>
+ + 
+ + #include <plat/omap_hwmod.h>
+ + 
+ + #include "wd_timer.h"
+ + 
+ + /*
+ +  * In order to avoid any assumptions from bootloader regarding WDT
+ +  * settings, WDT module is reset during init. This enables the watchdog
+ +  * timer. Hence it is required to disable the watchdog after the WDT reset
+ +  * during init. Otherwise the system would reboot as per the default
+ +  * watchdog timer registers settings.
+ +  */
+ + #define OMAP_WDT_WPS		0x34
+ + #define OMAP_WDT_SPR		0x48
+ + 
+ + 
+ + int omap2_wd_timer_disable(struct omap_hwmod *oh)
+ + {
+ + 	void __iomem *base;
+ + 
+ + 	if (!oh) {
+ + 		pr_err("%s: Could not look up wdtimer_hwmod\n", __func__);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	base = omap_hwmod_get_mpu_rt_va(oh);
+ + 	if (!base) {
+ + 		pr_err("%s: Could not get the base address for %s\n",
+ + 				oh->name, __func__);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	/* sequence required to disable watchdog */
+ + 	__raw_writel(0xAAAA, base + OMAP_WDT_SPR);
+ + 	while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
+ + 		cpu_relax();
+ + 
+ + 	__raw_writel(0x5555, base + OMAP_WDT_SPR);
+ + 	while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
+ + 		cpu_relax();
+ + 
+ + 	return 0;
+ + }
+ + 
+ diff -crN linux-3.2.1_o/arch/arm/mach-ckb_3352/wd_timer.h linux-3.2.1/arch/arm/mach-ckb_3352/wd_timer.h
+ *** linux-3.2.1_o/arch/arm/mach-ckb_3352/wd_timer.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/mach-ckb_3352/wd_timer.h	2014-11-25 13:19:15.099021935 +0900
+ ***************
+ *** 0 ****
+ --- 1,17 ----
+ + /*
+ +  * OMAP2+ MPU WD_TIMER-specific function prototypes
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; either version 2 of the License, or
+ +  * (at your option) any later version.
+ +  */
+ + 
+ + #ifndef __ARCH_ARM_MACH_OMAP2_WD_TIMER_H
+ + #define __ARCH_ARM_MACH_OMAP2_WD_TIMER_H
+ + 
+ + #include <plat/omap_hwmod.h>
+ + 
+ + extern int omap2_wd_timer_disable(struct omap_hwmod *oh);
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/Makefile linux-3.2.1/arch/arm/Makefile
+ *** linux-3.2.1_o/arch/arm/Makefile	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/arch/arm/Makefile	2014-11-25 13:19:15.099021935 +0900
+ ***************
+ *** 136,141 ****
+ --- 136,142 ----
+   # by CONFIG_* macro name.
+   machine-$(CONFIG_ARCH_AT91)		:= at91
+   machine-$(CONFIG_ARCH_BCMRING)		:= bcmring
+ + machine-$(CONFIG_ARCH_CKB)			:= ckb_3352
+   machine-$(CONFIG_ARCH_CLPS711X)		:= clps711x
+   machine-$(CONFIG_ARCH_CNS3XXX)		:= cns3xxx
+   machine-$(CONFIG_ARCH_DAVINCI)		:= davinci
+ ***************
+ *** 201,206 ****
+ --- 202,208 ----
+   
+   # Platform directory name.  This list is sorted alphanumerically
+   # by CONFIG_* macro name.
+ + plat-$(CONFIG_ARCH_CKB)		:= ckb
+   plat-$(CONFIG_ARCH_MXC)		:= mxc
+   plat-$(CONFIG_ARCH_OMAP)	:= omap
+   plat-$(CONFIG_ARCH_S3C64XX)	:= samsung
+ diff -crN linux-3.2.1_o/arch/arm/mm/idmap.c linux-3.2.1/arch/arm/mm/idmap.c
+ *** linux-3.2.1_o/arch/arm/mm/idmap.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/arch/arm/mm/idmap.c	2014-11-25 13:19:15.140007708 +0900
+ ***************
+ *** 78,84 ****
+    * the user-mode pages.  This will then ensure that we have predictable
+    * results when turning the mmu off
+    */
+ ! void setup_mm_for_reboot(char mode)
+   {
+   	/*
+   	 * We need to access to user-mode page tables here. For kernel threads
+ --- 78,84 ----
+    * the user-mode pages.  This will then ensure that we have predictable
+    * results when turning the mmu off
+    */
+ ! void setup_mm_for_reboot(void)
+   {
+   	/*
+   	 * We need to access to user-mode page tables here. For kernel threads
+ diff -crN linux-3.2.1_o/arch/arm/mm/init.c linux-3.2.1/arch/arm/mm/init.c
+ *** linux-3.2.1_o/arch/arm/mm/init.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/arch/arm/mm/init.c	2014-11-25 13:19:15.140007708 +0900
+ ***************
+ *** 35,40 ****
+ --- 35,44 ----
+   
+   #include "mm.h"
+   
+ + #ifdef CONFIG_MACH_CKB_3352
+ + #include <mach/ckb_3352_mem.h>
+ + #endif
+ + 
+   static unsigned long phys_initrd_start __initdata = 0;
+   static unsigned long phys_initrd_size __initdata = 0;
+   
+ ***************
+ *** 692,697 ****
+ --- 696,709 ----
+   			MLK_ROUNDUP(_sdata, _edata),
+   			MLK_ROUNDUP(__bss_start, __bss_stop));
+   
+ + #ifdef CONFIG_MACH_CKB_3352
+ + 	if(FB_DATA_ADDRESS !=0)
+ + 	{
+ + 		printk(KERN_NOTICE "   FB vaddr : 0x%08lx - 0x%08lx   (%4ld MB)\n", 
+ + 					MLM(FB_DATA_VADDRESS, FB_DATA_VADDRESS+FB_MAP_SIZE));
+ + 	}
+ + #endif
+ + 
+   #undef MLK
+   #undef MLM
+   #undef MLK_ROUNDUP
+ diff -crN linux-3.2.1_o/arch/arm/mm/nommu.c linux-3.2.1/arch/arm/mm/nommu.c
+ *** linux-3.2.1_o/arch/arm/mm/nommu.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/arch/arm/mm/nommu.c	2014-11-25 13:19:15.143717539 +0900
+ ***************
+ *** 29,34 ****
+ --- 29,36 ----
+   
+   void __init sanity_check_meminfo(void)
+   {
+ + 	phys_addr_t end = bank_phys_end(&meminfo.bank[meminfo.nr_banks - 1]);
+ + 	high_memory = __va(end - 1) + 1;
+   }
+   
+   /*
+ ***************
+ *** 43,49 ****
+   /*
+    * We don't need to do anything here for nommu machines.
+    */
+ ! void setup_mm_for_reboot(char mode)
+   {
+   }
+   
+ --- 45,51 ----
+   /*
+    * We don't need to do anything here for nommu machines.
+    */
+ ! void setup_mm_for_reboot(void)
+   {
+   }
+   
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/clock.c linux-3.2.1/arch/arm/plat-ckb/clock.c
+ *** linux-3.2.1_o/arch/arm/plat-ckb/clock.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/clock.c	2014-11-25 13:19:15.143717539 +0900
+ ***************
+ *** 0 ****
+ --- 1,595 ----
+ + /*
+ +  *  linux/arch/arm/plat-omap/clock.c
+ +  *
+ +  *  Copyright (C) 2004 - 2008 Nokia corporation
+ +  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
+ +  *
+ +  *  Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + #include <linux/kernel.h>
+ + #include <linux/init.h>
+ + #include <linux/list.h>
+ + #include <linux/errno.h>
+ + #include <linux/export.h>
+ + #include <linux/err.h>
+ + #include <linux/string.h>
+ + #include <linux/clk.h>
+ + #include <linux/mutex.h>
+ + #include <linux/cpufreq.h>
+ + #include <linux/debugfs.h>
+ + #include <linux/io.h>
+ + 
+ + #include <plat/clock.h>
+ + 
+ + static LIST_HEAD(clocks);
+ + static DEFINE_MUTEX(clocks_mutex);
+ + static DEFINE_SPINLOCK(clockfw_lock);
+ + 
+ + static struct clk_functions *arch_clock;
+ + 
+ + /*
+ +  * Standard clock functions defined in include/linux/clk.h
+ +  */
+ + 
+ + int clk_enable(struct clk *clk)
+ + {
+ + 	unsigned long flags;
+ + 	int ret;
+ + 
+ + 	if (clk == NULL || IS_ERR(clk))
+ + 		return -EINVAL;
+ + 
+ + 	if (!arch_clock || !arch_clock->clk_enable)
+ + 		return -EINVAL;
+ + 
+ + 	spin_lock_irqsave(&clockfw_lock, flags);
+ + 	ret = arch_clock->clk_enable(clk);
+ + 	spin_unlock_irqrestore(&clockfw_lock, flags);
+ + 
+ + 	return ret;
+ + }
+ + EXPORT_SYMBOL(clk_enable);
+ + 
+ + void clk_disable(struct clk *clk)
+ + {
+ + 	unsigned long flags;
+ + 
+ + 	if (clk == NULL || IS_ERR(clk))
+ + 		return;
+ + 
+ + 	if (!arch_clock || !arch_clock->clk_disable)
+ + 		return;
+ + 
+ + 	spin_lock_irqsave(&clockfw_lock, flags);
+ + 	if (clk->usecount == 0) {
+ + 		pr_err("Trying disable clock %s with 0 usecount\n",
+ + 		       clk->name);
+ + 		WARN_ON(1);
+ + 		goto out;
+ + 	}
+ + 
+ + 	arch_clock->clk_disable(clk);
+ + 
+ + out:
+ + 	spin_unlock_irqrestore(&clockfw_lock, flags);
+ + }
+ + EXPORT_SYMBOL(clk_disable);
+ + 
+ + unsigned long clk_get_rate(struct clk *clk)
+ + {
+ + 	unsigned long flags;
+ + 	unsigned long ret;
+ + 
+ + 	if (clk == NULL || IS_ERR(clk))
+ + 		return 0;
+ + 
+ + 	spin_lock_irqsave(&clockfw_lock, flags);
+ + 	ret = clk->rate;
+ + 	spin_unlock_irqrestore(&clockfw_lock, flags);
+ + 
+ + 	return ret;
+ + }
+ + EXPORT_SYMBOL(clk_get_rate);
+ + 
+ + /*
+ +  * Optional clock functions defined in include/linux/clk.h
+ +  */
+ + 
+ + long clk_round_rate(struct clk *clk, unsigned long rate)
+ + {
+ + 	unsigned long flags;
+ + 	long ret;
+ + 
+ + 	if (clk == NULL || IS_ERR(clk))
+ + 		return 0;
+ + 
+ + 	if (!arch_clock || !arch_clock->clk_round_rate)
+ + 		return 0;
+ + 
+ + 	spin_lock_irqsave(&clockfw_lock, flags);
+ + 	ret = arch_clock->clk_round_rate(clk, rate);
+ + 	spin_unlock_irqrestore(&clockfw_lock, flags);
+ + 
+ + 	return ret;
+ + }
+ + EXPORT_SYMBOL(clk_round_rate);
+ + 
+ + int clk_set_rate(struct clk *clk, unsigned long rate)
+ + {
+ + 	unsigned long flags;
+ + 	int ret = -EINVAL;
+ + 
+ + 	if (clk == NULL || IS_ERR(clk))
+ + 		return ret;
+ + 
+ + 	if (!arch_clock || !arch_clock->clk_set_rate)
+ + 		return ret;
+ + 
+ + 	spin_lock_irqsave(&clockfw_lock, flags);
+ + 	ret = arch_clock->clk_set_rate(clk, rate);
+ + 	if (ret == 0)
+ + 		propagate_rate(clk);
+ + 	spin_unlock_irqrestore(&clockfw_lock, flags);
+ + 
+ + 	return ret;
+ + }
+ + EXPORT_SYMBOL(clk_set_rate);
+ + 
+ + int clk_set_parent(struct clk *clk, struct clk *parent)
+ + {
+ + 	unsigned long flags;
+ + 	int ret = -EINVAL;
+ + 
+ + 	if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent))
+ + 		return ret;
+ + 
+ + 	if (!arch_clock || !arch_clock->clk_set_parent)
+ + 		return ret;
+ + 
+ + 	spin_lock_irqsave(&clockfw_lock, flags);
+ + 	if (clk->usecount == 0) {
+ + 		ret = arch_clock->clk_set_parent(clk, parent);
+ + 		if (ret == 0)
+ + 			propagate_rate(clk);
+ + 	} else
+ + 		ret = -EBUSY;
+ + 	spin_unlock_irqrestore(&clockfw_lock, flags);
+ + 
+ + 	return ret;
+ + }
+ + EXPORT_SYMBOL(clk_set_parent);
+ + 
+ + struct clk *clk_get_parent(struct clk *clk)
+ + {
+ + 	return clk->parent;
+ + }
+ + EXPORT_SYMBOL(clk_get_parent);
+ + 
+ + /*
+ +  * OMAP specific clock functions shared between omap1 and omap2
+ +  */
+ + 
+ + int __initdata mpurate;
+ + 
+ + /*
+ +  * By default we use the rate set by the bootloader.
+ +  * You can override this with mpurate= cmdline option.
+ +  */
+ + static int __init omap_clk_setup(char *str)
+ + {
+ + 	get_option(&str, &mpurate);
+ + 
+ + 	if (!mpurate)
+ + 		return 1;
+ + 
+ + 	if (mpurate < 1000)
+ + 		mpurate *= 1000000;
+ + 
+ + 	return 1;
+ + }
+ + __setup("mpurate=", omap_clk_setup);
+ + 
+ + /* Used for clocks that always have same value as the parent clock */
+ + unsigned long followparent_recalc(struct clk *clk)
+ + {
+ + 	return clk->parent->rate;
+ + }
+ + 
+ + /*
+ +  * Used for clocks that have the same value as the parent clock,
+ +  * divided by some factor
+ +  */
+ + unsigned long omap_fixed_divisor_recalc(struct clk *clk)
+ + {
+ + 	WARN_ON(!clk->fixed_div);
+ + 
+ + 	return clk->parent->rate / clk->fixed_div;
+ + }
+ + 
+ + void clk_reparent(struct clk *child, struct clk *parent)
+ + {
+ + 	list_del_init(&child->sibling);
+ + 	if (parent)
+ + 		list_add(&child->sibling, &parent->children);
+ + 	child->parent = parent;
+ + 
+ + 	/* now do the debugfs renaming to reattach the child
+ + 	   to the proper parent */
+ + }
+ + 
+ + /* Propagate rate to children */
+ + void propagate_rate(struct clk *tclk)
+ + {
+ + 	struct clk *clkp;
+ + 
+ + 	list_for_each_entry(clkp, &tclk->children, sibling) {
+ + 		if (clkp->recalc)
+ + 			clkp->rate = clkp->recalc(clkp);
+ + 		propagate_rate(clkp);
+ + 	}
+ + }
+ + 
+ + static LIST_HEAD(root_clks);
+ + 
+ + /**
+ +  * recalculate_root_clocks - recalculate and propagate all root clocks
+ +  *
+ +  * Recalculates all root clocks (clocks with no parent), which if the
+ +  * clock's .recalc is set correctly, should also propagate their rates.
+ +  * Called at init.
+ +  */
+ + void recalculate_root_clocks(void)
+ + {
+ + 	struct clk *clkp;
+ + 
+ + 	list_for_each_entry(clkp, &root_clks, sibling) {
+ + 		if (clkp->recalc)
+ + 			clkp->rate = clkp->recalc(clkp);
+ + 		propagate_rate(clkp);
+ + 	}
+ + }
+ + 
+ + /**
+ +  * clk_preinit - initialize any fields in the struct clk before clk init
+ +  * @clk: struct clk * to initialize
+ +  *
+ +  * Initialize any struct clk fields needed before normal clk initialization
+ +  * can run.  No return value.
+ +  */
+ + void clk_preinit(struct clk *clk)
+ + {
+ + 	INIT_LIST_HEAD(&clk->children);
+ + }
+ + 
+ + int clk_register(struct clk *clk)
+ + {
+ + 	if (clk == NULL || IS_ERR(clk))
+ + 		return -EINVAL;
+ + 
+ + 	/*
+ + 	 * trap out already registered clocks
+ + 	 */
+ + 	if (clk->node.next || clk->node.prev)
+ + 		return 0;
+ + 
+ + 	mutex_lock(&clocks_mutex);
+ + 	if (clk->parent)
+ + 		list_add(&clk->sibling, &clk->parent->children);
+ + 	else
+ + 		list_add(&clk->sibling, &root_clks);
+ + 
+ + 	list_add(&clk->node, &clocks);
+ + 	if (clk->init)
+ + 		clk->init(clk);
+ + 	mutex_unlock(&clocks_mutex);
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(clk_register);
+ + 
+ + void clk_unregister(struct clk *clk)
+ + {
+ + 	if (clk == NULL || IS_ERR(clk))
+ + 		return;
+ + 
+ + 	mutex_lock(&clocks_mutex);
+ + 	list_del(&clk->sibling);
+ + 	list_del(&clk->node);
+ + 	mutex_unlock(&clocks_mutex);
+ + }
+ + EXPORT_SYMBOL(clk_unregister);
+ + 
+ + void clk_enable_init_clocks(void)
+ + {
+ + 	struct clk *clkp;
+ + 
+ + 	list_for_each_entry(clkp, &clocks, node) {
+ + 		if (clkp->flags & ENABLE_ON_INIT)
+ + 			clk_enable(clkp);
+ + 	}
+ + }
+ + 
+ + /**
+ +  * omap_clk_get_by_name - locate OMAP struct clk by its name
+ +  * @name: name of the struct clk to locate
+ +  *
+ +  * Locate an OMAP struct clk by its name.  Assumes that struct clk
+ +  * names are unique.  Returns NULL if not found or a pointer to the
+ +  * struct clk if found.
+ +  */
+ + struct clk *omap_clk_get_by_name(const char *name)
+ + {
+ + 	struct clk *c;
+ + 	struct clk *ret = NULL;
+ + 
+ + 	mutex_lock(&clocks_mutex);
+ + 
+ + 	list_for_each_entry(c, &clocks, node) {
+ + 		if (!strcmp(c->name, name)) {
+ + 			ret = c;
+ + 			break;
+ + 		}
+ + 	}
+ + 
+ + 	mutex_unlock(&clocks_mutex);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + int omap_clk_enable_autoidle_all(void)
+ + {
+ + 	struct clk *c;
+ + 	unsigned long flags;
+ + 
+ + 	spin_lock_irqsave(&clockfw_lock, flags);
+ + 
+ + 	list_for_each_entry(c, &clocks, node)
+ + 		if (c->ops->allow_idle)
+ + 			c->ops->allow_idle(c);
+ + 
+ + 	spin_unlock_irqrestore(&clockfw_lock, flags);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + int omap_clk_disable_autoidle_all(void)
+ + {
+ + 	struct clk *c;
+ + 	unsigned long flags;
+ + 
+ + 	spin_lock_irqsave(&clockfw_lock, flags);
+ + 
+ + 	list_for_each_entry(c, &clocks, node)
+ + 		if (c->ops->deny_idle)
+ + 			c->ops->deny_idle(c);
+ + 
+ + 	spin_unlock_irqrestore(&clockfw_lock, flags);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /*
+ +  * Low level helpers
+ +  */
+ + static int clkll_enable_null(struct clk *clk)
+ + {
+ + 	return 0;
+ + }
+ + 
+ + static void clkll_disable_null(struct clk *clk)
+ + {
+ + }
+ + 
+ + const struct clkops clkops_null = {
+ + 	.enable		= clkll_enable_null,
+ + 	.disable	= clkll_disable_null,
+ + };
+ + 
+ + /*
+ +  * Dummy clock
+ +  *
+ +  * Used for clock aliases that are needed on some OMAPs, but not others
+ +  */
+ + struct clk dummy_ck = {
+ + 	.name	= "dummy",
+ + 	.ops	= &clkops_null,
+ + };
+ + 
+ + #ifdef CONFIG_CPU_FREQ
+ + void clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
+ + {
+ + 	unsigned long flags;
+ + 
+ + 	if (!arch_clock || !arch_clock->clk_init_cpufreq_table)
+ + 		return;
+ + 
+ + 	spin_lock_irqsave(&clockfw_lock, flags);
+ + 	arch_clock->clk_init_cpufreq_table(table);
+ + 	spin_unlock_irqrestore(&clockfw_lock, flags);
+ + }
+ + 
+ + void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
+ + {
+ + 	unsigned long flags;
+ + 
+ + 	if (!arch_clock || !arch_clock->clk_exit_cpufreq_table)
+ + 		return;
+ + 
+ + 	spin_lock_irqsave(&clockfw_lock, flags);
+ + 	arch_clock->clk_exit_cpufreq_table(table);
+ + 	spin_unlock_irqrestore(&clockfw_lock, flags);
+ + }
+ + #endif
+ + 
+ + /*
+ +  *
+ +  */
+ + 
+ + #ifdef CONFIG_OMAP_RESET_CLOCKS
+ + /*
+ +  * Disable any unused clocks left on by the bootloader
+ +  */
+ + static int __init clk_disable_unused(void)
+ + {
+ + 	struct clk *ck;
+ + 	unsigned long flags;
+ + 
+ + 	if (!arch_clock || !arch_clock->clk_disable_unused)
+ + 		return 0;
+ + 
+ + 	pr_info("clock: disabling unused clocks to save power\n");
+ + 	list_for_each_entry(ck, &clocks, node) {
+ + 		if (ck->ops == &clkops_null)
+ + 			continue;
+ + 
+ + 		if (ck->usecount > 0 || !ck->enable_reg)
+ + 			continue;
+ + 
+ + 		spin_lock_irqsave(&clockfw_lock, flags);
+ + 		arch_clock->clk_disable_unused(ck);
+ + 		spin_unlock_irqrestore(&clockfw_lock, flags);
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ + late_initcall(clk_disable_unused);
+ + late_initcall(omap_clk_enable_autoidle_all);
+ + #endif
+ + 
+ + int __init clk_init(struct clk_functions * custom_clocks)
+ + {
+ + 	if (!custom_clocks) {
+ + 		pr_err("No custom clock functions registered\n");
+ + 		BUG();
+ + 	}
+ + 
+ + 	arch_clock = custom_clocks;
+ + 
+ + 	return 0;
+ + }
+ + 
+ + #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
+ + /*
+ +  *	debugfs support to trace clock tree hierarchy and attributes
+ +  */
+ + 
+ + #include <linux/debugfs.h>
+ + #include <linux/seq_file.h>
+ + 
+ + static struct dentry *clk_debugfs_root;
+ + 
+ + static int clk_dbg_show_summary(struct seq_file *s, void *unused)
+ + {
+ + 	struct clk *c;
+ + 	struct clk *pa;
+ + 
+ + 	seq_printf(s, "%-30s %-30s %-10s %s\n",
+ + 		"clock-name", "parent-name", "rate", "use-count");
+ + 
+ + 	list_for_each_entry(c, &clocks, node) {
+ + 		pa = c->parent;
+ + 		seq_printf(s, "%-30s %-30s %-10lu %d\n",
+ + 			c->name, pa ? pa->name : "none", c->rate, c->usecount);
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static int clk_dbg_open(struct inode *inode, struct file *file)
+ + {
+ + 	return single_open(file, clk_dbg_show_summary, inode->i_private);
+ + }
+ + 
+ + static const struct file_operations debug_clock_fops = {
+ + 	.open           = clk_dbg_open,
+ + 	.read           = seq_read,
+ + 	.llseek         = seq_lseek,
+ + 	.release        = single_release,
+ + };
+ + 
+ + static int clk_debugfs_register_one(struct clk *c)
+ + {
+ + 	int err;
+ + 	struct dentry *d;
+ + 	struct clk *pa = c->parent;
+ + 
+ + 	d = debugfs_create_dir(c->name, pa ? pa->dent : clk_debugfs_root);
+ + 	if (!d)
+ + 		return -ENOMEM;
+ + 	c->dent = d;
+ + 
+ + 	d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usecount);
+ + 	if (!d) {
+ + 		err = -ENOMEM;
+ + 		goto err_out;
+ + 	}
+ + 	d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
+ + 	if (!d) {
+ + 		err = -ENOMEM;
+ + 		goto err_out;
+ + 	}
+ + 	d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
+ + 	if (!d) {
+ + 		err = -ENOMEM;
+ + 		goto err_out;
+ + 	}
+ + 	return 0;
+ + 
+ + err_out:
+ + 	debugfs_remove_recursive(c->dent);
+ + 	return err;
+ + }
+ + 
+ + static int clk_debugfs_register(struct clk *c)
+ + {
+ + 	int err;
+ + 	struct clk *pa = c->parent;
+ + 
+ + 	if (pa && !pa->dent) {
+ + 		err = clk_debugfs_register(pa);
+ + 		if (err)
+ + 			return err;
+ + 	}
+ + 
+ + 	if (!c->dent) {
+ + 		err = clk_debugfs_register_one(c);
+ + 		if (err)
+ + 			return err;
+ + 	}
+ + 	return 0;
+ + }
+ + 
+ + static int __init clk_debugfs_init(void)
+ + {
+ + 	struct clk *c;
+ + 	struct dentry *d;
+ + 	int err;
+ + 
+ + 	d = debugfs_create_dir("clock", NULL);
+ + 	if (!d)
+ + 		return -ENOMEM;
+ + 	clk_debugfs_root = d;
+ + 
+ + 	list_for_each_entry(c, &clocks, node) {
+ + 		err = clk_debugfs_register(c);
+ + 		if (err)
+ + 			goto err_out;
+ + 	}
+ + 
+ + 	d = debugfs_create_file("summary", S_IRUGO,
+ + 		d, NULL, &debug_clock_fops);
+ + 	if (!d)
+ + 		return -ENOMEM;
+ + 
+ + 	return 0;
+ + err_out:
+ + 	debugfs_remove_recursive(clk_debugfs_root);
+ + 	return err;
+ + }
+ + late_initcall(clk_debugfs_init);
+ + 
+ + #endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/common.c linux-3.2.1/arch/arm/plat-ckb/common.c
+ *** linux-3.2.1_o/arch/arm/plat-ckb/common.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/common.c	2014-11-25 13:19:15.143717539 +0900
+ ***************
+ *** 0 ****
+ --- 1,68 ----
+ + /*
+ +  * linux/arch/arm/plat-omap/common.c
+ +  *
+ +  * Code common to all OMAP machines.
+ +  * The file is created by Tony Lindgren <tony@atomide.com>
+ +  *
+ +  * Copyright (C) 2009 Texas Instruments
+ +  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + #include <linux/kernel.h>
+ + #include <linux/init.h>
+ + #include <linux/io.h>
+ + #include <linux/dma-mapping.h>
+ + #include <linux/omapfb.h>
+ + 
+ + #include <plat/common.h>
+ + #include <plat/board.h>
+ + //#include <plat/vram.h>
+ + 
+ + 
+ + #define NO_LENGTH_CHECK 0xffffffff
+ + 
+ + struct omap_board_config_kernel *omap_board_config __initdata;
+ + int omap_board_config_size;
+ + 
+ + static const void *__init get_config(u16 tag, size_t len,
+ + 		int skip, size_t *len_out)
+ + {
+ + 	struct omap_board_config_kernel *kinfo = NULL;
+ + 	int i;
+ + 
+ + 	/* Try to find the config from the board-specific structures
+ + 	 * in the kernel. */
+ + 	for (i = 0; i < omap_board_config_size; i++) {
+ + 		if (omap_board_config[i].tag == tag) {
+ + 			if (skip == 0) {
+ + 				kinfo = &omap_board_config[i];
+ + 				break;
+ + 			} else {
+ + 				skip--;
+ + 			}
+ + 		}
+ + 	}
+ + 	if (kinfo == NULL)
+ + 		return NULL;
+ + 	return kinfo->data;
+ + }
+ + 
+ + const void *__init __omap_get_config(u16 tag, size_t len, int nr)
+ + {
+ +         return get_config(tag, len, nr, NULL);
+ + }
+ + 
+ + const void *__init omap_get_var_config(u16 tag, size_t *len)
+ + {
+ +         return get_config(tag, NO_LENGTH_CHECK, 0, len);
+ + }
+ + 
+ + void __init omap_init_consistent_dma_size(void)
+ + {
+ + #ifdef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
+ + 	init_consistent_dma_size(CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE << 20);
+ + #endif
+ + }
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/counter_32k.c linux-3.2.1/arch/arm/plat-ckb/counter_32k.c
+ *** linux-3.2.1_o/arch/arm/plat-ckb/counter_32k.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/counter_32k.c	2014-11-25 13:19:15.147028649 +0900
+ ***************
+ *** 0 ****
+ --- 1,142 ----
+ + /*
+ +  * OMAP 32ksynctimer/counter_32k-related code
+ +  *
+ +  * Copyright (C) 2009 Texas Instruments
+ +  * Copyright (C) 2010 Nokia Corporation
+ +  * Tony Lindgren <tony@atomide.com>
+ +  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  *
+ +  * NOTE: This timer is not the same timer as the old OMAP1 MPU timer.
+ +  */
+ + #include <linux/kernel.h>
+ + #include <linux/init.h>
+ + #include <linux/clk.h>
+ + #include <linux/err.h>
+ + #include <linux/io.h>
+ + #include <linux/sched.h>
+ + #include <linux/clocksource.h>
+ + 
+ + #include <asm/sched_clock.h>
+ + 
+ + #include <plat/common.h>
+ + #include <plat/board.h>
+ + 
+ + #include <plat/clock.h>
+ + 
+ + /*
+ +  * 32KHz clocksource ... always available, on pretty most chips except
+ +  * OMAP 730 and 1510.  Other timers could be used as clocksources, with
+ +  * higher resolution in free-running counter modes (e.g. 12 MHz xtal),
+ +  * but systems won't necessarily want to spend resources that way.
+ +  */
+ + static void __iomem *timer_32k_base;
+ + 
+ + #define OMAP16XX_TIMER_32K_SYNCHRONIZED		0xfffbc410
+ + 
+ + /*
+ +  * Returns current time from boot in nsecs. It's OK for this to wrap
+ +  * around for now, as it's just a relative time stamp.
+ +  */
+ + static DEFINE_CLOCK_DATA(cd);
+ + 
+ + /*
+ +  * Constants generated by clocks_calc_mult_shift(m, s, 32768, NSEC_PER_SEC, 60).
+ +  * This gives a resolution of about 30us and a wrap period of about 36hrs.
+ +  */
+ + #define SC_MULT		4000000000u
+ + #define SC_SHIFT	17
+ + 
+ + static inline unsigned long long notrace _omap_32k_sched_clock(void)
+ + {
+ + 	u32 cyc = timer_32k_base ? __raw_readl(timer_32k_base) : 0;
+ + 	return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, SC_MULT, SC_SHIFT);
+ + }
+ + 
+ + #if defined(CONFIG_OMAP_32K_TIMER) && !defined(CONFIG_OMAP_MPU_TIMER)
+ + unsigned long long notrace sched_clock(void)
+ + {
+ + 	return _omap_32k_sched_clock();
+ + }
+ + #else
+ + unsigned long long notrace omap_32k_sched_clock(void)
+ + {
+ + 	return _omap_32k_sched_clock();
+ + }
+ + #endif
+ + 
+ + 
+ + static void notrace omap_update_sched_clock(void)
+ + {
+ + 	u32 cyc = timer_32k_base ? __raw_readl(timer_32k_base) : 0;
+ + 	update_sched_clock(&cd, cyc, (u32)~0);
+ + }
+ + 
+ + /**
+ +  * read_persistent_clock -  Return time from a persistent clock.
+ +  *
+ +  * Reads the time from a source which isn't disabled during PM, the
+ +  * 32k sync timer.  Convert the cycles elapsed since last read into
+ +  * nsecs and adds to a monotonically increasing timespec.
+ +  */
+ + static struct timespec persistent_ts;
+ + static cycles_t cycles, last_cycles;
+ + static unsigned int persistent_mult, persistent_shift;
+ + void read_persistent_clock(struct timespec *ts)
+ + {
+ + 	unsigned long long nsecs;
+ + 	cycles_t delta;
+ + 	struct timespec *tsp = &persistent_ts;
+ + 
+ + 	last_cycles = cycles;
+ + 	cycles = timer_32k_base ? __raw_readl(timer_32k_base) : 0;
+ + 	delta = cycles - last_cycles;
+ + 
+ + 	nsecs = clocksource_cyc2ns(delta, persistent_mult, persistent_shift);
+ + 
+ + 	timespec_add_ns(tsp, nsecs);
+ + 	*ts = *tsp;
+ + }
+ + 
+ + int __init omap_init_clocksource_32k(void)
+ + {
+ + 	static char err[] __initdata = KERN_ERR
+ + 			"%s: can't register clocksource!\n";
+ + 
+ + 		u32 pbase;
+ + 		unsigned long size = SZ_4K;
+ + 		void __iomem *base;
+ + 		struct clk *sync_32k_ick;
+ + 
+ + 		pbase = OMAP3430_32KSYNCT_BASE + 0x10;
+ + 		
+ + 		/* For this to work we must have a static mapping in io.c for this area */
+ + 		base = ioremap(pbase, size);
+ + 		if (!base)
+ + 			return -ENODEV;
+ + 
+ + 		sync_32k_ick = clk_get(NULL, "omap_32ksync_ick");
+ + 		if (!IS_ERR(sync_32k_ick))
+ + 			clk_enable(sync_32k_ick);
+ + 
+ + 		timer_32k_base = base;
+ + 
+ + 		/*
+ + 		 * 120000 rough estimate from the calculations in
+ + 		 * __clocksource_updatefreq_scale.
+ + 		 */
+ + 		clocks_calc_mult_shift(&persistent_mult, &persistent_shift,
+ + 				32768, NSEC_PER_SEC, 120000);
+ + 
+ + 		if (clocksource_mmio_init(base, "32k_counter", 32768, 250, 32,
+ + 					  clocksource_mmio_readl_up))
+ + 			printk(err, "32k_counter");
+ + 
+ + 		init_fixed_sched_clock(&cd, omap_update_sched_clock, 32,
+ + 				       32768, SC_MULT, SC_SHIFT);
+ + 
+ + 	return 0;
+ + }
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/devices.c linux-3.2.1/arch/arm/plat-ckb/devices.c
+ *** linux-3.2.1_o/arch/arm/plat-ckb/devices.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/devices.c	2014-11-25 13:19:15.147028649 +0900
+ ***************
+ *** 0 ****
+ --- 1,146 ----
+ + /*
+ +  * linux/arch/arm/plat-omap/devices.c
+ +  *
+ +  * Common platform device setup/initialization for OMAP1 and OMAP2
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; either version 2 of the License, or
+ +  * (at your option) any later version.
+ +  */
+ + #include <linux/gpio.h>
+ + #include <linux/module.h>
+ + #include <linux/kernel.h>
+ + #include <linux/init.h>
+ + #include <linux/platform_device.h>
+ + #include <linux/io.h>
+ + #include <linux/slab.h>
+ + #include <linux/memblock.h>
+ + 
+ + #include <mach/hardware.h>
+ + #include <asm/mach-types.h>
+ + #include <asm/mach/map.h>
+ + 
+ + #include <plat/board.h>
+ + #include <plat/mmc.h>
+ + //#include <plat/omap44xx.h>
+ + #include <plat/am33xx.h>
+ + 
+ + #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
+ + 	defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
+ + 
+ + #define OMAP_MMC_NR_RES		2
+ + 
+ + /*
+ +  * Register MMC devices. Called from mach-omap1 and mach-omap2 device init.
+ +  */
+ + int __init omap_mmc_add(const char *name, int id, unsigned long base,
+ + 				unsigned long size, unsigned int irq,
+ + 				struct omap_mmc_platform_data *data)
+ + {
+ + 	struct platform_device *pdev;
+ + 	struct resource res[OMAP_MMC_NR_RES];
+ + 	int ret;
+ + 
+ + 	pdev = platform_device_alloc(name, id);
+ + 	if (!pdev)
+ + 		return -ENOMEM;
+ + 
+ + 	memset(res, 0, OMAP_MMC_NR_RES * sizeof(struct resource));
+ + 	res[0].start = base;
+ + 	res[0].end = base + size - 1;
+ + 	res[0].flags = IORESOURCE_MEM;
+ + 	res[1].start = res[1].end = irq;
+ + 	res[1].flags = IORESOURCE_IRQ;
+ + 
+ + 	ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
+ + 	if (ret == 0)
+ + 		ret = platform_device_add_data(pdev, data, sizeof(*data));
+ + 	if (ret)
+ + 		goto fail;
+ + 
+ + 	ret = platform_device_add(pdev);
+ + 	if (ret)
+ + 		goto fail;
+ + 
+ + 	/* return device handle to board setup code */
+ + 	data->dev = &pdev->dev;
+ + 	return 0;
+ + 
+ + fail:
+ + 	platform_device_put(pdev);
+ + 	return ret;
+ + }
+ + 
+ + #endif
+ + 
+ + /*-------------------------------------------------------------------------*/
+ + 
+ + #if defined(CONFIG_HW_RANDOM_OMAP) || defined(CONFIG_HW_RANDOM_OMAP_MODULE)
+ + 
+ + #define	OMAP_RNG_BASE		0xfffe5000
+ + 
+ + static struct resource rng_resources[] = {
+ + 	{
+ + 		.start		= OMAP_RNG_BASE,
+ + 		.end		= OMAP_RNG_BASE + 0x4f,
+ + 		.flags		= IORESOURCE_MEM,
+ + 	},
+ + };
+ + 
+ + static struct platform_device omap_rng_device = {
+ + 	.name		= "omap_rng",
+ + 	.id		= -1,
+ + 	.num_resources	= ARRAY_SIZE(rng_resources),
+ + 	.resource	= rng_resources,
+ + };
+ + 
+ + static void omap_init_rng(void)
+ + {
+ + 	(void) platform_device_register(&omap_rng_device);
+ + }
+ + #else
+ + static inline void omap_init_rng(void) {}
+ + #endif
+ + 
+ + 
+ + #if defined(CONFIG_TIDSPBRIDGE) || defined(CONFIG_TIDSPBRIDGE_MODULE)
+ + 
+ + static phys_addr_t omap_dsp_phys_mempool_base;
+ + 
+ + phys_addr_t omap_dsp_get_mempool_base(void)
+ + {
+ + 	return omap_dsp_phys_mempool_base;
+ + }
+ + EXPORT_SYMBOL(omap_dsp_get_mempool_base);
+ + #endif
+ + 
+ + /*
+ +  * This gets called after board-specific INIT_MACHINE, and initializes most
+ +  * on-chip peripherals accessible on this board (except for few like USB):
+ +  *
+ +  *  (a) Does any "standard config" pin muxing needed.  Board-specific
+ +  *	code will have muxed GPIO pins and done "nonstandard" setup;
+ +  *	that code could live in the boot loader.
+ +  *  (b) Populating board-specific platform_data with the data drivers
+ +  *	rely on to handle wiring variations.
+ +  *  (c) Creating platform devices as meaningful on this board and
+ +  *	with this kernel configuration.
+ +  *
+ +  * Claiming GPIOs, and setting their direction and initial values, is the
+ +  * responsibility of the device drivers.  So is responding to probe().
+ +  *
+ +  * Board-specific knowledge like creating devices or pin setup is to be
+ +  * kept out of drivers as much as possible.  In particular, pin setup
+ +  * may be handled by the boot loader, and drivers should expect it will
+ +  * normally have been done by the time they're probed.
+ +  */
+ + static int __init omap_init_devices(void)
+ + {
+ + 	/* please keep these calls, and their implementations above,
+ + 	 * in alphabetical order so they're easier to sort through.
+ + 	 */
+ + 	omap_init_rng();
+ + 	return 0;
+ + }
+ + arch_initcall(omap_init_devices);
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/dmtimer.c linux-3.2.1/arch/arm/plat-ckb/dmtimer.c
+ *** linux-3.2.1_o/arch/arm/plat-ckb/dmtimer.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/dmtimer.c	2014-11-25 13:19:15.147028649 +0900
+ ***************
+ *** 0 ****
+ --- 1,742 ----
+ + /*
+ +  * linux/arch/arm/plat-omap/dmtimer.c
+ +  *
+ +  * OMAP Dual-Mode Timers
+ +  *
+ +  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ +  * Tarun Kanti DebBarma <tarun.kanti@ti.com>
+ +  * Thara Gopinath <thara@ti.com>
+ +  *
+ +  * dmtimer adaptation to platform_driver.
+ +  *
+ +  * Copyright (C) 2005 Nokia Corporation
+ +  * OMAP2 support by Juha Yrjola
+ +  * API improvements and OMAP2 clock framework support by Timo Teras
+ +  *
+ +  * Copyright (C) 2009 Texas Instruments
+ +  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify it
+ +  * under the terms of the GNU General Public License as published by the
+ +  * Free Software Foundation; either version 2 of the License, or (at your
+ +  * option) any later version.
+ +  *
+ +  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ +  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ +  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ +  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ +  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ +  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ +  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ +  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ +  *
+ +  * You should have received a copy of the  GNU General Public License along
+ +  * with this program; if not, write  to the Free Software Foundation, Inc.,
+ +  * 675 Mass Ave, Cambridge, MA 02139, USA.
+ +  */
+ + 
+ + #include <linux/module.h>
+ + #include <linux/io.h>
+ + #include <linux/slab.h>
+ + #include <linux/err.h>
+ + #include <linux/pm_runtime.h>
+ + 
+ + #include <plat/dmtimer.h>
+ + 
+ + static LIST_HEAD(omap_timer_list);
+ + static DEFINE_SPINLOCK(dm_timer_lock);
+ + 
+ + /**
+ +  * omap_dm_timer_read_reg - read timer registers in posted and non-posted mode
+ +  * @timer:      timer pointer over which read operation to perform
+ +  * @reg:        lowest byte holds the register offset
+ +  *
+ +  * The posted mode bit is encoded in reg. Note that in posted mode write
+ +  * pending bit must be checked. Otherwise a read of a non completed write
+ +  * will produce an error.
+ +  */
+ + static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
+ + {
+ + 	WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
+ + 	return __omap_dm_timer_read(timer, reg, timer->posted);
+ + }
+ + 
+ + /**
+ +  * omap_dm_timer_write_reg - write timer registers in posted and non-posted mode
+ +  * @timer:      timer pointer over which write operation is to perform
+ +  * @reg:        lowest byte holds the register offset
+ +  * @value:      data to write into the register
+ +  *
+ +  * The posted mode bit is encoded in reg. Note that in posted mode the write
+ +  * pending bit must be checked. Otherwise a write on a register which has a
+ +  * pending write will be lost.
+ +  */
+ + static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
+ + 						u32 value)
+ + {
+ + 	WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
+ + 	__omap_dm_timer_write(timer, reg, value, timer->posted);
+ + }
+ + 
+ + static void omap_timer_restore_context(struct omap_dm_timer *timer)
+ + {
+ + 	omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_OFFSET,
+ + 				timer->context.tiocp_cfg);
+ + 	if (timer->revision > 1)
+ + 		__raw_writel(timer->context.tistat, timer->sys_stat);
+ + 
+ + 	__raw_writel(timer->context.tisr, timer->irq_stat);
+ + 	omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG,
+ + 				timer->context.twer);
+ + 	omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG,
+ + 				timer->context.tcrr);
+ + 	omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG,
+ + 				timer->context.tldr);
+ + 	omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG,
+ + 				timer->context.tmar);
+ + 	omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
+ + 				timer->context.tsicr);
+ + 	__raw_writel(timer->context.tier, timer->irq_ena);
+ + 	omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG,
+ + 				timer->context.tclr);
+ + }
+ + 
+ + static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
+ + {
+ + 	int c;
+ + 
+ + 	if (!timer->sys_stat)
+ + 		return;
+ + 
+ + 	c = 0;
+ + 	while (!(__raw_readl(timer->sys_stat) & 1)) {
+ + 		c++;
+ + 		if (c > 100000) {
+ + 			printk(KERN_ERR "Timer failed to reset\n");
+ + 			return;
+ + 		}
+ + 	}
+ + }
+ + 
+ + static void omap_dm_timer_reset(struct omap_dm_timer *timer)
+ + {
+ + 	omap_dm_timer_enable(timer);
+ + 	if (timer->pdev->id != 1) {
+ + 		omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
+ + 		omap_dm_timer_wait_for_reset(timer);
+ + 	}
+ + 
+ + 	__omap_dm_timer_reset(timer, 0, 0);
+ + 	omap_dm_timer_disable(timer);
+ + 	timer->posted = 1;
+ + }
+ + 
+ + int omap_dm_timer_prepare(struct omap_dm_timer *timer)
+ + {
+ + 	struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data;
+ + 
+ + 	timer->fclk = clk_get(&timer->pdev->dev, "fck");
+ + 	if (WARN_ON_ONCE(IS_ERR_OR_NULL(timer->fclk))) {
+ + 		timer->fclk = NULL;
+ + 		dev_err(&timer->pdev->dev, ": No fclk handle.\n");
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	if (pdata->needs_manual_reset)
+ + 		omap_dm_timer_reset(timer);
+ + 
+ + 	timer->posted = 1;
+ + 	return 0;
+ + }
+ + 
+ + struct omap_dm_timer *omap_dm_timer_request(void)
+ + {
+ + 	struct omap_dm_timer *timer = NULL, *t;
+ + 	unsigned long flags;
+ + 	int ret = 0;
+ + 
+ + 	spin_lock_irqsave(&dm_timer_lock, flags);
+ + 	list_for_each_entry(t, &omap_timer_list, node) {
+ + 		if (t->reserved)
+ + 			continue;
+ + 
+ + 		timer = t;
+ + 		timer->reserved = 1;
+ + 		break;
+ + 	}
+ + 
+ + 	if (timer) {
+ + 		ret = omap_dm_timer_prepare(timer);
+ + 		if (ret) {
+ + 			timer->reserved = 0;
+ + 			timer = NULL;
+ + 		}
+ + 	}
+ + 	spin_unlock_irqrestore(&dm_timer_lock, flags);
+ + 
+ + 	if (!timer)
+ + 		pr_debug("%s: timer request failed!\n", __func__);
+ + 
+ + 	return timer;
+ + }
+ + EXPORT_SYMBOL_GPL(omap_dm_timer_request);
+ + 
+ + struct omap_dm_timer *omap_dm_timer_request_specific(int id)
+ + {
+ + 	struct omap_dm_timer *timer = NULL, *t;
+ + 	unsigned long flags;
+ + 	int ret = 0;
+ + 
+ + 	spin_lock_irqsave(&dm_timer_lock, flags);
+ + 	list_for_each_entry(t, &omap_timer_list, node) {
+ + 		if (t->pdev->id == id && !t->reserved) {
+ + 			timer = t;
+ + 			timer->reserved = 1;
+ + 			break;
+ + 		}
+ + 	}
+ + 
+ + 	if (timer) {
+ + 		ret = omap_dm_timer_prepare(timer);
+ + 		if (ret) {
+ + 			timer->reserved = 0;
+ + 			timer = NULL;
+ + 		}
+ + 	}
+ + 	spin_unlock_irqrestore(&dm_timer_lock, flags);
+ + 
+ + 	if (!timer)
+ + 		pr_debug("%s: timer%d request failed!\n", __func__, id);
+ + 
+ + 	return timer;
+ + }
+ + EXPORT_SYMBOL_GPL(omap_dm_timer_request_specific);
+ + 
+ + int omap_dm_timer_free(struct omap_dm_timer *timer)
+ + {
+ + 	if (unlikely(!timer))
+ + 		return -EINVAL;
+ + 
+ + 	clk_put(timer->fclk);
+ + 
+ + 	WARN_ON(!timer->reserved);
+ + 	timer->reserved = 0;
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL_GPL(omap_dm_timer_free);
+ + 
+ + void omap_dm_timer_enable(struct omap_dm_timer *timer)
+ + {
+ + 	pm_runtime_get_sync(&timer->pdev->dev);
+ + }
+ + EXPORT_SYMBOL_GPL(omap_dm_timer_enable);
+ + 
+ + void omap_dm_timer_disable(struct omap_dm_timer *timer)
+ + {
+ + 	pm_runtime_put(&timer->pdev->dev);
+ + }
+ + EXPORT_SYMBOL_GPL(omap_dm_timer_disable);
+ + 
+ + int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
+ + {
+ + 	if (timer)
+ + 		return timer->irq;
+ + 	return -EINVAL;
+ + }
+ + EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq);
+ + 
+ + 
+ + struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
+ + {
+ + 	if (timer)
+ + 		return timer->fclk;
+ + 	return NULL;
+ + }
+ + EXPORT_SYMBOL_GPL(omap_dm_timer_get_fclk);
+ + 
+ + __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
+ + {
+ + 	BUG();
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
+ + 
+ + int omap_dm_timer_trigger(struct omap_dm_timer *timer)
+ + {
+ + 	if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
+ + 		pr_err("%s: timer not available or enabled.\n", __func__);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL_GPL(omap_dm_timer_trigger);
+ + 
+ + int omap_dm_timer_start(struct omap_dm_timer *timer)
+ + {
+ + 	u32 l;
+ + 
+ + 	if (unlikely(!timer))
+ + 		return -EINVAL;
+ + 
+ + 	omap_dm_timer_enable(timer);
+ + 
+ + 	if (timer->loses_context) {
+ + 		u32 ctx_loss_cnt_after =
+ + 			timer->get_context_loss_count(&timer->pdev->dev);
+ + 		if (ctx_loss_cnt_after != timer->ctx_loss_count)
+ + 			omap_timer_restore_context(timer);
+ + 	}
+ + 
+ + 	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
+ + 	if (!(l & OMAP_TIMER_CTRL_ST)) {
+ + 		l |= OMAP_TIMER_CTRL_ST;
+ + 		omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
+ + 	}
+ + 
+ + 	/* Save the context */
+ + 	timer->context.tclr = l;
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL_GPL(omap_dm_timer_start);
+ + 
+ + int omap_dm_timer_stop(struct omap_dm_timer *timer)
+ + {
+ + 	unsigned long rate = 0;
+ + 	struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data;
+ + 
+ + 	if (unlikely(!timer))
+ + 		return -EINVAL;
+ + 
+ + 	if (!pdata->needs_manual_reset)
+ + 		rate = clk_get_rate(timer->fclk);
+ + 
+ + 	__omap_dm_timer_stop(timer, timer->posted, rate);
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
+ + 
+ + int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
+ + {
+ + 	int ret;
+ + 	struct dmtimer_platform_data *pdata;
+ + 
+ + 	if (unlikely(!timer))
+ + 		return -EINVAL;
+ + 
+ + 	pdata = timer->pdev->dev.platform_data;
+ + 
+ + 	if (source < 0 || source >= 3)
+ + 		return -EINVAL;
+ + 
+ + 	ret = pdata->set_timer_src(timer->pdev, source);
+ + 
+ + 	return ret;
+ + }
+ + EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
+ + 
+ + int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
+ + 			    unsigned int load)
+ + {
+ + 	u32 l;
+ + 
+ + 	if (unlikely(!timer))
+ + 		return -EINVAL;
+ + 
+ + 	omap_dm_timer_enable(timer);
+ + 	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
+ + 	if (autoreload)
+ + 		l |= OMAP_TIMER_CTRL_AR;
+ + 	else
+ + 		l &= ~OMAP_TIMER_CTRL_AR;
+ + 	omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
+ + 	omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
+ + 
+ + 	omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
+ + 	/* Save the context */
+ + 	timer->context.tclr = l;
+ + 	timer->context.tldr = load;
+ + 	omap_dm_timer_disable(timer);
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL_GPL(omap_dm_timer_set_load);
+ + 
+ + /* Optimized set_load which removes costly spin wait in timer_start */
+ + int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
+ +                             unsigned int load)
+ + {
+ + 	u32 l;
+ + 
+ + 	if (unlikely(!timer))
+ + 		return -EINVAL;
+ + 
+ + 	omap_dm_timer_enable(timer);
+ + 
+ + 	if (timer->loses_context) {
+ + 		u32 ctx_loss_cnt_after =
+ + 			timer->get_context_loss_count(&timer->pdev->dev);
+ + 		if (ctx_loss_cnt_after != timer->ctx_loss_count)
+ + 			omap_timer_restore_context(timer);
+ + 	}
+ + 
+ + 	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
+ + 	if (autoreload) {
+ + 		l |= OMAP_TIMER_CTRL_AR;
+ + 		omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
+ + 	} else {
+ + 		l &= ~OMAP_TIMER_CTRL_AR;
+ + 	}
+ + 	l |= OMAP_TIMER_CTRL_ST;
+ + 
+ + 	__omap_dm_timer_load_start(timer, l, load, timer->posted);
+ + 
+ + 	/* Save the context */
+ + 	timer->context.tclr = l;
+ + 	timer->context.tldr = load;
+ + 	timer->context.tcrr = load;
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL_GPL(omap_dm_timer_set_load_start);
+ + 
+ + int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
+ + 			     unsigned int match)
+ + {
+ + 	u32 l;
+ + 
+ + 	if (unlikely(!timer))
+ + 		return -EINVAL;
+ + 
+ + 	omap_dm_timer_enable(timer);
+ + 	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
+ + 	if (enable)
+ + 		l |= OMAP_TIMER_CTRL_CE;
+ + 	else
+ + 		l &= ~OMAP_TIMER_CTRL_CE;
+ + 	omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
+ + 	omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
+ + 
+ + 	/* Save the context */
+ + 	timer->context.tclr = l;
+ + 	timer->context.tmar = match;
+ + 	omap_dm_timer_disable(timer);
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL_GPL(omap_dm_timer_set_match);
+ + 
+ + int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
+ + 			   int toggle, int trigger)
+ + {
+ + 	u32 l;
+ + 
+ + 	if (unlikely(!timer))
+ + 		return -EINVAL;
+ + 
+ + 	omap_dm_timer_enable(timer);
+ + 	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
+ + 	l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
+ + 	       OMAP_TIMER_CTRL_PT | (0x03 << 10));
+ + 	if (def_on)
+ + 		l |= OMAP_TIMER_CTRL_SCPWM;
+ + 	if (toggle)
+ + 		l |= OMAP_TIMER_CTRL_PT;
+ + 	l |= trigger << 10;
+ + 	omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
+ + 
+ + 	/* Save the context */
+ + 	timer->context.tclr = l;
+ + 	omap_dm_timer_disable(timer);
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL_GPL(omap_dm_timer_set_pwm);
+ + 
+ + int omap_dm_timer_set_capture(struct omap_dm_timer *timer, bool lht,
+ + 				bool hlt, bool cm)
+ + {
+ + 	u32 l;
+ + 
+ + 	if (unlikely(!timer))
+ + 		return -EINVAL;
+ + 
+ + 	omap_dm_timer_enable(timer);
+ + 	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
+ + 
+ + 	if (lht && hlt)
+ + 		l |= OMAP_TIMER_CTRL_TCM_BOTHEDGES;
+ + 	else if (lht)
+ + 		l |= OMAP_TIMER_CTRL_TCM_LOWTOHIGH;
+ + 	else if (hlt)
+ + 		l |= OMAP_TIMER_CTRL_TCM_HIGHTOLOW;
+ + 	else
+ + 		l &= ~OMAP_TIMER_CTRL_TCM_BOTHEDGES;
+ + 
+ + 	if (cm)
+ + 		l |= OMAP_TIMER_CTRL_CAPTMODE;
+ + 	else
+ + 		l &= ~OMAP_TIMER_CTRL_CAPTMODE;
+ + 
+ + 	omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
+ + 
+ + 	/* Save the context */
+ + 	timer->context.tclr = l;
+ + 	omap_dm_timer_disable(timer);
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL_GPL(omap_dm_timer_set_capture);
+ + 
+ + int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
+ + {
+ + 	u32 l;
+ + 
+ + 	if (unlikely(!timer))
+ + 		return -EINVAL;
+ + 
+ + 	omap_dm_timer_enable(timer);
+ + 	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
+ + 	l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
+ + 	if (prescaler >= 0x00 && prescaler <= 0x07) {
+ + 		l |= OMAP_TIMER_CTRL_PRE;
+ + 		l |= prescaler << 2;
+ + 	}
+ + 	omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
+ + 
+ + 	/* Save the context */
+ + 	timer->context.tclr = l;
+ + 	omap_dm_timer_disable(timer);
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL_GPL(omap_dm_timer_set_prescaler);
+ + 
+ + int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
+ + 				  unsigned int value)
+ + {
+ + 	if (unlikely(!timer))
+ + 		return -EINVAL;
+ + 
+ + 	omap_dm_timer_enable(timer);
+ + 	__omap_dm_timer_int_enable(timer, value);
+ + 
+ + 	/* Save the context */
+ + 	timer->context.tier = value;
+ + 	timer->context.twer = value;
+ + 	omap_dm_timer_disable(timer);
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable);
+ + 
+ + unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
+ + {
+ + 	unsigned int l;
+ + 
+ + 	if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
+ + 		pr_err("%s: timer not available or enabled.\n", __func__);
+ + 		return 0;
+ + 	}
+ + 
+ + 	l = __raw_readl(timer->irq_stat);
+ + 
+ + 	return l;
+ + }
+ + EXPORT_SYMBOL_GPL(omap_dm_timer_read_status);
+ + 
+ + int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
+ + {
+ + 	if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev)))
+ + 		return -EINVAL;
+ + 
+ + 	__omap_dm_timer_write_status(timer, value);
+ + 	/* Save the context */
+ + 	timer->context.tisr = value;
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL_GPL(omap_dm_timer_write_status);
+ + 
+ + unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
+ + {
+ + 	if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
+ + 		pr_err("%s: timer not iavailable or enabled.\n", __func__);
+ + 		return 0;
+ + 	}
+ + 
+ + 	return __omap_dm_timer_read_counter(timer, timer->posted);
+ + }
+ + EXPORT_SYMBOL_GPL(omap_dm_timer_read_counter);
+ + 
+ + int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
+ + {
+ + 	if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
+ + 		pr_err("%s: timer not available or enabled.\n", __func__);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
+ + 
+ + 	/* Save the context */
+ + 	timer->context.tcrr = value;
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL_GPL(omap_dm_timer_write_counter);
+ + 
+ + int omap_dm_timers_active(void)
+ + {
+ + 	struct omap_dm_timer *timer;
+ + 
+ + 	list_for_each_entry(timer, &omap_timer_list, node) {
+ + 		if (!timer->reserved)
+ + 			continue;
+ + 
+ + 		if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
+ + 		    OMAP_TIMER_CTRL_ST) {
+ + 			return 1;
+ + 		}
+ + 	}
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL_GPL(omap_dm_timers_active);
+ + 
+ + /**
+ +  * omap_dm_timer_probe - probe function called for every registered device
+ +  * @pdev:	pointer to current timer platform device
+ +  *
+ +  * Called by driver framework at the end of device registration for all
+ +  * timer devices.
+ +  */
+ + static int __devinit omap_dm_timer_probe(struct platform_device *pdev)
+ + {
+ + 	int ret;
+ + 	unsigned long flags;
+ + 	struct omap_dm_timer *timer;
+ + 	struct resource *mem, *irq, *ioarea;
+ + 	struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
+ + 
+ + 	if (!pdata) {
+ + 		dev_err(&pdev->dev, "%s: no platform data.\n", __func__);
+ + 		return -ENODEV;
+ + 	}
+ + 
+ + 	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ + 	if (unlikely(!irq)) {
+ + 		dev_err(&pdev->dev, "%s: no IRQ resource.\n", __func__);
+ + 		return -ENODEV;
+ + 	}
+ + 
+ + 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ + 	if (unlikely(!mem)) {
+ + 		dev_err(&pdev->dev, "%s: no memory resource.\n", __func__);
+ + 		return -ENODEV;
+ + 	}
+ + 
+ + 	ioarea = request_mem_region(mem->start, resource_size(mem),
+ + 			pdev->name);
+ + 	if (!ioarea) {
+ + 		dev_err(&pdev->dev, "%s: region already claimed.\n", __func__);
+ + 		return -EBUSY;
+ + 	}
+ + 
+ + 	timer = kzalloc(sizeof(struct omap_dm_timer), GFP_KERNEL);
+ + 	if (!timer) {
+ + 		dev_err(&pdev->dev, "%s: no memory for omap_dm_timer.\n",
+ + 			__func__);
+ + 		ret = -ENOMEM;
+ + 		goto err_free_ioregion;
+ + 	}
+ + 
+ + 	timer->io_base = ioremap(mem->start, resource_size(mem));
+ + 	if (!timer->io_base) {
+ + 		dev_err(&pdev->dev, "%s: ioremap failed.\n", __func__);
+ + 		ret = -ENOMEM;
+ + 		goto err_free_mem;
+ + 	}
+ + 
+ + 	timer->id = pdev->id;
+ + 	timer->irq = irq->start;
+ + 	timer->reserved = pdata->reserved;
+ + 	timer->pdev = pdev;
+ + 	timer->loses_context = pdata->loses_context;
+ + 	timer->get_context_loss_count = pdata->get_context_loss_count;
+ + 
+ + 	/* Skip pm_runtime_enable for OMAP1 */
+ + 	if (!pdata->needs_manual_reset) {
+ + 		pm_runtime_enable(&pdev->dev);
+ + 		pm_runtime_irq_safe(&pdev->dev);
+ + 	}
+ + 
+ + 	if (!timer->reserved) {
+ + 		pm_runtime_get_sync(&pdev->dev);
+ + 		__omap_dm_timer_init_regs(timer);
+ + 		pm_runtime_put(&pdev->dev);
+ + 	}
+ + 
+ + 	/* add the timer element to the list */
+ + 	spin_lock_irqsave(&dm_timer_lock, flags);
+ + 	list_add_tail(&timer->node, &omap_timer_list);
+ + 	spin_unlock_irqrestore(&dm_timer_lock, flags);
+ + 
+ + 	dev_dbg(&pdev->dev, "Device Probed.\n");
+ + 
+ + 	return 0;
+ + 
+ + err_free_mem:
+ + 	kfree(timer);
+ + 
+ + err_free_ioregion:
+ + 	release_mem_region(mem->start, resource_size(mem));
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * omap_dm_timer_remove - cleanup a registered timer device
+ +  * @pdev:	pointer to current timer platform device
+ +  *
+ +  * Called by driver framework whenever a timer device is unregistered.
+ +  * In addition to freeing platform resources it also deletes the timer
+ +  * entry from the local list.
+ +  */
+ + static int __devexit omap_dm_timer_remove(struct platform_device *pdev)
+ + {
+ + 	struct omap_dm_timer *timer;
+ + 	unsigned long flags;
+ + 	int ret = -EINVAL;
+ + 
+ + 	spin_lock_irqsave(&dm_timer_lock, flags);
+ + 	list_for_each_entry(timer, &omap_timer_list, node)
+ + 		if (timer->pdev->id == pdev->id) {
+ + 			list_del(&timer->node);
+ + 			kfree(timer);
+ + 			ret = 0;
+ + 			break;
+ + 		}
+ + 	spin_unlock_irqrestore(&dm_timer_lock, flags);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + static struct platform_driver omap_dm_timer_driver = {
+ + 	.probe  = omap_dm_timer_probe,
+ + 	.remove = __devexit_p(omap_dm_timer_remove),
+ + 	.driver = {
+ + 		.name   = "omap_timer",
+ + 	},
+ + };
+ + 
+ + static int __init omap_dm_timer_driver_init(void)
+ + {
+ + 	return platform_driver_register(&omap_dm_timer_driver);
+ + }
+ + 
+ + static void __exit omap_dm_timer_driver_exit(void)
+ + {
+ + 	platform_driver_unregister(&omap_dm_timer_driver);
+ + }
+ + 
+ + early_platform_init("earlytimer", &omap_dm_timer_driver);
+ + module_init(omap_dm_timer_driver_init);
+ + module_exit(omap_dm_timer_driver_exit);
+ + 
+ + MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver");
+ + MODULE_LICENSE("GPL");
+ + MODULE_ALIAS("platform:" DRIVER_NAME);
+ + MODULE_AUTHOR("Texas Instruments Inc");
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/i2c.c linux-3.2.1/arch/arm/plat-ckb/i2c.c
+ *** linux-3.2.1_o/arch/arm/plat-ckb/i2c.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/i2c.c	2014-11-25 13:19:15.151027282 +0900
+ ***************
+ *** 0 ****
+ --- 1,193 ----
+ + /*
+ +  * linux/arch/arm/plat-omap/i2c.c
+ +  *
+ +  * Helper module for board specific I2C bus registration
+ +  *
+ +  * Copyright (C) 2007 Nokia Corporation.
+ +  *
+ +  * Contact: Jarkko Nikula <jhnikula@gmail.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License
+ +  * version 2 as published by the Free Software Foundation.
+ +  *
+ +  * This program is distributed in the hope that it will be useful, but
+ +  * WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ +  * General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ +  * 02110-1301 USA
+ +  *
+ +  */
+ + 
+ + #include <linux/kernel.h>
+ + #include <linux/platform_device.h>
+ + #include <linux/i2c.h>
+ + #include <linux/i2c-omap.h>
+ + #include <linux/slab.h>
+ + #include <linux/err.h>
+ + #include <linux/clk.h>
+ + 
+ + #include <mach/irqs.h>
+ + #include <plat/mux.h>
+ + #include <plat/i2c.h>
+ + #include <plat/omap-pm.h>
+ + #include <plat/omap_device.h>
+ + 
+ + 
+ + static const char name[] = "omap_i2c";
+ + 
+ + #define MAX_OMAP_I2C_HWMOD_NAME_LEN	16
+ + #define OMAP_I2C_MAX_CONTROLLERS 4
+ + static struct omap_i2c_bus_platform_data i2c_pdata[OMAP_I2C_MAX_CONTROLLERS];
+ + 
+ + #define OMAP_I2C_CMDLINE_SETUP	(BIT(31))
+ + 
+ + static int __init omap_i2c_nr_ports(void)
+ + {
+ + 	return 3;
+ + }
+ + 
+ + /*
+ +  * XXX This function is a temporary compatibility wrapper - only
+ +  * needed until the I2C driver can be converted to call
+ +  * omap_pm_set_max_dev_wakeup_lat() and handle a return code.
+ +  */
+ + static void omap_pm_set_max_mpu_wakeup_lat_compat(struct device *dev, long t)
+ + {
+ + 	omap_pm_set_max_mpu_wakeup_lat(dev, t);
+ + }
+ + 
+ + static inline int omap2_i2c_add_bus(int bus_id)
+ + {
+ + 	int l;
+ + 	struct omap_hwmod *oh;
+ + 	struct platform_device *pdev;
+ + 	char oh_name[MAX_OMAP_I2C_HWMOD_NAME_LEN];
+ + 	struct omap_i2c_bus_platform_data *pdata;
+ + 	struct omap_i2c_dev_attr *dev_attr;
+ + 
+ + 	l = snprintf(oh_name, MAX_OMAP_I2C_HWMOD_NAME_LEN, "i2c%d", bus_id);
+ + 	WARN(l >= MAX_OMAP_I2C_HWMOD_NAME_LEN,
+ + 		"String buffer overflow in I2C%d device setup\n", bus_id);
+ + 	oh = omap_hwmod_lookup(oh_name);
+ + 	if (!oh) {
+ + 			pr_err("Could not look up %s\n", oh_name);
+ + 			return -EEXIST;
+ + 	}
+ + 
+ + 	pdata = &i2c_pdata[bus_id - 1];
+ + 	/*
+ + 	 * pass the hwmod class's CPU-specific knowledge of I2C IP revision in
+ + 	 * use, and functionality implementation flags, up to the OMAP I2C
+ + 	 * driver via platform data
+ + 	 */
+ + 	pdata->rev = oh->class->rev;
+ + 
+ + 	dev_attr = (struct omap_i2c_dev_attr *)oh->dev_attr;
+ + 	pdata->flags = dev_attr->flags;
+ + 
+ + 	/*
+ + 	 * When waiting for completion of a i2c transfer, we need to
+ + 	 * set a wake up latency constraint for the MPU. This is to
+ + 	 * ensure quick enough wakeup from idle, when transfer
+ + 	 * completes.
+ + 	 * Only omap3 has support for constraints
+ + 	 */
+ + 	pdata->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat;
+ + 
+ + 	pdata->device_reset = omap_device_reset;
+ + 	pdev = omap_device_build(name, bus_id, oh, pdata,
+ + 			sizeof(struct omap_i2c_bus_platform_data),
+ + 			NULL, 0, 0);
+ + 	WARN(IS_ERR(pdev), "Could not build omap_device for %s\n", name);
+ + 
+ + 	return PTR_RET(pdev);
+ + }
+ + 
+ + static int __init omap_i2c_add_bus(int bus_id)
+ + {
+ + 	return omap2_i2c_add_bus(bus_id);
+ + }
+ + 
+ + /**
+ +  * omap_i2c_bus_setup - Process command line options for the I2C bus speed
+ +  * @str: String of options
+ +  *
+ +  * This function allow to override the default I2C bus speed for given I2C
+ +  * bus with a command line option.
+ +  *
+ +  * Format: i2c_bus=bus_id,clkrate (in kHz)
+ +  *
+ +  * Returns 1 on success, 0 otherwise.
+ +  */
+ + static int __init omap_i2c_bus_setup(char *str)
+ + {
+ + 	int ports;
+ + 	int ints[3];
+ + 
+ + 	ports = omap_i2c_nr_ports();
+ + 	get_options(str, 3, ints);
+ + 	if (ints[0] < 2 || ints[1] < 1 || ints[1] > ports)
+ + 		return 0;
+ + 	i2c_pdata[ints[1] - 1].clkrate = ints[2];
+ + 	i2c_pdata[ints[1] - 1].clkrate |= OMAP_I2C_CMDLINE_SETUP;
+ + 
+ + 	return 1;
+ + }
+ + __setup("i2c_bus=", omap_i2c_bus_setup);
+ + 
+ + /*
+ +  * Register busses defined in command line but that are not registered with
+ +  * omap_register_i2c_bus from board initialization code.
+ +  */
+ + static int __init omap_register_i2c_bus_cmdline(void)
+ + {
+ + 	int i, err = 0;
+ + 
+ + 	for (i = 0; i < ARRAY_SIZE(i2c_pdata); i++)
+ + 		if (i2c_pdata[i].clkrate & OMAP_I2C_CMDLINE_SETUP) {
+ + 			i2c_pdata[i].clkrate &= ~OMAP_I2C_CMDLINE_SETUP;
+ + 			err = omap_i2c_add_bus(i + 1);
+ + 			if (err)
+ + 				goto out;
+ + 		}
+ + 
+ + out:
+ + 	return err;
+ + }
+ + subsys_initcall(omap_register_i2c_bus_cmdline);
+ + 
+ + /**
+ +  * omap_register_i2c_bus - register I2C bus with device descriptors
+ +  * @bus_id: bus id counting from number 1
+ +  * @clkrate: clock rate of the bus in kHz
+ +  * @info: pointer into I2C device descriptor table or NULL
+ +  * @len: number of descriptors in the table
+ +  *
+ +  * Returns 0 on success or an error code.
+ +  */
+ + int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
+ + 			  struct i2c_board_info const *info,
+ + 			  unsigned len)
+ + {
+ + 	int err;
+ + 
+ + 	BUG_ON(bus_id < 1 || bus_id > omap_i2c_nr_ports());
+ + 
+ + 	if (info) {
+ + 		err = i2c_register_board_info(bus_id, info, len);
+ + 		if (err)
+ + 			return err;
+ + 	}
+ + 
+ + 	if (!i2c_pdata[bus_id - 1].clkrate)
+ + 		i2c_pdata[bus_id - 1].clkrate = clkrate;
+ + 
+ + 	i2c_pdata[bus_id - 1].clkrate &= ~OMAP_I2C_CMDLINE_SETUP;
+ + 
+ + 	return omap_i2c_add_bus(bus_id);
+ + }
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/am33xx.h linux-3.2.1/arch/arm/plat-ckb/include/plat/am33xx.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/am33xx.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/am33xx.h	2014-11-25 13:19:15.151027282 +0900
+ ***************
+ *** 0 ****
+ --- 1,111 ----
+ + /*
+ +  * This file contains the address info for various AM33XX modules.
+ +  *
+ +  * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #ifndef __ASM_ARCH_AM33XX_H
+ + #define __ASM_ARCH_AM33XX_H
+ + 
+ + #define L4_SLOW_AM33XX_BASE	0x48000000
+ + 
+ + #define AM33XX_SCM_BASE		0x44E10000
+ + #define AM33XX_CTRL_BASE	AM33XX_SCM_BASE
+ + #define AM33XX_PRCM_BASE	0x44E00000
+ + 
+ + #define AM33XX_EMIF0_BASE	0x4C000000
+ + 
+ + #define AM33XX_GPIO0_BASE	0x44E07000
+ + #define AM33XX_GPIO1_BASE	0x4804C000
+ + #define AM33XX_GPIO2_BASE	0x481AC000
+ + #define AM33XX_GPIO3_BASE	0x481AE000
+ + 
+ + #define AM33XX_TIMER0_BASE	0x44E05000
+ + #define AM33XX_TIMER1_BASE	0x44E31000
+ + #define AM33XX_TIMER2_BASE	0x48040000
+ + #define AM33XX_TIMER3_BASE	0x48042000
+ + #define AM33XX_TIMER4_BASE	0x48044000
+ + #define AM33XX_TIMER5_BASE	0x48046000
+ + #define AM33XX_TIMER6_BASE	0x48048000
+ + #define AM33XX_TIMER7_BASE	0x4804A000
+ + 
+ + #define AM33XX_WDT1_BASE	0x44E35000
+ + 
+ + #define AM33XX_TSC_BASE		0x44E0D000
+ + #define AM33XX_RTC_BASE		0x44E3E000
+ + 
+ + #define AM33XX_SR0_BASE         0x44E37000
+ + #define AM33XX_SR1_BASE         0x44E39000
+ + 
+ + #define AM33XX_ASP0_BASE	0x48038000
+ + #define AM33XX_ASP1_BASE	0x4803C000
+ + 
+ + #define AM33XX_MAILBOX0_BASE	0x480C8000
+ + 
+ + #define AM33XX_MMC0_BASE	0x48060100
+ + #define AM33XX_MMC1_BASE	0x481D8100
+ + #define AM33XX_MMC2_BASE	0x47810100
+ + 
+ + #define AM33XX_I2C0_BASE	0x44E0B000
+ + #define AM33XX_I2C1_BASE	0x4802A000
+ + #define AM33XX_I2C2_BASE	0x4819C000
+ + 
+ + #define AM33XX_SPI0_BASE	0x48030000
+ + #define AM33XX_SPI1_BASE	0x481A0000
+ + 
+ + #define AM33XX_USBSS_BASE	0x47400000
+ + #define AM33XX_USB0_BASE	0x47401000
+ + #define AM33XX_USB1_BASE	0x47401800
+ + 
+ + #define AM33XX_ELM_BASE		0x48080000
+ + 
+ + /* Base address for crypto modules */
+ + #define AM33XX_SHA1MD5_S_BASE	0x53000000
+ + #define AM33XX_SHA1MD5_P_BASE	0x53100000
+ + 
+ + #define	AM33XX_AES0_S_BASE	0x53400000
+ + #define	AM33XX_AES0_P_BASE	0x53500000
+ + #define	AM33XX_AES1_S_BASE	0x53600000
+ + #define	AM33XX_AES1_P_BASE	0x53700000
+ + 
+ + #define	AM33XX_RNG_BASE		0x48310000
+ + 
+ + #define AM33XX_ASP0_BASE	0x48038000
+ + #define AM33XX_ASP1_BASE	0x4803C000
+ + 
+ + #define AM33XX_CPSW_BASE       0x4A100000
+ + #define AM33XX_CPSW_MDIO_BASE  0x4A101000
+ + #define AM33XX_CPSW_SS_BASE    0x4A101200
+ + 
+ + #define AM33XX_ICSS_BASE	0x4A300000
+ + #define AM33XX_ICSS_LEN		0x3FFFF
+ + 
+ + #define AM33XX_EPWMSS0_BASE	0x48300000
+ + #define AM33XX_EPWMSS1_BASE	0x48302000
+ + #define AM33XX_EPWMSS2_BASE	0x48304000
+ + 
+ + /*
+ +  * ----------------------------------------------------------------------------
+ +  * CPSW
+ +  * ----------------------------------------------------------------------------
+ +  */
+ + #ifndef __ASSEMBLER__
+ + enum am33xx_cpsw_mac_mode {
+ + 	AM33XX_CPSW_MODE_MII,
+ + 	AM33XX_CPSW_MODE_RMII,
+ + 	AM33XX_CPSW_MODE_RGMII,
+ + };
+ + int am33xx_cpsw_init(enum am33xx_cpsw_mac_mode mode, unsigned char *mac_id, void (*save_mac_addr) (char *));
+ + #endif
+ + 
+ + 
+ + #endif /* __ASM_ARCH_AM33XX_H */
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/board.h linux-3.2.1/arch/arm/plat-ckb/include/plat/board.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/board.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/board.h	2014-11-25 13:19:15.151027282 +0900
+ ***************
+ *** 0 ****
+ --- 1,176 ----
+ + /*
+ +  *  arch/arm/plat-omap/include/mach/board.h
+ +  *
+ +  *  Information structures for board-specific data
+ +  *
+ +  *  Copyright (C) 2004	Nokia Corporation
+ +  *  Written by Juha Yrjölä <juha.yrjola@nokia.com>
+ +  */
+ + 
+ + #ifndef _OMAP_BOARD_H
+ + #define _OMAP_BOARD_H
+ + 
+ + #include <linux/types.h>
+ + 
+ + #include <plat/gpio-switch.h>
+ + 
+ + /*
+ +  * OMAP35x EVM revision
+ +  * Run time detection of EVM revision is done by reading Ethernet
+ +  * PHY ID -
+ +  *	GEN_1	= 0x01150000
+ +  *	GEN_2	= 0x92200000
+ +  */
+ + enum {
+ + 	OMAP3EVM_BOARD_GEN_1 = 0,	/* EVM Rev between  A - D */
+ + 	OMAP3EVM_BOARD_GEN_2,		/* EVM Rev >= Rev E */
+ + };
+ + 
+ + /* Different peripheral ids */
+ + #define OMAP_TAG_CLOCK		0x4f01
+ + #define OMAP_TAG_LCD		0x4f05
+ + #define OMAP_TAG_GPIO_SWITCH	0x4f06
+ + #define OMAP_TAG_FBMEM		0x4f08
+ + #define OMAP_TAG_STI_CONSOLE	0x4f09
+ + #define OMAP_TAG_CAMERA_SENSOR	0x4f0a
+ + 
+ + #define OMAP_TAG_BOOT_REASON    0x4f80
+ + #define OMAP_TAG_FLASH_PART	0x4f81
+ + #define OMAP_TAG_VERSION_STR	0x4f82
+ + 
+ + struct omap_clock_config {
+ + 	/* 0 for 12 MHz, 1 for 13 MHz and 2 for 19.2 MHz */
+ + 	u8 system_clock_type;
+ + };
+ + 
+ + struct omap_serial_console_config {
+ + 	u8 console_uart;
+ + 	u32 console_speed;
+ + };
+ + 
+ + struct omap_sti_console_config {
+ + 	unsigned enable:1;
+ + 	u8 channel;
+ + };
+ + 
+ + struct omap_camera_sensor_config {
+ + 	u16 reset_gpio;
+ + 	int (*power_on)(void * data);
+ + 	int (*power_off)(void * data);
+ + };
+ + 
+ + struct omap_usb_config {
+ + 	/* Configure drivers according to the connectors on your board:
+ + 	 *  - "A" connector (rectagular)
+ + 	 *	... for host/OHCI use, set "register_host".
+ + 	 *  - "B" connector (squarish) or "Mini-B"
+ + 	 *	... for device/gadget use, set "register_dev".
+ + 	 *  - "Mini-AB" connector (very similar to Mini-B)
+ + 	 *	... for OTG use as device OR host, initialize "otg"
+ + 	 */
+ + 	unsigned	register_host:1;
+ + 	unsigned	register_dev:1;
+ + 	u8		otg;	/* port number, 1-based:  usb1 == 2 */
+ + 
+ + 	u8		hmc_mode;
+ + 
+ + 	/* implicitly true if otg:  host supports remote wakeup? */
+ + 	u8		rwc;
+ + 
+ + 	/* signaling pins used to talk to transceiver on usbN:
+ + 	 *  0 == usbN unused
+ + 	 *  2 == usb0-only, using internal transceiver
+ + 	 *  3 == 3 wire bidirectional
+ + 	 *  4 == 4 wire bidirectional
+ + 	 *  6 == 6 wire unidirectional (or TLL)
+ + 	 */
+ + 	u8		pins[3];
+ + 
+ + 	struct platform_device *udc_device;
+ + 	struct platform_device *ohci_device;
+ + 	struct platform_device *otg_device;
+ + 
+ + 	u32 (*usb0_init)(unsigned nwires, unsigned is_device);
+ + 	u32 (*usb1_init)(unsigned nwires);
+ + 	u32 (*usb2_init)(unsigned nwires, unsigned alt_pingroup);
+ + };
+ + 
+ + struct omap_lcd_config {
+ + 	char panel_name[16];
+ + 	char ctrl_name[16];
+ + 	s16  nreset_gpio;
+ + 	u8   data_lines;
+ + };
+ + 
+ + struct device;
+ + struct fb_info;
+ + struct omap_backlight_config {
+ + 	int default_intensity;
+ + 	int (*set_power)(struct device *dev, int state);
+ + };
+ + 
+ + struct omap_fbmem_config {
+ + 	u32 start;
+ + 	u32 size;
+ + };
+ + 
+ + struct omap_pwm_led_platform_data {
+ + 	const char *name;
+ + 	int intensity_timer;
+ + 	int blink_timer;
+ + 	void (*set_power)(struct omap_pwm_led_platform_data *self, int on_off);
+ + };
+ + 
+ + struct omap_uart_config {
+ + 	/* Bit field of UARTs present; bit 0 --> UART1 */
+ + 	unsigned int enabled_uarts;
+ + };
+ + 
+ + 
+ + struct omap_flash_part_config {
+ + 	char part_table[0];
+ + };
+ + 
+ + struct omap_boot_reason_config {
+ + 	char reason_str[12];
+ + };
+ + 
+ + struct omap_version_config {
+ + 	char component[12];
+ + 	char version[12];
+ + };
+ + 
+ + struct omap_board_config_entry {
+ + 	u16 tag;
+ + 	u16 len;
+ + 	u8  data[0];
+ + };
+ + 
+ + struct omap_board_config_kernel {
+ + 	u16 tag;
+ + 	const void *data;
+ + };
+ + 
+ + extern const void *__init __omap_get_config(u16 tag, size_t len, int nr);
+ + 
+ + #define omap_get_config(tag, type) \
+ + 	((const type *) __omap_get_config((tag), sizeof(type), 0))
+ + #define omap_get_nr_config(tag, type, nr) \
+ + 	((const type *) __omap_get_config((tag), sizeof(type), (nr)))
+ + 
+ + extern const void *__init omap_get_var_config(u16 tag, size_t *len);
+ + 
+ + extern struct omap_board_config_kernel *omap_board_config;
+ + extern int omap_board_config_size;
+ + 
+ + 
+ + /* for TI reference platforms sharing the same debug card */
+ + extern int debug_card_init(u32 addr, unsigned gpio);
+ + 
+ + /* OMAP3EVM revision */
+ + #if defined(CONFIG_MACH_OMAP3EVM)
+ + u8 get_omap3_evm_rev(void);
+ + #else
+ + #define get_omap3_evm_rev() (-EINVAL)
+ + #endif
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/clkdev_omap.h linux-3.2.1/arch/arm/plat-ckb/include/plat/clkdev_omap.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/clkdev_omap.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/clkdev_omap.h	2014-11-25 13:19:15.151027282 +0900
+ ***************
+ *** 0 ****
+ --- 1,53 ----
+ + /*
+ +  * clkdev <-> OMAP integration
+ +  *
+ +  * Russell King <linux@arm.linux.org.uk>
+ +  *
+ +  */
+ + 
+ + #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H
+ + #define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H
+ + 
+ + #include <linux/clkdev.h>
+ + 
+ + struct omap_clk {
+ + 	u16				cpu;
+ + 	struct clk_lookup		lk;
+ + };
+ + 
+ + #define CLK(dev, con, ck, cp) 		\
+ + 	{				\
+ + 		 .cpu = cp,		\
+ + 		.lk = {			\
+ + 			.dev_id = dev,	\
+ + 			.con_id = con,	\
+ + 			.clk = ck,	\
+ + 		},			\
+ + 	}
+ + 
+ + /* Platform flags for the clkdev-OMAP integration code */
+ + #define CK_310		(1 << 0)
+ + #define CK_7XX		(1 << 1)	/* 7xx, 850 */
+ + #define CK_1510		(1 << 2)
+ + #define CK_16XX		(1 << 3)	/* 16xx, 17xx, 5912 */
+ + #define CK_242X		(1 << 4)
+ + #define CK_243X		(1 << 5)	/* 243x, 253x */
+ + #define CK_3430ES1	(1 << 6)	/* 34xxES1 only */
+ + #define CK_3430ES2PLUS	(1 << 7)	/* 34xxES2, ES3, non-Sitara 35xx only */
+ + #define CK_3505		(1 << 8)
+ + #define CK_3517		(1 << 9)
+ + #define CK_36XX		(1 << 10)	/* 36xx/37xx-specific clocks */
+ + #define CK_443X		(1 << 11)
+ + #define CK_TI816X	(1 << 12)
+ + #define CK_446X		(1 << 13)
+ + #define CK_AM33XX	(1 << 14)	/* AM33xx specific clocks */
+ + #define CK_1710		(1 << 15)	/* 1710 extra for rate selection */
+ + 
+ + 
+ + #define CK_34XX		(CK_3430ES1 | CK_3430ES2PLUS)
+ + #define CK_AM35XX	(CK_3505 | CK_3517)	/* all Sitara AM35xx */
+ + #define CK_3XXX		(CK_34XX | CK_AM35XX | CK_36XX)
+ + 
+ + 
+ + #endif
+ + 
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/clock.h linux-3.2.1/arch/arm/plat-ckb/include/plat/clock.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/clock.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/clock.h	2014-11-25 13:19:15.156021277 +0900
+ ***************
+ *** 0 ****
+ --- 1,306 ----
+ + /*
+ +  * OMAP clock: data structure definitions, function prototypes, shared macros
+ +  *
+ +  * Copyright (C) 2004-2005, 2008-2010 Nokia Corporation
+ +  * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
+ +  * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #ifndef __ARCH_ARM_OMAP_CLOCK_H
+ + #define __ARCH_ARM_OMAP_CLOCK_H
+ + 
+ + #include <linux/list.h>
+ + 
+ + struct module;
+ + struct clk;
+ + struct clockdomain;
+ + 
+ + /**
+ +  * struct clkops - some clock function pointers
+ +  * @enable: fn ptr that enables the current clock in hardware
+ +  * @disable: fn ptr that enables the current clock in hardware
+ +  * @find_idlest: function returning the IDLEST register for the clock's IP blk
+ +  * @find_companion: function returning the "companion" clk reg for the clock
+ +  * @allow_idle: fn ptr that enables autoidle for the current clock in hardware
+ +  * @deny_idle: fn ptr that disables autoidle for the current clock in hardware
+ +  *
+ +  * A "companion" clk is an accompanying clock to the one being queried
+ +  * that must be enabled for the IP module connected to the clock to
+ +  * become accessible by the hardware.  Neither @find_idlest nor
+ +  * @find_companion should be needed; that information is IP
+ +  * block-specific; the hwmod code has been created to handle this, but
+ +  * until hwmod data is ready and drivers have been converted to use PM
+ +  * runtime calls in place of clk_enable()/clk_disable(), @find_idlest and
+ +  * @find_companion must, unfortunately, remain.
+ +  */
+ + struct clkops {
+ + 	int			(*enable)(struct clk *);
+ + 	void			(*disable)(struct clk *);
+ + 	void			(*find_idlest)(struct clk *, void __iomem **,
+ + 					       u8 *, u8 *);
+ + 	void			(*find_companion)(struct clk *, void __iomem **,
+ + 						  u8 *);
+ + 	void			(*allow_idle)(struct clk *);
+ + 	void			(*deny_idle)(struct clk *);
+ + };
+ + 
+ + 
+ + /* struct clksel_rate.flags possibilities */
+ + #define RATE_IN_242X		(1 << 0)
+ + #define RATE_IN_243X		(1 << 1)
+ + #define RATE_IN_3430ES1		(1 << 2)	/* 3430ES1 rates only */
+ + #define RATE_IN_3430ES2PLUS	(1 << 3)	/* 3430 ES >= 2 rates only */
+ + #define RATE_IN_36XX		(1 << 4)
+ + #define RATE_IN_4430		(1 << 5)
+ + #define RATE_IN_TI816X		(1 << 6)
+ + #define RATE_IN_4460		(1 << 7)
+ + #define RATE_IN_AM33XX		(1 << 8)
+ + #define RATE_IN_TI814X		(1 << 9)
+ + 
+ + #define RATE_IN_24XX		(RATE_IN_242X | RATE_IN_243X)
+ + #define RATE_IN_34XX		(RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
+ + #define RATE_IN_3XXX		(RATE_IN_34XX | RATE_IN_36XX)
+ + #define RATE_IN_44XX		(RATE_IN_4430 | RATE_IN_4460)
+ + 
+ + /* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
+ + #define RATE_IN_3430ES2PLUS_36XX	(RATE_IN_3430ES2PLUS | RATE_IN_36XX)
+ + 
+ + 
+ + /**
+ +  * struct clksel_rate - register bitfield values corresponding to clk divisors
+ +  * @val: register bitfield value (shifted to bit 0)
+ +  * @div: clock divisor corresponding to @val
+ +  * @flags: (see "struct clksel_rate.flags possibilities" above)
+ +  *
+ +  * @val should match the value of a read from struct clk.clksel_reg
+ +  * AND'ed with struct clk.clksel_mask, shifted right to bit 0.
+ +  *
+ +  * @div is the divisor that should be applied to the parent clock's rate
+ +  * to produce the current clock's rate.
+ +  */
+ + struct clksel_rate {
+ + 	u32			val;
+ + 	u8			div;
+ + 	u16			flags;
+ + };
+ + 
+ + /**
+ +  * struct clksel - available parent clocks, and a pointer to their divisors
+ +  * @parent: struct clk * to a possible parent clock
+ +  * @rates: available divisors for this parent clock
+ +  *
+ +  * A struct clksel is always associated with one or more struct clks
+ +  * and one or more struct clksel_rates.
+ +  */
+ + struct clksel {
+ + 	struct clk		 *parent;
+ + 	const struct clksel_rate *rates;
+ + };
+ + 
+ + /**
+ +  * struct dpll_data - DPLL registers and integration data
+ +  * @mult_div1_reg: register containing the DPLL M and N bitfields
+ +  * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
+ +  * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
+ +  * @clk_bypass: struct clk pointer to the clock's bypass clock input
+ +  * @clk_ref: struct clk pointer to the clock's reference clock input
+ +  * @control_reg: register containing the DPLL mode bitfield
+ +  * @enable_mask: mask of the DPLL mode bitfield in @control_reg
+ +  * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
+ +  * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
+ +  * @max_multiplier: maximum valid non-bypass multiplier value (actual)
+ +  * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
+ +  * @min_divider: minimum valid non-bypass divider value (actual)
+ +  * @max_divider: maximum valid non-bypass divider value (actual)
+ +  * @modes: possible values of @enable_mask
+ +  * @autoidle_reg: register containing the DPLL autoidle mode bitfield
+ +  * @idlest_reg: register containing the DPLL idle status bitfield
+ +  * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
+ +  * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
+ +  * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
+ +  * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
+ +  * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
+ +  * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
+ +  * @flags: DPLL type/features (see below)
+ +  *
+ +  * Possible values for @flags:
+ +  * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
+ +  *
+ +  * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
+ +  *
+ +  * XXX Some DPLLs have multiple bypass inputs, so it's not technically
+ +  * correct to only have one @clk_bypass pointer.
+ +  *
+ +  * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
+ +  * @last_rounded_n) should be separated from the runtime-fixed fields
+ +  * and placed into a different structure, so that the runtime-fixed data
+ +  * can be placed into read-only space.
+ +  */
+ + struct dpll_data {
+ + 	void __iomem		*mult_div1_reg;
+ + 	u32			mult_mask;
+ + 	u32			div1_mask;
+ + 	struct clk		*clk_bypass;
+ + 	struct clk		*clk_ref;
+ + 	void __iomem		*control_reg;
+ + 	u32			enable_mask;
+ + 	unsigned long		last_rounded_rate;
+ + 	u16			last_rounded_m;
+ + 	u16			max_multiplier;
+ + 	u8			last_rounded_n;
+ + 	u8			min_divider;
+ + 	u16			max_divider;
+ + 	u8			modes;
+ + 	void __iomem		*autoidle_reg;
+ + 	void __iomem		*idlest_reg;
+ + 	u32			autoidle_mask;
+ + 	u32			freqsel_mask;
+ + 	u32			idlest_mask;
+ + 	u32			dco_mask;
+ + 	u32			sddiv_mask;
+ + 	u8			auto_recal_bit;
+ + 	u8			recal_en_bit;
+ + 	u8			recal_st_bit;
+ + 	u8			flags;
+ + };
+ + 
+ + /*
+ +  * struct clk.flags possibilities
+ +  *
+ +  * XXX document the rest of the clock flags here
+ +  *
+ +  * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
+ +  *     bits share the same register.  This flag allows the
+ +  *     omap4_dpllmx*() code to determine which GATE_CTRL bit field
+ +  *     should be used.  This is a temporary solution - a better approach
+ +  *     would be to associate clock type-specific data with the clock,
+ +  *     similar to the struct dpll_data approach.
+ +  */
+ + #define ENABLE_REG_32BIT	(1 << 0)	/* Use 32-bit access */
+ + #define CLOCK_IDLE_CONTROL	(1 << 1)
+ + #define CLOCK_NO_IDLE_PARENT	(1 << 2)
+ + #define ENABLE_ON_INIT		(1 << 3)	/* Enable upon framework init */
+ + #define INVERT_ENABLE		(1 << 4)	/* 0 enables, 1 disables */
+ + #define CLOCK_CLKOUTX2		(1 << 5)
+ + 
+ + /**
+ +  * struct clk - OMAP struct clk
+ +  * @node: list_head connecting this clock into the full clock list
+ +  * @ops: struct clkops * for this clock
+ +  * @name: the name of the clock in the hardware (used in hwmod data and debug)
+ +  * @parent: pointer to this clock's parent struct clk
+ +  * @children: list_head connecting to the child clks' @sibling list_heads
+ +  * @sibling: list_head connecting this clk to its parent clk's @children
+ +  * @rate: current clock rate
+ +  * @enable_reg: register to write to enable the clock (see @enable_bit)
+ +  * @recalc: fn ptr that returns the clock's current rate
+ +  * @set_rate: fn ptr that can change the clock's current rate
+ +  * @round_rate: fn ptr that can round the clock's current rate
+ +  * @init: fn ptr to do clock-specific initialization
+ +  * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
+ +  * @usecount: number of users that have requested this clock to be enabled
+ +  * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div
+ +  * @flags: see "struct clk.flags possibilities" above
+ +  * @clksel_reg: for clksel clks, register va containing src/divisor select
+ +  * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
+ +  * @clksel: for clksel clks, pointer to struct clksel for this clock
+ +  * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
+ +  * @clkdm_name: clockdomain name that this clock is contained in
+ +  * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
+ +  * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
+ +  * @src_offset: bitshift for source selection bitfield (OMAP1 only)
+ +  *
+ +  * XXX @rate_offset, @src_offset should probably be removed and OMAP1
+ +  * clock code converted to use clksel.
+ +  *
+ +  * XXX @usecount is poorly named.  It should be "enable_count" or
+ +  * something similar.  "users" in the description refers to kernel
+ +  * code (core code or drivers) that have called clk_enable() and not
+ +  * yet called clk_disable(); the usecount of parent clocks is also
+ +  * incremented by the clock code when clk_enable() is called on child
+ +  * clocks and decremented by the clock code when clk_disable() is
+ +  * called on child clocks.
+ +  *
+ +  * XXX @clkdm, @usecount, @children, @sibling should be marked for
+ +  * internal use only.
+ +  *
+ +  * @children and @sibling are used to optimize parent-to-child clock
+ +  * tree traversals.  (child-to-parent traversals use @parent.)
+ +  *
+ +  * XXX The notion of the clock's current rate probably needs to be
+ +  * separated from the clock's target rate.
+ +  */
+ + struct clk {
+ + 	struct list_head	node;
+ + 	const struct clkops	*ops;
+ + 	const char		*name;
+ + 	struct clk		*parent;
+ + 	struct list_head	children;
+ + 	struct list_head	sibling;	/* node for children */
+ + 	unsigned long		rate;
+ + 	void __iomem		*enable_reg;
+ + 	unsigned long		(*recalc)(struct clk *);
+ + 	int			(*set_rate)(struct clk *, unsigned long);
+ + 	long			(*round_rate)(struct clk *, unsigned long);
+ + 	void			(*init)(struct clk *);
+ + 	u8			enable_bit;
+ + 	s8			usecount;
+ + 	u8			fixed_div;
+ + 	u8			flags;
+ + 	void __iomem		*clksel_reg;
+ + 	u32			clksel_mask;
+ + 	const struct clksel	*clksel;
+ + 	struct dpll_data	*dpll_data;
+ + 	const char		*clkdm_name;
+ + 	struct clockdomain	*clkdm;
+ + #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
+ + 	struct dentry		*dent;	/* For visible tree hierarchy */
+ + #endif
+ + };
+ + 
+ + struct cpufreq_frequency_table;
+ + 
+ + struct clk_functions {
+ + 	int		(*clk_enable)(struct clk *clk);
+ + 	void		(*clk_disable)(struct clk *clk);
+ + 	long		(*clk_round_rate)(struct clk *clk, unsigned long rate);
+ + 	int		(*clk_set_rate)(struct clk *clk, unsigned long rate);
+ + 	int		(*clk_set_parent)(struct clk *clk, struct clk *parent);
+ + 	void		(*clk_allow_idle)(struct clk *clk);
+ + 	void		(*clk_deny_idle)(struct clk *clk);
+ + 	void		(*clk_disable_unused)(struct clk *clk);
+ + #ifdef CONFIG_CPU_FREQ
+ + 	void		(*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
+ + 	void		(*clk_exit_cpufreq_table)(struct cpufreq_frequency_table **);
+ + #endif
+ + };
+ + 
+ + extern int mpurate;
+ + 
+ + extern int clk_init(struct clk_functions *custom_clocks);
+ + extern void clk_preinit(struct clk *clk);
+ + extern int clk_register(struct clk *clk);
+ + extern void clk_reparent(struct clk *child, struct clk *parent);
+ + extern void clk_unregister(struct clk *clk);
+ + extern void propagate_rate(struct clk *clk);
+ + extern void recalculate_root_clocks(void);
+ + extern unsigned long followparent_recalc(struct clk *clk);
+ + extern void clk_enable_init_clocks(void);
+ + unsigned long omap_fixed_divisor_recalc(struct clk *clk);
+ + #ifdef CONFIG_CPU_FREQ
+ + extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
+ + extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
+ + #endif
+ + extern struct clk *omap_clk_get_by_name(const char *name);
+ + extern int omap_clk_enable_autoidle_all(void);
+ + extern int omap_clk_disable_autoidle_all(void);
+ + 
+ + extern const struct clkops clkops_null;
+ + 
+ + extern struct clk dummy_ck;
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/common.h linux-3.2.1/arch/arm/plat-ckb/include/plat/common.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/common.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/common.h	2014-11-25 13:19:15.156021277 +0900
+ ***************
+ *** 0 ****
+ --- 1,41 ----
+ + /*
+ +  * arch/arm/plat-omap/include/mach/common.h
+ +  *
+ +  * Header for code common to all OMAP machines.
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify it
+ +  * under the terms of the GNU General Public License as published by the
+ +  * Free Software Foundation; either version 2 of the License, or (at your
+ +  * option) any later version.
+ +  *
+ +  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ +  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ +  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ +  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ +  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ +  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ +  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ +  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ +  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ +  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ +  *
+ +  * You should have received a copy of the  GNU General Public License along
+ +  * with this program; if not, write  to the Free Software Foundation, Inc.,
+ +  * 675 Mass Ave, Cambridge, MA 02139, USA.
+ +  */
+ + 
+ + #ifndef __ARCH_ARM_MACH_OMAP_COMMON_H
+ + #define __ARCH_ARM_MACH_OMAP_COMMON_H
+ + 
+ + #include <plat/i2c.h>
+ + #include <plat/omap_hwmod.h>
+ + 
+ + extern int __init omap_init_clocksource_32k(void);
+ + extern unsigned long long notrace omap_32k_sched_clock(void);
+ + 
+ + extern void omap_reserve(void);
+ + extern int omap_dss_reset(struct omap_hwmod *);
+ + 
+ + void omap_sram_init(void);
+ + 
+ + #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/config_pwm.h linux-3.2.1/arch/arm/plat-ckb/include/plat/config_pwm.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/config_pwm.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/config_pwm.h	2014-11-25 13:19:15.156021277 +0900
+ ***************
+ *** 0 ****
+ --- 1,26 ----
+ + #ifndef __CONFIG_CONFIG_PWM
+ + #define __CONFIG_CONFIG_PWM
+ + 
+ + #define AM33XX_CONFIG_BASE      (0x0)
+ + #define AM33XX_CONFIG_SIZE      (AM33XX_CONFIG_BASE + 0x10)
+ + #define AM33XX_ECAP_BASE        (0x0100)
+ + #define AM33XX_ECAP_SIZE        (AM33XX_ECAP_BASE + 0x080)
+ + #define AM33XX_EQEP_BASE        (0x0180)
+ + #define AM33XX_EQeP_SIZE        (AM33XX_EQEP_BASE + 0x080)
+ + #define AM33XX_EPWM_BASE        (0x0200)
+ + #define AM33XX_EPWM_SIZE        (AM33XX_EPWM_BASE + 0x0100)
+ + 
+ + #define PWMSS_CLKCONFIG          (0x08)
+ + #define ECAP_CLK_EN              (0x0)
+ + #define ECAP_CLK_STOP_REQ        (0x1)
+ + #define EQEP_CLK_EN              (0x4)
+ + #define EQEP_CLK_STOP_REQ        (0x5)
+ + #define EPWM_CLK_EN              (0x8)
+ + #define EPWM_CLK_STOP_REQ        (0x9)
+ + 
+ + #define SET                      (1)
+ + #define CLEAR                    (0)
+ + 
+ + #define PWM_CON_ID_STRING_LENGTH (12)
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/cpu.h linux-3.2.1/arch/arm/plat-ckb/include/plat/cpu.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/cpu.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/cpu.h	2014-11-25 14:03:18.039129000 +0900
+ ***************
+ *** 0 ****
+ --- 1,406 ----
+ + /*
+ +  * arch/arm/plat-omap/include/mach/cpu.h
+ +  *
+ +  * OMAP cpu type detection
+ +  *
+ +  * Copyright (C) 2004, 2008 Nokia Corporation
+ +  *
+ +  * Copyright (C) 2009-11 Texas Instruments.
+ +  *
+ +  * Written by Tony Lindgren <tony.lindgren@nokia.com>
+ +  *
+ +  * Added OMAP4 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; either version 2 of the License, or
+ +  * (at your option) any later version.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ +  *
+ +  */
+ + 
+ + #ifndef __ASM_ARCH_OMAP_CPU_H
+ + #define __ASM_ARCH_OMAP_CPU_H
+ + 
+ + #include <linux/bitops.h>
+ + #include <plat/multi.h>
+ + 
+ + /*
+ +  * Omap device type i.e. EMU/HS/TST/GP/BAD
+ +  */
+ + #define OMAP2_DEVICE_TYPE_TEST		0
+ + #define OMAP2_DEVICE_TYPE_EMU		1
+ + #define OMAP2_DEVICE_TYPE_SEC		2
+ + #define OMAP2_DEVICE_TYPE_GP		3
+ + #define OMAP2_DEVICE_TYPE_BAD		4
+ + 
+ + int omap_type(void);
+ + 
+ + /*
+ +  * omap_rev bits:
+ +  * CPU id bits	(0730, 1510, 1710, 2422...)	[31:16]
+ +  * CPU revision	(See _REV_ defined in cpu.h)	[15:08]
+ +  * CPU class bits (15xx, 16xx, 24xx, 34xx...)	[07:00]
+ +  */
+ + unsigned int omap_rev(void);
+ + 
+ + /*
+ +  * Get the CPU revision for OMAP devices
+ +  */
+ + #define GET_OMAP_REVISION()	((omap_rev() >> 8) & 0xff)
+ + 
+ + /*
+ +  * Macros to group OMAP into cpu classes.
+ +  * These can be used in most places.
+ +  * cpu_is_omap7xx():	True for OMAP730, OMAP850
+ +  * cpu_is_omap15xx():	True for OMAP1510, OMAP5910 and OMAP310
+ +  * cpu_is_omap16xx():	True for OMAP1610, OMAP5912 and OMAP1710
+ +  * cpu_is_omap24xx():	True for OMAP2420, OMAP2422, OMAP2423, OMAP2430
+ +  * cpu_is_omap242x():	True for OMAP2420, OMAP2422, OMAP2423
+ +  * cpu_is_omap243x():	True for OMAP2430
+ +  * cpu_is_omap343x():	True for OMAP3430
+ +  * cpu_is_omap443x():	True for OMAP4430
+ +  * cpu_is_omap446x():	True for OMAP4460
+ +  * cpu_is_omap447x():	True for OMAP4470
+ +  */
+ + #define GET_OMAP_CLASS	(omap_rev() & 0xff)
+ + 
+ + #define IS_OMAP_CLASS(class, id)			\
+ + static inline int is_omap ##class (void)		\
+ + {							\
+ + 	return (GET_OMAP_CLASS == (id)) ? 1 : 0;	\
+ + }
+ + 
+ + #define GET_AM_CLASS	((omap_rev() >> 24) & 0xff)
+ + 
+ + #define IS_AM_CLASS(class, id)				\
+ + static inline int is_am ##class (void)			\
+ + {							\
+ + 	return (GET_AM_CLASS == (id)) ? 1 : 0;		\
+ + }
+ + 
+ + #define GET_TI_CLASS	((omap_rev() >> 24) & 0xff)
+ + 
+ + #define IS_TI_CLASS(class, id)			\
+ + static inline int is_ti ##class (void)		\
+ + {							\
+ + 	return (GET_TI_CLASS == (id)) ? 1 : 0;	\
+ + }
+ + 
+ + #define GET_OMAP_SUBCLASS	((omap_rev() >> 20) & 0x0fff)
+ + 
+ + #define IS_OMAP_SUBCLASS(subclass, id)			\
+ + static inline int is_omap ##subclass (void)		\
+ + {							\
+ + 	return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;	\
+ + }
+ + 
+ + #define IS_TI_SUBCLASS(subclass, id)			\
+ + static inline int is_ti ##subclass (void)		\
+ + {							\
+ + 	return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;	\
+ + }
+ + 
+ + #define IS_AM_SUBCLASS(subclass, id)			\
+ + static inline int is_am ##subclass (void)		\
+ + {							\
+ + 	return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;	\
+ + }
+ + 
+ + IS_OMAP_CLASS(7xx, 0x07)
+ + IS_OMAP_CLASS(15xx, 0x15)
+ + IS_OMAP_CLASS(16xx, 0x16)
+ + IS_OMAP_CLASS(24xx, 0x24)
+ + IS_OMAP_CLASS(34xx, 0x34)
+ + IS_OMAP_CLASS(44xx, 0x44)
+ + IS_AM_CLASS(33xx, 0x33)
+ + 
+ + IS_TI_CLASS(81xx, 0x81)
+ + 
+ + IS_OMAP_SUBCLASS(242x, 0x242)
+ + IS_OMAP_SUBCLASS(243x, 0x243)
+ + IS_OMAP_SUBCLASS(343x, 0x343)
+ + IS_OMAP_SUBCLASS(363x, 0x363)
+ + IS_OMAP_SUBCLASS(443x, 0x443)
+ + IS_OMAP_SUBCLASS(446x, 0x446)
+ + IS_OMAP_SUBCLASS(447x, 0x447)
+ + 
+ + IS_TI_SUBCLASS(816x, 0x816)
+ + IS_TI_SUBCLASS(814x, 0x814)
+ + IS_AM_SUBCLASS(335x, 0x335)
+ + 
+ + #define cpu_is_omap7xx()		0
+ + #define cpu_is_omap15xx()		0
+ + #define cpu_is_omap16xx()		0
+ + #define cpu_is_omap24xx()		0
+ + #define cpu_is_omap242x()		0
+ + #define cpu_is_omap243x()		0
+ + #define cpu_is_omap34xx()		0
+ + #define cpu_is_omap343x()		0
+ + #define cpu_is_ti81xx()			0
+ + #define cpu_is_ti816x()			0
+ + #define cpu_is_ti814x()			0
+ + #define cpu_is_am33xx()			0
+ + #define cpu_is_am335x()			0
+ + #define cpu_is_omap44xx()		0
+ + #define cpu_is_omap443x()		0
+ + #define cpu_is_omap446x()		0
+ + #define cpu_is_omap447x()		0
+ + 
+ + #  undef  cpu_is_omap34xx
+ + #  define cpu_is_omap34xx()		1
+ + 
+ + /*
+ +  * Macros to detect individual cpu types.
+ +  * These are only rarely needed.
+ +  * cpu_is_omap330():	True for OMAP330
+ +  * cpu_is_omap730():	True for OMAP730
+ +  * cpu_is_omap850():	True for OMAP850
+ +  * cpu_is_omap1510():	True for OMAP1510
+ +  * cpu_is_omap1610():	True for OMAP1610
+ +  * cpu_is_omap1611():	True for OMAP1611
+ +  * cpu_is_omap5912():	True for OMAP5912
+ +  * cpu_is_omap1621():	True for OMAP1621
+ +  * cpu_is_omap1710():	True for OMAP1710
+ +  * cpu_is_omap2420():	True for OMAP2420
+ +  * cpu_is_omap2422():	True for OMAP2422
+ +  * cpu_is_omap2423():	True for OMAP2423
+ +  * cpu_is_omap2430():	True for OMAP2430
+ +  * cpu_is_omap3430():	True for OMAP3430
+ +  * cpu_is_omap4430():	True for OMAP4430
+ +  * cpu_is_omap3505():	True for OMAP3505
+ +  * cpu_is_omap3517():	True for OMAP3517
+ +  */
+ + #define GET_OMAP_TYPE	((omap_rev() >> 16) & 0xffff)
+ + 
+ + #define IS_OMAP_TYPE(type, id)				\
+ + static inline int is_omap ##type (void)			\
+ + {							\
+ + 	return (GET_OMAP_TYPE == (id)) ? 1 : 0;		\
+ + }
+ + 
+ + IS_OMAP_TYPE(310, 0x0310)
+ + IS_OMAP_TYPE(730, 0x0730)
+ + IS_OMAP_TYPE(850, 0x0850)
+ + IS_OMAP_TYPE(1510, 0x1510)
+ + IS_OMAP_TYPE(1610, 0x1610)
+ + IS_OMAP_TYPE(1611, 0x1611)
+ + IS_OMAP_TYPE(5912, 0x1611)
+ + IS_OMAP_TYPE(1621, 0x1621)
+ + IS_OMAP_TYPE(1710, 0x1710)
+ + IS_OMAP_TYPE(2420, 0x2420)
+ + IS_OMAP_TYPE(2422, 0x2422)
+ + IS_OMAP_TYPE(2423, 0x2423)
+ + IS_OMAP_TYPE(2430, 0x2430)
+ + IS_OMAP_TYPE(3430, 0x3430)
+ + IS_OMAP_TYPE(3505, 0x3517)
+ + IS_OMAP_TYPE(3517, 0x3517)
+ + 
+ + #define cpu_is_omap310()		0
+ + #define cpu_is_omap730()		0
+ + #define cpu_is_omap850()		0
+ + #define cpu_is_omap1510()		0
+ + #define cpu_is_omap1610()		0
+ + #define cpu_is_omap5912()		0
+ + #define cpu_is_omap1611()		0
+ + #define cpu_is_omap1621()		0
+ + #define cpu_is_omap1710()		0
+ + #define cpu_is_omap2420()		0
+ + #define cpu_is_omap2422()		0
+ + #define cpu_is_omap2423()		0
+ + #define cpu_is_omap2430()		0
+ + #define cpu_is_omap3503()		0
+ + #define cpu_is_omap3515()		0
+ + #define cpu_is_omap3525()		0
+ + #define cpu_is_omap3530()		0
+ + #define cpu_is_omap3505()		0
+ + #define cpu_is_omap3517()		0
+ + #define cpu_is_omap3430()		0
+ + #define cpu_is_omap4430()		0
+ + #define cpu_is_omap3630()		0
+ + 
+ + /*
+ +  * Whether we have MULTI_OMAP1 or not, we still need to distinguish
+ +  * between 730 vs 850, 330 vs. 1510 and 1611B/5912 vs. 1710.
+ +  */
+ + 
+ + #if defined(CONFIG_ARCH_OMAP730)
+ + # undef  cpu_is_omap730
+ + # define cpu_is_omap730()		is_omap730()
+ + #endif
+ + 
+ + #if defined(CONFIG_ARCH_OMAP850)
+ + # undef  cpu_is_omap850
+ + # define cpu_is_omap850()		is_omap850()
+ + #endif
+ + 
+ + #if defined(CONFIG_ARCH_OMAP15XX)
+ + # undef  cpu_is_omap310
+ + # undef  cpu_is_omap1510
+ + # define cpu_is_omap310()		is_omap310()
+ + # define cpu_is_omap1510()		is_omap1510()
+ + #endif
+ + 
+ + # undef cpu_is_omap3430
+ + # undef cpu_is_omap3503
+ + # undef cpu_is_omap3515
+ + # undef cpu_is_omap3525
+ + # undef cpu_is_omap3530
+ + # undef cpu_is_omap3505
+ + # undef cpu_is_omap3517
+ + # undef cpu_is_ti81xx
+ + # undef cpu_is_ti816x
+ + # undef cpu_is_ti814x
+ + # undef cpu_is_am33xx
+ + # undef cpu_is_am335x
+ + # define cpu_is_omap3430()		is_omap3430()
+ + # define cpu_is_omap3503()		(cpu_is_omap3430() &&		\
+ + 						(!omap3_has_iva()) &&	\
+ + 						(!omap3_has_sgx()))
+ + # define cpu_is_omap3515()		(cpu_is_omap3430() &&		\
+ + 						(!omap3_has_iva()) &&	\
+ + 						(omap3_has_sgx()))
+ + # define cpu_is_omap3525()		(cpu_is_omap3430() &&		\
+ + 						(!omap3_has_sgx()) &&	\
+ + 						(omap3_has_iva()))
+ + # define cpu_is_omap3530()		(cpu_is_omap3430())
+ + # define cpu_is_omap3517()		is_omap3517()
+ + # define cpu_is_omap3505()		(cpu_is_omap3517() &&		\
+ + 						!omap3_has_sgx())
+ + # undef cpu_is_omap3630
+ + # define cpu_is_omap3630()		is_omap363x()
+ + # define cpu_is_ti81xx()		is_ti81xx()
+ + # define cpu_is_ti816x()		is_ti816x()
+ + # define cpu_is_ti814x()		is_ti814x()
+ + # define cpu_is_am33xx()		is_am33xx()
+ + # define cpu_is_am335x()		is_am335x()
+ + 
+ + /* Macros to detect if we have OMAP1 or OMAP2 */
+ + #define cpu_class_is_omap1()	(cpu_is_omap7xx() || cpu_is_omap15xx() || \
+ + 				cpu_is_omap16xx())
+ + #define cpu_class_is_omap2()	(cpu_is_omap24xx() || cpu_is_omap34xx() || \
+ + 				cpu_is_omap44xx())
+ + 
+ + /* Various silicon revisions for omap2 */
+ + #define OMAP242X_CLASS		0x24200024
+ + #define OMAP2420_REV_ES1_0	OMAP242X_CLASS
+ + #define OMAP2420_REV_ES2_0	(OMAP242X_CLASS | (0x1 << 8))
+ + 
+ + #define OMAP243X_CLASS		0x24300024
+ + #define OMAP2430_REV_ES1_0	OMAP243X_CLASS
+ + 
+ + #define OMAP343X_CLASS		0x34300034
+ + #define OMAP3430_REV_ES1_0	OMAP343X_CLASS
+ + #define OMAP3430_REV_ES2_0	(OMAP343X_CLASS | (0x1 << 8))
+ + #define OMAP3430_REV_ES2_1	(OMAP343X_CLASS | (0x2 << 8))
+ + #define OMAP3430_REV_ES3_0	(OMAP343X_CLASS | (0x3 << 8))
+ + #define OMAP3430_REV_ES3_1	(OMAP343X_CLASS | (0x4 << 8))
+ + #define OMAP3430_REV_ES3_1_2	(OMAP343X_CLASS | (0x5 << 8))
+ + 
+ + #define OMAP363X_CLASS		0x36300034
+ + #define OMAP3630_REV_ES1_0	OMAP363X_CLASS
+ + #define OMAP3630_REV_ES1_1	(OMAP363X_CLASS | (0x1 << 8))
+ + #define OMAP3630_REV_ES1_2	(OMAP363X_CLASS | (0x2 << 8))
+ + 
+ + #define OMAP3517_CLASS		0x35170034
+ + #define OMAP3517_REV_ES1_0	OMAP3517_CLASS
+ + #define OMAP3517_REV_ES1_1	(OMAP3517_CLASS | (0x1 << 8))
+ + 
+ + #define TI816X_CLASS		0x81600034
+ + #define TI8168_REV_ES1_0	TI816X_CLASS
+ + #define TI8168_REV_ES1_1	(TI816X_CLASS | (0x1 << 8))
+ + 
+ + #define TI814X_CLASS		0x81400034
+ + #define TI8148_REV_ES1_0	TI814X_CLASS
+ + #define TI8148_REV_ES2_0	(TI814X_CLASS | (0x1 << 8))
+ + #define TI8148_REV_ES2_1	(TI814X_CLASS | (0x2 << 8))
+ + 
+ + #define AM335X_CLASS		0x33500034
+ + #define AM335X_REV_ES1_0	AM335X_CLASS
+ + #define AM335X_REV_ES2_0	(AM335X_CLASS | (0x1 << 8))
+ + #define AM335X_REV_ES2_1	(AM335X_CLASS | (0x2 << 8))
+ + 
+ + #define OMAP443X_CLASS		0x44300044
+ + #define OMAP4430_REV_ES1_0	(OMAP443X_CLASS | (0x10 << 8))
+ + #define OMAP4430_REV_ES2_0	(OMAP443X_CLASS | (0x20 << 8))
+ + #define OMAP4430_REV_ES2_1	(OMAP443X_CLASS | (0x21 << 8))
+ + #define OMAP4430_REV_ES2_2	(OMAP443X_CLASS | (0x22 << 8))
+ + #define OMAP4430_REV_ES2_3	(OMAP443X_CLASS | (0x23 << 8))
+ + 
+ + #define OMAP446X_CLASS		0x44600044
+ + #define OMAP4460_REV_ES1_0	(OMAP446X_CLASS | (0x10 << 8))
+ + 
+ + #define OMAP447X_CLASS		0x44700044
+ + #define OMAP4470_REV_ES1_0	(OMAP447X_CLASS | (0x10 << 8))
+ + 
+ + void omap2xxx_check_revision(void);
+ + void omap3xxx_check_revision(void);
+ + void omap4xxx_check_revision(void);
+ + void ti81xx_check_features(void);
+ + void am33xx_check_features(void);
+ + void omap4xxx_check_features(void);
+ + 
+ + /*
+ +  * Runtime detection of OMAP3 features
+ +  *
+ +  * OMAP3_HAS_IO_CHAIN_CTRL: Some later members of the OMAP3 chip
+ +  *    family have OS-level control over the I/O chain clock.  This is
+ +  *    to avoid a window during which wakeups could potentially be lost
+ +  *    during powerdomain transitions.  If this bit is set, it
+ +  *    indicates that the chip does support OS-level control of this
+ +  *    feature.
+ +  */
+ + extern u32 omap_features;
+ + 
+ + #define OMAP3_HAS_L2CACHE		BIT(0)
+ + #define OMAP3_HAS_IVA			BIT(1)
+ + #define OMAP3_HAS_SGX			BIT(2)
+ + #define OMAP3_HAS_NEON			BIT(3)
+ + #define OMAP3_HAS_ISP			BIT(4)
+ + #define OMAP3_HAS_192MHZ_CLK		BIT(5)
+ + #define OMAP3_HAS_IO_WAKEUP		BIT(6)
+ + #define OMAP3_HAS_SDRC			BIT(7)
+ + #define OMAP3_HAS_IO_CHAIN_CTRL		BIT(8)
+ + #define OMAP4_HAS_MPU_1GHZ		BIT(9)
+ + #define OMAP4_HAS_MPU_1_2GHZ		BIT(10)
+ + #define OMAP4_HAS_MPU_1_5GHZ		BIT(11)
+ + 
+ + 
+ + #define OMAP3_HAS_FEATURE(feat,flag)			\
+ + static inline unsigned int omap3_has_ ##feat(void)	\
+ + {							\
+ + 	return omap_features & OMAP3_HAS_ ##flag;	\
+ + }							\
+ + 
+ + OMAP3_HAS_FEATURE(l2cache, L2CACHE)
+ + OMAP3_HAS_FEATURE(sgx, SGX)
+ + OMAP3_HAS_FEATURE(iva, IVA)
+ + OMAP3_HAS_FEATURE(neon, NEON)
+ + OMAP3_HAS_FEATURE(isp, ISP)
+ + OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK)
+ + OMAP3_HAS_FEATURE(io_wakeup, IO_WAKEUP)
+ + OMAP3_HAS_FEATURE(sdrc, SDRC)
+ + OMAP3_HAS_FEATURE(io_chain_ctrl, IO_CHAIN_CTRL)
+ + 
+ + /*
+ +  * Runtime detection of OMAP4 features
+ +  */
+ + #define OMAP4_HAS_FEATURE(feat, flag)			\
+ + static inline unsigned int omap4_has_ ##feat(void)	\
+ + {							\
+ + 	return omap_features & OMAP4_HAS_ ##flag;	\
+ + }							\
+ + 
+ + OMAP4_HAS_FEATURE(mpu_1ghz, MPU_1GHZ)
+ + OMAP4_HAS_FEATURE(mpu_1_2ghz, MPU_1_2GHZ)
+ + OMAP4_HAS_FEATURE(mpu_1_5ghz, MPU_1_5GHZ)
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/dma-33xx.h linux-3.2.1/arch/arm/plat-ckb/include/plat/dma-33xx.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/dma-33xx.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/dma-33xx.h	2014-11-25 13:19:15.160029504 +0900
+ ***************
+ *** 0 ****
+ --- 1,87 ----
+ + /*
+ +  * AM33XX SDMA channel definitions
+ +  *
+ +  * This file is automatically generated from the AM33XX hardware databases.
+ +  *
+ +  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #ifndef __ARCH_ARM_MACH_OMAP2_AM33XX_DMA_H
+ + #define __ARCH_ARM_MACH_OMAP2_AM33XX_DMA_H
+ + 
+ + 
+ + #define AM33XX_DMA_ICSS0_7				0
+ + #define AM33XX_DMA_ICSS0_6				1
+ + #define AM33XX_DMA_MMCHS1_W				2
+ + #define AM33XX_DMA_MMCHS1_R				3
+ + #define AM33XX_DMA_AESEIP36T0_CTXIN			4
+ + #define AM33XX_DMA_AESEIP36T0_DIN			5
+ + #define AM33XX_DMA_AESEIP36T0_DOUT			6
+ + #define AM33XX_DMA_AESEIP36T0_CTXOUT			7
+ + #define AM33XX_DMA_MCASP0_X				8
+ + #define AM33XX_DMA_MCASP0_R				9
+ + #define AM33XX_DMA_MCASP1_X				10
+ + #define AM33XX_DMA_MCASP1_R				11
+ + #define AM33XX_DMA_MCASP2_X				12
+ + #define AM33XX_DMA_MCASP2_R				13
+ + #define AM33XX_DMA_PWMSS0_EPWM				14
+ + #define AM33XX_DMA_PWMSS1_EPWM				15
+ + #define AM33XX_DMA_SPIOCP0_CH0W				16
+ + #define AM33XX_DMA_SPIOCP0_CH0R				17
+ + #define AM33XX_DMA_SPIOCP0_CH1W				18
+ + #define AM33XX_DMA_SPIOCP0_CH1R				19
+ + #define AM33XX_DMA_SPIOCP3_CH1W				20
+ + #define AM33XX_DMA_SPIOCP3_CH1R				21
+ + #define AM33XX_DMA_GPIO					22
+ + #define AM33XX_DMA_GPIO1				23
+ + #define AM33XX_DMA_MMCHS0_W				24
+ + #define AM33XX_DMA_MMCHS0_R				25
+ + #define AM33XX_DMA_UART0_0				26
+ + #define AM33XX_DMA_UART0_1				27
+ + #define AM33XX_DMA_UART1_0				28
+ + #define AM33XX_DMA_UART1_1				29
+ + #define AM33XX_DMA_UART2_0				30
+ + #define AM33XX_DMA_UART2_1				31
+ + #define AM33XX_DMA_DESEIP16T0_IN			32
+ + #define AM33XX_DMA_DESEIP16T0				33
+ + #define AM33XX_DMA_DESEIP16T0_OUT			34
+ + #define AM33XX_DMA_SHAEIP57T0_CTXIN			35
+ + #define AM33XX_DMA_SHAEIP57T0_DIN			36
+ + #define AM33XX_DMA_SHAEIP57T0_CTXOUT			37
+ + #define AM33XX_DMA_PWMSS0_ECAP				38
+ + #define AM33XX_DMA_PWMSS1_ECAP				39
+ + #define AM33XX_DMA_DCAN_1				40
+ + #define AM33XX_DMA_DCAN_2				41
+ + #define AM33XX_DMA_SPIOCP1_CH0W				42
+ + #define AM33XX_DMA_SPIOCP1_CH0R				43
+ + #define AM33XX_DMA_SPIOCP1_CH1W				44
+ + #define AM33XX_DMA_SPIOCP1_CH1R				45
+ + #define AM33XX_DMA_PWMSS0_EQEP				46
+ + #define AM33XX_DMA_DCAN_3				47
+ + #define AM33XX_DMA_TIMER_4				48
+ + #define AM33XX_DMA_TIMER_5				49
+ + #define AM33XX_DMA_TIMER_6				50
+ + #define AM33XX_DMA_TIMER_7				51
+ + #define AM33XX_DMA_GPM					52
+ + #define AM33XX_DMA_ADC0					53
+ + #define AM33XX_DMA_PWMSS1_EQEP				56
+ + #define AM33XX_DMA_ADC1					57
+ + #define AM33XX_DMA_MSHSI2COCP0_TX			58
+ + #define AM33XX_DMA_MSHSI2COCP0_RX			59
+ + #define AM33XX_DMA_MSHSI2COCP1_TX			60
+ + #define AM33XX_DMA_MSHSI2COCP1_RX			61
+ + #define AM33XX_DMA_PWMSS2_ECAP				62
+ + #define AM33XX_DMA_PWMSS2_EPW				63
+ + #define AM33XX_DMA_MMCHS2_W				64	/* xBar */
+ + #define AM33XX_DMA_MMCHS2_R				65	/* xBar */
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/dma-44xx.h linux-3.2.1/arch/arm/plat-ckb/include/plat/dma-44xx.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/dma-44xx.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/dma-44xx.h	2014-11-25 13:19:15.160029504 +0900
+ ***************
+ *** 0 ****
+ --- 1,147 ----
+ + /*
+ +  * OMAP4 SDMA channel definitions
+ +  *
+ +  * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ +  * Copyright (C) 2009-2010 Nokia Corporation
+ +  *
+ +  * Santosh Shilimkar (santosh.shilimkar@ti.com)
+ +  * Benoit Cousson (b-cousson@ti.com)
+ +  * Paul Walmsley (paul@pwsan.com)
+ +  *
+ +  * This file is automatically generated from the OMAP hardware databases.
+ +  * We respectfully ask that any modifications to this file be coordinated
+ +  * with the public linux-omap@vger.kernel.org mailing list and the
+ +  * authors above to ensure that the autogeneration scripts are kept
+ +  * up-to-date with the file contents.
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #ifndef __ARCH_ARM_MACH_OMAP2_OMAP44XX_DMA_H
+ + #define __ARCH_ARM_MACH_OMAP2_OMAP44XX_DMA_H
+ + 
+ + #define OMAP44XX_DMA_SYS_REQ0			2
+ + #define OMAP44XX_DMA_SYS_REQ1			3
+ + #define OMAP44XX_DMA_GPMC			4
+ + #define OMAP44XX_DMA_DSS_DISPC_REQ		6
+ + #define OMAP44XX_DMA_SYS_REQ2			7
+ + #define OMAP44XX_DMA_MCASP1_AXEVT		8
+ + #define OMAP44XX_DMA_ISS_REQ1			9
+ + #define OMAP44XX_DMA_ISS_REQ2			10
+ + #define OMAP44XX_DMA_MCASP1_AREVT		11
+ + #define OMAP44XX_DMA_ISS_REQ3			12
+ + #define OMAP44XX_DMA_ISS_REQ4			13
+ + #define OMAP44XX_DMA_DSS_RFBI_REQ		14
+ + #define OMAP44XX_DMA_SPI3_TX0			15
+ + #define OMAP44XX_DMA_SPI3_RX0			16
+ + #define OMAP44XX_DMA_MCBSP2_TX			17
+ + #define OMAP44XX_DMA_MCBSP2_RX			18
+ + #define OMAP44XX_DMA_MCBSP3_TX			19
+ + #define OMAP44XX_DMA_MCBSP3_RX			20
+ + #define OMAP44XX_DMA_C2C_SSCM_GPO0		21
+ + #define OMAP44XX_DMA_C2C_SSCM_GPO1		22
+ + #define OMAP44XX_DMA_SPI3_TX1			23
+ + #define OMAP44XX_DMA_SPI3_RX1			24
+ + #define OMAP44XX_DMA_I2C3_TX			25
+ + #define OMAP44XX_DMA_I2C3_RX			26
+ + #define OMAP44XX_DMA_I2C1_TX			27
+ + #define OMAP44XX_DMA_I2C1_RX			28
+ + #define OMAP44XX_DMA_I2C2_TX			29
+ + #define OMAP44XX_DMA_I2C2_RX			30
+ + #define OMAP44XX_DMA_MCBSP4_TX			31
+ + #define OMAP44XX_DMA_MCBSP4_RX			32
+ + #define OMAP44XX_DMA_MCBSP1_TX			33
+ + #define OMAP44XX_DMA_MCBSP1_RX			34
+ + #define OMAP44XX_DMA_SPI1_TX0			35
+ + #define OMAP44XX_DMA_SPI1_RX0			36
+ + #define OMAP44XX_DMA_SPI1_TX1			37
+ + #define OMAP44XX_DMA_SPI1_RX1			38
+ + #define OMAP44XX_DMA_SPI1_TX2			39
+ + #define OMAP44XX_DMA_SPI1_RX2			40
+ + #define OMAP44XX_DMA_SPI1_TX3			41
+ + #define OMAP44XX_DMA_SPI1_RX3			42
+ + #define OMAP44XX_DMA_SPI2_TX0			43
+ + #define OMAP44XX_DMA_SPI2_RX0			44
+ + #define OMAP44XX_DMA_SPI2_TX1			45
+ + #define OMAP44XX_DMA_SPI2_RX1			46
+ + #define OMAP44XX_DMA_MMC2_TX			47
+ + #define OMAP44XX_DMA_MMC2_RX			48
+ + #define OMAP44XX_DMA_UART1_TX			49
+ + #define OMAP44XX_DMA_UART1_RX			50
+ + #define OMAP44XX_DMA_UART2_TX			51
+ + #define OMAP44XX_DMA_UART2_RX			52
+ + #define OMAP44XX_DMA_UART3_TX			53
+ + #define OMAP44XX_DMA_UART3_RX			54
+ + #define OMAP44XX_DMA_UART4_TX			55
+ + #define OMAP44XX_DMA_UART4_RX			56
+ + #define OMAP44XX_DMA_MMC4_TX			57
+ + #define OMAP44XX_DMA_MMC4_RX			58
+ + #define OMAP44XX_DMA_MMC5_TX			59
+ + #define OMAP44XX_DMA_MMC5_RX			60
+ + #define OMAP44XX_DMA_MMC1_TX			61
+ + #define OMAP44XX_DMA_MMC1_RX			62
+ + #define OMAP44XX_DMA_SYS_REQ3			64
+ + #define OMAP44XX_DMA_MCPDM_UP			65
+ + #define OMAP44XX_DMA_MCPDM_DL			66
+ + #define OMAP44XX_DMA_DMIC_REQ			67
+ + #define OMAP44XX_DMA_C2C_SSCM_GPO2		68
+ + #define OMAP44XX_DMA_C2C_SSCM_GPO3		69
+ + #define OMAP44XX_DMA_SPI4_TX0			70
+ + #define OMAP44XX_DMA_SPI4_RX0			71
+ + #define OMAP44XX_DMA_DSS_DSI1_REQ0		72
+ + #define OMAP44XX_DMA_DSS_DSI1_REQ1		73
+ + #define OMAP44XX_DMA_DSS_DSI1_REQ2		74
+ + #define OMAP44XX_DMA_DSS_DSI1_REQ3		75
+ + #define OMAP44XX_DMA_DSS_HDMI_REQ		76
+ + #define OMAP44XX_DMA_MMC3_TX			77
+ + #define OMAP44XX_DMA_MMC3_RX			78
+ + #define OMAP44XX_DMA_USIM_TX			79
+ + #define OMAP44XX_DMA_USIM_RX			80
+ + #define OMAP44XX_DMA_DSS_DSI2_REQ0		81
+ + #define OMAP44XX_DMA_DSS_DSI2_REQ1		82
+ + #define OMAP44XX_DMA_DSS_DSI2_REQ2		83
+ + #define OMAP44XX_DMA_DSS_DSI2_REQ3		84
+ + #define OMAP44XX_DMA_SLIMBUS1_TX0		85
+ + #define OMAP44XX_DMA_SLIMBUS1_TX1		86
+ + #define OMAP44XX_DMA_SLIMBUS1_TX2		87
+ + #define OMAP44XX_DMA_SLIMBUS1_TX3		88
+ + #define OMAP44XX_DMA_SLIMBUS1_RX0		89
+ + #define OMAP44XX_DMA_SLIMBUS1_RX1		90
+ + #define OMAP44XX_DMA_SLIMBUS1_RX2		91
+ + #define OMAP44XX_DMA_SLIMBUS1_RX3		92
+ + #define OMAP44XX_DMA_SLIMBUS2_TX0		93
+ + #define OMAP44XX_DMA_SLIMBUS2_TX1		94
+ + #define OMAP44XX_DMA_SLIMBUS2_TX2		95
+ + #define OMAP44XX_DMA_SLIMBUS2_TX3		96
+ + #define OMAP44XX_DMA_SLIMBUS2_RX0		97
+ + #define OMAP44XX_DMA_SLIMBUS2_RX1		98
+ + #define OMAP44XX_DMA_SLIMBUS2_RX2		99
+ + #define OMAP44XX_DMA_SLIMBUS2_RX3		100
+ + #define OMAP44XX_DMA_ABE_REQ_0			101
+ + #define OMAP44XX_DMA_ABE_REQ_1			102
+ + #define OMAP44XX_DMA_ABE_REQ_2			103
+ + #define OMAP44XX_DMA_ABE_REQ_3			104
+ + #define OMAP44XX_DMA_ABE_REQ_4			105
+ + #define OMAP44XX_DMA_ABE_REQ_5			106
+ + #define OMAP44XX_DMA_ABE_REQ_6			107
+ + #define OMAP44XX_DMA_ABE_REQ_7			108
+ + #define OMAP44XX_DMA_AES1_P_CTX_IN_REQ		109
+ + #define OMAP44XX_DMA_AES1_P_DATA_IN_REQ		110
+ + #define OMAP44XX_DMA_AES1_P_DATA_OUT_REQ	111
+ + #define OMAP44XX_DMA_AES2_P_CTX_IN_REQ		112
+ + #define OMAP44XX_DMA_AES2_P_DATA_IN_REQ		113
+ + #define OMAP44XX_DMA_AES2_P_DATA_OUT_REQ	114
+ + #define OMAP44XX_DMA_DES_P_CTX_IN_REQ		115
+ + #define OMAP44XX_DMA_DES_P_DATA_IN_REQ		116
+ + #define OMAP44XX_DMA_DES_P_DATA_OUT_REQ		117
+ + #define OMAP44XX_DMA_SHA2_CTXIN_P		118
+ + #define OMAP44XX_DMA_SHA2_DIN_P			119
+ + #define OMAP44XX_DMA_SHA2_CTXOUT_P		120
+ + #define OMAP44XX_DMA_AES1_P_CONTEXT_OUT_REQ	121
+ + #define OMAP44XX_DMA_AES2_P_CONTEXT_OUT_REQ	122
+ + #define OMAP44XX_DMA_I2C4_TX			124
+ + #define OMAP44XX_DMA_I2C4_RX			125
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/dma.h linux-3.2.1/arch/arm/plat-ckb/include/plat/dma.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/dma.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/dma.h	2014-11-25 13:19:15.160029504 +0900
+ ***************
+ *** 0 ****
+ --- 1,535 ----
+ + /*
+ +  *  arch/arm/plat-omap/include/mach/dma.h
+ +  *
+ +  *  Copyright (C) 2003 Nokia Corporation
+ +  *  Author: Juha Yrjölä <juha.yrjola@nokia.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; either version 2 of the License, or
+ +  * (at your option) any later version.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ +  */
+ + #ifndef __ASM_ARCH_DMA_H
+ + #define __ASM_ARCH_DMA_H
+ + 
+ + #include <linux/platform_device.h>
+ + 
+ + /*
+ +  * TODO: These dma channel defines should go away once all
+ +  * the omap drivers hwmod adapted.
+ +  */
+ + 
+ + /* Move omap4 specific defines to dma-44xx.h */
+ + #include "dma-44xx.h"
+ + #include "dma-33xx.h"
+ + 
+ + /* DMA channels for omap1 */
+ + #define OMAP_DMA_NO_DEVICE		0
+ + #define OMAP_DMA_MCSI1_TX		1
+ + #define OMAP_DMA_MCSI1_RX		2
+ + #define OMAP_DMA_I2C_RX			3
+ + #define OMAP_DMA_I2C_TX			4
+ + #define OMAP_DMA_EXT_NDMA_REQ		5
+ + #define OMAP_DMA_EXT_NDMA_REQ2		6
+ + #define OMAP_DMA_UWIRE_TX		7
+ + #define OMAP_DMA_MCBSP1_TX		8
+ + #define OMAP_DMA_MCBSP1_RX		9
+ + #define OMAP_DMA_MCBSP3_TX		10
+ + #define OMAP_DMA_MCBSP3_RX		11
+ + #define OMAP_DMA_UART1_TX		12
+ + #define OMAP_DMA_UART1_RX		13
+ + #define OMAP_DMA_UART2_TX		14
+ + #define OMAP_DMA_UART2_RX		15
+ + #define OMAP_DMA_MCBSP2_TX		16
+ + #define OMAP_DMA_MCBSP2_RX		17
+ + #define OMAP_DMA_UART3_TX		18
+ + #define OMAP_DMA_UART3_RX		19
+ + #define OMAP_DMA_CAMERA_IF_RX		20
+ + #define OMAP_DMA_MMC_TX			21
+ + #define OMAP_DMA_MMC_RX			22
+ + #define OMAP_DMA_NAND			23
+ + #define OMAP_DMA_IRQ_LCD_LINE		24
+ + #define OMAP_DMA_MEMORY_STICK		25
+ + #define OMAP_DMA_USB_W2FC_RX0		26
+ + #define OMAP_DMA_USB_W2FC_RX1		27
+ + #define OMAP_DMA_USB_W2FC_RX2		28
+ + #define OMAP_DMA_USB_W2FC_TX0		29
+ + #define OMAP_DMA_USB_W2FC_TX1		30
+ + #define OMAP_DMA_USB_W2FC_TX2		31
+ + 
+ + /* These are only for 1610 */
+ + #define OMAP_DMA_CRYPTO_DES_IN		32
+ + #define OMAP_DMA_SPI_TX			33
+ + #define OMAP_DMA_SPI_RX			34
+ + #define OMAP_DMA_CRYPTO_HASH		35
+ + #define OMAP_DMA_CCP_ATTN		36
+ + #define OMAP_DMA_CCP_FIFO_NOT_EMPTY	37
+ + #define OMAP_DMA_CMT_APE_TX_CHAN_0	38
+ + #define OMAP_DMA_CMT_APE_RV_CHAN_0	39
+ + #define OMAP_DMA_CMT_APE_TX_CHAN_1	40
+ + #define OMAP_DMA_CMT_APE_RV_CHAN_1	41
+ + #define OMAP_DMA_CMT_APE_TX_CHAN_2	42
+ + #define OMAP_DMA_CMT_APE_RV_CHAN_2	43
+ + #define OMAP_DMA_CMT_APE_TX_CHAN_3	44
+ + #define OMAP_DMA_CMT_APE_RV_CHAN_3	45
+ + #define OMAP_DMA_CMT_APE_TX_CHAN_4	46
+ + #define OMAP_DMA_CMT_APE_RV_CHAN_4	47
+ + #define OMAP_DMA_CMT_APE_TX_CHAN_5	48
+ + #define OMAP_DMA_CMT_APE_RV_CHAN_5	49
+ + #define OMAP_DMA_CMT_APE_TX_CHAN_6	50
+ + #define OMAP_DMA_CMT_APE_RV_CHAN_6	51
+ + #define OMAP_DMA_CMT_APE_TX_CHAN_7	52
+ + #define OMAP_DMA_CMT_APE_RV_CHAN_7	53
+ + #define OMAP_DMA_MMC2_TX		54
+ + #define OMAP_DMA_MMC2_RX		55
+ + #define OMAP_DMA_CRYPTO_DES_OUT		56
+ + 
+ + /* DMA channels for 24xx */
+ + #define OMAP24XX_DMA_NO_DEVICE		0
+ + #define OMAP24XX_DMA_XTI_DMA		1	/* S_DMA_0 */
+ + #define OMAP24XX_DMA_EXT_DMAREQ0	2	/* S_DMA_1 */
+ + #define OMAP24XX_DMA_EXT_DMAREQ1	3	/* S_DMA_2 */
+ + #define OMAP24XX_DMA_GPMC		4	/* S_DMA_3 */
+ + #define OMAP24XX_DMA_GFX		5	/* S_DMA_4 */
+ + #define OMAP24XX_DMA_DSS		6	/* S_DMA_5 */
+ + #define OMAP242X_DMA_VLYNQ_TX		7	/* S_DMA_6 */
+ + #define OMAP24XX_DMA_EXT_DMAREQ2	7	/* S_DMA_6 */
+ + #define OMAP24XX_DMA_CWT		8	/* S_DMA_7 */
+ + #define OMAP24XX_DMA_AES_TX		9	/* S_DMA_8 */
+ + #define OMAP24XX_DMA_AES_RX		10	/* S_DMA_9 */
+ + #define OMAP24XX_DMA_DES_TX		11	/* S_DMA_10 */
+ + #define OMAP24XX_DMA_DES_RX		12	/* S_DMA_11 */
+ + #define OMAP24XX_DMA_SHA1MD5_RX		13	/* S_DMA_12 */
+ + #define OMAP34XX_DMA_SHA2MD5_RX		13	/* S_DMA_12 */
+ + #define OMAP242X_DMA_EXT_DMAREQ2	14	/* S_DMA_13 */
+ + #define OMAP242X_DMA_EXT_DMAREQ3	15	/* S_DMA_14 */
+ + #define OMAP242X_DMA_EXT_DMAREQ4	16	/* S_DMA_15 */
+ + #define OMAP242X_DMA_EAC_AC_RD		17	/* S_DMA_16 */
+ + #define OMAP242X_DMA_EAC_AC_WR		18	/* S_DMA_17 */
+ + #define OMAP242X_DMA_EAC_MD_UL_RD	19	/* S_DMA_18 */
+ + #define OMAP242X_DMA_EAC_MD_UL_WR	20	/* S_DMA_19 */
+ + #define OMAP242X_DMA_EAC_MD_DL_RD	21	/* S_DMA_20 */
+ + #define OMAP242X_DMA_EAC_MD_DL_WR	22	/* S_DMA_21 */
+ + #define OMAP242X_DMA_EAC_BT_UL_RD	23	/* S_DMA_22 */
+ + #define OMAP242X_DMA_EAC_BT_UL_WR	24	/* S_DMA_23 */
+ + #define OMAP242X_DMA_EAC_BT_DL_RD	25	/* S_DMA_24 */
+ + #define OMAP242X_DMA_EAC_BT_DL_WR	26	/* S_DMA_25 */
+ + #define OMAP243X_DMA_EXT_DMAREQ3	14	/* S_DMA_13 */
+ + #define OMAP24XX_DMA_SPI3_TX0		15	/* S_DMA_14 */
+ + #define OMAP24XX_DMA_SPI3_RX0		16	/* S_DMA_15 */
+ + #define OMAP24XX_DMA_MCBSP3_TX		17	/* S_DMA_16 */
+ + #define OMAP24XX_DMA_MCBSP3_RX		18	/* S_DMA_17 */
+ + #define OMAP24XX_DMA_MCBSP4_TX		19	/* S_DMA_18 */
+ + #define OMAP24XX_DMA_MCBSP4_RX		20	/* S_DMA_19 */
+ + #define OMAP24XX_DMA_MCBSP5_TX		21	/* S_DMA_20 */
+ + #define OMAP24XX_DMA_MCBSP5_RX		22	/* S_DMA_21 */
+ + #define OMAP24XX_DMA_SPI3_TX1		23	/* S_DMA_22 */
+ + #define OMAP24XX_DMA_SPI3_RX1		24	/* S_DMA_23 */
+ + #define OMAP243X_DMA_EXT_DMAREQ4	25	/* S_DMA_24 */
+ + #define OMAP243X_DMA_EXT_DMAREQ5	26	/* S_DMA_25 */
+ + #define OMAP34XX_DMA_I2C3_TX		25	/* S_DMA_24 */
+ + #define OMAP34XX_DMA_I2C3_RX		26	/* S_DMA_25 */
+ + #define OMAP24XX_DMA_I2C1_TX		27	/* S_DMA_26 */
+ + #define OMAP24XX_DMA_I2C1_RX		28	/* S_DMA_27 */
+ + #define OMAP24XX_DMA_I2C2_TX		29	/* S_DMA_28 */
+ + #define OMAP24XX_DMA_I2C2_RX		30	/* S_DMA_29 */
+ + #define OMAP24XX_DMA_MCBSP1_TX		31	/* S_DMA_30 */
+ + #define OMAP24XX_DMA_MCBSP1_RX		32	/* S_DMA_31 */
+ + #define OMAP24XX_DMA_MCBSP2_TX		33	/* S_DMA_32 */
+ + #define OMAP24XX_DMA_MCBSP2_RX		34	/* S_DMA_33 */
+ + #define OMAP24XX_DMA_SPI1_TX0		35	/* S_DMA_34 */
+ + #define OMAP24XX_DMA_SPI1_RX0		36	/* S_DMA_35 */
+ + #define OMAP24XX_DMA_SPI1_TX1		37	/* S_DMA_36 */
+ + #define OMAP24XX_DMA_SPI1_RX1		38	/* S_DMA_37 */
+ + #define OMAP24XX_DMA_SPI1_TX2		39	/* S_DMA_38 */
+ + #define OMAP24XX_DMA_SPI1_RX2		40	/* S_DMA_39 */
+ + #define OMAP24XX_DMA_SPI1_TX3		41	/* S_DMA_40 */
+ + #define OMAP24XX_DMA_SPI1_RX3		42	/* S_DMA_41 */
+ + #define OMAP24XX_DMA_SPI2_TX0		43	/* S_DMA_42 */
+ + #define OMAP24XX_DMA_SPI2_RX0		44	/* S_DMA_43 */
+ + #define OMAP24XX_DMA_SPI2_TX1		45	/* S_DMA_44 */
+ + #define OMAP24XX_DMA_SPI2_RX1		46	/* S_DMA_45 */
+ + #define OMAP24XX_DMA_MMC2_TX		47	/* S_DMA_46 */
+ + #define OMAP24XX_DMA_MMC2_RX		48	/* S_DMA_47 */
+ + #define OMAP24XX_DMA_UART1_TX		49	/* S_DMA_48 */
+ + #define OMAP24XX_DMA_UART1_RX		50	/* S_DMA_49 */
+ + #define OMAP24XX_DMA_UART2_TX		51	/* S_DMA_50 */
+ + #define OMAP24XX_DMA_UART2_RX		52	/* S_DMA_51 */
+ + #define OMAP24XX_DMA_UART3_TX		53	/* S_DMA_52 */
+ + #define OMAP24XX_DMA_UART3_RX		54	/* S_DMA_53 */
+ + #define OMAP24XX_DMA_USB_W2FC_TX0	55	/* S_DMA_54 */
+ + #define OMAP24XX_DMA_USB_W2FC_RX0	56	/* S_DMA_55 */
+ + #define OMAP24XX_DMA_USB_W2FC_TX1	57	/* S_DMA_56 */
+ + #define OMAP24XX_DMA_USB_W2FC_RX1	58	/* S_DMA_57 */
+ + #define OMAP24XX_DMA_USB_W2FC_TX2	59	/* S_DMA_58 */
+ + #define OMAP24XX_DMA_USB_W2FC_RX2	60	/* S_DMA_59 */
+ + #define OMAP24XX_DMA_MMC1_TX		61	/* S_DMA_60 */
+ + #define OMAP24XX_DMA_MMC1_RX		62	/* S_DMA_61 */
+ + #define OMAP24XX_DMA_MS			63	/* S_DMA_62 */
+ + #define OMAP242X_DMA_EXT_DMAREQ5	64	/* S_DMA_63 */
+ + #define OMAP243X_DMA_EXT_DMAREQ6	64	/* S_DMA_63 */
+ + #define OMAP34XX_DMA_EXT_DMAREQ3	64	/* S_DMA_63 */
+ + #define OMAP34XX_DMA_AES2_TX		65	/* S_DMA_64 */
+ + #define OMAP34XX_DMA_AES2_RX		66	/* S_DMA_65 */
+ + #define OMAP34XX_DMA_DES2_TX		67	/* S_DMA_66 */
+ + #define OMAP34XX_DMA_DES2_RX		68	/* S_DMA_67 */
+ + #define OMAP34XX_DMA_SHA1MD5_RX		69	/* S_DMA_68 */
+ + #define OMAP34XX_DMA_SPI4_TX0		70	/* S_DMA_69 */
+ + #define OMAP34XX_DMA_SPI4_RX0		71	/* S_DMA_70 */
+ + #define OMAP34XX_DSS_DMA0		72	/* S_DMA_71 */
+ + #define OMAP34XX_DSS_DMA1		73	/* S_DMA_72 */
+ + #define OMAP34XX_DSS_DMA2		74	/* S_DMA_73 */
+ + #define OMAP34XX_DSS_DMA3		75	/* S_DMA_74 */
+ + #define OMAP34XX_DMA_MMC3_TX		77	/* S_DMA_76 */
+ + #define OMAP34XX_DMA_MMC3_RX		78	/* S_DMA_77 */
+ + #define OMAP34XX_DMA_USIM_TX		79	/* S_DMA_78 */
+ + #define OMAP34XX_DMA_USIM_RX		80	/* S_DMA_79 */
+ + 
+ + #define OMAP36XX_DMA_UART4_TX		81	/* S_DMA_80 */
+ + #define OMAP36XX_DMA_UART4_RX		82	/* S_DMA_81 */
+ + 
+ + /* Only for AM35xx */
+ + #define AM35XX_DMA_UART4_TX		54
+ + #define AM35XX_DMA_UART4_RX		55
+ + 
+ + /*----------------------------------------------------------------------------*/
+ + 
+ + #define OMAP1_DMA_TOUT_IRQ		(1 << 0)
+ + #define OMAP_DMA_DROP_IRQ		(1 << 1)
+ + #define OMAP_DMA_HALF_IRQ		(1 << 2)
+ + #define OMAP_DMA_FRAME_IRQ		(1 << 3)
+ + #define OMAP_DMA_LAST_IRQ		(1 << 4)
+ + #define OMAP_DMA_BLOCK_IRQ		(1 << 5)
+ + #define OMAP1_DMA_SYNC_IRQ		(1 << 6)
+ + #define OMAP2_DMA_PKT_IRQ		(1 << 7)
+ + #define OMAP2_DMA_TRANS_ERR_IRQ		(1 << 8)
+ + #define OMAP2_DMA_SECURE_ERR_IRQ	(1 << 9)
+ + #define OMAP2_DMA_SUPERVISOR_ERR_IRQ	(1 << 10)
+ + #define OMAP2_DMA_MISALIGNED_ERR_IRQ	(1 << 11)
+ + 
+ + #define OMAP_DMA_CCR_EN			(1 << 7)
+ + #define OMAP_DMA_CCR_RD_ACTIVE		(1 << 9)
+ + #define OMAP_DMA_CCR_WR_ACTIVE		(1 << 10)
+ + #define OMAP_DMA_CCR_SEL_SRC_DST_SYNC	(1 << 24)
+ + #define OMAP_DMA_CCR_BUFFERING_DISABLE	(1 << 25)
+ + 
+ + #define OMAP_DMA_DATA_TYPE_S8		0x00
+ + #define OMAP_DMA_DATA_TYPE_S16		0x01
+ + #define OMAP_DMA_DATA_TYPE_S32		0x02
+ + 
+ + #define OMAP_DMA_SYNC_ELEMENT		0x00
+ + #define OMAP_DMA_SYNC_FRAME		0x01
+ + #define OMAP_DMA_SYNC_BLOCK		0x02
+ + #define OMAP_DMA_SYNC_PACKET		0x03
+ + 
+ + #define OMAP_DMA_DST_SYNC_PREFETCH	0x02
+ + #define OMAP_DMA_SRC_SYNC		0x01
+ + #define OMAP_DMA_DST_SYNC		0x00
+ + 
+ + #define OMAP_DMA_PORT_EMIFF		0x00
+ + #define OMAP_DMA_PORT_EMIFS		0x01
+ + #define OMAP_DMA_PORT_OCP_T1		0x02
+ + #define OMAP_DMA_PORT_TIPB		0x03
+ + #define OMAP_DMA_PORT_OCP_T2		0x04
+ + #define OMAP_DMA_PORT_MPUI		0x05
+ + 
+ + #define OMAP_DMA_AMODE_CONSTANT		0x00
+ + #define OMAP_DMA_AMODE_POST_INC		0x01
+ + #define OMAP_DMA_AMODE_SINGLE_IDX	0x02
+ + #define OMAP_DMA_AMODE_DOUBLE_IDX	0x03
+ + 
+ + #define DMA_DEFAULT_FIFO_DEPTH		0x10
+ + #define DMA_DEFAULT_ARB_RATE		0x01
+ + /* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */
+ + #define DMA_THREAD_RESERVE_NORM		(0x00 << 12) /* Def */
+ + #define DMA_THREAD_RESERVE_ONET		(0x01 << 12)
+ + #define DMA_THREAD_RESERVE_TWOT		(0x02 << 12)
+ + #define DMA_THREAD_RESERVE_THREET	(0x03 << 12)
+ + #define DMA_THREAD_FIFO_NONE		(0x00 << 14) /* Def */
+ + #define DMA_THREAD_FIFO_75		(0x01 << 14)
+ + #define DMA_THREAD_FIFO_25		(0x02 << 14)
+ + #define DMA_THREAD_FIFO_50		(0x03 << 14)
+ + 
+ + /* DMA4_OCP_SYSCONFIG bits */
+ + #define DMA_SYSCONFIG_MIDLEMODE_MASK		(3 << 12)
+ + #define DMA_SYSCONFIG_CLOCKACTIVITY_MASK	(3 << 8)
+ + #define DMA_SYSCONFIG_EMUFREE			(1 << 5)
+ + #define DMA_SYSCONFIG_SIDLEMODE_MASK		(3 << 3)
+ + #define DMA_SYSCONFIG_SOFTRESET			(1 << 2)
+ + #define DMA_SYSCONFIG_AUTOIDLE			(1 << 0)
+ + 
+ + #define DMA_SYSCONFIG_MIDLEMODE(n)		((n) << 12)
+ + #define DMA_SYSCONFIG_SIDLEMODE(n)		((n) << 3)
+ + 
+ + #define DMA_IDLEMODE_SMARTIDLE			0x2
+ + #define DMA_IDLEMODE_NO_IDLE			0x1
+ + #define DMA_IDLEMODE_FORCE_IDLE			0x0
+ + 
+ + /* Chaining modes*/
+ + #ifndef CONFIG_ARCH_OMAP1
+ + #define OMAP_DMA_STATIC_CHAIN		0x1
+ + #define OMAP_DMA_DYNAMIC_CHAIN		0x2
+ + #define OMAP_DMA_CHAIN_ACTIVE		0x1
+ + #define OMAP_DMA_CHAIN_INACTIVE		0x0
+ + #endif
+ + 
+ + #define DMA_CH_PRIO_HIGH		0x1
+ + #define DMA_CH_PRIO_LOW			0x0 /* Def */
+ + 
+ + /* Errata handling */
+ + #define IS_DMA_ERRATA(id)		(errata & (id))
+ + #define SET_DMA_ERRATA(id)		(errata |= (id))
+ + 
+ + #define DMA_ERRATA_IFRAME_BUFFERING	BIT(0x0)
+ + #define DMA_ERRATA_PARALLEL_CHANNELS	BIT(0x1)
+ + #define DMA_ERRATA_i378			BIT(0x2)
+ + #define DMA_ERRATA_i541			BIT(0x3)
+ + #define DMA_ERRATA_i88			BIT(0x4)
+ + #define DMA_ERRATA_3_3			BIT(0x5)
+ + #define DMA_ROMCODE_BUG			BIT(0x6)
+ + 
+ + /* Attributes for OMAP DMA Contrller */
+ + #define DMA_LINKED_LCH			BIT(0x0)
+ + #define GLOBAL_PRIORITY			BIT(0x1)
+ + #define RESERVE_CHANNEL			BIT(0x2)
+ + #define IS_CSSA_32			BIT(0x3)
+ + #define IS_CDSA_32			BIT(0x4)
+ + #define IS_RW_PRIORITY			BIT(0x5)
+ + #define ENABLE_1510_MODE		BIT(0x6)
+ + #define SRC_PORT			BIT(0x7)
+ + #define DST_PORT			BIT(0x8)
+ + #define SRC_INDEX			BIT(0x9)
+ + #define DST_INDEX			BIT(0xA)
+ + #define IS_BURST_ONLY4			BIT(0xB)
+ + #define CLEAR_CSR_ON_READ		BIT(0xC)
+ + #define IS_WORD_16			BIT(0xD)
+ + 
+ + enum omap_reg_offsets {
+ + 
+ + GCR,		GSCR,		GRST1,		HW_ID,
+ + PCH2_ID,	PCH0_ID,	PCH1_ID,	PCHG_ID,
+ + PCHD_ID,	CAPS_0,		CAPS_1,		CAPS_2,
+ + CAPS_3,		CAPS_4,		PCH2_SR,	PCH0_SR,
+ + PCH1_SR,	PCHD_SR,	REVISION,	IRQSTATUS_L0,
+ + IRQSTATUS_L1,	IRQSTATUS_L2,	IRQSTATUS_L3,	IRQENABLE_L0,
+ + IRQENABLE_L1,	IRQENABLE_L2,	IRQENABLE_L3,	SYSSTATUS,
+ + OCP_SYSCONFIG,
+ + 
+ + /* omap1+ specific */
+ + CPC, CCR2, LCH_CTRL,
+ + 
+ + /* Common registers for all omap's */
+ + CSDP,		CCR,		CICR,		CSR,
+ + CEN,		CFN,		CSFI,		CSEI,
+ + CSAC,		CDAC,		CDEI,
+ + CDFI,		CLNK_CTRL,
+ + 
+ + /* Channel specific registers */
+ + CSSA,		CDSA,		COLOR,
+ + CCEN,		CCFN,
+ + 
+ + /* omap3630 and omap4 specific */
+ + CDP,		CNDP,		CCDN,
+ + 
+ + };
+ + 
+ + enum omap_dma_burst_mode {
+ + 	OMAP_DMA_DATA_BURST_DIS = 0,
+ + 	OMAP_DMA_DATA_BURST_4,
+ + 	OMAP_DMA_DATA_BURST_8,
+ + 	OMAP_DMA_DATA_BURST_16,
+ + };
+ + 
+ + enum end_type {
+ + 	OMAP_DMA_LITTLE_ENDIAN = 0,
+ + 	OMAP_DMA_BIG_ENDIAN
+ + };
+ + 
+ + enum omap_dma_color_mode {
+ + 	OMAP_DMA_COLOR_DIS = 0,
+ + 	OMAP_DMA_CONSTANT_FILL,
+ + 	OMAP_DMA_TRANSPARENT_COPY
+ + };
+ + 
+ + enum omap_dma_write_mode {
+ + 	OMAP_DMA_WRITE_NON_POSTED = 0,
+ + 	OMAP_DMA_WRITE_POSTED,
+ + 	OMAP_DMA_WRITE_LAST_NON_POSTED
+ + };
+ + 
+ + enum omap_dma_channel_mode {
+ + 	OMAP_DMA_LCH_2D = 0,
+ + 	OMAP_DMA_LCH_G,
+ + 	OMAP_DMA_LCH_P,
+ + 	OMAP_DMA_LCH_PD
+ + };
+ + 
+ + struct omap_dma_channel_params {
+ + 	int data_type;		/* data type 8,16,32 */
+ + 	int elem_count;		/* number of elements in a frame */
+ + 	int frame_count;	/* number of frames in a element */
+ + 
+ + 	int src_port;		/* Only on OMAP1 REVISIT: Is this needed? */
+ + 	int src_amode;		/* constant, post increment, indexed,
+ + 					double indexed */
+ + 	unsigned long src_start;	/* source address : physical */
+ + 	int src_ei;		/* source element index */
+ + 	int src_fi;		/* source frame index */
+ + 
+ + 	int dst_port;		/* Only on OMAP1 REVISIT: Is this needed? */
+ + 	int dst_amode;		/* constant, post increment, indexed,
+ + 					double indexed */
+ + 	unsigned long dst_start;	/* source address : physical */
+ + 	int dst_ei;		/* source element index */
+ + 	int dst_fi;		/* source frame index */
+ + 
+ + 	int trigger;		/* trigger attached if the channel is
+ + 					synchronized */
+ + 	int sync_mode;		/* sycn on element, frame , block or packet */
+ + 	int src_or_dst_synch;	/* source synch(1) or destination synch(0) */
+ + 
+ + 	int ie;			/* interrupt enabled */
+ + 
+ + 	unsigned char read_prio;/* read priority */
+ + 	unsigned char write_prio;/* write priority */
+ + 
+ + #ifndef CONFIG_ARCH_OMAP1
+ + 	enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */
+ + #endif
+ + };
+ + 
+ + struct omap_dma_lch {
+ + 	int next_lch;
+ + 	int dev_id;
+ + 	u16 saved_csr;
+ + 	u16 enabled_irqs;
+ + 	const char *dev_name;
+ + 	void (*callback)(int lch, u16 ch_status, void *data);
+ + 	void *data;
+ + 	long flags;
+ + 	/* required for Dynamic chaining */
+ + 	int prev_linked_ch;
+ + 	int next_linked_ch;
+ + 	int state;
+ + 	int chain_id;
+ + 	int status;
+ + };
+ + 
+ + struct omap_dma_dev_attr {
+ + 	u32 dev_caps;
+ + 	u16 lch_count;
+ + 	u16 chan_count;
+ + 	struct omap_dma_lch *chan;
+ + };
+ + 
+ + /* System DMA platform data structure */
+ + struct omap_system_dma_plat_info {
+ + 	struct omap_dma_dev_attr *dma_attr;
+ + 	u32 errata;
+ + 	void (*disable_irq_lch)(int lch);
+ + 	void (*show_dma_caps)(void);
+ + 	void (*clear_lch_regs)(int lch);
+ + 	void (*clear_dma)(int lch);
+ + 	void (*dma_write)(u32 val, int reg, int lch);
+ + 	u32 (*dma_read)(int reg, int lch);
+ + };
+ + 
+ + extern void omap_set_dma_priority(int lch, int dst_port, int priority);
+ + extern int omap_request_dma(int dev_id, const char *dev_name,
+ + 			void (*callback)(int lch, u16 ch_status, void *data),
+ + 			void *data, int *dma_ch);
+ + extern void omap_enable_dma_irq(int ch, u16 irq_bits);
+ + extern void omap_disable_dma_irq(int ch, u16 irq_bits);
+ + extern void omap_free_dma(int ch);
+ + extern void omap_start_dma(int lch);
+ + extern void omap_stop_dma(int lch);
+ + extern void omap_set_dma_transfer_params(int lch, int data_type,
+ + 					 int elem_count, int frame_count,
+ + 					 int sync_mode,
+ + 					 int dma_trigger, int src_or_dst_synch);
+ + extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
+ + 				    u32 color);
+ + extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
+ + extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);
+ + 
+ + extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
+ + 				    unsigned long src_start,
+ + 				    int src_ei, int src_fi);
+ + extern void omap_set_dma_src_index(int lch, int eidx, int fidx);
+ + extern void omap_set_dma_src_data_pack(int lch, int enable);
+ + extern void omap_set_dma_src_burst_mode(int lch,
+ + 					enum omap_dma_burst_mode burst_mode);
+ + 
+ + extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
+ + 				     unsigned long dest_start,
+ + 				     int dst_ei, int dst_fi);
+ + extern void omap_set_dma_dest_index(int lch, int eidx, int fidx);
+ + extern void omap_set_dma_dest_data_pack(int lch, int enable);
+ + extern void omap_set_dma_dest_burst_mode(int lch,
+ + 					 enum omap_dma_burst_mode burst_mode);
+ + 
+ + extern void omap_set_dma_params(int lch,
+ + 				struct omap_dma_channel_params *params);
+ + 
+ + extern void omap_dma_link_lch(int lch_head, int lch_queue);
+ + extern void omap_dma_unlink_lch(int lch_head, int lch_queue);
+ + 
+ + extern int omap_set_dma_callback(int lch,
+ + 			void (*callback)(int lch, u16 ch_status, void *data),
+ + 			void *data);
+ + extern dma_addr_t omap_get_dma_src_pos(int lch);
+ + extern dma_addr_t omap_get_dma_dst_pos(int lch);
+ + extern void omap_clear_dma(int lch);
+ + extern int omap_get_dma_active_status(int lch);
+ + extern int omap_dma_running(void);
+ + extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
+ + 				       int tparams);
+ + extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
+ + 				 unsigned char write_prio);
+ + extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype);
+ + extern void omap_set_dma_src_endian_type(int lch, enum end_type etype);
+ + extern int omap_get_dma_index(int lch, int *ei, int *fi);
+ + 
+ + void omap_dma_global_context_save(void);
+ + void omap_dma_global_context_restore(void);
+ + 
+ + extern void omap_dma_disable_irq(int lch);
+ + 
+ + /* Chaining APIs */
+ + #ifndef CONFIG_ARCH_OMAP1
+ + extern int omap_request_dma_chain(int dev_id, const char *dev_name,
+ + 				  void (*callback) (int lch, u16 ch_status,
+ + 						    void *data),
+ + 				  int *chain_id, int no_of_chans,
+ + 				  int chain_mode,
+ + 				  struct omap_dma_channel_params params);
+ + extern int omap_free_dma_chain(int chain_id);
+ + extern int omap_dma_chain_a_transfer(int chain_id, int src_start,
+ + 				     int dest_start, int elem_count,
+ + 				     int frame_count, void *callbk_data);
+ + extern int omap_start_dma_chain_transfers(int chain_id);
+ + extern int omap_stop_dma_chain_transfers(int chain_id);
+ + extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi);
+ + extern int omap_get_dma_chain_dst_pos(int chain_id);
+ + extern int omap_get_dma_chain_src_pos(int chain_id);
+ + 
+ + extern int omap_modify_dma_chain_params(int chain_id,
+ + 					struct omap_dma_channel_params params);
+ + extern int omap_dma_chain_status(int chain_id);
+ + #endif
+ + 
+ + static inline int omap_lcd_dma_running(void)
+ + {
+ + 	return 0;
+ + }
+ + 
+ + #endif /* __ASM_ARCH_DMA_H */
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/dmtimer.h linux-3.2.1/arch/arm/plat-ckb/include/plat/dmtimer.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/dmtimer.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/dmtimer.h	2014-11-25 13:19:15.164003806 +0900
+ ***************
+ *** 0 ****
+ --- 1,429 ----
+ + /*
+ +  * arch/arm/plat-omap/include/plat/dmtimer.h
+ +  *
+ +  * OMAP Dual-Mode Timers
+ +  *
+ +  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ +  * Tarun Kanti DebBarma <tarun.kanti@ti.com>
+ +  * Thara Gopinath <thara@ti.com>
+ +  *
+ +  * Platform device conversion and hwmod support.
+ +  *
+ +  * Copyright (C) 2005 Nokia Corporation
+ +  * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
+ +  * PWM and clock framwork support by Timo Teras.
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify it
+ +  * under the terms of the GNU General Public License as published by the
+ +  * Free Software Foundation; either version 2 of the License, or (at your
+ +  * option) any later version.
+ +  *
+ +  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ +  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ +  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ +  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ +  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ +  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ +  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ +  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ +  *
+ +  * You should have received a copy of the  GNU General Public License along
+ +  * with this program; if not, write  to the Free Software Foundation, Inc.,
+ +  * 675 Mass Ave, Cambridge, MA 02139, USA.
+ +  */
+ + 
+ + #include <linux/clk.h>
+ + #include <linux/delay.h>
+ + #include <linux/io.h>
+ + #include <linux/platform_device.h>
+ + 
+ + #ifndef __ASM_ARCH_DMTIMER_H
+ + #define __ASM_ARCH_DMTIMER_H
+ + 
+ + /* clock sources */
+ + #define OMAP_TIMER_SRC_SYS_CLK			0x00
+ + #define OMAP_TIMER_SRC_32_KHZ			0x01
+ + #define OMAP_TIMER_SRC_EXT_CLK			0x02
+ + 
+ + /* timer interrupt enable bits */
+ + #define OMAP_TIMER_INT_CAPTURE			(1 << 2)
+ + #define OMAP_TIMER_INT_CAPTURE_RESET		(0 << 2)
+ + #define OMAP_TIMER_INT_OVERFLOW			(1 << 1)
+ + #define OMAP_TIMER_INT_MATCH			(1 << 0)
+ + 
+ + /* trigger types */
+ + #define OMAP_TIMER_TRIGGER_NONE			0x00
+ + #define OMAP_TIMER_TRIGGER_OVERFLOW		0x01
+ + #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE	0x02
+ + 
+ + /*
+ +  * IP revision identifier so that Highlander IP
+ +  * in OMAP4 can be distinguished.
+ +  */
+ + #define OMAP_TIMER_IP_VERSION_1                        0x1
+ + 
+ + /* timer capabilities used in hwmod database */
+ + #define OMAP_TIMER_SECURE				0x80000000
+ + #define OMAP_TIMER_ALWON				0x40000000
+ + #define OMAP_TIMER_HAS_PWM				0x20000000
+ + 
+ + struct omap_timer_capability_dev_attr {
+ + 	u32 timer_capability;
+ + };
+ + 
+ + struct omap_dm_timer;
+ + struct clk;
+ + 
+ + struct timer_regs {
+ + 	u32 tidr;
+ + 	u32 tiocp_cfg;
+ + 	u32 tistat;
+ + 	u32 tisr;
+ + 	u32 tier;
+ + 	u32 twer;
+ + 	u32 tclr;
+ + 	u32 tcrr;
+ + 	u32 tldr;
+ + 	u32 ttrg;
+ + 	u32 twps;
+ + 	u32 tmar;
+ + 	u32 tcar1;
+ + 	u32 tsicr;
+ + 	u32 tcar2;
+ + 	u32 tpir;
+ + 	u32 tnir;
+ + 	u32 tcvr;
+ + 	u32 tocr;
+ + 	u32 towr;
+ + };
+ + 
+ + struct dmtimer_platform_data {
+ + 	int (*set_timer_src)(struct platform_device *pdev, int source);
+ + 	int timer_ip_version;
+ + 	u32 needs_manual_reset:1;
+ + 	bool reserved;
+ + 
+ + 	bool loses_context;
+ + 
+ + 	int (*get_context_loss_count)(struct device *dev);
+ + };
+ + 
+ + struct omap_dm_timer *omap_dm_timer_request(void);
+ + struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
+ + int omap_dm_timer_free(struct omap_dm_timer *timer);
+ + void omap_dm_timer_enable(struct omap_dm_timer *timer);
+ + void omap_dm_timer_disable(struct omap_dm_timer *timer);
+ + 
+ + int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
+ + 
+ + u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
+ + struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer);
+ + 
+ + int omap_dm_timer_trigger(struct omap_dm_timer *timer);
+ + int omap_dm_timer_start(struct omap_dm_timer *timer);
+ + int omap_dm_timer_stop(struct omap_dm_timer *timer);
+ + 
+ + int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
+ + int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
+ + int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
+ + int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
+ + int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
+ + int omap_dm_timer_set_capture(struct omap_dm_timer *timer,
+ + 				bool lht, bool hlt, bool cm);
+ + int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
+ + 
+ + int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
+ + 
+ + unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
+ + int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
+ + unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer);
+ + int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value);
+ + 
+ + int omap_dm_timers_active(void);
+ + 
+ + /*
+ +  * Do not use the defines below, they are not needed. They should be only
+ +  * used by dmtimer.c and sys_timer related code.
+ +  */
+ + 
+ + /*
+ +  * The interrupt registers are different between v1 and v2 ip.
+ +  * These registers are offsets from timer->iobase.
+ +  */
+ + #define OMAP_TIMER_ID_OFFSET		0x00
+ + #define OMAP_TIMER_OCP_CFG_OFFSET	0x10
+ + 
+ + #define OMAP_TIMER_V1_SYS_STAT_OFFSET	0x14
+ + #define OMAP_TIMER_V1_STAT_OFFSET	0x18
+ + #define OMAP_TIMER_V1_INT_EN_OFFSET	0x1c
+ + 
+ + #define OMAP_TIMER_V2_IRQSTATUS_RAW	0x24
+ + #define OMAP_TIMER_V2_IRQSTATUS		0x28
+ + #define OMAP_TIMER_V2_IRQENABLE_SET	0x2c
+ + #define OMAP_TIMER_V2_IRQENABLE_CLR	0x30
+ + 
+ + /*
+ +  * The functional registers have a different base on v1 and v2 ip.
+ +  * These registers are offsets from timer->func_base. The func_base
+ +  * is samae as io_base for v1 and io_base + 0x14 for v2 ip.
+ +  *
+ +  */
+ + #define OMAP_TIMER_V2_FUNC_OFFSET		0x14
+ + 
+ + #define _OMAP_TIMER_WAKEUP_EN_OFFSET	0x20
+ + #define _OMAP_TIMER_CTRL_OFFSET		0x24
+ + #define		OMAP_TIMER_CTRL_GPOCFG		(1 << 14)
+ + #define		OMAP_TIMER_CTRL_CAPTMODE	(1 << 13)
+ + #define		OMAP_TIMER_CTRL_PT		(1 << 12)
+ + #define		OMAP_TIMER_CTRL_TCM_LOWTOHIGH	(0x1 << 8)
+ + #define		OMAP_TIMER_CTRL_TCM_HIGHTOLOW	(0x2 << 8)
+ + #define		OMAP_TIMER_CTRL_TCM_BOTHEDGES	(0x3 << 8)
+ + #define		OMAP_TIMER_CTRL_SCPWM		(1 << 7)
+ + #define		OMAP_TIMER_CTRL_CE		(1 << 6) /* compare enable */
+ + #define		OMAP_TIMER_CTRL_PRE		(1 << 5) /* prescaler enable */
+ + #define		OMAP_TIMER_CTRL_PTV_SHIFT	2 /* prescaler value shift */
+ + #define		OMAP_TIMER_CTRL_POSTED		(1 << 2)
+ + #define		OMAP_TIMER_CTRL_AR		(1 << 1) /* auto-reload enable */
+ + #define		OMAP_TIMER_CTRL_ST		(1 << 0) /* start timer */
+ + #define _OMAP_TIMER_COUNTER_OFFSET	0x28
+ + #define _OMAP_TIMER_LOAD_OFFSET		0x2c
+ + #define _OMAP_TIMER_TRIGGER_OFFSET	0x30
+ + #define _OMAP_TIMER_WRITE_PEND_OFFSET	0x34
+ + #define		WP_NONE			0	/* no write pending bit */
+ + #define		WP_TCLR			(1 << 0)
+ + #define		WP_TCRR			(1 << 1)
+ + #define		WP_TLDR			(1 << 2)
+ + #define		WP_TTGR			(1 << 3)
+ + #define		WP_TMAR			(1 << 4)
+ + #define		WP_TPIR			(1 << 5)
+ + #define		WP_TNIR			(1 << 6)
+ + #define		WP_TCVR			(1 << 7)
+ + #define		WP_TOCR			(1 << 8)
+ + #define		WP_TOWR			(1 << 9)
+ + #define _OMAP_TIMER_MATCH_OFFSET	0x38
+ + #define _OMAP_TIMER_CAPTURE_OFFSET	0x3c
+ + #define _OMAP_TIMER_IF_CTRL_OFFSET	0x40
+ + #define _OMAP_TIMER_CAPTURE2_OFFSET		0x44	/* TCAR2, 34xx only */
+ + #define _OMAP_TIMER_TICK_POS_OFFSET		0x48	/* TPIR, 34xx only */
+ + #define _OMAP_TIMER_TICK_NEG_OFFSET		0x4c	/* TNIR, 34xx only */
+ + #define _OMAP_TIMER_TICK_COUNT_OFFSET		0x50	/* TCVR, 34xx only */
+ + #define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET	0x54	/* TOCR, 34xx only */
+ + #define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET	0x58	/* TOWR, 34xx only */
+ + 
+ + /* register offsets with the write pending bit encoded */
+ + #define	WPSHIFT					16
+ + 
+ + #define OMAP_TIMER_WAKEUP_EN_REG		(_OMAP_TIMER_WAKEUP_EN_OFFSET \
+ + 							| (WP_NONE << WPSHIFT))
+ + 
+ + #define OMAP_TIMER_CTRL_REG			(_OMAP_TIMER_CTRL_OFFSET \
+ + 							| (WP_TCLR << WPSHIFT))
+ + 
+ + #define OMAP_TIMER_COUNTER_REG			(_OMAP_TIMER_COUNTER_OFFSET \
+ + 							| (WP_TCRR << WPSHIFT))
+ + 
+ + #define OMAP_TIMER_LOAD_REG			(_OMAP_TIMER_LOAD_OFFSET \
+ + 							| (WP_TLDR << WPSHIFT))
+ + 
+ + #define OMAP_TIMER_TRIGGER_REG			(_OMAP_TIMER_TRIGGER_OFFSET \
+ + 							| (WP_TTGR << WPSHIFT))
+ + 
+ + #define OMAP_TIMER_WRITE_PEND_REG		(_OMAP_TIMER_WRITE_PEND_OFFSET \
+ + 							| (WP_NONE << WPSHIFT))
+ + 
+ + #define OMAP_TIMER_MATCH_REG			(_OMAP_TIMER_MATCH_OFFSET \
+ + 							| (WP_TMAR << WPSHIFT))
+ + 
+ + #define OMAP_TIMER_CAPTURE_REG			(_OMAP_TIMER_CAPTURE_OFFSET \
+ + 							| (WP_NONE << WPSHIFT))
+ + 
+ + #define OMAP_TIMER_IF_CTRL_REG			(_OMAP_TIMER_IF_CTRL_OFFSET \
+ + 							| (WP_NONE << WPSHIFT))
+ + 
+ + #define OMAP_TIMER_CAPTURE2_REG			(_OMAP_TIMER_CAPTURE2_OFFSET \
+ + 							| (WP_NONE << WPSHIFT))
+ + 
+ + #define OMAP_TIMER_TICK_POS_REG			(_OMAP_TIMER_TICK_POS_OFFSET \
+ + 							| (WP_TPIR << WPSHIFT))
+ + 
+ + #define OMAP_TIMER_TICK_NEG_REG			(_OMAP_TIMER_TICK_NEG_OFFSET \
+ + 							| (WP_TNIR << WPSHIFT))
+ + 
+ + #define OMAP_TIMER_TICK_COUNT_REG		(_OMAP_TIMER_TICK_COUNT_OFFSET \
+ + 							| (WP_TCVR << WPSHIFT))
+ + 
+ + #define OMAP_TIMER_TICK_INT_MASK_SET_REG				\
+ + 		(_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
+ + 
+ + #define OMAP_TIMER_TICK_INT_MASK_COUNT_REG				\
+ + 		(_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
+ + 
+ + struct omap_dm_timer {
+ + 	unsigned long phys_base;
+ + 	int id;
+ + 	int irq;
+ + 	struct clk *iclk, *fclk;
+ + 
+ + 	void __iomem	*io_base;
+ + 	void __iomem	*sys_stat;	/* TISTAT timer status */
+ + 	void __iomem	*irq_stat;	/* TISR/IRQSTATUS interrupt status */
+ + 	void __iomem	*irq_ena;	/* irq enable */
+ + 	void __iomem	*irq_dis;	/* irq disable, only on v2 ip */
+ + 	void __iomem	*pend;		/* write pending */
+ + 	void __iomem	*func_base;	/* function register base */
+ + 
+ + 	unsigned long rate;
+ + 	unsigned reserved:1;
+ + 	unsigned posted:1;
+ + 	struct timer_regs context;
+ + 	bool loses_context;
+ + 	int ctx_loss_count;
+ + 	int revision;
+ + 	struct platform_device *pdev;
+ + 	struct list_head node;
+ + 
+ + 	int (*get_context_loss_count)(struct device *dev);
+ + };
+ + 
+ + int omap_dm_timer_prepare(struct omap_dm_timer *timer);
+ + 
+ + static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg,
+ + 						int posted)
+ + {
+ + 	if (posted)
+ + 		while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
+ + 			cpu_relax();
+ + 
+ + 	return __raw_readl(timer->func_base + (reg & 0xff));
+ + }
+ + 
+ + static inline void __omap_dm_timer_write(struct omap_dm_timer *timer,
+ + 					u32 reg, u32 val, int posted)
+ + {
+ + 	if (posted)
+ + 		while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
+ + 			cpu_relax();
+ + 
+ + 	__raw_writel(val, timer->func_base + (reg & 0xff));
+ + }
+ + 
+ + static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
+ + {
+ + 	u32 tidr;
+ + 
+ + 	/* Assume v1 ip if bits [31:16] are zero */
+ + 	tidr = __raw_readl(timer->io_base);
+ + 	if (!(tidr >> 16)) {
+ + 		timer->revision = 1;
+ + 		timer->sys_stat = timer->io_base +
+ + 				OMAP_TIMER_V1_SYS_STAT_OFFSET;
+ + 		timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
+ + 		timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
+ + 		timer->irq_dis = 0;
+ + 		timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
+ + 		timer->func_base = timer->io_base;
+ + 	} else {
+ + 		timer->revision = 2;
+ + 		timer->sys_stat = 0;
+ + 		timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS;
+ + 		timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET;
+ + 		timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR;
+ + 		timer->pend = timer->io_base +
+ + 			_OMAP_TIMER_WRITE_PEND_OFFSET +
+ + 				OMAP_TIMER_V2_FUNC_OFFSET;
+ + 		timer->func_base = timer->io_base + OMAP_TIMER_V2_FUNC_OFFSET;
+ + 	}
+ + }
+ + 
+ + /* Assumes the source clock has been set by caller */
+ + static inline void __omap_dm_timer_reset(struct omap_dm_timer *timer,
+ + 					int autoidle, int wakeup)
+ + {
+ + 	u32 l;
+ + 
+ + 	l = __raw_readl(timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
+ + 	l |= 0x02 << 3;  /* Set to smart-idle mode */
+ + 	l |= 0x2 << 8;   /* Set clock activity to perserve f-clock on idle */
+ + 
+ + 	if (autoidle)
+ + 		l |= 0x1 << 0;
+ + 
+ + 	if (wakeup)
+ + 		l |= 1 << 2;
+ + 
+ + 	__raw_writel(l, timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
+ + 
+ + 	/* Match hardware reset default of posted mode */
+ + 	__omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
+ + 					OMAP_TIMER_CTRL_POSTED, 0);
+ + }
+ + 
+ + static inline int __omap_dm_timer_set_source(struct clk *timer_fck,
+ + 						struct clk *parent)
+ + {
+ + 	int ret;
+ + 
+ + 	clk_disable(timer_fck);
+ + 	ret = clk_set_parent(timer_fck, parent);
+ + 	clk_enable(timer_fck);
+ + 
+ + 	/*
+ + 	 * When the functional clock disappears, too quick writes seem
+ + 	 * to cause an abort. XXX Is this still necessary?
+ + 	 */
+ + 	__delay(300000);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer,
+ + 					int posted, unsigned long rate)
+ + {
+ + 	u32 l;
+ + 
+ + 	l = __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
+ + 	if (l & OMAP_TIMER_CTRL_ST) {
+ + 		l &= ~0x1;
+ + 		__omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, l, posted);
+ + 
+ + 		/* Readback to make sure write has completed */
+ + 		__omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
+ + 		/*
+ + 		 * Wait for functional clock period x 3.5 to make sure that
+ + 		 * timer is stopped
+ + 		 */
+ + 		udelay(3500000 / rate + 1);
+ + 	}
+ + 
+ + 	/* Ack possibly pending interrupt */
+ + 	__raw_writel(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat);
+ + }
+ + 
+ + static inline void __omap_dm_timer_load_start(struct omap_dm_timer *timer,
+ + 						u32 ctrl, unsigned int load,
+ + 						int posted)
+ + {
+ + 	__omap_dm_timer_write(timer, OMAP_TIMER_COUNTER_REG, load, posted);
+ + 	__omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, ctrl, posted);
+ + }
+ + 
+ + static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer,
+ + 						unsigned int value)
+ + {
+ + 	__raw_writel(value, timer->irq_ena);
+ + 	__omap_dm_timer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
+ + }
+ + 
+ + static inline unsigned int
+ + __omap_dm_timer_read_counter(struct omap_dm_timer *timer, int posted)
+ + {
+ + 	return __omap_dm_timer_read(timer, OMAP_TIMER_COUNTER_REG, posted);
+ + }
+ + 
+ + static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer,
+ + 						unsigned int value)
+ + {
+ + 	__raw_writel(value, timer->irq_stat);
+ + }
+ + 
+ + #endif /* __ASM_ARCH_DMTIMER_H */
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/emif.h linux-3.2.1/arch/arm/plat-ckb/include/plat/emif.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/emif.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/emif.h	2014-11-25 13:19:15.164003806 +0900
+ ***************
+ *** 0 ****
+ --- 1,43 ----
+ + /*
+ +  * EMIF register definitions for TI81xx and AM33xx
+ +  *
+ +  * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #ifndef __EMIF_H
+ + #define __EMIF_H
+ + 
+ + #define EMIF_MOD_ID_REV			(0x0)
+ + #define EMIF4_0_SDRAM_STATUS		(0x04)
+ + #define EMIF4_0_SDRAM_CONFIG		(0x08)
+ + #define EMIF4_0_SDRAM_CONFIG2		(0x0C)
+ + #define EMIF4_0_SDRAM_REF_CTRL		(0x10)
+ + #define EMIF4_0_SDRAM_REF_CTRL_SHADOW	(0x14)
+ + #define EMIF4_0_SDRAM_TIM_1		(0x18)
+ + #define EMIF4_0_SDRAM_TIM_1_SHADOW	(0x1C)
+ + #define EMIF4_0_SDRAM_TIM_2		(0x20)
+ + #define EMIF4_0_SDRAM_TIM_2_SHADOW	(0x24)
+ + #define EMIF4_0_SDRAM_TIM_3		(0x28)
+ + #define EMIF4_0_SDRAM_TIM_3_SHADOW	(0x2C)
+ + #define EMIF4_0_SDRAM_MGMT_CTRL		(0x38)
+ + #define EMIF4_0_SDRAM_MGMT_CTRL_SHADOW	(0x3C)
+ + #define EMIF4_0_IODFT_TLGC		(0x60)
+ + #define EMIF4_0_ZQ_CONFIG		(0xC8)
+ + #define EMIF4_0_DDR_PHY_CTRL_1		(0xE4)
+ + #define EMIF4_0_DDR_PHY_CTRL_1_SHADOW	(0xE8)
+ + 
+ + #define SELF_REFRESH_ENABLE(m)		(0x2 << 8 | (m << 4))
+ + #define SELF_REFRESH_DISABLE		(0x0 << 8)
+ + 
+ + #define SDRAM_TYPE_MASK			0xe0000000
+ + #define SDRAM_TYPE_SHIFT		29
+ + #endif /* __EMIF_H */
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/gpio.h linux-3.2.1/arch/arm/plat-ckb/include/plat/gpio.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/gpio.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/gpio.h	2014-11-25 13:19:15.164003806 +0900
+ ***************
+ *** 0 ****
+ --- 1,242 ----
+ + /*
+ +  * arch/arm/plat-omap/include/mach/gpio.h
+ +  *
+ +  * OMAP GPIO handling defines and functions
+ +  *
+ +  * Copyright (C) 2003-2005 Nokia Corporation
+ +  *
+ +  * Written by Juha Yrjölä <juha.yrjola@nokia.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; either version 2 of the License, or
+ +  * (at your option) any later version.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ +  *
+ +  */
+ + 
+ + #ifndef __ASM_ARCH_OMAP_GPIO_H
+ + #define __ASM_ARCH_OMAP_GPIO_H
+ + 
+ + #ifndef __ASSEMBLER__
+ + #include <linux/io.h>
+ + #include <linux/platform_device.h>
+ + #include <mach/irqs.h>
+ + 
+ + #endif
+ + #define OMAP1_MPUIO_BASE			0xfffb5000
+ + 
+ + /*
+ +  * These are the omap15xx/16xx offsets. The omap7xx offset are
+ +  * OMAP_MPUIO_ / 2 offsets below.
+ +  */
+ + #define OMAP_MPUIO_INPUT_LATCH		0x00
+ + #define OMAP_MPUIO_OUTPUT		0x04
+ + #define OMAP_MPUIO_IO_CNTL		0x08
+ + #define OMAP_MPUIO_KBR_LATCH		0x10
+ + #define OMAP_MPUIO_KBC			0x14
+ + #define OMAP_MPUIO_GPIO_EVENT_MODE	0x18
+ + #define OMAP_MPUIO_GPIO_INT_EDGE	0x1c
+ + #define OMAP_MPUIO_KBD_INT		0x20
+ + #define OMAP_MPUIO_GPIO_INT		0x24
+ + #define OMAP_MPUIO_KBD_MASKIT		0x28
+ + #define OMAP_MPUIO_GPIO_MASKIT		0x2c
+ + #define OMAP_MPUIO_GPIO_DEBOUNCING	0x30
+ + #define OMAP_MPUIO_LATCH		0x34
+ + 
+ + #define OMAP34XX_NR_GPIOS		6
+ + 
+ + /*
+ +  * OMAP1510 GPIO registers
+ +  */
+ + #define OMAP1510_GPIO_DATA_INPUT	0x00
+ + #define OMAP1510_GPIO_DATA_OUTPUT	0x04
+ + #define OMAP1510_GPIO_DIR_CONTROL	0x08
+ + #define OMAP1510_GPIO_INT_CONTROL	0x0c
+ + #define OMAP1510_GPIO_INT_MASK		0x10
+ + #define OMAP1510_GPIO_INT_STATUS	0x14
+ + #define OMAP1510_GPIO_PIN_CONTROL	0x18
+ + 
+ + #define OMAP1510_IH_GPIO_BASE		64
+ + 
+ + /*
+ +  * OMAP1610 specific GPIO registers
+ +  */
+ + #define OMAP1610_GPIO_REVISION		0x0000
+ + #define OMAP1610_GPIO_SYSCONFIG		0x0010
+ + #define OMAP1610_GPIO_SYSSTATUS		0x0014
+ + #define OMAP1610_GPIO_IRQSTATUS1	0x0018
+ + #define OMAP1610_GPIO_IRQENABLE1	0x001c
+ + #define OMAP1610_GPIO_WAKEUPENABLE	0x0028
+ + #define OMAP1610_GPIO_DATAIN		0x002c
+ + #define OMAP1610_GPIO_DATAOUT		0x0030
+ + #define OMAP1610_GPIO_DIRECTION		0x0034
+ + #define OMAP1610_GPIO_EDGE_CTRL1	0x0038
+ + #define OMAP1610_GPIO_EDGE_CTRL2	0x003c
+ + #define OMAP1610_GPIO_CLEAR_IRQENABLE1	0x009c
+ + #define OMAP1610_GPIO_CLEAR_WAKEUPENA	0x00a8
+ + #define OMAP1610_GPIO_CLEAR_DATAOUT	0x00b0
+ + #define OMAP1610_GPIO_SET_IRQENABLE1	0x00dc
+ + #define OMAP1610_GPIO_SET_WAKEUPENA	0x00e8
+ + #define OMAP1610_GPIO_SET_DATAOUT	0x00f0
+ + 
+ + /*
+ +  * OMAP7XX specific GPIO registers
+ +  */
+ + #define OMAP7XX_GPIO_DATA_INPUT		0x00
+ + #define OMAP7XX_GPIO_DATA_OUTPUT	0x04
+ + #define OMAP7XX_GPIO_DIR_CONTROL	0x08
+ + #define OMAP7XX_GPIO_INT_CONTROL	0x0c
+ + #define OMAP7XX_GPIO_INT_MASK		0x10
+ + #define OMAP7XX_GPIO_INT_STATUS		0x14
+ + 
+ + /*
+ +  * omap2+ specific GPIO registers
+ +  */
+ + #define OMAP24XX_GPIO_REVISION		0x0000
+ + #define OMAP24XX_GPIO_IRQSTATUS1	0x0018
+ + #define OMAP24XX_GPIO_IRQSTATUS2	0x0028
+ + #define OMAP24XX_GPIO_IRQENABLE2	0x002c
+ + #define OMAP24XX_GPIO_IRQENABLE1	0x001c
+ + #define OMAP24XX_GPIO_WAKE_EN		0x0020
+ + #define OMAP24XX_GPIO_CTRL		0x0030
+ + #define OMAP24XX_GPIO_OE		0x0034
+ + #define OMAP24XX_GPIO_DATAIN		0x0038
+ + #define OMAP24XX_GPIO_DATAOUT		0x003c
+ + #define OMAP24XX_GPIO_LEVELDETECT0	0x0040
+ + #define OMAP24XX_GPIO_LEVELDETECT1	0x0044
+ + #define OMAP24XX_GPIO_RISINGDETECT	0x0048
+ + #define OMAP24XX_GPIO_FALLINGDETECT	0x004c
+ + #define OMAP24XX_GPIO_DEBOUNCE_EN	0x0050
+ + #define OMAP24XX_GPIO_DEBOUNCE_VAL	0x0054
+ + #define OMAP24XX_GPIO_CLEARIRQENABLE1	0x0060
+ + #define OMAP24XX_GPIO_SETIRQENABLE1	0x0064
+ + #define OMAP24XX_GPIO_CLEARWKUENA	0x0080
+ + #define OMAP24XX_GPIO_SETWKUENA		0x0084
+ + #define OMAP24XX_GPIO_CLEARDATAOUT	0x0090
+ + #define OMAP24XX_GPIO_SETDATAOUT	0x0094
+ + 
+ + #define OMAP4_GPIO_REVISION		0x0000
+ + #define OMAP4_GPIO_EOI			0x0020
+ + #define OMAP4_GPIO_IRQSTATUSRAW0	0x0024
+ + #define OMAP4_GPIO_IRQSTATUSRAW1	0x0028
+ + #define OMAP4_GPIO_IRQSTATUS0		0x002c
+ + #define OMAP4_GPIO_IRQSTATUS1		0x0030
+ + #define OMAP4_GPIO_IRQSTATUSSET0	0x0034
+ + #define OMAP4_GPIO_IRQSTATUSSET1	0x0038
+ + #define OMAP4_GPIO_IRQSTATUSCLR0	0x003c
+ + #define OMAP4_GPIO_IRQSTATUSCLR1	0x0040
+ + #define OMAP4_GPIO_IRQWAKEN0		0x0044
+ + #define OMAP4_GPIO_IRQWAKEN1		0x0048
+ + #define OMAP4_GPIO_IRQENABLE1		0x011c
+ + #define OMAP4_GPIO_WAKE_EN		0x0120
+ + #define OMAP4_GPIO_IRQSTATUS2		0x0128
+ + #define OMAP4_GPIO_IRQENABLE2		0x012c
+ + #define OMAP4_GPIO_CTRL			0x0130
+ + #define OMAP4_GPIO_OE			0x0134
+ + #define OMAP4_GPIO_DATAIN		0x0138
+ + #define OMAP4_GPIO_DATAOUT		0x013c
+ + #define OMAP4_GPIO_LEVELDETECT0		0x0140
+ + #define OMAP4_GPIO_LEVELDETECT1		0x0144
+ + #define OMAP4_GPIO_RISINGDETECT		0x0148
+ + #define OMAP4_GPIO_FALLINGDETECT	0x014c
+ + #define OMAP4_GPIO_DEBOUNCENABLE	0x0150
+ + #define OMAP4_GPIO_DEBOUNCINGTIME	0x0154
+ + #define OMAP4_GPIO_CLEARIRQENABLE1	0x0160
+ + #define OMAP4_GPIO_SETIRQENABLE1	0x0164
+ + #define OMAP4_GPIO_CLEARWKUENA		0x0180
+ + #define OMAP4_GPIO_SETWKUENA		0x0184
+ + #define OMAP4_GPIO_CLEARDATAOUT		0x0190
+ + #define OMAP4_GPIO_SETDATAOUT		0x0194
+ + 
+ + #define OMAP_MPUIO(nr)		(OMAP_MAX_GPIO_LINES + (nr))
+ + #define OMAP_GPIO_IS_MPUIO(nr)	((nr) >= OMAP_MAX_GPIO_LINES)
+ + 
+ + #define OMAP_GPIO_IRQ(nr)	(OMAP_GPIO_IS_MPUIO(nr) ? \
+ + 				 IH_MPUIO_BASE + ((nr) & 0x0f) : \
+ + 				 IH_GPIO_BASE + (nr))
+ + 
+ + #define METHOD_MPUIO		0
+ + #define METHOD_GPIO_1510	1
+ + #define METHOD_GPIO_1610	2
+ + #define METHOD_GPIO_7XX		3
+ + #define METHOD_GPIO_24XX	5
+ + #define METHOD_GPIO_44XX	6
+ + 
+ + #ifndef __ASSEMBLER__
+ + struct omap_gpio_dev_attr {
+ + 	int bank_width;		/* GPIO bank width */
+ + 	bool dbck_flag;		/* dbck required or not - True for OMAP3&4 */
+ + };
+ + 
+ + struct omap_gpio_reg_offs {
+ + 	u16 revision;
+ + 	u16 direction;
+ + 	u16 datain;
+ + 	u16 dataout;
+ + 	u16 set_dataout;
+ + 	u16 clr_dataout;
+ + 	u16 irqstatus;
+ + 	u16 irqstatus2;
+ + 	u16 irqenable;
+ + 	u16 set_irqenable;
+ + 	u16 clr_irqenable;
+ + 	u16 debounce;
+ + 	u16 debounce_en;
+ + 
+ + 	bool irqenable_inv;
+ + };
+ + 
+ + struct omap_gpio_platform_data {
+ + 	u16 virtual_irq_start;
+ + 	int bank_type;
+ + 	int bank_width;		/* GPIO bank width */
+ + 	int bank_stride;	/* Only needed for omap1 MPUIO */
+ + 	bool dbck_flag;		/* dbck required or not - True for OMAP3&4 */
+ + 
+ + 	struct omap_gpio_reg_offs *regs;
+ + };
+ + 
+ + /* TODO: Analyze removing gpio_bank_count usage from driver code */
+ + extern int gpio_bank_count;
+ + 
+ + extern void omap2_gpio_prepare_for_idle(int off_mode);
+ + extern void omap2_gpio_resume_after_idle(void);
+ + extern void omap_set_gpio_debounce(int gpio, int enable);
+ + extern void omap_set_gpio_debounce_time(int gpio, int enable);
+ + extern void omap_gpio_save_context(void);
+ + extern void omap_gpio_restore_context(void);
+ + /*-------------------------------------------------------------------------*/
+ + 
+ + /* Wrappers for "new style" GPIO calls, using the new infrastructure
+ +  * which lets us plug in FPGA, I2C, and other implementations.
+ +  * *
+ +  * The original OMAP-specific calls should eventually be removed.
+ +  */
+ + 
+ + #include <linux/errno.h>
+ + #include <asm-generic/gpio.h>
+ + 
+ + static inline int irq_to_gpio(unsigned irq)
+ + {
+ + 	int tmp;
+ + 
+ + 	/* SOC gpio */
+ + 	tmp = irq - IH_GPIO_BASE;
+ + 	if (tmp < OMAP_MAX_GPIO_LINES)
+ + 		return tmp;
+ + 
+ + 	/* we don't supply reverse mappings for non-SOC gpios */
+ + 	return -EIO;
+ + }
+ + #endif
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/gpio-switch.h linux-3.2.1/arch/arm/plat-ckb/include/plat/gpio-switch.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/gpio-switch.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/gpio-switch.h	2014-11-25 13:19:15.164003806 +0900
+ ***************
+ *** 0 ****
+ --- 1,54 ----
+ + /*
+ +  * GPIO switch definitions
+ +  *
+ +  * Copyright (C) 2006 Nokia Corporation
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #ifndef __ASM_ARCH_OMAP_GPIO_SWITCH_H
+ + #define __ASM_ARCH_OMAP_GPIO_SWITCH_H
+ + 
+ + #include <linux/types.h>
+ + 
+ + /* Cover:
+ +  *	high -> closed
+ +  *	low  -> open
+ +  * Connection:
+ +  *	high -> connected
+ +  *	low  -> disconnected
+ +  * Activity:
+ +  *	high -> active
+ +  *	low  -> inactive
+ +  *
+ +  */
+ + #define OMAP_GPIO_SWITCH_TYPE_COVER		0x0000
+ + #define OMAP_GPIO_SWITCH_TYPE_CONNECTION	0x0001
+ + #define OMAP_GPIO_SWITCH_TYPE_ACTIVITY		0x0002
+ + #define OMAP_GPIO_SWITCH_FLAG_INVERTED		0x0001
+ + #define OMAP_GPIO_SWITCH_FLAG_OUTPUT		0x0002
+ + 
+ + struct omap_gpio_switch {
+ + 	const char *name;
+ + 	s16 gpio;
+ + 	unsigned flags:4;
+ + 	unsigned type:4;
+ + 
+ + 	/* Time in ms to debounce when transitioning from
+ + 	 * inactive state to active state. */
+ + 	u16 debounce_rising;
+ + 	/* Same for transition from active to inactive state. */
+ + 	u16 debounce_falling;
+ + 
+ + 	/* notify board-specific code about state changes */
+ + 	void (* notify)(void *data, int state);
+ + 	void *notify_data;
+ + };
+ + 
+ + /* Call at init time only */
+ + extern void omap_register_gpio_switches(const struct omap_gpio_switch *tbl,
+ + 					int count);
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/gpmc.h linux-3.2.1/arch/arm/plat-ckb/include/plat/gpmc.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/gpmc.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/gpmc.h	2014-11-25 13:19:15.167997141 +0900
+ ***************
+ *** 0 ****
+ --- 1,179 ----
+ + /*
+ +  * General-Purpose Memory Controller for OMAP2
+ +  *
+ +  * Copyright (C) 2005-2006 Nokia Corporation
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #ifndef __OMAP2_GPMC_H
+ + #define __OMAP2_GPMC_H
+ + 
+ + /* Maximum Number of Chip Selects */
+ + #define GPMC_CS_NUM		8
+ + 
+ + #define GPMC_CS_CONFIG1		0x00
+ + #define GPMC_CS_CONFIG2		0x04
+ + #define GPMC_CS_CONFIG3		0x08
+ + #define GPMC_CS_CONFIG4		0x0c
+ + #define GPMC_CS_CONFIG5		0x10
+ + #define GPMC_CS_CONFIG6		0x14
+ + #define GPMC_CS_CONFIG7		0x18
+ + #define GPMC_CS_NAND_COMMAND	0x1c
+ + #define GPMC_CS_NAND_ADDRESS	0x20
+ + #define GPMC_CS_NAND_DATA	0x24
+ + 
+ + /* Control Commands */
+ + #define GPMC_CONFIG_RDY_BSY	0x00000001
+ + #define GPMC_CONFIG_DEV_SIZE	0x00000002
+ + #define GPMC_CONFIG_DEV_TYPE	0x00000003
+ + #define GPMC_SET_IRQ_STATUS	0x00000004
+ + #define GPMC_CONFIG_WP		0x00000005
+ + 
+ + #define GPMC_GET_IRQ_STATUS	0x00000006
+ + #define GPMC_PREFETCH_FIFO_CNT	0x00000007 /* bytes available in FIFO for r/w */
+ + #define GPMC_PREFETCH_COUNT	0x00000008 /* remaining bytes to be read/write*/
+ + #define GPMC_STATUS_BUFFER	0x00000009 /* 1: buffer is available to write */
+ + 
+ + #define GPMC_NAND_COMMAND	0x0000000a
+ + #define GPMC_NAND_ADDRESS	0x0000000b
+ + #define GPMC_NAND_DATA		0x0000000c
+ + 
+ + #define GPMC_ENABLE_IRQ		0x0000000d
+ + 
+ + /* ECC commands */
+ + #define GPMC_ECC_READ		0 /* Reset Hardware ECC for read */
+ + #define GPMC_ECC_WRITE		1 /* Reset Hardware ECC for write */
+ + #define GPMC_ECC_READSYN	2 /* Reset before syndrom is read back */
+ + 
+ + #define GPMC_CONFIG1_WRAPBURST_SUPP     (1 << 31)
+ + #define GPMC_CONFIG1_READMULTIPLE_SUPP  (1 << 30)
+ + #define GPMC_CONFIG1_READTYPE_ASYNC     (0 << 29)
+ + #define GPMC_CONFIG1_READTYPE_SYNC      (1 << 29)
+ + #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
+ + #define GPMC_CONFIG1_WRITETYPE_ASYNC    (0 << 27)
+ + #define GPMC_CONFIG1_WRITETYPE_SYNC     (1 << 27)
+ + #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
+ + #define GPMC_CONFIG1_PAGE_LEN(val)      ((val & 3) << 23)
+ + #define GPMC_CONFIG1_WAIT_READ_MON      (1 << 22)
+ + #define GPMC_CONFIG1_WAIT_WRITE_MON     (1 << 21)
+ + #define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18)
+ + #define GPMC_CONFIG1_WAIT_PIN_SEL(val)  ((val & 3) << 16)
+ + #define GPMC_CONFIG1_DEVICESIZE(val)    ((val & 3) << 12)
+ + #define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
+ + #define GPMC_CONFIG1_DEVICETYPE(val)    ((val & 3) << 10)
+ + #define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
+ + #define GPMC_CONFIG1_MUXADDDATA         (1 << 9)
+ + #define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
+ + #define GPMC_CONFIG1_FCLK_DIV(val)      (val & 3)
+ + #define GPMC_CONFIG1_FCLK_DIV2          (GPMC_CONFIG1_FCLK_DIV(1))
+ + #define GPMC_CONFIG1_FCLK_DIV3          (GPMC_CONFIG1_FCLK_DIV(2))
+ + #define GPMC_CONFIG1_FCLK_DIV4          (GPMC_CONFIG1_FCLK_DIV(3))
+ + #define GPMC_CONFIG7_CSVALID		(1 << 6)
+ + 
+ + #define GPMC_DEVICETYPE_NOR		0
+ + #define GPMC_DEVICETYPE_NAND		2
+ + #define GPMC_CONFIG_WRITEPROTECT	0x00000010
+ + #define GPMC_STATUS_BUFF_EMPTY		0x00000001
+ + #define WR_RD_PIN_MONITORING		0x00600000
+ + #define GPMC_PREFETCH_STATUS_FIFO_CNT(val)	((val >> 24) & 0x7F)
+ + #define GPMC_PREFETCH_STATUS_COUNT(val)	(val & 0x00003fff)
+ + #define GPMC_IRQ_FIFOEVENTENABLE	0x01
+ + #define GPMC_IRQ_COUNT_EVENT		0x02
+ + 
+ + #define PREFETCH_FIFOTHRESHOLD_MAX	0x40
+ + #define PREFETCH_FIFOTHRESHOLD(val)	((val) << 8)
+ + 
+ + enum omap_ecc {
+ + 		/* 1-bit ecc: stored at end of spare area */
+ + 	OMAP_ECC_HAMMING_CODE_DEFAULT = 0, /* Default, s/w method */
+ + 	OMAP_ECC_HAMMING_CODE_HW, /* gpmc to detect the error */
+ + 		/* 1-bit ecc: stored at beginning of spare area as romcode */
+ + 	OMAP_ECC_HAMMING_CODE_HW_ROMCODE, /* gpmc method & romcode layout */
+ + 	OMAP_ECC_BCH4_CODE_HW, /* gpmc bch detection & s/w method correction */
+ + 	OMAP_ECC_BCH8_CODE_HW, /* gpmc bch detection & s/w method correction */
+ + };
+ + 
+ + /*
+ +  * Note that all values in this struct are in nanoseconds except sync_clk
+ +  * (which is in picoseconds), while the register values are in gpmc_fck cycles.
+ +  */
+ + struct gpmc_timings {
+ + 	/* Minimum clock period for synchronous mode (in picoseconds) */
+ + 	u32 sync_clk;
+ + 
+ + 	/* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
+ + 	u16 cs_on;		/* Assertion time */
+ + 	u16 cs_rd_off;		/* Read deassertion time */
+ + 	u16 cs_wr_off;		/* Write deassertion time */
+ + 
+ + 	/* ADV signal timings corresponding to GPMC_CONFIG3 */
+ + 	u16 adv_on;		/* Assertion time */
+ + 	u16 adv_rd_off;		/* Read deassertion time */
+ + 	u16 adv_wr_off;		/* Write deassertion time */
+ + 
+ + 	/* WE signals timings corresponding to GPMC_CONFIG4 */
+ + 	u16 we_on;		/* WE assertion time */
+ + 	u16 we_off;		/* WE deassertion time */
+ + 
+ + 	/* OE signals timings corresponding to GPMC_CONFIG4 */
+ + 	u16 oe_on;		/* OE assertion time */
+ + 	u16 oe_off;		/* OE deassertion time */
+ + 
+ + 	/* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
+ + 	u16 page_burst_access;	/* Multiple access word delay */
+ + 	u16 access;		/* Start-cycle to first data valid delay */
+ + 	u16 rd_cycle;		/* Total read cycle time */
+ + 	u16 wr_cycle;		/* Total write cycle time */
+ + 
+ + 	/* The following are only on OMAP3430 */
+ + 	u16 wr_access;		/* WRACCESSTIME */
+ + 	u16 wr_data_mux_bus;	/* WRDATAONADMUXBUS */
+ + };
+ + 
+ + 
+ + struct gpmc_devices_info {
+ + 	void	*pdata;
+ + 	int	flag;
+ + };
+ + 
+ + #define	GPMC_DEVICE_NAND	(1 << 0)
+ + #define	GPMC_DEVICE_ONENAND	(1 << 1)
+ + #define	GPMC_DEVICE_NOR		(1 << 2)
+ + #define	GPMC_DEVICE_SMC91X	(1 << 3)
+ + #define	GPMC_DEVICE_SMS911X	(1 << 4)
+ + #define	GPMC_DEVICE_TUSB6010	(1 << 5)
+ + 
+ + extern int omap_init_gpmc(struct gpmc_devices_info *pdata, int pdata_len);
+ + 
+ + extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
+ + extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps);
+ + extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
+ + extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
+ + extern unsigned long gpmc_get_fclk_period(void);
+ + 
+ + extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
+ + extern u32 gpmc_cs_read_reg(int cs, int idx);
+ + extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk);
+ + extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
+ + extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
+ + extern void gpmc_cs_free(int cs);
+ + extern int gpmc_cs_set_reserved(int cs, int reserved);
+ + extern int gpmc_cs_reserved(int cs);
+ + extern int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
+ + 					unsigned int u32_count, int is_write);
+ + extern int gpmc_prefetch_reset(int cs);
+ + extern void omap3_gpmc_save_context(void);
+ + extern void omap3_gpmc_restore_context(void);
+ + extern int gpmc_read_status(int cmd);
+ + extern int gpmc_cs_configure(int cs, int cmd, int wval);
+ + extern int gpmc_nand_read(int cs, int cmd);
+ + extern int gpmc_nand_write(int cs, int cmd, int wval);
+ + 
+ + int gpmc_enable_hwecc(int ecc, int cs, int mode, int dev_width, int ecc_size);
+ + int gpmc_calculate_ecc(int ecc, int cs, const u_char *dat, u_char *ecc_code);
+ + int gpmc_suspend(void);
+ + int gpmc_resume(void);
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/hardware.h linux-3.2.1/arch/arm/plat-ckb/include/plat/hardware.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/hardware.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/hardware.h	2014-11-25 13:19:15.167997141 +0900
+ ***************
+ *** 0 ****
+ --- 1,246 ----
+ + /*
+ +  * arch/arm/plat-omap/include/mach/hardware.h
+ +  *
+ +  * Hardware definitions for TI OMAP processors and boards
+ +  *
+ +  * NOTE: Please put device driver specific defines into a separate header
+ +  *	 file for each driver.
+ +  *
+ +  * Copyright (C) 2001 RidgeRun, Inc.
+ +  * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
+ +  *
+ +  * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
+ +  *                          and Dirk Behme <dirk.behme@de.bosch.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify it
+ +  * under the terms of the GNU General Public License as published by the
+ +  * Free Software Foundation; either version 2 of the License, or (at your
+ +  * option) any later version.
+ +  *
+ +  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ +  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ +  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ +  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ +  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ +  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ +  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ +  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ +  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ +  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ +  *
+ +  * You should have received a copy of the GNU General Public License along
+ +  * with this program; if not, write to the Free Software Foundation, Inc.,
+ +  * 675 Mass Ave, Cambridge, MA 02139, USA.
+ +  */
+ + 
+ + #ifndef __ASM_ARCH_OMAP_HARDWARE_H
+ + #define __ASM_ARCH_OMAP_HARDWARE_H
+ + 
+ + #include <asm/sizes.h>
+ + #ifndef __ASSEMBLER__
+ + #include <asm/types.h>
+ + #include <plat/cpu.h>
+ + #endif
+ + #include <plat/serial.h>
+ + 
+ + /*
+ +  * ---------------------------------------------------------------------------
+ +  * Common definitions for all OMAP processors
+ +  * NOTE: Put all processor or board specific parts to the special header
+ +  *	 files.
+ +  * ---------------------------------------------------------------------------
+ +  */
+ + 
+ + /*
+ +  * ----------------------------------------------------------------------------
+ +  * Timers
+ +  * ----------------------------------------------------------------------------
+ +  */
+ + #define OMAP_MPU_TIMER1_BASE	(0xfffec500)
+ + #define OMAP_MPU_TIMER2_BASE	(0xfffec600)
+ + #define OMAP_MPU_TIMER3_BASE	(0xfffec700)
+ + #define MPU_TIMER_FREE		(1 << 6)
+ + #define MPU_TIMER_CLOCK_ENABLE	(1 << 5)
+ + #define MPU_TIMER_AR		(1 << 1)
+ + #define MPU_TIMER_ST		(1 << 0)
+ + 
+ + /*
+ +  * ----------------------------------------------------------------------------
+ +  * Clocks
+ +  * ----------------------------------------------------------------------------
+ +  */
+ + #define CLKGEN_REG_BASE		(0xfffece00)
+ + #define ARM_CKCTL		(CLKGEN_REG_BASE + 0x0)
+ + #define ARM_IDLECT1		(CLKGEN_REG_BASE + 0x4)
+ + #define ARM_IDLECT2		(CLKGEN_REG_BASE + 0x8)
+ + #define ARM_EWUPCT		(CLKGEN_REG_BASE + 0xC)
+ + #define ARM_RSTCT1		(CLKGEN_REG_BASE + 0x10)
+ + #define ARM_RSTCT2		(CLKGEN_REG_BASE + 0x14)
+ + #define ARM_SYSST		(CLKGEN_REG_BASE + 0x18)
+ + #define ARM_IDLECT3		(CLKGEN_REG_BASE + 0x24)
+ + 
+ + #define CK_RATEF		1
+ + #define CK_IDLEF		2
+ + #define CK_ENABLEF		4
+ + #define CK_SELECTF		8
+ + #define SETARM_IDLE_SHIFT
+ + 
+ + /* DPLL control registers */
+ + #define DPLL_CTL		(0xfffecf00)
+ + 
+ + /* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
+ + #define DSP_CONFIG_REG_BASE     IOMEM(0xe1008000)
+ + #define DSP_CKCTL		(DSP_CONFIG_REG_BASE + 0x0)
+ + #define DSP_IDLECT1		(DSP_CONFIG_REG_BASE + 0x4)
+ + #define DSP_IDLECT2		(DSP_CONFIG_REG_BASE + 0x8)
+ + #define DSP_RSTCT2		(DSP_CONFIG_REG_BASE + 0x14)
+ + 
+ + /*
+ +  * ---------------------------------------------------------------------------
+ +  * UPLD
+ +  * ---------------------------------------------------------------------------
+ +  */
+ + #define ULPD_REG_BASE		(0xfffe0800)
+ + #define ULPD_IT_STATUS		(ULPD_REG_BASE + 0x14)
+ + #define ULPD_SETUP_ANALOG_CELL_3	(ULPD_REG_BASE + 0x24)
+ + #define ULPD_CLOCK_CTRL		(ULPD_REG_BASE + 0x30)
+ + #	define DIS_USB_PVCI_CLK		(1 << 5)	/* no USB/FAC synch */
+ + #	define USB_MCLK_EN		(1 << 4)	/* enable W4_USB_CLKO */
+ + #define ULPD_SOFT_REQ		(ULPD_REG_BASE + 0x34)
+ + #	define SOFT_UDC_REQ		(1 << 4)
+ + #	define SOFT_USB_CLK_REQ		(1 << 3)
+ + #	define SOFT_DPLL_REQ		(1 << 0)
+ + #define ULPD_DPLL_CTRL		(ULPD_REG_BASE + 0x3c)
+ + #define ULPD_STATUS_REQ		(ULPD_REG_BASE + 0x40)
+ + #define ULPD_APLL_CTRL		(ULPD_REG_BASE + 0x4c)
+ + #define ULPD_POWER_CTRL		(ULPD_REG_BASE + 0x50)
+ + #define ULPD_SOFT_DISABLE_REQ_REG	(ULPD_REG_BASE + 0x68)
+ + #	define DIS_MMC2_DPLL_REQ	(1 << 11)
+ + #	define DIS_MMC1_DPLL_REQ	(1 << 10)
+ + #	define DIS_UART3_DPLL_REQ	(1 << 9)
+ + #	define DIS_UART2_DPLL_REQ	(1 << 8)
+ + #	define DIS_UART1_DPLL_REQ	(1 << 7)
+ + #	define DIS_USB_HOST_DPLL_REQ	(1 << 6)
+ + #define ULPD_SDW_CLK_DIV_CTRL_SEL	(ULPD_REG_BASE + 0x74)
+ + #define ULPD_CAM_CLK_CTRL	(ULPD_REG_BASE + 0x7c)
+ + 
+ + /*
+ +  * ---------------------------------------------------------------------------
+ +  * Watchdog timer
+ +  * ---------------------------------------------------------------------------
+ +  */
+ + 
+ + /* Watchdog timer within the OMAP3.2 gigacell */
+ + #define OMAP_MPU_WATCHDOG_BASE	(0xfffec800)
+ + #define OMAP_WDT_TIMER		(OMAP_MPU_WATCHDOG_BASE + 0x0)
+ + #define OMAP_WDT_LOAD_TIM	(OMAP_MPU_WATCHDOG_BASE + 0x4)
+ + #define OMAP_WDT_READ_TIM	(OMAP_MPU_WATCHDOG_BASE + 0x4)
+ + #define OMAP_WDT_TIMER_MODE	(OMAP_MPU_WATCHDOG_BASE + 0x8)
+ + 
+ + /*
+ +  * ----------------------------------------------------------------------------
+ +  * System control registers
+ +  * ----------------------------------------------------------------------------
+ +  */
+ + #define MOD_CONF_CTRL_0		0xfffe1080
+ + #define MOD_CONF_CTRL_1		0xfffe1110
+ + 
+ + /*
+ +  * ----------------------------------------------------------------------------
+ +  * Pin multiplexing registers
+ +  * ----------------------------------------------------------------------------
+ +  */
+ + #define FUNC_MUX_CTRL_0		0xfffe1000
+ + #define FUNC_MUX_CTRL_1		0xfffe1004
+ + #define FUNC_MUX_CTRL_2		0xfffe1008
+ + #define COMP_MODE_CTRL_0	0xfffe100c
+ + #define FUNC_MUX_CTRL_3		0xfffe1010
+ + #define FUNC_MUX_CTRL_4		0xfffe1014
+ + #define FUNC_MUX_CTRL_5		0xfffe1018
+ + #define FUNC_MUX_CTRL_6		0xfffe101C
+ + #define FUNC_MUX_CTRL_7		0xfffe1020
+ + #define FUNC_MUX_CTRL_8		0xfffe1024
+ + #define FUNC_MUX_CTRL_9		0xfffe1028
+ + #define FUNC_MUX_CTRL_A		0xfffe102C
+ + #define FUNC_MUX_CTRL_B		0xfffe1030
+ + #define FUNC_MUX_CTRL_C		0xfffe1034
+ + #define FUNC_MUX_CTRL_D		0xfffe1038
+ + #define PULL_DWN_CTRL_0		0xfffe1040
+ + #define PULL_DWN_CTRL_1		0xfffe1044
+ + #define PULL_DWN_CTRL_2		0xfffe1048
+ + #define PULL_DWN_CTRL_3		0xfffe104c
+ + #define PULL_DWN_CTRL_4		0xfffe10ac
+ + 
+ + /* OMAP-1610 specific multiplexing registers */
+ + #define FUNC_MUX_CTRL_E		0xfffe1090
+ + #define FUNC_MUX_CTRL_F		0xfffe1094
+ + #define FUNC_MUX_CTRL_10	0xfffe1098
+ + #define FUNC_MUX_CTRL_11	0xfffe109c
+ + #define FUNC_MUX_CTRL_12	0xfffe10a0
+ + #define PU_PD_SEL_0		0xfffe10b4
+ + #define PU_PD_SEL_1		0xfffe10b8
+ + #define PU_PD_SEL_2		0xfffe10bc
+ + #define PU_PD_SEL_3		0xfffe10c0
+ + #define PU_PD_SEL_4		0xfffe10c4
+ + 
+ + /* Timer32K for 1610 and 1710*/
+ + #define OMAP_TIMER32K_BASE	0xFFFBC400
+ + 
+ + /*
+ +  * ---------------------------------------------------------------------------
+ +  * TIPB bus interface
+ +  * ---------------------------------------------------------------------------
+ +  */
+ + #define TIPB_PUBLIC_CNTL_BASE		0xfffed300
+ + #define MPU_PUBLIC_TIPB_CNTL		(TIPB_PUBLIC_CNTL_BASE + 0x8)
+ + #define TIPB_PRIVATE_CNTL_BASE		0xfffeca00
+ + #define MPU_PRIVATE_TIPB_CNTL		(TIPB_PRIVATE_CNTL_BASE + 0x8)
+ + 
+ + /*
+ +  * ----------------------------------------------------------------------------
+ +  * MPUI interface
+ +  * ----------------------------------------------------------------------------
+ +  */
+ + #define MPUI_BASE			(0xfffec900)
+ + #define MPUI_CTRL			(MPUI_BASE + 0x0)
+ + #define MPUI_DEBUG_ADDR			(MPUI_BASE + 0x4)
+ + #define MPUI_DEBUG_DATA			(MPUI_BASE + 0x8)
+ + #define MPUI_DEBUG_FLAG			(MPUI_BASE + 0xc)
+ + #define MPUI_STATUS_REG			(MPUI_BASE + 0x10)
+ + #define MPUI_DSP_STATUS			(MPUI_BASE + 0x14)
+ + #define MPUI_DSP_BOOT_CONFIG		(MPUI_BASE + 0x18)
+ + #define MPUI_DSP_API_CONFIG		(MPUI_BASE + 0x1c)
+ + 
+ + /*
+ +  * ----------------------------------------------------------------------------
+ +  * LED Pulse Generator
+ +  * ----------------------------------------------------------------------------
+ +  */
+ + #define OMAP_LPG1_BASE			0xfffbd000
+ + #define OMAP_LPG2_BASE			0xfffbd800
+ + #define OMAP_LPG1_LCR			(OMAP_LPG1_BASE + 0x00)
+ + #define OMAP_LPG1_PMR			(OMAP_LPG1_BASE + 0x04)
+ + #define OMAP_LPG2_LCR			(OMAP_LPG2_BASE + 0x00)
+ + #define OMAP_LPG2_PMR			(OMAP_LPG2_BASE + 0x04)
+ + 
+ + /*
+ +  * ----------------------------------------------------------------------------
+ +  * Pulse-Width Light
+ +  * ----------------------------------------------------------------------------
+ +  */
+ + #define OMAP_PWL_BASE			0xfffb5800
+ + #define OMAP_PWL_ENABLE			(OMAP_PWL_BASE + 0x00)
+ + #define OMAP_PWL_CLK_ENABLE		(OMAP_PWL_BASE + 0x04)
+ + 
+ + /*
+ +  * ---------------------------------------------------------------------------
+ +  * Processor specific defines
+ +  * ---------------------------------------------------------------------------
+ +  */
+ + 
+ + 
+ + #include <plat/omap34xx.h>
+ + //#include <plat/omap44xx.h>
+ + #include <plat/am33xx.h>
+ + 
+ + #endif	/* __ASM_ARCH_OMAP_HARDWARE_H */
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/i2c.h linux-3.2.1/arch/arm/plat-ckb/include/plat/i2c.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/i2c.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/i2c.h	2014-11-25 13:19:15.167997141 +0900
+ ***************
+ *** 0 ****
+ --- 1,59 ----
+ + /*
+ +  * Helper module for board specific I2C bus registration
+ +  *
+ +  * Copyright (C) 2009 Nokia Corporation.
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License
+ +  * version 2 as published by the Free Software Foundation.
+ +  *
+ +  * This program is distributed in the hope that it will be useful, but
+ +  * WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ +  * General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ +  * 02110-1301 USA
+ +  *
+ +  */
+ + #ifndef __ASM__ARCH_OMAP_I2C_H
+ + #define __ASM__ARCH_OMAP_I2C_H
+ + 
+ + #include <linux/i2c.h>
+ + #include <linux/i2c-omap.h>
+ + 
+ + #if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
+ + extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
+ + 				 struct i2c_board_info const *info,
+ + 				 unsigned len);
+ + #else
+ + static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
+ + 				 struct i2c_board_info const *info,
+ + 				 unsigned len)
+ + {
+ + 	return 0;
+ + }
+ + #endif
+ + 
+ + /**
+ +  * i2c_dev_attr - OMAP I2C controller device attributes for omap_hwmod
+ +  * @fifo_depth: total controller FIFO size (in bytes)
+ +  * @flags: differences in hardware support capability
+ +  *
+ +  * @fifo_depth represents what exists on the hardware, not what is
+ +  * actually configured at runtime by the device driver.
+ +  */
+ + struct omap_i2c_dev_attr {
+ + 	u8	fifo_depth;
+ + 	u32	flags;
+ + };
+ + 
+ + void __init omap1_i2c_mux_pins(int bus_id);
+ + void __init omap2_i2c_mux_pins(int bus_id);
+ + 
+ + struct omap_hwmod;
+ + int omap_i2c_reset(struct omap_hwmod *oh);
+ + 
+ + #endif /* __ASM__ARCH_OMAP_I2C_H */
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/io.h linux-3.2.1/arch/arm/plat-ckb/include/plat/io.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/io.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/io.h	2014-11-25 13:19:15.167997141 +0900
+ ***************
+ *** 0 ****
+ --- 1,117 ----
+ + /*
+ +  * arch/arm/plat-omap/include/mach/io.h
+ +  *
+ +  * IO definitions for TI OMAP processors and boards
+ +  *
+ +  * Copied from arch/arm/mach-sa1100/include/mach/io.h
+ +  * Copyright (C) 1997-1999 Russell King
+ +  *
+ +  * Copyright (C) 2009 Texas Instruments
+ +  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify it
+ +  * under the terms of the GNU General Public License as published by the
+ +  * Free Software Foundation; either version 2 of the License, or (at your
+ +  * option) any later version.
+ +  *
+ +  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ +  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ +  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ +  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ +  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ +  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ +  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ +  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ +  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ +  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ +  *
+ +  * You should have received a copy of the GNU General Public License along
+ +  * with this program; if not, write to the Free Software Foundation, Inc.,
+ +  * 675 Mass Ave, Cambridge, MA 02139, USA.
+ +  *
+ +  * Modifications:
+ +  *  06-12-1997	RMK	Created.
+ +  *  07-04-1999	RMK	Major cleanup
+ +  */
+ + 
+ + #ifndef __ASM_ARM_ARCH_IO_H
+ + #define __ASM_ARM_ARCH_IO_H
+ + 
+ + #include <mach/hardware.h>
+ + 
+ + #define IO_SPACE_LIMIT 0xffffffff
+ + 
+ + /*
+ +  * We don't actually have real ISA nor PCI buses, but there is so many
+ +  * drivers out there that might just work if we fake them...
+ +  */
+ + #define __io(a)		__typesafe_io(a)
+ + #define __mem_pci(a)	(a)
+ + 
+ + /*
+ +  * ----------------------------------------------------------------------------
+ +  * I/O mapping
+ +  * ----------------------------------------------------------------------------
+ +  */
+ + 
+ + #ifdef __ASSEMBLER__
+ + #define IOMEM(x)		(x)
+ + #else
+ + #define IOMEM(x)		((void __force __iomem *)(x))
+ + #endif
+ + 
+ + #define OMAP2_L3_IO_OFFSET	0x90000000
+ + #define OMAP2_L3_IO_ADDRESS(pa)	IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */
+ + 
+ + #define OMAP2_L4_IO_OFFSET	0xB7100000
+ + #define OMAP2_L4_IO_ADDRESS(pa)	IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */
+ + 
+ + #define AM33XX_L4_WK_IO_OFFSET	0xBA900000
+ + #define AM33XX_L4_WK_IO_ADDRESS(pa)	IOMEM((pa) + AM33XX_L4_WK_IO_OFFSET)
+ + 
+ + /*
+ +  * ----------------------------------------------------------------------------
+ +  * Omap3 specific IO mapping
+ +  * ----------------------------------------------------------------------------
+ +  */
+ + #define L4_34XX_PHYS		L4_34XX_BASE	/* 0x48000000 --> 0xff100000 */
+ + #define L4_34XX_VIRT		(L4_34XX_PHYS + OMAP2_L4_IO_OFFSET)
+ + #define L4_34XX_SIZE		SZ_4M   /* 1MB of 128MB used, want 1MB sect */
+ + 
+ + /*
+ +  * ----------------------------------------------------------------------------
+ +  * AM33XX specific IO mapping
+ +  * ----------------------------------------------------------------------------
+ +  */
+ + #define L4_WK_AM33XX_PHYS	L4_WK_AM33XX_BASE /* 0x44C00000 --> 0xff500000 */
+ + #define L4_WK_AM33XX_VIRT	(L4_WK_AM33XX_PHYS + AM33XX_L4_WK_IO_OFFSET)
+ + #define L4_WK_AM33XX_SIZE	SZ_4M   /* 1MB of 128MB used, want 1MB sect */
+ + 
+ + /*
+ +  * ----------------------------------------------------------------------------
+ +  * Omap specific register access
+ +  * ----------------------------------------------------------------------------
+ +  */
+ + 
+ + #ifndef __ASSEMBLER__
+ + 
+ + /*
+ +  * NOTE: Please use ioremap + __raw_read/write where possible instead of these
+ +  */
+ + 
+ + extern u8 omap_readb(u32 pa);
+ + extern u16 omap_readw(u32 pa);
+ + extern u32 omap_readl(u32 pa);
+ + extern void omap_writeb(u8 v, u32 pa);
+ + extern void omap_writew(u16 v, u32 pa);
+ + extern void omap_writel(u32 v, u32 pa);
+ + 
+ + struct omap_sdrc_params;
+ + extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
+ + 				      struct omap_sdrc_params *sdrc_cs1);
+ + 
+ + extern void __init omap_init_consistent_dma_size(void);
+ + 
+ + #endif
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/iommu2.h linux-3.2.1/arch/arm/plat-ckb/include/plat/iommu2.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/iommu2.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/iommu2.h	2014-11-25 13:19:15.171994475 +0900
+ ***************
+ *** 0 ****
+ --- 1,96 ----
+ + /*
+ +  * omap iommu: omap2 architecture specific definitions
+ +  *
+ +  * Copyright (C) 2008-2009 Nokia Corporation
+ +  *
+ +  * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #ifndef __MACH_IOMMU2_H
+ + #define __MACH_IOMMU2_H
+ + 
+ + #include <linux/io.h>
+ + 
+ + /*
+ +  * MMU Register offsets
+ +  */
+ + #define MMU_REVISION		0x00
+ + #define MMU_SYSCONFIG		0x10
+ + #define MMU_SYSSTATUS		0x14
+ + #define MMU_IRQSTATUS		0x18
+ + #define MMU_IRQENABLE		0x1c
+ + #define MMU_WALKING_ST		0x40
+ + #define MMU_CNTL		0x44
+ + #define MMU_FAULT_AD		0x48
+ + #define MMU_TTB			0x4c
+ + #define MMU_LOCK		0x50
+ + #define MMU_LD_TLB		0x54
+ + #define MMU_CAM			0x58
+ + #define MMU_RAM			0x5c
+ + #define MMU_GFLUSH		0x60
+ + #define MMU_FLUSH_ENTRY		0x64
+ + #define MMU_READ_CAM		0x68
+ + #define MMU_READ_RAM		0x6c
+ + #define MMU_EMU_FAULT_AD	0x70
+ + 
+ + #define MMU_REG_SIZE		256
+ + 
+ + /*
+ +  * MMU Register bit definitions
+ +  */
+ + #define MMU_LOCK_BASE_SHIFT	10
+ + #define MMU_LOCK_BASE_MASK	(0x1f << MMU_LOCK_BASE_SHIFT)
+ + #define MMU_LOCK_BASE(x)	\
+ + 	((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT)
+ + 
+ + #define MMU_LOCK_VICT_SHIFT	4
+ + #define MMU_LOCK_VICT_MASK	(0x1f << MMU_LOCK_VICT_SHIFT)
+ + #define MMU_LOCK_VICT(x)	\
+ + 	((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT)
+ + 
+ + #define MMU_CAM_VATAG_SHIFT	12
+ + #define MMU_CAM_VATAG_MASK \
+ + 	((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
+ + #define MMU_CAM_P		(1 << 3)
+ + #define MMU_CAM_V		(1 << 2)
+ + #define MMU_CAM_PGSZ_MASK	3
+ + #define MMU_CAM_PGSZ_1M		(0 << 0)
+ + #define MMU_CAM_PGSZ_64K	(1 << 0)
+ + #define MMU_CAM_PGSZ_4K		(2 << 0)
+ + #define MMU_CAM_PGSZ_16M	(3 << 0)
+ + 
+ + #define MMU_RAM_PADDR_SHIFT	12
+ + #define MMU_RAM_PADDR_MASK \
+ + 	((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
+ + #define MMU_RAM_ENDIAN_SHIFT	9
+ + #define MMU_RAM_ENDIAN_MASK	(1 << MMU_RAM_ENDIAN_SHIFT)
+ + #define MMU_RAM_ENDIAN_BIG	(1 << MMU_RAM_ENDIAN_SHIFT)
+ + #define MMU_RAM_ENDIAN_LITTLE	(0 << MMU_RAM_ENDIAN_SHIFT)
+ + #define MMU_RAM_ELSZ_SHIFT	7
+ + #define MMU_RAM_ELSZ_MASK	(3 << MMU_RAM_ELSZ_SHIFT)
+ + #define MMU_RAM_ELSZ_8		(0 << MMU_RAM_ELSZ_SHIFT)
+ + #define MMU_RAM_ELSZ_16		(1 << MMU_RAM_ELSZ_SHIFT)
+ + #define MMU_RAM_ELSZ_32		(2 << MMU_RAM_ELSZ_SHIFT)
+ + #define MMU_RAM_ELSZ_NONE	(3 << MMU_RAM_ELSZ_SHIFT)
+ + #define MMU_RAM_MIXED_SHIFT	6
+ + #define MMU_RAM_MIXED_MASK	(1 << MMU_RAM_MIXED_SHIFT)
+ + #define MMU_RAM_MIXED		MMU_RAM_MIXED_MASK
+ + 
+ + /*
+ +  * register accessors
+ +  */
+ + static inline u32 iommu_read_reg(struct omap_iommu *obj, size_t offs)
+ + {
+ + 	return __raw_readl(obj->regbase + offs);
+ + }
+ + 
+ + static inline void iommu_write_reg(struct omap_iommu *obj, u32 val, size_t offs)
+ + {
+ + 	__raw_writel(val, obj->regbase + offs);
+ + }
+ + 
+ + #endif /* __MACH_IOMMU2_H */
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/iommu.h linux-3.2.1/arch/arm/plat-ckb/include/plat/iommu.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/iommu.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/iommu.h	2014-11-25 13:19:15.171994475 +0900
+ ***************
+ *** 0 ****
+ --- 1,177 ----
+ + /*
+ +  * omap iommu: main structures
+ +  *
+ +  * Copyright (C) 2008-2009 Nokia Corporation
+ +  *
+ +  * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #ifndef __MACH_IOMMU_H
+ + #define __MACH_IOMMU_H
+ + 
+ + struct iotlb_entry {
+ + 	u32 da;
+ + 	u32 pa;
+ + 	u32 pgsz, prsvd, valid;
+ + 	union {
+ + 		u16 ap;
+ + 		struct {
+ + 			u32 endian, elsz, mixed;
+ + 		};
+ + 	};
+ + };
+ + 
+ + struct omap_iommu {
+ + 	const char	*name;
+ + 	struct module	*owner;
+ + 	struct clk	*clk;
+ + 	void __iomem	*regbase;
+ + 	struct device	*dev;
+ + 	void		*isr_priv;
+ + 	struct iommu_domain *domain;
+ + 
+ + 	unsigned int	refcount;
+ + 	spinlock_t	iommu_lock;	/* global for this whole object */
+ + 
+ + 	/*
+ + 	 * We don't change iopgd for a situation like pgd for a task,
+ + 	 * but share it globally for each iommu.
+ + 	 */
+ + 	u32		*iopgd;
+ + 	spinlock_t	page_table_lock; /* protect iopgd */
+ + 
+ + 	int		nr_tlb_entries;
+ + 
+ + 	struct list_head	mmap;
+ + 	struct mutex		mmap_lock; /* protect mmap */
+ + 
+ + 	void *ctx; /* iommu context: registres saved area */
+ + 	u32 da_start;
+ + 	u32 da_end;
+ + };
+ + 
+ + struct cr_regs {
+ + 	union {
+ + 		struct {
+ + 			u16 cam_l;
+ + 			u16 cam_h;
+ + 		};
+ + 		u32 cam;
+ + 	};
+ + 	union {
+ + 		struct {
+ + 			u16 ram_l;
+ + 			u16 ram_h;
+ + 		};
+ + 		u32 ram;
+ + 	};
+ + };
+ + 
+ + struct iotlb_lock {
+ + 	short base;
+ + 	short vict;
+ + };
+ + 
+ + /* architecture specific functions */
+ + struct iommu_functions {
+ + 	unsigned long	version;
+ + 
+ + 	int (*enable)(struct omap_iommu *obj);
+ + 	void (*disable)(struct omap_iommu *obj);
+ + 	void (*set_twl)(struct omap_iommu *obj, bool on);
+ + 	u32 (*fault_isr)(struct omap_iommu *obj, u32 *ra);
+ + 
+ + 	void (*tlb_read_cr)(struct omap_iommu *obj, struct cr_regs *cr);
+ + 	void (*tlb_load_cr)(struct omap_iommu *obj, struct cr_regs *cr);
+ + 
+ + 	struct cr_regs *(*alloc_cr)(struct omap_iommu *obj,
+ + 							struct iotlb_entry *e);
+ + 	int (*cr_valid)(struct cr_regs *cr);
+ + 	u32 (*cr_to_virt)(struct cr_regs *cr);
+ + 	void (*cr_to_e)(struct cr_regs *cr, struct iotlb_entry *e);
+ + 	ssize_t (*dump_cr)(struct omap_iommu *obj, struct cr_regs *cr,
+ + 							char *buf);
+ + 
+ + 	u32 (*get_pte_attr)(struct iotlb_entry *e);
+ + 
+ + 	void (*save_ctx)(struct omap_iommu *obj);
+ + 	void (*restore_ctx)(struct omap_iommu *obj);
+ + 	ssize_t (*dump_ctx)(struct omap_iommu *obj, char *buf, ssize_t len);
+ + };
+ + 
+ + struct iommu_platform_data {
+ + 	const char *name;
+ + 	const char *clk_name;
+ + 	const int nr_tlb_entries;
+ + 	u32 da_start;
+ + 	u32 da_end;
+ + };
+ + 
+ + /* IOMMU errors */
+ + #define OMAP_IOMMU_ERR_TLB_MISS		(1 << 0)
+ + #define OMAP_IOMMU_ERR_TRANS_FAULT	(1 << 1)
+ + #define OMAP_IOMMU_ERR_EMU_MISS		(1 << 2)
+ + #define OMAP_IOMMU_ERR_TBLWALK_FAULT	(1 << 3)
+ + #define OMAP_IOMMU_ERR_MULTIHIT_FAULT	(1 << 4)
+ + 
+ + #include <plat/iommu2.h>
+ + 
+ + /*
+ +  * utilities for super page(16MB, 1MB, 64KB and 4KB)
+ +  */
+ + 
+ + #define iopgsz_max(bytes)			\
+ + 	(((bytes) >= SZ_16M) ? SZ_16M :		\
+ + 	 ((bytes) >= SZ_1M)  ? SZ_1M  :		\
+ + 	 ((bytes) >= SZ_64K) ? SZ_64K :		\
+ + 	 ((bytes) >= SZ_4K)  ? SZ_4K  :	0)
+ + 
+ + #define bytes_to_iopgsz(bytes)				\
+ + 	(((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M :	\
+ + 	 ((bytes) == SZ_1M)  ? MMU_CAM_PGSZ_1M  :	\
+ + 	 ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K :	\
+ + 	 ((bytes) == SZ_4K)  ? MMU_CAM_PGSZ_4K  : -1)
+ + 
+ + #define iopgsz_to_bytes(iopgsz)				\
+ + 	(((iopgsz) == MMU_CAM_PGSZ_16M)	? SZ_16M :	\
+ + 	 ((iopgsz) == MMU_CAM_PGSZ_1M)	? SZ_1M  :	\
+ + 	 ((iopgsz) == MMU_CAM_PGSZ_64K)	? SZ_64K :	\
+ + 	 ((iopgsz) == MMU_CAM_PGSZ_4K)	? SZ_4K  : 0)
+ + 
+ + #define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)
+ + 
+ + /*
+ +  * global functions
+ +  */
+ + extern u32 omap_iommu_arch_version(void);
+ + 
+ + extern void omap_iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e);
+ + 
+ + extern int
+ + omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e);
+ + 
+ + extern int omap_iommu_set_isr(const char *name,
+ + 		 int (*isr)(struct omap_iommu *obj, u32 da, u32 iommu_errs,
+ + 				    void *priv),
+ + 			 void *isr_priv);
+ + 
+ + extern void omap_iommu_save_ctx(struct omap_iommu *obj);
+ + extern void omap_iommu_restore_ctx(struct omap_iommu *obj);
+ + 
+ + extern int omap_install_iommu_arch(const struct iommu_functions *ops);
+ + extern void omap_uninstall_iommu_arch(const struct iommu_functions *ops);
+ + 
+ + extern int omap_foreach_iommu_device(void *data,
+ + 				int (*fn)(struct device *, void *));
+ + 
+ + extern ssize_t
+ + omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t len);
+ + extern size_t
+ + omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t len);
+ + struct device *omap_find_iommu_device(const char *name);
+ + 
+ + #endif /* __MACH_IOMMU_H */
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/iopgtable.h linux-3.2.1/arch/arm/plat-ckb/include/plat/iopgtable.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/iopgtable.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/iopgtable.h	2014-11-25 13:19:15.171994475 +0900
+ ***************
+ *** 0 ****
+ --- 1,120 ----
+ + /*
+ +  * omap iommu: pagetable definitions
+ +  *
+ +  * Copyright (C) 2008-2010 Nokia Corporation
+ +  *
+ +  * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #ifndef __PLAT_OMAP_IOMMU_H
+ + #define __PLAT_OMAP_IOMMU_H
+ + 
+ + /*
+ +  * "L2 table" address mask and size definitions.
+ +  */
+ + #define IOPGD_SHIFT		20
+ + #define IOPGD_SIZE		(1UL << IOPGD_SHIFT)
+ + #define IOPGD_MASK		(~(IOPGD_SIZE - 1))
+ + 
+ + /*
+ +  * "section" address mask and size definitions.
+ +  */
+ + #define IOSECTION_SHIFT		20
+ + #define IOSECTION_SIZE		(1UL << IOSECTION_SHIFT)
+ + #define IOSECTION_MASK		(~(IOSECTION_SIZE - 1))
+ + 
+ + /*
+ +  * "supersection" address mask and size definitions.
+ +  */
+ + #define IOSUPER_SHIFT		24
+ + #define IOSUPER_SIZE		(1UL << IOSUPER_SHIFT)
+ + #define IOSUPER_MASK		(~(IOSUPER_SIZE - 1))
+ + 
+ + #define PTRS_PER_IOPGD		(1UL << (32 - IOPGD_SHIFT))
+ + #define IOPGD_TABLE_SIZE	(PTRS_PER_IOPGD * sizeof(u32))
+ + 
+ + /*
+ +  * "small page" address mask and size definitions.
+ +  */
+ + #define IOPTE_SHIFT		12
+ + #define IOPTE_SIZE		(1UL << IOPTE_SHIFT)
+ + #define IOPTE_MASK		(~(IOPTE_SIZE - 1))
+ + 
+ + /*
+ +  * "large page" address mask and size definitions.
+ +  */
+ + #define IOLARGE_SHIFT		16
+ + #define IOLARGE_SIZE		(1UL << IOLARGE_SHIFT)
+ + #define IOLARGE_MASK		(~(IOLARGE_SIZE - 1))
+ + 
+ + #define PTRS_PER_IOPTE		(1UL << (IOPGD_SHIFT - IOPTE_SHIFT))
+ + #define IOPTE_TABLE_SIZE	(PTRS_PER_IOPTE * sizeof(u32))
+ + 
+ + #define IOPAGE_MASK		IOPTE_MASK
+ + 
+ + /**
+ +  * omap_iommu_translate() - va to pa translation
+ +  * @d:		omap iommu descriptor
+ +  * @va:		virtual address
+ +  * @mask:	omap iommu descriptor mask
+ +  *
+ +  * va to pa translation
+ +  */
+ + static inline phys_addr_t omap_iommu_translate(u32 d, u32 va, u32 mask)
+ + {
+ + 	return (d & mask) | (va & (~mask));
+ + }
+ + 
+ + /*
+ +  * some descriptor attributes.
+ +  */
+ + #define IOPGD_TABLE		(1 << 0)
+ + #define IOPGD_SECTION		(2 << 0)
+ + #define IOPGD_SUPER		(1 << 18 | 2 << 0)
+ + 
+ + #define iopgd_is_table(x)	(((x) & 3) == IOPGD_TABLE)
+ + #define iopgd_is_section(x)	(((x) & (1 << 18 | 3)) == IOPGD_SECTION)
+ + #define iopgd_is_super(x)	(((x) & (1 << 18 | 3)) == IOPGD_SUPER)
+ + 
+ + #define IOPTE_SMALL		(2 << 0)
+ + #define IOPTE_LARGE		(1 << 0)
+ + 
+ + #define iopte_is_small(x)	(((x) & 2) == IOPTE_SMALL)
+ + #define iopte_is_large(x)	(((x) & 3) == IOPTE_LARGE)
+ + 
+ + /* to find an entry in a page-table-directory */
+ + #define iopgd_index(da)		(((da) >> IOPGD_SHIFT) & (PTRS_PER_IOPGD - 1))
+ + #define iopgd_offset(obj, da)	((obj)->iopgd + iopgd_index(da))
+ + 
+ + #define iopgd_page_paddr(iopgd)	(*iopgd & ~((1 << 10) - 1))
+ + #define iopgd_page_vaddr(iopgd)	((u32 *)phys_to_virt(iopgd_page_paddr(iopgd)))
+ + 
+ + /* to find an entry in the second-level page table. */
+ + #define iopte_index(da)		(((da) >> IOPTE_SHIFT) & (PTRS_PER_IOPTE - 1))
+ + #define iopte_offset(iopgd, da)	(iopgd_page_vaddr(iopgd) + iopte_index(da))
+ + 
+ + static inline u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa,
+ + 				   u32 flags)
+ + {
+ + 	memset(e, 0, sizeof(*e));
+ + 
+ + 	e->da		= da;
+ + 	e->pa		= pa;
+ + 	e->valid	= 1;
+ + 	/* FIXME: add OMAP1 support */
+ + 	e->pgsz		= flags & MMU_CAM_PGSZ_MASK;
+ + 	e->endian	= flags & MMU_RAM_ENDIAN_MASK;
+ + 	e->elsz		= flags & MMU_RAM_ELSZ_MASK;
+ + 	e->mixed	= flags & MMU_RAM_MIXED_MASK;
+ + 
+ + 	return iopgsz_to_bytes(e->pgsz);
+ + }
+ + 
+ + #define to_iommu(dev)							\
+ + 	(struct omap_iommu *)platform_get_drvdata(to_platform_device(dev))
+ + 
+ + #endif /* __PLAT_OMAP_IOMMU_H */
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/iovmm.h linux-3.2.1/arch/arm/plat-ckb/include/plat/iovmm.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/iovmm.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/iovmm.h	2014-11-25 13:19:15.171994475 +0900
+ ***************
+ *** 0 ****
+ --- 1,89 ----
+ + /*
+ +  * omap iommu: simple virtual address space management
+ +  *
+ +  * Copyright (C) 2008-2009 Nokia Corporation
+ +  *
+ +  * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #ifndef __IOMMU_MMAP_H
+ + #define __IOMMU_MMAP_H
+ + 
+ + #include <linux/iommu.h>
+ + 
+ + struct iovm_struct {
+ + 	struct omap_iommu	*iommu;	/* iommu object which this belongs to */
+ + 	u32			da_start; /* area definition */
+ + 	u32			da_end;
+ + 	u32			flags; /* IOVMF_: see below */
+ + 	struct list_head	list; /* linked in ascending order */
+ + 	const struct sg_table	*sgt; /* keep 'page' <-> 'da' mapping */
+ + 	void			*va; /* mpu side mapped address */
+ + };
+ + 
+ + /*
+ +  * IOVMF_FLAGS: attribute for iommu virtual memory area(iovma)
+ +  *
+ +  * lower 16 bit is used for h/w and upper 16 bit is for s/w.
+ +  */
+ + #define IOVMF_SW_SHIFT		16
+ + 
+ + /*
+ +  * iovma: h/w flags derived from cam and ram attribute
+ +  */
+ + #define IOVMF_CAM_MASK		(~((1 << 10) - 1))
+ + #define IOVMF_RAM_MASK		(~IOVMF_CAM_MASK)
+ + 
+ + #define IOVMF_PGSZ_MASK		(3 << 0)
+ + #define IOVMF_PGSZ_1M		MMU_CAM_PGSZ_1M
+ + #define IOVMF_PGSZ_64K		MMU_CAM_PGSZ_64K
+ + #define IOVMF_PGSZ_4K		MMU_CAM_PGSZ_4K
+ + #define IOVMF_PGSZ_16M		MMU_CAM_PGSZ_16M
+ + 
+ + #define IOVMF_ENDIAN_MASK	(1 << 9)
+ + #define IOVMF_ENDIAN_BIG	MMU_RAM_ENDIAN_BIG
+ + #define IOVMF_ENDIAN_LITTLE	MMU_RAM_ENDIAN_LITTLE
+ + 
+ + #define IOVMF_ELSZ_MASK		(3 << 7)
+ + #define IOVMF_ELSZ_8		MMU_RAM_ELSZ_8
+ + #define IOVMF_ELSZ_16		MMU_RAM_ELSZ_16
+ + #define IOVMF_ELSZ_32		MMU_RAM_ELSZ_32
+ + #define IOVMF_ELSZ_NONE		MMU_RAM_ELSZ_NONE
+ + 
+ + #define IOVMF_MIXED_MASK	(1 << 6)
+ + #define IOVMF_MIXED		MMU_RAM_MIXED
+ + 
+ + /*
+ +  * iovma: s/w flags, used for mapping and umapping internally.
+ +  */
+ + #define IOVMF_MMIO		(1 << IOVMF_SW_SHIFT)
+ + #define IOVMF_ALLOC		(2 << IOVMF_SW_SHIFT)
+ + #define IOVMF_ALLOC_MASK	(3 << IOVMF_SW_SHIFT)
+ + 
+ + /* "superpages" is supported just with physically linear pages */
+ + #define IOVMF_DISCONT		(1 << (2 + IOVMF_SW_SHIFT))
+ + #define IOVMF_LINEAR		(2 << (2 + IOVMF_SW_SHIFT))
+ + #define IOVMF_LINEAR_MASK	(3 << (2 + IOVMF_SW_SHIFT))
+ + 
+ + #define IOVMF_DA_FIXED		(1 << (4 + IOVMF_SW_SHIFT))
+ + 
+ + 
+ + extern struct iovm_struct *omap_find_iovm_area(struct omap_iommu *obj, u32 da);
+ + extern u32
+ + omap_iommu_vmap(struct iommu_domain *domain, struct omap_iommu *obj, u32 da,
+ + 			const struct sg_table *sgt, u32 flags);
+ + extern struct sg_table *omap_iommu_vunmap(struct iommu_domain *domain,
+ + 				struct omap_iommu *obj, u32 da);
+ + extern u32
+ + omap_iommu_vmalloc(struct iommu_domain *domain, struct omap_iommu *obj,
+ + 				u32 da, size_t bytes, u32 flags);
+ + extern void
+ + omap_iommu_vfree(struct iommu_domain *domain, struct omap_iommu *obj,
+ + 				const u32 da);
+ + extern void *omap_da_to_va(struct omap_iommu *obj, u32 da);
+ + 
+ + #endif /* __IOMMU_MMAP_H */
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/irqs-33xx.h linux-3.2.1/arch/arm/plat-ckb/include/plat/irqs-33xx.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/irqs-33xx.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/irqs-33xx.h	2014-11-25 13:19:15.171994475 +0900
+ ***************
+ *** 0 ****
+ --- 1,143 ----
+ + /*
+ +  * AM33XX interrupts.
+ +  *
+ +  * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #ifndef __ARCH_ARM_MACH_OMAP2_AM33XX_IRQS_H
+ + #define __ARCH_ARM_MACH_OMAP2_AM33XX_IRQS_H
+ + 
+ + 
+ + #define AM33XX_IRQ_ELM			4
+ + #define AM33XX_IRQ_PI_NMI		7
+ + #define AM33XX_IRQ_CONTROL_PLATFORM	8
+ + #define AM33XX_IRQ_L3_FLAGMUX0		9
+ + #define AM33XX_IRQ_L3_FLAGMUX1		10
+ + #define AM33XX_IRQ_PRCM			11
+ + #define AM33XX_IRQ_TPCC0_INT_PO0	12
+ + #define AM33XX_IRQ_TPCC0_MPINT_PO	13
+ + #define AM33XX_IRQ_TPCC0_ERRINT_PO	14
+ + #define AM33XX_IRQ_WDT0			15
+ + #define AM33XX_IRQ_ADC_GEN		16
+ + #define AM33XX_IRQ_USBSS		17
+ + #define AM33XX_IRQ_USB0			18
+ + #define AM33XX_IRQ_USB1			19
+ + #define AM33XX_IRQ_ICSS0_0		20
+ + #define AM33XX_IRQ_ICSS0_1		21
+ + #define AM33XX_IRQ_ICSS0_2		22
+ + #define AM33XX_IRQ_ICSS0_3		23
+ + #define AM33XX_IRQ_ICSS0_4		24
+ + #define AM33XX_IRQ_ICSS0_5		25
+ + #define AM33XX_IRQ_ICSS0_6		26
+ + #define AM33XX_IRQ_ICSS0_7		27
+ + #define AM33XX_IRQ_MMCHS1		28
+ + #define AM33XX_IRQ_MMCHS2		29
+ + #define AM33XX_IRQ_MSHSI2COCP2		30
+ + #define AM33XX_IRQ_PWMSS0_ECAP		31
+ + #define AM33XX_IRQ_GPIO2_1		32
+ + #define AM33XX_IRQ_GPIO2_2		33
+ + #define AM33XX_IRQ_USB_P		34
+ + #define AM33XX_IRQ_PCI_SLV		35
+ + #define AM33XX_IRQ_LCD			36
+ + #define AM33XX_IRQ_THALIAIRQ		37
+ + #define AM33XX_IRQ_BB_2DHWA		38
+ + #define AM33XX_IRQ_PWMSS2_EPWM		39
+ + #define AM33XX_IRQ_CPSW_C0_RX		40
+ + #define AM33XX_IRQ_CPSW_RX		41
+ + #define AM33XX_IRQ_CPSW_TX		42
+ + #define AM33XX_IRQ_CPSW_C0		43
+ + #define AM33XX_IRQ_UART3		44
+ + #define AM33XX_IRQ_UART4		45
+ + #define AM33XX_IRQ_UART5		46
+ + #define AM33XX_IRQ_PWMSS1_ECAP		47
+ + #define AM33XX_IRQ_PCI0			48
+ + #define AM33XX_IRQ_PCI1			49
+ + #define AM33XX_IRQ_PCI2			50
+ + #define AM33XX_IRQ_PCI3			51
+ + #define AM33XX_IRQ_DCAN0_0		52
+ + #define AM33XX_IRQ_DCAN0_1		53
+ + #define AM33XX_IRQ_DCAN0_UERR		54
+ + #define AM33XX_IRQ_DCAN1_0		55
+ + #define AM33XX_IRQ_DCAN1_1		56
+ + #define AM33XX_IRQ_DCAN1_UERR		57
+ + #define AM33XX_IRQ_PWMSS0		58
+ + #define AM33XX_IRQ_PWMSS1		59
+ + #define AM33XX_IRQ_PWMSS2		60
+ + #define AM33XX_IRQ_PWMSS2_ECAP		61
+ + #define AM33XX_IRQ_GPIO3_1		62
+ + #define AM33XX_IRQ_GPIO3_2		63
+ + #define AM33XX_IRQ_MMCHS0		64
+ + #define AM33XX_IRQ_MCSPIOCP0		65
+ + #define AM33XX_IRQ_DMTIMER0		66
+ + #define AM33XX_IRQ_DMTIMER1		67
+ + #define AM33XX_IRQ_DMTIMER2		68
+ + #define AM33XX_IRQ_DMTIMER3		69
+ + #define AM33XX_IRQ_MSHSI2COCP0		70
+ + #define AM33XX_IRQ_MSHSI2COCP1		71
+ + #define AM33XX_IRQ_UART0		72
+ + #define AM33XX_IRQ_UART1		73
+ + #define AM33XX_IRQ_UART2		74
+ + #define AM33XX_IRQ_RTC_TIMER		75
+ + #define AM33XX_IRQ_RTC_ALARM		76
+ + #define AM33XX_IRQ_MAILBOX		77
+ + #define AM33XX_IRQ_M3_M3SP_TXEV		78
+ + #define AM33XX_IRQ_PWMSS0_EQEP		79
+ + #define AM33XX_IRQ_MCASP0_AX		80
+ + #define AM33XX_IRQ_MCASP0_AR		81
+ + #define AM33XX_IRQ_MCASP1_AX		82
+ + #define AM33XX_IRQ_MCASP1_AR		83
+ + #define AM33XX_IRQ_MCASP2_X		84
+ + #define AM33XX_IRQ_MCASP2_R		85
+ + #define AM33XX_IRQ_PWMSS0_EPWM		86
+ + #define AM33XX_IRQ_PWMSS1_EPWM		87
+ + #define AM33XX_IRQ_PWMSS1_EQEP		88
+ + #define AM33XX_IRQ_PWMSS2_EQEP		89
+ + #define AM33XX_IRQ_DMA			90
+ + #define AM33XX_IRQ_WDT1			91
+ + #define AM33XX_IRQ_DMTIMER4		92
+ + #define AM33XX_IRQ_DMTIMER5		93
+ + #define AM33XX_IRQ_DMTIMER6		94
+ + #define AM33XX_IRQ_DMTIMER7		95
+ + #define AM33XX_IRQ_GPIO0_1		96
+ + #define AM33XX_IRQ_GPIO0_2		97
+ + #define AM33XX_IRQ_GPIO1_1		98
+ + #define AM33XX_IRQ_GPIO1_2		99
+ + #define AM33XX_IRQ_GPMC0		100
+ + #define AM33XX_IRQ_EMI			101
+ + #define AM33XX_IRQ_AESEIP36t0_S		102
+ + #define AM33XX_IRQ_AESEIP36t0_P		103
+ + #define AM33XX_IRQ_AESEIP36t1_S		104
+ + #define AM33XX_IRQ_AESEIP36t1_P		105
+ + #define AM33XX_IRQ_DESEIP16t0_S		106
+ + #define AM33XX_IRQ_DESEIP16t0_P		107
+ + #define AM33XX_IRQ_SHAEIP57t0_S		108
+ + #define AM33XX_IRQ_SHAEIP57t0_P		109
+ + #define AM33XX_IRQ_PKAEIP29t0_S		110
+ + #define AM33XX_IRQ_RNGEIP75t0		111
+ + #define AM33XX_IRQ_TPTC0		112
+ + #define AM33XX_IRQ_TPTC1		113
+ + #define AM33XX_IRQ_TPTC2		114
+ + #define AM33XX_IRQ_TSC			115
+ + #define AM33XX_IRQ_SDMA0		116
+ + #define AM33XX_IRQ_SDMA1		117
+ + #define AM33XX_IRQ_SDMA2		118
+ + #define AM33XX_IRQ_SDMA3		119
+ + #define AM33XX_IRQ_SMARTREFLEX0		120
+ + #define AM33XX_IRQ_SMARTREFLEX1		121
+ + #define AM33XX_IRQ_NETRA_MMU		122
+ + #define AM33XX_IRQ_DMA0			123
+ + #define AM33XX_IRQ_DMA1			124
+ + #define AM33XX_IRQ_SPI1			125
+ + #define AM33XX_IRQ_SPI2			126
+ + #define AM33XX_IRQ_SPI			127
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/irqs.h linux-3.2.1/arch/arm/plat-ckb/include/plat/irqs.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/irqs.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/irqs.h	2014-11-25 14:03:37.981270000 +0900
+ ***************
+ *** 0 ****
+ --- 1,266 ----
+ + /*
+ +  *  arch/arm/plat-omap/include/mach/irqs.h
+ +  *
+ +  *  Copyright (C) Greg Lonnon 2001
+ +  *  Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
+ +  *
+ +  * Copyright (C) 2009 Texas Instruments
+ +  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; either version 2 of the License, or
+ +  * (at your option) any later version.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ +  *
+ +  * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610
+ +  *	 are different.
+ +  */
+ + 
+ + #ifndef __ASM_ARCH_OMAP15XX_IRQS_H
+ + #define __ASM_ARCH_OMAP15XX_IRQS_H
+ + 
+ + #include "irqs-33xx.h"
+ + 
+ + /*
+ +  * IRQ numbers for interrupt handler 1
+ +  *
+ +  * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
+ +  *
+ +  */
+ + #define INT_CAMERA		1
+ + #define INT_FIQ			3
+ + #define INT_RTDX		6
+ + #define INT_DSP_MMU_ABORT	7
+ + #define INT_HOST		8
+ + #define INT_ABORT		9
+ + #define INT_BRIDGE_PRIV		13
+ + #define INT_GPIO_BANK1		14
+ + #define INT_UART3		15
+ + #define INT_TIMER3		16
+ + #define INT_DMA_CH0_6		19
+ + #define INT_DMA_CH1_7		20
+ + #define INT_DMA_CH2_8		21
+ + #define INT_DMA_CH3		22
+ + #define INT_DMA_CH4		23
+ + #define INT_DMA_CH5		24
+ + #define INT_DMA_LCD		25
+ + #define INT_TIMER1		26
+ + #define INT_WD_TIMER		27
+ + #define INT_BRIDGE_PUB		28
+ + #define INT_TIMER2		30
+ + #define INT_LCD_CTRL		31
+ + 
+ + /*
+ +  * OMAP-1510 specific IRQ numbers for interrupt handler 1
+ +  */
+ + #define INT_1510_IH2_IRQ	0
+ + #define INT_1510_RES2		2
+ + #define INT_1510_SPI_TX		4
+ + #define INT_1510_SPI_RX		5
+ + #define INT_1510_DSP_MAILBOX1	10
+ + #define INT_1510_DSP_MAILBOX2	11
+ + #define INT_1510_RES12		12
+ + #define INT_1510_LB_MMU		17
+ + #define INT_1510_RES18		18
+ + #define INT_1510_LOCAL_BUS	29
+ + 
+ + 
+ + /*
+ +  * IRQ numbers for interrupt handler 2
+ +  *
+ +  * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
+ +  */
+ + #define IH2_BASE		32
+ + 
+ + #define INT_KEYBOARD		(1 + IH2_BASE)
+ + #define INT_uWireTX		(2 + IH2_BASE)
+ + #define INT_uWireRX		(3 + IH2_BASE)
+ + #define INT_I2C			(4 + IH2_BASE)
+ + #define INT_MPUIO		(5 + IH2_BASE)
+ + #define INT_USB_HHC_1		(6 + IH2_BASE)
+ + #define INT_McBSP3TX		(10 + IH2_BASE)
+ + #define INT_McBSP3RX		(11 + IH2_BASE)
+ + #define INT_McBSP1TX		(12 + IH2_BASE)
+ + #define INT_McBSP1RX		(13 + IH2_BASE)
+ + #define INT_UART1		(14 + IH2_BASE)
+ + #define INT_UART2		(15 + IH2_BASE)
+ + #define INT_BT_MCSI1TX		(16 + IH2_BASE)
+ + #define INT_BT_MCSI1RX		(17 + IH2_BASE)
+ + #define INT_SOSSI_MATCH		(19 + IH2_BASE)
+ + #define INT_USB_W2FC		(20 + IH2_BASE)
+ + #define INT_1WIRE		(21 + IH2_BASE)
+ + #define INT_OS_TIMER		(22 + IH2_BASE)
+ + #define INT_MMC			(23 + IH2_BASE)
+ + #define INT_GAUGE_32K		(24 + IH2_BASE)
+ + #define INT_RTC_TIMER		(25 + IH2_BASE)
+ + #define INT_RTC_ALARM		(26 + IH2_BASE)
+ + #define INT_MEM_STICK		(27 + IH2_BASE)
+ + 
+ + 
+ + #define INT_24XX_SYS_NIRQ	7
+ + #define INT_24XX_SDMA_IRQ0	12
+ + #define INT_24XX_SDMA_IRQ1	13
+ + #define INT_24XX_SDMA_IRQ2	14
+ + #define INT_24XX_SDMA_IRQ3	15
+ + #define INT_24XX_CAM_IRQ	24
+ + #define INT_24XX_DSS_IRQ	25
+ + #define INT_24XX_MAIL_U0_MPU	26
+ + #define INT_24XX_DSP_UMA	27
+ + #define INT_24XX_DSP_MMU	28
+ + #define INT_24XX_GPIO_BANK1	29
+ + #define INT_24XX_GPIO_BANK2	30
+ + #define INT_24XX_GPIO_BANK3	31
+ + #define INT_24XX_GPIO_BANK4	32
+ + #define INT_24XX_GPIO_BANK5	33
+ + #define INT_24XX_MAIL_U3_MPU	34
+ + #define INT_24XX_GPTIMER1	37
+ + #define INT_24XX_GPTIMER2	38
+ + #define INT_24XX_GPTIMER3	39
+ + #define INT_24XX_GPTIMER4	40
+ + #define INT_24XX_GPTIMER5	41
+ + #define INT_24XX_GPTIMER6	42
+ + #define INT_24XX_GPTIMER7	43
+ + #define INT_24XX_GPTIMER8	44
+ + #define INT_24XX_GPTIMER9	45
+ + #define INT_24XX_GPTIMER10	46
+ + #define INT_24XX_GPTIMER11	47
+ + #define INT_24XX_GPTIMER12	48
+ + #define INT_24XX_SHA1MD5	51
+ + #define INT_24XX_MCBSP4_IRQ_TX	54
+ + #define INT_24XX_MCBSP4_IRQ_RX	55
+ + #define INT_24XX_I2C1_IRQ	56
+ + #define INT_24XX_I2C2_IRQ	57
+ + #define INT_24XX_HDQ_IRQ	58
+ + #define INT_24XX_MCBSP1_IRQ_TX	59
+ + #define INT_24XX_MCBSP1_IRQ_RX	60
+ + #define INT_24XX_MCBSP2_IRQ_TX	62
+ + #define INT_24XX_MCBSP2_IRQ_RX	63
+ + #define INT_24XX_SPI1_IRQ	65
+ + #define INT_24XX_SPI2_IRQ	66
+ + #define INT_24XX_UART1_IRQ	72
+ + #define INT_24XX_UART2_IRQ	73
+ + #define INT_24XX_UART3_IRQ	74
+ + #define INT_24XX_USB_IRQ_GEN	75
+ + #define INT_24XX_USB_IRQ_NISO	76
+ + #define INT_24XX_USB_IRQ_ISO	77
+ + #define INT_24XX_USB_IRQ_HGEN	78
+ + #define INT_24XX_USB_IRQ_HSOF	79
+ + #define INT_24XX_USB_IRQ_OTG	80
+ + #define INT_24XX_MCBSP5_IRQ_TX	81
+ + #define INT_24XX_MCBSP5_IRQ_RX	82
+ + #define INT_24XX_MMC_IRQ	83
+ + #define INT_24XX_MMC2_IRQ	86
+ + #define INT_24XX_MCBSP3_IRQ_TX	89
+ + #define INT_24XX_MCBSP3_IRQ_RX	90
+ + #define INT_24XX_SPI3_IRQ	91
+ + 
+ + #define INT_243X_MCBSP2_IRQ	16
+ + #define INT_243X_MCBSP3_IRQ	17
+ + #define INT_243X_MCBSP4_IRQ	18
+ + #define INT_243X_MCBSP5_IRQ	19
+ + #define INT_243X_MCBSP1_IRQ	64
+ + #define INT_243X_HS_USB_MC	92
+ + #define INT_243X_HS_USB_DMA	93
+ + #define INT_243X_CARKIT_IRQ	94
+ + 
+ + #define INT_34XX_BENCH_MPU_EMUL	3
+ + #define INT_34XX_ST_MCBSP2_IRQ	4
+ + #define INT_34XX_ST_MCBSP3_IRQ	5
+ + #define INT_34XX_SSM_ABORT_IRQ	6
+ + #define INT_34XX_SYS_NIRQ	7
+ + #define INT_34XX_D2D_FW_IRQ	8
+ + #define INT_34XX_L3_DBG_IRQ     9
+ + #define INT_34XX_L3_APP_IRQ     10
+ + #define INT_34XX_PRCM_MPU_IRQ	11
+ + #define INT_34XX_MCBSP1_IRQ	16
+ + #define INT_34XX_MCBSP2_IRQ	17
+ + #define INT_34XX_GPMC_IRQ	20
+ + #define INT_34XX_MCBSP3_IRQ	22
+ + #define INT_34XX_MCBSP4_IRQ	23
+ + #define INT_34XX_CAM_IRQ	24
+ + #define INT_34XX_MCBSP5_IRQ	27
+ + #define INT_34XX_GPIO_BANK1	29
+ + #define INT_34XX_GPIO_BANK2	30
+ + #define INT_34XX_GPIO_BANK3	31
+ + #define INT_34XX_GPIO_BANK4	32
+ + #define INT_34XX_GPIO_BANK5	33
+ + #define INT_34XX_GPIO_BANK6	34
+ + #define INT_34XX_USIM_IRQ	35
+ + #define INT_34XX_WDT3_IRQ	36
+ + #define INT_34XX_SPI4_IRQ	48
+ + #define INT_34XX_SHA1MD52_IRQ	49
+ + #define INT_34XX_FPKA_READY_IRQ	50
+ + #define INT_34XX_SHA1MD51_IRQ	51
+ + #define INT_34XX_RNG_IRQ	52
+ + #define INT_34XX_I2C3_IRQ	61
+ + #define INT_34XX_FPKA_ERROR_IRQ	64
+ + #define INT_34XX_PBIAS_IRQ	75
+ + #define INT_34XX_OHCI_IRQ	76
+ + #define INT_34XX_EHCI_IRQ	77
+ + #define INT_34XX_TLL_IRQ	78
+ + #define INT_34XX_PARTHASH_IRQ	79
+ + #define INT_34XX_MMC3_IRQ	94
+ + #define INT_34XX_GPT12_IRQ	95
+ + 
+ + #define INT_36XX_UART4_IRQ	80
+ + 
+ + #define INT_35XX_HECC0_IRQ		24
+ + #define INT_35XX_HECC1_IRQ		28
+ + #define INT_35XX_EMAC_C0_RXTHRESH_IRQ	67
+ + #define INT_35XX_EMAC_C0_RX_PULSE_IRQ	68
+ + #define INT_35XX_EMAC_C0_TX_PULSE_IRQ	69
+ + #define INT_35XX_EMAC_C0_MISC_PULSE_IRQ	70
+ + #define INT_35XX_USBOTG_IRQ		71
+ + #define INT_35XX_UART4_IRQ		84
+ + #define INT_35XX_CCDC_VD0_IRQ		88
+ + #define INT_35XX_CCDC_VD1_IRQ		92
+ + #define INT_35XX_CCDC_VD2_IRQ		93
+ + 
+ + /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
+ +  * 16 MPUIO lines */
+ + #define OMAP_MAX_GPIO_LINES	192
+ + #define IH_GPIO_BASE		(128 + IH2_BASE)
+ + #define IH_MPUIO_BASE		(OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
+ + #define OMAP_IRQ_END		(IH_MPUIO_BASE + 16)
+ + 
+ + /* External FPGA handles interrupts on Innovator boards */
+ + #define	OMAP_FPGA_IRQ_BASE	(OMAP_IRQ_END)
+ + #ifdef	CONFIG_MACH_OMAP_INNOVATOR
+ + #define OMAP_FPGA_NR_IRQS	24
+ + #else
+ + #define OMAP_FPGA_NR_IRQS	0
+ + #endif
+ + #define OMAP_FPGA_IRQ_END	(OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
+ + 
+ + /* GPMC related */
+ + #define OMAP_GPMC_IRQ_BASE	(OMAP_FPGA_IRQ_END)
+ + #define OMAP_GPMC_NR_IRQS	8
+ + #define OMAP_GPMC_IRQ_END	(OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS)
+ + 
+ + 
+ + #define NR_IRQS			OMAP_GPMC_IRQ_END
+ + 
+ + #define OMAP_IRQ_BIT(irq)	(1 << ((irq) % 32))
+ + 
+ + /*
+ +  * Max from AM33XX device
+ +  */
+ + #define INTCPS_MAX_NR_REGS_REQ	4
+ + #define INTCPS_MAX_NR_IRQS	128
+ + 
+ + #include <mach/hardware.h>
+ + 
+ + #ifdef CONFIG_FIQ
+ + #define FIQ_START		1024
+ + #endif
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/l3_2xxx.h linux-3.2.1/arch/arm/plat-ckb/include/plat/l3_2xxx.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/l3_2xxx.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/l3_2xxx.h	2014-11-25 13:19:15.175994805 +0900
+ ***************
+ *** 0 ****
+ --- 1,20 ----
+ + /*
+ +  * arch/arm/plat-omap/include/plat/l3_2xxx.h - L3 firewall definitions
+ +  *
+ +  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ +  *	Sumit Semwal
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; either version 2 of the License, or
+ +  * (at your option) any later version.
+ +  *
+ +  */
+ + #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H
+ + #define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H
+ + 
+ + /* L3 CONNIDs */
+ + /* Display Sub system (DSS) */
+ + #define OMAP2_L3_CORE_FW_CONNID_DSS			8
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/l3_3xxx.h linux-3.2.1/arch/arm/plat-ckb/include/plat/l3_3xxx.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/l3_3xxx.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/l3_3xxx.h	2014-11-25 13:19:15.175994805 +0900
+ ***************
+ *** 0 ****
+ --- 1,20 ----
+ + /*
+ +  * arch/arm/plat-omap/include/plat/l3_3xxx.h - L3 firewall definitions
+ +  *
+ +  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ +  *	Sumit Semwal
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; either version 2 of the License, or
+ +  * (at your option) any later version.
+ +  *
+ +  */
+ + #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_3XXX_H
+ + #define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_3XXX_H
+ + 
+ + /* L3 Initiator IDs */
+ + /* Display Sub system (DSS) */
+ + #define OMAP3_L3_CORE_FW_INIT_ID_DSS			29
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/lcdc.h linux-3.2.1/arch/arm/plat-ckb/include/plat/lcdc.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/lcdc.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/lcdc.h	2014-11-25 13:19:15.175994805 +0900
+ ***************
+ *** 0 ****
+ --- 1,21 ----
+ + /*
+ +  * Header file for LCD controller
+ +  *
+ +  * Copyright (C) {2011} Texas Instruments Incorporated - http://www.ti.com/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ +  * GNU General Public License for more details.
+ +  **/
+ + 
+ + #ifndef __OMAP2_LCDC_H
+ + #define __OMAP2_LCDC_H
+ + 
+ + struct platform_device *am33xx_register_lcdc(
+ + 		struct da8xx_lcdc_platform_data *pdata);
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/led.h linux-3.2.1/arch/arm/plat-ckb/include/plat/led.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/led.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/led.h	2014-11-25 13:19:15.180012766 +0900
+ ***************
+ *** 0 ****
+ --- 1,24 ----
+ + /*
+ +  *  arch/arm/plat-omap/include/mach/led.h
+ +  *
+ +  *  Copyright (C) 2006 Samsung Electronics
+ +  *  Kyungmin Park <kyungmin.park@samsung.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + #ifndef ASMARM_ARCH_LED_H
+ + #define ASMARM_ARCH_LED_H
+ + 
+ + struct omap_led_config {
+ + 	struct led_classdev	cdev;
+ + 	s16			gpio;
+ + };
+ + 
+ + struct omap_led_platform_data {
+ + 	s16			nr_leds;
+ + 	struct omap_led_config	*leds;
+ + };
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/mailbox.h linux-3.2.1/arch/arm/plat-ckb/include/plat/mailbox.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/mailbox.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/mailbox.h	2014-11-25 13:19:15.180012766 +0900
+ ***************
+ *** 0 ****
+ --- 1,108 ----
+ + /* mailbox.h */
+ + 
+ + #ifndef MAILBOX_H
+ + #define MAILBOX_H
+ + 
+ + #include <linux/spinlock.h>
+ + #include <linux/workqueue.h>
+ + #include <linux/interrupt.h>
+ + #include <linux/device.h>
+ + #include <linux/kfifo.h>
+ + 
+ + typedef u32 mbox_msg_t;
+ + struct omap_mbox;
+ + 
+ + typedef int __bitwise omap_mbox_irq_t;
+ + #define IRQ_TX ((__force omap_mbox_irq_t) 1)
+ + #define IRQ_RX ((__force omap_mbox_irq_t) 2)
+ + 
+ + typedef int __bitwise omap_mbox_type_t;
+ + #define OMAP_MBOX_TYPE1 ((__force omap_mbox_type_t) 1)
+ + #define OMAP_MBOX_TYPE2 ((__force omap_mbox_type_t) 2)
+ + 
+ + struct omap_mbox_ops {
+ + 	omap_mbox_type_t	type;
+ + 	int		(*startup)(struct omap_mbox *mbox);
+ + 	void		(*shutdown)(struct omap_mbox *mbox);
+ + 	/* fifo */
+ + 	mbox_msg_t	(*fifo_read)(struct omap_mbox *mbox);
+ + 	void		(*fifo_write)(struct omap_mbox *mbox, mbox_msg_t msg);
+ + 	int		(*fifo_empty)(struct omap_mbox *mbox);
+ + 	int		(*fifo_full)(struct omap_mbox *mbox);
+ + 	int		(*fifo_needs_flush)(struct omap_mbox *mbox);
+ + 	mbox_msg_t	(*fifo_readback)(struct omap_mbox *mbox);
+ + 	/* irq */
+ + 	void		(*enable_irq)(struct omap_mbox *mbox,
+ + 						omap_mbox_irq_t irq);
+ + 	void		(*disable_irq)(struct omap_mbox *mbox,
+ + 						omap_mbox_irq_t irq);
+ + 	void		(*ack_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
+ + 	int		(*is_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
+ + 	/* ctx */
+ + 	void		(*save_ctx)(struct omap_mbox *mbox);
+ + 	void		(*restore_ctx)(struct omap_mbox *mbox);
+ + };
+ + 
+ + struct omap_mbox_queue {
+ + 	spinlock_t		lock;
+ + 	struct kfifo		fifo;
+ + 	struct work_struct	work;
+ + 	struct tasklet_struct	tasklet;
+ + 	struct omap_mbox	*mbox;
+ + 	bool full;
+ + };
+ + 
+ + struct omap_mbox {
+ + 	char			*name;
+ + 	unsigned int		irq;
+ + 	struct omap_mbox_queue	*txq, *rxq;
+ + 	struct omap_mbox_ops	*ops;
+ + 	struct device		*dev;
+ + 	void			*priv;
+ + 	int			use_count;
+ + 	struct blocking_notifier_head   notifier;
+ + };
+ + 
+ + int omap_mbox_msg_rx_flush(struct omap_mbox *mbox);
+ + int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg);
+ + void omap_mbox_init_seq(struct omap_mbox *);
+ + 
+ + struct omap_mbox *omap_mbox_get(const char *, struct notifier_block *nb);
+ + void omap_mbox_put(struct omap_mbox *mbox, struct notifier_block *nb);
+ + 
+ + int omap_mbox_register(struct device *parent, struct omap_mbox **);
+ + int omap_mbox_unregister(void);
+ + 
+ + static inline void omap_mbox_save_ctx(struct omap_mbox *mbox)
+ + {
+ + 	if (!mbox->ops->save_ctx) {
+ + 		dev_err(mbox->dev, "%s:\tno save\n", __func__);
+ + 		return;
+ + 	}
+ + 
+ + 	mbox->ops->save_ctx(mbox);
+ + }
+ + 
+ + static inline void omap_mbox_restore_ctx(struct omap_mbox *mbox)
+ + {
+ + 	if (!mbox->ops->restore_ctx) {
+ + 		dev_err(mbox->dev, "%s:\tno restore\n", __func__);
+ + 		return;
+ + 	}
+ + 
+ + 	mbox->ops->restore_ctx(mbox);
+ + }
+ + 
+ + static inline void omap_mbox_enable_irq(struct omap_mbox *mbox,
+ + 					omap_mbox_irq_t irq)
+ + {
+ + 	mbox->ops->enable_irq(mbox, irq);
+ + }
+ + 
+ + static inline void omap_mbox_disable_irq(struct omap_mbox *mbox,
+ + 					 omap_mbox_irq_t irq)
+ + {
+ + 	mbox->ops->disable_irq(mbox, irq);
+ + }
+ + 
+ + #endif /* MAILBOX_H */
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/mcspi.h linux-3.2.1/arch/arm/plat-ckb/include/plat/mcspi.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/mcspi.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/mcspi.h	2014-11-25 13:19:15.180012766 +0900
+ ***************
+ *** 0 ****
+ --- 1,23 ----
+ + #ifndef _OMAP2_MCSPI_H
+ + #define _OMAP2_MCSPI_H
+ + 
+ + #define OMAP2_MCSPI_REV 0
+ + #define OMAP3_MCSPI_REV 1
+ + #define OMAP4_MCSPI_REV 2
+ + 
+ + #define OMAP4_MCSPI_REG_OFFSET 0x100
+ + 
+ + struct omap2_mcspi_platform_config {
+ + 	unsigned short	num_cs;
+ + 	unsigned int regs_offset;
+ + };
+ + 
+ + struct omap2_mcspi_dev_attr {
+ + 	unsigned short num_chipselect;
+ + };
+ + 
+ + struct omap2_mcspi_device_config {
+ + 	unsigned turbo_mode:1;
+ + };
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/mmc.h linux-3.2.1/arch/arm/plat-ckb/include/plat/mmc.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/mmc.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/mmc.h	2014-11-25 13:19:15.180012766 +0900
+ ***************
+ *** 0 ****
+ --- 1,208 ----
+ + /*
+ +  * MMC definitions for OMAP2
+ +  *
+ +  * Copyright (C) 2006 Nokia Corporation
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #ifndef __OMAP2_MMC_H
+ + #define __OMAP2_MMC_H
+ + 
+ + #include <linux/types.h>
+ + #include <linux/device.h>
+ + #include <linux/mmc/host.h>
+ + 
+ + #include <plat/board.h>
+ + 
+ + #define OMAP15XX_NR_MMC		1
+ + #define OMAP16XX_NR_MMC		2
+ + #define OMAP1_MMC_SIZE		0x080
+ + #define OMAP1_MMC1_BASE		0xfffb7800
+ + #define OMAP1_MMC2_BASE		0xfffb7c00	/* omap16xx only */
+ + 
+ + #define OMAP24XX_NR_MMC		2
+ + #define OMAP2420_MMC_SIZE	OMAP1_MMC_SIZE
+ + #define OMAP2_MMC1_BASE		0x4809c000
+ + 
+ + #define OMAP4_MMC_REG_OFFSET	0x100
+ + 
+ + #define OMAP_MMC_MAX_SLOTS	2
+ + 
+ + /*
+ +  * struct omap_mmc_dev_attr.flags possibilities
+ +  *
+ +  * OMAP_HSMMC_SUPPORTS_DUAL_VOLT: Some HSMMC controller instances can
+ +  *    operate with either 1.8Vdc or 3.0Vdc card voltages; this flag
+ +  *    should be set if this is the case.  See for example Section 22.5.3
+ +  *    "MMC/SD/SDIO1 Bus Voltage Selection" of the OMAP34xx Multimedia
+ +  *    Device Silicon Revision 3.1.x Revision ZR (July 2011) (SWPU223R).
+ +  *
+ +  * OMAP_HSMMC_BROKEN_MULTIBLOCK_READ: Multiple-block read transfers
+ +  *    don't work correctly on some MMC controller instances on some
+ +  *    OMAP3 SoCs; this flag should be set if this is the case.  See
+ +  *    for example Advisory 2.1.1.128 "MMC: Multiple Block Read
+ +  *    Operation Issue" in _OMAP3530/3525/3515/3503 Silicon Errata_
+ +  *    Revision F (October 2010) (SPRZ278F).
+ +  */
+ + #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT		BIT(0)
+ + #define OMAP_HSMMC_BROKEN_MULTIBLOCK_READ	BIT(1)
+ + 
+ + enum {
+ + 	MMC_CTRL_VERSION_1 = 0, /* OMAP class devicess */
+ + 	MMC_CTRL_VERSION_2	/* AM33XX class devices */
+ + };
+ + 
+ + struct omap_mmc_dev_attr {
+ + 	u8 flags;
+ + };
+ + 
+ + struct omap_mmc_platform_data {
+ + 	/* back-link to device */
+ + 	struct device *dev;
+ + 
+ + 	/* number of slots per controller */
+ + 	unsigned nr_slots:2;
+ + 
+ + 	/* set if your board has components or wiring that limits the
+ + 	 * maximum frequency on the MMC bus */
+ + 	unsigned int max_freq;
+ + 
+ + 	/* switch the bus to a new slot */
+ + 	int (*switch_slot)(struct device *dev, int slot);
+ + 	/* initialize board-specific MMC functionality, can be NULL if
+ + 	 * not supported */
+ + 	int (*init)(struct device *dev);
+ + 	void (*cleanup)(struct device *dev);
+ + 	void (*shutdown)(struct device *dev);
+ + 
+ + 	/* To handle board related suspend/resume functionality for MMC */
+ + 	int (*suspend)(struct device *dev, int slot);
+ + 	int (*resume)(struct device *dev, int slot);
+ + 
+ + 	/* Return context loss count due to PM states changing */
+ + 	int (*get_context_loss_count)(struct device *dev);
+ + 
+ + 	u64 dma_mask;
+ + 
+ + 	/* Integrating attributes from the omap_hwmod layer */
+ + 	u8 controller_flags;
+ + 
+ + 	/* Register offset deviation */
+ + 	u16 reg_offset;
+ + 
+ + 	struct omap_mmc_slot_data {
+ + 
+ + 		/*
+ + 		 * 4/8 wires and any additional host capabilities
+ + 		 * need to OR'd all capabilities (ref. linux/mmc/host.h)
+ + 		 */
+ + 		u8  wires;	/* Used for the MMC driver on omap1 and 2420 */
+ + 		u32 caps;	/* Used for the MMC driver on 2430 and later */
+ + 		u32 pm_caps;	/* PM capabilities of the mmc */
+ + 
+ + 		/*
+ + 		 * nomux means "standard" muxing is wrong on this board, and
+ + 		 * that board-specific code handled it before common init logic.
+ + 		 */
+ + 		unsigned nomux:1;
+ + 
+ + 		/* switch pin can be for card detect (default) or card cover */
+ + 		unsigned cover:1;
+ + 
+ + 		/* use the internal clock */
+ + 		unsigned internal_clock:1;
+ + 
+ + 		/* nonremovable e.g. eMMC */
+ + 		unsigned nonremovable:1;
+ + 
+ + 		/* Try to sleep or power off when possible */
+ + 		unsigned power_saving:1;
+ + 
+ + 		/* If using power_saving and the MMC power is not to go off */
+ + 		unsigned no_off:1;
+ + 
+ + 		/* eMMC does not handle power off when not in sleep state */
+ + 		unsigned no_regulator_off_init:1;
+ + 
+ + 		/* Regulator off remapped to sleep */
+ + 		unsigned vcc_aux_disable_is_sleep:1;
+ + 
+ + 		/* we can put the features above into this variable */
+ + #define HSMMC_HAS_PBIAS		(1 << 0)
+ + #define HSMMC_HAS_UPDATED_RESET	(1 << 1)
+ + 		unsigned features;
+ + 
+ + 		int switch_pin;			/* gpio (card detect) */
+ + 		int gpio_wp;			/* gpio (write protect) */
+ + 
+ + 		int (*set_bus_mode)(struct device *dev, int slot, int bus_mode);
+ + 		int (*set_power)(struct device *dev, int slot,
+ + 				 int power_on, int vdd);
+ + 		int (*get_ro)(struct device *dev, int slot);
+ + 		int (*set_sleep)(struct device *dev, int slot, int sleep,
+ + 				 int vdd, int cardsleep);
+ + 		void (*remux)(struct device *dev, int slot, int power_on);
+ + 		/* Call back before enabling / disabling regulators */
+ + 		void (*before_set_reg)(struct device *dev, int slot,
+ + 				       int power_on, int vdd);
+ + 		/* Call back after enabling / disabling regulators */
+ + 		void (*after_set_reg)(struct device *dev, int slot,
+ + 				      int power_on, int vdd);
+ + 		/* if we have special card, init it using this callback */
+ + 		void (*init_card)(struct mmc_card *card);
+ + 
+ + 		/* return MMC cover switch state, can be NULL if not supported.
+ + 		 *
+ + 		 * possible return values:
+ + 		 *   0 - closed
+ + 		 *   1 - open
+ + 		 */
+ + 		int (*get_cover_state)(struct device *dev, int slot);
+ + 
+ + 		const char *name;
+ + 		u32 ocr_mask;
+ + 
+ + 		/* Card detection IRQs */
+ + 		int card_detect_irq;
+ + 		int (*card_detect)(struct device *dev, int slot);
+ + 
+ + 		unsigned int ban_openended:1;
+ + 
+ + 	} slots[OMAP_MMC_MAX_SLOTS];
+ + 
+ + 	u8 version;
+ + 	
+ + };
+ + 
+ + /* called from board-specific card detection service routine */
+ + extern void omap_mmc_notify_cover_event(struct device *dev, int slot,
+ + 					int is_closed);
+ + 
+ + #if	defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
+ + 	defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
+ + void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
+ + 				int nr_controllers);
+ + void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data);
+ + int omap_mmc_add(const char *name, int id, unsigned long base,
+ + 				unsigned long size, unsigned int irq,
+ + 				struct omap_mmc_platform_data *data);
+ + #else
+ + static inline void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
+ + 				int nr_controllers)
+ + {
+ + }
+ + static inline void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
+ + {
+ + }
+ + static inline int omap_mmc_add(const char *name, int id, unsigned long base,
+ + 				unsigned long size, unsigned int irq,
+ + 				struct omap_mmc_platform_data *data)
+ + {
+ + 	return 0;
+ + }
+ + 
+ + #endif
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/multi.h linux-3.2.1/arch/arm/plat-ckb/include/plat/multi.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/multi.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/multi.h	2014-11-25 13:19:15.180012766 +0900
+ ***************
+ *** 0 ****
+ --- 1,42 ----
+ + /*
+ +  * Support for compiling in multiple OMAP processors
+ +  *
+ +  * Copyright (C) 2010 Nokia Corporation
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; either version 2 of the License, or
+ +  * (at your option) any later version.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ +  *
+ +  */
+ + 
+ + #ifndef __PLAT_OMAP_MULTI_H
+ + #define __PLAT_OMAP_MULTI_H
+ + 
+ + /*
+ +  * Test if multicore OMAP support is needed
+ +  */
+ + #undef MULTI_OMAP1
+ + #undef MULTI_OMAP2
+ + #undef OMAP_NAME
+ + 
+ + # if (defined(OMAP_NAME) || defined(MULTI_OMAP1))
+ + #  error "OMAP1 and OMAP2PLUS can't be selected at the same time"
+ + # endif
+ + # ifdef OMAP_NAME
+ + #  undef  MULTI_OMAP2
+ + #  define MULTI_OMAP2
+ + # else
+ + #  define OMAP_NAME omap3
+ + # endif
+ + 
+ + #endif	/* __PLAT_OMAP_MULTI_H */
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/mux.h linux-3.2.1/arch/arm/plat-ckb/include/plat/mux.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/mux.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/mux.h	2014-11-25 13:19:15.180012766 +0900
+ ***************
+ *** 0 ****
+ --- 1,451 ----
+ + /*
+ +  * arch/arm/plat-omap/include/mach/mux.h
+ +  *
+ +  * Table of the Omap register configurations for the FUNC_MUX and
+ +  * PULL_DWN combinations.
+ +  *
+ +  * Copyright (C) 2004 - 2008 Texas Instruments Inc.
+ +  * Copyright (C) 2003 - 2008 Nokia Corporation
+ +  *
+ +  * Written by Tony Lindgren
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; either version 2 of the License, or
+ +  * (at your option) any later version.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ +  *
+ +  * NOTE: Please use the following naming style for new pin entries.
+ +  *	 For example, W8_1610_MMC2_DAT0, where:
+ +  *	 - W8	     = ball
+ +  *	 - 1610	     = 1510 or 1610, none if common for both 1510 and 1610
+ +  *	 - MMC2_DAT0 = function
+ +  */
+ + 
+ + #ifndef __ASM_ARCH_MUX_H
+ + #define __ASM_ARCH_MUX_H
+ + 
+ + #define PU_PD_SEL_NA		0	/* No pu_pd reg available */
+ + #define PULL_DWN_CTRL_NA	0	/* No pull-down control needed */
+ + 
+ + #ifdef	CONFIG_OMAP_MUX_DEBUG
+ + #define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \
+ + 					.mux_reg = FUNC_MUX_CTRL_##reg, \
+ + 					.mask_offset = mode_offset, \
+ + 					.mask = mode,
+ + 
+ + #define PULL_REG(reg, bit, status)	.pull_name = "PULL_DWN_CTRL_"#reg, \
+ + 					.pull_reg = PULL_DWN_CTRL_##reg, \
+ + 					.pull_bit = bit, \
+ + 					.pull_val = status,
+ + 
+ + #define PU_PD_REG(reg, status)		.pu_pd_name = "PU_PD_SEL_"#reg, \
+ + 					.pu_pd_reg = PU_PD_SEL_##reg, \
+ + 					.pu_pd_val = status,
+ + 
+ + #define MUX_REG_7XX(reg, mode_offset, mode) .mux_reg_name = "OMAP7XX_IO_CONF_"#reg, \
+ + 					.mux_reg = OMAP7XX_IO_CONF_##reg, \
+ + 					.mask_offset = mode_offset, \
+ + 					.mask = mode,
+ + 
+ + #define PULL_REG_7XX(reg, bit, status)	.pull_name = "OMAP7XX_IO_CONF_"#reg, \
+ + 					.pull_reg = OMAP7XX_IO_CONF_##reg, \
+ + 					.pull_bit = bit, \
+ + 					.pull_val = status,
+ + 
+ + #else
+ + 
+ + #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
+ + 					.mask_offset = mode_offset, \
+ + 					.mask = mode,
+ + 
+ + #define PULL_REG(reg, bit, status)	.pull_reg = PULL_DWN_CTRL_##reg, \
+ + 					.pull_bit = bit, \
+ + 					.pull_val = status,
+ + 
+ + #define PU_PD_REG(reg, status)		.pu_pd_reg = PU_PD_SEL_##reg, \
+ + 					.pu_pd_val = status,
+ + 
+ + #define MUX_REG_7XX(reg, mode_offset, mode) \
+ + 					.mux_reg = OMAP7XX_IO_CONF_##reg, \
+ + 					.mask_offset = mode_offset, \
+ + 					.mask = mode,
+ + 
+ + #define PULL_REG_7XX(reg, bit, status)	.pull_reg = OMAP7XX_IO_CONF_##reg, \
+ + 					.pull_bit = bit, \
+ + 					.pull_val = status,
+ + 
+ + #endif /* CONFIG_OMAP_MUX_DEBUG */
+ + 
+ + #define MUX_CFG(desc, mux_reg, mode_offset, mode,	\
+ + 		pull_reg, pull_bit, pull_status,	\
+ + 		pu_pd_reg, pu_pd_status, debug_status)	\
+ + {							\
+ + 	.name =	 desc,					\
+ + 	.debug = debug_status,				\
+ + 	MUX_REG(mux_reg, mode_offset, mode)		\
+ + 	PULL_REG(pull_reg, pull_bit, pull_status)	\
+ + 	PU_PD_REG(pu_pd_reg, pu_pd_status)		\
+ + },
+ + 
+ + 
+ + /*
+ +  * OMAP730/850 has a slightly different config for the pin mux.
+ +  * - config regs are the OMAP7XX_IO_CONF_x regs (see omap730.h) regs and
+ +  *   not the FUNC_MUX_CTRL_x regs from hardware.h
+ +  * - for pull-up/down, only has one enable bit which is is in the same register
+ +  *   as mux config
+ +  */
+ + #define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode,	\
+ + 		   pull_bit, pull_status, debug_status)\
+ + {							\
+ + 	.name =	 desc,					\
+ + 	.debug = debug_status,				\
+ + 	MUX_REG_7XX(mux_reg, mode_offset, mode)		\
+ + 	PULL_REG_7XX(mux_reg, pull_bit, pull_status)	\
+ + 	PU_PD_REG(NA, 0)		\
+ + },
+ + 
+ + struct pin_config {
+ + 	char 			*name;
+ + 	const unsigned int 	mux_reg;
+ + 	unsigned char		debug;
+ + 
+ + 	const unsigned char mask_offset;
+ + 	const unsigned char mask;
+ + 
+ + 	const char *pull_name;
+ + 	const unsigned int pull_reg;
+ + 	const unsigned char pull_val;
+ + 	const unsigned char pull_bit;
+ + 
+ + 	const char *pu_pd_name;
+ + 	const unsigned int pu_pd_reg;
+ + 	const unsigned char pu_pd_val;
+ + 
+ + #if	defined(CONFIG_OMAP_MUX_DEBUG)
+ + 	const char *mux_reg_name;
+ + #endif
+ + 
+ + };
+ + 
+ + enum omap7xx_index {
+ + 	/* OMAP 730 keyboard */
+ + 	E2_7XX_KBR0,
+ + 	J7_7XX_KBR1,
+ + 	E1_7XX_KBR2,
+ + 	F3_7XX_KBR3,
+ + 	D2_7XX_KBR4,
+ + 	C2_7XX_KBC0,
+ + 	D3_7XX_KBC1,
+ + 	E4_7XX_KBC2,
+ + 	F4_7XX_KBC3,
+ + 	E3_7XX_KBC4,
+ + 
+ + 	/* USB */
+ + 	AA17_7XX_USB_DM,
+ + 	W16_7XX_USB_PU_EN,
+ + 	W17_7XX_USB_VBUSI,
+ + 	W18_7XX_USB_DMCK_OUT,
+ + 	W19_7XX_USB_DCRST,
+ + 
+ + 	/* MMC */
+ + 	MMC_7XX_CMD,
+ + 	MMC_7XX_CLK,
+ + 	MMC_7XX_DAT0,
+ + 
+ + 	/* I2C */
+ + 	I2C_7XX_SCL,
+ + 	I2C_7XX_SDA,
+ + 
+ + 	/* SPI */
+ + 	SPI_7XX_1,
+ + 	SPI_7XX_2,
+ + 	SPI_7XX_3,
+ + 	SPI_7XX_4,
+ + 	SPI_7XX_5,
+ + 	SPI_7XX_6,
+ + 
+ + 	/* UART */
+ + 	UART_7XX_1,
+ + 	UART_7XX_2,
+ + };
+ + 
+ + enum omap1xxx_index {
+ + 	/* UART1 (BT_UART_GATING)*/
+ + 	UART1_TX = 0,
+ + 	UART1_RTS,
+ + 
+ + 	/* UART2 (COM_UART_GATING)*/
+ + 	UART2_TX,
+ + 	UART2_RX,
+ + 	UART2_CTS,
+ + 	UART2_RTS,
+ + 
+ + 	/* UART3 (GIGA_UART_GATING) */
+ + 	UART3_TX,
+ + 	UART3_RX,
+ + 	UART3_CTS,
+ + 	UART3_RTS,
+ + 	UART3_CLKREQ,
+ + 	UART3_BCLK,	/* 12MHz clock out */
+ + 	Y15_1610_UART3_RTS,
+ + 
+ + 	/* PWT & PWL */
+ + 	PWT,
+ + 	PWL,
+ + 
+ + 	/* USB master generic */
+ + 	R18_USB_VBUS,
+ + 	R18_1510_USB_GPIO0,
+ + 	W4_USB_PUEN,
+ + 	W4_USB_CLKO,
+ + 	W4_USB_HIGHZ,
+ + 	W4_GPIO58,
+ + 
+ + 	/* USB1 master */
+ + 	USB1_SUSP,
+ + 	USB1_SEO,
+ + 	W13_1610_USB1_SE0,
+ + 	USB1_TXEN,
+ + 	USB1_TXD,
+ + 	USB1_VP,
+ + 	USB1_VM,
+ + 	USB1_RCV,
+ + 	USB1_SPEED,
+ + 	R13_1610_USB1_SPEED,
+ + 	R13_1710_USB1_SE0,
+ + 
+ + 	/* USB2 master */
+ + 	USB2_SUSP,
+ + 	USB2_VP,
+ + 	USB2_TXEN,
+ + 	USB2_VM,
+ + 	USB2_RCV,
+ + 	USB2_SEO,
+ + 	USB2_TXD,
+ + 
+ + 	/* OMAP-1510 GPIO */
+ + 	R18_1510_GPIO0,
+ + 	R19_1510_GPIO1,
+ + 	M14_1510_GPIO2,
+ + 
+ + 	/* OMAP1610 GPIO */
+ + 	P18_1610_GPIO3,
+ + 	Y15_1610_GPIO17,
+ + 
+ + 	/* OMAP-1710 GPIO */
+ + 	R18_1710_GPIO0,
+ + 	V2_1710_GPIO10,
+ + 	N21_1710_GPIO14,
+ + 	W15_1710_GPIO40,
+ + 
+ + 	/* MPUIO */
+ + 	MPUIO2,
+ + 	N15_1610_MPUIO2,
+ + 	MPUIO4,
+ + 	MPUIO5,
+ + 	T20_1610_MPUIO5,
+ + 	W11_1610_MPUIO6,
+ + 	V10_1610_MPUIO7,
+ + 	W11_1610_MPUIO9,
+ + 	V10_1610_MPUIO10,
+ + 	W10_1610_MPUIO11,
+ + 	E20_1610_MPUIO13,
+ + 	U20_1610_MPUIO14,
+ + 	E19_1610_MPUIO15,
+ + 
+ + 	/* MCBSP2 */
+ + 	MCBSP2_CLKR,
+ + 	MCBSP2_CLKX,
+ + 	MCBSP2_DR,
+ + 	MCBSP2_DX,
+ + 	MCBSP2_FSR,
+ + 	MCBSP2_FSX,
+ + 
+ + 	/* MCBSP3 */
+ + 	MCBSP3_CLKX,
+ + 
+ + 	/* Misc ballouts */
+ + 	BALLOUT_V8_ARMIO3,
+ + 	N20_HDQ,
+ + 
+ + 	/* OMAP-1610 MMC2 */
+ + 	W8_1610_MMC2_DAT0,
+ + 	V8_1610_MMC2_DAT1,
+ + 	W15_1610_MMC2_DAT2,
+ + 	R10_1610_MMC2_DAT3,
+ + 	Y10_1610_MMC2_CLK,
+ + 	Y8_1610_MMC2_CMD,
+ + 	V9_1610_MMC2_CMDDIR,
+ + 	V5_1610_MMC2_DATDIR0,
+ + 	W19_1610_MMC2_DATDIR1,
+ + 	R18_1610_MMC2_CLKIN,
+ + 
+ + 	/* OMAP-1610 External Trace Interface */
+ + 	M19_1610_ETM_PSTAT0,
+ + 	L15_1610_ETM_PSTAT1,
+ + 	L18_1610_ETM_PSTAT2,
+ + 	L19_1610_ETM_D0,
+ + 	J19_1610_ETM_D6,
+ + 	J18_1610_ETM_D7,
+ + 
+ + 	/* OMAP16XX GPIO */
+ + 	P20_1610_GPIO4,
+ + 	V9_1610_GPIO7,
+ + 	W8_1610_GPIO9,
+ + 	N20_1610_GPIO11,
+ + 	N19_1610_GPIO13,
+ + 	P10_1610_GPIO22,
+ + 	V5_1610_GPIO24,
+ + 	AA20_1610_GPIO_41,
+ + 	W19_1610_GPIO48,
+ + 	M7_1610_GPIO62,
+ + 	V14_16XX_GPIO37,
+ + 	R9_16XX_GPIO18,
+ + 	L14_16XX_GPIO49,
+ + 
+ + 	/* OMAP-1610 uWire */
+ + 	V19_1610_UWIRE_SCLK,
+ + 	U18_1610_UWIRE_SDI,
+ + 	W21_1610_UWIRE_SDO,
+ + 	N14_1610_UWIRE_CS0,
+ + 	P15_1610_UWIRE_CS3,
+ + 	N15_1610_UWIRE_CS1,
+ + 
+ + 	/* OMAP-1610 SPI */
+ + 	U19_1610_SPIF_SCK,
+ + 	U18_1610_SPIF_DIN,
+ + 	P20_1610_SPIF_DIN,
+ + 	W21_1610_SPIF_DOUT,
+ + 	R18_1610_SPIF_DOUT,
+ + 	N14_1610_SPIF_CS0,
+ + 	N15_1610_SPIF_CS1,
+ + 	T19_1610_SPIF_CS2,
+ + 	P15_1610_SPIF_CS3,
+ + 
+ + 	/* OMAP-1610 Flash */
+ + 	L3_1610_FLASH_CS2B_OE,
+ + 	M8_1610_FLASH_CS2B_WE,
+ + 
+ + 	/* First MMC */
+ + 	MMC_CMD,
+ + 	MMC_DAT1,
+ + 	MMC_DAT2,
+ + 	MMC_DAT0,
+ + 	MMC_CLK,
+ + 	MMC_DAT3,
+ + 
+ + 	/* OMAP-1710 MMC CMDDIR and DATDIR0 */
+ + 	M15_1710_MMC_CLKI,
+ + 	P19_1710_MMC_CMDDIR,
+ + 	P20_1710_MMC_DATDIR0,
+ + 
+ + 	/* OMAP-1610 USB0 alternate pin configuration */
+ + 	W9_USB0_TXEN,
+ + 	AA9_USB0_VP,
+ + 	Y5_USB0_RCV,
+ + 	R9_USB0_VM,
+ + 	V6_USB0_TXD,
+ + 	W5_USB0_SE0,
+ + 	V9_USB0_SPEED,
+ + 	V9_USB0_SUSP,
+ + 
+ + 	/* USB2 */
+ + 	W9_USB2_TXEN,
+ + 	AA9_USB2_VP,
+ + 	Y5_USB2_RCV,
+ + 	R9_USB2_VM,
+ + 	V6_USB2_TXD,
+ + 	W5_USB2_SE0,
+ + 
+ + 	/* 16XX UART */
+ + 	R13_1610_UART1_TX,
+ + 	V14_16XX_UART1_RX,
+ + 	R14_1610_UART1_CTS,
+ + 	AA15_1610_UART1_RTS,
+ + 	R9_16XX_UART2_RX,
+ + 	L14_16XX_UART3_RX,
+ + 
+ + 	/* I2C OMAP-1610 */
+ + 	I2C_SCL,
+ + 	I2C_SDA,
+ + 
+ + 	/* Keypad */
+ + 	F18_1610_KBC0,
+ + 	D20_1610_KBC1,
+ + 	D19_1610_KBC2,
+ + 	E18_1610_KBC3,
+ + 	C21_1610_KBC4,
+ + 	G18_1610_KBR0,
+ + 	F19_1610_KBR1,
+ + 	H14_1610_KBR2,
+ + 	E20_1610_KBR3,
+ + 	E19_1610_KBR4,
+ + 	N19_1610_KBR5,
+ + 
+ + 	/* Power management */
+ + 	T20_1610_LOW_PWR,
+ + 
+ + 	/* MCLK Settings */
+ + 	V5_1710_MCLK_ON,
+ + 	V5_1710_MCLK_OFF,
+ + 	R10_1610_MCLK_ON,
+ + 	R10_1610_MCLK_OFF,
+ + 
+ + 	/* CompactFlash controller */
+ + 	P11_1610_CF_CD2,
+ + 	R11_1610_CF_IOIS16,
+ + 	V10_1610_CF_IREQ,
+ + 	W10_1610_CF_RESET,
+ + 	W11_1610_CF_CD1,
+ + 
+ + 	/* parallel camera */
+ + 	J15_1610_CAM_LCLK,
+ + 	J18_1610_CAM_D7,
+ + 	J19_1610_CAM_D6,
+ + 	J14_1610_CAM_D5,
+ + 	K18_1610_CAM_D4,
+ + 	K19_1610_CAM_D3,
+ + 	K15_1610_CAM_D2,
+ + 	K14_1610_CAM_D1,
+ + 	L19_1610_CAM_D0,
+ + 	L18_1610_CAM_VS,
+ + 	L15_1610_CAM_HS,
+ + 	M19_1610_CAM_RSTZ,
+ + 	Y15_1610_CAM_OUTCLK,
+ + 
+ + 	/* serial camera */
+ + 	H19_1610_CAM_EXCLK,
+ + 	Y12_1610_CCP_CLKP,
+ + 	W13_1610_CCP_CLKM,
+ + 	W14_1610_CCP_DATAP,
+ + 	Y14_1610_CCP_DATAM,
+ + 
+ + };
+ + 
+ + struct omap_mux_cfg {
+ + 	struct pin_config	*pins;
+ + 	unsigned long		size;
+ + 	int			(*cfg_reg)(const struct pin_config *cfg);
+ + };
+ + 
+ + #ifdef	CONFIG_OMAP_MUX
+ + /* setup pin muxing in Linux */
+ + extern int omap1_mux_init(void);
+ + extern int omap_mux_register(struct omap_mux_cfg *);
+ + #else
+ + static inline int omap1_mux_init(void) { return 0; }
+ + #endif
+ + 
+ + extern int omap2_mux_init(void);
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/omap34xx.h linux-3.2.1/arch/arm/plat-ckb/include/plat/omap34xx.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/omap34xx.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/omap34xx.h	2014-11-25 13:19:15.183986704 +0900
+ ***************
+ *** 0 ****
+ --- 1,101 ----
+ + /*
+ +  * arch/arm/plat-omap/include/mach/omap34xx.h
+ +  *
+ +  * This file contains the processor specific definitions of the TI OMAP34XX.
+ +  *
+ +  * Copyright (C) 2007 Texas Instruments.
+ +  * Copyright (C) 2007 Nokia Corporation.
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; either version 2 of the License, or
+ +  * (at your option) any later version.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ +  */
+ + 
+ + #ifndef __ASM_ARCH_OMAP3_H
+ + #define __ASM_ARCH_OMAP3_H
+ + 
+ + /*
+ +  * Please place only base defines here and put the rest in device
+ +  * specific headers.
+ +  */
+ + 
+ + #define L4_34XX_BASE		0x48000000
+ + #define L4_WK_34XX_BASE		0x48300000
+ + #define L4_PER_34XX_BASE	0x49000000
+ + #define L4_EMU_34XX_BASE	0x54000000
+ + #define L3_34XX_BASE		0x68000000
+ + 
+ + #define L4_WK_AM33XX_BASE	0x44C00000
+ + 
+ + #define OMAP3430_32KSYNCT_BASE	0x48320000
+ + #define OMAP3430_CM_BASE	0x48004800
+ + #define OMAP3430_PRM_BASE	0x48306800
+ + #define OMAP343X_SMS_BASE	0x6C000000
+ + #define OMAP343X_SDRC_BASE	0x6D000000
+ + #define OMAP34XX_GPMC_BASE	0x6E000000
+ + #define OMAP343X_SCM_BASE	0x48002000
+ + #define OMAP343X_CTRL_BASE	OMAP343X_SCM_BASE
+ + 
+ + #define OMAP34XX_IC_BASE	0x48200000
+ + 
+ + #define OMAP3430_ISP_BASE		(L4_34XX_BASE + 0xBC000)
+ + #define OMAP3430_ISP_CBUFF_BASE		(OMAP3430_ISP_BASE + 0x0100)
+ + #define OMAP3430_ISP_CCP2_BASE		(OMAP3430_ISP_BASE + 0x0400)
+ + #define OMAP3430_ISP_CCDC_BASE		(OMAP3430_ISP_BASE + 0x0600)
+ + #define OMAP3430_ISP_HIST_BASE		(OMAP3430_ISP_BASE + 0x0A00)
+ + #define OMAP3430_ISP_H3A_BASE		(OMAP3430_ISP_BASE + 0x0C00)
+ + #define OMAP3430_ISP_PREV_BASE		(OMAP3430_ISP_BASE + 0x0E00)
+ + #define OMAP3430_ISP_RESZ_BASE		(OMAP3430_ISP_BASE + 0x1000)
+ + #define OMAP3430_ISP_SBL_BASE		(OMAP3430_ISP_BASE + 0x1200)
+ + #define OMAP3430_ISP_MMU_BASE		(OMAP3430_ISP_BASE + 0x1400)
+ + #define OMAP3430_ISP_CSI2A_REGS1_BASE	(OMAP3430_ISP_BASE + 0x1800)
+ + #define OMAP3430_ISP_CSIPHY2_BASE	(OMAP3430_ISP_BASE + 0x1970)
+ + #define OMAP3630_ISP_CSI2A_REGS2_BASE	(OMAP3430_ISP_BASE + 0x19C0)
+ + #define OMAP3630_ISP_CSI2C_REGS1_BASE	(OMAP3430_ISP_BASE + 0x1C00)
+ + #define OMAP3630_ISP_CSIPHY1_BASE	(OMAP3430_ISP_BASE + 0x1D70)
+ + #define OMAP3630_ISP_CSI2C_REGS2_BASE	(OMAP3430_ISP_BASE + 0x1DC0)
+ + 
+ + #define OMAP3430_ISP_END		(OMAP3430_ISP_BASE         + 0x06F)
+ + #define OMAP3430_ISP_CBUFF_END		(OMAP3430_ISP_CBUFF_BASE   + 0x077)
+ + #define OMAP3430_ISP_CCP2_END		(OMAP3430_ISP_CCP2_BASE    + 0x1EF)
+ + #define OMAP3430_ISP_CCDC_END		(OMAP3430_ISP_CCDC_BASE    + 0x0A7)
+ + #define OMAP3430_ISP_HIST_END		(OMAP3430_ISP_HIST_BASE    + 0x047)
+ + #define OMAP3430_ISP_H3A_END		(OMAP3430_ISP_H3A_BASE     + 0x05F)
+ + #define OMAP3430_ISP_PREV_END		(OMAP3430_ISP_PREV_BASE    + 0x09F)
+ + #define OMAP3430_ISP_RESZ_END		(OMAP3430_ISP_RESZ_BASE    + 0x0AB)
+ + #define OMAP3430_ISP_SBL_END		(OMAP3430_ISP_SBL_BASE     + 0x0FB)
+ + #define OMAP3430_ISP_MMU_END		(OMAP3430_ISP_MMU_BASE     + 0x06F)
+ + #define OMAP3430_ISP_CSI2A_REGS1_END	(OMAP3430_ISP_CSI2A_REGS1_BASE + 0x16F)
+ + #define OMAP3430_ISP_CSIPHY2_END	(OMAP3430_ISP_CSIPHY2_BASE + 0x00B)
+ + #define OMAP3630_ISP_CSI2A_REGS2_END	(OMAP3630_ISP_CSI2A_REGS2_BASE + 0x3F)
+ + #define OMAP3630_ISP_CSI2C_REGS1_END	(OMAP3630_ISP_CSI2C_REGS1_BASE + 0x16F)
+ + #define OMAP3630_ISP_CSIPHY1_END	(OMAP3630_ISP_CSIPHY1_BASE + 0x00B)
+ + #define OMAP3630_ISP_CSI2C_REGS2_END	(OMAP3630_ISP_CSI2C_REGS2_BASE + 0x3F)
+ + 
+ + #define OMAP34XX_HSUSB_OTG_BASE	(L4_34XX_BASE + 0xAB000)
+ + #define OMAP34XX_USBTLL_BASE	(L4_34XX_BASE + 0x62000)
+ + #define OMAP34XX_UHH_CONFIG_BASE	(L4_34XX_BASE + 0x64000)
+ + #define OMAP34XX_OHCI_BASE	(L4_34XX_BASE + 0x64400)
+ + #define OMAP34XX_EHCI_BASE	(L4_34XX_BASE + 0x64800)
+ + #define OMAP34XX_SR1_BASE	0x480C9000
+ + #define OMAP34XX_SR2_BASE	0x480CB000
+ + 
+ + #define OMAP34XX_MAILBOX_BASE		(L4_34XX_BASE + 0x94000)
+ + 
+ + /* Security */
+ + #define OMAP34XX_SEC_BASE	(L4_34XX_BASE + 0xA0000)
+ + #define OMAP34XX_SEC_SHA1MD5_BASE	(OMAP34XX_SEC_BASE + 0x23000)
+ + #define OMAP34XX_SEC_AES_BASE	(OMAP34XX_SEC_BASE + 0x25000)
+ + 
+ + #endif /* __ASM_ARCH_OMAP3_H */
+ + 
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/omap_device.h linux-3.2.1/arch/arm/plat-ckb/include/plat/omap_device.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/omap_device.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/omap_device.h	2014-11-25 13:19:15.183986704 +0900
+ ***************
+ *** 0 ****
+ --- 1,171 ----
+ + /*
+ +  * omap_device headers
+ +  *
+ +  * Copyright (C) 2009 Nokia Corporation
+ +  * Paul Walmsley
+ +  *
+ +  * Developed in collaboration with (alphabetical order): Benoit
+ +  * Cousson, Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram
+ +  * Pandita, Sakari Poussa, Anand Sawant, Santosh Shilimkar, Richard
+ +  * Woodruff
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  *
+ +  * Eventually this type of functionality should either be
+ +  * a) implemented via arch-specific pointers in platform_device
+ +  * or
+ +  * b) implemented as a proper omap_bus/omap_device in Linux, no more
+ +  *    platform_device
+ +  *
+ +  * omap_device differs from omap_hwmod in that it includes external
+ +  * (e.g., board- and system-level) integration details.  omap_hwmod
+ +  * stores hardware data that is invariant for a given OMAP chip.
+ +  *
+ +  * To do:
+ +  * - GPIO integration
+ +  * - regulator integration
+ +  *
+ +  */
+ + #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_DEVICE_H
+ + #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_DEVICE_H
+ + 
+ + #include <linux/kernel.h>
+ + #include <linux/platform_device.h>
+ + 
+ + #include <plat/omap_hwmod.h>
+ + 
+ + extern struct device omap_device_parent;
+ + 
+ + /* omap_device._state values */
+ + #define OMAP_DEVICE_STATE_UNKNOWN	0
+ + #define OMAP_DEVICE_STATE_ENABLED	1
+ + #define OMAP_DEVICE_STATE_IDLE		2
+ + #define OMAP_DEVICE_STATE_SHUTDOWN	3
+ + 
+ + /* omap_device.flags values */
+ + #define OMAP_DEVICE_SUSPENDED BIT(0)
+ + #define OMAP_DEVICE_NO_IDLE_ON_SUSPEND BIT(1)
+ + 
+ + /**
+ +  * struct omap_device - omap_device wrapper for platform_devices
+ +  * @pdev: platform_device
+ +  * @hwmods: (one .. many per omap_device)
+ +  * @hwmods_cnt: ARRAY_SIZE() of @hwmods
+ +  * @pm_lats: ptr to an omap_device_pm_latency table
+ +  * @pm_lats_cnt: ARRAY_SIZE() of what is passed to @pm_lats
+ +  * @pm_lat_level: array index of the last odpl entry executed - -1 if never
+ +  * @dev_wakeup_lat: dev wakeup latency in nanoseconds
+ +  * @_dev_wakeup_lat_limit: dev wakeup latency limit in nsec - set by OMAP PM
+ +  * @_state: one of OMAP_DEVICE_STATE_* (see above)
+ +  * @flags: device flags
+ +  *
+ +  * Integrates omap_hwmod data into Linux platform_device.
+ +  *
+ +  * Field names beginning with underscores are for the internal use of
+ +  * the omap_device code.
+ +  *
+ +  */
+ + struct omap_device {
+ + 	struct platform_device		*pdev;
+ + 	struct omap_hwmod		**hwmods;
+ + 	struct omap_device_pm_latency	*pm_lats;
+ + 	u32				dev_wakeup_lat;
+ + 	u32				_dev_wakeup_lat_limit;
+ + 	u8				pm_lats_cnt;
+ + 	s8				pm_lat_level;
+ + 	u8				hwmods_cnt;
+ + 	u8				_state;
+ + 	u8                              flags;
+ + };
+ + 
+ + /* Device driver interface (call via platform_data fn ptrs) */
+ + 
+ + int omap_device_enable(struct platform_device *pdev);
+ + int omap_device_idle(struct platform_device *pdev);
+ + int omap_device_shutdown(struct platform_device *pdev);
+ + 
+ + /* Core code interface */
+ + 
+ + struct platform_device *omap_device_build(const char *pdev_name, int pdev_id,
+ + 				      struct omap_hwmod *oh, void *pdata,
+ + 				      int pdata_len,
+ + 				      struct omap_device_pm_latency *pm_lats,
+ + 				      int pm_lats_cnt, int is_early_device);
+ + 
+ + struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
+ + 					 struct omap_hwmod **oh, int oh_cnt,
+ + 					 void *pdata, int pdata_len,
+ + 					 struct omap_device_pm_latency *pm_lats,
+ + 					 int pm_lats_cnt, int is_early_device);
+ + 
+ + struct omap_device *omap_device_alloc(struct platform_device *pdev,
+ + 				      struct omap_hwmod **ohs, int oh_cnt,
+ + 				      struct omap_device_pm_latency *pm_lats,
+ + 				      int pm_lats_cnt);
+ + void omap_device_delete(struct omap_device *od);
+ + int omap_device_register(struct platform_device *pdev);
+ + 
+ + void __iomem *omap_device_get_rt_va(struct omap_device *od);
+ + struct device *omap_device_get_by_hwmod_name(const char *oh_name);
+ + 
+ + /* OMAP PM interface */
+ + int omap_device_align_pm_lat(struct platform_device *pdev,
+ + 			     u32 new_wakeup_lat_limit);
+ + struct powerdomain *omap_device_get_pwrdm(struct omap_device *od);
+ + int omap_device_get_context_loss_count(struct platform_device *pdev);
+ + 
+ + /* Other */
+ + 
+ + int omap_device_idle_hwmods(struct omap_device *od);
+ + int omap_device_enable_hwmods(struct omap_device *od);
+ + 
+ + int omap_device_disable_clocks(struct omap_device *od);
+ + int omap_device_enable_clocks(struct omap_device *od);
+ + int omap_device_reset(struct device *dev);
+ + 
+ + /*
+ +  * Entries should be kept in latency order ascending
+ +  *
+ +  * deact_lat is the maximum number of microseconds required to complete
+ +  * deactivate_func() at the device's slowest OPP.
+ +  *
+ +  * act_lat is the maximum number of microseconds required to complete
+ +  * activate_func() at the device's slowest OPP.
+ +  *
+ +  * This will result in some suboptimal power management decisions at fast
+ +  * OPPs, but avoids having to recompute all device power management decisions
+ +  * if the system shifts from a fast OPP to a slow OPP (in order to meet
+ +  * latency requirements).
+ +  *
+ +  * XXX should deactivate_func/activate_func() take platform_device pointers
+ +  * rather than omap_device pointers?
+ +  */
+ + struct omap_device_pm_latency {
+ + 	u32 deactivate_lat;
+ + 	u32 deactivate_lat_worst;
+ + 	int (*deactivate_func)(struct omap_device *od);
+ + 	u32 activate_lat;
+ + 	u32 activate_lat_worst;
+ + 	int (*activate_func)(struct omap_device *od);
+ + 	u32 flags;
+ + };
+ + 
+ + #define OMAP_DEVICE_LATENCY_AUTO_ADJUST BIT(1)
+ + 
+ + /* Get omap_device pointer from platform_device pointer */
+ + static inline struct omap_device *to_omap_device(struct platform_device *pdev)
+ + {
+ + 	return pdev ? pdev->archdata.od : NULL;
+ + }
+ + 
+ + static inline
+ + void omap_device_disable_idle_on_suspend(struct platform_device *pdev)
+ + {
+ + 	struct omap_device *od = to_omap_device(pdev);
+ + 
+ + 	od->flags |= OMAP_DEVICE_NO_IDLE_ON_SUSPEND;
+ + }
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/omap_hwmod.h linux-3.2.1/arch/arm/plat-ckb/include/plat/omap_hwmod.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/omap_hwmod.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/omap_hwmod.h	2014-11-25 13:19:15.183986704 +0900
+ ***************
+ *** 0 ****
+ --- 1,659 ----
+ + /*
+ +  * omap_hwmod macros, structures
+ +  *
+ +  * Copyright (C) 2009-2011 Nokia Corporation
+ +  * Copyright (C) 2011 Texas Instruments, Inc.
+ +  * Paul Walmsley
+ +  *
+ +  * Created in collaboration with (alphabetical order): Benoît Cousson,
+ +  * Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari
+ +  * Poussa, Anand Sawant, Santosh Shilimkar, Richard Woodruff
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  *
+ +  * These headers and macros are used to define OMAP on-chip module
+ +  * data and their integration with other OMAP modules and Linux.
+ +  * Copious documentation and references can also be found in the
+ +  * omap_hwmod code, in arch/arm/mach-omap2/omap_hwmod.c (as of this
+ +  * writing).
+ +  *
+ +  * To do:
+ +  * - add interconnect error log structures
+ +  * - add pinmuxing
+ +  * - init_conn_id_bit (CONNID_BIT_VECTOR)
+ +  * - implement default hwmod SMS/SDRC flags?
+ +  * - move Linux-specific data ("non-ROM data") out
+ +  *
+ +  */
+ + #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
+ + #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
+ + 
+ + #include <linux/kernel.h>
+ + #include <linux/init.h>
+ + #include <linux/list.h>
+ + #include <linux/ioport.h>
+ + #include <linux/spinlock.h>
+ + #include <plat/cpu.h>
+ + 
+ + struct omap_device;
+ + 
+ + extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1;
+ + extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
+ + extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3;
+ + extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type4;
+ + 
+ + /*
+ +  * OCP SYSCONFIG bit shifts/masks TYPE1. These are for IPs compliant
+ +  * with the original PRCM protocol defined for OMAP2420
+ +  */
+ + #define SYSC_TYPE1_MIDLEMODE_SHIFT	12
+ + #define SYSC_TYPE1_MIDLEMODE_MASK	(0x3 << SYSC_MIDLEMODE_SHIFT)
+ + #define SYSC_TYPE1_CLOCKACTIVITY_SHIFT	8
+ + #define SYSC_TYPE1_CLOCKACTIVITY_MASK	(0x3 << SYSC_CLOCKACTIVITY_SHIFT)
+ + #define SYSC_TYPE1_SIDLEMODE_SHIFT	3
+ + #define SYSC_TYPE1_SIDLEMODE_MASK	(0x3 << SYSC_SIDLEMODE_SHIFT)
+ + #define SYSC_TYPE1_ENAWAKEUP_SHIFT	2
+ + #define SYSC_TYPE1_ENAWAKEUP_MASK	(1 << SYSC_ENAWAKEUP_SHIFT)
+ + #define SYSC_TYPE1_SOFTRESET_SHIFT	1
+ + #define SYSC_TYPE1_SOFTRESET_MASK	(1 << SYSC_SOFTRESET_SHIFT)
+ + #define SYSC_TYPE1_AUTOIDLE_SHIFT	0
+ + #define SYSC_TYPE1_AUTOIDLE_MASK	(1 << SYSC_AUTOIDLE_SHIFT)
+ + 
+ + /*
+ +  * OCP SYSCONFIG bit shifts/masks TYPE2. These are for IPs compliant
+ +  * with the new PRCM protocol defined for new OMAP4 IPs.
+ +  */
+ + #define SYSC_TYPE2_SOFTRESET_SHIFT	0
+ + #define SYSC_TYPE2_SOFTRESET_MASK	(1 << SYSC_TYPE2_SOFTRESET_SHIFT)
+ + #define SYSC_TYPE2_SIDLEMODE_SHIFT	2
+ + #define SYSC_TYPE2_SIDLEMODE_MASK	(0x3 << SYSC_TYPE2_SIDLEMODE_SHIFT)
+ + #define SYSC_TYPE2_MIDLEMODE_SHIFT	4
+ + #define SYSC_TYPE2_MIDLEMODE_MASK	(0x3 << SYSC_TYPE2_MIDLEMODE_SHIFT)
+ + 
+ + /*
+ +  * OCP SYSCONFIG bit shifts/masks TYPE3.
+ +  * This is applicable for some IPs present in AM33XX
+ +  */
+ + #define SYSC_TYPE3_SIDLEMODE_SHIFT	0
+ + #define SYSC_TYPE3_SIDLEMODE_MASK	(0x3 << SYSC_TYPE3_SIDLEMODE_SHIFT)
+ + #define SYSC_TYPE3_MIDLEMODE_SHIFT	2
+ + #define SYSC_TYPE3_MIDLEMODE_MASK	(0x3 << SYSC_TYPE3_MIDLEMODE_SHIFT)
+ + 
+ + /*
+ +  * OCP SYSCONFIG bit shifts/masks TYPE4.
+ +  * This is applicable for some IPs present in AM33XX
+ +  */
+ + #define SYSC_TYPE4_CLOCKACTIVITY_SHIFT	8
+ + #define SYSC_TYPE4_CLOCKACTIVITY_MASK	(0x3 << SYSC_CLOCKACTIVITY_SHIFT)
+ + #define SYSC_TYPE4_MIDLEMODE_SHIFT	5
+ + #define SYSC_TYPE4_MIDLEMODE_MASK	(0x3 << SYSC_MIDLEMODE_SHIFT)
+ + #define SYSC_TYPE4_SIDLEMODE_SHIFT	3
+ + #define SYSC_TYPE4_SIDLEMODE_MASK	(0x3 << SYSC_SIDLEMODE_SHIFT)
+ + #define SYSC_TYPE4_ENAWAKEUP_SHIFT	2
+ + #define SYSC_TYPE4_ENAWAKEUP_MASK	(1 << SYSC_ENAWAKEUP_SHIFT)
+ + #define SYSC_TYPE4_SOFTRESET_SHIFT	1
+ + #define SYSC_TYPE4_SOFTRESET_MASK	(1 << SYSC_SOFTRESET_SHIFT)
+ + #define SYSC_TYPE4_AUTOIDLE_SHIFT	0
+ + #define SYSC_TYPE4_AUTOIDLE_MASK	(1 << SYSC_AUTOIDLE_SHIFT)
+ + 
+ + /* OCP SYSSTATUS bit shifts/masks */
+ + #define SYSS_RESETDONE_SHIFT		0
+ + #define SYSS_RESETDONE_MASK		(1 << SYSS_RESETDONE_SHIFT)
+ + 
+ + /* Master standby/slave idle mode flags */
+ + #define HWMOD_IDLEMODE_FORCE		(1 << 0)
+ + #define HWMOD_IDLEMODE_NO		(1 << 1)
+ + #define HWMOD_IDLEMODE_SMART		(1 << 2)
+ + #define HWMOD_IDLEMODE_SMART_WKUP	(1 << 3)
+ + 
+ + /* modulemode control type (SW or HW) */
+ + #define MODULEMODE_HWCTRL		1
+ + #define MODULEMODE_SWCTRL		2
+ + 
+ + 
+ + /**
+ +  * struct omap_hwmod_mux_info - hwmod specific mux configuration
+ +  * @pads:              array of omap_device_pad entries
+ +  * @nr_pads:           number of omap_device_pad entries
+ +  *
+ +  * Note that this is currently built during init as needed.
+ +  */
+ + struct omap_hwmod_mux_info {
+ + 	int				nr_pads;
+ + 	struct omap_device_pad		*pads;
+ + 	int				nr_pads_dynamic;
+ + 	struct omap_device_pad		**pads_dynamic;
+ + 	int				*irqs;
+ + 	bool				enabled;
+ + };
+ + 
+ + /**
+ +  * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod
+ +  * @name: name of the IRQ channel (module local name)
+ +  * @irq: IRQ channel ID (should be non-negative except -1 = terminator)
+ +  *
+ +  * @name should be something short, e.g., "tx" or "rx".  It is for use
+ +  * by platform_get_resource_byname().  It is defined locally to the
+ +  * hwmod.
+ +  */
+ + struct omap_hwmod_irq_info {
+ + 	const char	*name;
+ + 	s16		irq;
+ + };
+ + 
+ + /**
+ +  * struct omap_hwmod_dma_info - DMA channels used by the hwmod
+ +  * @name: name of the DMA channel (module local name)
+ +  * @dma_req: DMA request ID (should be non-negative except -1 = terminator)
+ +  *
+ +  * @name should be something short, e.g., "tx" or "rx".  It is for use
+ +  * by platform_get_resource_byname().  It is defined locally to the
+ +  * hwmod.
+ +  */
+ + struct omap_hwmod_dma_info {
+ + 	const char	*name;
+ + 	s16		dma_req;
+ + };
+ + 
+ + /**
+ +  * struct omap_hwmod_rst_info - IPs reset lines use by hwmod
+ +  * @name: name of the reset line (module local name)
+ +  * @rst_shift: Offset of the reset bit
+ +  * @st_shift: Offset of the reset status bit (OMAP2/3 only)
+ +  *
+ +  * @name should be something short, e.g., "cpu0" or "rst". It is defined
+ +  * locally to the hwmod.
+ +  */
+ + struct omap_hwmod_rst_info {
+ + 	const char	*name;
+ + 	u8		rst_shift;
+ + 	u8		st_shift;
+ + };
+ + 
+ + /**
+ +  * struct omap_hwmod_opt_clk - optional clocks used by this hwmod
+ +  * @role: "sys", "32k", "tv", etc -- for use in clk_get()
+ +  * @clk: opt clock: OMAP clock name
+ +  * @_clk: pointer to the struct clk (filled in at runtime)
+ +  *
+ +  * The module's interface clock and main functional clock should not
+ +  * be added as optional clocks.
+ +  */
+ + struct omap_hwmod_opt_clk {
+ + 	const char	*role;
+ + 	const char	*clk;
+ + 	struct clk	*_clk;
+ + };
+ + 
+ + 
+ + /* omap_hwmod_omap2_firewall.flags bits */
+ + #define OMAP_FIREWALL_L3		(1 << 0)
+ + #define OMAP_FIREWALL_L4		(1 << 1)
+ + 
+ + /**
+ +  * struct omap_hwmod_omap2_firewall - OMAP2/3 device firewall data
+ +  * @l3_perm_bit: bit shift for L3_PM_*_PERMISSION_*
+ +  * @l4_fw_region: L4 firewall region ID
+ +  * @l4_prot_group: L4 protection group ID
+ +  * @flags: (see omap_hwmod_omap2_firewall.flags macros above)
+ +  */
+ + struct omap_hwmod_omap2_firewall {
+ + 	u8 l3_perm_bit;
+ + 	u8 l4_fw_region;
+ + 	u8 l4_prot_group;
+ + 	u8 flags;
+ + };
+ + 
+ + 
+ + /*
+ +  * omap_hwmod_addr_space.flags bits
+ +  *
+ +  * ADDR_MAP_ON_INIT: Map this address space during omap_hwmod init.
+ +  * ADDR_TYPE_RT: Address space contains module register target data.
+ +  */
+ + #define ADDR_MAP_ON_INIT	(1 << 0)	/* XXX does not belong */
+ + #define ADDR_TYPE_RT		(1 << 1)
+ + 
+ + /**
+ +  * struct omap_hwmod_addr_space - address space handled by the hwmod
+ +  * @name: name of the address space
+ +  * @pa_start: starting physical address
+ +  * @pa_end: ending physical address
+ +  * @flags: (see omap_hwmod_addr_space.flags macros above)
+ +  *
+ +  * Address space doesn't necessarily follow physical interconnect
+ +  * structure.  GPMC is one example.
+ +  */
+ + struct omap_hwmod_addr_space {
+ + 	const char *name;
+ + 	u32 pa_start;
+ + 	u32 pa_end;
+ + 	u8 flags;
+ + };
+ + 
+ + 
+ + /*
+ +  * omap_hwmod_ocp_if.user bits: these indicate the initiators that use this
+ +  * interface to interact with the hwmod.  Used to add sleep dependencies
+ +  * when the module is enabled or disabled.
+ +  */
+ + #define OCP_USER_MPU			(1 << 0)
+ + #define OCP_USER_SDMA			(1 << 1)
+ + 
+ + /* omap_hwmod_ocp_if.flags bits */
+ + #define OCPIF_SWSUP_IDLE		(1 << 0)
+ + #define OCPIF_CAN_BURST			(1 << 1)
+ + 
+ + /**
+ +  * struct omap_hwmod_ocp_if - OCP interface data
+ +  * @master: struct omap_hwmod that initiates OCP transactions on this link
+ +  * @slave: struct omap_hwmod that responds to OCP transactions on this link
+ +  * @addr: address space associated with this link
+ +  * @clk: interface clock: OMAP clock name
+ +  * @_clk: pointer to the interface struct clk (filled in at runtime)
+ +  * @fw: interface firewall data
+ +  * @width: OCP data width
+ +  * @user: initiators using this interface (see OCP_USER_* macros above)
+ +  * @flags: OCP interface flags (see OCPIF_* macros above)
+ +  *
+ +  * It may also be useful to add a tag_cnt field for OCP2.x devices.
+ +  *
+ +  * Parameter names beginning with an underscore are managed internally by
+ +  * the omap_hwmod code and should not be set during initialization.
+ +  */
+ + struct omap_hwmod_ocp_if {
+ + 	struct omap_hwmod		*master;
+ + 	struct omap_hwmod		*slave;
+ + 	struct omap_hwmod_addr_space	*addr;
+ + 	const char			*clk;
+ + 	struct clk			*_clk;
+ + 	union {
+ + 		struct omap_hwmod_omap2_firewall omap2;
+ + 	}				fw;
+ + 	u8				width;
+ + 	u8				user;
+ + 	u8				flags;
+ + };
+ + 
+ + 
+ + /* Macros for use in struct omap_hwmod_sysconfig */
+ + 
+ + /* Flags for use in omap_hwmod_sysconfig.idlemodes */
+ + #define MASTER_STANDBY_SHIFT	4
+ + #define SLAVE_IDLE_SHIFT	0
+ + #define SIDLE_FORCE		(HWMOD_IDLEMODE_FORCE << SLAVE_IDLE_SHIFT)
+ + #define SIDLE_NO		(HWMOD_IDLEMODE_NO << SLAVE_IDLE_SHIFT)
+ + #define SIDLE_SMART		(HWMOD_IDLEMODE_SMART << SLAVE_IDLE_SHIFT)
+ + #define SIDLE_SMART_WKUP	(HWMOD_IDLEMODE_SMART_WKUP << SLAVE_IDLE_SHIFT)
+ + #define MSTANDBY_FORCE		(HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT)
+ + #define MSTANDBY_NO		(HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT)
+ + #define MSTANDBY_SMART		(HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT)
+ + #define MSTANDBY_SMART_WKUP	(HWMOD_IDLEMODE_SMART_WKUP << MASTER_STANDBY_SHIFT)
+ + 
+ + /* omap_hwmod_sysconfig.sysc_flags capability flags */
+ + #define SYSC_HAS_AUTOIDLE	(1 << 0)
+ + #define SYSC_HAS_SOFTRESET	(1 << 1)
+ + #define SYSC_HAS_ENAWAKEUP	(1 << 2)
+ + #define SYSC_HAS_EMUFREE	(1 << 3)
+ + #define SYSC_HAS_CLOCKACTIVITY	(1 << 4)
+ + #define SYSC_HAS_SIDLEMODE	(1 << 5)
+ + #define SYSC_HAS_MIDLEMODE	(1 << 6)
+ + #define SYSS_HAS_RESET_STATUS	(1 << 7)
+ + #define SYSC_NO_CACHE		(1 << 8)  /* XXX SW flag, belongs elsewhere */
+ + #define SYSC_HAS_RESET_STATUS	(1 << 9)
+ + 
+ + /* omap_hwmod_sysconfig.clockact flags */
+ + #define CLOCKACT_TEST_BOTH	0x0
+ + #define CLOCKACT_TEST_MAIN	0x1
+ + #define CLOCKACT_TEST_ICLK	0x2
+ + #define CLOCKACT_TEST_NONE	0x3
+ + 
+ + /**
+ +  * struct omap_hwmod_sysc_fields - hwmod OCP_SYSCONFIG register field offsets.
+ +  * @midle_shift: Offset of the midle bit
+ +  * @clkact_shift: Offset of the clockactivity bit
+ +  * @sidle_shift: Offset of the sidle bit
+ +  * @enwkup_shift: Offset of the enawakeup bit
+ +  * @srst_shift: Offset of the softreset bit
+ +  * @autoidle_shift: Offset of the autoidle bit
+ +  */
+ + struct omap_hwmod_sysc_fields {
+ + 	u8 midle_shift;
+ + 	u8 clkact_shift;
+ + 	u8 sidle_shift;
+ + 	u8 enwkup_shift;
+ + 	u8 srst_shift;
+ + 	u8 autoidle_shift;
+ + };
+ + 
+ + /**
+ +  * struct omap_hwmod_class_sysconfig - hwmod class OCP_SYS* data
+ +  * @rev_offs: IP block revision register offset (from module base addr)
+ +  * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr)
+ +  * @syss_offs: OCP_SYSSTATUS register offset (from module base addr)
+ +  * @rst_offs: OCP_SOFTRST register offset (from module base addr)
+ +  * @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART}
+ +  * @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported
+ +  * @clockact: the default value of the module CLOCKACTIVITY bits
+ +  *
+ +  * @clockact describes to the module which clocks are likely to be
+ +  * disabled when the PRCM issues its idle request to the module.  Some
+ +  * modules have separate clockdomains for the interface clock and main
+ +  * functional clock, and can check whether they should acknowledge the
+ +  * idle request based on the internal module functionality that has
+ +  * been associated with the clocks marked in @clockact.  This field is
+ +  * only used if HWMOD_SET_DEFAULT_CLOCKACT is set (see below)
+ +  *
+ +  * @sysc_fields: structure containing the offset positions of various bits in
+ +  * SYSCONFIG register. This can be populated using omap_hwmod_sysc_type1 or
+ +  * omap_hwmod_sysc_type2 defined in omap_hwmod_common_data.c depending on
+ +  * whether the device ip is compliant with the original PRCM protocol
+ +  * defined for OMAP2420 or the new PRCM protocol for new OMAP4 IPs.
+ +  * If the device follows a different scheme for the sysconfig register ,
+ +  * then this field has to be populated with the correct offset structure.
+ +  */
+ + struct omap_hwmod_class_sysconfig {
+ + 	u16 rev_offs;
+ + 	u16 sysc_offs;
+ + 	u16 syss_offs;
+ + 	u16 rst_offs;
+ + 	u16 sysc_flags;
+ + 	u8 idlemodes;
+ + 	u8 clockact;
+ + 	struct omap_hwmod_sysc_fields *sysc_fields;
+ + };
+ + 
+ + /**
+ +  * struct omap_hwmod_omap2_prcm - OMAP2/3-specific PRCM data
+ +  * @module_offs: PRCM submodule offset from the start of the PRM/CM
+ +  * @prcm_reg_id: PRCM register ID (e.g., 3 for CM_AUTOIDLE3)
+ +  * @module_bit: register bit shift for AUTOIDLE, WKST, WKEN, GRPSEL regs
+ +  * @idlest_reg_id: IDLEST register ID (e.g., 3 for CM_IDLEST3)
+ +  * @idlest_idle_bit: register bit shift for CM_IDLEST slave idle bit
+ +  * @idlest_stdby_bit: register bit shift for CM_IDLEST master standby bit
+ +  *
+ +  * @prcm_reg_id and @module_bit are specific to the AUTOIDLE, WKST,
+ +  * WKEN, GRPSEL registers.  In an ideal world, no extra information
+ +  * would be needed for IDLEST information, but alas, there are some
+ +  * exceptions, so @idlest_reg_id, @idlest_idle_bit, @idlest_stdby_bit
+ +  * are needed for the IDLEST registers (c.f. 2430 I2CHS, 3430 USBHOST)
+ +  */
+ + struct omap_hwmod_omap2_prcm {
+ + 	s16 module_offs;
+ + 	u8 prcm_reg_id;
+ + 	u8 module_bit;
+ + 	u8 idlest_reg_id;
+ + 	u8 idlest_idle_bit;
+ + 	u8 idlest_stdby_bit;
+ + };
+ + 
+ + 
+ + /**
+ +  * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
+ +  * @clkctrl_reg: PRCM address of the clock control register
+ +  * @rstctrl_reg: address of the XXX_RSTCTRL register located in the PRM
+ +  * @rstst_reg: address of the XXX_RSTST register located in the PRM
+ +  * @submodule_wkdep_bit: bit shift of the WKDEP range
+ +  */
+ + struct omap_hwmod_omap4_prcm {
+ + 	u16		clkctrl_offs;
+ + 	u16		rstctrl_offs;
+ + 	u16		rstst_offs;
+ + 	u16		context_offs;
+ + 	u8		submodule_wkdep_bit;
+ + 	u8		modulemode;
+ + };
+ + 
+ + 
+ + /*
+ +  * omap_hwmod.flags definitions
+ +  *
+ +  * HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out
+ +  *     of idle, rather than relying on module smart-idle
+ +  * HWMOD_SWSUP_MSTDBY: omap_hwmod code should manually bring module in and out
+ +  *     of standby, rather than relying on module smart-standby
+ +  * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for
+ +  *     SDRAM controller, etc. XXX probably belongs outside the main hwmod file
+ +  *     XXX Should be HWMOD_SETUP_NO_RESET
+ +  * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM
+ +  *     controller, etc. XXX probably belongs outside the main hwmod file
+ +  *     XXX Should be HWMOD_SETUP_NO_IDLE
+ +  * HWMOD_NO_OCP_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE)
+ +  *     when module is enabled, rather than the default, which is to
+ +  *     enable autoidle
+ +  * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup
+ +  * HWMOD_NO_IDLEST: this module does not have idle status - this is the case
+ +  *     only for few initiator modules on OMAP2 & 3.
+ +  * HWMOD_CONTROL_OPT_CLKS_IN_RESET: Enable all optional clocks during reset.
+ +  *     This is needed for devices like DSS that require optional clocks enabled
+ +  *     in order to complete the reset. Optional clocks will be disabled
+ +  *     again after the reset.
+ +  * HWMOD_16BIT_REG: Module has 16bit registers
+ +  * HWMOD_SWSUP_RESET_BEFORE_IDLE: omap_hwmod code should assert the ocp_reset before
+ +  *     idling/disabling the module.
+ +  */
+ + #define HWMOD_SWSUP_SIDLE			(1 << 0)
+ + #define HWMOD_SWSUP_MSTANDBY			(1 << 1)
+ + #define HWMOD_INIT_NO_RESET			(1 << 2)
+ + #define HWMOD_INIT_NO_IDLE			(1 << 3)
+ + #define HWMOD_NO_OCP_AUTOIDLE			(1 << 4)
+ + #define HWMOD_SET_DEFAULT_CLOCKACT		(1 << 5)
+ + #define HWMOD_NO_IDLEST				(1 << 6)
+ + #define HWMOD_CONTROL_OPT_CLKS_IN_RESET		(1 << 7)
+ + #define HWMOD_16BIT_REG				(1 << 8)
+ + #define HWMOD_SWSUP_RESET_BEFORE_IDLE		(1 << 9)
+ + 
+ + /*
+ +  * omap_hwmod._int_flags definitions
+ +  * These are for internal use only and are managed by the omap_hwmod code.
+ +  *
+ +  * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module
+ +  * _HWMOD_WAKEUP_ENABLED: set when the omap_hwmod code has enabled ENAWAKEUP
+ +  * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached
+ +  * _HWMOD_SKIP_ENABLE: set if hwmod enabled during init (HWMOD_INIT_NO_IDLE) -
+ +  *     causes the first call to _enable() to only update the pinmux
+ +  */
+ + #define _HWMOD_NO_MPU_PORT			(1 << 0)
+ + #define _HWMOD_WAKEUP_ENABLED			(1 << 1)
+ + #define _HWMOD_SYSCONFIG_LOADED			(1 << 2)
+ + #define _HWMOD_SKIP_ENABLE			(1 << 3)
+ + 
+ + /*
+ +  * omap_hwmod._state definitions
+ +  *
+ +  * INITIALIZED: reset (optionally), initialized, enabled, disabled
+ +  *              (optionally)
+ +  *
+ +  *
+ +  */
+ + #define _HWMOD_STATE_UNKNOWN			0
+ + #define _HWMOD_STATE_REGISTERED			1
+ + #define _HWMOD_STATE_CLKS_INITED		2
+ + #define _HWMOD_STATE_INITIALIZED		3
+ + #define _HWMOD_STATE_ENABLED			4
+ + #define _HWMOD_STATE_IDLE			5
+ + #define _HWMOD_STATE_DISABLED			6
+ + 
+ + /**
+ +  * struct omap_hwmod_class - the type of an IP block
+ +  * @name: name of the hwmod_class
+ +  * @sysc: device SYSCONFIG/SYSSTATUS register data
+ +  * @rev: revision of the IP class
+ +  * @pre_shutdown: ptr to fn to be executed immediately prior to device shutdown
+ +  * @reset: ptr to fn to be executed in place of the standard hwmod reset fn
+ +  *
+ +  * Represent the class of a OMAP hardware "modules" (e.g. timer,
+ +  * smartreflex, gpio, uart...)
+ +  *
+ +  * @pre_shutdown is a function that will be run immediately before
+ +  * hwmod clocks are disabled, etc.  It is intended for use for hwmods
+ +  * like the MPU watchdog, which cannot be disabled with the standard
+ +  * omap_hwmod_shutdown().  The function should return 0 upon success,
+ +  * or some negative error upon failure.  Returning an error will cause
+ +  * omap_hwmod_shutdown() to abort the device shutdown and return an
+ +  * error.
+ +  *
+ +  * If @reset is defined, then the function it points to will be
+ +  * executed in place of the standard hwmod _reset() code in
+ +  * mach-omap2/omap_hwmod.c.  This is needed for IP blocks which have
+ +  * unusual reset sequences - usually processor IP blocks like the IVA.
+ +  */
+ + struct omap_hwmod_class {
+ + 	const char				*name;
+ + 	struct omap_hwmod_class_sysconfig	*sysc;
+ + 	u32					rev;
+ + 	int					(*pre_shutdown)(struct omap_hwmod *oh);
+ + 	int					(*reset)(struct omap_hwmod *oh);
+ + };
+ + 
+ + /**
+ +  * struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks)
+ +  * @name: name of the hwmod
+ +  * @class: struct omap_hwmod_class * to the class of this hwmod
+ +  * @od: struct omap_device currently associated with this hwmod (internal use)
+ +  * @mpu_irqs: ptr to an array of MPU IRQs
+ +  * @sdma_reqs: ptr to an array of System DMA request IDs
+ +  * @prcm: PRCM data pertaining to this hwmod
+ +  * @main_clk: main clock: OMAP clock name
+ +  * @_clk: pointer to the main struct clk (filled in at runtime)
+ +  * @opt_clks: other device clocks that drivers can request (0..*)
+ +  * @vdd_name: voltage domain name
+ +  * @voltdm: pointer to voltage domain (filled in at runtime)
+ +  * @masters: ptr to array of OCP ifs that this hwmod can initiate on
+ +  * @slaves: ptr to array of OCP ifs that this hwmod can respond on
+ +  * @dev_attr: arbitrary device attributes that can be passed to the driver
+ +  * @_sysc_cache: internal-use hwmod flags
+ +  * @_mpu_rt_va: cached register target start address (internal use)
+ +  * @_mpu_port_index: cached MPU register target slave ID (internal use)
+ +  * @opt_clks_cnt: number of @opt_clks
+ +  * @master_cnt: number of @master entries
+ +  * @slaves_cnt: number of @slave entries
+ +  * @response_lat: device OCP response latency (in interface clock cycles)
+ +  * @_int_flags: internal-use hwmod flags
+ +  * @_state: internal-use hwmod state
+ +  * @_postsetup_state: internal-use state to leave the hwmod in after _setup()
+ +  * @flags: hwmod flags (documented below)
+ +  * @_lock: spinlock serializing operations on this hwmod
+ +  * @node: list node for hwmod list (internal use)
+ +  *
+ +  * @main_clk refers to this module's "main clock," which for our
+ +  * purposes is defined as "the functional clock needed for register
+ +  * accesses to complete."  Modules may not have a main clock if the
+ +  * interface clock also serves as a main clock.
+ +  *
+ +  * Parameter names beginning with an underscore are managed internally by
+ +  * the omap_hwmod code and should not be set during initialization.
+ +  */
+ + struct omap_hwmod {
+ + 	const char			*name;
+ + 	struct omap_hwmod_class		*class;
+ + 	struct omap_device		*od;
+ + 	struct omap_hwmod_mux_info	*mux;
+ + 	struct omap_hwmod_irq_info	*mpu_irqs;
+ + 	struct omap_hwmod_dma_info	*sdma_reqs;
+ + 	struct omap_hwmod_rst_info	*rst_lines;
+ + 	union {
+ + 		struct omap_hwmod_omap2_prcm omap2;
+ + 		struct omap_hwmod_omap4_prcm omap4;
+ + 	}				prcm;
+ + 	const char			*main_clk;
+ + 	struct clk			*_clk;
+ + 	struct omap_hwmod_opt_clk	*opt_clks;
+ + 	char				*clkdm_name;
+ + 	struct clockdomain		*clkdm;
+ + 	char				*vdd_name;
+ + 	struct omap_hwmod_ocp_if	**masters; /* connect to *_IA */
+ + 	struct omap_hwmod_ocp_if	**slaves;  /* connect to *_TA */
+ + 	void				*dev_attr;
+ + 	u32				_sysc_cache;
+ + 	void __iomem			*_mpu_rt_va;
+ + 	spinlock_t			_lock;
+ + 	struct list_head		node;
+ + 	u16				flags;
+ + 	u8				_mpu_port_index;
+ + 	u8				response_lat;
+ + 	u8				rst_lines_cnt;
+ + 	u8				opt_clks_cnt;
+ + 	u8				masters_cnt;
+ + 	u8				slaves_cnt;
+ + 	u8				hwmods_cnt;
+ + 	u8				_int_flags;
+ + 	u8				_state;
+ + 	u8				_postsetup_state;
+ + };
+ + 
+ + int omap_hwmod_register(struct omap_hwmod **ohs);
+ + struct omap_hwmod *omap_hwmod_lookup(const char *name);
+ + int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
+ + 			void *data);
+ + 
+ + int __init omap_hwmod_setup_one(const char *name);
+ + 
+ + int omap_hwmod_enable(struct omap_hwmod *oh);
+ + int _omap_hwmod_enable(struct omap_hwmod *oh);
+ + int omap_hwmod_idle(struct omap_hwmod *oh);
+ + int _omap_hwmod_idle(struct omap_hwmod *oh);
+ + int omap_hwmod_shutdown(struct omap_hwmod *oh);
+ + 
+ + int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name);
+ + int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name);
+ + int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name);
+ + 
+ + int omap_hwmod_enable_clocks(struct omap_hwmod *oh);
+ + int omap_hwmod_disable_clocks(struct omap_hwmod *oh);
+ + 
+ + int omap_hwmod_set_master_standbymode(struct omap_hwmod *oh, u8 idlemode);
+ + int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode);
+ + int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle);
+ + 
+ + int omap_hwmod_reset(struct omap_hwmod *oh);
+ + void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);
+ + 
+ + void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs);
+ + u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs);
+ + int omap_hwmod_softreset(struct omap_hwmod *oh);
+ + 
+ + int omap_hwmod_count_resources(struct omap_hwmod *oh);
+ + int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
+ + 
+ + struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh);
+ + void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh);
+ + 
+ + int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh,
+ + 				 struct omap_hwmod *init_oh);
+ + int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh,
+ + 				 struct omap_hwmod *init_oh);
+ + 
+ + int omap_hwmod_set_clockact_both(struct omap_hwmod *oh);
+ + int omap_hwmod_set_clockact_main(struct omap_hwmod *oh);
+ + int omap_hwmod_set_clockact_iclk(struct omap_hwmod *oh);
+ + int omap_hwmod_set_clockact_none(struct omap_hwmod *oh);
+ + 
+ + int omap_hwmod_enable_wakeup(struct omap_hwmod *oh);
+ + int omap_hwmod_disable_wakeup(struct omap_hwmod *oh);
+ + 
+ + int omap_hwmod_for_each_by_class(const char *classname,
+ + 				 int (*fn)(struct omap_hwmod *oh,
+ + 					   void *user),
+ + 				 void *user);
+ + 
+ + int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state);
+ + int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh);
+ + 
+ + int omap_hwmod_no_setup_reset(struct omap_hwmod *oh);
+ + 
+ + int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx);
+ + 
+ + /*
+ +  * Chip variant-specific hwmod init routines - XXX should be converted
+ +  * to use initcalls once the initial boot ordering is straightened out
+ +  */
+ + extern int omap2420_hwmod_init(void);
+ + extern int omap2430_hwmod_init(void);
+ + extern int omap3xxx_hwmod_init(void);
+ + extern int omap44xx_hwmod_init(void);
+ + extern int am33xx_hwmod_init(void);
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/omap-pm.h linux-3.2.1/arch/arm/plat-ckb/include/plat/omap-pm.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/omap-pm.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/omap-pm.h	2014-11-25 13:19:15.183986704 +0900
+ ***************
+ *** 0 ****
+ --- 1,352 ----
+ + /*
+ +  * omap-pm.h - OMAP power management interface
+ +  *
+ +  * Copyright (C) 2008-2010 Texas Instruments, Inc.
+ +  * Copyright (C) 2008-2010 Nokia Corporation
+ +  * Paul Walmsley
+ +  *
+ +  * Interface developed by (in alphabetical order): Karthik Dasu, Jouni
+ +  * Högander, Tony Lindgren, Rajendra Nayak, Sakari Poussa,
+ +  * Veeramanikandan Raju, Anand Sawant, Igor Stoppa, Paul Walmsley,
+ +  * Richard Woodruff
+ +  */
+ + 
+ + #ifndef ASM_ARM_ARCH_OMAP_OMAP_PM_H
+ + #define ASM_ARM_ARCH_OMAP_OMAP_PM_H
+ + 
+ + #include <linux/device.h>
+ + #include <linux/cpufreq.h>
+ + #include <linux/clk.h>
+ + #include <linux/opp.h>
+ + 
+ + /*
+ +  * agent_id values for use with omap_pm_set_min_bus_tput():
+ +  *
+ +  * OCP_INITIATOR_AGENT is only valid for devices that can act as
+ +  * initiators -- it represents the device's L3 interconnect
+ +  * connection.  OCP_TARGET_AGENT represents the device's L4
+ +  * interconnect connection.
+ +  */
+ + #define OCP_TARGET_AGENT		1
+ + #define OCP_INITIATOR_AGENT		2
+ + 
+ + /**
+ +  * omap_pm_if_early_init - OMAP PM init code called before clock fw init
+ +  * @mpu_opp_table: array ptr to struct omap_opp for MPU
+ +  * @dsp_opp_table: array ptr to struct omap_opp for DSP
+ +  * @l3_opp_table : array ptr to struct omap_opp for CORE
+ +  *
+ +  * Initialize anything that must be configured before the clock
+ +  * framework starts.  The "_if_" is to avoid name collisions with the
+ +  * PM idle-loop code.
+ +  */
+ + int __init omap_pm_if_early_init(void);
+ + 
+ + /**
+ +  * omap_pm_if_init - OMAP PM init code called after clock fw init
+ +  *
+ +  * The main initialization code.  OPP tables are passed in here.  The
+ +  * "_if_" is to avoid name collisions with the PM idle-loop code.
+ +  */
+ + int __init omap_pm_if_init(void);
+ + 
+ + /**
+ +  * omap_pm_if_exit - OMAP PM exit code
+ +  *
+ +  * Exit code; currently unused.  The "_if_" is to avoid name
+ +  * collisions with the PM idle-loop code.
+ +  */
+ + void omap_pm_if_exit(void);
+ + 
+ + /*
+ +  * Device-driver-originated constraints (via board-*.c files, platform_data)
+ +  */
+ + 
+ + 
+ + /**
+ +  * omap_pm_set_max_mpu_wakeup_lat - set the maximum MPU wakeup latency
+ +  * @dev: struct device * requesting the constraint
+ +  * @t: maximum MPU wakeup latency in microseconds
+ +  *
+ +  * Request that the maximum interrupt latency for the MPU to be no
+ +  * greater than @t microseconds. "Interrupt latency" in this case is
+ +  * defined as the elapsed time from the occurrence of a hardware or
+ +  * timer interrupt to the time when the device driver's interrupt
+ +  * service routine has been entered by the MPU.
+ +  *
+ +  * It is intended that underlying PM code will use this information to
+ +  * determine what power state to put the MPU powerdomain into, and
+ +  * possibly the CORE powerdomain as well, since interrupt handling
+ +  * code currently runs from SDRAM.  Advanced PM or board*.c code may
+ +  * also configure interrupt controller priorities, OCP bus priorities,
+ +  * CPU speed(s), etc.
+ +  *
+ +  * This function will not affect device wakeup latency, e.g., time
+ +  * elapsed from when a device driver enables a hardware device with
+ +  * clk_enable(), to when the device is ready for register access or
+ +  * other use.  To control this device wakeup latency, use
+ +  * omap_pm_set_max_dev_wakeup_lat()
+ +  *
+ +  * Multiple calls to omap_pm_set_max_mpu_wakeup_lat() will replace the
+ +  * previous t value.  To remove the latency target for the MPU, call
+ +  * with t = -1.
+ +  *
+ +  * XXX This constraint will be deprecated soon in favor of the more
+ +  * general omap_pm_set_max_dev_wakeup_lat()
+ +  *
+ +  * Returns -EINVAL for an invalid argument, -ERANGE if the constraint
+ +  * is not satisfiable, or 0 upon success.
+ +  */
+ + int omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t);
+ + 
+ + 
+ + /**
+ +  * omap_pm_set_min_bus_tput - set minimum bus throughput needed by device
+ +  * @dev: struct device * requesting the constraint
+ +  * @tbus_id: interconnect to operate on (OCP_{INITIATOR,TARGET}_AGENT)
+ +  * @r: minimum throughput (in KiB/s)
+ +  *
+ +  * Request that the minimum data throughput on the OCP interconnect
+ +  * attached to device @dev interconnect agent @tbus_id be no less
+ +  * than @r KiB/s.
+ +  *
+ +  * It is expected that the OMAP PM or bus code will use this
+ +  * information to set the interconnect clock to run at the lowest
+ +  * possible speed that satisfies all current system users.  The PM or
+ +  * bus code will adjust the estimate based on its model of the bus, so
+ +  * device driver authors should attempt to specify an accurate
+ +  * quantity for their device use case, and let the PM or bus code
+ +  * overestimate the numbers as necessary to handle request/response
+ +  * latency, other competing users on the system, etc.  On OMAP2/3, if
+ +  * a driver requests a minimum L4 interconnect speed constraint, the
+ +  * code will also need to add an minimum L3 interconnect speed
+ +  * constraint,
+ +  *
+ +  * Multiple calls to omap_pm_set_min_bus_tput() will replace the
+ +  * previous rate value for this device.  To remove the interconnect
+ +  * throughput restriction for this device, call with r = 0.
+ +  *
+ +  * Returns -EINVAL for an invalid argument, -ERANGE if the constraint
+ +  * is not satisfiable, or 0 upon success.
+ +  */
+ + int omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r);
+ + 
+ + 
+ + /**
+ +  * omap_pm_set_max_dev_wakeup_lat - set the maximum device enable latency
+ +  * @req_dev: struct device * requesting the constraint, or NULL if none
+ +  * @dev: struct device * to set the constraint one
+ +  * @t: maximum device wakeup latency in microseconds
+ +  *
+ +  * Request that the maximum amount of time necessary for a device @dev
+ +  * to become accessible after its clocks are enabled should be no
+ +  * greater than @t microseconds.  Specifically, this represents the
+ +  * time from when a device driver enables device clocks with
+ +  * clk_enable(), to when the register reads and writes on the device
+ +  * will succeed.  This function should be called before clk_disable()
+ +  * is called, since the power state transition decision may be made
+ +  * during clk_disable().
+ +  *
+ +  * It is intended that underlying PM code will use this information to
+ +  * determine what power state to put the powerdomain enclosing this
+ +  * device into.
+ +  *
+ +  * Multiple calls to omap_pm_set_max_dev_wakeup_lat() will replace the
+ +  * previous wakeup latency values for this device.  To remove the
+ +  * wakeup latency restriction for this device, call with t = -1.
+ +  *
+ +  * Returns -EINVAL for an invalid argument, -ERANGE if the constraint
+ +  * is not satisfiable, or 0 upon success.
+ +  */
+ + int omap_pm_set_max_dev_wakeup_lat(struct device *req_dev, struct device *dev,
+ + 				   long t);
+ + 
+ + 
+ + /**
+ +  * omap_pm_set_max_sdma_lat - set the maximum system DMA transfer start latency
+ +  * @dev: struct device *
+ +  * @t: maximum DMA transfer start latency in microseconds
+ +  *
+ +  * Request that the maximum system DMA transfer start latency for this
+ +  * device 'dev' should be no greater than 't' microseconds.  "DMA
+ +  * transfer start latency" here is defined as the elapsed time from
+ +  * when a device (e.g., McBSP) requests that a system DMA transfer
+ +  * start or continue, to the time at which data starts to flow into
+ +  * that device from the system DMA controller.
+ +  *
+ +  * It is intended that underlying PM code will use this information to
+ +  * determine what power state to put the CORE powerdomain into.
+ +  *
+ +  * Since system DMA transfers may not involve the MPU, this function
+ +  * will not affect MPU wakeup latency.  Use set_max_cpu_lat() to do
+ +  * so.  Similarly, this function will not affect device wakeup latency
+ +  * -- use set_max_dev_wakeup_lat() to affect that.
+ +  *
+ +  * Multiple calls to set_max_sdma_lat() will replace the previous t
+ +  * value for this device.  To remove the maximum DMA latency for this
+ +  * device, call with t = -1.
+ +  *
+ +  * Returns -EINVAL for an invalid argument, -ERANGE if the constraint
+ +  * is not satisfiable, or 0 upon success.
+ +  */
+ + int omap_pm_set_max_sdma_lat(struct device *dev, long t);
+ + 
+ + 
+ + /**
+ +  * omap_pm_set_min_clk_rate - set minimum clock rate requested by @dev
+ +  * @dev: struct device * requesting the constraint
+ +  * @clk: struct clk * to set the minimum rate constraint on
+ +  * @r: minimum rate in Hz
+ +  *
+ +  * Request that the minimum clock rate on the device @dev's clk @clk
+ +  * be no less than @r Hz.
+ +  *
+ +  * It is expected that the OMAP PM code will use this information to
+ +  * find an OPP or clock setting that will satisfy this clock rate
+ +  * constraint, along with any other applicable system constraints on
+ +  * the clock rate or corresponding voltage, etc.
+ +  *
+ +  * omap_pm_set_min_clk_rate() differs from the clock code's
+ +  * clk_set_rate() in that it considers other constraints before taking
+ +  * any hardware action, and may change a system OPP rather than just a
+ +  * clock rate.  clk_set_rate() is intended to be a low-level
+ +  * interface.
+ +  *
+ +  * omap_pm_set_min_clk_rate() is easily open to abuse.  A better API
+ +  * would be something like "omap_pm_set_min_dev_performance()";
+ +  * however, there is no easily-generalizable concept of performance
+ +  * that applies to all devices.  Only a device (and possibly the
+ +  * device subsystem) has both the subsystem-specific knowledge, and
+ +  * the hardware IP block-specific knowledge, to translate a constraint
+ +  * on "touchscreen sampling accuracy" or "number of pixels or polygons
+ +  * rendered per second" to a clock rate.  This translation can be
+ +  * dependent on the hardware IP block's revision, or firmware version,
+ +  * and the driver is the only code on the system that has this
+ +  * information and can know how to translate that into a clock rate.
+ +  *
+ +  * The intended use-case for this function is for userspace or other
+ +  * kernel code to communicate a particular performance requirement to
+ +  * a subsystem; then for the subsystem to communicate that requirement
+ +  * to something that is meaningful to the device driver; then for the
+ +  * device driver to convert that requirement to a clock rate, and to
+ +  * then call omap_pm_set_min_clk_rate().
+ +  *
+ +  * Users of this function (such as device drivers) should not simply
+ +  * call this function with some high clock rate to ensure "high
+ +  * performance."  Rather, the device driver should take a performance
+ +  * constraint from its subsystem, such as "render at least X polygons
+ +  * per second," and use some formula or table to convert that into a
+ +  * clock rate constraint given the hardware type and hardware
+ +  * revision.  Device drivers or subsystems should not assume that they
+ +  * know how to make a power/performance tradeoff - some device use
+ +  * cases may tolerate a lower-fidelity device function for lower power
+ +  * consumption; others may demand a higher-fidelity device function,
+ +  * no matter what the power consumption.
+ +  *
+ +  * Multiple calls to omap_pm_set_min_clk_rate() will replace the
+ +  * previous rate value for the device @dev.  To remove the minimum clock
+ +  * rate constraint for the device, call with r = 0.
+ +  *
+ +  * Returns -EINVAL for an invalid argument, -ERANGE if the constraint
+ +  * is not satisfiable, or 0 upon success.
+ +  */
+ + int omap_pm_set_min_clk_rate(struct device *dev, struct clk *c, long r);
+ + 
+ + /*
+ +  * DSP Bridge-specific constraints
+ +  */
+ + 
+ + /**
+ +  * omap_pm_dsp_get_opp_table - get OPP->DSP clock frequency table
+ +  *
+ +  * Intended for use by DSPBridge.  Returns an array of OPP->DSP clock
+ +  * frequency entries.  The final item in the array should have .rate =
+ +  * .opp_id = 0.
+ +  */
+ + const struct omap_opp *omap_pm_dsp_get_opp_table(void);
+ + 
+ + /**
+ +  * omap_pm_dsp_set_min_opp - receive desired OPP target ID from DSP Bridge
+ +  * @opp_id: target DSP OPP ID
+ +  *
+ +  * Set a minimum OPP ID for the DSP.  This is intended to be called
+ +  * only from the DSP Bridge MPU-side driver.  Unfortunately, the only
+ +  * information that code receives from the DSP/BIOS load estimator is the
+ +  * target OPP ID; hence, this interface.  No return value.
+ +  */
+ + void omap_pm_dsp_set_min_opp(u8 opp_id);
+ + 
+ + /**
+ +  * omap_pm_dsp_get_opp - report the current DSP OPP ID
+ +  *
+ +  * Report the current OPP for the DSP.  Since on OMAP3, the DSP and
+ +  * MPU share a single voltage domain, the OPP ID returned back may
+ +  * represent a higher DSP speed than the OPP requested via
+ +  * omap_pm_dsp_set_min_opp().
+ +  *
+ +  * Returns the current VDD1 OPP ID, or 0 upon error.
+ +  */
+ + u8 omap_pm_dsp_get_opp(void);
+ + 
+ + 
+ + /*
+ +  * CPUFreq-originated constraint
+ +  *
+ +  * In the future, this should be handled by custom OPP clocktype
+ +  * functions.
+ +  */
+ + 
+ + /**
+ +  * omap_pm_cpu_get_freq_table - return a cpufreq_frequency_table array ptr
+ +  *
+ +  * Provide a frequency table usable by CPUFreq for the current chip/board.
+ +  * Returns a pointer to a struct cpufreq_frequency_table array or NULL
+ +  * upon error.
+ +  */
+ + struct cpufreq_frequency_table **omap_pm_cpu_get_freq_table(void);
+ + 
+ + /**
+ +  * omap_pm_cpu_set_freq - set the current minimum MPU frequency
+ +  * @f: MPU frequency in Hz
+ +  *
+ +  * Set the current minimum CPU frequency.  The actual CPU frequency
+ +  * used could end up higher if the DSP requested a higher OPP.
+ +  * Intended to be called by plat-omap/cpu_omap.c:omap_target().  No
+ +  * return value.
+ +  */
+ + void omap_pm_cpu_set_freq(unsigned long f);
+ + 
+ + /**
+ +  * omap_pm_cpu_get_freq - report the current CPU frequency
+ +  *
+ +  * Returns the current MPU frequency, or 0 upon error.
+ +  */
+ + unsigned long omap_pm_cpu_get_freq(void);
+ + 
+ + 
+ + /*
+ +  * Device context loss tracking
+ +  */
+ + 
+ + /**
+ +  * omap_pm_get_dev_context_loss_count - return count of times dev has lost ctx
+ +  * @dev: struct device *
+ +  *
+ +  * This function returns the number of times that the device @dev has
+ +  * lost its internal context.  This generally occurs on a powerdomain
+ +  * transition to OFF.  Drivers use this as an optimization to avoid restoring
+ +  * context if the device hasn't lost it.  To use, drivers should initially
+ +  * call this in their context save functions and store the result.  Early in
+ +  * the driver's context restore function, the driver should call this function
+ +  * again, and compare the result to the stored counter.  If they differ, the
+ +  * driver must restore device context.   If the number of context losses
+ +  * exceeds the maximum positive integer, the function will wrap to 0 and
+ +  * continue counting.  Returns the number of context losses for this device,
+ +  * or negative value upon error.
+ +  */
+ + int omap_pm_get_dev_context_loss_count(struct device *dev);
+ + 
+ + void omap_pm_enable_off_mode(void);
+ + void omap_pm_disable_off_mode(void);
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/omap-serial.h linux-3.2.1/arch/arm/plat-ckb/include/plat/omap-serial.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/omap-serial.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/omap-serial.h	2014-11-25 13:19:15.192042018 +0900
+ ***************
+ *** 0 ****
+ --- 1,141 ----
+ + /*
+ +  * Driver for OMAP-UART controller.
+ +  * Based on drivers/serial/8250.c
+ +  *
+ +  * Copyright (C) 2010 Texas Instruments.
+ +  *
+ +  * Authors:
+ +  *	Govindraj R	<govindraj.raja@ti.com>
+ +  *	Thara Gopinath	<thara@ti.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; either version 2 of the License, or
+ +  * (at your option) any later version.
+ +  */
+ + 
+ + #ifndef __OMAP_SERIAL_H__
+ + #define __OMAP_SERIAL_H__
+ + 
+ + #include <linux/serial_core.h>
+ + #include <linux/platform_device.h>
+ + #include <linux/pm_qos.h>
+ + 
+ + #include <plat/mux.h>
+ + 
+ + #define DRIVER_NAME	"omap_uart"
+ + 
+ + /*
+ +  * Use tty device name as ttyO, [O -> OMAP]
+ +  * in bootargs we specify as console=ttyO0 if uart1
+ +  * is used as console uart.
+ +  */
+ + #define OMAP_SERIAL_NAME	"ttyO"
+ + 
+ + #define OMAP_MODE13X_SPEED	230400
+ + 
+ + #define OMAP_UART_SCR_TX_EMPTY	0x08
+ + 
+ + /* WER = 0x7F
+ +  * Enable module level wakeup in WER reg
+ +  */
+ + #define OMAP_UART_WER_MOD_WKUP	0X7F
+ + 
+ + /* Enable XON/XOFF flow control on output */
+ + #define OMAP_UART_SW_TX		0x04
+ + 
+ + /* Enable XON/XOFF flow control on input */
+ + #define OMAP_UART_SW_RX		0x04
+ + 
+ + #define OMAP_UART_SYSC_RESET	0X07
+ + #define OMAP_UART_TCR_TRIG	0X0F
+ + #define OMAP_UART_SW_CLR	0XF0
+ + #define OMAP_UART_FIFO_CLR	0X06
+ + 
+ + #define OMAP_UART_DMA_CH_FREE	-1
+ + 
+ + #define OMAP_MAX_HSUART_PORTS	6
+ + 
+ + #define MSR_SAVE_FLAGS		UART_MSR_ANY_DELTA
+ + 
+ + #define UART_ERRATA_i202_MDR1_ACCESS	BIT(0)
+ + #define UART_ERRATA_i291_DMA_FORCEIDLE	BIT(1)
+ + 
+ + struct omap_uart_port_info {
+ + 	bool			dma_enabled;	/* To specify DMA Mode */
+ + 	unsigned int		uartclk;	/* UART clock rate */
+ + 	upf_t			flags;		/* UPF_* flags */
+ + 	u32			errata;
+ + 	unsigned int		dma_rx_buf_size;
+ + 	unsigned int		dma_rx_timeout;
+ + 	unsigned int		autosuspend_timeout;
+ + 	unsigned int		dma_rx_poll_rate;
+ + 
+ + 	int (*get_context_loss_count)(struct device *);
+ + 	void (*set_forceidle)(struct platform_device *);
+ + 	void (*set_noidle)(struct platform_device *);
+ + 	void (*enable_wakeup)(struct platform_device *, bool);
+ + };
+ + 
+ + struct uart_omap_dma {
+ + 	u8			uart_dma_tx;
+ + 	u8			uart_dma_rx;
+ + 	int			rx_dma_channel;
+ + 	int			tx_dma_channel;
+ + 	dma_addr_t		rx_buf_dma_phys;
+ + 	dma_addr_t		tx_buf_dma_phys;
+ + 	unsigned int		uart_base;
+ + 	/*
+ + 	 * Buffer for rx dma.It is not required for tx because the buffer
+ + 	 * comes from port structure.
+ + 	 */
+ + 	unsigned char		*rx_buf;
+ + 	unsigned int		prev_rx_dma_pos;
+ + 	int			tx_buf_size;
+ + 	int			tx_dma_used;
+ + 	int			rx_dma_used;
+ + 	spinlock_t		tx_lock;
+ + 	spinlock_t		rx_lock;
+ + 	/* timer to poll activity on rx dma */
+ + 	struct timer_list	rx_timer;
+ + 	unsigned int		rx_buf_size;
+ + 	unsigned int		rx_poll_rate;
+ + 	unsigned int		rx_timeout;
+ + };
+ + 
+ + struct uart_omap_port {
+ + 	struct uart_port	port;
+ + 	struct uart_omap_dma	uart_dma;
+ + 	struct platform_device	*pdev;
+ + 
+ + 	unsigned char		ier;
+ + 	unsigned char		lcr;
+ + 	unsigned char		mcr;
+ + 	unsigned char		fcr;
+ + 	unsigned char		efr;
+ + 	unsigned char		dll;
+ + 	unsigned char		dlh;
+ + 	unsigned char		mdr1;
+ + 	unsigned char		scr;
+ + 
+ + 	int			use_dma;
+ + 	/*
+ + 	 * Some bits in registers are cleared on a read, so they must
+ + 	 * be saved whenever the register is read but the bits will not
+ + 	 * be immediately processed.
+ + 	 */
+ + 	unsigned int		lsr_break_flag;
+ + 	unsigned char		msr_saved_flags;
+ + 	char			name[20];
+ + 	unsigned long		port_activity;
+ + 	u32			context_loss_cnt;
+ + 	u32			errata;
+ + 	u8			wakeups_enabled;
+ + 
+ + 	struct pm_qos_request	pm_qos_request;
+ + 	u32			latency;
+ + 	u32			calc_latency;
+ + 	struct work_struct	qos_work;
+ + };
+ + 
+ + #endif /* __OMAP_SERIAL_H__ */
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/param.h linux-3.2.1/arch/arm/plat-ckb/include/plat/param.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/param.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/param.h	2014-11-25 13:19:15.192042018 +0900
+ ***************
+ *** 0 ****
+ --- 1,8 ----
+ + /*
+ +  *  arch/arm/plat-omap/include/mach/param.h
+ +  *
+ +  */
+ + 
+ + #ifdef CONFIG_OMAP_32K_TIMER_HZ
+ + #define HZ	CONFIG_OMAP_32K_TIMER_HZ
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/prcm.h linux-3.2.1/arch/arm/plat-ckb/include/plat/prcm.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/prcm.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/prcm.h	2014-11-25 13:19:15.192042018 +0900
+ ***************
+ *** 0 ****
+ --- 1,37 ----
+ + /*
+ +  * arch/arm/plat-omap/include/mach/prcm.h
+ +  *
+ +  * Access definations for use in OMAP24XX clock and power management
+ +  *
+ +  * Copyright (C) 2005 Texas Instruments, Inc.
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; either version 2 of the License, or
+ +  * (at your option) any later version.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ +  *
+ +  * XXX This file is deprecated.  The PRCM is an OMAP2+-only subsystem,
+ +  * so this file doesn't belong in plat-omap/include/plat.  Please
+ +  * do not add anything new to this file.
+ +  */
+ + 
+ + #ifndef __ASM_ARM_ARCH_OMAP_PRCM_H
+ + #define __ASM_ARM_ARCH_OMAP_PRCM_H
+ + 
+ + u32 omap_prcm_get_reset_sources(void);
+ + int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
+ + 			 const char *name);
+ + 
+ + #endif
+ + 
+ + 
+ + 
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/sdrc.h linux-3.2.1/arch/arm/plat-ckb/include/plat/sdrc.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/sdrc.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/sdrc.h	2014-11-25 13:19:15.196032475 +0900
+ ***************
+ *** 0 ****
+ --- 1,131 ----
+ + #ifndef ____ASM_ARCH_SDRC_H
+ + #define ____ASM_ARCH_SDRC_H
+ + 
+ + /*
+ +  * OMAP2/3 SDRC/SMS register definitions
+ +  *
+ +  * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ +  * Copyright (C) 2007-2008 Nokia Corporation
+ +  *
+ +  * Tony Lindgren
+ +  * Paul Walmsley
+ +  * Richard Woodruff
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #include <mach/io.h>
+ + 
+ + /* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
+ + 
+ + #define SDRC_SYSCONFIG		0x010
+ + #define SDRC_CS_CFG		0x040
+ + #define SDRC_SHARING		0x044
+ + #define SDRC_ERR_TYPE		0x04C
+ + #define SDRC_DLLA_CTRL		0x060
+ + #define SDRC_DLLA_STATUS	0x064
+ + #define SDRC_DLLB_CTRL		0x068
+ + #define SDRC_DLLB_STATUS	0x06C
+ + #define SDRC_POWER		0x070
+ + #define SDRC_MCFG_0		0x080
+ + #define SDRC_MR_0		0x084
+ + #define SDRC_EMR2_0		0x08c
+ + #define SDRC_ACTIM_CTRL_A_0	0x09c
+ + #define SDRC_ACTIM_CTRL_B_0	0x0a0
+ + #define SDRC_RFR_CTRL_0		0x0a4
+ + #define SDRC_MANUAL_0		0x0a8
+ + #define SDRC_MCFG_1		0x0B0
+ + #define SDRC_MR_1		0x0B4
+ + #define SDRC_EMR2_1		0x0BC
+ + #define SDRC_ACTIM_CTRL_A_1	0x0C4
+ + #define SDRC_ACTIM_CTRL_B_1	0x0C8
+ + #define SDRC_RFR_CTRL_1		0x0D4
+ + #define SDRC_MANUAL_1		0x0D8
+ + 
+ + #define SDRC_POWER_AUTOCOUNT_SHIFT	8
+ + #define SDRC_POWER_AUTOCOUNT_MASK	(0xffff << SDRC_POWER_AUTOCOUNT_SHIFT)
+ + #define SDRC_POWER_CLKCTRL_SHIFT	4
+ + #define SDRC_POWER_CLKCTRL_MASK		(0x3 << SDRC_POWER_CLKCTRL_SHIFT)
+ + #define SDRC_SELF_REFRESH_ON_AUTOCOUNT	(0x2 << SDRC_POWER_CLKCTRL_SHIFT)
+ + 
+ + /*
+ +  * These values represent the number of memory clock cycles between
+ +  * autorefresh initiation.  They assume 1 refresh per 64 ms (JEDEC), 8192
+ +  * rows per device, and include a subtraction of a 50 cycle window in the
+ +  * event that the autorefresh command is delayed due to other SDRC activity.
+ +  * The '| 1' sets the ARE field to send one autorefresh when the autorefresh
+ +  * counter reaches 0.
+ +  *
+ +  * These represent optimal values for common parts, it won't work for all.
+ +  * As long as you scale down, most parameters are still work, they just
+ +  * become sub-optimal. The RFR value goes in the opposite direction. If you
+ +  * don't adjust it down as your clock period increases the refresh interval
+ +  * will not be met. Setting all parameters for complete worst case may work,
+ +  * but may cut memory performance by 2x. Due to errata the DLLs need to be
+ +  * unlocked and their value needs run time calibration.	A dynamic call is
+ +  * need for that as no single right value exists acorss production samples.
+ +  *
+ +  * Only the FULL speed values are given. Current code is such that rate
+ +  * changes must be made at DPLLoutx2. The actual value adjustment for low
+ +  * frequency operation will be handled by omap_set_performance()
+ +  *
+ +  * By having the boot loader boot up in the fastest L4 speed available likely
+ +  * will result in something which you can switch between.
+ +  */
+ + #define SDRC_RFR_CTRL_165MHz	(0x00044c00 | 1)
+ + #define SDRC_RFR_CTRL_133MHz	(0x0003de00 | 1)
+ + #define SDRC_RFR_CTRL_100MHz	(0x0002da01 | 1)
+ + #define SDRC_RFR_CTRL_110MHz	(0x0002da01 | 1) /* Need to calc */
+ + #define SDRC_RFR_CTRL_BYPASS	(0x00005000 | 1) /* Need to calc */
+ + 
+ + 
+ + /* SMS register offsets - read/write with sms_{read,write}_reg() */
+ + 
+ + #define SMS_SYSCONFIG			0x010
+ + #define SMS_ROT_CONTROL(context)	(0x180 + 0x10 * context)
+ + #define SMS_ROT_SIZE(context)		(0x184 + 0x10 * context)
+ + #define SMS_ROT_PHYSICAL_BA(context)	(0x188 + 0x10 * context)
+ + /* REVISIT: fill in other SMS registers here */
+ + 
+ + 
+ + #ifndef __ASSEMBLER__
+ + 
+ + /**
+ +  * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate
+ +  * @rate: SDRC clock rate (in Hz)
+ +  * @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate
+ +  * @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate
+ +  * @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate
+ +  * @mr: Value to program to SDRC_MR for this rate
+ +  *
+ +  * This structure holds a pre-computed set of register values for the
+ +  * SDRC for a given SDRC clock rate and SDRAM chip.  These are
+ +  * intended to be pre-computed and specified in an array in the board-*.c
+ +  * files.  The structure is keyed off the 'rate' field.
+ +  */
+ + struct omap_sdrc_params {
+ + 	unsigned long rate;
+ + 	u32 actim_ctrla;
+ + 	u32 actim_ctrlb;
+ + 	u32 rfr_ctrl;
+ + 	u32 mr;
+ + };
+ + 
+ + void omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
+ + 			    struct omap_sdrc_params *sdrc_cs1);
+ + 
+ + int omap2_sdrc_get_params(unsigned long r,
+ + 			  struct omap_sdrc_params **sdrc_cs0,
+ + 			  struct omap_sdrc_params **sdrc_cs1);
+ + void omap2_sms_save_context(void);
+ + void omap2_sms_restore_context(void);
+ + 
+ + void omap2_sms_write_rot_control(u32 val, unsigned ctx);
+ + void omap2_sms_write_rot_size(u32 val, unsigned ctx);
+ + void omap2_sms_write_rot_physical_ba(u32 val, unsigned ctx);
+ + 
+ + #endif  /* __ASSEMBLER__ */
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/serial.h linux-3.2.1/arch/arm/plat-ckb/include/plat/serial.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/serial.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/serial.h	2014-11-25 13:19:15.196032475 +0900
+ ***************
+ *** 0 ****
+ --- 1,129 ----
+ + /*
+ +  * arch/arm/plat-omap/include/mach/serial.h
+ +  *
+ +  * Copyright (C) 2009 Texas Instruments
+ +  * Addded OMAP4 support- Santosh Shilimkar <santosh.shilimkar@ti.com>
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #ifndef __ASM_ARCH_SERIAL_H
+ + #define __ASM_ARCH_SERIAL_H
+ + 
+ + #include <linux/init.h>
+ + 
+ + /*
+ +  * Memory entry used for the DEBUG_LL UART configuration, relative to
+ +  * start of RAM. See also uncompress.h and debug-macro.S.
+ +  *
+ +  * Note that using a memory location for storing the UART configuration
+ +  * has at least two limitations:
+ +  *
+ +  * 1. Kernel uncompress code cannot overlap OMAP_UART_INFO as the
+ +  *    uncompress code could then partially overwrite itself
+ +  * 2. We assume printascii is called at least once before paging_init,
+ +  *    and addruart has a chance to read OMAP_UART_INFO
+ +  */
+ + #define OMAP_UART_INFO_OFS	0x3ffc
+ + 
+ + /* OMAP1 serial ports */
+ + #define OMAP1_UART1_BASE	0xfffb0000
+ + #define OMAP1_UART2_BASE	0xfffb0800
+ + #define OMAP1_UART3_BASE	0xfffb9800
+ + 
+ + /* OMAP2 serial ports */
+ + #define OMAP2_UART1_BASE	0x4806a000
+ + #define OMAP2_UART2_BASE	0x4806c000
+ + #define OMAP2_UART3_BASE	0x4806e000
+ + 
+ + /* OMAP3 serial ports */
+ + #define OMAP3_UART1_BASE	OMAP2_UART1_BASE
+ + #define OMAP3_UART2_BASE	OMAP2_UART2_BASE
+ + #define OMAP3_UART3_BASE	0x49020000
+ + #define OMAP3_UART4_BASE	0x49042000	/* Only on 36xx */
+ + #define OMAP3_UART4_AM35XX_BASE	0x4809E000	/* Only on AM35xx */
+ + 
+ + /* OMAP4 serial ports */
+ + #define OMAP4_UART1_BASE	OMAP2_UART1_BASE
+ + #define OMAP4_UART2_BASE	OMAP2_UART2_BASE
+ + #define OMAP4_UART3_BASE	0x48020000
+ + #define OMAP4_UART4_BASE	0x4806e000
+ + 
+ + /* TI81XX serial ports */
+ + #define TI81XX_UART1_BASE	0x48020000
+ + #define TI81XX_UART2_BASE	0x48022000
+ + #define TI81XX_UART3_BASE	0x48024000
+ + 
+ + /* AM3505/3517 UART4 */
+ + #define AM35XX_UART4_BASE	0x4809E000	/* Only on AM3505/3517 */
+ + 
+ + /* AM33XX serial port */
+ + #define AM33XX_UART1_BASE	0x44E09000
+ + #define AM33XX_UART2_BASE	0x48022000
+ + #define AM33XX_UART3_BASE	0x48024000
+ + #define AM33XX_UART4_BASE	0x481A6000
+ + #define AM33XX_UART5_BASE	0x481A8000
+ + #define AM33XX_UART6_BASE	0x481AA000
+ + 
+ + /* External port on Zoom2/3 */
+ + #define ZOOM_UART_BASE		0x10000000
+ + #define ZOOM_UART_VIRT		0xfa400000
+ + 
+ + #define OMAP_PORT_SHIFT		2
+ + #define OMAP7XX_PORT_SHIFT	0
+ + #define ZOOM_PORT_SHIFT		1
+ + 
+ + #define OMAP1510_BASE_BAUD	(12000000/16)
+ + #define OMAP16XX_BASE_BAUD	(48000000/16)
+ + #define OMAP24XX_BASE_BAUD	(48000000/16)
+ + 
+ + /*
+ +  * DEBUG_LL port encoding stored into the UART1 scratchpad register by
+ +  * decomp_setup in uncompress.h
+ +  */
+ + #define OMAP1UART1		11
+ + #define OMAP1UART2		12
+ + #define OMAP1UART3		13
+ + #define OMAP2UART1		21
+ + #define OMAP2UART2		22
+ + #define OMAP2UART3		23
+ + #define OMAP3UART1		OMAP2UART1
+ + #define OMAP3UART2		OMAP2UART2
+ + #define OMAP3UART3		33
+ + #define OMAP3UART4		34		/* Only on 36xx */
+ + #define OMAP4UART1		OMAP2UART1
+ + #define OMAP4UART2		OMAP2UART2
+ + #define OMAP4UART3		43
+ + #define OMAP4UART4		44
+ + #define TI81XXUART1		81
+ + #define TI81XXUART2		82
+ + #define TI81XXUART3		83
+ + #define AM33XXUART1		84
+ + #define AM33XXUART4		85
+ + #define ZOOM_UART		95		/* Only on zoom2/3 */
+ + 
+ + /* This is only used by 8250.c for omap1510 */
+ + #define is_omap_port(pt)	({int __ret = 0;			\
+ + 			if ((pt)->port.mapbase == OMAP1_UART1_BASE ||	\
+ + 			    (pt)->port.mapbase == OMAP1_UART2_BASE ||	\
+ + 			    (pt)->port.mapbase == OMAP1_UART3_BASE)	\
+ + 				__ret = 1;				\
+ + 			__ret;						\
+ + 			})
+ + 
+ + #ifndef __ASSEMBLER__
+ + 
+ + struct omap_board_data;
+ + struct omap_uart_port_info;
+ + 
+ + extern void omap_serial_init(void);
+ + extern int omap_uart_can_sleep(void);
+ + extern void omap_serial_board_init(struct omap_uart_port_info *platform_data);
+ + extern void omap_serial_init_port(struct omap_board_data *bdata,
+ + 		struct omap_uart_port_info *platform_data);
+ + #endif
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/smartreflex.h linux-3.2.1/arch/arm/plat-ckb/include/plat/smartreflex.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/smartreflex.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/smartreflex.h	2014-11-25 13:19:15.196032475 +0900
+ ***************
+ *** 0 ****
+ --- 1,431 ----
+ + /*
+ +  * OMAP Smartreflex Defines and Routines
+ +  *
+ +  * Author: Thara Gopinath	<thara@ti.com>
+ +  *
+ +  * Copyright (C) 2010 Texas Instruments, Inc.
+ +  * Thara Gopinath <thara@ti.com>
+ +  *
+ +  * Copyright (C) 2008 Nokia Corporation
+ +  * Kalle Jokiniemi
+ +  *
+ +  * Copyright (C) 2007 Texas Instruments, Inc.
+ +  * Lesly A M <x0080970@ti.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #ifndef __ASM_ARM_OMAP_SMARTREFLEX_H
+ + #define __ASM_ARM_OMAP_SMARTREFLEX_H
+ + 
+ + #include <linux/platform_device.h>
+ + #include <plat/voltage.h>
+ + 
+ + /*
+ +  * Different Smartreflex IPs version. The v1 is the 65nm version used in
+ +  * OMAP3430. The v2 is the update for the 45nm version of the IP
+ +  * used in OMAP3630 and OMAP4430
+ +  */
+ + #define SR_TYPE_V1	1
+ + #define SR_TYPE_V2	2
+ + 
+ + /* SMART REFLEX REG ADDRESS OFFSET */
+ + #define SRCONFIG		0x00
+ + #define SRSTATUS		0x04
+ + #define SENVAL			0x08
+ + #define SENMIN			0x0C
+ + #define SENMAX			0x10
+ + #define SENAVG			0x14
+ + #define AVGWEIGHT		0x18
+ + #define NVALUERECIPROCAL	0x1c
+ + #define SENERROR_V1		0x20
+ + #define ERRCONFIG_V1		0x24
+ + #define IRQ_EOI			0x20
+ + #define IRQSTATUS_RAW		0x24
+ + #define IRQSTATUS		0x28
+ + #define IRQENABLE_SET		0x2C
+ + #define IRQENABLE_CLR		0x30
+ + #define SENERROR_V2		0x34
+ + #define ERRCONFIG_V2		0x38
+ + 
+ + /* Bit/Shift Positions */
+ + 
+ + /* SRCONFIG */
+ + #define SRCONFIG_ACCUMDATA_SHIFT	22
+ + #define SRCONFIG_SRCLKLENGTH_SHIFT	12
+ + #define SRCONFIG_SENNENABLE_V1_SHIFT	5
+ + #define SRCONFIG_SENPENABLE_V1_SHIFT	3
+ + #define SRCONFIG_SENNENABLE_V2_SHIFT	1
+ + #define SRCONFIG_SENPENABLE_V2_SHIFT	0
+ + #define SRCONFIG_CLKCTRL_SHIFT		0
+ + 
+ + #define SRCONFIG_ACCUMDATA_MASK		(0x3ff << 22)
+ + 
+ + #define SRCONFIG_SRENABLE		BIT(11)
+ + #define SRCONFIG_SENENABLE		BIT(10)
+ + #define SRCONFIG_ERRGEN_EN		BIT(9)
+ + #define SRCONFIG_MINMAXAVG_EN		BIT(8)
+ + #define SRCONFIG_DELAYCTRL		BIT(2)
+ + 
+ + /* AVGWEIGHT */
+ + #define AVGWEIGHT_SENPAVGWEIGHT_SHIFT	2
+ + #define AVGWEIGHT_SENNAVGWEIGHT_SHIFT	0
+ + 
+ + /* NVALUERECIPROCAL */
+ + #define NVALUERECIPROCAL_SENPGAIN_SHIFT	20
+ + #define NVALUERECIPROCAL_SENNGAIN_SHIFT	16
+ + #define NVALUERECIPROCAL_RNSENP_SHIFT	8
+ + #define NVALUERECIPROCAL_RNSENN_SHIFT	0
+ + 
+ + /* ERRCONFIG */
+ + #define ERRCONFIG_ERRWEIGHT_SHIFT	16
+ + #define ERRCONFIG_ERRMAXLIMIT_SHIFT	8
+ + #define ERRCONFIG_ERRMINLIMIT_SHIFT	0
+ + 
+ + #define SR_ERRWEIGHT_MASK		(0x07 << 16)
+ + #define SR_ERRMAXLIMIT_MASK		(0xff << 8)
+ + #define SR_ERRMINLIMIT_MASK		(0xff << 0)
+ + 
+ + #define ERRCONFIG_VPBOUNDINTEN_V1	BIT(31)
+ + #define ERRCONFIG_VPBOUNDINTST_V1	BIT(30)
+ + #define	ERRCONFIG_MCUACCUMINTEN		BIT(29)
+ + #define ERRCONFIG_MCUACCUMINTST		BIT(28)
+ + #define	ERRCONFIG_MCUVALIDINTEN		BIT(27)
+ + #define ERRCONFIG_MCUVALIDINTST		BIT(26)
+ + #define ERRCONFIG_MCUBOUNDINTEN		BIT(25)
+ + #define	ERRCONFIG_MCUBOUNDINTST		BIT(24)
+ + #define	ERRCONFIG_MCUDISACKINTEN	BIT(23)
+ + #define ERRCONFIG_VPBOUNDINTST_V2	BIT(23)
+ + #define ERRCONFIG_MCUDISACKINTST	BIT(22)
+ + #define ERRCONFIG_VPBOUNDINTEN_V2	BIT(22)
+ + 
+ + #define ERRCONFIG_STATUS_V1_MASK	(ERRCONFIG_VPBOUNDINTST_V1 | \
+ + 					ERRCONFIG_MCUACCUMINTST | \
+ + 					ERRCONFIG_MCUVALIDINTST | \
+ + 					ERRCONFIG_MCUBOUNDINTST | \
+ + 					ERRCONFIG_MCUDISACKINTST)
+ + /* IRQSTATUS */
+ + #define IRQSTATUS_MCUACCUMINT		BIT(3)
+ + #define IRQSTATUS_MCVALIDINT		BIT(2)
+ + #define IRQSTATUS_MCBOUNDSINT		BIT(1)
+ + #define IRQSTATUS_MCUDISABLEACKINT	BIT(0)
+ + 
+ + /* IRQENABLE_SET and IRQENABLE_CLEAR */
+ + #define IRQENABLE_MCUACCUMINT		BIT(3)
+ + #define IRQENABLE_MCUVALIDINT		BIT(2)
+ + #define IRQENABLE_MCUBOUNDSINT		BIT(1)
+ + #define IRQENABLE_MCUDISABLEACKINT	BIT(0)
+ + 
+ + /* Common Bit values */
+ + 
+ + #define SRCLKLENGTH_12MHZ_SYSCLK	0x3c
+ + #define SRCLKLENGTH_13MHZ_SYSCLK	0x41
+ + #define SRCLKLENGTH_19MHZ_SYSCLK	0x60
+ + #define SRCLKLENGTH_26MHZ_SYSCLK	0x82
+ + #define SRCLKLENGTH_38MHZ_SYSCLK	0xC0
+ + 
+ + /*
+ +  * 3430 specific values. Maybe these should be passed from board file or
+ +  * pmic structures.
+ +  */
+ + #define OMAP3430_SR_ACCUMDATA		0x1f4
+ + 
+ + #define OMAP3430_SR1_SENPAVGWEIGHT	0x03
+ + #define OMAP3430_SR1_SENNAVGWEIGHT	0x03
+ + 
+ + #define OMAP3430_SR2_SENPAVGWEIGHT	0x01
+ + #define OMAP3430_SR2_SENNAVGWEIGHT	0x01
+ + 
+ + #define OMAP3430_SR_ERRWEIGHT		0x04
+ + #define OMAP3430_SR_ERRMAXLIMIT		0x02
+ + 
+ + /**
+ +  * struct omap_sr_pmic_data - Strucutre to be populated by pmic code to pass
+ +  *				pmic specific info to smartreflex driver
+ +  *
+ +  * @sr_pmic_init:	API to initialize smartreflex on the PMIC side.
+ +  */
+ + struct omap_sr_pmic_data {
+ + 	void (*sr_pmic_init) (void);
+ + };
+ + 
+ + #ifdef CONFIG_OMAP_SMARTREFLEX
+ + /*
+ +  * The smart reflex driver supports CLASS1 CLASS2 and CLASS3 SR.
+ +  * The smartreflex class driver should pass the class type.
+ +  * Should be used to populate the class_type field of the
+ +  * omap_smartreflex_class_data structure.
+ +  */
+ + #define SR_CLASS1	0x1
+ + #define SR_CLASS2	0x2
+ + #define SR_CLASS3	0x3
+ + 
+ + /**
+ +  * struct omap_sr_class_data - Smartreflex class driver info
+ +  *
+ +  * @enable:		API to enable a particular class smaartreflex.
+ +  * @disable:		API to disable a particular class smartreflex.
+ +  * @configure:		API to configure a particular class smartreflex.
+ +  * @notify:		API to notify the class driver about an event in SR.
+ +  *			Not needed for class3.
+ +  * @notify_flags:	specify the events to be notified to the class driver
+ +  * @class_type:		specify which smartreflex class.
+ +  *			Can be used by the SR driver to take any class
+ +  *			based decisions.
+ +  */
+ + struct omap_sr_class_data {
+ + 	int (*enable)(struct voltagedomain *voltdm);
+ + 	int (*disable)(struct voltagedomain *voltdm, int is_volt_reset);
+ + 	int (*configure)(struct voltagedomain *voltdm);
+ + 	int (*notify)(struct voltagedomain *voltdm, u32 status);
+ + 	u8 notify_flags;
+ + 	u8 class_type;
+ + };
+ + 
+ + /**
+ +  * struct omap_sr_nvalue_table	- Smartreflex n-target value info
+ +  *
+ +  * @efuse_offs:	The offset of the efuse where n-target values are stored.
+ +  * @nvalue:	The n-target value.
+ +  */
+ + struct omap_sr_nvalue_table {
+ + 	u32 efuse_offs;
+ + 	u32 nvalue;
+ + };
+ + 
+ + /**
+ +  * struct omap_sr_data - Smartreflex platform data.
+ +  *
+ +  * @ip_type:		Smartreflex IP type.
+ +  * @senp_mod:		SENPENABLE value for the sr
+ +  * @senn_mod:		SENNENABLE value for sr
+ +  * @nvalue_count:	Number of distinct nvalues in the nvalue table
+ +  * @enable_on_init:	whether this sr module needs to enabled at
+ +  *			boot up or not.
+ +  * @nvalue_table:	table containing the  efuse offsets and nvalues
+ +  *			corresponding to them.
+ +  * @voltdm:		Pointer to the voltage domain associated with the SR
+ +  */
+ + struct omap_sr_data {
+ + 	int				ip_type;
+ + 	u32				senp_mod;
+ + 	u32				senn_mod;
+ + 	int				nvalue_count;
+ + 	bool				enable_on_init;
+ + 	struct omap_sr_nvalue_table	*nvalue_table;
+ + 	struct voltagedomain		*voltdm;
+ + };
+ + 
+ + /* Smartreflex module enable/disable interface */
+ + void omap_sr_enable(struct voltagedomain *voltdm);
+ + void omap_sr_disable(struct voltagedomain *voltdm);
+ + void omap_sr_disable_reset_volt(struct voltagedomain *voltdm);
+ + 
+ + /* API to register the pmic specific data with the smartreflex driver. */
+ + void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data);
+ + 
+ + /* Smartreflex driver hooks to be called from Smartreflex class driver */
+ + int sr_enable(struct voltagedomain *voltdm, unsigned long volt);
+ + void sr_disable(struct voltagedomain *voltdm);
+ + int sr_configure_errgen(struct voltagedomain *voltdm);
+ + int sr_configure_minmax(struct voltagedomain *voltdm);
+ + 
+ + /* API to register the smartreflex class driver with the smartreflex driver */
+ + int sr_register_class(struct omap_sr_class_data *class_data);
+ + #else
+ + 
+ + #ifdef CONFIG_AM33XX_SMARTREFLEX
+ + 
+ + #define SR_CORE                         (0)
+ + #define SR_MPU                          (1)
+ + #define SRCLKLENGTH_125MHZ_SYSCLK	(0x78 << 12)
+ + #define GAIN_MAXLIMIT                   (16)
+ + #define R_MAXLIMIT                      (256)
+ + #define MAX_SENSORS                     2
+ + /* GG: eventually this should be determined at runtime */
+ + #define AM33XX_OPP_COUNT                4
+ + 
+ + /**
+ +  * struct am33xx_sr_opp_data	- Smartreflex data per OPP
+ +  * @efuse_offs:		The offset of the efuse where n-target values are
+ +  *			stored.
+ +  * @nvalue:             NTarget as stored in EFUSE.
+ +  * @adj_nvalue:         Adjusted NTarget (adjusted by margin)
+ +  * @e2v_gain:		Error to voltage gain for changing the percentage
+ +  *			error into voltage delta
+ +  * @err_weight:		Average sensor error weight
+ +  * @err_minlimit:	Minimum error limit of the sensor
+ +  * @err_maxlimit:	Maximum error limit of the sensor
+ +  * @margin:             Voltage margin to apply
+ +  * @nominal_volt:       Nominal voltage for this OPP
+ +  * @frequency:          Defined frequency for this OPP (in KHz)
+ +  */
+ + struct am33xx_sr_opp_data {
+ + 	u32	efuse_offs;
+ +         u32     nvalue;
+ +         u32     adj_nvalue;
+ + 	s32	e2v_gain;
+ + 	u32	err_weight;
+ + 	u32	err_minlimit;
+ + 	u32	err_maxlimit;
+ +         s32     margin;
+ +         u32     nominal_volt; /* nominal_volt and frequency may be removed
+ +                                  once am33xx voltdm layer works */
+ +         u32     frequency;
+ +         u32     opp_id;
+ + };
+ + 
+ + /**
+ +  * struct am33xx_sr_sdata	- Smartreflex sensors data
+ +  * @sr_opp_data:	Pointer to data structure containing per OPP data
+ +  *                      for this SR module.
+ +  * @no_of_opps:         Number of OPP's supported for this sensor -
+ +  *                       determined dynamically when possible.
+ +  * @default_opp:        Defines the opp to use on startup if OPP is fixed
+ +  *                       or cannot be determined dynamically.
+ +  * @senn_mod:		Enable bit for N sensor
+ +  * @senp_mod:		Enable bit for P sensor
+ +  */
+ + struct am33xx_sr_sdata {
+ + 	struct am33xx_sr_opp_data *sr_opp_data;
+ +         u32     no_of_opps;
+ +         u32     default_opp;
+ + 	u32	senn_mod;
+ + 	u32	senp_mod;
+ + };
+ + 
+ + struct am33xx_sr_sensor {
+ +         u32                             sr_id;
+ + 	u32			        irq;
+ + 	u32			        irq_status;
+ + 	u32			        senn_en;
+ + 	u32			        senp_en;
+ + 	char			        *name;
+ +         char                            *reg_name;
+ + 	void __iomem		        *base;
+ +         int				init_volt_mv;
+ +         int                             curr_opp;
+ +         u32                             no_of_opps;
+ +         struct delayed_work             work_reenable;
+ +         struct regulator		*reg;
+ +         struct am33xx_sr_opp_data       opp_data[AM33XX_OPP_COUNT];
+ + 	struct clk		        *fck;
+ +         struct voltagedomain		*voltdm;
+ +         struct omap_volt_data           *volt_data;
+ + };
+ + 
+ + struct am33xx_sr {
+ + 	u32				autocomp_active;
+ + 	u32				sens_per_vd;
+ +         u32                             no_of_sens;
+ +         u32                             no_of_vds;
+ + 	u32				ip_type;
+ +         u32				irq_delay;
+ +         u32                             disabled_by_user;
+ + 	int				uvoltage_step_size;
+ +         char                            *res_name[MAX_SENSORS];
+ + #ifdef CONFIG_CPU_FREQ
+ + 	struct notifier_block	        freq_transition;
+ + #endif
+ + 	/*struct work_struct		work;*/
+ +         struct delayed_work             work;
+ + 	struct sr_platform_data		*sr_data;
+ + 	struct am33xx_sr_sensor		sen[MAX_SENSORS];
+ + 	struct platform_device		*pdev;
+ + };
+ + 
+ + /**
+ +  * struct am33xx_sr_platform_data - Smartreflex platform data.
+ +  * @sr_sdata:		SR per sensor details, contains the efuse off-sets,
+ +  *			error to voltage gain factor, minimum error limits
+ +  * @vd_name:		Name of the voltage domain.
+ +  * @ip_type:		Smartreflex IP type, class1 or class2 or class3.
+ +  * @irq_delay:          Amount of time required for changed voltage to settle.
+ +  * @no_of_vds:		Number of voltage domains to which SR applicable
+ +  * @no_of_sens:		Number of SR sensors used to monitor the device
+ +  *			performance, temp etc...
+ +  * @vstep_size_uv:	PMIC voltage step size in micro volts
+ +  * @enable_on_init:	whether this sr module needs to enabled at
+ +  *			boot up or not.
+ +  */
+ + struct am33xx_sr_platform_data {
+ + 	struct am33xx_sr_sdata	*sr_sdata;
+ + 	char			*vd_name[2];
+ + 	u32			ip_type;
+ +         u32                     irq_delay;
+ + 	u32			no_of_vds;
+ + 	u32			no_of_sens;
+ + 	u32			vstep_size_uv;
+ + 	bool			enable_on_init;
+ + };
+ + 
+ + #endif /*CONFIG_AM33XX_SMARTREFLEX*/
+ + 
+ + #ifdef CONFIG_TI816X_SMARTREFLEX
+ + 
+ + #define SRHVT				0
+ + #define SRSVT				1
+ + 
+ + /* SRClk = 100KHz */
+ + #define SRCLKLENGTH_125MHZ_SYSCLK	(0x271 << 12)
+ + 
+ + /**
+ +  * struct ti816x_sr_sdata	- Smartreflex sensors data
+ +  * @efuse_offs:		The offset of the efuse where n-target values are
+ +  *			stored.
+ +  * @e2v_gain:		Error to voltage gain for changing the percentage
+ +  *			error into voltage delta
+ +  * @err_weight:		Average sensor error weight
+ +  * @err_minlimit:	Minimum error limit of the sensor
+ +  * @err_maxlimit:	Maximum error limit of the sensor
+ +  * @senn_mod:		Enable bit for N sensor
+ +  * @senp_mod:		Enable bit for P sensor
+ +  */
+ + struct ti816x_sr_sdata {
+ + 	u32	efuse_offs;
+ + 	u32	e2v_gain;
+ + 	u32	err_weight;
+ + 	u32	err_minlimit;
+ + 	u32	err_maxlimit;
+ + 	u32	senn_mod;
+ + 	u32	senp_mod;
+ + };
+ + 
+ + /**
+ +  * struct ti816x_sr_platform_data - Smartreflex platform data.
+ +  * @sr_sdata:		SR per sensor details, contains the efuse off-sets,
+ +  *			error to voltage gain factor, minimum error limits
+ +  * @vd_name:		Name of the voltage domain.
+ +  * @ip_type:		Smartreflex IP type, class1 or class2 or class3.
+ +  * @irq_delay:		Time delay between disable and re-enable the
+ +  *			interrupts, in msec
+ +  * @no_of_vds:		Number of voltage domains to which SR applicable
+ +  * @no_of_sens:		Number of SR sensors used to monitor the device
+ +  *			performance, temp etc...
+ +  * @vstep_size_uv:	PMIC voltage step size in micro volts
+ +  * @enable_on_init:	whether this sr module needs to enabled at
+ +  *			boot up or not.
+ +  */
+ + struct ti816x_sr_platform_data {
+ + 	struct ti816x_sr_sdata	*sr_sdata;
+ + 	char			*vd_name;
+ + 	u32			ip_type;
+ + 	u32			irq_delay;
+ + 	u32			no_of_vds;
+ + 	u32			no_of_sens;
+ + 	u32			vstep_size_uv;
+ + 	bool			enable_on_init;
+ + };
+ + 
+ + #endif /* CONFIG_TI816X_SMARTREFLEX */
+ + 
+ + static inline void omap_sr_enable(struct voltagedomain *voltdm) {}
+ + static inline void omap_sr_disable(struct voltagedomain *voltdm) {}
+ + static inline void omap_sr_disable_reset_volt(
+ + 		struct voltagedomain *voltdm) {}
+ + static inline void omap_sr_register_pmic(
+ + 		struct omap_sr_pmic_data *pmic_data) {}
+ + #endif
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/sram.h linux-3.2.1/arch/arm/plat-ckb/include/plat/sram.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/sram.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/sram.h	2014-11-25 13:19:15.196032475 +0900
+ ***************
+ *** 0 ****
+ --- 1,107 ----
+ + /*
+ +  * arch/arm/plat-omap/include/mach/sram.h
+ +  *
+ +  * Interface for functions that need to be run in internal SRAM
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #ifndef __ARCH_ARM_OMAP_SRAM_H
+ + #define __ARCH_ARM_OMAP_SRAM_H
+ + 
+ + #ifndef __ASSEMBLY__
+ + #include <linux/slab.h>
+ + #include <linux/genalloc.h>
+ + #include <asm/fncpy.h>
+ + 
+ + extern struct gen_pool *omap_gen_pool;
+ + 
+ + /*
+ +  * Note that fncpy requires the SRAM address to be aligned to an 8-byte
+ +  * boundary, so the min_alloc_order for the pool is set appropriately.
+ +  */
+ + #define omap_sram_push(funcp, size) ({					\
+ + 	typeof(&(funcp)) _res;						\
+ + 	size_t _sz = size;						\
+ + 	void *_sram = (void *) gen_pool_alloc(omap_gen_pool, _sz);	\
+ + 	_res = (_sram ? fncpy(_sram, &(funcp), _sz) : NULL);		\
+ + 	if (!_res)							\
+ + 		pr_err("Not enough space in SRAM to copy suspend code\n");			\
+ + 	_res;								\
+ + })
+ + 
+ + extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
+ + 
+ + extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
+ + 				u32 base_cs, u32 force_unlock);
+ + extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
+ + 				      u32 mem_type);
+ + extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
+ + 
+ + extern u32 omap3_configure_core_dpll(
+ + 			u32 m2, u32 unlock_dll, u32 f, u32 inc,
+ + 			u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
+ + 			u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
+ + 			u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
+ + 			u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
+ + extern void omap3_sram_restore_context(void);
+ + 
+ + /* Do not use these */
+ + extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
+ + extern unsigned long omap1_sram_reprogram_clock_sz;
+ + 
+ + extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
+ + extern unsigned long omap24xx_sram_reprogram_clock_sz;
+ + 
+ + extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
+ + 						u32 base_cs, u32 force_unlock);
+ + extern unsigned long omap242x_sram_ddr_init_sz;
+ + 
+ + extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
+ + 						int bypass);
+ + extern unsigned long omap242x_sram_set_prcm_sz;
+ + 
+ + extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
+ + 						u32 mem_type);
+ + extern unsigned long omap242x_sram_reprogram_sdrc_sz;
+ + 
+ + 
+ + extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
+ + 						u32 base_cs, u32 force_unlock);
+ + extern unsigned long omap243x_sram_ddr_init_sz;
+ + 
+ + extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
+ + 						int bypass);
+ + extern unsigned long omap243x_sram_set_prcm_sz;
+ + 
+ + extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
+ + 						u32 mem_type);
+ + extern unsigned long omap243x_sram_reprogram_sdrc_sz;
+ + 
+ + extern u32 omap3_sram_configure_core_dpll(
+ + 			u32 m2, u32 unlock_dll, u32 f, u32 inc,
+ + 			u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
+ + 			u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
+ + 			u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
+ + 			u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
+ + extern unsigned long omap3_sram_configure_core_dpll_sz;
+ + 
+ + #ifdef CONFIG_PM
+ + extern void am33xx_push_sram_idle(void);
+ + extern void omap_push_sram_idle(void);
+ + #else
+ + static inline void am33xx_push_sram_idle(void) {}
+ + static inline void omap_push_sram_idle(void) {}
+ + #endif /* CONFIG_PM */
+ + 
+ + #endif /* __ASSEMBLY__ */
+ + 
+ + /*
+ +  * OMAP2+: define the SRAM PA addresses.
+ +  * Used by the SRAM management code and the idle sleep code.
+ +  */
+ + #define OMAP3_SUSPEND_SRAM_PA   0x402F1000
+ + #define AM33XX_SRAM_PA			0x40300000
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/system.h linux-3.2.1/arch/arm/plat-ckb/include/plat/system.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/system.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/system.h	2014-11-25 13:19:15.196032475 +0900
+ ***************
+ *** 0 ****
+ --- 1,17 ----
+ + /*
+ +  * Copied from arch/arm/mach-sa1100/include/mach/system.h
+ +  * Copyright (c) 1999 Nicolas Pitre <nico@fluxnic.net>
+ +  */
+ + #ifndef __ASM_ARCH_SYSTEM_H
+ + #define __ASM_ARCH_SYSTEM_H
+ + 
+ + #include <asm/proc-fns.h>
+ + 
+ + static inline void arch_idle(void)
+ + {
+ + 	cpu_do_idle();
+ + }
+ + 
+ + extern void (*arch_reset)(char, const char *);
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/timex.h linux-3.2.1/arch/arm/plat-ckb/include/plat/timex.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/timex.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/timex.h	2014-11-25 13:19:15.196032475 +0900
+ ***************
+ *** 0 ****
+ --- 1,41 ----
+ + /*
+ +  * arch/arm/plat-omap/include/mach/timex.h
+ +  *
+ +  * Copyright (C) 2000 RidgeRun, Inc.
+ +  * Author:  Greg Lonnon <glonnon@ridgerun.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify it
+ +  * under the terms of the GNU General Public License as published by the
+ +  * Free Software Foundation; either version 2 of the License, or (at your
+ +  * option) any later version.
+ +  *
+ +  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ +  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ +  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ +  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ +  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ +  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ +  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ +  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ +  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ +  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ +  *
+ +  * You should have received a copy of the  GNU General Public License along
+ +  * with this program; if not, write  to the Free Software Foundation, Inc.,
+ +  * 675 Mass Ave, Cambridge, MA 02139, USA.
+ +  */
+ + 
+ + #if !defined(__ASM_ARCH_OMAP_TIMEX_H)
+ + #define __ASM_ARCH_OMAP_TIMEX_H
+ + 
+ + /*
+ +  * OMAP 32KHz timer updates time one jiffie at a time from a secondary timer,
+ +  * and that's why the CLOCK_TICK_RATE is not 32768.
+ +  */
+ + #ifdef CONFIG_OMAP_32K_TIMER
+ + #define CLOCK_TICK_RATE		(CONFIG_OMAP_32K_TIMER_HZ)
+ + #else
+ + #define CLOCK_TICK_RATE		(HZ * 100000UL)
+ + #endif
+ + 
+ + #endif /* __ASM_ARCH_OMAP_TIMEX_H */
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/uncompress.h linux-3.2.1/arch/arm/plat-ckb/include/plat/uncompress.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/uncompress.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/uncompress.h	2014-11-25 13:19:15.199985448 +0900
+ ***************
+ *** 0 ****
+ --- 1,55 ----
+ + /*
+ +  * arch/arm/plat-omap/include/mach/uncompress.h
+ +  *
+ +  * Serial port stubs for kernel decompress status messages
+ +  *
+ +  * Initially based on:
+ +  * linux-2.4.15-rmk1-dsplinux1.6/arch/arm/plat-omap/include/mach1510/uncompress.h
+ +  * Copyright (C) 2000 RidgeRun, Inc.
+ +  * Author: Greg Lonnon <glonnon@ridgerun.com>
+ +  *
+ +  * Rewritten by:
+ +  * Author: <source@mvista.com>
+ +  * 2004 (c) MontaVista Software, Inc.
+ +  *
+ +  * This file is licensed under the terms of the GNU General Public License
+ +  * version 2. This program is licensed "as is" without any warranty of any
+ +  * kind, whether express or implied.
+ +  */
+ + 
+ + #include <linux/types.h>
+ + #include <linux/serial_reg.h>
+ + 
+ + #include <asm/memory.h>
+ + #include <asm/mach-types.h>
+ + 
+ + #include <plat/serial.h>
+ + 
+ + #define MDR1_MODE_MASK			0x07
+ + 
+ + volatile u8 *uart_base;
+ + int uart_shift;
+ + 
+ + static void putc(int c)
+ + {
+ + 	if (!uart_base)
+ + 		return;
+ + 
+ + 	/* Check for UART 16x mode */
+ + 	if ((uart_base[UART_OMAP_MDR1 << uart_shift] & MDR1_MODE_MASK) != 0)
+ + 		return;
+ + 
+ + 	while (!(uart_base[UART_LSR << uart_shift] & UART_LSR_THRE))
+ + 		barrier();
+ + 	uart_base[UART_TX << uart_shift] = c;
+ + }
+ + 
+ + static inline void flush(void)
+ + {
+ + }
+ + 
+ + /*
+ +  * nothing to do
+ +  */
+ + #define arch_decomp_setup()
+ + #define arch_decomp_wdog()
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/usb.h linux-3.2.1/arch/arm/plat-ckb/include/plat/usb.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/usb.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/usb.h	2014-11-25 13:19:15.300691829 +0900
+ ***************
+ *** 0 ****
+ --- 1,383 ----
+ + // include/asm-arm/mach-omap/usb.h
+ + 
+ + #ifndef	__ASM_ARCH_OMAP_USB_H
+ + #define	__ASM_ARCH_OMAP_USB_H
+ + 
+ + #include <linux/usb/musb.h>
+ + #include <plat/board.h>
+ + 
+ + #define OMAP3_HS_USB_PORTS	3
+ + 
+ + enum usbhs_omap_port_mode {
+ + 	OMAP_USBHS_PORT_MODE_UNUSED,
+ + 	OMAP_EHCI_PORT_MODE_PHY,
+ + 	OMAP_EHCI_PORT_MODE_TLL,
+ + 	OMAP_EHCI_PORT_MODE_HSIC,
+ + 	OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0,
+ + 	OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM,
+ + 	OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0,
+ + 	OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM,
+ + 	OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0,
+ + 	OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM,
+ + 	OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0,
+ + 	OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM,
+ + 	OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0,
+ + 	OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM
+ + };
+ + 
+ + struct usbhs_omap_board_data {
+ + 	enum usbhs_omap_port_mode	port_mode[OMAP3_HS_USB_PORTS];
+ + 
+ + 	/* have to be valid if phy_reset is true and portx is in phy mode */
+ + 	int	reset_gpio_port[OMAP3_HS_USB_PORTS];
+ + 
+ + 	/* Set this to true for ES2.x silicon */
+ + 	unsigned			es2_compatibility:1;
+ + 
+ + 	unsigned			phy_reset:1;
+ + 
+ + 	/*
+ + 	 * Regulators for USB PHYs.
+ + 	 * Each PHY can have a separate regulator.
+ + 	 */
+ + 	struct regulator		*regulator[OMAP3_HS_USB_PORTS];
+ + };
+ + 
+ + struct ehci_hcd_omap_platform_data {
+ + 	enum usbhs_omap_port_mode	port_mode[OMAP3_HS_USB_PORTS];
+ + 	int				reset_gpio_port[OMAP3_HS_USB_PORTS];
+ + 	struct regulator		*regulator[OMAP3_HS_USB_PORTS];
+ + 	unsigned			phy_reset:1;
+ + };
+ + 
+ + struct ohci_hcd_omap_platform_data {
+ + 	enum usbhs_omap_port_mode	port_mode[OMAP3_HS_USB_PORTS];
+ + 	unsigned			es2_compatibility:1;
+ + };
+ + 
+ + struct usbhs_omap_platform_data {
+ + 	enum usbhs_omap_port_mode		port_mode[OMAP3_HS_USB_PORTS];
+ + 
+ + 	struct ehci_hcd_omap_platform_data	*ehci_data;
+ + 	struct ohci_hcd_omap_platform_data	*ohci_data;
+ + };
+ + /*-------------------------------------------------------------------------*/
+ + 
+ + #define OMAP1_OTG_BASE			0xfffb0400
+ + #define OMAP1_UDC_BASE			0xfffb4000
+ + #define OMAP1_OHCI_BASE			0xfffba000
+ + 
+ + #define OMAP2_OHCI_BASE			0x4805e000
+ + #define OMAP2_UDC_BASE			0x4805e200
+ + #define OMAP2_OTG_BASE			0x4805e300
+ + 
+ + #ifdef CONFIG_ARCH_OMAP1
+ + 
+ + #define OTG_BASE			OMAP1_OTG_BASE
+ + #define UDC_BASE			OMAP1_UDC_BASE
+ + #define OMAP_OHCI_BASE			OMAP1_OHCI_BASE
+ + 
+ + #else
+ + 
+ + #define OTG_BASE			OMAP2_OTG_BASE
+ + #define UDC_BASE			OMAP2_UDC_BASE
+ + #define OMAP_OHCI_BASE			OMAP2_OHCI_BASE
+ + 
+ + struct omap_musb_board_data {
+ + 	u8	interface_type;
+ + 	u8	mode;
+ + 	u16	power;
+ + 	unsigned extvbus:1;
+ + 	u8	instances;
+ + 	u8	grndis_for_host_rx;
+ + 	u8	babble_ctrl;
+ + 	void	(*set_phy_power)(u8 id, u8 on, bool wkup);
+ + 	void	(*clear_irq)(void);
+ + 	void	(*set_mode)(u8 mode);
+ + 	void	(*reset)(void);
+ + };
+ + 
+ + enum musb_interface    {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
+ + 
+ + extern void usb_musb_init(struct omap_musb_board_data *board_data);
+ + 
+ + extern void usbhs_init(const struct usbhs_omap_board_data *pdata);
+ + 
+ + extern int omap4430_phy_power(struct device *dev, int ID, int on);
+ + extern int omap4430_phy_set_clk(struct device *dev, int on);
+ + extern int omap4430_phy_exit(struct device *dev);
+ + extern int omap4430_phy_suspend(struct device *dev, int suspend);
+ + #endif
+ + 
+ + extern void am35x_musb_reset(void);
+ + extern void am35x_musb_phy_power(u8 id, u8 on);
+ + extern void am35x_musb_clear_irq(void);
+ + extern void am35x_set_mode(u8 musb_mode);
+ + extern void ti81xx_musb_phy_power(u8 id, u8 on, bool wkup);
+ + 
+ + /*
+ +  * FIXME correct answer depends on hmc_mode,
+ +  * as does (on omap1) any nonzero value for config->otg port number
+ +  */
+ + #ifdef	CONFIG_USB_GADGET_OMAP
+ + #define	is_usb0_device(config)	1
+ + #else
+ + #define	is_usb0_device(config)	0
+ + #endif
+ + 
+ + void omap_otg_init(struct omap_usb_config *config);
+ + 
+ + #if defined(CONFIG_USB) || defined(CONFIG_USB_MODULE)
+ + void omap1_usb_init(struct omap_usb_config *pdata);
+ + #else
+ + static inline void omap1_usb_init(struct omap_usb_config *pdata)
+ + {
+ + }
+ + #endif
+ + 
+ + #if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP_OTG_MODULE)
+ + void omap2_usbfs_init(struct omap_usb_config *pdata);
+ + #else
+ + static inline void omap2_usbfs_init(struct omap_usb_config *pdata)
+ + {
+ + }
+ + #endif
+ + 
+ + /*-------------------------------------------------------------------------*/
+ + 
+ + /*
+ +  * OTG and transceiver registers, for OMAPs starting with ARM926
+ +  */
+ + #define OTG_REV				(OTG_BASE + 0x00)
+ + #define OTG_SYSCON_1			(OTG_BASE + 0x04)
+ + #	define	 USB2_TRX_MODE(w)	(((w)>>24)&0x07)
+ + #	define	 USB1_TRX_MODE(w)	(((w)>>20)&0x07)
+ + #	define	 USB0_TRX_MODE(w)	(((w)>>16)&0x07)
+ + #	define	 OTG_IDLE_EN		(1 << 15)
+ + #	define	 HST_IDLE_EN		(1 << 14)
+ + #	define	 DEV_IDLE_EN		(1 << 13)
+ + #	define	 OTG_RESET_DONE		(1 << 2)
+ + #	define	 OTG_SOFT_RESET		(1 << 1)
+ + #define OTG_SYSCON_2			(OTG_BASE + 0x08)
+ + #	define	 OTG_EN			(1 << 31)
+ + #	define	 USBX_SYNCHRO		(1 << 30)
+ + #	define	 OTG_MST16		(1 << 29)
+ + #	define	 SRP_GPDATA		(1 << 28)
+ + #	define	 SRP_GPDVBUS		(1 << 27)
+ + #	define	 SRP_GPUVBUS(w)		(((w)>>24)&0x07)
+ + #	define	 A_WAIT_VRISE(w)	(((w)>>20)&0x07)
+ + #	define	 B_ASE_BRST(w)		(((w)>>16)&0x07)
+ + #	define	 SRP_DPW		(1 << 14)
+ + #	define	 SRP_DATA		(1 << 13)
+ + #	define	 SRP_VBUS		(1 << 12)
+ + #	define	 OTG_PADEN		(1 << 10)
+ + #	define	 HMC_PADEN		(1 << 9)
+ + #	define	 UHOST_EN		(1 << 8)
+ + #	define	 HMC_TLLSPEED		(1 << 7)
+ + #	define	 HMC_TLLATTACH		(1 << 6)
+ + #	define	 OTG_HMC(w)		(((w)>>0)&0x3f)
+ + #define OTG_CTRL			(OTG_BASE + 0x0c)
+ + #	define	 OTG_USB2_EN		(1 << 29)
+ + #	define	 OTG_USB2_DP		(1 << 28)
+ + #	define	 OTG_USB2_DM		(1 << 27)
+ + #	define	 OTG_USB1_EN		(1 << 26)
+ + #	define	 OTG_USB1_DP		(1 << 25)
+ + #	define	 OTG_USB1_DM		(1 << 24)
+ + #	define	 OTG_USB0_EN		(1 << 23)
+ + #	define	 OTG_USB0_DP		(1 << 22)
+ + #	define	 OTG_USB0_DM		(1 << 21)
+ + #	define	 OTG_ASESSVLD		(1 << 20)
+ + #	define	 OTG_BSESSEND		(1 << 19)
+ + #	define	 OTG_BSESSVLD		(1 << 18)
+ + #	define	 OTG_VBUSVLD		(1 << 17)
+ + #	define	 OTG_ID			(1 << 16)
+ + #	define	 OTG_DRIVER_SEL		(1 << 15)
+ + #	define	 OTG_A_SETB_HNPEN	(1 << 12)
+ + #	define	 OTG_A_BUSREQ		(1 << 11)
+ + #	define	 OTG_B_HNPEN		(1 << 9)
+ + #	define	 OTG_B_BUSREQ		(1 << 8)
+ + #	define	 OTG_BUSDROP		(1 << 7)
+ + #	define	 OTG_PULLDOWN		(1 << 5)
+ + #	define	 OTG_PULLUP		(1 << 4)
+ + #	define	 OTG_DRV_VBUS		(1 << 3)
+ + #	define	 OTG_PD_VBUS		(1 << 2)
+ + #	define	 OTG_PU_VBUS		(1 << 1)
+ + #	define	 OTG_PU_ID		(1 << 0)
+ + #define OTG_IRQ_EN			(OTG_BASE + 0x10)	/* 16-bit */
+ + #	define	 DRIVER_SWITCH		(1 << 15)
+ + #	define	 A_VBUS_ERR		(1 << 13)
+ + #	define	 A_REQ_TMROUT		(1 << 12)
+ + #	define	 A_SRP_DETECT		(1 << 11)
+ + #	define	 B_HNP_FAIL		(1 << 10)
+ + #	define	 B_SRP_TMROUT		(1 << 9)
+ + #	define	 B_SRP_DONE		(1 << 8)
+ + #	define	 B_SRP_STARTED		(1 << 7)
+ + #	define	 OPRT_CHG		(1 << 0)
+ + #define OTG_IRQ_SRC			(OTG_BASE + 0x14)	/* 16-bit */
+ + 	// same bits as in IRQ_EN
+ + #define OTG_OUTCTRL			(OTG_BASE + 0x18)	/* 16-bit */
+ + #	define	 OTGVPD			(1 << 14)
+ + #	define	 OTGVPU			(1 << 13)
+ + #	define	 OTGPUID		(1 << 12)
+ + #	define	 USB2VDR		(1 << 10)
+ + #	define	 USB2PDEN		(1 << 9)
+ + #	define	 USB2PUEN		(1 << 8)
+ + #	define	 USB1VDR		(1 << 6)
+ + #	define	 USB1PDEN		(1 << 5)
+ + #	define	 USB1PUEN		(1 << 4)
+ + #	define	 USB0VDR		(1 << 2)
+ + #	define	 USB0PDEN		(1 << 1)
+ + #	define	 USB0PUEN		(1 << 0)
+ + #define OTG_TEST			(OTG_BASE + 0x20)	/* 16-bit */
+ + #define OTG_VENDOR_CODE			(OTG_BASE + 0xfc)	/* 16-bit */
+ + 
+ + /*-------------------------------------------------------------------------*/
+ + 
+ + /* OMAP1 */
+ + #define	USB_TRANSCEIVER_CTRL		(0xfffe1000 + 0x0064)
+ + #	define	CONF_USB2_UNI_R		(1 << 8)
+ + #	define	CONF_USB1_UNI_R		(1 << 7)
+ + #	define	CONF_USB_PORT0_R(x)	(((x)>>4)&0x7)
+ + #	define	CONF_USB0_ISOLATE_R	(1 << 3)
+ + #	define	CONF_USB_PWRDN_DM_R	(1 << 2)
+ + #	define	CONF_USB_PWRDN_DP_R	(1 << 1)
+ + 
+ + /* OMAP2 */
+ + #	define	USB_UNIDIR			0x0
+ + #	define	USB_UNIDIR_TLL			0x1
+ + #	define	USB_BIDIR			0x2
+ + #	define	USB_BIDIR_TLL			0x3
+ + #	define	USBTXWRMODEI(port, x)	((x) << (22 - (port * 2)))
+ + #	define	USBT2TLL5PI		(1 << 17)
+ + #	define	USB0PUENACTLOI		(1 << 16)
+ + #	define	USBSTANDBYCTRL		(1 << 15)
+ + /* AM35x */
+ + /* USB 2.0 PHY Control */
+ + #define CONF2_PHY_GPIOMODE	(1 << 23)
+ + #define CONF2_OTGMODE		(3 << 14)
+ + #define CONF2_NO_OVERRIDE	(0 << 14)
+ + #define CONF2_FORCE_HOST	(1 << 14)
+ + #define CONF2_FORCE_DEVICE	(2 << 14)
+ + #define CONF2_FORCE_HOST_VBUS_LOW (3 << 14)
+ + #define CONF2_SESENDEN		(1 << 13)
+ + #define CONF2_VBDTCTEN		(1 << 12)
+ + #define CONF2_REFFREQ_24MHZ	(2 << 8)
+ + #define CONF2_REFFREQ_26MHZ	(7 << 8)
+ + #define CONF2_REFFREQ_13MHZ	(6 << 8)
+ + #define CONF2_REFFREQ		(0xf << 8)
+ + #define CONF2_PHYCLKGD		(1 << 7)
+ + #define CONF2_VBUSSENSE		(1 << 6)
+ + #define CONF2_PHY_PLLON		(1 << 5)
+ + #define CONF2_RESET		(1 << 4)
+ + #define CONF2_PHYPWRDN		(1 << 3)
+ + #define CONF2_OTGPWRDN		(1 << 2)
+ + #define CONF2_DATPOL		(1 << 1)
+ + 
+ + /* TI81XX specific definitions */
+ + #define USBCTRL0	0x620
+ + #define USBSTAT0	0x624
+ + #define USBCTRL1	0x628
+ + #define USBSTAT1	0x62c
+ + #define USBWKUPCTRL	0x648
+ + 
+ + /* TI816X PHY controls bits */
+ + #define TI816X_USBPHY0_NORMAL_MODE	(1 << 0)
+ + #define TI816X_USBPHY1_NORMAL_MODE	(1 << 1)
+ + #define TI816X_USBPHY_REFCLK_OSC	(1 << 8)
+ + 
+ + /* TI814X PHY controls bits */
+ + #define USBPHY_CM_PWRDN		(1 << 0)
+ + #define USBPHY_OTG_PWRDN	(1 << 1)
+ + #define USBPHY_CHGDET_DIS	(1 << 2)
+ + #define USBPHY_CHGDET_RSTRT	(1 << 3)
+ + #define USBPHY_SRCONDM		(1 << 4)
+ + #define USBPHY_SINKONDP		(1 << 5)
+ + #define USBPHY_CHGISINK_EN	(1 << 6)
+ + #define USBPHY_CHGVSRC_EN	(1 << 7)
+ + #define USBPHY_DMPULLUP		(1 << 8)
+ + #define USBPHY_DPPULLUP		(1 << 9)
+ + #define USBPHY_CDET_EXTCTL	(1 << 10)
+ + #define USBPHY_GPIO_MODE	(1 << 12)
+ + #define USBPHY_DPGPIO_PD	(1 << 17)
+ + #define USBPHY_DMGPIO_PD	(1 << 18)
+ + #define USBPHY_OTGVDET_EN	(1 << 19)
+ + #define USBPHY_OTGSESSEND_EN	(1 << 20)
+ + #define USBPHY_DATA_POLARITY	(1 << 23)
+ + 
+ + /* TI81XX only PHY bits */
+ + #define TI81XX_USBPHY_DPOPBUFCTL	(1 << 13)
+ + #define TI81XX_USBPHY_DMOPBUFCTL	(1 << 14)
+ + #define TI81XX_USBPHY_DPINPUT		(1 << 15)
+ + #define TI81XX_USBPHY_DMINPUT		(1 << 16)
+ + 
+ + /* AM335X only PHY bits */
+ + #define AM335X_USBPHY_GPIO_SIG_INV     (1 << 13)
+ + #define AM335X_USBPHY_GPIO_SIG_CROSS   (1 << 14)
+ + 
+ + /*AM335X USB wakeup control bits */
+ + #define AM33XX_USB_WKUP_CTRL_ENABLE    ((1 << 8) | (1 << 0))
+ + #define AM33XX_USB0_WKUP_CTRL_ENABLE    (1 << 0)
+ + #define AM33XX_USB1_WKUP_CTRL_ENABLE    (1 << 8)
+ + #define AM33XX_USB_WKUP_CTRL_DISABLE   0x0
+ + 
+ + 
+ + static inline u32 omap1_usb0_init(unsigned nwires, unsigned is_device)
+ + {
+ + 	return 0;
+ + }
+ + static inline u32 omap1_usb1_init(unsigned nwires)
+ + {
+ + 	return 0;
+ + 
+ + }
+ + static inline u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup)
+ + {
+ + 	return 0;
+ + }
+ + 
+ + /* DMA registers */
+ + #define TI81XX_USB_AUTOREQ_REG	0xd0
+ + #define TI81XX_USB_TEARDOWN_REG	0xd8
+ + #define USB_AUTOREQ_REG		0x14
+ + #define USB_TEARDOWN_REG	0x1c
+ + #define MOP_SOP_INTR_ENABLE	0x64
+ + /* 0x68-0x6c Reserved */
+ + #define USB_TX_MODE_REG		0x70	/* Transparent, CDC, [Generic] RNDIS */
+ + #define USB_RX_MODE_REG		0x74	/* Transparent, CDC, [Generic] RNDIS */
+ + #define EP_COUNT_MODE_REG	0x78
+ + #define USB_GENERIC_RNDIS_EP_SIZE_REG(n) (0x80 + (((n) - 1) << 2))
+ + 
+ + #define QUEUE_THRESHOLD_INTR_ENABLE_REG	0xc0
+ + #define	QUEUE_63_THRESHOLD_REG	0xc4
+ + #define QUEUE_63_THRESHOLD_INTR_CLEAR_REG 0xc8
+ + #define	QUEUE_65_THRESHOLD_REG	0xd4
+ + #define QUEUE_65_THRESHOLD_INTR_CLEAR_REG 0xd8
+ + 
+ + /* Mode register bits */
+ + #define USB_MODE_SHIFT(n)	((((n) - 1) << 1))
+ + #define USB_MODE_MASK(n)	(3 << USB_MODE_SHIFT(n))
+ + #define USB_RX_MODE_SHIFT(n)	USB_MODE_SHIFT(n)
+ + #define USB_TX_MODE_SHIFT(n)	USB_MODE_SHIFT(n)
+ + #define USB_RX_MODE_MASK(n)	USB_MODE_MASK(n)
+ + #define USB_TX_MODE_MASK(n)	USB_MODE_MASK(n)
+ + #define USB_TRANSPARENT_MODE	0
+ + #define USB_RNDIS_MODE		1
+ + #define USB_CDC_MODE		2
+ + #define USB_GENERIC_RNDIS_MODE	3
+ + 
+ + /* AutoReq register bits */
+ + #define USB_RX_AUTOREQ_SHIFT(n) (((n) - 1) << 1)
+ + #define USB_RX_AUTOREQ_MASK(n)	(3 << USB_RX_AUTOREQ_SHIFT(n))
+ + #define USB_NO_AUTOREQ		0
+ + #define USB_AUTOREQ_ALL_BUT_EOP 1
+ + #define USB_AUTOREQ_ALWAYS	3
+ + 
+ + /* Teardown register bits */
+ + #define USB_TX_TDOWN_SHIFT(n)	(16 + (n))
+ + #define USB_TX_TDOWN_MASK(n)	(1 << USB_TX_TDOWN_SHIFT(n))
+ + #define USB_RX_TDOWN_SHIFT(n)	(n)
+ + #define USB_RX_TDOWN_MASK(n)	(1 << USB_RX_TDOWN_SHIFT(n))
+ + 
+ + #define USB_CPPI41_NUM_CH	15
+ + 
+ + #endif	/* __ASM_ARCH_OMAP_USB_H */
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/include/plat/voltage.h linux-3.2.1/arch/arm/plat-ckb/include/plat/voltage.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/include/plat/voltage.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/include/plat/voltage.h	2014-11-25 13:19:15.300691829 +0900
+ ***************
+ *** 0 ****
+ --- 1,20 ----
+ + /*
+ +  * OMAP Voltage Management Routines
+ +  *
+ +  * Copyright (C) 2011, Texas Instruments, Inc.
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + 
+ + #ifndef __ARCH_ARM_OMAP_VOLTAGE_H
+ + #define __ARCH_ARM_OMAP_VOLTAGE_H
+ + 
+ + struct voltagedomain;
+ + 
+ + struct voltagedomain *voltdm_lookup(const char *name);
+ + int voltdm_scale(struct voltagedomain *voltdm, unsigned long target_volt);
+ + unsigned long voltdm_get_voltage(struct voltagedomain *voltdm);
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/mailbox.c linux-3.2.1/arch/arm/plat-ckb/mailbox.c
+ *** linux-3.2.1_o/arch/arm/plat-ckb/mailbox.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/mailbox.c	2014-11-25 13:19:15.303061410 +0900
+ ***************
+ *** 0 ****
+ --- 1,460 ----
+ + /*
+ +  * OMAP mailbox driver
+ +  *
+ +  * Copyright (C) 2006-2009 Nokia Corporation. All rights reserved.
+ +  *
+ +  * Contact: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License
+ +  * version 2 as published by the Free Software Foundation.
+ +  *
+ +  * This program is distributed in the hope that it will be useful, but
+ +  * WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ +  * General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ +  * 02110-1301 USA
+ +  *
+ +  */
+ + 
+ + #include <linux/interrupt.h>
+ + #include <linux/spinlock.h>
+ + #include <linux/mutex.h>
+ + #include <linux/delay.h>
+ + #include <linux/slab.h>
+ + #include <linux/kfifo.h>
+ + #include <linux/err.h>
+ + #include <linux/notifier.h>
+ + #include <linux/module.h>
+ + 
+ + #include <plat/mailbox.h>
+ + 
+ + static struct omap_mbox **mboxes;
+ + 
+ + static int mbox_configured;
+ + static DEFINE_MUTEX(mbox_configured_lock);
+ + #define CONFIG_OMAP_MBOX_KFIFO_SIZE  256
+ + static unsigned int mbox_kfifo_size = CONFIG_OMAP_MBOX_KFIFO_SIZE;
+ + module_param(mbox_kfifo_size, uint, S_IRUGO);
+ + MODULE_PARM_DESC(mbox_kfifo_size, "Size of omap's mailbox kfifo (bytes)");
+ + 
+ + /* Mailbox FIFO handle functions */
+ + static inline mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox)
+ + {
+ + 	return mbox->ops->fifo_read(mbox);
+ + }
+ + static inline void mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
+ + {
+ + 	mbox->ops->fifo_write(mbox, msg);
+ + }
+ + static inline int mbox_fifo_empty(struct omap_mbox *mbox)
+ + {
+ + 	return mbox->ops->fifo_empty(mbox);
+ + }
+ + static inline int mbox_fifo_full(struct omap_mbox *mbox)
+ + {
+ + 	return mbox->ops->fifo_full(mbox);
+ + }
+ + static inline int mbox_fifo_needs_flush(struct omap_mbox *mbox)
+ + {
+ + 	return mbox->ops->fifo_needs_flush(mbox);
+ + }
+ + static inline mbox_msg_t mbox_fifo_readback(struct omap_mbox *mbox)
+ + {
+ + 	return mbox->ops->fifo_readback(mbox);
+ + }
+ + 
+ + /* Mailbox IRQ handle functions */
+ + static inline void ack_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
+ + {
+ + 	if (mbox->ops->ack_irq)
+ + 		mbox->ops->ack_irq(mbox, irq);
+ + }
+ + static inline int is_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
+ + {
+ + 	return mbox->ops->is_irq(mbox, irq);
+ + }
+ + 
+ + /*
+ +  * message sender
+ +  */
+ + static int __mbox_poll_for_space(struct omap_mbox *mbox)
+ + {
+ + 	int ret = 0, i = 1000;
+ + 
+ + 	while (mbox_fifo_full(mbox)) {
+ + 		if (mbox->ops->type == OMAP_MBOX_TYPE2)
+ + 			return -1;
+ + 		if (--i == 0)
+ + 			return -1;
+ + 		udelay(1);
+ + 	}
+ + 	return ret;
+ + }
+ + 
+ + int omap_mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg)
+ + {
+ + 	struct omap_mbox_queue *mq = mbox->txq;
+ + 	int ret = 0, len;
+ + 
+ + 	spin_lock_bh(&mq->lock);
+ + 
+ + 	if (kfifo_avail(&mq->fifo) < sizeof(msg)) {
+ + 		ret = -ENOMEM;
+ + 		goto out;
+ + 	}
+ + 
+ + 	if (kfifo_is_empty(&mq->fifo) && !__mbox_poll_for_space(mbox)) {
+ + 		mbox_fifo_write(mbox, msg);
+ + 		goto out;
+ + 	}
+ + 
+ + 	len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
+ + 	WARN_ON(len != sizeof(msg));
+ + 
+ + 	tasklet_schedule(&mbox->txq->tasklet);
+ + 
+ + out:
+ + 	spin_unlock_bh(&mq->lock);
+ + 	return ret;
+ + }
+ + EXPORT_SYMBOL(omap_mbox_msg_send);
+ + 
+ + /*
+ +  * Flush the Rx FIFO by reading back the messages
+ +  * Since the normal expectation is that the Rx will do the
+ +  * reading, add a debug message to indicate if we really flush
+ +  * returns the no. of messages read back
+ +  */
+ + int omap_mbox_msg_rx_flush(struct omap_mbox *mbox)
+ + {
+ + 	int ret = 0;
+ + 	mbox_msg_t msg;
+ + 
+ + 	while (!mbox_fifo_needs_flush(mbox)) {
+ + 		ret++;
+ + 		msg = mbox_fifo_readback(mbox);
+ + 	}
+ + 	if (ret)
+ + 		pr_debug("Flushed %s Rx FIFO via %d readbacks\n", mbox->name, ret);
+ + 
+ + 	return ret;
+ + }
+ + EXPORT_SYMBOL(omap_mbox_msg_rx_flush);
+ + 
+ + static void mbox_tx_tasklet(unsigned long tx_data)
+ + {
+ + 	struct omap_mbox *mbox = (struct omap_mbox *)tx_data;
+ + 	struct omap_mbox_queue *mq = mbox->txq;
+ + 	mbox_msg_t msg;
+ + 	int ret;
+ + 
+ + 	while (kfifo_len(&mq->fifo)) {
+ + 		if (__mbox_poll_for_space(mbox)) {
+ + 			omap_mbox_enable_irq(mbox, IRQ_TX);
+ + 			break;
+ + 		}
+ + 
+ + 		ret = kfifo_out(&mq->fifo, (unsigned char *)&msg,
+ + 								sizeof(msg));
+ + 		WARN_ON(ret != sizeof(msg));
+ + 
+ + 		mbox_fifo_write(mbox, msg);
+ + 	}
+ + }
+ + 
+ + /*
+ +  * Message receiver(workqueue)
+ +  */
+ + static void mbox_rx_work(struct work_struct *work)
+ + {
+ + 	struct omap_mbox_queue *mq =
+ + 			container_of(work, struct omap_mbox_queue, work);
+ + 	mbox_msg_t msg;
+ + 	int len;
+ + 
+ + 	while (kfifo_len(&mq->fifo) >= sizeof(msg)) {
+ + 		len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
+ + 		WARN_ON(len != sizeof(msg));
+ + 
+ + 		blocking_notifier_call_chain(&mq->mbox->notifier, len,
+ + 								(void *)msg);
+ + 		spin_lock_irq(&mq->lock);
+ + 		if (mq->full) {
+ + 			mq->full = false;
+ + 			omap_mbox_enable_irq(mq->mbox, IRQ_RX);
+ + 		}
+ + 		spin_unlock_irq(&mq->lock);
+ + 	}
+ + }
+ + 
+ + /*
+ +  * Mailbox interrupt handler
+ +  */
+ + static void __mbox_tx_interrupt(struct omap_mbox *mbox)
+ + {
+ + 	omap_mbox_disable_irq(mbox, IRQ_TX);
+ + 	ack_mbox_irq(mbox, IRQ_TX);
+ + 	tasklet_schedule(&mbox->txq->tasklet);
+ + }
+ + 
+ + static void __mbox_rx_interrupt(struct omap_mbox *mbox)
+ + {
+ + 	struct omap_mbox_queue *mq = mbox->rxq;
+ + 	mbox_msg_t msg;
+ + 	int len;
+ + 
+ + 	while (!mbox_fifo_empty(mbox)) {
+ + 		if (unlikely(kfifo_avail(&mq->fifo) < sizeof(msg))) {
+ + 			omap_mbox_disable_irq(mbox, IRQ_RX);
+ + 			mq->full = true;
+ + 			goto nomem;
+ + 		}
+ + 
+ + 		msg = mbox_fifo_read(mbox);
+ + 
+ + 		len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
+ + 		WARN_ON(len != sizeof(msg));
+ + 
+ + 		if (mbox->ops->type == OMAP_MBOX_TYPE1)
+ + 			break;
+ + 	}
+ + 
+ + 	/* no more messages in the fifo. clear IRQ source. */
+ + 	ack_mbox_irq(mbox, IRQ_RX);
+ + nomem:
+ + 	schedule_work(&mbox->rxq->work);
+ + }
+ + 
+ + static irqreturn_t mbox_interrupt(int irq, void *p)
+ + {
+ + 	struct omap_mbox *mbox = p;
+ + 
+ + 	if (is_mbox_irq(mbox, IRQ_TX))
+ + 		__mbox_tx_interrupt(mbox);
+ + 
+ + 	if (is_mbox_irq(mbox, IRQ_RX))
+ + 		__mbox_rx_interrupt(mbox);
+ + 
+ + 	return IRQ_HANDLED;
+ + }
+ + 
+ + static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox,
+ + 					void (*work) (struct work_struct *),
+ + 					void (*tasklet)(unsigned long))
+ + {
+ + 	struct omap_mbox_queue *mq;
+ + 
+ + 	mq = kzalloc(sizeof(struct omap_mbox_queue), GFP_KERNEL);
+ + 	if (!mq)
+ + 		return NULL;
+ + 
+ + 	spin_lock_init(&mq->lock);
+ + 
+ + 	if (kfifo_alloc(&mq->fifo, mbox_kfifo_size, GFP_KERNEL))
+ + 		goto error;
+ + 
+ + 	if (work)
+ + 		INIT_WORK(&mq->work, work);
+ + 
+ + 	if (tasklet)
+ + 		tasklet_init(&mq->tasklet, tasklet, (unsigned long)mbox);
+ + 	return mq;
+ + error:
+ + 	kfree(mq);
+ + 	return NULL;
+ + }
+ + 
+ + static void mbox_queue_free(struct omap_mbox_queue *q)
+ + {
+ + 	kfifo_free(&q->fifo);
+ + 	kfree(q);
+ + }
+ + 
+ + static int omap_mbox_startup(struct omap_mbox *mbox)
+ + {
+ + 	int ret = 0;
+ + 	struct omap_mbox_queue *mq;
+ + 
+ + 	mutex_lock(&mbox_configured_lock);
+ + 	if (!mbox_configured++) {
+ + 		if (likely(mbox->ops->startup)) {
+ + 			ret = mbox->ops->startup(mbox);
+ + 			if (unlikely(ret))
+ + 				goto fail_startup;
+ + 		} else
+ + 			goto fail_startup;
+ + 	}
+ + 
+ + 	if (!mbox->use_count++) {
+ + 		ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED,
+ + 							mbox->name, mbox);
+ + 		if (unlikely(ret)) {
+ + 			pr_err("failed to register mailbox interrupt:%d\n",
+ + 									ret);
+ + 			goto fail_request_irq;
+ + 		}
+ + 		mq = mbox_queue_alloc(mbox, NULL, mbox_tx_tasklet);
+ + 		if (!mq) {
+ + 			ret = -ENOMEM;
+ + 			goto fail_alloc_txq;
+ + 		}
+ + 		mbox->txq = mq;
+ + 
+ + 		mq = mbox_queue_alloc(mbox, mbox_rx_work, NULL);
+ + 		if (!mq) {
+ + 			ret = -ENOMEM;
+ + 			goto fail_alloc_rxq;
+ + 		}
+ + 		mbox->rxq = mq;
+ + 		mq->mbox = mbox;
+ + 	}
+ + 	mutex_unlock(&mbox_configured_lock);
+ + 	return 0;
+ + 
+ + fail_alloc_rxq:
+ + 	mbox_queue_free(mbox->txq);
+ + fail_alloc_txq:
+ + 	free_irq(mbox->irq, mbox);
+ + fail_request_irq:
+ + 	if (mbox->ops->shutdown)
+ + 		mbox->ops->shutdown(mbox);
+ + 	mbox->use_count--;
+ + fail_startup:
+ + 	mbox_configured--;
+ + 	mutex_unlock(&mbox_configured_lock);
+ + 	return ret;
+ + }
+ + 
+ + static void omap_mbox_fini(struct omap_mbox *mbox)
+ + {
+ + 	mutex_lock(&mbox_configured_lock);
+ + 
+ + 	if (!--mbox->use_count) {
+ + 		free_irq(mbox->irq, mbox);
+ + 		tasklet_kill(&mbox->txq->tasklet);
+ + 	flush_work_sync(&mbox->rxq->work);
+ + 		mbox_queue_free(mbox->txq);
+ + 		mbox_queue_free(mbox->rxq);
+ + 	}
+ + 
+ + 	if (likely(mbox->ops->shutdown)) {
+ + 		if (!--mbox_configured)
+ + 			mbox->ops->shutdown(mbox);
+ + 	}
+ + 
+ + 	mutex_unlock(&mbox_configured_lock);
+ + }
+ + 
+ + struct omap_mbox *omap_mbox_get(const char *name, struct notifier_block *nb)
+ + {
+ + 	struct omap_mbox *_mbox, *mbox = NULL;
+ + 	int i, ret;
+ + 
+ + 	if (!mboxes)
+ + 		return ERR_PTR(-EINVAL);
+ + 
+ + 	for (i = 0; (_mbox = mboxes[i]); i++) {
+ + 		if (!strcmp(_mbox->name, name)) {
+ + 			mbox = _mbox;
+ + 			break;
+ + 		}
+ + 	}
+ + 
+ + 	if (!mbox)
+ + 		return ERR_PTR(-ENOENT);
+ + 
+ + 	ret = omap_mbox_startup(mbox);
+ + 	if (ret)
+ + 		return ERR_PTR(-ENODEV);
+ + 
+ + 	if (nb)
+ + 		blocking_notifier_chain_register(&mbox->notifier, nb);
+ + 
+ + 	return mbox;
+ + }
+ + EXPORT_SYMBOL(omap_mbox_get);
+ + 
+ + void omap_mbox_put(struct omap_mbox *mbox, struct notifier_block *nb)
+ + {
+ + 	blocking_notifier_chain_unregister(&mbox->notifier, nb);
+ + 	omap_mbox_fini(mbox);
+ + }
+ + EXPORT_SYMBOL(omap_mbox_put);
+ + 
+ + static struct class omap_mbox_class = { .name = "mbox", };
+ + 
+ + int omap_mbox_register(struct device *parent, struct omap_mbox **list)
+ + {
+ + 	int ret;
+ + 	int i;
+ + 
+ + 	mboxes = list;
+ + 	if (!mboxes)
+ + 		return -EINVAL;
+ + 
+ + 	for (i = 0; mboxes[i]; i++) {
+ + 		struct omap_mbox *mbox = mboxes[i];
+ + 		mbox->dev = device_create(&omap_mbox_class,
+ + 				parent, 0, mbox, "%s", mbox->name);
+ + 		if (IS_ERR(mbox->dev)) {
+ + 			ret = PTR_ERR(mbox->dev);
+ + 			goto err_out;
+ + 		}
+ + 
+ + 		BLOCKING_INIT_NOTIFIER_HEAD(&mbox->notifier);
+ + 	}
+ + 	return 0;
+ + 
+ + err_out:
+ + 	while (i--)
+ + 		device_unregister(mboxes[i]->dev);
+ + 	return ret;
+ + }
+ + EXPORT_SYMBOL(omap_mbox_register);
+ + 
+ + int omap_mbox_unregister(void)
+ + {
+ + 	int i;
+ + 
+ + 	if (!mboxes)
+ + 		return -EINVAL;
+ + 
+ + 	for (i = 0; mboxes[i]; i++)
+ + 		device_unregister(mboxes[i]->dev);
+ + 	mboxes = NULL;
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(omap_mbox_unregister);
+ + 
+ + static int __init omap_mbox_init(void)
+ + {
+ + 	int err;
+ + 
+ + 	err = class_register(&omap_mbox_class);
+ + 	if (err)
+ + 		return err;
+ + 
+ + 	/* kfifo size sanity check: alignment and minimal size */
+ + 	mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(mbox_msg_t));
+ + 	mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size,
+ + 							sizeof(mbox_msg_t));
+ + 
+ + 	return 0;
+ + }
+ + subsys_initcall(omap_mbox_init);
+ + 
+ + static void __exit omap_mbox_exit(void)
+ + {
+ + 	class_unregister(&omap_mbox_class);
+ + }
+ + module_exit(omap_mbox_exit);
+ + 
+ + MODULE_LICENSE("GPL v2");
+ + MODULE_DESCRIPTION("omap mailbox: interrupt driven messaging");
+ + MODULE_AUTHOR("Toshihiro Kobayashi");
+ + MODULE_AUTHOR("Hiroshi DOYU");
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/Makefile linux-3.2.1/arch/arm/plat-ckb/Makefile
+ *** linux-3.2.1_o/arch/arm/plat-ckb/Makefile	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/Makefile	2014-11-25 13:19:15.303061410 +0900
+ ***************
+ *** 0 ****
+ --- 1,24 ----
+ + #
+ + # Makefile for the linux kernel.
+ + #
+ + 
+ + # Common support
+ + obj-y := common.o sram.o clock.o devices.o mux.o \
+ + 	 usb.o counter_32k.o mailbox.o
+ + 
+ + 
+ + obj-m :=
+ + obj-n :=
+ + obj-  :=
+ + 
+ + obj-$(CONFIG_OMAP3_EDMA) += sdma2edma.o
+ + 
+ + # omap_device support (OMAP2+ only at the moment)
+ + obj-$(CONFIG_MACH_CKB_3352) += omap_device.o
+ + 
+ + obj-$(CONFIG_MACH_CKB_3352) += dmtimer.o
+ + 
+ + i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o
+ + obj-y += $(i2c-omap-m) $(i2c-omap-y)
+ + 
+ + obj-$(CONFIG_MACH_CKB_3352) += omap-pm-noop.o
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/mux.c linux-3.2.1/arch/arm/plat-ckb/mux.c
+ *** linux-3.2.1_o/arch/arm/plat-ckb/mux.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/mux.c	2014-11-25 13:19:15.303061410 +0900
+ ***************
+ *** 0 ****
+ --- 1,51 ----
+ + /*
+ +  * linux/arch/arm/plat-omap/mux.c
+ +  *
+ +  * Utility to set the Omap MUX and PULL_DWN registers from a table in mux.h
+ +  *
+ +  * Copyright (C) 2003 - 2008 Nokia Corporation
+ +  *
+ +  * Written by Tony Lindgren
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; either version 2 of the License, or
+ +  * (at your option) any later version.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ +  *
+ +  */
+ + #include <linux/module.h>
+ + #include <linux/init.h>
+ + #include <linux/kernel.h>
+ + #include <linux/io.h>
+ + #include <asm/system.h>
+ + #include <linux/spinlock.h>
+ + #include <plat/mux.h>
+ + 
+ + #ifdef CONFIG_OMAP_MUX
+ + 
+ + static struct omap_mux_cfg *mux_cfg;
+ + 
+ + int __init omap_mux_register(struct omap_mux_cfg *arch_mux_cfg)
+ + {
+ + 	if (!arch_mux_cfg || !arch_mux_cfg->pins || arch_mux_cfg->size == 0
+ + 			|| !arch_mux_cfg->cfg_reg) {
+ + 		printk(KERN_ERR "Invalid pin table\n");
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	mux_cfg = arch_mux_cfg;
+ + 
+ + 	return 0;
+ + }
+ + #else
+ + #define omap_mux_init() do {} while(0)
+ + #endif	/* CONFIG_OMAP_MUX */
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/omap_device.c linux-3.2.1/arch/arm/plat-ckb/omap_device.c
+ *** linux-3.2.1_o/arch/arm/plat-ckb/omap_device.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/omap_device.c	2014-11-25 13:19:15.307035517 +0900
+ ***************
+ *** 0 ****
+ --- 1,1162 ----
+ + /*
+ +  * omap_device implementation
+ +  *
+ +  * Copyright (C) 2009-2010 Nokia Corporation
+ +  * Paul Walmsley, Kevin Hilman
+ +  *
+ +  * Developed in collaboration with (alphabetical order): Benoit
+ +  * Cousson, Thara Gopinath, Tony Lindgren, Rajendra Nayak, Vikram
+ +  * Pandita, Sakari Poussa, Anand Sawant, Santosh Shilimkar, Richard
+ +  * Woodruff
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  *
+ +  * This code provides a consistent interface for OMAP device drivers
+ +  * to control power management and interconnect properties of their
+ +  * devices.
+ +  *
+ +  * In the medium- to long-term, this code should either be
+ +  * a) implemented via arch-specific pointers in platform_data
+ +  * or
+ +  * b) implemented as a proper omap_bus/omap_device in Linux, no more
+ +  *    platform_data func pointers
+ +  *
+ +  *
+ +  * Guidelines for usage by driver authors:
+ +  *
+ +  * 1. These functions are intended to be used by device drivers via
+ +  * function pointers in struct platform_data.  As an example,
+ +  * omap_device_enable() should be passed to the driver as
+ +  *
+ +  * struct foo_driver_platform_data {
+ +  * ...
+ +  *      int (*device_enable)(struct platform_device *pdev);
+ +  * ...
+ +  * }
+ +  *
+ +  * Note that the generic "device_enable" name is used, rather than
+ +  * "omap_device_enable".  This is so other architectures can pass in their
+ +  * own enable/disable functions here.
+ +  *
+ +  * This should be populated during device setup:
+ +  *
+ +  * ...
+ +  * pdata->device_enable = omap_device_enable;
+ +  * ...
+ +  *
+ +  * 2. Drivers should first check to ensure the function pointer is not null
+ +  * before calling it, as in:
+ +  *
+ +  * if (pdata->device_enable)
+ +  *     pdata->device_enable(pdev);
+ +  *
+ +  * This allows other architectures that don't use similar device_enable()/
+ +  * device_shutdown() functions to execute normally.
+ +  *
+ +  * ...
+ +  *
+ +  * Suggested usage by device drivers:
+ +  *
+ +  * During device initialization:
+ +  * device_enable()
+ +  *
+ +  * During device idle:
+ +  * (save remaining device context if necessary)
+ +  * device_idle();
+ +  *
+ +  * During device resume:
+ +  * device_enable();
+ +  * (restore context if necessary)
+ +  *
+ +  * During device shutdown:
+ +  * device_shutdown()
+ +  * (device must be reinitialized at this point to use it again)
+ +  *
+ +  */
+ + #undef DEBUG
+ + 
+ + #include <linux/kernel.h>
+ + #include <linux/export.h>
+ + #include <linux/platform_device.h>
+ + #include <linux/slab.h>
+ + #include <linux/err.h>
+ + #include <linux/io.h>
+ + #include <linux/clk.h>
+ + #include <linux/clkdev.h>
+ + #include <linux/pm_runtime.h>
+ + #include <linux/of.h>
+ + #include <linux/notifier.h>
+ + 
+ + #include <plat/omap_device.h>
+ + #include <plat/omap_hwmod.h>
+ + #include <plat/clock.h>
+ + 
+ + /* These parameters are passed to _omap_device_{de,}activate() */
+ + #define USE_WAKEUP_LAT			0
+ + #define IGNORE_WAKEUP_LAT		1
+ + 
+ + static int omap_early_device_register(struct platform_device *pdev);
+ + 
+ + static struct omap_device_pm_latency omap_default_latency[] = {
+ + 	{
+ + 		.deactivate_func = omap_device_idle_hwmods,
+ + 		.activate_func   = omap_device_enable_hwmods,
+ + 		.flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+ + 	}
+ + };
+ + 
+ + /* Private functions */
+ + 
+ + /**
+ +  * _omap_device_activate - increase device readiness
+ +  * @od: struct omap_device *
+ +  * @ignore_lat: increase to latency target (0) or full readiness (1)?
+ +  *
+ +  * Increase readiness of omap_device @od (thus decreasing device
+ +  * wakeup latency, but consuming more power).  If @ignore_lat is
+ +  * IGNORE_WAKEUP_LAT, make the omap_device fully active.  Otherwise,
+ +  * if @ignore_lat is USE_WAKEUP_LAT, and the device's maximum wakeup
+ +  * latency is greater than the requested maximum wakeup latency, step
+ +  * backwards in the omap_device_pm_latency table to ensure the
+ +  * device's maximum wakeup latency is less than or equal to the
+ +  * requested maximum wakeup latency.  Returns 0.
+ +  */
+ + static int _omap_device_activate(struct omap_device *od, u8 ignore_lat)
+ + {
+ + 	struct timespec a, b, c;
+ + 
+ + 	dev_dbg(&od->pdev->dev, "omap_device: activating\n");
+ + 
+ + 	while (od->pm_lat_level > 0) {
+ + 		struct omap_device_pm_latency *odpl;
+ + 		unsigned long long act_lat = 0;
+ + 
+ + 		od->pm_lat_level--;
+ + 
+ + 		odpl = od->pm_lats + od->pm_lat_level;
+ + 
+ + 		if (!ignore_lat &&
+ + 		    (od->dev_wakeup_lat <= od->_dev_wakeup_lat_limit))
+ + 			break;
+ + 
+ + 		read_persistent_clock(&a);
+ + 
+ + 		/* XXX check return code */
+ + 		odpl->activate_func(od);
+ + 
+ + 		read_persistent_clock(&b);
+ + 
+ + 		c = timespec_sub(b, a);
+ + 		act_lat = timespec_to_ns(&c);
+ + 
+ + 		dev_dbg(&od->pdev->dev,
+ + 			"omap_device: pm_lat %d: activate: elapsed time "
+ + 			"%llu nsec\n", od->pm_lat_level, act_lat);
+ + 
+ + 		if (act_lat > odpl->activate_lat) {
+ + 			odpl->activate_lat_worst = act_lat;
+ + 			if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) {
+ + 				odpl->activate_lat = act_lat;
+ + 				dev_dbg(&od->pdev->dev,
+ + 					"new worst case activate latency "
+ + 					"%d: %llu\n",
+ + 					od->pm_lat_level, act_lat);
+ + 			} else
+ + 				dev_warn(&od->pdev->dev,
+ + 					 "activate latency %d "
+ + 					 "higher than exptected. (%llu > %d)\n",
+ + 					 od->pm_lat_level, act_lat,
+ + 					 odpl->activate_lat);
+ + 		}
+ + 
+ + 		od->dev_wakeup_lat -= odpl->activate_lat;
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * _omap_device_deactivate - decrease device readiness
+ +  * @od: struct omap_device *
+ +  * @ignore_lat: decrease to latency target (0) or full inactivity (1)?
+ +  *
+ +  * Decrease readiness of omap_device @od (thus increasing device
+ +  * wakeup latency, but conserving power).  If @ignore_lat is
+ +  * IGNORE_WAKEUP_LAT, make the omap_device fully inactive.  Otherwise,
+ +  * if @ignore_lat is USE_WAKEUP_LAT, and the device's maximum wakeup
+ +  * latency is less than the requested maximum wakeup latency, step
+ +  * forwards in the omap_device_pm_latency table to ensure the device's
+ +  * maximum wakeup latency is less than or equal to the requested
+ +  * maximum wakeup latency.  Returns 0.
+ +  */
+ + static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
+ + {
+ + 	struct timespec a, b, c;
+ + 
+ + 	dev_dbg(&od->pdev->dev, "omap_device: deactivating\n");
+ + 
+ + 	while (od->pm_lat_level < od->pm_lats_cnt) {
+ + 		struct omap_device_pm_latency *odpl;
+ + 		unsigned long long deact_lat = 0;
+ + 
+ + 		odpl = od->pm_lats + od->pm_lat_level;
+ + 
+ + 		if (!ignore_lat &&
+ + 		    ((od->dev_wakeup_lat + odpl->activate_lat) >
+ + 		     od->_dev_wakeup_lat_limit))
+ + 			break;
+ + 
+ + 		read_persistent_clock(&a);
+ + 
+ + 		/* XXX check return code */
+ + 		odpl->deactivate_func(od);
+ + 
+ + 		read_persistent_clock(&b);
+ + 
+ + 		c = timespec_sub(b, a);
+ + 		deact_lat = timespec_to_ns(&c);
+ + 
+ + 		dev_dbg(&od->pdev->dev,
+ + 			"omap_device: pm_lat %d: deactivate: elapsed time "
+ + 			"%llu nsec\n", od->pm_lat_level, deact_lat);
+ + 
+ + 		if (deact_lat > odpl->deactivate_lat) {
+ + 			odpl->deactivate_lat_worst = deact_lat;
+ + 			if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) {
+ + 				odpl->deactivate_lat = deact_lat;
+ + 				dev_dbg(&od->pdev->dev,
+ + 					"new worst case deactivate latency "
+ + 					"%d: %llu\n",
+ + 					od->pm_lat_level, deact_lat);
+ + 			} else
+ + 				dev_warn(&od->pdev->dev,
+ + 					 "deactivate latency %d "
+ + 					 "higher than exptected. (%llu > %d)\n",
+ + 					 od->pm_lat_level, deact_lat,
+ + 					 odpl->deactivate_lat);
+ + 		}
+ + 
+ + 		od->dev_wakeup_lat += odpl->activate_lat;
+ + 
+ + 		od->pm_lat_level++;
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static void _add_clkdev(struct omap_device *od, const char *clk_alias,
+ + 		       const char *clk_name)
+ + {
+ + 	struct clk *r;
+ + 	struct clk_lookup *l;
+ + 
+ + 	if (!clk_alias || !clk_name)
+ + 		return;
+ + 
+ + 	dev_dbg(&od->pdev->dev, "Creating %s -> %s\n", clk_alias, clk_name);
+ + 
+ + 	r = clk_get_sys(dev_name(&od->pdev->dev), clk_alias);
+ + 	if (!IS_ERR(r)) {
+ + 		dev_warn(&od->pdev->dev,
+ + 			 "alias %s already exists\n", clk_alias);
+ + 		clk_put(r);
+ + 		return;
+ + 	}
+ + 
+ + 	r = omap_clk_get_by_name(clk_name);
+ + 	if (IS_ERR(r)) {
+ + 		dev_err(&od->pdev->dev,
+ + 			"omap_clk_get_by_name for %s failed\n", clk_name);
+ + 		return;
+ + 	}
+ + 
+ + 	l = clkdev_alloc(r, clk_alias, dev_name(&od->pdev->dev));
+ + 	if (!l) {
+ + 		dev_err(&od->pdev->dev,
+ + 			"clkdev_alloc for %s failed\n", clk_alias);
+ + 		return;
+ + 	}
+ + 
+ + 	clkdev_add(l);
+ + }
+ + 
+ + /**
+ +  * _add_hwmod_clocks_clkdev - Add clkdev entry for hwmod optional clocks
+ +  * and main clock
+ +  * @od: struct omap_device *od
+ +  * @oh: struct omap_hwmod *oh
+ +  *
+ +  * For the main clock and every optional clock present per hwmod per
+ +  * omap_device, this function adds an entry in the clkdev table of the
+ +  * form <dev-id=dev_name, con-id=role> if it does not exist already.
+ +  *
+ +  * The function is called from inside omap_device_build_ss(), after
+ +  * omap_device_register.
+ +  *
+ +  * This allows drivers to get a pointer to its optional clocks based on its role
+ +  * by calling clk_get(<dev*>, <role>).
+ +  * In the case of the main clock, a "fck" alias is used.
+ +  *
+ +  * No return value.
+ +  */
+ + static void _add_hwmod_clocks_clkdev(struct omap_device *od,
+ + 				     struct omap_hwmod *oh)
+ + {
+ + 	int i;
+ + 
+ + 	_add_clkdev(od, "fck", oh->main_clk);
+ + 
+ + 	for (i = 0; i < oh->opt_clks_cnt; i++)
+ + 		_add_clkdev(od, oh->opt_clks[i].role, oh->opt_clks[i].clk);
+ + }
+ + 
+ + 
+ + static struct dev_pm_domain omap_device_pm_domain;
+ + 
+ + /**
+ +  * omap_device_build_from_dt - build an omap_device with multiple hwmods
+ +  * @pdev_name: name of the platform_device driver to use
+ +  * @pdev_id: this platform_device's connection ID
+ +  * @oh: ptr to the single omap_hwmod that backs this omap_device
+ +  * @pdata: platform_data ptr to associate with the platform_device
+ +  * @pdata_len: amount of memory pointed to by @pdata
+ +  * @pm_lats: pointer to a omap_device_pm_latency array for this device
+ +  * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats
+ +  * @is_early_device: should the device be registered as an early device or not
+ +  *
+ +  * Function for building an omap_device already registered from device-tree
+ +  *
+ +  * Returns 0 or PTR_ERR() on error.
+ +  */
+ + static int omap_device_build_from_dt(struct platform_device *pdev)
+ + {
+ + 	struct omap_hwmod **hwmods;
+ + 	struct omap_device *od;
+ + 	struct omap_hwmod *oh;
+ + 	struct device_node *node = pdev->dev.of_node;
+ + 	const char *oh_name;
+ + 	int oh_cnt, i, ret = 0;
+ + 
+ + 	oh_cnt = of_property_count_strings(node, "ti,hwmods");
+ + 	if (!oh_cnt || IS_ERR_VALUE(oh_cnt)) {
+ + 		dev_warn(&pdev->dev, "No 'hwmods' to build omap_device\n");
+ + 		return -ENODEV;
+ + 	}
+ + 
+ + 	hwmods = kzalloc(sizeof(struct omap_hwmod *) * oh_cnt, GFP_KERNEL);
+ + 	if (!hwmods) {
+ + 		ret = -ENOMEM;
+ + 		goto odbfd_exit;
+ + 	}
+ + 
+ + 	for (i = 0; i < oh_cnt; i++) {
+ + 		of_property_read_string_index(node, "ti,hwmods", i, &oh_name);
+ + 		oh = omap_hwmod_lookup(oh_name);
+ + 		if (!oh) {
+ + 			dev_err(&pdev->dev, "Cannot lookup hwmod '%s'\n",
+ + 				oh_name);
+ + 			ret = -EINVAL;
+ + 			goto odbfd_exit1;
+ + 		}
+ + 		hwmods[i] = oh;
+ + 	}
+ + 
+ + 	od = omap_device_alloc(pdev, hwmods, oh_cnt, NULL, 0);
+ + 	if (!od) {
+ + 		dev_err(&pdev->dev, "Cannot allocate omap_device for :%s\n",
+ + 			oh_name);
+ + 		ret = PTR_ERR(od);
+ + 		goto odbfd_exit1;
+ + 	}
+ + 
+ + 	if (of_get_property(node, "ti,no_idle_on_suspend", NULL))
+ + 		omap_device_disable_idle_on_suspend(pdev);
+ + 
+ + 	pdev->dev.pm_domain = &omap_device_pm_domain;
+ + 
+ + odbfd_exit1:
+ + 	kfree(hwmods);
+ + odbfd_exit:
+ + 	return ret;
+ + }
+ + 
+ + static int _omap_device_notifier_call(struct notifier_block *nb,
+ + 				      unsigned long event, void *dev)
+ + {
+ + 	struct platform_device *pdev = to_platform_device(dev);
+ + 
+ + 	switch (event) {
+ + 	case BUS_NOTIFY_ADD_DEVICE:
+ + 		if (pdev->dev.of_node)
+ + 			omap_device_build_from_dt(pdev);
+ + 		break;
+ + 
+ + 	case BUS_NOTIFY_DEL_DEVICE:
+ + 		if (pdev->archdata.od)
+ + 			omap_device_delete(pdev->archdata.od);
+ + 		break;
+ + 	}
+ + 
+ + 	return NOTIFY_DONE;
+ + }
+ + 
+ + 
+ + /* Public functions for use by core code */
+ + 
+ + /**
+ +  * omap_device_get_context_loss_count - get lost context count
+ +  * @od: struct omap_device *
+ +  *
+ +  * Using the primary hwmod, query the context loss count for this
+ +  * device.
+ +  *
+ +  * Callers should consider context for this device lost any time this
+ +  * function returns a value different than the value the caller got
+ +  * the last time it called this function.
+ +  *
+ +  * If any hwmods exist for the omap_device assoiated with @pdev,
+ +  * return the context loss counter for that hwmod, otherwise return
+ +  * zero.
+ +  */
+ + int omap_device_get_context_loss_count(struct platform_device *pdev)
+ + {
+ + 	struct omap_device *od;
+ + 	u32 ret = 0;
+ + 
+ + 	od = to_omap_device(pdev);
+ + 
+ + 	if (od->hwmods_cnt)
+ + 		ret = omap_hwmod_get_context_loss_count(od->hwmods[0]);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * omap_device_count_resources - count number of struct resource entries needed
+ +  * @od: struct omap_device *
+ +  *
+ +  * Count the number of struct resource entries needed for this
+ +  * omap_device @od.  Used by omap_device_build_ss() to determine how
+ +  * much memory to allocate before calling
+ +  * omap_device_fill_resources().  Returns the count.
+ +  */
+ + static int omap_device_count_resources(struct omap_device *od)
+ + {
+ + 	int c = 0;
+ + 	int i;
+ + 
+ + 	for (i = 0; i < od->hwmods_cnt; i++)
+ + 		c += omap_hwmod_count_resources(od->hwmods[i]);
+ + 
+ + 	pr_debug("omap_device: %s: counted %d total resources across %d "
+ + 		 "hwmods\n", od->pdev->name, c, od->hwmods_cnt);
+ + 
+ + 	return c;
+ + }
+ + 
+ + /**
+ +  * omap_device_fill_resources - fill in array of struct resource
+ +  * @od: struct omap_device *
+ +  * @res: pointer to an array of struct resource to be filled in
+ +  *
+ +  * Populate one or more empty struct resource pointed to by @res with
+ +  * the resource data for this omap_device @od.  Used by
+ +  * omap_device_build_ss() after calling omap_device_count_resources().
+ +  * Ideally this function would not be needed at all.  If omap_device
+ +  * replaces platform_device, then we can specify our own
+ +  * get_resource()/ get_irq()/etc functions that use the underlying
+ +  * omap_hwmod information.  Or if platform_device is extended to use
+ +  * subarchitecture-specific function pointers, the various
+ +  * platform_device functions can simply call omap_device internal
+ +  * functions to get device resources.  Hacking around the existing
+ +  * platform_device code wastes memory.  Returns 0.
+ +  */
+ + static int omap_device_fill_resources(struct omap_device *od,
+ + 				      struct resource *res)
+ + {
+ + 	int c = 0;
+ + 	int i, r;
+ + 
+ + 	for (i = 0; i < od->hwmods_cnt; i++) {
+ + 		r = omap_hwmod_fill_resources(od->hwmods[i], res);
+ + 		res += r;
+ + 		c += r;
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * omap_device_alloc - allocate an omap_device
+ +  * @pdev: platform_device that will be included in this omap_device
+ +  * @oh: ptr to the single omap_hwmod that backs this omap_device
+ +  * @pdata: platform_data ptr to associate with the platform_device
+ +  * @pdata_len: amount of memory pointed to by @pdata
+ +  * @pm_lats: pointer to a omap_device_pm_latency array for this device
+ +  * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats
+ +  *
+ +  * Convenience function for allocating an omap_device structure and filling
+ +  * hwmods, resources and pm_latency attributes.
+ +  *
+ +  * Returns an struct omap_device pointer or ERR_PTR() on error;
+ +  */
+ + struct omap_device *omap_device_alloc(struct platform_device *pdev,
+ + 					struct omap_hwmod **ohs, int oh_cnt,
+ + 					struct omap_device_pm_latency *pm_lats,
+ + 					int pm_lats_cnt)
+ + {
+ + 	int ret = -ENOMEM;
+ + 	struct omap_device *od;
+ + 	struct resource *res = NULL;
+ + 	int i, res_count;
+ + 	struct omap_hwmod **hwmods;
+ + 
+ + 	od = kzalloc(sizeof(struct omap_device), GFP_KERNEL);
+ + 	if (!od) {
+ + 		ret = -ENOMEM;
+ + 		goto oda_exit1;
+ + 	}
+ + 	od->hwmods_cnt = oh_cnt;
+ + 
+ + 	hwmods = kmemdup(ohs, sizeof(struct omap_hwmod *) * oh_cnt, GFP_KERNEL);
+ + 	if (!hwmods)
+ + 		goto oda_exit2;
+ + 
+ + 	od->hwmods = hwmods;
+ + 	od->pdev = pdev;
+ + 
+ + 	/*
+ + 	 * HACK: Ideally the resources from DT should match, and hwmod
+ + 	 * should just add the missing ones. Since the name is not
+ + 	 * properly populated by DT, stick to hwmod resources only.
+ + 	 */
+ + 	if (pdev->num_resources && pdev->resource)
+ + 		dev_warn(&pdev->dev, "%s(): resources already allocated %d\n",
+ + 			__func__, pdev->num_resources);
+ + 
+ + 	res_count = omap_device_count_resources(od);
+ + 	if (res_count > 0) {
+ + 		dev_dbg(&pdev->dev, "%s(): resources allocated from hwmod %d\n",
+ + 			__func__, res_count);
+ + 		res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL);
+ + 		if (!res)
+ + 			goto oda_exit3;
+ + 
+ + 		omap_device_fill_resources(od, res);
+ + 
+ + 		ret = platform_device_add_resources(pdev, res, res_count);
+ + 		kfree(res);
+ + 
+ + 		if (ret)
+ + 			goto oda_exit3;
+ + 	}
+ + 
+ + 	if (!pm_lats) {
+ + 		pm_lats = omap_default_latency;
+ + 		pm_lats_cnt = ARRAY_SIZE(omap_default_latency);
+ + 	}
+ + 
+ + 	od->pm_lats_cnt = pm_lats_cnt;
+ + 	od->pm_lats = kmemdup(pm_lats,
+ + 			sizeof(struct omap_device_pm_latency) * pm_lats_cnt,
+ + 			GFP_KERNEL);
+ + 	if (!od->pm_lats)
+ + 		goto oda_exit3;
+ + 
+ + 	pdev->archdata.od = od;
+ + 
+ + 	for (i = 0; i < oh_cnt; i++) {
+ + 		hwmods[i]->od = od;
+ + 		_add_hwmod_clocks_clkdev(od, hwmods[i]);
+ + 	}
+ + 
+ + 	return od;
+ + 
+ + oda_exit3:
+ + 	kfree(hwmods);
+ + oda_exit2:
+ + 	kfree(od);
+ + oda_exit1:
+ + 	dev_err(&pdev->dev, "omap_device: build failed (%d)\n", ret);
+ + 
+ + 	return ERR_PTR(ret);
+ + }
+ + 
+ + void omap_device_delete(struct omap_device *od)
+ + {
+ + 	if (!od)
+ + 		return;
+ + 
+ + 	od->pdev->archdata.od = NULL;
+ + 	kfree(od->pm_lats);
+ + 	kfree(od->hwmods);
+ + 	kfree(od);
+ + }
+ + 
+ + /**
+ +  * omap_device_build - build and register an omap_device with one omap_hwmod
+ +  * @pdev_name: name of the platform_device driver to use
+ +  * @pdev_id: this platform_device's connection ID
+ +  * @oh: ptr to the single omap_hwmod that backs this omap_device
+ +  * @pdata: platform_data ptr to associate with the platform_device
+ +  * @pdata_len: amount of memory pointed to by @pdata
+ +  * @pm_lats: pointer to a omap_device_pm_latency array for this device
+ +  * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats
+ +  * @is_early_device: should the device be registered as an early device or not
+ +  *
+ +  * Convenience function for building and registering a single
+ +  * omap_device record, which in turn builds and registers a
+ +  * platform_device record.  See omap_device_build_ss() for more
+ +  * information.  Returns ERR_PTR(-EINVAL) if @oh is NULL; otherwise,
+ +  * passes along the return value of omap_device_build_ss().
+ +  */
+ + struct platform_device *omap_device_build(const char *pdev_name, int pdev_id,
+ + 				      struct omap_hwmod *oh, void *pdata,
+ + 				      int pdata_len,
+ + 				      struct omap_device_pm_latency *pm_lats,
+ + 				      int pm_lats_cnt, int is_early_device)
+ + {
+ + 	struct omap_hwmod *ohs[] = { oh };
+ + 
+ + 	if (!oh)
+ + 		return ERR_PTR(-EINVAL);
+ + 
+ + 	return omap_device_build_ss(pdev_name, pdev_id, ohs, 1, pdata,
+ + 				    pdata_len, pm_lats, pm_lats_cnt,
+ + 				    is_early_device);
+ + }
+ + 
+ + /**
+ +  * omap_device_build_ss - build and register an omap_device with multiple hwmods
+ +  * @pdev_name: name of the platform_device driver to use
+ +  * @pdev_id: this platform_device's connection ID
+ +  * @oh: ptr to the single omap_hwmod that backs this omap_device
+ +  * @pdata: platform_data ptr to associate with the platform_device
+ +  * @pdata_len: amount of memory pointed to by @pdata
+ +  * @pm_lats: pointer to a omap_device_pm_latency array for this device
+ +  * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats
+ +  * @is_early_device: should the device be registered as an early device or not
+ +  *
+ +  * Convenience function for building and registering an omap_device
+ +  * subsystem record.  Subsystem records consist of multiple
+ +  * omap_hwmods.  This function in turn builds and registers a
+ +  * platform_device record.  Returns an ERR_PTR() on error, or passes
+ +  * along the return value of omap_device_register().
+ +  */
+ + struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
+ + 					 struct omap_hwmod **ohs, int oh_cnt,
+ + 					 void *pdata, int pdata_len,
+ + 					 struct omap_device_pm_latency *pm_lats,
+ + 					 int pm_lats_cnt, int is_early_device)
+ + {
+ + 	int ret = -ENOMEM;
+ + 	struct platform_device *pdev;
+ + 	struct omap_device *od;
+ + 
+ + 	if (!ohs || oh_cnt == 0 || !pdev_name)
+ + 		return ERR_PTR(-EINVAL);
+ + 
+ + 	if (!pdata && pdata_len > 0)
+ + 		return ERR_PTR(-EINVAL);
+ + 
+ + 	pdev = platform_device_alloc(pdev_name, pdev_id);
+ + 	if (!pdev) {
+ + 		ret = -ENOMEM;
+ + 		goto odbs_exit;
+ + 	}
+ + 
+ + 	/* Set the dev_name early to allow dev_xxx in omap_device_alloc */
+ + 	if (pdev->id != -1)
+ + 		dev_set_name(&pdev->dev, "%s.%d", pdev->name,  pdev->id);
+ + 	else
+ + 		dev_set_name(&pdev->dev, "%s", pdev->name);
+ + 
+ + 	od = omap_device_alloc(pdev, ohs, oh_cnt, pm_lats, pm_lats_cnt);
+ + 	if (!od)
+ + 		goto odbs_exit1;
+ + 
+ + 	ret = platform_device_add_data(pdev, pdata, pdata_len);
+ + 	if (ret)
+ + 		goto odbs_exit2;
+ + 
+ + 	if (is_early_device)
+ + 		ret = omap_early_device_register(pdev);
+ + 	else
+ + 		ret = omap_device_register(pdev);
+ + 	if (ret)
+ + 		goto odbs_exit2;
+ + 
+ + 	return pdev;
+ + 
+ + odbs_exit2:
+ + 	omap_device_delete(od);
+ + odbs_exit1:
+ + 	platform_device_put(pdev);
+ + odbs_exit:
+ + 
+ + 	pr_err("omap_device: %s: build failed (%d)\n", pdev_name, ret);
+ + 
+ + 	return ERR_PTR(ret);
+ + }
+ + 
+ + /**
+ +  * omap_early_device_register - register an omap_device as an early platform
+ +  * device.
+ +  * @od: struct omap_device * to register
+ +  *
+ +  * Register the omap_device structure.  This currently just calls
+ +  * platform_early_add_device() on the underlying platform_device.
+ +  * Returns 0 by default.
+ +  */
+ + static int omap_early_device_register(struct platform_device *pdev)
+ + {
+ + 	struct platform_device *devices[1];
+ + 
+ + 	devices[0] = pdev;
+ + 	early_platform_add_devices(devices, 1);
+ + 	return 0;
+ + }
+ + 
+ + #ifdef CONFIG_PM_RUNTIME
+ + static int _od_runtime_suspend(struct device *dev)
+ + {
+ + 	struct platform_device *pdev = to_platform_device(dev);
+ + 	int ret;
+ + 
+ + 	ret = pm_generic_runtime_suspend(dev);
+ + 
+ + 	if (!ret)
+ + 		omap_device_idle(pdev);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + static int _od_runtime_idle(struct device *dev)
+ + {
+ + 	return pm_generic_runtime_idle(dev);
+ + }
+ + 
+ + static int _od_runtime_resume(struct device *dev)
+ + {
+ + 	struct platform_device *pdev = to_platform_device(dev);
+ + 
+ + 	omap_device_enable(pdev);
+ + 
+ + 	return pm_generic_runtime_resume(dev);
+ + }
+ + #endif
+ + 
+ + #ifdef CONFIG_SUSPEND
+ + static int _od_suspend_noirq(struct device *dev)
+ + {
+ + 	struct platform_device *pdev = to_platform_device(dev);
+ + 	struct omap_device *od = to_omap_device(pdev);
+ + 	int ret;
+ + 
+ + 	if (od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND)
+ + 		return pm_generic_suspend_noirq(dev);
+ + 
+ + 	ret = pm_generic_suspend_noirq(dev);
+ + 
+ + 	if (!ret && !pm_runtime_status_suspended(dev)) {
+ + 		if (pm_generic_runtime_suspend(dev) == 0) {
+ + 			omap_device_idle(pdev);
+ + 			od->flags |= OMAP_DEVICE_SUSPENDED;
+ + 		}
+ + 	}
+ + 
+ + 	return ret;
+ + }
+ + 
+ + static int _od_resume_noirq(struct device *dev)
+ + {
+ + 	struct platform_device *pdev = to_platform_device(dev);
+ + 	struct omap_device *od = to_omap_device(pdev);
+ + 
+ + 	if (od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND)
+ + 		return pm_generic_resume_noirq(dev);
+ + 
+ + 	if ((od->flags & OMAP_DEVICE_SUSPENDED) &&
+ + 	    !pm_runtime_status_suspended(dev)) {
+ + 		od->flags &= ~OMAP_DEVICE_SUSPENDED;
+ + 		omap_device_enable(pdev);
+ + 		pm_generic_runtime_resume(dev);
+ + 	}
+ + 
+ + 	return pm_generic_resume_noirq(dev);
+ + }
+ + #else
+ + #define _od_suspend_noirq NULL
+ + #define _od_resume_noirq NULL
+ + #endif
+ + 
+ + static struct dev_pm_domain omap_device_pm_domain = {
+ + 	.ops = {
+ + 		SET_RUNTIME_PM_OPS(_od_runtime_suspend, _od_runtime_resume,
+ + 				   _od_runtime_idle)
+ + 		USE_PLATFORM_PM_SLEEP_OPS
+ + 		.suspend_noirq = _od_suspend_noirq,
+ + 		.resume_noirq = _od_resume_noirq,
+ + 	}
+ + };
+ + 
+ + /**
+ +  * omap_device_register - register an omap_device with one omap_hwmod
+ +  * @od: struct omap_device * to register
+ +  *
+ +  * Register the omap_device structure.  This currently just calls
+ +  * platform_device_register() on the underlying platform_device.
+ +  * Returns the return value of platform_device_register().
+ +  */
+ + int omap_device_register(struct platform_device *pdev)
+ + {
+ + 	pr_debug("omap_device: %s: registering\n", pdev->name);
+ + 
+ + 	pdev->dev.parent = &omap_device_parent;
+ + 	pdev->dev.pm_domain = &omap_device_pm_domain;
+ + 	return platform_device_add(pdev);
+ + }
+ + 
+ + 
+ + /* Public functions for use by device drivers through struct platform_data */
+ + 
+ + /**
+ +  * omap_device_enable - fully activate an omap_device
+ +  * @od: struct omap_device * to activate
+ +  *
+ +  * Do whatever is necessary for the hwmods underlying omap_device @od
+ +  * to be accessible and ready to operate.  This generally involves
+ +  * enabling clocks, setting SYSCONFIG registers; and in the future may
+ +  * involve remuxing pins.  Device drivers should call this function
+ +  * (through platform_data function pointers) where they would normally
+ +  * enable clocks, etc.  Returns -EINVAL if called when the omap_device
+ +  * is already enabled, or passes along the return value of
+ +  * _omap_device_activate().
+ +  */
+ + int omap_device_enable(struct platform_device *pdev)
+ + {
+ + 	int ret;
+ + 	struct omap_device *od;
+ + 
+ + 	od = to_omap_device(pdev);
+ + 
+ + 	if (od->_state == OMAP_DEVICE_STATE_ENABLED) {
+ + 		dev_warn(&pdev->dev,
+ + 			 "omap_device: %s() called from invalid state %d\n",
+ + 			 __func__, od->_state);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	/* Enable everything if we're enabling this device from scratch */
+ + 	if (od->_state == OMAP_DEVICE_STATE_UNKNOWN)
+ + 		od->pm_lat_level = od->pm_lats_cnt;
+ + 
+ + 	ret = _omap_device_activate(od, IGNORE_WAKEUP_LAT);
+ + 
+ + 	od->dev_wakeup_lat = 0;
+ + 	od->_dev_wakeup_lat_limit = UINT_MAX;
+ + 	od->_state = OMAP_DEVICE_STATE_ENABLED;
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * omap_device_idle - idle an omap_device
+ +  * @od: struct omap_device * to idle
+ +  *
+ +  * Idle omap_device @od by calling as many .deactivate_func() entries
+ +  * in the omap_device's pm_lats table as is possible without exceeding
+ +  * the device's maximum wakeup latency limit, pm_lat_limit.  Device
+ +  * drivers should call this function (through platform_data function
+ +  * pointers) where they would normally disable clocks after operations
+ +  * complete, etc..  Returns -EINVAL if the omap_device is not
+ +  * currently enabled, or passes along the return value of
+ +  * _omap_device_deactivate().
+ +  */
+ + int omap_device_idle(struct platform_device *pdev)
+ + {
+ + 	int ret;
+ + 	struct omap_device *od;
+ + 
+ + 	od = to_omap_device(pdev);
+ + 
+ + 	if (od->_state != OMAP_DEVICE_STATE_ENABLED) {
+ + 		dev_warn(&pdev->dev,
+ + 			 "omap_device: %s() called from invalid state %d\n",
+ + 			 __func__, od->_state);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	ret = _omap_device_deactivate(od, USE_WAKEUP_LAT);
+ + 
+ + 	od->_state = OMAP_DEVICE_STATE_IDLE;
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * omap_device_shutdown - shut down an omap_device
+ +  * @od: struct omap_device * to shut down
+ +  *
+ +  * Shut down omap_device @od by calling all .deactivate_func() entries
+ +  * in the omap_device's pm_lats table and then shutting down all of
+ +  * the underlying omap_hwmods.  Used when a device is being "removed"
+ +  * or a device driver is being unloaded.  Returns -EINVAL if the
+ +  * omap_device is not currently enabled or idle, or passes along the
+ +  * return value of _omap_device_deactivate().
+ +  */
+ + int omap_device_shutdown(struct platform_device *pdev)
+ + {
+ + 	int ret, i;
+ + 	struct omap_device *od;
+ + 
+ + 	od = to_omap_device(pdev);
+ + 
+ + 	if (od->_state != OMAP_DEVICE_STATE_ENABLED &&
+ + 	    od->_state != OMAP_DEVICE_STATE_IDLE) {
+ + 		dev_warn(&pdev->dev,
+ + 			 "omap_device: %s() called from invalid state %d\n",
+ + 			 __func__, od->_state);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	ret = _omap_device_deactivate(od, IGNORE_WAKEUP_LAT);
+ + 
+ + 	for (i = 0; i < od->hwmods_cnt; i++)
+ + 		omap_hwmod_shutdown(od->hwmods[i]);
+ + 
+ + 	od->_state = OMAP_DEVICE_STATE_SHUTDOWN;
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * omap_device_align_pm_lat - activate/deactivate device to match wakeup lat lim
+ +  * @od: struct omap_device *
+ +  *
+ +  * When a device's maximum wakeup latency limit changes, call some of
+ +  * the .activate_func or .deactivate_func function pointers in the
+ +  * omap_device's pm_lats array to ensure that the device's maximum
+ +  * wakeup latency is less than or equal to the new latency limit.
+ +  * Intended to be called by OMAP PM code whenever a device's maximum
+ +  * wakeup latency limit changes (e.g., via
+ +  * omap_pm_set_dev_wakeup_lat()).  Returns 0 if nothing needs to be
+ +  * done (e.g., if the omap_device is not currently idle, or if the
+ +  * wakeup latency is already current with the new limit) or passes
+ +  * along the return value of _omap_device_deactivate() or
+ +  * _omap_device_activate().
+ +  */
+ + int omap_device_align_pm_lat(struct platform_device *pdev,
+ + 			     u32 new_wakeup_lat_limit)
+ + {
+ + 	int ret = -EINVAL;
+ + 	struct omap_device *od;
+ + 
+ + 	od = to_omap_device(pdev);
+ + 
+ + 	if (new_wakeup_lat_limit == od->dev_wakeup_lat)
+ + 		return 0;
+ + 
+ + 	od->_dev_wakeup_lat_limit = new_wakeup_lat_limit;
+ + 
+ + 	if (od->_state != OMAP_DEVICE_STATE_IDLE)
+ + 		return 0;
+ + 	else if (new_wakeup_lat_limit > od->dev_wakeup_lat)
+ + 		ret = _omap_device_deactivate(od, USE_WAKEUP_LAT);
+ + 	else if (new_wakeup_lat_limit < od->dev_wakeup_lat)
+ + 		ret = _omap_device_activate(od, USE_WAKEUP_LAT);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + /**
+ +  * omap_device_get_pwrdm - return the powerdomain * associated with @od
+ +  * @od: struct omap_device *
+ +  *
+ +  * Return the powerdomain associated with the first underlying
+ +  * omap_hwmod for this omap_device.  Intended for use by core OMAP PM
+ +  * code.  Returns NULL on error or a struct powerdomain * upon
+ +  * success.
+ +  */
+ + struct powerdomain *omap_device_get_pwrdm(struct omap_device *od)
+ + {
+ + 	/*
+ + 	 * XXX Assumes that all omap_hwmod powerdomains are identical.
+ + 	 * This may not necessarily be true.  There should be a sanity
+ + 	 * check in here to WARN() if any difference appears.
+ + 	 */
+ + 	if (!od->hwmods_cnt)
+ + 		return NULL;
+ + 
+ + 	return omap_hwmod_get_pwrdm(od->hwmods[0]);
+ + }
+ + 
+ + /**
+ +  * omap_device_get_mpu_rt_va - return the MPU's virtual addr for the hwmod base
+ +  * @od: struct omap_device *
+ +  *
+ +  * Return the MPU's virtual address for the base of the hwmod, from
+ +  * the ioremap() that the hwmod code does.  Only valid if there is one
+ +  * hwmod associated with this device.  Returns NULL if there are zero
+ +  * or more than one hwmods associated with this omap_device;
+ +  * otherwise, passes along the return value from
+ +  * omap_hwmod_get_mpu_rt_va().
+ +  */
+ + void __iomem *omap_device_get_rt_va(struct omap_device *od)
+ + {
+ + 	if (od->hwmods_cnt != 1)
+ + 		return NULL;
+ + 
+ + 	return omap_hwmod_get_mpu_rt_va(od->hwmods[0]);
+ + }
+ + 
+ + /**
+ +  * omap_device_get_by_hwmod_name() - convert a hwmod name to
+ +  * device pointer.
+ +  * @oh_name: name of the hwmod device
+ +  *
+ +  * Returns back a struct device * pointer associated with a hwmod
+ +  * device represented by a hwmod_name
+ +  */
+ + struct device *omap_device_get_by_hwmod_name(const char *oh_name)
+ + {
+ + 	struct omap_hwmod *oh;
+ + 
+ + 	if (!oh_name) {
+ + 		WARN(1, "%s: no hwmod name!\n", __func__);
+ + 		return ERR_PTR(-EINVAL);
+ + 	}
+ + 
+ + 	oh = omap_hwmod_lookup(oh_name);
+ + 	if (IS_ERR_OR_NULL(oh)) {
+ + 		WARN(1, "%s: no hwmod for %s\n", __func__,
+ + 			oh_name);
+ + 		return ERR_PTR(oh ? PTR_ERR(oh) : -ENODEV);
+ + 	}
+ + 	if (IS_ERR_OR_NULL(oh->od)) {
+ + 		WARN(1, "%s: no omap_device for %s\n", __func__,
+ + 			oh_name);
+ + 		return ERR_PTR(oh->od ? PTR_ERR(oh->od) : -ENODEV);
+ + 	}
+ + 
+ + 	if (IS_ERR_OR_NULL(oh->od->pdev))
+ + 		return ERR_PTR(oh->od->pdev ? PTR_ERR(oh->od->pdev) : -ENODEV);
+ + 
+ + 	return &oh->od->pdev->dev;
+ + }
+ + EXPORT_SYMBOL(omap_device_get_by_hwmod_name);
+ + 
+ + /*
+ +  * Public functions intended for use in omap_device_pm_latency
+ +  * .activate_func and .deactivate_func function pointers
+ +  */
+ + 
+ + /**
+ +  * omap_device_enable_hwmods - call omap_hwmod_enable() on all hwmods
+ +  * @od: struct omap_device *od
+ +  *
+ +  * Enable all underlying hwmods.  Returns 0.
+ +  */
+ + int omap_device_enable_hwmods(struct omap_device *od)
+ + {
+ + 	int i;
+ + 
+ + 	for (i = 0; i < od->hwmods_cnt; i++)
+ + 		omap_hwmod_enable(od->hwmods[i]);
+ + 
+ + 	/* XXX pass along return value here? */
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * omap_device_idle_hwmods - call omap_hwmod_idle() on all hwmods
+ +  * @od: struct omap_device *od
+ +  *
+ +  * Idle all underlying hwmods.  Returns 0.
+ +  */
+ + int omap_device_idle_hwmods(struct omap_device *od)
+ + {
+ + 	int i;
+ + 
+ + 	for (i = 0; i < od->hwmods_cnt; i++)
+ + 		omap_hwmod_idle(od->hwmods[i]);
+ + 
+ + 	/* XXX pass along return value here? */
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * omap_device_disable_clocks - disable all main and interface clocks
+ +  * @od: struct omap_device *od
+ +  *
+ +  * Disable the main functional clock and interface clock for all of the
+ +  * omap_hwmods associated with the omap_device.  Returns 0.
+ +  */
+ + int omap_device_disable_clocks(struct omap_device *od)
+ + {
+ + 	int i;
+ + 
+ + 	for (i = 0; i < od->hwmods_cnt; i++)
+ + 		omap_hwmod_disable_clocks(od->hwmods[i]);
+ + 
+ + 	/* XXX pass along return value here? */
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * omap_device_enable_clocks - enable all main and interface clocks
+ +  * @od: struct omap_device *od
+ +  *
+ +  * Enable the main functional clock and interface clock for all of the
+ +  * omap_hwmods associated with the omap_device.  Returns 0.
+ +  */
+ + int omap_device_enable_clocks(struct omap_device *od)
+ + {
+ + 	int i;
+ + 
+ + 	for (i = 0; i < od->hwmods_cnt; i++)
+ + 		omap_hwmod_enable_clocks(od->hwmods[i]);
+ + 
+ + 	/* XXX pass along return value here? */
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * omap_device_reset - reset the module.
+ +  * @dev: struct device *
+ +  *
+ +  * Reset all the hwmods associated with the device @dev.
+ +  */
+ + int omap_device_reset(struct device *dev)
+ + {
+ + 	int r = 0;
+ + 	int i;
+ + 	struct platform_device *pdev = to_platform_device(dev);
+ + 	struct omap_device *odev = to_omap_device(pdev);
+ + 	struct omap_hwmod *oh;
+ + 
+ + 	for (i = 0; i < odev->hwmods_cnt; i++) {
+ + 		oh = odev->hwmods[i];
+ + 		r |= omap_hwmod_reset(oh);
+ + 	}
+ + 	return r;
+ + }
+ + 
+ + 
+ + struct device omap_device_parent = {
+ + 	.init_name	= "omap",
+ + 	.parent         = &platform_bus,
+ + };
+ + 
+ + static struct notifier_block platform_nb = {
+ + 	.notifier_call = _omap_device_notifier_call,
+ + };
+ + 
+ + static int __init omap_device_init(void)
+ + {
+ + 	bus_register_notifier(&platform_bus_type, &platform_nb);
+ + 	return device_register(&omap_device_parent);
+ + }
+ + core_initcall(omap_device_init);
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/omap-pm-noop.c linux-3.2.1/arch/arm/plat-ckb/omap-pm-noop.c
+ *** linux-3.2.1_o/arch/arm/plat-ckb/omap-pm-noop.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/omap-pm-noop.c	2014-11-25 13:19:15.307035517 +0900
+ ***************
+ *** 0 ****
+ --- 1,363 ----
+ + /*
+ +  * omap-pm-noop.c - OMAP power management interface - dummy version
+ +  *
+ +  * This code implements the OMAP power management interface to
+ +  * drivers, CPUIdle, CPUFreq, and DSP Bridge.  It is strictly for
+ +  * debug/demonstration use, as it does nothing but printk() whenever a
+ +  * function is called (when DEBUG is defined, below)
+ +  *
+ +  * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ +  * Copyright (C) 2008-2009 Nokia Corporation
+ +  * Paul Walmsley
+ +  *
+ +  * Interface developed by (in alphabetical order):
+ +  * Karthik Dasu, Tony Lindgren, Rajendra Nayak, Sakari Poussa, Veeramanikandan
+ +  * Raju, Anand Sawant, Igor Stoppa, Paul Walmsley, Richard Woodruff
+ +  */
+ + 
+ + #undef DEBUG
+ + 
+ + #include <linux/init.h>
+ + #include <linux/cpufreq.h>
+ + #include <linux/device.h>
+ + #include <linux/platform_device.h>
+ + 
+ + /* Interface documentation is in mach/omap-pm.h */
+ + #include <plat/omap-pm.h>
+ + #include <plat/omap_device.h>
+ + 
+ + static bool off_mode_enabled;
+ + static int dummy_context_loss_counter;
+ + 
+ + /*
+ +  * Device-driver-originated constraints (via board-*.c files)
+ +  */
+ + 
+ + int omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t)
+ + {
+ + 	if (!dev || t < -1) {
+ + 		WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
+ + 		return -EINVAL;
+ + 	};
+ + 
+ + 	if (t == -1)
+ + 		pr_debug("OMAP PM: remove max MPU wakeup latency constraint: "
+ + 			 "dev %s\n", dev_name(dev));
+ + 	else
+ + 		pr_debug("OMAP PM: add max MPU wakeup latency constraint: "
+ + 			 "dev %s, t = %ld usec\n", dev_name(dev), t);
+ + 
+ + 	/*
+ + 	 * For current Linux, this needs to map the MPU to a
+ + 	 * powerdomain, then go through the list of current max lat
+ + 	 * constraints on the MPU and find the smallest.  If
+ + 	 * the latency constraint has changed, the code should
+ + 	 * recompute the state to enter for the next powerdomain
+ + 	 * state.
+ + 	 *
+ + 	 * TI CDP code can call constraint_set here.
+ + 	 */
+ + 
+ + 	return 0;
+ + }
+ + 
+ + int omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r)
+ + {
+ + 	if (!dev || (agent_id != OCP_INITIATOR_AGENT &&
+ + 	    agent_id != OCP_TARGET_AGENT)) {
+ + 		WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
+ + 		return -EINVAL;
+ + 	};
+ + 
+ + 	if (r == 0)
+ + 		pr_debug("OMAP PM: remove min bus tput constraint: "
+ + 			 "dev %s for agent_id %d\n", dev_name(dev), agent_id);
+ + 	else
+ + 		pr_debug("OMAP PM: add min bus tput constraint: "
+ + 			 "dev %s for agent_id %d: rate %ld KiB\n",
+ + 			 dev_name(dev), agent_id, r);
+ + 
+ + 	/*
+ + 	 * This code should model the interconnect and compute the
+ + 	 * required clock frequency, convert that to a VDD2 OPP ID, then
+ + 	 * set the VDD2 OPP appropriately.
+ + 	 *
+ + 	 * TI CDP code can call constraint_set here on the VDD2 OPP.
+ + 	 */
+ + 
+ + 	return 0;
+ + }
+ + 
+ + int omap_pm_set_max_dev_wakeup_lat(struct device *req_dev, struct device *dev,
+ + 				   long t)
+ + {
+ + 	if (!req_dev || !dev || t < -1) {
+ + 		WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
+ + 		return -EINVAL;
+ + 	};
+ + 
+ + 	if (t == -1)
+ + 		pr_debug("OMAP PM: remove max device latency constraint: "
+ + 			 "dev %s\n", dev_name(dev));
+ + 	else
+ + 		pr_debug("OMAP PM: add max device latency constraint: "
+ + 			 "dev %s, t = %ld usec\n", dev_name(dev), t);
+ + 
+ + 	/*
+ + 	 * For current Linux, this needs to map the device to a
+ + 	 * powerdomain, then go through the list of current max lat
+ + 	 * constraints on that powerdomain and find the smallest.  If
+ + 	 * the latency constraint has changed, the code should
+ + 	 * recompute the state to enter for the next powerdomain
+ + 	 * state.  Conceivably, this code should also determine
+ + 	 * whether to actually disable the device clocks or not,
+ + 	 * depending on how long it takes to re-enable the clocks.
+ + 	 *
+ + 	 * TI CDP code can call constraint_set here.
+ + 	 */
+ + 
+ + 	return 0;
+ + }
+ + 
+ + int omap_pm_set_max_sdma_lat(struct device *dev, long t)
+ + {
+ + 	if (!dev || t < -1) {
+ + 		WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
+ + 		return -EINVAL;
+ + 	};
+ + 
+ + 	if (t == -1)
+ + 		pr_debug("OMAP PM: remove max DMA latency constraint: "
+ + 			 "dev %s\n", dev_name(dev));
+ + 	else
+ + 		pr_debug("OMAP PM: add max DMA latency constraint: "
+ + 			 "dev %s, t = %ld usec\n", dev_name(dev), t);
+ + 
+ + 	/*
+ + 	 * For current Linux PM QOS params, this code should scan the
+ + 	 * list of maximum CPU and DMA latencies and select the
+ + 	 * smallest, then set cpu_dma_latency pm_qos_param
+ + 	 * accordingly.
+ + 	 *
+ + 	 * For future Linux PM QOS params, with separate CPU and DMA
+ + 	 * latency params, this code should just set the dma_latency param.
+ + 	 *
+ + 	 * TI CDP code can call constraint_set here.
+ + 	 */
+ + 
+ + 	return 0;
+ + }
+ + 
+ + int omap_pm_set_min_clk_rate(struct device *dev, struct clk *c, long r)
+ + {
+ + 	if (!dev || !c || r < 0) {
+ + 		WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	if (r == 0)
+ + 		pr_debug("OMAP PM: remove min clk rate constraint: "
+ + 			 "dev %s\n", dev_name(dev));
+ + 	else
+ + 		pr_debug("OMAP PM: add min clk rate constraint: "
+ + 			 "dev %s, rate = %ld Hz\n", dev_name(dev), r);
+ + 
+ + 	/*
+ + 	 * Code in a real implementation should keep track of these
+ + 	 * constraints on the clock, and determine the highest minimum
+ + 	 * clock rate.  It should iterate over each OPP and determine
+ + 	 * whether the OPP will result in a clock rate that would
+ + 	 * satisfy this constraint (and any other PM constraint in effect
+ + 	 * at that time).  Once it finds the lowest-voltage OPP that
+ + 	 * meets those conditions, it should switch to it, or return
+ + 	 * an error if the code is not capable of doing so.
+ + 	 */
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /*
+ +  * DSP Bridge-specific constraints
+ +  */
+ + 
+ + const struct omap_opp *omap_pm_dsp_get_opp_table(void)
+ + {
+ + 	pr_debug("OMAP PM: DSP request for OPP table\n");
+ + 
+ + 	/*
+ + 	 * Return DSP frequency table here:  The final item in the
+ + 	 * array should have .rate = .opp_id = 0.
+ + 	 */
+ + 
+ + 	return NULL;
+ + }
+ + 
+ + void omap_pm_dsp_set_min_opp(u8 opp_id)
+ + {
+ + 	if (opp_id == 0) {
+ + 		WARN_ON(1);
+ + 		return;
+ + 	}
+ + 
+ + 	pr_debug("OMAP PM: DSP requests minimum VDD1 OPP to be %d\n", opp_id);
+ + 
+ + 	/*
+ + 	 *
+ + 	 * For l-o dev tree, our VDD1 clk is keyed on OPP ID, so we
+ + 	 * can just test to see which is higher, the CPU's desired OPP
+ + 	 * ID or the DSP's desired OPP ID, and use whichever is
+ + 	 * highest.
+ + 	 *
+ + 	 * In CDP12.14+, the VDD1 OPP custom clock that controls the DSP
+ + 	 * rate is keyed on MPU speed, not the OPP ID.  So we need to
+ + 	 * map the OPP ID to the MPU speed for use with clk_set_rate()
+ + 	 * if it is higher than the current OPP clock rate.
+ + 	 *
+ + 	 */
+ + }
+ + 
+ + 
+ + u8 omap_pm_dsp_get_opp(void)
+ + {
+ + 	pr_debug("OMAP PM: DSP requests current DSP OPP ID\n");
+ + 
+ + 	/*
+ + 	 * For l-o dev tree, call clk_get_rate() on VDD1 OPP clock
+ + 	 *
+ + 	 * CDP12.14+:
+ + 	 * Call clk_get_rate() on the OPP custom clock, map that to an
+ + 	 * OPP ID using the tables defined in board-*.c/chip-*.c files.
+ + 	 */
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /*
+ +  * CPUFreq-originated constraint
+ +  *
+ +  * In the future, this should be handled by custom OPP clocktype
+ +  * functions.
+ +  */
+ + 
+ + struct cpufreq_frequency_table **omap_pm_cpu_get_freq_table(void)
+ + {
+ + 	pr_debug("OMAP PM: CPUFreq request for frequency table\n");
+ + 
+ + 	/*
+ + 	 * Return CPUFreq frequency table here: loop over
+ + 	 * all VDD1 clkrates, pull out the mpu_ck frequencies, build
+ + 	 * table
+ + 	 */
+ + 
+ + 	return NULL;
+ + }
+ + 
+ + void omap_pm_cpu_set_freq(unsigned long f)
+ + {
+ + 	if (f == 0) {
+ + 		WARN_ON(1);
+ + 		return;
+ + 	}
+ + 
+ + 	pr_debug("OMAP PM: CPUFreq requests CPU frequency to be set to %lu\n",
+ + 		 f);
+ + 
+ + 	/*
+ + 	 * For l-o dev tree, determine whether MPU freq or DSP OPP id
+ + 	 * freq is higher.  Find the OPP ID corresponding to the
+ + 	 * higher frequency.  Call clk_round_rate() and clk_set_rate()
+ + 	 * on the OPP custom clock.
+ + 	 *
+ + 	 * CDP should just be able to set the VDD1 OPP clock rate here.
+ + 	 */
+ + }
+ + 
+ + unsigned long omap_pm_cpu_get_freq(void)
+ + {
+ + 	pr_debug("OMAP PM: CPUFreq requests current CPU frequency\n");
+ + 
+ + 	/*
+ + 	 * Call clk_get_rate() on the mpu_ck.
+ + 	 */
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * omap_pm_enable_off_mode - notify OMAP PM that off-mode is enabled
+ +  *
+ +  * Intended for use only by OMAP PM core code to notify this layer
+ +  * that off mode has been enabled.
+ +  */
+ + void omap_pm_enable_off_mode(void)
+ + {
+ + 	off_mode_enabled = true;
+ + }
+ + 
+ + /**
+ +  * omap_pm_disable_off_mode - notify OMAP PM that off-mode is disabled
+ +  *
+ +  * Intended for use only by OMAP PM core code to notify this layer
+ +  * that off mode has been disabled.
+ +  */
+ + void omap_pm_disable_off_mode(void)
+ + {
+ + 	off_mode_enabled = false;
+ + }
+ + 
+ + /*
+ +  * Device context loss tracking
+ +  */
+ + 
+ + int omap_pm_get_dev_context_loss_count(struct device *dev)
+ + {
+ + 	struct platform_device *pdev = to_platform_device(dev);
+ + 	int count;
+ + 
+ + 	if (WARN_ON(!dev))
+ + 		return -ENODEV;
+ + 
+ + 	if (dev->parent == &omap_device_parent) {
+ + 		count = omap_device_get_context_loss_count(pdev);
+ + 	} else {
+ + 		WARN_ONCE(off_mode_enabled, "omap_pm: using dummy context loss counter; device %s should be converted to omap_device",
+ + 			  dev_name(dev));
+ + 
+ + 		count = dummy_context_loss_counter;
+ + 
+ + 		if (off_mode_enabled) {
+ + 			count++;
+ + 			/*
+ + 			 * Context loss count has to be a non-negative value.
+ + 			 * Clear the sign bit to get a value range from 0 to
+ + 			 * INT_MAX.
+ + 			 */
+ + 			count &= INT_MAX;
+ + 			dummy_context_loss_counter = count;
+ + 		}
+ + 	}
+ + 
+ + 	pr_debug("OMAP PM: context loss count for dev %s = %d\n",
+ + 		 dev_name(dev), count);
+ + 
+ + 	return count;
+ + }
+ + 
+ + 
+ + /* Should be called before clk framework init */
+ + int __init omap_pm_if_early_init(void)
+ + {
+ + 	return 0;
+ + }
+ + 
+ + /* Must be called after clock framework is initialized */
+ + int __init omap_pm_if_init(void)
+ + {
+ + 	return 0;
+ + }
+ + 
+ + void omap_pm_if_exit(void)
+ + {
+ + 	/* Deallocate CPUFreq frequency table here */
+ + }
+ + 
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/sdma2edma.c linux-3.2.1/arch/arm/plat-ckb/sdma2edma.c
+ *** linux-3.2.1_o/arch/arm/plat-ckb/sdma2edma.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/sdma2edma.c	2014-11-25 13:19:15.311791393 +0900
+ ***************
+ *** 0 ****
+ --- 1,358 ----
+ + /*
+ +  * sdma2edma.c
+ +  *
+ +  * SDMA to EDMA3 Wrapper.
+ +  *
+ +  * NOTE: Since we are invoking EDMA API, comments for all APIs in this file
+ +  * are EDMA specific.
+ +  *
+ +  * Copyright (C) 2010-2011 Texas Instruments.
+ +  * Author: Mansoor Ahamed <mansoor.ahamed@ti.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; either version 2 of the License, or
+ +  * (at your option) any later version.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ +  */
+ + 
+ + #include <linux/module.h>
+ + #include <linux/init.h>
+ + #include <linux/sched.h>
+ + #include <linux/spinlock.h>
+ + #include <linux/errno.h>
+ + #include <linux/interrupt.h>
+ + #include <linux/irq.h>
+ + #include <linux/io.h>
+ + 
+ + #include <asm/system.h>
+ + #include <mach/hardware.h>
+ + #include <plat/dma.h>
+ + 
+ + /* some edma specific hacks which might change */
+ + #include <mach/edma.h>
+ + 
+ + /**
+ +  * omap_request_dma - allocate DMA channel and paired parameter RAM
+ +  * @dev_id: specific channel to allocate; negative for "any unmapped channel"
+ +  * @callback: optional; to be issued on DMA completion or errors
+ +  * @data: passed to callback
+ +  * @dma_ch_out: allocated channel number returned in this variable
+ +  *
+ +  * This allocates a DMA channel and its associated parameter RAM slot.
+ +  * The parameter RAM is initialized to hold a dummy transfer.
+ +  *
+ +  * Normal use is to pass a specific channel number as @channel, to make
+ +  * use of hardware events mapped to that channel.  When the channel will
+ +  * be used only for software triggering or event chaining, channels not
+ +  * mapped to hardware events (or mapped to unused events) are preferable.
+ +  *
+ +  * DMA transfers start from a channel using edma_start(), or by
+ +  * chaining.  When the transfer described in that channel's parameter RAM
+ +  * slot completes, that slot's data may be reloaded through a link.
+ +  *
+ +  * DMA errors are only reported to the @callback associated with the
+ +  * channel driving that transfer, but transfer completion callbacks can
+ +  * be sent to another channel under control of the TCC field in
+ +  * the option word of the transfer's parameter RAM set.  Drivers must not
+ +  * use DMA transfer completion callbacks for channels they did not allocate.
+ +  * (The same applies to TCC codes used in transfer chaining.)
+ +  *
+ +  * TODO: -
+ +  * . In the edma call, last param i.e TC hard coded to EVENTQ_2
+ +  * . The callback's ch_status which should be used in McSPI driver
+ +  *   to stop/clean EDMA is currently ignored in some driver (eg. McSPI)
+ +  */
+ + int omap_request_dma(int dev_id, const char *dev_name,
+ + 		void (*callback)(int lch, u16 ch_status, void *data),
+ + 		void *data, int *dma_ch_out)
+ + {
+ + 	struct edmacc_param p_ram;
+ + 	typedef void (*EDMA_CALLBACK)(unsigned, u16, void*);
+ + 	EDMA_CALLBACK edma_callback = (EDMA_CALLBACK)(callback);
+ + 
+ + 	*dma_ch_out = edma_alloc_channel(dev_id, edma_callback, data, EVENTQ_2);
+ + 	if (*dma_ch_out < 0)
+ + 		return -1;
+ + 
+ + 	/* enable interrupts */
+ + 	edma_read_slot(*dma_ch_out, &p_ram);
+ + 	p_ram.opt |= TCINTEN | EDMA_TCC(EDMA_CHAN_SLOT(*dma_ch_out));
+ + 	edma_write_slot(*dma_ch_out, &p_ram);
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(omap_request_dma);
+ + 
+ + /**
+ +  * omap_free_dma - deallocate DMA channel
+ +  * @lch: dma channel returned from edma_alloc_channel()
+ +  *
+ +  * This deallocates the DMA channel and associated parameter RAM slot
+ +  * allocated by omap_request_dma().
+ +  *
+ +  * Callers are responsible for ensuring the channel is inactive, and
+ +  * will not be reactivated by linking, chaining, or software calls to
+ +  * omap_start_dma().
+ +  */
+ + void omap_free_dma(int lch)
+ + {
+ + 	edma_free_channel((unsigned)lch);
+ + }
+ + EXPORT_SYMBOL(omap_free_dma);
+ + 
+ + /**
+ +  * omap_start_dma - start dma on a channel
+ +  * @lch: channel being activated
+ +  *
+ +  * Channels with event associations will be triggered by their hardware
+ +  * events, and channels without such associations will be triggered by
+ +  * software.  (At this writing there is no interface for using software
+ +  * triggers except with channels that don't support hardware triggers.)
+ +  *
+ +  */
+ + void omap_start_dma(int lch)
+ + {
+ + 	edma_start((unsigned)lch);
+ + }
+ + EXPORT_SYMBOL(omap_start_dma);
+ + 
+ + /**
+ +  * omap_stop_dma - stops dma on the channel passed
+ +  * @lch: channel being deactivated
+ +  *
+ +  * When @lch is a channel, any active transfer is paused and
+ +  * all pending hardware events are cleared.  The current transfer
+ +  * may not be resumed, and the channel's Parameter RAM should be
+ +  * reinitialized before being reused.
+ +  */
+ + void omap_stop_dma(int lch)
+ + {
+ + 	edma_stop((unsigned)lch);
+ + }
+ + EXPORT_SYMBOL(omap_stop_dma);
+ + 
+ + /**
+ +  * omap_cleanup_dma - Bring back DMA to initial state
+ +  * @lch: channel being cleaned up
+ +  *
+ +  * It cleans ParamEntry and bring back EDMA to initial state if media has
+ +  * been removed before EDMA has finished.It is usedful for removable media.
+ +  *
+ +  *
+ +  * FIXME this should not be needed ... edma_stop() should suffice.
+ +  *
+ +  */
+ + void omap_cleanup_dma(int lch)
+ + {
+ + 	edma_clean_channel((unsigned)lch);
+ + }
+ + EXPORT_SYMBOL(omap_cleanup_dma);
+ + 
+ + /**
+ +  * omap_set_dma_transfer_params - configure DMA transfer parameters
+ +  * @lch: parameter RAM slot being configured
+ +  * @data_type: how many bytes per array (at least one)
+ +  * @elem_count: how many arrays per frame (at least one)
+ +  * @frame_count: how many frames per block (at least one)
+ +  * @sync_mode: ASYNC or ABSYNC
+ +  * @dma_trigger: device id (not used)
+ +  * @src_or_dst_synch: not used
+ +  *
+ +  * See the EDMA3 documentation to understand how to configure and link
+ +  * transfers using the fields in PaRAM slots.  If you are not doing it
+ +  * all at once with edma_write_slot(), you will use this routine
+ +  * plus two calls each for source and destination, setting the initial
+ +  * address and saying how to index that address.
+ +  *
+ +  * An example of an A-Synchronized transfer is a serial link using a
+ +  * single word shift register.  In that case, @acnt would be equal to
+ +  * that word size; the serial controller issues a DMA synchronization
+ +  * event to transfer each word, and memory access by the DMA transfer
+ +  * controller will be word-at-a-time.
+ +  *
+ +  * An example of an AB-Synchronized transfer is a device using a FIFO.
+ +  * In that case, @acnt equals the FIFO width and @bcnt equals its depth.
+ +  * The controller with the FIFO issues DMA synchronization events when
+ +  * the FIFO threshold is reached, and the DMA transfer controller will
+ +  * transfer one frame to (or from) the FIFO.  It will probably use
+ +  * efficient burst modes to access memory.
+ +  *
+ +  * . dma_trigger and channel number, this is ignored for EDMA
+ +  * . Setting bcnt_rld same as bcnt
+ +  * TODO
+ +  * . what is src_or_dst_synch?
+ +  */
+ + void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
+ + 			int frame_count, int sync_mode,
+ + 			int dma_trigger, int src_or_dst_synch)
+ + {
+ + 	int d_type[3] = {1, 2, 4};
+ + 	if ((enum sync_dimension)sync_mode > ABSYNC) {
+ + 		printk(KERN_ERR "SDMA2EDMA: Line:%d : Param \'sync_mode\' out"
+ + 				" of range\n", __LINE__);
+ + 		return;
+ + 	}
+ + 
+ + 	/* translate data_type */
+ + 	data_type = d_type[data_type];
+ + 
+ + 	edma_set_transfer_params(lch, (u16)data_type, (u16)elem_count,
+ + 					(u16)frame_count, (u16)elem_count,
+ + 					(enum sync_dimension)sync_mode);
+ + }
+ + EXPORT_SYMBOL(omap_set_dma_transfer_params);
+ + 
+ + /**
+ +  * omap_set_dma_dest_params - Set initial DMA destination addr in param RAM slot
+ +  * @lch: parameter RAM slot being configured
+ +  * @dest_port: not used
+ +  * @dest_amode: INCR, except in very rare cases
+ +  * @dest_start: physical address of destination (memory, controller FIFO, etc)
+ +  * @dst_ei: byte offset between destination arrays in a frame
+ +  * @dst_fi: byte offset between destination frames in a block
+ +  *
+ +  * Note that the destination address is modified during the DMA transfer
+ +  * according to edma_set_dest_index().
+ +  *
+ +  * TODO
+ +  * . Not sure about dst_ei and dst_fi
+ +  * . fifo_width for edma is not available in sdma API hence setting it to
+ +  *   W8BIT
+ +  * . dest_port is ignored
+ +  */
+ + void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
+ + 			unsigned long dest_start, int dst_ei, int dst_fi)
+ + {
+ + 	if ((enum address_mode)dest_amode > FIFO) {
+ + 		printk(KERN_ERR "SDMA2EDMA: Line:%d : Param \'dest_amode\' out"
+ + 				" of range\n", __LINE__);
+ + 		return;
+ + 	}
+ + 
+ + 	edma_set_dest((unsigned)lch, (dma_addr_t)dest_start,
+ + 					!dest_amode, W32BIT);
+ + 	edma_set_dest_index((unsigned)(lch), (s16)dst_ei, (s16)dst_fi);
+ + }
+ + EXPORT_SYMBOL(omap_set_dma_dest_params);
+ + 
+ + /**
+ +  * omap_set_dma_src_params - Set initial DMA source addr in param RAM slot
+ +  * @lch: parameter RAM slot being configured
+ +  * @src_port: not used
+ +  * @src_amode: INCR, except in very rare cases
+ +  * @src_start: physical address of destination (memory, controller FIFO, etc)
+ +  * @src_ei: byte offset between destination arrays in a frame
+ +  * @src_fi: byte offset between destination frames in a block
+ +  *
+ +  * Note that the source address is modified during the DMA transfer
+ +  * according to edma_set_src_index().
+ +  *
+ +  * TODO
+ +  * . Not sure about src_ei and src_fi
+ +  * . fifo_width for edma is not available in sdma API hence setting it to
+ +  *   W8BIT
+ +  * . src_port is ignored
+ +  */
+ + void omap_set_dma_src_params(int lch, int src_port, int src_amode,
+ + 			unsigned long src_start, int src_ei, int src_fi)
+ + {
+ + 	if ((enum address_mode)src_amode > FIFO) {
+ + 		printk(KERN_ERR "SDMA2EDMA: Line:%d : Param \'src_amode\' out "
+ + 				"of range\n", __LINE__);
+ + 		return;
+ + 	}
+ + 
+ + 	edma_set_src((unsigned)lch, (dma_addr_t)src_start,
+ + 					!src_amode, W32BIT);
+ + 	edma_set_src_index((unsigned)(lch), (s16)src_ei, (s16)src_fi);
+ + }
+ + EXPORT_SYMBOL(omap_set_dma_src_params);
+ + 
+ + void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
+ + {
+ + 	printk(KERN_WARNING "omap_set_dma_src_burst_mode: un-supported SDMA"
+ + 				" wrapper\n");
+ + }
+ + EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
+ + 
+ + void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
+ + {
+ + 	printk(KERN_WARNING "omap_set_dma_dest_burst_mode: un-supported SDMA"
+ + 				" wrapper\n");
+ + }
+ + EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
+ + 
+ + dma_addr_t omap_get_dma_dst_pos(int lch)
+ + {
+ + 	printk(KERN_WARNING "omap_get_dma_dst_pos: un-supported in SDMA"
+ + 				" wrapper\n");
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(omap_get_dma_dst_pos);
+ + 
+ + int omap_get_dma_active_status(int lch)
+ + {
+ + 	printk(KERN_WARNING "omap_get_dma_active_status: un-supported in SDMA"
+ + 				" wrapper\n");
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(omap_get_dma_active_status);
+ + 
+ + void omap_dma_global_context_save(void)
+ + {
+ + 	printk(KERN_WARNING "omap_dma_global_context_save: un-supported in SDMA"
+ + 				" wrapper\n");
+ + }
+ + EXPORT_SYMBOL(omap_dma_global_context_save);
+ + 
+ + void omap_dma_global_context_restore(void)
+ + {
+ + 	printk(KERN_WARNING "omap_dma_global_context_restore: un-supported in"
+ + 				"SDMA wrapper\n");
+ + }
+ + EXPORT_SYMBOL(omap_dma_global_context_restore);
+ + 
+ + int omap_dma_running(void)
+ + {
+ + 	printk(KERN_WARNING "omap_dma_running: un-supported in SDMA wrapper\n");
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(omap_dma_running);
+ + 
+ + void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
+ + {
+ + 	printk(KERN_WARNING "omap_set_dma_color_mode: un-supported in"
+ + 				"SDMA wrapper\n");
+ + }
+ + EXPORT_SYMBOL(omap_set_dma_color_mode);
+ + 
+ + void omap_set_dma_dest_data_pack(int lch, int enable)
+ + {
+ + 	printk(KERN_WARNING "omap_set_dma_dest_data_pack: un-supported in"
+ + 				"SDMA wrapper\n");
+ + }
+ + EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
+ + 
+ + void omap_set_dma_src_data_pack(int lch, int enable)
+ + {
+ + 	printk(KERN_WARNING "omap_set_dma_src_data_pack: un-supported in"
+ + 				"SDMA wrapper\n");
+ + }
+ + EXPORT_SYMBOL(omap_set_dma_src_data_pack);
+ + 
+ + void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
+ + {
+ + 	printk(KERN_WARNING "omap_set_dma_write_mode: un-supported in"
+ + 				"SDMA wrapper\n");
+ + }
+ + EXPORT_SYMBOL(omap_set_dma_write_mode);
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/sram.c linux-3.2.1/arch/arm/plat-ckb/sram.c
+ *** linux-3.2.1_o/arch/arm/plat-ckb/sram.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/sram.c	2014-11-25 13:19:15.311791393 +0900
+ ***************
+ *** 0 ****
+ --- 1,153 ----
+ + /*
+ +  * linux/arch/arm/plat-omap/sram.c
+ +  *
+ +  * OMAP SRAM detection and management
+ +  *
+ +  * Copyright (C) 2005 Nokia Corporation
+ +  * Written by Tony Lindgren <tony@atomide.com>
+ +  *
+ +  * Copyright (C) 2009 Texas Instruments
+ +  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + #undef DEBUG
+ + 
+ + #include <linux/module.h>
+ + #include <linux/kernel.h>
+ + #include <linux/init.h>
+ + #include <linux/io.h>
+ + 
+ + #include <asm/tlb.h>
+ + #include <asm/cacheflush.h>
+ + 
+ + #include <asm/mach/map.h>
+ + 
+ + #include <plat/sram.h>
+ + #include <plat/board.h>
+ + #include <plat/cpu.h>
+ + 
+ + #include "sram.h"
+ + 
+ + /* XXX These "sideways" includes are a sign that something is wrong */
+ + //# include "../mach-omap2/prm2xxx_3xxx.h"
+ + # include "../mach-ckb_3352/sdrc.h"
+ + 
+ + #define SRAM_BOOTLOADER_SZ	0x00
+ + 
+ + #define GP_DEVICE		0x300
+ + 
+ + #define ROUND_DOWN(value,boundary)	((value) & (~((boundary)-1)))
+ + 
+ + static unsigned long omap_sram_start;
+ + static void __iomem *omap_sram_base;
+ + static unsigned long omap_sram_size;
+ + 
+ + 
+ + struct gen_pool *omap_gen_pool;
+ + EXPORT_SYMBOL_GPL(omap_gen_pool);
+ + 
+ + /*
+ +  * The amount of SRAM depends on the core type.
+ +  * Note that we cannot try to test for SRAM here because writes
+ +  * to secure SRAM will hang the system. Also the SRAM is not
+ +  * yet mapped at this point.
+ +  */
+ + static void __init omap_detect_sram(void)
+ + {
+ + #if 0
+ + 	if (is_sram_locked()) {
+ + 		omap_sram_start = OMAP2_SRAM_PUB_PA;
+ + 		omap_sram_size = 0x800; /* 2K */
+ + 	} else {
+ + 		omap_sram_start = AM33XX_SRAM_PA;
+ + 		omap_sram_size = 0x10000; /* 64K */
+ + 	}
+ + #else
+ + 	omap_sram_start = OMAP3_SUSPEND_SRAM_PA;
+ + 	omap_sram_size = 0x6400; /* 25K */
+ + #endif
+ + }
+ + 
+ + /*
+ +  * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
+ +  */
+ + static void __init omap_map_sram(void)
+ + {
+ + 	if (omap_sram_size == 0)
+ + 		return;
+ + 
+ + 	/*
+ + 	 * SRAM must be marked as non-cached on OMAP3 since the
+ + 	 * CORE DPLL M2 divider change code (in SRAM) runs with the
+ + 	 * SDRAM controller disabled, and if it is marked cached,
+ + 	 * the ARM may attempt to write cache lines back to SDRAM
+ + 	 * which will cause the system to hang.
+ + 	 */
+ + 
+ + 	omap_sram_start = ROUND_DOWN(omap_sram_start, PAGE_SIZE);
+ + 	omap_sram_base = __arm_ioremap_exec(omap_sram_start, omap_sram_size,
+ + 						0);
+ + 	if (!omap_sram_base) {
+ + 		pr_err("SRAM: Could not map\n");
+ + 		return;
+ + 	}
+ + 
+ + 	/*
+ + 	 * Looks like we need to preserve some bootloader code at the
+ + 	 * beginning of SRAM for jumping to flash for reboot to work...
+ + 	 */
+ + 	memset((void *)omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
+ + 	       omap_sram_size - SRAM_BOOTLOADER_SZ);
+ + 	{
+ + 		/* The first SRAM_BOOTLOADER_SZ of SRAM are reserved */
+ + 		void *base = (void *)omap_sram_base + SRAM_BOOTLOADER_SZ;
+ + 		phys_addr_t phys = omap_sram_start + SRAM_BOOTLOADER_SZ;
+ + 		size_t len = omap_sram_size - SRAM_BOOTLOADER_SZ;
+ + 
+ + 		omap_gen_pool = gen_pool_create(ilog2(FNCPY_ALIGN), -1);
+ + 		if (omap_gen_pool)
+ + 			WARN_ON(gen_pool_add_virt(omap_gen_pool,
+ + 					(unsigned long)base, phys, len, -1));
+ + 		WARN_ON(!omap_gen_pool);
+ + 	}
+ + }
+ + 
+ + static u32 (*_omap3_sram_configure_core_dpll)(
+ + 			u32 m2, u32 unlock_dll, u32 f, u32 inc,
+ + 			u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
+ + 			u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
+ + 			u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
+ + 			u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
+ + 
+ + u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
+ + 			u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
+ + 			u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
+ + 			u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
+ + 			u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
+ + {
+ + 	BUG_ON(!_omap3_sram_configure_core_dpll);
+ + 	return _omap3_sram_configure_core_dpll(
+ + 			m2, unlock_dll, f, inc,
+ + 			sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
+ + 			sdrc_actim_ctrl_b_0, sdrc_mr_0,
+ + 			sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
+ + 			sdrc_actim_ctrl_b_1, sdrc_mr_1);
+ + }
+ + 
+ + static inline int am33xx_sram_init(void)
+ + {
+ + 	am33xx_push_sram_idle();
+ + 	return 0;
+ + }
+ + 
+ + int __init omap_sram_init(void)
+ + {
+ + 	omap_detect_sram();
+ + 	omap_map_sram();
+ + 	am33xx_sram_init();
+ + 
+ + 	return 0;
+ + }
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/sram.h linux-3.2.1/arch/arm/plat-ckb/sram.h
+ *** linux-3.2.1_o/arch/arm/plat-ckb/sram.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/sram.h	2014-11-25 13:19:15.311791393 +0900
+ ***************
+ *** 0 ****
+ --- 1,6 ----
+ + #ifndef __PLAT_OMAP_SRAM_H__
+ + #define __PLAT_OMAP_SRAM_H__
+ + 
+ + extern int __init omap_sram_init(void);
+ + 
+ + #endif /* __PLAT_OMAP_SRAM_H__ */
+ diff -crN linux-3.2.1_o/arch/arm/plat-ckb/usb.c linux-3.2.1/arch/arm/plat-ckb/usb.c
+ *** linux-3.2.1_o/arch/arm/plat-ckb/usb.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/arch/arm/plat-ckb/usb.c	2014-11-25 13:19:15.311791393 +0900
+ ***************
+ *** 0 ****
+ --- 1,128 ----
+ +  /*
+ +  * arch/arm/plat-omap/usb.c -- platform level USB initialization
+ +  *
+ +  * Copyright (C) 2004 Texas Instruments, Inc.
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; either version 2 of the License, or
+ +  * (at your option) any later version.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ +  */
+ + 
+ + #undef	DEBUG
+ + 
+ + #include <linux/module.h>
+ + #include <linux/kernel.h>
+ + #include <linux/init.h>
+ + #include <linux/platform_device.h>
+ + #include <linux/io.h>
+ + 
+ + #include <plat/usb.h>
+ + #include <plat/board.h>
+ + 
+ + #ifdef	CONFIG_ARCH_OMAP_OTG
+ + 
+ + void __init
+ + omap_otg_init(struct omap_usb_config *config)
+ + {
+ + 	u32		syscon;
+ + 	int		status;
+ + 	int		alt_pingroup = 0;
+ + 
+ + 	/* NOTE:  no bus or clock setup (yet?) */
+ + 
+ + 	syscon = omap_readl(OTG_SYSCON_1) & 0xffff;
+ + 	if (!(syscon & OTG_RESET_DONE))
+ + 		pr_debug("USB resets not complete?\n");
+ + 
+ + 	//omap_writew(0, OTG_IRQ_EN);
+ + 
+ + 	/* pin muxing and transceiver pinouts */
+ + 	if (config->pins[0] > 2)	/* alt pingroup 2 */
+ + 		alt_pingroup = 1;
+ + 	syscon |= config->usb0_init(config->pins[0], is_usb0_device(config));
+ + 	syscon |= config->usb1_init(config->pins[1]);
+ + 	syscon |= config->usb2_init(config->pins[2], alt_pingroup);
+ + 	pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
+ + 	omap_writel(syscon, OTG_SYSCON_1);
+ + 
+ + 	syscon = config->hmc_mode;
+ + 	syscon |= USBX_SYNCHRO | (4 << 16) /* B_ASE0_BRST */;
+ + #ifdef	CONFIG_USB_OTG
+ + 	if (config->otg)
+ + 		syscon |= OTG_EN;
+ + #endif
+ + 	
+ + 	pr_debug("OTG_SYSCON_2 = %08x\n", omap_readl(OTG_SYSCON_2));
+ + 	omap_writel(syscon, OTG_SYSCON_2);
+ + 
+ + 	printk("USB: hmc %d", config->hmc_mode);
+ + 	if (!alt_pingroup)
+ + 		printk(", usb2 alt %d wires", config->pins[2]);
+ + 	else if (config->pins[0])
+ + 		printk(", usb0 %d wires%s", config->pins[0],
+ + 			is_usb0_device(config) ? " (dev)" : "");
+ + 	if (config->pins[1])
+ + 		printk(", usb1 %d wires", config->pins[1]);
+ + 	if (!alt_pingroup && config->pins[2])
+ + 		printk(", usb2 %d wires", config->pins[2]);
+ + 	if (config->otg)
+ + 		printk(", Mini-AB on usb%d", config->otg - 1);
+ + 	printk("\n");
+ + 
+ + 	syscon = omap_readl(OTG_SYSCON_1);
+ + 	syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN;
+ + 
+ + #ifdef	CONFIG_USB_GADGET_OMAP
+ + 	if (config->otg || config->register_dev) {
+ + 		struct platform_device *udc_device = config->udc_device;
+ + 
+ + 		syscon &= ~DEV_IDLE_EN;
+ + 		udc_device->dev.platform_data = config;
+ + 		status = platform_device_register(udc_device);
+ + 		if (status)
+ + 			pr_debug("can't register UDC device, %d\n", status);
+ + 	}
+ + #endif
+ + 
+ + #if	defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+ + 	if (config->otg || config->register_host) {
+ + 		struct platform_device *ohci_device = config->ohci_device;
+ + 
+ + 		syscon &= ~HST_IDLE_EN;
+ + 		ohci_device->dev.platform_data = config;
+ + 		status = platform_device_register(ohci_device);
+ + 		if (status)
+ + 			pr_debug("can't register OHCI device, %d\n", status);
+ + 	}
+ + #endif
+ + 
+ + #ifdef	CONFIG_USB_OTG
+ + 	if (config->otg) {
+ + 		struct platform_device *otg_device = config->otg_device;
+ + 
+ + 		syscon &= ~OTG_IDLE_EN;
+ + 		otg_device->dev.platform_data = config;
+ + 		status = platform_device_register(otg_device);
+ + 		if (status)
+ + 			pr_debug("can't register OTG device, %d\n", status);
+ + 	}
+ + #endif
+ + 	pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
+ + 	omap_writel(syscon, OTG_SYSCON_1);
+ + 
+ + 	status = 0;
+ + }
+ + 
+ + #else
+ + void omap_otg_init(struct omap_usb_config *config) {}
+ + #endif
+ diff -crN linux-3.2.1_o/arch/arm/tools/mach-types linux-3.2.1/arch/arm/tools/mach-types
+ *** linux-3.2.1_o/arch/arm/tools/mach-types	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/arch/arm/tools/mach-types	2014-11-25 13:19:15.332014973 +0900
+ ***************
+ *** 1126,1128 ****
+ --- 1126,1129 ----
+   m28evk			MACH_M28EVK		M28EVK			3613
+   smdk4212		MACH_SMDK4212		SMDK4212		3638
+   smdk4412		MACH_SMDK4412		SMDK4412		3765
+ + ckb_3352		MACH_CKB_3352		CKB_3352		4744
+ diff -crN linux-3.2.1_o/drivers/char/hw_random/Kconfig linux-3.2.1/drivers/char/hw_random/Kconfig
+ *** linux-3.2.1_o/drivers/char/hw_random/Kconfig	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/char/hw_random/Kconfig	2014-11-25 13:19:15.340065939 +0900
+ ***************
+ *** 139,144 ****
+ --- 139,157 ----
+   
+    	  If unsure, say Y.
+   
+ + config HW_RANDOM_OMAP4
+ + 	tristate "OMAP4 Random Number Generator support"
+ + 	depends on HW_RANDOM && SOC_OMAPAM33XX
+ + 	default HW_RANDOM
+ + 	---help---
+ + 	  This driver provides kernel-side support for the Random Number
+ + 	  Generator hardware found on OMAP4 derived processors.
+ + 
+ + 	  To compile this driver as a module, choose M here: the
+ + 	  module will be called omap4-rng.
+ + 
+ + 	  If unsure, say Y.
+ + 
+   config HW_RANDOM_OCTEON
+   	tristate "Octeon Random Number Generator support"
+   	depends on HW_RANDOM && CPU_CAVIUM_OCTEON
+ diff -crN linux-3.2.1_o/drivers/char/hw_random/Makefile linux-3.2.1/drivers/char/hw_random/Makefile
+ *** linux-3.2.1_o/drivers/char/hw_random/Makefile	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/char/hw_random/Makefile	2014-11-25 13:19:15.340065939 +0900
+ ***************
+ *** 14,19 ****
+ --- 14,20 ----
+   obj-$(CONFIG_HW_RANDOM_VIA) += via-rng.o
+   obj-$(CONFIG_HW_RANDOM_IXP4XX) += ixp4xx-rng.o
+   obj-$(CONFIG_HW_RANDOM_OMAP) += omap-rng.o
+ + obj-$(CONFIG_HW_RANDOM_OMAP4) += omap4-rng.o
+   obj-$(CONFIG_HW_RANDOM_PASEMI) += pasemi-rng.o
+   obj-$(CONFIG_HW_RANDOM_VIRTIO) += virtio-rng.o
+   obj-$(CONFIG_HW_RANDOM_TX4939) += tx4939-rng.o
+ diff -crN linux-3.2.1_o/drivers/char/hw_random/omap4-rng.c linux-3.2.1/drivers/char/hw_random/omap4-rng.c
+ *** linux-3.2.1_o/drivers/char/hw_random/omap4-rng.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/drivers/char/hw_random/omap4-rng.c	2014-11-25 13:19:15.344005491 +0900
+ ***************
+ *** 0 ****
+ --- 1,301 ----
+ + /*
+ +  * drivers/char/hw_random/omap4-rng.c
+ +  *
+ +  * Copyright (c) 2012 Texas Instruments
+ +  * TRNG driver for OMAP4 derivatives (AM33x, etc) -  Herman Schuurman <herman@ti.com>
+ +  *
+ +  * derived from omap-rng.c.
+ +  *
+ +  * Author: Deepak Saxena <dsaxena@plexity.net>
+ +  *
+ +  * Copyright 2005 (c) MontaVista Software, Inc.
+ +  *
+ +  * Mostly based on original driver:
+ +  *
+ +  * Copyright (C) 2005 Nokia Corporation
+ +  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
+ +  *
+ +  * This file is licensed under  the terms of the GNU General Public
+ +  * License version 2. This program is licensed "as is" without any
+ +  * warranty of any kind, whether express or implied.
+ +  */
+ + 
+ + #include <linux/module.h>
+ + #include <linux/init.h>
+ + #include <linux/random.h>
+ + #include <linux/pm_runtime.h>
+ + #include <linux/err.h>
+ + #include <linux/platform_device.h>
+ + #include <linux/hw_random.h>
+ + #include <linux/delay.h>
+ + 
+ + #include <mach/hardware.h>
+ + #include <asm/io.h>
+ + 
+ + /* ==================================================================== */
+ + /** RNG module layout.
+ +  */
+ + /* ==================================================================== */
+ + #define	RNG_REG_OUTPUT_L		0x00
+ + #define	RNG_REG_OUTPUT_H		0x04
+ + 
+ + #define	RNG_REG_STATUS			0x08
+ + #define	RNG_REG_STATUS_NEED_CLK		(1 << 31)
+ + #define	RNG_REG_STATUS_SHUTDOWN_OFLO	(1 << 1)
+ + #define	RNG_REG_STATUS_RDY		(1 << 0)
+ + 
+ + #define	RNG_REG_IMASK			0x0C
+ + #define	RNG_REG_IMASK_SHUTDOWN_OFLO	(1 << 1)
+ + #define	RNG_REG_IMASK_RDY		(1 << 0)
+ + 
+ + #define	RNG_REG_INTACK			0x10
+ + #define	RNG_REG_INTACK_SHUTDOWN_OFLO	(1 << 1)
+ + #define	RNG_REG_INTACK_RDY		(1 << 0)
+ + 
+ + #define	RNG_REG_CONTROL			0x14
+ + #define	RNG_REG_CONTROL_STARTUP_MASK	0xFFFF0000
+ + #define	RNG_REG_CONTROL_ENABLE_TRNG	(1 << 10)
+ + #define	RNG_REG_CONTROL_NO_LFSR_FB	(1 << 2)
+ + 
+ + #define	RNG_REG_CONFIG			0x18
+ + #define	RNG_REG_CONFIG_MAX_REFILL_MASK	0xFFFF0000
+ + #define	RNG_REG_CONFIG_SAMPLE_DIV	0x00000F00
+ + #define	RNG_REG_CONFIG_MIN_REFILL_MASK	0x000000FF
+ + 
+ + #define	RNG_REG_ALARMCNT		0x1C
+ + #define	RNG_REG_ALARMCNT_SHTDWN_MASK	0x3F000000
+ + #define	RNG_REG_ALARMCNT_SD_THLD_MASK	0x001F0000
+ + #define	RNG_REG_ALARMCNT_ALM_THLD_MASK	0x000000FF
+ + 
+ + #define	RNG_REG_FROENABLE		0x20
+ + #define	RNG_REG_FRODETUNE		0x24
+ + #define	RNG_REG_ALARMMASK		0x28
+ + #define	RNG_REG_ALARMSTOP		0x2C
+ + #define	RNG_REG_LFSR_L			0x30
+ + #define	RNG_REG_LFSR_M			0x34
+ + #define	RNG_REG_LFSR_H			0x38
+ + #define	RNG_REG_COUNT			0x3C
+ + #define	RNG_REG_TEST			0x40
+ + 
+ + #define	RNG_REG_OPTIONS			0x78
+ + #define	RNG_REG_OPTIONS_NUM_FROS_MASK	0x00000FC0
+ + 
+ + #define	RNG_REG_EIP_REV			0x7C
+ + #define	RNG_REG_STATUS_EN		0x1FD8
+ + #define	RNG_REG_STATUS_EN_SHUTDOWN_OFLO	(1 << 1)
+ + #define	RNG_REG_STATUS_EN_RDY		(1 << 0)
+ + 
+ + #define	RNG_REG_REV			0x1FE0
+ + #define	 RNG_REG_REV_X_MAJOR_MASK	(0x0F << 4)
+ + #define	 RNG_REG_REV_Y_MINOR_MASK	(0x0F << 0)
+ + 
+ + #define	RNG_REG_SYSCFG			0x1FE4
+ + #define	RNG_REG_SYSCFG_SIDLEMODE_MASK	(3 << 3)
+ + #define	 RNG_REG_SYSCFG_SIDLEMODE_FORCE	(0 << 3)
+ + #define	 RNG_REG_SYSCFG_SIDLEMODE_NO	(1 << 3)
+ + #define	 RNG_REG_SYSCFG_SIDLEMODE_SMART	(2 << 3)
+ + #define	RNG_REG_SYSCFG_AUTOIDLE		(1 << 0)
+ + 
+ + #define	RNG_REG_STATUS_SET		0x1FEC
+ + #define	RNG_REG_STATUS_SET_SHUTDOWN_OFLO (1 << 1)
+ + #define	RNG_REG_STATUS_SET_RDY		(1 << 0)
+ + 
+ + #define	RNG_REG_SOFT_RESET		0x1FF0
+ + #define	RNG_REG_SOFTRESET		(1 << 0)
+ + 
+ + #define	RNG_REG_IRQ_EOI			0x1FF4
+ + #define	RNG_REG_IRQ_EOI_PULSE_INT_CLEAR	(1 << 0)
+ + 
+ + #define	RNG_REG_IRQSTATUS		0x1FF8
+ + #define	RNG_REG_IRQSTATUS_IRQ_EN	(1 << 0)
+ + 
+ + 
+ + static void __iomem *rng_base;
+ + static struct platform_device *rng_dev;
+ + 
+ + #define trng_read(reg)						\
+ + ({								\
+ + 	u32 __val;						\
+ + 	__val = __raw_readl(rng_base + RNG_REG_##reg);		\
+ + })
+ + 
+ + #define trng_write(val, reg)					\
+ + ({								\
+ + 	__raw_writel((val), rng_base + RNG_REG_##reg);		\
+ + })
+ + 
+ + static int omap4_rng_data_read(struct hwrng *rng, void *buf, size_t max, bool wait)
+ + {
+ + 	int res, i;
+ + 
+ + 	for (i = 0; i < 20; i++) {
+ + 		res = trng_read(STATUS) & RNG_REG_STATUS_RDY;
+ + 		if (res || !wait)
+ + 			break;
+ + 		/* RNG produces data fast enough (2+ MBit/sec, even
+ + 		 * during "rngtest" loads, that these delays don't
+ + 		 * seem to trigger.  We *could* use the RNG IRQ, but
+ + 		 * that'd be higher overhead ... so why bother?
+ + 		 */
+ + 		udelay(10);
+ + 	}
+ + 
+ + 	/* If we have data waiting, collect it... */
+ + 	if (res) {
+ + 		*(u32 *)buf = trng_read(OUTPUT_L);
+ + 		buf += sizeof(u32);
+ + 		*(u32 *)buf = trng_read(OUTPUT_H);
+ + 
+ + 		trng_write(RNG_REG_INTACK_RDY, INTACK);
+ + 
+ + 		res = 2  * sizeof(u32);
+ + 	}
+ + 	return res;
+ + }
+ + 
+ + static struct hwrng omap4_rng_ops = {
+ + 	.name		= "omap4",
+ + 	.read		= omap4_rng_data_read,
+ + };
+ + 
+ + static int __devinit omap4_rng_probe(struct platform_device *pdev)
+ + {
+ + 	struct resource *res;
+ + 	int ret;
+ + 	u32 reg;
+ + 
+ + 	/*
+ + 	 * A bit ugly, and it will never actually happen but there can
+ + 	 * be only one RNG and this catches any bork
+ + 	 */
+ + 	if (rng_dev)
+ + 		return -EBUSY;
+ + 
+ + 	pm_runtime_enable(&pdev->dev);
+ + 	pm_runtime_get_sync(&pdev->dev);
+ + 
+ + 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ + 	if (!res) {
+ + 		ret = -ENOENT;
+ + 		goto err_region;
+ + 	}
+ + 
+ + 	if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
+ + 		ret = -EBUSY;
+ + 		goto err_region;
+ + 	}
+ + 
+ + 	dev_set_drvdata(&pdev->dev, res);
+ + 	rng_base = ioremap(res->start, resource_size(res));
+ + 	if (!rng_base) {
+ + 		ret = -ENOMEM;
+ + 		goto err_ioremap;
+ + 	}
+ + 
+ + 	ret = hwrng_register(&omap4_rng_ops);
+ + 	if (ret)
+ + 		goto err_register;
+ + 
+ + 	reg = trng_read(REV);
+ + 	dev_info(&pdev->dev, "OMAP4 Random Number Generator ver. %u.%02u\n",
+ + 		 ((reg & RNG_REG_REV_X_MAJOR_MASK) >> 4),
+ + 		 (reg & RNG_REG_REV_Y_MINOR_MASK));
+ + 
+ + 	rng_dev = pdev;
+ + 
+ + 	/* start TRNG if not running yet */
+ + 	if (!(trng_read(CONTROL) & RNG_REG_CONTROL_ENABLE_TRNG)) {
+ + 		trng_write(0x00220021, CONFIG);
+ + 		trng_write(0x00210400, CONTROL);
+ + 	}
+ + 
+ + 	return 0;
+ + 
+ + err_register:
+ + 	iounmap(rng_base);
+ + 	rng_base = NULL;
+ + err_ioremap:
+ + 	release_mem_region(res->start, resource_size(res));
+ + err_region:
+ + 	pm_runtime_put_sync(&pdev->dev);
+ + 	pm_runtime_disable(&pdev->dev);
+ + 	return ret;
+ + }
+ + 
+ + static int __exit omap4_rng_remove(struct platform_device *pdev)
+ + {
+ + 	struct resource *res = dev_get_drvdata(&pdev->dev);
+ + 
+ + 	hwrng_unregister(&omap4_rng_ops);
+ + 
+ + 	trng_write(trng_read(CONTROL) & ~RNG_REG_CONTROL_ENABLE_TRNG, CONTROL);
+ + 
+ + 	iounmap(rng_base);
+ + 
+ + 	pm_runtime_put_sync(&pdev->dev);
+ + 	pm_runtime_disable(&pdev->dev);
+ + 	release_mem_region(res->start, resource_size(res));
+ + 	rng_base = NULL;
+ + 
+ + 	return 0;
+ + }
+ + 
+ + #ifdef CONFIG_PM
+ + 
+ + static int omap4_rng_suspend(struct platform_device *pdev, pm_message_t message)
+ + {
+ + 	trng_write(trng_read(CONTROL) & ~RNG_REG_CONTROL_ENABLE_TRNG, CONTROL);
+ + 
+ + 	pm_runtime_put_sync(&pdev->dev);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static int omap4_rng_resume(struct platform_device *pdev)
+ + {
+ + 	pm_runtime_get_sync(&pdev->dev);
+ + 
+ + 	trng_write(trng_read(CONTROL) | RNG_REG_CONTROL_ENABLE_TRNG, CONTROL);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + #else
+ + 
+ + #define	omap4_rng_suspend	NULL
+ + #define	omap4_rng_resume	NULL
+ + 
+ + #endif
+ + 
+ + /* work with hotplug and coldplug */
+ + MODULE_ALIAS("platform:omap4_rng");
+ + 
+ + static struct platform_driver omap4_rng_driver = {
+ + 	.driver = {
+ + 		.name		= "omap4_rng",
+ + 		.owner		= THIS_MODULE,
+ + 	},
+ + 	.probe		= omap4_rng_probe,
+ + 	.remove		= __exit_p(omap4_rng_remove),
+ + 	.suspend	= omap4_rng_suspend,
+ + 	.resume		= omap4_rng_resume
+ + };
+ + 
+ + static int __init omap4_rng_init(void)
+ + {
+ + 	if (!cpu_is_am33xx()  || omap_type() != OMAP2_DEVICE_TYPE_GP)
+ + 		return -ENODEV;
+ + 
+ + 	return platform_driver_register(&omap4_rng_driver);
+ + }
+ + 
+ + static void __exit omap4_rng_exit(void)
+ + {
+ + 	platform_driver_unregister(&omap4_rng_driver);
+ + }
+ + 
+ + module_init(omap4_rng_init);
+ + module_exit(omap4_rng_exit);
+ + 
+ + MODULE_LICENSE("GPL");
+ + MODULE_DESCRIPTION("AM33X TRNG driver");
+ diff -crN linux-3.2.1_o/drivers/char/random.c linux-3.2.1/drivers/char/random.c
+ *** linux-3.2.1_o/drivers/char/random.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/char/random.c	2014-11-25 13:19:15.344005491 +0900
+ ***************
+ *** 130,135 ****
+ --- 130,138 ----
+    * 	void add_interrupt_randomness(int irq);
+    * 	void add_disk_randomness(struct gendisk *disk);
+    *
+ +  *      void random_input_words(__u32 *buf, size_t wordcount, int ent_count)
+ +  *      int random_input_wait(void);
+ +  *
+    * add_input_randomness() uses the input layer interrupt timing, as well as
+    * the event type information from the hardware.
+    *
+ ***************
+ *** 147,152 ****
+ --- 150,162 ----
+    * seek times do not make for good sources of entropy, as their seek
+    * times are usually fairly consistent.
+    *
+ +  * random_input_words() just provides a raw block of entropy to the input
+ +  * pool, such as from a hardware entropy generator.
+ +  *
+ +  * random_input_wait() suspends the caller until such time as the
+ +  * entropy pool falls below the write threshold, and returns a count of how
+ +  * much entropy (in bits) is needed to sustain the pool.
+ +  *
+    * All of these routines try to estimate how many bits of randomness a
+    * particular randomness source.  They do this by keeping track of the
+    * first and second order deltas of the event timings.
+ ***************
+ *** 722,727 ****
+ --- 732,794 ----
+   }
+   #endif
+   
+ + /*
+ +  * random_input_words - add bulk entropy to pool
+ +  *
+ +  * @buf: buffer to add
+ +  * @wordcount: number of __u32 words to add
+ +  * @ent_count: total amount of entropy (in bits) to credit
+ +  *
+ +  * this provides bulk input of entropy to the input pool
+ +  *
+ +  */
+ + void random_input_words(__u32 *buf, size_t wordcount, int ent_count)
+ + {
+ + 	mix_pool_bytes(&input_pool, buf, wordcount*4);
+ + 
+ + 	credit_entropy_bits(&input_pool, ent_count);
+ + 
+ + 	DEBUG_ENT("crediting %d bits => %d\n",
+ + 		  ent_count, input_pool.entropy_count);
+ + 	/*
+ + 	 * Wake up waiting processes if we have enough
+ + 	 * entropy.
+ + 	 */
+ + 	if (input_pool.entropy_count >= random_read_wakeup_thresh)
+ + 		wake_up_interruptible(&random_read_wait);
+ + }
+ + EXPORT_SYMBOL(random_input_words);
+ + 
+ + /*
+ +  * random_input_wait - wait until random needs entropy
+ +  *
+ +  * this function sleeps until the /dev/random subsystem actually
+ +  * needs more entropy, and then return the amount of entropy
+ +  * that it would be nice to have added to the system.
+ +  */
+ + int random_input_wait(void)
+ + {
+ + 	int count;
+ + 
+ + 	wait_event_interruptible(random_write_wait,
+ + 			 input_pool.entropy_count < random_write_wakeup_thresh);
+ + 
+ + 	count = random_write_wakeup_thresh - input_pool.entropy_count;
+ + 
+ +         /* likely we got woken up due to a signal */
+ + 	if (count <= 0) count = random_read_wakeup_thresh;
+ + 
+ + 	DEBUG_ENT("requesting %d bits from input_wait()er %d<%d\n",
+ + 		  count,
+ + 		  input_pool.entropy_count, random_write_wakeup_thresh);
+ + 
+ + 	return count;
+ + }
+ + EXPORT_SYMBOL(random_input_wait);
+ + 
+ + 
+ + #define EXTRACT_SIZE 10
+ + 
+   /*********************************************************************
+    *
+    * Entropy extraction routines
+ diff -crN linux-3.2.1_o/drivers/cpufreq/cpufreq.c linux-3.2.1/drivers/cpufreq/cpufreq.c
+ *** linux-3.2.1_o/drivers/cpufreq/cpufreq.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/cpufreq/cpufreq.c	2014-11-25 13:19:15.360019403 +0900
+ ***************
+ *** 204,211 ****
+   		pr_debug("saving %lu as reference value for loops_per_jiffy; "
+   			"freq is %u kHz\n", l_p_j_ref, l_p_j_ref_freq);
+   	}
+ ! 	if ((val == CPUFREQ_PRECHANGE  && ci->old < ci->new) ||
+ ! 	    (val == CPUFREQ_POSTCHANGE && ci->old > ci->new) ||
+   	    (val == CPUFREQ_RESUMECHANGE || val == CPUFREQ_SUSPENDCHANGE)) {
+   		loops_per_jiffy = cpufreq_scale(l_p_j_ref, l_p_j_ref_freq,
+   								ci->new);
+ --- 204,210 ----
+   		pr_debug("saving %lu as reference value for loops_per_jiffy; "
+   			"freq is %u kHz\n", l_p_j_ref, l_p_j_ref_freq);
+   	}
+ ! 	if ((val == CPUFREQ_POSTCHANGE  && ci->old != ci->new) ||
+   	    (val == CPUFREQ_RESUMECHANGE || val == CPUFREQ_SUSPENDCHANGE)) {
+   		loops_per_jiffy = cpufreq_scale(l_p_j_ref, l_p_j_ref_freq,
+   								ci->new);
+ diff -crN linux-3.2.1_o/drivers/cpufreq/cpufreq_userspace.c linux-3.2.1/drivers/cpufreq/cpufreq_userspace.c
+ *** linux-3.2.1_o/drivers/cpufreq/cpufreq_userspace.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/cpufreq/cpufreq_userspace.c	2014-11-25 13:19:15.376053972 +0900
+ ***************
+ *** 47,55 ****
+   	if (!per_cpu(cpu_is_managed, freq->cpu))
+   		return 0;
+   
+ ! 	pr_debug("saving cpu_cur_freq of cpu %u to be %u kHz\n",
+ ! 			freq->cpu, freq->new);
+ ! 	per_cpu(cpu_cur_freq, freq->cpu) = freq->new;
+   
+   	return 0;
+   }
+ --- 47,57 ----
+   	if (!per_cpu(cpu_is_managed, freq->cpu))
+   		return 0;
+   
+ ! 	if (val == CPUFREQ_POSTCHANGE) {
+ ! 		pr_debug("saving cpu_cur_freq of cpu %u to be %u kHz\n",
+ ! 				freq->cpu, freq->new);
+ ! 		per_cpu(cpu_cur_freq, freq->cpu) = freq->new;
+ ! 	}
+   
+   	return 0;
+   }
+ diff -crN linux-3.2.1_o/drivers/cpufreq/Makefile linux-3.2.1/drivers/cpufreq/Makefile
+ *** linux-3.2.1_o/drivers/cpufreq/Makefile	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/cpufreq/Makefile	2014-11-25 13:19:15.391111013 +0900
+ ***************
+ *** 44,49 ****
+ --- 44,51 ----
+   obj-$(CONFIG_ARM_S5PV210_CPUFREQ)	+= s5pv210-cpufreq.o
+   obj-$(CONFIG_ARM_EXYNOS4210_CPUFREQ)	+= exynos4210-cpufreq.o
+   
+ + obj-$(CONFIG_ARCH_CKB)            += omap-cpufreq.o
+ + 
+   ##################################################################################
+   # PowerPC platform drivers
+   obj-$(CONFIG_CPU_FREQ_MAPLE)		+= maple-cpufreq.o
+ diff -crN linux-3.2.1_o/drivers/cpufreq/omap-cpufreq.c linux-3.2.1/drivers/cpufreq/omap-cpufreq.c
+ *** linux-3.2.1_o/drivers/cpufreq/omap-cpufreq.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/drivers/cpufreq/omap-cpufreq.c	2014-11-25 13:19:15.400007166 +0900
+ ***************
+ *** 0 ****
+ --- 1,412 ----
+ + /*
+ +  *  CPU frequency scaling for OMAP using OPP information
+ +  *
+ +  *  Copyright (C) 2005 Nokia Corporation
+ +  *  Written by Tony Lindgren <tony@atomide.com>
+ +  *
+ +  *  Based on cpu-sa1110.c, Copyright (C) 2001 Russell King
+ +  *
+ +  * Copyright (C) 2007-2011 Texas Instruments, Inc.
+ +  * - OMAP3/4 support by Rajendra Nayak, Santosh Shilimkar
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  */
+ + #include <linux/types.h>
+ + #include <linux/kernel.h>
+ + #include <linux/sched.h>
+ + #include <linux/cpufreq.h>
+ + #include <linux/delay.h>
+ + #include <linux/init.h>
+ + #include <linux/err.h>
+ + #include <linux/clk.h>
+ + #include <linux/io.h>
+ + #include <linux/opp.h>
+ + #include <linux/cpu.h>
+ + #include <linux/module.h>
+ + #include <linux/regulator/consumer.h>
+ + #include <linux/suspend.h>
+ + 
+ + #include <asm/system.h>
+ + #include <asm/smp_plat.h>
+ + #include <asm/cpu.h>
+ + 
+ + #include <plat/clock.h>
+ + #include <plat/omap-pm.h>
+ + #include <plat/common.h>
+ + #include <plat/omap_device.h>
+ + 
+ + #include <mach/hardware.h>
+ + 
+ + /* Tolerance for MPU voltage is 4%, we have to pass +4% as a
+ +  * maximum voltage while setting the MPU regulator voltage.
+ +  * Which is taken from AM33XX datasheet */
+ + #define MPU_TOLERANCE	4
+ + #define PER_ROUND_VAL	100
+ + 
+ + /* Use 275MHz when entering suspend */
+ + #define SLEEP_FREQ	(275 * 1000)
+ + 
+ + 
+ + #ifdef CONFIG_SMP
+ + struct lpj_info {
+ + 	unsigned long	ref;
+ + 	unsigned int	freq;
+ + };
+ + 
+ + static DEFINE_PER_CPU(struct lpj_info, lpj_ref);
+ + static struct lpj_info global_lpj_ref;
+ + #endif
+ + 
+ + static struct cpufreq_frequency_table *freq_table;
+ + static atomic_t freq_table_users = ATOMIC_INIT(0);
+ + static struct clk *mpu_clk;
+ + static char *mpu_clk_name;
+ + static struct device *mpu_dev;
+ + static struct regulator *mpu_reg;
+ + static DEFINE_MUTEX(omap_cpu_lock);
+ + static bool is_suspended;
+ + 
+ + static int omap_verify_speed(struct cpufreq_policy *policy)
+ + {
+ + 	if (!freq_table)
+ + 		return -EINVAL;
+ + 	return cpufreq_frequency_table_verify(policy, freq_table);
+ + }
+ + 
+ + static unsigned int omap_getspeed(unsigned int cpu)
+ + {
+ + 	unsigned long rate;
+ + 
+ + 	if (cpu >= NR_CPUS)
+ + 		return 0;
+ + 
+ + 	rate = clk_get_rate(mpu_clk) / 1000;
+ + 	return rate;
+ + }
+ + 
+ + static int omap_target(struct cpufreq_policy *policy,
+ + 		       unsigned int target_freq,
+ + 		       unsigned int relation)
+ + {
+ + 	unsigned int i;
+ + 	int ret = 0;
+ + 	struct cpufreq_freqs freqs;
+ + 	struct opp *opp;
+ + 	int volt_old = 0, volt_new = 0;
+ + 
+ + 	if (is_suspended)
+ + 		return -EBUSY;
+ + 
+ + 	if (!freq_table) {
+ + 		dev_err(mpu_dev, "%s: cpu%d: no freq table!\n", __func__,
+ + 				policy->cpu);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	ret = cpufreq_frequency_table_target(policy, freq_table, target_freq,
+ + 			relation, &i);
+ + 	if (ret) {
+ + 		dev_dbg(mpu_dev, "%s: cpu%d: no freq match for %d(ret=%d)\n",
+ + 			__func__, policy->cpu, target_freq, ret);
+ + 		return ret;
+ + 	}
+ + 	freqs.new = freq_table[i].frequency;
+ + 	if (!freqs.new) {
+ + 		dev_err(mpu_dev, "%s: cpu%d: no match for freq %d\n", __func__,
+ + 			policy->cpu, target_freq);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	freqs.old = omap_getspeed(policy->cpu);
+ + 	freqs.cpu = policy->cpu;
+ + 
+ + 	if (freqs.old == freqs.new && policy->cur == freqs.new)
+ + 		return ret;
+ + 
+ + 	opp = opp_find_freq_exact(mpu_dev, freqs.new * 1000, true);
+ + 	if (IS_ERR(opp)) {
+ + 		dev_err(mpu_dev, "%s: cpu%d: no opp match for freq %d\n",
+ + 			__func__, policy->cpu, target_freq);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	volt_new = opp_get_voltage(opp);
+ + 	if (!volt_new) {
+ + 		dev_err(mpu_dev, "%s: cpu%d: no opp voltage for freq %d\n",
+ + 			__func__, policy->cpu, target_freq);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	volt_old = regulator_get_voltage(mpu_reg);
+ + 
+ + #ifdef CONFIG_CPU_FREQ_DEBUG
+ + 	pr_info("cpufreq-omap: frequency transition: %u --> %u\n",
+ + 			freqs.old, freqs.new);
+ + 	pr_info("cpufreq-omap: voltage transition: %d --> %d\n",
+ + 			volt_old, volt_new);
+ + #endif
+ + 
+ + 	if (freqs.new > freqs.old) {
+ + 		ret = regulator_set_voltage(mpu_reg, volt_new,
+ + 			volt_new + (volt_new * MPU_TOLERANCE) / PER_ROUND_VAL);
+ + 		if (ret) {
+ + 			dev_err(mpu_dev, "%s: unable to set voltage to %d uV (for %u MHz)\n",
+ + 				__func__, volt_new, freqs.new/1000);
+ + 			return ret;
+ + 		}
+ + 	}
+ + 
+ + 	/* notifiers */
+ + 	for_each_cpu(i, policy->cpus) {
+ + 		freqs.cpu = i;
+ + 		cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+ + 	}
+ + 
+ + 	ret = clk_set_rate(mpu_clk, freqs.new * 1000);
+ + 	freqs.new = omap_getspeed(policy->cpu);
+ + 
+ + #ifdef CONFIG_SMP
+ + 	/*
+ + 	 * Note that loops_per_jiffy is not updated on SMP systems in
+ + 	 * cpufreq driver. So, update the per-CPU loops_per_jiffy value
+ + 	 * on frequency transition. We need to update all dependent CPUs.
+ + 	 */
+ + 	for_each_cpu(i, policy->cpus) {
+ + 		struct lpj_info *lpj = &per_cpu(lpj_ref, i);
+ + 		if (!lpj->freq) {
+ + 			lpj->ref = per_cpu(cpu_data, i).loops_per_jiffy;
+ + 			lpj->freq = freqs.old;
+ + 		}
+ + 
+ + 		per_cpu(cpu_data, i).loops_per_jiffy =
+ + 			cpufreq_scale(lpj->ref, lpj->freq, freqs.new);
+ + 	}
+ + 
+ + 	/* And don't forget to adjust the global one */
+ + 	if (!global_lpj_ref.freq) {
+ + 		global_lpj_ref.ref = loops_per_jiffy;
+ + 		global_lpj_ref.freq = freqs.old;
+ + 	}
+ + 	loops_per_jiffy = cpufreq_scale(global_lpj_ref.ref, global_lpj_ref.freq,
+ + 					freqs.new);
+ + #endif
+ + 
+ + 	/* notifiers */
+ + 	for_each_cpu(i, policy->cpus) {
+ + 		freqs.cpu = i;
+ + 		cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+ + 	}
+ + 
+ + 	if (freqs.new < freqs.old) {
+ + 		ret = regulator_set_voltage(mpu_reg, volt_new,
+ + 			volt_new + (volt_new * MPU_TOLERANCE) / PER_ROUND_VAL);
+ + 		if (ret) {
+ + 			unsigned int temp;
+ + 
+ + 			dev_err(mpu_dev, "%s: unable to set voltage to %d uV (for %u MHz)\n",
+ + 				__func__, volt_new, freqs.new/1000);
+ + 
+ + 			if (clk_set_rate(mpu_clk, freqs.old * 1000)) {
+ + 				dev_err(mpu_dev,
+ + 					"%s: failed restoring clock rate to %u MHz, clock rate is %u MHz",
+ + 					__func__,
+ + 					freqs.old/1000, freqs.new/1000);
+ + 				return ret;
+ + 			}
+ + 
+ + 			temp = freqs.new;
+ + 			freqs.new = freqs.old;
+ + 			freqs.old = temp;
+ + 
+ + 			for_each_cpu(i, policy->cpus) {
+ + 				freqs.cpu = i;
+ + 				cpufreq_notify_transition(&freqs,
+ + 					CPUFREQ_PRECHANGE);
+ + 				cpufreq_notify_transition(&freqs,
+ + 					CPUFREQ_POSTCHANGE);
+ + 			}
+ + 			return ret;
+ + 		}
+ + 	}
+ + 
+ + 	return ret;
+ + }
+ + 
+ + static inline void freq_table_free(void)
+ + {
+ + 	if (atomic_dec_and_test(&freq_table_users))
+ + 		opp_free_cpufreq_table(mpu_dev, &freq_table);
+ + }
+ + 
+ + static int omap_pm_notify(struct notifier_block *nb, unsigned long event,
+ +                                 void *dummy)
+ + {
+ + 	struct cpufreq_policy *policy = cpufreq_cpu_get(0);
+ + 	static unsigned int saved_frequency;
+ + 
+ + 	mutex_lock(&omap_cpu_lock);
+ + 	switch (event) {
+ + 	case PM_SUSPEND_PREPARE:
+ + 		if (is_suspended)
+ + 			goto out;
+ + 
+ +                 saved_frequency = omap_getspeed(0);
+ + 
+ +                 mutex_unlock(&omap_cpu_lock);
+ + 		omap_target(policy, SLEEP_FREQ, CPUFREQ_RELATION_H);
+ + 		mutex_lock(&omap_cpu_lock);
+ + 		is_suspended = true;
+ +                 break;
+ + 
+ +         case PM_POST_SUSPEND:
+ +                 is_suspended = false;
+ +                 mutex_unlock(&omap_cpu_lock);
+ + 		omap_target(policy, saved_frequency, CPUFREQ_RELATION_H);
+ + 		mutex_lock(&omap_cpu_lock);
+ +                 break;
+ + 	}
+ + out:
+ + 	mutex_unlock(&omap_cpu_lock);
+ + 
+ + 	return NOTIFY_OK;
+ + }
+ + 
+ + static struct notifier_block omap_cpu_pm_notifier = {
+ + 	.notifier_call = omap_pm_notify,
+ + };
+ + 
+ + static int __cpuinit omap_cpu_init(struct cpufreq_policy *policy)
+ + {
+ + 	int result = 0;
+ + 
+ + 	mpu_clk = clk_get(NULL, mpu_clk_name);
+ + 	if (IS_ERR(mpu_clk))
+ + 		return PTR_ERR(mpu_clk);
+ + 
+ + 	mpu_reg = regulator_get(NULL, "vdd_mpu");
+ + 	if (IS_ERR(mpu_reg)) {
+ + 		result = -EINVAL;
+ + 		goto fail_ck;
+ + 	}
+ + 
+ + 	/* success of regulator_get doesn't gurantee presence of driver for
+ + 	   physical regulator and presence of physical regulator (this
+ + 	   situation arises if dummy regulator is enabled),so check voltage
+ + 	   to verify that physical regulator and it's driver is present
+ + 	 */
+ + 	if (regulator_get_voltage(mpu_reg) < 0) {
+ + 		result = -EINVAL;
+ + 		goto fail_reg;
+ + 	}
+ + 
+ + 	if (policy->cpu >= NR_CPUS) {
+ + 		result = -EINVAL;
+ + 		goto fail_reg;
+ + 	}
+ + 
+ + 	policy->cur = policy->min = policy->max = omap_getspeed(policy->cpu);
+ + 
+ + 	if (atomic_inc_return(&freq_table_users) == 1)
+ + 		result = opp_init_cpufreq_table(mpu_dev, &freq_table);
+ + 
+ + 	if (result) {
+ + 		dev_err(mpu_dev, "%s: cpu%d: failed creating freq table[%d]\n",
+ + 				__func__, policy->cpu, result);
+ + 		goto fail_reg;
+ + 	}
+ + 
+ + 	result = cpufreq_frequency_table_cpuinfo(policy, freq_table);
+ + 	if (result)
+ + 		goto fail_table;
+ + 
+ + 	cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
+ + 
+ + 	policy->min = policy->cpuinfo.min_freq;
+ + 	policy->max = policy->cpuinfo.max_freq;
+ + 	policy->cur = omap_getspeed(policy->cpu);
+ + 
+ + 	/*
+ + 	 * On OMAP SMP configuartion, both processors share the voltage
+ + 	 * and clock. So both CPUs needs to be scaled together and hence
+ + 	 * needs software co-ordination. Use cpufreq affected_cpus
+ + 	 * interface to handle this scenario. Additional is_smp() check
+ + 	 * is to keep SMP_ON_UP build working.
+ + 	 */
+ + 	if (is_smp()) {
+ + 		policy->shared_type = CPUFREQ_SHARED_TYPE_ANY;
+ + 		cpumask_setall(policy->cpus);
+ + 	}
+ + 
+ + 	/* FIXME: what's the actual transition time? */
+ + 	policy->cpuinfo.transition_latency = 300 * 1000;
+ + 
+ + 	register_pm_notifier(&omap_cpu_pm_notifier);
+ + 
+ + 	return 0;
+ + 
+ + fail_table:
+ + 	freq_table_free();
+ + fail_reg:
+ + 	regulator_put(mpu_reg);
+ + fail_ck:
+ + 	clk_put(mpu_clk);
+ + 	return result;
+ + }
+ + 
+ + static int omap_cpu_exit(struct cpufreq_policy *policy)
+ + {
+ + 	freq_table_free();
+ + 	clk_put(mpu_clk);
+ + 	return 0;
+ + }
+ + 
+ + static struct freq_attr *omap_cpufreq_attr[] = {
+ + 	&cpufreq_freq_attr_scaling_available_freqs,
+ + 	NULL,
+ + };
+ + 
+ + static struct cpufreq_driver omap_driver = {
+ + 	.flags		= CPUFREQ_STICKY,
+ + 	.verify		= omap_verify_speed,
+ + 	.target		= omap_target,
+ + 	.get		= omap_getspeed,
+ + 	.init		= omap_cpu_init,
+ + 	.exit		= omap_cpu_exit,
+ + 	.name		= "omap",
+ + 	.attr		= omap_cpufreq_attr,
+ + };
+ + 
+ + static int __init omap_cpufreq_init(void)
+ + {
+ + 	if (cpu_is_omap24xx())
+ + 		mpu_clk_name = "virt_prcm_set";
+ + 	else if (cpu_is_omap34xx() && !cpu_is_am33xx())
+ + 		mpu_clk_name = "dpll1_ck";
+ + 	else if (cpu_is_omap44xx() || cpu_is_am33xx())
+ + 		mpu_clk_name = "dpll_mpu_ck";
+ + 
+ + 	if (!mpu_clk_name) {
+ + 		pr_err("%s: unsupported Silicon?\n", __func__);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	mpu_dev = omap_device_get_by_hwmod_name("mpu");
+ + 	if (!mpu_dev) {
+ + 		pr_warning("%s: unable to get the mpu device\n", __func__);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	return cpufreq_register_driver(&omap_driver);
+ + }
+ + 
+ + static void __exit omap_cpufreq_exit(void)
+ + {
+ + 	cpufreq_unregister_driver(&omap_driver);
+ + }
+ + 
+ + MODULE_DESCRIPTION("cpufreq driver for OMAP SoCs");
+ + MODULE_LICENSE("GPL");
+ + module_init(omap_cpufreq_init);
+ + module_exit(omap_cpufreq_exit);
+ diff -crN linux-3.2.1_o/drivers/gpio/gpio-omap.c linux-3.2.1/drivers/gpio/gpio-omap.c
+ *** linux-3.2.1_o/drivers/gpio/gpio-omap.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/gpio/gpio-omap.c	2014-11-25 13:19:15.433482337 +0900
+ ***************
+ *** 35,41 ****
+   	u16 virtual_irq_start;
+   	int method;
+   	u32 suspend_wakeup;
+ ! #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
+   	u32 saved_wakeup;
+   #endif
+   	u32 non_wakeup_gpios;
+ --- 35,41 ----
+   	u16 virtual_irq_start;
+   	int method;
+   	u32 suspend_wakeup;
+ ! #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_ARCH_CKB)
+   	u32 saved_wakeup;
+   #endif
+   	u32 non_wakeup_gpios;
+ ***************
+ *** 61,67 ****
+   	struct omap_gpio_reg_offs *regs;
+   };
+   
+ ! #ifdef CONFIG_ARCH_OMAP3
+   struct omap3_gpio_regs {
+   	u32 irqenable1;
+   	u32 irqenable2;
+ --- 61,67 ----
+   	struct omap_gpio_reg_offs *regs;
+   };
+   
+ ! #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_CKB)
+   struct omap3_gpio_regs {
+   	u32 irqenable1;
+   	u32 irqenable2;
+ ***************
+ *** 206,219 ****
+   	__raw_writel(val, reg);
+   }
+   
+ ! #ifdef CONFIG_ARCH_OMAP2PLUS
+   static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
+   						int trigger)
+   {
+   	void __iomem *base = bank->base;
+   	u32 gpio_bit = 1 << gpio;
+   
+ ! 	if (cpu_is_omap44xx()) {
+   		_gpio_rmw(base, OMAP4_GPIO_LEVELDETECT0, gpio_bit,
+   			  trigger & IRQ_TYPE_LEVEL_LOW);
+   		_gpio_rmw(base, OMAP4_GPIO_LEVELDETECT1, gpio_bit,
+ --- 206,219 ----
+   	__raw_writel(val, reg);
+   }
+   
+ ! #if defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_ARCH_CKB)
+   static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
+   						int trigger)
+   {
+   	void __iomem *base = bank->base;
+   	u32 gpio_bit = 1 << gpio;
+   
+ ! 	if (cpu_is_omap44xx() || cpu_is_am33xx()) {
+   		_gpio_rmw(base, OMAP4_GPIO_LEVELDETECT0, gpio_bit,
+   			  trigger & IRQ_TYPE_LEVEL_LOW);
+   		_gpio_rmw(base, OMAP4_GPIO_LEVELDETECT1, gpio_bit,
+ ***************
+ *** 233,239 ****
+   			  trigger & IRQ_TYPE_EDGE_FALLING);
+   	}
+   	if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
+ ! 		if (cpu_is_omap44xx()) {
+   			_gpio_rmw(base, OMAP4_GPIO_IRQWAKEN0, gpio_bit,
+   				  trigger != 0);
+   		} else {
+ --- 233,239 ----
+   			  trigger & IRQ_TYPE_EDGE_FALLING);
+   	}
+   	if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
+ ! 		if (cpu_is_omap44xx() || cpu_is_am33xx()) {
+   			_gpio_rmw(base, OMAP4_GPIO_IRQWAKEN0, gpio_bit,
+   				  trigger != 0);
+   		} else {
+ ***************
+ *** 264,270 ****
+   			bank->enabled_non_wakeup_gpios &= ~gpio_bit;
+   	}
+   
+ ! 	if (cpu_is_omap44xx()) {
+   		bank->level_mask =
+   			__raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
+   			__raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
+ --- 264,270 ----
+   			bank->enabled_non_wakeup_gpios &= ~gpio_bit;
+   	}
+   
+ ! 	if (cpu_is_omap44xx() || cpu_is_am33xx()) {
+   		bank->level_mask =
+   			__raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
+   			__raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
+ ***************
+ *** 382,388 ****
+   			goto bad;
+   		break;
+   #endif
+ ! #ifdef CONFIG_ARCH_OMAP2PLUS
+   	case METHOD_GPIO_24XX:
+   	case METHOD_GPIO_44XX:
+   		set_24xx_gpio_triggering(bank, gpio, trigger);
+ --- 382,388 ----
+   			goto bad;
+   		break;
+   #endif
+ ! #if defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_ARCH_CKB)
+   	case METHOD_GPIO_24XX:
+   	case METHOD_GPIO_44XX:
+   		set_24xx_gpio_triggering(bank, gpio, trigger);
+ ***************
+ *** 588,597 ****
+   			void __iomem *reg = bank->base;
+   			u32 ctrl;
+   
+ ! 			if (cpu_is_omap24xx() || cpu_is_omap34xx())
+ ! 				reg += OMAP24XX_GPIO_CTRL;
+ ! 			else if (cpu_is_omap44xx())
+   				reg += OMAP4_GPIO_CTRL;
+   			ctrl = __raw_readl(reg);
+   			/* Module is enabled, clocks are not gated */
+   			ctrl &= 0xFFFFFFFE;
+ --- 588,597 ----
+   			void __iomem *reg = bank->base;
+   			u32 ctrl;
+   
+ ! 			if (cpu_is_omap44xx() || cpu_is_am33xx())
+   				reg += OMAP4_GPIO_CTRL;
+ + 			else if (cpu_is_omap24xx() || cpu_is_omap34xx())
+ + 				reg += OMAP24XX_GPIO_CTRL;
+   			ctrl = __raw_readl(reg);
+   			/* Module is enabled, clocks are not gated */
+   			ctrl &= 0xFFFFFFFE;
+ ***************
+ *** 617,630 ****
+   		__raw_writel(1 << offset, reg);
+   	}
+   #endif
+ ! #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+   	if (bank->method == METHOD_GPIO_24XX) {
+   		/* Disable wake-up during idle for dynamic tick */
+   		void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
+   		__raw_writel(1 << offset, reg);
+   	}
+   #endif
+ ! #ifdef CONFIG_ARCH_OMAP4
+   	if (bank->method == METHOD_GPIO_44XX) {
+   		/* Disable wake-up during idle for dynamic tick */
+   		void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
+ --- 617,630 ----
+   		__raw_writel(1 << offset, reg);
+   	}
+   #endif
+ ! #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_CKB)
+   	if (bank->method == METHOD_GPIO_24XX) {
+   		/* Disable wake-up during idle for dynamic tick */
+   		void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
+   		__raw_writel(1 << offset, reg);
+   	}
+   #endif
+ ! #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAPAM33XX) || defined(CONFIG_ARCH_CKB)
+   	if (bank->method == METHOD_GPIO_44XX) {
+   		/* Disable wake-up during idle for dynamic tick */
+   		void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
+ ***************
+ *** 637,646 ****
+   			void __iomem *reg = bank->base;
+   			u32 ctrl;
+   
+ ! 			if (cpu_is_omap24xx() || cpu_is_omap34xx())
+ ! 				reg += OMAP24XX_GPIO_CTRL;
+ ! 			else if (cpu_is_omap44xx())
+   				reg += OMAP4_GPIO_CTRL;
+   			ctrl = __raw_readl(reg);
+   			/* Module is disabled, clocks are gated */
+   			ctrl |= 1;
+ --- 637,646 ----
+   			void __iomem *reg = bank->base;
+   			u32 ctrl;
+   
+ ! 			if (cpu_is_omap44xx() || cpu_is_am33xx())
+   				reg += OMAP4_GPIO_CTRL;
+ + 			else if (cpu_is_omap24xx() || cpu_is_omap34xx())
+ + 				reg += OMAP24XX_GPIO_CTRL;
+   			ctrl = __raw_readl(reg);
+   			/* Module is disabled, clocks are gated */
+   			ctrl |= 1;
+ ***************
+ *** 1023,1029 ****
+   static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
+   {
+   	if (cpu_class_is_omap2()) {
+ ! 		if (cpu_is_omap44xx()) {
+   			__raw_writel(0xffffffff, bank->base +
+   					OMAP4_GPIO_IRQSTATUSCLR0);
+   			__raw_writel(0x00000000, bank->base +
+ --- 1023,1029 ----
+   static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
+   {
+   	if (cpu_class_is_omap2()) {
+ ! 		if (cpu_is_omap44xx() || cpu_is_am33xx()) {
+   			__raw_writel(0xffffffff, bank->base +
+   					OMAP4_GPIO_IRQSTATUSCLR0);
+   			__raw_writel(0x00000000, bank->base +
+ ***************
+ *** 1232,1238 ****
+   	return 0;
+   }
+   
+ ! #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
+   static int omap_gpio_suspend(void)
+   {
+   	int i;
+ --- 1232,1238 ----
+   	return 0;
+   }
+   
+ ! #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_ARCH_CKB)
+   static int omap_gpio_suspend(void)
+   {
+   	int i;
+ ***************
+ *** 1255,1268 ****
+   			wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
+   			break;
+   #endif
+ ! #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+   		case METHOD_GPIO_24XX:
+   			wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
+   			wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
+   			wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
+   			break;
+   #endif
+ ! #ifdef CONFIG_ARCH_OMAP4
+   		case METHOD_GPIO_44XX:
+   			wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
+   			wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
+ --- 1255,1268 ----
+   			wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
+   			break;
+   #endif
+ ! #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_CKB)
+   		case METHOD_GPIO_24XX:
+   			wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
+   			wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
+   			wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
+   			break;
+   #endif
+ ! #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAPAM33XX) || defined(CONFIG_ARCH_CKB)
+   		case METHOD_GPIO_44XX:
+   			wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
+   			wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
+ ***************
+ *** 1303,1315 ****
+   			wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
+   			break;
+   #endif
+ ! #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+   		case METHOD_GPIO_24XX:
+   			wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
+   			wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
+   			break;
+   #endif
+ ! #ifdef CONFIG_ARCH_OMAP4
+   		case METHOD_GPIO_44XX:
+   			wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
+   			wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
+ --- 1303,1315 ----
+   			wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
+   			break;
+   #endif
+ ! #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_CKB)
+   		case METHOD_GPIO_24XX:
+   			wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
+   			wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
+   			break;
+   #endif
+ ! #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAPAM33XX) || defined(CONFIG_ARCH_CKB)
+   		case METHOD_GPIO_44XX:
+   			wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
+   			wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
+ ***************
+ *** 1333,1339 ****
+   
+   #endif
+   
+ ! #ifdef CONFIG_ARCH_OMAP2PLUS
+   
+   static int workaround_enabled;
+   
+ --- 1333,1339 ----
+   
+   #endif
+   
+ ! #if defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_ARCH_CKB)
+   
+   static int workaround_enabled;
+   
+ ***************
+ *** 1342,1348 ****
+   	int i, c = 0;
+   	int min = 0;
+   
+ ! 	if (cpu_is_omap34xx())
+   		min = 1;
+   
+   	for (i = min; i < gpio_bank_count; i++) {
+ --- 1342,1348 ----
+   	int i, c = 0;
+   	int min = 0;
+   
+ ! 	if ((cpu_is_omap34xx() && !cpu_is_am33xx()))
+   		min = 1;
+   
+   	for (i = min; i < gpio_bank_count; i++) {
+ ***************
+ *** 1362,1368 ****
+   		if (!(bank->enabled_non_wakeup_gpios))
+   			continue;
+   
+ ! 		if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+   			bank->saved_datain = __raw_readl(bank->base +
+   					OMAP24XX_GPIO_DATAIN);
+   			l1 = __raw_readl(bank->base +
+ --- 1362,1369 ----
+   		if (!(bank->enabled_non_wakeup_gpios))
+   			continue;
+   
+ ! 		if (cpu_is_omap24xx() || (cpu_is_omap34xx() &&
+ ! 							!cpu_is_am33xx())) {
+   			bank->saved_datain = __raw_readl(bank->base +
+   					OMAP24XX_GPIO_DATAIN);
+   			l1 = __raw_readl(bank->base +
+ ***************
+ *** 1371,1377 ****
+   					OMAP24XX_GPIO_RISINGDETECT);
+   		}
+   
+ ! 		if (cpu_is_omap44xx()) {
+   			bank->saved_datain = __raw_readl(bank->base +
+   						OMAP4_GPIO_DATAIN);
+   			l1 = __raw_readl(bank->base +
+ --- 1372,1378 ----
+   					OMAP24XX_GPIO_RISINGDETECT);
+   		}
+   
+ ! 		if (cpu_is_omap44xx() || cpu_is_am33xx()) {
+   			bank->saved_datain = __raw_readl(bank->base +
+   						OMAP4_GPIO_DATAIN);
+   			l1 = __raw_readl(bank->base +
+ ***************
+ *** 1385,1398 ****
+   		l1 &= ~bank->enabled_non_wakeup_gpios;
+   		l2 &= ~bank->enabled_non_wakeup_gpios;
+   
+ ! 		if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+   			__raw_writel(l1, bank->base +
+   					OMAP24XX_GPIO_FALLINGDETECT);
+   			__raw_writel(l2, bank->base +
+   					OMAP24XX_GPIO_RISINGDETECT);
+   		}
+   
+ ! 		if (cpu_is_omap44xx()) {
+   			__raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
+   			__raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
+   		}
+ --- 1386,1400 ----
+   		l1 &= ~bank->enabled_non_wakeup_gpios;
+   		l2 &= ~bank->enabled_non_wakeup_gpios;
+   
+ ! 		if (cpu_is_omap24xx() || (cpu_is_omap34xx() &&
+ ! 							!cpu_is_am33xx())) {
+   			__raw_writel(l1, bank->base +
+   					OMAP24XX_GPIO_FALLINGDETECT);
+   			__raw_writel(l2, bank->base +
+   					OMAP24XX_GPIO_RISINGDETECT);
+   		}
+   
+ ! 		if (cpu_is_omap44xx() || cpu_is_am33xx()) {
+   			__raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
+   			__raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
+   		}
+ ***************
+ *** 1411,1417 ****
+   	int i;
+   	int min = 0;
+   
+ ! 	if (cpu_is_omap34xx())
+   		min = 1;
+   	for (i = min; i < gpio_bank_count; i++) {
+   		struct gpio_bank *bank = &gpio_bank[i];
+ --- 1413,1419 ----
+   	int i;
+   	int min = 0;
+   
+ ! 	if ((cpu_is_omap34xx() && !cpu_is_am33xx()))
+   		min = 1;
+   	for (i = min; i < gpio_bank_count; i++) {
+   		struct gpio_bank *bank = &gpio_bank[i];
+ ***************
+ *** 1427,1433 ****
+   		if (!(bank->enabled_non_wakeup_gpios))
+   			continue;
+   
+ ! 		if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+   			__raw_writel(bank->saved_fallingdetect,
+   				 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
+   			__raw_writel(bank->saved_risingdetect,
+ --- 1429,1436 ----
+   		if (!(bank->enabled_non_wakeup_gpios))
+   			continue;
+   
+ ! 		if (cpu_is_omap24xx() || (cpu_is_omap34xx() &&
+ ! 							!cpu_is_am33xx())) {
+   			__raw_writel(bank->saved_fallingdetect,
+   				 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
+   			__raw_writel(bank->saved_risingdetect,
+ ***************
+ *** 1435,1441 ****
+   			l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
+   		}
+   
+ ! 		if (cpu_is_omap44xx()) {
+   			__raw_writel(bank->saved_fallingdetect,
+   				 bank->base + OMAP4_GPIO_FALLINGDETECT);
+   			__raw_writel(bank->saved_risingdetect,
+ --- 1438,1444 ----
+   			l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
+   		}
+   
+ ! 		if (cpu_is_omap44xx() || cpu_is_am33xx()) {
+   			__raw_writel(bank->saved_fallingdetect,
+   				 bank->base + OMAP4_GPIO_FALLINGDETECT);
+   			__raw_writel(bank->saved_risingdetect,
+ ***************
+ *** 1469,1475 ****
+   		if (gen) {
+   			u32 old0, old1;
+   
+ ! 			if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+   				old0 = __raw_readl(bank->base +
+   					OMAP24XX_GPIO_LEVELDETECT0);
+   				old1 = __raw_readl(bank->base +
+ --- 1472,1479 ----
+   		if (gen) {
+   			u32 old0, old1;
+   
+ ! 			if (cpu_is_omap24xx() || (cpu_is_omap34xx() &&
+ ! 							!cpu_is_am33xx())) {
+   				old0 = __raw_readl(bank->base +
+   					OMAP24XX_GPIO_LEVELDETECT0);
+   				old1 = __raw_readl(bank->base +
+ ***************
+ *** 1484,1490 ****
+   					OMAP24XX_GPIO_LEVELDETECT1);
+   			}
+   
+ ! 			if (cpu_is_omap44xx()) {
+   				old0 = __raw_readl(bank->base +
+   						OMAP4_GPIO_LEVELDETECT0);
+   				old1 = __raw_readl(bank->base +
+ --- 1488,1494 ----
+   					OMAP24XX_GPIO_LEVELDETECT1);
+   			}
+   
+ ! 			if (cpu_is_omap44xx() || cpu_is_am33xx()) {
+   				old0 = __raw_readl(bank->base +
+   						OMAP4_GPIO_LEVELDETECT0);
+   				old1 = __raw_readl(bank->base +
+ ***************
+ *** 1505,1511 ****
+   
+   #endif
+   
+ ! #ifdef CONFIG_ARCH_OMAP3
+   /* save the registers of bank 2-6 */
+   void omap_gpio_save_context(void)
+   {
+ --- 1509,1515 ----
+   
+   #endif
+   
+ ! #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_CKB)
+   /* save the registers of bank 2-6 */
+   void omap_gpio_save_context(void)
+   {
+ ***************
+ *** 1590,1596 ****
+   {
+   	mpuio_init();
+   
+ ! #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
+   	if (cpu_is_omap16xx() || cpu_class_is_omap2())
+   		register_syscore_ops(&omap_gpio_syscore_ops);
+   #endif
+ --- 1594,1600 ----
+   {
+   	mpuio_init();
+   
+ ! #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_ARCH_CKB)
+   	if (cpu_is_omap16xx() || cpu_class_is_omap2())
+   		register_syscore_ops(&omap_gpio_syscore_ops);
+   #endif
+ diff -crN linux-3.2.1_o/drivers/gpio/Makefile linux-3.2.1/drivers/gpio/Makefile
+ *** linux-3.2.1_o/drivers/gpio/Makefile	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/gpio/Makefile	2014-11-25 13:19:15.443821936 +0900
+ ***************
+ *** 36,41 ****
+ --- 36,42 ----
+   obj-$(CONFIG_GPIO_MXS)		+= gpio-mxs.o
+   obj-$(CONFIG_PLAT_NOMADIK)	+= gpio-nomadik.o
+   obj-$(CONFIG_ARCH_OMAP)		+= gpio-omap.o
+ + obj-$(CONFIG_ARCH_CKB)		+= gpio-omap.o
+   obj-$(CONFIG_GPIO_PCA953X)	+= gpio-pca953x.o
+   obj-$(CONFIG_GPIO_PCF857X)	+= gpio-pcf857x.o
+   obj-$(CONFIG_GPIO_PCH)		+= gpio-pch.o
+ diff -crN linux-3.2.1_o/drivers/hv/vmbus_drv.c linux-3.2.1/drivers/hv/vmbus_drv.c
+ *** linux-3.2.1_o/drivers/hv/vmbus_drv.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/hv/vmbus_drv.c	2014-11-25 13:19:15.448040423 +0900
+ ***************
+ *** 62,75 ****
+   	struct hv_dev_port_info outbound;
+   };
+   
+ - static int vmbus_exists(void)
+ - {
+ - 	if (hv_acpi_dev == NULL)
+ - 		return -ENODEV;
+ - 
+ - 	return 0;
+ - }
+ - 
+   
+   static void get_channel_info(struct hv_device *device,
+   			     struct hv_device_info *info)
+ --- 62,67 ----
+ ***************
+ *** 598,607 ****
+   
+   	pr_info("registering driver %s\n", hv_driver->name);
+   
+ - 	ret = vmbus_exists();
+ - 	if (ret < 0)
+ - 		return ret;
+ - 
+   	hv_driver->driver.name = hv_driver->name;
+   	hv_driver->driver.owner = owner;
+   	hv_driver->driver.mod_name = mod_name;
+ --- 590,595 ----
+ ***************
+ *** 626,633 ****
+   {
+   	pr_info("unregistering driver %s\n", hv_driver->name);
+   
+ ! 	if (!vmbus_exists())
+ ! 		driver_unregister(&hv_driver->driver);
+   }
+   EXPORT_SYMBOL_GPL(vmbus_driver_unregister);
+   
+ --- 614,621 ----
+   {
+   	pr_info("unregistering driver %s\n", hv_driver->name);
+   
+ ! 	driver_unregister(&hv_driver->driver);
+ ! 
+   }
+   EXPORT_SYMBOL_GPL(vmbus_driver_unregister);
+   
+ ***************
+ *** 788,794 ****
+   
+   cleanup:
+   	acpi_bus_unregister_driver(&vmbus_acpi_driver);
+ - 	hv_acpi_dev = NULL;
+   	return ret;
+   }
+   
+ --- 776,781 ----
+ diff -crN linux-3.2.1_o/drivers/i2c/busses/i2c-omap.c linux-3.2.1/drivers/i2c/busses/i2c-omap.c
+ *** linux-3.2.1_o/drivers/i2c/busses/i2c-omap.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/i2c/busses/i2c-omap.c	2014-11-25 13:19:15.505023797 +0900
+ ***************
+ *** 235,241 ****
+   	[OMAP_I2C_BUF_REG] = 0x94,
+   	[OMAP_I2C_CNT_REG] = 0x98,
+   	[OMAP_I2C_DATA_REG] = 0x9c,
+ ! 	[OMAP_I2C_SYSC_REG] = 0x20,
+   	[OMAP_I2C_CON_REG] = 0xa4,
+   	[OMAP_I2C_OA_REG] = 0xa8,
+   	[OMAP_I2C_SA_REG] = 0xac,
+ --- 235,241 ----
+   	[OMAP_I2C_BUF_REG] = 0x94,
+   	[OMAP_I2C_CNT_REG] = 0x98,
+   	[OMAP_I2C_DATA_REG] = 0x9c,
+ ! 	[OMAP_I2C_SYSC_REG] = 0x10,
+   	[OMAP_I2C_CON_REG] = 0xa4,
+   	[OMAP_I2C_OA_REG] = 0xa8,
+   	[OMAP_I2C_SA_REG] = 0xac,
+ ***************
+ *** 498,503 ****
+ --- 498,504 ----
+    */
+   static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
+   {
+ + #if 1 //Change this to 1 while testing Suspend
+   	unsigned long timeout;
+   
+   	timeout = jiffies + OMAP_I2C_TIMEOUT;
+ ***************
+ *** 508,514 ****
+   		}
+   		msleep(1);
+   	}
+ ! 
+   	return 0;
+   }
+   
+ --- 509,517 ----
+   		}
+   		msleep(1);
+   	}
+ ! #else
+ ! 	msleep(5);
+ ! #endif
+   	return 0;
+   }
+   
+ ***************
+ *** 830,840 ****
+   				~(OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
+   				OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
+   
+ ! 		if (stat & OMAP_I2C_STAT_NACK) {
+   			err |= OMAP_I2C_STAT_NACK;
+ ! 			omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
+ ! 					   OMAP_I2C_CON_STP);
+ ! 		}
+   		if (stat & OMAP_I2C_STAT_AL) {
+   			dev_err(dev->dev, "Arbitration lost\n");
+   			err |= OMAP_I2C_STAT_AL;
+ --- 833,841 ----
+   				~(OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
+   				OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
+   
+ ! 		if (stat & OMAP_I2C_STAT_NACK)
+   			err |= OMAP_I2C_STAT_NACK;
+ ! 
+   		if (stat & OMAP_I2C_STAT_AL) {
+   			dev_err(dev->dev, "Arbitration lost\n");
+   			err |= OMAP_I2C_STAT_AL;
+ ***************
+ *** 1066,1072 ****
+   
+   	isr = (dev->rev < OMAP_I2C_OMAP1_REV_2) ? omap_i2c_omap1_isr :
+   								   omap_i2c_isr;
+ ! 	r = request_irq(dev->irq, isr, 0, pdev->name, dev);
+   
+   	if (r) {
+   		dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
+ --- 1067,1073 ----
+   
+   	isr = (dev->rev < OMAP_I2C_OMAP1_REV_2) ? omap_i2c_omap1_isr :
+   								   omap_i2c_isr;
+ ! 	r = request_irq(dev->irq, isr, IRQF_NO_SUSPEND, pdev->name, dev);
+   
+   	if (r) {
+   		dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
+ diff -crN linux-3.2.1_o/drivers/i2c/busses/Kconfig linux-3.2.1/drivers/i2c/busses/Kconfig
+ *** linux-3.2.1_o/drivers/i2c/busses/Kconfig	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/i2c/busses/Kconfig	2014-11-25 13:19:15.519062255 +0900
+ ***************
+ *** 501,507 ****
+   
+   config I2C_OMAP
+   	tristate "OMAP I2C adapter"
+ ! 	depends on ARCH_OMAP
+   	default y if MACH_OMAP_H3 || MACH_OMAP_OSK
+   	help
+   	  If you say yes to this option, support will be included for the
+ --- 501,507 ----
+   
+   config I2C_OMAP
+   	tristate "OMAP I2C adapter"
+ ! 	depends on ARCH_OMAP || ARCH_CKB
+   	default y if MACH_OMAP_H3 || MACH_OMAP_OSK
+   	help
+   	  If you say yes to this option, support will be included for the
+ diff -crN linux-3.2.1_o/drivers/Kconfig linux-3.2.1/drivers/Kconfig
+ *** linux-3.2.1_o/drivers/Kconfig	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/Kconfig	2014-11-25 13:19:15.531439309 +0900
+ ***************
+ *** 60,65 ****
+ --- 60,67 ----
+   
+   source "drivers/gpio/Kconfig"
+   
+ + source "drivers/pwm/Kconfig"
+ + 
+   source "drivers/w1/Kconfig"
+   
+   source "drivers/power/Kconfig"
+ diff -crN linux-3.2.1_o/drivers/Makefile linux-3.2.1/drivers/Makefile
+ *** linux-3.2.1_o/drivers/Makefile	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/Makefile	2014-11-25 15:43:23.804639000 +0900
+ ***************
+ *** 36,42 ****
+   
+   # gpu/ comes after char for AGP vs DRM startup
+   obj-y				+= gpu/
+ ! 
+   obj-$(CONFIG_CONNECTOR)		+= connector/
+   
+   # i810fb and intelfb depend on char/agp/
+ --- 36,42 ----
+   
+   # gpu/ comes after char for AGP vs DRM startup
+   obj-y				+= gpu/
+ ! obj-$(CONFIG_MACH_CKB_3352)		+= pwm/
+   obj-$(CONFIG_CONNECTOR)		+= connector/
+   
+   # i810fb and intelfb depend on char/agp/
+ diff -crN linux-3.2.1_o/drivers/media/video/uvc/uvc_driver.c linux-3.2.1/drivers/media/video/uvc/uvc_driver.c
+ *** linux-3.2.1_o/drivers/media/video/uvc/uvc_driver.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/media/video/uvc/uvc_driver.c	2014-11-25 13:19:15.603243624 +0900
+ ***************
+ *** 2374,2379 ****
+ --- 2374,2401 ----
+   	  .bInterfaceProtocol	= 0,
+   	  .driver_info		= UVC_QUIRK_PROBE_MINMAX
+   				| UVC_QUIRK_IGNORE_SELECTOR_UNIT },
+ + 	/* iBUFFALO */
+ + 	{ .match_flags		= USB_DEVICE_ID_MATCH_DEVICE
+ + 				| USB_DEVICE_ID_MATCH_INT_INFO,
+ + 	  .idVendor		= 0x1e4e,
+ + 	  .idProduct		= 0x0103,
+ + 	  .bInterfaceClass	= USB_CLASS_VIDEO,
+ + 	  .bInterfaceSubClass	= 1,
+ + 	  .bInterfaceProtocol	= 0,
+ + 	  .driver_info		= UVC_QUIRK_PROBE_DEF  
+ + 	  			| UVC_QUIRK_PROBE_MINMAX
+ + 				| UVC_QUIRK_PROBE_EXTRAFIELDS },
+ + 	/* F2M_USB */
+ + 	{ .match_flags		= USB_DEVICE_ID_MATCH_DEVICE
+ + 				| USB_DEVICE_ID_MATCH_INT_INFO,
+ + 	  .idVendor		= 0x1e4e,
+ + 	  .idProduct		= 0x0110,
+ + 	  .bInterfaceClass	= USB_CLASS_VIDEO,
+ + 	  .bInterfaceSubClass	= 1,
+ + 	  .bInterfaceProtocol	= 0,
+ + 	  .driver_info		= UVC_QUIRK_PROBE_DEF  
+ + 	  			 | UVC_QUIRK_PROBE_MINMAX
+ + 				| UVC_QUIRK_PROBE_EXTRAFIELDS },
+   	/* Generic USB Video Class */
+   	{ USB_INTERFACE_INFO(USB_CLASS_VIDEO, 1, 0) },
+   	{}
+ diff -crN linux-3.2.1_o/drivers/mfd/Kconfig linux-3.2.1/drivers/mfd/Kconfig
+ *** linux-3.2.1_o/drivers/mfd/Kconfig	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/mfd/Kconfig	2014-11-25 13:19:15.608034783 +0900
+ ***************
+ *** 142,147 ****
+ --- 142,170 ----
+   	  This driver can also be built as a module.  If so, the module
+   	  will be called tps6507x.
+   
+ + config MFD_TI_TSCADC
+ + 	tristate "TI ADC / Touch Screen chip support"
+ + 	help
+ + 	  If you say yes here you get support for Texas Instruments series
+ + 	  of Touch Screen /ADC chips.
+ + 	  To compile this driver as a module, choose M here: the
+ + 	  module will be called ti_tscadc.
+ + 
+ + config MFD_TPS65217
+ + 	tristate "TPS65217 Power Management / White LED chips"
+ + 	depends on I2C
+ + 	select MFD_CORE
+ + 	select REGMAP_I2C
+ + 	help
+ + 	  If you say yes here you get support for the TPS65217 series of
+ + 	  Power Management / White LED chips.
+ + 	  These include voltage regulators, lithium ion/polymer battery
+ + 	  charger, wled and other features that are often used in portable
+ + 	  devices.
+ + 
+ + 	  This driver can also be built as a module.  If so, the module
+ + 	  will be called tps65217.
+ + 
+   config MFD_TPS6586X
+   	bool "TPS6586x Power Management chips"
+   	depends on I2C=y && GPIOLIB && GENERIC_HARDIRQS
+ diff -crN linux-3.2.1_o/drivers/mfd/Makefile linux-3.2.1/drivers/mfd/Makefile
+ *** linux-3.2.1_o/drivers/mfd/Makefile	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/mfd/Makefile	2014-11-25 13:19:15.612038111 +0900
+ ***************
+ *** 36,41 ****
+ --- 36,42 ----
+   obj-$(CONFIG_TPS6105X)		+= tps6105x.o
+   obj-$(CONFIG_TPS65010)		+= tps65010.o
+   obj-$(CONFIG_TPS6507X)		+= tps6507x.o
+ + obj-$(CONFIG_MFD_TPS65217)	+= tps65217.o
+   obj-$(CONFIG_MFD_TPS65910)	+= tps65910.o tps65910-irq.o
+   tps65912-objs                   := tps65912-core.o tps65912-irq.o
+   obj-$(CONFIG_MFD_TPS65912)	+= tps65912.o
+ ***************
+ *** 104,106 ****
+ --- 105,108 ----
+   obj-$(CONFIG_TPS65911_COMPARATOR)	+= tps65911-comparator.o
+   obj-$(CONFIG_MFD_AAT2870_CORE)	+= aat2870-core.o
+   obj-$(CONFIG_MFD_INTEL_MSIC)	+= intel_msic.o
+ + obj-$(CONFIG_MFD_TI_TSCADC)	+= ti_tscadc.o
+ diff -crN linux-3.2.1_o/drivers/mfd/omap-usb-host.c linux-3.2.1/drivers/mfd/omap-usb-host.c
+ *** linux-3.2.1_o/drivers/mfd/omap-usb-host.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/mfd/omap-usb-host.c	2014-11-25 13:19:15.624016732 +0900
+ ***************
+ *** 27,34 ****
+   #include <linux/spinlock.h>
+   #include <linux/gpio.h>
+   #include <plat/usb.h>
+   
+ ! #define USBHS_DRIVER_NAME	"usbhs-omap"
+   #define OMAP_EHCI_DEVICE	"ehci-omap"
+   #define OMAP_OHCI_DEVICE	"ohci-omap3"
+   
+ --- 27,35 ----
+   #include <linux/spinlock.h>
+   #include <linux/gpio.h>
+   #include <plat/usb.h>
+ + #include <linux/pm_runtime.h>
+   
+ ! #define USBHS_DRIVER_NAME	"usbhs_omap"
+   #define OMAP_EHCI_DEVICE	"ehci-omap"
+   #define OMAP_OHCI_DEVICE	"ohci-omap3"
+   
+ ***************
+ *** 147,155 ****
+   
+   
+   struct usbhs_hcd_omap {
+ - 	struct clk			*usbhost_ick;
+ - 	struct clk			*usbhost_hs_fck;
+ - 	struct clk			*usbhost_fs_fck;
+   	struct clk			*xclk60mhsp1_ck;
+   	struct clk			*xclk60mhsp2_ck;
+   	struct clk			*utmi_p1_fck;
+ --- 148,153 ----
+ ***************
+ *** 159,166 ****
+   	struct clk			*usbhost_p2_fck;
+   	struct clk			*usbtll_p2_fck;
+   	struct clk			*init_60m_fclk;
+ ! 	struct clk			*usbtll_fck;
+ ! 	struct clk			*usbtll_ick;
+   
+   	void __iomem			*uhh_base;
+   	void __iomem			*tll_base;
+ --- 157,163 ----
+   	struct clk			*usbhost_p2_fck;
+   	struct clk			*usbtll_p2_fck;
+   	struct clk			*init_60m_fclk;
+ ! 	struct clk			*ehci_logic_fck;
+   
+   	void __iomem			*uhh_base;
+   	void __iomem			*tll_base;
+ ***************
+ *** 169,175 ****
+   
+   	u32				usbhs_rev;
+   	spinlock_t			lock;
+ - 	int				count;
+   };
+   /*-------------------------------------------------------------------------*/
+   
+ --- 166,171 ----
+ ***************
+ *** 319,587 ****
+   	return ret;
+   }
+   
+ - /**
+ -  * usbhs_omap_probe - initialize TI-based HCDs
+ -  *
+ -  * Allocates basic resources for this USB host controller.
+ -  */
+ - static int __devinit usbhs_omap_probe(struct platform_device *pdev)
+ - {
+ - 	struct device			*dev =  &pdev->dev;
+ - 	struct usbhs_omap_platform_data	*pdata = dev->platform_data;
+ - 	struct usbhs_hcd_omap		*omap;
+ - 	struct resource			*res;
+ - 	int				ret = 0;
+ - 	int				i;
+ - 
+ - 	if (!pdata) {
+ - 		dev_err(dev, "Missing platform data\n");
+ - 		ret = -ENOMEM;
+ - 		goto end_probe;
+ - 	}
+ - 
+ - 	omap = kzalloc(sizeof(*omap), GFP_KERNEL);
+ - 	if (!omap) {
+ - 		dev_err(dev, "Memory allocation failed\n");
+ - 		ret = -ENOMEM;
+ - 		goto end_probe;
+ - 	}
+ - 
+ - 	spin_lock_init(&omap->lock);
+ - 
+ - 	for (i = 0; i < OMAP3_HS_USB_PORTS; i++)
+ - 		omap->platdata.port_mode[i] = pdata->port_mode[i];
+ - 
+ - 	omap->platdata.ehci_data = pdata->ehci_data;
+ - 	omap->platdata.ohci_data = pdata->ohci_data;
+ - 
+ - 	omap->usbhost_ick = clk_get(dev, "usbhost_ick");
+ - 	if (IS_ERR(omap->usbhost_ick)) {
+ - 		ret =  PTR_ERR(omap->usbhost_ick);
+ - 		dev_err(dev, "usbhost_ick failed error:%d\n", ret);
+ - 		goto err_end;
+ - 	}
+ - 
+ - 	omap->usbhost_hs_fck = clk_get(dev, "hs_fck");
+ - 	if (IS_ERR(omap->usbhost_hs_fck)) {
+ - 		ret = PTR_ERR(omap->usbhost_hs_fck);
+ - 		dev_err(dev, "usbhost_hs_fck failed error:%d\n", ret);
+ - 		goto err_usbhost_ick;
+ - 	}
+ - 
+ - 	omap->usbhost_fs_fck = clk_get(dev, "fs_fck");
+ - 	if (IS_ERR(omap->usbhost_fs_fck)) {
+ - 		ret = PTR_ERR(omap->usbhost_fs_fck);
+ - 		dev_err(dev, "usbhost_fs_fck failed error:%d\n", ret);
+ - 		goto err_usbhost_hs_fck;
+ - 	}
+ - 
+ - 	omap->usbtll_fck = clk_get(dev, "usbtll_fck");
+ - 	if (IS_ERR(omap->usbtll_fck)) {
+ - 		ret = PTR_ERR(omap->usbtll_fck);
+ - 		dev_err(dev, "usbtll_fck failed error:%d\n", ret);
+ - 		goto err_usbhost_fs_fck;
+ - 	}
+ - 
+ - 	omap->usbtll_ick = clk_get(dev, "usbtll_ick");
+ - 	if (IS_ERR(omap->usbtll_ick)) {
+ - 		ret = PTR_ERR(omap->usbtll_ick);
+ - 		dev_err(dev, "usbtll_ick failed error:%d\n", ret);
+ - 		goto err_usbtll_fck;
+ - 	}
+ - 
+ - 	omap->utmi_p1_fck = clk_get(dev, "utmi_p1_gfclk");
+ - 	if (IS_ERR(omap->utmi_p1_fck)) {
+ - 		ret = PTR_ERR(omap->utmi_p1_fck);
+ - 		dev_err(dev, "utmi_p1_gfclk failed error:%d\n",	ret);
+ - 		goto err_usbtll_ick;
+ - 	}
+ - 
+ - 	omap->xclk60mhsp1_ck = clk_get(dev, "xclk60mhsp1_ck");
+ - 	if (IS_ERR(omap->xclk60mhsp1_ck)) {
+ - 		ret = PTR_ERR(omap->xclk60mhsp1_ck);
+ - 		dev_err(dev, "xclk60mhsp1_ck failed error:%d\n", ret);
+ - 		goto err_utmi_p1_fck;
+ - 	}
+ - 
+ - 	omap->utmi_p2_fck = clk_get(dev, "utmi_p2_gfclk");
+ - 	if (IS_ERR(omap->utmi_p2_fck)) {
+ - 		ret = PTR_ERR(omap->utmi_p2_fck);
+ - 		dev_err(dev, "utmi_p2_gfclk failed error:%d\n", ret);
+ - 		goto err_xclk60mhsp1_ck;
+ - 	}
+ - 
+ - 	omap->xclk60mhsp2_ck = clk_get(dev, "xclk60mhsp2_ck");
+ - 	if (IS_ERR(omap->xclk60mhsp2_ck)) {
+ - 		ret = PTR_ERR(omap->xclk60mhsp2_ck);
+ - 		dev_err(dev, "xclk60mhsp2_ck failed error:%d\n", ret);
+ - 		goto err_utmi_p2_fck;
+ - 	}
+ - 
+ - 	omap->usbhost_p1_fck = clk_get(dev, "usb_host_hs_utmi_p1_clk");
+ - 	if (IS_ERR(omap->usbhost_p1_fck)) {
+ - 		ret = PTR_ERR(omap->usbhost_p1_fck);
+ - 		dev_err(dev, "usbhost_p1_fck failed error:%d\n", ret);
+ - 		goto err_xclk60mhsp2_ck;
+ - 	}
+ - 
+ - 	omap->usbtll_p1_fck = clk_get(dev, "usb_tll_hs_usb_ch0_clk");
+ - 	if (IS_ERR(omap->usbtll_p1_fck)) {
+ - 		ret = PTR_ERR(omap->usbtll_p1_fck);
+ - 		dev_err(dev, "usbtll_p1_fck failed error:%d\n", ret);
+ - 		goto err_usbhost_p1_fck;
+ - 	}
+ - 
+ - 	omap->usbhost_p2_fck = clk_get(dev, "usb_host_hs_utmi_p2_clk");
+ - 	if (IS_ERR(omap->usbhost_p2_fck)) {
+ - 		ret = PTR_ERR(omap->usbhost_p2_fck);
+ - 		dev_err(dev, "usbhost_p2_fck failed error:%d\n", ret);
+ - 		goto err_usbtll_p1_fck;
+ - 	}
+ - 
+ - 	omap->usbtll_p2_fck = clk_get(dev, "usb_tll_hs_usb_ch1_clk");
+ - 	if (IS_ERR(omap->usbtll_p2_fck)) {
+ - 		ret = PTR_ERR(omap->usbtll_p2_fck);
+ - 		dev_err(dev, "usbtll_p2_fck failed error:%d\n", ret);
+ - 		goto err_usbhost_p2_fck;
+ - 	}
+ - 
+ - 	omap->init_60m_fclk = clk_get(dev, "init_60m_fclk");
+ - 	if (IS_ERR(omap->init_60m_fclk)) {
+ - 		ret = PTR_ERR(omap->init_60m_fclk);
+ - 		dev_err(dev, "init_60m_fclk failed error:%d\n", ret);
+ - 		goto err_usbtll_p2_fck;
+ - 	}
+ - 
+ - 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "uhh");
+ - 	if (!res) {
+ - 		dev_err(dev, "UHH EHCI get resource failed\n");
+ - 		ret = -ENODEV;
+ - 		goto err_init_60m_fclk;
+ - 	}
+ - 
+ - 	omap->uhh_base = ioremap(res->start, resource_size(res));
+ - 	if (!omap->uhh_base) {
+ - 		dev_err(dev, "UHH ioremap failed\n");
+ - 		ret = -ENOMEM;
+ - 		goto err_init_60m_fclk;
+ - 	}
+ - 
+ - 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tll");
+ - 	if (!res) {
+ - 		dev_err(dev, "UHH EHCI get resource failed\n");
+ - 		ret = -ENODEV;
+ - 		goto err_tll;
+ - 	}
+ - 
+ - 	omap->tll_base = ioremap(res->start, resource_size(res));
+ - 	if (!omap->tll_base) {
+ - 		dev_err(dev, "TLL ioremap failed\n");
+ - 		ret = -ENOMEM;
+ - 		goto err_tll;
+ - 	}
+ - 
+ - 	platform_set_drvdata(pdev, omap);
+ - 
+ - 	ret = omap_usbhs_alloc_children(pdev);
+ - 	if (ret) {
+ - 		dev_err(dev, "omap_usbhs_alloc_children failed\n");
+ - 		goto err_alloc;
+ - 	}
+ - 
+ - 	goto end_probe;
+ - 
+ - err_alloc:
+ - 	iounmap(omap->tll_base);
+ - 
+ - err_tll:
+ - 	iounmap(omap->uhh_base);
+ - 
+ - err_init_60m_fclk:
+ - 	clk_put(omap->init_60m_fclk);
+ - 
+ - err_usbtll_p2_fck:
+ - 	clk_put(omap->usbtll_p2_fck);
+ - 
+ - err_usbhost_p2_fck:
+ - 	clk_put(omap->usbhost_p2_fck);
+ - 
+ - err_usbtll_p1_fck:
+ - 	clk_put(omap->usbtll_p1_fck);
+ - 
+ - err_usbhost_p1_fck:
+ - 	clk_put(omap->usbhost_p1_fck);
+ - 
+ - err_xclk60mhsp2_ck:
+ - 	clk_put(omap->xclk60mhsp2_ck);
+ - 
+ - err_utmi_p2_fck:
+ - 	clk_put(omap->utmi_p2_fck);
+ - 
+ - err_xclk60mhsp1_ck:
+ - 	clk_put(omap->xclk60mhsp1_ck);
+ - 
+ - err_utmi_p1_fck:
+ - 	clk_put(omap->utmi_p1_fck);
+ - 
+ - err_usbtll_ick:
+ - 	clk_put(omap->usbtll_ick);
+ - 
+ - err_usbtll_fck:
+ - 	clk_put(omap->usbtll_fck);
+ - 
+ - err_usbhost_fs_fck:
+ - 	clk_put(omap->usbhost_fs_fck);
+ - 
+ - err_usbhost_hs_fck:
+ - 	clk_put(omap->usbhost_hs_fck);
+ - 
+ - err_usbhost_ick:
+ - 	clk_put(omap->usbhost_ick);
+ - 
+ - err_end:
+ - 	kfree(omap);
+ - 
+ - end_probe:
+ - 	return ret;
+ - }
+ - 
+ - /**
+ -  * usbhs_omap_remove - shutdown processing for UHH & TLL HCDs
+ -  * @pdev: USB Host Controller being removed
+ -  *
+ -  * Reverses the effect of usbhs_omap_probe().
+ -  */
+ - static int __devexit usbhs_omap_remove(struct platform_device *pdev)
+ - {
+ - 	struct usbhs_hcd_omap *omap = platform_get_drvdata(pdev);
+ - 
+ - 	if (omap->count != 0) {
+ - 		dev_err(&pdev->dev,
+ - 			"Either EHCI or OHCI is still using usbhs core\n");
+ - 		return -EBUSY;
+ - 	}
+ - 
+ - 	iounmap(omap->tll_base);
+ - 	iounmap(omap->uhh_base);
+ - 	clk_put(omap->init_60m_fclk);
+ - 	clk_put(omap->usbtll_p2_fck);
+ - 	clk_put(omap->usbhost_p2_fck);
+ - 	clk_put(omap->usbtll_p1_fck);
+ - 	clk_put(omap->usbhost_p1_fck);
+ - 	clk_put(omap->xclk60mhsp2_ck);
+ - 	clk_put(omap->utmi_p2_fck);
+ - 	clk_put(omap->xclk60mhsp1_ck);
+ - 	clk_put(omap->utmi_p1_fck);
+ - 	clk_put(omap->usbtll_ick);
+ - 	clk_put(omap->usbtll_fck);
+ - 	clk_put(omap->usbhost_fs_fck);
+ - 	clk_put(omap->usbhost_hs_fck);
+ - 	clk_put(omap->usbhost_ick);
+ - 	kfree(omap);
+ - 
+ - 	return 0;
+ - }
+ - 
+   static bool is_ohci_port(enum usbhs_omap_port_mode pmode)
+   {
+   	switch (pmode) {
+ --- 315,320 ----
+ ***************
+ *** 689,718 ****
+   	}
+   }
+   
+ ! static int usbhs_enable(struct device *dev)
+   {
+   	struct usbhs_hcd_omap		*omap = dev_get_drvdata(dev);
+   	struct usbhs_omap_platform_data	*pdata = &omap->platdata;
+ ! 	unsigned long			flags = 0;
+ ! 	int				ret = 0;
+ ! 	unsigned long			timeout;
+ ! 	unsigned			reg;
+   
+ - 	dev_dbg(dev, "starting TI HSUSB Controller\n");
+   	if (!pdata) {
+   		dev_dbg(dev, "missing platform_data\n");
+   		return  -ENODEV;
+   	}
+   
+   	spin_lock_irqsave(&omap->lock, flags);
+ - 	if (omap->count > 0)
+ - 		goto end_count;
+   
+ ! 	clk_enable(omap->usbhost_ick);
+ ! 	clk_enable(omap->usbhost_hs_fck);
+ ! 	clk_enable(omap->usbhost_fs_fck);
+ ! 	clk_enable(omap->usbtll_fck);
+ ! 	clk_enable(omap->usbtll_ick);
+   
+   	if (pdata->ehci_data->phy_reset) {
+   		if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) {
+ --- 422,506 ----
+   	}
+   }
+   
+ ! static int usbhs_runtime_resume(struct device *dev)
+   {
+   	struct usbhs_hcd_omap		*omap = dev_get_drvdata(dev);
+   	struct usbhs_omap_platform_data	*pdata = &omap->platdata;
+ ! 	unsigned long			flags;
+ ! 
+ ! 	dev_dbg(dev, "usbhs_runtime_resume\n");
+ ! 
+ ! 	if (!pdata) {
+ ! 		dev_dbg(dev, "missing platform_data\n");
+ ! 		return  -ENODEV;
+ ! 	}
+ ! 
+ ! 	spin_lock_irqsave(&omap->lock, flags);
+ ! 
+ ! 	if (omap->ehci_logic_fck && !IS_ERR(omap->ehci_logic_fck))
+ ! 		clk_enable(omap->ehci_logic_fck);
+ ! 
+ ! 	if (is_ehci_tll_mode(pdata->port_mode[0])) {
+ ! 		clk_enable(omap->usbhost_p1_fck);
+ ! 		clk_enable(omap->usbtll_p1_fck);
+ ! 	}
+ ! 	if (is_ehci_tll_mode(pdata->port_mode[1])) {
+ ! 		clk_enable(omap->usbhost_p2_fck);
+ ! 		clk_enable(omap->usbtll_p2_fck);
+ ! 	}
+ ! 	clk_enable(omap->utmi_p1_fck);
+ ! 	clk_enable(omap->utmi_p2_fck);
+ ! 
+ ! 	spin_unlock_irqrestore(&omap->lock, flags);
+ ! 
+ ! 	return 0;
+ ! }
+ ! 
+ ! static int usbhs_runtime_suspend(struct device *dev)
+ ! {
+ ! 	struct usbhs_hcd_omap		*omap = dev_get_drvdata(dev);
+ ! 	struct usbhs_omap_platform_data	*pdata = &omap->platdata;
+ ! 	unsigned long			flags;
+ ! 
+ ! 	dev_dbg(dev, "usbhs_runtime_suspend\n");
+   
+   	if (!pdata) {
+   		dev_dbg(dev, "missing platform_data\n");
+   		return  -ENODEV;
+   	}
+   
+   	spin_lock_irqsave(&omap->lock, flags);
+   
+ ! 	if (is_ehci_tll_mode(pdata->port_mode[0])) {
+ ! 		clk_disable(omap->usbhost_p1_fck);
+ ! 		clk_disable(omap->usbtll_p1_fck);
+ ! 	}
+ ! 	if (is_ehci_tll_mode(pdata->port_mode[1])) {
+ ! 		clk_disable(omap->usbhost_p2_fck);
+ ! 		clk_disable(omap->usbtll_p2_fck);
+ ! 	}
+ ! 	clk_disable(omap->utmi_p2_fck);
+ ! 	clk_disable(omap->utmi_p1_fck);
+ ! 
+ ! 	if (omap->ehci_logic_fck && !IS_ERR(omap->ehci_logic_fck))
+ ! 		clk_disable(omap->ehci_logic_fck);
+ ! 
+ ! 	spin_unlock_irqrestore(&omap->lock, flags);
+ ! 
+ ! 	return 0;
+ ! }
+ ! 
+ ! static void omap_usbhs_init(struct device *dev)
+ ! {
+ ! 	struct usbhs_hcd_omap		*omap = dev_get_drvdata(dev);
+ ! 	struct usbhs_omap_platform_data	*pdata = &omap->platdata;
+ ! 	unsigned long			flags;
+ ! 	unsigned			reg;
+ ! 
+ ! 	dev_dbg(dev, "starting TI HSUSB Controller\n");
+ ! 
+ ! 	pm_runtime_get_sync(dev);
+ ! 	spin_lock_irqsave(&omap->lock, flags);
+   
+   	if (pdata->ehci_data->phy_reset) {
+   		if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) {
+ ***************
+ *** 736,785 ****
+   	omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION);
+   	dev_dbg(dev, "OMAP UHH_REVISION 0x%x\n", omap->usbhs_rev);
+   
+ - 	/* perform TLL soft reset, and wait until reset is complete */
+ - 	usbhs_write(omap->tll_base, OMAP_USBTLL_SYSCONFIG,
+ - 			OMAP_USBTLL_SYSCONFIG_SOFTRESET);
+ - 
+ - 	/* Wait for TLL reset to complete */
+ - 	timeout = jiffies + msecs_to_jiffies(1000);
+ - 	while (!(usbhs_read(omap->tll_base, OMAP_USBTLL_SYSSTATUS)
+ - 			& OMAP_USBTLL_SYSSTATUS_RESETDONE)) {
+ - 		cpu_relax();
+ - 
+ - 		if (time_after(jiffies, timeout)) {
+ - 			dev_dbg(dev, "operation timed out\n");
+ - 			ret = -EINVAL;
+ - 			goto err_tll;
+ - 		}
+ - 	}
+ - 
+ - 	dev_dbg(dev, "TLL RESET DONE\n");
+ - 
+ - 	/* (1<<3) = no idle mode only for initial debugging */
+ - 	usbhs_write(omap->tll_base, OMAP_USBTLL_SYSCONFIG,
+ - 			OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
+ - 			OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
+ - 			OMAP_USBTLL_SYSCONFIG_AUTOIDLE);
+ - 
+ - 	/* Put UHH in NoIdle/NoStandby mode */
+ - 	reg = usbhs_read(omap->uhh_base, OMAP_UHH_SYSCONFIG);
+ - 	if (is_omap_usbhs_rev1(omap)) {
+ - 		reg |= (OMAP_UHH_SYSCONFIG_ENAWAKEUP
+ - 				| OMAP_UHH_SYSCONFIG_SIDLEMODE
+ - 				| OMAP_UHH_SYSCONFIG_CACTIVITY
+ - 				| OMAP_UHH_SYSCONFIG_MIDLEMODE);
+ - 		reg &= ~OMAP_UHH_SYSCONFIG_AUTOIDLE;
+ - 
+ - 
+ - 	} else if (is_omap_usbhs_rev2(omap)) {
+ - 		reg &= ~OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR;
+ - 		reg |= OMAP4_UHH_SYSCONFIG_NOIDLE;
+ - 		reg &= ~OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR;
+ - 		reg |= OMAP4_UHH_SYSCONFIG_NOSTDBY;
+ - 	}
+ - 
+ - 	usbhs_write(omap->uhh_base, OMAP_UHH_SYSCONFIG, reg);
+ - 
+   	reg = usbhs_read(omap->uhh_base, OMAP_UHH_HOSTCONFIG);
+   	/* setup ULPI bypass and burst configurations */
+   	reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
+ --- 524,529 ----
+ ***************
+ *** 825,873 ****
+   		reg &= ~OMAP4_P1_MODE_CLEAR;
+   		reg &= ~OMAP4_P2_MODE_CLEAR;
+   
+ - 		if (is_ehci_phy_mode(pdata->port_mode[0])) {
+ - 			ret = clk_set_parent(omap->utmi_p1_fck,
+ - 						omap->xclk60mhsp1_ck);
+ - 			if (ret != 0) {
+ - 				dev_err(dev, "xclk60mhsp1_ck set parent"
+ - 				"failed error:%d\n", ret);
+ - 				goto err_tll;
+ - 			}
+ - 		} else if (is_ehci_tll_mode(pdata->port_mode[0])) {
+ - 			ret = clk_set_parent(omap->utmi_p1_fck,
+ - 						omap->init_60m_fclk);
+ - 			if (ret != 0) {
+ - 				dev_err(dev, "init_60m_fclk set parent"
+ - 				"failed error:%d\n", ret);
+ - 				goto err_tll;
+ - 			}
+ - 			clk_enable(omap->usbhost_p1_fck);
+ - 			clk_enable(omap->usbtll_p1_fck);
+ - 		}
+ - 
+ - 		if (is_ehci_phy_mode(pdata->port_mode[1])) {
+ - 			ret = clk_set_parent(omap->utmi_p2_fck,
+ - 						omap->xclk60mhsp2_ck);
+ - 			if (ret != 0) {
+ - 				dev_err(dev, "xclk60mhsp1_ck set parent"
+ - 					"failed error:%d\n", ret);
+ - 				goto err_tll;
+ - 			}
+ - 		} else if (is_ehci_tll_mode(pdata->port_mode[1])) {
+ - 			ret = clk_set_parent(omap->utmi_p2_fck,
+ - 						omap->init_60m_fclk);
+ - 			if (ret != 0) {
+ - 				dev_err(dev, "init_60m_fclk set parent"
+ - 				"failed error:%d\n", ret);
+ - 				goto err_tll;
+ - 			}
+ - 			clk_enable(omap->usbhost_p2_fck);
+ - 			clk_enable(omap->usbtll_p2_fck);
+ - 		}
+ - 
+ - 		clk_enable(omap->utmi_p1_fck);
+ - 		clk_enable(omap->utmi_p2_fck);
+ - 
+   		if (is_ehci_tll_mode(pdata->port_mode[0]) ||
+   			(is_ohci_port(pdata->port_mode[0])))
+   			reg |= OMAP4_P1_MODE_TLL;
+ --- 569,574 ----
+ ***************
+ *** 913,924 ****
+   				(pdata->ehci_data->reset_gpio_port[1], 1);
+   	}
+   
+ - end_count:
+ - 	omap->count++;
+   	spin_unlock_irqrestore(&omap->lock, flags);
+ ! 	return 0;
+   
+ - err_tll:
+   	if (pdata->ehci_data->phy_reset) {
+   		if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0]))
+   			gpio_free(pdata->ehci_data->reset_gpio_port[0]);
+ --- 614,628 ----
+   				(pdata->ehci_data->reset_gpio_port[1], 1);
+   	}
+   
+   	spin_unlock_irqrestore(&omap->lock, flags);
+ ! 	pm_runtime_put_sync(dev);
+ ! }
+ ! 
+ ! static void omap_usbhs_deinit(struct device *dev)
+ ! {
+ ! 	struct usbhs_hcd_omap		*omap = dev_get_drvdata(dev);
+ ! 	struct usbhs_omap_platform_data	*pdata = &omap->platdata;
+   
+   	if (pdata->ehci_data->phy_reset) {
+   		if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0]))
+   			gpio_free(pdata->ehci_data->reset_gpio_port[0]);
+ ***************
+ *** 926,1048 ****
+   		if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1]))
+   			gpio_free(pdata->ehci_data->reset_gpio_port[1]);
+   	}
+ - 
+ - 	clk_disable(omap->usbtll_ick);
+ - 	clk_disable(omap->usbtll_fck);
+ - 	clk_disable(omap->usbhost_fs_fck);
+ - 	clk_disable(omap->usbhost_hs_fck);
+ - 	clk_disable(omap->usbhost_ick);
+ - 	spin_unlock_irqrestore(&omap->lock, flags);
+ - 	return ret;
+   }
+   
+ ! static void usbhs_disable(struct device *dev)
+   {
+ ! 	struct usbhs_hcd_omap		*omap = dev_get_drvdata(dev);
+ ! 	struct usbhs_omap_platform_data	*pdata = &omap->platdata;
+ ! 	unsigned long			flags = 0;
+ ! 	unsigned long			timeout;
+   
+ ! 	dev_dbg(dev, "stopping TI HSUSB Controller\n");
+   
+ ! 	spin_lock_irqsave(&omap->lock, flags);
+   
+ ! 	if (omap->count == 0)
+ ! 		goto end_disble;
+   
+ ! 	omap->count--;
+   
+ ! 	if (omap->count != 0)
+ ! 		goto end_disble;
+   
+ - 	/* Reset OMAP modules for insmod/rmmod to work */
+ - 	usbhs_write(omap->uhh_base, OMAP_UHH_SYSCONFIG,
+ - 			is_omap_usbhs_rev2(omap) ?
+ - 			OMAP4_UHH_SYSCONFIG_SOFTRESET :
+ - 			OMAP_UHH_SYSCONFIG_SOFTRESET);
+   
+ ! 	timeout = jiffies + msecs_to_jiffies(100);
+ ! 	while (!(usbhs_read(omap->uhh_base, OMAP_UHH_SYSSTATUS)
+ ! 				& (1 << 0))) {
+ ! 		cpu_relax();
+   
+ ! 		if (time_after(jiffies, timeout))
+ ! 			dev_dbg(dev, "operation timed out\n");
+   	}
+   
+ ! 	while (!(usbhs_read(omap->uhh_base, OMAP_UHH_SYSSTATUS)
+ ! 				& (1 << 1))) {
+ ! 		cpu_relax();
+   
+ ! 		if (time_after(jiffies, timeout))
+ ! 			dev_dbg(dev, "operation timed out\n");
+   	}
+   
+ ! 	while (!(usbhs_read(omap->uhh_base, OMAP_UHH_SYSSTATUS)
+ ! 				& (1 << 2))) {
+ ! 		cpu_relax();
+   
+ ! 		if (time_after(jiffies, timeout))
+ ! 			dev_dbg(dev, "operation timed out\n");
+   	}
+   
+ ! 	usbhs_write(omap->tll_base, OMAP_USBTLL_SYSCONFIG, (1 << 1));
+   
+ ! 	while (!(usbhs_read(omap->tll_base, OMAP_USBTLL_SYSSTATUS)
+ ! 				& (1 << 0))) {
+ ! 		cpu_relax();
+   
+ ! 		if (time_after(jiffies, timeout))
+ ! 			dev_dbg(dev, "operation timed out\n");
+   	}
+   
+ ! 	if (is_omap_usbhs_rev2(omap)) {
+ ! 		if (is_ehci_tll_mode(pdata->port_mode[0]))
+ ! 			clk_disable(omap->usbtll_p1_fck);
+ ! 		if (is_ehci_tll_mode(pdata->port_mode[1]))
+ ! 			clk_disable(omap->usbtll_p2_fck);
+ ! 		clk_disable(omap->utmi_p2_fck);
+ ! 		clk_disable(omap->utmi_p1_fck);
+   	}
+   
+ ! 	clk_disable(omap->usbtll_ick);
+ ! 	clk_disable(omap->usbtll_fck);
+ ! 	clk_disable(omap->usbhost_fs_fck);
+ ! 	clk_disable(omap->usbhost_hs_fck);
+ ! 	clk_disable(omap->usbhost_ick);
+   
+ ! 	/* The gpio_free migh sleep; so unlock the spinlock */
+ ! 	spin_unlock_irqrestore(&omap->lock, flags);
+   
+ ! 	if (pdata->ehci_data->phy_reset) {
+ ! 		if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0]))
+ ! 			gpio_free(pdata->ehci_data->reset_gpio_port[0]);
+   
+ ! 		if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1]))
+ ! 			gpio_free(pdata->ehci_data->reset_gpio_port[1]);
+   	}
+ - 	return;
+   
+ ! end_disble:
+ ! 	spin_unlock_irqrestore(&omap->lock, flags);
+ ! }
+   
+ ! int omap_usbhs_enable(struct device *dev)
+ ! {
+ ! 	return  usbhs_enable(dev->parent);
+   }
+ - EXPORT_SYMBOL_GPL(omap_usbhs_enable);
+   
+ ! void omap_usbhs_disable(struct device *dev)
+   {
+ ! 	usbhs_disable(dev->parent);
+   }
+ ! EXPORT_SYMBOL_GPL(omap_usbhs_disable);
+   
+   static struct platform_driver usbhs_omap_driver = {
+   	.driver = {
+   		.name		= (char *)usbhs_driver_name,
+   		.owner		= THIS_MODULE,
+   	},
+   	.remove		= __exit_p(usbhs_omap_remove),
+   };
+ --- 630,901 ----
+   		if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1]))
+   			gpio_free(pdata->ehci_data->reset_gpio_port[1]);
+   	}
+   }
+   
+ ! 
+ ! /**
+ !  * usbhs_omap_probe - initialize TI-based HCDs
+ !  *
+ !  * Allocates basic resources for this USB host controller.
+ !  */
+ ! static int __devinit usbhs_omap_probe(struct platform_device *pdev)
+   {
+ ! 	struct device			*dev =  &pdev->dev;
+ ! 	struct usbhs_omap_platform_data	*pdata = dev->platform_data;
+ ! 	struct usbhs_hcd_omap		*omap;
+ ! 	struct resource			*res;
+ ! 	int				ret = 0;
+ ! 	int				i;
+ ! 
+ ! 	if (!pdata) {
+ ! 		dev_err(dev, "Missing platform data\n");
+ ! 		ret = -ENOMEM;
+ ! 		goto end_probe;
+ ! 	}
+   
+ ! 	omap = kzalloc(sizeof(*omap), GFP_KERNEL);
+ ! 	if (!omap) {
+ ! 		dev_err(dev, "Memory allocation failed\n");
+ ! 		ret = -ENOMEM;
+ ! 		goto end_probe;
+ ! 	}
+   
+ ! 	spin_lock_init(&omap->lock);
+   
+ ! 	for (i = 0; i < OMAP3_HS_USB_PORTS; i++)
+ ! 		omap->platdata.port_mode[i] = pdata->port_mode[i];
+   
+ ! 	omap->platdata.ehci_data = pdata->ehci_data;
+ ! 	omap->platdata.ohci_data = pdata->ohci_data;
+   
+ ! 	pm_runtime_enable(dev);
+   
+   
+ ! 	for (i = 0; i < OMAP3_HS_USB_PORTS; i++)
+ ! 		if (is_ehci_phy_mode(i) || is_ehci_tll_mode(i) ||
+ ! 			is_ehci_hsic_mode(i)) {
+ ! 			omap->ehci_logic_fck = clk_get(dev, "ehci_logic_fck");
+ ! 			if (IS_ERR(omap->ehci_logic_fck)) {
+ ! 				ret = PTR_ERR(omap->ehci_logic_fck);
+ ! 				dev_warn(dev, "ehci_logic_fck failed:%d\n",
+ ! 					 ret);
+ ! 			}
+ ! 			break;
+ ! 		}
+   
+ ! 	omap->utmi_p1_fck = clk_get(dev, "utmi_p1_gfclk");
+ ! 	if (IS_ERR(omap->utmi_p1_fck)) {
+ ! 		ret = PTR_ERR(omap->utmi_p1_fck);
+ ! 		dev_err(dev, "utmi_p1_gfclk failed error:%d\n",	ret);
+ ! 		goto err_end;
+   	}
+   
+ ! 	omap->xclk60mhsp1_ck = clk_get(dev, "xclk60mhsp1_ck");
+ ! 	if (IS_ERR(omap->xclk60mhsp1_ck)) {
+ ! 		ret = PTR_ERR(omap->xclk60mhsp1_ck);
+ ! 		dev_err(dev, "xclk60mhsp1_ck failed error:%d\n", ret);
+ ! 		goto err_utmi_p1_fck;
+ ! 	}
+   
+ ! 	omap->utmi_p2_fck = clk_get(dev, "utmi_p2_gfclk");
+ ! 	if (IS_ERR(omap->utmi_p2_fck)) {
+ ! 		ret = PTR_ERR(omap->utmi_p2_fck);
+ ! 		dev_err(dev, "utmi_p2_gfclk failed error:%d\n", ret);
+ ! 		goto err_xclk60mhsp1_ck;
+ ! 	}
+ ! 
+ ! 	omap->xclk60mhsp2_ck = clk_get(dev, "xclk60mhsp2_ck");
+ ! 	if (IS_ERR(omap->xclk60mhsp2_ck)) {
+ ! 		ret = PTR_ERR(omap->xclk60mhsp2_ck);
+ ! 		dev_err(dev, "xclk60mhsp2_ck failed error:%d\n", ret);
+ ! 		goto err_utmi_p2_fck;
+ ! 	}
+ ! 
+ ! 	omap->usbhost_p1_fck = clk_get(dev, "usb_host_hs_utmi_p1_clk");
+ ! 	if (IS_ERR(omap->usbhost_p1_fck)) {
+ ! 		ret = PTR_ERR(omap->usbhost_p1_fck);
+ ! 		dev_err(dev, "usbhost_p1_fck failed error:%d\n", ret);
+ ! 		goto err_xclk60mhsp2_ck;
+ ! 	}
+ ! 
+ ! 	omap->usbtll_p1_fck = clk_get(dev, "usb_tll_hs_usb_ch0_clk");
+ ! 	if (IS_ERR(omap->usbtll_p1_fck)) {
+ ! 		ret = PTR_ERR(omap->usbtll_p1_fck);
+ ! 		dev_err(dev, "usbtll_p1_fck failed error:%d\n", ret);
+ ! 		goto err_usbhost_p1_fck;
+ ! 	}
+ ! 
+ ! 	omap->usbhost_p2_fck = clk_get(dev, "usb_host_hs_utmi_p2_clk");
+ ! 	if (IS_ERR(omap->usbhost_p2_fck)) {
+ ! 		ret = PTR_ERR(omap->usbhost_p2_fck);
+ ! 		dev_err(dev, "usbhost_p2_fck failed error:%d\n", ret);
+ ! 		goto err_usbtll_p1_fck;
+   	}
+   
+ ! 	omap->usbtll_p2_fck = clk_get(dev, "usb_tll_hs_usb_ch1_clk");
+ ! 	if (IS_ERR(omap->usbtll_p2_fck)) {
+ ! 		ret = PTR_ERR(omap->usbtll_p2_fck);
+ ! 		dev_err(dev, "usbtll_p2_fck failed error:%d\n", ret);
+ ! 		goto err_usbhost_p2_fck;
+ ! 	}
+   
+ ! 	omap->init_60m_fclk = clk_get(dev, "init_60m_fclk");
+ ! 	if (IS_ERR(omap->init_60m_fclk)) {
+ ! 		ret = PTR_ERR(omap->init_60m_fclk);
+ ! 		dev_err(dev, "init_60m_fclk failed error:%d\n", ret);
+ ! 		goto err_usbtll_p2_fck;
+   	}
+   
+ ! 	if (is_ehci_phy_mode(pdata->port_mode[0])) {
+ ! 		/* for OMAP3 , the clk set paretn fails */
+ ! 		ret = clk_set_parent(omap->utmi_p1_fck,
+ ! 					omap->xclk60mhsp1_ck);
+ ! 		if (ret != 0)
+ ! 			dev_err(dev, "xclk60mhsp1_ck set parent"
+ ! 				"failed error:%d\n", ret);
+ ! 	} else if (is_ehci_tll_mode(pdata->port_mode[0])) {
+ ! 		ret = clk_set_parent(omap->utmi_p1_fck,
+ ! 					omap->init_60m_fclk);
+ ! 		if (ret != 0)
+ ! 			dev_err(dev, "init_60m_fclk set parent"
+ ! 				"failed error:%d\n", ret);
+ ! 	}
+   
+ ! 	if (is_ehci_phy_mode(pdata->port_mode[1])) {
+ ! 		ret = clk_set_parent(omap->utmi_p2_fck,
+ ! 					omap->xclk60mhsp2_ck);
+ ! 		if (ret != 0)
+ ! 			dev_err(dev, "xclk60mhsp2_ck set parent"
+ ! 					"failed error:%d\n", ret);
+ ! 	} else if (is_ehci_tll_mode(pdata->port_mode[1])) {
+ ! 		ret = clk_set_parent(omap->utmi_p2_fck,
+ ! 						omap->init_60m_fclk);
+ ! 		if (ret != 0)
+ ! 			dev_err(dev, "init_60m_fclk set parent"
+ ! 				"failed error:%d\n", ret);
+ ! 	}
+   
+ ! 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "uhh");
+ ! 	if (!res) {
+ ! 		dev_err(dev, "UHH EHCI get resource failed\n");
+ ! 		ret = -ENODEV;
+ ! 		goto err_init_60m_fclk;
+   	}
+   
+ ! 	omap->uhh_base = ioremap(res->start, resource_size(res));
+ ! 	if (!omap->uhh_base) {
+ ! 		dev_err(dev, "UHH ioremap failed\n");
+ ! 		ret = -ENOMEM;
+ ! 		goto err_init_60m_fclk;
+   	}
+   
+ ! 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tll");
+ ! 	if (!res) {
+ ! 		dev_err(dev, "UHH EHCI get resource failed\n");
+ ! 		ret = -ENODEV;
+ ! 		goto err_tll;
+ ! 	}
+   
+ ! 	omap->tll_base = ioremap(res->start, resource_size(res));
+ ! 	if (!omap->tll_base) {
+ ! 		dev_err(dev, "TLL ioremap failed\n");
+ ! 		ret = -ENOMEM;
+ ! 		goto err_tll;
+ ! 	}
+   
+ ! 	platform_set_drvdata(pdev, omap);
+   
+ ! 	ret = omap_usbhs_alloc_children(pdev);
+ ! 	if (ret) {
+ ! 		dev_err(dev, "omap_usbhs_alloc_children failed\n");
+ ! 		goto err_alloc;
+   	}
+   
+ ! 	omap_usbhs_init(dev);
+   
+ ! 	goto end_probe;
+ ! 
+ ! err_alloc:
+ ! 	iounmap(omap->tll_base);
+ ! 
+ ! err_tll:
+ ! 	iounmap(omap->uhh_base);
+ ! 
+ ! err_init_60m_fclk:
+ ! 	clk_put(omap->init_60m_fclk);
+ ! 
+ ! err_usbtll_p2_fck:
+ ! 	clk_put(omap->usbtll_p2_fck);
+ ! 
+ ! err_usbhost_p2_fck:
+ ! 	clk_put(omap->usbhost_p2_fck);
+ ! 
+ ! err_usbtll_p1_fck:
+ ! 	clk_put(omap->usbtll_p1_fck);
+ ! 
+ ! err_usbhost_p1_fck:
+ ! 	clk_put(omap->usbhost_p1_fck);
+ ! 
+ ! err_xclk60mhsp2_ck:
+ ! 	clk_put(omap->xclk60mhsp2_ck);
+ ! 
+ ! err_utmi_p2_fck:
+ ! 	clk_put(omap->utmi_p2_fck);
+ ! 
+ ! err_xclk60mhsp1_ck:
+ ! 	clk_put(omap->xclk60mhsp1_ck);
+ ! 
+ ! err_utmi_p1_fck:
+ ! 	clk_put(omap->utmi_p1_fck);
+ ! 
+ ! err_end:
+ ! 	clk_put(omap->ehci_logic_fck);
+ ! 	pm_runtime_disable(dev);
+ ! 	kfree(omap);
+ ! 
+ ! end_probe:
+ ! 	return ret;
+   }
+   
+ ! /**
+ !  * usbhs_omap_remove - shutdown processing for UHH & TLL HCDs
+ !  * @pdev: USB Host Controller being removed
+ !  *
+ !  * Reverses the effect of usbhs_omap_probe().
+ !  */
+ ! static int __devexit usbhs_omap_remove(struct platform_device *pdev)
+   {
+ ! 	struct usbhs_hcd_omap *omap = platform_get_drvdata(pdev);
+ ! 
+ ! 	omap_usbhs_deinit(&pdev->dev);
+ ! 	iounmap(omap->tll_base);
+ ! 	iounmap(omap->uhh_base);
+ ! 	clk_put(omap->init_60m_fclk);
+ ! 	clk_put(omap->usbtll_p2_fck);
+ ! 	clk_put(omap->usbhost_p2_fck);
+ ! 	clk_put(omap->usbtll_p1_fck);
+ ! 	clk_put(omap->usbhost_p1_fck);
+ ! 	clk_put(omap->xclk60mhsp2_ck);
+ ! 	clk_put(omap->utmi_p2_fck);
+ ! 	clk_put(omap->xclk60mhsp1_ck);
+ ! 	clk_put(omap->utmi_p1_fck);
+ ! 	clk_put(omap->ehci_logic_fck);
+ ! 	pm_runtime_disable(&pdev->dev);
+ ! 	kfree(omap);
+ ! 
+ ! 	return 0;
+   }
+ ! 
+ ! static const struct dev_pm_ops usbhsomap_dev_pm_ops = {
+ ! 	.runtime_suspend	= usbhs_runtime_suspend,
+ ! 	.runtime_resume		= usbhs_runtime_resume,
+ ! };
+   
+   static struct platform_driver usbhs_omap_driver = {
+   	.driver = {
+   		.name		= (char *)usbhs_driver_name,
+   		.owner		= THIS_MODULE,
+ + 		.pm		= &usbhsomap_dev_pm_ops,
+   	},
+   	.remove		= __exit_p(usbhs_omap_remove),
+   };
+ diff -crN linux-3.2.1_o/drivers/mfd/ti_tscadc.c linux-3.2.1/drivers/mfd/ti_tscadc.c
+ *** linux-3.2.1_o/drivers/mfd/ti_tscadc.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/drivers/mfd/ti_tscadc.c	2014-11-25 13:19:15.628014097 +0900
+ ***************
+ *** 0 ****
+ --- 1,261 ----
+ + /*
+ +  * TI Touch Screen / ADC MFD driver
+ +  *
+ +  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #include <linux/module.h>
+ + #include <linux/init.h>
+ + #include <linux/slab.h>
+ + #include <linux/err.h>
+ + #include <linux/io.h>
+ + #include <linux/clk.h>
+ + #include <linux/mfd/core.h>
+ + #include <linux/pm_runtime.h>
+ + #include <linux/mfd/ti_tscadc.h>
+ + #include <linux/input/ti_tsc.h>
+ + #include <linux/platform_data/ti_adc.h>
+ + 
+ + static unsigned int tscadc_readl(struct ti_tscadc_dev *tsadc, unsigned int reg)
+ + {
+ + 	return readl(tsadc->tscadc_base + reg);
+ + }
+ + 
+ + static void tscadc_writel(struct ti_tscadc_dev *tsadc, unsigned int reg,
+ + 					unsigned int val)
+ + {
+ + 	writel(val, tsadc->tscadc_base + reg);
+ + }
+ + 
+ + static void tscadc_idle_config(struct ti_tscadc_dev *config)
+ + {
+ + 	unsigned int idleconfig;
+ + 
+ + 	idleconfig = TSCADC_STEPCONFIG_YNN | TSCADC_STEPCONFIG_INM_ADCREFM |
+ + 			TSCADC_STEPCONFIG_INP_ADCREFM | TSCADC_STEPCONFIG_YPN;
+ + 
+ + 	tscadc_writel(config, TSCADC_REG_IDLECONFIG, idleconfig);
+ + }
+ + 
+ + static int __devinit ti_tscadc_probe(struct platform_device *pdev)
+ + {
+ + 	struct ti_tscadc_dev	*tscadc;
+ + 	struct resource		*res;
+ + 	struct clk		*clk;
+ + 	struct mfd_tscadc_board	*pdata = pdev->dev.platform_data;
+ + 	struct mfd_cell		*cell;
+ + 	int			err, ctrl, children = 0;
+ + 	int			clk_value, clock_rate;
+ + 	int			tsc_wires = 0, adc_channels = 0, total_channels;
+ + 
+ + 	if (!pdata) {
+ + 		dev_err(&pdev->dev, "Could not find platform data\n");
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	if (pdata->adc_init)
+ + 		adc_channels = pdata->adc_init->adc_channels;
+ + 
+ + 	if (pdata->tsc_init)
+ + 		tsc_wires = pdata->tsc_init->wires;
+ + 
+ + 	total_channels = tsc_wires + adc_channels;
+ + 
+ + 	if (total_channels > 8) {
+ + 		dev_err(&pdev->dev, "Number of i/p channels more than 8\n");
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ + 	if (!res) {
+ + 		dev_err(&pdev->dev, "no memory resource defined.\n");
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	/* Allocate memory for device */
+ + 	tscadc = kzalloc(sizeof(struct ti_tscadc_dev), GFP_KERNEL);
+ + 	if (!tscadc) {
+ + 		dev_err(&pdev->dev, "failed to allocate memory.\n");
+ + 		return -ENOMEM;
+ + 	}
+ + 
+ + 	res = request_mem_region(res->start, resource_size(res),
+ + 			pdev->name);
+ + 	if (!res) {
+ + 		dev_err(&pdev->dev, "failed to reserve registers.\n");
+ + 		err = -EBUSY;
+ + 		goto err_free_mem;
+ + 	}
+ + 
+ + 	tscadc->tscadc_base = ioremap(res->start, resource_size(res));
+ + 	if (!tscadc->tscadc_base) {
+ + 		dev_err(&pdev->dev, "failed to map registers.\n");
+ + 		err = -ENOMEM;
+ + 		goto err_release_mem;
+ + 	}
+ + 
+ + 	tscadc->irq = platform_get_irq(pdev, 0);
+ + 	if (tscadc->irq < 0) {
+ + 		dev_err(&pdev->dev, "no irq ID is specified.\n");
+ + 		return -ENODEV;
+ + 	}
+ + 
+ + 	tscadc->dev = &pdev->dev;
+ + 
+ + 	pm_runtime_enable(&pdev->dev);
+ + 	pm_runtime_get_sync(&pdev->dev);
+ + 
+ + 	/*
+ + 	 * The TSC_ADC_Subsystem has 2 clock domains
+ + 	 * OCP_CLK and ADC_CLK.
+ + 	 * The ADC clock is expected to run at target of 3MHz,
+ + 	 * and expected to capture 12-bit data at a rate of 200 KSPS.
+ + 	 * The TSC_ADC_SS controller design assumes the OCP clock is
+ + 	 * at least 6x faster than the ADC clock.
+ + 	 */
+ + 	clk = clk_get(&pdev->dev, "adc_tsc_fck");
+ + 	if (IS_ERR(clk)) {
+ + 		dev_err(&pdev->dev, "failed to get TSC fck\n");
+ + 		err = PTR_ERR(clk);
+ + 		goto err_fail;
+ + 	}
+ + 	clock_rate = clk_get_rate(clk);
+ + 	clk_put(clk);
+ + 	clk_value = clock_rate / ADC_CLK;
+ + 	/* TSCADC_CLKDIV needs to be configured to the value minus 1 */
+ + 	clk_value = clk_value - 1;
+ + 	tscadc_writel(tscadc, TSCADC_REG_CLKDIV, clk_value);
+ + 
+ + 	/* Set the control register bits */
+ + 	ctrl = TSCADC_CNTRLREG_STEPCONFIGWRT |
+ + 			TSCADC_CNTRLREG_STEPID;
+ + 	if (pdata->tsc_init)
+ + 		ctrl |= TSCADC_CNTRLREG_4WIRE |
+ + 				TSCADC_CNTRLREG_TSCENB;
+ + 	tscadc_writel(tscadc, TSCADC_REG_CTRL, ctrl);
+ + 
+ + 	/* Set register bits for Idle Config Mode */
+ + 	if (pdata->tsc_init)
+ + 		tscadc_idle_config(tscadc);
+ + 
+ + 	/* Enable the TSC module enable bit */
+ + 	ctrl = tscadc_readl(tscadc, TSCADC_REG_CTRL);
+ + 	ctrl |= TSCADC_CNTRLREG_TSCSSENB;
+ + 	tscadc_writel(tscadc, TSCADC_REG_CTRL, ctrl);
+ + 
+ + 	/* TSC Cell */
+ + 	if (pdata->tsc_init) {
+ + 		cell = &tscadc->cells[children];
+ + 		cell->name = "tsc";
+ + 		cell->platform_data = tscadc;
+ + 		cell->pdata_size = sizeof(*tscadc);
+ + 		children++;
+ + 	}
+ + 
+ + 	/* ADC Cell */
+ + 	if (pdata->adc_init) {
+ + 		cell = &tscadc->cells[children];
+ + 		cell->name = "tiadc";
+ + 		cell->platform_data = tscadc;
+ + 		cell->pdata_size = sizeof(*tscadc);
+ + 		children++;
+ + 	}
+ + 
+ + 	err = mfd_add_devices(&pdev->dev, pdev->id, tscadc->cells,
+ + 			children, NULL, 0);
+ + 	if (err < 0)
+ + 		goto err_fail;
+ + 
+ + 	device_init_wakeup(&pdev->dev, true);
+ + 	platform_set_drvdata(pdev, tscadc);
+ + 	return 0;
+ + 
+ + err_fail:
+ + 	pm_runtime_put_sync(&pdev->dev);
+ + 	pm_runtime_disable(&pdev->dev);
+ + 	iounmap(tscadc->tscadc_base);
+ + err_release_mem:
+ + 	release_mem_region(res->start, resource_size(res));
+ + 	mfd_remove_devices(tscadc->dev);
+ + err_free_mem:
+ + 	platform_set_drvdata(pdev, NULL);
+ + 	kfree(tscadc);
+ + 	return err;
+ + }
+ + 
+ + static int __devexit ti_tscadc_remove(struct platform_device *pdev)
+ + {
+ + 	struct ti_tscadc_dev	*tscadc = platform_get_drvdata(pdev);
+ + 	struct resource		*res;
+ + 
+ + 	tscadc_writel(tscadc, TSCADC_REG_SE, 0x00);
+ + 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ + 	iounmap(tscadc->tscadc_base);
+ + 	release_mem_region(res->start, resource_size(res));
+ + 
+ + 	pm_runtime_put_sync(&pdev->dev);
+ + 	pm_runtime_disable(&pdev->dev);
+ + 
+ + 	mfd_remove_devices(tscadc->dev);
+ + 	kfree(tscadc);
+ + 
+ + 	platform_set_drvdata(pdev, NULL);
+ + 	return 0;
+ + }
+ + 
+ + static int tscadc_suspend(struct platform_device *pdev, pm_message_t state)
+ + {
+ + 	struct ti_tscadc_dev	*tscadc_dev = platform_get_drvdata(pdev);
+ + 
+ + 	tscadc_writel(tscadc_dev, TSCADC_REG_SE, 0x00);
+ + 	tscadc_dev->irqstat = tscadc_readl(tscadc_dev, TSCADC_REG_IRQENABLE);
+ + 	tscadc_dev->ctrl = tscadc_readl(tscadc_dev, TSCADC_REG_CTRL);
+ + 	pm_runtime_put_sync(&pdev->dev);
+ + 	return 0;
+ + }
+ + 
+ + static int tscadc_resume(struct platform_device *pdev)
+ + {
+ + 	struct ti_tscadc_dev	*tscadc_dev = platform_get_drvdata(pdev);
+ + 	struct mfd_tscadc_board	*pdata = pdev->dev.platform_data;
+ + 	unsigned int irq_read;
+ + 
+ + 	pm_runtime_get_sync(&pdev->dev);
+ + 
+ + 	/* context restore */
+ + 	irq_read = tscadc_readl(tscadc_dev, TSCADC_REG_IRQSTATUS);
+ + 	tscadc_writel(tscadc_dev, TSCADC_REG_IRQSTATUS, irq_read);
+ + 
+ + 	tscadc_writel(tscadc_dev, TSCADC_REG_IRQENABLE, tscadc_dev->irqstat);
+ + 	if (pdata->tsc_init)
+ + 		tscadc_idle_config(tscadc_dev);
+ + 	tscadc_writel(tscadc_dev, TSCADC_REG_SE, TSCADC_STPENB_STEPENB_TC);
+ + 	tscadc_writel(tscadc_dev, TSCADC_REG_CTRL, tscadc_dev->ctrl);
+ + 	return 0;
+ + }
+ + 
+ + static struct platform_driver ti_tscadc_driver = {
+ + 	.driver = {
+ + 		.name   = "ti_tscadc",
+ + 		.owner	= THIS_MODULE,
+ + 	},
+ + 	.probe	= ti_tscadc_probe,
+ + 	.remove	= __devexit_p(ti_tscadc_remove),
+ + 	.suspend = tscadc_suspend,
+ + 	.resume = tscadc_resume,
+ + };
+ + 
+ + module_platform_driver(ti_tscadc_driver);
+ + 
+ + MODULE_DESCRIPTION("TI touchscreen / ADC MFD controller driver");
+ + MODULE_AUTHOR("Rachna Patil <rachna@ti.com>");
+ + MODULE_LICENSE("GPL");
+ diff -crN linux-3.2.1_o/drivers/mfd/tps65217.c linux-3.2.1/drivers/mfd/tps65217.c
+ *** linux-3.2.1_o/drivers/mfd/tps65217.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/drivers/mfd/tps65217.c	2014-11-25 13:19:15.628014097 +0900
+ ***************
+ *** 0 ****
+ --- 1,253 ----
+ + /*
+ +  * tps65217.c
+ +  *
+ +  * TPS65217 chip family multi-function driver
+ +  *
+ +  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #include <linux/kernel.h>
+ + #include <linux/device.h>
+ + #include <linux/module.h>
+ + #include <linux/platform_device.h>
+ + #include <linux/init.h>
+ + #include <linux/i2c.h>
+ + #include <linux/slab.h>
+ + #include <linux/regmap.h>
+ + #include <linux/err.h>
+ + 
+ + #include <linux/mfd/core.h>
+ + #include <linux/mfd/tps65217.h>
+ + 
+ + /**
+ +  * tps65217_reg_read: Read a single tps65217 register.
+ +  *
+ +  * @tps: Device to read from.
+ +  * @reg: Register to read.
+ +  * @val: Contians the value
+ +  */
+ + int tps65217_reg_read(struct tps65217 *tps, unsigned int reg,
+ + 			unsigned int *val)
+ + {
+ + 	return regmap_read(tps->regmap, reg, val);
+ + }
+ + EXPORT_SYMBOL_GPL(tps65217_reg_read);
+ + 
+ + /**
+ +  * tps65217_reg_write: Write a single tps65217 register.
+ +  *
+ +  * @tps65217: Device to write to.
+ +  * @reg: Register to write to.
+ +  * @val: Value to write.
+ +  * @level: Password protected level
+ +  */
+ + int tps65217_reg_write(struct tps65217 *tps, unsigned int reg,
+ + 			unsigned int val, unsigned int level)
+ + {
+ + 	int ret;
+ + 	unsigned int xor_reg_val;
+ + 
+ + 	switch (level) {
+ + 	case TPS65217_PROTECT_NONE:
+ + 		return regmap_write(tps->regmap, reg, val);
+ + 	case TPS65217_PROTECT_L1:
+ + 		xor_reg_val = reg ^ TPS65217_PASSWORD_REGS_UNLOCK;
+ + 		ret = regmap_write(tps->regmap, TPS65217_REG_PASSWORD,
+ + 							xor_reg_val);
+ + 		if (ret < 0)
+ + 			return ret;
+ + 
+ + 		return regmap_write(tps->regmap, reg, val);
+ + 	case TPS65217_PROTECT_L2:
+ + 		xor_reg_val = reg ^ TPS65217_PASSWORD_REGS_UNLOCK;
+ + 		ret = regmap_write(tps->regmap, TPS65217_REG_PASSWORD,
+ + 							xor_reg_val);
+ + 		if (ret < 0)
+ + 			return ret;
+ + 		ret = regmap_write(tps->regmap, reg, val);
+ + 		if (ret < 0)
+ + 			return ret;
+ + 		ret = regmap_write(tps->regmap, TPS65217_REG_PASSWORD,
+ + 							xor_reg_val);
+ + 		if (ret < 0)
+ + 			return ret;
+ + 		return regmap_write(tps->regmap, reg, val);
+ + 	default:
+ + 		return -EINVAL;
+ + 	}
+ + }
+ + EXPORT_SYMBOL_GPL(tps65217_reg_write);
+ + 
+ + /**
+ +  * tps65217_update_bits: Modify bits w.r.t mask, val and level.
+ +  *
+ +  * @tps65217: Device to write to.
+ +  * @reg: Register to read-write to.
+ +  * @mask: Mask.
+ +  * @val: Value to write.
+ +  * @level: Password protected level
+ +  */
+ + int tps65217_update_bits(struct tps65217 *tps, unsigned int reg,
+ + 		unsigned int mask, unsigned int val, unsigned int level)
+ + {
+ + 	int ret;
+ + 	unsigned int data;
+ + 
+ + 	ret = tps65217_reg_read(tps, reg, &data);
+ + 	if (ret) {
+ + 		dev_err(tps->dev, "Read from reg 0x%x failed\n", reg);
+ + 		return ret;
+ + 	}
+ + 
+ + 	data &= ~mask;
+ + 	data |= val & mask;
+ + 
+ + 	ret = tps65217_reg_write(tps, reg, data, level);
+ + 	if (ret)
+ + 		dev_err(tps->dev, "Write for reg 0x%x failed\n", reg);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + int tps65217_set_bits(struct tps65217 *tps, unsigned int reg,
+ + 		unsigned int mask, unsigned int val, unsigned int level)
+ + {
+ + 	return tps65217_update_bits(tps, reg, mask, val, level);
+ + }
+ + EXPORT_SYMBOL_GPL(tps65217_set_bits);
+ + 
+ + int tps65217_clear_bits(struct tps65217 *tps, unsigned int reg,
+ + 		unsigned int mask, unsigned int level)
+ + {
+ + 	return tps65217_update_bits(tps, reg, mask, 0, level);
+ + }
+ + EXPORT_SYMBOL_GPL(tps65217_clear_bits);
+ + 
+ + static struct regmap_config tps65217_regmap_config = {
+ + 	.reg_bits = 8,
+ + 	.val_bits = 8,
+ + };
+ + 
+ + static int __devinit tps65217_probe(struct i2c_client *client,
+ + 				const struct i2c_device_id *ids)
+ + {
+ + 	struct tps65217 *tps;
+ + 	struct tps65217_board *pdata = client->dev.platform_data;
+ + 	int i, ret;
+ + 	unsigned int version;
+ + 
+ + 	tps = devm_kzalloc(&client->dev, sizeof(*tps), GFP_KERNEL);
+ + 	if (!tps)
+ + 		return -ENOMEM;
+ + 
+ + 	tps->pdata = pdata;
+ + 	tps->regmap = regmap_init_i2c(client, &tps65217_regmap_config);
+ + 	if (IS_ERR(tps->regmap)) {
+ + 		ret = PTR_ERR(tps->regmap);
+ + 		dev_err(tps->dev, "Failed to allocate register map: %d\n",
+ + 			ret);
+ + 		return ret;
+ + 	}
+ + 
+ + 	i2c_set_clientdata(client, tps);
+ + 	tps->dev = &client->dev;
+ + 
+ + 	ret = tps65217_reg_read(tps, TPS65217_REG_CHIPID, &version);
+ + 	if (ret < 0) {
+ + 		dev_err(tps->dev, "Failed to read revision"
+ + 					" register: %d\n", ret);
+ + 		goto err_regmap;
+ + 	}
+ + 
+ + 	/* Set the PMIC to shutdown on PWR_EN toggle */
+ + 	if (pdata->status_off) {
+ + 		ret = tps65217_set_bits(tps, TPS65217_REG_STATUS,
+ + 				TPS65217_STATUS_OFF, TPS65217_STATUS_OFF,
+ + 				TPS65217_PROTECT_NONE);
+ + 		if (ret) {
+ + 			dev_err(tps->dev, "Failed to set the status OFF\n");
+ + 			goto err_regmap;
+ + 		}
+ + 	}
+ + 
+ + 	dev_info(tps->dev, "TPS65217 ID %#x version 1.%d\n",
+ + 			(version & TPS65217_CHIPID_CHIP_MASK) >> 4,
+ + 			version & TPS65217_CHIPID_REV_MASK);
+ + 
+ + 	for (i = 0; i < TPS65217_NUM_REGULATOR; i++) {
+ + 		struct platform_device *pdev;
+ + 
+ + 		pdev = platform_device_alloc("tps65217-pmic", i);
+ + 		if (!pdev) {
+ + 			dev_err(tps->dev, "Cannot create regulator %d\n", i);
+ + 			continue;
+ + 		}
+ + 
+ + 		pdev->dev.parent = tps->dev;
+ + 		platform_device_add_data(pdev, &pdata->tps65217_init_data[i],
+ + 					sizeof(pdata->tps65217_init_data[i]));
+ + 		tps->regulator_pdev[i] = pdev;
+ + 
+ + 		platform_device_add(pdev);
+ + 	}
+ + 
+ + 	return 0;
+ + 
+ + err_regmap:
+ + 	regmap_exit(tps->regmap);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + static int __devexit tps65217_remove(struct i2c_client *client)
+ + {
+ + 	struct tps65217 *tps = i2c_get_clientdata(client);
+ + 	int i;
+ + 
+ + 	for (i = 0; i < TPS65217_NUM_REGULATOR; i++)
+ + 		platform_device_unregister(tps->regulator_pdev[i]);
+ + 
+ + 	regmap_exit(tps->regmap);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static const struct i2c_device_id tps65217_id_table[] = {
+ + 	{"tps65217", 0xF0},
+ + 	{/* end of list */}
+ + };
+ + MODULE_DEVICE_TABLE(i2c, tps65217_id_table);
+ + 
+ + static struct i2c_driver tps65217_driver = {
+ + 	.driver		= {
+ + 		.name	= "tps65217",
+ + 	},
+ + 	.id_table	= tps65217_id_table,
+ + 	.probe		= tps65217_probe,
+ + 	.remove		= __devexit_p(tps65217_remove),
+ + };
+ + 
+ + static int __init tps65217_init(void)
+ + {
+ + 	return i2c_add_driver(&tps65217_driver);
+ + }
+ + subsys_initcall(tps65217_init);
+ + 
+ + static void __exit tps65217_exit(void)
+ + {
+ + 	i2c_del_driver(&tps65217_driver);
+ + }
+ + module_exit(tps65217_exit);
+ + 
+ + MODULE_AUTHOR("AnilKumar Ch <anilkumar@ti.com>");
+ + MODULE_DESCRIPTION("TPS65217 chip family multi-function driver");
+ + MODULE_LICENSE("GPL v2");
+ diff -crN linux-3.2.1_o/drivers/misc/eeprom/at24.c linux-3.2.1/drivers/misc/eeprom/at24.c
+ *** linux-3.2.1_o/drivers/misc/eeprom/at24.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/misc/eeprom/at24.c	2014-11-25 13:19:15.628014097 +0900
+ ***************
+ *** 662,667 ****
+ --- 662,671 ----
+   	int i;
+   
+   	at24 = i2c_get_clientdata(client);
+ + #ifdef CONFIG_MACH_CKB_3352
+ + 	if(at24->chip.unload)
+ + 		at24->chip.unload();
+ + #endif
+   	sysfs_remove_bin_file(&client->dev.kobj, &at24->bin);
+   
+   	for (i = 1; i < at24->num_addresses; i++)
+ diff -crN linux-3.2.1_o/drivers/mmc/card/block.c linux-3.2.1/drivers/mmc/card/block.c
+ *** linux-3.2.1_o/drivers/mmc/card/block.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/mmc/card/block.c	2014-11-25 13:19:15.636046488 +0900
+ ***************
+ *** 119,124 ****
+ --- 119,125 ----
+   	MMC_BLK_ABORT,
+   	MMC_BLK_DATA_ERR,
+   	MMC_BLK_ECC_ERR,
+ + 	MMC_BLK_NOMEDIUM,
+   };
+   
+   module_param(perdev_minors, int, 0444);
+ ***************
+ *** 565,570 ****
+ --- 566,572 ----
+   	return err;
+   }
+   
+ + #define ERR_NOMEDIUM	3
+   #define ERR_RETRY	2
+   #define ERR_ABORT	1
+   #define ERR_CONTINUE	0
+ ***************
+ *** 632,637 ****
+ --- 634,642 ----
+   	u32 status, stop_status = 0;
+   	int err, retry;
+   
+ + 	if (mmc_card_removed(card))
+ + 		return ERR_NOMEDIUM;
+ + 
+   	/*
+   	 * Try to get card status which indicates both the card state
+   	 * and why there was no response.  If the first attempt fails,
+ ***************
+ *** 648,655 ****
+   	}
+   
+   	/* We couldn't get a response from the card.  Give up. */
+ ! 	if (err)
+   		return ERR_ABORT;
+   
+   	/* Flag ECC errors */
+   	if ((status & R1_CARD_ECC_FAILED) ||
+ --- 653,664 ----
+   	}
+   
+   	/* We couldn't get a response from the card.  Give up. */
+ ! 	if (err) {
+ ! 		/* Check if the card is removed */
+ ! 		if (mmc_detect_card_removed(card->host))
+ ! 			return ERR_NOMEDIUM;
+   		return ERR_ABORT;
+ + 	}
+   
+   	/* Flag ECC errors */
+   	if ((status & R1_CARD_ECC_FAILED) ||
+ ***************
+ *** 922,927 ****
+ --- 931,938 ----
+   			return MMC_BLK_RETRY;
+   		case ERR_ABORT:
+   			return MMC_BLK_ABORT;
+ + 		case ERR_NOMEDIUM:
+ + 			return MMC_BLK_NOMEDIUM;
+   		case ERR_CONTINUE:
+   			break;
+   		}
+ ***************
+ *** 1255,1260 ****
+ --- 1266,1273 ----
+   			if (!ret)
+   				goto start_new_req;
+   			break;
+ + 		case MMC_BLK_NOMEDIUM:
+ + 			goto cmd_abort;
+   		}
+   
+   		if (ret) {
+ ***************
+ *** 1271,1276 ****
+ --- 1284,1291 ----
+   
+    cmd_abort:
+   	spin_lock_irq(&md->lock);
+ + 	if (mmc_card_removed(card))
+ + 		req->cmd_flags |= REQ_QUIET;
+   	while (ret)
+   		ret = __blk_end_request(req, -EIO, blk_rq_cur_bytes(req));
+   	spin_unlock_irq(&md->lock);
+ ***************
+ *** 1677,1683 ****
+   }
+   
+   #ifdef CONFIG_PM
+ ! static int mmc_blk_suspend(struct mmc_card *card, pm_message_t state)
+   {
+   	struct mmc_blk_data *part_md;
+   	struct mmc_blk_data *md = mmc_get_drvdata(card);
+ --- 1692,1698 ----
+   }
+   
+   #ifdef CONFIG_PM
+ ! static int mmc_blk_suspend(struct mmc_card *card)
+   {
+   	struct mmc_blk_data *part_md;
+   	struct mmc_blk_data *md = mmc_get_drvdata(card);
+ diff -crN linux-3.2.1_o/drivers/mmc/card/queue.c linux-3.2.1/drivers/mmc/card/queue.c
+ *** linux-3.2.1_o/drivers/mmc/card/queue.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/mmc/card/queue.c	2014-11-25 13:19:15.664016686 +0900
+ ***************
+ *** 29,34 ****
+ --- 29,36 ----
+    */
+   static int mmc_prep_request(struct request_queue *q, struct request *req)
+   {
+ + 	struct mmc_queue *mq = q->queuedata;
+ + 
+   	/*
+   	 * We only like normal block requests and discards.
+   	 */
+ ***************
+ *** 37,42 ****
+ --- 39,47 ----
+   		return BLKPREP_KILL;
+   	}
+   
+ + 	if (mq && mmc_card_removed(mq->card))
+ + 		return BLKPREP_KILL;
+ + 
+   	req->cmd_flags |= REQ_DONTPREP;
+   
+   	return BLKPREP_OK;
+ diff -crN linux-3.2.1_o/drivers/mmc/core/bus.c linux-3.2.1/drivers/mmc/core/bus.c
+ *** linux-3.2.1_o/drivers/mmc/core/bus.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/mmc/core/bus.c	2014-11-25 13:19:15.667107455 +0900
+ ***************
+ *** 122,135 ****
+   	return 0;
+   }
+   
+ ! static int mmc_bus_suspend(struct device *dev, pm_message_t state)
+   {
+   	struct mmc_driver *drv = to_mmc_driver(dev->driver);
+   	struct mmc_card *card = mmc_dev_to_card(dev);
+   	int ret = 0;
+   
+   	if (dev->driver && drv->suspend)
+ ! 		ret = drv->suspend(card, state);
+   	return ret;
+   }
+   
+ --- 122,135 ----
+   	return 0;
+   }
+   
+ ! static int mmc_bus_suspend(struct device *dev)
+   {
+   	struct mmc_driver *drv = to_mmc_driver(dev->driver);
+   	struct mmc_card *card = mmc_dev_to_card(dev);
+   	int ret = 0;
+   
+   	if (dev->driver && drv->suspend)
+ ! 		ret = drv->suspend(card);
+   	return ret;
+   }
+   
+ ***************
+ *** 165,184 ****
+   	return pm_runtime_suspend(dev);
+   }
+   
+   static const struct dev_pm_ops mmc_bus_pm_ops = {
+   	.runtime_suspend	= mmc_runtime_suspend,
+   	.runtime_resume		= mmc_runtime_resume,
+   	.runtime_idle		= mmc_runtime_idle,
+   };
+   
+ - #define MMC_PM_OPS_PTR	(&mmc_bus_pm_ops)
+ - 
+ - #else /* !CONFIG_PM_RUNTIME */
+ - 
+ - #define MMC_PM_OPS_PTR	NULL
+ - 
+ - #endif /* !CONFIG_PM_RUNTIME */
+ - 
+   static struct bus_type mmc_bus_type = {
+   	.name		= "mmc",
+   	.dev_attrs	= mmc_dev_attrs,
+ --- 165,184 ----
+   	return pm_runtime_suspend(dev);
+   }
+   
+ + #else /* !CONFIG_PM_RUNTIME */
+ + #define mmc_runtime_suspend	NULL
+ + #define mmc_runtime_resume	NULL
+ + #define mmc_runtime_idle	NULL
+ + #endif /* !CONFIG_PM_RUNTIME */
+ + 
+   static const struct dev_pm_ops mmc_bus_pm_ops = {
+   	.runtime_suspend	= mmc_runtime_suspend,
+   	.runtime_resume		= mmc_runtime_resume,
+   	.runtime_idle		= mmc_runtime_idle,
+ + 	.suspend		= mmc_bus_suspend,
+ + 	.resume			= mmc_bus_resume,
+   };
+   
+   static struct bus_type mmc_bus_type = {
+   	.name		= "mmc",
+   	.dev_attrs	= mmc_dev_attrs,
+ ***************
+ *** 186,194 ****
+   	.uevent		= mmc_bus_uevent,
+   	.probe		= mmc_bus_probe,
+   	.remove		= mmc_bus_remove,
+ ! 	.suspend	= mmc_bus_suspend,
+ ! 	.resume		= mmc_bus_resume,
+ ! 	.pm		= MMC_PM_OPS_PTR,
+   };
+   
+   int mmc_register_bus(void)
+ --- 186,192 ----
+   	.uevent		= mmc_bus_uevent,
+   	.probe		= mmc_bus_probe,
+   	.remove		= mmc_bus_remove,
+ ! 	.pm		= &mmc_bus_pm_ops,
+   };
+   
+   int mmc_register_bus(void)
+ diff -crN linux-3.2.1_o/drivers/mmc/core/core.c linux-3.2.1/drivers/mmc/core/core.c
+ *** linux-3.2.1_o/drivers/mmc/core/core.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/mmc/core/core.c	2014-11-25 13:19:15.672015413 +0900
+ ***************
+ *** 140,146 ****
+   			cmd->retries = 0;
+   	}
+   
+ ! 	if (err && cmd->retries) {
+   		/*
+   		 * Request starter must handle retries - see
+   		 * mmc_wait_for_req_done().
+ --- 140,146 ----
+   			cmd->retries = 0;
+   	}
+   
+ ! 	if (err && cmd->retries && !mmc_card_removed(host->card)) {
+   		/*
+   		 * Request starter must handle retries - see
+   		 * mmc_wait_for_req_done().
+ ***************
+ *** 208,214 ****
+   	}
+   
+   	WARN_ON(!host->claimed);
+ - 
+   	mrq->cmd->error = 0;
+   	mrq->cmd->mrq = mrq;
+   	if (mrq->data) {
+ --- 208,213 ----
+ ***************
+ *** 243,253 ****
+   	complete(&mrq->completion);
+   }
+   
+ ! static void __mmc_start_req(struct mmc_host *host, struct mmc_request *mrq)
+   {
+   	init_completion(&mrq->completion);
+   	mrq->done = mmc_wait_done;
+   	mmc_start_request(host, mrq);
+   }
+   
+   static void mmc_wait_for_req_done(struct mmc_host *host,
+ --- 242,258 ----
+   	complete(&mrq->completion);
+   }
+   
+ ! static int __mmc_start_req(struct mmc_host *host, struct mmc_request *mrq)
+   {
+   	init_completion(&mrq->completion);
+   	mrq->done = mmc_wait_done;
+ + 	if (mmc_card_removed(host->card)) {
+ + 		mrq->cmd->error = -ENOMEDIUM;
+ + 		complete(&mrq->completion);
+ + 		return -ENOMEDIUM;
+ + 	}
+   	mmc_start_request(host, mrq);
+ + 	return 0;
+   }
+   
+   static void mmc_wait_for_req_done(struct mmc_host *host,
+ ***************
+ *** 259,265 ****
+   		wait_for_completion(&mrq->completion);
+   
+   		cmd = mrq->cmd;
+ ! 		if (!cmd->error || !cmd->retries)
+   			break;
+   
+   		pr_debug("%s: req failed (CMD%u): %d, retrying...\n",
+ --- 264,271 ----
+   		wait_for_completion(&mrq->completion);
+   
+   		cmd = mrq->cmd;
+ ! 		if (!cmd->error || !cmd->retries ||
+ ! 		    mmc_card_removed(host->card))
+   			break;
+   
+   		pr_debug("%s: req failed (CMD%u): %d, retrying...\n",
+ ***************
+ *** 324,329 ****
+ --- 330,336 ----
+   				    struct mmc_async_req *areq, int *error)
+   {
+   	int err = 0;
+ + 	int start_err = 0;
+   	struct mmc_async_req *data = host->areq;
+   
+   	/* Prepare a new request */
+ ***************
+ *** 333,362 ****
+   	if (host->areq) {
+   		mmc_wait_for_req_done(host, host->areq->mrq);
+   		err = host->areq->err_check(host->card, host->areq);
+ - 		if (err) {
+ - 			/* post process the completed failed request */
+ - 			mmc_post_req(host, host->areq->mrq, 0);
+ - 			if (areq)
+ - 				/*
+ - 				 * Cancel the new prepared request, because
+ - 				 * it can't run until the failed
+ - 				 * request has been properly handled.
+ - 				 */
+ - 				mmc_post_req(host, areq->mrq, -EINVAL);
+ - 
+ - 			host->areq = NULL;
+ - 			goto out;
+ - 		}
+   	}
+   
+ ! 	if (areq)
+ ! 		__mmc_start_req(host, areq->mrq);
+   
+   	if (host->areq)
+   		mmc_post_req(host, host->areq->mrq, 0);
+   
+ ! 	host->areq = areq;
+ !  out:
+   	if (error)
+   		*error = err;
+   	return data;
+ --- 340,362 ----
+   	if (host->areq) {
+   		mmc_wait_for_req_done(host, host->areq->mrq);
+   		err = host->areq->err_check(host->card, host->areq);
+   	}
+   
+ ! 	if (!err && areq)
+ ! 		start_err = __mmc_start_req(host, areq->mrq);
+   
+   	if (host->areq)
+   		mmc_post_req(host, host->areq->mrq, 0);
+   
+ ! 	 /* Cancel a prepared request if it was not started. */
+ ! 	if ((err || start_err) && areq)
+ ! 			mmc_post_req(host, areq->mrq, -EINVAL);
+ ! 
+ ! 	if (err)
+ ! 		host->areq = NULL;
+ ! 	else
+ ! 		host->areq = areq;
+ ! 
+   	if (error)
+   		*error = err;
+   	return data;
+ ***************
+ *** 834,839 ****
+ --- 834,841 ----
+   
+   EXPORT_SYMBOL(mmc_release_host);
+   
+ + volatile struct mmc_host *vagi;
+ + volatile struct mmc_ios *anu;
+   /*
+    * Internal function that does the actual ios call to the host driver,
+    * optionally printing some debug output.
+ ***************
+ *** 841,847 ****
+   static inline void mmc_set_ios(struct mmc_host *host)
+   {
+   	struct mmc_ios *ios = &host->ios;
+ ! 
+   	pr_debug("%s: clock %uHz busmode %u powermode %u cs %u Vdd %u "
+   		"width %u timing %u\n",
+   		 mmc_hostname(host), ios->clock, ios->bus_mode,
+ --- 843,850 ----
+   static inline void mmc_set_ios(struct mmc_host *host)
+   {
+   	struct mmc_ios *ios = &host->ios;
+ ! 	vagi = host;
+ ! 	anu = ios;
+   	pr_debug("%s: clock %uHz busmode %u powermode %u cs %u Vdd %u "
+   		"width %u timing %u\n",
+   		 mmc_hostname(host), ios->clock, ios->bus_mode,
+ ***************
+ *** 1456,1462 ****
+   	WARN_ON(host->removed);
+   	spin_unlock_irqrestore(&host->lock, flags);
+   #endif
+ ! 
+   	mmc_schedule_delayed_work(&host->detect, delay);
+   }
+   
+ --- 1459,1465 ----
+   	WARN_ON(host->removed);
+   	spin_unlock_irqrestore(&host->lock, flags);
+   #endif
+ ! 	host->detect_change = 1;
+   	mmc_schedule_delayed_work(&host->detect, delay);
+   }
+   
+ ***************
+ *** 2049,2054 ****
+ --- 2052,2112 ----
+   	return -EIO;
+   }
+   
+ + int _mmc_detect_card_removed(struct mmc_host *host)
+ + {
+ + 	int ret;
+ + 
+ + 	if ((host->caps & MMC_CAP_NONREMOVABLE) || !host->bus_ops->alive)
+ + 		return 0;
+ + 
+ + 	if (!host->card || mmc_card_removed(host->card))
+ + 		return 1;
+ + 
+ + 	ret = host->bus_ops->alive(host);
+ + 	if (ret) {
+ + 		mmc_card_set_removed(host->card);
+ + 		pr_debug("%s: card remove detected\n", mmc_hostname(host));
+ + 	}
+ + 
+ + 	return ret;
+ + }
+ + 
+ + int mmc_detect_card_removed(struct mmc_host *host)
+ + {
+ + 	struct mmc_card *card = host->card;
+ + 	int ret;
+ + 
+ + 	WARN_ON(!host->claimed);
+ + 
+ + 	if (!card)
+ + 		return 1;
+ + 
+ + 	ret = mmc_card_removed(card);
+ + 	/*
+ + 	 * The card will be considered unchanged unless we have been asked to
+ + 	 * detect a change or host requires polling to provide card detection.
+ + 	 */
+ + 	if (!host->detect_change && !(host->caps & MMC_CAP_NEEDS_POLL) &&
+ + 	    !(host->caps2 & MMC_CAP2_DETECT_ON_ERR))
+ + 		return ret;
+ + 
+ + 	host->detect_change = 0;
+ + 	if (!ret) {
+ + 		ret = _mmc_detect_card_removed(host);
+ + 		if (ret && (host->caps2 & MMC_CAP2_DETECT_ON_ERR)) {
+ + 			/*
+ + 			 * Schedule a detect work as soon as possible to let a
+ + 			 * rescan handle the card removal.
+ + 			 */
+ + 			cancel_delayed_work(&host->detect);
+ + 			mmc_detect_change(host, 0);
+ + 		}
+ + 	}
+ + 
+ + 	return ret;
+ + }
+ + EXPORT_SYMBOL(mmc_detect_card_removed);
+ + 
+   void mmc_rescan(struct work_struct *work)
+   {
+   	static const unsigned freqs[] = { 400000, 300000, 200000, 100000 };
+ ***************
+ *** 2069,2074 ****
+ --- 2127,2134 ----
+   	    && !(host->caps & MMC_CAP_NONREMOVABLE))
+   		host->bus_ops->detect(host);
+   
+ + 	host->detect_change = 0;
+ + 
+   	/*
+   	 * Let mmc_bus_put() free the bus/bus_ops if we've found that
+   	 * the card is no longer present.
+ diff -crN linux-3.2.1_o/drivers/mmc/core/core.h linux-3.2.1/drivers/mmc/core/core.h
+ *** linux-3.2.1_o/drivers/mmc/core/core.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/mmc/core/core.h	2014-11-25 13:19:15.680037308 +0900
+ ***************
+ *** 24,29 ****
+ --- 24,30 ----
+   	int (*resume)(struct mmc_host *);
+   	int (*power_save)(struct mmc_host *);
+   	int (*power_restore)(struct mmc_host *);
+ + 	int (*alive)(struct mmc_host *);
+   };
+   
+   void mmc_attach_bus(struct mmc_host *host, const struct mmc_bus_ops *ops);
+ ***************
+ *** 59,64 ****
+ --- 60,67 ----
+   void mmc_start_host(struct mmc_host *host);
+   void mmc_stop_host(struct mmc_host *host);
+   
+ + int _mmc_detect_card_removed(struct mmc_host *host);
+ + 
+   int mmc_attach_mmc(struct mmc_host *host);
+   int mmc_attach_sd(struct mmc_host *host);
+   int mmc_attach_sdio(struct mmc_host *host);
+ diff -crN linux-3.2.1_o/drivers/mmc/core/mmc.c linux-3.2.1/drivers/mmc/core/mmc.c
+ *** linux-3.2.1_o/drivers/mmc/core/mmc.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/mmc/core/mmc.c	2014-11-25 13:19:15.687538140 +0900
+ ***************
+ *** 1105,1110 ****
+ --- 1105,1118 ----
+   }
+   
+   /*
+ +  * Card detection - card is alive.
+ +  */
+ + static int mmc_alive(struct mmc_host *host)
+ + {
+ + 	return mmc_send_status(host->card, NULL);
+ + }
+ + 
+ + /*
+    * Card detection callback from host.
+    */
+   static void mmc_detect(struct mmc_host *host)
+ ***************
+ *** 1119,1125 ****
+   	/*
+   	 * Just check if our card has been removed.
+   	 */
+ ! 	err = mmc_send_status(host->card, NULL);
+   
+   	mmc_release_host(host);
+   
+ --- 1127,1133 ----
+   	/*
+   	 * Just check if our card has been removed.
+   	 */
+ ! 	err = _mmc_detect_card_removed(host);
+   
+   	mmc_release_host(host);
+   
+ ***************
+ *** 1224,1229 ****
+ --- 1232,1238 ----
+   	.suspend = NULL,
+   	.resume = NULL,
+   	.power_restore = mmc_power_restore,
+ + 	.alive = mmc_alive,
+   };
+   
+   static const struct mmc_bus_ops mmc_ops_unsafe = {
+ ***************
+ *** 1234,1239 ****
+ --- 1243,1249 ----
+   	.suspend = mmc_suspend,
+   	.resume = mmc_resume,
+   	.power_restore = mmc_power_restore,
+ + 	.alive = mmc_alive,
+   };
+   
+   static void mmc_attach_bus_ops(struct mmc_host *host)
+ diff -crN linux-3.2.1_o/drivers/mmc/core/sd.c linux-3.2.1/drivers/mmc/core/sd.c
+ *** linux-3.2.1_o/drivers/mmc/core/sd.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/mmc/core/sd.c	2014-11-25 13:19:15.695628530 +0900
+ ***************
+ *** 1019,1024 ****
+ --- 1019,1032 ----
+   }
+   
+   /*
+ +  * Card detection - card is alive.
+ +  */
+ + static int mmc_sd_alive(struct mmc_host *host)
+ + {
+ + 	return mmc_send_status(host->card, NULL);
+ + }
+ + 
+ + /*
+    * Card detection callback from host.
+    */
+   static void mmc_sd_detect(struct mmc_host *host)
+ ***************
+ *** 1033,1039 ****
+   	/*
+   	 * Just check if our card has been removed.
+   	 */
+ ! 	err = mmc_send_status(host->card, NULL);
+   
+   	mmc_release_host(host);
+   
+ --- 1041,1047 ----
+   	/*
+   	 * Just check if our card has been removed.
+   	 */
+ ! 	err = _mmc_detect_card_removed(host);
+   
+   	mmc_release_host(host);
+   
+ ***************
+ *** 1102,1107 ****
+ --- 1110,1116 ----
+   	.suspend = NULL,
+   	.resume = NULL,
+   	.power_restore = mmc_sd_power_restore,
+ + 	.alive = mmc_sd_alive,
+   };
+   
+   static const struct mmc_bus_ops mmc_sd_ops_unsafe = {
+ ***************
+ *** 1110,1115 ****
+ --- 1119,1125 ----
+   	.suspend = mmc_sd_suspend,
+   	.resume = mmc_sd_resume,
+   	.power_restore = mmc_sd_power_restore,
+ + 	.alive = mmc_sd_alive,
+   };
+   
+   static void mmc_sd_attach_bus_ops(struct mmc_host *host)
+ diff -crN linux-3.2.1_o/drivers/mmc/core/sdio.c linux-3.2.1/drivers/mmc/core/sdio.c
+ *** linux-3.2.1_o/drivers/mmc/core/sdio.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/mmc/core/sdio.c	2014-11-25 13:19:15.703596240 +0900
+ ***************
+ *** 550,555 ****
+ --- 550,563 ----
+   }
+   
+   /*
+ +  * Card detection - card is alive.
+ +  */
+ + static int mmc_sdio_alive(struct mmc_host *host)
+ + {
+ + 	return mmc_select_card(host->card);
+ + }
+ + 
+ + /*
+    * Card detection callback from host.
+    */
+   static void mmc_sdio_detect(struct mmc_host *host)
+ ***************
+ *** 571,577 ****
+   	/*
+   	 * Just check if our card has been removed.
+   	 */
+ ! 	err = mmc_select_card(host->card);
+   
+   	mmc_release_host(host);
+   
+ --- 579,585 ----
+   	/*
+   	 * Just check if our card has been removed.
+   	 */
+ ! 	err = _mmc_detect_card_removed(host);
+   
+   	mmc_release_host(host);
+   
+ ***************
+ *** 749,754 ****
+ --- 757,763 ----
+   	.suspend = mmc_sdio_suspend,
+   	.resume = mmc_sdio_resume,
+   	.power_restore = mmc_sdio_power_restore,
+ + 	.alive = mmc_sdio_alive,
+   };
+   
+   
+ diff -crN linux-3.2.1_o/drivers/mmc/host/Kconfig linux-3.2.1/drivers/mmc/host/Kconfig
+ *** linux-3.2.1_o/drivers/mmc/host/Kconfig	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/mmc/host/Kconfig	2014-11-25 13:19:15.711620790 +0900
+ ***************
+ *** 231,237 ****
+   
+   config MMC_OMAP
+   	tristate "TI OMAP Multimedia Card Interface support"
+ ! 	depends on ARCH_OMAP
+   	select TPS65010 if MACH_OMAP_H2
+   	help
+   	  This selects the TI OMAP Multimedia card Interface.
+ --- 231,237 ----
+   
+   config MMC_OMAP
+   	tristate "TI OMAP Multimedia Card Interface support"
+ ! 	depends on ARCH_OMAP || ARCH_CKB
+   	select TPS65010 if MACH_OMAP_H2
+   	help
+   	  This selects the TI OMAP Multimedia card Interface.
+ ***************
+ *** 242,248 ****
+   
+   config MMC_OMAP_HS
+   	tristate "TI OMAP High Speed Multimedia Card Interface support"
+ ! 	depends on SOC_OMAP2430 || ARCH_OMAP3 || ARCH_OMAP4
+   	help
+   	  This selects the TI OMAP High Speed Multimedia card Interface.
+   	  If you have an OMAP2430 or OMAP3 board or OMAP4 board with a
+ --- 242,248 ----
+   
+   config MMC_OMAP_HS
+   	tristate "TI OMAP High Speed Multimedia Card Interface support"
+ ! 	depends on SOC_OMAP2430 || ARCH_OMAP3 || ARCH_OMAP4 || ARCH_CKB
+   	help
+   	  This selects the TI OMAP High Speed Multimedia card Interface.
+   	  If you have an OMAP2430 or OMAP3 board or OMAP4 board with a
+ diff -crN linux-3.2.1_o/drivers/mmc/host/omap_hsmmc.c linux-3.2.1/drivers/mmc/host/omap_hsmmc.c
+ *** linux-3.2.1_o/drivers/mmc/host/omap_hsmmc.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/mmc/host/omap_hsmmc.c	2014-11-25 13:19:15.719954089 +0900
+ ***************
+ *** 59,64 ****
+ --- 59,65 ----
+   #define OMAP_HSMMC_IE		0x0134
+   #define OMAP_HSMMC_ISE		0x0138
+   #define OMAP_HSMMC_CAPA		0x0140
+ + #define OMAP_HSMMC_PSTATE	0x0124
+   
+   #define VS18			(1 << 26)
+   #define VS30			(1 << 25)
+ ***************
+ *** 78,84 ****
+   #define CLKD_SHIFT		6
+   #define DTO_MASK		0x000F0000
+   #define DTO_SHIFT		16
+ ! #define INT_EN_MASK		0x307F0033
+   #define BWR_ENABLE		(1 << 4)
+   #define BRR_ENABLE		(1 << 5)
+   #define DTO_ENABLE		(1 << 20)
+ --- 79,85 ----
+   #define CLKD_SHIFT		6
+   #define DTO_MASK		0x000F0000
+   #define DTO_SHIFT		16
+ ! #define INT_EN_MASK		0x307F00f3
+   #define BWR_ENABLE		(1 << 4)
+   #define BRR_ENABLE		(1 << 5)
+   #define DTO_ENABLE		(1 << 20)
+ ***************
+ *** 89,94 ****
+ --- 90,100 ----
+   #define MSBS			(1 << 5)
+   #define BCE			(1 << 1)
+   #define FOUR_BIT		(1 << 1)
+ + #define HSPE			(1 << 2)
+ + #define DVAL_MASK		(3 << 9)
+ + #define DVAL_MAX		(3 << 9)	/* 8.4 ms debounce period */
+ + #define WPP_MASK		(1 << 8)
+ + #define WPP_ACT_LOW		(1 << 8)	/* WPP is Active Low */
+   #define DW8			(1 << 5)
+   #define CC			0x1
+   #define TC			0x02
+ ***************
+ *** 106,111 ****
+ --- 112,125 ----
+   #define SRD			(1 << 26)
+   #define SOFTRESET		(1 << 1)
+   #define RESETDONE		(1 << 0)
+ + #define CINS			(1 << 6)
+ + #define PSTATE_CINS_MASK	BIT(16)
+ + #define PSTATE_CINS_SHIFT	16
+ + #define PSTATE_WP_MASK		BIT(19)
+ + #define PSTATE_WP_SHIFT		19
+ + #define IE_CINS			0x00000040
+ + #define IE_CINS_SHIFT		6
+ + #define PSTATE_CINS     (1 << 16)
+   
+   /*
+    * FIXME: Most likely all the data using these _DEVID defines should come
+ ***************
+ *** 120,126 ****
+   
+   #define MMC_AUTOSUSPEND_DELAY	100
+   #define MMC_TIMEOUT_MS		20
+ - #define OMAP_MMC_MASTER_CLOCK	96000000
+   #define OMAP_MMC_MIN_CLOCK	400000
+   #define OMAP_MMC_MAX_CLOCK	52000000
+   #define DRIVER_NAME		"omap_hsmmc"
+ --- 134,139 ----
+ ***************
+ *** 193,198 ****
+ --- 206,213 ----
+   	struct	omap_mmc_platform_data	*pdata;
+   };
+   
+ + static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id);
+ + 
+   static int omap_hsmmc_card_detect(struct device *dev, int slot)
+   {
+   	struct omap_mmc_platform_data *mmc = dev->platform_data;
+ ***************
+ *** 224,229 ****
+ --- 239,245 ----
+   	struct omap_mmc_platform_data *mmc = dev->platform_data;
+   
+   	disable_irq(mmc->slots[0].card_detect_irq);
+ + 
+   	return 0;
+   }
+   
+ ***************
+ *** 232,237 ****
+ --- 248,254 ----
+   	struct omap_mmc_platform_data *mmc = dev->platform_data;
+   
+   	enable_irq(mmc->slots[0].card_detect_irq);
+ + 
+   	return 0;
+   }
+   
+ ***************
+ *** 592,609 ****
+   
+   static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
+   {
+   	OMAP_HSMMC_WRITE(host->base, ISE, 0);
+   	OMAP_HSMMC_WRITE(host->base, IE, 0);
+   	OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
+   }
+   
+   /* Calculate divisor for the given clock frequency */
+ ! static u16 calc_divisor(struct mmc_ios *ios)
+   {
+   	u16 dsor = 0;
+   
+   	if (ios->clock) {
+ ! 		dsor = DIV_ROUND_UP(OMAP_MMC_MASTER_CLOCK, ios->clock);
+   		if (dsor > 250)
+   			dsor = 250;
+   	}
+ --- 609,628 ----
+   
+   static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
+   {
+ + 
+   	OMAP_HSMMC_WRITE(host->base, ISE, 0);
+   	OMAP_HSMMC_WRITE(host->base, IE, 0);
+   	OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
+ + 
+   }
+   
+   /* Calculate divisor for the given clock frequency */
+ ! static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
+   {
+   	u16 dsor = 0;
+   
+   	if (ios->clock) {
+ ! 		dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
+   		if (dsor > 250)
+   			dsor = 250;
+   	}
+ ***************
+ *** 616,629 ****
+   	struct mmc_ios *ios = &host->mmc->ios;
+   	unsigned long regval;
+   	unsigned long timeout;
+   
+   	dev_dbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
+   
+   	omap_hsmmc_stop_clock(host);
+   
+   	regval = OMAP_HSMMC_READ(host->base, SYSCTL);
+   	regval = regval & ~(CLKD_MASK | DTO_MASK);
+ ! 	regval = regval | (calc_divisor(ios) << 6) | (DTO << 16);
+   	OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
+   	OMAP_HSMMC_WRITE(host->base, SYSCTL,
+   		OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
+ --- 635,660 ----
+   	struct mmc_ios *ios = &host->mmc->ios;
+   	unsigned long regval;
+   	unsigned long timeout;
+ + 	unsigned long clkdiv;
+ + //printk("************setting clock to %dHz\n", ios->clock);
+   
+   	dev_dbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
+   
+ + 	clkdiv = calc_divisor(host, ios);
+ + 	regval = OMAP_HSMMC_READ(host->base, HCTL);
+ + 	/* Enable HSPE bit for high speed card */
+ + 	if (ios->clock && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
+ + 		regval |= HSPE;
+ + 	else
+ + 		regval &= ~HSPE;
+ + 
+ + 	OMAP_HSMMC_WRITE(host->base, HCTL, regval);
+ + 
+   	omap_hsmmc_stop_clock(host);
+   
+   	regval = OMAP_HSMMC_READ(host->base, SYSCTL);
+   	regval = regval & ~(CLKD_MASK | DTO_MASK);
+ ! 	regval = regval | (clkdiv << 6) | (DTO << 16);
+   	OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
+   	OMAP_HSMMC_WRITE(host->base, SYSCTL,
+   		OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
+ ***************
+ *** 862,868 ****
+   	struct mmc_data *data)
+   {
+   	int cmdreg = 0, resptype = 0, cmdtype = 0;
+ - 
+   	dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
+   		mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
+   	host->cmd = cmd;
+ --- 893,898 ----
+ ***************
+ *** 941,954 ****
+   {
+   	if (!data) {
+   		struct mmc_request *mrq = host->mrq;
+ - 
+   		/* TC before CC from CMD6 - don't know why, but it happens */
+   		if (host->cmd && host->cmd->opcode == 6 &&
+   		    host->response_busy) {
+   			host->response_busy = 0;
+   			return;
+   		}
+ - 
+   		omap_hsmmc_request_done(host, mrq);
+   		return;
+   	}
+ --- 971,982 ----
+ ***************
+ *** 956,964 ****
+ --- 984,997 ----
+   	host->data = NULL;
+   
+   	if (!data->error)
+ + 	{
+   		data->bytes_xfered += data->blocks * (data->blksz);
+ + 	}
+   	else
+ + 	{
+ + 		printk("data->error, trans bytes=0\n");
+   		data->bytes_xfered = 0;
+ + 	}
+   
+   	if (!data->stop) {
+   		omap_hsmmc_request_done(host, data->mrq);
+ ***************
+ *** 1088,1094 ****
+   			__func__);
+   }
+   
+ ! static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
+   {
+   	struct mmc_data *data;
+   	int end_cmd = 0, end_trans = 0;
+ --- 1121,1127 ----
+   			__func__);
+   }
+   
+ ! static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status, int irq)
+   {
+   	struct mmc_data *data;
+   	int end_cmd = 0, end_trans = 0;
+ ***************
+ *** 1155,1163 ****
+ --- 1188,1200 ----
+   	OMAP_HSMMC_WRITE(host->base, STAT, status);
+   
+   	if (end_cmd || ((status & CC) && host->cmd))
+ + 	{
+   		omap_hsmmc_cmd_done(host, host->cmd);
+ + 	}
+   	if ((end_trans || (status & TC)) && host->mrq)
+ + 	{
+   		omap_hsmmc_xfer_done(host, data);
+ + 	}
+   }
+   
+   /*
+ ***************
+ *** 1167,1180 ****
+   {
+   	struct omap_hsmmc_host *host = dev_id;
+   	int status;
+ ! 
+   	status = OMAP_HSMMC_READ(host->base, STAT);
+   	do {
+ ! 		omap_hsmmc_do_irq(host, status);
+   		/* Flush posted write */
+   		status = OMAP_HSMMC_READ(host->base, STAT);
+   	} while (status & INT_EN_MASK);
+ - 
+   	return IRQ_HANDLED;
+   }
+   
+ --- 1204,1225 ----
+   {
+   	struct omap_hsmmc_host *host = dev_id;
+   	int status;
+ ! 	static int count = 0;
+   	status = OMAP_HSMMC_READ(host->base, STAT);
+ + 	if(irq == 29)
+ + 	{
+ + 		if (host->cmd == NULL && host->data == NULL) {
+ + 			OMAP_HSMMC_WRITE(host->base, STAT, status);
+ + 			return IRQ_NONE;
+ + 		}
+ + 	}
+   	do {
+ ! 		if(irq == 39)
+ ! 			printk("doing_irq 0x%x 0x%x\n", status, host->base); 
+ ! 		omap_hsmmc_do_irq(host, status, irq);
+   		/* Flush posted write */
+   		status = OMAP_HSMMC_READ(host->base, STAT);
+   	} while (status & INT_EN_MASK);
+   	return IRQ_HANDLED;
+   }
+   
+ ***************
+ *** 1338,1360 ****
+   				       struct scatterlist *sgl)
+   {
+   	int blksz, nblk, dma_ch;
+   
+   	dma_ch = host->dma_ch;
+   	if (data->flags & MMC_DATA_WRITE) {
+   		omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
+   			(host->mapbase + OMAP_HSMMC_DATA), 0, 0);
+   		omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
+ ! 			sg_dma_address(sgl), 0, 0);
+   	} else {
+   		omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
+   			(host->mapbase + OMAP_HSMMC_DATA), 0, 0);
+   		omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
+ ! 			sg_dma_address(sgl), 0, 0);
+   	}
+   
+ - 	blksz = host->data->blksz;
+ - 	nblk = sg_dma_len(sgl) / blksz;
+ - 
+   	omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
+   			blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
+   			omap_hsmmc_get_dma_sync_dev(host, data),
+ --- 1383,1412 ----
+   				       struct scatterlist *sgl)
+   {
+   	int blksz, nblk, dma_ch;
+ + 	int bindex = 0, cindex = 0;
+ + 	struct omap_mmc_platform_data *pdata = host->pdata;
+   
+   	dma_ch = host->dma_ch;
+ + 	blksz = host->data->blksz;
+ + 	nblk = sg_dma_len(sgl) / blksz;
+ + 
+ + 	if (pdata->version == MMC_CTRL_VERSION_2) {
+ + 		bindex = 4;
+ + 		cindex = blksz;
+ + 	}
+ + 
+   	if (data->flags & MMC_DATA_WRITE) {
+   		omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
+   			(host->mapbase + OMAP_HSMMC_DATA), 0, 0);
+   		omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
+ ! 			sg_dma_address(sgl), bindex, cindex);
+   	} else {
+   		omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
+   			(host->mapbase + OMAP_HSMMC_DATA), 0, 0);
+   		omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
+ ! 			sg_dma_address(sgl), bindex, cindex);
+   	}
+   
+   	omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
+   			blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
+   			omap_hsmmc_get_dma_sync_dev(host, data),
+ ***************
+ *** 1370,1381 ****
+   {
+   	struct omap_hsmmc_host *host = cb_data;
+   	struct mmc_data *data;
+   	int dma_ch, req_in_progress;
+   
+ ! 	if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
+ ! 		dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
+ ! 			ch_status);
+ ! 		return;
+   	}
+   
+   	spin_lock(&host->irq_lock);
+ --- 1422,1440 ----
+   {
+   	struct omap_hsmmc_host *host = cb_data;
+   	struct mmc_data *data;
+ + 	struct omap_mmc_platform_data *pdata = host->pdata;
+   	int dma_ch, req_in_progress;
+   
+ ! 
+ ! 	if (pdata->version == MMC_CTRL_VERSION_2) {
+ ! 		if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
+ ! 			dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
+ ! 	} else {
+ ! 		if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
+ ! 			dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
+ ! 				ch_status);
+ ! 			return;
+ ! 		}
+   	}
+   
+   	spin_lock(&host->irq_lock);
+ ***************
+ *** 1498,1508 ****
+   	return 0;
+   }
+   
+ ! static void set_data_timeout(struct omap_hsmmc_host *host,
+ ! 			     unsigned int timeout_ns,
+ ! 			     unsigned int timeout_clks)
+   {
+ - 	unsigned int timeout, cycle_ns;
+   	uint32_t reg, clkd, dto = 0;
+   
+   	reg = OMAP_HSMMC_READ(host->base, SYSCTL);
+ --- 1557,1564 ----
+   	return 0;
+   }
+   
+ ! static void set_data_timeout(struct omap_hsmmc_host *host)
+   {
+   	uint32_t reg, clkd, dto = 0;
+   
+   	reg = OMAP_HSMMC_READ(host->base, SYSCTL);
+ ***************
+ *** 1510,1534 ****
+   	if (clkd == 0)
+   		clkd = 1;
+   
+ ! 	cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
+ ! 	timeout = timeout_ns / cycle_ns;
+ ! 	timeout += timeout_clks;
+ ! 	if (timeout) {
+ ! 		while ((timeout & 0x80000000) == 0) {
+ ! 			dto += 1;
+ ! 			timeout <<= 1;
+ ! 		}
+ ! 		dto = 31 - dto;
+ ! 		timeout <<= 1;
+ ! 		if (timeout && dto)
+ ! 			dto += 1;
+ ! 		if (dto >= 13)
+ ! 			dto -= 13;
+ ! 		else
+ ! 			dto = 0;
+ ! 		if (dto > 14)
+ ! 			dto = 14;
+ ! 	}
+   
+   	reg &= ~DTO_MASK;
+   	reg |= dto << DTO_SHIFT;
+ --- 1566,1573 ----
+   	if (clkd == 0)
+   		clkd = 1;
+   
+ ! 	/* Use the maximum timeout value allowed in the standard of 14 or 0xE */
+ ! 	dto = 14;
+   
+   	reg &= ~DTO_MASK;
+   	reg |= dto << DTO_SHIFT;
+ ***************
+ *** 1551,1563 ****
+   		 * busy signal.
+   		 */
+   		if (req->cmd->flags & MMC_RSP_BUSY)
+ ! 			set_data_timeout(host, 100000000U, 0);
+   		return 0;
+   	}
+   
+   	OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
+   					| (req->data->blocks << 16));
+ ! 	set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
+   
+   	if (host->use_dma) {
+   		ret = omap_hsmmc_start_dma_transfer(host, req);
+ --- 1590,1602 ----
+   		 * busy signal.
+   		 */
+   		if (req->cmd->flags & MMC_RSP_BUSY)
+ ! 			set_data_timeout(host);
+   		return 0;
+   	}
+   
+   	OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
+   					| (req->data->blocks << 16));
+ ! 	set_data_timeout(host);
+   
+   	if (host->use_dma) {
+   		ret = omap_hsmmc_start_dma_transfer(host, req);
+ ***************
+ *** 1649,1654 ****
+ --- 1688,1695 ----
+   {
+   	struct omap_hsmmc_host *host = mmc_priv(mmc);
+   	int do_send_init_stream = 0;
+ + 	struct omap_mmc_platform_data *pdata = host->pdata;
+ + 	u32 regVal;
+   
+   	pm_runtime_get_sync(host->dev);
+   
+ ***************
+ *** 1673,1678 ****
+ --- 1714,1731 ----
+   
+   	/* FIXME: set registers based only on changes to ios */
+   
+ + 	if (pdata->version == MMC_CTRL_VERSION_2) {
+ + 		/*
+ + 		* Set
+ + 		*	Debounce filter value to max
+ + 		*	Write protect polarity to Active low level
+ + 		*/
+ + 		regVal = OMAP_HSMMC_READ(host->base, CON);
+ + 		regVal &= ~(DVAL_MASK | WPP_MASK);
+ + 		regVal |= (DVAL_MAX | WPP_ACT_LOW);
+ + 		OMAP_HSMMC_WRITE(host->base, CON, regVal);
+ + 	}
+ + 
+   	omap_hsmmc_set_bus_width(host);
+   
+   	if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
+ ***************
+ *** 1869,1875 ****
+   	struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
+   	struct mmc_host *mmc;
+   	struct omap_hsmmc_host *host = NULL;
+ ! 	struct resource *res;
+   	int ret, irq;
+   
+   	if (pdata == NULL) {
+ --- 1922,1928 ----
+   	struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
+   	struct mmc_host *mmc;
+   	struct omap_hsmmc_host *host = NULL;
+ ! 	struct resource *res, *dma_tx, *dma_rx;
+   	int ret, irq;
+   
+   	if (pdata == NULL) {
+ ***************
+ *** 1949,1980 ****
+   		dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
+   		mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
+   	}
+ ! 
+   	pm_runtime_enable(host->dev);
+   	pm_runtime_get_sync(host->dev);
+   	pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
+   	pm_runtime_use_autosuspend(host->dev);
+   
+ - 	if (cpu_is_omap2430()) {
+ - 		host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
+ - 		/*
+ - 		 * MMC can still work without debounce clock.
+ - 		 */
+ - 		if (IS_ERR(host->dbclk))
+ - 			dev_warn(mmc_dev(host->mmc),
+ - 				"Failed to get debounce clock\n");
+ - 		else
+ - 			host->got_dbclk = 1;
+ - 
+ - 		if (host->got_dbclk)
+ - 			if (clk_enable(host->dbclk) != 0)
+ - 				dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
+ - 							" clk failed\n");
+ - 	}
+ - 
+   	/* Since we do only SG emulation, we can have as many segs
+   	 * as we want. */
+ ! 	mmc->max_segs = 1024;
+   
+   	mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
+   	mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
+ --- 2002,2019 ----
+   		dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
+   		mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
+   	}
+ ! 	
+   	pm_runtime_enable(host->dev);
+   	pm_runtime_get_sync(host->dev);
+   	pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
+   	pm_runtime_use_autosuspend(host->dev);
+   
+   	/* Since we do only SG emulation, we can have as many segs
+   	 * as we want. */
+ ! 	if (pdata->version == MMC_CTRL_VERSION_2)
+ ! 		mmc->max_segs = 1;
+ ! 	else
+ ! 		mmc->max_segs = 1024;
+   
+   	mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
+   	mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
+ ***************
+ *** 1991,2025 ****
+   	if (mmc_slot(host).nonremovable)
+   		mmc->caps |= MMC_CAP_NONREMOVABLE;
+   
+   	omap_hsmmc_conf_bus_power(host);
+   
+   	/* Select DMA lines */
+ ! 	switch (host->id) {
+ ! 	case OMAP_MMC1_DEVID:
+ ! 		host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
+ ! 		host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
+ ! 		break;
+ ! 	case OMAP_MMC2_DEVID:
+ ! 		host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
+ ! 		host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
+ ! 		break;
+ ! 	case OMAP_MMC3_DEVID:
+ ! 		host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
+ ! 		host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
+ ! 		break;
+ ! 	case OMAP_MMC4_DEVID:
+ ! 		host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
+ ! 		host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
+ ! 		break;
+ ! 	case OMAP_MMC5_DEVID:
+ ! 		host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
+ ! 		host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
+ ! 		break;
+ ! 	default:
+ ! 		dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
+ ! 		goto err_irq;
+ ! 	}
+   
+   	/* Request IRQ for MMC operations */
+   	ret = request_irq(host->irq, omap_hsmmc_irq, 0,
+   			mmc_hostname(mmc), host);
+ --- 2030,2085 ----
+   	if (mmc_slot(host).nonremovable)
+   		mmc->caps |= MMC_CAP_NONREMOVABLE;
+   
+ + 	mmc->pm_caps = mmc_slot(host).pm_caps;
+ + 
+   	omap_hsmmc_conf_bus_power(host);
+   
+   	/* Select DMA lines */
+ ! 	if (pdata->version == MMC_CTRL_VERSION_2) {
+ ! 		dma_rx = platform_get_resource_byname(pdev,
+ ! 							IORESOURCE_DMA, "rx");
+ ! 		if (!dma_rx) {
+ ! 			ret = -EINVAL;
+ ! 			goto err1;
+ ! 		}
+ ! 
+ ! 		dma_tx = platform_get_resource_byname(pdev,
+ ! 							IORESOURCE_DMA, "tx");
+ ! 		if (!dma_tx) {
+ ! 			ret = -EINVAL;
+ ! 			goto err1;
+ ! 		}
+ ! 		host->dma_line_tx = dma_tx->start;
+ ! 		host->dma_line_rx = dma_rx->start;
+   
+ + 	} else {
+ + 		switch (host->id) {
+ + 		case OMAP_MMC1_DEVID:
+ + 			host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
+ + 			host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
+ + 			break;
+ + 		case OMAP_MMC2_DEVID:
+ + 			host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
+ + 			host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
+ + 			break;
+ + 		case OMAP_MMC3_DEVID:
+ + 			host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
+ + 			host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
+ + 			break;
+ + 		case OMAP_MMC4_DEVID:
+ + 			host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
+ + 			host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
+ + 			break;
+ + 		case OMAP_MMC5_DEVID:
+ + 			host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
+ + 			host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
+ + 			break;
+ + 		default:
+ + 			dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
+ + 			goto err_irq;
+ + 		}
+ + 	}
+ + 	
+   	/* Request IRQ for MMC operations */
+   	ret = request_irq(host->irq, omap_hsmmc_irq, 0,
+   			mmc_hostname(mmc), host);
+ ***************
+ *** 2042,2048 ****
+   			goto err_reg;
+   		host->use_reg = 1;
+   	}
+ - 
+   	mmc->ocr_avail = mmc_slot(host).ocr_mask;
+   
+   	/* Request IRQ for card detect */
+ --- 2102,2107 ----
+ ***************
+ *** 2065,2071 ****
+   	omap_hsmmc_protect_card(host);
+   
+   	mmc_add_host(mmc);
+ - 
+   	if (mmc_slot(host).name != NULL) {
+   		ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
+   		if (ret < 0)
+ --- 2124,2129 ----
+ ***************
+ *** 2179,2191 ****
+   		cancel_work_sync(&host->mmc_carddetect_work);
+   		ret = mmc_suspend_host(host->mmc);
+   
+ ! 		if (ret == 0) {
+ ! 			omap_hsmmc_disable_irq(host);
+ ! 			OMAP_HSMMC_WRITE(host->base, HCTL,
+ ! 				OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
+ ! 			if (host->got_dbclk)
+ ! 				clk_disable(host->dbclk);
+ ! 		} else {
+   			host->suspended = 0;
+   			if (host->pdata->resume) {
+   				ret = host->pdata->resume(&pdev->dev,
+ --- 2237,2243 ----
+   		cancel_work_sync(&host->mmc_carddetect_work);
+   		ret = mmc_suspend_host(host->mmc);
+   
+ ! 		if (ret) {
+   			host->suspended = 0;
+   			if (host->pdata->resume) {
+   				ret = host->pdata->resume(&pdev->dev,
+ ***************
+ *** 2194,2202 ****
+   					dev_dbg(mmc_dev(host->mmc),
+   						"Unmask interrupt failed\n");
+   			}
+   		}
+ ! 		pm_runtime_put_sync(host->dev);
+   	}
+   	return ret;
+   }
+   
+ --- 2246,2266 ----
+   					dev_dbg(mmc_dev(host->mmc),
+   						"Unmask interrupt failed\n");
+   			}
+ + 			ret = -EBUSY;
+ + 			goto err;
+   		}
+ ! 
+ ! 		if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
+ ! 			omap_hsmmc_disable_irq(host);
+ ! 			OMAP_HSMMC_WRITE(host->base, HCTL,
+ ! 				OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
+ ! 		}
+ ! 		if (host->got_dbclk)
+ ! 			clk_disable(host->dbclk);
+ ! 
+   	}
+ + err:
+ + 	pm_runtime_put_sync(host->dev);
+   	return ret;
+   }
+   
+ ***************
+ *** 2216,2222 ****
+   		if (host->got_dbclk)
+   			clk_enable(host->dbclk);
+   
+ ! 		omap_hsmmc_conf_bus_power(host);
+   
+   		if (host->pdata->resume) {
+   			ret = host->pdata->resume(&pdev->dev, host->slot_id);
+ --- 2280,2287 ----
+   		if (host->got_dbclk)
+   			clk_enable(host->dbclk);
+   
+ ! 		if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
+ ! 			omap_hsmmc_conf_bus_power(host);
+   
+   		if (host->pdata->resume) {
+   			ret = host->pdata->resume(&pdev->dev, host->slot_id);
+ diff -crN linux-3.2.1_o/drivers/mtd/chips/ckb_gpmc_cs1.c linux-3.2.1/drivers/mtd/chips/ckb_gpmc_cs1.c
+ *** linux-3.2.1_o/drivers/mtd/chips/ckb_gpmc_cs1.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/drivers/mtd/chips/ckb_gpmc_cs1.c	2014-11-25 13:19:15.723055623 +0900
+ ***************
+ *** 0 ****
+ --- 1,333 ----
+ + /*
+ +  * CKB_3352 board : EMIFA CS5 driver
+ +  * 
+ +  * Copyright (C) 2013 Computex Co.Ltd.
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; version 2 of the License.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ +  *
+ +  */     
+ + #include <linux/module.h>
+ + #include <linux/kernel.h>
+ + #include <linux/sched.h>
+ + #include <linux/slab.h>
+ + #include <linux/init.h>
+ + #include <asm/mach/map.h>
+ + #include <linux/platform_device.h>
+ + #include <linux/gpio.h>
+ + #include <linux/mutex.h>
+ + #include <linux/clk.h>
+ + #include <linux/err.h>
+ + #include <linux/platform_device.h>
+ + #include <linux/fs.h>
+ + #include <mach/hardware.h>
+ + #include <asm/uaccess.h>
+ + #include <asm/mach-types.h>
+ + #include <asm/mach/arch.h>
+ + #include <mtd/ckb_gpmc_cs1.h>
+ + #include <linux/syscalls.h>
+ + 
+ + 
+ + /* driver instance */
+ + static struct class *ckb_gpmc_cs1_dev_class;
+ + struct ckb_gpmc_cs1_device *cur_ckb_gpmc_cs1_dev=NULL;		/* single instance */
+ + 
+ + static long ckb_gpmc_cs1_ioctl_write_reg(int offset, unsigned long arg)
+ + {
+ + 	/* set the GPMC_CONFIGn register */
+ + 	void __iomem *gpmc_addr;
+ + 	unsigned long val;
+ + 	if (get_user(val, (unsigned long __user *)arg))
+ + 		return -EFAULT;
+ + 	gpmc_addr = ioremap(AM3352_GPMC_BASE, SZ_1K);
+ + 	writel(val, gpmc_addr + offset);
+ + 	iounmap(gpmc_addr);
+ + 	return 0;
+ + }
+ + 
+ + static long ckb_gpmc_cs1_ioctl_read_reg(int offset, unsigned long arg)
+ + {
+ + 	/* get the GPMC_CONFIGn register value */
+ + 	void __iomem *gpmc_addr;
+ + 	unsigned long val;
+ + 	gpmc_addr = ioremap(AM3352_GPMC_BASE, SZ_1K);
+ + 	val = readl(gpmc_addr + offset);
+ + 	iounmap(gpmc_addr);
+ + 	if (put_user(val, (unsigned long __user *)arg))
+ + 		return -EFAULT;
+ + 	return 0;
+ + }
+ + 
+ + static long ckb_gpmc_cs1_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
+ + {	
+ + 	switch(cmd)
+ + 	{
+ + 	case CKB_GPMC_CS1_IOCTL_SET_CONFIG1_REG:
+ + 		return ckb_gpmc_cs1_ioctl_write_reg(GPMC_CONFIG1_1, arg);
+ + 	case CKB_GPMC_CS1_IOCTL_GET_CONFIG1_REG:
+ + 		return ckb_gpmc_cs1_ioctl_read_reg(GPMC_CONFIG1_1, arg);
+ + 	case CKB_GPMC_CS1_IOCTL_SET_CONFIG2_REG:
+ + 		return ckb_gpmc_cs1_ioctl_write_reg(GPMC_CONFIG2_1, arg);
+ + 	case CKB_GPMC_CS1_IOCTL_GET_CONFIG2_REG:
+ + 		return ckb_gpmc_cs1_ioctl_read_reg(GPMC_CONFIG2_1, arg);
+ + 	case CKB_GPMC_CS1_IOCTL_SET_CONFIG3_REG:
+ + 		return ckb_gpmc_cs1_ioctl_write_reg(GPMC_CONFIG3_1, arg);
+ + 	case CKB_GPMC_CS1_IOCTL_GET_CONFIG3_REG:
+ + 		return ckb_gpmc_cs1_ioctl_read_reg(GPMC_CONFIG3_1, arg);
+ + 	case CKB_GPMC_CS1_IOCTL_SET_CONFIG4_REG:
+ + 		return ckb_gpmc_cs1_ioctl_write_reg(GPMC_CONFIG4_1, arg);
+ + 	case CKB_GPMC_CS1_IOCTL_GET_CONFIG4_REG:
+ + 		return ckb_gpmc_cs1_ioctl_read_reg(GPMC_CONFIG4_1, arg);
+ + 	case CKB_GPMC_CS1_IOCTL_SET_CONFIG5_REG:
+ + 		return ckb_gpmc_cs1_ioctl_write_reg(GPMC_CONFIG5_1, arg);
+ + 	case CKB_GPMC_CS1_IOCTL_GET_CONFIG5_REG:
+ + 		return ckb_gpmc_cs1_ioctl_read_reg(GPMC_CONFIG5_1, arg);
+ + 	case CKB_GPMC_CS1_IOCTL_SET_CONFIG6_REG:
+ + 		return ckb_gpmc_cs1_ioctl_write_reg(GPMC_CONFIG6_1, arg);
+ + 	case CKB_GPMC_CS1_IOCTL_GET_CONFIG6_REG:
+ + 		return ckb_gpmc_cs1_ioctl_read_reg(GPMC_CONFIG6_1, arg);
+ + 	case CKB_GPMC_CS1_IOCTL_SET_CONFIG7_REG:
+ + 		return ckb_gpmc_cs1_ioctl_write_reg(GPMC_CONFIG7_1, arg);
+ + 	case CKB_GPMC_CS1_IOCTL_GET_CONFIG7_REG:
+ + 		return ckb_gpmc_cs1_ioctl_read_reg(GPMC_CONFIG7_1, arg);
+ + 	}	
+ + 	return 0;
+ + }
+ + 
+ + static int ckb_gpmc_cs1_dev_mmap(struct file *file, struct vm_area_struct *vma)
+ + {
+ + 	unsigned long start;
+ + 	unsigned long off;
+ + 	u32 len;
+ + #if 0
+ + 	if ((vma->vm_end - vma->vm_start) > cur_ckb_gpmc_cs1_dev->mem_size)
+ + 		return -EINVAL;
+ + #endif
+ + 	off = vma->vm_pgoff << PAGE_SHIFT;
+ + 	start = cur_ckb_gpmc_cs1_dev->phys_base;
+ + 	len = PAGE_ALIGN((start & ~PAGE_MASK) + cur_ckb_gpmc_cs1_dev->mem_size);
+ + 	
+ + 	start &= PAGE_MASK;
+ + 	if ((vma->vm_end - vma->vm_start + off) > len)
+ + 		return -EINVAL;
+ + 	off += start;
+ + 	vma->vm_pgoff = off >> PAGE_SHIFT;
+ + 	vma->vm_flags |= VM_IO | VM_RESERVED;
+ + 	if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
+ + 				       vma->vm_end - vma->vm_start,
+ + 				       vma->vm_page_prot))
+ + 		return -EAGAIN;
+ + 	return 0; 
+ + }
+ + 
+ + static int ckb_gpmc_cs1_dev_open(struct inode *inode, struct file *file)
+ + {
+ + 	struct ckb_gpmc_cs1_dev *dev;
+ + 	if (cur_ckb_gpmc_cs1_dev == NULL){
+ + 		printk("ckb_gpmc_cs1 open: no device found\n");
+ + 		return -ENODEV;
+ + 	}
+ + 	dev = kzalloc(sizeof(struct ckb_gpmc_cs1_dev), GFP_KERNEL);
+ + 	if (!dev) {
+ + 		printk("ckb_gpmc_cs1 open: failed to allocate memory\n");
+ + 		return -ENOMEM;
+ + 	}
+ + 	dev->device = cur_ckb_gpmc_cs1_dev;
+ + 	file->private_data = dev;
+ + 	return 0;
+ + }
+ + 
+ + static int wramdev_release(struct inode *inode, struct file *file)
+ + {
+ + 	struct ram_dev *dev = file->private_data;
+ + 	kfree(dev);
+ + 	file->private_data = NULL;
+ + 	return 0;
+ + }
+ + 
+ + static ssize_t ckb_gpmc_cs1_info_show(struct device *dev, struct device_attribute *attr, char *buf)
+ + {
+ + 	return sprintf(buf, "%s\n", "ckb_gpmc_cs1");
+ + }
+ + 
+ + static DEVICE_ATTR(ckb_gpmc_cs1, 0666, ckb_gpmc_cs1_info_show, NULL);
+ + 
+ + static int __devinit ckb_gpmc_cs1_probe(struct platform_device *pdev)
+ + {
+ + 	struct resource *plat_res, *res;
+ + 	void __iomem *gpmc_addr;
+ + 	int ret = 0;
+ + 	if(cur_ckb_gpmc_cs1_dev)
+ + 	{
+ + 		dev_err(&pdev->dev, "ckb_gpmc_cs1 access driver can only be loaded once\n");
+ + 		return -ENODEV;
+ + 	}
+ + 	cur_ckb_gpmc_cs1_dev = kzalloc(sizeof(struct ckb_gpmc_cs1_device), GFP_KERNEL);
+ + 	if (cur_ckb_gpmc_cs1_dev == NULL) {
+ + 		dev_err(&pdev->dev, "failed to allocate memory\n");
+ + 		return -ENOMEM;
+ + 	}
+ + 	cur_ckb_gpmc_cs1_dev->pdev = pdev;
+ + 	
+ + 	plat_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ + 	if (plat_res == NULL) {
+ + 		dev_err(&pdev->dev, "no memory resource defined\n");
+ + 		ret = -ENODEV;
+ + 		goto err_free;
+ + 	}
+ + 	
+ + 	res = request_mem_region(plat_res->start, plat_res->end - plat_res->start + 1,
+ + 			pdev->name);
+ + 	if (res == NULL) {
+ + 		dev_err(&pdev->dev, "failed to request memory resource\n");
+ + 		ret = -EBUSY;
+ + 		goto err_free;
+ + 	}
+ + 	
+ + 	gpmc_addr = ioremap(AM3352_GPMC_BASE, SZ_32K);
+ + 
+ + 	/* Initilaize and configure data bus width of CS1 to 8 bit */
+ + 	writel(readl(gpmc_addr + GPMC_CONFIG1_1) & ~DEVICESIZE_MASK, gpmc_addr + GPMC_CONFIG1_1);
+ + 
+ + 	writel(WRAPBURST | READMULTIPLE | READTYPE | WRITEMULTIPLE | WRITETYPE | CLKACTIVATIONTIME | ATTACHDDVICEPAGELENGTH | WAITREADMONITORING | WAITWRITEMONITORING | WAITMONITORINGTIME | WAITPINSELECT | DEVICESIZE_8 | DEVICETYPE | MUXADDDATA | TIMEPARAGRANULARITY | GPMCFCLKDIVIDER
+ + 		, gpmc_addr + GPMC_CONFIG1_1);
+ + 	
+ + 	writel(CSWROFFTIME | CSRDOFFTIME | CEEXTRADELAY | CSONTIME, gpmc_addr + GPMC_CONFIG2_1);
+ + 	writel(ADVADMUXWROFFTIME | ADVAADMUXRDOFFTIME | ADVWROFFTIME | ADVRDOFFTIME | ADVEXTRADELAY | ADVAADMUXONTIME | ADVONTIME, gpmc_addr + GPMC_CONFIG3_1);
+ + 	writel(WEOFFTIME | WEEXTRADELAY | WEONTIME | OEAADMUXOFFTIME | OEOFFTIME | OEEXTRADELAY | OEAADMUXONTIME | OEONTIME, gpmc_addr + GPMC_CONFIG4_1);
+ + 	writel(PAGEBURSTACCESSTIME | RDACCESSTIME | WRCYCLETIME | RDCYCLETIME, gpmc_addr + GPMC_CONFIG5_1);
+ + 	writel(WRACCESSTIME | WRDATAONADMUXBUS | CYCLE2CYCLEDELAY | CYCLE2CYCLESAMECSEN | CYCLE2CYCLEDIFFCSEN | BUSTURNAROUND, gpmc_addr + GPMC_CONFIG6_1);
+ + 	writel(MASKADDRESS| CSVALID | 0x09, gpmc_addr + GPMC_CONFIG7_1);
+ + 	
+ + 	iounmap(gpmc_addr);
+ + 
+ + 	/* store WRAM physical address of the chipset and size */
+ + 	cur_ckb_gpmc_cs1_dev->mem_size = plat_res->end - plat_res->start;
+ + 	cur_ckb_gpmc_cs1_dev->phys_base = plat_res->start;
+ + 	
+ + 	cur_ckb_gpmc_cs1_dev->mmio_base = ioremap(res->start, res->end - res->start + 1);
+ + 	if (cur_ckb_gpmc_cs1_dev->mmio_base == NULL) {
+ + 		dev_err(&pdev->dev, "failed to ioremap() registers\n");
+ + 		ret = -ENODEV;
+ + 		goto err_free_mem;
+ + 	}
+ + 	
+ + 	/* register the GPIO device with the driver core */
+ + 	cur_ckb_gpmc_cs1_dev->dev = device_create(ckb_gpmc_cs1_dev_class, NULL,
+ + 				     MKDEV(CKB_GPMC_CS1_MAJOR,0), NULL,
+ + 				     CKB_GPMC_CS1_DEV_NAME);
+ + 	if (IS_ERR(cur_ckb_gpmc_cs1_dev->dev)) {
+ + 		goto err_free_dev;
+ + 	}
+ + 
+ + 	if (device_create_file(cur_ckb_gpmc_cs1_dev->dev, &dev_attr_ckb_gpmc_cs1))
+ + 		goto error_destroy;
+ + 		
+ + 	platform_set_drvdata(pdev, cur_ckb_gpmc_cs1_dev);
+ + 	
+ + 	return 0;
+ + error_destroy:
+ + 	device_destroy(ckb_gpmc_cs1_dev_class, MKDEV(CKB_GPMC_CS1_MAJOR,0));
+ + err_free_dev:	
+ + 	iounmap(cur_ckb_gpmc_cs1_dev->mmio_base);
+ + err_free_mem:
+ + 	release_mem_region(plat_res->start, plat_res->end - plat_res->start + 1);
+ + err_free:
+ + 	kfree(cur_ckb_gpmc_cs1_dev);
+ + 	cur_ckb_gpmc_cs1_dev = NULL;
+ + 	printk("ckb_gpmc_cs1 device not added\n");
+ + 	return ret;
+ + }
+ + 
+ + static int __devexit ckb_gpmc_cs1_remove(struct platform_device *pdev)
+ + {
+ + 	struct resource *res;
+ + 	if (cur_ckb_gpmc_cs1_dev == NULL)
+ + 		return -ENODEV;
+ + 	device_destroy(ckb_gpmc_cs1_dev_class, MKDEV(CKB_GPMC_CS1_MAJOR,0));
+ + 	iounmap(cur_ckb_gpmc_cs1_dev->mmio_base);
+ + 	
+ + 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ + 	release_mem_region(res->start, res->end - res->start + 1);
+ + 	
+ + 	kfree(cur_ckb_gpmc_cs1_dev);
+ + 	cur_ckb_gpmc_cs1_dev = NULL;
+ + 	return 0;
+ + }
+ + 
+ + static struct platform_driver ckb_gpmc_cs1_driver = {
+ + 	.probe		= ckb_gpmc_cs1_probe,
+ + 	.remove		= __devexit_p(ckb_gpmc_cs1_remove),
+ + 	.driver		= {
+ + 		.owner	= THIS_MODULE,
+ + 		.name	= CKB_GPMC_CS1_DEV_NAME,
+ + 	},
+ + };
+ + 
+ + static const struct file_operations ckb_cs_dev_fops = {
+ + 	.owner		= THIS_MODULE,
+ + 	.llseek		= no_llseek,
+ + 	.read		= NULL,
+ + 	.write		= NULL,
+ + 	.unlocked_ioctl	= ckb_gpmc_cs1_ioctl,
+ + 	.open		= ckb_gpmc_cs1_dev_open,
+ + 	.release	= wramdev_release,
+ + 	.mmap = ckb_gpmc_cs1_dev_mmap,
+ + 	
+ + };
+ + 
+ + static int ckb_gpmc_cs1_init(void)
+ + {
+ + 	int res;
+ + 	res = register_chrdev(CKB_GPMC_CS1_MAJOR, CKB_GPMC_CS1_DEV_NAME, &ckb_cs_dev_fops);
+ + 	if (res)
+ + 	{
+ + 		printk(KERN_ERR "%s: Can't create device file\n", __FILE__);
+ + 		goto out;
+ + 	}
+ + 	ckb_gpmc_cs1_dev_class = class_create(THIS_MODULE, CKB_GPMC_CS1_DEV_NAME);
+ + 	if (IS_ERR(ckb_gpmc_cs1_dev_class)) {
+ + 		printk(KERN_ERR "%s: Can't create class\n", __FILE__);
+ + 		res = PTR_ERR(ckb_gpmc_cs1_dev_class);
+ + 		goto out_unreg_chrdev;
+ + 	}
+ + 	res = platform_driver_register(&ckb_gpmc_cs1_driver);
+ + 	if(res)
+ + 	{
+ + 		printk(KERN_ERR "%s: Can't register driver\n", __FILE__);
+ + 		goto out_unreg_class;
+ + 	}
+ + 	return 0;
+ + 
+ + out_unreg_class:
+ + 	class_destroy(ckb_gpmc_cs1_dev_class);
+ + out_unreg_chrdev:
+ + 	unregister_chrdev(CKB_GPMC_CS1_MAJOR, CKB_GPMC_CS1_DEV_NAME);
+ + out:
+ + 	printk(KERN_ERR "%s: Driver Initialization failed\n", __FILE__);
+ + 	return res;	
+ + }
+ + 
+ + static void __exit ckb_gpmc_cs1_exit(void)
+ + {
+ + 	platform_driver_unregister(&ckb_gpmc_cs1_driver);
+ + 	class_destroy(ckb_gpmc_cs1_dev_class);
+ + 	unregister_chrdev(CKB_GPMC_CS1_MAJOR, CKB_GPMC_CS1_DEV_NAME);
+ + }
+ + 
+ + arch_initcall(ckb_gpmc_cs1_init);
+ + module_exit(ckb_gpmc_cs1_exit);
+ + 
+ + MODULE_DESCRIPTION("CKB 3352 GPMC CS1 driver");
+ + MODULE_AUTHOR("Aiyappa M.S.");
+ + MODULE_LICENSE("GPL");
+ diff -crN linux-3.2.1_o/drivers/mtd/chips/Kconfig linux-3.2.1/drivers/mtd/chips/Kconfig
+ *** linux-3.2.1_o/drivers/mtd/chips/Kconfig	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/mtd/chips/Kconfig	2014-11-25 13:19:15.723055623 +0900
+ ***************
+ *** 239,242 ****
+ --- 239,248 ----
+   	  used for XIP purposes.  If you're not sure what this is all about
+   	  then say N.
+   
+ + config CKB_GPMC_CS1_MEM
+ + 	tristate "CKB 3352 GPMC CS1 driver"
+ + 	depends on MACH_CKB_3352
+ + 	help
+ + 	  Builds CKB 3352 GPMC CS1 driver. The device has to be connected through EX_CN. 
+ + 
+   endmenu
+ diff -crN linux-3.2.1_o/drivers/mtd/chips/Makefile linux-3.2.1/drivers/mtd/chips/Makefile
+ *** linux-3.2.1_o/drivers/mtd/chips/Makefile	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/mtd/chips/Makefile	2014-11-25 13:19:15.728034168 +0900
+ ***************
+ *** 13,15 ****
+ --- 13,16 ----
+   obj-$(CONFIG_MTD_RAM)		+= map_ram.o
+   obj-$(CONFIG_MTD_ROM)		+= map_rom.o
+   obj-$(CONFIG_MTD_ABSENT)	+= map_absent.o
+ + obj-$(CONFIG_CKB_GPMC_CS1_MEM)	+= ckb_gpmc_cs1.o
+ diff -crN linux-3.2.1_o/drivers/mtd/devices/m25p80.c linux-3.2.1/drivers/mtd/devices/m25p80.c
+ *** linux-3.2.1_o/drivers/mtd/devices/m25p80.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/mtd/devices/m25p80.c	2014-11-25 13:19:15.735350193 +0900
+ ***************
+ *** 679,684 ****
+ --- 679,685 ----
+   	{ "mx25l4005a",  INFO(0xc22013, 0, 64 * 1024,   8, SECT_4K) },
+   	{ "mx25l8005",   INFO(0xc22014, 0, 64 * 1024,  16, 0) },
+   	{ "mx25l1606e",  INFO(0xc22015, 0, 64 * 1024,  32, SECT_4K) },
+ + 	{ "mx25l1633e",  INFO(0xc22415, 0, 64 * 1024,  32, SECT_4K) },
+   	{ "mx25l3205d",  INFO(0xc22016, 0, 64 * 1024,  64, 0) },
+   	{ "mx25l6405d",  INFO(0xc22017, 0, 64 * 1024, 128, 0) },
+   	{ "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
+ diff -crN linux-3.2.1_o/drivers/mtd/devices/Makefile linux-3.2.1/drivers/mtd/devices/Makefile
+ *** linux-3.2.1_o/drivers/mtd/devices/Makefile	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/mtd/devices/Makefile	2014-11-25 13:19:15.744070216 +0900
+ ***************
+ *** 18,22 ****
+   obj-$(CONFIG_MTD_DATAFLASH)	+= mtd_dataflash.o
+   obj-$(CONFIG_MTD_M25P80)	+= m25p80.o
+   obj-$(CONFIG_MTD_SST25L)	+= sst25l.o
+   
+ ! CFLAGS_docg3.o			+= -I$(src)
+ \ No newline at end of file
+ --- 18,23 ----
+   obj-$(CONFIG_MTD_DATAFLASH)	+= mtd_dataflash.o
+   obj-$(CONFIG_MTD_M25P80)	+= m25p80.o
+   obj-$(CONFIG_MTD_SST25L)	+= sst25l.o
+ + obj-$(CONFIG_MTD_NAND_OMAP2)	+= omap2_elm.o
+   
+ ! CFLAGS_docg3.o			+= -I$(src)
+ diff -crN linux-3.2.1_o/drivers/net/can/d_can/d_can.c linux-3.2.1/drivers/net/can/d_can/d_can.c
+ *** linux-3.2.1_o/drivers/net/can/d_can/d_can.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/drivers/net/can/d_can/d_can.c	2014-11-25 13:19:15.752074759 +0900
+ ***************
+ *** 0 ****
+ --- 1,1415 ----
+ + /*
+ +  * CAN bus driver for Bosch D_CAN controller
+ +  *
+ +  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ +  *
+ +  * Borrowed from C_CAN driver
+ +  * Copyright (C) 2010 ST Microelectronics
+ +  * - Bhupesh Sharma <bhupesh.sharma@st.com>
+ +  *
+ +  * Borrowed heavily from the C_CAN driver originally written by:
+ +  * Copyright (C) 2007
+ +  * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
+ +  * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
+ +  *
+ +  * Bosch D_CAN controller is compliant to CAN protocol version 2.0 part A and B.
+ +  * Bosch D_CAN user manual can be obtained from:
+ +  * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/can/
+ +  * d_can_users_manual_111.pdf
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #include <linux/kernel.h>
+ + #include <linux/module.h>
+ + #include <linux/interrupt.h>
+ + #include <linux/delay.h>
+ + #include <linux/netdevice.h>
+ + #include <linux/if_arp.h>
+ + #include <linux/if_ether.h>
+ + #include <linux/list.h>
+ + #include <linux/io.h>
+ + 
+ + #include <linux/platform_device.h>
+ + #include <linux/can.h>
+ + #include <linux/can/dev.h>
+ + #include <linux/can/error.h>
+ + 
+ + #include "d_can.h"
+ + 
+ + /* TI D_CAN module registers */
+ + #define D_CAN_CTL		0x0	/* CAN control register */
+ + #define D_CAN_ES		0x4	/* Error and status */
+ + #define D_CAN_PARITYERR_EOI	0x4	/* Parity error EOI */
+ + #define D_CAN_ERRC		0x8	/* Error counter */
+ + #define D_CAN_BTR		0xC	/* Bit timing */
+ + #define D_CAN_INT		0x10	/* Interrupt register */
+ + #define D_CAN_TEST		0x14	/* Test register */
+ + #define D_CAN_PERR		0x1C	/* Parity Error Code */
+ + #define D_CAN_ABOTR		0x80	/* Auto-Bus-On Time */
+ + #define D_CAN_TXRQ_X		0x84	/* Transmission Request X */
+ + #define D_CAN_TXRQ(n)		(0x88 + ((n) * 4)) /* Transmission request */
+ + #define D_CAN_NWDAT_X		0x98	/* New data X register */
+ + #define D_CAN_NWDAT(n)		(0x9C + ((n) * 4)) /* New data */
+ + #define D_CAN_INTPND_X		0xAC	/* Interrupt Pending X */
+ + #define D_CAN_INTPND(n)		(0xB0 + ((n) * 4)) /* Interrupt Pending */
+ + #define D_CAN_MSGVAL_X		0xC0		/* Message Valid X */
+ + #define D_CAN_MSGVAL(n)		(0xC4 + ((n) * 4)) /* Message Valid */
+ + #define D_CAN_INTMUX(n)		(0xD8 + ((n) * 4)) /* Interrupt Multiplexer */
+ + #define D_CAN_IFCMD(n)		(0x100 + ((n) * 0x20)) /* Command */
+ + #define D_CAN_IFMSK(n)		(0x104 + ((n) * 0x20)) /* Mask */
+ + #define D_CAN_IFARB(n)		(0x108 + ((n) * 0x20)) /* Arbitration */
+ + #define D_CAN_IFMCTL(n)		(0x10c + ((n) * 0x20)) /* Message ctl */
+ + #define D_CAN_IFDATA(n)		(0x110 + ((n) * 0x20)) /* DATA A */
+ + #define D_CAN_IFDATB(n)		(0x114 + ((n) * 0x20)) /* DATA B */
+ + #define D_CAN_IF3OBS		0x140	/* IF3 Observation */
+ + #define D_CAN_IF3UPD(n)		(0x160 + ((n) * 4)) /* Update enable */
+ + #define D_CAN_TIOC		0x1E0	/* CAN TX IO Control */
+ + #define D_CAN_RIOC		0x1E4	/* CAN RX IO Control */
+ + 
+ + /* Control register Bit fields */
+ + #define D_CAN_CTL_WUBA		BIT(26)	/* Automatic wake-up on bus activity */
+ + #define D_CAN_CTL_PDR		BIT(24)	/* Request for local low power mode */
+ + #define D_CAN_CTL_DE3		BIT(20)	/* Enable DMA request line for IF3 */
+ + #define D_CAN_CTL_DE2		BIT(19)	/* Enable DMA request line for IF2 */
+ + #define D_CAN_CTL_DE1		BIT(18)	/* Enable DMA request line for IF1 */
+ + #define D_CAN_CTL_IE1		BIT(17)	/* Interrupt line 1 enable */
+ + #define D_CAN_CTL_INITDBG	BIT(16)	/* Init state for debug access */
+ + #define D_CAN_CTL_SWR		BIT(15)	/* S/W reset enable */
+ + #define D_CAN_CTL_PMD		(0xF << 10)	/* Parity on/off */
+ + #define D_CAN_CTL_ABO		BIT(9)	/* Auto bus on enable */
+ + #define D_CAN_CTL_IDS		BIT(8)	/* Interruption debug support enable */
+ + #define D_CAN_CTL_TEST		BIT(7)	/* Test mode enable */
+ + #define D_CAN_CTL_CCE		BIT(6)	/* Configuration change enable */
+ + #define D_CAN_CTL_DISABLE_AR	BIT(5)	/* Disable automatic retransmission */
+ + #define D_CAN_CTL_ENABLE_AR	(0 << 5)
+ + #define D_CAN_CTL_EIE		BIT(3)	/* Error interrupt enable */
+ + #define D_CAN_CTL_SIE		BIT(2)	/* Status change int enable */
+ + #define D_CAN_CTL_IE0		BIT(1)	/* Interrupt line 0 enable */
+ + #define D_CAN_CTL_INIT		BIT(0)	/* D_CAN initialization mode */
+ + 
+ + /* D_CAN Error and Status and Parity Error EOI reg bit fields */
+ + #define D_CAN_ES_PDA		BIT(10)	/* Local power-down ACK */
+ + #define D_CAN_ES_WUP		BIT(9)	/* Wkae up pending */
+ + #define D_CAN_ES_PER		BIT(8)	/* Parity error detected */
+ + #define D_CAN_ES_BOFF		BIT(7)	/* Bus off state */
+ + #define D_CAN_ES_EWARN		BIT(6)	/* Warning state */
+ + #define D_CAN_ES_EPASS		BIT(5)	/* Error passive state */
+ + #define D_CAN_ES_RXOK		BIT(4)	/* Received a msg successfully */
+ + #define D_CAN_ES_TXOK		BIT(3)	/* Transmitted a msg successfully */
+ + #define D_CAN_ES_LEC_MASK	0x7	/* Last error code */
+ + 
+ + /* Parity error reg bit fields */
+ + #define D_CAN_PEEOI		BIT(8)	/* EOI indication for parity error */
+ + 
+ + /* Error counter reg bit fields */
+ + #define D_CAN_ERRC_RP_SHIFT	15
+ + #define D_CAN_ERRC_RP_MASK	BIT(15)		/* Receive error passive */
+ + #define D_CAN_ERRC_REC_SHIFT	8
+ + #define D_CAN_ERRC_REC_MASK	(0x7F << 8)	/* Receive err counter */
+ + #define D_CAN_ERRC_TEC_SHIFT	0
+ + #define D_CAN_ERRC_TEC_MASK	(0xFF << 0)	/* Transmit err counter */
+ + 
+ + /* Bit timing reg bit fields */
+ + #define D_CAN_BTR_BRPE_SHIFT	16
+ + #define D_CAN_BTR_BRPE_MASK	(0xF << 16)	/* Baud rate prescaler ext */
+ + #define D_CAN_BTR_TSEG2_SHIFT	12
+ + #define D_CAN_BTR_TSEG2_MASK	(0x7 << 12)	/* Time seg after smpl point */
+ + #define D_CAN_BTR_TSEG1_SHIFT	8
+ + #define D_CAN_BTR_TSEG1_MASK	(0xF << 8)	/* Time seg before smpl point */
+ + #define D_CAN_BTR_SJW_SHIFT	6
+ + #define D_CAN_BTR_SJW_MASK	(0x3 << 6)	/* Syncronization jump width */
+ + #define D_CAN_BTR_BRP_SHIFT	0
+ + #define D_CAN_BTR_BRP_MASK	(0x3F << 0)	/* Baud rate prescaler */
+ + 
+ + /* D_CAN Test register bit fields */
+ + #define D_CAN_TEST_RDA		BIT(9)	/* RAM direct access enable */
+ + #define D_CAN_TEST_EXL		BIT(8)	/* External loopback mode */
+ + #define D_CAN_TEST_RX		BIT(7)	/* Monitors the reveive pin */
+ + #define D_CAN_TEST_TX		(0x3 << 5)	/* Control of CAN_TX pin */
+ + #define D_CAN_TEST_LBACK	BIT(4)	/* Loopback mode */
+ + #define D_CAN_TEST_SILENT	BIT(3)	/* Silent mdoe */
+ + 
+ + /* D_CAN Parity error reg bit fields */
+ + #define D_CAN_PERR_WN_MASK	(0x7 << 8)	/* Parity error word nuber */
+ + #define D_CAN_PERR_MN_MASK	0xFF		/* Parity error msg object */
+ + 
+ + /* D_CAN X registers bit fields */
+ + #define D_CAN_BIT_FIELD(n)	(0x3 << (2 * n)) /* X reg's bit field 1 mask */
+ + 
+ + /* D_CAN IF command reg bit fields */
+ + #define D_CAN_IF_CMD_WR		BIT(23)	/* Write/read */
+ + #define D_CAN_IF_CMD_MASK	BIT(22)	/* Access to mask bits */
+ + #define D_CAN_IF_CMD_ARB	BIT(21)	/* Access to arbitration bits */
+ + #define D_CAN_IF_CMD_CONTROL	BIT(20)	/* Acess to control bits */
+ + #define D_CAN_IF_CMD_CIP	BIT(19)	/* Clear int pending */
+ + #define D_CAN_IF_CMD_TXRQST	BIT(18)	/* Access transmission request */
+ + #define D_CAN_IF_CMD_DATAA	BIT(17)	/* Access to Data Bytes 0-3 */
+ + #define D_CAN_IF_CMD_DATAB	BIT(16)	/* Access to Data Bytes 4-7 */
+ + #define D_CAN_IF_CMD_BUSY	BIT(15)	/* Busy flag */
+ + #define D_CAN_IF_CMD_DAM	BIT(14)	/* Activation of DMA */
+ + #define D_CAN_IF_CMD_MN_MASK	0xFF	/* No. of msg's used for DMA T/F */
+ + #define D_CAN_IF_CMD_ALL	(D_CAN_IF_CMD_MASK | D_CAN_IF_CMD_ARB | \
+ + 				D_CAN_IF_CMD_CONTROL | D_CAN_IF_CMD_TXRQST | \
+ + 				D_CAN_IF_CMD_DATAA | D_CAN_IF_CMD_DATAB)
+ + 
+ + /* D_CAN IF mask reg bit fields */
+ + #define D_CAN_IF_MASK_MX	BIT(31)	/* Mask Extended Identifier */
+ + #define D_CAN_IF_MASK_MD	BIT(30)	/* Mask Message direction */
+ + 
+ + /* D_CAN IF Arbitration */
+ + #define D_CAN_IF_ARB_MSGVAL	BIT(31)	/* Message Vaild */
+ + #define D_CAN_IF_ARB_MSGXTD	BIT(30)	/* Extended Identifier 0-11 1-29 */
+ + #define D_CAN_IF_ARB_DIR_XMIT	BIT(29) /* Message direction 0-R 1-T */
+ + 
+ + /* D_CAN IF Message control */
+ + #define D_CAN_IF_MCTL_NEWDAT	BIT(15)	/* New data available */
+ + #define D_CAN_IF_MCTL_MSGLST	BIT(14)	/* Message lost, only for receive */
+ + #define D_CAN_IF_MCTL_CLR_MSGLST (0 << 14)
+ + #define D_CAN_IF_MCTL_INTPND	BIT(13)	/* Interrupt pending */
+ + #define D_CAN_IF_MCTL_UMASK	BIT(12)	/* Use acceptance mask */
+ + #define D_CAN_IF_MCTL_TXIE	BIT(11)	/* Transmit int enable */
+ + #define D_CAN_IF_MCTL_RXIE	BIT(10)	/* Receive int enable */
+ + #define D_CAN_IF_MCTL_RMTEN	BIT(9)	/* Remote enable */
+ + #define D_CAN_IF_MCTL_TXRQST	BIT(8)	/* Transmit request */
+ + #define D_CAN_IF_MCTL_EOB	BIT(7)	/* Data frames */
+ + #define D_CAN_IF_MCTL_DLC_MASK	0xF	/* Data length code */
+ + 
+ + /* D_CAN IF3 Observation reg bit fields */
+ + #define D_CAN_IF3OBS_UP		BIT(15)	/* Update data status */
+ + #define D_CAN_IF3OBS_SDB	BIT(12)	/* DataB read out status */
+ + #define D_CAN_IF3OBS_SDA	BIT(11)	/* DataA read out status */
+ + #define D_CAN_IF3OBS_SC		BIT(10)	/* Contol bits read out status */
+ + #define D_CAN_IF3OBS_SA		BIT(9)	/* Arbitration read out status */
+ + #define D_CAN_IF3OBS_SM		BIT(8)	/* Mask bits read out status */
+ + #define D_CAN_IF3OBS_DB		BIT(4)	/* Data B read observation */
+ + #define D_CAN_IF3OBS_DA		BIT(3)	/* Data A read observation */
+ + #define D_CAN_IF3OBS_CTL	BIT(2)	/* Control read observation */
+ + #define D_CAN_IF3OBS_ARB	BIT(1)	/* Arbitration data read observation */
+ + #define D_CAN_IF3OBS_MASK	BIT(0)	/* Mask data read observation */
+ + 
+ + /* D_CAN TX I/O reg bit fields */
+ + #define D_CAN_TIOC_PU		BIT(18)	/* CAN_TX pull up/down select */
+ + #define D_CAN_TIOC_PD		BIT(17)	/* CAN_TX pull disable */
+ + #define D_CAN_TIOC_OD		BIT(16)	/* CAN_TX open drain enable */
+ + #define D_CAN_TIOC_FUNC		BIT(3)	/* CAN_TX function */
+ + #define D_CAN_TIOC_DIR		BIT(2)	/* CAN_TX data direction */
+ + #define D_CAN_TIOC_OUT		BIT(1)	/* CAN_TX data out write */
+ + #define D_CAN_TIOC_IN		BIT(0)	/* CAN_TX data in */
+ + 
+ + /* D_CAN RX I/O reg bit fields */
+ + #define D_CAN_RIOC_PU		BIT(18)	/* CAN_RX pull up/down select */
+ + #define D_CAN_RIOC_PD		BIT(17)	/* CAN_RX pull disable */
+ + #define D_CAN_RIOC_OD		BIT(16)	/* CAN_RX open drain enable */
+ + #define D_CAN_RIOC_FUNC		BIT(3)	/* CAN_RX function */
+ + #define D_CAN_RIOC_DIR		BIT(2)	/* CAN_RX data direction */
+ + #define D_CAN_RIOC_OUT		BIT(1)	/* CAN_RX data out write */
+ + #define D_CAN_RTIOC_IN		BIT(0)	/* CAN_RX data in */
+ + 
+ + #define D_CAN_SET_REG		0xFFFFFFFF
+ + 
+ + #define D_CAN_CANMID_IDE	BIT(31)	/* Extended frame format */
+ + #define D_CAN_CANMID_AME	BIT(30)	/* Acceptance mask enable */
+ + #define D_CAN_CANMID_AAM	BIT(29)	/* Auto answer mode */
+ + 
+ + /*
+ +  * IF register masks:
+ +  */
+ + #define IFX_WRITE_IDR(x)		((x) & 0x1FFFFFFF)
+ + 
+ + #define IFX_CMD_BITS(x)			((x) & 0xFFFFFF00)
+ + #define IFX_CMD_MSG_NUMBER(x)		((x) & 0xFF)
+ + 
+ + /* Message objects split */
+ + #define D_CAN_NUM_MSG_OBJECTS		64
+ + #define D_CAN_NUM_RX_MSG_OBJECTS	32
+ + #define D_CAN_NUM_TX_MSG_OBJECTS	32
+ + 
+ + #define D_CAN_MSG_OBJ_RX_FIRST		1
+ + #define D_CAN_MSG_OBJ_RX_LAST		(D_CAN_MSG_OBJ_RX_FIRST + \
+ + 					D_CAN_NUM_RX_MSG_OBJECTS - 1)
+ + 
+ + #define D_CAN_MSG_OBJ_TX_FIRST		(D_CAN_MSG_OBJ_RX_LAST + 1)
+ + #define D_CAN_MSG_OBJ_TX_LAST		(D_CAN_MSG_OBJ_TX_FIRST + \
+ + 					D_CAN_NUM_TX_MSG_OBJECTS - 1)
+ + 
+ + #define D_CAN_MSG_OBJ_RX_SPLIT		17
+ + #define D_CAN_MSG_OBJ_RX_LOW_LAST	(D_CAN_MSG_OBJ_RX_SPLIT - 1)
+ + 
+ + #define D_CAN_NEXT_MSG_OBJ_MASK		(D_CAN_NUM_TX_MSG_OBJECTS - 1)
+ + 
+ + /* status interrupt */
+ + #define STATUS_INTERRUPT		0x8000
+ + 
+ + /* global interrupt masks */
+ + #define ENABLE_ALL_INTERRUPTS		1
+ + #define DISABLE_ALL_INTERRUPTS		0
+ + 
+ + /* minimum timeout for checking BUSY status */
+ + #define MIN_TIMEOUT_VALUE		6
+ + 
+ + /* Wait for ~1 sec for INIT bit */
+ + #define D_CAN_WAIT_COUNT		1000
+ + 
+ + #define D_CAN_IF_RX_NUM			0
+ + #define D_CAN_IF_TX_NUM			1
+ + 
+ + #define D_CAN_GET_XREG_NUM(priv, reg)	(__ffs(d_can_read(priv, reg))/4)
+ + 
+ + /* CAN Bittiming constants as per D_CAN specs */
+ + static struct can_bittiming_const d_can_bittiming_const = {
+ + 	.name = D_CAN_DRV_NAME,
+ + 	.tseg1_min = 1,		/* Time segment 1 = prop_seg + phase_seg1 */
+ + 	.tseg1_max = 16,
+ + 	.tseg2_min = 1,		/* Time segment 2 = phase_seg2 */
+ + 	.tseg2_max = 8,
+ + 	.sjw_max = 4,
+ + 	.brp_min = 1,
+ + 	.brp_max = 1024,	/* 6-bit BRP field + 4-bit BRPE field*/
+ + 	.brp_inc = 1,
+ + };
+ + 
+ + /* d_can last error code (lec) values */
+ + enum d_can_lec_type {
+ + 	LEC_NO_ERROR = 0,
+ + 	LEC_STUFF_ERROR,
+ + 	LEC_FORM_ERROR,
+ + 	LEC_ACK_ERROR,
+ + 	LEC_BIT1_ERROR,
+ + 	LEC_BIT0_ERROR,
+ + 	LEC_CRC_ERROR,
+ + 	LEC_UNUSED,
+ + };
+ + 
+ + /*
+ +  * d_can error types:
+ +  * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported
+ +  */
+ + enum d_can_bus_error_types {
+ + 	D_CAN_NO_ERROR = 0,
+ + 	D_CAN_BUS_OFF,
+ + 	D_CAN_ERROR_WARNING,
+ + 	D_CAN_ERROR_PASSIVE,
+ + };
+ + 
+ + static inline void d_can_write(struct d_can_priv *priv, u32 reg, u32 val)
+ + {
+ + 	__raw_writel(val, priv->base + reg);
+ + }
+ + 
+ + static inline u32 d_can_read(struct d_can_priv *priv, int reg)
+ + {
+ + 	return __raw_readl(priv->base + reg);
+ + }
+ + 
+ + static inline void d_can_set_bit(struct d_can_priv *priv, int reg,
+ + 	u32 bit_mask)
+ + {
+ + 	d_can_write(priv, reg, d_can_read(priv, reg) | bit_mask);
+ + }
+ + 
+ + static inline u32 d_can_get_bit(struct d_can_priv *priv, int reg,
+ + 	u32 bit_mask)
+ + {
+ + 	return (d_can_read(priv, reg) & bit_mask) ? 1 : 0;
+ + }
+ + 
+ + static inline void d_can_clear_bit(struct d_can_priv *priv, int reg,
+ + 	u32 bit_mask)
+ + {
+ + 	d_can_write(priv, reg, d_can_read(priv, reg) & ~bit_mask);
+ + }
+ + 
+ + static inline int get_tx_next_msg_obj(const struct d_can_priv *priv)
+ + {
+ + 	return (priv->tx_next & D_CAN_NEXT_MSG_OBJ_MASK) +
+ + 			D_CAN_MSG_OBJ_TX_FIRST;
+ + }
+ + 
+ + static inline int get_tx_echo_msg_obj(const struct d_can_priv *priv)
+ + {
+ + 	return (priv->tx_echo & D_CAN_NEXT_MSG_OBJ_MASK) +
+ + 			D_CAN_MSG_OBJ_TX_FIRST;
+ + }
+ + 
+ + /*
+ +  * API for enabling and disabling the multiple interrupts
+ +  * of the DCAN module like error interrupt, status interrupt
+ +  * error enable/disable for instance zero and one and etc.
+ +  */
+ + static void d_can_interrupts(struct d_can_priv *priv, int enable)
+ + {
+ + 	unsigned int cntrl_save = d_can_read(priv, D_CAN_CTL);
+ + 
+ + 	if (enable)
+ + 		cntrl_save |= (D_CAN_CTL_IE1 | D_CAN_CTL_EIE |
+ + 				D_CAN_CTL_IE0);
+ + 	else
+ + 		cntrl_save &= ~(D_CAN_CTL_IE1 | D_CAN_CTL_SIE |
+ + 				D_CAN_CTL_EIE | D_CAN_CTL_IE0);
+ + 
+ + 	d_can_write(priv, D_CAN_CTL, cntrl_save);
+ + }
+ + 
+ + static inline int d_can_msg_obj_is_busy(struct d_can_priv *priv, int iface)
+ + {
+ + 	int count = MIN_TIMEOUT_VALUE;
+ + 
+ + 	while (count && (d_can_read(priv, D_CAN_IFCMD(iface)) &
+ + 				D_CAN_IF_CMD_BUSY)) {
+ + 		count--;
+ + 		udelay(1);
+ + 	}
+ + 
+ + 	if (!count)
+ + 		return 1;
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static inline void d_can_object_get(struct net_device *dev,
+ + 					int iface, int objno, int mask)
+ + {
+ + 	struct d_can_priv *priv = netdev_priv(dev);
+ + 
+ + 	d_can_write(priv, D_CAN_IFCMD(iface), IFX_CMD_BITS(mask) |
+ + 					IFX_CMD_MSG_NUMBER(objno));
+ + 
+ + 	/*
+ + 	 * As per specs, after writing the message object number in the
+ + 	 * IF command register the transfer b/w interface register and
+ + 	 * message RAM must be complete in 12 CAN-CLK period.
+ + 	 */
+ + 	if (d_can_msg_obj_is_busy(priv, iface))
+ + 		netdev_err(dev, "timed out in object get\n");
+ + }
+ + 
+ + static inline void d_can_object_put(struct net_device *dev,
+ + 					int iface, int objno, int mask)
+ + {
+ + 	struct d_can_priv *priv = netdev_priv(dev);
+ + 
+ + 	d_can_write(priv, D_CAN_IFCMD(iface), D_CAN_IF_CMD_WR |
+ + 		IFX_CMD_BITS(mask) | IFX_CMD_MSG_NUMBER(objno));
+ + 
+ + 	/*
+ + 	 * As per specs, after writing the message object number in the
+ + 	 * IF command register the transfer b/w interface register and
+ + 	 * message RAM must be complete in 12 CAN-CLK period.
+ + 	 */
+ + 	if (d_can_msg_obj_is_busy(priv, iface))
+ + 		netdev_err(dev, "timed out in object put\n");
+ + }
+ + 
+ + static void d_can_write_msg_object(struct net_device *dev,
+ + 			int iface, struct can_frame *frame, int objno)
+ + {
+ + 	int i;
+ + 	unsigned int id;
+ + 	u32 dataA = 0;
+ + 	u32 dataB = 0;
+ + 	u32 flags = 0;
+ + 	struct d_can_priv *priv = netdev_priv(dev);
+ + 
+ + 	if (!(frame->can_id & CAN_RTR_FLAG))
+ + 		flags |= D_CAN_IF_ARB_DIR_XMIT;
+ + 
+ + 	if (frame->can_id & CAN_EFF_FLAG) {
+ + 		id = frame->can_id & CAN_EFF_MASK;
+ + 		flags |= D_CAN_IF_ARB_MSGXTD;
+ + 	} else
+ + 		id = ((frame->can_id & CAN_SFF_MASK) << 18);
+ + 
+ + 	flags |= D_CAN_IF_ARB_MSGVAL;
+ + 	d_can_write(priv, D_CAN_IFARB(iface), IFX_WRITE_IDR(id) | flags);
+ + 
+ + 	for (i = 0; i < frame->can_dlc; i++) {
+ + 		if (frame->can_dlc <= 4)
+ + 			dataA |= (frame->data[i] << (8 * i));
+ + 		else {
+ + 			if (i < 4)
+ + 				dataA |= (frame->data[i] << (8 * i));
+ + 			else
+ + 				dataB |= (frame->data[i] << (8 * (i - 4)));
+ + 		}
+ + 	}
+ + 
+ + 	/* DATA write to Message object registers DATAA and DATAB */
+ + 	if (frame->can_dlc <= 4)
+ + 		d_can_write(priv, D_CAN_IFDATA(iface), dataA);
+ + 	else {
+ + 		d_can_write(priv, D_CAN_IFDATB(iface), dataB);
+ + 		d_can_write(priv, D_CAN_IFDATA(iface), dataA);
+ + 	}
+ + 
+ + 	/* enable TX interrupt for this message object */
+ + 	d_can_write(priv, D_CAN_IFMCTL(iface),
+ + 			D_CAN_IF_MCTL_TXIE | D_CAN_IF_MCTL_EOB |
+ + 			D_CAN_IF_MCTL_TXRQST | D_CAN_IF_MCTL_NEWDAT |
+ + 			frame->can_dlc);
+ + 
+ + 	/* Put message data into message RAM */
+ + 	d_can_object_put(dev, iface, objno, D_CAN_IF_CMD_ALL);
+ + }
+ + 
+ + /*
+ +  * Mark that this particular message object is received and clearing
+ +  * the interrupt pending register value.
+ +  */
+ + static inline void d_can_mark_rx_msg_obj(struct net_device *dev,
+ + 				int iface, int ctrl_mask, int obj)
+ + {
+ + 	struct d_can_priv *priv = netdev_priv(dev);
+ + 
+ + 	d_can_write(priv, D_CAN_IFMCTL(iface), ctrl_mask
+ + 		& ~(D_CAN_IF_MCTL_MSGLST | D_CAN_IF_MCTL_INTPND));
+ + 
+ + 	d_can_object_put(dev, iface, obj, D_CAN_IF_CMD_CONTROL);
+ + }
+ + 
+ + static inline void d_can_activate_all_lower_rx_msg_objs(struct net_device *dev,
+ + 				int iface, int ctrl_mask)
+ + {
+ + 	int i;
+ + 	struct d_can_priv *priv = netdev_priv(dev);
+ + 
+ + 	for (i = D_CAN_MSG_OBJ_RX_FIRST; i <= D_CAN_MSG_OBJ_RX_LOW_LAST; i++) {
+ + 		d_can_write(priv, D_CAN_IFMCTL(iface),
+ + 				ctrl_mask & ~(D_CAN_IF_MCTL_MSGLST |
+ + 				D_CAN_IF_MCTL_INTPND | D_CAN_IF_MCTL_NEWDAT));
+ + 		d_can_object_put(dev, iface, i, D_CAN_IF_CMD_CONTROL);
+ + 	}
+ + }
+ + 
+ + static inline void d_can_activate_rx_msg_obj(struct net_device *dev,
+ + 						int iface, int ctrl_mask,
+ + 						int obj)
+ + {
+ + 	struct d_can_priv *priv = netdev_priv(dev);
+ + 
+ + 	d_can_write(priv, D_CAN_IFMCTL(iface),
+ + 			ctrl_mask & ~(D_CAN_IF_MCTL_MSGLST |
+ + 			D_CAN_IF_MCTL_INTPND | D_CAN_IF_MCTL_NEWDAT));
+ + 	d_can_object_put(dev, iface, obj, D_CAN_IF_CMD_CONTROL);
+ + }
+ + 
+ + static void d_can_handle_lost_msg_obj(struct net_device *dev,
+ + 					int iface, int objno)
+ + {
+ + 	struct d_can_priv *priv = netdev_priv(dev);
+ + 	struct net_device_stats *stats = &dev->stats;
+ + 	struct sk_buff *skb;
+ + 	struct can_frame *frame;
+ + 
+ + 	netdev_err(dev, "msg lost in buffer %d\n", objno);
+ + 
+ + 	d_can_object_get(dev, iface, objno, D_CAN_IF_CMD_ALL &
+ + 					~D_CAN_IF_CMD_TXRQST);
+ + 
+ + 	d_can_write(priv, D_CAN_IFMCTL(iface), D_CAN_IF_MCTL_CLR_MSGLST);
+ + 
+ + 	d_can_object_put(dev, iface, objno, D_CAN_IF_CMD_CONTROL);
+ + 
+ + 	/* create an error msg */
+ + 	skb = alloc_can_err_skb(dev, &frame);
+ + 	if (unlikely(!skb))
+ + 		return;
+ + 
+ + 	frame->can_id |= CAN_ERR_CRTL;
+ + 	frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
+ + 	stats->rx_errors++;
+ + 	stats->rx_over_errors++;
+ + 
+ + 	netif_receive_skb(skb);
+ + }
+ + 
+ + static int d_can_read_msg_object(struct net_device *dev, int iface, int ctrl)
+ + {
+ + 	int i;
+ + 	u32 dataA = 0;
+ + 	u32 dataB = 0;
+ + 	unsigned int arb_val;
+ + 	unsigned int mctl_val;
+ + 	struct d_can_priv *priv = netdev_priv(dev);
+ + 	struct net_device_stats *stats = &dev->stats;
+ + 	struct sk_buff *skb;
+ + 	struct can_frame *frame;
+ + 
+ + 	skb = alloc_can_skb(dev, &frame);
+ + 	if (!skb) {
+ + 		stats->rx_dropped++;
+ + 		return -ENOMEM;
+ + 	}
+ + 
+ + 	frame->can_dlc = get_can_dlc(ctrl & 0x0F);
+ + 
+ + 	arb_val = d_can_read(priv, D_CAN_IFARB(iface));
+ + 	mctl_val = d_can_read(priv, D_CAN_IFMCTL(iface));
+ + 
+ + 	if (arb_val & D_CAN_IF_ARB_MSGXTD)
+ + 		frame->can_id = (arb_val & CAN_EFF_MASK) | CAN_EFF_FLAG;
+ + 	else
+ + 		frame->can_id = (arb_val >> 18) & CAN_SFF_MASK;
+ + 
+ + 	if (mctl_val & D_CAN_IF_MCTL_RMTEN)
+ + 		frame->can_id |= CAN_RTR_FLAG;
+ + 	else {
+ + 		dataA = d_can_read(priv, D_CAN_IFDATA(iface));
+ + 		dataB = d_can_read(priv, D_CAN_IFDATB(iface));
+ + 		for (i = 0; i < frame->can_dlc; i++) {
+ + 			/* Writing MO higher 4 data bytes to skb */
+ + 			if (frame->can_dlc <= 4)
+ + 				frame->data[i] = dataA >> (8 * i);
+ + 			else {
+ + 				if (i < 4)
+ + 					frame->data[i] = dataA >> (8 * i);
+ + 				else
+ + 					frame->data[i] = dataB >> (8 * (i-4));
+ + 			}
+ + 		}
+ + 	}
+ + 
+ + 	netif_receive_skb(skb);
+ + 
+ + 	stats->rx_packets++;
+ + 	stats->rx_bytes += frame->can_dlc;
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static void d_can_setup_receive_object(struct net_device *dev, int iface,
+ + 					int objno, unsigned int mask,
+ + 					unsigned int id, unsigned int mcont)
+ + {
+ + 	struct d_can_priv *priv = netdev_priv(dev);
+ + 
+ + 	d_can_write(priv, D_CAN_IFMSK(iface), IFX_WRITE_IDR(mask));
+ + 	d_can_write(priv, D_CAN_IFARB(iface), IFX_WRITE_IDR(id) |
+ + 			D_CAN_IF_ARB_MSGVAL);
+ + 	d_can_write(priv, D_CAN_IFMCTL(iface), mcont);
+ + 
+ + 	d_can_object_put(dev, iface, objno, D_CAN_IF_CMD_ALL &
+ + 					~D_CAN_IF_CMD_TXRQST);
+ + 
+ + 	netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, d_can_read(priv,
+ + 		D_CAN_MSGVAL(D_CAN_GET_XREG_NUM(priv, D_CAN_MSGVAL_X))));
+ + }
+ + 
+ + static void d_can_inval_msg_object(struct net_device *dev, int iface, int objno)
+ + {
+ + 	struct d_can_priv *priv = netdev_priv(dev);
+ + 
+ + 	d_can_write(priv, D_CAN_IFARB(iface), 0);
+ + 	d_can_write(priv, D_CAN_IFMCTL(iface), 0);
+ + 
+ + 	d_can_object_put(dev, iface, objno, D_CAN_IF_CMD_ARB |
+ + 					D_CAN_IF_CMD_CONTROL);
+ + 
+ + 	netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, d_can_read(priv,
+ + 		D_CAN_MSGVAL(D_CAN_GET_XREG_NUM(priv, D_CAN_MSGVAL_X))));
+ + }
+ + 
+ + static inline int d_can_is_next_tx_obj_busy(struct d_can_priv *priv, int objno)
+ + {
+ + 	u32 txrq_x_reg_val = D_CAN_GET_XREG_NUM(priv, D_CAN_TXRQ_X);
+ + 
+ + 	/*
+ + 	 * as transmission request register's bit n-1 corresponds to
+ + 	 * message object n, we need to handle the same properly.
+ + 	 */
+ + 	if (d_can_read(priv, D_CAN_TXRQ(txrq_x_reg_val)) &
+ + 			(1 << (objno - D_CAN_MSG_OBJ_TX_FIRST)))
+ + 		return 1;
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static netdev_tx_t d_can_start_xmit(struct sk_buff *skb,
+ + 					struct net_device *dev)
+ + {
+ + 	u32 msg_obj_no;
+ + 	struct d_can_priv *priv = netdev_priv(dev);
+ + 	struct can_frame *frame = (struct can_frame *)skb->data;
+ + 
+ + 	if (can_dropped_invalid_skb(dev, skb))
+ + 		return NETDEV_TX_OK;
+ + 
+ + 	msg_obj_no = get_tx_next_msg_obj(priv);
+ + 
+ + 	/* prepare message object for transmission */
+ + 	d_can_write_msg_object(dev, D_CAN_IF_TX_NUM, frame, msg_obj_no);
+ + 	can_put_echo_skb(skb, dev, msg_obj_no - D_CAN_MSG_OBJ_TX_FIRST);
+ + 
+ + 	/*
+ + 	 * we have to stop the queue in case of a wrap around or
+ + 	 * if the next TX message object is still in use
+ + 	 */
+ + 	priv->tx_next++;
+ + 	if (d_can_is_next_tx_obj_busy(priv, get_tx_next_msg_obj(priv)) ||
+ + 		((priv->tx_next & D_CAN_NEXT_MSG_OBJ_MASK) == 0))
+ + 		netif_stop_queue(dev);
+ + 
+ + 	return NETDEV_TX_OK;
+ + }
+ + 
+ + static int d_can_set_bittiming(struct net_device *dev)
+ + {
+ + 	struct d_can_priv *priv = netdev_priv(dev);
+ + 	const struct can_bittiming *bt = &priv->can.bittiming;
+ + 	u32 can_btc;
+ + 
+ + 	can_btc = ((bt->phase_seg2 - 1) & 0x7) << D_CAN_BTR_TSEG2_SHIFT;
+ + 	can_btc |= ((bt->phase_seg1 + bt->prop_seg - 1)
+ + 			& 0xF) << D_CAN_BTR_TSEG1_SHIFT;
+ + 
+ + 	can_btc |= ((bt->sjw - 1) & 0x3) << D_CAN_BTR_SJW_SHIFT;
+ + 
+ + 	/* Ten bits contains the BRP, 6 bits for BRP and upper 4 bits for brpe*/
+ + 	can_btc |= ((bt->brp - 1) & 0x3F) << D_CAN_BTR_BRP_SHIFT;
+ + 	can_btc |= ((((bt->brp - 1) >> 6) & 0xF) << D_CAN_BTR_BRPE_SHIFT);
+ + 
+ + 	d_can_write(priv, D_CAN_BTR, can_btc);
+ + 
+ + 	netdev_info(dev, "setting CAN BT = %#x\n", can_btc);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /*
+ +  * Configure D_CAN message objects for Tx and Rx purposes:
+ +  * D_CAN provides a total of 64 message objects that can be configured
+ +  * either for Tx or Rx purposes. In this driver first 32 message objects
+ +  * are used as a reception FIFO and the reception FIFO is signified by the
+ +  * EoB bit being SET. The remaining 32 message objects are kept aside for
+ +  * Tx purposes. See user guide document for further details on configuring
+ +  * message objects.
+ +  */
+ + static void d_can_configure_msg_objects(struct net_device *dev)
+ + {
+ + 	unsigned int i;
+ + 
+ + 	/* first invalidate all message objects */
+ + 	for (i = D_CAN_MSG_OBJ_RX_FIRST; i <= D_CAN_NUM_MSG_OBJECTS; i++)
+ + 		d_can_inval_msg_object(dev, D_CAN_IF_RX_NUM, i);
+ + 
+ + 	/* setup receive message objects */
+ + 	for (i = D_CAN_MSG_OBJ_RX_FIRST; i < D_CAN_MSG_OBJ_RX_LAST; i++)
+ + 		d_can_setup_receive_object(dev, D_CAN_IF_RX_NUM, i, 0, 0,
+ + 			(D_CAN_IF_MCTL_RXIE | D_CAN_IF_MCTL_UMASK) &
+ + 			~D_CAN_IF_MCTL_EOB);
+ + 
+ + 	/* Last object EoB bit should be 1 for terminate */
+ + 	d_can_setup_receive_object(dev, D_CAN_IF_RX_NUM, D_CAN_MSG_OBJ_RX_LAST,
+ + 			0, 0, D_CAN_IF_MCTL_RXIE | D_CAN_IF_MCTL_UMASK |
+ + 			D_CAN_IF_MCTL_EOB);
+ + }
+ + 
+ + static void d_can_test_mode(struct net_device *dev)
+ + {
+ + 	struct d_can_priv *priv = netdev_priv(dev);
+ + 
+ + 	/* Test mode is enabled in this step & the specific TEST bits
+ + 	 * are enabled accordingly */
+ + 	d_can_write(priv, D_CAN_CTL, D_CAN_CTL_EIE |
+ + 			D_CAN_CTL_IE1 |	D_CAN_CTL_IE0 | D_CAN_CTL_TEST);
+ + 
+ + 	if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
+ + 		/* silent mode : bus-monitoring mode */
+ + 		d_can_write(priv, D_CAN_TEST, D_CAN_TEST_SILENT);
+ + 	} else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
+ + 		/* loopback mode : useful for self-test function */
+ + 		d_can_write(priv, D_CAN_TEST, D_CAN_TEST_LBACK);
+ + 	} else {
+ + 		/* loopback + silent mode : useful for hot self-test */
+ + 		d_can_write(priv, D_CAN_TEST, D_CAN_TEST_LBACK |
+ + 				D_CAN_TEST_SILENT);
+ + 	}
+ + }
+ + 
+ + /*
+ +  * Configure D_CAN chip:
+ +  * - enable/disable auto-retransmission
+ +  * - set operating mode
+ +  * - configure message objects
+ +  */
+ + static void d_can_init(struct net_device *dev)
+ + {
+ + 	struct d_can_priv *priv = netdev_priv(dev);
+ + 	u32 cnt;
+ + 
+ + 	netdev_dbg(dev, "resetting d_can ...\n");
+ + 	d_can_set_bit(priv, D_CAN_CTL, D_CAN_CTL_SWR);
+ + 
+ + 	/* Enter initialization mode by setting the Init bit */
+ + 	d_can_set_bit(priv, D_CAN_CTL, D_CAN_CTL_INIT);
+ + 
+ + 	/* enable automatic retransmission */
+ + 	d_can_set_bit(priv, D_CAN_CTL, D_CAN_CTL_ENABLE_AR);
+ + 
+ + 	/* Set the Configure Change Enable ( CCE) bit */
+ + 	d_can_set_bit(priv, D_CAN_CTL, D_CAN_CTL_CCE);
+ + 
+ + 	/* Wait for the Init bit to get set */
+ + 	cnt = D_CAN_WAIT_COUNT;
+ + 	while (!d_can_get_bit(priv, D_CAN_CTL, D_CAN_CTL_INIT) && cnt != 0) {
+ + 		--cnt;
+ + 		udelay(10);
+ + 	}
+ + 
+ + 	/* set bittiming params */
+ + 	d_can_set_bittiming(dev);
+ + 
+ + 	d_can_clear_bit(priv, D_CAN_CTL, D_CAN_CTL_INIT | D_CAN_CTL_CCE);
+ + 
+ + 	/* Wait for the Init bit to get clear */
+ + 	cnt = D_CAN_WAIT_COUNT;
+ + 	while (d_can_get_bit(priv, D_CAN_CTL, D_CAN_CTL_INIT) && cnt != 0) {
+ + 		--cnt;
+ + 		udelay(10);
+ + 	}
+ + 
+ + 	if (priv->can.ctrlmode & (CAN_CTRLMODE_LOOPBACK |
+ + 				CAN_CTRLMODE_LISTENONLY))
+ + 		d_can_test_mode(dev);
+ + 	else
+ + 		/* normal mode*/
+ + 		d_can_write(priv, D_CAN_CTL, D_CAN_CTL_EIE | D_CAN_CTL_IE1 |
+ + 							D_CAN_CTL_IE0);
+ + 
+ + 	/* Enable TX and RX I/O Control pins */
+ + 	d_can_write(priv, D_CAN_TIOC, D_CAN_TIOC_FUNC);
+ + 	d_can_write(priv, D_CAN_RIOC, D_CAN_RIOC_FUNC);
+ + 
+ + 	/* configure message objects */
+ + 	d_can_configure_msg_objects(dev);
+ + 
+ + 	/* set a LEC value so that we can check for updates later */
+ + 	d_can_write(priv, D_CAN_ES, LEC_UNUSED);
+ + }
+ + 
+ + static void d_can_start(struct net_device *dev)
+ + {
+ + 	struct d_can_priv *priv = netdev_priv(dev);
+ + 
+ + 	/* basic d_can initialization */
+ + 	d_can_init(dev);
+ + 
+ + 	priv->can.state = CAN_STATE_ERROR_ACTIVE;
+ + 
+ + 	/* reset tx helper pointers */
+ + 	priv->tx_next = priv->tx_echo = 0;
+ + 
+ + 	/* enable status change, error and module interrupts */
+ + 	d_can_interrupts(priv, ENABLE_ALL_INTERRUPTS);
+ + }
+ + 
+ + static void d_can_stop(struct net_device *dev)
+ + {
+ + 	struct d_can_priv *priv = netdev_priv(dev);
+ + 
+ + 	/* disable all interrupts */
+ + 	d_can_interrupts(priv, DISABLE_ALL_INTERRUPTS);
+ + 
+ + 	/* set the state as STOPPED */
+ + 	priv->can.state = CAN_STATE_STOPPED;
+ + }
+ + 
+ + static int d_can_set_mode(struct net_device *dev, enum can_mode mode)
+ + {
+ + 	switch (mode) {
+ + 	case CAN_MODE_START:
+ + 		d_can_start(dev);
+ + 		netif_wake_queue(dev);
+ + 		break;
+ + 	default:
+ + 		return -EOPNOTSUPP;
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static int d_can_get_berr_counter(const struct net_device *dev,
+ + 					struct can_berr_counter *bec)
+ + {
+ + 	unsigned int reg_err_counter;
+ + 	struct d_can_priv *priv = netdev_priv(dev);
+ + 
+ + 	reg_err_counter = d_can_read(priv, D_CAN_ERRC);
+ + 	bec->rxerr = (reg_err_counter & D_CAN_ERRC_REC_MASK) >>
+ + 				D_CAN_ERRC_REC_SHIFT;
+ + 	bec->txerr = reg_err_counter & D_CAN_ERRC_TEC_MASK;
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /*
+ +  * theory of operation:
+ +  *
+ +  * priv->tx_echo holds the number of the oldest can_frame put for
+ +  * transmission into the hardware, but not yet ACKed by the CAN tx
+ +  * complete IRQ.
+ +  *
+ +  * We iterate from priv->tx_echo to priv->tx_next and check if the
+ +  * packet has been transmitted, echo it back to the CAN framework.
+ +  * If we discover a not yet transmitted package, stop looking for more.
+ +  */
+ + static void d_can_do_tx(struct net_device *dev)
+ + {
+ + 	u32 msg_obj_no;
+ + 	struct d_can_priv *priv = netdev_priv(dev);
+ + 	struct net_device_stats *stats = &dev->stats;
+ + 	u32 txrq_x_reg_val;
+ + 	u32 txrq_reg_val;
+ + 
+ + 	for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) {
+ + 		msg_obj_no = get_tx_echo_msg_obj(priv);
+ + 		txrq_x_reg_val = D_CAN_GET_XREG_NUM(priv, D_CAN_TXRQ_X);
+ + 		txrq_reg_val = d_can_read(priv, D_CAN_TXRQ(txrq_x_reg_val));
+ + 		if (!(txrq_reg_val & (1 << (msg_obj_no -
+ + 						D_CAN_MSG_OBJ_TX_FIRST)))) {
+ + 			can_get_echo_skb(dev,
+ + 					msg_obj_no - D_CAN_MSG_OBJ_TX_FIRST);
+ + 			stats->tx_bytes += d_can_read(priv,
+ + 					D_CAN_IFMCTL(D_CAN_IF_TX_NUM))
+ + 					& D_CAN_IF_MCTL_DLC_MASK;
+ + 			stats->tx_packets++;
+ + 			d_can_inval_msg_object(dev, D_CAN_IF_TX_NUM,
+ + 					msg_obj_no);
+ + 		} else
+ + 			break;
+ + 	}
+ + 
+ + 	/* restart queue if wrap-up or if queue stalled on last pkt */
+ + 	if (((priv->tx_next & D_CAN_NEXT_MSG_OBJ_MASK) != 0)
+ + 		|| ((priv->tx_echo & D_CAN_NEXT_MSG_OBJ_MASK) == 0))
+ + 		netif_wake_queue(dev);
+ + }
+ + 
+ + /*
+ +  * theory of operation:
+ +  *
+ +  * d_can core saves a received CAN message into the first free message
+ +  * object it finds free (starting with the lowest). Bits NEWDAT and
+ +  * INTPND are set for this message object indicating that a new message
+ +  * has arrived. To work-around this issue, we keep two groups of message
+ +  * objects whose partitioning is defined by D_CAN_MSG_OBJ_RX_SPLIT.
+ +  *
+ +  * To ensure in-order frame reception we use the following
+ +  * approach while re-activating a message object to receive further
+ +  * frames:
+ +  * - if the current message object number is lower than
+ +  *   D_CAN_MSG_RX_LOW_LAST, do not clear the NEWDAT bit while clearing
+ +  *   the INTPND bit.
+ +  * - if the current message object number is equal to
+ +  *   D_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of all lower
+ +  *   receive message objects.
+ +  * - if the current message object number is greater than
+ +  *   D_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of
+ +  *   only this message object.
+ +  */
+ + static int d_can_do_rx_poll(struct net_device *dev, int quota)
+ + {
+ + 	struct d_can_priv *priv = netdev_priv(dev);
+ + 	unsigned int msg_obj, mctrl_reg_val;
+ + 	u32 num_rx_pkts = 0;
+ + 	u32 intpnd_x_reg_val;
+ + 	u32 intpnd_reg_val;
+ + 
+ + 	for (msg_obj = D_CAN_MSG_OBJ_RX_FIRST; msg_obj <= D_CAN_MSG_OBJ_RX_LAST
+ + 				&& quota > 0; msg_obj++) {
+ + 
+ + 		intpnd_x_reg_val = D_CAN_GET_XREG_NUM(priv, D_CAN_INTPND_X);
+ + 		intpnd_reg_val = d_can_read(priv,
+ + 					D_CAN_INTPND(intpnd_x_reg_val));
+ + 
+ + 		/*
+ + 		 * as interrupt pending register's bit n-1 corresponds to
+ + 		 * message object n, we need to handle the same properly.
+ + 		 */
+ + 		if (intpnd_reg_val & (1 << (msg_obj - 1))) {
+ + 
+ + 			d_can_object_get(dev, D_CAN_IF_RX_NUM, msg_obj,
+ + 					D_CAN_IF_CMD_ALL &
+ + 					~D_CAN_IF_CMD_TXRQST);
+ + 
+ + 			mctrl_reg_val = d_can_read(priv,
+ + 					D_CAN_IFMCTL(D_CAN_IF_RX_NUM));
+ + 
+ + 			if (!(mctrl_reg_val & D_CAN_IF_MCTL_NEWDAT))
+ + 				continue;
+ + 
+ + 			/* read the data from the message object */
+ + 			d_can_read_msg_object(dev, D_CAN_IF_RX_NUM,
+ + 						mctrl_reg_val);
+ + 
+ + 			if (mctrl_reg_val & D_CAN_IF_MCTL_EOB)
+ + 				d_can_setup_receive_object(dev, D_CAN_IF_RX_NUM,
+ + 					D_CAN_MSG_OBJ_RX_LAST, 0, 0,
+ + 					D_CAN_IF_MCTL_RXIE | D_CAN_IF_MCTL_UMASK
+ + 					| D_CAN_IF_MCTL_EOB);
+ + 
+ + 			if (mctrl_reg_val & D_CAN_IF_MCTL_MSGLST) {
+ + 				d_can_handle_lost_msg_obj(dev, D_CAN_IF_RX_NUM,
+ + 					msg_obj);
+ + 				num_rx_pkts++;
+ + 				quota--;
+ + 				continue;
+ + 			}
+ + 
+ + 			if (msg_obj < D_CAN_MSG_OBJ_RX_LOW_LAST)
+ + 				d_can_mark_rx_msg_obj(dev, D_CAN_IF_RX_NUM,
+ + 						mctrl_reg_val, msg_obj);
+ + 			else if (msg_obj > D_CAN_MSG_OBJ_RX_LOW_LAST)
+ + 				/* activate this msg obj */
+ + 				d_can_activate_rx_msg_obj(dev, D_CAN_IF_RX_NUM,
+ + 						mctrl_reg_val, msg_obj);
+ + 			else if (msg_obj == D_CAN_MSG_OBJ_RX_LOW_LAST)
+ + 				/* activate all lower message objects */
+ + 				d_can_activate_all_lower_rx_msg_objs(dev,
+ + 						D_CAN_IF_RX_NUM, mctrl_reg_val);
+ + 
+ + 			num_rx_pkts++;
+ + 			quota--;
+ + 		}
+ + 	}
+ + 
+ + 	return num_rx_pkts;
+ + }
+ + 
+ + static inline int d_can_has_handle_berr(struct d_can_priv *priv)
+ + {
+ + 	return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
+ + 		(priv->current_status & LEC_UNUSED);
+ + }
+ + 
+ + static int d_can_handle_state_change(struct net_device *dev,
+ + 				enum d_can_bus_error_types error_type)
+ + {
+ + 	unsigned int reg_err_counter;
+ + 	unsigned int rx_err_passive;
+ + 	struct d_can_priv *priv = netdev_priv(dev);
+ + 	struct net_device_stats *stats = &dev->stats;
+ + 	struct can_frame *cf;
+ + 	struct sk_buff *skb;
+ + 	struct can_berr_counter bec;
+ + 
+ + 	/* propagate the error condition to the CAN stack */
+ + 	skb = alloc_can_err_skb(dev, &cf);
+ + 	if (unlikely(!skb))
+ + 		return 0;
+ + 
+ + 	d_can_get_berr_counter(dev, &bec);
+ + 	reg_err_counter = d_can_read(priv, D_CAN_ERRC);
+ + 	rx_err_passive = (reg_err_counter & D_CAN_ERRC_RP_MASK) >>
+ + 				D_CAN_ERRC_RP_SHIFT;
+ + 
+ + 	switch (error_type) {
+ + 	case D_CAN_ERROR_WARNING:
+ + 		/* error warning state */
+ + 		priv->can.can_stats.error_warning++;
+ + 		priv->can.state = CAN_STATE_ERROR_WARNING;
+ + 		cf->can_id |= CAN_ERR_CRTL;
+ + 		cf->data[1] = (bec.txerr > bec.rxerr) ?
+ + 			CAN_ERR_CRTL_TX_WARNING :
+ + 			CAN_ERR_CRTL_RX_WARNING;
+ + 		cf->data[6] = bec.txerr;
+ + 		cf->data[7] = bec.rxerr;
+ + 
+ + 		break;
+ + 	case D_CAN_ERROR_PASSIVE:
+ + 		/* error passive state */
+ + 		priv->can.can_stats.error_passive++;
+ + 		priv->can.state = CAN_STATE_ERROR_PASSIVE;
+ + 		cf->can_id |= CAN_ERR_CRTL;
+ + 		if (rx_err_passive)
+ + 			cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
+ + 		if (bec.txerr > 127)
+ + 			cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
+ + 
+ + 		cf->data[6] = bec.txerr;
+ + 		cf->data[7] = bec.rxerr;
+ + 		break;
+ + 	case D_CAN_BUS_OFF:
+ + 		/* bus-off state */
+ + 		priv->can.state = CAN_STATE_BUS_OFF;
+ + 		cf->can_id |= CAN_ERR_BUSOFF;
+ + 		/*
+ + 		 * disable all interrupts in bus-off mode to ensure that
+ + 		 * the CPU is not hogged down
+ + 		 */
+ + 		d_can_interrupts(priv, DISABLE_ALL_INTERRUPTS);
+ + 		can_bus_off(dev);
+ + 		break;
+ + 	default:
+ + 		break;
+ + 	}
+ + 
+ + 	netif_receive_skb(skb);
+ + 	stats->rx_packets++;
+ + 	stats->rx_bytes += cf->can_dlc;
+ + 
+ + 	return 1;
+ + }
+ + 
+ + static int d_can_handle_bus_err(struct net_device *dev,
+ + 				enum d_can_lec_type lec_type)
+ + {
+ + 	struct d_can_priv *priv = netdev_priv(dev);
+ + 	struct net_device_stats *stats = &dev->stats;
+ + 	struct can_frame *cf;
+ + 	struct sk_buff *skb;
+ + 
+ + 	/*
+ + 	 * early exit if no lec update or no error.
+ + 	 * no lec update means that no CAN bus event has been detected
+ + 	 * since CPU wrote 0x7 value to status reg.
+ + 	 */
+ + 	if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR)
+ + 		return 0;
+ + 
+ + 	/* propagate the error condition to the CAN stack */
+ + 	skb = alloc_can_err_skb(dev, &cf);
+ + 	if (unlikely(!skb))
+ + 		return 0;
+ + 
+ + 	/*
+ + 	 * check for 'last error code' which tells us the
+ + 	 * type of the last error to occur on the CAN bus
+ + 	 */
+ + 
+ + 	/* common for all type of bus errors */
+ + 	priv->can.can_stats.bus_error++;
+ + 	stats->rx_errors++;
+ + 	cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
+ + 	cf->data[2] |= CAN_ERR_PROT_UNSPEC;
+ + 
+ + 	switch (lec_type) {
+ + 	case LEC_STUFF_ERROR:
+ + 		netdev_dbg(dev, "stuff error\n");
+ + 		cf->data[2] |= CAN_ERR_PROT_STUFF;
+ + 		break;
+ + 	case LEC_FORM_ERROR:
+ + 		netdev_dbg(dev, "form error\n");
+ + 		cf->data[2] |= CAN_ERR_PROT_FORM;
+ + 		break;
+ + 	case LEC_ACK_ERROR:
+ + 		netdev_dbg(dev, "ack error\n");
+ + 		cf->data[2] |= (CAN_ERR_PROT_LOC_ACK |
+ + 				CAN_ERR_PROT_LOC_ACK_DEL);
+ + 		break;
+ + 	case LEC_BIT1_ERROR:
+ + 		netdev_dbg(dev, "bit1 error\n");
+ + 		cf->data[2] |= CAN_ERR_PROT_BIT1;
+ + 		break;
+ + 	case LEC_BIT0_ERROR:
+ + 		netdev_dbg(dev, "bit0 error\n");
+ + 		cf->data[2] |= CAN_ERR_PROT_BIT0;
+ + 		break;
+ + 	case LEC_CRC_ERROR:
+ + 		netdev_dbg(dev, "CRC error\n");
+ + 		cf->data[2] |= (CAN_ERR_PROT_LOC_CRC_SEQ |
+ + 				CAN_ERR_PROT_LOC_CRC_DEL);
+ + 		break;
+ + 	default:
+ + 		break;
+ + 	}
+ + 
+ + 	/* set a LEC value so that we can check for updates later */
+ + 	d_can_write(priv, D_CAN_ES, LEC_UNUSED);
+ + 
+ + 	netif_receive_skb(skb);
+ + 	stats->rx_packets++;
+ + 	stats->rx_bytes += cf->can_dlc;
+ + 
+ + 	return 1;
+ + }
+ + 
+ + static int d_can_poll(struct napi_struct *napi, int quota)
+ + {
+ + 	int lec_type = 0;
+ + 	int work_done = 0;
+ + 	struct net_device *dev = napi->dev;
+ + 	struct d_can_priv *priv = netdev_priv(dev);
+ + 
+ + 	if (!priv->irqstatus)
+ + 		goto end;
+ + 
+ + 	/* status events have the highest priority */
+ + 	if (priv->irqstatus == STATUS_INTERRUPT) {
+ + 		priv->current_status = d_can_read(priv, D_CAN_ES);
+ + 
+ + 		/* handle Tx/Rx events */
+ + 		if (priv->current_status & D_CAN_ES_TXOK)
+ + 			d_can_write(priv, D_CAN_ES,
+ + 					priv->current_status & ~D_CAN_ES_TXOK);
+ + 
+ + 		if (priv->current_status & D_CAN_ES_RXOK)
+ + 			d_can_write(priv, D_CAN_ES,
+ + 					priv->current_status & ~D_CAN_ES_RXOK);
+ + 
+ + 		/* handle state changes */
+ + 		if ((priv->current_status & D_CAN_ES_EWARN) &&
+ + 				(!(priv->last_status & D_CAN_ES_EWARN))) {
+ + 			netdev_dbg(dev, "entered error warning state\n");
+ + 			work_done += d_can_handle_state_change(dev,
+ + 						D_CAN_ERROR_WARNING);
+ + 		}
+ + 		if ((priv->current_status & D_CAN_ES_EPASS) &&
+ + 				(!(priv->last_status & D_CAN_ES_EPASS))) {
+ + 			netdev_dbg(dev, "entered error passive state\n");
+ + 			work_done += d_can_handle_state_change(dev,
+ + 						D_CAN_ERROR_PASSIVE);
+ + 		}
+ + 		if ((priv->current_status & D_CAN_ES_BOFF) &&
+ + 				(!(priv->last_status & D_CAN_ES_BOFF))) {
+ + 			netdev_dbg(dev, "entered bus off state\n");
+ + 			work_done += d_can_handle_state_change(dev,
+ + 						D_CAN_BUS_OFF);
+ + 		}
+ + 
+ + 		/* handle bus recovery events */
+ + 		if ((!(priv->current_status & D_CAN_ES_BOFF)) &&
+ + 				(priv->last_status & D_CAN_ES_BOFF)) {
+ + 			netdev_dbg(dev, "left bus off state\n");
+ + 			priv->can.state = CAN_STATE_ERROR_ACTIVE;
+ + 		}
+ + 		if ((!(priv->current_status & D_CAN_ES_EPASS)) &&
+ + 				(priv->last_status & D_CAN_ES_EPASS)) {
+ + 			netdev_dbg(dev, "left error passive state\n");
+ + 			priv->can.state = CAN_STATE_ERROR_ACTIVE;
+ + 		}
+ + 
+ + 		priv->last_status = priv->current_status;
+ + 
+ + 		/* handle lec errors on the bus */
+ + 		lec_type = d_can_has_handle_berr(priv);
+ + 		if (lec_type)
+ + 			work_done += d_can_handle_bus_err(dev, lec_type);
+ + 	} else if ((priv->irqstatus >= D_CAN_MSG_OBJ_RX_FIRST) &&
+ + 			(priv->irqstatus <= D_CAN_MSG_OBJ_RX_LAST)) {
+ + 		/* handle events corresponding to receive message objects */
+ + 		work_done += d_can_do_rx_poll(dev, (quota - work_done));
+ + 	} else if ((priv->irqstatus >= D_CAN_MSG_OBJ_TX_FIRST) &&
+ + 			(priv->irqstatus <= D_CAN_MSG_OBJ_TX_LAST)) {
+ + 		/* handle events corresponding to transmit message objects */
+ + 		d_can_do_tx(dev);
+ + 	}
+ + 
+ + end:
+ + 	if (work_done < quota) {
+ + 		napi_complete(napi);
+ + 		/* enable all IRQs */
+ + 		d_can_interrupts(priv, ENABLE_ALL_INTERRUPTS);
+ + 	}
+ + 
+ + 	return work_done;
+ + }
+ + 
+ + static irqreturn_t d_can_isr(int irq, void *dev_id)
+ + {
+ + 	struct net_device *dev = (struct net_device *)dev_id;
+ + 	struct d_can_priv *priv = netdev_priv(dev);
+ + 
+ + 	priv->irqstatus = d_can_read(priv, D_CAN_INT);
+ + 	if (!priv->irqstatus)
+ + 		return IRQ_NONE;
+ + 
+ + 	/* disable all interrupts and schedule the NAPI */
+ + 	d_can_interrupts(priv, DISABLE_ALL_INTERRUPTS);
+ + 	napi_schedule(&priv->napi);
+ + 
+ + 	return IRQ_HANDLED;
+ + }
+ + 
+ + static int d_can_open(struct net_device *ndev)
+ + {
+ + 	int err;
+ + 	struct d_can_priv *priv = netdev_priv(ndev);
+ + 
+ + 	/* Open common can device */
+ + 	err = open_candev(ndev);
+ + 	if (err) {
+ + 		netdev_err(ndev, "open_candev() failed %d\n", err);
+ + 		return err;
+ + 	}
+ + 
+ + 	/* register interrupt handler for Message Object (MO)
+ + 	 * and Error + status change (ES) */
+ + 	err = request_irq(ndev->irq, &d_can_isr, IRQF_SHARED, ndev->name,
+ + 				ndev);
+ + 	if (err) {
+ + 		netdev_err(ndev, "failed to request MO_ES interrupt\n");
+ + 		goto exit_close_candev;
+ + 	}
+ + 
+ + 	/* register interrupt handler for only Message Object */
+ + 	err = request_irq(priv->irq_obj, &d_can_isr, IRQF_SHARED, ndev->name,
+ + 				ndev);
+ + 	if (err) {
+ + 		netdev_err(ndev, "failed to request MO interrupt\n");
+ + 		goto exit_free_irq;
+ + 	}
+ + 
+ + 	/* start the d_can controller */
+ + 	d_can_start(ndev);
+ + 
+ + 	napi_enable(&priv->napi);
+ + 	netif_start_queue(ndev);
+ + 
+ + 	priv->opened = true;
+ + 	return 0;
+ + exit_free_irq:
+ + 	free_irq(ndev->irq, ndev);
+ + exit_close_candev:
+ + 	close_candev(ndev);
+ + 
+ + 	return err;
+ + }
+ + 
+ + static int d_can_close(struct net_device *ndev)
+ + {
+ + 	struct d_can_priv *priv = netdev_priv(ndev);
+ + 
+ + 	netif_stop_queue(ndev);
+ + 	napi_disable(&priv->napi);
+ + 	d_can_stop(ndev);
+ + 	free_irq(ndev->irq, ndev);
+ + 	free_irq(priv->irq_obj, ndev);
+ + 	close_candev(ndev);
+ + 	priv->opened = false;
+ + 
+ + 	return 0;
+ + }
+ + 
+ + void d_can_reset_ram(struct d_can_priv *d_can, unsigned int instance,
+ + 					unsigned int enable)
+ + {
+ + 	if (d_can->ram_init)
+ + 		d_can->ram_init(instance, enable);
+ + 
+ + 	/* Give some time delay for DCAN RAM initialization */
+ + 	udelay(1);
+ + }
+ + EXPORT_SYMBOL_GPL(d_can_reset_ram);
+ + 
+ + struct net_device *alloc_d_can_dev(int num_objs)
+ + {
+ + 	struct net_device *dev;
+ + 	struct d_can_priv *priv;
+ + 
+ + 	dev = alloc_candev(sizeof(struct d_can_priv), num_objs/2);
+ + 	if (!dev)
+ + 		return NULL;
+ + 
+ + 	priv = netdev_priv(dev);
+ + 	netif_napi_add(dev, &priv->napi, d_can_poll, num_objs/2);
+ + 
+ + 	priv->dev = dev;
+ + 	priv->can.bittiming_const = &d_can_bittiming_const;
+ + 	priv->can.do_set_mode = d_can_set_mode;
+ + 	priv->can.do_get_berr_counter = d_can_get_berr_counter;
+ + 	priv->can.ctrlmode_supported = (CAN_CTRLMODE_LOOPBACK |
+ + 					CAN_CTRLMODE_LISTENONLY |
+ + 					CAN_CTRLMODE_BERR_REPORTING |
+ + 					CAN_CTRLMODE_3_SAMPLES);
+ + 
+ + 	return dev;
+ + }
+ + EXPORT_SYMBOL_GPL(alloc_d_can_dev);
+ + 
+ + #ifdef CONFIG_PM
+ + int d_can_power_down(struct d_can_priv *d_can)
+ + {
+ + 	unsigned long time_out;
+ + 	struct net_device *ndev = platform_get_drvdata(d_can->pdev);
+ + 
+ + 	d_can_set_bit(d_can, D_CAN_CTL, D_CAN_CTL_PDR);
+ + 
+ + 	/* Wait for the PDA bit to get set */
+ + 	time_out = jiffies + msecs_to_jiffies(D_CAN_WAIT_COUNT);
+ + 	while (!d_can_get_bit(d_can, D_CAN_ES, D_CAN_ES_PDA) &&
+ + 				time_after(time_out, jiffies))
+ + 		cpu_relax();
+ + 
+ + 	if (time_after(jiffies, time_out))
+ + 		return -ETIMEDOUT;
+ + 
+ + 	if (d_can->opened)
+ + 		d_can_stop(ndev);
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL_GPL(d_can_power_down);
+ + 
+ + int d_can_power_up(struct d_can_priv *d_can)
+ + {
+ + 	unsigned long time_out;
+ + 	struct net_device *ndev = platform_get_drvdata(d_can->pdev);
+ + 
+ + 	d_can_clear_bit(d_can, D_CAN_CTL, D_CAN_CTL_PDR);
+ + 	d_can_clear_bit(d_can, D_CAN_CTL, D_CAN_CTL_INIT);
+ + 
+ + 	/* Wait for the PDA bit to get clear */
+ + 	time_out = jiffies + msecs_to_jiffies(D_CAN_WAIT_COUNT);
+ + 	while (d_can_get_bit(d_can, D_CAN_ES, D_CAN_ES_PDA) &&
+ + 				time_after(time_out, jiffies))
+ + 		cpu_relax();
+ + 
+ + 	if (time_after(jiffies, time_out))
+ + 		return -ETIMEDOUT;
+ + 
+ + 	if (d_can->opened)
+ + 		d_can_start(ndev);
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL_GPL(d_can_power_up);
+ + #else
+ + #define d_can_power_down NULL
+ + #define d_can_power_up NULL
+ + #endif
+ + 
+ + void free_d_can_dev(struct net_device *dev)
+ + {
+ + 	free_candev(dev);
+ + }
+ + EXPORT_SYMBOL_GPL(free_d_can_dev);
+ + 
+ + static const struct net_device_ops d_can_netdev_ops = {
+ + 	.ndo_open = d_can_open,
+ + 	.ndo_stop = d_can_close,
+ + 	.ndo_start_xmit = d_can_start_xmit,
+ + };
+ + 
+ + int register_d_can_dev(struct net_device *dev)
+ + {
+ + 	/* we support local echo */
+ + 	dev->flags |= IFF_ECHO;
+ + 	dev->netdev_ops = &d_can_netdev_ops;
+ + 
+ + 	return register_candev(dev);
+ + }
+ + EXPORT_SYMBOL_GPL(register_d_can_dev);
+ + 
+ + void unregister_d_can_dev(struct net_device *dev)
+ + {
+ + 	struct d_can_priv *priv = netdev_priv(dev);
+ + 
+ + 	/* disable all interrupts */
+ + 	d_can_interrupts(priv, DISABLE_ALL_INTERRUPTS);
+ + 
+ + 	unregister_candev(dev);
+ + }
+ + EXPORT_SYMBOL_GPL(unregister_d_can_dev);
+ + 
+ + MODULE_AUTHOR("AnilKumar Ch <anilkumar@ti.com>");
+ + MODULE_LICENSE("GPL v2");
+ + MODULE_VERSION(D_CAN_VERSION);
+ + MODULE_DESCRIPTION(D_CAN_DRV_DESC);
+ diff -crN linux-3.2.1_o/drivers/net/can/d_can/d_can.h linux-3.2.1/drivers/net/can/d_can/d_can.h
+ *** linux-3.2.1_o/drivers/net/can/d_can/d_can.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/drivers/net/can/d_can/d_can.h	2014-11-25 13:19:15.752074759 +0900
+ ***************
+ *** 0 ****
+ --- 1,72 ----
+ + /*
+ +  * CAN bus driver for Bosch D_CAN controller
+ +  *
+ +  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ +  *
+ +  * Borrowed from C_CAN driver
+ +  * Copyright (C) 2010 ST Microelectronics
+ +  * - Bhupesh Sharma <bhupesh.sharma@st.com>
+ +  *
+ +  * Borrowed heavily from the C_CAN driver originally written by:
+ +  * Copyright (C) 2007
+ +  * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
+ +  * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
+ +  *
+ +  * Bosch D_CAN controller is compliant to CAN protocol version 2.0 part A and B.
+ +  * Bosch D_CAN user manual can be obtained from:
+ +  * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/can/
+ +  * d_can_users_manual_111.pdf
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #ifndef D_CAN_H
+ + #define D_CAN_H
+ + 
+ + #define D_CAN_DRV_NAME	"d_can"
+ + #define D_CAN_VERSION	"1.0"
+ + #define D_CAN_DRV_DESC	"CAN bus driver for Bosch D_CAN controller " \
+ + 			D_CAN_VERSION
+ + 
+ + /* d_can private data structure */
+ + struct d_can_priv {
+ + 	struct can_priv can;	/* must be the first member */
+ + 	struct napi_struct napi;
+ + 	struct net_device *dev;
+ + 	struct platform_device *pdev;
+ + 	int current_status;
+ + 	int last_status;
+ + 	unsigned int irqstatus;
+ + 	void __iomem *base;
+ + 	u32 napi_weight;
+ + 	struct clk *fck;
+ + 	struct clk *ick;
+ + 	unsigned int irq;	/* device IRQ number, for all MO and ES	*/
+ + 	unsigned int irq_obj;	/* device IRQ number for only Msg Object */
+ + 	unsigned int irq_parity; /* device IRQ number for parity error */
+ + 	unsigned long irq_flags; /* for request_irq() */
+ + 	unsigned int tx_next;
+ + 	unsigned int tx_echo;
+ + 	unsigned int rx_next;
+ + 	bool opened;
+ + 	void *priv;		/* for board-specific data */
+ + 	void (*ram_init) (unsigned int, unsigned int);
+ + };
+ + 
+ + struct net_device *alloc_d_can_dev(int);
+ + void free_d_can_dev(struct net_device *dev);
+ + int d_can_power_up(struct d_can_priv *d_can);
+ + int d_can_power_down(struct d_can_priv *d_can);
+ + int register_d_can_dev(struct net_device *dev);
+ + void unregister_d_can_dev(struct net_device *dev);
+ + void d_can_reset_ram(struct d_can_priv *d_can, unsigned int instance,
+ + 					unsigned int enable);
+ + 
+ + #endif /* D_CAN_H */
+ diff -crN linux-3.2.1_o/drivers/net/can/d_can/d_can_platform.c linux-3.2.1/drivers/net/can/d_can/d_can_platform.c
+ *** linux-3.2.1_o/drivers/net/can/d_can/d_can_platform.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/drivers/net/can/d_can/d_can_platform.c	2014-11-25 13:19:15.756074210 +0900
+ ***************
+ *** 0 ****
+ --- 1,288 ----
+ + /*
+ +  * Platform CAN bus driver for Bosch D_CAN controller
+ +  *
+ +  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ +  *
+ +  * Borrowed from C_CAN driver
+ +  * Copyright (C) 2010 ST Microelectronics
+ +  * - Bhupesh Sharma <bhupesh.sharma@st.com>
+ +  *
+ +  * Borrowed heavily from the C_CAN driver originally written by:
+ +  * Copyright (C) 2007
+ +  * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
+ +  * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
+ +  *
+ +  * Bosch D_CAN controller is compliant to CAN protocol version 2.0 part A and B.
+ +  * Bosch D_CAN user manual can be obtained from:
+ +  * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/can/
+ +  * d_can_users_manual_111.pdf
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + /*
+ +  * Your platform definitions should specify module ram offsets and interrupt
+ +  * number to use as follows:
+ +  *
+ +  * static struct d_can_platform_data am33xx_evm_d_can_pdata = {
+ +  *	.num_of_msg_objs	= 64,
+ +  *	.dma_support		= false,
+ +  *	.ram_init		= d_can_hw_raminit,
+ +  * };
+ +  *
+ +  * Please see include/linux/can/platform/d_can.h for description of
+ +  * above fields.
+ +  *
+ +  */
+ + 
+ + #include <linux/kernel.h>
+ + #include <linux/module.h>
+ + #include <linux/interrupt.h>
+ + #include <linux/delay.h>
+ + #include <linux/netdevice.h>
+ + #include <linux/if_arp.h>
+ + #include <linux/if_ether.h>
+ + #include <linux/list.h>
+ + #include <linux/io.h>
+ + #include <linux/platform_device.h>
+ + #include <linux/can/platform/d_can.h>
+ + #include <linux/clk.h>
+ + #include <linux/pm_runtime.h>
+ + #include <linux/slab.h>
+ + #include <linux/can/dev.h>
+ + 
+ + #include "d_can.h"
+ + 
+ + static int __devinit d_can_plat_probe(struct platform_device *pdev)
+ + {
+ + 	int ret = 0;
+ + 	void __iomem *addr;
+ + 	struct net_device *ndev;
+ + 	struct d_can_priv *priv;
+ + 	struct resource *mem;
+ + 	struct d_can_platform_data *pdata;
+ + 	struct clk *fck;
+ + 
+ + 	pdata = pdev->dev.platform_data;
+ + 	if (!pdata) {
+ + 		dev_err(&pdev->dev, "No platform data\n");
+ + 		goto exit;
+ + 	}
+ + 
+ + 	/* allocate the d_can device */
+ + 	ndev = alloc_d_can_dev(pdata->num_of_msg_objs);
+ + 	if (!ndev) {
+ + 		ret = -ENOMEM;
+ + 		dev_err(&pdev->dev, "alloc_d_can_dev failed\n");
+ + 		goto exit;
+ + 	}
+ + 
+ + 	priv = netdev_priv(ndev);
+ + 	fck = clk_get(&pdev->dev, "fck");
+ + 	if (IS_ERR(fck)) {
+ + 		dev_err(&pdev->dev, "fck is not found\n");
+ + 		ret = -ENODEV;
+ + 		goto exit_free_ndev;
+ + 	}
+ + 
+ + 	/* get the platform data */
+ + 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ + 	if (!mem) {
+ + 		ret = -ENODEV;
+ + 		dev_err(&pdev->dev, "No mem resource\n");
+ + 		goto exit_clk_put;
+ + 	}
+ + 
+ + 	if (!request_mem_region(mem->start, resource_size(mem),
+ + 				D_CAN_DRV_NAME)) {
+ + 		dev_err(&pdev->dev, "resource unavailable\n");
+ + 		ret = -EBUSY;
+ + 		goto exit_clk_put;
+ + 	}
+ + 
+ + 	addr = ioremap(mem->start, resource_size(mem));
+ + 	if (!addr) {
+ + 		dev_err(&pdev->dev, "ioremap failed\n");
+ + 		ret = -ENOMEM;
+ + 		goto exit_release_mem;
+ + 	}
+ + 
+ + 	/* IRQ specific to Error and status & can be used for Message Object */
+ + 	ndev->irq = platform_get_irq_byname(pdev, "d_can_ms");
+ + 	if (!ndev->irq) {
+ + 		dev_err(&pdev->dev, "No irq0 resource\n");
+ + 		goto exit_iounmap;
+ + 	}
+ + 
+ + 	/* IRQ specific for Message Object */
+ + 	priv->irq_obj = platform_get_irq_byname(pdev, "d_can_mo");
+ + 	if (!priv->irq_obj) {
+ + 		dev_err(&pdev->dev, "No irq1 resource\n");
+ + 		goto exit_iounmap;
+ + 	}
+ + 
+ + 	pm_runtime_enable(&pdev->dev);
+ + 	pm_runtime_get_sync(&pdev->dev);
+ + 	priv->pdev = pdev;
+ + 	priv->base = addr;
+ + 	priv->can.clock.freq = clk_get_rate(fck);
+ + 	priv->ram_init = pdata->ram_init;
+ + 	priv->opened = false;
+ + 
+ + 	platform_set_drvdata(pdev, ndev);
+ + 	SET_NETDEV_DEV(ndev, &pdev->dev);
+ + 
+ + 	ret = register_d_can_dev(ndev);
+ + 	if (ret) {
+ + 		dev_err(&pdev->dev, "registering %s failed (err=%d)\n",
+ + 				D_CAN_DRV_NAME, ret);
+ + 		goto exit_free_device;
+ + 	}
+ + 
+ + 	/* Initialize DCAN RAM */
+ + 	d_can_reset_ram(priv, pdev->id, 1);
+ + 
+ + 	dev_info(&pdev->dev, "device registered (irq=%d, irq_obj=%d)\n",
+ + 						ndev->irq, priv->irq_obj);
+ + 
+ + 	return 0;
+ + 
+ + exit_free_device:
+ + 	platform_set_drvdata(pdev, NULL);
+ + 	pm_runtime_disable(&pdev->dev);
+ + exit_iounmap:
+ + 	iounmap(addr);
+ + exit_release_mem:
+ + 	release_mem_region(mem->start, resource_size(mem));
+ + exit_clk_put:
+ + 	clk_put(fck);
+ + exit_free_ndev:
+ + 	free_d_can_dev(ndev);
+ + exit:
+ + 	dev_err(&pdev->dev, "probe failed\n");
+ + 
+ + 	return ret;
+ + }
+ + 
+ + static int __devexit d_can_plat_remove(struct platform_device *pdev)
+ + {
+ + 	struct net_device *ndev = platform_get_drvdata(pdev);
+ + 	struct d_can_priv *priv = netdev_priv(ndev);
+ + 	struct resource *mem;
+ + 
+ + 	/* De-initialize DCAN RAM */
+ + 	d_can_reset_ram(priv, pdev->id, 0);
+ + 
+ + 	unregister_d_can_dev(ndev);
+ + 	platform_set_drvdata(pdev, NULL);
+ + 
+ + 	free_d_can_dev(ndev);
+ + 	iounmap(priv->base);
+ + 
+ + 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ + 	release_mem_region(mem->start, resource_size(mem));
+ + 
+ + 	pm_runtime_put_sync(&pdev->dev);
+ + 	pm_runtime_disable(&pdev->dev);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + #ifdef CONFIG_PM
+ + static int d_can_suspend(struct platform_device *pdev, pm_message_t state)
+ + {
+ + 	int ret;
+ + 	struct net_device *ndev = platform_get_drvdata(pdev);
+ + 	struct d_can_priv *priv = netdev_priv(ndev);
+ + 
+ + 	if (netif_running(ndev)) {
+ + 		netif_stop_queue(ndev);
+ + 		netif_device_detach(ndev);
+ + 	}
+ + 
+ + 	ret = d_can_power_down(priv);
+ + 	if (ret) {
+ + 		dev_err(&pdev->dev, "Not entered power down mode\n");
+ + 		return ret;
+ + 	}
+ + 
+ + 	priv->can.state = CAN_STATE_SLEEPING;
+ + 
+ + 	/* De-initialize DCAN RAM */
+ + 	d_can_reset_ram(priv, pdev->id, 0);
+ + 
+ + 	/* Disable the module */
+ + 	pm_runtime_put_sync(&pdev->dev);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static int d_can_resume(struct platform_device *pdev)
+ + {
+ + 	int ret;
+ + 
+ + 	struct net_device *ndev = platform_get_drvdata(pdev);
+ + 	struct d_can_priv *priv = netdev_priv(ndev);
+ + 
+ + 	/* Enable the module */
+ + 	pm_runtime_get_sync(&pdev->dev);
+ + 
+ + 	/* Initialize DCAN RAM */
+ + 	d_can_reset_ram(priv, pdev->id, 1);
+ + 
+ + 	ret = d_can_power_up(priv);
+ + 	if (ret) {
+ + 		dev_err(&pdev->dev, "Not came out from power down mode\n");
+ + 		return ret;
+ + 	}
+ + 
+ + 	priv->can.state = CAN_STATE_ERROR_ACTIVE;
+ + 
+ + 	if (netif_running(ndev)) {
+ + 		netif_device_attach(ndev);
+ + 		netif_start_queue(ndev);
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ + #else
+ + #define d_can_suspend NULL
+ + #define d_can_resume NULL
+ + #endif
+ + 
+ + static struct platform_driver d_can_plat_driver = {
+ + 	.driver = {
+ + 		.name	= D_CAN_DRV_NAME,
+ + 		.owner	= THIS_MODULE,
+ + 	},
+ + 	.probe		= d_can_plat_probe,
+ + 	.remove		= __devexit_p(d_can_plat_remove),
+ + 	.suspend	= d_can_suspend,
+ + 	.resume		= d_can_resume,
+ + };
+ + 
+ + static int __init d_can_plat_init(void)
+ + {
+ + 	printk(KERN_INFO D_CAN_DRV_DESC "\n");
+ + 	return platform_driver_register(&d_can_plat_driver);
+ + }
+ + module_init(d_can_plat_init);
+ + 
+ + static void __exit d_can_plat_exit(void)
+ + {
+ + 	printk(KERN_INFO D_CAN_DRV_DESC " unloaded\n");
+ + 	platform_driver_unregister(&d_can_plat_driver);
+ + }
+ + module_exit(d_can_plat_exit);
+ + 
+ + MODULE_AUTHOR("AnilKumar Ch <anilkumar@ti.com>");
+ + MODULE_LICENSE("GPL v2");
+ + MODULE_VERSION(D_CAN_VERSION);
+ + MODULE_DESCRIPTION(D_CAN_DRV_DESC);
+ diff -crN linux-3.2.1_o/drivers/net/can/d_can/Kconfig linux-3.2.1/drivers/net/can/d_can/Kconfig
+ *** linux-3.2.1_o/drivers/net/can/d_can/Kconfig	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/drivers/net/can/d_can/Kconfig	2014-11-25 13:19:15.759100635 +0900
+ ***************
+ *** 0 ****
+ --- 1,14 ----
+ + menuconfig CAN_D_CAN
+ + 	tristate "Bosch D_CAN devices"
+ + 	depends on CAN_DEV && HAS_IOMEM
+ + 
+ + if CAN_D_CAN
+ + 
+ + config CAN_D_CAN_PLATFORM
+ + 	tristate "Generic Platform Bus based D_CAN driver"
+ + 	---help---
+ + 	  This driver adds support for the D_CAN chips connected to
+ + 	  the "platform bus" (Linux abstraction for directly to the
+ + 	  processor attached devices) which can be found on am335x
+ + 	  and dm814x boards from TI (http://www.ti.com).
+ + endif
+ diff -crN linux-3.2.1_o/drivers/net/can/d_can/Makefile linux-3.2.1/drivers/net/can/d_can/Makefile
+ *** linux-3.2.1_o/drivers/net/can/d_can/Makefile	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/drivers/net/can/d_can/Makefile	2014-11-25 13:19:15.759100635 +0900
+ ***************
+ *** 0 ****
+ --- 1,8 ----
+ + #
+ + #  Makefile for the Bosch D_CAN controller drivers.
+ + #
+ + 
+ + obj-$(CONFIG_CAN_D_CAN) += d_can.o
+ + obj-$(CONFIG_CAN_D_CAN_PLATFORM) += d_can_platform.o
+ + 
+ + ccflags-$(CONFIG_CAN_DEBUG_DEVICES) := -DDEBUG
+ diff -crN linux-3.2.1_o/drivers/net/can/Kconfig linux-3.2.1/drivers/net/can/Kconfig
+ *** linux-3.2.1_o/drivers/net/can/Kconfig	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/net/can/Kconfig	2014-11-25 13:19:15.759100635 +0900
+ ***************
+ *** 116,121 ****
+ --- 116,123 ----
+   
+   source "drivers/net/can/c_can/Kconfig"
+   
+ + source "drivers/net/can/d_can/Kconfig"
+ + 
+   source "drivers/net/can/usb/Kconfig"
+   
+   source "drivers/net/can/softing/Kconfig"
+ diff -crN linux-3.2.1_o/drivers/net/can/Makefile linux-3.2.1/drivers/net/can/Makefile
+ *** linux-3.2.1_o/drivers/net/can/Makefile	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/net/can/Makefile	2014-11-25 13:19:15.759100635 +0900
+ ***************
+ *** 14,19 ****
+ --- 14,20 ----
+   obj-$(CONFIG_CAN_SJA1000)	+= sja1000/
+   obj-$(CONFIG_CAN_MSCAN)		+= mscan/
+   obj-$(CONFIG_CAN_C_CAN)		+= c_can/
+ + obj-$(CONFIG_CAN_D_CAN)		+= d_can/
+   obj-$(CONFIG_CAN_AT91)		+= at91_can.o
+   obj-$(CONFIG_CAN_TI_HECC)	+= ti_hecc.o
+   obj-$(CONFIG_CAN_MCP251X)	+= mcp251x.o
+ diff -crN linux-3.2.1_o/drivers/net/ethernet/ti/cpsw_ale.c linux-3.2.1/drivers/net/ethernet/ti/cpsw_ale.c
+ *** linux-3.2.1_o/drivers/net/ethernet/ti/cpsw_ale.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/drivers/net/ethernet/ti/cpsw_ale.c	2014-11-25 13:19:15.764047143 +0900
+ ***************
+ *** 0 ****
+ --- 1,982 ----
+ + /*
+ +  * Texas Instruments 3-Port Ethernet Switch Address Lookup Engine
+ +  *
+ +  * Copyright (C) 2010 Texas Instruments
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + #include <linux/kernel.h>
+ + #include <linux/platform_device.h>
+ + #include <linux/seq_file.h>
+ + #include <linux/slab.h>
+ + #include <linux/err.h>
+ + #include <linux/io.h>
+ + #include <linux/stat.h>
+ + #include <linux/sysfs.h>
+ + #include <linux/export.h>
+ + #include <linux/module.h>
+ + #include <linux/etherdevice.h>
+ + 
+ + #include "cpsw_ale.h"
+ + 
+ + #define BITMASK(bits)		(BIT(bits) - 1)
+ + #define ADDR_FMT_STR		"%02x:%02x:%02x:%02x:%02x:%02x"
+ + #define ADDR_FMT_ARGS(addr)	(addr)[0], (addr)[1], (addr)[2], \
+ + 				(addr)[3], (addr)[4], (addr)[5]
+ + #define ALE_ENTRY_BITS		68
+ + #define ALE_ENTRY_WORDS		DIV_ROUND_UP(ALE_ENTRY_BITS, 32)
+ + 
+ + /* ALE Registers */
+ + #define ALE_IDVER		0x00
+ + #define ALE_CONTROL		0x08
+ + #define ALE_PRESCALE		0x10
+ + #define ALE_UNKNOWNVLAN		0x18
+ + #define ALE_TABLE_CONTROL	0x20
+ + #define ALE_TABLE		0x34
+ + #define ALE_PORTCTL		0x40
+ + 
+ + #define ALE_TABLE_WRITE		BIT(31)
+ + 
+ + #define ALE_TYPE_FREE			0
+ + #define ALE_TYPE_ADDR			1
+ + #define ALE_TYPE_VLAN			2
+ + #define ALE_TYPE_VLAN_ADDR		3
+ + 
+ + #define ALE_UCAST_PERSISTANT		0
+ + #define ALE_UCAST_UNTOUCHED		1
+ + #define ALE_UCAST_OUI			2
+ + #define ALE_UCAST_TOUCHED		3
+ + 
+ + #define ALE_MCAST_FWD			0
+ + #define ALE_MCAST_BLOCK_LEARN_FWD	1
+ + #define ALE_MCAST_FWD_LEARN		2
+ + #define ALE_MCAST_FWD_2			3
+ + 
+ + /* the following remap params into members of cpsw_ale */
+ + #define ale_regs	params.ale_regs
+ + #define ale_entries	params.ale_entries
+ + #define ale_ports	params.ale_ports
+ + 
+ + static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
+ + {
+ + 	int idx;
+ + 
+ + 	idx    = start / 32;
+ + 	start -= idx * 32;
+ + 	idx    = 2 - idx; /* flip */
+ + 	return (ale_entry[idx] >> start) & BITMASK(bits);
+ + }
+ + 
+ + static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits,
+ + 				      u32 value)
+ + {
+ + 	int idx;
+ + 
+ + 	value &= BITMASK(bits);
+ + 	idx    = start / 32;
+ + 	start -= idx * 32;
+ + 	idx    = 2 - idx; /* flip */
+ + 	ale_entry[idx] &= ~(BITMASK(bits) << start);
+ + 	ale_entry[idx] |=  (value << start);
+ + }
+ + 
+ + #define DEFINE_ALE_FIELD(name, start, bits)				\
+ + static inline int cpsw_ale_get_##name(u32 *ale_entry)			\
+ + {									\
+ + 	return cpsw_ale_get_field(ale_entry, start, bits);		\
+ + }									\
+ + static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value)	\
+ + {									\
+ + 	cpsw_ale_set_field(ale_entry, start, bits, value);		\
+ + }
+ + 
+ + DEFINE_ALE_FIELD(entry_type,		60,	2)
+ + DEFINE_ALE_FIELD(vlan_id,		48,	12)
+ + DEFINE_ALE_FIELD(mcast_state,		62,	2)
+ + DEFINE_ALE_FIELD(port_mask,		66,     3)
+ + DEFINE_ALE_FIELD(super,			65,	1)
+ + DEFINE_ALE_FIELD(ucast_type,		62,     2)
+ + DEFINE_ALE_FIELD(port_num,		66,     2)
+ + DEFINE_ALE_FIELD(blocked,		65,     1)
+ + DEFINE_ALE_FIELD(secure,		64,     1)
+ + DEFINE_ALE_FIELD(vlan_untag_force,	24,	3)
+ + DEFINE_ALE_FIELD(vlan_reg_mcast,	16,	3)
+ + DEFINE_ALE_FIELD(vlan_unreg_mcast,	8,	3)
+ + DEFINE_ALE_FIELD(vlan_member_list,	0,	3)
+ + DEFINE_ALE_FIELD(mcast,			40,     1)
+ + 
+ + /* The MAC address field in the ALE entry cannot be macroized as above */
+ + static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr)
+ + {
+ + 	int i;
+ + 
+ + 	for (i = 0; i < 6; i++)
+ + 		addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8);
+ + }
+ + 
+ + static inline void cpsw_ale_set_addr(u32 *ale_entry, u8 *addr)
+ + {
+ + 	int i;
+ + 
+ + 	for (i = 0; i < 6; i++)
+ + 		cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]);
+ + }
+ + 
+ + static int cpsw_ale_read(struct cpsw_ale *ale, int idx, u32 *ale_entry)
+ + {
+ + 	int i;
+ + 
+ + 	WARN_ON(idx > ale->ale_entries);
+ + 
+ + 	__raw_writel(idx, ale->ale_regs + ALE_TABLE_CONTROL);
+ + 
+ + 	for (i = 0; i < ALE_ENTRY_WORDS; i++)
+ + 		ale_entry[i] = __raw_readl(ale->ale_regs + ALE_TABLE + 4 * i);
+ + 
+ + 	return idx;
+ + }
+ + 
+ + static int cpsw_ale_write(struct cpsw_ale *ale, int idx, u32 *ale_entry)
+ + {
+ + 	int i;
+ + 
+ + 	WARN_ON(idx > ale->ale_entries);
+ + 
+ + 	for (i = 0; i < ALE_ENTRY_WORDS; i++)
+ + 		__raw_writel(ale_entry[i], ale->ale_regs + ALE_TABLE + 4 * i);
+ + 
+ + 	__raw_writel(idx | ALE_TABLE_WRITE, ale->ale_regs + ALE_TABLE_CONTROL);
+ + 
+ + 	return idx;
+ + }
+ + 
+ + int cpsw_ale_match_addr(struct cpsw_ale *ale, u8* addr, u16 vid)
+ + {
+ + 	u32 ale_entry[ALE_ENTRY_WORDS];
+ + 	int type, idx;
+ + 
+ + 	for (idx = 0; idx < ale->ale_entries; idx++) {
+ + 		u8 entry_addr[6];
+ + 
+ + 		cpsw_ale_read(ale, idx, ale_entry);
+ + 		type = cpsw_ale_get_entry_type(ale_entry);
+ + 		if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
+ + 			continue;
+ + 		if (cpsw_ale_get_vlan_id(ale_entry) != vid)
+ + 			continue;
+ + 		cpsw_ale_get_addr(ale_entry, entry_addr);
+ + 		if (memcmp(entry_addr, addr, 6) == 0)
+ + 			return idx;
+ + 	}
+ + 	return -ENOENT;
+ + }
+ + 
+ + int cpsw_ale_match_vlan(struct cpsw_ale *ale, u16 vid)
+ + {
+ + 	u32 ale_entry[ALE_ENTRY_WORDS];
+ + 	int type, idx;
+ + 
+ + 	for (idx = 0; idx < ale->ale_entries; idx++) {
+ + 		cpsw_ale_read(ale, idx, ale_entry);
+ + 		type = cpsw_ale_get_entry_type(ale_entry);
+ + 		if (type != ALE_TYPE_VLAN)
+ + 			continue;
+ + 		if (cpsw_ale_get_vlan_id(ale_entry) == vid)
+ + 			return idx;
+ + 	}
+ + 	return -ENOENT;
+ + }
+ + 
+ + static int cpsw_ale_match_free(struct cpsw_ale *ale)
+ + {
+ + 	u32 ale_entry[ALE_ENTRY_WORDS];
+ + 	int type, idx;
+ + 
+ + 	for (idx = 0; idx < ale->ale_entries; idx++) {
+ + 		cpsw_ale_read(ale, idx, ale_entry);
+ + 		type = cpsw_ale_get_entry_type(ale_entry);
+ + 		if (type == ALE_TYPE_FREE)
+ + 			return idx;
+ + 	}
+ + 	return -ENOENT;
+ + }
+ + 
+ + static int cpsw_ale_find_ageable(struct cpsw_ale *ale)
+ + {
+ + 	u32 ale_entry[ALE_ENTRY_WORDS];
+ + 	int type, idx;
+ + 
+ + 	for (idx = 0; idx < ale->ale_entries; idx++) {
+ + 		cpsw_ale_read(ale, idx, ale_entry);
+ + 		type = cpsw_ale_get_entry_type(ale_entry);
+ + 		if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
+ + 			continue;
+ + 		if (cpsw_ale_get_mcast(ale_entry))
+ + 			continue;
+ + 		type = cpsw_ale_get_ucast_type(ale_entry);
+ + 		if (type != ALE_UCAST_PERSISTANT &&
+ + 		    type != ALE_UCAST_OUI)
+ + 			return idx;
+ + 	}
+ + 	return -ENOENT;
+ + }
+ + 
+ + static void cpsw_ale_flush_mcast(struct cpsw_ale *ale, u32 *ale_entry,
+ + 				 int port_mask)
+ + {
+ + 	int mask;
+ + 
+ + 	mask = cpsw_ale_get_port_mask(ale_entry);
+ + 	if ((mask & port_mask) == 0)
+ + 		return; /* ports dont intersect, not interested */
+ + 	mask &= ~port_mask;
+ + 
+ + 	/* free if only remaining port is host port */
+ + 	if (mask)
+ + 		cpsw_ale_set_port_mask(ale_entry, mask);
+ + 	else
+ + 		cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
+ + }
+ + 
+ + int cpsw_ale_flush_multicast(struct cpsw_ale *ale, int port_mask)
+ + {
+ + 	u32 ale_entry[ALE_ENTRY_WORDS];
+ + 	int ret, idx;
+ + 
+ + 	for (idx = 0; idx < ale->ale_entries; idx++) {
+ + 		cpsw_ale_read(ale, idx, ale_entry);
+ + 		ret = cpsw_ale_get_entry_type(ale_entry);
+ + 		if (ret != ALE_TYPE_ADDR && ret != ALE_TYPE_VLAN_ADDR)
+ + 			continue;
+ + 
+ + 		if (cpsw_ale_get_mcast(ale_entry)) {
+ + 			u8 addr[6];
+ + 
+ + 			cpsw_ale_get_addr(ale_entry, addr);
+ + 			if (!is_broadcast_ether_addr(addr))
+ + 				cpsw_ale_flush_mcast(ale, ale_entry, port_mask);
+ + 		}
+ + 
+ + 		cpsw_ale_write(ale, idx, ale_entry);
+ + 	}
+ + 	return 0;
+ + }
+ + 
+ + void cpsw_ale_flush_vlan_multicast(struct cpsw_ale *ale, u16 vid, int port_mask)
+ + {
+ + 	u32 ale_entry[ALE_ENTRY_WORDS];
+ + 	int ret, idx;
+ + 
+ + 	for (idx = 0; idx < ale->ale_entries; idx++) {
+ + 		cpsw_ale_read(ale, idx, ale_entry);
+ + 		ret = cpsw_ale_get_entry_type(ale_entry);
+ + 		if (ret != ALE_TYPE_VLAN_ADDR)
+ + 			continue;
+ + 		if (cpsw_ale_get_vlan_id(ale_entry) != vid)
+ + 			continue;
+ + 
+ + 		if (cpsw_ale_get_mcast(ale_entry)) {
+ + 			u8 addr[6];
+ + 
+ + 			cpsw_ale_get_addr(ale_entry, addr);
+ + 			if (!is_broadcast_ether_addr(addr)) {
+ + 				cpsw_ale_flush_mcast(ale, ale_entry, port_mask);
+ + 				cpsw_ale_write(ale, idx, ale_entry);
+ + 			}
+ + 		}
+ + 	}
+ + }
+ + 
+ + static void cpsw_ale_flush_ucast(struct cpsw_ale *ale, u32 *ale_entry,
+ + 				 int port_mask)
+ + {
+ + 	int port;
+ + 
+ + 	port = cpsw_ale_get_port_num(ale_entry);
+ + 	if ((BIT(port) & port_mask) == 0)
+ + 		return; /* ports dont intersect, not interested */
+ + 	cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
+ + }
+ + 
+ + int cpsw_ale_flush(struct cpsw_ale *ale, int port_mask)
+ + {
+ + 	u32 ale_entry[ALE_ENTRY_WORDS];
+ + 	int ret, idx;
+ + 
+ + 	for (idx = 0; idx < ale->ale_entries; idx++) {
+ + 		cpsw_ale_read(ale, idx, ale_entry);
+ + 		ret = cpsw_ale_get_entry_type(ale_entry);
+ + 		if (ret != ALE_TYPE_ADDR && ret != ALE_TYPE_VLAN_ADDR)
+ + 			continue;
+ + 
+ + 		if (cpsw_ale_get_mcast(ale_entry))
+ + 			cpsw_ale_flush_mcast(ale, ale_entry, port_mask);
+ + 		else
+ + 			cpsw_ale_flush_ucast(ale, ale_entry, port_mask);
+ + 
+ + 		cpsw_ale_write(ale, idx, ale_entry);
+ + 	}
+ + 	return 0;
+ + }
+ + 
+ + static int cpsw_ale_dump_mcast(u32 *ale_entry, char *buf, int len)
+ + {
+ + 	int outlen = 0;
+ + 	static const char *str_mcast_state[] = {"f", "blf", "lf", "f"};
+ + 	int mcast_state = cpsw_ale_get_mcast_state(ale_entry);
+ + 	int port_mask   = cpsw_ale_get_port_mask(ale_entry);
+ + 	int super       = cpsw_ale_get_super(ale_entry);
+ + 
+ + 	outlen += snprintf(buf + outlen, len - outlen,
+ + 			   "mcstate: %s(%d), ", str_mcast_state[mcast_state],
+ + 			   mcast_state);
+ + 	outlen += snprintf(buf + outlen, len - outlen,
+ + 			   "port mask: %x, %ssuper\n", port_mask,
+ + 			   super ? "" : "no ");
+ + 	return outlen;
+ + }
+ + 
+ + static int cpsw_ale_dump_ucast(u32 *ale_entry, char *buf, int len)
+ + {
+ + 	int outlen = 0;
+ + 	static const char *str_ucast_type[] = {"persistant", "untouched",
+ + 					       "oui", "touched"};
+ + 	int ucast_type  = cpsw_ale_get_ucast_type(ale_entry);
+ + 	int port_num    = cpsw_ale_get_port_num(ale_entry);
+ + 	int secure      = cpsw_ale_get_secure(ale_entry);
+ + 	int blocked     = cpsw_ale_get_blocked(ale_entry);
+ + 
+ + 	outlen += snprintf(buf + outlen, len - outlen,
+ + 			   "uctype: %s(%d), ", str_ucast_type[ucast_type],
+ + 			   ucast_type);
+ + 	outlen += snprintf(buf + outlen, len - outlen,
+ + 			   "port: %d%s%s\n", port_num, secure ? ", Secure" : "",
+ + 			   blocked ? ", Blocked" : "");
+ + 	return outlen;
+ + }
+ + 
+ + static int cpsw_ale_dump_vlan(u32 *ale_entry, char *buf, int len)
+ + {
+ + 	int outlen = 0;
+ + 	int untag_force = cpsw_ale_get_vlan_untag_force(ale_entry);
+ + 	int reg_mcast   = cpsw_ale_get_vlan_reg_mcast(ale_entry);
+ + 	int unreg_mcast = cpsw_ale_get_vlan_unreg_mcast(ale_entry);
+ + 	int member_list = cpsw_ale_get_vlan_member_list(ale_entry);
+ + 
+ + 	outlen += snprintf(buf + outlen, len - outlen,
+ + 			   "vlanuntag: %x, ", untag_force);
+ + 	outlen += snprintf(buf + outlen, len - outlen,
+ + 			   "vlanregmcast: %x, ", reg_mcast);
+ + 	outlen += snprintf(buf + outlen, len - outlen,
+ + 			   "vlanunregmcast: %x, ", unreg_mcast);
+ + 	outlen += snprintf(buf + outlen, len - outlen,
+ + 			   "vlanmemberlist: %x\n", member_list);
+ + 	return outlen;
+ + }
+ + 
+ + static int cpsw_ale_dump_entry(int idx, u32 *ale_entry, char *buf, int len)
+ + {
+ + 	int type, outlen = 0;
+ + 	u8 addr[6];
+ + 	static const char *str_type[] = {"free", "addr", "vlan", "vlan+addr"};
+ + 
+ + 	type = cpsw_ale_get_entry_type(ale_entry);
+ + 	if (type == ALE_TYPE_FREE)
+ + 		return outlen;
+ + 
+ + 	if (idx >= 0) {
+ + 		outlen += snprintf(buf + outlen, len - outlen,
+ + 				   "index %d, ", idx);
+ + 	}
+ + 
+ + 	outlen += snprintf(buf + outlen, len - outlen, "raw: %08x %08x %08x, ",
+ + 			   ale_entry[0], ale_entry[1], ale_entry[2]);
+ + 
+ + 	outlen += snprintf(buf + outlen, len - outlen,
+ + 			   "type: %s(%d), ", str_type[type], type);
+ + 
+ + 	if (type == ALE_TYPE_VLAN || type == ALE_TYPE_VLAN_ADDR) {
+ + 		outlen += snprintf(buf + outlen, len - outlen, "vlan: %d, ",
+ + 				   cpsw_ale_get_vlan_id(ale_entry));
+ + 	}
+ + 
+ + 	if (type == ALE_TYPE_ADDR || type == ALE_TYPE_VLAN_ADDR) {
+ + 		cpsw_ale_get_addr(ale_entry, addr);
+ + 		outlen += snprintf(buf + outlen, len - outlen,
+ + 			"addr: " ADDR_FMT_STR ", ", ADDR_FMT_ARGS(addr));
+ + 		outlen += cpsw_ale_get_mcast(ale_entry) ?
+ + 			cpsw_ale_dump_mcast(ale_entry, buf + outlen,
+ + 						len - outlen) :
+ + 			cpsw_ale_dump_ucast(ale_entry, buf + outlen,
+ + 						len - outlen);
+ + 	} else {
+ + 		/* type == ALE_TYPE_VLAN */
+ + 		outlen += cpsw_ale_dump_vlan(ale_entry, buf + outlen,
+ + 					     len - outlen);
+ + 	}
+ + 	return outlen;
+ + }
+ + 
+ + int cpsw_ale_dump(struct cpsw_ale *ale, int index, char *buf, int len)
+ + {
+ + 	int outlen = 0, idx;
+ + 	u32 ale_entry[ALE_ENTRY_WORDS];
+ + 
+ + 	if (index) {
+ + 		cpsw_ale_read(ale, index, ale_entry);
+ + 		outlen += cpsw_ale_dump_entry(index, ale_entry,
+ + 				buf + outlen, len - outlen);
+ + 	} else {
+ + 		for (idx = 0; idx < ale->ale_entries; idx++) {
+ + 			cpsw_ale_read(ale, idx, ale_entry);
+ + 			outlen += cpsw_ale_dump_entry(idx, ale_entry,
+ + 					buf + outlen, len - outlen);
+ + 		}
+ + 	}
+ + 	return outlen;
+ + }
+ + 
+ + int cpsw_ale_add_ucast(struct cpsw_ale *ale, u8 *addr, int port, int flags)
+ + {
+ + 	u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
+ + 	int idx;
+ + 
+ + 	cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
+ + 	cpsw_ale_set_addr(ale_entry, addr);
+ + 	cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
+ + 	cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
+ + 	cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
+ + 	cpsw_ale_set_port_num(ale_entry, port);
+ + 
+ + 	idx = cpsw_ale_match_addr(ale, addr, 0);
+ + 	if (idx < 0)
+ + 		idx = cpsw_ale_match_free(ale);
+ + 	if (idx < 0)
+ + 		idx = cpsw_ale_find_ageable(ale);
+ + 	if (idx < 0)
+ + 		return -ENOMEM;
+ + 
+ + 	cpsw_ale_write(ale, idx, ale_entry);
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL_GPL(cpsw_ale_add_ucast);
+ + 
+ + int cpsw_ale_add_oui(struct cpsw_ale *ale, u8 *addr)
+ + {
+ + 	u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
+ + 	int idx;
+ + 
+ + 	cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
+ + 	cpsw_ale_set_addr(ale_entry, addr);
+ + 	cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_OUI);
+ + 
+ + 	idx = cpsw_ale_match_addr(ale, addr, 0);
+ + 	if (idx < 0)
+ + 		idx = cpsw_ale_match_free(ale);
+ + 	if (idx < 0)
+ + 		idx = cpsw_ale_find_ageable(ale);
+ + 	if (idx < 0)
+ + 		return -ENOMEM;
+ + 
+ + 	cpsw_ale_write(ale, idx, ale_entry);
+ + 	return 0;
+ + }
+ + 
+ + int cpsw_ale_del_ucast(struct cpsw_ale *ale, u8 *addr, int port)
+ + {
+ + 	u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
+ + 	int idx;
+ + 
+ + 	idx = cpsw_ale_match_addr(ale, addr, 0);
+ + 	if (idx < 0)
+ + 		return -ENOENT;
+ + 
+ + 	cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
+ + 	cpsw_ale_write(ale, idx, ale_entry);
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL_GPL(cpsw_ale_del_ucast);
+ + 
+ + int cpsw_ale_add_mcast(struct cpsw_ale *ale, u8 *addr, int port_mask,
+ + 			int super, int mcast_state)
+ + {
+ + 	u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
+ + 	int idx, mask;
+ + 
+ + 	idx = cpsw_ale_match_addr(ale, addr, 0);
+ + 	if (idx >= 0)
+ + 		cpsw_ale_read(ale, idx, ale_entry);
+ + 
+ + 	cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
+ + 	cpsw_ale_set_addr(ale_entry, addr);
+ + 	cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2);
+ + 	cpsw_ale_set_super(ale_entry, super);
+ + 	cpsw_ale_set_mcast_state(ale_entry, mcast_state);
+ + 
+ + 	mask = cpsw_ale_get_port_mask(ale_entry);
+ + 	port_mask |= mask;
+ + 	cpsw_ale_set_port_mask(ale_entry, port_mask);
+ + 
+ + 	if (idx < 0)
+ + 		idx = cpsw_ale_match_free(ale);
+ + 	if (idx < 0)
+ + 		idx = cpsw_ale_find_ageable(ale);
+ + 	if (idx < 0)
+ + 		return -ENOMEM;
+ + 
+ + 	cpsw_ale_write(ale, idx, ale_entry);
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL_GPL(cpsw_ale_add_mcast);
+ + 
+ + int cpsw_ale_del_mcast(struct cpsw_ale *ale, u8 *addr, int port_mask)
+ + {
+ + 	u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
+ + 	int idx;
+ + 
+ + 	idx = cpsw_ale_match_addr(ale, addr, 0);
+ + 	if (idx < 0)
+ + 		return -EINVAL;
+ + 
+ + 	cpsw_ale_read(ale, idx, ale_entry);
+ + 
+ + 	if (port_mask)
+ + 		cpsw_ale_set_port_mask(ale_entry, port_mask);
+ + 	else
+ + 		cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
+ + 
+ + 	cpsw_ale_write(ale, idx, ale_entry);
+ + 	return 0;
+ + }
+ + 
+ + int cpsw_ale_add_vlan(struct cpsw_ale *ale, u16 vid, int port, int untag,
+ + 		      int reg_mcast, int unreg_mcast)
+ + {
+ + 	u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
+ + 	int idx;
+ + 
+ + 	idx = cpsw_ale_match_vlan(ale, vid);
+ + 	if (idx >= 0)
+ + 		cpsw_ale_read(ale, idx, ale_entry);
+ + 
+ + 	cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_VLAN);
+ + 	cpsw_ale_set_vlan_id(ale_entry, vid);
+ + 
+ + 	cpsw_ale_set_vlan_untag_force(ale_entry, untag);
+ + 	cpsw_ale_set_vlan_reg_mcast(ale_entry, reg_mcast);
+ + 	cpsw_ale_set_vlan_unreg_mcast(ale_entry, unreg_mcast);
+ + 	cpsw_ale_set_vlan_member_list(ale_entry, port);
+ + 
+ + 	if (idx < 0)
+ + 		idx = cpsw_ale_match_free(ale);
+ + 	if (idx < 0)
+ + 		idx = cpsw_ale_find_ageable(ale);
+ + 	if (idx < 0)
+ + 		return -ENOMEM;
+ + 
+ + 	cpsw_ale_write(ale, idx, ale_entry);
+ + 	return 0;
+ + }
+ + 
+ + int cpsw_ale_del_vlan(struct cpsw_ale *ale, u16 vid, int port)
+ + {
+ + 	u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
+ + 	int idx, mask;
+ + 
+ + 	idx = cpsw_ale_match_vlan(ale, vid);
+ + 	if (idx < 0)
+ + 		return -ENOENT;
+ + 
+ + 	cpsw_ale_read(ale, idx, ale_entry);
+ + 
+ + 	mask  = cpsw_ale_get_vlan_member_list(ale_entry);
+ + 	mask &= ~port;
+ + 	if (!mask)
+ + 		cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
+ + 	else
+ + 		cpsw_ale_set_vlan_member_list(ale_entry, mask);
+ + 
+ + 	cpsw_ale_write(ale, idx, ale_entry);
+ + 	return 0;
+ + }
+ + 
+ + int cpsw_ale_vlan_add_ucast(struct cpsw_ale *ale, u8 *addr, int port,
+ + 				int flags, u16 vid)
+ + {
+ + 	u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
+ + 	int idx;
+ + 
+ + 	cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_VLAN_ADDR);
+ + 	cpsw_ale_set_addr(ale_entry, addr);
+ + 	cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
+ + 	cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
+ + 	cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
+ + 	cpsw_ale_set_port_num(ale_entry, port);
+ + 	cpsw_ale_set_vlan_id(ale_entry, vid);
+ + 
+ + 	idx = cpsw_ale_match_addr(ale, addr, vid);
+ + 	if (idx < 0)
+ + 		idx = cpsw_ale_match_free(ale);
+ + 	if (idx < 0)
+ + 		idx = cpsw_ale_find_ageable(ale);
+ + 	if (idx < 0)
+ + 		return -ENOMEM;
+ + 
+ + 	cpsw_ale_write(ale, idx, ale_entry);
+ + 	return 0;
+ + }
+ + 
+ + int cpsw_ale_vlan_del_ucast(struct cpsw_ale *ale, u8 *addr, int port, u16 vid)
+ + {
+ + 	u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
+ + 	int idx;
+ + 
+ + 	idx = cpsw_ale_match_addr(ale, addr, vid);
+ + 	if (idx < 0)
+ + 		return -ENOENT;
+ + 
+ + 	cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
+ + 	cpsw_ale_write(ale, idx, ale_entry);
+ + 	return 0;
+ + }
+ + 
+ + int cpsw_ale_vlan_add_mcast(struct cpsw_ale *ale, u8 *addr,
+ + 		int port_mask, u16 vid, int super, int mcast_state)
+ + {
+ + 	u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
+ + 	int idx, mask;
+ + 
+ + 	idx = cpsw_ale_match_addr(ale, addr, vid);
+ + 	if (idx >= 0)
+ + 		cpsw_ale_read(ale, idx, ale_entry);
+ + 
+ + 	cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_VLAN_ADDR);
+ + 	cpsw_ale_set_addr(ale_entry, addr);
+ + 	cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2);
+ + 	cpsw_ale_set_vlan_id(ale_entry, vid);
+ + 	cpsw_ale_set_super(ale_entry, super);
+ + 	cpsw_ale_set_mcast_state(ale_entry, mcast_state);
+ + 
+ + 	mask = cpsw_ale_get_port_mask(ale_entry);
+ + 	port_mask |= mask;
+ + 	cpsw_ale_set_port_mask(ale_entry, port_mask);
+ + 
+ + 	if (idx < 0)
+ + 		idx = cpsw_ale_match_free(ale);
+ + 	if (idx < 0)
+ + 		idx = cpsw_ale_find_ageable(ale);
+ + 	if (idx < 0)
+ + 		return -ENOMEM;
+ + 
+ + 	cpsw_ale_write(ale, idx, ale_entry);
+ + 	return 0;
+ + }
+ + 
+ + int cpsw_ale_vlan_del_mcast(struct cpsw_ale *ale, u8 *addr,
+ + 				int port_mask, u16 vid)
+ + {
+ + 	u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
+ + 	int idx;
+ + 
+ + 	idx = cpsw_ale_match_addr(ale, addr, vid);
+ + 	if (idx < 0)
+ + 		return -EINVAL;
+ + 
+ + 	cpsw_ale_read(ale, idx, ale_entry);
+ + 
+ + 	if (port_mask)
+ + 		cpsw_ale_set_port_mask(ale_entry, port_mask);
+ + 	else
+ + 		cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
+ + 
+ + 	cpsw_ale_write(ale, idx, ale_entry);
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL_GPL(cpsw_ale_del_mcast);
+ + 
+ + struct ale_control_info {
+ + 	const char	*name;
+ + 	int		offset, port_offset;
+ + 	int		shift, port_shift;
+ + 	int		bits;
+ + };
+ + 
+ + #define CTRL_GLOBAL(name, bit)		{#name, ALE_CONTROL, 0, bit, 0, 1}
+ + #define CTRL_UNK(name, shift)		{#name, ALE_UNKNOWNVLAN, 0, shift, 0, 6}
+ + #define CTRL_PORTCTL(name, start, bits)	{#name, ALE_PORTCTL, 4, start, 0, bits}
+ + 
+ + static struct ale_control_info ale_controls[] = {
+ + 	[ALE_ENABLE]		= CTRL_GLOBAL(enable, 31),
+ + 	[ALE_CLEAR]		= CTRL_GLOBAL(clear, 30),
+ + 	[ALE_AGEOUT]		= CTRL_GLOBAL(ageout, 29),
+ + 	[ALE_P0_UNI_FLOOD]	= CTRL_GLOBAL(p0_uni_flood, 8),
+ + 	[ALE_VLAN_NOLEARN]	= CTRL_GLOBAL(vlan_nolearn, 7),
+ + 	[ALE_NO_PORT_VLAN]	= CTRL_GLOBAL(no_port_vlan, 6),
+ + 	[ALE_OUI_DENY]		= CTRL_GLOBAL(oui_deny, 5),
+ + 	[ALE_BYPASS]		= CTRL_GLOBAL(bypass, 4),
+ + 	[ALE_RATE_LIMIT_TX]	= CTRL_GLOBAL(rate_limit_tx, 3),
+ + 	[ALE_VLAN_AWARE]	= CTRL_GLOBAL(vlan_aware, 2),
+ + 	[ALE_AUTH_ENABLE]	= CTRL_GLOBAL(auth_enable, 1),
+ + 	[ALE_RATE_LIMIT]	= CTRL_GLOBAL(rate_limit, 0),
+ + 
+ + 	[ALE_PORT_STATE]	     = CTRL_PORTCTL(port_state, 0, 2),
+ + 	[ALE_PORT_DROP_UNTAGGED]     = CTRL_PORTCTL(drop_untagged, 2, 1),
+ + 	[ALE_PORT_DROP_UNKNOWN_VLAN] = CTRL_PORTCTL(drop_unknown, 3, 1),
+ + 	[ALE_PORT_NOLEARN]	     = CTRL_PORTCTL(nolearn, 4, 1),
+ + 	[ALE_PORT_NO_SA_UPDATE]	     = CTRL_PORTCTL(nolearn, 5, 1),
+ + 	[ALE_PORT_MCAST_LIMIT]	     = CTRL_PORTCTL(mcast_limit, 16, 8),
+ + 	[ALE_PORT_BCAST_LIMIT]	     = CTRL_PORTCTL(bcast_limit, 24, 8),
+ + 
+ + 	[ALE_PORT_UNKNOWN_VLAN_MEMBER]	   = CTRL_UNK(unknown_vlan_member, 0),
+ + 	[ALE_PORT_UNKNOWN_MCAST_FLOOD]	   = CTRL_UNK(unknown_mcast_flood, 8),
+ + 	[ALE_PORT_UNKNOWN_REG_MCAST_FLOOD] = CTRL_UNK(unknown_reg_flood, 16),
+ + 	[ALE_PORT_UNTAGGED_EGRESS]	   = CTRL_UNK(untagged_egress, 24),
+ + };
+ + 
+ + int cpsw_ale_control_set(struct cpsw_ale *ale, int port, int control,
+ + 			 int value)
+ + {
+ + 	struct ale_control_info *info = &ale_controls[control];
+ + 	int offset, shift;
+ + 	u32 tmp, mask;
+ + 
+ + 	if (control < 0 || control >= ARRAY_SIZE(ale_controls))
+ + 		return -EINVAL;
+ + 
+ + 	if (info->port_offset == 0 && info->port_shift == 0)
+ + 		port = 0; /* global, port is a dont care */
+ + 
+ + 	if (port < 0 || port > ale->ale_ports)
+ + 		return -EINVAL;
+ + 
+ + 	mask = BITMASK(info->bits);
+ + 	if (value & ~mask)
+ + 		return -EINVAL;
+ + 
+ + 	offset = info->offset + (port * info->port_offset);
+ + 	shift  = info->shift  + (port * info->port_shift);
+ + 
+ + 	tmp = __raw_readl(ale->ale_regs + offset);
+ + 	tmp = (tmp & ~(mask << shift)) | (value << shift);
+ + 	__raw_writel(tmp, ale->ale_regs + offset);
+ + 
+ + 	{
+ + 		volatile u32 dly = 10000;
+ + 		while (dly--)
+ + 			;
+ + 	}
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL_GPL(cpsw_ale_control_set);
+ + 
+ + int cpsw_ale_control_get(struct cpsw_ale *ale, int port, int control)
+ + {
+ + 	struct ale_control_info *info = &ale_controls[control];
+ + 	int offset, shift;
+ + 	u32 tmp;
+ + 
+ + 	if (control < 0 || control >= ARRAY_SIZE(ale_controls))
+ + 		return -EINVAL;
+ + 
+ + 	if (info->port_offset == 0 && info->port_shift == 0)
+ + 		port = 0; /* global, port is a dont care */
+ + 
+ + 	if (port < 0 || port > ale->ale_ports)
+ + 		return -EINVAL;
+ + 
+ + 	offset = info->offset + (port * info->port_offset);
+ + 	shift  = info->shift  + (port * info->port_shift);
+ + 
+ + 	tmp = __raw_readl(ale->ale_regs + offset) >> shift;
+ + 	return tmp & BITMASK(info->bits);
+ + }
+ + EXPORT_SYMBOL_GPL(cpsw_ale_control_get);
+ + 
+ + static ssize_t cpsw_ale_control_show(struct device *dev,
+ + 				     struct device_attribute *attr,
+ + 				     char *buf)
+ + {
+ + 	int i, port, len = 0;
+ + 	struct ale_control_info *info;
+ + 	struct cpsw_ale *ale = control_attr_to_ale(attr);
+ + 
+ + 	for (i = 0, info = ale_controls; i < ALE_NUM_CONTROLS; i++, info++) {
+ + 		/* global controls */
+ + 		if (info->port_shift == 0 &&  info->port_offset == 0) {
+ + 			len += snprintf(buf + len, SZ_4K - len,
+ + 					"%s=%d\n", info->name,
+ + 					cpsw_ale_control_get(ale, 0, i));
+ + 			continue;
+ + 		}
+ + 		/* port specific controls */
+ + 		for (port = 0; port < ale->ale_ports; port++) {
+ + 			len += snprintf(buf + len, SZ_4K - len,
+ + 					"%s.%d=%d\n", info->name, port,
+ + 					cpsw_ale_control_get(ale, port, i));
+ + 		}
+ + 	}
+ + 	return len;
+ + }
+ + 
+ + static ssize_t cpsw_ale_control_store(struct device *dev,
+ + 				      struct device_attribute *attr,
+ + 				      const char *buf, size_t count)
+ + {
+ + 	char ctrl_str[33], *end;
+ + 	int port = 0, value, len, ret, control;
+ + 	struct cpsw_ale *ale = control_attr_to_ale(attr);
+ + 
+ + 	len = strcspn(buf, ".=");
+ + 	if (len >= 32)
+ + 		return -ENOMEM;
+ + 	strncpy(ctrl_str, buf, len);
+ + 	ctrl_str[len] = '\0';
+ + 	buf += len;
+ + 
+ + 	if (*buf == '.') {
+ + 		port = simple_strtoul(buf + 1, &end, 0);
+ + 		buf = end;
+ + 	}
+ + 
+ + 	if (*buf != '=')
+ + 		return -EINVAL;
+ + 
+ + 	value = simple_strtoul(buf + 1, NULL, 0);
+ + 
+ + 	for (control = 0; control < ALE_NUM_CONTROLS; control++)
+ + 		if (strcmp(ctrl_str, ale_controls[control].name) == 0)
+ + 			break;
+ + 
+ + 	if (control >= ALE_NUM_CONTROLS)
+ + 		return -ENOENT;
+ + 
+ + 	dev_dbg(ale->params.dev, "processing command %s.%d=%d\n",
+ + 		ale_controls[control].name, port, value);
+ + 
+ + 	ret = cpsw_ale_control_set(ale, port, control, value);
+ + 	if (ret < 0)
+ + 		return ret;
+ + 	return count;
+ + }
+ + 
+ + DEVICE_ATTR(ale_control, S_IRUGO | S_IWUSR, cpsw_ale_control_show,
+ + 	    cpsw_ale_control_store);
+ + 
+ + static ssize_t cpsw_ale_table_show(struct device *dev,
+ + 				   struct device_attribute *attr,
+ + 				   char *buf)
+ + {
+ + 	int len = SZ_4K, outlen = 0, idx;
+ + 	u32 ale_entry[ALE_ENTRY_WORDS];
+ + 	struct cpsw_ale *ale = table_attr_to_ale(attr);
+ + 
+ + 	for (idx = 0; idx < ale->ale_entries; idx++) {
+ + 		cpsw_ale_read(ale, idx, ale_entry);
+ + 		outlen += cpsw_ale_dump_entry(idx, ale_entry, buf + outlen,
+ + 					      len - outlen);
+ + 	}
+ + 	return outlen;
+ + }
+ + DEVICE_ATTR(ale_table, S_IRUGO, cpsw_ale_table_show, NULL);
+ + 
+ + static void cpsw_ale_timer(unsigned long arg)
+ + {
+ + 	struct cpsw_ale *ale = (struct cpsw_ale *)arg;
+ + 
+ + 	cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
+ + 
+ + 	if (ale->ageout) {
+ + 		ale->timer.expires = jiffies + ale->ageout;
+ + 		add_timer(&ale->timer);
+ + 	}
+ + }
+ + 
+ + int cpsw_ale_set_ageout(struct cpsw_ale *ale, int ageout)
+ + {
+ + 	del_timer_sync(&ale->timer);
+ + 	ale->ageout = ageout * HZ;
+ + 	if (ale->ageout) {
+ + 		ale->timer.expires = jiffies + ale->ageout;
+ + 		add_timer(&ale->timer);
+ + 	}
+ + 	return 0;
+ + }
+ + 
+ + void cpsw_ale_start(struct cpsw_ale *ale)
+ + {
+ + 	u32 rev;
+ + 	int ret;
+ + 
+ + 	rev = __raw_readl(ale->ale_regs + ALE_IDVER);
+ + 	dev_dbg(ale->params.dev, "initialized cpsw ale revision %d.%d\n",
+ + 		(rev >> 8) & 0xff, rev & 0xff);
+ + 	cpsw_ale_control_set(ale, 0, ALE_ENABLE, 1);
+ + 	cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1);
+ + 
+ + 	ale->ale_control_attr = dev_attr_ale_control;
+ + 	sysfs_attr_init(&ale->ale_control_attr.attr);
+ + 	ret = device_create_file(ale->params.dev, &ale->ale_control_attr);
+ + 	WARN_ON(ret < 0);
+ + 
+ + 	ale->ale_table_attr = dev_attr_ale_table;
+ + 	sysfs_attr_init(&ale->ale_table_attr.attr);
+ + 	ret = device_create_file(ale->params.dev, &ale->ale_table_attr);
+ + 	WARN_ON(ret < 0);
+ + 
+ + 	init_timer(&ale->timer);
+ + 	ale->timer.data	    = (unsigned long)ale;
+ + 	ale->timer.function = cpsw_ale_timer;
+ + 	if (ale->ageout) {
+ + 		ale->timer.expires = jiffies + ale->ageout;
+ + 		add_timer(&ale->timer);
+ + 	}
+ + }
+ + EXPORT_SYMBOL_GPL(cpsw_ale_start);
+ + 
+ + void cpsw_ale_stop(struct cpsw_ale *ale)
+ + {
+ + 	cpsw_ale_control_set(ale, 0, ALE_ENABLE, 0);
+ + 	del_timer_sync(&ale->timer);
+ + 	device_remove_file(ale->params.dev, &ale->ale_table_attr);
+ + 	device_remove_file(ale->params.dev, &ale->ale_control_attr);
+ + }
+ + EXPORT_SYMBOL_GPL(cpsw_ale_stop);
+ + 
+ + struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params)
+ + {
+ + 	struct cpsw_ale *ale;
+ + 	int ret;
+ + 
+ + 	ret = -ENOMEM;
+ + 	ale = kzalloc(sizeof(*ale), GFP_KERNEL);
+ + 	if (WARN_ON(!ale))
+ + 		return NULL;
+ + 
+ + 	ale->params = *params;
+ + 	ale->ageout = ale->params.ale_ageout * HZ;
+ + 
+ + 	return ale;
+ + }
+ + EXPORT_SYMBOL_GPL(cpsw_ale_create);
+ + 
+ + int cpsw_ale_destroy(struct cpsw_ale *ale)
+ + {
+ + 	if (!ale)
+ + 		return -EINVAL;
+ + 	cpsw_ale_stop(ale);
+ + 	cpsw_ale_control_set(ale, 0, ALE_ENABLE, 0);
+ + 	kfree(ale);
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL_GPL(cpsw_ale_destroy);
+ + 
+ + MODULE_DESCRIPTION("Ethernet Switch Address Lookup Engine driver");
+ + MODULE_AUTHOR("Chandan Nath <chandan.nath@ti.com>");
+ + MODULE_LICENSE("GPL");
+ diff -crN linux-3.2.1_o/drivers/net/ethernet/ti/cpsw_ale.h linux-3.2.1/drivers/net/ethernet/ti/cpsw_ale.h
+ *** linux-3.2.1_o/drivers/net/ethernet/ti/cpsw_ale.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/drivers/net/ethernet/ti/cpsw_ale.h	2014-11-25 13:19:15.764047143 +0900
+ ***************
+ *** 0 ****
+ --- 1,114 ----
+ + /*
+ +  * Texas Instruments 3-Port Ethernet Switch Address Lookup Engine APIs
+ +  *
+ +  * Copyright (C) 2010 Texas Instruments
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + #ifndef __TI_CPSW_ALE_H__
+ + #define __TI_CPSW_ALE_H__
+ + 
+ + struct cpsw_ale_params {
+ + 	struct device		*dev;
+ + 	void __iomem		*ale_regs;
+ + 	unsigned long		ale_ageout;	/* in secs */
+ + 	unsigned long		ale_entries;
+ + 	unsigned long		ale_ports;
+ + };
+ + 
+ + struct cpsw_ale {
+ + 	struct cpsw_ale_params	params;
+ + 	struct timer_list	timer;
+ + 	unsigned long		ageout;
+ + 	struct device_attribute ale_control_attr;
+ + #define control_attr_to_ale(attr)	\
+ + 	container_of(attr, struct cpsw_ale, ale_control_attr);
+ + 	struct device_attribute ale_table_attr;
+ + #define table_attr_to_ale(attr)		\
+ + 	container_of(attr, struct cpsw_ale, ale_table_attr);
+ + };
+ + 
+ + enum cpsw_ale_control {
+ + 	/* global */
+ + 	ALE_ENABLE,
+ + 	ALE_CLEAR,
+ + 	ALE_AGEOUT,
+ + 	ALE_P0_UNI_FLOOD,
+ + 	ALE_VLAN_NOLEARN,
+ + 	ALE_NO_PORT_VLAN,
+ + 	ALE_OUI_DENY,
+ + 	ALE_BYPASS,
+ + 	ALE_RATE_LIMIT_TX,
+ + 	ALE_VLAN_AWARE,
+ + 	ALE_AUTH_ENABLE,
+ + 	ALE_RATE_LIMIT,
+ + 	/* port controls */
+ + 	ALE_PORT_STATE,
+ + 	ALE_PORT_DROP_UNTAGGED,
+ + 	ALE_PORT_DROP_UNKNOWN_VLAN,
+ + 	ALE_PORT_NOLEARN,
+ + 	ALE_PORT_NO_SA_UPDATE,
+ + 	ALE_PORT_UNKNOWN_VLAN_MEMBER,
+ + 	ALE_PORT_UNKNOWN_MCAST_FLOOD,
+ + 	ALE_PORT_UNKNOWN_REG_MCAST_FLOOD,
+ + 	ALE_PORT_UNTAGGED_EGRESS,
+ + 	ALE_PORT_BCAST_LIMIT,
+ + 	ALE_PORT_MCAST_LIMIT,
+ + 	ALE_NUM_CONTROLS,
+ + };
+ + 
+ + enum cpsw_ale_port_state {
+ + 	ALE_PORT_STATE_DISABLE	= 0x00,
+ + 	ALE_PORT_STATE_BLOCK	= 0x01,
+ + 	ALE_PORT_STATE_LEARN	= 0x02,
+ + 	ALE_PORT_STATE_FORWARD	= 0x03,
+ + };
+ + 
+ + /* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */
+ + #define ALE_SECURE	1
+ + #define ALE_BLOCKED	2
+ + 
+ + struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params);
+ + int cpsw_ale_destroy(struct cpsw_ale *ale);
+ + 
+ + void cpsw_ale_start(struct cpsw_ale *ale);
+ + void cpsw_ale_stop(struct cpsw_ale *ale);
+ + 
+ + int cpsw_ale_set_ageout(struct cpsw_ale *ale, int ageout);
+ + int cpsw_ale_flush(struct cpsw_ale *ale, int port_mask);
+ + int cpsw_ale_add_ucast(struct cpsw_ale *ale, u8 *addr, int port, int flags);
+ + int cpsw_ale_del_ucast(struct cpsw_ale *ale, u8 *addr, int port);
+ + int cpsw_ale_add_mcast(struct cpsw_ale *ale, u8 *addr, int port_mask,
+ + 			int super, int mcast_state);
+ + int cpsw_ale_del_mcast(struct cpsw_ale *ale, u8 *addr, int port_mask);
+ + int cpsw_ale_add_vlan(struct cpsw_ale *ale, u16 vid, int port, int untag,
+ + 			int reg_mcast, int unreg_mcast);
+ + int cpsw_ale_del_vlan(struct cpsw_ale *ale, u16 vid, int port);
+ + int cpsw_ale_vlan_add_ucast(struct cpsw_ale *ale, u8 *addr, int port,
+ + 			int flags, u16 vid);
+ + int cpsw_ale_vlan_del_ucast(struct cpsw_ale *ale, u8 *addr, int port,
+ + 			u16 vid);
+ + int cpsw_ale_vlan_add_mcast(struct cpsw_ale *ale, u8 *addr, int port_mask,
+ + 			u16 vid, int super, int mcast_state);
+ + int cpsw_ale_vlan_del_mcast(struct cpsw_ale *ale, u8 *addr, int port_mask,
+ + 			u16 vid);
+ + 
+ + int cpsw_ale_control_get(struct cpsw_ale *ale, int port, int control);
+ + int cpsw_ale_control_set(struct cpsw_ale *ale, int port,
+ + 			 int control, int value);
+ + int cpsw_ale_flush_multicast(struct cpsw_ale *ale, int port_mask);
+ + void cpsw_ale_flush_vlan_multicast(struct cpsw_ale *ale, u16 vid,
+ + 				   int port_mask);
+ + int cpsw_ale_dump(struct cpsw_ale *ale, int index, char *buf, int len);
+ + int cpsw_ale_match_addr(struct cpsw_ale *ale, u8* addr, u16 vid);
+ + int cpsw_ale_match_vlan(struct cpsw_ale *ale, u16 vid);
+ + int cpsw_ale_add_oui(struct cpsw_ale *ale, u8 *addr);
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/drivers/net/ethernet/ti/cpsw.c linux-3.2.1/drivers/net/ethernet/ti/cpsw.c
+ *** linux-3.2.1_o/drivers/net/ethernet/ti/cpsw.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/drivers/net/ethernet/ti/cpsw.c	2014-11-25 13:19:15.773030210 +0900
+ ***************
+ *** 0 ****
+ --- 1,2969 ----
+ + /*
+ +  * Texas Instruments Ethernet Switch Driver
+ +  *
+ +  * Copyright (C) 2010 Texas Instruments
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + #include <linux/kernel.h>
+ + #include <linux/io.h>
+ + #include <linux/clk.h>
+ + #include <linux/timer.h>
+ + #include <linux/module.h>
+ + #include <linux/platform_device.h>
+ + #include <linux/if_ether.h>
+ + #include <linux/etherdevice.h>
+ + #include <linux/ethtool.h>
+ + #include <linux/netdevice.h>
+ + #include <linux/net_tstamp.h>
+ + #include <linux/phy.h>
+ + #include <linux/workqueue.h>
+ + #include <linux/delay.h>
+ + #include <linux/interrupt.h>
+ + #include <linux/pm_runtime.h>
+ + #include <linux/if_vlan.h>
+ + #include <linux/net_switch_config.h>
+ + 
+ + #include <linux/cpsw.h>
+ + #include <plat/dmtimer.h>
+ + #include "cpsw_ale.h"
+ + #include "cpts.h"
+ + #include "davinci_cpdma.h"
+ + 
+ + 
+ + #define CPSW_DEBUG	(NETIF_MSG_HW		| NETIF_MSG_WOL		| \
+ + 			 NETIF_MSG_DRV		| NETIF_MSG_LINK	| \
+ + 			 NETIF_MSG_IFUP		| NETIF_MSG_INTR	| \
+ + 			 NETIF_MSG_PROBE	| NETIF_MSG_TIMER	| \
+ + 			 NETIF_MSG_IFDOWN	| NETIF_MSG_RX_ERR	| \
+ + 			 NETIF_MSG_TX_ERR	| NETIF_MSG_TX_DONE	| \
+ + 			 NETIF_MSG_PKTDATA	| NETIF_MSG_TX_QUEUED	| \
+ + 			 NETIF_MSG_RX_STATUS)
+ + 
+ + #define msg(level, type, format, ...)				\
+ + do {								\
+ + 	if (netif_msg_##type(priv) && net_ratelimit())		\
+ + 		dev_##level(priv->dev, format, ## __VA_ARGS__);	\
+ + } while (0)
+ + 
+ + #define CPSW_VERSION1		0x19010a
+ + #define CPSW_VERSION2		0x19010c
+ + #define CPDMA_RXTHRESH		0x0c0
+ + #define CPDMA_RXFREE		0x0e0
+ + #define CPDMA_TXHDP_VER1	0x100
+ + #define CPDMA_TXHDP_VER2	0x200
+ + #define CPDMA_RXHDP_VER1	0x120
+ + #define CPDMA_RXHDP_VER2	0x220
+ + #define CPDMA_TXCP_VER1		0x140
+ + #define CPDMA_TXCP_VER2		0x240
+ + #define CPDMA_RXCP_VER1		0x160
+ + #define CPDMA_RXCP_VER2		0x260
+ + 
+ + #define CPSW_POLL_WEIGHT	64
+ + #define CPSW_MIN_PACKET_SIZE	60
+ + #define CPSW_MAX_PACKET_SIZE	(1500 + 14 + 4 + 4)
+ + #define CPSW_PHY_SPEED		1000
+ + 
+ + #define CPSW_PRIMAP(shift, priority)	(priority << (shift * 4))
+ + 
+ + #define slave(priv, idx)	((priv)->slaves + idx)
+ + #define switchcmd(__cmd__)	((__cmd__)->cmd_data.switchcmd)
+ + #define portcmd(__cmd__)	((__cmd__)->cmd_data.portcmd)
+ + #define priocmd(__cmd__)	((__cmd__)->cmd_data.priocmd)
+ + 
+ + /* CPSW control module masks */
+ + #define CPSW_INTPACEEN		(0x3 << 16)
+ + #define CPSW_INTPRESCALE_MASK	(0x7FF << 0)
+ + #define CPSW_CMINTMAX_CNT	63
+ + #define CPSW_CMINTMIN_CNT	2
+ + #define CPSW_CMINTMAX_INTVL	(1000 / CPSW_CMINTMIN_CNT)
+ + #define CPSW_CMINTMIN_INTVL	((1000 / CPSW_CMINTMAX_CNT) + 1)
+ + 
+ + #define cpsw_enable_irq(priv)	\
+ + 	do {			\
+ + 		u32 i;		\
+ + 		for (i = 0; i < priv->num_irqs; i++) \
+ + 			enable_irq(priv->irqs_table[i]); \
+ + 	} while (0);
+ + #define cpsw_disable_irq(priv)	\
+ + 	do {			\
+ + 		u32 i;		\
+ + 		for (i = 0; i < priv->num_irqs; i++) \
+ + 			disable_irq_nosync(priv->irqs_table[i]); \
+ + 	} while (0);
+ + 
+ + #define ALE_ALL_PORTS		0x7
+ + 
+ + #define CPSW_CPDMA_EOI_REG	0x894
+ + #define CPSW_TIMER_MASK		0xA0908
+ + #define CPSW_TIMER_CAP_REG	0xFD0
+ + #define CPSW_RX_TIMER_REQ	5
+ + #define CPSW_TX_TIMER_REQ	6
+ + 
+ + /* CPSW_PORT_V1 */
+ + #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
+ + #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
+ + #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
+ + #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
+ + #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
+ + #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
+ + #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
+ + #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
+ + 
+ + /* CPSW_PORT_V2 */
+ + #define CPSW2_CONTROL       0x00 /* Control Register */
+ + #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
+ + #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
+ + #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
+ + #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
+ + #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
+ + #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
+ + 
+ + /* CPSW_PORT_V1 and V2 */
+ + #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
+ + #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
+ + #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
+ + 
+ + /* CPSW_PORT_V2 only */
+ + #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
+ + #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
+ + #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
+ + #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
+ + #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
+ + #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
+ + #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
+ + #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
+ + 
+ + /* Bit definitions for the CPSW2_CONTROL register */
+ + #define PASS_PRI_TAGGED     (1<<24) /* Pass Priority Tagged */
+ + #define VLAN_LTYPE2_EN      (1<<21) /* VLAN LTYPE 2 enable */
+ + #define VLAN_LTYPE1_EN      (1<<20) /* VLAN LTYPE 1 enable */
+ + #define DSCP_PRI_EN         (1<<16) /* DSCP Priority Enable */
+ + #define TS_320              (1<<14) /* Time Sync Dest Port 320 enable */
+ + #define TS_319              (1<<13) /* Time Sync Dest Port 319 enable */
+ + #define TS_132              (1<<12) /* Time Sync Dest IP Addr 132 enable */
+ + #define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
+ + #define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
+ + #define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
+ + #define TS_BIT8             (1<<8)  /* ts_ttl_nonzero? */
+ + #define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
+ + #define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
+ + #define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
+ + #define TS_TX_EN            (1<<1)  /* Time Sync Transmit Enable */
+ + #define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
+ + 
+ + #define CTRL_TS_BITS \
+ + 	(TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \
+ + 	 TS_ANNEX_D_EN | TS_LTYPE1_EN)
+ + 
+ + #define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN)
+ + #define CTRL_TX_TS_BITS  (CTRL_TS_BITS | TS_TX_EN)
+ + #define CTRL_RX_TS_BITS  (CTRL_TS_BITS | TS_RX_EN)
+ + 
+ + /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
+ + #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
+ + #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
+ + #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
+ + #define TS_MSG_TYPE_EN_MASK      (0xffff)
+ + 
+ + /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
+ + #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
+ + 
+ + /* Bit definitions for the CPSW1_TS_CTL register */
+ + #define CPSW_V1_TS_RX_EN		BIT(0)
+ + #define CPSW_V1_TS_TX_EN		BIT(4)
+ + #define CPSW_V1_MSG_TYPE_OFS		16
+ + 
+ + /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
+ + #define CPSW_V1_SEQ_ID_OFS_SHIFT	16
+ + 
+ + #ifdef CONFIG_TI_CPSW_DUAL_EMAC
+ + 
+ + /* Enable VLAN aware mode to add VLAN for induvudual interface */
+ + #define CPSW_VLAN_AWARE_MODE
+ + 
+ + #define cpsw_get_slave_ndev(priv, __slave_no__)		\
+ + 	(priv->slaves[__slave_no__].ndev)
+ + #define cpsw_get_slave_priv(priv, __slave_no__)		\
+ + 	netdev_priv(priv->slaves[__slave_no__].ndev)
+ + #define for_each_slave(priv, func, arg...)			\
+ + 	do {							\
+ + 		(func)((priv)->slaves + priv->emac_port, ##arg);\
+ + 	} while (0)
+ + #define cpsw_dual_emac_source_port_detect(status, priv, ndev, skb)	\
+ + 	do {								\
+ + 		if (CPDMA_RX_SOURCE_PORT(status) == 1) {		\
+ + 			ndev = cpsw_get_slave_ndev(priv, 0);		\
+ + 			priv = netdev_priv(ndev);			\
+ + 			skb->dev = ndev;				\
+ + 		} else if (CPDMA_RX_SOURCE_PORT(status) == 2) {		\
+ + 			ndev = cpsw_get_slave_ndev(priv, 1);		\
+ + 			priv = netdev_priv(ndev);			\
+ + 			skb->dev = ndev;				\
+ + 		}							\
+ + 	} while (0)
+ + #define cpsw_add_switch_mode_bcast_ale_entries(priv, slave_port)
+ + #define cpsw_update_slave_open_state(priv, state)		\
+ + 	priv->slaves[priv->emac_port].open_stat = state;
+ + #define cpsw_slave_phy_index(priv)	((priv)->emac_port)
+ + 
+ + #else	/* CONFIG_TI_CPSW_DUAL_EMAC */
+ + 
+ + #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
+ + #define VLAN_SUPPORT
+ + #define CPSW_VLAN_AWARE_MODE
+ + #endif
+ + 
+ + #define cpsw_get_slave_ndev(priv, __slave_no__)		NULL
+ + #define cpsw_get_slave_priv(priv, __slave_no__)		NULL
+ + #define for_each_slave(priv, func, arg...)			\
+ + 	do {							\
+ + 		int idx;					\
+ + 		for (idx = 0; idx < (priv)->data.slaves; idx++)	\
+ + 			(func)((priv)->slaves + idx, ##arg);	\
+ + 	} while (0)
+ + #define cpsw_dual_emac_source_port_detect(status, priv, ndev, skb)
+ + #define cpsw_add_switch_mode_bcast_ale_entries(priv, slave_port)	\
+ + 	cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,		\
+ + 			   1 << slave_port, 0, 0)
+ + #define cpsw_update_slave_open_state(priv, state)
+ + #define cpsw_slave_phy_index(priv)	((priv)->data.ethtool_slave)
+ + 
+ + #endif	/* CONFIG_TI_CPSW_DUAL_EMAC */
+ + 
+ + #ifdef CPSW_VLAN_AWARE_MODE
+ + #define CPSW_VLAN_AWARE		BIT(1)
+ + #define CPSW_ALE_VLAN_AWARE	1
+ + #else
+ + #define CPSW_VLAN_AWARE		0x0
+ + #define CPSW_ALE_VLAN_AWARE	0
+ + #endif
+ + 
+ + struct omap_dm_timer *dmtimer_rx;
+ + struct omap_dm_timer *dmtimer_tx;
+ + 
+ + extern u32 omap_ctrl_readl(u16 offset);
+ + extern void omap_ctrl_writel(u32 val, u16 offset);
+ + 
+ + static int debug_level;
+ + module_param(debug_level, int, 0);
+ + MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
+ + 
+ + static int ale_ageout = 10;
+ + module_param(ale_ageout, int, 0);
+ + MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
+ + 
+ + static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
+ + module_param(rx_packet_max, int, 0);
+ + MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
+ + 
+ + struct cpsw_wr_regs {
+ + 	u32	id_ver;
+ + 	u32	soft_reset;
+ + 	u32	control;
+ + 	u32	int_control;
+ + 	u32	rx_thresh_en;
+ + 	u32	rx_en;
+ + 	u32	tx_en;
+ + 	u32	misc_en;
+ + 	u32	mem_allign1[8];
+ + 	u32	rx_thresh_stat;
+ + 	u32	rx_stat;
+ + 	u32	tx_stat;
+ + 	u32	misc_stat;
+ + 	u32	mem_allign2[8];
+ + 	u32	rx_imax;
+ + 	u32	tx_imax;
+ + };
+ + 
+ + struct cpsw_ss_regs {
+ + 	u32	id_ver;
+ + 	u32	control;
+ + 	u32	soft_reset;
+ + 	u32	stat_port_en;
+ + 	u32	ptype;
+ + 	u32	soft_idle;
+ + 	u32	thru_rate;
+ + 	u32	gap_thresh;
+ + 	u32	tx_start_wds;
+ + 	u32	flow_control;
+ + 	u32	vlan_ltype;
+ + 	u32	ts_ltype;
+ + 	u32	dlr_ltype;
+ + };
+ + 
+ + struct cpsw_host_regs {
+ + 	u32	max_blks;
+ + 	u32	blk_cnt;
+ + 	u32	flow_thresh;
+ + 	u32	port_vlan;
+ + 	u32	tx_pri_map;
+ + 	u32	cpdma_tx_pri_map;
+ + 	u32	cpdma_rx_chan_map;
+ + };
+ + 
+ + struct cpsw_sliver_regs {
+ + 	u32	id_ver;
+ + 	u32	mac_control;
+ + 	u32	mac_status;
+ + 	u32	soft_reset;
+ + 	u32	rx_maxlen;
+ + 	u32	__reserved_0;
+ + 	u32	rx_pause;
+ + 	u32	tx_pause;
+ + 	u32	__reserved_1;
+ + 	u32	rx_pri_map;
+ + };
+ + 
+ + struct cpsw_hw_stats {
+ + 	u32	rxgoodframes;
+ + 	u32	rxbroadcastframes;
+ + 	u32	rxmulticastframes;
+ + 	u32	rxpauseframes;
+ + 	u32	rxcrcerrors;
+ + 	u32	rxaligncodeerrors;
+ + 	u32	rxoversizedframes;
+ + 	u32	rxjabberframes;
+ + 	u32	rxundersizedframes;
+ + 	u32	rxfragments;
+ + 	u32	__pad_0[2];
+ + 	u32	rxoctets;
+ + 	u32	txgoodframes;
+ + 	u32	txbroadcastframes;
+ + 	u32	txmulticastframes;
+ + 	u32	txpauseframes;
+ + 	u32	txdeferredframes;
+ + 	u32	txcollisionframes;
+ + 	u32	txsinglecollframes;
+ + 	u32	txmultcollframes;
+ + 	u32	txexcessivecollisions;
+ + 	u32	txlatecollisions;
+ + 	u32	txunderrun;
+ + 	u32	txcarriersenseerrors;
+ + 	u32	txoctets;
+ + 	u32	octetframes64;
+ + 	u32	octetframes65t127;
+ + 	u32	octetframes128t255;
+ + 	u32	octetframes256t511;
+ + 	u32	octetframes512t1023;
+ + 	u32	octetframes1024tup;
+ + 	u32	netoctets;
+ + 	u32	rxsofoverruns;
+ + 	u32	rxmofoverruns;
+ + 	u32	rxdmaoverruns;
+ + };
+ + 
+ + struct cpsw_slave {
+ + 	void __iomem			*regs;
+ + 	struct cpsw_sliver_regs __iomem	*sliver;
+ + 	int				slave_num;
+ + 	u32				mac_control;
+ + 	struct cpsw_slave_data		*data;
+ + 	struct phy_device		*phy;
+ + 	u32				port_vlan;
+ + 	struct net_device		*ndev;
+ + 	u32				open_stat;
+ + };
+ + 
+ + struct cpsw_priv {
+ + 	spinlock_t			lock;
+ + 	struct platform_device		*pdev;
+ + 	struct net_device		*ndev;
+ + 	struct resource			*cpsw_res;
+ + 	struct resource			*cpsw_ss_res;
+ + 	struct napi_struct		napi;
+ + #define napi_to_priv(napi)	container_of(napi, struct cpsw_priv, napi)
+ + 	struct device			*dev;
+ + 	struct cpsw_platform_data	data;
+ + 	struct cpsw_ss_regs __iomem	*regs;
+ + 	struct cpsw_wr_regs __iomem	*wr_regs;
+ + 	struct cpsw_hw_stats __iomem	*hw_stats;
+ + 	struct cpsw_host_regs __iomem	*host_port_regs;
+ + 	u32				msg_enable;
+ + 	u32				version;
+ + 	u32				coal_intvl;
+ + 	u32				bus_freq_mhz;
+ + 	struct net_device_stats		stats;
+ + 	int				rx_packet_max;
+ + 	int				host_port;
+ + 	struct clk			*clk;
+ + 	u8				mac_addr[ETH_ALEN];
+ + 	struct cpsw_slave		*slaves;
+ + 	struct cpdma_ctlr		*dma;
+ + 	struct cpdma_chan		*txch, *rxch;
+ + 	struct cpsw_ale			*ale;
+ + 	u32				emac_port;
+ + 	u8				port_state[3];
+ + 	/* snapshot of IRQ numbers */
+ + 	u32 irqs_table[4];
+ + 	u32 num_irqs;
+ + 	struct cpts *cpts;
+ + 	void (*save_mac_addr) (char *);		/* function for saving MAC address */
+ + };
+ + 
+ + static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
+ + {
+ + 	return readl(slave->regs + offset);
+ + }
+ + 
+ + static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
+ + {
+ + 	writel(val, slave->regs + offset);
+ + }
+ + 
+ + #ifdef CONFIG_TI_CPTS
+ + 
+ + static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
+ + {
+ + 	struct cpsw_slave *slave = &priv->slaves[priv->data.cpts_active_slave];
+ + 	u32 ts_en, seq_id;
+ + 
+ + 	if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
+ + 		slave_write(slave, 0, CPSW1_TS_CTL);
+ + 		return;
+ + 	}
+ + 
+ + 	seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
+ + 	ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
+ + 
+ + 	if (priv->cpts->tx_enable)
+ + 		ts_en |= CPSW_V1_TS_TX_EN;
+ + 
+ + 	if (priv->cpts->rx_enable)
+ + 		ts_en |= CPSW_V1_TS_RX_EN;
+ + 
+ + 	slave_write(slave, ts_en, CPSW1_TS_CTL);
+ + 	slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
+ + }
+ + 
+ + static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
+ + {
+ + 	struct cpsw_slave *slave = &priv->slaves[priv->data.cpts_active_slave];
+ + 	u32 ctrl, mtype;
+ + 
+ + 	ctrl = slave_read(slave, CPSW2_CONTROL);
+ + 	ctrl &= ~CTRL_ALL_TS_MASK;
+ + 
+ + 	if (priv->cpts->tx_enable)
+ + 		ctrl |= CTRL_TX_TS_BITS;
+ + 
+ + 	if (priv->cpts->rx_enable)
+ + 		ctrl |= CTRL_RX_TS_BITS;
+ + 
+ + 	mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
+ + 
+ + 	slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
+ + 	slave_write(slave, ctrl, CPSW2_CONTROL);
+ + 	__raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
+ + }
+ + 
+ + #ifdef CONFIG_TI_CPSW_DUAL_EMAC
+ + static int cpsw_select_ts_slave_port(struct cpsw_priv *priv)
+ + {
+ + 	if (priv->cpts->tx_enable)
+ + 		return -ENOTSUPP;
+ + 	priv->data.cpts_active_slave = priv->emac_port;
+ + 	return 0;
+ + }
+ + #else
+ + static int cpsw_select_ts_slave_port(struct cpsw_priv *priv)
+ + {
+ + 	return 0;
+ + }
+ + #endif
+ + 
+ + static int cpsw_hwtstamp_ioctl(struct net_device *ndev, struct ifreq *ifr)
+ + {
+ + 	struct cpsw_priv *priv = netdev_priv(ndev);
+ + 	struct cpts *cpts = priv->cpts;
+ + 	struct hwtstamp_config cfg;
+ + 
+ + 	if (cpsw_select_ts_slave_port(priv))
+ + 		return -ENOTSUPP;
+ + 
+ + 	if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
+ + 		return -EFAULT;
+ + 
+ + 	/* reserved for future extensions */
+ + 	if (cfg.flags)
+ + 		return -EINVAL;
+ + 
+ + 	switch (cfg.tx_type) {
+ + 	case HWTSTAMP_TX_OFF:
+ + 		cpts->tx_enable = 0;
+ + 		break;
+ + 	case HWTSTAMP_TX_ON:
+ + 		cpts->tx_enable = 1;
+ + 		break;
+ + 	default:
+ + 		return -ERANGE;
+ + 	}
+ + 
+ + 	switch (cfg.rx_filter) {
+ + 	case HWTSTAMP_FILTER_NONE:
+ + 		cpts->rx_enable = 0;
+ + 		break;
+ + 	case HWTSTAMP_FILTER_ALL:
+ + 	case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
+ + 	case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
+ + 	case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
+ + 		return -ERANGE;
+ + 	case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
+ + 	case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
+ + 	case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
+ + 	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
+ + 	case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
+ + 	case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
+ + 	case HWTSTAMP_FILTER_PTP_V2_EVENT:
+ + 	case HWTSTAMP_FILTER_PTP_V2_SYNC:
+ + 	case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
+ + 		cpts->rx_enable = 1;
+ + 		cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
+ + 		break;
+ + 	default:
+ + 		return -ERANGE;
+ + 	}
+ + 
+ + 	switch (priv->version) {
+ + 	case CPSW_VERSION1:
+ + 		cpsw_hwtstamp_v1(priv);
+ + 		break;
+ + 	case CPSW_VERSION2:
+ + 		cpsw_hwtstamp_v2(priv);
+ + 		break;
+ + 	default:
+ + 		return -ENOTSUPP;
+ + 	}
+ + 
+ + 	return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
+ + }
+ + 
+ + #endif
+ + 
+ + #ifdef CONFIG_TI_CPSW_DUAL_EMAC
+ + 
+ + static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
+ + {
+ + 	struct cpsw_priv *priv = netdev_priv(ndev);
+ + 	struct cpsw_slave *slave = priv->slaves + priv->emac_port;
+ + 
+ + 	/* Clear all mcast from ALE */
+ + 	cpsw_ale_flush_vlan_multicast(priv->ale, slave->port_vlan,
+ + 			1 << (priv->emac_port + 1) | 1 << priv->host_port);
+ + 
+ + 	if (!netdev_mc_empty(ndev)) {
+ + 		struct netdev_hw_addr *ha;
+ + 
+ + 		/* program multicast address list into ALE register */
+ + 		netdev_for_each_mc_addr(ha, ndev) {
+ + 			cpsw_ale_vlan_add_mcast(priv->ale, (u8 *)ha->addr,
+ + 					1 << (priv->emac_port + 1) |
+ + 					1 << priv->host_port,
+ + 					slave->port_vlan, 0, 0);
+ + 		}
+ + 	}
+ + }
+ + 
+ + static void cpsw_ndo_change_rx_flags(struct net_device *ndev, int flags)
+ + {
+ + 	struct cpsw_priv *priv = netdev_priv(ndev);
+ + 	struct cpsw_ale *ale = priv->ale;
+ + 
+ + 	if (flags & IFF_PROMISC) {
+ + 		if ((priv->slaves[0].ndev->flags & IFF_PROMISC) ||
+ + 				(priv->slaves[1].ndev->flags & IFF_PROMISC)) {
+ + 			/*
+ + 			 * Enabling promiscuous mode for one interface will be
+ + 			 * common for both the interface as the interface
+ + 			 * shares the same hardware resource.
+ + 			 */
+ + 
+ + 			/* Enable Bypass */
+ + 			cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
+ + 
+ + 			dev_err(&ndev->dev, "promiscuity enabled\n");
+ + 		} else {
+ + 			/* Disable Bypass */
+ + 			cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
+ + 			dev_err(&ndev->dev, "promiscuity disabled\n");
+ + 		}
+ + 	}
+ + 
+ + 	/*
+ + 	 * The switch cannot filter multicast traffic unless it is configured
+ + 	 * in "VLAN Aware" mode.  Unfortunately, VLAN awareness requires a
+ + 	 * whole bunch of additional logic that this driver does not implement
+ + 	 * at present.
+ + 	 */
+ + 	if ((flags & IFF_ALLMULTI) && !(ndev->flags & IFF_ALLMULTI))
+ + 		dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n");
+ + }
+ + 
+ + static inline void cpsw_p0_fifo_type_select(struct cpsw_priv *priv)
+ + {
+ + 	u32 reg;
+ + 	reg = readl(&priv->host_port_regs->flow_thresh);
+ + 	reg &= ~(0x3 << 16);
+ + 	reg |= 0x1 << 16;
+ + 	writel(reg, &priv->host_port_regs->flow_thresh);
+ + }
+ + 
+ + static inline void cpsw_add_dual_emac_mode_default_ale_entries(
+ + 		struct cpsw_priv *priv, struct cpsw_slave *slave,
+ + 		u32 slave_port)
+ + {
+ + 	if (priv->version == CPSW_VERSION1)
+ + 		slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
+ + 	else
+ + 		slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
+ + 	cpsw_ale_add_vlan(priv->ale, slave->port_vlan,
+ + 		1 << slave_port | 1 << priv->host_port, 0,
+ + 		1 << slave_port | 1 << priv->host_port,
+ + 		1 << slave_port | 1 << priv->host_port);
+ + 	cpsw_ale_vlan_add_mcast(priv->ale,
+ + 		priv->ndev->broadcast,
+ + 		1 << slave_port | 1 << priv->host_port,
+ + 		slave->port_vlan, 0, 0);
+ + 	cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
+ + 		priv->host_port, 0);
+ + 	cpsw_ale_add_vlan(priv->ale, 0,
+ + 		ALE_ALL_PORTS << priv->host_port,
+ + 		ALE_ALL_PORTS << priv->host_port, priv->host_port, 0);
+ + }
+ + 
+ + static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
+ + {
+ + 	u32 i;
+ + 	u32 usage_count = 0;
+ + 
+ + 	for (i = 0; i < priv->data.slaves; i++)
+ + 		if (priv->slaves[i].open_stat)
+ + 			usage_count++;
+ + 
+ + 	return usage_count;
+ + }
+ + 
+ + static inline int cpsw_tx_packet_submit(struct net_device *ndev,
+ + 			struct cpsw_priv *priv, struct sk_buff *skb)
+ + {
+ + 	if (ndev == cpsw_get_slave_ndev(priv, 0))
+ + 		return cpdma_chan_submit(priv->txch, skb, skb->data,
+ + 				  skb->len, 1, GFP_KERNEL);
+ + 	else
+ + 		return cpdma_chan_submit(priv->txch, skb, skb->data,
+ + 				  skb->len, 2, GFP_KERNEL);
+ + }
+ + 
+ + #define cpsw_add_switch_mode_default_ale_entries(priv)
+ + 
+ + #else	/* CONFIG_TI_CPSW_DUAL_EMAC */
+ + 
+ + static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
+ + {
+ + 	struct cpsw_priv *priv = netdev_priv(ndev);
+ + 
+ + 	/* Clear all mcast from ALE */
+ + 	cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port);
+ + 
+ + 	if (!netdev_mc_empty(ndev)) {
+ + 		struct netdev_hw_addr *ha;
+ + 
+ + 		/* program multicast address list into ALE register */
+ + 		netdev_for_each_mc_addr(ha, ndev) {
+ + 			cpsw_ale_add_mcast(priv->ale, (u8 *)ha->addr,
+ + 				ALE_ALL_PORTS << priv->host_port, 0, 0);
+ + 		}
+ + 	}
+ + }
+ + 
+ + static void cpsw_ndo_change_rx_flags(struct net_device *ndev, int flags)
+ + {
+ + 	struct cpsw_priv *priv = netdev_priv(ndev);
+ + 	struct cpsw_ale *ale = priv->ale;
+ + 	int i;
+ + 
+ + 	if (flags & IFF_PROMISC) {
+ + 		if (ndev->flags & IFF_PROMISC) {
+ + 			unsigned long timeout = jiffies + HZ;
+ + 
+ + 			/* Disable Learn for all ports */
+ + 			for (i = 0; i <= priv->data.slaves; i++) {
+ + 				cpsw_ale_control_set(ale, i,
+ + 						     ALE_PORT_NOLEARN, 1);
+ + 				cpsw_ale_control_set(ale, i,
+ + 						     ALE_PORT_NO_SA_UPDATE, 1);
+ + 			}
+ + 
+ + 			/* Clear All Untouched entries */
+ + 			cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
+ + 			do {
+ + 				cpu_relax();
+ + 				if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
+ + 					break;
+ + 			} while (time_after(timeout, jiffies));
+ + 			cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
+ + 
+ + 			/* Clear all mcast from ALE */
+ + 			cpsw_ale_flush_multicast(ale,
+ + 					ALE_ALL_PORTS << priv->host_port);
+ + 
+ + 			/* Flood All Unicast Packets to Host port */
+ + 			cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
+ + 			dev_err(&ndev->dev, "promiscuity enabled\n");
+ + 		} else {
+ + 			/* Flood All Unicast Packets to Host port */
+ + 			cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
+ + 
+ + 			/* Enable Learn for all ports */
+ + 			for (i = 0; i <= priv->data.slaves; i++) {
+ + 				cpsw_ale_control_set(ale, i,
+ + 						     ALE_PORT_NOLEARN, 0);
+ + 				cpsw_ale_control_set(ale, i,
+ + 						     ALE_PORT_NO_SA_UPDATE, 0);
+ + 			}
+ + 
+ + 			cpsw_ndo_set_rx_mode(ndev);
+ + 			dev_err(&ndev->dev, "promiscuity disabled\n");
+ + 		}
+ + 	}
+ + 
+ + 	/*
+ + 	 * The switch cannot filter multicast traffic unless it is configured
+ + 	 * in "VLAN Aware" mode.  Unfortunately, VLAN awareness requires a
+ + 	 * whole bunch of additional logic that this driver does not implement
+ + 	 * at present.
+ + 	 */
+ + 	if ((flags & IFF_ALLMULTI) && !(ndev->flags & IFF_ALLMULTI))
+ + 		dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n");
+ + }
+ + 
+ + #define cpsw_p0_fifo_type_select(priv)
+ + #define cpsw_add_dual_emac_mode_default_ale_entries(priv, slave, slave_port)
+ + #define cpsw_update_slave_open_state(priv, state)
+ + #define cpsw_common_res_usage_state(priv)	0
+ + #define cpsw_tx_packet_submit(ndev, priv, skb)		\
+ + 	cpdma_chan_submit(priv->txch, skb, skb->data,	\
+ + 			  skb->len, 0, GFP_KERNEL)
+ + 
+ + static inline void cpsw_add_switch_mode_default_ale_entries(
+ + 			struct cpsw_priv *priv)
+ + {
+ + 	cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
+ + 			   priv->host_port, 0);
+ + 	cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
+ + 			   1 << priv->host_port, 0, 0);
+ + }
+ + 
+ + #endif	/* CONFIG_TI_CPSW_DUAL_EMAC */
+ + 
+ + static int cpsw_set_coalesce(struct net_device *ndev,
+ + 			struct ethtool_coalesce *coal);
+ + 
+ + static void cpsw_intr_enable(struct cpsw_priv *priv)
+ + {
+ + 	__raw_writel(0xFF, &priv->wr_regs->tx_en);
+ + 	__raw_writel(0xFF, &priv->wr_regs->rx_en);
+ + 
+ + 	cpdma_ctlr_int_ctrl(priv->dma, true);
+ + 	return;
+ + }
+ + 
+ + static void cpsw_intr_disable(struct cpsw_priv *priv)
+ + {
+ + 	__raw_writel(0, &priv->wr_regs->tx_en);
+ + 	__raw_writel(0, &priv->wr_regs->rx_en);
+ + 
+ + 	cpdma_ctlr_int_ctrl(priv->dma, false);
+ + 	return;
+ + }
+ + 
+ + void cpsw_tx_handler(void *token, int len, int status)
+ + {
+ + 	struct sk_buff		*skb = token;
+ + 	struct net_device	*ndev = skb->dev;
+ + 	struct cpsw_priv	*priv = netdev_priv(ndev);
+ + 
+ + 	if (unlikely(netif_queue_stopped(ndev)))
+ + 		netif_start_queue(ndev);
+ + 	cpts_tx_timestamp(priv->cpts, skb);
+ + 	priv->stats.tx_packets++;
+ + 	priv->stats.tx_bytes += len;
+ + 	dev_kfree_skb_any(skb);
+ + }
+ + 
+ + void cpsw_rx_handler(void *token, int len, int status)
+ + {
+ + 	struct sk_buff		*skb = token;
+ + 	struct net_device	*ndev = skb->dev;
+ + 	struct cpsw_priv	*priv = netdev_priv(ndev);
+ + 	int			ret = 0;
+ + 
+ + 	cpsw_dual_emac_source_port_detect(status, priv, ndev, skb);
+ + 
+ + 	if (unlikely(!netif_running(ndev)) ||
+ + 			unlikely(!netif_carrier_ok(ndev))) {
+ + 		dev_kfree_skb_any(skb);
+ + 		return;
+ + 	}
+ + 
+ + 	if (likely(status >= 0)) {
+ + 		skb_put(skb, len);
+ + 		cpts_rx_timestamp(priv->cpts, skb);
+ + 		skb->protocol = eth_type_trans(skb, ndev);
+ + 		netif_receive_skb(skb);
+ + 		priv->stats.rx_bytes += len;
+ + 		priv->stats.rx_packets++;
+ + 		skb = NULL;
+ + 	}
+ + 
+ + 
+ + 	if (unlikely(!netif_running(ndev))) {
+ + 		if (skb)
+ + 			dev_kfree_skb_any(skb);
+ + 		return;
+ + 	}
+ + 
+ + 	if (likely(!skb)) {
+ + 		skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
+ + 		if (WARN_ON(!skb))
+ + 			return;
+ + 
+ + 		ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
+ + 				skb_tailroom(skb), 0, GFP_KERNEL);
+ + 	}
+ + 
+ + 	WARN_ON(ret < 0);
+ + 
+ + }
+ + 
+ + static void set_cpsw_dmtimer_clear(void)
+ + {
+ + 	omap_dm_timer_write_status(dmtimer_rx, OMAP_TIMER_INT_CAPTURE);
+ + 	omap_dm_timer_write_status(dmtimer_tx, OMAP_TIMER_INT_CAPTURE);
+ + 
+ + 	return;
+ + }
+ + 
+ + static irqreturn_t cpsw_interrupt(int irq, void *dev_id)
+ + {
+ + 	struct cpsw_priv *priv = dev_id;
+ + 
+ + 	if (likely(netif_running(priv->ndev))) {
+ + 		cpsw_intr_disable(priv);
+ + 		cpsw_disable_irq(priv);
+ + 		napi_schedule(&priv->napi);
+ + 	} else {
+ + 		priv = cpsw_get_slave_priv(priv, 1);
+ + 		if (likely(priv) && likely(netif_running(priv->ndev))) {
+ + 			cpsw_intr_disable(priv);
+ + 			cpsw_disable_irq(priv);
+ + 			napi_schedule(&priv->napi);
+ + 		}
+ + 	}
+ + 
+ + 	return IRQ_HANDLED;
+ + }
+ + 
+ + static int cpsw_poll(struct napi_struct *napi, int budget)
+ + {
+ + 	struct cpsw_priv	*priv = napi_to_priv(napi);
+ + 	int			num_tx, num_rx;
+ + 
+ + 	num_tx = cpdma_chan_process(priv->txch, 128);
+ + 	num_rx = cpdma_chan_process(priv->rxch, budget);
+ + 
+ + 	if (num_rx || num_tx)
+ + 		msg(dbg, intr, "poll %d rx, %d tx pkts\n", num_rx, num_tx);
+ + 
+ + 	if (num_rx < budget) {
+ + 		napi_complete(napi);
+ + 		cpdma_ctlr_eoi(priv->dma);
+ + 		set_cpsw_dmtimer_clear();
+ + 		cpsw_intr_enable(priv);
+ + 		cpsw_enable_irq(priv);
+ + 	}
+ + 
+ + 	return num_rx;
+ + }
+ + 
+ + static inline void soft_reset(const char *module, void __iomem *reg)
+ + {
+ + 	unsigned long timeout = jiffies + HZ;
+ + 
+ + 	__raw_writel(1, reg);
+ + 	do {
+ + 		cpu_relax();
+ + 	} while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
+ + 
+ + 	WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
+ + }
+ + 
+ + #define mac_hi(mac)	(((mac)[0] << 0) | ((mac)[1] << 8) |	\
+ + 			 ((mac)[2] << 16) | ((mac)[3] << 24))
+ + #define mac_lo(mac)	(((mac)[4] << 0) | ((mac)[5] << 8))
+ + 
+ + static void cpsw_set_slave_mac(struct cpsw_slave *slave,
+ + 			       struct cpsw_priv *priv)
+ + {
+ + 	slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
+ + 	slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
+ + }
+ + 
+ + static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
+ + {
+ + 	if (priv->host_port == 0)
+ + 		return slave_num + 1;
+ + 	else
+ + 		return slave_num;
+ + }
+ + 
+ + static void _cpsw_adjust_link(struct cpsw_slave *slave,
+ + 			      struct cpsw_priv *priv, bool *link)
+ + {
+ + 	struct phy_device	*phy = slave->phy;
+ + 	u32			mac_control = 0;
+ + 	u32			slave_port;
+ + 	struct cpsw_platform_data *pdata;
+ + 
+ + 	if (!phy)
+ + 		return;
+ + 
+ + 	slave_port = cpsw_get_slave_port(priv, slave->slave_num);
+ + 
+ + 	pdata = priv->pdev->dev.platform_data;
+ + 	if (!pdata->gigabit_en)
+ + 		phy->speed = 100;
+ + 
+ + 	if (phy->link) {
+ + 		/* enable forwarding */
+ + 		cpsw_ale_control_set(priv->ale, slave_port,
+ + 			ALE_PORT_STATE, priv->port_state[slave_port]);
+ + 
+ + 		mac_control = priv->data.mac_control;
+ + 		if (phy->speed == 10)
+ + 			mac_control |= BIT(18); /* In Band mode */
+ + 		if (phy->speed == 1000) {
+ + 			mac_control |= BIT(7);	/* Enable gigabit mode */
+ + 		}
+ + 		if (phy->speed == 100)
+ + 			mac_control |= BIT(15);
+ + 		if (phy->duplex)
+ + 			mac_control |= BIT(0);	/* FULLDUPLEXEN	*/
+ + 		if (phy->interface == PHY_INTERFACE_MODE_RGMII) /* RGMII */
+ + 			mac_control |= (BIT(15)|BIT(16));
+ + 		*link = true;
+ + 	} else {
+ + 		cpsw_ale_control_set(priv->ale, slave_port,
+ + 			     ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
+ + 		mac_control = 0;
+ + 	}
+ + 
+ + 	if (mac_control != slave->mac_control) {
+ + 		phy_print_status(phy);
+ + 		__raw_writel(mac_control, &slave->sliver->mac_control);
+ + 	}
+ + 
+ + 	slave->mac_control = mac_control;
+ + }
+ + 
+ + static void cpsw_adjust_link(struct net_device *ndev)
+ + {
+ + 	struct cpsw_priv	*priv = netdev_priv(ndev);
+ + 	bool			link = false;
+ + 
+ + 	for_each_slave(priv, _cpsw_adjust_link, priv, &link);
+ + 
+ + 	if (link) {
+ + 		netif_carrier_on(ndev);
+ + 		if (netif_running(ndev))
+ + 			netif_wake_queue(ndev);
+ + 	} else {
+ + 		netif_carrier_off(ndev);
+ + 		netif_stop_queue(ndev);
+ + 	}
+ + }
+ + 
+ + static inline int __show_stat(char *buf, int maxlen, const char* name, u32 val)
+ + {
+ + 	static char *leader = "........................................";
+ + 
+ + 	if (!val)
+ + 		return 0;
+ + 	else
+ + 		return snprintf(buf, maxlen, "%s %s %10d\n", name,
+ + 				leader + strlen(name), val);
+ + }
+ + 
+ + static ssize_t cpsw_hw_stats_show(struct device *dev,
+ + 				     struct device_attribute *attr,
+ + 				     char *buf)
+ + {
+ + 	struct net_device	*ndev = to_net_dev(dev);
+ + 	struct cpsw_priv	*priv = netdev_priv(ndev);
+ + 	int			len = 0;
+ + 	struct cpdma_chan_stats	dma_stats;
+ + 
+ + #define show_stat(x) do {						\
+ + 	len += __show_stat(buf + len, SZ_4K - len, #x,			\
+ + 			   __raw_readl(&priv->hw_stats->x));		\
+ + } while (0)
+ + 
+ + #define show_dma_stat(x) do {						\
+ + 	len += __show_stat(buf + len, SZ_4K - len, #x, dma_stats.x);	\
+ + } while (0)
+ + 
+ + 	len += snprintf(buf + len, SZ_4K - len, "CPSW Statistics:\n");
+ + 	show_stat(rxgoodframes);	show_stat(rxbroadcastframes);
+ + 	show_stat(rxmulticastframes);	show_stat(rxpauseframes);
+ + 	show_stat(rxcrcerrors);		show_stat(rxaligncodeerrors);
+ + 	show_stat(rxoversizedframes);	show_stat(rxjabberframes);
+ + 	show_stat(rxundersizedframes);	show_stat(rxfragments);
+ + 	show_stat(rxoctets);		show_stat(txgoodframes);
+ + 	show_stat(txbroadcastframes);	show_stat(txmulticastframes);
+ + 	show_stat(txpauseframes);	show_stat(txdeferredframes);
+ + 	show_stat(txcollisionframes);	show_stat(txsinglecollframes);
+ + 	show_stat(txmultcollframes);	show_stat(txexcessivecollisions);
+ + 	show_stat(txlatecollisions);	show_stat(txunderrun);
+ + 	show_stat(txcarriersenseerrors); show_stat(txoctets);
+ + 	show_stat(octetframes64);	show_stat(octetframes65t127);
+ + 	show_stat(octetframes128t255);	show_stat(octetframes256t511);
+ + 	show_stat(octetframes512t1023);	show_stat(octetframes1024tup);
+ + 	show_stat(netoctets);		show_stat(rxsofoverruns);
+ + 	show_stat(rxmofoverruns);	show_stat(rxdmaoverruns);
+ + 
+ + 	cpdma_chan_get_stats(priv->rxch, &dma_stats);
+ + 	len += snprintf(buf + len, SZ_4K - len, "\nRX DMA Statistics:\n");
+ + 	show_dma_stat(head_enqueue);	show_dma_stat(tail_enqueue);
+ + 	show_dma_stat(pad_enqueue);	show_dma_stat(misqueued);
+ + 	show_dma_stat(desc_alloc_fail);	show_dma_stat(pad_alloc_fail);
+ + 	show_dma_stat(runt_receive_buff); show_dma_stat(runt_transmit_buff);
+ + 	show_dma_stat(empty_dequeue);	show_dma_stat(busy_dequeue);
+ + 	show_dma_stat(good_dequeue);	show_dma_stat(teardown_dequeue);
+ + 
+ + 	cpdma_chan_get_stats(priv->txch, &dma_stats);
+ + 	len += snprintf(buf + len, SZ_4K - len, "\nTX DMA Statistics:\n");
+ + 	show_dma_stat(head_enqueue);	show_dma_stat(tail_enqueue);
+ + 	show_dma_stat(pad_enqueue);	show_dma_stat(misqueued);
+ + 	show_dma_stat(desc_alloc_fail);	show_dma_stat(pad_alloc_fail);
+ + 	show_dma_stat(runt_receive_buff); show_dma_stat(runt_transmit_buff);
+ + 	show_dma_stat(empty_dequeue);	show_dma_stat(busy_dequeue);
+ + 	show_dma_stat(good_dequeue);	show_dma_stat(teardown_dequeue);
+ + 
+ + 	return len;
+ + }
+ + 
+ + DEVICE_ATTR(hw_stats, S_IRUGO, cpsw_hw_stats_show, NULL);
+ + 
+ + #define PHY_CONFIG_REG	22
+ + static void cpsw_set_phy_config(struct cpsw_priv *priv, struct phy_device *phy)
+ + {
+ + 	struct cpsw_platform_data *pdata = priv->pdev->dev.platform_data;
+ + 	struct mii_bus *miibus;
+ + 	int phy_addr = 0;
+ + 	u16 val = 0;
+ + 	u16 tmp = 0;
+ + 
+ + 	if (!phy)
+ + 		return;
+ + 
+ + 	miibus = phy->bus;
+ + 	
+ + 	if (!miibus)
+ + 		return;
+ + 
+ + 	phy_addr = phy->addr;
+ + 
+ + 	/* Disable 1 Gig mode support if it is not supported */
+ + 	if (!pdata->gigabit_en)
+ + 	{
+ + 		phy->supported &= ~(SUPPORTED_1000baseT_Half |
+ + 					SUPPORTED_1000baseT_Full);
+ + 		phy->speed = 100;
+ + 	}
+ + 	/* Following lines enable gigbit advertisement capability even in case
+ + 	 * the advertisement is not enabled by default
+ + 	 */
+ + 	val = miibus->read(miibus, phy_addr, MII_BMCR);
+ + 	val |= (BMCR_SPEED100 | BMCR_ANENABLE | BMCR_FULLDPLX);
+ + 	if (!pdata->gigabit_en)
+ + 	{
+ + 		val &= ~BMCR_SPEED1000;
+ + 	}
+ + 	miibus->write(miibus, phy_addr, MII_BMCR, val);
+ + 	tmp = miibus->read(miibus, phy_addr, MII_BMCR);
+ + 	
+ + 	/* Enable gigabit support only if the speed is 1000Mbps */
+ + 	if (phy->speed == CPSW_PHY_SPEED) {
+ + 		tmp = miibus->read(miibus, phy_addr, MII_BMSR);
+ + 		if (tmp & 0x1) {
+ + 			val = miibus->read(miibus, phy_addr, MII_CTRL1000);
+ + 			val |= BIT(9);
+ + 			miibus->write(miibus, phy_addr, MII_CTRL1000, val);
+ + 			tmp = miibus->read(miibus, phy_addr, MII_CTRL1000);
+ + 		}
+ + 	}
+ + 
+ + 	val = miibus->read(miibus, phy_addr, MII_ADVERTISE);
+ + 	val |= (ADVERTISE_10HALF | ADVERTISE_10FULL | \
+ + 		ADVERTISE_100HALF | ADVERTISE_100FULL);
+ + 	if (!pdata->gigabit_en)
+ + 	{
+ + 		val &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF
+ + 					| ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM);
+ + 	}
+ + 
+ + 	miibus->write(miibus, phy_addr, MII_ADVERTISE, val);
+ + 	tmp = miibus->read(miibus, phy_addr, MII_ADVERTISE);
+ + 	/* TODO : This check is required. This should be
+ + 	 * moved to a board init section as its specific
+ + 	 * to a phy.*/
+ + 	if (phy->phy_id == 0x0282F014) {
+ + 		/* This enables TX_CLK-ing in case of 10/100MBps operation */
+ + 		val = miibus->read(miibus, phy_addr, PHY_CONFIG_REG);
+ + 		val |= BIT(5);
+ + 		miibus->write(miibus, phy_addr, PHY_CONFIG_REG, val);
+ + 		tmp = miibus->read(miibus, phy_addr, PHY_CONFIG_REG);
+ + 	}
+ + 
+ + 	return;
+ + }
+ + 
+ + static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
+ + {
+ + 	char name[32];
+ + 	u32 slave_port;
+ + 
+ + 	sprintf(name, "slave-%d", slave->slave_num);
+ + 
+ + 	soft_reset(name, &slave->sliver->soft_reset);
+ + 
+ + 	/* setup priority mapping */
+ + 	writel(0x76543210, &slave->sliver->rx_pri_map);
+ + 	if (priv->version == CPSW_VERSION1)
+ + 		slave_write(slave, 0x33221100, CPSW1_TX_PRI_MAP);
+ + 	else
+ + 		slave_write(slave, 0x33221100, CPSW2_TX_PRI_MAP);
+ + 
+ + 	/* setup max packet size, and mac address */
+ + 	__raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
+ + 	cpsw_set_slave_mac(slave, priv);
+ + 
+ + 	slave->mac_control = 0;	/* no link yet */
+ + 
+ + 	slave_port = cpsw_get_slave_port(priv, slave->slave_num);
+ + 
+ + 	cpsw_add_dual_emac_mode_default_ale_entries(priv, slave, slave_port);
+ + 	cpsw_add_switch_mode_bcast_ale_entries(priv, slave_port);
+ + 	priv->port_state[slave_port] = ALE_PORT_STATE_FORWARD;
+ + 
+ + 	slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
+ + 				 &cpsw_adjust_link, 0, slave->data->phy_if);
+ + 	if (IS_ERR(slave->phy)) {
+ + 		msg(err, ifup, "phy %s not found on slave %d\n",
+ + 		    slave->data->phy_id, slave->slave_num);
+ + 		slave->phy = NULL;
+ + 	} else {
+ + 		dev_info(priv->dev, "CPSW phy found : id is : 0x%x\n",
+ + 			slave->phy->phy_id);
+ + 		cpsw_set_phy_config(priv, slave->phy);
+ + 		phy_start(slave->phy);
+ + 	}
+ + }
+ + 
+ + #if defined(VLAN_SUPPORT) && !defined(CONFIG_TI_CPSW_DUAL_EMAC)
+ + static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
+ + {
+ + 	writel(priv->data.default_vlan, &priv->host_port_regs->port_vlan);
+ + 	if (priv->version == CPSW_VERSION1) {
+ + 		slave_write(&priv->slaves[0], priv->data.default_vlan,
+ + 			    CPSW1_PORT_VLAN);
+ + 		slave_write(&priv->slaves[1], priv->data.default_vlan,
+ + 			    CPSW1_PORT_VLAN);
+ + 	} else {
+ + 		slave_write(&priv->slaves[0], priv->data.default_vlan,
+ + 			    CPSW2_PORT_VLAN);
+ + 		slave_write(&priv->slaves[1], priv->data.default_vlan,
+ + 			    CPSW2_PORT_VLAN);
+ + 	}
+ + 	cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan,
+ + 			ALE_ALL_PORTS << priv->host_port,
+ + 			ALE_ALL_PORTS << priv->host_port,
+ + 			ALE_ALL_PORTS << priv->host_port, 0);
+ + }
+ + #else
+ + #define cpsw_add_default_vlan(priv)
+ + #endif
+ + 
+ + static void cpsw_init_host_port(struct cpsw_priv *priv)
+ + {
+ + 	u32 control_reg;
+ + 
+ + 	/* soft reset the controller and initialize ale */
+ + 	soft_reset("cpsw", &priv->regs->soft_reset);
+ + 	cpsw_ale_start(priv->ale);
+ + 
+ + 	/* switch to vlan aware/unaware mode */
+ + 	cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
+ + 			     CPSW_ALE_VLAN_AWARE);
+ + 	control_reg = readl(&priv->regs->control);
+ + 	control_reg |= CPSW_VLAN_AWARE;
+ + 	writel(control_reg, &priv->regs->control);
+ + 	cpsw_p0_fifo_type_select(priv);
+ + 
+ + 	/* setup host port priority mapping */
+ + 	__raw_writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map);
+ + 	__raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
+ + 
+ + 	cpsw_ale_control_set(priv->ale, priv->host_port,
+ + 			     ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
+ + 
+ + 	cpsw_add_switch_mode_default_ale_entries(priv);
+ + }
+ + 
+ + static int cpsw_ndo_open(struct net_device *ndev)
+ + {
+ + 	struct cpsw_priv *priv = netdev_priv(ndev);
+ + 	int i, ret;
+ + 	u32 reg;
+ + 
+ + 	if (!cpsw_common_res_usage_state(priv))
+ + 		cpsw_intr_disable(priv);
+ + 	netif_carrier_off(ndev);
+ + 
+ + 	if (priv->data.phy_control)
+ + 		(*priv->data.phy_control)(true);
+ + 
+ + 	reg = __raw_readl(&priv->regs->id_ver);
+ + 	priv->version = reg;
+ + 
+ + 	msg(info, ifup, "initializing cpsw version %d.%d (%d)\n",
+ + 	    (reg >> 8 & 0x7), reg & 0xff, (reg >> 11) & 0x1f);
+ + 
+ + 	/* initialize host and slave ports */
+ + 	if (!cpsw_common_res_usage_state(priv))
+ + 		cpsw_init_host_port(priv);
+ + 	for_each_slave(priv, cpsw_slave_open, priv);
+ + 
+ + 	/* Add default VLAN */
+ + 	cpsw_add_default_vlan(priv);
+ + 
+ + 	if (!cpsw_common_res_usage_state(priv)) {
+ + 		ret = device_create_file(&ndev->dev, &dev_attr_hw_stats);
+ + 		if (ret < 0) {
+ + 			dev_err(priv->dev, "unable to add device attr\n");
+ + 			return ret;
+ + 		}
+ + 
+ + 		/* setup tx dma to fixed prio and zero offset */
+ + 		cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
+ + 		cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
+ + 
+ + 		/* disable priority elevation and enable statistics */
+ + 		/* on all ports */
+ + 		writel(0, &priv->regs->ptype);
+ + 		writel(0x7, &priv->regs->stat_port_en);
+ + 
+ + 		if (WARN_ON(!priv->data.rx_descs))
+ + 			priv->data.rx_descs = 128;
+ + 
+ + 		for (i = 0; i < priv->data.rx_descs; i++) {
+ + 			struct sk_buff *skb;
+ + 
+ + 			ret = -ENOMEM;
+ + 			skb = netdev_alloc_skb_ip_align(priv->ndev,
+ + 							priv->rx_packet_max);
+ + 			if (!skb)
+ + 				break;
+ + 			ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
+ + 					skb_tailroom(skb), 0, GFP_KERNEL);
+ + 			if (WARN_ON(ret < 0)) {
+ + 				dev_kfree_skb_any(skb);
+ + 				break;
+ + 			}
+ + 		}
+ + 		/*
+ + 		 * continue even if we didn't manage to submit all
+ + 		 * receive descs
+ + 		 */
+ + 		msg(info, ifup, "submitted %d rx descriptors\n", i);
+ + 
+ + 		if (cpts_register(&priv->pdev->dev, priv->cpts,
+ + 				  priv->data.cpts_clock_mult,
+ + 				  priv->data.cpts_clock_shift))
+ + 			dev_err(priv->dev, "error registering cpts device\n");
+ + 	}
+ + 
+ + 	/* Enable Interrupt pacing if configured */
+ + 	if (priv->coal_intvl != 0) {
+ + 		struct ethtool_coalesce coal;
+ + 
+ + 		coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
+ + 		cpsw_set_coalesce(ndev, &coal);
+ + 	}
+ + 
+ + 	/* Enable Timer for capturing cpsw rx interrupts */
+ + 	omap_dm_timer_set_int_enable(dmtimer_rx, OMAP_TIMER_INT_CAPTURE);
+ + 	omap_dm_timer_set_capture(dmtimer_rx, 1, 0, 0);
+ + 	omap_dm_timer_enable(dmtimer_rx);
+ + 
+ + 	/* Enable Timer for capturing cpsw tx interrupts */
+ + 	omap_dm_timer_set_int_enable(dmtimer_tx, OMAP_TIMER_INT_CAPTURE);
+ + 	omap_dm_timer_set_capture(dmtimer_tx, 1, 0, 0);
+ + 	omap_dm_timer_enable(dmtimer_tx);
+ + 
+ + 	cpdma_ctlr_start(priv->dma);
+ + 	cpsw_intr_enable(priv);
+ + 	napi_enable(&priv->napi);
+ + 	cpdma_ctlr_eoi(priv->dma);
+ + 
+ + 	cpsw_update_slave_open_state(priv, true)
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
+ + {
+ + 	if (!slave->phy)
+ + 		return;
+ + 	phy_stop(slave->phy);
+ + 	phy_disconnect(slave->phy);
+ + 	slave->phy = NULL;
+ + }
+ + 
+ + static int cpsw_ndo_stop(struct net_device *ndev)
+ + {
+ + 	struct cpsw_priv *priv = netdev_priv(ndev);
+ + 
+ + 	msg(info, ifdown, "shutting down cpsw device\n");
+ + 
+ + 	netif_stop_queue(priv->ndev);
+ + 	napi_disable(&priv->napi);
+ + 	netif_carrier_off(priv->ndev);
+ + 
+ + 	if (cpsw_common_res_usage_state(priv) <= 1) {
+ + 		cpsw_intr_disable(priv);
+ + 		cpdma_ctlr_int_ctrl(priv->dma, false);
+ + 
+ + 		omap_dm_timer_set_int_enable(dmtimer_rx, 0);
+ + 		omap_dm_timer_set_int_enable(dmtimer_tx, 0);
+ + 
+ + 		cpdma_ctlr_stop(priv->dma);
+ + 		cpsw_ale_stop(priv->ale);
+ + 
+ + 		cpts_unregister(priv->cpts);
+ + 	}
+ + 
+ + 	device_remove_file(&ndev->dev, &dev_attr_hw_stats);
+ + 	for_each_slave(priv, cpsw_slave_stop, priv);
+ + 	if (priv->data.phy_control)
+ + 		(*priv->data.phy_control)(false);
+ + 
+ + 	cpsw_update_slave_open_state(priv, false)
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
+ + 				       struct net_device *ndev)
+ + {
+ + 	struct cpsw_priv *priv = netdev_priv(ndev);
+ + 	int ret;
+ + 
+ + 	ndev->trans_start = jiffies;
+ + 
+ + 	ret = skb_padto(skb, CPSW_MIN_PACKET_SIZE);
+ + 	if (unlikely(ret < 0)) {
+ + 		msg(err, tx_err, "packet pad failed");
+ + 		goto fail;
+ + 	}
+ + 
+ + 	if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
+ + 			priv->cpts->tx_enable)
+ + 		skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
+ + 
+ + 	skb_tx_timestamp(skb);
+ + 
+ + 	ret = cpsw_tx_packet_submit(ndev, priv, skb);
+ + 	if (unlikely(ret != 0)) {
+ + 		msg(err, tx_err, "desc submit failed");
+ + 		goto fail;
+ + 	}
+ + 
+ + 	return NETDEV_TX_OK;
+ + fail:
+ + 	priv->stats.tx_dropped++;
+ + 	netif_stop_queue(ndev);
+ + 	return NETDEV_TX_BUSY;
+ + }
+ + 
+ + #ifndef CONFIG_TI_CPSW_DUAL_EMAC
+ + /*
+ +  *  cpsw_set_priority_mapping
+ +  *    This function configures the packet priority handling on each port.
+ +  */
+ + static int cpsw_set_priority_mapping(struct cpsw_priv *priv, int port,
+ + 	int rxpriority, int txpriority, int switchpriority)
+ + {
+ + 	if (port == 0) {
+ + 		writel(CPSW_PRIMAP(rxpriority, txpriority),
+ + 			&priv->host_port_regs->cpdma_tx_pri_map);
+ + 		writel(CPSW_PRIMAP(txpriority, switchpriority),
+ + 			&priv->host_port_regs->cpdma_tx_pri_map);
+ + 	} else {
+ + 		/* Configure sliver priority mapping registers */
+ + 		writel(CPSW_PRIMAP(rxpriority, txpriority),
+ + 			&slave(priv, port-1)->sliver->rx_pri_map);
+ + 		writel(CPSW_PRIMAP(txpriority, switchpriority),
+ + 			&slave(priv, port-1)->sliver->rx_pri_map);
+ + 	}
+ + 	return 0;
+ + }
+ + 
+ + /*
+ +  * cpsw_rate_limit_tx
+ +  * Limits the number of Tx packets on a port for a 100ms time period.
+ +  * Rate limit can be done either on Tx or Rx for all the ports due to
+ +  * hardware limitation
+ +  */
+ + static int cpsw_rate_limit_tx(struct cpsw_ale *ale, u32 enable, u32 port,
+ + 				u32 addr_type, u32 limit)
+ + {
+ + 	u32 type;
+ + 
+ + 	if (!enable) {
+ + 		cpsw_ale_control_set(ale, port, ALE_RATE_LIMIT, 0);
+ + 		return 0;
+ + 	}
+ + 
+ + 	/* ALE prescale is set for 100 ms time */
+ + 	if (addr_type == ADDR_TYPE_BROADCAST)
+ + 		type = ALE_PORT_BCAST_LIMIT;
+ + 	else if (addr_type == ADDR_TYPE_MULTICAST)
+ + 		type = ALE_PORT_MCAST_LIMIT;
+ + 	else
+ + 		return -EFAULT;
+ + 
+ + 	cpsw_ale_control_set(ale, port, type, limit);
+ + 	/* Enable the bit for rate limiting transmission */
+ + 	cpsw_ale_control_set(ale, port, ALE_RATE_LIMIT_TX, 1);
+ + 	cpsw_ale_control_set(ale, port, ALE_RATE_LIMIT, 1);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /*
+ +  * cpsw_rate_limit_rx
+ +  * Limits the number of Rx packets on a port for a 100ms time period.
+ +  * Rate limit can be done either on Tx or Rx for all the ports due to
+ +  * hardware limitation
+ +  */
+ + static int cpsw_rate_limit_rx(struct cpsw_ale *ale, u32 enable, u32 port,
+ + 				u32 addr_type, u32 limit)
+ + {
+ + 	u32 type;
+ + 
+ + 	if (!enable) {
+ + 		cpsw_ale_control_set(ale, port, ALE_RATE_LIMIT, 0);
+ + 		return 0;
+ + 	}
+ + 
+ + 	/* ALE prescale is set for 100 ms time */
+ + 	if (addr_type == ADDR_TYPE_BROADCAST)
+ + 		type = ALE_PORT_BCAST_LIMIT;
+ + 	else if (addr_type == ADDR_TYPE_MULTICAST)
+ + 		type = ALE_PORT_MCAST_LIMIT;
+ + 	else
+ + 		return -EFAULT;
+ + 
+ + 	cpsw_ale_control_set(ale, port, type, limit);
+ + 	/* Disable the bit for rate limiting reception */
+ + 	cpsw_ale_control_set(ale, port, ALE_RATE_LIMIT_TX, 0);
+ + 	cpsw_ale_control_set(ale, port, ALE_RATE_LIMIT, 1);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + int cpsw_rate_limit(struct cpsw_ale *ale, u32 enable, u32 direction, u32 port,
+ + 			u32 packet_type, u32 limit)
+ + {
+ + 
+ + 	if (port == 0) {
+ + 		/*
+ + 		 * For host port transmit/receive terminlogy is inverse
+ + 		 * of cpgmac port
+ + 		 */
+ + 		if (direction)
+ + 			cpsw_rate_limit_rx(ale, enable, port,
+ + 					packet_type, limit);
+ + 		else
+ + 			cpsw_rate_limit_tx(ale, enable, port,
+ + 					packet_type, limit);
+ + 	} else {
+ + 		if (direction)
+ + 			cpsw_rate_limit_tx(ale, enable, port,
+ + 					packet_type, limit);
+ + 		else
+ + 			cpsw_rate_limit_rx(ale, enable, port,
+ + 					packet_type, limit);
+ + 	}
+ + 	return 0;
+ + }
+ + 
+ + static int cpsw_config_dump(struct cpsw_priv *priv, u8 *buf, u32 size)
+ + {
+ + 	int vlan_aware = 0;
+ + 	int out_len = 0;
+ + 	u32 port_state;
+ + 	char *port_state_str[] = {"disabled", "blocked", "learn", "forward"};
+ + 
+ + 	out_len += snprintf(buf, size, "Switch Configuarion\n");
+ + 
+ + 	vlan_aware = readl(&priv->regs->control) & CPSW_VLAN_AWARE;
+ + 
+ + 	out_len += snprintf(buf + out_len, size - out_len, "VLAN Aware Mode"
+ + 			"                              :  %s\n",
+ + 			(vlan_aware ? "Yes" : "No"));
+ + 	out_len += snprintf(buf + out_len, size - out_len, "ALE VLAN Aware "
+ + 			"Mode                          :  %s\n",
+ + 			(cpsw_ale_control_get(priv->ale, priv->host_port,
+ + 				ALE_VLAN_AWARE) ? "Yes" : "No"));
+ + 	out_len += snprintf(buf + out_len, size - out_len, "Unknown VLAN "
+ + 			"Members                         :  %u\n",
+ + 			cpsw_ale_control_get(priv->ale, 0,
+ + 				ALE_PORT_UNKNOWN_VLAN_MEMBER));
+ + 	out_len += snprintf(buf + out_len, size - out_len, "Unknown Multicast"
+ + 			" Flood Mask                 :  %u\n",
+ + 			cpsw_ale_control_get(priv->ale, 0,
+ + 				ALE_PORT_UNKNOWN_MCAST_FLOOD));
+ + 	out_len += snprintf(buf + out_len, size - out_len, "Unknown Registered"
+ + 			" Multicast Flood Mask      :  %u\n",
+ + 			cpsw_ale_control_get(priv->ale, 0,
+ + 				ALE_PORT_UNKNOWN_REG_MCAST_FLOOD));
+ + 	out_len += snprintf(buf + out_len, size - out_len, "Unknown VLAN Force"
+ + 			" Untagged Egress           :  %u\n",
+ + 			cpsw_ale_control_get(priv->ale, 0,
+ + 				ALE_PORT_UNTAGGED_EGRESS));
+ + 
+ + 	out_len += snprintf(buf + out_len, size - out_len,
+ + 			"\nPort Configuration\n");
+ + 	out_len += snprintf(buf + out_len, size - out_len,
+ + 			"\t%-8s %-8s %-8s %s\n", "PORT", "PVID", "PRIORITY",
+ + 			"STATE");
+ + 	out_len += snprintf(buf + out_len, size - out_len,
+ + 			"\t---------------------------------\n");
+ + 
+ + 	if (vlan_aware) {
+ + 		int port_vlan;
+ + 		struct cpsw_slave *slave;
+ + 
+ + 		port_state = cpsw_ale_control_get(priv->ale, 0, ALE_PORT_STATE);
+ + 		port_vlan = readl(&priv->host_port_regs->port_vlan);
+ + 		out_len += snprintf(buf + out_len, size - out_len,
+ + 			"\t%-8u %-8u %-8u %s\n", 0,
+ + 			port_vlan & 0xfff, (port_vlan > 13) & 0x7,
+ + 			port_state_str[port_state]);
+ + 
+ + 		port_state = cpsw_ale_control_get(priv->ale, 1, ALE_PORT_STATE);
+ + 		slave = &priv->slaves[0];
+ + 		if (priv->version == CPSW_VERSION1)
+ + 			port_vlan = slave_read(slave, CPSW1_PORT_VLAN);
+ + 		else
+ + 			port_vlan = slave_read(slave, CPSW2_PORT_VLAN);
+ + 		out_len += snprintf(buf + out_len, size - out_len,
+ + 			"\t%-8u %-8u %-8u %s\n", 1,
+ + 			port_vlan & 0xfff, (port_vlan > 13) & 0x7,
+ + 			port_state_str[port_state]);
+ + 
+ + 		port_state = cpsw_ale_control_get(priv->ale, 2, ALE_PORT_STATE);
+ + 		slave = &priv->slaves[1];
+ + 		if (priv->version == CPSW_VERSION1)
+ + 			port_vlan = slave_read(slave, CPSW1_PORT_VLAN);
+ + 		else
+ + 			port_vlan = slave_read(slave, CPSW2_PORT_VLAN);
+ + 		out_len += snprintf(buf + out_len, size - out_len,
+ + 			"\t%-8u %-8u %-8u %s\n", 2,
+ + 			port_vlan & 0xfff, (port_vlan > 13) & 0x7,
+ + 			port_state_str[port_state]);
+ + 	} else {
+ + 		port_state = cpsw_ale_control_get(priv->ale, 0, ALE_PORT_STATE);
+ + 		out_len += snprintf(buf + out_len, size - out_len,
+ + 			"\t%-8u %-8s %-8s %s\n", 0,
+ + 			"-", "-", port_state_str[port_state]);
+ + 
+ + 		port_state = cpsw_ale_control_get(priv->ale, 1, ALE_PORT_STATE);
+ + 		out_len += snprintf(buf + out_len, size - out_len,
+ + 			"\t%-8u %-8s %-8s %s\n", 1,
+ + 			"-", "-", port_state_str[port_state]);
+ + 
+ + 		port_state = cpsw_ale_control_get(priv->ale, 2, ALE_PORT_STATE);
+ + 		out_len += snprintf(buf + out_len, size - out_len,
+ + 			"\t%-8u %-8s %-8s %s\n", 2,
+ + 			"-", "-", port_state_str[port_state]);
+ + 	}
+ + 
+ + 	return out_len;
+ + }
+ + 
+ + static int cpsw_set_port_state(struct cpsw_priv *priv, int port,
+ + 			int port_state)
+ + {
+ + 	int ret = -EFAULT;
+ + 	switch (port_state) {
+ + 	case PORT_STATE_DISABLED:
+ + 		priv->port_state[port] = ALE_PORT_STATE_DISABLE;
+ + 		break;
+ + 	case PORT_STATE_BLOCKED:
+ + 		priv->port_state[port] = ALE_PORT_STATE_BLOCK;
+ + 		break;
+ + 	case PORT_STATE_LEARN:
+ + 		priv->port_state[port] = ALE_PORT_STATE_LEARN;
+ + 		break;
+ + 	case PORT_STATE_FORWARD:
+ + 		priv->port_state[port] = ALE_PORT_STATE_FORWARD;
+ + 		break;
+ + 	}
+ + 	ret = cpsw_ale_control_set(priv->ale, port, ALE_PORT_STATE,
+ + 			priv->port_state[port]);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + static int cpsw_switch_config_ioctl(struct net_device *ndev,
+ + 		struct ifreq *ifrq, int cmd)
+ + {
+ + 	struct cpsw_priv *priv = netdev_priv(ndev);
+ + 	struct net_switch_config *switch_config;
+ + 	int ret = -EFAULT;
+ + 
+ + 	/*
+ + 	* Only SIOCSWITCHCONFIG is used as cmd argument and hence, there is no
+ + 	* switch statement required.
+ + 	* Function calls are based on switch_config.cmd
+ + 	*/
+ + 	if (cmd != SIOCSWITCHCONFIG)
+ + 		return ret;
+ + 
+ + 	switch_config = kzalloc(sizeof(struct net_switch_config), GFP_KERNEL);
+ + 	if (copy_from_user(switch_config, (ifrq->ifr_data),
+ + 			sizeof(struct net_switch_config)))
+ + 		return ret;
+ + 
+ + 	switch (switch_config->cmd) {
+ + 	case CONFIG_SWITCH_ADD_MULTICAST:
+ + 		if ((switchcmd(switch_config).untag_port <= 3) &&
+ + 				(switchcmd(switch_config).vid <= 4095) &&
+ + 				(switchcmd(switch_config).mem_port > 0) &&
+ + 				(switchcmd(switch_config).mem_port <= 7) &&
+ + 				is_multicast_ether_addr(
+ + 				switchcmd(switch_config).addr)) {
+ + 			if (switchcmd(switch_config).vid == 0)
+ + 				ret = cpsw_ale_add_mcast(priv->ale,
+ + 					switchcmd(switch_config).addr,
+ + 					switchcmd(switch_config).mem_port
+ + 						<< priv->host_port,
+ + 					switchcmd(switch_config).flag,
+ + 					switchcmd(switch_config).untag_port);
+ + 			else
+ + 				ret = cpsw_ale_vlan_add_mcast(priv->ale,
+ + 					switchcmd(switch_config).addr,
+ + 					switchcmd(switch_config).mem_port
+ + 						<< priv->host_port,
+ + 					switchcmd(switch_config).vid,
+ + 					switchcmd(switch_config).flag,
+ + 					switchcmd(switch_config).untag_port);
+ + 		} else {
+ + 			dev_err(priv->dev, "Invalid Switch config arguments\n");
+ + 			ret = -EFAULT;
+ + 		}
+ + 		break;
+ + 
+ + 	case CONFIG_SWITCH_ADD_UNICAST:
+ + 		if ((switchcmd(switch_config).vid <= 4095) &&
+ + 				(switchcmd(switch_config).mem_port <= 2) &&
+ + 				is_valid_ether_addr(
+ + 					switchcmd(switch_config).addr)) {
+ + 			if (switchcmd(switch_config).vid == 0)
+ + 				ret = cpsw_ale_add_ucast(priv->ale,
+ + 					switchcmd(switch_config).addr,
+ + 					priv->host_port, 0);
+ + 			else
+ + 				ret = cpsw_ale_vlan_add_ucast(priv->ale,
+ + 					switchcmd(switch_config).addr,
+ + 					priv->host_port, 0,
+ + 					switchcmd(switch_config).vid);
+ + 		} else {
+ + 			dev_err(priv->dev, "Invalid Switch config arguments\n");
+ + 			ret = -EFAULT;
+ + 		}
+ + 		break;
+ + 
+ + 	case CONFIG_SWITCH_ADD_OUI:
+ + 		if (!is_zero_ether_addr(switchcmd(switch_config).addr)) {
+ + 			ret = cpsw_ale_add_oui(priv->ale,
+ + 				switchcmd(switch_config).addr);
+ + 		} else {
+ + 			dev_err(priv->dev, "Invalid Switch config arguments\n");
+ + 			ret = -EFAULT;
+ + 		}
+ + 		break;
+ + 
+ + 	case CONFIG_SWITCH_FIND_ADDR:
+ + 		if ((switchcmd(switch_config).vid <= 4095) &&
+ + 			!is_zero_ether_addr(switchcmd(switch_config).addr)) {
+ + 			ret = cpsw_ale_match_addr(priv->ale,
+ + 				switchcmd(switch_config).addr,
+ + 				switchcmd(switch_config).vid);
+ + 			if (ret >= 0) {
+ + 				switch_config->ret_type = ret;
+ + 				ret = copy_to_user(ifrq->ifr_data,
+ + 					switch_config,
+ + 					sizeof(struct net_switch_config)) ?
+ + 					-EFAULT : 0;
+ + 			}
+ + 		} else {
+ + 			dev_err(priv->dev, "Invalid Arguments\n");
+ + 			ret = -EFAULT;
+ + 		}
+ + 		break;
+ + 
+ + 	case CONFIG_SWITCH_DEL_MULTICAST:
+ + 		if ((switchcmd(switch_config).vid <= 4095) &&
+ + 				is_multicast_ether_addr(
+ + 				switchcmd(switch_config).addr)) {
+ + 			if (switchcmd(switch_config).vid == 0)
+ + 				ret = cpsw_ale_del_mcast(priv->ale,
+ + 					switchcmd(switch_config).addr,
+ + 					switchcmd(switch_config).mem_port
+ + 						<< priv->host_port);
+ + 			else
+ + 				ret = cpsw_ale_vlan_del_mcast(priv->ale,
+ + 					switchcmd(switch_config).addr,
+ + 					switchcmd(switch_config).mem_port
+ + 						<< priv->host_port,
+ + 					switchcmd(switch_config).vid);
+ + 		} else {
+ + 			dev_err(priv->dev, "Invalid Arguments\n");
+ + 			ret = -EFAULT;
+ + 		}
+ + 		break;
+ + 
+ + 	case CONFIG_SWITCH_DEL_UNICAST:
+ + 		if ((switchcmd(switch_config).vid <= 4095) &&
+ + 			is_valid_ether_addr(switchcmd(switch_config).addr)) {
+ + 			if (switchcmd(switch_config).vid == 0) {
+ + 				if (!memcmp(switchcmd(switch_config).addr,
+ + 						priv->mac_addr, 6)) {
+ + 					ret = -EPERM;
+ + 					break;
+ + 				}
+ + 				ret = cpsw_ale_del_ucast(priv->ale,
+ + 					switchcmd(switch_config).addr, 0);
+ + 			} else
+ + 				ret = cpsw_ale_del_ucast(priv->ale,
+ + 					switchcmd(switch_config).addr,
+ + 					switchcmd(switch_config).vid);
+ + 		} else {
+ + 			dev_err(priv->dev, "Invalid Arguments\n");
+ + 			ret = -EFAULT;
+ + 		}
+ + 		break;
+ + 
+ + 	case CONFIG_SWITCH_ADD_VLAN:
+ + 		if ((switchcmd(switch_config).vid <= 4095) &&
+ + 				(switchcmd(switch_config).mem_port > 0) &&
+ + 				(switchcmd(switch_config).mem_port <= 7)) {
+ + 			ret = cpsw_ale_add_vlan(priv->ale,
+ + 				switchcmd(switch_config).vid,
+ + 				switchcmd(switch_config).mem_port
+ + 					<< priv->host_port,
+ + 				switchcmd(switch_config).untag_port,
+ + 				switchcmd(switch_config).reg_multi,
+ + 				switchcmd(switch_config).unreg_multi);
+ + 		} else {
+ + 			dev_err(priv->dev, "Invalid Arguments\n");
+ + 			ret = -EFAULT;
+ + 		}
+ + 		break;
+ + 
+ + 	case CONFIG_SWITCH_FIND_VLAN:
+ + 		if (switchcmd(switch_config).vid <= 4095) {
+ + 			switch_config->ret_type = cpsw_ale_match_vlan(priv->ale,
+ + 				switchcmd(switch_config).vid);
+ + 			ret = copy_to_user(ifrq->ifr_data, switch_config,
+ + 				sizeof(struct net_switch_config)) ?
+ + 				-EFAULT : 0;
+ + 		} else {
+ + 			dev_err(priv->dev, "Invalid Arguments\n");
+ + 			ret = -EFAULT;
+ + 		}
+ + 		break;
+ + 
+ + 	case CONFIG_SWITCH_DEL_VLAN:
+ + 		if ((switchcmd(switch_config).vid <= 4095) &&
+ + 				(switchcmd(switch_config).mem_port <= 7)) {
+ + 			ret = cpsw_ale_del_vlan(priv->ale,
+ + 				switchcmd(switch_config).vid,
+ + 				switchcmd(switch_config).mem_port
+ + 				<< priv->host_port);
+ + 		} else {
+ + 			dev_err(priv->dev, "Invalid Arguments\n");
+ + 			ret = -EFAULT;
+ + 		}
+ + 		break;
+ + 
+ + 	case CONFIG_SWITCH_SET_PORT_VLAN_CONFIG:
+ + 	{
+ + 		int port_vlan = switchcmd(switch_config).vid |
+ + 				switchcmd(switch_config).prio_port << 13;
+ + 
+ + 		if ((switchcmd(switch_config).vid <= 4095) &&
+ + 				(switchcmd(switch_config).port <= 2) &&
+ + 				(switchcmd(switch_config).prio_port <= 7)) {
+ + 			if (switchcmd(switch_config).CFI_port)
+ + 				port_vlan |= (1 << 12);
+ + 
+ + 			if (switchcmd(switch_config).port == 0) {
+ + 				writel(port_vlan,
+ + 					&priv->host_port_regs->port_vlan);
+ + 			} else if (switchcmd(switch_config).port == 1) {
+ + 				if (priv->version == CPSW_VERSION1)
+ + 					slave_write(&priv->slaves[0], port_vlan,
+ + 						    CPSW1_PORT_VLAN);
+ + 				else
+ + 					slave_write(&priv->slaves[0], port_vlan,
+ + 						    CPSW2_PORT_VLAN);
+ + 			} else {
+ + 				if (priv->version == CPSW_VERSION1)
+ + 					slave_write(&priv->slaves[1], port_vlan,
+ + 						    CPSW1_PORT_VLAN);
+ + 				else
+ + 					slave_write(&priv->slaves[1], port_vlan,
+ + 						    CPSW2_PORT_VLAN);
+ + 			}
+ + 			ret = 0;
+ + 		} else {
+ + 			dev_err(priv->dev, "Invalid Arguments\n");
+ + 			ret = -EFAULT;
+ + 		}
+ + 		break;
+ + 	}
+ + 
+ + 	case CONFIG_SWITCH_TIMEOUT:
+ + 		ret = cpsw_ale_set_ageout(priv->ale,
+ + 			switchcmd(switch_config).ale_timeout);
+ + 		break;
+ + 
+ + 	case CONFIG_SWITCH_DUMP:
+ + 		ret = cpsw_ale_dump(priv->ale,
+ + 			switchcmd(switch_config).aledump,
+ + 			switch_config->cmd_data.buf, 4095);
+ + 		if (ret)
+ + 			ret = copy_to_user(ifrq->ifr_data, switch_config,
+ + 				sizeof(struct net_switch_config)) ?
+ + 				-EFAULT : 0;
+ + 		break;
+ + 
+ + 	case CONFIG_SWITCH_SET_FLOW_CONTROL:
+ + 		if (portcmd(switch_config).port <= 7) {
+ + 			writel(portcmd(switch_config).port,
+ + 				&priv->regs->flow_control);
+ + 		} else {
+ + 			dev_err(priv->dev, "Invalid Arguments\n");
+ + 			ret = -EFAULT;
+ + 		}
+ + 		break;
+ + 
+ + 	case CONFIG_SWITCH_SET_PRIORITY_MAPPING:
+ + 		if ((priocmd(switch_config).port <= 2) &&
+ + 			(priocmd(switch_config).prio_rx <= 7) &&
+ + 			(priocmd(switch_config).prio_tx <= 7) &&
+ + 			(priocmd(switch_config).prio_switch <= 3)) {
+ + 			ret = cpsw_set_priority_mapping(priv,
+ + 				priocmd(switch_config).port,
+ + 				priocmd(switch_config).prio_rx,
+ + 				priocmd(switch_config).prio_tx,
+ + 				priocmd(switch_config).prio_switch);
+ + 		} else {
+ + 			dev_err(priv->dev, "Invalid Arguments\n");
+ + 			ret = -EFAULT;
+ + 		}
+ + 		break;
+ + 
+ + 	case CONFIG_SWITCH_PORT_STATISTICS_ENABLE:
+ + 		if (portcmd(switch_config).port <= 7) {
+ + 			writel(portcmd(switch_config).port,
+ + 				&priv->regs->stat_port_en);
+ + 			ret = 0;
+ + 		} else {
+ + 			dev_err(priv->dev, "Invalid Arguments\n");
+ + 			ret = -EFAULT;
+ + 		}
+ + 		break;
+ + 
+ + 	case CONFIG_SWITCH_CONFIG_DUMP:
+ + 		cpsw_config_dump(priv, switch_config->cmd_data.buf, 4096);
+ + 		ret = copy_to_user(ifrq->ifr_data, switch_config,
+ + 			sizeof(struct net_switch_config)) ?
+ + 			-EFAULT : 0;
+ + 		break;
+ + 
+ + 	case CONFIG_SWITCH_RATELIMIT:
+ + 		if ((portcmd(switch_config).port <= 2) &&
+ + 				(portcmd(switch_config).enable == 0))
+ + 			ret = cpsw_ale_control_set(priv->ale,
+ + 				portcmd(switch_config).port,
+ + 				ALE_RATE_LIMIT, 0);
+ + 		else if ((portcmd(switch_config).port <= 2) &&
+ + 				((portcmd(switch_config).addr_type
+ + 					== ADDR_TYPE_BROADCAST) ||
+ + 				(portcmd(switch_config).addr_type
+ + 					== ADDR_TYPE_MULTICAST)) &&
+ + 				(portcmd(switch_config).limit <= 255)) {
+ + 			ret = cpsw_rate_limit(priv->ale,
+ + 				portcmd(switch_config).enable,
+ + 				portcmd(switch_config).direction,
+ + 				portcmd(switch_config).port,
+ + 				portcmd(switch_config).addr_type,
+ + 				portcmd(switch_config).limit);
+ + 		} else {
+ + 			dev_err(priv->dev, "Invalid Arguments\n");
+ + 			ret = -EFAULT;
+ + 		}
+ + 		break;
+ + 
+ + 	case CONFIG_SWITCH_VID_INGRESS_CHECK:
+ + 		if (portcmd(switch_config).port <= 2) {
+ + 			cpsw_ale_control_set(priv->ale,
+ + 				portcmd(switch_config).port,
+ + 				ALE_PORT_DROP_UNTAGGED, 1);
+ + 			cpsw_ale_control_set(priv->ale,
+ + 				portcmd(switch_config).port,
+ + 				ALE_PORT_DROP_UNKNOWN_VLAN, 1);
+ + 			ret = 0;
+ + 		} else {
+ + 			dev_err(priv->dev, "Invalid Arguments\n");
+ + 			ret = -EFAULT;
+ + 		}
+ + 		break;
+ + 
+ + 	case CONFIG_SWITCH_ADD_UNKNOWN_VLAN_INFO:
+ + 		if ((portcmd(switch_config).port <= 7) &&
+ + 				(portcmd(switch_config).
+ + 					reg_multi_port_mask <= 7) &&
+ + 				(portcmd(switch_config).
+ + 					unknown_reg_multi_port_mask <= 7) &&
+ + 				(portcmd(switch_config).
+ + 					unknown_vlan_member <= 7)) {
+ + 			cpsw_ale_control_set(priv->ale, 0,
+ + 				ALE_PORT_UNTAGGED_EGRESS,
+ + 				portcmd(switch_config).port);
+ + 			cpsw_ale_control_set(priv->ale, 0,
+ + 				ALE_PORT_UNKNOWN_REG_MCAST_FLOOD,
+ + 				portcmd(switch_config).reg_multi_port_mask);
+ + 			cpsw_ale_control_set(priv->ale, 0,
+ + 				ALE_PORT_UNKNOWN_MCAST_FLOOD,
+ + 				portcmd(switch_config).
+ + 					unknown_reg_multi_port_mask);
+ + 			cpsw_ale_control_set(priv->ale, 0,
+ + 				ALE_PORT_UNKNOWN_VLAN_MEMBER,
+ + 				portcmd(switch_config).unknown_vlan_member);
+ + 			ret = 0;
+ + 		} else {
+ + 			dev_err(priv->dev, "Invalid Arguments\n");
+ + 			ret = -EFAULT;
+ + 		}
+ + 		break;
+ + 
+ + 	case CONFIG_SWITCH_802_1:
+ + 	{
+ + 		char addr_802_1[6] = {0x01, 0x80, 0xc2, 0x0, 0x0, 0x03};
+ + 		if (portcmd(switch_config).enable)
+ + 			ret = cpsw_ale_add_mcast(priv->ale,
+ + 					addr_802_1, 0x7, 0, 0);
+ + 		else
+ + 			ret = cpsw_ale_add_mcast(priv->ale,
+ + 					addr_802_1, 0x3, 0, 0);
+ + 		break;
+ + 	}
+ + 
+ + 	case CONFIG_SWITCH_MACAUTH:
+ + 		ret = cpsw_ale_control_set(priv->ale, priv->host_port,
+ + 			ALE_AUTH_ENABLE, 1);
+ + 		break;
+ + 
+ + 	case CONFIG_SWITCH_SET_PORT_CONFIG:
+ + 	{
+ + 		struct ethtool_cmd ecmd;
+ + 
+ + 		if (portcmd(switch_config).port == 1)
+ + 			if (priv->slaves[0].phy) {
+ + 				ecmd.phy_address = priv->slaves[0].phy->addr;
+ + 				ret = phy_ethtool_gset(priv->slaves[0].phy,
+ + 						&ecmd);
+ + 			} else {
+ + 				dev_err(priv->dev, "Phy not Found\n");
+ + 				ret = -EFAULT;
+ + 				break;
+ + 			}
+ + 		else if (portcmd(switch_config).port == 2)
+ + 			if (priv->slaves[1].phy) {
+ + 				ecmd.phy_address = priv->slaves[1].phy->addr;
+ + 				ret = phy_ethtool_gset(priv->slaves[1].phy,
+ + 						&ecmd);
+ + 			} else {
+ + 				dev_err(priv->dev, "Phy not Found\n");
+ + 				ret = -EFAULT;
+ + 				break;
+ + 			}
+ + 		else {
+ + 			dev_err(priv->dev, "Invalid Arguments\n");
+ + 			ret = -EFAULT;
+ + 			break;
+ + 		}
+ + 
+ + 		if (((portcmd(switch_config).limit == 0) ||
+ + 			(portcmd(switch_config).limit == 10) ||
+ + 			(portcmd(switch_config).limit == 100) ||
+ + 			(portcmd(switch_config).limit == 1000))) {
+ + 
+ + 			if (portcmd(switch_config).limit == 0)
+ + 				ecmd.autoneg = AUTONEG_ENABLE;
+ + 			else {
+ + 				ecmd.autoneg = AUTONEG_DISABLE;
+ + 				ecmd.speed =
+ + 					portcmd(switch_config).limit;
+ + 				if (portcmd(switch_config).direction
+ + 						== 1)
+ + 					ecmd.duplex = DUPLEX_FULL;
+ + 				else
+ + 					ecmd.duplex = DUPLEX_HALF;
+ + 			}
+ + 
+ + 			if (portcmd(switch_config).port == 1)
+ + 				ret = phy_ethtool_sset(priv->slaves[0].phy,
+ + 					&ecmd);
+ + 			else
+ + 				ret = phy_ethtool_sset(priv->slaves[1].phy,
+ + 					&ecmd);
+ + 		} else {
+ + 			dev_err(priv->dev, "Invalid Arguments\n");
+ + 			ret = -EFAULT;
+ + 		}
+ + 		break;
+ + 	}
+ + 
+ + 	case CONFIG_SWITCH_GET_PORT_CONFIG:
+ + 	{
+ + 		struct ethtool_cmd ecmd;
+ + 
+ + 		if (portcmd(switch_config).port == 1)
+ + 			if (priv->slaves[0].phy) {
+ + 				ecmd.phy_address = priv->slaves[0].phy->addr;
+ + 				ret = phy_ethtool_gset(priv->slaves[0].phy,
+ + 						&ecmd);
+ + 			} else {
+ + 				dev_err(priv->dev, "Phy not Found\n");
+ + 				ret = -EFAULT;
+ + 				break;
+ + 			}
+ + 		else if (portcmd(switch_config).port == 2)
+ + 			if (priv->slaves[1].phy) {
+ + 				ecmd.phy_address = priv->slaves[1].phy->addr;
+ + 				ret = phy_ethtool_gset(priv->slaves[1].phy,
+ + 						&ecmd);
+ + 			} else {
+ + 				dev_err(priv->dev, "Phy not Found\n");
+ + 				ret = -EFAULT;
+ + 				break;
+ + 			}
+ + 		else {
+ + 			dev_err(priv->dev, "Invalid Arguments\n");
+ + 			ret = -EFAULT;
+ + 			break;
+ + 		}
+ + 
+ + 		if (!ret) {
+ + 			portcmd(switch_config).limit = ecmd.speed;
+ + 			if (ecmd.duplex == DUPLEX_FULL)
+ + 				portcmd(switch_config).direction = 1;
+ + 			else
+ + 				portcmd(switch_config).direction = 0;
+ + 			ret = copy_to_user(ifrq->ifr_data, switch_config,
+ + 				sizeof(struct net_switch_config)) ?
+ + 				-EFAULT : 0;
+ + 		}
+ + 
+ + 		break;
+ + 	}
+ + 
+ + 	case CONFIG_SWITCH_PORT_STATE:
+ + 		if (portcmd(switch_config).port <= 2) {
+ + 			ret = cpsw_set_port_state(priv,
+ + 				portcmd(switch_config).port,
+ + 				portcmd(switch_config).port_state);
+ + 		} else {
+ + 			dev_err(priv->dev, "Invalid Arguments\n");
+ + 			ret = -EFAULT;
+ + 		}
+ + 		break;
+ + 
+ + 	case CONFIG_SWITCH_RESET:
+ + 		ret = cpsw_ndo_stop(ndev);
+ + 		if (!ret)
+ + 			ret = cpsw_ndo_open(ndev);
+ + 		break;
+ + 
+ + 	default:
+ + 		ret = -EOPNOTSUPP;
+ + 	}
+ + 
+ + 	kfree(switch_config);
+ + 	return ret;
+ + }
+ + 
+ + #else
+ + #define cpsw_switch_config_ioctl(ndev, ifrq, cmd) (-EOPNOTSUPP)
+ + #endif /* CONFIG_TI_CPSW_DUAL_EMAC */
+ + 
+ + static int cpsw_ndo_do_ioctl(struct net_device *ndev, struct ifreq *ifrq,
+ + 		int cmd)
+ + {
+ + 	if (!(netif_running(ndev)))
+ + 		return -EINVAL;
+ + 
+ + 	switch (cmd) {
+ + 
+ + 	case SIOCSWITCHCONFIG:
+ + 		return cpsw_switch_config_ioctl(ndev, ifrq, cmd);
+ + 
+ + #ifdef CONFIG_TI_CPTS
+ + 	case SIOCSHWTSTAMP:
+ + 		return cpsw_hwtstamp_ioctl(ndev, ifrq);
+ + #endif
+ + 
+ + 	default:
+ + 		return -EOPNOTSUPP;
+ + 	}
+ + 	return 0;
+ + }
+ + 
+ + static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
+ + {
+ + 	struct cpsw_priv *priv = netdev_priv(ndev);
+ + 	struct sockaddr *addr = (struct sockaddr *)p;
+ + 
+ + 	if (!is_valid_ether_addr(addr->sa_data))
+ + 		return -EADDRNOTAVAIL;
+ + 
+ + 	cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port);
+ + 
+ + 	memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
+ + 	memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
+ + 
+ + 	cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
+ + 			   0);
+ + 	for_each_slave(priv, cpsw_set_slave_mac, priv);
+ + 
+ + 	/* save the mac address */
+ + 	if(priv->save_mac_addr)
+ + 		priv->save_mac_addr(priv->mac_addr);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static void cpsw_ndo_tx_timeout(struct net_device *ndev)
+ + {
+ + 	struct cpsw_priv *priv = netdev_priv(ndev);
+ + 
+ + 	msg(err, tx_err, "transmit timeout, restarting dma");
+ + 	priv->stats.tx_errors++;
+ + 	cpsw_intr_disable(priv);
+ + 	cpdma_ctlr_int_ctrl(priv->dma, false);
+ + 	cpdma_chan_stop(priv->txch);
+ + 	cpdma_chan_start(priv->txch);
+ + 	cpdma_ctlr_int_ctrl(priv->dma, true);
+ + 	cpsw_intr_enable(priv);
+ + 	cpdma_ctlr_eoi(priv->dma);
+ + }
+ + 
+ + static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev)
+ + {
+ + 	struct cpsw_priv *priv = netdev_priv(ndev);
+ + 	return &priv->stats;
+ + }
+ + 
+ + #ifdef CONFIG_NET_POLL_CONTROLLER
+ + static void cpsw_ndo_poll_controller(struct net_device *ndev)
+ + {
+ + 	struct cpsw_priv *priv = netdev_priv(ndev);
+ + 
+ + 	cpsw_intr_disable(priv);
+ + 	cpdma_ctlr_int_ctrl(priv->dma, false);
+ + 	cpsw_interrupt(ndev->irq, priv);
+ + 	cpdma_ctlr_int_ctrl(priv->dma, true);
+ + 	cpsw_intr_enable(priv);
+ + 	cpdma_ctlr_eoi(priv->dma);
+ + }
+ + #endif
+ + 
+ + /**
+ +  * cpsw_get_coalesce : Get interrupt coalesce settings for this device
+ +  * @ndev : CPSW network adapter
+ +  * @coal : ethtool coalesce settings structure
+ +  *
+ +  * Fetch the current interrupt coalesce settings
+ +  *
+ +  */
+ + static int cpsw_get_coalesce(struct net_device *ndev,
+ + 				struct ethtool_coalesce *coal)
+ + {
+ + 	struct cpsw_priv *priv = netdev_priv(ndev);
+ + 
+ + 	coal->rx_coalesce_usecs = priv->coal_intvl;
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * cpsw_set_coalesce : Set interrupt coalesce settings for this device
+ +  * @ndev : CPSW network adapter
+ +  * @coal : ethtool coalesce settings structure
+ +  *
+ +  * Set interrupt coalesce parameters
+ +  *
+ +  */
+ + static int cpsw_set_coalesce(struct net_device *ndev,
+ + 				struct ethtool_coalesce *coal)
+ + {
+ + 	struct cpsw_priv *priv = netdev_priv(ndev);
+ + 	u32 int_ctrl;
+ + 	u32 num_interrupts = 0;
+ + 	u32 prescale = 0;
+ + 	u32 addnl_dvdr = 1;
+ + 	u32 coal_intvl = 0;
+ + 
+ + 	if (!coal->rx_coalesce_usecs)
+ + 		return -EINVAL;
+ + 
+ + 	coal_intvl = coal->rx_coalesce_usecs;
+ + 
+ + 	int_ctrl =  __raw_readl(&priv->wr_regs->int_control);
+ + 	prescale = priv->bus_freq_mhz * 4;
+ + 
+ + 	if (coal_intvl < CPSW_CMINTMIN_INTVL)
+ + 		coal_intvl = CPSW_CMINTMIN_INTVL;
+ + 
+ + 	if (coal_intvl > CPSW_CMINTMAX_INTVL) {
+ + 		/*
+ + 		 * Interrupt pacer works with 4us Pulse, we can
+ + 		 * throttle further by dilating the 4us pulse.
+ + 		 */
+ + 		addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
+ + 
+ + 		if (addnl_dvdr > 1) {
+ + 			prescale *= addnl_dvdr;
+ + 			if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
+ + 				coal_intvl = (CPSW_CMINTMAX_INTVL
+ + 						* addnl_dvdr);
+ + 		} else {
+ + 			addnl_dvdr = 1;
+ + 			coal_intvl = CPSW_CMINTMAX_INTVL;
+ + 		}
+ + 	}
+ + 
+ + 	num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
+ + 
+ + 	int_ctrl |= CPSW_INTPACEEN;
+ + 	int_ctrl &= (~CPSW_INTPRESCALE_MASK);
+ + 	int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
+ + 	__raw_writel(int_ctrl, &priv->wr_regs->int_control);
+ + 
+ + 	__raw_writel(num_interrupts, &priv->wr_regs->rx_imax);
+ + 	__raw_writel(num_interrupts, &priv->wr_regs->tx_imax);
+ + 
+ + 	printk(KERN_INFO"Set coalesce to %d usecs.\n", coal_intvl);
+ + 	priv->coal_intvl = coal_intvl;
+ + 
+ + 	return 0;
+ + }
+ + 
+ + #ifdef VLAN_SUPPORT
+ + 
+ + #ifdef CONFIG_TI_CPSW_DUAL_EMAC
+ + 
+ + static inline void cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
+ + 					   unsigned short vid)
+ + {
+ + 	cpsw_ale_add_vlan(priv->ale, vid, 1 << priv->host_port |
+ + 			1 << (priv->emac_port + 1), 0,
+ + 			1 << priv->host_port | 1 << (priv->emac_port + 1), 0);
+ + 	cpsw_ale_vlan_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
+ + 			0, vid);
+ + 	cpsw_ale_vlan_add_mcast(priv->ale, priv->ndev->broadcast,
+ + 			1 << priv->host_port | 1 << (priv->emac_port + 1),
+ + 			vid, 0, 0);
+ + }
+ + 
+ + #else
+ + 
+ + static inline void cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
+ + 				unsigned short vid)
+ + {
+ + 	cpsw_ale_add_vlan(priv->ale, vid, ALE_ALL_PORTS << priv->host_port,
+ + 			0, ALE_ALL_PORTS << priv->host_port,
+ + 			(BIT(1) | BIT(2)) << priv->host_port);
+ + 	cpsw_ale_vlan_add_ucast(priv->ale, priv->mac_addr,
+ + 			priv->host_port, 0, vid);
+ + 	cpsw_ale_vlan_add_mcast(priv->ale, priv->ndev->broadcast,
+ + 			ALE_ALL_PORTS << priv->host_port, vid, 0, 0);
+ + }
+ + 
+ + #endif
+ + 
+ + static void cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
+ + 		unsigned short vid)
+ + {
+ + 	struct cpsw_priv *priv = netdev_priv(ndev);
+ + 
+ + 	spin_lock(&priv->lock);
+ + 
+ + 	dev_dbg(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
+ + 	if (vid) {
+ + 		cpsw_add_vlan_ale_entry(priv, vid);
+ + 	} else {
+ + 		cpsw_ale_add_vlan(priv->ale, vid,
+ + 				ALE_ALL_PORTS << priv->host_port,
+ + 				ALE_ALL_PORTS << priv->host_port,
+ + 				ALE_ALL_PORTS << priv->host_port,
+ + 				(BIT(1) | BIT(2)) << priv->host_port);
+ + 	}
+ + 
+ + 	spin_unlock(&priv->lock);
+ + }
+ + 
+ + static void cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
+ + 		unsigned short vid)
+ + {
+ + 	struct cpsw_priv *priv = netdev_priv(ndev);
+ + 
+ + 	spin_lock(&priv->lock);
+ + 
+ + 	dev_dbg(priv->dev, "removing vlanid %d from vlan filter\n", vid);
+ + 	cpsw_ale_del_vlan(priv->ale, vid, ALE_ALL_PORTS << priv->host_port);
+ + 	cpsw_ale_vlan_del_ucast(priv->ale, priv->mac_addr,
+ + 				priv->host_port, vid);
+ + 	cpsw_ale_vlan_del_mcast(priv->ale, priv->ndev->broadcast, 0, vid);
+ + 
+ + 	spin_unlock(&priv->lock);
+ + }
+ + 
+ + #endif /* VLAN_SUPPORT */
+ + 
+ + static const struct net_device_ops cpsw_netdev_ops = {
+ + 	.ndo_open		= cpsw_ndo_open,
+ + 	.ndo_stop		= cpsw_ndo_stop,
+ + 	.ndo_start_xmit		= cpsw_ndo_start_xmit,
+ + 	.ndo_change_rx_flags	= cpsw_ndo_change_rx_flags,
+ + 	.ndo_set_mac_address	= cpsw_ndo_set_mac_address,
+ + 	.ndo_do_ioctl		= cpsw_ndo_do_ioctl,
+ + 	.ndo_validate_addr	= eth_validate_addr,
+ + 	.ndo_tx_timeout		= cpsw_ndo_tx_timeout,
+ + 	.ndo_get_stats		= cpsw_ndo_get_stats,
+ + 	.ndo_set_rx_mode	= cpsw_ndo_set_rx_mode,
+ + #ifdef CONFIG_NET_POLL_CONTROLLER
+ + 	.ndo_poll_controller	= cpsw_ndo_poll_controller,
+ + #endif
+ + #ifdef VLAN_SUPPORT
+ + 	.ndo_vlan_rx_add_vid	= cpsw_ndo_vlan_rx_add_vid,
+ + 	.ndo_vlan_rx_kill_vid	= cpsw_ndo_vlan_rx_kill_vid,
+ + #endif
+ + };
+ + 
+ + static void cpsw_get_drvinfo(struct net_device *ndev,
+ + 			     struct ethtool_drvinfo *info)
+ + {
+ + 	struct cpsw_priv *priv = netdev_priv(ndev);
+ + 	strcpy(info->driver, "TI CPSW Driver v1.0");
+ + 	strcpy(info->version, "1.0");
+ + 	strcpy(info->bus_info, priv->pdev->name);
+ + }
+ + 
+ + static u32 cpsw_get_msglevel(struct net_device *ndev)
+ + {
+ + 	struct cpsw_priv *priv = netdev_priv(ndev);
+ + 	return priv->msg_enable;
+ + }
+ + 
+ + static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
+ + {
+ + 	struct cpsw_priv *priv = netdev_priv(ndev);
+ + 	priv->msg_enable = value;
+ + }
+ + 
+ + /**
+ +  * cpsw_get_settings: Get EMAC settings
+ +  * @ndev: CPSW network adapter
+ +  * @ecmd: ethtool command
+ +  *
+ +  * Executes ethool get command
+ +  *
+ +  */
+ + static int cpsw_get_settings(struct net_device *ndev,
+ + 			     struct ethtool_cmd *ecmd)
+ + {
+ + 	struct cpsw_priv *priv = netdev_priv(ndev);
+ + 	int slave_no = cpsw_slave_phy_index(priv);
+ + 
+ + 	if (priv->slaves[slave_no].phy)
+ + 		return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
+ + 	else
+ + 		return -EOPNOTSUPP;
+ + }
+ + 
+ + /**
+ +  * cpsw_set_settings: Set EMAC settings
+ +  * @ndev: CPSW network adapter
+ +  * @ecmd: ethtool command
+ +  *
+ +  * Executes ethool set command
+ +  *
+ +  */
+ + static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
+ + {
+ + 	struct cpsw_priv *priv = netdev_priv(ndev);
+ + 	int slave_no = cpsw_slave_phy_index(priv);
+ + 
+ + 	if (priv->slaves[slave_no].phy)
+ + 		return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
+ + 	else
+ + 		return -EOPNOTSUPP;
+ + }
+ + 
+ + static const struct ethtool_ops cpsw_ethtool_ops = {
+ + 	.get_drvinfo	= cpsw_get_drvinfo,
+ + 	.get_msglevel	= cpsw_get_msglevel,
+ + 	.set_msglevel	= cpsw_set_msglevel,
+ + 	.get_link	= ethtool_op_get_link,
+ + 	.get_settings	= cpsw_get_settings,
+ + 	.set_settings	= cpsw_set_settings,
+ + 	.get_coalesce	= cpsw_get_coalesce,
+ + 	.set_coalesce	= cpsw_set_coalesce,
+ + };
+ + 
+ + static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv)
+ + {
+ + 	void __iomem		*regs = priv->regs;
+ + 	int			slave_num = slave->slave_num;
+ + 	struct cpsw_slave_data	*data = priv->data.slave_data + slave_num;
+ + 
+ + 	slave->data	= data;
+ + 	slave->regs	= regs + data->slave_reg_ofs;
+ + 	slave->sliver	= regs + data->sliver_reg_ofs;
+ + 	slave->port_vlan = data->dual_emac_reserved_vlan;
+ + }
+ + 
+ + #ifdef CONFIG_TI_CPSW_DUAL_EMAC
+ + 
+ + static int cpsw_init_slave_emac(struct platform_device *pdev,
+ + 				struct cpsw_priv *priv)
+ + {
+ + 	struct cpsw_platform_data	*data = pdev->dev.platform_data;
+ + 	struct net_device		*ndev;
+ + 	struct cpsw_priv		*priv_sl2;
+ + 	int ret = 0, i;
+ + 
+ + 	ndev = alloc_etherdev(sizeof(struct cpsw_priv));
+ + 	if (!ndev) {
+ + 		pr_err("cpsw: error allocating net_device\n");
+ + 		return -ENOMEM;
+ + 	}
+ + 
+ + 	priv_sl2 = netdev_priv(ndev);
+ + 	spin_lock_init(&priv_sl2->lock);
+ + 	priv_sl2->data = *data;
+ + 	priv_sl2->pdev = pdev;
+ + 	priv_sl2->ndev = ndev;
+ + 	priv_sl2->dev  = &ndev->dev;
+ + 	priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
+ + 	priv_sl2->rx_packet_max = max(rx_packet_max, 128);
+ + 
+ + 	if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
+ + 		memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
+ + 			ETH_ALEN);
+ + 		pr_info("cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
+ + 	} else {
+ + 		random_ether_addr(priv_sl2->mac_addr);
+ + 		pr_info("cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
+ + 	}
+ + 	memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
+ + 
+ + 	priv_sl2->slaves = priv->slaves;
+ + 	priv_sl2->clk = priv->clk;
+ + 
+ + 	priv_sl2->coal_intvl = 0;
+ + 	priv_sl2->bus_freq_mhz = clk_get_rate(priv_sl2->clk) / 1000000;
+ + 
+ + 	priv_sl2->cpsw_res = priv->cpsw_res;
+ + 	priv_sl2->regs = priv->regs;
+ + 	priv_sl2->host_port = priv->host_port;
+ + 	priv_sl2->host_port_regs = priv->host_port_regs;
+ + 	priv_sl2->hw_stats = priv->hw_stats;
+ + 	priv_sl2->cpsw_ss_res = priv->cpsw_ss_res;
+ + 	priv_sl2->wr_regs = priv->wr_regs;
+ + 	priv_sl2->dma = priv->dma;
+ + 	priv_sl2->txch = priv->txch;
+ + 	priv_sl2->rxch = priv->rxch;
+ + 	priv_sl2->ale = priv->ale;
+ + 	priv_sl2->emac_port = 1;
+ + 	priv->slaves[1].ndev = ndev;
+ + 	priv_sl2->cpts = priv->cpts;
+ + 	for_each_slave(priv_sl2, cpsw_slave_init, priv_sl2);
+ + 
+ + 	for (i = 0; i < priv->num_irqs; i++) {
+ + 		priv_sl2->irqs_table[i] = priv->irqs_table[i];
+ + 		priv_sl2->num_irqs = priv->num_irqs;
+ + 	}
+ + 
+ + #ifdef VLAN_SUPPORT
+ + 	ndev->features |= NETIF_F_HW_VLAN_FILTER;
+ + #endif
+ + 
+ + 	ndev->flags |= IFF_ALLMULTI;	/* see cpsw_ndo_change_rx_flags() */
+ + 
+ + 	ndev->netdev_ops = &cpsw_netdev_ops;
+ + 	SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops);
+ + 	netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT);
+ + 
+ + 	/* register the network device */
+ + 	SET_NETDEV_DEV(ndev, &pdev->dev);
+ + 	ret = register_netdev(ndev);
+ + 	if (ret) {
+ + 		pr_err("cpsw: error registering net device\n");
+ + 		ret = -ENODEV;
+ + 	}
+ + 
+ + 	return ret;
+ + }
+ + 
+ + static inline void cpsw_deinit_slave_emac(struct cpsw_priv *priv)
+ + {
+ + 	struct net_device *ndev = priv->slaves[1].ndev;
+ + 
+ + 	unregister_netdev(ndev);
+ + 	free_netdev(ndev);
+ + }
+ + 
+ + #else
+ + #define cpsw_init_slave_emac(pdev, priv)	0
+ + #define cpsw_deinit_slave_emac(priv)
+ + #endif
+ + 
+ + static int __devinit cpsw_probe(struct platform_device *pdev)
+ + {
+ + 	struct cpsw_platform_data	*data = pdev->dev.platform_data;
+ + 	struct net_device		*ndev;
+ + 	struct cpsw_priv		*priv;
+ + 	struct cpdma_params		dma_params;
+ + 	struct cpsw_ale_params		ale_params;
+ + 	void __iomem			*regs;
+ + 	int ret = 0, i, k = 0;
+ + 
+ + 	if (!data) {
+ + 		pr_err("cpsw: platform data missing\n");
+ + 		return -ENODEV;
+ + 	}
+ + 
+ + 	ndev = alloc_etherdev(sizeof(struct cpsw_priv));
+ + 	if (!ndev) {
+ + 		pr_err("cpsw: error allocating net_device\n");
+ + 		return -ENOMEM;
+ + 	}
+ + 
+ + 	platform_set_drvdata(pdev, ndev);
+ + 	priv = netdev_priv(ndev);
+ + 	spin_lock_init(&priv->lock);
+ + 	priv->data = *data;
+ + 	priv->pdev = pdev;
+ + 	priv->ndev = ndev;
+ + 	priv->dev  = &ndev->dev;
+ + 	priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
+ + 	priv->rx_packet_max = max(rx_packet_max, 128);
+ + 	priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
+ + 
+ + 	if (is_valid_ether_addr(data->mac_addr)) {
+ + 		memcpy(priv->mac_addr, data->mac_addr, ETH_ALEN);
+ + 		printk(KERN_INFO"Detected MACID=%x:%x:%x:%x:%x:%x\n",
+ + 			priv->mac_addr[0], priv->mac_addr[1],
+ + 			priv->mac_addr[2], priv->mac_addr[3],
+ + 			priv->mac_addr[4], priv->mac_addr[5]);
+ + 	} else {
+ + 		random_ether_addr(priv->mac_addr);
+ + 		printk(KERN_INFO"Random MACID=%x:%x:%x:%x:%x:%x\n",
+ + 			priv->mac_addr[0], priv->mac_addr[1],
+ + 			priv->mac_addr[2], priv->mac_addr[3],
+ + 			priv->mac_addr[4], priv->mac_addr[5]);
+ + 	}
+ + 
+ + 	memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
+ + 
+ + 	priv->slaves = kzalloc(sizeof(struct cpsw_slave) * data->slaves,
+ + 			       GFP_KERNEL);
+ + 	if (!priv->slaves) {
+ + 		dev_err(priv->dev, "failed to allocate slave ports\n");
+ + 		ret = -EBUSY;
+ + 		goto clean_ndev_ret;
+ + 	}
+ + 	for (i = 0; i < data->slaves; i++)
+ + 		priv->slaves[i].slave_num = i;
+ + 
+ + 	priv->slaves[0].ndev = ndev;
+ + 	priv->emac_port = 0;
+ + 
+ + 	pm_runtime_enable(&pdev->dev);
+ + 	pm_runtime_get_sync(&pdev->dev);
+ + 	priv->clk = clk_get(&pdev->dev, "fck");
+ + 	if (IS_ERR(priv->clk)) {
+ + 		dev_err(&pdev->dev, "fck is not found\n");
+ + 		ret = -ENODEV;
+ + 		goto clean_slave_ret;
+ + 	}
+ + 
+ + 	priv->coal_intvl = 0;
+ + 	priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
+ + 
+ + 	priv->cpsw_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ + 	if (!priv->cpsw_res) {
+ + 		dev_err(priv->dev, "error getting i/o resource\n");
+ + 		ret = -ENOENT;
+ + 		goto clean_clk_ret;
+ + 	}
+ + 
+ + 	if (!request_mem_region(priv->cpsw_res->start,
+ + 		resource_size(priv->cpsw_res), ndev->name)) {
+ + 		dev_err(priv->dev, "failed request i/o region\n");
+ + 		ret = -ENXIO;
+ + 		goto clean_clk_ret;
+ + 	}
+ + 
+ + 	regs = ioremap(priv->cpsw_res->start, resource_size(priv->cpsw_res));
+ + 	if (!regs) {
+ + 		dev_err(priv->dev, "unable to map i/o region\n");
+ + 		goto clean_cpsw_iores_ret;
+ + 	}
+ + 	priv->regs = regs;
+ + 	priv->host_port = data->host_port_num;
+ + 	priv->host_port_regs = regs + data->host_port_reg_ofs;
+ + 	priv->hw_stats = regs + data->hw_stats_reg_ofs;
+ + 	priv->cpts->reg = regs + data->cpts_reg_ofs;
+ + 	priv->save_mac_addr = data->save_mac_addr;
+ + 
+ + 	priv->cpsw_ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ + 	if (!priv->cpsw_ss_res) {
+ + 		dev_err(priv->dev, "error getting i/o resource\n");
+ + 		ret = -ENOENT;
+ + 		goto clean_clk_ret;
+ + 	}
+ + 
+ + 	if (!request_mem_region(priv->cpsw_ss_res->start,
+ + 		resource_size(priv->cpsw_ss_res), ndev->name)) {
+ + 		dev_err(priv->dev, "failed request i/o region\n");
+ + 		ret = -ENXIO;
+ + 		goto clean_clk_ret;
+ + 	}
+ + 
+ + 	regs = ioremap(priv->cpsw_ss_res->start,
+ + 			resource_size(priv->cpsw_ss_res));
+ + 	if (!regs) {
+ + 		dev_err(priv->dev, "unable to map i/o region\n");
+ + 		goto clean_cpsw_ss_iores_ret;
+ + 	}
+ + 	priv->wr_regs = regs;
+ + 
+ + 	for_each_slave(priv, cpsw_slave_init, priv);
+ + 
+ + 	omap_ctrl_writel(CPSW_TIMER_MASK, CPSW_TIMER_CAP_REG);
+ + 
+ + 	dmtimer_rx = omap_dm_timer_request_specific(CPSW_RX_TIMER_REQ);
+ + 	if (!dmtimer_rx) {
+ + 		dev_err(priv->dev, "Error getting Rx Timer resource\n");
+ + 		ret = -ENODEV;
+ + 		goto clean_iomap_ret;
+ + 	}
+ + 	dmtimer_tx = omap_dm_timer_request_specific(CPSW_TX_TIMER_REQ);
+ + 	if (!dmtimer_tx) {
+ + 		dev_err(priv->dev, "Error getting Tx Timer resource\n");
+ + 		ret = -ENODEV;
+ + 		goto clean_timer_rx_ret;
+ + 	}
+ + 
+ + 	memset(&dma_params, 0, sizeof(dma_params));
+ + 	dma_params.dev			= &pdev->dev;
+ + 	dma_params.dmaregs		= (void __iomem *)(((u32)priv->regs) +
+ + 						data->cpdma_reg_ofs);
+ + 	dma_params.rxthresh		= (void __iomem *)(((u32)priv->regs) +
+ + 					data->cpdma_reg_ofs + CPDMA_RXTHRESH);
+ + 	dma_params.rxfree		= (void __iomem *)(((u32)priv->regs) +
+ + 					data->cpdma_reg_ofs + CPDMA_RXFREE);
+ + 
+ + 	if (data->version == CPSW_VERSION_2) {
+ + 		dma_params.txhdp	= (void __iomem *)(((u32)priv->regs) +
+ + 					data->cpdma_reg_ofs + CPDMA_TXHDP_VER2);
+ + 		dma_params.rxhdp	= (void __iomem *)(((u32)priv->regs) +
+ + 					data->cpdma_reg_ofs + CPDMA_RXHDP_VER2);
+ + 		dma_params.txcp		= (void __iomem *)(((u32)priv->regs) +
+ + 					data->cpdma_reg_ofs + CPDMA_TXCP_VER2);
+ + 		dma_params.rxcp		= (void __iomem *)(((u32)priv->regs) +
+ + 					data->cpdma_reg_ofs + CPDMA_RXCP_VER2);
+ + 	} else {
+ + 		dma_params.txhdp	= (void __iomem *)(((u32)priv->regs) +
+ + 					data->cpdma_reg_ofs + CPDMA_TXHDP_VER1);
+ + 		dma_params.rxhdp	= (void __iomem *)(((u32)priv->regs) +
+ + 					data->cpdma_reg_ofs + CPDMA_RXHDP_VER1);
+ + 		dma_params.txcp		= (void __iomem *)(((u32)priv->regs) +
+ + 					data->cpdma_reg_ofs + CPDMA_TXCP_VER1);
+ + 		dma_params.rxcp		= (void __iomem *)(((u32)priv->regs) +
+ + 					data->cpdma_reg_ofs + CPDMA_RXCP_VER1);
+ + 	}
+ + 
+ + 	dma_params.num_chan		= data->channels;
+ + 	dma_params.has_soft_reset	= true;
+ + 	dma_params.min_packet_size	= CPSW_MIN_PACKET_SIZE;
+ + 	dma_params.desc_mem_size	= data->bd_ram_size;
+ + 	dma_params.desc_align		= 16;
+ + 	dma_params.has_ext_regs		= true;
+ + 	dma_params.desc_mem_phys	= data->no_bd_ram ? 0 :
+ + 			(u32 __force)priv->cpsw_res->start + data->bd_ram_ofs;
+ + 	dma_params.desc_hw_addr		= data->hw_ram_addr ?
+ + 				data->hw_ram_addr : dma_params.desc_mem_phys ;
+ + 
+ + 	priv->dma = cpdma_ctlr_create(&dma_params);
+ + 	if (!priv->dma) {
+ + 		dev_err(priv->dev, "error initializing dma\n");
+ + 		ret = -ENOMEM;
+ + 		goto clean_timer_ret;
+ + 	}
+ + 
+ + 	priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
+ + 				       cpsw_tx_handler);
+ + 	priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
+ + 				       cpsw_rx_handler);
+ + 
+ + 	if (WARN_ON(!priv->txch || !priv->rxch)) {
+ + 		dev_err(priv->dev, "error initializing dma channels\n");
+ + 		ret = -ENOMEM;
+ + 		goto clean_dma_ret;
+ + 	}
+ + 
+ + 	memset(&ale_params, 0, sizeof(ale_params));
+ + 	ale_params.dev		= &ndev->dev;
+ + 	ale_params.ale_regs	= (void *)((u32)priv->regs) +
+ + 					((u32)data->ale_reg_ofs);
+ + 	ale_params.ale_ageout	= ale_ageout;
+ + 	ale_params.ale_entries	= data->ale_entries;
+ + 	ale_params.ale_ports	= data->slaves;
+ + 
+ + 	priv->ale = cpsw_ale_create(&ale_params);
+ + 	if (!priv->ale) {
+ + 		dev_err(priv->dev, "error initializing ale engine\n");
+ + 		ret = -ENODEV;
+ + 		goto clean_dma_ret;
+ + 	}
+ + 
+ + 	while ((i = platform_get_irq(pdev, k)) >= 0) {
+ + 		if (request_irq(i, cpsw_interrupt, IRQF_DISABLED,
+ + 				dev_name(&pdev->dev), priv)) {
+ + 			dev_err(priv->dev, "error attaching irq\n");
+ + 			goto clean_ale_ret;
+ + 		}
+ + 		priv->irqs_table[k] = i;
+ + 		priv->num_irqs = ++k;
+ + 	}
+ + 
+ + #ifdef VLAN_SUPPORT
+ + 	ndev->features |= NETIF_F_HW_VLAN_FILTER;
+ + #endif
+ + 
+ + 	ndev->flags |= IFF_ALLMULTI;	/* see cpsw_ndo_change_rx_flags() */
+ + 
+ + 	ndev->netdev_ops = &cpsw_netdev_ops;
+ + 	SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops);
+ + 	netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);
+ + 
+ + 	/* register the network device */
+ + 	SET_NETDEV_DEV(ndev, &pdev->dev);
+ + 	ret = register_netdev(ndev);
+ + 	if (ret) {
+ + 		dev_err(priv->dev, "error registering net device\n");
+ + 		ret = -ENODEV;
+ + 		goto clean_irq_ret;
+ + 	}
+ + 
+ + 	msg(notice, probe, "initialized device (regs %x, irq %d)\n",
+ + 	    priv->cpsw_res->start, ndev->irq);
+ + 
+ + 	ret = cpsw_init_slave_emac(pdev, priv);
+ + 	if (ret) {
+ + 		dev_err(priv->dev, "error probe slave 2 emac interface\n");
+ + 		goto clean_irq_ret;
+ + 	}
+ + 
+ + 	return 0;
+ + 
+ + clean_irq_ret:
+ + 	free_irq(ndev->irq, priv);
+ + clean_ale_ret:
+ + 	cpsw_ale_destroy(priv->ale);
+ + clean_dma_ret:
+ + 	cpdma_chan_destroy(priv->txch);
+ + 	cpdma_chan_destroy(priv->rxch);
+ + 	cpdma_ctlr_destroy(priv->dma);
+ + clean_timer_ret:
+ + 	omap_dm_timer_free(dmtimer_tx);
+ + clean_timer_rx_ret:
+ + 	omap_dm_timer_free(dmtimer_rx);
+ + clean_iomap_ret:
+ + 	iounmap(priv->regs);
+ + clean_cpsw_ss_iores_ret:
+ + 	release_mem_region(priv->cpsw_ss_res->start,
+ + 				resource_size(priv->cpsw_ss_res));
+ + clean_cpsw_iores_ret:
+ + 	release_mem_region(priv->cpsw_res->start,
+ + 				resource_size(priv->cpsw_res));
+ + clean_clk_ret:
+ + 	clk_put(priv->clk);
+ + clean_slave_ret:
+ + 	pm_runtime_get_sync(&pdev->dev);
+ + 	pm_runtime_disable(&pdev->dev);
+ + 	kfree(priv->slaves);
+ + clean_ndev_ret:
+ + 	free_netdev(ndev);
+ + 	return ret;
+ + }
+ + 
+ + static int __devexit cpsw_remove(struct platform_device *pdev)
+ + {
+ + 	struct net_device *ndev = platform_get_drvdata(pdev);
+ + 	struct cpsw_priv *priv = netdev_priv(ndev);
+ + 	u32 i;
+ + 
+ + 	msg(notice, probe, "removing device\n");
+ + 	platform_set_drvdata(pdev, NULL);
+ + 
+ + 	cpsw_deinit_slave_emac(priv);
+ + 	omap_dm_timer_free(dmtimer_rx);
+ + 	omap_dm_timer_free(dmtimer_tx);
+ + 	for (i = 0; i < priv->num_irqs; i++)
+ + 		free_irq(priv->irqs_table[i], priv);
+ + 	cpsw_ale_destroy(priv->ale);
+ + 	cpdma_chan_destroy(priv->txch);
+ + 	cpdma_chan_destroy(priv->rxch);
+ + 	cpdma_ctlr_destroy(priv->dma);
+ + 	iounmap(priv->regs);
+ + 	release_mem_region(priv->cpsw_res->start,
+ + 				resource_size(priv->cpsw_res));
+ + 	release_mem_region(priv->cpsw_ss_res->start,
+ + 				resource_size(priv->cpsw_ss_res));
+ + 	pm_runtime_put_sync(&pdev->dev);
+ + 	pm_runtime_disable(&pdev->dev);
+ + 	clk_put(priv->clk);
+ + 	kfree(priv->slaves);
+ + 	unregister_netdev(ndev);
+ + 	free_netdev(ndev);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + #ifdef CONFIG_TI_CPSW_DUAL_EMAC
+ + 
+ + static inline void cpsw_start_slaves_interface(struct net_device *ndev)
+ + {
+ + 	struct cpsw_priv *priv = netdev_priv(ndev);
+ + 	u32 i = 0;
+ + 
+ + 	for (i = 0; i < priv->data.slaves; i++) {
+ + 		ndev = cpsw_get_slave_ndev(priv, i);
+ + 		if (netif_running(ndev))
+ + 			cpsw_ndo_open(ndev);
+ + 	}
+ + }
+ + 
+ + static inline void cpsw_stop_slaves_interface(struct net_device *ndev)
+ + {
+ + 	u32 i = 0;
+ + 	struct cpsw_priv *priv = netdev_priv(ndev);
+ + 
+ + 	for (i = 0; i < priv->data.slaves; i++) {
+ + 		ndev = cpsw_get_slave_ndev(priv, i);
+ + 		if (netif_running(ndev))
+ + 			cpsw_ndo_stop(ndev);
+ + 	}
+ + }
+ + 
+ + #else
+ + 
+ + #define cpsw_start_slaves_interface(ndev)		\
+ + 	if (netif_running(ndev))			\
+ + 		cpsw_ndo_open(ndev)
+ + #define cpsw_stop_slaves_interface(ndev)		\
+ + 	if (netif_running(ndev))			\
+ + 		cpsw_ndo_stop(ndev)
+ + 
+ + #endif
+ + 
+ + static int cpsw_suspend(struct device *dev)
+ + {
+ + 	struct platform_device	*pdev = to_platform_device(dev);
+ + 	struct net_device	*ndev = platform_get_drvdata(pdev);
+ + 
+ + 	cpsw_stop_slaves_interface(ndev);
+ + 	pm_runtime_put_sync(&pdev->dev);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static int cpsw_resume(struct device *dev)
+ + {
+ + 	struct platform_device	*pdev = to_platform_device(dev);
+ + 	struct net_device	*ndev = platform_get_drvdata(pdev);
+ + 
+ + 	pm_runtime_get_sync(&pdev->dev);
+ + 	cpsw_start_slaves_interface(ndev);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static const struct dev_pm_ops cpsw_pm_ops = {
+ + 	.suspend	= cpsw_suspend,
+ + 	.resume		= cpsw_resume,
+ + };
+ + 
+ + static struct platform_driver cpsw_driver = {
+ + 	.driver = {
+ + 		.name	 = "cpsw",
+ + 		.owner	 = THIS_MODULE,
+ + 		.pm	 = &cpsw_pm_ops,
+ + 	},
+ + 	.probe = cpsw_probe,
+ + 	.remove = __devexit_p(cpsw_remove),
+ + };
+ + 
+ + static int __init cpsw_init(void)
+ + {
+ + 	return platform_driver_register(&cpsw_driver);
+ + }
+ + late_initcall(cpsw_init);
+ + 
+ + static void __exit cpsw_exit(void)
+ + {
+ + 	platform_driver_unregister(&cpsw_driver);
+ + }
+ + module_exit(cpsw_exit);
+ + 
+ + MODULE_LICENSE("GPL");
+ + MODULE_DESCRIPTION("TI CPSW Ethernet driver");
+ diff -crN linux-3.2.1_o/drivers/net/ethernet/ti/cpts.c linux-3.2.1/drivers/net/ethernet/ti/cpts.c
+ *** linux-3.2.1_o/drivers/net/ethernet/ti/cpts.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/drivers/net/ethernet/ti/cpts.c	2014-11-25 13:19:15.774992296 +0900
+ ***************
+ *** 0 ****
+ --- 1,425 ----
+ + /*
+ +  * TI Common Platform Time Sync
+ +  *
+ +  * Copyright (C) 2012 Richard Cochran <richardcochran@gmail.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; either version 2 of the License, or
+ +  * (at your option) any later version.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ +  */
+ + #include <linux/err.h>
+ + #include <linux/if.h>
+ + #include <linux/hrtimer.h>
+ + #include <linux/module.h>
+ + #include <linux/net_tstamp.h>
+ + #include <linux/ptp_classify.h>
+ + #include <linux/time.h>
+ + #include <linux/uaccess.h>
+ + #include <linux/workqueue.h>
+ + 
+ + #include <plat/clock.h>
+ + 
+ + #include "cpts.h"
+ + 
+ + #ifdef CONFIG_TI_CPTS
+ + 
+ + static struct sock_filter ptp_filter[] = {
+ + 	PTP_FILTER
+ + };
+ + 
+ + #define cpts_read32(c, r)	__raw_readl(&c->reg->r)
+ + #define cpts_write32(c, v, r)	__raw_writel(v, &c->reg->r)
+ + 
+ + static int event_expired(struct cpts_event *event)
+ + {
+ + 	return time_after(jiffies, event->tmo);
+ + }
+ + 
+ + static int event_type(struct cpts_event *event)
+ + {
+ + 	return (event->high >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
+ + }
+ + 
+ + static int cpts_fifo_pop(struct cpts *cpts, u32 *high, u32 *low)
+ + {
+ + 	u32 r = cpts_read32(cpts, intstat_raw);
+ + 
+ + 	if (r & TS_PEND_RAW) {
+ + 		*high = cpts_read32(cpts, event_high);
+ + 		*low  = cpts_read32(cpts, event_low);
+ + 		cpts_write32(cpts, EVENT_POP, event_pop);
+ + 		return 0;
+ + 	}
+ + 	return -1;
+ + }
+ + 
+ + /*
+ +  * Returns zero if matching event type was found.
+ +  */
+ + static int cpts_fifo_read(struct cpts *cpts, int match)
+ + {
+ + 	int i, type = -1;
+ + 	u32 hi, lo;
+ + 	struct cpts_event *event;
+ + 
+ + 	for (i = 0; i < CPTS_FIFO_DEPTH; i++) {
+ + 		if (cpts_fifo_pop(cpts, &hi, &lo))
+ + 			break;
+ + 		if (list_empty(&cpts->pool)) {
+ + 			pr_err("cpts: event pool is empty\n");
+ + 			return -1;
+ + 		}
+ + 		event = list_first_entry(&cpts->pool, struct cpts_event, list);
+ + 		event->tmo = jiffies + 2;
+ + 		event->high = hi;
+ + 		event->low = lo;
+ + 		type = event_type(event);
+ + 		switch (type) {
+ + 		case CPTS_EV_PUSH:
+ + 		case CPTS_EV_RX:
+ + 		case CPTS_EV_TX:
+ + 			list_del_init(&event->list);
+ + 			list_add_tail(&event->list, &cpts->events);
+ + 			break;
+ + 		case CPTS_EV_ROLL:
+ + 		case CPTS_EV_HALF:
+ + 		case CPTS_EV_HW:
+ + 			break;
+ + 		default:
+ + 			pr_err("cpts: unkown event type\n");
+ + 			break;
+ + 		}
+ + 		if (type == match)
+ + 			break;
+ + 	}
+ + 	return type == match ? 0 : -1;
+ + }
+ + 
+ + static cycle_t cpts_systim_read(const struct cyclecounter *cc)
+ + {
+ + 	u64 val = 0;
+ + 	struct cpts_event *event;
+ + 	struct list_head *this, *next;
+ + 	struct cpts *cpts = container_of(cc, struct cpts, cc);
+ + 
+ + 	cpts_write32(cpts, TS_PUSH, ts_push);
+ + 	if (cpts_fifo_read(cpts, CPTS_EV_PUSH))
+ + 		pr_err("cpts: unable to obtain a time stamp\n");
+ + 
+ + 	list_for_each_safe(this, next, &cpts->events) {
+ + 		event = list_entry(this, struct cpts_event, list);
+ + 		if (event_type(event) == CPTS_EV_PUSH) {
+ + 			list_del_init(&event->list);
+ + 			list_add(&event->list, &cpts->pool);
+ + 			val = event->low;
+ + 			break;
+ + 		}
+ + 	}
+ + 
+ + 	return val;
+ + }
+ + 
+ + /* PTP clock operations */
+ + 
+ + static int cpts_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
+ + {
+ + 	u64 adj;
+ + 	u32 diff, mult;
+ + 	int neg_adj = 0;
+ + 	unsigned long flags;
+ + 	struct cpts *cpts = container_of(ptp, struct cpts, info);
+ + 
+ + 	if (ppb < 0) {
+ + 		neg_adj = 1;
+ + 		ppb = -ppb;
+ + 	}
+ + 	mult = cpts->cc_mult;
+ + 	adj = mult;
+ + 	adj *= ppb;
+ + 	diff = div_u64(adj, 1000000000ULL);
+ + 
+ + 	spin_lock_irqsave(&cpts->lock, flags);
+ + 
+ + 	timecounter_read(&cpts->tc);
+ + 
+ + 	cpts->cc.mult = neg_adj ? mult - diff : mult + diff;
+ + 
+ + 	spin_unlock_irqrestore(&cpts->lock, flags);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static int cpts_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
+ + {
+ + 	s64 now;
+ + 	unsigned long flags;
+ + 	struct cpts *cpts = container_of(ptp, struct cpts, info);
+ + 
+ + 	spin_lock_irqsave(&cpts->lock, flags);
+ + 	now = timecounter_read(&cpts->tc);
+ + 	now += delta;
+ + 	timecounter_init(&cpts->tc, &cpts->cc, now);
+ + 	spin_unlock_irqrestore(&cpts->lock, flags);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static int cpts_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
+ + {
+ + 	u64 ns;
+ + 	u32 remainder;
+ + 	unsigned long flags;
+ + 	struct cpts *cpts = container_of(ptp, struct cpts, info);
+ + 
+ + 	spin_lock_irqsave(&cpts->lock, flags);
+ + 	ns = timecounter_read(&cpts->tc);
+ + 	spin_unlock_irqrestore(&cpts->lock, flags);
+ + 
+ + 	ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
+ + 	ts->tv_nsec = remainder;
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static int cpts_ptp_settime(struct ptp_clock_info *ptp,
+ + 			    const struct timespec *ts)
+ + {
+ + 	u64 ns;
+ + 	unsigned long flags;
+ + 	struct cpts *cpts = container_of(ptp, struct cpts, info);
+ + 
+ + 	ns = ts->tv_sec * 1000000000ULL;
+ + 	ns += ts->tv_nsec;
+ + 
+ + 	spin_lock_irqsave(&cpts->lock, flags);
+ + 	timecounter_init(&cpts->tc, &cpts->cc, ns);
+ + 	spin_unlock_irqrestore(&cpts->lock, flags);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static int cpts_ptp_enable(struct ptp_clock_info *ptp,
+ + 			   struct ptp_clock_request *rq, int on)
+ + {
+ + 	return -EOPNOTSUPP;
+ + }
+ + 
+ + static struct ptp_clock_info cpts_info = {
+ + 	.owner		= THIS_MODULE,
+ + 	.name		= "CTPS timer",
+ + 	.max_adj	= 1000000,
+ + 	.n_ext_ts	= 0,
+ + 	.pps		= 0,
+ + 	.adjfreq	= cpts_ptp_adjfreq,
+ + 	.adjtime	= cpts_ptp_adjtime,
+ + 	.gettime	= cpts_ptp_gettime,
+ + 	.settime	= cpts_ptp_settime,
+ + 	.enable		= cpts_ptp_enable,
+ + };
+ + 
+ + static void cpts_overflow_check(struct work_struct *work)
+ + {
+ + 	struct timespec ts;
+ + 	struct cpts *cpts = container_of(work, struct cpts, overflow_work.work);
+ + 
+ + 	cpts_write32(cpts, CPTS_EN, control);
+ + 	cpts_write32(cpts, TS_PEND_EN, int_enable);
+ + 	cpts_ptp_gettime(&cpts->info, &ts);
+ + 	pr_debug("cpts overflow check at %ld.%09lu\n", ts.tv_sec, ts.tv_nsec);
+ + 	schedule_delayed_work(&cpts->overflow_work, CPTS_OVERFLOW_PERIOD);
+ + }
+ + 
+ + #define CPTS_REF_CLOCK_NAME "cpsw_cpts_rft_clk"
+ + 
+ + static void cpts_clk_init(struct cpts *cpts)
+ + {
+ + 	cpts->refclk = clk_get(NULL, CPTS_REF_CLOCK_NAME);
+ + 	if (IS_ERR(cpts->refclk)) {
+ + 		pr_err("Failed to clk_get %s\n", CPTS_REF_CLOCK_NAME);
+ + 		cpts->refclk = NULL;
+ + 		return;
+ + 	}
+ + 	clk_enable(cpts->refclk);
+ + 	cpts->freq = cpts->refclk->recalc(cpts->refclk);
+ + }
+ + 
+ + static void cpts_clk_release(struct cpts *cpts)
+ + {
+ + 	clk_disable(cpts->refclk);
+ + 	clk_put(cpts->refclk);
+ + }
+ + 
+ + static int cpts_match(struct sk_buff *skb, unsigned int ptp_class,
+ + 		      u16 ts_seqid, u8 ts_msgtype)
+ + {
+ + 	u16 *seqid;
+ + 	unsigned int offset;
+ + 	u8 *msgtype, *data = skb->data;
+ + 
+ + 	switch (ptp_class) {
+ + 	case PTP_CLASS_V1_IPV4:
+ + 	case PTP_CLASS_V2_IPV4:
+ + 		offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
+ + 		break;
+ + 	case PTP_CLASS_V1_IPV6:
+ + 	case PTP_CLASS_V2_IPV6:
+ + 		offset = OFF_PTP6;
+ + 		break;
+ + 	case PTP_CLASS_V2_L2:
+ + 		offset = ETH_HLEN;
+ + 		break;
+ + 	case PTP_CLASS_V2_VLAN:
+ + 		offset = ETH_HLEN + VLAN_HLEN;
+ + 		break;
+ + 	default:
+ + 		return 0;
+ + 	}
+ + 
+ + 	if (skb->len + ETH_HLEN < offset + OFF_PTP_SEQUENCE_ID + sizeof(*seqid))
+ + 		return 0;
+ + 
+ + 	if (unlikely(ptp_class & PTP_CLASS_V1))
+ + 		msgtype = data + offset + OFF_PTP_CONTROL;
+ + 	else
+ + 		msgtype = data + offset;
+ + 
+ + 	seqid = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
+ + 
+ + 	return (ts_msgtype == (*msgtype & 0xf) && ts_seqid == ntohs(*seqid));
+ + }
+ + 
+ + static u64 cpts_find_ts(struct cpts *cpts, struct sk_buff *skb, int ev_type)
+ + {
+ + 	u64 ns = 0;
+ + 	struct cpts_event *event;
+ + 	struct list_head *this, *next;
+ + 	unsigned int class = sk_run_filter(skb, ptp_filter);
+ + 	unsigned long flags;
+ + 	u16 seqid;
+ + 	u8 mtype;
+ + 
+ + 	if (class == PTP_CLASS_NONE)
+ + 		return 0;
+ + 
+ + 	spin_lock_irqsave(&cpts->lock, flags);
+ + 	cpts_fifo_read(cpts, CPTS_EV_PUSH);
+ + 	list_for_each_safe(this, next, &cpts->events) {
+ + 		event = list_entry(this, struct cpts_event, list);
+ + 		if (event_expired(event)) {
+ + 			list_del_init(&event->list);
+ + 			list_add(&event->list, &cpts->pool);
+ + 			continue;
+ + 		}
+ + 		mtype = (event->high >> MESSAGE_TYPE_SHIFT) & MESSAGE_TYPE_MASK;
+ + 		seqid = (event->high >> SEQUENCE_ID_SHIFT) & SEQUENCE_ID_MASK;
+ + 		if (ev_type == event_type(event) &&
+ + 		    cpts_match(skb, class, seqid, mtype)) {
+ + 			ns = timecounter_cyc2time(&cpts->tc, event->low);
+ + 			list_del_init(&event->list);
+ + 			list_add(&event->list, &cpts->pool);
+ + 			break;
+ + 		}
+ + 	}
+ + 	spin_unlock_irqrestore(&cpts->lock, flags);
+ + 
+ + 	return ns;
+ + }
+ + 
+ + void cpts_rx_timestamp(struct cpts *cpts, struct sk_buff *skb)
+ + {
+ + 	u64 ns;
+ + 	struct skb_shared_hwtstamps *ssh;
+ + 
+ + 	if (!cpts->rx_enable)
+ + 		return;
+ + 	ns = cpts_find_ts(cpts, skb, CPTS_EV_RX);
+ + 	if (!ns)
+ + 		return;
+ + 	ssh = skb_hwtstamps(skb);
+ + 	memset(ssh, 0, sizeof(*ssh));
+ + 	ssh->hwtstamp = ns_to_ktime(ns);
+ + }
+ + 
+ + void cpts_tx_timestamp(struct cpts *cpts, struct sk_buff *skb)
+ + {
+ + 	u64 ns;
+ + 	struct skb_shared_hwtstamps ssh;
+ + 
+ + 	if (!(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
+ + 		return;
+ + 	ns = cpts_find_ts(cpts, skb, CPTS_EV_TX);
+ + 	if (!ns)
+ + 		return;
+ + 	memset(&ssh, 0, sizeof(ssh));
+ + 	ssh.hwtstamp = ns_to_ktime(ns);
+ + 	skb_tstamp_tx(skb, &ssh);
+ + }
+ + 
+ + #endif /*CONFIG_TI_CPTS*/
+ + 
+ + int cpts_register(struct device *dev, struct cpts *cpts,
+ + 		  u32 mult, u32 shift)
+ + {
+ + #ifdef CONFIG_TI_CPTS
+ + 	int err, i;
+ + 	unsigned long flags;
+ + 
+ + 	if (ptp_filter_init(ptp_filter, ARRAY_SIZE(ptp_filter))) {
+ + 		pr_err("cpts: bad ptp filter\n");
+ + 		return -EINVAL;
+ + 	}
+ + 	cpts->info = cpts_info;
+ + 	cpts->clock = ptp_clock_register(&cpts->info);
+ + 	if (IS_ERR(cpts->clock)) {
+ + 		err = PTR_ERR(cpts->clock);
+ + 		cpts->clock = NULL;
+ + 		return err;
+ + 	}
+ + 	spin_lock_init(&cpts->lock);
+ + 
+ + 	cpts->cc.read = cpts_systim_read;
+ + 	cpts->cc.mask = CLOCKSOURCE_MASK(32);
+ + 	cpts->cc_mult = mult;
+ + 	cpts->cc.mult = mult;
+ + 	cpts->cc.shift = shift;
+ + 
+ + 	INIT_LIST_HEAD(&cpts->events);
+ + 	INIT_LIST_HEAD(&cpts->pool);
+ + 	for (i = 0; i < CPTS_MAX_EVENTS; i++)
+ + 		list_add(&cpts->pool_data[i].list, &cpts->pool);
+ + 
+ + 	cpts_clk_init(cpts);
+ + 	cpts_write32(cpts, CPTS_EN, control);
+ + 	cpts_write32(cpts, TS_PEND_EN, int_enable);
+ + 
+ + 	spin_lock_irqsave(&cpts->lock, flags);
+ + 	timecounter_init(&cpts->tc, &cpts->cc, ktime_to_ns(ktime_get_real()));
+ + 	spin_unlock_irqrestore(&cpts->lock, flags);
+ + 
+ + 	INIT_DELAYED_WORK(&cpts->overflow_work, cpts_overflow_check);
+ + 	schedule_delayed_work(&cpts->overflow_work, CPTS_OVERFLOW_PERIOD);
+ + #endif
+ + 	return 0;
+ + }
+ + 
+ + void cpts_unregister(struct cpts *cpts)
+ + {
+ + #ifdef CONFIG_TI_CPTS
+ + 	if (cpts->clock) {
+ + 		ptp_clock_unregister(cpts->clock);
+ + 		cancel_delayed_work_sync(&cpts->overflow_work);
+ + 	}
+ + 	if (cpts->refclk)
+ + 		cpts_clk_release(cpts);
+ + #endif
+ + }
+ diff -crN linux-3.2.1_o/drivers/net/ethernet/ti/cpts.h linux-3.2.1/drivers/net/ethernet/ti/cpts.h
+ *** linux-3.2.1_o/drivers/net/ethernet/ti/cpts.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/drivers/net/ethernet/ti/cpts.h	2014-11-25 13:19:15.774992296 +0900
+ ***************
+ *** 0 ****
+ --- 1,146 ----
+ + /*
+ +  * TI Common Platform Time Sync
+ +  *
+ +  * Copyright (C) 2012 Richard Cochran <richardcochran@gmail.com>
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; either version 2 of the License, or
+ +  * (at your option) any later version.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ +  */
+ + #ifndef _TI_CPTS_H_
+ + #define _TI_CPTS_H_
+ + 
+ + #include <linux/clk.h>
+ + #include <linux/clkdev.h>
+ + #include <linux/clocksource.h>
+ + #include <linux/device.h>
+ + #include <linux/list.h>
+ + #include <linux/ptp_clock_kernel.h>
+ + #include <linux/skbuff.h>
+ + 
+ + struct cpsw_cpts {
+ + 	u32 idver;                /* Identification and version */
+ + 	u32 control;              /* Time sync control */
+ + 	u32 res1;
+ + 	u32 ts_push;              /* Time stamp event push */
+ + 	u32 ts_load_val;          /* Time stamp load value */
+ + 	u32 ts_load_en;           /* Time stamp load enable */
+ + 	u32 res2[2];
+ + 	u32 intstat_raw;          /* Time sync interrupt status raw */
+ + 	u32 intstat_masked;       /* Time sync interrupt status masked */
+ + 	u32 int_enable;           /* Time sync interrupt enable */
+ + 	u32 res3;
+ + 	u32 event_pop;            /* Event interrupt pop */
+ + 	u32 event_low;            /* 32 Bit Event Time Stamp */
+ + 	u32 event_high;           /* Event Type Fields */
+ + };
+ + 
+ + /* Bit definitions for the IDVER register */
+ + #define TX_IDENT_SHIFT       (16)    /* TX Identification Value */
+ + #define TX_IDENT_MASK        (0xffff)
+ + #define RTL_VER_SHIFT        (11)    /* RTL Version Value */
+ + #define RTL_VER_MASK         (0x1f)
+ + #define MAJOR_VER_SHIFT      (8)     /* Major Version Value */
+ + #define MAJOR_VER_MASK       (0x7)
+ + #define MINOR_VER_SHIFT      (0)     /* Minor Version Value */
+ + #define MINOR_VER_MASK       (0xff)
+ + 
+ + /* Bit definitions for the CONTROL register */
+ + #define HW4_TS_PUSH_EN       (1<<11) /* Hardware push 4 enable */
+ + #define HW3_TS_PUSH_EN       (1<<10) /* Hardware push 3 enable */
+ + #define HW2_TS_PUSH_EN       (1<<9)  /* Hardware push 2 enable */
+ + #define HW1_TS_PUSH_EN       (1<<8)  /* Hardware push 1 enable */
+ + #define INT_TEST             (1<<1)  /* Interrupt Test */
+ + #define CPTS_EN              (1<<0)  /* Time Sync Enable */
+ + 
+ + /*
+ +  * Definitions for the single bit resisters:
+ +  * TS_PUSH TS_LOAD_EN  INTSTAT_RAW INTSTAT_MASKED INT_ENABLE EVENT_POP
+ +  */
+ + #define TS_PUSH             (1<<0)  /* Time stamp event push */
+ + #define TS_LOAD_EN          (1<<0)  /* Time Stamp Load */
+ + #define TS_PEND_RAW         (1<<0)  /* int read (before enable) */
+ + #define TS_PEND             (1<<0)  /* masked interrupt read (after enable) */
+ + #define TS_PEND_EN          (1<<0)  /* masked interrupt enable */
+ + #define EVENT_POP           (1<<0)  /* writing discards one event */
+ + 
+ + /* Bit definitions for the EVENT_HIGH register */
+ + #define PORT_NUMBER_SHIFT    (24)    /* Indicates Ethernet port or HW pin */
+ + #define PORT_NUMBER_MASK     (0x1f)
+ + #define EVENT_TYPE_SHIFT     (20)    /* Time sync event type */
+ + #define EVENT_TYPE_MASK      (0xf)
+ + #define MESSAGE_TYPE_SHIFT   (16)    /* PTP message type */
+ + #define MESSAGE_TYPE_MASK    (0xf)
+ + #define SEQUENCE_ID_SHIFT    (0)     /* PTP message sequence ID */
+ + #define SEQUENCE_ID_MASK     (0xffff)
+ + 
+ + enum {
+ + 	CPTS_EV_PUSH, /* Time Stamp Push Event */
+ + 	CPTS_EV_ROLL, /* Time Stamp Rollover Event */
+ + 	CPTS_EV_HALF, /* Time Stamp Half Rollover Event */
+ + 	CPTS_EV_HW,   /* Hardware Time Stamp Push Event */
+ + 	CPTS_EV_RX,   /* Ethernet Receive Event */
+ + 	CPTS_EV_TX,   /* Ethernet Transmit Event */
+ + };
+ + 
+ + /* This covers any input clock up to about 500 MHz. */
+ + #define CPTS_OVERFLOW_PERIOD (HZ * 8)
+ + 
+ + #define CPTS_FIFO_DEPTH 16
+ + #define CPTS_MAX_EVENTS 32
+ + 
+ + struct cpts_event {
+ + 	struct list_head list;
+ + 	unsigned long tmo;
+ + 	u32 high;
+ + 	u32 low;
+ + };
+ + 
+ + struct cpts {
+ + 	struct cpsw_cpts __iomem *reg;
+ + 	int tx_enable;
+ + 	int rx_enable;
+ + #ifdef CONFIG_TI_CPTS
+ + 	struct ptp_clock_info info;
+ + 	struct ptp_clock *clock;
+ + 	spinlock_t lock; /* protects time registers */
+ + 	u32 cc_mult; /* for the nominal frequency */
+ + 	struct cyclecounter cc;
+ + 	struct timecounter tc;
+ + 	struct delayed_work overflow_work;
+ + 	int phc_index;
+ + 	struct clk *refclk;
+ + 	unsigned long freq;
+ + 	struct list_head events;
+ + 	struct list_head pool;
+ + 	struct cpts_event pool_data[CPTS_MAX_EVENTS];
+ + #endif
+ + };
+ + 
+ + #ifdef CONFIG_TI_CPTS
+ + extern void cpts_rx_timestamp(struct cpts *cpts, struct sk_buff *skb);
+ + extern void cpts_tx_timestamp(struct cpts *cpts, struct sk_buff *skb);
+ + #else
+ + static inline void cpts_rx_timestamp(struct cpts *cpts, struct sk_buff *skb)
+ + {
+ + }
+ + static inline void cpts_tx_timestamp(struct cpts *cpts, struct sk_buff *skb)
+ + {
+ + }
+ + #endif
+ + 
+ + extern int cpts_register(struct device *dev, struct cpts *cpts,
+ + 			 u32 mult, u32 shift);
+ + extern void cpts_unregister(struct cpts *cpts);
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/drivers/net/ethernet/ti/davinci_cpdma.c linux-3.2.1/drivers/net/ethernet/ti/davinci_cpdma.c
+ *** linux-3.2.1_o/drivers/net/ethernet/ti/davinci_cpdma.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/net/ethernet/ti/davinci_cpdma.c	2014-11-25 13:19:15.774992296 +0900
+ ***************
+ *** 19,24 ****
+ --- 19,25 ----
+   #include <linux/err.h>
+   #include <linux/dma-mapping.h>
+   #include <linux/io.h>
+ + #include <linux/export.h>
+   
+   #include "davinci_cpdma.h"
+   
+ ***************
+ *** 59,64 ****
+ --- 60,67 ----
+   #define CPDMA_DESC_EOQ		BIT(28)
+   #define CPDMA_DESC_TD_COMPLETE	BIT(27)
+   #define CPDMA_DESC_PASS_CRC	BIT(26)
+ + #define CPDMA_DESC_TO_PORT_EN	BIT(20)
+ + #define CPDMA_DESC_PORT_MASK	(BIT(18) | BIT(17) | BIT(16))
+   
+   #define CPDMA_TEARDOWN_VALUE	0xfffffffc
+   
+ ***************
+ *** 104,116 ****
+   };
+   
+   struct cpdma_chan {
+   	enum cpdma_state		state;
+   	struct cpdma_ctlr		*ctlr;
+   	int				chan_num;
+   	spinlock_t			lock;
+ - 	struct cpdma_desc __iomem	*head, *tail;
+   	int				count;
+ - 	void __iomem			*hdp, *cp, *rxfree;
+   	u32				mask;
+   	cpdma_handler_fn		handler;
+   	enum dma_data_direction		dir;
+ --- 107,119 ----
+   };
+   
+   struct cpdma_chan {
+ + 	struct cpdma_desc __iomem	*head, *tail;
+ + 	void __iomem			*hdp, *cp, *rxfree;
+   	enum cpdma_state		state;
+   	struct cpdma_ctlr		*ctlr;
+   	int				chan_num;
+   	spinlock_t			lock;
+   	int				count;
+   	u32				mask;
+   	cpdma_handler_fn		handler;
+   	enum dma_data_direction		dir;
+ ***************
+ *** 216,222 ****
+   }
+   
+   static struct cpdma_desc __iomem *
+ ! cpdma_desc_alloc(struct cpdma_desc_pool *pool, int num_desc)
+   {
+   	unsigned long flags;
+   	int index;
+ --- 219,225 ----
+   }
+   
+   static struct cpdma_desc __iomem *
+ ! cpdma_desc_alloc(struct cpdma_desc_pool *pool, int num_desc, bool is_rx)
+   {
+   	unsigned long flags;
+   	int index;
+ ***************
+ *** 224,231 ****
+   
+   	spin_lock_irqsave(&pool->lock, flags);
+   
+ ! 	index = bitmap_find_next_zero_area(pool->bitmap, pool->num_desc, 0,
+ ! 					   num_desc, 0);
+   	if (index < pool->num_desc) {
+   		bitmap_set(pool->bitmap, index, num_desc);
+   		desc = pool->iomap + pool->desc_size * index;
+ --- 227,240 ----
+   
+   	spin_lock_irqsave(&pool->lock, flags);
+   
+ ! 	if (is_rx) {
+ ! 		index = bitmap_find_next_zero_area(pool->bitmap,
+ ! 				pool->num_desc/2, 0, num_desc, 0);
+ ! 	 } else {
+ ! 		index = bitmap_find_next_zero_area(pool->bitmap,
+ ! 				pool->num_desc, pool->num_desc/2, num_desc, 0);
+ ! 	}
+ ! 
+   	if (index < pool->num_desc) {
+   		bitmap_set(pool->bitmap, index, num_desc);
+   		desc = pool->iomap + pool->desc_size * index;
+ ***************
+ *** 276,281 ****
+ --- 285,291 ----
+   		ctlr->num_chan = CPDMA_MAX_CHANNELS;
+   	return ctlr;
+   }
+ + EXPORT_SYMBOL_GPL(cpdma_ctlr_create);
+   
+   int cpdma_ctlr_start(struct cpdma_ctlr *ctlr)
+   {
+ ***************
+ *** 321,326 ****
+ --- 331,337 ----
+   	spin_unlock_irqrestore(&ctlr->lock, flags);
+   	return 0;
+   }
+ + EXPORT_SYMBOL_GPL(cpdma_ctlr_start);
+   
+   int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr)
+   {
+ ***************
+ *** 351,356 ****
+ --- 362,368 ----
+   	spin_unlock_irqrestore(&ctlr->lock, flags);
+   	return 0;
+   }
+ + EXPORT_SYMBOL_GPL(cpdma_ctlr_stop);
+   
+   int cpdma_ctlr_dump(struct cpdma_ctlr *ctlr)
+   {
+ ***************
+ *** 444,449 ****
+ --- 456,462 ----
+   	kfree(ctlr);
+   	return ret;
+   }
+ + EXPORT_SYMBOL_GPL(cpdma_ctlr_destroy);
+   
+   int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable)
+   {
+ ***************
+ *** 467,477 ****
+ --- 480,494 ----
+   	spin_unlock_irqrestore(&ctlr->lock, flags);
+   	return 0;
+   }
+ + EXPORT_SYMBOL_GPL(cpdma_ctlr_int_ctrl);
+   
+   void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr)
+   {
+   	dma_reg_write(ctlr, CPDMA_MACEOIVECTOR, 0);
+ + 	dma_reg_write(ctlr, CPDMA_MACEOIVECTOR, 1);
+ + 	dma_reg_write(ctlr, CPDMA_MACEOIVECTOR, 2);
+   }
+ + EXPORT_SYMBOL_GPL(cpdma_ctlr_eoi);
+   
+   struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num,
+   				     cpdma_handler_fn handler)
+ ***************
+ *** 528,533 ****
+ --- 545,551 ----
+   err_chan_alloc:
+   	return ERR_PTR(ret);
+   }
+ + EXPORT_SYMBOL_GPL(cpdma_chan_create);
+   
+   int cpdma_chan_destroy(struct cpdma_chan *chan)
+   {
+ ***************
+ *** 545,550 ****
+ --- 563,569 ----
+   	kfree(chan);
+   	return 0;
+   }
+ + EXPORT_SYMBOL_GPL(cpdma_chan_destroy);
+   
+   int cpdma_chan_get_stats(struct cpdma_chan *chan,
+   			 struct cpdma_chan_stats *stats)
+ ***************
+ *** 557,562 ****
+ --- 576,582 ----
+   	spin_unlock_irqrestore(&chan->lock, flags);
+   	return 0;
+   }
+ + EXPORT_SYMBOL_GPL(cpdma_chan_get_stats);
+   
+   int cpdma_chan_dump(struct cpdma_chan *chan)
+   {
+ ***************
+ *** 643,649 ****
+   }
+   
+   int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data,
+ ! 		      int len, gfp_t gfp_mask)
+   {
+   	struct cpdma_ctlr		*ctlr = chan->ctlr;
+   	struct cpdma_desc __iomem	*desc;
+ --- 663,669 ----
+   }
+   
+   int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data,
+ ! 		      int len, int directed, gfp_t gfp_mask)
+   {
+   	struct cpdma_ctlr		*ctlr = chan->ctlr;
+   	struct cpdma_desc __iomem	*desc;
+ ***************
+ *** 651,656 ****
+ --- 671,677 ----
+   	unsigned long			flags;
+   	u32				mode;
+   	int				ret = 0;
+ + 	bool                            is_rx;
+   
+   	spin_lock_irqsave(&chan->lock, flags);
+   
+ ***************
+ *** 659,665 ****
+   		goto unlock_ret;
+   	}
+   
+ ! 	desc = cpdma_desc_alloc(ctlr->pool, 1);
+   	if (!desc) {
+   		chan->stats.desc_alloc_fail++;
+   		ret = -ENOMEM;
+ --- 680,687 ----
+   		goto unlock_ret;
+   	}
+   
+ ! 	is_rx = (chan->rxfree != 0);
+ ! 	desc = cpdma_desc_alloc(ctlr->pool, 1, is_rx);
+   	if (!desc) {
+   		chan->stats.desc_alloc_fail++;
+   		ret = -ENOMEM;
+ ***************
+ *** 673,678 ****
+ --- 695,702 ----
+   
+   	buffer = dma_map_single(ctlr->dev, data, len, chan->dir);
+   	mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP;
+ + 	if ((!is_rx) && ((directed == 1) || (directed == 2)))
+ + 		mode |= (CPDMA_DESC_TO_PORT_EN | (directed << 16));
+   
+   	desc_write(desc, hw_next,   0);
+   	desc_write(desc, hw_buffer, buffer);
+ ***************
+ *** 693,698 ****
+ --- 717,723 ----
+   	spin_unlock_irqrestore(&chan->lock, flags);
+   	return ret;
+   }
+ + EXPORT_SYMBOL_GPL(cpdma_chan_submit);
+   
+   static void __cpdma_chan_free(struct cpdma_chan *chan,
+   			      struct cpdma_desc __iomem *desc,
+ ***************
+ *** 720,728 ****
+   	int				status, outlen;
+   	struct cpdma_desc_pool		*pool = ctlr->pool;
+   	dma_addr_t			desc_dma;
+ - 	unsigned long			flags;
+ - 
+ - 	spin_lock_irqsave(&chan->lock, flags);
+   
+   	desc = chan->head;
+   	if (!desc) {
+ --- 745,750 ----
+ ***************
+ *** 739,763 ****
+   		status = -EBUSY;
+   		goto unlock_ret;
+   	}
+ ! 	status	= status & (CPDMA_DESC_EOQ | CPDMA_DESC_TD_COMPLETE);
+   
+   	chan->head = desc_from_phys(pool, desc_read(desc, hw_next));
+   	chan_write(chan, cp, desc_dma);
+   	chan->count--;
+   	chan->stats.good_dequeue++;
+   
+ ! 	if (status & CPDMA_DESC_EOQ) {
+   		chan->stats.requeue++;
+   		chan_write(chan, hdp, desc_phys(pool, chan->head));
+   	}
+   
+ - 	spin_unlock_irqrestore(&chan->lock, flags);
+ - 
+   	__cpdma_chan_free(chan, desc, outlen, status);
+   	return status;
+   
+   unlock_ret:
+ - 	spin_unlock_irqrestore(&chan->lock, flags);
+   	return status;
+   }
+   
+ --- 761,784 ----
+   		status = -EBUSY;
+   		goto unlock_ret;
+   	}
+ ! 	status	= status & (CPDMA_DESC_EOQ | CPDMA_DESC_TD_COMPLETE |
+ ! 			    CPDMA_DESC_PORT_MASK);
+   
+   	chan->head = desc_from_phys(pool, desc_read(desc, hw_next));
+   	chan_write(chan, cp, desc_dma);
+   	chan->count--;
+   	chan->stats.good_dequeue++;
+   
+ ! 	if ((status & CPDMA_DESC_EOQ) && (chan->head) &&
+ ! 			(!(status & CPDMA_DESC_TD_COMPLETE))) {
+   		chan->stats.requeue++;
+   		chan_write(chan, hdp, desc_phys(pool, chan->head));
+   	}
+   
+   	__cpdma_chan_free(chan, desc, outlen, status);
+   	return status;
+   
+   unlock_ret:
+   	return status;
+   }
+   
+ ***************
+ *** 776,781 ****
+ --- 797,803 ----
+   	}
+   	return used;
+   }
+ + EXPORT_SYMBOL_GPL(cpdma_chan_process);
+   
+   int cpdma_chan_start(struct cpdma_chan *chan)
+   {
+ ***************
+ *** 803,808 ****
+ --- 825,831 ----
+   	spin_unlock_irqrestore(&chan->lock, flags);
+   	return 0;
+   }
+ + EXPORT_SYMBOL_GPL(cpdma_chan_start);
+   
+   int cpdma_chan_stop(struct cpdma_chan *chan)
+   {
+ ***************
+ *** 863,868 ****
+ --- 886,892 ----
+   	spin_unlock_irqrestore(&chan->lock, flags);
+   	return 0;
+   }
+ + EXPORT_SYMBOL_GPL(cpdma_chan_stop);
+   
+   int cpdma_chan_int_ctrl(struct cpdma_chan *chan, bool enable)
+   {
+ ***************
+ *** 934,939 ****
+ --- 958,964 ----
+   	spin_unlock_irqrestore(&ctlr->lock, flags);
+   	return ret;
+   }
+ + EXPORT_SYMBOL_GPL(cpdma_control_get);
+   
+   int cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value)
+   {
+ ***************
+ *** 970,972 ****
+ --- 995,998 ----
+   	spin_unlock_irqrestore(&ctlr->lock, flags);
+   	return ret;
+   }
+ + EXPORT_SYMBOL_GPL(cpdma_control_set);
+ diff -crN linux-3.2.1_o/drivers/net/ethernet/ti/davinci_cpdma.h linux-3.2.1/drivers/net/ethernet/ti/davinci_cpdma.h
+ *** linux-3.2.1_o/drivers/net/ethernet/ti/davinci_cpdma.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/net/ethernet/ti/davinci_cpdma.h	2014-11-25 13:19:15.774992296 +0900
+ ***************
+ *** 24,29 ****
+ --- 24,31 ----
+   #define __chan_linear(chan_num)	((chan_num) & (CPDMA_MAX_CHANNELS - 1))
+   #define chan_linear(chan)	__chan_linear((chan)->chan_num)
+   
+ + #define CPDMA_RX_SOURCE_PORT(__status__)	((__status__ >> 16) & 0x7)
+ + 
+   struct cpdma_params {
+   	struct device		*dev;
+   	void __iomem		*dmaregs;
+ ***************
+ *** 82,88 ****
+   int cpdma_chan_get_stats(struct cpdma_chan *chan,
+   			 struct cpdma_chan_stats *stats);
+   int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data,
+ ! 		      int len, gfp_t gfp_mask);
+   int cpdma_chan_process(struct cpdma_chan *chan, int quota);
+   
+   int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable);
+ --- 84,90 ----
+   int cpdma_chan_get_stats(struct cpdma_chan *chan,
+   			 struct cpdma_chan_stats *stats);
+   int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data,
+ ! 		      int len, int directed, gfp_t gfp_mask);
+   int cpdma_chan_process(struct cpdma_chan *chan, int quota);
+   
+   int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable);
+ diff -crN linux-3.2.1_o/drivers/net/ethernet/ti/davinci_emac.c linux-3.2.1/drivers/net/ethernet/ti/davinci_emac.c
+ *** linux-3.2.1_o/drivers/net/ethernet/ti/davinci_emac.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/net/ethernet/ti/davinci_emac.c	2014-11-25 13:19:15.779627926 +0900
+ ***************
+ *** 1035,1041 ****
+   
+   recycle:
+   	ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
+ ! 			skb_tailroom(skb), GFP_KERNEL);
+   	if (WARN_ON(ret < 0))
+   		dev_kfree_skb_any(skb);
+   }
+ --- 1035,1041 ----
+   
+   recycle:
+   	ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
+ ! 			skb_tailroom(skb), 0, GFP_KERNEL);
+   	if (WARN_ON(ret < 0))
+   		dev_kfree_skb_any(skb);
+   }
+ ***************
+ *** 1085,1091 ****
+   	skb_tx_timestamp(skb);
+   
+   	ret_code = cpdma_chan_submit(priv->txchan, skb, skb->data, skb->len,
+ ! 				     GFP_KERNEL);
+   	if (unlikely(ret_code != 0)) {
+   		if (netif_msg_tx_err(priv) && net_ratelimit())
+   			dev_err(emac_dev, "DaVinci EMAC: desc submit failed");
+ --- 1085,1091 ----
+   	skb_tx_timestamp(skb);
+   
+   	ret_code = cpdma_chan_submit(priv->txchan, skb, skb->data, skb->len,
+ ! 				     0, GFP_KERNEL);
+   	if (unlikely(ret_code != 0)) {
+   		if (netif_msg_tx_err(priv) && net_ratelimit())
+   			dev_err(emac_dev, "DaVinci EMAC: desc submit failed");
+ ***************
+ *** 1544,1550 ****
+   			break;
+   
+   		ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
+ ! 					skb_tailroom(skb), GFP_KERNEL);
+   		if (WARN_ON(ret < 0))
+   			break;
+   	}
+ --- 1544,1550 ----
+   			break;
+   
+   		ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
+ ! 					skb_tailroom(skb), 0, GFP_KERNEL);
+   		if (WARN_ON(ret < 0))
+   			break;
+   	}
+ diff -crN linux-3.2.1_o/drivers/net/ethernet/ti/davinci_mdio.c linux-3.2.1/drivers/net/ethernet/ti/davinci_mdio.c
+ *** linux-3.2.1_o/drivers/net/ethernet/ti/davinci_mdio.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/net/ethernet/ti/davinci_mdio.c	2014-11-25 13:19:15.779627926 +0900
+ ***************
+ *** 34,39 ****
+ --- 34,40 ----
+   #include <linux/clk.h>
+   #include <linux/err.h>
+   #include <linux/io.h>
+ + #include <linux/pm_runtime.h>
+   #include <linux/davinci_emac.h>
+   
+   /*
+ ***************
+ *** 48,53 ****
+ --- 49,58 ----
+   
+   #define DEF_OUT_FREQ		2200000		/* 2.2 MHz */
+   
+ + #define CPGMAC_CLK_CTRL_REG	0x44E00014
+ + #define CPGMAC_CLK_SYSC         0x4A101208
+ + #define CPSW_NO_IDLE_NO_STDBY   0xA
+ + 
+   struct davinci_mdio_regs {
+   	u32	version;
+   	u32	control;
+ ***************
+ *** 181,186 ****
+ --- 186,196 ----
+   		__davinci_mdio_reset(data);
+   		return -EAGAIN;
+   	}
+ + 
+ + 	reg = __raw_readl(&regs->user[0].access);
+ + 	if ((reg & USERACCESS_GO) == 0)
+ + 		return 0;
+ + 
+   	dev_err(data->dev, "timed out waiting for user access\n");
+   	return -ETIMEDOUT;
+   }
+ ***************
+ *** 315,321 ****
+   	data->bus->priv		= data;
+   	snprintf(data->bus->id, MII_BUS_ID_SIZE, "%x", pdev->id);
+   
+ ! 	data->clk = clk_get(dev, NULL);
+   	if (IS_ERR(data->clk)) {
+   		data->clk = NULL;
+   		dev_err(dev, "failed to get device clock\n");
+ --- 325,333 ----
+   	data->bus->priv		= data;
+   	snprintf(data->bus->id, MII_BUS_ID_SIZE, "%x", pdev->id);
+   
+ ! 	pm_runtime_enable(&pdev->dev);
+ ! 	pm_runtime_get_sync(&pdev->dev);
+ ! 	data->clk = clk_get(&pdev->dev, "fck");
+   	if (IS_ERR(data->clk)) {
+   		data->clk = NULL;
+   		dev_err(dev, "failed to get device clock\n");
+ ***************
+ *** 323,330 ****
+   		goto bail_out;
+   	}
+   
+ - 	clk_enable(data->clk);
+ - 
+   	dev_set_drvdata(dev, data);
+   	data->dev = dev;
+   	spin_lock_init(&data->lock);
+ --- 335,340 ----
+ ***************
+ *** 371,381 ****
+   bail_out:
+   	if (data->bus)
+   		mdiobus_free(data->bus);
+ ! 
+ ! 	if (data->clk) {
+ ! 		clk_disable(data->clk);
+   		clk_put(data->clk);
+ ! 	}
+   
+   	kfree(data);
+   
+ --- 381,390 ----
+   bail_out:
+   	if (data->bus)
+   		mdiobus_free(data->bus);
+ ! 	if (data->clk)
+   		clk_put(data->clk);
+ ! 	pm_runtime_put_sync(&pdev->dev);
+ ! 	pm_runtime_disable(&pdev->dev);
+   
+   	kfree(data);
+   
+ ***************
+ *** 387,399 ****
+   	struct device *dev = &pdev->dev;
+   	struct davinci_mdio_data *data = dev_get_drvdata(dev);
+   
+ ! 	if (data->bus)
+   		mdiobus_free(data->bus);
+   
+ ! 	if (data->clk) {
+ ! 		clk_disable(data->clk);
+   		clk_put(data->clk);
+ ! 	}
+   
+   	dev_set_drvdata(dev, NULL);
+   
+ --- 396,410 ----
+   	struct device *dev = &pdev->dev;
+   	struct davinci_mdio_data *data = dev_get_drvdata(dev);
+   
+ ! 	if (data->bus) {
+ ! 		mdiobus_unregister(data->bus);
+   		mdiobus_free(data->bus);
+ + 	}
+   
+ ! 	if (data->clk)
+   		clk_put(data->clk);
+ ! 	pm_runtime_put_sync(&pdev->dev);
+ ! 	pm_runtime_disable(&pdev->dev);
+   
+   	dev_set_drvdata(dev, NULL);
+   
+ ***************
+ *** 402,407 ****
+ --- 413,445 ----
+   	return 0;
+   }
+   
+ + static inline int wait_for_clock_enable(struct davinci_mdio_data *data)
+ + {
+ + 	unsigned long timeout = jiffies + msecs_to_jiffies(MDIO_TIMEOUT);
+ + 	u32 __iomem *cpgmac_clk = ioremap(CPGMAC_CLK_CTRL_REG, 4);
+ + 	u32 __iomem *cpgmac_sysc = ioremap(CPGMAC_CLK_SYSC, 4);
+ + 	u32 reg = 0;
+ + 
+ + 	while (time_after(timeout, jiffies)) {
+ + 		reg = readl(cpgmac_clk);
+ + 		if ((reg & 0x30000) == 0) {
+ + 			writel(CPSW_NO_IDLE_NO_STDBY, cpgmac_sysc);
+ + 			goto iounmap_ret;
+ +                 }
+ + 	}
+ + 	dev_err(data->dev,
+ + 		"timed out waiting for CPGMAC clock enable, value = 0x%x\n",
+ + 		reg);
+ + 	iounmap(cpgmac_sysc);
+ + 	iounmap(cpgmac_clk);
+ + 	return -ETIMEDOUT;
+ + 
+ + iounmap_ret:
+ + 	iounmap(cpgmac_sysc);
+ + 	iounmap(cpgmac_clk);
+ + 	return 0;
+ + }
+ + 
+   static int davinci_mdio_suspend(struct device *dev)
+   {
+   	struct davinci_mdio_data *data = dev_get_drvdata(dev);
+ ***************
+ *** 415,422 ****
+   	__raw_writel(ctrl, &data->regs->control);
+   	wait_for_idle(data);
+   
+ ! 	if (data->clk)
+ ! 		clk_disable(data->clk);
+   
+   	data->suspended = true;
+   	spin_unlock(&data->lock);
+ --- 453,459 ----
+   	__raw_writel(ctrl, &data->regs->control);
+   	wait_for_idle(data);
+   
+ ! 	pm_runtime_put_sync(data->dev);
+   
+   	data->suspended = true;
+   	spin_unlock(&data->lock);
+ ***************
+ *** 430,444 ****
+   	u32 ctrl;
+   
+   	spin_lock(&data->lock);
+ ! 	if (data->clk)
+ ! 		clk_enable(data->clk);
+   
+   	/* restart the scan state machine */
+   	ctrl = __raw_readl(&data->regs->control);
+   	ctrl |= CONTROL_ENABLE;
+   	__raw_writel(ctrl, &data->regs->control);
+ - 
+   	data->suspended = false;
+   	spin_unlock(&data->lock);
+   
+   	return 0;
+ --- 467,483 ----
+   	u32 ctrl;
+   
+   	spin_lock(&data->lock);
+ ! 	pm_runtime_put_sync(data->dev);
+ ! 
+ ! 	/* Need to wait till Module is enabled */
+ ! 	wait_for_clock_enable(data);
+   
+   	/* restart the scan state machine */
+   	ctrl = __raw_readl(&data->regs->control);
+   	ctrl |= CONTROL_ENABLE;
+   	__raw_writel(ctrl, &data->regs->control);
+   	data->suspended = false;
+ + 
+   	spin_unlock(&data->lock);
+   
+   	return 0;
+ diff -crN linux-3.2.1_o/drivers/net/ethernet/ti/Kconfig linux-3.2.1/drivers/net/ethernet/ti/Kconfig
+ *** linux-3.2.1_o/drivers/net/ethernet/ti/Kconfig	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/net/ethernet/ti/Kconfig	2014-11-25 13:19:15.779627926 +0900
+ ***************
+ *** 5,11 ****
+   config NET_VENDOR_TI
+   	bool "Texas Instruments (TI) devices"
+   	default y
+ ! 	depends on PCI || EISA || AR7 || (ARM && (ARCH_DAVINCI || ARCH_OMAP3))
+   	---help---
+   	  If you have a network (Ethernet) card belonging to this class, say Y
+   	  and read the Ethernet-HOWTO, available from
+ --- 5,11 ----
+   config NET_VENDOR_TI
+   	bool "Texas Instruments (TI) devices"
+   	default y
+ ! 	depends on PCI || EISA || AR7 || (ARM && (ARCH_DAVINCI || ARCH_OMAP3 || ARCH_CKB))
+   	---help---
+   	  If you have a network (Ethernet) card belonging to this class, say Y
+   	  and read the Ethernet-HOWTO, available from
+ ***************
+ *** 20,26 ****
+   
+   config TI_DAVINCI_EMAC
+   	tristate "TI DaVinci EMAC Support"
+ ! 	depends on ARM && ( ARCH_DAVINCI || ARCH_OMAP3 )
+   	select TI_DAVINCI_MDIO
+   	select TI_DAVINCI_CPDMA
+   	select PHYLIB
+ --- 20,26 ----
+   
+   config TI_DAVINCI_EMAC
+   	tristate "TI DaVinci EMAC Support"
+ ! 	depends on ARM && ( ARCH_DAVINCI || ARCH_OMAP3 || ARCH_CKB )
+   	select TI_DAVINCI_MDIO
+   	select TI_DAVINCI_CPDMA
+   	select PHYLIB
+ ***************
+ *** 32,38 ****
+   
+   config TI_DAVINCI_MDIO
+   	tristate "TI DaVinci MDIO Support"
+ ! 	depends on ARM && ( ARCH_DAVINCI || ARCH_OMAP3 )
+   	select PHYLIB
+   	---help---
+   	  This driver supports TI's DaVinci MDIO module.
+ --- 32,38 ----
+   
+   config TI_DAVINCI_MDIO
+   	tristate "TI DaVinci MDIO Support"
+ ! 	depends on ARM && ( ARCH_DAVINCI || ARCH_OMAP3 || ARCH_CKB )
+   	select PHYLIB
+   	---help---
+   	  This driver supports TI's DaVinci MDIO module.
+ ***************
+ *** 42,54 ****
+   
+   config TI_DAVINCI_CPDMA
+   	tristate "TI DaVinci CPDMA Support"
+ ! 	depends on ARM && ( ARCH_DAVINCI || ARCH_OMAP3 )
+   	---help---
+   	  This driver supports TI's DaVinci CPDMA dma engine.
+   
+   	  To compile this driver as a module, choose M here: the module
+   	  will be called davinci_cpdma.  This is recommended.
+   
+   config TLAN
+   	tristate "TI ThunderLAN support"
+   	depends on (PCI || EISA)
+ --- 42,85 ----
+   
+   config TI_DAVINCI_CPDMA
+   	tristate "TI DaVinci CPDMA Support"
+ ! 	depends on ARM && ( ARCH_DAVINCI || ARCH_OMAP3 || ARCH_CKB )
+   	---help---
+   	  This driver supports TI's DaVinci CPDMA dma engine.
+   
+   	  To compile this driver as a module, choose M here: the module
+   	  will be called davinci_cpdma.  This is recommended.
+   
+ + config TI_CPSW
+ + 	tristate "TI CPSW Switch Support"
+ + 	depends on ARM && (ARCH_DAVINCI || SOC_OMAPAM33XX || ARCH_CKB )
+ + 	select TI_DAVINCI_CPDMA
+ + 	select TI_DAVINCI_MDIO
+ + 	---help---
+ + 	  This driver supports TI's CPSW Ethernet Switch.
+ + 
+ + 	  To compile this driver as a module, choose M here: the module
+ + 	  will be called cpsw.
+ + 
+ + config TI_CPTS
+ + 	boolean "TI Common Platform Time Sync (CPTS) Support"
+ + 	depends on TI_CPSW
+ + 	select PTP_1588_CLOCK
+ + 	select PPS
+ + 	---help---
+ + 	  This driver supports the Common Platform Time Sync unit of
+ + 	  the CPSW Ethernet Switch.
+ + 
+ + 	  The unit can time stamp PTP UDP/IPv4
+ + 	  and Layer 2 packets, and the driver offers a PTP Hardware Clock.
+ + 
+ + config TI_CPSW_DUAL_EMAC
+ + 	bool "TI CPSW Switch as Dual EMAC"
+ + 	depends on TI_CPSW
+ + 	help
+ + 	  This driver makes TI's CPSW Ethernet Switch as Dual EMAC. Switch
+ + 	  features will not be available in this mode, Dual Emac default
+ + 	  VLAN ids should not be used in VLAN configuration
+ + 
+   config TLAN
+   	tristate "TI ThunderLAN support"
+   	depends on (PCI || EISA)
+ diff -crN linux-3.2.1_o/drivers/net/ethernet/ti/Makefile linux-3.2.1/drivers/net/ethernet/ti/Makefile
+ *** linux-3.2.1_o/drivers/net/ethernet/ti/Makefile	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/net/ethernet/ti/Makefile	2014-11-25 13:19:15.783313495 +0900
+ ***************
+ *** 7,9 ****
+ --- 7,11 ----
+   obj-$(CONFIG_TI_DAVINCI_EMAC) += davinci_emac.o
+   obj-$(CONFIG_TI_DAVINCI_MDIO) += davinci_mdio.o
+   obj-$(CONFIG_TI_DAVINCI_CPDMA) += davinci_cpdma.o
+ + obj-$(CONFIG_TI_CPSW) += ti_cpsw.o
+ + ti_cpsw-y := cpsw_ale.o cpsw.o cpts.o
+ diff -crN linux-3.2.1_o/drivers/net/phy/micrel.c linux-3.2.1/drivers/net/phy/micrel.c
+ *** linux-3.2.1_o/drivers/net/phy/micrel.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/net/phy/micrel.c	2014-11-25 13:19:15.783313495 +0900
+ ***************
+ *** 179,185 ****
+   	.features	= (PHY_GBIT_FEATURES | SUPPORTED_Pause
+   				| SUPPORTED_Asym_Pause),
+   	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
+ ! 	.config_init	= kszphy_config_init,
+   	.config_aneg	= genphy_config_aneg,
+   	.read_status	= genphy_read_status,
+   	.ack_interrupt	= kszphy_ack_interrupt,
+ --- 179,186 ----
+   	.features	= (PHY_GBIT_FEATURES | SUPPORTED_Pause
+   				| SUPPORTED_Asym_Pause),
+   	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
+ ! 	//.config_init	= kszphy_config_init,
+ ! 	.config_init	= genphy_config_init,
+   	.config_aneg	= genphy_config_aneg,
+   	.read_status	= genphy_read_status,
+   	.ack_interrupt	= kszphy_ack_interrupt,
+ ***************
+ *** 191,204 ****
+   {
+   	int ret;
+   
+ ! 	ret = phy_driver_register(&ks8001_driver);
+   	if (ret)
+   		goto err1;
+   
+ ! 	ret = phy_driver_register(&ksz9021_driver);
+   	if (ret)
+   		goto err2;
+ ! 
+   	ret = phy_driver_register(&ks8737_driver);
+   	if (ret)
+   		goto err3;
+ --- 192,205 ----
+   {
+   	int ret;
+   
+ ! 	ret = phy_driver_register(&ksz9021_driver);
+   	if (ret)
+   		goto err1;
+   
+ ! 	ret = phy_driver_register(&ks8001_driver);
+   	if (ret)
+   		goto err2;
+ ! 		
+   	ret = phy_driver_register(&ks8737_driver);
+   	if (ret)
+   		goto err3;
+ ***************
+ *** 216,233 ****
+   err4:
+   	phy_driver_unregister(&ks8737_driver);
+   err3:
+ - 	phy_driver_unregister(&ksz9021_driver);
+ - err2:
+   	phy_driver_unregister(&ks8001_driver);
+   err1:
+   	return ret;
+   }
+   
+   static void __exit ksphy_exit(void)
+   {
+   	phy_driver_unregister(&ks8001_driver);
+   	phy_driver_unregister(&ks8737_driver);
+ - 	phy_driver_unregister(&ksz9021_driver);
+   	phy_driver_unregister(&ks8041_driver);
+   	phy_driver_unregister(&ks8051_driver);
+   }
+ --- 217,234 ----
+   err4:
+   	phy_driver_unregister(&ks8737_driver);
+   err3:
+   	phy_driver_unregister(&ks8001_driver);
+ + err2:
+ + 	phy_driver_unregister(&ksz9021_driver);
+   err1:
+   	return ret;
+   }
+   
+   static void __exit ksphy_exit(void)
+   {
+ + 	phy_driver_unregister(&ksz9021_driver);
+   	phy_driver_unregister(&ks8001_driver);
+   	phy_driver_unregister(&ks8737_driver);
+   	phy_driver_unregister(&ks8041_driver);
+   	phy_driver_unregister(&ks8051_driver);
+   }
+ diff -crN linux-3.2.1_o/drivers/net/phy/phy_device.c linux-3.2.1/drivers/net/phy/phy_device.c
+ *** linux-3.2.1_o/drivers/net/phy/phy_device.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/net/phy/phy_device.c	2014-11-25 13:19:15.783313495 +0900
+ ***************
+ *** 169,176 ****
+   	dev->link = 1;
+   	dev->interface = PHY_INTERFACE_MODE_GMII;
+   
+   	dev->autoneg = AUTONEG_ENABLE;
+ ! 
+   	dev->addr = addr;
+   	dev->phy_id = phy_id;
+   	dev->bus = bus;
+ --- 169,179 ----
+   	dev->link = 1;
+   	dev->interface = PHY_INTERFACE_MODE_GMII;
+   
+ + #if 1
+   	dev->autoneg = AUTONEG_ENABLE;
+ ! #else
+ ! 	dev->autoneg = AUTONEG_DISABLE;
+ ! #endif
+   	dev->addr = addr;
+   	dev->phy_id = phy_id;
+   	dev->bus = bus;
+ ***************
+ *** 624,630 ****
+   {
+   	int err;
+   	int ctl = 0;
+ ! 
+   	phydev->pause = phydev->asym_pause = 0;
+   
+   	if (SPEED_1000 == phydev->speed)
+ --- 627,633 ----
+   {
+   	int err;
+   	int ctl = 0;
+ ! 	int bmcr;
+   	phydev->pause = phydev->asym_pause = 0;
+   
+   	if (SPEED_1000 == phydev->speed)
+ ***************
+ *** 637,642 ****
+ --- 640,660 ----
+   	
+   	err = phy_write(phydev, MII_BMCR, ctl);
+   
+ + 	bmcr = phy_read(phydev, MII_BMCR);
+ + 
+ + 	if (bmcr & BMCR_SPEED1000)
+ + 	{
+ + 		printk("1000..haha\n");
+ + 	}
+ + 	if (bmcr & BMCR_SPEED100)
+ + 	{
+ + 		printk("100..haha\n");
+ + 	}
+ + 	else
+ + 	{
+ + 		printk("10..haha\n");
+ + 	}
+ + 
+   	return err;
+   }
+   
+ ***************
+ *** 836,842 ****
+   }
+   EXPORT_SYMBOL(genphy_read_status);
+   
+ ! static int genphy_config_init(struct phy_device *phydev)
+   {
+   	int val;
+   	u32 features;
+ --- 854,860 ----
+   }
+   EXPORT_SYMBOL(genphy_read_status);
+   
+ ! int genphy_config_init(struct phy_device *phydev)
+   {
+   	int val;
+   	u32 features;
+ ***************
+ *** 882,887 ****
+ --- 900,907 ----
+   
+   	return 0;
+   }
+ + EXPORT_SYMBOL(genphy_config_init);
+ + 
+   int genphy_suspend(struct phy_device *phydev)
+   {
+   	int value;
+ diff -crN linux-3.2.1_o/drivers/net/wireless/iwlwifi/iwl-commands.h linux-3.2.1/drivers/net/wireless/iwlwifi/iwl-commands.h
+ *** linux-3.2.1_o/drivers/net/wireless/iwlwifi/iwl-commands.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/net/wireless/iwlwifi/iwl-commands.h	2014-11-25 13:19:15.799070426 +0900
+ ***************
+ *** 809,815 ****
+   #define	IWLAGN_STATION_COUNT	16
+   
+   #define	IWL_INVALID_STATION 	255
+ ! #define IWL_MAX_TID_COUNT	8
+   
+   #define STA_FLG_TX_RATE_MSK		cpu_to_le32(1 << 2)
+   #define STA_FLG_PWR_SAVE_MSK		cpu_to_le32(1 << 8)
+ --- 809,815 ----
+   #define	IWLAGN_STATION_COUNT	16
+   
+   #define	IWL_INVALID_STATION 	255
+ ! #define IWL_MAX_TID_COUNT	9
+   
+   #define STA_FLG_TX_RATE_MSK		cpu_to_le32(1 << 2)
+   #define STA_FLG_PWR_SAVE_MSK		cpu_to_le32(1 << 8)
+ diff -crN linux-3.2.1_o/drivers/net/wireless/iwlwifi/iwl-trans-pcie-int.h linux-3.2.1/drivers/net/wireless/iwlwifi/iwl-trans-pcie-int.h
+ *** linux-3.2.1_o/drivers/net/wireless/iwlwifi/iwl-trans-pcie-int.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/net/wireless/iwlwifi/iwl-trans-pcie-int.h	2014-11-25 13:19:15.804468780 +0900
+ ***************
+ *** 219,225 ****
+ --- 219,227 ----
+   
+   	/* INT ICT Table */
+   	__le32 *ict_tbl;
+ + 	void *ict_tbl_vir;
+   	dma_addr_t ict_tbl_dma;
+ + 	dma_addr_t aligned_ict_tbl_dma;
+   	int ict_index;
+   	u32 inta;
+   	bool use_ict;
+ diff -crN linux-3.2.1_o/drivers/net/wireless/iwlwifi/iwl-trans-pcie-rx.c linux-3.2.1/drivers/net/wireless/iwlwifi/iwl-trans-pcie-rx.c
+ *** linux-3.2.1_o/drivers/net/wireless/iwlwifi/iwl-trans-pcie-rx.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/net/wireless/iwlwifi/iwl-trans-pcie-rx.c	2014-11-25 13:19:15.804468780 +0900
+ ***************
+ *** 1136,1146 ****
+    * ICT functions
+    *
+    ******************************************************************************/
+ ! 
+ ! /* a device (PCI-E) page is 4096 bytes long */
+ ! #define ICT_SHIFT	12
+ ! #define ICT_SIZE	(1 << ICT_SHIFT)
+ ! #define ICT_COUNT	(ICT_SIZE / sizeof(u32))
+   
+   /* Free dram table */
+   void iwl_free_isr_ict(struct iwl_trans *trans)
+ --- 1136,1142 ----
+    * ICT functions
+    *
+    ******************************************************************************/
+ ! #define ICT_COUNT (PAGE_SIZE/sizeof(u32))
+   
+   /* Free dram table */
+   void iwl_free_isr_ict(struct iwl_trans *trans)
+ ***************
+ *** 1148,1166 ****
+   	struct iwl_trans_pcie *trans_pcie =
+   		IWL_TRANS_GET_PCIE_TRANS(trans);
+   
+ ! 	if (trans_pcie->ict_tbl) {
+ ! 		dma_free_coherent(bus(trans)->dev, ICT_SIZE,
+ ! 				  trans_pcie->ict_tbl,
+   				  trans_pcie->ict_tbl_dma);
+ ! 		trans_pcie->ict_tbl = NULL;
+ ! 		trans_pcie->ict_tbl_dma = 0;
+   	}
+   }
+   
+   
+ ! /*
+ !  * allocate dram shared table, it is an aligned memory
+ !  * block of ICT_SIZE.
+    * also reset all data related to ICT table interrupt.
+    */
+   int iwl_alloc_isr_ict(struct iwl_trans *trans)
+ --- 1144,1164 ----
+   	struct iwl_trans_pcie *trans_pcie =
+   		IWL_TRANS_GET_PCIE_TRANS(trans);
+   
+ ! 	if (trans_pcie->ict_tbl_vir) {
+ ! 		dma_free_coherent(bus(trans)->dev,
+ ! 				  (sizeof(u32) * ICT_COUNT) + PAGE_SIZE,
+ ! 				  trans_pcie->ict_tbl_vir,
+   				  trans_pcie->ict_tbl_dma);
+ ! 		trans_pcie->ict_tbl_vir = NULL;
+ ! 		memset(&trans_pcie->ict_tbl_dma, 0,
+ ! 			sizeof(trans_pcie->ict_tbl_dma));
+ ! 		memset(&trans_pcie->aligned_ict_tbl_dma, 0,
+ ! 			sizeof(trans_pcie->aligned_ict_tbl_dma));
+   	}
+   }
+   
+   
+ ! /* allocate dram shared table it is a PAGE_SIZE aligned
+    * also reset all data related to ICT table interrupt.
+    */
+   int iwl_alloc_isr_ict(struct iwl_trans *trans)
+ ***************
+ *** 1168,1193 ****
+   	struct iwl_trans_pcie *trans_pcie =
+   		IWL_TRANS_GET_PCIE_TRANS(trans);
+   
+ ! 	trans_pcie->ict_tbl =
+ ! 		dma_alloc_coherent(bus(trans)->dev, ICT_SIZE,
+ ! 				   &trans_pcie->ict_tbl_dma,
+ ! 				   GFP_KERNEL);
+ ! 	if (!trans_pcie->ict_tbl)
+   		return -ENOMEM;
+   
+ ! 	/* just an API sanity check ... it is guaranteed to be aligned */
+ ! 	if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) {
+ ! 		iwl_free_isr_ict(trans);
+ ! 		return -EINVAL;
+ ! 	}
+ ! 
+ ! 	IWL_DEBUG_ISR(trans, "ict dma addr %Lx\n",
+ ! 		      (unsigned long long)trans_pcie->ict_tbl_dma);
+ ! 
+ ! 	IWL_DEBUG_ISR(trans, "ict vir addr %p\n", trans_pcie->ict_tbl);
+   
+   	/* reset table and index to all 0 */
+ ! 	memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
+   	trans_pcie->ict_index = 0;
+   
+   	/* add periodic RX interrupt */
+ --- 1166,1201 ----
+   	struct iwl_trans_pcie *trans_pcie =
+   		IWL_TRANS_GET_PCIE_TRANS(trans);
+   
+ ! 	/* allocate shrared data table */
+ ! 	trans_pcie->ict_tbl_vir =
+ ! 		dma_alloc_coherent(bus(trans)->dev,
+ ! 				   (sizeof(u32) * ICT_COUNT) + PAGE_SIZE,
+ ! 				   &trans_pcie->ict_tbl_dma, GFP_KERNEL);
+ ! 	if (!trans_pcie->ict_tbl_vir)
+   		return -ENOMEM;
+   
+ ! 	/* align table to PAGE_SIZE boundary */
+ ! 	trans_pcie->aligned_ict_tbl_dma =
+ ! 		ALIGN(trans_pcie->ict_tbl_dma, PAGE_SIZE);
+ ! 
+ ! 	IWL_DEBUG_ISR(trans, "ict dma addr %Lx dma aligned %Lx diff %d\n",
+ ! 			   (unsigned long long)trans_pcie->ict_tbl_dma,
+ ! 			   (unsigned long long)trans_pcie->aligned_ict_tbl_dma,
+ ! 			   (int)(trans_pcie->aligned_ict_tbl_dma -
+ ! 			   trans_pcie->ict_tbl_dma));
+ ! 
+ ! 	trans_pcie->ict_tbl =  trans_pcie->ict_tbl_vir +
+ ! 			  (trans_pcie->aligned_ict_tbl_dma -
+ ! 			  trans_pcie->ict_tbl_dma);
+ ! 
+ ! 	IWL_DEBUG_ISR(trans, "ict vir addr %p vir aligned %p diff %d\n",
+ ! 			     trans_pcie->ict_tbl, trans_pcie->ict_tbl_vir,
+ ! 			(int)(trans_pcie->aligned_ict_tbl_dma -
+ ! 			    trans_pcie->ict_tbl_dma));
+   
+   	/* reset table and index to all 0 */
+ ! 	memset(trans_pcie->ict_tbl_vir, 0,
+ ! 		(sizeof(u32) * ICT_COUNT) + PAGE_SIZE);
+   	trans_pcie->ict_index = 0;
+   
+   	/* add periodic RX interrupt */
+ ***************
+ *** 1205,1224 ****
+   	struct iwl_trans_pcie *trans_pcie =
+   		IWL_TRANS_GET_PCIE_TRANS(trans);
+   
+ ! 	if (!trans_pcie->ict_tbl)
+   		return 0;
+   
+   	spin_lock_irqsave(&trans->shrd->lock, flags);
+   	iwl_disable_interrupts(trans);
+   
+ ! 	memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
+   
+ ! 	val = trans_pcie->ict_tbl_dma >> ICT_SHIFT;
+   
+   	val |= CSR_DRAM_INT_TBL_ENABLE;
+   	val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
+   
+ ! 	IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
+   
+   	iwl_write32(bus(trans), CSR_DRAM_INT_TBL_REG, val);
+   	trans_pcie->use_ict = true;
+ --- 1213,1235 ----
+   	struct iwl_trans_pcie *trans_pcie =
+   		IWL_TRANS_GET_PCIE_TRANS(trans);
+   
+ ! 	if (!trans_pcie->ict_tbl_vir)
+   		return 0;
+   
+   	spin_lock_irqsave(&trans->shrd->lock, flags);
+   	iwl_disable_interrupts(trans);
+   
+ ! 	memset(&trans_pcie->ict_tbl[0], 0, sizeof(u32) * ICT_COUNT);
+   
+ ! 	val = trans_pcie->aligned_ict_tbl_dma >> PAGE_SHIFT;
+   
+   	val |= CSR_DRAM_INT_TBL_ENABLE;
+   	val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
+   
+ ! 	IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%X "
+ ! 			"aligned dma address %Lx\n",
+ ! 			val,
+ ! 			(unsigned long long)trans_pcie->aligned_ict_tbl_dma);
+   
+   	iwl_write32(bus(trans), CSR_DRAM_INT_TBL_REG, val);
+   	trans_pcie->use_ict = true;
+ diff -crN linux-3.2.1_o/drivers/pwm/ecap.c linux-3.2.1/drivers/pwm/ecap.c
+ *** linux-3.2.1_o/drivers/pwm/ecap.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/drivers/pwm/ecap.c	2014-11-25 13:19:15.807524695 +0900
+ ***************
+ *** 0 ****
+ --- 1,472 ----
+ + /*
+ +  * eCAP driver for PWM output generation
+ +  *
+ +  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed .as is. WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + #include <linux/module.h>
+ + #include <linux/kernel.h>
+ + #include <linux/platform_device.h>
+ + #include <linux/err.h>
+ + #include <linux/clk.h>
+ + #include <linux/io.h>
+ + #include <linux/pwm/pwm.h>
+ + #include <linux/slab.h>
+ + #include <linux/pm_runtime.h>
+ + 
+ + #include <plat/clock.h>
+ + #include <plat/config_pwm.h>
+ + 
+ + #define TIMER_CTR_REG			0x0
+ + #define CAPTURE_1_REG			0x08
+ + #define CAPTURE_2_REG			0x0c
+ + #define CAPTURE_3_REG			0x10
+ + #define CAPTURE_4_REG			0x14
+ + #define CAPTURE_CTRL2_REG		0x2A
+ + 
+ + #define ECTRL2_SYNCOSEL_MASK		(0x03 << 6)
+ + 
+ + #define ECTRL2_MDSL_ECAP		BIT(9)
+ + #define ECTRL2_CTRSTP_FREERUN		BIT(4)
+ + #define ECTRL2_PLSL_LOW			BIT(10)
+ + #define ECTRL2_SYNC_EN			BIT(5)
+ + 
+ + struct ecap_regs {
+ + 	unsigned	tsctr;
+ + 	unsigned	cap1;
+ + 	unsigned	cap2;
+ + 	unsigned	cap3;
+ + 	unsigned	cap4;
+ + 	unsigned short	ecctl2;
+ + 	unsigned short	clkconfig;
+ + };
+ + 
+ + struct ecap_pwm {
+ + 	struct pwm_device pwm;
+ + 	struct pwm_device_ops ops;
+ + 	spinlock_t	lock;
+ + 	struct clk	*clk;
+ + 	void __iomem	*mmio_base;
+ + 	u8 version;
+ + 	void __iomem *config_mem_base;
+ + 	struct device *dev;
+ + 	struct ecap_regs ctx;
+ + };
+ + 
+ + static inline struct ecap_pwm *to_ecap_pwm(const struct pwm_device *p)
+ + {
+ + 	return pwm_get_drvdata(p);
+ + }
+ + 
+ + static int ecap_pwm_stop(struct pwm_device *p)
+ + {
+ + 	unsigned long flags, v;
+ + 	struct ecap_pwm *ep = to_ecap_pwm(p);
+ + 
+ + 	/* Trying to stop a non-running PWM, not allowed */
+ + 	if (!pwm_is_running(p))
+ + 		return -EPERM;
+ + 
+ + 	spin_lock_irqsave(&ep->lock, flags);
+ + 	v = readw(ep->mmio_base + CAPTURE_CTRL2_REG);
+ + 	v &= ~(ECTRL2_CTRSTP_FREERUN | ECTRL2_MDSL_ECAP);
+ + 	writew(v, ep->mmio_base + CAPTURE_CTRL2_REG);
+ + 	spin_unlock_irqrestore(&ep->lock, flags);
+ + 
+ + 	/* For PWM clock should be disabled on stop */
+ + 	pm_runtime_put_sync(ep->dev);
+ + 	clear_bit(FLAG_RUNNING, &p->flags);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static int ecap_pwm_start(struct pwm_device *p)
+ + {
+ + 	int ret = 0;
+ + 	unsigned long flags, v;
+ + 	struct ecap_pwm *ep = to_ecap_pwm(p);
+ + 
+ + 	/* Trying to start a running PWM, not allowed */
+ + 	if (pwm_is_running(p))
+ + 		return -EPERM;
+ + 
+ + 	/* For PWM clock should be enabled on start */
+ + 	pm_runtime_get_sync(ep->dev);
+ + 
+ + 	spin_lock_irqsave(&ep->lock, flags);
+ + 	v = readw(ep->mmio_base + CAPTURE_CTRL2_REG);
+ + 	v |= (ECTRL2_CTRSTP_FREERUN | ECTRL2_MDSL_ECAP);
+ + 	writew(v, ep->mmio_base + CAPTURE_CTRL2_REG);
+ + 	spin_unlock_irqrestore(&ep->lock, flags);
+ + 	set_bit(FLAG_RUNNING, &p->flags);
+ + 
+ + 	return ret;
+ + }
+ + 
+ + static int ecap_pwm_set_polarity(struct pwm_device *p, char pol)
+ + {
+ + 	unsigned long flags, v;
+ + 	struct ecap_pwm *ep = to_ecap_pwm(p);
+ + 
+ + 	pm_runtime_get_sync(ep->dev);
+ + 
+ + 	spin_lock_irqsave(&ep->lock, flags);
+ + 	v = readw(ep->mmio_base + CAPTURE_CTRL2_REG);
+ + 	v &= ~ECTRL2_PLSL_LOW;
+ + 	v |= pol << 10;
+ + 	writew(v, ep->mmio_base + CAPTURE_CTRL2_REG);
+ + 	spin_unlock_irqrestore(&ep->lock, flags);
+ + 
+ + 	pm_runtime_put_sync(ep->dev);
+ + 	return 0;
+ + }
+ + 
+ + static int ecap_pwm_config_period(struct pwm_device *p)
+ + {
+ + 	unsigned long flags;
+ + 	struct ecap_pwm *ep = to_ecap_pwm(p);
+ + 
+ + 	 pm_runtime_get_sync(ep->dev);
+ + 
+ + 	spin_lock_irqsave(&ep->lock, flags);
+ + 	writel((p->period_ticks) - 1, ep->mmio_base + CAPTURE_3_REG);
+ + 	spin_unlock_irqrestore(&ep->lock, flags);
+ + 
+ + 	pm_runtime_put_sync(ep->dev);
+ + 	return 0;
+ + }
+ + 
+ + static int ecap_pwm_config_duty(struct pwm_device *p)
+ + {
+ + 	unsigned long flags, v;
+ + 	struct ecap_pwm *ep = to_ecap_pwm(p);
+ + 
+ + 	pm_runtime_get_sync(ep->dev);
+ + 
+ + 	spin_lock_irqsave(&ep->lock, flags);
+ + 	v = readw(ep->mmio_base + CAPTURE_CTRL2_REG);
+ + 	v |= (ECTRL2_MDSL_ECAP | ECTRL2_SYNCOSEL_MASK);
+ + 	writew(v, ep->mmio_base + CAPTURE_CTRL2_REG);
+ + 
+ + 	if (p->duty_ticks > 0) {
+ + 		writel(p->duty_ticks, ep->mmio_base + CAPTURE_4_REG);
+ + 	} else {
+ + 		writel(p->duty_ticks, ep->mmio_base + CAPTURE_2_REG);
+ + 		writel(0, ep->mmio_base + TIMER_CTR_REG);
+ + 	}
+ + 	spin_unlock_irqrestore(&ep->lock, flags);
+ + 
+ + 	if (!pwm_is_running(p)) {
+ + 		v = readw(ep->mmio_base + CAPTURE_CTRL2_REG);
+ + 		v &= ~ECTRL2_MDSL_ECAP;
+ + 		writew(v, ep->mmio_base + CAPTURE_CTRL2_REG);
+ + 	}
+ + 
+ + 	pm_runtime_put_sync(ep->dev);
+ + 	return 0;
+ + }
+ + 
+ + static int ecap_pwm_config(struct pwm_device *p,
+ + 				struct pwm_config *c)
+ + {
+ + 	int ret = 0;
+ + 	switch (c->config_mask) {
+ + 
+ + 	case BIT(PWM_CONFIG_DUTY_TICKS):
+ + 		p->duty_ticks = c->duty_ticks;
+ + 		ret = ecap_pwm_config_duty(p);
+ + 		break;
+ + 
+ + 	case BIT(PWM_CONFIG_PERIOD_TICKS):
+ + 		p->period_ticks = c->period_ticks;
+ + 		ret = ecap_pwm_config_period(p);
+ + 		break;
+ + 
+ + 	case BIT(PWM_CONFIG_POLARITY):
+ + 		p->active_high = c->polarity;
+ + 		ret = ecap_pwm_set_polarity(p, c->polarity);
+ + 		break;
+ + 
+ + 	case BIT(PWM_CONFIG_START):
+ + 		ret = ecap_pwm_start(p);
+ + 		break;
+ + 
+ + 	case BIT(PWM_CONFIG_STOP):
+ + 		ret = ecap_pwm_stop(p);
+ + 		break;
+ + 	}
+ + 
+ + 	return ret;
+ + }
+ + 
+ + static int ecap_pwm_request(struct pwm_device *p)
+ + {
+ + 	struct ecap_pwm *ep = to_ecap_pwm(p);
+ + 
+ + 	p->tick_hz = clk_get_rate(ep->clk);
+ + 	return 0;
+ + }
+ + 
+ + static int ecap_frequency_transition_cb(struct pwm_device *p)
+ + {
+ + 	struct ecap_pwm *ep = to_ecap_pwm(p);
+ + 	unsigned long duty_ns, rate;
+ + 
+ + 	rate = clk_get_rate(ep->clk);
+ + 	if (rate == p->tick_hz)
+ + 		return 0;
+ + 	p->tick_hz = rate;
+ + 
+ + 	duty_ns = p->duty_ns;
+ + 	if (pwm_is_running(p)) {
+ + 		pwm_stop(p);
+ + 		pwm_set_duty_ns(p, 0);
+ + 		pwm_set_period_ns(p, p->period_ns);
+ + 		pwm_set_duty_ns(p, duty_ns);
+ + 		pwm_start(p);
+ + 	} else {
+ + 		pwm_set_duty_ns(p, 0);
+ + 		pwm_set_period_ns(p, p->period_ns);
+ + 		pwm_set_duty_ns(p, duty_ns);
+ + 	}
+ + 		return 0;
+ + }
+ + 
+ + static int ecap_probe(struct platform_device *pdev)
+ + {
+ + 	struct ecap_pwm *ep = NULL;
+ + 	struct resource *r;
+ + 	int ret = 0;
+ + 	int val;
+ + 	char con_id[PWM_CON_ID_STRING_LENGTH] = "epwmss";
+ + 	struct pwmss_platform_data *pdata = (&pdev->dev)->platform_data;
+ + 
+ + 	ep = kzalloc(sizeof(*ep), GFP_KERNEL);
+ + 
+ + 	if (!ep) {
+ + 		dev_err(&pdev->dev, "failed to allocate memory\n");
+ + 		return -ENOMEM;
+ + 	}
+ + 
+ + 	ep->version = pdata->version;
+ + 
+ + 	if (ep->version == PWM_VERSION_1) {
+ + 		sprintf(con_id, "%s%d_%s", con_id, pdev->id, "fck");
+ + 		ep->clk = clk_get(&pdev->dev, con_id);
+ + 	} else
+ + 		ep->clk = clk_get(&pdev->dev, "ecap");
+ + 
+ + 	pm_runtime_enable(&pdev->dev);
+ + 	ep->dev = &pdev->dev;
+ + 	if (IS_ERR(ep->clk)) {
+ + 		ret = PTR_ERR(ep->clk);
+ + 		goto err_clk_get;
+ + 	}
+ + 
+ + 	if (ep->version == PWM_VERSION_1) {
+ + 		r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ + 
+ + 		if (!r) {
+ + 			dev_err(&pdev->dev, "no memory resource defined\n");
+ + 			ret = -ENOMEM;
+ + 			goto err_get_resource;
+ + 		}
+ + 
+ + 		ep->config_mem_base = ioremap(r->start, resource_size(r));
+ + 
+ + 		if (!ep->config_mem_base) {
+ + 
+ + 			dev_err(&pdev->dev, "failed to ioremap() registers\n");
+ + 			ret = -ENOMEM;
+ + 			goto err_get_resource;
+ + 		}
+ + 
+ + 		pm_runtime_get_sync(ep->dev);
+ + 		val = readw(ep->config_mem_base + PWMSS_CLKCONFIG);
+ + 		val |= BIT(ECAP_CLK_EN);
+ + 		writew(val, ep->config_mem_base + PWMSS_CLKCONFIG);
+ + 		pm_runtime_put_sync(ep->dev);
+ + 	}
+ + 
+ + 	spin_lock_init(&ep->lock);
+ + 	ep->ops.config = ecap_pwm_config;
+ + 	ep->ops.request = ecap_pwm_request;
+ + 	ep->ops.freq_transition_notifier_cb = ecap_frequency_transition_cb;
+ + 
+ + 	if (ep->version == PWM_VERSION_1)
+ + 		r = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ + 	else
+ + 		r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ + 
+ + 	if (!r) {
+ + 		dev_err(&pdev->dev, "no memory resource defined\n");
+ + 		ret = -ENODEV;
+ + 		goto err_request_mem;
+ + 	}
+ + 
+ + 	r = request_mem_region(r->start, resource_size(r), pdev->name);
+ + 	if (!r) {
+ + 		dev_err(&pdev->dev, "failed to request memory resource\n");
+ + 		ret = -EBUSY;
+ + 		goto err_request_mem;
+ + 	}
+ + 
+ + 	ep->mmio_base = ioremap(r->start, resource_size(r));
+ + 	if (!ep->mmio_base) {
+ + 		dev_err(&pdev->dev, "failed to ioremap() registers\n");
+ + 		ret = -ENODEV;
+ + 		goto err_ioremap;
+ + 	}
+ + 
+ + 	ep->pwm.ops = &ep->ops;
+ + 	pwm_set_drvdata(&ep->pwm, ep);
+ + 	ret =  pwm_register(&ep->pwm, &pdev->dev, -1);
+ + 	platform_set_drvdata(pdev, ep);
+ + 	/* Inverse the polarity of PWM wave */
+ + 	if (pdata->chan_attrib[0].inverse_pol) {
+ + 		ep->pwm.active_high = 1;
+ + 		ecap_pwm_set_polarity(&ep->pwm, 1);
+ + 	}
+ + 	return 0;
+ + 
+ + err_ioremap:
+ + 	release_mem_region(r->start, resource_size(r));
+ + err_request_mem:
+ + 	if (ep->version == PWM_VERSION_1) {
+ + 		iounmap(ep->config_mem_base);
+ + 		ep->config_mem_base = NULL;
+ + 	}
+ + err_get_resource:
+ + 	clk_put(ep->clk);
+ + 	pm_runtime_disable(&pdev->dev);
+ + err_clk_get:
+ + 	kfree(ep);
+ + 	return ret;
+ + }
+ + 
+ + #ifdef CONFIG_PM
+ + 
+ + void ecap_save_reg(struct ecap_pwm *ep)
+ + {
+ + 	pm_runtime_get_sync(ep->dev);
+ + 
+ + 	ep->ctx.ecctl2 = readw(ep->mmio_base + CAPTURE_CTRL2_REG);
+ + 	ep->ctx.tsctr = readl(ep->mmio_base + TIMER_CTR_REG);
+ + 	ep->ctx.cap1 = readl(ep->mmio_base + CAPTURE_1_REG);
+ + 	ep->ctx.cap2 = readl(ep->mmio_base + CAPTURE_2_REG);
+ + 	ep->ctx.cap4 = readl(ep->mmio_base + CAPTURE_4_REG);
+ + 	ep->ctx.cap3 = readl(ep->mmio_base + CAPTURE_3_REG);
+ + 
+ + 	ep->ctx.clkconfig = readw(ep->config_mem_base + PWMSS_CLKCONFIG);
+ + 
+ + 	pm_runtime_put_sync(ep->dev);
+ + }
+ + 
+ + void ecap_restore_reg(struct ecap_pwm *ep)
+ + {
+ + 	writew(ep->ctx.clkconfig, ep->config_mem_base + PWMSS_CLKCONFIG);
+ + 
+ + 	writel(ep->ctx.cap3, ep->mmio_base + CAPTURE_3_REG);
+ + 	writel(ep->ctx.cap4, ep->mmio_base + CAPTURE_4_REG);
+ + 	writel(ep->ctx.cap2, ep->mmio_base + CAPTURE_2_REG);
+ + 	writel(ep->ctx.cap1, ep->mmio_base + CAPTURE_1_REG);
+ + 	writel(ep->ctx.tsctr, ep->mmio_base + TIMER_CTR_REG);
+ + 	writew(ep->ctx.ecctl2, ep->mmio_base + CAPTURE_CTRL2_REG);
+ + }
+ + 
+ + static int ecap_suspend(struct platform_device *pdev, pm_message_t state)
+ + {
+ + 	struct ecap_pwm *ep = platform_get_drvdata(pdev);
+ + 
+ + 	ecap_save_reg(ep);
+ + 	pm_runtime_put_sync(ep->dev);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static int ecap_resume(struct platform_device *pdev)
+ + {
+ + 	struct ecap_pwm *ep = platform_get_drvdata(pdev);
+ + 
+ + 	pm_runtime_get_sync(ep->dev);
+ + 
+ + 	ecap_restore_reg(ep);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + #else
+ + #define ecap_suspend NULL
+ + #define ecap_resume NULL
+ + #endif
+ + 
+ + static int __devexit ecap_remove(struct platform_device *pdev)
+ + {
+ + 	struct ecap_pwm *ep = platform_get_drvdata(pdev);
+ + 	struct resource *r;
+ + 	struct pwmss_platform_data *pdata;
+ + 	int val;
+ + 
+ + 	if (ep->version == PWM_VERSION_1) {
+ + 		pdata = (&pdev->dev)->platform_data;
+ + 		pm_runtime_get_sync(ep->dev);
+ + 		val = readw(ep->config_mem_base + PWMSS_CLKCONFIG);
+ + 		val &= ~BIT(ECAP_CLK_EN);
+ + 		writew(val, ep->config_mem_base + PWMSS_CLKCONFIG);
+ + 		pm_runtime_put_sync(ep->dev);
+ + 		iounmap(ep->config_mem_base);
+ + 		ep->config_mem_base = NULL;
+ + 	}
+ + 
+ + 	pwm_unregister(&ep->pwm);
+ + 	iounmap(ep->mmio_base);
+ + 
+ + 	if (ep->version == PWM_VERSION_1)
+ + 		r = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ + 	else
+ + 		r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ + 	release_mem_region(r->start, resource_size(r));
+ + 	platform_set_drvdata(pdev, NULL);
+ + 	clk_put(ep->clk);
+ + 	pm_runtime_disable(&pdev->dev);
+ + 	kfree(ep);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static struct platform_driver ecap_driver = {
+ + 	.driver	= {
+ + 		.name	= "ecap",
+ + 		.owner	= THIS_MODULE,
+ + 	},
+ + 	.probe		= ecap_probe,
+ + 	.remove		= __devexit_p(ecap_remove),
+ + 	.suspend	= ecap_suspend,
+ + 	.resume		= ecap_resume,
+ + };
+ + 
+ + static int __init ecap_init(void)
+ + {
+ + 	return platform_driver_register(&ecap_driver);
+ + }
+ + 
+ + static void __exit ecap_exit(void)
+ + {
+ + 	platform_driver_unregister(&ecap_driver);
+ + }
+ + 
+ + module_init(ecap_init);
+ + module_exit(ecap_exit);
+ + 
+ + MODULE_AUTHOR("Texas Instruments");
+ + MODULE_DESCRIPTION("Driver for Davinci eCAP peripheral");
+ + MODULE_LICENSE("GPL v2");
+ + MODULE_ALIAS("platform:ecap");
+ diff -crN linux-3.2.1_o/drivers/pwm/ehrpwm.c linux-3.2.1/drivers/pwm/ehrpwm.c
+ *** linux-3.2.1_o/drivers/pwm/ehrpwm.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/drivers/pwm/ehrpwm.c	2014-11-25 13:19:15.811062565 +0900
+ ***************
+ *** 0 ****
+ --- 1,1646 ----
+ + /*
+ +  * eHRPWM driver for simple PWM output generation
+ +  *
+ +  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed .as is. WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + #include <linux/module.h>
+ + #include <linux/init.h>
+ + #include <linux/clk.h>
+ + #include <linux/err.h>
+ + #include <linux/io.h>
+ + #include <linux/interrupt.h>
+ + #include <linux/platform_device.h>
+ + #include <linux/slab.h>
+ + #include <linux/pwm/pwm.h>
+ + #include <linux/pwm/ehrpwm.h>
+ + #include <linux/pm_runtime.h>
+ + 
+ + #include <plat/clock.h>
+ + #include <plat/config_pwm.h>
+ + 
+ + #ifdef DEBUG
+ + #define debug(format, args...) printk(format, ##args)
+ + #else
+ + #define debug(format, args...) { }
+ + #endif
+ + 
+ + /******************** Time base sub module*****************************/
+ + #define TBCTL				0x0
+ + #define TBSTS				0x2
+ + #define TBPHS				0x6
+ + #define TBCTR				0x8
+ + #define TBPRD				0xA
+ + 
+ + #define TBCTL_CLKDIV_MASK		(BIT(12) | BIT(11) | BIT(10))
+ + #define TBCTL_HSPCLKDIV_MASK		(BIT(9) | BIT(8) | BIT(7))
+ + #define TBCTL_SYNCOSEL_MASK		(BIT(5) | BIT(4))
+ + #define TBCTL_CTRMODE_MASK		(BIT(1) | BIT(0))
+ + 
+ + #define	TBCTL_CLKDIV_POS		0xA
+ + #define TBCTL_HSPCLKDIV_POS		0x7
+ + #define TBCTL_PHSEN_POS			0x2
+ + #define TBCTL_SYNCOSEL_POS		0x4
+ + #define TBCTL_PHSDIR_POS		0xD
+ + #define TBCTL_FRC_SYC_POS		0x6
+ + #define TBCTL_LOAD_MD_POS		0x3
+ + 
+ + #define TBCTL_FREERUN_FREE		0x2
+ + #define TBCTL_CTRMOD_CTRUP		0x0
+ + 
+ + /******************* Counter-Compare Sub Module ***********************/
+ + #define CMPCTL				0xE
+ + #define CMPA				0x12
+ + #define CMPB				0x14
+ + 
+ + #define CMPCTL_LDBMODE_MASK		(BIT(3) | BIT(2))
+ + #define CMPCTL_LDAMODE_MASK		(BIT(1) | BIT(0))
+ + 
+ + #define CMPCTL_SHDAMODE_POS		0x4
+ + #define CMPCTL_SHDBMODE_POS		0x6
+ + #define CMPCTL_LDBMODE_POS		0x2
+ + 
+ + /*********************** Action Control Sub module ********************/
+ + #define AQCTLA				0x16
+ + #define AQCTLB				0x18
+ + #define AQSFRC				0x1A
+ + #define AQCSFRC				0x1c
+ + 
+ + #define ACTCTL_CBD_MASK			(BIT(11) | BIT(10))
+ + #define ACTCTL_CBU_MASK			(BIT(9) | BIT(8))
+ + #define ACTCTL_CAD_MASK			(BIT(7) | BIT(6))
+ + #define ACTCTL_CAU_MASK			(BIT(5) | BIT(4))
+ + #define ACTCTL_CPRD_MASK		(BIT(3) | BIT(2))
+ + #define ACTCTL_CZRO_MASK		(BIT(1) | BIT(0))
+ + 
+ + #define ACTCTL_CTREQPRD_POS		0x2
+ + #define ACTCTL_CTREQCMPAUP_POS		0x4
+ + #define ACTCTL_CTREQCMPADN_POS		0x6
+ + #define ACTCTL_CTREQCMPBUP_POS		0x8
+ + #define ACTCTL_CTREQCMPBDN_POS		0xA
+ + 
+ + #define ACTCTL_CTREQCMP_LOW		0x1
+ + #define ACTCTL_CTREQCMP_HIGH		0x2
+ + #define ACTCTL_CTREQZRO_LOW		0x1
+ + #define ACTCTL_CTREQZRO_HIGH		0x2
+ + 
+ + #define AQSFRC_ACTA_MASK		(BIT(1) | BIT(0))
+ + #define AQSFRC_ACTB_MASK		(BIT(4) | BIT(3))
+ + 
+ + #define AQSFRC_ACTB_POS			0x3
+ + #define AQSFRC_OTFRCA_POS		0x2
+ + #define AQSFRC_OTFRCB_POS		0x5
+ + 
+ + #define AQSFRC_RLDCSF_ZRO		0
+ + #define AQSFRC_RLDCSF_IMDT		(BIT(1) | BIT(0))
+ + #define AQSFRC_LDMD_POS			0x6
+ + #define AQSFRC_CFRC_LOAD_MASK		(BIT(7) | BIT(6))
+ + 
+ + #define AQCSFRC_CSF_FRCDIS		0
+ + #define AQCSFRC_CSF_FRCLOW		BIT(0)
+ + #define AQCSFRC_OUTB_MASK		(BIT(3) | BIT(2))
+ + #define AQCSFRC_OUTA_MASK		(BIT(1) | BIT(0))
+ + #define AQCSFRC_OUTB_POS		0x2
+ + 
+ + /******************** Dead Band Generator Sub module *******************/
+ + #define DBCTL				0x1E
+ + #define DBRED				0x20
+ + #define DBFED				0x22
+ + 
+ + #define DBCTL_INMODE_MASK		(BIT(5) | BIT(4))
+ + #define DBCTL_PLSEL_MASK		(BIT(3) | BIT(2))
+ + #define DBCTL_OUTMODE_MASK		(BIT(1) | BIT(0))
+ + 
+ + #define DBCTL_INMODE_POS		0x4
+ + #define DBCTL_POLSEL_POS		0x2
+ + 
+ + /********************** PWM Chopper Sub module ************************/
+ + #define PCCTL				0x3C
+ + 
+ + #define PCCTL_CHPDUTY_MASK		(BIT(10) | BIT(9) | BIT(8))
+ + #define PCCTL_CHPFREQ_MASK		(BIT(7) | BIT(6) | BIT(5))
+ + #define PCCTL_OSHTWTH_MASK		(BIT(4) | BIT(3) | BIT(2) | BIT(1))
+ + 
+ + #define PCCTL_CHPDUTY_POS		0x8
+ + #define PCCTL_CHPFRQ_POS		0x5
+ + #define PCCTL_OSTWID_POS		0x1
+ + 
+ + /*************************Trip-zone submodule **************************/
+ + #define TZSEL				0x24
+ + #define TZCTL				0x28
+ + #define TZEINT				0x2A
+ + #define TZFLG				0x2C
+ + #define TZCLR				0x2E
+ + #define TZFRC				0x30
+ + 
+ + #define TZCTL_ACTA_MASK			(BIT(1) | BIT(0))
+ + #define TZCTL_ACTB_MASK			(BIT(3) | BIT(2))
+ + 
+ + #define TZCTL_ACTB_POS			0x2
+ + 
+ + #define TZEINT_OSHTEVT_POS		0x2
+ + #define TZEINT_CBCEVT_POS		0x1
+ + 
+ + /*************************Event-Trigger submodule registers**************/
+ + #define ETSEL				0x32
+ + #define ETPS				0x34
+ + #define ETFLG				0x36
+ + #define ETCLR				0x38
+ + #define ETFRC				0x3A
+ + 
+ + #define ETSEL_INTSEL_MASK		(BIT(2) | BIT(1) | BIT(0))
+ + #define ETPS_INTCNT_MASK		(BIT(3) | BIT(2))
+ + #define ETPS_INTPRD_MASK		(BIT(1) | BIT(0))
+ + 
+ + #define ETSEL_EN_INT_EN_POS		0x3
+ + 
+ + /**********************High Resolution Registers ********************/
+ + #define TBPHSHR				0x4
+ + #define CMPAHR				0x10
+ + #define HRCNFG				0x1040
+ + 
+ + #define AM335X_HRCNFG			0x40
+ + 
+ + #define HRCNFG_EDGEMD_MASK		(BIT(1) | BIT(0))
+ + #define HRCNFG_LDMD_POS			0x3
+ + #define HRCNFG_CTLMD_POS		0x2
+ + 
+ + struct ehrpwm_suspend_params {
+ + 	struct pwm_device *pch;
+ + 	unsigned long req_delay_cycles;
+ + 	unsigned long act_delay;
+ + } ehrpwm_suspend_params;
+ + 
+ + static inline unsigned short ehrpwm_read(struct ehrpwm_pwm *ehrpwm,
+ + 	unsigned int offset)
+ + {
+ + 	return readw(ehrpwm->mmio_base + offset);
+ + }
+ + 
+ + static inline void ehrpwm_write(struct ehrpwm_pwm *ehrpwm, unsigned int offset,
+ + 	unsigned short val)
+ + {
+ + 	writew(val, ehrpwm->mmio_base + offset);
+ + }
+ + 
+ + static void ehrpwm_reg_config(struct ehrpwm_pwm *ehrpwm, unsigned int offset,
+ + 	       unsigned short val, unsigned short mask)
+ + {
+ + 	unsigned short read_val;
+ + 
+ + 	read_val = ehrpwm_read(ehrpwm, offset);
+ + 	read_val = read_val & ~mask;
+ + 	read_val = read_val | val;
+ + 	ehrpwm_write(ehrpwm, offset, read_val);
+ + }
+ + 
+ + static inline struct ehrpwm_pwm *to_ehrpwm_pwm(const struct pwm_device *p)
+ + {
+ + 	return pwm_get_drvdata(p);
+ + }
+ + 
+ + /* Time Base Module Configurations */
+ + int ehrpwm_tb_set_prescalar_val(struct pwm_device *p, unsigned char clkdiv,
+ + 	unsigned char hspclkdiv)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 
+ + 	if (clkdiv > 0x7 || hspclkdiv > 0x7)
+ + 		return -EINVAL;
+ + 
+ + 	ehrpwm_reg_config(ehrpwm, TBCTL, clkdiv << TBCTL_CLKDIV_POS,
+ + 		       TBCTL_CLKDIV_MASK);
+ + 	ehrpwm_reg_config(ehrpwm, TBCTL, hspclkdiv << TBCTL_HSPCLKDIV_POS,
+ + 		       TBCTL_HSPCLKDIV_MASK);
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_tb_set_prescalar_val);
+ + 
+ + int ehrpwm_tb_config_sync(struct pwm_device *p, unsigned char phsen,
+ + 	unsigned char syncosel)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 
+ + 	if (phsen > 1 || syncosel > 0x3)
+ + 		return -EINVAL;
+ + 
+ + 	ehrpwm_reg_config(ehrpwm, TBCTL, phsen << TBCTL_PHSEN_POS, BIT(2));
+ + 	ehrpwm_reg_config(ehrpwm, TBCTL, syncosel << TBCTL_SYNCOSEL_POS,
+ + 		       TBCTL_SYNCOSEL_MASK);
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_tb_config_sync);
+ + 
+ + int ehrpwm_tb_set_counter_mode(struct pwm_device *p, unsigned char ctrmode,
+ + 	       unsigned char phsdir)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 
+ + 	if (ctrmode > 0x3 || phsdir > 1)
+ + 		return -EINVAL;
+ + 
+ + 	ehrpwm_reg_config(ehrpwm, TBCTL, phsdir << TBCTL_PHSDIR_POS, BIT(13));
+ + 	ehrpwm_reg_config(ehrpwm, TBCTL, ctrmode, TBCTL_CTRMODE_MASK);
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_tb_set_counter_mode);
+ + 
+ + int ehrpwm_tb_force_sync(struct pwm_device *p)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 
+ + 	ehrpwm_reg_config(ehrpwm, TBCTL, ENABLE << TBCTL_FRC_SYC_POS, BIT(6));
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_tb_force_sync);
+ + 
+ + int ehrpwm_tb_set_periodload(struct pwm_device *p, unsigned char loadmode)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 
+ + 	if (loadmode > 0x1)
+ + 		return -EINVAL;
+ + 
+ + 	ehrpwm_reg_config(ehrpwm, TBCTL, loadmode << TBCTL_LOAD_MD_POS, BIT(3));
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_tb_set_periodload);
+ + 
+ + int ehrpwm_tb_read_status(struct pwm_device *p, unsigned short *val)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 
+ + 	*val = ehrpwm_read(ehrpwm, TBSTS);
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_tb_read_status);
+ + 
+ + int ehrpwm_tb_read_counter(struct pwm_device *p, unsigned short *val)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 
+ + 	*val = ehrpwm_read(ehrpwm, TBCTR);
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_tb_read_counter);
+ + 
+ + int ehrpwm_tb_set_period(struct pwm_device *p,	unsigned short val)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 
+ + 	ehrpwm_write(ehrpwm, TBPRD, val);
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_tb_set_period);
+ + 
+ + int ehrpwm_tb_set_phase(struct pwm_device *p, unsigned short val)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 
+ + 	ehrpwm_write(ehrpwm, TBPHS, val);
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_tb_set_phase);
+ + 
+ + int ehrpwm_cmp_set_cmp_ctl(struct pwm_device *p, unsigned char shdwamode,
+ + 	unsigned char shdwbmode, unsigned char loadamode,
+ + 	unsigned char loadbmode)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 
+ + 	if (shdwamode > 0x1 || shdwbmode > 0x1 || loadamode > 0x3 ||
+ + 		loadbmode > 0x3)
+ + 		return -EINVAL;
+ + 
+ + 	ehrpwm_reg_config(ehrpwm, CMPCTL, shdwamode << CMPCTL_SHDAMODE_POS,
+ + 		       BIT(4));
+ + 	ehrpwm_reg_config(ehrpwm, CMPCTL, shdwbmode << CMPCTL_SHDBMODE_POS,
+ + 		       BIT(6));
+ + 	ehrpwm_reg_config(ehrpwm, CMPCTL, loadamode, CMPCTL_LDAMODE_MASK);
+ + 	ehrpwm_reg_config(ehrpwm, CMPCTL, loadbmode << CMPCTL_LDBMODE_POS,
+ + 		       CMPCTL_LDBMODE_MASK);
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_cmp_set_cmp_ctl);
+ + 
+ + int ehrpwm_cmp_set_cmp_val(struct pwm_device *p, unsigned char reg,
+ + 	unsigned short val)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 	unsigned char offset;
+ + 
+ + 	if (reg > 0x1)
+ + 		return -EINVAL;
+ + 
+ + 	if (reg == 0)
+ + 		offset = CMPA;
+ + 	else
+ + 		offset = CMPB;
+ + 
+ + 	ehrpwm_write(ehrpwm, offset, val);
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_cmp_set_cmp_val);
+ + 
+ + int ehrpwm_aq_set_act_ctrl(struct pwm_device *p, struct aq_config_params *cfg)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 	unsigned char reg;
+ + 
+ + 	if (!cfg)
+ + 		return -EINVAL;
+ + 
+ + 	if (cfg->ch > 1 || cfg->ctreqzro > 3 || cfg->ctreqprd > 3 ||
+ + 		cfg->ctreqcmpaup > 3 || cfg->ctreqcmpadown > 3 ||
+ + 		cfg->ctreqcmpbup > 3 || cfg->ctreqcmpbdown > 3)
+ + 		return -EINVAL;
+ + 
+ + 	if (cfg->ch == 0)
+ + 		reg = AQCTLA;
+ + 	else
+ + 		reg = AQCTLB;
+ + 
+ + 	ehrpwm_reg_config(ehrpwm, reg, cfg->ctreqzro, ACTCTL_CZRO_MASK);
+ + 	ehrpwm_reg_config(ehrpwm, reg, cfg->ctreqprd << ACTCTL_CTREQPRD_POS,
+ + 		       ACTCTL_CPRD_MASK);
+ + 	ehrpwm_reg_config(ehrpwm, reg, cfg->ctreqcmpaup <<
+ + 		       ACTCTL_CTREQCMPAUP_POS, ACTCTL_CAU_MASK);
+ + 	ehrpwm_reg_config(ehrpwm, reg, cfg->ctreqcmpadown <<
+ + 		       ACTCTL_CTREQCMPADN_POS, ACTCTL_CAD_MASK);
+ + 	ehrpwm_reg_config(ehrpwm, reg, cfg->ctreqcmpbup <<
+ + 		       ACTCTL_CTREQCMPBUP_POS, ACTCTL_CBU_MASK);
+ + 	ehrpwm_reg_config(ehrpwm, reg, cfg->ctreqcmpbdown <<
+ + 		       ACTCTL_CTREQCMPBDN_POS, ACTCTL_CBD_MASK);
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_aq_set_act_ctrl);
+ + 
+ + int ehrpwm_aq_set_one_shot_act(struct pwm_device  *p, unsigned char ch,
+ + 	unsigned char act)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 
+ + 	if (ch > 1 || act > 3)
+ + 		return -EINVAL;
+ + 
+ + 	if (ch == 0)
+ + 		ehrpwm_reg_config(ehrpwm, AQSFRC, act, AQSFRC_ACTA_MASK);
+ + 	else
+ + 		ehrpwm_reg_config(ehrpwm, AQSFRC, act << AQSFRC_ACTB_POS,
+ + 			       AQSFRC_ACTB_MASK);
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_aq_set_one_shot_act);
+ + 
+ + int ehrpwm_aq_ot_frc(struct pwm_device *p, unsigned char ch)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 
+ + 	if (ch > 1)
+ + 		return -EINVAL;
+ + 
+ + 	if (ch == 0)
+ + 		ehrpwm_reg_config(ehrpwm, AQSFRC, ENABLE << AQSFRC_OTFRCA_POS,
+ + 			       BIT(2));
+ + 	else
+ + 		ehrpwm_reg_config(ehrpwm, AQSFRC, ENABLE << AQSFRC_OTFRCB_POS,
+ + 			       BIT(5));
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_aq_ot_frc);
+ + 
+ + int ehrpwm_aq_set_csfrc_load_mode(struct pwm_device *p, unsigned char loadmode)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 
+ + 	if (loadmode > 0x3)
+ + 		return -EINVAL;
+ + 
+ + 	ehrpwm_reg_config(ehrpwm, AQSFRC, loadmode << AQSFRC_LDMD_POS,
+ + 		       AQSFRC_CFRC_LOAD_MASK);
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_aq_set_csfrc_load_mode);
+ + 
+ + int ehrpwm_aq_continuous_frc(struct pwm_device *p, unsigned char ch,
+ + 	unsigned char act)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 
+ + 	if (ch > 1)
+ + 		return -EINVAL;
+ + 
+ + 	if (ch == 0)
+ + 		ehrpwm_reg_config(ehrpwm, AQCSFRC, act, AQCSFRC_OUTA_MASK);
+ + 	else
+ + 		ehrpwm_reg_config(ehrpwm, AQCSFRC, act << AQCSFRC_OUTB_POS,
+ + 			       AQCSFRC_OUTB_MASK);
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_aq_continuous_frc);
+ + 
+ + int ehrpwm_db_get_max_delay(struct pwm_device *p, enum config_mask cfgmask,
+ + 	unsigned long *delay_val)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 	unsigned long delay_ns;
+ + 	unsigned long max_ticks;
+ + 
+ + 	if (cfgmask == CONFIG_NS) {
+ + 		max_ticks = 0x3ff * ehrpwm->prescale_val;
+ + 		delay_ns = pwm_ticks_to_ns(p, max_ticks);
+ + 		*delay_val = delay_ns;
+ + 	} else if (cfgmask == CONFIG_TICKS) {
+ + 		*delay_val = 0x3ff * ehrpwm->prescale_val;
+ + 	} else {
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_db_get_max_delay);
+ + 
+ + int ehrpwm_db_get_delay(struct pwm_device *p, unsigned char edge,
+ + 	enum config_mask cfgmask, unsigned long *delay_val)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 	unsigned long delay_ns;
+ + 	unsigned long delay_ticks;
+ + 	unsigned char offset;
+ + 
+ + 	if (!ehrpwm)
+ + 		return -EINVAL;
+ + 
+ + 	if (edge == RISING_EDGE_DELAY)
+ + 		offset = DBRED;
+ + 	else if (edge == FALLING_EDGE_DELAY)
+ + 		offset = DBFED;
+ + 	else
+ + 		return -EINVAL;
+ + 
+ + 	delay_ticks = ehrpwm_read(ehrpwm, offset);
+ + 	/* Only least 10 bits are required */
+ + 	delay_ticks = delay_ticks & 0x3ff;
+ + 	if (cfgmask == CONFIG_TICKS) {
+ + 		*delay_val = delay_ticks * ehrpwm->prescale_val;
+ + 	} else if (cfgmask == CONFIG_NS) {
+ + 		delay_ticks = delay_ticks * ehrpwm->prescale_val;
+ + 		delay_ns = pwm_ticks_to_ns(p, delay_ticks);
+ + 		debug("\n delay ns value is %lu", delay_ns);
+ + 		*delay_val = delay_ns;
+ + 	} else {
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_db_get_delay);
+ + 
+ + int ehrpwm_db_set_delay(struct pwm_device *p, unsigned char edge,
+ + 		enum config_mask cfgmask, unsigned long delay)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 	unsigned long delay_ticks;
+ + 	unsigned char offset = 0;
+ + 
+ + 	if (!ehrpwm)
+ + 		return -EINVAL;
+ + 
+ + 	if (edge == RISING_EDGE_DELAY)
+ + 		offset = DBRED;
+ + 	else if (edge == FALLING_EDGE_DELAY)
+ + 		offset = DBFED;
+ + 	else
+ + 		return -EINVAL;
+ + 
+ + 	if (cfgmask == CONFIG_TICKS) {
+ + 		delay = delay / ehrpwm->prescale_val;
+ + 		if (delay > 0x3ff)
+ + 			return -EINVAL;
+ + 		ehrpwm_write(ehrpwm, offset, delay);
+ + 	} else if (cfgmask == CONFIG_NS) {
+ + 		delay_ticks = pwm_ns_to_ticks(p, delay);
+ + 		delay_ticks = delay_ticks / ehrpwm->prescale_val;
+ + 		if (delay_ticks > 0x3ff) {
+ + 			ehrpwm_db_get_max_delay(p, CONFIG_NS, &delay_ticks);
+ + 			dev_dbg(p->dev, "%s: Expected delay cannot be"
+ + 			" attained setting the maximum possible delay of"
+ + 			" %lu ns", __func__, delay_ticks);
+ + 			delay_ticks = 0x3ff;
+ + 		}
+ + 		debug("\n delay ticks is %lu", delay_ticks);
+ + 		ehrpwm_write(ehrpwm, offset, delay_ticks);
+ + 	} else {
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_db_set_delay);
+ + 
+ + /* Dead Band Configuration functions */
+ + int ehrpwm_db_set_mode(struct pwm_device *p, unsigned char inmode,
+ + 		unsigned char polsel, unsigned char outmode)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 
+ + 	if (inmode > 0x3 || polsel > 0x3 || outmode > 0x3)
+ + 		return -EINVAL;
+ + 
+ + 	ehrpwm_reg_config(ehrpwm, DBCTL, inmode << DBCTL_INMODE_POS,
+ + 		       DBCTL_INMODE_MASK);
+ + 	ehrpwm_reg_config(ehrpwm, DBCTL, polsel << DBCTL_POLSEL_POS,
+ + 		       DBCTL_PLSEL_MASK);
+ + 	ehrpwm_reg_config(ehrpwm, DBCTL, outmode, DBCTL_OUTMODE_MASK);
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_db_set_mode);
+ + 
+ + /* PWM chopper Configuration functions */
+ + int ehrpwm_pc_configure(struct pwm_device *p, unsigned char chpduty,
+ + 		unsigned char chpfreq, unsigned char oshtwidth)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 
+ + 	if (chpduty > 0x7 || chpfreq > 0x7 || oshtwidth > 0xf)
+ + 		return -EINVAL;
+ + 
+ + 	ehrpwm_reg_config(ehrpwm, PCCTL, chpduty << PCCTL_CHPDUTY_POS,
+ + 		       PCCTL_CHPDUTY_MASK);
+ + 	ehrpwm_reg_config(ehrpwm, PCCTL, chpfreq << PCCTL_CHPFRQ_POS,
+ + 		       PCCTL_CHPFREQ_MASK);
+ + 	ehrpwm_reg_config(ehrpwm, PCCTL, oshtwidth << PCCTL_OSTWID_POS,
+ + 		       PCCTL_OSHTWTH_MASK);
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_pc_configure);
+ + 
+ + int ehrpwm_pc_en_dis(struct pwm_device *p, unsigned char chpen)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 
+ + 	if (chpen > 1)
+ + 		return -EINVAL;
+ + 
+ + 	ehrpwm_reg_config(ehrpwm, PCCTL, chpen, BIT(0));
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_pc_en_dis);
+ + 
+ + /* Trip Zone configuration functions */
+ + int ehrpwm_tz_sel_event(struct pwm_device *p, unsigned char input,
+ + 	       enum tz_event evt)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 
+ + 	unsigned short val = 0;
+ + 	unsigned short mask;
+ + 	unsigned short pos;
+ + 
+ + 	if (evt > 4 || input > 7)
+ + 		return -EINVAL;
+ + 
+ + 	switch (evt) {
+ + 	case TZ_ONE_SHOT_EVENT:
+ + 		pos = input + 8;
+ + 		mask = BIT((pos)) | BIT(input);
+ + 		ehrpwm_reg_config(ehrpwm, TZSEL, 1 << pos, mask);
+ + 		break;
+ + 
+ + 	case TZ_CYCLE_BY_CYCLE:
+ + 		pos = input;
+ + 		mask = BIT(pos) | BIT((pos + 8));
+ + 		ehrpwm_reg_config(ehrpwm, TZSEL, 1 << pos, mask);
+ + 		break;
+ + 
+ + 	case TZ_OSHT_CBC:
+ + 	case TZ_DIS_EVT:
+ + 		if (evt == TZ_OSHT_CBC)
+ + 			val = 1;
+ + 		else
+ + 			val = 0;
+ + 
+ + 		pos = input + 8;
+ + 		mask = BIT((pos));
+ + 		ehrpwm_reg_config(ehrpwm, TZSEL, val << pos, mask);
+ + 		pos = input;
+ + 		mask = BIT((pos));
+ + 		ehrpwm_reg_config(ehrpwm, TZSEL, val << pos, mask);
+ + 		break;
+ + 
+ + 	default:
+ + 		dev_dbg(p->dev, "%s: Invalid command", __func__);
+ + 		return -EINVAL;
+ + 	}
+ + 	debug("\n TZ_sel val is %0x", ehrpwm_read(ehrpwm, TZSEL));
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_tz_sel_event);
+ + 
+ + int ehrpwm_tz_set_action(struct pwm_device *p, unsigned char ch,
+ + 	unsigned char act)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 
+ + 	if (act > 0x3 || ch > 1)
+ + 		return -EINVAL;
+ + 
+ + 	if (ch == 0)
+ + 		ehrpwm_reg_config(ehrpwm, TZCTL, act, TZCTL_ACTA_MASK);
+ + 	else
+ + 		ehrpwm_reg_config(ehrpwm, TZCTL, act << TZCTL_ACTB_POS,
+ + 			       TZCTL_ACTB_MASK);
+ + 
+ + 	debug("\n TZCTL reg val is %0x", ehrpwm_read(ehrpwm, TZCTL));
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_tz_set_action);
+ + 
+ + int ehrpwm_tz_set_int_en_dis(struct pwm_device *p, enum tz_event event,
+ + 		unsigned char int_en_dis)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 
+ + 	if (event == TZ_ONE_SHOT_EVENT)
+ + 		ehrpwm_reg_config(ehrpwm, TZEINT, int_en_dis <<
+ + 			       TZEINT_OSHTEVT_POS, BIT(2));
+ + 	else if (event == TZ_CYCLE_BY_CYCLE)
+ + 		ehrpwm_reg_config(ehrpwm, TZEINT, int_en_dis <<
+ + 			       TZEINT_CBCEVT_POS, BIT(1));
+ + 	else
+ + 		return -EINVAL;
+ + 
+ + 	debug("\n TZEINT reg val is %0x", ehrpwm_read(ehrpwm, TZEINT));
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_tz_set_int_en_dis);
+ + 
+ + int ehrpwm_tz_force_evt(struct pwm_device *p, enum tz_event event)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 
+ + 	if (event == TZ_ONE_SHOT_EVENT)
+ + 		ehrpwm_write(ehrpwm, TZFRC, 0x4);
+ + 	else if (event == TZ_CYCLE_BY_CYCLE)
+ + 		ehrpwm_write(ehrpwm, TZFRC, 0x2);
+ + 	else
+ + 		return -EINVAL;
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_tz_force_evt);
+ + 
+ + inline int ehrpwm_tz_read_status(struct pwm_device *p, unsigned short *status)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 
+ + 	*status = ehrpwm_read(ehrpwm, TZFLG);
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_tz_read_status);
+ + 
+ + inline int ehrpwm_tz_clr_evt_status(struct pwm_device *p)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 	unsigned short ret;
+ + 
+ + 	ret = ehrpwm_read(ehrpwm, TZFLG);
+ + 	ehrpwm_write(ehrpwm, TZCLR, ret & ~0x1);
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_tz_clr_evt_status);
+ + 
+ + inline int ehrpwm_tz_clr_int_status(struct pwm_device *p)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 
+ + 	ehrpwm_write(ehrpwm, TZCLR, 0x1);
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_tz_clr_int_status);
+ + 
+ + /* Event Trigger Configuration functions */
+ + int ehrpwm_et_set_sel_evt(struct pwm_device *p, unsigned char evt,
+ + 		unsigned char prd)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 
+ + 	if (evt > 0x7 || prd > 0x3)
+ + 		return -EINVAL;
+ + 
+ + 	ehrpwm_reg_config(ehrpwm, ETSEL, evt, ETSEL_INTSEL_MASK);
+ + 	ehrpwm_reg_config(ehrpwm, ETPS, prd, ETPS_INTPRD_MASK);
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_et_set_sel_evt);
+ + 
+ + inline int ehrpwm_et_int_en_dis(struct pwm_device *p, unsigned char en_dis)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 
+ + 	ehrpwm_reg_config(ehrpwm, ETSEL, en_dis << ETSEL_EN_INT_EN_POS, BIT(3));
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_et_int_en_dis);
+ + 
+ + inline int ehrpwm_et_read_evt_cnt(struct pwm_device *p,
+ + 	unsigned long *evtcnt)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 
+ + 	*evtcnt = ehrpwm_read(ehrpwm, ETPS) & ETPS_INTCNT_MASK;
+ + 	*evtcnt >>= 0x2;
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_et_read_evt_cnt);
+ + 
+ + inline int ehrpwm_et_read_int_status(struct pwm_device *p,
+ + 	unsigned long *status)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 
+ + 	*status = ehrpwm_read(ehrpwm, ETFLG) & BIT(0);
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_et_read_int_status);
+ + 
+ + inline int ehrpwm_et_frc_int(struct pwm_device *p)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 
+ + 	ehrpwm_write(ehrpwm, ETFRC, ENABLE);
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_et_frc_int);
+ + 
+ + inline int ehrpwm_et_clr_int(struct pwm_device *p)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 
+ + 	ehrpwm_write(ehrpwm, ETCLR, ENABLE);
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_et_clr_int);
+ + 
+ + /* High Resolution Module configuration */
+ + inline int ehrpwm_hr_set_phase(struct pwm_device *p, unsigned char val)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 
+ + 	ehrpwm_write(ehrpwm, TBPHSHR, val << 8);
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_hr_set_phase);
+ + 
+ + inline int ehrpwm_hr_set_cmpval(struct pwm_device *p, unsigned char val)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 
+ + 	ehrpwm_write(ehrpwm, CMPAHR, val << 8);
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_hr_set_cmpval);
+ + 
+ + int ehrpwm_hr_config(struct pwm_device *p, unsigned char loadmode,
+ + 		unsigned char ctlmode, unsigned char edgemode)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 
+ + 	if (loadmode > 1 || ctlmode > 1 || edgemode > 3)
+ + 		return -EINVAL;
+ + 
+ + 	if (ehrpwm->version == PWM_VERSION_1) {
+ + 		ehrpwm_reg_config(ehrpwm, AM335X_HRCNFG,
+ + 				loadmode << HRCNFG_LDMD_POS, BIT(3));
+ + 		ehrpwm_reg_config(ehrpwm, AM335X_HRCNFG,
+ + 				ctlmode << HRCNFG_CTLMD_POS, BIT(2));
+ + 		ehrpwm_reg_config(ehrpwm, AM335X_HRCNFG,
+ + 				edgemode, HRCNFG_EDGEMD_MASK);
+ + 	} else {
+ + 		ehrpwm_reg_config(ehrpwm, HRCNFG,
+ + 				loadmode << HRCNFG_LDMD_POS, BIT(3));
+ + 		ehrpwm_reg_config(ehrpwm, HRCNFG,
+ + 				ctlmode << HRCNFG_CTLMD_POS, BIT(2));
+ + 		ehrpwm_reg_config(ehrpwm, HRCNFG,
+ + 				edgemode, HRCNFG_EDGEMD_MASK);
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_hr_config);
+ + 
+ + inline int ehrpwm_reg_read(struct pwm_device *p, unsigned int reg,
+ + 	       unsigned short *val)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 
+ + 	if (!(ehrpwm->version == PWM_VERSION_1)) {
+ + 		if (reg > HRCNFG)
+ + 			return -EINVAL;
+ + 	}
+ + 
+ + 	*val = ehrpwm_read(ehrpwm, reg);
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_reg_read);
+ + 
+ + inline int ehrpwm_reg_write(struct pwm_device *p, unsigned int reg,
+ + 	       unsigned short val)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 
+ + 	if (!(ehrpwm->version == PWM_VERSION_1)) {
+ + 		if (reg > HRCNFG)
+ + 			return -EINVAL;
+ + 	}
+ + 
+ + 	ehrpwm_write(ehrpwm, reg, val);
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_reg_write);
+ + 
+ + 
+ + static void ehrpwm_channel_output_low(struct pwm_device *p)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 	int chan = p - &ehrpwm->pwm[0];
+ + 
+ + 	ehrpwm_aq_set_csfrc_load_mode(p, AQSFRC_RLDCSF_IMDT);
+ + 	ehrpwm_aq_continuous_frc(p, chan, AQCSFRC_CSF_FRCLOW);
+ + }
+ + 
+ + static void ehrpwm_channel_output_enable(struct pwm_device *p, int channel)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 
+ + 	pm_runtime_get_sync(ehrpwm->dev);
+ + 	ehrpwm_aq_set_csfrc_load_mode(p, AQSFRC_RLDCSF_ZRO);
+ + 	ehrpwm_aq_continuous_frc(p, channel, AQCSFRC_CSF_FRCDIS);
+ + 	pm_runtime_put_sync(ehrpwm->dev);
+ + }
+ + 
+ + static int ehrpwm_pwm_set_pol(struct pwm_device *p)
+ + {
+ + 	unsigned int act_ctrl_reg;
+ + 	unsigned int cmp_reg;
+ + 	unsigned int ctreqcmp_mask;
+ + 	unsigned int ctreqcmp;
+ + 	unsigned short val;
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 	int chan;
+ + 
+ + 	chan = p - &ehrpwm->pwm[0];
+ + 	if (!chan) {
+ + 		act_ctrl_reg = AQCTLA;
+ + 		cmp_reg = CMPA;
+ + 		ctreqcmp_mask = ACTCTL_CAU_MASK;
+ + 		ctreqcmp = 4;
+ + 	} else {
+ + 		act_ctrl_reg = AQCTLB;
+ + 		cmp_reg = CMPB;
+ + 		ctreqcmp_mask = ACTCTL_CBU_MASK;
+ + 		ctreqcmp = 8;
+ + 	}
+ + 
+ + 
+ + 	pm_runtime_get_sync(ehrpwm->dev);
+ + 	val = ((p->active_high ? ACTCTL_CTREQCMP_HIGH : ACTCTL_CTREQCMP_LOW)
+ + 		 << ctreqcmp) | (p->active_high ? ACTCTL_CTREQZRO_LOW :
+ + 			ACTCTL_CTREQZRO_HIGH);
+ + 	ehrpwm_write(ehrpwm, act_ctrl_reg, val);
+ + 	pm_runtime_put_sync(ehrpwm->dev);
+ + 	return 0;
+ + }
+ + 
+ + static int ehrpwm_pwm_start(struct pwm_device *p)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 	unsigned short val;
+ + 	int chan;
+ + 
+ + 	/* Trying to start a running PWM, not allowed */
+ + 	if (pwm_is_running(p))
+ + 		return -EPERM;
+ + 
+ + 	/* For PWM clock should be enabled on start */
+ + 	pm_runtime_get_sync(ehrpwm->dev);
+ + 
+ + 	ehrpwm_pwm_set_pol(p);
+ + 	chan = p - &ehrpwm->pwm[0];
+ + 	val = ehrpwm_read(ehrpwm, TBCTL);
+ + 	val = (val & ~TBCTL_CTRMODE_MASK) | (TBCTL_CTRMOD_CTRUP |
+ + 		 TBCTL_FREERUN_FREE << 14);
+ + 	ehrpwm_write(ehrpwm, TBCTL, val);
+ + 
+ + 	/* Enable PWM channel output */
+ + 	ehrpwm_channel_output_enable(p, chan);
+ + 
+ + 	set_bit(FLAG_RUNNING, &p->flags);
+ + 	return 0;
+ + }
+ + 
+ + /*
+ +  * Stop function is implemented using the Trip Zone module. Action for the
+ +  * corresponding channel is set to low and the one shot software force
+ +  * event is triggered.
+ +  */
+ + static int ehrpwm_pwm_stop(struct pwm_device *p)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 
+ + 	/* Trying to stop a non-running PWM, not allowed */
+ + 	if (!pwm_is_running(p))
+ + 		return -EPERM;
+ + 
+ + 	/* Put PWM output to low */
+ + 	ehrpwm_channel_output_low(p);
+ + 
+ + 	/* For PWM clock should be disabled on stop */
+ + 	pm_runtime_put_sync(ehrpwm->dev);
+ + 	clear_bit(FLAG_RUNNING, &p->flags);
+ + 	return 0;
+ + }
+ + 
+ + /*
+ +  * Prescalar is used when the period value exceeds the maximum value
+ +  * of the 16 bit period register. We always look for the minimum prescalar
+ +  * value as it would result in wide range of duty control
+ +  */
+ + static char get_divider_val(unsigned int desired_ps_val, unsigned int
+ + *ps_div_val, unsigned int *tb_div_val)
+ + {
+ + 	char i = 0;
+ + 	char j = 0;
+ + 
+ + 	for (i = 0; i <= 7; i++) {
+ + 		for (j = 0; j <= 7; j++) {
+ + 			if (((1 << i) * (j ? (j * 2) : 1)) >= desired_ps_val) {
+ + 				*ps_div_val = (1 << i) * (j ? (j * 2) : 1);
+ + 				*tb_div_val = (i << 10) | (j << 7) ;
+ + 				return 0;
+ + 			}
+ + 		}
+ + 	}
+ + 
+ + 	return -1;
+ + }
+ + 
+ + static int ehrpwm_pwm_set_prd(struct pwm_device *p)
+ + {
+ + 	unsigned int ps_div_val = 1;
+ + 	unsigned int tb_div_val = 0;
+ + 	char ret;
+ + 	unsigned short val;
+ + 	unsigned short period_ticks;
+ + 	struct pwm_device *temp;
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 	int chan = 0;
+ + 	/*
+ + 	 * Since the device has a singe period register, copy the period
+ + 	 * value to the other channel also.
+ + 	 */
+ + 	chan = p - &ehrpwm->pwm[0];
+ + 	temp = &ehrpwm->pwm[!chan];
+ + 	temp->period_ticks = p->period_ticks;
+ + 	temp->period_ns = p->period_ns;
+ + 	debug("\n period_ticks is %lu", p->period_ticks);
+ + 
+ + 	if (p->period_ticks > 65535) {
+ + 		ret = get_divider_val(p->period_ticks / 65535 + 1, &ps_div_val,
+ + 				&tb_div_val);
+ + 		if (ret) {
+ + 			dev_err(p->dev, "failed to get the divider value");
+ + 			return -EINVAL;
+ + 		}
+ + 	}
+ + 
+ + 	pm_runtime_get_sync(ehrpwm->dev);
+ + 	val = ehrpwm_read(ehrpwm, TBCTL);
+ + 	val = (val & ~TBCTL_CLKDIV_MASK & ~TBCTL_HSPCLKDIV_MASK) | tb_div_val;
+ + 	ehrpwm_write(ehrpwm, TBCTL, val);
+ + 	period_ticks = p->period_ticks / ps_div_val;
+ + 
+ + 	if (period_ticks <= 1) {
+ + 		dev_err(p->dev, "Required period/frequency cannot be obtained");
+ + 		pm_runtime_put_sync(ehrpwm->dev);
+ + 		return -EINVAL;
+ + 	}
+ + 	/*
+ + 	 * Program the period register with 1 less than the actual value since
+ + 	 * the module generates waveform with period always 1 greater
+ + 	 * the programmed value.
+ + 	 */
+ + 	ehrpwm_write(ehrpwm, TBPRD, (unsigned short)(period_ticks - 1));
+ + 	pm_runtime_put_sync(ehrpwm->dev);
+ + 	debug("\n period_ticks is %d", period_ticks);
+ + 	ehrpwm->prescale_val = ps_div_val;
+ + 	debug("\n Prescaler value is %d", ehrpwm->prescale_val);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static int ehrpwm_hr_duty_config(struct pwm_device *p)
+ + {
+ + 	unsigned char no_of_mepsteps;
+ + 	unsigned short cmphr_val;
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 
+ + 	if (!p->tick_hz) {
+ + 		dev_dbg(p->dev, "%s: p->tick_hz is zero\n", __func__);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	/*
+ + 	 * Calculate the no of MEP steps. Assume system clock
+ + 	 * is in the order of MHZ.
+ + 	 */
+ + 	no_of_mepsteps = USEC_PER_SEC / ((p->tick_hz / USEC_PER_SEC) * 63);
+ + 
+ + 	pm_runtime_get_sync(ehrpwm->dev);
+ + 	/* Calculate the CMPHR Value */
+ + 	cmphr_val = p->tick_hz / USEC_PER_SEC;
+ + 	cmphr_val = (p->duty_ns * cmphr_val) % MSEC_PER_SEC;
+ + 	cmphr_val = (cmphr_val * no_of_mepsteps) / 1000;
+ + 	cmphr_val = (cmphr_val << 8) + 0x180;
+ + 	ehrpwm_write(ehrpwm, CMPAHR, cmphr_val);
+ + 
+ + 	if (ehrpwm->version == PWM_VERSION_1)
+ + 		ehrpwm_write(ehrpwm, AM335X_HRCNFG, 0x2);
+ + 	else
+ + 		ehrpwm_write(ehrpwm, HRCNFG, 0x2);
+ + 
+ + 	pm_runtime_put_sync(ehrpwm->dev);
+ + 	return 0;
+ + }
+ + 
+ + static int ehrpwm_pwm_set_dty(struct pwm_device *p)
+ + {
+ + 	unsigned short duty_ticks = 0;
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 	int ret = 0;
+ + 	int chan;
+ + 
+ + 	chan = p - &ehrpwm->pwm[0];
+ + 
+ + 	if (!ehrpwm->prescale_val) {
+ + 		dev_dbg(p->dev, "%s: prescale_val is zero\n", __func__);
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	duty_ticks = p->duty_ticks / ehrpwm->prescale_val;
+ + 	debug("\n Prescaler value is %d", ehrpwm->prescale_val);
+ + 	debug("\n duty ticks is %d", duty_ticks);
+ + 	pm_runtime_get_sync(ehrpwm->dev);
+ + 	/* High resolution module */
+ + 	if (chan && ehrpwm->prescale_val <= 1) {
+ + 		ret = ehrpwm_hr_duty_config(p);
+ + 		if (ehrpwm->version == PWM_VERSION_1)
+ + 			ehrpwm_write(ehrpwm, AM335X_HRCNFG, 0x2);
+ + 		else
+ + 			ehrpwm_write(ehrpwm, HRCNFG, 0x2);
+ + 	}
+ + 
+ + 	ehrpwm_write(ehrpwm, (chan ? CMPB : CMPA), duty_ticks);
+ + 	pm_runtime_put_sync(ehrpwm->dev);
+ + 	return ret;
+ + }
+ + 
+ + int ehrpwm_et_cb_register(struct pwm_device *p, void *data,
+ + 	p_fcallback cb)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 	unsigned long flags;
+ + 
+ + 	spin_lock_irqsave(&ehrpwm->lock, flags);
+ + 	ehrpwm->st_etint.data = data;
+ + 	ehrpwm->st_etint.pcallback = cb;
+ + 	spin_unlock_irqrestore(&ehrpwm->lock, flags);
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_et_cb_register);
+ + 
+ + int ehrpwm_tz_cb_register(struct pwm_device *p, void *data,
+ + 	p_fcallback cb)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 	unsigned long flags;
+ + 
+ + 	spin_lock_irqsave(&ehrpwm->lock, flags);
+ + 	ehrpwm->st_tzint.data = data;
+ + 	ehrpwm->st_tzint.pcallback = cb;
+ + 	spin_unlock_irqrestore(&ehrpwm->lock, flags);
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_tz_cb_register);
+ + 
+ + static int ehrpwm_pwm_suspend_cb(struct ehrpwm_pwm *ehrpwm, void *data)
+ + {
+ + 	struct ehrpwm_suspend_params *pwm_suspend_params =
+ + 				(struct ehrpwm_suspend_params *)data;
+ + 
+ + 	if (pwm_suspend_params->act_delay++ >= pwm_suspend_params->
+ + 			req_delay_cycles) {
+ + 		pwm_start(pwm_suspend_params->pch);
+ + 		ehrpwm_et_cb_register(pwm_suspend_params->pch, NULL, NULL);
+ + 		ehrpwm_et_int_en_dis(pwm_suspend_params->pch, DISABLE);
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ + 
+ + int ehrpwm_pwm_suspend(struct pwm_device *p, enum config_mask config_mask,
+ + 	       unsigned long val)
+ + {
+ + 	unsigned long long req_cycles = 0;
+ + 
+ + 	if (!p->period_ns)
+ + 		return -EINVAL;
+ + 
+ + 	ehrpwm_pwm_stop(p);
+ + 	/* Calculate the delay in terms of cycles */
+ + 	if (config_mask == CONFIG_NS)
+ + 		req_cycles =  val / p->period_ns;
+ + 	else if (config_mask == CONFIG_TICKS)
+ + 		req_cycles = val;
+ + 	else
+ + 		return -EINVAL;
+ + 
+ + 	/* Configute the event interrupt */
+ + 	ehrpwm_et_set_sel_evt(p, 0x2, 0x1);
+ + 	ehrpwm_suspend_params.pch = p;
+ + 	ehrpwm_suspend_params.req_delay_cycles = req_cycles;
+ + 	ehrpwm_suspend_params.act_delay = 0;
+ + 	ehrpwm_et_cb_register(p, &ehrpwm_suspend_params,
+ + 		ehrpwm_pwm_suspend_cb);
+ + 	ehrpwm_et_int_en_dis(p, ENABLE);
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(ehrpwm_pwm_suspend);
+ + 
+ + static irqreturn_t ehrpwm_trip_zone_irq_handler(int irq, void *data)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = (struct ehrpwm_pwm *)data;
+ + 	unsigned long flags;
+ + 	int ret = 0;
+ + 
+ + 	spin_lock_irqsave(&ehrpwm->lock, flags);
+ + 	 ret = ehrpwm_read(ehrpwm, TZFLG);
+ + 	if (!(ret & 0x1))
+ + 		return IRQ_NONE;
+ + 
+ + 	if (ehrpwm->st_tzint.pcallback)
+ + 		ret = ehrpwm->st_tzint.pcallback(ehrpwm, ehrpwm->st_tzint.data);
+ + 
+ + 	ret = ehrpwm_read(ehrpwm, TZFLG);
+ + 	ehrpwm_write(ehrpwm, TZCLR, ret & ~0x1);
+ + 	ehrpwm_write(ehrpwm, TZCLR, 0x1);
+ + 	spin_unlock_irqrestore(&ehrpwm->lock, flags);
+ + 
+ + 	return IRQ_HANDLED;
+ + }
+ + 
+ + static irqreturn_t ehrpwm_event_irq_handler(int irq, void *data)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = (struct ehrpwm_pwm *)data;
+ + 	unsigned long flags;
+ + 
+ + 	spin_lock_irqsave(&ehrpwm->lock, flags);
+ + 
+ + 	if (ehrpwm->st_etint.pcallback)
+ + 		ehrpwm->st_etint.pcallback(ehrpwm, ehrpwm->st_etint.data);
+ + 
+ + 	ehrpwm_write(ehrpwm, ETCLR, 0x1);
+ + 
+ + 	spin_unlock_irqrestore(&ehrpwm->lock, flags);
+ + 
+ + 	return IRQ_HANDLED;
+ + }
+ + 
+ + static int ehrpwm_pwm_config(struct pwm_device *p,
+ + 	struct pwm_config *c)
+ + {
+ + 	int ret = 0;
+ + 
+ + 	switch (c->config_mask) {
+ + 	case BIT(PWM_CONFIG_PERIOD_TICKS):
+ + 		if (p->max_period_ticks &&
+ + 				(p->max_period_ticks >= c->period_ticks))
+ + 			p->period_ticks = p->max_period_ticks;
+ + 		else
+ + 			p->period_ticks = c->period_ticks;
+ + 
+ + 		ret = ehrpwm_pwm_set_prd(p);
+ + 		break;
+ + 
+ + 	case BIT(PWM_CONFIG_DUTY_TICKS):
+ + 		p->duty_ticks = c->duty_ticks;
+ + 		ret = ehrpwm_pwm_set_dty(p);
+ + 		break;
+ + 
+ + 	case BIT(PWM_CONFIG_POLARITY):
+ + 		p->active_high = c->polarity;
+ + 		ret = ehrpwm_pwm_set_pol(p);
+ + 		break;
+ + 
+ + 	case BIT(PWM_CONFIG_START):
+ + 		 ret = ehrpwm_pwm_start(p);
+ + 		 break;
+ + 
+ + 	case BIT(PWM_CONFIG_STOP):
+ + 		ret = ehrpwm_pwm_stop(p);
+ + 		break;
+ + 
+ + 	default:
+ + 		dev_dbg(p->dev, "%s: Invalid configuration\n", __func__);
+ + 		ret = -EINVAL;
+ + 	}
+ + 
+ + 	return ret;
+ + }
+ + 
+ + static int ehrpwm_pwm_request(struct pwm_device *p)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 	int chan;
+ + 
+ + 	chan = p - &ehrpwm->pwm[0];
+ + 
+ + 	p->tick_hz = clk_get_rate(ehrpwm->clk);
+ + 	debug("\n The clk freq is %lu", p->tick_hz);
+ + 	/* Put PWM output to low */
+ + 	pm_runtime_get_sync(ehrpwm->dev);
+ + 	ehrpwm_channel_output_low(p);
+ + 	pm_runtime_put_sync(ehrpwm->dev);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static int ehrpwm_freq_transition_cb(struct pwm_device *p)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
+ + 	unsigned long duty_ns;
+ + 
+ + 	p->tick_hz = clk_get_rate(ehrpwm->clk);
+ + 	duty_ns = p->duty_ns;
+ + 	if (pwm_is_running(p)) {
+ + 		pwm_stop(p);
+ + 		pwm_set_duty_ns(p, 0);
+ + 		pwm_set_period_ns(p, p->period_ns);
+ + 		pwm_set_duty_ns(p, duty_ns);
+ + 		pwm_start(p);
+ + 	} else {
+ + 		pwm_set_duty_ns(p, 0);
+ + 		pwm_set_period_ns(p, p->period_ns);
+ + 		pwm_set_duty_ns(p, duty_ns);
+ + 	}
+ + 		return 0;
+ + }
+ + 
+ + static int ehrpwm_probe(struct platform_device *pdev)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = NULL;
+ + 	struct resource *r;
+ + 	int ret = 0;
+ + 	int chan = 0;
+ + 	struct pwmss_platform_data *pdata = (&pdev->dev)->platform_data;
+ + 	int ch_mask = 0;
+ + 	int val;
+ + 	char con_id[PWM_CON_ID_STRING_LENGTH] = "epwmss";
+ + 
+ + 	ehrpwm = kzalloc(sizeof(*ehrpwm), GFP_KERNEL);
+ + 	if (!ehrpwm) {
+ + 		dev_err(&pdev->dev, "failed to allocate memory\n");
+ + 		ret = -ENOMEM;
+ + 		goto err_mem_failure;
+ + 	}
+ + 
+ + 	ehrpwm->version = pdata->version;
+ + 
+ + 	if (ehrpwm->version == PWM_VERSION_1) {
+ + 		sprintf(con_id, "%s%d_%s", con_id, pdev->id, "fck");
+ + 		ehrpwm->clk = clk_get(&pdev->dev, con_id);
+ + 	} else
+ + 		ehrpwm->clk = clk_get(&pdev->dev, "ehrpwm");
+ + 
+ + 	pm_runtime_enable(&pdev->dev);
+ + 	ehrpwm->dev = &pdev->dev;
+ + 	if (IS_ERR(ehrpwm->clk)) {
+ + 		ret = PTR_ERR(ehrpwm->clk);
+ + 		goto err_clock_failure;
+ + 	}
+ + 
+ + 	if (ehrpwm->version == PWM_VERSION_1) {
+ + 		r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ + 
+ + 		if (!r) {
+ + 			dev_err(&pdev->dev, "no memory resource defined\n");
+ + 			ret = -ENOMEM;
+ + 			goto err_resource_mem_failure;
+ + 		}
+ + 
+ + 		ehrpwm->config_mem_base = ioremap(r->start, resource_size(r));
+ + 
+ + 		if (!ehrpwm->config_mem_base) {
+ + 
+ + 			dev_err(&pdev->dev, "failed to ioremap() registers\n");
+ + 			ret = -ENODEV;
+ + 			goto err_free_mem_config;
+ + 		}
+ + 
+ + 		pm_runtime_get_sync(ehrpwm->dev);
+ + 		val = readw(ehrpwm->config_mem_base + PWMSS_CLKCONFIG);
+ + 		val |= BIT(EPWM_CLK_EN);
+ + 		writew(val, ehrpwm->config_mem_base + PWMSS_CLKCONFIG);
+ + 		pm_runtime_put_sync(ehrpwm->dev);
+ + 	} else
+ + 		ch_mask = pdata->channel_mask;
+ + 
+ + 	spin_lock_init(&ehrpwm->lock);
+ + 	ehrpwm->ops.config = ehrpwm_pwm_config;
+ + 	ehrpwm->ops.request = ehrpwm_pwm_request;
+ + 	ehrpwm->ops.freq_transition_notifier_cb = ehrpwm_freq_transition_cb;
+ + 	ehrpwm->prescale_val = 1;
+ + 
+ + 	if (ehrpwm->version == PWM_VERSION_1)
+ + 		r = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ + 	else
+ + 		r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ + 
+ + 	if (!r) {
+ + 		dev_err(&pdev->dev, "no memory resource defined\n");
+ + 		ret = -ENODEV;
+ + 		goto err_resource_mem2_failiure;
+ + 	}
+ + 
+ + 	r = request_mem_region(r->start, resource_size(r), pdev->name);
+ + 	if (!r) {
+ + 		dev_err(&pdev->dev, "failed to request memory resource\n");
+ + 		ret = -EBUSY;
+ + 		goto err_request_mem2_failure;
+ + 	}
+ + 
+ + 	ehrpwm->mmio_base = ioremap(r->start, resource_size(r));
+ + 	if (!ehrpwm->mmio_base) {
+ + 		dev_err(&pdev->dev, "failed to ioremap() registers\n");
+ + 		ret = -ENODEV;
+ + 		goto err_free_mem2;
+ + 	}
+ + 
+ + 	ehrpwm->irq[0] = platform_get_irq(pdev, 0);
+ + 	if (ehrpwm->irq[0] == -ENXIO) {
+ + 		dev_err(&pdev->dev, "No IRQ resource\n");
+ + 		ret = -ENXIO;
+ + 		goto err_free_io;
+ + 	}
+ + 
+ + 	ret = request_irq(ehrpwm->irq[0], ehrpwm_trip_zone_irq_handler,
+ + 				0, "ehrpwmTZ", ehrpwm);
+ + 	if (ret)
+ + 		goto err_free_io;
+ + 
+ + 	ehrpwm->irq[1] = platform_get_irq(pdev, 1);
+ + 	if (ehrpwm->irq[1] == -ENXIO) {
+ + 		dev_err(&pdev->dev, "No IRQ resource\n");
+ + 		ret = -ENXIO;
+ + 		goto err_request_irq;
+ + 	}
+ + 
+ + 	ret = request_irq(ehrpwm->irq[1], ehrpwm_event_irq_handler,
+ + 				0, "ehrpwm_evt", ehrpwm);
+ + 	if (ret)
+ + 		goto err_request_irq;
+ + 
+ + 	for (chan = 0; chan < NCHAN; chan++) {
+ + 		ehrpwm->pwm[chan].ops = &ehrpwm->ops;
+ + 		pwm_set_drvdata(&ehrpwm->pwm[chan], ehrpwm);
+ + 		ehrpwm->pwm[chan].tick_hz = clk_get_rate(ehrpwm->clk);
+ + 
+ + 		if (pdata->chan_attrib[chan].max_freq) {
+ + 			int period_ns = NSEC_PER_SEC
+ + 				/ pdata->chan_attrib[chan].max_freq;
+ + 
+ + 			ehrpwm->pwm[chan].max_period_ticks =
+ + 				pwm_ns_to_ticks(&ehrpwm->pwm[chan], period_ns);
+ + 		}
+ + 
+ + 		if (!(ehrpwm->version == PWM_VERSION_1)) {
+ + 			if (!(ch_mask & (0x1 << chan)))
+ + 				continue;
+ + 		}
+ + 
+ + 		ret =  pwm_register(&ehrpwm->pwm[chan], &pdev->dev, chan);
+ + 		if (ret)
+ + 			goto err_pwm_register;
+ + 	}
+ + 
+ + 		platform_set_drvdata(pdev, ehrpwm);
+ + 	return 0;
+ + 
+ + err_pwm_register:
+ + 	for (chan = 0; chan < NCHAN; chan++) {
+ + 		if (pwm_is_registered(&ehrpwm->pwm[chan]))
+ + 			pwm_unregister(&ehrpwm->pwm[chan]);
+ + 	}
+ + 
+ + err_request_irq:
+ + 	if (ehrpwm->irq[0] != -ENXIO)
+ + 		free_irq(ehrpwm->irq[0], ehrpwm);
+ + err_free_io:
+ + 	iounmap(ehrpwm->mmio_base);
+ + err_free_mem2:
+ + 	release_mem_region(r->start, resource_size(r));
+ + err_request_mem2_failure:
+ + err_resource_mem2_failiure:
+ + 	if (ehrpwm->version == PWM_VERSION_1) {
+ + 		iounmap(ehrpwm->config_mem_base);
+ + 		ehrpwm->config_mem_base = NULL;
+ + 	}
+ + err_free_mem_config:
+ + err_resource_mem_failure:
+ + 	clk_put(ehrpwm->clk);
+ + 	pm_runtime_disable(ehrpwm->dev);
+ + err_clock_failure:
+ + 	kfree(ehrpwm);
+ + err_mem_failure:
+ + 	return ret;
+ + }
+ + 
+ + #ifdef CONFIG_PM
+ + 
+ + void ehrpwm_context_save(struct ehrpwm_pwm *ehrpwm,
+ + 		struct ehrpwm_context *ehrpwm_ctx)
+ + {
+ + 	pm_runtime_get_sync(ehrpwm->dev);
+ + 	ehrpwm_ctx->tbctl = ehrpwm_read(ehrpwm, TBCTL);
+ + 	ehrpwm_ctx->tbprd = ehrpwm_read(ehrpwm, TBPRD);
+ + 	if (ehrpwm->version == PWM_VERSION_1)
+ + 		ehrpwm_ctx->hrcfg = ehrpwm_read(ehrpwm, AM335X_HRCNFG);
+ + 	else
+ + 		ehrpwm_ctx->hrcfg = ehrpwm_read(ehrpwm, HRCNFG);
+ + 	ehrpwm_ctx->aqctla = ehrpwm_read(ehrpwm, AQCTLA);
+ + 	ehrpwm_ctx->aqctlb = ehrpwm_read(ehrpwm, AQCTLB);
+ + 	ehrpwm_ctx->aqsfrc = ehrpwm_read(ehrpwm, AQSFRC);
+ + 	ehrpwm_ctx->aqcsfrc = ehrpwm_read(ehrpwm, AQCSFRC);
+ + 	ehrpwm_ctx->cmpa = ehrpwm_read(ehrpwm, CMPA);
+ + 	ehrpwm_ctx->cmpb = ehrpwm_read(ehrpwm, CMPB);
+ + 	pm_runtime_put_sync(ehrpwm->dev);
+ + }
+ + 
+ + void ehrpwm_context_restore(struct ehrpwm_pwm *ehrpwm,
+ + 		struct ehrpwm_context *ehrpwm_ctx)
+ + {
+ + 	ehrpwm_write(ehrpwm, TBCTL, ehrpwm_ctx->tbctl);
+ + 	ehrpwm_write(ehrpwm, TBPRD, ehrpwm_ctx->tbprd);
+ + 	if (ehrpwm->version == PWM_VERSION_1)
+ + 		ehrpwm_write(ehrpwm, AM335X_HRCNFG, ehrpwm_ctx->hrcfg);
+ + 	else
+ + 		ehrpwm_write(ehrpwm, HRCNFG, ehrpwm_ctx->hrcfg);
+ + 	ehrpwm_write(ehrpwm, AQCTLA, ehrpwm_ctx->aqctla);
+ + 	ehrpwm_write(ehrpwm, AQCTLB, ehrpwm_ctx->aqctlb);
+ + 	ehrpwm_write(ehrpwm, AQSFRC, ehrpwm_ctx->aqsfrc);
+ + 	ehrpwm_write(ehrpwm, AQCSFRC, ehrpwm_ctx->aqcsfrc);
+ + 	ehrpwm_write(ehrpwm, CMPA, ehrpwm_ctx->cmpa);
+ + 	ehrpwm_write(ehrpwm, CMPB, ehrpwm_ctx->cmpb);
+ + }
+ + 
+ + static int ehrpwm_suspend(struct platform_device *pdev, pm_message_t state)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = platform_get_drvdata(pdev);
+ + 
+ + 	ehrpwm_context_save(ehrpwm, &ehrpwm->ctx);
+ + 	pm_runtime_put_sync(ehrpwm->dev);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static int ehrpwm_resume(struct platform_device *pdev)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = platform_get_drvdata(pdev);
+ + 
+ + 	pm_runtime_get_sync(ehrpwm->dev);
+ + 	ehrpwm_context_restore(ehrpwm, &ehrpwm->ctx);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + #else
+ + #define ehrpwm_suspend NULL
+ + #define ehrpwm_resume NULL
+ + #endif /* CONFIG_PM */
+ + 
+ + static int __devexit ehrpwm_remove(struct platform_device *pdev)
+ + {
+ + 	struct ehrpwm_pwm *ehrpwm = platform_get_drvdata(pdev);
+ + 	struct resource *r;
+ + 	unsigned char i;
+ + 	int val;
+ + 	struct pwmss_platform_data *pdata;
+ + 
+ + 	if (ehrpwm->version == PWM_VERSION_1) {
+ + 		pdata = (&pdev->dev)->platform_data;
+ + 		pm_runtime_get_sync(ehrpwm->dev);
+ + 		val = readw(ehrpwm->config_mem_base + PWMSS_CLKCONFIG);
+ + 		val &= ~BIT(EPWM_CLK_EN);
+ + 		writew(val, ehrpwm->config_mem_base + PWMSS_CLKCONFIG);
+ + 		pm_runtime_put_sync(ehrpwm->dev);
+ + 		iounmap(ehrpwm->config_mem_base);
+ + 		ehrpwm->config_mem_base = NULL;
+ + 	}
+ + 
+ + 	for (i = 0; i < NCHAN; i++) {
+ + 		if (pwm_is_registered(&ehrpwm->pwm[i]))
+ + 			pwm_unregister(&ehrpwm->pwm[i]);
+ + 	}
+ + 
+ + 	for (i = 0; i < 2; i++)
+ + 		if (ehrpwm->irq[i] != -ENXIO)
+ + 			free_irq(ehrpwm->irq[i], ehrpwm);
+ + 	iounmap(ehrpwm->mmio_base);
+ + 
+ + 	if (ehrpwm->version == PWM_VERSION_1)
+ + 		r = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ + 	else
+ + 		r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ + 
+ + 	release_mem_region(r->start, resource_size(r));
+ + 	platform_set_drvdata(pdev, NULL);
+ + 	clk_put(ehrpwm->clk);
+ + 	pm_runtime_disable(ehrpwm->dev);
+ + 	kfree(ehrpwm);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static struct platform_driver ehrpwm_driver = {
+ + 	.driver	= {
+ + 		.name	= "ehrpwm",
+ + 		.owner	= THIS_MODULE,
+ + 	},
+ + 	.probe		= ehrpwm_probe,
+ + 	.remove		= __devexit_p(ehrpwm_remove),
+ + 	.suspend	= ehrpwm_suspend,
+ + 	.resume		= ehrpwm_resume,
+ + };
+ + 
+ + static int __init ehrpwm_init(void)
+ + {
+ + 	return platform_driver_register(&ehrpwm_driver);
+ + }
+ + module_init(ehrpwm_init);
+ + 
+ + static void __exit ehrpwm_exit(void)
+ + {
+ + 	platform_driver_unregister(&ehrpwm_driver);
+ + }
+ + module_exit(ehrpwm_exit);
+ + 
+ + MODULE_AUTHOR("Texas Instruments");
+ + MODULE_DESCRIPTION("Driver for Davinci eHRPWM peripheral");
+ + MODULE_LICENSE("GPL");
+ + MODULE_ALIAS("platform:ehrpwm");
+ diff -crN linux-3.2.1_o/drivers/pwm/Kconfig linux-3.2.1/drivers/pwm/Kconfig
+ *** linux-3.2.1_o/drivers/pwm/Kconfig	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/drivers/pwm/Kconfig	2014-11-25 13:19:15.811062565 +0900
+ ***************
+ *** 0 ****
+ --- 1,29 ----
+ + #
+ + # PWM infrastructure and devices
+ + #
+ + 
+ + menuconfig GENERIC_PWM
+ + 	tristate "PWM Support"
+ + 	default n
+ + 	help
+ + 	  Enables PWM device support implemented via a generic
+ + 	  framework.  If unsure, say N.
+ + 
+ + config DAVINCI_EHRPWM
+ + 	bool "Davinci eHRPWM support"
+ + 	select HAVE_PWM
+ + 	depends on GENERIC_PWM && (ARCH_DAVINCI_DA850 || SOC_OMAPAM33XX)
+ + 	help
+ + 	  This option enables support for eHRPWM driver. If
+ + 	  unsure, say N.
+ + 
+ + config ECAP_PWM
+ + 	tristate "eCAP PWM support"
+ + 	select HAVE_PWM
+ + 	depends on GENERIC_PWM && (ARCH_DAVINCI_DA850 || SOC_OMAPAM33XX)
+ + 	help
+ + 	  This option enables device driver support for eCAP module found
+ + 	  on DA8xx Processors & AM335x processor. eCAP module is used to
+ + 	  generate wide range of PWM waveforms. Maximum frequency generated
+ + 	  is equal to half the system clock frequency.
+ + 	  Say Y to enable the eCAP support. If unsure, say N.
+ diff -crN linux-3.2.1_o/drivers/pwm/Makefile linux-3.2.1/drivers/pwm/Makefile
+ *** linux-3.2.1_o/drivers/pwm/Makefile	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/drivers/pwm/Makefile	2014-11-25 13:19:15.811062565 +0900
+ ***************
+ *** 0 ****
+ --- 1,8 ----
+ + #
+ + # Makefile for pwm devices
+ + #
+ + obj-$(CONFIG_GENERIC_PWM) := pwm.o
+ + 
+ + obj-$(CONFIG_DAVINCI_EHRPWM)	+= ehrpwm.o
+ + 
+ + obj-$(CONFIG_ECAP_PWM)		+= ecap.o
+ diff -crN linux-3.2.1_o/drivers/pwm/pwm.c linux-3.2.1/drivers/pwm/pwm.c
+ *** linux-3.2.1_o/drivers/pwm/pwm.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/drivers/pwm/pwm.c	2014-11-25 13:19:15.811062565 +0900
+ ***************
+ *** 0 ****
+ --- 1,843 ----
+ + /*
+ +  * PWM API implementation
+ +  *
+ +  * Copyright (C) 2011 Bill Gatliff <bgat@billgatliff.com>
+ +  * Copyright (C) 2011 Arun Murthy <arun.murthy@stericsson.com>
+ +  *
+ +  * This program is free software; you may redistribute and/or modify
+ +  * it under the terms of the GNU General Public License version 2 as
+ +  * published by the Free Software Foundation.
+ +  *
+ +  * This program is distributed in the hope that it will be useful, but
+ +  * WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ +  * General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+ +  * USA
+ +  */
+ + 
+ + #include <linux/module.h>
+ + #include <linux/kernel.h>
+ + #include <linux/init.h>
+ + #include <linux/slab.h>
+ + #include <linux/device.h>
+ + #include <linux/fs.h>
+ + #include <linux/completion.h>
+ + #include <linux/workqueue.h>
+ + #include <linux/list.h>
+ + #include <linux/sched.h>
+ + #include <linux/platform_device.h>
+ + #include <linux/cpufreq.h>
+ + #include <linux/pwm/pwm.h>
+ + 
+ + static const char *REQUEST_SYSFS = "sysfs";
+ + static LIST_HEAD(pwm_device_list);
+ + static DEFINE_MUTEX(device_list_mutex);
+ + static struct class pwm_class;
+ + static struct workqueue_struct *pwm_handler_workqueue;
+ + 
+ + static int pwm_match_name(struct device *dev, void *name)
+ + {
+ + 	return !strcmp(name, dev_name(dev));
+ + }
+ + 
+ + static struct pwm_device *__pwm_request(struct pwm_device *p, const char *label)
+ + {
+ + 	int ret;
+ + 
+ + 	ret = test_and_set_bit(FLAG_REQUESTED, &p->flags);
+ + 	if (ret) {
+ + 		p = ERR_PTR(-EBUSY);
+ + 		goto done;
+ + 	}
+ + 
+ + 	p->label = label;
+ + 	p->pid = current->pid;
+ + 
+ + 	if (p->ops->request) {
+ + 		ret = p->ops->request(p);
+ + 		if (ret) {
+ + 			p = ERR_PTR(ret);
+ + 			clear_bit(FLAG_REQUESTED, &p->flags);
+ + 			goto done;
+ + 		}
+ + 	}
+ + 
+ + done:
+ + 	return p;
+ + }
+ + 
+ + static struct pwm_device *__pwm_request_byname(const char *name,
+ + 					       const char *label)
+ + {
+ + 	struct device *d;
+ + 	struct pwm_device *p;
+ + 
+ + 	d = class_find_device(&pwm_class, NULL, (char *)name, pwm_match_name);
+ + 	if (!d) {
+ + 		p = ERR_PTR(-EINVAL);
+ + 		goto done;
+ + 	}
+ + 	if (IS_ERR(d)) {
+ + 		p = (struct pwm_device *)d;
+ + 		goto done;
+ + 	}
+ + 
+ + 	p = __pwm_request(dev_get_drvdata(d), label);
+ + 
+ + done:
+ + 	return p;
+ + }
+ + 
+ + struct pwm_device *pwm_request_byname(const char *name, const char *label)
+ + {
+ + 	struct pwm_device *p;
+ + 
+ + 	mutex_lock(&device_list_mutex);
+ + 	p = __pwm_request_byname(name, label);
+ + 	mutex_unlock(&device_list_mutex);
+ + 	return p;
+ + }
+ + EXPORT_SYMBOL(pwm_request_byname);
+ + 
+ + struct pwm_device *pwm_request(const char *bus_id, int id, const char *label)
+ + {
+ + 	char name[256];
+ + 	int ret;
+ + 
+ + 	if (id == -1)
+ + 		ret = scnprintf(name, sizeof name, "%s", bus_id);
+ + 	else
+ + 		ret = scnprintf(name, sizeof name, "%s:%d", bus_id, id);
+ + 	if (ret <= 0 || ret >= sizeof name)
+ + 		return ERR_PTR(-EINVAL);
+ + 
+ + 	return pwm_request_byname(name, label);
+ + }
+ + EXPORT_SYMBOL(pwm_request);
+ + 
+ + void pwm_release(struct pwm_device *p)
+ + {
+ + 	mutex_lock(&device_list_mutex);
+ + 
+ + 	if (!test_and_clear_bit(FLAG_REQUESTED, &p->flags)) {
+ + 		pr_debug("%s pwm device is not requested!\n",
+ + 				dev_name(p->dev));
+ + 		goto done;
+ + 	}
+ + 
+ + 	pwm_stop(p);
+ + 	pwm_unsynchronize(p, NULL);
+ + 	pwm_set_handler(p, NULL, NULL);
+ + 
+ + 	p->label = NULL;
+ + 	p->pid = -1;
+ + 
+ + 	if (p->ops->release)
+ + 		p->ops->release(p);
+ + done:
+ + 	mutex_unlock(&device_list_mutex);
+ + }
+ + EXPORT_SYMBOL(pwm_release);
+ + 
+ + unsigned long pwm_ns_to_ticks(struct pwm_device *p, unsigned long nsecs)
+ + {
+ + 	unsigned long long ticks;
+ + 
+ + 	ticks = nsecs;
+ + 	ticks *= p->tick_hz;
+ + 	do_div(ticks, 1000000000);
+ + 	return ticks;
+ + }
+ + EXPORT_SYMBOL(pwm_ns_to_ticks);
+ + 
+ + unsigned long pwm_ticks_to_ns(struct pwm_device *p, unsigned long ticks)
+ + {
+ + 	unsigned long long ns;
+ + 
+ + 	if (!p->tick_hz) {
+ + 		pr_debug("%s: frequency is zero\n", dev_name(p->dev));
+ + 		return 0;
+ + 	}
+ + 
+ + 	ns = ticks;
+ + 	ns *= 1000000000UL;
+ + 	do_div(ns, p->tick_hz);
+ + 	return ns;
+ + }
+ + EXPORT_SYMBOL(pwm_ticks_to_ns);
+ + 
+ + static void pwm_config_ns_to_ticks(struct pwm_device *p, struct pwm_config *c)
+ + {
+ + 	if (test_bit(PWM_CONFIG_PERIOD_NS, &c->config_mask)) {
+ + 		c->period_ticks = pwm_ns_to_ticks(p, c->period_ns);
+ + 		clear_bit(PWM_CONFIG_PERIOD_NS, &c->config_mask);
+ + 		set_bit(PWM_CONFIG_PERIOD_TICKS, &c->config_mask);
+ + 	}
+ + 
+ + 	if (test_bit(PWM_CONFIG_DUTY_NS, &c->config_mask)) {
+ + 		c->duty_ticks = pwm_ns_to_ticks(p, c->duty_ns);
+ + 		clear_bit(PWM_CONFIG_DUTY_NS, &c->config_mask);
+ + 		set_bit(PWM_CONFIG_DUTY_TICKS, &c->config_mask);
+ + 	}
+ + }
+ + 
+ + static void pwm_config_percent_to_ticks(struct pwm_device *p,
+ + 					struct pwm_config *c)
+ + {
+ + 	if (test_bit(PWM_CONFIG_DUTY_PERCENT, &c->config_mask)) {
+ + 		if (test_bit(PWM_CONFIG_PERIOD_TICKS, &c->config_mask))
+ + 			c->duty_ticks = c->period_ticks;
+ + 		else
+ + 			c->duty_ticks = p->period_ticks;
+ + 
+ + 		c->duty_ticks *= c->duty_percent;
+ + 		c->duty_ticks /= 100;
+ + 		clear_bit(PWM_CONFIG_DUTY_PERCENT, &c->config_mask);
+ + 		set_bit(PWM_CONFIG_DUTY_TICKS, &c->config_mask);
+ + 	}
+ + }
+ + 
+ + int pwm_config_nosleep(struct pwm_device *p, struct pwm_config *c)
+ + {
+ + 	if (!p->ops->config_nosleep)
+ + 		return -EINVAL;
+ + 
+ + 	pwm_config_ns_to_ticks(p, c);
+ + 	pwm_config_percent_to_ticks(p, c);
+ + 
+ + 	return p->ops->config_nosleep(p, c);
+ + }
+ + EXPORT_SYMBOL(pwm_config_nosleep);
+ + 
+ + int pwm_config(struct pwm_device *p, struct pwm_config *c)
+ + {
+ + 	int ret = 0;
+ + 
+ + 	pwm_config_ns_to_ticks(p, c);
+ + 	pwm_config_percent_to_ticks(p, c);
+ + 
+ + 	switch (c->config_mask & (BIT(PWM_CONFIG_PERIOD_TICKS)
+ + 				  | BIT(PWM_CONFIG_DUTY_TICKS))) {
+ + 	case BIT(PWM_CONFIG_PERIOD_TICKS):
+ + 		if (p->duty_ticks > c->period_ticks) {
+ + 			ret = -EINVAL;
+ + 			goto err;
+ + 		}
+ + 		break;
+ + 	case BIT(PWM_CONFIG_DUTY_TICKS):
+ + 		if (p->period_ticks < c->duty_ticks) {
+ + 			ret = -EINVAL;
+ + 			goto err;
+ + 		}
+ + 		break;
+ + 	case BIT(PWM_CONFIG_DUTY_TICKS) | BIT(PWM_CONFIG_PERIOD_TICKS):
+ + 		if (c->duty_ticks > c->period_ticks) {
+ + 			ret = -EINVAL;
+ + 			goto err;
+ + 		}
+ + 		break;
+ + 	default:
+ + 		break;
+ + 	}
+ + 
+ + err:
+ + 	dev_dbg(p->dev, "%s: config_mask %lu period_ticks %lu duty_ticks %lu"
+ + 		" polarity %d duty_ns %lu period_ns %lu duty_percent %d\n",
+ + 		__func__, c->config_mask, c->period_ticks, c->duty_ticks,
+ + 		c->polarity, c->duty_ns, c->period_ns, c->duty_percent);
+ + 
+ + 	if (ret)
+ + 		return ret;
+ + 	spin_lock(&p->pwm_lock);
+ + 	ret = p->ops->config(p, c);
+ + 	spin_unlock(&p->pwm_lock);
+ + 	return ret;
+ + }
+ + EXPORT_SYMBOL(pwm_config);
+ + 
+ + int pwm_set_period_ns(struct pwm_device *p, unsigned long period_ns)
+ + {
+ + 	struct pwm_config c = {
+ + 		.config_mask = BIT(PWM_CONFIG_PERIOD_TICKS),
+ + 		.period_ticks = pwm_ns_to_ticks(p, period_ns),
+ + 	};
+ + 
+ + 	spin_lock(&p->pwm_lock);
+ + 	p->period_ns = period_ns;
+ + 	spin_unlock(&p->pwm_lock);
+ + 	return pwm_config(p, &c);
+ + }
+ + EXPORT_SYMBOL(pwm_set_period_ns);
+ + 
+ + unsigned long pwm_get_period_ns(struct pwm_device *p)
+ + {
+ + 	return pwm_ticks_to_ns(p, p->period_ticks);
+ + }
+ + EXPORT_SYMBOL(pwm_get_period_ns);
+ + 
+ + int pwm_set_frequency(struct pwm_device *p, unsigned long freq)
+ + {
+ + 	struct pwm_config c;
+ + 
+ + 	if (!freq)
+ + 		return -EINVAL;
+ + 
+ + 	c.config_mask = BIT(PWM_CONFIG_PERIOD_TICKS),
+ + 	c.period_ticks = pwm_ns_to_ticks(p, (NSEC_PER_SEC / freq)),
+ + 	spin_lock(&p->pwm_lock);
+ + 	p->period_ns = NSEC_PER_SEC / freq;
+ + 	spin_unlock(&p->pwm_lock);
+ + 	return pwm_config(p, &c);
+ + }
+ + EXPORT_SYMBOL(pwm_set_frequency);
+ + 
+ + unsigned long pwm_get_frequency(struct pwm_device *p)
+ + {
+ + 	unsigned long period_ns;
+ + 
+ + 	 period_ns = pwm_ticks_to_ns(p, p->period_ticks);
+ + 
+ + 	if (!period_ns) {
+ + 		pr_debug("%s: frequency is zero\n", dev_name(p->dev));
+ + 		return 0;
+ + 	}
+ + 
+ + 	return	NSEC_PER_SEC / period_ns;
+ + }
+ + EXPORT_SYMBOL(pwm_get_frequency);
+ + 
+ + int pwm_set_period_ticks(struct pwm_device *p,
+ + 					unsigned long ticks)
+ + {
+ + 	struct pwm_config c = {
+ + 		.config_mask = BIT(PWM_CONFIG_PERIOD_TICKS),
+ + 		.period_ticks = ticks,
+ + 	};
+ + 
+ + 	spin_lock(&p->pwm_lock);
+ + 	p->period_ns = pwm_ticks_to_ns(p, ticks);
+ + 	spin_unlock(&p->pwm_lock);
+ + 	return pwm_config(p, &c);
+ + }
+ + EXPORT_SYMBOL(pwm_set_period_ticks);
+ + 
+ + int pwm_set_duty_ns(struct pwm_device *p, unsigned long duty_ns)
+ + {
+ + 	struct pwm_config c = {
+ + 		.config_mask = BIT(PWM_CONFIG_DUTY_TICKS),
+ + 		.duty_ticks = pwm_ns_to_ticks(p, duty_ns),
+ + 	};
+ + 	spin_lock(&p->pwm_lock);
+ + 	p->duty_ns = duty_ns;
+ + 	spin_unlock(&p->pwm_lock);
+ + 	return pwm_config(p, &c);
+ + }
+ + EXPORT_SYMBOL(pwm_set_duty_ns);
+ + 
+ + unsigned long pwm_get_duty_ns(struct pwm_device *p)
+ + {
+ + 	return pwm_ticks_to_ns(p, p->duty_ticks);
+ + }
+ + EXPORT_SYMBOL(pwm_get_duty_ns);
+ + 
+ + int pwm_set_duty_percent(struct pwm_device *p, int percent)
+ + {
+ + 	struct pwm_config c = {
+ + 		.config_mask = BIT(PWM_CONFIG_DUTY_PERCENT),
+ + 		.duty_percent = percent,
+ + 	};
+ + 
+ + 	spin_lock(&p->pwm_lock);
+ + 	p->duty_ns = p->period_ns * percent;
+ + 	p->duty_ns /= 100;
+ + 	spin_unlock(&p->pwm_lock);
+ + 	return pwm_config(p, &c);
+ + }
+ + EXPORT_SYMBOL(pwm_set_duty_percent);
+ + 
+ + unsigned long pwm_get_duty_percent(struct pwm_device *p)
+ + {
+ + 	unsigned long long duty_percent;
+ + 
+ + 	if (!p->period_ns) {
+ + 		pr_debug("%s: frequency is zero\n", dev_name(p->dev));
+ + 		return 0;
+ + 	}
+ + 
+ + 	duty_percent = pwm_ticks_to_ns(p, p->duty_ticks);
+ + 	duty_percent *= 100;
+ + 	do_div(duty_percent, p->period_ns);
+ + 	return duty_percent;
+ + }
+ + EXPORT_SYMBOL(pwm_get_duty_percent);
+ + 
+ + int pwm_set_duty_ticks(struct pwm_device *p,
+ + 					unsigned long ticks)
+ + {
+ + 	struct pwm_config c = {
+ + 		.config_mask = BIT(PWM_CONFIG_DUTY_TICKS),
+ + 		.duty_ticks = ticks,
+ + 	};
+ + 
+ + 	spin_lock(&p->pwm_lock);
+ + 	p->duty_ns = pwm_ticks_to_ns(p, ticks);
+ + 	spin_unlock(&p->pwm_lock);
+ + 	return pwm_config(p, &c);
+ + }
+ + EXPORT_SYMBOL(pwm_set_duty_ticks);
+ + 
+ + int pwm_set_polarity(struct pwm_device *p, int active_high)
+ + {
+ + 	struct pwm_config c = {
+ + 		.config_mask = BIT(PWM_CONFIG_POLARITY),
+ + 		.polarity = active_high,
+ + 	};
+ + 	return pwm_config(p, &c);
+ + }
+ + EXPORT_SYMBOL(pwm_set_polarity);
+ + 
+ + int pwm_start(struct pwm_device *p)
+ + {
+ + 	struct pwm_config c = {
+ + 		.config_mask = BIT(PWM_CONFIG_START),
+ + 	};
+ + 	return pwm_config(p, &c);
+ + }
+ + EXPORT_SYMBOL(pwm_start);
+ + 
+ + int pwm_stop(struct pwm_device *p)
+ + {
+ + 	struct pwm_config c = {
+ + 		.config_mask = BIT(PWM_CONFIG_STOP),
+ + 	};
+ + 	return pwm_config(p, &c);
+ + }
+ + EXPORT_SYMBOL(pwm_stop);
+ + 
+ + int pwm_synchronize(struct pwm_device *p, struct pwm_device *to_p)
+ + {
+ + 	if (!p->ops->synchronize)
+ + 		return -EINVAL;
+ + 
+ + 	return p->ops->synchronize(p, to_p);
+ + }
+ + EXPORT_SYMBOL(pwm_synchronize);
+ + 
+ + int pwm_unsynchronize(struct pwm_device *p, struct pwm_device *from_p)
+ + {
+ + 	if (!p->ops->unsynchronize)
+ + 		return -EINVAL;
+ + 
+ + 	return p->ops->unsynchronize(p, from_p);
+ + }
+ + EXPORT_SYMBOL(pwm_unsynchronize);
+ + 
+ + static void pwm_handler(struct work_struct *w)
+ + {
+ + 	struct pwm_device *p = container_of(w, struct pwm_device,
+ + 					    handler_work);
+ + 	if (p->handler && p->handler(p, p->handler_data))
+ + 		pwm_stop(p);
+ + }
+ + 
+ + static void __pwm_callback(struct pwm_device *p)
+ + {
+ + 	queue_work(pwm_handler_workqueue, &p->handler_work);
+ + }
+ + 
+ + int pwm_set_handler(struct pwm_device *p, pwm_handler_t handler, void *data)
+ + {
+ + 	if (p->ops->set_callback) {
+ + 		p->handler_data = data;
+ + 		p->handler = handler;
+ + 		INIT_WORK(&p->handler_work, pwm_handler);
+ + 		return p->ops->set_callback(p, handler ? __pwm_callback : NULL);
+ + 	}
+ + 	return -EINVAL;
+ + }
+ + EXPORT_SYMBOL(pwm_set_handler);
+ + 
+ + static ssize_t pwm_run_show(struct device *dev,
+ + 			    struct device_attribute *attr,
+ + 			    char *buf)
+ + {
+ + 	struct pwm_device *p = dev_get_drvdata(dev);
+ + 	return sprintf(buf, "%d\n", pwm_is_running(p));
+ + }
+ + 
+ + static ssize_t pwm_run_store(struct device *dev,
+ + 			     struct device_attribute *attr,
+ + 			     const char *buf, size_t len)
+ + {
+ + 	struct pwm_device *p = dev_get_drvdata(dev);
+ + 	int ret;
+ + 
+ + 	if (sysfs_streq(buf, "1"))
+ + 		ret = pwm_start(p);
+ + 	else if (sysfs_streq(buf, "0"))
+ + 		ret = pwm_stop(p);
+ + 	else
+ + 		ret = -EINVAL;
+ + 
+ + 	if (ret < 0)
+ + 		return ret;
+ + 	return len;
+ + }
+ + static DEVICE_ATTR(run, S_IRUGO | S_IWUSR, pwm_run_show, pwm_run_store);
+ + 
+ + static ssize_t pwm_tick_hz_show(struct device *dev,
+ + 				struct device_attribute *attr,
+ + 				char *buf)
+ + {
+ + 	struct pwm_device *p = dev_get_drvdata(dev);
+ + 	return sprintf(buf, "%lu\n", p->tick_hz);
+ + }
+ + static DEVICE_ATTR(tick_hz, S_IRUGO, pwm_tick_hz_show, NULL);
+ + 
+ + static ssize_t pwm_duty_ns_show(struct device *dev,
+ + 				struct device_attribute *attr,
+ + 				char *buf)
+ + {
+ + 	struct pwm_device *p = dev_get_drvdata(dev);
+ + 	return sprintf(buf, "%lu\n", pwm_get_duty_ns(p));
+ + }
+ + 
+ + static ssize_t pwm_duty_ns_store(struct device *dev,
+ + 				 struct device_attribute *attr,
+ + 				 const char *buf, size_t len)
+ + {
+ + 	unsigned long duty_ns;
+ + 	struct pwm_device *p = dev_get_drvdata(dev);
+ + 	int ret;
+ + 
+ + 	if (!kstrtoul(buf, 10, &duty_ns)) {
+ + 		ret = pwm_set_duty_ns(p, duty_ns);
+ + 
+ + 		if (ret < 0)
+ + 			return ret;
+ + 	}
+ + 
+ + 	return len;
+ + }
+ + static DEVICE_ATTR(duty_ns, S_IRUGO | S_IWUSR, pwm_duty_ns_show,
+ + 	       pwm_duty_ns_store);
+ + 
+ + static ssize_t pwm_duty_percent_show(struct device *dev,
+ + 				struct device_attribute *attr,
+ + 				char *buf)
+ + {
+ + 	struct pwm_device *p = dev_get_drvdata(dev);
+ + 	return sprintf(buf, "%lu\n", pwm_get_duty_percent(p));
+ + }
+ + 
+ + static ssize_t pwm_duty_percent_store(struct device *dev,
+ + 				 struct device_attribute *attr,
+ + 				 const char *buf,
+ + 				 size_t len)
+ + {
+ + 	unsigned long duty_ns;
+ + 	struct pwm_device *p = dev_get_drvdata(dev);
+ + 	int ret;
+ + 
+ + 	if (!kstrtoul(buf, 10, &duty_ns)) {
+ + 		ret = pwm_set_duty_percent(p, duty_ns);
+ + 
+ + 		if (ret < 0)
+ + 			return ret;
+ + 	}
+ + 
+ + 	return len;
+ + }
+ + 
+ + static DEVICE_ATTR(duty_percent, S_IRUGO | S_IWUSR, pwm_duty_percent_show,
+ + 	       pwm_duty_percent_store);
+ + 
+ + static ssize_t pwm_period_ns_show(struct device *dev,
+ + 				  struct device_attribute *attr,
+ + 				  char *buf)
+ + {
+ + 	struct pwm_device *p = dev_get_drvdata(dev);
+ + 	return sprintf(buf, "%lu\n", pwm_get_period_ns(p));
+ + }
+ + 
+ + static ssize_t pwm_period_ns_store(struct device *dev,
+ + 				   struct device_attribute *attr,
+ + 				   const char *buf, size_t len)
+ + {
+ + 	unsigned long period_ns;
+ + 	struct pwm_device *p = dev_get_drvdata(dev);
+ + 	int ret;
+ + 
+ + 	if (!kstrtoul(buf, 10, &period_ns)) {
+ + 		ret = pwm_set_period_ns(p, period_ns);
+ + 
+ + 		if (ret < 0)
+ + 			return ret;
+ + 	}
+ + 
+ + 	return len;
+ + }
+ + static DEVICE_ATTR(period_ns, S_IRUGO | S_IWUSR, pwm_period_ns_show,
+ + 	       pwm_period_ns_store);
+ + 
+ + static ssize_t pwm_period_freq_show(struct device *dev,
+ + 				  struct device_attribute *attr,
+ + 				  char *buf)
+ + {
+ + 	struct pwm_device *p = dev_get_drvdata(dev);
+ + 	return sprintf(buf, "%lu\n", pwm_get_frequency(p));
+ + }
+ + 
+ + static ssize_t pwm_period_freq_store(struct device *dev,
+ + 				   struct device_attribute *attr,
+ + 				   const char *buf,
+ + 				   size_t len)
+ + {
+ + 	unsigned long freq_hz;
+ + 	int ret;
+ + 
+ + 	struct pwm_device *p = dev_get_drvdata(dev);
+ + 	if (!kstrtoul(buf, 10, &freq_hz)) {
+ + 		ret = pwm_set_frequency(p, freq_hz);
+ + 
+ + 		if (ret < 0)
+ + 			return ret;
+ + 	}
+ + 	return len;
+ + }
+ + 
+ + static DEVICE_ATTR(period_freq, S_IRUGO | S_IWUSR, pwm_period_freq_show,
+ + 	       pwm_period_freq_store);
+ + 
+ + static ssize_t pwm_polarity_show(struct device *dev,
+ + 				 struct device_attribute *attr,
+ + 				 char *buf)
+ + {
+ + 	struct pwm_device *p = dev_get_drvdata(dev);
+ + 	return sprintf(buf, "%d\n", p->active_high ? 1 : 0);
+ + }
+ + 
+ + static ssize_t pwm_polarity_store(struct device *dev,
+ + 				  struct device_attribute *attr,
+ + 				  const char *buf, size_t len)
+ + {
+ + 	unsigned long polarity;
+ + 	struct pwm_device *p = dev_get_drvdata(dev);
+ + 	int ret;
+ + 
+ + 	if (!kstrtoul(buf, 10, &polarity)) {
+ + 		ret = pwm_set_polarity(p, polarity);
+ + 
+ + 		if (ret < 0)
+ + 			return ret;
+ + 	}
+ + 
+ + 	return len;
+ + }
+ + static DEVICE_ATTR(polarity, S_IRUGO | S_IWUSR, pwm_polarity_show,
+ + 	       pwm_polarity_store);
+ + 
+ + static ssize_t pwm_request_show(struct device *dev,
+ + 				struct device_attribute *attr,
+ + 				char *buf)
+ + {
+ + 	struct pwm_device *p = dev_get_drvdata(dev);
+ + 	int ret;
+ + 
+ + 	ret = test_bit(FLAG_REQUESTED, &p->flags);
+ + 
+ + 	if (ret)
+ + 		return sprintf(buf, "%s requested by %s\n",
+ + 				dev_name(p->dev), p->label);
+ + 	else
+ + 		return sprintf(buf, "%s is free\n",
+ + 				dev_name(p->dev));
+ + }
+ + 
+ + static ssize_t pwm_request_store(struct device *dev,
+ + 				 struct device_attribute *attr,
+ + 				 const char *buf, size_t len)
+ + {
+ + 	struct pwm_device *p = dev_get_drvdata(dev);
+ + 	unsigned long request;
+ + 	struct pwm_device *ret;
+ + 
+ + 	if (!kstrtoul(buf, 10, &request)) {
+ + 		if (request) {
+ + 			mutex_lock(&device_list_mutex);
+ + 			ret = __pwm_request(p, REQUEST_SYSFS);
+ + 			mutex_unlock(&device_list_mutex);
+ + 
+ + 			if (IS_ERR(ret))
+ + 				return PTR_ERR(ret);
+ + 		} else
+ + 			pwm_release(p);
+ + 	}
+ + 
+ + 	return len;
+ + }
+ + static DEVICE_ATTR(request, S_IRUGO | S_IWUSR, pwm_request_show,
+ + 	       pwm_request_store);
+ + 
+ + static const struct attribute *pwm_attrs[] = {
+ + 	&dev_attr_tick_hz.attr,
+ + 	&dev_attr_run.attr,
+ + 	&dev_attr_polarity.attr,
+ + 	&dev_attr_duty_ns.attr,
+ + 	&dev_attr_period_ns.attr,
+ + 	&dev_attr_request.attr,
+ + 	&dev_attr_duty_percent.attr,
+ + 	&dev_attr_period_freq.attr,
+ + 	NULL,
+ + };
+ + 
+ + static const struct attribute_group pwm_device_attr_group = {
+ + 	.attrs = (struct attribute **) pwm_attrs,
+ + };
+ + 
+ + static struct class_attribute pwm_class_attrs[] = {
+ + 	__ATTR_NULL,
+ + };
+ + 
+ + static struct class pwm_class = {
+ + 	.name = "pwm",
+ + 	.owner = THIS_MODULE,
+ + 
+ + 	.class_attrs = pwm_class_attrs,
+ + };
+ + 
+ + static int pwm_freq_transition_notifier_cb(struct notifier_block *nb,
+ + 		unsigned long val, void *data)
+ + {
+ + 	struct pwm_device *p;
+ + 
+ + 	p = container_of(nb, struct pwm_device, freq_transition);
+ + 
+ + 	if (val == CPUFREQ_POSTCHANGE && pwm_is_requested(p))
+ + 		p->ops->freq_transition_notifier_cb(p);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static inline int pwm_cpufreq_notifier_register(struct pwm_device *p)
+ + {
+ + 	p->freq_transition.notifier_call = pwm_freq_transition_notifier_cb;
+ + 
+ + 	return cpufreq_register_notifier(&p->freq_transition,
+ + 		       CPUFREQ_TRANSITION_NOTIFIER);
+ + }
+ + 
+ + int pwm_register_byname(struct pwm_device *p, struct device *parent,
+ + 			const char *name)
+ + {
+ + 	struct device *d;
+ + 	int ret;
+ + 
+ + 	if (!p->ops || !p->ops->config)
+ + 		return -EINVAL;
+ + 
+ + 	mutex_lock(&device_list_mutex);
+ + 
+ + 	d = class_find_device(&pwm_class, NULL, (char *)name, pwm_match_name);
+ + 	if (d) {
+ + 		ret = -EEXIST;
+ + 		goto err_found_device;
+ + 	}
+ + 
+ + 	p->dev = device_create(&pwm_class, parent, MKDEV(0, 0), NULL, name);
+ + 	if (IS_ERR(p->dev)) {
+ + 		ret = PTR_ERR(p->dev);
+ + 		goto err_device_create;
+ + 	}
+ + 
+ + 	ret = sysfs_create_group(&p->dev->kobj, &pwm_device_attr_group);
+ + 	if (ret)
+ + 		goto err_create_group;
+ + 
+ + 	dev_set_drvdata(p->dev, p);
+ + 	p->flags = BIT(FLAG_REGISTERED);
+ + 
+ + 	ret = pwm_cpufreq_notifier_register(p);
+ + 
+ + 	if (ret < 0)
+ + 		printk(KERN_ERR "Failed to add cpufreq notifier\n");
+ + 
+ + 	spin_lock_init(&p->pwm_lock);
+ + 	goto done;
+ + 
+ + err_create_group:
+ + 	device_unregister(p->dev);
+ + 	p->flags = 0;
+ + 
+ + err_device_create:
+ + err_found_device:
+ + done:
+ + 	mutex_unlock(&device_list_mutex);
+ + 
+ + 	return ret;
+ + }
+ + EXPORT_SYMBOL(pwm_register_byname);
+ + 
+ + int pwm_register(struct pwm_device *p, struct device *parent, int id)
+ + {
+ + 	int ret;
+ + 	char name[256];
+ + 
+ + 	if (IS_ERR_OR_NULL(parent))
+ + 		return -EINVAL;
+ + 
+ + 	if (id == -1)
+ + 		ret = scnprintf(name, sizeof name, "%s", dev_name(parent));
+ + 	else
+ + 		ret = scnprintf(name, sizeof name, "%s:%d",
+ + 			       dev_name(parent), id);
+ + 	if (ret <= 0 || ret >= sizeof name)
+ + 		return -EINVAL;
+ + 
+ + 	return pwm_register_byname(p, parent, name);
+ + }
+ + EXPORT_SYMBOL(pwm_register);
+ + 
+ + int pwm_unregister(struct pwm_device *p)
+ + {
+ + 	int ret = 0;
+ + 
+ + 	mutex_lock(&device_list_mutex);
+ + 
+ + 	if (pwm_is_running(p) || pwm_is_requested(p)) {
+ + 		ret = -EBUSY;
+ + 		goto done;
+ + 	}
+ + 
+ + 	sysfs_remove_group(&p->dev->kobj, &pwm_device_attr_group);
+ + 	device_unregister(p->dev);
+ + 	p->flags = 0;
+ + 
+ + done:
+ + 	mutex_unlock(&device_list_mutex);
+ + 
+ + 	return ret;
+ + }
+ + EXPORT_SYMBOL(pwm_unregister);
+ + 
+ + static int __init pwm_init(void)
+ + {
+ + 	return class_register(&pwm_class);
+ + }
+ + 
+ + static void __exit pwm_exit(void)
+ + {
+ + 	class_unregister(&pwm_class);
+ + }
+ + 
+ + #ifdef MODULE
+ + module_init(pwm_init);
+ + module_exit(pwm_exit);
+ + MODULE_LICENSE("GPL");
+ + #else
+ + postcore_initcall(pwm_init);
+ + #endif
+ diff -crN linux-3.2.1_o/drivers/regulator/core.c linux-3.2.1/drivers/regulator/core.c
+ *** linux-3.2.1_o/drivers/regulator/core.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/regulator/core.c	2014-11-25 13:19:15.868424377 +0900
+ ***************
+ *** 169,174 ****
+ --- 169,177 ----
+   {
+   	struct regulator *regulator;
+   
+ +         if (rdev->ignore_check_consumers)
+ +                 return 0;
+ + 
+   	list_for_each_entry(regulator, &rdev->consumer_list, list) {
+   		/*
+   		 * Assume consumers that didn't say anything are OK
+ ***************
+ *** 1768,1810 ****
+   			}
+   		}
+   
+   		/*
+   		 * If we can't obtain the old selector there is not enough
+   		 * info to call set_voltage_time_sel().
+   		 */
+   		if (rdev->desc->ops->set_voltage_time_sel &&
+   		    rdev->desc->ops->get_voltage_sel) {
+ ! 			unsigned int old_selector = 0;
+   
+ - 			ret = rdev->desc->ops->get_voltage_sel(rdev);
+ - 			if (ret < 0)
+ - 				return ret;
+ - 			old_selector = ret;
+   			delay = rdev->desc->ops->set_voltage_time_sel(rdev,
+   						old_selector, selector);
+   		}
+   
+ ! 		if (best_val != INT_MAX) {
+ ! 			ret = rdev->desc->ops->set_voltage_sel(rdev, selector);
+ ! 			selector = best_val;
+ ! 		} else {
+ ! 			ret = -EINVAL;
+   		}
+ - 	} else {
+ - 		ret = -EINVAL;
+ - 	}
+   
+ - 	/* Insert any necessary delays */
+ - 	if (delay >= 1000) {
+ - 		mdelay(delay / 1000);
+ - 		udelay(delay % 1000);
+ - 	} else if (delay) {
+ - 		udelay(delay);
+ - 	}
+ - 
+ - 	if (ret == 0)
+   		_notifier_call_chain(rdev, REGULATOR_EVENT_VOLTAGE_CHANGE,
+ ! 				     NULL);
+   
+   	trace_regulator_set_voltage_complete(rdev_get_name(rdev), selector);
+   
+ --- 1771,1819 ----
+   			}
+   		}
+   
+ + 		if (best_val != INT_MAX) {
+ + 			ret = rdev->desc->ops->set_voltage_sel(rdev, selector);
+ + 			selector = best_val;
+ + 		} else {
+ + 			ret = -EINVAL;
+ + 		}
+ + 	} else {
+ + 		ret = -EINVAL;
+ + 	}
+ + 
+ + 	if (ret == 0) {
+   		/*
+   		 * If we can't obtain the old selector there is not enough
+   		 * info to call set_voltage_time_sel().
+   		 */
+   		if (rdev->desc->ops->set_voltage_time_sel &&
+   		    rdev->desc->ops->get_voltage_sel) {
+ ! 			int old_selector;
+ ! 
+ ! 			old_selector = rdev->desc->ops->get_voltage_sel(rdev);
+ ! 			if (old_selector < 0)
+ ! 				return old_selector;
+   
+   			delay = rdev->desc->ops->set_voltage_time_sel(rdev,
+   						old_selector, selector);
+ + 			if (delay < 0) {
+ + 				delay = 0;
+ + 				rdev_warn(rdev, "set_voltage_time_sel() failed"
+ + 							": %d\n", ret);
+ + 			}
+   		}
+   
+ ! 		/* Insert any necessary delays */
+ ! 		if (delay >= 1000) {
+ ! 			mdelay(delay / 1000);
+ ! 			udelay(delay % 1000);
+ ! 		} else if (delay) {
+ ! 			udelay(delay);
+   		}
+   
+   		_notifier_call_chain(rdev, REGULATOR_EVENT_VOLTAGE_CHANGE,
+ ! 					NULL);
+ ! 	}
+   
+   	trace_regulator_set_voltage_complete(rdev_get_name(rdev), selector);
+   
+ ***************
+ *** 2682,2687 ****
+ --- 2691,2697 ----
+   	rdev->reg_data = driver_data;
+   	rdev->owner = regulator_desc->owner;
+   	rdev->desc = regulator_desc;
+ +         rdev->ignore_check_consumers = init_data->ignore_check_consumers;
+   	INIT_LIST_HEAD(&rdev->consumer_list);
+   	INIT_LIST_HEAD(&rdev->list);
+   	BLOCKING_INIT_NOTIFIER_HEAD(&rdev->notifier);
+ diff -crN linux-3.2.1_o/drivers/regulator/Kconfig linux-3.2.1/drivers/regulator/Kconfig
+ *** linux-3.2.1_o/drivers/regulator/Kconfig	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/regulator/Kconfig	2014-11-25 13:19:16.033107646 +0900
+ ***************
+ *** 259,264 ****
+ --- 259,273 ----
+   	  three step-down converters and two general-purpose LDO voltage regulators.
+   	  It supports TI's software based Class-2 SmartReflex implementation.
+   
+ + config REGULATOR_TPS65217
+ + 	tristate "TI TPS65217 Power regulators"
+ + 	depends on MFD_TPS65217
+ + 	help
+ + 	  This driver supports TPS65217 voltage regulator chips. TPS65217
+ + 	  provides three step-down converters and four general-purpose LDO
+ + 	  voltage regulators. It supports software based voltage control
+ + 	  for different voltage domains
+ + 
+   config REGULATOR_TPS65912
+   	tristate "TI TPS65912 Power regulator"
+   	depends on (MFD_TPS65912_I2C || MFD_TPS65912_SPI)
+ diff -crN linux-3.2.1_o/drivers/regulator/Makefile linux-3.2.1/drivers/regulator/Makefile
+ *** linux-3.2.1_o/drivers/regulator/Makefile	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/regulator/Makefile	2014-11-25 13:19:16.033107646 +0900
+ ***************
+ *** 38,43 ****
+ --- 38,44 ----
+   obj-$(CONFIG_REGULATOR_TPS6105X) += tps6105x-regulator.o
+   obj-$(CONFIG_REGULATOR_TPS65023) += tps65023-regulator.o
+   obj-$(CONFIG_REGULATOR_TPS6507X) += tps6507x-regulator.o
+ + obj-$(CONFIG_REGULATOR_TPS65217) += tps65217-regulator.o
+   obj-$(CONFIG_REGULATOR_TPS6524X) += tps6524x-regulator.o
+   obj-$(CONFIG_REGULATOR_TPS65912) += tps65912-regulator.o
+   obj-$(CONFIG_REGULATOR_88PM8607) += 88pm8607.o
+ diff -crN linux-3.2.1_o/drivers/regulator/tps65217-regulator.c linux-3.2.1/drivers/regulator/tps65217-regulator.c
+ *** linux-3.2.1_o/drivers/regulator/tps65217-regulator.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/drivers/regulator/tps65217-regulator.c	2014-11-25 13:19:16.037039520 +0900
+ ***************
+ *** 0 ****
+ --- 1,514 ----
+ + /*
+ +  * tps65217-regulator.c
+ +  *
+ +  * Regulator driver for TPS65217 PMIC
+ +  *
+ +  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #include <linux/kernel.h>
+ + #include <linux/module.h>
+ + #include <linux/device.h>
+ + #include <linux/init.h>
+ + #include <linux/err.h>
+ + #include <linux/platform_device.h>
+ + 
+ + #include <linux/regulator/driver.h>
+ + #include <linux/regulator/machine.h>
+ + #include <linux/mfd/tps65217.h>
+ + 
+ + #define TPS65217_REGULATOR(_name, _id, _ops, _n)	\
+ + 	{						\
+ + 		.name		= _name,		\
+ + 		.id		= _id,			\
+ + 		.ops		= &_ops,		\
+ + 		.n_voltages	= _n,			\
+ + 		.type		= REGULATOR_VOLTAGE,	\
+ + 		.owner		= THIS_MODULE,		\
+ + 	}						\
+ + 
+ + #define TPS65217_INFO(_nm, _min, _max, _f1, _f2, _t, _n, _em, _vr, _vm)	\
+ + 	{						\
+ + 		.name		= _nm,			\
+ + 		.min_uV		= _min,			\
+ + 		.max_uV		= _max,			\
+ + 		.vsel_to_uv	= _f1,			\
+ + 		.uv_to_vsel	= _f2,			\
+ + 		.table		= _t,			\
+ + 		.table_len	= _n,			\
+ + 		.enable_mask	= _em,			\
+ + 		.set_vout_reg	= _vr,			\
+ + 		.set_vout_mask	= _vm,			\
+ + 	}
+ + 
+ + static const int LDO1_VSEL_table[] = {
+ + 	1000000, 1100000, 1200000, 1250000,
+ + 	1300000, 1350000, 1400000, 1500000,
+ + 	1600000, 1800000, 2500000, 2750000,
+ + 	2800000, 3000000, 3100000, 3300000,
+ + };
+ + 
+ + static int tps65217_vsel_to_uv1(unsigned int vsel)
+ + {
+ + 	int uV = 0;
+ + 
+ + 	if (vsel > 63)
+ + 		return -EINVAL;
+ + 
+ + 	if (vsel <= 24)
+ + 		uV = vsel * 25000 + 900000;
+ + 	else if (vsel <= 52)
+ + 		uV = (vsel - 24) * 50000 + 1500000;
+ + 	else if (vsel < 56)
+ + 		uV = (vsel - 52) * 100000 + 2900000;
+ + 	else
+ + 		uV = 3300000;
+ + 
+ + 	return uV;
+ + }
+ + 
+ + static int tps65217_uv_to_vsel1(int uV, unsigned int *vsel)
+ + {
+ + 	if ((uV < 0) && (uV > 3300000))
+ + 		return -EINVAL;
+ + 
+ + 	if (uV <= 1500000)
+ + 		*vsel = (uV - 875001) / 25000;
+ + 	else if (uV <= 2900000)
+ + 		*vsel = 24 + (uV - 1450001) / 50000;
+ + 	else if (uV < 3300000)
+ + 		*vsel = 52 + (uV - 2800001) / 100000;
+ + 	else
+ + 		*vsel = 56;
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static int tps65217_vsel_to_uv2(unsigned int vsel)
+ + {
+ + 	int uV = 0;
+ + 
+ + 	if (vsel > 31)
+ + 		return -EINVAL;
+ + 
+ + 	if (vsel <= 8)
+ + 		uV = vsel * 50000 + 1500000;
+ + 	else if (vsel <= 13)
+ + 		uV = (vsel - 8) * 100000 + 1900000;
+ + 	else
+ + 		uV = (vsel - 13) * 50000 + 2400000;
+ + 
+ + 	return uV;
+ + }
+ + 
+ + static int tps65217_uv_to_vsel2(int uV, unsigned int *vsel)
+ + {
+ + 	if ((uV < 0) && (uV > 3300000))
+ + 		return -EINVAL;
+ + 
+ + 	if (uV <= 1900000)
+ + 		*vsel = (uV - 1450001) / 50000;
+ + 	else if (uV <= 2400000)
+ + 		*vsel = 8 + (uV - 1800001) / 100000;
+ + 	else
+ + 		*vsel = 13 + (uV - 2350001) / 50000;
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static struct tps_info tps65217_pmic_regs[] = {
+ + 	TPS65217_INFO("DCDC1", 900000, 1800000, tps65217_vsel_to_uv1,
+ + 			tps65217_uv_to_vsel1, NULL, 64, TPS65217_ENABLE_DC1_EN,
+ + 			TPS65217_REG_DEFDCDC1, TPS65217_DEFDCDCX_DCDC_MASK),
+ + 	TPS65217_INFO("DCDC2", 900000, 3300000, tps65217_vsel_to_uv1,
+ + 			tps65217_uv_to_vsel1, NULL, 64, TPS65217_ENABLE_DC2_EN,
+ + 			TPS65217_REG_DEFDCDC2, TPS65217_DEFDCDCX_DCDC_MASK),
+ + 	TPS65217_INFO("DCDC3", 900000, 1500000, tps65217_vsel_to_uv1,
+ + 			tps65217_uv_to_vsel1, NULL, 64, TPS65217_ENABLE_DC3_EN,
+ + 			TPS65217_REG_DEFDCDC3, TPS65217_DEFDCDCX_DCDC_MASK),
+ + 	TPS65217_INFO("LDO1", 1000000, 3300000, NULL, NULL, LDO1_VSEL_table,
+ + 			16, TPS65217_ENABLE_LDO1_EN, TPS65217_REG_DEFLDO1,
+ + 			TPS65217_DEFLDO1_LDO1_MASK),
+ + 	TPS65217_INFO("LDO2", 900000, 3300000, tps65217_vsel_to_uv1,
+ + 			tps65217_uv_to_vsel1, NULL, 64, TPS65217_ENABLE_LDO2_EN,
+ + 			TPS65217_REG_DEFLDO2, TPS65217_DEFLDO2_LDO2_MASK),
+ + 	TPS65217_INFO("LDO3", 1800000, 3300000, tps65217_vsel_to_uv2,
+ + 			tps65217_uv_to_vsel2, NULL, 32,
+ + 			TPS65217_ENABLE_LS1_EN | TPS65217_DEFLDO3_LDO3_EN,
+ + 			TPS65217_REG_DEFLS1, TPS65217_DEFLDO3_LDO3_MASK),
+ + 	TPS65217_INFO("LDO4", 1800000, 3300000, tps65217_vsel_to_uv2,
+ + 			tps65217_uv_to_vsel2, NULL, 32,
+ + 			TPS65217_ENABLE_LS2_EN | TPS65217_DEFLDO4_LDO4_EN,
+ + 			TPS65217_REG_DEFLS2, TPS65217_DEFLDO4_LDO4_MASK),
+ + };
+ + 
+ + static int tps65217_pmic_dcdc_is_enabled(struct regulator_dev *dev)
+ + {
+ + 	int ret;
+ + 	struct tps65217 *tps = rdev_get_drvdata(dev);
+ + 	unsigned int data, dcdc = rdev_get_id(dev);
+ + 
+ + 	if (dcdc < TPS65217_DCDC_1 || dcdc > TPS65217_DCDC_3)
+ + 		return -EINVAL;
+ + 
+ + 	ret = tps65217_reg_read(tps, TPS65217_REG_ENABLE, &data);
+ + 	if (ret)
+ + 		return ret;
+ + 
+ + 	return (data & tps->info[dcdc]->enable_mask) ? 1 : 0;
+ + }
+ + 
+ + static int tps65217_pmic_ldo_is_enabled(struct regulator_dev *dev)
+ + {
+ + 	int ret;
+ + 	struct tps65217 *tps = rdev_get_drvdata(dev);
+ + 	unsigned int data, ldo = rdev_get_id(dev);
+ + 
+ + 	if (ldo < TPS65217_LDO_1 || ldo > TPS65217_LDO_4)
+ + 		return -EINVAL;
+ + 
+ + 	ret = tps65217_reg_read(tps, TPS65217_REG_ENABLE, &data);
+ + 	if (ret)
+ + 		return ret;
+ + 
+ + 	return (data & tps->info[ldo]->enable_mask) ? 1 : 0;
+ + }
+ + 
+ + static int tps65217_pmic_dcdc_enable(struct regulator_dev *dev)
+ + {
+ + 	struct tps65217 *tps = rdev_get_drvdata(dev);
+ + 	unsigned int dcdc = rdev_get_id(dev);
+ + 
+ + 	if (dcdc < TPS65217_DCDC_1 || dcdc > TPS65217_DCDC_3)
+ + 		return -EINVAL;
+ + 
+ + 	/* Enable the regulator and password protection is level 1 */
+ + 	return tps65217_set_bits(tps, TPS65217_REG_ENABLE,
+ + 				tps->info[dcdc]->enable_mask,
+ + 				tps->info[dcdc]->enable_mask,
+ + 				TPS65217_PROTECT_L1);
+ + }
+ + 
+ + static int tps65217_pmic_dcdc_disable(struct regulator_dev *dev)
+ + {
+ + 	struct tps65217 *tps = rdev_get_drvdata(dev);
+ + 	unsigned int dcdc = rdev_get_id(dev);
+ + 
+ + 	if (dcdc < TPS65217_DCDC_1 || dcdc > TPS65217_DCDC_3)
+ + 		return -EINVAL;
+ + 
+ + 	/* Disable the regulator and password protection is level 1 */
+ + 	return tps65217_clear_bits(tps, TPS65217_REG_ENABLE,
+ + 			tps->info[dcdc]->enable_mask, TPS65217_PROTECT_L1);
+ + }
+ + 
+ + static int tps65217_pmic_ldo_enable(struct regulator_dev *dev)
+ + {
+ + 	struct tps65217 *tps = rdev_get_drvdata(dev);
+ + 	unsigned int ldo = rdev_get_id(dev);
+ + 
+ + 	if (ldo < TPS65217_LDO_1 || ldo > TPS65217_LDO_4)
+ + 		return -EINVAL;
+ + 
+ + 	/* Enable the regulator and password protection is level 1 */
+ + 	return tps65217_set_bits(tps, TPS65217_REG_ENABLE,
+ + 				tps->info[ldo]->enable_mask,
+ + 				tps->info[ldo]->enable_mask,
+ + 				TPS65217_PROTECT_L1);
+ + }
+ + 
+ + static int tps65217_pmic_ldo_disable(struct regulator_dev *dev)
+ + {
+ + 	struct tps65217 *tps = rdev_get_drvdata(dev);
+ + 	unsigned int ldo = rdev_get_id(dev);
+ + 
+ + 	if (ldo < TPS65217_LDO_1 || ldo > TPS65217_LDO_4)
+ + 		return -EINVAL;
+ + 
+ + 	/* Disable the regulator and password protection is level 1 */
+ + 	return tps65217_clear_bits(tps, TPS65217_REG_ENABLE,
+ + 			tps->info[ldo]->enable_mask, TPS65217_PROTECT_L1);
+ + }
+ + 
+ + static int tps65217_pmic_dcdc_get_voltage_sel(struct regulator_dev *dev)
+ + {
+ + 	int ret;
+ + 	struct tps65217 *tps = rdev_get_drvdata(dev);
+ + 	unsigned int selector, dcdc = rdev_get_id(dev);
+ + 
+ + 	if (dcdc < TPS65217_DCDC_1 || dcdc > TPS65217_DCDC_3)
+ + 		return -EINVAL;
+ + 
+ + 	ret = tps65217_reg_read(tps, tps->info[dcdc]->set_vout_reg, &selector);
+ + 	if (ret)
+ + 		return ret;
+ + 
+ + 	selector &= tps->info[dcdc]->set_vout_mask;
+ + 
+ + 	return selector;
+ + }
+ + 
+ + static int tps65217_pmic_dcdc_set_voltage(struct regulator_dev *dev,
+ + 				  int min_uV, int max_uV, unsigned *selector)
+ + {
+ + 	int ret;
+ + 	struct tps65217 *tps = rdev_get_drvdata(dev);
+ + 	unsigned int dcdc = rdev_get_id(dev);
+ + 
+ + 	if (dcdc < TPS65217_DCDC_1 || dcdc > TPS65217_DCDC_3)
+ + 		return -EINVAL;
+ + 
+ + 	if (min_uV < tps->info[dcdc]->min_uV
+ + 		|| min_uV > tps->info[dcdc]->max_uV)
+ + 		return -EINVAL;
+ + 
+ + 	if (max_uV < tps->info[dcdc]->min_uV
+ + 		|| max_uV > tps->info[dcdc]->max_uV)
+ + 		return -EINVAL;
+ + 
+ + 	ret = tps->info[dcdc]->uv_to_vsel(min_uV, selector);
+ + 	if (ret)
+ + 		return ret;
+ + 
+ + 	/* Set the voltage based on vsel value and write protect level is 2 */
+ + 	ret = tps65217_set_bits(tps, tps->info[dcdc]->set_vout_reg,
+ + 					tps->info[dcdc]->set_vout_mask,
+ + 					*selector, TPS65217_PROTECT_L2);
+ + 	if (ret)
+ + 		return ret;
+ + 
+ + 	/* Set GO bit to initiate voltage transistion */
+ + 	return tps65217_set_bits(tps, TPS65217_REG_DEFSLEW,
+ + 				TPS65217_DEFSLEW_GO, TPS65217_DEFSLEW_GO,
+ + 				TPS65217_PROTECT_L2);
+ + }
+ + 
+ + static int tps65217_pmic_ldo_get_voltage_sel(struct regulator_dev *dev)
+ + {
+ + 	int ret;
+ + 	struct tps65217 *tps = rdev_get_drvdata(dev);
+ + 	unsigned int selector, ldo = rdev_get_id(dev);
+ + 
+ + 	if (ldo < TPS65217_LDO_1 || ldo > TPS65217_LDO_4)
+ + 		return -EINVAL;
+ + 
+ + 	ret = tps65217_reg_read(tps, tps->info[ldo]->set_vout_reg, &selector);
+ + 	if (ret)
+ + 		return ret;
+ + 
+ + 	selector &= tps->info[ldo]->set_vout_mask;
+ + 
+ + 	return selector;
+ + }
+ + 
+ + static int tps65217_pmic_ldo_set_voltage_sel(struct regulator_dev *dev,
+ + 						unsigned selector)
+ + {
+ + 	struct tps65217 *tps = rdev_get_drvdata(dev);
+ + 	int ldo = rdev_get_id(dev);
+ + 
+ + 	if (ldo != TPS65217_LDO_1)
+ + 		return -EINVAL;
+ + 
+ + 	if (selector >= tps->info[ldo]->table_len)
+ + 		return -EINVAL;
+ + 
+ + 	/* Set the voltage based on vsel value and write protect level is 2 */
+ + 	return tps65217_set_bits(tps, tps->info[ldo]->set_vout_reg,
+ + 					tps->info[ldo]->set_vout_mask,
+ + 					selector, TPS65217_PROTECT_L2);
+ + }
+ + 
+ + static int tps65217_pmic_ldo_set_voltage(struct regulator_dev *dev,
+ + 				  int min_uV, int max_uV, unsigned *selector)
+ + {
+ + 	int ret;
+ + 	struct tps65217 *tps = rdev_get_drvdata(dev);
+ + 	unsigned int ldo = rdev_get_id(dev);
+ + 
+ + 	if (ldo < TPS65217_LDO_2 || ldo > TPS65217_LDO_4)
+ + 		return -EINVAL;
+ + 
+ + 	if (min_uV < tps->info[ldo]->min_uV
+ + 		|| min_uV > tps->info[ldo]->max_uV)
+ + 		return -EINVAL;
+ + 
+ + 	if (max_uV < tps->info[ldo]->min_uV
+ + 		|| max_uV > tps->info[ldo]->max_uV)
+ + 		return -EINVAL;
+ + 
+ + 	ret = tps->info[ldo]->uv_to_vsel(min_uV, selector);
+ + 	if (ret)
+ + 		return ret;
+ + 
+ + 	/* Set the voltage based on vsel value and write protect level is 2 */
+ + 	return tps65217_set_bits(tps, tps->info[ldo]->set_vout_reg,
+ + 					tps->info[ldo]->set_vout_mask,
+ + 					*selector, TPS65217_PROTECT_L2);
+ + }
+ + 
+ + static int tps65217_pmic_dcdc_list_voltage(struct regulator_dev *dev,
+ + 					unsigned selector)
+ + {
+ + 	struct tps65217 *tps = rdev_get_drvdata(dev);
+ + 	unsigned int dcdc = rdev_get_id(dev);
+ + 
+ + 	if (dcdc < TPS65217_DCDC_1 || dcdc > TPS65217_DCDC_3)
+ + 		return -EINVAL;
+ + 
+ + 	if (selector >= tps->info[dcdc]->table_len)
+ + 		return -EINVAL;
+ + 
+ + 	return tps->info[dcdc]->vsel_to_uv(selector);
+ + }
+ + 
+ + static int tps65217_pmic_ldo_list_voltage(struct regulator_dev *dev,
+ + 					unsigned selector)
+ + {
+ + 	struct tps65217 *tps = rdev_get_drvdata(dev);
+ + 	unsigned int ldo = rdev_get_id(dev);
+ + 
+ + 	if (ldo < TPS65217_LDO_1 || ldo > TPS65217_LDO_4)
+ + 		return -EINVAL;
+ + 
+ + 	if (selector >= tps->info[ldo]->table_len)
+ + 		return -EINVAL;
+ + 
+ + 	if (tps->info[ldo]->table)
+ + 		return tps->info[ldo]->table[selector];
+ + 
+ + 	return tps->info[ldo]->vsel_to_uv(selector);
+ + }
+ + 
+ + static int tps65217_pmic_dcdc_set_voltage_time_sel(struct regulator_dev *dev,
+ + 			unsigned int old_sel, unsigned int new_sel)
+ + {
+ + 	struct tps65217 *tps = rdev_get_drvdata(dev);
+ + 	unsigned int dcdc = rdev_get_id(dev);
+ + 	int ret;
+ + 
+ + 	/* If the regulator isn't on, it won't take time here */
+ + 	ret = tps65217_pmic_dcdc_is_enabled(dev);
+ + 	if (!ret || ret < 0)
+ + 		return ret;
+ + 
+ + 	return tps->info[dcdc]->delay;
+ + }
+ + 
+ + /* Operations permitted on DCDCx */
+ + static struct regulator_ops tps65217_pmic_dcdc_ops = {
+ + 	.is_enabled		= tps65217_pmic_dcdc_is_enabled,
+ + 	.enable			= tps65217_pmic_dcdc_enable,
+ + 	.disable		= tps65217_pmic_dcdc_disable,
+ + 	.get_voltage_sel	= tps65217_pmic_dcdc_get_voltage_sel,
+ + 	.set_voltage		= tps65217_pmic_dcdc_set_voltage,
+ + 	.list_voltage		= tps65217_pmic_dcdc_list_voltage,
+ + 	.set_voltage_time_sel	= tps65217_pmic_dcdc_set_voltage_time_sel,
+ + };
+ + 
+ + /* Operations permitted on LDO1 */
+ + static struct regulator_ops tps65217_pmic_ldo1_ops = {
+ + 	.is_enabled		= tps65217_pmic_ldo_is_enabled,
+ + 	.enable			= tps65217_pmic_ldo_enable,
+ + 	.disable		= tps65217_pmic_ldo_disable,
+ + 	.get_voltage_sel	= tps65217_pmic_ldo_get_voltage_sel,
+ + 	.set_voltage_sel	= tps65217_pmic_ldo_set_voltage_sel,
+ + 	.list_voltage		= tps65217_pmic_ldo_list_voltage,
+ + };
+ + 
+ + /* Operations permitted on LDO2, LDO3 and LDO4 */
+ + static struct regulator_ops tps65217_pmic_ldo234_ops = {
+ + 	.is_enabled		= tps65217_pmic_ldo_is_enabled,
+ + 	.enable			= tps65217_pmic_ldo_enable,
+ + 	.disable		= tps65217_pmic_ldo_disable,
+ + 	.get_voltage_sel	= tps65217_pmic_ldo_get_voltage_sel,
+ + 	.set_voltage		= tps65217_pmic_ldo_set_voltage,
+ + 	.list_voltage		= tps65217_pmic_ldo_list_voltage,
+ + };
+ + 
+ + static struct regulator_desc regulators[] = {
+ + 	TPS65217_REGULATOR("DCDC1", TPS65217_DCDC_1,
+ + 				tps65217_pmic_dcdc_ops, 64),
+ + 	TPS65217_REGULATOR("DCDC2",TPS65217_DCDC_2,
+ + 				tps65217_pmic_dcdc_ops, 64),
+ + 	TPS65217_REGULATOR("DCDC3", TPS65217_DCDC_3,
+ + 				tps65217_pmic_dcdc_ops, 64),
+ + 	TPS65217_REGULATOR("LDO1", TPS65217_LDO_1,
+ + 				tps65217_pmic_ldo1_ops, 16),
+ + 	TPS65217_REGULATOR("LDO2", TPS65217_LDO_2,
+ + 				tps65217_pmic_ldo234_ops, 64),
+ + 	TPS65217_REGULATOR("LDO3", TPS65217_LDO_3,
+ + 				tps65217_pmic_ldo234_ops, 32),
+ + 	TPS65217_REGULATOR("LDO4", TPS65217_LDO_4,
+ + 				tps65217_pmic_ldo234_ops, 32),
+ + };
+ + 
+ + static int __devinit tps65217_regulator_probe(struct platform_device *pdev)
+ + {
+ + 	struct regulator_dev *rdev;
+ + 	struct tps65217 *tps;
+ + 	struct tps_info *info = &tps65217_pmic_regs[pdev->id];
+ + 	const struct regulator_init_data *init_data = pdev->dev.platform_data;
+ + 	struct tps65217_rdelay *pd = init_data->driver_data;
+ + 
+ + 	/* Already set by core driver */
+ + 	tps = dev_to_tps65217(pdev->dev.parent);
+ + 	tps->info[pdev->id] = info;
+ + 
+ + 	if (pd)
+ + 		tps->info[pdev->id]->delay = pd->ramp_delay;
+ + 
+ + 	rdev = regulator_register(&regulators[pdev->id], &pdev->dev,
+ + 				  pdev->dev.platform_data, tps);
+ + 	if (IS_ERR(rdev))
+ + 		return PTR_ERR(rdev);
+ + 
+ + 	platform_set_drvdata(pdev, rdev);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static int __devexit tps65217_regulator_remove(struct platform_device *pdev)
+ + {
+ + 	struct regulator_dev *rdev = platform_get_drvdata(pdev);
+ + 
+ + 	platform_set_drvdata(pdev, NULL);
+ + 	regulator_unregister(rdev);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static struct platform_driver tps65217_regulator_driver = {
+ + 	.driver = {
+ + 		.name = "tps65217-pmic",
+ + 	},
+ + 	.probe = tps65217_regulator_probe,
+ + 	.remove = __devexit_p(tps65217_regulator_remove),
+ + };
+ + 
+ + static int __init tps65217_regulator_init(void)
+ + {
+ + 	return platform_driver_register(&tps65217_regulator_driver);
+ + }
+ + subsys_initcall(tps65217_regulator_init);
+ + 
+ + static void __exit tps65217_regulator_exit(void)
+ + {
+ + 	platform_driver_unregister(&tps65217_regulator_driver);
+ + }
+ + module_exit(tps65217_regulator_exit);
+ + 
+ + 
+ + MODULE_AUTHOR("AnilKumar Ch <anilkumar@ti.com>");
+ + MODULE_DESCRIPTION("TPS65217 voltage regulator driver");
+ + MODULE_ALIAS("platform:tps65217-pmic");
+ + MODULE_LICENSE("GPL v2");
+ diff -crN linux-3.2.1_o/drivers/rtc/Kconfig linux-3.2.1/drivers/rtc/Kconfig
+ *** linux-3.2.1_o/drivers/rtc/Kconfig	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/rtc/Kconfig	2014-11-25 13:19:16.037039520 +0900
+ ***************
+ *** 733,739 ****
+   
+   config RTC_DRV_OMAP
+   	tristate "TI OMAP1"
+ ! 	depends on ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_DAVINCI_DA8XX
+   	help
+   	  Say "yes" here to support the real time clock on TI OMAP1 and
+   	  DA8xx/OMAP-L13x chips.  This driver can also be built as a
+ --- 733,739 ----
+   
+   config RTC_DRV_OMAP
+   	tristate "TI OMAP1"
+ ! 	depends on ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_DAVINCI_DA8XX || SOC_OMAPAM33XX
+   	help
+   	  Say "yes" here to support the real time clock on TI OMAP1 and
+   	  DA8xx/OMAP-L13x chips.  This driver can also be built as a
+ diff -crN linux-3.2.1_o/drivers/rtc/rtc-omap.c linux-3.2.1/drivers/rtc/rtc-omap.c
+ *** linux-3.2.1_o/drivers/rtc/rtc-omap.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/rtc/rtc-omap.c	2014-11-25 13:19:16.087520986 +0900
+ ***************
+ *** 19,25 ****
+ --- 19,27 ----
+   #include <linux/delay.h>
+   #include <linux/rtc.h>
+   #include <linux/bcd.h>
+ + #include <linux/rtc/rtc-omap.h>
+   #include <linux/platform_device.h>
+ + #include <linux/pm_runtime.h>
+   
+   #include <asm/io.h>
+   
+ ***************
+ *** 38,43 ****
+ --- 40,47 ----
+    * the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment.
+    */
+   
+ + #define DRIVER_NAME			"omap_rtc"
+ + 
+   #define OMAP_RTC_BASE			0xfffb4800
+   
+   /* RTC registers */
+ ***************
+ *** 64,69 ****
+ --- 68,83 ----
+   #define OMAP_RTC_COMP_MSB_REG		0x50
+   #define OMAP_RTC_OSC_REG		0x54
+   
+ + #define OMAP_RTC_ALARM2_SECONDS_REG	0x80
+ + #define OMAP_RTC_ALARM2_MINUTES_REG	0x84
+ + #define OMAP_RTC_ALARM2_HOURS_REG	0x88
+ + #define OMAP_RTC_ALARM2_DAYS_REG	0x8c
+ + #define OMAP_RTC_ALARM2_MONTHS_REG	0x90
+ + #define OMAP_RTC_ALARM2_YEARS_REG	0x94
+ + #define OMAP_RTC_PMIC_REG		0x98
+ + 
+ + #define OMAP_RTC_IRQWAKEEN		0x7C
+ + 
+   /* OMAP_RTC_CTRL_REG bit fields: */
+   #define OMAP_RTC_CTRL_SPLIT		(1<<7)
+   #define OMAP_RTC_CTRL_DISABLE		(1<<6)
+ ***************
+ *** 85,93 ****
+ --- 99,125 ----
+   #define OMAP_RTC_STATUS_BUSY            (1<<0)
+   
+   /* OMAP_RTC_INTERRUPTS_REG bit fields: */
+ + #define OMAP_RTC_INTERRUPTS_IT_ALARM2	(1<<4)
+   #define OMAP_RTC_INTERRUPTS_IT_ALARM    (1<<3)
+   #define OMAP_RTC_INTERRUPTS_IT_TIMER    (1<<2)
+   
+ + /* OMAP_RTC_PMIC_REG bit fields: */
+ + #define OMAP_RTC_PMIC_POWER_EN_EN	(1<<16)
+ + 
+ + #define SHUTDOWN_TIME_SEC		2
+ + #define SECS_IN_MIN			60
+ + #define WAIT_AFTER			(SECS_IN_MIN - SHUTDOWN_TIME_SEC)
+ + #define WAIT_TIME_MS			(SHUTDOWN_TIME_SEC * 1000)
+ + 
+ + /* OMAP_RTC_IRQWAKEEN bit fields: */
+ + #define OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN    (1<<1)
+ + 
+ + /*
+ +  * Few RTC IP revision has special WAKEEN Register to enable Wakeup
+ +  * generation for event Alarm.
+ +  */
+ + #define	OMAP_RTC_HAS_IRQWAKEEN		0x2
+ + 
+   static void __iomem	*rtc_base;
+   
+   #define rtc_read(addr)		__raw_readb(rtc_base + (addr))
+ ***************
+ *** 274,279 ****
+ --- 306,358 ----
+   	return 0;
+   }
+   
+ + /*
+ +  * rtc_power_off: Set the pmic power off sequence. The RTC generates
+ +  * pmic_pwr_enable control, which can be used to control an external
+ +  * PMIC.
+ +  */
+ + static void rtc_power_off(void)
+ + {
+ + 	u32 val;
+ + 	struct rtc_time tm;
+ + 
+ + 	/* Set PMIC power enable */
+ + 	val = readl(rtc_base + OMAP_RTC_PMIC_REG);
+ + 	writel(val | OMAP_RTC_PMIC_POWER_EN_EN, rtc_base + OMAP_RTC_PMIC_REG);
+ + 
+ + 	/* Wait few seconds instead of rollover */
+ + 	do {
+ + 		omap_rtc_read_time(NULL, &tm);
+ + 		if (WAIT_AFTER <= tm.tm_sec)
+ + 			mdelay(WAIT_TIME_MS);
+ + 	} while (WAIT_AFTER <= tm.tm_sec);
+ + 
+ + 	/* Add shutdown time to the current value */
+ + 	tm.tm_sec += SHUTDOWN_TIME_SEC;
+ + 
+ + 	if (tm2bcd(&tm) < 0)
+ + 		return;
+ + 
+ + 	pr_info("System will go to power_off state in approx. %d secs\n",
+ + 			SHUTDOWN_TIME_SEC);
+ + 
+ + 	/* Set the ALARM2 time */
+ + 	rtc_write(tm.tm_sec, OMAP_RTC_ALARM2_SECONDS_REG);
+ + 	rtc_write(tm.tm_min, OMAP_RTC_ALARM2_MINUTES_REG);
+ + 	rtc_write(tm.tm_hour, OMAP_RTC_ALARM2_HOURS_REG);
+ + 	rtc_write(tm.tm_mday, OMAP_RTC_ALARM2_DAYS_REG);
+ + 	rtc_write(tm.tm_mon, OMAP_RTC_ALARM2_MONTHS_REG);
+ + 	rtc_write(tm.tm_year, OMAP_RTC_ALARM2_YEARS_REG);
+ + 
+ + 	/* Enable alarm2 interrupt */
+ + 	val = readl(rtc_base + OMAP_RTC_INTERRUPTS_REG);
+ + 	writel(val | OMAP_RTC_INTERRUPTS_IT_ALARM2,
+ + 				rtc_base + OMAP_RTC_INTERRUPTS_REG);
+ + 
+ + 	/* Do not allow to execute any other task */
+ + 	while (1);
+ + }
+ + 
+   static struct rtc_class_ops omap_rtc_ops = {
+   	.read_time	= omap_rtc_read_time,
+   	.set_time	= omap_rtc_set_time,
+ ***************
+ *** 285,292 ****
+ --- 364,383 ----
+   static int omap_rtc_alarm;
+   static int omap_rtc_timer;
+   
+ + static struct platform_device_id omap_rtc_devtype[] = {
+ + 	{
+ + 		.name	= DRIVER_NAME,
+ + 	}, {
+ + 		.name	= "am33xx-rtc",
+ + 		.driver_data = OMAP_RTC_HAS_IRQWAKEEN,
+ + 	},
+ + 	{},
+ + };
+ + MODULE_DEVICE_TABLE(platform, omap_rtc_devtype);
+ + 
+   static int __init omap_rtc_probe(struct platform_device *pdev)
+   {
+ + 	struct omap_rtc_pdata	*pdata = pdev->dev.platform_data;
+   	struct resource		*res, *mem;
+   	struct rtc_device	*rtc;
+   	u8			reg, new_ctrl;
+ ***************
+ *** 322,327 ****
+ --- 413,422 ----
+   		goto fail;
+   	}
+   
+ + 	/* Enable the clock/module so that we can access the registers */
+ + 	pm_runtime_enable(&pdev->dev);
+ + 	pm_runtime_get_sync(&pdev->dev);
+ + 
+   	rtc = rtc_device_register(pdev->name, &pdev->dev,
+   			&omap_rtc_ops, THIS_MODULE);
+   	if (IS_ERR(rtc)) {
+ ***************
+ *** 332,337 ****
+ --- 427,436 ----
+   	platform_set_drvdata(pdev, rtc);
+   	dev_set_drvdata(&rtc->dev, mem);
+   
+ + 	/* RTC power off */
+ + 	if (pdata && pdata->pm_off && !pm_power_off)
+ + 		pm_power_off = rtc_power_off;
+ + 
+   	/* clear pending irqs, and set 1/second periodic,
+   	 * which we'll use instead of update irqs
+   	 */
+ ***************
+ *** 391,396 ****
+ --- 490,498 ----
+   	if (reg != new_ctrl)
+   		rtc_write(new_ctrl, OMAP_RTC_CTRL_REG);
+   
+ + 	if (pdata->wakeup_capable)
+ + 		device_init_wakeup(&pdev->dev, 1);
+ + 
+   	return 0;
+   
+   fail2:
+ ***************
+ *** 398,403 ****
+ --- 500,507 ----
+   fail1:
+   	rtc_device_unregister(rtc);
+   fail0:
+ + 	pm_runtime_put_sync(&pdev->dev);
+ + 	pm_runtime_disable(&pdev->dev);
+   	iounmap(rtc_base);
+   fail:
+   	release_mem_region(mem->start, resource_size(mem));
+ ***************
+ *** 420,425 ****
+ --- 524,534 ----
+   		free_irq(omap_rtc_alarm, rtc);
+   
+   	rtc_device_unregister(rtc);
+ + 
+ + 	/* Disable the clock/module */
+ + 	pm_runtime_put_sync(&pdev->dev);
+ + 	pm_runtime_disable(&pdev->dev);
+ + 
+   	iounmap(rtc_base);
+   	release_mem_region(mem->start, resource_size(mem));
+   	return 0;
+ ***************
+ *** 431,456 ****
+   
+   static int omap_rtc_suspend(struct platform_device *pdev, pm_message_t state)
+   {
+   	irqstat = rtc_read(OMAP_RTC_INTERRUPTS_REG);
+   
+   	/* FIXME the RTC alarm is not currently acting as a wakeup event
+   	 * source, and in fact this enable() call is just saving a flag
+   	 * that's never used...
+   	 */
+ ! 	if (device_may_wakeup(&pdev->dev))
+   		enable_irq_wake(omap_rtc_alarm);
+ ! 	else
+   		rtc_write(0, OMAP_RTC_INTERRUPTS_REG);
+   
+   	return 0;
+   }
+   
+   static int omap_rtc_resume(struct platform_device *pdev)
+   {
+ ! 	if (device_may_wakeup(&pdev->dev))
+   		disable_irq_wake(omap_rtc_alarm);
+ ! 	else
+   		rtc_write(irqstat, OMAP_RTC_INTERRUPTS_REG);
+   	return 0;
+   }
+   
+ --- 540,593 ----
+   
+   static int omap_rtc_suspend(struct platform_device *pdev, pm_message_t state)
+   {
+ + 	u8 irqwake_stat;
+ + 	const struct platform_device_id *id_entry =
+ + 				platform_get_device_id(pdev);
+ + 
+   	irqstat = rtc_read(OMAP_RTC_INTERRUPTS_REG);
+   
+   	/* FIXME the RTC alarm is not currently acting as a wakeup event
+   	 * source, and in fact this enable() call is just saving a flag
+   	 * that's never used...
+   	 */
+ ! 	if (device_may_wakeup(&pdev->dev)) {
+   		enable_irq_wake(omap_rtc_alarm);
+ ! 
+ ! 		if (id_entry->driver_data & OMAP_RTC_HAS_IRQWAKEEN) {
+ ! 			irqwake_stat = rtc_read(OMAP_RTC_IRQWAKEEN);
+ ! 			irqwake_stat |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
+ ! 			rtc_write(irqwake_stat, OMAP_RTC_IRQWAKEEN);
+ ! 		}
+ ! 	} else {
+   		rtc_write(0, OMAP_RTC_INTERRUPTS_REG);
+ + 	}
+ + 
+ + 	/* Disable the clock/module */
+ + 	pm_runtime_put_sync(&pdev->dev);
+   
+   	return 0;
+   }
+   
+   static int omap_rtc_resume(struct platform_device *pdev)
+   {
+ ! 	u8 irqwake_stat;
+ ! 	const struct platform_device_id *id_entry =
+ ! 				platform_get_device_id(pdev);
+ ! 
+ ! 	/* Enable the clock/module so that we can access the registers */
+ ! 	pm_runtime_get_sync(&pdev->dev);
+ ! 
+ ! 	if (device_may_wakeup(&pdev->dev)) {
+   		disable_irq_wake(omap_rtc_alarm);
+ ! 
+ ! 		if (id_entry->driver_data & OMAP_RTC_HAS_IRQWAKEEN) {
+ ! 			irqwake_stat = rtc_read(OMAP_RTC_IRQWAKEEN);
+ ! 			irqwake_stat &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
+ ! 			rtc_write(irqwake_stat, OMAP_RTC_IRQWAKEEN);
+ ! 		}
+ ! 	} else {
+   		rtc_write(irqstat, OMAP_RTC_INTERRUPTS_REG);
+ + 	}
+   	return 0;
+   }
+   
+ ***************
+ *** 471,479 ****
+   	.resume		= omap_rtc_resume,
+   	.shutdown	= omap_rtc_shutdown,
+   	.driver		= {
+ ! 		.name	= "omap_rtc",
+   		.owner	= THIS_MODULE,
+   	},
+   };
+   
+   static int __init rtc_init(void)
+ --- 608,617 ----
+   	.resume		= omap_rtc_resume,
+   	.shutdown	= omap_rtc_shutdown,
+   	.driver		= {
+ ! 		.name	= DRIVER_NAME,
+   		.owner	= THIS_MODULE,
+   	},
+ + 	.id_table	= omap_rtc_devtype,
+   };
+   
+   static int __init rtc_init(void)
+ diff -crN linux-3.2.1_o/drivers/spi/Kconfig linux-3.2.1/drivers/spi/Kconfig
+ *** linux-3.2.1_o/drivers/spi/Kconfig	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/spi/Kconfig	2014-11-25 13:19:16.104003867 +0900
+ ***************
+ *** 232,238 ****
+   
+   config SPI_OMAP24XX
+   	tristate "McSPI driver for OMAP"
+ ! 	depends on ARCH_OMAP2PLUS
+   	help
+   	  SPI master controller for OMAP24XX and later Multichannel SPI
+   	  (McSPI) modules.
+ --- 232,238 ----
+   
+   config SPI_OMAP24XX
+   	tristate "McSPI driver for OMAP"
+ ! 	depends on ARCH_OMAP2PLUS || MACH_CKB_3352
+   	help
+   	  SPI master controller for OMAP24XX and later Multichannel SPI
+   	  (McSPI) modules.
+ diff -crN linux-3.2.1_o/drivers/spi/spi-omap2-mcspi.c linux-3.2.1/drivers/spi/spi-omap2-mcspi.c
+ *** linux-3.2.1_o/drivers/spi/spi-omap2-mcspi.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/spi/spi-omap2-mcspi.c	2014-11-25 13:19:16.112275177 +0900
+ ***************
+ *** 40,45 ****
+ --- 40,46 ----
+   #include <plat/dma.h>
+   #include <plat/clock.h>
+   #include <plat/mcspi.h>
+ + #include <mach/edma.h>
+   
+   #define OMAP2_MCSPI_MAX_FREQ		48000000
+   
+ ***************
+ *** 101,106 ****
+ --- 102,108 ----
+   
+   	struct completion dma_tx_completion;
+   	struct completion dma_rx_completion;
+ + 	int dummy_param_slot;
+   };
+   
+   /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
+ ***************
+ *** 108,114 ****
+    */
+   #define DMA_MIN_BYTES			160
+   
+ - 
+   struct omap2_mcspi {
+   	struct work_struct	work;
+   	/* lock protects queue and registers */
+ --- 110,115 ----
+ ***************
+ *** 303,308 ****
+ --- 304,310 ----
+   	u8			* rx;
+   	const u8		* tx;
+   	void __iomem		*chstat_reg;
+ + 	struct edmacc_param	param;
+   
+   	mcspi = spi_master_get_devdata(spi->master);
+   	mcspi_dma = &mcspi->dma_channels[spi->chip_select];
+ ***************
+ *** 332,368 ****
+   	}
+   
+   	if (tx != NULL) {
+ ! 		omap_set_dma_transfer_params(mcspi_dma->dma_tx_channel,
+ ! 				data_type, element_count, 1,
+ ! 				OMAP_DMA_SYNC_ELEMENT,
+ ! 				mcspi_dma->dma_tx_sync_dev, 0);
+ ! 
+ ! 		omap_set_dma_dest_params(mcspi_dma->dma_tx_channel, 0,
+ ! 				OMAP_DMA_AMODE_CONSTANT,
+ ! 				tx_reg, 0, 0);
+ ! 
+ ! 		omap_set_dma_src_params(mcspi_dma->dma_tx_channel, 0,
+ ! 				OMAP_DMA_AMODE_POST_INC,
+ ! 				xfer->tx_dma, 0, 0);
+   	}
+   
+   	if (rx != NULL) {
+   		elements = element_count - 1;
+   		if (l & OMAP2_MCSPI_CHCONF_TURBO)
+   			elements--;
+   
+ ! 		omap_set_dma_transfer_params(mcspi_dma->dma_rx_channel,
+ ! 				data_type, elements, 1,
+ ! 				OMAP_DMA_SYNC_ELEMENT,
+ ! 				mcspi_dma->dma_rx_sync_dev, 1);
+ ! 
+ ! 		omap_set_dma_src_params(mcspi_dma->dma_rx_channel, 0,
+ ! 				OMAP_DMA_AMODE_CONSTANT,
+ ! 				rx_reg, 0, 0);
+ ! 
+ ! 		omap_set_dma_dest_params(mcspi_dma->dma_rx_channel, 0,
+ ! 				OMAP_DMA_AMODE_POST_INC,
+ ! 				xfer->rx_dma, 0, 0);
+   	}
+   
+   	if (tx != NULL) {
+ --- 334,390 ----
+   	}
+   
+   	if (tx != NULL) {
+ ! 		int a_cnt, b_cnt, c_cnt, b_cntrld;
+ ! 
+ ! 		a_cnt    = 1 << data_type;
+ ! 		b_cnt    = 1;
+ ! 		c_cnt    = element_count / 256;
+ ! 		b_cntrld = SZ_64K - 1;
+ ! 
+ ! 		param.opt          = TCINTEN |
+ ! 			EDMA_TCC(mcspi_dma->dma_tx_channel) | SYNCDIM ;
+ ! 		param.src          = xfer->tx_dma;
+ ! 		param.a_b_cnt      = a_cnt | b_cnt << 16;
+ ! 		param.dst          = tx_reg;
+ ! 		param.src_dst_bidx = a_cnt;
+ ! 		param.link_bcntrld = b_cntrld << 16;
+ ! 		param.src_dst_cidx = a_cnt;
+ ! 		param.ccnt         = element_count;
+ ! 		edma_write_slot(mcspi_dma->dma_tx_channel, &param);
+ ! 		edma_link(mcspi_dma->dma_tx_channel,
+ ! 				mcspi_dma->dummy_param_slot);
+   	}
+   
+   	if (rx != NULL) {
+ + 		int a_cnt, b_cnt, c_cnt, b_cntrld;
+ + 
+ + 		a_cnt    = 1 << data_type;
+ + 		c_cnt    = element_count / (SZ_64K - 1);
+ + 		b_cnt    = element_count - c_cnt * (SZ_64K - 1);
+ + 		b_cntrld = SZ_64K - 1;
+ + 
+ + 		if (b_cnt)
+ + 			c_cnt++;
+ + 		else
+ + 			b_cnt = SZ_64K - 1;
+ + 
+   		elements = element_count - 1;
+   		if (l & OMAP2_MCSPI_CHCONF_TURBO)
+   			elements--;
+   
+ ! 		param.opt          = TCINTEN |
+ ! 			EDMA_TCC(mcspi_dma->dma_rx_channel);
+ ! 		param.src          = rx_reg;
+ ! 		param.a_b_cnt      = a_cnt | b_cnt << 16;
+ ! 		param.dst          = xfer->rx_dma;
+ ! 		param.src_dst_bidx = a_cnt << 16;
+ ! 		param.link_bcntrld = b_cntrld << 16;
+ ! 		param.src_dst_cidx = a_cnt << 16;
+ ! 		param.ccnt         = c_cnt;
+ ! 		edma_write_slot(mcspi_dma->dma_rx_channel, &param);
+ ! 		edma_link(mcspi_dma->dma_rx_channel,
+ ! 				mcspi_dma->dummy_param_slot);
+ ! 
+   	}
+   
+   	if (tx != NULL) {
+ ***************
+ *** 419,441 ****
+   			}
+   		}
+   
+ - 		if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
+ - 				& OMAP2_MCSPI_CHSTAT_RXS)) {
+ - 			u32 w;
+ - 
+ - 			w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
+ - 			if (word_len <= 8)
+ - 				((u8 *)xfer->rx_buf)[elements] = w;
+ - 			else if (word_len <= 16)
+ - 				((u16 *)xfer->rx_buf)[elements] = w;
+ - 			else /* word_len <= 32 */
+ - 				((u32 *)xfer->rx_buf)[elements] = w;
+ - 		} else {
+ - 			dev_err(&spi->dev, "DMA RX last word empty");
+ - 			count -= (word_len <= 8)  ? 1 :
+ - 				 (word_len <= 16) ? 2 :
+ - 			       /* word_len <= 32 */ 4;
+ - 		}
+   		omap2_mcspi_set_enable(spi, 1);
+   	}
+   	return count;
+ --- 441,446 ----
+ ***************
+ *** 718,730 ****
+   	struct omap2_mcspi	*mcspi;
+   	struct omap2_mcspi_dma	*mcspi_dma;
+   
+   	mcspi = spi_master_get_devdata(spi->master);
+   	mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
+   
+   	complete(&mcspi_dma->dma_rx_completion);
+   
+ - 	/* We must disable the DMA RX request */
+ - 	omap2_mcspi_set_dma_req(spi, 1, 0);
+   }
+   
+   static void omap2_mcspi_dma_tx_callback(int lch, u16 ch_status, void *data)
+ --- 723,735 ----
+   	struct omap2_mcspi	*mcspi;
+   	struct omap2_mcspi_dma	*mcspi_dma;
+   
+ + 	/* We must disable the DMA RX request */
+ + 	omap2_mcspi_set_dma_req(spi, 1, 0);
+   	mcspi = spi_master_get_devdata(spi->master);
+   	mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
+   
+   	complete(&mcspi_dma->dma_rx_completion);
+   
+   }
+   
+   static void omap2_mcspi_dma_tx_callback(int lch, u16 ch_status, void *data)
+ ***************
+ *** 733,745 ****
+   	struct omap2_mcspi	*mcspi;
+   	struct omap2_mcspi_dma	*mcspi_dma;
+   
+   	mcspi = spi_master_get_devdata(spi->master);
+   	mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
+   
+   	complete(&mcspi_dma->dma_tx_completion);
+   
+ - 	/* We must disable the DMA TX request */
+ - 	omap2_mcspi_set_dma_req(spi, 0, 0);
+   }
+   
+   static int omap2_mcspi_request_dma(struct spi_device *spi)
+ --- 738,750 ----
+   	struct omap2_mcspi	*mcspi;
+   	struct omap2_mcspi_dma	*mcspi_dma;
+   
+ + 	/* We must disable the DMA TX request */
+ + 	omap2_mcspi_set_dma_req(spi, 0, 0);
+   	mcspi = spi_master_get_devdata(spi->master);
+   	mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
+   
+   	complete(&mcspi_dma->dma_tx_completion);
+   
+   }
+   
+   static int omap2_mcspi_request_dma(struct spi_device *spi)
+ ***************
+ *** 747,752 ****
+ --- 752,758 ----
+   	struct spi_master	*master = spi->master;
+   	struct omap2_mcspi	*mcspi;
+   	struct omap2_mcspi_dma	*mcspi_dma;
+ + 	int			ret = 0;
+   
+   	mcspi = spi_master_get_devdata(master);
+   	mcspi_dma = mcspi->dma_channels + spi->chip_select;
+ ***************
+ *** 766,771 ****
+ --- 772,789 ----
+   		dev_err(&spi->dev, "no TX DMA channel for McSPI\n");
+   		return -EAGAIN;
+   	}
+ + 	ret = edma_alloc_slot(EDMA_CTLR(mcspi_dma->dma_tx_channel),
+ + 			EDMA_SLOT_ANY);
+ + 
+ + 	if (ret < 0) {
+ + 		pr_err("Unable to request SPI TX DMA param slot\n");
+ + 		ret = -EAGAIN;
+ + 		return ret;
+ + 	}
+ + 
+ + 	mcspi_dma->dummy_param_slot = ret;
+ + 	edma_link(mcspi_dma->dummy_param_slot,
+ + 			mcspi_dma->dummy_param_slot);
+   
+   	init_completion(&mcspi_dma->dma_rx_completion);
+   	init_completion(&mcspi_dma->dma_tx_completion);
+ ***************
+ *** 1114,1120 ****
+   	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+   	if (r == NULL) {
+   		status = -ENODEV;
+ ! 		goto err1;
+   	}
+   
+   	r->start += pdata->regs_offset;
+ --- 1132,1138 ----
+   	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+   	if (r == NULL) {
+   		status = -ENODEV;
+ ! 		goto free_master;
+   	}
+   
+   	r->start += pdata->regs_offset;
+ ***************
+ *** 1123,1136 ****
+   	if (!request_mem_region(r->start, resource_size(r),
+   				dev_name(&pdev->dev))) {
+   		status = -EBUSY;
+ ! 		goto err1;
+   	}
+   
+   	mcspi->base = ioremap(r->start, resource_size(r));
+   	if (!mcspi->base) {
+   		dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
+   		status = -ENOMEM;
+ ! 		goto err2;
+   	}
+   
+   	mcspi->dev = &pdev->dev;
+ --- 1141,1154 ----
+   	if (!request_mem_region(r->start, resource_size(r),
+   				dev_name(&pdev->dev))) {
+   		status = -EBUSY;
+ ! 		goto free_master;
+   	}
+   
+   	mcspi->base = ioremap(r->start, resource_size(r));
+   	if (!mcspi->base) {
+   		dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
+   		status = -ENOMEM;
+ ! 		goto release_region;
+   	}
+   
+   	mcspi->dev = &pdev->dev;
+ ***************
+ *** 1145,1151 ****
+   			GFP_KERNEL);
+   
+   	if (mcspi->dma_channels == NULL)
+ ! 		goto err2;
+   
+   	for (i = 0; i < master->num_chipselect; i++) {
+   		char dma_ch_name[14];
+ --- 1163,1169 ----
+   			GFP_KERNEL);
+   
+   	if (mcspi->dma_channels == NULL)
+ ! 		goto unmap_io;
+   
+   	for (i = 0; i < master->num_chipselect; i++) {
+   		char dma_ch_name[14];
+ ***************
+ *** 1175,1199 ****
+   		mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
+   	}
+   
+   	pm_runtime_enable(&pdev->dev);
+   
+   	if (status || omap2_mcspi_master_setup(mcspi) < 0)
+ ! 		goto err3;
+   
+   	status = spi_register_master(master);
+   	if (status < 0)
+ ! 		goto err4;
+   
+   	return status;
+   
+ ! err4:
+   	spi_master_put(master);
+ ! err3:
+   	kfree(mcspi->dma_channels);
+ ! err2:
+ ! 	release_mem_region(r->start, resource_size(r));
+   	iounmap(mcspi->base);
+ ! err1:
+   	return status;
+   }
+   
+ --- 1193,1226 ----
+   		mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
+   	}
+   
+ + 	if (status < 0)
+ + 		goto dma_chnl_free;
+ + 
+   	pm_runtime_enable(&pdev->dev);
+   
+   	if (status || omap2_mcspi_master_setup(mcspi) < 0)
+ ! 		goto diable_pm;
+   
+   	status = spi_register_master(master);
+   	if (status < 0)
+ ! 		goto err_spi_register;
+   
+   	return status;
+   
+ ! err_spi_register:
+   	spi_master_put(master);
+ ! diable_pm:
+ ! 	pm_runtime_put_sync(&pdev->dev);
+ ! 	pm_runtime_disable(&pdev->dev);
+ ! dma_chnl_free:
+   	kfree(mcspi->dma_channels);
+ ! unmap_io:
+   	iounmap(mcspi->base);
+ ! release_region:
+ ! 	release_mem_region(r->start, resource_size(r));
+ ! free_master:
+ ! 	kfree(master);
+ ! 	platform_set_drvdata(pdev, NULL);
+   	return status;
+   }
+   
+ ***************
+ *** 1210,1222 ****
+   	dma_channels = mcspi->dma_channels;
+   
+   	omap2_mcspi_disable_clocks(mcspi);
+   	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+   	release_mem_region(r->start, resource_size(r));
+   
+ - 	base = mcspi->base;
+   	spi_unregister_master(master);
+ ! 	iounmap(base);
+ ! 	kfree(dma_channels);
+   
+   	return 0;
+   }
+ --- 1237,1252 ----
+   	dma_channels = mcspi->dma_channels;
+   
+   	omap2_mcspi_disable_clocks(mcspi);
+ + 	pm_runtime_disable(&pdev->dev);
+ + 	kfree(dma_channels);
+ + 	base = mcspi->base;
+ + 	iounmap(base);
+ + 
+   	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+   	release_mem_region(r->start, resource_size(r));
+   
+   	spi_unregister_master(master);
+ ! 	platform_set_drvdata(pdev, NULL);
+   
+   	return 0;
+   }
+ diff -crN linux-3.2.1_o/drivers/staging/iio/adc/Kconfig linux-3.2.1/drivers/staging/iio/adc/Kconfig
+ *** linux-3.2.1_o/drivers/staging/iio/adc/Kconfig	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/staging/iio/adc/Kconfig	2014-11-25 13:19:16.129026845 +0900
+ ***************
+ *** 193,196 ****
+ --- 193,204 ----
+   	  Say yes here to include ring buffer support in the MAX1363
+   	  ADC driver.
+   
+ + config TI_ADC
+ + 	tristate "TI's ADC driver"
+ + 	help
+ + 	  Say yes here to build support for Texas Instruments ADC
+ + 	  driver which is also a MFD.
+ + 	  To compile this driver as a module, choose M here: the
+ + 	  module will be called ti_adc.
+ + 
+   endmenu
+ diff -crN linux-3.2.1_o/drivers/staging/iio/adc/Makefile linux-3.2.1/drivers/staging/iio/adc/Makefile
+ *** linux-3.2.1_o/drivers/staging/iio/adc/Makefile	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/staging/iio/adc/Makefile	2014-11-25 13:19:16.131055799 +0900
+ ***************
+ *** 37,39 ****
+ --- 37,40 ----
+   obj-$(CONFIG_ADT7310) += adt7310.o
+   obj-$(CONFIG_ADT7410) += adt7410.o
+   obj-$(CONFIG_AD7280) += ad7280a.o
+ + obj-$(CONFIG_TI_ADC) += ti_adc.o
+ diff -crN linux-3.2.1_o/drivers/staging/iio/adc/ti_adc.c linux-3.2.1/drivers/staging/iio/adc/ti_adc.c
+ *** linux-3.2.1_o/drivers/staging/iio/adc/ti_adc.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/drivers/staging/iio/adc/ti_adc.c	2014-11-25 13:19:16.140497307 +0900
+ ***************
+ *** 0 ****
+ --- 1,542 ----
+ + /*
+ +  * TI ADC MFD driver
+ +  *
+ +  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #include <linux/init.h>
+ + #include <linux/kernel.h>
+ + #include <linux/err.h>
+ + #include <linux/module.h>
+ + #include <linux/slab.h>
+ + #include <linux/interrupt.h>
+ + #include <linux/platform_device.h>
+ + #include <linux/io.h>
+ + #include <linux/sched.h>
+ + 
+ + #include "../iio.h"
+ + #include "../sysfs.h"
+ + #include "../buffer_generic.h"
+ + #include "../ring_sw.h"
+ + 
+ + #include <linux/mfd/ti_tscadc.h>
+ + #include <linux/platform_data/ti_adc.h>
+ + 
+ + struct adc_device {
+ + 	struct ti_tscadc_dev	*mfd_tscadc;
+ + 	struct iio_dev		*idev;
+ + 	struct work_struct	poll_work;
+ + 	wait_queue_head_t	wq_data_avail;
+ + 	int			channels;
+ + 	int			irq;
+ + 	bool			is_continuous_mode;
+ + 	u16			*buffer;
+ + };
+ + 
+ + static unsigned int adc_readl(struct adc_device *adc, unsigned int reg)
+ + {
+ + 	return readl(adc->mfd_tscadc->tscadc_base + reg);
+ + }
+ + 
+ + static void adc_writel(struct adc_device *adc, unsigned int reg,
+ + 					unsigned int val)
+ + {
+ + 	writel(val, adc->mfd_tscadc->tscadc_base + reg);
+ + }
+ + 
+ + static void adc_step_config(struct adc_device *adc_dev, bool mode)
+ + {
+ + 	unsigned int    stepconfig;
+ + 	int i, channels = 0, steps;
+ + 
+ + 	/*
+ + 	 * There are 16 configurable steps and 8 analog input
+ + 	 * lines available which are shared between Touchscreen and ADC.
+ + 	 *
+ + 	 * Steps backwards i.e. from 16 towards 0 are used by ADC
+ + 	 * depending on number of input lines needed.
+ + 	 * Channel would represent which analog input
+ + 	 * needs to be given to ADC to digitalize data.
+ + 	 */
+ + 
+ + 	steps = TOTAL_STEPS - adc_dev->channels;
+ + 	channels = TOTAL_CHANNELS - adc_dev->channels;
+ + 
+ + 	if (mode == 0)
+ + 		stepconfig = TSCADC_STEPCONFIG_AVG_16 | TSCADC_STEPCONFIG_FIFO1;
+ + 	else
+ + 		stepconfig = TSCADC_STEPCONFIG_AVG_16 | TSCADC_STEPCONFIG_FIFO1
+ + 			| TSCADC_STEPCONFIG_MODE_SWCNT;
+ + 
+ + 	for (i = (steps + 1); i <= TOTAL_STEPS; i++) {
+ + 		adc_writel(adc_dev, TSCADC_REG_STEPCONFIG(i),
+ + 				stepconfig | TSCADC_STEPCONFIG_INP(channels));
+ + 		adc_writel(adc_dev, TSCADC_REG_STEPDELAY(i),
+ + 				TSCADC_STEPCONFIG_OPENDLY);
+ + 		channels++;
+ + 	}
+ + }
+ + 
+ + static ssize_t tiadc_show_mode(struct device *dev,
+ + 		struct device_attribute *attr, char *buf)
+ + {
+ + 	struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ + 	struct adc_device *adc_dev = iio_priv(indio_dev);
+ + 	unsigned int tmp;
+ + 
+ + 	tmp = adc_readl(adc_dev, TSCADC_REG_STEPCONFIG(TOTAL_STEPS));
+ + 	tmp &= TSCADC_STEPCONFIG_MODE(1);
+ + 
+ + 	if (tmp == 0x00)
+ + 		return sprintf(buf, "oneshot\n");
+ + 	else if (tmp == 0x01)
+ + 		return sprintf(buf, "continuous\n");
+ + 	else
+ + 		return sprintf(buf, "Operation mode unknown\n");
+ + }
+ + 
+ + static ssize_t tiadc_set_mode(struct device *dev,
+ + 		struct device_attribute *attr, const char *buf, size_t count)
+ + {
+ + 	struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ + 	struct adc_device *adc_dev = iio_priv(indio_dev);
+ + 	unsigned int config;
+ + 
+ + 	config = adc_readl(adc_dev, TSCADC_REG_CTRL);
+ + 	config &= ~(TSCADC_CNTRLREG_TSCSSENB);
+ + 	adc_writel(adc_dev, TSCADC_REG_CTRL, config);
+ + 
+ + 	if (!strncmp(buf, "oneshot", 7))
+ + 		adc_dev->is_continuous_mode = false;
+ + 	else if (!strncmp(buf, "continuous", 10))
+ + 		adc_dev->is_continuous_mode = true;
+ + 	else {
+ + 		dev_err(dev, "Operational mode unknown\n");
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	adc_step_config(adc_dev, adc_dev->is_continuous_mode);
+ + 
+ + 	config = adc_readl(adc_dev, TSCADC_REG_CTRL);
+ + 	adc_writel(adc_dev, TSCADC_REG_CTRL,
+ + 			(config | TSCADC_CNTRLREG_TSCSSENB));
+ + 	return count;
+ + }
+ + 
+ + static IIO_DEVICE_ATTR(mode, S_IRUGO | S_IWUSR, tiadc_show_mode,
+ + 		tiadc_set_mode, 0);
+ + 
+ + static struct attribute *tiadc_attributes[] = {
+ + 	&iio_dev_attr_mode.dev_attr.attr,
+ + 	NULL,
+ + };
+ + 
+ + static const struct attribute_group tiadc_attribute_group = {
+ + 	.attrs = tiadc_attributes,
+ + };
+ + 
+ + static irqreturn_t tiadc_irq(int irq, void *private)
+ + {
+ + 	struct iio_dev *idev = private;
+ + 	struct adc_device *adc_dev = iio_priv(idev);
+ + 	unsigned int status, config;
+ + 
+ + 	status = adc_readl(adc_dev, TSCADC_REG_IRQSTATUS);
+ + 	if (status & TSCADC_IRQENB_FIFO1OVRRUN) {
+ + 		config = adc_readl(adc_dev, TSCADC_REG_CTRL);
+ + 		config &= ~(TSCADC_CNTRLREG_TSCSSENB);
+ + 		adc_writel(adc_dev, TSCADC_REG_CTRL, config);
+ + 
+ + 		adc_writel(adc_dev, TSCADC_REG_IRQSTATUS,
+ + 				TSCADC_IRQENB_FIFO1OVRRUN |
+ + 				TSCADC_IRQENB_FIFO1UNDRFLW |
+ + 				TSCADC_IRQENB_FIFO1THRES);
+ + 
+ + 		adc_writel(adc_dev, TSCADC_REG_CTRL,
+ + 			(config | TSCADC_CNTRLREG_TSCSSENB));
+ + 		return IRQ_HANDLED;
+ + 	} else if (status & TSCADC_IRQENB_FIFO1THRES) {
+ + 		adc_writel(adc_dev, TSCADC_REG_IRQCLR,
+ + 				TSCADC_IRQENB_FIFO1THRES);
+ + 
+ + 		if (iio_buffer_enabled(idev)) {
+ + 			if (!work_pending(&adc_dev->poll_work))
+ + 				schedule_work(&adc_dev->poll_work);
+ + 		} else {
+ + 			wake_up_interruptible(&adc_dev->wq_data_avail);
+ + 		}
+ + 		return IRQ_HANDLED;
+ + 	} else {
+ + 		return IRQ_NONE;
+ + 	}
+ + }
+ + 
+ + static void tiadc_poll_handler(struct work_struct *work_s)
+ + {
+ + 	struct adc_device *adc_dev =
+ + 		container_of(work_s, struct adc_device, poll_work);
+ + 	struct iio_dev *idev = iio_priv_to_dev(adc_dev);
+ + 	struct iio_buffer *buffer = idev->buffer;
+ + 	unsigned int fifo1count, readx1;
+ + 	int i;
+ + 	u32 *iBuf;
+ + 
+ + 	fifo1count = adc_readl(adc_dev, TSCADC_REG_FIFO1CNT);
+ + 	if (fifo1count * sizeof(u32) <
+ + 				buffer->access->get_bytes_per_datum(buffer)) {
+ + 		dev_err(adc_dev->mfd_tscadc->dev, "%s: Short FIFO event\n",
+ + 								__func__);
+ + 		goto out;
+ + 	}
+ + 
+ + 	iBuf = kmalloc(fifo1count * sizeof(u32), GFP_KERNEL);
+ + 	if (iBuf == NULL)
+ + 		goto out;
+ + 
+ + 	for (i = 0; i < fifo1count; i++) {
+ + 		readx1 = adc_readl(adc_dev, TSCADC_REG_FIFO1);
+ + 		readx1 &= TSCADC_FIFOREAD_DATA_MASK;
+ + 		iBuf[i] = readx1;
+ + 	}
+ + 
+ + 	buffer->access->store_to(buffer, (u8 *) iBuf, iio_get_time_ns());
+ + 	kfree(iBuf);
+ + 
+ + out:
+ + 	adc_writel(adc_dev, TSCADC_REG_IRQSTATUS,
+ + 				TSCADC_IRQENB_FIFO1THRES);
+ + 	adc_writel(adc_dev, TSCADC_REG_IRQENABLE,
+ + 				TSCADC_IRQENB_FIFO1THRES);
+ + }
+ + 
+ + static int tiadc_buffer_preenable(struct iio_dev *idev)
+ + {
+ + 	struct iio_buffer *buffer = idev->buffer;
+ + 
+ + 	buffer->access->set_bytes_per_datum(buffer, 16);
+ + 	return 0;
+ + }
+ + 
+ + static int tiadc_buffer_postenable(struct iio_dev *idev)
+ + {
+ + 	struct adc_device *adc_dev = iio_priv(idev);
+ + 	struct iio_buffer *buffer = idev->buffer;
+ + 	unsigned int enb, config;
+ + 	int stepnum;
+ + 	u8 bit;
+ + 
+ + 	if (!adc_dev->is_continuous_mode) {
+ + 		pr_info("Data cannot be read continuously in one shot mode\n");
+ + 		return -EINVAL;
+ + 	} else {
+ + 
+ + 		config = adc_readl(adc_dev, TSCADC_REG_CTRL);
+ + 		adc_writel(adc_dev, TSCADC_REG_CTRL,
+ + 					config & ~TSCADC_CNTRLREG_TSCSSENB);
+ + 		adc_writel(adc_dev, TSCADC_REG_CTRL,
+ + 					config | TSCADC_CNTRLREG_TSCSSENB);
+ + 
+ + 
+ + 		adc_writel(adc_dev, TSCADC_REG_IRQSTATUS,
+ + 				TSCADC_IRQENB_FIFO1THRES |
+ + 				TSCADC_IRQENB_FIFO1OVRRUN |
+ + 				TSCADC_IRQENB_FIFO1UNDRFLW);
+ + 		adc_writel(adc_dev, TSCADC_REG_IRQENABLE,
+ + 				TSCADC_IRQENB_FIFO1THRES |
+ + 				TSCADC_IRQENB_FIFO1OVRRUN);
+ + 
+ + 		adc_writel(adc_dev, TSCADC_REG_SE, 0x00);
+ + 		for_each_set_bit(bit, buffer->scan_mask,
+ + 				adc_dev->channels) {
+ + 			struct iio_chan_spec const *chan = idev->channels + bit;
+ + 			/*
+ + 			 * There are a total of 16 steps available
+ + 			 * that are shared between ADC and touchscreen.
+ + 			 * We start configuring from step 16 to 0 incase of
+ + 			 * ADC. Hence the relation between input channel
+ + 			 * and step for ADC would be as below.
+ + 			 */
+ + 			stepnum = chan->channel + 9;
+ + 			enb = adc_readl(adc_dev, TSCADC_REG_SE);
+ + 			enb |= (1 << stepnum);
+ + 			adc_writel(adc_dev, TSCADC_REG_SE, enb);
+ + 		}
+ + 		return 0;
+ + 	}
+ + }
+ + 
+ + static int tiadc_buffer_postdisable(struct iio_dev *idev)
+ + {
+ + 	struct adc_device *adc_dev = iio_priv(idev);
+ + 
+ + 	adc_writel(adc_dev, TSCADC_REG_IRQCLR, (TSCADC_IRQENB_FIFO1THRES |
+ + 				TSCADC_IRQENB_FIFO1OVRRUN |
+ + 				TSCADC_IRQENB_FIFO1UNDRFLW));
+ + 	adc_writel(adc_dev, TSCADC_REG_SE, TSCADC_STPENB_STEPENB_TC);
+ + 	return 0;
+ + }
+ + 
+ + static const struct iio_buffer_setup_ops tiadc_swring_setup_ops = {
+ + 	.preenable = &tiadc_buffer_preenable,
+ + 	.postenable = &tiadc_buffer_postenable,
+ + 	.postdisable = &tiadc_buffer_postdisable,
+ + };
+ + 
+ + static int tiadc_config_sw_ring(struct iio_dev *idev)
+ + {
+ + 	struct adc_device *adc_dev = iio_priv(idev);
+ + 	int ret;
+ + 
+ + 	idev->buffer = iio_sw_rb_allocate(idev);
+ + 	if (!idev->buffer)
+ + 		ret = -ENOMEM;
+ + 
+ + 	idev->buffer->access = &ring_sw_access_funcs;
+ + 	idev->buffer->setup_ops = &tiadc_swring_setup_ops;
+ + 
+ + 	INIT_WORK(&adc_dev->poll_work, &tiadc_poll_handler);
+ + 
+ + 	idev->modes |= INDIO_BUFFER_HARDWARE;
+ + 	return 0;
+ + }
+ + 
+ + static int tiadc_channel_init(struct iio_dev *idev, struct adc_device *adc_dev)
+ + {
+ + 	struct iio_chan_spec *chan_array;
+ + 	int i, channels;
+ + 
+ + 	idev->num_channels = adc_dev->channels;
+ + 	chan_array = kcalloc(idev->num_channels, sizeof(struct iio_chan_spec),
+ + 					GFP_KERNEL);
+ + 
+ + 	if (chan_array == NULL)
+ + 		return -ENOMEM;
+ + 
+ + 	channels = TOTAL_CHANNELS - adc_dev->channels;
+ + 	for (i = 0; i < (idev->num_channels); i++) {
+ + 		struct iio_chan_spec *chan = chan_array + i;
+ + 		chan->type = IIO_VOLTAGE;
+ + 		chan->indexed = 1;
+ + 		chan->channel = channels;
+ + 		chan->scan_index = i;
+ + 		chan->scan_type.sign = 'u';
+ + 		chan->scan_type.realbits = 12;
+ + 		chan->scan_type.storagebits = 32;
+ + 		chan->scan_type.shift = 0;
+ + 		channels++;
+ + 	}
+ + 
+ + 	idev->channels = chan_array;
+ + 	return idev->num_channels;
+ + }
+ + 
+ + static void tiadc_channel_remove(struct iio_dev *idev)
+ + {
+ + 	kfree(idev->channels);
+ + }
+ + 
+ + static int tiadc_read_raw(struct iio_dev *idev,
+ + 		struct iio_chan_spec const *chan,
+ + 		int *val, int *val2, long mask)
+ + {
+ + 	struct adc_device *adc_dev = iio_priv(idev);
+ + 	int i, map_val;
+ + 	unsigned int fifo1count, readx1, stepid;
+ + 	unsigned long timeout = jiffies + usecs_to_jiffies
+ + 			(IDLE_TIMEOUT * adc_dev->channels);
+ + 
+ + 	if (adc_dev->is_continuous_mode) {
+ + 		pr_info("One shot mode not enabled\n");
+ + 		return -EINVAL;
+ + 	} else {
+ + 		adc_writel(adc_dev, TSCADC_REG_SE, TSCADC_STPENB_STEPENB);
+ + 
+ + 		/* Wait for ADC sequencer to complete sampling */
+ + 		while (adc_readl(adc_dev, TSCADC_REG_ADCFSM) &
+ + 				TSCADC_SEQ_STATUS) {
+ + 			if (time_after(jiffies, timeout))
+ + 				return -EAGAIN;
+ + 		}
+ + 
+ + 		map_val = chan->channel + TOTAL_CHANNELS;
+ + 		fifo1count = adc_readl(adc_dev, TSCADC_REG_FIFO1CNT);
+ + 		for (i = 0; i < fifo1count; i++) {
+ + 			readx1 = adc_readl(adc_dev, TSCADC_REG_FIFO1);
+ + 			stepid = readx1 & TSCADC_FIFOREAD_CHNLID_MASK;
+ + 			stepid = stepid >> 0x10;
+ + 
+ + 			if (stepid == map_val) {
+ + 				readx1 = readx1 & TSCADC_FIFOREAD_DATA_MASK;
+ + 				*val = readx1;
+ + 			}
+ + 		}
+ + 		return IIO_VAL_INT;
+ + 	}
+ + }
+ + 
+ + static const struct iio_info tiadc_info = {
+ + 	.read_raw = &tiadc_read_raw,
+ + 	.attrs = &tiadc_attribute_group,
+ + };
+ + 
+ + static int __devinit tiadc_probe(struct platform_device *pdev)
+ + {
+ + 	struct iio_dev		*idev;
+ + 	struct adc_device	*adc_dev = NULL;
+ + 	struct ti_tscadc_dev	*tscadc_dev = pdev->dev.platform_data;
+ + 	struct mfd_tscadc_board	*pdata;
+ + 	int			err;
+ + 
+ + 	pdata = (struct mfd_tscadc_board *)tscadc_dev->dev->platform_data;
+ + 	if (!pdata || !pdata->adc_init)  {
+ + 		dev_err(tscadc_dev->dev, "Could not find platform data\n");
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	idev = iio_allocate_device(sizeof(struct adc_device));
+ + 	if (idev == NULL) {
+ + 		dev_err(&pdev->dev, "failed to allocate iio device.\n");
+ + 		err = -ENOMEM;
+ + 		goto err_ret;
+ + 	}
+ + 	adc_dev = iio_priv(idev);
+ + 
+ + 	tscadc_dev->adc = adc_dev;
+ + 	adc_dev->mfd_tscadc = tscadc_dev;
+ + 	adc_dev->idev = idev;
+ + 	adc_dev->channels = pdata->adc_init->adc_channels;
+ + 	adc_dev->irq = tscadc_dev->irq;
+ + 
+ + 	idev->dev.parent = &pdev->dev;
+ + 	idev->name = dev_name(&pdev->dev);
+ + 	idev->modes = INDIO_DIRECT_MODE;
+ + 	idev->info = &tiadc_info;
+ + 
+ + 	/* by default driver comes up with oneshot mode */
+ + 	adc_step_config(adc_dev, adc_dev->is_continuous_mode);
+ + 
+ + 	/* program FIFO threshold to value minus 1 */
+ + 	adc_writel(adc_dev, TSCADC_REG_FIFO1THR, FIFO1_THRESHOLD);
+ + 
+ + 	err = tiadc_channel_init(idev, adc_dev);
+ + 	if (err < 0)
+ + 		goto err_free_device;
+ + 
+ + 	init_waitqueue_head(&adc_dev->wq_data_avail);
+ + 
+ + 	err = request_irq(adc_dev->irq, tiadc_irq, IRQF_SHARED,
+ + 		idev->name, idev);
+ + 	if (err)
+ + 		goto err_cleanup_channels;
+ + 
+ + 	err = tiadc_config_sw_ring(idev);
+ + 	if (err)
+ + 		goto err_free_irq;
+ + 
+ + 	err = iio_buffer_register(idev,
+ + 			idev->channels, idev->num_channels);
+ + 	if (err < 0)
+ + 		goto err_free_sw_rb;
+ + 
+ + 	err = iio_device_register(idev);
+ + 	if (err)
+ + 		goto err_unregister;
+ + 
+ + 	dev_info(&pdev->dev, "attached adc driver\n");
+ + 	platform_set_drvdata(pdev, idev);
+ + 
+ + 	return 0;
+ + 
+ + err_unregister:
+ + 	iio_buffer_unregister(idev);
+ + err_free_sw_rb:
+ + 	iio_sw_rb_free(idev->buffer);
+ + err_free_irq:
+ + 	free_irq(adc_dev->irq, idev);
+ + err_cleanup_channels:
+ + 	tiadc_channel_remove(idev);
+ + err_free_device:
+ + 	iio_free_device(idev);
+ + err_ret:
+ + 	return err;
+ + }
+ + 
+ + static int __devexit tiadc_remove(struct platform_device *pdev)
+ + {
+ + 	struct ti_tscadc_dev	*tscadc_dev = pdev->dev.platform_data;
+ + 	struct adc_device	*adc_dev = tscadc_dev->adc;
+ + 	struct iio_dev		*idev = adc_dev->idev;
+ + 
+ + 	free_irq(adc_dev->irq, idev);
+ + 	iio_device_unregister(idev);
+ + 	iio_buffer_unregister(idev);
+ + 	iio_sw_rb_free(idev->buffer);
+ + 	tiadc_channel_remove(idev);
+ + 
+ + 	tscadc_dev->adc = NULL;
+ + 	iio_free_device(idev);
+ + 
+ + 	platform_set_drvdata(pdev, NULL);
+ + 	return 0;
+ + }
+ + 
+ + static int adc_suspend(struct platform_device *pdev, pm_message_t state)
+ + {
+ + 	struct ti_tscadc_dev   *tscadc_dev = pdev->dev.platform_data;
+ + 	struct adc_device	*adc_dev = tscadc_dev->adc;
+ + 	unsigned int idle;
+ + 
+ + 	if (!device_may_wakeup(tscadc_dev->dev)) {
+ + 		idle = adc_readl(adc_dev, TSCADC_REG_CTRL);
+ + 		idle &= ~(TSCADC_CNTRLREG_TSCSSENB);
+ + 		adc_writel(adc_dev, TSCADC_REG_CTRL, (idle |
+ + 				TSCADC_CNTRLREG_POWERDOWN));
+ + 	}
+ + 	return 0;
+ + }
+ + 
+ + static int adc_resume(struct platform_device *pdev)
+ + {
+ + 	struct ti_tscadc_dev   *tscadc_dev = pdev->dev.platform_data;
+ + 	struct adc_device	*adc_dev = tscadc_dev->adc;
+ + 	unsigned int restore;
+ + 
+ + 	restore = adc_readl(adc_dev, TSCADC_REG_CTRL);
+ + 	restore &= ~(TSCADC_CNTRLREG_TSCSSENB);
+ + 	adc_writel(adc_dev, TSCADC_REG_CTRL, restore);
+ + 
+ + 	adc_writel(adc_dev, TSCADC_REG_FIFO1THR, FIFO1_THRESHOLD);
+ + 	adc_step_config(adc_dev, adc_dev->is_continuous_mode);
+ + 
+ + 	/* Make sure ADC is powered up */
+ + 	restore &= ~(TSCADC_CNTRLREG_POWERDOWN);
+ + 	restore |= TSCADC_CNTRLREG_TSCSSENB;
+ + 	adc_writel(adc_dev, TSCADC_REG_CTRL, restore);
+ + 	return 0;
+ + }
+ + 
+ + static struct platform_driver tiadc_driver = {
+ + 	.driver = {
+ + 		.name   = "tiadc",
+ + 		.owner = THIS_MODULE,
+ + 	},
+ + 	.probe          = tiadc_probe,
+ + 	.remove         = __devexit_p(tiadc_remove),
+ + 	.suspend = adc_suspend,
+ + 	.resume = adc_resume,
+ + };
+ + 
+ + module_platform_driver(tiadc_driver);
+ + 
+ + MODULE_DESCRIPTION("TI ADC controller driver");
+ + MODULE_AUTHOR("Rachna Patil <rachna@ti.com>");
+ + MODULE_LICENSE("GPL");
+ diff -crN linux-3.2.1_o/drivers/staging/iio/Documentation/generic_buffer.c linux-3.2.1/drivers/staging/iio/Documentation/generic_buffer.c
+ *** linux-3.2.1_o/drivers/staging/iio/Documentation/generic_buffer.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/staging/iio/Documentation/generic_buffer.c	2014-11-25 13:19:16.148843827 +0900
+ ***************
+ *** 129,141 ****
+   	int fp;
+   
+   	int num_channels;
+ ! 	char *trigger_name = NULL, *device_name = NULL;
+   	char *dev_dir_name, *buf_dir_name;
+   
+ - 	int datardytrigger = 1;
+   	char *data;
+   	ssize_t read_size;
+ ! 	int dev_num, trig_num;
+   	char *buffer_access;
+   	int scan_size;
+   	int noevents = 0;
+ --- 129,140 ----
+   	int fp;
+   
+   	int num_channels;
+ ! 	char *device_name = NULL;
+   	char *dev_dir_name, *buf_dir_name;
+   
+   	char *data;
+   	ssize_t read_size;
+ ! 	int dev_num;
+   	char *buffer_access;
+   	int scan_size;
+   	int noevents = 0;
+ ***************
+ *** 148,157 ****
+   		case 'n':
+   			device_name = optarg;
+   			break;
+ - 		case 't':
+ - 			trigger_name = optarg;
+ - 			datardytrigger = 0;
+ - 			break;
+   		case 'e':
+   			noevents = 1;
+   			break;
+ --- 147,152 ----
+ ***************
+ *** 182,209 ****
+   	printf("iio device number being used is %d\n", dev_num);
+   
+   	asprintf(&dev_dir_name, "%siio:device%d", iio_dir, dev_num);
+ - 	if (trigger_name == NULL) {
+ - 		/*
+ - 		 * Build the trigger name. If it is device associated it's
+ - 		 * name is <device_name>_dev[n] where n matches the device
+ - 		 * number found above
+ - 		 */
+ - 		ret = asprintf(&trigger_name,
+ - 			       "%s-dev%d", device_name, dev_num);
+ - 		if (ret < 0) {
+ - 			ret = -ENOMEM;
+ - 			goto error_ret;
+ - 		}
+ - 	}
+ - 
+ - 	/* Verify the trigger exists */
+ - 	trig_num = find_type_by_name(trigger_name, "trigger");
+ - 	if (trig_num < 0) {
+ - 		printf("Failed to find the trigger %s\n", trigger_name);
+ - 		ret = -ENODEV;
+ - 		goto error_free_triggername;
+ - 	}
+ - 	printf("iio trigger number being used is %d\n", trig_num);
+   
+   	/*
+   	 * Parse the files in scan_elements to identify what channels are
+ --- 177,182 ----
+ ***************
+ *** 213,219 ****
+   	if (ret) {
+   		printf("Problem reading scan element information\n");
+   		printf("diag %s\n", dev_dir_name);
+ ! 		goto error_free_triggername;
+   	}
+   
+   	/*
+ --- 186,192 ----
+   	if (ret) {
+   		printf("Problem reading scan element information\n");
+   		printf("diag %s\n", dev_dir_name);
+ ! 		goto error_ret;
+   	}
+   
+   	/*
+ ***************
+ *** 225,262 ****
+   		       "%siio:device%d/buffer", iio_dir, dev_num);
+   	if (ret < 0) {
+   		ret = -ENOMEM;
+ ! 		goto error_free_triggername;
+ ! 	}
+ ! 	printf("%s %s\n", dev_dir_name, trigger_name);
+ ! 	/* Set the device trigger to be the data rdy trigger found above */
+ ! 	ret = write_sysfs_string_and_verify("trigger/current_trigger",
+ ! 					dev_dir_name,
+ ! 					trigger_name);
+ ! 	if (ret < 0) {
+ ! 		printf("Failed to write current_trigger file\n");
+ ! 		goto error_free_buf_dir_name;
+   	}
+ ! 
+   	/* Setup ring buffer parameters */
+   	ret = write_sysfs_int("length", buf_dir_name, buf_len);
+   	if (ret < 0)
+   		goto error_free_buf_dir_name;
+ - 
+   	/* Enable the buffer */
+   	ret = write_sysfs_int("enable", buf_dir_name, 1);
+   	if (ret < 0)
+   		goto error_free_buf_dir_name;
+ - 	scan_size = size_from_channelarray(infoarray, num_channels);
+ - 	data = malloc(scan_size*buf_len);
+ - 	if (!data) {
+ - 		ret = -ENOMEM;
+ - 		goto error_free_buf_dir_name;
+ - 	}
+   
+   	ret = asprintf(&buffer_access, "/dev/iio:device%d", dev_num);
+   	if (ret < 0) {
+   		ret = -ENOMEM;
+ ! 		goto error_free_data;
+   	}
+   
+   	/* Attempt to open non blocking the access dev */
+ --- 198,219 ----
+   		       "%siio:device%d/buffer", iio_dir, dev_num);
+   	if (ret < 0) {
+   		ret = -ENOMEM;
+ ! 		goto error_ret;
+   	}
+ ! 	printf("%s \n", dev_dir_name);
+   	/* Setup ring buffer parameters */
+   	ret = write_sysfs_int("length", buf_dir_name, buf_len);
+   	if (ret < 0)
+   		goto error_free_buf_dir_name;
+   	/* Enable the buffer */
+   	ret = write_sysfs_int("enable", buf_dir_name, 1);
+   	if (ret < 0)
+   		goto error_free_buf_dir_name;
+   
+   	ret = asprintf(&buffer_access, "/dev/iio:device%d", dev_num);
+   	if (ret < 0) {
+   		ret = -ENOMEM;
+ ! 		goto error_free_buf_dir_name;
+   	}
+   
+   	/* Attempt to open non blocking the access dev */
+ ***************
+ *** 264,299 ****
+   	if (fp == -1) { /*If it isn't there make the node */
+   		printf("Failed to open %s\n", buffer_access);
+   		ret = -errno;
+ ! 		goto error_free_buffer_access;
+   	}
+   
+   	/* Wait for events 10 times */
+   	for (j = 0; j < num_loops; j++) {
+ ! 		if (!noevents) {
+ ! 			struct pollfd pfd = {
+ ! 				.fd = fp,
+ ! 				.events = POLLIN,
+ ! 			};
+ ! 
+ ! 			poll(&pfd, 1, -1);
+ ! 			toread = buf_len;
+ ! 
+ ! 		} else {
+ ! 			usleep(timedelay);
+ ! 			toread = 64;
+ ! 		}
+ ! 
+   		read_size = read(fp,
+   				 data,
+ ! 				 toread*scan_size);
+   		if (read_size == -EAGAIN) {
+   			printf("nothing available\n");
+   			continue;
+   		}
+ ! 		for (i = 0; i < read_size/scan_size; i++)
+ ! 			process_scan(data + scan_size*i,
+ ! 				     infoarray,
+ ! 				     num_channels);
+   	}
+   
+   	/* Stop the ring buffer */
+ --- 221,248 ----
+   	if (fp == -1) { /*If it isn't there make the node */
+   		printf("Failed to open %s\n", buffer_access);
+   		ret = -errno;
+ ! 		goto error_free_buf_dir_name;
+ ! 	}
+ ! 
+ ! 	scan_size = size_from_channelarray(infoarray, num_channels);
+ ! 	data = malloc(scan_size*buf_len);
+ ! 	if (!data) {
+ ! 		ret = -ENOMEM;
+ ! 		goto error_close_buffer_access;
+   	}
+   
+   	/* Wait for events 10 times */
+   	for (j = 0; j < num_loops; j++) {
+ ! 		usleep(timedelay);
+   		read_size = read(fp,
+   				 data,
+ ! 				 buf_len*scan_size);
+   		if (read_size == -EAGAIN) {
+   			printf("nothing available\n");
+   			continue;
+   		}
+ ! 		for (i = 0; i < read_size/4; i++, data+=4)
+ ! 			printf("ADC Value: %d\n", *(long*)data);
+   	}
+   
+   	/* Stop the ring buffer */
+ ***************
+ *** 301,321 ****
+   	if (ret < 0)
+   		goto error_close_buffer_access;
+   
+ - 	/* Disconnect from the trigger - just write a dummy name.*/
+ - 	write_sysfs_string("trigger/current_trigger",
+ - 			dev_dir_name, "NULL");
+ - 
+   error_close_buffer_access:
+   	close(fp);
+ - error_free_data:
+ - 	free(data);
+ - error_free_buffer_access:
+ - 	free(buffer_access);
+   error_free_buf_dir_name:
+   	free(buf_dir_name);
+ - error_free_triggername:
+ - 	if (datardytrigger)
+ - 		free(trigger_name);
+   error_ret:
+   	return ret;
+   }
+ --- 250,259 ----
+ diff -crN linux-3.2.1_o/drivers/tty/serial/atmel_serial.c linux-3.2.1/drivers/tty/serial/atmel_serial.c
+ *** linux-3.2.1_o/drivers/tty/serial/atmel_serial.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/tty/serial/atmel_serial.c	2014-11-25 13:19:16.187092959 +0900
+ ***************
+ *** 212,220 ****
+   {
+   	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
+   	unsigned int mode;
+ - 	unsigned long flags;
+   
+ ! 	spin_lock_irqsave(&port->lock, flags);
+   
+   	/* Disable interrupts */
+   	UART_PUT_IDR(port, atmel_port->tx_done_mask);
+ --- 212,219 ----
+   {
+   	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
+   	unsigned int mode;
+   
+ ! 	spin_lock(&port->lock);
+   
+   	/* Disable interrupts */
+   	UART_PUT_IDR(port, atmel_port->tx_done_mask);
+ ***************
+ *** 245,251 ****
+   	/* Enable interrupts */
+   	UART_PUT_IER(port, atmel_port->tx_done_mask);
+   
+ ! 	spin_unlock_irqrestore(&port->lock, flags);
+   
+   }
+   
+ --- 244,250 ----
+   	/* Enable interrupts */
+   	UART_PUT_IER(port, atmel_port->tx_done_mask);
+   
+ ! 	spin_unlock(&port->lock);
+   
+   }
+   
+ diff -crN linux-3.2.1_o/drivers/tty/serial/Kconfig linux-3.2.1/drivers/tty/serial/Kconfig
+ *** linux-3.2.1_o/drivers/tty/serial/Kconfig	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/tty/serial/Kconfig	2014-11-25 13:19:16.195069233 +0900
+ ***************
+ *** 1324,1330 ****
+   
+   config SERIAL_OMAP
+   	tristate "OMAP serial port support"
+ ! 	depends on ARCH_OMAP2 || ARCH_OMAP3 || ARCH_OMAP4
+   	select SERIAL_CORE
+   	help
+   	  If you have a machine based on an Texas Instruments OMAP CPU you
+ --- 1324,1330 ----
+   
+   config SERIAL_OMAP
+   	tristate "OMAP serial port support"
+ ! 	depends on ARCH_OMAP2 || ARCH_OMAP3 || ARCH_OMAP4 || ARCH_CKB
+   	select SERIAL_CORE
+   	help
+   	  If you have a machine based on an Texas Instruments OMAP CPU you
+ diff -crN linux-3.2.1_o/drivers/tty/serial/omap-serial.c linux-3.2.1/drivers/tty/serial/omap-serial.c
+ *** linux-3.2.1_o/drivers/tty/serial/omap-serial.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/tty/serial/omap-serial.c	2014-11-25 13:19:16.203085001 +0900
+ ***************
+ *** 37,53 ****
+   #include <linux/clk.h>
+   #include <linux/serial_core.h>
+   #include <linux/irq.h>
+   
+   #include <plat/dma.h>
+   #include <plat/dmtimer.h>
+   #include <plat/omap-serial.h>
+   
+   static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
+   
+   /* Forward declaration of functions */
+   static void uart_tx_dma_callback(int lch, u16 ch_status, void *data);
+ ! static void serial_omap_rx_timeout(unsigned long uart_no);
+   static int serial_omap_start_rxdma(struct uart_omap_port *up);
+   
+   static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
+   {
+ --- 37,60 ----
+   #include <linux/clk.h>
+   #include <linux/serial_core.h>
+   #include <linux/irq.h>
+ + #include <linux/pm_runtime.h>
+ + #include <linux/of.h>
+   
+   #include <plat/dma.h>
+   #include <plat/dmtimer.h>
+   #include <plat/omap-serial.h>
+   
+ + #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
+ + 
+   static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
+   
+   /* Forward declaration of functions */
+   static void uart_tx_dma_callback(int lch, u16 ch_status, void *data);
+ ! static void serial_omap_rxdma_poll(unsigned long uart_no);
+   static int serial_omap_start_rxdma(struct uart_omap_port *up);
+ + static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
+ + 
+ + static struct workqueue_struct *serial_omap_uart_wq;
+   
+   static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
+   {
+ ***************
+ *** 102,107 ****
+ --- 109,116 ----
+   		omap_free_dma(up->uart_dma.rx_dma_channel);
+   		up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
+   		up->uart_dma.rx_dma_used = false;
+ + 		pm_runtime_mark_last_busy(&up->pdev->dev);
+ + 		pm_runtime_put_autosuspend(&up->pdev->dev);
+   	}
+   }
+   
+ ***************
+ *** 109,117 ****
+   {
+   	struct uart_omap_port *up = (struct uart_omap_port *)port;
+   
+ ! 	dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->pdev->id);
+   	up->ier |= UART_IER_MSI;
+   	serial_out(up, UART_IER, up->ier);
+   }
+   
+   static void serial_omap_stop_tx(struct uart_port *port)
+ --- 118,129 ----
+   {
+   	struct uart_omap_port *up = (struct uart_omap_port *)port;
+   
+ ! 	dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
+ ! 
+ ! 	pm_runtime_get_sync(&up->pdev->dev);
+   	up->ier |= UART_IER_MSI;
+   	serial_out(up, UART_IER, up->ier);
+ + 	pm_runtime_put(&up->pdev->dev);
+   }
+   
+   static void serial_omap_stop_tx(struct uart_port *port)
+ ***************
+ *** 129,158 ****
+   		omap_stop_dma(up->uart_dma.tx_dma_channel);
+   		omap_free_dma(up->uart_dma.tx_dma_channel);
+   		up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
+   	}
+   
+   	if (up->ier & UART_IER_THRI) {
+   		up->ier &= ~UART_IER_THRI;
+   		serial_out(up, UART_IER, up->ier);
+   	}
+   }
+   
+   static void serial_omap_stop_rx(struct uart_port *port)
+   {
+   	struct uart_omap_port *up = (struct uart_omap_port *)port;
+   
+   	if (up->use_dma)
+   		serial_omap_stop_rxdma(up);
+   	up->ier &= ~UART_IER_RLSI;
+   	up->port.read_status_mask &= ~UART_LSR_DR;
+   	serial_out(up, UART_IER, up->ier);
+   }
+   
+ ! static inline void receive_chars(struct uart_omap_port *up, int *status)
+   {
+   	struct tty_struct *tty = up->port.state->port.tty;
+ ! 	unsigned int flag;
+ ! 	unsigned char ch, lsr = *status;
+   	int max_count = 256;
+   
+   	do {
+ --- 141,180 ----
+   		omap_stop_dma(up->uart_dma.tx_dma_channel);
+   		omap_free_dma(up->uart_dma.tx_dma_channel);
+   		up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
+ + 		pm_runtime_mark_last_busy(&up->pdev->dev);
+ + 		pm_runtime_put_autosuspend(&up->pdev->dev);
+   	}
+   
+ + 	pm_runtime_get_sync(&up->pdev->dev);
+   	if (up->ier & UART_IER_THRI) {
+   		up->ier &= ~UART_IER_THRI;
+   		serial_out(up, UART_IER, up->ier);
+   	}
+ + 
+ + 	pm_runtime_mark_last_busy(&up->pdev->dev);
+ + 	pm_runtime_put_autosuspend(&up->pdev->dev);
+   }
+   
+   static void serial_omap_stop_rx(struct uart_port *port)
+   {
+   	struct uart_omap_port *up = (struct uart_omap_port *)port;
+   
+ + 	pm_runtime_get_sync(&up->pdev->dev);
+   	if (up->use_dma)
+   		serial_omap_stop_rxdma(up);
+   	up->ier &= ~UART_IER_RLSI;
+   	up->port.read_status_mask &= ~UART_LSR_DR;
+   	serial_out(up, UART_IER, up->ier);
+ + 	pm_runtime_mark_last_busy(&up->pdev->dev);
+ + 	pm_runtime_put_autosuspend(&up->pdev->dev);
+   }
+   
+ ! static inline void receive_chars(struct uart_omap_port *up,
+ ! 		unsigned int *status)
+   {
+   	struct tty_struct *tty = up->port.state->port.tty;
+ ! 	unsigned int flag, lsr = *status;
+ ! 	unsigned char ch = 0;
+   	int max_count = 256;
+   
+   	do {
+ ***************
+ *** 262,268 ****
+ --- 284,293 ----
+   	int ret = 0;
+   
+   	if (!up->use_dma) {
+ + 		pm_runtime_get_sync(&up->pdev->dev);
+   		serial_omap_enable_ier_thri(up);
+ + 		pm_runtime_mark_last_busy(&up->pdev->dev);
+ + 		pm_runtime_put_autosuspend(&up->pdev->dev);
+   		return;
+   	}
+   
+ ***************
+ *** 272,277 ****
+ --- 297,303 ----
+   	xmit = &up->port.state->xmit;
+   
+   	if (up->uart_dma.tx_dma_channel == OMAP_UART_DMA_CH_FREE) {
+ + 		pm_runtime_get_sync(&up->pdev->dev);
+   		ret = omap_request_dma(up->uart_dma.uart_dma_tx,
+   				"UART Tx DMA",
+   				(void *)uart_tx_dma_callback, up,
+ ***************
+ *** 354,362 ****
+   	unsigned int iir, lsr;
+   	unsigned long flags;
+   
+   	iir = serial_in(up, UART_IIR);
+ ! 	if (iir & UART_IIR_NO_INT)
+   		return IRQ_NONE;
+   
+   	spin_lock_irqsave(&up->port.lock, flags);
+   	lsr = serial_in(up, UART_LSR);
+ --- 380,392 ----
+   	unsigned int iir, lsr;
+   	unsigned long flags;
+   
+ + 	pm_runtime_get_sync(&up->pdev->dev);
+   	iir = serial_in(up, UART_IIR);
+ ! 	if (iir & UART_IIR_NO_INT) {
+ ! 		pm_runtime_mark_last_busy(&up->pdev->dev);
+ ! 		pm_runtime_put_autosuspend(&up->pdev->dev);
+   		return IRQ_NONE;
+ + 	}
+   
+   	spin_lock_irqsave(&up->port.lock, flags);
+   	lsr = serial_in(up, UART_LSR);
+ ***************
+ *** 378,383 ****
+ --- 408,416 ----
+   		transmit_chars(up);
+   
+   	spin_unlock_irqrestore(&up->port.lock, flags);
+ + 	pm_runtime_mark_last_busy(&up->pdev->dev);
+ + 	pm_runtime_put_autosuspend(&up->pdev->dev);
+ + 
+   	up->port_activity = jiffies;
+   	return IRQ_HANDLED;
+   }
+ ***************
+ *** 388,398 ****
+   	unsigned long flags = 0;
+   	unsigned int ret = 0;
+   
+ ! 	dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->pdev->id);
+   	spin_lock_irqsave(&up->port.lock, flags);
+   	ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
+   	spin_unlock_irqrestore(&up->port.lock, flags);
+ ! 
+   	return ret;
+   }
+   
+ --- 421,432 ----
+   	unsigned long flags = 0;
+   	unsigned int ret = 0;
+   
+ ! 	pm_runtime_get_sync(&up->pdev->dev);
+ ! 	dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
+   	spin_lock_irqsave(&up->port.lock, flags);
+   	ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
+   	spin_unlock_irqrestore(&up->port.lock, flags);
+ ! 	pm_runtime_put(&up->pdev->dev);
+   	return ret;
+   }
+   
+ ***************
+ *** 402,409 ****
+   	unsigned char status;
+   	unsigned int ret = 0;
+   
+   	status = check_modem_status(up);
+ ! 	dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->pdev->id);
+   
+   	if (status & UART_MSR_DCD)
+   		ret |= TIOCM_CAR;
+ --- 436,446 ----
+   	unsigned char status;
+   	unsigned int ret = 0;
+   
+ + 	pm_runtime_get_sync(&up->pdev->dev);
+   	status = check_modem_status(up);
+ ! 	pm_runtime_put(&up->pdev->dev);
+ ! 
+ ! 	dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
+   
+   	if (status & UART_MSR_DCD)
+   		ret |= TIOCM_CAR;
+ ***************
+ *** 421,427 ****
+   	struct uart_omap_port *up = (struct uart_omap_port *)port;
+   	unsigned char mcr = 0;
+   
+ ! 	dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->pdev->id);
+   	if (mctrl & TIOCM_RTS)
+   		mcr |= UART_MCR_RTS;
+   	if (mctrl & TIOCM_DTR)
+ --- 458,464 ----
+   	struct uart_omap_port *up = (struct uart_omap_port *)port;
+   	unsigned char mcr = 0;
+   
+ ! 	dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
+   	if (mctrl & TIOCM_RTS)
+   		mcr |= UART_MCR_RTS;
+   	if (mctrl & TIOCM_DTR)
+ ***************
+ *** 433,440 ****
+   	if (mctrl & TIOCM_LOOP)
+   		mcr |= UART_MCR_LOOP;
+   
+ ! 	mcr |= up->mcr;
+ ! 	serial_out(up, UART_MCR, mcr);
+   }
+   
+   static void serial_omap_break_ctl(struct uart_port *port, int break_state)
+ --- 470,480 ----
+   	if (mctrl & TIOCM_LOOP)
+   		mcr |= UART_MCR_LOOP;
+   
+ ! 	pm_runtime_get_sync(&up->pdev->dev);
+ ! 	up->mcr = serial_in(up, UART_MCR);
+ ! 	up->mcr |= mcr;
+ ! 	serial_out(up, UART_MCR, up->mcr);
+ ! 	pm_runtime_put(&up->pdev->dev);
+   }
+   
+   static void serial_omap_break_ctl(struct uart_port *port, int break_state)
+ ***************
+ *** 442,448 ****
+   	struct uart_omap_port *up = (struct uart_omap_port *)port;
+   	unsigned long flags = 0;
+   
+ ! 	dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->pdev->id);
+   	spin_lock_irqsave(&up->port.lock, flags);
+   	if (break_state == -1)
+   		up->lcr |= UART_LCR_SBC;
+ --- 482,489 ----
+   	struct uart_omap_port *up = (struct uart_omap_port *)port;
+   	unsigned long flags = 0;
+   
+ ! 	dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
+ ! 	pm_runtime_get_sync(&up->pdev->dev);
+   	spin_lock_irqsave(&up->port.lock, flags);
+   	if (break_state == -1)
+   		up->lcr |= UART_LCR_SBC;
+ ***************
+ *** 450,455 ****
+ --- 491,497 ----
+   		up->lcr &= ~UART_LCR_SBC;
+   	serial_out(up, UART_LCR, up->lcr);
+   	spin_unlock_irqrestore(&up->port.lock, flags);
+ + 	pm_runtime_put(&up->pdev->dev);
+   }
+   
+   static int serial_omap_startup(struct uart_port *port)
+ ***************
+ *** 466,473 ****
+   	if (retval)
+   		return retval;
+   
+ ! 	dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->pdev->id);
+   
+   	/*
+   	 * Clear the FIFO buffers and disable them.
+   	 * (they will be reenabled in set_termios())
+ --- 508,516 ----
+   	if (retval)
+   		return retval;
+   
+ ! 	dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
+   
+ + 	pm_runtime_get_sync(&up->pdev->dev);
+   	/*
+   	 * Clear the FIFO buffers and disable them.
+   	 * (they will be reenabled in set_termios())
+ ***************
+ *** 505,512 ****
+   			(dma_addr_t *)&(up->uart_dma.tx_buf_dma_phys),
+   			0);
+   		init_timer(&(up->uart_dma.rx_timer));
+ ! 		up->uart_dma.rx_timer.function = serial_omap_rx_timeout;
+ ! 		up->uart_dma.rx_timer.data = up->pdev->id;
+   		/* Currently the buffer size is 4KB. Can increase it */
+   		up->uart_dma.rx_buf = dma_alloc_coherent(NULL,
+   			up->uart_dma.rx_buf_size,
+ --- 548,555 ----
+   			(dma_addr_t *)&(up->uart_dma.tx_buf_dma_phys),
+   			0);
+   		init_timer(&(up->uart_dma.rx_timer));
+ ! 		up->uart_dma.rx_timer.function = serial_omap_rxdma_poll;
+ ! 		up->uart_dma.rx_timer.data = up->port.line;
+   		/* Currently the buffer size is 4KB. Can increase it */
+   		up->uart_dma.rx_buf = dma_alloc_coherent(NULL,
+   			up->uart_dma.rx_buf_size,
+ ***************
+ *** 523,528 ****
+ --- 566,573 ----
+   	/* Enable module level wake up */
+   	serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
+   
+ + 	pm_runtime_mark_last_busy(&up->pdev->dev);
+ + 	pm_runtime_put_autosuspend(&up->pdev->dev);
+   	up->port_activity = jiffies;
+   	return 0;
+   }
+ ***************
+ *** 532,538 ****
+   	struct uart_omap_port *up = (struct uart_omap_port *)port;
+   	unsigned long flags = 0;
+   
+ ! 	dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->pdev->id);
+   	/*
+   	 * Disable interrupts from this port
+   	 */
+ --- 577,585 ----
+   	struct uart_omap_port *up = (struct uart_omap_port *)port;
+   	unsigned long flags = 0;
+   
+ ! 	dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
+ ! 
+ ! 	pm_runtime_get_sync(&up->pdev->dev);
+   	/*
+   	 * Disable interrupts from this port
+   	 */
+ ***************
+ *** 566,571 ****
+ --- 613,620 ----
+   			up->uart_dma.rx_buf_dma_phys);
+   		up->uart_dma.rx_buf = NULL;
+   	}
+ + 
+ + 	pm_runtime_put(&up->pdev->dev);
+   	free_irq(up->port.irq, up);
+   }
+   
+ ***************
+ *** 573,580 ****
+   serial_omap_configure_xonxoff
+   		(struct uart_omap_port *up, struct ktermios *termios)
+   {
+ - 	unsigned char efr = 0;
+ - 
+   	up->lcr = serial_in(up, UART_LCR);
+   	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
+   	up->efr = serial_in(up, UART_EFR);
+ --- 622,627 ----
+ ***************
+ *** 584,591 ****
+   	serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
+   
+   	/* clear SW control mode bits */
+ ! 	efr = up->efr;
+ ! 	efr &= OMAP_UART_SW_CLR;
+   
+   	/*
+   	 * IXON Flag:
+ --- 631,637 ----
+   	serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
+   
+   	/* clear SW control mode bits */
+ ! 	up->efr &= OMAP_UART_SW_CLR;
+   
+   	/*
+   	 * IXON Flag:
+ ***************
+ *** 593,599 ****
+   	 * Transmit XON1, XOFF1
+   	 */
+   	if (termios->c_iflag & IXON)
+ ! 		efr |= OMAP_UART_SW_TX;
+   
+   	/*
+   	 * IXOFF Flag:
+ --- 639,645 ----
+   	 * Transmit XON1, XOFF1
+   	 */
+   	if (termios->c_iflag & IXON)
+ ! 		up->efr |= OMAP_UART_SW_TX;
+   
+   	/*
+   	 * IXOFF Flag:
+ ***************
+ *** 601,607 ****
+   	 * Receiver compares XON1, XOFF1.
+   	 */
+   	if (termios->c_iflag & IXOFF)
+ ! 		efr |= OMAP_UART_SW_RX;
+   
+   	serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
+   	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
+ --- 647,653 ----
+   	 * Receiver compares XON1, XOFF1.
+   	 */
+   	if (termios->c_iflag & IXOFF)
+ ! 		up->efr |= OMAP_UART_SW_RX;
+   
+   	serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
+   	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
+ ***************
+ *** 624,636 ****
+   	 * load the new software flow control mode IXON or IXOFF
+   	 * and restore the UARTi.EFR_REG[4] ENHANCED_EN value.
+   	 */
+ ! 	serial_out(up, UART_EFR, efr | UART_EFR_SCD);
+   	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
+   
+   	serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR);
+   	serial_out(up, UART_LCR, up->lcr);
+   }
+   
+   static void
+   serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
+   			struct ktermios *old)
+ --- 670,690 ----
+   	 * load the new software flow control mode IXON or IXOFF
+   	 * and restore the UARTi.EFR_REG[4] ENHANCED_EN value.
+   	 */
+ ! 	serial_out(up, UART_EFR, up->efr | UART_EFR_SCD);
+   	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
+   
+   	serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR);
+   	serial_out(up, UART_LCR, up->lcr);
+   }
+   
+ + static void serial_omap_uart_qos_work(struct work_struct *work)
+ + {
+ + 	struct uart_omap_port *up = container_of(work, struct uart_omap_port,
+ + 						qos_work);
+ + 
+ + 	pm_qos_update_request(&up->pm_qos_request, up->latency);
+ + }
+ + 
+   static void
+   serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
+   			struct ktermios *old)
+ ***************
+ *** 671,676 ****
+ --- 725,740 ----
+   	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
+   	quot = serial_omap_get_divisor(port, baud);
+   
+ + 	/* calculate wakeup latency constraint */
+ + 	up->calc_latency = (1000000 * up->port.fifosize) /
+ + 				(1000 * baud / 8);
+ + 	up->latency = up->calc_latency;
+ + 	schedule_work(&up->qos_work);
+ + 
+ + 	up->dll = quot & 0xff;
+ + 	up->dlh = quot >> 8;
+ + 	up->mdr1 = UART_OMAP_MDR1_DISABLE;
+ + 
+   	up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
+   			UART_FCR_ENABLE_FIFO;
+   	if (up->use_dma)
+ ***************
+ *** 680,685 ****
+ --- 744,750 ----
+   	 * Ok, we're now changing the port state. Do it with
+   	 * interrupts disabled.
+   	 */
+ + 	pm_runtime_get_sync(&up->pdev->dev);
+   	spin_lock_irqsave(&up->port.lock, flags);
+   
+   	/*
+ ***************
+ *** 723,728 ****
+ --- 788,795 ----
+   		up->ier |= UART_IER_MSI;
+   	serial_out(up, UART_IER, up->ier);
+   	serial_out(up, UART_LCR, cval);		/* reset DLAB */
+ + 	up->lcr = cval;
+ + 	up->scr = OMAP_UART_SCR_TX_EMPTY;
+   
+   	/* FIFOs and DMA Settings */
+   
+ ***************
+ *** 749,765 ****
+   
+   	if (up->use_dma) {
+   		serial_out(up, UART_TI752_TLR, 0);
+ ! 		serial_out(up, UART_OMAP_SCR,
+ ! 			(UART_FCR_TRIGGER_4 | UART_FCR_TRIGGER_8));
+   	}
+   
+   	serial_out(up, UART_EFR, up->efr);
+   	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
+   	serial_out(up, UART_MCR, up->mcr);
+   
+   	/* Protocol, Baud Rate, and Interrupt Settings */
+   
+ ! 	serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
+   	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
+   
+   	up->efr = serial_in(up, UART_EFR);
+ --- 816,837 ----
+   
+   	if (up->use_dma) {
+   		serial_out(up, UART_TI752_TLR, 0);
+ ! 		up->scr |= (UART_FCR_TRIGGER_4 | UART_FCR_TRIGGER_8);
+   	}
+   
+ + 	serial_out(up, UART_OMAP_SCR, up->scr);
+ + 
+   	serial_out(up, UART_EFR, up->efr);
+   	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
+   	serial_out(up, UART_MCR, up->mcr);
+   
+   	/* Protocol, Baud Rate, and Interrupt Settings */
+   
+ ! 	if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
+ ! 		serial_omap_mdr1_errataset(up, up->mdr1);
+ ! 	else
+ ! 		serial_out(up, UART_OMAP_MDR1, up->mdr1);
+ ! 
+   	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
+   
+   	up->efr = serial_in(up, UART_EFR);
+ ***************
+ *** 769,776 ****
+   	serial_out(up, UART_IER, 0);
+   	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
+   
+ ! 	serial_out(up, UART_DLL, quot & 0xff);          /* LS of divisor */
+ ! 	serial_out(up, UART_DLM, quot >> 8);            /* MS of divisor */
+   
+   	serial_out(up, UART_LCR, 0);
+   	serial_out(up, UART_IER, up->ier);
+ --- 841,848 ----
+   	serial_out(up, UART_IER, 0);
+   	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
+   
+ ! 	serial_out(up, UART_DLL, up->dll);	/* LS of divisor */
+ ! 	serial_out(up, UART_DLM, up->dlh);	/* MS of divisor */
+   
+   	serial_out(up, UART_LCR, 0);
+   	serial_out(up, UART_IER, up->ier);
+ ***************
+ *** 780,788 ****
+   	serial_out(up, UART_LCR, cval);
+   
+   	if (baud > 230400 && baud != 3000000)
+ ! 		serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_13X_MODE);
+   	else
+ ! 		serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE);
+   
+   	/* Hardware Flow Control Configuration */
+   
+ --- 852,865 ----
+   	serial_out(up, UART_LCR, cval);
+   
+   	if (baud > 230400 && baud != 3000000)
+ ! 		up->mdr1 = UART_OMAP_MDR1_13X_MODE;
+   	else
+ ! 		up->mdr1 = UART_OMAP_MDR1_16X_MODE;
+ ! 
+ ! 	if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
+ ! 		serial_omap_mdr1_errataset(up, up->mdr1);
+ ! 	else
+ ! 		serial_out(up, UART_OMAP_MDR1, up->mdr1);
+   
+   	/* Hardware Flow Control Configuration */
+   
+ ***************
+ *** 809,815 ****
+   	serial_omap_configure_xonxoff(up, termios);
+   
+   	spin_unlock_irqrestore(&up->port.lock, flags);
+ ! 	dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->pdev->id);
+   }
+   
+   static void
+ --- 886,893 ----
+   	serial_omap_configure_xonxoff(up, termios);
+   
+   	spin_unlock_irqrestore(&up->port.lock, flags);
+ ! 	pm_runtime_put(&up->pdev->dev);
+ ! 	dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
+   }
+   
+   static void
+ ***************
+ *** 819,825 ****
+   	struct uart_omap_port *up = (struct uart_omap_port *)port;
+   	unsigned char efr;
+   
+ ! 	dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->pdev->id);
+   	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
+   	efr = serial_in(up, UART_EFR);
+   	serial_out(up, UART_EFR, efr | UART_EFR_ECB);
+ --- 897,905 ----
+   	struct uart_omap_port *up = (struct uart_omap_port *)port;
+   	unsigned char efr;
+   
+ ! 	dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
+ ! 
+ ! 	pm_runtime_get_sync(&up->pdev->dev);
+   	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
+   	efr = serial_in(up, UART_EFR);
+   	serial_out(up, UART_EFR, efr | UART_EFR_ECB);
+ ***************
+ *** 829,834 ****
+ --- 909,923 ----
+   	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
+   	serial_out(up, UART_EFR, efr);
+   	serial_out(up, UART_LCR, 0);
+ + 
+ + 	if (!device_may_wakeup(&up->pdev->dev)) {
+ + 		if (!state)
+ + 			pm_runtime_forbid(&up->pdev->dev);
+ + 		else
+ + 			pm_runtime_allow(&up->pdev->dev);
+ + 	}
+ + 
+ + 	pm_runtime_put(&up->pdev->dev);
+   }
+   
+   static void serial_omap_release_port(struct uart_port *port)
+ ***************
+ *** 847,853 ****
+   	struct uart_omap_port *up = (struct uart_omap_port *)port;
+   
+   	dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
+ ! 							up->pdev->id);
+   	up->port.type = PORT_OMAP;
+   }
+   
+ --- 936,942 ----
+   	struct uart_omap_port *up = (struct uart_omap_port *)port;
+   
+   	dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
+ ! 							up->port.line);
+   	up->port.type = PORT_OMAP;
+   }
+   
+ ***************
+ *** 864,870 ****
+   {
+   	struct uart_omap_port *up = (struct uart_omap_port *)port;
+   
+ ! 	dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->pdev->id);
+   	return up->name;
+   }
+   
+ --- 953,959 ----
+   {
+   	struct uart_omap_port *up = (struct uart_omap_port *)port;
+   
+ ! 	dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
+   	return up->name;
+   }
+   
+ ***************
+ *** 906,924 ****
+   static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
+   {
+   	struct uart_omap_port *up = (struct uart_omap_port *)port;
+   	wait_for_xmitr(up);
+   	serial_out(up, UART_TX, ch);
+   }
+   
+   static int serial_omap_poll_get_char(struct uart_port *port)
+   {
+   	struct uart_omap_port *up = (struct uart_omap_port *)port;
+ ! 	unsigned int status = serial_in(up, UART_LSR);
+   
+   	if (!(status & UART_LSR_DR))
+   		return NO_POLL_CHAR;
+   
+ ! 	return serial_in(up, UART_RX);
+   }
+   
+   #endif /* CONFIG_CONSOLE_POLL */
+ --- 995,1020 ----
+   static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
+   {
+   	struct uart_omap_port *up = (struct uart_omap_port *)port;
+ + 
+ + 	pm_runtime_get_sync(&up->pdev->dev);
+   	wait_for_xmitr(up);
+   	serial_out(up, UART_TX, ch);
+ + 	pm_runtime_put(&up->pdev->dev);
+   }
+   
+   static int serial_omap_poll_get_char(struct uart_port *port)
+   {
+   	struct uart_omap_port *up = (struct uart_omap_port *)port;
+ ! 	unsigned int status;
+   
+ + 	pm_runtime_get_sync(&up->pdev->dev);
+ + 	status = serial_in(up, UART_LSR);
+   	if (!(status & UART_LSR_DR))
+   		return NO_POLL_CHAR;
+   
+ ! 	status = serial_in(up, UART_RX);
+ ! 	pm_runtime_put(&up->pdev->dev);
+ ! 	return status;
+   }
+   
+   #endif /* CONFIG_CONSOLE_POLL */
+ ***************
+ *** 946,951 ****
+ --- 1042,1049 ----
+   	unsigned int ier;
+   	int locked = 1;
+   
+ + 	pm_runtime_get_sync(&up->pdev->dev);
+ + 
+   	local_irq_save(flags);
+   	if (up->port.sysrq)
+   		locked = 0;
+ ***************
+ *** 978,983 ****
+ --- 1076,1083 ----
+   	if (up->msr_saved_flags)
+   		check_modem_status(up);
+   
+ + 	pm_runtime_mark_last_busy(&up->pdev->dev);
+ + 	pm_runtime_put_autosuspend(&up->pdev->dev);
+   	if (locked)
+   		spin_unlock(&up->port.lock);
+   	local_irq_restore(flags);
+ ***************
+ *** 1014,1020 ****
+   
+   static void serial_omap_add_console_port(struct uart_omap_port *up)
+   {
+ ! 	serial_omap_console_ports[up->pdev->id] = up;
+   }
+   
+   #define OMAP_CONSOLE	(&serial_omap_console)
+ --- 1114,1120 ----
+   
+   static void serial_omap_add_console_port(struct uart_omap_port *up)
+   {
+ ! 	serial_omap_console_ports[up->port.line] = up;
+   }
+   
+   #define OMAP_CONSOLE	(&serial_omap_console)
+ ***************
+ *** 1060,1085 ****
+   	.cons		= OMAP_CONSOLE,
+   };
+   
+ ! static int
+ ! serial_omap_suspend(struct platform_device *pdev, pm_message_t state)
+   {
+ ! 	struct uart_omap_port *up = platform_get_drvdata(pdev);
+   
+ - 	if (up)
+   		uart_suspend_port(&serial_omap_reg, &up->port);
+   	return 0;
+   }
+   
+ ! static int serial_omap_resume(struct platform_device *dev)
+   {
+ ! 	struct uart_omap_port *up = platform_get_drvdata(dev);
+   
+   	if (up)
+   		uart_resume_port(&serial_omap_reg, &up->port);
+   	return 0;
+   }
+   
+ ! static void serial_omap_rx_timeout(unsigned long uart_no)
+   {
+   	struct uart_omap_port *up = ui[uart_no];
+   	unsigned int curr_dma_pos, curr_transmitted_size;
+ --- 1160,1199 ----
+   	.cons		= OMAP_CONSOLE,
+   };
+   
+ ! #ifdef CONFIG_SUSPEND
+ ! static int serial_omap_suspend(struct device *dev)
+   {
+ ! 	struct uart_omap_port *up = dev_get_drvdata(dev);
+ ! 
+ ! 	if (up) {
+ !                 /*
+ !                   In case suspending during Bluetooth traffic, after resume
+ !                   the bluetooth is stuck.
+ !                   It was identified that suspend is happening before the
+ !                   UART buffer was fully drained which caused this hang after
+ !                   resume. The following delay is a temporary workaround until
+ !                   the issue is resolved properly.
+ !                 */
+ !                 msleep(10);
+   
+   		uart_suspend_port(&serial_omap_reg, &up->port);
+ + 		flush_work_sync(&up->qos_work);
+ + 	}
+ + 
+   	return 0;
+   }
+   
+ ! static int serial_omap_resume(struct device *dev)
+   {
+ ! 	struct uart_omap_port *up = dev_get_drvdata(dev);
+   
+   	if (up)
+   		uart_resume_port(&serial_omap_reg, &up->port);
+   	return 0;
+   }
+ + #endif
+   
+ ! static void serial_omap_rxdma_poll(unsigned long uart_no)
+   {
+   	struct uart_omap_port *up = ui[uart_no];
+   	unsigned int curr_dma_pos, curr_transmitted_size;
+ ***************
+ *** 1089,1097 ****
+   	if ((curr_dma_pos == up->uart_dma.prev_rx_dma_pos) ||
+   			     (curr_dma_pos == 0)) {
+   		if (jiffies_to_msecs(jiffies - up->port_activity) <
+ ! 							RX_TIMEOUT) {
+   			mod_timer(&up->uart_dma.rx_timer, jiffies +
+ ! 				usecs_to_jiffies(up->uart_dma.rx_timeout));
+   		} else {
+   			serial_omap_stop_rxdma(up);
+   			up->ier |= (UART_IER_RDI | UART_IER_RLSI);
+ --- 1203,1211 ----
+   	if ((curr_dma_pos == up->uart_dma.prev_rx_dma_pos) ||
+   			     (curr_dma_pos == 0)) {
+   		if (jiffies_to_msecs(jiffies - up->port_activity) <
+ ! 						up->uart_dma.rx_timeout) {
+   			mod_timer(&up->uart_dma.rx_timer, jiffies +
+ ! 				usecs_to_jiffies(up->uart_dma.rx_poll_rate));
+   		} else {
+   			serial_omap_stop_rxdma(up);
+   			up->ier |= (UART_IER_RDI | UART_IER_RLSI);
+ ***************
+ *** 1120,1126 ****
+   		}
+   	} else  {
+   		mod_timer(&up->uart_dma.rx_timer, jiffies +
+ ! 			usecs_to_jiffies(up->uart_dma.rx_timeout));
+   	}
+   	up->port_activity = jiffies;
+   }
+ --- 1234,1240 ----
+   		}
+   	} else  {
+   		mod_timer(&up->uart_dma.rx_timer, jiffies +
+ ! 			usecs_to_jiffies(up->uart_dma.rx_poll_rate));
+   	}
+   	up->port_activity = jiffies;
+   }
+ ***************
+ *** 1135,1140 ****
+ --- 1249,1255 ----
+   	int ret = 0;
+   
+   	if (up->uart_dma.rx_dma_channel == -1) {
+ + 		pm_runtime_get_sync(&up->pdev->dev);
+   		ret = omap_request_dma(up->uart_dma.uart_dma_rx,
+   				"UART Rx DMA",
+   				(void *)uart_rx_dma_callback, up,
+ ***************
+ *** 1158,1164 ****
+   	/* FIXME: Cache maintenance needed here? */
+   	omap_start_dma(up->uart_dma.rx_dma_channel);
+   	mod_timer(&up->uart_dma.rx_timer, jiffies +
+ ! 				usecs_to_jiffies(up->uart_dma.rx_timeout));
+   	up->uart_dma.rx_dma_used = true;
+   	return ret;
+   }
+ --- 1273,1279 ----
+   	/* FIXME: Cache maintenance needed here? */
+   	omap_start_dma(up->uart_dma.rx_dma_channel);
+   	mod_timer(&up->uart_dma.rx_timer, jiffies +
+ ! 				usecs_to_jiffies(up->uart_dma.rx_poll_rate));
+   	up->uart_dma.rx_dma_used = true;
+   	return ret;
+   }
+ ***************
+ *** 1221,1226 ****
+ --- 1336,1354 ----
+   	return;
+   }
+   
+ + static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
+ + {
+ + 	struct omap_uart_port_info *omap_up_info;
+ + 
+ + 	omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
+ + 	if (!omap_up_info)
+ + 		return NULL; /* out of memory */
+ + 
+ + 	of_property_read_u32(dev->of_node, "clock-frequency",
+ + 					 &omap_up_info->uartclk);
+ + 	return omap_up_info;
+ + }
+ + 
+   static int serial_omap_probe(struct platform_device *pdev)
+   {
+   	struct uart_omap_port	*up;
+ ***************
+ *** 1228,1233 ****
+ --- 1356,1364 ----
+   	struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
+   	int ret = -ENOSPC;
+   
+ + 	if (pdev->dev.of_node)
+ + 		omap_up_info = of_get_uart_port_info(&pdev->dev);
+ + 
+   	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+   	if (!mem) {
+   		dev_err(&pdev->dev, "no mem resource?\n");
+ ***************
+ *** 1263,1269 ****
+   		ret = -ENOMEM;
+   		goto do_release_region;
+   	}
+ - 	sprintf(up->name, "OMAP UART%d", pdev->id);
+   	up->pdev = pdev;
+   	up->port.dev = &pdev->dev;
+   	up->port.type = PORT_OMAP;
+ --- 1394,1399 ----
+ ***************
+ *** 1273,1306 ****
+   	up->port.regshift = 2;
+   	up->port.fifosize = 64;
+   	up->port.ops = &serial_omap_pops;
+ - 	up->port.line = pdev->id;
+   
+ ! 	up->port.membase = omap_up_info->membase;
+ ! 	up->port.mapbase = omap_up_info->mapbase;
+   	up->port.flags = omap_up_info->flags;
+ - 	up->port.irqflags = omap_up_info->irqflags;
+   	up->port.uartclk = omap_up_info->uartclk;
+   	up->uart_dma.uart_base = mem->start;
+   
+   	if (omap_up_info->dma_enabled) {
+   		up->uart_dma.uart_dma_tx = dma_tx->start;
+   		up->uart_dma.uart_dma_rx = dma_rx->start;
+   		up->use_dma = 1;
+ ! 		up->uart_dma.rx_buf_size = 4096;
+ ! 		up->uart_dma.rx_timeout = 2;
+   		spin_lock_init(&(up->uart_dma.tx_lock));
+   		spin_lock_init(&(up->uart_dma.rx_lock));
+   		up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
+   		up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
+   	}
+   
+ ! 	ui[pdev->id] = up;
+   	serial_omap_add_console_port(up);
+   
+   	ret = uart_add_one_port(&serial_omap_reg, &up->port);
+   	if (ret != 0)
+   		goto do_release_region;
+   
+   	platform_set_drvdata(pdev, up);
+   	return 0;
+   err:
+ --- 1403,1476 ----
+   	up->port.regshift = 2;
+   	up->port.fifosize = 64;
+   	up->port.ops = &serial_omap_pops;
+   
+ ! 	if (pdev->dev.of_node)
+ ! 		up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
+ ! 	else
+ ! 		up->port.line = pdev->id;
+ ! 
+ ! 	if (up->port.line < 0) {
+ ! 		dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
+ ! 								up->port.line);
+ ! 		ret = -ENODEV;
+ ! 		goto err;
+ ! 	}
+ ! 
+ ! 	sprintf(up->name, "OMAP UART%d", up->port.line);
+ ! 	up->port.mapbase = mem->start;
+ ! 	up->port.membase = ioremap(mem->start, resource_size(mem));
+ ! 	if (!up->port.membase) {
+ ! 		dev_err(&pdev->dev, "can't ioremap UART\n");
+ ! 		ret = -ENOMEM;
+ ! 		goto err;
+ ! 	}
+ ! 
+   	up->port.flags = omap_up_info->flags;
+   	up->port.uartclk = omap_up_info->uartclk;
+ + 	if (!up->port.uartclk) {
+ + 		up->port.uartclk = DEFAULT_CLK_SPEED;
+ + 		dev_warn(&pdev->dev, "No clock speed specified: using default:"
+ + 						"%d\n", DEFAULT_CLK_SPEED);
+ + 	}
+   	up->uart_dma.uart_base = mem->start;
+ + 	up->errata = omap_up_info->errata;
+   
+   	if (omap_up_info->dma_enabled) {
+   		up->uart_dma.uart_dma_tx = dma_tx->start;
+   		up->uart_dma.uart_dma_rx = dma_rx->start;
+   		up->use_dma = 1;
+ ! 		up->uart_dma.rx_buf_size = omap_up_info->dma_rx_buf_size;
+ ! 		up->uart_dma.rx_timeout = omap_up_info->dma_rx_timeout;
+ ! 		up->uart_dma.rx_poll_rate = omap_up_info->dma_rx_poll_rate;
+   		spin_lock_init(&(up->uart_dma.tx_lock));
+   		spin_lock_init(&(up->uart_dma.rx_lock));
+   		up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
+   		up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
+   	}
+   
+ ! 	up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
+ ! 	up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
+ ! 	pm_qos_add_request(&up->pm_qos_request,
+ ! 		PM_QOS_CPU_DMA_LATENCY, up->latency);
+ ! 	serial_omap_uart_wq = create_singlethread_workqueue(up->name);
+ ! 	INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
+ ! 
+ ! 	pm_runtime_use_autosuspend(&pdev->dev);
+ ! 	pm_runtime_set_autosuspend_delay(&pdev->dev,
+ ! 			omap_up_info->autosuspend_timeout);
+ ! 
+ ! 	pm_runtime_irq_safe(&pdev->dev);
+ ! 	pm_runtime_enable(&pdev->dev);
+ ! 	pm_runtime_get_sync(&pdev->dev);
+ ! 
+ ! 	ui[up->port.line] = up;
+   	serial_omap_add_console_port(up);
+   
+   	ret = uart_add_one_port(&serial_omap_reg, &up->port);
+   	if (ret != 0)
+   		goto do_release_region;
+   
+ + 	pm_runtime_put(&pdev->dev);
+   	platform_set_drvdata(pdev, up);
+   	return 0;
+   err:
+ ***************
+ *** 1315,1336 ****
+   {
+   	struct uart_omap_port *up = platform_get_drvdata(dev);
+   
+ - 	platform_set_drvdata(dev, NULL);
+   	if (up) {
+   		uart_remove_one_port(&serial_omap_reg, &up->port);
+   		kfree(up);
+   	}
+   	return 0;
+   }
+   
+   static struct platform_driver serial_omap_driver = {
+   	.probe          = serial_omap_probe,
+   	.remove         = serial_omap_remove,
+ - 
+ - 	.suspend	= serial_omap_suspend,
+ - 	.resume		= serial_omap_resume,
+   	.driver		= {
+   		.name	= DRIVER_NAME,
+   	},
+   };
+   
+ --- 1485,1652 ----
+   {
+   	struct uart_omap_port *up = platform_get_drvdata(dev);
+   
+   	if (up) {
+ + 		pm_runtime_disable(&up->pdev->dev);
+   		uart_remove_one_port(&serial_omap_reg, &up->port);
+ + 		pm_qos_remove_request(&up->pm_qos_request);
+ + 
+   		kfree(up);
+   	}
+ + 
+ + 	platform_set_drvdata(dev, NULL);
+   	return 0;
+   }
+   
+ + /*
+ +  * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
+ +  * The access to uart register after MDR1 Access
+ +  * causes UART to corrupt data.
+ +  *
+ +  * Need a delay =
+ +  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
+ +  * give 10 times as much
+ +  */
+ + static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
+ + {
+ + 	u8 timeout = 255;
+ + 
+ + 	serial_out(up, UART_OMAP_MDR1, mdr1);
+ + 	udelay(2);
+ + 	serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
+ + 			UART_FCR_CLEAR_RCVR);
+ + 	/*
+ + 	 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
+ + 	 * TX_FIFO_E bit is 1.
+ + 	 */
+ + 	while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
+ + 				(UART_LSR_THRE | UART_LSR_DR))) {
+ + 		timeout--;
+ + 		if (!timeout) {
+ + 			/* Should *never* happen. we warn and carry on */
+ + 			dev_crit(&up->pdev->dev, "Errata i202: timedout %x\n",
+ + 						serial_in(up, UART_LSR));
+ + 			break;
+ + 		}
+ + 		udelay(1);
+ + 	}
+ + }
+ + 
+ + static void serial_omap_restore_context(struct uart_omap_port *up)
+ + {
+ + 	if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
+ + 		serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
+ + 	else
+ + 		serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
+ + 
+ + 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
+ + 	serial_out(up, UART_EFR, UART_EFR_ECB);
+ + 	serial_out(up, UART_LCR, 0x0); /* Operational mode */
+ + 	serial_out(up, UART_IER, 0x0);
+ + 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
+ + 	serial_out(up, UART_DLL, up->dll);
+ + 	serial_out(up, UART_DLM, up->dlh);
+ + 	serial_out(up, UART_LCR, 0x0); /* Operational mode */
+ + 	serial_out(up, UART_IER, up->ier);
+ + 	serial_out(up, UART_FCR, up->fcr);
+ + 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
+ + 	serial_out(up, UART_MCR, up->mcr);
+ + 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
+ + 	serial_out(up, UART_OMAP_SCR, up->scr);
+ + 	serial_out(up, UART_EFR, up->efr);
+ + 	serial_out(up, UART_LCR, up->lcr);
+ + 	if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
+ + 		serial_omap_mdr1_errataset(up, up->mdr1);
+ + 	else
+ + 		serial_out(up, UART_OMAP_MDR1, up->mdr1);
+ + }
+ + 
+ + #ifdef CONFIG_PM_RUNTIME
+ + static int serial_omap_runtime_suspend(struct device *dev)
+ + {
+ + 	struct uart_omap_port *up = dev_get_drvdata(dev);
+ + 	struct omap_uart_port_info *pdata = dev->platform_data;
+ + 
+ + 	if (!up)
+ + 		return -EINVAL;
+ + 
+ + 	if (!pdata || !pdata->enable_wakeup)
+ + 		return 0;
+ + 
+ + 	if (pdata->get_context_loss_count)
+ + 		up->context_loss_cnt = pdata->get_context_loss_count(dev);
+ + 
+ + 	if (device_may_wakeup(dev)) {
+ + 		if (!up->wakeups_enabled) {
+ + 			pdata->enable_wakeup(up->pdev, true);
+ + 			up->wakeups_enabled = true;
+ + 		}
+ + 	} else {
+ + 		if (up->wakeups_enabled) {
+ + 			pdata->enable_wakeup(up->pdev, false);
+ + 			up->wakeups_enabled = false;
+ + 		}
+ + 	}
+ + 
+ + 	/* Errata i291 */
+ + 	if (up->use_dma && pdata->set_forceidle &&
+ + 			(up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
+ + 		pdata->set_forceidle(up->pdev);
+ + 
+ + 	up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
+ + 	schedule_work(&up->qos_work);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static int serial_omap_runtime_resume(struct device *dev)
+ + {
+ + 	struct uart_omap_port *up = dev_get_drvdata(dev);
+ + 	struct omap_uart_port_info *pdata = dev->platform_data;
+ + 
+ + 	if (up) {
+ + 		if (pdata->get_context_loss_count) {
+ + 			u32 loss_cnt = pdata->get_context_loss_count(dev);
+ + 
+ + 			if (up->context_loss_cnt != loss_cnt)
+ + 				serial_omap_restore_context(up);
+ + 		}
+ + 
+ + 		/* Errata i291 */
+ + 		if (up->use_dma && pdata->set_noidle &&
+ + 				(up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
+ + 			pdata->set_noidle(up->pdev);
+ + 
+ + 		up->latency = up->calc_latency;
+ + 		schedule_work(&up->qos_work);
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ + #endif
+ + 
+ + static const struct dev_pm_ops serial_omap_dev_pm_ops = {
+ + 	SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
+ + 	SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
+ + 				serial_omap_runtime_resume, NULL)
+ + };
+ + 
+ + #if defined(CONFIG_OF)
+ + static const struct of_device_id omap_serial_of_match[] = {
+ + 	{ .compatible = "ti,omap2-uart" },
+ + 	{ .compatible = "ti,omap3-uart" },
+ + 	{ .compatible = "ti,omap4-uart" },
+ + 	{},
+ + };
+ + MODULE_DEVICE_TABLE(of, omap_serial_of_match);
+ + #endif
+ + 
+   static struct platform_driver serial_omap_driver = {
+   	.probe          = serial_omap_probe,
+   	.remove         = serial_omap_remove,
+   	.driver		= {
+   		.name	= DRIVER_NAME,
+ + 		.pm	= &serial_omap_dev_pm_ops,
+ + 		.of_match_table = of_match_ptr(omap_serial_of_match),
+   	},
+   };
+   
+ diff -crN linux-3.2.1_o/drivers/uio/Kconfig linux-3.2.1/drivers/uio/Kconfig
+ *** linux-3.2.1_o/drivers/uio/Kconfig	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/uio/Kconfig	2014-11-25 13:19:16.223044521 +0900
+ ***************
+ *** 96,104 ****
+   
+   config UIO_PRUSS
+   	tristate "Texas Instruments PRUSS driver"
+ ! 	depends on ARCH_DAVINCI_DA850
+   	help
+ ! 	  PRUSS driver for OMAPL138/DA850/AM18XX devices
+   	  PRUSS driver requires user space components, examples and user space
+   	  driver is available from below SVN repo - you may use anonymous login
+   
+ --- 96,104 ----
+   
+   config UIO_PRUSS
+   	tristate "Texas Instruments PRUSS driver"
+ ! 	depends on ARCH_DAVINCI_DA850 || SOC_OMAPAM33XX
+   	help
+ ! 	  PRUSS driver for OMAPL138/DA850/AM18XX/AM33XX devices
+   	  PRUSS driver requires user space components, examples and user space
+   	  driver is available from below SVN repo - you may use anonymous login
+   
+ diff -crN linux-3.2.1_o/drivers/uio/uio_pruss.c linux-3.2.1/drivers/uio/uio_pruss.c
+ *** linux-3.2.1_o/drivers/uio/uio_pruss.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/uio/uio_pruss.c	2014-11-25 13:19:16.227067448 +0900
+ ***************
+ *** 25,31 ****
+ --- 25,38 ----
+   #include <linux/clk.h>
+   #include <linux/dma-mapping.h>
+   #include <linux/slab.h>
+ + 
+ + #ifdef ARCH_DAVINCI_DA850
+ + #define ENABLE_SRAM_SUPPORT
+ + #endif
+ + 
+ + #ifdef ENABLE_SRAM_SUPPORT
+   #include <mach/sram.h>
+ + #endif
+   
+   #define DRV_NAME "pruss_uio"
+   #define DRV_VERSION "1.0"
+ ***************
+ *** 62,68 ****
+   struct uio_pruss_dev {
+   	struct uio_info *info;
+   	struct clk *pruss_clk;
+ ! 	dma_addr_t sram_paddr;
+   	dma_addr_t ddr_paddr;
+   	void __iomem *prussio_vaddr;
+   	void *sram_vaddr;
+ --- 69,75 ----
+   struct uio_pruss_dev {
+   	struct uio_info *info;
+   	struct clk *pruss_clk;
+ ! 	phys_addr_t sram_paddr;
+   	dma_addr_t ddr_paddr;
+   	void __iomem *prussio_vaddr;
+   	void *sram_vaddr;
+ ***************
+ *** 105,112 ****
+   		dma_free_coherent(&dev->dev, extram_pool_sz, gdev->ddr_vaddr,
+   			gdev->ddr_paddr);
+   	}
+   	if (gdev->sram_vaddr)
+ ! 		sram_free(gdev->sram_vaddr, sram_pool_sz);
+   	kfree(gdev->info);
+   	clk_put(gdev->pruss_clk);
+   	kfree(gdev);
+ --- 112,122 ----
+   		dma_free_coherent(&dev->dev, extram_pool_sz, gdev->ddr_vaddr,
+   			gdev->ddr_paddr);
+   	}
+ + #ifdef ENABLE_SRAM_SUPPORT
+   	if (gdev->sram_vaddr)
+ ! 		gen_pool_free(davinci_gen_pool,
+ ! 			      (unsigned long)gdev->sram_vaddr, sram_pool_sz);
+ ! #endif
+   	kfree(gdev->info);
+   	clk_put(gdev->pruss_clk);
+   	kfree(gdev);
+ ***************
+ *** 152,163 ****
+   		goto out_free;
+   	}
+   
+ ! 	gdev->sram_vaddr = sram_alloc(sram_pool_sz, &(gdev->sram_paddr));
+   	if (!gdev->sram_vaddr) {
+   		dev_err(&dev->dev, "Could not allocate SRAM pool\n");
+   		goto out_free;
+   	}
+   
+   	gdev->ddr_vaddr = dma_alloc_coherent(&dev->dev, extram_pool_sz,
+   				&(gdev->ddr_paddr), GFP_KERNEL | GFP_DMA);
+   	if (!gdev->ddr_vaddr) {
+ --- 162,178 ----
+   		goto out_free;
+   	}
+   
+ ! #ifdef ENABLE_SRAM_SUPPORT
+ ! 	gdev->sram_vaddr = (void *)gen_pool_alloc(davinci_gen_pool,
+ ! 						  sram_pool_sz);
+   	if (!gdev->sram_vaddr) {
+   		dev_err(&dev->dev, "Could not allocate SRAM pool\n");
+   		goto out_free;
+   	}
+   
+ + 	gdev->sram_paddr = gen_pool_virt_to_phys(davinci_gen_pool,
+ + 					(unsigned long)gdev->sram_vaddr);
+ + #endif
+   	gdev->ddr_vaddr = dma_alloc_coherent(&dev->dev, extram_pool_sz,
+   				&(gdev->ddr_paddr), GFP_KERNEL | GFP_DMA);
+   	if (!gdev->ddr_vaddr) {
+ ***************
+ *** 179,186 ****
+   		p->mem[0].addr = regs_prussio->start;
+   		p->mem[0].size = resource_size(regs_prussio);
+   		p->mem[0].memtype = UIO_MEM_PHYS;
+ - 
+ - 		p->mem[1].addr = gdev->sram_paddr;
+   		p->mem[1].size = sram_pool_sz;
+   		p->mem[1].memtype = UIO_MEM_PHYS;
+   
+ --- 194,199 ----
+ diff -crN linux-3.2.1_o/drivers/usb/class/cdc-acm.c linux-3.2.1/drivers/usb/class/cdc-acm.c
+ *** linux-3.2.1_o/drivers/usb/class/cdc-acm.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/class/cdc-acm.c	2014-11-25 13:19:16.231052413 +0900
+ ***************
+ *** 554,571 ****
+   
+   static void acm_tty_hangup(struct tty_struct *tty)
+   {
+ ! 	struct acm *acm;
+ ! 
+ ! 	mutex_lock(&open_mutex);
+ ! 	acm = tty->driver_data;
+ ! 
+ ! 	if (!acm)
+ ! 		goto out;
+ ! 
+   	tty_port_hangup(&acm->port);
+   	acm_port_down(acm);
+ - 
+ - out:
+   	mutex_unlock(&open_mutex);
+   }
+   
+ --- 554,563 ----
+   
+   static void acm_tty_hangup(struct tty_struct *tty)
+   {
+ ! 	struct acm *acm = tty->driver_data;
+   	tty_port_hangup(&acm->port);
+ + 	mutex_lock(&open_mutex);
+   	acm_port_down(acm);
+   	mutex_unlock(&open_mutex);
+   }
+   
+ ***************
+ *** 1191,1198 ****
+   		i = device_create_file(&intf->dev, &dev_attr_wCountryCodes);
+   		if (i < 0) {
+   			kfree(acm->country_codes);
+ - 			acm->country_codes = NULL;
+ - 			acm->country_code_size = 0;
+   			goto skip_countries;
+   		}
+   
+ --- 1183,1188 ----
+ ***************
+ *** 1201,1208 ****
+   		if (i < 0) {
+   			device_remove_file(&intf->dev, &dev_attr_wCountryCodes);
+   			kfree(acm->country_codes);
+ - 			acm->country_codes = NULL;
+ - 			acm->country_code_size = 0;
+   			goto skip_countries;
+   		}
+   	}
+ --- 1191,1196 ----
+ diff -crN linux-3.2.1_o/drivers/usb/core/devio.c linux-3.2.1/drivers/usb/core/devio.c
+ *** linux-3.2.1_o/drivers/usb/core/devio.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/core/devio.c	2014-11-25 13:19:16.235047544 +0900
+ ***************
+ *** 249,256 ****
+   static void free_async(struct async *as)
+   {
+   	put_pid(as->pid);
+ ! 	if (as->cred)
+ ! 		put_cred(as->cred);
+   	kfree(as->urb->transfer_buffer);
+   	kfree(as->urb->setup_packet);
+   	usb_free_urb(as->urb);
+ --- 249,255 ----
+   static void free_async(struct async *as)
+   {
+   	put_pid(as->pid);
+ ! 	put_cred(as->cred);
+   	kfree(as->urb->transfer_buffer);
+   	kfree(as->urb->setup_packet);
+   	usb_free_urb(as->urb);
+ diff -crN linux-3.2.1_o/drivers/usb/core/hcd.c linux-3.2.1/drivers/usb/core/hcd.c
+ *** linux-3.2.1_o/drivers/usb/core/hcd.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/core/hcd.c	2014-11-25 13:19:16.235047544 +0900
+ ***************
+ *** 1412,1421 ****
+   					ret = -EAGAIN;
+   				else
+   					urb->transfer_flags |= URB_DMA_MAP_SG;
+ ! 				urb->num_mapped_sgs = n;
+ ! 				if (n != urb->num_sgs)
+   					urb->transfer_flags |=
+   							URB_DMA_SG_COMBINED;
+   			} else if (urb->sg) {
+   				struct scatterlist *sg = urb->sg;
+   				urb->transfer_dma = dma_map_page(
+ --- 1412,1422 ----
+   					ret = -EAGAIN;
+   				else
+   					urb->transfer_flags |= URB_DMA_MAP_SG;
+ ! 				if (n != urb->num_sgs) {
+ ! 					urb->num_sgs = n;
+   					urb->transfer_flags |=
+   							URB_DMA_SG_COMBINED;
+ + 				}
+   			} else if (urb->sg) {
+   				struct scatterlist *sg = urb->sg;
+   				urb->transfer_dma = dma_map_page(
+ diff -crN linux-3.2.1_o/drivers/usb/core/hub.c linux-3.2.1/drivers/usb/core/hub.c
+ *** linux-3.2.1_o/drivers/usb/core/hub.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/core/hub.c	2014-11-25 13:19:16.239045643 +0900
+ ***************
+ *** 1296,1302 ****
+   	 * since that isn't a "real" hub.
+   	 */
+   	if (!hub_is_superspeed(hdev) || !hdev->parent)
+ ! 		usb_enable_autosuspend(hdev);
+   
+   	if (hdev->level == MAX_TOPO_LEVEL) {
+   		dev_err(&intf->dev,
+ --- 1296,1302 ----
+   	 * since that isn't a "real" hub.
+   	 */
+   	if (!hub_is_superspeed(hdev) || !hdev->parent)
+ ! 		usb_disable_autosuspend(hdev);
+   
+   	if (hdev->level == MAX_TOPO_LEVEL) {
+   		dev_err(&intf->dev,
+ diff -crN linux-3.2.1_o/drivers/usb/core/quirks.c linux-3.2.1/drivers/usb/core/quirks.c
+ *** linux-3.2.1_o/drivers/usb/core/quirks.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/core/quirks.c	2014-11-25 13:19:16.239045643 +0900
+ ***************
+ *** 117,127 ****
+   	{ USB_DEVICE(0x06a3, 0x0006), .driver_info =
+   			USB_QUIRK_CONFIG_INTF_STRINGS },
+   
+ - 	/* Guillemot Webcam Hercules Dualpix Exchange (2nd ID) */
+ - 	{ USB_DEVICE(0x06f8, 0x0804), .driver_info = USB_QUIRK_RESET_RESUME },
+ - 
+   	/* Guillemot Webcam Hercules Dualpix Exchange*/
+ ! 	{ USB_DEVICE(0x06f8, 0x3005), .driver_info = USB_QUIRK_RESET_RESUME },
+   
+   	/* M-Systems Flash Disk Pioneers */
+   	{ USB_DEVICE(0x08ec, 0x1000), .driver_info = USB_QUIRK_RESET_RESUME },
+ --- 117,124 ----
+   	{ USB_DEVICE(0x06a3, 0x0006), .driver_info =
+   			USB_QUIRK_CONFIG_INTF_STRINGS },
+   
+   	/* Guillemot Webcam Hercules Dualpix Exchange*/
+ ! 	{ USB_DEVICE(0x06f8, 0x0804), .driver_info = USB_QUIRK_RESET_RESUME },
+   
+   	/* M-Systems Flash Disk Pioneers */
+   	{ USB_DEVICE(0x08ec, 0x1000), .driver_info = USB_QUIRK_RESET_RESUME },
+ diff -crN linux-3.2.1_o/drivers/usb/dwc3/gadget.c linux-3.2.1/drivers/usb/dwc3/gadget.c
+ *** linux-3.2.1_o/drivers/usb/dwc3/gadget.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/dwc3/gadget.c	2014-11-25 13:19:16.239045643 +0900
+ ***************
+ *** 1986,1992 ****
+   	dev_set_name(&dwc->gadget.dev, "gadget");
+   
+   	dwc->gadget.ops			= &dwc3_gadget_ops;
+ ! 	dwc->gadget.is_dualspeed	= true;
+   	dwc->gadget.speed		= USB_SPEED_UNKNOWN;
+   	dwc->gadget.dev.parent		= dwc->dev;
+   
+ --- 1986,1992 ----
+   	dev_set_name(&dwc->gadget.dev, "gadget");
+   
+   	dwc->gadget.ops			= &dwc3_gadget_ops;
+ ! 	dwc->gadget.max_speed		= USB_SPEED_SUPER;
+   	dwc->gadget.speed		= USB_SPEED_UNKNOWN;
+   	dwc->gadget.dev.parent		= dwc->dev;
+   
+ diff -crN linux-3.2.1_o/drivers/usb/gadget/amd5536udc.c linux-3.2.1/drivers/usb/gadget/amd5536udc.c
+ *** linux-3.2.1_o/drivers/usb/gadget/amd5536udc.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/gadget/amd5536udc.c	2014-11-25 13:19:16.263034063 +0900
+ ***************
+ *** 1959,1965 ****
+   	u32 tmp;
+   
+   	if (!driver || !bind || !driver->setup
+ ! 			|| driver->speed < USB_SPEED_HIGH)
+   		return -EINVAL;
+   	if (!dev)
+   		return -ENODEV;
+ --- 1959,1965 ----
+   	u32 tmp;
+   
+   	if (!driver || !bind || !driver->setup
+ ! 			|| driver->max_speed < USB_SPEED_HIGH)
+   		return -EINVAL;
+   	if (!dev)
+   		return -ENODEV;
+ ***************
+ *** 3349,3355 ****
+   	dev_set_name(&dev->gadget.dev, "gadget");
+   	dev->gadget.dev.release = gadget_release;
+   	dev->gadget.name = name;
+ ! 	dev->gadget.is_dualspeed = 1;
+   
+   	/* init registers, interrupts, ... */
+   	startup_registers(dev);
+ --- 3349,3355 ----
+   	dev_set_name(&dev->gadget.dev, "gadget");
+   	dev->gadget.dev.release = gadget_release;
+   	dev->gadget.name = name;
+ ! 	dev->gadget.max_speed = USB_SPEED_HIGH;
+   
+   	/* init registers, interrupts, ... */
+   	startup_registers(dev);
+ diff -crN linux-3.2.1_o/drivers/usb/gadget/at91_udc.c linux-3.2.1/drivers/usb/gadget/at91_udc.c
+ *** linux-3.2.1_o/drivers/usb/gadget/at91_udc.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/gadget/at91_udc.c	2014-11-25 13:19:16.263034063 +0900
+ ***************
+ *** 1633,1639 ****
+   	unsigned long	flags;
+   
+   	if (!driver
+ ! 			|| driver->speed < USB_SPEED_FULL
+   			|| !bind
+   			|| !driver->setup) {
+   		DBG("bad parameter.\n");
+ --- 1633,1639 ----
+   	unsigned long	flags;
+   
+   	if (!driver
+ ! 			|| driver->max_speed < USB_SPEED_FULL
+   			|| !bind
+   			|| !driver->setup) {
+   		DBG("bad parameter.\n");
+ diff -crN linux-3.2.1_o/drivers/usb/gadget/atmel_usba_udc.c linux-3.2.1/drivers/usb/gadget/atmel_usba_udc.c
+ *** linux-3.2.1_o/drivers/usb/gadget/atmel_usba_udc.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/gadget/atmel_usba_udc.c	2014-11-25 13:19:16.267046204 +0900
+ ***************
+ *** 1038,1044 ****
+   	.gadget	= {
+   		.ops		= &usba_udc_ops,
+   		.ep_list	= LIST_HEAD_INIT(the_udc.gadget.ep_list),
+ ! 		.is_dualspeed	= 1,
+   		.name		= "atmel_usba_udc",
+   		.dev	= {
+   			.init_name	= "gadget",
+ --- 1038,1044 ----
+   	.gadget	= {
+   		.ops		= &usba_udc_ops,
+   		.ep_list	= LIST_HEAD_INIT(the_udc.gadget.ep_list),
+ ! 		.max_speed	= USB_SPEED_HIGH,
+   		.name		= "atmel_usba_udc",
+   		.dev	= {
+   			.init_name	= "gadget",
+ diff -crN linux-3.2.1_o/drivers/usb/gadget/ci13xxx_udc.c linux-3.2.1/drivers/usb/gadget/ci13xxx_udc.c
+ *** linux-3.2.1_o/drivers/usb/gadget/ci13xxx_udc.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/gadget/ci13xxx_udc.c	2014-11-25 13:19:16.271090628 +0900
+ ***************
+ *** 754,761 ****
+   
+   	n += scnprintf(buf + n, PAGE_SIZE - n, "speed             = %d\n",
+   		       gadget->speed);
+   	n += scnprintf(buf + n, PAGE_SIZE - n, "is_dualspeed      = %d\n",
+ ! 		       gadget->is_dualspeed);
+   	n += scnprintf(buf + n, PAGE_SIZE - n, "is_otg            = %d\n",
+   		       gadget->is_otg);
+   	n += scnprintf(buf + n, PAGE_SIZE - n, "is_a_peripheral   = %d\n",
+ --- 754,764 ----
+   
+   	n += scnprintf(buf + n, PAGE_SIZE - n, "speed             = %d\n",
+   		       gadget->speed);
+ + 	n += scnprintf(buf + n, PAGE_SIZE - n, "max_speed         = %d\n",
+ + 		       gadget->max_speed);
+ + 	/* TODO: Scheduled for removal in 3.8. */
+   	n += scnprintf(buf + n, PAGE_SIZE - n, "is_dualspeed      = %d\n",
+ ! 		       gadget_is_dualspeed(gadget));
+   	n += scnprintf(buf + n, PAGE_SIZE - n, "is_otg            = %d\n",
+   		       gadget->is_otg);
+   	n += scnprintf(buf + n, PAGE_SIZE - n, "is_a_peripheral   = %d\n",
+ ***************
+ *** 798,804 ****
+   	n += scnprintf(buf + n, PAGE_SIZE - n, "function  = %s\n",
+   		       (driver->function ? driver->function : ""));
+   	n += scnprintf(buf + n, PAGE_SIZE - n, "max speed = %d\n",
+ ! 		       driver->speed);
+   
+   	return n;
+   }
+ --- 801,807 ----
+   	n += scnprintf(buf + n, PAGE_SIZE - n, "function  = %s\n",
+   		       (driver->function ? driver->function : ""));
+   	n += scnprintf(buf + n, PAGE_SIZE - n, "max speed = %d\n",
+ ! 		       driver->max_speed);
+   
+   	return n;
+   }
+ ***************
+ *** 2871,2877 ****
+   
+   	udc->gadget.ops          = &usb_gadget_ops;
+   	udc->gadget.speed        = USB_SPEED_UNKNOWN;
+ ! 	udc->gadget.is_dualspeed = 1;
+   	udc->gadget.is_otg       = 0;
+   	udc->gadget.name         = driver->name;
+   
+ --- 2874,2880 ----
+   
+   	udc->gadget.ops          = &usb_gadget_ops;
+   	udc->gadget.speed        = USB_SPEED_UNKNOWN;
+ ! 	udc->gadget.max_speed    = USB_SPEED_HIGH;
+   	udc->gadget.is_otg       = 0;
+   	udc->gadget.name         = driver->name;
+   
+ diff -crN linux-3.2.1_o/drivers/usb/gadget/composite.c linux-3.2.1/drivers/usb/gadget/composite.c
+ *** linux-3.2.1_o/drivers/usb/gadget/composite.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/gadget/composite.c	2014-11-25 13:19:16.275091282 +0900
+ ***************
+ *** 1535,1543 ****
+   
+   static struct usb_gadget_driver composite_driver = {
+   #ifdef CONFIG_USB_GADGET_SUPERSPEED
+ ! 	.speed		= USB_SPEED_SUPER,
+   #else
+ ! 	.speed		= USB_SPEED_HIGH,
+   #endif
+   
+   	.unbind		= composite_unbind,
+ --- 1535,1543 ----
+   
+   static struct usb_gadget_driver composite_driver = {
+   #ifdef CONFIG_USB_GADGET_SUPERSPEED
+ ! 	.max_speed	= USB_SPEED_SUPER,
+   #else
+ ! 	.max_speed	= USB_SPEED_HIGH,
+   #endif
+   
+   	.unbind		= composite_unbind,
+ ***************
+ *** 1584,1591 ****
+   		driver->iProduct = driver->name;
+   	composite_driver.function =  (char *) driver->name;
+   	composite_driver.driver.name = driver->name;
+ ! 	composite_driver.speed = min((u8)composite_driver.speed,
+ ! 				     (u8)driver->max_speed);
+   	composite = driver;
+   	composite_gadget_bind = bind;
+   
+ --- 1584,1591 ----
+   		driver->iProduct = driver->name;
+   	composite_driver.function =  (char *) driver->name;
+   	composite_driver.driver.name = driver->name;
+ ! 	composite_driver.max_speed =
+ ! 		min_t(u8, composite_driver.max_speed, driver->max_speed);
+   	composite = driver;
+   	composite_gadget_bind = bind;
+   
+ diff -crN linux-3.2.1_o/drivers/usb/gadget/dbgp.c linux-3.2.1/drivers/usb/gadget/dbgp.c
+ *** linux-3.2.1_o/drivers/usb/gadget/dbgp.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/gadget/dbgp.c	2014-11-25 13:19:16.275091282 +0900
+ ***************
+ *** 404,410 ****
+   
+   static struct usb_gadget_driver dbgp_driver = {
+   	.function = "dbgp",
+ ! 	.speed = USB_SPEED_HIGH,
+   	.unbind = dbgp_unbind,
+   	.setup = dbgp_setup,
+   	.disconnect = dbgp_disconnect,
+ --- 404,410 ----
+   
+   static struct usb_gadget_driver dbgp_driver = {
+   	.function = "dbgp",
+ ! 	.max_speed = USB_SPEED_HIGH,
+   	.unbind = dbgp_unbind,
+   	.setup = dbgp_setup,
+   	.disconnect = dbgp_disconnect,
+ diff -crN linux-3.2.1_o/drivers/usb/gadget/dummy_hcd.c linux-3.2.1/drivers/usb/gadget/dummy_hcd.c
+ *** linux-3.2.1_o/drivers/usb/gadget/dummy_hcd.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/gadget/dummy_hcd.c	2014-11-25 13:19:16.279051187 +0900
+ ***************
+ *** 823,841 ****
+   
+   	if (value && dum->driver) {
+   		if (mod_data.is_super_speed)
+ ! 			dum->gadget.speed = dum->driver->speed;
+   		else if (mod_data.is_high_speed)
+   			dum->gadget.speed = min_t(u8, USB_SPEED_HIGH,
+ ! 					dum->driver->speed);
+   		else
+   			dum->gadget.speed = USB_SPEED_FULL;
+   		dummy_udc_udpate_ep0(dum);
+   
+ ! 		if (dum->gadget.speed < dum->driver->speed)
+   			dev_dbg(udc_dev(dum), "This device can perform faster"
+ ! 					" if you connect it to a %s port...\n",
+ ! 					(dum->driver->speed == USB_SPEED_SUPER ?
+ ! 					 "SuperSpeed" : "HighSpeed"));
+   	}
+   	dum_hcd = gadget_to_dummy_hcd(_gadget);
+   
+ --- 823,840 ----
+   
+   	if (value && dum->driver) {
+   		if (mod_data.is_super_speed)
+ ! 			dum->gadget.speed = dum->driver->max_speed;
+   		else if (mod_data.is_high_speed)
+   			dum->gadget.speed = min_t(u8, USB_SPEED_HIGH,
+ ! 					dum->driver->max_speed);
+   		else
+   			dum->gadget.speed = USB_SPEED_FULL;
+   		dummy_udc_udpate_ep0(dum);
+   
+ ! 		if (dum->gadget.speed < dum->driver->max_speed)
+   			dev_dbg(udc_dev(dum), "This device can perform faster"
+ ! 				" if you connect it to a %s port...\n",
+ ! 				usb_speed_string(dum->driver->max_speed));
+   	}
+   	dum_hcd = gadget_to_dummy_hcd(_gadget);
+   
+ ***************
+ *** 898,904 ****
+   	struct dummy_hcd	*dum_hcd = gadget_to_dummy_hcd(g);
+   	struct dummy		*dum = dum_hcd->dum;
+   
+ ! 	if (driver->speed == USB_SPEED_UNKNOWN)
+   		return -EINVAL;
+   
+   	/*
+ --- 897,903 ----
+   	struct dummy_hcd	*dum_hcd = gadget_to_dummy_hcd(g);
+   	struct dummy		*dum = dum_hcd->dum;
+   
+ ! 	if (driver->max_speed == USB_SPEED_UNKNOWN)
+   		return -EINVAL;
+   
+   	/*
+ ***************
+ *** 977,983 ****
+   
+   	dum->gadget.name = gadget_name;
+   	dum->gadget.ops = &dummy_ops;
+ ! 	dum->gadget.is_dualspeed = 1;
+   
+   	dev_set_name(&dum->gadget.dev, "gadget");
+   	dum->gadget.dev.parent = &pdev->dev;
+ --- 976,982 ----
+   
+   	dum->gadget.name = gadget_name;
+   	dum->gadget.ops = &dummy_ops;
+ ! 	dum->gadget.max_speed = USB_SPEED_SUPER;
+   
+   	dev_set_name(&dum->gadget.dev, "gadget");
+   	dum->gadget.dev.parent = &pdev->dev;
+ diff -crN linux-3.2.1_o/drivers/usb/gadget/epautoconf.c linux-3.2.1/drivers/usb/gadget/epautoconf.c
+ *** linux-3.2.1_o/drivers/usb/gadget/epautoconf.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/gadget/epautoconf.c	2014-11-25 13:19:16.279051187 +0900
+ ***************
+ *** 149,155 ****
+   	switch (type) {
+   	case USB_ENDPOINT_XFER_INT:
+   		/* INT:  limit 64 bytes full speed, 1024 high/super speed */
+ ! 		if (!gadget->is_dualspeed && max > 64)
+   			return 0;
+   		/* FALLTHROUGH */
+   
+ --- 149,155 ----
+   	switch (type) {
+   	case USB_ENDPOINT_XFER_INT:
+   		/* INT:  limit 64 bytes full speed, 1024 high/super speed */
+ ! 		if (!gadget_is_dualspeed(gadget) && max > 64)
+   			return 0;
+   		/* FALLTHROUGH */
+   
+ ***************
+ *** 157,168 ****
+   		/* ISO:  limit 1023 bytes full speed, 1024 high/super speed */
+   		if (ep->maxpacket < max)
+   			return 0;
+ ! 		if (!gadget->is_dualspeed && max > 1023)
+   			return 0;
+   
+   		/* BOTH:  "high bandwidth" works only at high speed */
+   		if ((desc->wMaxPacketSize & cpu_to_le16(3<<11))) {
+ ! 			if (!gadget->is_dualspeed)
+   				return 0;
+   			/* configure your hardware with enough buffering!! */
+   		}
+ --- 157,168 ----
+   		/* ISO:  limit 1023 bytes full speed, 1024 high/super speed */
+   		if (ep->maxpacket < max)
+   			return 0;
+ ! 		if (!gadget_is_dualspeed(gadget) && max > 1023)
+   			return 0;
+   
+   		/* BOTH:  "high bandwidth" works only at high speed */
+   		if ((desc->wMaxPacketSize & cpu_to_le16(3<<11))) {
+ ! 			if (!gadget_is_dualspeed(gadget))
+   				return 0;
+   			/* configure your hardware with enough buffering!! */
+   		}
+ ***************
+ *** 380,385 ****
+ --- 380,386 ----
+   
+   	list_for_each_entry (ep, &gadget->ep_list, ep_list) {
+   		ep->driver_data = NULL;
+ + 		ep->desc = NULL;
+   	}
+   #ifdef	MANY_ENDPOINTS
+   	in_epnum = 0;
+ diff -crN linux-3.2.1_o/drivers/usb/gadget/ether.c linux-3.2.1/drivers/usb/gadget/ether.c
+ *** linux-3.2.1_o/drivers/usb/gadget/ether.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/gadget/ether.c	2014-11-25 13:19:16.283048292 +0900
+ ***************
+ *** 93,98 ****
+ --- 93,102 ----
+   #endif
+   }
+   
+ + static char manufacturer[50];
+ + 
+ + static u16 vendorID;
+ + 
+   /*-------------------------------------------------------------------------*/
+   
+   /*
+ ***************
+ *** 201,208 ****
+   #define STRING_MANUFACTURER_IDX		0
+   #define STRING_PRODUCT_IDX		1
+   
+ - static char manufacturer[50];
+ - 
+   static struct usb_string strings_dev[] = {
+   	[STRING_MANUFACTURER_IDX].s = manufacturer,
+   	[STRING_PRODUCT_IDX].s = PREFIX DRIVER_DESC,
+ --- 205,210 ----
+ ***************
+ *** 323,328 ****
+ --- 325,332 ----
+   		device_desc.bNumConfigurations = 2;
+   	}
+   
+ + 	vendorID = device_desc.idVendor;
+ + 
+   	gcnum = usb_gadget_controller_number(gadget);
+   	if (gcnum >= 0)
+   		device_desc.bcdDevice = cpu_to_le16(0x0300 | gcnum);
+ diff -crN linux-3.2.1_o/drivers/usb/gadget/f_ecm.c linux-3.2.1/drivers/usb/gadget/f_ecm.c
+ *** linux-3.2.1_o/drivers/usb/gadget/f_ecm.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/gadget/f_ecm.c	2014-11-25 13:19:16.283048292 +0900
+ ***************
+ *** 690,695 ****
+ --- 690,696 ----
+   	status = -ENODEV;
+   
+   	/* allocate instance-specific endpoints */
+ + 	usb_ep_autoconfig_reset(cdev->gadget);
+   	ep = usb_ep_autoconfig(cdev->gadget, &fs_ecm_in_desc);
+   	if (!ep)
+   		goto fail;
+ diff -crN linux-3.2.1_o/drivers/usb/gadget/file_storage.c linux-3.2.1/drivers/usb/gadget/file_storage.c
+ *** linux-3.2.1_o/drivers/usb/gadget/file_storage.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/gadget/file_storage.c	2014-11-25 13:19:16.287049396 +0900
+ ***************
+ *** 3584,3590 ****
+   /*-------------------------------------------------------------------------*/
+   
+   static struct usb_gadget_driver		fsg_driver = {
+ ! 	.speed		= USB_SPEED_SUPER,
+   	.function	= (char *) fsg_string_product,
+   	.unbind		= fsg_unbind,
+   	.disconnect	= fsg_disconnect,
+ --- 3584,3590 ----
+   /*-------------------------------------------------------------------------*/
+   
+   static struct usb_gadget_driver		fsg_driver = {
+ ! 	.max_speed	= USB_SPEED_SUPER,
+   	.function	= (char *) fsg_string_product,
+   	.unbind		= fsg_unbind,
+   	.disconnect	= fsg_disconnect,
+ diff -crN linux-3.2.1_o/drivers/usb/gadget/f_rndis.c linux-3.2.1/drivers/usb/gadget/f_rndis.c
+ *** linux-3.2.1_o/drivers/usb/gadget/f_rndis.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/gadget/f_rndis.c	2014-11-25 13:19:16.287049396 +0900
+ ***************
+ *** 684,689 ****
+ --- 684,690 ----
+   	status = -ENODEV;
+   
+   	/* allocate instance-specific endpoints */
+ + 	usb_ep_autoconfig_reset(cdev->gadget);
+   	ep = usb_ep_autoconfig(cdev->gadget, &fs_in_desc);
+   	if (!ep)
+   		goto fail;
+ ***************
+ *** 767,778 ****
+   	rndis_set_param_medium(rndis->config, NDIS_MEDIUM_802_3, 0);
+   	rndis_set_host_mac(rndis->config, rndis->ethaddr);
+   
+ - #if 0
+ - // FIXME
+   	if (rndis_set_param_vendor(rndis->config, vendorID,
+   				manufacturer))
+ ! 		goto fail0;
+ ! #endif
+   
+   	/* NOTE:  all that is done without knowing or caring about
+   	 * the network link ... which is unavailable to this code
+ --- 768,776 ----
+   	rndis_set_param_medium(rndis->config, NDIS_MEDIUM_802_3, 0);
+   	rndis_set_host_mac(rndis->config, rndis->ethaddr);
+   
+   	if (rndis_set_param_vendor(rndis->config, vendorID,
+   				manufacturer))
+ ! 		goto fail;
+   
+   	/* NOTE:  all that is done without knowing or caring about
+   	 * the network link ... which is unavailable to this code
+ diff -crN linux-3.2.1_o/drivers/usb/gadget/fsl_qe_udc.c linux-3.2.1/drivers/usb/gadget/fsl_qe_udc.c
+ *** linux-3.2.1_o/drivers/usb/gadget/fsl_qe_udc.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/gadget/fsl_qe_udc.c	2014-11-25 13:19:16.287049396 +0900
+ ***************
+ *** 2336,2342 ****
+   	if (!udc_controller)
+   		return -ENODEV;
+   
+ ! 	if (!driver || driver->speed < USB_SPEED_FULL
+   			|| !bind || !driver->disconnect || !driver->setup)
+   		return -EINVAL;
+   
+ --- 2336,2342 ----
+   	if (!udc_controller)
+   		return -ENODEV;
+   
+ ! 	if (!driver || driver->max_speed < USB_SPEED_FULL
+   			|| !bind || !driver->disconnect || !driver->setup)
+   		return -EINVAL;
+   
+ ***************
+ *** 2350,2356 ****
+   	/* hook up the driver */
+   	udc_controller->driver = driver;
+   	udc_controller->gadget.dev.driver = &driver->driver;
+ ! 	udc_controller->gadget.speed = (enum usb_device_speed)(driver->speed);
+   	spin_unlock_irqrestore(&udc_controller->lock, flags);
+   
+   	retval = bind(&udc_controller->gadget);
+ --- 2350,2356 ----
+   	/* hook up the driver */
+   	udc_controller->driver = driver;
+   	udc_controller->gadget.dev.driver = &driver->driver;
+ ! 	udc_controller->gadget.speed = driver->max_speed;
+   	spin_unlock_irqrestore(&udc_controller->lock, flags);
+   
+   	retval = bind(&udc_controller->gadget);
+ diff -crN linux-3.2.1_o/drivers/usb/gadget/fsl_udc_core.c linux-3.2.1/drivers/usb/gadget/fsl_udc_core.c
+ *** linux-3.2.1_o/drivers/usb/gadget/fsl_udc_core.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/gadget/fsl_udc_core.c	2014-11-25 13:19:16.291072717 +0900
+ ***************
+ *** 1934,1940 ****
+   	if (!udc_controller)
+   		return -ENODEV;
+   
+ ! 	if (!driver || driver->speed < USB_SPEED_FULL
+   			|| !bind || !driver->disconnect || !driver->setup)
+   		return -EINVAL;
+   
+ --- 1934,1940 ----
+   	if (!udc_controller)
+   		return -ENODEV;
+   
+ ! 	if (!driver || driver->max_speed < USB_SPEED_FULL
+   			|| !bind || !driver->disconnect || !driver->setup)
+   		return -EINVAL;
+   
+ ***************
+ *** 2525,2531 ****
+   
+   	/* Setup gadget structure */
+   	udc_controller->gadget.ops = &fsl_gadget_ops;
+ ! 	udc_controller->gadget.is_dualspeed = 1;
+   	udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
+   	INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
+   	udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
+ --- 2525,2531 ----
+   
+   	/* Setup gadget structure */
+   	udc_controller->gadget.ops = &fsl_gadget_ops;
+ ! 	udc_controller->gadget.max_speed = USB_SPEED_HIGH;
+   	udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
+   	INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
+   	udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
+ diff -crN linux-3.2.1_o/drivers/usb/gadget/f_subset.c linux-3.2.1/drivers/usb/gadget/f_subset.c
+ *** linux-3.2.1_o/drivers/usb/gadget/f_subset.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/gadget/f_subset.c	2014-11-25 13:19:16.291072717 +0900
+ ***************
+ *** 307,312 ****
+ --- 307,313 ----
+   	status = -ENODEV;
+   
+   	/* allocate instance-specific endpoints */
+ + 	usb_ep_autoconfig_reset(cdev->gadget);
+   	ep = usb_ep_autoconfig(cdev->gadget, &fs_subset_in_desc);
+   	if (!ep)
+   		goto fail;
+ diff -crN linux-3.2.1_o/drivers/usb/gadget/fusb300_udc.c linux-3.2.1/drivers/usb/gadget/fusb300_udc.c
+ *** linux-3.2.1_o/drivers/usb/gadget/fusb300_udc.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/gadget/fusb300_udc.c	2014-11-25 13:19:16.383113574 +0900
+ ***************
+ *** 1317,1323 ****
+   	int retval;
+   
+   	if (!driver
+ ! 			|| driver->speed < USB_SPEED_FULL
+   			|| !bind
+   			|| !driver->setup)
+   		return -EINVAL;
+ --- 1317,1323 ----
+   	int retval;
+   
+   	if (!driver
+ ! 			|| driver->max_speed < USB_SPEED_FULL
+   			|| !bind
+   			|| !driver->setup)
+   		return -EINVAL;
+ ***************
+ *** 1463,1469 ****
+   
+   	dev_set_name(&fusb300->gadget.dev, "gadget");
+   
+ ! 	fusb300->gadget.is_dualspeed = 1;
+   	fusb300->gadget.dev.parent = &pdev->dev;
+   	fusb300->gadget.dev.dma_mask = pdev->dev.dma_mask;
+   	fusb300->gadget.dev.release = pdev->dev.release;
+ --- 1463,1469 ----
+   
+   	dev_set_name(&fusb300->gadget.dev, "gadget");
+   
+ ! 	fusb300->gadget.max_speed = USB_SPEED_HIGH;
+   	fusb300->gadget.dev.parent = &pdev->dev;
+   	fusb300->gadget.dev.dma_mask = pdev->dev.dma_mask;
+   	fusb300->gadget.dev.release = pdev->dev.release;
+ diff -crN linux-3.2.1_o/drivers/usb/gadget/goku_udc.c linux-3.2.1/drivers/usb/gadget/goku_udc.c
+ *** linux-3.2.1_o/drivers/usb/gadget/goku_udc.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/gadget/goku_udc.c	2014-11-25 13:19:16.383113574 +0900
+ ***************
+ *** 1357,1363 ****
+   	int			retval;
+   
+   	if (!driver
+ ! 			|| driver->speed < USB_SPEED_FULL
+   			|| !bind
+   			|| !driver->disconnect
+   			|| !driver->setup)
+ --- 1357,1363 ----
+   	int			retval;
+   
+   	if (!driver
+ ! 			|| driver->max_speed < USB_SPEED_FULL
+   			|| !bind
+   			|| !driver->disconnect
+   			|| !driver->setup)
+ ***************
+ *** 1796,1801 ****
+ --- 1796,1802 ----
+   	spin_lock_init(&dev->lock);
+   	dev->pdev = pdev;
+   	dev->gadget.ops = &goku_ops;
+ + 	dev->gadget.max_speed = USB_SPEED_FULL;
+   
+   	/* the "gadget" abstracts/virtualizes the controller */
+   	dev_set_name(&dev->gadget.dev, "gadget");
+ diff -crN linux-3.2.1_o/drivers/usb/gadget/imx_udc.c linux-3.2.1/drivers/usb/gadget/imx_udc.c
+ *** linux-3.2.1_o/drivers/usb/gadget/imx_udc.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/gadget/imx_udc.c	2014-11-25 13:19:16.387155246 +0900
+ ***************
+ *** 1336,1342 ****
+   	int retval;
+   
+   	if (!driver
+ ! 		|| driver->speed < USB_SPEED_FULL
+   		|| !bind
+   		|| !driver->disconnect
+   		|| !driver->setup)
+ --- 1336,1342 ----
+   	int retval;
+   
+   	if (!driver
+ ! 		|| driver->max_speed < USB_SPEED_FULL
+   		|| !bind
+   		|| !driver->disconnect
+   		|| !driver->setup)
+ diff -crN linux-3.2.1_o/drivers/usb/gadget/inode.c linux-3.2.1/drivers/usb/gadget/inode.c
+ *** linux-3.2.1_o/drivers/usb/gadget/inode.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/gadget/inode.c	2014-11-25 13:19:16.391051971 +0900
+ ***************
+ *** 1766,1774 ****
+   
+   static struct usb_gadget_driver gadgetfs_driver = {
+   #ifdef	CONFIG_USB_GADGET_DUALSPEED
+ ! 	.speed		= USB_SPEED_HIGH,
+   #else
+ ! 	.speed		= USB_SPEED_FULL,
+   #endif
+   	.function	= (char *) driver_desc,
+   	.unbind		= gadgetfs_unbind,
+ --- 1766,1774 ----
+   
+   static struct usb_gadget_driver gadgetfs_driver = {
+   #ifdef	CONFIG_USB_GADGET_DUALSPEED
+ ! 	.max_speed	= USB_SPEED_HIGH,
+   #else
+ ! 	.max_speed	= USB_SPEED_FULL,
+   #endif
+   	.function	= (char *) driver_desc,
+   	.unbind		= gadgetfs_unbind,
+ ***************
+ *** 1792,1798 ****
+   }
+   
+   static struct usb_gadget_driver probe_driver = {
+ ! 	.speed		= USB_SPEED_HIGH,
+   	.unbind		= gadgetfs_nop,
+   	.setup		= (void *)gadgetfs_nop,
+   	.disconnect	= gadgetfs_nop,
+ --- 1792,1798 ----
+   }
+   
+   static struct usb_gadget_driver probe_driver = {
+ ! 	.max_speed	= USB_SPEED_HIGH,
+   	.unbind		= gadgetfs_nop,
+   	.setup		= (void *)gadgetfs_nop,
+   	.disconnect	= gadgetfs_nop,
+ diff -crN linux-3.2.1_o/drivers/usb/gadget/langwell_udc.c linux-3.2.1/drivers/usb/gadget/langwell_udc.c
+ *** linux-3.2.1_o/drivers/usb/gadget/langwell_udc.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/gadget/langwell_udc.c	2014-11-25 13:19:16.391051971 +0900
+ ***************
+ *** 3267,3273 ****
+   	dev->gadget.ep0 = &dev->ep[0].ep;	/* gadget ep0 */
+   	INIT_LIST_HEAD(&dev->gadget.ep_list);	/* ep_list */
+   	dev->gadget.speed = USB_SPEED_UNKNOWN;	/* speed */
+ ! 	dev->gadget.is_dualspeed = 1;		/* support dual speed */
+   #ifdef	OTG_TRANSCEIVER
+   	dev->gadget.is_otg = 1;			/* support otg mode */
+   #endif
+ --- 3267,3273 ----
+   	dev->gadget.ep0 = &dev->ep[0].ep;	/* gadget ep0 */
+   	INIT_LIST_HEAD(&dev->gadget.ep_list);	/* ep_list */
+   	dev->gadget.speed = USB_SPEED_UNKNOWN;	/* speed */
+ ! 	dev->gadget.max_speed = USB_SPEED_HIGH;	/* support dual speed */
+   #ifdef	OTG_TRANSCEIVER
+   	dev->gadget.is_otg = 1;			/* support otg mode */
+   #endif
+ diff -crN linux-3.2.1_o/drivers/usb/gadget/m66592-udc.c linux-3.2.1/drivers/usb/gadget/m66592-udc.c
+ *** linux-3.2.1_o/drivers/usb/gadget/m66592-udc.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/gadget/m66592-udc.c	2014-11-25 13:19:16.395051610 +0900
+ ***************
+ *** 1472,1478 ****
+   	int retval;
+   
+   	if (!driver
+ ! 			|| driver->speed < USB_SPEED_HIGH
+   			|| !bind
+   			|| !driver->setup)
+   		return -EINVAL;
+ --- 1472,1478 ----
+   	int retval;
+   
+   	if (!driver
+ ! 			|| driver->max_speed < USB_SPEED_HIGH
+   			|| !bind
+   			|| !driver->setup)
+   		return -EINVAL;
+ ***************
+ *** 1653,1659 ****
+   	m66592->gadget.ops = &m66592_gadget_ops;
+   	device_initialize(&m66592->gadget.dev);
+   	dev_set_name(&m66592->gadget.dev, "gadget");
+ ! 	m66592->gadget.is_dualspeed = 1;
+   	m66592->gadget.dev.parent = &pdev->dev;
+   	m66592->gadget.dev.dma_mask = pdev->dev.dma_mask;
+   	m66592->gadget.dev.release = pdev->dev.release;
+ --- 1653,1659 ----
+   	m66592->gadget.ops = &m66592_gadget_ops;
+   	device_initialize(&m66592->gadget.dev);
+   	dev_set_name(&m66592->gadget.dev, "gadget");
+ ! 	m66592->gadget.max_speed = USB_SPEED_HIGH;
+   	m66592->gadget.dev.parent = &pdev->dev;
+   	m66592->gadget.dev.dma_mask = pdev->dev.dma_mask;
+   	m66592->gadget.dev.release = pdev->dev.release;
+ diff -crN linux-3.2.1_o/drivers/usb/gadget/mv_udc_core.c linux-3.2.1/drivers/usb/gadget/mv_udc_core.c
+ *** linux-3.2.1_o/drivers/usb/gadget/mv_udc_core.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/gadget/mv_udc_core.c	2014-11-25 13:19:16.395051610 +0900
+ ***************
+ *** 2312,2318 ****
+   	udc->gadget.ep0 = &udc->eps[0].ep;	/* gadget ep0 */
+   	INIT_LIST_HEAD(&udc->gadget.ep_list);	/* ep_list */
+   	udc->gadget.speed = USB_SPEED_UNKNOWN;	/* speed */
+ ! 	udc->gadget.is_dualspeed = 1;		/* support dual speed */
+   
+   	/* the "gadget" abstracts/virtualizes the controller */
+   	dev_set_name(&udc->gadget.dev, "gadget");
+ --- 2312,2318 ----
+   	udc->gadget.ep0 = &udc->eps[0].ep;	/* gadget ep0 */
+   	INIT_LIST_HEAD(&udc->gadget.ep_list);	/* ep_list */
+   	udc->gadget.speed = USB_SPEED_UNKNOWN;	/* speed */
+ ! 	udc->gadget.max_speed = USB_SPEED_HIGH;	/* support dual speed */
+   
+   	/* the "gadget" abstracts/virtualizes the controller */
+   	dev_set_name(&udc->gadget.dev, "gadget");
+ diff -crN linux-3.2.1_o/drivers/usb/gadget/net2272.c linux-3.2.1/drivers/usb/gadget/net2272.c
+ *** linux-3.2.1_o/drivers/usb/gadget/net2272.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/gadget/net2272.c	2014-11-25 13:19:16.399053230 +0900
+ ***************
+ *** 1459,1465 ****
+   	unsigned i;
+   
+   	if (!driver || !driver->unbind || !driver->setup ||
+ ! 	    driver->speed != USB_SPEED_HIGH)
+   		return -EINVAL;
+   
+   	dev = container_of(_gadget, struct net2272, gadget);
+ --- 1459,1465 ----
+   	unsigned i;
+   
+   	if (!driver || !driver->unbind || !driver->setup ||
+ ! 	    driver->max_speed != USB_SPEED_HIGH)
+   		return -EINVAL;
+   
+   	dev = container_of(_gadget, struct net2272, gadget);
+ ***************
+ *** 2235,2241 ****
+   	ret->irq = irq;
+   	ret->dev = dev;
+   	ret->gadget.ops = &net2272_ops;
+ ! 	ret->gadget.is_dualspeed = 1;
+   
+   	/* the "gadget" abstracts/virtualizes the controller */
+   	dev_set_name(&ret->gadget.dev, "gadget");
+ --- 2235,2241 ----
+   	ret->irq = irq;
+   	ret->dev = dev;
+   	ret->gadget.ops = &net2272_ops;
+ ! 	ret->gadget.max_speed = USB_SPEED_HIGH;
+   
+   	/* the "gadget" abstracts/virtualizes the controller */
+   	dev_set_name(&ret->gadget.dev, "gadget");
+ diff -crN linux-3.2.1_o/drivers/usb/gadget/net2280.c linux-3.2.1/drivers/usb/gadget/net2280.c
+ *** linux-3.2.1_o/drivers/usb/gadget/net2280.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/gadget/net2280.c	2014-11-25 13:19:16.399053230 +0900
+ ***************
+ *** 1881,1887 ****
+   	 * (dev->usb->xcvrdiag & FORCE_FULL_SPEED_MODE)
+   	 * "must not be used in normal operation"
+   	 */
+ ! 	if (!driver || driver->speed < USB_SPEED_HIGH
+   			|| !driver->setup)
+   		return -EINVAL;
+   
+ --- 1881,1887 ----
+   	 * (dev->usb->xcvrdiag & FORCE_FULL_SPEED_MODE)
+   	 * "must not be used in normal operation"
+   	 */
+ ! 	if (!driver || driver->max_speed < USB_SPEED_HIGH
+   			|| !driver->setup)
+   		return -EINVAL;
+   
+ ***************
+ *** 2698,2704 ****
+   	spin_lock_init (&dev->lock);
+   	dev->pdev = pdev;
+   	dev->gadget.ops = &net2280_ops;
+ ! 	dev->gadget.is_dualspeed = 1;
+   
+   	/* the "gadget" abstracts/virtualizes the controller */
+   	dev_set_name(&dev->gadget.dev, "gadget");
+ --- 2698,2704 ----
+   	spin_lock_init (&dev->lock);
+   	dev->pdev = pdev;
+   	dev->gadget.ops = &net2280_ops;
+ ! 	dev->gadget.max_speed = USB_SPEED_HIGH;
+   
+   	/* the "gadget" abstracts/virtualizes the controller */
+   	dev_set_name(&dev->gadget.dev, "gadget");
+ diff -crN linux-3.2.1_o/drivers/usb/gadget/omap_udc.c linux-3.2.1/drivers/usb/gadget/omap_udc.c
+ *** linux-3.2.1_o/drivers/usb/gadget/omap_udc.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/gadget/omap_udc.c	2014-11-25 13:19:16.403060885 +0900
+ ***************
+ *** 2110,2116 ****
+   		return -ENODEV;
+   	if (!driver
+   			// FIXME if otg, check:  driver->is_otg
+ ! 			|| driver->speed < USB_SPEED_FULL
+   			|| !bind || !driver->setup)
+   		return -EINVAL;
+   
+ --- 2110,2116 ----
+   		return -ENODEV;
+   	if (!driver
+   			// FIXME if otg, check:  driver->is_otg
+ ! 			|| driver->max_speed < USB_SPEED_FULL
+   			|| !bind || !driver->setup)
+   		return -EINVAL;
+   
+ ***************
+ *** 2676,2681 ****
+ --- 2676,2682 ----
+   	INIT_LIST_HEAD(&udc->gadget.ep_list);
+   	INIT_LIST_HEAD(&udc->iso);
+   	udc->gadget.speed = USB_SPEED_UNKNOWN;
+ + 	udc->gadget.max_speed = USB_SPEED_FULL;
+   	udc->gadget.name = driver_name;
+   
+   	device_initialize(&udc->gadget.dev);
+ ***************
+ *** 2794,2799 ****
+ --- 2795,2801 ----
+   	struct omap_usb_config	*config = pdev->dev.platform_data;
+   	struct clk		*dc_clk;
+   	struct clk		*hhc_clk;
+ + 	u8			pdev_id;
+   
+   	/* NOTE:  "knows" the order of the resources! */
+   	if (!request_mem_region(pdev->resource[0].start,
+ ***************
+ *** 2862,2868 ****
+   		 * use it.  Except for OTG, we don't _need_ to talk to one;
+   		 * but not having one probably means no VBUS detection.
+   		 */
+ ! 		xceiv = otg_get_transceiver();
+   		if (xceiv)
+   			type = xceiv->label;
+   		else if (config->otg) {
+ --- 2864,2871 ----
+   		 * use it.  Except for OTG, we don't _need_ to talk to one;
+   		 * but not having one probably means no VBUS detection.
+   		 */
+ ! 		pdev_id = (pdev->id >= 0) ? pdev->id : 0;
+ ! 		xceiv = otg_get_transceiver(pdev_id);
+   		if (xceiv)
+   			type = xceiv->label;
+   		else if (config->otg) {
+ diff -crN linux-3.2.1_o/drivers/usb/gadget/pch_udc.c linux-3.2.1/drivers/usb/gadget/pch_udc.c
+ *** linux-3.2.1_o/drivers/usb/gadget/pch_udc.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/gadget/pch_udc.c	2014-11-25 13:19:16.407070483 +0900
+ ***************
+ *** 2693,2699 ****
+   	struct pch_udc_dev	*dev = pch_udc;
+   	int			retval;
+   
+ ! 	if (!driver || (driver->speed == USB_SPEED_UNKNOWN) || !bind ||
+   	    !driver->setup || !driver->unbind || !driver->disconnect) {
+   		dev_err(&dev->pdev->dev,
+   			"%s: invalid driver parameter\n", __func__);
+ --- 2693,2699 ----
+   	struct pch_udc_dev	*dev = pch_udc;
+   	int			retval;
+   
+ ! 	if (!driver || (driver->max_speed == USB_SPEED_UNKNOWN) || !bind ||
+   	    !driver->setup || !driver->unbind || !driver->disconnect) {
+   		dev_err(&dev->pdev->dev,
+   			"%s: invalid driver parameter\n", __func__);
+ ***************
+ *** 2941,2947 ****
+   	dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
+   	dev->gadget.dev.release = gadget_release;
+   	dev->gadget.name = KBUILD_MODNAME;
+ ! 	dev->gadget.is_dualspeed = 1;
+   
+   	retval = device_register(&dev->gadget.dev);
+   	if (retval)
+ --- 2941,2947 ----
+   	dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
+   	dev->gadget.dev.release = gadget_release;
+   	dev->gadget.name = KBUILD_MODNAME;
+ ! 	dev->gadget.max_speed = USB_SPEED_HIGH;
+   
+   	retval = device_register(&dev->gadget.dev);
+   	if (retval)
+ diff -crN linux-3.2.1_o/drivers/usb/gadget/printer.c linux-3.2.1/drivers/usb/gadget/printer.c
+ *** linux-3.2.1_o/drivers/usb/gadget/printer.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/gadget/printer.c	2014-11-25 13:19:16.407070483 +0900
+ ***************
+ *** 1141,1147 ****
+   				break;
+   #ifdef CONFIG_USB_GADGET_DUALSPEED
+   			case USB_DT_DEVICE_QUALIFIER:
+ ! 				if (!gadget->is_dualspeed)
+   					break;
+   				/*
+   				 * assumes ep0 uses the same value for both
+ --- 1141,1147 ----
+   				break;
+   #ifdef CONFIG_USB_GADGET_DUALSPEED
+   			case USB_DT_DEVICE_QUALIFIER:
+ ! 				if (!gadget_is_dualspeed(gadget))
+   					break;
+   				/*
+   				 * assumes ep0 uses the same value for both
+ ***************
+ *** 1155,1161 ****
+   				break;
+   
+   			case USB_DT_OTHER_SPEED_CONFIG:
+ ! 				if (!gadget->is_dualspeed)
+   					break;
+   				/* FALLTHROUGH */
+   #endif /* CONFIG_USB_GADGET_DUALSPEED */
+ --- 1155,1161 ----
+   				break;
+   
+   			case USB_DT_OTHER_SPEED_CONFIG:
+ ! 				if (!gadget_is_dualspeed(gadget))
+   					break;
+   				/* FALLTHROUGH */
+   #endif /* CONFIG_USB_GADGET_DUALSPEED */
+ ***************
+ *** 1535,1541 ****
+   /*-------------------------------------------------------------------------*/
+   
+   static struct usb_gadget_driver printer_driver = {
+ ! 	.speed		= DEVSPEED,
+   
+   	.function	= (char *) driver_desc,
+   	.unbind		= printer_unbind,
+ --- 1535,1541 ----
+   /*-------------------------------------------------------------------------*/
+   
+   static struct usb_gadget_driver printer_driver = {
+ ! 	.max_speed	= DEVSPEED,
+   
+   	.function	= (char *) driver_desc,
+   	.unbind		= printer_unbind,
+ diff -crN linux-3.2.1_o/drivers/usb/gadget/pxa25x_udc.c linux-3.2.1/drivers/usb/gadget/pxa25x_udc.c
+ *** linux-3.2.1_o/drivers/usb/gadget/pxa25x_udc.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/gadget/pxa25x_udc.c	2014-11-25 13:19:16.411080161 +0900
+ ***************
+ *** 1264,1270 ****
+   	int			retval;
+   
+   	if (!driver
+ ! 			|| driver->speed < USB_SPEED_FULL
+   			|| !bind
+   			|| !driver->disconnect
+   			|| !driver->setup)
+ --- 1264,1270 ----
+   	int			retval;
+   
+   	if (!driver
+ ! 			|| driver->max_speed < USB_SPEED_FULL
+   			|| !bind
+   			|| !driver->disconnect
+   			|| !driver->setup)
+ diff -crN linux-3.2.1_o/drivers/usb/gadget/pxa27x_udc.c linux-3.2.1/drivers/usb/gadget/pxa27x_udc.c
+ *** linux-3.2.1_o/drivers/usb/gadget/pxa27x_udc.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/gadget/pxa27x_udc.c	2014-11-25 13:19:16.411080161 +0900
+ ***************
+ *** 1807,1813 ****
+   	struct pxa_udc *udc = the_controller;
+   	int retval;
+   
+ ! 	if (!driver || driver->speed < USB_SPEED_FULL || !bind
+   			|| !driver->disconnect || !driver->setup)
+   		return -EINVAL;
+   	if (!udc)
+ --- 1807,1813 ----
+   	struct pxa_udc *udc = the_controller;
+   	int retval;
+   
+ ! 	if (!driver || driver->max_speed < USB_SPEED_FULL || !bind
+   			|| !driver->disconnect || !driver->setup)
+   		return -EINVAL;
+   	if (!udc)
+ diff -crN linux-3.2.1_o/drivers/usb/gadget/r8a66597-udc.c linux-3.2.1/drivers/usb/gadget/r8a66597-udc.c
+ *** linux-3.2.1_o/drivers/usb/gadget/r8a66597-udc.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/gadget/r8a66597-udc.c	2014-11-25 13:19:16.415054272 +0900
+ ***************
+ *** 1746,1752 ****
+   	struct r8a66597 *r8a66597 = gadget_to_r8a66597(gadget);
+   
+   	if (!driver
+ ! 			|| driver->speed < USB_SPEED_HIGH
+   			|| !driver->setup)
+   		return -EINVAL;
+   	if (!r8a66597)
+ --- 1746,1752 ----
+   	struct r8a66597 *r8a66597 = gadget_to_r8a66597(gadget);
+   
+   	if (!driver
+ ! 			|| driver->max_speed < USB_SPEED_HIGH
+   			|| !driver->setup)
+   		return -EINVAL;
+   	if (!r8a66597)
+ ***************
+ *** 1911,1917 ****
+   
+   	r8a66597->gadget.ops = &r8a66597_gadget_ops;
+   	dev_set_name(&r8a66597->gadget.dev, "gadget");
+ ! 	r8a66597->gadget.is_dualspeed = 1;
+   	r8a66597->gadget.dev.parent = &pdev->dev;
+   	r8a66597->gadget.dev.dma_mask = pdev->dev.dma_mask;
+   	r8a66597->gadget.dev.release = pdev->dev.release;
+ --- 1911,1917 ----
+   
+   	r8a66597->gadget.ops = &r8a66597_gadget_ops;
+   	dev_set_name(&r8a66597->gadget.dev, "gadget");
+ ! 	r8a66597->gadget.max_speed = USB_SPEED_HIGH;
+   	r8a66597->gadget.dev.parent = &pdev->dev;
+   	r8a66597->gadget.dev.dma_mask = pdev->dev.dma_mask;
+   	r8a66597->gadget.dev.release = pdev->dev.release;
+ diff -crN linux-3.2.1_o/drivers/usb/gadget/rndis.c linux-3.2.1/drivers/usb/gadget/rndis.c
+ *** linux-3.2.1_o/drivers/usb/gadget/rndis.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/gadget/rndis.c	2014-11-25 13:19:16.419051663 +0900
+ ***************
+ *** 314,320 ****
+   	/* mandatory */
+   	case OID_GEN_CURRENT_PACKET_FILTER:
+   		pr_debug("%s: OID_GEN_CURRENT_PACKET_FILTER\n", __func__);
+ ! 		*outbuf = cpu_to_le32(*rndis_per_dev_params[configNr].filter);
+   		retval = 0;
+   		break;
+   
+ --- 314,321 ----
+   	/* mandatory */
+   	case OID_GEN_CURRENT_PACKET_FILTER:
+   		pr_debug("%s: OID_GEN_CURRENT_PACKET_FILTER\n", __func__);
+ ! 		*outbuf =
+ ! 		cpu_to_le32(*(u16 *)rndis_per_dev_params[configNr].filter);
+   		retval = 0;
+   		break;
+   
+ ***************
+ *** 336,342 ****
+   
+   	case OID_GEN_PHYSICAL_MEDIUM:
+   		pr_debug("%s: OID_GEN_PHYSICAL_MEDIUM\n", __func__);
+ ! 		*outbuf = cpu_to_le32(0);
+   		retval = 0;
+   		break;
+   
+ --- 337,343 ----
+   
+   	case OID_GEN_PHYSICAL_MEDIUM:
+   		pr_debug("%s: OID_GEN_PHYSICAL_MEDIUM\n", __func__);
+ ! 		*outbuf = __constant_cpu_to_le32(2);
+   		retval = 0;
+   		break;
+   
+ ***************
+ *** 413,419 ****
+   		if (rndis_per_dev_params[configNr].dev) {
+   			length = ETH_ALEN;
+   			memcpy(outbuf,
+ ! 				rndis_per_dev_params[configNr].host_mac,
+   				length);
+   			retval = 0;
+   		}
+ --- 414,420 ----
+   		if (rndis_per_dev_params[configNr].dev) {
+   			length = ETH_ALEN;
+   			memcpy(outbuf,
+ ! 				rndis_per_dev_params[configNr].perm_mac,
+   				length);
+   			retval = 0;
+   		}
+ ***************
+ *** 443,449 ****
+   	case OID_802_3_MAXIMUM_LIST_SIZE:
+   		pr_debug("%s: OID_802_3_MAXIMUM_LIST_SIZE\n", __func__);
+   		/* Multicast base address only */
+ ! 		*outbuf = cpu_to_le32(1);
+   		retval = 0;
+   		break;
+   
+ --- 444,450 ----
+   	case OID_802_3_MAXIMUM_LIST_SIZE:
+   		pr_debug("%s: OID_802_3_MAXIMUM_LIST_SIZE\n", __func__);
+   		/* Multicast base address only */
+ ! 		*outbuf = __constant_cpu_to_le32(32);
+   		retval = 0;
+   		break;
+   
+ ***************
+ *** 549,554 ****
+ --- 550,559 ----
+   	case OID_802_3_MULTICAST_LIST:
+   		/* I think we can ignore this */
+   		pr_debug("%s: OID_802_3_MULTICAST_LIST\n", __func__);
+ + 		memset(rndis_per_dev_params[configNr].mcast_addr, 0,
+ + 			RNDIS_MAX_MULTICAST_SIZE * 6);
+ + 		memcpy(rndis_per_dev_params[configNr].mcast_addr,
+ + 			buf, buf_len);
+   		retval = 0;
+   		break;
+   
+ ***************
+ *** 578,583 ****
+ --- 583,591 ----
+   		return -ENOMEM;
+   	resp = (rndis_init_cmplt_type *)r->buf;
+   
+ + 	if (!resp)
+ + 		return -ENOMEM;
+ + 
+   	resp->MessageType = cpu_to_le32(REMOTE_NDIS_INITIALIZE_CMPLT);
+   	resp->MessageLength = cpu_to_le32(52);
+   	resp->RequestID = buf->RequestID; /* Still LE in msg buffer */
+ ***************
+ *** 788,794 ****
+   
+   void rndis_set_host_mac(int configNr, const u8 *addr)
+   {
+ ! 	rndis_per_dev_params[configNr].host_mac = addr;
+   }
+   
+   /*
+ --- 796,803 ----
+   
+   void rndis_set_host_mac(int configNr, const u8 *addr)
+   {
+ ! 	rndis_per_dev_params[configNr].host_mac = (u8 *)addr;
+ ! 	memcpy((void *)rndis_per_dev_params[configNr].perm_mac, addr, 6);
+   }
+   
+   /*
+ ***************
+ *** 830,835 ****
+ --- 839,846 ----
+   			__func__);
+   		params->state = RNDIS_UNINITIALIZED;
+   		if (params->dev) {
+ + 			memcpy((void *)rndis_per_dev_params[configNr].host_mac,
+ + 			(void *)rndis_per_dev_params[configNr].perm_mac, 6);
+   			netif_carrier_off(params->dev);
+   			netif_stop_queue(params->dev);
+   		}
+ diff -crN linux-3.2.1_o/drivers/usb/gadget/rndis.h linux-3.2.1/drivers/usb/gadget/rndis.h
+ *** linux-3.2.1_o/drivers/usb/gadget/rndis.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/gadget/rndis.h	2014-11-25 13:19:16.419051663 +0900
+ ***************
+ *** 18,24 ****
+   #include "ndis.h"
+   
+   #define RNDIS_MAXIMUM_FRAME_SIZE	1518
+ ! #define RNDIS_MAX_TOTAL_SIZE		1558
+   
+   /* Remote NDIS Versions */
+   #define RNDIS_MAJOR_VERSION		1
+ --- 18,25 ----
+   #include "ndis.h"
+   
+   #define RNDIS_MAXIMUM_FRAME_SIZE	1518
+ ! #define RNDIS_MAX_TOTAL_SIZE		1514
+ ! #define RNDIS_MAX_MULTICAST_SIZE        32
+   
+   /* Remote NDIS Versions */
+   #define RNDIS_MAJOR_VERSION		1
+ ***************
+ *** 230,236 ****
+   	u32			speed;
+   	u32			media_state;
+   
+ ! 	const u8		*host_mac;
+   	u16			*filter;
+   	struct net_device	*dev;
+   
+ --- 231,238 ----
+   	u32			speed;
+   	u32			media_state;
+   
+ ! 	u8                      perm_mac[6];
+ ! 	u8                      *host_mac;
+   	u16			*filter;
+   	struct net_device	*dev;
+   
+ ***************
+ *** 239,244 ****
+ --- 241,247 ----
+   	void			(*resp_avail)(void *v);
+   	void			*v;
+   	struct list_head	resp_queue;
+ + 	u8			mcast_addr[RNDIS_MAX_MULTICAST_SIZE][6];
+   } rndis_params;
+   
+   /* RNDIS Message parser and other useless functions */
+ diff -crN linux-3.2.1_o/drivers/usb/gadget/s3c2410_udc.c linux-3.2.1/drivers/usb/gadget/s3c2410_udc.c
+ *** linux-3.2.1_o/drivers/usb/gadget/s3c2410_udc.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/gadget/s3c2410_udc.c	2014-11-25 13:19:16.419051663 +0900
+ ***************
+ *** 1683,1691 ****
+   	if (udc->driver)
+   		return -EBUSY;
+   
+ ! 	if (!bind || !driver->setup || driver->speed < USB_SPEED_FULL) {
+   		printk(KERN_ERR "Invalid driver: bind %p setup %p speed %d\n",
+ ! 			bind, driver->setup, driver->speed);
+   		return -EINVAL;
+   	}
+   #if defined(MODULE)
+ --- 1683,1691 ----
+   	if (udc->driver)
+   		return -EBUSY;
+   
+ ! 	if (!bind || !driver->setup || driver->max_speed < USB_SPEED_FULL) {
+   		printk(KERN_ERR "Invalid driver: bind %p setup %p speed %d\n",
+ ! 			bind, driver->setup, driver->max_speed);
+   		return -EINVAL;
+   	}
+   #if defined(MODULE)
+ diff -crN linux-3.2.1_o/drivers/usb/gadget/s3c-hsotg.c linux-3.2.1/drivers/usb/gadget/s3c-hsotg.c
+ *** linux-3.2.1_o/drivers/usb/gadget/s3c-hsotg.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/gadget/s3c-hsotg.c	2014-11-25 13:19:16.423074302 +0900
+ ***************
+ *** 2586,2592 ****
+   		return -EINVAL;
+   	}
+   
+ ! 	if (driver->speed < USB_SPEED_FULL)
+   		dev_err(hsotg->dev, "%s: bad speed\n", __func__);
+   
+   	if (!bind || !driver->setup) {
+ --- 2586,2592 ----
+   		return -EINVAL;
+   	}
+   
+ ! 	if (driver->max_speed < USB_SPEED_FULL)
+   		dev_err(hsotg->dev, "%s: bad speed\n", __func__);
+   
+   	if (!bind || !driver->setup) {
+ ***************
+ *** 3362,3368 ****
+   
+   	dev_set_name(&hsotg->gadget.dev, "gadget");
+   
+ ! 	hsotg->gadget.is_dualspeed = 1;
+   	hsotg->gadget.ops = &s3c_hsotg_gadget_ops;
+   	hsotg->gadget.name = dev_name(dev);
+   
+ --- 3362,3368 ----
+   
+   	dev_set_name(&hsotg->gadget.dev, "gadget");
+   
+ ! 	hsotg->gadget.max_speed = USB_SPEED_HIGH;
+   	hsotg->gadget.ops = &s3c_hsotg_gadget_ops;
+   	hsotg->gadget.name = dev_name(dev);
+   
+ diff -crN linux-3.2.1_o/drivers/usb/gadget/s3c-hsudc.c linux-3.2.1/drivers/usb/gadget/s3c-hsudc.c
+ *** linux-3.2.1_o/drivers/usb/gadget/s3c-hsudc.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/gadget/s3c-hsudc.c	2014-11-25 13:19:16.423074302 +0900
+ ***************
+ *** 1142,1148 ****
+   	int ret;
+   
+   	if (!driver
+ ! 		|| driver->speed < USB_SPEED_FULL
+   		|| !bind
+   		|| !driver->unbind || !driver->disconnect || !driver->setup)
+   		return -EINVAL;
+ --- 1142,1148 ----
+   	int ret;
+   
+   	if (!driver
+ ! 		|| driver->max_speed < USB_SPEED_FULL
+   		|| !bind
+   		|| !driver->unbind || !driver->disconnect || !driver->setup)
+   		return -EINVAL;
+ ***************
+ *** 1310,1316 ****
+   	device_initialize(&hsudc->gadget.dev);
+   	dev_set_name(&hsudc->gadget.dev, "gadget");
+   
+ ! 	hsudc->gadget.is_dualspeed = 1;
+   	hsudc->gadget.ops = &s3c_hsudc_gadget_ops;
+   	hsudc->gadget.name = dev_name(dev);
+   	hsudc->gadget.dev.parent = dev;
+ --- 1310,1316 ----
+   	device_initialize(&hsudc->gadget.dev);
+   	dev_set_name(&hsudc->gadget.dev, "gadget");
+   
+ ! 	hsudc->gadget.max_speed = USB_SPEED_HIGH;
+   	hsudc->gadget.ops = &s3c_hsudc_gadget_ops;
+   	hsudc->gadget.name = dev_name(dev);
+   	hsudc->gadget.dev.parent = dev;
+ diff -crN linux-3.2.1_o/drivers/usb/gadget/udc-core.c linux-3.2.1/drivers/usb/gadget/udc-core.c
+ *** linux-3.2.1_o/drivers/usb/gadget/udc-core.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/gadget/udc-core.c	2014-11-25 13:19:16.428100346 +0900
+ ***************
+ *** 211,219 ****
+   
+   	if (udc_is_newstyle(udc)) {
+   		udc->driver->disconnect(udc->gadget);
+   		udc->driver->unbind(udc->gadget);
+   		usb_gadget_udc_stop(udc->gadget, udc->driver);
+ - 		usb_gadget_disconnect(udc->gadget);
+   	} else {
+   		usb_gadget_stop(udc->gadget, udc->driver);
+   	}
+ --- 211,219 ----
+   
+   	if (udc_is_newstyle(udc)) {
+   		udc->driver->disconnect(udc->gadget);
+ + 		usb_gadget_disconnect(udc->gadget);
+   		udc->driver->unbind(udc->gadget);
+   		usb_gadget_udc_stop(udc->gadget, udc->driver);
+   	} else {
+   		usb_gadget_stop(udc->gadget, udc->driver);
+   	}
+ ***************
+ *** 359,367 ****
+ --- 359,371 ----
+   	struct usb_udc		*udc = container_of(dev, struct usb_udc, dev);
+   
+   	if (sysfs_streq(buf, "connect")) {
+ + 		if (udc_is_newstyle(udc))
+ + 			usb_gadget_udc_start(udc->gadget, udc->driver);
+   		usb_gadget_connect(udc->gadget);
+   	} else if (sysfs_streq(buf, "disconnect")) {
+   		usb_gadget_disconnect(udc->gadget);
+ + 		if (udc_is_newstyle(udc))
+ + 			usb_gadget_udc_stop(udc->gadget, udc->driver);
+   	} else {
+   		dev_err(dev, "unsupported command '%s'\n", buf);
+   		return -EINVAL;
+ ***************
+ *** 371,384 ****
+   }
+   static DEVICE_ATTR(soft_connect, S_IWUSR, NULL, usb_udc_softconn_store);
+   
+ ! static ssize_t usb_udc_speed_show(struct device *dev,
+   		struct device_attribute *attr, char *buf)
+   {
+   	struct usb_udc		*udc = container_of(dev, struct usb_udc, dev);
+ ! 	return snprintf(buf, PAGE_SIZE, "%s\n",
+ ! 			usb_speed_string(udc->gadget->speed));
+   }
+ ! static DEVICE_ATTR(speed, S_IRUGO, usb_udc_speed_show, NULL);
+   
+   #define USB_UDC_ATTR(name)					\
+   ssize_t usb_udc_##name##_show(struct device *dev,		\
+ --- 375,402 ----
+   }
+   static DEVICE_ATTR(soft_connect, S_IWUSR, NULL, usb_udc_softconn_store);
+   
+ ! #define USB_UDC_SPEED_ATTR(name, param)					\
+ ! ssize_t usb_udc_##param##_show(struct device *dev,			\
+ ! 		struct device_attribute *attr, char *buf)		\
+ ! {									\
+ ! 	struct usb_udc *udc = container_of(dev, struct usb_udc, dev);	\
+ ! 	return snprintf(buf, PAGE_SIZE, "%s\n",				\
+ ! 			usb_speed_string(udc->gadget->param));		\
+ ! }									\
+ ! static DEVICE_ATTR(name, S_IRUSR, usb_udc_##param##_show, NULL)
+ ! 
+ ! static USB_UDC_SPEED_ATTR(current_speed, speed);
+ ! static USB_UDC_SPEED_ATTR(maximum_speed, max_speed);
+ ! 
+ ! /* TODO: Scheduled for removal in 3.8. */
+ ! static ssize_t usb_udc_is_dualspeed_show(struct device *dev,
+   		struct device_attribute *attr, char *buf)
+   {
+   	struct usb_udc		*udc = container_of(dev, struct usb_udc, dev);
+ ! 	return snprintf(buf, PAGE_SIZE, "%d\n",
+ ! 			gadget_is_dualspeed(udc->gadget));
+   }
+ ! static DEVICE_ATTR(is_dualspeed, S_IRUSR, usb_udc_is_dualspeed_show, NULL);
+   
+   #define USB_UDC_ATTR(name)					\
+   ssize_t usb_udc_##name##_show(struct device *dev,		\
+ ***************
+ *** 391,397 ****
+   }								\
+   static DEVICE_ATTR(name, S_IRUGO, usb_udc_##name##_show, NULL)
+   
+ - static USB_UDC_ATTR(is_dualspeed);
+   static USB_UDC_ATTR(is_otg);
+   static USB_UDC_ATTR(is_a_peripheral);
+   static USB_UDC_ATTR(b_hnp_enable);
+ --- 409,414 ----
+ ***************
+ *** 401,407 ****
+   static struct attribute *usb_udc_attrs[] = {
+   	&dev_attr_srp.attr,
+   	&dev_attr_soft_connect.attr,
+ ! 	&dev_attr_speed.attr,
+   
+   	&dev_attr_is_dualspeed.attr,
+   	&dev_attr_is_otg.attr,
+ --- 418,425 ----
+   static struct attribute *usb_udc_attrs[] = {
+   	&dev_attr_srp.attr,
+   	&dev_attr_soft_connect.attr,
+ ! 	&dev_attr_current_speed.attr,
+ ! 	&dev_attr_maximum_speed.attr,
+   
+   	&dev_attr_is_dualspeed.attr,
+   	&dev_attr_is_otg.attr,
+ diff -crN linux-3.2.1_o/drivers/usb/host/ehci-omap.c linux-3.2.1/drivers/usb/host/ehci-omap.c
+ *** linux-3.2.1_o/drivers/usb/host/ehci-omap.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/host/ehci-omap.c	2014-11-25 13:19:16.428100346 +0900
+ ***************
+ *** 41,46 ****
+ --- 41,47 ----
+   #include <linux/usb/ulpi.h>
+   #include <plat/usb.h>
+   #include <linux/regulator/consumer.h>
+ + #include <linux/pm_runtime.h>
+   
+   /* EHCI Register Set */
+   #define EHCI_INSNREG04					(0xA0)
+ ***************
+ *** 190,200 ****
+   		}
+   	}
+   
+ ! 	ret = omap_usbhs_enable(dev);
+ ! 	if (ret) {
+ ! 		dev_err(dev, "failed to start usbhs with err %d\n", ret);
+ ! 		goto err_enable;
+ ! 	}
+   
+   	/*
+   	 * An undocumented "feature" in the OMAP3 EHCI controller,
+ --- 191,198 ----
+   		}
+   	}
+   
+ ! 	pm_runtime_enable(dev);
+ ! 	pm_runtime_get_sync(dev);
+   
+   	/*
+   	 * An undocumented "feature" in the OMAP3 EHCI controller,
+ ***************
+ *** 240,250 ****
+   	return 0;
+   
+   err_add_hcd:
+ - 	omap_usbhs_disable(dev);
+ - 
+ - err_enable:
+   	disable_put_regulator(pdata);
+ ! 	usb_put_hcd(hcd);
+   
+   err_io:
+   	iounmap(regs);
+ --- 238,245 ----
+   	return 0;
+   
+   err_add_hcd:
+   	disable_put_regulator(pdata);
+ ! 	pm_runtime_put_sync(dev);
+   
+   err_io:
+   	iounmap(regs);
+ ***************
+ *** 266,275 ****
+   	struct usb_hcd *hcd	= dev_get_drvdata(dev);
+   
+   	usb_remove_hcd(hcd);
+ - 	omap_usbhs_disable(dev);
+   	disable_put_regulator(dev->platform_data);
+   	iounmap(hcd->regs);
+   	usb_put_hcd(hcd);
+   	return 0;
+   }
+   
+ --- 261,272 ----
+   	struct usb_hcd *hcd	= dev_get_drvdata(dev);
+   
+   	usb_remove_hcd(hcd);
+   	disable_put_regulator(dev->platform_data);
+   	iounmap(hcd->regs);
+   	usb_put_hcd(hcd);
+ + 	pm_runtime_put_sync(dev);
+ + 	pm_runtime_disable(dev);
+ + 
+   	return 0;
+   }
+   
+ diff -crN linux-3.2.1_o/drivers/usb/host/ehci-pxa168.c linux-3.2.1/drivers/usb/host/ehci-pxa168.c
+ *** linux-3.2.1_o/drivers/usb/host/ehci-pxa168.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/host/ehci-pxa168.c	2014-11-25 13:19:16.428100346 +0900
+ ***************
+ *** 299,305 ****
+   	ehci = hcd_to_ehci(hcd);
+   	ehci->caps = hcd->regs + 0x100;
+   	ehci->regs = hcd->regs + 0x100 +
+ ! 		HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
+   	ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
+   	hcd->has_tt = 1;
+   	ehci->sbrn = 0x20;
+ --- 299,305 ----
+   	ehci = hcd_to_ehci(hcd);
+   	ehci->caps = hcd->regs + 0x100;
+   	ehci->regs = hcd->regs + 0x100 +
+ ! 		HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
+   	ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
+   	hcd->has_tt = 1;
+   	ehci->sbrn = 0x20;
+ diff -crN linux-3.2.1_o/drivers/usb/host/ehci-q.c linux-3.2.1/drivers/usb/host/ehci-q.c
+ *** linux-3.2.1_o/drivers/usb/host/ehci-q.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/host/ehci-q.c	2014-11-25 13:19:16.431735692 +0900
+ ***************
+ *** 647,653 ****
+   	/*
+   	 * data transfer stage:  buffer setup
+   	 */
+ ! 	i = urb->num_mapped_sgs;
+   	if (len > 0 && i > 0) {
+   		sg = urb->sg;
+   		buf = sg_dma_address(sg);
+ --- 647,653 ----
+   	/*
+   	 * data transfer stage:  buffer setup
+   	 */
+ ! 	i = urb->num_sgs;
+   	if (len > 0 && i > 0) {
+   		sg = urb->sg;
+   		buf = sg_dma_address(sg);
+ diff -crN linux-3.2.1_o/drivers/usb/host/ohci-omap3.c linux-3.2.1/drivers/usb/host/ohci-omap3.c
+ *** linux-3.2.1_o/drivers/usb/host/ohci-omap3.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/host/ohci-omap3.c	2014-11-25 13:19:16.431735692 +0900
+ ***************
+ *** 31,36 ****
+ --- 31,37 ----
+   
+   #include <linux/platform_device.h>
+   #include <plat/usb.h>
+ + #include <linux/pm_runtime.h>
+   
+   /*-------------------------------------------------------------------------*/
+   
+ ***************
+ *** 134,140 ****
+   	int			irq;
+   
+   	if (usb_disabled())
+ ! 		goto err_end;
+   
+   	if (!dev->parent) {
+   		dev_err(dev, "Missing parent device\n");
+ --- 135,141 ----
+   	int			irq;
+   
+   	if (usb_disabled())
+ ! 		return -ENODEV;
+   
+   	if (!dev->parent) {
+   		dev_err(dev, "Missing parent device\n");
+ ***************
+ *** 172,182 ****
+   	hcd->rsrc_len = resource_size(res);
+   	hcd->regs =  regs;
+   
+ ! 	ret = omap_usbhs_enable(dev);
+ ! 	if (ret) {
+ ! 		dev_dbg(dev, "failed to start ohci\n");
+ ! 		goto err_end;
+ ! 	}
+   
+   	ohci_hcd_init(hcd_to_ohci(hcd));
+   
+ --- 173,180 ----
+   	hcd->rsrc_len = resource_size(res);
+   	hcd->regs =  regs;
+   
+ ! 	pm_runtime_enable(dev);
+ ! 	pm_runtime_get_sync(dev);
+   
+   	ohci_hcd_init(hcd_to_ohci(hcd));
+   
+ ***************
+ *** 189,197 ****
+   	return 0;
+   
+   err_add_hcd:
+ ! 	omap_usbhs_disable(dev);
+ ! 
+ ! err_end:
+   	usb_put_hcd(hcd);
+   
+   err_io:
+ --- 187,193 ----
+   	return 0;
+   
+   err_add_hcd:
+ ! 	pm_runtime_put_sync(dev);
+   	usb_put_hcd(hcd);
+   
+   err_io:
+ ***************
+ *** 220,228 ****
+   
+   	iounmap(hcd->regs);
+   	usb_remove_hcd(hcd);
+ ! 	omap_usbhs_disable(dev);
+   	usb_put_hcd(hcd);
+ - 
+   	return 0;
+   }
+   
+ --- 216,224 ----
+   
+   	iounmap(hcd->regs);
+   	usb_remove_hcd(hcd);
+ ! 	pm_runtime_put_sync(dev);
+ ! 	pm_runtime_disable(dev);
+   	usb_put_hcd(hcd);
+   	return 0;
+   }
+   
+ diff -crN linux-3.2.1_o/drivers/usb/host/uhci-q.c linux-3.2.1/drivers/usb/host/uhci-q.c
+ *** linux-3.2.1_o/drivers/usb/host/uhci-q.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/host/uhci-q.c	2014-11-25 13:19:16.431735692 +0900
+ ***************
+ *** 943,949 ****
+   	if (usb_pipein(urb->pipe))
+   		status |= TD_CTRL_SPD;
+   
+ ! 	i = urb->num_mapped_sgs;
+   	if (len > 0 && i > 0) {
+   		sg = urb->sg;
+   		data = sg_dma_address(sg);
+ --- 943,949 ----
+   	if (usb_pipein(urb->pipe))
+   		status |= TD_CTRL_SPD;
+   
+ ! 	i = urb->num_sgs;
+   	if (len > 0 && i > 0) {
+   		sg = urb->sg;
+   		data = sg_dma_address(sg);
+ diff -crN linux-3.2.1_o/drivers/usb/host/whci/qset.c linux-3.2.1/drivers/usb/host/whci/qset.c
+ *** linux-3.2.1_o/drivers/usb/host/whci/qset.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/host/whci/qset.c	2014-11-25 13:19:16.435498010 +0900
+ ***************
+ *** 443,449 ****
+   
+   	remaining = urb->transfer_buffer_length;
+   
+ ! 	for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) {
+   		dma_addr_t dma_addr;
+   		size_t dma_remaining;
+   		dma_addr_t sp, ep;
+ --- 443,449 ----
+   
+   	remaining = urb->transfer_buffer_length;
+   
+ ! 	for_each_sg(urb->sg, sg, urb->num_sgs, i) {
+   		dma_addr_t dma_addr;
+   		size_t dma_remaining;
+   		dma_addr_t sp, ep;
+ ***************
+ *** 561,567 ****
+   
+   	remaining = urb->transfer_buffer_length;
+   
+ ! 	for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) {
+   		size_t len;
+   		size_t sg_remaining;
+   		void *orig;
+ --- 561,567 ----
+   
+   	remaining = urb->transfer_buffer_length;
+   
+ ! 	for_each_sg(urb->sg, sg, urb->num_sgs, i) {
+   		size_t len;
+   		size_t sg_remaining;
+   		void *orig;
+ diff -crN linux-3.2.1_o/drivers/usb/host/xhci.c linux-3.2.1/drivers/usb/host/xhci.c
+ *** linux-3.2.1_o/drivers/usb/host/xhci.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/host/xhci.c	2014-11-25 13:19:16.435498010 +0900
+ ***************
+ *** 1620,1626 ****
+   		/* FIXME: can we allocate more resources for the HC? */
+   		break;
+   	case COMP_BW_ERR:
+ - 	case COMP_2ND_BW_ERR:
+   		dev_warn(&udev->dev, "Not enough bandwidth "
+   				"for new device state.\n");
+   		ret = -ENOSPC;
+ --- 1620,1625 ----
+ ***************
+ *** 2797,2803 ****
+   		if (ret < 0)
+   			return ret;
+   
+ ! 		max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
+   		if (max_streams < (*num_streams - 1)) {
+   			xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
+   					eps[i]->desc.bEndpointAddress,
+ --- 2796,2803 ----
+   		if (ret < 0)
+   			return ret;
+   
+ ! 		max_streams = USB_SS_MAX_STREAMS(
+ ! 				eps[i]->ss_ep_comp.bmAttributes);
+   		if (max_streams < (*num_streams - 1)) {
+   			xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
+   					eps[i]->desc.bEndpointAddress,
+ diff -crN linux-3.2.1_o/drivers/usb/host/xhci.h linux-3.2.1/drivers/usb/host/xhci.h
+ *** linux-3.2.1_o/drivers/usb/host/xhci.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/host/xhci.h	2014-11-25 13:19:16.439503587 +0900
+ ***************
+ *** 1033,1038 ****
+ --- 1033,1039 ----
+   /* Invalid Stream ID Error */
+   #define COMP_STRID_ERR	34
+   /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */
+ + /* FIXME - check for this */
+   #define COMP_2ND_BW_ERR	35
+   /* Split Transaction Error */
+   #define	COMP_SPLIT_ERR	36
+ diff -crN linux-3.2.1_o/drivers/usb/host/xhci-ring.c linux-3.2.1/drivers/usb/host/xhci-ring.c
+ *** linux-3.2.1_o/drivers/usb/host/xhci-ring.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/host/xhci-ring.c	2014-11-25 13:19:16.439503587 +0900
+ ***************
+ *** 2561,2567 ****
+   	struct scatterlist *sg;
+   
+   	sg = NULL;
+ ! 	num_sgs = urb->num_mapped_sgs;
+   	temp = urb->transfer_buffer_length;
+   
+   	xhci_dbg(xhci, "count sg list trbs: \n");
+ --- 2561,2567 ----
+   	struct scatterlist *sg;
+   
+   	sg = NULL;
+ ! 	num_sgs = urb->num_sgs;
+   	temp = urb->transfer_buffer_length;
+   
+   	xhci_dbg(xhci, "count sg list trbs: \n");
+ ***************
+ *** 2745,2751 ****
+   		return -EINVAL;
+   
+   	num_trbs = count_sg_trbs_needed(xhci, urb);
+ ! 	num_sgs = urb->num_mapped_sgs;
+   	total_packet_count = roundup(urb->transfer_buffer_length,
+   			usb_endpoint_maxp(&urb->ep->desc));
+   
+ --- 2745,2751 ----
+   		return -EINVAL;
+   
+   	num_trbs = count_sg_trbs_needed(xhci, urb);
+ ! 	num_sgs = urb->num_sgs;
+   	total_packet_count = roundup(urb->transfer_buffer_length,
+   			usb_endpoint_maxp(&urb->ep->desc));
+   
+ diff -crN linux-3.2.1_o/drivers/usb/misc/isight_firmware.c linux-3.2.1/drivers/usb/misc/isight_firmware.c
+ *** linux-3.2.1_o/drivers/usb/misc/isight_firmware.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/misc/isight_firmware.c	2014-11-25 13:19:16.443063833 +0900
+ ***************
+ *** 55,63 ****
+   
+   	ptr = firmware->data;
+   
+ - 	buf[0] = 0x01;
+   	if (usb_control_msg
+ ! 	    (dev, usb_sndctrlpipe(dev, 0), 0xa0, 0x40, 0xe600, 0, buf, 1,
+   	     300) != 1) {
+   		printk(KERN_ERR
+   		       "Failed to initialise isight firmware loader\n");
+ --- 55,62 ----
+   
+   	ptr = firmware->data;
+   
+   	if (usb_control_msg
+ ! 	    (dev, usb_sndctrlpipe(dev, 0), 0xa0, 0x40, 0xe600, 0, "\1", 1,
+   	     300) != 1) {
+   		printk(KERN_ERR
+   		       "Failed to initialise isight firmware loader\n");
+ ***************
+ *** 101,109 ****
+   		}
+   	}
+   
+ - 	buf[0] = 0x00;
+   	if (usb_control_msg
+ ! 	    (dev, usb_sndctrlpipe(dev, 0), 0xa0, 0x40, 0xe600, 0, buf, 1,
+   	     300) != 1) {
+   		printk(KERN_ERR "isight firmware loading completion failed\n");
+   		ret = -ENODEV;
+ --- 100,107 ----
+   		}
+   	}
+   
+   	if (usb_control_msg
+ ! 	    (dev, usb_sndctrlpipe(dev, 0), 0xa0, 0x40, 0xe600, 0, "\0", 1,
+   	     300) != 1) {
+   		printk(KERN_ERR "isight firmware loading completion failed\n");
+   		ret = -ENODEV;
+ diff -crN linux-3.2.1_o/drivers/usb/musb/am35x.c linux-3.2.1/drivers/usb/musb/am35x.c
+ *** linux-3.2.1_o/drivers/usb/musb/am35x.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/musb/am35x.c	2014-11-25 13:19:16.527121316 +0900
+ ***************
+ *** 36,41 ****
+ --- 36,43 ----
+   #include <plat/usb.h>
+   
+   #include "musb_core.h"
+ + #include "cppi41.h"
+ + #include "cppi41_dma.h"
+   
+   /*
+    * AM35x specific definitions
+ ***************
+ *** 46,54 ****
+   #define USB_STAT_REG		0x08
+   #define USB_EMULATION_REG	0x0c
+   /* 0x10 Reserved */
+ - #define USB_AUTOREQ_REG		0x14
+   #define USB_SRP_FIX_TIME_REG	0x18
+ - #define USB_TEARDOWN_REG	0x1c
+   #define EP_INTR_SRC_REG		0x20
+   #define EP_INTR_SRC_SET_REG	0x24
+   #define EP_INTR_SRC_CLEAR_REG	0x28
+ --- 48,54 ----
+ ***************
+ *** 80,87 ****
+ --- 80,275 ----
+   #define AM35X_TX_INTR_MASK	(AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT)
+   #define AM35X_RX_INTR_MASK	(AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT)
+   
+ + /* CPPI 4.1 queue manager registers */
+ + #define QMGR_PEND0_REG		0x4090
+ + #define QMGR_PEND1_REG		0x4094
+ + #define QMGR_PEND2_REG		0x4098
+ + 
+   #define USB_MENTOR_CORE_OFFSET	0x400
+   
+ + #ifdef CONFIG_USB_TI_CPPI41_DMA
+ + #define CPPI41_QMGR_REG0SIZE	0x3fff
+ + 
+ + /*
+ +  * CPPI 4.1 resources used for USB OTG controller module:
+ +  *
+ +  * USB   DMA  DMA  QMgr  Tx     Src
+ +  *       Tx   Rx         QNum   Port
+ +  * ---------------------------------
+ +  * EP0   0    0    0     16,17  1
+ +  * ---------------------------------
+ +  * EP1   1    1    0     18,19  2
+ +  * ---------------------------------
+ +  * EP2   2    2    0     20,21  3
+ +  * ---------------------------------
+ +  * EP3   3    3    0     22,23  4
+ +  * ---------------------------------
+ +  */
+ + 
+ + static u16 tx_comp_q[] = {63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63, 63,
+ + 				63, 63};
+ + static u16 rx_comp_q[] = {65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65, 65,
+ + 				65, 65};
+ + 
+ + /* Fair scheduling */
+ + u32 dma_sched_table[] = {
+ + 	0x81018000, 0x83038202, 0x85058404, 0x87078606,
+ + 	0x89098808, 0x8b0b8a0a, 0x8d0d8c0c, 0x00008e0e
+ + };
+ + 
+ + /* DMA block configuration */
+ + static const struct cppi41_tx_ch tx_ch_info[] = {
+ + 	[0] = {
+ + 		.port_num	= 1,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 32} , {0, 33} }
+ + 	},
+ + 	[1] = {
+ + 		.port_num	= 2,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 34} , {0, 35} }
+ + 	},
+ + 	[2] = {
+ + 		.port_num	= 3,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 36} , {0, 37} }
+ + 	},
+ + 	[3] = {
+ + 		.port_num	= 4,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 38} , {0, 39} }
+ + 	},
+ + 	[4] = {
+ + 		.port_num	= 5,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 40} , {0, 41} }
+ + 	},
+ + 	[5] = {
+ + 		.port_num	= 6,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 42} , {0, 43} }
+ + 	},
+ + 	[6] = {
+ + 		.port_num	= 7,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 44} , {0, 45} }
+ + 	},
+ + 	[7] = {
+ + 		.port_num	= 8,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 46} , {0, 47} }
+ + 	},
+ + 	[8] = {
+ + 		.port_num	= 9,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 48} , {0, 49} }
+ + 	},
+ + 	[9] = {
+ + 		.port_num	= 10,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 50} , {0, 51} }
+ + 	},
+ + 	[10] = {
+ + 		.port_num	= 11,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 52} , {0, 53} }
+ + 	},
+ + 	[11] = {
+ + 		.port_num	= 12,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 54} , {0, 55} }
+ + 	},
+ + 	[12] = {
+ + 		.port_num	= 13,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 56} , {0, 57} }
+ + 	},
+ + 	[13] = {
+ + 		.port_num	= 14,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 58} , {0, 59} }
+ + 	},
+ + 	[14] = {
+ + 		.port_num	= 15,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 60} , {0, 61} }
+ + 	}
+ + };
+ + 
+ + /* Queues 0 to 66 are pre-assigned, others are spare */
+ + static const u32 assigned_queues[] = { 0xffffffff, 0xffffffff, 0x7 };
+ + 
+ + int __devinit cppi41_init(struct musb *musb)
+ + {
+ + 	struct usb_cppi41_info *cppi_info = &usb_cppi41_info[musb->id];
+ + 	u16 numch, blknum, order, i;
+ + 
+ + 	/* init cppi info structure  */
+ + 	cppi_info->dma_block = 0;
+ + 	for (i = 0 ; i < USB_CPPI41_NUM_CH ; i++)
+ + 		cppi_info->ep_dma_ch[i] = i;
+ + 
+ + 	cppi_info->q_mgr = 0;
+ + 	cppi_info->num_tx_comp_q = 15;
+ + 	cppi_info->num_rx_comp_q = 15;
+ + 	cppi_info->tx_comp_q = tx_comp_q;
+ + 	cppi_info->rx_comp_q = rx_comp_q;
+ + 	cppi_info->bd_intr_ctrl = 0; /* am35x dont support bd interrupt */
+ + 
+ + 	blknum = cppi_info->dma_block;
+ + 
+ + 	/* Queue manager information */
+ + 	cppi41_queue_mgr[0].num_queue = 96;
+ + 	cppi41_queue_mgr[0].queue_types = CPPI41_FREE_DESC_BUF_QUEUE |
+ + 						CPPI41_UNASSIGNED_QUEUE;
+ + 	cppi41_queue_mgr[0].base_fdbq_num = 0;
+ + 	cppi41_queue_mgr[0].assigned = assigned_queues;
+ + 
+ + 	/* init mappings */
+ + 	cppi41_queue_mgr[0].q_mgr_rgn_base = musb->ctrl_base + 0x4000;
+ + 	cppi41_queue_mgr[0].desc_mem_rgn_base = musb->ctrl_base + 0x5000;
+ + 	cppi41_queue_mgr[0].q_mgmt_rgn_base = musb->ctrl_base + 0x6000;
+ + 	cppi41_queue_mgr[0].q_stat_rgn_base = musb->ctrl_base + 0x6800;
+ + 
+ + 	/* init DMA block */
+ + 	cppi41_dma_block[0].num_tx_ch = 15;
+ + 	cppi41_dma_block[0].num_rx_ch = 15;
+ + 	cppi41_dma_block[0].tx_ch_info = tx_ch_info;
+ + 
+ + 	cppi41_dma_block[0].global_ctrl_base = musb->ctrl_base + 0x1000;
+ + 	cppi41_dma_block[0].ch_ctrl_stat_base = musb->ctrl_base + 0x1800;
+ + 	cppi41_dma_block[0].sched_ctrl_base = musb->ctrl_base + 0x2000;
+ + 	cppi41_dma_block[0].sched_table_base = musb->ctrl_base + 0x2800;
+ + 
+ + 	/* Initialize for Linking RAM region 0 alone */
+ + 	cppi41_queue_mgr_init(cppi_info->q_mgr, 0, CPPI41_QMGR_REG0SIZE);
+ + 
+ + 	numch =  USB_CPPI41_NUM_CH * 2;
+ + 	order = get_count_order(numch);
+ + 
+ + 	/* TODO: check two teardown desc per channel (5 or 7 ?)*/
+ + 	if (order < 5)
+ + 		order = 5;
+ + 
+ + 	cppi41_dma_block_init(blknum, cppi_info->q_mgr, order,
+ + 			dma_sched_table, numch);
+ + 	return 0;
+ + }
+ + void cppi41_free(void)
+ + {
+ + 	u32 numch, blknum, order;
+ + 	struct usb_cppi41_info *cppi_info = &usb_cppi41_info[0];
+ + 
+ + 	numch =  USB_CPPI41_NUM_CH * 2;
+ + 	order = get_count_order(numch);
+ + 	blknum = cppi_info->dma_block;
+ + 
+ + 	cppi41_dma_block_uninit(blknum, cppi_info->q_mgr, order,
+ + 			dma_sched_table, numch);
+ + 	cppi41_queue_mgr_uninit(cppi_info->q_mgr);
+ + }
+ + #endif /* CONFIG_USB_TI_CPPI41_DMA */
+ + 
+   struct am35x_glue {
+   	struct device		*dev;
+   	struct platform_device	*musb;
+ ***************
+ *** 228,237 ****
+ --- 416,451 ----
+   	struct omap_musb_board_data *data = plat->board_data;
+   	unsigned long flags;
+   	irqreturn_t ret = IRQ_NONE;
+ + 	u32 pend1 = 0, pend2 = 0, tx, rx;
+   	u32 epintr, usbintr;
+   
+   	spin_lock_irqsave(&musb->lock, flags);
+   
+ + 	/*
+ + 	 * CPPI 4.1 interrupts share the same IRQ and the EOI register but
+ + 	 * don't get reflected in the interrupt source/mask registers.
+ + 	 */
+ + 	if (is_cppi41_enabled(musb)) {
+ + 		/*
+ + 		 * Check for the interrupts from Tx/Rx completion queues; they
+ + 		 * are level-triggered and will stay asserted until the queues
+ + 		 * are emptied.  We're using the queue pending register 0 as a
+ + 		 * substitute for the interrupt status register and reading it
+ + 		 * directly for speed.
+ + 		 */
+ + 		pend1 = musb_readl(reg_base, QMGR_PEND1_REG);
+ + 		pend2 = musb_readl(reg_base, QMGR_PEND2_REG);
+ + 
+ + 		/* AM3517 uses 63,64,65 and 66 queues as completion queue */
+ + 		if ((pend1 & (1 << 31)) || (pend2 & (7 << 0))) {
+ + 			tx = (pend1 >> 31)  | ((pend2 & 1) ? (1 << 1) : 0);
+ + 			rx = (pend2 >> 1) & 0x3;
+ + 
+ + 			dev_dbg(musb->controller, "CPPI 4.1 IRQ: Tx %x, Rx %x\n", tx, rx);
+ + 			cppi41_completion(musb, rx, tx);
+ + 			ret = IRQ_HANDLED;
+ + 		}
+ + 	}
+   	/* Get endpoint interrupts */
+   	epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);
+   
+ ***************
+ *** 362,369 ****
+   	if (!rev)
+   		return -ENODEV;
+   
+ ! 	usb_nop_xceiv_register();
+ ! 	musb->xceiv = otg_get_transceiver();
+   	if (!musb->xceiv)
+   		return -ENODEV;
+   
+ --- 576,583 ----
+   	if (!rev)
+   		return -ENODEV;
+   
+ ! 	usb_nop_xceiv_register(musb->id);
+ ! 	musb->xceiv = otg_get_transceiver(musb->id);
+   	if (!musb->xceiv)
+   		return -ENODEV;
+   
+ ***************
+ *** 379,388 ****
+   
+   	/* Start the on-chip PHY and its PLL. */
+   	if (data->set_phy_power)
+ ! 		data->set_phy_power(1);
+   
+   	msleep(5);
+   
+   	musb->isr = am35x_musb_interrupt;
+   
+   	/* clear level interrupt */
+ --- 593,606 ----
+   
+   	/* Start the on-chip PHY and its PLL. */
+   	if (data->set_phy_power)
+ ! 		data->set_phy_power(0, 1);
+   
+   	msleep(5);
+   
+ + #ifdef CONFIG_USB_TI_CPPI41_DMA
+ + 	cppi41_init(musb);
+ + #endif
+ + 
+   	musb->isr = am35x_musb_interrupt;
+   
+   	/* clear level interrupt */
+ ***************
+ *** 403,418 ****
+   
+   	/* Shutdown the on-chip PHY and its PLL. */
+   	if (data->set_phy_power)
+ ! 		data->set_phy_power(0);
+   
+   	otg_put_transceiver(musb->xceiv);
+ ! 	usb_nop_xceiv_unregister();
+   
+   	return 0;
+   }
+   
+   /* AM35x supports only 32bit read operation */
+ ! void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
+   {
+   	void __iomem *fifo = hw_ep->fifo;
+   	u32		val;
+ --- 621,636 ----
+   
+   	/* Shutdown the on-chip PHY and its PLL. */
+   	if (data->set_phy_power)
+ ! 		data->set_phy_power(0, 0);
+   
+   	otg_put_transceiver(musb->xceiv);
+ ! 	usb_nop_xceiv_unregister(musb->id);
+   
+   	return 0;
+   }
+   
+   /* AM35x supports only 32bit read operation */
+ ! static void am35x_musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
+   {
+   	void __iomem *fifo = hw_ep->fifo;
+   	u32		val;
+ ***************
+ *** 442,447 ****
+ --- 660,667 ----
+   }
+   
+   static const struct musb_platform_ops am35x_ops = {
+ + 	.fifo_mode	= 4,
+ + 	.flags		= MUSB_GLUE_EP_ADDR_FLAT_MAPPING | MUSB_GLUE_DMA_CPPI41,
+   	.init		= am35x_musb_init,
+   	.exit		= am35x_musb_exit,
+   
+ ***************
+ *** 452,457 ****
+ --- 672,683 ----
+   	.try_idle	= am35x_musb_try_idle,
+   
+   	.set_vbus	= am35x_musb_set_vbus,
+ + 
+ + 	.read_fifo  = am35x_musb_read_fifo,
+ + 	.write_fifo = musb_write_fifo,
+ + 
+ + 	.dma_controller_create = cppi41_dma_controller_create,
+ + 	.dma_controller_destroy = cppi41_dma_controller_destroy,
+   };
+   
+   static u64 am35x_dmamask = DMA_BIT_MASK(32);
+ ***************
+ *** 473,484 ****
+   		goto err0;
+   	}
+   
+ ! 	musb = platform_device_alloc("musb-hdrc", -1);
+   	if (!musb) {
+   		dev_err(&pdev->dev, "failed to allocate musb device\n");
+   		goto err1;
+   	}
+   
+   	phy_clk = clk_get(&pdev->dev, "fck");
+   	if (IS_ERR(phy_clk)) {
+   		dev_err(&pdev->dev, "failed to get PHY clock\n");
+ --- 699,711 ----
+   		goto err0;
+   	}
+   
+ ! 	musb = platform_device_alloc("musb-hdrc", pdev->id);
+   	if (!musb) {
+   		dev_err(&pdev->dev, "failed to allocate musb device\n");
+   		goto err1;
+   	}
+   
+ + 	dev_set_name(&pdev->dev, "musb-am35x");
+   	phy_clk = clk_get(&pdev->dev, "fck");
+   	if (IS_ERR(phy_clk)) {
+   		dev_err(&pdev->dev, "failed to get PHY clock\n");
+ ***************
+ *** 566,572 ****
+   	struct am35x_glue	*glue = platform_get_drvdata(pdev);
+   
+   	platform_device_del(glue->musb);
+ ! 	platform_device_put(glue->musb);
+   	clk_disable(glue->clk);
+   	clk_disable(glue->phy_clk);
+   	clk_put(glue->clk);
+ --- 793,799 ----
+   	struct am35x_glue	*glue = platform_get_drvdata(pdev);
+   
+   	platform_device_del(glue->musb);
+ ! 	/*platform_device_put(glue->musb);*/
+   	clk_disable(glue->clk);
+   	clk_disable(glue->phy_clk);
+   	clk_put(glue->clk);
+ ***************
+ *** 585,591 ****
+   
+   	/* Shutdown the on-chip PHY and its PLL. */
+   	if (data->set_phy_power)
+ ! 		data->set_phy_power(0);
+   
+   	clk_disable(glue->phy_clk);
+   	clk_disable(glue->clk);
+ --- 812,818 ----
+   
+   	/* Shutdown the on-chip PHY and its PLL. */
+   	if (data->set_phy_power)
+ ! 		data->set_phy_power(0, 0);
+   
+   	clk_disable(glue->phy_clk);
+   	clk_disable(glue->clk);
+ ***************
+ *** 602,608 ****
+   
+   	/* Start the on-chip PHY and its PLL. */
+   	if (data->set_phy_power)
+ ! 		data->set_phy_power(1);
+   
+   	ret = clk_enable(glue->phy_clk);
+   	if (ret) {
+ --- 829,835 ----
+   
+   	/* Start the on-chip PHY and its PLL. */
+   	if (data->set_phy_power)
+ ! 		data->set_phy_power(0, 1);
+   
+   	ret = clk_enable(glue->phy_clk);
+   	if (ret) {
+ ***************
+ *** 649,654 ****
+ --- 876,884 ----
+   
+   static void __exit am35x_exit(void)
+   {
+ + #ifdef CONFIG_USB_TI_CPPI41_DMA
+ + 	cppi41_free();
+ + #endif
+   	platform_driver_unregister(&am35x_driver);
+   }
+   module_exit(am35x_exit);
+ diff -crN linux-3.2.1_o/drivers/usb/musb/blackfin.c linux-3.2.1/drivers/usb/musb/blackfin.c
+ *** linux-3.2.1_o/drivers/usb/musb/blackfin.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/musb/blackfin.c	2014-11-25 13:19:16.531506316 +0900
+ ***************
+ *** 34,40 ****
+   /*
+    * Load an endpoint's FIFO
+    */
+ ! void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
+   {
+   	struct musb *musb = hw_ep->musb;
+   	void __iomem *fifo = hw_ep->fifo;
+ --- 34,41 ----
+   /*
+    * Load an endpoint's FIFO
+    */
+ ! static void bfin_musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
+ ! 				const u8 *src)
+   {
+   	struct musb *musb = hw_ep->musb;
+   	void __iomem *fifo = hw_ep->fifo;
+ ***************
+ *** 98,104 ****
+   /*
+    * Unload an endpoint's FIFO
+    */
+ ! void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
+   {
+   	struct musb *musb = hw_ep->musb;
+   	void __iomem *fifo = hw_ep->fifo;
+ --- 99,105 ----
+   /*
+    * Unload an endpoint's FIFO
+    */
+ ! static void bfin_musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
+   {
+   	struct musb *musb = hw_ep->musb;
+   	void __iomem *fifo = hw_ep->fifo;
+ ***************
+ *** 414,421 ****
+   	}
+   	gpio_direction_output(musb->config->gpio_vrsel, 0);
+   
+ ! 	usb_nop_xceiv_register();
+ ! 	musb->xceiv = otg_get_transceiver();
+   	if (!musb->xceiv) {
+   		gpio_free(musb->config->gpio_vrsel);
+   		return -ENODEV;
+ --- 415,422 ----
+   	}
+   	gpio_direction_output(musb->config->gpio_vrsel, 0);
+   
+ ! 	usb_nop_xceiv_register(musb->id);
+ ! 	musb->xceiv = otg_get_transceiver(musb->id);
+   	if (!musb->xceiv) {
+   		gpio_free(musb->config->gpio_vrsel);
+   		return -ENODEV;
+ ***************
+ *** 441,457 ****
+   	gpio_free(musb->config->gpio_vrsel);
+   
+   	otg_put_transceiver(musb->xceiv);
+ ! 	usb_nop_xceiv_unregister();
+   	return 0;
+   }
+   
+   static const struct musb_platform_ops bfin_ops = {
+   	.init		= bfin_musb_init,
+   	.exit		= bfin_musb_exit,
+   
+   	.enable		= bfin_musb_enable,
+   	.disable	= bfin_musb_disable,
+   
+   	.set_mode	= bfin_musb_set_mode,
+   	.try_idle	= bfin_musb_try_idle,
+   
+ --- 442,464 ----
+   	gpio_free(musb->config->gpio_vrsel);
+   
+   	otg_put_transceiver(musb->xceiv);
+ ! 	usb_nop_xceiv_unregister(musb->id);
+   	return 0;
+   }
+   
+   static const struct musb_platform_ops bfin_ops = {
+ + 	.fifo_mode	= 2,
+ + 	.flags		= MUSB_GLUE_EP_ADDR_FLAT_MAPPING |
+ + 				MUSB_GLUE_DMA_INVENTRA,
+   	.init		= bfin_musb_init,
+   	.exit		= bfin_musb_exit,
+   
+   	.enable		= bfin_musb_enable,
+   	.disable	= bfin_musb_disable,
+   
+ + 	.read_fifo      = bfin_musb_read_fifo,
+ + 	.write_fifo     = bfin_musb_write_fifo,
+ + 
+   	.set_mode	= bfin_musb_set_mode,
+   	.try_idle	= bfin_musb_try_idle,
+   
+ ***************
+ *** 459,464 ****
+ --- 466,474 ----
+   	.set_vbus	= bfin_musb_set_vbus,
+   
+   	.adjust_channel_params = bfin_musb_adjust_channel_params,
+ + 
+ + 	.dma_controller_create = inventra_dma_controller_create,
+ + 	.dma_controller_destroy = inventra_dma_controller_destroy,
+   };
+   
+   static u64 bfin_dmamask = DMA_BIT_MASK(32);
+ diff -crN linux-3.2.1_o/drivers/usb/musb/cppi41.c linux-3.2.1/drivers/usb/musb/cppi41.c
+ *** linux-3.2.1_o/drivers/usb/musb/cppi41.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/drivers/usb/musb/cppi41.c	2014-11-25 13:19:16.536052811 +0900
+ ***************
+ *** 0 ****
+ --- 1,1124 ----
+ + /*
+ +  * CPPI 4.1 support
+ +  *
+ +  * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
+ +  *
+ +  * Based on the PAL CPPI 4.1 implementation
+ +  * Copyright (C) 1998-2006 Texas Instruments Incorporated
+ +  *
+ +  * This file contains the main implementation for CPPI 4.1 common peripherals,
+ +  * including the DMA Controllers and the Queue Managers.
+ +  *
+ +  * This program is free software; you can distribute it and/or modify it
+ +  * under the terms of the GNU General Public License (Version 2) as
+ +  * published by the Free Software Foundation.
+ +  *
+ +  * This program is distributed in the hope it will be useful, but WITHOUT
+ +  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ +  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ +  * for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License along
+ +  * with this program; if not, write to the Free Software Foundation, Inc.,
+ +  * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ +  *
+ +  */
+ + 
+ + #include <linux/io.h>
+ + #include <linux/init.h>
+ + #include <linux/slab.h>
+ + #include <linux/module.h>
+ + #include <linux/dma-mapping.h>
+ + 
+ + #include "cppi41.h"
+ + 
+ + #undef	CPPI41_DEBUG
+ + 
+ + #ifdef	CPPI41_DEBUG
+ + #define DBG(format, args...) printk(format, ##args)
+ + #else
+ + #define DBG(format, args...)
+ + #endif
+ + 
+ + static struct {
+ + 	void *virt_addr;
+ + 	dma_addr_t phys_addr;
+ + 	u32     size;
+ + } linking_ram[CPPI41_NUM_QUEUE_MGR];
+ + 
+ + static u32 *allocated_queues[CPPI41_NUM_QUEUE_MGR];
+ + 
+ + /* First 32 packet descriptors are reserved for unallocated memory regions. */
+ + static u32 next_desc_index[CPPI41_NUM_QUEUE_MGR] = { 1 << 5 };
+ + static u8  next_mem_rgn[CPPI41_NUM_QUEUE_MGR];
+ + 
+ + static struct {
+ + 	size_t rgn_size;
+ + 	void *virt_addr;
+ + 	dma_addr_t phys_addr;
+ + 	struct cppi41_queue_obj queue_obj;
+ + 	u8 mem_rgn;
+ + 	u16 q_mgr;
+ + 	u16 q_num;
+ + 	u32 num_desc;
+ + } dma_teardown[CPPI41_NUM_DMA_BLOCK];
+ + 
+ + struct cppi41_dma_sched_tbl_t {
+ + 	u8      pos;
+ + 	u8      dma_ch;
+ + 	u8      is_tx;
+ + 	u8      enb;
+ + };
+ + 
+ + struct cppi41_dma_sched_tbl_t dma_sched_tbl[MAX_SCHED_TBL_ENTRY] = {
+ + 	/*pos  dma_ch#  is_tx  enb/dis*/
+ + 	{ 0,    0,      0,      1},
+ + 	{ 1,    0,      1,      1},
+ + 	{ 2,    1,      0,      1},
+ + 	{ 3,    1,      1,      1},
+ + 	{ 4,    2,      0,      1},
+ + 	{ 5,    2,      1,      1},
+ + 	{ 6,    3,      0,      1},
+ + 	{ 7,    3,      1,      1}
+ + };
+ + 
+ + struct cppi41_queue_mgr cppi41_queue_mgr[CPPI41_NUM_QUEUE_MGR];
+ + EXPORT_SYMBOL(cppi41_queue_mgr);
+ + 
+ + struct cppi41_dma_block cppi41_dma_block[CPPI41_NUM_DMA_BLOCK];
+ + EXPORT_SYMBOL(cppi41_dma_block);
+ + /******************** CPPI 4.1 Functions (External Interface) *****************/
+ + 
+ + int cppi41_queue_mgr_init(u8 q_mgr, dma_addr_t rgn0_base, u16 rgn0_size)
+ + {
+ + 	void __iomem *q_mgr_regs;
+ + 	void *ptr;
+ + 
+ + 	if (q_mgr >= cppi41_num_queue_mgr)
+ + 		return -EINVAL;
+ + 
+ + 	q_mgr_regs = cppi41_queue_mgr[q_mgr].q_mgr_rgn_base;
+ + 	ptr = dma_alloc_coherent(NULL, rgn0_size * 4,
+ + 				 &linking_ram[q_mgr].phys_addr,
+ + 				 GFP_KERNEL | GFP_DMA);
+ + 	if (ptr == NULL) {
+ + 		printk(KERN_ERR "ERROR: %s: Unable to allocate "
+ + 		       "linking RAM.\n", __func__);
+ + 		return -ENOMEM;
+ + 	}
+ + 	linking_ram[q_mgr].virt_addr = ptr;
+ + 	linking_ram[q_mgr].size = rgn0_size * 4;
+ + 
+ + 	cppi_writel(linking_ram[q_mgr].phys_addr,
+ + 			q_mgr_regs + QMGR_LINKING_RAM_RGN0_BASE_REG);
+ + 	DBG("Linking RAM region 0 base @ %p, value: %x\n",
+ + 	    q_mgr_regs + QMGR_LINKING_RAM_RGN0_BASE_REG,
+ + 	    cppi_readl(q_mgr_regs + QMGR_LINKING_RAM_RGN0_BASE_REG));
+ + 
+ + 	cppi_writel(rgn0_size, q_mgr_regs + QMGR_LINKING_RAM_RGN0_SIZE_REG);
+ + 	DBG("Linking RAM region 0 size @ %p, value: %x\n",
+ + 	    q_mgr_regs + QMGR_LINKING_RAM_RGN0_SIZE_REG,
+ + 	    cppi_readl(q_mgr_regs + QMGR_LINKING_RAM_RGN0_SIZE_REG));
+ + 
+ + 	ptr = kzalloc(BITS_TO_LONGS(cppi41_queue_mgr[q_mgr].num_queue) *
+ + 			sizeof(long), GFP_KERNEL);
+ + 	if (ptr == NULL) {
+ + 		printk(KERN_ERR "ERROR: %s: Unable to allocate queue bitmap.\n",
+ + 		       __func__);
+ + 		dma_free_coherent(NULL, rgn0_size * 4,
+ + 				  linking_ram[q_mgr].virt_addr,
+ + 				  linking_ram[q_mgr].phys_addr);
+ + 		return -ENOMEM;
+ + 	}
+ + 	allocated_queues[q_mgr] = ptr;
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(cppi41_queue_mgr_init);
+ + 
+ + int cppi41_queue_mgr_uninit(u8 q_mgr)
+ + {
+ + 	void __iomem *q_mgr_regs;
+ + 
+ + 	if (q_mgr >= cppi41_num_queue_mgr)
+ + 		return -EINVAL;
+ + 
+ + 	q_mgr_regs = cppi41_queue_mgr[q_mgr].q_mgr_rgn_base;
+ + 
+ + 	/* free the Queue Mgr linking ram space */
+ + 	cppi_writel(0,	q_mgr_regs + QMGR_LINKING_RAM_RGN0_BASE_REG);
+ + 	cppi_writel(0, q_mgr_regs + QMGR_LINKING_RAM_RGN0_SIZE_REG);
+ + 	dma_free_coherent(NULL, linking_ram[q_mgr].size,
+ + 			linking_ram[q_mgr].virt_addr,
+ + 			linking_ram[q_mgr].phys_addr);
+ + 
+ + 	/* free the allocated queues */
+ + 	kfree(allocated_queues[q_mgr]);
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(cppi41_queue_mgr_uninit);
+ + 
+ + int cppi41_dma_sched_tbl_init(u8 dma_num, u8 q_mgr,
+ + 			u32 *sched_tbl, u8 tbl_size)
+ + {
+ + 	struct cppi41_dma_block *dma_block;
+ + 	int num_reg, k, i, val = 0;
+ + 
+ + 	dma_block = (struct cppi41_dma_block *)&cppi41_dma_block[dma_num];
+ + 
+ + 	num_reg = (tbl_size + 3) / 4;
+ + 	for (k = i = 0; i < num_reg; i++) {
+ + #if 0
+ + 		for (val = j = 0; j < 4; j++, k++) {
+ + 			val >>= 8;
+ + 			if (k < tbl_size)
+ + 				val |= sched_tbl[k] << 24;
+ + 		}
+ + #endif
+ + 		val = sched_tbl[i];
+ + 		cppi_writel(val, dma_block->sched_table_base +
+ + 			DMA_SCHED_TABLE_WORD_REG(i));
+ + 		DBG("DMA scheduler table @ %p, value written: %x\n",
+ + 		dma_block->sched_table_base + DMA_SCHED_TABLE_WORD_REG(i),
+ + 			val);
+ + 	}
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(cppi41_dma_sched_tbl_init);
+ + 
+ + int cppi41_schedtbl_add_dma_ch(u8 dmanum, u8 qmgr, u8 dma_ch, u8 is_tx)
+ + {
+ + 	struct cppi41_dma_block *dma_block;
+ + 	int num_ch, i, tbl_index = 0, j = 0, found = 0;
+ + 	u32 val;
+ + 
+ + 	dma_block = (struct cppi41_dma_block *)&cppi41_dma_block[dmanum];
+ + 
+ + 	val = 0;
+ + 	for (num_ch = 0, i = 0; i < MAX_SCHED_TBL_ENTRY; i++) {
+ + 		if (!found && dma_sched_tbl[i].dma_ch == dma_ch &&
+ + 			dma_sched_tbl[i].is_tx == is_tx &&
+ + 			dma_sched_tbl[i].enb == 0) {
+ + 			dma_sched_tbl[i].enb = 1;
+ + 			found = 1;
+ + 		}
+ + 
+ + 		if (dma_sched_tbl[i].enb) {
+ + 			val |= ((dma_sched_tbl[i].dma_ch |
+ + 				(dma_sched_tbl[i].is_tx ? 0 : (1<<7))) << j*8);
+ + 			num_ch++;
+ + 			j++;
+ + 		}
+ + 		if (num_ch % 4 == 0) {
+ + 			cppi_writel(val, dma_block->sched_table_base +
+ + 				DMA_SCHED_TABLE_WORD_REG(tbl_index));
+ + 			tbl_index++;
+ + 			val = j = 0;
+ + 		}
+ + 	}
+ + 
+ + 	if (num_ch % 4) {
+ + 		cppi_writel(val, dma_block->sched_table_base +
+ + 			DMA_SCHED_TABLE_WORD_REG(tbl_index));
+ + 	}
+ + 	return num_ch;
+ + }
+ + EXPORT_SYMBOL(cppi41_schedtbl_add_dma_ch);
+ + 
+ + int cppi41_schedtbl_remove_dma_ch(u8 dmanum, u8 qmgr, u8 dma_ch, u8 is_tx)
+ + {
+ + 	struct cppi41_dma_block *dma_block;
+ + 	int num_ch, i, tbl_index = 0, j = 0, found = 0;
+ + 	u32 val;
+ + 
+ + 	dma_block = (struct cppi41_dma_block *)&cppi41_dma_block[dmanum];
+ + 
+ + 	val = 0;
+ + 	for (num_ch = 0, i = 0; i < MAX_SCHED_TBL_ENTRY; i++) {
+ + 		if (!found && dma_sched_tbl[i].dma_ch == dma_ch &&
+ + 			dma_sched_tbl[i].is_tx == is_tx &&
+ + 			dma_sched_tbl[i].enb == 1) {
+ + 			dma_sched_tbl[i].enb = 0;
+ + 		}
+ + 
+ + 		if (dma_sched_tbl[i].enb) {
+ + 			val |= ((dma_sched_tbl[i].dma_ch |
+ + 				(dma_sched_tbl[i].is_tx ? 0 : (1<<7))) << j*8);
+ + 			num_ch++;
+ + 			j++;
+ + 		}
+ + 		if (num_ch % 4 == 0) {
+ + 			cppi_writel(val, dma_block->sched_table_base +
+ + 				DMA_SCHED_TABLE_WORD_REG(tbl_index));
+ + 			tbl_index++;
+ + 			val = j = 0;
+ + 		}
+ + 	}
+ + 
+ + 	if (num_ch % 4) {
+ + 		cppi_writel(val, dma_block->sched_table_base +
+ + 			DMA_SCHED_TABLE_WORD_REG(tbl_index));
+ + 	}
+ + 	return num_ch;
+ + }
+ + EXPORT_SYMBOL(cppi41_schedtbl_remove_dma_ch);
+ + 
+ + int cppi41_dma_block_init(u8 dma_num, u8 q_mgr, u8 num_order,
+ + 				 u32 *sched_tbl, u8 tbl_size)
+ + {
+ + 	const struct cppi41_dma_block *dma_block;
+ + 	unsigned num_desc, num_reg;
+ + 	void *ptr;
+ + 	int error, i;
+ + 	u16 q_num;
+ + 	u32 val;
+ + 
+ + 	if (dma_num >= cppi41_num_dma_block ||
+ + 	    q_mgr >= cppi41_num_queue_mgr ||
+ + 	    !tbl_size || sched_tbl == NULL)
+ + 		return -EINVAL;
+ + 
+ + 	error = cppi41_queue_alloc(CPPI41_FREE_DESC_QUEUE |
+ + 				   CPPI41_UNASSIGNED_QUEUE, q_mgr, &q_num);
+ + 	if (error) {
+ + 		printk(KERN_ERR "ERROR: %s: Unable to allocate teardown "
+ + 		       "descriptor queue.\n", __func__);
+ + 		return error;
+ + 	}
+ + 	DBG("Teardown descriptor queue %d in queue manager 0 "
+ + 	    "allocated\n", q_num);
+ + 
+ + 	/*
+ + 	 * Tell the hardware about the Teardown descriptor
+ + 	 * queue manager and queue number.
+ + 	 */
+ + 	dma_block = &cppi41_dma_block[dma_num];
+ + 	cppi_writel((q_mgr << DMA_TD_DESC_QMGR_SHIFT) |
+ + 		     (q_num << DMA_TD_DESC_QNUM_SHIFT),
+ + 		     dma_block->global_ctrl_base +
+ + 		     DMA_TEARDOWN_FREE_DESC_CTRL_REG);
+ + 	DBG("Teardown free descriptor control @ %p, value: %x\n",
+ + 	    dma_block->global_ctrl_base + DMA_TEARDOWN_FREE_DESC_CTRL_REG,
+ + 	    cppi_readl(dma_block->global_ctrl_base +
+ + 			DMA_TEARDOWN_FREE_DESC_CTRL_REG));
+ + 
+ + 	num_desc = 1 << num_order;
+ + 	dma_teardown[dma_num].rgn_size = num_desc *
+ + 					 sizeof(struct cppi41_teardown_desc);
+ + 
+ + 	/* Pre-allocate teardown descriptors. */
+ + 	ptr = dma_alloc_coherent(NULL, dma_teardown[dma_num].rgn_size,
+ + 				 &dma_teardown[dma_num].phys_addr,
+ + 				 GFP_KERNEL | GFP_DMA);
+ + 	if (ptr == NULL) {
+ + 		printk(KERN_ERR "ERROR: %s: Unable to allocate teardown "
+ + 		       "descriptors.\n", __func__);
+ + 		error = -ENOMEM;
+ + 		goto free_queue;
+ + 	}
+ + 	dma_teardown[dma_num].virt_addr = ptr;
+ + 
+ + 	error = cppi41_mem_rgn_alloc(q_mgr, dma_teardown[dma_num].phys_addr, 5,
+ + 				     num_order, &dma_teardown[dma_num].mem_rgn);
+ + 	if (error) {
+ + 		printk(KERN_ERR "ERROR: %s: Unable to allocate queue manager "
+ + 		       "memory region for teardown descriptors.\n", __func__);
+ + 		goto free_mem;
+ + 	}
+ + 
+ + 	error = cppi41_queue_init(&dma_teardown[dma_num].queue_obj, 0, q_num);
+ + 	if (error) {
+ + 		printk(KERN_ERR "ERROR: %s: Unable to initialize teardown "
+ + 		       "free descriptor queue.\n", __func__);
+ + 		goto free_rgn;
+ + 	}
+ + 
+ + 	dma_teardown[dma_num].q_num = q_num;
+ + 	dma_teardown[dma_num].q_mgr = q_mgr;
+ + 	dma_teardown[dma_num].num_desc = num_desc;
+ + 	/*
+ + 	 * Push all teardown descriptors to the free teardown queue
+ + 	 * for the CPPI 4.1 system.
+ + 	 */
+ + 	cppi41_init_teardown_queue(dma_num);
+ + 
+ + 	/* Initialize the DMA scheduler. */
+ + 	num_reg = (tbl_size + 3) / 4;
+ + 	for (i = 0; i < num_reg; i++) {
+ + 		val = sched_tbl[i];
+ + 		cppi_writel(val, dma_block->sched_table_base +
+ + 			     DMA_SCHED_TABLE_WORD_REG(i));
+ + 		DBG("DMA scheduler table @ %p, value written: %x\n",
+ + 		    dma_block->sched_table_base + DMA_SCHED_TABLE_WORD_REG(i),
+ + 		    val);
+ + 	}
+ + 
+ + 	cppi_writel((tbl_size - 1) << DMA_SCHED_LAST_ENTRY_SHIFT |
+ + 		     DMA_SCHED_ENABLE_MASK,
+ + 		     dma_block->sched_ctrl_base + DMA_SCHED_CTRL_REG);
+ + 	DBG("DMA scheduler control @ %p, value: %x\n",
+ + 	    dma_block->sched_ctrl_base + DMA_SCHED_CTRL_REG,
+ + 	    cppi_readl(dma_block->sched_ctrl_base + DMA_SCHED_CTRL_REG));
+ + 
+ + 	return 0;
+ + 
+ + free_rgn:
+ + 	cppi41_mem_rgn_free(q_mgr, dma_teardown[dma_num].mem_rgn);
+ + free_mem:
+ + 	dma_free_coherent(NULL, dma_teardown[dma_num].rgn_size,
+ + 			  dma_teardown[dma_num].virt_addr,
+ + 			  dma_teardown[dma_num].phys_addr);
+ + free_queue:
+ + 	cppi41_queue_free(q_mgr, q_num);
+ + 	return error;
+ + }
+ + EXPORT_SYMBOL(cppi41_dma_block_init);
+ + 
+ + int cppi41_dma_block_uninit(u8 dma_num, u8 q_mgr, u8 num_order,
+ + 				 u32 *sched_tbl, u8 tbl_size)
+ + {
+ + 	const struct cppi41_dma_block *dma_block;
+ + 	unsigned num_reg;
+ + 	int i;
+ + 
+ + 	/* popout all teardown descriptors */
+ + 	cppi41_free_teardown_queue(dma_num);
+ + 
+ + 	/* free queue mgr region */
+ + 	cppi41_mem_rgn_free(q_mgr, dma_teardown[dma_num].mem_rgn);
+ + 	/* free the allocated teardown descriptors */
+ + 	dma_free_coherent(NULL, dma_teardown[dma_num].rgn_size,
+ + 			dma_teardown[dma_num].virt_addr,
+ + 			dma_teardown[dma_num].phys_addr);
+ + 
+ + 	/* free the teardown queue*/
+ + 	cppi41_queue_free(dma_teardown[dma_num].q_mgr,
+ + 			dma_teardown[dma_num].q_num);
+ + 
+ + 	dma_block = (struct cppi41_dma_block *)&cppi41_dma_block[dma_num];
+ + 	/* disable the dma schedular */
+ + 	num_reg = (tbl_size + 3) / 4;
+ + 	for (i = 0; i < num_reg; i++) {
+ + 		cppi_writel(0, dma_block->sched_table_base +
+ + 			     DMA_SCHED_TABLE_WORD_REG(i));
+ + 		DBG("DMA scheduler table @ %p, value written: %x\n",
+ + 		    dma_block->sched_table_base + DMA_SCHED_TABLE_WORD_REG(i),
+ + 		    0);
+ + 	}
+ + 
+ + 	cppi_writel(0,	dma_block->sched_ctrl_base + DMA_SCHED_CTRL_REG);
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(cppi41_dma_block_uninit);
+ + /*
+ +  * cppi41_mem_rgn_alloc - allocate a memory region within the queue manager
+ +  */
+ + int cppi41_mem_rgn_alloc(u8 q_mgr, dma_addr_t rgn_addr, u8 size_order,
+ + 			 u8 num_order, u8 *mem_rgn)
+ + {
+ + 	void __iomem *desc_mem_regs;
+ + 	u32 num_desc = 1 << num_order, index, ctrl;
+ + 	int rgn;
+ + 
+ + 	DBG("%s called with rgn_addr = %08x, size_order = %d, num_order = %d\n",
+ + 	    __func__, rgn_addr, size_order, num_order);
+ + 
+ + 	if (q_mgr >= cppi41_num_queue_mgr ||
+ + 	    size_order < 5 || size_order > 13 ||
+ + 	    num_order  < 5 || num_order  > 12 ||
+ + 	    (rgn_addr & ((1 << size_order) - 1)))
+ + 		return -EINVAL;
+ + 
+ + 	rgn = next_mem_rgn[q_mgr];
+ + 	index = next_desc_index[q_mgr];
+ + 	if (rgn >= CPPI41_MAX_MEM_RGN || index + num_desc > 0x4000)
+ + 		return -ENOSPC;
+ + 
+ + 	next_mem_rgn[q_mgr] = rgn + 1;
+ + 	next_desc_index[q_mgr] = index + num_desc;
+ + 
+ + 	desc_mem_regs = cppi41_queue_mgr[q_mgr].desc_mem_rgn_base;
+ + 
+ + 	/* Write the base register */
+ + 	cppi_writel(rgn_addr, desc_mem_regs + QMGR_MEM_RGN_BASE_REG(rgn));
+ + 	DBG("Descriptor region base @ %p, value: %x\n",
+ + 	    desc_mem_regs + QMGR_MEM_RGN_BASE_REG(rgn),
+ + 	    cppi_readl(desc_mem_regs + QMGR_MEM_RGN_BASE_REG(rgn)));
+ + 
+ + 	/* Write the control register */
+ + 	ctrl = ((index << QMGR_MEM_RGN_INDEX_SHIFT) &
+ + 		QMGR_MEM_RGN_INDEX_MASK) |
+ + 	       (((size_order - 5) << QMGR_MEM_RGN_DESC_SIZE_SHIFT) &
+ + 		QMGR_MEM_RGN_DESC_SIZE_MASK) |
+ + 	       (((num_order - 5) << QMGR_MEM_RGN_SIZE_SHIFT) &
+ + 		QMGR_MEM_RGN_SIZE_MASK);
+ + 	cppi_writel(ctrl, desc_mem_regs + QMGR_MEM_RGN_CTRL_REG(rgn));
+ + 	DBG("Descriptor region control @ %p, value: %x\n",
+ + 	    desc_mem_regs + QMGR_MEM_RGN_CTRL_REG(rgn),
+ + 	    cppi_readl(desc_mem_regs + QMGR_MEM_RGN_CTRL_REG(rgn)));
+ + 
+ + 	*mem_rgn = rgn;
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(cppi41_mem_rgn_alloc);
+ + 
+ + /*
+ +  * cppi41_mem_rgn_free - free the memory region within the queue manager
+ +  */
+ + int cppi41_mem_rgn_free(u8 q_mgr, u8 mem_rgn)
+ + {
+ + 	void __iomem *desc_mem_regs;
+ + 
+ + 	DBG("%s called.\n", __func__);
+ + 
+ + 	if (q_mgr >= cppi41_num_queue_mgr || mem_rgn >= next_mem_rgn[q_mgr])
+ + 		return -EINVAL;
+ + 
+ + 	desc_mem_regs = cppi41_queue_mgr[q_mgr].desc_mem_rgn_base;
+ + 
+ + 	if (cppi_readl(desc_mem_regs + QMGR_MEM_RGN_BASE_REG(mem_rgn)) == 0)
+ + 		return -ENOENT;
+ + 
+ + 	cppi_writel(0, desc_mem_regs + QMGR_MEM_RGN_BASE_REG(mem_rgn));
+ + 	cppi_writel(0, desc_mem_regs + QMGR_MEM_RGN_CTRL_REG(mem_rgn));
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(cppi41_mem_rgn_free);
+ + 
+ + /*
+ +  * cppi41_tx_ch_init - initialize a CPPI 4.1 Tx channel object
+ +  *
+ +  * Verify the channel info (range checking, etc.) and store the channel
+ +  * information within the object structure.
+ +  */
+ + int cppi41_tx_ch_init(struct cppi41_dma_ch_obj *tx_ch_obj,
+ + 		      u8 dma_num, u8 ch_num)
+ + {
+ + 	if (dma_num >= cppi41_num_dma_block ||
+ + 	    ch_num  >= cppi41_dma_block[dma_num].num_tx_ch)
+ + 		return -EINVAL;
+ + 
+ + 	/* Populate the channel object structure */
+ + 	tx_ch_obj->base_addr  = cppi41_dma_block[dma_num].ch_ctrl_stat_base +
+ + 				DMA_CH_TX_GLOBAL_CFG_REG(ch_num);
+ + 	tx_ch_obj->global_cfg = cppi_readl(tx_ch_obj->base_addr);
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(cppi41_tx_ch_init);
+ + 
+ + /*
+ +  * cppi41_rx_ch_init - initialize a CPPI 4.1 Rx channel object
+ +  *
+ +  * Verify the channel info (range checking, etc.) and store the channel
+ +  * information within the object structure.
+ +  */
+ + int cppi41_rx_ch_init(struct cppi41_dma_ch_obj *rx_ch_obj,
+ + 		      u8 dma_num, u8 ch_num)
+ + {
+ + 	if (dma_num >= cppi41_num_dma_block ||
+ + 	    ch_num  >= cppi41_dma_block[dma_num].num_rx_ch)
+ + 		return -EINVAL;
+ + 
+ + 	/* Populate the channel object structure */
+ + 	rx_ch_obj->base_addr  = cppi41_dma_block[dma_num].ch_ctrl_stat_base +
+ + 				DMA_CH_RX_GLOBAL_CFG_REG(ch_num);
+ + 	rx_ch_obj->global_cfg = cppi_readl(rx_ch_obj->base_addr);
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(cppi41_rx_ch_init);
+ + 
+ + /*
+ +  * We have to cache the last written Rx/Tx channel global configration register
+ +  * value due to its bits other than enable/teardown being write-only. Yet there
+ +  * is a caveat related to caching the enable bit: this bit may be automatically
+ +  * cleared as a result of teardown, so we can't trust its cached value!
+ +  * When modifying the write only register fields, we're making use of the fact
+ +  * that they read back as zeros, and not clearing them explicitly...
+ +  */
+ + 
+ + /*
+ +  * cppi41_dma_ch_default_queue - set CPPI 4.1 channel default completion queue
+ +  */
+ + void cppi41_dma_ch_default_queue(struct cppi41_dma_ch_obj *dma_ch_obj,
+ + 				 u8 q_mgr, u16 q_num)
+ + {
+ + 	u32 val = dma_ch_obj->global_cfg;
+ + 
+ + 	/* Clear the fields to be modified. */
+ + 	val &= ~(DMA_CH_TX_DEFAULT_QMGR_MASK | DMA_CH_TX_DEFAULT_QNUM_MASK |
+ + 		 DMA_CH_TX_ENABLE_MASK);
+ + 
+ + 	/* Set the default completion queue. */
+ + 	val |= ((q_mgr << DMA_CH_TX_DEFAULT_QMGR_SHIFT) &
+ + 		DMA_CH_TX_DEFAULT_QMGR_MASK) |
+ + 	       ((q_num << DMA_CH_TX_DEFAULT_QNUM_SHIFT) &
+ + 		DMA_CH_TX_DEFAULT_QNUM_MASK);
+ + 
+ + 	/* Get the current state of the enable bit. */
+ + 	dma_ch_obj->global_cfg = val |= cppi_readl(dma_ch_obj->base_addr);
+ + 	cppi_writel(val, dma_ch_obj->base_addr);
+ + 	DBG("Channel global configuration @ %p, value written: %x, "
+ + 	    "value read: %x\n", dma_ch_obj->base_addr, val,
+ + 	    cppi_readl(dma_ch_obj->base_addr));
+ + 
+ + }
+ + EXPORT_SYMBOL(cppi41_dma_ch_default_queue);
+ + 
+ + /*
+ +  * cppi41_rx_ch_configure - configure CPPI 4.1 Rx channel
+ +  */
+ + void cppi41_rx_ch_configure(struct cppi41_dma_ch_obj *rx_ch_obj,
+ + 			    struct cppi41_rx_ch_cfg  *cfg)
+ + {
+ + 	void __iomem *base = rx_ch_obj->base_addr;
+ + 	u32 val = cppi_readl(rx_ch_obj->base_addr);
+ + 
+ + 	val |= ((cfg->sop_offset << DMA_CH_RX_SOP_OFFSET_SHIFT) &
+ + 		DMA_CH_RX_SOP_OFFSET_MASK) |
+ + 	       ((cfg->default_desc_type << DMA_CH_RX_DEFAULT_DESC_TYPE_SHIFT) &
+ + 		DMA_CH_RX_DEFAULT_DESC_TYPE_MASK) |
+ + 	       ((cfg->retry_starved << DMA_CH_RX_ERROR_HANDLING_SHIFT) &
+ + 		DMA_CH_RX_ERROR_HANDLING_MASK) |
+ + 	       ((cfg->rx_queue.q_mgr << DMA_CH_RX_DEFAULT_RQ_QMGR_SHIFT) &
+ + 		DMA_CH_RX_DEFAULT_RQ_QMGR_MASK) |
+ + 	       ((cfg->rx_queue.q_num << DMA_CH_RX_DEFAULT_RQ_QNUM_SHIFT) &
+ + 		DMA_CH_RX_DEFAULT_RQ_QNUM_MASK);
+ + 
+ + 	val &= ~(0x7 << DMA_CH_RX_MAX_BUF_CNT_SHIFT);
+ + 	val |= (cfg->rx_max_buf_cnt << DMA_CH_RX_MAX_BUF_CNT_SHIFT);
+ + 
+ + 	rx_ch_obj->global_cfg = val;
+ + 	cppi_writel(val, base);
+ + 	DBG("Rx channel global configuration @ %p, value written: %x, "
+ + 	    "value read: %x\n", base, val, cppi_readl(base));
+ + 
+ + 	base -= DMA_CH_RX_GLOBAL_CFG_REG(0);
+ + 
+ + 	/*
+ + 	 * Set up the packet configuration register
+ + 	 * based on the descriptor type...
+ + 	 */
+ + 	switch (cfg->default_desc_type) {
+ + 	case DMA_CH_RX_DEFAULT_DESC_EMBED:
+ + 		val = ((cfg->cfg.embed_pkt.fd_queue.q_mgr <<
+ + 			DMA_CH_RX_EMBED_FDQ_QMGR_SHIFT) &
+ + 		       DMA_CH_RX_EMBED_FDQ_QMGR_MASK) |
+ + 		      ((cfg->cfg.embed_pkt.fd_queue.q_num <<
+ + 			DMA_CH_RX_EMBED_FDQ_QNUM_SHIFT) &
+ + 		       DMA_CH_RX_EMBED_FDQ_QNUM_MASK) |
+ + 		      ((cfg->cfg.embed_pkt.num_buf_slot <<
+ + 			DMA_CH_RX_EMBED_NUM_SLOT_SHIFT) &
+ + 		       DMA_CH_RX_EMBED_NUM_SLOT_MASK) |
+ + 		      ((cfg->cfg.embed_pkt.sop_slot_num <<
+ + 			DMA_CH_RX_EMBED_SOP_SLOT_SHIFT) &
+ + 		       DMA_CH_RX_EMBED_SOP_SLOT_MASK);
+ + 
+ + 		cppi_writel(val, base + DMA_CH_RX_EMBED_PKT_CFG_REG_B(0));
+ + 		DBG("Rx channel embedded packet configuration B @ %p, "
+ + 		    "value written: %x\n",
+ + 		    base + DMA_CH_RX_EMBED_PKT_CFG_REG_B(0), val);
+ + 
+ + 		val = ((cfg->cfg.embed_pkt.free_buf_pool[0].b_pool <<
+ + 			DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(0)) &
+ + 		       DMA_CH_RX_EMBED_FBP_PNUM_MASK(0)) |
+ + 		      ((cfg->cfg.embed_pkt.free_buf_pool[0].b_mgr <<
+ + 			DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(0)) &
+ + 		       DMA_CH_RX_EMBED_FBP_BMGR_MASK(0)) |
+ + 		      ((cfg->cfg.embed_pkt.free_buf_pool[1].b_pool <<
+ + 			DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(1)) &
+ + 		       DMA_CH_RX_EMBED_FBP_PNUM_MASK(1)) |
+ + 		      ((cfg->cfg.embed_pkt.free_buf_pool[1].b_mgr <<
+ + 			DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(1)) &
+ + 		       DMA_CH_RX_EMBED_FBP_BMGR_MASK(1)) |
+ + 		      ((cfg->cfg.embed_pkt.free_buf_pool[2].b_pool <<
+ + 			DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(2)) &
+ + 		       DMA_CH_RX_EMBED_FBP_PNUM_MASK(2)) |
+ + 		      ((cfg->cfg.embed_pkt.free_buf_pool[2].b_mgr <<
+ + 			DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(2)) &
+ + 		       DMA_CH_RX_EMBED_FBP_BMGR_MASK(2)) |
+ + 		      ((cfg->cfg.embed_pkt.free_buf_pool[3].b_pool <<
+ + 			DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(3)) &
+ + 		       DMA_CH_RX_EMBED_FBP_PNUM_MASK(3)) |
+ + 		      ((cfg->cfg.embed_pkt.free_buf_pool[3].b_mgr <<
+ + 			DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(3)) &
+ + 		       DMA_CH_RX_EMBED_FBP_BMGR_MASK(3));
+ + 
+ + 		cppi_writel(val, base + DMA_CH_RX_EMBED_PKT_CFG_REG_A(0));
+ + 		DBG("Rx channel embedded packet configuration A @ %p, "
+ + 		    "value written: %x\n",
+ + 		    base + DMA_CH_RX_EMBED_PKT_CFG_REG_A(0), val);
+ + 		break;
+ + 	case DMA_CH_RX_DEFAULT_DESC_HOST:
+ + 		val = ((cfg->cfg.host_pkt.fdb_queue[0].q_num <<
+ + 			DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(0)) &
+ + 		       DMA_CH_RX_HOST_FDQ_QNUM_MASK(0)) |
+ + 		      ((cfg->cfg.host_pkt.fdb_queue[0].q_mgr <<
+ + 			DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(0)) &
+ + 		       DMA_CH_RX_HOST_FDQ_QMGR_MASK(0)) |
+ + 		      ((cfg->cfg.host_pkt.fdb_queue[1].q_num <<
+ + 			DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(1)) &
+ + 		       DMA_CH_RX_HOST_FDQ_QNUM_MASK(1)) |
+ + 		      ((cfg->cfg.host_pkt.fdb_queue[1].q_mgr <<
+ + 			DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(1)) &
+ + 		       DMA_CH_RX_HOST_FDQ_QMGR_MASK(1));
+ + 
+ + 		cppi_writel(val, base + DMA_CH_RX_HOST_PKT_CFG_REG_A(0));
+ + 		DBG("Rx channel host packet configuration A @ %p, "
+ + 		    "value written: %x\n",
+ + 		    base + DMA_CH_RX_HOST_PKT_CFG_REG_A(0), val);
+ + 
+ + 		val = ((cfg->cfg.host_pkt.fdb_queue[2].q_num <<
+ + 			DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(2)) &
+ + 		       DMA_CH_RX_HOST_FDQ_QNUM_MASK(2)) |
+ + 		      ((cfg->cfg.host_pkt.fdb_queue[2].q_mgr <<
+ + 			DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(2)) &
+ + 		       DMA_CH_RX_HOST_FDQ_QMGR_MASK(2)) |
+ + 		      ((cfg->cfg.host_pkt.fdb_queue[3].q_num <<
+ + 		       DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(3)) &
+ + 		       DMA_CH_RX_HOST_FDQ_QNUM_MASK(3)) |
+ + 		      ((cfg->cfg.host_pkt.fdb_queue[3].q_mgr <<
+ + 			DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(3)) &
+ + 		       DMA_CH_RX_HOST_FDQ_QMGR_MASK(3));
+ + 
+ + 		cppi_writel(val, base + DMA_CH_RX_HOST_PKT_CFG_REG_B(0));
+ + 		DBG("Rx channel host packet configuration B @ %p, "
+ + 		    "value written: %x\n",
+ + 		    base + DMA_CH_RX_HOST_PKT_CFG_REG_B(0), val);
+ + 		break;
+ + 	case DMA_CH_RX_DEFAULT_DESC_MONO:
+ + 		val = ((cfg->cfg.mono_pkt.fd_queue.q_num <<
+ + 			DMA_CH_RX_MONO_FDQ_QNUM_SHIFT) &
+ + 		       DMA_CH_RX_MONO_FDQ_QNUM_MASK) |
+ + 		      ((cfg->cfg.mono_pkt.fd_queue.q_mgr <<
+ + 			DMA_CH_RX_MONO_FDQ_QMGR_SHIFT) &
+ + 		       DMA_CH_RX_MONO_FDQ_QMGR_MASK) |
+ + 		      ((cfg->cfg.mono_pkt.sop_offset <<
+ + 			DMA_CH_RX_MONO_SOP_OFFSET_SHIFT) &
+ + 		       DMA_CH_RX_MONO_SOP_OFFSET_MASK);
+ + 
+ + 		cppi_writel(val, base + DMA_CH_RX_MONO_PKT_CFG_REG(0));
+ + 		DBG("Rx channel monolithic packet configuration @ %p, "
+ + 		    "value written: %x\n",
+ + 		    base + DMA_CH_RX_MONO_PKT_CFG_REG(0), val);
+ + 		break;
+ + 	}
+ + }
+ + EXPORT_SYMBOL(cppi41_rx_ch_configure);
+ + 
+ + void cppi41_rx_ch_set_maxbufcnt(struct cppi41_dma_ch_obj *rx_ch_obj,
+ + 			    u8 rx_max_buf_cnt)
+ + {
+ + 	void __iomem *base = rx_ch_obj->base_addr;
+ + 	u32 val = cppi_readl(rx_ch_obj->base_addr);
+ + 
+ + 	val = rx_ch_obj->global_cfg;
+ + 	val &= ~(0x7 << DMA_CH_RX_MAX_BUF_CNT_SHIFT);
+ + 	val |= (rx_max_buf_cnt << DMA_CH_RX_MAX_BUF_CNT_SHIFT);
+ + 
+ + 	rx_ch_obj->global_cfg = val;
+ + 	cppi_writel(val, base);
+ + 
+ + 	DBG("%s: rx-global-cfg @ %p, value written: %x, "
+ + 	    "value read: %x\n", __func__, base, val, cppi_readl(base));
+ + 
+ + }
+ + EXPORT_SYMBOL(cppi41_rx_ch_set_maxbufcnt);
+ + /*
+ +  * cppi41_dma_ch_teardown - teardown a given Tx/Rx channel
+ +  */
+ + void cppi41_dma_ch_teardown(struct cppi41_dma_ch_obj *dma_ch_obj)
+ + {
+ + 	u32 val = cppi_readl(dma_ch_obj->base_addr);
+ + 
+ + 	/* Initiate channel teardown. */
+ + 	val |= dma_ch_obj->global_cfg & ~DMA_CH_TX_ENABLE_MASK;
+ + 	dma_ch_obj->global_cfg = val |= DMA_CH_TX_TEARDOWN_MASK;
+ + 	cppi_writel(val, dma_ch_obj->base_addr);
+ + 	DBG("Tear down channel @ %p, value written: %x, value read: %x\n",
+ + 	    dma_ch_obj->base_addr, val, cppi_readl(dma_ch_obj->base_addr));
+ + }
+ + EXPORT_SYMBOL(cppi41_dma_ch_teardown);
+ + 
+ + /*
+ +  * cppi41_dma_ch_enable - enable Tx/Rx DMA channel in hardware
+ +  *
+ +  * Makes the channel ready for data transmission/reception.
+ +  */
+ + void cppi41_dma_ch_enable(struct cppi41_dma_ch_obj *dma_ch_obj)
+ + {
+ + 	u32 val = dma_ch_obj->global_cfg | DMA_CH_TX_ENABLE_MASK;
+ + 
+ + 	/* Teardown bit remains set after completion, so clear it now... */
+ + 	dma_ch_obj->global_cfg = val &= ~DMA_CH_TX_TEARDOWN_MASK;
+ + 	cppi_writel(val, dma_ch_obj->base_addr);
+ + 	DBG("Enable channel @ %p, value written: %x, value read: %x\n",
+ + 	    dma_ch_obj->base_addr, val, cppi_readl(dma_ch_obj->base_addr));
+ + }
+ + EXPORT_SYMBOL(cppi41_dma_ch_enable);
+ + 
+ + /*
+ +  * cppi41_dma_ch_disable - disable Tx/Rx DMA channel in hardware
+ +  */
+ + void cppi41_dma_ch_disable(struct cppi41_dma_ch_obj *dma_ch_obj)
+ + {
+ + 	dma_ch_obj->global_cfg &= ~DMA_CH_TX_ENABLE_MASK;
+ + 	cppi_writel(dma_ch_obj->global_cfg, dma_ch_obj->base_addr);
+ + 	DBG("Disable channel @ %p, value written: %x, value read: %x\n",
+ + 	    dma_ch_obj->base_addr, dma_ch_obj->global_cfg,
+ + 	    cppi_readl(dma_ch_obj->base_addr));
+ + }
+ + EXPORT_SYMBOL(cppi41_dma_ch_disable);
+ + 
+ + void cppi41_init_teardown_queue(int dma_num)
+ + {
+ + 	dma_addr_t td_addr;
+ + 	struct cppi41_teardown_desc *curr_td;
+ + 	u32 num_desc = dma_teardown[dma_num].num_desc;
+ + 	int i;
+ + 
+ + 	curr_td = dma_teardown[dma_num].virt_addr;
+ + 	td_addr = dma_teardown[dma_num].phys_addr;
+ + 
+ + 	for (i = 0; i < num_desc; i++) {
+ + 		cppi41_queue_push(&dma_teardown[dma_num].queue_obj, td_addr,
+ + 				  sizeof(*curr_td), 0);
+ + 		td_addr += sizeof(*curr_td);
+ + 	}
+ + }
+ + EXPORT_SYMBOL(cppi41_init_teardown_queue);
+ + 
+ + void cppi41_free_teardown_queue(int dma_num)
+ + {
+ + 	unsigned long td_addr;
+ + 	u32 num_desc = dma_teardown[dma_num].num_desc;
+ + 
+ + 	while (num_desc--) {
+ + 		td_addr = cppi41_queue_pop(&dma_teardown[dma_num].queue_obj);
+ + 
+ + 		if (td_addr == 0)
+ + 			break;
+ + 	}
+ + }
+ + EXPORT_SYMBOL(cppi41_free_teardown_queue);
+ + 
+ + /**
+ +  * alloc_queue - allocate a queue in the given range
+ +  * @allocated:	pointer to the bitmap of the allocated queues
+ +  * @excluded:	pointer to the bitmap of the queues excluded from allocation
+ +  *		(optional)
+ +  * @start:	starting queue number
+ +  * @count:	number of queues available
+ +  *
+ +  * Returns queue number on success, -ENOSPC otherwise.
+ +  */
+ + static int alloc_queue(u32 *allocated, const u32 *excluded, unsigned start,
+ + 		       unsigned count)
+ + {
+ + 	u32 bit, mask = 0;
+ + 	int index = -1;
+ + 
+ + 	/*
+ + 	 * We're starting the loop as if we've just wrapped around 32 bits
+ + 	 * in order to save on preloading the bitmasks.
+ + 	 */
+ + 	for (bit = 0; count--; start++, bit <<= 1) {
+ + 		/* Have we just wrapped around 32 bits? */
+ + 		if (!bit) {
+ + 			/* Start over with the next bitmask word */
+ + 			bit = 1;
+ + 			index++;
+ + 			/* Have we just entered the loop? */
+ + 			if (!index) {
+ + 				/* Calculate the starting values */
+ + 				bit <<= start & 0x1f;
+ + 				index = start >> 5;
+ + 			}
+ + 			/*
+ + 			 * Load the next word of the allocated bitmask OR'ing
+ + 			 * it with the excluded bitmask if it's been passed.
+ + 			 */
+ + 			mask = allocated[index];
+ + 			if (excluded != NULL)
+ + 				mask |= excluded[index];
+ + 		}
+ + 		/*
+ + 		 * If the bit in the combined bitmask is zero,
+ + 		 * we've just found a free queue.
+ + 		 */
+ + 		if (!(mask & bit)) {
+ + 			allocated[index] |= bit;
+ + 			return start;
+ + 		}
+ + 	}
+ + 	return -ENOSPC;
+ + }
+ + 
+ + /*
+ +  * cppi41_queue_alloc - allocate a queue of a given type in the queue manager
+ +  */
+ + int cppi41_queue_alloc(u8 type, u8 q_mgr, u16 *q_num)
+ + {
+ + 	int res = -ENOSPC;
+ + 
+ + 	if (q_mgr >= cppi41_num_queue_mgr)
+ + 		return -EINVAL;
+ + 
+ + 	/* Mask out the unsupported queue types */
+ + 	type &= cppi41_queue_mgr[q_mgr].queue_types;
+ + 	/* First see if a free descriptor queue was requested... */
+ + 	if (type & CPPI41_FREE_DESC_QUEUE)
+ + 		res = alloc_queue(allocated_queues[q_mgr], NULL,
+ + 				  cppi41_queue_mgr[q_mgr].base_fdq_num,  16);
+ + 
+ + 	/* Then see if a free descriptor/buffer queue was requested... */
+ + 	if (res < 0 && (type & CPPI41_FREE_DESC_BUF_QUEUE))
+ + 		res = alloc_queue(allocated_queues[q_mgr], NULL,
+ + 				  cppi41_queue_mgr[q_mgr].base_fdbq_num, 16);
+ + 
+ + 	/* Last see if an unassigned queue was requested... */
+ + 	if (res < 0 && (type & CPPI41_UNASSIGNED_QUEUE))
+ + 		res = alloc_queue(allocated_queues[q_mgr],
+ + 				  cppi41_queue_mgr[q_mgr].assigned, 0,
+ + 				  cppi41_queue_mgr[q_mgr].num_queue);
+ + 
+ + 	/* See if any queue was allocated... */
+ + 	if (res < 0)
+ + 		return res;
+ + 
+ + 	/* Return the queue allocated */
+ + 	*q_num = res;
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(cppi41_queue_alloc);
+ + 
+ + /*
+ +  * cppi41_queue_free - free the given queue in the queue manager
+ +  */
+ + int cppi41_queue_free(u8 q_mgr, u16 q_num)
+ + {
+ + 	int index = q_num >> 5, bit = 1 << (q_num & 0x1f);
+ + 
+ + 	if (allocated_queues[q_mgr] != NULL) {
+ + 		if (q_mgr >= cppi41_num_queue_mgr ||
+ + 		    q_num >= cppi41_queue_mgr[q_mgr].num_queue ||
+ + 		    !(allocated_queues[q_mgr][index] & bit))
+ + 			return -EINVAL;
+ + 		allocated_queues[q_mgr][index] &= ~bit;
+ + 	}
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(cppi41_queue_free);
+ + 
+ + /*
+ +  * cppi41_queue_init - initialize a CPPI 4.1 queue object
+ +  */
+ + int cppi41_queue_init(struct cppi41_queue_obj *queue_obj, u8 q_mgr, u16 q_num)
+ + {
+ + 	if (q_mgr >= cppi41_num_queue_mgr ||
+ + 	    q_num >= cppi41_queue_mgr[q_mgr].num_queue)
+ + 		return -EINVAL;
+ + 
+ + 	queue_obj->base_addr = cppi41_queue_mgr[q_mgr].q_mgmt_rgn_base +
+ + 			       QMGR_QUEUE_STATUS_REG_A(q_num);
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(cppi41_queue_init);
+ + 
+ + /*
+ +  * cppi41_queue_push - push a descriptor into the given queue
+ +  */
+ + void cppi41_queue_push(const struct cppi41_queue_obj *queue_obj, u32 desc_addr,
+ + 		       u32 desc_size, u32 pkt_size)
+ + {
+ + 	u32 val;
+ + 
+ + 	/*
+ + 	 * Write to the tail of the queue.
+ + 	 * TODO: Can't think of a reason why a queue to head may be required.
+ + 	 * If it is, the API may have to be extended.
+ + 	 */
+ + #if 0
+ + 	/*
+ + 	 * Also, can't understand why packet size is required to queue up a
+ + 	 * descriptor. The spec says packet size *must* be written prior to
+ + 	 * the packet write operation.
+ + 	 */
+ + 	if (pkt_size)
+ + 		val = (pkt_size << QMGR_QUEUE_PKT_SIZE_SHIFT) &
+ + 		      QMGR_QUEUE_PKT_SIZE_MASK;
+ + 	cppi_writel(val, queue_obj->base_addr + QMGR_QUEUE_REG_C(0));
+ + #endif
+ + 
+ + 	val = (((desc_size - 24) >> (2 - QMGR_QUEUE_DESC_SIZE_SHIFT)) &
+ + 	       QMGR_QUEUE_DESC_SIZE_MASK) |
+ + 	      (desc_addr & QMGR_QUEUE_DESC_PTR_MASK);
+ + 
+ + 	DBG("Pushing value %x to queue @ %p\n", val, queue_obj->base_addr);
+ + 
+ + 	cppi_writel(val, queue_obj->base_addr + QMGR_QUEUE_REG_D(0));
+ + }
+ + EXPORT_SYMBOL(cppi41_queue_push);
+ + 
+ + /*
+ +  * cppi41_queue_pop - pop a descriptor from a given queue
+ +  */
+ + unsigned long cppi41_queue_pop(const struct cppi41_queue_obj *queue_obj)
+ + {
+ + 	u32 val = cppi_readl(queue_obj->base_addr + QMGR_QUEUE_REG_D(0));
+ + 
+ + 	DBG("Popping value %x from queue @ %p\n", val, queue_obj->base_addr);
+ + 
+ + 	return val & QMGR_QUEUE_DESC_PTR_MASK;
+ + }
+ + EXPORT_SYMBOL(cppi41_queue_pop);
+ + 
+ + /*
+ +  * cppi41_get_teardown_info - extract information from a teardown descriptor
+ +  */
+ + int cppi41_get_teardown_info(unsigned long addr, u32 *info)
+ + {
+ + 	struct cppi41_teardown_desc *desc;
+ + 	int dma_num;
+ + 
+ + 	for (dma_num = 0; dma_num < cppi41_num_dma_block; dma_num++)
+ + 		if (addr >= dma_teardown[dma_num].phys_addr &&
+ + 		    addr <  dma_teardown[dma_num].phys_addr +
+ + 			    dma_teardown[dma_num].rgn_size)
+ + 			break;
+ + 
+ + 	if (dma_num == cppi41_num_dma_block)
+ + 		return -EINVAL;
+ + 
+ + 	desc = addr - dma_teardown[dma_num].phys_addr +
+ + 	       dma_teardown[dma_num].virt_addr;
+ + 
+ + 	if ((desc->teardown_info & CPPI41_DESC_TYPE_MASK) !=
+ + 	    (CPPI41_DESC_TYPE_TEARDOWN << CPPI41_DESC_TYPE_SHIFT))
+ + 		return -EINVAL;
+ + 
+ + 	*info = desc->teardown_info;
+ + #if 1
+ + 	/* Hardware is not giving the current DMA number as of now. :-/ */
+ + 	*info |= (dma_num << CPPI41_TEARDOWN_DMA_NUM_SHIFT) &
+ + 		 CPPI41_TEARDOWN_DMA_NUM_MASK;
+ + #else
+ + 	dma_num = (desc->teardown_info & CPPI41_TEARDOWN_DMA_NUM_MASK) >>
+ + 		 CPPI41_TEARDOWN_DMA_NUM_SHIFT;
+ + #endif
+ + 
+ + 	cppi41_queue_push(&dma_teardown[dma_num].queue_obj, addr,
+ + 			  sizeof(struct cppi41_teardown_desc), 0);
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(cppi41_get_teardown_info);
+ + 
+ + /*
+ +  * cppi41_save_context - save regsiter context before going to suspend.
+ +  */
+ + void cppi41_save_context(u8 dma_num)
+ + {
+ + 	const struct cppi41_dma_block *dma_block;
+ + 	struct cppi41_dma_regs *cppi41;
+ + 	struct cppi41_queue_manager *qmgr;
+ + 	void __iomem *q_mgr_regs, *desc_mem_regs;
+ + 	u8 i, q_mgr = 0;
+ + 
+ + 	dma_block = (struct cppi41_dma_block *)&cppi41_dma_block[dma_num];
+ + 	cppi41 = (struct cppi41_dma_regs *)&dma_block->cppi41_regs;
+ + 	qmgr = &cppi41->qmgr;
+ + 	q_mgr_regs = cppi41_queue_mgr[q_mgr].q_mgr_rgn_base;
+ + 	desc_mem_regs = cppi41_queue_mgr[q_mgr].desc_mem_rgn_base;
+ + 
+ + 	/* popout all teardown descriptors */
+ + 	cppi41_free_teardown_queue(dma_num);
+ + 
+ + 	cppi41->teardn_fdq_ctrl = cppi_readl(dma_block->global_ctrl_base +
+ + 			DMA_TEARDOWN_FREE_DESC_CTRL_REG);
+ + 	cppi41->emulation_ctrl = cppi_readl(dma_block->global_ctrl_base +
+ + 			DMA_EMULATION_CTRL_REG);
+ + 
+ + 	qmgr->link_ram_rgn0_base = cppi_readl(q_mgr_regs +
+ + 				QMGR_LINKING_RAM_RGN0_BASE_REG);
+ + 	qmgr->link_ram_rgn0_size = cppi_readl(q_mgr_regs +
+ + 				QMGR_LINKING_RAM_RGN0_SIZE_REG);
+ + 	qmgr->link_ram_rgn1_base = cppi_readl(q_mgr_regs +
+ + 				QMGR_LINKING_RAM_RGN1_BASE_REG);
+ + 
+ + 	for (i = 0 ; i < 8 ; i++) {
+ + 		qmgr->memr_base[i] = cppi_readl(desc_mem_regs +
+ + 				QMGR_MEM_RGN_BASE_REG(i));
+ + 		qmgr->memr_ctrl[i] = cppi_readl(desc_mem_regs +
+ + 				QMGR_MEM_RGN_CTRL_REG(i));
+ + 	}
+ + 
+ + 	cppi41->sched_ctrl = cppi_readl(dma_block->sched_ctrl_base +
+ + 				DMA_SCHED_CTRL_REG);
+ + 
+ + }
+ + EXPORT_SYMBOL(cppi41_save_context);
+ + 
+ + /*
+ +  * cppi41_restore_context - restore regsiter context after resume.
+ +  */
+ + void cppi41_restore_context(u8 dma_num, u32 *sched_tbl)
+ + {
+ + 	const struct cppi41_dma_block *dma_block;
+ + 	struct cppi41_dma_regs *cppi41;
+ + 	struct cppi41_queue_manager *qmgr;
+ + 	void __iomem *q_mgr_regs, *desc_mem_regs;
+ + 	unsigned num_reg;
+ + 	u32 val;
+ + 	u8 tbl_size;
+ + 	u8 i, q_mgr = 0;
+ + 
+ + 	dma_block = (struct cppi41_dma_block *)&cppi41_dma_block[dma_num];
+ + 	cppi41 = (struct cppi41_dma_regs *)&dma_block->cppi41_regs;
+ + 	qmgr = &cppi41->qmgr;
+ + 	q_mgr_regs = cppi41_queue_mgr[q_mgr].q_mgr_rgn_base;
+ + 	desc_mem_regs = cppi41_queue_mgr[q_mgr].desc_mem_rgn_base;
+ + 	tbl_size = dma_block->num_max_ch;
+ + 
+ + 	cppi_writel(cppi41->teardn_fdq_ctrl, dma_block->global_ctrl_base +
+ + 			DMA_TEARDOWN_FREE_DESC_CTRL_REG);
+ + 	cppi_writel(cppi41->emulation_ctrl, dma_block->global_ctrl_base +
+ + 			DMA_EMULATION_CTRL_REG);
+ + 
+ + 	cppi_writel(qmgr->link_ram_rgn0_base, q_mgr_regs +
+ + 				QMGR_LINKING_RAM_RGN0_BASE_REG);
+ + 	cppi_writel(qmgr->link_ram_rgn0_size, q_mgr_regs +
+ + 				QMGR_LINKING_RAM_RGN0_SIZE_REG);
+ + 	cppi_writel(qmgr->link_ram_rgn1_base, q_mgr_regs +
+ + 				QMGR_LINKING_RAM_RGN1_BASE_REG);
+ + 
+ + 	for (i = 0 ; i < 8 ; i++) {
+ + 		cppi_writel(qmgr->memr_base[i], desc_mem_regs +
+ + 				QMGR_MEM_RGN_BASE_REG(i));
+ + 		cppi_writel(qmgr->memr_ctrl[i], desc_mem_regs +
+ + 				QMGR_MEM_RGN_CTRL_REG(i));
+ + 	}
+ + 
+ + 	/*
+ + 	 * Push all teardown descriptors to the free teardown queue
+ + 	 * for the CPPI 4.1 system.
+ + 	 */
+ + 	cppi41_init_teardown_queue(dma_num);
+ + 
+ + 	/* Initialize the DMA scheduler. */
+ + 	num_reg = (tbl_size + 3) / 4;
+ + 	for (i = 0; i < num_reg; i++) {
+ + 		val = sched_tbl[i];
+ + 		cppi_writel(val, dma_block->sched_table_base +
+ + 			     DMA_SCHED_TABLE_WORD_REG(i));
+ + 	}
+ + 	cppi_writel(cppi41->sched_ctrl, dma_block->sched_ctrl_base +
+ + 				DMA_SCHED_CTRL_REG);
+ + }
+ + EXPORT_SYMBOL(cppi41_restore_context);
+ + 
+ + MODULE_DESCRIPTION("TI CPPI 4.1 support");
+ + MODULE_AUTHOR("MontaVista Software");
+ + MODULE_LICENSE("GPL");
+ diff -crN linux-3.2.1_o/drivers/usb/musb/cppi41_dma.c linux-3.2.1/drivers/usb/musb/cppi41_dma.c
+ *** linux-3.2.1_o/drivers/usb/musb/cppi41_dma.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/drivers/usb/musb/cppi41_dma.c	2014-11-25 13:19:16.563673216 +0900
+ ***************
+ *** 0 ****
+ --- 1,1855 ----
+ + /*
+ +  * Copyright (C) 2005-2006 by Texas Instruments
+ +  * Copyright (c) 2008, MontaVista Software, Inc. <source@mvista.com>
+ +  *
+ +  * This file implements a DMA interface using TI's CPPI 4.1 DMA.
+ +  *
+ +  * This program is free software; you can distribute it and/or modify it
+ +  * under the terms of the GNU General Public License (Version 2) as
+ +  * published by the Free Software Foundation.
+ +  *
+ +  * This program is distributed in the hope it will be useful, but WITHOUT
+ +  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ +  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ +  * for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License along
+ +  * with this program; if not, write to the Free Software Foundation, Inc.,
+ +  * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ +  *
+ +  */
+ + 
+ + #include <linux/errno.h>
+ + #include <linux/dma-mapping.h>
+ + #include <linux/module.h>
+ + 
+ + #include "cppi41.h"
+ + 
+ + #include "musb_core.h"
+ + #include "musb_dma.h"
+ + #include "cppi41_dma.h"
+ + 
+ + /* Configuration */
+ + #define USB_CPPI41_DESC_SIZE_SHIFT 6
+ + #define USB_CPPI41_DESC_ALIGN	(1 << USB_CPPI41_DESC_SIZE_SHIFT)
+ + #define USB_CPPI41_CH_NUM_PD	128	/* 4K bulk data at full speed */
+ + #define USB_CPPI41_MAX_PD	(USB_CPPI41_CH_NUM_PD * (USB_CPPI41_NUM_CH+1))
+ + 
+ + #undef DEBUG_CPPI_TD
+ + #undef USBDRV_DEBUG
+ + 
+ + #ifdef USBDRV_DEBUG
+ + #define dprintk(x, ...) printk(x, ## __VA_ARGS__)
+ + #else
+ + #define dprintk(x, ...)
+ + #endif
+ + 
+ + /*
+ +  * Data structure definitions
+ +  */
+ + 
+ + /*
+ +  * USB Packet Descriptor
+ +  */
+ + struct usb_pkt_desc;
+ + 
+ + struct usb_pkt_desc {
+ + 	/* Hardware descriptor fields from this point */
+ + 	struct cppi41_host_pkt_desc hw_desc;	/* 40 bytes */
+ + 	/* Protocol specific data */
+ + 	dma_addr_t dma_addr;			/* offs:44 byte */
+ + 	struct usb_pkt_desc *next_pd_ptr;	/* offs:48 byte*/
+ + 	u8 ch_num;
+ + 	u8 ep_num;
+ + 	u8 eop;
+ + 	u8 res1;				/* offs:52 */
+ + 	u8 res2[12];				/* offs:64 */
+ + };
+ + 
+ + /**
+ +  * struct cppi41_channel - DMA Channel Control Structure
+ +  *
+ +  * Using the same for Tx/Rx.
+ +  */
+ + struct cppi41_channel {
+ + 	struct dma_channel channel;
+ + 
+ + 	struct cppi41_dma_ch_obj dma_ch_obj; /* DMA channel object */
+ + 	struct cppi41_queue src_queue;	/* Tx queue or Rx free descriptor/ */
+ + 					/* buffer queue */
+ + 	struct cppi41_queue_obj queue_obj; /* Tx queue object or Rx free */
+ + 					/* descriptor/buffer queue object */
+ + 
+ + 	u32 tag_info;			/* Tx PD Tag Information field */
+ + 
+ + 	/* Which direction of which endpoint? */
+ + 	struct musb_hw_ep *end_pt;
+ + 	u8 transmit;
+ + 	u8 ch_num;			/* Channel number of Tx/Rx 0..3 */
+ + 
+ + 	/* DMA mode: "transparent", RNDIS, CDC, or Generic RNDIS */
+ + 	u8 dma_mode;
+ + 	u8 autoreq;
+ + 
+ + 	/* Book keeping for the current transfer request */
+ + 	dma_addr_t start_addr;
+ + 	u32 length;
+ + 	u32 curr_offset;
+ + 	u16 pkt_size;
+ + 	u8  transfer_mode;
+ + 	u8  zlp_queued;
+ + 	u8  inf_mode;
+ + 	u8  tx_complete;
+ + 	u8  rx_complete;
+ + 	u8  hb_mult;
+ + 	u8  txf_complete;
+ + 	u8  txfifo_intr_enable;
+ + 	u8  count;
+ + 	struct usb_pkt_desc *curr_pd;
+ + };
+ + 
+ + /**
+ +  * struct cppi41 - CPPI 4.1 DMA Controller Object
+ +  *
+ +  * Encapsulates all book keeping and data structures pertaining to
+ +  * the CPPI 1.4 DMA controller.
+ +  */
+ + struct cppi41 {
+ + 	struct dma_controller controller;
+ + 	struct musb *musb;
+ + 
+ + 	struct cppi41_channel tx_cppi_ch[USB_CPPI41_NUM_CH];
+ + 	struct cppi41_channel rx_cppi_ch[USB_CPPI41_NUM_CH];
+ + 	struct work_struct      txdma_work;
+ + 	struct work_struct      rxdma_work;
+ + 
+ + 	struct usb_pkt_desc *pd_pool_head; /* Free PD pool head */
+ + 	dma_addr_t pd_mem_phys;		/* PD memory physical address */
+ + 	void *pd_mem;			/* PD memory pointer */
+ + 	u8 pd_mem_rgn;			/* PD memory region number */
+ + 
+ + 	u16 teardownQNum;		/* Teardown completion queue number */
+ + 	struct cppi41_queue_obj queue_obj; /* Teardown completion queue */
+ + 					/* object */
+ + 	u32 pkt_info;			/* Tx PD Packet Information field */
+ + 	struct usb_cppi41_info *cppi_info; /* cppi channel information */
+ + 	u8 en_bd_intr;			/* enable bd interrupt */
+ + 	u32 automode_reg_offs;		/* USB_AUTOREQ_REG offset */
+ + 	u32 teardown_reg_offs;		/* USB_TEARDOWN_REG offset */
+ + 	u32 bd_size;
+ + 	u8  inf_mode;
+ + 	u8  txfifo_intr_enable;		/* txfifo empty interrupt logic */
+ + };
+ + 
+ + struct usb_cppi41_info usb_cppi41_info[2];
+ + EXPORT_SYMBOL(usb_cppi41_info);
+ + static void rxdma_completion_work(struct work_struct *data);
+ + 
+ + #ifdef DEBUG_CPPI_TD
+ + static void print_pd_list(struct usb_pkt_desc *pd_pool_head)
+ + {
+ + 	struct usb_pkt_desc *curr_pd = pd_pool_head;
+ + 	int cnt = 0;
+ + 
+ + 	while (curr_pd != NULL) {
+ + 		if (cnt % 8 == 0)
+ + 			dprintk("\n%02x ", cnt);
+ + 		cnt++;
+ + 		dprintk(" %p", curr_pd);
+ + 		curr_pd = curr_pd->next_pd_ptr;
+ + 	}
+ + 	dprintk("\n");
+ + }
+ + #endif
+ + 
+ + static struct usb_pkt_desc *usb_get_free_pd(struct cppi41 *cppi)
+ + {
+ + 	struct usb_pkt_desc *free_pd = cppi->pd_pool_head;
+ + 
+ + 	if (free_pd != NULL) {
+ + 		cppi->pd_pool_head = free_pd->next_pd_ptr;
+ + 		free_pd->next_pd_ptr = NULL;
+ + 	}
+ + 	return free_pd;
+ + }
+ + 
+ + static void usb_put_free_pd(struct cppi41 *cppi, struct usb_pkt_desc *free_pd)
+ + {
+ + 	free_pd->next_pd_ptr = cppi->pd_pool_head;
+ + 	cppi->pd_pool_head = free_pd;
+ + }
+ + 
+ + /**
+ +  * cppi41_controller_start - start DMA controller
+ +  * @controller: the controller
+ +  *
+ +  * This function initializes the CPPI 4.1 Tx/Rx channels.
+ +  */
+ + static int __devinit cppi41_controller_start(struct dma_controller *controller)
+ + {
+ + 	struct cppi41 *cppi;
+ + 	struct cppi41_channel *cppi_ch;
+ + 	void __iomem *reg_base;
+ + 	struct usb_pkt_desc *curr_pd;
+ + 	unsigned long pd_addr;
+ + 	int i;
+ + 	struct usb_cppi41_info *cppi_info;
+ + 	struct musb *musb;
+ + 
+ + 	cppi = container_of(controller, struct cppi41, controller);
+ + 	cppi_info = cppi->cppi_info;
+ + 	musb = cppi->musb;
+ + 
+ + 	if (cpu_is_ti816x() || cpu_is_am33xx()) {
+ + 		cppi->automode_reg_offs = TI81XX_USB_AUTOREQ_REG;
+ + 		cppi->teardown_reg_offs = TI81XX_USB_TEARDOWN_REG;
+ + 	} else {
+ + 		cppi->automode_reg_offs = USB_AUTOREQ_REG;
+ + 		cppi->teardown_reg_offs = USB_TEARDOWN_REG;
+ + 	}
+ + 
+ + 	/*
+ + 	 * TODO: We may need to check USB_CPPI41_MAX_PD here since CPPI 4.1
+ + 	 * requires the descriptor count to be a multiple of 2 ^ 5 (i.e. 32).
+ + 	 * Similarly, the descriptor size should also be a multiple of 32.
+ + 	 */
+ + 
+ + 	/*
+ + 	 * Allocate free packet descriptor pool for all Tx/Rx endpoints --
+ + 	 * dma_alloc_coherent()  will return a page aligned address, so our
+ + 	 * alignment requirement will be honored.
+ + 	 */
+ + 	cppi->bd_size = USB_CPPI41_MAX_PD * sizeof(struct usb_pkt_desc);
+ + 	cppi->pd_mem = dma_alloc_coherent(cppi->musb->controller,
+ + 					  cppi->bd_size,
+ + 					  &cppi->pd_mem_phys,
+ + 					  GFP_KERNEL | GFP_DMA);
+ + 	if (cppi->pd_mem == NULL) {
+ + 		dev_dbg(musb->controller, "ERROR: packet descriptor memory allocation failed\n");
+ + 		return 0;
+ + 	}
+ + 
+ + 	if (cppi41_mem_rgn_alloc(cppi_info->q_mgr, cppi->pd_mem_phys,
+ + 				 USB_CPPI41_DESC_SIZE_SHIFT,
+ + 				 get_count_order(USB_CPPI41_MAX_PD),
+ + 				 &cppi->pd_mem_rgn)) {
+ + 		dev_dbg(musb->controller, "ERROR: queue manager memory region allocation "
+ + 		    "failed\n");
+ + 		goto free_pds;
+ + 	}
+ + 
+ + 	/* Allocate the teardown completion queue */
+ + 	if (cppi41_queue_alloc(CPPI41_UNASSIGNED_QUEUE,
+ + 			       0, &cppi->teardownQNum)) {
+ + 		dev_dbg(musb->controller, "ERROR: teardown completion queue allocation failed\n");
+ + 		goto free_mem_rgn;
+ + 	}
+ + 	dev_dbg(musb->controller, "Allocated teardown completion queue %d in queue manager 0\n",
+ + 	    cppi->teardownQNum);
+ + 
+ + 	if (cppi41_queue_init(&cppi->queue_obj, 0, cppi->teardownQNum)) {
+ + 		dev_dbg(musb->controller, "ERROR: teardown completion queue initialization "
+ + 		    "failed\n");
+ + 		goto free_queue;
+ + 	}
+ + 
+ + 	/*
+ + 	 * "Slice" PDs one-by-one from the big chunk and
+ + 	 * add them to the free pool.
+ + 	 */
+ + 	curr_pd = (struct usb_pkt_desc *)cppi->pd_mem;
+ + 	pd_addr = cppi->pd_mem_phys;
+ + 	for (i = 0; i < USB_CPPI41_MAX_PD; i++) {
+ + 		curr_pd->dma_addr = pd_addr;
+ + 
+ + 		usb_put_free_pd(cppi, curr_pd);
+ + 		curr_pd = (struct usb_pkt_desc *)((char *)curr_pd +
+ + 						  USB_CPPI41_DESC_ALIGN);
+ + 		pd_addr += USB_CPPI41_DESC_ALIGN;
+ + 	}
+ + 
+ + 	/* Configure the Tx channels */
+ + 	for (i = 0, cppi_ch = cppi->tx_cppi_ch;
+ + 	     i < ARRAY_SIZE(cppi->tx_cppi_ch); ++i, ++cppi_ch) {
+ + 		const struct cppi41_tx_ch *tx_info;
+ + 
+ + 		memset(cppi_ch, 0, sizeof(struct cppi41_channel));
+ + 		cppi_ch->transmit = 1;
+ + 		cppi_ch->ch_num = i;
+ + 		cppi_ch->channel.private_data = cppi;
+ + 
+ + 		/*
+ + 		 * Extract the CPPI 4.1 DMA Tx channel configuration and
+ + 		 * construct/store the Tx PD tag info field for later use...
+ + 		 */
+ + 		tx_info = cppi41_dma_block[cppi_info->dma_block].tx_ch_info
+ + 			  + cppi_info->ep_dma_ch[i];
+ + 		cppi_ch->src_queue = tx_info->tx_queue[0];
+ + 		cppi_ch->tag_info = (tx_info->port_num <<
+ + 				     CPPI41_SRC_TAG_PORT_NUM_SHIFT) |
+ + 				    (tx_info->ch_num <<
+ + 				     CPPI41_SRC_TAG_CH_NUM_SHIFT) |
+ + 				    (tx_info->sub_ch_num <<
+ + 				     CPPI41_SRC_TAG_SUB_CH_NUM_SHIFT);
+ + 	}
+ + 
+ + 	/* Configure the Rx channels */
+ + 	for (i = 0, cppi_ch = cppi->rx_cppi_ch;
+ + 	     i < ARRAY_SIZE(cppi->rx_cppi_ch); ++i, ++cppi_ch) {
+ + 		memset(cppi_ch, 0, sizeof(struct cppi41_channel));
+ + 		cppi_ch->ch_num = i;
+ + 		cppi_ch->channel.private_data = cppi;
+ + 	}
+ + 
+ + 	/* Construct/store Tx PD packet info field for later use */
+ + 	cppi->pkt_info = (CPPI41_PKT_TYPE_USB << CPPI41_PKT_TYPE_SHIFT) |
+ + 			 (CPPI41_RETURN_LINKED << CPPI41_RETURN_POLICY_SHIFT);
+ + 
+ + 	/* Do necessary configuartion in hardware to get started */
+ + 	reg_base = cppi->musb->ctrl_base;
+ + 
+ + 	/* Disable auto request mode */
+ + 	musb_writel(reg_base, cppi->automode_reg_offs, 0);
+ + 
+ + 	/* Disable the CDC/RNDIS modes */
+ + 	musb_writel(reg_base, USB_TX_MODE_REG, 0);
+ + 	musb_writel(reg_base, USB_RX_MODE_REG, 0);
+ + 
+ + 	return 1;
+ + 
+ +  free_queue:
+ + 	if (cppi41_queue_free(0, cppi->teardownQNum))
+ + 		dev_dbg(musb->controller, "ERROR: failed to free teardown completion queue\n");
+ + 
+ +  free_mem_rgn:
+ + 	if (cppi41_mem_rgn_free(cppi_info->q_mgr, cppi->pd_mem_rgn))
+ + 		dev_dbg(musb->controller, "ERROR: failed to free queue manager memory region\n");
+ + 
+ +  free_pds:
+ + 	dma_free_coherent(cppi->musb->controller,
+ + 			  cppi->bd_size,
+ + 			  cppi->pd_mem, cppi->pd_mem_phys);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /**
+ +  * cppi41_controller_stop - stop DMA controller
+ +  * @controller: the controller
+ +  *
+ +  * De-initialize the DMA Controller as necessary.
+ +  */
+ + static int cppi41_controller_stop(struct dma_controller *controller)
+ + {
+ + 	struct cppi41 *cppi;
+ + 	void __iomem *reg_base;
+ + 	struct usb_cppi41_info *cppi_info;
+ + 	struct musb *musb;
+ + 
+ + 	cppi = container_of(controller, struct cppi41, controller);
+ + 	cppi_info = cppi->cppi_info;
+ + 	musb = cppi->musb;
+ + 
+ + 	/* Free the teardown completion queue */
+ + 	if (cppi41_queue_free(cppi_info->q_mgr, cppi->teardownQNum))
+ + 		dev_dbg(musb->controller, "ERROR: failed to free teardown completion queue\n");
+ + 
+ + 	/*
+ + 	 * Free the packet descriptor region allocated
+ + 	 * for all Tx/Rx channels.
+ + 	 */
+ + 	if (cppi41_mem_rgn_free(cppi_info->q_mgr, cppi->pd_mem_rgn))
+ + 		dev_dbg(musb->controller, "ERROR: failed to free queue manager memory region\n");
+ + 
+ + 	dma_free_coherent(cppi->musb->controller, cppi->bd_size,
+ + 			  cppi->pd_mem, cppi->pd_mem_phys);
+ + 
+ + 	cppi->pd_mem = 0;
+ + 	cppi->pd_mem_phys = 0;
+ + 	cppi->pd_pool_head = 0;
+ + 	cppi->bd_size = 0;
+ + 
+ + 	reg_base = cppi->musb->ctrl_base;
+ + 
+ + 	/* Disable auto request mode */
+ + 	musb_writel(reg_base, cppi->automode_reg_offs, 0);
+ + 
+ + 	/* Disable the CDC/RNDIS modes */
+ + 	musb_writel(reg_base, USB_TX_MODE_REG, 0);
+ + 	musb_writel(reg_base, USB_RX_MODE_REG, 0);
+ + 
+ + 	return 1;
+ + }
+ + 
+ + /**
+ +  * cppi41_channel_alloc - allocate a CPPI channel for DMA.
+ +  * @controller: the controller
+ +  * @ep:		the endpoint
+ +  * @is_tx:	1 for Tx channel, 0 for Rx channel
+ +  *
+ +  * With CPPI, channels are bound to each transfer direction of a non-control
+ +  * endpoint, so allocating (and deallocating) is mostly a way to notice bad
+ +  * housekeeping on the software side.  We assume the IRQs are always active.
+ +  */
+ + static struct dma_channel *cppi41_channel_alloc(struct dma_controller
+ + 						*controller,
+ + 						struct musb_hw_ep *ep, u8 is_tx)
+ + {
+ + 	struct cppi41 *cppi;
+ + 	struct cppi41_channel  *cppi_ch;
+ + 	u32 ch_num, ep_num = ep->epnum;
+ + 	struct usb_cppi41_info *cppi_info;
+ + 	struct musb *musb;
+ + 
+ + 	cppi = container_of(controller, struct cppi41, controller);
+ + 	cppi_info = cppi->cppi_info;
+ + 	musb = cppi->musb;
+ + 
+ + 	/* Remember, ep_num: 1 .. Max_EP, and CPPI ch_num: 0 .. Max_EP - 1 */
+ + 	ch_num = ep_num - 1;
+ + 
+ + 	if (ep_num > USB_CPPI41_NUM_CH) {
+ + 		dev_dbg(musb->controller, "No %cx DMA channel for EP%d\n",
+ + 		    is_tx ? 'T' : 'R', ep_num);
+ + 		return NULL;
+ + 	}
+ + 
+ + 	cppi_ch = (is_tx ? cppi->tx_cppi_ch : cppi->rx_cppi_ch) + ch_num;
+ + 
+ + 	/* As of now, just return the corresponding CPPI 4.1 channel handle */
+ + 	if (is_tx) {
+ + 		/* Initialize the CPPI 4.1 Tx DMA channel */
+ + 		if (cppi41_tx_ch_init(&cppi_ch->dma_ch_obj,
+ + 				      cppi_info->dma_block,
+ + 				      cppi_info->ep_dma_ch[ch_num])) {
+ + 			dev_dbg(musb->controller, "ERROR: cppi41_tx_ch_init failed for "
+ + 			    "channel %d\n", ch_num);
+ + 			return NULL;
+ + 		}
+ + 		/*
+ + 		 * Teardown descriptors will be pushed to the dedicated
+ + 		 * completion queue.
+ + 		 */
+ + 		cppi41_dma_ch_default_queue(&cppi_ch->dma_ch_obj,
+ + 					    0, cppi->teardownQNum);
+ + 	} else {
+ + 		struct cppi41_rx_ch_cfg rx_cfg;
+ + 		u8 q_mgr = cppi_info->q_mgr;
+ + 		int i;
+ + 
+ + 		/* Initialize the CPPI 4.1 Rx DMA channel */
+ + 		if (cppi41_rx_ch_init(&cppi_ch->dma_ch_obj,
+ + 				      cppi_info->dma_block,
+ + 				      cppi_info->ep_dma_ch[ch_num])) {
+ + 			dev_dbg(musb->controller, "ERROR: cppi41_rx_ch_init failed\n");
+ + 			return NULL;
+ + 		}
+ + 
+ + 		if (cppi41_queue_alloc(CPPI41_FREE_DESC_BUF_QUEUE |
+ + 				       CPPI41_UNASSIGNED_QUEUE,
+ + 				       q_mgr, &cppi_ch->src_queue.q_num)) {
+ + 			dev_dbg(musb->controller, "ERROR: cppi41_queue_alloc failed for "
+ + 			    "free descriptor/buffer queue\n");
+ + 			return NULL;
+ + 		}
+ + 		dev_dbg(musb->controller, "Allocated free descriptor/buffer queue %d in "
+ + 		    "queue manager %d\n", cppi_ch->src_queue.q_num, q_mgr);
+ + 
+ + 		rx_cfg.default_desc_type = cppi41_rx_host_desc;
+ + 		rx_cfg.sop_offset = 0;
+ + 		rx_cfg.retry_starved = 1;
+ + 		rx_cfg.rx_max_buf_cnt = 0;
+ + 		rx_cfg.rx_queue.q_mgr = cppi_ch->src_queue.q_mgr = q_mgr;
+ + 		rx_cfg.rx_queue.q_num = cppi_info->rx_comp_q[ch_num];
+ + 		for (i = 0; i < 4; i++)
+ + 			rx_cfg.cfg.host_pkt.fdb_queue[i] = cppi_ch->src_queue;
+ + 		cppi41_rx_ch_configure(&cppi_ch->dma_ch_obj, &rx_cfg);
+ + 	}
+ + 
+ + 	/* Initialize the CPPI 4.1 DMA source queue */
+ + 	if (cppi41_queue_init(&cppi_ch->queue_obj, cppi_ch->src_queue.q_mgr,
+ + 			       cppi_ch->src_queue.q_num)) {
+ + 		dev_dbg(musb->controller, "ERROR: cppi41_queue_init failed for %s queue",
+ + 		    is_tx ? "Tx" : "Rx free descriptor/buffer");
+ + 		if (is_tx == 0 &&
+ + 		    cppi41_queue_free(cppi_ch->src_queue.q_mgr,
+ + 				      cppi_ch->src_queue.q_num))
+ + 			dev_dbg(musb->controller, "ERROR: failed to free Rx descriptor/buffer "
+ + 			    "queue\n");
+ + 		 return NULL;
+ + 	}
+ + 
+ + 	/* Enable the DMA channel */
+ + 	cppi41_dma_ch_enable(&cppi_ch->dma_ch_obj);
+ + 
+ + 	if (cppi_ch->end_pt)
+ + 		dev_dbg(musb->controller, "Re-allocating DMA %cx channel %d (%p)\n",
+ + 		    is_tx ? 'T' : 'R', ch_num, cppi_ch);
+ + 
+ + 	cppi_ch->end_pt = ep;
+ + 	cppi_ch->ch_num = ch_num;
+ + 	cppi_ch->channel.status = MUSB_DMA_STATUS_FREE;
+ + 	cppi_ch->channel.max_len = is_tx ?
+ + 				CPPI41_TXDMA_MAXLEN : CPPI41_RXDMA_MAXLEN;
+ + 
+ + 	dev_dbg(musb->controller, "Allocated DMA %cx channel %d for EP%d\n", is_tx ? 'T' : 'R',
+ + 	    ch_num, ep_num);
+ + 
+ + 	return &cppi_ch->channel;
+ + }
+ + 
+ + /**
+ +  * cppi41_channel_release - release a CPPI DMA channel
+ +  * @channel: the channel
+ +  */
+ + static void cppi41_channel_release(struct dma_channel *channel)
+ + {
+ + 	struct cppi41_channel *cppi_ch;
+ + 
+ + 	/* REVISIT: for paranoia, check state and abort if needed... */
+ + 	cppi_ch = container_of(channel, struct cppi41_channel, channel);
+ + 
+ + 	if (cppi_ch->end_pt == NULL)
+ + 		printk(KERN_INFO "Releasing idle DMA channel %p\n", cppi_ch);
+ + 
+ + 	/* But for now, not its IRQ */
+ + 	cppi_ch->end_pt = NULL;
+ + 	channel->status = MUSB_DMA_STATUS_UNKNOWN;
+ + 
+ + 	cppi41_dma_ch_disable(&cppi_ch->dma_ch_obj);
+ + 
+ + 	/* De-allocate Rx free descriptior/buffer queue */
+ + 	if (cppi_ch->transmit == 0 &&
+ + 	    cppi41_queue_free(cppi_ch->src_queue.q_mgr,
+ + 			      cppi_ch->src_queue.q_num))
+ + 		printk(KERN_ERR "ERROR: failed to free Rx descriptor/buffer queue\n");
+ + }
+ + 
+ + static void cppi41_mode_update(struct cppi41_channel *cppi_ch, u8 mode)
+ + {
+ + 	if (mode != cppi_ch->dma_mode) {
+ + 		struct cppi41 *cppi = cppi_ch->channel.private_data;
+ + 		void *__iomem reg_base = cppi->musb->ctrl_base;
+ + 		u32 reg_val;
+ + 		u8 ep_num = cppi_ch->ch_num + 1;
+ + 
+ + 		if (cppi_ch->transmit) {
+ + 			reg_val = musb_readl(reg_base, USB_TX_MODE_REG);
+ + 			reg_val &= ~USB_TX_MODE_MASK(ep_num);
+ + 			reg_val |= mode << USB_TX_MODE_SHIFT(ep_num);
+ + 			musb_writel(reg_base, USB_TX_MODE_REG, reg_val);
+ + 		} else {
+ + 			reg_val = musb_readl(reg_base, USB_RX_MODE_REG);
+ + 			reg_val &= ~USB_RX_MODE_MASK(ep_num);
+ + 			reg_val |= mode << USB_RX_MODE_SHIFT(ep_num);
+ + 			musb_writel(reg_base, USB_RX_MODE_REG, reg_val);
+ + 		}
+ + 		cppi_ch->dma_mode = mode;
+ + 	}
+ + }
+ + 
+ + /*
+ +  * CPPI 4.1 Tx:
+ +  * ============
+ +  * Tx is a lot more reasonable than Rx: RNDIS mode seems to behave well except
+ +  * how it handles the exactly-N-packets case. It appears that there's a hiccup
+ +  * in that case (maybe the DMA completes before a ZLP gets written?) boiling
+ +  * down to not being able to rely on the XFER DMA writing any terminating zero
+ +  * length packet before the next transfer is started...
+ +  *
+ +  * The generic RNDIS mode does not have this misfeature, so we prefer using it
+ +  * instead.  We then send the terminating ZLP *explictly* using DMA instead of
+ +  * doing it by PIO after an IRQ.
+ +  *
+ +  */
+ + 
+ + /**
+ +  * cppi41_next_tx_segment - DMA write for the next chunk of a buffer
+ +  * @tx_ch:	Tx channel
+ +  *
+ +  * Context: controller IRQ-locked
+ +  */
+ + static unsigned cppi41_next_tx_segment(struct cppi41_channel *tx_ch)
+ + {
+ + 	struct cppi41 *cppi = tx_ch->channel.private_data;
+ + 	struct musb *musb = cppi->musb;
+ + 	struct usb_pkt_desc *curr_pd;
+ + 	u32 length = tx_ch->length - tx_ch->curr_offset;
+ + 	u32 pkt_size = tx_ch->pkt_size;
+ + 	unsigned num_pds, n;
+ + 	struct usb_cppi41_info *cppi_info = cppi->cppi_info;
+ + 	u16 q_mgr = cppi_info->q_mgr;
+ + 	u16 tx_comp_q = cppi_info->tx_comp_q[tx_ch->ch_num];
+ + 	u8 en_bd_intr = cppi->en_bd_intr;
+ + 	u8 is_isoc = 0;
+ + 	struct musb_hw_ep *hw_ep = cppi->musb->endpoints + tx_ch->end_pt->epnum;
+ + 	int xfer_type = hw_ep->xfer_type;
+ + 
+ + 	/*
+ + 	 * Tx can use the generic RNDIS mode where we can probably fit this
+ + 	 * transfer in one PD and one IRQ.  The only time we would NOT want
+ + 	 * to use it is when the hardware constraints prevent it...
+ + 	 */
+ + 	if ((pkt_size & 0x3f) == 0) {
+ + 		num_pds  = length ? 1 : 0;
+ + 		cppi41_mode_update(tx_ch, USB_GENERIC_RNDIS_MODE);
+ + 	} else {
+ + 		num_pds  = (length + pkt_size - 1) / pkt_size;
+ + 		cppi41_mode_update(tx_ch, USB_TRANSPARENT_MODE);
+ + 	}
+ + 
+ + 	pkt_size = length;
+ + 	/*
+ + 	 * If length of transmit buffer is 0 or a multiple of the endpoint size,
+ + 	 * then send the zero length packet.
+ + 	 */
+ + 	if (!length || (tx_ch->transfer_mode && length % pkt_size == 0))
+ + 		num_pds++;
+ + 
+ + 	dev_dbg(musb->controller, "TX DMA%u, %s, maxpkt %u, %u PDs, addr %#x, len %u\n",
+ + 	    tx_ch->ch_num, tx_ch->dma_mode ? "accelerated" : "transparent",
+ + 	    pkt_size, num_pds, tx_ch->start_addr + tx_ch->curr_offset, length);
+ + 
+ + 	if (xfer_type  == USB_ENDPOINT_XFER_ISOC)
+ + 		is_isoc = 1;
+ + 
+ + 	if (is_isoc && cppi->txfifo_intr_enable && (length <= tx_ch->pkt_size))
+ + 		tx_ch->txfifo_intr_enable = 1;
+ + 
+ + 	for (n = 0; n < num_pds; n++) {
+ + 		struct cppi41_host_pkt_desc *hw_desc;
+ + 
+ + 		/* Get Tx host packet descriptor from the free pool */
+ + 		curr_pd = usb_get_free_pd(cppi);
+ + 		if (curr_pd == NULL) {
+ + 			dev_dbg(musb->controller, "No Tx PDs\n");
+ + 			break;
+ + 		}
+ + 
+ + 		if (length < pkt_size)
+ + 			pkt_size = length;
+ + 
+ + 		hw_desc = &curr_pd->hw_desc;
+ + 		hw_desc->desc_info = (CPPI41_DESC_TYPE_HOST <<
+ + 				      CPPI41_DESC_TYPE_SHIFT) | pkt_size;
+ + 		hw_desc->tag_info = tx_ch->tag_info;
+ + 		hw_desc->pkt_info = cppi->pkt_info;
+ + 		hw_desc->pkt_info |= ((q_mgr << CPPI41_RETURN_QMGR_SHIFT) |
+ + 				(tx_comp_q << CPPI41_RETURN_QNUM_SHIFT));
+ + 
+ + 		hw_desc->buf_ptr = tx_ch->start_addr + tx_ch->curr_offset;
+ + 		hw_desc->buf_len = pkt_size;
+ + 		hw_desc->next_desc_ptr = 0;
+ + 		hw_desc->orig_buf_len = pkt_size;
+ + 
+ + 		curr_pd->ch_num = tx_ch->ch_num;
+ + 		curr_pd->ep_num = tx_ch->end_pt->epnum;
+ + 
+ + 		tx_ch->curr_offset += pkt_size;
+ + 		length -= pkt_size;
+ + 
+ + 		if (pkt_size == 0)
+ + 			tx_ch->zlp_queued = 1;
+ + 
+ + 		if (en_bd_intr)
+ + 			hw_desc->orig_buf_len |= CPPI41_PKT_INTR_FLAG;
+ + 
+ + 		dev_dbg(musb->controller, "TX PD %p: buf %08x, len %08x, pkt info %08x\n", curr_pd,
+ + 		    hw_desc->buf_ptr, hw_desc->buf_len, hw_desc->pkt_info);
+ + 
+ + 		/* make sure descriptor details are updated to memory*/
+ + 		dsb();
+ + 
+ + 		/* enable tx fifo empty interrupt */
+ + 		if (tx_ch->txfifo_intr_enable) {
+ + 			dev_dbg(musb->controller, "txs(%p %d) enable txFintr\n",
+ + 				curr_pd, hw_desc->orig_buf_len &
+ + 					~CPPI41_PKT_INTR_FLAG);
+ + 			txfifoempty_int_enable(cppi->musb, curr_pd->ep_num);
+ + 		}
+ + 
+ + 		cppi41_queue_push(&tx_ch->queue_obj, curr_pd->dma_addr,
+ + 				  USB_CPPI41_DESC_ALIGN, pkt_size);
+ + 	}
+ + 
+ + 	return n;
+ + }
+ + 
+ + static void cppi41_autoreq_update(struct cppi41_channel *rx_ch, u8 autoreq)
+ + {
+ + 	struct cppi41 *cppi = rx_ch->channel.private_data;
+ + 
+ + 	if (is_host_active(cppi->musb) &&
+ + 	    autoreq != rx_ch->autoreq) {
+ + 		void *__iomem reg_base = cppi->musb->ctrl_base;
+ + 		u32 reg_val = musb_readl(reg_base, cppi->automode_reg_offs);
+ + 		u8 ep_num = rx_ch->ch_num + 1;
+ + 
+ + 		reg_val &= ~USB_RX_AUTOREQ_MASK(ep_num);
+ + 		reg_val |= autoreq << USB_RX_AUTOREQ_SHIFT(ep_num);
+ + 
+ + 		musb_writel(reg_base, cppi->automode_reg_offs, reg_val);
+ + 		rx_ch->autoreq = autoreq;
+ + 	}
+ + }
+ + 
+ + static void cppi41_set_ep_size(struct cppi41_channel *rx_ch, u32 pkt_size)
+ + {
+ + 	struct cppi41 *cppi = rx_ch->channel.private_data;
+ + 	void *__iomem reg_base = cppi->musb->ctrl_base;
+ + 	u8 ep_num = rx_ch->ch_num + 1;
+ + 	u32 res = pkt_size % 64;
+ + 
+ + 	/* epsize register must be multiple of 64 */
+ + 	pkt_size += res ? (64 - res) : res;
+ + 
+ + 	musb_writel(reg_base, USB_GENERIC_RNDIS_EP_SIZE_REG(ep_num), pkt_size);
+ + }
+ + 
+ + /*
+ +  * CPPI 4.1 Rx:
+ +  * ============
+ +  * Consider a 1KB bulk Rx buffer in two scenarios: (a) it's fed two 300 byte
+ +  * packets back-to-back, and (b) it's fed two 512 byte packets back-to-back.
+ +  * (Full speed transfers have similar scenarios.)
+ +  *
+ +  * The correct behavior for Linux is that (a) fills the buffer with 300 bytes,
+ +  * and the next packet goes into a buffer that's queued later; while (b) fills
+ +  * the buffer with 1024 bytes.  How to do that with accelerated DMA modes?
+ +  *
+ +  * Rx queues in RNDIS mode (one single BD) handle (a) correctly but (b) loses
+ +  * BADLY because nothing (!) happens when that second packet fills the buffer,
+ +  * much less when a third one arrives -- which makes it not a "true" RNDIS mode.
+ +  * In the RNDIS protocol short-packet termination is optional, and it's fine if
+ +  * the peripherals (not hosts!) pad the messages out to end of buffer. Standard
+ +  * PCI host controller DMA descriptors implement that mode by default... which
+ +  * is no accident.
+ +  *
+ +  * Generic RNDIS mode is the only way to reliably make both cases work.  This
+ +  * mode is identical to the "normal" RNDIS mode except for the case where the
+ +  * last packet of the segment matches the max USB packet size -- in this case,
+ +  * the packet will be closed when a value (0x10000 max) in the Generic RNDIS
+ +  * EP Size register is reached.  This mode will work for the network drivers
+ +  * (CDC/RNDIS) as well as for the mass storage drivers where there is no short
+ +  * packet.
+ +  *
+ +  * BUT we can only use non-transparent modes when USB packet size is a multiple
+ +  * of 64 bytes. Let's see what happens when  this is not the case...
+ +  *
+ +  * Rx queues (2 BDs with 512 bytes each) have converse problems to RNDIS mode:
+ +  * (b) is handled right but (a) loses badly.  DMA doesn't stop after receiving
+ +  * a short packet and processes both of those PDs; so both packets are loaded
+ +  * into the buffer (with 212 byte gap between them), and the next buffer queued
+ +  * will NOT get its 300 bytes of data.  Even in the case when there should be
+ +  * no short packets (URB_SHORT_NOT_OK is set), queueing several packets in the
+ +  * host mode doesn't win us anything since we have to manually "prod" the Rx
+ +  * process after each packet is received by setting ReqPkt bit in endpoint's
+ +  * RXCSR; in the peripheral mode without short packets, queueing could be used
+ +  * BUT we'll have to *teardown* the channel if a short packet still arrives in
+ +  * the peripheral mode, and to "collect" the left-over packet descriptors from
+ +  * the free descriptor/buffer queue in both cases...
+ +  *
+ +  * One BD at a time is the only way to make make both cases work reliably, with
+ +  * software handling both cases correctly, at the significant penalty of needing
+ +  * an IRQ per packet.  (The lack of I/O overlap can be slightly ameliorated by
+ +  * enabling double buffering.)
+ +  *
+ +  * There seems to be no way to identify for sure the cases where the CDC mode
+ +  * is appropriate...
+ +  *
+ +  */
+ + 
+ + /**
+ +  * cppi41_next_rx_segment - DMA read for the next chunk of a buffer
+ +  * @rx_ch:	Rx channel
+ +  *
+ +  * Context: controller IRQ-locked
+ +  *
+ +  * NOTE: In the transparent mode, we have to queue one packet at a time since:
+ +  *	 - we must avoid starting reception of another packet after receiving
+ +  *	   a short packet;
+ +  *	 - in host mode we have to set ReqPkt bit in the endpoint's RXCSR after
+ +  *	   receiving each packet but the last one... ugly!
+ +  */
+ + static unsigned cppi41_next_rx_segment(struct cppi41_channel *rx_ch)
+ + {
+ + 	struct cppi41 *cppi = rx_ch->channel.private_data;
+ + 	struct musb *musb = cppi->musb;
+ + 	struct usb_pkt_desc *curr_pd;
+ + 	struct cppi41_host_pkt_desc *hw_desc;
+ + 	u32 length = rx_ch->length - rx_ch->curr_offset;
+ + 	u32 pkt_size = rx_ch->pkt_size;
+ + 	u32 max_rx_transfer_size = 64 * 1024;
+ + 	u32 i, n_bd , pkt_len;
+ + 	struct usb_gadget_driver *gadget_driver;
+ + 	u8 en_bd_intr = cppi->en_bd_intr, mode;
+ + 
+ + 	if (is_peripheral_active(cppi->musb)) {
+ + 		/* TODO: temporary fix for CDC/RNDIS which needs to be in
+ + 		 * GENERIC_RNDIS mode. Without this RNDIS gadget taking
+ + 		 * more then 2K ms for a 64 byte pings.
+ + 		 */
+ + 		gadget_driver = cppi->musb->gadget_driver;
+ + 
+ + 		pkt_len = rx_ch->pkt_size;
+ + 		mode = USB_GENERIC_RNDIS_MODE;
+ + 		if (!strcmp(gadget_driver->driver.name, "g_file_storage") ||
+ + 			!strcmp(gadget_driver->driver.name, "g_mass_storage")) {
+ + 			if (cppi->inf_mode && length > pkt_len) {
+ + 				pkt_len = 0;
+ + 				length = length - rx_ch->pkt_size;
+ + 				cppi41_rx_ch_set_maxbufcnt(&rx_ch->dma_ch_obj,
+ + 					DMA_CH_RX_MAX_BUF_CNT_1);
+ + 				rx_ch->inf_mode = 1;
+ + 			} else {
+ + 				max_rx_transfer_size = rx_ch->pkt_size;
+ + 				mode = USB_TRANSPARENT_MODE;
+ + 			}
+ + 		} else
+ + 			if (rx_ch->length < max_rx_transfer_size)
+ + 				pkt_len = rx_ch->length;
+ + 
+ + 		if (mode != USB_TRANSPARENT_MODE)
+ + 			cppi41_set_ep_size(rx_ch, pkt_len);
+ + 		cppi41_mode_update(rx_ch, mode);
+ + 	} else {
+ + 		/*
+ + 		 * Rx can use the generic RNDIS mode where we can
+ + 		 * probably fit this transfer in one PD and one IRQ
+ + 		 * (or two with a short packet).
+ + 		 */
+ + 		if (cppi->cppi_info->grndis_for_host_rx &&
+ + 					(pkt_size & 0x3f) == 0) {
+ + 			cppi41_mode_update(rx_ch, USB_GENERIC_RNDIS_MODE);
+ + 			cppi41_autoreq_update(rx_ch, USB_AUTOREQ_ALL_BUT_EOP);
+ + 
+ + 			pkt_size = (length > 0x10000) ? 0x10000 : length;
+ + 			cppi41_set_ep_size(rx_ch, pkt_size);
+ + 			mode = USB_GENERIC_RNDIS_MODE;
+ + 		} else {
+ + 			cppi41_mode_update(rx_ch, USB_TRANSPARENT_MODE);
+ + 			cppi41_autoreq_update(rx_ch, USB_NO_AUTOREQ);
+ + 			max_rx_transfer_size = rx_ch->hb_mult * rx_ch->pkt_size;
+ + 			mode = USB_TRANSPARENT_MODE;
+ + 		}
+ + 	}
+ + 
+ + 	dev_dbg(musb->controller, "RX DMA%u, %s, maxpkt %u, addr %#x, rec'd %u/%u\n",
+ + 	    rx_ch->ch_num, rx_ch->dma_mode ? "accelerated" : "transparent",
+ + 	    pkt_size, rx_ch->start_addr + rx_ch->curr_offset,
+ + 	    rx_ch->curr_offset, rx_ch->length);
+ + 
+ + 	/* calculate number of bd required */
+ + 	if (is_host_active(cppi->musb) && (mode == USB_TRANSPARENT_MODE))
+ + 		n_bd = 1;
+ + 	else
+ + 		n_bd = (length + max_rx_transfer_size - 1)/max_rx_transfer_size;
+ + 
+ + 	for (i = 0; i < n_bd ; ++i) {
+ + 		/* Get Rx packet descriptor from the free pool */
+ + 		curr_pd = usb_get_free_pd(cppi);
+ + 		if (curr_pd == NULL) {
+ + 			/* Shouldn't ever happen! */
+ + 			dev_dbg(musb->controller, "No Rx PDs\n");
+ + 			goto sched;
+ + 		}
+ + 
+ + 		pkt_len =
+ + 		(length > max_rx_transfer_size) ? max_rx_transfer_size : length;
+ + 
+ + 		hw_desc = &curr_pd->hw_desc;
+ + 		hw_desc->desc_info = (CPPI41_DESC_TYPE_HOST <<
+ + 				      CPPI41_DESC_TYPE_SHIFT);
+ + 		hw_desc->orig_buf_ptr = rx_ch->start_addr + rx_ch->curr_offset;
+ + 		hw_desc->orig_buf_len = pkt_len;
+ + 
+ + 		/* buf_len field of buffer descriptor updated by dma
+ + 		 * after reception of data is completed
+ + 		 */
+ + 		hw_desc->buf_len = 0;
+ + 
+ + 		curr_pd->ch_num = rx_ch->ch_num;
+ + 		curr_pd->ep_num = rx_ch->end_pt->epnum;
+ + 
+ + 		curr_pd->eop = (length -= pkt_len) ? 0 : 1;
+ + 		rx_ch->curr_offset += pkt_len;
+ + 
+ + 		if (en_bd_intr)
+ + 			hw_desc->orig_buf_len |= CPPI41_PKT_INTR_FLAG;
+ + 
+ + 		/* make sure descriptor details are updated to memory*/
+ + 		dsb();
+ + 
+ + 		/*
+ + 		 * Push the free Rx packet descriptor
+ + 		 * to the free descriptor/buffer queue.
+ + 		 */
+ + 		cppi41_queue_push(&rx_ch->queue_obj, curr_pd->dma_addr,
+ + 			USB_CPPI41_DESC_ALIGN, 0);
+ + 	}
+ + 
+ + sched:
+ + 	/*
+ + 	 * HCD arranged ReqPkt for the first packet.
+ + 	 * We arrange it for all but the last one.
+ + 	 */
+ + 	if (is_host_active(cppi->musb) && rx_ch->channel.actual_len) {
+ + 		void __iomem *epio = rx_ch->end_pt->regs;
+ + 		u16 csr = musb_readw(epio, MUSB_RXCSR);
+ + 
+ + 		if (musb->datatog_fix) {
+ + 			u8 curr_toggle;
+ + 			curr_toggle = (csr & MUSB_RXCSR_H_DATATOGGLE) ? 1 : 0;
+ + 
+ + 			/* check if data toggle bit got out of sync */
+ + 			if (curr_toggle == rx_ch->end_pt->prev_toggle) {
+ + 				dev_dbg(musb->controller,
+ + 				"Data toggle same as previous (=%d) on ep%d\n",
+ + 					curr_toggle, rx_ch->end_pt->epnum);
+ + 
+ + 				csr |= MUSB_RXCSR_H_DATATOGGLE |
+ + 					MUSB_RXCSR_H_WR_DATATOGGLE;
+ + 				musb_writew(epio, MUSB_RXCSR, csr);
+ + 
+ + 				rx_ch->end_pt->prev_toggle = !curr_toggle;
+ + 			} else {
+ + 				rx_ch->end_pt->prev_toggle = curr_toggle;
+ + 			}
+ + 			csr = musb_readw(epio, MUSB_RXCSR);
+ + 		}
+ + 
+ + 		csr |= MUSB_RXCSR_H_REQPKT | MUSB_RXCSR_H_WZC_BITS;
+ + 		musb_writew(epio, MUSB_RXCSR, csr);
+ + 	}
+ + 
+ + 	/* enable schedular if not enabled */
+ + 	if (is_peripheral_active(cppi->musb) && (n_bd > 0))
+ + 		cppi41_schedtbl_add_dma_ch(0, 0, rx_ch->ch_num, 0);
+ + 	return 1;
+ + }
+ + 
+ + /**
+ +  * cppi41_channel_program - program channel for data transfer
+ +  * @channel:	the channel
+ +  * @maxpacket:	max packet size
+ +  * @mode:	for Rx, 1 unless the USB protocol driver promised to treat
+ +  *		all short reads as errors and kick in high level fault recovery;
+ +  *		for Tx, 0 unless the protocol driver _requires_ short-packet
+ +  *		termination mode
+ +  * @dma_addr:	DMA address of buffer
+ +  * @length:	length of buffer
+ +  *
+ +  * Context: controller IRQ-locked
+ +  */
+ + static int cppi41_channel_program(struct dma_channel *channel,	u16 maxpacket,
+ + 				  u8 mode, dma_addr_t dma_addr, u32 length)
+ + {
+ + 	struct cppi41_channel *cppi_ch;
+ + 	unsigned queued;
+ + 
+ + 	cppi_ch = container_of(channel, struct cppi41_channel, channel);
+ + 
+ + 	switch (channel->status) {
+ + 	case MUSB_DMA_STATUS_BUS_ABORT:
+ + 	case MUSB_DMA_STATUS_CORE_ABORT:
+ + 		/* Fault IRQ handler should have handled cleanup */
+ + 		WARNING("%cx DMA%d not cleaned up after abort!\n",
+ + 			cppi_ch->transmit ? 'T' : 'R', cppi_ch->ch_num);
+ + 		break;
+ + 	case MUSB_DMA_STATUS_BUSY:
+ + 		WARNING("Program active channel? %cx DMA%d\n",
+ + 			cppi_ch->transmit ? 'T' : 'R', cppi_ch->ch_num);
+ + 		break;
+ + 	case MUSB_DMA_STATUS_UNKNOWN:
+ + 		WARNING("%cx DMA%d not allocated!\n",
+ + 		    cppi_ch->transmit ? 'T' : 'R', cppi_ch->ch_num);
+ + 		return 0;
+ + 	case MUSB_DMA_STATUS_FREE:
+ + 		break;
+ + 	}
+ + 
+ + 	channel->status = MUSB_DMA_STATUS_BUSY;
+ + 
+ + 	/* Set the transfer parameters, then queue up the first segment */
+ + 	cppi_ch->start_addr = dma_addr;
+ + 	cppi_ch->curr_offset = 0;
+ + 	cppi_ch->hb_mult = (maxpacket >> 11) & 0x03;
+ + 	cppi_ch->pkt_size = maxpacket & 0x7ff;
+ + 	cppi_ch->length = length;
+ + 	cppi_ch->transfer_mode = mode;
+ + 	cppi_ch->zlp_queued = 0;
+ + 	cppi_ch->channel.actual_len = 0;
+ + 
+ + 	/* Tx or Rx channel? */
+ + 	if (cppi_ch->transmit)
+ + 		queued = cppi41_next_tx_segment(cppi_ch);
+ + 	else
+ + 		queued = cppi41_next_rx_segment(cppi_ch);
+ + 
+ + 	return	queued > 0;
+ + }
+ + 
+ + static struct usb_pkt_desc *usb_get_pd_ptr(struct cppi41 *cppi,
+ + 					   unsigned long pd_addr)
+ + {
+ + 	if (pd_addr >= cppi->pd_mem_phys && pd_addr < cppi->pd_mem_phys +
+ + 	    USB_CPPI41_MAX_PD * USB_CPPI41_DESC_ALIGN)
+ + 		return pd_addr - cppi->pd_mem_phys + cppi->pd_mem;
+ + 	else
+ + 		return NULL;
+ + }
+ + 
+ + static int usb_check_teardown(struct cppi41_channel *cppi_ch,
+ + 			      unsigned long pd_addr)
+ + {
+ + 	u32 info;
+ + 	struct cppi41 *cppi = cppi_ch->channel.private_data;
+ + 	struct usb_cppi41_info *cppi_info = cppi->cppi_info;
+ + 	struct musb *musb = cppi->musb;
+ + 
+ + 	if (cppi41_get_teardown_info(pd_addr, &info)) {
+ + 		dev_dbg(musb->controller, "ERROR: not a teardown descriptor\n");
+ + 		return 0;
+ + 	}
+ + 
+ + 	if ((info & CPPI41_TEARDOWN_TX_RX_MASK) ==
+ + 	    (!cppi_ch->transmit << CPPI41_TEARDOWN_TX_RX_SHIFT) &&
+ + 	    (info & CPPI41_TEARDOWN_DMA_NUM_MASK) ==
+ + 	    (cppi_info->dma_block << CPPI41_TEARDOWN_DMA_NUM_SHIFT) &&
+ + 	    (info & CPPI41_TEARDOWN_CHAN_NUM_MASK) ==
+ + 	    (cppi_info->ep_dma_ch[cppi_ch->ch_num] <<
+ + 	     CPPI41_TEARDOWN_CHAN_NUM_SHIFT))
+ + 		return 1;
+ + 
+ + 	dev_dbg(musb->controller, "ERROR: unexpected values in teardown descriptor\n");
+ + 	return 0;
+ + }
+ + 
+ + /*
+ +  * We can't handle the channel teardown via the default completion queue in
+ +  * context of the controller IRQ-locked, so we use the dedicated teardown
+ +  * completion queue which we can just poll for a teardown descriptor, not
+ +  * interfering with the Tx completion queue processing.
+ +  */
+ + static void usb_tx_ch_teardown(struct cppi41_channel *tx_ch)
+ + {
+ + 	struct cppi41 *cppi = tx_ch->channel.private_data;
+ + 	struct musb *musb = cppi->musb;
+ + 	void __iomem *reg_base = musb->ctrl_base;
+ + 	u32 td_reg, timeout = 0xfffff;
+ + 	u8 ep_num = tx_ch->ch_num + 1;
+ + 	unsigned long pd_addr;
+ + 	struct cppi41_queue_obj tx_queue_obj;
+ + 	struct usb_cppi41_info *cppi_info;
+ + 
+ + 	/* Initiate teardown for Tx DMA channel */
+ + 	cppi41_dma_ch_teardown(&tx_ch->dma_ch_obj);
+ + 
+ + 	/* Wait for a descriptor to be queued and pop it... */
+ + 	do {
+ + 		td_reg  = musb_readl(reg_base, cppi->teardown_reg_offs);
+ + 		td_reg |= USB_TX_TDOWN_MASK(ep_num);
+ + 		musb_writel(reg_base, cppi->teardown_reg_offs, td_reg);
+ + 
+ + 		pd_addr = cppi41_queue_pop(&cppi->queue_obj);
+ + 	} while (!pd_addr && timeout--);
+ + 
+ + 	if (pd_addr) {
+ + 
+ + 		dev_dbg(musb->controller, "Descriptor (%08lx) popped from teardown completion "
+ + 			"queue\n", pd_addr);
+ + 
+ + 		if (usb_check_teardown(tx_ch, pd_addr)) {
+ + 			dev_dbg(musb->controller, "Teardown Desc (%lx) rcvd\n", pd_addr);
+ + 		} else
+ + 			ERR("Invalid PD(%08lx)popped from TearDn completion"
+ + 				"queue\n", pd_addr);
+ + 	} else {
+ + 		if (timeout <= 0)
+ + 			ERR("Teardown Desc not rcvd\n");
+ + 	}
+ + 
+ + 	/* read the tx completion queue and remove
+ + 	 * completion bd if any
+ + 	 */
+ + 	cppi_info = cppi->cppi_info;
+ + 	if (cppi41_queue_init(&tx_queue_obj, cppi_info->q_mgr,
+ + 			      cppi_info->tx_comp_q[tx_ch->ch_num])) {
+ + 		ERR("ERROR: cppi41_queue_init failed for "
+ + 		    "Tx completion queue");
+ + 		return;
+ + 	}
+ + 
+ + 	while ((pd_addr = cppi41_queue_pop(&tx_queue_obj)) != 0) {
+ + 		struct usb_pkt_desc *curr_pd;
+ + 
+ + 		curr_pd = usb_get_pd_ptr(cppi, pd_addr);
+ + 		if (curr_pd == NULL) {
+ + 			ERR("Invalid PD popped from Tx completion queue\n");
+ + 			continue;
+ + 		}
+ + 
+ + 		dev_dbg(musb->controller, "Tx-PD(%p) popped from completion queue\n", curr_pd);
+ + 		dev_dbg(musb->controller, "ch(%d)epnum(%d)len(%d)\n", curr_pd->ch_num,
+ + 			curr_pd->ep_num, curr_pd->hw_desc.buf_len);
+ + 
+ + 		usb_put_free_pd(cppi, curr_pd);
+ + 	}
+ + }
+ + 
+ + /*
+ +  * For Rx DMA channels, the situation is more complex: there's only a single
+ +  * completion queue for all our needs, so we have to temporarily redirect the
+ +  * completed descriptors to our teardown completion queue, with a possibility
+ +  * of a completed packet landing there as well...
+ +  */
+ + static void usb_rx_ch_teardown(struct cppi41_channel *rx_ch)
+ + {
+ + 	struct cppi41 *cppi = rx_ch->channel.private_data;
+ + 	struct musb *musb = cppi->musb;
+ + 	struct usb_cppi41_info *cppi_info = cppi->cppi_info;
+ + 	u32 timeout = 0xfffff, pd_addr;
+ + 	struct cppi41_queue_obj rx_queue_obj;
+ + 
+ + 	cppi41_dma_ch_default_queue(&rx_ch->dma_ch_obj, 0, cppi->teardownQNum);
+ + 
+ + 	/* Initiate teardown for Rx DMA channel */
+ + 	cppi41_dma_ch_teardown(&rx_ch->dma_ch_obj);
+ + 
+ + 	do {
+ + 		struct usb_pkt_desc *curr_pd;
+ + 		unsigned long pd_addr;
+ + 
+ + 		/* Wait for a descriptor to be queued and pop it... */
+ + 		do {
+ + 			pd_addr = cppi41_queue_pop(&cppi->queue_obj);
+ + 		} while (!pd_addr && timeout--);
+ + 
+ + 		if (timeout <= 0 || !pd_addr) {
+ + 			ERR("teardown Desc not found\n");
+ + 			break;
+ + 		}
+ + 
+ + 		dev_dbg(musb->controller, "Descriptor (%08lx) popped from teardown completion "
+ + 			"queue\n", pd_addr);
+ + 
+ + 		/*
+ + 		 * We might have popped a completed Rx PD, so check if the
+ + 		 * physical address is within the PD region first.  If it's
+ + 		 * not the case, it must be a teardown descriptor...
+ + 		 * */
+ + 		curr_pd = usb_get_pd_ptr(cppi, pd_addr);
+ + 		if (curr_pd == NULL) {
+ + 			if (usb_check_teardown(rx_ch, pd_addr))
+ + 				break;
+ + 			continue;
+ + 		}
+ + 
+ + 		/* Paranoia: check if PD is from the right channel... */
+ + 		if (curr_pd->ch_num != rx_ch->ch_num) {
+ + 			ERR("Unexpected channel %d in Rx PD\n",
+ + 			    curr_pd->ch_num);
+ + 			continue;
+ + 		}
+ + 
+ + 		/* Extract the buffer length from the completed PD */
+ + 		rx_ch->channel.actual_len += curr_pd->hw_desc.buf_len;
+ + 
+ + 		/*
+ + 		 * Return Rx PDs to the software list --
+ + 		 * this is protected by critical section.
+ + 		 */
+ + 		usb_put_free_pd(cppi, curr_pd);
+ + 	} while (0);
+ + 
+ + 	/* read the rx completion queue and remove
+ + 	 * completion bd if any
+ + 	 */
+ + 	if (cppi41_queue_init(&rx_queue_obj, cppi_info->q_mgr,
+ + 			      cppi_info->rx_comp_q[rx_ch->ch_num])) {
+ + 		ERR("ERROR: cppi41_queue_init failed for "
+ + 		    "Rx completion queue");
+ + 		return;
+ + 	}
+ + 
+ + 	while ((pd_addr = cppi41_queue_pop(&rx_queue_obj)) != 0) {
+ + 		struct usb_pkt_desc *curr_pd;
+ + 
+ + 		curr_pd = usb_get_pd_ptr(cppi, pd_addr);
+ + 		if (curr_pd == NULL) {
+ + 			ERR("Invalid PD popped from Rx completion queue\n");
+ + 			continue;
+ + 		}
+ + 
+ + 		dev_dbg(musb->controller, "Rx-PD(%p) popped from completion queue\n", curr_pd);
+ + 		dev_dbg(musb->controller, "ch(%d)epnum(%d)len(%d)\n", curr_pd->ch_num,
+ + 			curr_pd->ep_num, curr_pd->hw_desc.buf_len);
+ + 
+ + 		usb_put_free_pd(cppi, curr_pd);
+ + 	}
+ + 
+ + 	/* Now restore the default Rx completion queue... */
+ + 	cppi41_dma_ch_default_queue(&rx_ch->dma_ch_obj, cppi_info->q_mgr,
+ + 				    cppi_info->rx_comp_q[rx_ch->ch_num]);
+ + }
+ + 
+ + /*
+ +  * cppi41_channel_abort
+ +  *
+ +  * Context: controller IRQ-locked, endpoint selected.
+ +  */
+ + static int cppi41_channel_abort(struct dma_channel *channel)
+ + {
+ + 	struct cppi41 *cppi;
+ + 	struct cppi41_channel *cppi_ch;
+ + 	struct musb  *musb;
+ + 	void __iomem *reg_base, *epio;
+ + 	unsigned long pd_addr;
+ + 	u32 csr, td_reg;
+ + 	u8 ch_num, ep_num, i;
+ + 
+ + 	cppi_ch = container_of(channel, struct cppi41_channel, channel);
+ + 	ch_num = cppi_ch->ch_num;
+ + 	cppi = cppi_ch->channel.private_data;
+ + 	musb = cppi->musb;
+ + 
+ + 	switch (channel->status) {
+ + 	case MUSB_DMA_STATUS_BUS_ABORT:
+ + 	case MUSB_DMA_STATUS_CORE_ABORT:
+ + 		/* From Rx or Tx fault IRQ handler */
+ + 	case MUSB_DMA_STATUS_BUSY:
+ + 		/* The hardware needs shutting down... */
+ + 		dprintk("%s: DMA busy, status = %x\n",
+ + 			__func__, channel->status);
+ + 		break;
+ + 	case MUSB_DMA_STATUS_UNKNOWN:
+ + 		dev_dbg(musb->controller, "%cx DMA%d not allocated\n",
+ + 		    cppi_ch->transmit ? 'T' : 'R', ch_num);
+ + 		/* FALLTHROUGH */
+ + 	case MUSB_DMA_STATUS_FREE:
+ + 		return 0;
+ + 	}
+ + 
+ + 	reg_base = musb->ctrl_base;
+ + 	epio = cppi_ch->end_pt->regs;
+ + 	ep_num = ch_num + 1;
+ + 
+ + #ifdef DEBUG_CPPI_TD
+ + 	printk("Before teardown:");
+ + 	print_pd_list(cppi->pd_pool_head);
+ + #endif
+ + 
+ + 	if (cppi_ch->transmit) {
+ + 		dprintk("Tx channel teardown, cppi_ch = %p\n", cppi_ch);
+ + 
+ + 		/* disable the DMAreq before teardown */
+ + 		csr  = musb_readw(epio, MUSB_TXCSR);
+ + 		csr &= ~MUSB_TXCSR_DMAENAB;
+ + 		musb_writew(epio, MUSB_TXCSR, csr);
+ + 
+ + 		cppi_ch->tx_complete = 0;
+ + 		cppi_ch->txf_complete = 0;
+ + 		/* Tear down Tx DMA channel */
+ + 		usb_tx_ch_teardown(cppi_ch);
+ + 
+ + 		/* Issue CPPI FIFO teardown for Tx channel */
+ + 		td_reg  = musb_readl(reg_base, cppi->teardown_reg_offs);
+ + 		td_reg |= USB_TX_TDOWN_MASK(ep_num);
+ + 		musb_writel(reg_base, cppi->teardown_reg_offs, td_reg);
+ + 
+ + 		/* Flush FIFO of the endpoint */
+ + 		for (i = 0; i < 2; ++i) {
+ + 			csr  = musb_readw(epio, MUSB_TXCSR);
+ + 			if (csr & MUSB_TXCSR_TXPKTRDY) {
+ + 				csr |= MUSB_TXCSR_FLUSHFIFO |
+ + 					MUSB_TXCSR_H_WZC_BITS;
+ + 				musb_writew(epio, MUSB_TXCSR, csr);
+ + 			}
+ + 		}
+ + 	} else { /* Rx */
+ + 		dprintk("Rx channel teardown, cppi_ch = %p\n", cppi_ch);
+ + 
+ + 		/* For host, ensure ReqPkt is never set again */
+ + 		cppi41_autoreq_update(cppi_ch, USB_NO_AUTOREQ);
+ + 
+ + 		/* disable the DMAreq and remove reqpkt */
+ + 		csr  = musb_readw(epio, MUSB_RXCSR);
+ + 		dev_dbg(musb->controller,
+ + 			"before rx-teardown: rxcsr %x rxcount %x\n", csr,
+ + 			musb_readw(epio, MUSB_RXCOUNT));
+ + 		/* 250usec delay to drain to cppi dma
+ + 		 * pipe line */
+ + 		udelay(250);
+ + 
+ + 		/* For host, clear (just) ReqPkt at end of current packet(s) */
+ + 		if (is_host_active(cppi->musb))
+ + 			csr &= ~MUSB_RXCSR_H_REQPKT;
+ + 
+ + 		csr &= ~MUSB_RXCSR_DMAENAB;
+ + 		musb_writew(epio, MUSB_RXCSR, csr);
+ + 		/* wait till xdma completes last 64 bytes transfer from
+ + 		 * mentor fifo to internal cppi fifo and drain
+ + 		 * cppi dma pipe line
+ + 		 */
+ + 		udelay(250);
+ + 
+ + 		/* Flush FIFO of the endpoint */
+ + 		csr  = musb_readw(epio, MUSB_RXCSR);
+ + 
+ + 		if (csr & MUSB_RXCSR_RXPKTRDY)
+ + 			csr |= MUSB_RXCSR_FLUSHFIFO;
+ + 
+ + 		csr |= MUSB_RXCSR_H_WZC_BITS;
+ + 		musb_writew(epio, MUSB_RXCSR, csr);
+ + 		musb_writew(epio, MUSB_RXCSR, csr);
+ + 		csr  = musb_readw(epio, MUSB_RXCSR);
+ + 
+ + 		/* Issue CPPI FIFO teardown for Rx channel */
+ + 		td_reg  = musb_readl(reg_base, cppi->teardown_reg_offs);
+ + 		td_reg |= USB_RX_TDOWN_MASK(ep_num);
+ + 		musb_writel(reg_base, cppi->teardown_reg_offs, td_reg);
+ + 
+ + 		/* Tear down Rx DMA channel */
+ + 		usb_rx_ch_teardown(cppi_ch);
+ + 
+ + 		/*
+ + 		 * NOTE: docs don't guarantee any of this works...  we expect
+ + 		 * that if the USB core stops telling the CPPI core to pull
+ + 		 * more data from it, then it'll be safe to flush current Rx
+ + 		 * DMA state iff any pending FIFO transfer is done.
+ + 		 */
+ + 
+ + 		/* For host, ensure ReqPkt is never set again */
+ + 		cppi41_autoreq_update(cppi_ch, USB_NO_AUTOREQ);
+ + 	}
+ + 
+ + 	/*
+ + 	 * There might be PDs in the Rx/Tx source queue that were not consumed
+ + 	 * by the DMA controller -- they need to be recycled properly.
+ + 	 */
+ + 	while ((pd_addr = cppi41_queue_pop(&cppi_ch->queue_obj)) != 0) {
+ + 		struct usb_pkt_desc *curr_pd;
+ + 
+ + 		curr_pd = usb_get_pd_ptr(cppi, pd_addr);
+ + 		if (curr_pd == NULL) {
+ + 			ERR("Invalid PD popped from source queue\n");
+ + 			continue;
+ + 		}
+ + 
+ + 		/*
+ + 		 * Return Rx/Tx PDs to the software list --
+ + 		 * this is protected by critical section.
+ + 		 */
+ + 		dprintk("Returning PD %p to the free PD list\n", curr_pd);
+ + 		usb_put_free_pd(cppi, curr_pd);
+ + 	}
+ + 
+ + #ifdef DEBUG_CPPI_TD
+ + 	printk("After teardown:");
+ + 	print_pd_list(cppi->pd_pool_head);
+ + #endif
+ + 
+ + 	/* Re-enable the DMA channel */
+ + 	cppi41_dma_ch_enable(&cppi_ch->dma_ch_obj);
+ + 
+ + 	channel->status = MUSB_DMA_STATUS_FREE;
+ + 
+ + 	return 0;
+ + }
+ + 
+ + void txdma_completion_work(struct work_struct *data)
+ + {
+ + 	struct cppi41 *cppi = container_of(data, struct cppi41, txdma_work);
+ + 	struct cppi41_channel *tx_ch;
+ + 	struct musb *musb = cppi->musb;
+ + 	unsigned index;
+ + 	u8 resched = 0;
+ + 	unsigned long flags;
+ + 
+ + 	while (1) {
+ + 		for (index = 0; index < USB_CPPI41_NUM_CH; index++) {
+ + 			void __iomem *epio;
+ + 			u16 csr;
+ + 
+ + 			tx_ch = &cppi->tx_cppi_ch[index];
+ + 			if (tx_ch->tx_complete) {
+ + 				/* Sometimes a EP can unregister from a DMA
+ + 				 * channel while the data is still in the FIFO.
+ + 				 * Probable reason a proper abort was not
+ + 				 * called before taking such a step.
+ + 				 * Protect against such cases.
+ + 				 */
+ + 				if (!tx_ch->end_pt) {
+ + 					tx_ch->tx_complete = 0;
+ + 					tx_ch->count = 0;
+ + 					continue;
+ + 				}
+ + 
+ + 				epio = tx_ch->end_pt->regs;
+ + 				csr = musb_readw(epio, MUSB_TXCSR);
+ + 
+ + 				if (!tx_ch->txfifo_intr_enable &&
+ + 					(csr & (MUSB_TXCSR_TXPKTRDY |
+ + 					MUSB_TXCSR_FIFONOTEMPTY))) {
+ + 					resched = 1;
+ + 				} else {
+ + 					if (tx_ch->count > 0) {
+ + 						tx_ch->count--;
+ + 						resched = 1;
+ + 						continue;
+ + 					}
+ + 					tx_ch->channel.status =
+ + 						MUSB_DMA_STATUS_FREE;
+ + 					tx_ch->tx_complete = 0;
+ + 					spin_lock_irqsave(&musb->lock, flags);
+ + 					musb_dma_completion(musb, index+1, 1);
+ + 					spin_unlock_irqrestore(&musb->lock,
+ + 						flags);
+ + 				}
+ + 			}
+ + 
+ + 			if (!resched)
+ + 				cond_resched();
+ + 		}
+ + 
+ + 		if (resched) {
+ + 			resched = 0;
+ + 			cond_resched();
+ + 		} else {
+ + 			return ;
+ + 		}
+ + 	}
+ + 
+ + }
+ + 
+ + void cppi41_handle_txfifo_intr(struct musb *musb, u16 usbintr)
+ + {
+ + 	struct cppi41 *cppi;
+ + 	struct cppi41_channel *tx_ch;
+ + 	int index;
+ + 
+ + 	cppi = container_of(musb->dma_controller, struct cppi41, controller);
+ + 	for (index = 0; (index < USB_CPPI41_NUM_CH) && usbintr; index++) {
+ + 		if (usbintr & 1) {
+ + 			tx_ch = &cppi->tx_cppi_ch[index];
+ + 			if (tx_ch->txf_complete) {
+ + 				/* disable txfifo empty interupt */
+ + 				txfifoempty_int_disable(musb, index+1);
+ + 				tx_ch->txf_complete = 0;
+ + 				if (!tx_ch->txfifo_intr_enable)
+ + 					dev_dbg(musb->controller,
+ + 					"Bug, wrong TxFintr ep%d\n", index+1);
+ + 				tx_ch->txfifo_intr_enable = 0;
+ + 
+ + 				tx_ch->channel.status =
+ + 					MUSB_DMA_STATUS_FREE;
+ + 
+ + 				dev_dbg(musb->controller,
+ + 					"txc: givback ep%d\n", index+1);
+ + 				musb_dma_completion(musb, index+1, 1);
+ + 			}
+ + 		}
+ + 		usbintr = usbintr >> 1;
+ + 	}
+ + }
+ + EXPORT_SYMBOL(cppi41_handle_txfifo_intr);
+ + 
+ + /**
+ +  * cppi41_dma_controller_create -
+ +  * instantiate an object representing DMA controller.
+ +  */
+ + struct dma_controller * __devinit
+ + cppi41_dma_controller_create(struct musb  *musb, void __iomem *mregs)
+ + {
+ + 	struct cppi41 *cppi;
+ + 
+ + 	cppi = kzalloc(sizeof *cppi, GFP_KERNEL);
+ + 	if (!cppi)
+ + 		return NULL;
+ + 
+ + 	/* Initialize the CPPI 4.1 DMA controller structure */
+ + 	cppi->musb  = musb;
+ + 	cppi->controller.start = cppi41_controller_start;
+ + 	cppi->controller.stop  = cppi41_controller_stop;
+ + 	cppi->controller.channel_alloc = cppi41_channel_alloc;
+ + 	cppi->controller.channel_release = cppi41_channel_release;
+ + 	cppi->controller.channel_program = cppi41_channel_program;
+ + 	cppi->controller.channel_abort = cppi41_channel_abort;
+ + 	cppi->cppi_info = (struct usb_cppi41_info *)&usb_cppi41_info[musb->id];;
+ + 	cppi->en_bd_intr = cppi->cppi_info->bd_intr_ctrl;
+ + 	cppi->txfifo_intr_enable = musb->txfifo_intr_enable;
+ + 	INIT_WORK(&cppi->txdma_work, txdma_completion_work);
+ + 	INIT_WORK(&cppi->rxdma_work, rxdma_completion_work);
+ + 
+ + 	/*
+ + 	 * Extra IN token has been seen when a file is transferred from one MSC
+ + 	 * device to other due to xDMA IP bug when multiple masters access
+ + 	 * mentor controller register space.
+ + 	 * As a software workaround use transparent mode and correct data toggle
+ + 	 * when they go wrong.
+ + 	 * This issue is expected to be fixed in RTL version post 0xD.
+ + 	 * Since RTL version is not available to distinguish the fix, based on
+ + 	 * soc revision the rxdma generic rndis shall be enabled/disabled by
+ + 	 * platform driver as mentioned below
+ + 	 * set cppi_info->grndis_for_host_rx = 1 to enable
+ + 	 *			rxdma generic rndis mode
+ + 	 * set cppi_info->grndis_for_host_rx = 0 and
+ + 	 *	cppi->musb->datatog_fix = 0 to disable the rxdma generic rndis.
+ + 	 */
+ + 	if (cppi->cppi_info->grndis_for_host_rx)
+ + 		cppi->musb->datatog_fix = 0;
+ + 	else
+ + 		cppi->musb->datatog_fix = 1;
+ + 	dev_dbg(musb->controller, "musb%d: %s cppi41 rxdma grndis-mode\n",
+ + 		musb->id, cppi->cppi_info->grndis_for_host_rx ? "enable" :
+ + 			"disable");
+ + 
+ + 	/* enable infinite mode only for ti81xx silicon rev2 */
+ + 	if (cpu_is_am33xx() || cpu_is_ti816x()) {
+ + 		dev_dbg(musb->controller, "cppi41dma supports infinite mode\n");
+ + 		cppi->inf_mode = 1;
+ + 	}
+ + 
+ + 	return &cppi->controller;
+ + }
+ + EXPORT_SYMBOL(cppi41_dma_controller_create);
+ + 
+ + /**
+ +  * cppi41_dma_controller_destroy -
+ +  * destroy a previously instantiated DMA controller
+ +  * @controller: the controller
+ +  */
+ + void cppi41_dma_controller_destroy(struct dma_controller *controller)
+ + {
+ + 	struct cppi41 *cppi;
+ + 
+ + 	cppi = container_of(controller, struct cppi41, controller);
+ + 
+ + 	/* Free the CPPI object */
+ + 	kfree(cppi);
+ + }
+ + EXPORT_SYMBOL(cppi41_dma_controller_destroy);
+ + 
+ + static void usb_process_tx_queue(struct cppi41 *cppi, unsigned index)
+ + {
+ + 	struct cppi41_queue_obj tx_queue_obj;
+ + 	unsigned long pd_addr;
+ + 	struct usb_cppi41_info *cppi_info = cppi->cppi_info;
+ + 	struct musb *musb = cppi->musb;
+ + 
+ + 	if (cppi41_queue_init(&tx_queue_obj, cppi_info->q_mgr,
+ + 			      cppi_info->tx_comp_q[index])) {
+ + 		dev_dbg(musb->controller, "ERROR: cppi41_queue_init failed for "
+ + 		    "Tx completion queue");
+ + 		return;
+ + 	}
+ + 
+ + 	while ((pd_addr = cppi41_queue_pop(&tx_queue_obj)) != 0) {
+ + 		struct usb_pkt_desc *curr_pd;
+ + 		struct cppi41_channel *tx_ch;
+ + 		u8 ch_num, ep_num;
+ + 		u32 length;
+ + 
+ + 		curr_pd = usb_get_pd_ptr(cppi, pd_addr);
+ + 		if (curr_pd == NULL) {
+ + 			ERR("Invalid PD popped from Tx completion queue\n");
+ + 			continue;
+ + 		}
+ + 
+ + 		/* Extract the data from received packet descriptor */
+ + 		ch_num = curr_pd->ch_num;
+ + 		ep_num = curr_pd->ep_num;
+ + 		length = curr_pd->hw_desc.buf_len;
+ + 
+ + 		tx_ch = &cppi->tx_cppi_ch[ch_num];
+ + 		tx_ch->channel.actual_len += length;
+ + 
+ + 		/*
+ + 		 * Return Tx PD to the software list --
+ + 		 * this is protected by critical section
+ + 		 */
+ + 		usb_put_free_pd(cppi, curr_pd);
+ + 
+ + 		if ((tx_ch->curr_offset < tx_ch->length) ||
+ + 		    (tx_ch->transfer_mode && !tx_ch->zlp_queued))
+ + 			cppi41_next_tx_segment(tx_ch);
+ + 		else if (tx_ch->channel.actual_len >= tx_ch->length) {
+ + 			void __iomem *epio;
+ + 			u16 csr;
+ + 
+ + 			/*
+ + 			 * We get Tx DMA completion interrupt even when
+ + 			 * data is still in FIFO and not moved out to
+ + 			 * USB bus. As we program the next request we
+ + 			 * flush out and old data in FIFO which affects
+ + 			 * USB functionality. So far, we have obsered
+ + 			 * failure with iperf.
+ + 			 */
+ + 			/* wait for tx fifo empty completion interrupt
+ + 			 * if enabled other wise use the workthread
+ + 			 * to poll fifo empty status
+ + 			 */
+ + 			epio = tx_ch->end_pt->regs;
+ + 			csr = musb_readw(epio, MUSB_TXCSR);
+ + 
+ + 			if (tx_ch->txfifo_intr_enable) {
+ + 				tx_ch->txf_complete = 1;
+ + 				dev_dbg(musb->controller,
+ + 				"wait for TxF-EmptyIntr ep%d\n", ep_num);
+ + 			} else {
+ + 				int residue;
+ + 
+ + 				residue = tx_ch->channel.actual_len %
+ + 						tx_ch->pkt_size;
+ + 
+ + 				if (tx_ch->pkt_size > 128 && !residue) {
+ + 					tx_ch->channel.status =
+ + 						MUSB_DMA_STATUS_FREE;
+ + 					musb_dma_completion(cppi->musb,
+ + 						ep_num, 1);
+ + 				} else {
+ + 					tx_ch->tx_complete = 1;
+ + 					tx_ch->count = 1;
+ + 					schedule_work(&cppi->txdma_work);
+ + 				}
+ + 			}
+ + 		}
+ + 	}
+ + }
+ + 
+ + static void usb_process_rx_bd(struct cppi41 *cppi,
+ + 		struct usb_pkt_desc *curr_pd)
+ + {
+ + 	u8 en_bd_intr = cppi->en_bd_intr;
+ + 	struct cppi41_channel *rx_ch;
+ + 	u8 ch_num, ep_num;
+ + 	struct musb *musb = cppi->musb;
+ + 	u32 length = 0, orig_buf_len;
+ + 
+ + 	/* Extract the data from received packet descriptor */
+ + 	length = curr_pd->hw_desc.desc_info & CPPI41_PKT_LEN_MASK;
+ + 	ch_num = curr_pd->ch_num;
+ + 	ep_num = curr_pd->ep_num;
+ + 
+ + 	/* the cppi41 dma will set received byte length as 1 when
+ + 	 * zero length packet is received, fix this dummy byte by
+ + 	 * setting acutal length received as zero
+ + 	 */
+ + 	if (curr_pd->hw_desc.pkt_info & CPPI41_ZLP)
+ + 		length = 0;
+ + 
+ + 	rx_ch = &cppi->rx_cppi_ch[ch_num];
+ + 	dev_dbg(musb->controller, "Rx complete: dma channel(%d) ep%d len %d\n",
+ + 		ch_num, ep_num, length);
+ + 
+ + 	rx_ch->channel.actual_len += length;
+ + 
+ + 	if (curr_pd->eop) {
+ + 		curr_pd->eop = 0;
+ + 		/* disable the rx dma schedular */
+ + 		if (is_peripheral_active(cppi->musb) && !cppi->inf_mode)
+ + 			cppi41_schedtbl_remove_dma_ch(0, 0, ch_num, 0);
+ + 	}
+ + 
+ + 	/*
+ + 	 * Return Rx PD to the software list --
+ + 	 * this is protected by critical section
+ + 	 */
+ + 	usb_put_free_pd(cppi, curr_pd);
+ + 
+ + 	orig_buf_len = curr_pd->hw_desc.orig_buf_len;
+ + 	if (en_bd_intr)
+ + 		orig_buf_len &= ~CPPI41_PKT_INTR_FLAG;
+ + 
+ + 	dev_dbg(musb->controller,
+ + 		"curr_pd=%p, len=%d, origlen=%d,rxch(alen/len)=%d/%d\n",
+ + 			curr_pd, length, orig_buf_len,
+ + 			rx_ch->channel.actual_len, rx_ch->length);
+ + 
+ + 	if (unlikely(rx_ch->channel.actual_len >= rx_ch->length ||
+ + 		     length < orig_buf_len)) {
+ + 
+ + #if defined(CONFIG_SOC_OMAPTI81XX) || defined(CONFIG_SOC_OMAPAM33XX)
+ + 		struct musb_hw_ep *ep;
+ + 		u8 isoc, next_seg = 0;
+ + 
+ + 		/* Workaround for early rx completion of
+ + 		 * cppi41 dma in Generic RNDIS mode for ti81xx
+ + 		 */
+ + 		if (is_host_enabled(cppi->musb)) {
+ + 			u32 pkt_size = rx_ch->pkt_size;
+ + 			ep = cppi->musb->endpoints + ep_num;
+ + 			isoc = musb_readb(ep->regs, MUSB_RXTYPE);
+ + 			isoc = (isoc >> 4) & 0x1;
+ + 
+ + 			if (!isoc
+ + 				&& (rx_ch->dma_mode == USB_GENERIC_RNDIS_MODE)
+ + 				&& (rx_ch->channel.actual_len < rx_ch->length)
+ + 				&& !(rx_ch->channel.actual_len % pkt_size))
+ + 					next_seg = 1;
+ + 		}
+ + 		if (next_seg) {
+ + 			rx_ch->curr_offset = rx_ch->channel.actual_len;
+ + 			cppi41_next_rx_segment(rx_ch);
+ + 		} else
+ + #endif
+ + 		{
+ + 			rx_ch->channel.status = MUSB_DMA_STATUS_FREE;
+ + 
+ + 			if (rx_ch->inf_mode) {
+ + 				cppi41_rx_ch_set_maxbufcnt(
+ + 				&rx_ch->dma_ch_obj, 0);
+ + 				rx_ch->inf_mode = 0;
+ + 			}
+ + 
+ + 			/* Rx completion routine callback */
+ + 			musb_dma_completion(cppi->musb, ep_num, 0);
+ + 		}
+ + 	} else {
+ + 			if ((rx_ch->length - rx_ch->curr_offset) > 0)
+ + 				cppi41_next_rx_segment(rx_ch);
+ + 	}
+ + }
+ + 
+ + static void rxdma_completion_work(struct work_struct *data)
+ + {
+ + 	struct cppi41 *cppi = container_of(data, struct cppi41, rxdma_work);
+ + 	struct musb *musb = cppi->musb;
+ + 	unsigned index;
+ + 	u8 resched = 0;
+ + 	unsigned long flags, length;
+ + 	struct cppi41_channel *rx_ch;
+ + 
+ + 	while (1) {
+ + 		for (index = 0; index < USB_CPPI41_NUM_CH; index++) {
+ + 			rx_ch = &cppi->rx_cppi_ch[index];
+ + 			if (rx_ch->rx_complete) {
+ + 				/* Sometimes a EP can unregister from a DMA
+ + 				 * channel while the data is still in the FIFO.
+ + 				 * Probable reason a proper abort was not
+ + 				 * called before taking such a step.
+ + 				 */
+ + 				if (!rx_ch->curr_pd) {
+ + 					ERR("invalid curr_pd chnum%d\n", index);
+ + 					continue;
+ + 				}
+ + 
+ + 				length = rx_ch->curr_pd->hw_desc.desc_info &
+ + 						CPPI41_PKT_LEN_MASK;
+ + 				if (length == 0) {
+ + 					resched = 1;
+ + 					continue;
+ + 				}
+ + 				spin_lock_irqsave(&musb->lock, flags);
+ + 				usb_process_rx_bd(cppi, rx_ch->curr_pd);
+ + 				rx_ch->rx_complete = 0;
+ + 				rx_ch->curr_pd = 0;
+ + 				spin_unlock_irqrestore(&musb->lock, flags);
+ + 			}
+ + 		}
+ + 
+ + 		if (resched) {
+ + 			resched = 0;
+ + 			cond_resched();
+ + 		} else
+ + 			return ;
+ + 	}
+ + }
+ + 
+ + static void usb_process_rx_queue(struct cppi41 *cppi, unsigned index)
+ + {
+ + 	struct cppi41_queue_obj rx_queue_obj;
+ + 	unsigned long pd_addr;
+ + 	struct usb_cppi41_info *cppi_info = cppi->cppi_info;
+ + 	struct musb *musb = cppi->musb;
+ + 
+ + 	if (cppi41_queue_init(&rx_queue_obj, cppi_info->q_mgr,
+ + 			      cppi_info->rx_comp_q[index])) {
+ + 		dev_dbg(musb->controller, "ERROR: cppi41_queue_init failed for Rx queue\n");
+ + 		return;
+ + 	}
+ + 
+ + 	while ((pd_addr = cppi41_queue_pop(&rx_queue_obj)) != 0) {
+ + 		struct usb_pkt_desc *curr_pd;
+ + 		struct cppi41_channel *rx_ch;
+ + 		u8 ch_num, ep_num;
+ + 		u32 length = 0, timeout = 50;
+ + 
+ + 		curr_pd = usb_get_pd_ptr(cppi, pd_addr);
+ + 		if (curr_pd == NULL) {
+ + 			ERR("Invalid PD popped from Rx completion queue\n");
+ + 			continue;
+ + 		}
+ + 
+ + 		/* This delay is required to overcome the dma race condition
+ + 		 * where software reads buffer descriptor before being updated
+ + 		 * by dma as buffer descriptor's writes by dma still pending in
+ + 		 * interconnect bridge.
+ + 		 */
+ + 		while (timeout--) {
+ + 			length = curr_pd->hw_desc.desc_info &
+ + 					CPPI41_PKT_LEN_MASK;
+ + 			if (length != 0)
+ + 				break;
+ + 			udelay(1);
+ + 		}
+ + 
+ + 
+ + 		/* Extract the data from received packet descriptor */
+ + 		ch_num = curr_pd->ch_num;
+ + 		ep_num = curr_pd->ep_num;
+ + 		rx_ch = &cppi->rx_cppi_ch[ch_num];
+ + 
+ + 		if (length == 0) {
+ + 			dev_dbg(musb->controller, "!Race condtion: rxBD still not"
+ + 				"updated, poll rxBD update ch%d ep%d\n", ch_num,
+ + 				ep_num);
+ + 			rx_ch->rx_complete = 1;
+ + 			rx_ch->curr_pd = curr_pd;
+ + 			schedule_work(&cppi->rxdma_work);
+ + 			continue;
+ + 		}
+ + 
+ + 
+ + 		usb_process_rx_bd(cppi, curr_pd);
+ + 	}
+ + }
+ + 
+ + /*
+ +  * cppi41_completion - handle interrupts from the Tx/Rx completion queues
+ +  *
+ +  * NOTE: since we have to manually prod the Rx process in the transparent mode,
+ +  *	 we certainly want to handle the Rx queues first.
+ +  */
+ + void cppi41_completion(struct musb *musb, u32 rx, u32 tx)
+ + {
+ + 	struct cppi41 *cppi;
+ + 	unsigned index;
+ + 
+ + 	cppi = container_of(musb->dma_controller, struct cppi41, controller);
+ + 
+ + 	/* Process packet descriptors from the Rx queues */
+ + 	for (index = 0; rx != 0; rx >>= 1, index++)
+ + 		if (rx & 1)
+ + 			usb_process_rx_queue(cppi, index);
+ + 
+ + 	/* Process packet descriptors from the Tx completion queues */
+ + 	for (index = 0; tx != 0; tx >>= 1, index++)
+ + 		if (tx & 1)
+ + 			usb_process_tx_queue(cppi, index);
+ + }
+ + EXPORT_SYMBOL(cppi41_completion);
+ + 
+ + MODULE_DESCRIPTION("CPPI4.1 dma controller driver for musb");
+ + MODULE_LICENSE("GPL v2");
+ + 
+ + static int __init cppi41_dma_init(void)
+ + {
+ + 	return 0;
+ + }
+ + module_init(cppi41_dma_init);
+ + 
+ + static void __exit cppi41_dma__exit(void)
+ + {
+ + }
+ + module_exit(cppi41_dma__exit);
+ diff -crN linux-3.2.1_o/drivers/usb/musb/cppi41_dma.h linux-3.2.1/drivers/usb/musb/cppi41_dma.h
+ *** linux-3.2.1_o/drivers/usb/musb/cppi41_dma.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/drivers/usb/musb/cppi41_dma.h	2014-11-25 13:19:16.567059801 +0900
+ ***************
+ *** 0 ****
+ --- 1,68 ----
+ + /*
+ +  * Copyright (C) 2005-2006 by Texas Instruments
+ +  * Copyright (c) 2008, MontaVista Software, Inc. <source@mvista.com>
+ +  *
+ +  * This program is free software; you can distribute it and/or modify it
+ +  * under the terms of the GNU General Public License (Version 2) as
+ +  * published by the Free Software Foundation.
+ +  *
+ +  * This program is distributed in the hope it will be useful, but WITHOUT
+ +  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ +  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ +  * for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License along
+ +  * with this program; if not, write to the Free Software Foundation, Inc.,
+ +  * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ +  *
+ +  */
+ + 
+ + #ifndef _CPPI41_DMA_H_
+ + #define _CPPI41_DMA_H_
+ + #include <plat/usb.h>
+ + 
+ + /* USBSS RTL versions */
+ + #define USBSS_RTL_VERSION_MASK	0xF
+ + #define USBSS_RTL_VERSION_D	0xD
+ + 
+ + /**
+ +  * struct usb_cppi41_info - CPPI 4.1 USB implementation details
+ +  * @dma_block:	DMA block number
+ +  * @ep_dma_ch:	DMA channel numbers used for EPs 1 .. Max_EP
+ +  * @q_mgr:	queue manager number
+ +  * @num_tx_comp_q: number of the Tx completion queues
+ +  * @num_rx_comp_q: number of the Rx queues
+ +  * @tx_comp_q:	pointer to the list of the Tx completion queue numbers
+ +  * @rx_comp_q:	pointer to the list of the Rx queue numbers
+ +  */
+ + struct usb_cppi41_info {
+ + 	u8 dma_block;
+ + 	u8 ep_dma_ch[USB_CPPI41_NUM_CH];
+ + 	u8 q_mgr;
+ + 	u8 num_tx_comp_q;
+ + 	u8 num_rx_comp_q;
+ + 	u16 *tx_comp_q;
+ + 	u16 *rx_comp_q;
+ + 	u8 bd_intr_ctrl;
+ + 	u8 grndis_for_host_rx;
+ + 	u32 version;
+ + };
+ + 
+ + extern struct usb_cppi41_info usb_cppi41_info[];
+ + 
+ + /**
+ +  * cppi41_completion - Tx/Rx completion queue interrupt handling hook
+ +  * @musb:	the controller
+ +  * @rx:	bitmask having bit N set if Rx queue N is not empty
+ +  * @tx:	bitmask having bit N set if Tx completion queue N is not empty
+ +  */
+ + void cppi41_completion(struct musb *musb, u32 rx, u32 tx);
+ + 
+ + /**
+ +  * cppi41_handle_txfifo_intr - Handles tx fifo empty interupts
+ +  * @musb:	the controller
+ +  */
+ + void cppi41_handle_txfifo_intr(struct musb *musb, u16 usbintr);
+ + void txfifoempty_int_enable(struct musb *musb, u8 ep_num);
+ + void txfifoempty_int_disable(struct musb *musb, u8 ep_num);
+ + #endif	/* _CPPI41_DMA_H_ */
+ diff -crN linux-3.2.1_o/drivers/usb/musb/cppi41.h linux-3.2.1/drivers/usb/musb/cppi41.h
+ *** linux-3.2.1_o/drivers/usb/musb/cppi41.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/drivers/usb/musb/cppi41.h	2014-11-25 13:19:16.567059801 +0900
+ ***************
+ *** 0 ****
+ --- 1,851 ----
+ + /*
+ +  * CPPI 4.1 definitions
+ +  *
+ +  * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
+ +  *
+ +  * This program is free software; you can distribute it and/or modify it
+ +  * under the terms of the GNU General Public License (Version 2) as
+ +  * published by the Free Software Foundation.
+ +  *
+ +  * This program is distributed in the hope it will be useful, but WITHOUT
+ +  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ +  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ +  * for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License along
+ +  * with this program; if not, write to the Free Software Foundation, Inc.,
+ +  * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ +  *
+ +  */
+ + 
+ + #include <linux/types.h>
+ + 
+ + /*
+ +  * Queue Manager - Control Registers Region
+ +  */
+ + #define QMGR_REVISION_REG		0x00	/* Major and minor versions */
+ + 						/* of the module */
+ + #define QMGR_QUEUE_DIVERSION_REG	0x08	/* Queue Diversion register */
+ + #define QMGR_FREE_DESC_BUF_STARVED_REG(n) (0x20 + ((n) << 2)) /* Free Desc./ */
+ + 						/* Buffer Starvation Count */
+ + #define QMGR_FREE_DESC_STARVED_REG(n)	(0x30 + ((n) << 2)) /* Free Desc. */
+ + 						/* Starvation Count */
+ + #define QMGR_LINKING_RAM_RGN0_BASE_REG	0x80	/* Linking RAM Region 0 Base */
+ + 						/* Address */
+ + #define QMGR_LINKING_RAM_RGN0_SIZE_REG	0x84	/* Linking RAM Region 0 Size */
+ + #define QMGR_LINKING_RAM_RGN1_BASE_REG	0x88	/* Linking RAM Region 1 Base */
+ + 						/* Address */
+ + #define QMGR_QUEUE_PENDING_REG(n)	(0x90 + ((n) << 2)) /* Pending status */
+ + 						/* for all queues */
+ + 
+ + /*
+ +  * Queue Manager - Memory Region Registers
+ +  */
+ + #define QMGR_MEM_RGN_BASE_REG(r)	(0x00 + ((r) << 4))
+ + #define QMGR_MEM_RGN_CTRL_REG(r)	(0x04 + ((r) << 4))
+ + 
+ + /* Memory Region R Control Register bits */
+ + #define QMGR_MEM_RGN_INDEX_SHIFT	16
+ + #define QMGR_MEM_RGN_INDEX_MASK		(0x3fff << QMGR_MEM_RGN_INDEX_SHIFT)
+ + #define QMGR_MEM_RGN_DESC_SIZE_SHIFT	8
+ + #define QMGR_MEM_RGN_DESC_SIZE_MASK	(0xf << QMGR_MEM_RGN_DESC_SIZE_SHIFT)
+ + #define QMGR_MEM_RGN_SIZE_SHIFT		0
+ + #define QMGR_MEM_RGN_SIZE_MASK		(7 << QMGR_MEM_RGN_SIZE_SHIFT)
+ + 
+ + /*
+ +  * Queue Manager - Queues Region
+ +  */
+ + #define QMGR_QUEUE_REG_A(n)		(0x00 + ((n) << 4))
+ + #define QMGR_QUEUE_REG_B(n)		(0x04 + ((n) << 4))
+ + #define QMGR_QUEUE_REG_C(n)		(0x08 + ((n) << 4))
+ + #define QMGR_QUEUE_REG_D(n)		(0x0C + ((n) << 4))
+ + 
+ + /* Queue N Register C bits */
+ + #define QMGR_QUEUE_HEAD_TAIL_SHIFT	31
+ + #define QMGR_QUEUE_HEAD_TAIL_MASK	(1 << QMGR_QUEUE_HEAD_TAIL_SHIFT)
+ + #define QMGR_QUEUE_PKT_SIZE_SHIFT	0
+ + #define QMGR_QUEUE_PKT_SIZE_MASK	(0x3fff << QMGR_QUEUE_PKT_SIZE_SHIFT)
+ + /* Queue N Register D bits */
+ + #define QMGR_QUEUE_DESC_PTR_SHIFT	5
+ + #define QMGR_QUEUE_DESC_PTR_MASK	(0x7ffffff << QMGR_QUEUE_DESC_PTR_SHIFT)
+ + #define QMGR_QUEUE_DESC_SIZE_SHIFT	0
+ + #define QMGR_QUEUE_DESC_SIZE_MASK	(0x1f << QMGR_QUEUE_DESC_SIZE_SHIFT)
+ + 
+ + /*
+ +  * Queue Manager - Queue Status Region
+ +  */
+ + #define QMGR_QUEUE_STATUS_REG_A(n)	(0x00 + ((n) << 4))
+ + #define QMGR_QUEUE_STATUS_REG_B(n)	(0x04 + ((n) << 4))
+ + #define QMGR_QUEUE_STATUS_REG_C(n)	(0x08 + ((n) << 4))
+ + 
+ + /*
+ +  * DMA Controller - Global Control Registers Region
+ +  */
+ + #define DMA_REVISION_REG		0x00	/* Major and minor versions */
+ + 						/* of the module */
+ + #define DMA_TEARDOWN_FREE_DESC_CTRL_REG 0x04	/* Queue  manager and queue */
+ + 						/* number for Teardown free */
+ + 						/* descriptor queue */
+ + #define DMA_EMULATION_CTRL_REG		0x08	/* Emulation control register */
+ + 
+ + /* Teardown Free Descriptor Queue Control Register bits */
+ + #define DMA_TD_DESC_QMGR_SHIFT		12
+ + #define DMA_TD_DESC_QMGR_MASK		(3 << DMA_TD_DESC_QMGR_SHIFT)
+ + #define DMA_TD_DESC_QNUM_SHIFT		0
+ + #define DMA_TD_DESC_QNUM_MASK		(0xfff << DMA_TD_DESC_QNUM_SHIFT)
+ + 
+ + /*
+ +  * DMA Controller - Channel Control / Status Registers Region
+ +  */
+ + #define DMA_CH_TX_GLOBAL_CFG_REG(n)	 (0x00 + ((n) << 5))
+ + #define DMA_CH_RX_GLOBAL_CFG_REG(n)	 (0x08 + ((n) << 5))
+ + #define DMA_CH_RX_HOST_PKT_CFG_REG_A(n)  (0x0C + ((n) << 5))
+ + #define DMA_CH_RX_HOST_PKT_CFG_REG_B(n)  (0x10 + ((n) << 5))
+ + #define DMA_CH_RX_EMBED_PKT_CFG_REG_A(n) (0x14 + ((n) << 5))
+ + #define DMA_CH_RX_EMBED_PKT_CFG_REG_B(n) (0x18 + ((n) << 5))
+ + #define DMA_CH_RX_MONO_PKT_CFG_REG(n)	 (0x1C + ((n) << 5))
+ + 
+ + /* Tx Channel N Global Configuration Register bits */
+ + #define DMA_CH_TX_ENABLE_SHIFT		31
+ + #define DMA_CH_TX_ENABLE_MASK		(1 << DMA_CH_TX_ENABLE_SHIFT)
+ + #define DMA_CH_TX_TEARDOWN_SHIFT	30
+ + #define DMA_CH_TX_TEARDOWN_MASK		(1 << DMA_CH_TX_TEARDOWN_SHIFT)
+ + #define DMA_CH_TX_DEFAULT_QMGR_SHIFT	12
+ + #define DMA_CH_TX_DEFAULT_QMGR_MASK	(3 << DMA_CH_TX_DEFAULT_QMGR_SHIFT)
+ + #define DMA_CH_TX_DEFAULT_QNUM_SHIFT	0
+ + #define DMA_CH_TX_DEFAULT_QNUM_MASK	(0xfff << DMA_CH_TX_DEFAULT_QNUM_SHIFT)
+ + 
+ + /* Rx Channel N Global Configuration Register bits */
+ + #define DMA_CH_RX_ENABLE_SHIFT		31
+ + #define DMA_CH_RX_ENABLE_MASK		(1 << DMA_CH_RX_ENABLE_SHIFT)
+ + #define DMA_CH_RX_TEARDOWN_SHIFT	30
+ + #define DMA_CH_RX_TEARDOWN_MASK		(1 << DMA_CH_RX_TEARDOWN_SHIFT)
+ + #define DMA_CH_RX_ERROR_HANDLING_SHIFT	24
+ + #define DMA_CH_RX_ERROR_HANDLING_MASK	(1 << DMA_CH_RX_ERROR_HANDLING_SHIFT)
+ + #define DMA_CH_RX_SOP_OFFSET_SHIFT	16
+ + #define DMA_CH_RX_SOP_OFFSET_MASK	(0xff << DMA_CH_RX_SOP_OFFSET_SHIFT)
+ + #define DMA_CH_RX_DEFAULT_DESC_TYPE_SHIFT 14
+ + #define DMA_CH_RX_DEFAULT_DESC_TYPE_MASK  (3 << \
+ + 					   DMA_CH_RX_DEFAULT_DESC_TYPE_SHIFT)
+ + #define DMA_CH_RX_DEFAULT_DESC_EMBED	0
+ + #define DMA_CH_RX_DEFAULT_DESC_HOST	1
+ + #define DMA_CH_RX_DEFAULT_DESC_MONO	2
+ + #define DMA_CH_RX_DEFAULT_RQ_QMGR_SHIFT 12
+ + #define DMA_CH_RX_DEFAULT_RQ_QMGR_MASK	(3 << DMA_CH_RX_DEFAULT_RQ_QMGR_SHIFT)
+ + #define DMA_CH_RX_DEFAULT_RQ_QNUM_SHIFT 0
+ + #define DMA_CH_RX_DEFAULT_RQ_QNUM_MASK	(0xfff << \
+ + 					 DMA_CH_RX_DEFAULT_RQ_QNUM_SHIFT)
+ + #define DMA_CH_RX_MAX_BUF_CNT_SHIFT	26
+ + #define	DMA_CH_RX_MAX_BUF_CNT_0		0
+ + #define	DMA_CH_RX_MAX_BUF_CNT_1		1
+ + #define	DMA_CH_RX_MAX_BUF_CNT_2		2
+ + #define	DMA_CH_RX_MAX_BUF_CNT_3		3
+ + 
+ + /* Rx Channel N Host Packet Configuration Register A/B bits */
+ + #define DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(n) (12 + 16 * ((n) & 1))
+ + #define DMA_CH_RX_HOST_FDQ_QMGR_MASK(n)  (3 << DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(n))
+ + #define DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(n) (0 + 16 * ((n) & 1))
+ + #define DMA_CH_RX_HOST_FDQ_QNUM_MASK(n)  (0xfff << \
+ + 					  DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(n))
+ + 
+ + /* Rx Channel N Embedded Packet Configuration Register A bits */
+ + #define DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(n) (6 + 8 * (n))
+ + #define DMA_CH_RX_EMBED_FBP_BMGR_MASK(n)  (3 << \
+ + 					   DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(n))
+ + #define DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(n) (0 + 8 * (n))
+ + #define DMA_CH_RX_EMBED_FBP_PNUM_MASK(n)  (0x1f << \
+ + 					   DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(n))
+ + 
+ + /* Rx Channel N Embedded Packet Configuration Register B bits */
+ + #define DMA_CH_RX_EMBED_NUM_SLOT_SHIFT	24
+ + #define DMA_CH_RX_EMBED_NUM_SLOT_MASK	(7 << DMA_CH_RX_EMBED_NUM_SLOT_SHIFT)
+ + #define DMA_CH_RX_EMBED_SOP_SLOT_SHIFT	16
+ + #define DMA_CH_RX_EMBED_SOP_SLOT_MASK	(7 << DMA_CH_RX_EMBED_SOP_SLOT_SHIFT)
+ + #define DMA_CH_RX_EMBED_FDQ_QMGR_SHIFT	12
+ + #define DMA_CH_RX_EMBED_FDQ_QMGR_MASK	(3 << DMA_CH_RX_EMBED_FDQ_QMGR_SHIFT)
+ + #define DMA_CH_RX_EMBED_FDQ_QNUM_SHIFT	0
+ + #define DMA_CH_RX_EMBED_FDQ_QNUM_MASK	(0xfff << \
+ + 					 DMA_CH_RX_EMBED_FDQ_QNUM_SHIFT)
+ + 
+ + /* Rx Channel N Monolithic Packet Configuration Register bits */
+ + #define DMA_CH_RX_MONO_SOP_OFFSET_SHIFT 16
+ + #define DMA_CH_RX_MONO_SOP_OFFSET_MASK	(0xff << \
+ + 					 DMA_CH_RX_MONO_SOP_OFFSET_SHIFT)
+ + #define DMA_CH_RX_MONO_FDQ_QMGR_SHIFT	12
+ + #define DMA_CH_RX_MONO_FDQ_QMGR_MASK	(3 << DMA_CH_RX_MONO_FDQ_QMGR_SHIFT)
+ + #define DMA_CH_RX_MONO_FDQ_QNUM_SHIFT	0
+ + #define DMA_CH_RX_MONO_FDQ_QNUM_MASK	(0xfff << DMA_CH_RX_MONO_FDQ_QNUM_SHIFT)
+ + 
+ + /*
+ +  * DMA Scheduler - Control Region
+ +  */
+ + #define DMA_SCHED_CTRL_REG		0x00
+ + 
+ + /* DMA Scheduler Control Register bits */
+ + #define DMA_SCHED_ENABLE_SHIFT		31
+ + #define DMA_SCHED_ENABLE_MASK		(1 << DMA_SCHED_ENABLE_SHIFT)
+ + #define DMA_SCHED_LAST_ENTRY_SHIFT	0
+ + #define DMA_SCHED_LAST_ENTRY_MASK	(0xff << DMA_SCHED_LAST_ENTRY_SHIFT)
+ + 
+ + #define CPPI41_TXDMA_MAXLEN		(4 * 1024 * 1024 - 1)
+ + #define CPPI41_RXDMA_MAXLEN		(64 * 1024)
+ + 
+ + /*
+ +  * Queue Status register
+ +  */
+ + #define CPPI41_QSTATUS_REG0	0x90
+ + #define CPPI41_QSTATUS_REG1	0x94
+ + #define CPPI41_QSTATUS_REG2	0x98
+ + #define CPPI41_QSTATUS_REG3	0x9c
+ + #define CPPI41_QSTATUS_REG4	0xa0
+ + 
+ + /*
+ +  * DMA Scheduler - Table Region
+ +  */
+ + #define DMA_SCHED_TABLE_WORD_REG(n)	((n) << 2)
+ + #define MAX_SCHED_TBL_ENTRY     8
+ + 
+ + /*
+ +  * CPPI 4.1 Host Packet Descriptor
+ +  */
+ + struct cppi41_host_pkt_desc {
+ + 	u32 desc_info;		/* Descriptor type, protocol specific word */
+ + 				/* count, packet length */
+ + 	u32 tag_info;		/* Source tag (31:16), destination tag (15:0) */
+ + 	u32 pkt_info;		/* Packet error state, type, protocol flags, */
+ + 				/* return info, descriptor location */
+ + 	u32 buf_len;		/* Number of valid data bytes in the buffer */
+ + 	u32 buf_ptr;		/* Pointer to the buffer associated with */
+ + 				/* this descriptor */
+ + 	u32 next_desc_ptr;	/* Pointer to the next buffer descriptor */
+ + 	u32 orig_buf_len;	/* Original buffer length */
+ + 	u32 orig_buf_ptr;	/* Original buffer pointer */
+ + 	u32 stk_comms_info[2];	/* Network stack private communications info */
+ + };
+ + 
+ + /*
+ +  * CPPI 4.1 Host Buffer Descriptor
+ +  */
+ + struct cppi41_host_buf_desc {
+ + 	u32 reserved[2];
+ + 	u32 buf_recl_info;	/* Return info, descriptor location */
+ + 	u32 buf_len;		/* Number of valid data bytes in the buffer */
+ + 	u32 buf_ptr;		/* Pointer to the buffer associated with */
+ + 				/* this descriptor */
+ + 	u32 next_desc_ptr;	/* Pointer to the next buffer descriptor */
+ + 	u32 orig_buf_len;	/* Original buffer length */
+ + 	u32 orig_buf_ptr;	/* Original buffer pointer */
+ + };
+ + 
+ + #define CPPI41_DESC_TYPE_SHIFT		27
+ + #define CPPI41_DESC_TYPE_MASK		(0x1f << CPPI41_DESC_TYPE_SHIFT)
+ + #define CPPI41_DESC_TYPE_HOST		16
+ + #define CPPI41_DESC_TYPE_MONOLITHIC	18
+ + #define CPPI41_DESC_TYPE_TEARDOWN	19
+ + #define CPPI41_PROT_VALID_WORD_CNT_SHIFT 22
+ + #define CPPI41_PROT_VALID_WORD_CNT_MASK	(0x1f << CPPI41_PROT_WORD_CNT_SHIFT)
+ + #define CPPI41_PKT_LEN_SHIFT		0
+ + #define CPPI41_PKT_LEN_MASK		(0x1fffff << CPPI41_PKT_LEN_SHIFT)
+ + 
+ + #define CPPI41_PKT_ERROR_SHIFT		31
+ + #define CPPI41_PKT_ERROR_MASK		(1 << CPPI41_PKT_ERROR_SHIFT)
+ + #define CPPI41_PKT_TYPE_SHIFT		26
+ + #define CPPI41_PKT_TYPE_MASK		(0x1f << CPPI41_PKT_TYPE_SHIFT)
+ + #define CPPI41_PKT_TYPE_ATM_AAL5	0
+ + #define CPPI41_PKT_TYPE_ATM_NULL_AAL	1
+ + #define CPPI41_PKT_TYPE_ATM_OAM		2
+ + #define CPPI41_PKT_TYPE_ATM_TRANSPARENT	3
+ + #define CPPI41_PKT_TYPE_EFM		4
+ + #define CPPI41_PKT_TYPE_USB		5
+ + #define CPPI41_PKT_TYPE_GENERIC		6
+ + #define CPPI41_PKT_TYPE_ETHERNET	7
+ + #define CPPI41_ZLP			(1 << 19)
+ + #define CPPI41_RETURN_POLICY_SHIFT	15
+ + #define CPPI41_RETURN_POLICY_MASK	(1 << CPPI41_RETURN_POLICY_SHIFT)
+ + #define CPPI41_RETURN_LINKED		0
+ + #define CPPI41_RETURN_UNLINKED		1
+ + #define CPPI41_ONCHIP_SHIFT		14
+ + #define CPPI41_ONCHIP_MASK		(1 << CPPI41_ONCHIP_SHIFT)
+ + #define CPPI41_RETURN_QMGR_SHIFT	12
+ + #define CPPI41_RETURN_QMGR_MASK		(3 << CPPI41_RETURN_QMGR_SHIFT)
+ + #define CPPI41_RETURN_QNUM_SHIFT	0
+ + #define CPPI41_RETURN_QNUM_MASK		(0xfff << CPPI41_RETURN_QNUM_SHIFT)
+ + 
+ + #define CPPI41_SRC_TAG_PORT_NUM_SHIFT	27
+ + #define CPPI41_SRC_TAG_PORT_NUM_MASK	(0x1f << CPPI41_SRC_TAG_PORT_NUM_SHIFT)
+ + #define CPPI41_SRC_TAG_CH_NUM_SHIFT	21
+ + #define CPPI41_SRC_TAG_CH_NUM_MASK	(0x3f << CPPI41_SRC_TAG_CH_NUM_SHIFT)
+ + #define CPPI41_SRC_TAG_SUB_CH_NUM_SHIFT 16
+ + #define CPPI41_SRC_TAG_SUB_CH_NUM_MASK	(0x1f << \
+ + 					CPPI41_SRC_TAG_SUB_CH_NUM_SHIFT)
+ + #define CPPI41_DEST_TAG_SHIFT		0
+ + #define CPPI41_DEST_TAG_MASK		(0xffff << CPPI41_DEST_TAG_SHIFT)
+ + #define CPPI41_PKT_INTR_FLAG		(1 << 31)
+ + 
+ + /*
+ +  * CPPI 4.1 Teardown Descriptor
+ +  */
+ + struct cppi41_teardown_desc {
+ + 	u32 teardown_info;	/* Teardown information */
+ + 	u32 reserved[7];	/* 28 byte padding */
+ + };
+ + 
+ + #define CPPI41_TEARDOWN_TX_RX_SHIFT	16
+ + #define CPPI41_TEARDOWN_TX_RX_MASK	(1 << CPPI41_TEARDOWN_TX_RX_SHIFT)
+ + #define CPPI41_TEARDOWN_DMA_NUM_SHIFT	10
+ + #define CPPI41_TEARDOWN_DMA_NUM_MASK	(0x3f << CPPI41_TEARDOWN_DMA_NUM_SHIFT)
+ + #define CPPI41_TEARDOWN_CHAN_NUM_SHIFT	0
+ + #define CPPI41_TEARDOWN_CHAN_NUM_MASK	(0x3f << CPPI41_TEARDOWN_CHAN_NUM_SHIFT)
+ + 
+ + #define CPPI41_MAX_MEM_RGN		16
+ + 
+ + /* CPPI 4.1 configuration for AM3517 */
+ + #define CPPI41_NUM_QUEUE_MGR		1	/* 4  max */
+ + #define CPPI41_NUM_DMA_BLOCK		1	/* 64 max */
+ + #define cppi41_num_queue_mgr	CPPI41_NUM_QUEUE_MGR
+ + #define cppi41_num_dma_block	CPPI41_NUM_DMA_BLOCK
+ + 
+ + /**
+ +  * struct cppi41_queue_manager - CPPI 4.1 DMA queue manager registers for
+ +  * context save and restore.
+ +  */
+ + struct cppi41_queue_manager {
+ + 	u32	link_ram_rgn0_base;
+ + 	u32	link_ram_rgn0_size;
+ + 	u32	link_ram_rgn1_base;
+ + 
+ + 	u32	memr_base[8];
+ + 	u32	memr_ctrl[8];
+ + };
+ + 
+ + /**
+ +  * struct cppi41_dma_regs - CPPI 4.1 DMA registers for
+ +  * context save and restore.
+ +  */
+ + struct cppi41_dma_regs {
+ + 	u32	teardn_fdq_ctrl;
+ + 	u32	emulation_ctrl;
+ + 
+ + 	/* CPPI DMA scheduler registers */
+ + 	u32	sched_ctrl;
+ + 
+ + 	/* Queue manager registers */
+ + 	struct cppi41_queue_manager qmgr;
+ + };
+ + 
+ + /**
+ +  * struct cppi41_queue - Queue Tuple
+ +  *
+ +  * The basic queue tuple in CPPI 4.1 used across all data structures
+ +  * where a definition of a queue is required.
+ +  */
+ + struct cppi41_queue {
+ + 	u8  q_mgr;		/* The queue manager number */
+ + 	u16 q_num;		/* The queue number */
+ + };
+ + 
+ + /**
+ +  * struct cppi41_buf_pool - Buffer Pool Tuple
+ +  *
+ +  * The basic buffer pool tuple in CPPI 4.1 used across all data structures
+ +  * where a definition of a buffer pool is required.
+ +  */
+ + struct cppi41_buf_pool {
+ + 	u8  b_mgr;		/* The buffer manager number */
+ + 	u16 b_pool;		/* The buffer pool number */
+ + };
+ + 
+ + /**
+ +  * struct cppi41_queue_mgr - Queue Manager information
+ +  *
+ +  * Contains the information about the queue manager which should be copied from
+ +  * the hardware spec as is.
+ +  */
+ + struct cppi41_queue_mgr {
+ + 	void __iomem *q_mgr_rgn_base; /* Base address of the Control region. */
+ + 	void __iomem *desc_mem_rgn_base; /* Base address of the descriptor */
+ + 				/* memory region. */
+ + 	void __iomem *q_mgmt_rgn_base; /* Base address of the queues region. */
+ + 	void __iomem *q_stat_rgn_base; /* Base address of the queue status */
+ + 				/* region. */
+ + 	u16 num_queue;		/* Number of the queues supported. */
+ + 	u8 queue_types;		/* Bitmask of the supported queue types. */
+ + 	u16 base_fdq_num;	/* The base free descriptor queue number. */
+ + 				/* If present, there's always 16 such queues. */
+ + 	u16 base_fdbq_num;	/* The base free descriptor/buffer queue */
+ + 				/* number.  If present, there's always 16 */
+ + 				/* such queues. */
+ + 	const u32 *assigned;	/* Pointer to the bitmask of the pre-assigned */
+ + 				/* queues. */
+ + };
+ + 
+ + /* Queue type flags */
+ + #define CPPI41_FREE_DESC_QUEUE		0x01
+ + #define CPPI41_FREE_DESC_BUF_QUEUE	0x02
+ + #define CPPI41_UNASSIGNED_QUEUE		0x04
+ + 
+ + /**
+ +  * struct cppi41_embed_pkt_cfg - Rx Channel Embedded packet configuration
+ +  *
+ +  * An instance of this structure forms part of the Rx channel information
+ +  * structure.
+ +  */
+ + struct cppi41_embed_pkt_cfg {
+ + 	struct cppi41_queue fd_queue; /* Free Descriptor queue.*/
+ + 	u8 num_buf_slot;	/* Number of buffer slots in the descriptor */
+ + 	u8 sop_slot_num;	/* SOP buffer slot number. */
+ + 	struct cppi41_buf_pool free_buf_pool[4]; /* Free Buffer pool. Element */
+ + 				/* 0 used for the 1st Rx buffer, etc. */
+ + };
+ + 
+ + /**
+ +  * struct cppi41_host_pkt_cfg - Rx Channel Host Packet Configuration
+ +  *
+ +  * An instance of this structure forms part of the Rx channel information
+ +  * structure.
+ +  */
+ + struct cppi41_host_pkt_cfg {
+ + 	struct cppi41_queue fdb_queue[4]; /* Free Desc/Buffer queue. Element */
+ + 				/* 0 used for 1st Rx buffer, etc. */
+ + };
+ + 
+ + /**
+ +  * struct cppi41_mono_pkt_cfg - Rx Channel Monolithic Packet Configuration
+ +  *
+ +  * An instance of this structure forms part of the Rx channel information
+ +  * structure.
+ +  */
+ + struct cppi41_mono_pkt_cfg {
+ + 	struct cppi41_queue fd_queue; /* Free descriptor queue */
+ + 	u8 sop_offset;		/* Number of bytes to skip before writing */
+ + 				/* payload */
+ + };
+ + 
+ + enum cppi41_rx_desc_type {
+ + 	cppi41_rx_embed_desc,
+ + 	cppi41_rx_host_desc,
+ + 	cppi41_rx_mono_desc,
+ + };
+ + 
+ + /**
+ +  * struct cppi41_rx_ch_cfg - Rx Channel Configuration
+ +  *
+ +  * Must be allocated and filled by the caller of cppi41_rx_ch_configure().
+ +  *
+ +  * The same channel can be configured to receive different descripor type
+ +  * packets (not simaltaneously). When the Rx packets on a port need to be sent
+ +  * to the SR, the channels default descriptor type is set to Embedded and the
+ +  * Rx completion queue is set to the queue which CPU polls for input packets.
+ +  * When in SR bypass mode, the same channel's default descriptor type will be
+ +  * set to Host and the Rx completion queue set to one of the queues which host
+ +  * can get interrupted on (via the Queuing proxy/accumulator). In this example,
+ +  * the embedded mode configuration fetches free descriptor from the Free
+ +  * descriptor queue (as defined by struct cppi41_embed_pkt_cfg) and host
+ +  * mode configuration fetches free descriptors/buffers from the free descriptor/
+ +  * buffer queue (as defined by struct cppi41_host_pkt_cfg).
+ +  *
+ +  * NOTE: There seems to be no separate configuration for teardown completion
+ +  * descriptor. The assumption is rxQueue tuple is used for this purpose as well.
+ +  */
+ + struct cppi41_rx_ch_cfg {
+ + 	enum cppi41_rx_desc_type default_desc_type; /* Describes which queue */
+ + 				/* configuration is used for the free */
+ + 				/* descriptors and/or buffers */
+ + 	u8 sop_offset;		/* Number of bytes to skip in SOP buffer */
+ + 				/* before writing payload */
+ + 	u8 retry_starved;	/* 0 = Drop packet on descriptor/buffer */
+ + 				/* starvartion, 1 = DMA retries FIFO block */
+ + 				/* transfer at a later time */
+ + 	u8 rx_max_buf_cnt;	/* The DMA ignores the SOP bit and closes up
+ + 				 * a packet after a max_buf_cnt buffer has been
+ + 				 * filled OR if the EOP field is set in the
+ + 				 * info word 0
+ + 				 */
+ + 	struct cppi41_queue rx_queue; /* Rx complete packets queue */
+ + 	union {
+ + 		struct cppi41_host_pkt_cfg host_pkt; /* Host packet */
+ + 				/* configuration. This defines where channel */
+ + 				/* picks free descriptors from. */
+ + 		struct cppi41_embed_pkt_cfg embed_pkt; /* Embedded packet */
+ + 				/* configuration. This defines where channel */
+ + 				/* picks free descriptors/buffers from. */
+ + 				/* from. */
+ + 		struct cppi41_mono_pkt_cfg mono_pkt; /* Monolithic packet */
+ + 				/* configuration. This defines where channel */
+ + 				/* picks free descriptors from. */
+ + 	} cfg;			/* Union of packet configuration structures */
+ + 				/* to be filled in depending on the */
+ + 				/* defDescType field. */
+ + };
+ + 
+ + /**
+ +  * struct cppi41_tx_ch - Tx channel information
+ +  *
+ +  * NOTE: The queues that feed into the Tx channel are fixed at SoC design time.
+ +  */
+ + struct cppi41_tx_ch {
+ + 	u8 port_num;		/* Port number. */
+ + 	u8 ch_num;		/* Channel number within port. */
+ + 	u8 sub_ch_num;		/* Sub-channel number within channel. */
+ + 	u8 num_tx_queue;	/* Number of queues from which the channel */
+ + 				/* can feed. */
+ + 	struct cppi41_queue tx_queue[4]; /* List of queues from which the */
+ + 				/* channel can feed. */
+ + };
+ + 
+ + /**
+ +  * struct cppi41_dma_block - CPPI 4.1 DMA configuration
+ +  *
+ +  * Configuration information for CPPI DMA functionality. Includes the Global
+ +  * configuration, Channel configuration, and the Scheduler configuration.
+ +  */
+ + struct cppi41_dma_block {
+ + 	void __iomem *global_ctrl_base; /* Base address of the Global Control */
+ + 				/* registers. */
+ + 	void __iomem *ch_ctrl_stat_base; /* Base address of the Channel */
+ + 				/* Control/Status registers. */
+ + 	void __iomem *sched_ctrl_base; /* Base address of the Scheduler */
+ + 				/* Control register. */
+ + 	void __iomem *sched_table_base; /* Base address of the Scheduler */
+ + 				/* Table registers. */
+ + 	u8 num_tx_ch;		/* Number of the Tx channels. */
+ + 	u8 num_rx_ch;		/* Number of the Rx channels. */
+ + 	u8 num_max_ch;		/* maximum dma channels */
+ + 	const struct cppi41_tx_ch *tx_ch_info;
+ + 	struct cppi41_dma_regs cppi41_regs; /* registers to save and restore */
+ + };
+ + 
+ + extern struct cppi41_queue_mgr cppi41_queue_mgr[];
+ + extern struct cppi41_dma_block cppi41_dma_block[];
+ + 
+ + /**
+ +  * struct cppi41_dma_ch_obj - CPPI 4.1 DMA Channel object
+ +  */
+ + struct cppi41_dma_ch_obj {
+ + 	void __iomem *base_addr; /* The address of the channel global */
+ + 				/* configuration register */
+ + 	u32 global_cfg;		/* Tx/Rx global configuration backed-up value */
+ + };
+ + 
+ + /**
+ +  * struct cppi41_queue_obj - CPPI 4.1 queue object
+ +  */
+ + struct cppi41_queue_obj {
+ + 	void __iomem *base_addr; /* The base address of the queue management */
+ + 				/* registers */
+ + };
+ + 
+ + static inline u32 cppi_readl(const void __iomem *addr)
+ + 	{ return readl(addr); }
+ + static inline void cppi_writel(u32 data, void __iomem *addr)
+ + 	{ writel(data, addr); }
+ + /**
+ +  * cppi41_queue_mgr_init - CPPI 4.1 queue manager initialization.
+ +  * @q_mgr:	the queue manager to initialize
+ +  * @rgn0_base:	linking RAM region 0 physical address
+ +  * @rgn0_size:	linking RAM region 0 size in 32-bit words (0 to 0x3fff)
+ +  *
+ +  * Returns 0 on success, error otherwise.
+ +  */
+ + int cppi41_queue_mgr_init(u8 q_mgr, dma_addr_t rgn0_base, u16 rgn0_size);
+ + 
+ + /**
+ +  * cppi41_queue_mgr_init - CPPI 4.1 queue manager un-initialization.
+ +  * @q_mgr:	the queue manager to un-initialize
+ +  * Returns 0 on success, error otherwise.
+ +  */
+ + int cppi41_queue_mgr_uninit(u8 q_mgr);
+ + 
+ + /*
+ +  * CPPI 4.1 Queue Manager Memory Region Allocation and De-allocation APIs.
+ +  */
+ + 
+ + /**
+ +  * cppi41_mem_rgn_alloc - CPPI 4.1 queue manager memory region allocation.
+ +  * @q_mgr:	the queue manager whose memory region to allocate
+ +  * @rgn_addr:	physical address of the memory region
+ +  * @size_order:	descriptor size as a power of two (between 5 and 13)
+ +  * @num_order:	number of descriptors as a power of two (between 5 and 12)
+ +  * @mem_rgn:	pointer to the index of the memory region allocated
+ +  *
+ +  * This function allocates a memory region within the queue manager
+ +  * consisiting of the descriptors of paricular size and number.
+ +  *
+ +  * Returns 0 on success, error otherwise.
+ +  */
+ + int cppi41_mem_rgn_alloc(u8 q_mgr, dma_addr_t rgn_addr, u8 size_order,
+ + 			 u8 num_order, u8 *mem_rgn);
+ + 
+ + /**
+ +  * cppi41_mem_rgn_free - CPPI 4.1 queue manager memory region de-allocation.
+ +  * @q_mgr:	the queue manager whose memory region was allocated
+ +  * @mem_rgn:	index of the memory region
+ +  *
+ +  * This function frees the memory region allocated by cppi41_mem_rgn_alloc().
+ +  *
+ +  * Returns 0 on success, -EINVAL otherwise.
+ +  */
+ + int cppi41_mem_rgn_free(u8 q_mgr, u8 mem_rgn);
+ + 
+ + /**
+ +  * cppi41_dma_block_init - CPPI 4.1 DMA block initialization.
+ +  * @dma_num:	number of the DMA block
+ +  * @q_mgr:	the queue manager in which to allocate the free teardown
+ +  *		descriptor queue
+ +  * @num_order:	number of teardown descriptors as a power of two (at least 5)
+ +  * @sched_tbl:	the DMA scheduler table
+ +  * @tbl_size:	number of entries in the DMA scheduler table
+ +  *
+ +  * This function frees the memory region allocated by cppi41_mem_rgn_alloc().
+ +  *
+ +  * Returns 0 on success, error otherwise.
+ +  */
+ + int cppi41_dma_block_init(u8 dma_num, u8 q_mgr, u8 num_order,
+ + 				 u32 *sched_tbl, u8 tbl_size);
+ + 
+ + /**
+ +  * cppi41_dma_block_init - CPPI 4.1 DMA block un-initialization.
+ +  * @dma_num:	number of the DMA block
+ +  * @q_mgr:	the queue manager in which to allocate the free teardown
+ +  *		descriptor queue
+ +  * @num_order:	number of teardown descriptors as a power of two (at least 5)
+ +  * @sched_tbl:	the DMA scheduler table
+ +  * @tbl_size:	number of entries in the DMA scheduler table
+ +  *
+ +  * Returns 0 on success, error otherwise.
+ +  */
+ + int cppi41_dma_block_uninit(u8 dma_num, u8 q_mgr, u8 num_order,
+ + 				 u32 *sched_tbl, u8 tbl_size);
+ + 
+ + /*
+ +  * CPPI 4.1 DMA Channel Management APIs
+ +  */
+ + 
+ + /**
+ +  * cppi41_tx_ch_init - initialize CPPI 4.1 transmit channel object
+ +  * @tx_ch_obj:	pointer to Tx channel object
+ +  * @dma_num:	DMA block to which this channel belongs
+ +  * @ch_num:	DMA channel number
+ +  *
+ +  * Returns 0 if valid Tx channel, -EINVAL otherwise.
+ +  */
+ + int cppi41_tx_ch_init(struct cppi41_dma_ch_obj *tx_ch_obj,
+ + 		      u8 dma_num, u8 ch_num);
+ + 
+ + /**
+ +  * cppi41_rx_ch_init - initialize CPPI 4.1 receive channel object
+ +  * @rx_ch_obj:	pointer to Rx channel object
+ +  * @dma_num:	DMA block to which this channel belongs
+ +  * @ch_num:	DMA channel number
+ +  *
+ +  * Returns 0 if valid Rx channel, -EINVAL otherwise.
+ +  */
+ + int cppi41_rx_ch_init(struct cppi41_dma_ch_obj *rx_ch_obj,
+ + 		      u8 dma_num, u8 ch_num);
+ + 
+ + /**
+ +  * cppi41_dma_ch_default_queue - set CPPI 4.1 channel default completion queue
+ +  * @dma_ch_obj: pointer to DMA channel object
+ +  * @q_mgr:	default queue manager
+ +  * @q_num:	default queue number
+ +  *
+ +  * This function configures the specified channel.  The caller is required to
+ +  * provide the default queue onto which the teardown descriptors will be queued.
+ +  */
+ + void cppi41_dma_ch_default_queue(struct cppi41_dma_ch_obj *dma_ch_obj,
+ + 				 u8 q_mgr, u16 q_num);
+ + 
+ + /**
+ +  * cppi41_rx_ch_configure - configure CPPI 4.1 receive channel
+ +  * @rx_ch_obj:	pointer to Rx channel object
+ +  * @cfg:	pointer to Rx channel configuration
+ +  *
+ +  * This function configures and opens the specified Rx channel.  The caller
+ +  * is required to provide channel configuration information by initializing
+ +  * a struct cppi41_rx_ch_cfg.
+ +  */
+ + void cppi41_rx_ch_configure(struct cppi41_dma_ch_obj *rx_ch_obj,
+ + 			    struct cppi41_rx_ch_cfg  *cfg);
+ + 
+ + /**
+ +  * cppi41_rx_ch_set_maxbufcnt - configure max rx buffer count
+ +  * @rx_ch_obj:	pointer to Rx channel object
+ +  * rx_max_buf_cnt: maximum rx buffer count
+ +  *
+ +  * This function configures the maximum rx buffer count in rx dma
+ +  * global configuration register. The valid rx_max_buf_cnt value
+ +  * must be 0 to 4.
+ +  */
+ + void cppi41_rx_ch_set_maxbufcnt(struct cppi41_dma_ch_obj *rx_ch_obj,
+ + 			    u8 rx_max_buf_cnt);
+ + /**
+ +  * cppi41_dma_ch_enable - enable CPPI 4.1 Tx/Rx DMA channel
+ +  * @dma_ch_obj:	pointer to DMA channel object
+ +  *
+ +  * This function enables  a specified Tx channel.  The caller is required to
+ +  * provide a reference to a channel object initialized by an earlier call of
+ +  * the cppi41_dma_ch_init() function.  After the successful completion of this
+ +  * function, the Tx DMA channel will be active and ready for data transmission.
+ +  */
+ + void cppi41_dma_ch_enable(struct cppi41_dma_ch_obj *dma_ch_obj);
+ + 
+ + /**
+ +  * cppi41_dma_ch_disable - disable CPPI 4.1 Tx/Rx DMA channel
+ +  * @dma_ch_obj:	pointer to DMA channel object
+ +  *
+ +  * This function disables a specific Tx channel.  The caller is required to
+ +  * provide a reference to a channel object initialized by an earlier call of
+ +  * the cppi41_dma_ch_init() function.  After the successful completion of this
+ +  * function, the Tx DMA channel will be deactived.
+ +  */
+ + void cppi41_dma_ch_disable(struct cppi41_dma_ch_obj *dma_ch_obj);
+ + 
+ + /**
+ +  * cppi41_dma_ch_teardown - tear down CPPI 4.1 transmit channel
+ +  * @dma_ch_obj:	pointer DMA channel object
+ +  *
+ +  * This function triggers the teardown of the given DMA channel.
+ +  *
+ +  * ATTENTION: Channel disable should not be called before the teardown is
+ +  * completed as a disable will stop the DMA scheduling on the channel resulting
+ +  * in the teardown complete event not being registered at all.
+ +  *
+ +  * NOTE: A successful channel teardown event is reported via queueing of a
+ +  * teardown descriptor.
+ +  *
+ +  * This function just sets up for the teardown of the channel and returns. The
+ +  * caller must detect the channel teardown event to assume that the channel is
+ +  * disabled.
+ +  *
+ +  * See cppi41_get_teardown_info() for the teardown completion processing.
+ +  */
+ + void cppi41_dma_ch_teardown(struct cppi41_dma_ch_obj *dma_ch_obj);
+ + 
+ + /*
+ +  * CPPI 4.1 Queue Allocation and De-allocation APIs.
+ +  */
+ + 
+ + /**
+ +  * cppi41_queue_alloc - allocate CPPI 4.1 queue
+ +  * @type:	queue type bitmask
+ +  * @q_mgr:	queue manager
+ +  * @q_num:	pointer to the queue number
+ +  *
+ +  * Returns 0 if queue allocated, error otherwise.
+ +  */
+ + int cppi41_queue_alloc(u8 type, u8 q_mgr, u16 *q_num);
+ + 
+ + /**
+ +  * cppi41_queue_free - de-allocate CPPI 4.1 queue
+ +  * @q_mgr:	queue manager
+ +  * @q_num:	queue number
+ +  *
+ +  * Returns 0 on success, -EINVAL otherwise.
+ +  */
+ + int cppi41_queue_free(u8 q_mgr, u16 q_num);
+ + 
+ + /*
+ +  *  CPPI 4.1 Queue Management APIs
+ +  */
+ + 
+ + /**
+ +  * cppi41_queue_init - initialize CPPI 4.1 queue object
+ +  * @queue_obj:	pointer to the queue object
+ +  * @q_mgr:	queue manager
+ +  * @q_num:	queue number
+ +  *
+ +  * Returns 0 if valid queue, -EINVAL otherwise.
+ +  */
+ + int cppi41_queue_init(struct cppi41_queue_obj *queue_obj, u8 q_mgr, u16 q_num);
+ + 
+ + /**
+ +  * cppi41_queue_push - push to CPPI 4.1 queue
+ +  * @queue_obj:	pointer to the queue object
+ +  * @desc_addr:	descriptor physical address
+ +  * @desc_size:	descriptor size
+ +  * @pkt_size:	packet size
+ +  *
+ +  * This function is called to queue a descriptor onto a queue.
+ +  * NOTE: pSize parameter is optional. Pass 0 in case not required.
+ +  */
+ + void cppi41_queue_push(const struct cppi41_queue_obj *queue_obj, u32 desc_addr,
+ + 		       u32 desc_size, u32 pkt_size);
+ + 
+ + /**
+ +  * cppi41_queue_pop - pop from CPPI 4.1 queue
+ +  * @queue_obj:	pointer to the queue object
+ +  *
+ +  * This function is called to pop a single descriptor from the queue.
+ +  *
+ +  * Returns a packet descriptor's physical address.
+ +  */
+ + unsigned long cppi41_queue_pop(const struct cppi41_queue_obj *queue_obj);
+ + 
+ + /*
+ +  * CPPI 4.1 Miscellaneous APIs
+ +  */
+ + 
+ + /**
+ +  * cppi41_get_teardown_info - CPPI 4.1 teardown completion processing function
+ +  *
+ +  * @addr:	physical address of teardown descriptor
+ +  * @info:	pointer to the teardown information word
+ +  *
+ +  * This function is called to complete the teardown processing on a channel
+ +  * and provides teardown information from the teardown descriptor passed to it.
+ +  * It also recycles the teardown descriptor back to the teardown descriptor
+ +  * queue.
+ +  *
+ +  * Returns 0 if valid descriptor, -EINVAL otherwise.
+ +  */
+ + int cppi41_get_teardown_info(unsigned long addr, u32 *info);
+ + 
+ + /**
+ +  * cppi41_dma_sched_tbl_init
+ +  */
+ + int cppi41_dma_sched_tbl_init(u8 dma_num, u8 q_mgr,
+ + 				u32 *sched_tbl, u8 tbl_size);
+ + 
+ + /**
+ +  * cppi41_schedtbl_add_dma_ch - add a dma channel to schedular table
+ +  *
+ +  * @dmanum      Number of DMa block
+ +  * @qmgr        Queue Manager Number
+ +  * @dma_ch      dma channel number
+ +  * @is_tx       transmit (is_tx=1) or recieve(is_tx=0)
+ +  *
+ +  * returns      number of channel in schedular table
+ +  */
+ + int cppi41_schedtbl_add_dma_ch(u8 dmanum, u8 qmgr, u8 dma_ch, u8 is_tx);
+ + 
+ + /**
+ +  * cppi41_schedtbl_remove_dma_ch - remove a dma channel from schedular table
+ +  *
+ +  * @dmanum      Number of DMa block
+ +  * @qmgr        Queue Manager Number
+ +  * @dma_ch      dma channel number
+ +  * @is_tx       transmit (is_tx=1) or recieve(is_tx=0)
+ +  *
+ +  * returns      number of channel in schedular table
+ +  */
+ + int cppi41_schedtbl_remove_dma_ch(u8 dmanum, u8 qmgr, u8 dma_ch, u8 is_tx);
+ + 
+ + /**
+ +  * cppi41_init_teardown_queue
+ +  */
+ + void cppi41_init_teardown_queue(int dma_num);
+ + 
+ + /**
+ +  * cppi41_free_teardown_queue
+ +  */
+ + void cppi41_free_teardown_queue(int dma_num);
+ + 
+ + /**
+ +  * cppi41_save_context
+ +  */
+ + void cppi41_save_context(u8 dma_num);
+ + 
+ + /**
+ +  * cppi41_restore_context
+ +  */
+ + void cppi41_restore_context(u8 dma_num, u32 *sched_tbl);
+ diff -crN linux-3.2.1_o/drivers/usb/musb/cppi_dma.c linux-3.2.1/drivers/usb/musb/cppi_dma.c
+ *** linux-3.2.1_o/drivers/usb/musb/cppi_dma.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/musb/cppi_dma.c	2014-11-25 13:19:16.571458448 +0900
+ ***************
+ *** 104,110 ****
+   	musb_writel(&tx->tx_complete, 0, ptr);
+   }
+   
+ ! static void __init cppi_pool_init(struct cppi *cppi, struct cppi_channel *c)
+   {
+   	int	j;
+   
+ --- 104,110 ----
+   	musb_writel(&tx->tx_complete, 0, ptr);
+   }
+   
+ ! static void __devinit cppi_pool_init(struct cppi *cppi, struct cppi_channel *c)
+   {
+   	int	j;
+   
+ ***************
+ *** 149,155 ****
+   	c->last_processed = NULL;
+   }
+   
+ ! static int __init cppi_controller_start(struct dma_controller *c)
+   {
+   	struct cppi	*controller;
+   	void __iomem	*tibase;
+ --- 149,155 ----
+   	c->last_processed = NULL;
+   }
+   
+ ! static int __devinit cppi_controller_start(struct dma_controller *c)
+   {
+   	struct cppi	*controller;
+   	void __iomem	*tibase;
+ ***************
+ *** 359,366 ****
+   {
+   	void __iomem			*base = c->controller->mregs;
+   	struct cppi_rx_stateram __iomem	*rx = c->state_ram;
+   
+ ! 	musb_ep_select(base, c->index + 1);
+   
+   	dev_dbg(c->controller->musb->controller,
+   		"RX DMA%d%s: %d left, csr %04x, "
+ --- 359,367 ----
+   {
+   	void __iomem			*base = c->controller->mregs;
+   	struct cppi_rx_stateram __iomem	*rx = c->state_ram;
+ + 	struct musb		*musb = c->controller->musb;
+   
+ ! 	musb_ep_select(musb, base, c->index + 1);
+   
+   	dev_dbg(c->controller->musb->controller,
+   		"RX DMA%d%s: %d left, csr %04x, "
+ ***************
+ *** 390,397 ****
+   {
+   	void __iomem			*base = c->controller->mregs;
+   	struct cppi_tx_stateram __iomem	*tx = c->state_ram;
+   
+ ! 	musb_ep_select(base, c->index + 1);
+   
+   	dev_dbg(c->controller->musb->controller,
+   		"TX DMA%d%s: csr %04x, "
+ --- 391,399 ----
+   {
+   	void __iomem			*base = c->controller->mregs;
+   	struct cppi_tx_stateram __iomem	*tx = c->state_ram;
+ + 	struct musb		*musb = c->controller->musb;
+   
+ ! 	musb_ep_select(musb, base, c->index + 1);
+   
+   	dev_dbg(c->controller->musb->controller,
+   		"TX DMA%d%s: csr %04x, "
+ ***************
+ *** 513,519 ****
+   		if (!(val & MUSB_RXCSR_H_REQPKT)) {
+   			val |= MUSB_RXCSR_H_REQPKT | MUSB_RXCSR_H_WZC_BITS;
+   			musb_writew(regs, MUSB_RXCSR, val);
+ ! 			/* flush writebufer */
+   			val = musb_readw(regs, MUSB_RXCSR);
+   		}
+   	}
+ --- 515,521 ----
+   		if (!(val & MUSB_RXCSR_H_REQPKT)) {
+   			val |= MUSB_RXCSR_H_REQPKT | MUSB_RXCSR_H_WZC_BITS;
+   			musb_writew(regs, MUSB_RXCSR, val);
+ ! 			/* flush writebuffer */
+   			val = musb_readw(regs, MUSB_RXCSR);
+   		}
+   	}
+ ***************
+ *** 1117,1123 ****
+   			 */
+   			WARN_ON(rx->head);
+   		}
+ ! 		musb_ep_select(cppi->mregs, rx->index + 1);
+   		csr = musb_readw(regs, MUSB_RXCSR);
+   		if (csr & MUSB_RXCSR_DMAENAB) {
+   			dev_dbg(musb->controller, "list%d %p/%p, last %llx%s, csr %04x\n",
+ --- 1119,1125 ----
+   			 */
+   			WARN_ON(rx->head);
+   		}
+ ! 		musb_ep_select(cppi->musb, cppi->mregs, rx->index + 1);
+   		csr = musb_readw(regs, MUSB_RXCSR);
+   		if (csr & MUSB_RXCSR_DMAENAB) {
+   			dev_dbg(musb->controller, "list%d %p/%p, last %llx%s, csr %04x\n",
+ ***************
+ *** 1315,1322 ****
+   }
+   
+   /* Instantiate a software object representing a DMA controller. */
+ ! struct dma_controller *__init
+ ! dma_controller_create(struct musb *musb, void __iomem *mregs)
+   {
+   	struct cppi		*controller;
+   	struct device		*dev = musb->controller;
+ --- 1317,1324 ----
+   }
+   
+   /* Instantiate a software object representing a DMA controller. */
+ ! struct dma_controller *__devinit
+ ! cppi_dma_controller_create(struct musb *musb, void __iomem *mregs)
+   {
+   	struct cppi		*controller;
+   	struct device		*dev = musb->controller;
+ ***************
+ *** 1355,1361 ****
+   	if (irq > 0) {
+   		if (request_irq(irq, cppi_interrupt, 0, "cppi-dma", musb)) {
+   			dev_err(dev, "request_irq %d failed!\n", irq);
+ ! 			dma_controller_destroy(&controller->controller);
+   			return NULL;
+   		}
+   		controller->irq = irq;
+ --- 1357,1363 ----
+   	if (irq > 0) {
+   		if (request_irq(irq, cppi_interrupt, 0, "cppi-dma", musb)) {
+   			dev_err(dev, "request_irq %d failed!\n", irq);
+ ! 			cppi_dma_controller_destroy(&controller->controller);
+   			return NULL;
+   		}
+   		controller->irq = irq;
+ ***************
+ *** 1363,1373 ****
+   
+   	return &controller->controller;
+   }
+   
+   /*
+    *  Destroy a previously-instantiated DMA controller.
+    */
+ ! void dma_controller_destroy(struct dma_controller *c)
+   {
+   	struct cppi	*cppi;
+   
+ --- 1365,1376 ----
+   
+   	return &controller->controller;
+   }
+ + EXPORT_SYMBOL(cppi_dma_controller_create);
+   
+   /*
+    *  Destroy a previously-instantiated DMA controller.
+    */
+ ! void cppi_dma_controller_destroy(struct dma_controller *c)
+   {
+   	struct cppi	*cppi;
+   
+ ***************
+ *** 1381,1386 ****
+ --- 1384,1390 ----
+   
+   	kfree(cppi);
+   }
+ + EXPORT_SYMBOL(cppi_dma_controller_destroy);
+   
+   /*
+    * Context: controller irqlocked, endpoint selected
+ ***************
+ *** 1428,1434 ****
+   	 * and caller should rely on us not changing it.
+   	 * peripheral code is safe ... check host too.
+   	 */
+ ! 	musb_ep_select(mbase, cppi_ch->index + 1);
+   
+   	if (cppi_ch->transmit) {
+   		struct cppi_tx_stateram __iomem *tx_ram;
+ --- 1432,1438 ----
+   	 * and caller should rely on us not changing it.
+   	 * peripheral code is safe ... check host too.
+   	 */
+ ! 	musb_ep_select(controller->musb, mbase, cppi_ch->index + 1);
+   
+   	if (cppi_ch->transmit) {
+   		struct cppi_tx_stateram __iomem *tx_ram;
+ ***************
+ *** 1561,1563 ****
+ --- 1565,1580 ----
+    * Power Management ... probably turn off cppi during suspend, restart;
+    * check state ram?  Clocking is presumably shared with usb core.
+    */
+ + MODULE_DESCRIPTION("CPPI dma controller driver for musb");
+ + MODULE_LICENSE("GPL v2");
+ + 
+ + static int __init cppi_dma_init(void)
+ + {
+ + 	return 0;
+ + }
+ + module_init(cppi_dma_init);
+ + 
+ + static void __exit cppi_dma__exit(void)
+ + {
+ + }
+ + module_exit(cppi_dma__exit);
+ diff -crN linux-3.2.1_o/drivers/usb/musb/da8xx.c linux-3.2.1/drivers/usb/musb/da8xx.c
+ *** linux-3.2.1_o/drivers/usb/musb/da8xx.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/musb/da8xx.c	2014-11-25 13:19:16.579757957 +0900
+ ***************
+ *** 423,430 ****
+   	if (!rev)
+   		goto fail;
+   
+ ! 	usb_nop_xceiv_register();
+ ! 	musb->xceiv = otg_get_transceiver();
+   	if (!musb->xceiv)
+   		goto fail;
+   
+ --- 423,430 ----
+   	if (!rev)
+   		goto fail;
+   
+ ! 	usb_nop_xceiv_register(musb->id);
+ ! 	musb->xceiv = otg_get_transceiver(musb->id);
+   	if (!musb->xceiv)
+   		goto fail;
+   
+ ***************
+ *** 458,469 ****
+   	phy_off();
+   
+   	otg_put_transceiver(musb->xceiv);
+ ! 	usb_nop_xceiv_unregister();
+   
+   	return 0;
+   }
+   
+   static const struct musb_platform_ops da8xx_ops = {
+   	.init		= da8xx_musb_init,
+   	.exit		= da8xx_musb_exit,
+   
+ --- 458,471 ----
+   	phy_off();
+   
+   	otg_put_transceiver(musb->xceiv);
+ ! 	usb_nop_xceiv_unregister(musb->id);
+   
+   	return 0;
+   }
+   
+   static const struct musb_platform_ops da8xx_ops = {
+ + 	.fifo_mode	= 2,
+ + 	.flags		= MUSB_GLUE_EP_ADDR_FLAT_MAPPING,
+   	.init		= da8xx_musb_init,
+   	.exit		= da8xx_musb_exit,
+   
+ ***************
+ *** 474,479 ****
+ --- 476,484 ----
+   	.try_idle	= da8xx_musb_try_idle,
+   
+   	.set_vbus	= da8xx_musb_set_vbus,
+ + 
+ + 	.read_fifo	= musb_read_fifo,
+ + 	.write_fifo	= musb_write_fifo,
+   };
+   
+   static u64 da8xx_dmamask = DMA_BIT_MASK(32);
+ diff -crN linux-3.2.1_o/drivers/usb/musb/davinci.c linux-3.2.1/drivers/usb/musb/davinci.c
+ *** linux-3.2.1_o/drivers/usb/musb/davinci.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/musb/davinci.c	2014-11-25 13:19:16.587594536 +0900
+ ***************
+ *** 287,293 ****
+   	 * mask, state, "vector", and EOI registers.
+   	 */
+   	cppi = container_of(musb->dma_controller, struct cppi, controller);
+ ! 	if (is_cppi_enabled() && musb->dma_controller && !cppi->irq)
+   		retval = cppi_interrupt(irq, __hci);
+   
+   	/* ack and handle non-CPPI interrupts */
+ --- 287,293 ----
+   	 * mask, state, "vector", and EOI registers.
+   	 */
+   	cppi = container_of(musb->dma_controller, struct cppi, controller);
+ ! 	if (is_cppi_enabled(musb) && musb->dma_controller && !cppi->irq)
+   		retval = cppi_interrupt(irq, __hci);
+   
+   	/* ack and handle non-CPPI interrupts */
+ ***************
+ *** 385,392 ****
+   	void __iomem	*tibase = musb->ctrl_base;
+   	u32		revision;
+   
+ ! 	usb_nop_xceiv_register();
+ ! 	musb->xceiv = otg_get_transceiver();
+   	if (!musb->xceiv)
+   		return -ENODEV;
+   
+ --- 385,392 ----
+   	void __iomem	*tibase = musb->ctrl_base;
+   	u32		revision;
+   
+ ! 	usb_nop_xceiv_register(musb->id);
+ ! 	musb->xceiv = otg_get_transceiver(musb->id);
+   	if (!musb->xceiv)
+   		return -ENODEV;
+   
+ ***************
+ *** 446,452 ****
+   
+   fail:
+   	otg_put_transceiver(musb->xceiv);
+ ! 	usb_nop_xceiv_unregister();
+   	return -ENODEV;
+   }
+   
+ --- 446,452 ----
+   
+   fail:
+   	otg_put_transceiver(musb->xceiv);
+ ! 	usb_nop_xceiv_unregister(musb->id);
+   	return -ENODEV;
+   }
+   
+ ***************
+ *** 495,506 ****
+   	phy_off();
+   
+   	otg_put_transceiver(musb->xceiv);
+ ! 	usb_nop_xceiv_unregister();
+   
+   	return 0;
+   }
+   
+   static const struct musb_platform_ops davinci_ops = {
+   	.init		= davinci_musb_init,
+   	.exit		= davinci_musb_exit,
+   
+ --- 495,508 ----
+   	phy_off();
+   
+   	otg_put_transceiver(musb->xceiv);
+ ! 	usb_nop_xceiv_unregister(musb->id);
+   
+   	return 0;
+   }
+   
+   static const struct musb_platform_ops davinci_ops = {
+ + 	.fifo_mode	= 2,
+ + 	.flags		= MUSB_GLUE_EP_ADDR_FLAT_MAPPING | MUSB_GLUE_DMA_CPPI,
+   	.init		= davinci_musb_init,
+   	.exit		= davinci_musb_exit,
+   
+ ***************
+ *** 510,515 ****
+ --- 512,523 ----
+   	.set_mode	= davinci_musb_set_mode,
+   
+   	.set_vbus	= davinci_musb_set_vbus,
+ + 
+ + 	.read_fifo	= musb_read_fifo,
+ + 	.write_fifo	= musb_write_fifo,
+ + 
+ + 	.dma_controller_create = cppi_dma_controller_create,
+ + 	.dma_controller_destroy = cppi_dma_controller_destroy,
+   };
+   
+   static u64 davinci_dmamask = DMA_BIT_MASK(32);
+ diff -crN linux-3.2.1_o/drivers/usb/musb/Kconfig linux-3.2.1/drivers/usb/musb/Kconfig
+ *** linux-3.2.1_o/drivers/usb/musb/Kconfig	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/musb/Kconfig	2014-11-25 13:19:16.624098740 +0900
+ ***************
+ *** 5,18 ****
+   
+   # (M)HDRC = (Multipoint) Highspeed Dual-Role Controller
+   config USB_MUSB_HDRC
+   	depends on USB && USB_GADGET
+ - 	depends on (ARM || (BF54x && !BF544) || (BF52x && !BF522 && !BF523))
+   	select NOP_USB_XCEIV if (ARCH_DAVINCI || MACH_OMAP3EVM || BLACKFIN)
+   	select TWL4030_USB if MACH_OMAP_3430SDP
+   	select TWL6030_USB if MACH_OMAP_4430SDP || MACH_OMAP4_PANDA
+   	select USB_OTG_UTILS
+   	select USB_GADGET_DUALSPEED
+ - 	tristate 'Inventra Highspeed Dual Role Controller (TI, ADI, ...)'
+   	help
+   	  Say Y here if your system has a dual role high speed USB
+   	  controller based on the Mentor Graphics silicon IP.  Then
+ --- 5,18 ----
+   
+   # (M)HDRC = (Multipoint) Highspeed Dual-Role Controller
+   config USB_MUSB_HDRC
+ + 	tristate 'Inventra Highspeed Dual Role Controller (TI, ADI, ...)'
+   	depends on USB && USB_GADGET
+   	select NOP_USB_XCEIV if (ARCH_DAVINCI || MACH_OMAP3EVM || BLACKFIN)
+ + 	select NOP_USB_XCEIV if (SOC_OMAPTI81XX || SOC_OMAPAM33XX)
+   	select TWL4030_USB if MACH_OMAP_3430SDP
+   	select TWL6030_USB if MACH_OMAP_4430SDP || MACH_OMAP4_PANDA
+   	select USB_OTG_UTILS
+   	select USB_GADGET_DUALSPEED
+   	help
+   	  Say Y here if your system has a dual role high speed USB
+   	  controller based on the Mentor Graphics silicon IP.  Then
+ ***************
+ *** 31,110 ****
+   	  To compile this driver as a module, choose M here; the
+   	  module will be called "musb-hdrc".
+   
+ ! choice
+ ! 	prompt "Platform Glue Layer"
+ ! 	depends on USB_MUSB_HDRC
+   
+ ! config USB_MUSB_DAVINCI
+   	tristate "DaVinci"
+ ! 	depends on ARCH_DAVINCI_DMx
+   
+ ! config USB_MUSB_DA8XX
+   	tristate "DA8xx/OMAP-L1x"
+ ! 	depends on ARCH_DAVINCI_DA8XX
+   
+ ! config USB_MUSB_TUSB6010
+   	tristate "TUSB6010"
+ ! 	depends on ARCH_OMAP
+   
+ ! config USB_MUSB_OMAP2PLUS
+   	tristate "OMAP2430 and onwards"
+ ! 	depends on ARCH_OMAP2PLUS
+   
+ ! config USB_MUSB_AM35X
+   	tristate "AM35x"
+ ! 	depends on ARCH_OMAP
+   
+ ! config USB_MUSB_BLACKFIN
+   	tristate "Blackfin"
+ ! 	depends on (BF54x && !BF544) || (BF52x && ! BF522 && !BF523)
+   
+ ! config USB_MUSB_UX500
+   	tristate "U8500 and U5500"
+ ! 	depends on (ARCH_U8500 && AB8500_USB)
+   
+   endchoice
+   
+   config MUSB_PIO_ONLY
+   	bool 'Disable DMA (always use PIO)'
+ ! 	depends on USB_MUSB_HDRC
+ ! 	default USB_MUSB_TUSB6010 || USB_MUSB_DA8XX || USB_MUSB_AM35X
+   	help
+   	  All data is copied between memory and FIFO by the CPU.
+   	  DMA controllers are ignored.
+   
+ ! 	  Do not select 'n' here unless DMA support for your SOC or board
+ ! 	  is unavailable (or unstable).  When DMA is enabled at compile time,
+ ! 	  you can still disable it at run time using the "use_dma=n" module
+ ! 	  parameter.
+ ! 
+ ! config USB_UX500_DMA
+ ! 	bool
+ ! 	depends on USB_MUSB_HDRC && !MUSB_PIO_ONLY
+ ! 	default USB_MUSB_UX500
+ ! 	help
+ ! 	  Enable DMA transfers on UX500 platforms.
+   
+   config USB_INVENTRA_DMA
+   	bool
+ ! 	depends on USB_MUSB_HDRC && !MUSB_PIO_ONLY
+ ! 	default USB_MUSB_OMAP2PLUS || USB_MUSB_BLACKFIN
+ ! 	help
+ ! 	  Enable DMA transfers using Mentor's engine.
+   
+   config USB_TI_CPPI_DMA
+   	bool
+ ! 	depends on USB_MUSB_HDRC && !MUSB_PIO_ONLY
+ ! 	default USB_MUSB_DAVINCI
+ ! 	help
+ ! 	  Enable DMA transfers when TI CPPI DMA is available.
+   
+   config USB_TUSB_OMAP_DMA
+   	bool
+ ! 	depends on USB_MUSB_HDRC && !MUSB_PIO_ONLY
+ ! 	depends on USB_MUSB_TUSB6010
+ ! 	depends on ARCH_OMAP
+ ! 	default y
+ ! 	help
+ ! 	  Enable DMA transfers on TUSB 6010 when OMAP DMA is available.
+   
+ --- 31,194 ----
+   	  To compile this driver as a module, choose M here; the
+   	  module will be called "musb-hdrc".
+   
+ ! if USB_MUSB_HDRC
+   
+ ! comment "Platform Glue Layer"
+ ! 
+ ! config USB_MUSB_DAVINCI_GLUE
+ ! 	select USB_MUSB_DAVINCI
+   	tristate "DaVinci"
+ ! 	depends on ARCH_DAVINCI_DMx && USB_MUSB_HDRC
+   
+ ! config USB_MUSB_DA8XX_GLUE
+ ! 	select USB_MUSB_DA8XX
+   	tristate "DA8xx/OMAP-L1x"
+ ! 	depends on ARCH_DAVINCI_DA8XX && USB_MUSB_HDRC
+   
+ ! config USB_MUSB_TUSB6010_GLUE
+ ! 	select USB_MUSB_TUSB6010
+   	tristate "TUSB6010"
+ ! 	depends on ARCH_OMAP && USB_MUSB_HDRC
+   
+ ! config USB_MUSB_OMAP2PLUS_GLUE
+ ! 	select USB_MUSB_OMAP2PLUS
+   	tristate "OMAP2430 and onwards"
+ ! 	depends on ARCH_OMAP2PLUS && USB_MUSB_HDRC
+   
+ ! config USB_MUSB_AM35X_GLUE
+ ! 	select USB_MUSB_AM35X
+   	tristate "AM35x"
+ ! 	depends on ARCH_OMAP && USB_MUSB_HDRC
+   
+ ! config USB_MUSB_TI81XX_GLUE
+ ! 	select USB_MUSB_TI81XX
+ ! 	tristate "TI81XX onward"
+ ! 	depends on (SOC_OMAPTI81XX || SOC_OMAPAM33XX) && USB_MUSB_HDRC
+ ! 
+ ! config USB_MUSB_BLACKFIN_GLUE
+ ! 	select USB_MUSB_BLACKFIN
+   	tristate "Blackfin"
+ ! 	depends on (BF54x && !BF544) || (BF52x && ! BF522 && !BF523) && USB_MUSB_HDRC
+   
+ ! config USB_MUSB_UX500_GLUE
+ ! 	select USB_MUSB_UX500
+   	tristate "U8500 and U5500"
+ ! 	depends on (ARCH_U8500 && AB8500_USB) && USB_MUSB_HDRC
+ ! 
+ ! config USB_MUSB_DAVINCI
+ ! 	bool
+ ! 	default n
+ ! config USB_MUSB_DA8XX
+ ! 	bool
+ ! 	default n
+ ! config USB_MUSB_TUSB6010
+ ! 	bool
+ ! 	default n
+ ! config USB_MUSB_OMAP2PLUS
+ ! 	bool
+ ! 	default n
+ ! config USB_MUSB_AM35X
+ ! 	bool
+ ! 	default n
+ ! config USB_MUSB_TI81XX
+ ! 	bool
+ ! 	default n
+ ! config USB_MUSB_BLACKFIN
+ ! 	bool
+ ! 	default n
+ ! config USB_MUSB_UX500
+ ! 	bool
+ ! 	default n
+ ! 
+ ! choice
+ ! 	prompt 'MUSB DMA mode'
+ ! 	depends on !MUSB_PIO_ONLY
+ ! 	default USB_UX500_DMA_HW if USB_MUSB_UX500
+ ! 	default USB_INVENTRA_DMA_HW if USB_MUSB_OMAP2PLUS || USB_MUSB_BLACKFIN
+ ! 	default USB_TI_CPPI_DMA_HW if USB_MUSB_DAVINCI
+ ! 	default USB_TUSB_OMAP_DMA_HW if USB_MUSB_TUSB6010
+ ! 	default USB_TI_CPPI41_DMA_HW if USB_MUSB_DA8XX || USB_MUSB_AM35X || USB_MUSB_TI81XX
+ ! 	help
+ ! 	  Unfortunately, only one option can be enabled here. Ideally one
+ ! 	  should be able to build all these drivers into one kernel to
+ ! 	  allow using DMA on multiplatform kernels.
+ ! 
+ ! config USB_UX500_DMA_HW
+ ! 	tristate 'ST Ericsson U8500 and U5500'
+ ! 	select USB_UX500_DMA
+ ! 	depends on USB_MUSB_UX500
+ ! 	help
+ ! 	  Enable DMA transfers on UX500 platforms.
+ ! 
+ ! config USB_INVENTRA_DMA_HW
+ ! 	tristate 'Inventra'
+ ! 	select USB_INVENTRA_DMA
+ ! 	depends on (USB_MUSB_OMAP2PLUS || USB_MUSB_BLACKFIN) && !USB_MUSB_AM35X
+ ! 	help
+ ! 	  Enable DMA transfers using Mentor's engine.
+ ! 
+ ! config USB_TI_CPPI_DMA_HW
+ ! 	tristate 'TI CPPI (Davinci)'
+ ! 	select USB_TI_CPPI_DMA
+ ! 	depends on USB_MUSB_DAVINCI
+ ! 	help
+ ! 	  Enable DMA transfers when TI CPPI DMA is available.
+ ! 
+ ! config USB_TI_CPPI41_DMA_HW
+ ! 	tristate 'TI CPPI4.1'
+ ! 	select USB_TI_CPPI41_DMA
+ ! 	depends on USB_MUSB_DA8XX || USB_MUSB_AM35X || USB_MUSB_TI81XX
+ ! 	select CPPI41
+ ! 	help
+ ! 	 Configure this option to include the CPPI 4.1 support,
+ ! 	 The CPPI 4.1 DMA engine integrated with musb controller
+ ! 	 accelarate the usb packet transmission and receception
+ ! 	 to/from musb endpoints.
+ ! 
+ ! config USB_TUSB_OMAP_DMA_HW
+ ! 	tristate 'TUSB 6010'
+ ! 	select USB_TUSB_OMAP_DMA
+ ! 	depends on USB_MUSB_TUSB6010
+ ! 	depends on ARCH_OMAP
+ ! 	help
+ ! 	  Enable DMA transfers on TUSB 6010 when OMAP DMA is available.
+   
+   endchoice
+   
+   config MUSB_PIO_ONLY
+   	bool 'Disable DMA (always use PIO)'
+ ! 	default USB_MUSB_TUSB6010 || USB_MUSB_DA8XX
+   	help
+   	  All data is copied between memory and FIFO by the CPU.
+   	  DMA controllers are ignored.
+   
+ ! 	  Select 'y' here if DMA support for your SOC or board
+ ! 	  is unavailable (or unstable). On CPPI 4.1 DMA based
+ ! 	  systems (AM335x, AM35x, and AM180x) DMA support is
+ ! 	  considered unstable and this option should be enabled
+ ! 	  in production systems so that DMA is disabled, unless DMA
+ ! 	  has been validated for all use cases. When DMA is enabled at
+ ! 	  compile time, you can still disable it at run time using the
+ ! 	  "use_dma=n" module parameter.
+   
+   config USB_INVENTRA_DMA
+   	bool
+ ! 	default n
+   
+   config USB_TI_CPPI_DMA
+   	bool
+ ! 	default n
+ ! 
+ ! config USB_TI_CPPI41_DMA
+ ! 	bool
+ ! 	default n
+   
+   config USB_TUSB_OMAP_DMA
+   	bool
+ ! 	default n
+ ! 
+ ! config USB_UX500_DMA
+ ! 	bool
+ ! 	default n
+   
+ + endif # USB_MUSB_HDRC
+ diff -crN linux-3.2.1_o/drivers/usb/musb/Makefile linux-3.2.1/drivers/usb/musb/Makefile
+ *** linux-3.2.1_o/drivers/usb/musb/Makefile	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/musb/Makefile	2014-11-25 13:19:16.627568385 +0900
+ ***************
+ *** 9,48 ****
+   musb_hdrc-y					+= musb_gadget_ep0.o musb_gadget.o
+   musb_hdrc-y					+= musb_virthub.o musb_host.o
+   musb_hdrc-$(CONFIG_DEBUG_FS)			+= musb_debugfs.o
+ ! 
+   # Hardware Glue Layer
+ ! obj-$(CONFIG_USB_MUSB_OMAP2PLUS)		+= omap2430.o
+ ! obj-$(CONFIG_USB_MUSB_AM35X)			+= am35x.o
+ ! obj-$(CONFIG_USB_MUSB_TUSB6010)			+= tusb6010.o
+ ! obj-$(CONFIG_USB_MUSB_DAVINCI)			+= davinci.o
+ ! obj-$(CONFIG_USB_MUSB_DA8XX)			+= da8xx.o
+ ! obj-$(CONFIG_USB_MUSB_BLACKFIN)			+= blackfin.o
+ ! obj-$(CONFIG_USB_MUSB_UX500)			+= ux500.o
+   
+   # the kconfig must guarantee that only one of the
+   # possible I/O schemes will be enabled at a time ...
+   # PIO only, or DMA (several potential schemes).
+   # though PIO is always there to back up DMA, and for ep0
+   
+ ! ifneq ($(CONFIG_MUSB_PIO_ONLY),y)
+ ! 
+ !   ifeq ($(CONFIG_USB_INVENTRA_DMA),y)
+ !     musb_hdrc-y			+= musbhsdma.o
+ ! 
+ !   else
+ !     ifeq ($(CONFIG_USB_TI_CPPI_DMA),y)
+ !       musb_hdrc-y		+= cppi_dma.o
+ ! 
+ !     else
+ !       ifeq ($(CONFIG_USB_TUSB_OMAP_DMA),y)
+ ! 	musb_hdrc-y		+= tusb6010_omap.o
+ ! 
+ !       else
+ !         ifeq ($(CONFIG_USB_UX500_DMA),y)
+ ! 	  musb_hdrc-y		+= ux500_dma.o
+ ! 
+ !         endif
+ !       endif
+ !     endif
+ !   endif
+ ! endif
+ --- 9,33 ----
+   musb_hdrc-y					+= musb_gadget_ep0.o musb_gadget.o
+   musb_hdrc-y					+= musb_virthub.o musb_host.o
+   musb_hdrc-$(CONFIG_DEBUG_FS)			+= musb_debugfs.o
+ ! musb_hdrc-$(CONFIG_PROC_FS)			+= musb_procfs.o
+   # Hardware Glue Layer
+ ! obj-$(CONFIG_USB_MUSB_OMAP2PLUS_GLUE)		+= omap2430.o
+ ! obj-$(CONFIG_USB_MUSB_AM35X_GLUE)		+= am35x.o
+ ! obj-$(CONFIG_USB_MUSB_TI81XX_GLUE)		+= ti81xx.o
+ ! obj-$(CONFIG_USB_MUSB_TUSB6010_GLUE)		+= tusb6010.o
+ ! obj-$(CONFIG_USB_MUSB_DAVINCI_GLUE)			+= davinci.o
+ ! obj-$(CONFIG_USB_MUSB_DA8XX_GLUE)			+= da8xx.o
+ ! obj-$(CONFIG_USB_MUSB_BLACKFIN_GLUE)		+= blackfin.o
+ ! obj-$(CONFIG_USB_MUSB_UX500_GLUE)			+= ux500.o
+   
+   # the kconfig must guarantee that only one of the
+   # possible I/O schemes will be enabled at a time ...
+   # PIO only, or DMA (several potential schemes).
+   # though PIO is always there to back up DMA, and for ep0
+   
+ ! obj-$(CONFIG_USB_INVENTRA_DMA_HW)		+= musbhsdma.o
+ ! obj-$(CONFIG_USB_TI_CPPI_DMA_HW)		+= cppi_dma.o
+ ! obj-$(CONFIG_USB_TI_CPPI41_DMA_HW)		+= cppi41dma.o
+ ! cppi41dma-y					+= cppi41.o cppi41_dma.o
+ ! obj-$(CONFIG_USB_TUSB_OMAP_DMA_HW)		+= tusb6010_omap.o
+ ! obj-$(CONFIG_USB_UX500_DMA_HW)			+= ux500_dma.o
+ diff -crN linux-3.2.1_o/drivers/usb/musb/musb_core.c linux-3.2.1/drivers/usb/musb/musb_core.c
+ *** linux-3.2.1_o/drivers/usb/musb/musb_core.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/musb/musb_core.c	2014-11-25 13:19:16.636057328 +0900
+ ***************
+ *** 102,108 ****
+   
+   #include "musb_core.h"
+   
+ - #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
+   
+   
+   #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
+ --- 102,107 ----
+ ***************
+ *** 120,125 ****
+ --- 119,128 ----
+   MODULE_LICENSE("GPL");
+   MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
+   
+ + u8 (*musb_readb)(const void __iomem *addr, unsigned offset);
+ + EXPORT_SYMBOL_GPL(musb_readb);
+ + void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data);
+ + EXPORT_SYMBOL_GPL(musb_writeb);
+   
+   /*-------------------------------------------------------------------------*/
+   
+ ***************
+ *** 131,136 ****
+ --- 134,177 ----
+   /*-------------------------------------------------------------------------*/
+   
+   #ifndef CONFIG_BLACKFIN
+ + 
+ + /*
+ +  * TUSB6010 doesn't allow 8-bit access; 16-bit access is the minimum.
+ +  */
+ + static inline u8 __tusb_musb_readb(const void __iomem *addr, unsigned offset)
+ + {
+ + 	u16 tmp;
+ + 	u8 val;
+ + 
+ + 	tmp = __raw_readw(addr + (offset & ~1));
+ + 	if (offset & 1)
+ + 		val = (tmp >> 8);
+ + 	else
+ + 		val = tmp & 0xff;
+ + 
+ + 	return val;
+ + }
+ + 
+ + static inline void __tusb_musb_writeb(void __iomem *addr, unsigned offset,
+ + 					u8 data)
+ + {
+ + 	u16 tmp;
+ + 
+ + 	tmp = __raw_readw(addr + (offset & ~1));
+ + 	if (offset & 1)
+ + 		tmp = (data << 8) | (tmp & 0xff);
+ + 	else
+ + 		tmp = (tmp & 0xff00) | data;
+ + 
+ + 	__raw_writew(tmp, addr + (offset & ~1));
+ + }
+ + 
+ + static inline u8 __musb_readb(const void __iomem *addr, unsigned offset)
+ + 	{ return readb(addr + offset); }
+ + 
+ + static inline void __musb_writeb(void __iomem *addr, unsigned offset, u8 data)
+ + 	{ writeb(data, addr + offset); }
+ + 
+   static int musb_ulpi_read(struct otg_transceiver *otg, u32 offset)
+   {
+   	void __iomem *addr = otg->io_priv;
+ ***************
+ *** 196,201 ****
+ --- 237,248 ----
+   	return 0;
+   }
+   #else
+ + static inline u8 __musb_readb(const void __iomem *addr, unsigned offset)
+ + 	{ return (u8) (bfin_read16(addr + offset)); }
+ + 
+ + static inline void __musb_writeb(void __iomem *addr, unsigned offset, u8 data)
+ + 	{ bfin_write16(addr + offset, (u16) data); }
+ + 
+   #define musb_ulpi_read		NULL
+   #define musb_ulpi_write		NULL
+   #endif
+ ***************
+ *** 205,214 ****
+   	.write = musb_ulpi_write,
+   };
+   
+ - /*-------------------------------------------------------------------------*/
+ - 
+ - #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN)
+ - 
+   /*
+    * Load an endpoint's FIFO
+    */
+ --- 252,257 ----
+ ***************
+ *** 249,256 ****
+   		writesb(fifo, src, len);
+   	}
+   }
+   
+ - #if !defined(CONFIG_USB_MUSB_AM35X)
+   /*
+    * Unload an endpoint's FIFO
+    */
+ --- 292,299 ----
+   		writesb(fifo, src, len);
+   	}
+   }
+ + EXPORT_SYMBOL_GPL(musb_write_fifo);
+   
+   /*
+    * Unload an endpoint's FIFO
+    */
+ ***************
+ *** 289,298 ****
+   		readsb(fifo, dst, len);
+   	}
+   }
+ ! #endif
+ ! 
+ ! #endif	/* normal PIO */
+ ! 
+   
+   /*-------------------------------------------------------------------------*/
+   
+ --- 332,338 ----
+   		readsb(fifo, dst, len);
+   	}
+   }
+ ! EXPORT_SYMBOL_GPL(musb_read_fifo);
+   
+   /*-------------------------------------------------------------------------*/
+   
+ ***************
+ *** 318,334 ****
+   
+   void musb_load_testpacket(struct musb *musb)
+   {
+ ! 	void __iomem	*regs = musb->endpoints[0].regs;
+ ! 
+ ! 	musb_ep_select(musb->mregs, 0);
+ ! 	musb_write_fifo(musb->control_ep,
+   			sizeof(musb_test_packet), musb_test_packet);
+ - 	musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
+   }
+   
+   /*-------------------------------------------------------------------------*/
+   
+   /*
+    * Handles OTG hnp timeouts, such as b_ase0_brst
+    */
+   void musb_otg_timer_func(unsigned long data)
+ --- 358,377 ----
+   
+   void musb_load_testpacket(struct musb *musb)
+   {
+ ! 	musb_ep_select(musb, musb->mregs, 0);
+ ! 	musb->ops->write_fifo(musb->control_ep,
+   			sizeof(musb_test_packet), musb_test_packet);
+   }
+   
+   /*-------------------------------------------------------------------------*/
+   
+   /*
+ +  * See also USB_OTG_1-3.pdf 6.6.5 Timers
+ +  * REVISIT: Are the other timers done in the hardware?
+ +  */
+ + #define TB_ASE0_BRST		100	/* Min 3.125 ms */
+ + 
+ + /*
+    * Handles OTG hnp timeouts, such as b_ase0_brst
+    */
+   void musb_otg_timer_func(unsigned long data)
+ ***************
+ *** 344,355 ****
+   		musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
+   		musb->is_active = 0;
+   		break;
+ - 	case OTG_STATE_A_SUSPEND:
+   	case OTG_STATE_A_WAIT_BCON:
+ ! 		dev_dbg(musb->controller, "HNP: %s timeout\n",
+ ! 			otg_state_string(musb->xceiv->state));
+ ! 		musb_platform_set_vbus(musb, 0);
+ ! 		musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
+   		break;
+   	default:
+   		dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
+ --- 387,395 ----
+   		musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
+   		musb->is_active = 0;
+   		break;
+   	case OTG_STATE_A_WAIT_BCON:
+ ! 		dev_dbg(musb->controller, "HNP: a_wait_bcon timeout; back to a_host\n");
+ ! 		musb_hnp_stop(musb);
+   		break;
+   	default:
+   		dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
+ ***************
+ *** 360,366 ****
+   }
+   
+   /*
+ !  * Stops the HNP transition. Caller must take care of locking.
+    */
+   void musb_hnp_stop(struct musb *musb)
+   {
+ --- 400,406 ----
+   }
+   
+   /*
+ !  * Stops the B-device HNP state. Caller must take care of locking.
+    */
+   void musb_hnp_stop(struct musb *musb)
+   {
+ ***************
+ *** 368,380 ****
+   	void __iomem	*mbase = musb->mregs;
+   	u8	reg;
+   
+ - 	dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state));
+ - 
+   	switch (musb->xceiv->state) {
+   	case OTG_STATE_A_PERIPHERAL:
+   		musb_g_disconnect(musb);
+ ! 		dev_dbg(musb->controller, "HNP: back to %s\n",
+ ! 			otg_state_string(musb->xceiv->state));
+   		break;
+   	case OTG_STATE_B_HOST:
+   		dev_dbg(musb->controller, "HNP: Disabling HR\n");
+ --- 408,422 ----
+   	void __iomem	*mbase = musb->mregs;
+   	u8	reg;
+   
+   	switch (musb->xceiv->state) {
+   	case OTG_STATE_A_PERIPHERAL:
+ + 	case OTG_STATE_A_WAIT_VFALL:
+ + 	case OTG_STATE_A_WAIT_BCON:
+ + 		dev_dbg(musb->controller, "HNP: Switching back to A-host\n");
+   		musb_g_disconnect(musb);
+ ! 		musb->xceiv->state = OTG_STATE_A_IDLE;
+ ! 		MUSB_HST_MODE(musb);
+ ! 		musb->is_active = 0;
+   		break;
+   	case OTG_STATE_B_HOST:
+   		dev_dbg(musb->controller, "HNP: Disabling HR\n");
+ ***************
+ *** 427,433 ****
+   		handled = IRQ_HANDLED;
+   		dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state));
+   
+ ! 		if (devctl & MUSB_DEVCTL_HM) {
+   			void __iomem *mbase = musb->mregs;
+   
+   			switch (musb->xceiv->state) {
+ --- 469,475 ----
+   		handled = IRQ_HANDLED;
+   		dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state));
+   
+ ! 		if (is_host_enabled(musb) && (devctl & MUSB_DEVCTL_HM)) {
+   			void __iomem *mbase = musb->mregs;
+   
+   			switch (musb->xceiv->state) {
+ ***************
+ *** 470,495 ****
+   		} else {
+   			switch (musb->xceiv->state) {
+   			case OTG_STATE_A_SUSPEND:
+ ! 				/* possibly DISCONNECT is upcoming */
+ ! 				musb->xceiv->state = OTG_STATE_A_HOST;
+ ! 				usb_hcd_resume_root_hub(musb_to_hcd(musb));
+   				break;
+   			case OTG_STATE_B_WAIT_ACON:
+   			case OTG_STATE_B_PERIPHERAL:
+ ! 				/* disconnect while suspended?  we may
+ ! 				 * not get a disconnect irq...
+ ! 				 */
+ ! 				if ((devctl & MUSB_DEVCTL_VBUS)
+   						!= (3 << MUSB_DEVCTL_VBUS_SHIFT)
+ ! 						) {
+ ! 					musb->int_usb |= MUSB_INTR_DISCONNECT;
+ ! 					musb->int_usb &= ~MUSB_INTR_SUSPEND;
+ ! 					break;
+   				}
+ - 				musb_g_resume(musb);
+   				break;
+   			case OTG_STATE_B_IDLE:
+ ! 				musb->int_usb &= ~MUSB_INTR_SUSPEND;
+   				break;
+   			default:
+   				WARNING("bogus %s RESUME (%s)\n",
+ --- 512,545 ----
+   		} else {
+   			switch (musb->xceiv->state) {
+   			case OTG_STATE_A_SUSPEND:
+ ! 				if (is_host_enabled(musb)) {
+ ! 					/* possibly DISCONNECT is upcoming */
+ ! 					musb->xceiv->state = OTG_STATE_A_HOST;
+ ! 					usb_hcd_resume_root_hub(
+ ! 							musb_to_hcd(musb));
+ ! 				}
+   				break;
+   			case OTG_STATE_B_WAIT_ACON:
+   			case OTG_STATE_B_PERIPHERAL:
+ ! 				if (is_peripheral_enabled(musb)) {
+ ! 					/* disconnect while suspended?  we may
+ ! 					 * not get a disconnect irq...
+ ! 					 */
+ ! 					if ((devctl & MUSB_DEVCTL_VBUS)
+   						!= (3 << MUSB_DEVCTL_VBUS_SHIFT)
+ ! 							) {
+ ! 						musb->int_usb |=
+ ! 							MUSB_INTR_DISCONNECT;
+ ! 						musb->int_usb &=
+ ! 							~MUSB_INTR_SUSPEND;
+ ! 						break;
+ ! 					}
+ ! 					musb_g_resume(musb);
+   				}
+   				break;
+   			case OTG_STATE_B_IDLE:
+ ! 				if (is_peripheral_enabled(musb))
+ ! 					musb->int_usb &= ~MUSB_INTR_SUSPEND;
+   				break;
+   			default:
+   				WARNING("bogus %s RESUME (%s)\n",
+ ***************
+ *** 500,506 ****
+   	}
+   
+   	/* see manual for the order of the tests */
+ ! 	if (int_usb & MUSB_INTR_SESSREQ) {
+   		void __iomem *mbase = musb->mregs;
+   
+   		if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
+ --- 550,556 ----
+   	}
+   
+   	/* see manual for the order of the tests */
+ ! 	if (is_host_enabled(musb) && (int_usb & MUSB_INTR_SESSREQ)) {
+   		void __iomem *mbase = musb->mregs;
+   
+   		if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
+ ***************
+ *** 528,534 ****
+   		handled = IRQ_HANDLED;
+   	}
+   
+ ! 	if (int_usb & MUSB_INTR_VBUSERROR) {
+   		int	ignore = 0;
+   
+   		/* During connection as an A-Device, we may see a short
+ --- 578,585 ----
+   		handled = IRQ_HANDLED;
+   	}
+   
+ ! 	if (is_host_enabled(musb) && (int_usb & MUSB_INTR_VBUSERROR)) {
+ ! 		struct usb_hcd *hcd = musb_to_hcd(musb);
+   		int	ignore = 0;
+   
+   		/* During connection as an A-Device, we may see a short
+ ***************
+ *** 568,573 ****
+ --- 619,631 ----
+   				musb->port1_status |=
+   					  USB_PORT_STAT_OVERCURRENT
+   					| (USB_PORT_STAT_C_OVERCURRENT << 16);
+ + 
+ + 				if (hcd->status_urb)
+ + 					usb_hcd_poll_rh_status(hcd);
+ + 				else
+ + 					usb_hcd_resume_root_hub(hcd);
+ + 
+ + 				MUSB_HST_MODE(musb);
+   			}
+   			break;
+   		default:
+ ***************
+ *** 604,625 ****
+   		handled = IRQ_HANDLED;
+   
+   		switch (musb->xceiv->state) {
+ - 		case OTG_STATE_A_PERIPHERAL:
+ - 			/* We also come here if the cable is removed, since
+ - 			 * this silicon doesn't report ID-no-longer-grounded.
+ - 			 *
+ - 			 * We depend on T(a_wait_bcon) to shut us down, and
+ - 			 * hope users don't do anything dicey during this
+ - 			 * undesired detour through A_WAIT_BCON.
+ - 			 */
+ - 			musb_hnp_stop(musb);
+ - 			usb_hcd_resume_root_hub(musb_to_hcd(musb));
+ - 			musb_root_disconnect(musb);
+ - 			musb_platform_try_idle(musb, jiffies
+ - 					+ msecs_to_jiffies(musb->a_wait_bcon
+ - 						? : OTG_TIME_A_WAIT_BCON));
+ - 
+ - 			break;
+   		case OTG_STATE_B_IDLE:
+   			if (!musb->is_active)
+   				break;
+ --- 662,667 ----
+ ***************
+ *** 627,638 ****
+   			musb_g_suspend(musb);
+   			musb->is_active = is_otg_enabled(musb)
+   					&& musb->xceiv->gadget->b_hnp_enable;
+ ! 			if (musb->is_active) {
+   				musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
+   				dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
+   				mod_timer(&musb->otg_timer, jiffies
+ ! 					+ msecs_to_jiffies(
+ ! 							OTG_TIME_B_ASE0_BRST));
+   			}
+   			break;
+   		case OTG_STATE_A_WAIT_BCON:
+ --- 669,679 ----
+   			musb_g_suspend(musb);
+   			musb->is_active = is_otg_enabled(musb)
+   					&& musb->xceiv->gadget->b_hnp_enable;
+ ! 			if (is_otg_enabled(musb) && musb->is_active) {
+   				musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
+   				dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
+   				mod_timer(&musb->otg_timer, jiffies
+ ! 					+ msecs_to_jiffies(TB_ASE0_BRST));
+   			}
+   			break;
+   		case OTG_STATE_A_WAIT_BCON:
+ ***************
+ *** 649,654 ****
+ --- 690,702 ----
+   			/* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
+   			dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
+   			break;
+ + 		case OTG_STATE_A_PERIPHERAL:
+ + 			/*
+ + 			 * We cannot stop HNP here, devctl BDEVICE might be
+ + 			 * still set.
+ + 			 */
+ + 			if (is_otg_enabled(musb))
+ + 				break;
+   		default:
+   			/* "should not happen" */
+   			musb->is_active = 0;
+ ***************
+ *** 656,662 ****
+   		}
+   	}
+   
+ ! 	if (int_usb & MUSB_INTR_CONNECT) {
+   		struct usb_hcd *hcd = musb_to_hcd(musb);
+   
+   		handled = IRQ_HANDLED;
+ --- 704,710 ----
+   		}
+   	}
+   
+ ! 	if (is_host_enabled(musb) && (int_usb & MUSB_INTR_CONNECT)) {
+   		struct usb_hcd *hcd = musb_to_hcd(musb);
+   
+   		handled = IRQ_HANDLED;
+ ***************
+ *** 665,677 ****
+   
+   		musb->ep0_stage = MUSB_EP0_START;
+   
+ ! 		/* flush endpoints when transitioning from Device Mode */
+ ! 		if (is_peripheral_active(musb)) {
+ ! 			/* REVISIT HNP; just force disconnect */
+ ! 		}
+ ! 		musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask);
+ ! 		musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe);
+ ! 		musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
+   		musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
+   					|USB_PORT_STAT_HIGH_SPEED
+   					|USB_PORT_STAT_ENABLE
+ --- 713,728 ----
+   
+   		musb->ep0_stage = MUSB_EP0_START;
+   
+ ! 		if (is_otg_enabled(musb)) {
+ ! 			/* flush endpoints when transitioning from DeviceMode */
+ ! 			if (is_peripheral_active(musb)) {
+ ! 				/* REVISIT HNP; just force disconnect */
+ ! 			}
+ ! 			musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask);
+ ! 			musb_writew(musb->mregs, MUSB_INTRRXE,
+ ! 						musb->epmask & 0xfffe);
+ ! 			musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
+ ! 		}
+   		musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
+   					|USB_PORT_STAT_HIGH_SPEED
+   					|USB_PORT_STAT_ENABLE
+ ***************
+ *** 683,705 ****
+   		if (devctl & MUSB_DEVCTL_LSDEV)
+   			musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
+   
+   		/* indicate new connection to OTG machine */
+   		switch (musb->xceiv->state) {
+   		case OTG_STATE_B_PERIPHERAL:
+   			if (int_usb & MUSB_INTR_SUSPEND) {
+   				dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
+   				int_usb &= ~MUSB_INTR_SUSPEND;
+ - 				goto b_host;
+   			} else
+   				dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
+   			break;
+   		case OTG_STATE_B_WAIT_ACON:
+ ! 			dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
+ ! b_host:
+   			musb->xceiv->state = OTG_STATE_B_HOST;
+   			hcd->self.is_b_host = 1;
+ - 			musb->ignore_disconnect = 0;
+ - 			del_timer(&musb->otg_timer);
+   			break;
+   		default:
+   			if ((devctl & MUSB_DEVCTL_VBUS)
+ --- 734,761 ----
+   		if (devctl & MUSB_DEVCTL_LSDEV)
+   			musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
+   
+ + 		if (hcd->status_urb)
+ + 			usb_hcd_poll_rh_status(hcd);
+ + 		else
+ + 			usb_hcd_resume_root_hub(hcd);
+ + 
+ + 		MUSB_HST_MODE(musb);
+ + 
+   		/* indicate new connection to OTG machine */
+   		switch (musb->xceiv->state) {
+   		case OTG_STATE_B_PERIPHERAL:
+   			if (int_usb & MUSB_INTR_SUSPEND) {
+   				dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
+ + 				musb->xceiv->state = OTG_STATE_B_HOST;
+ + 				hcd->self.is_b_host = 1;
+   				int_usb &= ~MUSB_INTR_SUSPEND;
+   			} else
+   				dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
+   			break;
+   		case OTG_STATE_B_WAIT_ACON:
+ ! 			dev_dbg(musb->controller, "HNP: Waiting to switch to b_host state\n");
+   			musb->xceiv->state = OTG_STATE_B_HOST;
+   			hcd->self.is_b_host = 1;
+   			break;
+   		default:
+   			if ((devctl & MUSB_DEVCTL_VBUS)
+ ***************
+ *** 710,722 ****
+   			break;
+   		}
+   
+ - 		/* poke the root hub */
+ - 		MUSB_HST_MODE(musb);
+ - 		if (hcd->status_urb)
+ - 			usb_hcd_poll_rh_status(hcd);
+ - 		else
+ - 			usb_hcd_resume_root_hub(hcd);
+ - 
+   		dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
+   				otg_state_string(musb->xceiv->state), devctl);
+   	}
+ --- 766,771 ----
+ ***************
+ *** 730,762 ****
+   		switch (musb->xceiv->state) {
+   		case OTG_STATE_A_HOST:
+   		case OTG_STATE_A_SUSPEND:
+ ! 			usb_hcd_resume_root_hub(musb_to_hcd(musb));
+ ! 			musb_root_disconnect(musb);
+ ! 			if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
+ ! 				musb_platform_try_idle(musb, jiffies
+   					+ msecs_to_jiffies(musb->a_wait_bcon));
+   			break;
+   		case OTG_STATE_B_HOST:
+ ! 			/* REVISIT this behaves for "real disconnect"
+ ! 			 * cases; make sure the other transitions from
+ ! 			 * from B_HOST act right too.  The B_HOST code
+ ! 			 * in hnp_stop() is currently not used...
+ ! 			 */
+ ! 			musb_root_disconnect(musb);
+ ! 			musb_to_hcd(musb)->self.is_b_host = 0;
+ ! 			musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
+ ! 			MUSB_DEV_MODE(musb);
+ ! 			musb_g_disconnect(musb);
+   			break;
+   		case OTG_STATE_A_PERIPHERAL:
+ ! 			musb_hnp_stop(musb);
+ ! 			musb_root_disconnect(musb);
+   			/* FALLTHROUGH */
+   		case OTG_STATE_B_WAIT_ACON:
+   			/* FALLTHROUGH */
+   		case OTG_STATE_B_PERIPHERAL:
+   		case OTG_STATE_B_IDLE:
+ ! 			musb_g_disconnect(musb);
+   			break;
+   		default:
+   			WARNING("unhandled DISCONNECT transition (%s)\n",
+ --- 779,816 ----
+   		switch (musb->xceiv->state) {
+   		case OTG_STATE_A_HOST:
+   		case OTG_STATE_A_SUSPEND:
+ ! 			if (is_host_enabled(musb)) {
+ ! 				usb_hcd_resume_root_hub(musb_to_hcd(musb));
+ ! 				musb_root_disconnect(musb);
+ ! 				if (musb->a_wait_bcon != 0 &&
+ ! 						is_otg_enabled(musb))
+ ! 					musb_platform_try_idle(musb, jiffies
+   					+ msecs_to_jiffies(musb->a_wait_bcon));
+ + 			}
+   			break;
+   		case OTG_STATE_B_HOST:
+ ! 			if (is_otg_enabled(musb))
+ ! 				musb_hnp_stop(musb);
+   			break;
+   		case OTG_STATE_A_PERIPHERAL:
+ ! 			if (is_otg_enabled(musb)) {
+ ! 				musb_hnp_stop(musb);
+ ! 				musb_root_disconnect(musb);
+ ! 			}
+   			/* FALLTHROUGH */
+   		case OTG_STATE_B_WAIT_ACON:
+ + 			if (!is_otg_enabled(musb))
+ + 				break;
+   			/* FALLTHROUGH */
+   		case OTG_STATE_B_PERIPHERAL:
+   		case OTG_STATE_B_IDLE:
+ ! 			if (is_peripheral_enabled(musb)) {
+ ! 				printk(KERN_INFO "musb %s gadget disconnected.\n",
+ ! 					musb->gadget_driver
+ ! 					? musb->gadget_driver->driver.name
+ ! 					: "");
+ ! 				musb_g_disconnect(musb);
+ ! 			}
+   			break;
+   		default:
+   			WARNING("unhandled DISCONNECT transition (%s)\n",
+ ***************
+ *** 770,776 ****
+   	 */
+   	if (int_usb & MUSB_INTR_RESET) {
+   		handled = IRQ_HANDLED;
+ ! 		if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
+   			/*
+   			 * Looks like non-HS BABBLE can be ignored, but
+   			 * HS BABBLE is an error condition. For HS the solution
+ --- 824,830 ----
+   	 */
+   	if (int_usb & MUSB_INTR_RESET) {
+   		handled = IRQ_HANDLED;
+ ! 		if (is_host_enabled(musb) && (devctl & MUSB_DEVCTL_HM) != 0) {
+   			/*
+   			 * Looks like non-HS BABBLE can be ignored, but
+   			 * HS BABBLE is an error condition. For HS the solution
+ ***************
+ *** 784,819 ****
+   				ERR("Stopping host session -- babble\n");
+   				musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
+   			}
+ ! 		} else if (is_peripheral_capable()) {
+   			dev_dbg(musb->controller, "BUS RESET as %s\n",
+   				otg_state_string(musb->xceiv->state));
+   			switch (musb->xceiv->state) {
+   			case OTG_STATE_A_SUSPEND:
+ ! 				/* We need to ignore disconnect on suspend
+ ! 				 * otherwise tusb 2.0 won't reconnect after a
+ ! 				 * power cycle, which breaks otg compliance.
+ ! 				 */
+ ! 				musb->ignore_disconnect = 1;
+ ! 				musb_g_reset(musb);
+   				/* FALLTHROUGH */
+   			case OTG_STATE_A_WAIT_BCON:	/* OPT TD.4.7-900ms */
+ ! 				/* never use invalid T(a_wait_bcon) */
+ ! 				dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
+ ! 					otg_state_string(musb->xceiv->state),
+ ! 					TA_WAIT_BCON(musb));
+ ! 				mod_timer(&musb->otg_timer, jiffies
+ ! 					+ msecs_to_jiffies(TA_WAIT_BCON(musb)));
+   				break;
+   			case OTG_STATE_A_PERIPHERAL:
+ ! 				musb->ignore_disconnect = 0;
+ ! 				del_timer(&musb->otg_timer);
+ ! 				musb_g_reset(musb);
+   				break;
+   			case OTG_STATE_B_WAIT_ACON:
+ ! 				dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
+   					otg_state_string(musb->xceiv->state));
+ ! 				musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
+ ! 				musb_g_reset(musb);
+   				break;
+   			case OTG_STATE_B_IDLE:
+   				musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
+ --- 838,882 ----
+   				ERR("Stopping host session -- babble\n");
+   				musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
+   			}
+ ! 		} else if (is_peripheral_enabled(musb)) {
+   			dev_dbg(musb->controller, "BUS RESET as %s\n",
+   				otg_state_string(musb->xceiv->state));
+   			switch (musb->xceiv->state) {
+   			case OTG_STATE_A_SUSPEND:
+ ! 				if (is_otg_enabled(musb)) {
+ ! 					/* We need to ignore disconnect on
+ ! 					 * suspend otherwise tusb 2.0 won't
+ ! 					 * reconnect after a power cycle,
+ ! 					 * which breaks otg compliance.
+ ! 					 */
+ ! 					musb->ignore_disconnect = 1;
+ ! 					musb_g_reset(musb);
+ ! 				} else {
+ ! 					break;
+ ! 				}
+   				/* FALLTHROUGH */
+   			case OTG_STATE_A_WAIT_BCON:	/* OPT TD.4.7-900ms */
+ ! 				if (is_otg_enabled(musb)) {
+ ! 					dev_dbg(musb->controller,
+ ! 					"HNP: Setting timer as %s\n",
+ ! 					otg_state_string(musb->xceiv->state));
+ ! 					mod_timer(&musb->otg_timer, jiffies
+ ! 						+ msecs_to_jiffies(100));
+ ! 				}
+   				break;
+   			case OTG_STATE_A_PERIPHERAL:
+ ! 				if (is_otg_enabled(musb))
+ ! 					musb_hnp_stop(musb);
+   				break;
+   			case OTG_STATE_B_WAIT_ACON:
+ ! 				if (is_otg_enabled(musb)) {
+ ! 					dev_dbg(musb->controller,
+ ! 					"HNP: RESET (%s), to b_peripheral\n",
+   					otg_state_string(musb->xceiv->state));
+ ! 					musb->xceiv->state =
+ ! 						OTG_STATE_B_PERIPHERAL;
+ ! 					musb_g_reset(musb);
+ ! 				}
+   				break;
+   			case OTG_STATE_B_IDLE:
+   				musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
+ ***************
+ *** 906,912 ****
+   
+   	musb->is_active = 0;
+   	devctl = musb_readb(regs, MUSB_DEVCTL);
+ - 	devctl &= ~MUSB_DEVCTL_SESSION;
+   
+   	if (is_otg_enabled(musb)) {
+   		/* session started after:
+ --- 969,974 ----
+ ***************
+ *** 930,936 ****
+   	musb_platform_enable(musb);
+   	musb_writeb(regs, MUSB_DEVCTL, devctl);
+   }
+ ! 
+   
+   static void musb_generic_disable(struct musb *musb)
+   {
+ --- 992,998 ----
+   	musb_platform_enable(musb);
+   	musb_writeb(regs, MUSB_DEVCTL, devctl);
+   }
+ ! EXPORT_SYMBOL(musb_start);
+   
+   static void musb_generic_disable(struct musb *musb)
+   {
+ ***************
+ *** 1000,1039 ****
+   /*-------------------------------------------------------------------------*/
+   
+   /*
+ -  * The silicon either has hard-wired endpoint configurations, or else
+ -  * "dynamic fifo" sizing.  The driver has support for both, though at this
+ -  * writing only the dynamic sizing is very well tested.   Since we switched
+ -  * away from compile-time hardware parameters, we can no longer rely on
+ -  * dead code elimination to leave only the relevant one in the object file.
+ -  *
+ -  * We don't currently use dynamic fifo setup capability to do anything
+ -  * more than selecting one of a bunch of predefined configurations.
+ -  */
+ - #if defined(CONFIG_USB_MUSB_TUSB6010)			\
+ - 	|| defined(CONFIG_USB_MUSB_TUSB6010_MODULE)	\
+ - 	|| defined(CONFIG_USB_MUSB_OMAP2PLUS)		\
+ - 	|| defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE)	\
+ - 	|| defined(CONFIG_USB_MUSB_AM35X)		\
+ - 	|| defined(CONFIG_USB_MUSB_AM35X_MODULE)
+ - static ushort __initdata fifo_mode = 4;
+ - #elif defined(CONFIG_USB_MUSB_UX500)			\
+ - 	|| defined(CONFIG_USB_MUSB_UX500_MODULE)
+ - static ushort __initdata fifo_mode = 5;
+ - #else
+ - static ushort __initdata fifo_mode = 2;
+ - #endif
+ - 
+ - /* "modprobe ... fifo_mode=1" etc */
+ - module_param(fifo_mode, ushort, 0);
+ - MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
+ - 
+ - /*
+    * tables defining fifo_mode values.  define more if you like.
+    * for host side, make sure both halves of ep1 are set up.
+    */
+   
+   /* mode 0 - fits in 2KB */
+ ! static struct musb_fifo_cfg __initdata mode_0_cfg[] = {
+   { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, },
+   { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, },
+   { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
+ --- 1062,1073 ----
+   /*-------------------------------------------------------------------------*/
+   
+   /*
+    * tables defining fifo_mode values.  define more if you like.
+    * for host side, make sure both halves of ep1 are set up.
+    */
+   
+   /* mode 0 - fits in 2KB */
+ ! static struct musb_fifo_cfg mode_0_cfg[] = {
+   { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, },
+   { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, },
+   { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
+ ***************
+ *** 1042,1048 ****
+   };
+   
+   /* mode 1 - fits in 4KB */
+ ! static struct musb_fifo_cfg __initdata mode_1_cfg[] = {
+   { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
+   { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
+   { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
+ --- 1076,1082 ----
+   };
+   
+   /* mode 1 - fits in 4KB */
+ ! static struct musb_fifo_cfg mode_1_cfg[] = {
+   { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
+   { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
+   { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
+ ***************
+ *** 1051,1057 ****
+   };
+   
+   /* mode 2 - fits in 4KB */
+ ! static struct musb_fifo_cfg __initdata mode_2_cfg[] = {
+   { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, },
+   { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, },
+   { .hw_ep_num = 2, .style = FIFO_TX,   .maxpacket = 512, },
+ --- 1085,1091 ----
+   };
+   
+   /* mode 2 - fits in 4KB */
+ ! static struct musb_fifo_cfg mode_2_cfg[] = {
+   { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, },
+   { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, },
+   { .hw_ep_num = 2, .style = FIFO_TX,   .maxpacket = 512, },
+ ***************
+ *** 1061,1067 ****
+   };
+   
+   /* mode 3 - fits in 4KB */
+ ! static struct musb_fifo_cfg __initdata mode_3_cfg[] = {
+   { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
+   { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
+   { .hw_ep_num = 2, .style = FIFO_TX,   .maxpacket = 512, },
+ --- 1095,1101 ----
+   };
+   
+   /* mode 3 - fits in 4KB */
+ ! static struct musb_fifo_cfg mode_3_cfg[] = {
+   { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
+   { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
+   { .hw_ep_num = 2, .style = FIFO_TX,   .maxpacket = 512, },
+ ***************
+ *** 1071,1083 ****
+   };
+   
+   /* mode 4 - fits in 16KB */
+ ! static struct musb_fifo_cfg __initdata mode_4_cfg[] = {
+ ! { .hw_ep_num =  1, .style = FIFO_TX,   .maxpacket = 512, },
+ ! { .hw_ep_num =  1, .style = FIFO_RX,   .maxpacket = 512, },
+ ! { .hw_ep_num =  2, .style = FIFO_TX,   .maxpacket = 512, },
+ ! { .hw_ep_num =  2, .style = FIFO_RX,   .maxpacket = 512, },
+ ! { .hw_ep_num =  3, .style = FIFO_TX,   .maxpacket = 512, },
+ ! { .hw_ep_num =  3, .style = FIFO_RX,   .maxpacket = 512, },
+   { .hw_ep_num =  4, .style = FIFO_TX,   .maxpacket = 512, },
+   { .hw_ep_num =  4, .style = FIFO_RX,   .maxpacket = 512, },
+   { .hw_ep_num =  5, .style = FIFO_TX,   .maxpacket = 512, },
+ --- 1105,1117 ----
+   };
+   
+   /* mode 4 - fits in 16KB */
+ ! static struct musb_fifo_cfg mode_4_cfg[] = {
+ ! { .hw_ep_num =  1, .style = FIFO_TX,   .maxpacket = 512,},
+ ! { .hw_ep_num =  1, .style = FIFO_RX,   .maxpacket = 512,},
+ ! { .hw_ep_num =  2, .style = FIFO_TX,   .maxpacket = 512,},
+ ! { .hw_ep_num =  2, .style = FIFO_RX,   .maxpacket = 512,},
+ ! { .hw_ep_num =  3, .style = FIFO_TX,   .maxpacket = 512,},
+ ! { .hw_ep_num =  3, .style = FIFO_RX,   .maxpacket = 512,},
+   { .hw_ep_num =  4, .style = FIFO_TX,   .maxpacket = 512, },
+   { .hw_ep_num =  4, .style = FIFO_RX,   .maxpacket = 512, },
+   { .hw_ep_num =  5, .style = FIFO_TX,   .maxpacket = 512, },
+ ***************
+ *** 1101,1108 ****
+   { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
+   };
+   
+   /* mode 5 - fits in 8KB */
+ ! static struct musb_fifo_cfg __initdata mode_5_cfg[] = {
+   { .hw_ep_num =  1, .style = FIFO_TX,   .maxpacket = 512, },
+   { .hw_ep_num =  1, .style = FIFO_RX,   .maxpacket = 512, },
+   { .hw_ep_num =  2, .style = FIFO_TX,   .maxpacket = 512, },
+ --- 1135,1143 ----
+   { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
+   };
+   
+ + 
+   /* mode 5 - fits in 8KB */
+ ! static struct musb_fifo_cfg mode_5_cfg[] = {
+   { .hw_ep_num =  1, .style = FIFO_TX,   .maxpacket = 512, },
+   { .hw_ep_num =  1, .style = FIFO_RX,   .maxpacket = 512, },
+   { .hw_ep_num =  2, .style = FIFO_TX,   .maxpacket = 512, },
+ ***************
+ *** 1132,1144 ****
+   { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
+   };
+   
+   /*
+    * configure a fifo; for non-shared endpoints, this may be called
+    * once for a tx fifo and once for an rx fifo.
+    *
+    * returns negative errno or offset for next fifo.
+    */
+ ! static int __init
+   fifo_setup(struct musb *musb, struct musb_hw_ep  *hw_ep,
+   		const struct musb_fifo_cfg *cfg, u16 offset)
+   {
+ --- 1167,1210 ----
+   { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
+   };
+   
+ + /* mode 6 - fits in 32KB */
+ + static struct musb_fifo_cfg mode_6_cfg[] = {
+ + { .hw_ep_num =  1, .style = FIFO_TX,   .maxpacket = 512, .mode = BUF_DOUBLE,},
+ + { .hw_ep_num =  1, .style = FIFO_RX,   .maxpacket = 512, .mode = BUF_DOUBLE,},
+ + { .hw_ep_num =  2, .style = FIFO_TX,   .maxpacket = 512, .mode = BUF_DOUBLE,},
+ + { .hw_ep_num =  2, .style = FIFO_RX,   .maxpacket = 512, .mode = BUF_DOUBLE,},
+ + { .hw_ep_num =  3, .style = FIFO_TX,   .maxpacket = 512, .mode = BUF_DOUBLE,},
+ + { .hw_ep_num =  3, .style = FIFO_RX,   .maxpacket = 512, .mode = BUF_DOUBLE,},
+ + { .hw_ep_num =  4, .style = FIFO_TX,   .maxpacket = 64, },
+ + { .hw_ep_num =  4, .style = FIFO_RX,   .maxpacket = 64, },
+ + { .hw_ep_num =  5, .style = FIFO_TX,   .maxpacket = 64, },
+ + { .hw_ep_num =  5, .style = FIFO_RX,   .maxpacket = 64, },
+ + { .hw_ep_num =  6, .style = FIFO_TX,   .maxpacket = 64, },
+ + { .hw_ep_num =  6, .style = FIFO_RX,   .maxpacket = 64, },
+ + { .hw_ep_num =  7, .style = FIFO_TX,   .maxpacket = 64, },
+ + { .hw_ep_num =  7, .style = FIFO_RX,   .maxpacket = 64, },
+ + { .hw_ep_num =  8, .style = FIFO_TX,   .maxpacket = 64, },
+ + { .hw_ep_num =  8, .style = FIFO_RX,   .maxpacket = 64, },
+ + { .hw_ep_num =  9, .style = FIFO_TX,   .maxpacket = 64, },
+ + { .hw_ep_num =  9, .style = FIFO_RX,   .maxpacket = 64, },
+ + { .hw_ep_num = 10, .style = FIFO_TX,   .maxpacket = 256, },
+ + { .hw_ep_num = 10, .style = FIFO_RX,   .maxpacket = 64, },
+ + { .hw_ep_num = 11, .style = FIFO_TX,   .maxpacket = 256, },
+ + { .hw_ep_num = 11, .style = FIFO_RX,   .maxpacket = 64, },
+ + { .hw_ep_num = 12, .style = FIFO_TX,   .maxpacket = 256, },
+ + { .hw_ep_num = 12, .style = FIFO_RX,   .maxpacket = 64, },
+ + { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
+ + { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
+ + { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
+ + };
+ + 
+   /*
+    * configure a fifo; for non-shared endpoints, this may be called
+    * once for a tx fifo and once for an rx fifo.
+    *
+    * returns negative errno or offset for next fifo.
+    */
+ ! static int __devinit
+   fifo_setup(struct musb *musb, struct musb_hw_ep  *hw_ep,
+   		const struct musb_fifo_cfg *cfg, u16 offset)
+   {
+ ***************
+ *** 1170,1176 ****
+   	/* EP0 reserved endpoint for control, bidirectional;
+   	 * EP1 reserved for bulk, two unidirection halves.
+   	 */
+ ! 	if (hw_ep->epnum == 1)
+   		musb->bulk_ep = hw_ep;
+   	/* REVISIT error check:  be sure ep0 can both rx and tx ... */
+   	switch (cfg->style) {
+ --- 1236,1242 ----
+   	/* EP0 reserved endpoint for control, bidirectional;
+   	 * EP1 reserved for bulk, two unidirection halves.
+   	 */
+ ! 	if (is_host_enabled(musb) && hw_ep->epnum == 1)
+   		musb->bulk_ep = hw_ep;
+   	/* REVISIT error check:  be sure ep0 can both rx and tx ... */
+   	switch (cfg->style) {
+ ***************
+ *** 1209,1234 ****
+   	return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
+   }
+   
+ ! static struct musb_fifo_cfg __initdata ep0_cfg = {
+   	.style = FIFO_RXTX, .maxpacket = 64,
+   };
+   
+ ! static int __init ep_config_from_table(struct musb *musb)
+   {
+   	const struct musb_fifo_cfg	*cfg;
+   	unsigned		i, n;
+   	int			offset;
+   	struct musb_hw_ep	*hw_ep = musb->endpoints;
+   
+ ! 	if (musb->config->fifo_cfg) {
+   		cfg = musb->config->fifo_cfg;
+   		n = musb->config->fifo_cfg_size;
+   		goto done;
+   	}
+   
+ ! 	switch (fifo_mode) {
+   	default:
+ ! 		fifo_mode = 0;
+   		/* FALLTHROUGH */
+   	case 0:
+   		cfg = mode_0_cfg;
+ --- 1275,1302 ----
+   	return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
+   }
+   
+ ! static struct musb_fifo_cfg ep0_cfg = {
+   	.style = FIFO_RXTX, .maxpacket = 64,
+   };
+   
+ ! int ep_config_from_table(struct musb *musb)
+   {
+   	const struct musb_fifo_cfg	*cfg;
+   	unsigned		i, n;
+   	int			offset;
+   	struct musb_hw_ep	*hw_ep = musb->endpoints;
+   
+ ! 	if (musb->config->fifo_mode)
+ ! 		musb->fifo_mode = musb->config->fifo_mode;
+ ! 	else if (musb->config->fifo_cfg) {
+   		cfg = musb->config->fifo_cfg;
+   		n = musb->config->fifo_cfg_size;
+   		goto done;
+   	}
+   
+ ! 	switch (musb->fifo_mode) {
+   	default:
+ ! 		musb->fifo_mode = 0;
+   		/* FALLTHROUGH */
+   	case 0:
+   		cfg = mode_0_cfg;
+ ***************
+ *** 1254,1263 ****
+   		cfg = mode_5_cfg;
+   		n = ARRAY_SIZE(mode_5_cfg);
+   		break;
+   	}
+   
+   	printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
+ ! 			musb_driver_name, fifo_mode);
+   
+   
+   done:
+ --- 1322,1335 ----
+   		cfg = mode_5_cfg;
+   		n = ARRAY_SIZE(mode_5_cfg);
+   		break;
+ + 	case 6:
+ + 		cfg = mode_6_cfg;
+ + 		n = ARRAY_SIZE(mode_6_cfg);
+ + 		break;
+   	}
+   
+   	printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
+ ! 			musb_driver_name, musb->fifo_mode);
+   
+   
+   done:
+ ***************
+ *** 1291,1310 ****
+   			n + 1, musb->config->num_eps * 2 - 1,
+   			offset, (1 << (musb->config->ram_bits + 2)));
+   
+ ! 	if (!musb->bulk_ep) {
+   		pr_debug("%s: missing bulk\n", musb_driver_name);
+   		return -EINVAL;
+   	}
+   
+   	return 0;
+   }
+ ! 
+   
+   /*
+    * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
+    * @param musb the controller
+    */
+ ! static int __init ep_config_from_hw(struct musb *musb)
+   {
+   	u8 epnum = 0;
+   	struct musb_hw_ep *hw_ep;
+ --- 1363,1382 ----
+   			n + 1, musb->config->num_eps * 2 - 1,
+   			offset, (1 << (musb->config->ram_bits + 2)));
+   
+ ! 	if (is_host_enabled(musb) && !musb->bulk_ep) {
+   		pr_debug("%s: missing bulk\n", musb_driver_name);
+   		return -EINVAL;
+   	}
+   
+   	return 0;
+   }
+ ! EXPORT_SYMBOL(ep_config_from_table);
+   
+   /*
+    * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
+    * @param musb the controller
+    */
+ ! static int __devinit ep_config_from_hw(struct musb *musb)
+   {
+   	u8 epnum = 0;
+   	struct musb_hw_ep *hw_ep;
+ ***************
+ *** 1316,1322 ****
+   	/* FIXME pick up ep0 maxpacket size */
+   
+   	for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
+ ! 		musb_ep_select(mbase, epnum);
+   		hw_ep = musb->endpoints + epnum;
+   
+   		ret = musb_read_fifosize(musb, hw_ep, epnum);
+ --- 1388,1394 ----
+   	/* FIXME pick up ep0 maxpacket size */
+   
+   	for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
+ ! 		musb_ep_select(musb, mbase, epnum);
+   		hw_ep = musb->endpoints + epnum;
+   
+   		ret = musb_read_fifosize(musb, hw_ep, epnum);
+ ***************
+ *** 1325,1344 ****
+   
+   		/* FIXME set up hw_ep->{rx,tx}_double_buffered */
+   
+ ! 		/* pick an RX/TX endpoint for bulk */
+ ! 		if (hw_ep->max_packet_sz_tx < 512
+   				|| hw_ep->max_packet_sz_rx < 512)
+ ! 			continue;
+   
+ ! 		/* REVISIT:  this algorithm is lazy, we should at least
+ ! 		 * try to pick a double buffered endpoint.
+ ! 		 */
+ ! 		if (musb->bulk_ep)
+ ! 			continue;
+ ! 		musb->bulk_ep = hw_ep;
+   	}
+   
+ ! 	if (!musb->bulk_ep) {
+   		pr_debug("%s: missing bulk\n", musb_driver_name);
+   		return -EINVAL;
+   	}
+ --- 1397,1418 ----
+   
+   		/* FIXME set up hw_ep->{rx,tx}_double_buffered */
+   
+ ! 		if (is_host_enabled(musb)) {
+ ! 			/* pick an RX/TX endpoint for bulk */
+ ! 			if (hw_ep->max_packet_sz_tx < 512
+   				|| hw_ep->max_packet_sz_rx < 512)
+ ! 				continue;
+   
+ ! 			/* REVISIT:  this algorithm is lazy, we should at least
+ ! 			 * try to pick a double buffered endpoint.
+ ! 			 */
+ ! 			if (musb->bulk_ep)
+ ! 				continue;
+ ! 			musb->bulk_ep = hw_ep;
+ ! 		}
+   	}
+   
+ ! 	if (is_host_enabled(musb) && !musb->bulk_ep) {
+   		pr_debug("%s: missing bulk\n", musb_driver_name);
+   		return -EINVAL;
+   	}
+ ***************
+ *** 1351,1358 ****
+   /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
+    * configure endpoints, or take their config from silicon
+    */
+ ! static int __init musb_core_init(u16 musb_type, struct musb *musb)
+   {
+   	u8 reg;
+   	char *type;
+   	char aInfo[90], aRevision[32], aDate[12];
+ --- 1425,1434 ----
+   /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
+    * configure endpoints, or take their config from silicon
+    */
+ ! static int __devinit musb_core_init(u16 musb_type, struct musb *musb)
+   {
+ + 	struct device *dev = musb->controller;
+ + 	struct musb_hdrc_platform_data *plat = dev->platform_data;
+   	u8 reg;
+   	char *type;
+   	char aInfo[90], aRevision[32], aDate[12];
+ ***************
+ *** 1398,1406 ****
+   		musb->is_multipoint = 0;
+   		type = "";
+   #ifndef	CONFIG_USB_OTG_BLACKLIST_HUB
+ ! 		printk(KERN_ERR
+ ! 			"%s: kernel must blacklist external hubs\n",
+ ! 			musb_driver_name);
+   #endif
+   	}
+   
+ --- 1474,1483 ----
+   		musb->is_multipoint = 0;
+   		type = "";
+   #ifndef	CONFIG_USB_OTG_BLACKLIST_HUB
+ ! 		if (is_host_enabled(musb))
+ ! 			printk(KERN_ERR
+ ! 				"%s: kernel must blacklist external hubs\n",
+ ! 				musb_driver_name);
+   #endif
+   	}
+   
+ ***************
+ *** 1431,1453 ****
+   	for (i = 0; i < musb->nr_endpoints; i++) {
+   		struct musb_hw_ep	*hw_ep = musb->endpoints + i;
+   
+ ! 		hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
+ ! #ifdef CONFIG_USB_MUSB_TUSB6010
+ ! 		hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
+ ! 		hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
+ ! 		hw_ep->fifo_sync_va =
+ ! 			musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
+   
+ ! 		if (i == 0)
+ ! 			hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
+ ! 		else
+ ! 			hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
+ ! #endif
+   
+ ! 		hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
+ ! 		hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
+ ! 		hw_ep->rx_reinit = 1;
+ ! 		hw_ep->tx_reinit = 1;
+   
+   		if (hw_ep->max_packet_sz_tx) {
+   			dev_dbg(musb->controller,
+ --- 1508,1538 ----
+   	for (i = 0; i < musb->nr_endpoints; i++) {
+   		struct musb_hw_ep	*hw_ep = musb->endpoints + i;
+   
+ ! 		if (musb->ops->flags & MUSB_GLUE_TUSB_STYLE) {
+ ! 			hw_ep->fifo = MUSB_TUSB_FIFO_OFFSET(i) + mbase;
+ ! 			hw_ep->fifo_async = musb->async +
+ ! 					0x400 + MUSB_TUSB_FIFO_OFFSET(i);
+ ! 			hw_ep->fifo_sync = musb->sync +
+ ! 					0x400 + MUSB_TUSB_FIFO_OFFSET(i);
+ ! 			hw_ep->fifo_sync_va = musb->sync_va + 0x400 +
+ ! 					MUSB_TUSB_FIFO_OFFSET(i);
+   
+ ! 			if (i == 0)
+ ! 				hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
+ ! 			else
+ ! 				hw_ep->conf = mbase + 0x400 +
+ ! 						(((i - 1) & 0xf) << 2);
+ ! 		} else {
+ ! 			hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
+ ! 		}
+   
+ ! 		hw_ep->regs = MUSB_EP_OFFSET(musb, i, 0) + mbase;
+ ! 		if (is_host_enabled(musb)) {
+ ! 			hw_ep->target_regs =
+ ! 					musb_read_target_reg_base(i, mbase);
+ ! 			hw_ep->rx_reinit = 1;
+ ! 			hw_ep->tx_reinit = 1;
+ ! 		}
+   
+   		if (hw_ep->max_packet_sz_tx) {
+   			dev_dbg(musb->controller,
+ ***************
+ *** 1471,1479 ****
+ --- 1556,1581 ----
+   			dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
+   	}
+   
+ + 	if (!plat->config->mult_bulk_tx) {
+ + 		musb->bulk_split = 0;
+ + 		printk(KERN_DEBUG "%s.%d: bulk split disabled\n",
+ + 			musb_driver_name, musb->id);
+ + 	}
+ + 	if (!plat->config->mult_bulk_rx) {
+ + 		musb->bulk_combine = 0;
+ + 		printk(KERN_DEBUG "%s.%d: bulk combine disabled\n",
+ + 			musb_driver_name, musb->id);
+ + 	}
+ + 
+   	return 0;
+   }
+   
+ + void musb_reinit(u16 musb_type, struct musb *musb)
+ + {
+ + 	musb_core_init(musb_type ? MUSB_CONTROLLER_MHDRC
+ + 			: MUSB_CONTROLLER_HDRC, musb);
+ + }
+ + EXPORT_SYMBOL(musb_reinit);
+   /*-------------------------------------------------------------------------*/
+   
+   #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \
+ ***************
+ *** 1546,1559 ****
+   	ep_num = 1;
+   	while (reg) {
+   		if (reg & 1) {
+ ! 			/* musb_ep_select(musb->mregs, ep_num); */
+   			/* REVISIT just retval = ep->rx_irq(...) */
+   			retval = IRQ_HANDLED;
+   			if (devctl & MUSB_DEVCTL_HM) {
+ ! 				if (is_host_capable())
+   					musb_host_rx(musb, ep_num);
+   			} else {
+ ! 				if (is_peripheral_capable())
+   					musb_g_rx(musb, ep_num);
+   			}
+   		}
+ --- 1648,1661 ----
+   	ep_num = 1;
+   	while (reg) {
+   		if (reg & 1) {
+ ! 			/* musb_ep_select(musb, musb->mregs, ep_num); */
+   			/* REVISIT just retval = ep->rx_irq(...) */
+   			retval = IRQ_HANDLED;
+   			if (devctl & MUSB_DEVCTL_HM) {
+ ! 				if (is_host_enabled(musb))
+   					musb_host_rx(musb, ep_num);
+   			} else {
+ ! 				if (is_peripheral_enabled(musb))
+   					musb_g_rx(musb, ep_num);
+   			}
+   		}
+ ***************
+ *** 1567,1580 ****
+   	ep_num = 1;
+   	while (reg) {
+   		if (reg & 1) {
+ ! 			/* musb_ep_select(musb->mregs, ep_num); */
+   			/* REVISIT just retval |= ep->tx_irq(...) */
+   			retval = IRQ_HANDLED;
+   			if (devctl & MUSB_DEVCTL_HM) {
+ ! 				if (is_host_capable())
+   					musb_host_tx(musb, ep_num);
+   			} else {
+ ! 				if (is_peripheral_capable())
+   					musb_g_tx(musb, ep_num);
+   			}
+   		}
+ --- 1669,1682 ----
+   	ep_num = 1;
+   	while (reg) {
+   		if (reg & 1) {
+ ! 			/* musb_ep_select(musb, musb->mregs, ep_num); */
+   			/* REVISIT just retval |= ep->tx_irq(...) */
+   			retval = IRQ_HANDLED;
+   			if (devctl & MUSB_DEVCTL_HM) {
+ ! 				if (is_host_enabled(musb))
+   					musb_host_tx(musb, ep_num);
+   			} else {
+ ! 				if (is_peripheral_enabled(musb))
+   					musb_g_tx(musb, ep_num);
+   			}
+   		}
+ ***************
+ *** 1587,1598 ****
+   EXPORT_SYMBOL_GPL(musb_interrupt);
+   
+   #ifndef CONFIG_MUSB_PIO_ONLY
+ - static int __initdata use_dma = 1;
+ - 
+ - /* "modprobe ... use_dma=0" etc */
+ - module_param(use_dma, bool, 0);
+ - MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
+ - 
+   void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
+   {
+   	u8	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
+ --- 1689,1694 ----
+ ***************
+ *** 1600,1639 ****
+   	/* called with controller lock already held */
+   
+   	if (!epnum) {
+ ! #ifndef CONFIG_USB_TUSB_OMAP_DMA
+ ! 		if (!is_cppi_enabled()) {
+   			/* endpoint 0 */
+   			if (devctl & MUSB_DEVCTL_HM)
+   				musb_h_ep0_irq(musb);
+   			else
+   				musb_g_ep0_irq(musb);
+   		}
+ - #endif
+   	} else {
+   		/* endpoints 1..15 */
+   		if (transmit) {
+   			if (devctl & MUSB_DEVCTL_HM) {
+ ! 				if (is_host_capable())
+   					musb_host_tx(musb, epnum);
+   			} else {
+ ! 				if (is_peripheral_capable())
+   					musb_g_tx(musb, epnum);
+   			}
+   		} else {
+   			/* receive */
+   			if (devctl & MUSB_DEVCTL_HM) {
+ ! 				if (is_host_capable())
+   					musb_host_rx(musb, epnum);
+   			} else {
+ ! 				if (is_peripheral_capable())
+   					musb_g_rx(musb, epnum);
+   			}
+   		}
+   	}
+   }
+ ! 
+ ! #else
+ ! #define use_dma			0
+   #endif
+   
+   /*-------------------------------------------------------------------------*/
+ --- 1696,1732 ----
+   	/* called with controller lock already held */
+   
+   	if (!epnum) {
+ ! 		if (!tusb_dma_omap(musb) && !is_cppi_enabled(musb)
+ ! 				&& !is_cppi41_enabled(musb)) {
+   			/* endpoint 0 */
+   			if (devctl & MUSB_DEVCTL_HM)
+   				musb_h_ep0_irq(musb);
+   			else
+   				musb_g_ep0_irq(musb);
+   		}
+   	} else {
+   		/* endpoints 1..15 */
+   		if (transmit) {
+   			if (devctl & MUSB_DEVCTL_HM) {
+ ! 				if (is_host_enabled(musb))
+   					musb_host_tx(musb, epnum);
+   			} else {
+ ! 				if (is_peripheral_enabled(musb))
+   					musb_g_tx(musb, epnum);
+   			}
+   		} else {
+   			/* receive */
+   			if (devctl & MUSB_DEVCTL_HM) {
+ ! 				if (is_host_enabled(musb))
+   					musb_host_rx(musb, epnum);
+   			} else {
+ ! 				if (is_peripheral_enabled(musb))
+   					musb_g_rx(musb, epnum);
+   			}
+   		}
+   	}
+   }
+ ! EXPORT_SYMBOL_GPL(musb_dma_completion);
+   #endif
+   
+   /*-------------------------------------------------------------------------*/
+ ***************
+ *** 1691,1698 ****
+   	}
+   
+   	spin_lock_irqsave(&musb->lock, flags);
+ ! 	/* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
+ ! 	musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
+   	if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
+   		musb->is_active = 0;
+   	musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
+ --- 1784,1790 ----
+   	}
+   
+   	spin_lock_irqsave(&musb->lock, flags);
+ ! 	musb->a_wait_bcon = val;
+   	if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
+   		musb->is_active = 0;
+   	musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
+ ***************
+ *** 1711,1723 ****
+   
+   	spin_lock_irqsave(&musb->lock, flags);
+   	val = musb->a_wait_bcon;
+ - 	/* FIXME get_vbus_status() is normally #defined as false...
+ - 	 * and is effectively TUSB-specific.
+ - 	 */
+   	vbus = musb_platform_get_vbus_status(musb);
+   	spin_unlock_irqrestore(&musb->lock, flags);
+   
+ ! 	return sprintf(buf, "Vbus %s, timeout %lu msec\n",
+   			vbus ? "on" : "off", val);
+   }
+   static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
+ --- 1803,1812 ----
+   
+   	spin_lock_irqsave(&musb->lock, flags);
+   	val = musb->a_wait_bcon;
+   	vbus = musb_platform_get_vbus_status(musb);
+   	spin_unlock_irqrestore(&musb->lock, flags);
+   
+ ! 	return sprintf(buf, "Vbus %s, timeout %lu\n",
+   			vbus ? "on" : "off", val);
+   }
+   static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
+ ***************
+ *** 1762,1771 ****
+   static void musb_irq_work(struct work_struct *data)
+   {
+   	struct musb *musb = container_of(data, struct musb, irq_work);
+ - 	static int old_state;
+   
+ ! 	if (musb->xceiv->state != old_state) {
+ ! 		old_state = musb->xceiv->state;
+   		sysfs_notify(&musb->controller->kobj, NULL, "mode");
+   	}
+   }
+ --- 1851,1859 ----
+   static void musb_irq_work(struct work_struct *data)
+   {
+   	struct musb *musb = container_of(data, struct musb, irq_work);
+   
+ ! 	if (musb->xceiv->state != musb->old_state) {
+ ! 		musb->old_state = musb->xceiv->state;
+   		sysfs_notify(&musb->controller->kobj, NULL, "mode");
+   	}
+   }
+ ***************
+ *** 1774,1780 ****
+    * Init support
+    */
+   
+ ! static struct musb *__init
+   allocate_instance(struct device *dev,
+   		struct musb_hdrc_config *config, void __iomem *mbase)
+   {
+ --- 1862,1868 ----
+    * Init support
+    */
+   
+ ! static struct musb *__devinit
+   allocate_instance(struct device *dev,
+   		struct musb_hdrc_config *config, void __iomem *mbase)
+   {
+ ***************
+ *** 1782,1803 ****
+   	struct musb_hw_ep	*ep;
+   	int			epnum;
+   	struct usb_hcd	*hcd;
+   
+ ! 	hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
+ ! 	if (!hcd)
+ ! 		return NULL;
+ ! 	/* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
+ ! 
+ ! 	musb = hcd_to_musb(hcd);
+ ! 	INIT_LIST_HEAD(&musb->control);
+ ! 	INIT_LIST_HEAD(&musb->in_bulk);
+ ! 	INIT_LIST_HEAD(&musb->out_bulk);
+ ! 
+ ! 	hcd->uses_new_polling = 1;
+ ! 	hcd->has_tt = 1;
+   
+ ! 	musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
+ ! 	musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
+   	dev_set_drvdata(dev, musb);
+   	musb->mregs = mbase;
+   	musb->ctrl_base = mbase;
+ --- 1870,1899 ----
+   	struct musb_hw_ep	*ep;
+   	int			epnum;
+   	struct usb_hcd	*hcd;
+ + 	struct musb_hdrc_platform_data *plat = dev->platform_data;
+   
+ ! 	if (plat->mode != MUSB_PERIPHERAL) {
+ ! 		hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
+ ! 		if (!hcd)
+ ! 			return NULL;
+ ! 		/* usbcore sets dev->driver_data to hcd, and sometimes uses
+ ! 		 * that...
+ ! 		 */
+   
+ ! 		musb = hcd_to_musb(hcd);
+ ! 		INIT_LIST_HEAD(&musb->control);
+ ! 		INIT_LIST_HEAD(&musb->in_bulk);
+ ! 		INIT_LIST_HEAD(&musb->out_bulk);
+ ! 		INIT_LIST_HEAD(&musb->gb_list);
+ ! 
+ ! 		hcd->uses_new_polling = 1;
+ ! 		hcd->has_tt = 1;
+ ! 		musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
+ ! 	} else {
+ ! 		musb = kzalloc(sizeof *musb, GFP_KERNEL);
+ ! 		if (!musb)
+ ! 			return NULL;
+ ! 	}
+   	dev_set_drvdata(dev, musb);
+   	musb->mregs = mbase;
+   	musb->ctrl_base = mbase;
+ ***************
+ *** 1827,1833 ****
+   	sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
+   #endif
+   
+ ! 	musb_gadget_cleanup(musb);
+   
+   	if (musb->nIrq >= 0) {
+   		if (musb->irq_wake)
+ --- 1923,1930 ----
+   	sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
+   #endif
+   
+ ! 	if (is_peripheral_enabled(musb))
+ ! 		musb_gadget_cleanup(musb);
+   
+   	if (musb->nIrq >= 0) {
+   		if (musb->irq_wake)
+ ***************
+ *** 1838,1847 ****
+   		struct dma_controller	*c = musb->dma_controller;
+   
+   		(void) c->stop(c);
+ ! 		dma_controller_destroy(c);
+   	}
+   
+ ! 	kfree(musb);
+   }
+   
+   /*
+ --- 1935,1953 ----
+   		struct dma_controller	*c = musb->dma_controller;
+   
+   		(void) c->stop(c);
+ ! 		musb->ops->dma_controller_destroy(c);
+   	}
+   
+ ! 	if (is_otg_enabled(musb))
+ ! 		del_timer_sync(&musb->otg_timer);
+ ! 
+ ! 	if (is_host_enabled(musb)) {
+ ! 		if (musb->gb_queue)
+ ! 			destroy_workqueue(musb->gb_queue);
+ ! 		usb_put_hcd(musb_to_hcd(musb));
+ ! 	} else {
+ ! 		kfree(musb);
+ ! 	}
+   }
+   
+   /*
+ ***************
+ *** 1852,1863 ****
+    * @mregs: virtual address of controller registers,
+    *	not yet corrected for platform-specific offsets
+    */
+ ! static int __init
+   musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
+   {
+   	int			status;
+   	struct musb		*musb;
+   	struct musb_hdrc_platform_data *plat = dev->platform_data;
+   
+   	/* The driver might handle more features than the board; OK.
+   	 * Fail when the board needs a feature that's not enabled.
+ --- 1958,1970 ----
+    * @mregs: virtual address of controller registers,
+    *	not yet corrected for platform-specific offsets
+    */
+ ! static int __devinit
+   musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
+   {
+   	int			status;
+   	struct musb		*musb;
+   	struct musb_hdrc_platform_data *plat = dev->platform_data;
+ + 	struct platform_device *pdev = to_platform_device(dev);
+   
+   	/* The driver might handle more features than the board; OK.
+   	 * Fail when the board needs a feature that's not enabled.
+ ***************
+ *** 1884,1889 ****
+ --- 1991,2015 ----
+   	musb->board_set_power = plat->set_power;
+   	musb->min_power = plat->min_power;
+   	musb->ops = plat->platform_ops;
+ + 	musb->id = pdev->id;
+ + 	musb->first = 1;
+ + 	if (is_host_enabled(musb))
+ + 		spin_lock_init(&musb->gb_lock);
+ + 
+ + 	musb->fifo_mode = musb->ops->fifo_mode;
+ + 
+ + #ifndef CONFIG_MUSB_PIO_ONLY
+ + 	musb->orig_dma_mask = dev->dma_mask;
+ + #endif
+ + 	if (musb->ops->flags & MUSB_GLUE_TUSB_STYLE) {
+ + 		musb_readb = __tusb_musb_readb;
+ + 		musb_writeb = __tusb_musb_writeb;
+ + 	} else {
+ + 		musb_readb = __musb_readb;
+ + 		musb_writeb = __musb_writeb;
+ + 	}
+ + 
+ + 	dev_info(dev, "dma type: %s\n", get_dma_name(musb));
+   
+   	/* The musb_platform_init() call:
+   	 *   - adjusts musb->mregs and musb->isr if needed,
+ ***************
+ *** 1912,1921 ****
+   	}
+   
+   #ifndef CONFIG_MUSB_PIO_ONLY
+ ! 	if (use_dma && dev->dma_mask) {
+   		struct dma_controller	*c;
+   
+ ! 		c = dma_controller_create(musb, musb->mregs);
+   		musb->dma_controller = c;
+   		if (c)
+   			(void) c->start(c);
+ --- 2038,2052 ----
+   	}
+   
+   #ifndef CONFIG_MUSB_PIO_ONLY
+ ! 	if (dev->dma_mask) {
+   		struct dma_controller	*c;
+   
+ ! 		if (!musb->ops->dma_controller_create) {
+ ! 			dev_err(dev, "no dma_controller_create for non-PIO mode!\n");
+ ! 			status = -ENODEV;
+ ! 			goto fail3;
+ ! 		}
+ ! 		c = musb->ops->dma_controller_create(musb, musb->mregs);
+   		musb->dma_controller = c;
+   		if (c)
+   			(void) c->start(c);
+ ***************
+ *** 1936,1943 ****
+   	if (status < 0)
+   		goto fail3;
+   
+ - 	setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
+ - 
+   	/* Init IRQ workqueue before request_irq */
+   	INIT_WORK(&musb->irq_work, musb_irq_work);
+   
+ --- 2067,2072 ----
+ ***************
+ *** 1949,1960 ****
+   	}
+   	musb->nIrq = nIrq;
+   /* FIXME this handles wakeup irqs wrong */
+ ! 	if (enable_irq_wake(nIrq) == 0) {
+   		musb->irq_wake = 1;
+ ! 		device_init_wakeup(dev, 1);
+ ! 	} else {
+   		musb->irq_wake = 0;
+ ! 	}
+   
+   	/* host side needs more setup */
+   	if (is_host_enabled(musb)) {
+ --- 2078,2089 ----
+   	}
+   	musb->nIrq = nIrq;
+   /* FIXME this handles wakeup irqs wrong */
+ ! 	if (enable_irq_wake(nIrq) == 0)
+   		musb->irq_wake = 1;
+ ! 	else
+   		musb->irq_wake = 0;
+ ! 
+ ! 	device_init_wakeup(dev, 1);
+   
+   	/* host side needs more setup */
+   	if (is_host_enabled(musb)) {
+ ***************
+ *** 1987,1993 ****
+   		musb->xceiv->state = OTG_STATE_A_IDLE;
+   
+   		status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
+ ! 
+   		hcd->self.uses_pio_for_control = 1;
+   		dev_dbg(musb->controller, "%s mode, status %d, devctl %02x %c\n",
+   			"HOST", status,
+ --- 2116,2122 ----
+   		musb->xceiv->state = OTG_STATE_A_IDLE;
+   
+   		status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
+ ! 		device_set_wakeup_enable(dev, 0);
+   		hcd->self.uses_pio_for_control = 1;
+   		dev_dbg(musb->controller, "%s mode, status %d, devctl %02x %c\n",
+   			"HOST", status,
+ ***************
+ *** 2002,2007 ****
+ --- 2131,2137 ----
+   		musb->xceiv->state = OTG_STATE_B_IDLE;
+   
+   		status = musb_gadget_setup(musb);
+ + 		device_set_wakeup_enable(dev, 0);
+   
+   		dev_dbg(musb->controller, "%s mode, status %d, dev%02x\n",
+   			is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
+ ***************
+ *** 2034,2041 ****
+ --- 2164,2193 ----
+   			? "DMA" : "PIO",
+   			musb->nIrq);
+   
+ + 	if (status == 0) {
+ + 		u8 drvbuf[19];
+ + 		sprintf(drvbuf, "driver/musb_hdrc.%d", musb->id);
+ + 		musb_debug_create(drvbuf, musb);
+ + 	}
+ + 
+ + 	if (is_host_enabled(musb)) {
+ + 		musb->gb_queue = create_singlethread_workqueue(dev_name(dev));
+ + 		if (musb->gb_queue == NULL)
+ + 			goto fail6;
+ + 		/* Init giveback workqueue */
+ + 		INIT_WORK(&musb->gb_work, musb_gb_work);
+ + 	}
+ + 
+ + 	/* setup otg_timer */
+ + 	if (is_otg_enabled(musb))
+ + 		setup_timer(&musb->otg_timer, musb_otg_timer_func,
+ + 						(unsigned long) musb);
+   	return 0;
+   
+ + fail6:
+ + 	if (is_host_enabled(musb))
+ + 		destroy_workqueue(musb->gb_queue);
+ + 
+   fail5:
+   	musb_exit_debugfs(musb);
+   
+ ***************
+ *** 2067,2086 ****
+   /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
+    * bridge to a platform device; this driver then suffices.
+    */
+ ! 
+ ! #ifndef CONFIG_MUSB_PIO_ONLY
+ ! static u64	*orig_dma_mask;
+ ! #endif
+ ! 
+ ! static int __init musb_probe(struct platform_device *pdev)
+   {
+   	struct device	*dev = &pdev->dev;
+   	int		irq = platform_get_irq_byname(pdev, "mc");
+   	int		status;
+   	struct resource	*iomem;
+   	void __iomem	*base;
+   
+ - 	iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+   	if (!iomem || irq <= 0)
+   		return -ENODEV;
+   
+ --- 2219,2247 ----
+   /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
+    * bridge to a platform device; this driver then suffices.
+    */
+ ! static int __devinit musb_probe(struct platform_device *pdev)
+   {
+   	struct device	*dev = &pdev->dev;
+   	int		irq = platform_get_irq_byname(pdev, "mc");
+   	int		status;
+   	struct resource	*iomem;
+   	void __iomem	*base;
+ + 	char	res_name[20];
+ + 
+ + 	if (pdev->id == -1)
+ + 		strcpy(res_name, "mc");
+ + 	else
+ + 		sprintf(res_name, "musb%d-irq", pdev->id);
+ + 	irq = platform_get_irq_byname(pdev, res_name);
+ + 
+ + 	if (pdev->id == -1)
+ + 		iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ + 	else {
+ + 		sprintf(res_name, "musb%d", pdev->id);
+ + 		iomem = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ + 			res_name);
+ + 	}
+   
+   	if (!iomem || irq <= 0)
+   		return -ENODEV;
+   
+ ***************
+ *** 2090,2099 ****
+   		return -ENOMEM;
+   	}
+   
+ - #ifndef CONFIG_MUSB_PIO_ONLY
+ - 	/* clobbered by use_dma=n */
+ - 	orig_dma_mask = dev->dma_mask;
+ - #endif
+   	status = musb_init_controller(dev, irq, base);
+   	if (status < 0)
+   		iounmap(base);
+ --- 2251,2256 ----
+ ***************
+ *** 2105,2110 ****
+ --- 2262,2268 ----
+   {
+   	struct musb	*musb = dev_to_musb(&pdev->dev);
+   	void __iomem	*ctrl_base = musb->ctrl_base;
+ + 	u8 drvbuf[19];
+   
+   	/* this gets called on rmmod.
+   	 *  - Host mode: host may still be active
+ ***************
+ *** 2114,2133 ****
+   	pm_runtime_get_sync(musb->controller);
+   	musb_exit_debugfs(musb);
+   	musb_shutdown(pdev);
+   
+   	pm_runtime_put(musb->controller);
+   	musb_free(musb);
+   	iounmap(ctrl_base);
+   	device_init_wakeup(&pdev->dev, 0);
+   #ifndef CONFIG_MUSB_PIO_ONLY
+ ! 	pdev->dev.dma_mask = orig_dma_mask;
+   #endif
+   	return 0;
+   }
+   
+   #ifdef	CONFIG_PM
+   
+ ! static void musb_save_context(struct musb *musb)
+   {
+   	int i;
+   	void __iomem *musb_base = musb->mregs;
+ --- 2272,2293 ----
+   	pm_runtime_get_sync(musb->controller);
+   	musb_exit_debugfs(musb);
+   	musb_shutdown(pdev);
+ + 	sprintf(drvbuf, "driver/musb_hdrc.%d", musb->id);
+ + 	musb_debug_delete(drvbuf, musb);
+   
+   	pm_runtime_put(musb->controller);
+   	musb_free(musb);
+   	iounmap(ctrl_base);
+   	device_init_wakeup(&pdev->dev, 0);
+   #ifndef CONFIG_MUSB_PIO_ONLY
+ ! 	pdev->dev.dma_mask = musb->orig_dma_mask;
+   #endif
+   	return 0;
+   }
+   
+   #ifdef	CONFIG_PM
+   
+ ! void musb_save_context(struct musb *musb)
+   {
+   	int i;
+   	void __iomem *musb_base = musb->mregs;
+ ***************
+ *** 2156,2161 ****
+ --- 2316,2322 ----
+   		if (!epio)
+   			continue;
+   
+ + 		musb_writeb(musb_base, MUSB_INDEX, i);
+   		musb->context.index_regs[i].txmaxp =
+   			musb_readw(epio, MUSB_TXMAXP);
+   		musb->context.index_regs[i].txcsr =
+ ***************
+ *** 2201,2208 ****
+   		}
+   	}
+   }
+   
+ ! static void musb_restore_context(struct musb *musb)
+   {
+   	int i;
+   	void __iomem *musb_base = musb->mregs;
+ --- 2362,2370 ----
+   		}
+   	}
+   }
+ + EXPORT_SYMBOL(musb_save_context);
+   
+ ! void musb_restore_context(struct musb *musb)
+   {
+   	int i;
+   	void __iomem *musb_base = musb->mregs;
+ ***************
+ *** 2231,2236 ****
+ --- 2393,2399 ----
+   		if (!epio)
+   			continue;
+   
+ + 		musb_writeb(musb_base, MUSB_INDEX, i);
+   		musb_writew(epio, MUSB_TXMAXP,
+   			musb->context.index_regs[i].txmaxp);
+   		musb_writew(epio, MUSB_TXCSR,
+ ***************
+ *** 2281,2297 ****
+   	}
+   	musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
+   }
+   
+   static int musb_suspend(struct device *dev)
+   {
+   	struct musb	*musb = dev_to_musb(dev);
+   	unsigned long	flags;
+   
+   	spin_lock_irqsave(&musb->lock, flags);
+   
+   	if (is_peripheral_active(musb)) {
+ ! 		/* FIXME force disconnect unless we know USB will wake
+ ! 		 * the system up quickly enough to respond ...
+   		 */
+   	} else if (is_host_active(musb)) {
+   		/* we know all the children are suspended; sometimes
+ --- 2444,2463 ----
+   	}
+   	musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
+   }
+ + EXPORT_SYMBOL(musb_restore_context);
+   
+   static int musb_suspend(struct device *dev)
+   {
+   	struct musb	*musb = dev_to_musb(dev);
+   	unsigned long	flags;
+ + 	int ret = 0;
+   
+   	spin_lock_irqsave(&musb->lock, flags);
+   
+   	if (is_peripheral_active(musb)) {
+ ! 		/*
+ ! 		 * Don't allow system suspend while peripheral mode
+ ! 		 * is actve and cable is connected to host.
+   		 */
+   	} else if (is_host_active(musb)) {
+   		/* we know all the children are suspended; sometimes
+ ***************
+ *** 2300,2306 ****
+   	}
+   
+   	spin_unlock_irqrestore(&musb->lock, flags);
+ ! 	return 0;
+   }
+   
+   static int musb_resume_noirq(struct device *dev)
+ --- 2466,2472 ----
+   	}
+   
+   	spin_unlock_irqrestore(&musb->lock, flags);
+ ! 	return ret;
+   }
+   
+   static int musb_resume_noirq(struct device *dev)
+ ***************
+ *** 2324,2330 ****
+   static int musb_runtime_resume(struct device *dev)
+   {
+   	struct musb	*musb = dev_to_musb(dev);
+ - 	static int	first = 1;
+   
+   	/*
+   	 * When pm_runtime_get_sync called for the first time in driver
+ --- 2490,2495 ----
+ ***************
+ *** 2335,2343 ****
+   	 * Also context restore without save does not make
+   	 * any sense
+   	 */
+ ! 	if (!first)
+   		musb_restore_context(musb);
+ ! 	first = 0;
+   
+   	return 0;
+   }
+ --- 2500,2510 ----
+   	 * Also context restore without save does not make
+   	 * any sense
+   	 */
+ ! 	if (musb->first)
+ ! 		musb->first = 0;
+ ! 	else
+   		musb_restore_context(musb);
+ ! 
+   
+   	return 0;
+   }
+ ***************
+ *** 2361,2366 ****
+ --- 2528,2534 ----
+   		.owner		= THIS_MODULE,
+   		.pm		= MUSB_DEV_PM_OPS,
+   	},
+ + 	.probe      = musb_probe,
+   	.remove		= __exit_p(musb_remove),
+   	.shutdown	= musb_shutdown,
+   };
+ ***************
+ *** 2377,2383 ****
+   		", "
+   		"otg (peripheral+host)",
+   		musb_driver_name);
+ ! 	return platform_driver_probe(&musb_driver, musb_probe);
+   }
+   
+   /* make us init after usbcore and i2c (transceivers, regulators, etc)
+ --- 2545,2551 ----
+   		", "
+   		"otg (peripheral+host)",
+   		musb_driver_name);
+ ! 	return platform_driver_register(&musb_driver);
+   }
+   
+   /* make us init after usbcore and i2c (transceivers, regulators, etc)
+ diff -crN linux-3.2.1_o/drivers/usb/musb/musb_core.h linux-3.2.1/drivers/usb/musb/musb_core.h
+ *** linux-3.2.1_o/drivers/usb/musb/musb_core.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/musb/musb_core.h	2014-11-25 13:19:16.640105276 +0900
+ ***************
+ *** 39,46 ****
+   #include <linux/list.h>
+   #include <linux/interrupt.h>
+   #include <linux/errno.h>
+ - #include <linux/timer.h>
+ - #include <linux/clk.h>
+   #include <linux/device.h>
+   #include <linux/usb/ch9.h>
+   #include <linux/usb/gadget.h>
+ --- 39,44 ----
+ ***************
+ *** 62,67 ****
+ --- 60,68 ----
+   #define MUSB_HWVERS_1900	0x784
+   #define MUSB_HWVERS_2000	0x800
+   
+ + extern u8 (*musb_readb)(const void __iomem *addr, unsigned offset);
+ + extern void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data);
+ + 
+   #include "musb_debug.h"
+   #include "musb_dma.h"
+   
+ ***************
+ *** 97,104 ****
+   
+   /****************************** PERIPHERAL ROLE *****************************/
+   
+ - #define	is_peripheral_capable()	(1)
+ - 
+   extern irqreturn_t musb_g_ep0_irq(struct musb *);
+   extern void musb_g_tx(struct musb *, u8);
+   extern void musb_g_rx(struct musb *, u8);
+ --- 98,103 ----
+ ***************
+ *** 110,117 ****
+   
+   /****************************** HOST ROLE ***********************************/
+   
+ - #define	is_host_capable()	(1)
+ - 
+   extern irqreturn_t musb_h_ep0_irq(struct musb *);
+   extern void musb_host_tx(struct musb *, u8);
+   extern void musb_host_rx(struct musb *, u8);
+ --- 109,114 ----
+ ***************
+ *** 146,160 ****
+   	MUSB_EP0_STAGE_ACKWAIT,		/* after zlp, before statusin */
+   } __attribute__ ((packed));
+   
+ ! /*
+ !  * OTG protocol constants.  See USB OTG 1.3 spec,
+ !  * sections 5.5 "Device Timings" and 6.6.5 "Timers".
+ !  */
+   #define OTG_TIME_A_WAIT_VRISE	100		/* msec (max) */
+ ! #define OTG_TIME_A_WAIT_BCON	1100		/* min 1 second */
+ ! #define OTG_TIME_A_AIDL_BDIS	200		/* min 200 msec */
+ ! #define OTG_TIME_B_ASE0_BRST	100		/* min 3.125 ms */
+ ! 
+   
+   /*************************** REGISTER ACCESS ********************************/
+   
+ --- 143,152 ----
+   	MUSB_EP0_STAGE_ACKWAIT,		/* after zlp, before statusin */
+   } __attribute__ ((packed));
+   
+ ! /* OTG protocol constants */
+   #define OTG_TIME_A_WAIT_VRISE	100		/* msec (max) */
+ ! #define OTG_TIME_A_WAIT_BCON	0		/* 0=infinite; min 1000 msec */
+ ! #define OTG_TIME_A_IDLE_BDIS	200		/* msec (min) */
+   
+   /*************************** REGISTER ACCESS ********************************/
+   
+ ***************
+ *** 162,195 ****
+    * directly with the "flat" model, or after setting up an index register.
+    */
+   
+ ! #if defined(CONFIG_ARCH_DAVINCI) || defined(CONFIG_SOC_OMAP2430) \
+ ! 		|| defined(CONFIG_SOC_OMAP3430) || defined(CONFIG_BLACKFIN) \
+ ! 		|| defined(CONFIG_ARCH_OMAP4)
+ ! /* REVISIT indexed access seemed to
+ !  * misbehave (on DaVinci) for at least peripheral IN ...
+ !  */
+ ! #define	MUSB_FLAT_REG
+ ! #endif
+ ! 
+ ! /* TUSB mapping: "flat" plus ep0 special cases */
+ ! #if defined(CONFIG_USB_MUSB_TUSB6010) || \
+ ! 	defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
+ ! #define musb_ep_select(_mbase, _epnum) \
+ ! 	musb_writeb((_mbase), MUSB_INDEX, (_epnum))
+ ! #define	MUSB_EP_OFFSET			MUSB_TUSB_OFFSET
+ ! 
+ ! /* "flat" mapping: each endpoint has its own i/o address */
+ ! #elif	defined(MUSB_FLAT_REG)
+ ! #define musb_ep_select(_mbase, _epnum)	(((void)(_mbase)), ((void)(_epnum)))
+ ! #define	MUSB_EP_OFFSET			MUSB_FLAT_OFFSET
+ ! 
+ ! /* "indexed" mapping: INDEX register controls register bank select */
+ ! #else
+ ! #define musb_ep_select(_mbase, _epnum) \
+ ! 	musb_writeb((_mbase), MUSB_INDEX, (_epnum))
+ ! #define	MUSB_EP_OFFSET			MUSB_INDEXED_OFFSET
+ ! #endif
+   
+   /****************************** FUNCTIONS ********************************/
+   
+   #define MUSB_HST_MODE(_musb)\
+ --- 154,165 ----
+    * directly with the "flat" model, or after setting up an index register.
+    */
+   
+ ! #define musb_ep_select(_musb, _mbase, _epnum) do { \
+ ! 	if (_musb->ops->flags & MUSB_GLUE_EP_ADDR_INDEXED_MAPPING) \
+ ! 		musb_writeb((_mbase), MUSB_INDEX, (_epnum)); \
+ !  } while (0)
+   
+ + #define	MUSB_EP_OFFSET	MUSB_OFFSET
+   /****************************** FUNCTIONS ********************************/
+   
+   #define MUSB_HST_MODE(_musb)\
+ ***************
+ *** 204,235 ****
+ --- 174,236 ----
+   
+   /******************************** TYPES *************************************/
+   
+ + #define     MUSB_GLUE_TUSB_STYLE   0x0001
+ + #define     MUSB_GLUE_EP_ADDR_FLAT_MAPPING	0x0002
+ + #define     MUSB_GLUE_EP_ADDR_INDEXED_MAPPING	0x0004
+ + #define		MUSB_GLUE_DMA_INVENTRA				0x0008
+ + #define		MUSB_GLUE_DMA_CPPI					0x0010
+ + #define		MUSB_GLUE_DMA_TUSB					0x0020
+ + #define		MUSB_GLUE_DMA_UX500					0x0040
+ + #define		MUSB_GLUE_DMA_CPPI41					0x0080
+ + 
+ + 
+   /**
+    * struct musb_platform_ops - Operations passed to musb_core by HW glue layer
+ +  * @fifo_mode: which fifo_mode is taken by me
+ +  * @flags:	each hw glue difference information will be here
+    * @init:	turns on clocks, sets up platform-specific registers, etc
+    * @exit:	undoes @init
+ +  * @read_fifo: read data from musb fifo in PIO
+ +  * @write_fifo: write data into musb fifo in PIO
+    * @set_mode:	forcefully changes operating mode
+    * @try_ilde:	tries to idle the IP
+ +  * @get_hw_revision: get hardware revision
+    * @vbus_status: returns vbus status if possible
+    * @set_vbus:	forces vbus status
+    * @adjust_channel_params: pre check for standard dma channel_program func
+ +  * @dma_controller_create: create dma controller for me
+ +  * @dma_controller_destroy: destroy dma controller
+    */
+   struct musb_platform_ops {
+ + 	short	fifo_mode;
+ + 	unsigned short	flags;
+   	int	(*init)(struct musb *musb);
+   	int	(*exit)(struct musb *musb);
+   
+   	void	(*enable)(struct musb *musb);
+   	void	(*disable)(struct musb *musb);
+   
+ + 	void (*read_fifo)(struct musb_hw_ep *hw_ep, u16 len, u8 *buf);
+ + 	void (*write_fifo)(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf);
+ + 
+   	int	(*set_mode)(struct musb *musb, u8 mode);
+   	void	(*try_idle)(struct musb *musb, unsigned long timeout);
+   
+ + 	u16  (*get_hw_revision)(struct musb *musb);
+ + 
+   	int	(*vbus_status)(struct musb *musb);
+   	void	(*set_vbus)(struct musb *musb, int on);
+   
+   	int	(*adjust_channel_params)(struct dma_channel *channel,
+   				u16 packet_sz, u8 *mode,
+   				dma_addr_t *dma_addr, u32 *len);
+ + 	struct dma_controller* (*dma_controller_create)(struct musb *,
+ + 		void __iomem *);
+ + 	void (*dma_controller_destroy)(struct dma_controller *);
+ + 	int (*simulate_babble_intr)(struct musb *musb);
+ + 	void (*txfifoempty_intr_enable)(struct musb *musb, u8 ep_num);
+ + 	void (*txfifoempty_intr_disable)(struct musb *musb, u8 ep_num);
+ + 	void (*reinit)(u16 musb_type, struct musb *musb);
+   };
+   
+   /*
+ ***************
+ *** 242,251 ****
+   	void __iomem		*fifo;
+   	void __iomem		*regs;
+   
+ ! #if defined(CONFIG_USB_MUSB_TUSB6010) || \
+ ! 	defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
+   	void __iomem		*conf;
+ - #endif
+   
+   	/* index in musb->endpoints[]  */
+   	u8			epnum;
+ --- 243,250 ----
+   	void __iomem		*fifo;
+   	void __iomem		*regs;
+   
+ ! 	/*Fixme: the following field is only used by tusb*/
+   	void __iomem		*conf;
+   
+   	/* index in musb->endpoints[]  */
+   	u8			epnum;
+ ***************
+ *** 260,272 ****
+   	struct dma_channel	*tx_channel;
+   	struct dma_channel	*rx_channel;
+   
+ ! #if defined(CONFIG_USB_MUSB_TUSB6010) || \
+ ! 	defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
+ ! 	/* TUSB has "asynchronous" and "synchronous" dma modes */
+   	dma_addr_t		fifo_async;
+   	dma_addr_t		fifo_sync;
+   	void __iomem		*fifo_sync_va;
+ - #endif
+   
+   	void __iomem		*target_regs;
+   
+ --- 259,271 ----
+   	struct dma_channel	*tx_channel;
+   	struct dma_channel	*rx_channel;
+   
+ ! 	/*
+ ! 	 * TUSB has "asynchronous" and "synchronous" dma modes
+ ! 	 * Fixme: the following three fields are only valid for TUSB.
+ ! 	 * */
+   	dma_addr_t		fifo_async;
+   	dma_addr_t		fifo_sync;
+   	void __iomem		*fifo_sync_va;
+   
+   	void __iomem		*target_regs;
+   
+ ***************
+ *** 280,285 ****
+ --- 279,287 ----
+   	/* peripheral side */
+   	struct musb_ep		ep_in;			/* TX */
+   	struct musb_ep		ep_out;			/* RX */
+ + 
+ + 	u8			prev_toggle;		/* Rx */
+ + 	u8			xfer_type;
+   };
+   
+   static inline struct musb_request *next_in_request(struct musb_hw_ep *hw_ep)
+ ***************
+ *** 311,316 ****
+ --- 313,319 ----
+   	u8 index, testmode;
+   
+   	u8 devctl, busctl, misc;
+ + 	u32 otg_interfsel;
+   
+   	struct musb_csr_regs index_regs[MUSB_C_NUM_EPS];
+   };
+ ***************
+ *** 327,332 ****
+ --- 330,338 ----
+   
+   	irqreturn_t		(*isr)(int, void *);
+   	struct work_struct	irq_work;
+ + 	struct work_struct      work;
+ + 	struct work_struct	otg_notifier_work;
+ + 	u8                      enable_babble_work;
+   	u16			hwvers;
+   
+   /* this hub status bit is reserved by USB 2.0 and not seen by usbcore */
+ ***************
+ *** 350,356 ****
+   	struct list_head	in_bulk;	/* of musb_qh */
+   	struct list_head	out_bulk;	/* of musb_qh */
+   
+ ! 	struct timer_list	otg_timer;
+   	struct notifier_block	nb;
+   
+   	struct dma_controller	*dma_controller;
+ --- 356,366 ----
+   	struct list_head	in_bulk;	/* of musb_qh */
+   	struct list_head	out_bulk;	/* of musb_qh */
+   
+ ! 	struct workqueue_struct *gb_queue;
+ ! 	struct work_struct      gb_work;
+ ! 	spinlock_t              gb_lock;
+ ! 	struct list_head        gb_list;        /* of urbs */
+ ! 
+   	struct notifier_block	nb;
+   
+   	struct dma_controller	*dma_controller;
+ ***************
+ *** 359,370 ****
+   	void __iomem		*ctrl_base;
+   	void __iomem		*mregs;
+   
+ ! #if defined(CONFIG_USB_MUSB_TUSB6010) || \
+ ! 	defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
+   	dma_addr_t		async;
+   	dma_addr_t		sync;
+   	void __iomem		*sync_va;
+ - #endif
+   
+   	/* passed down from chip/board specific irq handlers */
+   	u8			int_usb;
+ --- 369,378 ----
+   	void __iomem		*ctrl_base;
+   	void __iomem		*mregs;
+   
+ ! 	/*Fixme: the three fields below are only used by tusb*/
+   	dma_addr_t		async;
+   	dma_addr_t		sync;
+   	void __iomem		*sync_va;
+   
+   	/* passed down from chip/board specific irq handlers */
+   	u8			int_usb;
+ ***************
+ *** 372,377 ****
+ --- 380,386 ----
+   	u16			int_tx;
+   
+   	struct otg_transceiver	*xceiv;
+ + 	u8			xceiv_event;
+   
+   	int nIrq;
+   	unsigned		irq_wake:1;
+ ***************
+ *** 454,459 ****
+ --- 463,486 ----
+   #ifdef MUSB_CONFIG_PROC_FS
+   	struct proc_dir_entry *proc_entry;
+   #endif
+ + 	/* id for multiple musb instances */
+ + 	u8			id;
+ + 	struct	timer_list	otg_workaround;
+ + 	unsigned long		last_timer;
+ + 	int			first;
+ + 	int			old_state;
+ + 	struct	timer_list	otg_timer;
+ + 	u8			en_otg_timer;
+ + 	u8			en_otgw_timer;
+ + #ifndef CONFIG_MUSB_PIO_ONLY
+ + 	u64			*orig_dma_mask;
+ + #endif
+ + 	short			fifo_mode;
+ + 	u8			txfifo_intr_enable;
+ + 	u8			datatog_fix;
+ + 	u8			hw_babble_ctrl;
+ + 	u8			sof_enabled;
+ + 	u32			sof_cnt;
+   };
+   
+   static inline struct musb *gadget_to_musb(struct usb_gadget *g)
+ ***************
+ *** 496,502 ****
+   	u8 reg = 0;
+   
+   	/* read from core using indexed model */
+ ! 	reg = musb_readb(mbase, MUSB_EP_OFFSET(epnum, MUSB_FIFOSIZE));
+   	/* 0's returned when no more endpoints */
+   	if (!reg)
+   		return -ENODEV;
+ --- 523,529 ----
+   	u8 reg = 0;
+   
+   	/* read from core using indexed model */
+ ! 	reg = musb_readb(mbase, MUSB_EP_OFFSET(musb, epnum, MUSB_FIFOSIZE));
+   	/* 0's returned when no more endpoints */
+   	if (!reg)
+   		return -ENODEV;
+ ***************
+ *** 544,549 ****
+ --- 571,588 ----
+   
+   extern void musb_hnp_stop(struct musb *musb);
+   
+ + static inline void txfifoempty_int_enable(struct musb *musb, u8 ep_num)
+ + {
+ + 	if (musb->ops->txfifoempty_intr_enable)
+ + 		musb->ops->txfifoempty_intr_enable(musb, ep_num);
+ + }
+ + 
+ + static inline void txfifoempty_int_disable(struct musb *musb, u8 ep_num)
+ + {
+ + 	if (musb->ops->txfifoempty_intr_disable)
+ + 		musb->ops->txfifoempty_intr_disable(musb, ep_num);
+ + }
+ + 
+   static inline void musb_platform_set_vbus(struct musb *musb, int is_on)
+   {
+   	if (musb->ops->set_vbus)
+ ***************
+ *** 601,604 ****
+ --- 640,687 ----
+   	return musb->ops->exit(musb);
+   }
+   
+ + static inline u16 musb_platform_get_hw_revision(struct musb *musb)
+ + {
+ + 	if (!musb->ops->get_hw_revision)
+ + 		return musb_readw(musb->mregs, MUSB_HWVERS);
+ + 
+ + 	return musb->ops->get_hw_revision(musb);
+ + }
+ + 
+ + static inline int musb_simulate_babble_intr(struct musb *musb)
+ + {
+ + 	if (!musb->ops->simulate_babble_intr)
+ + 		return -EINVAL;
+ + 
+ + 	return musb->ops->simulate_babble_intr(musb);
+ + }
+ + 
+ + static inline const char *get_dma_name(struct musb *musb)
+ + {
+ + #ifdef CONFIG_MUSB_PIO_ONLY
+ + 	return "pio";
+ + #else
+ + 	if (musb->ops->flags & MUSB_GLUE_DMA_INVENTRA)
+ + 		return "dma-inventra";
+ + 	else if (musb->ops->flags & MUSB_GLUE_DMA_CPPI)
+ + 		return "dma-cppi3";
+ + 	else if (musb->ops->flags & MUSB_GLUE_DMA_CPPI41)
+ + 		return "dma-cppi41";
+ + 	else if (musb->ops->flags & MUSB_GLUE_DMA_TUSB)
+ + 		return "dma-tusb-omap";
+ + 	else
+ + 		return "?dma?";
+ + #endif
+ + }
+ + extern void musb_reinit(u16 musb_type, struct musb *musb);
+ + 
+ + extern void musb_gb_work(struct work_struct *data);
+ + /*-------------------------- ProcFS definitions ---------------------*/
+ + 
+ + struct proc_dir_entry;
+ + 
+ + extern struct proc_dir_entry *musb_debug_create(char *name, struct musb *data);
+ + extern void musb_debug_delete(char *name, struct musb *data);
+ + extern void musb_save_context(struct musb *musb);
+ + extern void musb_restore_context(struct musb *musb);
+   #endif	/* __MUSB_CORE_H__ */
+ diff -crN linux-3.2.1_o/drivers/usb/musb/musb_debugfs.c linux-3.2.1/drivers/usb/musb/musb_debugfs.c
+ *** linux-3.2.1_o/drivers/usb/musb/musb_debugfs.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/musb/musb_debugfs.c	2014-11-25 13:19:16.644109094 +0900
+ ***************
+ *** 33,43 ****
+   
+   #include <linux/module.h>
+   #include <linux/kernel.h>
+ - #include <linux/sched.h>
+   #include <linux/init.h>
+ - #include <linux/list.h>
+ - #include <linux/platform_device.h>
+ - #include <linux/io.h>
+   #include <linux/debugfs.h>
+   #include <linux/seq_file.h>
+   
+ --- 33,39 ----
+ ***************
+ *** 46,55 ****
+   #include "musb_core.h"
+   #include "musb_debug.h"
+   
+ - #ifdef CONFIG_ARCH_DAVINCI
+ - #include "davinci.h"
+ - #endif
+ - 
+   struct musb_register_map {
+   	char			*name;
+   	unsigned		offset;
+ --- 42,47 ----
+ ***************
+ *** 111,117 ****
+   	{  }	/* Terminating Entry */
+   };
+   
+ ! static struct dentry *musb_debugfs_root;
+   
+   static int musb_regdump_show(struct seq_file *s, void *unused)
+   {
+ --- 103,109 ----
+   	{  }	/* Terminating Entry */
+   };
+   
+ ! static struct dentry *musb_debugfs_root[2];
+   
+   static int musb_regdump_show(struct seq_file *s, void *unused)
+   {
+ ***************
+ *** 231,236 ****
+ --- 223,229 ----
+   		test = MUSB_TEST_SE0_NAK;
+   
+   	musb_writeb(musb->mregs, MUSB_TESTMODE, test);
+ + 	pr_info("%smusb%d: test-mode value %x\n", buf, musb->id, test);
+   
+   	return count;
+   }
+ ***************
+ *** 243,255 ****
+   	.release		= single_release,
+   };
+   
+ ! int __init musb_init_debugfs(struct musb *musb)
+   {
+   	struct dentry		*root;
+   	struct dentry		*file;
+   	int			ret;
+   
+ ! 	root = debugfs_create_dir("musb", NULL);
+   	if (IS_ERR(root)) {
+   		ret = PTR_ERR(root);
+   		goto err0;
+ --- 236,248 ----
+   	.release		= single_release,
+   };
+   
+ ! int __devinit musb_init_debugfs(struct musb *musb)
+   {
+   	struct dentry		*root;
+   	struct dentry		*file;
+   	int			ret;
+   
+ ! 	root = debugfs_create_dir(dev_name(musb->controller), NULL);
+   	if (IS_ERR(root)) {
+   		ret = PTR_ERR(root);
+   		goto err0;
+ ***************
+ *** 269,275 ****
+   		goto err1;
+   	}
+   
+ ! 	musb_debugfs_root = root;
+   
+   	return 0;
+   
+ --- 262,268 ----
+   		goto err1;
+   	}
+   
+ ! 	musb_debugfs_root[musb->id] = root;
+   
+   	return 0;
+   
+ ***************
+ *** 280,286 ****
+   	return ret;
+   }
+   
+ ! void /* __init_or_exit */ musb_exit_debugfs(struct musb *musb)
+   {
+ ! 	debugfs_remove_recursive(musb_debugfs_root);
+   }
+ --- 273,279 ----
+   	return ret;
+   }
+   
+ ! void /* __devinit_or_exit */ musb_exit_debugfs(struct musb *musb)
+   {
+ ! 	debugfs_remove_recursive(musb_debugfs_root[musb->id]);
+   }
+ diff -crN linux-3.2.1_o/drivers/usb/musb/musb_debug.h linux-3.2.1/drivers/usb/musb/musb_debug.h
+ *** linux-3.2.1_o/drivers/usb/musb/musb_debug.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/musb/musb_debug.h	2014-11-25 13:19:16.648107419 +0900
+ ***************
+ *** 43,50 ****
+   #define ERR(fmt, args...) yprintk(KERN_ERR, fmt, ## args)
+   
+   #ifdef CONFIG_DEBUG_FS
+ ! extern int musb_init_debugfs(struct musb *musb);
+ ! extern void musb_exit_debugfs(struct musb *musb);
+   #else
+   static inline int musb_init_debugfs(struct musb *musb)
+   {
+ --- 43,50 ----
+   #define ERR(fmt, args...) yprintk(KERN_ERR, fmt, ## args)
+   
+   #ifdef CONFIG_DEBUG_FS
+ ! int musb_init_debugfs(struct musb *musb);
+ ! void musb_exit_debugfs(struct musb *musb);
+   #else
+   static inline int musb_init_debugfs(struct musb *musb)
+   {
+ diff -crN linux-3.2.1_o/drivers/usb/musb/musb_dma.h linux-3.2.1/drivers/usb/musb/musb_dma.h
+ *** linux-3.2.1_o/drivers/usb/musb/musb_dma.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/musb/musb_dma.h	2014-11-25 13:19:16.651257762 +0900
+ ***************
+ *** 68,83 ****
+   #define	is_dma_capable()	(0)
+   #endif
+   
+   #ifdef CONFIG_USB_TI_CPPI_DMA
+ ! #define	is_cppi_enabled()	1
+   #else
+ ! #define	is_cppi_enabled()	0
+   #endif
+   
+   #ifdef CONFIG_USB_TUSB_OMAP_DMA
+ ! #define tusb_dma_omap()			1
+   #else
+ ! #define tusb_dma_omap()			0
+   #endif
+   
+   /* Anomaly 05000456 - USB Receive Interrupt Is Not Generated in DMA Mode 1
+ --- 68,102 ----
+   #define	is_dma_capable()	(0)
+   #endif
+   
+ + #ifdef CONFIG_USB_UX500_DMA
+ + #define	is_ux500_dma(musb)	(musb->ops->flags & MUSB_GLUE_DMA_UX500)
+ + #else
+ + #define	is_ux500_dma(musb)	0
+ + #endif
+ + 
+ + #ifdef CONFIG_USB_INVENTRA_DMA
+ + #define	is_inventra_dma(musb)	(musb->ops->flags & MUSB_GLUE_DMA_INVENTRA)
+ + #else
+ + #define	is_inventra_dma(musb)	0
+ + #endif
+ + 
+   #ifdef CONFIG_USB_TI_CPPI_DMA
+ ! #define	is_cppi_enabled(musb)	(musb->ops->flags & MUSB_GLUE_DMA_CPPI)
+ ! 
+ ! #else
+ ! #define	is_cppi_enabled(musb)	0
+ ! #endif
+ ! 
+ ! #ifdef CONFIG_USB_TI_CPPI41_DMA
+ ! #define is_cppi41_enabled(musb)	(musb->ops->flags & MUSB_GLUE_DMA_CPPI41)
+   #else
+ ! #define is_cppi41_enabled(musb)     0
+   #endif
+   
+   #ifdef CONFIG_USB_TUSB_OMAP_DMA
+ ! #define tusb_dma_omap(musb)		(musb->ops->flags & MUSB_GLUE_DMA_TUSB)
+   #else
+ ! #define tusb_dma_omap(musb)		0
+   #endif
+   
+   /* Anomaly 05000456 - USB Receive Interrupt Is Not Generated in DMA Mode 1
+ ***************
+ *** 178,186 ****
+   extern void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit);
+   
+   
+ ! extern struct dma_controller *__init
+ ! dma_controller_create(struct musb *, void __iomem *);
+   
+ ! extern void dma_controller_destroy(struct dma_controller *);
+   
+   #endif	/* __MUSB_DMA_H__ */
+ --- 197,268 ----
+   extern void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit);
+   
+   
+ ! #ifdef CONFIG_USB_TI_CPPI_DMA
+ ! extern struct dma_controller *__devinit
+ ! cppi_dma_controller_create(struct musb *, void __iomem *);
+ ! 
+ ! extern void cppi_dma_controller_destroy(struct dma_controller *);
+ ! #else
+ ! static inline struct dma_controller *__devinit
+ ! cppi_dma_controller_create(struct musb *musb, void __iomem *mregs)
+ ! {
+ ! 	return NULL;
+ ! }
+ ! 
+ ! static inline void cppi_dma_controller_destroy(struct dma_controller *c)
+ ! {
+ ! }
+ ! #endif
+ ! 
+ ! #ifdef CONFIG_USB_TI_CPPI41_DMA
+ ! extern struct dma_controller *__devinit
+ ! cppi41_dma_controller_create(struct musb *, void __iomem *);
+ ! 
+ ! extern void cppi41_dma_controller_destroy(struct dma_controller *);
+ ! #else
+ ! static inline struct dma_controller *__devinit
+ ! cppi41_dma_controller_create(struct musb *musb, void __iomem *mregs)
+ ! {
+ ! 	return NULL;
+ ! }
+ ! 
+ ! static inline void cppi41_dma_controller_destroy(struct dma_controller *c)
+ ! {
+ ! }
+ ! #endif
+ ! 
+ ! #ifdef CONFIG_USB_INVENTRA_DMA
+ ! extern struct dma_controller *__devinit
+ ! inventra_dma_controller_create(struct musb *, void __iomem *);
+ ! 
+ ! extern void inventra_dma_controller_destroy(struct dma_controller *);
+ ! #else
+ ! static inline struct dma_controller *__devinit
+ ! inventra_dma_controller_create(struct musb *musb, void __iomem *mregs)
+ ! {
+ ! 	return NULL;
+ ! }
+   
+ ! static inline void inventra_dma_controller_destroy(struct dma_controller *c)
+ ! {
+ ! }
+ ! #endif
+ ! 
+ ! #ifdef CONFIG_USB_TUSB_OMAP_DMA
+ ! extern struct dma_controller *__devinit
+ ! tusb_dma_controller_create(struct musb *, void __iomem *);
+ ! 
+ ! extern void tusb_dma_controller_destroy(struct dma_controller *);
+ ! #else
+ ! static inline struct dma_controller *__devinit
+ ! tusb_dma_controller_create(struct musb *musb, void __iomem *mregs)
+ ! {
+ ! 	return NULL;
+ ! }
+ ! 
+ ! static inline void tusb_dma_controller_destroy(struct dma_controller *c)
+ ! {
+ ! }
+ ! #endif
+   
+   #endif	/* __MUSB_DMA_H__ */
+ diff -crN linux-3.2.1_o/drivers/usb/musb/musb_gadget.c linux-3.2.1/drivers/usb/musb/musb_gadget.c
+ *** linux-3.2.1_o/drivers/usb/musb/musb_gadget.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/musb/musb_gadget.c	2014-11-25 13:19:16.660060746 +0900
+ ***************
+ *** 40,47 ****
+   #include <linux/smp.h>
+   #include <linux/spinlock.h>
+   #include <linux/delay.h>
+ - #include <linux/moduleparam.h>
+ - #include <linux/stat.h>
+   #include <linux/dma-mapping.h>
+   #include <linux/slab.h>
+   
+ --- 40,45 ----
+ ***************
+ *** 278,285 ****
+   }
+   
+   
+ - #ifdef CONFIG_USB_INVENTRA_DMA
+ - 
+   /* Peripheral tx (IN) using Mentor DMA works as follows:
+   	Only mode 0 is used for transfers <= wPktSize,
+   	mode 1 is used for larger transfers,
+ --- 276,281 ----
+ ***************
+ *** 310,317 ****
+    * upleveling from irq-per-packet to irq-per-buffer.
+    */
+   
+ - #endif
+ - 
+   /*
+    * An endpoint is transmitting data. This can be called either from
+    * the IRQ routine or from ep.queue() to kickstart a request on an
+ --- 306,311 ----
+ ***************
+ *** 372,379 ****
+   
+   		/* MUSB_TXCSR_P_ISO is still set correctly */
+   
+ ! #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
+ ! 		{
+   			if (request_size < musb_ep->packet_sz)
+   				musb_ep->dma->desired_mode = 0;
+   			else
+ --- 366,372 ----
+   
+   		/* MUSB_TXCSR_P_ISO is still set correctly */
+   
+ ! 		if (is_inventra_dma(musb) || is_ux500_dma(musb)) {
+   			if (request_size < musb_ep->packet_sz)
+   				musb_ep->dma->desired_mode = 0;
+   			else
+ ***************
+ *** 410,458 ****
+   
+   				musb_writew(epio, MUSB_TXCSR, csr);
+   			}
+ ! 		}
+ ! 
+ ! #elif defined(CONFIG_USB_TI_CPPI_DMA)
+ ! 		/* program endpoint CSR first, then setup DMA */
+ ! 		csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
+ ! 		csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
+ ! 		       MUSB_TXCSR_MODE;
+ ! 		musb_writew(epio, MUSB_TXCSR,
+ ! 			(MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN)
+ ! 				| csr);
+   
+ ! 		/* ensure writebuffer is empty */
+ ! 		csr = musb_readw(epio, MUSB_TXCSR);
+   
+ ! 		/* NOTE host side sets DMAENAB later than this; both are
+ ! 		 * OK since the transfer dma glue (between CPPI and Mentor
+ ! 		 * fifos) just tells CPPI it could start.  Data only moves
+ ! 		 * to the USB TX fifo when both fifos are ready.
+ ! 		 */
+   
+ ! 		/* "mode" is irrelevant here; handle terminating ZLPs like
+ ! 		 * PIO does, since the hardware RNDIS mode seems unreliable
+ ! 		 * except for the last-packet-is-already-short case.
+ ! 		 */
+ ! 		use_dma = use_dma && c->channel_program(
+ ! 				musb_ep->dma, musb_ep->packet_sz,
+ ! 				0,
+ ! 				request->dma + request->actual,
+ ! 				request_size);
+ ! 		if (!use_dma) {
+ ! 			c->channel_release(musb_ep->dma);
+ ! 			musb_ep->dma = NULL;
+ ! 			csr &= ~MUSB_TXCSR_DMAENAB;
+ ! 			musb_writew(epio, MUSB_TXCSR, csr);
+ ! 			/* invariant: prequest->buf is non-null */
+   		}
+ - #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
+ - 		use_dma = use_dma && c->channel_program(
+ - 				musb_ep->dma, musb_ep->packet_sz,
+ - 				request->zero,
+ - 				request->dma + request->actual,
+ - 				request_size);
+ - #endif
+   	}
+   #endif
+   
+ --- 403,460 ----
+   
+   				musb_writew(epio, MUSB_TXCSR, csr);
+   			}
+ ! 		} else if (is_cppi_enabled(musb) || is_cppi41_enabled(musb)) {
+ ! 			/* program endpoint CSR first, then setup DMA */
+ ! 			csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
+ ! 
+ ! 			if (request_size == 0)
+ ! 				csr &= ~(MUSB_TXCSR_DMAENAB |
+ ! 					MUSB_TXCSR_DMAMODE);
+ ! 			else
+ ! 				csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
+ ! 				       MUSB_TXCSR_MODE;
+ ! 			musb_writew(epio, MUSB_TXCSR,
+ ! 				(MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN)
+ ! 					| csr);
+   
+ ! 			/* ensure writebuffer is empty */
+ ! 			csr = musb_readw(epio, MUSB_TXCSR);
+   
+ ! 			/* NOTE host side sets DMAENAB later than this; both are
+ ! 			 * OK since the transfer dma glue (between CPPI & Mentor
+ ! 			 * fifos) just tells CPPI it could start.  Data only
+ ! 			 * moves to the USB TX fifo when both fifos are ready.
+ ! 			 */
+   
+ ! 			/* "mode" is irrelevant here; handle terminating ZLPs
+ ! 			 * like PIO does, since the hardware RNDIS mode seems
+ ! 			 * unreliable except for the last-packet-is-already-
+ ! 			 * short case.
+ ! 			 */
+ ! 			/* for zero byte transfer use pio mode */
+ ! 			if (request_size == 0)
+ ! 				use_dma = 0;
+ ! 			else {
+ ! 				use_dma = use_dma && c->channel_program(
+ ! 					musb_ep->dma, musb_ep->packet_sz,
+ ! 					0,
+ ! 					request->dma + request->actual,
+ ! 					request_size);
+ ! 				if (!use_dma) {
+ ! 					c->channel_release(musb_ep->dma);
+ ! 					musb_ep->dma = NULL;
+ ! 					csr &= ~MUSB_TXCSR_DMAENAB;
+ ! 					musb_writew(epio, MUSB_TXCSR, csr);
+ ! 				/* invariant: prequest->buf is non-null */
+ ! 				}
+ ! 			}
+ ! 		} else if (tusb_dma_omap(musb)) {
+ ! 			use_dma = use_dma && c->channel_program(
+ ! 					musb_ep->dma, musb_ep->packet_sz,
+ ! 					request->zero,
+ ! 					request->dma + request->actual,
+ ! 					request_size);
+   		}
+   	}
+   #endif
+   
+ ***************
+ *** 463,469 ****
+   		 */
+   		unmap_dma_buffer(req, musb);
+   
+ ! 		musb_write_fifo(musb_ep->hw_ep, fifo_count,
+   				(u8 *) (request->buf + request->actual));
+   		request->actual += fifo_count;
+   		csr |= MUSB_TXCSR_TXPKTRDY;
+ --- 465,471 ----
+   		 */
+   		unmap_dma_buffer(req, musb);
+   
+ ! 		musb->ops->write_fifo(musb_ep->hw_ep, fifo_count,
+   				(u8 *) (request->buf + request->actual));
+   		request->actual += fifo_count;
+   		csr |= MUSB_TXCSR_TXPKTRDY;
+ ***************
+ *** 494,500 ****
+   	void __iomem		*epio = musb->endpoints[epnum].regs;
+   	struct dma_channel	*dma;
+   
+ ! 	musb_ep_select(mbase, epnum);
+   	req = next_request(musb_ep);
+   	request = &req->request;
+   
+ --- 496,502 ----
+   	void __iomem		*epio = musb->endpoints[epnum].regs;
+   	struct dma_channel	*dma;
+   
+ ! 	musb_ep_select(musb, mbase, epnum);
+   	req = next_request(musb_ep);
+   	request = &req->request;
+   
+ ***************
+ *** 555,565 ****
+   		if ((request->zero && request->length
+   			&& (request->length % musb_ep->packet_sz == 0)
+   			&& (request->actual == request->length))
+ ! #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
+ ! 			|| (is_dma && (!dma->desired_mode ||
+ ! 				(request->actual &
+ ! 					(musb_ep->packet_sz - 1))))
+ ! #endif
+   		) {
+   			/*
+   			 * On DMA completion, FIFO may not be
+ --- 557,565 ----
+   		if ((request->zero && request->length
+   			&& (request->length % musb_ep->packet_sz == 0)
+   			&& (request->actual == request->length))
+ ! 			|| ((is_inventra_dma(musb) || is_ux500_dma(musb)) &&
+ ! 			is_dma && (!dma->desired_mode || (request->actual &
+ ! 			(musb_ep->packet_sz - 1))))
+   		) {
+   			/*
+   			 * On DMA completion, FIFO may not be
+ ***************
+ *** 590,597 ****
+   
+   /* ------------------------------------------------------------ */
+   
+ - #ifdef CONFIG_USB_INVENTRA_DMA
+ - 
+   /* Peripheral rx (OUT) using Mentor DMA works as follows:
+   	- Only mode 0 is used.
+   
+ --- 590,595 ----
+ ***************
+ *** 619,626 ****
+    * Non-Mentor DMA engines can of course work differently.
+    */
+   
+ - #endif
+ - 
+   /*
+    * Context: controller locked, IRQs blocked, endpoint selected
+    */
+ --- 617,622 ----
+ ***************
+ *** 655,661 ****
+   		return;
+   	}
+   
+ ! 	if (is_cppi_enabled() && is_buffer_mapped(req)) {
+   		struct dma_controller	*c = musb->dma_controller;
+   		struct dma_channel	*channel = musb_ep->dma;
+   
+ --- 651,658 ----
+   		return;
+   	}
+   
+ ! 	if ((is_cppi_enabled(musb) || is_cppi41_enabled(musb)) &&
+ ! 					is_buffer_mapped(req)) {
+   		struct dma_controller	*c = musb->dma_controller;
+   		struct dma_channel	*channel = musb_ep->dma;
+   
+ ***************
+ *** 697,704 ****
+   			use_mode_1 = 0;
+   
+   		if (request->actual < request->length) {
+ ! #ifdef CONFIG_USB_INVENTRA_DMA
+ ! 			if (is_buffer_mapped(req)) {
+   				struct dma_controller	*c;
+   				struct dma_channel	*channel;
+   				int			use_dma = 0;
+ --- 694,700 ----
+   			use_mode_1 = 0;
+   
+   		if (request->actual < request->length) {
+ ! 			if (is_buffer_mapped(req) && is_inventra_dma(musb)) {
+   				struct dma_controller	*c;
+   				struct dma_channel	*channel;
+   				int			use_dma = 0;
+ ***************
+ *** 775,782 ****
+   				if (use_dma)
+   					return;
+   			}
+ ! #elif defined(CONFIG_USB_UX500_DMA)
+ ! 			if ((is_buffer_mapped(req)) &&
+   				(request->actual < request->length)) {
+   
+   				struct dma_controller *c;
+ --- 771,777 ----
+   				if (use_dma)
+   					return;
+   			}
+ ! 			if (is_ux500_dma(musb) && (is_buffer_mapped(req)) &&
+   				(request->actual < request->length)) {
+   
+   				struct dma_controller *c;
+ ***************
+ *** 822,828 ****
+   
+   					return;
+   			}
+ - #endif	/* Mentor's DMA */
+   
+   			fifo_count = request->length - request->actual;
+   			dev_dbg(musb->controller, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
+ --- 817,822 ----
+ ***************
+ *** 832,839 ****
+   
+   			fifo_count = min_t(unsigned, len, fifo_count);
+   
+ ! #ifdef	CONFIG_USB_TUSB_OMAP_DMA
+ ! 			if (tusb_dma_omap() && is_buffer_mapped(req)) {
+   				struct dma_controller *c = musb->dma_controller;
+   				struct dma_channel *channel = musb_ep->dma;
+   				u32 dma_addr = request->dma + request->actual;
+ --- 826,832 ----
+   
+   			fifo_count = min_t(unsigned, len, fifo_count);
+   
+ ! 			if (tusb_dma_omap(musb) && is_buffer_mapped(req)) {
+   				struct dma_controller *c = musb->dma_controller;
+   				struct dma_channel *channel = musb_ep->dma;
+   				u32 dma_addr = request->dma + request->actual;
+ ***************
+ *** 847,853 ****
+   				if (ret)
+   					return;
+   			}
+ ! #endif
+   			/*
+   			 * Unmap the dma buffer back to cpu if dma channel
+   			 * programming fails. This buffer is mapped if the
+ --- 840,846 ----
+   				if (ret)
+   					return;
+   			}
+ ! 
+   			/*
+   			 * Unmap the dma buffer back to cpu if dma channel
+   			 * programming fails. This buffer is mapped if the
+ ***************
+ *** 864,870 ****
+   				musb_writew(epio, MUSB_RXCSR, csr);
+   			}
+   
+ ! 			musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
+   					(request->buf + request->actual));
+   			request->actual += fifo_count;
+   
+ --- 857,863 ----
+   				musb_writew(epio, MUSB_RXCSR, csr);
+   			}
+   
+ ! 			musb->ops->read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
+   					(request->buf + request->actual));
+   			request->actual += fifo_count;
+   
+ ***************
+ *** 903,909 ****
+   	else
+   		musb_ep = &hw_ep->ep_out;
+   
+ ! 	musb_ep_select(mbase, epnum);
+   
+   	req = next_request(musb_ep);
+   	if (!req)
+ --- 896,902 ----
+   	else
+   		musb_ep = &hw_ep->ep_out;
+   
+ ! 	musb_ep_select(musb, mbase, epnum);
+   
+   	req = next_request(musb_ep);
+   	if (!req)
+ ***************
+ *** 959,999 ****
+   			musb_readw(epio, MUSB_RXCSR),
+   			musb_ep->dma->actual_len, request);
+   
+ ! #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
+ ! 	defined(CONFIG_USB_UX500_DMA)
+ ! 		/* Autoclear doesn't clear RxPktRdy for short packets */
+ ! 		if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered)
+ ! 				|| (dma->actual_len
+ ! 					& (musb_ep->packet_sz - 1))) {
+ ! 			/* ack the read! */
+ ! 			csr &= ~MUSB_RXCSR_RXPKTRDY;
+ ! 			musb_writew(epio, MUSB_RXCSR, csr);
+ ! 		}
+   
+ ! 		/* incomplete, and not short? wait for next IN packet */
+ ! 		if ((request->actual < request->length)
+ ! 				&& (musb_ep->dma->actual_len
+ ! 					== musb_ep->packet_sz)) {
+ ! 			/* In double buffer case, continue to unload fifo if
+ !  			 * there is Rx packet in FIFO.
+ !  			 **/
+ ! 			csr = musb_readw(epio, MUSB_RXCSR);
+ ! 			if ((csr & MUSB_RXCSR_RXPKTRDY) &&
+ ! 				hw_ep->rx_double_buffered)
+ ! 				goto exit;
+ ! 			return;
+   		}
+ - #endif
+   		musb_g_giveback(musb_ep, request, 0);
+   
+   		req = next_request(musb_ep);
+   		if (!req)
+   			return;
+   	}
+ - #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
+ - 	defined(CONFIG_USB_UX500_DMA)
+ - exit:
+ - #endif
+   	/* Analyze request */
+   	rxstate(musb, req);
+   }
+ --- 952,988 ----
+   			musb_readw(epio, MUSB_RXCSR),
+   			musb_ep->dma->actual_len, request);
+   
+ ! 		if (is_inventra_dma(musb) || tusb_dma_omap(musb)
+ ! 				|| is_ux500_dma(musb)) {
+ ! 			/* Autoclear doesn't clear RxPktRdy for short packets */
+ ! 			if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered)
+ ! 					|| (dma->actual_len
+ ! 						& (musb_ep->packet_sz - 1))) {
+ ! 				/* ack the read! */
+ ! 				csr &= ~MUSB_RXCSR_RXPKTRDY;
+ ! 				musb_writew(epio, MUSB_RXCSR, csr);
+ ! 			}
+   
+ ! 			/* incomplete, and not short? wait for next IN packet */
+ ! 			if ((request->actual < request->length)
+ ! 					&& (musb_ep->dma->actual_len
+ ! 						== musb_ep->packet_sz)) {
+ ! 				/* In double buffer case, continue to unload
+ ! 				 * fifo if there is Rx packet in FIFO.
+ ! 				 **/
+ ! 				csr = musb_readw(epio, MUSB_RXCSR);
+ ! 				if ((csr & MUSB_RXCSR_RXPKTRDY) &&
+ ! 					hw_ep->rx_double_buffered)
+ ! 					rxstate(musb, to_musb_request(request));
+ ! 				return;
+ ! 			}
+   		}
+   		musb_g_giveback(musb_ep, request, 0);
+   
+   		req = next_request(musb_ep);
+   		if (!req)
+   			return;
+   	}
+   	/* Analyze request */
+   	rxstate(musb, req);
+   }
+ ***************
+ *** 1031,1036 ****
+ --- 1020,1026 ----
+   		goto fail;
+   	}
+   	musb_ep->type = usb_endpoint_type(desc);
+ + 	hw_ep->xfer_type = musb_ep->type;
+   
+   	/* check direction and (later) maxpacket size against endpoint */
+   	if (usb_endpoint_num(desc) != epnum)
+ ***************
+ *** 1061,1067 ****
+   	/* enable the interrupts for the endpoint, set the endpoint
+   	 * packet size (or fail), set the mode, clear the fifo
+   	 */
+ ! 	musb_ep_select(mbase, epnum);
+   	if (usb_endpoint_dir_in(desc)) {
+   		u16 int_txe = musb_readw(mbase, MUSB_INTRTXE);
+   
+ --- 1051,1057 ----
+   	/* enable the interrupts for the endpoint, set the endpoint
+   	 * packet size (or fail), set the mode, clear the fifo
+   	 */
+ ! 	musb_ep_select(musb, mbase, epnum);
+   	if (usb_endpoint_dir_in(desc)) {
+   		u16 int_txe = musb_readw(mbase, MUSB_INTRTXE);
+   
+ ***************
+ *** 1200,1206 ****
+   	epio = musb->endpoints[epnum].regs;
+   
+   	spin_lock_irqsave(&musb->lock, flags);
+ ! 	musb_ep_select(musb->mregs, epnum);
+   
+   	/* zero the endpoint sizes */
+   	if (musb_ep->is_in) {
+ --- 1190,1196 ----
+   	epio = musb->endpoints[epnum].regs;
+   
+   	spin_lock_irqsave(&musb->lock, flags);
+ ! 	musb_ep_select(musb, musb->mregs, epnum);
+   
+   	/* zero the endpoint sizes */
+   	if (musb_ep->is_in) {
+ ***************
+ *** 1279,1285 ****
+   		req->tx ? "TX/IN" : "RX/OUT",
+   		&req->request, req->request.length, req->epnum);
+   
+ ! 	musb_ep_select(musb->mregs, req->epnum);
+   	if (req->tx)
+   		txstate(musb, req);
+   	else
+ --- 1269,1275 ----
+   		req->tx ? "TX/IN" : "RX/OUT",
+   		&req->request, req->request.length, req->epnum);
+   
+ ! 	musb_ep_select(musb, musb->mregs, req->epnum);
+   	if (req->tx)
+   		txstate(musb, req);
+   	else
+ ***************
+ *** 1373,1379 ****
+   	else if (is_dma_capable() && musb_ep->dma) {
+   		struct dma_controller	*c = musb->dma_controller;
+   
+ ! 		musb_ep_select(musb->mregs, musb_ep->current_epnum);
+   		if (c->channel_abort)
+   			status = c->channel_abort(musb_ep->dma);
+   		else
+ --- 1363,1369 ----
+   	else if (is_dma_capable() && musb_ep->dma) {
+   		struct dma_controller	*c = musb->dma_controller;
+   
+ ! 		musb_ep_select(musb, musb->mregs, musb_ep->current_epnum);
+   		if (c->channel_abort)
+   			status = c->channel_abort(musb_ep->dma);
+   		else
+ ***************
+ *** 1421,1427 ****
+   		goto done;
+   	}
+   
+ ! 	musb_ep_select(mbase, epnum);
+   
+   	request = next_request(musb_ep);
+   	if (value) {
+ --- 1411,1417 ----
+   		goto done;
+   	}
+   
+ ! 	musb_ep_select(musb, mbase, epnum);
+   
+   	request = next_request(musb_ep);
+   	if (value) {
+ ***************
+ *** 1509,1515 ****
+   
+   		spin_lock_irqsave(&musb->lock, flags);
+   
+ ! 		musb_ep_select(mbase, epnum);
+   		/* FIXME return zero unless RXPKTRDY is set */
+   		retval = musb_readw(epio, MUSB_RXCOUNT);
+   
+ --- 1499,1505 ----
+   
+   		spin_lock_irqsave(&musb->lock, flags);
+   
+ ! 		musb_ep_select(musb, mbase, epnum);
+   		/* FIXME return zero unless RXPKTRDY is set */
+   		retval = musb_readw(epio, MUSB_RXCOUNT);
+   
+ ***************
+ *** 1531,1537 ****
+   	mbase = musb->mregs;
+   
+   	spin_lock_irqsave(&musb->lock, flags);
+ ! 	musb_ep_select(mbase, (u8) epnum);
+   
+   	/* disable interrupts */
+   	int_txe = musb_readw(mbase, MUSB_INTRTXE);
+ --- 1521,1527 ----
+   	mbase = musb->mregs;
+   
+   	spin_lock_irqsave(&musb->lock, flags);
+ ! 	musb_ep_select(musb, mbase, (u8) epnum);
+   
+   	/* disable interrupts */
+   	int_txe = musb_readw(mbase, MUSB_INTRTXE);
+ ***************
+ *** 1764,1770 ****
+   }
+   
+   
+ ! static void __init
+   init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
+   {
+   	struct musb_hw_ep	*hw_ep = musb->endpoints + epnum;
+ --- 1754,1760 ----
+   }
+   
+   
+ ! static void __devinit
+   init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
+   {
+   	struct musb_hw_ep	*hw_ep = musb->endpoints + epnum;
+ ***************
+ *** 1801,1807 ****
+    * Initialize the endpoints exposed to peripheral drivers, with backlinks
+    * to the rest of the driver state.
+    */
+ ! static inline void __init musb_g_init_endpoints(struct musb *musb)
+   {
+   	u8			epnum;
+   	struct musb_hw_ep	*hw_ep;
+ --- 1791,1797 ----
+    * Initialize the endpoints exposed to peripheral drivers, with backlinks
+    * to the rest of the driver state.
+    */
+ ! static inline void __devinit musb_g_init_endpoints(struct musb *musb)
+   {
+   	u8			epnum;
+   	struct musb_hw_ep	*hw_ep;
+ ***************
+ *** 1834,1840 ****
+   /* called once during driver setup to initialize and link into
+    * the driver model; memory is zeroed.
+    */
+ ! int __init musb_gadget_setup(struct musb *musb)
+   {
+   	int status;
+   
+ --- 1824,1830 ----
+   /* called once during driver setup to initialize and link into
+    * the driver model; memory is zeroed.
+    */
+ ! int __devinit musb_gadget_setup(struct musb *musb)
+   {
+   	int status;
+   
+ ***************
+ *** 1844,1850 ****
+   	 */
+   
+   	musb->g.ops = &musb_gadget_operations;
+ ! 	musb->g.is_dualspeed = 1;
+   	musb->g.speed = USB_SPEED_UNKNOWN;
+   
+   	/* this "gadget" abstracts/virtualizes the controller */
+ --- 1834,1840 ----
+   	 */
+   
+   	musb->g.ops = &musb_gadget_operations;
+ ! 	musb->g.max_speed = USB_SPEED_HIGH;
+   	musb->g.speed = USB_SPEED_UNKNOWN;
+   
+   	/* this "gadget" abstracts/virtualizes the controller */
+ ***************
+ *** 1903,1909 ****
+   	unsigned long		flags;
+   	int			retval = -EINVAL;
+   
+ ! 	if (driver->speed < USB_SPEED_HIGH)
+   		goto err0;
+   
+   	pm_runtime_get_sync(musb->controller);
+ --- 1893,1899 ----
+   	unsigned long		flags;
+   	int			retval = -EINVAL;
+   
+ ! 	if (driver->max_speed < USB_SPEED_HIGH)
+   		goto err0;
+   
+   	pm_runtime_get_sync(musb->controller);
+ ***************
+ *** 1941,1946 ****
+ --- 1931,1937 ----
+   		 * ensures HdrcStart is indirectly called.
+   		 */
+   		retval = usb_add_hcd(musb_to_hcd(musb), -1, 0);
+ + 		device_set_wakeup_enable(musb->controller, 0);
+   		if (retval < 0) {
+   			dev_dbg(musb->controller, "add_hcd failed, %d\n", retval);
+   			goto err2;
+ ***************
+ *** 1989,1995 ****
+   		for (i = 0, hw_ep = musb->endpoints;
+   				i < musb->nr_endpoints;
+   				i++, hw_ep++) {
+ ! 			musb_ep_select(musb->mregs, i);
+   			if (hw_ep->is_shared_fifo /* || !epnum */) {
+   				nuke(&hw_ep->ep_in, -ESHUTDOWN);
+   			} else {
+ --- 1980,1986 ----
+   		for (i = 0, hw_ep = musb->endpoints;
+   				i < musb->nr_endpoints;
+   				i++, hw_ep++) {
+ ! 			musb_ep_select(musb, musb->mregs, i);
+   			if (hw_ep->is_shared_fifo /* || !epnum */) {
+   				nuke(&hw_ep->ep_in, -ESHUTDOWN);
+   			} else {
+ ***************
+ *** 2024,2030 ****
+   
+   	spin_lock_irqsave(&musb->lock, flags);
+   
+ ! 	musb_hnp_stop(musb);
+   
+   	(void) musb_gadget_vbus_draw(&musb->g, 0);
+   
+ --- 2015,2022 ----
+   
+   	spin_lock_irqsave(&musb->lock, flags);
+   
+ ! 	if (is_otg_enabled(musb))
+ ! 		musb_hnp_stop(musb);
+   
+   	(void) musb_gadget_vbus_draw(&musb->g, 0);
+   
+ ***************
+ *** 2049,2054 ****
+ --- 2041,2047 ----
+   	if (!is_otg_enabled(musb))
+   		musb_stop(musb);
+   
+ + 	musb->gadget_driver = NULL;
+   	pm_runtime_put(musb->controller);
+   
+   	return 0;
+ ***************
+ *** 2138,2154 ****
+   
+   	switch (musb->xceiv->state) {
+   	default:
+ ! 		dev_dbg(musb->controller, "Unhandled disconnect %s, setting a_idle\n",
+ ! 			otg_state_string(musb->xceiv->state));
+ ! 		musb->xceiv->state = OTG_STATE_A_IDLE;
+ ! 		MUSB_HST_MODE(musb);
+ ! 		break;
+   	case OTG_STATE_A_PERIPHERAL:
+ ! 		musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
+ ! 		MUSB_HST_MODE(musb);
+   		break;
+   	case OTG_STATE_B_WAIT_ACON:
+   	case OTG_STATE_B_HOST:
+   	case OTG_STATE_B_PERIPHERAL:
+   	case OTG_STATE_B_IDLE:
+   		musb->xceiv->state = OTG_STATE_B_IDLE;
+ --- 2131,2150 ----
+   
+   	switch (musb->xceiv->state) {
+   	default:
+ ! 		if (is_otg_enabled(musb)) {
+ ! 			dev_dbg(musb->controller, "Unhandled disconnect %s, setting a_idle\n",
+ ! 				otg_state_string(musb->xceiv->state));
+ ! 			musb->xceiv->state = OTG_STATE_A_IDLE;
+ ! 			break;
+ ! 		}
+   	case OTG_STATE_A_PERIPHERAL:
+ ! 		if (is_otg_enabled(musb))
+ ! 			musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
+   		break;
+   	case OTG_STATE_B_WAIT_ACON:
+   	case OTG_STATE_B_HOST:
+ + 		if (!is_otg_enabled(musb))
+ + 			break;
+   	case OTG_STATE_B_PERIPHERAL:
+   	case OTG_STATE_B_IDLE:
+   		musb->xceiv->state = OTG_STATE_B_IDLE;
+ diff -crN linux-3.2.1_o/drivers/usb/musb/musb_gadget_ep0.c linux-3.2.1/drivers/usb/musb/musb_gadget_ep0.c
+ *** linux-3.2.1_o/drivers/usb/musb/musb_gadget_ep0.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/musb/musb_gadget_ep0.c	2014-11-25 13:19:16.660060746 +0900
+ ***************
+ *** 37,43 ****
+   #include <linux/list.h>
+   #include <linux/timer.h>
+   #include <linux/spinlock.h>
+ - #include <linux/init.h>
+   #include <linux/device.h>
+   #include <linux/interrupt.h>
+   
+ --- 37,42 ----
+ ***************
+ *** 88,94 ****
+   	case USB_RECIP_DEVICE:
+   		result[0] = musb->is_self_powered << USB_DEVICE_SELF_POWERED;
+   		result[0] |= musb->may_wakeup << USB_DEVICE_REMOTE_WAKEUP;
+ ! 		if (musb->g.is_otg) {
+   			result[0] |= musb->g.b_hnp_enable
+   				<< USB_DEVICE_B_HNP_ENABLE;
+   			result[0] |= musb->g.a_alt_hnp_support
+ --- 87,93 ----
+   	case USB_RECIP_DEVICE:
+   		result[0] = musb->is_self_powered << USB_DEVICE_SELF_POWERED;
+   		result[0] |= musb->may_wakeup << USB_DEVICE_REMOTE_WAKEUP;
+ ! 		if (is_otg_enabled(musb) && musb->g.is_otg) {
+   			result[0] |= musb->g.b_hnp_enable
+   				<< USB_DEVICE_B_HNP_ENABLE;
+   			result[0] |= musb->g.a_alt_hnp_support
+ ***************
+ *** 128,141 ****
+   			break;
+   		}
+   
+ ! 		musb_ep_select(mbase, epnum);
+   		if (is_in)
+   			tmp = musb_readw(regs, MUSB_TXCSR)
+   						& MUSB_TXCSR_P_SENDSTALL;
+   		else
+   			tmp = musb_readw(regs, MUSB_RXCSR)
+   						& MUSB_RXCSR_P_SENDSTALL;
+ ! 		musb_ep_select(mbase, 0);
+   
+   		result[0] = tmp ? 1 : 0;
+   		} break;
+ --- 127,140 ----
+   			break;
+   		}
+   
+ ! 		musb_ep_select(musb, mbase, epnum);
+   		if (is_in)
+   			tmp = musb_readw(regs, MUSB_TXCSR)
+   						& MUSB_TXCSR_P_SENDSTALL;
+   		else
+   			tmp = musb_readw(regs, MUSB_RXCSR)
+   						& MUSB_RXCSR_P_SENDSTALL;
+ ! 		musb_ep_select(musb, mbase, 0);
+   
+   		result[0] = tmp ? 1 : 0;
+   		} break;
+ ***************
+ *** 152,158 ****
+   
+   		if (len > 2)
+   			len = 2;
+ ! 		musb_write_fifo(&musb->endpoints[0], len, result);
+   	}
+   
+   	return handled;
+ --- 151,157 ----
+   
+   		if (len > 2)
+   			len = 2;
+ ! 		musb->ops->write_fifo(&musb->endpoints[0], len, result);
+   	}
+   
+   	return handled;
+ ***************
+ *** 283,289 ****
+   				if (musb_ep->wedged)
+   					break;
+   
+ ! 				musb_ep_select(mbase, epnum);
+   				if (is_in) {
+   					csr  = musb_readw(regs, MUSB_TXCSR);
+   					csr |= MUSB_TXCSR_CLRDATATOG |
+ --- 282,288 ----
+   				if (musb_ep->wedged)
+   					break;
+   
+ ! 				musb_ep_select(musb, mbase, epnum);
+   				if (is_in) {
+   					csr  = musb_readw(regs, MUSB_TXCSR);
+   					csr |= MUSB_TXCSR_CLRDATATOG |
+ ***************
+ *** 309,315 ****
+   				}
+   
+   				/* select ep0 again */
+ ! 				musb_ep_select(mbase, 0);
+   				} break;
+   			default:
+   				/* class, vendor, etc ... delegate */
+ --- 308,314 ----
+   				}
+   
+   				/* select ep0 again */
+ ! 				musb_ep_select(musb, mbase, 0);
+   				} break;
+   			default:
+   				/* class, vendor, etc ... delegate */
+ ***************
+ *** 391,410 ****
+   						musb->test_mode = true;
+   					break;
+   				case USB_DEVICE_B_HNP_ENABLE:
+ ! 					if (!musb->g.is_otg)
+ ! 						goto stall;
+ ! 					musb->g.b_hnp_enable = 1;
+ ! 					musb_try_b_hnp_enable(musb);
+   					break;
+   				case USB_DEVICE_A_HNP_SUPPORT:
+ ! 					if (!musb->g.is_otg)
+ ! 						goto stall;
+ ! 					musb->g.a_hnp_support = 1;
+   					break;
+   				case USB_DEVICE_A_ALT_HNP_SUPPORT:
+ ! 					if (!musb->g.is_otg)
+ ! 						goto stall;
+ ! 					musb->g.a_alt_hnp_support = 1;
+   					break;
+   				case USB_DEVICE_DEBUG_MODE:
+   					handled = 0;
+ --- 390,415 ----
+   						musb->test_mode = true;
+   					break;
+   				case USB_DEVICE_B_HNP_ENABLE:
+ ! 					if (is_otg_enabled(musb)) {
+ ! 						if (!musb->g.is_otg)
+ ! 							goto stall;
+ ! 						musb->g.b_hnp_enable = 1;
+ ! 						musb_try_b_hnp_enable(musb);
+ ! 					}
+   					break;
+   				case USB_DEVICE_A_HNP_SUPPORT:
+ ! 					if (is_otg_enabled(musb)) {
+ ! 						if (!musb->g.is_otg)
+ ! 							goto stall;
+ ! 						musb->g.a_hnp_support = 1;
+ ! 					}
+   					break;
+   				case USB_DEVICE_A_ALT_HNP_SUPPORT:
+ ! 					if (is_otg_enabled(musb)) {
+ ! 						if (!musb->g.is_otg)
+ ! 							goto stall;
+ ! 						musb->g.a_alt_hnp_support = 1;
+ ! 					}
+   					break;
+   				case USB_DEVICE_DEBUG_MODE:
+   					handled = 0;
+ ***************
+ *** 442,448 ****
+   				if (!musb_ep->desc)
+   					break;
+   
+ ! 				musb_ep_select(mbase, epnum);
+   				if (is_in) {
+   					csr = musb_readw(regs, MUSB_TXCSR);
+   					if (csr & MUSB_TXCSR_FIFONOTEMPTY)
+ --- 447,453 ----
+   				if (!musb_ep->desc)
+   					break;
+   
+ ! 				musb_ep_select(musb, mbase, epnum);
+   				if (is_in) {
+   					csr = musb_readw(regs, MUSB_TXCSR);
+   					if (csr & MUSB_TXCSR_FIFONOTEMPTY)
+ ***************
+ *** 461,467 ****
+   				}
+   
+   				/* select ep0 again */
+ ! 				musb_ep_select(mbase, 0);
+   				handled = 1;
+   				} break;
+   
+ --- 466,472 ----
+   				}
+   
+   				/* select ep0 again */
+ ! 				musb_ep_select(musb, mbase, 0);
+   				handled = 1;
+   				} break;
+   
+ ***************
+ *** 506,513 ****
+   			req->status = -EOVERFLOW;
+   			count = len;
+   		}
+ ! 		musb_read_fifo(&musb->endpoints[0], count, buf);
+ ! 		req->actual += count;
+   		csr = MUSB_CSR0_P_SVDRXPKTRDY;
+   		if (count < 64 || req->actual == req->length) {
+   			musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
+ --- 511,520 ----
+   			req->status = -EOVERFLOW;
+   			count = len;
+   		}
+ ! 		if (count > 0) {
+ ! 			musb->ops->read_fifo(&musb->endpoints[0], count, buf);
+ ! 			req->actual += count;
+ ! 		}
+   		csr = MUSB_CSR0_P_SVDRXPKTRDY;
+   		if (count < 64 || req->actual == req->length) {
+   			musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
+ ***************
+ *** 528,534 ****
+   			return;
+   		musb->ackpend = 0;
+   	}
+ ! 	musb_ep_select(musb->mregs, 0);
+   	musb_writew(regs, MUSB_CSR0, csr);
+   }
+   
+ --- 535,541 ----
+   			return;
+   		musb->ackpend = 0;
+   	}
+ ! 	musb_ep_select(musb, musb->mregs, 0);
+   	musb_writew(regs, MUSB_CSR0, csr);
+   }
+   
+ ***************
+ *** 559,565 ****
+   	fifo_src = (u8 *) request->buf + request->actual;
+   	fifo_count = min((unsigned) MUSB_EP0_FIFOSIZE,
+   		request->length - request->actual);
+ ! 	musb_write_fifo(&musb->endpoints[0], fifo_count, fifo_src);
+   	request->actual += fifo_count;
+   
+   	/* update the flags */
+ --- 566,572 ----
+   	fifo_src = (u8 *) request->buf + request->actual;
+   	fifo_count = min((unsigned) MUSB_EP0_FIFOSIZE,
+   		request->length - request->actual);
+ ! 	musb->ops->write_fifo(&musb->endpoints[0], fifo_count, fifo_src);
+   	request->actual += fifo_count;
+   
+   	/* update the flags */
+ ***************
+ *** 585,591 ****
+   	}
+   
+   	/* send it out, triggering a "txpktrdy cleared" irq */
+ ! 	musb_ep_select(musb->mregs, 0);
+   	musb_writew(regs, MUSB_CSR0, csr);
+   }
+   
+ --- 592,598 ----
+   	}
+   
+   	/* send it out, triggering a "txpktrdy cleared" irq */
+ ! 	musb_ep_select(musb, musb->mregs, 0);
+   	musb_writew(regs, MUSB_CSR0, csr);
+   }
+   
+ ***************
+ *** 601,607 ****
+   	struct musb_request	*r;
+   	void __iomem		*regs = musb->control_ep->regs;
+   
+ ! 	musb_read_fifo(&musb->endpoints[0], sizeof *req, (u8 *)req);
+   
+   	/* NOTE:  earlier 2.6 versions changed setup packets to host
+   	 * order, but now USB packets always stay in USB byte order.
+ --- 608,614 ----
+   	struct musb_request	*r;
+   	void __iomem		*regs = musb->control_ep->regs;
+   
+ ! 	musb->ops->read_fifo(&musb->endpoints[0], sizeof *req, (u8 *)req);
+   
+   	/* NOTE:  earlier 2.6 versions changed setup packets to host
+   	 * order, but now USB packets always stay in USB byte order.
+ ***************
+ *** 670,676 ****
+   	void __iomem	*regs = musb->endpoints[0].regs;
+   	irqreturn_t	retval = IRQ_NONE;
+   
+ ! 	musb_ep_select(mbase, 0);	/* select ep0 */
+   	csr = musb_readw(regs, MUSB_CSR0);
+   	len = musb_readb(regs, MUSB_COUNT0);
+   
+ --- 677,683 ----
+   	void __iomem	*regs = musb->endpoints[0].regs;
+   	irqreturn_t	retval = IRQ_NONE;
+   
+ ! 	musb_ep_select(musb, mbase, 0);	/* select ep0 */
+   	csr = musb_readw(regs, MUSB_CSR0);
+   	len = musb_readb(regs, MUSB_COUNT0);
+   
+ ***************
+ *** 760,765 ****
+ --- 767,775 ----
+   
+   			musb_writeb(mbase, MUSB_TESTMODE,
+   					musb->test_mode_nr);
+ + 			if (MUSB_TEST_PACKET == musb->test_mode_nr)
+ + 				musb_writew(musb->endpoints[0].regs,
+ + 					MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
+   		}
+   		/* FALLTHROUGH */
+   
+ ***************
+ *** 880,886 ****
+   
+   			handled = forward_to_driver(musb, &setup);
+   			if (handled < 0) {
+ ! 				musb_ep_select(mbase, 0);
+   stall:
+   				dev_dbg(musb->controller, "stall (%d)\n", handled);
+   				musb->ackpend |= MUSB_CSR0_P_SENDSTALL;
+ --- 890,896 ----
+   
+   			handled = forward_to_driver(musb, &setup);
+   			if (handled < 0) {
+ ! 				musb_ep_select(musb, mbase, 0);
+   stall:
+   				dev_dbg(musb->controller, "stall (%d)\n", handled);
+   				musb->ackpend |= MUSB_CSR0_P_SENDSTALL;
+ ***************
+ *** 975,981 ****
+   			ep->name, ep->is_in ? "IN/TX" : "OUT/RX",
+   			req->request.length);
+   
+ ! 	musb_ep_select(musb->mregs, 0);
+   
+   	/* sequence #1, IN ... start writing the data */
+   	if (musb->ep0_state == MUSB_EP0_STAGE_TX)
+ --- 985,991 ----
+   			ep->name, ep->is_in ? "IN/TX" : "OUT/RX",
+   			req->request.length);
+   
+ ! 	musb_ep_select(musb, musb->mregs, 0);
+   
+   	/* sequence #1, IN ... start writing the data */
+   	if (musb->ep0_state == MUSB_EP0_STAGE_TX)
+ ***************
+ *** 1038,1044 ****
+   		goto cleanup;
+   	}
+   
+ ! 	musb_ep_select(base, 0);
+   	csr = musb->ackpend;
+   
+   	switch (musb->ep0_state) {
+ --- 1048,1054 ----
+   		goto cleanup;
+   	}
+   
+ ! 	musb_ep_select(musb, base, 0);
+   	csr = musb->ackpend;
+   
+   	switch (musb->ep0_state) {
+ diff -crN linux-3.2.1_o/drivers/usb/musb/musb_host.c linux-3.2.1/drivers/usb/musb/musb_host.c
+ *** linux-3.2.1_o/drivers/usb/musb/musb_host.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/musb/musb_host.c	2014-11-25 13:19:16.668047009 +0900
+ ***************
+ *** 101,106 ****
+ --- 101,130 ----
+   			struct urb *urb, int is_out,
+   			u8 *buf, u32 offset, u32 len);
+   
+ + void push_queue(struct musb *musb, struct urb *urb)
+ + {
+ + 	spin_lock(&musb->gb_lock);
+ + 	list_add_tail(&urb->giveback_list, &musb->gb_list);
+ + 	spin_unlock(&musb->gb_lock);
+ + }
+ + 
+ + struct urb *pop_queue(struct musb *musb)
+ + {
+ + 	struct urb *urb;
+ + 	unsigned long flags;
+ + 
+ + 	spin_lock_irqsave(&musb->gb_lock, flags);
+ + 	if (list_empty(&musb->gb_list)) {
+ + 		spin_unlock_irqrestore(&musb->gb_lock, flags);
+ + 		return NULL;
+ + 	}
+ + 	urb = list_entry(musb->gb_list.next, struct urb, giveback_list);
+ + 	list_del(&urb->giveback_list);
+ + 	spin_unlock_irqrestore(&musb->gb_lock, flags);
+ + 
+ + 	return urb;
+ + }
+ + 
+   /*
+    * Clear TX fifo. Needed to avoid BABBLE errors.
+    */
+ ***************
+ *** 109,130 ****
+   	struct musb	*musb = ep->musb;
+   	void __iomem	*epio = ep->regs;
+   	u16		csr;
+ - 	u16		lastcsr = 0;
+   	int		retries = 1000;
+   
+   	csr = musb_readw(epio, MUSB_TXCSR);
+ ! 	while (csr & MUSB_TXCSR_FIFONOTEMPTY) {
+ ! 		if (csr != lastcsr)
+ ! 			dev_dbg(musb->controller, "Host TX FIFONOTEMPTY csr: %02x\n", csr);
+ ! 		lastcsr = csr;
+   		csr |= MUSB_TXCSR_FLUSHFIFO;
+   		musb_writew(epio, MUSB_TXCSR, csr);
+   		csr = musb_readw(epio, MUSB_TXCSR);
+ ! 		if (WARN(retries-- < 1,
+   				"Could not flush host TX%d fifo: csr: %04x\n",
+ ! 				ep->epnum, csr))
+   			return;
+ ! 		mdelay(1);
+   	}
+   }
+   
+ --- 133,158 ----
+   	struct musb	*musb = ep->musb;
+   	void __iomem	*epio = ep->regs;
+   	u16		csr;
+   	int		retries = 1000;
+   
+   	csr = musb_readw(epio, MUSB_TXCSR);
+ ! 	while (csr & MUSB_TXCSR_TXPKTRDY) {
+ ! 		if (!(csr & MUSB_TXCSR_FIFONOTEMPTY))
+ ! 			return;
+ ! 		else
+ ! 			dev_dbg(musb->controller,
+ ! 				"Host TX FIFONOTEMPTY csr: %02x\n", csr);
+ ! 
+   		csr |= MUSB_TXCSR_FLUSHFIFO;
+   		musb_writew(epio, MUSB_TXCSR, csr);
+   		csr = musb_readw(epio, MUSB_TXCSR);
+ ! 
+ ! 		if (retries-- < 1) {
+ ! 			dev_dbg(musb->controller,
+   				"Could not flush host TX%d fifo: csr: %04x\n",
+ ! 					ep->epnum, csr);
+   			return;
+ ! 		}
+   	}
+   }
+   
+ ***************
+ *** 178,184 ****
+   	/* NOTE: no locks here; caller should lock and select EP */
+   	txcsr = musb_readw(ep->regs, MUSB_TXCSR);
+   	txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS;
+ ! 	if (is_cppi_enabled())
+   		txcsr |= MUSB_TXCSR_DMAMODE;
+   	musb_writew(ep->regs, MUSB_TXCSR, txcsr);
+   }
+ --- 206,212 ----
+   	/* NOTE: no locks here; caller should lock and select EP */
+   	txcsr = musb_readw(ep->regs, MUSB_TXCSR);
+   	txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS;
+ ! 	if (is_cppi_enabled(ep->musb) || is_cppi41_enabled(ep->musb))
+   		txcsr |= MUSB_TXCSR_DMAMODE;
+   	musb_writew(ep->regs, MUSB_TXCSR, txcsr);
+   }
+ ***************
+ *** 219,224 ****
+ --- 247,253 ----
+   	/* initialize software qh state */
+   	qh->offset = 0;
+   	qh->segsize = 0;
+ + 	hw_ep->xfer_type = qh->type;
+   
+   	/* gather right source of data */
+   	switch (qh->type) {
+ ***************
+ *** 292,306 ****
+   
+   		if (!hw_ep->tx_channel)
+   			musb_h_tx_start(hw_ep);
+ ! 		else if (is_cppi_enabled() || tusb_dma_omap())
+   			musb_h_tx_dma_start(hw_ep);
+   	}
+   }
+   
+   /* Context: caller owns controller lock, IRQs are blocked */
+   static void musb_giveback(struct musb *musb, struct urb *urb, int status)
+ - __releases(musb->lock)
+ - __acquires(musb->lock)
+   {
+   	dev_dbg(musb->controller,
+   			"complete %p %pF (%d), dev%d ep%d%s, %d/%d\n",
+ --- 321,334 ----
+   
+   		if (!hw_ep->tx_channel)
+   			musb_h_tx_start(hw_ep);
+ ! 		else if (is_cppi_enabled(musb) || is_cppi41_enabled(musb)
+ ! 				|| tusb_dma_omap(musb))
+   			musb_h_tx_dma_start(hw_ep);
+   	}
+   }
+   
+   /* Context: caller owns controller lock, IRQs are blocked */
+   static void musb_giveback(struct musb *musb, struct urb *urb, int status)
+   {
+   	dev_dbg(musb->controller,
+   			"complete %p %pF (%d), dev%d ep%d%s, %d/%d\n",
+ ***************
+ *** 311,341 ****
+   			urb->actual_length, urb->transfer_buffer_length
+   			);
+   
+ - 	usb_hcd_unlink_urb_from_ep(musb_to_hcd(musb), urb);
+ - 	spin_unlock(&musb->lock);
+   	usb_hcd_giveback_urb(musb_to_hcd(musb), urb, status);
+ - 	spin_lock(&musb->lock);
+   }
+   
+   /* For bulk/interrupt endpoints only */
+   static inline void musb_save_toggle(struct musb_qh *qh, int is_in,
+   				    struct urb *urb)
+   {
+   	void __iomem		*epio = qh->hw_ep->regs;
+   	u16			csr;
+   
+   	/*
+   	 * FIXME: the current Mentor DMA code seems to have
+   	 * problems getting toggle correct.
+   	 */
+   
+ ! 	if (is_in)
+   		csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE;
+ ! 	else
+   		csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE;
+   
+   	usb_settoggle(urb->dev, qh->epnum, !is_in, csr ? 1 : 0);
+   }
+   
+   /*
+    * Advance this hardware endpoint's queue, completing the specified URB and
+ --- 339,396 ----
+   			urb->actual_length, urb->transfer_buffer_length
+   			);
+   
+   	usb_hcd_giveback_urb(musb_to_hcd(musb), urb, status);
+   }
+   
+   /* For bulk/interrupt endpoints only */
+   static inline void musb_save_toggle(struct musb_qh *qh, int is_in,
+   				    struct urb *urb)
+   {
+ + 	struct musb		*musb = qh->hw_ep->musb;
+   	void __iomem		*epio = qh->hw_ep->regs;
+   	u16			csr;
+ + 	u8			curr_toggle;
+   
+   	/*
+   	 * FIXME: the current Mentor DMA code seems to have
+   	 * problems getting toggle correct.
+   	 */
+   
+ ! 	if (is_in) {
+   		csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE;
+ ! 		if (musb->datatog_fix) {
+ ! 			curr_toggle = csr ? 1 : 0;
+ ! 
+ ! 			/* check if data toggle has gone out of sync */
+ ! 			if (is_dma_capable() && qh->hw_ep->rx_channel &&
+ ! 				curr_toggle == qh->hw_ep->prev_toggle) {
+ ! 				dev_dbg(musb->controller,
+ ! 				"Data toggle same as previous (=%d) on ep%d\n",
+ ! 					curr_toggle, qh->hw_ep->epnum);
+ ! 
+ ! 				csr = musb_readw(epio, MUSB_RXCSR);
+ ! 				csr |= MUSB_RXCSR_H_DATATOGGLE |
+ ! 					MUSB_RXCSR_H_WR_DATATOGGLE;
+ ! 				musb_writew(epio, MUSB_RXCSR, csr);
+ ! 
+ ! 				csr = 1;
+ ! 			}
+ ! 		}
+ ! 	} else {
+   		csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE;
+ + 	}
+   
+   	usb_settoggle(urb->dev, qh->epnum, !is_in, csr ? 1 : 0);
+   }
+ + /* Used to complete urb giveback */
+ + void musb_gb_work(struct work_struct *data)
+ + {
+ + 	struct musb *musb = container_of(data, struct musb, gb_work);
+ + 	struct urb *urb;
+ + 
+ + 	while ((urb = pop_queue(musb)) != 0)
+ + 		musb_giveback(musb, urb, 0);
+ + }
+   
+   /*
+    * Advance this hardware endpoint's queue, completing the specified URB and
+ ***************
+ *** 366,385 ****
+   		break;
+   	}
+   
+ ! 	qh->is_ready = 0;
+ ! 	musb_giveback(musb, urb, status);
+ ! 	qh->is_ready = ready;
+   
+   	/* reclaim resources (and bandwidth) ASAP; deschedule it, and
+   	 * invalidate qh as soon as list_empty(&hep->urb_list)
+   	 */
+   	if (list_empty(&qh->hep->urb_list)) {
+   		struct list_head	*head;
+   
+ ! 		if (is_in)
+   			ep->rx_reinit = 1;
+ ! 		else
+   			ep->tx_reinit = 1;
+   
+   		/* Clobber old pointers to this qh */
+   		musb_ep_set_qh(ep, is_in, NULL);
+ --- 421,456 ----
+   		break;
+   	}
+   
+ ! 	usb_hcd_unlink_urb_from_ep(musb_to_hcd(musb), urb);
+   
+ + 	/* If URB completed with error then giveback first */
+ + 	if (status != 0) {
+ + 		qh->is_ready = 0;
+ + 		spin_unlock(&musb->lock);
+ + 		musb_giveback(musb, urb, status);
+ + 		spin_lock(&musb->lock);
+ + 		qh->is_ready = ready;
+ + 	}
+   	/* reclaim resources (and bandwidth) ASAP; deschedule it, and
+   	 * invalidate qh as soon as list_empty(&hep->urb_list)
+   	 */
+   	if (list_empty(&qh->hep->urb_list)) {
+   		struct list_head	*head;
+ + 		struct dma_controller	*dma = musb->dma_controller;
+   
+ ! 		if (is_in) {
+   			ep->rx_reinit = 1;
+ ! 			if (ep->rx_channel) {
+ ! 				dma->channel_release(ep->rx_channel);
+ ! 				ep->rx_channel = NULL;
+ ! 			}
+ ! 		} else {
+   			ep->tx_reinit = 1;
+ + 			if (ep->tx_channel) {
+ + 				dma->channel_release(ep->tx_channel);
+ + 				ep->tx_channel = NULL;
+ + 			}
+ + 		}
+   
+   		/* Clobber old pointers to this qh */
+   		musb_ep_set_qh(ep, is_in, NULL);
+ ***************
+ *** 412,422 ****
+   		}
+   	}
+   
+ ! 	if (qh != NULL && qh->is_ready) {
+   		dev_dbg(musb->controller, "... next ep%d %cX urb %p\n",
+   		    hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh));
+   		musb_start_urb(musb, is_in, qh);
+   	}
+   }
+   
+   static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr)
+ --- 483,506 ----
+   		}
+   	}
+   
+ ! 	/* we should not start next urb when current urb
+ ! 	 * has failed, this is because stack will unlink/dequeue
+ ! 	 * remaining urbs. Programming the next urb will endup in
+ ! 	 * urb completion because of expected error (cause of current
+ ! 	 * urb failure) interrupts and interfere with urb dequeue
+ ! 	 * initiated by stack and cause a crash.
+ ! 	 */
+ ! 	if (status == 0 && qh != NULL && qh->is_ready) {
+   		dev_dbg(musb->controller, "... next ep%d %cX urb %p\n",
+   		    hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh));
+   		musb_start_urb(musb, is_in, qh);
+   	}
+ + 
+ + 	/* if URB is successfully completed then giveback in workqueue */
+ + 	if (status == 0) {
+ + 		push_queue(musb, urb);
+ + 		queue_work(musb->gb_queue, &musb->gb_work);
+ + 	}
+   }
+   
+   static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr)
+ ***************
+ *** 425,431 ****
+   	 * ignore dma (various models),
+   	 * leave toggle alone (may not have been saved yet)
+   	 */
+ ! 	csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY;
+   	csr &= ~(MUSB_RXCSR_H_REQPKT
+   		| MUSB_RXCSR_H_AUTOREQ
+   		| MUSB_RXCSR_AUTOCLEAR);
+ --- 509,516 ----
+   	 * ignore dma (various models),
+   	 * leave toggle alone (may not have been saved yet)
+   	 */
+ ! 	if (csr & MUSB_RXCSR_RXPKTRDY)
+ ! 		csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY;
+   	csr &= ~(MUSB_RXCSR_H_REQPKT
+   		| MUSB_RXCSR_H_AUTOREQ
+   		| MUSB_RXCSR_AUTOCLEAR);
+ ***************
+ *** 456,462 ****
+   	int			pipe = urb->pipe;
+   	void			*buffer = urb->transfer_buffer;
+   
+ ! 	/* musb_ep_select(mbase, epnum); */
+   	rx_count = musb_readw(epio, MUSB_RXCOUNT);
+   	dev_dbg(musb->controller, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count,
+   			urb->transfer_buffer, qh->offset,
+ --- 541,547 ----
+   	int			pipe = urb->pipe;
+   	void			*buffer = urb->transfer_buffer;
+   
+ ! 	/* musb_ep_select(musb, mbase, epnum); */
+   	rx_count = musb_readw(epio, MUSB_RXCOUNT);
+   	dev_dbg(musb->controller, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count,
+   			urb->transfer_buffer, qh->offset,
+ ***************
+ *** 517,523 ****
+   			urb->status = -EREMOTEIO;
+   	}
+   
+ ! 	musb_read_fifo(hw_ep, length, buf);
+   
+   	csr = musb_readw(epio, MUSB_RXCSR);
+   	csr |= MUSB_RXCSR_H_WZC_BITS;
+ --- 602,608 ----
+   			urb->status = -EREMOTEIO;
+   	}
+   
+ ! 	musb->ops->read_fifo(hw_ep, length, buf);
+   
+   	csr = musb_readw(epio, MUSB_RXCSR);
+   	csr |= MUSB_RXCSR_H_WZC_BITS;
+ ***************
+ *** 615,650 ****
+   	u16			csr;
+   	u8			mode;
+   
+ ! #ifdef	CONFIG_USB_INVENTRA_DMA
+ ! 	if (length > channel->max_len)
+ ! 		length = channel->max_len;
+   
+ ! 	csr = musb_readw(epio, MUSB_TXCSR);
+ ! 	if (length > pkt_size) {
+ ! 		mode = 1;
+ ! 		csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB;
+ ! 		/* autoset shouldn't be set in high bandwidth */
+ ! 		if (qh->hb_mult == 1)
+ ! 			csr |= MUSB_TXCSR_AUTOSET;
+   	} else {
+ ! 		mode = 0;
+ ! 		csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE);
+ ! 		csr |= MUSB_TXCSR_DMAENAB; /* against programmer's guide */
+ ! 	}
+ ! 	channel->desired_mode = mode;
+ ! 	musb_writew(epio, MUSB_TXCSR, csr);
+ ! #else
+ ! 	if (!is_cppi_enabled() && !tusb_dma_omap())
+ ! 		return false;
+   
+ ! 	channel->actual_len = 0;
+   
+ ! 	/*
+ ! 	 * TX uses "RNDIS" mode automatically but needs help
+ ! 	 * to identify the zero-length-final-packet case.
+ ! 	 */
+ ! 	mode = (urb->transfer_flags & URB_ZERO_PACKET) ? 1 : 0;
+ ! #endif
+   
+   	qh->segsize = length;
+   
+ --- 700,737 ----
+   	u16			csr;
+   	u8			mode;
+   
+ ! 	if (is_inventra_dma(hw_ep->musb)) {
+ ! 		if (length > channel->max_len)
+ ! 			length = channel->max_len;
+   
+ ! 		csr = musb_readw(epio, MUSB_TXCSR);
+ ! 		if (length > pkt_size) {
+ ! 			mode = 1;
+ ! 			csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB;
+ ! 			/* autoset shouldn't be set in high bandwidth */
+ ! 			if (qh->hb_mult == 1)
+ ! 				csr |= MUSB_TXCSR_AUTOSET;
+ ! 		} else {
+ ! 			mode = 0;
+ ! 			csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE);
+ ! 			csr |= MUSB_TXCSR_DMAENAB; /* against progrmr's guide */
+ ! 		}
+ ! 		channel->desired_mode = mode;
+ ! 		musb_writew(epio, MUSB_TXCSR, csr);
+   	} else {
+ ! 		if (!is_cppi_enabled(hw_ep->musb)
+ ! 			&& !is_cppi41_enabled(hw_ep->musb)
+ ! 			&& !tusb_dma_omap(hw_ep->musb))
+ ! 			return false;
+   
+ ! 		channel->actual_len = 0;
+   
+ ! 		/*
+ ! 		 * TX uses "RNDIS" mode automatically but needs help
+ ! 		 * to identify the zero-length-final-packet case.
+ ! 		 */
+ ! 		mode = (urb->transfer_flags & URB_ZERO_PACKET) ? 1 : 0;
+ ! 	}
+   
+   	qh->segsize = length;
+   
+ ***************
+ *** 654,660 ****
+   	 */
+   	wmb();
+   
+ ! 	if (!dma->channel_program(channel, pkt_size, mode,
+   			urb->transfer_dma + offset, length)) {
+   		dma->channel_release(channel);
+   		hw_ep->tx_channel = NULL;
+ --- 741,748 ----
+   	 */
+   	wmb();
+   
+ ! 	if (!dma->channel_program(channel, pkt_size |
+ ! 			(qh->hb_mult << 11), mode,
+   			urb->transfer_dma + offset, length)) {
+   		dma->channel_release(channel);
+   		hw_ep->tx_channel = NULL;
+ ***************
+ *** 683,688 ****
+ --- 771,778 ----
+   	void __iomem		*epio = hw_ep->regs;
+   	struct musb_qh		*qh = musb_ep_get_qh(hw_ep, !is_out);
+   	u16			packet_sz = qh->maxpacket;
+ + 	u8			use_dma = 1;
+ + 	u16			csr;
+   
+   	dev_dbg(musb->controller, "%s hw%d urb %p spd%d dev%d ep%d%s "
+   				"h_addr%02x h_port%02x bytes %d\n",
+ ***************
+ *** 692,702 ****
+   			qh->h_addr_reg, qh->h_port_reg,
+   			len);
+   
+ ! 	musb_ep_select(mbase, epnum);
+   
+   	/* candidate for DMA? */
+   	dma_controller = musb->dma_controller;
+ ! 	if (is_dma_capable() && epnum && dma_controller) {
+   		dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel;
+   		if (!dma_channel) {
+   			dma_channel = dma_controller->channel_alloc(
+ --- 782,800 ----
+   			qh->h_addr_reg, qh->h_port_reg,
+   			len);
+   
+ ! 	musb_ep_select(musb, mbase, epnum);
+ ! 
+ ! 	if (is_out && !len) {
+ ! 		use_dma = 0;
+ ! 		csr = musb_readw(epio, MUSB_TXCSR);
+ ! 		csr &= ~MUSB_TXCSR_DMAENAB;
+ ! 		musb_writew(epio, MUSB_TXCSR, csr);
+ ! 		hw_ep->tx_channel = NULL;
+ ! 	}
+   
+   	/* candidate for DMA? */
+   	dma_controller = musb->dma_controller;
+ ! 	if (use_dma && is_dma_capable() && epnum && dma_controller) {
+   		dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel;
+   		if (!dma_channel) {
+   			dma_channel = dma_controller->channel_alloc(
+ ***************
+ *** 779,787 ****
+   					| ((hw_ep->max_packet_sz_tx /
+   						packet_sz) - 1) << 11);
+   			else
+ ! 				musb_writew(epio, MUSB_TXMAXP,
+ ! 						qh->maxpacket |
+ ! 						((qh->hb_mult - 1) << 11));
+   			musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg);
+   		} else {
+   			musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg);
+ --- 877,884 ----
+   					| ((hw_ep->max_packet_sz_tx /
+   						packet_sz) - 1) << 11);
+   			else
+ ! 				musb_writew(epio, MUSB_TXMAXP, qh->maxpacket |
+ ! 						(qh->hb_mult << 11));
+   			musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg);
+   		} else {
+   			musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg);
+ ***************
+ *** 803,809 ****
+   		if (load_count) {
+   			/* PIO to load FIFO */
+   			qh->segsize = load_count;
+ ! 			musb_write_fifo(hw_ep, load_count, buf);
+   		}
+   
+   		/* re-enable interrupt */
+ --- 900,906 ----
+   		if (load_count) {
+   			/* PIO to load FIFO */
+   			qh->segsize = load_count;
+ ! 			musb->ops->write_fifo(hw_ep, load_count, buf);
+   		}
+   
+   		/* re-enable interrupt */
+ ***************
+ *** 828,836 ****
+   		} else {
+   			csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
+   
+ ! 			if (csr & (MUSB_RXCSR_RXPKTRDY
+ ! 					| MUSB_RXCSR_DMAENAB
+ ! 					| MUSB_RXCSR_H_REQPKT))
+   				ERR("broken !rx_reinit, ep%d csr %04x\n",
+   						hw_ep->epnum, csr);
+   
+ --- 925,933 ----
+   		} else {
+   			csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
+   
+ ! 			if (csr & (MUSB_RXCSR_RXPKTRDY | (is_cppi_enabled(musb)
+ ! 			|| is_cppi41_enabled(musb)) ? 0 : MUSB_RXCSR_DMAENAB
+ ! 			| MUSB_RXCSR_H_REQPKT))
+   				ERR("broken !rx_reinit, ep%d csr %04x\n",
+   						hw_ep->epnum, csr);
+   
+ ***************
+ *** 840,846 ****
+   
+   		/* kick things off */
+   
+ ! 		if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) {
+   			/* Candidate for DMA */
+   			dma_channel->actual_len = 0L;
+   			qh->segsize = len;
+ --- 937,944 ----
+   
+   		/* kick things off */
+   
+ ! 		if ((is_cppi_enabled(musb) || is_cppi41_enabled(musb) ||
+ ! 			tusb_dma_omap(musb)) && dma_channel) {
+   			/* Candidate for DMA */
+   			dma_channel->actual_len = 0L;
+   			qh->segsize = len;
+ ***************
+ *** 849,860 ****
+   			musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
+   			csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
+   
+   			/*
+   			 * Unless caller treats short RX transfers as
+   			 * errors, we dare not queue multiple transfers.
+   			 */
+   			dma_ok = dma_controller->channel_program(dma_channel,
+ ! 					packet_sz, !(urb->transfer_flags &
+   						     URB_SHORT_NOT_OK),
+   					urb->transfer_dma + offset,
+   					qh->segsize);
+ --- 947,969 ----
+   			musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
+   			csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
+   
+ + 			if (musb->datatog_fix) {
+ + 				/*
+ + 				 * Save the data toggle value which can be
+ + 				 * compared later to see if data toggle goes
+ + 				 * out of sync
+ + 				 */
+ + 				hw_ep->prev_toggle = (csr &
+ + 					MUSB_RXCSR_H_DATATOGGLE) ? 1 : 0;
+ + 			}
+ + 
+   			/*
+   			 * Unless caller treats short RX transfers as
+   			 * errors, we dare not queue multiple transfers.
+   			 */
+   			dma_ok = dma_controller->channel_program(dma_channel,
+ ! 					packet_sz | (qh->hb_mult << 11),
+ ! 					 !(urb->transfer_flags &
+   						     URB_SHORT_NOT_OK),
+   					urb->transfer_dma + offset,
+   					qh->segsize);
+ ***************
+ *** 872,877 ****
+ --- 981,1053 ----
+   	}
+   }
+   
+ + /* Schedule next QH from musb->in_bulk/out_bulk and move the current qh to
+ +  * the end; avoids starvation for other endpoints.
+ +  */
+ + static void musb_bulk_nak_timeout(struct musb *musb, struct musb_hw_ep *ep,
+ + 	int is_in)
+ + {
+ + 	struct dma_channel	*dma;
+ + 	struct urb		*urb;
+ + 	void __iomem		*mbase = musb->mregs;
+ + 	void __iomem		*epio = ep->regs;
+ + 	struct musb_qh		*cur_qh, *next_qh;
+ + 	u16			rx_csr, tx_csr;
+ + 
+ + 	musb_ep_select(musb, mbase, ep->epnum);
+ + 	if (is_in) {
+ + 		dma = is_dma_capable() ? ep->rx_channel : NULL;
+ + 
+ + 		/* clear nak timeout bit */
+ + 		rx_csr = musb_readw(epio, MUSB_RXCSR);
+ + 		rx_csr |= MUSB_RXCSR_H_WZC_BITS;
+ + 		rx_csr &= ~MUSB_RXCSR_DATAERROR;
+ + 		musb_writew(epio, MUSB_RXCSR, rx_csr);
+ + 
+ + 		cur_qh = first_qh(&musb->in_bulk);
+ + 	} else {
+ + 		dma = is_dma_capable() ? ep->tx_channel : NULL;
+ + 
+ + 		/* clear nak timeout bit */
+ + 		tx_csr = musb_readw(epio, MUSB_TXCSR);
+ + 		tx_csr |= MUSB_TXCSR_H_WZC_BITS;
+ + 		tx_csr &= ~MUSB_TXCSR_H_NAKTIMEOUT;
+ + 		musb_writew(epio, MUSB_TXCSR, tx_csr);
+ + 
+ + 		cur_qh = first_qh(&musb->out_bulk);
+ + 	}
+ + 	if (cur_qh) {
+ + 		urb = next_urb(cur_qh);
+ + 		if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
+ + 			dma->status = MUSB_DMA_STATUS_CORE_ABORT;
+ + 			musb->dma_controller->channel_abort(dma);
+ + 			urb->actual_length += dma->actual_len;
+ + 			dma->actual_len = 0L;
+ + 		}
+ + 		musb_save_toggle(cur_qh, is_in, urb);
+ + 
+ + 		if (is_in) {
+ + 			/* move cur_qh to end of queue */
+ + 			list_move_tail(&cur_qh->ring, &musb->in_bulk);
+ + 
+ + 			/* get the next qh from musb->in_bulk */
+ + 			next_qh = first_qh(&musb->in_bulk);
+ + 
+ + 			/* set rx_reinit and schedule the next qh */
+ + 			ep->rx_reinit = 1;
+ + 		} else {
+ + 			/* move cur_qh to end of queue */
+ + 			list_move_tail(&cur_qh->ring, &musb->out_bulk);
+ + 
+ + 			/* get the next qh from musb->out_bulk */
+ + 			next_qh = first_qh(&musb->out_bulk);
+ + 
+ + 			/* set tx_reinit and schedule the next qh */
+ + 			ep->tx_reinit = 1;
+ + 		}
+ + 		musb_start_urb(musb, is_in, next_qh);
+ + 	}
+ + }
+   
+   /*
+    * Service the default endpoint (ep0) as host.
+ ***************
+ *** 894,900 ****
+   		if (fifo_count < len)
+   			urb->status = -EOVERFLOW;
+   
+ ! 		musb_read_fifo(hw_ep, fifo_count, fifo_dest);
+   
+   		urb->actual_length += fifo_count;
+   		if (len < qh->maxpacket) {
+ --- 1070,1076 ----
+   		if (fifo_count < len)
+   			urb->status = -EOVERFLOW;
+   
+ ! 		musb->ops->read_fifo(hw_ep, fifo_count, fifo_dest);
+   
+   		urb->actual_length += fifo_count;
+   		if (len < qh->maxpacket) {
+ ***************
+ *** 933,939 ****
+   					fifo_count,
+   					(fifo_count == 1) ? "" : "s",
+   					fifo_dest);
+ ! 			musb_write_fifo(hw_ep, fifo_count, fifo_dest);
+   
+   			urb->actual_length += fifo_count;
+   			more = true;
+ --- 1109,1115 ----
+   					fifo_count,
+   					(fifo_count == 1) ? "" : "s",
+   					fifo_dest);
+ ! 			musb->ops->write_fifo(hw_ep, fifo_count, fifo_dest);
+   
+   			urb->actual_length += fifo_count;
+   			more = true;
+ ***************
+ *** 968,974 ****
+   	/* ep0 only has one queue, "in" */
+   	urb = next_urb(qh);
+   
+ ! 	musb_ep_select(mbase, 0);
+   	csr = musb_readw(epio, MUSB_CSR0);
+   	len = (csr & MUSB_CSR0_RXPKTRDY)
+   			? musb_readb(epio, MUSB_COUNT0)
+ --- 1144,1150 ----
+   	/* ep0 only has one queue, "in" */
+   	urb = next_urb(qh);
+   
+ ! 	musb_ep_select(musb, mbase, 0);
+   	csr = musb_readw(epio, MUSB_CSR0);
+   	len = (csr & MUSB_CSR0_RXPKTRDY)
+   			? musb_readb(epio, MUSB_COUNT0)
+ ***************
+ *** 1054,1059 ****
+ --- 1230,1237 ----
+   			else
+   				csr = MUSB_CSR0_H_STATUSPKT
+   					| MUSB_CSR0_TXPKTRDY;
+ + 			/* disable ping token in status phase */
+ + 				csr |= MUSB_CSR0_H_DIS_PING;
+   
+   			/* flag status stage */
+   			musb->ep0_stage = MUSB_EP0_STATUS;
+ ***************
+ *** 1074,1081 ****
+   }
+   
+   
+ - #ifdef CONFIG_USB_INVENTRA_DMA
+ - 
+   /* Host side TX (OUT) using Mentor DMA works as follows:
+   	submit_urb ->
+   		- if queue was empty, Program Endpoint
+ --- 1252,1257 ----
+ ***************
+ *** 1088,1095 ****
+   			short packets in mode 1.
+   */
+   
+ - #endif
+ - 
+   /* Service a Tx-Available or dma completion irq for the endpoint */
+   void musb_host_tx(struct musb *musb, u8 epnum)
+   {
+ --- 1264,1269 ----
+ ***************
+ *** 1107,1113 ****
+   	struct dma_channel	*dma;
+   	bool			transfer_pending = false;
+   
+ ! 	musb_ep_select(mbase, epnum);
+   	tx_csr = musb_readw(epio, MUSB_TXCSR);
+   
+   	/* with CPPI, DMA sometimes triggers "extra" irqs */
+ --- 1281,1287 ----
+   	struct dma_channel	*dma;
+   	bool			transfer_pending = false;
+   
+ ! 	musb_ep_select(musb, mbase, epnum);
+   	tx_csr = musb_readw(epio, MUSB_TXCSR);
+   
+   	/* with CPPI, DMA sometimes triggers "extra" irqs */
+ ***************
+ *** 1136,1155 ****
+   		status = -ETIMEDOUT;
+   
+   	} else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) {
+ ! 		dev_dbg(musb->controller, "TX end=%d device not responding\n", epnum);
+   
+ ! 		/* NOTE:  this code path would be a good place to PAUSE a
+ ! 		 * transfer, if there's some other (nonperiodic) tx urb
+ ! 		 * that could use this fifo.  (dma complicates it...)
+ ! 		 * That's already done for bulk RX transfers.
+ ! 		 *
+ ! 		 * if (bulk && qh->ring.next != &musb->out_bulk), then
+ ! 		 * we have a candidate... NAKing is *NOT* an error
+ ! 		 */
+ ! 		musb_ep_select(mbase, epnum);
+ ! 		musb_writew(epio, MUSB_TXCSR,
+ ! 				MUSB_TXCSR_H_WZC_BITS
+ ! 				| MUSB_TXCSR_TXPKTRDY);
+   		return;
+   	}
+   
+ --- 1310,1336 ----
+   		status = -ETIMEDOUT;
+   
+   	} else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) {
+ ! 		if (USB_ENDPOINT_XFER_BULK == qh->type && qh->mux == 1
+ ! 				&& !list_is_singular(&musb->out_bulk)) {
+   
+ ! 			dev_dbg(musb->controller, "TX end %d NAK timeout\n", epnum);
+ ! 			musb_bulk_nak_timeout(musb, hw_ep, 0);
+ ! 		} else {
+ ! 			dev_dbg(musb->controller, "TX end=%d device not responding\n", epnum);
+ ! 
+ ! 			/* NOTE: this code path would be a good place to PAUSE a
+ ! 			 * transfer, if there's some other (nonperiodic) tx urb
+ ! 			 * that could use this fifo.  (dma complicates it...)
+ ! 			 * That's already done for bulk RX transfers.
+ ! 			 *
+ ! 			 * if (bulk && qh->ring.next != &musb->out_bulk), then
+ ! 			 * we have a candidate... NAKing is *NOT* an error
+ ! 			 */
+ ! 			musb_ep_select(musb, mbase, epnum);
+ ! 			musb_writew(epio, MUSB_TXCSR,
+ ! 					MUSB_TXCSR_H_WZC_BITS
+ ! 					| MUSB_TXCSR_TXPKTRDY);
+ ! 		}
+   		return;
+   	}
+   
+ ***************
+ *** 1170,1176 ****
+   				| MUSB_TXCSR_H_NAKTIMEOUT
+   				);
+   
+ ! 		musb_ep_select(mbase, epnum);
+   		musb_writew(epio, MUSB_TXCSR, tx_csr);
+   		/* REVISIT may need to clear FLUSHFIFO ... */
+   		musb_writew(epio, MUSB_TXCSR, tx_csr);
+ --- 1351,1357 ----
+   				| MUSB_TXCSR_H_NAKTIMEOUT
+   				);
+   
+ ! 		musb_ep_select(musb, mbase, epnum);
+   		musb_writew(epio, MUSB_TXCSR, tx_csr);
+   		/* REVISIT may need to clear FLUSHFIFO ... */
+   		musb_writew(epio, MUSB_TXCSR, tx_csr);
+ ***************
+ *** 1302,1308 ****
+   	} else if ((usb_pipeisoc(pipe) || transfer_pending) && dma) {
+   		if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb,
+   				offset, length)) {
+ ! 			if (is_cppi_enabled() || tusb_dma_omap())
+   				musb_h_tx_dma_start(hw_ep);
+   			return;
+   		}
+ --- 1483,1490 ----
+   	} else if ((usb_pipeisoc(pipe) || transfer_pending) && dma) {
+   		if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb,
+   				offset, length)) {
+ ! 			if (is_cppi_enabled(musb) || is_cppi41_enabled(musb) ||
+ ! 					tusb_dma_omap(musb))
+   				musb_h_tx_dma_start(hw_ep);
+   			return;
+   		}
+ ***************
+ *** 1322,1338 ****
+   		length = qh->maxpacket;
+   	/* Unmap the buffer so that CPU can use it */
+   	usb_hcd_unmap_urb_for_dma(musb_to_hcd(musb), urb);
+ ! 	musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset);
+   	qh->segsize = length;
+   
+ ! 	musb_ep_select(mbase, epnum);
+   	musb_writew(epio, MUSB_TXCSR,
+   			MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY);
+   }
+   
+   
+ - #ifdef CONFIG_USB_INVENTRA_DMA
+ - 
+   /* Host side RX (IN) using Mentor DMA works as follows:
+   	submit_urb ->
+   		- if queue was empty, ProgramEndpoint
+ --- 1504,1518 ----
+   		length = qh->maxpacket;
+   	/* Unmap the buffer so that CPU can use it */
+   	usb_hcd_unmap_urb_for_dma(musb_to_hcd(musb), urb);
+ ! 	musb->ops->write_fifo(hw_ep, length, urb->transfer_buffer + offset);
+   	qh->segsize = length;
+   
+ ! 	musb_ep_select(musb, mbase, epnum);
+   	musb_writew(epio, MUSB_TXCSR,
+   			MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY);
+   }
+   
+   
+   /* Host side RX (IN) using Mentor DMA works as follows:
+   	submit_urb ->
+   		- if queue was empty, ProgramEndpoint
+ ***************
+ *** 1368,1419 ****
+    *	last packet of one URB's transfer.
+    */
+   
+ - #endif
+ - 
+ - /* Schedule next QH from musb->in_bulk and move the current qh to
+ -  * the end; avoids starvation for other endpoints.
+ -  */
+ - static void musb_bulk_rx_nak_timeout(struct musb *musb, struct musb_hw_ep *ep)
+ - {
+ - 	struct dma_channel	*dma;
+ - 	struct urb		*urb;
+ - 	void __iomem		*mbase = musb->mregs;
+ - 	void __iomem		*epio = ep->regs;
+ - 	struct musb_qh		*cur_qh, *next_qh;
+ - 	u16			rx_csr;
+ - 
+ - 	musb_ep_select(mbase, ep->epnum);
+ - 	dma = is_dma_capable() ? ep->rx_channel : NULL;
+ - 
+ - 	/* clear nak timeout bit */
+ - 	rx_csr = musb_readw(epio, MUSB_RXCSR);
+ - 	rx_csr |= MUSB_RXCSR_H_WZC_BITS;
+ - 	rx_csr &= ~MUSB_RXCSR_DATAERROR;
+ - 	musb_writew(epio, MUSB_RXCSR, rx_csr);
+ - 
+ - 	cur_qh = first_qh(&musb->in_bulk);
+ - 	if (cur_qh) {
+ - 		urb = next_urb(cur_qh);
+ - 		if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
+ - 			dma->status = MUSB_DMA_STATUS_CORE_ABORT;
+ - 			musb->dma_controller->channel_abort(dma);
+ - 			urb->actual_length += dma->actual_len;
+ - 			dma->actual_len = 0L;
+ - 		}
+ - 		musb_save_toggle(cur_qh, 1, urb);
+ - 
+ - 		/* move cur_qh to end of queue */
+ - 		list_move_tail(&cur_qh->ring, &musb->in_bulk);
+ - 
+ - 		/* get the next qh from musb->in_bulk */
+ - 		next_qh = first_qh(&musb->in_bulk);
+ - 
+ - 		/* set rx_reinit and schedule the next qh */
+ - 		ep->rx_reinit = 1;
+ - 		musb_start_urb(musb, 1, next_qh);
+ - 	}
+ - }
+ - 
+   /*
+    * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso,
+    * and high-bandwidth IN transfer cases.
+ --- 1548,1553 ----
+ ***************
+ *** 1433,1439 ****
+   	u32			status;
+   	struct dma_channel	*dma;
+   
+ ! 	musb_ep_select(mbase, epnum);
+   
+   	urb = next_urb(qh);
+   	dma = is_dma_capable() ? hw_ep->rx_channel : NULL;
+ --- 1567,1573 ----
+   	u32			status;
+   	struct dma_channel	*dma;
+   
+ ! 	musb_ep_select(musb, mbase, epnum);
+   
+   	urb = next_urb(qh);
+   	dma = is_dma_capable() ? hw_ep->rx_channel : NULL;
+ ***************
+ *** 1490,1499 ****
+   			if (usb_pipebulk(urb->pipe)
+   					&& qh->mux == 1
+   					&& !list_is_singular(&musb->in_bulk)) {
+ ! 				musb_bulk_rx_nak_timeout(musb, hw_ep);
+   				return;
+   			}
+ ! 			musb_ep_select(mbase, epnum);
+   			rx_csr |= MUSB_RXCSR_H_WZC_BITS;
+   			rx_csr &= ~MUSB_RXCSR_DATAERROR;
+   			musb_writew(epio, MUSB_RXCSR, rx_csr);
+ --- 1624,1633 ----
+   			if (usb_pipebulk(urb->pipe)
+   					&& qh->mux == 1
+   					&& !list_is_singular(&musb->in_bulk)) {
+ ! 				musb_bulk_nak_timeout(musb, hw_ep, 1);
+   				return;
+   			}
+ ! 			musb_ep_select(musb, mbase, epnum);
+   			rx_csr |= MUSB_RXCSR_H_WZC_BITS;
+   			rx_csr &= ~MUSB_RXCSR_DATAERROR;
+   			musb_writew(epio, MUSB_RXCSR, rx_csr);
+ ***************
+ *** 1537,1544 ****
+   
+   	/* FIXME this is _way_ too much in-line logic for Mentor DMA */
+   
+ ! #ifndef CONFIG_USB_INVENTRA_DMA
+ ! 	if (rx_csr & MUSB_RXCSR_H_REQPKT)  {
+   		/* REVISIT this happened for a while on some short reads...
+   		 * the cleanup still needs investigation... looks bad...
+   		 * and also duplicates dma cleanup code above ... plus,
+ --- 1671,1677 ----
+   
+   	/* FIXME this is _way_ too much in-line logic for Mentor DMA */
+   
+ ! 	if (!is_inventra_dma(musb) && (rx_csr & MUSB_RXCSR_H_REQPKT))  {
+   		/* REVISIT this happened for a while on some short reads...
+   		 * the cleanup still needs investigation... looks bad...
+   		 * and also duplicates dma cleanup code above ... plus,
+ ***************
+ *** 1555,1565 ****
+   				xfer_len, dma ? ", dma" : "");
+   		rx_csr &= ~MUSB_RXCSR_H_REQPKT;
+   
+ ! 		musb_ep_select(mbase, epnum);
+   		musb_writew(epio, MUSB_RXCSR,
+   				MUSB_RXCSR_H_WZC_BITS | rx_csr);
+   	}
+ - #endif
+   	if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) {
+   		xfer_len = dma->actual_len;
+   
+ --- 1688,1697 ----
+   				xfer_len, dma ? ", dma" : "");
+   		rx_csr &= ~MUSB_RXCSR_H_REQPKT;
+   
+ ! 		musb_ep_select(musb, mbase, epnum);
+   		musb_writew(epio, MUSB_RXCSR,
+   				MUSB_RXCSR_H_WZC_BITS | rx_csr);
+   	}
+   	if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) {
+   		xfer_len = dma->actual_len;
+   
+ ***************
+ *** 1567,1575 ****
+   			| MUSB_RXCSR_H_AUTOREQ
+   			| MUSB_RXCSR_AUTOCLEAR
+   			| MUSB_RXCSR_RXPKTRDY);
+   		musb_writew(hw_ep->regs, MUSB_RXCSR, val);
+   
+ - #ifdef CONFIG_USB_INVENTRA_DMA
+   		if (usb_pipeisoc(pipe)) {
+   			struct usb_iso_packet_descriptor *d;
+   
+ --- 1699,1710 ----
+   			| MUSB_RXCSR_H_AUTOREQ
+   			| MUSB_RXCSR_AUTOCLEAR
+   			| MUSB_RXCSR_RXPKTRDY);
+ + 
+ + 		if (is_cppi_enabled(musb) || is_cppi41_enabled(musb))
+ + 			val |= MUSB_RXCSR_DMAENAB;
+ + 
+   		musb_writew(hw_ep->regs, MUSB_RXCSR, val);
+   
+   		if (usb_pipeisoc(pipe)) {
+   			struct usb_iso_packet_descriptor *d;
+   
+ ***************
+ *** 1584,1597 ****
+   
+   			if (++qh->iso_idx >= urb->number_of_packets)
+   				done = true;
+ ! 			else
+   				done = false;
+ ! 
+   		} else  {
+ ! 		/* done if urb buffer is full or short packet is recd */
+ ! 		done = (urb->actual_length + xfer_len >=
+ ! 				urb->transfer_buffer_length
+ ! 			|| dma->actual_len < qh->maxpacket);
+   		}
+   
+   		/* send IN token for next packet, without AUTOREQ */
+ --- 1719,1751 ----
+   
+   			if (++qh->iso_idx >= urb->number_of_packets)
+   				done = true;
+ ! 			else if (is_cppi_enabled(musb) ||
+ ! 					is_cppi41_enabled(musb)) {
+ ! 				struct dma_controller   *c;
+ ! 				void *buf;
+ ! 				u32 length, ret;
+ ! 
+ ! 				c = musb->dma_controller;
+ ! 				buf = (void *)
+ ! 					urb->iso_frame_desc[qh->iso_idx].offset
+ ! 					+ (u32)urb->transfer_dma;
+ ! 
+ ! 				length =
+ ! 					urb->iso_frame_desc[qh->iso_idx].length;
+ ! 
+ ! 				ret = c->channel_program(dma, qh->maxpacket |
+ ! 						(qh->hb_mult << 11),
+ ! 						0, (u32) buf, length);
+   				done = false;
+ ! 			} else {
+ ! 				done = false;
+ ! 			}
+   		} else  {
+ ! 			/* done if urb buffer is full or short packet is recd */
+ ! 			done = (urb->actual_length + xfer_len >=
+ ! 					urb->transfer_buffer_length
+ ! 				|| dma->actual_len < qh->maxpacket
+ ! 				|| dma->actual_len % qh->maxpacket);
+   		}
+   
+   		/* send IN token for next packet, without AUTOREQ */
+ ***************
+ *** 1601,1613 ****
+   				MUSB_RXCSR_H_WZC_BITS | val);
+   		}
+   
+ ! 		dev_dbg(musb->controller, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum,
+   			done ? "off" : "reset",
+   			musb_readw(epio, MUSB_RXCSR),
+   			musb_readw(epio, MUSB_RXCOUNT));
+ - #else
+ - 		done = true;
+ - #endif
+   	} else if (urb->status == -EINPROGRESS) {
+   		/* if no errors, be sure a packet is ready for unloading */
+   		if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) {
+ --- 1755,1765 ----
+   				MUSB_RXCSR_H_WZC_BITS | val);
+   		}
+   
+ ! 		dev_dbg(musb->controller,
+ ! 			"ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum,
+   			done ? "off" : "reset",
+   			musb_readw(epio, MUSB_RXCSR),
+   			musb_readw(epio, MUSB_RXCOUNT));
+   	} else if (urb->status == -EINPROGRESS) {
+   		/* if no errors, be sure a packet is ready for unloading */
+   		if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) {
+ ***************
+ *** 1618,1631 ****
+   
+   /* SCRUB (RX) */
+   			/* do the proper sequence to abort the transfer */
+ ! 			musb_ep_select(mbase, epnum);
+   			val &= ~MUSB_RXCSR_H_REQPKT;
+   			musb_writew(epio, MUSB_RXCSR, val);
+   			goto finish;
+   		}
+   
+   		/* we are expecting IN packets */
+ - #ifdef CONFIG_USB_INVENTRA_DMA
+   		if (dma) {
+   			struct dma_controller	*c;
+   			u16			rx_count;
+ --- 1770,1782 ----
+   
+   /* SCRUB (RX) */
+   			/* do the proper sequence to abort the transfer */
+ ! 			musb_ep_select(musb, mbase, epnum);
+   			val &= ~MUSB_RXCSR_H_REQPKT;
+   			musb_writew(epio, MUSB_RXCSR, val);
+   			goto finish;
+   		}
+   
+   		/* we are expecting IN packets */
+   		if (dma) {
+   			struct dma_controller	*c;
+   			u16			rx_count;
+ ***************
+ *** 1729,1735 ****
+   			 * adjusted first...
+   			 */
+   			ret = c->channel_program(
+ ! 				dma, qh->maxpacket,
+   				dma->desired_mode, buf, length);
+   
+   			if (!ret) {
+ --- 1880,1886 ----
+   			 * adjusted first...
+   			 */
+   			ret = c->channel_program(
+ ! 				dma, qh->maxpacket | ((qh->hb_mult - 1) << 11),
+   				dma->desired_mode, buf, length);
+   
+   			if (!ret) {
+ ***************
+ *** 1739,1745 ****
+   				/* REVISIT reset CSR */
+   			}
+   		}
+ - #endif	/* Mentor DMA */
+   
+   		if (!dma) {
+   			/* Unmap the buffer so that CPU can use it */
+ --- 1890,1895 ----
+ ***************
+ *** 1754,1761 ****
+   	urb->actual_length += xfer_len;
+   	qh->offset += xfer_len;
+   	if (done) {
+ ! 		if (urb->status == -EINPROGRESS)
+ ! 			urb->status = status;
+   		musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN);
+   	}
+   }
+ --- 1904,1922 ----
+   	urb->actual_length += xfer_len;
+   	qh->offset += xfer_len;
+   	if (done) {
+ ! 		if (urb->status == -EINPROGRESS) {
+ ! 			/* If short packet is not expected any transfer length
+ ! 			 * less than actual length is an error, hence
+ ! 			 * set urb status to -EREMOTEIO
+ ! 			 */
+ ! 			if ((urb->status == -EINPROGRESS)
+ ! 				&& (urb->transfer_flags & URB_SHORT_NOT_OK)
+ ! 				&& (urb->actual_length
+ ! 					< urb->transfer_buffer_length))
+ ! 				urb->status = -EREMOTEIO;
+ ! 			else
+ ! 				urb->status = status;
+ ! 		}
+   		musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN);
+   	}
+   }
+ ***************
+ *** 1849,1862 ****
+   		else
+   			head = &musb->out_bulk;
+   
+ ! 		/* Enable bulk RX NAK timeout scheme when bulk requests are
+   		 * multiplexed.  This scheme doen't work in high speed to full
+   		 * speed scenario as NAK interrupts are not coming from a
+   		 * full speed device connected to a high speed device.
+   		 * NAK timeout interval is 8 (128 uframe or 16ms) for HS and
+   		 * 4 (8 frame or 8ms) for FS device.
+   		 */
+ ! 		if (is_in && qh->dev)
+   			qh->intv_reg =
+   				(USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4;
+   		goto success;
+ --- 2010,2023 ----
+   		else
+   			head = &musb->out_bulk;
+   
+ ! 		/* Enable bulk RX/TX NAK timeout scheme when bulk requests are
+   		 * multiplexed.  This scheme doen't work in high speed to full
+   		 * speed scenario as NAK interrupts are not coming from a
+   		 * full speed device connected to a high speed device.
+   		 * NAK timeout interval is 8 (128 uframe or 16ms) for HS and
+   		 * 4 (8 frame or 8ms) for FS device.
+   		 */
+ ! 		if (qh->dev)
+   			qh->intv_reg =
+   				(USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4;
+   		goto success;
+ ***************
+ *** 1904,1909 ****
+ --- 2065,2072 ----
+   	qh = ret ? NULL : hep->hcpriv;
+   	if (qh)
+   		urb->hcpriv = qh;
+ + 
+ + 	INIT_LIST_HEAD(&urb->giveback_list);
+   	spin_unlock_irqrestore(&musb->lock, flags);
+   
+   	/* DMA mapping was already done, if needed, and this urb is on
+ ***************
+ *** 2081,2087 ****
+   	int			status = 0;
+   	u16			csr;
+   
+ ! 	musb_ep_select(regs, hw_end);
+   
+   	if (is_dma_capable()) {
+   		struct dma_channel	*dma;
+ --- 2244,2250 ----
+   	int			status = 0;
+   	u16			csr;
+   
+ ! 	musb_ep_select(ep->musb, regs, hw_end);
+   
+   	if (is_dma_capable()) {
+   		struct dma_channel	*dma;
+ ***************
+ *** 2098,2104 ****
+   	}
+   
+   	/* turn off DMA requests, discard state, stop polling ... */
+ ! 	if (is_in) {
+   		/* giveback saves bulk toggle */
+   		csr = musb_h_flush_rxfifo(ep, 0);
+   
+ --- 2261,2267 ----
+   	}
+   
+   	/* turn off DMA requests, discard state, stop polling ... */
+ ! 	if (is_in && ep->epnum) {
+   		/* giveback saves bulk toggle */
+   		csr = musb_h_flush_rxfifo(ep, 0);
+   
+ ***************
+ *** 2167,2174 ****
+ --- 2330,2341 ----
+   			|| musb_ep_get_qh(qh->hw_ep, is_in) != qh) {
+   		int	ready = qh->is_ready;
+   
+ + 		usb_hcd_unlink_urb_from_ep(musb_to_hcd(musb), urb);
+ + 
+   		qh->is_ready = 0;
+ + 		spin_unlock(&musb->lock);
+   		musb_giveback(musb, urb, 0);
+ + 		spin_lock(&musb->lock);
+   		qh->is_ready = ready;
+   
+   		/* If nothing else (usually musb_giveback) is using it
+ ***************
+ *** 2229,2236 ****
+   		 * other transfers, and since !qh->is_ready nothing
+   		 * will activate any of these as it advances.
+   		 */
+ ! 		while (!list_empty(&hep->urb_list))
+ ! 			musb_giveback(musb, next_urb(qh), -ESHUTDOWN);
+   
+   		hep->hcpriv = NULL;
+   		list_del(&qh->ring);
+ --- 2396,2408 ----
+   		 * other transfers, and since !qh->is_ready nothing
+   		 * will activate any of these as it advances.
+   		 */
+ ! 		while (!list_empty(&hep->urb_list)) {
+ ! 			urb = next_urb(qh);
+ ! 			usb_hcd_unlink_urb_from_ep(musb_to_hcd(musb), urb);
+ ! 			spin_unlock(&musb->lock);
+ ! 			musb_giveback(musb, urb, -ESHUTDOWN);
+ ! 			spin_lock(&musb->lock);
+ ! 		}
+   
+   		hep->hcpriv = NULL;
+   		list_del(&qh->ring);
+ ***************
+ *** 2290,2296 ****
+   	}
+   
+   	if (musb->is_active) {
+ ! 		WARNING("trying to suspend as %s while active\n",
+   				otg_state_string(musb->xceiv->state));
+   		return -EBUSY;
+   	} else
+ --- 2462,2468 ----
+   	}
+   
+   	if (musb->is_active) {
+ ! 		dev_dbg(musb->controller, "trying to suspend as %s while active\n",
+   				otg_state_string(musb->xceiv->state));
+   		return -EBUSY;
+   	} else
+ ***************
+ *** 2299,2305 ****
+   
+   static int musb_bus_resume(struct usb_hcd *hcd)
+   {
+ - 	/* resuming child port does the work */
+   	return 0;
+   }
+   
+ --- 2471,2476 ----
+ diff -crN linux-3.2.1_o/drivers/usb/musb/musbhsdma.c linux-3.2.1/drivers/usb/musb/musbhsdma.c
+ *** linux-3.2.1_o/drivers/usb/musb/musbhsdma.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/musb/musbhsdma.c	2014-11-25 13:19:16.668047009 +0900
+ ***************
+ *** 30,35 ****
+ --- 30,36 ----
+    * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+    *
+    */
+ + #include <linux/module.h>
+   #include <linux/device.h>
+   #include <linux/interrupt.h>
+   #include <linux/platform_device.h>
+ ***************
+ *** 205,218 ****
+   {
+   	struct musb_dma_channel *musb_channel = channel->private_data;
+   	void __iomem *mbase = musb_channel->controller->base;
+ ! 
+   	u8 bchannel = musb_channel->idx;
+   	int offset;
+   	u16 csr;
+   
+   	if (channel->status == MUSB_DMA_STATUS_BUSY) {
+   		if (musb_channel->transmit) {
+ ! 			offset = MUSB_EP_OFFSET(musb_channel->epnum,
+   						MUSB_TXCSR);
+   
+   			/*
+ --- 206,219 ----
+   {
+   	struct musb_dma_channel *musb_channel = channel->private_data;
+   	void __iomem *mbase = musb_channel->controller->base;
+ ! 	struct musb *musb = musb_channel->controller->private_data;
+   	u8 bchannel = musb_channel->idx;
+   	int offset;
+   	u16 csr;
+   
+   	if (channel->status == MUSB_DMA_STATUS_BUSY) {
+   		if (musb_channel->transmit) {
+ ! 			offset = MUSB_EP_OFFSET(musb, musb_channel->epnum,
+   						MUSB_TXCSR);
+   
+   			/*
+ ***************
+ *** 225,231 ****
+   			csr &= ~MUSB_TXCSR_DMAMODE;
+   			musb_writew(mbase, offset, csr);
+   		} else {
+ ! 			offset = MUSB_EP_OFFSET(musb_channel->epnum,
+   						MUSB_RXCSR);
+   
+   			csr = musb_readw(mbase, offset);
+ --- 226,232 ----
+   			csr &= ~MUSB_TXCSR_DMAMODE;
+   			musb_writew(mbase, offset, csr);
+   		} else {
+ ! 			offset = MUSB_EP_OFFSET(musb, musb_channel->epnum,
+   						MUSB_RXCSR);
+   
+   			csr = musb_readw(mbase, offset);
+ ***************
+ *** 336,342 ****
+   					    (musb_channel->max_packet_sz - 1)))
+   				    ) {
+   					u8  epnum  = musb_channel->epnum;
+ ! 					int offset = MUSB_EP_OFFSET(epnum,
+   								    MUSB_TXCSR);
+   					u16 txcsr;
+   
+ --- 337,343 ----
+   					    (musb_channel->max_packet_sz - 1)))
+   				    ) {
+   					u8  epnum  = musb_channel->epnum;
+ ! 					int offset = MUSB_EP_OFFSET(musb, epnum,
+   								    MUSB_TXCSR);
+   					u16 txcsr;
+   
+ ***************
+ *** 344,350 ****
+   					 * The programming guide says that we
+   					 * must clear DMAENAB before DMAMODE.
+   					 */
+ ! 					musb_ep_select(mbase, epnum);
+   					txcsr = musb_readw(mbase, offset);
+   					txcsr &= ~(MUSB_TXCSR_DMAENAB
+   							| MUSB_TXCSR_AUTOSET);
+ --- 345,351 ----
+   					 * The programming guide says that we
+   					 * must clear DMAENAB before DMAMODE.
+   					 */
+ ! 					musb_ep_select(musb, mbase, epnum);
+   					txcsr = musb_readw(mbase, offset);
+   					txcsr &= ~(MUSB_TXCSR_DMAENAB
+   							| MUSB_TXCSR_AUTOSET);
+ ***************
+ *** 366,372 ****
+   	return retval;
+   }
+   
+ ! void dma_controller_destroy(struct dma_controller *c)
+   {
+   	struct musb_dma_controller *controller = container_of(c,
+   			struct musb_dma_controller, controller);
+ --- 367,373 ----
+   	return retval;
+   }
+   
+ ! void inventra_dma_controller_destroy(struct dma_controller *c)
+   {
+   	struct musb_dma_controller *controller = container_of(c,
+   			struct musb_dma_controller, controller);
+ ***************
+ *** 379,387 ****
+   
+   	kfree(controller);
+   }
+   
+ ! struct dma_controller *__init
+ ! dma_controller_create(struct musb *musb, void __iomem *base)
+   {
+   	struct musb_dma_controller *controller;
+   	struct device *dev = musb->controller;
+ --- 380,389 ----
+   
+   	kfree(controller);
+   }
+ + EXPORT_SYMBOL(inventra_dma_controller_destroy);
+   
+ ! struct dma_controller *__devinit
+ ! inventra_dma_controller_create(struct musb *musb, void __iomem *base)
+   {
+   	struct musb_dma_controller *controller;
+   	struct device *dev = musb->controller;
+ ***************
+ *** 411,417 ****
+   	if (request_irq(irq, dma_controller_irq, 0,
+   			dev_name(musb->controller), &controller->controller)) {
+   		dev_err(dev, "request_irq %d failed!\n", irq);
+ ! 		dma_controller_destroy(&controller->controller);
+   
+   		return NULL;
+   	}
+ --- 413,419 ----
+   	if (request_irq(irq, dma_controller_irq, 0,
+   			dev_name(musb->controller), &controller->controller)) {
+   		dev_err(dev, "request_irq %d failed!\n", irq);
+ ! 		inventra_dma_controller_destroy(&controller->controller);
+   
+   		return NULL;
+   	}
+ ***************
+ *** 420,422 ****
+ --- 422,439 ----
+   
+   	return &controller->controller;
+   }
+ + EXPORT_SYMBOL(inventra_dma_controller_create);
+ + 
+ + MODULE_DESCRIPTION("MUSB Inventra dma controller driver");
+ + MODULE_LICENSE("GPL v2");
+ + 
+ + static int __init inventra_dma_init(void)
+ + {
+ + 	return 0;
+ + }
+ + module_init(inventra_dma_init);
+ + 
+ + static void __exit inventra_dma__exit(void)
+ + {
+ + }
+ + module_exit(inventra_dma__exit);
+ diff -crN linux-3.2.1_o/drivers/usb/musb/musb_io.h linux-3.2.1/drivers/usb/musb/musb_io.h
+ *** linux-3.2.1_o/drivers/usb/musb/musb_io.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/musb/musb_io.h	2014-11-25 13:19:16.672097212 +0900
+ ***************
+ *** 61,135 ****
+   /* NOTE:  these offsets are all in bytes */
+   
+   static inline u16 musb_readw(const void __iomem *addr, unsigned offset)
+ ! 	{ return __raw_readw(addr + offset); }
+   
+   static inline u32 musb_readl(const void __iomem *addr, unsigned offset)
+ ! 	{ return __raw_readl(addr + offset); }
+   
+   
+   static inline void musb_writew(void __iomem *addr, unsigned offset, u16 data)
+ ! 	{ __raw_writew(data, addr + offset); }
+   
+   static inline void musb_writel(void __iomem *addr, unsigned offset, u32 data)
+ ! 	{ __raw_writel(data, addr + offset); }
+ ! 
+ ! 
+ ! #ifdef CONFIG_USB_MUSB_TUSB6010
+ ! 
+ ! /*
+ !  * TUSB6010 doesn't allow 8-bit access; 16-bit access is the minimum.
+ !  */
+ ! static inline u8 musb_readb(const void __iomem *addr, unsigned offset)
+ ! {
+ ! 	u16 tmp;
+ ! 	u8 val;
+ ! 
+ ! 	tmp = __raw_readw(addr + (offset & ~1));
+ ! 	if (offset & 1)
+ ! 		val = (tmp >> 8);
+ ! 	else
+ ! 		val = tmp & 0xff;
+ ! 
+ ! 	return val;
+ ! }
+ ! 
+ ! static inline void musb_writeb(void __iomem *addr, unsigned offset, u8 data)
+ ! {
+ ! 	u16 tmp;
+ ! 
+ ! 	tmp = __raw_readw(addr + (offset & ~1));
+ ! 	if (offset & 1)
+ ! 		tmp = (data << 8) | (tmp & 0xff);
+ ! 	else
+ ! 		tmp = (tmp & 0xff00) | data;
+ ! 
+ ! 	__raw_writew(tmp, addr + (offset & ~1));
+ ! }
+ ! 
+ ! #else
+ ! 
+ ! static inline u8 musb_readb(const void __iomem *addr, unsigned offset)
+ ! 	{ return __raw_readb(addr + offset); }
+ ! 
+ ! static inline void musb_writeb(void __iomem *addr, unsigned offset, u8 data)
+ ! 	{ __raw_writeb(data, addr + offset); }
+ ! 
+ ! #endif	/* CONFIG_USB_MUSB_TUSB6010 */
+   
+   #else
+   
+ - static inline u8 musb_readb(const void __iomem *addr, unsigned offset)
+ - 	{ return (u8) (bfin_read16(addr + offset)); }
+ - 
+   static inline u16 musb_readw(const void __iomem *addr, unsigned offset)
+   	{ return bfin_read16(addr + offset); }
+   
+   static inline u32 musb_readl(const void __iomem *addr, unsigned offset)
+   	{ return (u32) (bfin_read16(addr + offset)); }
+   
+ - static inline void musb_writeb(void __iomem *addr, unsigned offset, u8 data)
+ - 	{ bfin_write16(addr + offset, (u16) data); }
+ - 
+   static inline void musb_writew(void __iomem *addr, unsigned offset, u16 data)
+   	{ bfin_write16(addr + offset, data); }
+   
+ --- 61,86 ----
+   /* NOTE:  these offsets are all in bytes */
+   
+   static inline u16 musb_readw(const void __iomem *addr, unsigned offset)
+ ! 	{ return readw(addr + offset); }
+   
+   static inline u32 musb_readl(const void __iomem *addr, unsigned offset)
+ ! 	{ return readl(addr + offset); }
+   
+   
+   static inline void musb_writew(void __iomem *addr, unsigned offset, u16 data)
+ ! 	{ writew(data, addr + offset); }
+   
+   static inline void musb_writel(void __iomem *addr, unsigned offset, u32 data)
+ ! 	{ writel(data, addr + offset); }
+   
+   #else
+   
+   static inline u16 musb_readw(const void __iomem *addr, unsigned offset)
+   	{ return bfin_read16(addr + offset); }
+   
+   static inline u32 musb_readl(const void __iomem *addr, unsigned offset)
+   	{ return (u32) (bfin_read16(addr + offset)); }
+   
+   static inline void musb_writew(void __iomem *addr, unsigned offset, u16 data)
+   	{ bfin_write16(addr + offset, data); }
+   
+ diff -crN linux-3.2.1_o/drivers/usb/musb/musb_procfs.c linux-3.2.1/drivers/usb/musb/musb_procfs.c
+ *** linux-3.2.1_o/drivers/usb/musb/musb_procfs.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/drivers/usb/musb/musb_procfs.c	2014-11-25 13:19:16.680078754 +0900
+ ***************
+ *** 0 ****
+ --- 1,809 ----
+ + /*
+ +  * MUSB OTG driver debug support
+ +  *
+ +  * Copyright 2005 Mentor Graphics Corporation
+ +  * Copyright (C) 2005-2006 by Texas Instruments
+ +  * Copyright (C) 2006-2007 Nokia Corporation
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License
+ +  * version 2 as published by the Free Software Foundation.
+ +  *
+ +  * This program is distributed in the hope that it will be useful, but
+ +  * WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ +  * General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ +  * 02110-1301 USA
+ +  *
+ +  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ +  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ +  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ +  * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ +  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ +  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ +  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ +  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ +  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ +  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ +  *
+ +  */
+ + 
+ + #include <linux/kernel.h>
+ + #include <linux/proc_fs.h>
+ + #include <linux/seq_file.h>
+ + #include <linux/uaccess.h>	/* FIXME remove procfs writes */
+ + #include <mach/hardware.h>
+ + 
+ + #include "musb_core.h"
+ + 
+ + #include "davinci.h"
+ + 
+ + static int dump_qh(struct musb_qh *qh, char *buf, unsigned max)
+ + {
+ + 	int				count;
+ + 	int				tmp;
+ + 	struct usb_host_endpoint	*hep = qh->hep;
+ + 	struct urb			*urb;
+ + 
+ + 	count = snprintf(buf, max, "    qh %p dev%d ep%d%s max%d\n",
+ + 			qh, qh->dev->devnum, qh->epnum,
+ + 			({ char *s; switch (qh->type) {
+ + 			case USB_ENDPOINT_XFER_BULK:
+ + 				s = "-bulk"; break;
+ + 			case USB_ENDPOINT_XFER_INT:
+ + 				s = "-int"; break;
+ + 			case USB_ENDPOINT_XFER_CONTROL:
+ + 				s = ""; break;
+ + 			default:
+ + 				s = "iso"; break;
+ + 			}; s; }),
+ + 			qh->maxpacket);
+ + 	if (count <= 0)
+ + 		return 0;
+ + 	buf += count;
+ + 	max -= count;
+ + 
+ + 	list_for_each_entry(urb, &hep->urb_list, urb_list) {
+ + 		tmp = snprintf(buf, max, "\t%s urb %p %d/%d\n",
+ + 				usb_pipein(urb->pipe) ? "in" : "out",
+ + 				urb, urb->actual_length,
+ + 				urb->transfer_buffer_length);
+ + 		if (tmp <= 0)
+ + 			break;
+ + 		tmp = min(tmp, (int)max);
+ + 		count += tmp;
+ + 		buf += tmp;
+ + 		max -= tmp;
+ + 	}
+ + 	return count;
+ + }
+ + 
+ + static int
+ + dump_queue(struct list_head *q, char *buf, unsigned max)
+ + {
+ + 	int		count = 0;
+ + 	struct musb_qh	*qh;
+ + 
+ + 	list_for_each_entry(qh, q, ring) {
+ + 		int	tmp;
+ + 
+ + 		tmp = dump_qh(qh, buf, max);
+ + 		if (tmp <= 0)
+ + 			break;
+ + 		tmp = min(tmp, (int)max);
+ + 		count += tmp;
+ + 		buf += tmp;
+ + 		max -= tmp;
+ + 	}
+ + 	return count;
+ + }
+ + 
+ + static int dump_ep(struct musb_ep *ep, char *buffer, unsigned max)
+ + {
+ + 	char		*buf = buffer;
+ + 	int		code = 0;
+ + 	void __iomem	*regs = ep->hw_ep->regs;
+ + 	char		*mode = "1buf";
+ + 
+ + 	if (ep->is_in) {
+ + 		if (ep->hw_ep->tx_double_buffered)
+ + 			mode = "2buf";
+ + 	} else {
+ + 		if (ep->hw_ep->rx_double_buffered)
+ + 			mode = "2buf";
+ + 	}
+ + 
+ + 	do {
+ + 		struct usb_request	*req;
+ + 
+ + 		code = snprintf(buf, max,
+ + 				"\n%s (hw%d): %s%s, csr %04x maxp %04x\n",
+ + 				ep->name, ep->current_epnum,
+ + 				mode, ep->dma ? " dma" : "",
+ + 				musb_readw(regs,
+ + 					(ep->is_in || !ep->current_epnum)
+ + 						? MUSB_TXCSR
+ + 						: MUSB_RXCSR),
+ + 				musb_readw(regs, ep->is_in
+ + 						? MUSB_TXMAXP
+ + 						: MUSB_RXMAXP)
+ + 				);
+ + 		if (code <= 0)
+ + 			break;
+ + 		code = min(code, (int) max);
+ + 		buf += code;
+ + 		max -= code;
+ + 
+ + 		if ((is_cppi_enabled(ep->musb) || is_cppi41_enabled(ep->musb))
+ + 				&& ep->current_epnum) {
+ + 			unsigned	cppi = ep->current_epnum - 1;
+ + 			void __iomem	*base = ep->musb->ctrl_base;
+ + 			unsigned	off1 = cppi << 2;
+ + 			void __iomem	*ram = base;
+ + 			char		tmp[16];
+ + 
+ + 			if (ep->is_in) {
+ + 				ram += DAVINCI_TXCPPI_STATERAM_OFFSET(cppi);
+ + 				tmp[0] = 0;
+ + 			} else {
+ + 				ram += DAVINCI_RXCPPI_STATERAM_OFFSET(cppi);
+ + 				snprintf(tmp, sizeof tmp, "%d left, ",
+ + 					musb_readl(base,
+ + 					DAVINCI_RXCPPI_BUFCNT0_REG + off1));
+ + 			}
+ + 
+ + 			code = snprintf(buf, max, "%cX DMA%d: %s"
+ + 					"%08x %08x, %08x %08x; "
+ + 					"%08x %08x %08x .. %08x\n",
+ + 				ep->is_in ? 'T' : 'R',
+ + 				ep->current_epnum - 1, tmp,
+ + 				musb_readl(ram, 0 * 4),
+ + 				musb_readl(ram, 1 * 4),
+ + 				musb_readl(ram, 2 * 4),
+ + 				musb_readl(ram, 3 * 4),
+ + 				musb_readl(ram, 4 * 4),
+ + 				musb_readl(ram, 5 * 4),
+ + 				musb_readl(ram, 6 * 4),
+ + 				musb_readl(ram, 7 * 4));
+ + 			if (code <= 0)
+ + 				break;
+ + 			code = min(code, (int) max);
+ + 			buf += code;
+ + 			max -= code;
+ + 		}
+ + 
+ + 		if (list_empty(&ep->req_list)) {
+ + 			code = snprintf(buf, max, "\t(queue empty)\n");
+ + 			if (code <= 0)
+ + 				break;
+ + 			code = min(code, (int) max);
+ + 			buf += code;
+ + 			max -= code;
+ + 			break;
+ + 		}
+ + 		list_for_each_entry(req, &ep->req_list, list) {
+ + 			code = snprintf(buf, max, "\treq %p, %s%s%d/%d\n",
+ + 					req,
+ + 					req->zero ? "zero, " : "",
+ + 					req->short_not_ok ? "!short, " : "",
+ + 					req->actual, req->length);
+ + 			if (code <= 0)
+ + 				break;
+ + 			code = min(code, (int) max);
+ + 			buf += code;
+ + 			max -= code;
+ + 		}
+ + 	} while (0);
+ + 	return buf - buffer;
+ + }
+ + 
+ + static int
+ + dump_end_info(struct musb *musb, u8 epnum, char *aBuffer, unsigned max)
+ + {
+ + 	int			code = 0;
+ + 	char			*buf = aBuffer;
+ + 	struct musb_hw_ep	*hw_ep = &musb->endpoints[epnum];
+ + 
+ + 	do {
+ + 		musb_ep_select(musb, musb->mregs, epnum);
+ + 		if (is_host_active(musb)) {
+ + 			int		dump_rx, dump_tx;
+ + 			void __iomem	*regs = hw_ep->regs;
+ + 
+ + 			/* TEMPORARY (!) until we have a real periodic
+ + 			 * schedule tree ...
+ + 			 */
+ + 			if (!epnum) {
+ + 				/* control is shared, uses RX queue
+ + 				 * but (mostly) shadowed tx registers
+ + 				 */
+ + 				dump_tx = !list_empty(&musb->control);
+ + 				dump_rx = 0;
+ + 			} else if (hw_ep == musb->bulk_ep) {
+ + 				dump_tx = !list_empty(&musb->out_bulk);
+ + 				dump_rx = !list_empty(&musb->in_bulk);
+ + 			} else if (hw_ep->in_qh || hw_ep->out_qh) {
+ + 				if (hw_ep->in_qh)
+ + 					dump_rx = 1;
+ + 				else
+ + 					dump_rx = 0;
+ + 				dump_tx = !dump_rx;
+ + 			} else
+ + 				break;
+ + 			/* END TEMPORARY */
+ + 
+ + 
+ + 			if (dump_rx) {
+ + 				code = snprintf(buf, max,
+ + 					"\nRX%d: %s rxcsr %04x interval %02x "
+ + 					"max %04x type %02x; "
+ + 					"dev %d hub %d port %d"
+ + 					"\n",
+ + 					epnum,
+ + 					hw_ep->rx_double_buffered
+ + 						? "2buf" : "1buf",
+ + 					musb_readw(regs, MUSB_RXCSR),
+ + 					musb_readb(regs, MUSB_RXINTERVAL),
+ + 					musb_readw(regs, MUSB_RXMAXP),
+ + 					musb_readb(regs, MUSB_RXTYPE),
+ + 					/* FIXME:  assumes multipoint */
+ + 					musb_readb(musb->mregs,
+ + 						MUSB_BUSCTL_OFFSET(epnum,
+ + 						MUSB_RXFUNCADDR)),
+ + 					musb_readb(musb->mregs,
+ + 						MUSB_BUSCTL_OFFSET(epnum,
+ + 						MUSB_RXHUBADDR)),
+ + 					musb_readb(musb->mregs,
+ + 						MUSB_BUSCTL_OFFSET(epnum,
+ + 						MUSB_RXHUBPORT))
+ + 					);
+ + 				if (code <= 0)
+ + 					break;
+ + 				code = min(code, (int) max);
+ + 				buf += code;
+ + 				max -= code;
+ + 
+ + 				if ((is_cppi_enabled(musb) ||
+ + 						is_cppi41_enabled(musb))
+ + 						&& epnum
+ + 						&& hw_ep->rx_channel) {
+ + 					unsigned	cppi = epnum - 1;
+ + 					unsigned	off1 = cppi << 2;
+ + 					void __iomem	*base;
+ + 					void __iomem	*ram;
+ + 					char		tmp[16];
+ + 
+ + 					base = musb->ctrl_base;
+ + 					ram = DAVINCI_RXCPPI_STATERAM_OFFSET(
+ + 							cppi) + base;
+ + 					snprintf(tmp, sizeof tmp, "%d left, ",
+ + 						musb_readl(base,
+ + 						DAVINCI_RXCPPI_BUFCNT0_REG
+ + 								+ off1));
+ + 
+ + 					code = snprintf(buf, max,
+ + 						"    rx dma%d: %s"
+ + 						"%08x %08x, %08x %08x; "
+ + 						"%08x %08x %08x .. %08x\n",
+ + 						cppi, tmp,
+ + 						musb_readl(ram, 0 * 4),
+ + 						musb_readl(ram, 1 * 4),
+ + 						musb_readl(ram, 2 * 4),
+ + 						musb_readl(ram, 3 * 4),
+ + 						musb_readl(ram, 4 * 4),
+ + 						musb_readl(ram, 5 * 4),
+ + 						musb_readl(ram, 6 * 4),
+ + 						musb_readl(ram, 7 * 4));
+ + 					if (code <= 0)
+ + 						break;
+ + 					code = min(code, (int) max);
+ + 					buf += code;
+ + 					max -= code;
+ + 				}
+ + 
+ + 				if (hw_ep == musb->bulk_ep
+ + 						&& !list_empty(
+ + 							&musb->in_bulk)) {
+ + 					code = dump_queue(&musb->in_bulk,
+ + 							buf, max);
+ + 					if (code <= 0)
+ + 						break;
+ + 					code = min(code, (int) max);
+ + 					buf += code;
+ + 					max -= code;
+ + 				} else if (hw_ep->in_qh) {
+ + 					code = dump_qh(hw_ep->in_qh,
+ + 							buf, max);
+ + 					if (code <= 0)
+ + 						break;
+ + 					code = min(code, (int) max);
+ + 					buf += code;
+ + 					max -= code;
+ + 				}
+ + 			}
+ + 
+ + 			if (dump_tx) {
+ + 				code = snprintf(buf, max,
+ + 					"\nTX%d: %s txcsr %04x interval %02x "
+ + 					"max %04x type %02x; "
+ + 					"dev %d hub %d port %d"
+ + 					"\n",
+ + 					epnum,
+ + 					hw_ep->tx_double_buffered
+ + 						? "2buf" : "1buf",
+ + 					musb_readw(regs, MUSB_TXCSR),
+ + 					musb_readb(regs, MUSB_TXINTERVAL),
+ + 					musb_readw(regs, MUSB_TXMAXP),
+ + 					musb_readb(regs, MUSB_TXTYPE),
+ + 					/* FIXME:  assumes multipoint */
+ + 					musb_readb(musb->mregs,
+ + 						MUSB_BUSCTL_OFFSET(epnum,
+ + 						MUSB_TXFUNCADDR)),
+ + 					musb_readb(musb->mregs,
+ + 						MUSB_BUSCTL_OFFSET(epnum,
+ + 						MUSB_TXHUBADDR)),
+ + 					musb_readb(musb->mregs,
+ + 						MUSB_BUSCTL_OFFSET(epnum,
+ + 						MUSB_TXHUBPORT))
+ + 					);
+ + 				if (code <= 0)
+ + 					break;
+ + 				code = min(code, (int) max);
+ + 				buf += code;
+ + 				max -= code;
+ + 
+ + 				if ((is_cppi_enabled(musb) ||
+ + 						is_cppi41_enabled(musb))
+ + 						&& epnum
+ + 						&& hw_ep->tx_channel) {
+ + 					unsigned	cppi = epnum - 1;
+ + 					void __iomem	*base;
+ + 					void __iomem	*ram;
+ + 
+ + 					base = musb->ctrl_base;
+ + 					ram = DAVINCI_RXCPPI_STATERAM_OFFSET(
+ + 							cppi) + base;
+ + 					code = snprintf(buf, max,
+ + 						"    tx dma%d: "
+ + 						"%08x %08x, %08x %08x; "
+ + 						"%08x %08x %08x .. %08x\n",
+ + 						cppi,
+ + 						musb_readl(ram, 0 * 4),
+ + 						musb_readl(ram, 1 * 4),
+ + 						musb_readl(ram, 2 * 4),
+ + 						musb_readl(ram, 3 * 4),
+ + 						musb_readl(ram, 4 * 4),
+ + 						musb_readl(ram, 5 * 4),
+ + 						musb_readl(ram, 6 * 4),
+ + 						musb_readl(ram, 7 * 4));
+ + 					if (code <= 0)
+ + 						break;
+ + 					code = min(code, (int) max);
+ + 					buf += code;
+ + 					max -= code;
+ + 				}
+ + 
+ + 				if (hw_ep == musb->control_ep
+ + 						&& !list_empty(
+ + 							&musb->control)) {
+ + 					code = dump_queue(&musb->control,
+ + 							buf, max);
+ + 					if (code <= 0)
+ + 						break;
+ + 					code = min(code, (int) max);
+ + 					buf += code;
+ + 					max -= code;
+ + 				} else if (hw_ep == musb->bulk_ep
+ + 						&& !list_empty(
+ + 							&musb->out_bulk)) {
+ + 					code = dump_queue(&musb->out_bulk,
+ + 							buf, max);
+ + 					if (code <= 0)
+ + 						break;
+ + 					code = min(code, (int) max);
+ + 					buf += code;
+ + 					max -= code;
+ + 				} else if (hw_ep->out_qh) {
+ + 					code = dump_qh(hw_ep->out_qh,
+ + 							buf, max);
+ + 					if (code <= 0)
+ + 						break;
+ + 					code = min(code, (int) max);
+ + 					buf += code;
+ + 					max -= code;
+ + 				}
+ + 			}
+ + 		}
+ + 		if (is_peripheral_active(musb)) {
+ + 			code = 0;
+ + 
+ + 			if (hw_ep->ep_in.desc || !epnum) {
+ + 				code = dump_ep(&hw_ep->ep_in, buf, max);
+ + 				if (code <= 0)
+ + 					break;
+ + 				code = min(code, (int) max);
+ + 				buf += code;
+ + 				max -= code;
+ + 			}
+ + 			if (hw_ep->ep_out.desc) {
+ + 				code = dump_ep(&hw_ep->ep_out, buf, max);
+ + 				if (code <= 0)
+ + 					break;
+ + 				code = min(code, (int) max);
+ + 				buf += code;
+ + 				max -= code;
+ + 			}
+ + 		}
+ + 	} while (0);
+ + 
+ + 	return buf - aBuffer;
+ + }
+ + 
+ + /* Dump the current status and compile options.
+ +  * @param musb the device driver instance
+ +  * @param buffer where to dump the status; it must be big enough to hold the
+ +  * result otherwise "BAD THINGS HAPPENS(TM)".
+ +  */
+ + static int dump_header_stats(struct musb *musb, char *buffer)
+ + {
+ + 	int code, count = 0;
+ + 	const void __iomem *mbase = musb->mregs;
+ + 
+ + 	*buffer = 0;
+ + 	count = sprintf(buffer, "Status: %sHDRC, Mode=%s "
+ + 				"(Power=%02x, DevCtl=%02x)\n",
+ + 			(musb->is_multipoint ? "M" : ""), MUSB_MODE(musb),
+ + 			musb_readb(mbase, MUSB_POWER),
+ + 			musb_readb(mbase, MUSB_DEVCTL));
+ + 	if (count <= 0)
+ + 		return 0;
+ + 	buffer += count;
+ + 
+ + 	code = sprintf(buffer, "OTG state: %s; %sactive\n",
+ + 			otg_state_string(musb->xceiv->state),
+ + 			musb->is_active ? "" : "in");
+ + 	if (code <= 0)
+ + 		goto done;
+ + 	buffer += code;
+ + 	count += code;
+ + 
+ + 	code = sprintf(buffer,
+ + 			"Options: "
+ + #ifdef CONFIG_MUSB_PIO_ONLY
+ + 			"pio"
+ + #elif defined(CONFIG_USB_TI_CPPI_DMA)
+ + 			"cppi-dma"
+ + #elif defined(CONFIG_USB_INVENTRA_DMA)
+ + 			"musb-dma"
+ + #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
+ + 			"tusb-omap-dma"
+ + #else
+ + 			"?dma?"
+ + #endif
+ + 			", "
+ + 			"otg (peripheral+host)"
+ + 			", [eps=%d]\n",
+ + 		musb->nr_endpoints);
+ + 	if (code <= 0)
+ + 		goto done;
+ + 	count += code;
+ + 	buffer += code;
+ + 
+ + 	code = sprintf(buffer, "Peripheral address: %02x\n",
+ + 			musb_readb(musb->ctrl_base, MUSB_FADDR));
+ + 	if (code <= 0)
+ + 		goto done;
+ + 	buffer += code;
+ + 	count += code;
+ + 
+ + 	code = sprintf(buffer, "Root port status: %08x\n",
+ + 			musb->port1_status);
+ + 	if (code <= 0)
+ + 		goto done;
+ + 	buffer += code;
+ + 	count += code;
+ + 
+ + #ifdef	CONFIG_ARCH_DAVINCI
+ + 	code = sprintf(buffer,
+ + 			"DaVinci: ctrl=%02x stat=%1x phy=%03x\n"
+ + 			"\trndis=%05x auto=%04x intsrc=%08x intmsk=%08x"
+ + 			"\n",
+ + 			musb_readl(musb->ctrl_base, DAVINCI_USB_CTRL_REG),
+ + 			musb_readl(musb->ctrl_base, DAVINCI_USB_STAT_REG),
+ + 			readl((void __force __iomem *)
+ + 					IO_ADDRESS(USBPHY_CTL_PADDR)),
+ + 			musb_readl(musb->ctrl_base, DAVINCI_RNDIS_REG),
+ + 			musb_readl(musb->ctrl_base, DAVINCI_AUTOREQ_REG),
+ + 			musb_readl(musb->ctrl_base,
+ + 					DAVINCI_USB_INT_SOURCE_REG),
+ + 			musb_readl(musb->ctrl_base,
+ + 					DAVINCI_USB_INT_MASK_REG));
+ + 	if (code <= 0)
+ + 		goto done;
+ + 	count += code;
+ + 	buffer += code;
+ + #endif	/* DAVINCI */
+ + 
+ + #ifdef CONFIG_USB_TUSB6010
+ + 	code = sprintf(buffer,
+ + 			"TUSB6010: devconf %08x, phy enable %08x drive %08x"
+ + 			"\n\totg %03x timer %08x"
+ + 			"\n\tprcm conf %08x mgmt %08x; int src %08x mask %08x"
+ + 			"\n",
+ + 			musb_readl(musb->ctrl_base, TUSB_DEV_CONF),
+ + 			musb_readl(musb->ctrl_base, TUSB_PHY_OTG_CTRL_ENABLE),
+ + 			musb_readl(musb->ctrl_base, TUSB_PHY_OTG_CTRL),
+ + 			musb_readl(musb->ctrl_base, TUSB_DEV_OTG_STAT),
+ + 			musb_readl(musb->ctrl_base, TUSB_DEV_OTG_TIMER),
+ + 			musb_readl(musb->ctrl_base, TUSB_PRCM_CONF),
+ + 			musb_readl(musb->ctrl_base, TUSB_PRCM_MNGMT),
+ + 			musb_readl(musb->ctrl_base, TUSB_INT_SRC),
+ + 			musb_readl(musb->ctrl_base, TUSB_INT_MASK));
+ + 	if (code <= 0)
+ + 		goto done;
+ + 	count += code;
+ + 	buffer += code;
+ + #endif	/* DAVINCI */
+ + 
+ + 	if ((is_cppi_enabled(musb) || is_cppi41_enabled(musb))
+ + 		&& musb->dma_controller) {
+ + 		code = sprintf(buffer,
+ + 				"CPPI: txcr=%d txsrc=%01x txena=%01x; "
+ + 				"rxcr=%d rxsrc=%01x rxena=%01x "
+ + 				"\n",
+ + 				musb_readl(musb->ctrl_base,
+ + 						DAVINCI_TXCPPI_CTRL_REG),
+ + 				musb_readl(musb->ctrl_base,
+ + 						DAVINCI_TXCPPI_RAW_REG),
+ + 				musb_readl(musb->ctrl_base,
+ + 						DAVINCI_TXCPPI_INTENAB_REG),
+ + 				musb_readl(musb->ctrl_base,
+ + 						DAVINCI_RXCPPI_CTRL_REG),
+ + 				musb_readl(musb->ctrl_base,
+ + 						DAVINCI_RXCPPI_RAW_REG),
+ + 				musb_readl(musb->ctrl_base,
+ + 						DAVINCI_RXCPPI_INTENAB_REG));
+ + 		if (code <= 0)
+ + 			goto done;
+ + 		count += code;
+ + 		buffer += code;
+ + 	}
+ + 
+ + 	if (is_peripheral_enabled(musb)) {
+ + 		code = sprintf(buffer, "Gadget driver: %s\n",
+ + 				musb->gadget_driver
+ + 					? musb->gadget_driver->driver.name
+ + 					: "(none)");
+ + 		if (code <= 0)
+ + 			goto done;
+ + 		count += code;
+ + 		buffer += code;
+ + 	}
+ + 
+ + done:
+ + 	return count;
+ + }
+ + 
+ + /* Write to ProcFS
+ +  *
+ +  * C soft-connect
+ +  * c soft-disconnect
+ +  * I enable HS
+ +  * i disable HS
+ +  * s stop session
+ +  * F force session (OTG-unfriendly)
+ +  * E rElinquish bus (OTG)
+ +  * H request host mode
+ +  * h cancel host request
+ +  * T start sending TEST_PACKET
+ +  * D<num> set/query the debug level
+ +  */
+ + static int musb_proc_write(struct file *file, const char __user *buffer,
+ + 			unsigned long count, void *data)
+ + {
+ + 	char cmd;
+ + 	u8 reg;
+ + 	struct musb *musb = (struct musb *)data;
+ + 	void __iomem *mbase = musb->mregs;
+ + 
+ + 	/* MOD_INC_USE_COUNT; */
+ + 
+ + 	if (unlikely(copy_from_user(&cmd, buffer, 1)))
+ + 		return -EFAULT;
+ + 
+ + 	switch (cmd) {
+ + 	case 'S':
+ + 		if (mbase) {
+ + 			reg = musb_readb(mbase, MUSB_POWER)
+ + 					| MUSB_POWER_SUSPENDM;
+ + 			musb_writeb(mbase, MUSB_POWER, reg);
+ + 		}
+ + 		break;
+ + 
+ + 	case 'C':
+ + 		if (mbase) {
+ + 			reg = musb_readb(mbase, MUSB_POWER)
+ + 					| MUSB_POWER_SOFTCONN;
+ + 			musb_writeb(mbase, MUSB_POWER, reg);
+ + 		}
+ + 		break;
+ + 
+ + 	case 'c':
+ + 		if (mbase) {
+ + 			reg = musb_readb(mbase, MUSB_POWER)
+ + 					& ~MUSB_POWER_SOFTCONN;
+ + 			musb_writeb(mbase, MUSB_POWER, reg);
+ + 		}
+ + 		break;
+ + 
+ + 	case 'I':
+ + 		if (mbase) {
+ + 			reg = musb_readb(mbase, MUSB_POWER)
+ + 					| MUSB_POWER_HSENAB;
+ + 			musb_writeb(mbase, MUSB_POWER, reg);
+ + 		}
+ + 		break;
+ + 
+ + 	case 'i':
+ + 		if (mbase) {
+ + 			reg = musb_readb(mbase, MUSB_POWER)
+ + 					& ~MUSB_POWER_HSENAB;
+ + 			musb_writeb(mbase, MUSB_POWER, reg);
+ + 		}
+ + 		break;
+ + 
+ + 	case 'F':
+ + 		reg = musb_readb(mbase, MUSB_DEVCTL);
+ + 		reg |= MUSB_DEVCTL_SESSION;
+ + 		musb_writeb(mbase, MUSB_DEVCTL, reg);
+ + 		break;
+ + 
+ + 	case 'H':
+ + 		if (mbase) {
+ + 			reg = musb_readb(mbase, MUSB_DEVCTL);
+ + 			reg |= MUSB_DEVCTL_HR;
+ + 			musb_writeb(mbase, MUSB_DEVCTL, reg);
+ + 			/* MUSB_HST_MODE( ((struct musb*)data) ); */
+ + 			/* WARNING("Host Mode\n"); */
+ + 		}
+ + 		break;
+ + 
+ + 	case 'h':
+ + 		if (mbase) {
+ + 			reg = musb_readb(mbase, MUSB_DEVCTL);
+ + 			reg &= ~MUSB_DEVCTL_HR;
+ + 			musb_writeb(mbase, MUSB_DEVCTL, reg);
+ + 		}
+ + 		break;
+ + 
+ + 	case 'T':
+ + 		if (mbase) {
+ + 			musb_load_testpacket(musb);
+ + 			musb_writeb(mbase, MUSB_TESTMODE,
+ + 					MUSB_TEST_PACKET);
+ + 			musb_writew(musb->endpoints[0].regs,
+ + 				MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
+ + 			dev_dbg(musb->controller,
+ + 				"musb:testmode sending test packet\n");
+ + 		}
+ + 		break;
+ + 
+ + 	case 'b':
+ + 		/* generate software babble interrupt */
+ + 		musb_simulate_babble_intr(musb);
+ + 		break;
+ + 
+ + 	case 'K':
+ + 		/* enable babble workaround */
+ + 		musb->enable_babble_work = 1;
+ + 		INFO("enabled babble workaround\n");
+ + 		break;
+ + 
+ + 	case 'k':
+ + 		/* disable babble workaround */
+ + 		musb->enable_babble_work = 0;
+ + 		INFO("disabled babble workaround\n");
+ + 		break;
+ + 
+ + 	case '?':
+ + 		INFO("?: you are seeing it\n");
+ + 		INFO("S: suspend the usb bus\n");
+ + 		INFO("C/c: soft connect enable/disable\n");
+ + 		INFO("I/i: hispeed enable/disable\n");
+ + 		INFO("F: force session start\n");
+ + 		INFO("H: host mode\n");
+ + 		INFO("T: start sending TEST_PACKET\n");
+ + 		INFO("D: set/read dbug level\n");
+ + 		INFO("K/k: enable/disable babble workaround\n");
+ + 		INFO("b: generate software babble interrupt\n");
+ + 		break;
+ + 
+ + 	default:
+ + 		ERR("Command %c not implemented\n", cmd);
+ + 		break;
+ + 	}
+ + 
+ + 	musb_platform_try_idle(musb, 0);
+ + 
+ + 	return count;
+ + }
+ + 
+ + static int musb_proc_read(char *page, char **start,
+ + 			off_t off, int count, int *eof, void *data)
+ + {
+ + 	char *buffer = page;
+ + 	int code = 0;
+ + 	unsigned long	flags;
+ + 	struct musb	*musb = data;
+ + 	unsigned	epnum;
+ + 
+ + 	count -= off;
+ + 	count -= 1;		/* for NUL at end */
+ + 	if (count <= 0)
+ + 		return -EINVAL;
+ + 
+ + 	spin_lock_irqsave(&musb->lock, flags);
+ + 
+ + 	code = dump_header_stats(musb, buffer);
+ + 	if (code > 0) {
+ + 		buffer += code;
+ + 		count -= code;
+ + 	}
+ + 
+ + 	/* generate the report for the end points */
+ + 	/* REVISIT ... not unless something's connected! */
+ + 	for (epnum = 0; count >= 0 && epnum < musb->nr_endpoints;
+ + 			epnum++) {
+ + 		code = dump_end_info(musb, epnum, buffer, count);
+ + 		if (code > 0) {
+ + 			buffer += code;
+ + 			count -= code;
+ + 		}
+ + 	}
+ + 
+ + 	musb_platform_try_idle(musb, 0);
+ + 
+ + 	spin_unlock_irqrestore(&musb->lock, flags);
+ + 	*eof = 1;
+ + 
+ + 	return buffer - page;
+ + }
+ + 
+ + void musb_debug_delete(char *name, struct musb *musb)
+ + {
+ + 	if (musb->proc_entry)
+ + 		remove_proc_entry(name, NULL);
+ + }
+ + 
+ + struct proc_dir_entry *__devinit
+ + musb_debug_create(char *name, struct musb *data)
+ + {
+ + 	struct proc_dir_entry	*pde;
+ + 
+ + 	/* FIXME convert everything to seq_file; then later, debugfs */
+ + 
+ + 	if (!name)
+ + 		return NULL;
+ + 
+ + 	pde = create_proc_entry(name, S_IFREG | S_IRUGO | S_IWUSR, NULL);
+ + 	data->proc_entry = pde;
+ + 	if (pde) {
+ + 		pde->data = data;
+ + 		/* pde->owner = THIS_MODULE; */
+ + 
+ + 		pde->read_proc = musb_proc_read;
+ + 		pde->write_proc = musb_proc_write;
+ + 
+ + 		pde->size = 0;
+ + 
+ + 		pr_debug("Registered /proc/%s\n", name);
+ + 	} else {
+ + 		pr_debug("Cannot create a valid proc file entry");
+ + 	}
+ + 
+ + 	return pde;
+ + }
+ diff -crN linux-3.2.1_o/drivers/usb/musb/musb_regs.h linux-3.2.1/drivers/usb/musb/musb_regs.h
+ *** linux-3.2.1_o/drivers/usb/musb/musb_regs.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/musb/musb_regs.h	2014-11-25 13:19:16.683128762 +0900
+ ***************
+ *** 202,207 ****
+ --- 202,213 ----
+   #define MUSB_RXCSR_H_REQPKT		0x0020
+   #define MUSB_RXCSR_H_ERROR		0x0004
+   
+ + /* MISC control register offs 0x61 */
+ + #define MUSB_MISC_FORCE_TXIDLE		0x80
+ + #define MUSB_MISC_SW_SESSION_CTRL	0x40
+ + #define MUSB_MISC_STUCK_J		0x20
+ + #define MUSB_MISC_RCV_DISABLE		0x04
+ + 
+   /* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
+   #define MUSB_RXCSR_P_WZC_BITS	\
+   	(MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \
+ ***************
+ *** 234,251 ****
+   #define MUSB_TESTMODE		0x0F	/* 8 bit */
+   
+   /* Get offset for a given FIFO from musb->mregs */
+ ! #if defined(CONFIG_USB_MUSB_TUSB6010) ||	\
+ ! 	defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
+ ! #define MUSB_FIFO_OFFSET(epnum)	(0x200 + ((epnum) * 0x20))
+ ! #else
+   #define MUSB_FIFO_OFFSET(epnum)	(0x20 + ((epnum) * 4))
+ - #endif
+   
+   /*
+    * Additional Control Registers
+    */
+   
+   #define MUSB_DEVCTL		0x60	/* 8 bit */
+   
+   /* These are always controlled through the INDEX register */
+   #define MUSB_TXFIFOSZ		0x62	/* 8-bit (see masks) */
+ --- 240,254 ----
+   #define MUSB_TESTMODE		0x0F	/* 8 bit */
+   
+   /* Get offset for a given FIFO from musb->mregs */
+ ! #define MUSB_TUSB_FIFO_OFFSET(epnum)	(0x200 + ((epnum) * 0x20))
+   #define MUSB_FIFO_OFFSET(epnum)	(0x20 + ((epnum) * 4))
+   
+   /*
+    * Additional Control Registers
+    */
+   
+   #define MUSB_DEVCTL		0x60	/* 8 bit */
+ + #define MUSB_MISC		0x61	/* 8 bit babble control bits */
+   
+   /* These are always controlled through the INDEX register */
+   #define MUSB_TXFIFOSZ		0x62	/* 8-bit (see masks) */
+ ***************
+ *** 288,308 ****
+   #define MUSB_FIFOSIZE		0x0F
+   #define MUSB_CONFIGDATA		MUSB_FIFOSIZE	/* Re-used for EP0 */
+   
+   /* Offsets to endpoint registers in indexed model (using INDEX register) */
+ ! #define MUSB_INDEXED_OFFSET(_epnum, _offset)	\
+   	(0x10 + (_offset))
+   
+   /* Offsets to endpoint registers in flat models */
+ ! #define MUSB_FLAT_OFFSET(_epnum, _offset)	\
+   	(0x100 + (0x10*(_epnum)) + (_offset))
+   
+ - #if defined(CONFIG_USB_MUSB_TUSB6010) ||	\
+ - 	defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
+ - /* TUSB6010 EP0 configuration register is special */
+ - #define MUSB_TUSB_OFFSET(_epnum, _offset)	\
+ - 	(0x10 + _offset)
+   #include "tusb6010.h"		/* Needed "only" for TUSB_EP0_CONF */
+ - #endif
+   
+   #define MUSB_TXCSR_MODE			0x2000
+   
+ --- 291,313 ----
+   #define MUSB_FIFOSIZE		0x0F
+   #define MUSB_CONFIGDATA		MUSB_FIFOSIZE	/* Re-used for EP0 */
+   
+ + 
+ + #if 0
+   /* Offsets to endpoint registers in indexed model (using INDEX register) */
+ ! #define MUSB_INDEXED_OFFSET(_musb, _epnum, _offset)	\
+   	(0x10 + (_offset))
+   
+   /* Offsets to endpoint registers in flat models */
+ ! #define MUSB_FLAT_OFFSET(_musb, _epnum, _offset)	\
+   	(0x100 + (0x10*(_epnum)) + (_offset))
+ + #endif
+ + 
+ + #define MUSB_OFFSET(_musb, _epnum, _offset)	\
+ + 	((_musb)->ops->flags & MUSB_GLUE_EP_ADDR_INDEXED_MAPPING ? \
+ + 		(0x10 + (_offset)) : (0x100 + (0x10*(_epnum)) + (_offset)))
+ + 
+   
+   #include "tusb6010.h"		/* Needed "only" for TUSB_EP0_CONF */
+   
+   #define MUSB_TXCSR_MODE			0x2000
+   
+ ***************
+ *** 506,516 ****
+   #define MUSB_TXCOUNT		0x28
+   
+   /* Offsets to endpoint registers in indexed model (using INDEX register) */
+ ! #define MUSB_INDEXED_OFFSET(_epnum, _offset)	\
+   	(0x40 + (_offset))
+   
+   /* Offsets to endpoint registers in flat models */
+ ! #define MUSB_FLAT_OFFSET(_epnum, _offset)	\
+   	(USB_OFFSET(USB_EP_NI0_TXMAXP) + (0x40 * (_epnum)) + (_offset))
+   
+   /* Not implemented - HW has separate Tx/Rx FIFO */
+ --- 511,521 ----
+   #define MUSB_TXCOUNT		0x28
+   
+   /* Offsets to endpoint registers in indexed model (using INDEX register) */
+ ! #define MUSB_INDEXED_OFFSET(_musb, _epnum, _offset)	\
+   	(0x40 + (_offset))
+   
+   /* Offsets to endpoint registers in flat models */
+ ! #define MUSB_FLAT_OFFSET(_musb, _epnum, _offset)	\
+   	(USB_OFFSET(USB_EP_NI0_TXMAXP) + (0x40 * (_epnum)) + (_offset))
+   
+   /* Not implemented - HW has separate Tx/Rx FIFO */
+ diff -crN linux-3.2.1_o/drivers/usb/musb/musb_virthub.c linux-3.2.1/drivers/usb/musb/musb_virthub.c
+ *** linux-3.2.1_o/drivers/usb/musb/musb_virthub.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/musb/musb_virthub.c	2014-11-25 13:19:16.688099134 +0900
+ ***************
+ *** 82,98 ****
+   			musb->xceiv->state = OTG_STATE_A_SUSPEND;
+   			musb->is_active = is_otg_enabled(musb)
+   					&& musb->xceiv->host->b_hnp_enable;
+ - 			if (musb->is_active)
+ - 				mod_timer(&musb->otg_timer, jiffies
+ - 					+ msecs_to_jiffies(
+ - 						OTG_TIME_A_AIDL_BDIS));
+   			musb_platform_try_idle(musb, 0);
+   			break;
+   		case OTG_STATE_B_HOST:
+ ! 			musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
+ ! 			musb->is_active = is_otg_enabled(musb)
+   					&& musb->xceiv->host->b_hnp_enable;
+ ! 			musb_platform_try_idle(musb, 0);
+   			break;
+   		default:
+   			dev_dbg(musb->controller, "bogus rh suspend? %s\n",
+ --- 82,96 ----
+   			musb->xceiv->state = OTG_STATE_A_SUSPEND;
+   			musb->is_active = is_otg_enabled(musb)
+   					&& musb->xceiv->host->b_hnp_enable;
+   			musb_platform_try_idle(musb, 0);
+   			break;
+   		case OTG_STATE_B_HOST:
+ ! 			if (is_otg_enabled(musb)) {
+ ! 				musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
+ ! 				musb->is_active = is_otg_enabled(musb)
+   					&& musb->xceiv->host->b_hnp_enable;
+ ! 				musb_platform_try_idle(musb, 0);
+ ! 			}
+   			break;
+   		default:
+   			dev_dbg(musb->controller, "bogus rh suspend? %s\n",
+ ***************
+ *** 116,122 ****
+   	u8		power;
+   	void __iomem	*mbase = musb->mregs;
+   
+ ! 	if (musb->xceiv->state == OTG_STATE_B_IDLE) {
+   		dev_dbg(musb->controller, "HNP: Returning from HNP; no hub reset from b_idle\n");
+   		musb->port1_status &= ~USB_PORT_STAT_RESET;
+   		return;
+ --- 114,120 ----
+   	u8		power;
+   	void __iomem	*mbase = musb->mregs;
+   
+ ! 	if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE) {
+   		dev_dbg(musb->controller, "HNP: Returning from HNP; no hub reset from b_idle\n");
+   		musb->port1_status &= ~USB_PORT_STAT_RESET;
+   		return;
+ ***************
+ *** 186,200 ****
+   	musb->is_active = 0;
+   
+   	switch (musb->xceiv->state) {
+ - 	case OTG_STATE_A_SUSPEND:
+ - 		if (is_otg_enabled(musb)
+ - 				&& musb->xceiv->host->b_hnp_enable) {
+ - 			musb->xceiv->state = OTG_STATE_A_PERIPHERAL;
+ - 			musb->g.is_a_peripheral = 1;
+ - 			break;
+ - 		}
+ - 		/* FALLTHROUGH */
+   	case OTG_STATE_A_HOST:
+   		musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
+   		musb->is_active = 0;
+   		break;
+ --- 184,191 ----
+   	musb->is_active = 0;
+   
+   	switch (musb->xceiv->state) {
+   	case OTG_STATE_A_HOST:
+ + 	case OTG_STATE_A_SUSPEND:
+   		musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
+   		musb->is_active = 0;
+   		break;
+ ***************
+ *** 414,419 ****
+ --- 405,414 ----
+   				goto error;
+   			}
+   			musb_writeb(musb->mregs, MUSB_TESTMODE, temp);
+ + 			if (wIndex == 4) {
+ + 				musb_writew(musb->endpoints[0].regs,
+ + 					MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
+ + 			}
+   			break;
+   		default:
+   			goto error;
+ diff -crN linux-3.2.1_o/drivers/usb/musb/omap2430.c linux-3.2.1/drivers/usb/musb/omap2430.c
+ *** linux-3.2.1_o/drivers/usb/musb/omap2430.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/musb/omap2430.c	2014-11-25 13:19:16.692109709 +0900
+ ***************
+ *** 29,35 ****
+   #include <linux/sched.h>
+   #include <linux/init.h>
+   #include <linux/list.h>
+ - #include <linux/clk.h>
+   #include <linux/io.h>
+   #include <linux/platform_device.h>
+   #include <linux/dma-mapping.h>
+ --- 29,34 ----
+ ***************
+ *** 96,101 ****
+ --- 95,101 ----
+   	spin_unlock_irqrestore(&musb->lock, flags);
+   }
+   
+ + #define MUSB_TIMEOUT_A_WAIT_BCON	1100
+   
+   static void omap2430_musb_try_idle(struct musb *musb, unsigned long timeout)
+   {
+ ***************
+ *** 228,248 ****
+   		unsigned long event, void *unused)
+   {
+   	struct musb	*musb = container_of(nb, struct musb, nb);
+   	struct device *dev = musb->controller;
+   	struct musb_hdrc_platform_data *pdata = dev->platform_data;
+   	struct omap_musb_board_data *data = pdata->board_data;
+   
+ ! 	switch (event) {
+   	case USB_EVENT_ID:
+   		dev_dbg(musb->controller, "ID GND\n");
+   
+ ! 		if (is_otg_enabled(musb)) {
+ ! 			if (musb->gadget_driver) {
+ ! 				pm_runtime_get_sync(musb->controller);
+ ! 				otg_init(musb->xceiv);
+ ! 				omap2430_musb_set_vbus(musb, 1);
+ ! 			}
+ ! 		} else {
+   			pm_runtime_get_sync(musb->controller);
+   			otg_init(musb->xceiv);
+   			omap2430_musb_set_vbus(musb, 1);
+ --- 228,252 ----
+   		unsigned long event, void *unused)
+   {
+   	struct musb	*musb = container_of(nb, struct musb, nb);
+ + 
+ + 	musb->xceiv_event = event;
+ + 	schedule_work(&musb->otg_notifier_work);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static void musb_otg_notifier_work(struct work_struct *data_notifier_work)
+ + {
+ + 	struct musb *musb = container_of(data_notifier_work, struct musb, otg_notifier_work);
+   	struct device *dev = musb->controller;
+   	struct musb_hdrc_platform_data *pdata = dev->platform_data;
+   	struct omap_musb_board_data *data = pdata->board_data;
+   
+ ! 	switch (musb->xceiv_event) {
+   	case USB_EVENT_ID:
+   		dev_dbg(musb->controller, "ID GND\n");
+   
+ ! 		if (!is_otg_enabled(musb) || musb->gadget_driver) {
+   			pm_runtime_get_sync(musb->controller);
+   			otg_init(musb->xceiv);
+   			omap2430_musb_set_vbus(musb, 1);
+ ***************
+ *** 274,283 ****
+   		break;
+   	default:
+   		dev_dbg(musb->controller, "ID float\n");
+ - 		return NOTIFY_DONE;
+   	}
+ - 
+ - 	return NOTIFY_OK;
+   }
+   
+   static int omap2430_musb_init(struct musb *musb)
+ --- 278,284 ----
+ ***************
+ *** 291,302 ****
+   	 * up through ULPI.  TWL4030-family PMICs include one,
+   	 * which needs a driver, drivers aren't always needed.
+   	 */
+ ! 	musb->xceiv = otg_get_transceiver();
+   	if (!musb->xceiv) {
+   		pr_err("HS USB OTG: no transceiver configured\n");
+   		return -ENODEV;
+   	}
+   
+   	status = pm_runtime_get_sync(dev);
+   	if (status < 0) {
+   		dev_err(dev, "pm_runtime_get_sync FAILED");
+ --- 292,305 ----
+   	 * up through ULPI.  TWL4030-family PMICs include one,
+   	 * which needs a driver, drivers aren't always needed.
+   	 */
+ ! 	musb->xceiv = otg_get_transceiver(musb->id);
+   	if (!musb->xceiv) {
+   		pr_err("HS USB OTG: no transceiver configured\n");
+   		return -ENODEV;
+   	}
+   
+ + 	INIT_WORK(&musb->otg_notifier_work, musb_otg_notifier_work);
+ + 
+   	status = pm_runtime_get_sync(dev);
+   	if (status < 0) {
+   		dev_err(dev, "pm_runtime_get_sync FAILED");
+ ***************
+ *** 329,340 ****
+   	if (status)
+   		dev_dbg(musb->controller, "notification register failed\n");
+   
+   	setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
+   
+   	return 0;
+   
+   err1:
+ - 	pm_runtime_disable(dev);
+   	return status;
+   }
+   
+ --- 332,343 ----
+   	if (status)
+   		dev_dbg(musb->controller, "notification register failed\n");
+   
+ + 	musb->a_wait_bcon = MUSB_TIMEOUT_A_WAIT_BCON;
+   	setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
+   
+   	return 0;
+   
+   err1:
+   	return status;
+   }
+   
+ ***************
+ *** 350,369 ****
+   
+   	case USB_EVENT_ID:
+   		otg_init(musb->xceiv);
+ ! 		if (data->interface_type == MUSB_INTERFACE_UTMI) {
+ ! 			devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
+ ! 			/* start the session */
+ ! 			devctl |= MUSB_DEVCTL_SESSION;
+ ! 			musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
+ ! 			while (musb_readb(musb->mregs, MUSB_DEVCTL) &
+ ! 						MUSB_DEVCTL_BDEVICE) {
+ ! 				cpu_relax();
+ ! 
+ ! 				if (time_after(jiffies, timeout)) {
+ ! 					dev_err(musb->controller,
+ ! 					"configured as A device timeout");
+ ! 					break;
+ ! 				}
+   			}
+   		}
+   		break;
+ --- 353,371 ----
+   
+   	case USB_EVENT_ID:
+   		otg_init(musb->xceiv);
+ ! 		if (data->interface_type != MUSB_INTERFACE_UTMI)
+ ! 			break;
+ ! 		devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
+ ! 		/* start the session */
+ ! 		devctl |= MUSB_DEVCTL_SESSION;
+ ! 		musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
+ ! 		while (musb_readb(musb->mregs, MUSB_DEVCTL) &
+ ! 				MUSB_DEVCTL_BDEVICE) {
+ ! 			cpu_relax();
+ ! 
+ ! 			if (time_after(jiffies, timeout)) {
+ ! 				dev_err(dev, "configured as A device timeout");
+ ! 				break;
+   			}
+   		}
+   		break;
+ ***************
+ *** 394,402 ****
+ --- 396,410 ----
+   }
+   
+   static const struct musb_platform_ops omap2430_ops = {
+ + 	.fifo_mode	= 4,
+ + 	.flags		= MUSB_GLUE_EP_ADDR_FLAT_MAPPING |
+ + 				MUSB_GLUE_DMA_INVENTRA,
+   	.init		= omap2430_musb_init,
+   	.exit		= omap2430_musb_exit,
+   
+ + 	.read_fifo      = musb_read_fifo,
+ + 	.write_fifo     = musb_write_fifo,
+ + 
+   	.set_mode	= omap2430_musb_set_mode,
+   	.try_idle	= omap2430_musb_try_idle,
+   
+ ***************
+ *** 404,409 ****
+ --- 412,420 ----
+   
+   	.enable		= omap2430_musb_enable,
+   	.disable	= omap2430_musb_disable,
+ + 
+ + 	.dma_controller_create = inventra_dma_controller_create,
+ + 	.dma_controller_destroy = inventra_dma_controller_destroy,
+   };
+   
+   static u64 omap2430_dmamask = DMA_BIT_MASK(32);
+ ***************
+ *** 421,432 ****
+   		goto err0;
+   	}
+   
+ ! 	musb = platform_device_alloc("musb-hdrc", -1);
+   	if (!musb) {
+   		dev_err(&pdev->dev, "failed to allocate musb device\n");
+   		goto err1;
+   	}
+   
+   	musb->dev.parent		= &pdev->dev;
+   	musb->dev.dma_mask		= &omap2430_dmamask;
+   	musb->dev.coherent_dma_mask	= omap2430_dmamask;
+ --- 432,444 ----
+   		goto err0;
+   	}
+   
+ ! 	musb = platform_device_alloc("musb-hdrc", pdev->id);
+   	if (!musb) {
+   		dev_err(&pdev->dev, "failed to allocate musb device\n");
+   		goto err1;
+   	}
+   
+ + 	ev_set_name(&pdev->dev, "musb-omap2430");
+   	musb->dev.parent		= &pdev->dev;
+   	musb->dev.dma_mask		= &omap2430_dmamask;
+   	musb->dev.coherent_dma_mask	= omap2430_dmamask;
+ ***************
+ *** 478,484 ****
+   	platform_device_del(glue->musb);
+   	platform_device_put(glue->musb);
+   	pm_runtime_put(&pdev->dev);
+ - 	pm_runtime_disable(&pdev->dev);
+   	kfree(glue);
+   
+   	return 0;
+ --- 490,495 ----
+ ***************
+ *** 491,496 ****
+ --- 502,510 ----
+   	struct omap2430_glue		*glue = dev_get_drvdata(dev);
+   	struct musb			*musb = glue_to_musb(glue);
+   
+ + 	musb->context.otg_interfsel = musb_readl(musb->mregs,
+ + 						OTG_INTERFSEL);
+ + 
+   	omap2430_low_level_exit(musb);
+   	otg_set_suspend(musb->xceiv, 1);
+   
+ ***************
+ *** 503,508 ****
+ --- 517,525 ----
+   	struct musb			*musb = glue_to_musb(glue);
+   
+   	omap2430_low_level_init(musb);
+ + 	musb_writel(musb->mregs, OTG_INTERFSEL,
+ + 					musb->context.otg_interfsel);
+ + 
+   	otg_set_suspend(musb->xceiv, 0);
+   
+   	return 0;
+ diff -crN linux-3.2.1_o/drivers/usb/musb/ti81xx.c linux-3.2.1/drivers/usb/musb/ti81xx.c
+ *** linux-3.2.1_o/drivers/usb/musb/ti81xx.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/drivers/usb/musb/ti81xx.c	2014-11-25 13:19:16.696059453 +0900
+ ***************
+ *** 0 ****
+ --- 1,1884 ----
+ + /*
+ +  * Texas Instruments TI81XX "usb platform glue layer"
+ +  *
+ +  * Copyright (c) 2008, MontaVista Software, Inc. <source@mvista.com>
+ +  *
+ +  * Based on the DaVinci "glue layer" code.
+ +  * Copyright (C) 2005-2006 by Texas Instruments
+ +  *
+ +  * This file is part of the Inventra Controller Driver for Linux.
+ +  *
+ +  * The Inventra Controller Driver for Linux is free software; you
+ +  * can redistribute it and/or modify it under the terms of the GNU
+ +  * General Public License version 2 as published by the Free Software
+ +  * Foundation.
+ +  *
+ +  * The Inventra Controller Driver for Linux is distributed in
+ +  * the hope that it will be useful, but WITHOUT ANY WARRANTY;
+ +  * without even the implied warranty of MERCHANTABILITY or
+ +  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+ +  * License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with The Inventra Controller Driver for Linux ; if not,
+ +  * write to the Free Software Foundation, Inc., 59 Temple Place,
+ +  * Suite 330, Boston, MA  02111-1307  USA
+ +  *
+ +  */
+ + 
+ + #include <linux/init.h>
+ + #include <linux/io.h>
+ + #include <linux/usb/otg.h>
+ + #include <linux/platform_device.h>
+ + #include <linux/dma-mapping.h>
+ + #include <linux/module.h>
+ + 
+ + #include "cppi41.h"
+ + #include "ti81xx.h"
+ + 
+ + #include "musb_core.h"
+ + #include "cppi41_dma.h"
+ + 
+ + #ifdef CONFIG_PM
+ + struct ti81xx_usbss_regs {
+ + 	u32	sysconfig;
+ + 
+ + 	u32	irq_en_set;
+ + 
+ + #ifdef CONFIG_USB_TI_CPPI41_DMA
+ + 	u32	irq_dma_th_tx0[4];
+ + 	u32	irq_dma_th_rx0[4];
+ + 	u32	irq_dma_th_tx1[4];
+ + 	u32	irq_dma_th_rx1[4];
+ + 	u32	irq_dma_en[2];
+ + 
+ + 	u32	irq_frame_th_tx0[4];
+ + 	u32	irq_frame_th_rx0[4];
+ + 	u32	irq_frame_th_tx1[4];
+ + 	u32	irq_frame_th_rx1[4];
+ + 	u32	irq_frame_en[2];
+ + #endif
+ + };
+ + 
+ + struct ti81xx_usb_regs {
+ + 	u32	control;
+ + 
+ + 	u32	irq_en_set[2];
+ + 
+ + #ifdef CONFIG_USB_TI_CPPI41_DMA
+ + 	u32	tx_mode;
+ + 	u32	rx_mode;
+ + 	u32	grndis_size[15];
+ + 	u32	auto_req;
+ + 	u32	teardn;
+ + 	u32	th_xdma_idle;
+ + #endif
+ + 	u32	srp_fix;
+ + 	u32	phy_utmi;
+ + 	u32	mgc_utmi_loopback;
+ + 	u32	mode;
+ + };
+ + #endif
+ + 
+ + #define BABBLE_WORKAROUND_1 0
+ + #define BABBLE_WORKAROUND_2 1
+ + #define BABBLE_WORKAROUND_3 2
+ + 
+ + #define BABBLE_WORKAROUND (BABBLE_WORKAROUND_2)
+ + 
+ + struct ti81xx_glue {
+ + 	struct device *dev;
+ + 	struct resource *mem_pa;	/* usbss memory resource */
+ + 	void *mem_va;			/* ioremapped virtual address */
+ + 	struct platform_device *musb[2];/* child musb pdevs */
+ + 	u8	irq;			/* usbss irq */
+ + 	u8	first;			/* ignore first call of resume */
+ + 
+ + #ifdef CONFIG_PM
+ + 	struct ti81xx_usbss_regs usbss_regs;
+ + 	struct ti81xx_usb_regs usb_regs[2];
+ + #endif
+ + };
+ + 
+ + static u64 musb_dmamask = DMA_BIT_MASK(32);
+ + static void *usbss_virt_base;
+ + static u8 usbss_init_done;
+ + struct musb *gmusb[2];
+ + 
+ + u8 usbid_sw_ctrl;
+ + #undef USB_TI81XX_DEBUG
+ + 
+ + #ifdef USB_TI81XX_DEBUG
+ + #define	dprintk(x, ...) printk(x, ## __VA_ARGS__)
+ + #else
+ + #define dprintk(x, ...)
+ + #endif
+ + 
+ + #ifdef CONFIG_USB_TI_CPPI41_DMA
+ + static irqreturn_t cppi41dma_Interrupt(int irq, void *hci);
+ + static u8 cppi41_init_done;
+ + static void *cppi41_dma_base;
+ + #define CPPI41_ADDR(offs) ((void *)((u32)cppi41_dma_base + (offs - 0x2000)))
+ + #endif
+ + 
+ + extern void omap_ctrl_writel(u32 val, u16 offset);
+ + extern u32 omap_ctrl_readl(u16 offset);
+ + 
+ + static inline u32 usbss_read(u32 offset)
+ + {
+ + 	if (!usbss_init_done)
+ + 		return 0;
+ + 	return readl(usbss_virt_base + offset);
+ + }
+ + 
+ + static inline void usbss_write(u32 offset, u32 data)
+ + {
+ + 	if (!usbss_init_done)
+ + 		return ;
+ + 	writel(data, usbss_virt_base + offset);
+ + }
+ + 
+ + static void usbotg_ss_init(void)
+ + {
+ + 	if (!usbss_init_done) {
+ + 		usbss_init_done = 1;
+ + 
+ + 		/* clear any USBSS interrupts */
+ + 		usbss_write(USBSS_IRQ_EOI, 0);
+ + 		usbss_write(USBSS_IRQ_STATUS, usbss_read(USBSS_IRQ_STATUS));
+ + 	}
+ + }
+ + static void usbotg_ss_uninit(void)
+ + {
+ + 	if (usbss_init_done) {
+ + 		usbss_init_done = 0;
+ + 		usbss_virt_base = 0;
+ + 	}
+ + }
+ + void set_frame_threshold(struct musb *musb, u8 is_tx, u8 epnum, u8 value, u8 en_intr)
+ + {
+ + 	u32     base, reg_val, frame_intr = 0, frame_base = 0;
+ + 	u32     offs = epnum/4*4;
+ + 	u8      indx = (epnum % 4) * 8;
+ + 
+ + 	if (is_tx)
+ + 		base = musb->id ? USBSS_IRQ_FRAME_THRESHOLD_TX1 :
+ + 				USBSS_IRQ_FRAME_THRESHOLD_TX0;
+ + 	else
+ + 		base = musb->id ? USBSS_IRQ_FRAME_THRESHOLD_RX1 :
+ + 				USBSS_IRQ_FRAME_THRESHOLD_RX0;
+ + 
+ + 	reg_val = usbss_read(base + offs);
+ + 	reg_val &= ~(0xFF << indx);
+ + 	reg_val |= (value << indx);
+ + 	usbss_write(base + offs, reg_val);
+ + 
+ + 	if (en_intr) {
+ + 		frame_base = musb->id ? USBSS_IRQ_FRAME_ENABLE_1 :
+ + 			USBSS_IRQ_FRAME_ENABLE_0;
+ + 		frame_intr = musb->id ? usbss_read(USBSS_IRQ_FRAME_ENABLE_0) :
+ + 			usbss_read(USBSS_IRQ_FRAME_ENABLE_1);
+ + 		frame_intr |= is_tx ? (1 << epnum) : (1 << (16 + epnum));
+ + 		usbss_write(frame_base, frame_intr);
+ + 		dev_dbg(musb->controller, "%s: framebase=%x, frame_intr=%x\n",
+ + 			is_tx ? "tx" : "rx", frame_base, frame_intr);
+ + 	}
+ + }
+ + 
+ + void set_dma_threshold(struct musb *musb, u8 is_tx, u8 epnum, u8 value)
+ + {
+ + 	u32     base, reg_val;
+ + 	u32     offs = epnum/4*4;
+ + 	u8      indx = (epnum % 4) * 8;
+ + 
+ + 	if (musb->id == 0)
+ + 		base = is_tx ? USBSS_IRQ_DMA_THRESHOLD_TX0 :
+ + 				USBSS_IRQ_DMA_THRESHOLD_RX0;
+ + 	else
+ + 		base = is_tx ? USBSS_IRQ_DMA_THRESHOLD_TX1 :
+ + 				USBSS_IRQ_DMA_THRESHOLD_RX1;
+ + 
+ + 	reg_val = usbss_read(base + offs);
+ + 	reg_val &= ~(0xFF << indx);
+ + 	reg_val |= (value << indx);
+ + 	dev_dbg(musb->controller, "base=%x, offs=%x, indx=%d, reg_val = (%x)%x\n",
+ + 		base, offs, indx, reg_val, usbss_read(base + offs));
+ + 	usbss_write(base + offs, reg_val);
+ + }
+ + 
+ + /* ti81xx specific read/write functions */
+ + u16 ti81xx_musb_readw(const void __iomem *addr, unsigned offset)
+ + {
+ + 	u32 tmp;
+ + 	u16 val;
+ + 
+ + 	tmp = readl(addr + (offset & ~3));
+ + 
+ + 	switch (offset & 0x3) {
+ + 	case 0:
+ + 		val = (tmp & 0xffff);
+ + 		break;
+ + 	case 1:
+ + 		val = (tmp >> 8) & 0xffff;
+ + 		break;
+ + 	case 2:
+ + 	case 3:
+ + 	default:
+ + 		val = (tmp >> 16) & 0xffff;
+ + 		break;
+ + 	}
+ + 	return val;
+ + }
+ + 
+ + void ti81xx_musb_writew(void __iomem *addr, unsigned offset, u16 data)
+ + {
+ + 	__raw_writew(data, addr + offset);
+ + }
+ + 
+ + u8 ti81xx_musb_readb(const void __iomem *addr, unsigned offset)
+ + {
+ + 	u32 tmp;
+ + 	u8 val;
+ + 
+ + 	tmp = readl(addr + (offset & ~3));
+ + 
+ + 	switch (offset & 0x3) {
+ + 	case 0:
+ + 		val = tmp & 0xff;
+ + 		break;
+ + 	case 1:
+ + 		val = (tmp >> 8);
+ + 		break;
+ + 	case 2:
+ + 		val = (tmp >> 16);
+ + 		break;
+ + 	case 3:
+ + 	default:
+ + 		val = (tmp >> 24);
+ + 		break;
+ + 	}
+ + 	return val;
+ + }
+ + void ti81xx_musb_writeb(void __iomem *addr, unsigned offset, u8 data)
+ + {
+ + 	__raw_writeb(data, addr + offset);
+ + }
+ + 
+ + #ifdef CONFIG_USB_TI_CPPI41_DMA
+ + /*
+ +  * CPPI 4.1 resources used for USB OTG controller module:
+ +  *
+ +  tx/rx completion queues for usb0 */
+ + static u16 tx_comp_q[] = {93, 94, 95, 96, 97,
+ + 				98, 99, 100, 101, 102,
+ + 				103, 104, 105, 106, 107 };
+ + 
+ + static u16 rx_comp_q[] = {109, 110, 111, 112, 113,
+ + 				114, 115, 116, 117, 118,
+ + 				119, 120, 121, 122, 123 };
+ + 
+ + /* tx/rx completion queues for usb1 */
+ + static u16 tx_comp_q1[] = {125, 126, 127, 128, 129,
+ + 				 130, 131, 132, 133, 134,
+ + 				 135, 136, 137, 138, 139 };
+ + 
+ + static u16 rx_comp_q1[] = {141, 142, 143, 144, 145,
+ + 				 146, 147, 148, 149, 150,
+ + 				 151, 152, 153, 154, 155 };
+ + 
+ + /* Fair scheduling */
+ + u32 dma_sched_table[] = {
+ + 	0x81018000, 0x83038202, 0x85058404, 0x87078606,
+ + 	0x89098808, 0x8b0b8a0a, 0x8d0d8c0c, 0x8f0f8e0e,
+ + 	0x91119010, 0x93139212, 0x95159414, 0x97179616,
+ + 	0x99199818, 0x9b1b9a1a, 0x9d1d9c1c, 0x00009e1e,
+ + };
+ + 
+ + /* cppi41 dma tx channel info */
+ + static const struct cppi41_tx_ch tx_ch_info[] = {
+ + 	[0] = {
+ + 		.port_num	= 1,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 32} , {0, 33} }
+ + 	},
+ + 	[1] = {
+ + 		.port_num	= 2,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 34} , {0, 35} }
+ + 	},
+ + 	[2] = {
+ + 		.port_num	= 3,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 36} , {0, 37} }
+ + 	},
+ + 	[3] = {
+ + 		.port_num	= 4,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 38} , {0, 39} }
+ + 	},
+ + 	[4] = {
+ + 		.port_num	= 5,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 40} , {0, 41} }
+ + 	},
+ + 	[5] = {
+ + 		.port_num	= 6,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 42} , {0, 43} }
+ + 	},
+ + 	[6] = {
+ + 		.port_num	= 7,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 44} , {0, 45} }
+ + 	},
+ + 	[7] = {
+ + 		.port_num	= 8,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 46} , {0, 47} }
+ + 	},
+ + 	[8] = {
+ + 		.port_num	= 9,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 48} , {0, 49} }
+ + 	},
+ + 	[9] = {
+ + 		.port_num	= 10,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 50} , {0, 51} }
+ + 	},
+ + 	[10] = {
+ + 		.port_num	= 11,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 52} , {0, 53} }
+ + 	},
+ + 	[11] = {
+ + 		.port_num	= 12,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 54} , {0, 55} }
+ + 	},
+ + 	[12] = {
+ + 		.port_num	= 13,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 56} , {0, 57} }
+ + 	},
+ + 	[13] = {
+ + 		.port_num	= 14,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 58} , {0, 59} }
+ + 	},
+ + 	[14] = {
+ + 		.port_num	= 15,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 60} , {0, 61} }
+ + 	},
+ + 	[15] = {
+ + 		.port_num	= 1,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 62} , {0, 63} }
+ + 	},
+ + 	[16] = {
+ + 		.port_num	= 2,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 64} , {0, 65} }
+ + 	},
+ + 	[17] = {
+ + 		.port_num	= 3,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 66} , {0, 67} }
+ + 	},
+ + 	[18] = {
+ + 		.port_num	= 4,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 68} , {0, 69} }
+ + 	},
+ + 	[19] = {
+ + 		.port_num	= 5,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 70} , {0, 71} }
+ + 	},
+ + 	[20] = {
+ + 		.port_num	= 6,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 72} , {0, 73} }
+ + 	},
+ + 	[21] = {
+ + 		.port_num	= 7,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 74} , {0, 75} }
+ + 	},
+ + 	[22] = {
+ + 		.port_num	= 8,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 76} , {0, 77} }
+ + 	},
+ + 	[23] = {
+ + 		.port_num	= 9,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 78} , {0, 79} }
+ + 	},
+ + 	[24] = {
+ + 		.port_num	= 10,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 80} , {0, 81} }
+ + 	},
+ + 	[25] = {
+ + 		.port_num	= 11,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 82} , {0, 83} }
+ + 	},
+ + 	[26] = {
+ + 		.port_num	= 12,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 84} , {0, 85} }
+ + 	},
+ + 	[27] = {
+ + 		.port_num	= 13,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 86} , {0, 87} }
+ + 	},
+ + 	[28] = {
+ + 		.port_num	= 14,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 88} , {0, 89} }
+ + 	},
+ + 	[29] = {
+ + 		.port_num	= 15,
+ + 		.num_tx_queue	= 2,
+ + 		.tx_queue	= { {0, 90} , {0, 91} }
+ + 	}
+ + };
+ + 
+ + /* Queues 0 to 66 are pre-assigned, others are spare */
+ + static const u32 assigned_queues[] = {	0xffffffff, /* queue 0..31 */
+ + 					0xffffffff, /* queue 32..63 */
+ + 					0xffffffff, /* queue 64..95 */
+ + 					0xffffffff, /* queue 96..127 */
+ + 					0x0fffffff  /* queue 128..155 */
+ + 					};
+ + 
+ + int __devinit cppi41_init(u8 id, u8 irq, int num_instances)
+ + {
+ + 	struct usb_cppi41_info *cppi_info = &usb_cppi41_info[id];
+ + 	u16 numch, blknum, order;
+ + 	u32 i;
+ + 
+ + 	/* init cppi info structure  */
+ + 	cppi_info->dma_block = 0;
+ + 	for (i = 0 ; i < USB_CPPI41_NUM_CH ; i++)
+ + 		cppi_info->ep_dma_ch[i] = i + (15 * id);
+ + 
+ + 	cppi_info->q_mgr = 0;
+ + 	cppi_info->num_tx_comp_q = 15;
+ + 	cppi_info->num_rx_comp_q = 15;
+ + 	cppi_info->tx_comp_q = id ? tx_comp_q1 : tx_comp_q;
+ + 	cppi_info->rx_comp_q = id ? rx_comp_q1 : rx_comp_q;
+ + 	cppi_info->bd_intr_ctrl = 1;
+ + 	cppi_info->version = usbss_read(USBSS_REVISION);
+ + 
+ + 	if (cppi41_init_done)
+ + 		return 0;
+ + 
+ + 	blknum = cppi_info->dma_block;
+ + 
+ + 	/* Queue manager information */
+ + 	cppi41_queue_mgr[0].num_queue = 159;
+ + 	cppi41_queue_mgr[0].queue_types = CPPI41_FREE_DESC_BUF_QUEUE |
+ + 						CPPI41_UNASSIGNED_QUEUE;
+ + 	cppi41_queue_mgr[0].base_fdbq_num = 0;
+ + 	cppi41_queue_mgr[0].assigned = assigned_queues;
+ + 
+ + 	/* init DMA block */
+ + 	cppi41_dma_block[0].num_tx_ch = 30;
+ + 	cppi41_dma_block[0].num_rx_ch = 30;
+ + 	cppi41_dma_block[0].tx_ch_info = tx_ch_info;
+ + 
+ + 	/* initilize cppi41 dma & Qmgr address */
+ + 	cppi41_dma_base = ioremap(TI81XX_USB_CPPIDMA_BASE,
+ + 					TI81XX_USB_CPPIDMA_LEN);
+ + 
+ + 	cppi41_queue_mgr[0].q_mgr_rgn_base = CPPI41_ADDR(QMGR_RGN_OFFS);
+ + 	cppi41_queue_mgr[0].desc_mem_rgn_base = CPPI41_ADDR(QMRG_DESCRGN_OFFS);
+ + 	cppi41_queue_mgr[0].q_mgmt_rgn_base = CPPI41_ADDR(QMGR_REG_OFFS);
+ + 	cppi41_queue_mgr[0].q_stat_rgn_base = CPPI41_ADDR(QMGR_STAT_OFFS);
+ + 	cppi41_dma_block[0].global_ctrl_base = CPPI41_ADDR(DMA_GLBCTRL_OFFS);
+ + 	cppi41_dma_block[0].ch_ctrl_stat_base = CPPI41_ADDR(DMA_CHCTRL_OFFS);
+ + 	cppi41_dma_block[0].sched_ctrl_base = CPPI41_ADDR(DMA_SCHED_OFFS);
+ + 	cppi41_dma_block[0].sched_table_base = CPPI41_ADDR(DMA_SCHEDTBL_OFFS);
+ + 
+ + 	/* Initialize for Linking RAM region 0 alone */
+ + 	cppi41_queue_mgr_init(cppi_info->q_mgr, 0, 0x3fff);
+ + 
+ + 	numch =  USB_CPPI41_NUM_CH * 2 * num_instances;
+ + 	cppi41_dma_block[0].num_max_ch = numch;
+ + 
+ + 	order = get_count_order(numch);
+ + 
+ + 	/* TODO: check two teardown desc per channel (5 or 7 ?)*/
+ + 	if (order < 5)
+ + 		order = 5;
+ + 
+ + 	cppi41_dma_block_init(blknum, cppi_info->q_mgr, order,
+ + 			dma_sched_table, numch);
+ + 
+ + 	/* attach to the IRQ */
+ + 	if (request_irq(irq, cppi41dma_Interrupt, 0, "cppi41_dma", 0))
+ + 		printk(KERN_INFO "request_irq %d failed!\n", irq);
+ + 	else
+ + 		printk(KERN_INFO "registerd cppi-dma Intr @ IRQ %d\n", irq);
+ + 
+ + 	cppi41_init_done = 1;
+ + 
+ + 	printk(KERN_INFO "Cppi41 Init Done Qmgr-base(%p) dma-base(%p)\n",
+ + 		cppi41_queue_mgr[0].q_mgr_rgn_base,
+ + 		cppi41_dma_block[0].global_ctrl_base);
+ + 
+ + 	/* enable all usbss the interrupts */
+ + 	usbss_write(USBSS_IRQ_EOI, 0);
+ + 	usbss_write(USBSS_IRQ_ENABLE_SET, USBSS_INTR_FLAGS);
+ + 	usbss_write(USBSS_IRQ_DMA_ENABLE_0, 0xFFFeFFFe);
+ + 
+ + 	printk(KERN_INFO "Cppi41 Init Done\n");
+ + 
+ + 	return 0;
+ + }
+ + 
+ + void cppi41_free(void)
+ + {
+ + 	u32 numch, blknum, order;
+ + 	struct usb_cppi41_info *cppi_info = &usb_cppi41_info[0];
+ + 
+ + 	if (!cppi41_init_done)
+ + 		return ;
+ + 
+ + 	numch = cppi41_dma_block[0].num_max_ch;
+ + 	order = get_count_order(numch);
+ + 	blknum = cppi_info->dma_block;
+ + 
+ + 	cppi41_dma_block_uninit(blknum, cppi_info->q_mgr, order,
+ + 			dma_sched_table, numch);
+ + 	cppi41_queue_mgr_uninit(cppi_info->q_mgr);
+ + 
+ + 	iounmap(cppi41_dma_base);
+ + 	cppi41_dma_base = 0;
+ + 	cppi41_init_done = 0;
+ + }
+ + 
+ + int cppi41_disable_sched_rx(void)
+ + {
+ + 	cppi41_dma_sched_tbl_init(0, 0, dma_sched_table, 30);
+ + 	return 0;
+ + }
+ + 
+ + int cppi41_enable_sched_rx(void)
+ + {
+ + 	cppi41_dma_sched_tbl_init(0, 0, dma_sched_table, 30);
+ + 	return 0;
+ + }
+ + 
+ + /*
+ +  * Because we don't set CTRL.UINT, it's "important" to:
+ +  *	- not read/write INTRUSB/INTRUSBE (except during
+ +  *	  initial setup, as a workaround);
+ +  *	- use INTSET/INTCLR instead.
+ +  */
+ + 
+ + void txfifoempty_intr_enable(struct musb *musb, u8 ep_num)
+ + {
+ + 	void __iomem *reg_base = musb->ctrl_base;
+ + 	u32 coremask;
+ + 
+ + 	if (musb->txfifo_intr_enable) {
+ + 		coremask = musb_readl(reg_base, USB_CORE_INTR_SET_REG);
+ + 		coremask |= (1 << (ep_num + 16));
+ + 		musb_writel(reg_base, USB_CORE_INTR_SET_REG, coremask);
+ + 		dev_dbg(musb->controller, "enable txF intr ep%d coremask %x\n",
+ + 			ep_num, coremask);
+ + 	}
+ + }
+ + 
+ + void txfifoempty_intr_disable(struct musb *musb, u8 ep_num)
+ + {
+ + 	void __iomem *reg_base = musb->ctrl_base;
+ + 	u32 coremask;
+ + 
+ + 	if (musb->txfifo_intr_enable) {
+ + 		coremask = (1 << (ep_num + 16));
+ + 		musb_writel(reg_base, USB_CORE_INTR_CLEAR_REG, coremask);
+ + 	}
+ + }
+ + 
+ + #endif /* CONFIG_USB_TI_CPPI41_DMA */
+ + 
+ + void ti81xx_musb_enable_sof(struct musb *musb)
+ + {
+ + 	void __iomem *reg_base = musb->ctrl_base;
+ + 
+ + 	musb->sof_enabled = 1;
+ + 	musb_writeb(musb->mregs, MUSB_INTRUSBE, MUSB_INTR_SOF |
+ + 		musb_readb(musb->mregs, MUSB_INTRUSBE));
+ + 	musb_writel(reg_base, USB_CORE_INTR_SET_REG, MUSB_INTR_SOF |
+ + 		musb_readl(reg_base, USB_CORE_INTR_SET_REG));
+ + }
+ + 
+ + void ti81xx_musb_disable_sof(struct musb *musb)
+ + {
+ + 	void __iomem *reg_base = musb->ctrl_base;
+ + 	u8 intrusb;
+ + 
+ + 	intrusb = musb_readb(musb->mregs, MUSB_INTRUSBE);
+ + 	intrusb &= ~MUSB_INTR_SOF;
+ + 	musb_writeb(musb->mregs, MUSB_INTRUSBE, intrusb);
+ + 	musb_writel(reg_base, USB_CORE_INTR_CLEAR_REG, MUSB_INTR_SOF);
+ + 	musb->sof_enabled = 0;
+ + }
+ + 
+ + /**
+ +  * ti81xx_musb_enable - enable interrupts
+ +  */
+ + void ti81xx_musb_enable(struct musb *musb)
+ + {
+ + 	void __iomem *reg_base = musb->ctrl_base;
+ + 	u32 epmask, coremask;
+ + 
+ + 	/* Workaround: setup IRQs through both register sets. */
+ + 	epmask = ((musb->epmask & USB_TX_EP_MASK) << USB_INTR_TX_SHIFT) |
+ + 	       ((musb->epmask & USB_RX_EP_MASK) << USB_INTR_RX_SHIFT);
+ + 	coremask = (0x01ff << USB_INTR_USB_SHIFT);
+ + 
+ + 	coremask &= ~MUSB_INTR_SOF;
+ + 
+ + 	musb_writel(reg_base, USB_EP_INTR_SET_REG, epmask);
+ + 	musb_writel(reg_base, USB_CORE_INTR_SET_REG, coremask);
+ + 	/* Force the DRVVBUS IRQ so we can start polling for ID change. */
+ + 	if (is_otg_enabled(musb))
+ + 		musb_writel(reg_base, USB_CORE_INTR_SET_REG,
+ + 			    USB_INTR_DRVVBUS << USB_INTR_USB_SHIFT);
+ + }
+ + 
+ + /**
+ +  * ti81xx_musb_disable - disable HDRC and flush interrupts
+ +  */
+ + void ti81xx_musb_disable(struct musb *musb)
+ + {
+ + 	void __iomem *reg_base = musb->ctrl_base;
+ + 
+ + 	musb_writel(reg_base, USB_CORE_INTR_CLEAR_REG, USB_INTR_USB_MASK);
+ + 	musb_writel(reg_base, USB_EP_INTR_CLEAR_REG,
+ + 			 USB_TX_INTR_MASK | USB_RX_INTR_MASK);
+ + 	musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
+ + 	musb_writel(reg_base, USB_IRQ_EOI, 0);
+ + }
+ + 
+ + #define	POLL_SECONDS	2
+ + 
+ + static void otg_timer(unsigned long _musb)
+ + {
+ + 	struct musb		*musb = (void *)_musb;
+ + 	void __iomem		*mregs = musb->mregs;
+ + 	u8			devctl;
+ + 	unsigned long		flags;
+ + 
+ + 	/* We poll because DaVinci's won't expose several OTG-critical
+ + 	* status change events (from the transceiver) otherwise.
+ + 	 */
+ + 	devctl = musb_readb(mregs, MUSB_DEVCTL);
+ + 	dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
+ + 			otg_state_string(musb->xceiv->state));
+ + 
+ + 	spin_lock_irqsave(&musb->lock, flags);
+ + 	switch (musb->xceiv->state) {
+ + 	case OTG_STATE_A_WAIT_BCON:
+ + 		devctl &= ~MUSB_DEVCTL_SESSION;
+ + 		musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
+ + 
+ + 		devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
+ + 		if (devctl & MUSB_DEVCTL_HM) {
+ + 			musb->xceiv->state = OTG_STATE_A_IDLE;
+ + 			MUSB_HST_MODE(musb);
+ + 		} else {
+ + 			musb->xceiv->state = OTG_STATE_B_IDLE;
+ + 			MUSB_DEV_MODE(musb);
+ + 			mod_timer(&musb->otg_workaround,
+ + 					jiffies + POLL_SECONDS * HZ);
+ + 		}
+ + 		break;
+ + 	case OTG_STATE_A_WAIT_VFALL:
+ + 		/*
+ + 		 * Wait till VBUS falls below SessionEnd (~0.2 V); the 1.3
+ + 		 * RTL seems to mis-handle session "start" otherwise (or in
+ + 		 * our case "recover"), in routine "VBUS was valid by the time
+ + 		 * VBUSERR got reported during enumeration" cases.
+ + 		 */
+ + 		if (devctl & MUSB_DEVCTL_VBUS) {
+ + 			mod_timer(&musb->otg_workaround,
+ + 					jiffies + POLL_SECONDS * HZ);
+ + 			break;
+ + 		}
+ + 		musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
+ + 		musb_writel(musb->ctrl_base, USB_CORE_INTR_SET_REG,
+ + 			    MUSB_INTR_VBUSERROR << USB_INTR_USB_SHIFT);
+ + 		break;
+ + 	case OTG_STATE_B_IDLE:
+ + 		if (!is_peripheral_enabled(musb))
+ + 			break;
+ + 
+ + 		/*
+ + 		 * There's no ID-changed IRQ, so we have no good way to tell
+ + 		 * when to switch to the A-Default state machine (by setting
+ + 		 * the DEVCTL.SESSION flag).
+ + 		 *
+ + 		 * Workaround:  whenever we're in B_IDLE, try setting the
+ + 		 * session flag every few seconds.  If it works, ID was
+ + 		 * grounded and we're now in the A-Default state machine.
+ + 		 *
+ + 		 * NOTE: setting the session flag is _supposed_ to trigger
+ + 		 * SRP but clearly it doesn't.
+ + 		 */
+ + 		devctl = musb_readb(mregs, MUSB_DEVCTL);
+ + 		if (devctl & MUSB_DEVCTL_HM) {
+ + 			musb->xceiv->state = OTG_STATE_A_IDLE;
+ + 			break;
+ + 		}
+ + 
+ + 		/* don't toggle SESSION flag if VBUS presents - connected
+ + 		 * to Host already
+ + 		 */
+ + 		if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
+ + 			break;
+ + 
+ + 		if ((devctl & MUSB_DEVCTL_SESSION) &&
+ + 				!(devctl & MUSB_DEVCTL_BDEVICE))
+ + 			devctl &= ~MUSB_DEVCTL_SESSION;
+ + 		else
+ + 			devctl |= MUSB_DEVCTL_SESSION;
+ + 
+ + 		mod_timer(&musb->otg_workaround,
+ + 				jiffies + POLL_SECONDS * HZ);
+ + 		musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
+ + 		break;
+ + 	default:
+ + 		break;
+ + 	}
+ + 	spin_unlock_irqrestore(&musb->lock, flags);
+ + }
+ + 
+ + void ti81xx_musb_try_idle(struct musb *musb, unsigned long timeout)
+ + {
+ + 	if (!is_otg_enabled(musb))
+ + 		return;
+ + 
+ + 	if (timeout == 0)
+ + 		timeout = jiffies + msecs_to_jiffies(3);
+ + 
+ + 	/* Never idle if active, or when VBUS timeout is not set as host */
+ + 	if (musb->is_active || (musb->a_wait_bcon == 0 &&
+ + 				musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
+ + 		dev_dbg(musb->controller, "%s active, deleting timer\n",
+ + 			otg_state_string(musb->xceiv->state));
+ + 		del_timer(&musb->otg_workaround);
+ + 		musb->last_timer = jiffies;
+ + 		return;
+ + 	}
+ + 
+ + 	if (time_after(musb->last_timer, timeout) &&
+ + 					timer_pending(&musb->otg_workaround)) {
+ + 		dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
+ + 		return;
+ + 	}
+ + 	musb->last_timer = timeout;
+ + 
+ + 	dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
+ + 	    otg_state_string(musb->xceiv->state),
+ + 		jiffies_to_msecs(timeout - jiffies));
+ + 	mod_timer(&musb->otg_workaround, timeout);
+ + }
+ + 
+ + #ifdef CONFIG_USB_TI_CPPI41_DMA
+ + static irqreturn_t cppi41dma_Interrupt(int irq, void *hci)
+ + {
+ + 	u32 intr_status;
+ + 	irqreturn_t ret = IRQ_NONE;
+ + 	u32 q_cmpl_status_0, q_cmpl_status_1, q_cmpl_status_2;
+ + 	u32 usb0_tx_intr, usb0_rx_intr;
+ + 	u32 usb1_tx_intr, usb1_rx_intr;
+ + 	void *q_mgr_base = cppi41_queue_mgr[0].q_mgr_rgn_base;
+ + 	unsigned long flags;
+ + 
+ + 	/*
+ + 	 * CPPI 4.1 interrupts share the same IRQ and the EOI register but
+ + 	 * don't get reflected in the interrupt source/mask registers.
+ + 	 */
+ + 	/*
+ + 	 * Check for the interrupts from Tx/Rx completion queues; they
+ + 	 * are level-triggered and will stay asserted until the queues
+ + 	 * are emptied.  We're using the queue pending register 0 as a
+ + 	 * substitute for the interrupt status register and reading it
+ + 	 * directly for speed.
+ + 	 */
+ + 	intr_status = usbss_read(USBSS_IRQ_STATUS);
+ + 
+ + 	if (intr_status)
+ + 		usbss_write(USBSS_IRQ_STATUS, intr_status);
+ + 	else
+ + 		printk(KERN_DEBUG "spurious usbss intr\n");
+ + 
+ + 	q_cmpl_status_0 = musb_readl(q_mgr_base, CPPI41_QSTATUS_REG2);
+ + 	q_cmpl_status_1 = musb_readl(q_mgr_base, CPPI41_QSTATUS_REG3);
+ + 	q_cmpl_status_2 = musb_readl(q_mgr_base, CPPI41_QSTATUS_REG4);
+ + 
+ + 	/* USB0 tx/rx completion */
+ + 	/* usb0 tx completion interrupt for ep1..15 */
+ + 	usb0_tx_intr = (q_cmpl_status_0 >> 29) |
+ + 			((q_cmpl_status_1 & 0xFFF) << 3);
+ + 	usb0_rx_intr = ((q_cmpl_status_1 & 0x07FFe000) >> 13);
+ + 
+ + 	usb1_tx_intr = (q_cmpl_status_1 >> 29) |
+ + 			((q_cmpl_status_2 & 0xFFF) << 3);
+ + 	usb1_rx_intr = ((q_cmpl_status_2 & 0x0fffe000) >> 13);
+ + 
+ + 	/* get proper musb handle based usb0/usb1 ctrl-id */
+ + 
+ + 	if (gmusb[0] && (usb0_tx_intr || usb0_rx_intr)) {
+ + 		dev_dbg(gmusb[0]->controller, "CPPI 4.1 IRQ: Tx %x, Rx %x\n",
+ + 			usb0_tx_intr, usb0_rx_intr);
+ + 		spin_lock_irqsave(&gmusb[0]->lock, flags);
+ + 		cppi41_completion(gmusb[0], usb0_rx_intr,
+ + 					usb0_tx_intr);
+ + 		spin_unlock_irqrestore(&gmusb[0]->lock, flags);
+ + 		ret = IRQ_HANDLED;
+ + 	}
+ + 
+ + 	if (gmusb[1] && (usb1_rx_intr || usb1_tx_intr)) {
+ + 		dev_dbg(gmusb[1]->controller, "CPPI 4.1 IRQ: Tx %x, Rx %x\n",
+ + 			usb1_tx_intr, usb1_rx_intr);
+ + 		spin_lock_irqsave(&gmusb[1]->lock, flags);
+ + 		cppi41_completion(gmusb[1], usb1_rx_intr,
+ + 			usb1_tx_intr);
+ + 		spin_unlock_irqrestore(&gmusb[1]->lock, flags);
+ + 		ret = IRQ_HANDLED;
+ + 	}
+ + 	usbss_write(USBSS_IRQ_EOI, 0);
+ + 
+ + 	return ret;
+ + }
+ + #endif
+ + 
+ + int musb_simulate_babble(struct musb *musb)
+ + {
+ + 	void __iomem *reg_base = musb->ctrl_base;
+ + 	void __iomem *mbase = musb->mregs;
+ + 	struct device *dev = musb->controller;
+ + 	struct musb_hdrc_platform_data *plat = dev->platform_data;
+ + 	struct omap_musb_board_data *data = plat->board_data;
+ + 	u8 reg;
+ + 
+ + 	/* during babble condition musb controller
+ + 	 * remove the session
+ + 	 */
+ + 	if (!data->babble_ctrl) {
+ + 		reg = musb_readb(mbase, MUSB_DEVCTL);
+ + 		reg &= ~MUSB_DEVCTL_SESSION;
+ + 		musb_writeb(mbase, MUSB_DEVCTL, reg);
+ + 		mdelay(100);
+ + 	}
+ + 
+ + 	/* generate s/w babble interrupt */
+ + 	musb_writel(reg_base, USB_IRQ_STATUS_RAW_1, MUSB_INTR_BABBLE);
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(musb_simulate_babble);
+ + 
+ + void musb_babble_workaround(struct musb *musb)
+ + {
+ + 	void __iomem *reg_base = musb->ctrl_base;
+ + 	struct device *dev = musb->controller;
+ + 	struct musb_hdrc_platform_data *plat = dev->platform_data;
+ + 	struct omap_musb_board_data *data = plat->board_data;
+ + 
+ + 	ERR("Babble: devtcl(%x)Restarting musb....\n",
+ + 			 musb_readb(musb->mregs, MUSB_DEVCTL));
+ + 
+ + 	/* Reset the controller */
+ + 	musb_writel(reg_base, USB_CTRL_REG, USB_SOFT_RESET_MASK);
+ + 	while ((musb_readl(reg_base, USB_CTRL_REG) & 0x1))
+ + 		cpu_relax();
+ + 
+ + 	/* Shutdown the on-chip PHY and its PLL. */
+ + 	if (data->set_phy_power)
+ + 		data->set_phy_power(musb->id, 0, false);
+ + 	udelay(100);
+ + 
+ + 	musb_platform_set_mode(musb, MUSB_HOST);
+ + 	udelay(100);
+ + 
+ + 	/* enable the usbphy */
+ + 	if (data->set_phy_power)
+ + 		data->set_phy_power(musb->id, 1, false);
+ + 	mdelay(100);
+ + 
+ + 	/* re-setup the endpoint fifo addresses */
+ + 	if (musb->ops->reinit)
+ + 		musb->ops->reinit(plat->config->multipoint, musb);
+ + 	musb_start(musb);
+ + }
+ + 
+ + void musb_babble_hwfix(struct musb *musb)
+ + {
+ + 	int timeout = 10;
+ + 	u8 temp, session_restart = 0;
+ + 
+ + 	/* wait for 320 clock cycles and check whether still babble
+ + 	 * present on the bus */
+ + 	udelay(6);
+ + 
+ + 	temp = musb_readb(musb->mregs, MUSB_MISC);
+ + 	dev_dbg(musb->controller, "babble: MUSB MISC value %x\n", temp);
+ + 
+ + 	/* check line monitor flag to check whether babble is
+ + 	 * due to noise
+ + 	 */
+ + 	dev_dbg(musb->controller, "STUCK_J is %s\n",
+ + 		temp & MUSB_MISC_STUCK_J ? "set" : "reset");
+ + 
+ + 	if (temp & MUSB_MISC_STUCK_J) {
+ + 		/* babble is due to noise, then set transmit idle (d7 bit)
+ + 		 * to resume normal operation
+ + 		 */
+ + 		temp = musb_readb(musb->mregs, MUSB_MISC);
+ + 		temp |= MUSB_MISC_FORCE_TXIDLE;
+ + 		musb_writeb(musb->mregs, MUSB_MISC, temp);
+ + 
+ + 		/* wait till line monitor flag cleared */
+ + 		dev_dbg(musb->controller, "Set TXIDLE, wait J to clear\n");
+ + 		do {
+ + 			temp = musb_readb(musb->mregs, MUSB_MISC);
+ + 			udelay(1);
+ + 		} while ((temp & MUSB_MISC_STUCK_J) && timeout--);
+ + 
+ + 		/* check whether stuck_at_j bit cleared */
+ + 		temp = musb_readb(musb->mregs, MUSB_MISC);
+ + 		if (temp & MUSB_MISC_STUCK_J) {
+ + 			/* real babble condition is occured
+ + 			 * restart the controller to start the
+ + 			 * session again
+ + 			 */
+ + 			dev_dbg(musb->controller, "J not cleared, misc (%x)\n",
+ + 				temp);
+ + 
+ + 			session_restart = 1;
+ + 		} else {
+ + 			pr_info("babble: controller shall resume normal\n");
+ + 			/* check controller resumes normal operation
+ + 			 * by checking sof occurs for few frames
+ + 			 */
+ + 			musb->sof_cnt = 2;
+ + 			ti81xx_musb_enable_sof(musb);
+ + 			udelay(280);
+ + 			if (musb->sof_cnt) {
+ + 				pr_info("babble: controller cannot resume\n");
+ + 				session_restart = 1;
+ + 			} else
+ + 				pr_info("babble: controller resumed normal\n");
+ + 			ti81xx_musb_disable_sof(musb);
+ + 		}
+ + 	} else
+ + 		session_restart = 1;
+ + 
+ + 	if (session_restart) {
+ + 		unsigned long flags;
+ + 
+ + 		dev_dbg(musb->controller, "babble: restart controller\n");
+ + 		temp = musb_readb(musb->mregs, MUSB_DEVCTL);
+ + 		temp &= ~MUSB_DEVCTL_SESSION;
+ + 		musb_writeb(musb->mregs, MUSB_DEVCTL, temp);
+ + 
+ + 		 /* inform stack about disconnect of root hub */
+ + 		spin_lock_irqsave(&musb->lock, flags);
+ + 		musb->int_usb = MUSB_INTR_DISCONNECT;
+ + 		musb_interrupt(musb);
+ + 		spin_unlock_irqrestore(&musb->lock, flags);
+ + 
+ + 		/* restart the session */
+ + 		musb_babble_workaround(musb);
+ + 	}
+ + }
+ + 
+ + static void evm_deferred_musb_restart(struct work_struct *work)
+ + {
+ + 	struct musb *musb =
+ + 		container_of(work, struct musb, work);
+ + 
+ + 	if (musb->enable_babble_work == BABBLE_WORKAROUND_3) {
+ + 		/* hw will not end the session  */
+ + 		musb_babble_hwfix(musb);
+ + 	} else {
+ + 		ERR("deferred musb restart musbid(%d)\n", musb->id);
+ + 		musb_babble_workaround(musb);
+ + 	}
+ + }
+ + 
+ + static irqreturn_t ti81xx_interrupt(int irq, void *hci)
+ + {
+ + 	struct musb  *musb = hci;
+ + 	void __iomem *reg_base = musb->ctrl_base;
+ + 	unsigned long flags;
+ + 	irqreturn_t ret = IRQ_NONE;
+ + 	u32 pend1 = 0, pend2 = 0;
+ + 	u32 epintr, usbintr;
+ + 	u8  is_babble = 0;
+ + 
+ + 	spin_lock_irqsave(&musb->lock, flags);
+ + 
+ + 	/* Acknowledge and handle non-CPPI interrupts */
+ + 	/* Get endpoint interrupts */
+ + 	epintr = musb_readl(reg_base, USB_EP_INTR_STATUS_REG);
+ + 	musb->int_rx = (epintr & USB_RX_INTR_MASK) >> USB_INTR_RX_SHIFT;
+ + 	musb->int_tx = (epintr & USB_TX_INTR_MASK) >> USB_INTR_TX_SHIFT;
+ + 	if (epintr)
+ + 		musb_writel(reg_base, USB_EP_INTR_STATUS_REG, epintr);
+ + 
+ + 	/* Get usb core interrupts */
+ + 	usbintr = musb_readl(reg_base, USB_CORE_INTR_STATUS_REG);
+ + 	if (!usbintr && !epintr) {
+ + 		dev_dbg(musb->controller, "sprious interrupt\n");
+ + 		goto eoi;
+ + 	}
+ + 
+ + 	if (usbintr)
+ + 		musb_writel(reg_base, USB_CORE_INTR_STATUS_REG, usbintr);
+ + 	musb->int_usb =	(usbintr & USB_INTR_USB_MASK) >> USB_INTR_USB_SHIFT;
+ + 
+ + 	dev_dbg(musb->controller, "usbintr (%x) epintr(%x)\n", usbintr, epintr);
+ + 
+ + 	if (musb->int_usb & MUSB_INTR_SOF) {
+ + 		if (musb->sof_enabled) {
+ + 			if (musb->sof_cnt == 0)
+ + 				ti81xx_musb_disable_sof(musb);
+ + 			else
+ + 				--musb->sof_cnt;
+ + 		}
+ + 		ret = IRQ_HANDLED;
+ + 	}
+ + 
+ + 	if (musb->txfifo_intr_enable && (usbintr & USB_INTR_TXFIFO_MASK)) {
+ + #ifdef CONFIG_USB_TI_CPPI41_DMA
+ + 		dev_dbg(musb->controller,
+ + 			"TxFIFOIntr %x\n", usbintr >> USB_INTR_TXFIFO_EMPTY);
+ + 		cppi41_handle_txfifo_intr(musb,
+ + 				usbintr >> USB_INTR_TXFIFO_EMPTY);
+ + 		ret = IRQ_HANDLED;
+ + #endif
+ + 	}
+ + 	usbintr &= ~USB_INTR_TXFIFO_MASK;
+ + 
+ + 	/*
+ + 	 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
+ + 	 * AM3517's missing ID change IRQ.  We need an ID change IRQ to
+ + 	 * switch appropriately between halves of the OTG state machine.
+ + 	 * Managing DEVCTL.SESSION per Mentor docs requires that we know its
+ + 	 * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
+ + 	 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
+ + 	 */
+ + 	if ((usbintr & MUSB_INTR_BABBLE) && is_otg_enabled(musb)
+ + 		&& (musb->xceiv->state == OTG_STATE_A_HOST))
+ + 		is_babble = 1;
+ + 	else if ((usbintr & MUSB_INTR_BABBLE) && !is_otg_enabled(musb)
+ + 		&& is_host_enabled(musb))
+ + 			is_babble = 1;
+ + 
+ + 	if (is_babble) {
+ + 		if (musb->enable_babble_work != BABBLE_WORKAROUND_3)
+ + 			musb->int_usb = MUSB_INTR_DISCONNECT;
+ + 
+ + 		ERR("CAUTION: musb%d: Babble Interrupt Occured\n", musb->id);
+ + 	}
+ + 
+ + 	if (usbintr & (USB_INTR_DRVVBUS << USB_INTR_USB_SHIFT)) {
+ + 		int drvvbus = musb_readl(reg_base, USB_STAT_REG);
+ + 		void __iomem *mregs = musb->mregs;
+ + 		u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
+ + 		int err;
+ + 
+ + 		err = is_host_enabled(musb) && (musb->int_usb &
+ + 						MUSB_INTR_VBUSERROR);
+ + 		if (err) {
+ + 			/*
+ + 			 * The Mentor core doesn't debounce VBUS as needed
+ + 			 * to cope with device connect current spikes. This
+ + 			 * means it's not uncommon for bus-powered devices
+ + 			 * to get VBUS errors during enumeration.
+ + 			 *
+ + 			 * This is a workaround, but newer RTL from Mentor
+ + 			 * seems to allow a better one: "re"-starting sessions
+ + 			 * without waiting for VBUS to stop registering in
+ + 			 * devctl.
+ + 			 */
+ + 			musb->int_usb &= ~MUSB_INTR_VBUSERROR;
+ + 			musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
+ + 			mod_timer(&musb->otg_workaround,
+ + 						jiffies + POLL_SECONDS * HZ);
+ + 			WARNING("VBUS error workaround (delay coming)\n");
+ + 		} else if (is_host_enabled(musb) && drvvbus) {
+ + 			if ((devctl & MUSB_DEVCTL_SESSION) &&
+ + 				!(devctl & MUSB_DEVCTL_BDEVICE) &&
+ + 				!(devctl & MUSB_DEVCTL_HM)) {
+ + 				dev_dbg(musb->controller,
+ + 					"Only micro-A plug is connected\n");
+ + 			} else {
+ + 				if (musb->is_active)
+ + 					del_timer(&musb->otg_workaround);
+ + 				else
+ + 					musb->is_active = 1;
+ + 
+ + 				MUSB_HST_MODE(musb);
+ + 				musb->xceiv->default_a = 1;
+ + 				musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
+ + 			}
+ + 		} else {
+ + 			musb->is_active = 0;
+ + 			MUSB_DEV_MODE(musb);
+ + 			musb->xceiv->default_a = 0;
+ + 			musb->xceiv->state = OTG_STATE_B_IDLE;
+ + 		}
+ + 
+ + 		/* NOTE: this must complete power-on within 100 ms. */
+ + 		dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
+ + 				drvvbus ? "on" : "off",
+ + 				otg_state_string(musb->xceiv->state),
+ + 				err ? " ERROR" : "",
+ + 				devctl);
+ + 		ret = IRQ_HANDLED;
+ + 	}
+ + 
+ + 	if (musb->int_tx || musb->int_rx || musb->int_usb)
+ + 		ret |= musb_interrupt(musb);
+ + 
+ +  eoi:
+ + 	/* EOI needs to be written for the IRQ to be re-asserted. */
+ + 	if (ret == IRQ_HANDLED || epintr || usbintr) {
+ + 		/* write EOI */
+ + 		musb_writel(reg_base, USB_IRQ_EOI, 1);
+ + 	}
+ + 
+ + 	/* Poll for ID change */
+ + 	if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
+ + 		mod_timer(&musb->otg_workaround, jiffies + POLL_SECONDS * HZ);
+ + 
+ + 	spin_unlock_irqrestore(&musb->lock, flags);
+ + 
+ + 	if (ret != IRQ_HANDLED) {
+ + 		if (epintr || usbintr)
+ + 			/*
+ + 			 * We sometimes get unhandled IRQs in the peripheral
+ + 			 * mode from EP0 and SOF...
+ + 			 */
+ + 			dev_dbg(musb->controller, "Unhandled USB IRQ %08x-%08x\n",
+ + 					 epintr, usbintr);
+ + 		else if (printk_ratelimit())
+ + 			/*
+ + 			 * We've seen series of spurious interrupts in the
+ + 			 * peripheral mode after USB reset and then after some
+ + 			 * time a real interrupt storm starting...
+ + 			 */
+ + 			dev_dbg(musb->controller, "Spurious IRQ, CPPI 4.1 status %08x, %08x\n",
+ + 					 pend1, pend2);
+ + 	}
+ + 
+ + 	if (is_babble) {
+ + 		if (musb->enable_babble_work)
+ + 			schedule_work(&musb->work);
+ + 		else {
+ + 			musb_writeb(musb->mregs, MUSB_DEVCTL,
+ + 				musb_readb(musb->mregs, MUSB_DEVCTL) |
+ + 				MUSB_DEVCTL_SESSION);
+ + 		}
+ + 	}
+ + 	return ret;
+ + }
+ + int ti81xx_musb_set_mode(struct musb *musb, u8 musb_mode)
+ + {
+ + 	void __iomem *reg_base = musb->ctrl_base;
+ + 	u32 regval;
+ + 
+ + 	/* TODO: implement this using CONF0 */
+ + 	if (musb_mode == MUSB_HOST) {
+ + 		regval = musb_readl(reg_base, USB_MODE_REG);
+ + 
+ + 		regval &= ~USBMODE_USBID_HIGH;
+ + 		if (usbid_sw_ctrl && cpu_is_ti816x())
+ + 			regval |= USBMODE_USBID_MUXSEL;
+ + 
+ + 		musb_writel(reg_base, USB_MODE_REG, regval);
+ + 		musb_writel(musb->ctrl_base, USB_PHY_UTMI_REG, 0x02);
+ + 		dev_dbg(musb->controller, "host: value of mode reg=%x regval(%x)\n",
+ + 			musb_readl(reg_base, USB_MODE_REG), regval);
+ + 	} else if (musb_mode == MUSB_PERIPHERAL) {
+ + 		/* TODO commmented writing 8 to USB_MODE_REG device
+ + 			mode is not working */
+ + 		regval = musb_readl(reg_base, USB_MODE_REG);
+ + 
+ + 		regval |= USBMODE_USBID_HIGH;
+ + 		if (usbid_sw_ctrl && cpu_is_ti816x())
+ + 			regval |= USBMODE_USBID_MUXSEL;
+ + 
+ + 		musb_writel(reg_base, USB_MODE_REG, regval);
+ + 		dev_dbg(musb->controller, "device: value of mode reg=%x regval(%x)\n",
+ + 			musb_readl(reg_base, USB_MODE_REG), regval);
+ + 	} else if (musb_mode == MUSB_OTG) {
+ + 		musb_writel(musb->ctrl_base, USB_PHY_UTMI_REG, 0x02);
+ + 	} else
+ + 		return -EIO;
+ + 
+ + 	return 0;
+ + }
+ + 
+ + int ti81xx_musb_init(struct musb *musb)
+ + {
+ + 	void __iomem *reg_base = musb->ctrl_base;
+ + 	struct device *dev = musb->controller;
+ + 	struct musb_hdrc_platform_data *plat = dev->platform_data;
+ + 	struct omap_musb_board_data *data = plat->board_data;
+ + 	u32 rev;
+ + 	u8 mode;
+ + 
+ + 	if (musb->id < 2)
+ + 		gmusb[musb->id] = musb;
+ + 
+ + 	usb_nop_xceiv_register(musb->id);
+ + 
+ + 	musb->xceiv = otg_get_transceiver(musb->id);
+ + 	if (!musb->xceiv)
+ + 		return -ENODEV;
+ + 
+ + 	/* mentor is at offset of 0x400 in am3517/ti81xx */
+ + 	musb->mregs += USB_MENTOR_CORE_OFFSET;
+ + 
+ + 	/* Returns zero if e.g. not clocked */
+ + 	rev = musb_readl(reg_base, USB_REVISION_REG);
+ + 	if (!rev)
+ + 		return -ENODEV;
+ + 
+ + 	pr_info("MUSB%d controller's USBSS revision = %08x\n", musb->id, rev);
+ + 
+ + 	if (is_host_enabled(musb))
+ + 		setup_timer(&musb->otg_workaround, otg_timer,
+ + 					(unsigned long) musb);
+ + 
+ + 	/* Reset the controller */
+ + 	musb_writel(reg_base, USB_CTRL_REG, USB_SOFT_RESET_MASK);
+ + 
+ + 	/* wait till reset bit clears */
+ + 	while ((musb_readl(reg_base, USB_CTRL_REG) & 0x1))
+ + 		cpu_relax();
+ + 
+ + 	/* Start the on-chip PHY and its PLL with PHYWKUP disabled */
+ + 	if (data->set_phy_power)
+ + 		data->set_phy_power(musb->id, 1, false);
+ + 
+ + 	musb->a_wait_bcon = A_WAIT_BCON_TIMEOUT;
+ + 	musb->isr = ti81xx_interrupt;
+ + 
+ + 	if (cpu_is_ti816x())
+ + 		usbid_sw_ctrl = 1;
+ + 
+ + 	if (is_otg_enabled(musb)) {
+ + 		/* if usb-id contolled through software for ti816x then
+ + 		 * configure the usb0 in peripheral mode and usb1 in
+ + 		 * host mode
+ + 		*/
+ + 		if (usbid_sw_ctrl && cpu_is_ti816x())
+ + 			mode = musb->id ? MUSB_HOST : MUSB_PERIPHERAL;
+ + 		else
+ + 			mode = MUSB_OTG;
+ + 	} else
+ + 		/* set musb controller to host mode */
+ + 		mode = is_host_enabled(musb) ? MUSB_HOST : MUSB_PERIPHERAL;
+ + 
+ + 	/* set musb controller to host mode */
+ + 	musb_platform_set_mode(musb, mode);
+ + 
+ + #ifdef CONFIG_USB_TI_CPPI41_DMA
+ + 	musb->txfifo_intr_enable = 1;
+ + 	if (musb->txfifo_intr_enable)
+ + 		printk(KERN_DEBUG "TxFifo Empty intr enabled\n");
+ + 	else
+ + 		printk(KERN_DEBUG "TxFifo Empty intr disabled\n");
+ + 
+ + 	/* enable rxdma GRNDIS mode, as Extra IN token
+ + 	 * issue fixed in PG2.0 RTL
+ + 	 */
+ + 	if (data->grndis_for_host_rx)
+ + 		usb_cppi41_info[musb->id].grndis_for_host_rx = 1;
+ + #endif
+ + 	/* enable babble workaround */
+ + 	INIT_WORK(&musb->work, evm_deferred_musb_restart);
+ + 	musb->enable_babble_work = 0;
+ + 
+ + 	musb->enable_babble_work = BABBLE_WORKAROUND;
+ + 	musb_writel(reg_base, USB_IRQ_EOI, 0);
+ + 
+ + 	if (data->babble_ctrl) {
+ + 		u8 temp;
+ + 		/* enable s/w controlled session bit during
+ + 		 * babble condition
+ + 		 */
+ + 		temp = musb_readb(musb->mregs, MUSB_MISC);
+ + 		temp |= MUSB_MISC_SW_SESSION_CTRL;
+ + 		musb_writeb(musb->mregs, MUSB_MISC, temp);
+ + 
+ + 		musb->enable_babble_work = BABBLE_WORKAROUND_3;
+ + 		pr_info("musb%d: Enabled SW babble control\n", musb->id);
+ + 		dev_dbg(musb->controller, "musb.misc regval %x\n",
+ + 			musb_readb(musb->mregs, MUSB_MISC));
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /* TI81xx supports only 32bit read operation */
+ + void ti81xx_musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
+ + {
+ + 	void __iomem *fifo = hw_ep->fifo;
+ + 	u32		val;
+ + 	int		i;
+ + 
+ + 	/* Read for 32bit-aligned destination address */
+ + 	if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
+ + 		readsl(fifo, dst, len >> 2);
+ + 		dst += len & ~0x03;
+ + 		len &= 0x03;
+ + 	}
+ + 	/*
+ + 	 * Now read the remaining 1 to 3 byte or complete length if
+ + 	 * unaligned address.
+ + 	 */
+ + 	if (len > 4) {
+ + 		for (i = 0; i < (len >> 2); i++) {
+ + 			*(u32 *) dst = musb_readl(fifo, 0);
+ + 			dst += 4;
+ + 		}
+ + 		len &= 0x03;
+ + 	}
+ + 	if (len > 0) {
+ + 		val = musb_readl(fifo, 0);
+ + 		memcpy(dst, &val, len);
+ + 	}
+ + }
+ + 
+ + int ti81xx_musb_exit(struct musb *musb)
+ + {
+ + 	struct device *dev = musb->controller;
+ + 	struct musb_hdrc_platform_data *plat = dev->platform_data;
+ + 	struct omap_musb_board_data *data = plat->board_data;
+ + 
+ + 	if (is_host_enabled(musb))
+ + 		del_timer_sync(&musb->otg_workaround);
+ + 
+ + 	/* Shutdown the on-chip PHY and its PLL. */
+ + 	if (data->set_phy_power)
+ + 		data->set_phy_power(musb->id, 0, false);
+ + 
+ + 	otg_put_transceiver(musb->xceiv);
+ + 	usb_nop_xceiv_unregister(musb->id);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static struct musb_platform_ops ti81xx_ops = {
+ + 	.fifo_mode	= 4,
+ + 	.flags		= MUSB_GLUE_EP_ADDR_FLAT_MAPPING | MUSB_GLUE_DMA_CPPI41,
+ + 	.init		= ti81xx_musb_init,
+ + 	.exit		= ti81xx_musb_exit,
+ + 
+ + 	.enable		= ti81xx_musb_enable,
+ + 	.disable	= ti81xx_musb_disable,
+ + 
+ + 	.try_idle	= ti81xx_musb_try_idle,
+ + 	.set_mode	= ti81xx_musb_set_mode,
+ + 
+ + 	.read_fifo      = ti81xx_musb_read_fifo,
+ + 	.write_fifo     = musb_write_fifo,
+ + 
+ + 	.dma_controller_create	= cppi41_dma_controller_create,
+ + 	.dma_controller_destroy	= cppi41_dma_controller_destroy,
+ + 	.simulate_babble_intr	= musb_simulate_babble,
+ + #ifdef CONFIG_USB_TI_CPPI41_DMA
+ + 	.txfifoempty_intr_enable = txfifoempty_intr_enable,
+ + 	.txfifoempty_intr_disable = txfifoempty_intr_disable,
+ + #endif
+ + 	.reinit = musb_reinit,
+ + };
+ + 
+ + static void __devexit ti81xx_delete_musb_pdev(struct ti81xx_glue *glue, u8 id)
+ + {
+ + 	platform_device_del(glue->musb[id]);
+ + 	platform_device_put(glue->musb[id]);
+ + }
+ + 
+ + static int __devinit ti81xx_create_musb_pdev(struct ti81xx_glue *glue, u8 id)
+ + {
+ + 	struct device *dev = glue->dev;
+ + 	struct platform_device *pdev = to_platform_device(dev);
+ + 	struct musb_hdrc_platform_data  *pdata = dev->platform_data;
+ + 	struct omap_musb_board_data *bdata = pdata->board_data;
+ + 	struct platform_device	*musb;
+ + 	struct resource *res;
+ + 	struct resource	resources[2];
+ + 	char res_name[10];
+ + 	int ret = 0;
+ + 
+ + 	/* get memory resource */
+ + 	sprintf(res_name, "musb%d", id);
+ + 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, res_name);
+ + 	if (!res) {
+ + 		dev_err(dev, "%s get mem resource failed\n", res_name);
+ + 		ret = -ENODEV;
+ + 		goto err0;
+ + 	}
+ + 	res->parent = NULL;
+ + 	resources[0] = *res;
+ + 
+ + 	/* get irq resource */
+ + 	sprintf(res_name, "musb%d-irq", id);
+ + 	res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, res_name);
+ + 	if (!res) {
+ + 		dev_err(dev, "%s get irq resource failed\n", res_name);
+ + 		ret = -ENODEV;
+ + 		goto err0;
+ + 	}
+ + 	res->parent = NULL;
+ + 	resources[1] = *res;
+ + 
+ + 	/* allocate the child platform device */
+ + 	musb = platform_device_alloc("musb-hdrc", id);
+ + 	if (!musb) {
+ + 		dev_err(dev, "failed to allocate musb device\n");
+ + 		goto err0;
+ + 	}
+ + 
+ + 	musb->id			= id;
+ + 	musb->dev.parent		= dev;
+ + 	musb->dev.dma_mask		= &musb_dmamask;
+ + 	musb->dev.coherent_dma_mask	= musb_dmamask;
+ + 
+ + 	glue->musb[id]			= musb;
+ + 
+ + 	pdata->platform_ops		= &ti81xx_ops;
+ + 
+ + 	ret = platform_device_add_resources(musb, resources, 2);
+ + 	if (ret) {
+ + 		dev_err(dev, "failed to add resources\n");
+ + 		goto err1;
+ + 	}
+ + 
+ + 	if (id == 0)
+ + 		pdata->mode = bdata->mode & USB0PORT_MODEMASK;
+ + 	else
+ + 		pdata->mode = (bdata->mode & USB1PORT_MODEMASK)
+ + 					>> USB1PORT_MODESHIFT;
+ + 
+ + 	dev_info(dev, "musb%d, board_mode=0x%x, plat_mode=0x%x\n",
+ + 					id, bdata->mode, pdata->mode);
+ + 
+ + 	ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
+ + 	if (ret) {
+ + 		dev_err(dev, "failed to add platform_data\n");
+ + 		goto err1;
+ + 	}
+ + 
+ + 	ret = platform_device_add(musb);
+ + 	if (ret) {
+ + 		dev_err(dev, "failed to register musb device\n");
+ + 		goto err1;
+ + 	}
+ + 
+ + 	return 0;
+ + 
+ + err1:
+ + 	platform_device_put(musb);
+ + err0:
+ + 	return ret;
+ + }
+ + 
+ + static int __init ti81xx_probe(struct platform_device *pdev)
+ + {
+ + 	struct ti81xx_glue *glue;
+ + 	struct device *dev = &pdev->dev;
+ + 	struct musb_hdrc_platform_data *plat = dev->platform_data;
+ + 	struct omap_musb_board_data *data = plat->board_data;
+ + 	int ret = 0, i;
+ + 	struct resource *res;
+ + 
+ + 	/* allocate glue */
+ + 	glue = kzalloc(sizeof(*glue), GFP_KERNEL);
+ + 	if (!glue) {
+ + 		dev_err(&pdev->dev, "unable to allocate glue memory\n");
+ + 		ret = -ENOMEM;
+ + 		goto err0;
+ + 	}
+ + 
+ + 	/* get memory resource */
+ + 	glue->mem_pa = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ + 	if (!glue->mem_pa) {
+ + 		dev_err(&pdev->dev, "failed to get usbss mem resourse\n");
+ + 		ret = -ENODEV;
+ + 		goto err1;
+ + 	}
+ + 
+ + 	/* get memory resource */
+ + 	res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "usbss-irq");
+ + 	if (!res) {
+ + 		dev_err(&pdev->dev, "failed to get usbss irq resourse\n");
+ + 		ret = -ENODEV;
+ + 		goto err1;
+ + 	}
+ + 	glue->irq = res->start;
+ + 
+ + 	/* iomap for usbss mem space */
+ + 	glue->mem_va =
+ + 		ioremap(glue->mem_pa->start, resource_size(glue->mem_pa));
+ + 	if (!glue->mem_va) {
+ + 		dev_err(&pdev->dev, "usbss ioremap failed\n");
+ + 		ret = -ENOMEM;
+ + 		goto err1;
+ + 	}
+ + 	usbss_virt_base = glue->mem_va;
+ + 
+ + 	glue->first = 1;
+ + 	glue->dev = &pdev->dev;
+ + 	platform_set_drvdata(pdev, glue);
+ + 
+ + 	/* enable clocks */
+ + 	pm_runtime_enable(&pdev->dev);
+ + 	ret = pm_runtime_get_sync(&pdev->dev);
+ + 	if (ret < 0) {
+ + 		dev_err(dev, "pm_runtime_get_sync FAILED");
+ + 		goto err2;
+ + 	}
+ + 
+ + 	/* usb subsystem init */
+ + 	usbotg_ss_init();
+ + 
+ + 	/* clear any USBSS interrupts */
+ + 	writel(0, glue->mem_va + USBSS_IRQ_EOI);
+ + 	writel(readl(glue->mem_va + USBSS_IRQ_STATUS),
+ + 					glue->mem_va + USBSS_IRQ_STATUS);
+ + 
+ + 	/* create the child platform device for mulitple instances of musb */
+ + 	for (i = 0; i <= data->instances; ++i) {
+ + #ifdef CONFIG_USB_TI_CPPI41_DMA
+ + 		/* initialize the cppi41dma init */
+ + 		cppi41_init(i, glue->irq, data->instances+1);
+ + #endif
+ + 		ret = ti81xx_create_musb_pdev(glue, i);
+ + 		if (ret != 0)
+ + 			goto err3;
+ + 	}
+ + 
+ + 	return 0;
+ + 
+ + err3:
+ + 	pm_runtime_put_sync(&pdev->dev);
+ + err2:
+ + 	pm_runtime_disable(&pdev->dev);
+ + 	iounmap(glue->mem_va);
+ + err1:
+ + 	kfree(glue);
+ + err0:
+ + 	return ret;
+ + }
+ + 
+ + static int __exit ti81xx_remove(struct platform_device *pdev)
+ + {
+ + 	struct ti81xx_glue *glue = platform_get_drvdata(pdev);
+ + 	struct device *dev = &pdev->dev;
+ + 	struct musb_hdrc_platform_data *plat = dev->platform_data;
+ + 	struct omap_musb_board_data *data = plat->board_data;
+ + 	int i;
+ + 
+ + 	pm_runtime_put_sync(&pdev->dev);
+ + 	pm_runtime_disable(&pdev->dev);
+ + 
+ + 	/* delete the child platform device for mulitple instances of musb */
+ + 	for (i = 0; i <= data->instances; ++i)
+ + 		ti81xx_delete_musb_pdev(glue, i);
+ + 
+ + #ifdef CONFIG_USB_TI_CPPI41_DMA
+ + 	cppi41_free();
+ + #endif
+ + 	/* iounmap */
+ + 	iounmap(glue->mem_va);
+ + 	usbotg_ss_uninit();
+ + 
+ + 	kfree(glue);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + #ifdef CONFIG_PM
+ + static void ti81xx_save_context(struct ti81xx_glue *glue)
+ + {
+ + 	struct ti81xx_usbss_regs *usbss = &glue->usbss_regs;
+ + 	u8 i, j;
+ + 
+ + 	/* save USBSS register */
+ + 	usbss->irq_en_set = usbss_read(USBSS_IRQ_ENABLE_SET);
+ + 
+ + #ifdef CONFIG_USB_TI_CPPI41_DMA
+ + 	for (i = 0 ; i < 4 ; i++) {
+ + 		usbss->irq_dma_th_tx0[i] =
+ + 			usbss_read(USBSS_IRQ_DMA_THRESHOLD_TX0 + (0x4 * i));
+ + 		usbss->irq_dma_th_rx0[i] =
+ + 			usbss_read(USBSS_IRQ_DMA_THRESHOLD_RX0 + (0x4 * i));
+ + 		usbss->irq_dma_th_tx1[i] =
+ + 			usbss_read(USBSS_IRQ_DMA_THRESHOLD_TX1 + (0x4 * i));
+ + 		usbss->irq_dma_th_rx1[i] =
+ + 			usbss_read(USBSS_IRQ_DMA_THRESHOLD_RX1 + (0x4 * i));
+ + 
+ + 		usbss->irq_frame_th_tx0[i] =
+ + 			usbss_read(USBSS_IRQ_FRAME_THRESHOLD_TX0 + (0x4 * i));
+ + 		usbss->irq_frame_th_rx0[i] =
+ + 			usbss_read(USBSS_IRQ_FRAME_THRESHOLD_RX0 + (0x4 * i));
+ + 		usbss->irq_frame_th_tx1[i] =
+ + 			usbss_read(USBSS_IRQ_FRAME_THRESHOLD_TX1 + (0x4 * i));
+ + 		usbss->irq_frame_th_rx1[i] =
+ + 			usbss_read(USBSS_IRQ_FRAME_THRESHOLD_RX1 + (0x4 * i));
+ + 	}
+ + 	for (i = 0 ; i < 2 ; i++) {
+ + 		usbss->irq_dma_en[i] =
+ + 			usbss_read(USBSS_IRQ_DMA_ENABLE_0 + (0x4 * i));
+ + 		usbss->irq_frame_en[i] =
+ + 			usbss_read(USBSS_IRQ_FRAME_ENABLE_0 + (0x4 * i));
+ + 	}
+ + #endif
+ + 	/* save usbX register */
+ + 	for (i = 0 ; i < 2 ; i++) {
+ + 		struct ti81xx_usb_regs *usb = &glue->usb_regs[i];
+ + 		struct musb *musb = platform_get_drvdata(glue->musb[i]);
+ + 		void __iomem *cbase = musb->ctrl_base;
+ + 
+ + 		/* disable the timers */
+ + 		if (timer_pending(&musb->otg_workaround) &&
+ + 					is_host_enabled(musb)) {
+ + 			del_timer_sync(&musb->otg_workaround);
+ + 			musb->en_otgw_timer = 1;
+ + 		}
+ + 
+ + 		if (timer_pending(&musb->otg_timer) &&
+ + 					is_otg_enabled(musb)) {
+ + 			del_timer_sync(&musb->otg_timer);
+ + 			musb->en_otg_timer = 1;
+ + 		}
+ + 
+ + 		musb_save_context(musb);
+ + 		usb->control = musb_readl(cbase, USB_CTRL_REG);
+ + 
+ + 		for (j = 0 ; j < 2 ; j++)
+ + 			usb->irq_en_set[j] = musb_readl(cbase,
+ + 					USB_IRQ_ENABLE_SET_0 + (0x4 * j));
+ + #ifdef CONFIG_USB_TI_CPPI41_DMA
+ + 		usb->tx_mode = musb_readl(cbase, USB_TX_MODE_REG);
+ + 		usb->rx_mode = musb_readl(cbase, USB_RX_MODE_REG);
+ + 
+ + 		for (j = 0 ; j < 15 ; j++)
+ + 			usb->grndis_size[j] = musb_readl(cbase,
+ + 					USB_GENERIC_RNDIS_EP_SIZE_REG(j + 1));
+ + 
+ + 		usb->auto_req = musb_readl(cbase, TI81XX_USB_AUTOREQ_REG);
+ + 		usb->teardn = musb_readl(cbase, TI81XX_USB_TEARDOWN_REG);
+ + 		usb->th_xdma_idle = musb_readl(cbase, USB_TH_XDMA_IDLE_REG);
+ + #endif
+ + 		usb->srp_fix = musb_readl(cbase, USB_SRP_FIX_TIME_REG);
+ + 		usb->phy_utmi = musb_readl(cbase, USB_PHY_UTMI_REG);
+ + 		usb->mgc_utmi_loopback = musb_readl(cbase, USB_PHY_UTMI_LB_REG);
+ + 		usb->mode = musb_readl(cbase, USB_MODE_REG);
+ + 	}
+ + #ifdef CONFIG_USB_TI_CPPI41_DMA
+ + 	/* save CPPI4.1 DMA register for dma block 0 */
+ + 	cppi41_save_context(0);
+ + #endif
+ + }
+ + static void ti81xx_restore_context(struct ti81xx_glue *glue)
+ + {
+ + 	struct ti81xx_usbss_regs *usbss = &glue->usbss_regs;
+ + 	u8 i, j;
+ + 
+ + 	/* restore USBSS register */
+ + 	usbss_write(USBSS_IRQ_ENABLE_SET, usbss->irq_en_set);
+ + 
+ + #ifdef CONFIG_USB_TI_CPPI41_DMA
+ + 	for (i = 0 ; i < 4 ; i++) {
+ + 		usbss_write(USBSS_IRQ_DMA_THRESHOLD_TX0 + (0x4 * i),
+ + 				usbss->irq_dma_th_tx0[i]);
+ + 		usbss_write(USBSS_IRQ_DMA_THRESHOLD_RX0 + (0x4 * i),
+ + 				usbss->irq_dma_th_rx0[i]);
+ + 		usbss_write(USBSS_IRQ_DMA_THRESHOLD_TX1 + (0x4 * i),
+ + 				usbss->irq_dma_th_tx1[i]);
+ + 		usbss_write(USBSS_IRQ_DMA_THRESHOLD_RX1 + (0x4 * i),
+ + 				usbss->irq_dma_th_rx1[i]);
+ + 
+ + 		usbss_write(USBSS_IRQ_FRAME_THRESHOLD_TX0 + (0x4 * i),
+ + 				usbss->irq_frame_th_tx0[i]);
+ + 		usbss_write(USBSS_IRQ_FRAME_THRESHOLD_RX0 + (0x4 * i),
+ + 				usbss->irq_frame_th_rx0[i]);
+ + 		usbss_write(USBSS_IRQ_FRAME_THRESHOLD_TX1 + (0x4 * i),
+ + 				usbss->irq_frame_th_tx1[i]);
+ + 		usbss_write(USBSS_IRQ_FRAME_THRESHOLD_RX1 + (0x4 * i),
+ + 				usbss->irq_frame_th_rx1[i]);
+ + 	}
+ + 	for (i = 0 ; i < 2 ; i++) {
+ + 		usbss_write(USBSS_IRQ_DMA_ENABLE_0 + (0x4 * i),
+ + 				usbss->irq_dma_en[i]);
+ + 		usbss_write(USBSS_IRQ_FRAME_ENABLE_0 + (0x4 * i),
+ + 				usbss->irq_frame_en[i]);
+ + 	}
+ + #endif
+ + 	/* restore usbX register */
+ + 	for (i = 0 ; i < 2 ; i++) {
+ + 		struct ti81xx_usb_regs *usb = &glue->usb_regs[i];
+ + 		struct musb *musb = platform_get_drvdata(glue->musb[i]);
+ + 		void __iomem *cbase = musb->ctrl_base;
+ + 
+ + 		musb_restore_context(musb);
+ + 		musb_writel(cbase, USB_CTRL_REG, usb->control);
+ + 
+ + 		for (j = 0 ; j < 2 ; j++)
+ + 			musb_writel(cbase, USB_IRQ_ENABLE_SET_0 + (0x4 * j),
+ + 					usb->irq_en_set[j]);
+ + 
+ + #ifdef CONFIG_USB_TI_CPPI41_DMA
+ + 		musb_writel(cbase, USB_TX_MODE_REG, usb->tx_mode);
+ + 		musb_writel(cbase, USB_RX_MODE_REG, usb->rx_mode);
+ + 
+ + 		for (j = 0 ; j < 15 ; j++)
+ + 			musb_writel(cbase, USB_GENERIC_RNDIS_EP_SIZE_REG(j + 1),
+ + 					usb->grndis_size[j]);
+ + 
+ + 		musb_writel(cbase, TI81XX_USB_AUTOREQ_REG, usb->auto_req);
+ + 		musb_writel(cbase, TI81XX_USB_TEARDOWN_REG, usb->teardn);
+ + 		musb_writel(cbase, USB_TH_XDMA_IDLE_REG, usb->th_xdma_idle);
+ + #endif
+ + 		musb_writel(cbase, USB_SRP_FIX_TIME_REG, usb->srp_fix);
+ + 		musb_writel(cbase, USB_PHY_UTMI_REG, usb->phy_utmi);
+ + 		musb_writel(cbase, USB_PHY_UTMI_LB_REG, usb->mgc_utmi_loopback);
+ + 		musb_writel(cbase, USB_MODE_REG, usb->mode);
+ + 
+ + 		/* reenable the timers */
+ + 		if (musb->en_otgw_timer && is_host_enabled(musb)) {
+ + 			mod_timer(&musb->otg_workaround,
+ + 					jiffies + POLL_SECONDS * HZ);
+ + 			musb->en_otgw_timer = 0;
+ + 		}
+ + 		if (musb->en_otg_timer && is_otg_enabled(musb)) {
+ + 			mod_timer(&musb->otg_timer,
+ + 					jiffies + POLL_SECONDS * HZ);
+ + 			musb->en_otg_timer = 0;
+ + 		}
+ + 	}
+ + #ifdef CONFIG_USB_TI_CPPI41_DMA
+ + 	/* restore CPPI4.1 DMA register for dma block 0 */
+ + 	cppi41_restore_context(0, dma_sched_table);
+ + #endif
+ + 	/* controller needs delay for successful resume */
+ + 	msleep(200);
+ + }
+ + static int ti81xx_runtime_suspend(struct device *dev)
+ + {
+ + 	struct ti81xx_glue *glue = dev_get_drvdata(dev);
+ + 	struct musb_hdrc_platform_data *plat = dev->platform_data;
+ + 	struct omap_musb_board_data *data = plat->board_data;
+ + 	struct platform_device *pdev;
+ + 	int i;
+ + 
+ + 	/* save wrappers and cppi4.1 dma register */
+ + 	ti81xx_save_context(glue);
+ + 
+ + 	/* Shutdown the on-chip PHY and its PLL.
+ + 	 * Enable USB PHYWKUP only if enabled through sysfs.
+ + 	 * By default USB PHYWKUP is  disabled
+ + 	 */
+ + 	if (data->set_phy_power) {
+ + 		for (i = 0; i <= data->instances; ++i) {
+ + 			pdev = glue->musb[i];
+ + 			if (device_may_wakeup(&pdev->dev))
+ + 				data->set_phy_power(i, 0, true);
+ + 			else
+ + 				data->set_phy_power(i, 0, false);
+ + 		}
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static int ti81xx_runtime_resume(struct device *dev)
+ + {
+ + 	struct ti81xx_glue *glue = dev_get_drvdata(dev);
+ + 	struct musb_hdrc_platform_data *plat = dev->platform_data;
+ + 	struct omap_musb_board_data *data = plat->board_data;
+ + 	int i;
+ + 
+ + 	/*
+ + 	 * ignore first call of resume as all registers are not yet
+ + 	 * initialized
+ + 	 */
+ + 	if (glue->first) {
+ + 		glue->first = 0;
+ + 		return 0;
+ + 	}
+ + 
+ + 	/* Start the on-chip PHY and its PLL. */
+ + 	for (i = 0; i <= data->instances; ++i) {
+ + 		if (data->set_phy_power)
+ + 			data->set_phy_power(i, 1, false);
+ + 	}
+ + 
+ + 	/* restore wrappers and cppi4.1 dma register */
+ + 	ti81xx_restore_context(glue);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static const struct dev_pm_ops ti81xx_pm_ops = {
+ + 	.runtime_suspend = ti81xx_runtime_suspend,
+ + 	.runtime_resume	= ti81xx_runtime_resume,
+ + };
+ + 
+ + #define DEV_PM_OPS	(&ti81xx_pm_ops)
+ + #else
+ + #define DEV_PM_OPS	NULL
+ + #endif
+ + 
+ + static struct platform_driver ti81xx_musb_driver = {
+ + 	.remove         = __exit_p(ti81xx_remove),
+ + 	.driver         = {
+ + 		.name   = "musb-ti81xx",
+ + 		.pm	= DEV_PM_OPS,
+ + 	},
+ + };
+ + 
+ + MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
+ + MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
+ + MODULE_LICENSE("GPL v2");
+ + 
+ + static int __init ti81xx_glue_init(void)
+ + {
+ + 	return platform_driver_probe(&ti81xx_musb_driver, ti81xx_probe);
+ + }
+ + subsys_initcall(ti81xx_glue_init);
+ + 
+ + static void __exit ti81xx_glue_exit(void)
+ + {
+ + #ifdef CONFIG_USB_TI_CPPI41_DMA
+ + 	/* free the usbss irq */
+ + 	free_irq(TI81XX_IRQ_USBSS, 0);
+ + #endif
+ + 
+ + 	/* disable the interrupts */
+ + 	usbss_write(USBSS_IRQ_EOI, 0);
+ + 	usbss_write(USBSS_IRQ_ENABLE_SET, 0);
+ + 	usbss_write(USBSS_IRQ_DMA_ENABLE_0, 0);
+ + 
+ + 	/* unregister platform driver */
+ + 	platform_driver_unregister(&ti81xx_musb_driver);
+ + }
+ + module_exit(ti81xx_glue_exit);
+ diff -crN linux-3.2.1_o/drivers/usb/musb/ti81xx.h linux-3.2.1/drivers/usb/musb/ti81xx.h
+ *** linux-3.2.1_o/drivers/usb/musb/ti81xx.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/drivers/usb/musb/ti81xx.h	2014-11-25 13:19:16.700047930 +0900
+ ***************
+ *** 0 ****
+ --- 1,176 ----
+ + /*
+ +  * Copyright (C) 2005-2006 by Texas Instruments
+ +  *
+ +  * The Inventra Controller Driver for Linux is free software; you
+ +  * can redistribute it and/or modify it under the terms of the GNU
+ +  * General Public License version 2 as published by the Free Software
+ +  * Foundation.
+ +  */
+ + 
+ + #ifndef __MUSB_HDRDF_H__
+ + #define __MUSB_HDRDF_H__
+ + 
+ + #define TI81XX_USB_CPPIDMA_BASE 0x47402000
+ + #define TI81XX_USB_CPPIDMA_LEN  0x5FFF
+ + #define TI81XX_IRQ_USBSS        17
+ + 
+ + /* Netra USB susbsystem register offsets */
+ + #define USBSS_REVISION			0x0000
+ + #define USBSS_SYSCONFIG			0x0010
+ + /* USBSS EOI interrupt register */
+ + #define USBSS_IRQ_EOI			0x0020
+ + /* USBSS interrupt generation/status register */
+ + #define USBSS_IRQ_STATUS_RAW		0x0024
+ + /* USBSS interrupt status register */
+ + #define USBSS_IRQ_STATUS		0x0028
+ + /* USBSS interrupt enable register */
+ + #define USBSS_IRQ_ENABLE_SET		0x002c
+ + /* USBSS interrupt clear register */
+ + #define USBSS_IRQ_ENABLE_CLEAR		0x0030
+ + /* USB0: TxDMA 8bit tx completion interrupt pacing
+ + 	threshold value for ep1..15 */
+ + #define USBSS_IRQ_DMA_THRESHOLD_TX0	0x0100
+ + /* USB0: RxDMA 8bit rx completion interrupt pacing
+ + 	threshold value for ep1..15 */
+ + #define USBSS_IRQ_DMA_THRESHOLD_RX0	0x0110
+ + /* USB1: TxDMA 8bit tx completion interrupt pacing
+ + 	threshold value for ep1..15 */
+ + #define USBSS_IRQ_DMA_THRESHOLD_TX1	0x0120
+ + /* USB1: RxDMA 8bit rx completion interrupt pacing
+ + 	threshold value for ep1..15 */
+ + #define USBSS_IRQ_DMA_THRESHOLD_RX1	0x0130
+ + /* USB0: TxDMA threshold enable tx completion for ep1..ep15
+ + 	RxDMA threshold enable rx completion for ep1..ep15 */
+ + #define USBSS_IRQ_DMA_ENABLE_0		0x0140
+ + /* USB1: TxDMA threshold enable for ep1..ep15
+ + 	RxDMA threshold enable for ep1..ep15 */
+ + #define USBSS_IRQ_DMA_ENABLE_1		0x0144
+ + /* USB0: TxDMA Frame threshold for tx completion for ep1..ep15
+ + 	RxDMA Frame threshold for rx completion for ep1..ep15 */
+ + #define USBSS_IRQ_FRAME_THRESHOLD_TX0	0x0200
+ + #define USBSS_IRQ_FRAME_THRESHOLD_RX0	0x0210
+ + /* USB1: TxDMA Frame threshold for tx completion for ep1..ep15
+ + 	RxDMA Frame threshold for rx completion for ep1..ep15 */
+ + #define USBSS_IRQ_FRAME_THRESHOLD_TX1	0x0220
+ + #define USBSS_IRQ_FRAME_THRESHOLD_RX1	0x0230
+ + /* USB0: Frame threshold enable tx completion for ep1..ep15
+ + 	Frame threshold enable rx completion for ep1..ep15 */
+ + #define USBSS_IRQ_FRAME_ENABLE_0	0x0240
+ + #define USBSS_IRQ_FRAME_ENABLE_1	0x0244
+ + 
+ + 
+ + /* USB 2.0 OTG module registers */
+ + #define USB_REVISION_REG        0x0000
+ + #define USB_CTRL_REG            0x0014
+ + #define USB_STAT_REG            0x0018
+ + #define	USB_IRQ_MERGED_STATUS	0x0020
+ + #define USB_IRQ_EOI		0x0024
+ + #define	USB_IRQ_STATUS_RAW_0	0x0028
+ + #define	USB_IRQ_STATUS_RAW_1	0x002c
+ + #define	USB_IRQ_STATUS_0	0x0030
+ + #define	USB_IRQ_STATUS_1	0x0034
+ + #define	USB_IRQ_ENABLE_SET_0	0x0038
+ + #define	USB_IRQ_ENABLE_SET_1	0x003c
+ + #define	USB_IRQ_ENABLE_CLR_0	0x0040
+ + #define	USB_IRQ_ENABLE_CLR_1	0x0044
+ + 
+ + #define USB_EP_INTR_SET_REG		(USB_IRQ_ENABLE_SET_0)
+ + #define USB_CORE_INTR_SET_REG		(USB_IRQ_ENABLE_SET_1)
+ + #define USB_EP_INTR_CLEAR_REG		(USB_IRQ_ENABLE_CLR_0)
+ + #define USB_CORE_INTR_CLEAR_REG		(USB_IRQ_ENABLE_CLR_1)
+ + #define USB_EP_INTR_STATUS_REG		(USB_IRQ_STATUS_0)
+ + #define USB_CORE_INTR_STATUS_REG	(USB_IRQ_STATUS_1)
+ + 
+ + #define USB_GRNDIS_EPSIZE_OFFS	0X0080
+ + #define USB_SRP_FIX_TIME_REG    0x00d4
+ + #define USB_TH_XDMA_IDLE_REG    0x00dc
+ + #define USB_PHY_UTMI_REG	0x00e0
+ + #define USB_PHY_UTMI_LB_REG	0x00e4
+ + #define USB_MODE_REG		0x00e8
+ + 
+ + #define QUEUE_THRESHOLD_INTR_ENABLE_REG 0xc0
+ + #define QUEUE_63_THRESHOLD_REG  0xc4
+ + #define QUEUE_63_THRESHOLD_INTR_CLEAR_REG 0xc8
+ + #define QUEUE_65_THRESHOLD_REG  0xd4
+ + #define QUEUE_65_THRESHOLD_INTR_CLEAR_REG 0xd8
+ + 
+ + /* Control register bits */
+ + #define USB_SOFT_RESET_MASK     1
+ + 
+ + /* Mode register bits */
+ + #define USB_MODE_SHIFT(n)       ((((n) - 1) << 1))
+ + #define USB_MODE_MASK(n)        (3 << USB_MODE_SHIFT(n))
+ + #define USB_RX_MODE_SHIFT(n)    USB_MODE_SHIFT(n)
+ + #define USB_TX_MODE_SHIFT(n)    USB_MODE_SHIFT(n)
+ + #define USB_RX_MODE_MASK(n)     USB_MODE_MASK(n)
+ + #define USB_TX_MODE_MASK(n)     USB_MODE_MASK(n)
+ + #define USB_TRANSPARENT_MODE    0
+ + #define USB_RNDIS_MODE          1
+ + #define USB_CDC_MODE            2
+ + #define USB_GENERIC_RNDIS_MODE  3
+ + 
+ + /* AutoReq register bits */
+ + #define USB_RX_AUTOREQ_SHIFT(n) (((n) - 1) << 1)
+ + #define USB_RX_AUTOREQ_MASK(n)  (3 << USB_RX_AUTOREQ_SHIFT(n))
+ + #define USB_NO_AUTOREQ          0
+ + #define USB_AUTOREQ_ALL_BUT_EOP 1
+ + #define USB_AUTOREQ_ALWAYS      3
+ + 
+ + /* Teardown register bits */
+ + #define USB_TX_TDOWN_SHIFT(n)   (16 + (n))
+ + #define USB_TX_TDOWN_MASK(n)    (1 << USB_TX_TDOWN_SHIFT(n))
+ + #define USB_RX_TDOWN_SHIFT(n)   (n)
+ + #define USB_RX_TDOWN_MASK(n)    (1 << USB_RX_TDOWN_SHIFT(n))
+ + 
+ + /* USB interrupt register bits */
+ + #define USB_INTR_USB_SHIFT      0
+ + #define USB_INTR_USB_MASK       (0x1ff << USB_INTR_USB_SHIFT) /* 8 Mentor */
+ + #define USB_INTR_TXFIFO_MASK     (0xffff << 16)
+ + #define USB_INTR_TXFIFO_EMPTY	17
+ + 
+ + 				/* interrupts and DRVVBUS interrupt */
+ + #define USB_INTR_DRVVBUS        0x100
+ + #define USB_INTR_RX_SHIFT       16
+ + #define USB_INTR_TX_SHIFT       0
+ + 
+ + #define USB_MENTOR_CORE_OFFSET  0x400
+ + #define USB_CPPI41_NUM_CH       15
+ + 
+ + #define MAX_MUSB_INSTANCE	2
+ + /* CPPI 4.1 queue manager registers */
+ + #define QMGR_PEND0_REG		0x4090
+ + #define QMGR_PEND1_REG		0x4094
+ + #define QMGR_PEND2_REG		0x4098
+ + 
+ + #define QMGR_RGN_OFFS		0x4000
+ + #define QMRG_DESCRGN_OFFS	0x5000
+ + #define QMGR_REG_OFFS		0x6000
+ + #define QMGR_STAT_OFFS		0x7000
+ + #define DMA_GLBCTRL_OFFS	0x2000
+ + #define DMA_CHCTRL_OFFS		0x2800
+ + #define DMA_SCHED_OFFS		0x3000
+ + #define DMA_SCHEDTBL_OFFS	0x3800
+ + 
+ + #define USB_TX_EP_MASK		0xffff		/* EP0 + 15 Tx EPs */
+ + #define USB_RX_EP_MASK		0xfffe		/* 15 Rx EPs */
+ + 
+ + #define USB_TX_INTR_MASK	(USB_TX_EP_MASK << USB_INTR_TX_SHIFT)
+ + #define USB_RX_INTR_MASK	(USB_RX_EP_MASK << USB_INTR_RX_SHIFT)
+ + 
+ + #define A_WAIT_BCON_TIMEOUT	1100		/* in ms */
+ + 
+ + #define USBSS_INTR_RX_STARV	0x00000001
+ + #define USBSS_INTR_PD_CMPL	0x00000004
+ + #define USBSS_INTR_TX_CMPL	0x00000500
+ + #define USBSS_INTR_RX_CMPL	0x00000A00
+ + #define USBSS_INTR_FLAGS	(USBSS_INTR_PD_CMPL | USBSS_INTR_TX_CMPL \
+ + 					| USBSS_INTR_RX_CMPL)
+ + 
+ + #define	USBMODE_USBID_MUXSEL	0x80
+ + #define	USBMODE_USBID_HIGH	0x100
+ + 
+ + #define	USB0PORT_MODEMASK	0x0f
+ + #define	USB1PORT_MODEMASK	0xf0
+ + #define USB1PORT_MODESHIFT	4
+ + extern void usb_nop_xceiv_register(int id);
+ + #endif
+ diff -crN linux-3.2.1_o/drivers/usb/musb/tusb6010.c linux-3.2.1/drivers/usb/musb/tusb6010.c
+ *** linux-3.2.1_o/drivers/usb/musb/tusb6010.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/musb/tusb6010.c	2014-11-25 13:19:16.700047930 +0900
+ ***************
+ *** 40,50 ****
+    * Checks the revision. We need to use the DMA register as 3.0 does not
+    * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV.
+    */
+ ! u8 tusb_get_revision(struct musb *musb)
+   {
+   	void __iomem	*tbase = musb->ctrl_base;
+   	u32		die_id;
+ ! 	u8		rev;
+   
+   	rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;
+   	if (TUSB_REV_MAJOR(rev) == 3) {
+ --- 40,50 ----
+    * Checks the revision. We need to use the DMA register as 3.0 does not
+    * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV.
+    */
+ ! static u16 tusb_get_revision(struct musb *musb)
+   {
+   	void __iomem	*tbase = musb->ctrl_base;
+   	u32		die_id;
+ ! 	u16		rev;
+   
+   	rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;
+   	if (TUSB_REV_MAJOR(rev) == 3) {
+ ***************
+ *** 56,66 ****
+   
+   	return rev;
+   }
+   
+   static int tusb_print_revision(struct musb *musb)
+   {
+   	void __iomem	*tbase = musb->ctrl_base;
+ ! 	u8		rev;
+   
+   	rev = tusb_get_revision(musb);
+   
+ --- 56,67 ----
+   
+   	return rev;
+   }
+ + EXPORT_SYMBOL_GPL(tusb_get_revision);
+   
+   static int tusb_print_revision(struct musb *musb)
+   {
+   	void __iomem	*tbase = musb->ctrl_base;
+ ! 	u16		rev;
+   
+   	rev = tusb_get_revision(musb);
+   
+ ***************
+ *** 171,177 ****
+   	}
+   }
+   
+ ! void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
+   {
+   	struct musb *musb = hw_ep->musb;
+   	void __iomem	*ep_conf = hw_ep->conf;
+ --- 172,179 ----
+   	}
+   }
+   
+ ! static void tusb_musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
+ ! 		const u8 *buf)
+   {
+   	struct musb *musb = hw_ep->musb;
+   	void __iomem	*ep_conf = hw_ep->conf;
+ ***************
+ *** 221,227 ****
+   		tusb_fifo_write_unaligned(fifo, buf, len);
+   }
+   
+ ! void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
+   {
+   	struct musb *musb = hw_ep->musb;
+   	void __iomem	*ep_conf = hw_ep->conf;
+ --- 223,229 ----
+   		tusb_fifo_write_unaligned(fifo, buf, len);
+   }
+   
+ ! static void tusb_musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
+   {
+   	struct musb *musb = hw_ep->musb;
+   	void __iomem	*ep_conf = hw_ep->conf;
+ ***************
+ *** 854,860 ****
+   
+   		dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src);
+   		real_dma_src = ~real_dma_src & dma_src;
+ ! 		if (tusb_dma_omap() && real_dma_src) {
+   			int	tx_source = (real_dma_src & 0xffff);
+   			int	i;
+   
+ --- 856,862 ----
+   
+   		dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src);
+   		real_dma_src = ~real_dma_src & dma_src;
+ ! 		if (tusb_dma_omap(musb) && real_dma_src) {
+   			int	tx_source = (real_dma_src & 0xffff);
+   			int	i;
+   
+ ***************
+ *** 1074,1081 ****
+   	void __iomem		*sync = NULL;
+   	int			ret;
+   
+ ! 	usb_nop_xceiv_register();
+ ! 	musb->xceiv = otg_get_transceiver();
+   	if (!musb->xceiv)
+   		return -ENODEV;
+   
+ --- 1076,1083 ----
+   	void __iomem		*sync = NULL;
+   	int			ret;
+   
+ ! 	usb_nop_xceiv_register(musb->id);
+ ! 	musb->xceiv = otg_get_transceiver(musb->id);
+   	if (!musb->xceiv)
+   		return -ENODEV;
+   
+ ***************
+ *** 1128,1134 ****
+   			iounmap(sync);
+   
+   		otg_put_transceiver(musb->xceiv);
+ ! 		usb_nop_xceiv_unregister();
+   	}
+   	return ret;
+   }
+ --- 1130,1136 ----
+   			iounmap(sync);
+   
+   		otg_put_transceiver(musb->xceiv);
+ ! 		usb_nop_xceiv_unregister(musb->id);
+   	}
+   	return ret;
+   }
+ ***************
+ *** 1144,1154 ****
+   	iounmap(musb->sync_va);
+   
+   	otg_put_transceiver(musb->xceiv);
+ ! 	usb_nop_xceiv_unregister();
+   	return 0;
+   }
+   
+   static const struct musb_platform_ops tusb_ops = {
+   	.init		= tusb_musb_init,
+   	.exit		= tusb_musb_exit,
+   
+ --- 1146,1159 ----
+   	iounmap(musb->sync_va);
+   
+   	otg_put_transceiver(musb->xceiv);
+ ! 	usb_nop_xceiv_unregister(musb->id);
+   	return 0;
+   }
+   
+   static const struct musb_platform_ops tusb_ops = {
+ + 	.fifo_mode	= 4,
+ + 	.flags		= MUSB_GLUE_TUSB_STYLE |
+ + 				MUSB_GLUE_EP_ADDR_INDEXED_MAPPING,
+   	.init		= tusb_musb_init,
+   	.exit		= tusb_musb_exit,
+   
+ ***************
+ *** 1158,1165 ****
+ --- 1163,1177 ----
+   	.set_mode	= tusb_musb_set_mode,
+   	.try_idle	= tusb_musb_try_idle,
+   
+ + 	.get_hw_revision	= tusb_get_revision,
+ + 
+   	.vbus_status	= tusb_musb_vbus_status,
+   	.set_vbus	= tusb_musb_set_vbus,
+ + 	.read_fifo	= tusb_musb_read_fifo,
+ + 	.write_fifo	= tusb_musb_write_fifo,
+ + 
+ + 	.dma_controller_create = tusb_dma_controller_create,
+ + 	.dma_controller_destroy = tusb_dma_controller_destroy,
+   };
+   
+   static u64 tusb_dmamask = DMA_BIT_MASK(32);
+ diff -crN linux-3.2.1_o/drivers/usb/musb/tusb6010.h linux-3.2.1/drivers/usb/musb/tusb6010.h
+ *** linux-3.2.1_o/drivers/usb/musb/tusb6010.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/musb/tusb6010.h	2014-11-25 13:19:16.704103655 +0900
+ ***************
+ *** 12,31 ****
+   #ifndef __TUSB6010_H__
+   #define __TUSB6010_H__
+   
+ - extern u8 tusb_get_revision(struct musb *musb);
+ - 
+ - #ifdef CONFIG_USB_TUSB6010
+ - #define musb_in_tusb()			1
+ - #else
+ - #define musb_in_tusb()			0
+ - #endif
+ - 
+ - #ifdef CONFIG_USB_TUSB_OMAP_DMA
+ - #define tusb_dma_omap()			1
+ - #else
+ - #define tusb_dma_omap()			0
+ - #endif
+ - 
+   /* VLYNQ control register. 32-bit at offset 0x000 */
+   #define TUSB_VLYNQ_CTRL			0x004
+   
+ --- 12,17 ----
+ diff -crN linux-3.2.1_o/drivers/usb/musb/tusb6010_omap.c linux-3.2.1/drivers/usb/musb/tusb6010_omap.c
+ *** linux-3.2.1_o/drivers/usb/musb/tusb6010_omap.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/musb/tusb6010_omap.c	2014-11-25 13:19:16.708081047 +0900
+ ***************
+ *** 178,189 ****
+   			dma_unmap_single(dev, chdat->dma_addr,
+   						chdat->transfer_len,
+   						DMA_TO_DEVICE);
+ ! 			musb_write_fifo(hw_ep, pio, buf);
+   		} else {
+   			dma_unmap_single(dev, chdat->dma_addr,
+   						chdat->transfer_len,
+   						DMA_FROM_DEVICE);
+ ! 			musb_read_fifo(hw_ep, pio, buf);
+   		}
+   		channel->actual_len += pio;
+   	}
+ --- 178,189 ----
+   			dma_unmap_single(dev, chdat->dma_addr,
+   						chdat->transfer_len,
+   						DMA_TO_DEVICE);
+ ! 			musb->ops->write_fifo(hw_ep, pio, buf);
+   		} else {
+   			dma_unmap_single(dev, chdat->dma_addr,
+   						chdat->transfer_len,
+   						DMA_FROM_DEVICE);
+ ! 			musb->ops->read_fifo(hw_ep, pio, buf);
+   		}
+   		channel->actual_len += pio;
+   	}
+ ***************
+ *** 211,217 ****
+   
+   		if (chdat->tx) {
+   			dev_dbg(musb->controller, "terminating short tx packet\n");
+ ! 			musb_ep_select(mbase, chdat->epnum);
+   			csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
+   			csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY
+   				| MUSB_TXCSR_P_WZC_BITS;
+ --- 211,217 ----
+   
+   		if (chdat->tx) {
+   			dev_dbg(musb->controller, "terminating short tx packet\n");
+ ! 			musb_ep_select(musb, mbase, chdat->epnum);
+   			csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
+   			csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY
+   				| MUSB_TXCSR_P_WZC_BITS;
+ ***************
+ *** 386,399 ****
+   	 * Prepare MUSB for DMA transfer
+   	 */
+   	if (chdat->tx) {
+ ! 		musb_ep_select(mbase, chdat->epnum);
+   		csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
+   		csr |= (MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB
+   			| MUSB_TXCSR_DMAMODE | MUSB_TXCSR_MODE);
+   		csr &= ~MUSB_TXCSR_P_UNDERRUN;
+   		musb_writew(hw_ep->regs, MUSB_TXCSR, csr);
+   	} else {
+ ! 		musb_ep_select(mbase, chdat->epnum);
+   		csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
+   		csr |= MUSB_RXCSR_DMAENAB;
+   		csr &= ~(MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAMODE);
+ --- 386,399 ----
+   	 * Prepare MUSB for DMA transfer
+   	 */
+   	if (chdat->tx) {
+ ! 		musb_ep_select(musb, mbase, chdat->epnum);
+   		csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
+   		csr |= (MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB
+   			| MUSB_TXCSR_DMAMODE | MUSB_TXCSR_MODE);
+   		csr &= ~MUSB_TXCSR_P_UNDERRUN;
+   		musb_writew(hw_ep->regs, MUSB_TXCSR, csr);
+   	} else {
+ ! 		musb_ep_select(musb, mbase, chdat->epnum);
+   		csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
+   		csr |= MUSB_RXCSR_DMAENAB;
+   		csr &= ~(MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAMODE);
+ ***************
+ *** 642,648 ****
+   	channel = NULL;
+   }
+   
+ ! void dma_controller_destroy(struct dma_controller *c)
+   {
+   	struct tusb_omap_dma	*tusb_dma;
+   	int			i;
+ --- 642,648 ----
+   	channel = NULL;
+   }
+   
+ ! void tusb_dma_controller_destroy(struct dma_controller *c)
+   {
+   	struct tusb_omap_dma	*tusb_dma;
+   	int			i;
+ ***************
+ *** 661,669 ****
+   
+   	kfree(tusb_dma);
+   }
+   
+ ! struct dma_controller *__init
+ ! dma_controller_create(struct musb *musb, void __iomem *base)
+   {
+   	void __iomem		*tbase = musb->ctrl_base;
+   	struct tusb_omap_dma	*tusb_dma;
+ --- 661,670 ----
+   
+   	kfree(tusb_dma);
+   }
+ + EXPORT_SYMBOL(tusb_dma_controller_destroy);
+   
+ ! struct dma_controller *__devinit
+ ! tusb_dma_controller_create(struct musb *musb, void __iomem *base)
+   {
+   	void __iomem		*tbase = musb->ctrl_base;
+   	struct tusb_omap_dma	*tusb_dma;
+ ***************
+ *** 697,703 ****
+   	tusb_dma->controller.channel_program = tusb_omap_dma_program;
+   	tusb_dma->controller.channel_abort = tusb_omap_dma_abort;
+   
+ ! 	if (tusb_get_revision(musb) >= TUSB_REV_30)
+   		tusb_dma->multichannel = 1;
+   
+   	for (i = 0; i < MAX_DMAREQ; i++) {
+ --- 698,704 ----
+   	tusb_dma->controller.channel_program = tusb_omap_dma_program;
+   	tusb_dma->controller.channel_abort = tusb_omap_dma_abort;
+   
+ ! 	if (musb_platform_get_hw_revision(musb) >= TUSB_REV_30)
+   		tusb_dma->multichannel = 1;
+   
+   	for (i = 0; i < MAX_DMAREQ; i++) {
+ ***************
+ *** 721,727 ****
+   	return &tusb_dma->controller;
+   
+   cleanup:
+ ! 	dma_controller_destroy(&tusb_dma->controller);
+   out:
+   	return NULL;
+   }
+ --- 722,743 ----
+   	return &tusb_dma->controller;
+   
+   cleanup:
+ ! 	tusb_dma_controller_destroy(&tusb_dma->controller);
+   out:
+   	return NULL;
+   }
+ + EXPORT_SYMBOL(tusb_dma_controller_create);
+ + 
+ + MODULE_DESCRIPTION("TUSB dma controller driver for musb");
+ + MODULE_LICENSE("GPL v2");
+ + 
+ + static int __init tusb_dma_init(void)
+ + {
+ + 	return 0;
+ + }
+ + module_init(tusb_dma_init);
+ + 
+ + static void __exit tusb_dma__exit(void)
+ + {
+ + }
+ + module_exit(tusb_dma__exit);
+ diff -crN linux-3.2.1_o/drivers/usb/musb/ux500.c linux-3.2.1/drivers/usb/musb/ux500.c
+ *** linux-3.2.1_o/drivers/usb/musb/ux500.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/musb/ux500.c	2014-11-25 13:19:16.711078000 +0900
+ ***************
+ *** 54,59 ****
+ --- 54,60 ----
+   }
+   
+   static const struct musb_platform_ops ux500_ops = {
+ + 	.fifo_mode	= 5,
+   	.init		= ux500_musb_init,
+   	.exit		= ux500_musb_exit,
+   };
+ diff -crN linux-3.2.1_o/drivers/usb/musb/ux500_dma.c linux-3.2.1/drivers/usb/musb/ux500_dma.c
+ *** linux-3.2.1_o/drivers/usb/musb/ux500_dma.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/musb/ux500_dma.c	2014-11-25 13:19:16.716060610 +0900
+ ***************
+ *** 37,43 ****
+   	struct dma_channel channel;
+   	struct ux500_dma_controller *controller;
+   	struct musb_hw_ep *hw_ep;
+ - 	struct work_struct channel_work;
+   	struct dma_chan *dma_chan;
+   	unsigned int cur_len;
+   	dma_cookie_t cookie;
+ --- 37,42 ----
+ ***************
+ *** 56,86 ****
+   	dma_addr_t phy_base;
+   };
+   
+ - /* Work function invoked from DMA callback to handle tx transfers. */
+ - static void ux500_tx_work(struct work_struct *data)
+ - {
+ - 	struct ux500_dma_channel *ux500_channel = container_of(data,
+ - 		struct ux500_dma_channel, channel_work);
+ - 	struct musb_hw_ep       *hw_ep = ux500_channel->hw_ep;
+ - 	struct musb *musb = hw_ep->musb;
+ - 	unsigned long flags;
+ - 
+ - 	dev_dbg(musb->controller, "DMA tx transfer done on hw_ep=%d\n",
+ - 		hw_ep->epnum);
+ - 
+ - 	spin_lock_irqsave(&musb->lock, flags);
+ - 	ux500_channel->channel.actual_len = ux500_channel->cur_len;
+ - 	ux500_channel->channel.status = MUSB_DMA_STATUS_FREE;
+ - 	musb_dma_completion(musb, hw_ep->epnum,
+ - 				ux500_channel->is_tx);
+ - 	spin_unlock_irqrestore(&musb->lock, flags);
+ - }
+ - 
+   /* Work function invoked from DMA callback to handle rx transfers. */
+ ! static void ux500_rx_work(struct work_struct *data)
+   {
+ ! 	struct ux500_dma_channel *ux500_channel = container_of(data,
+ ! 		struct ux500_dma_channel, channel_work);
+   	struct musb_hw_ep       *hw_ep = ux500_channel->hw_ep;
+   	struct musb *musb = hw_ep->musb;
+   	unsigned long flags;
+ --- 55,65 ----
+   	dma_addr_t phy_base;
+   };
+   
+   /* Work function invoked from DMA callback to handle rx transfers. */
+ ! void ux500_dma_callback(void *private_data)
+   {
+ ! 	struct dma_channel *channel = private_data;
+ ! 	struct ux500_dma_channel *ux500_channel = channel->private_data;
+   	struct musb_hw_ep       *hw_ep = ux500_channel->hw_ep;
+   	struct musb *musb = hw_ep->musb;
+   	unsigned long flags;
+ ***************
+ *** 94,107 ****
+   	musb_dma_completion(musb, hw_ep->epnum,
+   		ux500_channel->is_tx);
+   	spin_unlock_irqrestore(&musb->lock, flags);
+ - }
+ - 
+ - void ux500_dma_callback(void *private_data)
+ - {
+ - 	struct dma_channel *channel = (struct dma_channel *)private_data;
+ - 	struct ux500_dma_channel *ux500_channel = channel->private_data;
+   
+ - 	schedule_work(&ux500_channel->channel_work);
+   }
+   
+   static bool ux500_configure_channel(struct dma_channel *channel,
+ --- 73,79 ----
+ ***************
+ *** 330,336 ****
+   	void **param_array;
+   	struct ux500_dma_channel *channel_array;
+   	u32 ch_count;
+ - 	void (*musb_channel_work)(struct work_struct *);
+   	dma_cap_mask_t mask;
+   
+   	if ((data->num_rx_channels > UX500_MUSB_DMA_NUM_RX_CHANNELS) ||
+ --- 302,307 ----
+ ***************
+ *** 347,353 ****
+   	channel_array = controller->rx_channel;
+   	ch_count = data->num_rx_channels;
+   	param_array = data->dma_rx_param_array;
+ - 	musb_channel_work = ux500_rx_work;
+   
+   	for (dir = 0; dir < 2; dir++) {
+   		for (ch_num = 0; ch_num < ch_count; ch_num++) {
+ --- 318,323 ----
+ ***************
+ *** 374,388 ****
+   				return -EBUSY;
+   			}
+   
+ - 			INIT_WORK(&ux500_channel->channel_work,
+ - 				musb_channel_work);
+   		}
+   
+   		/* Prepare the loop for TX channels */
+   		channel_array = controller->tx_channel;
+   		ch_count = data->num_tx_channels;
+   		param_array = data->dma_tx_param_array;
+ - 		musb_channel_work = ux500_tx_work;
+   		is_tx = 1;
+   	}
+   
+ --- 344,355 ----
+ diff -crN linux-3.2.1_o/drivers/usb/otg/nop-usb-xceiv.c linux-3.2.1/drivers/usb/otg/nop-usb-xceiv.c
+ *** linux-3.2.1_o/drivers/usb/otg/nop-usb-xceiv.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/otg/nop-usb-xceiv.c	2014-11-25 13:19:16.719526353 +0900
+ ***************
+ *** 37,60 ****
+   	struct device		*dev;
+   };
+   
+ ! static struct platform_device *pd;
+   
+ ! void usb_nop_xceiv_register(void)
+   {
+ ! 	if (pd)
+   		return;
+ ! 	pd = platform_device_register_simple("nop_usb_xceiv", -1, NULL, 0);
+ ! 	if (!pd) {
+   		printk(KERN_ERR "Unable to register usb nop transceiver\n");
+   		return;
+   	}
+   }
+   EXPORT_SYMBOL(usb_nop_xceiv_register);
+   
+ ! void usb_nop_xceiv_unregister(void)
+   {
+ ! 	platform_device_unregister(pd);
+ ! 	pd = NULL;
+   }
+   EXPORT_SYMBOL(usb_nop_xceiv_unregister);
+   
+ --- 37,60 ----
+   	struct device		*dev;
+   };
+   
+ ! static struct platform_device *pd[2] = {NULL, NULL};
+   
+ ! void usb_nop_xceiv_register(int id)
+   {
+ ! 	if (pd[id])
+   		return;
+ ! 	pd[id] = platform_device_register_simple("nop_usb_xceiv", id, NULL, 0);
+ ! 	if (!pd[id]) {
+   		printk(KERN_ERR "Unable to register usb nop transceiver\n");
+   		return;
+   	}
+   }
+   EXPORT_SYMBOL(usb_nop_xceiv_register);
+   
+ ! void usb_nop_xceiv_unregister(int id)
+   {
+ ! 	platform_device_unregister(pd[id]);
+ ! 	pd[id] = NULL;
+   }
+   EXPORT_SYMBOL(usb_nop_xceiv_unregister);
+   
+ ***************
+ *** 122,127 ****
+ --- 122,128 ----
+   	nop->otg.set_host	= nop_set_host;
+   	nop->otg.set_peripheral	= nop_set_peripheral;
+   	nop->otg.set_suspend	= nop_set_suspend;
+ + 	nop->otg.id		= pdev->id;
+   
+   	err = otg_set_transceiver(&nop->otg);
+   	if (err) {
+ ***************
+ *** 144,150 ****
+   {
+   	struct nop_usb_xceiv *nop = platform_get_drvdata(pdev);
+   
+ ! 	otg_set_transceiver(NULL);
+   
+   	platform_set_drvdata(pdev, NULL);
+   	kfree(nop);
+ --- 145,151 ----
+   {
+   	struct nop_usb_xceiv *nop = platform_get_drvdata(pdev);
+   
+ ! 	otg_reset_transceiver(&nop->otg);
+   
+   	platform_set_drvdata(pdev, NULL);
+   	kfree(nop);
+ diff -crN linux-3.2.1_o/drivers/usb/otg/otg.c linux-3.2.1/drivers/usb/otg/otg.c
+ *** linux-3.2.1_o/drivers/usb/otg/otg.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/otg/otg.c	2014-11-25 13:19:16.719526353 +0900
+ ***************
+ *** 15,21 ****
+   
+   #include <linux/usb/otg.h>
+   
+ ! static struct otg_transceiver *xceiv;
+   
+   /**
+    * otg_get_transceiver - find the (single) OTG transceiver
+ --- 15,21 ----
+   
+   #include <linux/usb/otg.h>
+   
+ ! static struct otg_transceiver *xceiv[2];
+   
+   /**
+    * otg_get_transceiver - find the (single) OTG transceiver
+ ***************
+ *** 26,36 ****
+    *
+    * For use by USB host and peripheral drivers.
+    */
+ ! struct otg_transceiver *otg_get_transceiver(void)
+   {
+ ! 	if (xceiv)
+ ! 		get_device(xceiv->dev);
+ ! 	return xceiv;
+   }
+   EXPORT_SYMBOL(otg_get_transceiver);
+   
+ --- 26,36 ----
+    *
+    * For use by USB host and peripheral drivers.
+    */
+ ! struct otg_transceiver *otg_get_transceiver(int id)
+   {
+ ! 	if (xceiv[id])
+ ! 		get_device(xceiv[id]->dev);
+ ! 	return xceiv[id];
+   }
+   EXPORT_SYMBOL(otg_get_transceiver);
+   
+ ***************
+ *** 59,71 ****
+    */
+   int otg_set_transceiver(struct otg_transceiver *x)
+   {
+ ! 	if (xceiv && x)
+   		return -EBUSY;
+ ! 	xceiv = x;
+   	return 0;
+   }
+   EXPORT_SYMBOL(otg_set_transceiver);
+   
+   const char *otg_state_string(enum usb_otg_state state)
+   {
+   	switch (state) {
+ --- 59,88 ----
+    */
+   int otg_set_transceiver(struct otg_transceiver *x)
+   {
+ ! 	if ( x && xceiv[x->id])
+   		return -EBUSY;
+ ! 	xceiv[x->id] = x;
+   	return 0;
+   }
+   EXPORT_SYMBOL(otg_set_transceiver);
+   
+ + 
+ + /**
+ +  * otg_set_transceiver - declare the (single) OTG transceiver
+ +  * @x: the USB OTG transceiver to be used; or NULL
+ +  *
+ +  * This call is exclusively for use by transceiver drivers, which
+ +  * coordinate the activities of drivers for host and peripheral
+ +  * controllers, and in some cases for VBUS current regulation.
+ +  */
+ + int otg_reset_transceiver(struct otg_transceiver *x)
+ + {
+ + 	if (x && xceiv[x->id])
+ + 		xceiv[x->id] = NULL;
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(otg_reset_transceiver);
+ + 
+   const char *otg_state_string(enum usb_otg_state state)
+   {
+   	switch (state) {
+ diff -crN linux-3.2.1_o/drivers/usb/renesas_usbhs/mod_gadget.c linux-3.2.1/drivers/usb/renesas_usbhs/mod_gadget.c
+ *** linux-3.2.1_o/drivers/usb/renesas_usbhs/mod_gadget.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/renesas_usbhs/mod_gadget.c	2014-11-25 13:19:16.719526353 +0900
+ ***************
+ *** 755,761 ****
+   
+   	if (!driver		||
+   	    !driver->setup	||
+ ! 	    driver->speed < USB_SPEED_FULL)
+   		return -EINVAL;
+   
+   	/* first hook up the driver ... */
+ --- 755,761 ----
+   
+   	if (!driver		||
+   	    !driver->setup	||
+ ! 	    driver->max_speed < USB_SPEED_FULL)
+   		return -EINVAL;
+   
+   	/* first hook up the driver ... */
+ ***************
+ *** 866,872 ****
+   	gpriv->gadget.dev.parent	= dev;
+   	gpriv->gadget.name		= "renesas_usbhs_udc";
+   	gpriv->gadget.ops		= &usbhsg_gadget_ops;
+ ! 	gpriv->gadget.is_dualspeed	= 1;
+   	ret = device_register(&gpriv->gadget.dev);
+   	if (ret < 0)
+   		goto err_add_udc;
+ --- 866,872 ----
+   	gpriv->gadget.dev.parent	= dev;
+   	gpriv->gadget.name		= "renesas_usbhs_udc";
+   	gpriv->gadget.ops		= &usbhsg_gadget_ops;
+ ! 	gpriv->gadget.max_speed		= USB_SPEED_HIGH;
+   	ret = device_register(&gpriv->gadget.dev);
+   	if (ret < 0)
+   		goto err_add_udc;
+ diff -crN linux-3.2.1_o/drivers/usb/serial/cp210x.c linux-3.2.1/drivers/usb/serial/cp210x.c
+ *** linux-3.2.1_o/drivers/usb/serial/cp210x.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/serial/cp210x.c	2014-11-25 13:19:16.719526353 +0900
+ ***************
+ *** 92,98 ****
+   	{ USB_DEVICE(0x10C4, 0x818B) }, /* AVIT Research USB to TTL */
+   	{ USB_DEVICE(0x10C4, 0x819F) }, /* MJS USB Toslink Switcher */
+   	{ USB_DEVICE(0x10C4, 0x81A6) }, /* ThinkOptics WavIt */
+ - 	{ USB_DEVICE(0x10C4, 0x81A9) }, /* Multiplex RC Interface */
+   	{ USB_DEVICE(0x10C4, 0x81AC) }, /* MSD Dash Hawk */
+   	{ USB_DEVICE(0x10C4, 0x81AD) }, /* INSYS USB Modem */
+   	{ USB_DEVICE(0x10C4, 0x81C8) }, /* Lipowsky Industrie Elektronik GmbH, Baby-JTAG */
+ --- 92,97 ----
+ diff -crN linux-3.2.1_o/drivers/usb/serial/omninet.c linux-3.2.1/drivers/usb/serial/omninet.c
+ *** linux-3.2.1_o/drivers/usb/serial/omninet.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/serial/omninet.c	2014-11-25 13:19:16.723712707 +0900
+ ***************
+ *** 315,321 ****
+   	int room = 0; /* Default: no room */
+   
+   	/* FIXME: no consistent locking for write_urb_busy */
+ ! 	if (!wport->write_urb_busy)
+   		room = wport->bulk_out_size - OMNINET_HEADERLEN;
+   
+   	dbg("%s - returns %d", __func__, room);
+ --- 315,321 ----
+   	int room = 0; /* Default: no room */
+   
+   	/* FIXME: no consistent locking for write_urb_busy */
+ ! 	if (wport->write_urb_busy)
+   		room = wport->bulk_out_size - OMNINET_HEADERLEN;
+   
+   	dbg("%s - returns %d", __func__, room);
+ diff -crN linux-3.2.1_o/drivers/usb/serial/option.c linux-3.2.1/drivers/usb/serial/option.c
+ *** linux-3.2.1_o/drivers/usb/serial/option.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/serial/option.c	2014-11-25 13:19:16.723712707 +0900
+ ***************
+ *** 476,485 ****
+   #define VIETTEL_VENDOR_ID			0x2262
+   #define VIETTEL_PRODUCT_VT1000			0x0002
+   
+ - /* ZD Incorporated */
+ - #define ZD_VENDOR_ID				0x0685
+ - #define ZD_PRODUCT_7000				0x7000
+ - 
+   /* some devices interfaces need special handling due to a number of reasons */
+   enum option_blacklist_reason {
+   		OPTION_BLACKLIST_NONE = 0,
+ --- 476,481 ----
+ ***************
+ *** 1182,1188 ****
+   	{ USB_DEVICE(YUGA_VENDOR_ID, YUGA_PRODUCT_CLU528) },
+   	{ USB_DEVICE(YUGA_VENDOR_ID, YUGA_PRODUCT_CLU526) },
+   	{ USB_DEVICE_AND_INTERFACE_INFO(VIETTEL_VENDOR_ID, VIETTEL_PRODUCT_VT1000, 0xff, 0xff, 0xff) },
+ - 	{ USB_DEVICE_AND_INTERFACE_INFO(ZD_VENDOR_ID, ZD_PRODUCT_7000, 0xff, 0xff, 0xff) },
+   	{ } /* Terminating entry */
+   };
+   MODULE_DEVICE_TABLE(usb, option_ids);
+ --- 1178,1183 ----
+ diff -crN linux-3.2.1_o/drivers/usb/storage/usb.c linux-3.2.1/drivers/usb/storage/usb.c
+ *** linux-3.2.1_o/drivers/usb/storage/usb.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/usb/storage/usb.c	2014-11-25 13:19:16.728102306 +0900
+ ***************
+ *** 1073,1079 ****
+   	.id_table =	usb_storage_usb_ids,
+   	.supports_autosuspend = 1,
+   	.soft_unbind =	1,
+ - 	.no_dynamic_id = 1,
+   };
+   
+   static int __init usb_stor_init(void)
+ --- 1073,1078 ----
+ diff -crN linux-3.2.1_o/drivers/video/backlight/Kconfig linux-3.2.1/drivers/video/backlight/Kconfig
+ *** linux-3.2.1_o/drivers/video/backlight/Kconfig	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/video/backlight/Kconfig	2014-11-25 13:19:16.743469138 +0900
+ ***************
+ *** 342,347 ****
+ --- 342,355 ----
+   	  If you have a AnalogicTech AAT2870 say Y to enable the
+   	  backlight driver.
+   
+ + config BACKLIGHT_TLC59108
+ + 	tristate "TLC59108 LCD Backlight Driver"
+ + 	depends on I2C && BACKLIGHT_CLASS_DEVICE
+ + 	default n
+ + 	help
+ + 	  If you have an LCD Panel with backlight control via TLC59108,
+ + 	  say Y to enable its LCD control driver.
+ + 
+   endif # BACKLIGHT_CLASS_DEVICE
+   
+   endif # BACKLIGHT_LCD_SUPPORT
+ diff -crN linux-3.2.1_o/drivers/video/backlight/Makefile linux-3.2.1/drivers/video/backlight/Makefile
+ *** linux-3.2.1_o/drivers/video/backlight/Makefile	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/video/backlight/Makefile	2014-11-25 13:19:16.752094438 +0900
+ ***************
+ *** 39,42 ****
+ --- 39,43 ----
+   obj-$(CONFIG_BACKLIGHT_88PM860X) += 88pm860x_bl.o
+   obj-$(CONFIG_BACKLIGHT_PCF50633)	+= pcf50633-backlight.o
+   obj-$(CONFIG_BACKLIGHT_AAT2870) += aat2870_bl.o
+ + obj-$(CONFIG_BACKLIGHT_TLC59108)	+= tlc59108.o
+   
+ diff -crN linux-3.2.1_o/drivers/video/backlight/pwm_bl.c linux-3.2.1/drivers/video/backlight/pwm_bl.c
+ *** linux-3.2.1_o/drivers/video/backlight/pwm_bl.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/video/backlight/pwm_bl.c	2014-11-25 13:19:16.793893140 +0900
+ ***************
+ *** 17,23 ****
+   #include <linux/fb.h>
+   #include <linux/backlight.h>
+   #include <linux/err.h>
+ ! #include <linux/pwm.h>
+   #include <linux/pwm_backlight.h>
+   #include <linux/slab.h>
+   
+ --- 17,23 ----
+   #include <linux/fb.h>
+   #include <linux/backlight.h>
+   #include <linux/err.h>
+ ! #include <linux/pwm/pwm.h>
+   #include <linux/pwm_backlight.h>
+   #include <linux/slab.h>
+   
+ ***************
+ *** 49,61 ****
+   		brightness = pb->notify(pb->dev, brightness);
+   
+   	if (brightness == 0) {
+ ! 		pwm_config(pb->pwm, 0, pb->period);
+ ! 		pwm_disable(pb->pwm);
+   	} else {
+   		brightness = pb->lth_brightness +
+   			(brightness * (pb->period - pb->lth_brightness) / max);
+ ! 		pwm_config(pb->pwm, brightness, pb->period);
+ ! 		pwm_enable(pb->pwm);
+   	}
+   
+   	if (pb->notify_after)
+ --- 49,62 ----
+   		brightness = pb->notify(pb->dev, brightness);
+   
+   	if (brightness == 0) {
+ ! 		pwm_set_duty_ns(pb->pwm, 0);
+ ! 		pwm_stop(pb->pwm);
+   	} else {
+   		brightness = pb->lth_brightness +
+   			(brightness * (pb->period - pb->lth_brightness) / max);
+ ! 		pwm_set_period_ns(pb->pwm, pb->period);
+ ! 		pwm_set_duty_ns(pb->pwm, brightness);
+ ! 		pwm_start(pb->pwm);
+   	}
+   
+   	if (pb->notify_after)
+ ***************
+ *** 117,123 ****
+   		(data->pwm_period_ns / data->max_brightness);
+   	pb->dev = &pdev->dev;
+   
+ ! 	pb->pwm = pwm_request(data->pwm_id, "backlight");
+   	if (IS_ERR(pb->pwm)) {
+   		dev_err(&pdev->dev, "unable to request PWM for backlight\n");
+   		ret = PTR_ERR(pb->pwm);
+ --- 118,124 ----
+   		(data->pwm_period_ns / data->max_brightness);
+   	pb->dev = &pdev->dev;
+   
+ ! 	pb->pwm = pwm_request(data->pwm_id, data->ch, "backlight");
+   	if (IS_ERR(pb->pwm)) {
+   		dev_err(&pdev->dev, "unable to request PWM for backlight\n");
+   		ret = PTR_ERR(pb->pwm);
+ ***************
+ *** 143,149 ****
+   	return 0;
+   
+   err_bl:
+ ! 	pwm_free(pb->pwm);
+   err_pwm:
+   	kfree(pb);
+   err_alloc:
+ --- 144,150 ----
+   	return 0;
+   
+   err_bl:
+ ! 	pwm_release(pb->pwm);
+   err_pwm:
+   	kfree(pb);
+   err_alloc:
+ ***************
+ *** 159,167 ****
+   	struct pwm_bl_data *pb = dev_get_drvdata(&bl->dev);
+   
+   	backlight_device_unregister(bl);
+ ! 	pwm_config(pb->pwm, 0, pb->period);
+ ! 	pwm_disable(pb->pwm);
+ ! 	pwm_free(pb->pwm);
+   	kfree(pb);
+   	if (data->exit)
+   		data->exit(&pdev->dev);
+ --- 160,168 ----
+   	struct pwm_bl_data *pb = dev_get_drvdata(&bl->dev);
+   
+   	backlight_device_unregister(bl);
+ ! 	pwm_set_duty_ns(pb->pwm, 0);
+ ! 	pwm_stop(pb->pwm);
+ ! 	pwm_release(pb->pwm);
+   	kfree(pb);
+   	if (data->exit)
+   		data->exit(&pdev->dev);
+ ***************
+ *** 177,186 ****
+   
+   	if (pb->notify)
+   		pb->notify(pb->dev, 0);
+ ! 	pwm_config(pb->pwm, 0, pb->period);
+ ! 	pwm_disable(pb->pwm);
+ ! 	if (pb->notify_after)
+ ! 		pb->notify_after(pb->dev, 0);
+   	return 0;
+   }
+   
+ --- 178,185 ----
+   
+   	if (pb->notify)
+   		pb->notify(pb->dev, 0);
+ ! 	pwm_set_duty_ns(pb->pwm, 0);
+ ! 	pwm_stop(pb->pwm);
+   	return 0;
+   }
+   
+ diff -crN linux-3.2.1_o/drivers/video/backlight/tlc59108.c linux-3.2.1/drivers/video/backlight/tlc59108.c
+ *** linux-3.2.1_o/drivers/video/backlight/tlc59108.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/drivers/video/backlight/tlc59108.c	2014-11-25 13:19:16.797129034 +0900
+ ***************
+ *** 0 ****
+ --- 1,170 ----
+ + /*
+ +  * ti81xxhdmi_tlc59108.c
+ +  *
+ +  * Copyright (C) 2011 Texas Instruments
+ +  * Author: Senthil Natarajan
+ +  *
+ +  * tlc59108 HDMI Driver
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify it
+ +  * under the terms of the GNU General Public License version 2 as published by
+ +  * the Free Software Foundation.
+ +  *
+ +  * This program is distributed in the hope that it will be useful, but WITHOUT
+ +  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ +  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ +  * more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License along with
+ +  * this program.  If not, see <http://www.gnu.org/licenses/>.
+ +  * History:
+ +  *
+ +  * Senthil Natarajan<senthil.n@ti.com> July 2011 I2C driver for tlc59108
+ +  *						 backlight control
+ +  */
+ + 
+ + #include <linux/i2c.h>
+ + #include <linux/kernel.h>
+ + #include <linux/module.h>
+ + #include <linux/backlight.h>
+ + #include <linux/fb.h>
+ + 
+ + #define tlc59108_MODULE_NAME	"tlc59108"
+ + #define TLC59108_MODE1   0x00
+ + #define TLC59108_PWM2    0x04
+ + #define TLC59108_LEDOUT0 0x0c
+ + #define TLC59108_LEDOUT1 0x0d
+ + #define TLC59108_MAX_BRIGHTNESS 0xFF
+ + 
+ + struct tlc59108_bl {
+ + 	struct i2c_client *client;
+ + 	struct backlight_device *bl;
+ + };
+ + 
+ + static void tlc59108_bl_set_backlight(struct tlc59108_bl *data, int brightness)
+ + {
+ + 	/* Set Mode1 Register */
+ + 	i2c_smbus_write_byte_data(data->client, TLC59108_MODE1, 0x00);
+ + 
+ + 	/* Set LEDOUT0 Register */
+ + 	i2c_smbus_write_byte_data(data->client, TLC59108_LEDOUT0, 0x21);
+ + 
+ + 	/* Set Backlight Duty Cycle*/
+ + 	i2c_smbus_write_byte_data(data->client, TLC59108_PWM2,
+ + 				  brightness & 0xff);
+ + }
+ + 
+ + static int tlc59108_bl_get_brightness(struct backlight_device *dev)
+ + {
+ + 	struct backlight_properties *props = &dev->props;
+ + 
+ + 	return props->brightness;
+ + }
+ + 
+ + static int tlc59108_bl_update_status(struct backlight_device *dev)
+ + {
+ + 	struct backlight_properties *props = &dev->props;
+ + 	struct tlc59108_bl *data = dev_get_drvdata(&dev->dev);
+ + 	int brightness = props->brightness;
+ + 
+ + 	tlc59108_bl_set_backlight(data, brightness);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + static const struct backlight_ops bl_ops = {
+ + 	.get_brightness		= tlc59108_bl_get_brightness,
+ + 	.update_status		= tlc59108_bl_update_status,
+ + };
+ + 
+ + static int tlc59108_probe(struct i2c_client *c, const struct i2c_device_id *id)
+ + {
+ + 	struct backlight_properties props;
+ + 	struct tlc59108_bl *data = kzalloc(sizeof(struct tlc59108_bl),
+ + 					   GFP_KERNEL);
+ + 	int ret = 0;
+ + 
+ + 	if (!data)
+ + 		return -ENOMEM;
+ + 
+ + 	i2c_set_clientdata(c, data);
+ + 	data->client = c;
+ + 
+ + 	/* FIXME: This is definitely how it should be done.
+ + 	 * Someone more familiar with the framework needs to make it proper
+ + 	 */
+ + 	if (cpu_is_am335x()) {
+ + 		/* Set LED4 to always on in LEDOUT1 Register*/
+ + 		ret = i2c_smbus_write_byte_data(data->client, TLC59108_LEDOUT1, 0x01);
+ + 		if(ret < 0)
+ + 			pr_err("Could not set LED4 to fully on\n");
+ + 	}
+ + 
+ + 	memset(&props, 0, sizeof(struct backlight_properties));
+ + 	props.max_brightness = TLC59108_MAX_BRIGHTNESS;
+ + 	props.type = BACKLIGHT_RAW;
+ + 	data->bl = backlight_device_register("tlc59108-bl", &c->dev, data,
+ + 					     &bl_ops, &props);
+ + 	if (IS_ERR(data->bl)) {
+ + 		ret = PTR_ERR(data->bl);
+ + 		goto err_reg;
+ + 	}
+ + 
+ + 	data->bl->props.brightness = TLC59108_MAX_BRIGHTNESS;
+ + 
+ + 	backlight_update_status(data->bl);
+ + 
+ + 	return 0;
+ + 
+ + err_reg:
+ + 	data->bl = NULL;
+ + 	kfree(data);
+ + 	return ret;
+ + }
+ + 
+ + static int tlc59108_remove(struct i2c_client *c)
+ + {
+ + 	struct tlc59108_bl *data = i2c_get_clientdata(c);
+ + 
+ + 	backlight_device_unregister(data->bl);
+ + 	data->bl = NULL;
+ + 
+ + 	kfree(data);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + /* I2C Device ID table */
+ + static const struct i2c_device_id tlc59108_id[] = {
+ + 	{ "tlc59108", 0 },
+ + 	{ }
+ + };
+ + MODULE_DEVICE_TABLE(i2c, tlc59108_id);
+ + 
+ + /* I2C driver data */
+ + static struct i2c_driver tlc59108_driver = {
+ + 	.driver = {
+ + 		.owner = THIS_MODULE,
+ + 		.name = tlc59108_MODULE_NAME,
+ + 	},
+ + 	.probe = tlc59108_probe,
+ + 	.remove = tlc59108_remove,
+ + 	.id_table = tlc59108_id,
+ + };
+ + 
+ + static int __init tlc59108_init(void)
+ + {
+ + 	return i2c_add_driver(&tlc59108_driver);
+ + }
+ + 
+ + static void __exit tlc59108_exit(void)
+ + {
+ + 	i2c_del_driver(&tlc59108_driver);
+ + }
+ + 
+ + module_init(tlc59108_init);
+ + module_exit(tlc59108_exit);
+ + 
+ + MODULE_DESCRIPTION("LCD/Backlight control for TLC59108");
+ + MODULE_AUTHOR("Senthil Natarajan <senthil.n@ti.com>");
+ + MODULE_LICENSE("GPL v2");
+ diff -crN linux-3.2.1_o/drivers/video/bf54x-lq043fb.c linux-3.2.1/drivers/video/bf54x-lq043fb.c
+ *** linux-3.2.1_o/drivers/video/bf54x-lq043fb.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/video/bf54x-lq043fb.c	2014-11-25 13:19:16.799216168 +0900
+ ***************
+ *** 4,10 ****
+    * Author:       Michael Hennerich <hennerich@blackfin.uclinux.org>
+    *
+    * Created:
+ !  * Description:  ADSP-BF54x Framebufer driver
+    *
+    *
+    * Modified:
+ --- 4,10 ----
+    * Author:       Michael Hennerich <hennerich@blackfin.uclinux.org>
+    *
+    * Created:
+ !  * Description:  ADSP-BF54x Framebuffer driver
+    *
+    *
+    * Modified:
+ diff -crN linux-3.2.1_o/drivers/video/bfin-t350mcqb-fb.c linux-3.2.1/drivers/video/bfin-t350mcqb-fb.c
+ *** linux-3.2.1_o/drivers/video/bfin-t350mcqb-fb.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/video/bfin-t350mcqb-fb.c	2014-11-25 13:19:16.805081678 +0900
+ ***************
+ *** 4,10 ****
+    * Author:       Michael Hennerich <hennerich@blackfin.uclinux.org>
+    *
+    * Created:
+ !  * Description:  Blackfin LCD Framebufer driver
+    *
+    *
+    * Modified:
+ --- 4,10 ----
+    * Author:       Michael Hennerich <hennerich@blackfin.uclinux.org>
+    *
+    * Created:
+ !  * Description:  Blackfin LCD Framebuffer driver
+    *
+    *
+    * Modified:
+ diff -crN linux-3.2.1_o/drivers/video/ckb/ckb_dvi.c linux-3.2.1/drivers/video/ckb/ckb_dvi.c
+ *** linux-3.2.1_o/drivers/video/ckb/ckb_dvi.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/drivers/video/ckb/ckb_dvi.c	2014-11-25 13:19:16.809099059 +0900
+ ***************
+ *** 0 ****
+ --- 1,464 ----
+ + /*
+ +  * CKB DVI driver that uses TFP410 I2C driver
+ +  *
+ +  * Copyright (C) 2013 Computex Co.Ltd.
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; version 2 of the License.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ +  *
+ +  */
+ +  
+ + #include <linux/module.h>
+ + #include <linux/kernel.h>
+ + #include <linux/sched.h>
+ + #include <linux/slab.h>
+ + #include <linux/init.h>
+ + #include <linux/io.h>
+ + #include <linux/fs.h>
+ + #include <linux/clk.h>
+ + #include <linux/err.h>
+ + #include <video/da8xx-fb.h>
+ + #include <linux/platform_device.h>
+ + #include <mach/devices.h>
+ + #include <video/ckb_tfp410.h>
+ + #include <video/ckb_dvi.h>
+ + #include <video/ckb_video_modes.h>
+ + 
+ + #define MAX_EDID			128
+ + 
+ + /* device instance */
+ + static struct class *ckb_dvi_dev_class;
+ + struct ckb_dvi_device *ckb_dvi_dev=NULL;		/* single instance */
+ + 
+ + static int ckb_dvi_open(struct inode *inode, struct file *file)
+ + {
+ + 	if (ckb_dvi_dev == NULL){
+ + 		printk("%s: no device found\n", CKB_DVI_NAME);
+ + 		return -ENODEV;
+ + 	}
+ + 	file->private_data = ckb_dvi_dev;
+ + 	return 0;
+ + }
+ + 
+ + static int ckb_dvi_release(struct inode *inode, struct file *file)
+ + {
+ + 	file->private_data = NULL;
+ + 	return 0;
+ + }
+ + 
+ + static ssize_t ckb_dvi_info_show(struct device *dev, struct device_attribute *attr, char *buf)
+ + {
+ + 	return sprintf(buf, "%s\n", CKB_DVI_NAME);
+ + }
+ + 
+ + static DEVICE_ATTR(ckb_dvi, 0666, ckb_dvi_info_show, NULL);
+ + 
+ + extern unsigned char *fb_do_probe_ddc_edid(struct i2c_adapter *adapter);
+ + u8 *get_edid(struct i2c_adapter *adapter)
+ + {
+ + 	u8 *edid = NULL;
+ + 	int i;
+ + 	/* 3 retries */
+ + 	for (i = 0; i < 3 && !edid; i++) {
+ + 		edid = fb_do_probe_ddc_edid(adapter);
+ + 	}
+ + 	if(!edid)
+ + 		pr_err("Could not read EDID from DVI device\n");
+ + 	return edid;	
+ + }
+ + 
+ + void get_monitor_specs(u8 *edid, struct fb_monspecs *specs)
+ + {
+ + 	fb_edid_to_monspecs(edid, specs);
+ + 	if (edid[126] > 0)
+ + 		fb_edid_add_monspecs(edid + 0x80, specs);
+ + }
+ + 
+ + int get_dvi_info(struct fb_info *info)
+ + {
+ + 	struct i2c_adapter *adapter;
+ + 	struct tfp410_priv *tfp;
+ + 	u8 *edid;
+ + 	if(!ckb_dvi_dev)
+ + 		return 1;
+ + 	
+ + 	adapter = i2c_get_adapter(ckb_dvi_dev->plat_data->i2c_port);
+ + 	if (!adapter) {
+ + 		pr_err("failed to get adapter i2c%u\n", ckb_dvi_dev->plat_data->i2c_port);
+ + 		return 1;
+ + 	}
+ + 	tfp = get_current_tfp410_device();
+ + 	if(!tfp || tfp->tfp410_isconnected() == 0) 
+ + 	{
+ + 		return 1;
+ + 	}
+ + 	edid = get_edid(adapter);
+ + 	if(!edid)
+ + 	{
+ + 		pr_err("Couldn't read EDID from device on adapter i2c%u\n", ckb_dvi_dev->plat_data->i2c_port);
+ + 		return 2;
+ + 	}
+ + 	get_monitor_specs(edid, &info->monspecs);
+ + 	
+ + 	kfree(edid);
+ + 	return 0;	
+ + }
+ + 
+ + EXPORT_SYMBOL(get_dvi_info);
+ + 
+ + void display_resolution(struct fb_videomode *m)
+ + {
+ + #if 0
+ + 	if(m->name)
+ + 		printk("Name: %s ", m->name);
+ + #endif
+ + 	printk("%dx%d Clk: %luMHz (%d picosecs)\n",
+ + 				m->xres, m->yres,
+ + 				PICOS2KHZ(m->pixclock)/1000, m->pixclock);
+ + }
+ + 
+ + int on_dvi_connector_plugged(struct ckb_dvi_device *dev_priv, struct i2c_adapter *adapter)
+ + {
+ + 	struct fb_monspecs *specs;
+ + 	char duplicate[10];
+ + 	struct fb_videomode *m, *temp;
+ + #ifdef CONFIG_DISPLAY_UNSUPPORTED_DVI_RESOLUTIONS
+ + 	int ignored_edid[MAX_EDID];
+ + 	int ignored_count;
+ + #endif
+ + 	unsigned long clockMhz;
+ + 	int max_tot_res;
+ + 	u8 *edid;
+ + 	int i, j;
+ + 
+ + 	printk("DVI device connected. Updating file %s\n", FBSET_DB_FILE);
+ + 	printk("Resolutions upto %dx%d are supported (non-interlaced mode)\n", dev_priv->plat_data->max_xres, dev_priv->plat_data->max_yres);
+ + 	/* include the supported modes in /etc/fb.modes */
+ + 	edid = get_edid(adapter);
+ + 	if(!edid)
+ + 	{
+ + 		printk("DVI: No EDID found\n");
+ + 		return 1;
+ + 	}
+ + 	if(!create_video_mode_file())
+ + 	{
+ + 		return 1;
+ + 	}
+ + 	specs = kzalloc(sizeof(*specs), GFP_KERNEL);
+ + 	if (specs == NULL) {
+ + 		printk("DVI: Failed to allocate memory\n");
+ + 		return 1;
+ + 	}
+ + 	max_tot_res = dev_priv->plat_data->max_yres * dev_priv->plat_data->max_xres;
+ + 	get_monitor_specs(edid, specs);
+ + #ifdef CONFIG_DISPLAY_DVI_RESOLUTIONS
+ +     printk("*** Found the following supported resolutions ***\n");
+ + #endif
+ + #ifdef CONFIG_DISPLAY_UNSUPPORTED_DVI_RESOLUTIONS
+ + 	ignored_count = 0;
+ + #endif
+ + 	for (i=0; i < specs->modedb_len; i++) 
+ + 	{
+ + 		m = &specs->modedb[i];
+ + 		/* donot display unsupported resolution */
+ + 		if (m->pixclock == 0)
+ + 			goto _ignore;
+ + 		/* skip resolutions that are not supported */
+ + 		if (m->xres > dev_priv->plat_data->max_xres || m->yres > dev_priv->plat_data->max_yres)
+ + 			goto _ignore;
+ + 		if ((m->xres * m->yres) > max_tot_res)
+ + 			goto _ignore;
+ + 		if(m->vmode != FB_VMODE_NONINTERLACED)
+ + 			goto _ignore;
+ + 
+ + 		/* check for duplicate modes */
+ + 		duplicate[0] = 0;
+ + 		clockMhz = PICOS2KHZ(m->pixclock)/1000; 
+ + 		for(j=0; j<i; j++)
+ + 		{
+ + 			temp = &specs->modedb[j];
+ + 			if(temp->xres == m->xres && temp->yres == m->yres
+ + 					&& (PICOS2KHZ(temp->pixclock)/1000) == clockMhz)
+ + 			{
+ + 				/* check if it is an exact duplicate */
+ + 				if(temp->pixclock ==  m->pixclock
+ + 					&& temp->left_margin == m->left_margin
+ + 					&& temp->right_margin == m->right_margin
+ + 					&& temp->upper_margin == m->upper_margin
+ + 					&& temp->lower_margin == m->lower_margin
+ + 					&& temp->hsync_len == m->hsync_len
+ + 					&& temp->vsync_len == m->vsync_len
+ + 					&& temp->sync == m->sync)
+ + 				{
+ + 					/* exact duplicate */
+ + 					goto _loop;
+ + 				}
+ + 				sprintf(duplicate, "-%d", i);
+ + 				break;
+ + 			}
+ + 		}
+ + 
+ + #ifdef CONFIG_DISPLAY_DVI_RESOLUTIONS
+ + 		display_resolution(m);
+ + #endif
+ + 		/* write to file */
+ + 		append_video_mode("", m->xres, m->yres, duplicate, clockMhz,
+ + 				m->pixclock, m->left_margin, m->right_margin, m->upper_margin, m->lower_margin,
+ + 				m->hsync_len,  m->vsync_len, m->sync);
+ + 
+ + 		continue;
+ + 
+ + _ignore:
+ + #ifdef CONFIG_DISPLAY_UNSUPPORTED_DVI_RESOLUTIONS
+ + 		ignored_edid[ignored_count++] = i;
+ + #endif
+ + _loop:
+ + 		continue;
+ + 
+ + 	}
+ + 	dev_priv->connector_plugged = 1;
+ + 	append_fb_mode();
+ + 	close_video_mode_file();
+ + #ifdef CONFIG_DISPLAY_DVI_RESOLUTIONS
+ + 	printk("*** End ***\n");
+ + #endif
+ + #ifdef CONFIG_DISPLAY_UNSUPPORTED_DVI_RESOLUTIONS
+ + 	if(ignored_count)
+ + 	{
+ +      	printk("***  Ignored the following resolutions ***\n");
+ + 		for (i=0; i<ignored_count; i++) 
+ + 		{
+ + 			display_resolution(&specs->modedb[ignored_edid[i]]);
+ + 		}
+ + 		printk("*** End ***\n");
+ + 	}
+ + #endif
+ + 	kfree(specs);
+ + 	kfree(edid);
+ + 	return 0;
+ + }
+ + 
+ + void on_dvi_connector_pulled(struct ckb_dvi_device *dev_priv)
+ + {
+ + 	dev_priv->connector_plugged = 0;
+ + 	printk("DVI device disconnected; Updating file %s\n", FBSET_DB_FILE);
+ + 	create_video_mode_file();
+ + 	append_fb_mode();
+ + 	close_video_mode_file();
+ + }
+ + 
+ + /* check the status to determine of the connector is plugged in/out */
+ + static void check_dvi_connector_state(struct work_struct *work)
+ + {
+ + 	struct ckb_dvi_device *dev_priv = container_of(work, struct ckb_dvi_device,
+ + 						    pluggedin_work);
+ + 	volatile int connector_plugged;
+ + 	struct i2c_adapter *adapter;
+ + 	struct tfp410_priv *tfp;
+ + 	adapter = i2c_get_adapter(dev_priv->plat_data->i2c_port);
+ + 	if (!adapter) {
+ + 		pr_err("failed to get adapter i2c%u\n", dev_priv->plat_data->i2c_port);
+ + 		goto _out;
+ + 	}
+ + 	
+ + 	tfp = get_current_tfp410_device();
+ + 	if(tfp)
+ + 		connector_plugged = tfp->tfp410_isconnected()?1:0;
+ + 	else
+ + 	{
+ + 		printk("tfp410 device not found");
+ + 		connector_plugged = 0;
+ + 	}
+ + 	
+ + 	if(connector_plugged != dev_priv->connector_plugged)
+ + 	{
+ + 		if(connector_plugged)
+ + 		{
+ + 			if(on_dvi_connector_plugged(dev_priv, adapter))
+ + 			{
+ + 				goto _out;
+ + 			}
+ + 		}
+ + 		else
+ + 		{
+ + 			on_dvi_connector_pulled(dev_priv);
+ + 		}
+ + 	}
+ + 	
+ + _out:
+ + 	if (mod_timer(&ckb_dvi_dev->pluggedin_timer, jiffies + msecs_to_jiffies(ckb_dvi_dev->plat_data->connect_poll_interval)))
+ + 	{ 
+ + 		printk("%s: Error in timer\n", CKB_DVI_NAME);
+ + 	}
+ + }
+ + 
+ + static void ckb_connector_plugged_timer(unsigned long arg)
+ + {
+ + 	struct ckb_dvi_device *dev_priv = (struct ckb_dvi_device *)arg;
+ + 	queue_work(dev_priv->wq, &dev_priv->pluggedin_work);
+ + }
+ + 
+ + static int __devinit ckb_dvi_probe(struct platform_device *pdev)
+ + {
+ + 	int ret = 0;
+ + 	if(ckb_dvi_dev)
+ + 	{
+ + 		dev_err(&pdev->dev, "%s driver can only be loaded once\n", CKB_DVI_NAME);
+ + 		return -ENODEV;
+ + 	}
+ + 	ckb_dvi_dev = kzalloc(sizeof(struct ckb_dvi_device), GFP_KERNEL);
+ + 	if (ckb_dvi_dev == NULL) {
+ + 		dev_err(&pdev->dev, "failed to allocate memory\n");
+ + 		return -ENOMEM;
+ + 	}
+ + 	if(!pdev->dev.platform_data) {
+ + 		dev_err(&pdev->dev, "Platform data not provided\n");
+ + 		return -ENODEV;
+ + 	}
+ + 
+ + 	ckb_dvi_dev->pdev = pdev;
+ + 	ckb_dvi_dev->plat_data = pdev->dev.platform_data;
+ + 
+ + 	/* register the device with the driver core */
+ + 	ckb_dvi_dev->dev = device_create(ckb_dvi_dev_class, NULL,
+ + 				     MKDEV(CKB_DVI_MAJOR,0), NULL,
+ + 				     CKB_DVI_NAME);
+ + 	if (IS_ERR(ckb_dvi_dev->dev)) {
+ + 		ret = PTR_ERR(ckb_dvi_dev->dev);
+ + 		goto err_free;
+ + 	}
+ + 
+ + 	if (device_create_file(ckb_dvi_dev->dev, &dev_attr_ckb_dvi))
+ + 	{
+ + 		ret = -ENOMEM;
+ + 		goto error_destroy;
+ + 	}
+ + 	platform_set_drvdata(pdev, ckb_dvi_dev);
+ + 
+ + 	/* start a timer to check for the pluggedin event */
+ + 	ckb_dvi_dev->wq = alloc_workqueue("CKB_DVI",
+ + 				       WQ_UNBOUND | WQ_NON_REENTRANT,
+ + 				       1);
+ + 	if (ckb_dvi_dev->wq == NULL) {
+ + 		dev_err(&pdev->dev, "Failed to create workqueue\n");
+ + 		ret = -ENOMEM;
+ + 		goto error_destroy;
+ + 	}
+ + 	
+ + 	ckb_dvi_dev->connector_plugged = 0;
+ + 
+ + 	INIT_WORK(&ckb_dvi_dev->pluggedin_work, check_dvi_connector_state);
+ + 	setup_timer(&ckb_dvi_dev->pluggedin_timer, ckb_connector_plugged_timer,
+ + 		    (unsigned long)ckb_dvi_dev);
+ + 	ret = mod_timer(&ckb_dvi_dev->pluggedin_timer, jiffies + msecs_to_jiffies(ckb_dvi_dev->plat_data->connect_poll_interval));
+ + 	if (ret)
+ + 	{ 
+ + 		dev_err(&pdev->dev, "Error in timer\n");
+ + 		goto error_timer;
+ + 	}
+ + 
+ + 	printk("CKB DVI driver with max resolution %dx%d\n",
+ + 				ckb_dvi_dev->plat_data->max_xres, ckb_dvi_dev->plat_data->max_yres);
+ + 	
+ + 	return 0;
+ + error_timer:
+ + 	destroy_workqueue(ckb_dvi_dev->wq);
+ + 	del_timer(&ckb_dvi_dev->pluggedin_timer);
+ + error_destroy:
+ + 	device_destroy(ckb_dvi_dev_class, MKDEV(CKB_DVI_MAJOR,0));
+ + 	
+ + err_free:
+ + 	kfree(ckb_dvi_dev);
+ + 	ckb_dvi_dev = NULL;
+ + 	dev_err(&pdev->dev, "device not added\n");
+ + 	return ret;
+ + }
+ + 
+ + static int __devexit ckb_dvi_remove(struct platform_device *pdev)
+ + {
+ + 	if (ckb_dvi_dev == NULL)
+ + 		return -ENODEV;
+ + 
+ + 	flush_workqueue(ckb_dvi_dev->wq);
+ + 	destroy_workqueue(ckb_dvi_dev->wq);
+ + 	del_timer(&ckb_dvi_dev->pluggedin_timer);
+ + 
+ + 	device_destroy(ckb_dvi_dev_class, MKDEV(CKB_DVI_MAJOR,0));
+ + 	kfree(ckb_dvi_dev);
+ + 	ckb_dvi_dev = NULL;
+ + 	return 0;
+ + }
+ + 
+ + static const struct file_operations ckb_dvi_fops = {
+ + 	.owner		= THIS_MODULE,
+ + 	.llseek		= no_llseek,
+ + 	.read		= NULL,
+ + 	.write		= NULL,
+ + 	.open		= ckb_dvi_open,
+ + 	.release	= ckb_dvi_release,
+ + };
+ + 
+ + static struct platform_driver ckb_dvi_driver = {
+ + 	.probe		= ckb_dvi_probe,
+ + 	.remove		= __devexit_p(ckb_dvi_remove),
+ + 	.driver		= {
+ + 		.owner	= THIS_MODULE,
+ + 		.name	= CKB_DVI_NAME,
+ + 	},
+ + };
+ + 
+ + static int __init ckb_dvi_init(void)
+ + {
+ + 	int res;
+ + 	res = register_chrdev(CKB_DVI_MAJOR, CKB_DVI_NAME, &ckb_dvi_fops);
+ + 	if (res)
+ + 	{
+ + 		printk(KERN_ERR "%s: Can't create device file\n", __FILE__);
+ + 		goto out;
+ + 	}
+ + 	ckb_dvi_dev_class = class_create(THIS_MODULE, CKB_DVI_NAME);
+ + 	if (IS_ERR(ckb_dvi_dev_class)) {
+ + 		printk(KERN_ERR "%s: Can't create class\n", __FILE__);
+ + 		res = PTR_ERR(ckb_dvi_dev_class);
+ + 		goto out_unreg_chrdev;
+ + 	}
+ + 	res = platform_driver_register(&ckb_dvi_driver);
+ + 	if(res)
+ + 	{
+ + 		printk(KERN_ERR "%s: Can't register driver\n", __FILE__);
+ + 		goto out_unreg_class;
+ + 	}
+ + 	return 0;
+ + 
+ + out_unreg_class:
+ + 	class_destroy(ckb_dvi_dev_class);
+ + out_unreg_chrdev:
+ + 	unregister_chrdev(CKB_DVI_MAJOR, CKB_DVI_NAME);
+ + out:
+ + 	printk(KERN_ERR "%s: Driver Initialization failed\n", __FILE__);
+ + 	return res;	
+ + }
+ + 
+ + static void __exit ckb_dvi_exit(void)
+ + {
+ + 	platform_driver_unregister(&ckb_dvi_driver);
+ + 	class_destroy(ckb_dvi_dev_class);
+ + 	unregister_chrdev(CKB_DVI_MAJOR, CKB_DVI_NAME);
+ + }
+ + 
+ + arch_initcall(ckb_dvi_init);
+ + module_exit(ckb_dvi_exit);
+ + 
+ + MODULE_DESCRIPTION("CKB DVI access driver");
+ + MODULE_AUTHOR("Aiyappa M.S.");
+ + MODULE_LICENSE("GPL");
+ diff -crN linux-3.2.1_o/drivers/video/ckb/ckb_tfp410.c linux-3.2.1/drivers/video/ckb/ckb_tfp410.c
+ *** linux-3.2.1_o/drivers/video/ckb/ckb_tfp410.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/drivers/video/ckb/ckb_tfp410.c	2014-11-25 13:19:16.817125383 +0900
+ ***************
+ *** 0 ****
+ --- 1,361 ----
+ + /*
+ +  * TFP410 I2C driver
+ +  *
+ +  * Copyright (C) 2013 Computex Co.Ltd.
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; version 2 of the License.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ +  *
+ +  */
+ +   
+ + #include <linux/module.h>
+ + #include <linux/slab.h>
+ + #include <linux/i2c.h>
+ + #include <video/ckb_tfp410.h>
+ + 
+ + /* register definitions according to the TFP410 data sheet */
+ + #define TFP410_VID		0x014C
+ + #define TFP410_DID		0x0410
+ + 
+ + #define TFP410_VID_LO		0x00
+ + #define TFP410_VID_HI		0x01
+ + #define TFP410_DID_LO		0x02
+ + #define TFP410_DID_HI		0x03
+ + #define TFP410_REV		0x04
+ + 
+ + #define TFP410_CTL_1		0x08
+ + #define TFP410_CTL_1_TDIS	(1<<6)
+ + #define TFP410_CTL_1_VEN	(1<<5)
+ + #define TFP410_CTL_1_HEN	(1<<4)
+ + #define TFP410_CTL_1_DSEL	(1<<3)
+ + #define TFP410_CTL_1_BSEL	(1<<2)
+ + #define TFP410_CTL_1_EDGE	(1<<1)
+ + #define TFP410_CTL_1_PD		(1<<0)
+ + 
+ + #define TFP410_CTL_2		0x09
+ + #define TFP410_CTL_2_VLOW	(1<<7)
+ + #define TFP410_CTL_2_MSEL_MASK	(0x7<<4)
+ + #define TFP410_CTL_2_MSEL	(1<<4)
+ + #define TFP410_CTL_2_TSEL	(1<<3)
+ + #define TFP410_CTL_2_RSEN	(1<<2)
+ + #define TFP410_CTL_2_HTPLG	(1<<1)
+ + #define TFP410_CTL_2_MDI	(1<<0)
+ + 
+ + #define TFP410_CTL_3		0x0A
+ + #define TFP410_CTL_3_DK_MASK	(0x7<<5)
+ + #define TFP410_CTL_3_DK		(1<<5)
+ + #define TFP410_CTL_3_DKEN	(1<<4)
+ + #define TFP410_CTL_3_CTL_MASK	(0x7<<1)
+ + #define TFP410_CTL_3_CTL	(1<<1)
+ + 
+ + #define TFP410_USERCFG		0x0B
+ + 
+ + #define TFP410_DE_DLY		0x32
+ + 
+ + #define TFP410_DE_CTL		0x33
+ + #define TFP410_DE_CTL_DEGEN	(1<<6)
+ + #define TFP410_DE_CTL_VSPOL	(1<<5)
+ + #define TFP410_DE_CTL_HSPOL	(1<<4)
+ + #define TFP410_DE_CTL_DEDLY8	(1<<0)
+ + 
+ + #define TFP410_DE_TOP		0x34
+ + 
+ + #define TFP410_DE_CNT_LO	0x36
+ + #define TFP410_DE_CNT_HI	0x37
+ + 
+ + #define TFP410_DE_LIN_LO	0x38
+ + #define TFP410_DE_LIN_HI	0x39
+ + 
+ + #define TFP410_H_RES_LO		0x3A
+ + #define TFP410_H_RES_HI		0x3B
+ + 
+ + #define TFP410_V_RES_LO		0x3C
+ + #define TFP410_V_RES_HI		0x3D
+ + 
+ + struct tfp410_priv *cur_ckb_tfp410_device=NULL;
+ + 
+ + struct tfp410_priv *get_current_tfp410_device()
+ + {
+ + 	return cur_ckb_tfp410_device;
+ + }
+ + 	 	
+ + struct i2c_adapter *get_i2c_adapter(void)
+ + {
+ + 	if(cur_ckb_tfp410_device)
+ + 		return cur_ckb_tfp410_device->client->adapter;
+ + 	return 0;
+ + }
+ + 	 	 
+ + bool tfp410_readb(struct i2c_client *client, int addr, uint8_t *ch)
+ + {
+ + 	struct i2c_adapter *adapter = client->adapter;
+ + 	struct tfp410_priv *tfp = i2c_get_clientdata(client);
+ + 	u8 out_buf[2];
+ + 	u8 in_buf[2];
+ + 
+ + 	struct i2c_msg msgs[] = {
+ + 		{
+ + 			.addr = client->addr,
+ + 			.flags = 0,
+ + 			.len = 1,
+ + 			.buf = out_buf,
+ + 		},
+ + 		{
+ + 			.addr = client->addr,
+ + 			.flags = I2C_M_RD,
+ + 			.len = 1,
+ + 			.buf = in_buf,
+ + 		}
+ + 	};
+ + 
+ + 	out_buf[0] = addr;
+ + 	out_buf[1] = 0;
+ + 
+ + 	if (i2c_transfer(adapter, msgs, 2) == 2) {
+ + 		*ch = in_buf[0];
+ + 		return true;
+ + 	};
+ + 
+ + 	dev_err(tfp->dev, "Unable to read register 0x%02x to %s:%d.\n",
+ + 			  addr, adapter->name, client->addr);
+ + 	return false;
+ + }
+ + 
+ + static bool tfp410_writeb(struct i2c_client *client, int addr, uint8_t ch)
+ + {
+ + 	struct tfp410_priv *tfp = i2c_get_clientdata(client);
+ + 	struct i2c_adapter *adapter = client->adapter;
+ + 	uint8_t out_buf[2];
+ + 	struct i2c_msg msg = {
+ + 		.addr = client->addr,
+ + 		.flags = 0,
+ + 		.len = 2,
+ + 		.buf = out_buf,
+ + 	};
+ + 
+ + 	out_buf[0] = addr;
+ + 	out_buf[1] = ch;
+ + 
+ + 	if (i2c_transfer(adapter, &msg, 1) == 1)
+ + 		return true;
+ + 
+ + 	dev_err(tfp->dev, "Unable to write register 0x%02x to %s:%d.\n",
+ + 			  addr, adapter->name, client->addr);
+ + 	
+ + 	return false;
+ + }
+ + 
+ + static bool tfp410_detect(struct i2c_client *client)
+ + {
+ + 	uint8_t ctl2;
+ + 	if (tfp410_readb(client, TFP410_CTL_2, &ctl2)) {
+ + 		if (ctl2 & TFP410_CTL_2_RSEN)
+ + 		{
+ + 			return 1;	/* connected */
+ + 		}
+ + 	}
+ + 	return 0;	/* disconnected */
+ + }
+ + 
+ + static bool tfp410_read(int addr, uint8_t *ch)
+ + {
+ + 	if(cur_ckb_tfp410_device)
+ + 		return tfp410_readb(cur_ckb_tfp410_device->client, addr, ch);
+ + 	return 0;
+ + }
+ + 
+ + static bool tfp410_write(int addr, uint8_t ch)
+ + {
+ + 	if(cur_ckb_tfp410_device)
+ + 		return tfp410_writeb(cur_ckb_tfp410_device->client, addr, ch);
+ + 	return 0;
+ + }
+ + 
+ + static bool tfp410_isconnected(void)
+ + {
+ + 	if(cur_ckb_tfp410_device)
+ + 		return tfp410_detect(cur_ckb_tfp410_device->client);
+ + 	return 0;
+ + }
+ + 	
+ + static int tfp410_getid(struct i2c_client *client, int addr)
+ + {
+ + 	uint8_t ch1, ch2;
+ + 
+ + 	if (tfp410_readb(client, addr+0, &ch1) &&
+ + 	    tfp410_readb(client, addr+1, &ch2))
+ + 		return ((ch2 << 8) & 0xFF00) | (ch1 & 0x00FF);
+ + 
+ + 	return -1;
+ + }
+ + 
+ + /* set the tfp410 power state */
+ + static void tfp410_setpower(struct i2c_client *client, int mode)
+ + {
+ + 	uint8_t ctl1;
+ + 
+ + 	if (!tfp410_readb(client, TFP410_CTL_1, &ctl1))
+ + 		return;
+ + 
+ + 	if (mode == 1)		/* power on */
+ + 		ctl1 |= TFP410_CTL_1_PD;
+ + 	else
+ + 		ctl1 &= ~TFP410_CTL_1_PD;
+ + 
+ + 	tfp410_writeb(client, TFP410_CTL_1, ctl1);
+ + 	if (mode == 1)
+ + 	{
+ + 		if (!tfp410_readb(client, TFP410_CTL_2, &ctl1))
+ + 			return;
+ + 		tfp410_writeb(client, TFP410_CTL_2, (ctl1 & ~TFP410_CTL_2_MSEL_MASK) | (1 << 4) );
+ + 	}
+ + }
+ + 
+ + #if 0
+ + static void tfp410_dump_regs(struct i2c_client *client)
+ + {
+ + 	uint8_t val, val2;
+ + 
+ + 	tfp410_readb(client, TFP410_REV, &val);
+ + 	printk("TFP410_REV: 0x%02X\n", val);
+ + 	tfp410_readb(client, TFP410_CTL_1, &val);
+ + 	printk("TFP410_CTL1: 0x%02X\n", val);
+ + 	tfp410_readb(client, TFP410_CTL_2, &val);
+ + 	printk("TFP410_CTL2: 0x%02X\n", val);
+ + 	tfp410_readb(client, TFP410_CTL_3, &val);
+ + 	printk("TFP410_CTL3: 0x%02X\n", val);
+ + 	tfp410_readb(client, TFP410_USERCFG, &val);
+ + 	printk("TFP410_USERCFG: 0x%02X\n", val);
+ + 	tfp410_readb(client, TFP410_DE_DLY, &val);
+ + 	printk("TFP410_DE_DLY: 0x%02X\n", val);
+ + 	tfp410_readb(client, TFP410_DE_CTL, &val);
+ + 	printk("TFP410_DE_CTL: 0x%02X\n", val);
+ + 	tfp410_readb(client, TFP410_DE_TOP, &val);
+ + 	printk("TFP410_DE_TOP: 0x%02X\n", val);
+ + 	tfp410_readb(client, TFP410_DE_CNT_LO, &val);
+ + 	tfp410_readb(client, TFP410_DE_CNT_HI, &val2);
+ + 	printk("TFP410_DE_CNT: 0x%02X%02X\n", val2, val);
+ + 	tfp410_readb(client, TFP410_DE_LIN_LO, &val);
+ + 	tfp410_readb(client, TFP410_DE_LIN_HI, &val2);
+ + 	printk("TFP410_DE_LIN: 0x%02X%02X\n", val2, val);
+ + 	tfp410_readb(client, TFP410_H_RES_LO, &val);
+ + 	tfp410_readb(client, TFP410_H_RES_HI, &val2);
+ + 	printk("TFP410_H_RES: 0x%02X%02X\n", val2, val);
+ + 	tfp410_readb(client, TFP410_V_RES_LO, &val);
+ + 	tfp410_readb(client, TFP410_V_RES_HI, &val2);
+ + 	printk("TFP410_V_RES: 0x%02X%02X\n", val2, val);
+ + }
+ + #endif
+ + 
+ + static int __devinit tfp410_probe(struct i2c_client *client,
+ + 				const struct i2c_device_id *ids)
+ + {
+ + 	/* this will detect the tfp410 chip on the specified i2c bus */
+ + 	struct tfp410_priv *tfp;
+ + 	struct tfp410_platform_data *pdata = client->dev.platform_data;
+ + 	uint8_t ctl3;
+ + 	int id;
+ + 	tfp = devm_kzalloc(&client->dev, sizeof(*tfp), GFP_KERNEL);
+ + 	if (!tfp)
+ + 		return -ENOMEM;
+ + 		
+ + 	tfp->dev = &client->dev;
+ + 	tfp410_setpower(client, 1);
+ + 
+ + 	if ((id = tfp410_getid(client, TFP410_VID_LO)) != TFP410_VID) {
+ + 		dev_err(tfp->dev, "TFP410 not detected got VID %X: from %s "
+ + 				"Slave %d.\n",
+ + 			  id, client->adapter->name, client->addr);
+ + 		goto out;
+ + 	}
+ + 
+ + 	if ((id = tfp410_getid(client, TFP410_DID_LO)) != TFP410_DID) {
+ + 		dev_err(tfp->dev, "TFP410 not detected got DID %X: from %s "
+ + 				"Slave %d.\n",
+ + 			  id, client->adapter->name, client->addr);
+ + 		goto out;
+ + 	}
+ + 	
+ + 	/* enable skew */
+ + 	tfp410_readb(client, TFP410_CTL_3, &ctl3); 
+ + 	tfp410_writeb(client, TFP410_CTL_3, 
+ + 		ctl3 | TFP410_CTL_3_DKEN | (0x7<<5));
+ + 	
+ + 	tfp410_readb(client, TFP410_CTL_1, &ctl3);
+ + 	tfp410_writeb(client, TFP410_CTL_1, 
+ + 		(ctl3 & ~(TFP410_CTL_1_DSEL)) | TFP410_CTL_1_EDGE | TFP410_CTL_1_BSEL);
+ + 	
+ + //	tfp410_dump_regs(client);
+ + 	
+ + 	cur_ckb_tfp410_device = tfp;
+ + 	cur_ckb_tfp410_device->tfp410_read = tfp410_read;
+ + 	cur_ckb_tfp410_device->tfp410_write = tfp410_write;
+ + 	cur_ckb_tfp410_device->tfp410_isconnected = tfp410_isconnected;
+ + 	cur_ckb_tfp410_device->get_i2c_adapter = get_i2c_adapter;
+ + 	
+ + 	dev_info(tfp->dev, "TFP410 VID %#x DID %#x\n",
+ + 			TFP410_VID, TFP410_DID);
+ + 
+ + 	i2c_set_clientdata(client, tfp);
+ + 	tfp->client = client;
+ + 	tfp->pdata = pdata;
+ + 	
+ + 	return 0;
+ + out:
+ + 	kfree(tfp);
+ + 	return -1;
+ + }
+ + 
+ + static int __devexit tfp410_remove(struct i2c_client *client)
+ + {
+ + 	struct tfp410_priv *tfp = i2c_get_clientdata(client);
+ + 	cur_ckb_tfp410_device = NULL;
+ + 	kfree(tfp);
+ + 
+ + 	return 0;
+ + }
+ + 
+ + 
+ + 
+ + static const struct i2c_device_id tfp410_id_table[] = {
+ + 	{"tfp410", 0xF0},
+ + 	{/* end of list */}
+ + };
+ + MODULE_DEVICE_TABLE(i2c, tfp410_id_table);
+ + 
+ + static struct i2c_driver tfp410_driver = {
+ + 	.driver		= {
+ + 		.name	= "tfp410",
+ + 	},
+ + 	.id_table	= tfp410_id_table,
+ + 	.probe		= tfp410_probe,
+ + 	.remove		= __devexit_p(tfp410_remove),
+ + };
+ + 
+ + 
+ + static int __init tfp410_init(void)
+ + {
+ + 	return i2c_add_driver(&tfp410_driver);
+ + }
+ + subsys_initcall(tfp410_init);
+ + 
+ + static void __exit tfp410_exit(void)
+ + {
+ + 	i2c_del_driver(&tfp410_driver);
+ + }
+ + module_exit(tfp410_exit);
+ + 
+ + MODULE_AUTHOR("Aiyappa M.S.");
+ + MODULE_DESCRIPTION("TFP410 chip i2c driver");
+ + MODULE_LICENSE("GPL");
+ + 
+ diff -crN linux-3.2.1_o/drivers/video/ckb/ckb_video_modes.c linux-3.2.1/drivers/video/ckb/ckb_video_modes.c
+ *** linux-3.2.1_o/drivers/video/ckb/ckb_video_modes.c	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/drivers/video/ckb/ckb_video_modes.c	2014-11-25 13:19:16.820827695 +0900
+ ***************
+ *** 0 ****
+ --- 1,197 ----
+ + /*
+ +  * CKB DVI driver that uses TFP410 I2C driver
+ +  *
+ +  * Copyright (C) 2013 Computex Co.Ltd.
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; version 2 of the License.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ +  *
+ +  */
+ +  
+ + #include <linux/module.h>
+ + #include <linux/kernel.h>
+ + #include <linux/sched.h>
+ + #include <linux/slab.h>
+ + #include <linux/init.h>
+ + #include <linux/io.h>
+ + #include <linux/fs.h>
+ + #include <linux/clk.h>
+ + #include <linux/err.h>
+ + #include <linux/i2c.h>
+ + #include <linux/delay.h>
+ + #include <linux/fb.h>
+ + #include <linux/platform_device.h>
+ + #include <mach/devices.h>
+ + #include <video/da8xx-fb.h>
+ + #include <video/ckb_video_modes.h>
+ + 
+ + static struct file *vfile_fd = NULL;
+ + static loff_t vfile_pos = 0;
+ + static int g_mode_index = 0;
+ + static struct da8xx_panel *g_fb_panels=NULL;
+ + int g_fb_panels_size;
+ + static int g_fb_bpp;
+ + static char g_buffer[512];
+ + static char g_synbuffer[512];
+ + 
+ + char *getSync(__u32 sync)
+ + {
+ + 	int len;
+ + 	if(sync == 0)
+ + 		return "None";
+ + 
+ + 	g_synbuffer[0] = 0;
+ + 	if(sync & FB_SYNC_HOR_HIGH_ACT)
+ + 		strcat(g_synbuffer, "FB_SYNC_HOR_HIGH_ACT | ");
+ + 	if(sync & FB_SYNC_VERT_HIGH_ACT)
+ + 		strcat(g_synbuffer, "FB_SYNC_VERT_HIGH_ACT | ");
+ + 	if(sync & FB_SYNC_EXT)
+ + 		strcat(g_synbuffer, "FB_SYNC_EXT | ");
+ + 	if(sync & FB_SYNC_COMP_HIGH_ACT)
+ + 		strcat(g_synbuffer, "FB_SYNC_COMP_HIGH_ACT | ");
+ + 	if(sync & FB_SYNC_BROADCAST)
+ + 		strcat(g_synbuffer, "FB_SYNC_BROADCAST | ");
+ + 	if(sync & FB_SYNC_ON_GREEN)
+ + 		strcat(g_synbuffer, "FB_SYNC_ON_GREEN | ");
+ + 	
+ + 	len = strlen(g_synbuffer);
+ + 	if(!len)
+ + 	{
+ + 		return "Unknown";
+ + 	}
+ + 	g_synbuffer[len-3] = 0;
+ + 	return g_synbuffer;
+ + }
+ + 
+ + char create_video_mode_file()
+ + {
+ + 	static struct file *dir_fd;
+ + 	int retry = 10;
+ + 	if(vfile_fd != NULL)
+ + 		filp_close(vfile_fd, NULL);
+ + 
+ + 	else
+ + 	{
+ + 		/* make sure /etc exists, this needed as this code is sometimes called before the FS is mounted */
+ + 		dir_fd = filp_open(FBSET_DB_DIR, O_RDONLY, 0);
+ + 		while(IS_ERR(dir_fd) && retry--)
+ + 		{
+ + 			mdelay(500);
+ + 			dir_fd = filp_open(FBSET_DB_DIR, O_RDONLY, 0);
+ + 		}
+ + 		if(retry<0)
+ + 			goto _failed;
+ + 		/* directory exits */
+ + 		filp_close(dir_fd, NULL);
+ + 	}
+ + 
+ + 	vfile_fd = filp_open(FBSET_DB_FILE, O_CREAT | O_RDWR | O_TRUNC, 0);
+ + 	if (IS_ERR(vfile_fd))
+ + 	{
+ + _failed:
+ + 		printk("File %s could not be created\n", FBSET_DB_FILE);
+ + 		vfile_fd = NULL;
+ + 		return 0;
+ +     }
+ + 	g_mode_index = 0;
+ + 	vfile_pos = 0;
+ + 	return 1;
+ + }
+ + 
+ + void close_video_mode_file()
+ + {
+ + 	if(vfile_fd != NULL)
+ + 	{
+ + 		filp_close(vfile_fd, NULL);
+ + 		vfile_fd = NULL;
+ +     }
+ + }
+ + 
+ + void append_video_mode(const char *name, __u32 xres, __u32 yres, char *duplicate, __u32 clockMhz,
+ + 			__u32 pixclock, __u32 left_margin, __u32 right_margin, __u32 upper_margin, __u32 lower_margin,
+ + 			__u32 hsync_len,  __u32 vsync_len, 	__u32 sync)
+ + {
+ + 	sprintf(g_buffer, "mode "
+ + #ifdef CONFIG_CKB_EASY_SWITCH_MODE
+ + 		"\"%d\"\n"
+ + #else
+ + 		"\"%dx%d@%d%s%s\"\n"
+ + #endif
+ + 		"    #%dx%d%s%s\n"
+ + 		"    #Clock=%dMHz (%d picosecs)\n" 
+ + 		"    geometry %d %d %d %d %d\n"
+ + 		"    timings %d %d %d %d %d %d %d\n"
+ + 		"    #sync: %s\n"
+ + 		"endmode\n\n",
+ + #ifdef CONFIG_CKB_EASY_SWITCH_MODE
+ + 			g_mode_index,
+ + #else
+ + 			xres, yres, clockMhz, duplicate, name,
+ + #endif
+ + 			xres, yres, duplicate, name,
+ + 			clockMhz, pixclock,
+ + 			xres, yres, xres, yres, g_fb_bpp,
+ + 			pixclock, left_margin, right_margin, upper_margin, lower_margin, hsync_len,  vsync_len,
+ + 			getSync(sync)
+ + 		);
+ + 
+ + 	vfs_write(vfile_fd, g_buffer, strlen(g_buffer), &vfile_pos);
+ + 	g_mode_index++;
+ + 
+ + }
+ + 
+ + void append_fb_mode()
+ + {
+ + 	struct da8xx_panel *lcdc_info;
+ + 	int i;
+ + 	
+ + 	if(g_fb_panels)
+ + 	{
+ + 		if(vfile_fd == NULL)
+ + 		{
+ + 			vfile_fd = filp_open(FBSET_DB_FILE, O_CREAT | O_RDWR | O_APPEND, 0);
+ + 			if (IS_ERR(vfile_fd))
+ + 			{
+ + 				printk("File %s could not be opened for writing\n", FBSET_DB_FILE);
+ + 				vfile_fd = NULL;
+ + 				return;
+ + 			}
+ + 			vfile_pos = 0;
+ + 		}
+ + 
+ + 		for (i=0,lcdc_info=g_fb_panels; i<g_fb_panels_size; i++,lcdc_info++)
+ + 		{
+ + 
+ + 			append_video_mode(lcdc_info->name, lcdc_info->width, lcdc_info->height,
+ + 				" ", PICOS2KHZ(lcdc_info->pxl_clk)/1000, lcdc_info->pxl_clk,
+ + 				lcdc_info->hbp, lcdc_info->hfp,
+ + 					lcdc_info->vbp, lcdc_info->vfp, 
+ + 					lcdc_info->hsw,  lcdc_info->vsw,
+ + 					lcdc_info->sync);
+ + 		}
+ + 		
+ + 	}
+ + }
+ + 
+ + void set_fb_panel_info(struct da8xx_panel *fb_panels, int size, int bpp)
+ + {
+ + 	g_fb_panels = fb_panels;
+ + 	g_fb_panels_size = size;
+ + 	g_fb_bpp = bpp;
+ + }
+ + 
+ + EXPORT_SYMBOL(create_video_mode_file);
+ + EXPORT_SYMBOL(close_video_mode_file);
+ + EXPORT_SYMBOL(append_video_mode);
+ + EXPORT_SYMBOL(append_fb_mode);
+ + EXPORT_SYMBOL(set_fb_panel_info);
+ diff -crN linux-3.2.1_o/drivers/video/ckb/Makefile linux-3.2.1/drivers/video/ckb/Makefile
+ *** linux-3.2.1_o/drivers/video/ckb/Makefile	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/drivers/video/ckb/Makefile	2014-11-25 13:19:16.820827695 +0900
+ ***************
+ *** 0 ****
+ --- 1,4 ----
+ + # Makefile for the Linux CKB LCD/DVI support.
+ + 
+ + obj-$(CONFIG_CKB_LCD_SUPPORT)     += ckb_video_modes.o
+ + obj-$(CONFIG_CKB_DVI_SUPPORT)     += ckb_video_modes.o ckb_tfp410.o ckb_dvi.o
+ \ No newline at end of file
+ diff -crN linux-3.2.1_o/drivers/video/da8xx-fb.c linux-3.2.1/drivers/video/da8xx-fb.c
+ *** linux-3.2.1_o/drivers/video/da8xx-fb.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/video/da8xx-fb.c	2014-11-25 13:19:16.938128020 +0900
+ ***************
+ *** 30,37 ****
+ --- 30,51 ----
+   #include <linux/clk.h>
+   #include <linux/cpufreq.h>
+   #include <linux/console.h>
+ + #include <linux/spinlock.h>
+   #include <linux/slab.h>
+ + #include <linux/delay.h>
+ + #include <linux/pm_runtime.h>
+ + #include <linux/lcm.h>
+   #include <video/da8xx-fb.h>
+ + #include <asm/mach-types.h>
+ + #include <asm/div64.h>
+ + 
+ + #if defined(CONFIG_CKB_LCD_SUPPORT) || defined(CONFIG_CKB_DVI_SUPPORT)
+ + #include <mach/ckb_3352_mem.h>
+ + #include <video/ckb_video_modes.h>
+ + #endif
+ + #ifdef CONFIG_CKB_DVI_SUPPORT
+ + #include <video/ckb_dvi.h>
+ + #endif
+   
+   #define DRIVER_NAME "da8xx_lcdc"
+   
+ ***************
+ *** 82,87 ****
+ --- 96,103 ----
+   #define LCD_V2_LIDD_CLK_EN		BIT(1)
+   #define LCD_V2_CORE_CLK_EN		BIT(0)
+   #define LCD_V2_LPP_B10			26
+ + #define LCD_V2_TFT_24BPP_MODE		BIT(25)
+ + #define LCD_V2_TFT_24BPP_UNPACK		BIT(26)
+   
+   /* LCD Raster Timing 2 Register */
+   #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x)	((x) << 16)
+ ***************
+ *** 126,131 ****
+ --- 142,149 ----
+   #define RIGHT_MARGIN	64
+   #define UPPER_MARGIN	32
+   #define LOWER_MARGIN	32
+ + #define WAIT_FOR_FRAME_DONE	true
+ + #define NO_WAIT_FOR_FRAME_DONE	false
+   
+   static resource_size_t da8xx_fb_reg_base;
+   static struct resource *lcdc_regs;
+ ***************
+ *** 143,148 ****
+ --- 161,167 ----
+   }
+   
+   struct da8xx_fb_par {
+ + 	struct device *dev;
+   	resource_size_t p_palette_base;
+   	unsigned char *v_palette_base;
+   	dma_addr_t		vram_phys;
+ ***************
+ *** 159,172 ****
+   	wait_queue_head_t	vsync_wait;
+   	int			vsync_flag;
+   	int			vsync_timeout;
+   #ifdef CONFIG_CPU_FREQ
+   	struct notifier_block	freq_transition;
+   #endif
+   	void (*panel_power_ctrl)(int);
+   };
+   
+   /* Variable Screen Information */
+ ! static struct fb_var_screeninfo da8xx_fb_var __devinitdata = {
+   	.xoffset = 0,
+   	.yoffset = 0,
+   	.transp = {0, 0, 0},
+ --- 178,203 ----
+   	wait_queue_head_t	vsync_wait;
+   	int			vsync_flag;
+   	int			vsync_timeout;
+ + 	spinlock_t		lock_for_chan_update;
+ + 
+ + 	/*
+ + 	 * LCDC has 2 ping pong DMA channels, channel 0
+ + 	 * and channel 1.
+ + 	 */
+ + 	unsigned int		which_dma_channel_done;
+ + 	unsigned char dma_alloc;
+   #ifdef CONFIG_CPU_FREQ
+   	struct notifier_block	freq_transition;
+ + 	unsigned int		lcd_fck_rate;
+ + #endif
+ + #if defined(CONFIG_CKB_LCD_SUPPORT) || defined(CONFIG_CKB_DVI_SUPPORT)
+ + 	struct lcd_ctrl_config *lcd_cfg;
+   #endif
+   	void (*panel_power_ctrl)(int);
+   };
+   
+   /* Variable Screen Information */
+ ! static struct fb_var_screeninfo da8xx_fb_var = {
+   	.xoffset = 0,
+   	.yoffset = 0,
+   	.transp = {0, 0, 0},
+ ***************
+ *** 174,180 ****
+   	.activate = 0,
+   	.height = -1,
+   	.width = -1,
+ - 	.pixclock = 46666,	/* 46us - AUO display */
+   	.accel_flags = 0,
+   	.left_margin = LEFT_MARGIN,
+   	.right_margin = RIGHT_MARGIN,
+ --- 205,210 ----
+ ***************
+ *** 195,217 ****
+   	.accel = FB_ACCEL_NONE
+   };
+   
+ ! struct da8xx_panel {
+ ! 	const char	name[25];	/* Full name <vendor>_<model> */
+ ! 	unsigned short	width;
+ ! 	unsigned short	height;
+ ! 	int		hfp;		/* Horizontal front porch */
+ ! 	int		hbp;		/* Horizontal back porch */
+ ! 	int		hsw;		/* Horizontal Sync Pulse Width */
+ ! 	int		vfp;		/* Vertical front porch */
+ ! 	int		vbp;		/* Vertical back porch */
+ ! 	int		vsw;		/* Vertical Sync Pulse Width */
+ ! 	unsigned int	pxl_clk;	/* Pixel clock */
+ ! 	unsigned char	invert_pxl_clk;	/* Invert Pixel clock */
+ ! };
+   
+   static struct da8xx_panel known_lcd_panels[] = {
+   	/* Sharp LCD035Q3DG01 */
+ ! 	[0] = {
+   		.name = "Sharp_LCD035Q3DG01",
+   		.width = 320,
+   		.height = 240,
+ --- 225,284 ----
+   	.accel = FB_ACCEL_NONE
+   };
+   
+ ! static vsync_callback_t vsync_cb_handler;
+ ! static void *vsync_cb_arg;
+   
+   static struct da8xx_panel known_lcd_panels[] = {
+ + #if defined(CONFIG_CKB_LCD_SUPPORT) || defined(CONFIG_CKB_DVI_SUPPORT)
+ + #ifdef CONFIG_CKB_LCD_SUPPORT
+ + 	/* Visionx KTM050AL02 */
+ + 	{
+ + 		.name = "Visionx_KTM050AL02",
+ + 		.width = 800,
+ + 		.height = 480,
+ + 		.hfp = 40,
+ + 		.hbp = 40,
+ + 		.hsw = 48,
+ + 		.vfp = 13,
+ + 		.vbp = 29,
+ + 		.vsw = 3,
+ + 		.pxl_clk = 33000000,
+ + 		.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ + 	},
+ + 	/* Kyocera TCG070WVLPAAFA_AA00 */
+ + 	{
+ + 		.name = "KyoceraTCG070WVLPAAFA_AA00",
+ + 		.width = 800,						
+ + 		.height = 480,
+ + 		.pxl_clk = 33200000,
+ + 		.hbp = 88,		/* left_margin */
+ + 		.hfp = 40,		/* right_margin */
+ + 		.vbp = 32,		/* upper_margin */
+ + 		.vfp = 11,		/* lower_margin */
+ + 		.hsw = 128,		/* hsync_len */
+ + 		.vsw = 2,			/* vsync_len */
+ + 		.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,     
+ + 	},
+ + #endif
+ + #ifdef CONFIG_CKB_DVI_SUPPORT
+ + 	/* Generic DVI monitor (This setting works for most monitors) */
+ + 	{
+ + 		.name = "Generic DVI panel",
+ + 		.width = 800,
+ + 		.height = 480,
+ + 		.pxl_clk = 33000000,
+ + 		.hbp = 40,
+ + 		.hfp = 40,
+ + 		.vbp = 29,
+ + 		.vfp = 13,
+ + 		.hsw = 48,
+ + 		.vsw = 3,
+ + 		.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ + 	},
+ + #endif
+ + #else
+   	/* Sharp LCD035Q3DG01 */
+ ! 	{
+   		.name = "Sharp_LCD035Q3DG01",
+   		.width = 320,
+   		.height = 240,
+ ***************
+ *** 222,243 ****
+   		.vbp = 2,
+   		.vsw = 0,
+   		.pxl_clk = 4608000,
+ ! 		.invert_pxl_clk = 1,
+   	},
+   	/* Sharp LK043T1DG01 */
+ ! 	[1] = {
+   		.name = "Sharp_LK043T1DG01",
+   		.width = 480,
+   		.height = 272,
+   		.hfp = 2,
+   		.hbp = 2,
+   		.hsw = 41,
+ ! 		.vfp = 2,
+ ! 		.vbp = 2,
+   		.vsw = 10,
+   		.pxl_clk = 7833600,
+ ! 		.invert_pxl_clk = 0,
+   	},
+   };
+   
+   /* Enable the Raster Engine of the LCD Controller */
+ --- 289,340 ----
+   		.vbp = 2,
+   		.vsw = 0,
+   		.pxl_clk = 4608000,
+ ! 		.sync           = FB_SYNC_CLK_INVERT |
+ ! 			FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+   	},
+   	/* Sharp LK043T1DG01 */
+ ! 	{
+   		.name = "Sharp_LK043T1DG01",
+   		.width = 480,
+   		.height = 272,
+   		.hfp = 2,
+   		.hbp = 2,
+   		.hsw = 41,
+ ! 		.vfp = 3,
+ ! 		.vbp = 3,
+   		.vsw = 10,
+   		.pxl_clk = 7833600,
+ ! 		.sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ ! 	},
+ ! 	/* ThreeFive S9700RTWV35TR */
+ ! 	{
+ ! 		.name = "TFC_S9700RTWV35TR_01B",
+ ! 		.width = 800,
+ ! 		.height = 480,
+ ! 		.hfp = 39,
+ ! 		.hbp = 39,
+ ! 		.hsw = 47,
+ ! 		.vfp = 13,
+ ! 		.vbp = 29,
+ ! 		.vsw = 2,
+ ! 		.pxl_clk = 30000000,
+ ! 		.sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ ! 	},
+ ! 	/* Newhaven Display */
+ ! 	{
+ ! 		.name = "NHD-4.3-ATXI#-T-1",
+ ! 		.width = 480,
+ ! 		.height = 272,
+ ! 		.hfp = 8,
+ ! 		.hbp = 43,
+ ! 		.hsw = 4,
+ ! 		.vfp = 4,
+ ! 		.vbp = 12,
+ ! 		.vsw = 10,
+ ! 		.pxl_clk = 9000000,
+ ! 		.sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+   	},
+ + #endif
+   };
+   
+   /* Enable the Raster Engine of the LCD Controller */
+ ***************
+ *** 245,271 ****
+   {
+   	u32 reg;
+   
+   	/* Bring LCDC out of reset */
+   	if (lcd_revision == LCD_VERSION_2)
+   		lcdc_write(0, LCD_CLK_RESET_REG);
+   
+   	reg = lcdc_read(LCD_RASTER_CTRL_REG);
+   	if (!(reg & LCD_RASTER_ENABLE))
+   		lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
+   }
+   
+   /* Disable the Raster Engine of the LCD Controller */
+ ! static inline void lcd_disable_raster(void)
+   {
+   	u32 reg;
+   
+   	reg = lcdc_read(LCD_RASTER_CTRL_REG);
+   	if (reg & LCD_RASTER_ENABLE)
+   		lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
+   
+ ! 	if (lcd_revision == LCD_VERSION_2)
+ ! 		/* Write 1 to reset LCDC */
+ ! 		lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
+   }
+   
+   static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
+ --- 342,399 ----
+   {
+   	u32 reg;
+   
+ + 	/* Put LCDC in reset for several cycles */
+ + 	if (lcd_revision == LCD_VERSION_2)
+ + 		lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
+ + 
+ + 	mdelay(1);
+ + 
+   	/* Bring LCDC out of reset */
+   	if (lcd_revision == LCD_VERSION_2)
+   		lcdc_write(0, LCD_CLK_RESET_REG);
+   
+ + 	mdelay(1);
+ + 
+ + 	/* Above reset sequence doesnot reset register context */
+   	reg = lcdc_read(LCD_RASTER_CTRL_REG);
+   	if (!(reg & LCD_RASTER_ENABLE))
+   		lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
+   }
+   
+   /* Disable the Raster Engine of the LCD Controller */
+ ! static inline void lcd_disable_raster(bool wait_for_frame_done)
+   {
+   	u32 reg;
+ + 	u32 loop_cnt = 0;
+ + 	u32 stat;
+ + 	u32 i = 0;
+ + 
+ + 	if (wait_for_frame_done)
+ + 		loop_cnt = 5000;
+   
+   	reg = lcdc_read(LCD_RASTER_CTRL_REG);
+   	if (reg & LCD_RASTER_ENABLE)
+   		lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
+   
+ ! 	/* Wait for the current frame to complete */
+ ! 	do {
+ ! 		if (lcd_revision == LCD_VERSION_1)
+ ! 			stat = lcdc_read(LCD_STAT_REG);
+ ! 		else
+ ! 			stat = lcdc_read(LCD_RAW_STAT_REG);
+ ! 
+ ! 		mdelay(1);
+ ! 	} while (!(stat & BIT(0)) && (i++ < loop_cnt));
+ ! 
+ ! 	if (lcd_revision == LCD_VERSION_1)
+ ! 		lcdc_write(stat, LCD_STAT_REG);
+ ! 	else
+ ! 		lcdc_write(stat, LCD_MASKED_STAT_REG);
+ ! 
+ ! 	if ((loop_cnt != 0) && (i >= loop_cnt)) {
+ ! 		printk(KERN_ERR "LCD Controller timed out\n");
+ ! 		return;
+ ! 	}
+   }
+   
+   static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
+ ***************
+ *** 292,298 ****
+   		} else {
+   			reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
+   				LCD_V2_END_OF_FRAME0_INT_ENA |
+ ! 				LCD_V2_END_OF_FRAME1_INT_ENA;
+   			lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
+   		}
+   		reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
+ --- 420,427 ----
+   		} else {
+   			reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
+   				LCD_V2_END_OF_FRAME0_INT_ENA |
+ ! 				LCD_V2_END_OF_FRAME1_INT_ENA |
+ ! 				LCD_V2_UNDERFLOW_INT_ENA | LCD_SYNC_LOST;
+   			lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
+   		}
+   		reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
+ ***************
+ *** 329,336 ****
+   	lcd_enable_raster();
+   }
+   
+ ! /* Configure the Burst Size of DMA */
+ ! static int lcd_cfg_dma(int burst_size)
+   {
+   	u32 reg;
+   
+ --- 458,465 ----
+   	lcd_enable_raster();
+   }
+   
+ ! /* Configure the Burst Size and fifo threhold of DMA */
+ ! static int lcd_cfg_dma(int burst_size,  int fifo_th)
+   {
+   	u32 reg;
+   
+ ***************
+ *** 354,359 ****
+ --- 483,491 ----
+   	default:
+   		return -EINVAL;
+   	}
+ + 
+ + 	reg |= (fifo_th << 8);
+ + 
+   	lcdc_write(reg, LCD_DMA_CTRL_REG);
+   
+   	return 0;
+ ***************
+ *** 374,385 ****
+ --- 506,534 ----
+   		int front_porch)
+   {
+   	u32 reg;
+ + 	
+ + #if 1
+ + 	/* fill low bits */
+ + 	reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0x3ff;
+ + 	reg |= ((back_porch & 0xff) << 24)
+ + 	    | ((front_porch & 0xff) << 16)
+ + 	    | ((pulse_width & 0x3f) << 10);
+ + 	lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
+   
+ + 	/* fill high bits */
+ + 	reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0x07ffff00;
+ + 	reg |= (((back_porch & 0x300)>>8) << 4)
+ + 	    | (((front_porch & 0x300)>>8))
+ + 	    | (((pulse_width & 0x3C0)>>6) << 27);
+ + 	lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
+ + #else
+   	reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf;
+   	reg |= ((back_porch & 0xff) << 24)
+   	    | ((front_porch & 0xff) << 16)
+   	    | ((pulse_width & 0x3f) << 10);
+   	lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
+ + #endif	
+ + 	
+   }
+   
+   static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
+ ***************
+ *** 394,400 ****
+   	lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
+   }
+   
+ ! static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
+   {
+   	u32 reg;
+   	u32 reg_int;
+ --- 543,550 ----
+   	lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
+   }
+   
+ ! static int lcd_cfg_display(const struct lcd_ctrl_config *cfg,
+ ! 		struct da8xx_panel *panel)
+   {
+   	u32 reg;
+   	u32 reg_int;
+ ***************
+ *** 447,458 ****
+   	else
+   		reg &= ~LCD_SYNC_EDGE;
+   
+ ! 	if (cfg->invert_line_clock)
+   		reg |= LCD_INVERT_LINE_CLOCK;
+   	else
+   		reg &= ~LCD_INVERT_LINE_CLOCK;
+   
+ ! 	if (cfg->invert_frm_clock)
+   		reg |= LCD_INVERT_FRAME_CLOCK;
+   	else
+   		reg &= ~LCD_INVERT_FRAME_CLOCK;
+ --- 597,608 ----
+   	else
+   		reg &= ~LCD_SYNC_EDGE;
+   
+ ! 	if (panel->sync & FB_SYNC_HOR_HIGH_ACT)
+   		reg |= LCD_INVERT_LINE_CLOCK;
+   	else
+   		reg &= ~LCD_INVERT_LINE_CLOCK;
+   
+ ! 	if (panel->sync & FB_SYNC_VERT_HIGH_ACT)
+   		reg |= LCD_INVERT_FRAME_CLOCK;
+   	else
+   		reg &= ~LCD_INVERT_FRAME_CLOCK;
+ ***************
+ *** 510,515 ****
+ --- 660,672 ----
+   	reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);
+   	if (raster_order)
+   		reg |= LCD_RASTER_ORDER;
+ + 
+ + 	if (bpp == 24)
+ + 		reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE);
+ + 	else if (bpp == 32)
+ + 		reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE
+ + 				| LCD_V2_TFT_24BPP_UNPACK);
+ + 
+   	lcdc_write(reg, LCD_RASTER_CTRL_REG);
+   
+   	switch (bpp) {
+ ***************
+ *** 517,522 ****
+ --- 674,681 ----
+   	case 2:
+   	case 4:
+   	case 16:
+ + 	case 24:
+ + 	case 32:
+   		par->palette_sz = 16 * 2;
+   		break;
+   
+ ***************
+ *** 575,580 ****
+ --- 734,756 ----
+   			update_hw = 1;
+   			palette[0] = 0x4000;
+   		}
+ + 	} else if (((info->var.bits_per_pixel == 32) && regno < 32) ||
+ + 		    ((info->var.bits_per_pixel == 24) && regno < 24)) {
+ + 		red >>= (24 - info->var.red.length);
+ + 		red <<= info->var.red.offset;
+ + 
+ + 		green >>= (24 - info->var.green.length);
+ + 		green <<= info->var.green.offset;
+ + 
+ + 		blue >>= (24 - info->var.blue.length);
+ + 		blue <<= info->var.blue.offset;
+ + 
+ + 		par->pseudo_palette[regno] = red | green | blue;
+ + 
+ + 		if (palette[0] != 0x4000) {
+ + 			update_hw = 1;
+ + 			palette[0] = 0x4000;
+ + 		}
+   	}
+   
+   	/* Update the palette in the h/w as needed. */
+ ***************
+ *** 587,593 ****
+   static void lcd_reset(struct da8xx_fb_par *par)
+   {
+   	/* Disable the Raster if previously Enabled */
+ ! 	lcd_disable_raster();
+   
+   	/* DMA has to be disabled */
+   	lcdc_write(0, LCD_DMA_CTRL_REG);
+ --- 763,769 ----
+   static void lcd_reset(struct da8xx_fb_par *par)
+   {
+   	/* Disable the Raster if previously Enabled */
+ ! 	lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
+   
+   	/* DMA has to be disabled */
+   	lcdc_write(0, LCD_DMA_CTRL_REG);
+ ***************
+ *** 601,613 ****
+   	}
+   }
+   
+   static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
+   {
+   	unsigned int lcd_clk, div;
+ - 
+   	lcd_clk = clk_get_rate(par->lcdc_clk);
+   	div = lcd_clk / par->pxl_clk;
+ ! 
+   	/* Configure the LCD clock divisor. */
+   	lcdc_write(LCD_CLK_DIVISOR(div) |
+   			(LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);
+ --- 777,857 ----
+   	}
+   }
+   
+ + #if defined(CONFIG_LCD_CLOCK_CLOSEST_MATCH)
+ + int get_clk_divider(struct da8xx_fb_par *par)
+ + {
+ + 	/* try to get a good value by calculating the best PLL clock and divider */
+ + 	volatile int best_divider;
+ + 	volatile int output_clock;
+ + 	volatile unsigned long best_difference = 0xffffffff;
+ + 	volatile int i, div;
+ + 	volatile unsigned long difference;
+ + 	volatile int dpll_clock;
+ + 	volatile int dpll_divider;
+ + 	/* check to see if the exact divider or divider+1 will give a nearest value */
+ + 	/* The only way to get the precise clock is to alter DPLL clock */ 
+ + 	/* check the CM_DIV_M2_DPLL_DISP Register */
+ + 	int orig_rate = clk_get_rate(par->lcdc_clk);
+ + 	volatile int found = 0;
+ + 	for(i=1; i<=1; i++)
+ + 	{
+ + 		dpll_clock = orig_rate/i;
+ + 		
+ + 		/* calculate upper difference; the clock obtained here will be faster than what is requested */
+ + 		div = dpll_clock / par->pxl_clk;
+ + 		if(div>1)
+ + 		{
+ + 			output_clock = dpll_clock / div;
+ + 			difference = output_clock - par->pxl_clk;
+ + 			if(output_clock - par->pxl_clk <= best_difference)
+ + 			{
+ + 				best_difference = difference;
+ + 				best_divider = div;
+ + 				dpll_divider = i;
+ + 				found = 1;
+ + 			}
+ + 		}
+ + 		if(div>0)
+ + 		{
+ + 			/* calculate lower difference; the clock obtained here will be slower than what is requested */
+ + 			output_clock = dpll_clock / (div+1);
+ + 			difference = par->pxl_clk - output_clock;
+ + 			if(par->pxl_clk - output_clock <= best_difference)
+ + 			{
+ + 				best_difference = difference;
+ + 				best_divider = div+1;
+ + 				dpll_divider = i;
+ + 				found = 1;
+ + 			}
+ + 		}
+ + 	}
+ + 	if(found)
+ + 	{
+ + 		div = best_divider;
+ + //		par->pxl_clk = best_output_clock;
+ + 	}
+ + 	else
+ + 	{
+ + 		div = clk_get_rate(par->lcdc_clk) / par->pxl_clk;
+ + 	}
+ + 	//printk("****div=%d, dpll_divider=%d", div, dpll_divider);
+ + 	return div;
+ + 	
+ + }
+ + #endif
+ + 
+   static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
+   {
+ + #if defined(CONFIG_LCD_CLOCK_CLOSEST_MATCH)
+ + 	unsigned int div;
+ + 	div = get_clk_divider(par);
+ + 	//printk("***clock divider = %d\n", div);
+ + #else
+   	unsigned int lcd_clk, div;
+   	lcd_clk = clk_get_rate(par->lcdc_clk);
+   	div = lcd_clk / par->pxl_clk;
+ ! #endif
+ ! 	
+   	/* Configure the LCD clock divisor. */
+   	lcdc_write(LCD_CLK_DIVISOR(div) |
+   			(LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);
+ ***************
+ *** 615,643 ****
+   	if (lcd_revision == LCD_VERSION_2)
+   		lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
+   				LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG);
+ - 
+   }
+   
+   static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
+ ! 		struct da8xx_panel *panel)
+   {
+   	u32 bpp;
+   	int ret = 0;
+   
+ ! 	lcd_reset(par);
+   
+   	/* Calculate the divider */
+   	lcd_calc_clk_divider(par);
+   
+ ! 	if (panel->invert_pxl_clk)
+   		lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) |
+   			LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
+   	else
+   		lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) &
+   			~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
+   
+ ! 	/* Configure the DMA burst size. */
+ ! 	ret = lcd_cfg_dma(cfg->dma_burst_sz);
+   	if (ret < 0)
+   		return ret;
+   
+ --- 859,891 ----
+   	if (lcd_revision == LCD_VERSION_2)
+   		lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
+   				LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG);
+   }
+   
+   static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
+ ! 		struct da8xx_panel *panel, unsigned char reset)
+   {
+   	u32 bpp;
+   	int ret = 0;
+   
+ ! 	if(reset)
+ ! 	{
+ ! 		lcd_reset(par);
+ ! 		
+ ! 	}
+   
+   	/* Calculate the divider */
+   	lcd_calc_clk_divider(par);
+   
+ ! 
+ ! 	if (panel->sync & FB_SYNC_CLK_INVERT)
+   		lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) |
+   			LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
+   	else
+   		lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) &
+   			~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
+   
+ ! 	/* Configure the DMA burst size and fifo threshold. */
+ ! 	ret = lcd_cfg_dma(cfg->dma_burst_sz, cfg->fifo_th);
+   	if (ret < 0)
+   		return ret;
+   
+ ***************
+ *** 649,659 ****
+   	lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
+   
+   	/* Configure for disply */
+ ! 	ret = lcd_cfg_display(cfg);
+   	if (ret < 0)
+   		return ret;
+   
+ ! 	if (QVGA != cfg->p_disp_panel->panel_type)
+   		return -EINVAL;
+   
+   	if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
+ --- 897,909 ----
+   	lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
+   
+   	/* Configure for disply */
+ ! 	ret = lcd_cfg_display(cfg, panel);
+   	if (ret < 0)
+   		return ret;
+   
+ ! 
+ ! 	if ((QVGA != cfg->p_disp_panel->panel_type) &&
+ ! 			(WVGA != cfg->p_disp_panel->panel_type))
+   		return -EINVAL;
+   
+   	if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
+ ***************
+ *** 676,681 ****
+ --- 926,957 ----
+   	return 0;
+   }
+   
+ + int register_vsync_cb(vsync_callback_t handler, void *arg, int idx)
+ + {
+ + 	if ((vsync_cb_handler == NULL) && (vsync_cb_arg == NULL)) {
+ + 		vsync_cb_handler = handler;
+ + 		vsync_cb_arg = arg;
+ + 	} else {
+ + 		return -EEXIST;
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(register_vsync_cb);
+ + 
+ + int unregister_vsync_cb(vsync_callback_t handler, void *arg, int idx)
+ + {
+ + 	if ((vsync_cb_handler == handler) && (vsync_cb_arg == arg)) {
+ + 		vsync_cb_handler = NULL;
+ + 		vsync_cb_arg = NULL;
+ + 	} else {
+ + 		return -ENXIO;
+ + 	}
+ + 
+ + 	return 0;
+ + }
+ + EXPORT_SYMBOL(unregister_vsync_cb);
+ + 
+   /* IRQ handler for version 2 of LCDC */
+   static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg)
+   {
+ ***************
+ *** 684,690 ****
+   	u32 reg_int;
+   
+   	if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
+ ! 		lcd_disable_raster();
+   		lcdc_write(stat, LCD_MASKED_STAT_REG);
+   		lcd_enable_raster();
+   	} else if (stat & LCD_PL_LOAD_DONE) {
+ --- 960,967 ----
+   	u32 reg_int;
+   
+   	if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
+ ! 		printk(KERN_ERR "LCDC sync lost or underflow error occured\n");
+ ! 		lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
+   		lcdc_write(stat, LCD_MASKED_STAT_REG);
+   		lcd_enable_raster();
+   	} else if (stat & LCD_PL_LOAD_DONE) {
+ ***************
+ *** 694,700 ****
+   		 * interrupt via the following write to the status register. If
+   		 * this is done after then one gets multiple PL done interrupts.
+   		 */
+ ! 		lcd_disable_raster();
+   
+   		lcdc_write(stat, LCD_MASKED_STAT_REG);
+   
+ --- 971,977 ----
+   		 * interrupt via the following write to the status register. If
+   		 * this is done after then one gets multiple PL done interrupts.
+   		 */
+ ! 		lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
+   
+   		lcdc_write(stat, LCD_MASKED_STAT_REG);
+   
+ ***************
+ *** 709,729 ****
+ --- 986,1012 ----
+   		lcdc_write(stat, LCD_MASKED_STAT_REG);
+   
+   		if (stat & LCD_END_OF_FRAME0) {
+ + 			par->which_dma_channel_done = 0;
+   			lcdc_write(par->dma_start,
+   				   LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
+   			lcdc_write(par->dma_end,
+   				   LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
+   			par->vsync_flag = 1;
+   			wake_up_interruptible(&par->vsync_wait);
+ + 			if (vsync_cb_handler)
+ + 				vsync_cb_handler(vsync_cb_arg);
+   		}
+   
+   		if (stat & LCD_END_OF_FRAME1) {
+ + 			par->which_dma_channel_done = 1;
+   			lcdc_write(par->dma_start,
+   				   LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
+   			lcdc_write(par->dma_end,
+   				   LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
+   			par->vsync_flag = 1;
+   			wake_up_interruptible(&par->vsync_wait);
+ + 			if (vsync_cb_handler)
+ + 				vsync_cb_handler(vsync_cb_arg);
+   		}
+   	}
+   
+ ***************
+ *** 739,747 ****
+   	u32 reg_ras;
+   
+   	if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
+ ! 		lcd_disable_raster();
+   		lcdc_write(stat, LCD_STAT_REG);
+   		lcd_enable_raster();
+   	} else if (stat & LCD_PL_LOAD_DONE) {
+   		/*
+   		 * Must disable raster before changing state of any control bit.
+ --- 1022,1033 ----
+   	u32 reg_ras;
+   
+   	if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
+ ! 		printk(KERN_ERR "LCDC sync lost or underflow error occured\n");
+ ! 		lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
+ ! 		clk_disable(par->lcdc_clk);
+   		lcdc_write(stat, LCD_STAT_REG);
+   		lcd_enable_raster();
+ + 		clk_enable(par->lcdc_clk);
+   	} else if (stat & LCD_PL_LOAD_DONE) {
+   		/*
+   		 * Must disable raster before changing state of any control bit.
+ ***************
+ *** 749,755 ****
+   		 * interrupt via the following write to the status register. If
+   		 * this is done after then one gets multiple PL done interrupts.
+   		 */
+ ! 		lcd_disable_raster();
+   
+   		lcdc_write(stat, LCD_STAT_REG);
+   
+ --- 1035,1041 ----
+   		 * interrupt via the following write to the status register. If
+   		 * this is done after then one gets multiple PL done interrupts.
+   		 */
+ ! 		lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
+   
+   		lcdc_write(stat, LCD_STAT_REG);
+   
+ ***************
+ *** 822,827 ****
+ --- 1108,1131 ----
+   		var->transp.offset = 0;
+   		var->transp.length = 0;
+   		break;
+ + 	case 24:
+ + 		var->red.offset = 16;
+ + 		var->red.length = 8;
+ + 		var->green.offset = 8;
+ + 		var->green.length = 8;
+ + 		var->blue.offset = 0;
+ + 		var->blue.length = 8;
+ + 		break;
+ + 	case 32:
+ + 		var->transp.offset = 24;
+ + 		var->transp.length = 8;
+ + 		var->red.offset = 16;
+ + 		var->red.length = 8;
+ + 		var->green.offset = 8;
+ + 		var->green.length = 8;
+ + 		var->blue.offset = 0;
+ + 		var->blue.length = 8;
+ + 		break;
+   	default:
+   		err = -EINVAL;
+   	}
+ ***************
+ *** 840,850 ****
+   	struct da8xx_fb_par *par;
+   
+   	par = container_of(nb, struct da8xx_fb_par, freq_transition);
+ ! 	if (val == CPUFREQ_PRECHANGE) {
+ ! 		lcd_disable_raster();
+ ! 	} else if (val == CPUFREQ_POSTCHANGE) {
+ ! 		lcd_calc_clk_divider(par);
+ ! 		lcd_enable_raster();
+   	}
+   
+   	return 0;
+ --- 1144,1155 ----
+   	struct da8xx_fb_par *par;
+   
+   	par = container_of(nb, struct da8xx_fb_par, freq_transition);
+ ! 	if (val == CPUFREQ_POSTCHANGE) {
+ ! 		if (par->lcd_fck_rate != clk_get_rate(par->lcdc_clk)) {
+ ! 			lcd_disable_raster(WAIT_FOR_FRAME_DONE);
+ ! 			lcd_calc_clk_divider(par);
+ ! 			lcd_enable_raster();
+ ! 		}
+   	}
+   
+   	return 0;
+ ***************
+ *** 878,884 ****
+   		if (par->panel_power_ctrl)
+   			par->panel_power_ctrl(0);
+   
+ ! 		lcd_disable_raster();
+   		lcdc_write(0, LCD_RASTER_CTRL_REG);
+   
+   		/* disable DMA  */
+ --- 1183,1189 ----
+   		if (par->panel_power_ctrl)
+   			par->panel_power_ctrl(0);
+   
+ ! 		lcd_disable_raster(WAIT_FOR_FRAME_DONE);
+   		lcdc_write(0, LCD_RASTER_CTRL_REG);
+   
+   		/* disable DMA  */
+ ***************
+ *** 888,898 ****
+   		fb_dealloc_cmap(&info->cmap);
+   		dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
+   				  par->p_palette_base);
+ ! 		dma_free_coherent(NULL, par->vram_size, par->vram_virt,
+ ! 				  par->vram_phys);
+   		free_irq(par->irq, par);
+ ! 		clk_disable(par->lcdc_clk);
+ ! 		clk_put(par->lcdc_clk);
+   		framebuffer_release(info);
+   		iounmap((void __iomem *)da8xx_fb_reg_base);
+   		release_mem_region(lcdc_regs->start, resource_size(lcdc_regs));
+ --- 1193,1211 ----
+   		fb_dealloc_cmap(&info->cmap);
+   		dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
+   				  par->p_palette_base);
+ ! 		if(!par->dma_alloc)
+ ! 		{
+ ! 			iounmap((void __iomem *)par->vram_virt);
+ ! 			release_mem_region(par->vram_phys, par->vram_size);
+ ! 		}
+ ! 		else
+ ! 		{
+ ! 			dma_free_coherent(NULL, par->vram_size, par->vram_virt,
+ ! 					  par->vram_phys);
+ ! 		}
+   		free_irq(par->irq, par);
+ ! 		pm_runtime_put_sync(&dev->dev);
+ ! 		pm_runtime_disable(&dev->dev);
+   		framebuffer_release(info);
+   		iounmap((void __iomem *)da8xx_fb_reg_base);
+   		release_mem_region(lcdc_regs->start, resource_size(lcdc_regs));
+ ***************
+ *** 931,936 ****
+ --- 1244,1257 ----
+   	if (ret == 0)
+   		return -ETIMEDOUT;
+   
+ + 	if (par->panel_power_ctrl) {
+ + 		/* Switch off panel power and backlight */
+ + 		par->panel_power_ctrl(0);
+ + 
+ + 		/* Switch on panel power and backlight */
+ + 		par->panel_power_ctrl(1);
+ + 	}
+ + 
+   	return 0;
+   }
+   
+ ***************
+ *** 987,997 ****
+   
+   		lcd_enable_raster();
+   		break;
+   	case FB_BLANK_POWERDOWN:
+   		if (par->panel_power_ctrl)
+   			par->panel_power_ctrl(0);
+   
+ ! 		lcd_disable_raster();
+   		break;
+   	default:
+   		ret = -EINVAL;
+ --- 1308,1321 ----
+   
+   		lcd_enable_raster();
+   		break;
+ + 	case FB_BLANK_NORMAL:
+ + 	case FB_BLANK_VSYNC_SUSPEND:
+ + 	case FB_BLANK_HSYNC_SUSPEND:
+   	case FB_BLANK_POWERDOWN:
+   		if (par->panel_power_ctrl)
+   			par->panel_power_ctrl(0);
+   
+ ! 		lcd_disable_raster(WAIT_FOR_FRAME_DONE);
+   		break;
+   	default:
+   		ret = -EINVAL;
+ ***************
+ *** 1013,1018 ****
+ --- 1337,1343 ----
+   	struct fb_fix_screeninfo    *fix = &fbi->fix;
+   	unsigned int end;
+   	unsigned int start;
+ + 	unsigned long irq_flags;
+   
+   	if (var->xoffset != fbi->var.xoffset ||
+   			var->yoffset != fbi->var.yoffset) {
+ ***************
+ *** 1030,1041 ****
+ --- 1355,1508 ----
+   			end	= start + fbi->var.yres * fix->line_length - 1;
+   			par->dma_start	= start;
+   			par->dma_end	= end;
+ + 			spin_lock_irqsave(&par->lock_for_chan_update,
+ + 					irq_flags);
+ + 			if (par->which_dma_channel_done == 0) {
+ + 				lcdc_write(par->dma_start,
+ + 					   LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
+ + 				lcdc_write(par->dma_end,
+ + 					   LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
+ + 			} else if (par->which_dma_channel_done == 1) {
+ + 				lcdc_write(par->dma_start,
+ + 					   LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
+ + 				lcdc_write(par->dma_end,
+ + 					   LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
+ + 			}
+ + 			spin_unlock_irqrestore(&par->lock_for_chan_update,
+ + 					irq_flags);
+   		}
+   	}
+   
+   	return ret;
+   }
+   
+ + #if defined(CONFIG_CKB_LCD_SUPPORT) || defined(CONFIG_CKB_DVI_SUPPORT)
+ + int reinit_fb_device(struct fb_info *info, struct da8xx_panel *lcdc_info);
+ + 
+ + /*
+ +  * Switch to a new mode. The parameters for it has been check already by
+ +  * fb_check_var.
+ +  */
+ + static int fb_initialized = 0;
+ + 
+ + 
+ + static int ckb_fb_set_par(struct fb_info *info)
+ + {
+ + 	volatile struct fb_var_screeninfo *var;
+ + 	int i;
+ + 	int matched_index;
+ + #ifdef CONFIG_CKB_DVI_SUPPORT
+ + 	volatile struct fb_videomode *mode;
+ + 	volatile struct fb_videomode *m;
+ + 	
+ + 	volatile unsigned int best_pico_difference = 0xffffffff;
+ + 	volatile unsigned int difference;
+ + #endif
+ + 	if(!fb_initialized)
+ + 	{
+ + 		/* driver not initialized yet */
+ + 		return 0;
+ + 	}
+ + 	if(!info)
+ + 	{
+ + 		return -EINVAL;
+ + 	}
+ + 	var = &info->var;
+ + 	if(!var)
+ + 	{
+ + 		return -EINVAL;
+ + 	}
+ + 
+ + 	printk("Trying to set %dx%d @ %d...\n", var->xres, var->yres, var->pixclock);
+ + #ifdef CONFIG_CKB_DVI_SUPPORT
+ + 	/* check to see if a DVI monitor is connected and the mode is supported by it */
+ + 	if(!get_dvi_info(info))
+ + 	{
+ + 		mode = NULL;
+ + 		for (i=0; i < info->monspecs.modedb_len; i++) 
+ + 		{
+ + 			m = &info->monspecs.modedb[i];
+ + 			if (m->pixclock == 0)
+ + 				continue;
+ + 			/* skip repeated pixel modes */
+ + 			if (m->xres == var->xres && m->yres == var->yres)
+ + 			{
+ + 				/* find the best match for the pico secs */
+ + 				if(m->pixclock < var->pixclock)
+ + 				{
+ + 					difference = var->pixclock - m->pixclock; 
+ + 				}
+ + 				else
+ + 				{
+ + 					difference = m->pixclock - var->pixclock;
+ + 				}
+ + 				if(difference < best_pico_difference)
+ + 				{
+ + 					/* closest match */
+ + 					best_pico_difference = difference;
+ + 					mode = m;
+ + 				}
+ + 			}
+ + 		}
+ + 		if(mode)
+ + 		{
+ + 			struct da8xx_panel dvi_panel;
+ + 			/* fill the DVI mode structure */
+ + 			dvi_panel.width = mode->xres;
+ + 			dvi_panel.hbp = mode->left_margin;
+ + 			dvi_panel.hfp = mode->right_margin;
+ + 			dvi_panel.hsw = mode->hsync_len;
+ + 			dvi_panel.height = mode->yres;
+ + 			dvi_panel.vbp = mode->upper_margin;
+ + 			dvi_panel.vfp = mode->lower_margin;
+ + 			dvi_panel.vsw = mode->vsync_len;
+ + 			
+ + 			dvi_panel.pxl_clk = PICOS2KHZ(mode->pixclock) * 1000;
+ + 			
+ + 			printk("DVI %dx%d @ %dMHz (%d picosecs)\n",
+ + 				dvi_panel.width, dvi_panel.height, dvi_panel.pxl_clk/1000000, mode->pixclock);
+ + 				
+ + 			reinit_fb_device(info, &dvi_panel);
+ + 			return 0;
+ + 		}
+ + 	}
+ + #endif
+ + 
+ + 	/* fall back to FB mode */
+ + 	matched_index = -1;
+ + 	for (i=0; i<ARRAY_SIZE(known_lcd_panels); i++)
+ + 	{
+ + 		/* check for a perfect match, otherwise use the last match */
+ + 		if(var->xres == known_lcd_panels[i].width
+ + 			&& var->yres == known_lcd_panels[i].height)
+ + 		{
+ + 			if(var->hsync_len == known_lcd_panels[i].hsw
+ + 				&&	var->vsync_len == known_lcd_panels[i].vsw
+ + 				&& var->right_margin == known_lcd_panels[i].hfp
+ + 				&& var->left_margin  == known_lcd_panels[i].hbp
+ + 				&& var->lower_margin == known_lcd_panels[i].vfp
+ + 				&& var->upper_margin == known_lcd_panels[i].vbp)
+ + 				{
+ + 					break;
+ + 				}
+ + 			matched_index = i;
+ + 		}
+ + 	}
+ + 	if (i != ARRAY_SIZE(known_lcd_panels)) {
+ + 		printk("Done.\n");
+ + 		reinit_fb_device(info, &known_lcd_panels[i]);
+ + 		return 0;
+ + 	}
+ + 	if(matched_index != -1) {
+ + 		printk("Perfect match not found. Resolution changed to supported panel.\n");
+ + 		reinit_fb_device(info, &known_lcd_panels[matched_index]);
+ + 		return 0;
+ + 	}
+ + 	pr_err("Display resolution not supported.\n");
+ + 	return -EINVAL;
+ + }
+ + #endif
+ + 
+   static struct fb_ops da8xx_fb_ops = {
+   	.owner = THIS_MODULE,
+   	.fb_check_var = fb_check_var,
+ ***************
+ *** 1046,1053 ****
+ --- 1513,1620 ----
+   	.fb_copyarea = cfb_copyarea,
+   	.fb_imageblit = cfb_imageblit,
+   	.fb_blank = cfb_blank,
+ + #if defined(CONFIG_CKB_LCD_SUPPORT) || defined(CONFIG_CKB_DVI_SUPPORT)
+ + 	.fb_set_par = ckb_fb_set_par,
+ + #endif
+   };
+   
+ + /* Calculate and return pixel clock period in pico seconds */
+ + static unsigned int da8xxfb_pixel_clk_period(struct da8xx_fb_par *par)
+ + {
+ + 	unsigned int lcd_clk, div;
+ + 	unsigned int configured_pix_clk;
+ + 	unsigned long long pix_clk_period_picosec = 1000000000000ULL;
+ + 
+ + 	lcd_clk = clk_get_rate(par->lcdc_clk);
+ + 	//printk("*****LCD Clock rate = %d\n",  lcd_clk);
+ + #if defined(CONFIG_LCD_CLOCK_CLOSEST_MATCH)
+ + 	div = get_clk_divider(par);
+ + #else
+ + 	div = lcd_clk / par->pxl_clk;
+ + #endif
+ + 	configured_pix_clk = (lcd_clk / div);
+ + 
+ + 	do_div(pix_clk_period_picosec, configured_pix_clk);
+ + 
+ + 	return pix_clk_period_picosec;
+ + }
+ + 
+ + #if defined(CONFIG_CKB_LCD_SUPPORT) || defined(CONFIG_CKB_DVI_SUPPORT)
+ + int reinit_fb_device(struct fb_info *info, struct da8xx_panel *lcdc_info)
+ + {
+ + 	struct da8xx_fb_par *par;
+ + 	struct device *dev;
+ + 	struct da8xx_lcdc_platform_data *fb_pdata;
+ + 	struct lcd_ctrl_config *lcd_cfg;
+ + 	struct fb_info *da8xx_fb_info;
+ + 
+ + 	par = info->par;
+ + 	dev = par->dev;
+ + 	fb_pdata = dev->platform_data;
+ + 	
+ + 	da8xx_fb_info = dev_get_drvdata(dev);
+ + 	lcd_cfg = (struct lcd_ctrl_config *)par->lcd_cfg;
+ + 
+ + 	par->pxl_clk = lcdc_info->pxl_clk;
+ + 
+ + 	/* disable the raster */		
+ + 	lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
+ + 
+ + 	/* reinitialize the LCD */
+ + 	if (lcd_init(par, lcd_cfg, lcdc_info, 0) < 0) {
+ + 		dev_err(dev, "LCD controller reinit failed\n");
+ + 		return -EFAULT;
+ + 	}
+ + 
+ + 	da8xx_fb_fix.line_length   = (lcdc_info->width * lcd_cfg->bpp) / 8;
+ + 	
+ + 	par->dma_end   = par->dma_start + lcdc_info->height *
+ + 		da8xx_fb_fix.line_length - 1;
+ + 		
+ + 	/* Initialize par */
+ + 	da8xx_fb_info->var.bits_per_pixel = lcd_cfg->bpp;
+ + 
+ + 	da8xx_fb_var.xres = lcdc_info->width;
+ + 	da8xx_fb_var.xres_virtual = lcdc_info->width;
+ + 
+ + 	da8xx_fb_var.yres         = lcdc_info->height;
+ + 	da8xx_fb_var.yres_virtual = lcdc_info->height * LCD_NUM_BUFFERS;
+ + 
+ + 	da8xx_fb_var.grayscale =
+ + 	    lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
+ + 
+ + 	da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp;
+ + 
+ + 	da8xx_fb_var.hsync_len = lcdc_info->hsw;
+ + 	da8xx_fb_var.vsync_len = lcdc_info->vsw;
+ + 
+ + 	da8xx_fb_var.pixclock = da8xxfb_pixel_clk_period(par);
+ + 	
+ + 	da8xx_fb_var.right_margin = lcdc_info->hfp;
+ + 	da8xx_fb_var.left_margin  = lcdc_info->hbp;
+ + 	da8xx_fb_var.lower_margin = lcdc_info->vfp;
+ + 	da8xx_fb_var.upper_margin = lcdc_info->vbp;
+ + 
+ + 	
+ + 	/* Initialize fbinfo */
+ + 	da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
+ + 	da8xx_fb_info->fix = da8xx_fb_fix;
+ + 	da8xx_fb_info->var = da8xx_fb_var;
+ + 	da8xx_fb_info->fbops = &da8xx_fb_ops;
+ + 
+ + 	da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
+ + 				FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
+ + 
+ + 	/* initialize var_screeninfo */
+ + 	da8xx_fb_var.activate = FB_ACTIVATE_FORCE;
+ + //	fb_set_var(da8xx_fb_info, &da8xx_fb_var);
+ + 
+ + 
+ + 	lcd_enable_raster();
+ + 	return 0;
+ + }
+ + #endif
+ + 
+   static int __devinit fb_probe(struct platform_device *device)
+   {
+   	struct da8xx_lcdc_platform_data *fb_pdata =
+ ***************
+ *** 1059,1065 ****
+   	struct da8xx_fb_par *par;
+   	resource_size_t len;
+   	int ret, i;
+ ! 
+   	if (fb_pdata == NULL) {
+   		dev_err(&device->dev, "Can not get platform data\n");
+   		return -ENOENT;
+ --- 1626,1635 ----
+   	struct da8xx_fb_par *par;
+   	resource_size_t len;
+   	int ret, i;
+ ! 	unsigned long ulcm;
+ ! #if defined(CONFIG_CKB_LCD_SUPPORT) || defined(CONFIG_CKB_DVI_SUPPORT)
+ ! 	fb_initialized = 0;
+ ! #endif
+   	if (fb_pdata == NULL) {
+   		dev_err(&device->dev, "Can not get platform data\n");
+   		return -ENOENT;
+ ***************
+ *** 1090,1105 ****
+   		ret = -ENODEV;
+   		goto err_ioremap;
+   	}
+ - 	ret = clk_enable(fb_clk);
+ - 	if (ret)
+ - 		goto err_clk_put;
+   
+   	/* Determine LCD IP Version */
+   	switch (lcdc_read(LCD_PID_REG)) {
+   	case 0x4C100102:
+   		lcd_revision = LCD_VERSION_1;
+   		break;
+   	case 0x4F200800:
+   		lcd_revision = LCD_VERSION_2;
+   		break;
+   	default:
+ --- 1660,1677 ----
+   		ret = -ENODEV;
+   		goto err_ioremap;
+   	}
+   
+ + 	pm_runtime_irq_safe(&device->dev);
+ + 	pm_runtime_enable(&device->dev);
+ + 	pm_runtime_get_sync(&device->dev);
+ + 	
+   	/* Determine LCD IP Version */
+   	switch (lcdc_read(LCD_PID_REG)) {
+   	case 0x4C100102:
+   		lcd_revision = LCD_VERSION_1;
+   		break;
+   	case 0x4F200800:
+ + 	case 0x4F201000:
+   		lcd_revision = LCD_VERSION_2;
+   		break;
+   	default:
+ ***************
+ *** 1120,1168 ****
+   	if (i == ARRAY_SIZE(known_lcd_panels)) {
+   		dev_err(&device->dev, "GLCD: No valid panel found\n");
+   		ret = -ENODEV;
+ ! 		goto err_clk_disable;
+   	} else
+   		dev_info(&device->dev, "GLCD: Found %s panel\n",
+   					fb_pdata->type);
+   
+   	lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;
+ ! 
+   	da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par),
+   					&device->dev);
+   	if (!da8xx_fb_info) {
+   		dev_dbg(&device->dev, "Memory allocation failed for fb_info\n");
+   		ret = -ENOMEM;
+ ! 		goto err_clk_disable;
+   	}
+ ! 
+   	par = da8xx_fb_info->par;
+   	par->lcdc_clk = fb_clk;
+   	par->pxl_clk = lcdc_info->pxl_clk;
+   	if (fb_pdata->panel_power_ctrl) {
+   		par->panel_power_ctrl = fb_pdata->panel_power_ctrl;
+   		par->panel_power_ctrl(1);
+   	}
+   
+ ! 	if (lcd_init(par, lcd_cfg, lcdc_info) < 0) {
+   		dev_err(&device->dev, "lcd_init failed\n");
+   		ret = -EFAULT;
+   		goto err_release_fb;
+   	}
+ - 
+   	/* allocate frame buffer */
+   	par->vram_size = lcdc_info->width * lcdc_info->height * lcd_cfg->bpp;
+ ! 	par->vram_size = PAGE_ALIGN(par->vram_size/8);
+   	par->vram_size = par->vram_size * LCD_NUM_BUFFERS;
+ ! 
+ ! 	par->vram_virt = dma_alloc_coherent(NULL,
+   					    par->vram_size,
+   					    (resource_size_t *) &par->vram_phys,
+   					    GFP_KERNEL | GFP_DMA);
+   	if (!par->vram_virt) {
+   		dev_err(&device->dev,
+   			"GLCD: kmalloc for frame buffer failed\n");
+   		ret = -EINVAL;
+ ! 		goto err_release_fb;
+   	}
+   
+   	da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt;
+ --- 1692,1769 ----
+   	if (i == ARRAY_SIZE(known_lcd_panels)) {
+   		dev_err(&device->dev, "GLCD: No valid panel found\n");
+   		ret = -ENODEV;
+ ! 		goto err_pm_runtime_disable;
+   	} else
+   		dev_info(&device->dev, "GLCD: Found %s panel\n",
+   					fb_pdata->type);
+   
+   	lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;
+ ! 	
+   	da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par),
+   					&device->dev);
+   	if (!da8xx_fb_info) {
+   		dev_dbg(&device->dev, "Memory allocation failed for fb_info\n");
+   		ret = -ENOMEM;
+ ! 		goto err_pm_runtime_disable;
+   	}
+ ! 	
+   	par = da8xx_fb_info->par;
+ + 	par->dev = &device->dev;
+   	par->lcdc_clk = fb_clk;
+ + #ifdef CONFIG_CPU_FREQ
+ + 	par->lcd_fck_rate = clk_get_rate(fb_clk);
+ + #endif
+   	par->pxl_clk = lcdc_info->pxl_clk;
+   	if (fb_pdata->panel_power_ctrl) {
+   		par->panel_power_ctrl = fb_pdata->panel_power_ctrl;
+   		par->panel_power_ctrl(1);
+   	}
+   
+ ! #if defined(CONFIG_CKB_LCD_SUPPORT) || defined(CONFIG_CKB_DVI_SUPPORT)
+ ! 	par->lcd_cfg = lcd_cfg;
+ ! 	if (lcd_init(par, lcd_cfg, lcdc_info, 0) < 0) {
+ ! #else
+ ! 	if (lcd_init(par, lcd_cfg, lcdc_info, 1) < 0) {
+ ! #endif
+   		dev_err(&device->dev, "lcd_init failed\n");
+   		ret = -EFAULT;
+   		goto err_release_fb;
+   	}
+   	/* allocate frame buffer */
+   	par->vram_size = lcdc_info->width * lcdc_info->height * lcd_cfg->bpp;
+ ! 	ulcm = lcm((lcdc_info->width * lcd_cfg->bpp)/8, PAGE_SIZE);
+ ! 	
+ ! 	par->vram_size = roundup(par->vram_size/8, ulcm);
+   	par->vram_size = par->vram_size * LCD_NUM_BUFFERS;
+ ! 	
+ ! 	if(fb_pdata->fb_mapped_physaddr != 0 && par->vram_size <= fb_pdata->fb_mapped_len)
+ ! 	{
+ ! 		/* use mapped address */
+ ! 		par->vram_phys = fb_pdata->fb_mapped_physaddr;
+ ! 		if (!request_mem_region(par->vram_phys, par->vram_size, "FB_mem"))
+ ! 		{
+ ! 			dev_err(&device->dev,
+ ! 				"Memory request for FB failed\n");
+ ! 			ret = -EFAULT;
+ ! 			goto err_release_fb;
+ ! 		}
+ ! 		par->dma_alloc = 0;
+ ! 		par->vram_virt = ioremap(par->vram_phys, par->vram_size);
+ ! 	}
+ ! 	else
+ ! 	{
+ ! 		/* map address from RAM */
+ ! 		par->vram_virt = dma_alloc_coherent(NULL,
+   					    par->vram_size,
+   					    (resource_size_t *) &par->vram_phys,
+   					    GFP_KERNEL | GFP_DMA);
+ + 		par->dma_alloc = 1;
+ + 	}
+   	if (!par->vram_virt) {
+   		dev_err(&device->dev,
+   			"GLCD: kmalloc for frame buffer failed\n");
+   		ret = -EINVAL;
+ ! 		goto err_release_fb_request;
+   	}
+   
+   	da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt;
+ ***************
+ *** 1209,1214 ****
+ --- 1810,1822 ----
+   
+   	da8xx_fb_var.hsync_len = lcdc_info->hsw;
+   	da8xx_fb_var.vsync_len = lcdc_info->vsw;
+ + 	
+ + 	da8xx_fb_var.pixclock = da8xxfb_pixel_clk_period(par);
+ + 
+ + 	da8xx_fb_var.right_margin = lcdc_info->hfp;
+ + 	da8xx_fb_var.left_margin  = lcdc_info->hbp;
+ + 	da8xx_fb_var.lower_margin = lcdc_info->vfp;
+ + 	da8xx_fb_var.upper_margin = lcdc_info->vbp;
+   
+   	/* Initialize fbinfo */
+   	da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
+ ***************
+ *** 1229,1238 ****
+   	fb_set_var(da8xx_fb_info, &da8xx_fb_var);
+   
+   	dev_set_drvdata(&device->dev, da8xx_fb_info);
+ ! 
+   	/* initialize the vsync wait queue */
+   	init_waitqueue_head(&par->vsync_wait);
+   	par->vsync_timeout = HZ / 5;
+   
+   	/* Register the Frame Buffer  */
+   	if (register_framebuffer(da8xx_fb_info) < 0) {
+ --- 1837,1848 ----
+   	fb_set_var(da8xx_fb_info, &da8xx_fb_var);
+   
+   	dev_set_drvdata(&device->dev, da8xx_fb_info);
+ ! 	
+   	/* initialize the vsync wait queue */
+   	init_waitqueue_head(&par->vsync_wait);
+   	par->vsync_timeout = HZ / 5;
+ + 	par->which_dma_channel_done = -1;
+ + 	spin_lock_init(&par->lock_for_chan_update);
+   
+   	/* Register the Frame Buffer  */
+   	if (register_framebuffer(da8xx_fb_info) < 0) {
+ ***************
+ *** 1242,1247 ****
+ --- 1852,1858 ----
+   		goto err_dealloc_cmap;
+   	}
+   
+ + 
+   #ifdef CONFIG_CPU_FREQ
+   	ret = lcd_da8xx_cpufreq_register(par);
+   	if (ret) {
+ ***************
+ *** 1259,1271 ****
+   			DRIVER_NAME, par);
+   	if (ret)
+   		goto irq_freq;
+   	return 0;
+   
+   irq_freq:
+   #ifdef CONFIG_CPU_FREQ
+   	lcd_da8xx_cpufreq_deregister(par);
+ - #endif
+   err_cpu_freq:
+   	unregister_framebuffer(da8xx_fb_info);
+   
+   err_dealloc_cmap:
+ --- 1870,1889 ----
+   			DRIVER_NAME, par);
+   	if (ret)
+   		goto irq_freq;
+ + 
+ + #if defined(CONFIG_CKB_LCD_SUPPORT) || defined(CONFIG_CKB_DVI_SUPPORT)
+ + 	fb_initialized = 1; 
+ + 	set_fb_panel_info(known_lcd_panels, ARRAY_SIZE(known_lcd_panels), lcd_cfg->bpp);
+ + 	append_fb_mode();
+ + 	close_video_mode_file();
+ + #endif
+   	return 0;
+   
+   irq_freq:
+   #ifdef CONFIG_CPU_FREQ
+   	lcd_da8xx_cpufreq_deregister(par);
+   err_cpu_freq:
+ + #endif
+   	unregister_framebuffer(da8xx_fb_info);
+   
+   err_dealloc_cmap:
+ ***************
+ *** 1276,1293 ****
+   			  par->p_palette_base);
+   
+   err_release_fb_mem:
+ ! 	dma_free_coherent(NULL, par->vram_size, par->vram_virt, par->vram_phys);
+ ! 
+   err_release_fb:
+   	framebuffer_release(da8xx_fb_info);
+   
+ ! err_clk_disable:
+ ! 	clk_disable(fb_clk);
+ ! 
+ ! err_clk_put:
+ ! 	clk_put(fb_clk);
+   
+   err_ioremap:
+   	iounmap((void __iomem *)da8xx_fb_reg_base);
+   
+   err_request_mem:
+ --- 1894,1915 ----
+   			  par->p_palette_base);
+   
+   err_release_fb_mem:
+ ! 	if(!par->dma_alloc)
+ ! 		iounmap((void __iomem *)par->vram_virt);
+ ! 	else
+ ! 		dma_free_coherent(NULL, par->vram_size, par->vram_virt, par->vram_phys);
+ ! err_release_fb_request:
+ ! 	if(!par->dma_alloc)
+ ! 		release_mem_region(par->vram_phys, par->vram_size);
+   err_release_fb:
+   	framebuffer_release(da8xx_fb_info);
+   
+ ! err_pm_runtime_disable:
+ ! 	pm_runtime_put_sync(&device->dev);
+ ! 	pm_runtime_disable(&device->dev);
+   
+   err_ioremap:
+ + 
+   	iounmap((void __iomem *)da8xx_fb_reg_base);
+   
+   err_request_mem:
+ ***************
+ *** 1297,1302 ****
+ --- 1919,1982 ----
+   }
+   
+   #ifdef CONFIG_PM
+ + 
+ + struct lcdc_context {
+ + 	u32 clk_enable;
+ + 	u32 ctrl;
+ + 	u32 dma_ctrl;
+ + 	u32 raster_timing_0;
+ + 	u32 raster_timing_1;
+ + 	u32 raster_timing_2;
+ + 	u32 int_enable_set;
+ + 	u32 dma_frm_buf_base_addr_0;
+ + 	u32 dma_frm_buf_ceiling_addr_0;
+ + 	u32 dma_frm_buf_base_addr_1;
+ + 	u32 dma_frm_buf_ceiling_addr_1;
+ + 	u32 raster_ctrl;
+ + } reg_context;
+ + 
+ + static void lcd_context_save(void)
+ + {
+ + 	reg_context.clk_enable = lcdc_read(LCD_CLK_ENABLE_REG);
+ + 	reg_context.ctrl = lcdc_read(LCD_CTRL_REG);
+ + 	reg_context.dma_ctrl = lcdc_read(LCD_DMA_CTRL_REG);
+ + 	reg_context.raster_timing_0 = lcdc_read(LCD_RASTER_TIMING_0_REG);
+ + 	reg_context.raster_timing_1 = lcdc_read(LCD_RASTER_TIMING_1_REG);
+ + 	reg_context.raster_timing_2 = lcdc_read(LCD_RASTER_TIMING_2_REG);
+ + 	reg_context.int_enable_set = lcdc_read(LCD_INT_ENABLE_SET_REG);
+ + 	reg_context.dma_frm_buf_base_addr_0 =
+ + 		lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
+ + 	reg_context.dma_frm_buf_ceiling_addr_0 =
+ + 		lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
+ + 	reg_context.dma_frm_buf_base_addr_1 =
+ + 		lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
+ + 	reg_context.dma_frm_buf_ceiling_addr_1 =
+ + 		lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
+ + 	reg_context.raster_ctrl = lcdc_read(LCD_RASTER_CTRL_REG);
+ + 	return;
+ + }
+ + 
+ + static void lcd_context_restore(void)
+ + {
+ + 	lcdc_write(reg_context.clk_enable, LCD_CLK_ENABLE_REG);
+ + 	lcdc_write(reg_context.ctrl, LCD_CTRL_REG);
+ + 	lcdc_write(reg_context.dma_ctrl, LCD_DMA_CTRL_REG);
+ + 	lcdc_write(reg_context.raster_timing_0, LCD_RASTER_TIMING_0_REG);
+ + 	lcdc_write(reg_context.raster_timing_1, LCD_RASTER_TIMING_1_REG);
+ + 	lcdc_write(reg_context.raster_timing_2, LCD_RASTER_TIMING_2_REG);
+ + 	lcdc_write(reg_context.int_enable_set, LCD_INT_ENABLE_SET_REG);
+ + 	lcdc_write(reg_context.dma_frm_buf_base_addr_0,
+ + 			LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
+ + 	lcdc_write(reg_context.dma_frm_buf_ceiling_addr_0,
+ + 			LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
+ + 	lcdc_write(reg_context.dma_frm_buf_base_addr_1,
+ + 			LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
+ + 	lcdc_write(reg_context.dma_frm_buf_ceiling_addr_1,
+ + 			LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
+ + 	lcdc_write(reg_context.raster_ctrl, LCD_RASTER_CTRL_REG);
+ + 	return;
+ + }
+ + 
+   static int fb_suspend(struct platform_device *dev, pm_message_t state)
+   {
+   	struct fb_info *info = platform_get_drvdata(dev);
+ ***************
+ *** 1307,1314 ****
+   		par->panel_power_ctrl(0);
+   
+   	fb_set_suspend(info, 1);
+ ! 	lcd_disable_raster();
+ ! 	clk_disable(par->lcdc_clk);
+   	console_unlock();
+   
+   	return 0;
+ --- 1987,1996 ----
+   		par->panel_power_ctrl(0);
+   
+   	fb_set_suspend(info, 1);
+ ! 	lcd_disable_raster(WAIT_FOR_FRAME_DONE);
+ ! 	lcd_context_save();
+ ! 
+ ! 	pm_runtime_put(&dev->dev);
+   	console_unlock();
+   
+   	return 0;
+ ***************
+ *** 1319,1329 ****
+   	struct da8xx_fb_par *par = info->par;
+   
+   	console_lock();
+   	if (par->panel_power_ctrl)
+   		par->panel_power_ctrl(1);
+   
+ - 	clk_enable(par->lcdc_clk);
+ - 	lcd_enable_raster();
+   	fb_set_suspend(info, 0);
+   	console_unlock();
+   
+ --- 2001,2016 ----
+   	struct da8xx_fb_par *par = info->par;
+   
+   	console_lock();
+ + 
+ + 	pm_runtime_get_sync(&dev->dev);
+ + 
+ + 	msleep(1);
+ + 	lcd_context_restore();
+ + 	lcd_enable_raster();
+ + 
+   	if (par->panel_power_ctrl)
+   		par->panel_power_ctrl(1);
+   
+   	fb_set_suspend(info, 0);
+   	console_unlock();
+   
+ diff -crN linux-3.2.1_o/drivers/video/fb_ddc.c linux-3.2.1/drivers/video/fb_ddc.c
+ *** linux-3.2.1_o/drivers/video/fb_ddc.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/video/fb_ddc.c	2014-11-25 13:19:16.951106064 +0900
+ ***************
+ *** 19,25 ****
+ --- 19,29 ----
+   
+   #define DDC_ADDR	0x50
+   
+ + #ifdef CONFIG_CKB_DVI_SUPPORT	
+ + unsigned char *fb_do_probe_ddc_edid(struct i2c_adapter *adapter)
+ + #else
+   static unsigned char *fb_do_probe_ddc_edid(struct i2c_adapter *adapter)
+ + #endif
+   {
+   	unsigned char start = 0x0;
+   	unsigned char *buf = kmalloc(EDID_LENGTH, GFP_KERNEL);
+ diff -crN linux-3.2.1_o/drivers/video/fbmem.c linux-3.2.1/drivers/video/fbmem.c
+ *** linux-3.2.1_o/drivers/video/fbmem.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/video/fbmem.c	2014-11-25 13:19:16.960684691 +0900
+ ***************
+ *** 1913,1918 ****
+ --- 1913,1920 ----
+   __setup("video=", video_setup);
+   #endif
+   
+ + 
+ + 
+       /*
+        *  Visible symbols for modules
+        */
+ diff -crN linux-3.2.1_o/drivers/video/Kconfig linux-3.2.1/drivers/video/Kconfig
+ *** linux-3.2.1_o/drivers/video/Kconfig	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/video/Kconfig	2014-11-25 13:19:17.019085130 +0900
+ ***************
+ *** 30,36 ****
+   config VIDEO_OUTPUT_CONTROL
+   	tristate "Lowlevel video output switch controls"
+   	help
+ ! 	  This framework adds support for low-level control of the video 
+   	  output switch.
+   
+   menuconfig FB
+ --- 30,36 ----
+   config VIDEO_OUTPUT_CONTROL
+   	tristate "Lowlevel video output switch controls"
+   	help
+ ! 	  This framework adds support for low-level control of the video
+   	  output switch.
+   
+   menuconfig FB
+ ***************
+ *** 691,697 ****
+   	  BIOS routines contained in a ROM chip in HP PA-RISC based machines.
+   	  Enabling this option will implement the linux framebuffer device
+   	  using calls to the STI BIOS routines for initialisation.
+ ! 	
+   	  If you enable this option, you will get a planar framebuffer device
+   	  /dev/fb which will work on the most common HP graphic cards of the
+   	  NGLE family, including the artist chips (in the 7xx and Bxxx series),
+ --- 691,697 ----
+   	  BIOS routines contained in a ROM chip in HP PA-RISC based machines.
+   	  Enabling this option will implement the linux framebuffer device
+   	  using calls to the STI BIOS routines for initialisation.
+ ! 
+   	  If you enable this option, you will get a planar framebuffer device
+   	  /dev/fb which will work on the most common HP graphic cards of the
+   	  NGLE family, including the artist chips (in the 7xx and Bxxx series),
+ ***************
+ *** 1132,1167 ****
+   	select FB_CFB_IMAGEBLIT
+   	select VGASTATE
+   	help
+ ! 	  This driver supports the on-board graphics built in to the Intel 810 
+             and 815 chipsets.  Say Y if you have and plan to use such a board.
+   
+             To compile this driver as a module, choose M here: the
+   	  module will be called i810fb.
+   
+ !           For more information, please read 
+   	  <file:Documentation/fb/intel810.txt>
+   
+   config FB_I810_GTF
+   	bool "use VESA Generalized Timing Formula"
+   	depends on FB_I810
+   	help
+ ! 	  If you say Y, then the VESA standard, Generalized Timing Formula 
+             or GTF, will be used to calculate the required video timing values
+ ! 	  per video mode.  Since the GTF allows nondiscrete timings 
+             (nondiscrete being a range of values as opposed to discrete being a
+ !           set of values), you'll be able to use any combination of horizontal 
+   	  and vertical resolutions, and vertical refresh rates without having
+   	  to specify your own timing parameters.  This is especially useful
+ ! 	  to maximize the performance of an aging display, or if you just 
+ !           have a display with nonstandard dimensions. A VESA compliant 
+   	  monitor is recommended, but can still work with non-compliant ones.
+ ! 	  If you need or want this, then select this option. The timings may 
+ ! 	  not be compliant with Intel's recommended values. Use at your own 
+   	  risk.
+   
+ !           If you say N, the driver will revert to discrete video timings 
+   	  using a set recommended by Intel in their documentation.
+ !   
+             If unsure, say N.
+   
+   config FB_I810_I2C
+ --- 1132,1167 ----
+   	select FB_CFB_IMAGEBLIT
+   	select VGASTATE
+   	help
+ ! 	  This driver supports the on-board graphics built in to the Intel 810
+             and 815 chipsets.  Say Y if you have and plan to use such a board.
+   
+             To compile this driver as a module, choose M here: the
+   	  module will be called i810fb.
+   
+ !           For more information, please read
+   	  <file:Documentation/fb/intel810.txt>
+   
+   config FB_I810_GTF
+   	bool "use VESA Generalized Timing Formula"
+   	depends on FB_I810
+   	help
+ ! 	  If you say Y, then the VESA standard, Generalized Timing Formula
+             or GTF, will be used to calculate the required video timing values
+ ! 	  per video mode.  Since the GTF allows nondiscrete timings
+             (nondiscrete being a range of values as opposed to discrete being a
+ !           set of values), you'll be able to use any combination of horizontal
+   	  and vertical resolutions, and vertical refresh rates without having
+   	  to specify your own timing parameters.  This is especially useful
+ ! 	  to maximize the performance of an aging display, or if you just
+ !           have a display with nonstandard dimensions. A VESA compliant
+   	  monitor is recommended, but can still work with non-compliant ones.
+ ! 	  If you need or want this, then select this option. The timings may
+ ! 	  not be compliant with Intel's recommended values. Use at your own
+   	  risk.
+   
+ !           If you say N, the driver will revert to discrete video timings
+   	  using a set recommended by Intel in their documentation.
+ ! 
+             If unsure, say N.
+   
+   config FB_I810_I2C
+ ***************
+ *** 1279,1288 ****
+   	  G450/G550 secondary head and digital output are supported without
+   	  additional modules.
+   
+ ! 	  The driver starts in monitor mode. You must use the matroxset tool 
+ ! 	  (available at <ftp://platan.vc.cvut.cz/pub/linux/matrox-latest/>) to 
+ ! 	  swap primary and secondary head outputs, or to change output mode.  
+ ! 	  Secondary head driver always start in 640x480 resolution and you 
+   	  must use fbset to change it.
+   
+   	  Do not forget that second head supports only 16 and 32 bpp
+ --- 1279,1288 ----
+   	  G450/G550 secondary head and digital output are supported without
+   	  additional modules.
+   
+ ! 	  The driver starts in monitor mode. You must use the matroxset tool
+ ! 	  (available at <ftp://platan.vc.cvut.cz/pub/linux/matrox-latest/>) to
+ ! 	  swap primary and secondary head outputs, or to change output mode.
+ ! 	  Secondary head driver always start in 640x480 resolution and you
+   	  must use fbset to change it.
+   
+   	  Do not forget that second head supports only 16 and 32 bpp
+ ***************
+ *** 1365,1371 ****
+   	select FB_DDC
+   	default y
+   	help
+ ! 	  Say Y here if you want DDC/I2C support for your Radeon board. 
+   
+   config FB_RADEON_BACKLIGHT
+   	bool "Support for backlight control"
+ --- 1365,1371 ----
+   	select FB_DDC
+   	default y
+   	help
+ ! 	  Say Y here if you want DDC/I2C support for your Radeon board.
+   
+   config FB_RADEON_BACKLIGHT
+   	bool "Support for backlight control"
+ ***************
+ *** 1599,1605 ****
+   	select VGASTATE
+   	help
+   	  This driver supports notebooks with NeoMagic PCI chips.
+ ! 	  Say Y if you have such a graphics card. 
+   
+   	  To compile this driver as a module, choose M here: the
+   	  module will be called neofb.
+ --- 1599,1605 ----
+   	select VGASTATE
+   	help
+   	  This driver supports notebooks with NeoMagic PCI chips.
+ ! 	  Say Y if you have such a graphics card.
+   
+   	  To compile this driver as a module, choose M here: the
+   	  module will be called neofb.
+ ***************
+ *** 1654,1660 ****
+   	select FB_CFB_COPYAREA
+   	select FB_CFB_IMAGEBLIT
+   	---help---
+ ! 	  Say Y here if you have a 3Dfx Voodoo Graphics (Voodoo1/sst1) or 
+   	  Voodoo2 (cvg) based graphics card.
+   
+   	  To compile this driver as a module, choose M here: the
+ --- 1654,1660 ----
+   	select FB_CFB_COPYAREA
+   	select FB_CFB_IMAGEBLIT
+   	---help---
+ ! 	  Say Y here if you have a 3Dfx Voodoo Graphics (Voodoo1/sst1) or
+   	  Voodoo2 (cvg) based graphics card.
+   
+   	  To compile this driver as a module, choose M here: the
+ ***************
+ *** 2229,2235 ****
+   
+   config FB_DA8XX
+   	tristate "DA8xx/OMAP-L1xx Framebuffer support"
+ ! 	depends on FB && ARCH_DAVINCI_DA8XX
+   	select FB_CFB_FILLRECT
+   	select FB_CFB_COPYAREA
+   	select FB_CFB_IMAGEBLIT
+ --- 2229,2235 ----
+   
+   config FB_DA8XX
+   	tristate "DA8xx/OMAP-L1xx Framebuffer support"
+ ! 	depends on FB && (ARCH_DAVINCI_DA8XX || SOC_OMAPAM33XX || ARCH_CKB)
+   	select FB_CFB_FILLRECT
+   	select FB_CFB_COPYAREA
+   	select FB_CFB_IMAGEBLIT
+ diff -crN linux-3.2.1_o/drivers/video/Makefile linux-3.2.1/drivers/video/Makefile
+ *** linux-3.2.1_o/drivers/video/Makefile	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/video/Makefile	2014-11-25 13:19:17.023131386 +0900
+ ***************
+ *** 13,19 ****
+   
+   obj-$(CONFIG_VT)		  += console/
+   obj-$(CONFIG_LOGO)		  += logo/
+ ! obj-y				  += backlight/ display/
+   
+   obj-$(CONFIG_FB_CFB_FILLRECT)  += cfbfillrect.o
+   obj-$(CONFIG_FB_CFB_COPYAREA)  += cfbcopyarea.o
+ --- 13,19 ----
+   
+   obj-$(CONFIG_VT)		  += console/
+   obj-$(CONFIG_LOGO)		  += logo/
+ ! obj-y				  += backlight/ display/ ckb/
+   
+   obj-$(CONFIG_FB_CFB_FILLRECT)  += cfbfillrect.o
+   obj-$(CONFIG_FB_CFB_COPYAREA)  += cfbcopyarea.o
+ ***************
+ *** 136,141 ****
+ --- 136,142 ----
+   obj-$(CONFIG_FB_SH_MOBILE_LCDC)	  += sh_mobile_lcdcfb.o
+   obj-$(CONFIG_FB_OMAP)             += omap/
+   obj-y                             += omap2/
+ + obj-$(CONFIG_CKB_TFP410)          += ckb/
+   obj-$(CONFIG_XEN_FBDEV_FRONTEND)  += xen-fbfront.o
+   obj-$(CONFIG_FB_CARMINE)          += carminefb.o
+   obj-$(CONFIG_FB_MB862XX)	  += mb862xx/
+ ***************
+ *** 158,163 ****
+ --- 159,165 ----
+   obj-$(CONFIG_FB_MX3)		  += mx3fb.o
+   obj-$(CONFIG_FB_DA8XX)		  += da8xx-fb.o
+   obj-$(CONFIG_FB_MXS)		  += mxsfb.o
+ + obj-$(CONFIG_CKB_3352_HDMI)	  += ckb/
+   
+   # the test framebuffer is last
+   obj-$(CONFIG_FB_VIRTUAL)          += vfb.o
+ diff -crN linux-3.2.1_o/drivers/video/offb.c linux-3.2.1/drivers/video/offb.c
+ *** linux-3.2.1_o/drivers/video/offb.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/video/offb.c	2014-11-25 13:19:17.027079592 +0900
+ ***************
+ *** 100,131 ****
+   			  u_int transp, struct fb_info *info)
+   {
+   	struct offb_par *par = (struct offb_par *) info->par;
+   
+ ! 	if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
+ ! 		u32 *pal = info->pseudo_palette;
+ ! 		u32 cr = red >> (16 - info->var.red.length);
+ ! 		u32 cg = green >> (16 - info->var.green.length);
+ ! 		u32 cb = blue >> (16 - info->var.blue.length);
+ ! 		u32 value;
+ ! 
+ ! 		if (regno >= 16)
+ ! 			return -EINVAL;
+ ! 
+ ! 		value = (cr << info->var.red.offset) |
+ ! 			(cg << info->var.green.offset) |
+ ! 			(cb << info->var.blue.offset);
+ ! 		if (info->var.transp.length > 0) {
+ ! 			u32 mask = (1 << info->var.transp.length) - 1;
+ ! 			mask <<= info->var.transp.offset;
+ ! 			value |= mask;
+   		}
+ - 		pal[regno] = value;
+ - 		return 0;
+   	}
+   
+ - 	if (regno > 255)
+ - 		return -EINVAL;
+ - 
+   	red >>= 8;
+   	green >>= 8;
+   	blue >>= 8;
+ --- 100,135 ----
+   			  u_int transp, struct fb_info *info)
+   {
+   	struct offb_par *par = (struct offb_par *) info->par;
+ + 	int i, depth;
+ + 	u32 *pal = info->pseudo_palette;
+   
+ ! 	depth = info->var.bits_per_pixel;
+ ! 	if (depth == 16)
+ ! 		depth = (info->var.green.length == 5) ? 15 : 16;
+ ! 
+ ! 	if (regno > 255 ||
+ ! 	    (depth == 16 && regno > 63) ||
+ ! 	    (depth == 15 && regno > 31))
+ ! 		return 1;
+ ! 
+ ! 	if (regno < 16) {
+ ! 		switch (depth) {
+ ! 		case 15:
+ ! 			pal[regno] = (regno << 10) | (regno << 5) | regno;
+ ! 			break;
+ ! 		case 16:
+ ! 			pal[regno] = (regno << 11) | (regno << 5) | regno;
+ ! 			break;
+ ! 		case 24:
+ ! 			pal[regno] = (regno << 16) | (regno << 8) | regno;
+ ! 			break;
+ ! 		case 32:
+ ! 			i = (regno << 8) | regno;
+ ! 			pal[regno] = (i << 16) | i;
+ ! 			break;
+   		}
+   	}
+   
+   	red >>= 8;
+   	green >>= 8;
+   	blue >>= 8;
+ ***************
+ *** 377,383 ****
+   				int pitch, unsigned long address,
+   				int foreign_endian, struct device_node *dp)
+   {
+ ! 	unsigned long res_size = pitch * height;
+   	struct offb_par *par = &default_par;
+   	unsigned long res_start = address;
+   	struct fb_fix_screeninfo *fix;
+ --- 381,387 ----
+   				int pitch, unsigned long address,
+   				int foreign_endian, struct device_node *dp)
+   {
+ ! 	unsigned long res_size = pitch * height * (depth + 7) / 8;
+   	struct offb_par *par = &default_par;
+   	unsigned long res_start = address;
+   	struct fb_fix_screeninfo *fix;
+ diff -crN linux-3.2.1_o/drivers/watchdog/Kconfig linux-3.2.1/drivers/watchdog/Kconfig
+ *** linux-3.2.1_o/drivers/watchdog/Kconfig	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/watchdog/Kconfig	2014-11-25 14:10:28.670760000 +0900
+ ***************
+ *** 226,232 ****
+   
+   config OMAP_WATCHDOG
+   	tristate "OMAP Watchdog"
+ ! 	depends on ARCH_OMAP16XX || ARCH_OMAP2PLUS
+   	help
+   	  Support for TI OMAP1610/OMAP1710/OMAP2420/OMAP3430/OMAP4430 watchdog.  Say 'Y'
+   	  here to enable the OMAP1610/OMAP1710/OMAP2420/OMAP3430/OMAP4430 watchdog timer.
+ --- 226,232 ----
+   
+   config OMAP_WATCHDOG
+   	tristate "OMAP Watchdog"
+ ! 	depends on ARCH_OMAP16XX || ARCH_OMAP2PLUS || MACH_CKB_3352 
+   	help
+   	  Support for TI OMAP1610/OMAP1710/OMAP2420/OMAP3430/OMAP4430 watchdog.  Say 'Y'
+   	  here to enable the OMAP1610/OMAP1710/OMAP2420/OMAP3430/OMAP4430 watchdog timer.
+ diff -crN linux-3.2.1_o/drivers/watchdog/omap_wdt.c linux-3.2.1/drivers/watchdog/omap_wdt.c
+ *** linux-3.2.1_o/drivers/watchdog/omap_wdt.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/drivers/watchdog/omap_wdt.c	2014-11-25 13:19:17.031078257 +0900
+ ***************
+ *** 124,131 ****
+   	u32 pre_margin = GET_WLDR_VAL(timer_margin);
+   	void __iomem *base = wdev->base;
+   
+ - 	pm_runtime_get_sync(wdev->dev);
+ - 
+   	/* just count up at 32 KHz */
+   	while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
+   		cpu_relax();
+ --- 124,129 ----
+ ***************
+ *** 133,140 ****
+   	__raw_writel(pre_margin, base + OMAP_WATCHDOG_LDR);
+   	while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
+   		cpu_relax();
+ - 
+ - 	pm_runtime_put_sync(wdev->dev);
+   }
+   
+   /*
+ --- 131,136 ----
+ ***************
+ *** 164,171 ****
+   	omap_wdt_ping(wdev); /* trigger loading of new timeout value */
+   	omap_wdt_enable(wdev);
+   
+ - 	pm_runtime_put_sync(wdev->dev);
+ - 
+   	return nonseekable_open(inode, file);
+   }
+   
+ --- 160,165 ----
+ ***************
+ *** 177,184 ****
+   	 *      Shut off the timer unless NOWAYOUT is defined.
+   	 */
+   #ifndef CONFIG_WATCHDOG_NOWAYOUT
+ - 	pm_runtime_get_sync(wdev->dev);
+ - 
+   	omap_wdt_disable(wdev);
+   
+   	pm_runtime_put_sync(wdev->dev);
+ --- 171,176 ----
+ ***************
+ *** 197,207 ****
+   
+   	/* Refresh LOAD_TIME. */
+   	if (len) {
+ - 		pm_runtime_get_sync(wdev->dev);
+   		spin_lock(&wdt_lock);
+   		omap_wdt_ping(wdev);
+   		spin_unlock(&wdt_lock);
+ - 		pm_runtime_put_sync(wdev->dev);
+   	}
+   	return len;
+   }
+ --- 189,197 ----
+ ***************
+ *** 233,250 ****
+   			return put_user(omap_prcm_get_reset_sources(),
+   					(int __user *)arg);
+   	case WDIOC_KEEPALIVE:
+ - 		pm_runtime_get_sync(wdev->dev);
+   		spin_lock(&wdt_lock);
+   		omap_wdt_ping(wdev);
+   		spin_unlock(&wdt_lock);
+ - 		pm_runtime_put_sync(wdev->dev);
+   		return 0;
+   	case WDIOC_SETTIMEOUT:
+   		if (get_user(new_margin, (int __user *)arg))
+   			return -EFAULT;
+   		omap_wdt_adjust_timeout(new_margin);
+   
+ - 		pm_runtime_get_sync(wdev->dev);
+   		spin_lock(&wdt_lock);
+   		omap_wdt_disable(wdev);
+   		omap_wdt_set_timeout(wdev);
+ --- 223,237 ----
+ ***************
+ *** 252,258 ****
+   
+   		omap_wdt_ping(wdev);
+   		spin_unlock(&wdt_lock);
+ - 		pm_runtime_put_sync(wdev->dev);
+   		/* Fall */
+   	case WDIOC_GETTIMEOUT:
+   		return put_user(timer_margin, (int __user *)arg);
+ --- 239,244 ----
+ ***************
+ *** 359,365 ****
+   	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
+   
+   	if (wdev->omap_wdt_users) {
+ - 		pm_runtime_get_sync(wdev->dev);
+   		omap_wdt_disable(wdev);
+   		pm_runtime_put_sync(wdev->dev);
+   	}
+ --- 345,350 ----
+ ***************
+ *** 398,404 ****
+   	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
+   
+   	if (wdev->omap_wdt_users) {
+ - 		pm_runtime_get_sync(wdev->dev);
+   		omap_wdt_disable(wdev);
+   		pm_runtime_put_sync(wdev->dev);
+   	}
+ --- 383,388 ----
+ ***************
+ *** 414,420 ****
+   		pm_runtime_get_sync(wdev->dev);
+   		omap_wdt_enable(wdev);
+   		omap_wdt_ping(wdev);
+ - 		pm_runtime_put_sync(wdev->dev);
+   	}
+   
+   	return 0;
+ --- 398,403 ----
+ diff -crN linux-3.2.1_o/include/linux/can/platform/d_can.h linux-3.2.1/include/linux/can/platform/d_can.h
+ *** linux-3.2.1_o/include/linux/can/platform/d_can.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/include/linux/can/platform/d_can.h	2014-11-25 13:19:17.031078257 +0900
+ ***************
+ *** 0 ****
+ --- 1,40 ----
+ + /*
+ +  * D_CAN controller driver platform header
+ +  *
+ +  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ +  *
+ +  * Bosch D_CAN controller is compliant to CAN protocol version 2.0 part A and B.
+ +  * Bosch D_CAN user manual can be obtained from:
+ +  * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/can/
+ +  * d_can_users_manual_111.pdf
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #ifndef __CAN_PLATFORM_TI_D_CAN_H__
+ + #define __CAN_PLATFORM_TI_D_CAN_H__
+ + 
+ + /**
+ +  * struct d_can_platform_data - DCAN Platform Data
+ +  *
+ +  * @num_of_msg_objs:	Number of message objects
+ +  * @dma_support:	DMA support is required/not
+ +  * @ram_init:		DCAN RAM initialization
+ +  *
+ +  * Platform data structure to get all platform specific settings.
+ +  * this structure also accounts the fact that the IP may have different
+ +  * RAM and mailbox offsets for different SOC's
+ +  */
+ + struct d_can_platform_data {
+ + 	u32 num_of_msg_objs;
+ + 	bool dma_support;
+ + 	void (*ram_init) (unsigned int, unsigned int);
+ + };
+ + #endif
+ diff -crN linux-3.2.1_o/include/linux/cpsw.h linux-3.2.1/include/linux/cpsw.h
+ *** linux-3.2.1_o/include/linux/cpsw.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/include/linux/cpsw.h	2014-11-25 13:19:17.031078257 +0900
+ ***************
+ *** 0 ****
+ --- 1,63 ----
+ + #ifndef __CPSW_H__
+ + #define __CPSW_H__
+ + 
+ + #include <linux/if_ether.h>
+ + 
+ + enum {
+ + 	CPSW_VERSION_1 = 0,    /* TI8148 */
+ + 	CPSW_VERSION_2,        /* AM33XX */
+ + };
+ + 
+ + struct cpsw_slave_data {
+ + 	u32		slave_reg_ofs;
+ + 	u32		sliver_reg_ofs;
+ + 	const char	*phy_id;
+ + 	int		phy_if;
+ + 	u8		mac_addr[ETH_ALEN];
+ + 	u32		dual_emac_reserved_vlan;
+ + };
+ + 
+ + struct cpsw_platform_data {
+ + 	u32	ss_reg_ofs;	/* Subsystem control register offset */
+ + 	int	channels;	/* number of cpdma channels (symmetric) */
+ + 	u32	cpdma_reg_ofs;	/* cpdma register offset */
+ + 
+ + 	int	slaves;		/* number of slave cpgmac ports */
+ + 	struct cpsw_slave_data	*slave_data;
+ + 	int	ethtool_slave;	/* Holds which slave attaches to ethtool */
+ + 
+ + 	u32	ale_reg_ofs;	/* address lookup engine reg offset */
+ + 	int	ale_entries;	/* ale table size */
+ + 
+ + 	u32	host_port_reg_ofs; /* cpsw cpdma host port registers */
+ + 
+ + 	u32	hw_stats_reg_ofs;  /* cpsw hardware statistics counters */
+ + 
+ + 	u32	bd_ram_ofs;   /* embedded buffer descriptor RAM offset*/
+ + 	u32	bd_ram_size;  /*buffer descriptor ram size */
+ + 	u32	hw_ram_addr; /*if the HW address for BD RAM is different */
+ + 
+ + 	u32	cpts_reg_ofs;		/* cpts registers */
+ + 	u32	cpts_active_slave;	/* time stamping slave */
+ + 	u32	cpts_clock_mult; /* convert input clock ticks to nanoseconds */
+ + 	u32	cpts_clock_shift; /* convert input clock ticks to nanoseconds */
+ + 
+ + 	u8	mac_addr[ETH_ALEN];
+ + 
+ + 	int	rx_descs;
+ + 
+ + 	void	(*phy_control)(bool enabled);
+ + 
+ + 	u32	mac_control;
+ + 
+ + 	u32	gigabit_en; /* Is gigabit capable AND enabled */
+ + 	u32	rmii_en; /* Is RMII mode capable AND enabled */
+ + 	u32	host_port_num; /* The port number for the host port */
+ + 
+ + 	bool	no_bd_ram; /* no embedded BD ram*/
+ + 	u8	version;
+ + 	u32	default_vlan; /* Default VLAN for Untagged packet handling*/
+ + 	void (*save_mac_addr) (char *);		/* function for saving MAC address */
+ + };
+ + 
+ + #endif /* __CPSW_H__ */
+ diff -crN linux-3.2.1_o/include/linux/i2c/at24.h linux-3.2.1/include/linux/i2c/at24.h
+ *** linux-3.2.1_o/include/linux/i2c/at24.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/include/linux/i2c/at24.h	2014-11-25 13:19:17.049081009 +0900
+ ***************
+ *** 27,32 ****
+ --- 27,35 ----
+   
+   	void		(*setup)(struct memory_accessor *, void *context);
+   	void		*context;
+ + #ifdef CONFIG_MACH_CKB_3352
+ + 	void		(*unload)(void);
+ + #endif
+   };
+   
+   #endif /* _LINUX_AT24_H */
+ diff -crN linux-3.2.1_o/include/linux/i2c-omap.h linux-3.2.1/include/linux/i2c-omap.h
+ *** linux-3.2.1_o/include/linux/i2c-omap.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/include/linux/i2c-omap.h	2014-11-25 13:19:17.057114762 +0900
+ ***************
+ *** 35,40 ****
+ --- 35,41 ----
+   	u32		rev;
+   	u32		flags;
+   	void		(*set_mpu_wkup_lat)(struct device *dev, long set);
+ + 	int		(*device_reset) (struct device *dev);
+   };
+   
+   #endif
+ diff -crN linux-3.2.1_o/include/linux/input/ti_tsc.h linux-3.2.1/include/linux/input/ti_tsc.h
+ *** linux-3.2.1_o/include/linux/input/ti_tsc.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/include/linux/input/ti_tsc.h	2014-11-25 13:19:17.061090797 +0900
+ ***************
+ *** 0 ****
+ --- 1,18 ----
+ + /**
+ +  * struct tsc_data	Touchscreen wire configuration
+ +  * @wires:		Wires refer to application modes
+ +  *			i.e. 4/5/8 wire touchscreen support
+ +  *			on the platform
+ +  * @x_plate_resistance:	X plate resistance.
+ +  * @steps_to_configure: The sequencer supports a total of
+ +  *			16 programmable steps.
+ +  *			A step configured to read a single
+ +  *			co-ordinate value, can be applied
+ +  *			more number of times for better results.
+ +  */
+ + 
+ + struct tsc_data {
+ + 	int wires;
+ + 	int x_plate_resistance;
+ + 	int steps_to_configure;
+ + };
+ diff -crN linux-3.2.1_o/include/linux/Kbuild linux-3.2.1/include/linux/Kbuild
+ *** linux-3.2.1_o/include/linux/Kbuild	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/include/linux/Kbuild	2014-11-25 13:19:17.151170482 +0900
+ ***************
+ *** 258,263 ****
+ --- 258,264 ----
+   header-y += net.h
+   header-y += net_dropmon.h
+   header-y += net_tstamp.h
+ + header-y += net_switch_config.h
+   header-y += netdevice.h
+   header-y += netfilter.h
+   header-y += netfilter_arp.h
+ diff -crN linux-3.2.1_o/include/linux/mfd/ti_tscadc.h linux-3.2.1/include/linux/mfd/ti_tscadc.h
+ *** linux-3.2.1_o/include/linux/mfd/ti_tscadc.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/include/linux/mfd/ti_tscadc.h	2014-11-25 13:19:17.157163937 +0900
+ ***************
+ *** 0 ****
+ --- 1,167 ----
+ + /*
+ +  * TI Touch Screen / ADC MFD driver
+ +  *
+ +  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #include <linux/mfd/core.h>
+ + 
+ + #define TSCADC_REG_RAWIRQSTATUS		0x024
+ + #define TSCADC_REG_IRQSTATUS		0x028
+ + #define TSCADC_REG_IRQENABLE		0x02C
+ + #define TSCADC_REG_IRQCLR		0x030
+ + #define TSCADC_REG_IRQWAKEUP		0x034
+ + #define TSCADC_REG_CTRL			0x040
+ + #define TSCADC_REG_ADCFSM		0x044
+ + #define TSCADC_REG_CLKDIV		0x04C
+ + #define TSCADC_REG_SE			0x054
+ + #define TSCADC_REG_IDLECONFIG		0x058
+ + #define TSCADC_REG_CHARGECONFIG		0x05C
+ + #define TSCADC_REG_CHARGEDELAY		0x060
+ + #define TSCADC_REG_STEPCONFIG(n)	(0x64 + ((n - 1) * 8))
+ + #define TSCADC_REG_STEPDELAY(n)		(0x68 + ((n - 1) * 8))
+ + #define TSCADC_REG_FIFO0CNT		0xE4
+ + #define TSCADC_REG_FIFO0THR		0xE8
+ + #define TSCADC_REG_FIFO1CNT		0xF0
+ + #define TSCADC_REG_FIFO1THR		0xF4
+ + #define TSCADC_REG_FIFO0		0x100
+ + #define TSCADC_REG_FIFO1		0x200
+ + 
+ + /*	Register Bitfields	*/
+ + /* IRQ wakeup enable */
+ + #define TSCADC_IRQWKUP_ENB		BIT(0)
+ + 
+ + /* Step Enable */
+ + #define TSCADC_STEPENB_MASK		(0x1FFFF << 0)
+ + #define TSCADC_STEPENB(val)		((val) << 0)
+ + #define TSCADC_STPENB_STEPENB		TSCADC_STEPENB(0x1FFFF)
+ + #define TSCADC_STPENB_STEPENB_TC	TSCADC_STEPENB(0x1FFF)
+ + #define TSCADC_ENB(val)			(1 << (val))
+ + 
+ + /* IRQ enable */
+ + #define TSCADC_IRQENB_HW_PEN		BIT(0)
+ + #define TSCADC_IRQENB_FIFO0THRES	BIT(2)
+ + #define TSCADC_IRQENB_FIFO0OVRRUN	BIT(3)
+ + #define TSCADC_IRQENB_FIFO0UNDRFLW	BIT(4)
+ + #define TSCADC_IRQENB_FIFO1THRES	BIT(5)
+ + #define TSCADC_IRQENB_FIFO1OVRRUN       BIT(6)
+ + #define TSCADC_IRQENB_FIFO1UNDRFLW      BIT(7)
+ + #define TSCADC_IRQENB_PENUP		BIT(9)
+ + 
+ + /* Step Configuration */
+ + #define TSCADC_STEPCONFIG_MODE_MASK	(3 << 0)
+ + #define TSCADC_STEPCONFIG_MODE(val)	((val) << 0)
+ + #define TSCADC_STEPCONFIG_MODE_HWSYNC	TSCADC_STEPCONFIG_MODE(2)
+ + #define TSCADC_STEPCONFIG_MODE_SWCNT	TSCADC_STEPCONFIG_MODE(1)
+ + #define TSCADC_STEPCONFIG_AVG_MASK	(7 << 2)
+ + #define TSCADC_STEPCONFIG_AVG(val)	((val) << 2)
+ + #define TSCADC_STEPCONFIG_AVG_16	TSCADC_STEPCONFIG_AVG(4)
+ + #define TSCADC_STEPCONFIG_XPP		BIT(5)
+ + #define TSCADC_STEPCONFIG_XNN		BIT(6)
+ + #define TSCADC_STEPCONFIG_YPP		BIT(7)
+ + #define TSCADC_STEPCONFIG_YNN		BIT(8)
+ + #define TSCADC_STEPCONFIG_XNP		BIT(9)
+ + #define TSCADC_STEPCONFIG_YPN		BIT(10)
+ + #define TSCADC_STEPCONFIG_INM_MASK	(0xF << 15)
+ + #define TSCADC_STEPCONFIG_INM(val)	((val) << 15)
+ + #define TSCADC_STEPCONFIG_INM_ADCREFM	TSCADC_STEPCONFIG_INM(8)
+ + #define TSCADC_STEPCONFIG_INP_MASK	(0xF << 19)
+ + #define TSCADC_STEPCONFIG_INP(val)	((val) << 19)
+ + #define TSCADC_STEPCONFIG_INP_AN2	TSCADC_STEPCONFIG_INP(2)
+ + #define TSCADC_STEPCONFIG_INP_AN3	TSCADC_STEPCONFIG_INP(3)
+ + #define TSCADC_STEPCONFIG_INP_AN4	TSCADC_STEPCONFIG_INP(4)
+ + #define TSCADC_STEPCONFIG_INP_ADCREFM	TSCADC_STEPCONFIG_INP(8)
+ + #define TSCADC_STEPCONFIG_FIFO1		BIT(26)
+ + 
+ + /* Delay register */
+ + #define TSCADC_STEPDELAY_OPEN_MASK	(0x3FFFF << 0)
+ + #define TSCADC_STEPDELAY_OPEN(val)	((val) << 0)
+ + #define TSCADC_STEPCONFIG_OPENDLY	TSCADC_STEPDELAY_OPEN(0x098)
+ + #define TSCADC_STEPDELAY_SAMPLE_MASK	(0xFF << 24)
+ + #define TSCADC_STEPDELAY_SAMPLE(val)	((val) << 24)
+ + #define TSCADC_STEPCONFIG_SAMPLEDLY	TSCADC_STEPDELAY_SAMPLE(0)
+ + 
+ + /* Charge Config */
+ + #define TSCADC_STEPCHARGE_RFP_MASK	(7 << 12)
+ + #define TSCADC_STEPCHARGE_RFP(val)	((val) << 12)
+ + #define TSCADC_STEPCHARGE_RFP_XPUL	TSCADC_STEPCHARGE_RFP(1)
+ + #define TSCADC_STEPCHARGE_INM_MASK	(0xF << 15)
+ + #define TSCADC_STEPCHARGE_INM(val)	((val) << 15)
+ + #define TSCADC_STEPCHARGE_INM_AN1	TSCADC_STEPCHARGE_INM(1)
+ + #define TSCADC_STEPCHARGE_INP_MASK	(0xF << 19)
+ + #define TSCADC_STEPCHARGE_INP(val)	((val) << 19)
+ + #define TSCADC_STEPCHARGE_INP_AN1	TSCADC_STEPCHARGE_INP(1)
+ + #define TSCADC_STEPCHARGE_RFM_MASK	(3 << 23)
+ + #define TSCADC_STEPCHARGE_RFM(val)	((val) << 23)
+ + #define TSCADC_STEPCHARGE_RFM_XNUR	TSCADC_STEPCHARGE_RFM(1)
+ + 
+ + /* Charge delay */
+ + #define TSCADC_CHARGEDLY_OPEN_MASK	(0x3FFFF << 0)
+ + #define TSCADC_CHARGEDLY_OPEN(val)	((val) << 0)
+ + #define TSCADC_CHARGEDLY_OPENDLY	TSCADC_CHARGEDLY_OPEN(1)
+ + 
+ + /* Control register */
+ + #define TSCADC_CNTRLREG_TSCSSENB	BIT(0)
+ + #define TSCADC_CNTRLREG_STEPID		BIT(1)
+ + #define TSCADC_CNTRLREG_STEPCONFIGWRT	BIT(2)
+ + #define TSCADC_CNTRLREG_POWERDOWN	BIT(4)
+ + #define TSCADC_CNTRLREG_AFE_CTRL_MASK	(3 << 5)
+ + #define TSCADC_CNTRLREG_AFE_CTRL(val)	((val) << 5)
+ + #define TSCADC_CNTRLREG_4WIRE		TSCADC_CNTRLREG_AFE_CTRL(1)
+ + #define TSCADC_CNTRLREG_5WIRE		TSCADC_CNTRLREG_AFE_CTRL(2)
+ + #define TSCADC_CNTRLREG_8WIRE		TSCADC_CNTRLREG_AFE_CTRL(3)
+ + #define TSCADC_CNTRLREG_TSCENB		BIT(7)
+ + 
+ + /* FIFO READ Register */
+ + #define TSCADC_FIFOREAD_DATA_MASK	(0xfff << 0)
+ + #define TSCADC_FIFOREAD_CHNLID_MASK	(0xf << 16)
+ + 
+ + /* Sequencer Status */
+ + #define TSCADC_SEQ_STATUS		BIT(5)
+ + 
+ + #define ADC_CLK				3000000
+ + #define TOTAL_STEPS			16
+ + #define TOTAL_CHANNELS			8
+ + #define FIFO1_THRESHOLD			19
+ + 
+ + /*
+ +  * ADC runs at 3MHz, and it takes
+ +  * 15 cycles to latch one data output.
+ +  * Hence the idle time for ADC to
+ +  * process one sample data would be
+ +  * around 5 micro seconds.
+ +  */
+ + #define IDLE_TIMEOUT			5 /* microsec */
+ + 
+ + #define TSCADC_CELLS			2
+ + 
+ + struct mfd_tscadc_board {
+ + 	struct tsc_data *tsc_init;
+ + 	struct adc_data *adc_init;
+ + };
+ + 
+ + struct ti_tscadc_dev {
+ + 	struct device *dev;
+ + 	void __iomem *tscadc_base;
+ + 	int irq;
+ + 	struct mfd_cell cells[TSCADC_CELLS];
+ + 
+ + 	/* tsc device */
+ + 	struct tscadc *tsc;
+ + 
+ + 	/* adc device */
+ + 	struct adc_device *adc;
+ + 
+ + 	/* Context save */
+ + 	unsigned int irqstat;
+ + 	unsigned int ctrl;
+ + };
+ diff -crN linux-3.2.1_o/include/linux/mfd/tps65217.h linux-3.2.1/include/linux/mfd/tps65217.h
+ *** linux-3.2.1_o/include/linux/mfd/tps65217.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/include/linux/mfd/tps65217.h	2014-11-25 13:19:17.157163937 +0900
+ ***************
+ *** 0 ****
+ --- 1,291 ----
+ + /*
+ +  * linux/mfd/tps65217.h
+ +  *
+ +  * Functions to access TPS65217 power management chip.
+ +  *
+ +  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #ifndef __LINUX_MFD_TPS65217_H
+ + #define __LINUX_MFD_TPS65217_H
+ + 
+ + #include <linux/i2c.h>
+ + #include <linux/regulator/driver.h>
+ + #include <linux/regulator/machine.h>
+ + 
+ + /* I2C ID for TPS65217 part */
+ + #define TPS65217_I2C_ID			0x24
+ + 
+ + /* All register addresses */
+ + #define TPS65217_REG_CHIPID		0X00
+ + #define TPS65217_REG_PPATH		0X01
+ + #define TPS65217_REG_INT		0X02
+ + #define TPS65217_REG_CHGCONFIG0		0X03
+ + #define TPS65217_REG_CHGCONFIG1		0X04
+ + #define TPS65217_REG_CHGCONFIG2		0X05
+ + #define TPS65217_REG_CHGCONFIG3		0X06
+ + #define TPS65217_REG_WLEDCTRL1		0X07
+ + #define TPS65217_REG_WLEDCTRL2		0X08
+ + #define TPS65217_REG_MUXCTRL		0X09
+ + #define TPS65217_REG_STATUS		0X0A
+ + #define TPS65217_REG_PASSWORD		0X0B
+ + #define TPS65217_REG_PGOOD		0X0C
+ + #define TPS65217_REG_DEFPG		0X0D
+ + #define TPS65217_REG_DEFDCDC1		0X0E
+ + #define TPS65217_REG_DEFDCDC2		0X0F
+ + #define TPS65217_REG_DEFDCDC3		0X10
+ + #define TPS65217_REG_DEFSLEW		0X11
+ + #define TPS65217_REG_DEFLDO1		0X12
+ + #define TPS65217_REG_DEFLDO2		0X13
+ + #define TPS65217_REG_DEFLS1		0X14
+ + #define TPS65217_REG_DEFLS2		0X15
+ + #define TPS65217_REG_ENABLE		0X16
+ + #define TPS65217_REG_DEFUVLO		0X18
+ + #define TPS65217_REG_SEQ1		0X19
+ + #define TPS65217_REG_SEQ2		0X1A
+ + #define TPS65217_REG_SEQ3		0X1B
+ + #define TPS65217_REG_SEQ4		0X1C
+ + #define TPS65217_REG_SEQ5		0X1D
+ + #define TPS65217_REG_SEQ6		0X1E
+ + 
+ + /* Register field definitions */
+ + #define TPS65217_CHIPID_CHIP_MASK	0xF0
+ + #define TPS65217_CHIPID_REV_MASK	0x0F
+ + 
+ + #define TPS65217_PPATH_ACSINK_ENABLE	BIT(7)
+ + #define TPS65217_PPATH_USBSINK_ENABLE	BIT(6)
+ + #define TPS65217_PPATH_AC_PW_ENABLE	BIT(5)
+ + #define TPS65217_PPATH_USB_PW_ENABLE	BIT(4)
+ + #define TPS65217_PPATH_AC_CURRENT_MASK	0x0C
+ + #define TPS65217_PPATH_USB_CURRENT_MASK	0x03
+ + 
+ + #define TPS65217_INT_PBM		BIT(6)
+ + #define TPS65217_INT_ACM		BIT(5)
+ + #define TPS65217_INT_USBM		BIT(4)
+ + #define TPS65217_INT_PBI		BIT(2)
+ + #define TPS65217_INT_ACI		BIT(1)
+ + #define TPS65217_INT_USBI		BIT(0)
+ + 
+ + #define TPS65217_CHGCONFIG0_TREG	BIT(7)
+ + #define TPS65217_CHGCONFIG0_DPPM	BIT(6)
+ + #define TPS65217_CHGCONFIG0_TSUSP	BIT(5)
+ + #define TPS65217_CHGCONFIG0_TERMI	BIT(4)
+ + #define TPS65217_CHGCONFIG0_ACTIVE	BIT(3)
+ + #define TPS65217_CHGCONFIG0_CHGTOUT	BIT(2)
+ + #define TPS65217_CHGCONFIG0_PCHGTOUT	BIT(1)
+ + #define TPS65217_CHGCONFIG0_BATTEMP	BIT(0)
+ + 
+ + #define TPS65217_CHGCONFIG1_TMR_MASK	0xC0
+ + #define TPS65217_CHGCONFIG1_TMR_ENABLE	BIT(5)
+ + #define TPS65217_CHGCONFIG1_NTC_TYPE	BIT(4)
+ + #define TPS65217_CHGCONFIG1_RESET	BIT(3)
+ + #define TPS65217_CHGCONFIG1_TERM	BIT(2)
+ + #define TPS65217_CHGCONFIG1_SUSP	BIT(1)
+ + #define TPS65217_CHGCONFIG1_CHG_EN	BIT(0)
+ + 
+ + #define TPS65217_CHGCONFIG2_DYNTMR	BIT(7)
+ + #define TPS65217_CHGCONFIG2_VPREGHG	BIT(6)
+ + #define TPS65217_CHGCONFIG2_VOREG_MASK	0x30
+ + 
+ + #define TPS65217_CHGCONFIG3_ICHRG_MASK	0xC0
+ + #define TPS65217_CHGCONFIG3_DPPMTH_MASK	0x30
+ + #define TPS65217_CHGCONFIG2_PCHRGT	BIT(3)
+ + #define TPS65217_CHGCONFIG2_TERMIF	0x06
+ + #define TPS65217_CHGCONFIG2_TRANGE	BIT(0)
+ + 
+ + #define TPS65217_WLEDCTRL1_ISINK_ENABLE	BIT(3)
+ + #define TPS65217_WLEDCTRL1_ISEL		BIT(2)
+ + #define TPS65217_WLEDCTRL1_FDIM_MASK	0x03
+ + 
+ + #define TPS65217_WLEDCTRL2_DUTY_MASK	0x7F
+ + 
+ + #define TPS65217_MUXCTRL_MUX_MASK	0x07
+ + 
+ + #define TPS65217_STATUS_OFF		BIT(7)
+ + #define TPS65217_STATUS_ACPWR		BIT(3)
+ + #define TPS65217_STATUS_USBPWR		BIT(2)
+ + #define TPS65217_STATUS_PB		BIT(0)
+ + 
+ + #define TPS65217_PASSWORD_REGS_UNLOCK	0x7D
+ + 
+ + #define TPS65217_PGOOD_LDO3_PG		BIT(6)
+ + #define TPS65217_PGOOD_LDO4_PG		BIT(5)
+ + #define TPS65217_PGOOD_DC1_PG		BIT(4)
+ + #define TPS65217_PGOOD_DC2_PG		BIT(3)
+ + #define TPS65217_PGOOD_DC3_PG		BIT(2)
+ + #define TPS65217_PGOOD_LDO1_PG		BIT(1)
+ + #define TPS65217_PGOOD_LDO2_PG		BIT(0)
+ + 
+ + #define TPS65217_DEFPG_LDO1PGM		BIT(3)
+ + #define TPS65217_DEFPG_LDO2PGM		BIT(2)
+ + #define TPS65217_DEFPG_PGDLY_MASK	0x03
+ + 
+ + #define TPS65217_DEFDCDCX_XADJX		BIT(7)
+ + #define TPS65217_DEFDCDCX_DCDC_MASK	0x3F
+ + 
+ + #define TPS65217_DEFSLEW_GO		BIT(7)
+ + #define TPS65217_DEFSLEW_GODSBL		BIT(6)
+ + #define TPS65217_DEFSLEW_PFM_EN1	BIT(5)
+ + #define TPS65217_DEFSLEW_PFM_EN2	BIT(4)
+ + #define TPS65217_DEFSLEW_PFM_EN3	BIT(3)
+ + #define TPS65217_DEFSLEW_SLEW_MASK	0x07
+ + 
+ + #define TPS65217_DEFLDO1_LDO1_MASK	0x0F
+ + 
+ + #define TPS65217_DEFLDO2_TRACK		BIT(6)
+ + #define TPS65217_DEFLDO2_LDO2_MASK	0x3F
+ + 
+ + #define TPS65217_DEFLDO3_LDO3_EN	BIT(5)
+ + #define TPS65217_DEFLDO3_LDO3_MASK	0x1F
+ + 
+ + #define TPS65217_DEFLDO4_LDO4_EN	BIT(5)
+ + #define TPS65217_DEFLDO4_LDO4_MASK	0x1F
+ + 
+ + #define TPS65217_ENABLE_LS1_EN		BIT(6)
+ + #define TPS65217_ENABLE_LS2_EN		BIT(5)
+ + #define TPS65217_ENABLE_DC1_EN		BIT(4)
+ + #define TPS65217_ENABLE_DC2_EN		BIT(3)
+ + #define TPS65217_ENABLE_DC3_EN		BIT(2)
+ + #define TPS65217_ENABLE_LDO1_EN		BIT(1)
+ + #define TPS65217_ENABLE_LDO2_EN		BIT(0)
+ + 
+ + #define TPS65217_DEFUVLO_UVLOHYS	BIT(2)
+ + #define TPS65217_DEFUVLO_UVLO_MASK	0x03
+ + 
+ + #define TPS65217_SEQ1_DC1_SEQ_MASK	0xF0
+ + #define TPS65217_SEQ1_DC2_SEQ_MASK	0x0F
+ + 
+ + #define TPS65217_SEQ2_DC3_SEQ_MASK	0xF0
+ + #define TPS65217_SEQ2_LDO1_SEQ_MASK	0x0F
+ + 
+ + #define TPS65217_SEQ3_LDO2_SEQ_MASK	0xF0
+ + #define TPS65217_SEQ3_LDO3_SEQ_MASK	0x0F
+ + 
+ + #define TPS65217_SEQ4_LDO4_SEQ_MASK	0xF0
+ + 
+ + #define TPS65217_SEQ5_DLY1_MASK		0xC0
+ + #define TPS65217_SEQ5_DLY2_MASK		0x30
+ + #define TPS65217_SEQ5_DLY3_MASK		0x0C
+ + #define TPS65217_SEQ5_DLY4_MASK		0x03
+ + 
+ + #define TPS65217_SEQ6_DLY5_MASK		0xC0
+ + #define TPS65217_SEQ6_DLY6_MASK		0x30
+ + #define TPS65217_SEQ6_SEQUP		BIT(2)
+ + #define TPS65217_SEQ6_SEQDWN		BIT(1)
+ + #define TPS65217_SEQ6_INSTDWN		BIT(0)
+ + 
+ + #define TPS65217_MAX_REGISTER		0x1E
+ + #define TPS65217_PROTECT_NONE		0
+ + #define TPS65217_PROTECT_L1		1
+ + #define TPS65217_PROTECT_L2		2
+ + 
+ + 
+ + enum tps65217_regulator_id {
+ + 	/* DCDC's */
+ + 	TPS65217_DCDC_1,
+ + 	TPS65217_DCDC_2,
+ + 	TPS65217_DCDC_3,
+ + 	/* LDOs */
+ + 	TPS65217_LDO_1,
+ + 	TPS65217_LDO_2,
+ + 	TPS65217_LDO_3,
+ + 	TPS65217_LDO_4,
+ + };
+ + 
+ + #define TPS65217_MAX_REG_ID		TPS65217_LDO_4
+ + 
+ + /* Number of step-down converters available */
+ + #define TPS65217_NUM_DCDC		3
+ + /* Number of LDO voltage regulators available */
+ + #define TPS65217_NUM_LDO		4
+ + /* Number of total regulators available */
+ + #define TPS65217_NUM_REGULATOR		(TPS65217_NUM_DCDC + TPS65217_NUM_LDO)
+ + 
+ + /**
+ +  * struct tps65217_board - packages regulator init data
+ +  * @tps65217_regulator_data: regulator initialization values
+ +  * @status_off: Set the PMIC to shutdown on PWR_EN toggle
+ +  *
+ +  * Board data may be used to initialize regulator.
+ +  */
+ + struct tps65217_board {
+ + 	struct regulator_init_data *tps65217_init_data;
+ + 	bool status_off;
+ + };
+ + 
+ + struct tps65217_rdelay {
+ + 	int ramp_delay;
+ + };
+ + 
+ + /**
+ +  * struct tps_info - packages regulator constraints
+ +  * @name:		Voltage regulator name
+ +  * @min_uV:		minimum micro volts
+ +  * @max_uV:		minimum micro volts
+ +  * @vsel_to_uv:		Function pointer to get voltage from selector
+ +  * @uv_to_vsel:		Function pointer to get selector from voltage
+ +  * @delay:		Set voltage delay in us
+ +  * @table:		Table for non-uniform voltage step-size
+ +  * @table_len:		Length of the voltage table
+ +  * @enable_mask:	Regulator enable mask bits
+ +  * @set_vout_reg:	Regulator output voltage set register
+ +  * @set_vout_mask:	Regulator output voltage set mask
+ +  *
+ +  * This data is used to check the regualtor voltage limits while setting.
+ +  */
+ + struct tps_info {
+ + 	const char *name;
+ + 	int min_uV;
+ + 	int max_uV;
+ + 	int (*vsel_to_uv)(unsigned int vsel);
+ + 	int (*uv_to_vsel)(int uV, unsigned int *vsel);
+ + 	int delay;
+ + 	const int *table;
+ + 	unsigned int table_len;
+ + 	unsigned int enable_mask;
+ + 	unsigned int set_vout_reg;
+ + 	unsigned int set_vout_mask;
+ + };
+ + 
+ + /**
+ +  * struct tps65217 - tps65217 sub-driver chip access routines
+ +  *
+ +  * Device data may be used to access the TPS65217 chip
+ +  */
+ + 
+ + struct tps65217 {
+ + 	struct device *dev;
+ + 	struct tps65217_board *pdata;
+ + 	struct regulator_desc desc[TPS65217_NUM_REGULATOR];
+ + 	struct regulator_dev *rdev[TPS65217_NUM_REGULATOR];
+ + 	struct tps_info *info[TPS65217_NUM_REGULATOR];
+ + 	struct regmap *regmap;
+ + 
+ + 	/* Client devices */
+ + 	struct platform_device *regulator_pdev[TPS65217_NUM_REGULATOR];
+ + };
+ + 
+ + static inline struct tps65217 *dev_to_tps65217(struct device *dev)
+ + {
+ + 	return dev_get_drvdata(dev);
+ + }
+ + 
+ + int tps65217_reg_read(struct tps65217 *tps, unsigned int reg,
+ + 					unsigned int *val);
+ + int tps65217_reg_write(struct tps65217 *tps, unsigned int reg,
+ + 			unsigned int val, unsigned int level);
+ + int tps65217_set_bits(struct tps65217 *tps, unsigned int reg,
+ + 		unsigned int mask, unsigned int val, unsigned int level);
+ + int tps65217_clear_bits(struct tps65217 *tps, unsigned int reg,
+ + 		unsigned int mask, unsigned int level);
+ + 
+ + #endif /*  __LINUX_MFD_TPS65217_H */
+ diff -crN linux-3.2.1_o/include/linux/mfd/tps65910.h linux-3.2.1/include/linux/mfd/tps65910.h
+ *** linux-3.2.1_o/include/linux/mfd/tps65910.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/include/linux/mfd/tps65910.h	2014-11-25 13:19:17.173120940 +0900
+ ***************
+ *** 17,26 ****
+ --- 17,33 ----
+   #ifndef __LINUX_MFD_TPS65910_H
+   #define __LINUX_MFD_TPS65910_H
+   
+ + #include <linux/gpio.h>
+ + #include <linux/regulator/machine.h>
+ + 
+   /* TPS chip id list */
+   #define TPS65910			0
+   #define TPS65911			1
+   
+ + /* I2C Slave Address 7-bit */
+ + #define TPS65910_I2C_ID0 0x12 /* Smart Reflex */
+ + #define TPS65910_I2C_ID1 0x2D /* general-purpose control */
+ + 
+   /* TPS regulator type list */
+   #define REGULATOR_LDO			0
+   #define REGULATOR_DCDC			1
+ ***************
+ *** 740,745 ****
+ --- 747,780 ----
+   #define TPS65910_GPIO_STS				BIT(1)
+   #define TPS65910_GPIO_SET				BIT(0)
+   
+ + /* Regulator Index Definitions */
+ + #define TPS65910_REG_VRTC				0
+ + #define TPS65910_REG_VIO				1
+ + #define TPS65910_REG_VDD1				2
+ + #define TPS65910_REG_VDD2				3
+ + #define TPS65910_REG_VDD3				4
+ + #define TPS65910_REG_VDIG1				5
+ + #define TPS65910_REG_VDIG2				6
+ + #define TPS65910_REG_VPLL				7
+ + #define TPS65910_REG_VDAC				8
+ + #define TPS65910_REG_VAUX1				9
+ + #define TPS65910_REG_VAUX2				10
+ + #define TPS65910_REG_VAUX33				11
+ + #define TPS65910_REG_VMMC				12
+ + 
+ + #define TPS65911_REG_VDDCTRL				4
+ + #define TPS65911_REG_LDO1				5
+ + #define TPS65911_REG_LDO2				6
+ + #define TPS65911_REG_LDO3				7
+ + #define TPS65911_REG_LDO4				8
+ + #define TPS65911_REG_LDO5				9
+ + #define TPS65911_REG_LDO6				10
+ + #define TPS65911_REG_LDO7				11
+ + #define TPS65911_REG_LDO8				12
+ + 
+ + /* Max number of TPS65910/11 regulators */
+ + #define TPS65910_NUM_REGS				13
+ + 
+   /**
+    * struct tps65910_board
+    * Board platform data may be used to initialize regulators.
+ ***************
+ *** 751,757 ****
+   	int irq_base;
+   	int vmbch_threshold;
+   	int vmbch2_threshold;
+ ! 	struct regulator_init_data *tps65910_pmic_init_data;
+   };
+   
+   /**
+ --- 786,792 ----
+   	int irq_base;
+   	int vmbch_threshold;
+   	int vmbch2_threshold;
+ ! 	struct regulator_init_data *tps65910_pmic_init_data[TPS65910_NUM_REGS];
+   };
+   
+   /**
+ diff -crN linux-3.2.1_o/include/linux/mmc/card.h linux-3.2.1/include/linux/mmc/card.h
+ *** linux-3.2.1_o/include/linux/mmc/card.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/include/linux/mmc/card.h	2014-11-25 13:19:17.180513161 +0900
+ ***************
+ *** 206,211 ****
+ --- 206,212 ----
+   #define MMC_STATE_HIGHSPEED_DDR (1<<4)		/* card is in high speed mode */
+   #define MMC_STATE_ULTRAHIGHSPEED (1<<5)		/* card is in ultra high speed mode */
+   #define MMC_CARD_SDXC		(1<<6)		/* card is SDXC */
+ + #define MMC_CARD_REMOVED	(1<<7)		/* card has been removed */
+   	unsigned int		quirks; 	/* card quirks */
+   #define MMC_QUIRK_LENIENT_FN0	(1<<0)		/* allow SDIO FN0 writes outside of the VS CCCR range */
+   #define MMC_QUIRK_BLKSZ_FOR_BYTE_MODE (1<<1)	/* use func->cur_blksize */
+ ***************
+ *** 366,371 ****
+ --- 367,373 ----
+   #define mmc_card_ddr_mode(c)	((c)->state & MMC_STATE_HIGHSPEED_DDR)
+   #define mmc_sd_card_uhs(c) ((c)->state & MMC_STATE_ULTRAHIGHSPEED)
+   #define mmc_card_ext_capacity(c) ((c)->state & MMC_CARD_SDXC)
+ + #define mmc_card_removed(c)	((c) && ((c)->state & MMC_CARD_REMOVED))
+   
+   #define mmc_card_set_present(c)	((c)->state |= MMC_STATE_PRESENT)
+   #define mmc_card_set_readonly(c) ((c)->state |= MMC_STATE_READONLY)
+ ***************
+ *** 374,379 ****
+ --- 376,382 ----
+   #define mmc_card_set_ddr_mode(c) ((c)->state |= MMC_STATE_HIGHSPEED_DDR)
+   #define mmc_sd_card_set_uhs(c) ((c)->state |= MMC_STATE_ULTRAHIGHSPEED)
+   #define mmc_card_set_ext_capacity(c) ((c)->state |= MMC_CARD_SDXC)
+ + #define mmc_card_set_removed(c) ((c)->state |= MMC_CARD_REMOVED)
+   
+   /*
+    * Quirk add/remove for MMC products.
+ ***************
+ *** 455,461 ****
+   	struct device_driver drv;
+   	int (*probe)(struct mmc_card *);
+   	void (*remove)(struct mmc_card *);
+ ! 	int (*suspend)(struct mmc_card *, pm_message_t);
+   	int (*resume)(struct mmc_card *);
+   };
+   
+ --- 458,464 ----
+   	struct device_driver drv;
+   	int (*probe)(struct mmc_card *);
+   	void (*remove)(struct mmc_card *);
+ ! 	int (*suspend)(struct mmc_card *);
+   	int (*resume)(struct mmc_card *);
+   };
+   
+ diff -crN linux-3.2.1_o/include/linux/mmc/core.h linux-3.2.1/include/linux/mmc/core.h
+ *** linux-3.2.1_o/include/linux/mmc/core.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/include/linux/mmc/core.h	2014-11-25 13:19:17.183136314 +0900
+ ***************
+ *** 180,185 ****
+ --- 180,187 ----
+   
+   extern int mmc_flush_cache(struct mmc_card *);
+   
+ + extern int mmc_detect_card_removed(struct mmc_host *host);
+ + 
+   /**
+    *	mmc_claim_host - exclusively claim a host
+    *	@host: mmc host to claim
+ diff -crN linux-3.2.1_o/include/linux/mmc/host.h linux-3.2.1/include/linux/mmc/host.h
+ *** linux-3.2.1_o/include/linux/mmc/host.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/include/linux/mmc/host.h	2014-11-25 13:19:17.191368416 +0900
+ ***************
+ *** 213,218 ****
+ --- 213,219 ----
+   #define MMC_CAP_WAIT_WHILE_BUSY	(1 << 9)	/* Waits while card is busy */
+   #define MMC_CAP_ERASE		(1 << 10)	/* Allow erase/trim commands */
+   #define MMC_CAP_1_8V_DDR	(1 << 11)	/* can support */
+ + #define MMC_CAP2_DETECT_ON_ERR (1 << 8)        /* On I/O err check card removal */
+   						/* DDR mode at 1.8V */
+   #define MMC_CAP_1_2V_DDR	(1 << 12)	/* can support */
+   						/* DDR mode at 1.2V */
+ ***************
+ *** 297,302 ****
+ --- 298,304 ----
+   	int			claim_cnt;	/* "claim" nesting count */
+   
+   	struct delayed_work	detect;
+ + 	int			detect_change;	/* card detect flag */
+   
+   	const struct mmc_bus_ops *bus_ops;	/* current bus driver */
+   	unsigned int		bus_refs;	/* reference counter */
+ diff -crN linux-3.2.1_o/include/linux/net_switch_config.h linux-3.2.1/include/linux/net_switch_config.h
+ *** linux-3.2.1_o/include/linux/net_switch_config.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/include/linux/net_switch_config.h	2014-11-25 13:19:17.200690408 +0900
+ ***************
+ *** 0 ****
+ --- 1,120 ----
+ + /*
+ +  * Texas Instruments Ethernet Switch Driver
+ +  *
+ +  * Copyright (C) 2012 Texas Instruments
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + /*
+ +  * Userspace API for Switch Configuration
+ +  */
+ + 
+ + #ifndef __NET_CONFIG_SWITCH_H__
+ + #define __NET_CONFIG_SWITCH_H__
+ + 
+ + enum {
+ + 	CONFIG_SWITCH_INVALID,
+ + 	CONFIG_SWITCH_ADD_MULTICAST,
+ + 	CONFIG_SWITCH_ADD_UNICAST,
+ + 	CONFIG_SWITCH_ADD_OUI,
+ + 	CONFIG_SWITCH_FIND_ADDR,
+ + 	CONFIG_SWITCH_DEL_MULTICAST,
+ + 	CONFIG_SWITCH_DEL_UNICAST,
+ + 	CONFIG_SWITCH_ADD_VLAN,
+ + 	CONFIG_SWITCH_FIND_VLAN,
+ + 	CONFIG_SWITCH_DEL_VLAN,
+ + 	CONFIG_SWITCH_SET_PORT_VLAN_CONFIG,
+ + 	CONFIG_SWITCH_TIMEOUT,
+ + 	CONFIG_SWITCH_DUMP,
+ + 	CONFIG_SWITCH_SET_FLOW_CONTROL,
+ + 	CONFIG_SWITCH_SET_PRIORITY_MAPPING,
+ + 	CONFIG_SWITCH_PORT_STATISTICS_ENABLE,
+ + 	CONFIG_SWITCH_CONFIG_DUMP,
+ + 	CONFIG_SWITCH_RATELIMIT,
+ + 	CONFIG_SWITCH_VID_INGRESS_CHECK,
+ + 	CONFIG_SWITCH_ADD_UNKNOWN_VLAN_INFO,
+ + 	CONFIG_SWITCH_802_1,
+ + 	CONFIG_SWITCH_MACAUTH,
+ + 	CONFIG_SWITCH_SET_PORT_CONFIG,
+ + 	CONFIG_SWITCH_GET_PORT_CONFIG,
+ + 	CONFIG_SWITCH_PORT_STATE,
+ + 	CONFIG_SWITCH_RESET,
+ + };
+ + 
+ + enum {
+ + 	ADDR_TYPE_BROADCAST = 1,
+ + 	ADDR_TYPE_MULTICAST,
+ + 	ADDR_TYPE_UNICAST,
+ + };
+ + 
+ + enum {
+ + 	PORT_STATE_DISABLED = 0,
+ + 	PORT_STATE_BLOCKED,
+ + 	PORT_STATE_LEARN,
+ + 	PORT_STATE_FORWARD,
+ + };
+ + 
+ + struct net_switch_cmd {
+ + 	unsigned int	port;
+ + 	unsigned int	vid;		/* VLAN identifier */
+ + 	unsigned int	prio_port;	/* port priority 0 -7 */
+ + 	unsigned int	CFI_port;	/* port CFI  0 /1 */
+ + 	unsigned int	mem_port;	/* port number 0 - 2 */
+ + 	unsigned char	unreg_multi;	/* unreg multicast Egress Ports */
+ + 	unsigned char	reg_multi;	/* register multicast Egress ports */
+ + 	unsigned char	untag_port;	/* Untag ports */
+ + 	unsigned char	addr[6];
+ + 	unsigned int	flag;
+ + 	unsigned int	blocked;
+ + 	unsigned int	secure;
+ + 	unsigned int	ageable;
+ + 	unsigned int	ale_timeout;
+ + 	unsigned char	aledump;	/* if 1 print ale table */
+ + };
+ + 
+ + struct net_switch_port_cmd {
+ + 	unsigned int	port;		/* Port number */
+ + 	unsigned int	direction;	/* Tx -1 / Rx - 0 */
+ + 	unsigned int	addr_type;	/* Address type BroadMulti/Uni cast */
+ + 	unsigned int	limit;		/* multicast/broadcast limit */
+ + 	unsigned int	vlan_ingress_check;
+ + 	unsigned int	port_state;
+ + 	unsigned int	vlan_port_mask;
+ + 	unsigned char	drop_untagged;
+ + 	unsigned char	enable;		/* 1-enable/0-Disable */
+ + 	unsigned int	reg_multi_port_mask;
+ + 	unsigned int	unknown_reg_multi_port_mask;
+ + 	unsigned char	unknown_vlan_member;
+ + };
+ + 
+ + struct net_switch_prio_cmd {
+ + 	unsigned char port;
+ + 	unsigned char prio_rx;
+ + 	unsigned char prio_tx;
+ + 	unsigned char prio_switch;
+ + 	unsigned char hostRxCh;		/* packet with switch priority receive
+ + 						on this channel */
+ + 	unsigned char hostRxChSuper;	/* supervisory packet receive on
+ + 						this channel */
+ + };
+ + 
+ + struct net_switch_config {
+ + 	unsigned int cmd;	/* API to be invoked by the kernel driver */
+ + 	union {
+ + 		struct net_switch_cmd switchcmd;
+ + 		struct net_switch_port_cmd portcmd;
+ + 		struct net_switch_prio_cmd priocmd;
+ + 		char buf[4096];		/* Buffer for Ale Dump */
+ + 	} cmd_data;
+ + 	unsigned int ret_type;   /* Return  Success/Failure */
+ + };
+ + 
+ + #endif /* __NET_CONFIG_SWITCH_H__*/
+ diff -crN linux-3.2.1_o/include/linux/phy.h linux-3.2.1/include/linux/phy.h
+ *** linux-3.2.1_o/include/linux/phy.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/include/linux/phy.h	2014-11-25 13:19:17.215283949 +0900
+ ***************
+ *** 496,501 ****
+ --- 496,502 ----
+   	return phydev->drv->read_status(phydev);
+   }
+   
+ + int genphy_config_init(struct phy_device *phydev);
+   int genphy_restart_aneg(struct phy_device *phydev);
+   int genphy_config_aneg(struct phy_device *phydev);
+   int genphy_update_link(struct phy_device *phydev);
+ diff -crN linux-3.2.1_o/include/linux/platform_data/ti_adc.h linux-3.2.1/include/linux/platform_data/ti_adc.h
+ *** linux-3.2.1_o/include/linux/platform_data/ti_adc.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/include/linux/platform_data/ti_adc.h	2014-11-25 13:19:17.224624167 +0900
+ ***************
+ *** 0 ****
+ --- 1,9 ----
+ + /**
+ +  * struct adc_data	ADC Input information
+ +  * @adc_channels:	Number of analog inputs
+ +  *			available for ADC.
+ +  */
+ + 
+ + struct adc_data {
+ + 	int adc_channels;
+ + };
+ diff -crN linux-3.2.1_o/include/linux/pwm/ehrpwm.h linux-3.2.1/include/linux/pwm/ehrpwm.h
+ *** linux-3.2.1_o/include/linux/pwm/ehrpwm.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/include/linux/pwm/ehrpwm.h	2014-11-25 13:19:17.224624167 +0900
+ ***************
+ *** 0 ****
+ --- 1,188 ----
+ + #ifndef __EHRPWM_H__
+ + #define __EHRPWM_H__
+ + 
+ + #include <linux/pwm/pwm.h>
+ + 
+ + #define NCHAN 2
+ + 
+ + struct ehrpwm_pwm;
+ + 
+ + typedef int (*p_fcallback) (struct ehrpwm_pwm *, void *data);
+ + 
+ + struct et_int {
+ + 	void *data;
+ + 	p_fcallback pcallback;
+ + };
+ + 
+ + struct tz_int {
+ + 	void *data;
+ + 	p_fcallback pcallback;
+ + };
+ + 
+ + struct ehrpwm_context {
+ + 	u32 tbctl;
+ + 	u32 tbprd;
+ + 	u32 hrcfg;
+ + 	u32 aqctla;
+ + 	u32 aqctlb;
+ + 	u32 aqsfrc;
+ + 	u32 aqcsfrc;
+ + 	u32 cmpa;
+ + 	u32 cmpb;
+ + };
+ + 
+ + struct ehrpwm_pwm {
+ + 	struct pwm_device pwm[NCHAN];
+ + 	struct pwm_device_ops ops;
+ + 	spinlock_t      lock;
+ + 	struct clk      *clk;
+ + 	void __iomem    *mmio_base;
+ + 	unsigned short prescale_val;
+ + 	int irq[2];
+ + 	struct et_int st_etint;
+ + 	struct tz_int st_tzint;
+ + 	u8 version;
+ + 	void __iomem *config_mem_base;
+ + 	struct device *dev;
+ + 	struct ehrpwm_context ctx;
+ + };
+ + 
+ + enum tz_event {
+ + 	TZ_ONE_SHOT_EVENT = 0,
+ + 	TZ_CYCLE_BY_CYCLE,
+ + 	TZ_OSHT_CBC,
+ + 	TZ_DIS_EVT,
+ + };
+ + 
+ + enum config_mask {
+ + 	CONFIG_NS,
+ + 	CONFIG_TICKS,
+ + };
+ + 
+ + enum db_edge_delay {
+ + 	RISING_EDGE_DELAY,
+ + 	FALLING_EDGE_DELAY,
+ + };
+ + 
+ + struct aq_config_params {
+ + 	unsigned char ch;
+ + 	unsigned char ctreqzro;
+ + 	unsigned char ctreqprd;
+ + 	unsigned char ctreqcmpaup;
+ + 	unsigned char ctreqcmpadown;
+ + 	unsigned char ctreqcmpbup;
+ + 	unsigned char ctreqcmpbdown;
+ + };
+ + 
+ + int ehrpwm_tb_set_prescalar_val(struct pwm_device *p, unsigned char
+ + 	clkdiv, unsigned char hspclkdiv);
+ + 
+ + int ehrpwm_tb_config_sync(struct pwm_device *p, unsigned char phsen,
+ + 	unsigned char syncosel);
+ + 
+ + int ehrpwm_tb_set_counter_mode(struct pwm_device *p, unsigned char
+ + 	ctrmode, unsigned char phsdir);
+ + 
+ + int ehrpwm_tb_force_sync(struct pwm_device *p);
+ + 
+ + int ehrpwm_tb_set_periodload(struct pwm_device *p, unsigned char
+ + 	       loadmode);
+ + 
+ + int ehrpwm_tb_read_status(struct pwm_device *p, unsigned short *val);
+ + 
+ + int ehrpwm_tb_read_counter(struct pwm_device *p, unsigned short *val);
+ + 
+ + int ehrpwm_tb_set_period(struct pwm_device *p,	unsigned short val);
+ + 
+ + int ehrpwm_tb_set_phase(struct pwm_device *p, unsigned short val);
+ + 
+ + int ehrpwm_cmp_set_cmp_ctl(struct pwm_device *p, unsigned char
+ + 	       shdwamode, unsigned char shdwbmode, unsigned char loadamode,
+ + 	unsigned char loadbmode);
+ + 
+ + int ehrpwm_cmp_set_cmp_val(struct pwm_device *p, unsigned char reg,
+ + 	unsigned short val);
+ + 
+ + int ehrpwm_aq_set_act_ctrl(struct pwm_device *p,
+ + 	       struct aq_config_params *cfg);
+ + 
+ + int ehrpwm_aq_set_one_shot_act(struct pwm_device  *p, unsigned char ch,
+ + 	unsigned char act);
+ + 
+ + int ehrpwm_aq_ot_frc(struct pwm_device *p, unsigned char ch);
+ + 
+ + int ehrpwm_aq_set_csfrc_load_mode(struct pwm_device *p, unsigned char
+ + 	       loadmode);
+ + 
+ + int ehrpwm_aq_continuous_frc(struct pwm_device *p, unsigned char ch,
+ + 	unsigned char act);
+ + 
+ + int ehrpwm_db_get_max_delay(struct pwm_device *p,
+ + 	       enum config_mask cfgmask, unsigned long *delay_val);
+ + 
+ + int ehrpwm_db_get_delay(struct pwm_device *p, unsigned char edge,
+ + 	enum config_mask cfgmask, unsigned long *delay_val);
+ + 
+ + int ehrpwm_db_set_delay(struct pwm_device *p, unsigned char edge,
+ + 		enum config_mask cfgmask, unsigned long delay);
+ + 
+ + int ehrpwm_db_set_mode(struct pwm_device *p, unsigned char inmode,
+ + 		unsigned char polsel, unsigned char outmode);
+ + 
+ + int ehrpwm_pc_configure(struct pwm_device *p, unsigned char chpduty,
+ + 		unsigned char chpfreq, unsigned char oshtwidth);
+ + 
+ + int ehrpwm_pc_en_dis(struct pwm_device *p, unsigned char chpen);
+ + 
+ + int ehrpwm_tz_sel_event(struct pwm_device *p, unsigned char input,
+ + 	       enum tz_event evt);
+ + 
+ + int ehrpwm_tz_set_action(struct pwm_device *p, unsigned char ch,
+ + 	unsigned char act);
+ + 
+ + int ehrpwm_tz_set_int_en_dis(struct pwm_device *p, enum tz_event event,
+ + 		unsigned char int_en_dis);
+ + 
+ + int ehrpwm_tz_force_evt(struct pwm_device *p, enum tz_event event);
+ + 
+ + int ehrpwm_tz_read_status(struct pwm_device *p, unsigned short *status);
+ + 
+ + int ehrpwm_tz_clr_evt_status(struct pwm_device *p);
+ + 
+ + int ehrpwm_tz_clr_int_status(struct pwm_device *p);
+ + 
+ + int ehrpwm_et_set_sel_evt(struct pwm_device *p, unsigned char evt,
+ + 		unsigned char prd);
+ + 
+ + int ehrpwm_et_int_en_dis(struct pwm_device *p, unsigned char en_dis);
+ + 
+ + int ehrpwm_et_read_evt_cnt(struct pwm_device *p, unsigned long *evtcnt);
+ + 
+ + int pwm_et_read_int_status(struct pwm_device *p,
+ + 	unsigned long *status);
+ + 
+ + int ehrpwm_et_frc_int(struct pwm_device *p);
+ + 
+ + int ehrpwm_et_clr_int(struct pwm_device *p);
+ + 
+ + int ehrpwm_hr_set_phase(struct pwm_device *p, unsigned char val);
+ + 
+ + int ehrpwm_hr_set_cmpval(struct pwm_device *p, unsigned char val);
+ + 
+ + int ehrpwm_hr_config(struct pwm_device *p, unsigned char loadmode,
+ + 		unsigned char ctlmode, unsigned char edgemode);
+ + 
+ + int ehrpwm_et_cb_register(struct pwm_device *p, void *data,
+ + 	p_fcallback cb);
+ + 
+ + int ehrpwm_tz_cb_register(struct pwm_device *p, void *data,
+ + 	p_fcallback cb);
+ + 
+ + int ehrpwm_pwm_suspend(struct pwm_device *p, enum
+ + 	       config_mask config_mask,
+ + 	       unsigned long val);
+ + 
+ + #define ENABLE 1
+ + #define DISABLE 0
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/include/linux/pwm/pwm.h linux-3.2.1/include/linux/pwm/pwm.h
+ *** linux-3.2.1_o/include/linux/pwm/pwm.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/include/linux/pwm/pwm.h	2014-11-25 13:19:17.224624167 +0900
+ ***************
+ *** 0 ****
+ --- 1,195 ----
+ + /*
+ +  * Copyright (C) 2011 Bill Gatliff < bgat@billgatliff.com>
+ +  * Copyright (C) 2011 Arun Murthy <arun.murth@stericsson.com>
+ +  *
+ +  * This program is free software; you may redistribute and/or modify
+ +  * it under the terms of the GNU General Public License version 2, as
+ +  * published by the Free Software Foundation.
+ +  *
+ +  * This program is distributed in the hope that it will be useful, but
+ +  * WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ +  * General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+ +  * USA
+ +  */
+ + #ifndef __LINUX_PWM_H
+ + #define __LINUX_PWM_H
+ + 
+ + enum {
+ + 	FLAG_REGISTERED		= 0,
+ + 	FLAG_REQUESTED		= 1,
+ + 	FLAG_STOP		= 2,
+ + 	FLAG_RUNNING		= 3,
+ + };
+ + 
+ + enum {
+ + 	PWM_CONFIG_DUTY_TICKS	= 0,
+ + 	PWM_CONFIG_PERIOD_TICKS	= 1,
+ + 	PWM_CONFIG_POLARITY	= 2,
+ + 	PWM_CONFIG_START	= 3,
+ + 	PWM_CONFIG_STOP		= 4,
+ + 
+ + 	PWM_CONFIG_HANDLER	= 5,
+ + 
+ + 	PWM_CONFIG_DUTY_NS	= 6,
+ + 	PWM_CONFIG_DUTY_PERCENT	= 7,
+ + 	PWM_CONFIG_PERIOD_NS	= 8,
+ + };
+ + 
+ + struct pwm_config;
+ + struct pwm_device;
+ + 
+ + typedef int (*pwm_handler_t)(struct pwm_device *p, void *data);
+ + typedef void (*pwm_callback_t)(struct pwm_device *p);
+ + 
+ + struct pwm_device_ops {
+ + 	int	(*request)		(struct pwm_device *p);
+ + 	void	(*release)		(struct pwm_device *p);
+ + 	int	(*config)		(struct pwm_device *p,
+ + 					 struct pwm_config *c);
+ + 	int	(*config_nosleep)	(struct pwm_device *p,
+ + 					 struct pwm_config *c);
+ + 	int	(*synchronize)		(struct pwm_device *p,
+ + 					 struct pwm_device *to_p);
+ + 	int	(*unsynchronize)	(struct pwm_device *p,
+ + 					 struct pwm_device *from_p);
+ + 	int	(*set_callback)		(struct pwm_device *p,
+ + 					 pwm_callback_t callback);
+ + 	int	(*freq_transition_notifier_cb) (struct pwm_device *p);
+ + };
+ + 
+ + struct pwm_config {
+ + 	unsigned long config_mask;
+ + 	unsigned long duty_ticks;
+ + 	unsigned long period_ticks;
+ + 	int polarity;
+ + 
+ + 	pwm_handler_t handler;
+ + 
+ + 	unsigned long duty_ns;
+ + 	unsigned long period_ns;
+ + 	int duty_percent;
+ + };
+ + 
+ + struct pwm_device {
+ + 	struct list_head list;
+ + 
+ + 	struct device *dev;
+ + 	struct pwm_device_ops *ops;
+ + 
+ + 	void *data;
+ + 
+ + 	const char *label;
+ + 	pid_t pid;
+ + 
+ + 	volatile unsigned long flags;
+ + 
+ + 	unsigned long tick_hz;
+ + 
+ + 	pwm_callback_t callback;
+ + 
+ + 	struct work_struct handler_work;
+ + 	pwm_handler_t handler;
+ + 	void *handler_data;
+ + 
+ + 	int active_high;
+ + 	unsigned long period_ticks;
+ + 	unsigned long duty_ticks;
+ + 	unsigned long period_ns;
+ + 	unsigned long duty_ns;
+ + 	struct notifier_block freq_transition;
+ + 	unsigned long max_period_ticks;
+ + 	spinlock_t pwm_lock;
+ + };
+ + 
+ + #include <linux/semaphore.h>
+ + #include <linux/pwm/ehrpwm.h>
+ + 
+ + enum {
+ + 	PWM_VERSION_0,
+ + 	PWM_VERSION_1,
+ + };
+ + 
+ + struct pwm_chan_attrib {
+ + 	int max_freq;
+ + 	bool inverse_pol;
+ + };
+ + 
+ + #define PWM_CHANNEL NCHAN
+ + 
+ + struct pwmss_platform_data {
+ + 	int channel_mask;
+ + 	u8 version;
+ + 	struct pwm_chan_attrib chan_attrib[PWM_CHANNEL];
+ + };
+ + 
+ + struct pwm_device *pwm_request_byname(const char *name, const char *label);
+ + struct pwm_device *pwm_request(const char *bus_id, int id, const char *label);
+ + void pwm_release(struct pwm_device *p);
+ + 
+ + static inline int pwm_is_registered(struct pwm_device *p)
+ + {
+ + 	return test_bit(FLAG_REGISTERED, &p->flags);
+ + }
+ + 
+ + static inline int pwm_is_requested(struct pwm_device *p)
+ + {
+ + 	return test_bit(FLAG_REQUESTED, &p->flags);
+ + }
+ + 
+ + static inline int pwm_is_running(struct pwm_device *p)
+ + {
+ + 	return test_bit(FLAG_RUNNING, &p->flags);
+ + }
+ + 
+ + static inline void pwm_set_drvdata(struct pwm_device *p, void *data)
+ + {
+ + 	p->data = data;
+ + }
+ + 
+ + static inline void *pwm_get_drvdata(const struct pwm_device *p)
+ + {
+ + 	return p->data;
+ + }
+ + 
+ + unsigned long pwm_ns_to_ticks(struct pwm_device *p, unsigned long nsecs);
+ + unsigned long pwm_ticks_to_ns(struct pwm_device *p, unsigned long ticks);
+ + 
+ + int pwm_config_nosleep(struct pwm_device *p, struct pwm_config *c);
+ + int pwm_config(struct pwm_device *p, struct pwm_config *c);
+ + 
+ + int pwm_set_period_ns(struct pwm_device *p, unsigned long period_ns);
+ + unsigned long pwm_get_period_ns(struct pwm_device *p);
+ + int pwm_set_duty_ns(struct pwm_device *p, unsigned long duty_ns);
+ + unsigned long pwm_get_duty_ns(struct pwm_device *p);
+ + int pwm_set_duty_percent(struct pwm_device *p, int percent);
+ + int pwm_set_polarity(struct pwm_device *p, int active_high);
+ + 
+ + int pwm_start(struct pwm_device *p);
+ + int pwm_stop(struct pwm_device *p);
+ + 
+ + int pwm_synchronize(struct pwm_device *p, struct pwm_device *to_p);
+ + int pwm_unsynchronize(struct pwm_device *p, struct pwm_device *from_p);
+ + int pwm_set_handler(struct pwm_device *p, pwm_handler_t handler, void *data);
+ + 
+ + int pwm_register(struct pwm_device *p, struct device *parent, int id);
+ + int pwm_register_byname(struct pwm_device *p, struct device *parent,
+ + 			const char *name);
+ + int pwm_unregister(struct pwm_device *p);
+ + 
+ + #ifdef CONFIG_GPIO_PWM
+ + struct pwm_device *gpio_pwm_create(int gpio);
+ + int gpio_pwm_destroy(struct pwm_device *p);
+ + #endif
+ + int pwm_set_frequency(struct pwm_device *p, unsigned long freq);
+ + unsigned long pwm_get_frequency(struct pwm_device *p);
+ + int pwm_set_period_ticks(struct pwm_device *p,
+ + 					unsigned long ticks);
+ + unsigned long pwm_get_duty_percent(struct pwm_device *p);
+ + int pwm_set_duty_ticks(struct pwm_device *p,
+ + 					unsigned long ticks);
+ + #endif
+ diff -crN linux-3.2.1_o/include/linux/pwm_backlight.h linux-3.2.1/include/linux/pwm_backlight.h
+ *** linux-3.2.1_o/include/linux/pwm_backlight.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/include/linux/pwm_backlight.h	2014-11-25 13:19:17.327092208 +0900
+ ***************
+ *** 7,13 ****
+   #include <linux/backlight.h>
+   
+   struct platform_pwm_backlight_data {
+ ! 	int pwm_id;
+   	unsigned int max_brightness;
+   	unsigned int dft_brightness;
+   	unsigned int lth_brightness;
+ --- 7,14 ----
+   #include <linux/backlight.h>
+   
+   struct platform_pwm_backlight_data {
+ ! 	const char *pwm_id;
+ ! 	int ch;
+   	unsigned int max_brightness;
+   	unsigned int dft_brightness;
+   	unsigned int lth_brightness;
+ diff -crN linux-3.2.1_o/include/linux/random.h linux-3.2.1/include/linux/random.h
+ *** linux-3.2.1_o/include/linux/random.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/include/linux/random.h	2014-11-25 13:19:17.343631868 +0900
+ ***************
+ *** 34,39 ****
+ --- 34,63 ----
+   /* Clear the entropy pool and associated counters.  (Superuser only.) */
+   #define RNDCLEARPOOL	_IO( 'R', 0x06 )
+   
+ + #ifdef CONFIG_FIPS_RNG
+ + 
+ + /* Size of seed value - equal to AES blocksize */
+ + #define AES_BLOCK_SIZE_BYTES	16
+ + #define SEED_SIZE_BYTES			AES_BLOCK_SIZE_BYTES
+ + /* Size of AES key */
+ + #define KEY_SIZE_BYTES		16
+ + 
+ + /* ioctl() structure used by FIPS 140-2 Tests */
+ + struct rand_fips_test {
+ + 	unsigned char key[KEY_SIZE_BYTES];			/* Input */
+ + 	unsigned char datetime[SEED_SIZE_BYTES];	/* Input */
+ + 	unsigned char seed[SEED_SIZE_BYTES];		/* Input */
+ + 	unsigned char result[SEED_SIZE_BYTES];		/* Output */
+ + };
+ + 
+ + /* FIPS 140-2 RNG Variable Seed Test. (Superuser only.) */
+ + #define RNDFIPSVST	_IOWR('R', 0x10, struct rand_fips_test)
+ + 
+ + /* FIPS 140-2 RNG Monte Carlo Test. (Superuser only.) */
+ + #define RNDFIPSMCT	_IOWR('R', 0x11, struct rand_fips_test)
+ + 
+ + #endif /* #ifdef CONFIG_FIPS_RNG */
+ + 
+   struct rand_pool_info {
+   	int	entropy_count;
+   	int	buf_size;
+ ***************
+ *** 54,59 ****
+ --- 78,87 ----
+   				 unsigned int value);
+   extern void add_interrupt_randomness(int irq);
+   
+ + extern void random_input_words(__u32 *buf, size_t wordcount, int ent_count);
+ + extern int random_input_wait(void);
+ + #define HAS_RANDOM_INPUT_WAIT 1
+ + 
+   extern void get_random_bytes(void *buf, int nbytes);
+   void generate_random_uuid(unsigned char uuid_out[16]);
+   
+ diff -crN linux-3.2.1_o/include/linux/rcupdate.h linux-3.2.1/include/linux/rcupdate.h
+ *** linux-3.2.1_o/include/linux/rcupdate.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/include/linux/rcupdate.h	2014-11-25 13:19:17.349102269 +0900
+ ***************
+ *** 800,812 ****
+   	return offset < 4096;
+   }
+   
+   static __always_inline
+   void __kfree_rcu(struct rcu_head *head, unsigned long offset)
+   {
+   	typedef void (*rcu_callback)(struct rcu_head *);
+   
+ - 	BUILD_BUG_ON(!__builtin_constant_p(offset));
+ - 
+   	/* See the kfree_rcu() header comment. */
+   	BUILD_BUG_ON(!__is_kfree_rcu_offset(offset));
+   
+ --- 800,813 ----
+   	return offset < 4096;
+   }
+   
+ + /*
+ +  * Intended to be called only from the kfree_rcu() macro.
+ +  */
+   static __always_inline
+   void __kfree_rcu(struct rcu_head *head, unsigned long offset)
+   {
+   	typedef void (*rcu_callback)(struct rcu_head *);
+   
+   	/* See the kfree_rcu() header comment. */
+   	BUILD_BUG_ON(!__is_kfree_rcu_offset(offset));
+   
+ diff -crN linux-3.2.1_o/include/linux/regulator/driver.h linux-3.2.1/include/linux/regulator/driver.h
+ *** linux-3.2.1_o/include/linux/regulator/driver.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/include/linux/regulator/driver.h	2014-11-25 13:19:17.353087324 +0900
+ ***************
+ *** 204,210 ****
+   	int deferred_disables;
+   
+   	void *reg_data;		/* regulator_dev data */
+ ! 
+   #ifdef CONFIG_DEBUG_FS
+   	struct dentry *debugfs;
+   #endif
+ --- 204,210 ----
+   	int deferred_disables;
+   
+   	void *reg_data;		/* regulator_dev data */
+ !         int ignore_check_consumers;
+   #ifdef CONFIG_DEBUG_FS
+   	struct dentry *debugfs;
+   #endif
+ diff -crN linux-3.2.1_o/include/linux/regulator/machine.h linux-3.2.1/include/linux/regulator/machine.h
+ *** linux-3.2.1_o/include/linux/regulator/machine.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/include/linux/regulator/machine.h	2014-11-25 13:19:17.361098995 +0900
+ ***************
+ *** 169,175 ****
+    *               be usable.
+    * @num_consumer_supplies: Number of consumer device supplies.
+    * @consumer_supplies: Consumer device supply configuration.
+ !  *
+    * @regulator_init: Callback invoked when the regulator has been registered.
+    * @driver_data: Data passed to regulator_init.
+    */
+ --- 169,175 ----
+    *               be usable.
+    * @num_consumer_supplies: Number of consumer device supplies.
+    * @consumer_supplies: Consumer device supply configuration.
+ !  * @ignore_check_consumers: If != 0, regulator_check_consumers() is disabled.
+    * @regulator_init: Callback invoked when the regulator has been registered.
+    * @driver_data: Data passed to regulator_init.
+    */
+ ***************
+ *** 181,186 ****
+ --- 181,187 ----
+   	int num_consumer_supplies;
+   	struct regulator_consumer_supply *consumer_supplies;
+   
+ +         int ignore_check_consumers;
+   	/* optional regulator machine specific init */
+   	int (*regulator_init)(void *driver_data);
+   	void *driver_data;	/* core does not touch this */
+ diff -crN linux-3.2.1_o/include/linux/rtc/rtc-omap.h linux-3.2.1/include/linux/rtc/rtc-omap.h
+ *** linux-3.2.1_o/include/linux/rtc/rtc-omap.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/include/linux/rtc/rtc-omap.h	2014-11-25 13:19:17.363081579 +0900
+ ***************
+ *** 0 ****
+ --- 1,30 ----
+ + /*
+ +  * RTC-OMAP driver platform header
+ +  *
+ +  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #ifndef _LINUX_RTC_OMAP_H_
+ + #define _LINUX_RTC_OMAP_H_
+ + 
+ + /**
+ +  * struct omap_rtc_pdata - OMAP rtc Platform Data
+ +  *
+ +  * @pm_off:		Flag to specify whether the RTC is incharge of
+ +  *			controlling the system/device power.
+ +  * @wakeup_capable:	module supports wakeup from suspend with alarm events
+ +  */
+ + struct omap_rtc_pdata {
+ + 	bool pm_off;
+ + 	unsigned wakeup_capable:1;
+ + };
+ + #endif
+ diff -crN linux-3.2.1_o/include/linux/sched.h linux-3.2.1/include/linux/sched.h
+ *** linux-3.2.1_o/include/linux/sched.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/include/linux/sched.h	2014-11-25 13:19:17.363081579 +0900
+ ***************
+ *** 1302,1307 ****
+ --- 1302,1312 ----
+   	unsigned sched_reset_on_fork:1;
+   	unsigned sched_contributes_to_load:1;
+   
+ + #ifdef CONFIG_GENERIC_HARDIRQS
+ + 	/* IRQ handler threads */
+ + 	unsigned irq_thread:1;
+ + #endif
+ + 
+   	pid_t pid;
+   	pid_t tgid;
+   
+ ***************
+ *** 1410,1420 ****
+    * mempolicy */
+   	spinlock_t alloc_lock;
+   
+ - #ifdef CONFIG_GENERIC_HARDIRQS
+ - 	/* IRQ handler threads */
+ - 	struct irqaction *irqaction;
+ - #endif
+ - 
+   	/* Protection of the PI data structures: */
+   	raw_spinlock_t pi_lock;
+   
+ --- 1415,1420 ----
+ diff -crN linux-3.2.1_o/include/linux/sockios.h linux-3.2.1/include/linux/sockios.h
+ *** linux-3.2.1_o/include/linux/sockios.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/include/linux/sockios.h	2014-11-25 13:19:17.367959031 +0900
+ ***************
+ *** 127,132 ****
+ --- 127,135 ----
+   /* hardware time stamping: parameters in linux/net_tstamp.h */
+   #define SIOCSHWTSTAMP   0x89b0
+   
+ + /* Switch config calls: parameters in linux/net_switch_config.h */
+ + #define SIOCSWITCHCONFIG    0x89c0
+ + 
+   /* Device private ioctl calls */
+   
+   /*
+ diff -crN linux-3.2.1_o/include/linux/syscalls.h linux-3.2.1/include/linux/syscalls.h
+ *** linux-3.2.1_o/include/linux/syscalls.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/include/linux/syscalls.h	2014-11-25 13:19:17.376122626 +0900
+ ***************
+ *** 856,860 ****
+ --- 856,862 ----
+   				      const struct iovec __user *rvec,
+   				      unsigned long riovcnt,
+   				      unsigned long flags);
+ + asmlinkage long sys_ckb3352_change_mux(const char __user *pin_name, unsigned int mux_mode,
+ + 				  unsigned int flags);
+   
+   #endif
+ diff -crN linux-3.2.1_o/include/linux/usb/ch9.h linux-3.2.1/include/linux/usb/ch9.h
+ *** linux-3.2.1_o/include/linux/usb/ch9.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/include/linux/usb/ch9.h	2014-11-25 13:19:17.384135721 +0900
+ ***************
+ *** 605,630 ****
+   } __attribute__ ((packed));
+   
+   #define USB_DT_SS_EP_COMP_SIZE		6
+ - 
+   /* Bits 4:0 of bmAttributes if this is a bulk endpoint */
+ ! static inline int
+ ! usb_ss_max_streams(const struct usb_ss_ep_comp_descriptor *comp)
+ ! {
+ ! 	int		max_streams;
+ ! 
+ ! 	if (!comp)
+ ! 		return 0;
+ ! 
+ ! 	max_streams = comp->bmAttributes & 0x1f;
+ ! 
+ ! 	if (!max_streams)
+ ! 		return 0;
+ ! 
+ ! 	max_streams = 1 << max_streams;
+ ! 
+ ! 	return max_streams;
+ ! }
+ ! 
+   /* Bits 1:0 of bmAttributes if this is an isoc endpoint */
+   #define USB_SS_MULT(p)			(1 + ((p) & 0x3))
+   
+ --- 605,612 ----
+   } __attribute__ ((packed));
+   
+   #define USB_DT_SS_EP_COMP_SIZE		6
+   /* Bits 4:0 of bmAttributes if this is a bulk endpoint */
+ ! #define USB_SS_MAX_STREAMS(p)		(1 << ((p) & 0x1f))
+   /* Bits 1:0 of bmAttributes if this is an isoc endpoint */
+   #define USB_SS_MULT(p)			(1 + ((p) & 0x3))
+   
+ diff -crN linux-3.2.1_o/include/linux/usb/gadget.h linux-3.2.1/include/linux/usb/gadget.h
+ *** linux-3.2.1_o/include/linux/usb/gadget.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/include/linux/usb/gadget.h	2014-11-25 13:19:17.388119132 +0900
+ ***************
+ *** 477,484 ****
+    *	driver setup() requests
+    * @ep_list: List of other endpoints supported by the device.
+    * @speed: Speed of current connection to USB host.
+ !  * @is_dualspeed: True if the controller supports both high and full speed
+ !  *	operation.  If it does, the gadget driver must also support both.
+    * @is_otg: True if the USB device port uses a Mini-AB jack, so that the
+    *	gadget driver must provide a USB OTG descriptor.
+    * @is_a_peripheral: False unless is_otg, the "A" end of a USB cable
+ --- 477,484 ----
+    *	driver setup() requests
+    * @ep_list: List of other endpoints supported by the device.
+    * @speed: Speed of current connection to USB host.
+ !  * @max_speed: Maximal speed the UDC can handle.  UDC must support this
+ !  *      and all slower speeds.
+    * @is_otg: True if the USB device port uses a Mini-AB jack, so that the
+    *	gadget driver must provide a USB OTG descriptor.
+    * @is_a_peripheral: False unless is_otg, the "A" end of a USB cable
+ ***************
+ *** 518,524 ****
+   	struct usb_ep			*ep0;
+   	struct list_head		ep_list;	/* of usb_ep */
+   	enum usb_device_speed		speed;
+ ! 	unsigned			is_dualspeed:1;
+   	unsigned			is_otg:1;
+   	unsigned			is_a_peripheral:1;
+   	unsigned			b_hnp_enable:1;
+ --- 518,524 ----
+   	struct usb_ep			*ep0;
+   	struct list_head		ep_list;	/* of usb_ep */
+   	enum usb_device_speed		speed;
+ ! 	enum usb_device_speed		max_speed;
+   	unsigned			is_otg:1;
+   	unsigned			is_a_peripheral:1;
+   	unsigned			b_hnp_enable:1;
+ ***************
+ *** 549,555 ****
+   static inline int gadget_is_dualspeed(struct usb_gadget *g)
+   {
+   #ifdef CONFIG_USB_GADGET_DUALSPEED
+ ! 	/* runtime test would check "g->is_dualspeed" ... that might be
+   	 * useful to work around hardware bugs, but is mostly pointless
+   	 */
+   	return 1;
+ --- 549,555 ----
+   static inline int gadget_is_dualspeed(struct usb_gadget *g)
+   {
+   #ifdef CONFIG_USB_GADGET_DUALSPEED
+ ! 	/* runtime test would check "g->max_speed" ... that might be
+   	 * useful to work around hardware bugs, but is mostly pointless
+   	 */
+   	return 1;
+ ***************
+ *** 567,573 ****
+   {
+   #ifdef CONFIG_USB_GADGET_SUPERSPEED
+   	/*
+ ! 	 * runtime test would check "g->is_superspeed" ... that might be
+   	 * useful to work around hardware bugs, but is mostly pointless
+   	 */
+   	return 1;
+ --- 567,573 ----
+   {
+   #ifdef CONFIG_USB_GADGET_SUPERSPEED
+   	/*
+ ! 	 * runtime test would check "g->max_speed" ... that might be
+   	 * useful to work around hardware bugs, but is mostly pointless
+   	 */
+   	return 1;
+ ***************
+ *** 760,766 ****
+   /**
+    * struct usb_gadget_driver - driver for usb 'slave' devices
+    * @function: String describing the gadget's function
+ !  * @speed: Highest speed the driver handles.
+    * @setup: Invoked for ep0 control requests that aren't handled by
+    *	the hardware level driver. Most calls must be handled by
+    *	the gadget driver, including descriptor and configuration
+ --- 760,766 ----
+   /**
+    * struct usb_gadget_driver - driver for usb 'slave' devices
+    * @function: String describing the gadget's function
+ !  * @max_speed: Highest speed the driver handles.
+    * @setup: Invoked for ep0 control requests that aren't handled by
+    *	the hardware level driver. Most calls must be handled by
+    *	the gadget driver, including descriptor and configuration
+ ***************
+ *** 824,830 ****
+    */
+   struct usb_gadget_driver {
+   	char			*function;
+ ! 	enum usb_device_speed	speed;
+   	void			(*unbind)(struct usb_gadget *);
+   	int			(*setup)(struct usb_gadget *,
+   					const struct usb_ctrlrequest *);
+ --- 824,830 ----
+    */
+   struct usb_gadget_driver {
+   	char			*function;
+ ! 	enum usb_device_speed	max_speed;
+   	void			(*unbind)(struct usb_gadget *);
+   	int			(*setup)(struct usb_gadget *,
+   					const struct usb_ctrlrequest *);
+ diff -crN linux-3.2.1_o/include/linux/usb/musb.h linux-3.2.1/include/linux/usb/musb.h
+ *** linux-3.2.1_o/include/linux/usb/musb.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/include/linux/usb/musb.h	2014-11-25 13:19:17.396100090 +0900
+ ***************
+ *** 62,67 ****
+ --- 62,68 ----
+   struct musb_hdrc_config {
+   	struct musb_fifo_cfg	*fifo_cfg;	/* board fifo configuration */
+   	unsigned		fifo_cfg_size;	/* size of the fifo configuration */
+ + 	unsigned short		fifo_mode;	/* fifo mode to be selected */
+   
+   	/* MUSB configuration-specific details */
+   	unsigned	multipoint:1;	/* multipoint device */
+ diff -crN linux-3.2.1_o/include/linux/usb/otg.h linux-3.2.1/include/linux/usb/otg.h
+ *** linux-3.2.1_o/include/linux/usb/otg.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/include/linux/usb/otg.h	2014-11-25 13:19:17.404125753 +0900
+ ***************
+ *** 63,68 ****
+ --- 63,69 ----
+   	struct device		*dev;
+   	const char		*label;
+   	unsigned int		 flags;
+ + 	u8			id;
+   
+   	u8			default_a;
+   	enum usb_otg_state	state;
+ ***************
+ *** 116,132 ****
+   
+   /* for board-specific init logic */
+   extern int otg_set_transceiver(struct otg_transceiver *);
+   
+   #if defined(CONFIG_NOP_USB_XCEIV) || (defined(CONFIG_NOP_USB_XCEIV_MODULE) && defined(MODULE))
+   /* sometimes transceivers are accessed only through e.g. ULPI */
+ ! extern void usb_nop_xceiv_register(void);
+ ! extern void usb_nop_xceiv_unregister(void);
+   #else
+ ! static inline void usb_nop_xceiv_register(void)
+   {
+   }
+   
+ ! static inline void usb_nop_xceiv_unregister(void)
+   {
+   }
+   #endif
+ --- 117,134 ----
+   
+   /* for board-specific init logic */
+   extern int otg_set_transceiver(struct otg_transceiver *);
+ + extern int otg_reset_transceiver(struct otg_transceiver *);
+   
+   #if defined(CONFIG_NOP_USB_XCEIV) || (defined(CONFIG_NOP_USB_XCEIV_MODULE) && defined(MODULE))
+   /* sometimes transceivers are accessed only through e.g. ULPI */
+ ! extern void usb_nop_xceiv_register(int id);
+ ! extern void usb_nop_xceiv_unregister(int id);
+   #else
+ ! static inline void usb_nop_xceiv_register(int id)
+   {
+   }
+   
+ ! static inline void usb_nop_xceiv_unregister(int id)
+   {
+   }
+   #endif
+ ***************
+ *** 166,176 ****
+   
+   /* for usb host and peripheral controller drivers */
+   #ifdef CONFIG_USB_OTG_UTILS
+ ! extern struct otg_transceiver *otg_get_transceiver(void);
+   extern void otg_put_transceiver(struct otg_transceiver *);
+   extern const char *otg_state_string(enum usb_otg_state state);
+   #else
+ ! static inline struct otg_transceiver *otg_get_transceiver(void)
+   {
+   	return NULL;
+   }
+ --- 168,178 ----
+   
+   /* for usb host and peripheral controller drivers */
+   #ifdef CONFIG_USB_OTG_UTILS
+ ! extern struct otg_transceiver *otg_get_transceiver(int id);
+   extern void otg_put_transceiver(struct otg_transceiver *);
+   extern const char *otg_state_string(enum usb_otg_state state);
+   #else
+ ! static inline struct otg_transceiver *otg_get_transceiver(int id)
+   {
+   	return NULL;
+   }
+ diff -crN linux-3.2.1_o/include/linux/usb.h linux-3.2.1/include/linux/usb.h
+ *** linux-3.2.1_o/include/linux/usb.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/include/linux/usb.h	2014-11-25 13:19:17.416090289 +0900
+ ***************
+ *** 1211,1216 ****
+ --- 1211,1217 ----
+   	struct list_head urb_list;	/* list head for use by the urb's
+   					 * current owner */
+   	struct list_head anchor_list;	/* the URB may be anchored */
+ + 	struct list_head giveback_list;	/* to postpone the giveback call */
+   	struct usb_anchor *anchor;
+   	struct usb_device *dev;		/* (in) pointer to associated device */
+   	struct usb_host_endpoint *ep;	/* (internal) pointer to endpoint */
+ ***************
+ *** 1221,1227 ****
+   	void *transfer_buffer;		/* (in) associated data buffer */
+   	dma_addr_t transfer_dma;	/* (in) dma addr for transfer_buffer */
+   	struct scatterlist *sg;		/* (in) scatter gather buffer list */
+ - 	int num_mapped_sgs;		/* (internal) mapped sg entries */
+   	int num_sgs;			/* (in) number of entries in the sg list */
+   	u32 transfer_buffer_length;	/* (in) data buffer length */
+   	u32 actual_length;		/* (return) actual transfer length */
+ --- 1222,1227 ----
+ diff -crN linux-3.2.1_o/include/linux/vmalloc.h linux-3.2.1/include/linux/vmalloc.h
+ *** linux-3.2.1_o/include/linux/vmalloc.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/include/linux/vmalloc.h	2014-11-25 13:19:17.444119579 +0900
+ ***************
+ *** 131,136 ****
+ --- 131,137 ----
+    */
+   extern rwlock_t vmlist_lock;
+   extern struct vm_struct *vmlist;
+ + extern __init void vm_area_add_early(struct vm_struct *vm);
+   extern __init void vm_area_register_early(struct vm_struct *vm, size_t align);
+   
+   #ifdef CONFIG_SMP
+ diff -crN linux-3.2.1_o/include/linux/wl12xx.h linux-3.2.1/include/linux/wl12xx.h
+ *** linux-3.2.1_o/include/linux/wl12xx.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/include/linux/wl12xx.h	2014-11-25 13:19:17.447123938 +0900
+ ***************
+ *** 54,59 ****
+ --- 54,61 ----
+   	int board_ref_clock;
+   	int board_tcxo_clock;
+   	unsigned long platform_quirks;
+ + 	int bt_enable_gpio;
+ + 	int wlan_enable_gpio;
+   };
+   
+   /* Platform does not support level trigger interrupts */
+ diff -crN linux-3.2.1_o/include/mtd/ckb_gpmc_cs1.h linux-3.2.1/include/mtd/ckb_gpmc_cs1.h
+ *** linux-3.2.1_o/include/mtd/ckb_gpmc_cs1.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/include/mtd/ckb_gpmc_cs1.h	2014-11-25 13:19:17.452103131 +0900
+ ***************
+ *** 0 ****
+ --- 1,58 ----
+ + /*
+ +  * Sharp LR35504 board : WRAM access header
+ +  *
+ +  * Copyright (C) 2013 Computex Co.Ltd.
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; version 2 of the License.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ +  *
+ +  */
+ + 
+ + #ifndef __MTD_CKB_EMIF_CS5_H
+ + #define __MTD_CKB_EMIF_CS5_H
+ + 
+ + #define CKB_GPMC_CS1_DEV_NAME			"gpmc_cs1"
+ + #define CKB_GPMC_CS1_MAJOR				255
+ + 
+ + #define CKB_GPMC_CS1_BASE			0x09000000
+ + 
+ + /* Register offsets */
+ + #define GPMC_CONFIG1_1	0x090
+ + #define GPMC_CONFIG2_1	0x094
+ + #define GPMC_CONFIG3_1	0x098
+ + #define GPMC_CONFIG4_1	0x09c
+ + #define GPMC_CONFIG5_1	0x0A0
+ + #define GPMC_CONFIG6_1	0x0A4
+ + #define GPMC_CONFIG7_1	0x0A8
+ + 
+ + 
+ + #define DEVICESIZE_MASK		(0x3<<12)
+ + 
+ + 
+ + struct ckb_gpmc_cs1_device {
+ + 	struct platform_device *pdev;
+ + 
+ + 	unsigned long	phys_base;
+ + 	unsigned long 	mem_size;
+ + 	void __iomem	*mmio_base;
+ + 	struct device *dev;
+ + };
+ + 
+ + struct ckb_gpmc_cs1_dev {
+ + 	struct ckb_gpmc_cs1_device *device;
+ + };
+ + 
+ + #include  <mtd/ckb_gpmc_cs1_ioctl.h>
+ + 
+ + #endif /* __MTD_CKB_EMIF_CS5_H */
+ + 
+ diff -crN linux-3.2.1_o/include/mtd/ckb_gpmc_cs1_ioctl.h linux-3.2.1/include/mtd/ckb_gpmc_cs1_ioctl.h
+ *** linux-3.2.1_o/include/mtd/ckb_gpmc_cs1_ioctl.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/include/mtd/ckb_gpmc_cs1_ioctl.h	2014-11-25 13:19:17.452103131 +0900
+ ***************
+ *** 0 ****
+ --- 1,103 ----
+ + /*
+ +  * Sharp LR35504 board : WRAM access header
+ +  *
+ +  * Copyright (C) 2013 Computex Co.Ltd.
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; version 2 of the License.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ +  *
+ +  */
+ + 
+ + #ifndef __MTD_CKB_EMIF_CS5_IOCTL_H
+ + #define __MTD_CKB_EMIF_CS5_IOCTL_H
+ + 
+ + #define CKB_GPMC_CS1_IOCTL_SET_CONFIG1_REG 		_IOW('C', 1, int)
+ + #define CKB_GPMC_CS1_IOCTL_GET_CONFIG1_REG 		_IOR('C', 2, int)
+ + #define CKB_GPMC_CS1_IOCTL_SET_CONFIG2_REG 		_IOW('C', 3, int)
+ + #define CKB_GPMC_CS1_IOCTL_GET_CONFIG2_REG 		_IOR('C', 4, int)
+ + #define CKB_GPMC_CS1_IOCTL_SET_CONFIG3_REG 		_IOW('C', 5, int)
+ + #define CKB_GPMC_CS1_IOCTL_GET_CONFIG3_REG 		_IOR('C', 6, int)
+ + #define CKB_GPMC_CS1_IOCTL_SET_CONFIG4_REG 		_IOW('C', 7, int)
+ + #define CKB_GPMC_CS1_IOCTL_GET_CONFIG4_REG 		_IOR('C', 8, int)
+ + #define CKB_GPMC_CS1_IOCTL_SET_CONFIG5_REG 		_IOW('C', 9, int)
+ + #define CKB_GPMC_CS1_IOCTL_GET_CONFIG5_REG 		_IOR('C', 10, int)
+ + #define CKB_GPMC_CS1_IOCTL_SET_CONFIG6_REG 		_IOW('C', 11, int)
+ + #define CKB_GPMC_CS1_IOCTL_GET_CONFIG6_REG 		_IOR('C', 12, int)
+ + #define CKB_GPMC_CS1_IOCTL_SET_CONFIG7_REG 		_IOW('C', 13, int)
+ + #define CKB_GPMC_CS1_IOCTL_GET_CONFIG7_REG 		_IOR('C', 14, int)
+ + 
+ + /* GPMC_CONFIG1 */
+ + #define WRAPBURST				(0<<31)
+ + #define READMULTIPLE			(0<<30)
+ + #define READTYPE				(0<<29)
+ + #define WRITEMULTIPLE			(0<<28)
+ + #define WRITETYPE				(0<<27)
+ + #define CLKACTIVATIONTIME		(0<<25)
+ + #define ATTACHDDVICEPAGELENGTH	(0<<23)
+ + #define WAITREADMONITORING		(0<<22)
+ + #define WAITWRITEMONITORING		(0<<21)
+ + #define WAITMONITORINGTIME		(0<<18)
+ + #define WAITPINSELECT			(0<<16)
+ + #define DEVICESIZE_8			(0x0<<12)
+ + #define DEVICESIZE_16			(0x1<<12)
+ + #define DEVICETYPE				(0x0<<10)
+ + #define MUXADDDATA				(0x2<<8)
+ + #define TIMEPARAGRANULARITY		(0<<4)
+ + #define GPMCFCLKDIVIDER			0
+ + 
+ + /* GPMC_CONFIG2 */
+ + #define CSWROFFTIME				(18<<16)
+ + #define CSRDOFFTIME				(18<<8)
+ + #define CEEXTRADELAY			(0<<7)
+ + #define CSONTIME				1
+ + 
+ + /* GPMC_CONFIG3 */
+ + #define ADVADMUXWROFFTIME		(0<<28)
+ + #define ADVAADMUXRDOFFTIME		(0<<24)
+ + #define ADVWROFFTIME			(5<<16)
+ + #define ADVRDOFFTIME			(5<<8)
+ + #define ADVEXTRADELAY			(0<<7)
+ + #define ADVAADMUXONTIME			(0<<4)
+ + #define ADVONTIME				2
+ + 
+ + /* GPMC_CONFIG4 */
+ + #define WEOFFTIME				(16<<24)
+ + #define WEEXTRADELAY			(0<<23)
+ + #define WEONTIME				(8<<16)
+ + #define OEAADMUXOFFTIME			(0<<13)
+ + #define OEOFFTIME				(17<<8)
+ + #define OEEXTRADELAY			(0<<7)
+ + #define OEAADMUXONTIME			(0<<4)
+ + #define OEONTIME				7
+ + 	
+ + /* GPMC_CONFIG5 */
+ + #define PAGEBURSTACCESSTIME		(2<<24)
+ + #define RDACCESSTIME			(16<<16)
+ + #define WRCYCLETIME				(19<<8)
+ + #define RDCYCLETIME				19 
+ + 
+ + /* GPMC_CONFIG6 */
+ + #define WRACCESSTIME			(13 <<24)
+ + #define WRDATAONADMUXBUS		(6 <<16)
+ + #define CYCLE2CYCLEDELAY		(0<<8)
+ + #define CYCLE2CYCLESAMECSEN		(0<<7)
+ + #define CYCLE2CYCLEDIFFCSEN		(0<<6)
+ + #define BUSTURNAROUND			1
+ + 
+ + /* GPMC_CONFIG7 */
+ + #define MASKADDRESS				(0xF<<8)  		// 16MByte
+ + #define CSVALID					(0x1<<6)
+ + 
+ + 
+ + #endif /* __MTD_CKB_EMIF_CS5_IOCTL_H */
+ + 
+ diff -crN linux-3.2.1_o/include/video/ckb_dvi.h linux-3.2.1/include/video/ckb_dvi.h
+ *** linux-3.2.1_o/include/video/ckb_dvi.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/include/video/ckb_dvi.h	2014-11-25 13:19:17.455665165 +0900
+ ***************
+ *** 0 ****
+ --- 1,60 ----
+ + /*
+ +  * Header for CKB DVI driver
+ +  *
+ +  * Copyright (C) 2013 Computex Co.Ltd.
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; version 2 of the License.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ +  *
+ +  */
+ + 
+ + #ifndef __CKB_DVI_H
+ + #define __CKB_DVI_H
+ + 
+ + #define CKB_DVI_NAME			"ckb-dvi"
+ + 
+ + #include <linux/fb.h>
+ + 
+ + struct ckb_dvi_platform_data {
+ + 	int max_xres;
+ + 	int max_yres;
+ + 	int connect_poll_interval;
+ + 	int i2c_port;
+ + };
+ + 
+ + struct ckb_dvi_device {
+ + 	struct platform_device *pdev;
+ + 	unsigned long	phys_base;
+ + 	unsigned long 	mem_size;
+ + 	struct device *dev;
+ + 	struct workqueue_struct *wq;
+ + 	struct work_struct pluggedin_work;
+ + 	struct timer_list pluggedin_timer;
+ + 	unsigned char connector_plugged;
+ + 	struct ckb_dvi_platform_data *plat_data;
+ + };
+ + 
+ + 
+ + struct ckb_dvi_video_timings {
+ + 	u16 x_res;
+ + 	u16 y_res;
+ + 	u16 hsw;	/* Horizontal synchronization pulse width */
+ + 	u16 hfp;	/* Horizontal front porch */
+ + 	u16 hbp;	/* Horizontal back porch */
+ + 	u16 vsw;	/* Vertical synchronization pulse width */
+ + 	u16 vfp;	/* Vertical front porch */
+ + 	u16 vbp;	/* Vertical back porch */
+ + };
+ + 
+ + int get_dvi_info(struct fb_info *info);
+ + #endif /* __CKB_DVI_H */
+ diff -crN linux-3.2.1_o/include/video/ckb_tfp410.h linux-3.2.1/include/video/ckb_tfp410.h
+ *** linux-3.2.1_o/include/video/ckb_tfp410.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/include/video/ckb_tfp410.h	2014-11-25 13:19:17.455665165 +0900
+ ***************
+ *** 0 ****
+ --- 1,49 ----
+ + /*
+ +  * Header for TFP410 I2C driver
+ +  *
+ +  * Copyright (C) 2013 Computex Co.Ltd.
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; version 2 of the License.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ +  *
+ +  */
+ + 
+ + #ifndef __CKB_TFP410_H
+ + #define __CKB_TFP410_H
+ + 
+ + struct omap_dss_device;
+ + 
+ + /**
+ +  * struct tfp410_platform_data - panel driver configuration data
+ +  * @i2c_bus_num: i2c bus id for the panel
+ +  * @power_down_gpio: gpio number for PD pin (or -1 if not available)
+ +  */
+ + struct tfp410_platform_data {
+ +        u16 i2c_bus_num;
+ +        int power_down_gpio;
+ + };
+ + 
+ + 
+ + struct tfp410_priv {
+ + 	 struct i2c_client *client;
+ + 	 struct device *dev;
+ + 	 struct tfp410_platform_data *pdata;
+ + 	 bool (*tfp410_read)(int addr, uint8_t *ch);
+ + 	 bool (*tfp410_write)(int addr, uint8_t ch);
+ + 	 bool (*tfp410_isconnected)(void);
+ + 	 struct i2c_adapter *(*get_i2c_adapter)(void);
+ + };
+ + 
+ + struct tfp410_priv *get_current_tfp410_device(void);
+ + 
+ + #endif /* __CKB_TFP410_H */
+ diff -crN linux-3.2.1_o/include/video/ckb_video_modes.h linux-3.2.1/include/video/ckb_video_modes.h
+ *** linux-3.2.1_o/include/video/ckb_video_modes.h	1970-01-01 09:00:00.000000000 +0900
+ --- linux-3.2.1/include/video/ckb_video_modes.h	2014-11-25 13:19:17.455665165 +0900
+ ***************
+ *** 0 ****
+ --- 1,15 ----
+ + #ifndef CKB_VIDEO_MODES_H
+ + #define CKB_VIDEO_MODES_H
+ + 
+ + #define FBSET_DB_DIR			"/etc"
+ + #define FBSET_DB_FILE			FBSET_DB_DIR"/fb.modes"
+ + 
+ + char create_video_mode_file(void);
+ + void close_video_mode_file(void);
+ + void append_video_mode(const char *name, __u32 xres, __u32 yres, char *duplicate, __u32 clockMhz,
+ + 			__u32 pixclock, __u32 left_margin, __u32 right_margin, __u32 upper_margin, __u32 lower_margin,
+ + 			__u32 hsync_len,  __u32 vsync_len, 	__u32 sync);
+ + void append_fb_mode(void);
+ + void set_fb_panel_info(struct da8xx_panel *da8xx_panels, int size, int bpp);
+ + 
+ + #endif
+ diff -crN linux-3.2.1_o/include/video/da8xx-fb.h linux-3.2.1/include/video/da8xx-fb.h
+ *** linux-3.2.1_o/include/video/da8xx-fb.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/include/video/da8xx-fb.h	2014-11-25 13:19:17.471260354 +0900
+ ***************
+ *** 13,19 ****
+   #define DA8XX_FB_H
+   
+   enum panel_type {
+ ! 	QVGA = 0
+   };
+   
+   enum panel_shade {
+ --- 13,20 ----
+   #define DA8XX_FB_H
+   
+   enum panel_type {
+ ! 	QVGA = 0,
+ ! 	WVGA,
+   };
+   
+   enum panel_shade {
+ ***************
+ *** 28,34 ****
+   };
+   
+   struct display_panel {
+ ! 	enum panel_type panel_type; /* QVGA */
+   	int max_bpp;
+   	int min_bpp;
+   	enum panel_shade panel_shade;
+ --- 29,35 ----
+   };
+   
+   struct display_panel {
+ ! 	enum panel_type panel_type;
+   	int max_bpp;
+   	int min_bpp;
+   	enum panel_shade panel_shade;
+ ***************
+ *** 37,44 ****
+   struct da8xx_lcdc_platform_data {
+   	const char manu_name[10];
+   	void *controller_data;
+ ! 	const char type[25];
+   	void (*panel_power_ctrl)(int);
+   };
+   
+   struct lcd_ctrl_config {
+ --- 38,47 ----
+   struct da8xx_lcdc_platform_data {
+   	const char manu_name[10];
+   	void *controller_data;
+ ! 	const char type[30];
+   	void (*panel_power_ctrl)(int);
+ + 	unsigned long fb_mapped_physaddr;		/* Optional: FB mapped physical address */
+ + 	unsigned long fb_mapped_len;			/* Optional: FB mapped length */
+   };
+   
+   struct lcd_ctrl_config {
+ ***************
+ *** 68,79 ****
+   	/* Mono 8-bit Mode: 1=D0-D7 or 0=D0-D3 */
+   	unsigned char mono_8bit_mode;
+   
+ - 	/* Invert line clock */
+ - 	unsigned char invert_line_clock;
+ - 
+ - 	/* Invert frame clock  */
+ - 	unsigned char invert_frm_clock;
+ - 
+   	/* Horizontal and Vertical Sync Edge: 0=rising 1=falling */
+   	unsigned char sync_edge;
+   
+ --- 71,76 ----
+ ***************
+ *** 82,87 ****
+ --- 79,87 ----
+   
+   	/* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
+   	unsigned char raster_order;
+ + 
+ + 	/* DMA FIFO threshold */
+ + 	int fifo_th;
+   };
+   
+   struct lcd_sync_arg {
+ ***************
+ *** 90,95 ****
+ --- 90,111 ----
+   	int pulse_width;
+   };
+   
+ + 
+ + struct da8xx_panel {
+ + 	const char	name[30];	/* Full name <vendor>_<model> */
+ + 	unsigned short	width;
+ + 	unsigned short	height;
+ + 	int		hfp;		/* Horizontal front porch */
+ + 	int		hbp;		/* Horizontal back porch */
+ + 	int		hsw;		/* Horizontal Sync Pulse Width */
+ + 	int		vfp;		/* Vertical front porch */
+ + 	int		vbp;		/* Vertical back porch */
+ + 	int		vsw;		/* Vertical Sync Pulse Width */
+ + 	unsigned int	pxl_clk;	/* Pixel clock */
+ + 	unsigned char	sync;	/* Invert Pixel clock */
+ + };
+ + 
+ + 
+   /* ioctls */
+   #define FBIOGET_CONTRAST	_IOR('F', 1, int)
+   #define FBIOPUT_CONTRAST	_IOW('F', 2, int)
+ ***************
+ *** 100,104 ****
+ --- 116,127 ----
+   #define FBIPUT_HSYNC		_IOW('F', 9, int)
+   #define FBIPUT_VSYNC		_IOW('F', 10, int)
+   
+ + /* Proprietary FB_SYNC_ flags */
+ + #define FB_SYNC_CLK_INVERT 0x40000000
+ + 
+ + typedef void (*vsync_callback_t)(void *arg);
+ + int register_vsync_cb(vsync_callback_t handler, void *arg, int idx);
+ + int unregister_vsync_cb(vsync_callback_t handler, void *arg, int idx);
+ + 
+   #endif  /* ifndef DA8XX_FB_H */
+   
+ diff -crN linux-3.2.1_o/kernel/cgroup.c linux-3.2.1/kernel/cgroup.c
+ *** linux-3.2.1_o/kernel/cgroup.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/kernel/cgroup.c	2014-11-25 13:19:17.527139356 +0900
+ ***************
+ *** 1175,1184 ****
+   
+   	/*
+   	 * If the 'all' option was specified select all the subsystems,
+ ! 	 * otherwise if 'none', 'name=' and a subsystem name options
+ ! 	 * were not specified, let's default to 'all'
+   	 */
+ ! 	if (all_ss || (!one_ss && !opts->none && !opts->name)) {
+   		for (i = 0; i < CGROUP_SUBSYS_COUNT; i++) {
+   			struct cgroup_subsys *ss = subsys[i];
+   			if (ss == NULL)
+ --- 1175,1184 ----
+   
+   	/*
+   	 * If the 'all' option was specified select all the subsystems,
+ ! 	 * otherwise 'all, 'none' and a subsystem name options were not
+ ! 	 * specified, let's default to 'all'
+   	 */
+ ! 	if (all_ss || (!all_ss && !one_ss && !opts->none)) {
+   		for (i = 0; i < CGROUP_SUBSYS_COUNT; i++) {
+   			struct cgroup_subsys *ss = subsys[i];
+   			if (ss == NULL)
+ diff -crN linux-3.2.1_o/kernel/exit.c linux-3.2.1/kernel/exit.c
+ *** linux-3.2.1_o/kernel/exit.c	2014-11-25 13:15:17.315166994 +0900
+ --- linux-3.2.1/kernel/exit.c	2014-11-25 13:19:17.543140456 +0900
+ ***************
+ *** 937,944 ****
+   		schedule();
+   	}
+   
+ - 	exit_irq_thread();
+ - 
+   	exit_signals(tsk);  /* sets PF_EXITING */
+   	/*
+   	 * tsk->flags are checked in the futex code to protect against
+ --- 937,942 ----
+ ***************
+ *** 947,952 ****
+ --- 945,952 ----
+   	smp_mb();
+   	raw_spin_unlock_wait(&tsk->pi_lock);
+   
+ + 	exit_irq_thread();
+ + 
+   	if (unlikely(in_atomic()))
+   		printk(KERN_INFO "note: %s[%d] exited with preempt_count %d\n",
+   				current->comm, task_pid_nr(current),
+ diff -crN linux-3.2.1_o/kernel/irq/autoprobe.c linux-3.2.1/kernel/irq/autoprobe.c
+ *** linux-3.2.1_o/kernel/irq/autoprobe.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/kernel/irq/autoprobe.c	2014-11-25 13:19:17.547516089 +0900
+ ***************
+ *** 53,59 ****
+   			if (desc->irq_data.chip->irq_set_type)
+   				desc->irq_data.chip->irq_set_type(&desc->irq_data,
+   							 IRQ_TYPE_PROBE);
+ ! 			irq_startup(desc);
+   		}
+   		raw_spin_unlock_irq(&desc->lock);
+   	}
+ --- 53,59 ----
+   			if (desc->irq_data.chip->irq_set_type)
+   				desc->irq_data.chip->irq_set_type(&desc->irq_data,
+   							 IRQ_TYPE_PROBE);
+ ! 			irq_startup(desc, false);
+   		}
+   		raw_spin_unlock_irq(&desc->lock);
+   	}
+ ***************
+ *** 70,76 ****
+   		raw_spin_lock_irq(&desc->lock);
+   		if (!desc->action && irq_settings_can_probe(desc)) {
+   			desc->istate |= IRQS_AUTODETECT | IRQS_WAITING;
+ ! 			if (irq_startup(desc))
+   				desc->istate |= IRQS_PENDING;
+   		}
+   		raw_spin_unlock_irq(&desc->lock);
+ --- 70,76 ----
+   		raw_spin_lock_irq(&desc->lock);
+   		if (!desc->action && irq_settings_can_probe(desc)) {
+   			desc->istate |= IRQS_AUTODETECT | IRQS_WAITING;
+ ! 			if (irq_startup(desc, false))
+   				desc->istate |= IRQS_PENDING;
+   		}
+   		raw_spin_unlock_irq(&desc->lock);
+ diff -crN linux-3.2.1_o/kernel/irq/chip.c linux-3.2.1/kernel/irq/chip.c
+ *** linux-3.2.1_o/kernel/irq/chip.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/kernel/irq/chip.c	2014-11-25 13:19:17.555120125 +0900
+ ***************
+ *** 157,175 ****
+   	irqd_set(&desc->irq_data, IRQD_IRQ_MASKED);
+   }
+   
+ ! int irq_startup(struct irq_desc *desc)
+   {
+   	irq_state_clr_disabled(desc);
+   	desc->depth = 0;
+   
+   	if (desc->irq_data.chip->irq_startup) {
+ ! 		int ret = desc->irq_data.chip->irq_startup(&desc->irq_data);
+   		irq_state_clr_masked(desc);
+ ! 		return ret;
+   	}
+ ! 
+ ! 	irq_enable(desc);
+ ! 	return 0;
+   }
+   
+   void irq_shutdown(struct irq_desc *desc)
+ --- 157,178 ----
+   	irqd_set(&desc->irq_data, IRQD_IRQ_MASKED);
+   }
+   
+ ! int irq_startup(struct irq_desc *desc, bool resend)
+   {
+ + 	int ret = 0;
+ + 
+   	irq_state_clr_disabled(desc);
+   	desc->depth = 0;
+   
+   	if (desc->irq_data.chip->irq_startup) {
+ ! 		ret = desc->irq_data.chip->irq_startup(&desc->irq_data);
+   		irq_state_clr_masked(desc);
+ ! 	} else {
+ ! 		irq_enable(desc);
+   	}
+ ! 	if (resend)
+ ! 		check_irq_resend(desc, desc->irq_data.irq);
+ ! 	return ret;
+   }
+   
+   void irq_shutdown(struct irq_desc *desc)
+ ***************
+ *** 625,631 ****
+   		irq_settings_set_noprobe(desc);
+   		irq_settings_set_norequest(desc);
+   		irq_settings_set_nothread(desc);
+ ! 		irq_startup(desc);
+   	}
+   out:
+   	irq_put_desc_busunlock(desc, flags);
+ --- 628,634 ----
+   		irq_settings_set_noprobe(desc);
+   		irq_settings_set_norequest(desc);
+   		irq_settings_set_nothread(desc);
+ ! 		irq_startup(desc, true);
+   	}
+   out:
+   	irq_put_desc_busunlock(desc, flags);
+ diff -crN linux-3.2.1_o/kernel/irq/handle.c linux-3.2.1/kernel/irq/handle.c
+ *** linux-3.2.1_o/kernel/irq/handle.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/kernel/irq/handle.c	2014-11-25 13:19:17.563952317 +0900
+ ***************
+ *** 60,66 ****
+   	 * device interrupt, so no irq storm is lurking. If the
+   	 * RUNTHREAD bit is already set, nothing to do.
+   	 */
+ ! 	if (test_bit(IRQTF_DIED, &action->thread_flags) ||
+   	    test_and_set_bit(IRQTF_RUNTHREAD, &action->thread_flags))
+   		return;
+   
+ --- 60,66 ----
+   	 * device interrupt, so no irq storm is lurking. If the
+   	 * RUNTHREAD bit is already set, nothing to do.
+   	 */
+ ! 	if ((action->thread->flags & PF_EXITING) ||
+   	    test_and_set_bit(IRQTF_RUNTHREAD, &action->thread_flags))
+   		return;
+   
+ ***************
+ *** 110,115 ****
+ --- 110,127 ----
+   	 * threads_oneshot untouched and runs the thread another time.
+   	 */
+   	desc->threads_oneshot |= action->thread_mask;
+ + 
+ + 	/*
+ + 	 * We increment the threads_active counter in case we wake up
+ + 	 * the irq thread. The irq thread decrements the counter when
+ + 	 * it returns from the handler or in the exit path and wakes
+ + 	 * up waiters which are stuck in synchronize_irq() when the
+ + 	 * active count becomes zero. synchronize_irq() is serialized
+ + 	 * against this code (hard irq handler) via IRQS_INPROGRESS
+ + 	 * like the finalize_oneshot() code. See comment above.
+ + 	 */
+ + 	atomic_inc(&desc->threads_active);
+ + 
+   	wake_up_process(action->thread);
+   }
+   
+ diff -crN linux-3.2.1_o/kernel/irq/internals.h linux-3.2.1/kernel/irq/internals.h
+ *** linux-3.2.1_o/kernel/irq/internals.h	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/kernel/irq/internals.h	2014-11-25 13:19:17.572122657 +0900
+ ***************
+ *** 20,33 ****
+   /*
+    * Bits used by threaded handlers:
+    * IRQTF_RUNTHREAD - signals that the interrupt handler thread should run
+ -  * IRQTF_DIED      - handler thread died
+    * IRQTF_WARNED    - warning "IRQ_WAKE_THREAD w/o thread_fn" has been printed
+    * IRQTF_AFFINITY  - irq thread is requested to adjust affinity
+    * IRQTF_FORCED_THREAD  - irq action is force threaded
+    */
+   enum {
+   	IRQTF_RUNTHREAD,
+ - 	IRQTF_DIED,
+   	IRQTF_WARNED,
+   	IRQTF_AFFINITY,
+   	IRQTF_FORCED_THREAD,
+ --- 20,31 ----
+ ***************
+ *** 67,73 ****
+   extern void __disable_irq(struct irq_desc *desc, unsigned int irq, bool susp);
+   extern void __enable_irq(struct irq_desc *desc, unsigned int irq, bool resume);
+   
+ ! extern int irq_startup(struct irq_desc *desc);
+   extern void irq_shutdown(struct irq_desc *desc);
+   extern void irq_enable(struct irq_desc *desc);
+   extern void irq_disable(struct irq_desc *desc);
+ --- 65,71 ----
+   extern void __disable_irq(struct irq_desc *desc, unsigned int irq, bool susp);
+   extern void __enable_irq(struct irq_desc *desc, unsigned int irq, bool resume);
+   
+ ! extern int irq_startup(struct irq_desc *desc, bool resend);
+   extern void irq_shutdown(struct irq_desc *desc);
+   extern void irq_enable(struct irq_desc *desc);
+   extern void irq_disable(struct irq_desc *desc);
+ diff -crN linux-3.2.1_o/kernel/irq/manage.c linux-3.2.1/kernel/irq/manage.c
+ *** linux-3.2.1_o/kernel/irq/manage.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/kernel/irq/manage.c	2014-11-25 13:19:17.579598568 +0900
+ ***************
+ *** 645,651 ****
+    * is marked MASKED.
+    */
+   static void irq_finalize_oneshot(struct irq_desc *desc,
+ ! 				 struct irqaction *action, bool force)
+   {
+   	if (!(desc->istate & IRQS_ONESHOT))
+   		return;
+ --- 645,651 ----
+    * is marked MASKED.
+    */
+   static void irq_finalize_oneshot(struct irq_desc *desc,
+ ! 				 struct irqaction *action)
+   {
+   	if (!(desc->istate & IRQS_ONESHOT))
+   		return;
+ ***************
+ *** 679,685 ****
+   	 * we would clear the threads_oneshot bit of this thread which
+   	 * was just set.
+   	 */
+ ! 	if (!force && test_bit(IRQTF_RUNTHREAD, &action->thread_flags))
+   		goto out_unlock;
+   
+   	desc->threads_oneshot &= ~action->thread_mask;
+ --- 679,685 ----
+   	 * we would clear the threads_oneshot bit of this thread which
+   	 * was just set.
+   	 */
+ ! 	if (test_bit(IRQTF_RUNTHREAD, &action->thread_flags))
+   		goto out_unlock;
+   
+   	desc->threads_oneshot &= ~action->thread_mask;
+ ***************
+ *** 739,745 ****
+   
+   	local_bh_disable();
+   	ret = action->thread_fn(action->irq, action->dev_id);
+ ! 	irq_finalize_oneshot(desc, action, false);
+   	local_bh_enable();
+   	return ret;
+   }
+ --- 739,745 ----
+   
+   	local_bh_disable();
+   	ret = action->thread_fn(action->irq, action->dev_id);
+ ! 	irq_finalize_oneshot(desc, action);
+   	local_bh_enable();
+   	return ret;
+   }
+ ***************
+ *** 755,764 ****
+   	irqreturn_t ret;
+   
+   	ret = action->thread_fn(action->irq, action->dev_id);
+ ! 	irq_finalize_oneshot(desc, action, false);
+   	return ret;
+   }
+   
+   /*
+    * Interrupt handler thread
+    */
+ --- 755,771 ----
+   	irqreturn_t ret;
+   
+   	ret = action->thread_fn(action->irq, action->dev_id);
+ ! 	irq_finalize_oneshot(desc, action);
+   	return ret;
+   }
+   
+ + static void wake_threads_waitq(struct irq_desc *desc)
+ + {
+ + 	if (atomic_dec_and_test(&desc->threads_active) &&
+ + 	    waitqueue_active(&desc->wait_for_threads))
+ + 		wake_up(&desc->wait_for_threads);
+ + }
+ + 
+   /*
+    * Interrupt handler thread
+    */
+ ***************
+ *** 771,827 ****
+   	struct irq_desc *desc = irq_to_desc(action->irq);
+   	irqreturn_t (*handler_fn)(struct irq_desc *desc,
+   			struct irqaction *action);
+ - 	int wake;
+   
+ ! 	if (force_irqthreads & test_bit(IRQTF_FORCED_THREAD,
+   					&action->thread_flags))
+   		handler_fn = irq_forced_thread_fn;
+   	else
+   		handler_fn = irq_thread_fn;
+   
+   	sched_setscheduler(current, SCHED_FIFO, &param);
+ ! 	current->irqaction = action;
+   
+   	while (!irq_wait_for_interrupt(action)) {
+   
+   		irq_thread_check_affinity(desc, action);
+   
+ ! 		atomic_inc(&desc->threads_active);
+ ! 
+ ! 		raw_spin_lock_irq(&desc->lock);
+ ! 		if (unlikely(irqd_irq_disabled(&desc->irq_data))) {
+ ! 			/*
+ ! 			 * CHECKME: We might need a dedicated
+ ! 			 * IRQ_THREAD_PENDING flag here, which
+ ! 			 * retriggers the thread in check_irq_resend()
+ ! 			 * but AFAICT IRQS_PENDING should be fine as it
+ ! 			 * retriggers the interrupt itself --- tglx
+ ! 			 */
+ ! 			desc->istate |= IRQS_PENDING;
+ ! 			raw_spin_unlock_irq(&desc->lock);
+ ! 		} else {
+ ! 			irqreturn_t action_ret;
+ ! 
+ ! 			raw_spin_unlock_irq(&desc->lock);
+ ! 			action_ret = handler_fn(desc, action);
+ ! 			if (!noirqdebug)
+ ! 				note_interrupt(action->irq, desc, action_ret);
+ ! 		}
+ ! 
+ ! 		wake = atomic_dec_and_test(&desc->threads_active);
+   
+ ! 		if (wake && waitqueue_active(&desc->wait_for_threads))
+ ! 			wake_up(&desc->wait_for_threads);
+   	}
+   
+ - 	/* Prevent a stale desc->threads_oneshot */
+ - 	irq_finalize_oneshot(desc, action, true);
+ - 
+   	/*
+ ! 	 * Clear irqaction. Otherwise exit_irq_thread() would make
+   	 * fuzz about an active irq thread going into nirvana.
+   	 */
+ ! 	current->irqaction = NULL;
+   	return 0;
+   }
+   
+ --- 778,818 ----
+   	struct irq_desc *desc = irq_to_desc(action->irq);
+   	irqreturn_t (*handler_fn)(struct irq_desc *desc,
+   			struct irqaction *action);
+   
+ ! 	if (force_irqthreads && test_bit(IRQTF_FORCED_THREAD,
+   					&action->thread_flags))
+   		handler_fn = irq_forced_thread_fn;
+   	else
+   		handler_fn = irq_thread_fn;
+   
+   	sched_setscheduler(current, SCHED_FIFO, &param);
+ ! 	current->irq_thread = 1;
+   
+   	while (!irq_wait_for_interrupt(action)) {
+ + 		irqreturn_t action_ret;
+   
+   		irq_thread_check_affinity(desc, action);
+   
+ ! 		action_ret = handler_fn(desc, action);
+ ! 		if (!noirqdebug)
+ ! 			note_interrupt(action->irq, desc, action_ret);
+   
+ ! 		wake_threads_waitq(desc);
+   	}
+   
+   	/*
+ ! 	 * This is the regular exit path. __free_irq() is stopping the
+ ! 	 * thread via kthread_stop() after calling
+ ! 	 * synchronize_irq(). So neither IRQTF_RUNTHREAD nor the
+ ! 	 * oneshot mask bit can be set. We cannot verify that as we
+ ! 	 * cannot touch the oneshot mask at this point anymore as
+ ! 	 * __setup_irq() might have given out currents thread_mask
+ ! 	 * again.
+ ! 	 *
+ ! 	 * Clear irq_thread. Otherwise exit_irq_thread() would make
+   	 * fuzz about an active irq thread going into nirvana.
+   	 */
+ ! 	current->irq_thread = 0;
+   	return 0;
+   }
+   
+ ***************
+ *** 832,858 ****
+   {
+   	struct task_struct *tsk = current;
+   	struct irq_desc *desc;
+   
+ ! 	if (!tsk->irqaction)
+   		return;
+   
+   	printk(KERN_ERR
+   	       "exiting task \"%s\" (%d) is an active IRQ thread (irq %d)\n",
+ ! 	       tsk->comm ? tsk->comm : "", tsk->pid, tsk->irqaction->irq);
+   
+ ! 	desc = irq_to_desc(tsk->irqaction->irq);
+   
+   	/*
+ ! 	 * Prevent a stale desc->threads_oneshot. Must be called
+ ! 	 * before setting the IRQTF_DIED flag.
+   	 */
+ ! 	irq_finalize_oneshot(desc, tsk->irqaction, true);
+   
+ ! 	/*
+ ! 	 * Set the THREAD DIED flag to prevent further wakeups of the
+ ! 	 * soon to be gone threaded handler.
+ ! 	 */
+ ! 	set_bit(IRQTF_DIED, &tsk->irqaction->flags);
+   }
+   
+   static void irq_setup_forced_threading(struct irqaction *new)
+ --- 823,850 ----
+   {
+   	struct task_struct *tsk = current;
+   	struct irq_desc *desc;
+ + 	struct irqaction *action;
+   
+ ! 	if (!tsk->irq_thread)
+   		return;
+   
+ + 	action = kthread_data(tsk);
+ + 
+   	printk(KERN_ERR
+   	       "exiting task \"%s\" (%d) is an active IRQ thread (irq %d)\n",
+ ! 	       tsk->comm ? tsk->comm : "", tsk->pid, action->irq);
+   
+ ! 	desc = irq_to_desc(action->irq);
+   
+   	/*
+ ! 	 * If IRQTF_RUNTHREAD is set, we need to decrement
+ ! 	 * desc->threads_active and wake possible waiters.
+   	 */
+ ! 	if (test_and_clear_bit(IRQTF_RUNTHREAD, &action->thread_flags))
+ ! 		wake_threads_waitq(desc);
+   
+ ! 	/* Prevent a stale desc->threads_oneshot */
+ ! 	irq_finalize_oneshot(desc, action);
+   }
+   
+   static void irq_setup_forced_threading(struct irqaction *new)
+ ***************
+ *** 985,990 ****
+ --- 977,987 ----
+   
+   		/* add new interrupt at end of irq queue */
+   		do {
+ + 			/*
+ + 			 * Or all existing action->thread_mask bits,
+ + 			 * so we can find the next zero bit for this
+ + 			 * new action.
+ + 			 */
+   			thread_mask |= old->thread_mask;
+   			old_ptr = &old->next;
+   			old = *old_ptr;
+ ***************
+ *** 993,1006 ****
+   	}
+   
+   	/*
+ ! 	 * Setup the thread mask for this irqaction. Unlikely to have
+ ! 	 * 32 resp 64 irqs sharing one line, but who knows.
+   	 */
+ ! 	if (new->flags & IRQF_ONESHOT && thread_mask == ~0UL) {
+ ! 		ret = -EBUSY;
+ ! 		goto out_mask;
+   	}
+ - 	new->thread_mask = 1 << ffz(thread_mask);
+   
+   	if (!shared) {
+   		init_waitqueue_head(&desc->wait_for_threads);
+ --- 990,1030 ----
+   	}
+   
+   	/*
+ ! 	 * Setup the thread mask for this irqaction for ONESHOT. For
+ ! 	 * !ONESHOT irqs the thread mask is 0 so we can avoid a
+ ! 	 * conditional in irq_wake_thread().
+   	 */
+ ! 	if (new->flags & IRQF_ONESHOT) {
+ ! 		/*
+ ! 		 * Unlikely to have 32 resp 64 irqs sharing one line,
+ ! 		 * but who knows.
+ ! 		 */
+ ! 		if (thread_mask == ~0UL) {
+ ! 			ret = -EBUSY;
+ ! 			goto out_mask;
+ ! 		}
+ ! 		/*
+ ! 		 * The thread_mask for the action is or'ed to
+ ! 		 * desc->thread_active to indicate that the
+ ! 		 * IRQF_ONESHOT thread handler has been woken, but not
+ ! 		 * yet finished. The bit is cleared when a thread
+ ! 		 * completes. When all threads of a shared interrupt
+ ! 		 * line have completed desc->threads_active becomes
+ ! 		 * zero and the interrupt line is unmasked. See
+ ! 		 * handle.c:irq_wake_thread() for further information.
+ ! 		 *
+ ! 		 * If no thread is woken by primary (hard irq context)
+ ! 		 * interrupt handlers, then desc->threads_active is
+ ! 		 * also checked for zero to unmask the irq line in the
+ ! 		 * affected hard irq flow handlers
+ ! 		 * (handle_[fasteoi|level]_irq).
+ ! 		 *
+ ! 		 * The new action gets the first zero bit of
+ ! 		 * thread_mask assigned. See the loop above which or's
+ ! 		 * all existing action->thread_mask bits.
+ ! 		 */
+ ! 		new->thread_mask = 1 << ffz(thread_mask);
+   	}
+   
+   	if (!shared) {
+   		init_waitqueue_head(&desc->wait_for_threads);
+ ***************
+ *** 1027,1033 ****
+   			desc->istate |= IRQS_ONESHOT;
+   
+   		if (irq_settings_can_autoenable(desc))
+ ! 			irq_startup(desc);
+   		else
+   			/* Undo nested disables: */
+   			desc->depth = 1;
+ --- 1051,1057 ----
+   			desc->istate |= IRQS_ONESHOT;
+   
+   		if (irq_settings_can_autoenable(desc))
+ ! 			irq_startup(desc, true);
+   		else
+   			/* Undo nested disables: */
+   			desc->depth = 1;
+ ***************
+ *** 1103,1110 ****
+   		struct task_struct *t = new->thread;
+   
+   		new->thread = NULL;
+ ! 		if (likely(!test_bit(IRQTF_DIED, &new->thread_flags)))
+ ! 			kthread_stop(t);
+   		put_task_struct(t);
+   	}
+   out_mput:
+ --- 1127,1133 ----
+   		struct task_struct *t = new->thread;
+   
+   		new->thread = NULL;
+ ! 		kthread_stop(t);
+   		put_task_struct(t);
+   	}
+   out_mput:
+ ***************
+ *** 1214,1221 ****
+   #endif
+   
+   	if (action->thread) {
+ ! 		if (!test_bit(IRQTF_DIED, &action->thread_flags))
+ ! 			kthread_stop(action->thread);
+   		put_task_struct(action->thread);
+   	}
+   
+ --- 1237,1243 ----
+   #endif
+   
+   	if (action->thread) {
+ ! 		kthread_stop(action->thread);
+   		put_task_struct(action->thread);
+   	}
+   
+ diff -crN linux-3.2.1_o/kernel/pid.c linux-3.2.1/kernel/pid.c
+ *** linux-3.2.1_o/kernel/pid.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/kernel/pid.c	2014-11-25 13:19:17.587766070 +0900
+ ***************
+ *** 428,433 ****
+ --- 428,434 ----
+   {
+   	return find_task_by_pid_ns(vnr, current->nsproxy->pid_ns);
+   }
+ + EXPORT_SYMBOL(find_task_by_vpid);
+   
+   struct pid *get_task_pid(struct task_struct *task, enum pid_type type)
+   {
+ diff -crN linux-3.2.1_o/mm/vmalloc.c linux-3.2.1/mm/vmalloc.c
+ *** linux-3.2.1_o/mm/vmalloc.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/mm/vmalloc.c	2014-11-25 13:19:17.644290149 +0900
+ ***************
+ *** 1118,1123 ****
+ --- 1118,1149 ----
+   EXPORT_SYMBOL(vm_map_ram);
+   
+   /**
+ +  * vm_area_add_early - add vmap area early during boot
+ +  * @vm: vm_struct to add
+ +  *
+ +  * This function is used to add fixed kernel vm area to vmlist before
+ +  * vmalloc_init() is called.  @vm->addr, @vm->size, and @vm->flags
+ +  * should contain proper values and the other fields should be zero.
+ +  *
+ +  * DO NOT USE THIS FUNCTION UNLESS YOU KNOW WHAT YOU'RE DOING.
+ +  */
+ + void __init vm_area_add_early(struct vm_struct *vm)
+ + {
+ + 	struct vm_struct *tmp, **p;
+ + 
+ + 	BUG_ON(vmap_initialized);
+ + 	for (p = &vmlist; (tmp = *p) != NULL; p = &tmp->next) {
+ + 		if (tmp->addr >= vm->addr) {
+ + 			BUG_ON(tmp->addr < vm->addr + vm->size);
+ + 			break;
+ + 		} else
+ + 			BUG_ON(tmp->addr + tmp->size > vm->addr);
+ + 	}
+ + 	vm->next = *p;
+ + 	*p = vm;
+ + }
+ + 
+ + /**
+    * vm_area_register_early - register vmap area early during boot
+    * @vm: vm_struct to register
+    * @align: requested alignment
+ ***************
+ *** 1139,1146 ****
+   
+   	vm->addr = (void *)addr;
+   
+ ! 	vm->next = vmlist;
+ ! 	vmlist = vm;
+   }
+   
+   void __init vmalloc_init(void)
+ --- 1165,1171 ----
+   
+   	vm->addr = (void *)addr;
+   
+ ! 	vm_area_add_early(vm);
+   }
+   
+   void __init vmalloc_init(void)
+ diff -crN linux-3.2.1_o/net/sched/sch_generic.c linux-3.2.1/net/sched/sch_generic.c
+ *** linux-3.2.1_o/net/sched/sch_generic.c	2012-01-13 04:42:45.000000000 +0900
+ --- linux-3.2.1/net/sched/sch_generic.c	2014-11-25 13:19:17.664138472 +0900
+ ***************
+ *** 251,258 ****
+ --- 251,260 ----
+   			}
+   
+   			if (some_queue_timedout) {
+ + #ifndef CONFIG_MACH_CKB_3352
+   				WARN_ONCE(1, KERN_INFO "NETDEV WATCHDOG: %s (%s): transmit queue %u timed out\n",
+   				       dev->name, netdev_drivername(dev), i);
+ + #endif
+   				dev->netdev_ops->ndo_tx_timeout(dev);
+   			}
+   			if (!mod_timer(&dev->watchdog_timer,
diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-3352/patches/uboot-2012.10-20140328.patch buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-3352/patches/uboot-2012.10-20140328.patch
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-3352/patches/uboot-2012.10-20140328.patch	2014-06-06 11:20:43.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-3352/patches/uboot-2012.10-20140328.patch	1970-01-01 09:00:00.000000000 +0900
***************
*** 1,6174 ****
- diff -crN u-boot-2012.10_o/arch/arm/cpu/armv7/ckb_3352/ckb_3352.c u-boot-2012.10/arch/arm/cpu/armv7/ckb_3352/ckb_3352.c
- *** u-boot-2012.10_o/arch/arm/cpu/armv7/ckb_3352/ckb_3352.c	1970-01-01 09:00:00.000000000 +0900
- --- u-boot-2012.10/arch/arm/cpu/armv7/ckb_3352/ckb_3352.c	2014-02-27 11:33:16.720633268 +0900
- ***************
- *** 0 ****
- --- 1,138 ----
- + /*
- +  * board.c
- +  *
- +  * Common board functions for CKB-3352 board
- +  *
- +  * Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation; either version 2 of
- +  * the License, or (at your option) any later version.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #include <common.h>
- + #include <errno.h>
- + #include <asm/arch/cpu.h>
- + #include <asm/arch/hardware.h>
- + #include <asm/arch/omap.h>
- + #include <asm/arch/ddr_defs.h>
- + #include <asm/arch/clock.h>
- + #include <asm/arch/gpio.h>
- + #include <asm/arch/mem.h>
- + #include <asm/arch/mmc_host_def.h>
- + #include <asm/arch/sys_proto.h>
- + #include <asm/io.h>
- + #include <asm/emif.h>
- + #include <asm/gpio.h>
- + #include <asm/errno.h>
- + 
- + 
- + DECLARE_GLOBAL_DATA_PTR;
- + 
- + struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
- + struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
- + 
- + static const struct gpio_bank gpio_bank_am33xx[4] = {
- + 	{ (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
- + 	{ (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
- + 	{ (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
- + 	{ (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
- + };
- + 
- + const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
- + 
- + #if defined(CONFIG_OMAP_HSMMC)
- + int board_mmc_init(bd_t *bis)
- + {
- + 	int ret;
- + 	
- + 	ret = omap_mmc_init(0, 0, 0);
- + 	if (ret)
- + 		return ret;
- + #if 0
- + 	return omap_mmc_init(1, 0, 0);
- + #else
- + 	return ret;
- + #endif
- + }
- + #endif
- + 
- + void setup_clocks_for_console(void)
- + {
- + 	/* Not yet implemented */
- + 	return;
- + }
- + 
- + 
- + int arch_misc_init(void)
- + {
- + 	return 0;
- + }
- + 
- + /*
- +  * early system init of muxing and clocks.
- +  */
- + void s_init(void)
- + {
- + 	/* WDT1 is already running when the bootloader gets control
- + 	 * Disable it to avoid "random" resets
- + 	 */
- + 	writel(0xAAAA, &wdtimer->wdtwspr);
- + 	while (readl(&wdtimer->wdtwwps) != 0x0)
- + 		;
- + 	writel(0x5555, &wdtimer->wdtwspr);
- + 	while (readl(&wdtimer->wdtwwps) != 0x0)
- + 		;
- + 	
- + }
- + 
- + 
- + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
- + int ckb_3352_cur_flash_bank = -1;
- + void set_nor_flash_bank(int bank)
- + {
- + 	void *reg = gpio_bank_am33xx[1].base + OMAP_GPIO_DATAOUT;
- + 	__raw_writel((__raw_readl(reg) & (~(0x7F<<20))) | (bank<<20), reg);
- + 	//printf("Setting Nor GPIO bank to %d\n", bank);
- + 	ckb_3352_cur_flash_bank = bank;
- + }
- + 
- + /* GPIO bank 1 [20~26] should be configured as output */
- + void init_nor_flash_GPIO()
- + {
- + 	void *reg = gpio_bank_am33xx[1].base + OMAP_GPIO_OE;
- + 	__raw_writel(__raw_readl(reg) & (~(0x7F<<20)), reg);
- + 	/* select bank 0 */
- + 	set_nor_flash_bank(0);
- + }
- + #endif
- + 
- + 
- + /*
- +  * Basic board specific setup.  Pinmux has been handled already.
- +  */
- + int board_init(void)
- + {
- + 	/* Setup the PLLs and the clocks for the peripherals */
- + 	enable_board_pin_mux();
- + 
- + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER	
- + 	/* configure NOT flash GPIO pins */
- + 	init_nor_flash_GPIO();
- + #endif
- + 	
- + #ifdef CONFIG_ALL_PLL
- + 	pll_init();
- + #endif
- + 
- + 	gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
- + 
- + 	return 0;
- + }
- + 
- diff -crN u-boot-2012.10_o/arch/arm/cpu/armv7/ckb_3352/clock.c u-boot-2012.10/arch/arm/cpu/armv7/ckb_3352/clock.c
- *** u-boot-2012.10_o/arch/arm/cpu/armv7/ckb_3352/clock.c	1970-01-01 09:00:00.000000000 +0900
- --- u-boot-2012.10/arch/arm/cpu/armv7/ckb_3352/clock.c	2014-02-27 11:33:16.720633268 +0900
- ***************
- *** 0 ****
- --- 1,389 ----
- + /*
- +  * clock.c
- +  *
- +  * clocks for CKB-3352 board
- +  *
- +  * Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation; either version 2 of
- +  * the License, or (at your option) any later version.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #include <common.h>
- + #include <asm/arch/cpu.h>
- + #include <asm/arch/clock.h>
- + #include <asm/arch/hardware.h>
- + #include <asm/io.h>
- + 
- + #define PRCM_MOD_EN		0x2
- + #define PRCM_FORCE_WAKEUP	0x2
- + #define PRCM_FUNCTL		0x0
- + 
- + #define PRCM_EMIF_CLK_ACTIVITY	BIT(2)
- + #define PRCM_L3_GCLK_ACTIVITY	BIT(4)
- + 
- + #define PLL_BYPASS_MODE		0x4
- + #define ST_MN_BYPASS		0x00000100
- + #define ST_DPLL_CLK		0x00000001
- + #define CLK_SEL_MASK		0x7ffff
- + #define CLK_DIV_MASK		0x1f
- + #define CLK_DIV2_MASK		0x7f
- + #define CLK_SEL_SHIFT		0x8
- + #define CLK_MODE_SEL		0x7
- + #define CLK_MODE_MASK		0xfffffff8
- + #define CLK_DIV_SEL		0xFFFFFFE0
- + #define CPGMAC0_IDLE		0x30000
- + #define DPLL_CLKDCOLDO_GATE_CTRL        0x300
- + 
- + const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
- + const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
- + const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
- + const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC;
- + 
- + #ifdef CONFIG_ALL_PLL
- + static void enable_interface_clocks(void)
- + {
- + 	/* Enable all the Interconnect Modules */
- + 	writel(PRCM_MOD_EN, &cmper->l3clkctrl);
- + 	while (readl(&cmper->l3clkctrl) != PRCM_MOD_EN)
- + 		;
- + 
- + 	writel(PRCM_MOD_EN, &cmper->l4lsclkctrl);
- + 	while (readl(&cmper->l4lsclkctrl) != PRCM_MOD_EN)
- + 		;
- + 
- + 	writel(PRCM_MOD_EN, &cmper->l4fwclkctrl);
- + 	while (readl(&cmper->l4fwclkctrl) != PRCM_MOD_EN)
- + 		;
- + 
- + 	writel(PRCM_MOD_EN, &cmwkup->wkl4wkclkctrl);
- + 	while (readl(&cmwkup->wkl4wkclkctrl) != PRCM_MOD_EN)
- + 		;
- + 
- + 	writel(PRCM_MOD_EN, &cmper->l3instrclkctrl);
- + 	while (readl(&cmper->l3instrclkctrl) != PRCM_MOD_EN)
- + 		;
- + 
- + 	writel(PRCM_MOD_EN, &cmper->l4hsclkctrl);
- + 	while (readl(&cmper->l4hsclkctrl) != PRCM_MOD_EN)
- + 		;
- + 
- + 	writel(PRCM_MOD_EN, &cmwkup->wkgpio0clkctrl);
- + 	while (readl(&cmwkup->wkgpio0clkctrl) != PRCM_MOD_EN)
- + 		;
- + }
- + 
- + /*
- +  * Force power domain wake up transition
- +  * Ensure that the corresponding interface clock is active before
- +  * using the peripheral
- +  */
- + static void power_domain_wkup_transition(void)
- + {
- + 	writel(PRCM_FORCE_WAKEUP, &cmper->l3clkstctrl);
- + 	writel(PRCM_FORCE_WAKEUP, &cmper->l4lsclkstctrl);
- + 	writel(PRCM_FORCE_WAKEUP, &cmwkup->wkclkstctrl);
- + 	writel(PRCM_FORCE_WAKEUP, &cmper->l4fwclkstctrl);
- + 	writel(PRCM_FORCE_WAKEUP, &cmper->l3sclkstctrl);
- + }
- + 
- + /*
- +  * Enable the peripheral clock for required peripherals
- +  */
- + static void enable_per_clocks(void)
- + {
- + 	/* Enable the control module though RBL would have done it*/
- + 	writel(PRCM_MOD_EN, &cmwkup->wkctrlclkctrl);
- + 	while (readl(&cmwkup->wkctrlclkctrl) != PRCM_MOD_EN)
- + 		;
- + 
- + 	/* Enable the module clock */
- + 	writel(PRCM_MOD_EN, &cmper->timer2clkctrl);
- + 	while (readl(&cmper->timer2clkctrl) != PRCM_MOD_EN)
- + 		;
- + 
- + 	/* Select the Master osc 24 MHZ as Timer2 clock source */
- + 	writel(0x1, &cmdpll->clktimer2clk);
- + 
- + 	/* UART0 */
- + 	writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl);
- + 	while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
- + 		;
- + 
- + 	/* GPMC */
- + 	writel(PRCM_MOD_EN, &cmper->gpmcclkctrl);
- + 	while (readl(&cmper->gpmcclkctrl) != PRCM_MOD_EN)
- + 		;
- + 
- + 	/* ELM */
- + 	writel(PRCM_MOD_EN, &cmper->elmclkctrl);
- + 	while (readl(&cmper->elmclkctrl) != PRCM_MOD_EN)
- + 		;
- + 
- + 	/* MMC0*/
- + 	writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
- + 	while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
- + 		;
- + 
- + 	/* i2c0 */
- + 	writel(PRCM_MOD_EN, &cmwkup->wkup_i2c0ctrl);
- + 	while (readl(&cmwkup->wkup_i2c0ctrl) != PRCM_MOD_EN)
- + 		;
- + 
- + 	/* gpio1 module */
- + 	writel(PRCM_MOD_EN, &cmper->gpio1clkctrl);
- + 	while (readl(&cmper->gpio1clkctrl) != PRCM_MOD_EN)
- + 		;
- + 
- + 	/* gpio2 module */
- + 	writel(PRCM_MOD_EN, &cmper->gpio2clkctrl);
- + 	while (readl(&cmper->gpio2clkctrl) != PRCM_MOD_EN)
- + 		;
- + 
- + 	/* gpio3 module */
- + 	writel(PRCM_MOD_EN, &cmper->gpio3clkctrl);
- + 	while (readl(&cmper->gpio3clkctrl) != PRCM_MOD_EN)
- + 		;
- + 
- + 	/* i2c1 */
- + 	writel(PRCM_MOD_EN, &cmper->i2c1clkctrl);
- + 	while (readl(&cmper->i2c1clkctrl) != PRCM_MOD_EN)
- + 		;
- + 
- + 	/* Ethernet */
- + 	writel(PRCM_MOD_EN, &cmper->cpgmac0clkctrl);
- + 	while ((readl(&cmper->cpgmac0clkctrl) & CPGMAC0_IDLE) != PRCM_FUNCTL)
- + 		;
- + 
- + 	/* spi0 */
- + 	writel(PRCM_MOD_EN, &cmper->spi0clkctrl);
- + 	while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN)
- + 		;
- + 
- + 	/* MUSB */
- + 	writel(PRCM_MOD_EN, &cmper->usb0clkctrl);
- + 	while (readl(&cmper->usb0clkctrl) != PRCM_MOD_EN)
- + 		;
- + 
- + 	/* RTC */
- + 	writel(PRCM_MOD_EN, &cmrtc->rtcclkctrl);
- + 	while (readl(&cmrtc->rtcclkctrl) != PRCM_MOD_EN)
- + 		;
- + }
- + 
- + void mpu_pll_config(int mpupll_M)
- + {
- + 	u32 clkmode, clksel, div_m2;
- + 
- + 	clkmode = readl(&cmwkup->clkmoddpllmpu);
- + 	clksel = readl(&cmwkup->clkseldpllmpu);
- + 	div_m2 = readl(&cmwkup->divm2dpllmpu);
- + 
- + 	/* Set the PLL to bypass Mode */
- + 	writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllmpu);
- + 	while (readl(&cmwkup->idlestdpllmpu) != ST_MN_BYPASS)
- + 		;
- + 
- + 	clksel = clksel & (~CLK_SEL_MASK);
- + 	clksel = clksel | ((mpupll_M << CLK_SEL_SHIFT) | MPUPLL_N);
- + 	writel(clksel, &cmwkup->clkseldpllmpu);
- + 
- + 	div_m2 = div_m2 & ~CLK_DIV_MASK;
- + 	div_m2 = div_m2 | MPUPLL_M2;
- + 	writel(div_m2, &cmwkup->divm2dpllmpu);
- + 
- + 	clkmode = clkmode | CLK_MODE_SEL;
- + 	writel(clkmode, &cmwkup->clkmoddpllmpu);
- + 
- + 	while (readl(&cmwkup->idlestdpllmpu) != ST_DPLL_CLK)
- + 		;
- + }
- + 
- + static void core_pll_config(void)
- + {
- + 	u32 clkmode, clksel, div_m4, div_m5, div_m6;
- + 
- + 	clkmode = readl(&cmwkup->clkmoddpllcore);
- + 	clksel = readl(&cmwkup->clkseldpllcore);
- + 	div_m4 = readl(&cmwkup->divm4dpllcore);
- + 	div_m5 = readl(&cmwkup->divm5dpllcore);
- + 	div_m6 = readl(&cmwkup->divm6dpllcore);
- + 
- + 	/* Set the PLL to bypass Mode */
- + 	writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllcore);
- + 
- + 	while (readl(&cmwkup->idlestdpllcore) != ST_MN_BYPASS)
- + 		;
- + 
- + 	clksel = clksel & (~CLK_SEL_MASK);
- + 	clksel = clksel | ((COREPLL_M << CLK_SEL_SHIFT) | COREPLL_N);
- + 	writel(clksel, &cmwkup->clkseldpllcore);
- + 
- + 	div_m4 = div_m4 & ~CLK_DIV_MASK;
- + 	div_m4 = div_m4 | COREPLL_M4;
- + 	writel(div_m4, &cmwkup->divm4dpllcore);
- + 
- + 	div_m5 = div_m5 & ~CLK_DIV_MASK;
- + 	div_m5 = div_m5 | COREPLL_M5;
- + 	writel(div_m5, &cmwkup->divm5dpllcore);
- + 
- + 	div_m6 = div_m6 & ~CLK_DIV_MASK;
- + 	div_m6 = div_m6 | COREPLL_M6;
- + 	writel(div_m6, &cmwkup->divm6dpllcore);
- + 
- + 	clkmode = clkmode | CLK_MODE_SEL;
- + 	writel(clkmode, &cmwkup->clkmoddpllcore);
- + 
- + 	while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK)
- + 		;
- + }
- + 
- + static void per_pll_config(void)
- + {
- + 	u32 clkmode, clksel, div_m2;
- + 
- + 	clkmode = readl(&cmwkup->clkmoddpllper);
- + 	clksel = readl(&cmwkup->clkseldpllper);
- + 	div_m2 = readl(&cmwkup->divm2dpllper);
- + 
- + 	/* Set the PLL to bypass Mode */
- + 	writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllper);
- + 
- + 	while (readl(&cmwkup->idlestdpllper) != ST_MN_BYPASS)
- + 		;
- + 
- + 	clksel = clksel & (~CLK_SEL_MASK);
- + 	clksel = clksel | ((PERPLL_M << CLK_SEL_SHIFT) | PERPLL_N);
- + 	writel(clksel, &cmwkup->clkseldpllper);
- + 
- + 	div_m2 = div_m2 & ~CLK_DIV2_MASK;
- + 	div_m2 = div_m2 | PERPLL_M2;
- + 	writel(div_m2, &cmwkup->divm2dpllper);
- + 
- + 	clkmode = clkmode | CLK_MODE_SEL;
- + 	writel(clkmode, &cmwkup->clkmoddpllper);
- + 
- + 	while (readl(&cmwkup->idlestdpllper) != ST_DPLL_CLK)
- + 		;
- + 
- + 	writel(DPLL_CLKDCOLDO_GATE_CTRL, &cmwkup->clkdcoldodpllper);
- + }
- + 
- + void ddr_pll_config(unsigned int ddrpll_m)
- + {
- + 	u32 clkmode, clksel, div_m2;
- + 
- + 	clkmode = readl(&cmwkup->clkmoddpllddr);
- + 	clksel = readl(&cmwkup->clkseldpllddr);
- + 	div_m2 = readl(&cmwkup->divm2dpllddr);
- + 
- + 	/* Set the PLL to bypass Mode */
- + 	clkmode = (clkmode & CLK_MODE_MASK) | PLL_BYPASS_MODE;
- + 	writel(clkmode, &cmwkup->clkmoddpllddr);
- + 
- + 	/* Wait till bypass mode is enabled */
- + 	while ((readl(&cmwkup->idlestdpllddr) & ST_MN_BYPASS)
- + 				!= ST_MN_BYPASS)
- + 		;
- + 
- + 	clksel = clksel & (~CLK_SEL_MASK);
- + 	clksel = clksel | ((ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N);
- + 	writel(clksel, &cmwkup->clkseldpllddr);
- + 
- + 	div_m2 = div_m2 & CLK_DIV_SEL;
- + 	div_m2 = div_m2 | DDRPLL_M2;
- + 	writel(div_m2, &cmwkup->divm2dpllddr);
- + 
- + 	clkmode = (clkmode & CLK_MODE_MASK) | CLK_MODE_SEL;
- + 	writel(clkmode, &cmwkup->clkmoddpllddr);
- + 
- + 	/* Wait till dpll is locked */
- + 	while ((readl(&cmwkup->idlestdpllddr) & ST_DPLL_CLK) != ST_DPLL_CLK)
- + 		;
- + }
- + 
- + void enable_emif_clocks(void)
- + {
- + 	/* Enable the  EMIF_FW Functional clock */
- + 	writel(PRCM_MOD_EN, &cmper->emiffwclkctrl);
- + 	/* Enable EMIF0 Clock */
- + 	writel(PRCM_MOD_EN, &cmper->emifclkctrl);
- + 	/* Poll if module is functional */
- + 	while ((readl(&cmper->emifclkctrl)) != PRCM_MOD_EN)
- + 		;
- + }
- + 
- + /*
- +  * Configure the PLL/PRCM for necessary peripherals
- +  */
- + void pll_init()
- + {
- + 	/* Start at 550MHz, will be tweaked up if possible. */
- + 	mpu_pll_config(MPUPLL_M_550);
- + 	core_pll_config();
- + 	per_pll_config();
- + 
- + 	/* Enable the required interconnect clocks */
- + 	enable_interface_clocks();
- + 
- + 	/* Power domain wake up transition */
- + 	power_domain_wkup_transition();
- + 
- + 	/* Enable the required peripherals */
- + 	enable_per_clocks();
- + }
- + #endif
- + 
- + 
- + void enable_lcd_clock(void)
- + {
- + 	writel(PRCM_MOD_EN, &cmper->lcdclkctrl);
- + 	while (readl(&cmper->lcdclkctrl) != PRCM_MOD_EN)
- + 		;
- + }
- + 
- + 
- + void lcd_power_domain_wkup_transition()
- + {
- + 	writel(PRCM_FORCE_WAKEUP, &cmper->lcdclkstctrl);
- + }
- + 
- + void disp_pll_config()
- + {
- + 	volatile u32 clkmode, clksel, div_m2;
- + 
- + 	clkmode = readl(&cmwkup->clkmoddplldisp);
- + 	clksel = readl(&cmwkup->clkseldplldisp);
- + 	div_m2 = readl(&cmwkup->divm2dplldisp);
- + 
- + 	/* Set the PLL to bypass Mode */
- + 	writel(PLL_BYPASS_MODE, &cmwkup->clkmoddplldisp);
- + 	while (readl(&cmwkup->idlestdplldisp) != ST_MN_BYPASS)
- + 		;
- + 
- + 	clksel = clksel & (~CLK_SEL_MASK);
- + 	clksel = clksel | ((DISPPLL_M << CLK_SEL_SHIFT) | DISPPLL_N);
- + 	writel(clksel, &cmwkup->clkseldplldisp);
- + 
- + 	div_m2 = div_m2 & ~CLK_DIV_MASK;
- + 	div_m2 = div_m2 | DISPPLL_M2;
- + 	writel(div_m2, &cmwkup->divm2dplldisp);
- + 
- + 	clkmode = clkmode | CLK_MODE_SEL;
- + 	writel(clkmode, &cmwkup->clkmoddplldisp);
- + 
- + 	while (readl(&cmwkup->idlestdplldisp) != ST_DPLL_CLK)
- + 		;
- + 	
- + 	lcd_power_domain_wkup_transition();
- + 	
- + 	enable_lcd_clock();
- + 	
- + }
- diff -crN u-boot-2012.10_o/arch/arm/cpu/armv7/ckb_3352/config.mk u-boot-2012.10/arch/arm/cpu/armv7/ckb_3352/config.mk
- *** u-boot-2012.10_o/arch/arm/cpu/armv7/ckb_3352/config.mk	1970-01-01 09:00:00.000000000 +0900
- --- u-boot-2012.10/arch/arm/cpu/armv7/ckb_3352/config.mk	2014-02-27 11:33:16.731635581 +0900
- ***************
- *** 0 ****
- --- 1,19 ----
- + #
- + # Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
- + #
- + # This program is free software; you can redistribute it and/or
- + # modify it under the terms of the GNU General Public License as
- + # published by the Free Software Foundation; either version 2 of
- + # the License, or (at your option) any later version.
- + #
- + # This program is distributed "as is" WITHOUT ANY WARRANTY of any
- + # kind, whether express or implied; without even the implied warranty
- + # of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- + # GNU General Public License for more details.
- + #
- + ifdef CONFIG_SPL_BUILD
- + ALL-y	+= $(OBJTREE)/MLO
- + ALL-$(CONFIG_SPL_SPI_SUPPORT) += $(OBJTREE)/MLO.byteswap
- + else
- + ALL-y	+= $(obj)u-boot.img
- + endif
- diff -crN u-boot-2012.10_o/arch/arm/cpu/armv7/ckb_3352/ddr.c u-boot-2012.10/arch/arm/cpu/armv7/ckb_3352/ddr.c
- *** u-boot-2012.10_o/arch/arm/cpu/armv7/ckb_3352/ddr.c	1970-01-01 09:00:00.000000000 +0900
- --- u-boot-2012.10/arch/arm/cpu/armv7/ckb_3352/ddr.c	2014-02-27 11:33:16.731635581 +0900
- ***************
- *** 0 ****
- --- 1,119 ----
- + /*
- +  * DDR Configuration for CKB-3352.
- +  *
- +  * Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation; either version 2 of
- +  * the License, or (at your option) any later version.
- +  *
- +  * This program is distributed .as is. WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #include <asm/arch/cpu.h>
- + #include <asm/arch/ddr_defs.h>
- + #include <asm/arch/sys_proto.h>
- + #include <asm/io.h>
- + #include <asm/emif.h>
- + 
- + 
- + /**
- +  * Base address for EMIF instances
- +  */
- + static struct emif_reg_struct *emif_reg = {
- + 				(struct emif_reg_struct *)EMIF4_0_CFG_BASE};
- + 
- + /**
- +  * Base address for DDR instance
- +  */
- + static struct ddr_regs *ddr_reg[2] = {
- + 				(struct ddr_regs *)DDR_PHY_BASE_ADDR,
- + 				(struct ddr_regs *)DDR_PHY_BASE_ADDR2};
- + 
- + /**
- +  * Base address for ddr io control instances
- +  */
- + static struct ddr_cmdtctrl *ioctrl_reg = {
- + 			(struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
- + 
- + /**
- +  * Configure SDRAM
- +  */
- + void config_sdram(const struct emif_regs *regs)
- + {
- + 	writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl);
- + 	writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw);
- + 	if (regs->zq_config){
- + 		writel(regs->zq_config, &emif_reg->emif_zq_config);
- + 		writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
- + 	}
- + 	writel(regs->sdram_config, &emif_reg->emif_sdram_config);
- + }
- + 
- + /**
- +  * Set SDRAM timings
- +  */
- + void set_sdram_timings(const struct emif_regs *regs)
- + {
- + 	writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1);
- + 	writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1_shdw);
- + 	writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2);
- + 	writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2_shdw);
- + 	writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3);
- + 	writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3_shdw);
- + }
- + 
- + /**
- +  * Configure DDR PHY
- +  */
- + void config_ddr_phy(const struct emif_regs *regs)
- + {
- + 	writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1);
- + 	writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1_shdw);
- + }
- + 
- + /**
- +  * Configure DDR CMD control registers
- +  */
- + void config_cmd_ctrl(const struct cmd_control *cmd)
- + {
- + 	writel(cmd->cmd0csratio, &ddr_reg[0]->cm0csratio);
- + 	writel(cmd->cmd0dldiff, &ddr_reg[0]->cm0dldiff);
- + 	writel(cmd->cmd0iclkout, &ddr_reg[0]->cm0iclkout);
- + 
- + 	writel(cmd->cmd1csratio, &ddr_reg[0]->cm1csratio);
- + 	writel(cmd->cmd1dldiff, &ddr_reg[0]->cm1dldiff);
- + 	writel(cmd->cmd1iclkout, &ddr_reg[0]->cm1iclkout);
- + 
- + 	writel(cmd->cmd2csratio, &ddr_reg[0]->cm2csratio);
- + 	writel(cmd->cmd2dldiff, &ddr_reg[0]->cm2dldiff);
- + 	writel(cmd->cmd2iclkout, &ddr_reg[0]->cm2iclkout);
- + }
- + 
- + /**
- +  * Configure DDR DATA registers
- +  */
- + void config_ddr_data(int macrono, const struct ddr_data *data)
- + {
- + 	writel(data->datardsratio0, &ddr_reg[macrono]->dt0rdsratio0);
- + 	writel(data->datawdsratio0, &ddr_reg[macrono]->dt0wdsratio0);
- + 	writel(data->datawiratio0, &ddr_reg[macrono]->dt0wiratio0);
- + 	writel(data->datagiratio0, &ddr_reg[macrono]->dt0giratio0);
- + 	writel(data->datafwsratio0, &ddr_reg[macrono]->dt0fwsratio0);
- + 	writel(data->datawrsratio0, &ddr_reg[macrono]->dt0wrsratio0);
- + 	writel(data->datauserank0delay, &ddr_reg[macrono]->dt0rdelays0);
- + 	writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0);
- + }
- + 
- + void config_io_ctrl(unsigned long val)
- + {
- + 	writel(val, &ioctrl_reg->cm0ioctl);
- + 	writel(val, &ioctrl_reg->cm1ioctl);
- + 	writel(val, &ioctrl_reg->cm2ioctl);
- + 	writel(val, &ioctrl_reg->dt0ioctl);
- + 	writel(val, &ioctrl_reg->dt1ioctl);
- + }
- diff -crN u-boot-2012.10_o/arch/arm/cpu/armv7/ckb_3352/emif4.c u-boot-2012.10/arch/arm/cpu/armv7/ckb_3352/emif4.c
- *** u-boot-2012.10_o/arch/arm/cpu/armv7/ckb_3352/emif4.c	1970-01-01 09:00:00.000000000 +0900
- --- u-boot-2012.10/arch/arm/cpu/armv7/ckb_3352/emif4.c	2014-02-27 11:33:16.731635581 +0900
- ***************
- *** 0 ****
- --- 1,44 ----
- + /*
- +  * emif4.c
- +  *
- +  * CKB-3352 emif4 configuration file
- +  *
- +  * Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation; either version 2 of
- +  * the License, or (at your option) any later version.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #include <common.h>
- + #include <asm/arch/cpu.h>
- + #include <asm/arch/ddr_defs.h>
- + #include <asm/arch/hardware.h>
- + #include <asm/arch/clock.h>
- + #include <asm/arch/sys_proto.h>
- + #include <asm/io.h>
- + #include <asm/emif.h>
- + 
- + DECLARE_GLOBAL_DATA_PTR;
- + 
- + int dram_init(void)
- + {
- + 	/* dram_init must store complete ramsize in gd->ram_size */
- + 	gd->ram_size = get_ram_size(
- + 			(void *)CONFIG_SYS_SDRAM_BASE,
- + 			CONFIG_MAX_RAM_BANK_SIZE);
- + 	return 0;
- + }
- + 
- + void dram_init_banksize(void)
- + {
- + 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- + 	gd->bd->bi_dram[0].size = gd->ram_size;
- + }
- + 
- diff -crN u-boot-2012.10_o/arch/arm/cpu/armv7/ckb_3352/Makefile u-boot-2012.10/arch/arm/cpu/armv7/ckb_3352/Makefile
- *** u-boot-2012.10_o/arch/arm/cpu/armv7/ckb_3352/Makefile	1970-01-01 09:00:00.000000000 +0900
- --- u-boot-2012.10/arch/arm/cpu/armv7/ckb_3352/Makefile	2014-03-07 11:21:15.608250000 +0900
- ***************
- *** 0 ****
- --- 1,47 ----
- + #
- + # Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
- + #
- + # This program is free software; you can redistribute it and/or
- + # modify it under the terms of the GNU General Public License as
- + # published by the Free Software Foundation; either version 2 of
- + # the License, or (at your option) any later version.
- + #
- + # This program is distributed "as is" WITHOUT ANY WARRANTY of any
- + # kind, whether express or implied; without even the implied warranty
- + # of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- + # GNU General Public License for more details.
- + #
- + 
- + include $(TOPDIR)/config.mk
- + 
- + LIB	= $(obj)lib$(SOC).o
- + 
- + COBJS	+= clock.o
- + COBJS	+= sys_info.o
- + COBJS	+= ddr.o
- + COBJS	+= emif4.o
- + COBJS	+= ckb_3352.o
- + 
- + 
- + SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
- + OBJS	:= $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
- + 
- + all:	$(obj).depend $(LIB)
- + 
- + $(LIB):	$(OBJS)
- + 	$(call cmd_link_o_target, $(OBJS))
- + 
- + clean:
- + 	rm -f $(SOBJS) $(OBJS)
- + 
- + distclean:	clean
- + 	rm -f $(LIB) core *.bak .depend
- + 
- + #########################################################################
- + 
- + # defines $(obj).depend target
- + include $(SRCTREE)/rules.mk
- + 
- + sinclude $(obj).depend
- + 
- + #########################################################################
- diff -crN u-boot-2012.10_o/arch/arm/cpu/armv7/ckb_3352/sys_info.c u-boot-2012.10/arch/arm/cpu/armv7/ckb_3352/sys_info.c
- *** u-boot-2012.10_o/arch/arm/cpu/armv7/ckb_3352/sys_info.c	1970-01-01 09:00:00.000000000 +0900
- --- u-boot-2012.10/arch/arm/cpu/armv7/ckb_3352/sys_info.c	2014-02-27 11:33:16.753647295 +0900
- ***************
- *** 0 ****
- --- 1,130 ----
- + /*
- +  * sys_info.c
- +  *
- +  * System information functions
- +  *
- +  * Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
- +  *
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation; either version 2 of
- +  * the License, or (at your option) any later version.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #include <common.h>
- + #include <asm/io.h>
- + #include <asm/arch/sys_proto.h>
- + #include <asm/arch/cpu.h>
- + #include <asm/arch/clock.h>
- + 
- + struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
- + 
- + /**
- +  * get_cpu_rev(void) - extract rev info
- +  */
- + u32 get_cpu_rev(void)
- + {
- + 	u32 id;
- + 	u32 rev;
- + 
- + 	id = readl(DEVICE_ID);
- + 	rev = (id >> 28) & 0xff;
- + 
- + 	return rev;
- + }
- + 
- + /**
- +  * get_cpu_type(void) - extract cpu info
- +  */
- + u32 get_cpu_type(void)
- + {
- + 	u32 id = 0;
- + 	u32 partnum;
- + 
- + 	id = readl(DEVICE_ID);
- + 	partnum = (id >> 12) & 0xffff;
- + 
- + 	return partnum;
- + }
- + 
- + /**
- +  * get_board_rev() - setup to pass kernel board revision information
- +  * returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
- +  */
- + u32 get_board_rev(void)
- + {
- + 	return BOARD_REV_ID;
- + }
- + 
- + /**
- +  * get_device_type(): tell if GP/HS/EMU/TST
- +  */
- + u32 get_device_type(void)
- + {
- + 	int mode;
- + 	mode = readl(&cstat->statusreg) & (DEVICE_MASK);
- + 	return mode >>= 8;
- + }
- + 
- + /**
- +  * get_sysboot_value(void) - return SYS_BOOT[4:0]
- +  */
- + u32 get_sysboot_value(void)
- + {
- + 	int mode;
- + 	mode = readl(&cstat->statusreg) & (SYSBOOT_MASK);
- + 	return mode;
- + }
- + 
- + #ifdef CONFIG_DISPLAY_CPUINFO
- + /**
- +  * Print CPU information
- +  */
- + int print_cpuinfo(void)
- + {
- + 	char *cpu_s, *sec_s;
- + 	int arm_freq, ddr_freq;
- + 
- + 	switch (get_cpu_type()) {
- + 	case AM335X:
- + 		cpu_s = "AM335X";
- + 		break;
- + 	default:
- + 		cpu_s = "Unknown cpu type";
- + 		break;
- + 	}
- + 
- + 	switch (get_device_type()) {
- + 	case TST_DEVICE:
- + 		sec_s = "TST";
- + 		break;
- + 	case EMU_DEVICE:
- + 		sec_s = "EMU";
- + 		break;
- + 	case HS_DEVICE:
- + 		sec_s = "HS";
- + 		break;
- + 	case GP_DEVICE:
- + 		sec_s = "GP";
- + 		break;
- + 	default:
- + 		sec_s = "?";
- + 	}
- + 
- + 	printf("AM%s-%s rev %d\n",
- + 			cpu_s, sec_s, get_cpu_rev());
- + 
- + 	/* TODO: Print ARM and DDR frequencies  */
- + 
- + 	return 0;
- + }
- + 
- + 
- + #endif	/* CONFIG_DISPLAY_CPUINFO */
- + 
- diff -crN u-boot-2012.10_o/arch/arm/cpu/armv7/start.S u-boot-2012.10/arch/arm/cpu/armv7/start.S
- *** u-boot-2012.10_o/arch/arm/cpu/armv7/start.S	2012-10-16 00:14:08.000000000 +0900
- --- u-boot-2012.10/arch/arm/cpu/armv7/start.S	2014-02-27 11:33:16.763632368 +0900
- ***************
- *** 102,107 ****
- --- 102,118 ----
-   _end_ofs:
-   	.word _end - _start
-   
- + #ifdef CONFIG_MACH_CKB_3352
- + .globl _loader_executed_uboot
- + _loader_executed_uboot:
- +  	.word 0		/* initialize to 0, if Uboot was loaded and executed by "loader",
- + 	 			    this will be set to 1 by "loader" */
- + .globl _approx_uboot_len
- + _approx_uboot_len:
- + 	.word 0		/* filled later */
- + #endif
- + 
- + 
-   #ifdef CONFIG_USE_IRQ
-   /* IRQ stack memory (calculated at run-time) */
-   .globl IRQ_STACK_START
- ***************
- *** 159,164 ****
- --- 170,197 ----
-   call_board_init_f:
-   	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
-   	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
- + #ifdef CONFIG_MACH_CKB_3352
- + 	ldr	r0, _loader_executed_uboot
- + 	cmp r0, #0
- + 	bne _execute_uboot					/* loader executed u-Boot */
- + 	/* copy Uboot code to temp memory in RAM */
- + 	adr	r0, _start						/* r0 <- Current Start address */
- + 	mov r1, #(UBOOT_TEMP_ADDR & 0xFF000000)	/* r1 <- temp address */
- + 	add r1, r1, #(UBOOT_TEMP_ADDR & 0x00FF0000)
- + 	add r1, r1, #(UBOOT_TEMP_ADDR & 0x0000FF00)
- + 	add r1, r1, #(UBOOT_TEMP_ADDR & 0x000000FF)
- + 	ldr	r2, _end_ofs					/* exact length of U-Boot */
- + 	adr r3, _approx_uboot_len
- +  	str r2, [r3]
- + 	add r2, r2, r0						/* r2 <- end address */
- + _copy_uboot_code:
- + 	ldmia r0!, {r3-r12}
- + 	stmia r1!, {r3-r12}
- + 	cmp r0, r2
- + 	ble _copy_uboot_code
- + _execute_uboot:
- + #endif
- + 
-   	ldr	r0,=0x00000000
-   	bl	board_init_f
-   
- ***************
- *** 184,190 ****
- --- 217,227 ----
-   	adr	r0, _start
-   	cmp	r0, r6
-   	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
- + #ifdef CONFIG_NO_RELOCATE_UBOOT
- + 	beq	copy_dyn		/* skip code relocation, branch to dynamic section copy */
- + #else
-   	beq	clear_bss		/* skip relocation */
- + #endif
-   	mov	r1, r6			/* r1 <- scratch for copy_loop */
-   	ldr	r3, _image_copy_end_ofs
-   	add	r2, r0, r3		/* r2 <- source end address	    */
- ***************
- *** 195,200 ****
- --- 232,238 ----
-   	cmp	r0, r2			/* until source end address [r2]    */
-   	blo	copy_loop
-   
- + copy_dyn:
-   	/*
-   	 * fix .rel.dyn relocations
-   	 */
- diff -crN u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/clock.h u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/clock.h
- *** u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/clock.h	1970-01-01 09:00:00.000000000 +0900
- --- u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/clock.h	2014-02-27 11:33:16.763632368 +0900
- ***************
- *** 0 ****
- --- 1,24 ----
- + /*
- +  * clock.h
- +  *
- +  * clock header
- +  *
- +  * Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation; either version 2 of
- +  * the License, or (at your option) any later version.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #ifndef _CLOCKS_H_
- + #define _CLOCKS_H_
- + 
- + #include <asm/arch/clocks_am33xx.h>
- + 
- + #endif
- diff -crN u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/clocks_am33xx.h u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/clocks_am33xx.h
- *** u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/clocks_am33xx.h	1970-01-01 09:00:00.000000000 +0900
- --- u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/clocks_am33xx.h	2014-02-27 11:33:16.763632368 +0900
- ***************
- *** 0 ****
- --- 1,62 ----
- + /*
- +  * clocks_am33xx.h
- +  *
- +  * AM33xx clock define
- +  *
- +  * Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation; either version 2 of
- +  * the License, or (at your option) any later version.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #ifndef _CLOCKS_AM33XX_H_
- + #define _CLOCKS_AM33XX_H_
- + 
- + #define OSC	(V_OSCK/1000000)
- + 
- + /* MAIN PLL Fdll = 550MHz, 720MHz or 800MHz */
- + #define MPUPLL_M_800	800
- + #define MPUPLL_M_720	720
- + #define MPUPLL_M_550	550
- + #define MPUPLL_N	(OSC-1)
- + #define MPUPLL_M2	1
- + 
- + /* Core PLL Fdll = 1 GHZ, */
- + #define COREPLL_M	1000
- + #define COREPLL_N	(OSC-1)
- + 
- + #define COREPLL_M4	10	/* CORE_CLKOUTM4 = 200 MHZ */
- + #define COREPLL_M5	8	/* CORE_CLKOUTM5 = 250 MHZ */
- + #define COREPLL_M6	4	/* CORE_CLKOUTM6 = 500 MHZ */
- + 
- + /*
- +  * USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll
- +  * frequency needs to be set to 960 MHZ. Hence,
- +  * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
- +  */
- + #define PERPLL_M	960
- + #define PERPLL_N	(OSC-1)
- + #define PERPLL_M2	5
- + 
- + /* DDR Freq is 266 MHZ for now */
- + /* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
- + #define DDRPLL_M	266
- + #define DDRPLL_N	(OSC-1)
- + #define DDRPLL_M2	1
- + 
- + /* DISP Freq is 300 MHZ for now */
- + #define DISPPLL_M	300
- + #define DISPPLL_N	(OSC-1)
- + #define DISPPLL_M2	1
- + 
- + extern void pll_init(void);
- + extern void enable_emif_clocks(void);
- + 
- + #endif	/* endif _CLOCKS_AM33XX_H_ */
- diff -crN u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/cpu.h u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/cpu.h
- *** u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/cpu.h	1970-01-01 09:00:00.000000000 +0900
- --- u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/cpu.h	2014-02-27 11:33:16.767558729 +0900
- ***************
- *** 0 ****
- --- 1,352 ----
- + /*
- +  * cpu.h
- +  *
- +  * CKB-3352 specific header file
- +  *
- +  * Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation; either version 2 of
- +  * the License, or (at your option) any later version.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #ifndef _AM33XX_CPU_H
- + #define _AM33XX_CPU_H
- + 
- + #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
- + #include <asm/types.h>
- + #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
- + 
- + #include <asm/arch/hardware.h>
- + 
- + #define BIT(x)				(1 << x)
- + #define CL_BIT(x)			(0 << x)
- + 
- + /* Timer register bits */
- + #define TCLR_ST				BIT(0)	/* Start=1 Stop=0 */
- + #define TCLR_AR				BIT(1)	/* Auto reload */
- + #define TCLR_PRE			BIT(5)	/* Pre-scaler enable */
- + #define TCLR_PTV_SHIFT			(2)	/* Pre-scaler shift value */
- + #define TCLR_PRE_DISABLE		CL_BIT(5) /* Pre-scalar disable */
- + 
- + /* device type */
- + #define DEVICE_MASK			(BIT(8) | BIT(9) | BIT(10))
- + #define TST_DEVICE			0x0
- + #define EMU_DEVICE			0x1
- + #define HS_DEVICE			0x2
- + #define GP_DEVICE			0x3
- + 
- + /* cpu-id for AM33XX family */
- + #define AM335X				0xB944
- + #define DEVICE_ID			0x44E10600
- + 
- + /* This gives the status of the boot mode pins on the evm */
- + #define SYSBOOT_MASK			(BIT(0) | BIT(1) | BIT(2)\
- + 					| BIT(3) | BIT(4))
- + 
- + /* Reset control */
- + #ifdef CONFIG_AM33XX
- + #define PRM_RSTCTRL			0x44E00F00
- + #define PRM_RSTST			0x44E00F08
- + #endif
- + #define PRM_RSTCTRL_RESET		0x01
- + #define PRM_RSTST_WARM_RESET_MASK	0x232
- + 
- + #ifndef __KERNEL_STRICT_NAMES
- + #ifndef __ASSEMBLY__
- + struct gpmc_cs {
- + 	u32 config1;		/* 0x00 */
- + 	u32 config2;		/* 0x04 */
- + 	u32 config3;		/* 0x08 */
- + 	u32 config4;		/* 0x0C */
- + 	u32 config5;		/* 0x10 */
- + 	u32 config6;		/* 0x14 */
- + 	u32 config7;		/* 0x18 */
- + 	u32 nand_cmd;		/* 0x1C */
- + 	u32 nand_adr;		/* 0x20 */
- + 	u32 nand_dat;		/* 0x24 */
- + 	u8 res[8];		/* blow up to 0x30 byte */
- + };
- + 
- + struct bch_res_0_3 {
- + 	u32 bch_result_x[4];
- + };
- + 
- + struct gpmc {
- + 	u8 res1[0x10];
- + 	u32 sysconfig;		/* 0x10 */
- + 	u8 res2[0x4];
- + 	u32 irqstatus;		/* 0x18 */
- + 	u32 irqenable;		/* 0x1C */
- + 	u8 res3[0x20];
- + 	u32 timeout_control;	/* 0x40 */
- + 	u8 res4[0xC];
- + 	u32 config;		/* 0x50 */
- + 	u32 status;		/* 0x54 */
- + 	u8 res5[0x8];		/* 0x58 */
- + 	struct gpmc_cs cs[8];	/* 0x60, 0x90, .. */
- + 	u8 res6[0x14];		/* 0x1E0 */
- + 	u32 ecc_config;		/* 0x1F4 */
- + 	u32 ecc_control;	/* 0x1F8 */
- + 	u32 ecc_size_config;	/* 0x1FC */
- + 	u32 ecc1_result;	/* 0x200 */
- + 	u32 ecc2_result;	/* 0x204 */
- + 	u32 ecc3_result;	/* 0x208 */
- + 	u32 ecc4_result;	/* 0x20C */
- + 	u32 ecc5_result;	/* 0x210 */
- + 	u32 ecc6_result;	/* 0x214 */
- + 	u32 ecc7_result;	/* 0x218 */
- + 	u32 ecc8_result;	/* 0x21C */
- + 	u32 ecc9_result;	/* 0x220 */
- + 	u8 res7[12];		/* 0x224 */
- + 	u32 testmomde_ctrl;	/* 0x230 */
- + 	u8 res8[12];		/* 0x234 */
- + 	struct bch_res_0_3 bch_result_0_3[2];	/* 0x240 */
- + };
- + 
- + /* Used for board specific gpmc initialization */
- + extern struct gpmc *gpmc_cfg;
- + 
- + /* Encapsulating core pll registers */
- + struct cm_wkuppll {
- + 	unsigned int wkclkstctrl;	/* offset 0x00 */
- + 	unsigned int wkctrlclkctrl;	/* offset 0x04 */
- + 	unsigned int wkgpio0clkctrl;	/* offset 0x08 */
- + 	unsigned int wkl4wkclkctrl;	/* offset 0x0c */
- + 	unsigned int resv2[4];
- + 	unsigned int idlestdpllmpu;	/* offset 0x20 */
- + 	unsigned int resv3[2];
- + 	unsigned int clkseldpllmpu;	/* offset 0x2c */
- + 	unsigned int resv4[1];
- + 	unsigned int idlestdpllddr;	/* offset 0x34 */
- + 	unsigned int resv5[2];
- + 	unsigned int clkseldpllddr;	/* offset 0x40 */
- + 	unsigned int autoidledplldisp;	/* offset 0x44 */
- + 	unsigned int idlestdplldisp;	/* offset 0x48 */
- + 	unsigned int resv6[2];
- + 	unsigned int clkseldplldisp;	/* offset 0x54 */
- + 	unsigned int resv7[1];
- + 	unsigned int idlestdpllcore;	/* offset 0x5c */
- + 	unsigned int resv8[2];
- + 	unsigned int clkseldpllcore;	/* offset 0x68 */
- + 	unsigned int resv9[1];
- + 	unsigned int idlestdpllper;	/* offset 0x70 */
- + 	unsigned int resv10[2];
- + 	unsigned int clkdcoldodpllper;	/* offset 0x7c */
- + 	unsigned int divm4dpllcore;	/* offset 0x80 */
- + 	unsigned int divm5dpllcore;	/* offset 0x84 */
- + 	unsigned int clkmoddpllmpu;	/* offset 0x88 */
- + 	unsigned int clkmoddpllper;	/* offset 0x8c */
- + 	unsigned int clkmoddpllcore;	/* offset 0x90 */
- + 	unsigned int clkmoddpllddr;	/* offset 0x94 */
- + 	unsigned int clkmoddplldisp;	/* offset 0x98 */
- + 	unsigned int clkseldpllper;	/* offset 0x9c */
- + 	unsigned int divm2dpllddr;	/* offset 0xA0 */
- + 	unsigned int divm2dplldisp;	/* offset 0xA4 */
- + 	unsigned int divm2dpllmpu;	/* offset 0xA8 */
- + 	unsigned int divm2dpllper;	/* offset 0xAC */
- + 	unsigned int resv11[1];
- + 	unsigned int wkup_uart0ctrl;	/* offset 0xB4 */
- + 	unsigned int wkup_i2c0ctrl;	/* offset 0xB8 */
- + 	unsigned int resv12[7];
- + 	unsigned int divm6dpllcore;	/* offset 0xD8 */
- + };
- + 
- + /**
- +  * Encapsulating peripheral functional clocks
- +  * pll registers
- +  */
- + struct cm_perpll {
- + 	unsigned int l4lsclkstctrl;	/* offset 0x00 */
- + 	unsigned int l3sclkstctrl;	/* offset 0x04 */
- + 	unsigned int l4fwclkstctrl;	/* offset 0x08 */
- + 	unsigned int l3clkstctrl;	/* offset 0x0c */
- + 	unsigned int resv1;
- + 	unsigned int cpgmac0clkctrl;	/* offset 0x14 */
- + 	unsigned int lcdclkctrl;	/* offset 0x18 */
- + 	unsigned int usb0clkctrl;	/* offset 0x1C */
- + 	unsigned int resv2;
- + 	unsigned int tptc0clkctrl;	/* offset 0x24 */
- + 	unsigned int emifclkctrl;	/* offset 0x28 */
- + 	unsigned int ocmcramclkctrl;	/* offset 0x2c */
- + 	unsigned int gpmcclkctrl;	/* offset 0x30 */
- + 	unsigned int mcasp0clkctrl;	/* offset 0x34 */
- + 	unsigned int uart5clkctrl;	/* offset 0x38 */
- + 	unsigned int mmc0clkctrl;	/* offset 0x3C */
- + 	unsigned int elmclkctrl;	/* offset 0x40 */
- + 	unsigned int i2c2clkctrl;	/* offset 0x44 */
- + 	unsigned int i2c1clkctrl;	/* offset 0x48 */
- + 	unsigned int spi0clkctrl;	/* offset 0x4C */
- + 	unsigned int spi1clkctrl;	/* offset 0x50 */
- + 	unsigned int resv3[3];
- + 	unsigned int l4lsclkctrl;	/* offset 0x60 */
- + 	unsigned int l4fwclkctrl;	/* offset 0x64 */
- + 	unsigned int mcasp1clkctrl;	/* offset 0x68 */
- + 	unsigned int uart1clkctrl;	/* offset 0x6C */
- + 	unsigned int uart2clkctrl;	/* offset 0x70 */
- + 	unsigned int uart3clkctrl;	/* offset 0x74 */
- + 	unsigned int uart4clkctrl;	/* offset 0x78 */
- + 	unsigned int timer7clkctrl;	/* offset 0x7C */
- + 	unsigned int timer2clkctrl;	/* offset 0x80 */
- + 	unsigned int timer3clkctrl;	/* offset 0x84 */
- + 	unsigned int timer4clkctrl;	/* offset 0x88 */
- + 	unsigned int resv4[8];
- + 	unsigned int gpio1clkctrl;	/* offset 0xAC */
- + 	unsigned int gpio2clkctrl;	/* offset 0xB0 */
- + 	unsigned int gpio3clkctrl;	/* offset 0xB4 */
- + 	unsigned int resv5;
- + 	unsigned int tpccclkctrl;	/* offset 0xBC */
- + 	unsigned int dcan0clkctrl;	/* offset 0xC0 */
- + 	unsigned int dcan1clkctrl;	/* offset 0xC4 */
- + 	unsigned int resv6[2];
- + 	unsigned int emiffwclkctrl;	/* offset 0xD0 */
- + 	unsigned int resv7[2];
- + 	unsigned int l3instrclkctrl;	/* offset 0xDC */
- + 	unsigned int l3clkctrl;		/* Offset 0xE0 */
- + 	unsigned int resv8[4];
- + 	unsigned int mmc1clkctrl;	/* offset 0xF4 */
- + 	unsigned int mmc2clkctrl;	/* offset 0xF8 */
- + 	unsigned int resv9[8];
- + 	unsigned int l4hsclkstctrl;	/* offset 0x11C */
- + 	unsigned int l4hsclkctrl;	/* offset 0x120 */
- + 	unsigned int resv10[8];
- + 	unsigned int cpswclkstctrl;	/* offset 0x144 */
- + 	unsigned int lcdclkstctrl;	/* offset 0x148 */
- + };
- + 
- + /* Encapsulating Display pll registers */
- + struct cm_dpll {
- + 	unsigned int resv1[2];
- + 	unsigned int clktimer2clk;	/* offset 0x08 */
- + 	unsigned int resv2[9];	
- + 	unsigned int clklcdcpixelclk;	/* offset 0x34 */
- + };
- + 
- + /* Control Module RTC registers */
- + struct cm_rtc {
- + 	unsigned int rtcclkctrl;	/* offset 0x0 */
- + 	unsigned int clkstctrl;		/* offset 0x4 */
- + };
- + 
- + /* Watchdog timer registers */
- + struct wd_timer {
- + 	unsigned int resv1[4];
- + 	unsigned int wdtwdsc;	/* offset 0x010 */
- + 	unsigned int wdtwdst;	/* offset 0x014 */
- + 	unsigned int wdtwisr;	/* offset 0x018 */
- + 	unsigned int wdtwier;	/* offset 0x01C */
- + 	unsigned int wdtwwer;	/* offset 0x020 */
- + 	unsigned int wdtwclr;	/* offset 0x024 */
- + 	unsigned int wdtwcrr;	/* offset 0x028 */
- + 	unsigned int wdtwldr;	/* offset 0x02C */
- + 	unsigned int wdtwtgr;	/* offset 0x030 */
- + 	unsigned int wdtwwps;	/* offset 0x034 */
- + 	unsigned int resv2[3];
- + 	unsigned int wdtwdly;	/* offset 0x044 */
- + 	unsigned int wdtwspr;	/* offset 0x048 */
- + 	unsigned int resv3[1];
- + 	unsigned int wdtwqeoi;	/* offset 0x050 */
- + 	unsigned int wdtwqstar;	/* offset 0x054 */
- + 	unsigned int wdtwqsta;	/* offset 0x058 */
- + 	unsigned int wdtwqens;	/* offset 0x05C */
- + 	unsigned int wdtwqenc;	/* offset 0x060 */
- + 	unsigned int resv4[39];
- + 	unsigned int wdt_unfr;	/* offset 0x100 */
- + };
- + 
- + /* Timer 32 bit registers */
- + struct gptimer {
- + 	unsigned int tidr;		/* offset 0x00 */
- + 	unsigned char res1[12];
- + 	unsigned int tiocp_cfg;		/* offset 0x10 */
- + 	unsigned char res2[12];
- + 	unsigned int tier;		/* offset 0x20 */
- + 	unsigned int tistatr;		/* offset 0x24 */
- + 	unsigned int tistat;		/* offset 0x28 */
- + 	unsigned int tisr;		/* offset 0x2c */
- + 	unsigned int tcicr;		/* offset 0x30 */
- + 	unsigned int twer;		/* offset 0x34 */
- + 	unsigned int tclr;		/* offset 0x38 */
- + 	unsigned int tcrr;		/* offset 0x3c */
- + 	unsigned int tldr;		/* offset 0x40 */
- + 	unsigned int ttgr;		/* offset 0x44 */
- + 	unsigned int twpc;		/* offset 0x48 */
- + 	unsigned int tmar;		/* offset 0x4c */
- + 	unsigned int tcar1;		/* offset 0x50 */
- + 	unsigned int tscir;		/* offset 0x54 */
- + 	unsigned int tcar2;		/* offset 0x58 */
- + };
- + 
- + /* RTC Registers */
- + struct rtc_regs {
- + 	unsigned int res[21];
- + 	unsigned int osc;		/* offset 0x54 */
- + 	unsigned int res2[5];
- + 	unsigned int kick0r;		/* offset 0x6c */
- + 	unsigned int kick1r;		/* offset 0x70 */
- + };
- + 
- + /* UART Registers */
- + struct uart_sys {
- + 	unsigned int resv1[21];
- + 	unsigned int uartsyscfg;	/* offset 0x54 */
- + 	unsigned int uartsyssts;	/* offset 0x58 */
- + };
- + 
- + /* VTP Registers */
- + struct vtp_reg {
- + 	unsigned int vtp0ctrlreg;
- + };
- + 
- + /* Control Status Register */
- + struct ctrl_stat {
- + 	unsigned int resv1[16];
- + 	unsigned int statusreg;		/* ofset 0x40 */
- + 	unsigned int resv2[51];
- + 	unsigned int secure_emif_sdram_config;	/* offset 0x0110 */
- + };
- + 
- + /* AM33XX GPIO registers */
- + #define OMAP_GPIO_REVISION		0x0000
- + #define OMAP_GPIO_SYSCONFIG		0x0010
- + #define OMAP_GPIO_SYSSTATUS		0x0114
- + #define OMAP_GPIO_IRQSTATUS1		0x002c
- + #define OMAP_GPIO_IRQSTATUS2		0x0030
- + #define OMAP_GPIO_CTRL			0x0130
- + #define OMAP_GPIO_OE			0x0134
- + #define OMAP_GPIO_DATAIN		0x0138
- + #define OMAP_GPIO_DATAOUT		0x013c
- + #define OMAP_GPIO_LEVELDETECT0		0x0140
- + #define OMAP_GPIO_LEVELDETECT1		0x0144
- + #define OMAP_GPIO_RISINGDETECT		0x0148
- + #define OMAP_GPIO_FALLINGDETECT		0x014c
- + #define OMAP_GPIO_DEBOUNCE_EN		0x0150
- + #define OMAP_GPIO_DEBOUNCE_VAL		0x0154
- + #define OMAP_GPIO_CLEARDATAOUT		0x0190
- + #define OMAP_GPIO_SETDATAOUT		0x0194
- + 
- + /* Control Device Register */
- + struct ctrl_dev {
- + 	unsigned int deviceid;		/* offset 0x00 */
- + 	unsigned int resv1[7];
- + 	unsigned int usb_ctrl0;		/* offset 0x20 */
- + 	unsigned int resv2;
- + 	unsigned int usb_ctrl1;		/* offset 0x28 */
- + 	unsigned int resv3;
- + 	unsigned int macid0l;		/* offset 0x30 */
- + 	unsigned int macid0h;		/* offset 0x34 */
- + 	unsigned int macid1l;		/* offset 0x38 */
- + 	unsigned int macid1h;		/* offset 0x3c */
- + 	unsigned int resv4[4];
- + 	unsigned int miisel;		/* offset 0x50 */
- + };
- + #endif /* __ASSEMBLY__ */
- + #endif /* __KERNEL_STRICT_NAMES */
- + 
- + #endif /* _AM33XX_CPU_H */
- diff -crN u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/ddr_defs.h u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/ddr_defs.h
- *** u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/ddr_defs.h	1970-01-01 09:00:00.000000000 +0900
- --- u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/ddr_defs.h	2014-02-27 11:33:16.767558729 +0900
- ***************
- *** 0 ****
- --- 1,202 ----
- + /*
- +  * ddr_defs.h
- +  *
- +  * ddr specific header
- +  *
- +  * Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation; either version 2 of
- +  * the License, or (at your option) any later version.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #ifndef _DDR_DEFS_H
- + #define _DDR_DEFS_H
- + 
- + #include <asm/arch/hardware.h>
- + #include <asm/emif.h>
- + 
- + /* AM335X EMIF Register values */
- + #define VTP_CTRL_READY		(0x1 << 5)
- + #define VTP_CTRL_ENABLE		(0x1 << 6)
- + #define VTP_CTRL_START_EN	(0x1)
- + #define PHY_DLL_LOCK_DIFF	0x0
- + #define DDR_CKE_CTRL_NORMAL	0x1
- + 
- + #define DDR2_EMIF_READ_LATENCY	0x100005	/* Enable Dynamic Power Down */
- + #define DDR2_EMIF_TIM1		0x0666B3C9
- + #define DDR2_EMIF_TIM2		0x243631CA
- + #define DDR2_EMIF_TIM3		0x0000033F
- + #define DDR2_EMIF_SDCFG		0x41805332
- + #define DDR2_EMIF_SDREF		0x0000081a
- + #define DDR2_DLL_LOCK_DIFF	0x0
- + #define DDR2_RATIO		0x80
- + #define DDR2_INVERT_CLKOUT	0x00
- + #define DDR2_RD_DQS		0x12
- + #define DDR2_WR_DQS		0x00
- + #define DDR2_PHY_WRLVL		0x00
- + #define DDR2_PHY_GATELVL	0x00
- + #define DDR2_PHY_WR_DATA	0x40
- + #define DDR2_PHY_FIFO_WE	0x80
- + #define DDR2_PHY_RANK0_DELAY	0x1
- + #define DDR2_IOCTRL_VALUE	0x18B
- + 
- + /* Micron MT41J128M16JT-125 */
- + #define DDR3_EMIF_READ_LATENCY	0x100006	/* Enable Dynamic Power Down */
- + #define DDR3_EMIF_TIM1		0x0888A39B
- + #define DDR3_EMIF_TIM2		0x26337FDA
- + #define DDR3_EMIF_TIM3		0x501F830F
- + #define DDR3_EMIF_SDCFG		0x61C04AB2
- + #define DDR3_EMIF_SDREF		0x0000093B
- + #define DDR3_ZQ_CFG		0x50074BE4
- + #define DDR3_DLL_LOCK_DIFF	0x1
- + #define DDR3_RATIO		0x40
- + #define DDR3_INVERT_CLKOUT	0x1
- + #define DDR3_RD_DQS		0x3B
- + #define DDR3_WR_DQS		0x85
- + #define DDR3_PHY_WR_DATA	0xC1
- + #define DDR3_PHY_FIFO_WE	0x100
- + #define DDR3_IOCTRL_VALUE	0x18B
- + 
- + /* Micron ???? on 1.5 and later EVMs */
- + #define DDR3_EMIF_TIM2_EVM	0x26517FDA
- + #define DDR3_EMIF_TIM3_EVM	0x501F851F
- + #define DDR3_RD_DQS_EVM		0x3A
- + #define DDR3_WR_DQS_EVM		0x0CD
- + #define DDR3_PHY_FIFO_WE_EVM	0x10B
- + #define DDR3_PHY_WR_DATA_EVM	0x106
- + 
- + /**
- +  * Configure SDRAM
- +  */
- + void config_sdram(const struct emif_regs *regs);
- + 
- + /**
- +  * Set SDRAM timings
- +  */
- + void set_sdram_timings(const struct emif_regs *regs);
- + 
- + /**
- +  * Configure DDR PHY
- +  */
- + void config_ddr_phy(const struct emif_regs *regs);
- + 
- + /**
- +  * This structure represents the DDR registers on AM33XX devices.
- +  * We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that
- +  * correspond to DATA1 registers defined here.
- +  */
- + struct ddr_regs {
- + 	unsigned int resv0[7];
- + 	unsigned int cm0csratio;	/* offset 0x01C */
- + 	unsigned int resv1[2];
- + 	unsigned int cm0dldiff;		/* offset 0x028 */
- + 	unsigned int cm0iclkout;	/* offset 0x02C */
- + 	unsigned int resv2[8];
- + 	unsigned int cm1csratio;	/* offset 0x050 */
- + 	unsigned int resv3[2];
- + 	unsigned int cm1dldiff;		/* offset 0x05C */
- + 	unsigned int cm1iclkout;	/* offset 0x060 */
- + 	unsigned int resv4[8];
- + 	unsigned int cm2csratio;	/* offset 0x084 */
- + 	unsigned int resv5[2];
- + 	unsigned int cm2dldiff;		/* offset 0x090 */
- + 	unsigned int cm2iclkout;	/* offset 0x094 */
- + 	unsigned int resv6[12];
- + 	unsigned int dt0rdsratio0;	/* offset 0x0C8 */
- + 	unsigned int resv7[4];
- + 	unsigned int dt0wdsratio0;	/* offset 0x0DC */
- + 	unsigned int resv8[4];
- + 	unsigned int dt0wiratio0;	/* offset 0x0F0 */
- + 	unsigned int resv9;
- + 	unsigned int dt0wimode0;	/* offset 0x0F8 */
- + 	unsigned int dt0giratio0;	/* offset 0x0FC */
- + 	unsigned int resv10;
- + 	unsigned int dt0gimode0;	/* offset 0x104 */
- + 	unsigned int dt0fwsratio0;	/* offset 0x108 */
- + 	unsigned int resv11[4];
- + 	unsigned int dt0dqoffset;	/* offset 0x11C */
- + 	unsigned int dt0wrsratio0;	/* offset 0x120 */
- + 	unsigned int resv12[4];
- + 	unsigned int dt0rdelays0;	/* offset 0x134 */
- + 	unsigned int dt0dldiff0;	/* offset 0x138 */
- + };
- + 
- + /**
- +  * Encapsulates DDR CMD control registers.
- +  */
- + struct cmd_control {
- + 	unsigned long cmd0csratio;
- + 	unsigned long cmd0csforce;
- + 	unsigned long cmd0csdelay;
- + 	unsigned long cmd0dldiff;
- + 	unsigned long cmd0iclkout;
- + 	unsigned long cmd1csratio;
- + 	unsigned long cmd1csforce;
- + 	unsigned long cmd1csdelay;
- + 	unsigned long cmd1dldiff;
- + 	unsigned long cmd1iclkout;
- + 	unsigned long cmd2csratio;
- + 	unsigned long cmd2csforce;
- + 	unsigned long cmd2csdelay;
- + 	unsigned long cmd2dldiff;
- + 	unsigned long cmd2iclkout;
- + };
- + 
- + /**
- +  * Encapsulates DDR DATA registers.
- +  */
- + struct ddr_data {
- + 	unsigned long datardsratio0;
- + 	unsigned long datawdsratio0;
- + 	unsigned long datawiratio0;
- + 	unsigned long datagiratio0;
- + 	unsigned long datafwsratio0;
- + 	unsigned long datawrsratio0;
- + 	unsigned long datauserank0delay;
- + 	unsigned long datadldiff0;
- + };
- + 
- + /**
- +  * Configure DDR CMD control registers
- +  */
- + void config_cmd_ctrl(const struct cmd_control *cmd);
- + 
- + /**
- +  * Configure DDR DATA registers
- +  */
- + void config_ddr_data(int data_macrono, const struct ddr_data *data);
- + 
- + /**
- +  * This structure represents the DDR io control on AM33XX devices.
- +  */
- + struct ddr_cmdtctrl {
- + 	unsigned int resv1[1];
- + 	unsigned int cm0ioctl;
- + 	unsigned int cm1ioctl;
- + 	unsigned int cm2ioctl;
- + 	unsigned int resv2[12];
- + 	unsigned int dt0ioctl;
- + 	unsigned int dt1ioctl;
- + };
- + 
- + /**
- +  * Configure DDR io control registers
- +  */
- + void config_io_ctrl(unsigned long val);
- + 
- + struct ddr_ctrl {
- + 	unsigned int ddrioctrl;
- + 	unsigned int resv1[325];
- + 	unsigned int ddrckectrl;
- + };
- + 
- + void config_ddr(short ddr_type);
- + 
- + #endif  /* _DDR_DEFS_H */
- diff -crN u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/elm.h u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/elm.h
- *** u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/elm.h	1970-01-01 09:00:00.000000000 +0900
- --- u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/elm.h	2014-02-27 11:33:16.767558729 +0900
- ***************
- *** 0 ****
- --- 1,93 ----
- + /*
- +  * (C) Copyright 2010-2011 Texas Instruments, <www.ti.com>
- +  * Mansoor Ahamed <mansoor.ahamed@ti.com>
- +  *
- +  * Derived from work done by Rohit Choraria <rohitkc@ti.com> for omap3
- +  *
- +  * See file CREDITS for list of people who contributed to this
- +  * project.
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation; either version 2 of
- +  * the License, or (at your option) any later version.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- +  * MA 02111-1307 USA
- +  */
- + #ifndef __ASM_ARCH_ELM_H
- + #define __ASM_ARCH_ELM_H
- + /*
- +  * ELM Module Registers
- +  */
- + 
- + /* ELM registers bit fields */
- + #define ELM_SYSCONFIG_SOFTRESET_MASK			(0x2)
- + #define ELM_SYSCONFIG_SOFTRESET			(0x2)
- + #define ELM_SYSSTATUS_RESETDONE_MASK			(0x1)
- + #define ELM_SYSSTATUS_RESETDONE			(0x1)
- + #define ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_MASK		(0x3)
- + #define ELM_LOCATION_CONFIG_ECC_SIZE_MASK		(0x7FF0000)
- + #define ELM_LOCATION_CONFIG_ECC_SIZE_POS		(16)
- + #define ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID		(0x00010000)
- + #define ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK	(0x100)
- + #define ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK		(0x1F)
- + 
- + #ifndef __ASSEMBLY__
- + 
- + enum bch_level {
- + 	BCH_4_BIT = 0,
- + 	BCH_8_BIT,
- + 	BCH_16_BIT
- + };
- + 
- + 
- + /* BCH syndrome registers */
- + struct syndrome {
- + 	u32 syndrome_fragment_x[7];	/* 0x400, 0x404.... 0x418 */
- + 	u8 res1[36];			/* 0x41c */
- + };
- + 
- + /* BCH error status & location register */
- + struct location {
- + 	u32 location_status;		/* 0x800 */
- + 	u8 res1[124];			/* 0x804 */
- + 	u32 error_location_x[16];	/* 0x880.... */
- + 	u8 res2[64];			/* 0x8c0 */
- + };
- + 
- + /* BCH ELM register map - do not try to allocate memmory for this structure.
- +  * We have used plenty of reserved variables to fill the slots in the ELM
- +  * register memory map.
- +  * Directly initialize the struct pointer to ELM base address.
- +  */
- + struct elm {
- + 	u32 rev;				/* 0x000 */
- + 	u8 res1[12];				/* 0x004 */
- + 	u32 sysconfig;				/* 0x010 */
- + 	u32 sysstatus;				/* 0x014 */
- + 	u32 irqstatus;				/* 0x018 */
- + 	u32 irqenable;				/* 0x01c */
- + 	u32 location_config;			/* 0x020 */
- + 	u8 res2[92];				/* 0x024 */
- + 	u32 page_ctrl;				/* 0x080 */
- + 	u8 res3[892];				/* 0x084 */
- + 	struct  syndrome syndrome_fragments[8]; /* 0x400 */
- + 	u8 res4[512];				/* 0x600 */
- + 	struct location  error_location[8];	/* 0x800 */
- + };
- + 
- + int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count,
- + 		u32 *error_locations);
- + int elm_config(enum bch_level level);
- + void elm_reset(void);
- + void elm_init(void);
- + #endif /* __ASSEMBLY__ */
- + #endif /* __ASM_ARCH_ELM_H */
- diff -crN u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/gpio.h u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/gpio.h
- *** u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/gpio.h	1970-01-01 09:00:00.000000000 +0900
- --- u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/gpio.h	2014-02-27 11:33:16.767558729 +0900
- ***************
- *** 0 ****
- --- 1,29 ----
- + /*
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation; either version 2 of
- +  * the License, or (at your option) any later version.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- +  * MA 02111-1307 USA
- +  *
- +  */
- + #ifndef _GPIO_AM33xx_H
- + #define _GPIO_AM33xx_H
- + 
- + #include <asm/omap_gpio.h>
- + 
- + #define AM33XX_GPIO0_BASE       0x44E07000
- + #define AM33XX_GPIO1_BASE       0x4804C000
- + #define AM33XX_GPIO2_BASE       0x481AC000
- + #define AM33XX_GPIO3_BASE       0x481AE000
- + 
- + #endif /* _GPIO_AM33xx_H */
- diff -crN u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/hardware.h u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/hardware.h
- *** u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/hardware.h	1970-01-01 09:00:00.000000000 +0900
- --- u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/hardware.h	2014-02-27 11:33:16.767558729 +0900
- ***************
- *** 0 ****
- --- 1,97 ----
- + /*
- +  * hardware.h
- +  *
- +  * hardware specific header
- +  *
- +  * Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation; either version 2 of
- +  * the License, or (at your option) any later version.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #ifndef __AM33XX_HARDWARE_H
- + #define __AM33XX_HARDWARE_H
- + 
- + #include <asm/arch/omap.h>
- + 
- + /* Module base addresses */
- + #define UART0_BASE			0x44E09000
- + 
- + /* DM Timer base addresses */
- + #define DM_TIMER0_BASE			0x4802C000
- + #define DM_TIMER1_BASE			0x4802E000
- + #define DM_TIMER2_BASE			0x48040000
- + #define DM_TIMER3_BASE			0x48042000
- + #define DM_TIMER4_BASE			0x48044000
- + #define DM_TIMER5_BASE			0x48046000
- + #define DM_TIMER6_BASE			0x48048000
- + #define DM_TIMER7_BASE			0x4804A000
- + 
- + /* GPIO Base address */
- + #define GPIO0_BASE			0x48032000
- + #define GPIO1_BASE			0x4804C000
- + #define GPIO2_BASE			0x481AC000
- + 
- + /* BCH Error Location Module */
- + #define ELM_BASE			0x48080000
- + 
- + /* Watchdog Timer */
- + #define WDT_BASE			0x44E35000
- + 
- + /* Control Module Base Address */
- + #define CTRL_BASE			0x44E10000
- + #define CTRL_DEVICE_BASE		0x44E10600
- + 
- + /* PRCM Base Address */
- + #define PRCM_BASE			0x44E00000
- + 
- + /* EMIF Base address */
- + #define EMIF4_0_CFG_BASE		0x4C000000
- + #define EMIF4_1_CFG_BASE		0x4D000000
- + 
- + /* PLL related registers */
- + #define CM_PER				0x44E00000
- + #define CM_WKUP				0x44E00400
- + #define CM_DPLL				0x44E00500
- + #define CM_DEVICE			0x44E00700
- + #define CM_RTC				0x44E00800
- + #define CM_CEFUSE			0x44E00A00
- + #define PRM_DEVICE			0x44E00F00
- + 
- + /* VTP Base address */
- + #define VTP0_CTRL_ADDR			0x44E10E0C
- + 
- + /* DDR Base address */
- + #define DDR_CTRL_ADDR			0x44E10E04
- + #define DDR_CONTROL_BASE_ADDR		0x44E11404
- + #define DDR_PHY_BASE_ADDR		0x44E12000
- + #define DDR_PHY_BASE_ADDR2		0x44E120A4
- + 
- + /* UART */
- + #define DEFAULT_UART_BASE		UART0_BASE
- + 
- + #define DDRPHY_0_CONFIG_BASE		(CTRL_BASE + 0x1400)
- + #define DDRPHY_CONFIG_BASE		DDRPHY_0_CONFIG_BASE
- + 
- + /* GPMC Base address */
- + #define GPMC_BASE			0x50000000
- + 
- + /* CPSW Config space */
- + #define AM335X_CPSW_BASE		0x4A100000
- + #define AM335X_CPSW_MDIO_BASE		0x4A101000
- + 
- + /* OTG */
- + #define AM335X_USB0_OTG_BASE		0x47401000
- + #define AM335X_USB1_OTG_BASE		0x47401800
- + 
- + /* RTC base address */
- + #define AM335X_RTC_BASE			0x44E3E000
- + 
- + #endif /* __AM33XX_HARDWARE_H */
- diff -crN u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/i2c.h u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/i2c.h
- *** u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/i2c.h	1970-01-01 09:00:00.000000000 +0900
- --- u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/i2c.h	2014-02-27 11:33:16.767558729 +0900
- ***************
- *** 0 ****
- --- 1,81 ----
- + /*
- +  * (C) Copyright 2012
- +  * Texas Instruments, <www.ti.com>
- +  *
- +  * See file CREDITS for list of people who contributed to this
- +  * project.
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation; either version 2 of
- +  * the License, or (at your option) any later version.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- +  * MA 02111-1307 USA
- +  */
- + #ifndef _I2C_H_
- + #define _I2C_H_
- + 
- + #define  I2C_BASE1		0x44E0B000
- + #define  I2C_BASE2		0x4802A000
- + #define  I2C_BASE3		0x4819C000
- + #define	 I2C_BUS_MAX		3
- + 
- + #define I2C_DEFAULT_BASE		I2C_BASE1
- + 
- + struct i2c {
- + 	unsigned short revnb_lo;        /* 0x00 */
- + 	unsigned short res1;
- + 	unsigned short revnb_hi;        /* 0x04 */
- + 	unsigned short res2[5];
- + 	unsigned short sysc;		/* 0x10 */
- + 	unsigned short res3[9];
- + 	unsigned short irqstatus_raw;   /* 0x24 */
- + 	unsigned short res4;
- + 	unsigned short stat;            /* 0x28 */
- + 	unsigned short res5;
- + 	unsigned short ie;              /* 0x2C */
- + 	unsigned short res6;
- + 	unsigned short irqenable_clr;   /* 0x30 */
- + 	unsigned short res7;
- + 	unsigned short iv;              /* 0x34 */
- + 	unsigned short res8[45];
- + 	unsigned short syss;            /* 0x90 */
- + 	unsigned short res9;
- + 	unsigned short buf;             /* 0x94 */
- + 	unsigned short res10;
- + 	unsigned short cnt;             /* 0x98 */
- + 	unsigned short res11;
- + 	unsigned short data;            /* 0x9C */
- + 	unsigned short res13;
- + 	unsigned short res14;           /* 0xA0 */
- + 	unsigned short res15;
- + 	unsigned short con;             /* 0xA4 */
- + 	unsigned short res16;
- + 	unsigned short oa;              /* 0xA8 */
- + 	unsigned short res17;
- + 	unsigned short sa;              /* 0xAC */
- + 	unsigned short res18;
- + 	unsigned short psc;             /* 0xB0 */
- + 	unsigned short res19;
- + 	unsigned short scll;            /* 0xB4 */
- + 	unsigned short res20;
- + 	unsigned short sclh;            /* 0xB8 */
- + 	unsigned short res21;
- + 	unsigned short systest;         /* 0xBC */
- + 	unsigned short res22;
- + 	unsigned short bufstat;         /* 0xC0 */
- + 	unsigned short res23;
- + };
- + 
- + #define I2C_IP_CLK			48000000
- + #define I2C_INTERNAL_SAMPLING_CLK	12000000
- + 
- + #endif /* _I2C_H_ */
- diff -crN u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/mem.h u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/mem.h
- *** u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/mem.h	1970-01-01 09:00:00.000000000 +0900
- --- u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/mem.h	2014-02-27 11:33:16.772186341 +0900
- ***************
- *** 0 ****
- --- 1,92 ----
- + /*
- +  * (C) Copyright 2006-2008
- +  * Texas Instruments, <www.ti.com>
- +  *
- +  * Author
- +  *		Mansoor Ahamed <mansoor.ahamed@ti.com>
- +  *
- +  * Initial Code from:
- +  *		Richard Woodruff <r-woodruff2@ti.com>
- +  *
- +  * See file CREDITS for list of people who contributed to this
- +  * project.
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation; either version 2 of
- +  * the License, or (at your option) any later version.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- +  * MA 02111-1307 USA
- +  */
- + 
- + #ifndef _MEM_H_
- + #define _MEM_H_
- + 
- + /*
- +  * GPMC settings -
- +  * Definitions is as per the following format
- +  * #define <PART>_GPMC_CONFIG<x> <value>
- +  * Where:
- +  * PART is the part name e.g. STNOR - Intel Strata Flash
- +  * x is GPMC config registers from 1 to 6 (there will be 6 macros)
- +  * Value is corresponding value
- +  *
- +  * For every valid PRCM configuration there should be only one definition of
- +  * the same. if values are independent of the board, this definition will be
- +  * present in this file if values are dependent on the board, then this should
- +  * go into corresponding mem-boardName.h file
- +  *
- +  * Currently valid part Names are (PART):
- +  * M_NAND - Micron NAND
- +  */
- + #define GPMC_SIZE_256M		0x0
- + #define GPMC_SIZE_128M		0x8
- + #define GPMC_SIZE_64M		0xC
- + #define GPMC_SIZE_32M		0xE
- + #define GPMC_SIZE_16M		0xF
- + 
- + #define M_NAND_GPMC_CONFIG1	0x00000800
- + #define M_NAND_GPMC_CONFIG2	0x001e1e00
- + #define M_NAND_GPMC_CONFIG3	0x001e1e00
- + #define M_NAND_GPMC_CONFIG4	0x16051807
- + #define M_NAND_GPMC_CONFIG5	0x00151e1e
- + #define M_NAND_GPMC_CONFIG6	0x16000f80
- + #define M_NAND_GPMC_CONFIG7	0x00000008
- + 
- + /* ST NOR chip on NOR cape for Beaglebone */
- + #define STNOR_GPMC_CONFIG1	0x00001200
- + #define STNOR_GPMC_CONFIG2	0x00101000
- + #define STNOR_GPMC_CONFIG3	0x00030301
- + #define STNOR_GPMC_CONFIG4	0x10041004
- + #define STNOR_GPMC_CONFIG5	0x000C1010
- + #define STNOR_GPMC_CONFIG6	0x08070280
- + #define STNOR_GPMC_CONFIG7	0x00000F48
- + 
- + /* max number of GPMC Chip Selects */
- + #define GPMC_MAX_CS		8
- + /* max number of GPMC regs */
- + #define GPMC_MAX_REG		7
- + 
- + #define PISMO1_NOR		1
- + #define PISMO1_NAND		2
- + #define PISMO2_CS0		3
- + #define PISMO2_CS1		4
- + #define PISMO1_ONENAND		5
- + #define DBG_MPDB		6
- + #define PISMO2_NAND_CS0		7
- + #define PISMO2_NAND_CS1		8
- + 
- + /* make it readable for the gpmc_init */
- + #define PISMO1_NOR_BASE	FLASH_BASE
- + #define PISMO1_NAND_BASE	CONFIG_SYS_NAND_BASE
- + #define PISMO1_NAND_SIZE	GPMC_SIZE_256M
- + 
- + #endif /* endif _MEM_H_ */
- diff -crN u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/mmc_host_def.h u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/mmc_host_def.h
- *** u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/mmc_host_def.h	1970-01-01 09:00:00.000000000 +0900
- --- u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/mmc_host_def.h	2014-02-27 11:33:16.772186341 +0900
- ***************
- *** 0 ****
- --- 1,163 ----
- + /*
- +  * mmc_host_def.h
- +  *
- +  * Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #ifndef MMC_HOST_DEF_H
- + #define MMC_HOST_DEF_H
- + 
- + /*
- +  * OMAP HSMMC register definitions
- +  */
- + #define OMAP_HSMMC1_BASE		0x48060100
- + #define OMAP_HSMMC2_BASE		0x481D8100
- + 
- + typedef struct hsmmc {
- + 	unsigned char res1[0x10];
- + 	unsigned int sysconfig;		/* 0x10 */
- + 	unsigned int sysstatus;		/* 0x14 */
- + 	unsigned char res2[0x14];
- + 	unsigned int con;		/* 0x2C */
- + 	unsigned char res3[0xD4];
- + 	unsigned int blk;		/* 0x104 */
- + 	unsigned int arg;		/* 0x108 */
- + 	unsigned int cmd;		/* 0x10C */
- + 	unsigned int rsp10;		/* 0x110 */
- + 	unsigned int rsp32;		/* 0x114 */
- + 	unsigned int rsp54;		/* 0x118 */
- + 	unsigned int rsp76;		/* 0x11C */
- + 	unsigned int data;		/* 0x120 */
- + 	unsigned int pstate;		/* 0x124 */
- + 	unsigned int hctl;		/* 0x128 */
- + 	unsigned int sysctl;		/* 0x12C */
- + 	unsigned int stat;		/* 0x130 */
- + 	unsigned int ie;		/* 0x134 */
- + 	unsigned char res4[0x8];
- + 	unsigned int capa;		/* 0x140 */
- + } hsmmc_t;
- + 
- + /*
- +  * OMAP HS MMC Bit definitions
- +  */
- + #define MMC_SOFTRESET			(0x1 << 1)
- + #define RESETDONE			(0x1 << 0)
- + #define NOOPENDRAIN			(0x0 << 0)
- + #define OPENDRAIN			(0x1 << 0)
- + #define OD				(0x1 << 0)
- + #define INIT_NOINIT			(0x0 << 1)
- + #define INIT_INITSTREAM			(0x1 << 1)
- + #define HR_NOHOSTRESP			(0x0 << 2)
- + #define STR_BLOCK			(0x0 << 3)
- + #define MODE_FUNC			(0x0 << 4)
- + #define DW8_1_4BITMODE			(0x0 << 5)
- + #define MIT_CTO				(0x0 << 6)
- + #define CDP_ACTIVEHIGH			(0x0 << 7)
- + #define WPP_ACTIVEHIGH			(0x0 << 8)
- + #define RESERVED_MASK			(0x3 << 9)
- + #define CTPL_MMC_SD			(0x0 << 11)
- + #define BLEN_512BYTESLEN		(0x200 << 0)
- + #define NBLK_STPCNT			(0x0 << 16)
- + #define DE_DISABLE			(0x0 << 0)
- + #define BCE_DISABLE			(0x0 << 1)
- + #define BCE_ENABLE			(0x1 << 1)
- + #define ACEN_DISABLE			(0x0 << 2)
- + #define DDIR_OFFSET			(4)
- + #define DDIR_MASK			(0x1 << 4)
- + #define DDIR_WRITE			(0x0 << 4)
- + #define DDIR_READ			(0x1 << 4)
- + #define MSBS_SGLEBLK			(0x0 << 5)
- + #define MSBS_MULTIBLK			(0x1 << 5)
- + #define RSP_TYPE_OFFSET			(16)
- + #define RSP_TYPE_MASK			(0x3 << 16)
- + #define RSP_TYPE_NORSP			(0x0 << 16)
- + #define RSP_TYPE_LGHT136		(0x1 << 16)
- + #define RSP_TYPE_LGHT48			(0x2 << 16)
- + #define RSP_TYPE_LGHT48B		(0x3 << 16)
- + #define CCCE_NOCHECK			(0x0 << 19)
- + #define CCCE_CHECK			(0x1 << 19)
- + #define CICE_NOCHECK			(0x0 << 20)
- + #define CICE_CHECK			(0x1 << 20)
- + #define DP_OFFSET			(21)
- + #define DP_MASK				(0x1 << 21)
- + #define DP_NO_DATA			(0x0 << 21)
- + #define DP_DATA				(0x1 << 21)
- + #define CMD_TYPE_NORMAL			(0x0 << 22)
- + #define INDEX_OFFSET			(24)
- + #define INDEX_MASK			(0x3f << 24)
- + #define INDEX(i)			(i << 24)
- + #define DATI_MASK			(0x1 << 1)
- + #define CMDI_MASK			(0x1 << 0)
- + #define DTW_1_BITMODE			(0x0 << 1)
- + #define DTW_4_BITMODE			(0x1 << 1)
- + #define DTW_8_BITMODE                   (0x1 << 5) /* CON[DW8]*/
- + #define SDBP_PWROFF			(0x0 << 8)
- + #define SDBP_PWRON			(0x1 << 8)
- + #define SDVS_1V8			(0x5 << 9)
- + #define SDVS_3V0			(0x6 << 9)
- + #define ICE_MASK			(0x1 << 0)
- + #define ICE_STOP			(0x0 << 0)
- + #define ICS_MASK			(0x1 << 1)
- + #define ICS_NOTREADY			(0x0 << 1)
- + #define ICE_OSCILLATE			(0x1 << 0)
- + #define CEN_MASK			(0x1 << 2)
- + #define CEN_DISABLE			(0x0 << 2)
- + #define CEN_ENABLE			(0x1 << 2)
- + #define CLKD_OFFSET			(6)
- + #define CLKD_MASK			(0x3FF << 6)
- + #define DTO_MASK			(0xF << 16)
- + #define DTO_15THDTO			(0xE << 16)
- + #define SOFTRESETALL			(0x1 << 24)
- + #define CC_MASK				(0x1 << 0)
- + #define TC_MASK				(0x1 << 1)
- + #define BWR_MASK			(0x1 << 4)
- + #define BRR_MASK			(0x1 << 5)
- + #define ERRI_MASK			(0x1 << 15)
- + #define IE_CC				(0x01 << 0)
- + #define IE_TC				(0x01 << 1)
- + #define IE_BWR				(0x01 << 4)
- + #define IE_BRR				(0x01 << 5)
- + #define IE_CTO				(0x01 << 16)
- + #define IE_CCRC				(0x01 << 17)
- + #define IE_CEB				(0x01 << 18)
- + #define IE_CIE				(0x01 << 19)
- + #define IE_DTO				(0x01 << 20)
- + #define IE_DCRC				(0x01 << 21)
- + #define IE_DEB				(0x01 << 22)
- + #define IE_CERR				(0x01 << 28)
- + #define IE_BADA				(0x01 << 29)
- + 
- + #define VS30_3V0SUP			(1 << 25)
- + #define VS18_1V8SUP			(1 << 26)
- + 
- + /* Driver definitions */
- + #define MMCSD_SECTOR_SIZE		512
- + #define MMC_CARD			0
- + #define SD_CARD				1
- + #define BYTE_MODE			0
- + #define SECTOR_MODE			1
- + #define CLK_INITSEQ			0
- + #define CLK_400KHZ			1
- + #define CLK_MISC			2
- + 
- + #define RSP_TYPE_NONE	(RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
- + #define MMC_CMD0	(INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
- + 
- + /* Clock Configurations and Macros */
- + #define MMC_CLOCK_REFERENCE	96 /* MHz */
- + 
- + #define mmc_reg_out(addr, mask, val)\
- + 	writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
- + 
- + int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max);
- + 
- + #endif /* MMC_HOST_DEF_H */
- diff -crN u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/omap_gpmc.h u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/omap_gpmc.h
- *** u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/omap_gpmc.h	1970-01-01 09:00:00.000000000 +0900
- --- u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/omap_gpmc.h	2014-02-27 11:33:16.772186341 +0900
- ***************
- *** 0 ****
- --- 1,120 ----
- + /*
- +  * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
- +  * Rohit Choraria <rohitkc@ti.com>
- +  *
- +  * See file CREDITS for list of people who contributed to this
- +  * project.
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation; either version 2 of
- +  * the License, or (at your option) any later version.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- +  * MA 02111-1307 USA
- +  */
- + #ifndef __ASM_ARCH_OMAP_GPMC_H
- + #define __ASM_ARCH_OMAP_GPMC_H
- + 
- + #define GPMC_BUF_EMPTY	0
- + #define GPMC_BUF_FULL	1
- + 
- + #define ECCCLEAR	(0x1 << 8)
- + #define ECCRESULTREG1	(0x1 << 0)
- + #define ECCSIZE512BYTE	0xFF
- + #define ECCSIZE1	(ECCSIZE512BYTE << 22)
- + #define ECCSIZE0	(ECCSIZE512BYTE << 12)
- + #define ECCSIZE0SEL	(0x000 << 0)
- + 
- + /* Generic ECC Layouts */
- + /* Large Page x8 NAND device Layout */
- + #ifdef GPMC_NAND_ECC_LP_x8_LAYOUT
- + #define GPMC_NAND_HW_ECC_LAYOUT {\
- + 	.eccbytes = 12,\
- + 	.eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\
- + 		9, 10, 11, 12},\
- + 	.oobfree = {\
- + 		{.offset = 13,\
- + 		 .length = 51 } } \
- + }
- + #endif
- + 
- + /* Large Page x16 NAND device Layout */
- + #ifdef GPMC_NAND_ECC_LP_x16_LAYOUT
- + #define GPMC_NAND_HW_ECC_LAYOUT {\
- + 	.eccbytes = 12,\
- + 	.eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\
- + 		10, 11, 12, 13},\
- + 	.oobfree = {\
- + 		{.offset = 14,\
- + 		 .length = 50 } } \
- + }
- + #endif
- + 
- + /* Small Page x8 NAND device Layout */
- + #ifdef GPMC_NAND_ECC_SP_x8_LAYOUT
- + #define GPMC_NAND_HW_ECC_LAYOUT {\
- + 	.eccbytes = 3,\
- + 	.eccpos = {1, 2, 3},\
- + 	.oobfree = {\
- + 		{.offset = 4,\
- + 		 .length = 12 } } \
- + }
- + #endif
- + 
- + /* Small Page x16 NAND device Layout */
- + #ifdef GPMC_NAND_ECC_SP_x16_LAYOUT
- + #define GPMC_NAND_HW_ECC_LAYOUT {\
- + 	.eccbytes = 3,\
- + 	.eccpos = {2, 3, 4},\
- + 	.oobfree = {\
- + 		{.offset = 5,\
- + 		 .length = 11 } } \
- + }
- + #endif
- + 
- + #define GPMC_NAND_HW_BCH4_ECC_LAYOUT {\
- + 	.eccbytes = 32,\
- + 	.eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
- + 				16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
- + 				28, 29, 30, 31, 32, 33},\
- + 	.oobfree = {\
- + 		{.offset = 34,\
- + 		 .length = 30 } } \
- + }
- + 
- + #define GPMC_NAND_HW_BCH8_ECC_LAYOUT {\
- + 	.eccbytes = 56,\
- + 	.eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
- + 				16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
- + 				28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\
- + 				40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,\
- + 				52, 53, 54, 55, 56, 57},\
- + 	.oobfree = {\
- + 		{.offset = 58,\
- + 		 .length = 6 } } \
- + }
- + 
- + #define GPMC_NAND_HW_BCH16_ECC_LAYOUT {\
- + 	.eccbytes = 104,\
- + 	.eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
- + 				16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
- + 				28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\
- + 				40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,\
- + 				52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,\
- + 				64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,\
- + 				76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,\
- + 				88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,\
- + 				100, 101, 102, 103, 104, 105},\
- + 	.oobfree = {\
- + 		{.offset = 106,\
- + 		 .length = 8 } } \
- + }
- + #endif /* __ASM_ARCH_OMAP_GPMC_H */
- diff -crN u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/omap.h u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/omap.h
- *** u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/omap.h	1970-01-01 09:00:00.000000000 +0900
- --- u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/omap.h	2014-02-27 11:33:16.772186341 +0900
- ***************
- *** 0 ****
- --- 1,58 ----
- + /*
- +  * omap.h
- +  *
- +  * Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation; either version 2 of
- +  * the License, or (at your option) any later version.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #ifndef _OMAP_H_
- + #define _OMAP_H_
- + 
- + /*
- +  * Non-secure SRAM Addresses
- +  * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
- +  * at 0x40304000(EMU base) so that our code works for both EMU and GP
- +  */
- + #define NON_SECURE_SRAM_START	0x402F0400
- + #define NON_SECURE_SRAM_END	0x402FFFFF
- + 
- + /* ROM code defines */
- + /* Boot device */
- + #define BOOT_DEVICE_MASK	0xFF
- + #define BOOT_DEVICE_OFFSET	0x8
- + #define DEV_DESC_PTR_OFFSET	0x4
- + #define DEV_DATA_PTR_OFFSET	0x18
- + #define BOOT_MODE_OFFSET	0x8
- + #define RESET_REASON_OFFSET	0x9
- + #define CH_FLAGS_OFFSET		0xA
- + 
- + #define CH_FLAGS_CHSETTINGS	(0x1 << 0)
- + #define CH_FLAGS_CHRAM		(0x1 << 1)
- + #define CH_FLAGS_CHFLASH	(0x1 << 2)
- + #define CH_FLAGS_CHMMCSD	(0x1 << 3)
- + 
- + #ifndef __ASSEMBLY__
- + struct omap_boot_parameters {
- + 	char *boot_message;
- + 	unsigned int mem_boot_descriptor;
- + 	unsigned char omap_bootdevice;
- + 	unsigned char reset_reason;
- + 	unsigned char ch_flags;
- + };
- + #endif
- + #endif
- + 
- + 
- + 
- + 
- + 
- + 
- diff -crN u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/spl.h u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/spl.h
- *** u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/spl.h	1970-01-01 09:00:00.000000000 +0900
- --- u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/spl.h	2014-02-27 11:33:16.772186341 +0900
- ***************
- *** 0 ****
- --- 1,35 ----
- + /*
- +  * (C) Copyright 2012
- +  * Texas Instruments, <www.ti.com>
- +  *
- +  * See file CREDITS for list of people who contributed to this
- +  * project.
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation; either version 2 of
- +  * the License, or (at your option) any later version.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- +  * MA 02111-1307 USA
- +  */
- + #ifndef	_ASM_ARCH_SPL_H_
- + #define	_ASM_SPL_H_
- + 
- + #define BOOT_DEVICE_XIP       	2
- + #define BOOT_DEVICE_NAND	5
- + #define BOOT_DEVICE_MMC1	8
- + #define BOOT_DEVICE_MMC2	9	/* eMMC or daughter card */
- + #define BOOT_DEVICE_SPI		11
- + #define BOOT_DEVICE_UART	65
- + #define BOOT_DEVICE_USB		68
- + #define BOOT_DEVICE_CPGMAC	70
- + #define BOOT_DEVICE_MMC2_2      0xFF
- + #endif
- diff -crN u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/sys_proto.h u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/sys_proto.h
- *** u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/sys_proto.h	1970-01-01 09:00:00.000000000 +0900
- --- u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/sys_proto.h	2014-02-27 11:33:16.775510866 +0900
- ***************
- *** 0 ****
- --- 1,70 ----
- + /*
- +  * sys_proto.h
- +  *
- +  * System information header
- +  *
- +  * Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation; either version 2 of
- +  * the License, or (at your option) any later version.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #ifndef _SYS_PROTO_H_
- + #define _SYS_PROTO_H_
- + 
- + /*
- +  * AM335x parts define a system EEPROM that defines certain sub-fields.
- +  * We use these fields to in turn see what board we are on, and what
- +  * that might require us to set or not set.
- +  */
- + #define HDR_NO_OF_MAC_ADDR	3
- + #define HDR_ETH_ALEN		6
- + #define HDR_NAME_LEN		8
- + 
- + struct am335x_baseboard_id {
- + 	unsigned int  magic;
- + 	char name[HDR_NAME_LEN];
- + 	char version[4];
- + 	char serial[12];
- + 	char config[32];
- + 	char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
- + };
- + 
- + int board_is_evm_15_or_later(void);
- + 
- + #define BOARD_REV_ID	0x0
- + 
- + u32 get_cpu_rev(void);
- + u32 get_sysboot_value(void);
- + 
- + #ifdef CONFIG_DISPLAY_CPUINFO
- + int print_cpuinfo(void);
- + #endif
- + 
- + extern struct ctrl_stat *cstat;
- + u32 get_device_type(void);
- + void setup_clocks_for_console(void);
- + void ddr_pll_config(unsigned int ddrpll_M);
- + void mpu_pll_config(int mpupll_M);
- + void sdelay(unsigned long);
- + void gpmc_init(void);
- + void omap_nand_switch_ecc(int);
- + void am33xx_spl_board_init(void);
- + 
- + /*
- +  * We have three pin mux functions that must exist.  We must be able to enable
- +  * uart0, for initial output and i2c0 to read the main EEPROM.  We then have a
- +  * main pinmux function that can be overridden to enable all other pinmux that
- +  * is required on the board.
- +  */
- + void enable_uart0_pin_mux(void);
- + void enable_i2c0_pin_mux(void);
- + void enable_board_pin_mux();
- + #endif
- diff -crN u-boot-2012.10_o/arch/arm/include/asm/setup.h u-boot-2012.10/arch/arm/include/asm/setup.h
- *** u-boot-2012.10_o/arch/arm/include/asm/setup.h	2012-10-16 00:14:08.000000000 +0900
- --- u-boot-2012.10/arch/arm/include/asm/setup.h	2014-03-28 11:37:09.796688000 +0900
- ***************
- *** 105,110 ****
- --- 105,113 ----
-   	u32	start;	/* physical start address */
-   };
-   
- + /* FB TAG */
- + #define ATAG_FB		0x54411002
- + 
-   /* VGA text type displays */
-   #define ATAG_VIDEOTEXT	0x54410003
-   
- diff -crN u-boot-2012.10_o/arch/arm/lib/board.c u-boot-2012.10/arch/arm/lib/board.c
- *** u-boot-2012.10_o/arch/arm/lib/board.c	2012-10-16 00:14:08.000000000 +0900
- --- u-boot-2012.10/arch/arm/lib/board.c	2014-03-28 11:37:26.037617000 +0900
- ***************
- *** 331,336 ****
- --- 331,340 ----
-   
-   	addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size;
-   
- + #ifdef CONFIG_MACH_CKB_3352
- + 	addr -= CONFIG_CKB_RESERVED_MEM;		/* reserve memory (donot use this in U-boot) */
- + #endif
- + 
-   #ifdef CONFIG_LOGBUFFER
-   #ifndef CONFIG_ALT_LB_ADDR
-   	/* reserve kernel log buffer */
- ***************
- *** 374,379 ****
- --- 378,384 ----
-   #endif /* CONFIG_FB_ADDR */
-   #endif /* CONFIG_LCD */
-   
- + #ifndef CONFIG_NO_RELOCATE_UBOOT
-   	/*
-   	 * reserve memory for U-Boot code, data & bss
-   	 * round down to next 4 kB limit
- ***************
- *** 382,387 ****
- --- 387,393 ----
-   	addr &= ~(4096 - 1);
-   
-   	debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, addr);
- + #endif
-   
-   #ifndef CONFIG_SPL_BUILD
-   	/*
- ***************
- *** 438,447 ****
- --- 444,466 ----
-   	dram_init_banksize();
-   	display_dram_config();	/* and display it */
-   
- + #ifdef CONFIG_NO_RELOCATE_UBOOT
- + 	addr = _TEXT_BASE;
- + #endif
- + 
-   	gd->relocaddr = addr;
-   	gd->start_addr_sp = addr_sp;
-   	gd->reloc_off = addr - _TEXT_BASE;
- + #ifdef CONFIG_MACH_CKB_3352
- + #ifndef CONFIG_NO_RELOCATE_UBOOT
- + 	printf("Relocating U-Boot to %08lX, Offset: %08lX\n", gd->relocaddr, gd->reloc_off);
- + #endif
- + 	printf("Malloc area at %08lX, len=%dkB\n", gd->bd+sizeof(bd_t), TOTAL_MALLOC_LEN>>10);
- + 	printf("Board info at %08lX, len=%d bytes\n", gd->bd, sizeof(bd_t));
- + 	printf("Stack at %08lX\n", gd->start_addr_sp);
- + #else
-   	debug("relocation Offset is: %08lx\n", gd->reloc_off);
- + #endif
-   	memcpy(id, (void *)gd, sizeof(gd_t));
-   
-   	relocate_code(addr_sp, id, addr);
- ***************
- *** 453,458 ****
- --- 472,478 ----
-   static char *failed = "*** failed ***\n";
-   #endif
-   
- + 
-   /*
-    ************************************************************************
-    *
- ***************
- *** 513,518 ****
- --- 533,544 ----
-   	arch_early_init_r();
-   #endif
-   
- + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
- + 	unsigned long env_addr = gd->env_addr;
- + 	gd->env_addr = malloc(CONFIG_ENV_SIZE);
- + 	memcpy(gd->env_addr, env_addr, CONFIG_ENV_SIZE);
- + #endif
- + 
-   #if !defined(CONFIG_SYS_NO_FLASH)
-   	puts("Flash: ");
-   
- ***************
- *** 542,547 ****
- --- 568,577 ----
-   	}
-   #endif
-   
- + #ifdef CONFIG_MACH_CKB_3352
- + 	init_lcd_and_display_logo();
- + #endif
- + 
-   #if defined(CONFIG_CMD_NAND)
-   	puts("NAND:  ");
-   	nand_init();		/* go init the NAND */
- ***************
- *** 649,654 ****
- --- 679,690 ----
-   	}
-   #endif
-   
- + #ifdef CONFIG_MACH_CKB_3352
- + 	volatile extern int _loader_executed_uboot;
- + 	if(!_loader_executed_uboot)
- + 		printf("U-Boot has been copied to 0x%X, use the command \""FLASH_UBOOT_CMD_STR"\" to write U-Boot to flash memory\n", UBOOT_TEMP_ADDR);
- + #endif
- + 
-   	/* main_loop() can return to retry autoboot, if so just run it again. */
-   	for (;;) {
-   		main_loop();
- diff -crN u-boot-2012.10_o/arch/arm/lib/bootm.c u-boot-2012.10/arch/arm/lib/bootm.c
- *** u-boot-2012.10_o/arch/arm/lib/bootm.c	2012-10-16 00:14:08.000000000 +0900
- --- u-boot-2012.10/arch/arm/lib/bootm.c	2014-03-28 11:37:40.327435000 +0900
- ***************
- *** 140,145 ****
- --- 140,153 ----
-   
-   		params = tag_next (params);
-   	}
- + #ifdef CONFIG_FB_BASE_ADDRESS
- + 	/* fill FB address */
- + 	params->hdr.tag = ATAG_FB;
- + 	params->hdr.size = tag_size (tag_mem32);
- + 	params->u.mem.start = CONFIG_FB_BASE_ADDRESS;
- + 	params->u.mem.size = CONFIG_FB_MAP_SIZE;
- + 	params = tag_next (params);
- + #endif
-   }
-   #endif
-   
- diff -crN u-boot-2012.10_o/board/computex/ckb-3352/cmd_custom.c u-boot-2012.10/board/computex/ckb-3352/cmd_custom.c
- *** u-boot-2012.10_o/board/computex/ckb-3352/cmd_custom.c	1970-01-01 09:00:00.000000000 +0900
- --- u-boot-2012.10/board/computex/ckb-3352/cmd_custom.c	2014-03-28 11:38:11.202201000 +0900
- ***************
- *** 0 ****
- --- 1,530 ----
- + /*
- +  * Computex CKB board additional commands
- +  *
- +  * Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; version 2 of the License.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- +  *
- +  */
- + #include <common.h>
- + #include <command.h>
- + 
- + extern int do_mem_cp ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
- + extern int do_flerase (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
- + extern int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
- + 
- + //U_BOOT_CMD(name,maxargs,repeatable,command,"usage","help")
- + volatile extern int _approx_uboot_len;
- + volatile extern int _loader_executed_uboot;
- + extern int ckb_3352_cur_flash_bank;
- + 
- + #define KERNEL_FLASH_BANK				8
- + #define KERNEL_FLASH_BANK_STR			"8"
- + 
- + #ifdef CONFIG_SYS_USE_NOR
- + 
- + int parse_bank_n_address(char *str, int *bank, ulong *addr)
- + {
- + 	char *p;
- + 
- + 	/* check for ":" */
- + 	if ((p = strchr (str, ':')) == NULL)
- + 	{
- + 		printf ("Flash bank not specified.\n");
- + 		return 1;
- + 	}
- + 	*bank = simple_strtoul (str, NULL, 10);
- + 	*p++ = '\0';
- + 	*addr = simple_strtoul(p, NULL, 16);
- + 	return 0;
- + }
- + 
- + int get_required_flash_sectors(int len)
- + {
- + 	int banks = len / CONFIG_SYS_FLASH_SECT_SZ;
- + 	if(len % CONFIG_SYS_FLASH_SECT_SZ)
- + 		banks++;
- + 	return banks;
- + }
- + 
- + int erase_and_write(cmd_tbl_t *cmdtp, int flag, char *image_name, ulong src_addr, int bank, ulong len)
- + {
- + 	char addr1[16], length[16], addr2[16];
- + 	char *temp_argv[5];
- + 	ulong flash_addr;
- + 	printf("Writing %s from 0x%X to NOR Bank#%d, %ld bytes\n", image_name, src_addr, bank, len);
- + 
- + 	printf ("Erasing Flash...\n");
- + 	temp_argv[0] = "erase";
- + 	flash_addr = CONFIG_SYS_FLASH_BASE + (bank*CONFIG_FLASH_CKB_BANK_SIZE);
- + 	sprintf(addr1, "%X", flash_addr);
- + 	/* length must be aligned */
- + 	sprintf(addr2, "%X", flash_addr + ((get_required_flash_sectors(len)*CONFIG_SYS_FLASH_SECT_SZ) - 1));
- + 	temp_argv[1] = addr1;
- + 	temp_argv[2] = addr2;
- + 	//printf("Actual %s %s\n",  addr1, addr2);
- + 	if(do_flerase(cmdtp, flag, 3, temp_argv))
- + 	{
- + _failed:
- + 		printf ("Failed\n");
- + 		return 1;
- + 	}
- + 	printf ("Flashing %s...\n", image_name);
- + 	/* write Uboot to flash */
- + 	temp_argv[0] = "cp.b";
- + 	sprintf(addr2, "%X", src_addr);
- + 	sprintf(length, "%X", len);
- + 	temp_argv[1] = addr2;				/* source address */
- + 	temp_argv[2] = addr1;				/* destination flash address */
- + 	temp_argv[3] = length;				/* count */
- + 	if(do_mem_cp(cmdtp, flag, 4, temp_argv))
- + 	{
- + 		goto _failed;
- + 	}
- + 	return 0;
- + }
- + 
- + 
- + int ckb_flash_uboot(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
- + {
- + 	if(argc!=1)
- + 	{
- + 		goto usage;
- + 	}
- + 	return erase_and_write(cmdtp, flag, "U-boot", UBOOT_TEMP_ADDR, (UBOOT_NOR_BASE_ADDR-CONFIG_SYS_FLASH_BASE)/CONFIG_FLASH_CKB_BANK_SIZE,
- + 				_approx_uboot_len);
- + 
- + usage:
- + 	cmd_usage(cmdtp);
- + 	return 1;
- + }
- + 
- + U_BOOT_CMD(flash_uboot,1,0,ckb_flash_uboot,"Write U-Boot(current U-Boot binary) to NOR flash","");
- + 
- + int ctex_check_flash_bank(int bank)
- + {
- + 	if(bank<0 || bank>=CONFIG_FLASH_CKB_BANKS)
- + 	{
- + 		printf ("Invalid flash bank %d. Valid value 0~%d.\n", bank, CONFIG_FLASH_CKB_BANKS-1);
- + 		return 1;
- + 	}
- + 	return 0;
- + }
- + 
- + int ctex_check_flash_addr(ulong addr)
- + {
- + 	if(addr<CONFIG_SYS_FLASH_BASE || addr>=(CONFIG_SYS_FLASH_BASE+CONFIG_FLASH_CKB_BANK_SIZE))
- + 	{
- + 		printf ("Invalid flash address 0x%X. Valid value 0x%X~0x%X.\n", addr, 
- + 					CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+CONFIG_FLASH_CKB_BANK_SIZE-1);
- + 		return 1;
- + 	}
- + 	return 0;
- + }
- + 
- + int ctex_flash_boundary_check(ulong addr, int bank, ulong count, ulong *actual_addr)
- + {
- + 	
- + 	if(ctex_check_flash_bank(bank) || ctex_check_flash_addr(addr))
- + 		return 1;
- + 
- + 	/* get actual flash address */
- + 	addr = addr+(bank*CONFIG_FLASH_CKB_BANK_SIZE);
- + 	if((addr+count) > (CONFIG_SYS_FLASH_BASE+(CONFIG_FLASH_CKB_BANK_SIZE*CONFIG_FLASH_CKB_BANKS)))
- + 	{
- + 		printf ("Data overflow. Count exceeds flash limit\n");
- + 		return 1;
- + 	}
- + 	*actual_addr = addr;
- + 	return 0;
- + }
- + 
- + int ctex_flash_write(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
- + {
- + 	char *temp_argv[4];
- + 	ulong	addr, count;
- + 	int bank;
- + 	char addr1[16];
- + 	if(argc!=4)
- + 	{
- + 		goto usage;
- + 	}
- + 	/* address check */
- + 	if(parse_bank_n_address(argv[2], &bank, &addr))
- + 	{
- + 		goto usage;
- + 	}
- + 	count = simple_strtoul(argv[3], NULL, 16);
- + 	if(ctex_flash_boundary_check(addr, bank, count, &addr))
- + 		return 1;
- + 
- + 	temp_argv[0] = "cp.b";
- + 	temp_argv[1] = argv[1];				/* source address */
- + 	/* The actual flash address */
- + 	sprintf(addr1, "%X", addr);
- + 	temp_argv[2] = addr1;				/* destination flash address */
- + 	temp_argv[3] = argv[3];				/* count */
- + 	return do_mem_cp(cmdtp, flag, 4, temp_argv);
- + 	
- + usage:
- + 	cmd_usage(cmdtp);
- + 	return 1;
- + }
- + 
- + /* flash write command */
- + U_BOOT_CMD(fwrite,4,1,ctex_flash_write,
- + 	"Write to flash memory",
- + 	"source N:target count\n"
- + 	"    - Write 'count' bytes from addr 'source' to flash addr 'target' of bank 'N'\n"
- + 	);
- + 
- + 
- + int ctex_flash_read(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
- + {
- + 	char *temp_argv[4];
- + 	ulong	addr, count;
- + 	int bank;
- + 	char addr1[16];
- + 	if(argc!=4)
- + 	{
- + 		goto usage;
- + 	}
- + 	/* address check */
- + 	if(parse_bank_n_address(argv[1], &bank, &addr))
- + 	{
- + 		goto usage;
- + 	}
- + 	/* address check */
- + 	count = simple_strtoul(argv[3], NULL, 16);
- + 	if(ctex_flash_boundary_check(addr, bank, count, &addr))
- + 		return 1;
- + 
- + 	temp_argv[0] = "cp.b";
- + 	/* The actual flash address */
- + 	sprintf(addr1, "%X", addr);
- + 	temp_argv[1] = addr1;				/* source flash address */
- + 	temp_argv[2] = argv[2];				/* destination address */
- + 	temp_argv[3] = argv[3];				/* count */
- + 	return do_mem_cp(cmdtp, flag, 4, temp_argv);
- + 	
- + usage:
- + 	cmd_usage(cmdtp);
- + 	return 1;
- + }
- + 
- + /* flash read command */
- + U_BOOT_CMD(fread,4,1,ctex_flash_read,
- + 	"Read from flash memory",
- + 	"N:source target count\n"
- + 	"    - Read 'count' bytes from flash addr 'source' of bank 'N' to addr 'target'\n"
- + 	);
- + 	
- + 
- + int ctex_flash_erase(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
- + {
- + 	char *temp_argv[3];
- + 	ulong start_addr, end_addr;
- + 	char addr1[16], addr2[16];
- + 	int bank, bank_end;
- + 	temp_argv[0] = "erase";
- + 
- + 	if(argc == 2 && strcmp(argv[1], "all") == 0) 
- + 	{
- + 		temp_argv[1] = argv[1];
- + 		return do_flerase(cmdtp, flag, 2, temp_argv);
- + 	}
- + 	if(argc == 2 || argc == 3)
- + 	{
- + 		/* get the bank */
- + 		bank = simple_strtoul (argv[1], NULL, 10);
- + 		if(ctex_check_flash_bank(bank))
- + 			return 1;
- + 
- + 		/* get the actual address and erase the bank */
- + 		start_addr = (bank*CONFIG_FLASH_CKB_BANK_SIZE) | CONFIG_SYS_FLASH_BASE;
- + 		if(argc == 2)
- + 		{
- + 			end_addr = start_addr + CONFIG_FLASH_CKB_BANK_SIZE-1;
- + 		}
- + 		else
- + 		{
- + 			bank_end = simple_strtoul (argv[2], NULL, 10);
- + 			if(ctex_check_flash_bank(bank_end))
- + 				return 1;
- + 			end_addr =  ((bank_end*CONFIG_FLASH_CKB_BANK_SIZE) | CONFIG_SYS_FLASH_BASE) + CONFIG_FLASH_CKB_BANK_SIZE-1;
- + 		}
- + 
- + 		sprintf(addr1, "%X", start_addr);
- + 		sprintf(addr2, "%X", end_addr);
- + 		//printf("Actual %X %X\n",  start_addr, end_addr);
- + 		temp_argv[1] = addr1;
- + 		temp_argv[2] = addr2;
- + 		return do_flerase(cmdtp, flag, 3, temp_argv);
- + 	}
- + 
- + usage:
- + 	cmd_usage(cmdtp);
- + 	return 1;
- + }
- + 
- + U_BOOT_CMD(
- + 	erase,   3,   0,  ctex_flash_erase,
- + 	"erase FLASH memory",
- + 	" N\n   - erase FLASH bank 'N'\n"
- + 	"erase n1 n2\n   - erase FLASH bank 'n1' through 'n2'\n"
- + 	"erase all\n    - erase all FLASH banks"
- + );
- + 
- + int ctex_flash_protect(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
- + {
- + 	char *temp_argv[4];
- + 	ulong start_addr, end_addr;
- + 	char addr1[16], addr2[16];
- + 	int bank;
- + 	temp_argv[0] = "protect";
- + 
- + 	if(argc<3 || (strcmp(argv[1], "on") && strcmp(argv[1], "off")))
- + 	{
- + 		goto usage;
- + 	}
- + 	temp_argv[1] = argv[1];
- + 
- + 	if(argc == 3)
- + 	{
- + 		char *p;
- + 		if (strcmp(argv[2], "all") == 0) {
- + 			temp_argv[2] = argv[2];
- + 			return do_protect(cmdtp, flag, 3, temp_argv);
- + 		}
- + 
- + 		/* address not specified; get the bank */
- + 		bank = simple_strtoul (argv[2], NULL, 10);
- + 		if(ctex_check_flash_bank(bank))
- + 			return 1;
- + 		/* get the actual address */
- + 		start_addr = (bank*CONFIG_FLASH_CKB_BANK_SIZE) | CONFIG_SYS_FLASH_BASE;
- + 		end_addr = start_addr + CONFIG_FLASH_CKB_BANK_SIZE-1;
- + 		sprintf(addr1, "%X", start_addr);
- + 		sprintf(addr2, "%X", end_addr);
- + 		//printf("Actual %X %X\n",  start_addr, end_addr);
- + 		temp_argv[2] = addr1;
- + 		temp_argv[3] = addr2;
- + 		return do_protect(cmdtp, flag, 4, temp_argv);
- + 	}
- + usage:
- + 	cmd_usage(cmdtp);
- + 	return 1;
- + }
- + 
- + U_BOOT_CMD(
- + 	protect, 3,  0,   ctex_flash_protect,
- + 	"enable or disable FLASH write protection",
- + 	"on  N\n    - protect FLASH bank 'N'\n"
- + 	"protect on  all\n    - protect all FLASH banks\n"
- + 	"protect off N\n    - make FLASH bank 'N' writable\n"
- + 	"protect off all\n    - make all FLASH banks writable"
- + );
- + 
- + int ctex_set_flash_bank(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
- + {
- + 	int bank;
- + 	if(argc != 2)
- + 	{
- + 		goto usage;
- + 	}
- + 
- + 	/* get the bank */
- + 	bank = simple_strtoul (argv[1], NULL, 10);
- + 	if(ctex_check_flash_bank(bank))
- + 		return 1;
- + 	set_nor_flash_bank(bank);
- + 	return 0;
- + usage:
- + 	cmd_usage(cmdtp);
- + 	return 1;
- + }
- + 
- + U_BOOT_CMD(
- + 	fbank_set,   2,   0,  ctex_set_flash_bank,
- + 	"Set FLASH memory bank",
- + 	"N\n    - Set FLASH memory bank to 'N'"
- + );
- + 
- + 
- + int ckb_flash_kernel(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
- + {
- + 	ulong addr;
- + 	image_header_t *hdr;
- + 	ulong size;
- + 	if(argc != 2) 
- + 	{
- + 		goto usage;
- + 	}
- + 	addr = simple_strtoul (argv[1], NULL, 16);
- + 	/* check for the kernel header */
- + 	hdr = (image_header_t *)addr;
- + 	size = image_get_data_size(hdr) + sizeof(image_header_t);
- + 	if(size < CKB_KERN_MIN_SIZE ||  size > CKB_KERN_MAX_SIZE)
- + 	{
- + 		printf ("Image size is %d (0x%08X) bytes which is too %s\n", size, size,
- + 					(size < CKB_KERN_MIN_SIZE)?"small":"large");
- + 		return 1;
- + 	}
- + 	return erase_and_write(cmdtp, flag, "Kernel", addr, KERNEL_FLASH_BANK, size);
- + 
- + usage:
- + 	cmd_usage(cmdtp);
- + 	return 1;
- + }
- + 
- + U_BOOT_CMD(
- + 	flash_kernel,   2,   0,  ckb_flash_kernel,
- + 	"Write Kernel binary (uImage) to NOR flash",
- + 	"addr\n    - Write Kernel from SDRAM address 'addr' to NOR Bank# "KERNEL_FLASH_BANK_STR":0x08000000"
- + );
- + 
- + int ckb_fread_kernel(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
- + {
- + 	ulong addr;
- + 	image_header_t *hdr;
- + 	ulong size;
- + 	ulong faddr;
- + 	char *temp_argv[4];
- + 	char addr1[16], count[16];
- + 	if(argc != 2)
- + 	{
- + 		goto usage;
- + 	}
- + 	addr = simple_strtoul (argv[1], NULL, 16);
- + 	/* check for the kernel at the flash bank */
- + 	int cur_bank = ckb_3352_cur_flash_bank;
- + 	set_nor_flash_bank(KERNEL_FLASH_BANK);
- + 	hdr = (image_header_t *)CONFIG_SYS_FLASH_BASE;
- + 	size = image_get_data_size(hdr) + sizeof(image_header_t);
- + 	printf ("Reading Kernel from NOR Bank# "KERNEL_FLASH_BANK_STR" to 0x%X\n", addr);
- + 	if(size < CKB_KERN_MIN_SIZE || size > CKB_KERN_MAX_SIZE)
- + 	{
- + 		printf ("Kernel Image size is %d (0x%08X) bytes which is too %s\n", size, size,
- + 					(size < CKB_KERN_MIN_SIZE)?"small":"large");
- + 		printf ("Ignoring command\n");
- + 		set_nor_flash_bank(cur_bank);
- + 		return 1;
- + 	}
- + 	printf ("%d (0x%08X) bytes\n", size, size);
- + 	/* get actual flash address */
- + 	faddr = CONFIG_SYS_FLASH_BASE+(KERNEL_FLASH_BANK*CONFIG_FLASH_CKB_BANK_SIZE);
- + 	/* copy the kernel image to the specified address */
- + 	temp_argv[0] = "cp.b";
- + 	/* The actual flash address */
- + 	sprintf(addr1, "%X", faddr);
- + 	temp_argv[1] = addr1;				/* source flash address */
- + 	temp_argv[2] = argv[1];				/* destination address */
- + 	sprintf(count, "%X", size);
- + 	temp_argv[3] = count;				/* count */
- + 	return do_mem_cp(cmdtp, flag, 4, temp_argv);
- + 	
- + usage:
- + 	cmd_usage(cmdtp);
- + 	return 1;
- + }
- + 
- + U_BOOT_CMD(
- + 	fread_kernel,   2,   0,  ckb_fread_kernel,
- + 	"Read Kernel binary (uImage) from NOR flash",
- + 	"addr\n    - Read Kernel from NOR Bank# "KERNEL_FLASH_BANK_STR":0x08000000 to SDRAM address 'addr'"
- + );
- + 
- + int ckb_flash_bootloader(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
- + {
- + 	ulong addr;
- + 	ulong size;
- + 	if(argc == 2) 
- + 	{
- + 		size = 0x2000;
- + 	}
- + 	else if(argc == 3)
- + 	{
- + 		size = simple_strtoul (argv[2], NULL, 16);
- + 	}
- + 	else
- + 	{
- + 		goto usage;
- + 	}
- + 	addr = simple_strtoul (argv[1], NULL, 16);
- + 	if(size > MAX_BOOTLOADER_FILE_SIZE)
- + 	{
- + 		printf ("Image size is %d (0x%08X) which is too large. Max allowed size = %d (0x%08X)\n", size, size, MAX_BOOTLOADER_FILE_SIZE, MAX_BOOTLOADER_FILE_SIZE);
- + 		return 1;
- + 	}
- + 	return erase_and_write(cmdtp, flag, "Bootloader", addr, 0, size);
- + 
- + usage:
- + 	cmd_usage(cmdtp);
- + 	return 1;
- + }
- + 
- + U_BOOT_CMD(
- + 	flash_bootloader,   3,   0,  ckb_flash_bootloader,
- + 	"Write bootloader binary to NOR flash",
- + 	"addr [len]\n    - Write Bootloader from SDRAM address 'addr' to NOR Bank# 0:0x08000000.\n       'len' is optional; the default value is 0x2000"
- + );
- + 
- + 
- + int ckb_flash_titleimage(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
- + {
- + 	ulong addr;
- + 	ulong size;
- + 	if(argc == 2) 
- + 	{
- + 		size = 0x40000;
- + 	}
- + 	else if(argc == 3)
- + 	{
- + 		size = simple_strtoul (argv[2], NULL, 16);
- + 	}
- + 	else
- + 	{
- + 		goto usage;
- + 	}
- + 	addr = simple_strtoul (argv[1], NULL, 16);
- + 	if(size > MAX_LCD_IMAGE_FILE_SIZE)
- + 	{
- + 		printf ("Image size is %d (0x%08X) which is too large. Max allowed size = %d (0x%08X)\n", size, size, MAX_LCD_IMAGE_FILE_SIZE, MAX_LCD_IMAGE_FILE_SIZE);
- + 		return 1;
- + 	}
- + 	return erase_and_write(cmdtp, flag, "LCD image", addr, 4, size);
- + 
- + usage:
- + 	cmd_usage(cmdtp);
- + 	return 1;
- + }
- + 
- + U_BOOT_CMD(
- + 	flash_titleimage,   3,   0,  ckb_flash_titleimage,
- + 	"Write title image to NOR flash",
- + 	"addr [len]\n    - Write title image from SDRAM address 'addr' to NOR Bank# 4:0x08000000.\n       'len' is optional; the default value is 0x40000"
- + );
- + 
- + #endif
- + 
- + 
- + 
- + 
- + 
- + 
- + 
- + 
- + 
- + 
- + 
- diff -crN u-boot-2012.10_o/board/computex/ckb-3352/lcd.c u-boot-2012.10/board/computex/ckb-3352/lcd.c
- *** u-boot-2012.10_o/board/computex/ckb-3352/lcd.c	1970-01-01 09:00:00.000000000 +0900
- --- u-boot-2012.10/board/computex/ckb-3352/lcd.c	2014-03-28 10:20:56.671121000 +0900
- ***************
- *** 0 ****
- --- 1,826 ----
- + /*
- +  * CKB board Display Logo source
- +  *
- +  * Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; either version 2 of the License, or
- +  * (at your option) any later version.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- +  */
- + #include <asm/arch/cpu.h>
- + #include <asm/arch/hardware.h>
- + #include <asm/arch/omap.h>
- + #include <asm/arch/ddr_defs.h>
- + #include <asm/arch/clock.h>
- + #include <asm/arch/gpio.h>
- + #include <asm/arch/mem.h>
- + #include <asm/arch/mmc_host_def.h>
- + #include <asm/arch/sys_proto.h>
- + #include <asm/io.h>
- + #include <asm/emif.h>
- + #include <asm/gpio.h>
- + #include <common.h>
- + #include <asm/omap_gpio.h>
- + 
- + DECLARE_GLOBAL_DATA_PTR;
- + #define HALF_IMAGE
- + 
- + char displaying_ckb_logo = 0;
- + 
- + #if defined(CONFIG_CKB_LCD_01) || defined(CONFIG_CKB_LCD_02) || defined(CONFIG_CKB_DVI)
- + 
- + /* donot optimize the code in this file */
- + //#pragma GCC optimize ("O0")
- + 
- + #define LCD_VERSION_1	1
- + #define LCD_VERSION_2	2
- + 
- + 
- + 
- + 
- + #define FB_PALETTE_SIZE					(16*2)				/* Palette size */
- + #define LCD_16_BPP_PALETTE				0x4000
- + #define FB_PALLET_ADDRESS				(CONFIG_FB_BASE_ADDRESS-FB_PALETTE_SIZE)
- + 
- + #define LCD_IN_CLK					300000000
- + 
- + /* LCD Status Register */
- + #define LCD_END_OF_FRAME1		BIT(9)
- + #define LCD_END_OF_FRAME0		BIT(8)
- + #define LCD_PL_LOAD_DONE		BIT(6)
- + #define LCD_FIFO_UNDERFLOW		BIT(5)
- + #define LCD_SYNC_LOST			BIT(2)
- + 
- + /* LCD DMA Control Register */
- + #define LCD_DMA_BURST_SIZE(x)		((x) << 4)
- + #define LCD_DMA_BURST_1			0x0
- + #define LCD_DMA_BURST_2			0x1
- + #define LCD_DMA_BURST_4			0x2
- + #define LCD_DMA_BURST_8			0x3
- + #define LCD_DMA_BURST_16		0x4
- + #define LCD_V1_END_OF_FRAME_INT_ENA	BIT(2)
- + #define LCD_V2_END_OF_FRAME0_INT_ENA	BIT(8)
- + #define LCD_V2_END_OF_FRAME1_INT_ENA	BIT(9)
- + #define LCD_DUAL_FRAME_BUFFER_ENABLE	BIT(0)
- + 
- + /* LCD Control Register */
- + #define LCD_CLK_DIVISOR(x)		((x) << 8)
- + #define LCD_RASTER_MODE			0x01
- + 
- + /* LCD Raster Control Register */
- + #define LCD_PALETTE_LOAD_MODE(x)	((x) << 20)
- + #define PALETTE_AND_DATA		0x00
- + #define PALETTE_ONLY			0x01
- + #define DATA_ONLY			0x02
- + 
- + #define LCD_MONO_8BIT_MODE		BIT(9)
- + #define LCD_RASTER_ORDER		BIT(8)
- + #define LCD_TFT_MODE			BIT(7)
- + #define LCD_V1_UNDERFLOW_INT_ENA	BIT(6)
- + #define LCD_V2_UNDERFLOW_INT_ENA	BIT(5)
- + #define LCD_V1_PL_INT_ENA		BIT(4)
- + #define LCD_V2_PL_INT_ENA		BIT(6)
- + #define LCD_MONOCHROME_MODE		BIT(1)
- + #define LCD_RASTER_ENABLE		BIT(0)
- + #define LCD_TFT_ALT_ENABLE		BIT(23)
- + #define LCD_STN_565_ENABLE		BIT(24)
- + #define LCD_V2_DMA_CLK_EN		BIT(2)
- + #define LCD_V2_LIDD_CLK_EN		BIT(1)
- + #define LCD_V2_CORE_CLK_EN		BIT(0)
- + #define LCD_V2_LPP_B10			26
- + #define LCD_V2_TFT_24BPP_MODE		BIT(25)
- + #define LCD_V2_TFT_24BPP_UNPACK		BIT(26)
- + 
- + /* LCD Raster Timing 2 Register */
- + #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x)	((x) << 16)
- + #define LCD_AC_BIAS_FREQUENCY(x)		((x) << 8)
- + #define LCD_SYNC_CTRL				BIT(25)
- + #define LCD_SYNC_EDGE				BIT(24)
- + #define LCD_INVERT_PIXEL_CLOCK			BIT(22)
- + #define LCD_INVERT_LINE_CLOCK			BIT(21)
- + #define LCD_INVERT_FRAME_CLOCK			BIT(20)
- + 
- + /* LCD Block */
- + #define  LCD_PID_REG				0x0
- + #define  LCD_CTRL_REG				0x4
- + #define  LCD_STAT_REG				0x8
- + #define  LCD_RASTER_CTRL_REG			0x28
- + #define  LCD_RASTER_TIMING_0_REG		0x2C
- + #define  LCD_RASTER_TIMING_1_REG		0x30
- + #define  LCD_RASTER_TIMING_2_REG		0x34
- + #define  LCD_DMA_CTRL_REG			0x40
- + #define  LCD_DMA_FRM_BUF_BASE_ADDR_0_REG	0x44
- + #define  LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG	0x48
- + #define  LCD_DMA_FRM_BUF_BASE_ADDR_1_REG	0x4C
- + #define  LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG	0x50
- + 
- + /* Interrupt Registers available only in Version 2 */
- + #define  LCD_RAW_STAT_REG			0x58
- + #define  LCD_MASKED_STAT_REG			0x5c
- + #define  LCD_INT_ENABLE_SET_REG			0x60
- + #define  LCD_INT_ENABLE_CLR_REG			0x64
- + #define  LCD_END_OF_INT_IND_REG			0x68
- + 
- + /* Clock registers available only on Version 2 */
- + #define  LCD_CLK_ENABLE_REG			0x6c
- + #define  LCD_CLK_RESET_REG			0x70
- + #define  LCD_CLK_MAIN_RESET			BIT(3)
- + 
- + #define GPIO_DISP_POWER				7		/* lcd power GPIO3[7] */
- + #define GPIO_BACKLIGHT_POWER		8		/* lcd backlight  GPIO3[8] */
- + /* TPS for backlight */
- + #define GPIO_TPS_BACKLIGHT			19	/* lcd backlight TPS power GPIO3[19] */
- + 
- + #if defined(CONFIG_CKB_LCD_01) && defined(CONFIG_CKB_LCD_02)
- + Error "Only one LCD type can be defined" 
- + #endif
- + 
- + struct da8xx_panel *g_lcdpanel;
- + 
- + struct da8xx_panel {
- + 	char *name;
- + 	unsigned short	width;
- + 	unsigned short	height;
- + 	int		hfp;		/* Horizontal front porch */
- + 	int		hbp;		/* Horizontal back porch */
- + 	int		hsw;		/* Horizontal Sync Pulse Width */
- + 	int		vfp;		/* Vertical front porch */
- + 	int		vbp;		/* Vertical back porch */
- + 	int		vsw;		/* Vertical Sync Pulse Width */
- + 	unsigned int	pxl_clk;	/* Pixel clock */
- + 	unsigned char	invert_pxl_clk;	/* Invert Pixel clock */
- + 	int bpp;
- + 	int dma_burst_sz;
- + 	int fifo_th;
- + 	int fdd;			/* FIFO DMA delay */
- + 	int ac_bias;
- + 	int ac_bias_intrpt;
- + 	int sync_ctrl;				/* sync control */
- + 	int sync_edge;				/* sync edge */
- + 	int invert_line_clock;			/* invert line clock */
- + 	int invert_frm_clock;			/* invert frame clock */
- + };
- + 
- + #ifdef CONFIG_CKB_LCD_01
- + struct da8xx_panel VisionxKTM050AL02 = {
- + 		/* Visionx KTM050AL02 */
- + 		.name = "Visionx KTM050AL02",
- + 		.width = 800,
- + 		.height = 480,
- + 		.hfp = 40,
- + 		.hbp = 40,
- + 		.hsw = 48,
- + 		.vfp = 13,
- + 		.vbp = 29,
- + 		.vsw = 3,
- + 		.pxl_clk = 33000000,
- + 		.invert_pxl_clk = 0,
- + 		.dma_burst_sz = 16,
- + 		.fifo_th = 6,
- + 		.bpp = 16,
- + 		.fdd = 255,
- + 		.ac_bias		= 255,
- + 		.ac_bias_intrpt		= 0,
- + 		.sync_ctrl = 1,
- + 		.sync_edge = 0,
- + 		.invert_line_clock = 1, 
- + 		.invert_frm_clock = 1,
- + };
- + #endif
- + #ifdef CONFIG_CKB_LCD_02
- + struct da8xx_panel KyoceraTCG070WVLPAAFA_AA00 = {
- + 		/* Kyocera TCG070WVLPAAFA_AA00 */
- + 		.name = "Kyocera TCG070WVLPAAFA_AA00",
- + 		.width = 800,
- + 		.height = 480,
- + 		.hfp = 40,			/* right_margin */
- + 		.hbp = 88,			/* left_margin */
- + 		.hsw = 128,			/* hsync_len */
- + 		.vfp = 11,			/* lower_margin */
- + 		.vbp = 32,			/* upper_margin */
- + 		.vsw = 2,			/* vsync_len */
- + 		.pxl_clk = 33200000,
- + 		.invert_pxl_clk = 0,
- + 		.dma_burst_sz = 16,
- + 		.fifo_th = 6,
- + 		.bpp = 16,
- + 		.fdd = 255,
- + 		.ac_bias		= 255,
- + 		.ac_bias_intrpt		= 0,
- + 		.sync_ctrl = 1,
- + 		.sync_edge = 0,
- + 		.invert_line_clock = 1, 
- + 		.invert_frm_clock = 1,
- + };
- + #endif
- + #if !defined(CONFIG_CKB_LCD_01) && !defined(CONFIG_CKB_LCD_02)
- + struct da8xx_panel generic_DVI_monitor = {
- + 		/* Generic DVI monitor (This setting works for most monitors) */
- + 		.name = "Generic DVI panel",
- + 		.width = 800,
- + 		.height = 480,
- + 		.hfp = 40,
- + 		.hbp = 40,
- + 		.hsw = 48,
- + 		.vfp = 13,
- + 		.vbp = 29,
- + 		.vsw = 3,
- + 		.pxl_clk = 33000000,
- + 		.invert_pxl_clk = 0,
- + 		.dma_burst_sz = 16,
- + 		.fifo_th = 6,
- + 		.bpp = 16,
- + 		.fdd = 255,
- + 		.ac_bias		= 255,
- + 		.ac_bias_intrpt		= 0,
- + 		.sync_ctrl = 1,
- + 		.sync_edge = 0,
- + 		.invert_line_clock = 1, 
- + 		.invert_frm_clock = 1,
- + };
- + #endif
- + 
- + static unsigned int lcd_revision;
- + 
- + inline unsigned int lcdc_read(unsigned int addr)
- + {
- + 	return __raw_readl(DA8XX_LCD_CNTRL_BASE + (addr));
- + }
- + 
- + inline void lcdc_write(unsigned int val, unsigned int addr)
- + {
- + 	__raw_writel(val, DA8XX_LCD_CNTRL_BASE + (addr));
- + }
- + 
- + /* Enable the Raster Engine of the LCD Controller */
- + inline void lcd_enable_raster(void)
- + {
- + 	u32 reg;
- + 
- + 	/* Put LCDC in reset for several cycles */
- + 	if (lcd_revision == LCD_VERSION_2)
- + 	{
- + 		lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
- + 		mdelay(1);
- + 	
- + 		/* Bring LCDC out of reset */
- + 		lcdc_write(0, LCD_CLK_RESET_REG);
- + 		mdelay(1);
- + 	}
- + 
- + 	/* Above reset sequence doesnot reset register context */
- + 	reg = lcdc_read(LCD_RASTER_CTRL_REG);
- + 	if (!(reg & LCD_RASTER_ENABLE))
- + 		lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
- + }
- + 
- + /* Disable the Raster Engine of the LCD Controller */
- + inline void lcd_disable_raster()
- + {
- + 	lcdc_write(lcdc_read(LCD_RASTER_CTRL_REG) & (~LCD_RASTER_ENABLE), LCD_RASTER_CTRL_REG);
- + 	/* there is not need to wait */
- + }
- + 
- + 
- + void lcd_fb_addr()
- + {
- + 	/* single FB mode and interrupt disable */
- + 	if (lcd_revision == LCD_VERSION_1) 
- + 	{
- + 		/* single FB mode and interrupt disable */
- + 		lcdc_write(lcdc_read(LCD_DMA_CTRL_REG) & 
- + 					~(LCD_V1_END_OF_FRAME_INT_ENA|LCD_DUAL_FRAME_BUFFER_ENABLE),
- + 				 LCD_DMA_CTRL_REG);
- + 	
- + 		/* palette and data */
- + 		/* fill FB0 address register */
- + 		lcdc_write(FB_PALLET_ADDRESS, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
- + 		lcdc_write(FB_PALLET_ADDRESS+(g_lcdpanel->height*g_lcdpanel->width)*2+FB_PALETTE_SIZE-2,
- + 						 LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
- + #if 0
- + 		lcdc_write(FB_PALLET_ADDRESS, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
- + 		lcdc_write(FB_PALLET_ADDRESS+(g_lcdpanel->height*g_lcdpanel->width)*2+FB_PALETTE_SIZE-2,
- + 						 LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
- + #endif
- + 		/* load palette and data */
- + 		lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & ~(3<<20))
- + 						| LCD_PALETTE_LOAD_MODE(PALETTE_AND_DATA), 
- + 							LCD_RASTER_CTRL_REG);
- + 	}
- + 	else
- + 	{
- + 		/* single FB mode */
- + 		lcdc_write(lcdc_read(LCD_DMA_CTRL_REG) & 
- + 					~(LCD_DUAL_FRAME_BUFFER_ENABLE),
- + 				 LCD_DMA_CTRL_REG);
- + 		lcdc_write(lcdc_read(LCD_INT_ENABLE_SET_REG) &
- + 				~(LCD_V2_END_OF_FRAME0_INT_ENA | LCD_V2_END_OF_FRAME1_INT_ENA
- + 				| LCD_V2_UNDERFLOW_INT_ENA | LCD_SYNC_LOST),
- + 				LCD_INT_ENABLE_SET_REG);
- + 					 
- + 		/* data only */
- + 		/* fill FB0 address register */
- + 		lcdc_write(CONFIG_FB_BASE_ADDRESS, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
- + 		lcdc_write(CONFIG_FB_BASE_ADDRESS+(g_lcdpanel->height*g_lcdpanel->width)*2-2,
- + 					 LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
- + #if 0
- + 		lcdc_write(CONFIG_FB_BASE_ADDRESS, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
- + 		lcdc_write(CONFIG_FB_BASE_ADDRESS+(g_lcdpanel->height*g_lcdpanel->width)*2-2,
- + 						 LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
- + #endif
- + 		/* load data */
- + 		lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & ~(3<<20))
- + 					| LCD_PALETTE_LOAD_MODE(DATA_ONLY), 
- + 					LCD_RASTER_CTRL_REG);
- + 	}
- + 	
- + }
- + 
- + /* Configure the Burst Size and fifo threhold of DMA */
- + void lcd_cfg_dma(int burst_size,  int fifo_th)
- + {
- + 	u32 reg;
- + 
- + 	reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001;
- + 	switch (burst_size) {
- + 	case 1:
- + 		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
- + 		break;
- + 	case 2:
- + 		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
- + 		break;
- + 	case 4:
- + 		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
- + 		break;
- + 	case 8:
- + 		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
- + 		break;
- + 	case 16:
- + 		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
- + 		break;
- + 	}
- + 
- + 	reg |= (fifo_th << 8);
- + 
- + 	lcdc_write(reg, LCD_DMA_CTRL_REG);
- + }
- + 
- + void lcd_cfg_ac_bias(int period, int transitions_per_int)
- + {
- + 	u32 reg;
- + 
- + 	/* Set the AC Bias Period and Number of Transisitons per Interrupt */
- + 	reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000;
- + 	reg |= LCD_AC_BIAS_FREQUENCY(period) |
- + 		LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
- + 	lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
- + }
- + 
- + void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
- + 		int front_porch)
- + {
- + 	u32 reg;
- + 	
- + 	/* fill low bits */
- + 	reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0x3ff;
- + 	reg |= ((back_porch & 0xff) << 24)
- + 	    | ((front_porch & 0xff) << 16)
- + 	    | ((pulse_width & 0x3f) << 10);
- + 	lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
- + 
- + 	/* fill high bits */
- + 	reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0x07ffff00;
- + 	reg |= (((back_porch & 0x300)>>8) << 4)
- + 	    | (((front_porch & 0x300)>>8))
- + 	    | (((pulse_width & 0x3C0)>>6) << 27);
- + 	lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
- + }
- + 
- + void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
- + 		int front_porch)
- + {
- + 	u32 reg;
- + 	reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff;
- + 	reg |= ((back_porch & 0xff) << 24)
- + 	    | ((front_porch & 0xff) << 16)
- + 	    | ((pulse_width & 0x3f) << 10);
- + 	lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
- + }
- + 
- + void lcd_cfg_display(void)
- + {
- + 	u32 reg;
- + 
- + 	reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE |
- + 						LCD_MONO_8BIT_MODE |
- + 						LCD_MONOCHROME_MODE);
- + 
- + 	/* MONOCHROME *
- + 	reg |= LCD_MONOCHROME_MODE; */
- + 	/* COLOR_ACTIVE */
- + 	reg |= LCD_TFT_MODE;
- + 	/* COLOR_PASSIVE */
- + 		
- + 	/* enable additional interrupts here */
- + 	//reg |= LCD_V1_UNDERFLOW_INT_ENA;
- + 
- + 	lcdc_write(reg, LCD_RASTER_CTRL_REG);
- + 
- + 	reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
- + 
- + 	if (g_lcdpanel->sync_ctrl)
- + 		reg |= LCD_SYNC_CTRL;
- + 	else
- + 		reg &= ~LCD_SYNC_CTRL;
- + 
- + 	if (g_lcdpanel->sync_edge)
- + 		reg |= LCD_SYNC_EDGE;
- + 	else
- + 		reg &= ~LCD_SYNC_EDGE;
- + 
- + 	if (g_lcdpanel->invert_line_clock)
- + 		reg |= LCD_INVERT_LINE_CLOCK;
- + 	else
- + 		reg &= ~LCD_INVERT_LINE_CLOCK;
- + 
- + 	if (g_lcdpanel->invert_frm_clock)
- + 		reg |= LCD_INVERT_FRAME_CLOCK;
- + 	else
- + 		reg &= ~LCD_INVERT_FRAME_CLOCK;
- + 
- + 	lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
- + }
- + 
- + void lcd_cfg_frame_buffer(u32 width, u32 height, u32 raster_order)
- + {
- + 	u32 reg;
- + 
- + 	/* Set the Panel Width */
- + 	/* Pixels per line = (PPL + 1)*16 */
- + 	if (lcd_revision == LCD_VERSION_1) {
- + 		/*
- + 		 * 0x3F in bits 4..9 gives max horizontal resolution = 1024
- + 		 * pixels.
- + 		 */
- + 		width &= 0x3f0;
- + 	} else {
- + 		/*
- + 		 * 0x7F in bits 4..10 gives max horizontal resolution = 2048
- + 		 * pixels.
- + 		 */
- + 		width &= 0x7f0;
- + 	}
- + 
- + 	reg = lcdc_read(LCD_RASTER_TIMING_0_REG);
- + 	reg &= 0xfffffc00;
- + 	if (lcd_revision == LCD_VERSION_1) {
- + 		reg |= ((width >> 4) - 1) << 4;
- + 	} else {
- + 		width = (width >> 4) - 1;
- + 		reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
- + 	}
- + 	lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
- + 
- + 	/* Set the Panel Height */
- + 	/* Set bits 9:0 of Lines Per Pixel */
- + 	reg = lcdc_read(LCD_RASTER_TIMING_1_REG);
- + 	reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
- + 	lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
- + 
- + 	/* Set bit 10 of Lines Per Pixel */
- + 	if (lcd_revision == LCD_VERSION_2) {
- + 		reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
- + 		reg |= ((height - 1) & 0x400) << 16;
- + 		lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
- + 	}
- + 
- + 	/* Set the Raster Order of the Frame Buffer */
- + 	reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);
- + 	if (raster_order)
- + 		reg |= LCD_RASTER_ORDER;
- + 	lcdc_write(reg, LCD_RASTER_CTRL_REG);
- + }
- + 
- + 
- + static void lcd_calc_clk_divider(unsigned int clk)
- + {
- + #if 1
- + 
- + /* try to get a good value by calculating the best PLL clock and divider */
- + 	volatile int best_divider;
- + 	volatile int output_clock;
- + 	volatile int best_difference = 0xffffffff;
- + 	volatile int i, div;
- + 	volatile int difference;
- + 	volatile int dpll_clock;
- + 	volatile int dpll_divider;
- + 	/* check to see if the exact divider or divider+1 will give a nearest value */
- + 	/* The only way to get the precise clock is to alter DPLL clock */ 
- + 	/* check the CM_DIV_M2_DPLL_DISP Register */
- + 	int orig_rate = LCD_IN_CLK;
- + 	volatile int found = 0;
- + 	for(i=1; i<=1; i++)
- + 	{
- + 		dpll_clock = orig_rate/i;
- + 		
- + 		/* calculate upper difference; the clock obtained here will be faster than what is requested */
- + 		div = dpll_clock / clk;
- + 		if(div>1)
- + 		{
- + 			output_clock = dpll_clock / div;
- + 			difference = output_clock - clk;
- + 			if(output_clock - clk <= best_difference)
- + 			{
- + 				best_difference = difference;
- + 				best_divider = div;
- + 				dpll_divider = i;
- + 				found = 1;
- + 			}
- + 		}
- + 		if(div>0)
- + 		{
- + 			/* calculate lower difference; the clock obtained here will be slower than what is requested */
- + 			output_clock = dpll_clock / (div+1);
- + 			difference = clk - output_clock;
- + 			if(clk - output_clock <= best_difference)
- + 			{
- + 				best_difference = difference;
- + 				best_divider = div+1;
- + 				dpll_divider = i;
- + 				found = 1;
- + 			}
- + 		}
- + 	}
- + 	if(found)
- + 	{
- + 		div = best_divider;
- + //		par->pxl_clk = best_output_clock;
- + 	}
- + 	else
- + 	{
- + 		div = orig_rate / clk;
- + 	}
- + 	//printf("****div=%d, dpll_divider=%d", div, dpll_divider);
- + #else
- + 	/* LCD controller used PLL0_sysclk2 */
- + 	unsigned int lcd_clk, div;
- + 	lcd_clk = LCD_IN_CLK;
- + 
- + 	div = lcd_clk / clk;
- + #endif
- + 	
- + 	/* Configure the LCD clock divisor. */
- + 	lcdc_write(LCD_CLK_DIVISOR(div) |
- + 			(LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);
- + 
- + 	if (lcd_revision == LCD_VERSION_2)
- + 		lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
- + 				LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG);
- + }
- + 
- + void da850_lcd_gpio_init(void)
- + {
- + #if defined(CONFIG_CKB_LCD_01) || defined(CONFIG_CKB_LCD_02)
- + 	/* GPIO as output */
- + 	void *reg = omap_gpio_bank[3].base + OMAP_GPIO_OE;
- + 	__raw_writel((__raw_readl(reg) & ~((1<<GPIO_DISP_POWER)
- + 								| (1<<GPIO_BACKLIGHT_POWER)
- + 								| (1<<GPIO_TPS_BACKLIGHT)))	, reg);
- + #endif	
- + 	/* GPIO8[10] -> Donot use LCD_MCLK *
- + 	ckb_gpio_bank[3]->dir &= ~(1<<10); */
- + #if 0
- + 	/* configure interrupt trigger */
- + 	ckb_gpio_bank01->set_rising |= (1<<GPIO_DISP_POWER);
- + 	ckb_gpio_bank01->set_falling |= (1<<GPIO_DISP_POWER);
- + 	ckb_gpio_bank01->set_rising |= (1<<GPIO_BACKLIGHT_POWER);
- + 	ckb_gpio_bank01->set_falling |= (1<<GPIO_BACKLIGHT_POWER);
- + #endif
- + }
- + 
- + void da850_backlight_power_ctrl(int val)
- + {
- + 	void *reg = omap_gpio_bank[3].base + OMAP_GPIO_DATAOUT;
- + 	if(!val)
- + 	{
- + 		/* switch off */
- + 		__raw_writel((__raw_readl(reg) & ~((1<<GPIO_BACKLIGHT_POWER)
- + 										| (1<<GPIO_TPS_BACKLIGHT))), reg);
- + 	}
- + 	else
- + 	{
- + 		/* switch on */
- + 		__raw_writel((__raw_readl(reg) | ((1<<GPIO_BACKLIGHT_POWER)
- + 										| (1<<GPIO_TPS_BACKLIGHT))), reg);
- + 	}
- + }
- + 
- + void da850_panel_power_ctrl(int val)
- + {
- + #if defined(CONFIG_CKB_LCD_01) || defined(CONFIG_CKB_LCD_02)
- + 	void *reg = omap_gpio_bank[3].base + OMAP_GPIO_DATAOUT;
- + 	/* lcd power GPIO2[8] */
- + 	if(!val)
- + 		/* switch off */
- + 		__raw_writel((__raw_readl(reg) & ~(1<<GPIO_DISP_POWER)), reg);
- + 	else
- + 		/* switch on */
- + 		__raw_writel((__raw_readl(reg) | (1<<GPIO_DISP_POWER)), reg);
- + #endif
- + }
- + 
- + 
- + #ifdef HALF_IMAGE
- + void scaleImage_x_2(int image_width, int image_height, unsigned short *src_addr, unsigned short *dest_addr)
- + {
- + 	/* The image need to be scaled 2 times;
- + 	   Write the same value to the adjascent pixel
- + 	   Replicate the line */ 
- + 	int i, j;
- + 	for(i=0; i<image_height; i++)
- + 	{
- + #if 0
- + 		int l;
- + 		for(l=0; l<2; l++)			/* replicate the line again */
- + 		{
- + 			for(j=0; j<image_width; j++)
- + 			{
- + 				*dest_addr++ = *(src_addr+j);
- + 				*dest_addr++ = *(src_addr+j);
- + 			}
- + 		}
- + 		s_dest += j;
- + #else
- + 		for(j=0; j<image_width; j++)
- + 		{
- + 			/* fill 2 pixels and the next line */
- + 			*dest_addr = *(dest_addr+1) = *(dest_addr+g_lcdpanel->width) = *(dest_addr+(g_lcdpanel->width+1)) = *(src_addr+j);
- + 			dest_addr+=2;	/* increment pixels by 2 */		
- + 		}
- + 		src_addr += j;
- + 		dest_addr+=g_lcdpanel->width; /* move to the line after the next line */
- + #endif
- + 	}
- + }
- + #endif
- + 		
- + int fill_logo_from_flash(unsigned long address, unsigned char *dest_addr)
- + {
- + 	int read_size;
- + #ifdef HALF_IMAGE
- + 	unsigned char *orig_dest = dest_addr;
- + 	int half_width = g_lcdpanel->width/2;
- + 	int half_height = g_lcdpanel->height/2;
- + 	read_size = half_width*half_height*2;
- + 	/* move to the end of the FB and use it as temp address */
- + 	dest_addr = dest_addr+(g_lcdpanel->width*g_lcdpanel->height*2);
- + #else
- + 	read_size = g_lcdpanel->width*g_lcdpanel->height*2;
- + #endif
- + 	/* read image from NOR flash */
- + 	char *temp_argv[4];
- + 	char addr1[16], addr2[16], size[16];
- + 	sprintf(addr1, "%X", address);
- + 	sprintf(addr2, "%X", dest_addr);
- + 	sprintf(size, "%X", read_size);
- + 	temp_argv[0] = "cp.b";
- + 	temp_argv[1] = addr1;				/* source flash address */
- + 	temp_argv[2] = addr2;				/* destination address */
- + 	temp_argv[3] = size;				/* count */
- + 	
- + 	displaying_ckb_logo = 1;
- + 	/* set the start of the command table as the first paramater; 
- + 	This is not OK, but since the parameters are valid, it's ok :-) */
- + 	if(!do_mem_cp(&__u_boot_cmd_start, 0, 4, temp_argv))
- + 	{
- + #ifdef HALF_IMAGE
- + 		scaleImage_x_2(half_width, half_height, dest_addr, orig_dest);
- + #endif
- + 	}
- + 	displaying_ckb_logo = 0;
- + 
- + 	return 0;
- + }
- + 
- + void init_lcd(void)
- + {
- + 	/* init display pll */
- + 	disp_pll_config();
- + 	/* initialize GPIO */
- + 	da850_lcd_gpio_init();
- + 
- + 	/* Determine LCD IP Version */
- + 	switch (lcdc_read(LCD_PID_REG)) {
- + 	case 0x4C100102:
- + 		lcd_revision = LCD_VERSION_1;
- + 		//printf("LCD revision 1\n");
- + 		break;
- + 	case 0x4F200800:
- + 	case 0x4F201000:
- + 		lcd_revision = LCD_VERSION_2;
- + 		//printf("LCD revision 2\n");
- + 		break;
- + 	default:
- + 		printf("Unknown PID Reg value 0x%x, "
- + 				"defaulting to LCD revision 1\n",
- + 				lcdc_read(LCD_PID_REG));
- + 		lcd_revision = LCD_VERSION_1;
- + 		break;
- + 	}
- + 
- + 	/* disable raster */
- + 	lcd_disable_raster();
- + 
- + 	if(lcd_revision == LCD_VERSION_1)
- + 	{
- + 		/* set palette: For 16BPP, the 0th entry in the Palette should be 0x4000 and all other 
- + 	   	   entries must be 0 */
- + 		*(unsigned short *)FB_PALLET_ADDRESS = LCD_16_BPP_PALETTE;
- + 		memset(FB_PALLET_ADDRESS+2, 0, FB_PALETTE_SIZE-2);
- + 	}
- + 	
- + 
- + 
- + 	/* clear status register */
- + 	//printf("Status=%X\n", lcdc_read(LCD_STAT_REG));
- + 	lcdc_write(lcdc_read(LCD_STAT_REG), LCD_STAT_REG);
- + 
- +     /* init clock */
- + 	lcd_calc_clk_divider(g_lcdpanel->pxl_clk);
- + 	/* configure registers */
- + 	/* timing */
- + 	lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) &
- + 			~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
- + 	/* burst size */
- + 	lcd_cfg_dma(g_lcdpanel->dma_burst_sz, g_lcdpanel->fifo_th);
- + 	/* AC bias */
- + 	lcd_cfg_ac_bias(g_lcdpanel->ac_bias, g_lcdpanel->ac_bias_intrpt);
- + 	/* vertical and horizontal sync properties */
- + 	lcd_cfg_vertical_sync(g_lcdpanel->vbp, g_lcdpanel->vsw, g_lcdpanel->vfp);
- + 	lcd_cfg_horizontal_sync(g_lcdpanel->hbp, g_lcdpanel->hsw, g_lcdpanel->hfp);
- + 	lcd_cfg_display();
- + 	lcd_cfg_frame_buffer(g_lcdpanel->width, g_lcdpanel->height, 0);
- + 	/* FIFO DMA delay */
- + 	lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) |
- + 		       (g_lcdpanel->fdd << 12), LCD_RASTER_CTRL_REG);
- + 
- + 	lcd_fb_addr();
- + 
- + 	/* enable raster */
- + 	lcd_enable_raster();
- + 
- + 	/* Let the controller take it's own time to display the image */
- + 	//while(!(lcdc_read(LCD_STAT_REG) & LCD_END_OF_FRAME0));
- + 
- + 	/* turn on LCD power */
- + 	da850_panel_power_ctrl(1);
- + }
- + 
- + void enable_backlight()
- + {
- + 	da850_backlight_power_ctrl(1);
- + }
- + 
- + void init_lcd_and_display_logo()
- + {
- + 	/* LCD panel to use */
- + #ifdef CONFIG_CKB_LCD_01
- + 	g_lcdpanel = &VisionxKTM050AL02;
- + #endif
- + #ifdef CONFIG_CKB_LCD_02
- + 	g_lcdpanel = &KyoceraTCG070WVLPAAFA_AA00;
- + #endif
- + #if !defined(CONFIG_CKB_LCD_01) && !defined(CONFIG_CKB_LCD_02)
- + 	g_lcdpanel = &generic_DVI_monitor;
- + #endif		
- + 
- + 	printf("LCD panel: %s\n", g_lcdpanel->name);
- + 	printf("FB allocated @ 0x%X\n", CONFIG_FB_BASE_ADDRESS);
- + 	gd->fb_base = CONFIG_FB_BASE_ADDRESS;
- + 
- + 	fill_logo_from_flash(LCD_IMAGE_ADDRESS, CONFIG_FB_BASE_ADDRESS);
- + 	
- + 	init_lcd();
- + #if defined(CONFIG_CKB_LCD_01) || defined(CONFIG_CKB_LCD_02)
- + 	enable_backlight();
- + #endif
- + #if defined(CONFIG_CKB_DVI)
- + 	init_tfp410();
- + #endif
- + }
- + #else
- + void init_lcd_and_display_logo()
- + {
- + 	printf("LCD panel: None\n");
- + }
- + #endif
- diff -crN u-boot-2012.10_o/board/computex/ckb-3352/Makefile u-boot-2012.10/board/computex/ckb-3352/Makefile
- *** u-boot-2012.10_o/board/computex/ckb-3352/Makefile	1970-01-01 09:00:00.000000000 +0900
- --- u-boot-2012.10/board/computex/ckb-3352/Makefile	2014-03-19 14:23:40.491830000 +0900
- ***************
- *** 0 ****
- --- 1,43 ----
- + #
- + # Makefile
- + #
- + # Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
- + #
- + # This program is free software; you can redistribute it and/or
- + # modify it under the terms of the GNU General Public License as
- + # published by the Free Software Foundation; either version 2 of
- + # the License, or (at your option) any later version.
- + #
- + # This program is distributed "as is" WITHOUT ANY WARRANTY of any
- + # kind, whether express or implied; without even the implied warranty
- + # of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- + # GNU General Public License for more details.
- + #
- + 
- + include $(TOPDIR)/config.mk
- + 
- + LIB	= $(obj)lib$(BOARD).o
- + 
- + COBJS	:= mux.o cmd_custom.o lcd.o tfp410.o
- + 
- + SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
- + OBJS	:= $(addprefix $(obj),$(COBJS))
- + SOBJS	:= $(addprefix $(obj),$(SOBJS))
- + 
- + $(LIB):	$(obj).depend $(OBJS) $(SOBJS)
- + 	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
- + 
- + clean:
- + 	rm -f $(SOBJS) $(OBJS)
- + 
- + distclean:	clean
- + 	rm -f $(LIB) core *.bak $(obj).depend
- + 
- + #########################################################################
- + 
- + # defines $(obj).depend target
- + include $(SRCTREE)/rules.mk
- + 
- + sinclude $(obj).depend
- + 
- + #########################################################################
- diff -crN u-boot-2012.10_o/board/computex/ckb-3352/mux.c u-boot-2012.10/board/computex/ckb-3352/mux.c
- *** u-boot-2012.10_o/board/computex/ckb-3352/mux.c	1970-01-01 09:00:00.000000000 +0900
- --- u-boot-2012.10/board/computex/ckb-3352/mux.c	2014-02-27 11:33:16.781140652 +0900
- ***************
- *** 0 ****
- --- 1,418 ----
- + /*
- +  * mux.c
- +  *
- +  * Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #include <common.h>
- + #include <asm/arch/sys_proto.h>
- + #include <asm/arch/hardware.h>
- + #include <asm/io.h>
- + #include <i2c.h>
- + 
- + #define MUX_CFG(value, offset)	\
- + 	__raw_writel(value, (CTRL_BASE + offset));
- + 
- + /* PAD Control Fields */
- + #define SLEWCTRL	(0x1 << 6)
- + #define RXACTIVE	(0x1 << 5)
- + #define PULLUP_EN	(0x1 << 4) /* Pull UP Selection */
- + #define PULLUDEN	(0x0 << 3) /* Pull up enabled */
- + #define PULLUDDIS	(0x1 << 3) /* Pull up disabled */
- + #define MODE(val)	val	/* used for Readability */
- + 
- + /*
- +  * PAD CONTROL OFFSETS
- +  * Field names corresponds to the pad signal name
- +  */
- + struct pad_signals {
- + 	int gpmc_ad0;
- + 	int gpmc_ad1;
- + 	int gpmc_ad2;
- + 	int gpmc_ad3;
- + 	int gpmc_ad4;
- + 	int gpmc_ad5;
- + 	int gpmc_ad6;
- + 	int gpmc_ad7;
- + 	int gpmc_ad8;
- + 	int gpmc_ad9;
- + 	int gpmc_ad10;
- + 	int gpmc_ad11;
- + 	int gpmc_ad12;
- + 	int gpmc_ad13;
- + 	int gpmc_ad14;
- + 	int gpmc_ad15;
- + 	int gpmc_a0;
- + 	int gpmc_a1;
- + 	int gpmc_a2;
- + 	int gpmc_a3;
- + 	int gpmc_a4;
- + 	int gpmc_a5;
- + 	int gpmc_a6;
- + 	int gpmc_a7;
- + 	int gpmc_a8;
- + 	int gpmc_a9;
- + 	int gpmc_a10;
- + 	int gpmc_a11;
- + 	int gpmc_wait0;
- + 	int gpmc_wpn;
- + 	int gpmc_be1n;
- + 	int gpmc_csn0;
- + 	int gpmc_csn1;
- + 	int gpmc_csn2;
- + 	int gpmc_csn3;
- + 	int gpmc_clk;
- + 	int gpmc_advn_ale;
- + 	int gpmc_oen_ren;
- + 	int gpmc_wen;
- + 	int gpmc_be0n_cle;
- + 	int lcd_data0;
- + 	int lcd_data1;
- + 	int lcd_data2;
- + 	int lcd_data3;
- + 	int lcd_data4;
- + 	int lcd_data5;
- + 	int lcd_data6;
- + 	int lcd_data7;
- + 	int lcd_data8;
- + 	int lcd_data9;
- + 	int lcd_data10;
- + 	int lcd_data11;
- + 	int lcd_data12;
- + 	int lcd_data13;
- + 	int lcd_data14;
- + 	int lcd_data15;
- + 	int lcd_vsync;
- + 	int lcd_hsync;
- + 	int lcd_pclk;
- + 	int lcd_ac_bias_en;
- + 	int mmc0_dat3;
- + 	int mmc0_dat2;
- + 	int mmc0_dat1;
- + 	int mmc0_dat0;
- + 	int mmc0_clk;
- + 	int mmc0_cmd;
- + 	int mii1_col;
- + 	int mii1_crs;
- + 	int mii1_rxerr;
- + 	int mii1_txen;
- + 	int mii1_rxdv;
- + 	int mii1_txd3;
- + 	int mii1_txd2;
- + 	int mii1_txd1;
- + 	int mii1_txd0;
- + 	int mii1_txclk;
- + 	int mii1_rxclk;
- + 	int mii1_rxd3;
- + 	int mii1_rxd2;
- + 	int mii1_rxd1;
- + 	int mii1_rxd0;
- + 	int rmii1_refclk;
- + 	int mdio_data;
- + 	int mdio_clk;
- + 	int spi0_sclk;
- + 	int spi0_d0;
- + 	int spi0_d1;
- + 	int spi0_cs0;
- + 	int spi0_cs1;
- + 	int ecap0_in_pwm0_out;
- + 	int uart0_ctsn;
- + 	int uart0_rtsn;
- + 	int uart0_rxd;
- + 	int uart0_txd;
- + 	int uart1_ctsn;
- + 	int uart1_rtsn;
- + 	int uart1_rxd;
- + 	int uart1_txd;
- + 	int i2c0_sda;
- + 	int i2c0_scl;
- + 	int mcasp0_aclkx;
- + 	int mcasp0_fsx;
- + 	int mcasp0_axr0;
- + 	int mcasp0_ahclkr;
- + 	int mcasp0_aclkr;
- + 	int mcasp0_fsr;
- + 	int mcasp0_axr1;
- + 	int mcasp0_ahclkx;
- + 	int xdma_event_intr0;
- + 	int xdma_event_intr1;
- + 	int nresetin_out;
- + 	int porz;
- + 	int nnmi;
- + 	int osc0_in;
- + 	int osc0_out;
- + 	int rsvd1;
- + 	int tms;
- + 	int tdi;
- + 	int tdo;
- + 	int tck;
- + 	int ntrst;
- + 	int emu0;
- + 	int emu1;
- + 	int osc1_in;
- + 	int osc1_out;
- + 	int pmic_power_en;
- + 	int rtc_porz;
- + 	int rsvd2;
- + 	int ext_wakeup;
- + 	int enz_kaldo_1p8v;
- + 	int usb0_dm;
- + 	int usb0_dp;
- + 	int usb0_ce;
- + 	int usb0_id;
- + 	int usb0_vbus;
- + 	int usb0_drvvbus;
- + 	int usb1_dm;
- + 	int usb1_dp;
- + 	int usb1_ce;
- + 	int usb1_id;
- + 	int usb1_vbus;
- + 	int usb1_drvvbus;
- + 	int ddr_resetn;
- + 	int ddr_csn0;
- + 	int ddr_cke;
- + 	int ddr_ck;
- + 	int ddr_nck;
- + 	int ddr_casn;
- + 	int ddr_rasn;
- + 	int ddr_wen;
- + 	int ddr_ba0;
- + 	int ddr_ba1;
- + 	int ddr_ba2;
- + 	int ddr_a0;
- + 	int ddr_a1;
- + 	int ddr_a2;
- + 	int ddr_a3;
- + 	int ddr_a4;
- + 	int ddr_a5;
- + 	int ddr_a6;
- + 	int ddr_a7;
- + 	int ddr_a8;
- + 	int ddr_a9;
- + 	int ddr_a10;
- + 	int ddr_a11;
- + 	int ddr_a12;
- + 	int ddr_a13;
- + 	int ddr_a14;
- + 	int ddr_a15;
- + 	int ddr_odt;
- + 	int ddr_d0;
- + 	int ddr_d1;
- + 	int ddr_d2;
- + 	int ddr_d3;
- + 	int ddr_d4;
- + 	int ddr_d5;
- + 	int ddr_d6;
- + 	int ddr_d7;
- + 	int ddr_d8;
- + 	int ddr_d9;
- + 	int ddr_d10;
- + 	int ddr_d11;
- + 	int ddr_d12;
- + 	int ddr_d13;
- + 	int ddr_d14;
- + 	int ddr_d15;
- + 	int ddr_dqm0;
- + 	int ddr_dqm1;
- + 	int ddr_dqs0;
- + 	int ddr_dqsn0;
- + 	int ddr_dqs1;
- + 	int ddr_dqsn1;
- + 	int ddr_vref;
- + 	int ddr_vtp;
- + 	int ddr_strben0;
- + 	int ddr_strben1;
- + 	int ain7;
- + 	int ain6;
- + 	int ain5;
- + 	int ain4;
- + 	int ain3;
- + 	int ain2;
- + 	int ain1;
- + 	int ain0;
- + 	int vrefp;
- + 	int vrefn;
- + };
- + 
- + struct module_pin_mux {
- + 	short reg_offset;
- + 	unsigned char val;
- + };
- + 
- + /* Pad control register offset */
- + #define PAD_CTRL_BASE	0x800
- + #define OFFSET(x)	(unsigned int) (&((struct pad_signals *) \
- + 				(PAD_CTRL_BASE))->x)
- + 
- + #if 0
- + static struct module_pin_mux uart0_pin_mux[] = {
- + 	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_RXD */
- + 	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},		/* UART0_TXD */
- + 	{-1},
- + };
- + #endif
- + 
- + static struct module_pin_mux mmc0_pin_mux[] = {
- + 	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
- + 	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
- + 	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
- + 	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
- + 	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
- + 	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
- + 	//{OFFSET(spi0_cs1), (MODE(7) | RXACTIVE | PULLUP_EN)},	/* MMC0_CD */
- + 	{-1},
- + };
- + 
- + #if 0
- + static struct module_pin_mux i2c0_pin_mux[] = {
- + 	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
- + 			PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
- + 	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
- + 			PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
- + 	{-1},
- + };
- + 
- + static struct module_pin_mux i2c1_pin_mux[] = {
- + 	{OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
- + 			PULLUDEN | SLEWCTRL)},	/* I2C_DATA */
- + 	{OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
- + 			PULLUDEN | SLEWCTRL)},	/* I2C_SCLK */
- + 	{-1},
- + };
- + 
- + static struct module_pin_mux rgmii1_pin_mux[] = {
- + 	{OFFSET(mii1_txen), MODE(2)},			/* RGMII1_TCTL */
- + 	{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE},	/* RGMII1_RCTL */
- + 	{OFFSET(mii1_txd3), MODE(2)},			/* RGMII1_TD3 */
- + 	{OFFSET(mii1_txd2), MODE(2)},			/* RGMII1_TD2 */
- + 	{OFFSET(mii1_txd1), MODE(2)},			/* RGMII1_TD1 */
- + 	{OFFSET(mii1_txd0), MODE(2)},			/* RGMII1_TD0 */
- + 	{OFFSET(mii1_txclk), MODE(2)},			/* RGMII1_TCLK */
- + 	{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE},	/* RGMII1_RCLK */
- + 	{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE},	/* RGMII1_RD3 */
- + 	{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE},	/* RGMII1_RD2 */
- + 	{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE},	/* RGMII1_RD1 */
- + 	{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE},	/* RGMII1_RD0 */
- + 	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
- + 	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
- + 	{-1},
- + };
- + #endif
- + static struct module_pin_mux lcd_pin_mux[] = {
- + 	{OFFSET(lcd_data0), MODE(0) | PULLUDDIS | SLEWCTRL},
- + 	{OFFSET(lcd_data1), MODE(0) | PULLUDDIS | SLEWCTRL},
- + 	{OFFSET(lcd_data2), MODE(0) | PULLUDDIS | SLEWCTRL},
- + 	{OFFSET(lcd_data3), MODE(0) | PULLUDDIS | SLEWCTRL},
- + 	{OFFSET(lcd_data4), MODE(0) | PULLUDDIS | SLEWCTRL},
- + 	{OFFSET(lcd_data5), MODE(0) | PULLUDDIS | SLEWCTRL},
- + 	{OFFSET(lcd_data6), MODE(0) | PULLUDDIS | SLEWCTRL},
- + 	{OFFSET(lcd_data7), MODE(0) | PULLUDDIS | SLEWCTRL},
- + 	{OFFSET(lcd_data8), MODE(0) | PULLUDDIS | SLEWCTRL},
- + 	{OFFSET(lcd_data9), MODE(0) | PULLUDDIS | SLEWCTRL},
- + 	{OFFSET(lcd_data10), MODE(0) | PULLUDDIS | SLEWCTRL},
- + 	{OFFSET(lcd_data11), MODE(0) | PULLUDDIS | SLEWCTRL},
- + 	{OFFSET(lcd_data12), MODE(0) | PULLUDDIS | SLEWCTRL},
- + 	{OFFSET(lcd_data13), MODE(0) | PULLUDDIS | SLEWCTRL},
- + 	{OFFSET(lcd_data14), MODE(0) | PULLUDDIS | SLEWCTRL},
- + 	{OFFSET(lcd_data15), MODE(0) | PULLUDDIS | SLEWCTRL},
- + 	{OFFSET(lcd_vsync), MODE(0) | SLEWCTRL},
- + 	{OFFSET(lcd_hsync), MODE(0) | SLEWCTRL},
- + 	{OFFSET(lcd_pclk), MODE(0) | SLEWCTRL},
- + 	{OFFSET(lcd_ac_bias_en), MODE(0) | SLEWCTRL},
- + 	
- + 	{-1},
- + };
- + 
- + static struct module_pin_mux lcdpwr_pin_mux[] = {
- + 	{OFFSET(emu0), MODE(7) | PULLUP_EN},		/* LCDC Pwr pin */
- + 	{OFFSET(emu1), MODE(7) | PULLUP_EN},		/* Backlight pin */
- + 	{OFFSET(mcasp0_fsr), MODE(7) | PULLUP_EN},	/* TPS pin */
- + 	{-1},
- + };
- + 
- + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
- + struct module_pin_mux nor_flash_pins[] = {
- + 	{OFFSET(gpmc_ad0), MODE(0) | PULLUDEN | RXACTIVE},	/* NOR_AD0 */
- + 	{OFFSET(gpmc_ad1), MODE(0) | PULLUDEN | RXACTIVE},	/* NOR_AD1 */
- + 	{OFFSET(gpmc_ad2), MODE(0) | PULLUDEN | RXACTIVE},	/* NOR_AD2 */
- + 	{OFFSET(gpmc_ad3), MODE(0) | PULLUDEN | RXACTIVE},	/* NOR_AD3 */
- + 	{OFFSET(gpmc_ad4), MODE(0) | PULLUDEN | RXACTIVE},	/* NOR_AD4 */
- + 	{OFFSET(gpmc_ad5), MODE(0) | PULLUDEN | RXACTIVE},	/* NOR_AD5 */
- + 	{OFFSET(gpmc_ad6), MODE(0) | PULLUDEN | RXACTIVE},	/* NOR_AD6 */
- + 	{OFFSET(gpmc_ad7), MODE(0) | PULLUDEN | RXACTIVE},	/* NOR_AD7 */
- + 	{OFFSET(gpmc_ad8), MODE(0) | PULLUDEN | RXACTIVE},	/* NOR_AD8 */
- + 	{OFFSET(gpmc_ad9), MODE(0) | PULLUDEN | RXACTIVE},	/* NOR_AD9 */
- + 	{OFFSET(gpmc_ad10), MODE(0) | PULLUDEN | RXACTIVE},	/* NOR_AD10 */
- + 	{OFFSET(gpmc_ad11), MODE(0) | PULLUDEN | RXACTIVE},	/* NOR_AD11 */
- + 	{OFFSET(gpmc_ad12), MODE(0) | PULLUDEN | RXACTIVE},	/* NOR_AD12 */
- + 	{OFFSET(gpmc_ad13), MODE(0) | PULLUDEN | RXACTIVE},	/* NOR_AD13 */
- + 	{OFFSET(gpmc_ad14), MODE(0) | PULLUDEN | RXACTIVE},	/* NOR_AD14 */
- + 	{OFFSET(gpmc_ad15), MODE(0) | PULLUDEN | RXACTIVE},	/* NOR_AD15 */
- + 
- + 	{OFFSET(gpmc_csn0), MODE(0) | PULLUDDIS},			/* NOR_CE */
- + 	{OFFSET(gpmc_advn_ale), MODE(0) | PULLUDDIS}, 		/* NOR_ADVN_ALE */
- + 	{OFFSET(gpmc_oen_ren), MODE(0) | PULLUDDIS},		/* NOR_OE */
- + 	{OFFSET(gpmc_wen), MODE(0) | PULLUDDIS},			/* NOR_WEN */
- + 	{-1},
- + };
- + 	
- + struct module_pin_mux nor_flash_gpio_pins[] = {
- + 	/* GPIOs for selecting banks */
- + 	{OFFSET(gpmc_a4), (MODE(7) | PULLUDDIS)},	/* GP1_20 */
- + 	{OFFSET(gpmc_a5), (MODE(7) | PULLUDDIS)},	/* GP1_21 */
- + 	{OFFSET(gpmc_a6), (MODE(7) | PULLUDDIS)},	/* GP1_22 */
- + 	{OFFSET(gpmc_a7), (MODE(7) | PULLUDDIS)},	/* GP1_23 */
- + 	{OFFSET(gpmc_a8), (MODE(7) | PULLUDDIS)},	/* GP1_24 */
- + 	{OFFSET(gpmc_a9), (MODE(7) | PULLUDDIS)},	/* GP1_25 */
- + 	{OFFSET(gpmc_a10), (MODE(7) | PULLUDDIS)},	/* GP1_26 */
- + 	{-1},
- + };
- + #endif
- + 
- + /*
- +  * Configure the pin mux for the module
- +  */
- + static void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux)
- + {
- + 	int i;
- + 
- + 	if (!mod_pin_mux)
- + 		return;
- + 
- + 	for (i = 0; mod_pin_mux[i].reg_offset != -1; i++)
- + 		MUX_CFG(mod_pin_mux[i].val, mod_pin_mux[i].reg_offset);
- + }
- + #if 0
- + void enable_uart0_pin_mux(void)
- + {
- + 	configure_module_pin_mux(uart0_pin_mux);
- + }
- + 
- + 
- + void enable_i2c0_pin_mux(void)
- + {
- + 	configure_module_pin_mux(i2c0_pin_mux);
- + }
- + #endif
- + void enable_board_pin_mux()
- + {
- + 	configure_module_pin_mux(lcd_pin_mux);
- + 	configure_module_pin_mux(lcdpwr_pin_mux);
- + 	
- + #if defined(CONFIG_OMAP_HSMMC)
- + 	configure_module_pin_mux(mmc0_pin_mux);
- + #endif
- + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
- + 	configure_module_pin_mux(nor_flash_pins);
- + 	configure_module_pin_mux(nor_flash_gpio_pins);
- + #endif
- + }
- diff -crN u-boot-2012.10_o/board/computex/ckb-3352/tfp410.c u-boot-2012.10/board/computex/ckb-3352/tfp410.c
- *** u-boot-2012.10_o/board/computex/ckb-3352/tfp410.c	1970-01-01 09:00:00.000000000 +0900
- --- u-boot-2012.10/board/computex/ckb-3352/tfp410.c	2014-03-19 14:41:08.048747000 +0900
- ***************
- *** 0 ****
- --- 1,211 ----
- + /*
- +  * TFP410 basic functions, uses the I2c interface
- +  *
- +  * Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
- +  *
- +  * This program is free software; you can redistribute it and/or modify
- +  * it under the terms of the GNU General Public License as published by
- +  * the Free Software Foundation; either version 2 of the License, or
- +  * (at your option) any later version.
- +  *
- +  * This program is distributed in the hope that it will be useful,
- +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  *
- +  * You should have received a copy of the GNU General Public License
- +  * along with this program; if not, write to the Free Software
- +  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- +  */
- + #include <asm/arch/cpu.h>
- + #include <asm/arch/hardware.h>
- + #include <asm/arch/omap.h>
- + #include <asm/arch/ddr_defs.h>
- + #include <asm/arch/clock.h>
- + #include <asm/arch/gpio.h>
- + #include <asm/arch/mem.h>
- + #include <asm/arch/mmc_host_def.h>
- + #include <asm/arch/sys_proto.h>
- + #include <asm/io.h>
- + #include <asm/emif.h>
- + #include <asm/gpio.h>
- + #include <common.h>
- + #include <asm/omap_gpio.h>
- + 
- + #if defined(CONFIG_CKB_DVI)
- + 
- + #define TFP410_I2C_ADDR				0x38
- + /* register definitions according to the TFP410 data sheet */
- + #define TFP410_VID		0x014C
- + #define TFP410_DID		0x0410
- + 
- + #define TFP410_VID_LO		0x00
- + #define TFP410_VID_HI		0x01
- + #define TFP410_DID_LO		0x02
- + #define TFP410_DID_HI		0x03
- + #define TFP410_REV		0x04
- + 
- + #define TFP410_CTL_1		0x08
- + #define TFP410_CTL_1_TDIS	(1<<6)
- + #define TFP410_CTL_1_VEN	(1<<5)
- + #define TFP410_CTL_1_HEN	(1<<4)
- + #define TFP410_CTL_1_DSEL	(1<<3)
- + #define TFP410_CTL_1_BSEL	(1<<2)
- + #define TFP410_CTL_1_EDGE	(1<<1)
- + #define TFP410_CTL_1_PD		(1<<0)
- + 
- + #define TFP410_CTL_2		0x09
- + #define TFP410_CTL_2_VLOW	(1<<7)
- + #define TFP410_CTL_2_MSEL_MASK	(0x7<<4)
- + #define TFP410_CTL_2_MSEL	(1<<4)
- + #define TFP410_CTL_2_TSEL	(1<<3)
- + #define TFP410_CTL_2_RSEN	(1<<2)
- + #define TFP410_CTL_2_HTPLG	(1<<1)
- + #define TFP410_CTL_2_MDI	(1<<0)
- + 
- + #define TFP410_CTL_3		0x0A
- + #define TFP410_CTL_3_DK_MASK	(0x7<<5)
- + #define TFP410_CTL_3_DK		(1<<5)
- + #define TFP410_CTL_3_DKEN	(1<<4)
- + #define TFP410_CTL_3_CTL_MASK	(0x7<<1)
- + #define TFP410_CTL_3_CTL	(1<<1)
- + 
- + #define TFP410_USERCFG		0x0B
- + 
- + #define TFP410_DE_DLY		0x32
- + 
- + #define TFP410_DE_CTL		0x33
- + #define TFP410_DE_CTL_DEGEN	(1<<6)
- + #define TFP410_DE_CTL_VSPOL	(1<<5)
- + #define TFP410_DE_CTL_HSPOL	(1<<4)
- + #define TFP410_DE_CTL_DEDLY8	(1<<0)
- + 
- + #define TFP410_DE_TOP		0x34
- + 
- + #define TFP410_DE_CNT_LO	0x36
- + #define TFP410_DE_CNT_HI	0x37
- + 
- + #define TFP410_DE_LIN_LO	0x38
- + #define TFP410_DE_LIN_HI	0x39
- + 
- + #define TFP410_H_RES_LO		0x3A
- + #define TFP410_H_RES_HI		0x3B
- + 
- + #define TFP410_V_RES_LO		0x3C
- + #define TFP410_V_RES_HI		0x3D
- + 	
- + static int tfp410_readb(uint addr, uchar *ch)
- + {
- + 	if(i2c_read(TFP410_I2C_ADDR, addr, 1, ch, 1))
- + 	{
- + 		printf("TFP410 read failed\n");
- + 		return -1;
- + 	}
- + 	return 0;
- + }
- + 
- + static int tfp410_writeb(uint addr, uchar ch)
- + {
- + 	if(i2c_write(TFP410_I2C_ADDR, addr, 1, &ch, 1))
- + 	{
- + 		printf("TFP410 write failed\n");
- + 		return -1;
- + 	}
- + 	return 0;
- + }
- + 
- + 
- + /* set the tfp410 power state */
- + static void tfp410_poweron()
- + {
- + 	uchar ctl1;
- + 
- + 	if (tfp410_readb(TFP410_CTL_1, &ctl1))
- + 		return;
- + 
- + 	ctl1 |= TFP410_CTL_1_PD;
- + 	
- + 	tfp410_writeb(TFP410_CTL_1, ctl1);
- + 	
- + 	if (tfp410_readb(TFP410_CTL_2, &ctl1))
- + 		return;
- + 	tfp410_writeb(TFP410_CTL_2, (ctl1 & ~TFP410_CTL_2_MSEL_MASK) | (1 << 4) );
- + }
- + 
- + 
- + static int tfp410_getid(uint addr)
- + {
- + 	uchar ch[2];
- + 
- + 	if(i2c_read(TFP410_I2C_ADDR, addr, 1, &ch, 2))
- + 	{
- + 		printf("TFP410 ID read failed\n");
- + 		return -1;
- + 	}
- + 	return ((ch[1] << 8) & 0xFF00) | (ch[0] & 0x00FF);
- + }
- + 
- + #if 0
- + static void tfp410_dump_regs()
- + {
- + 	uint8_t val, val2;
- + 
- + 	tfp410_readb(TFP410_REV, &val);
- + 	printf("TFP410_REV: 0x%02X\n", val);
- + 	tfp410_readb(TFP410_CTL_1, &val);
- + 	printf("TFP410_CTL1: 0x%02X\n", val);
- + 	tfp410_readb(TFP410_CTL_2, &val);
- + 	printf("TFP410_CTL2: 0x%02X\n", val);
- + 	tfp410_readb(TFP410_CTL_3, &val);
- + 	printf("TFP410_CTL3: 0x%02X\n", val);
- + 	tfp410_readb(TFP410_USERCFG, &val);
- + 	printf("TFP410_USERCFG: 0x%02X\n", val);
- + 	tfp410_readb(TFP410_DE_DLY, &val);
- + 	printf("TFP410_DE_DLY: 0x%02X\n", val);
- + 	tfp410_readb(TFP410_DE_CTL, &val);
- + 	printf("TFP410_DE_CTL: 0x%02X\n", val);
- + 	tfp410_readb(TFP410_DE_TOP, &val);
- + 	printf("TFP410_DE_TOP: 0x%02X\n", val);
- + 	tfp410_readb(TFP410_DE_CNT_LO, &val);
- + 	tfp410_readb(TFP410_DE_CNT_HI, &val2);
- + 	printf("TFP410_DE_CNT: 0x%02X%02X\n", val2, val);
- + 	tfp410_readb(TFP410_DE_LIN_LO, &val);
- + 	tfp410_readb(TFP410_DE_LIN_HI, &val2);
- + 	printf("TFP410_DE_LIN: 0x%02X%02X\n", val2, val);
- + 	tfp410_readb(TFP410_H_RES_LO, &val);
- + 	tfp410_readb(TFP410_H_RES_HI, &val2);
- + 	printf("TFP410_H_RES: 0x%02X%02X\n", val2, val);
- + 	tfp410_readb(TFP410_V_RES_LO, &val);
- + 	tfp410_readb(TFP410_V_RES_HI, &val2);
- + 	printf("TFP410_V_RES: 0x%02X%02X\n", val2, val);
- + }
- + #endif
- + 
- + int init_tfp410()
- + {
- + 	int id;
- + 	uchar ctl3;
- + 	tfp410_poweron(1);
- + 	/* Get ID  */
- + 	if ((id = tfp410_getid(TFP410_VID_LO)) != TFP410_VID) {
- + 		printf("TFP410 not detected got VID %X\n", id);
- + 		return 1;
- + 	}
- + 
- + 	if ((id = tfp410_getid(TFP410_DID_LO)) != TFP410_DID) {
- + 		printf("TFP410 not detected got DID %X\n", id);
- + 		return 1;
- + 	}
- + 	//tfp410_dump_regs();
- + 	/* enable skew */
- + 	if(tfp410_readb(TFP410_CTL_3, &ctl3)
- + 		|| tfp410_writeb(TFP410_CTL_3, 
- + 				ctl3 | TFP410_CTL_3_DKEN | (0x7<<5))
- + 		|| tfp410_readb(TFP410_CTL_1, &ctl3)
- + 		|| tfp410_writeb(TFP410_CTL_1, 
- + 				(ctl3 & ~(TFP410_CTL_1_DSEL)) | TFP410_CTL_1_EDGE | TFP410_CTL_1_BSEL))
- + 		return 1;
- + 	//tfp410_dump_regs();
- + 	return 0;
- + }
- + #endif
- diff -crN u-boot-2012.10_o/boards.cfg u-boot-2012.10/boards.cfg
- *** u-boot-2012.10_o/boards.cfg	2012-10-16 00:14:08.000000000 +0900
- --- u-boot-2012.10/boards.cfg	2014-03-07 11:28:15.982294000 +0900
- ***************
- *** 226,231 ****
- --- 226,232 ----
-   integratorcp_cm946es         arm         arm946es    integrator          armltd         -               integratorcp:CM946ES
-   ca9x4_ct_vxp                 arm         armv7       vexpress            armltd
-   am335x_evm                   arm         armv7       am335x              ti             am33xx
- + ckb-3352                     arm         armv7       ckb-3352            computex       ckb_3352      ckb_3352
-   highbank                     arm         armv7       highbank            -              highbank
-   mx51_efikamx                 arm         armv7       mx51_efikamx        genesi         mx5		mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg
-   mx51_efikasb                 arm         armv7       mx51_efikamx        genesi         mx5		mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg
- diff -crN u-boot-2012.10_o/common/cmd_flash.c u-boot-2012.10/common/cmd_flash.c
- *** u-boot-2012.10_o/common/cmd_flash.c	2012-10-16 00:14:08.000000000 +0900
- --- u-boot-2012.10/common/cmd_flash.c	2014-02-27 11:33:16.781140652 +0900
- ***************
- *** 302,309 ****
-   #ifndef CONFIG_SYS_NO_FLASH
-   	if (argc == 1) {	/* print info for all FLASH banks */
-   		for (bank=0; bank <CONFIG_SYS_MAX_FLASH_BANKS; ++bank) {
-   			printf ("\nBank # %ld: ", bank+1);
- ! 
-   			flash_print_info (&flash_info[bank]);
-   		}
-   		return 0;
- --- 302,312 ----
-   #ifndef CONFIG_SYS_NO_FLASH
-   	if (argc == 1) {	/* print info for all FLASH banks */
-   		for (bank=0; bank <CONFIG_SYS_MAX_FLASH_BANKS; ++bank) {
- + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
- + 			printf ("\nFlash information: ");
- + #else
-   			printf ("\nBank # %ld: ", bank+1);
- ! #endif
-   			flash_print_info (&flash_info[bank]);
-   		}
-   		return 0;
- ***************
- *** 339,345 ****
- --- 342,352 ----
-   
-   	if (strcmp(argv[1], "all") == 0) {
-   		for (bank=1; bank<=CONFIG_SYS_MAX_FLASH_BANKS; ++bank) {
- + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
- + 			printf ("Erasing entire flash Banks ");
- + #else
-   			printf ("Erase Flash Bank # %ld ", bank);
- + #endif
-   			info = &flash_info[bank-1];
-   			rcode = flash_erase (info, 0, info->sector_count-1);
-   		}
- ***************
- *** 695,706 ****
- --- 702,720 ----
-   #endif
-   
-   U_BOOT_CMD(
- + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
- + 	flinfo,    1,    1,    do_flinfo,
- + #else
-   	flinfo,    2,    1,    do_flinfo,
- + #endif
-   	"print FLASH memory information",
-   	"\n    - print information for all FLASH memory banks\n"
- + #ifndef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
-   	"flinfo N\n    - print information for FLASH memory bank # N"
- + #endif
-   );
-   
- + #ifndef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
-   U_BOOT_CMD(
-   	erase,   3,   0,  do_flerase,
-   	"erase FLASH memory",
- ***************
- *** 739,744 ****
- --- 753,759 ----
-   	TMP_PROT_OFF
-   	"protect off all\n    - make all FLASH banks writable"
-   );
- + #endif
-   
-   #undef	TMP_ERASE
-   #undef	TMP_PROT_ON
- diff -crN u-boot-2012.10_o/common/cmd_mem.c u-boot-2012.10/common/cmd_mem.c
- *** u-boot-2012.10_o/common/cmd_mem.c	2012-10-16 00:14:08.000000000 +0900
- --- u-boot-2012.10/common/cmd_mem.c	2014-03-07 11:21:58.577708000 +0900
- ***************
- *** 45,50 ****
- --- 45,54 ----
-   
-   static	ulong	base_address = 0;
-   
- + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
- + extern char displaying_ckb_logo;
- + #endif
- + 
-   /* Memory Display
-    *
-    * Syntax:
- ***************
- *** 155,161 ****
-   {
-   	return mod_mem (cmdtp, 0, flag, argc, argv);
-   }
- ! 
-   int do_mem_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-   {
-   	ulong	addr, writeval, count;
- --- 159,165 ----
-   {
-   	return mod_mem (cmdtp, 0, flag, argc, argv);
-   }
- ! #ifndef CONFIG_MACH_CKB_3352
-   int do_mem_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-   {
-   	ulong	addr, writeval, count;
- ***************
- *** 196,202 ****
-   	}
-   	return 0;
-   }
- ! 
-   #ifdef CONFIG_MX_CYCLIC
-   int do_mem_mdc ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-   {
- --- 200,206 ----
-   	}
-   	return 0;
-   }
- ! #endif
-   #ifdef CONFIG_MX_CYCLIC
-   int do_mem_mdc ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-   {
- ***************
- *** 252,258 ****
-   	return 0;
-   }
-   #endif /* CONFIG_MX_CYCLIC */
- ! 
-   int do_mem_cmp (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-   {
-   	ulong	addr1, addr2, count, ngood;
- --- 256,262 ----
-   	return 0;
-   }
-   #endif /* CONFIG_MX_CYCLIC */
- ! #ifndef CONFIG_MACH_CKB_3352
-   int do_mem_cmp (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-   {
-   	ulong	addr1, addr2, count, ngood;
- ***************
- *** 322,332 ****
-   	printf("Total of %ld %s(s) were the same\n", ngood, type);
-   	return rcode;
-   }
- ! 
-   int do_mem_cp ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-   {
-   	ulong	addr, dest, count;
-   	int	size;
-   
-   	if (argc != 4)
-   		return CMD_RET_USAGE;
- --- 326,339 ----
-   	printf("Total of %ld %s(s) were the same\n", ngood, type);
-   	return rcode;
-   }
- ! #endif
-   int do_mem_cp ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-   {
-   	ulong	addr, dest, count;
-   	int	size;
- + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
- + 	ulong	*s, *d;
- + #endif
-   
-   	if (argc != 4)
-   		return CMD_RET_USAGE;
- ***************
- *** 349,354 ****
- --- 356,411 ----
-   		return 1;
-   	}
-   
- + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
- + 	/* check if both source and destination addresses are in flash */
- + 	if (addr2info(addr) && addr2info(dest)){
- + 		puts ("Unsupported combination of source/destination.\n\r");
- + 		return 1;
- + 	}
- + 	/* check if source address is in flash */
- + 	if ( addr2info(addr) != NULL){
- + 		if(!displaying_ckb_logo) {
- + 			puts ("Copying from Flash... ");
- + 		}
- + 		while (count > 0) {
- + 			if( (32<=count) && (get_ckb_3352_flash_bank(addr) == get_ckb_3352_flash_bank(addr+32-1)) ) {
- + 				s = (ulong *)set_ckb_3352_flash_bank(addr);
- + 				d = (ulong *)dest;
- + 				*d++ = *s++;
- + 				*d++ = *s++;
- + 				*d++ = *s++;
- + 				*d++ = *s++;
- + 				*d++ = *s++;
- + 				*d++ = *s++;
- + 				*d++ = *s++;
- + 				*d++ = *s++;
- + 				addr += 32;
- + 				dest += 32;
- + 				count -= 32;
- + 			} else {
- + 				if (size == 4) {
- + 					*((ulong  *)dest) = *((ulong  *)set_ckb_3352_flash_bank(addr));
- + 				} else if (size == 2) {
- + 					*((ushort *)dest) = *((ushort *)set_ckb_3352_flash_bank(addr));
- + 				} else {
- + 					*((u_char *)dest) = *((u_char *)set_ckb_3352_flash_bank(addr));
- + 				}
- + 				addr += size;
- + 				dest += size;
- + 				count++;
- + 			}
- + 			/* reset watchdog from time to time */
- + 			if ((count % (64 << 10)) == 0) {
- + 				WATCHDOG_RESET();
- + 			}
- + 		}
- + 		if(!displaying_ckb_logo) {
- + 			puts ("done\n");
- + 		}
- + 		return 0;
- + 	}
- + #endif
- + 
-   #ifndef CONFIG_SYS_NO_FLASH
-   	/* check if we are copying to Flash */
-   	if ( (addr2info(dest) != NULL)
- ***************
- *** 445,451 ****
-   	printf("Base Address: 0x%08lx\n", base_address);
-   	return 0;
-   }
- ! 
-   int do_mem_loop (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-   {
-   	ulong	addr, length, i;
- --- 502,508 ----
-   	printf("Base Address: 0x%08lx\n", base_address);
-   	return 0;
-   }
- ! #ifndef CONFIG_MACH_CKB_3352
-   int do_mem_loop (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-   {
-   	ulong	addr, length, i;
- ***************
- *** 513,519 ****
-   			*cp++;
-   	}
-   }
- ! 
-   #ifdef CONFIG_LOOPW
-   int do_mem_loopw (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-   {
- --- 570,576 ----
-   			*cp++;
-   	}
-   }
- ! #endif
-   #ifdef CONFIG_LOOPW
-   int do_mem_loopw (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-   {
- ***************
- *** 586,592 ****
-   	}
-   }
-   #endif /* CONFIG_LOOPW */
- ! 
-   /*
-    * Perform a memory test. A more complete alternative test can be
-    * configured using CONFIG_SYS_ALT_MEMTEST. The complete test loops until
- --- 643,649 ----
-   	}
-   }
-   #endif /* CONFIG_LOOPW */
- ! #ifndef CONFIG_MACH_CKB_3352
-   /*
-    * Perform a memory test. A more complete alternative test can be
-    * configured using CONFIG_SYS_ALT_MEMTEST. The complete test loops until
- ***************
- *** 941,947 ****
-   #endif
-   	return 0;	/* not reached */
-   }
- ! 
-   
-   /* Modify memory.
-    *
- --- 998,1004 ----
-   #endif
-   	return 0;	/* not reached */
-   }
- ! #endif
-   
-   /* Modify memory.
-    *
- ***************
- *** 1158,1181 ****
-   	"memory modify (constant address)",
-   	"[.b, .w, .l] address"
-   );
- ! 
-   U_BOOT_CMD(
-   	mw,	4,	1,	do_mem_mw,
-   	"memory write (fill)",
-   	"[.b, .w, .l] address value [count]"
-   );
- ! 
-   U_BOOT_CMD(
-   	cp,	4,	1,	do_mem_cp,
-   	"memory copy",
-   	"[.b, .w, .l] source target count"
-   );
- ! 
-   U_BOOT_CMD(
-   	cmp,	4,	1,	do_mem_cmp,
-   	"memory compare",
-   	"[.b, .w, .l] addr1 addr2 count"
-   );
-   
-   #ifdef CONFIG_CMD_CRC32
-   
- --- 1215,1239 ----
-   	"memory modify (constant address)",
-   	"[.b, .w, .l] address"
-   );
- ! #ifndef CONFIG_MACH_CKB_3352
-   U_BOOT_CMD(
-   	mw,	4,	1,	do_mem_mw,
-   	"memory write (fill)",
-   	"[.b, .w, .l] address value [count]"
-   );
- ! #endif
-   U_BOOT_CMD(
-   	cp,	4,	1,	do_mem_cp,
-   	"memory copy",
-   	"[.b, .w, .l] source target count"
-   );
- ! #ifndef CONFIG_MACH_CKB_3352
-   U_BOOT_CMD(
-   	cmp,	4,	1,	do_mem_cmp,
-   	"memory compare",
-   	"[.b, .w, .l] addr1 addr2 count"
-   );
- + #endif
-   
-   #ifdef CONFIG_CMD_CRC32
-   
- ***************
- *** 1206,1218 ****
-   	"\n    - print address offset for memory commands\n"
-   	"base off\n    - set address offset for memory commands to 'off'"
-   );
- ! 
-   U_BOOT_CMD(
-   	loop,	3,	1,	do_mem_loop,
-   	"infinite loop on address range",
-   	"[.b, .w, .l] address number_of_objects"
-   );
- ! 
-   #ifdef CONFIG_LOOPW
-   U_BOOT_CMD(
-   	loopw,	4,	1,	do_mem_loopw,
- --- 1264,1276 ----
-   	"\n    - print address offset for memory commands\n"
-   	"base off\n    - set address offset for memory commands to 'off'"
-   );
- ! #ifndef CONFIG_MACH_CKB_3352
-   U_BOOT_CMD(
-   	loop,	3,	1,	do_mem_loop,
-   	"infinite loop on address range",
-   	"[.b, .w, .l] address number_of_objects"
-   );
- ! #endif
-   #ifdef CONFIG_LOOPW
-   U_BOOT_CMD(
-   	loopw,	4,	1,	do_mem_loopw,
- ***************
- *** 1220,1232 ****
-   	"[.b, .w, .l] address number_of_objects data_to_write"
-   );
-   #endif /* CONFIG_LOOPW */
- ! 
-   U_BOOT_CMD(
-   	mtest,	5,	1,	do_mem_mtest,
-   	"simple RAM read/write test",
-   	"[start [end [pattern [iterations]]]]"
-   );
- ! 
-   #ifdef CONFIG_MX_CYCLIC
-   U_BOOT_CMD(
-   	mdc,	4,	1,	do_mem_mdc,
- --- 1278,1290 ----
-   	"[.b, .w, .l] address number_of_objects data_to_write"
-   );
-   #endif /* CONFIG_LOOPW */
- ! #ifndef CONFIG_MACH_CKB_3352
-   U_BOOT_CMD(
-   	mtest,	5,	1,	do_mem_mtest,
-   	"simple RAM read/write test",
-   	"[start [end [pattern [iterations]]]]"
-   );
- ! #endif
-   #ifdef CONFIG_MX_CYCLIC
-   U_BOOT_CMD(
-   	mdc,	4,	1,	do_mem_mdc,
- diff -crN u-boot-2012.10_o/common/cmd_nand.c u-boot-2012.10/common/cmd_nand.c
- *** u-boot-2012.10_o/common/cmd_nand.c	2012-10-16 00:14:08.000000000 +0900
- --- u-boot-2012.10/common/cmd_nand.c	2014-02-27 11:33:16.785289084 +0900
- ***************
- *** 219,224 ****
- --- 219,227 ----
-   	}
-   
-   print:
- + 	if (getenv("nandsilent") != NULL)
- + 		return 0;
- + 
-   	printf("device %d ", *idx);
-   	if (*size == nand_info[*idx].size)
-   		puts("whole chip\n");
- ***************
- *** 556,562 ****
-   		if (argc != o + args)
-   			goto usage;
-   
- ! 		printf("\nNAND %s: ", cmd);
-   		/* skip first two or three arguments, look for offset and size */
-   		if (arg_off_size(argc - o, argv + o, &dev, &off, &size) != 0)
-   			return 1;
- --- 559,567 ----
-   		if (argc != o + args)
-   			goto usage;
-   
- ! 		if (getenv("nandsilent") == NULL)
- ! 			printf("\nNAND %s: ", cmd);
- ! 
-   		/* skip first two or three arguments, look for offset and size */
-   		if (arg_off_size(argc - o, argv + o, &dev, &off, &size) != 0)
-   			return 1;
- ***************
- *** 590,596 ****
-   			}
-   		}
-   		ret = nand_erase_opts(nand, &opts);
- ! 		printf("%s\n", ret ? "ERROR" : "OK");
-   
-   		return ret == 0 ? 0 : 1;
-   	}
- --- 595,603 ----
-   			}
-   		}
-   		ret = nand_erase_opts(nand, &opts);
- ! 
- ! 		if (getenv("nandsilent") == NULL)
- ! 			printf("%s\n", ret ? "ERROR" : "OK");
-   
-   		return ret == 0 ? 0 : 1;
-   	}
- ***************
- *** 617,623 ****
-   		addr = (ulong)simple_strtoul(argv[2], NULL, 16);
-   
-   		read = strncmp(cmd, "read", 4) == 0; /* 1 = read, 0 = write */
- ! 		printf("\nNAND %s: ", read ? "read" : "write");
-   
-   		nand = &nand_info[dev];
-   
- --- 624,632 ----
-   		addr = (ulong)simple_strtoul(argv[2], NULL, 16);
-   
-   		read = strncmp(cmd, "read", 4) == 0; /* 1 = read, 0 = write */
- ! 
- ! 		if (getenv("nandsilent") == NULL)
- ! 			printf("\nNAND %s: ", read ? "read" : "write");
-   
-   		nand = &nand_info[dev];
-   
- ***************
- *** 695,702 ****
-   			return 1;
-   		}
-   
- ! 		printf(" %zu bytes %s: %s\n", rwsize,
- ! 		       read ? "read" : "written", ret ? "ERROR" : "OK");
-   
-   		return ret == 0 ? 0 : 1;
-   	}
- --- 704,712 ----
-   			return 1;
-   		}
-   
- ! 		if (getenv("nandsilent") == NULL)
- ! 			printf(" %zu bytes %s: %s\n", rwsize,
- ! 			       read ? "read" : "written", ret ? "ERROR" : "OK");
-   
-   		return ret == 0 ? 0 : 1;
-   	}
- diff -crN u-boot-2012.10_o/common/command.c u-boot-2012.10/common/command.c
- *** u-boot-2012.10_o/common/command.c	2012-10-16 00:14:08.000000000 +0900
- --- u-boot-2012.10/common/command.c	2014-02-27 11:35:23.634797000 +0900
- ***************
- *** 29,34 ****
- --- 29,38 ----
-   #include <command.h>
-   #include <linux/ctype.h>
-   
- + #ifdef CONFIG_MACH_CKB_3352
- + extern int _loader_executed_uboot;
- + #endif
- + 
-   /*
-    * Use puts() instead of printf() to avoid printf buffer overflow
-    * for long help messages
- ***************
- *** 39,45 ****
-   {
-   	int i;
-   	int rcode = 0;
- ! 
-   	if (argc == 1) {	/*show list of commands */
-   		cmd_tbl_t *cmd_array[cmd_items];
-   		int i, j, swaps;
- --- 43,52 ----
-   {
-   	int i;
-   	int rcode = 0;
- ! 	
- ! #ifdef CONFIG_MACH_CKB_3352
- ! 	u_char cmd_ignored = 0;
- ! #endif
-   	if (argc == 1) {	/*show list of commands */
-   		cmd_tbl_t *cmd_array[cmd_items];
-   		int i, j, swaps;
- ***************
- *** 76,81 ****
- --- 83,95 ----
-   				return 1;
-   			if (usage == NULL)
-   				continue;
- + #ifdef CONFIG_MACH_CKB_3352
- + 			if(!cmd_ignored && _loader_executed_uboot && !strcmp(cmd_array[i]->name, FLASH_UBOOT_CMD_STR))
- + 			{
- + 				cmd_ignored = 1;
- + 				continue;
- + 			}
- + #endif
-   			printf("%-*s- %s\n", CONFIG_SYS_HELP_CMD_WIDTH,
-   			       cmd_array[i]->name, usage);
-   		}
- ***************
- *** 103,114 ****
-    */
-   cmd_tbl_t *find_cmd_tbl (const char *cmd, cmd_tbl_t *table, int table_len)
-   {
- ! 	cmd_tbl_t *cmdtp;
- ! 	cmd_tbl_t *cmdtp_temp = table;	/*Init value */
-   	const char *p;
-   	int len;
-   	int n_found = 0;
- ! 
-   	if (!cmd)
-   		return NULL;
-   	/*
- --- 117,130 ----
-    */
-   cmd_tbl_t *find_cmd_tbl (const char *cmd, cmd_tbl_t *table, int table_len)
-   {
- ! 	volatile cmd_tbl_t *cmdtp;
- ! 	volatile cmd_tbl_t *cmdtp_temp = table;	/*Init value */
-   	const char *p;
-   	int len;
-   	int n_found = 0;
- ! #ifdef CONFIG_MACH_CKB_3352
- ! 	u_char cmd_ignored = 0;
- ! #endif
-   	if (!cmd)
-   		return NULL;
-   	/*
- ***************
- *** 120,125 ****
- --- 136,148 ----
-   	for (cmdtp = table;
-   	     cmdtp != table + table_len;
-   	     cmdtp++) {
- + #ifdef CONFIG_MACH_CKB_3352
- + 		if(!cmd_ignored && _loader_executed_uboot && !strcmp(cmdtp->name, FLASH_UBOOT_CMD_STR))
- + 		{
- + 			cmd_ignored = 1;
- + 			continue;
- + 		}
- + #endif
-   		if (strncmp (cmd, cmdtp->name, len) == 0) {
-   			if (len == strlen (cmdtp->name))
-   				return cmdtp;	/* full match */
- ***************
- *** 181,192 ****
-   
-   static int complete_cmdv(int argc, char * const argv[], char last_char, int maxv, char *cmdv[])
-   {
- ! 	cmd_tbl_t *cmdtp;
-   	const char *p;
-   	int len, clen;
-   	int n_found = 0;
-   	const char *cmd;
- ! 
-   	/* sanity? */
-   	if (maxv < 2)
-   		return -2;
- --- 204,217 ----
-   
-   static int complete_cmdv(int argc, char * const argv[], char last_char, int maxv, char *cmdv[])
-   {
- ! 	volatile cmd_tbl_t *cmdtp;
-   	const char *p;
-   	int len, clen;
-   	int n_found = 0;
-   	const char *cmd;
- ! #ifdef CONFIG_MACH_CKB_3352
- ! 	u_char cmd_ignored = 0;
- ! #endif
-   	/* sanity? */
-   	if (maxv < 2)
-   		return -2;
- ***************
- *** 196,201 ****
- --- 221,233 ----
-   	if (argc == 0) {
-   		/* output full list of commands */
-   		for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) {
- + #ifdef CONFIG_MACH_CKB_3352
- + 			if(!cmd_ignored && _loader_executed_uboot && !strcmp(cmdtp->name, FLASH_UBOOT_CMD_STR))
- + 			{
- + 				cmd_ignored = 1;
- + 				continue;
- + 			}
- + #endif		
-   			if (n_found >= maxv - 2) {
-   				cmdv[n_found++] = "...";
-   				break;
- ***************
- *** 229,235 ****
-   
-   	/* return the partial matches */
-   	for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) {
- ! 
-   		clen = strlen(cmdtp->name);
-   		if (clen < len)
-   			continue;
- --- 261,273 ----
-   
-   	/* return the partial matches */
-   	for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) {
- ! #ifdef CONFIG_MACH_CKB_3352
- ! 		if(!cmd_ignored && _loader_executed_uboot && !strcmp(cmdtp->name, FLASH_UBOOT_CMD_STR))
- ! 		{
- ! 			cmd_ignored = 1;
- ! 			continue;
- ! 		}
- ! #endif
-   		clen = strlen(cmdtp->name);
-   		if (clen < len)
-   			continue;
- ***************
- *** 513,519 ****
-   			       int *repeatable)
-   {
-   	enum command_ret_t rc = CMD_RET_SUCCESS;
- ! 	cmd_tbl_t *cmdtp;
-   
-   	/* Look up command in command table */
-   	cmdtp = find_cmd(argv[0]);
- --- 551,557 ----
-   			       int *repeatable)
-   {
-   	enum command_ret_t rc = CMD_RET_SUCCESS;
- ! 	volatile cmd_tbl_t *cmdtp;
-   
-   	/* Look up command in command table */
-   	cmdtp = find_cmd(argv[0]);
- diff -crN u-boot-2012.10_o/common/env_common.c u-boot-2012.10/common/env_common.c
- *** u-boot-2012.10_o/common/env_common.c	2012-10-16 00:14:08.000000000 +0900
- --- u-boot-2012.10/common/env_common.c	2014-02-27 11:33:16.787904930 +0900
- ***************
- *** 238,245 ****
-    */
-   int env_import(const char *buf, int check)
-   {
-   	env_t *ep = (env_t *)buf;
- ! 
-   	if (check) {
-   		uint32_t crc;
-   
- --- 238,250 ----
-    */
-   int env_import(const char *buf, int check)
-   {
- + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
- + 	unsigned long addr = set_ckb_3352_flash_bank(buf);
- + 	env_t *ep = (env_t *)addr;
- + #else
-   	env_t *ep = (env_t *)buf;
- ! #endif
- ! 	
-   	if (check) {
-   		uint32_t crc;
-   
- diff -crN u-boot-2012.10_o/common/env_flash.c u-boot-2012.10/common/env_flash.c
- *** u-boot-2012.10_o/common/env_flash.c	2012-10-16 00:14:08.000000000 +0900
- --- u-boot-2012.10/common/env_flash.c	2014-02-27 11:33:16.787904930 +0900
- ***************
- *** 72,78 ****
-   static ulong end_addr_new = CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1;
-   #endif /* CONFIG_ENV_ADDR_REDUND */
-   
- - 
-   #ifdef CONFIG_ENV_ADDR_REDUND
-   int env_init(void)
-   {
- --- 72,77 ----
- ***************
- *** 230,240 ****
- --- 229,250 ----
-   
-   int env_init(void)
-   {
- + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
- + 	/* Set the bank */
- + 	unsigned long addr = set_ckb_3352_flash_bank(env_ptr->data);
- + 	if (crc32(0, addr, ENV_SIZE) == env_ptr->crc) {
- + 		/* for now point the enviroment to the flash bank, this will me moved after malloc is available */
- + 		gd->env_addr = addr;
- + 		gd->env_valid	= 1;
- + 		return 0;
- + 	}	
- + #else
-   	if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) {
-   		gd->env_addr	= (ulong)&(env_ptr->data);
-   		gd->env_valid	= 1;
-   		return 0;
-   	}
- + #endif
-   
-   	gd->env_addr	= (ulong)&default_environment[0];
-   	gd->env_valid	= 0;
- diff -crN u-boot-2012.10_o/drivers/mtd/cfi_flash.c u-boot-2012.10/drivers/mtd/cfi_flash.c
- *** u-boot-2012.10_o/drivers/mtd/cfi_flash.c	2012-10-16 00:14:08.000000000 +0900
- --- u-boot-2012.10/drivers/mtd/cfi_flash.c	2014-02-27 11:33:16.791619660 +0900
- ***************
- *** 79,84 ****
- --- 79,139 ----
-   #define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
-   #endif
-   
- + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
- + extern int ckb_3352_cur_flash_bank;
- + 
- + inline static void mem_write8(u8 value, void *addr)
- + {
- + 	__raw_writeb(value, addr);
- + }
- + 
- + inline static void mem_write16(u16 value, void *addr)
- + {
- + 	__raw_writew(value, addr);
- + }
- + 
- + inline static void mem_write32(u32 value, void *addr)
- + {
- + 	__raw_writel(value, addr);
- + }
- + 
- + inline static u8 mem_read8(void *addr)
- + {
- + 	return __raw_readb(addr);
- + }
- + 
- + inline static u16 mem_read16(void *addr)
- + {
- + 	return __raw_readw(addr);
- + }
- + 
- + inline static u32 mem_read32(void *addr)
- + {
- + 	return __raw_readl(addr);
- + }
- + 
- + inline unsigned long set_ckb_3352_flash_bank(unsigned long addr)
- + {
- + 	/* The flash bank is a shadow mapping of 128KB changable by the GPIOs GP1[20]~GP1[26] */
- + 	int ckb_3352_flash_bank = (addr - CONFIG_SYS_FLASH_BASE)/CONFIG_FLASH_CKB_BANK_SIZE;
- + 	//printf("Map address %x ", addr);
- + 	if(ckb_3352_flash_bank != ckb_3352_cur_flash_bank)
- + 	{
- + 		/* select map using GPIOs GP2[0]~GP2[3] */
- + 		//printf("changing bank to %d addr %x\n", ckb_3352_flash_bank, addr); 
- + 		set_nor_flash_bank(ckb_3352_flash_bank);
- + 	}
- + 	/* adjust the address */
- + 	return (addr & (CONFIG_FLASH_CKB_BANK_SIZE-1)) | CONFIG_SYS_FLASH_BASE;
- + }
- + 
- + unsigned long get_ckb_3352_flash_bank(unsigned long addr)
- + {
- + 	return (addr - CONFIG_SYS_FLASH_BASE) / CONFIG_FLASH_CKB_BANK_SIZE;
- + }
- + 
- + #endif
- + 
-   /*
-    * 0xffff is an undefined value for the configuration register. When
-    * this value is returned, the configuration register shall not be
- ***************
- *** 115,132 ****
- --- 170,205 ----
-   unsigned long cfi_flash_bank_size(int i)
-   	__attribute__((weak, alias("__cfi_flash_bank_size")));
-   
- + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
- + inline
- + #endif
-   static void __flash_write8(u8 value, void *addr)
-   {
- + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
- + 	addr = set_ckb_3352_flash_bank(addr);
- + #endif
-   	__raw_writeb(value, addr);
-   }
-   
- + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
- + inline
- + #endif
-   static void __flash_write16(u16 value, void *addr)
-   {
- + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
- + 	addr = set_ckb_3352_flash_bank(addr);
- + #endif
-   	__raw_writew(value, addr);
-   }
-   
- + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
- + inline
- + #endif
-   static void __flash_write32(u32 value, void *addr)
-   {
- + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
- + 	addr = set_ckb_3352_flash_bank(addr);
- + #endif
-   	__raw_writel(value, addr);
-   }
-   
- ***************
- *** 136,153 ****
- --- 209,245 ----
-   	*(volatile u64 *)addr = value;
-   }
-   
- + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
- + inline
- + #endif
-   static u8 __flash_read8(void *addr)
-   {
- + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
- + 	addr = set_ckb_3352_flash_bank(addr);
- + #endif
-   	return __raw_readb(addr);
-   }
-   
- + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
- + inline
- + #endif
-   static u16 __flash_read16(void *addr)
-   {
- + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
- + 	addr = set_ckb_3352_flash_bank(addr);
- + #endif
-   	return __raw_readw(addr);
-   }
-   
- + 
- + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
- + inline
- + #endif
-   static u32 __flash_read32(void *addr)
-   {
- + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
- + 	addr = set_ckb_3352_flash_bank(addr);
- + #endif
-   	return __raw_readl(addr);
-   }
-   
- ***************
- *** 901,918 ****
- --- 993,1025 ----
-   	while ((cnt-- > 0) && (flag == 1)) {
-   		switch (info->portwidth) {
-   		case FLASH_CFI_8BIT:
- + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
- + 			flag = ((flash_read8(dst2) & mem_read8(src)) ==
- + 				mem_read8(src));
- + #else
-   			flag = ((flash_read8(dst2) & flash_read8(src)) ==
-   				flash_read8(src));
- + #endif
-   			src += 1, dst2 += 1;
-   			break;
-   		case FLASH_CFI_16BIT:
- + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
- + 			flag = ((flash_read16(dst2) & mem_read16(src)) ==
- + 				mem_read16(src));
- + #else
-   			flag = ((flash_read16(dst2) & flash_read16(src)) ==
-   				flash_read16(src));
- + #endif
-   			src += 2, dst2 += 2;
-   			break;
-   		case FLASH_CFI_32BIT:
- + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
- + 			flag = ((flash_read32(dst2) & mem_read32(src)) ==
- + 				mem_read32(src));
- + #else
-   			flag = ((flash_read32(dst2) & flash_read32(src)) ==
-   				flash_read32(src));
- + #endif
-   			src += 4, dst2 += 4;
-   			break;
-   		case FLASH_CFI_64BIT:
- ***************
- *** 950,964 ****
- --- 1057,1083 ----
-   			while (cnt-- > 0) {
-   				switch (info->portwidth) {
-   				case FLASH_CFI_8BIT:
- + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
- + 					flash_write8(mem_read8(src), dst);
- + #else
-   					flash_write8(flash_read8(src), dst);
- + #endif
-   					src += 1, dst += 1;
-   					break;
-   				case FLASH_CFI_16BIT:
- + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
- + 					flash_write16(mem_read16(src), dst);
- + #else
-   					flash_write16(flash_read16(src), dst);
- + #endif
-   					src += 2, dst += 2;
-   					break;
-   				case FLASH_CFI_32BIT:
- + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
- + 					flash_write32(mem_read32(src), dst);
- + #else
-   					flash_write32(flash_read32(src), dst);
- + #endif
-   					src += 4, dst += 4;
-   					break;
-   				case FLASH_CFI_64BIT:
- ***************
- *** 993,1011 ****
- --- 1112,1142 ----
-   		switch (info->portwidth) {
-   		case FLASH_CFI_8BIT:
-   			while (cnt-- > 0) {
- + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
- + 				flash_write8(mem_read8(src), dst);
- + #else
-   				flash_write8(flash_read8(src), dst);
- + #endif
-   				src += 1, dst += 1;
-   			}
-   			break;
-   		case FLASH_CFI_16BIT:
-   			while (cnt-- > 0) {
- + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
- + 				flash_write16(mem_read16(src), dst);
- + #else
-   				flash_write16(flash_read16(src), dst);
- + #endif
-   				src += 2, dst += 2;
-   			}
-   			break;
-   		case FLASH_CFI_32BIT:
-   			while (cnt-- > 0) {
- + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
- + 				flash_write32(mem_read32(src), dst);
- + #else
-   				flash_write32(flash_read32(src), dst);
- + #endif
-   				src += 4, dst += 4;
-   			}
-   			break;
- ***************
- *** 1256,1261 ****
- --- 1387,1417 ----
-   		info->buffer_size);
-   	}
-   
- + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
- + 	printf ("  Number of banks: %ld\n", CONFIG_FLASH_CKB_BANKS);
- + 	int bank = 0;
- + 	for (i = 0; i < info->sector_count; ++i) {
- + 		if (ctrlc())
- + 			break;
- + 		if(info->start[i] % CONFIG_FLASH_CKB_BANK_SIZE == 0)
- + 		{
- + 			printf ("\nBank# %ld: ", bank++);
- + 			//puts ("\n  Sector Start Addresses:");
- + 		}
- + 		
- + #ifdef CONFIG_SYS_FLASH_EMPTY_INFO
- + 		/* print empty and read-only info */
- + 		printf ("  %08lX %c %s ",
- + 			(info->start[i] & (CONFIG_FLASH_CKB_BANK_SIZE-1)) | CONFIG_SYS_FLASH_BASE,
- + 			sector_erased(info, i) ? 'E' : ' ',
- + 			info->protect[i] ? "RO" : "  ");
- + #else	/* ! CONFIG_SYS_FLASH_EMPTY_INFO */
- + 		printf ("  %08lX   %s ",
- + 			(info->start[i] & (CONFIG_FLASH_CKB_BANK_SIZE-1)) | CONFIG_SYS_FLASH_BASE,
- + 			info->protect[i] ? "RO" : "  ");
- + #endif
- + 	}
- + #else
-   	puts ("\n  Sector Start Addresses:");
-   	for (i = 0; i < info->sector_count; ++i) {
-   		if (ctrlc())
- ***************
- *** 1274,1279 ****
- --- 1430,1436 ----
-   			info->protect[i] ? "RO" : "  ");
-   #endif
-   	}
- + #endif
-   	putc ('\n');
-   	return;
-   }
- diff -crN u-boot-2012.10_o/include/configs/ckb_3352.h u-boot-2012.10/include/configs/ckb_3352.h
- *** u-boot-2012.10_o/include/configs/ckb_3352.h	1970-01-01 09:00:00.000000000 +0900
- --- u-boot-2012.10/include/configs/ckb_3352.h	2014-03-28 11:36:47.664423000 +0900
- ***************
- *** 0 ****
- --- 1,347 ----
- + /*
- +  * ckb_3352.h
- +  *
- +  * Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
- +  *
- +  * This program is free software; you can redistribute it and/or
- +  * modify it under the terms of the GNU General Public License as
- +  * published by the Free Software Foundation version 2.
- +  *
- +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- +  * kind, whether express or implied; without even the implied warranty
- +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- +  * GNU General Public License for more details.
- +  */
- + 
- + #ifndef __CONFIG_CKB_3352_H
- + #define __CONFIG_CKB_3352_H
- + 
- + #define CONFIG_AM33XX
- + 
- + #include <asm/arch/cpu.h>
- + #include <asm/arch/hardware.h>
- + 
- + /* LCD type (Use NO for undefining them). Do not remove or comment them */
- + #define CONFIG_CKB_LCD_01
- + #define CONFIG_CKB_NO_LCD_02
- + /* DVI support (Use NO for undefining this) Do not remove or comment this */
- + #define CONFIG_CKB_DVI
- + 
- + #define CONFIG_REDUCE_UBOOT_SIZE
- + 
- + #define CONFIG_DMA_COHERENT
- + #define CONFIG_DMA_COHERENT_SIZE	(1 << 20)
- + 
- + #define CONFIG_MACH_CKB_3352
- + 
- + #define CONFIG_CMDLINE_EDITING
- + #define CONFIG_SYS_LONGHELP		/* undef to save memory */
- + #define CONFIG_SYS_PROMPT		"U-Boot > "
- + #undef CONFIG_SYS_NO_FLASH
- + #define CONFIG_MACH_TYPE			4744	/* should match the machine type in the kernel (arch/arm/tools/mach-types.h) */
- + 
- + #define CONFIG_OF_LIBFDT
- + #define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
- + #define CONFIG_SETUP_MEMORY_TAGS
- + #define CONFIG_INITRD_TAG
- + 
- + #define CONFIG_SYS_CACHELINE_SIZE       64
- + 
- + #define CONFIG_CMD_ECHO
- + 
- + /* commands to include */
- + #include <config_cmd_default.h>
- + 
- + #undef CONFIG_CMD_ENV
- + #undef CONFIG_CMD_ASKENV
- + #undef CONFIG_CMD_LOADS
- + #undef CONFIG_CMD_SAVES
- + 
- + #undef CONFIG_USE_SPIFLASH
- + #undef	CONFIG_USE_NAND
- + #define CONFIG_SYS_USE_NOR
- + #define CONFIG_USE_NOR
- + #define CONFIG_NOR
- + 
- + #define CONFIG_NO_RELOCATE_UBOOT
- + /*
- +  * NOR Size = 16 MB
- +  * No.Of Sectors/Blocks = 128
- +  * Sector Size = 128 KB
- +  * Word lenght = 16 bits
- +  */
- + #ifdef CONFIG_SYS_USE_NOR
- + #define CONFIG_FLASH_SHOW_PROGRESS		45
- + #define CONFIG_ENV_IS_IN_FLASH
- + 
- + #undef CONFIG_SYS_NO_FLASH
- + #define CONFIG_SYS_MAX_FLASH_BANKS		1 /* max number of flash banks */
- + 
- + #define CONFIG_FLASH_CFI_DRIVER
- + #define CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
- + #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
- + #define CONFIG_FLASH_CKB_BANKS			128
- + #define CONFIG_FLASH_CKB_BANK_SIZE		0x20000
- + #define CONFIG_SYS_FLASH_CFI
- + #define CONFIG_SYS_MAX_FLASH_SECT	128
- + #define CONFIG_SYS_FLASH_BASE		0x08000000
- + #define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
- + //#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
- + #ifndef CONFIG_REDUCE_UBOOT_SIZE
- + #define CONFIG_MTD_DEVICE
- + #define CONFIG_FLASH_CFI_MTD
- + #endif
- + #define CONFIG_CMD_FLASH
- + #define CONFIG_SYS_FLASH_PROTECTION
- + #define CONFIG_SYS_FLASH_CFI_AMD_RESET
- + #define CONFIG_SYS_FLASH_SECT_SZ		(128 << 10) /* 128KB */
- + #define CONFIG_ENV_OFFSET				0xE0000
- + #define CONFIG_ENV_SIZE					(2 << 10)
- + 
- + #define CONFIG_ENV_SECT_SIZE			CONFIG_SYS_FLASH_SECT_SZ
- + 
- + #endif
- + 
- + #ifdef CONFIG_REDUCE_UBOOT_SIZE
- + #undef CONFIG_CMD_BDI
- + #undef CONFIG_CMD_BOOTD
- + #undef CONFIG_CMD_CONSOLE
- + #undef CONFIG_CMD_ECHO
- + #undef CONFIG_CMD_FPGA
- + #undef CONFIG_CMD_IMI
- + #undef CONFIG_CMD_ITEST
- + #undef CONFIG_CMD_IMLS
- + //#undef CONFIG_CMD_LOADS
- + #undef CONFIG_CMD_MISC
- + #undef CONFIG_CMD_NET
- + #undef CONFIG_CMD_NFS
- + #undef CONFIG_CMD_SETGETDCR
- + #undef CONFIG_CMD_SOURCE
- + #undef CONFIG_CMD_XIMG
- + #undef CONFIG_CMD_CRC32
- + #undef CONFIG_CMD_EXPORTENV
- + #undef CONFIG_CMD_GO
- + #undef CONFIG_CMD_IMPORTENV
- + #undef CONFIG_BOOTM_NETBSD
- + #undef CONFIG_BOOTM_RTEMS
- + #undef CONFIG_GZIP
- + #undef CONFIG_ZLIB
- + #undef CONFIG_PARTITIONS
- + #endif
- + #define CONFIG_AUTO_COMPLETE
- + 
- + #ifndef CONFIG_REDUCE_UBOOT_SIZE
- + #define CONFIG_CMD_ASKENV
- + #define CONFIG_VERSION_VARIABLE
- + #endif
- + 
- + #define CONFIG_BOOTARGS				"console=ttyO0,115200n8"
- + #define CONFIG_BOOTDELAY			3
- + #define CONFIG_ZERO_BOOTDELAY_CHECK	
- + #define CONFIG_BOOTCOMMAND			CKB_NOR_BOOTCOMMAND
- + 
- + #define CONFIG_USE_ARCH_MEMCPY
- + #define CONFIG_USE_ARCH_MEMSET
- + 
- + /* Clock Defines */
- + #define V_OSCK				24000000  /* Clock output from T2 */
- + #define V_SCLK				(V_OSCK)
- + 
- + /* max number of command args */
- + #define CONFIG_SYS_MAXARGS		16
- + 
- + /* Console I/O Buffer Size */
- + #define CONFIG_SYS_CBSIZE		512
- + 
- + /* Print Buffer Size */
- + #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE \
- + 					+ sizeof(CONFIG_SYS_PROMPT) + 16)
- + 
- + /* Boot Argument Buffer Size */
- + #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
- + 
- + /*
- +  * memtest works on 8 MB in DRAM after skipping 32MB from
- +  * start addr of ram disk
- +  */
- + #define CONFIG_SYS_MEMTEST_START	(PHYS_DRAM_1 + (64 * 1024 * 1024))
- + #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START \
- + 					+ (8 * 1024 * 1024))
- + 
- + #define CONFIG_SYS_LOAD_ADDR		0x80007FC0 /* Default load address */
- + #define CONFIG_SYS_HZ				1000 /* 1ms clock */
- + 
- + #define CONFIG_MMC
- + #define CONFIG_GENERIC_MMC
- + #define CONFIG_OMAP_HSMMC
- + #define CONFIG_PARTITIONS
- + 
- + #ifdef CONFIG_MMC
- + #define CONFIG_CMD_MMC
- + #define CONFIG_DOS_PARTITION
- + #define CONFIG_CMD_FAT
- + #define CONFIG_CMD_EXT2
- + #endif
- + 
- + /* CPSW ethernet */
- + #if 0
- + #define CONFIG_CMD_NET
- + #define CONFIG_CMD_DHCP
- + #define CONFIG_CMD_PING
- + #define CONFIG_BOOTP_DEFAULT
- + #define CONFIG_BOOTP_DNS
- + #define CONFIG_BOOTP_DNS2
- + #define CONFIG_BOOTP_SEND_HOSTNAME
- + #define CONFIG_BOOTP_GATEWAY
- + #define CONFIG_BOOTP_SUBNETMASK
- + #define CONFIG_NET_RETRY_COUNT         10
- + #define CONFIG_NET_MULTI
- + #define CONFIG_PHY_GIGE
- + #define CONFIG_PHYLIB
- + #define CONFIG_PHY_SMSC
- + #else
- + //#undef CONFIG_CMD_NET
- + #undef CONFIG_CMD_NFS
- + #endif
- + 
- +  /* Physical Memory Map */
- + #define CONFIG_NR_DRAM_BANKS		1		/*  1 bank of DRAM */
- + #define PHYS_DRAM_1			0x80000000	/* DRAM Bank #1 */
- + #define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
- + 
- + #define CONFIG_SYS_SDRAM_BASE		PHYS_DRAM_1
- + #define CONFIG_SYS_INIT_SP_ADDR         (NON_SECURE_SRAM_END - \
- + 						GENERATED_GBL_DATA_SIZE)
- + #define CONFIG_SYS_SDRAM_SIZE		0x08000000					/* 128MB */
- + 
- +  /* Platform/Board specific defs */
- + #define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
- + #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
- + #define CONFIG_SYS_HZ			1000
- + 
- + /* NS16550 Configuration */
- + #define CONFIG_SYS_NS16550
- + #define CONFIG_SYS_NS16550_SERIAL
- + #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
- + #define CONFIG_SYS_NS16550_CLK		(48000000)
- + #define CONFIG_SYS_NS16550_COM1		0x44e09000	/* Base EVM has UART0 */
- + 
- + #ifdef CONFIG_CKB_DVI
- + /* I2C Configuration */
- + #define CONFIG_I2C
- + #define CONFIG_CMD_I2C
- + #define CONFIG_HARD_I2C
- + #define CONFIG_SYS_I2C_SPEED		100000
- + #define CONFIG_SYS_I2C_SLAVE		1
- + #define CONFIG_I2C_MULTI_BUS
- + #define CONFIG_DRIVER_OMAP24XX_I2C
- + #endif
- + 
- + #ifndef CONFIG_REDUCE_UBOOT_SIZE
- + /* I2C Configuration */
- + #define CONFIG_I2C
- + #define CONFIG_CMD_I2C
- + #define CONFIG_HARD_I2C
- + #define CONFIG_SYS_I2C_SPEED		100000
- + #define CONFIG_SYS_I2C_SLAVE		1
- + #define CONFIG_I2C_MULTI_BUS
- + #define CONFIG_DRIVER_OMAP24XX_I2C
- + #define CONFIG_CMD_EEPROM
- + #define CONFIG_ENV_EEPROM_IS_ON_I2C
- + #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Main EEPROM */
- + #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
- + #define CONFIG_SYS_I2C_MULTI_EEPROMS
- + #endif
- + 
- + #define CONFIG_OMAP_GPIO
- + 
- + #define CONFIG_BAUDRATE		115200
- + #define CONFIG_SYS_BAUDRATE_TABLE	{ 110, 300, 600, 1200, 2400, \
- + 4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 }
- + 
- + /*
- +  * select serial console configuration
- +  */
- + #define CONFIG_SERIAL1			1
- + #define CONFIG_CONS_INDEX		1
- + #define CONFIG_SYS_CONSOLE_INFO_QUIET
- + 
- + //#define  CONFIG_SPL_BUILD
- + 
- + #define CONFIG_SYS_TEXT_BASE		0x87500000
- + #define UBOOT_NOR_BASE_ADDR 		0x08020000		/* address of U-Boot on NOR flash */
- + 
- + #define CONFIG_SYS_MALLOC_LEN		(0x100000)
- + #define CONFIG_STACKSIZE			(256*1024) /* regular stack */
- + 
- + #define CONFIG_SKIP_LOWLEVEL_INIT
- + 
- + /* Unsupported features */
- + #undef CONFIG_USE_IRQ
- + 
- + /* Specific ENV defines */
- + #define KERNEL_LOAD_ADDRESS			"0x80007FC0"		/* This address will eliminate re-copying the kernel code by U-Boot */
- + #define CKB_KERN_MIN_SIZE			0x020000					/* Min size of the kernel image (just a rough value) */
- + #define CKB_KERN_MAX_SIZE			0xE00000					/* Max size of the kernel image 14 MB */
- + #define CKB_NOR_BOOTCOMMAND			"fread_kernel "KERNEL_LOAD_ADDRESS"; bootm "KERNEL_LOAD_ADDRESS
- + #define CKB_MMC_BOOTCOMMAND			"mmc rescan 0; fatload mmc 0:1 "KERNEL_LOAD_ADDRESS" /uImage.bin; bootm "KERNEL_LOAD_ADDRESS
- + #define MAX_LCD_IMAGE_FILE_SIZE		0x60000			/* 3 flash blocks */
- + #define MAX_BOOTLOADER_FILE_SIZE		0x10000 		/* 64Kb */
- + 
- + #ifdef CONFIG_MMC
- + #define CKB_MMC_BOOT_CMD		"mmcboot="CKB_MMC_BOOTCOMMAND"\0"
- + #else
- + #define CKB_MMC_BOOT_CMD
- + #endif
- + 
- + #ifdef CONFIG_DRIVER_TI_EMAC
- + #define CKB_NET_ENVS	"serverip=192.168.0.1\0" \
- + 							"netmask=255.255.255.0\0" \
- + 							"ipaddr=192.168.0.xx\0" \
- + 							"gatewayip=192.168.0.1\0" \
- + 							"manual_ethaddr=Set ethaddr manually. Eg: set ethaddr 00:e0:22:fe:41:4d. It can be set only once.\0"
- + #else
- + #define CKB_NET_ENVS
- + #endif
- + 
- + #define CONFIG_EXTRA_ENV_SETTINGS \
- + 	"norboot="CKB_NOR_BOOTCOMMAND"\0" \
- + 	"r=bootm "KERNEL_LOAD_ADDRESS"\0" \
- + 	CKB_MMC_BOOT_CMD \
- + 	CKB_NET_ENVS
- + 	
- + #define DA8XX_LCD_CNTRL_BASE		0x4830E000
- + #define LCD_IMAGE_ADDRESS			0x08080000
- + 
- + #if defined(CONFIG_CKB_DVI)
- + #define CONFIG_FB_MAP_SIZE			0x500000			/* Approx 4MB (1366x768 max (DVI)) */
- + #elif defined(CONFIG_CKB_LCD_01) || defined(CONFIG_CKB_LCD_02)
- + #define CONFIG_FB_MAP_SIZE			0x200000			/* 2MB */
- + #else
- + #define CONFIG_FB_MAP_SIZE			0
- + #endif
- + 
- + #if defined(CONFIG_CKB_LCD_01) || defined(CONFIG_CKB_LCD_02) || defined(CONFIG_CKB_DVI) 
- + #define CONFIG_FB_BASE_ADDRESS		(CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE-CONFIG_FB_MAP_SIZE)		/* lower SDRAM (1MB aligned) */
- + #endif
- + 
- + /* Note: The FB Palette is located just above the FB address. Because it
- +    takes up only 32bytes, it's ok not to reserve this memory as 
- +    UBOOT_TEMP_ADDR will take care of this.
- +    This case is only when the Palette is used */ 
- + 
- + #define MAX_UBOOT_SIZE				0x60000			/* max uboot size (used for erasing flash while flashing U-Boot) */
- + 
- + /* memory that is hidden from U-boot (refer board.c) */
- + #define CONFIG_CKB_RESERVED_MEM		(MAX_UBOOT_SIZE)
- +  /* Memory to be hidden from Kernel */
- + #define CONFIG_SYS_MEM_TOP_HIDE		(CONFIG_FB_MAP_SIZE)
- + 
- + /* addr where U-boot will be copied for flashing */
- + #define UBOOT_TEMP_ADDR				(CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE-(CONFIG_SYS_MEM_TOP_HIDE+CONFIG_CKB_RESERVED_MEM))
- + 
- + #define FLASH_UBOOT_CMD_STR				"flash_uboot"
- + 
- + #endif	/* ! __CONFIG_CKB_3352_H */
- + 
- + 
--- 0 ----
diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-3352/patches/uboot-2012.10-20141125.patch buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-3352/patches/uboot-2012.10-20141125.patch
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-3352/patches/uboot-2012.10-20141125.patch	1970-01-01 09:00:00.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-3352/patches/uboot-2012.10-20141125.patch	2014-11-25 15:27:02.000000000 +0900
***************
*** 0 ****
--- 1,6174 ----
+ diff -crN u-boot-2012.10_o/arch/arm/cpu/armv7/ckb_3352/ckb_3352.c u-boot-2012.10/arch/arm/cpu/armv7/ckb_3352/ckb_3352.c
+ *** u-boot-2012.10_o/arch/arm/cpu/armv7/ckb_3352/ckb_3352.c	1970-01-01 09:00:00.000000000 +0900
+ --- u-boot-2012.10/arch/arm/cpu/armv7/ckb_3352/ckb_3352.c	2014-02-27 11:33:16.720633268 +0900
+ ***************
+ *** 0 ****
+ --- 1,138 ----
+ + /*
+ +  * board.c
+ +  *
+ +  * Common board functions for CKB-3352 board
+ +  *
+ +  * Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation; either version 2 of
+ +  * the License, or (at your option) any later version.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #include <common.h>
+ + #include <errno.h>
+ + #include <asm/arch/cpu.h>
+ + #include <asm/arch/hardware.h>
+ + #include <asm/arch/omap.h>
+ + #include <asm/arch/ddr_defs.h>
+ + #include <asm/arch/clock.h>
+ + #include <asm/arch/gpio.h>
+ + #include <asm/arch/mem.h>
+ + #include <asm/arch/mmc_host_def.h>
+ + #include <asm/arch/sys_proto.h>
+ + #include <asm/io.h>
+ + #include <asm/emif.h>
+ + #include <asm/gpio.h>
+ + #include <asm/errno.h>
+ + 
+ + 
+ + DECLARE_GLOBAL_DATA_PTR;
+ + 
+ + struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+ + struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
+ + 
+ + static const struct gpio_bank gpio_bank_am33xx[4] = {
+ + 	{ (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
+ + 	{ (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
+ + 	{ (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
+ + 	{ (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
+ + };
+ + 
+ + const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
+ + 
+ + #if defined(CONFIG_OMAP_HSMMC)
+ + int board_mmc_init(bd_t *bis)
+ + {
+ + 	int ret;
+ + 	
+ + 	ret = omap_mmc_init(0, 0, 0);
+ + 	if (ret)
+ + 		return ret;
+ + #if 0
+ + 	return omap_mmc_init(1, 0, 0);
+ + #else
+ + 	return ret;
+ + #endif
+ + }
+ + #endif
+ + 
+ + void setup_clocks_for_console(void)
+ + {
+ + 	/* Not yet implemented */
+ + 	return;
+ + }
+ + 
+ + 
+ + int arch_misc_init(void)
+ + {
+ + 	return 0;
+ + }
+ + 
+ + /*
+ +  * early system init of muxing and clocks.
+ +  */
+ + void s_init(void)
+ + {
+ + 	/* WDT1 is already running when the bootloader gets control
+ + 	 * Disable it to avoid "random" resets
+ + 	 */
+ + 	writel(0xAAAA, &wdtimer->wdtwspr);
+ + 	while (readl(&wdtimer->wdtwwps) != 0x0)
+ + 		;
+ + 	writel(0x5555, &wdtimer->wdtwspr);
+ + 	while (readl(&wdtimer->wdtwwps) != 0x0)
+ + 		;
+ + 	
+ + }
+ + 
+ + 
+ + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
+ + int ckb_3352_cur_flash_bank = -1;
+ + void set_nor_flash_bank(int bank)
+ + {
+ + 	void *reg = gpio_bank_am33xx[1].base + OMAP_GPIO_DATAOUT;
+ + 	__raw_writel((__raw_readl(reg) & (~(0x7F<<20))) | (bank<<20), reg);
+ + 	//printf("Setting Nor GPIO bank to %d\n", bank);
+ + 	ckb_3352_cur_flash_bank = bank;
+ + }
+ + 
+ + /* GPIO bank 1 [20~26] should be configured as output */
+ + void init_nor_flash_GPIO()
+ + {
+ + 	void *reg = gpio_bank_am33xx[1].base + OMAP_GPIO_OE;
+ + 	__raw_writel(__raw_readl(reg) & (~(0x7F<<20)), reg);
+ + 	/* select bank 0 */
+ + 	set_nor_flash_bank(0);
+ + }
+ + #endif
+ + 
+ + 
+ + /*
+ +  * Basic board specific setup.  Pinmux has been handled already.
+ +  */
+ + int board_init(void)
+ + {
+ + 	/* Setup the PLLs and the clocks for the peripherals */
+ + 	enable_board_pin_mux();
+ + 
+ + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER	
+ + 	/* configure NOT flash GPIO pins */
+ + 	init_nor_flash_GPIO();
+ + #endif
+ + 	
+ + #ifdef CONFIG_ALL_PLL
+ + 	pll_init();
+ + #endif
+ + 
+ + 	gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
+ + 
+ + 	return 0;
+ + }
+ + 
+ diff -crN u-boot-2012.10_o/arch/arm/cpu/armv7/ckb_3352/clock.c u-boot-2012.10/arch/arm/cpu/armv7/ckb_3352/clock.c
+ *** u-boot-2012.10_o/arch/arm/cpu/armv7/ckb_3352/clock.c	1970-01-01 09:00:00.000000000 +0900
+ --- u-boot-2012.10/arch/arm/cpu/armv7/ckb_3352/clock.c	2014-02-27 11:33:16.720633268 +0900
+ ***************
+ *** 0 ****
+ --- 1,389 ----
+ + /*
+ +  * clock.c
+ +  *
+ +  * clocks for CKB-3352 board
+ +  *
+ +  * Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation; either version 2 of
+ +  * the License, or (at your option) any later version.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #include <common.h>
+ + #include <asm/arch/cpu.h>
+ + #include <asm/arch/clock.h>
+ + #include <asm/arch/hardware.h>
+ + #include <asm/io.h>
+ + 
+ + #define PRCM_MOD_EN		0x2
+ + #define PRCM_FORCE_WAKEUP	0x2
+ + #define PRCM_FUNCTL		0x0
+ + 
+ + #define PRCM_EMIF_CLK_ACTIVITY	BIT(2)
+ + #define PRCM_L3_GCLK_ACTIVITY	BIT(4)
+ + 
+ + #define PLL_BYPASS_MODE		0x4
+ + #define ST_MN_BYPASS		0x00000100
+ + #define ST_DPLL_CLK		0x00000001
+ + #define CLK_SEL_MASK		0x7ffff
+ + #define CLK_DIV_MASK		0x1f
+ + #define CLK_DIV2_MASK		0x7f
+ + #define CLK_SEL_SHIFT		0x8
+ + #define CLK_MODE_SEL		0x7
+ + #define CLK_MODE_MASK		0xfffffff8
+ + #define CLK_DIV_SEL		0xFFFFFFE0
+ + #define CPGMAC0_IDLE		0x30000
+ + #define DPLL_CLKDCOLDO_GATE_CTRL        0x300
+ + 
+ + const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
+ + const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
+ + const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
+ + const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC;
+ + 
+ + #ifdef CONFIG_ALL_PLL
+ + static void enable_interface_clocks(void)
+ + {
+ + 	/* Enable all the Interconnect Modules */
+ + 	writel(PRCM_MOD_EN, &cmper->l3clkctrl);
+ + 	while (readl(&cmper->l3clkctrl) != PRCM_MOD_EN)
+ + 		;
+ + 
+ + 	writel(PRCM_MOD_EN, &cmper->l4lsclkctrl);
+ + 	while (readl(&cmper->l4lsclkctrl) != PRCM_MOD_EN)
+ + 		;
+ + 
+ + 	writel(PRCM_MOD_EN, &cmper->l4fwclkctrl);
+ + 	while (readl(&cmper->l4fwclkctrl) != PRCM_MOD_EN)
+ + 		;
+ + 
+ + 	writel(PRCM_MOD_EN, &cmwkup->wkl4wkclkctrl);
+ + 	while (readl(&cmwkup->wkl4wkclkctrl) != PRCM_MOD_EN)
+ + 		;
+ + 
+ + 	writel(PRCM_MOD_EN, &cmper->l3instrclkctrl);
+ + 	while (readl(&cmper->l3instrclkctrl) != PRCM_MOD_EN)
+ + 		;
+ + 
+ + 	writel(PRCM_MOD_EN, &cmper->l4hsclkctrl);
+ + 	while (readl(&cmper->l4hsclkctrl) != PRCM_MOD_EN)
+ + 		;
+ + 
+ + 	writel(PRCM_MOD_EN, &cmwkup->wkgpio0clkctrl);
+ + 	while (readl(&cmwkup->wkgpio0clkctrl) != PRCM_MOD_EN)
+ + 		;
+ + }
+ + 
+ + /*
+ +  * Force power domain wake up transition
+ +  * Ensure that the corresponding interface clock is active before
+ +  * using the peripheral
+ +  */
+ + static void power_domain_wkup_transition(void)
+ + {
+ + 	writel(PRCM_FORCE_WAKEUP, &cmper->l3clkstctrl);
+ + 	writel(PRCM_FORCE_WAKEUP, &cmper->l4lsclkstctrl);
+ + 	writel(PRCM_FORCE_WAKEUP, &cmwkup->wkclkstctrl);
+ + 	writel(PRCM_FORCE_WAKEUP, &cmper->l4fwclkstctrl);
+ + 	writel(PRCM_FORCE_WAKEUP, &cmper->l3sclkstctrl);
+ + }
+ + 
+ + /*
+ +  * Enable the peripheral clock for required peripherals
+ +  */
+ + static void enable_per_clocks(void)
+ + {
+ + 	/* Enable the control module though RBL would have done it*/
+ + 	writel(PRCM_MOD_EN, &cmwkup->wkctrlclkctrl);
+ + 	while (readl(&cmwkup->wkctrlclkctrl) != PRCM_MOD_EN)
+ + 		;
+ + 
+ + 	/* Enable the module clock */
+ + 	writel(PRCM_MOD_EN, &cmper->timer2clkctrl);
+ + 	while (readl(&cmper->timer2clkctrl) != PRCM_MOD_EN)
+ + 		;
+ + 
+ + 	/* Select the Master osc 24 MHZ as Timer2 clock source */
+ + 	writel(0x1, &cmdpll->clktimer2clk);
+ + 
+ + 	/* UART0 */
+ + 	writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl);
+ + 	while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
+ + 		;
+ + 
+ + 	/* GPMC */
+ + 	writel(PRCM_MOD_EN, &cmper->gpmcclkctrl);
+ + 	while (readl(&cmper->gpmcclkctrl) != PRCM_MOD_EN)
+ + 		;
+ + 
+ + 	/* ELM */
+ + 	writel(PRCM_MOD_EN, &cmper->elmclkctrl);
+ + 	while (readl(&cmper->elmclkctrl) != PRCM_MOD_EN)
+ + 		;
+ + 
+ + 	/* MMC0*/
+ + 	writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
+ + 	while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
+ + 		;
+ + 
+ + 	/* i2c0 */
+ + 	writel(PRCM_MOD_EN, &cmwkup->wkup_i2c0ctrl);
+ + 	while (readl(&cmwkup->wkup_i2c0ctrl) != PRCM_MOD_EN)
+ + 		;
+ + 
+ + 	/* gpio1 module */
+ + 	writel(PRCM_MOD_EN, &cmper->gpio1clkctrl);
+ + 	while (readl(&cmper->gpio1clkctrl) != PRCM_MOD_EN)
+ + 		;
+ + 
+ + 	/* gpio2 module */
+ + 	writel(PRCM_MOD_EN, &cmper->gpio2clkctrl);
+ + 	while (readl(&cmper->gpio2clkctrl) != PRCM_MOD_EN)
+ + 		;
+ + 
+ + 	/* gpio3 module */
+ + 	writel(PRCM_MOD_EN, &cmper->gpio3clkctrl);
+ + 	while (readl(&cmper->gpio3clkctrl) != PRCM_MOD_EN)
+ + 		;
+ + 
+ + 	/* i2c1 */
+ + 	writel(PRCM_MOD_EN, &cmper->i2c1clkctrl);
+ + 	while (readl(&cmper->i2c1clkctrl) != PRCM_MOD_EN)
+ + 		;
+ + 
+ + 	/* Ethernet */
+ + 	writel(PRCM_MOD_EN, &cmper->cpgmac0clkctrl);
+ + 	while ((readl(&cmper->cpgmac0clkctrl) & CPGMAC0_IDLE) != PRCM_FUNCTL)
+ + 		;
+ + 
+ + 	/* spi0 */
+ + 	writel(PRCM_MOD_EN, &cmper->spi0clkctrl);
+ + 	while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN)
+ + 		;
+ + 
+ + 	/* MUSB */
+ + 	writel(PRCM_MOD_EN, &cmper->usb0clkctrl);
+ + 	while (readl(&cmper->usb0clkctrl) != PRCM_MOD_EN)
+ + 		;
+ + 
+ + 	/* RTC */
+ + 	writel(PRCM_MOD_EN, &cmrtc->rtcclkctrl);
+ + 	while (readl(&cmrtc->rtcclkctrl) != PRCM_MOD_EN)
+ + 		;
+ + }
+ + 
+ + void mpu_pll_config(int mpupll_M)
+ + {
+ + 	u32 clkmode, clksel, div_m2;
+ + 
+ + 	clkmode = readl(&cmwkup->clkmoddpllmpu);
+ + 	clksel = readl(&cmwkup->clkseldpllmpu);
+ + 	div_m2 = readl(&cmwkup->divm2dpllmpu);
+ + 
+ + 	/* Set the PLL to bypass Mode */
+ + 	writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllmpu);
+ + 	while (readl(&cmwkup->idlestdpllmpu) != ST_MN_BYPASS)
+ + 		;
+ + 
+ + 	clksel = clksel & (~CLK_SEL_MASK);
+ + 	clksel = clksel | ((mpupll_M << CLK_SEL_SHIFT) | MPUPLL_N);
+ + 	writel(clksel, &cmwkup->clkseldpllmpu);
+ + 
+ + 	div_m2 = div_m2 & ~CLK_DIV_MASK;
+ + 	div_m2 = div_m2 | MPUPLL_M2;
+ + 	writel(div_m2, &cmwkup->divm2dpllmpu);
+ + 
+ + 	clkmode = clkmode | CLK_MODE_SEL;
+ + 	writel(clkmode, &cmwkup->clkmoddpllmpu);
+ + 
+ + 	while (readl(&cmwkup->idlestdpllmpu) != ST_DPLL_CLK)
+ + 		;
+ + }
+ + 
+ + static void core_pll_config(void)
+ + {
+ + 	u32 clkmode, clksel, div_m4, div_m5, div_m6;
+ + 
+ + 	clkmode = readl(&cmwkup->clkmoddpllcore);
+ + 	clksel = readl(&cmwkup->clkseldpllcore);
+ + 	div_m4 = readl(&cmwkup->divm4dpllcore);
+ + 	div_m5 = readl(&cmwkup->divm5dpllcore);
+ + 	div_m6 = readl(&cmwkup->divm6dpllcore);
+ + 
+ + 	/* Set the PLL to bypass Mode */
+ + 	writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllcore);
+ + 
+ + 	while (readl(&cmwkup->idlestdpllcore) != ST_MN_BYPASS)
+ + 		;
+ + 
+ + 	clksel = clksel & (~CLK_SEL_MASK);
+ + 	clksel = clksel | ((COREPLL_M << CLK_SEL_SHIFT) | COREPLL_N);
+ + 	writel(clksel, &cmwkup->clkseldpllcore);
+ + 
+ + 	div_m4 = div_m4 & ~CLK_DIV_MASK;
+ + 	div_m4 = div_m4 | COREPLL_M4;
+ + 	writel(div_m4, &cmwkup->divm4dpllcore);
+ + 
+ + 	div_m5 = div_m5 & ~CLK_DIV_MASK;
+ + 	div_m5 = div_m5 | COREPLL_M5;
+ + 	writel(div_m5, &cmwkup->divm5dpllcore);
+ + 
+ + 	div_m6 = div_m6 & ~CLK_DIV_MASK;
+ + 	div_m6 = div_m6 | COREPLL_M6;
+ + 	writel(div_m6, &cmwkup->divm6dpllcore);
+ + 
+ + 	clkmode = clkmode | CLK_MODE_SEL;
+ + 	writel(clkmode, &cmwkup->clkmoddpllcore);
+ + 
+ + 	while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK)
+ + 		;
+ + }
+ + 
+ + static void per_pll_config(void)
+ + {
+ + 	u32 clkmode, clksel, div_m2;
+ + 
+ + 	clkmode = readl(&cmwkup->clkmoddpllper);
+ + 	clksel = readl(&cmwkup->clkseldpllper);
+ + 	div_m2 = readl(&cmwkup->divm2dpllper);
+ + 
+ + 	/* Set the PLL to bypass Mode */
+ + 	writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllper);
+ + 
+ + 	while (readl(&cmwkup->idlestdpllper) != ST_MN_BYPASS)
+ + 		;
+ + 
+ + 	clksel = clksel & (~CLK_SEL_MASK);
+ + 	clksel = clksel | ((PERPLL_M << CLK_SEL_SHIFT) | PERPLL_N);
+ + 	writel(clksel, &cmwkup->clkseldpllper);
+ + 
+ + 	div_m2 = div_m2 & ~CLK_DIV2_MASK;
+ + 	div_m2 = div_m2 | PERPLL_M2;
+ + 	writel(div_m2, &cmwkup->divm2dpllper);
+ + 
+ + 	clkmode = clkmode | CLK_MODE_SEL;
+ + 	writel(clkmode, &cmwkup->clkmoddpllper);
+ + 
+ + 	while (readl(&cmwkup->idlestdpllper) != ST_DPLL_CLK)
+ + 		;
+ + 
+ + 	writel(DPLL_CLKDCOLDO_GATE_CTRL, &cmwkup->clkdcoldodpllper);
+ + }
+ + 
+ + void ddr_pll_config(unsigned int ddrpll_m)
+ + {
+ + 	u32 clkmode, clksel, div_m2;
+ + 
+ + 	clkmode = readl(&cmwkup->clkmoddpllddr);
+ + 	clksel = readl(&cmwkup->clkseldpllddr);
+ + 	div_m2 = readl(&cmwkup->divm2dpllddr);
+ + 
+ + 	/* Set the PLL to bypass Mode */
+ + 	clkmode = (clkmode & CLK_MODE_MASK) | PLL_BYPASS_MODE;
+ + 	writel(clkmode, &cmwkup->clkmoddpllddr);
+ + 
+ + 	/* Wait till bypass mode is enabled */
+ + 	while ((readl(&cmwkup->idlestdpllddr) & ST_MN_BYPASS)
+ + 				!= ST_MN_BYPASS)
+ + 		;
+ + 
+ + 	clksel = clksel & (~CLK_SEL_MASK);
+ + 	clksel = clksel | ((ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N);
+ + 	writel(clksel, &cmwkup->clkseldpllddr);
+ + 
+ + 	div_m2 = div_m2 & CLK_DIV_SEL;
+ + 	div_m2 = div_m2 | DDRPLL_M2;
+ + 	writel(div_m2, &cmwkup->divm2dpllddr);
+ + 
+ + 	clkmode = (clkmode & CLK_MODE_MASK) | CLK_MODE_SEL;
+ + 	writel(clkmode, &cmwkup->clkmoddpllddr);
+ + 
+ + 	/* Wait till dpll is locked */
+ + 	while ((readl(&cmwkup->idlestdpllddr) & ST_DPLL_CLK) != ST_DPLL_CLK)
+ + 		;
+ + }
+ + 
+ + void enable_emif_clocks(void)
+ + {
+ + 	/* Enable the  EMIF_FW Functional clock */
+ + 	writel(PRCM_MOD_EN, &cmper->emiffwclkctrl);
+ + 	/* Enable EMIF0 Clock */
+ + 	writel(PRCM_MOD_EN, &cmper->emifclkctrl);
+ + 	/* Poll if module is functional */
+ + 	while ((readl(&cmper->emifclkctrl)) != PRCM_MOD_EN)
+ + 		;
+ + }
+ + 
+ + /*
+ +  * Configure the PLL/PRCM for necessary peripherals
+ +  */
+ + void pll_init()
+ + {
+ + 	/* Start at 550MHz, will be tweaked up if possible. */
+ + 	mpu_pll_config(MPUPLL_M_550);
+ + 	core_pll_config();
+ + 	per_pll_config();
+ + 
+ + 	/* Enable the required interconnect clocks */
+ + 	enable_interface_clocks();
+ + 
+ + 	/* Power domain wake up transition */
+ + 	power_domain_wkup_transition();
+ + 
+ + 	/* Enable the required peripherals */
+ + 	enable_per_clocks();
+ + }
+ + #endif
+ + 
+ + 
+ + void enable_lcd_clock(void)
+ + {
+ + 	writel(PRCM_MOD_EN, &cmper->lcdclkctrl);
+ + 	while (readl(&cmper->lcdclkctrl) != PRCM_MOD_EN)
+ + 		;
+ + }
+ + 
+ + 
+ + void lcd_power_domain_wkup_transition()
+ + {
+ + 	writel(PRCM_FORCE_WAKEUP, &cmper->lcdclkstctrl);
+ + }
+ + 
+ + void disp_pll_config()
+ + {
+ + 	volatile u32 clkmode, clksel, div_m2;
+ + 
+ + 	clkmode = readl(&cmwkup->clkmoddplldisp);
+ + 	clksel = readl(&cmwkup->clkseldplldisp);
+ + 	div_m2 = readl(&cmwkup->divm2dplldisp);
+ + 
+ + 	/* Set the PLL to bypass Mode */
+ + 	writel(PLL_BYPASS_MODE, &cmwkup->clkmoddplldisp);
+ + 	while (readl(&cmwkup->idlestdplldisp) != ST_MN_BYPASS)
+ + 		;
+ + 
+ + 	clksel = clksel & (~CLK_SEL_MASK);
+ + 	clksel = clksel | ((DISPPLL_M << CLK_SEL_SHIFT) | DISPPLL_N);
+ + 	writel(clksel, &cmwkup->clkseldplldisp);
+ + 
+ + 	div_m2 = div_m2 & ~CLK_DIV_MASK;
+ + 	div_m2 = div_m2 | DISPPLL_M2;
+ + 	writel(div_m2, &cmwkup->divm2dplldisp);
+ + 
+ + 	clkmode = clkmode | CLK_MODE_SEL;
+ + 	writel(clkmode, &cmwkup->clkmoddplldisp);
+ + 
+ + 	while (readl(&cmwkup->idlestdplldisp) != ST_DPLL_CLK)
+ + 		;
+ + 	
+ + 	lcd_power_domain_wkup_transition();
+ + 	
+ + 	enable_lcd_clock();
+ + 	
+ + }
+ diff -crN u-boot-2012.10_o/arch/arm/cpu/armv7/ckb_3352/config.mk u-boot-2012.10/arch/arm/cpu/armv7/ckb_3352/config.mk
+ *** u-boot-2012.10_o/arch/arm/cpu/armv7/ckb_3352/config.mk	1970-01-01 09:00:00.000000000 +0900
+ --- u-boot-2012.10/arch/arm/cpu/armv7/ckb_3352/config.mk	2014-02-27 11:33:16.731635581 +0900
+ ***************
+ *** 0 ****
+ --- 1,19 ----
+ + #
+ + # Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
+ + #
+ + # This program is free software; you can redistribute it and/or
+ + # modify it under the terms of the GNU General Public License as
+ + # published by the Free Software Foundation; either version 2 of
+ + # the License, or (at your option) any later version.
+ + #
+ + # This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ + # kind, whether express or implied; without even the implied warranty
+ + # of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ + # GNU General Public License for more details.
+ + #
+ + ifdef CONFIG_SPL_BUILD
+ + ALL-y	+= $(OBJTREE)/MLO
+ + ALL-$(CONFIG_SPL_SPI_SUPPORT) += $(OBJTREE)/MLO.byteswap
+ + else
+ + ALL-y	+= $(obj)u-boot.img
+ + endif
+ diff -crN u-boot-2012.10_o/arch/arm/cpu/armv7/ckb_3352/ddr.c u-boot-2012.10/arch/arm/cpu/armv7/ckb_3352/ddr.c
+ *** u-boot-2012.10_o/arch/arm/cpu/armv7/ckb_3352/ddr.c	1970-01-01 09:00:00.000000000 +0900
+ --- u-boot-2012.10/arch/arm/cpu/armv7/ckb_3352/ddr.c	2014-02-27 11:33:16.731635581 +0900
+ ***************
+ *** 0 ****
+ --- 1,119 ----
+ + /*
+ +  * DDR Configuration for CKB-3352.
+ +  *
+ +  * Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation; either version 2 of
+ +  * the License, or (at your option) any later version.
+ +  *
+ +  * This program is distributed .as is. WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #include <asm/arch/cpu.h>
+ + #include <asm/arch/ddr_defs.h>
+ + #include <asm/arch/sys_proto.h>
+ + #include <asm/io.h>
+ + #include <asm/emif.h>
+ + 
+ + 
+ + /**
+ +  * Base address for EMIF instances
+ +  */
+ + static struct emif_reg_struct *emif_reg = {
+ + 				(struct emif_reg_struct *)EMIF4_0_CFG_BASE};
+ + 
+ + /**
+ +  * Base address for DDR instance
+ +  */
+ + static struct ddr_regs *ddr_reg[2] = {
+ + 				(struct ddr_regs *)DDR_PHY_BASE_ADDR,
+ + 				(struct ddr_regs *)DDR_PHY_BASE_ADDR2};
+ + 
+ + /**
+ +  * Base address for ddr io control instances
+ +  */
+ + static struct ddr_cmdtctrl *ioctrl_reg = {
+ + 			(struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
+ + 
+ + /**
+ +  * Configure SDRAM
+ +  */
+ + void config_sdram(const struct emif_regs *regs)
+ + {
+ + 	writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl);
+ + 	writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw);
+ + 	if (regs->zq_config){
+ + 		writel(regs->zq_config, &emif_reg->emif_zq_config);
+ + 		writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
+ + 	}
+ + 	writel(regs->sdram_config, &emif_reg->emif_sdram_config);
+ + }
+ + 
+ + /**
+ +  * Set SDRAM timings
+ +  */
+ + void set_sdram_timings(const struct emif_regs *regs)
+ + {
+ + 	writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1);
+ + 	writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1_shdw);
+ + 	writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2);
+ + 	writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2_shdw);
+ + 	writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3);
+ + 	writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3_shdw);
+ + }
+ + 
+ + /**
+ +  * Configure DDR PHY
+ +  */
+ + void config_ddr_phy(const struct emif_regs *regs)
+ + {
+ + 	writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1);
+ + 	writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1_shdw);
+ + }
+ + 
+ + /**
+ +  * Configure DDR CMD control registers
+ +  */
+ + void config_cmd_ctrl(const struct cmd_control *cmd)
+ + {
+ + 	writel(cmd->cmd0csratio, &ddr_reg[0]->cm0csratio);
+ + 	writel(cmd->cmd0dldiff, &ddr_reg[0]->cm0dldiff);
+ + 	writel(cmd->cmd0iclkout, &ddr_reg[0]->cm0iclkout);
+ + 
+ + 	writel(cmd->cmd1csratio, &ddr_reg[0]->cm1csratio);
+ + 	writel(cmd->cmd1dldiff, &ddr_reg[0]->cm1dldiff);
+ + 	writel(cmd->cmd1iclkout, &ddr_reg[0]->cm1iclkout);
+ + 
+ + 	writel(cmd->cmd2csratio, &ddr_reg[0]->cm2csratio);
+ + 	writel(cmd->cmd2dldiff, &ddr_reg[0]->cm2dldiff);
+ + 	writel(cmd->cmd2iclkout, &ddr_reg[0]->cm2iclkout);
+ + }
+ + 
+ + /**
+ +  * Configure DDR DATA registers
+ +  */
+ + void config_ddr_data(int macrono, const struct ddr_data *data)
+ + {
+ + 	writel(data->datardsratio0, &ddr_reg[macrono]->dt0rdsratio0);
+ + 	writel(data->datawdsratio0, &ddr_reg[macrono]->dt0wdsratio0);
+ + 	writel(data->datawiratio0, &ddr_reg[macrono]->dt0wiratio0);
+ + 	writel(data->datagiratio0, &ddr_reg[macrono]->dt0giratio0);
+ + 	writel(data->datafwsratio0, &ddr_reg[macrono]->dt0fwsratio0);
+ + 	writel(data->datawrsratio0, &ddr_reg[macrono]->dt0wrsratio0);
+ + 	writel(data->datauserank0delay, &ddr_reg[macrono]->dt0rdelays0);
+ + 	writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0);
+ + }
+ + 
+ + void config_io_ctrl(unsigned long val)
+ + {
+ + 	writel(val, &ioctrl_reg->cm0ioctl);
+ + 	writel(val, &ioctrl_reg->cm1ioctl);
+ + 	writel(val, &ioctrl_reg->cm2ioctl);
+ + 	writel(val, &ioctrl_reg->dt0ioctl);
+ + 	writel(val, &ioctrl_reg->dt1ioctl);
+ + }
+ diff -crN u-boot-2012.10_o/arch/arm/cpu/armv7/ckb_3352/emif4.c u-boot-2012.10/arch/arm/cpu/armv7/ckb_3352/emif4.c
+ *** u-boot-2012.10_o/arch/arm/cpu/armv7/ckb_3352/emif4.c	1970-01-01 09:00:00.000000000 +0900
+ --- u-boot-2012.10/arch/arm/cpu/armv7/ckb_3352/emif4.c	2014-02-27 11:33:16.731635581 +0900
+ ***************
+ *** 0 ****
+ --- 1,44 ----
+ + /*
+ +  * emif4.c
+ +  *
+ +  * CKB-3352 emif4 configuration file
+ +  *
+ +  * Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation; either version 2 of
+ +  * the License, or (at your option) any later version.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #include <common.h>
+ + #include <asm/arch/cpu.h>
+ + #include <asm/arch/ddr_defs.h>
+ + #include <asm/arch/hardware.h>
+ + #include <asm/arch/clock.h>
+ + #include <asm/arch/sys_proto.h>
+ + #include <asm/io.h>
+ + #include <asm/emif.h>
+ + 
+ + DECLARE_GLOBAL_DATA_PTR;
+ + 
+ + int dram_init(void)
+ + {
+ + 	/* dram_init must store complete ramsize in gd->ram_size */
+ + 	gd->ram_size = get_ram_size(
+ + 			(void *)CONFIG_SYS_SDRAM_BASE,
+ + 			CONFIG_MAX_RAM_BANK_SIZE);
+ + 	return 0;
+ + }
+ + 
+ + void dram_init_banksize(void)
+ + {
+ + 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ + 	gd->bd->bi_dram[0].size = gd->ram_size;
+ + }
+ + 
+ diff -crN u-boot-2012.10_o/arch/arm/cpu/armv7/ckb_3352/Makefile u-boot-2012.10/arch/arm/cpu/armv7/ckb_3352/Makefile
+ *** u-boot-2012.10_o/arch/arm/cpu/armv7/ckb_3352/Makefile	1970-01-01 09:00:00.000000000 +0900
+ --- u-boot-2012.10/arch/arm/cpu/armv7/ckb_3352/Makefile	2014-03-07 11:21:15.608250000 +0900
+ ***************
+ *** 0 ****
+ --- 1,47 ----
+ + #
+ + # Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
+ + #
+ + # This program is free software; you can redistribute it and/or
+ + # modify it under the terms of the GNU General Public License as
+ + # published by the Free Software Foundation; either version 2 of
+ + # the License, or (at your option) any later version.
+ + #
+ + # This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ + # kind, whether express or implied; without even the implied warranty
+ + # of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ + # GNU General Public License for more details.
+ + #
+ + 
+ + include $(TOPDIR)/config.mk
+ + 
+ + LIB	= $(obj)lib$(SOC).o
+ + 
+ + COBJS	+= clock.o
+ + COBJS	+= sys_info.o
+ + COBJS	+= ddr.o
+ + COBJS	+= emif4.o
+ + COBJS	+= ckb_3352.o
+ + 
+ + 
+ + SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+ + OBJS	:= $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
+ + 
+ + all:	$(obj).depend $(LIB)
+ + 
+ + $(LIB):	$(OBJS)
+ + 	$(call cmd_link_o_target, $(OBJS))
+ + 
+ + clean:
+ + 	rm -f $(SOBJS) $(OBJS)
+ + 
+ + distclean:	clean
+ + 	rm -f $(LIB) core *.bak .depend
+ + 
+ + #########################################################################
+ + 
+ + # defines $(obj).depend target
+ + include $(SRCTREE)/rules.mk
+ + 
+ + sinclude $(obj).depend
+ + 
+ + #########################################################################
+ diff -crN u-boot-2012.10_o/arch/arm/cpu/armv7/ckb_3352/sys_info.c u-boot-2012.10/arch/arm/cpu/armv7/ckb_3352/sys_info.c
+ *** u-boot-2012.10_o/arch/arm/cpu/armv7/ckb_3352/sys_info.c	1970-01-01 09:00:00.000000000 +0900
+ --- u-boot-2012.10/arch/arm/cpu/armv7/ckb_3352/sys_info.c	2014-02-27 11:33:16.753647295 +0900
+ ***************
+ *** 0 ****
+ --- 1,130 ----
+ + /*
+ +  * sys_info.c
+ +  *
+ +  * System information functions
+ +  *
+ +  * Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
+ +  *
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation; either version 2 of
+ +  * the License, or (at your option) any later version.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #include <common.h>
+ + #include <asm/io.h>
+ + #include <asm/arch/sys_proto.h>
+ + #include <asm/arch/cpu.h>
+ + #include <asm/arch/clock.h>
+ + 
+ + struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
+ + 
+ + /**
+ +  * get_cpu_rev(void) - extract rev info
+ +  */
+ + u32 get_cpu_rev(void)
+ + {
+ + 	u32 id;
+ + 	u32 rev;
+ + 
+ + 	id = readl(DEVICE_ID);
+ + 	rev = (id >> 28) & 0xff;
+ + 
+ + 	return rev;
+ + }
+ + 
+ + /**
+ +  * get_cpu_type(void) - extract cpu info
+ +  */
+ + u32 get_cpu_type(void)
+ + {
+ + 	u32 id = 0;
+ + 	u32 partnum;
+ + 
+ + 	id = readl(DEVICE_ID);
+ + 	partnum = (id >> 12) & 0xffff;
+ + 
+ + 	return partnum;
+ + }
+ + 
+ + /**
+ +  * get_board_rev() - setup to pass kernel board revision information
+ +  * returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
+ +  */
+ + u32 get_board_rev(void)
+ + {
+ + 	return BOARD_REV_ID;
+ + }
+ + 
+ + /**
+ +  * get_device_type(): tell if GP/HS/EMU/TST
+ +  */
+ + u32 get_device_type(void)
+ + {
+ + 	int mode;
+ + 	mode = readl(&cstat->statusreg) & (DEVICE_MASK);
+ + 	return mode >>= 8;
+ + }
+ + 
+ + /**
+ +  * get_sysboot_value(void) - return SYS_BOOT[4:0]
+ +  */
+ + u32 get_sysboot_value(void)
+ + {
+ + 	int mode;
+ + 	mode = readl(&cstat->statusreg) & (SYSBOOT_MASK);
+ + 	return mode;
+ + }
+ + 
+ + #ifdef CONFIG_DISPLAY_CPUINFO
+ + /**
+ +  * Print CPU information
+ +  */
+ + int print_cpuinfo(void)
+ + {
+ + 	char *cpu_s, *sec_s;
+ + 	int arm_freq, ddr_freq;
+ + 
+ + 	switch (get_cpu_type()) {
+ + 	case AM335X:
+ + 		cpu_s = "AM335X";
+ + 		break;
+ + 	default:
+ + 		cpu_s = "Unknown cpu type";
+ + 		break;
+ + 	}
+ + 
+ + 	switch (get_device_type()) {
+ + 	case TST_DEVICE:
+ + 		sec_s = "TST";
+ + 		break;
+ + 	case EMU_DEVICE:
+ + 		sec_s = "EMU";
+ + 		break;
+ + 	case HS_DEVICE:
+ + 		sec_s = "HS";
+ + 		break;
+ + 	case GP_DEVICE:
+ + 		sec_s = "GP";
+ + 		break;
+ + 	default:
+ + 		sec_s = "?";
+ + 	}
+ + 
+ + 	printf("AM%s-%s rev %d\n",
+ + 			cpu_s, sec_s, get_cpu_rev());
+ + 
+ + 	/* TODO: Print ARM and DDR frequencies  */
+ + 
+ + 	return 0;
+ + }
+ + 
+ + 
+ + #endif	/* CONFIG_DISPLAY_CPUINFO */
+ + 
+ diff -crN u-boot-2012.10_o/arch/arm/cpu/armv7/start.S u-boot-2012.10/arch/arm/cpu/armv7/start.S
+ *** u-boot-2012.10_o/arch/arm/cpu/armv7/start.S	2012-10-16 00:14:08.000000000 +0900
+ --- u-boot-2012.10/arch/arm/cpu/armv7/start.S	2014-02-27 11:33:16.763632368 +0900
+ ***************
+ *** 102,107 ****
+ --- 102,118 ----
+   _end_ofs:
+   	.word _end - _start
+   
+ + #ifdef CONFIG_MACH_CKB_3352
+ + .globl _loader_executed_uboot
+ + _loader_executed_uboot:
+ +  	.word 0		/* initialize to 0, if Uboot was loaded and executed by "loader",
+ + 	 			    this will be set to 1 by "loader" */
+ + .globl _approx_uboot_len
+ + _approx_uboot_len:
+ + 	.word 0		/* filled later */
+ + #endif
+ + 
+ + 
+   #ifdef CONFIG_USE_IRQ
+   /* IRQ stack memory (calculated at run-time) */
+   .globl IRQ_STACK_START
+ ***************
+ *** 159,164 ****
+ --- 170,197 ----
+   call_board_init_f:
+   	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
+   	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
+ + #ifdef CONFIG_MACH_CKB_3352
+ + 	ldr	r0, _loader_executed_uboot
+ + 	cmp r0, #0
+ + 	bne _execute_uboot					/* loader executed u-Boot */
+ + 	/* copy Uboot code to temp memory in RAM */
+ + 	adr	r0, _start						/* r0 <- Current Start address */
+ + 	mov r1, #(UBOOT_TEMP_ADDR & 0xFF000000)	/* r1 <- temp address */
+ + 	add r1, r1, #(UBOOT_TEMP_ADDR & 0x00FF0000)
+ + 	add r1, r1, #(UBOOT_TEMP_ADDR & 0x0000FF00)
+ + 	add r1, r1, #(UBOOT_TEMP_ADDR & 0x000000FF)
+ + 	ldr	r2, _end_ofs					/* exact length of U-Boot */
+ + 	adr r3, _approx_uboot_len
+ +  	str r2, [r3]
+ + 	add r2, r2, r0						/* r2 <- end address */
+ + _copy_uboot_code:
+ + 	ldmia r0!, {r3-r12}
+ + 	stmia r1!, {r3-r12}
+ + 	cmp r0, r2
+ + 	ble _copy_uboot_code
+ + _execute_uboot:
+ + #endif
+ + 
+   	ldr	r0,=0x00000000
+   	bl	board_init_f
+   
+ ***************
+ *** 184,190 ****
+ --- 217,227 ----
+   	adr	r0, _start
+   	cmp	r0, r6
+   	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
+ + #ifdef CONFIG_NO_RELOCATE_UBOOT
+ + 	beq	copy_dyn		/* skip code relocation, branch to dynamic section copy */
+ + #else
+   	beq	clear_bss		/* skip relocation */
+ + #endif
+   	mov	r1, r6			/* r1 <- scratch for copy_loop */
+   	ldr	r3, _image_copy_end_ofs
+   	add	r2, r0, r3		/* r2 <- source end address	    */
+ ***************
+ *** 195,200 ****
+ --- 232,238 ----
+   	cmp	r0, r2			/* until source end address [r2]    */
+   	blo	copy_loop
+   
+ + copy_dyn:
+   	/*
+   	 * fix .rel.dyn relocations
+   	 */
+ diff -crN u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/clock.h u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/clock.h
+ *** u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/clock.h	1970-01-01 09:00:00.000000000 +0900
+ --- u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/clock.h	2014-02-27 11:33:16.763632368 +0900
+ ***************
+ *** 0 ****
+ --- 1,24 ----
+ + /*
+ +  * clock.h
+ +  *
+ +  * clock header
+ +  *
+ +  * Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation; either version 2 of
+ +  * the License, or (at your option) any later version.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #ifndef _CLOCKS_H_
+ + #define _CLOCKS_H_
+ + 
+ + #include <asm/arch/clocks_am33xx.h>
+ + 
+ + #endif
+ diff -crN u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/clocks_am33xx.h u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/clocks_am33xx.h
+ *** u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/clocks_am33xx.h	1970-01-01 09:00:00.000000000 +0900
+ --- u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/clocks_am33xx.h	2014-02-27 11:33:16.763632368 +0900
+ ***************
+ *** 0 ****
+ --- 1,62 ----
+ + /*
+ +  * clocks_am33xx.h
+ +  *
+ +  * AM33xx clock define
+ +  *
+ +  * Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation; either version 2 of
+ +  * the License, or (at your option) any later version.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #ifndef _CLOCKS_AM33XX_H_
+ + #define _CLOCKS_AM33XX_H_
+ + 
+ + #define OSC	(V_OSCK/1000000)
+ + 
+ + /* MAIN PLL Fdll = 550MHz, 720MHz or 800MHz */
+ + #define MPUPLL_M_800	800
+ + #define MPUPLL_M_720	720
+ + #define MPUPLL_M_550	550
+ + #define MPUPLL_N	(OSC-1)
+ + #define MPUPLL_M2	1
+ + 
+ + /* Core PLL Fdll = 1 GHZ, */
+ + #define COREPLL_M	1000
+ + #define COREPLL_N	(OSC-1)
+ + 
+ + #define COREPLL_M4	10	/* CORE_CLKOUTM4 = 200 MHZ */
+ + #define COREPLL_M5	8	/* CORE_CLKOUTM5 = 250 MHZ */
+ + #define COREPLL_M6	4	/* CORE_CLKOUTM6 = 500 MHZ */
+ + 
+ + /*
+ +  * USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll
+ +  * frequency needs to be set to 960 MHZ. Hence,
+ +  * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
+ +  */
+ + #define PERPLL_M	960
+ + #define PERPLL_N	(OSC-1)
+ + #define PERPLL_M2	5
+ + 
+ + /* DDR Freq is 266 MHZ for now */
+ + /* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
+ + #define DDRPLL_M	266
+ + #define DDRPLL_N	(OSC-1)
+ + #define DDRPLL_M2	1
+ + 
+ + /* DISP Freq is 300 MHZ for now */
+ + #define DISPPLL_M	300
+ + #define DISPPLL_N	(OSC-1)
+ + #define DISPPLL_M2	1
+ + 
+ + extern void pll_init(void);
+ + extern void enable_emif_clocks(void);
+ + 
+ + #endif	/* endif _CLOCKS_AM33XX_H_ */
+ diff -crN u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/cpu.h u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/cpu.h
+ *** u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/cpu.h	1970-01-01 09:00:00.000000000 +0900
+ --- u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/cpu.h	2014-02-27 11:33:16.767558729 +0900
+ ***************
+ *** 0 ****
+ --- 1,352 ----
+ + /*
+ +  * cpu.h
+ +  *
+ +  * CKB-3352 specific header file
+ +  *
+ +  * Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation; either version 2 of
+ +  * the License, or (at your option) any later version.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #ifndef _AM33XX_CPU_H
+ + #define _AM33XX_CPU_H
+ + 
+ + #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+ + #include <asm/types.h>
+ + #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+ + 
+ + #include <asm/arch/hardware.h>
+ + 
+ + #define BIT(x)				(1 << x)
+ + #define CL_BIT(x)			(0 << x)
+ + 
+ + /* Timer register bits */
+ + #define TCLR_ST				BIT(0)	/* Start=1 Stop=0 */
+ + #define TCLR_AR				BIT(1)	/* Auto reload */
+ + #define TCLR_PRE			BIT(5)	/* Pre-scaler enable */
+ + #define TCLR_PTV_SHIFT			(2)	/* Pre-scaler shift value */
+ + #define TCLR_PRE_DISABLE		CL_BIT(5) /* Pre-scalar disable */
+ + 
+ + /* device type */
+ + #define DEVICE_MASK			(BIT(8) | BIT(9) | BIT(10))
+ + #define TST_DEVICE			0x0
+ + #define EMU_DEVICE			0x1
+ + #define HS_DEVICE			0x2
+ + #define GP_DEVICE			0x3
+ + 
+ + /* cpu-id for AM33XX family */
+ + #define AM335X				0xB944
+ + #define DEVICE_ID			0x44E10600
+ + 
+ + /* This gives the status of the boot mode pins on the evm */
+ + #define SYSBOOT_MASK			(BIT(0) | BIT(1) | BIT(2)\
+ + 					| BIT(3) | BIT(4))
+ + 
+ + /* Reset control */
+ + #ifdef CONFIG_AM33XX
+ + #define PRM_RSTCTRL			0x44E00F00
+ + #define PRM_RSTST			0x44E00F08
+ + #endif
+ + #define PRM_RSTCTRL_RESET		0x01
+ + #define PRM_RSTST_WARM_RESET_MASK	0x232
+ + 
+ + #ifndef __KERNEL_STRICT_NAMES
+ + #ifndef __ASSEMBLY__
+ + struct gpmc_cs {
+ + 	u32 config1;		/* 0x00 */
+ + 	u32 config2;		/* 0x04 */
+ + 	u32 config3;		/* 0x08 */
+ + 	u32 config4;		/* 0x0C */
+ + 	u32 config5;		/* 0x10 */
+ + 	u32 config6;		/* 0x14 */
+ + 	u32 config7;		/* 0x18 */
+ + 	u32 nand_cmd;		/* 0x1C */
+ + 	u32 nand_adr;		/* 0x20 */
+ + 	u32 nand_dat;		/* 0x24 */
+ + 	u8 res[8];		/* blow up to 0x30 byte */
+ + };
+ + 
+ + struct bch_res_0_3 {
+ + 	u32 bch_result_x[4];
+ + };
+ + 
+ + struct gpmc {
+ + 	u8 res1[0x10];
+ + 	u32 sysconfig;		/* 0x10 */
+ + 	u8 res2[0x4];
+ + 	u32 irqstatus;		/* 0x18 */
+ + 	u32 irqenable;		/* 0x1C */
+ + 	u8 res3[0x20];
+ + 	u32 timeout_control;	/* 0x40 */
+ + 	u8 res4[0xC];
+ + 	u32 config;		/* 0x50 */
+ + 	u32 status;		/* 0x54 */
+ + 	u8 res5[0x8];		/* 0x58 */
+ + 	struct gpmc_cs cs[8];	/* 0x60, 0x90, .. */
+ + 	u8 res6[0x14];		/* 0x1E0 */
+ + 	u32 ecc_config;		/* 0x1F4 */
+ + 	u32 ecc_control;	/* 0x1F8 */
+ + 	u32 ecc_size_config;	/* 0x1FC */
+ + 	u32 ecc1_result;	/* 0x200 */
+ + 	u32 ecc2_result;	/* 0x204 */
+ + 	u32 ecc3_result;	/* 0x208 */
+ + 	u32 ecc4_result;	/* 0x20C */
+ + 	u32 ecc5_result;	/* 0x210 */
+ + 	u32 ecc6_result;	/* 0x214 */
+ + 	u32 ecc7_result;	/* 0x218 */
+ + 	u32 ecc8_result;	/* 0x21C */
+ + 	u32 ecc9_result;	/* 0x220 */
+ + 	u8 res7[12];		/* 0x224 */
+ + 	u32 testmomde_ctrl;	/* 0x230 */
+ + 	u8 res8[12];		/* 0x234 */
+ + 	struct bch_res_0_3 bch_result_0_3[2];	/* 0x240 */
+ + };
+ + 
+ + /* Used for board specific gpmc initialization */
+ + extern struct gpmc *gpmc_cfg;
+ + 
+ + /* Encapsulating core pll registers */
+ + struct cm_wkuppll {
+ + 	unsigned int wkclkstctrl;	/* offset 0x00 */
+ + 	unsigned int wkctrlclkctrl;	/* offset 0x04 */
+ + 	unsigned int wkgpio0clkctrl;	/* offset 0x08 */
+ + 	unsigned int wkl4wkclkctrl;	/* offset 0x0c */
+ + 	unsigned int resv2[4];
+ + 	unsigned int idlestdpllmpu;	/* offset 0x20 */
+ + 	unsigned int resv3[2];
+ + 	unsigned int clkseldpllmpu;	/* offset 0x2c */
+ + 	unsigned int resv4[1];
+ + 	unsigned int idlestdpllddr;	/* offset 0x34 */
+ + 	unsigned int resv5[2];
+ + 	unsigned int clkseldpllddr;	/* offset 0x40 */
+ + 	unsigned int autoidledplldisp;	/* offset 0x44 */
+ + 	unsigned int idlestdplldisp;	/* offset 0x48 */
+ + 	unsigned int resv6[2];
+ + 	unsigned int clkseldplldisp;	/* offset 0x54 */
+ + 	unsigned int resv7[1];
+ + 	unsigned int idlestdpllcore;	/* offset 0x5c */
+ + 	unsigned int resv8[2];
+ + 	unsigned int clkseldpllcore;	/* offset 0x68 */
+ + 	unsigned int resv9[1];
+ + 	unsigned int idlestdpllper;	/* offset 0x70 */
+ + 	unsigned int resv10[2];
+ + 	unsigned int clkdcoldodpllper;	/* offset 0x7c */
+ + 	unsigned int divm4dpllcore;	/* offset 0x80 */
+ + 	unsigned int divm5dpllcore;	/* offset 0x84 */
+ + 	unsigned int clkmoddpllmpu;	/* offset 0x88 */
+ + 	unsigned int clkmoddpllper;	/* offset 0x8c */
+ + 	unsigned int clkmoddpllcore;	/* offset 0x90 */
+ + 	unsigned int clkmoddpllddr;	/* offset 0x94 */
+ + 	unsigned int clkmoddplldisp;	/* offset 0x98 */
+ + 	unsigned int clkseldpllper;	/* offset 0x9c */
+ + 	unsigned int divm2dpllddr;	/* offset 0xA0 */
+ + 	unsigned int divm2dplldisp;	/* offset 0xA4 */
+ + 	unsigned int divm2dpllmpu;	/* offset 0xA8 */
+ + 	unsigned int divm2dpllper;	/* offset 0xAC */
+ + 	unsigned int resv11[1];
+ + 	unsigned int wkup_uart0ctrl;	/* offset 0xB4 */
+ + 	unsigned int wkup_i2c0ctrl;	/* offset 0xB8 */
+ + 	unsigned int resv12[7];
+ + 	unsigned int divm6dpllcore;	/* offset 0xD8 */
+ + };
+ + 
+ + /**
+ +  * Encapsulating peripheral functional clocks
+ +  * pll registers
+ +  */
+ + struct cm_perpll {
+ + 	unsigned int l4lsclkstctrl;	/* offset 0x00 */
+ + 	unsigned int l3sclkstctrl;	/* offset 0x04 */
+ + 	unsigned int l4fwclkstctrl;	/* offset 0x08 */
+ + 	unsigned int l3clkstctrl;	/* offset 0x0c */
+ + 	unsigned int resv1;
+ + 	unsigned int cpgmac0clkctrl;	/* offset 0x14 */
+ + 	unsigned int lcdclkctrl;	/* offset 0x18 */
+ + 	unsigned int usb0clkctrl;	/* offset 0x1C */
+ + 	unsigned int resv2;
+ + 	unsigned int tptc0clkctrl;	/* offset 0x24 */
+ + 	unsigned int emifclkctrl;	/* offset 0x28 */
+ + 	unsigned int ocmcramclkctrl;	/* offset 0x2c */
+ + 	unsigned int gpmcclkctrl;	/* offset 0x30 */
+ + 	unsigned int mcasp0clkctrl;	/* offset 0x34 */
+ + 	unsigned int uart5clkctrl;	/* offset 0x38 */
+ + 	unsigned int mmc0clkctrl;	/* offset 0x3C */
+ + 	unsigned int elmclkctrl;	/* offset 0x40 */
+ + 	unsigned int i2c2clkctrl;	/* offset 0x44 */
+ + 	unsigned int i2c1clkctrl;	/* offset 0x48 */
+ + 	unsigned int spi0clkctrl;	/* offset 0x4C */
+ + 	unsigned int spi1clkctrl;	/* offset 0x50 */
+ + 	unsigned int resv3[3];
+ + 	unsigned int l4lsclkctrl;	/* offset 0x60 */
+ + 	unsigned int l4fwclkctrl;	/* offset 0x64 */
+ + 	unsigned int mcasp1clkctrl;	/* offset 0x68 */
+ + 	unsigned int uart1clkctrl;	/* offset 0x6C */
+ + 	unsigned int uart2clkctrl;	/* offset 0x70 */
+ + 	unsigned int uart3clkctrl;	/* offset 0x74 */
+ + 	unsigned int uart4clkctrl;	/* offset 0x78 */
+ + 	unsigned int timer7clkctrl;	/* offset 0x7C */
+ + 	unsigned int timer2clkctrl;	/* offset 0x80 */
+ + 	unsigned int timer3clkctrl;	/* offset 0x84 */
+ + 	unsigned int timer4clkctrl;	/* offset 0x88 */
+ + 	unsigned int resv4[8];
+ + 	unsigned int gpio1clkctrl;	/* offset 0xAC */
+ + 	unsigned int gpio2clkctrl;	/* offset 0xB0 */
+ + 	unsigned int gpio3clkctrl;	/* offset 0xB4 */
+ + 	unsigned int resv5;
+ + 	unsigned int tpccclkctrl;	/* offset 0xBC */
+ + 	unsigned int dcan0clkctrl;	/* offset 0xC0 */
+ + 	unsigned int dcan1clkctrl;	/* offset 0xC4 */
+ + 	unsigned int resv6[2];
+ + 	unsigned int emiffwclkctrl;	/* offset 0xD0 */
+ + 	unsigned int resv7[2];
+ + 	unsigned int l3instrclkctrl;	/* offset 0xDC */
+ + 	unsigned int l3clkctrl;		/* Offset 0xE0 */
+ + 	unsigned int resv8[4];
+ + 	unsigned int mmc1clkctrl;	/* offset 0xF4 */
+ + 	unsigned int mmc2clkctrl;	/* offset 0xF8 */
+ + 	unsigned int resv9[8];
+ + 	unsigned int l4hsclkstctrl;	/* offset 0x11C */
+ + 	unsigned int l4hsclkctrl;	/* offset 0x120 */
+ + 	unsigned int resv10[8];
+ + 	unsigned int cpswclkstctrl;	/* offset 0x144 */
+ + 	unsigned int lcdclkstctrl;	/* offset 0x148 */
+ + };
+ + 
+ + /* Encapsulating Display pll registers */
+ + struct cm_dpll {
+ + 	unsigned int resv1[2];
+ + 	unsigned int clktimer2clk;	/* offset 0x08 */
+ + 	unsigned int resv2[9];	
+ + 	unsigned int clklcdcpixelclk;	/* offset 0x34 */
+ + };
+ + 
+ + /* Control Module RTC registers */
+ + struct cm_rtc {
+ + 	unsigned int rtcclkctrl;	/* offset 0x0 */
+ + 	unsigned int clkstctrl;		/* offset 0x4 */
+ + };
+ + 
+ + /* Watchdog timer registers */
+ + struct wd_timer {
+ + 	unsigned int resv1[4];
+ + 	unsigned int wdtwdsc;	/* offset 0x010 */
+ + 	unsigned int wdtwdst;	/* offset 0x014 */
+ + 	unsigned int wdtwisr;	/* offset 0x018 */
+ + 	unsigned int wdtwier;	/* offset 0x01C */
+ + 	unsigned int wdtwwer;	/* offset 0x020 */
+ + 	unsigned int wdtwclr;	/* offset 0x024 */
+ + 	unsigned int wdtwcrr;	/* offset 0x028 */
+ + 	unsigned int wdtwldr;	/* offset 0x02C */
+ + 	unsigned int wdtwtgr;	/* offset 0x030 */
+ + 	unsigned int wdtwwps;	/* offset 0x034 */
+ + 	unsigned int resv2[3];
+ + 	unsigned int wdtwdly;	/* offset 0x044 */
+ + 	unsigned int wdtwspr;	/* offset 0x048 */
+ + 	unsigned int resv3[1];
+ + 	unsigned int wdtwqeoi;	/* offset 0x050 */
+ + 	unsigned int wdtwqstar;	/* offset 0x054 */
+ + 	unsigned int wdtwqsta;	/* offset 0x058 */
+ + 	unsigned int wdtwqens;	/* offset 0x05C */
+ + 	unsigned int wdtwqenc;	/* offset 0x060 */
+ + 	unsigned int resv4[39];
+ + 	unsigned int wdt_unfr;	/* offset 0x100 */
+ + };
+ + 
+ + /* Timer 32 bit registers */
+ + struct gptimer {
+ + 	unsigned int tidr;		/* offset 0x00 */
+ + 	unsigned char res1[12];
+ + 	unsigned int tiocp_cfg;		/* offset 0x10 */
+ + 	unsigned char res2[12];
+ + 	unsigned int tier;		/* offset 0x20 */
+ + 	unsigned int tistatr;		/* offset 0x24 */
+ + 	unsigned int tistat;		/* offset 0x28 */
+ + 	unsigned int tisr;		/* offset 0x2c */
+ + 	unsigned int tcicr;		/* offset 0x30 */
+ + 	unsigned int twer;		/* offset 0x34 */
+ + 	unsigned int tclr;		/* offset 0x38 */
+ + 	unsigned int tcrr;		/* offset 0x3c */
+ + 	unsigned int tldr;		/* offset 0x40 */
+ + 	unsigned int ttgr;		/* offset 0x44 */
+ + 	unsigned int twpc;		/* offset 0x48 */
+ + 	unsigned int tmar;		/* offset 0x4c */
+ + 	unsigned int tcar1;		/* offset 0x50 */
+ + 	unsigned int tscir;		/* offset 0x54 */
+ + 	unsigned int tcar2;		/* offset 0x58 */
+ + };
+ + 
+ + /* RTC Registers */
+ + struct rtc_regs {
+ + 	unsigned int res[21];
+ + 	unsigned int osc;		/* offset 0x54 */
+ + 	unsigned int res2[5];
+ + 	unsigned int kick0r;		/* offset 0x6c */
+ + 	unsigned int kick1r;		/* offset 0x70 */
+ + };
+ + 
+ + /* UART Registers */
+ + struct uart_sys {
+ + 	unsigned int resv1[21];
+ + 	unsigned int uartsyscfg;	/* offset 0x54 */
+ + 	unsigned int uartsyssts;	/* offset 0x58 */
+ + };
+ + 
+ + /* VTP Registers */
+ + struct vtp_reg {
+ + 	unsigned int vtp0ctrlreg;
+ + };
+ + 
+ + /* Control Status Register */
+ + struct ctrl_stat {
+ + 	unsigned int resv1[16];
+ + 	unsigned int statusreg;		/* ofset 0x40 */
+ + 	unsigned int resv2[51];
+ + 	unsigned int secure_emif_sdram_config;	/* offset 0x0110 */
+ + };
+ + 
+ + /* AM33XX GPIO registers */
+ + #define OMAP_GPIO_REVISION		0x0000
+ + #define OMAP_GPIO_SYSCONFIG		0x0010
+ + #define OMAP_GPIO_SYSSTATUS		0x0114
+ + #define OMAP_GPIO_IRQSTATUS1		0x002c
+ + #define OMAP_GPIO_IRQSTATUS2		0x0030
+ + #define OMAP_GPIO_CTRL			0x0130
+ + #define OMAP_GPIO_OE			0x0134
+ + #define OMAP_GPIO_DATAIN		0x0138
+ + #define OMAP_GPIO_DATAOUT		0x013c
+ + #define OMAP_GPIO_LEVELDETECT0		0x0140
+ + #define OMAP_GPIO_LEVELDETECT1		0x0144
+ + #define OMAP_GPIO_RISINGDETECT		0x0148
+ + #define OMAP_GPIO_FALLINGDETECT		0x014c
+ + #define OMAP_GPIO_DEBOUNCE_EN		0x0150
+ + #define OMAP_GPIO_DEBOUNCE_VAL		0x0154
+ + #define OMAP_GPIO_CLEARDATAOUT		0x0190
+ + #define OMAP_GPIO_SETDATAOUT		0x0194
+ + 
+ + /* Control Device Register */
+ + struct ctrl_dev {
+ + 	unsigned int deviceid;		/* offset 0x00 */
+ + 	unsigned int resv1[7];
+ + 	unsigned int usb_ctrl0;		/* offset 0x20 */
+ + 	unsigned int resv2;
+ + 	unsigned int usb_ctrl1;		/* offset 0x28 */
+ + 	unsigned int resv3;
+ + 	unsigned int macid0l;		/* offset 0x30 */
+ + 	unsigned int macid0h;		/* offset 0x34 */
+ + 	unsigned int macid1l;		/* offset 0x38 */
+ + 	unsigned int macid1h;		/* offset 0x3c */
+ + 	unsigned int resv4[4];
+ + 	unsigned int miisel;		/* offset 0x50 */
+ + };
+ + #endif /* __ASSEMBLY__ */
+ + #endif /* __KERNEL_STRICT_NAMES */
+ + 
+ + #endif /* _AM33XX_CPU_H */
+ diff -crN u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/ddr_defs.h u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/ddr_defs.h
+ *** u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/ddr_defs.h	1970-01-01 09:00:00.000000000 +0900
+ --- u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/ddr_defs.h	2014-02-27 11:33:16.767558729 +0900
+ ***************
+ *** 0 ****
+ --- 1,202 ----
+ + /*
+ +  * ddr_defs.h
+ +  *
+ +  * ddr specific header
+ +  *
+ +  * Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation; either version 2 of
+ +  * the License, or (at your option) any later version.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #ifndef _DDR_DEFS_H
+ + #define _DDR_DEFS_H
+ + 
+ + #include <asm/arch/hardware.h>
+ + #include <asm/emif.h>
+ + 
+ + /* AM335X EMIF Register values */
+ + #define VTP_CTRL_READY		(0x1 << 5)
+ + #define VTP_CTRL_ENABLE		(0x1 << 6)
+ + #define VTP_CTRL_START_EN	(0x1)
+ + #define PHY_DLL_LOCK_DIFF	0x0
+ + #define DDR_CKE_CTRL_NORMAL	0x1
+ + 
+ + #define DDR2_EMIF_READ_LATENCY	0x100005	/* Enable Dynamic Power Down */
+ + #define DDR2_EMIF_TIM1		0x0666B3C9
+ + #define DDR2_EMIF_TIM2		0x243631CA
+ + #define DDR2_EMIF_TIM3		0x0000033F
+ + #define DDR2_EMIF_SDCFG		0x41805332
+ + #define DDR2_EMIF_SDREF		0x0000081a
+ + #define DDR2_DLL_LOCK_DIFF	0x0
+ + #define DDR2_RATIO		0x80
+ + #define DDR2_INVERT_CLKOUT	0x00
+ + #define DDR2_RD_DQS		0x12
+ + #define DDR2_WR_DQS		0x00
+ + #define DDR2_PHY_WRLVL		0x00
+ + #define DDR2_PHY_GATELVL	0x00
+ + #define DDR2_PHY_WR_DATA	0x40
+ + #define DDR2_PHY_FIFO_WE	0x80
+ + #define DDR2_PHY_RANK0_DELAY	0x1
+ + #define DDR2_IOCTRL_VALUE	0x18B
+ + 
+ + /* Micron MT41J128M16JT-125 */
+ + #define DDR3_EMIF_READ_LATENCY	0x100006	/* Enable Dynamic Power Down */
+ + #define DDR3_EMIF_TIM1		0x0888A39B
+ + #define DDR3_EMIF_TIM2		0x26337FDA
+ + #define DDR3_EMIF_TIM3		0x501F830F
+ + #define DDR3_EMIF_SDCFG		0x61C04AB2
+ + #define DDR3_EMIF_SDREF		0x0000093B
+ + #define DDR3_ZQ_CFG		0x50074BE4
+ + #define DDR3_DLL_LOCK_DIFF	0x1
+ + #define DDR3_RATIO		0x40
+ + #define DDR3_INVERT_CLKOUT	0x1
+ + #define DDR3_RD_DQS		0x3B
+ + #define DDR3_WR_DQS		0x85
+ + #define DDR3_PHY_WR_DATA	0xC1
+ + #define DDR3_PHY_FIFO_WE	0x100
+ + #define DDR3_IOCTRL_VALUE	0x18B
+ + 
+ + /* Micron ???? on 1.5 and later EVMs */
+ + #define DDR3_EMIF_TIM2_EVM	0x26517FDA
+ + #define DDR3_EMIF_TIM3_EVM	0x501F851F
+ + #define DDR3_RD_DQS_EVM		0x3A
+ + #define DDR3_WR_DQS_EVM		0x0CD
+ + #define DDR3_PHY_FIFO_WE_EVM	0x10B
+ + #define DDR3_PHY_WR_DATA_EVM	0x106
+ + 
+ + /**
+ +  * Configure SDRAM
+ +  */
+ + void config_sdram(const struct emif_regs *regs);
+ + 
+ + /**
+ +  * Set SDRAM timings
+ +  */
+ + void set_sdram_timings(const struct emif_regs *regs);
+ + 
+ + /**
+ +  * Configure DDR PHY
+ +  */
+ + void config_ddr_phy(const struct emif_regs *regs);
+ + 
+ + /**
+ +  * This structure represents the DDR registers on AM33XX devices.
+ +  * We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that
+ +  * correspond to DATA1 registers defined here.
+ +  */
+ + struct ddr_regs {
+ + 	unsigned int resv0[7];
+ + 	unsigned int cm0csratio;	/* offset 0x01C */
+ + 	unsigned int resv1[2];
+ + 	unsigned int cm0dldiff;		/* offset 0x028 */
+ + 	unsigned int cm0iclkout;	/* offset 0x02C */
+ + 	unsigned int resv2[8];
+ + 	unsigned int cm1csratio;	/* offset 0x050 */
+ + 	unsigned int resv3[2];
+ + 	unsigned int cm1dldiff;		/* offset 0x05C */
+ + 	unsigned int cm1iclkout;	/* offset 0x060 */
+ + 	unsigned int resv4[8];
+ + 	unsigned int cm2csratio;	/* offset 0x084 */
+ + 	unsigned int resv5[2];
+ + 	unsigned int cm2dldiff;		/* offset 0x090 */
+ + 	unsigned int cm2iclkout;	/* offset 0x094 */
+ + 	unsigned int resv6[12];
+ + 	unsigned int dt0rdsratio0;	/* offset 0x0C8 */
+ + 	unsigned int resv7[4];
+ + 	unsigned int dt0wdsratio0;	/* offset 0x0DC */
+ + 	unsigned int resv8[4];
+ + 	unsigned int dt0wiratio0;	/* offset 0x0F0 */
+ + 	unsigned int resv9;
+ + 	unsigned int dt0wimode0;	/* offset 0x0F8 */
+ + 	unsigned int dt0giratio0;	/* offset 0x0FC */
+ + 	unsigned int resv10;
+ + 	unsigned int dt0gimode0;	/* offset 0x104 */
+ + 	unsigned int dt0fwsratio0;	/* offset 0x108 */
+ + 	unsigned int resv11[4];
+ + 	unsigned int dt0dqoffset;	/* offset 0x11C */
+ + 	unsigned int dt0wrsratio0;	/* offset 0x120 */
+ + 	unsigned int resv12[4];
+ + 	unsigned int dt0rdelays0;	/* offset 0x134 */
+ + 	unsigned int dt0dldiff0;	/* offset 0x138 */
+ + };
+ + 
+ + /**
+ +  * Encapsulates DDR CMD control registers.
+ +  */
+ + struct cmd_control {
+ + 	unsigned long cmd0csratio;
+ + 	unsigned long cmd0csforce;
+ + 	unsigned long cmd0csdelay;
+ + 	unsigned long cmd0dldiff;
+ + 	unsigned long cmd0iclkout;
+ + 	unsigned long cmd1csratio;
+ + 	unsigned long cmd1csforce;
+ + 	unsigned long cmd1csdelay;
+ + 	unsigned long cmd1dldiff;
+ + 	unsigned long cmd1iclkout;
+ + 	unsigned long cmd2csratio;
+ + 	unsigned long cmd2csforce;
+ + 	unsigned long cmd2csdelay;
+ + 	unsigned long cmd2dldiff;
+ + 	unsigned long cmd2iclkout;
+ + };
+ + 
+ + /**
+ +  * Encapsulates DDR DATA registers.
+ +  */
+ + struct ddr_data {
+ + 	unsigned long datardsratio0;
+ + 	unsigned long datawdsratio0;
+ + 	unsigned long datawiratio0;
+ + 	unsigned long datagiratio0;
+ + 	unsigned long datafwsratio0;
+ + 	unsigned long datawrsratio0;
+ + 	unsigned long datauserank0delay;
+ + 	unsigned long datadldiff0;
+ + };
+ + 
+ + /**
+ +  * Configure DDR CMD control registers
+ +  */
+ + void config_cmd_ctrl(const struct cmd_control *cmd);
+ + 
+ + /**
+ +  * Configure DDR DATA registers
+ +  */
+ + void config_ddr_data(int data_macrono, const struct ddr_data *data);
+ + 
+ + /**
+ +  * This structure represents the DDR io control on AM33XX devices.
+ +  */
+ + struct ddr_cmdtctrl {
+ + 	unsigned int resv1[1];
+ + 	unsigned int cm0ioctl;
+ + 	unsigned int cm1ioctl;
+ + 	unsigned int cm2ioctl;
+ + 	unsigned int resv2[12];
+ + 	unsigned int dt0ioctl;
+ + 	unsigned int dt1ioctl;
+ + };
+ + 
+ + /**
+ +  * Configure DDR io control registers
+ +  */
+ + void config_io_ctrl(unsigned long val);
+ + 
+ + struct ddr_ctrl {
+ + 	unsigned int ddrioctrl;
+ + 	unsigned int resv1[325];
+ + 	unsigned int ddrckectrl;
+ + };
+ + 
+ + void config_ddr(short ddr_type);
+ + 
+ + #endif  /* _DDR_DEFS_H */
+ diff -crN u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/elm.h u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/elm.h
+ *** u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/elm.h	1970-01-01 09:00:00.000000000 +0900
+ --- u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/elm.h	2014-02-27 11:33:16.767558729 +0900
+ ***************
+ *** 0 ****
+ --- 1,93 ----
+ + /*
+ +  * (C) Copyright 2010-2011 Texas Instruments, <www.ti.com>
+ +  * Mansoor Ahamed <mansoor.ahamed@ti.com>
+ +  *
+ +  * Derived from work done by Rohit Choraria <rohitkc@ti.com> for omap3
+ +  *
+ +  * See file CREDITS for list of people who contributed to this
+ +  * project.
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation; either version 2 of
+ +  * the License, or (at your option) any later version.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ +  * MA 02111-1307 USA
+ +  */
+ + #ifndef __ASM_ARCH_ELM_H
+ + #define __ASM_ARCH_ELM_H
+ + /*
+ +  * ELM Module Registers
+ +  */
+ + 
+ + /* ELM registers bit fields */
+ + #define ELM_SYSCONFIG_SOFTRESET_MASK			(0x2)
+ + #define ELM_SYSCONFIG_SOFTRESET			(0x2)
+ + #define ELM_SYSSTATUS_RESETDONE_MASK			(0x1)
+ + #define ELM_SYSSTATUS_RESETDONE			(0x1)
+ + #define ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_MASK		(0x3)
+ + #define ELM_LOCATION_CONFIG_ECC_SIZE_MASK		(0x7FF0000)
+ + #define ELM_LOCATION_CONFIG_ECC_SIZE_POS		(16)
+ + #define ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID		(0x00010000)
+ + #define ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK	(0x100)
+ + #define ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK		(0x1F)
+ + 
+ + #ifndef __ASSEMBLY__
+ + 
+ + enum bch_level {
+ + 	BCH_4_BIT = 0,
+ + 	BCH_8_BIT,
+ + 	BCH_16_BIT
+ + };
+ + 
+ + 
+ + /* BCH syndrome registers */
+ + struct syndrome {
+ + 	u32 syndrome_fragment_x[7];	/* 0x400, 0x404.... 0x418 */
+ + 	u8 res1[36];			/* 0x41c */
+ + };
+ + 
+ + /* BCH error status & location register */
+ + struct location {
+ + 	u32 location_status;		/* 0x800 */
+ + 	u8 res1[124];			/* 0x804 */
+ + 	u32 error_location_x[16];	/* 0x880.... */
+ + 	u8 res2[64];			/* 0x8c0 */
+ + };
+ + 
+ + /* BCH ELM register map - do not try to allocate memmory for this structure.
+ +  * We have used plenty of reserved variables to fill the slots in the ELM
+ +  * register memory map.
+ +  * Directly initialize the struct pointer to ELM base address.
+ +  */
+ + struct elm {
+ + 	u32 rev;				/* 0x000 */
+ + 	u8 res1[12];				/* 0x004 */
+ + 	u32 sysconfig;				/* 0x010 */
+ + 	u32 sysstatus;				/* 0x014 */
+ + 	u32 irqstatus;				/* 0x018 */
+ + 	u32 irqenable;				/* 0x01c */
+ + 	u32 location_config;			/* 0x020 */
+ + 	u8 res2[92];				/* 0x024 */
+ + 	u32 page_ctrl;				/* 0x080 */
+ + 	u8 res3[892];				/* 0x084 */
+ + 	struct  syndrome syndrome_fragments[8]; /* 0x400 */
+ + 	u8 res4[512];				/* 0x600 */
+ + 	struct location  error_location[8];	/* 0x800 */
+ + };
+ + 
+ + int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count,
+ + 		u32 *error_locations);
+ + int elm_config(enum bch_level level);
+ + void elm_reset(void);
+ + void elm_init(void);
+ + #endif /* __ASSEMBLY__ */
+ + #endif /* __ASM_ARCH_ELM_H */
+ diff -crN u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/gpio.h u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/gpio.h
+ *** u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/gpio.h	1970-01-01 09:00:00.000000000 +0900
+ --- u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/gpio.h	2014-02-27 11:33:16.767558729 +0900
+ ***************
+ *** 0 ****
+ --- 1,29 ----
+ + /*
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation; either version 2 of
+ +  * the License, or (at your option) any later version.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ +  * MA 02111-1307 USA
+ +  *
+ +  */
+ + #ifndef _GPIO_AM33xx_H
+ + #define _GPIO_AM33xx_H
+ + 
+ + #include <asm/omap_gpio.h>
+ + 
+ + #define AM33XX_GPIO0_BASE       0x44E07000
+ + #define AM33XX_GPIO1_BASE       0x4804C000
+ + #define AM33XX_GPIO2_BASE       0x481AC000
+ + #define AM33XX_GPIO3_BASE       0x481AE000
+ + 
+ + #endif /* _GPIO_AM33xx_H */
+ diff -crN u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/hardware.h u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/hardware.h
+ *** u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/hardware.h	1970-01-01 09:00:00.000000000 +0900
+ --- u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/hardware.h	2014-02-27 11:33:16.767558729 +0900
+ ***************
+ *** 0 ****
+ --- 1,97 ----
+ + /*
+ +  * hardware.h
+ +  *
+ +  * hardware specific header
+ +  *
+ +  * Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation; either version 2 of
+ +  * the License, or (at your option) any later version.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #ifndef __AM33XX_HARDWARE_H
+ + #define __AM33XX_HARDWARE_H
+ + 
+ + #include <asm/arch/omap.h>
+ + 
+ + /* Module base addresses */
+ + #define UART0_BASE			0x44E09000
+ + 
+ + /* DM Timer base addresses */
+ + #define DM_TIMER0_BASE			0x4802C000
+ + #define DM_TIMER1_BASE			0x4802E000
+ + #define DM_TIMER2_BASE			0x48040000
+ + #define DM_TIMER3_BASE			0x48042000
+ + #define DM_TIMER4_BASE			0x48044000
+ + #define DM_TIMER5_BASE			0x48046000
+ + #define DM_TIMER6_BASE			0x48048000
+ + #define DM_TIMER7_BASE			0x4804A000
+ + 
+ + /* GPIO Base address */
+ + #define GPIO0_BASE			0x48032000
+ + #define GPIO1_BASE			0x4804C000
+ + #define GPIO2_BASE			0x481AC000
+ + 
+ + /* BCH Error Location Module */
+ + #define ELM_BASE			0x48080000
+ + 
+ + /* Watchdog Timer */
+ + #define WDT_BASE			0x44E35000
+ + 
+ + /* Control Module Base Address */
+ + #define CTRL_BASE			0x44E10000
+ + #define CTRL_DEVICE_BASE		0x44E10600
+ + 
+ + /* PRCM Base Address */
+ + #define PRCM_BASE			0x44E00000
+ + 
+ + /* EMIF Base address */
+ + #define EMIF4_0_CFG_BASE		0x4C000000
+ + #define EMIF4_1_CFG_BASE		0x4D000000
+ + 
+ + /* PLL related registers */
+ + #define CM_PER				0x44E00000
+ + #define CM_WKUP				0x44E00400
+ + #define CM_DPLL				0x44E00500
+ + #define CM_DEVICE			0x44E00700
+ + #define CM_RTC				0x44E00800
+ + #define CM_CEFUSE			0x44E00A00
+ + #define PRM_DEVICE			0x44E00F00
+ + 
+ + /* VTP Base address */
+ + #define VTP0_CTRL_ADDR			0x44E10E0C
+ + 
+ + /* DDR Base address */
+ + #define DDR_CTRL_ADDR			0x44E10E04
+ + #define DDR_CONTROL_BASE_ADDR		0x44E11404
+ + #define DDR_PHY_BASE_ADDR		0x44E12000
+ + #define DDR_PHY_BASE_ADDR2		0x44E120A4
+ + 
+ + /* UART */
+ + #define DEFAULT_UART_BASE		UART0_BASE
+ + 
+ + #define DDRPHY_0_CONFIG_BASE		(CTRL_BASE + 0x1400)
+ + #define DDRPHY_CONFIG_BASE		DDRPHY_0_CONFIG_BASE
+ + 
+ + /* GPMC Base address */
+ + #define GPMC_BASE			0x50000000
+ + 
+ + /* CPSW Config space */
+ + #define AM335X_CPSW_BASE		0x4A100000
+ + #define AM335X_CPSW_MDIO_BASE		0x4A101000
+ + 
+ + /* OTG */
+ + #define AM335X_USB0_OTG_BASE		0x47401000
+ + #define AM335X_USB1_OTG_BASE		0x47401800
+ + 
+ + /* RTC base address */
+ + #define AM335X_RTC_BASE			0x44E3E000
+ + 
+ + #endif /* __AM33XX_HARDWARE_H */
+ diff -crN u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/i2c.h u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/i2c.h
+ *** u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/i2c.h	1970-01-01 09:00:00.000000000 +0900
+ --- u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/i2c.h	2014-02-27 11:33:16.767558729 +0900
+ ***************
+ *** 0 ****
+ --- 1,81 ----
+ + /*
+ +  * (C) Copyright 2012
+ +  * Texas Instruments, <www.ti.com>
+ +  *
+ +  * See file CREDITS for list of people who contributed to this
+ +  * project.
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation; either version 2 of
+ +  * the License, or (at your option) any later version.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ +  * MA 02111-1307 USA
+ +  */
+ + #ifndef _I2C_H_
+ + #define _I2C_H_
+ + 
+ + #define  I2C_BASE1		0x44E0B000
+ + #define  I2C_BASE2		0x4802A000
+ + #define  I2C_BASE3		0x4819C000
+ + #define	 I2C_BUS_MAX		3
+ + 
+ + #define I2C_DEFAULT_BASE		I2C_BASE1
+ + 
+ + struct i2c {
+ + 	unsigned short revnb_lo;        /* 0x00 */
+ + 	unsigned short res1;
+ + 	unsigned short revnb_hi;        /* 0x04 */
+ + 	unsigned short res2[5];
+ + 	unsigned short sysc;		/* 0x10 */
+ + 	unsigned short res3[9];
+ + 	unsigned short irqstatus_raw;   /* 0x24 */
+ + 	unsigned short res4;
+ + 	unsigned short stat;            /* 0x28 */
+ + 	unsigned short res5;
+ + 	unsigned short ie;              /* 0x2C */
+ + 	unsigned short res6;
+ + 	unsigned short irqenable_clr;   /* 0x30 */
+ + 	unsigned short res7;
+ + 	unsigned short iv;              /* 0x34 */
+ + 	unsigned short res8[45];
+ + 	unsigned short syss;            /* 0x90 */
+ + 	unsigned short res9;
+ + 	unsigned short buf;             /* 0x94 */
+ + 	unsigned short res10;
+ + 	unsigned short cnt;             /* 0x98 */
+ + 	unsigned short res11;
+ + 	unsigned short data;            /* 0x9C */
+ + 	unsigned short res13;
+ + 	unsigned short res14;           /* 0xA0 */
+ + 	unsigned short res15;
+ + 	unsigned short con;             /* 0xA4 */
+ + 	unsigned short res16;
+ + 	unsigned short oa;              /* 0xA8 */
+ + 	unsigned short res17;
+ + 	unsigned short sa;              /* 0xAC */
+ + 	unsigned short res18;
+ + 	unsigned short psc;             /* 0xB0 */
+ + 	unsigned short res19;
+ + 	unsigned short scll;            /* 0xB4 */
+ + 	unsigned short res20;
+ + 	unsigned short sclh;            /* 0xB8 */
+ + 	unsigned short res21;
+ + 	unsigned short systest;         /* 0xBC */
+ + 	unsigned short res22;
+ + 	unsigned short bufstat;         /* 0xC0 */
+ + 	unsigned short res23;
+ + };
+ + 
+ + #define I2C_IP_CLK			48000000
+ + #define I2C_INTERNAL_SAMPLING_CLK	12000000
+ + 
+ + #endif /* _I2C_H_ */
+ diff -crN u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/mem.h u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/mem.h
+ *** u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/mem.h	1970-01-01 09:00:00.000000000 +0900
+ --- u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/mem.h	2014-02-27 11:33:16.772186341 +0900
+ ***************
+ *** 0 ****
+ --- 1,92 ----
+ + /*
+ +  * (C) Copyright 2006-2008
+ +  * Texas Instruments, <www.ti.com>
+ +  *
+ +  * Author
+ +  *		Mansoor Ahamed <mansoor.ahamed@ti.com>
+ +  *
+ +  * Initial Code from:
+ +  *		Richard Woodruff <r-woodruff2@ti.com>
+ +  *
+ +  * See file CREDITS for list of people who contributed to this
+ +  * project.
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation; either version 2 of
+ +  * the License, or (at your option) any later version.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ +  * MA 02111-1307 USA
+ +  */
+ + 
+ + #ifndef _MEM_H_
+ + #define _MEM_H_
+ + 
+ + /*
+ +  * GPMC settings -
+ +  * Definitions is as per the following format
+ +  * #define <PART>_GPMC_CONFIG<x> <value>
+ +  * Where:
+ +  * PART is the part name e.g. STNOR - Intel Strata Flash
+ +  * x is GPMC config registers from 1 to 6 (there will be 6 macros)
+ +  * Value is corresponding value
+ +  *
+ +  * For every valid PRCM configuration there should be only one definition of
+ +  * the same. if values are independent of the board, this definition will be
+ +  * present in this file if values are dependent on the board, then this should
+ +  * go into corresponding mem-boardName.h file
+ +  *
+ +  * Currently valid part Names are (PART):
+ +  * M_NAND - Micron NAND
+ +  */
+ + #define GPMC_SIZE_256M		0x0
+ + #define GPMC_SIZE_128M		0x8
+ + #define GPMC_SIZE_64M		0xC
+ + #define GPMC_SIZE_32M		0xE
+ + #define GPMC_SIZE_16M		0xF
+ + 
+ + #define M_NAND_GPMC_CONFIG1	0x00000800
+ + #define M_NAND_GPMC_CONFIG2	0x001e1e00
+ + #define M_NAND_GPMC_CONFIG3	0x001e1e00
+ + #define M_NAND_GPMC_CONFIG4	0x16051807
+ + #define M_NAND_GPMC_CONFIG5	0x00151e1e
+ + #define M_NAND_GPMC_CONFIG6	0x16000f80
+ + #define M_NAND_GPMC_CONFIG7	0x00000008
+ + 
+ + /* ST NOR chip on NOR cape for Beaglebone */
+ + #define STNOR_GPMC_CONFIG1	0x00001200
+ + #define STNOR_GPMC_CONFIG2	0x00101000
+ + #define STNOR_GPMC_CONFIG3	0x00030301
+ + #define STNOR_GPMC_CONFIG4	0x10041004
+ + #define STNOR_GPMC_CONFIG5	0x000C1010
+ + #define STNOR_GPMC_CONFIG6	0x08070280
+ + #define STNOR_GPMC_CONFIG7	0x00000F48
+ + 
+ + /* max number of GPMC Chip Selects */
+ + #define GPMC_MAX_CS		8
+ + /* max number of GPMC regs */
+ + #define GPMC_MAX_REG		7
+ + 
+ + #define PISMO1_NOR		1
+ + #define PISMO1_NAND		2
+ + #define PISMO2_CS0		3
+ + #define PISMO2_CS1		4
+ + #define PISMO1_ONENAND		5
+ + #define DBG_MPDB		6
+ + #define PISMO2_NAND_CS0		7
+ + #define PISMO2_NAND_CS1		8
+ + 
+ + /* make it readable for the gpmc_init */
+ + #define PISMO1_NOR_BASE	FLASH_BASE
+ + #define PISMO1_NAND_BASE	CONFIG_SYS_NAND_BASE
+ + #define PISMO1_NAND_SIZE	GPMC_SIZE_256M
+ + 
+ + #endif /* endif _MEM_H_ */
+ diff -crN u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/mmc_host_def.h u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/mmc_host_def.h
+ *** u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/mmc_host_def.h	1970-01-01 09:00:00.000000000 +0900
+ --- u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/mmc_host_def.h	2014-02-27 11:33:16.772186341 +0900
+ ***************
+ *** 0 ****
+ --- 1,163 ----
+ + /*
+ +  * mmc_host_def.h
+ +  *
+ +  * Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #ifndef MMC_HOST_DEF_H
+ + #define MMC_HOST_DEF_H
+ + 
+ + /*
+ +  * OMAP HSMMC register definitions
+ +  */
+ + #define OMAP_HSMMC1_BASE		0x48060100
+ + #define OMAP_HSMMC2_BASE		0x481D8100
+ + 
+ + typedef struct hsmmc {
+ + 	unsigned char res1[0x10];
+ + 	unsigned int sysconfig;		/* 0x10 */
+ + 	unsigned int sysstatus;		/* 0x14 */
+ + 	unsigned char res2[0x14];
+ + 	unsigned int con;		/* 0x2C */
+ + 	unsigned char res3[0xD4];
+ + 	unsigned int blk;		/* 0x104 */
+ + 	unsigned int arg;		/* 0x108 */
+ + 	unsigned int cmd;		/* 0x10C */
+ + 	unsigned int rsp10;		/* 0x110 */
+ + 	unsigned int rsp32;		/* 0x114 */
+ + 	unsigned int rsp54;		/* 0x118 */
+ + 	unsigned int rsp76;		/* 0x11C */
+ + 	unsigned int data;		/* 0x120 */
+ + 	unsigned int pstate;		/* 0x124 */
+ + 	unsigned int hctl;		/* 0x128 */
+ + 	unsigned int sysctl;		/* 0x12C */
+ + 	unsigned int stat;		/* 0x130 */
+ + 	unsigned int ie;		/* 0x134 */
+ + 	unsigned char res4[0x8];
+ + 	unsigned int capa;		/* 0x140 */
+ + } hsmmc_t;
+ + 
+ + /*
+ +  * OMAP HS MMC Bit definitions
+ +  */
+ + #define MMC_SOFTRESET			(0x1 << 1)
+ + #define RESETDONE			(0x1 << 0)
+ + #define NOOPENDRAIN			(0x0 << 0)
+ + #define OPENDRAIN			(0x1 << 0)
+ + #define OD				(0x1 << 0)
+ + #define INIT_NOINIT			(0x0 << 1)
+ + #define INIT_INITSTREAM			(0x1 << 1)
+ + #define HR_NOHOSTRESP			(0x0 << 2)
+ + #define STR_BLOCK			(0x0 << 3)
+ + #define MODE_FUNC			(0x0 << 4)
+ + #define DW8_1_4BITMODE			(0x0 << 5)
+ + #define MIT_CTO				(0x0 << 6)
+ + #define CDP_ACTIVEHIGH			(0x0 << 7)
+ + #define WPP_ACTIVEHIGH			(0x0 << 8)
+ + #define RESERVED_MASK			(0x3 << 9)
+ + #define CTPL_MMC_SD			(0x0 << 11)
+ + #define BLEN_512BYTESLEN		(0x200 << 0)
+ + #define NBLK_STPCNT			(0x0 << 16)
+ + #define DE_DISABLE			(0x0 << 0)
+ + #define BCE_DISABLE			(0x0 << 1)
+ + #define BCE_ENABLE			(0x1 << 1)
+ + #define ACEN_DISABLE			(0x0 << 2)
+ + #define DDIR_OFFSET			(4)
+ + #define DDIR_MASK			(0x1 << 4)
+ + #define DDIR_WRITE			(0x0 << 4)
+ + #define DDIR_READ			(0x1 << 4)
+ + #define MSBS_SGLEBLK			(0x0 << 5)
+ + #define MSBS_MULTIBLK			(0x1 << 5)
+ + #define RSP_TYPE_OFFSET			(16)
+ + #define RSP_TYPE_MASK			(0x3 << 16)
+ + #define RSP_TYPE_NORSP			(0x0 << 16)
+ + #define RSP_TYPE_LGHT136		(0x1 << 16)
+ + #define RSP_TYPE_LGHT48			(0x2 << 16)
+ + #define RSP_TYPE_LGHT48B		(0x3 << 16)
+ + #define CCCE_NOCHECK			(0x0 << 19)
+ + #define CCCE_CHECK			(0x1 << 19)
+ + #define CICE_NOCHECK			(0x0 << 20)
+ + #define CICE_CHECK			(0x1 << 20)
+ + #define DP_OFFSET			(21)
+ + #define DP_MASK				(0x1 << 21)
+ + #define DP_NO_DATA			(0x0 << 21)
+ + #define DP_DATA				(0x1 << 21)
+ + #define CMD_TYPE_NORMAL			(0x0 << 22)
+ + #define INDEX_OFFSET			(24)
+ + #define INDEX_MASK			(0x3f << 24)
+ + #define INDEX(i)			(i << 24)
+ + #define DATI_MASK			(0x1 << 1)
+ + #define CMDI_MASK			(0x1 << 0)
+ + #define DTW_1_BITMODE			(0x0 << 1)
+ + #define DTW_4_BITMODE			(0x1 << 1)
+ + #define DTW_8_BITMODE                   (0x1 << 5) /* CON[DW8]*/
+ + #define SDBP_PWROFF			(0x0 << 8)
+ + #define SDBP_PWRON			(0x1 << 8)
+ + #define SDVS_1V8			(0x5 << 9)
+ + #define SDVS_3V0			(0x6 << 9)
+ + #define ICE_MASK			(0x1 << 0)
+ + #define ICE_STOP			(0x0 << 0)
+ + #define ICS_MASK			(0x1 << 1)
+ + #define ICS_NOTREADY			(0x0 << 1)
+ + #define ICE_OSCILLATE			(0x1 << 0)
+ + #define CEN_MASK			(0x1 << 2)
+ + #define CEN_DISABLE			(0x0 << 2)
+ + #define CEN_ENABLE			(0x1 << 2)
+ + #define CLKD_OFFSET			(6)
+ + #define CLKD_MASK			(0x3FF << 6)
+ + #define DTO_MASK			(0xF << 16)
+ + #define DTO_15THDTO			(0xE << 16)
+ + #define SOFTRESETALL			(0x1 << 24)
+ + #define CC_MASK				(0x1 << 0)
+ + #define TC_MASK				(0x1 << 1)
+ + #define BWR_MASK			(0x1 << 4)
+ + #define BRR_MASK			(0x1 << 5)
+ + #define ERRI_MASK			(0x1 << 15)
+ + #define IE_CC				(0x01 << 0)
+ + #define IE_TC				(0x01 << 1)
+ + #define IE_BWR				(0x01 << 4)
+ + #define IE_BRR				(0x01 << 5)
+ + #define IE_CTO				(0x01 << 16)
+ + #define IE_CCRC				(0x01 << 17)
+ + #define IE_CEB				(0x01 << 18)
+ + #define IE_CIE				(0x01 << 19)
+ + #define IE_DTO				(0x01 << 20)
+ + #define IE_DCRC				(0x01 << 21)
+ + #define IE_DEB				(0x01 << 22)
+ + #define IE_CERR				(0x01 << 28)
+ + #define IE_BADA				(0x01 << 29)
+ + 
+ + #define VS30_3V0SUP			(1 << 25)
+ + #define VS18_1V8SUP			(1 << 26)
+ + 
+ + /* Driver definitions */
+ + #define MMCSD_SECTOR_SIZE		512
+ + #define MMC_CARD			0
+ + #define SD_CARD				1
+ + #define BYTE_MODE			0
+ + #define SECTOR_MODE			1
+ + #define CLK_INITSEQ			0
+ + #define CLK_400KHZ			1
+ + #define CLK_MISC			2
+ + 
+ + #define RSP_TYPE_NONE	(RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
+ + #define MMC_CMD0	(INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
+ + 
+ + /* Clock Configurations and Macros */
+ + #define MMC_CLOCK_REFERENCE	96 /* MHz */
+ + 
+ + #define mmc_reg_out(addr, mask, val)\
+ + 	writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
+ + 
+ + int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max);
+ + 
+ + #endif /* MMC_HOST_DEF_H */
+ diff -crN u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/omap_gpmc.h u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/omap_gpmc.h
+ *** u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/omap_gpmc.h	1970-01-01 09:00:00.000000000 +0900
+ --- u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/omap_gpmc.h	2014-02-27 11:33:16.772186341 +0900
+ ***************
+ *** 0 ****
+ --- 1,120 ----
+ + /*
+ +  * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
+ +  * Rohit Choraria <rohitkc@ti.com>
+ +  *
+ +  * See file CREDITS for list of people who contributed to this
+ +  * project.
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation; either version 2 of
+ +  * the License, or (at your option) any later version.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ +  * MA 02111-1307 USA
+ +  */
+ + #ifndef __ASM_ARCH_OMAP_GPMC_H
+ + #define __ASM_ARCH_OMAP_GPMC_H
+ + 
+ + #define GPMC_BUF_EMPTY	0
+ + #define GPMC_BUF_FULL	1
+ + 
+ + #define ECCCLEAR	(0x1 << 8)
+ + #define ECCRESULTREG1	(0x1 << 0)
+ + #define ECCSIZE512BYTE	0xFF
+ + #define ECCSIZE1	(ECCSIZE512BYTE << 22)
+ + #define ECCSIZE0	(ECCSIZE512BYTE << 12)
+ + #define ECCSIZE0SEL	(0x000 << 0)
+ + 
+ + /* Generic ECC Layouts */
+ + /* Large Page x8 NAND device Layout */
+ + #ifdef GPMC_NAND_ECC_LP_x8_LAYOUT
+ + #define GPMC_NAND_HW_ECC_LAYOUT {\
+ + 	.eccbytes = 12,\
+ + 	.eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\
+ + 		9, 10, 11, 12},\
+ + 	.oobfree = {\
+ + 		{.offset = 13,\
+ + 		 .length = 51 } } \
+ + }
+ + #endif
+ + 
+ + /* Large Page x16 NAND device Layout */
+ + #ifdef GPMC_NAND_ECC_LP_x16_LAYOUT
+ + #define GPMC_NAND_HW_ECC_LAYOUT {\
+ + 	.eccbytes = 12,\
+ + 	.eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\
+ + 		10, 11, 12, 13},\
+ + 	.oobfree = {\
+ + 		{.offset = 14,\
+ + 		 .length = 50 } } \
+ + }
+ + #endif
+ + 
+ + /* Small Page x8 NAND device Layout */
+ + #ifdef GPMC_NAND_ECC_SP_x8_LAYOUT
+ + #define GPMC_NAND_HW_ECC_LAYOUT {\
+ + 	.eccbytes = 3,\
+ + 	.eccpos = {1, 2, 3},\
+ + 	.oobfree = {\
+ + 		{.offset = 4,\
+ + 		 .length = 12 } } \
+ + }
+ + #endif
+ + 
+ + /* Small Page x16 NAND device Layout */
+ + #ifdef GPMC_NAND_ECC_SP_x16_LAYOUT
+ + #define GPMC_NAND_HW_ECC_LAYOUT {\
+ + 	.eccbytes = 3,\
+ + 	.eccpos = {2, 3, 4},\
+ + 	.oobfree = {\
+ + 		{.offset = 5,\
+ + 		 .length = 11 } } \
+ + }
+ + #endif
+ + 
+ + #define GPMC_NAND_HW_BCH4_ECC_LAYOUT {\
+ + 	.eccbytes = 32,\
+ + 	.eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
+ + 				16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
+ + 				28, 29, 30, 31, 32, 33},\
+ + 	.oobfree = {\
+ + 		{.offset = 34,\
+ + 		 .length = 30 } } \
+ + }
+ + 
+ + #define GPMC_NAND_HW_BCH8_ECC_LAYOUT {\
+ + 	.eccbytes = 56,\
+ + 	.eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
+ + 				16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
+ + 				28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\
+ + 				40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,\
+ + 				52, 53, 54, 55, 56, 57},\
+ + 	.oobfree = {\
+ + 		{.offset = 58,\
+ + 		 .length = 6 } } \
+ + }
+ + 
+ + #define GPMC_NAND_HW_BCH16_ECC_LAYOUT {\
+ + 	.eccbytes = 104,\
+ + 	.eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
+ + 				16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
+ + 				28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\
+ + 				40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,\
+ + 				52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,\
+ + 				64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,\
+ + 				76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,\
+ + 				88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,\
+ + 				100, 101, 102, 103, 104, 105},\
+ + 	.oobfree = {\
+ + 		{.offset = 106,\
+ + 		 .length = 8 } } \
+ + }
+ + #endif /* __ASM_ARCH_OMAP_GPMC_H */
+ diff -crN u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/omap.h u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/omap.h
+ *** u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/omap.h	1970-01-01 09:00:00.000000000 +0900
+ --- u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/omap.h	2014-02-27 11:33:16.772186341 +0900
+ ***************
+ *** 0 ****
+ --- 1,58 ----
+ + /*
+ +  * omap.h
+ +  *
+ +  * Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation; either version 2 of
+ +  * the License, or (at your option) any later version.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #ifndef _OMAP_H_
+ + #define _OMAP_H_
+ + 
+ + /*
+ +  * Non-secure SRAM Addresses
+ +  * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
+ +  * at 0x40304000(EMU base) so that our code works for both EMU and GP
+ +  */
+ + #define NON_SECURE_SRAM_START	0x402F0400
+ + #define NON_SECURE_SRAM_END	0x402FFFFF
+ + 
+ + /* ROM code defines */
+ + /* Boot device */
+ + #define BOOT_DEVICE_MASK	0xFF
+ + #define BOOT_DEVICE_OFFSET	0x8
+ + #define DEV_DESC_PTR_OFFSET	0x4
+ + #define DEV_DATA_PTR_OFFSET	0x18
+ + #define BOOT_MODE_OFFSET	0x8
+ + #define RESET_REASON_OFFSET	0x9
+ + #define CH_FLAGS_OFFSET		0xA
+ + 
+ + #define CH_FLAGS_CHSETTINGS	(0x1 << 0)
+ + #define CH_FLAGS_CHRAM		(0x1 << 1)
+ + #define CH_FLAGS_CHFLASH	(0x1 << 2)
+ + #define CH_FLAGS_CHMMCSD	(0x1 << 3)
+ + 
+ + #ifndef __ASSEMBLY__
+ + struct omap_boot_parameters {
+ + 	char *boot_message;
+ + 	unsigned int mem_boot_descriptor;
+ + 	unsigned char omap_bootdevice;
+ + 	unsigned char reset_reason;
+ + 	unsigned char ch_flags;
+ + };
+ + #endif
+ + #endif
+ + 
+ + 
+ + 
+ + 
+ + 
+ + 
+ diff -crN u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/spl.h u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/spl.h
+ *** u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/spl.h	1970-01-01 09:00:00.000000000 +0900
+ --- u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/spl.h	2014-02-27 11:33:16.772186341 +0900
+ ***************
+ *** 0 ****
+ --- 1,35 ----
+ + /*
+ +  * (C) Copyright 2012
+ +  * Texas Instruments, <www.ti.com>
+ +  *
+ +  * See file CREDITS for list of people who contributed to this
+ +  * project.
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation; either version 2 of
+ +  * the License, or (at your option) any later version.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ +  * MA 02111-1307 USA
+ +  */
+ + #ifndef	_ASM_ARCH_SPL_H_
+ + #define	_ASM_SPL_H_
+ + 
+ + #define BOOT_DEVICE_XIP       	2
+ + #define BOOT_DEVICE_NAND	5
+ + #define BOOT_DEVICE_MMC1	8
+ + #define BOOT_DEVICE_MMC2	9	/* eMMC or daughter card */
+ + #define BOOT_DEVICE_SPI		11
+ + #define BOOT_DEVICE_UART	65
+ + #define BOOT_DEVICE_USB		68
+ + #define BOOT_DEVICE_CPGMAC	70
+ + #define BOOT_DEVICE_MMC2_2      0xFF
+ + #endif
+ diff -crN u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/sys_proto.h u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/sys_proto.h
+ *** u-boot-2012.10_o/arch/arm/include/asm/arch-ckb_3352/sys_proto.h	1970-01-01 09:00:00.000000000 +0900
+ --- u-boot-2012.10/arch/arm/include/asm/arch-ckb_3352/sys_proto.h	2014-02-27 11:33:16.775510866 +0900
+ ***************
+ *** 0 ****
+ --- 1,70 ----
+ + /*
+ +  * sys_proto.h
+ +  *
+ +  * System information header
+ +  *
+ +  * Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation; either version 2 of
+ +  * the License, or (at your option) any later version.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #ifndef _SYS_PROTO_H_
+ + #define _SYS_PROTO_H_
+ + 
+ + /*
+ +  * AM335x parts define a system EEPROM that defines certain sub-fields.
+ +  * We use these fields to in turn see what board we are on, and what
+ +  * that might require us to set or not set.
+ +  */
+ + #define HDR_NO_OF_MAC_ADDR	3
+ + #define HDR_ETH_ALEN		6
+ + #define HDR_NAME_LEN		8
+ + 
+ + struct am335x_baseboard_id {
+ + 	unsigned int  magic;
+ + 	char name[HDR_NAME_LEN];
+ + 	char version[4];
+ + 	char serial[12];
+ + 	char config[32];
+ + 	char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
+ + };
+ + 
+ + int board_is_evm_15_or_later(void);
+ + 
+ + #define BOARD_REV_ID	0x0
+ + 
+ + u32 get_cpu_rev(void);
+ + u32 get_sysboot_value(void);
+ + 
+ + #ifdef CONFIG_DISPLAY_CPUINFO
+ + int print_cpuinfo(void);
+ + #endif
+ + 
+ + extern struct ctrl_stat *cstat;
+ + u32 get_device_type(void);
+ + void setup_clocks_for_console(void);
+ + void ddr_pll_config(unsigned int ddrpll_M);
+ + void mpu_pll_config(int mpupll_M);
+ + void sdelay(unsigned long);
+ + void gpmc_init(void);
+ + void omap_nand_switch_ecc(int);
+ + void am33xx_spl_board_init(void);
+ + 
+ + /*
+ +  * We have three pin mux functions that must exist.  We must be able to enable
+ +  * uart0, for initial output and i2c0 to read the main EEPROM.  We then have a
+ +  * main pinmux function that can be overridden to enable all other pinmux that
+ +  * is required on the board.
+ +  */
+ + void enable_uart0_pin_mux(void);
+ + void enable_i2c0_pin_mux(void);
+ + void enable_board_pin_mux();
+ + #endif
+ diff -crN u-boot-2012.10_o/arch/arm/include/asm/setup.h u-boot-2012.10/arch/arm/include/asm/setup.h
+ *** u-boot-2012.10_o/arch/arm/include/asm/setup.h	2012-10-16 00:14:08.000000000 +0900
+ --- u-boot-2012.10/arch/arm/include/asm/setup.h	2014-03-28 11:37:09.796688000 +0900
+ ***************
+ *** 105,110 ****
+ --- 105,113 ----
+   	u32	start;	/* physical start address */
+   };
+   
+ + /* FB TAG */
+ + #define ATAG_FB		0x54411002
+ + 
+   /* VGA text type displays */
+   #define ATAG_VIDEOTEXT	0x54410003
+   
+ diff -crN u-boot-2012.10_o/arch/arm/lib/board.c u-boot-2012.10/arch/arm/lib/board.c
+ *** u-boot-2012.10_o/arch/arm/lib/board.c	2012-10-16 00:14:08.000000000 +0900
+ --- u-boot-2012.10/arch/arm/lib/board.c	2014-03-28 11:37:26.037617000 +0900
+ ***************
+ *** 331,336 ****
+ --- 331,340 ----
+   
+   	addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size;
+   
+ + #ifdef CONFIG_MACH_CKB_3352
+ + 	addr -= CONFIG_CKB_RESERVED_MEM;		/* reserve memory (donot use this in U-boot) */
+ + #endif
+ + 
+   #ifdef CONFIG_LOGBUFFER
+   #ifndef CONFIG_ALT_LB_ADDR
+   	/* reserve kernel log buffer */
+ ***************
+ *** 374,379 ****
+ --- 378,384 ----
+   #endif /* CONFIG_FB_ADDR */
+   #endif /* CONFIG_LCD */
+   
+ + #ifndef CONFIG_NO_RELOCATE_UBOOT
+   	/*
+   	 * reserve memory for U-Boot code, data & bss
+   	 * round down to next 4 kB limit
+ ***************
+ *** 382,387 ****
+ --- 387,393 ----
+   	addr &= ~(4096 - 1);
+   
+   	debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, addr);
+ + #endif
+   
+   #ifndef CONFIG_SPL_BUILD
+   	/*
+ ***************
+ *** 438,447 ****
+ --- 444,466 ----
+   	dram_init_banksize();
+   	display_dram_config();	/* and display it */
+   
+ + #ifdef CONFIG_NO_RELOCATE_UBOOT
+ + 	addr = _TEXT_BASE;
+ + #endif
+ + 
+   	gd->relocaddr = addr;
+   	gd->start_addr_sp = addr_sp;
+   	gd->reloc_off = addr - _TEXT_BASE;
+ + #ifdef CONFIG_MACH_CKB_3352
+ + #ifndef CONFIG_NO_RELOCATE_UBOOT
+ + 	printf("Relocating U-Boot to %08lX, Offset: %08lX\n", gd->relocaddr, gd->reloc_off);
+ + #endif
+ + 	printf("Malloc area at %08lX, len=%dkB\n", gd->bd+sizeof(bd_t), TOTAL_MALLOC_LEN>>10);
+ + 	printf("Board info at %08lX, len=%d bytes\n", gd->bd, sizeof(bd_t));
+ + 	printf("Stack at %08lX\n", gd->start_addr_sp);
+ + #else
+   	debug("relocation Offset is: %08lx\n", gd->reloc_off);
+ + #endif
+   	memcpy(id, (void *)gd, sizeof(gd_t));
+   
+   	relocate_code(addr_sp, id, addr);
+ ***************
+ *** 453,458 ****
+ --- 472,478 ----
+   static char *failed = "*** failed ***\n";
+   #endif
+   
+ + 
+   /*
+    ************************************************************************
+    *
+ ***************
+ *** 513,518 ****
+ --- 533,544 ----
+   	arch_early_init_r();
+   #endif
+   
+ + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
+ + 	unsigned long env_addr = gd->env_addr;
+ + 	gd->env_addr = malloc(CONFIG_ENV_SIZE);
+ + 	memcpy(gd->env_addr, env_addr, CONFIG_ENV_SIZE);
+ + #endif
+ + 
+   #if !defined(CONFIG_SYS_NO_FLASH)
+   	puts("Flash: ");
+   
+ ***************
+ *** 542,547 ****
+ --- 568,577 ----
+   	}
+   #endif
+   
+ + #ifdef CONFIG_MACH_CKB_3352
+ + 	init_lcd_and_display_logo();
+ + #endif
+ + 
+   #if defined(CONFIG_CMD_NAND)
+   	puts("NAND:  ");
+   	nand_init();		/* go init the NAND */
+ ***************
+ *** 649,654 ****
+ --- 679,690 ----
+   	}
+   #endif
+   
+ + #ifdef CONFIG_MACH_CKB_3352
+ + 	volatile extern int _loader_executed_uboot;
+ + 	if(!_loader_executed_uboot)
+ + 		printf("U-Boot has been copied to 0x%X, use the command \""FLASH_UBOOT_CMD_STR"\" to write U-Boot to flash memory\n", UBOOT_TEMP_ADDR);
+ + #endif
+ + 
+   	/* main_loop() can return to retry autoboot, if so just run it again. */
+   	for (;;) {
+   		main_loop();
+ diff -crN u-boot-2012.10_o/arch/arm/lib/bootm.c u-boot-2012.10/arch/arm/lib/bootm.c
+ *** u-boot-2012.10_o/arch/arm/lib/bootm.c	2012-10-16 00:14:08.000000000 +0900
+ --- u-boot-2012.10/arch/arm/lib/bootm.c	2014-03-28 11:37:40.327435000 +0900
+ ***************
+ *** 140,145 ****
+ --- 140,153 ----
+   
+   		params = tag_next (params);
+   	}
+ + #ifdef CONFIG_FB_BASE_ADDRESS
+ + 	/* fill FB address */
+ + 	params->hdr.tag = ATAG_FB;
+ + 	params->hdr.size = tag_size (tag_mem32);
+ + 	params->u.mem.start = CONFIG_FB_BASE_ADDRESS;
+ + 	params->u.mem.size = CONFIG_FB_MAP_SIZE;
+ + 	params = tag_next (params);
+ + #endif
+   }
+   #endif
+   
+ diff -crN u-boot-2012.10_o/board/computex/ckb-3352/cmd_custom.c u-boot-2012.10/board/computex/ckb-3352/cmd_custom.c
+ *** u-boot-2012.10_o/board/computex/ckb-3352/cmd_custom.c	1970-01-01 09:00:00.000000000 +0900
+ --- u-boot-2012.10/board/computex/ckb-3352/cmd_custom.c	2014-03-28 11:38:11.202201000 +0900
+ ***************
+ *** 0 ****
+ --- 1,530 ----
+ + /*
+ +  * Computex CKB board additional commands
+ +  *
+ +  * Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; version 2 of the License.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ +  *
+ +  */
+ + #include <common.h>
+ + #include <command.h>
+ + 
+ + extern int do_mem_cp ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+ + extern int do_flerase (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+ + extern int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+ + 
+ + //U_BOOT_CMD(name,maxargs,repeatable,command,"usage","help")
+ + volatile extern int _approx_uboot_len;
+ + volatile extern int _loader_executed_uboot;
+ + extern int ckb_3352_cur_flash_bank;
+ + 
+ + #define KERNEL_FLASH_BANK				8
+ + #define KERNEL_FLASH_BANK_STR			"8"
+ + 
+ + #ifdef CONFIG_SYS_USE_NOR
+ + 
+ + int parse_bank_n_address(char *str, int *bank, ulong *addr)
+ + {
+ + 	char *p;
+ + 
+ + 	/* check for ":" */
+ + 	if ((p = strchr (str, ':')) == NULL)
+ + 	{
+ + 		printf ("Flash bank not specified.\n");
+ + 		return 1;
+ + 	}
+ + 	*bank = simple_strtoul (str, NULL, 10);
+ + 	*p++ = '\0';
+ + 	*addr = simple_strtoul(p, NULL, 16);
+ + 	return 0;
+ + }
+ + 
+ + int get_required_flash_sectors(int len)
+ + {
+ + 	int banks = len / CONFIG_SYS_FLASH_SECT_SZ;
+ + 	if(len % CONFIG_SYS_FLASH_SECT_SZ)
+ + 		banks++;
+ + 	return banks;
+ + }
+ + 
+ + int erase_and_write(cmd_tbl_t *cmdtp, int flag, char *image_name, ulong src_addr, int bank, ulong len)
+ + {
+ + 	char addr1[16], length[16], addr2[16];
+ + 	char *temp_argv[5];
+ + 	ulong flash_addr;
+ + 	printf("Writing %s from 0x%X to NOR Bank#%d, %ld bytes\n", image_name, src_addr, bank, len);
+ + 
+ + 	printf ("Erasing Flash...\n");
+ + 	temp_argv[0] = "erase";
+ + 	flash_addr = CONFIG_SYS_FLASH_BASE + (bank*CONFIG_FLASH_CKB_BANK_SIZE);
+ + 	sprintf(addr1, "%X", flash_addr);
+ + 	/* length must be aligned */
+ + 	sprintf(addr2, "%X", flash_addr + ((get_required_flash_sectors(len)*CONFIG_SYS_FLASH_SECT_SZ) - 1));
+ + 	temp_argv[1] = addr1;
+ + 	temp_argv[2] = addr2;
+ + 	//printf("Actual %s %s\n",  addr1, addr2);
+ + 	if(do_flerase(cmdtp, flag, 3, temp_argv))
+ + 	{
+ + _failed:
+ + 		printf ("Failed\n");
+ + 		return 1;
+ + 	}
+ + 	printf ("Flashing %s...\n", image_name);
+ + 	/* write Uboot to flash */
+ + 	temp_argv[0] = "cp.b";
+ + 	sprintf(addr2, "%X", src_addr);
+ + 	sprintf(length, "%X", len);
+ + 	temp_argv[1] = addr2;				/* source address */
+ + 	temp_argv[2] = addr1;				/* destination flash address */
+ + 	temp_argv[3] = length;				/* count */
+ + 	if(do_mem_cp(cmdtp, flag, 4, temp_argv))
+ + 	{
+ + 		goto _failed;
+ + 	}
+ + 	return 0;
+ + }
+ + 
+ + 
+ + int ckb_flash_uboot(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+ + {
+ + 	if(argc!=1)
+ + 	{
+ + 		goto usage;
+ + 	}
+ + 	return erase_and_write(cmdtp, flag, "U-boot", UBOOT_TEMP_ADDR, (UBOOT_NOR_BASE_ADDR-CONFIG_SYS_FLASH_BASE)/CONFIG_FLASH_CKB_BANK_SIZE,
+ + 				_approx_uboot_len);
+ + 
+ + usage:
+ + 	cmd_usage(cmdtp);
+ + 	return 1;
+ + }
+ + 
+ + U_BOOT_CMD(flash_uboot,1,0,ckb_flash_uboot,"Write U-Boot(current U-Boot binary) to NOR flash","");
+ + 
+ + int ctex_check_flash_bank(int bank)
+ + {
+ + 	if(bank<0 || bank>=CONFIG_FLASH_CKB_BANKS)
+ + 	{
+ + 		printf ("Invalid flash bank %d. Valid value 0~%d.\n", bank, CONFIG_FLASH_CKB_BANKS-1);
+ + 		return 1;
+ + 	}
+ + 	return 0;
+ + }
+ + 
+ + int ctex_check_flash_addr(ulong addr)
+ + {
+ + 	if(addr<CONFIG_SYS_FLASH_BASE || addr>=(CONFIG_SYS_FLASH_BASE+CONFIG_FLASH_CKB_BANK_SIZE))
+ + 	{
+ + 		printf ("Invalid flash address 0x%X. Valid value 0x%X~0x%X.\n", addr, 
+ + 					CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+CONFIG_FLASH_CKB_BANK_SIZE-1);
+ + 		return 1;
+ + 	}
+ + 	return 0;
+ + }
+ + 
+ + int ctex_flash_boundary_check(ulong addr, int bank, ulong count, ulong *actual_addr)
+ + {
+ + 	
+ + 	if(ctex_check_flash_bank(bank) || ctex_check_flash_addr(addr))
+ + 		return 1;
+ + 
+ + 	/* get actual flash address */
+ + 	addr = addr+(bank*CONFIG_FLASH_CKB_BANK_SIZE);
+ + 	if((addr+count) > (CONFIG_SYS_FLASH_BASE+(CONFIG_FLASH_CKB_BANK_SIZE*CONFIG_FLASH_CKB_BANKS)))
+ + 	{
+ + 		printf ("Data overflow. Count exceeds flash limit\n");
+ + 		return 1;
+ + 	}
+ + 	*actual_addr = addr;
+ + 	return 0;
+ + }
+ + 
+ + int ctex_flash_write(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+ + {
+ + 	char *temp_argv[4];
+ + 	ulong	addr, count;
+ + 	int bank;
+ + 	char addr1[16];
+ + 	if(argc!=4)
+ + 	{
+ + 		goto usage;
+ + 	}
+ + 	/* address check */
+ + 	if(parse_bank_n_address(argv[2], &bank, &addr))
+ + 	{
+ + 		goto usage;
+ + 	}
+ + 	count = simple_strtoul(argv[3], NULL, 16);
+ + 	if(ctex_flash_boundary_check(addr, bank, count, &addr))
+ + 		return 1;
+ + 
+ + 	temp_argv[0] = "cp.b";
+ + 	temp_argv[1] = argv[1];				/* source address */
+ + 	/* The actual flash address */
+ + 	sprintf(addr1, "%X", addr);
+ + 	temp_argv[2] = addr1;				/* destination flash address */
+ + 	temp_argv[3] = argv[3];				/* count */
+ + 	return do_mem_cp(cmdtp, flag, 4, temp_argv);
+ + 	
+ + usage:
+ + 	cmd_usage(cmdtp);
+ + 	return 1;
+ + }
+ + 
+ + /* flash write command */
+ + U_BOOT_CMD(fwrite,4,1,ctex_flash_write,
+ + 	"Write to flash memory",
+ + 	"source N:target count\n"
+ + 	"    - Write 'count' bytes from addr 'source' to flash addr 'target' of bank 'N'\n"
+ + 	);
+ + 
+ + 
+ + int ctex_flash_read(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+ + {
+ + 	char *temp_argv[4];
+ + 	ulong	addr, count;
+ + 	int bank;
+ + 	char addr1[16];
+ + 	if(argc!=4)
+ + 	{
+ + 		goto usage;
+ + 	}
+ + 	/* address check */
+ + 	if(parse_bank_n_address(argv[1], &bank, &addr))
+ + 	{
+ + 		goto usage;
+ + 	}
+ + 	/* address check */
+ + 	count = simple_strtoul(argv[3], NULL, 16);
+ + 	if(ctex_flash_boundary_check(addr, bank, count, &addr))
+ + 		return 1;
+ + 
+ + 	temp_argv[0] = "cp.b";
+ + 	/* The actual flash address */
+ + 	sprintf(addr1, "%X", addr);
+ + 	temp_argv[1] = addr1;				/* source flash address */
+ + 	temp_argv[2] = argv[2];				/* destination address */
+ + 	temp_argv[3] = argv[3];				/* count */
+ + 	return do_mem_cp(cmdtp, flag, 4, temp_argv);
+ + 	
+ + usage:
+ + 	cmd_usage(cmdtp);
+ + 	return 1;
+ + }
+ + 
+ + /* flash read command */
+ + U_BOOT_CMD(fread,4,1,ctex_flash_read,
+ + 	"Read from flash memory",
+ + 	"N:source target count\n"
+ + 	"    - Read 'count' bytes from flash addr 'source' of bank 'N' to addr 'target'\n"
+ + 	);
+ + 	
+ + 
+ + int ctex_flash_erase(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+ + {
+ + 	char *temp_argv[3];
+ + 	ulong start_addr, end_addr;
+ + 	char addr1[16], addr2[16];
+ + 	int bank, bank_end;
+ + 	temp_argv[0] = "erase";
+ + 
+ + 	if(argc == 2 && strcmp(argv[1], "all") == 0) 
+ + 	{
+ + 		temp_argv[1] = argv[1];
+ + 		return do_flerase(cmdtp, flag, 2, temp_argv);
+ + 	}
+ + 	if(argc == 2 || argc == 3)
+ + 	{
+ + 		/* get the bank */
+ + 		bank = simple_strtoul (argv[1], NULL, 10);
+ + 		if(ctex_check_flash_bank(bank))
+ + 			return 1;
+ + 
+ + 		/* get the actual address and erase the bank */
+ + 		start_addr = (bank*CONFIG_FLASH_CKB_BANK_SIZE) | CONFIG_SYS_FLASH_BASE;
+ + 		if(argc == 2)
+ + 		{
+ + 			end_addr = start_addr + CONFIG_FLASH_CKB_BANK_SIZE-1;
+ + 		}
+ + 		else
+ + 		{
+ + 			bank_end = simple_strtoul (argv[2], NULL, 10);
+ + 			if(ctex_check_flash_bank(bank_end))
+ + 				return 1;
+ + 			end_addr =  ((bank_end*CONFIG_FLASH_CKB_BANK_SIZE) | CONFIG_SYS_FLASH_BASE) + CONFIG_FLASH_CKB_BANK_SIZE-1;
+ + 		}
+ + 
+ + 		sprintf(addr1, "%X", start_addr);
+ + 		sprintf(addr2, "%X", end_addr);
+ + 		//printf("Actual %X %X\n",  start_addr, end_addr);
+ + 		temp_argv[1] = addr1;
+ + 		temp_argv[2] = addr2;
+ + 		return do_flerase(cmdtp, flag, 3, temp_argv);
+ + 	}
+ + 
+ + usage:
+ + 	cmd_usage(cmdtp);
+ + 	return 1;
+ + }
+ + 
+ + U_BOOT_CMD(
+ + 	erase,   3,   0,  ctex_flash_erase,
+ + 	"erase FLASH memory",
+ + 	" N\n   - erase FLASH bank 'N'\n"
+ + 	"erase n1 n2\n   - erase FLASH bank 'n1' through 'n2'\n"
+ + 	"erase all\n    - erase all FLASH banks"
+ + );
+ + 
+ + int ctex_flash_protect(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+ + {
+ + 	char *temp_argv[4];
+ + 	ulong start_addr, end_addr;
+ + 	char addr1[16], addr2[16];
+ + 	int bank;
+ + 	temp_argv[0] = "protect";
+ + 
+ + 	if(argc<3 || (strcmp(argv[1], "on") && strcmp(argv[1], "off")))
+ + 	{
+ + 		goto usage;
+ + 	}
+ + 	temp_argv[1] = argv[1];
+ + 
+ + 	if(argc == 3)
+ + 	{
+ + 		char *p;
+ + 		if (strcmp(argv[2], "all") == 0) {
+ + 			temp_argv[2] = argv[2];
+ + 			return do_protect(cmdtp, flag, 3, temp_argv);
+ + 		}
+ + 
+ + 		/* address not specified; get the bank */
+ + 		bank = simple_strtoul (argv[2], NULL, 10);
+ + 		if(ctex_check_flash_bank(bank))
+ + 			return 1;
+ + 		/* get the actual address */
+ + 		start_addr = (bank*CONFIG_FLASH_CKB_BANK_SIZE) | CONFIG_SYS_FLASH_BASE;
+ + 		end_addr = start_addr + CONFIG_FLASH_CKB_BANK_SIZE-1;
+ + 		sprintf(addr1, "%X", start_addr);
+ + 		sprintf(addr2, "%X", end_addr);
+ + 		//printf("Actual %X %X\n",  start_addr, end_addr);
+ + 		temp_argv[2] = addr1;
+ + 		temp_argv[3] = addr2;
+ + 		return do_protect(cmdtp, flag, 4, temp_argv);
+ + 	}
+ + usage:
+ + 	cmd_usage(cmdtp);
+ + 	return 1;
+ + }
+ + 
+ + U_BOOT_CMD(
+ + 	protect, 3,  0,   ctex_flash_protect,
+ + 	"enable or disable FLASH write protection",
+ + 	"on  N\n    - protect FLASH bank 'N'\n"
+ + 	"protect on  all\n    - protect all FLASH banks\n"
+ + 	"protect off N\n    - make FLASH bank 'N' writable\n"
+ + 	"protect off all\n    - make all FLASH banks writable"
+ + );
+ + 
+ + int ctex_set_flash_bank(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+ + {
+ + 	int bank;
+ + 	if(argc != 2)
+ + 	{
+ + 		goto usage;
+ + 	}
+ + 
+ + 	/* get the bank */
+ + 	bank = simple_strtoul (argv[1], NULL, 10);
+ + 	if(ctex_check_flash_bank(bank))
+ + 		return 1;
+ + 	set_nor_flash_bank(bank);
+ + 	return 0;
+ + usage:
+ + 	cmd_usage(cmdtp);
+ + 	return 1;
+ + }
+ + 
+ + U_BOOT_CMD(
+ + 	fbank_set,   2,   0,  ctex_set_flash_bank,
+ + 	"Set FLASH memory bank",
+ + 	"N\n    - Set FLASH memory bank to 'N'"
+ + );
+ + 
+ + 
+ + int ckb_flash_kernel(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+ + {
+ + 	ulong addr;
+ + 	image_header_t *hdr;
+ + 	ulong size;
+ + 	if(argc != 2) 
+ + 	{
+ + 		goto usage;
+ + 	}
+ + 	addr = simple_strtoul (argv[1], NULL, 16);
+ + 	/* check for the kernel header */
+ + 	hdr = (image_header_t *)addr;
+ + 	size = image_get_data_size(hdr) + sizeof(image_header_t);
+ + 	if(size < CKB_KERN_MIN_SIZE ||  size > CKB_KERN_MAX_SIZE)
+ + 	{
+ + 		printf ("Image size is %d (0x%08X) bytes which is too %s\n", size, size,
+ + 					(size < CKB_KERN_MIN_SIZE)?"small":"large");
+ + 		return 1;
+ + 	}
+ + 	return erase_and_write(cmdtp, flag, "Kernel", addr, KERNEL_FLASH_BANK, size);
+ + 
+ + usage:
+ + 	cmd_usage(cmdtp);
+ + 	return 1;
+ + }
+ + 
+ + U_BOOT_CMD(
+ + 	flash_kernel,   2,   0,  ckb_flash_kernel,
+ + 	"Write Kernel binary (uImage) to NOR flash",
+ + 	"addr\n    - Write Kernel from SDRAM address 'addr' to NOR Bank# "KERNEL_FLASH_BANK_STR":0x08000000"
+ + );
+ + 
+ + int ckb_fread_kernel(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+ + {
+ + 	ulong addr;
+ + 	image_header_t *hdr;
+ + 	ulong size;
+ + 	ulong faddr;
+ + 	char *temp_argv[4];
+ + 	char addr1[16], count[16];
+ + 	if(argc != 2)
+ + 	{
+ + 		goto usage;
+ + 	}
+ + 	addr = simple_strtoul (argv[1], NULL, 16);
+ + 	/* check for the kernel at the flash bank */
+ + 	int cur_bank = ckb_3352_cur_flash_bank;
+ + 	set_nor_flash_bank(KERNEL_FLASH_BANK);
+ + 	hdr = (image_header_t *)CONFIG_SYS_FLASH_BASE;
+ + 	size = image_get_data_size(hdr) + sizeof(image_header_t);
+ + 	printf ("Reading Kernel from NOR Bank# "KERNEL_FLASH_BANK_STR" to 0x%X\n", addr);
+ + 	if(size < CKB_KERN_MIN_SIZE || size > CKB_KERN_MAX_SIZE)
+ + 	{
+ + 		printf ("Kernel Image size is %d (0x%08X) bytes which is too %s\n", size, size,
+ + 					(size < CKB_KERN_MIN_SIZE)?"small":"large");
+ + 		printf ("Ignoring command\n");
+ + 		set_nor_flash_bank(cur_bank);
+ + 		return 1;
+ + 	}
+ + 	printf ("%d (0x%08X) bytes\n", size, size);
+ + 	/* get actual flash address */
+ + 	faddr = CONFIG_SYS_FLASH_BASE+(KERNEL_FLASH_BANK*CONFIG_FLASH_CKB_BANK_SIZE);
+ + 	/* copy the kernel image to the specified address */
+ + 	temp_argv[0] = "cp.b";
+ + 	/* The actual flash address */
+ + 	sprintf(addr1, "%X", faddr);
+ + 	temp_argv[1] = addr1;				/* source flash address */
+ + 	temp_argv[2] = argv[1];				/* destination address */
+ + 	sprintf(count, "%X", size);
+ + 	temp_argv[3] = count;				/* count */
+ + 	return do_mem_cp(cmdtp, flag, 4, temp_argv);
+ + 	
+ + usage:
+ + 	cmd_usage(cmdtp);
+ + 	return 1;
+ + }
+ + 
+ + U_BOOT_CMD(
+ + 	fread_kernel,   2,   0,  ckb_fread_kernel,
+ + 	"Read Kernel binary (uImage) from NOR flash",
+ + 	"addr\n    - Read Kernel from NOR Bank# "KERNEL_FLASH_BANK_STR":0x08000000 to SDRAM address 'addr'"
+ + );
+ + 
+ + int ckb_flash_bootloader(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+ + {
+ + 	ulong addr;
+ + 	ulong size;
+ + 	if(argc == 2) 
+ + 	{
+ + 		size = 0x2000;
+ + 	}
+ + 	else if(argc == 3)
+ + 	{
+ + 		size = simple_strtoul (argv[2], NULL, 16);
+ + 	}
+ + 	else
+ + 	{
+ + 		goto usage;
+ + 	}
+ + 	addr = simple_strtoul (argv[1], NULL, 16);
+ + 	if(size > MAX_BOOTLOADER_FILE_SIZE)
+ + 	{
+ + 		printf ("Image size is %d (0x%08X) which is too large. Max allowed size = %d (0x%08X)\n", size, size, MAX_BOOTLOADER_FILE_SIZE, MAX_BOOTLOADER_FILE_SIZE);
+ + 		return 1;
+ + 	}
+ + 	return erase_and_write(cmdtp, flag, "Bootloader", addr, 0, size);
+ + 
+ + usage:
+ + 	cmd_usage(cmdtp);
+ + 	return 1;
+ + }
+ + 
+ + U_BOOT_CMD(
+ + 	flash_bootloader,   3,   0,  ckb_flash_bootloader,
+ + 	"Write bootloader binary to NOR flash",
+ + 	"addr [len]\n    - Write Bootloader from SDRAM address 'addr' to NOR Bank# 0:0x08000000.\n       'len' is optional; the default value is 0x2000"
+ + );
+ + 
+ + 
+ + int ckb_flash_titleimage(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+ + {
+ + 	ulong addr;
+ + 	ulong size;
+ + 	if(argc == 2) 
+ + 	{
+ + 		size = 0x40000;
+ + 	}
+ + 	else if(argc == 3)
+ + 	{
+ + 		size = simple_strtoul (argv[2], NULL, 16);
+ + 	}
+ + 	else
+ + 	{
+ + 		goto usage;
+ + 	}
+ + 	addr = simple_strtoul (argv[1], NULL, 16);
+ + 	if(size > MAX_LCD_IMAGE_FILE_SIZE)
+ + 	{
+ + 		printf ("Image size is %d (0x%08X) which is too large. Max allowed size = %d (0x%08X)\n", size, size, MAX_LCD_IMAGE_FILE_SIZE, MAX_LCD_IMAGE_FILE_SIZE);
+ + 		return 1;
+ + 	}
+ + 	return erase_and_write(cmdtp, flag, "LCD image", addr, 4, size);
+ + 
+ + usage:
+ + 	cmd_usage(cmdtp);
+ + 	return 1;
+ + }
+ + 
+ + U_BOOT_CMD(
+ + 	flash_titleimage,   3,   0,  ckb_flash_titleimage,
+ + 	"Write title image to NOR flash",
+ + 	"addr [len]\n    - Write title image from SDRAM address 'addr' to NOR Bank# 4:0x08000000.\n       'len' is optional; the default value is 0x40000"
+ + );
+ + 
+ + #endif
+ + 
+ + 
+ + 
+ + 
+ + 
+ + 
+ + 
+ + 
+ + 
+ + 
+ + 
+ diff -crN u-boot-2012.10_o/board/computex/ckb-3352/lcd.c u-boot-2012.10/board/computex/ckb-3352/lcd.c
+ *** u-boot-2012.10_o/board/computex/ckb-3352/lcd.c	1970-01-01 09:00:00.000000000 +0900
+ --- u-boot-2012.10/board/computex/ckb-3352/lcd.c	2014-03-28 10:20:56.671121000 +0900
+ ***************
+ *** 0 ****
+ --- 1,826 ----
+ + /*
+ +  * CKB board Display Logo source
+ +  *
+ +  * Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; either version 2 of the License, or
+ +  * (at your option) any later version.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ +  */
+ + #include <asm/arch/cpu.h>
+ + #include <asm/arch/hardware.h>
+ + #include <asm/arch/omap.h>
+ + #include <asm/arch/ddr_defs.h>
+ + #include <asm/arch/clock.h>
+ + #include <asm/arch/gpio.h>
+ + #include <asm/arch/mem.h>
+ + #include <asm/arch/mmc_host_def.h>
+ + #include <asm/arch/sys_proto.h>
+ + #include <asm/io.h>
+ + #include <asm/emif.h>
+ + #include <asm/gpio.h>
+ + #include <common.h>
+ + #include <asm/omap_gpio.h>
+ + 
+ + DECLARE_GLOBAL_DATA_PTR;
+ + #define HALF_IMAGE
+ + 
+ + char displaying_ckb_logo = 0;
+ + 
+ + #if defined(CONFIG_CKB_LCD_01) || defined(CONFIG_CKB_LCD_02) || defined(CONFIG_CKB_DVI)
+ + 
+ + /* donot optimize the code in this file */
+ + //#pragma GCC optimize ("O0")
+ + 
+ + #define LCD_VERSION_1	1
+ + #define LCD_VERSION_2	2
+ + 
+ + 
+ + 
+ + 
+ + #define FB_PALETTE_SIZE					(16*2)				/* Palette size */
+ + #define LCD_16_BPP_PALETTE				0x4000
+ + #define FB_PALLET_ADDRESS				(CONFIG_FB_BASE_ADDRESS-FB_PALETTE_SIZE)
+ + 
+ + #define LCD_IN_CLK					300000000
+ + 
+ + /* LCD Status Register */
+ + #define LCD_END_OF_FRAME1		BIT(9)
+ + #define LCD_END_OF_FRAME0		BIT(8)
+ + #define LCD_PL_LOAD_DONE		BIT(6)
+ + #define LCD_FIFO_UNDERFLOW		BIT(5)
+ + #define LCD_SYNC_LOST			BIT(2)
+ + 
+ + /* LCD DMA Control Register */
+ + #define LCD_DMA_BURST_SIZE(x)		((x) << 4)
+ + #define LCD_DMA_BURST_1			0x0
+ + #define LCD_DMA_BURST_2			0x1
+ + #define LCD_DMA_BURST_4			0x2
+ + #define LCD_DMA_BURST_8			0x3
+ + #define LCD_DMA_BURST_16		0x4
+ + #define LCD_V1_END_OF_FRAME_INT_ENA	BIT(2)
+ + #define LCD_V2_END_OF_FRAME0_INT_ENA	BIT(8)
+ + #define LCD_V2_END_OF_FRAME1_INT_ENA	BIT(9)
+ + #define LCD_DUAL_FRAME_BUFFER_ENABLE	BIT(0)
+ + 
+ + /* LCD Control Register */
+ + #define LCD_CLK_DIVISOR(x)		((x) << 8)
+ + #define LCD_RASTER_MODE			0x01
+ + 
+ + /* LCD Raster Control Register */
+ + #define LCD_PALETTE_LOAD_MODE(x)	((x) << 20)
+ + #define PALETTE_AND_DATA		0x00
+ + #define PALETTE_ONLY			0x01
+ + #define DATA_ONLY			0x02
+ + 
+ + #define LCD_MONO_8BIT_MODE		BIT(9)
+ + #define LCD_RASTER_ORDER		BIT(8)
+ + #define LCD_TFT_MODE			BIT(7)
+ + #define LCD_V1_UNDERFLOW_INT_ENA	BIT(6)
+ + #define LCD_V2_UNDERFLOW_INT_ENA	BIT(5)
+ + #define LCD_V1_PL_INT_ENA		BIT(4)
+ + #define LCD_V2_PL_INT_ENA		BIT(6)
+ + #define LCD_MONOCHROME_MODE		BIT(1)
+ + #define LCD_RASTER_ENABLE		BIT(0)
+ + #define LCD_TFT_ALT_ENABLE		BIT(23)
+ + #define LCD_STN_565_ENABLE		BIT(24)
+ + #define LCD_V2_DMA_CLK_EN		BIT(2)
+ + #define LCD_V2_LIDD_CLK_EN		BIT(1)
+ + #define LCD_V2_CORE_CLK_EN		BIT(0)
+ + #define LCD_V2_LPP_B10			26
+ + #define LCD_V2_TFT_24BPP_MODE		BIT(25)
+ + #define LCD_V2_TFT_24BPP_UNPACK		BIT(26)
+ + 
+ + /* LCD Raster Timing 2 Register */
+ + #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x)	((x) << 16)
+ + #define LCD_AC_BIAS_FREQUENCY(x)		((x) << 8)
+ + #define LCD_SYNC_CTRL				BIT(25)
+ + #define LCD_SYNC_EDGE				BIT(24)
+ + #define LCD_INVERT_PIXEL_CLOCK			BIT(22)
+ + #define LCD_INVERT_LINE_CLOCK			BIT(21)
+ + #define LCD_INVERT_FRAME_CLOCK			BIT(20)
+ + 
+ + /* LCD Block */
+ + #define  LCD_PID_REG				0x0
+ + #define  LCD_CTRL_REG				0x4
+ + #define  LCD_STAT_REG				0x8
+ + #define  LCD_RASTER_CTRL_REG			0x28
+ + #define  LCD_RASTER_TIMING_0_REG		0x2C
+ + #define  LCD_RASTER_TIMING_1_REG		0x30
+ + #define  LCD_RASTER_TIMING_2_REG		0x34
+ + #define  LCD_DMA_CTRL_REG			0x40
+ + #define  LCD_DMA_FRM_BUF_BASE_ADDR_0_REG	0x44
+ + #define  LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG	0x48
+ + #define  LCD_DMA_FRM_BUF_BASE_ADDR_1_REG	0x4C
+ + #define  LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG	0x50
+ + 
+ + /* Interrupt Registers available only in Version 2 */
+ + #define  LCD_RAW_STAT_REG			0x58
+ + #define  LCD_MASKED_STAT_REG			0x5c
+ + #define  LCD_INT_ENABLE_SET_REG			0x60
+ + #define  LCD_INT_ENABLE_CLR_REG			0x64
+ + #define  LCD_END_OF_INT_IND_REG			0x68
+ + 
+ + /* Clock registers available only on Version 2 */
+ + #define  LCD_CLK_ENABLE_REG			0x6c
+ + #define  LCD_CLK_RESET_REG			0x70
+ + #define  LCD_CLK_MAIN_RESET			BIT(3)
+ + 
+ + #define GPIO_DISP_POWER				7		/* lcd power GPIO3[7] */
+ + #define GPIO_BACKLIGHT_POWER		8		/* lcd backlight  GPIO3[8] */
+ + /* TPS for backlight */
+ + #define GPIO_TPS_BACKLIGHT			19	/* lcd backlight TPS power GPIO3[19] */
+ + 
+ + #if defined(CONFIG_CKB_LCD_01) && defined(CONFIG_CKB_LCD_02)
+ + Error "Only one LCD type can be defined" 
+ + #endif
+ + 
+ + struct da8xx_panel *g_lcdpanel;
+ + 
+ + struct da8xx_panel {
+ + 	char *name;
+ + 	unsigned short	width;
+ + 	unsigned short	height;
+ + 	int		hfp;		/* Horizontal front porch */
+ + 	int		hbp;		/* Horizontal back porch */
+ + 	int		hsw;		/* Horizontal Sync Pulse Width */
+ + 	int		vfp;		/* Vertical front porch */
+ + 	int		vbp;		/* Vertical back porch */
+ + 	int		vsw;		/* Vertical Sync Pulse Width */
+ + 	unsigned int	pxl_clk;	/* Pixel clock */
+ + 	unsigned char	invert_pxl_clk;	/* Invert Pixel clock */
+ + 	int bpp;
+ + 	int dma_burst_sz;
+ + 	int fifo_th;
+ + 	int fdd;			/* FIFO DMA delay */
+ + 	int ac_bias;
+ + 	int ac_bias_intrpt;
+ + 	int sync_ctrl;				/* sync control */
+ + 	int sync_edge;				/* sync edge */
+ + 	int invert_line_clock;			/* invert line clock */
+ + 	int invert_frm_clock;			/* invert frame clock */
+ + };
+ + 
+ + #ifdef CONFIG_CKB_LCD_01
+ + struct da8xx_panel VisionxKTM050AL02 = {
+ + 		/* Visionx KTM050AL02 */
+ + 		.name = "Visionx KTM050AL02",
+ + 		.width = 800,
+ + 		.height = 480,
+ + 		.hfp = 40,
+ + 		.hbp = 40,
+ + 		.hsw = 48,
+ + 		.vfp = 13,
+ + 		.vbp = 29,
+ + 		.vsw = 3,
+ + 		.pxl_clk = 33000000,
+ + 		.invert_pxl_clk = 0,
+ + 		.dma_burst_sz = 16,
+ + 		.fifo_th = 6,
+ + 		.bpp = 16,
+ + 		.fdd = 255,
+ + 		.ac_bias		= 255,
+ + 		.ac_bias_intrpt		= 0,
+ + 		.sync_ctrl = 1,
+ + 		.sync_edge = 0,
+ + 		.invert_line_clock = 1, 
+ + 		.invert_frm_clock = 1,
+ + };
+ + #endif
+ + #ifdef CONFIG_CKB_LCD_02
+ + struct da8xx_panel KyoceraTCG070WVLPAAFA_AA00 = {
+ + 		/* Kyocera TCG070WVLPAAFA_AA00 */
+ + 		.name = "Kyocera TCG070WVLPAAFA_AA00",
+ + 		.width = 800,
+ + 		.height = 480,
+ + 		.hfp = 40,			/* right_margin */
+ + 		.hbp = 88,			/* left_margin */
+ + 		.hsw = 128,			/* hsync_len */
+ + 		.vfp = 11,			/* lower_margin */
+ + 		.vbp = 32,			/* upper_margin */
+ + 		.vsw = 2,			/* vsync_len */
+ + 		.pxl_clk = 33200000,
+ + 		.invert_pxl_clk = 0,
+ + 		.dma_burst_sz = 16,
+ + 		.fifo_th = 6,
+ + 		.bpp = 16,
+ + 		.fdd = 255,
+ + 		.ac_bias		= 255,
+ + 		.ac_bias_intrpt		= 0,
+ + 		.sync_ctrl = 1,
+ + 		.sync_edge = 0,
+ + 		.invert_line_clock = 1, 
+ + 		.invert_frm_clock = 1,
+ + };
+ + #endif
+ + #if !defined(CONFIG_CKB_LCD_01) && !defined(CONFIG_CKB_LCD_02)
+ + struct da8xx_panel generic_DVI_monitor = {
+ + 		/* Generic DVI monitor (This setting works for most monitors) */
+ + 		.name = "Generic DVI panel",
+ + 		.width = 800,
+ + 		.height = 480,
+ + 		.hfp = 40,
+ + 		.hbp = 40,
+ + 		.hsw = 48,
+ + 		.vfp = 13,
+ + 		.vbp = 29,
+ + 		.vsw = 3,
+ + 		.pxl_clk = 33000000,
+ + 		.invert_pxl_clk = 0,
+ + 		.dma_burst_sz = 16,
+ + 		.fifo_th = 6,
+ + 		.bpp = 16,
+ + 		.fdd = 255,
+ + 		.ac_bias		= 255,
+ + 		.ac_bias_intrpt		= 0,
+ + 		.sync_ctrl = 1,
+ + 		.sync_edge = 0,
+ + 		.invert_line_clock = 1, 
+ + 		.invert_frm_clock = 1,
+ + };
+ + #endif
+ + 
+ + static unsigned int lcd_revision;
+ + 
+ + inline unsigned int lcdc_read(unsigned int addr)
+ + {
+ + 	return __raw_readl(DA8XX_LCD_CNTRL_BASE + (addr));
+ + }
+ + 
+ + inline void lcdc_write(unsigned int val, unsigned int addr)
+ + {
+ + 	__raw_writel(val, DA8XX_LCD_CNTRL_BASE + (addr));
+ + }
+ + 
+ + /* Enable the Raster Engine of the LCD Controller */
+ + inline void lcd_enable_raster(void)
+ + {
+ + 	u32 reg;
+ + 
+ + 	/* Put LCDC in reset for several cycles */
+ + 	if (lcd_revision == LCD_VERSION_2)
+ + 	{
+ + 		lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
+ + 		mdelay(1);
+ + 	
+ + 		/* Bring LCDC out of reset */
+ + 		lcdc_write(0, LCD_CLK_RESET_REG);
+ + 		mdelay(1);
+ + 	}
+ + 
+ + 	/* Above reset sequence doesnot reset register context */
+ + 	reg = lcdc_read(LCD_RASTER_CTRL_REG);
+ + 	if (!(reg & LCD_RASTER_ENABLE))
+ + 		lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
+ + }
+ + 
+ + /* Disable the Raster Engine of the LCD Controller */
+ + inline void lcd_disable_raster()
+ + {
+ + 	lcdc_write(lcdc_read(LCD_RASTER_CTRL_REG) & (~LCD_RASTER_ENABLE), LCD_RASTER_CTRL_REG);
+ + 	/* there is not need to wait */
+ + }
+ + 
+ + 
+ + void lcd_fb_addr()
+ + {
+ + 	/* single FB mode and interrupt disable */
+ + 	if (lcd_revision == LCD_VERSION_1) 
+ + 	{
+ + 		/* single FB mode and interrupt disable */
+ + 		lcdc_write(lcdc_read(LCD_DMA_CTRL_REG) & 
+ + 					~(LCD_V1_END_OF_FRAME_INT_ENA|LCD_DUAL_FRAME_BUFFER_ENABLE),
+ + 				 LCD_DMA_CTRL_REG);
+ + 	
+ + 		/* palette and data */
+ + 		/* fill FB0 address register */
+ + 		lcdc_write(FB_PALLET_ADDRESS, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
+ + 		lcdc_write(FB_PALLET_ADDRESS+(g_lcdpanel->height*g_lcdpanel->width)*2+FB_PALETTE_SIZE-2,
+ + 						 LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
+ + #if 0
+ + 		lcdc_write(FB_PALLET_ADDRESS, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
+ + 		lcdc_write(FB_PALLET_ADDRESS+(g_lcdpanel->height*g_lcdpanel->width)*2+FB_PALETTE_SIZE-2,
+ + 						 LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
+ + #endif
+ + 		/* load palette and data */
+ + 		lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & ~(3<<20))
+ + 						| LCD_PALETTE_LOAD_MODE(PALETTE_AND_DATA), 
+ + 							LCD_RASTER_CTRL_REG);
+ + 	}
+ + 	else
+ + 	{
+ + 		/* single FB mode */
+ + 		lcdc_write(lcdc_read(LCD_DMA_CTRL_REG) & 
+ + 					~(LCD_DUAL_FRAME_BUFFER_ENABLE),
+ + 				 LCD_DMA_CTRL_REG);
+ + 		lcdc_write(lcdc_read(LCD_INT_ENABLE_SET_REG) &
+ + 				~(LCD_V2_END_OF_FRAME0_INT_ENA | LCD_V2_END_OF_FRAME1_INT_ENA
+ + 				| LCD_V2_UNDERFLOW_INT_ENA | LCD_SYNC_LOST),
+ + 				LCD_INT_ENABLE_SET_REG);
+ + 					 
+ + 		/* data only */
+ + 		/* fill FB0 address register */
+ + 		lcdc_write(CONFIG_FB_BASE_ADDRESS, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
+ + 		lcdc_write(CONFIG_FB_BASE_ADDRESS+(g_lcdpanel->height*g_lcdpanel->width)*2-2,
+ + 					 LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
+ + #if 0
+ + 		lcdc_write(CONFIG_FB_BASE_ADDRESS, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
+ + 		lcdc_write(CONFIG_FB_BASE_ADDRESS+(g_lcdpanel->height*g_lcdpanel->width)*2-2,
+ + 						 LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
+ + #endif
+ + 		/* load data */
+ + 		lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & ~(3<<20))
+ + 					| LCD_PALETTE_LOAD_MODE(DATA_ONLY), 
+ + 					LCD_RASTER_CTRL_REG);
+ + 	}
+ + 	
+ + }
+ + 
+ + /* Configure the Burst Size and fifo threhold of DMA */
+ + void lcd_cfg_dma(int burst_size,  int fifo_th)
+ + {
+ + 	u32 reg;
+ + 
+ + 	reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001;
+ + 	switch (burst_size) {
+ + 	case 1:
+ + 		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
+ + 		break;
+ + 	case 2:
+ + 		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
+ + 		break;
+ + 	case 4:
+ + 		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
+ + 		break;
+ + 	case 8:
+ + 		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
+ + 		break;
+ + 	case 16:
+ + 		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
+ + 		break;
+ + 	}
+ + 
+ + 	reg |= (fifo_th << 8);
+ + 
+ + 	lcdc_write(reg, LCD_DMA_CTRL_REG);
+ + }
+ + 
+ + void lcd_cfg_ac_bias(int period, int transitions_per_int)
+ + {
+ + 	u32 reg;
+ + 
+ + 	/* Set the AC Bias Period and Number of Transisitons per Interrupt */
+ + 	reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000;
+ + 	reg |= LCD_AC_BIAS_FREQUENCY(period) |
+ + 		LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
+ + 	lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
+ + }
+ + 
+ + void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
+ + 		int front_porch)
+ + {
+ + 	u32 reg;
+ + 	
+ + 	/* fill low bits */
+ + 	reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0x3ff;
+ + 	reg |= ((back_porch & 0xff) << 24)
+ + 	    | ((front_porch & 0xff) << 16)
+ + 	    | ((pulse_width & 0x3f) << 10);
+ + 	lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
+ + 
+ + 	/* fill high bits */
+ + 	reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0x07ffff00;
+ + 	reg |= (((back_porch & 0x300)>>8) << 4)
+ + 	    | (((front_porch & 0x300)>>8))
+ + 	    | (((pulse_width & 0x3C0)>>6) << 27);
+ + 	lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
+ + }
+ + 
+ + void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
+ + 		int front_porch)
+ + {
+ + 	u32 reg;
+ + 	reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff;
+ + 	reg |= ((back_porch & 0xff) << 24)
+ + 	    | ((front_porch & 0xff) << 16)
+ + 	    | ((pulse_width & 0x3f) << 10);
+ + 	lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
+ + }
+ + 
+ + void lcd_cfg_display(void)
+ + {
+ + 	u32 reg;
+ + 
+ + 	reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE |
+ + 						LCD_MONO_8BIT_MODE |
+ + 						LCD_MONOCHROME_MODE);
+ + 
+ + 	/* MONOCHROME *
+ + 	reg |= LCD_MONOCHROME_MODE; */
+ + 	/* COLOR_ACTIVE */
+ + 	reg |= LCD_TFT_MODE;
+ + 	/* COLOR_PASSIVE */
+ + 		
+ + 	/* enable additional interrupts here */
+ + 	//reg |= LCD_V1_UNDERFLOW_INT_ENA;
+ + 
+ + 	lcdc_write(reg, LCD_RASTER_CTRL_REG);
+ + 
+ + 	reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
+ + 
+ + 	if (g_lcdpanel->sync_ctrl)
+ + 		reg |= LCD_SYNC_CTRL;
+ + 	else
+ + 		reg &= ~LCD_SYNC_CTRL;
+ + 
+ + 	if (g_lcdpanel->sync_edge)
+ + 		reg |= LCD_SYNC_EDGE;
+ + 	else
+ + 		reg &= ~LCD_SYNC_EDGE;
+ + 
+ + 	if (g_lcdpanel->invert_line_clock)
+ + 		reg |= LCD_INVERT_LINE_CLOCK;
+ + 	else
+ + 		reg &= ~LCD_INVERT_LINE_CLOCK;
+ + 
+ + 	if (g_lcdpanel->invert_frm_clock)
+ + 		reg |= LCD_INVERT_FRAME_CLOCK;
+ + 	else
+ + 		reg &= ~LCD_INVERT_FRAME_CLOCK;
+ + 
+ + 	lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
+ + }
+ + 
+ + void lcd_cfg_frame_buffer(u32 width, u32 height, u32 raster_order)
+ + {
+ + 	u32 reg;
+ + 
+ + 	/* Set the Panel Width */
+ + 	/* Pixels per line = (PPL + 1)*16 */
+ + 	if (lcd_revision == LCD_VERSION_1) {
+ + 		/*
+ + 		 * 0x3F in bits 4..9 gives max horizontal resolution = 1024
+ + 		 * pixels.
+ + 		 */
+ + 		width &= 0x3f0;
+ + 	} else {
+ + 		/*
+ + 		 * 0x7F in bits 4..10 gives max horizontal resolution = 2048
+ + 		 * pixels.
+ + 		 */
+ + 		width &= 0x7f0;
+ + 	}
+ + 
+ + 	reg = lcdc_read(LCD_RASTER_TIMING_0_REG);
+ + 	reg &= 0xfffffc00;
+ + 	if (lcd_revision == LCD_VERSION_1) {
+ + 		reg |= ((width >> 4) - 1) << 4;
+ + 	} else {
+ + 		width = (width >> 4) - 1;
+ + 		reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
+ + 	}
+ + 	lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
+ + 
+ + 	/* Set the Panel Height */
+ + 	/* Set bits 9:0 of Lines Per Pixel */
+ + 	reg = lcdc_read(LCD_RASTER_TIMING_1_REG);
+ + 	reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
+ + 	lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
+ + 
+ + 	/* Set bit 10 of Lines Per Pixel */
+ + 	if (lcd_revision == LCD_VERSION_2) {
+ + 		reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
+ + 		reg |= ((height - 1) & 0x400) << 16;
+ + 		lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
+ + 	}
+ + 
+ + 	/* Set the Raster Order of the Frame Buffer */
+ + 	reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);
+ + 	if (raster_order)
+ + 		reg |= LCD_RASTER_ORDER;
+ + 	lcdc_write(reg, LCD_RASTER_CTRL_REG);
+ + }
+ + 
+ + 
+ + static void lcd_calc_clk_divider(unsigned int clk)
+ + {
+ + #if 1
+ + 
+ + /* try to get a good value by calculating the best PLL clock and divider */
+ + 	volatile int best_divider;
+ + 	volatile int output_clock;
+ + 	volatile int best_difference = 0xffffffff;
+ + 	volatile int i, div;
+ + 	volatile int difference;
+ + 	volatile int dpll_clock;
+ + 	volatile int dpll_divider;
+ + 	/* check to see if the exact divider or divider+1 will give a nearest value */
+ + 	/* The only way to get the precise clock is to alter DPLL clock */ 
+ + 	/* check the CM_DIV_M2_DPLL_DISP Register */
+ + 	int orig_rate = LCD_IN_CLK;
+ + 	volatile int found = 0;
+ + 	for(i=1; i<=1; i++)
+ + 	{
+ + 		dpll_clock = orig_rate/i;
+ + 		
+ + 		/* calculate upper difference; the clock obtained here will be faster than what is requested */
+ + 		div = dpll_clock / clk;
+ + 		if(div>1)
+ + 		{
+ + 			output_clock = dpll_clock / div;
+ + 			difference = output_clock - clk;
+ + 			if(output_clock - clk <= best_difference)
+ + 			{
+ + 				best_difference = difference;
+ + 				best_divider = div;
+ + 				dpll_divider = i;
+ + 				found = 1;
+ + 			}
+ + 		}
+ + 		if(div>0)
+ + 		{
+ + 			/* calculate lower difference; the clock obtained here will be slower than what is requested */
+ + 			output_clock = dpll_clock / (div+1);
+ + 			difference = clk - output_clock;
+ + 			if(clk - output_clock <= best_difference)
+ + 			{
+ + 				best_difference = difference;
+ + 				best_divider = div+1;
+ + 				dpll_divider = i;
+ + 				found = 1;
+ + 			}
+ + 		}
+ + 	}
+ + 	if(found)
+ + 	{
+ + 		div = best_divider;
+ + //		par->pxl_clk = best_output_clock;
+ + 	}
+ + 	else
+ + 	{
+ + 		div = orig_rate / clk;
+ + 	}
+ + 	//printf("****div=%d, dpll_divider=%d", div, dpll_divider);
+ + #else
+ + 	/* LCD controller used PLL0_sysclk2 */
+ + 	unsigned int lcd_clk, div;
+ + 	lcd_clk = LCD_IN_CLK;
+ + 
+ + 	div = lcd_clk / clk;
+ + #endif
+ + 	
+ + 	/* Configure the LCD clock divisor. */
+ + 	lcdc_write(LCD_CLK_DIVISOR(div) |
+ + 			(LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);
+ + 
+ + 	if (lcd_revision == LCD_VERSION_2)
+ + 		lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
+ + 				LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG);
+ + }
+ + 
+ + void da850_lcd_gpio_init(void)
+ + {
+ + #if defined(CONFIG_CKB_LCD_01) || defined(CONFIG_CKB_LCD_02)
+ + 	/* GPIO as output */
+ + 	void *reg = omap_gpio_bank[3].base + OMAP_GPIO_OE;
+ + 	__raw_writel((__raw_readl(reg) & ~((1<<GPIO_DISP_POWER)
+ + 								| (1<<GPIO_BACKLIGHT_POWER)
+ + 								| (1<<GPIO_TPS_BACKLIGHT)))	, reg);
+ + #endif	
+ + 	/* GPIO8[10] -> Donot use LCD_MCLK *
+ + 	ckb_gpio_bank[3]->dir &= ~(1<<10); */
+ + #if 0
+ + 	/* configure interrupt trigger */
+ + 	ckb_gpio_bank01->set_rising |= (1<<GPIO_DISP_POWER);
+ + 	ckb_gpio_bank01->set_falling |= (1<<GPIO_DISP_POWER);
+ + 	ckb_gpio_bank01->set_rising |= (1<<GPIO_BACKLIGHT_POWER);
+ + 	ckb_gpio_bank01->set_falling |= (1<<GPIO_BACKLIGHT_POWER);
+ + #endif
+ + }
+ + 
+ + void da850_backlight_power_ctrl(int val)
+ + {
+ + 	void *reg = omap_gpio_bank[3].base + OMAP_GPIO_DATAOUT;
+ + 	if(!val)
+ + 	{
+ + 		/* switch off */
+ + 		__raw_writel((__raw_readl(reg) & ~((1<<GPIO_BACKLIGHT_POWER)
+ + 										| (1<<GPIO_TPS_BACKLIGHT))), reg);
+ + 	}
+ + 	else
+ + 	{
+ + 		/* switch on */
+ + 		__raw_writel((__raw_readl(reg) | ((1<<GPIO_BACKLIGHT_POWER)
+ + 										| (1<<GPIO_TPS_BACKLIGHT))), reg);
+ + 	}
+ + }
+ + 
+ + void da850_panel_power_ctrl(int val)
+ + {
+ + #if defined(CONFIG_CKB_LCD_01) || defined(CONFIG_CKB_LCD_02)
+ + 	void *reg = omap_gpio_bank[3].base + OMAP_GPIO_DATAOUT;
+ + 	/* lcd power GPIO2[8] */
+ + 	if(!val)
+ + 		/* switch off */
+ + 		__raw_writel((__raw_readl(reg) & ~(1<<GPIO_DISP_POWER)), reg);
+ + 	else
+ + 		/* switch on */
+ + 		__raw_writel((__raw_readl(reg) | (1<<GPIO_DISP_POWER)), reg);
+ + #endif
+ + }
+ + 
+ + 
+ + #ifdef HALF_IMAGE
+ + void scaleImage_x_2(int image_width, int image_height, unsigned short *src_addr, unsigned short *dest_addr)
+ + {
+ + 	/* The image need to be scaled 2 times;
+ + 	   Write the same value to the adjascent pixel
+ + 	   Replicate the line */ 
+ + 	int i, j;
+ + 	for(i=0; i<image_height; i++)
+ + 	{
+ + #if 0
+ + 		int l;
+ + 		for(l=0; l<2; l++)			/* replicate the line again */
+ + 		{
+ + 			for(j=0; j<image_width; j++)
+ + 			{
+ + 				*dest_addr++ = *(src_addr+j);
+ + 				*dest_addr++ = *(src_addr+j);
+ + 			}
+ + 		}
+ + 		s_dest += j;
+ + #else
+ + 		for(j=0; j<image_width; j++)
+ + 		{
+ + 			/* fill 2 pixels and the next line */
+ + 			*dest_addr = *(dest_addr+1) = *(dest_addr+g_lcdpanel->width) = *(dest_addr+(g_lcdpanel->width+1)) = *(src_addr+j);
+ + 			dest_addr+=2;	/* increment pixels by 2 */		
+ + 		}
+ + 		src_addr += j;
+ + 		dest_addr+=g_lcdpanel->width; /* move to the line after the next line */
+ + #endif
+ + 	}
+ + }
+ + #endif
+ + 		
+ + int fill_logo_from_flash(unsigned long address, unsigned char *dest_addr)
+ + {
+ + 	int read_size;
+ + #ifdef HALF_IMAGE
+ + 	unsigned char *orig_dest = dest_addr;
+ + 	int half_width = g_lcdpanel->width/2;
+ + 	int half_height = g_lcdpanel->height/2;
+ + 	read_size = half_width*half_height*2;
+ + 	/* move to the end of the FB and use it as temp address */
+ + 	dest_addr = dest_addr+(g_lcdpanel->width*g_lcdpanel->height*2);
+ + #else
+ + 	read_size = g_lcdpanel->width*g_lcdpanel->height*2;
+ + #endif
+ + 	/* read image from NOR flash */
+ + 	char *temp_argv[4];
+ + 	char addr1[16], addr2[16], size[16];
+ + 	sprintf(addr1, "%X", address);
+ + 	sprintf(addr2, "%X", dest_addr);
+ + 	sprintf(size, "%X", read_size);
+ + 	temp_argv[0] = "cp.b";
+ + 	temp_argv[1] = addr1;				/* source flash address */
+ + 	temp_argv[2] = addr2;				/* destination address */
+ + 	temp_argv[3] = size;				/* count */
+ + 	
+ + 	displaying_ckb_logo = 1;
+ + 	/* set the start of the command table as the first paramater; 
+ + 	This is not OK, but since the parameters are valid, it's ok :-) */
+ + 	if(!do_mem_cp(&__u_boot_cmd_start, 0, 4, temp_argv))
+ + 	{
+ + #ifdef HALF_IMAGE
+ + 		scaleImage_x_2(half_width, half_height, dest_addr, orig_dest);
+ + #endif
+ + 	}
+ + 	displaying_ckb_logo = 0;
+ + 
+ + 	return 0;
+ + }
+ + 
+ + void init_lcd(void)
+ + {
+ + 	/* init display pll */
+ + 	disp_pll_config();
+ + 	/* initialize GPIO */
+ + 	da850_lcd_gpio_init();
+ + 
+ + 	/* Determine LCD IP Version */
+ + 	switch (lcdc_read(LCD_PID_REG)) {
+ + 	case 0x4C100102:
+ + 		lcd_revision = LCD_VERSION_1;
+ + 		//printf("LCD revision 1\n");
+ + 		break;
+ + 	case 0x4F200800:
+ + 	case 0x4F201000:
+ + 		lcd_revision = LCD_VERSION_2;
+ + 		//printf("LCD revision 2\n");
+ + 		break;
+ + 	default:
+ + 		printf("Unknown PID Reg value 0x%x, "
+ + 				"defaulting to LCD revision 1\n",
+ + 				lcdc_read(LCD_PID_REG));
+ + 		lcd_revision = LCD_VERSION_1;
+ + 		break;
+ + 	}
+ + 
+ + 	/* disable raster */
+ + 	lcd_disable_raster();
+ + 
+ + 	if(lcd_revision == LCD_VERSION_1)
+ + 	{
+ + 		/* set palette: For 16BPP, the 0th entry in the Palette should be 0x4000 and all other 
+ + 	   	   entries must be 0 */
+ + 		*(unsigned short *)FB_PALLET_ADDRESS = LCD_16_BPP_PALETTE;
+ + 		memset(FB_PALLET_ADDRESS+2, 0, FB_PALETTE_SIZE-2);
+ + 	}
+ + 	
+ + 
+ + 
+ + 	/* clear status register */
+ + 	//printf("Status=%X\n", lcdc_read(LCD_STAT_REG));
+ + 	lcdc_write(lcdc_read(LCD_STAT_REG), LCD_STAT_REG);
+ + 
+ +     /* init clock */
+ + 	lcd_calc_clk_divider(g_lcdpanel->pxl_clk);
+ + 	/* configure registers */
+ + 	/* timing */
+ + 	lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) &
+ + 			~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
+ + 	/* burst size */
+ + 	lcd_cfg_dma(g_lcdpanel->dma_burst_sz, g_lcdpanel->fifo_th);
+ + 	/* AC bias */
+ + 	lcd_cfg_ac_bias(g_lcdpanel->ac_bias, g_lcdpanel->ac_bias_intrpt);
+ + 	/* vertical and horizontal sync properties */
+ + 	lcd_cfg_vertical_sync(g_lcdpanel->vbp, g_lcdpanel->vsw, g_lcdpanel->vfp);
+ + 	lcd_cfg_horizontal_sync(g_lcdpanel->hbp, g_lcdpanel->hsw, g_lcdpanel->hfp);
+ + 	lcd_cfg_display();
+ + 	lcd_cfg_frame_buffer(g_lcdpanel->width, g_lcdpanel->height, 0);
+ + 	/* FIFO DMA delay */
+ + 	lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) |
+ + 		       (g_lcdpanel->fdd << 12), LCD_RASTER_CTRL_REG);
+ + 
+ + 	lcd_fb_addr();
+ + 
+ + 	/* enable raster */
+ + 	lcd_enable_raster();
+ + 
+ + 	/* Let the controller take it's own time to display the image */
+ + 	//while(!(lcdc_read(LCD_STAT_REG) & LCD_END_OF_FRAME0));
+ + 
+ + 	/* turn on LCD power */
+ + 	da850_panel_power_ctrl(1);
+ + }
+ + 
+ + void enable_backlight()
+ + {
+ + 	da850_backlight_power_ctrl(1);
+ + }
+ + 
+ + void init_lcd_and_display_logo()
+ + {
+ + 	/* LCD panel to use */
+ + #ifdef CONFIG_CKB_LCD_01
+ + 	g_lcdpanel = &VisionxKTM050AL02;
+ + #endif
+ + #ifdef CONFIG_CKB_LCD_02
+ + 	g_lcdpanel = &KyoceraTCG070WVLPAAFA_AA00;
+ + #endif
+ + #if !defined(CONFIG_CKB_LCD_01) && !defined(CONFIG_CKB_LCD_02)
+ + 	g_lcdpanel = &generic_DVI_monitor;
+ + #endif		
+ + 
+ + 	printf("LCD panel: %s\n", g_lcdpanel->name);
+ + 	printf("FB allocated @ 0x%X\n", CONFIG_FB_BASE_ADDRESS);
+ + 	gd->fb_base = CONFIG_FB_BASE_ADDRESS;
+ + 
+ + 	fill_logo_from_flash(LCD_IMAGE_ADDRESS, CONFIG_FB_BASE_ADDRESS);
+ + 	
+ + 	init_lcd();
+ + #if defined(CONFIG_CKB_LCD_01) || defined(CONFIG_CKB_LCD_02)
+ + 	enable_backlight();
+ + #endif
+ + #if defined(CONFIG_CKB_DVI)
+ + 	init_tfp410();
+ + #endif
+ + }
+ + #else
+ + void init_lcd_and_display_logo()
+ + {
+ + 	printf("LCD panel: None\n");
+ + }
+ + #endif
+ diff -crN u-boot-2012.10_o/board/computex/ckb-3352/Makefile u-boot-2012.10/board/computex/ckb-3352/Makefile
+ *** u-boot-2012.10_o/board/computex/ckb-3352/Makefile	1970-01-01 09:00:00.000000000 +0900
+ --- u-boot-2012.10/board/computex/ckb-3352/Makefile	2014-03-19 14:23:40.491830000 +0900
+ ***************
+ *** 0 ****
+ --- 1,43 ----
+ + #
+ + # Makefile
+ + #
+ + # Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
+ + #
+ + # This program is free software; you can redistribute it and/or
+ + # modify it under the terms of the GNU General Public License as
+ + # published by the Free Software Foundation; either version 2 of
+ + # the License, or (at your option) any later version.
+ + #
+ + # This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ + # kind, whether express or implied; without even the implied warranty
+ + # of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ + # GNU General Public License for more details.
+ + #
+ + 
+ + include $(TOPDIR)/config.mk
+ + 
+ + LIB	= $(obj)lib$(BOARD).o
+ + 
+ + COBJS	:= mux.o cmd_custom.o lcd.o tfp410.o
+ + 
+ + SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+ + OBJS	:= $(addprefix $(obj),$(COBJS))
+ + SOBJS	:= $(addprefix $(obj),$(SOBJS))
+ + 
+ + $(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+ + 	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+ + 
+ + clean:
+ + 	rm -f $(SOBJS) $(OBJS)
+ + 
+ + distclean:	clean
+ + 	rm -f $(LIB) core *.bak $(obj).depend
+ + 
+ + #########################################################################
+ + 
+ + # defines $(obj).depend target
+ + include $(SRCTREE)/rules.mk
+ + 
+ + sinclude $(obj).depend
+ + 
+ + #########################################################################
+ diff -crN u-boot-2012.10_o/board/computex/ckb-3352/mux.c u-boot-2012.10/board/computex/ckb-3352/mux.c
+ *** u-boot-2012.10_o/board/computex/ckb-3352/mux.c	1970-01-01 09:00:00.000000000 +0900
+ --- u-boot-2012.10/board/computex/ckb-3352/mux.c	2014-02-27 11:33:16.781140652 +0900
+ ***************
+ *** 0 ****
+ --- 1,418 ----
+ + /*
+ +  * mux.c
+ +  *
+ +  * Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #include <common.h>
+ + #include <asm/arch/sys_proto.h>
+ + #include <asm/arch/hardware.h>
+ + #include <asm/io.h>
+ + #include <i2c.h>
+ + 
+ + #define MUX_CFG(value, offset)	\
+ + 	__raw_writel(value, (CTRL_BASE + offset));
+ + 
+ + /* PAD Control Fields */
+ + #define SLEWCTRL	(0x1 << 6)
+ + #define RXACTIVE	(0x1 << 5)
+ + #define PULLUP_EN	(0x1 << 4) /* Pull UP Selection */
+ + #define PULLUDEN	(0x0 << 3) /* Pull up enabled */
+ + #define PULLUDDIS	(0x1 << 3) /* Pull up disabled */
+ + #define MODE(val)	val	/* used for Readability */
+ + 
+ + /*
+ +  * PAD CONTROL OFFSETS
+ +  * Field names corresponds to the pad signal name
+ +  */
+ + struct pad_signals {
+ + 	int gpmc_ad0;
+ + 	int gpmc_ad1;
+ + 	int gpmc_ad2;
+ + 	int gpmc_ad3;
+ + 	int gpmc_ad4;
+ + 	int gpmc_ad5;
+ + 	int gpmc_ad6;
+ + 	int gpmc_ad7;
+ + 	int gpmc_ad8;
+ + 	int gpmc_ad9;
+ + 	int gpmc_ad10;
+ + 	int gpmc_ad11;
+ + 	int gpmc_ad12;
+ + 	int gpmc_ad13;
+ + 	int gpmc_ad14;
+ + 	int gpmc_ad15;
+ + 	int gpmc_a0;
+ + 	int gpmc_a1;
+ + 	int gpmc_a2;
+ + 	int gpmc_a3;
+ + 	int gpmc_a4;
+ + 	int gpmc_a5;
+ + 	int gpmc_a6;
+ + 	int gpmc_a7;
+ + 	int gpmc_a8;
+ + 	int gpmc_a9;
+ + 	int gpmc_a10;
+ + 	int gpmc_a11;
+ + 	int gpmc_wait0;
+ + 	int gpmc_wpn;
+ + 	int gpmc_be1n;
+ + 	int gpmc_csn0;
+ + 	int gpmc_csn1;
+ + 	int gpmc_csn2;
+ + 	int gpmc_csn3;
+ + 	int gpmc_clk;
+ + 	int gpmc_advn_ale;
+ + 	int gpmc_oen_ren;
+ + 	int gpmc_wen;
+ + 	int gpmc_be0n_cle;
+ + 	int lcd_data0;
+ + 	int lcd_data1;
+ + 	int lcd_data2;
+ + 	int lcd_data3;
+ + 	int lcd_data4;
+ + 	int lcd_data5;
+ + 	int lcd_data6;
+ + 	int lcd_data7;
+ + 	int lcd_data8;
+ + 	int lcd_data9;
+ + 	int lcd_data10;
+ + 	int lcd_data11;
+ + 	int lcd_data12;
+ + 	int lcd_data13;
+ + 	int lcd_data14;
+ + 	int lcd_data15;
+ + 	int lcd_vsync;
+ + 	int lcd_hsync;
+ + 	int lcd_pclk;
+ + 	int lcd_ac_bias_en;
+ + 	int mmc0_dat3;
+ + 	int mmc0_dat2;
+ + 	int mmc0_dat1;
+ + 	int mmc0_dat0;
+ + 	int mmc0_clk;
+ + 	int mmc0_cmd;
+ + 	int mii1_col;
+ + 	int mii1_crs;
+ + 	int mii1_rxerr;
+ + 	int mii1_txen;
+ + 	int mii1_rxdv;
+ + 	int mii1_txd3;
+ + 	int mii1_txd2;
+ + 	int mii1_txd1;
+ + 	int mii1_txd0;
+ + 	int mii1_txclk;
+ + 	int mii1_rxclk;
+ + 	int mii1_rxd3;
+ + 	int mii1_rxd2;
+ + 	int mii1_rxd1;
+ + 	int mii1_rxd0;
+ + 	int rmii1_refclk;
+ + 	int mdio_data;
+ + 	int mdio_clk;
+ + 	int spi0_sclk;
+ + 	int spi0_d0;
+ + 	int spi0_d1;
+ + 	int spi0_cs0;
+ + 	int spi0_cs1;
+ + 	int ecap0_in_pwm0_out;
+ + 	int uart0_ctsn;
+ + 	int uart0_rtsn;
+ + 	int uart0_rxd;
+ + 	int uart0_txd;
+ + 	int uart1_ctsn;
+ + 	int uart1_rtsn;
+ + 	int uart1_rxd;
+ + 	int uart1_txd;
+ + 	int i2c0_sda;
+ + 	int i2c0_scl;
+ + 	int mcasp0_aclkx;
+ + 	int mcasp0_fsx;
+ + 	int mcasp0_axr0;
+ + 	int mcasp0_ahclkr;
+ + 	int mcasp0_aclkr;
+ + 	int mcasp0_fsr;
+ + 	int mcasp0_axr1;
+ + 	int mcasp0_ahclkx;
+ + 	int xdma_event_intr0;
+ + 	int xdma_event_intr1;
+ + 	int nresetin_out;
+ + 	int porz;
+ + 	int nnmi;
+ + 	int osc0_in;
+ + 	int osc0_out;
+ + 	int rsvd1;
+ + 	int tms;
+ + 	int tdi;
+ + 	int tdo;
+ + 	int tck;
+ + 	int ntrst;
+ + 	int emu0;
+ + 	int emu1;
+ + 	int osc1_in;
+ + 	int osc1_out;
+ + 	int pmic_power_en;
+ + 	int rtc_porz;
+ + 	int rsvd2;
+ + 	int ext_wakeup;
+ + 	int enz_kaldo_1p8v;
+ + 	int usb0_dm;
+ + 	int usb0_dp;
+ + 	int usb0_ce;
+ + 	int usb0_id;
+ + 	int usb0_vbus;
+ + 	int usb0_drvvbus;
+ + 	int usb1_dm;
+ + 	int usb1_dp;
+ + 	int usb1_ce;
+ + 	int usb1_id;
+ + 	int usb1_vbus;
+ + 	int usb1_drvvbus;
+ + 	int ddr_resetn;
+ + 	int ddr_csn0;
+ + 	int ddr_cke;
+ + 	int ddr_ck;
+ + 	int ddr_nck;
+ + 	int ddr_casn;
+ + 	int ddr_rasn;
+ + 	int ddr_wen;
+ + 	int ddr_ba0;
+ + 	int ddr_ba1;
+ + 	int ddr_ba2;
+ + 	int ddr_a0;
+ + 	int ddr_a1;
+ + 	int ddr_a2;
+ + 	int ddr_a3;
+ + 	int ddr_a4;
+ + 	int ddr_a5;
+ + 	int ddr_a6;
+ + 	int ddr_a7;
+ + 	int ddr_a8;
+ + 	int ddr_a9;
+ + 	int ddr_a10;
+ + 	int ddr_a11;
+ + 	int ddr_a12;
+ + 	int ddr_a13;
+ + 	int ddr_a14;
+ + 	int ddr_a15;
+ + 	int ddr_odt;
+ + 	int ddr_d0;
+ + 	int ddr_d1;
+ + 	int ddr_d2;
+ + 	int ddr_d3;
+ + 	int ddr_d4;
+ + 	int ddr_d5;
+ + 	int ddr_d6;
+ + 	int ddr_d7;
+ + 	int ddr_d8;
+ + 	int ddr_d9;
+ + 	int ddr_d10;
+ + 	int ddr_d11;
+ + 	int ddr_d12;
+ + 	int ddr_d13;
+ + 	int ddr_d14;
+ + 	int ddr_d15;
+ + 	int ddr_dqm0;
+ + 	int ddr_dqm1;
+ + 	int ddr_dqs0;
+ + 	int ddr_dqsn0;
+ + 	int ddr_dqs1;
+ + 	int ddr_dqsn1;
+ + 	int ddr_vref;
+ + 	int ddr_vtp;
+ + 	int ddr_strben0;
+ + 	int ddr_strben1;
+ + 	int ain7;
+ + 	int ain6;
+ + 	int ain5;
+ + 	int ain4;
+ + 	int ain3;
+ + 	int ain2;
+ + 	int ain1;
+ + 	int ain0;
+ + 	int vrefp;
+ + 	int vrefn;
+ + };
+ + 
+ + struct module_pin_mux {
+ + 	short reg_offset;
+ + 	unsigned char val;
+ + };
+ + 
+ + /* Pad control register offset */
+ + #define PAD_CTRL_BASE	0x800
+ + #define OFFSET(x)	(unsigned int) (&((struct pad_signals *) \
+ + 				(PAD_CTRL_BASE))->x)
+ + 
+ + #if 0
+ + static struct module_pin_mux uart0_pin_mux[] = {
+ + 	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_RXD */
+ + 	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},		/* UART0_TXD */
+ + 	{-1},
+ + };
+ + #endif
+ + 
+ + static struct module_pin_mux mmc0_pin_mux[] = {
+ + 	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
+ + 	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
+ + 	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
+ + 	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
+ + 	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
+ + 	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
+ + 	//{OFFSET(spi0_cs1), (MODE(7) | RXACTIVE | PULLUP_EN)},	/* MMC0_CD */
+ + 	{-1},
+ + };
+ + 
+ + #if 0
+ + static struct module_pin_mux i2c0_pin_mux[] = {
+ + 	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+ + 			PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
+ + 	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+ + 			PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
+ + 	{-1},
+ + };
+ + 
+ + static struct module_pin_mux i2c1_pin_mux[] = {
+ + 	{OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
+ + 			PULLUDEN | SLEWCTRL)},	/* I2C_DATA */
+ + 	{OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
+ + 			PULLUDEN | SLEWCTRL)},	/* I2C_SCLK */
+ + 	{-1},
+ + };
+ + 
+ + static struct module_pin_mux rgmii1_pin_mux[] = {
+ + 	{OFFSET(mii1_txen), MODE(2)},			/* RGMII1_TCTL */
+ + 	{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE},	/* RGMII1_RCTL */
+ + 	{OFFSET(mii1_txd3), MODE(2)},			/* RGMII1_TD3 */
+ + 	{OFFSET(mii1_txd2), MODE(2)},			/* RGMII1_TD2 */
+ + 	{OFFSET(mii1_txd1), MODE(2)},			/* RGMII1_TD1 */
+ + 	{OFFSET(mii1_txd0), MODE(2)},			/* RGMII1_TD0 */
+ + 	{OFFSET(mii1_txclk), MODE(2)},			/* RGMII1_TCLK */
+ + 	{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE},	/* RGMII1_RCLK */
+ + 	{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE},	/* RGMII1_RD3 */
+ + 	{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE},	/* RGMII1_RD2 */
+ + 	{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE},	/* RGMII1_RD1 */
+ + 	{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE},	/* RGMII1_RD0 */
+ + 	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+ + 	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+ + 	{-1},
+ + };
+ + #endif
+ + static struct module_pin_mux lcd_pin_mux[] = {
+ + 	{OFFSET(lcd_data0), MODE(0) | PULLUDDIS | SLEWCTRL},
+ + 	{OFFSET(lcd_data1), MODE(0) | PULLUDDIS | SLEWCTRL},
+ + 	{OFFSET(lcd_data2), MODE(0) | PULLUDDIS | SLEWCTRL},
+ + 	{OFFSET(lcd_data3), MODE(0) | PULLUDDIS | SLEWCTRL},
+ + 	{OFFSET(lcd_data4), MODE(0) | PULLUDDIS | SLEWCTRL},
+ + 	{OFFSET(lcd_data5), MODE(0) | PULLUDDIS | SLEWCTRL},
+ + 	{OFFSET(lcd_data6), MODE(0) | PULLUDDIS | SLEWCTRL},
+ + 	{OFFSET(lcd_data7), MODE(0) | PULLUDDIS | SLEWCTRL},
+ + 	{OFFSET(lcd_data8), MODE(0) | PULLUDDIS | SLEWCTRL},
+ + 	{OFFSET(lcd_data9), MODE(0) | PULLUDDIS | SLEWCTRL},
+ + 	{OFFSET(lcd_data10), MODE(0) | PULLUDDIS | SLEWCTRL},
+ + 	{OFFSET(lcd_data11), MODE(0) | PULLUDDIS | SLEWCTRL},
+ + 	{OFFSET(lcd_data12), MODE(0) | PULLUDDIS | SLEWCTRL},
+ + 	{OFFSET(lcd_data13), MODE(0) | PULLUDDIS | SLEWCTRL},
+ + 	{OFFSET(lcd_data14), MODE(0) | PULLUDDIS | SLEWCTRL},
+ + 	{OFFSET(lcd_data15), MODE(0) | PULLUDDIS | SLEWCTRL},
+ + 	{OFFSET(lcd_vsync), MODE(0) | SLEWCTRL},
+ + 	{OFFSET(lcd_hsync), MODE(0) | SLEWCTRL},
+ + 	{OFFSET(lcd_pclk), MODE(0) | SLEWCTRL},
+ + 	{OFFSET(lcd_ac_bias_en), MODE(0) | SLEWCTRL},
+ + 	
+ + 	{-1},
+ + };
+ + 
+ + static struct module_pin_mux lcdpwr_pin_mux[] = {
+ + 	{OFFSET(emu0), MODE(7) | PULLUP_EN},		/* LCDC Pwr pin */
+ + 	{OFFSET(emu1), MODE(7) | PULLUP_EN},		/* Backlight pin */
+ + 	{OFFSET(mcasp0_fsr), MODE(7) | PULLUP_EN},	/* TPS pin */
+ + 	{-1},
+ + };
+ + 
+ + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
+ + struct module_pin_mux nor_flash_pins[] = {
+ + 	{OFFSET(gpmc_ad0), MODE(0) | PULLUDEN | RXACTIVE},	/* NOR_AD0 */
+ + 	{OFFSET(gpmc_ad1), MODE(0) | PULLUDEN | RXACTIVE},	/* NOR_AD1 */
+ + 	{OFFSET(gpmc_ad2), MODE(0) | PULLUDEN | RXACTIVE},	/* NOR_AD2 */
+ + 	{OFFSET(gpmc_ad3), MODE(0) | PULLUDEN | RXACTIVE},	/* NOR_AD3 */
+ + 	{OFFSET(gpmc_ad4), MODE(0) | PULLUDEN | RXACTIVE},	/* NOR_AD4 */
+ + 	{OFFSET(gpmc_ad5), MODE(0) | PULLUDEN | RXACTIVE},	/* NOR_AD5 */
+ + 	{OFFSET(gpmc_ad6), MODE(0) | PULLUDEN | RXACTIVE},	/* NOR_AD6 */
+ + 	{OFFSET(gpmc_ad7), MODE(0) | PULLUDEN | RXACTIVE},	/* NOR_AD7 */
+ + 	{OFFSET(gpmc_ad8), MODE(0) | PULLUDEN | RXACTIVE},	/* NOR_AD8 */
+ + 	{OFFSET(gpmc_ad9), MODE(0) | PULLUDEN | RXACTIVE},	/* NOR_AD9 */
+ + 	{OFFSET(gpmc_ad10), MODE(0) | PULLUDEN | RXACTIVE},	/* NOR_AD10 */
+ + 	{OFFSET(gpmc_ad11), MODE(0) | PULLUDEN | RXACTIVE},	/* NOR_AD11 */
+ + 	{OFFSET(gpmc_ad12), MODE(0) | PULLUDEN | RXACTIVE},	/* NOR_AD12 */
+ + 	{OFFSET(gpmc_ad13), MODE(0) | PULLUDEN | RXACTIVE},	/* NOR_AD13 */
+ + 	{OFFSET(gpmc_ad14), MODE(0) | PULLUDEN | RXACTIVE},	/* NOR_AD14 */
+ + 	{OFFSET(gpmc_ad15), MODE(0) | PULLUDEN | RXACTIVE},	/* NOR_AD15 */
+ + 
+ + 	{OFFSET(gpmc_csn0), MODE(0) | PULLUDDIS},			/* NOR_CE */
+ + 	{OFFSET(gpmc_advn_ale), MODE(0) | PULLUDDIS}, 		/* NOR_ADVN_ALE */
+ + 	{OFFSET(gpmc_oen_ren), MODE(0) | PULLUDDIS},		/* NOR_OE */
+ + 	{OFFSET(gpmc_wen), MODE(0) | PULLUDDIS},			/* NOR_WEN */
+ + 	{-1},
+ + };
+ + 	
+ + struct module_pin_mux nor_flash_gpio_pins[] = {
+ + 	/* GPIOs for selecting banks */
+ + 	{OFFSET(gpmc_a4), (MODE(7) | PULLUDDIS)},	/* GP1_20 */
+ + 	{OFFSET(gpmc_a5), (MODE(7) | PULLUDDIS)},	/* GP1_21 */
+ + 	{OFFSET(gpmc_a6), (MODE(7) | PULLUDDIS)},	/* GP1_22 */
+ + 	{OFFSET(gpmc_a7), (MODE(7) | PULLUDDIS)},	/* GP1_23 */
+ + 	{OFFSET(gpmc_a8), (MODE(7) | PULLUDDIS)},	/* GP1_24 */
+ + 	{OFFSET(gpmc_a9), (MODE(7) | PULLUDDIS)},	/* GP1_25 */
+ + 	{OFFSET(gpmc_a10), (MODE(7) | PULLUDDIS)},	/* GP1_26 */
+ + 	{-1},
+ + };
+ + #endif
+ + 
+ + /*
+ +  * Configure the pin mux for the module
+ +  */
+ + static void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux)
+ + {
+ + 	int i;
+ + 
+ + 	if (!mod_pin_mux)
+ + 		return;
+ + 
+ + 	for (i = 0; mod_pin_mux[i].reg_offset != -1; i++)
+ + 		MUX_CFG(mod_pin_mux[i].val, mod_pin_mux[i].reg_offset);
+ + }
+ + #if 0
+ + void enable_uart0_pin_mux(void)
+ + {
+ + 	configure_module_pin_mux(uart0_pin_mux);
+ + }
+ + 
+ + 
+ + void enable_i2c0_pin_mux(void)
+ + {
+ + 	configure_module_pin_mux(i2c0_pin_mux);
+ + }
+ + #endif
+ + void enable_board_pin_mux()
+ + {
+ + 	configure_module_pin_mux(lcd_pin_mux);
+ + 	configure_module_pin_mux(lcdpwr_pin_mux);
+ + 	
+ + #if defined(CONFIG_OMAP_HSMMC)
+ + 	configure_module_pin_mux(mmc0_pin_mux);
+ + #endif
+ + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
+ + 	configure_module_pin_mux(nor_flash_pins);
+ + 	configure_module_pin_mux(nor_flash_gpio_pins);
+ + #endif
+ + }
+ diff -crN u-boot-2012.10_o/board/computex/ckb-3352/tfp410.c u-boot-2012.10/board/computex/ckb-3352/tfp410.c
+ *** u-boot-2012.10_o/board/computex/ckb-3352/tfp410.c	1970-01-01 09:00:00.000000000 +0900
+ --- u-boot-2012.10/board/computex/ckb-3352/tfp410.c	2014-03-19 14:41:08.048747000 +0900
+ ***************
+ *** 0 ****
+ --- 1,211 ----
+ + /*
+ +  * TFP410 basic functions, uses the I2c interface
+ +  *
+ +  * Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
+ +  *
+ +  * This program is free software; you can redistribute it and/or modify
+ +  * it under the terms of the GNU General Public License as published by
+ +  * the Free Software Foundation; either version 2 of the License, or
+ +  * (at your option) any later version.
+ +  *
+ +  * This program is distributed in the hope that it will be useful,
+ +  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ +  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  *
+ +  * You should have received a copy of the GNU General Public License
+ +  * along with this program; if not, write to the Free Software
+ +  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ +  */
+ + #include <asm/arch/cpu.h>
+ + #include <asm/arch/hardware.h>
+ + #include <asm/arch/omap.h>
+ + #include <asm/arch/ddr_defs.h>
+ + #include <asm/arch/clock.h>
+ + #include <asm/arch/gpio.h>
+ + #include <asm/arch/mem.h>
+ + #include <asm/arch/mmc_host_def.h>
+ + #include <asm/arch/sys_proto.h>
+ + #include <asm/io.h>
+ + #include <asm/emif.h>
+ + #include <asm/gpio.h>
+ + #include <common.h>
+ + #include <asm/omap_gpio.h>
+ + 
+ + #if defined(CONFIG_CKB_DVI)
+ + 
+ + #define TFP410_I2C_ADDR				0x38
+ + /* register definitions according to the TFP410 data sheet */
+ + #define TFP410_VID		0x014C
+ + #define TFP410_DID		0x0410
+ + 
+ + #define TFP410_VID_LO		0x00
+ + #define TFP410_VID_HI		0x01
+ + #define TFP410_DID_LO		0x02
+ + #define TFP410_DID_HI		0x03
+ + #define TFP410_REV		0x04
+ + 
+ + #define TFP410_CTL_1		0x08
+ + #define TFP410_CTL_1_TDIS	(1<<6)
+ + #define TFP410_CTL_1_VEN	(1<<5)
+ + #define TFP410_CTL_1_HEN	(1<<4)
+ + #define TFP410_CTL_1_DSEL	(1<<3)
+ + #define TFP410_CTL_1_BSEL	(1<<2)
+ + #define TFP410_CTL_1_EDGE	(1<<1)
+ + #define TFP410_CTL_1_PD		(1<<0)
+ + 
+ + #define TFP410_CTL_2		0x09
+ + #define TFP410_CTL_2_VLOW	(1<<7)
+ + #define TFP410_CTL_2_MSEL_MASK	(0x7<<4)
+ + #define TFP410_CTL_2_MSEL	(1<<4)
+ + #define TFP410_CTL_2_TSEL	(1<<3)
+ + #define TFP410_CTL_2_RSEN	(1<<2)
+ + #define TFP410_CTL_2_HTPLG	(1<<1)
+ + #define TFP410_CTL_2_MDI	(1<<0)
+ + 
+ + #define TFP410_CTL_3		0x0A
+ + #define TFP410_CTL_3_DK_MASK	(0x7<<5)
+ + #define TFP410_CTL_3_DK		(1<<5)
+ + #define TFP410_CTL_3_DKEN	(1<<4)
+ + #define TFP410_CTL_3_CTL_MASK	(0x7<<1)
+ + #define TFP410_CTL_3_CTL	(1<<1)
+ + 
+ + #define TFP410_USERCFG		0x0B
+ + 
+ + #define TFP410_DE_DLY		0x32
+ + 
+ + #define TFP410_DE_CTL		0x33
+ + #define TFP410_DE_CTL_DEGEN	(1<<6)
+ + #define TFP410_DE_CTL_VSPOL	(1<<5)
+ + #define TFP410_DE_CTL_HSPOL	(1<<4)
+ + #define TFP410_DE_CTL_DEDLY8	(1<<0)
+ + 
+ + #define TFP410_DE_TOP		0x34
+ + 
+ + #define TFP410_DE_CNT_LO	0x36
+ + #define TFP410_DE_CNT_HI	0x37
+ + 
+ + #define TFP410_DE_LIN_LO	0x38
+ + #define TFP410_DE_LIN_HI	0x39
+ + 
+ + #define TFP410_H_RES_LO		0x3A
+ + #define TFP410_H_RES_HI		0x3B
+ + 
+ + #define TFP410_V_RES_LO		0x3C
+ + #define TFP410_V_RES_HI		0x3D
+ + 	
+ + static int tfp410_readb(uint addr, uchar *ch)
+ + {
+ + 	if(i2c_read(TFP410_I2C_ADDR, addr, 1, ch, 1))
+ + 	{
+ + 		printf("TFP410 read failed\n");
+ + 		return -1;
+ + 	}
+ + 	return 0;
+ + }
+ + 
+ + static int tfp410_writeb(uint addr, uchar ch)
+ + {
+ + 	if(i2c_write(TFP410_I2C_ADDR, addr, 1, &ch, 1))
+ + 	{
+ + 		printf("TFP410 write failed\n");
+ + 		return -1;
+ + 	}
+ + 	return 0;
+ + }
+ + 
+ + 
+ + /* set the tfp410 power state */
+ + static void tfp410_poweron()
+ + {
+ + 	uchar ctl1;
+ + 
+ + 	if (tfp410_readb(TFP410_CTL_1, &ctl1))
+ + 		return;
+ + 
+ + 	ctl1 |= TFP410_CTL_1_PD;
+ + 	
+ + 	tfp410_writeb(TFP410_CTL_1, ctl1);
+ + 	
+ + 	if (tfp410_readb(TFP410_CTL_2, &ctl1))
+ + 		return;
+ + 	tfp410_writeb(TFP410_CTL_2, (ctl1 & ~TFP410_CTL_2_MSEL_MASK) | (1 << 4) );
+ + }
+ + 
+ + 
+ + static int tfp410_getid(uint addr)
+ + {
+ + 	uchar ch[2];
+ + 
+ + 	if(i2c_read(TFP410_I2C_ADDR, addr, 1, &ch, 2))
+ + 	{
+ + 		printf("TFP410 ID read failed\n");
+ + 		return -1;
+ + 	}
+ + 	return ((ch[1] << 8) & 0xFF00) | (ch[0] & 0x00FF);
+ + }
+ + 
+ + #if 0
+ + static void tfp410_dump_regs()
+ + {
+ + 	uint8_t val, val2;
+ + 
+ + 	tfp410_readb(TFP410_REV, &val);
+ + 	printf("TFP410_REV: 0x%02X\n", val);
+ + 	tfp410_readb(TFP410_CTL_1, &val);
+ + 	printf("TFP410_CTL1: 0x%02X\n", val);
+ + 	tfp410_readb(TFP410_CTL_2, &val);
+ + 	printf("TFP410_CTL2: 0x%02X\n", val);
+ + 	tfp410_readb(TFP410_CTL_3, &val);
+ + 	printf("TFP410_CTL3: 0x%02X\n", val);
+ + 	tfp410_readb(TFP410_USERCFG, &val);
+ + 	printf("TFP410_USERCFG: 0x%02X\n", val);
+ + 	tfp410_readb(TFP410_DE_DLY, &val);
+ + 	printf("TFP410_DE_DLY: 0x%02X\n", val);
+ + 	tfp410_readb(TFP410_DE_CTL, &val);
+ + 	printf("TFP410_DE_CTL: 0x%02X\n", val);
+ + 	tfp410_readb(TFP410_DE_TOP, &val);
+ + 	printf("TFP410_DE_TOP: 0x%02X\n", val);
+ + 	tfp410_readb(TFP410_DE_CNT_LO, &val);
+ + 	tfp410_readb(TFP410_DE_CNT_HI, &val2);
+ + 	printf("TFP410_DE_CNT: 0x%02X%02X\n", val2, val);
+ + 	tfp410_readb(TFP410_DE_LIN_LO, &val);
+ + 	tfp410_readb(TFP410_DE_LIN_HI, &val2);
+ + 	printf("TFP410_DE_LIN: 0x%02X%02X\n", val2, val);
+ + 	tfp410_readb(TFP410_H_RES_LO, &val);
+ + 	tfp410_readb(TFP410_H_RES_HI, &val2);
+ + 	printf("TFP410_H_RES: 0x%02X%02X\n", val2, val);
+ + 	tfp410_readb(TFP410_V_RES_LO, &val);
+ + 	tfp410_readb(TFP410_V_RES_HI, &val2);
+ + 	printf("TFP410_V_RES: 0x%02X%02X\n", val2, val);
+ + }
+ + #endif
+ + 
+ + int init_tfp410()
+ + {
+ + 	int id;
+ + 	uchar ctl3;
+ + 	tfp410_poweron(1);
+ + 	/* Get ID  */
+ + 	if ((id = tfp410_getid(TFP410_VID_LO)) != TFP410_VID) {
+ + 		printf("TFP410 not detected got VID %X\n", id);
+ + 		return 1;
+ + 	}
+ + 
+ + 	if ((id = tfp410_getid(TFP410_DID_LO)) != TFP410_DID) {
+ + 		printf("TFP410 not detected got DID %X\n", id);
+ + 		return 1;
+ + 	}
+ + 	//tfp410_dump_regs();
+ + 	/* enable skew */
+ + 	if(tfp410_readb(TFP410_CTL_3, &ctl3)
+ + 		|| tfp410_writeb(TFP410_CTL_3, 
+ + 				ctl3 | TFP410_CTL_3_DKEN | (0x7<<5))
+ + 		|| tfp410_readb(TFP410_CTL_1, &ctl3)
+ + 		|| tfp410_writeb(TFP410_CTL_1, 
+ + 				(ctl3 & ~(TFP410_CTL_1_DSEL)) | TFP410_CTL_1_EDGE | TFP410_CTL_1_BSEL))
+ + 		return 1;
+ + 	//tfp410_dump_regs();
+ + 	return 0;
+ + }
+ + #endif
+ diff -crN u-boot-2012.10_o/boards.cfg u-boot-2012.10/boards.cfg
+ *** u-boot-2012.10_o/boards.cfg	2012-10-16 00:14:08.000000000 +0900
+ --- u-boot-2012.10/boards.cfg	2014-03-07 11:28:15.982294000 +0900
+ ***************
+ *** 226,231 ****
+ --- 226,232 ----
+   integratorcp_cm946es         arm         arm946es    integrator          armltd         -               integratorcp:CM946ES
+   ca9x4_ct_vxp                 arm         armv7       vexpress            armltd
+   am335x_evm                   arm         armv7       am335x              ti             am33xx
+ + ckb-3352                     arm         armv7       ckb-3352            computex       ckb_3352      ckb_3352
+   highbank                     arm         armv7       highbank            -              highbank
+   mx51_efikamx                 arm         armv7       mx51_efikamx        genesi         mx5		mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg
+   mx51_efikasb                 arm         armv7       mx51_efikamx        genesi         mx5		mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg
+ diff -crN u-boot-2012.10_o/common/cmd_flash.c u-boot-2012.10/common/cmd_flash.c
+ *** u-boot-2012.10_o/common/cmd_flash.c	2012-10-16 00:14:08.000000000 +0900
+ --- u-boot-2012.10/common/cmd_flash.c	2014-02-27 11:33:16.781140652 +0900
+ ***************
+ *** 302,309 ****
+   #ifndef CONFIG_SYS_NO_FLASH
+   	if (argc == 1) {	/* print info for all FLASH banks */
+   		for (bank=0; bank <CONFIG_SYS_MAX_FLASH_BANKS; ++bank) {
+   			printf ("\nBank # %ld: ", bank+1);
+ ! 
+   			flash_print_info (&flash_info[bank]);
+   		}
+   		return 0;
+ --- 302,312 ----
+   #ifndef CONFIG_SYS_NO_FLASH
+   	if (argc == 1) {	/* print info for all FLASH banks */
+   		for (bank=0; bank <CONFIG_SYS_MAX_FLASH_BANKS; ++bank) {
+ + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
+ + 			printf ("\nFlash information: ");
+ + #else
+   			printf ("\nBank # %ld: ", bank+1);
+ ! #endif
+   			flash_print_info (&flash_info[bank]);
+   		}
+   		return 0;
+ ***************
+ *** 339,345 ****
+ --- 342,352 ----
+   
+   	if (strcmp(argv[1], "all") == 0) {
+   		for (bank=1; bank<=CONFIG_SYS_MAX_FLASH_BANKS; ++bank) {
+ + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
+ + 			printf ("Erasing entire flash Banks ");
+ + #else
+   			printf ("Erase Flash Bank # %ld ", bank);
+ + #endif
+   			info = &flash_info[bank-1];
+   			rcode = flash_erase (info, 0, info->sector_count-1);
+   		}
+ ***************
+ *** 695,706 ****
+ --- 702,720 ----
+   #endif
+   
+   U_BOOT_CMD(
+ + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
+ + 	flinfo,    1,    1,    do_flinfo,
+ + #else
+   	flinfo,    2,    1,    do_flinfo,
+ + #endif
+   	"print FLASH memory information",
+   	"\n    - print information for all FLASH memory banks\n"
+ + #ifndef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
+   	"flinfo N\n    - print information for FLASH memory bank # N"
+ + #endif
+   );
+   
+ + #ifndef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
+   U_BOOT_CMD(
+   	erase,   3,   0,  do_flerase,
+   	"erase FLASH memory",
+ ***************
+ *** 739,744 ****
+ --- 753,759 ----
+   	TMP_PROT_OFF
+   	"protect off all\n    - make all FLASH banks writable"
+   );
+ + #endif
+   
+   #undef	TMP_ERASE
+   #undef	TMP_PROT_ON
+ diff -crN u-boot-2012.10_o/common/cmd_mem.c u-boot-2012.10/common/cmd_mem.c
+ *** u-boot-2012.10_o/common/cmd_mem.c	2012-10-16 00:14:08.000000000 +0900
+ --- u-boot-2012.10/common/cmd_mem.c	2014-03-07 11:21:58.577708000 +0900
+ ***************
+ *** 45,50 ****
+ --- 45,54 ----
+   
+   static	ulong	base_address = 0;
+   
+ + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
+ + extern char displaying_ckb_logo;
+ + #endif
+ + 
+   /* Memory Display
+    *
+    * Syntax:
+ ***************
+ *** 155,161 ****
+   {
+   	return mod_mem (cmdtp, 0, flag, argc, argv);
+   }
+ ! 
+   int do_mem_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+   {
+   	ulong	addr, writeval, count;
+ --- 159,165 ----
+   {
+   	return mod_mem (cmdtp, 0, flag, argc, argv);
+   }
+ ! #ifndef CONFIG_MACH_CKB_3352
+   int do_mem_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+   {
+   	ulong	addr, writeval, count;
+ ***************
+ *** 196,202 ****
+   	}
+   	return 0;
+   }
+ ! 
+   #ifdef CONFIG_MX_CYCLIC
+   int do_mem_mdc ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+   {
+ --- 200,206 ----
+   	}
+   	return 0;
+   }
+ ! #endif
+   #ifdef CONFIG_MX_CYCLIC
+   int do_mem_mdc ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+   {
+ ***************
+ *** 252,258 ****
+   	return 0;
+   }
+   #endif /* CONFIG_MX_CYCLIC */
+ ! 
+   int do_mem_cmp (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+   {
+   	ulong	addr1, addr2, count, ngood;
+ --- 256,262 ----
+   	return 0;
+   }
+   #endif /* CONFIG_MX_CYCLIC */
+ ! #ifndef CONFIG_MACH_CKB_3352
+   int do_mem_cmp (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+   {
+   	ulong	addr1, addr2, count, ngood;
+ ***************
+ *** 322,332 ****
+   	printf("Total of %ld %s(s) were the same\n", ngood, type);
+   	return rcode;
+   }
+ ! 
+   int do_mem_cp ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+   {
+   	ulong	addr, dest, count;
+   	int	size;
+   
+   	if (argc != 4)
+   		return CMD_RET_USAGE;
+ --- 326,339 ----
+   	printf("Total of %ld %s(s) were the same\n", ngood, type);
+   	return rcode;
+   }
+ ! #endif
+   int do_mem_cp ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+   {
+   	ulong	addr, dest, count;
+   	int	size;
+ + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
+ + 	ulong	*s, *d;
+ + #endif
+   
+   	if (argc != 4)
+   		return CMD_RET_USAGE;
+ ***************
+ *** 349,354 ****
+ --- 356,411 ----
+   		return 1;
+   	}
+   
+ + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
+ + 	/* check if both source and destination addresses are in flash */
+ + 	if (addr2info(addr) && addr2info(dest)){
+ + 		puts ("Unsupported combination of source/destination.\n\r");
+ + 		return 1;
+ + 	}
+ + 	/* check if source address is in flash */
+ + 	if ( addr2info(addr) != NULL){
+ + 		if(!displaying_ckb_logo) {
+ + 			puts ("Copying from Flash... ");
+ + 		}
+ + 		while (count > 0) {
+ + 			if( (32<=count) && (get_ckb_3352_flash_bank(addr) == get_ckb_3352_flash_bank(addr+32-1)) ) {
+ + 				s = (ulong *)set_ckb_3352_flash_bank(addr);
+ + 				d = (ulong *)dest;
+ + 				*d++ = *s++;
+ + 				*d++ = *s++;
+ + 				*d++ = *s++;
+ + 				*d++ = *s++;
+ + 				*d++ = *s++;
+ + 				*d++ = *s++;
+ + 				*d++ = *s++;
+ + 				*d++ = *s++;
+ + 				addr += 32;
+ + 				dest += 32;
+ + 				count -= 32;
+ + 			} else {
+ + 				if (size == 4) {
+ + 					*((ulong  *)dest) = *((ulong  *)set_ckb_3352_flash_bank(addr));
+ + 				} else if (size == 2) {
+ + 					*((ushort *)dest) = *((ushort *)set_ckb_3352_flash_bank(addr));
+ + 				} else {
+ + 					*((u_char *)dest) = *((u_char *)set_ckb_3352_flash_bank(addr));
+ + 				}
+ + 				addr += size;
+ + 				dest += size;
+ + 				count++;
+ + 			}
+ + 			/* reset watchdog from time to time */
+ + 			if ((count % (64 << 10)) == 0) {
+ + 				WATCHDOG_RESET();
+ + 			}
+ + 		}
+ + 		if(!displaying_ckb_logo) {
+ + 			puts ("done\n");
+ + 		}
+ + 		return 0;
+ + 	}
+ + #endif
+ + 
+   #ifndef CONFIG_SYS_NO_FLASH
+   	/* check if we are copying to Flash */
+   	if ( (addr2info(dest) != NULL)
+ ***************
+ *** 445,451 ****
+   	printf("Base Address: 0x%08lx\n", base_address);
+   	return 0;
+   }
+ ! 
+   int do_mem_loop (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+   {
+   	ulong	addr, length, i;
+ --- 502,508 ----
+   	printf("Base Address: 0x%08lx\n", base_address);
+   	return 0;
+   }
+ ! #ifndef CONFIG_MACH_CKB_3352
+   int do_mem_loop (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+   {
+   	ulong	addr, length, i;
+ ***************
+ *** 513,519 ****
+   			*cp++;
+   	}
+   }
+ ! 
+   #ifdef CONFIG_LOOPW
+   int do_mem_loopw (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+   {
+ --- 570,576 ----
+   			*cp++;
+   	}
+   }
+ ! #endif
+   #ifdef CONFIG_LOOPW
+   int do_mem_loopw (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+   {
+ ***************
+ *** 586,592 ****
+   	}
+   }
+   #endif /* CONFIG_LOOPW */
+ ! 
+   /*
+    * Perform a memory test. A more complete alternative test can be
+    * configured using CONFIG_SYS_ALT_MEMTEST. The complete test loops until
+ --- 643,649 ----
+   	}
+   }
+   #endif /* CONFIG_LOOPW */
+ ! #ifndef CONFIG_MACH_CKB_3352
+   /*
+    * Perform a memory test. A more complete alternative test can be
+    * configured using CONFIG_SYS_ALT_MEMTEST. The complete test loops until
+ ***************
+ *** 941,947 ****
+   #endif
+   	return 0;	/* not reached */
+   }
+ ! 
+   
+   /* Modify memory.
+    *
+ --- 998,1004 ----
+   #endif
+   	return 0;	/* not reached */
+   }
+ ! #endif
+   
+   /* Modify memory.
+    *
+ ***************
+ *** 1158,1181 ****
+   	"memory modify (constant address)",
+   	"[.b, .w, .l] address"
+   );
+ ! 
+   U_BOOT_CMD(
+   	mw,	4,	1,	do_mem_mw,
+   	"memory write (fill)",
+   	"[.b, .w, .l] address value [count]"
+   );
+ ! 
+   U_BOOT_CMD(
+   	cp,	4,	1,	do_mem_cp,
+   	"memory copy",
+   	"[.b, .w, .l] source target count"
+   );
+ ! 
+   U_BOOT_CMD(
+   	cmp,	4,	1,	do_mem_cmp,
+   	"memory compare",
+   	"[.b, .w, .l] addr1 addr2 count"
+   );
+   
+   #ifdef CONFIG_CMD_CRC32
+   
+ --- 1215,1239 ----
+   	"memory modify (constant address)",
+   	"[.b, .w, .l] address"
+   );
+ ! #ifndef CONFIG_MACH_CKB_3352
+   U_BOOT_CMD(
+   	mw,	4,	1,	do_mem_mw,
+   	"memory write (fill)",
+   	"[.b, .w, .l] address value [count]"
+   );
+ ! #endif
+   U_BOOT_CMD(
+   	cp,	4,	1,	do_mem_cp,
+   	"memory copy",
+   	"[.b, .w, .l] source target count"
+   );
+ ! #ifndef CONFIG_MACH_CKB_3352
+   U_BOOT_CMD(
+   	cmp,	4,	1,	do_mem_cmp,
+   	"memory compare",
+   	"[.b, .w, .l] addr1 addr2 count"
+   );
+ + #endif
+   
+   #ifdef CONFIG_CMD_CRC32
+   
+ ***************
+ *** 1206,1218 ****
+   	"\n    - print address offset for memory commands\n"
+   	"base off\n    - set address offset for memory commands to 'off'"
+   );
+ ! 
+   U_BOOT_CMD(
+   	loop,	3,	1,	do_mem_loop,
+   	"infinite loop on address range",
+   	"[.b, .w, .l] address number_of_objects"
+   );
+ ! 
+   #ifdef CONFIG_LOOPW
+   U_BOOT_CMD(
+   	loopw,	4,	1,	do_mem_loopw,
+ --- 1264,1276 ----
+   	"\n    - print address offset for memory commands\n"
+   	"base off\n    - set address offset for memory commands to 'off'"
+   );
+ ! #ifndef CONFIG_MACH_CKB_3352
+   U_BOOT_CMD(
+   	loop,	3,	1,	do_mem_loop,
+   	"infinite loop on address range",
+   	"[.b, .w, .l] address number_of_objects"
+   );
+ ! #endif
+   #ifdef CONFIG_LOOPW
+   U_BOOT_CMD(
+   	loopw,	4,	1,	do_mem_loopw,
+ ***************
+ *** 1220,1232 ****
+   	"[.b, .w, .l] address number_of_objects data_to_write"
+   );
+   #endif /* CONFIG_LOOPW */
+ ! 
+   U_BOOT_CMD(
+   	mtest,	5,	1,	do_mem_mtest,
+   	"simple RAM read/write test",
+   	"[start [end [pattern [iterations]]]]"
+   );
+ ! 
+   #ifdef CONFIG_MX_CYCLIC
+   U_BOOT_CMD(
+   	mdc,	4,	1,	do_mem_mdc,
+ --- 1278,1290 ----
+   	"[.b, .w, .l] address number_of_objects data_to_write"
+   );
+   #endif /* CONFIG_LOOPW */
+ ! #ifndef CONFIG_MACH_CKB_3352
+   U_BOOT_CMD(
+   	mtest,	5,	1,	do_mem_mtest,
+   	"simple RAM read/write test",
+   	"[start [end [pattern [iterations]]]]"
+   );
+ ! #endif
+   #ifdef CONFIG_MX_CYCLIC
+   U_BOOT_CMD(
+   	mdc,	4,	1,	do_mem_mdc,
+ diff -crN u-boot-2012.10_o/common/cmd_nand.c u-boot-2012.10/common/cmd_nand.c
+ *** u-boot-2012.10_o/common/cmd_nand.c	2012-10-16 00:14:08.000000000 +0900
+ --- u-boot-2012.10/common/cmd_nand.c	2014-02-27 11:33:16.785289084 +0900
+ ***************
+ *** 219,224 ****
+ --- 219,227 ----
+   	}
+   
+   print:
+ + 	if (getenv("nandsilent") != NULL)
+ + 		return 0;
+ + 
+   	printf("device %d ", *idx);
+   	if (*size == nand_info[*idx].size)
+   		puts("whole chip\n");
+ ***************
+ *** 556,562 ****
+   		if (argc != o + args)
+   			goto usage;
+   
+ ! 		printf("\nNAND %s: ", cmd);
+   		/* skip first two or three arguments, look for offset and size */
+   		if (arg_off_size(argc - o, argv + o, &dev, &off, &size) != 0)
+   			return 1;
+ --- 559,567 ----
+   		if (argc != o + args)
+   			goto usage;
+   
+ ! 		if (getenv("nandsilent") == NULL)
+ ! 			printf("\nNAND %s: ", cmd);
+ ! 
+   		/* skip first two or three arguments, look for offset and size */
+   		if (arg_off_size(argc - o, argv + o, &dev, &off, &size) != 0)
+   			return 1;
+ ***************
+ *** 590,596 ****
+   			}
+   		}
+   		ret = nand_erase_opts(nand, &opts);
+ ! 		printf("%s\n", ret ? "ERROR" : "OK");
+   
+   		return ret == 0 ? 0 : 1;
+   	}
+ --- 595,603 ----
+   			}
+   		}
+   		ret = nand_erase_opts(nand, &opts);
+ ! 
+ ! 		if (getenv("nandsilent") == NULL)
+ ! 			printf("%s\n", ret ? "ERROR" : "OK");
+   
+   		return ret == 0 ? 0 : 1;
+   	}
+ ***************
+ *** 617,623 ****
+   		addr = (ulong)simple_strtoul(argv[2], NULL, 16);
+   
+   		read = strncmp(cmd, "read", 4) == 0; /* 1 = read, 0 = write */
+ ! 		printf("\nNAND %s: ", read ? "read" : "write");
+   
+   		nand = &nand_info[dev];
+   
+ --- 624,632 ----
+   		addr = (ulong)simple_strtoul(argv[2], NULL, 16);
+   
+   		read = strncmp(cmd, "read", 4) == 0; /* 1 = read, 0 = write */
+ ! 
+ ! 		if (getenv("nandsilent") == NULL)
+ ! 			printf("\nNAND %s: ", read ? "read" : "write");
+   
+   		nand = &nand_info[dev];
+   
+ ***************
+ *** 695,702 ****
+   			return 1;
+   		}
+   
+ ! 		printf(" %zu bytes %s: %s\n", rwsize,
+ ! 		       read ? "read" : "written", ret ? "ERROR" : "OK");
+   
+   		return ret == 0 ? 0 : 1;
+   	}
+ --- 704,712 ----
+   			return 1;
+   		}
+   
+ ! 		if (getenv("nandsilent") == NULL)
+ ! 			printf(" %zu bytes %s: %s\n", rwsize,
+ ! 			       read ? "read" : "written", ret ? "ERROR" : "OK");
+   
+   		return ret == 0 ? 0 : 1;
+   	}
+ diff -crN u-boot-2012.10_o/common/command.c u-boot-2012.10/common/command.c
+ *** u-boot-2012.10_o/common/command.c	2012-10-16 00:14:08.000000000 +0900
+ --- u-boot-2012.10/common/command.c	2014-02-27 11:35:23.634797000 +0900
+ ***************
+ *** 29,34 ****
+ --- 29,38 ----
+   #include <command.h>
+   #include <linux/ctype.h>
+   
+ + #ifdef CONFIG_MACH_CKB_3352
+ + extern int _loader_executed_uboot;
+ + #endif
+ + 
+   /*
+    * Use puts() instead of printf() to avoid printf buffer overflow
+    * for long help messages
+ ***************
+ *** 39,45 ****
+   {
+   	int i;
+   	int rcode = 0;
+ ! 
+   	if (argc == 1) {	/*show list of commands */
+   		cmd_tbl_t *cmd_array[cmd_items];
+   		int i, j, swaps;
+ --- 43,52 ----
+   {
+   	int i;
+   	int rcode = 0;
+ ! 	
+ ! #ifdef CONFIG_MACH_CKB_3352
+ ! 	u_char cmd_ignored = 0;
+ ! #endif
+   	if (argc == 1) {	/*show list of commands */
+   		cmd_tbl_t *cmd_array[cmd_items];
+   		int i, j, swaps;
+ ***************
+ *** 76,81 ****
+ --- 83,95 ----
+   				return 1;
+   			if (usage == NULL)
+   				continue;
+ + #ifdef CONFIG_MACH_CKB_3352
+ + 			if(!cmd_ignored && _loader_executed_uboot && !strcmp(cmd_array[i]->name, FLASH_UBOOT_CMD_STR))
+ + 			{
+ + 				cmd_ignored = 1;
+ + 				continue;
+ + 			}
+ + #endif
+   			printf("%-*s- %s\n", CONFIG_SYS_HELP_CMD_WIDTH,
+   			       cmd_array[i]->name, usage);
+   		}
+ ***************
+ *** 103,114 ****
+    */
+   cmd_tbl_t *find_cmd_tbl (const char *cmd, cmd_tbl_t *table, int table_len)
+   {
+ ! 	cmd_tbl_t *cmdtp;
+ ! 	cmd_tbl_t *cmdtp_temp = table;	/*Init value */
+   	const char *p;
+   	int len;
+   	int n_found = 0;
+ ! 
+   	if (!cmd)
+   		return NULL;
+   	/*
+ --- 117,130 ----
+    */
+   cmd_tbl_t *find_cmd_tbl (const char *cmd, cmd_tbl_t *table, int table_len)
+   {
+ ! 	volatile cmd_tbl_t *cmdtp;
+ ! 	volatile cmd_tbl_t *cmdtp_temp = table;	/*Init value */
+   	const char *p;
+   	int len;
+   	int n_found = 0;
+ ! #ifdef CONFIG_MACH_CKB_3352
+ ! 	u_char cmd_ignored = 0;
+ ! #endif
+   	if (!cmd)
+   		return NULL;
+   	/*
+ ***************
+ *** 120,125 ****
+ --- 136,148 ----
+   	for (cmdtp = table;
+   	     cmdtp != table + table_len;
+   	     cmdtp++) {
+ + #ifdef CONFIG_MACH_CKB_3352
+ + 		if(!cmd_ignored && _loader_executed_uboot && !strcmp(cmdtp->name, FLASH_UBOOT_CMD_STR))
+ + 		{
+ + 			cmd_ignored = 1;
+ + 			continue;
+ + 		}
+ + #endif
+   		if (strncmp (cmd, cmdtp->name, len) == 0) {
+   			if (len == strlen (cmdtp->name))
+   				return cmdtp;	/* full match */
+ ***************
+ *** 181,192 ****
+   
+   static int complete_cmdv(int argc, char * const argv[], char last_char, int maxv, char *cmdv[])
+   {
+ ! 	cmd_tbl_t *cmdtp;
+   	const char *p;
+   	int len, clen;
+   	int n_found = 0;
+   	const char *cmd;
+ ! 
+   	/* sanity? */
+   	if (maxv < 2)
+   		return -2;
+ --- 204,217 ----
+   
+   static int complete_cmdv(int argc, char * const argv[], char last_char, int maxv, char *cmdv[])
+   {
+ ! 	volatile cmd_tbl_t *cmdtp;
+   	const char *p;
+   	int len, clen;
+   	int n_found = 0;
+   	const char *cmd;
+ ! #ifdef CONFIG_MACH_CKB_3352
+ ! 	u_char cmd_ignored = 0;
+ ! #endif
+   	/* sanity? */
+   	if (maxv < 2)
+   		return -2;
+ ***************
+ *** 196,201 ****
+ --- 221,233 ----
+   	if (argc == 0) {
+   		/* output full list of commands */
+   		for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) {
+ + #ifdef CONFIG_MACH_CKB_3352
+ + 			if(!cmd_ignored && _loader_executed_uboot && !strcmp(cmdtp->name, FLASH_UBOOT_CMD_STR))
+ + 			{
+ + 				cmd_ignored = 1;
+ + 				continue;
+ + 			}
+ + #endif		
+   			if (n_found >= maxv - 2) {
+   				cmdv[n_found++] = "...";
+   				break;
+ ***************
+ *** 229,235 ****
+   
+   	/* return the partial matches */
+   	for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) {
+ ! 
+   		clen = strlen(cmdtp->name);
+   		if (clen < len)
+   			continue;
+ --- 261,273 ----
+   
+   	/* return the partial matches */
+   	for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) {
+ ! #ifdef CONFIG_MACH_CKB_3352
+ ! 		if(!cmd_ignored && _loader_executed_uboot && !strcmp(cmdtp->name, FLASH_UBOOT_CMD_STR))
+ ! 		{
+ ! 			cmd_ignored = 1;
+ ! 			continue;
+ ! 		}
+ ! #endif
+   		clen = strlen(cmdtp->name);
+   		if (clen < len)
+   			continue;
+ ***************
+ *** 513,519 ****
+   			       int *repeatable)
+   {
+   	enum command_ret_t rc = CMD_RET_SUCCESS;
+ ! 	cmd_tbl_t *cmdtp;
+   
+   	/* Look up command in command table */
+   	cmdtp = find_cmd(argv[0]);
+ --- 551,557 ----
+   			       int *repeatable)
+   {
+   	enum command_ret_t rc = CMD_RET_SUCCESS;
+ ! 	volatile cmd_tbl_t *cmdtp;
+   
+   	/* Look up command in command table */
+   	cmdtp = find_cmd(argv[0]);
+ diff -crN u-boot-2012.10_o/common/env_common.c u-boot-2012.10/common/env_common.c
+ *** u-boot-2012.10_o/common/env_common.c	2012-10-16 00:14:08.000000000 +0900
+ --- u-boot-2012.10/common/env_common.c	2014-02-27 11:33:16.787904930 +0900
+ ***************
+ *** 238,245 ****
+    */
+   int env_import(const char *buf, int check)
+   {
+   	env_t *ep = (env_t *)buf;
+ ! 
+   	if (check) {
+   		uint32_t crc;
+   
+ --- 238,250 ----
+    */
+   int env_import(const char *buf, int check)
+   {
+ + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
+ + 	unsigned long addr = set_ckb_3352_flash_bank(buf);
+ + 	env_t *ep = (env_t *)addr;
+ + #else
+   	env_t *ep = (env_t *)buf;
+ ! #endif
+ ! 	
+   	if (check) {
+   		uint32_t crc;
+   
+ diff -crN u-boot-2012.10_o/common/env_flash.c u-boot-2012.10/common/env_flash.c
+ *** u-boot-2012.10_o/common/env_flash.c	2012-10-16 00:14:08.000000000 +0900
+ --- u-boot-2012.10/common/env_flash.c	2014-02-27 11:33:16.787904930 +0900
+ ***************
+ *** 72,78 ****
+   static ulong end_addr_new = CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1;
+   #endif /* CONFIG_ENV_ADDR_REDUND */
+   
+ - 
+   #ifdef CONFIG_ENV_ADDR_REDUND
+   int env_init(void)
+   {
+ --- 72,77 ----
+ ***************
+ *** 230,240 ****
+ --- 229,250 ----
+   
+   int env_init(void)
+   {
+ + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
+ + 	/* Set the bank */
+ + 	unsigned long addr = set_ckb_3352_flash_bank(env_ptr->data);
+ + 	if (crc32(0, addr, ENV_SIZE) == env_ptr->crc) {
+ + 		/* for now point the enviroment to the flash bank, this will me moved after malloc is available */
+ + 		gd->env_addr = addr;
+ + 		gd->env_valid	= 1;
+ + 		return 0;
+ + 	}	
+ + #else
+   	if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) {
+   		gd->env_addr	= (ulong)&(env_ptr->data);
+   		gd->env_valid	= 1;
+   		return 0;
+   	}
+ + #endif
+   
+   	gd->env_addr	= (ulong)&default_environment[0];
+   	gd->env_valid	= 0;
+ diff -crN u-boot-2012.10_o/drivers/mtd/cfi_flash.c u-boot-2012.10/drivers/mtd/cfi_flash.c
+ *** u-boot-2012.10_o/drivers/mtd/cfi_flash.c	2012-10-16 00:14:08.000000000 +0900
+ --- u-boot-2012.10/drivers/mtd/cfi_flash.c	2014-02-27 11:33:16.791619660 +0900
+ ***************
+ *** 79,84 ****
+ --- 79,139 ----
+   #define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
+   #endif
+   
+ + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
+ + extern int ckb_3352_cur_flash_bank;
+ + 
+ + inline static void mem_write8(u8 value, void *addr)
+ + {
+ + 	__raw_writeb(value, addr);
+ + }
+ + 
+ + inline static void mem_write16(u16 value, void *addr)
+ + {
+ + 	__raw_writew(value, addr);
+ + }
+ + 
+ + inline static void mem_write32(u32 value, void *addr)
+ + {
+ + 	__raw_writel(value, addr);
+ + }
+ + 
+ + inline static u8 mem_read8(void *addr)
+ + {
+ + 	return __raw_readb(addr);
+ + }
+ + 
+ + inline static u16 mem_read16(void *addr)
+ + {
+ + 	return __raw_readw(addr);
+ + }
+ + 
+ + inline static u32 mem_read32(void *addr)
+ + {
+ + 	return __raw_readl(addr);
+ + }
+ + 
+ + inline unsigned long set_ckb_3352_flash_bank(unsigned long addr)
+ + {
+ + 	/* The flash bank is a shadow mapping of 128KB changable by the GPIOs GP1[20]~GP1[26] */
+ + 	int ckb_3352_flash_bank = (addr - CONFIG_SYS_FLASH_BASE)/CONFIG_FLASH_CKB_BANK_SIZE;
+ + 	//printf("Map address %x ", addr);
+ + 	if(ckb_3352_flash_bank != ckb_3352_cur_flash_bank)
+ + 	{
+ + 		/* select map using GPIOs GP2[0]~GP2[3] */
+ + 		//printf("changing bank to %d addr %x\n", ckb_3352_flash_bank, addr); 
+ + 		set_nor_flash_bank(ckb_3352_flash_bank);
+ + 	}
+ + 	/* adjust the address */
+ + 	return (addr & (CONFIG_FLASH_CKB_BANK_SIZE-1)) | CONFIG_SYS_FLASH_BASE;
+ + }
+ + 
+ + unsigned long get_ckb_3352_flash_bank(unsigned long addr)
+ + {
+ + 	return (addr - CONFIG_SYS_FLASH_BASE) / CONFIG_FLASH_CKB_BANK_SIZE;
+ + }
+ + 
+ + #endif
+ + 
+   /*
+    * 0xffff is an undefined value for the configuration register. When
+    * this value is returned, the configuration register shall not be
+ ***************
+ *** 115,132 ****
+ --- 170,205 ----
+   unsigned long cfi_flash_bank_size(int i)
+   	__attribute__((weak, alias("__cfi_flash_bank_size")));
+   
+ + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
+ + inline
+ + #endif
+   static void __flash_write8(u8 value, void *addr)
+   {
+ + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
+ + 	addr = set_ckb_3352_flash_bank(addr);
+ + #endif
+   	__raw_writeb(value, addr);
+   }
+   
+ + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
+ + inline
+ + #endif
+   static void __flash_write16(u16 value, void *addr)
+   {
+ + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
+ + 	addr = set_ckb_3352_flash_bank(addr);
+ + #endif
+   	__raw_writew(value, addr);
+   }
+   
+ + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
+ + inline
+ + #endif
+   static void __flash_write32(u32 value, void *addr)
+   {
+ + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
+ + 	addr = set_ckb_3352_flash_bank(addr);
+ + #endif
+   	__raw_writel(value, addr);
+   }
+   
+ ***************
+ *** 136,153 ****
+ --- 209,245 ----
+   	*(volatile u64 *)addr = value;
+   }
+   
+ + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
+ + inline
+ + #endif
+   static u8 __flash_read8(void *addr)
+   {
+ + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
+ + 	addr = set_ckb_3352_flash_bank(addr);
+ + #endif
+   	return __raw_readb(addr);
+   }
+   
+ + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
+ + inline
+ + #endif
+   static u16 __flash_read16(void *addr)
+   {
+ + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
+ + 	addr = set_ckb_3352_flash_bank(addr);
+ + #endif
+   	return __raw_readw(addr);
+   }
+   
+ + 
+ + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
+ + inline
+ + #endif
+   static u32 __flash_read32(void *addr)
+   {
+ + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
+ + 	addr = set_ckb_3352_flash_bank(addr);
+ + #endif
+   	return __raw_readl(addr);
+   }
+   
+ ***************
+ *** 901,918 ****
+ --- 993,1025 ----
+   	while ((cnt-- > 0) && (flag == 1)) {
+   		switch (info->portwidth) {
+   		case FLASH_CFI_8BIT:
+ + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
+ + 			flag = ((flash_read8(dst2) & mem_read8(src)) ==
+ + 				mem_read8(src));
+ + #else
+   			flag = ((flash_read8(dst2) & flash_read8(src)) ==
+   				flash_read8(src));
+ + #endif
+   			src += 1, dst2 += 1;
+   			break;
+   		case FLASH_CFI_16BIT:
+ + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
+ + 			flag = ((flash_read16(dst2) & mem_read16(src)) ==
+ + 				mem_read16(src));
+ + #else
+   			flag = ((flash_read16(dst2) & flash_read16(src)) ==
+   				flash_read16(src));
+ + #endif
+   			src += 2, dst2 += 2;
+   			break;
+   		case FLASH_CFI_32BIT:
+ + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
+ + 			flag = ((flash_read32(dst2) & mem_read32(src)) ==
+ + 				mem_read32(src));
+ + #else
+   			flag = ((flash_read32(dst2) & flash_read32(src)) ==
+   				flash_read32(src));
+ + #endif
+   			src += 4, dst2 += 4;
+   			break;
+   		case FLASH_CFI_64BIT:
+ ***************
+ *** 950,964 ****
+ --- 1057,1083 ----
+   			while (cnt-- > 0) {
+   				switch (info->portwidth) {
+   				case FLASH_CFI_8BIT:
+ + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
+ + 					flash_write8(mem_read8(src), dst);
+ + #else
+   					flash_write8(flash_read8(src), dst);
+ + #endif
+   					src += 1, dst += 1;
+   					break;
+   				case FLASH_CFI_16BIT:
+ + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
+ + 					flash_write16(mem_read16(src), dst);
+ + #else
+   					flash_write16(flash_read16(src), dst);
+ + #endif
+   					src += 2, dst += 2;
+   					break;
+   				case FLASH_CFI_32BIT:
+ + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
+ + 					flash_write32(mem_read32(src), dst);
+ + #else
+   					flash_write32(flash_read32(src), dst);
+ + #endif
+   					src += 4, dst += 4;
+   					break;
+   				case FLASH_CFI_64BIT:
+ ***************
+ *** 993,1011 ****
+ --- 1112,1142 ----
+   		switch (info->portwidth) {
+   		case FLASH_CFI_8BIT:
+   			while (cnt-- > 0) {
+ + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
+ + 				flash_write8(mem_read8(src), dst);
+ + #else
+   				flash_write8(flash_read8(src), dst);
+ + #endif
+   				src += 1, dst += 1;
+   			}
+   			break;
+   		case FLASH_CFI_16BIT:
+   			while (cnt-- > 0) {
+ + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
+ + 				flash_write16(mem_read16(src), dst);
+ + #else
+   				flash_write16(flash_read16(src), dst);
+ + #endif
+   				src += 2, dst += 2;
+   			}
+   			break;
+   		case FLASH_CFI_32BIT:
+   			while (cnt-- > 0) {
+ + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
+ + 				flash_write32(mem_read32(src), dst);
+ + #else
+   				flash_write32(flash_read32(src), dst);
+ + #endif
+   				src += 4, dst += 4;
+   			}
+   			break;
+ ***************
+ *** 1256,1261 ****
+ --- 1387,1417 ----
+   		info->buffer_size);
+   	}
+   
+ + #ifdef CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
+ + 	printf ("  Number of banks: %ld\n", CONFIG_FLASH_CKB_BANKS);
+ + 	int bank = 0;
+ + 	for (i = 0; i < info->sector_count; ++i) {
+ + 		if (ctrlc())
+ + 			break;
+ + 		if(info->start[i] % CONFIG_FLASH_CKB_BANK_SIZE == 0)
+ + 		{
+ + 			printf ("\nBank# %ld: ", bank++);
+ + 			//puts ("\n  Sector Start Addresses:");
+ + 		}
+ + 		
+ + #ifdef CONFIG_SYS_FLASH_EMPTY_INFO
+ + 		/* print empty and read-only info */
+ + 		printf ("  %08lX %c %s ",
+ + 			(info->start[i] & (CONFIG_FLASH_CKB_BANK_SIZE-1)) | CONFIG_SYS_FLASH_BASE,
+ + 			sector_erased(info, i) ? 'E' : ' ',
+ + 			info->protect[i] ? "RO" : "  ");
+ + #else	/* ! CONFIG_SYS_FLASH_EMPTY_INFO */
+ + 		printf ("  %08lX   %s ",
+ + 			(info->start[i] & (CONFIG_FLASH_CKB_BANK_SIZE-1)) | CONFIG_SYS_FLASH_BASE,
+ + 			info->protect[i] ? "RO" : "  ");
+ + #endif
+ + 	}
+ + #else
+   	puts ("\n  Sector Start Addresses:");
+   	for (i = 0; i < info->sector_count; ++i) {
+   		if (ctrlc())
+ ***************
+ *** 1274,1279 ****
+ --- 1430,1436 ----
+   			info->protect[i] ? "RO" : "  ");
+   #endif
+   	}
+ + #endif
+   	putc ('\n');
+   	return;
+   }
+ diff -crN u-boot-2012.10_o/include/configs/ckb_3352.h u-boot-2012.10/include/configs/ckb_3352.h
+ *** u-boot-2012.10_o/include/configs/ckb_3352.h	1970-01-01 09:00:00.000000000 +0900
+ --- u-boot-2012.10/include/configs/ckb_3352.h	2014-11-25 15:23:33.675568000 +0900
+ ***************
+ *** 0 ****
+ --- 1,347 ----
+ + /*
+ +  * ckb_3352.h
+ +  *
+ +  * Copyright (C) 2012 Computex Co.,Ltd. - http://www.computex.co.jp/
+ +  *
+ +  * This program is free software; you can redistribute it and/or
+ +  * modify it under the terms of the GNU General Public License as
+ +  * published by the Free Software Foundation version 2.
+ +  *
+ +  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ +  * kind, whether express or implied; without even the implied warranty
+ +  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ +  * GNU General Public License for more details.
+ +  */
+ + 
+ + #ifndef __CONFIG_CKB_3352_H
+ + #define __CONFIG_CKB_3352_H
+ + 
+ + #define CONFIG_AM33XX
+ + 
+ + #include <asm/arch/cpu.h>
+ + #include <asm/arch/hardware.h>
+ + 
+ + /* LCD type (Use NO for undefining them). Do not remove or comment them */
+ + #define CONFIG_CKB_LCD_01
+ + #define CONFIG_CKB_NO_LCD_02
+ + /* DVI support (Use NO for undefining this) Do not remove or comment this */
+ + #define CONFIG_CKB_NO_DVI
+ + 
+ + #define CONFIG_REDUCE_UBOOT_SIZE
+ + 
+ + #define CONFIG_DMA_COHERENT
+ + #define CONFIG_DMA_COHERENT_SIZE	(1 << 20)
+ + 
+ + #define CONFIG_MACH_CKB_3352
+ + 
+ + #define CONFIG_CMDLINE_EDITING
+ + #define CONFIG_SYS_LONGHELP		/* undef to save memory */
+ + #define CONFIG_SYS_PROMPT		"U-Boot > "
+ + #undef CONFIG_SYS_NO_FLASH
+ + #define CONFIG_MACH_TYPE			4744	/* should match the machine type in the kernel (arch/arm/tools/mach-types.h) */
+ + 
+ + #define CONFIG_OF_LIBFDT
+ + #define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+ + #define CONFIG_SETUP_MEMORY_TAGS
+ + #define CONFIG_INITRD_TAG
+ + 
+ + #define CONFIG_SYS_CACHELINE_SIZE       64
+ + 
+ + #define CONFIG_CMD_ECHO
+ + 
+ + /* commands to include */
+ + #include <config_cmd_default.h>
+ + 
+ + #undef CONFIG_CMD_ENV
+ + #undef CONFIG_CMD_ASKENV
+ + #undef CONFIG_CMD_LOADS
+ + #undef CONFIG_CMD_SAVES
+ + 
+ + #undef CONFIG_USE_SPIFLASH
+ + #undef	CONFIG_USE_NAND
+ + #define CONFIG_SYS_USE_NOR
+ + #define CONFIG_USE_NOR
+ + #define CONFIG_NOR
+ + 
+ + #define CONFIG_NO_RELOCATE_UBOOT
+ + /*
+ +  * NOR Size = 16 MB
+ +  * No.Of Sectors/Blocks = 128
+ +  * Sector Size = 128 KB
+ +  * Word lenght = 16 bits
+ +  */
+ + #ifdef CONFIG_SYS_USE_NOR
+ + #define CONFIG_FLASH_SHOW_PROGRESS		45
+ + #define CONFIG_ENV_IS_IN_FLASH
+ + 
+ + #undef CONFIG_SYS_NO_FLASH
+ + #define CONFIG_SYS_MAX_FLASH_BANKS		1 /* max number of flash banks */
+ + 
+ + #define CONFIG_FLASH_CFI_DRIVER
+ + #define CONFIG_FLASH_CKB_3352_TUNE_CFI_DRIVER
+ + #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+ + #define CONFIG_FLASH_CKB_BANKS			128
+ + #define CONFIG_FLASH_CKB_BANK_SIZE		0x20000
+ + #define CONFIG_SYS_FLASH_CFI
+ + #define CONFIG_SYS_MAX_FLASH_SECT	128
+ + #define CONFIG_SYS_FLASH_BASE		0x08000000
+ + #define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+ + //#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+ + #ifndef CONFIG_REDUCE_UBOOT_SIZE
+ + #define CONFIG_MTD_DEVICE
+ + #define CONFIG_FLASH_CFI_MTD
+ + #endif
+ + #define CONFIG_CMD_FLASH
+ + #define CONFIG_SYS_FLASH_PROTECTION
+ + #define CONFIG_SYS_FLASH_CFI_AMD_RESET
+ + #define CONFIG_SYS_FLASH_SECT_SZ		(128 << 10) /* 128KB */
+ + #define CONFIG_ENV_OFFSET				0xE0000
+ + #define CONFIG_ENV_SIZE					(2 << 10)
+ + 
+ + #define CONFIG_ENV_SECT_SIZE			CONFIG_SYS_FLASH_SECT_SZ
+ + 
+ + #endif
+ + 
+ + #ifdef CONFIG_REDUCE_UBOOT_SIZE
+ + #undef CONFIG_CMD_BDI
+ + #undef CONFIG_CMD_BOOTD
+ + #undef CONFIG_CMD_CONSOLE
+ + #undef CONFIG_CMD_ECHO
+ + #undef CONFIG_CMD_FPGA
+ + #undef CONFIG_CMD_IMI
+ + #undef CONFIG_CMD_ITEST
+ + #undef CONFIG_CMD_IMLS
+ + //#undef CONFIG_CMD_LOADS
+ + #undef CONFIG_CMD_MISC
+ + #undef CONFIG_CMD_NET
+ + #undef CONFIG_CMD_NFS
+ + #undef CONFIG_CMD_SETGETDCR
+ + #undef CONFIG_CMD_SOURCE
+ + #undef CONFIG_CMD_XIMG
+ + #undef CONFIG_CMD_CRC32
+ + #undef CONFIG_CMD_EXPORTENV
+ + #undef CONFIG_CMD_GO
+ + #undef CONFIG_CMD_IMPORTENV
+ + #undef CONFIG_BOOTM_NETBSD
+ + #undef CONFIG_BOOTM_RTEMS
+ + #undef CONFIG_GZIP
+ + #undef CONFIG_ZLIB
+ + #undef CONFIG_PARTITIONS
+ + #endif
+ + #define CONFIG_AUTO_COMPLETE
+ + 
+ + #ifndef CONFIG_REDUCE_UBOOT_SIZE
+ + #define CONFIG_CMD_ASKENV
+ + #define CONFIG_VERSION_VARIABLE
+ + #endif
+ + 
+ + #define CONFIG_BOOTARGS				"console=ttyO0,115200n8"
+ + #define CONFIG_BOOTDELAY			3
+ + #define CONFIG_ZERO_BOOTDELAY_CHECK	
+ + #define CONFIG_BOOTCOMMAND			CKB_NOR_BOOTCOMMAND
+ + 
+ + #define CONFIG_USE_ARCH_MEMCPY
+ + #define CONFIG_USE_ARCH_MEMSET
+ + 
+ + /* Clock Defines */
+ + #define V_OSCK				24000000  /* Clock output from T2 */
+ + #define V_SCLK				(V_OSCK)
+ + 
+ + /* max number of command args */
+ + #define CONFIG_SYS_MAXARGS		16
+ + 
+ + /* Console I/O Buffer Size */
+ + #define CONFIG_SYS_CBSIZE		512
+ + 
+ + /* Print Buffer Size */
+ + #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE \
+ + 					+ sizeof(CONFIG_SYS_PROMPT) + 16)
+ + 
+ + /* Boot Argument Buffer Size */
+ + #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+ + 
+ + /*
+ +  * memtest works on 8 MB in DRAM after skipping 32MB from
+ +  * start addr of ram disk
+ +  */
+ + #define CONFIG_SYS_MEMTEST_START	(PHYS_DRAM_1 + (64 * 1024 * 1024))
+ + #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START \
+ + 					+ (8 * 1024 * 1024))
+ + 
+ + #define CONFIG_SYS_LOAD_ADDR		0x80007FC0 /* Default load address */
+ + #define CONFIG_SYS_HZ				1000 /* 1ms clock */
+ + 
+ + #define CONFIG_MMC
+ + #define CONFIG_GENERIC_MMC
+ + #define CONFIG_OMAP_HSMMC
+ + #define CONFIG_PARTITIONS
+ + 
+ + #ifdef CONFIG_MMC
+ + #define CONFIG_CMD_MMC
+ + #define CONFIG_DOS_PARTITION
+ + #define CONFIG_CMD_FAT
+ + #define CONFIG_CMD_EXT2
+ + #endif
+ + 
+ + /* CPSW ethernet */
+ + #if 0
+ + #define CONFIG_CMD_NET
+ + #define CONFIG_CMD_DHCP
+ + #define CONFIG_CMD_PING
+ + #define CONFIG_BOOTP_DEFAULT
+ + #define CONFIG_BOOTP_DNS
+ + #define CONFIG_BOOTP_DNS2
+ + #define CONFIG_BOOTP_SEND_HOSTNAME
+ + #define CONFIG_BOOTP_GATEWAY
+ + #define CONFIG_BOOTP_SUBNETMASK
+ + #define CONFIG_NET_RETRY_COUNT         10
+ + #define CONFIG_NET_MULTI
+ + #define CONFIG_PHY_GIGE
+ + #define CONFIG_PHYLIB
+ + #define CONFIG_PHY_SMSC
+ + #else
+ + //#undef CONFIG_CMD_NET
+ + #undef CONFIG_CMD_NFS
+ + #endif
+ + 
+ +  /* Physical Memory Map */
+ + #define CONFIG_NR_DRAM_BANKS		1		/*  1 bank of DRAM */
+ + #define PHYS_DRAM_1			0x80000000	/* DRAM Bank #1 */
+ + #define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
+ + 
+ + #define CONFIG_SYS_SDRAM_BASE		PHYS_DRAM_1
+ + #define CONFIG_SYS_INIT_SP_ADDR         (NON_SECURE_SRAM_END - \
+ + 						GENERATED_GBL_DATA_SIZE)
+ + #define CONFIG_SYS_SDRAM_SIZE		0x08000000					/* 128MB */
+ + 
+ +  /* Platform/Board specific defs */
+ + #define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
+ + #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+ + #define CONFIG_SYS_HZ			1000
+ + 
+ + /* NS16550 Configuration */
+ + #define CONFIG_SYS_NS16550
+ + #define CONFIG_SYS_NS16550_SERIAL
+ + #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+ + #define CONFIG_SYS_NS16550_CLK		(48000000)
+ + #define CONFIG_SYS_NS16550_COM1		0x44e09000	/* Base EVM has UART0 */
+ + 
+ + #ifdef CONFIG_CKB_DVI
+ + /* I2C Configuration */
+ + #define CONFIG_I2C
+ + #define CONFIG_CMD_I2C
+ + #define CONFIG_HARD_I2C
+ + #define CONFIG_SYS_I2C_SPEED		100000
+ + #define CONFIG_SYS_I2C_SLAVE		1
+ + #define CONFIG_I2C_MULTI_BUS
+ + #define CONFIG_DRIVER_OMAP24XX_I2C
+ + #endif
+ + 
+ + #ifndef CONFIG_REDUCE_UBOOT_SIZE
+ + /* I2C Configuration */
+ + #define CONFIG_I2C
+ + #define CONFIG_CMD_I2C
+ + #define CONFIG_HARD_I2C
+ + #define CONFIG_SYS_I2C_SPEED		100000
+ + #define CONFIG_SYS_I2C_SLAVE		1
+ + #define CONFIG_I2C_MULTI_BUS
+ + #define CONFIG_DRIVER_OMAP24XX_I2C
+ + #define CONFIG_CMD_EEPROM
+ + #define CONFIG_ENV_EEPROM_IS_ON_I2C
+ + #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Main EEPROM */
+ + #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+ + #define CONFIG_SYS_I2C_MULTI_EEPROMS
+ + #endif
+ + 
+ + #define CONFIG_OMAP_GPIO
+ + 
+ + #define CONFIG_BAUDRATE		115200
+ + #define CONFIG_SYS_BAUDRATE_TABLE	{ 110, 300, 600, 1200, 2400, \
+ + 4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 }
+ + 
+ + /*
+ +  * select serial console configuration
+ +  */
+ + #define CONFIG_SERIAL1			1
+ + #define CONFIG_CONS_INDEX		1
+ + #define CONFIG_SYS_CONSOLE_INFO_QUIET
+ + 
+ + //#define  CONFIG_SPL_BUILD
+ + 
+ + #define CONFIG_SYS_TEXT_BASE		0x87500000
+ + #define UBOOT_NOR_BASE_ADDR 		0x08020000		/* address of U-Boot on NOR flash */
+ + 
+ + #define CONFIG_SYS_MALLOC_LEN		(0x100000)
+ + #define CONFIG_STACKSIZE			(256*1024) /* regular stack */
+ + 
+ + #define CONFIG_SKIP_LOWLEVEL_INIT
+ + 
+ + /* Unsupported features */
+ + #undef CONFIG_USE_IRQ
+ + 
+ + /* Specific ENV defines */
+ + #define KERNEL_LOAD_ADDRESS			"0x80007FC0"		/* This address will eliminate re-copying the kernel code by U-Boot */
+ + #define CKB_KERN_MIN_SIZE			0x020000					/* Min size of the kernel image (just a rough value) */
+ + #define CKB_KERN_MAX_SIZE			0xE00000					/* Max size of the kernel image 14 MB */
+ + #define CKB_NOR_BOOTCOMMAND			"fread_kernel "KERNEL_LOAD_ADDRESS"; bootm "KERNEL_LOAD_ADDRESS
+ + #define CKB_MMC_BOOTCOMMAND			"mmc rescan 0; fatload mmc 0:1 "KERNEL_LOAD_ADDRESS" /uImage.bin; bootm "KERNEL_LOAD_ADDRESS
+ + #define MAX_LCD_IMAGE_FILE_SIZE		0x60000			/* 3 flash blocks */
+ + #define MAX_BOOTLOADER_FILE_SIZE		0x10000 		/* 64Kb */
+ + 
+ + #ifdef CONFIG_MMC
+ + #define CKB_MMC_BOOT_CMD		"mmcboot="CKB_MMC_BOOTCOMMAND"\0"
+ + #else
+ + #define CKB_MMC_BOOT_CMD
+ + #endif
+ + 
+ + #ifdef CONFIG_DRIVER_TI_EMAC
+ + #define CKB_NET_ENVS	"serverip=192.168.0.1\0" \
+ + 							"netmask=255.255.255.0\0" \
+ + 							"ipaddr=192.168.0.xx\0" \
+ + 							"gatewayip=192.168.0.1\0" \
+ + 							"manual_ethaddr=Set ethaddr manually. Eg: set ethaddr 00:e0:22:fe:41:4d. It can be set only once.\0"
+ + #else
+ + #define CKB_NET_ENVS
+ + #endif
+ + 
+ + #define CONFIG_EXTRA_ENV_SETTINGS \
+ + 	"norboot="CKB_NOR_BOOTCOMMAND"\0" \
+ + 	"r=bootm "KERNEL_LOAD_ADDRESS"\0" \
+ + 	CKB_MMC_BOOT_CMD \
+ + 	CKB_NET_ENVS
+ + 	
+ + #define DA8XX_LCD_CNTRL_BASE		0x4830E000
+ + #define LCD_IMAGE_ADDRESS			0x08080000
+ + 
+ + #if defined(CONFIG_CKB_DVI)
+ + #define CONFIG_FB_MAP_SIZE			0x500000			/* Approx 4MB (1366x768 max (DVI)) */
+ + #elif defined(CONFIG_CKB_LCD_01) || defined(CONFIG_CKB_LCD_02)
+ + #define CONFIG_FB_MAP_SIZE			0x200000			/* 2MB */
+ + #else
+ + #define CONFIG_FB_MAP_SIZE			0
+ + #endif
+ + 
+ + #if defined(CONFIG_CKB_LCD_01) || defined(CONFIG_CKB_LCD_02) || defined(CONFIG_CKB_DVI) 
+ + #define CONFIG_FB_BASE_ADDRESS		(CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE-CONFIG_FB_MAP_SIZE)		/* lower SDRAM (1MB aligned) */
+ + #endif
+ + 
+ + /* Note: The FB Palette is located just above the FB address. Because it
+ +    takes up only 32bytes, it's ok not to reserve this memory as 
+ +    UBOOT_TEMP_ADDR will take care of this.
+ +    This case is only when the Palette is used */ 
+ + 
+ + #define MAX_UBOOT_SIZE				0x60000			/* max uboot size (used for erasing flash while flashing U-Boot) */
+ + 
+ + /* memory that is hidden from U-boot (refer board.c) */
+ + #define CONFIG_CKB_RESERVED_MEM		(MAX_UBOOT_SIZE)
+ +  /* Memory to be hidden from Kernel */
+ + #define CONFIG_SYS_MEM_TOP_HIDE		(CONFIG_FB_MAP_SIZE)
+ + 
+ + /* addr where U-boot will be copied for flashing */
+ + #define UBOOT_TEMP_ADDR				(CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE-(CONFIG_SYS_MEM_TOP_HIDE+CONFIG_CKB_RESERVED_MEM))
+ + 
+ + #define FLASH_UBOOT_CMD_STR				"flash_uboot"
+ + 
+ + #endif	/* ! __CONFIG_CKB_3352_H */
+ + 
+ + 
diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-3352/samples/wdt/Makefile buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-3352/samples/wdt/Makefile
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-3352/samples/wdt/Makefile	1970-01-01 09:00:00.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-3352/samples/wdt/Makefile	2014-11-25 18:55:22.000000000 +0900
***************
*** 0 ****
--- 1,24 ----
+ # Makefile
+ 
+ BUILDROOT_DIR:=../../../../../
+ OUTPUT_DIR:=output
+ CROSS_COMPILE:=$(BUILDROOT_DIR)/$(OUTPUT_DIR)/host/usr/bin/arm-linux-
+ KERNEL_HEADERS:=$(BUILDROOT_DIR)/output/host/usr/arm-buildroot-linux-uclibcgnueabihf/sysroot/usr
+ #APP_DEBUG:=-ggdb
+ 
+ CC = $(CROSS_COMPILE)gcc $(APP_DEBUG) -I../common -I$(KERNEL_HEADERS) -O0
+ APP= saWatchdog
+ 
+ SRCS= saWatchdog.c
+ 
+ all: $(SRCS)
+ ifndef KERNEL_HEADERS
+ 	@echo "Error: The environment variable \"KERNEL_HEADERS\" is invalid."
+ 	@echo "\"KERNEL_HEADERS\" should point to the Kernel headers directory. Try \"make KERNEL_HEADERS=<kernel header directory>\""
+ else
+ 	$(CC) -o $(APP) $(SRCS) $(LIB)
+ endif
+ 
+ clean:
+ 	rm -f *.o $(APP)
+ 
diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-3352/samples/wdt/saWatchdog.c buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-3352/samples/wdt/saWatchdog.c
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-3352/samples/wdt/saWatchdog.c	1970-01-01 09:00:00.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-3352/samples/wdt/saWatchdog.c	2014-11-25 19:20:00.000000000 +0900
***************
*** 0 ****
--- 1,130 ----
+ /*
+  * Application to test AM335X Watchdog Timer (copied from that of TI816X)
+  *
+  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+  *
+  *  Redistribution and use in source and binary forms, with or without
+  *  modification, are permitted provided that the following conditions
+  *  are met:
+  *
+  *    Redistributions of source code must retain the above copyright
+  *    notice, this list of conditions and the following disclaimer.
+  *
+  *    Redistributions in binary form must reproduce the above copyright
+  *    notice, this list of conditions and the following disclaimer in the
+  *    documentation and/or other materials provided with the
+  *    distribution.
+  *
+  *    Neither the name of Texas Instruments Incorporated nor the names of
+  *    its contributors may be used to endorse or promote products derived
+  *    from this software without specific prior written permission.
+  *
+  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+ */
+ 
+ 
+ #include <stdio.h>
+ #include <linux/rtc.h>
+ #include <sys/ioctl.h>
+ #include <sys/time.h>
+ #include <sys/types.h>
+ #include <fcntl.h>
+ #include <unistd.h>
+ #include <errno.h>
+ #include <asm/types.h>
+ #include <linux/watchdog.h>
+ #include <sys/stat.h>
+ #include <signal.h>
+ 
+ int fd;
+ 
+ void catch_int(int signum)
+ {
+ 	signal(SIGINT, catch_int);
+ 
+ 	printf("In signal handler\n");
+ 	if(0 != close(fd))
+ 		printf("Close failed in signal handler\n");
+ 	else
+ 		printf("Close succeeded in signal handler\n");
+ }
+ 
+ int main(int argc, const char *argv[]) {
+ 
+ 	int sleep_time;
+ 	int wdt_timout, old_timout;
+ 	int ret_val;
+     
+ 	if(argc!=3)
+ 	{
+ 		printf("Usage: %s <WDT timeout> <Refresh time>\n", argv[0]);
+ 		printf("\t\t WDT timeout  : Watchdog timeout\n");
+ 		printf("\t\t Refresh time : Time to refresh Watchdog timer\n");
+ 		printf("If \"Refresh time\" is greater than \"WDT timeout\", the system will reset \n");
+ 		return 1;
+ 	}
+ 	wdt_timout = atoi(argv[1]);
+ 	sleep_time = atoi(argv[2]);
+ 	signal(SIGINT, catch_int);
+ 
+     fd=open("/dev/watchdog",O_WRONLY);
+ 	if (fd==-1) {
+     	perror("watchdog");
+ 		return 1;
+ 	}
+ 	printf ("Initializing WDT...\n");
+ 	ret_val = ioctl (fd, WDIOC_GETTIMEOUT, &old_timout);
+ 	if (ret_val) {
+ 		printf ("Watchdog Timer : WDIOC_GETTIMEOUT failed");
+ 	}
+ 	else {
+ 		printf ("Current timeout value is : %d seconds\n", old_timout);
+ 	}
+ 
+ 	ret_val = ioctl (fd, WDIOC_SETTIMEOUT, &wdt_timout);
+ 	if (ret_val) {
+ 		printf ("Watchdog Timer : WDIOC_SETTIMEOUT failed");
+ 	}
+ 	else {
+ 		printf ("New timeout value is : %d seconds\n", wdt_timout);
+ 	}
+ 
+ 	ret_val = ioctl (fd, WDIOC_GETTIMEOUT, &old_timout);
+ 	if (ret_val) {
+ 		printf ("Watchdog Timer : WDIOC_GETTIMEOUT failed");
+ 	}
+ 	else if(old_timout != wdt_timout){
+ 	
+ 		printf ("Opps...timeout value not set properly, current timeout is : %d seconds\n", old_timout);
+ 	}
+ 	while(1)
+ 	{
+     	if (1 != write(fd, "\0", 1))
+ 		{
+ 			printf("Write to WDT failed\n");
+ 			break;
+ 		}
+ 		else
+ 			printf("Wrote to WDT\n");
+ 
+     	sleep(sleep_time);
+ 	}
+ 
+ 	if (0 != close (fd))
+ 		printf("Close failed\n");
+ 	else
+ 		printf("Close succeeded\n");
+ 
+ 	return 0;
+ }
diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-3352/usr_to_rootfs.sh buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-3352/usr_to_rootfs.sh
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-3352/usr_to_rootfs.sh	1970-01-01 09:00:00.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-3352/usr_to_rootfs.sh	2014-11-27 16:43:26.000000000 +0900
***************
*** 0 ****
--- 1,65 ----
+ #!/bin/sh
+ #Environment variables passed as the arguments by buildroot
+ # $1 : Root FS folder
+ # $2 : Folder to which /usr has been moved
+ 
+ export ROOT_FS_FOLDER=$1
+ export USR_FOLDER=$2
+ 
+ #copy important libs and bins from /usr directory to the root folder directory
+ 	mkdir -p $ROOT_FS_FOLDER/usr/bin
+ 	mkdir -p $ROOT_FS_FOLDER/usr/sbin
+ 	mkdir -p $ROOT_FS_FOLDER/usr/lib
+ 	mkdir -p $ROOT_FS_FOLDER/usr/local/bin
+ 	cp -rpd $USR_FOLDER/local/bin/* $ROOT_FS_FOLDER/usr/local/bin/
+ 	cp -rpd $USR_FOLDER/bin/iperf $ROOT_FS_FOLDER/usr/bin/
+ 	cp -rpd $USR_FOLDER/bin/ts_test $ROOT_FS_FOLDER/usr/bin/
+ 	cp -rpd $USR_FOLDER/bin/ntpdate $ROOT_FS_FOLDER/usr/bin/
+ 	cp -rpd $USR_FOLDER/bin/inotify* $ROOT_FS_FOLDER/usr/bin/
+ 	cp -rpd $USR_FOLDER/bin/i2c* $ROOT_FS_FOLDER/usr/bin/
+ 	cp -rpd $USR_FOLDER/lib/ts* $ROOT_FS_FOLDER/usr/lib/
+ 	cp -rpd $USR_FOLDER/lib/libts* $ROOT_FS_FOLDER/usr/lib
+ 	cp -rpd $USR_FOLDER/lib/libintl.* $ROOT_FS_FOLDER/usr/lib
+ 	cp -rpd $USR_FOLDER/lib/libnl* $ROOT_FS_FOLDER/usr/lib
+ 	cp -rpd $USR_FOLDER/lib/libssl* $ROOT_FS_FOLDER/usr/lib/
+ 	cp -rpd $USR_FOLDER/lib/libcrypto* $ROOT_FS_FOLDER/usr/lib/
+ 	cp -rpd $USR_FOLDER/lib/libgpg-error* $ROOT_FS_FOLDER/usr/lib/
+ 	cp -rpd $USR_FOLDER/lib/libdbus* $ROOT_FS_FOLDER/usr/lib/
+ 	cp -rpd $USR_FOLDER/lib/libstdc++.so* $ROOT_FS_FOLDER/usr/lib/
+ 	cp -rpd $USR_FOLDER/lib/crda $ROOT_FS_FOLDER/usr/lib/
+ 	cp -rpd $USR_FOLDER/lib/avahi $ROOT_FS_FOLDER/usr/lib/
+ 	cp -rpd $USR_FOLDER/lib/libavahi-* $ROOT_FS_FOLDER/usr/lib/
+ 	cp -rpd $USR_FOLDER/lib/libdaemon.* $ROOT_FS_FOLDER/usr/lib/
+ 	cp -rpd $USR_FOLDER/lib/libexpat.* $ROOT_FS_FOLDER/usr/lib/
+ 	cp -rpd $USR_FOLDER/lib/libgcrypt.* $ROOT_FS_FOLDER/usr/lib/
+ 	cp -rpd $USR_FOLDER/sbin/iw $ROOT_FS_FOLDER/usr/sbin/
+ 	cp -rpd $USR_FOLDER/sbin/wpa_* $ROOT_FS_FOLDER/usr/sbin/
+ 	cp -rpd $USR_FOLDER/sbin/hostapd $ROOT_FS_FOLDER/usr/sbin/
+ 	cp -rpd $USR_FOLDER/sbin/mtd* $ROOT_FS_FOLDER/usr/sbin/
+ 	cp -rpd $USR_FOLDER/sbin/rtc* $ROOT_FS_FOLDER/usr/sbin/
+ 	cp -rpd $USR_FOLDER/sbin/fbset* $ROOT_FS_FOLDER/usr/sbin/
+ 	cp -rpd $USR_FOLDER/sbin/avahi-* $ROOT_FS_FOLDER/usr/sbin/
+ 	cp -rpd $USR_FOLDER/share/avahi $ROOT_FS_FOLDER/usr/share/
+ 	cp -rpd $USR_FOLDER/sbin/fbset* $ROOT_FS_FOLDER/usr/sbin/
+ 	cp -rpd $USR_FOLDER/share/udhcpc $ROOT_FS_FOLDER/usr/share/
+ 	cp -rpd $USR_FOLDER/bin/_cside* $ROOT_FS_FOLDER/usr/bin/
+ 	cp -rpd $USR_FOLDER/bin/cside* $ROOT_FS_FOLDER/usr/bin/
+ 	cp -rpd $USR_FOLDER/bin/libcsidemprof.so $ROOT_FS_FOLDER/usr/bin/
+ 	cp -rpd $USR_FOLDER/lib/libcdbmem.so $ROOT_FS_FOLDER/lib/
+ # - IPTABLES
+ #	cp -rpd $USR_FOLDER/sbin/iptables* $ROOT_FS_FOLDER/usr/sbin/
+ #	cp -rpd $USR_FOLDER/sbin/xtables* $ROOT_FS_FOLDER/usr/sbin/
+ # - SDL
+ #	cp -rpd $USR_FOLDER/lib/libSDL* $ROOT_FS_FOLDER/usr/lib/
+ 	cp -rpd $USR_FOLDER/lib/libjpeg.so* $ROOT_FS_FOLDER/usr/lib/
+ #	cp -rpd $USR_FOLDER/lib/libtiff.so* $ROOT_FS_FOLDER/usr/lib/
+ #	cp -rpd $USR_FOLDER/lib/libz.so* $ROOT_FS_FOLDER/usr/lib/
+ #	cp -rpd $USR_FOLDER/lib/libfreetype.so* $ROOT_FS_FOLDER/usr/lib/
+ 
+ #End
+ 
+ #Change permissions
+ chmod +x $ROOT_FS_FOLDER/etc/udhcpc.scripts 
+ chmod +x $ROOT_FS_FOLDER/etc/init.d/*
+ chmod +x $ROOT_FS_FOLDER/etc/network/wlan-scripts/*
+ sync
diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-rz/before_packing_fs.sh buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-rz/before_packing_fs.sh
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-rz/before_packing_fs.sh	1970-01-01 09:00:00.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-rz/before_packing_fs.sh	2014-02-13 09:03:29.000000000 +0900
***************
*** 0 ****
--- 1,14 ----
+ #!/bin/sh
+ #Environment variables; $TARGET_DIR is passed as the argument by buildroot
+ export TARGET_FS_FOLDER=$1
+ 
+ # legal-info licenses.txt
+ mkdir -p $TARGET_FS_FOLDER/etc/legal-info
+ cp $TARGET_FS_FOLDER/../legal-info/licenses.txt $TARGET_FS_FOLDER/etc/legal-info/licenses.txt
+ 
+ #Change permissions
+ chmod +x $TARGET_FS_FOLDER/etc/udhcpc.scripts 
+ chmod +x $TARGET_FS_FOLDER/etc/init.d/*
+ chmod +x $TARGET_FS_FOLDER/etc/network/wlan-scripts/*
+ #chmod +x $TARGET_FS_FOLDER/bin/*
+ sync
diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-rz/custom_fs.sh buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-rz/custom_fs.sh
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-rz/custom_fs.sh	2014-02-13 09:03:29.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-rz/custom_fs.sh	1970-01-01 09:00:00.000000000 +0900
***************
*** 1,14 ****
- #!/bin/sh
- #Environment variables; $TARGET_DIR is passed as the argument by buildroot
- export TARGET_FS_FOLDER=$1
- 
- # legal-info licenses.txt
- mkdir -p $TARGET_FS_FOLDER/etc/legal-info
- cp $TARGET_FS_FOLDER/../legal-info/licenses.txt $TARGET_FS_FOLDER/etc/legal-info/licenses.txt
- 
- #Change permissions
- chmod +x $TARGET_FS_FOLDER/etc/udhcpc.scripts 
- chmod +x $TARGET_FS_FOLDER/etc/init.d/*
- chmod +x $TARGET_FS_FOLDER/etc/network/wlan-scripts/*
- #chmod +x $TARGET_FS_FOLDER/bin/*
- sync
--- 0 ----
diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-rz/extern_fs.sh buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-rz/extern_fs.sh
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-rz/extern_fs.sh	2014-07-03 13:04:00.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-rz/extern_fs.sh	1970-01-01 09:00:00.000000000 +0900
***************
*** 1,65 ****
- #!/bin/sh
- #Environment variables passed as the arguments by buildroot
- # $1 : Root FS folder
- # $2 : Folder to which /usr has been moved
- 
- export ROOT_FS_FOLDER=$1
- export USR_FOLDER=$2
- 
- #copy important libs/bins from sdcard directory to the root folder directory
- 	mkdir -p $ROOT_FS_FOLDER/usr/bin
- 	mkdir -p $ROOT_FS_FOLDER/usr/sbin
- 	mkdir -p $ROOT_FS_FOLDER/usr/lib
- 	mkdir -p $ROOT_FS_FOLDER/usr/local/bin
- 	cp -rpd $USR_FOLDER/local/bin/* $ROOT_FS_FOLDER/usr/local/bin/
- 	cp -rpd $USR_FOLDER/bin/iperf $ROOT_FS_FOLDER/usr/bin/
-         cp -rpd $USR_FOLDER/bin/calibrator $ROOT_FS_FOLDER/usr/bin/
- 	cp -rpd $USR_FOLDER/bin/ts_test $ROOT_FS_FOLDER/usr/bin/
- 	cp -rpd $USR_FOLDER/bin/ntpdate $ROOT_FS_FOLDER/usr/bin/
- #	cp -rpd $USR_FOLDER/bin/inotify* $ROOT_FS_FOLDER/usr/bin/
- 	cp -rpd $USR_FOLDER/bin/i2c* $ROOT_FS_FOLDER/usr/bin/
- 	cp -rpd $USR_FOLDER/lib/ts* $ROOT_FS_FOLDER/usr/lib/
- 	cp -rpd $USR_FOLDER/lib/libts* $ROOT_FS_FOLDER/usr/lib
- #	cp -rpd $USR_FOLDER/lib/libintl.* $ROOT_FS_FOLDER/usr/lib
- 	cp -rpd $USR_FOLDER/lib/libnl* $ROOT_FS_FOLDER/usr/lib
- #	cp -rpd $USR_FOLDER/lib/libssl* $ROOT_FS_FOLDER/usr/lib/
- #	cp -rpd $USR_FOLDER/lib/libcrypto* $ROOT_FS_FOLDER/usr/lib/
- 	cp -rpd $USR_FOLDER/lib/libgpg-error* $ROOT_FS_FOLDER/usr/lib/
- #	cp -rpd $USR_FOLDER/lib/libdbus* $ROOT_FS_FOLDER/usr/lib/
- 	cp -rpd $USR_FOLDER/lib/libstdc++.so* $ROOT_FS_FOLDER/usr/lib/
- 	cp -rpd $USR_FOLDER/lib/crda $ROOT_FS_FOLDER/usr/lib/
- 	cp -rpd $USR_FOLDER/lib/avahi $ROOT_FS_FOLDER/usr/lib/
- 	cp -rpd $USR_FOLDER/lib/libavahi-* $ROOT_FS_FOLDER/usr/lib/
- 	cp -rpd $USR_FOLDER/lib/libdaemon.* $ROOT_FS_FOLDER/usr/lib/
- 	cp -rpd $USR_FOLDER/lib/libexpat.* $ROOT_FS_FOLDER/usr/lib/
- 	cp -rpd $USR_FOLDER/lib/libgcrypt.* $ROOT_FS_FOLDER/usr/lib/
- 	cp -rpd $USR_FOLDER/sbin/iw $ROOT_FS_FOLDER/usr/sbin/
- 	cp -rpd $USR_FOLDER/sbin/wpa_* $ROOT_FS_FOLDER/usr/sbin/
- 	cp -rpd $USR_FOLDER/sbin/hostapd $ROOT_FS_FOLDER/usr/sbin/
- #	cp -rpd $USR_FOLDER/sbin/mtd* $ROOT_FS_FOLDER/usr/sbin/
- #	cp -rpd $USR_FOLDER/sbin/rtc* $ROOT_FS_FOLDER/usr/sbin/
- 	cp -rpd $USR_FOLDER/sbin/fbset* $ROOT_FS_FOLDER/usr/sbin/
- 	cp -rpd $USR_FOLDER/sbin/avahi-* $ROOT_FS_FOLDER/usr/sbin/
- 	cp -rpd $USR_FOLDER/share/avahi $ROOT_FS_FOLDER/usr/share/
- 	cp -rpd $USR_FOLDER/share/udhcpc $ROOT_FS_FOLDER/usr/share/
- 	cp -rpd $USR_FOLDER/bin/_cside* $ROOT_FS_FOLDER/usr/bin/
- 	cp -rpd $USR_FOLDER/bin/cside* $ROOT_FS_FOLDER/usr/bin/
- 	cp -rpd $USR_FOLDER/bin/libcsidemprof.so $ROOT_FS_FOLDER/usr/bin/
- #	cp -rpd $USR_FOLDER/lib/libcdbmem.so $ROOT_FS_FOLDER/lib/
- # - IPTABLES
- #	cp -rpd $USR_FOLDER/sbin/iptables* $ROOT_FS_FOLDER/usr/sbin/
- #	cp -rpd $USR_FOLDER/sbin/xtables* $ROOT_FS_FOLDER/usr/sbin/
- # - SDL
- #	cp -rpd $USR_FOLDER/lib/libSDL* $ROOT_FS_FOLDER/usr/lib/
- #	cp -rpd $USR_FOLDER/lib/libjpeg.so* $ROOT_FS_FOLDER/usr/lib/
- #	cp -rpd $USR_FOLDER/lib/libtiff.so* $ROOT_FS_FOLDER/usr/lib/
- #	cp -rpd $USR_FOLDER/lib/libz.so* $ROOT_FS_FOLDER/usr/lib/
- #	cp -rpd $USR_FOLDER/lib/libfreetype.so* $ROOT_FS_FOLDER/usr/lib/
- 
- #End
- 
- #Change permissions
- chmod +x $ROOT_FS_FOLDER/etc/udhcpc.scripts 
- chmod +x $ROOT_FS_FOLDER/etc/init.d/*
- chmod +x $ROOT_FS_FOLDER/etc/network/wlan-scripts/*
- sync
--- 0 ----
diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-rz/usr_to_rootfs.sh buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-rz/usr_to_rootfs.sh
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/ckb-rz/usr_to_rootfs.sh	1970-01-01 09:00:00.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/ckb-rz/usr_to_rootfs.sh	2014-11-28 08:58:50.000000000 +0900
***************
*** 0 ****
--- 1,65 ----
+ #!/bin/sh
+ #Environment variables passed as the arguments by buildroot
+ # $1 : Root FS folder
+ # $2 : Folder to which /usr has been moved
+ 
+ export ROOT_FS_FOLDER=$1
+ export USR_FOLDER=$2
+ 
+ #copy important libs and bins from /usr directory to the root folder directory
+ 	mkdir -p $ROOT_FS_FOLDER/usr/bin
+ 	mkdir -p $ROOT_FS_FOLDER/usr/sbin
+ 	mkdir -p $ROOT_FS_FOLDER/usr/lib
+ 	mkdir -p $ROOT_FS_FOLDER/usr/local/bin
+ 	cp -rpd $USR_FOLDER/local/bin/* $ROOT_FS_FOLDER/usr/local/bin/
+ 	cp -rpd $USR_FOLDER/bin/iperf $ROOT_FS_FOLDER/usr/bin/
+         cp -rpd $USR_FOLDER/bin/calibrator $ROOT_FS_FOLDER/usr/bin/
+ 	cp -rpd $USR_FOLDER/bin/ts_test $ROOT_FS_FOLDER/usr/bin/
+ 	cp -rpd $USR_FOLDER/bin/ntpdate $ROOT_FS_FOLDER/usr/bin/
+ #	cp -rpd $USR_FOLDER/bin/inotify* $ROOT_FS_FOLDER/usr/bin/
+ 	cp -rpd $USR_FOLDER/bin/i2c* $ROOT_FS_FOLDER/usr/bin/
+ 	cp -rpd $USR_FOLDER/lib/ts* $ROOT_FS_FOLDER/usr/lib/
+ 	cp -rpd $USR_FOLDER/lib/libts* $ROOT_FS_FOLDER/usr/lib
+ #	cp -rpd $USR_FOLDER/lib/libintl.* $ROOT_FS_FOLDER/usr/lib
+ 	cp -rpd $USR_FOLDER/lib/libnl* $ROOT_FS_FOLDER/usr/lib
+ #	cp -rpd $USR_FOLDER/lib/libssl* $ROOT_FS_FOLDER/usr/lib/
+ #	cp -rpd $USR_FOLDER/lib/libcrypto* $ROOT_FS_FOLDER/usr/lib/
+ 	cp -rpd $USR_FOLDER/lib/libgpg-error* $ROOT_FS_FOLDER/usr/lib/
+ #	cp -rpd $USR_FOLDER/lib/libdbus* $ROOT_FS_FOLDER/usr/lib/
+ 	cp -rpd $USR_FOLDER/lib/libstdc++.so* $ROOT_FS_FOLDER/usr/lib/
+ 	cp -rpd $USR_FOLDER/lib/crda $ROOT_FS_FOLDER/usr/lib/
+ 	cp -rpd $USR_FOLDER/lib/avahi $ROOT_FS_FOLDER/usr/lib/
+ 	cp -rpd $USR_FOLDER/lib/libavahi-* $ROOT_FS_FOLDER/usr/lib/
+ 	cp -rpd $USR_FOLDER/lib/libdaemon.* $ROOT_FS_FOLDER/usr/lib/
+ 	cp -rpd $USR_FOLDER/lib/libexpat.* $ROOT_FS_FOLDER/usr/lib/
+ 	cp -rpd $USR_FOLDER/lib/libgcrypt.* $ROOT_FS_FOLDER/usr/lib/
+ 	cp -rpd $USR_FOLDER/sbin/iw $ROOT_FS_FOLDER/usr/sbin/
+ 	cp -rpd $USR_FOLDER/sbin/wpa_* $ROOT_FS_FOLDER/usr/sbin/
+ 	cp -rpd $USR_FOLDER/sbin/hostapd $ROOT_FS_FOLDER/usr/sbin/
+ #	cp -rpd $USR_FOLDER/sbin/mtd* $ROOT_FS_FOLDER/usr/sbin/
+ #	cp -rpd $USR_FOLDER/sbin/rtc* $ROOT_FS_FOLDER/usr/sbin/
+ 	cp -rpd $USR_FOLDER/sbin/fbset* $ROOT_FS_FOLDER/usr/sbin/
+ 	cp -rpd $USR_FOLDER/sbin/avahi-* $ROOT_FS_FOLDER/usr/sbin/
+ 	cp -rpd $USR_FOLDER/share/avahi $ROOT_FS_FOLDER/usr/share/
+ 	cp -rpd $USR_FOLDER/share/udhcpc $ROOT_FS_FOLDER/usr/share/
+ 	cp -rpd $USR_FOLDER/bin/_cside* $ROOT_FS_FOLDER/usr/bin/
+ 	cp -rpd $USR_FOLDER/bin/cside* $ROOT_FS_FOLDER/usr/bin/
+ 	cp -rpd $USR_FOLDER/bin/libcsidemprof.so $ROOT_FS_FOLDER/usr/bin/
+ #	cp -rpd $USR_FOLDER/lib/libcdbmem.so $ROOT_FS_FOLDER/lib/
+ # - IPTABLES
+ #	cp -rpd $USR_FOLDER/sbin/iptables* $ROOT_FS_FOLDER/usr/sbin/
+ #	cp -rpd $USR_FOLDER/sbin/xtables* $ROOT_FS_FOLDER/usr/sbin/
+ # - SDL
+ #	cp -rpd $USR_FOLDER/lib/libSDL* $ROOT_FS_FOLDER/usr/lib/
+ #	cp -rpd $USR_FOLDER/lib/libjpeg.so* $ROOT_FS_FOLDER/usr/lib/
+ #	cp -rpd $USR_FOLDER/lib/libtiff.so* $ROOT_FS_FOLDER/usr/lib/
+ #	cp -rpd $USR_FOLDER/lib/libz.so* $ROOT_FS_FOLDER/usr/lib/
+ #	cp -rpd $USR_FOLDER/lib/libfreetype.so* $ROOT_FS_FOLDER/usr/lib/
+ 
+ #End
+ 
+ #Change permissions
+ chmod +x $ROOT_FS_FOLDER/etc/udhcpc.scripts 
+ chmod +x $ROOT_FS_FOLDER/etc/init.d/*
+ chmod +x $ROOT_FS_FOLDER/etc/network/wlan-scripts/*
+ sync
diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/common/samples/usb_cam_app/usb_cam_app.c buildroot-2013.08.1-ckb-20141129-1/board/ckb/common/samples/usb_cam_app/usb_cam_app.c
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/common/samples/usb_cam_app/usb_cam_app.c	2014-07-23 10:32:33.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/common/samples/usb_cam_app/usb_cam_app.c	2014-11-27 16:03:31.000000000 +0900
***************
*** 45,54 ****
  
  #include <linux/input.h>
  
- #include <string.h>
- #include <fcntl.h>
- #include <unistd.h>
- #include <stdio.h>
  /******************************************************************************
   Macros
   MAX_BUFFERS    : Changing the following will result different number of
--- 45,50 ----
***************
*** 1202,1208 ****
  
  void help(char *app_name)
  {
! 	printf("%s -d [device path] -f [0/1] -W [width] -H [height] -r [frame rate]"
  					"\n\t\t-X [x coordinate] -Y [y coordinate]"
  					"\n\t\t-z -v -y -u -o -i -n -s -j [JPEG quality] -b\n", app_name);
  	printf("\t-d - Camera device path ("CAPTURE_DEVICE")\n");
--- 1198,1204 ----
  
  void help(char *app_name)
  {
! 	printf("%s -d [device path] -W [width] -H [height] -r [frame rate]"
  					"\n\t\t-X [x coordinate] -Y [y coordinate]"
  					"\n\t\t-z -v -y -u -o -i -n -s -j [JPEG quality] -b\n", app_name);
  	printf("\t-d - Camera device path ("CAPTURE_DEVICE")\n");
***************
*** 1227,1233 ****
  int main(int argc, char *argv[])
  {
  	int ret = 0, i, d, index;
! 	char shortoptions[] = "d:f:W:H:r:X:Y:j:zvyuoinsb";
  	int temp;
  	int daemon = 0;
  	char filename[256], buf[256];
--- 1223,1229 ----
  int main(int argc, char *argv[])
  {
  	int ret = 0, i, d, index;
! 	char shortoptions[] = "d:W:H:r:X:Y:j:zvyuoinsb";
  	int temp;
  	int daemon = 0;
  	char filename[256], buf[256];
***************
*** 1301,1307 ****
  			daemon = 1;
  			break;
  		default:
- _exit:
  			help(argv[0]);
  			exit(1);
  		}
--- 1297,1302 ----
diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/common/samples/usb_cam_streamer/main.c buildroot-2013.08.1-ckb-20141129-1/board/ckb/common/samples/usb_cam_streamer/main.c
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/common/samples/usb_cam_streamer/main.c	2014-07-22 18:40:01.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/common/samples/usb_cam_streamer/main.c	2014-11-28 08:54:20.000000000 +0900
***************
*** 308,316 ****
  	DBG("starting output\n");
  	syslog(LOG_INFO, "starting output");
  	output_run();
!   
  	/* create the watchdog task */
  	watchdog_run();
  	/* wait for signals */
  	pause();
  
--- 308,318 ----
  	DBG("starting output\n");
  	syslog(LOG_INFO, "starting output");
  	output_run();
! 
! #if 0		/* not needed */
  	/* create the watchdog task */
  	watchdog_run();
+ #endif
  	/* wait for signals */
  	pause();
  
diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/common/samples/yuv_usb_cam_app/Makefile buildroot-2013.08.1-ckb-20141129-1/board/ckb/common/samples/yuv_usb_cam_app/Makefile
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/common/samples/yuv_usb_cam_app/Makefile	2014-06-12 14:21:55.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/common/samples/yuv_usb_cam_app/Makefile	1970-01-01 09:00:00.000000000 +0900
***************
*** 1,21 ****
- # Makefile
- 
- BUILDROOT_DIR:=../../../../../
- OUTPUT_DIR:=output
- CROSS_COMPILE:=$(BUILDROOT_DIR)/$(OUTPUT_DIR)/host/usr/bin/arm-linux-
- KERNEL_HEADERS:=$(BUILDROOT_DIR)/output/host/usr/arm-buildroot-linux-uclibcgnueabi/sysroot/usr
- #APP_DEBUG:=-ggdb
- 
- CC = $(CROSS_COMPILE)gcc $(APP_DEBUG) -I$(KERNEL_HEADERS)
- 
- all:
- ifndef KERNEL_HEADERS
- 	@echo "Error: The environment variable \"KERNEL_HEADERS\" is invalid."
- 	@echo "\"KERNEL_HEADERS\" should point to the Kernel headers directory. Try \"make KERNEL_HEADERS=<kernel header directory>\""
- else
- 	$(CC) -lpthread -ljpeg -o yuv_usb_cam_app yuv_usb_cam_app.c -ggdb
- endif
- 
- clean:
- 	rm -f *.o yuv_usb_cam_app
- 
--- 0 ----
diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/common/samples/yuv_usb_cam_app/framebuffer.h buildroot-2013.08.1-ckb-20141129-1/board/ckb/common/samples/yuv_usb_cam_app/framebuffer.h
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/common/samples/yuv_usb_cam_app/framebuffer.h	2013-02-20 10:54:18.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/common/samples/yuv_usb_cam_app/framebuffer.h	1970-01-01 09:00:00.000000000 +0900
***************
*** 1,38 ****
- /*
-  * Author: Yusuf Caglar Akyuz, Bilkon, Inc. <caglar@bilkon-kontrol.com.tr>
-  *
-  * Copyright (C) 2010 Bilkon Bilgisayar Kontrollu Cihazlar Ltd. Sti.
-  *
-  * This program is free software: you can redistribute it and/or modify
-  * it under the terms of the GNU General Public License as published by
-  * the Free Software Foundation, either version 3 of the License.
- 
-  * This program is distributed in the hope that it will be useful,
-  * but WITHOUT ANY WARRANTY; without even the implied warranty of
-  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-  * GNU General Public License for more details.
-  *
-  *  You should have received a copy of the GNU General Public License
-  *  along with this program.  If not, see <http://www.gnu.org/licenses/>.
-  */
- #ifndef FRAMEBUFFER_H_
- #define FRAMEBUFFER_H_
- 
- #ifdef __cplusplus
- extern "C" {
- #endif
- 
- struct framebuffer_info {
- 	int fd;
- 	char *device_name;
- 	int disp_size;
- 	char *userptr;
- };
- 
- int init_framebuffer(struct framebuffer_info *fbinfo);
- 
- #ifdef __cplusplus
- }
- #endif
- 
- #endif /* FRAMEBUFFER_H_ */
--- 0 ----
バイナリーファイル buildroot-2013.08.1-ckb-20140807-1/board/ckb/common/samples/yuv_usb_cam_app/yuv_usb_cam_app とbuildroot-2013.08.1-ckb-20141129-1/board/ckb/common/samples/yuv_usb_cam_app/yuv_usb_cam_app は異なります
diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/common/samples/yuv_usb_cam_app/yuv_usb_cam_app-mine.c buildroot-2013.08.1-ckb-20141129-1/board/ckb/common/samples/yuv_usb_cam_app/yuv_usb_cam_app-mine.c
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/common/samples/yuv_usb_cam_app/yuv_usb_cam_app-mine.c	2014-06-10 09:58:14.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/common/samples/yuv_usb_cam_app/yuv_usb_cam_app-mine.c	1970-01-01 09:00:00.000000000 +0900
***************
*** 1,1213 ****
- /*
-  * vpif_cam_test.c
-  *
-  * This is the sample to show AM1808 VPIF capture functionality using
-  * memory mapped buffers. It accepts channel number and standard to capture
-  * as input; It captures frames from the camera copies them from capture buffer
-  * to the frame buffer and displays them.
-  * Flow: Camera -> VPIF -> Display
-  *
-  * Copyright (c) 2011 Computex Co.,Ltd.  All Rights Reserved.
-  *
-  *
- */
-  /******************************************************************************
-   Header File Inclusion
-  ******************************************************************************/
- #include <stdio.h>
- #include <stdlib.h>
- #include <string.h>
- #include <unistd.h>
- #include <sys/types.h>
- #include <sys/stat.h>
- #include <fcntl.h>
- #include <dirent.h>
- #include <sys/ioctl.h>
- #include <sys/mman.h>
- #include <errno.h>
- #include <linux/videodev2.h>
- #include <linux/v4l2-mediabus.h>
- #include <linux/fb.h>
- #include <asm/errno.h>
- #include "framebuffer.h"
- #include <termios.h>
- #include <sys/epoll.h>
- #include <pthread.h>
- #include <jpeglib.h>
- 
- #define uint32_t u32
- #define uint8_t u8 
- typedef unsigned int u32;
- typedef unsigned char u8;
- typedef unsigned char u_char;
- //#define _USE_TP_EVENT_
- #define TP_EVENT_DEVICE			"/dev/input/event0"
- 
- #include <linux/input.h>
- 
- #include <string.h>
- #include <fcntl.h>
- #include <unistd.h>
- #include <stdio.h>
- /******************************************************************************
-  Macros
-  MAX_BUFFERS    : Changing the following will result different number of
- 		  instances of buf_info structure.
-  CAPTURE_DEVICE : This indicates device to be used for capture
-  DISPLAY_DEVICE : This indicates device to be used for display
-  ******************************************************************************/
- #define MAX_BUFFERS		3
- #define FRAME_CAPTURE_FILE	"/root/capt_frame.raw"
- #define CAPTURE_DEVICE	"/dev/video2"
- #define CAPTURE_INPUT "Camera"
- #define CLEAR(x)	memset(&(x), 0, sizeof(x))
- #define ALIGN(x, y)     (((x + (y-1)) / y) * y)
- char temp_buffer[2*1024*1024];
- char temp_buffer2[2*1024*1024];
- int epfd;
- //int g_pixelformat = V4L2_PIX_FMT_YUYV;
- int g_pixelformat = V4L2_PIX_FMT_MJPEG;
- int g_width = 640;
- int g_height = 480;
- int g_fps = 30;
- int x_start=0, y_start=0;
- int ux_start=-1, uy_start=-1;
- struct v4l2_buffer g_capture_buf;
- 
- /* save captured frame */
- int save_frame = 0;
- int g_hflip = 0;
- int g_vflip = 1;
- 
- #define _FASTEST_PROCESSING_		/* Omits averaging and uses only 1 value during color interpolation */
- #define _FASTER_PROCESSING_			/* Averages 2 values during color interpolation */
- #define _FASTER_CODE_				/* Omits displaying the first top and bottom lines of the image */
- 
- /******************************************************************************
-  Declaration
- 	Following structure is used to store information of the buffers which
- 	are mmapped.
-  ******************************************************************************/
- struct buf_info {
- 	int index;
- 	unsigned int length;
- 	char *start;
- };
- 
- static struct buf_info capture_buff_info[MAX_BUFFERS];
- static int g_numbuffers;
- static unsigned int g_buffer_size;
- /******************************************************************************
- 			Function Definitions
-  ******************************************************************************/
- static int initCapture(int *capture_fd, struct v4l2_format *fmt);
- static int startCapture(int *);
- static int getCaptureBuffer(int *);
- static int putCaptureBuffer(int *capture_fd);
- static int stopCapture(int *);
- static void releaseCapture(int *);
- 
- char input_device[16];
- 
- /* print frame number */
- int print_fn = 0;
- FILE *file_fp = NULL;
- int bytesperline_camera;
- int sizeimage_camera;
- 
- int app_main();
- 
- struct framebuffer_info fbinfo;
- struct fb_var_screeninfo varInfo;
-     
-     
-     
- /******************************************************************************
- Description.: yuv2jpeg function is based on compress_yuyv_to_jpeg written by
-               Gabriel A. Devenyi.
-               It uses the destination manager implemented above to compress
-               YUYV data to JPEG. Most other implementations use the
-               "jpeg_stdio_dest" from libjpeg, which can not store compressed
-               pictures to memory instead of a file.
- Input Value.: video structure from v4l2uvc.c/h, destination buffer and buffersize
-               the buffer must be large enough, no error/size checking is done!
- Return Value: the buffer will contain the compressed data
- ******************************************************************************/
- void compress_yuyv_to_rgb565(unsigned char *in_buffer, unsigned char *out_buffer)
- {
- 	unsigned char *yuyv;
- 	int z;
- 	static int written;
- 	int line = 0;
- 	unsigned short *ptr = (unsigned short *)out_buffer;
- 	
- 	written = 0;
- 	/* YUV (Not 422) */
- 	yuyv = in_buffer;
- 	z = 0;
- 	while (line < g_height) {
- 		int x;
- 		for (x = 0; x < g_width; x++) {
- 			int r, g, b;
- 			int y, u, v;
- 
- 			if (!z)
- 			y = yuyv[0] << 8;
- 			else
- 			y = yuyv[2] << 8;
- 			u = yuyv[1] - 128;
- 			v = yuyv[3] - 128;
- 
- 			r = (y + (359 * v)) >> 8;
- 			g = (y - (88 * u) - (183 * v)) >> 8;
- 			b = (y + (454 * u)) >> 8;
- #if 0
- 			*(ptr++) = (r > 255) ? 255 : ((r < 0) ? 0 : r);
- 			*(ptr++) = (g > 255) ? 255 : ((g < 0) ? 0 : g);
- 			*(ptr++) = (b > 255) ? 255 : ((b < 0) ? 0 : b);
- #else
- 			*ptr = ((r & 0xF8)<<8) | ((g & 0xFC)<< 3)  | ((b & 0xF8) >>3);
- 			ptr++;			 
- #endif
- 			
- 			if (z++) {
- 				z = 0;
- 				yuyv += 4;
- 			}
- 		}
- 		line++;
- 	}
- }
- 
- const static unsigned char dht_data[] = {
-   0xff, 0xc4, 0x01, 0xa2, 0x00, 0x00, 0x01, 0x05, 0x01, 0x01, 0x01, 0x01,
-   0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02,
-   0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x01, 0x00, 0x03,
-   0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00,
-   0x00, 0x00, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09,
-   0x0a, 0x0b, 0x10, 0x00, 0x02, 0x01, 0x03, 0x03, 0x02, 0x04, 0x03, 0x05,
-   0x05, 0x04, 0x04, 0x00, 0x00, 0x01, 0x7d, 0x01, 0x02, 0x03, 0x00, 0x04,
-   0x11, 0x05, 0x12, 0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07, 0x22,
-   0x71, 0x14, 0x32, 0x81, 0x91, 0xa1, 0x08, 0x23, 0x42, 0xb1, 0xc1, 0x15,
-   0x52, 0xd1, 0xf0, 0x24, 0x33, 0x62, 0x72, 0x82, 0x09, 0x0a, 0x16, 0x17,
-   0x18, 0x19, 0x1a, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x34, 0x35, 0x36,
-   0x37, 0x38, 0x39, 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4a,
-   0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5a, 0x63, 0x64, 0x65, 0x66,
-   0x67, 0x68, 0x69, 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7a,
-   0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8a, 0x92, 0x93, 0x94, 0x95,
-   0x96, 0x97, 0x98, 0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8,
-   0xa9, 0xaa, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 0xc2,
-   0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2, 0xd3, 0xd4, 0xd5,
-   0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
-   0xe8, 0xe9, 0xea, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9,
-   0xfa, 0x11, 0x00, 0x02, 0x01, 0x02, 0x04, 0x04, 0x03, 0x04, 0x07, 0x05,
-   0x04, 0x04, 0x00, 0x01, 0x02, 0x77, 0x00, 0x01, 0x02, 0x03, 0x11, 0x04,
-   0x05, 0x21, 0x31, 0x06, 0x12, 0x41, 0x51, 0x07, 0x61, 0x71, 0x13, 0x22,
-   0x32, 0x81, 0x08, 0x14, 0x42, 0x91, 0xa1, 0xb1, 0xc1, 0x09, 0x23, 0x33,
-   0x52, 0xf0, 0x15, 0x62, 0x72, 0xd1, 0x0a, 0x16, 0x24, 0x34, 0xe1, 0x25,
-   0xf1, 0x17, 0x18, 0x19, 0x1a, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x35, 0x36,
-   0x37, 0x38, 0x39, 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4a,
-   0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5a, 0x63, 0x64, 0x65, 0x66,
-   0x67, 0x68, 0x69, 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7a,
-   0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8a, 0x92, 0x93, 0x94,
-   0x95, 0x96, 0x97, 0x98, 0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
-   0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba,
-   0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2, 0xd3, 0xd4,
-   0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
-   0xe8, 0xe9, 0xea, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9, 0xfa
- };
- 
- 
- /******************************************************************************
- Description.: 
- Input Value.: 
- Return Value: 
- ******************************************************************************/
- int is_huffman(unsigned char *buf)
- {
-   unsigned char *ptbuf;
-   int i = 0;
-   ptbuf = buf;
-   while (((ptbuf[0] << 8) | ptbuf[1]) != 0xffda) {
-     if (i++ > 2048)
-       return 0;
-     if (((ptbuf[0] << 8) | ptbuf[1]) == 0xffc4)
-       return 1;
-     ptbuf++;
-   }
-   return 0;
- }
- 
- /******************************************************************************
- Description.: yuv2jpeg function is based on compress_yuyv_to_jpeg written by
-               Gabriel A. Devenyi.
-               It uses the destination manager implemented above to compress
-               YUYV data to JPEG. Most other implementations use the
-               "jpeg_stdio_dest" from libjpeg, which can not store compressed
-               pictures to memory instead of a file.
- Input Value.: video structure from v4l2uvc.c/h, destination buffer and buffersize
-               the buffer must be large enough, no error/size checking is done!
- Return Value: the buffer will contain the compressed data
- ******************************************************************************/
- void jpeg_to_rgb565(unsigned char *in_buffer, unsigned char *out_buffer, unsigned char *tmp_buffer, int size) 
- {
-   	struct jpeg_decompress_struct cinfo;
-   	struct jpeg_error_mgr jerr;
-   	JSAMPROW row_pointer[1];
-   	int i, j;
-   	int sizein;
- 	unsigned char *buf = in_buffer;
- 	unsigned char *ptdeb, *ptlimit, *ptcur;
- 	unsigned short *dest;
-   	unsigned char *src;
-   	if (!is_huffman(in_buffer)) {
-   		ptdeb = ptcur = buf;
- 	    ptlimit = in_buffer + size;
- 	    while ((((ptcur[0] << 8) | ptcur[1]) != 0xffc0) && (ptcur < ptlimit))
- 	      ptcur++;
- 	      	
- 	    if (ptcur >= ptlimit)
- 	        return;
- 	        
- 	    in_buffer = tmp_buffer;    
- 	    sizein = ptcur - ptdeb;
- 	
- 	    memcpy(tmp_buffer, buf, sizein);
- 		tmp_buffer += sizein;
- 	    memcpy(tmp_buffer, dht_data, sizeof(dht_data));
- 		tmp_buffer += sizeof(dht_data);
- 	    memcpy(tmp_buffer, ptcur, size - sizein);
- 	    
-     }
- 	cinfo.err = jpeg_std_error (&jerr);
-   	jpeg_create_decompress (&cinfo);
-   	
- 	jpeg_mem_src(&cinfo, in_buffer, size);
-   	jpeg_read_header(&cinfo, TRUE);
-   	cinfo.out_color_space = JCS_RGB;
-   	jpeg_start_decompress(&cinfo);
- 
-   	for(i=0; i<cinfo.output_height; i++)
- 	{
- 		row_pointer[0] = out_buffer+(i*cinfo.output_width*3);
-     	jpeg_read_scanlines(&cinfo, row_pointer, 1);
-   	}
- 
-   	jpeg_finish_decompress (&cinfo);
-   	jpeg_destroy_decompress (&cinfo);
- 
-   	dest = (unsigned short *)out_buffer;
-   	src = out_buffer;
-   	/* conver from RGB888 to RGB565 */
-   	for(i=0; i<cinfo.output_height; i++)
- 	{
- 		for(j=0; j<cinfo.output_width; j++)
- 		{
- 			*dest = (((*(src)) & 0xF8)<<8) | (((*(src+1)) & 0xFC)<< 3)  | (((*(src+2)) & 0xF8) >>3);			
- 			src+=3;
- 			dest++;
- 		}
- 	}
- 
- }
- 
- 
- 
- /**
-  * Initialize kernel frame buffer driver for data displaying.
-  *
-  * Screen is adjusted for 640x480 resolution. Kernel bufferers are
-  * memory mapped so this buffer can be passed to DSP directly
-  * since kernel buffers are contiguous.
-  */
- int init_framebuffer(struct framebuffer_info *fbinfo)
- {
-     int screensize;
-     int err;
-     printf("Opening FB device %s\n", fbinfo->device_name);
-     /* Open video display device */
-     fbinfo->fd = open(fbinfo->device_name, O_RDWR);
- 
-     if (fbinfo->fd == -1) {
-         printf("Error: Cannot open %s\n", fbinfo->device_name);
-         return -ENODEV;
-     }
- 
-     if (ioctl(fbinfo->fd, FBIOGET_VSCREENINFO, &varInfo) == -1) {
-         perror("Unable to get FB screen info ");
-         err = EINVAL;
-         goto cleanup_devnode;
-     }
- 
- 	printf("Frame buffer: %dx%d, %dbpp\n", varInfo.xres, varInfo.yres, varInfo.bits_per_pixel );
- 	screensize = varInfo.xres * varInfo.yres * varInfo.bits_per_pixel / 8;
- 		
-     fbinfo->userptr = (char *) mmap (NULL,
- 							screensize,
-                             PROT_READ | PROT_WRITE,
-                             MAP_SHARED,
-                             fbinfo->fd, 0);
- 
-     if (fbinfo->userptr == MAP_FAILED) {
-         perror("Failed to map FB memory ");
-         err = ENOMEM;
-         goto cleanup_devnode;
-     }
- 	printf("***** FB ptr = %x\n", fbinfo->userptr);
-     return 0;
- 
- cleanup_devnode:
- 	close(fbinfo->fd);
- 	return -err;
- }
- 
- int use_usr_ptr = 0;
- int video_output = 0;
- int video_mode = 0;
- int use_nonblock = 0;
- /*=============================================*/
- /* This function initializes capture device. It detects   *
-  * first input connected on the channel-0 and detects the *
-  * standard on that input. It, then, allocates buffers in *
-  * the driver's memory space and mmaps them in the        *
-  * application space.					  */
- static int initCapture(int *capture_fd, struct v4l2_format *fmt)
- {
- 	int ret, i;
- 	struct v4l2_requestbuffers reqbuf;
- 	struct v4l2_buffer buf;
- 	struct v4l2_input input;
- 	int input_idx;
- 	int found = 0;
-  	struct v4l2_control ctrl;
- 	struct v4l2_capability cap;
-     printf("Opening camera device %s\n", input_device);
- 	/* Open the channel-0 capture device */
- 	if(use_nonblock)
- 		*capture_fd = open((const char *)input_device, O_RDWR | O_NONBLOCK);
- 	else
- 		*capture_fd = open((const char *)input_device, O_RDWR);
- 	
- 	if (*capture_fd < 0) {
- 		printf("Error: Cannot open %s\n", input_device);
- 		return -1;
- 	}
- #if 0	/* go with the default size */
- 	ret = ioctl(*capture_fd, VIDIOC_S_STD, &input_std_id);
- 	if (ret < 0) {
- 		perror("VIDIOC_S_STD: Setting format to bayer VGA failed ");
- 		return -1;
- 	}
- #endif
-  
- 	ret = ioctl(*capture_fd, VIDIOC_QUERYCAP, &cap);
- 	if (ret < 0) {
-         perror("VIDIOC_QUERYCAP: Querying device failed ");
- 		return -1;
-     }
- 	if (!(cap.capabilities & V4L2_CAP_VIDEO_CAPTURE)) {
-         printf("Error: %s is not a video capture device\n", input_device);
- 		return -1;
-     }
- 	if (!(cap.capabilities & V4L2_CAP_STREAMING)) {
- 		printf("Error: %s does not support streaming i/o\n", input_device);
-         return -1;
-     }
-  	printf("Camera settings:\n");
- 	printf("\tCurrent dimensions: %dx%d\n", g_width, g_height);
- 	printf("\tImage format: ");
-     switch(g_pixelformat)
- 	{
- 	case V4L2_PIX_FMT_YUYV:
- 		printf("YUV");
- 		break;
- 	case V4L2_PIX_FMT_MJPEG:
- 		printf("MJPEG");
- 		break;
- 	default:
- 		printf("Unknown");
- 	}
-   	printf("\n\tHorizontal flip: %s\n", g_hflip?"enabled":"disabled");
- 	printf("\tVertical flip: %s\n", g_vflip?"enabled":"disabled");
- 	printf("\n\tImage X position: ");
- 	if(ux_start != -1)
- 		printf("%d", ux_start);
- 	else
- 		printf("center");
- 	printf("\n\tImage Y position: ");
- 	if(uy_start != -1)
- 		printf("%d", uy_start);
- 	else
- 		printf("center");
- 	printf("\n");
- 	
- 	printf("\n\tVidoe mode: %s\n", video_mode?"Interlaced": "Any");
- 
- 	CLEAR(*fmt);
- 	fmt->type = video_output?V4L2_BUF_TYPE_VIDEO_OUTPUT:V4L2_BUF_TYPE_VIDEO_CAPTURE;
- 	fmt->fmt.pix.width = g_width;
- 	fmt->fmt.pix.height = g_height;
- 	fmt->fmt.pix.pixelformat = g_pixelformat;
- 	fmt->fmt.pix.field = video_mode?V4L2_FIELD_INTERLACED:V4L2_FIELD_ANY;
- 	ret = ioctl(*capture_fd, VIDIOC_S_FMT, fmt);
- 	if (ret < 0)
- 	{
- 		perror("Unable to set format ");
- 		return -1;
- 	}
- 	if (fmt->fmt.pix.width != g_width || fmt->fmt.pix.height != g_height)
- 	{
- 		printf("Dimentions asked (%dx%d) unavailable, setting dimentions to: %dx%d\n", g_width, g_height, fmt->fmt.pix.width, fmt->fmt.pix.height);
- 		g_width = fmt->fmt.pix.width;
- 		g_height = fmt->fmt.pix.height;
- 	}
- 
- 	g_buffer_size = fmt->fmt.pix.sizeimage;
- 	printf("***Buffer size = %d\n", g_buffer_size);
- 
- 	/* set framerate */
- 	struct v4l2_streamparm setfps;
- 	memset(&setfps, 0, sizeof(struct v4l2_streamparm));
- 	setfps.type = video_output?V4L2_BUF_TYPE_VIDEO_OUTPUT:V4L2_BUF_TYPE_VIDEO_CAPTURE;
- 	setfps.parm.capture.timeperframe.numerator = 1;
- 	setfps.parm.capture.timeperframe.denominator = g_fps;
- 	ret = ioctl(*capture_fd, VIDIOC_S_PARM, &setfps);
- 	if (ret < 0) {	
- 		perror("Unable to set frame rate ");
- 	}
- 
- #if 0
- 	/* flip */
- 	ctrl.id = V4L2_CID_HFLIP;	 
- 	ctrl.value = g_hflip;
- 	ret = ioctl(*capture_fd, VIDIOC_S_CTRL, &ctrl);
- 	if (ret < 0) {
- 		perror("Unable to set Horizontal flip ");
- 	}
- 	
- 	ctrl.id = V4L2_CID_VFLIP;	 
- 	ctrl.value = g_vflip;
- 	ret = ioctl(*capture_fd, VIDIOC_S_CTRL, &ctrl);
- 	if (ret < 0) {
- 		perror("Unable to set Vertical flip ");
- 	}
- #endif
- 	/* Buffer allocation
- 		* Buffer can be allocated either from capture driver or
- 		* user pointer can be used
- 		*/
- 	/* Request for 3 or 4 input buffers. As far as Physically contiguous
- 		* memory is available, driver can allocate as many buffers as
- 		* possible. If memory is not available, it returns number of
- 		* buffers it has allocated in count member of reqbuf.
- 		* HERE count = number of buffer to be allocated.
- 		* type = type of device for which buffers are to be allocated.
- 		* memory = type of the buffers requested i.e. driver allocated or
- 		* user pointer */
- 	CLEAR(reqbuf);
- 	reqbuf.count = g_numbuffers;
- 	reqbuf.type = video_output?V4L2_BUF_TYPE_VIDEO_OUTPUT:V4L2_BUF_TYPE_VIDEO_CAPTURE;
- 		
- 	if(!use_usr_ptr)
- 	{
- 		reqbuf.memory = V4L2_MEMORY_MMAP;
- 	}
- 	else
- 	{
- 		reqbuf.memory = V4L2_MEMORY_USERPTR;
- 	}
- 
- 	ret = ioctl(*capture_fd, VIDIOC_REQBUFS, &reqbuf);
- 	if (ret < 0) {
- 		perror("Unable to allocate buffers ");
- 		return -1;
- 	}
- 
- 	/* Store the number of buffers actually allocated */
- 	g_numbuffers = reqbuf.count;
- 
- 	printf("***ACtailt buffers allocated = %d %d\n", g_numbuffers, g_fps);
- 	if(!use_usr_ptr)
- 	{
- 		/* map the buffers */
- 		for (i=0; i<g_numbuffers; i++)
- 		{
- 			CLEAR(buf);
- 			/* Query physical address of the buffers */
- 			buf.type = video_output?V4L2_BUF_TYPE_VIDEO_OUTPUT:V4L2_BUF_TYPE_VIDEO_CAPTURE;
- 			buf.index = i;
- 			buf.memory = V4L2_MEMORY_MMAP;
- 			ret = ioctl(*capture_fd, VIDIOC_QUERYBUF, &buf);
- 			if (ret < 0) {
- 				perror("Unable to query buffer ");
- 				return -1;
- 			}
- 			capture_buff_info[i].length = buf.length;
- 			capture_buff_info[i].index = i;
- 			capture_buff_info[i].start = mmap(NULL,	/* start anywhere */
- 						buf.length, PROT_READ, MAP_SHARED, *capture_fd, buf.m.offset);
- 	
- 			if (capture_buff_info[i].start == MAP_FAILED) {
- 				printf("mmap: Unable to map buffer %d\n", i);
- 				return -1;
- 			}
- 		}
- 	}
- 	else
- 	{
- 		/* allocate the buffers */
- 		for (i=0; i<g_numbuffers; i++)
- 		{
- 			capture_buff_info[i].start = malloc(g_buffer_size);
- 			if(!capture_buff_info[i].start)
- 			{
- 				perror("Out of memory;couldn't allocate buffer ");
- 				return -1;
- 			}
- 			capture_buff_info[i].length = g_buffer_size;
- 			capture_buff_info[i].index = i;
- 		}
- 	}
- 	/* Queue buffers
- 		* Before starting streaming, all the buffers needs to be en-queued
- 		* in the driver incoming queue. These buffers will be used by the
- 		* drive for storing captured frames. */
- 	/* Enqueue buffers */
- 	/* Queue buffers
- 		* Before starting streaming, all the buffers needs to be en-queued
- 		* in the driver incoming queue. These buffers will be used by the
- 		* drive for storing captured frames. */
- 	/* Enqueue buffers */
- 	for (i=0; i<g_numbuffers; i++)
- 	{
- 		CLEAR(buf);
- 		buf.type = video_output?V4L2_BUF_TYPE_VIDEO_OUTPUT:V4L2_BUF_TYPE_VIDEO_CAPTURE;
- 		buf.index = i;
- 		if(!use_usr_ptr)
- 		{
- 			buf.memory = V4L2_MEMORY_MMAP;
- 		}
- 		else
- 		{
- 			buf.memory = V4L2_MEMORY_USERPTR;
- 			buf.m.userptr = capture_buff_info[i].start;
- 			buf.length = capture_buff_info[i].length;
- 		}
- 		ret = ioctl(*capture_fd, VIDIOC_QBUF, &buf);
- 		if (ret < 0) 
- 		{
- 			printf("Unable to queue buffer %d\n", i);
- 			return -1;
- 		}
- 	}
- 	return 0;
- }
- 
- /*=====================startCapture========================*/
- /* This function starts streaming on the capture device	   */
- static int startCapture(int *capture_fd)
- {
- 	int a = video_output?V4L2_BUF_TYPE_VIDEO_OUTPUT:V4L2_BUF_TYPE_VIDEO_CAPTURE, ret;
- 	/* Here type of device to be streamed on is required to be passed */
- 	ret = ioctl(*capture_fd, VIDIOC_STREAMON, &a);
- 	if (ret < 0) {
- 		perror("Unable to start capture ");
- 		return -1;
- 	}
- 	return 0;
- }
- 
- 
- 
- /*=====================getCaptureBuffer====================*/
- /* This function de-queues captured buffer from the 	   *
-  * capture device's outgoing queue. 			   */
- static int getCaptureBuffer(int *capture_fd)
- {
- 	int ret;
- 	int i;
- 	/* It is better to zero members of v4l2_buffer structure */
- 	memset(&g_capture_buf, 0, sizeof(g_capture_buf));
- 	g_capture_buf.type = video_output?V4L2_BUF_TYPE_VIDEO_OUTPUT:V4L2_BUF_TYPE_VIDEO_CAPTURE;
- 	if(!use_usr_ptr)
- 	{
- 		g_capture_buf.memory = V4L2_MEMORY_MMAP;
- 		/* Dequeue buffer
- 		 * VIDIOC_DQBUF ioctl de-queues a captured buffer from driver.
- 		 * This call can be blocking or non blocking. For blocking call, it
- 		 * blocks untill a capture frame is available. For non-blocking call,
- 		 * it returns instantaneously with success or error depending on
- 		 * captured buffer is available or not. */
- 		printf("***Calling IOCTL VIDIOC_DQBUF %x\n", VIDIOC_DQBUF);
- 		while(1)
- 		{
- #if 0
- 			 fd_set fds;
-                         struct timeval tv;
-                         int r;
- 
-                         FD_ZERO(&fds);
-                         FD_SET(*capture_fd, &fds);
- 
-                         /* Timeout. */
-                         tv.tv_sec = 2;
-                         tv.tv_usec = 0;
- 
-                         r = select(*capture_fd + 1, &fds, NULL, NULL, &tv);
- 						 if (-1 == r) {
-                                 if (EINTR == errno)
-                                         continue;
-                                 perror("***Select Error: ");
- 								return -1;
-                         }
- 
-                         if (0 == r) {
-                                 perror("select timeout: ");
-                                continue;
-                         }
- #endif
- 			ret = ioctl(*capture_fd, VIDIOC_DQBUF, &g_capture_buf);
- 			
- 			if (ret < 0) {
- 				if(use_nonblock && errno == EAGAIN)
- 				{
- 					printf("****continuing\n");
- 					continue;
- 				}
- 				perror("Unable to de-queue buffer ");
- 				return -1;
- 			}
- 			if(g_capture_buf.index >= MAX_BUFFERS)
- 			{
- 				perror("De-queue buffer mismatch ");
- 				return -1;
- 			}
- 			printf("***GOt frame\n");
- 			return 0;
- 		}
- 	}
- 	
- 	g_capture_buf.memory = V4L2_MEMORY_USERPTR;
- 	/* Dequeue buffer
- 		* VIDIOC_DQBUF ioctl de-queues a captured buffer from driver.
- 		* This call can be blocking or non blocking. For blocking call, it
- 		* blocks untill a capture frame is available. For non-blocking call,
- 		* it returns instantaneously with success or error depending on
- 		* captured buffer is available or not. */
- 	printf("***Calling IOCTL VIDIOC_DQBUF %x\n", VIDIOC_DQBUF);
- 	ret = ioctl(*capture_fd, VIDIOC_DQBUF, &g_capture_buf);
- 	if (ret < 0) {
- 		perror("Unable to de-queue buffer ");
- 		return -1;
- 	}
- 	for(i=0; i<MAX_BUFFERS; i++)
- 	{
- 		if(capture_buff_info[i].start == g_capture_buf.m.userptr
- 			&& g_capture_buf.length == capture_buff_info[i].length)
- 			return 0;
- 	}
- 	perror("De-queue buffer mismatch ");
- 	return -1;
- }
- 
- 
- /*=====================putCaptureBuffer====================*/
- /* This function en-queues empty buffer into the 	   *
-  * capture device's incoming queue. 			   */
- static int putCaptureBuffer(int *capture_fd)
- {
- 	int ret;
- 	ret = ioctl(*capture_fd, VIDIOC_QBUF, &g_capture_buf);
- 	if (ret < 0) {
- 		perror("Unable to queue buffer during capture ");
- 		return ret;
- 	}
- 	return 0;
- }
- /*=====================stopCapture========================*/
- /* This function stops streaming on the capture device	  */
- static int stopCapture(int *capture_fd)
- {
- 	int ret, a = video_output?V4L2_BUF_TYPE_VIDEO_OUTPUT:V4L2_BUF_TYPE_VIDEO_CAPTURE;
- 	/* Here type of device to be streamed off is required to be passed */
- 	ret = ioctl(*capture_fd, VIDIOC_STREAMOFF, &a);
- 	if (ret < 0) {
- 		perror("Unable to stop capture ");
- 		return -1;
- 	}
- 	return 0;
- }
- 
- /*=====================releaseCapture========================*/
- /* This function un-maps all the mmapped buffers of capture  *
-  * and closes the capture file handle			     */
- static void releaseCapture(int *capture_fd)
- {
- 	int i;
- 	if(!use_usr_ptr)
- 	{
- 		/* Un-map the buffers */
- 		for (i = 0; i < g_numbuffers; i++) {
- 			munmap(capture_buff_info[i].start, capture_buff_info[i].length);
- 		}
- 	}
- 	else
- 	{
- 		for (i = 0; i < g_numbuffers; i++) {
- 			if(capture_buff_info[i].start){
- 				free(capture_buff_info[i].start);
- 			}
- 		}
- 	}
- 	/* Close the file handle */
- 	close(*capture_fd);
- 	*capture_fd = 0;
- }
- 
- #ifdef _USE_TP_EVENT_
- char g_tp_pressed = 0;
- void *Thread_TP_event(void *threadid)
- {
- 	int rd;
- 	int fd = open(TP_EVENT_DEVICE, O_RDONLY);;
- 	if (fd == -1) {
- 		printf("Unable to open event device %s\n", TP_EVENT_DEVICE);
- 		goto _out;
- 	}
- 	struct input_event ev;
- 	rd = read(fd, &ev, sizeof(struct input_event));
- 	if (rd < (int) sizeof(struct input_event)) {
- 		printf("\nevtest: error reading");
- 		goto _out;
- 	}
- 	printf("TP Event: 2x\n");
- _out:
- 	g_tp_pressed = 1;
- 	pthread_exit(0);
- }
- #else
- struct termios orig_tio, new_tio;
- void saveOrigTTYsettings()
- {
- 	 tcgetattr(0, &orig_tio);
- }
- void restoreOrigTTYsettings()
- {
- 	 tcsetattr(0, TCSANOW, &orig_tio);
- }
- 
- _Bool kbhit(u_char *ch)
- {
-     return read(0,ch,1)?1:0;
- }
- 
- void setKbhitMode()
- {
- 	memcpy(&new_tio, &orig_tio, sizeof(struct termios));
- 	new_tio.c_cc[VMIN]=0;
-     new_tio.c_lflag &= ~ICANON;
-     new_tio.c_lflag &= ~ECHO;
-     new_tio.c_lflag &= ~ISIG;
- //    new_tio.c_cc[VMIN] = 1;
-     new_tio.c_cc[VTIME] = 0;
-     tcsetattr(0, TCSANOW, &new_tio);
- }
- #endif
- 
- void fill_frame_buffer(int x_start, int y_start, int x_max, int y_max, unsigned short *image_buf, unsigned short *fb_addr)
- {
- 	int y;
- 	fb_addr += x_start+(y_start*varInfo.xres);
- 	for(y=0; y<y_max; y++)
- 	{
- 		memcpy(fb_addr, image_buf, x_max*2);
- 		fb_addr += varInfo.xres;
- 		image_buf += g_width;
- 	}
- }
- 			
- /*=====================app_main===========================*/
- int app_main()
- {
- 	int i = 0;
- 	void *capturebuffer;
- 	int counter = 1;
- 	int ret = 0;
- 	int rc;
- 	struct v4l2_format capture_fmt;
- 	int capture_fd=-1;
- 	u_char ch;
- 	unsigned short *orig_fb_Addr;
- 	int max_x, max_y;
- 	int image_divider;
- 	
- 	for (i = 0; i < MAX_BUFFERS; i++) {
- 		capture_buff_info[i].start = NULL;
- 	}
- 	g_numbuffers = MAX_BUFFERS;
- 	pthread_t threads;
- 	/* initilaizer Frame buffer */
- 	fbinfo.fd = -1;
- 	fbinfo.device_name = (char *)"/dev/fb0";
- 	if (init_framebuffer(&fbinfo) != 0)
- 		return -ENODEV;
- 	
- 	printf("Framebuffer init successful\n");
- 	
- 	/* open capture channel 0 */
- 	ret = initCapture(&capture_fd, &capture_fmt);
- 	if (ret < 0) {
- 		goto _out;
- 	}
- 	
- 	if(ux_start != -1 && (ux_start < 0 || ux_start >= varInfo.xres))
- 	{
- 		printf("Invalid X coordinated specified\nMax value = %d",varInfo.xres-1);
- 		ret = -1;
- 		goto _out;
- 	}
- 	if(uy_start != -1 && (uy_start < 0 || uy_start >= varInfo.yres))
- 	{
- 		printf("Invalid Y coordinated specified\nMax value = %d",varInfo.yres-1);
- 		ret = -1;
- 		goto _out;
- 	}
- 	
- 	orig_fb_Addr = (unsigned short *)fbinfo.userptr;
- 	image_divider = 1;		/* VGA */
- 	if(ux_start == -1)
- 	{
- 		x_start = (varInfo.xres/2)-(capture_fmt.fmt.pix.width/(image_divider*2));
- 	}
- 	else
- 	  	x_start = ux_start;
- 	if(uy_start == -1)
- 	{
- 		y_start = (varInfo.yres/2)-(capture_fmt.fmt.pix.height/(image_divider*2));
- 	}
- 	else
- 	  	y_start = uy_start;
- 	if(x_start<0)
- 		x_start = 0;
- 	if(y_start<0)
- 		y_start = 0;
- 	
- 	if(capture_fmt.fmt.pix.width/image_divider < (varInfo.xres-x_start))
- 		max_x = capture_fmt.fmt.pix.width/image_divider;
- 	else
- 		max_x = varInfo.xres-x_start;
- 	if(capture_fmt.fmt.pix.height/image_divider < (varInfo.yres-y_start))
- 		max_y = capture_fmt.fmt.pix.height/image_divider;
- 	else
- 		max_y = varInfo.yres-y_start;
- 	/* adjust the frame buffer pointer */
- 	orig_fb_Addr += x_start+(y_start*varInfo.xres);
- #ifdef _USE_TP_EVENT_
- 	g_tp_pressed = 0;
- 	rc = pthread_create(&threads, NULL, Thread_TP_event, 0);
-     if (rc){
-          printf("ERROR; return code from pthread_create() is %d\n", rc);
-          goto _out;
-     }
- #else
- 	saveOrigTTYsettings();
- 	setKbhitMode();
- #endif
- 	printf("Capture initialized, displaying image at (%d,%d)\n", x_start, y_start);
- 	/* start capturing for channel 0 */
- 	ret = startCapture(&capture_fd);
- 	if (ret < 0) {
- 		printf("Error in starting capturing for channel 0\n");
- 		goto _out;
- 	}
- 	printf("Capturing frames\n");
- 	/* One buffer is dequeued from the capture channel.
- 	 * Capture buffer will be modified and copied to the frame buffer.
- 	 * This sequence is repeated in loop.
- 	 * */
- 	while (1) 
- 	{
- #ifdef _USE_TP_EVENT_
- 		if(g_tp_pressed)
- 			break;
- #else	
- 		if(kbhit(&ch)==1)
- 		{
- 			//if(ch=='q')
- 				break;
- 		}
- #endif
- 		printf("Capturing frames\n");
- 		/* get capturing buffer for channel 0 */
- 		if (getCaptureBuffer(&capture_fd) < 0) {
- 			printf("Error in get capture buffer for channel 0\n");
- 			break;
- 		}
- 		capturebuffer = capture_buff_info[g_capture_buf.index].start;
- 		if (save_frame == counter) {
- 			printf("Writing to file, %d bytes\n", g_capture_buf.bytesused);
- 			fwrite(capturebuffer, 1, g_capture_buf.bytesused,
- 				file_fp);
- 			fclose(file_fp);
- 			printf("Done..\n");
- 		}
- 		if(g_pixelformat==V4L2_PIX_FMT_YUYV)
- 		{
- 			printf("***Pixel format YUV\n");
- 			compress_yuyv_to_rgb565(capturebuffer, temp_buffer);
- 			fill_frame_buffer(x_start, y_start, max_x, max_y, temp_buffer, fbinfo.userptr);
- 		}
- 		else if(g_pixelformat==V4L2_PIX_FMT_MJPEG)
- 		{
- 			unsigned short *fb_Addr = fbinfo.userptr;
- 			unsigned short *file_buf = temp_buffer;
- 			int y;
- 			printf("***Pixel format V4L2_PIX_FMT_MJPEG\n");
- 			jpeg_to_rgb565(capturebuffer, temp_buffer, temp_buffer2, g_capture_buf.bytesused);
- 			fill_frame_buffer(x_start, y_start, max_x, max_y, temp_buffer, fbinfo.userptr);
- 		}
- 		printf("***Putting buffer\n");
- 		/* put buffers in capture channels */
- 		ret = putCaptureBuffer(&capture_fd);
- 		if (ret < 0) {
- 			printf("Error in put capture buffer for channel 0\n");
- 			break;
- 		}
- 		counter++;
- 	}
- #ifdef _USE_TP_EVENT_
- 	if(!g_tp_pressed)
- 		pthread_cancel(threads);
- #else
- 	restoreOrigTTYsettings();
- #endif	
- 	printf("Stopping capture/display\n");
- 	/* stop capturing for channel 0 */
- 	ret = stopCapture(&capture_fd);
- 	if (ret < 0) {
- 		printf("Error in stopping capturing for channel 0\n");
- 	}
- _out:
- 	
- 	close(fbinfo.fd);
- 	if(capture_fd>=0)
- 	{
- 		/* close capture channel 0 */
- 		releaseCapture(&capture_fd);
- 	}
- 	/* Free section
- 	 * Here channels for capture and display are close.
- 	 * */
- 	return ret;
- }
- 
- /******************************************************************************
- Description.: 
- Input Value.: 
- Return Value: 
- ******************************************************************************/
- void daemon_mode(void) {
-   int fr=0;
- 
-   fr = fork();
-   if( fr < 0 ) {
-     fprintf(stderr, "fork() failed\n");
-     exit(1);
-   }
-   if ( fr > 0 ) {
-     exit(0);
-   }
- 
-   if( setsid() < 0 ) {
-     fprintf(stderr, "setsid() failed\n");
-     exit(1);
-   }
- 
-   fr = fork();
-   if( fr < 0 ) {
-     fprintf(stderr, "fork() failed\n");
-     exit(1);
-   }
-   if ( fr > 0 ) {
-     fprintf(stderr, "forked to background (%d)\n", fr);
-     exit(0);
-   }
- 
-   umask(0);
- 
-   chdir("/");
-   close(0);
-   close(1);
-   close(2);
- 
-   open("/dev/null", O_RDWR);
-   dup(0);
-   dup(0);
- }
- 
- void help(char *app_name)
- {
- 	printf("%s -d [device path] -f [0/1] -x [x coordinate] -y [y coordinate] -h [0/1] -v [0/1] -u [0/1] -w [Frame number] -b [0/1]\n", app_name);
- 	printf("\t-d - Camera device path ("CAPTURE_DEVICE")\n");
- 	printf("\t-f - Image format (1) \n\t\t0: YUV\n\t\t1: MJPEG\n");
- 	printf("\t-x - Move image to the specified X coordinate\n\t-y - Move image to the specified Y coordinate\n");
- 	printf("\t-h - Disable/enable horizontal flip\n\t-v - Disable/enable vertical flip\n");
- 	printf("\t-u - Buffer to use\n");
- 	printf("\t\t 1 - Use user space buffer\n\t\t 0 - Use buffer allocated by the driver\n");
- 	printf("\t-o - Buffer type\n");
- 	printf("\t\t 1 - Video output buffer\n\t\t 0 - Video capture buffer\n");
- 	printf("\t-m - Mode\n");
- 	printf("\t\t 1 - Interlaced mode\n\t\t 0 - Any mode\n");
- 	printf("\t-n - Blocking/nonblocking mode\n");
- 	printf("\t\t 1 - Non blocking mode\n\t\t 0 - Blocking mode\n");
- 	printf("\t-a - Width\n");
- 	printf("\t-c - Height\n");
- 	printf("\t-w - Save frame to file \"%s\"\n", FRAME_CAPTURE_FILE);
- 	printf("\t\t 0 - Donot save frame\n\t\t 1~n - Saves the frame 'n'\n");
- 	printf("\t-d - Execute in background\n\t\t1 - Run in background\n\t\t0 - Run in foreground\n");
- }
- 
- /******************************************************************************
- 				Program Main
- *******************************************************************************/
- int main(int argc, char *argv[])
- {
- 	int ret = 0, i, d, index;
- 	char shortoptions[] = "d:x:y:w:h:v:f:d:u:o:m:n:a:c:";
- 	int temp;
- 	int daemon = 0;
- 	char filename[256], buf[256];
- 	int fd;
- 
- 	/* capture device auto select */
- 	strcpy(input_device, CAPTURE_DEVICE);	/* default capture device */
- 	for( i = 0 ; i < 16 ; i++ ) {
- 		sprintf(filename, "/sys/class/video4linux/video%d/name",i);
- 		if( 0 > (fd=open(filename,O_RDONLY)) ) {
- 			break;
- 		} else {
- 			read(fd, buf, sizeof(buf));
- 			close(fd);
- 			if( 0 == strncmp(buf, "UVC Camera", strlen("UVC Camera")) ) {
- 				sprintf(input_device, "/dev/video%d", i);
- 				break;
- 			}
- 		}
- 	}
- 
- 	for (;;) {
- 		d = getopt_long(argc, argv, shortoptions, (void *)NULL, &index);
- 		if (-1 == d)
- 		{
- 			break;
- 		}
- 		switch (d) {
- 		case 'd':
- 			strcpy(input_device, optarg);
- 			break;
- 		case 'w':
- 			save_frame = atoi(optarg);
- 			break;
- 		case 'x':
- 			temp = atoi(optarg);
- 			ux_start = temp;
- 			break; 
- 		case 'y':
- 			temp = atoi(optarg);
- 			uy_start = temp;
- 			break;
- 		case 'f':
- 			temp = atoi(optarg); 
- 			switch(temp)
- 			{
- 			case 0:
- 				g_pixelformat = V4L2_PIX_FMT_YUYV;
- 				break;
- 			case 1:
- 				g_pixelformat = V4L2_PIX_FMT_MJPEG;
- 				break;
- 			default:
- 				printf("Invalid operand for \"-f\"\nValue should be >=0 and <=1\n");
- 				goto _exit;
- 			}
- 			break;
- 		case 'h':
- 			/* horizontal flip */
- 			temp = atoi(optarg); 
- 			if(temp)
- 				g_hflip = 1;
- 			else
- 				g_hflip = 0;
- 			break;
- 		case 'v':
- 			/* vertical flip */
- 			temp = atoi(optarg); 
- 			if(temp)
- 				g_vflip = 1;
- 			else
- 				g_vflip = 0;
- 			break;
- 		case 'u':
- 			/* vertical flip */
- 			temp = atoi(optarg); 
- 			if(temp)
- 				use_usr_ptr = 1;
- 			else
- 				use_usr_ptr = 0;
- 			break;
- 		case 'o':
- 			/* vertical flip */
- 			temp = atoi(optarg); 
- 			if(temp)
- 				video_output = 1;
- 			else
- 				video_output = 0;
- 			break;
- 		case 'm':
- 			/* vertical flip */
- 			temp = atoi(optarg); 
- 			if(temp)
- 				video_mode = 1;
- 			else
- 				video_mode = 0;
- 			break;
- 		case 'n':
- 			/* vertical flip */
- 			temp = atoi(optarg); 
- 			if(temp)
- 				use_nonblock = 1;
- 			else
- 				use_nonblock = 0;
- 			break;
- 		case 'a':
- 			/* vertical flip */
- 			g_width = atoi(optarg); 
- 			break;
- 		case 'c':
- 			/* vertical flip */
- 			g_height = atoi(optarg); 
- 			break;
- 		case 'b':
- 			daemon = atoi(optarg);
- 			break;
- 		default:
- _exit:
- 			help(argv[0]);
- 			exit(1);
- 		}
- 	}
- 	if(daemon)
- 		daemon_mode();
- 
- 	if (save_frame) {
- 		printf("Opening file %s for saving frame %d\n", FRAME_CAPTURE_FILE, save_frame);
- 		file_fp = fopen(FRAME_CAPTURE_FILE, "wb");
- 		if (file_fp == NULL) {
- 			printf("Unable to open \"%s\"\n", FRAME_CAPTURE_FILE);
- 			exit(1);
- 		}
- 	}
- 	app_main();
- 	return 0;
- }
- 
--- 0 ----
diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/common/samples/yuv_usb_cam_app/yuv_usb_cam_app.c buildroot-2013.08.1-ckb-20141129-1/board/ckb/common/samples/yuv_usb_cam_app/yuv_usb_cam_app.c
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/common/samples/yuv_usb_cam_app/yuv_usb_cam_app.c	2014-06-26 10:55:19.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/common/samples/yuv_usb_cam_app/yuv_usb_cam_app.c	1970-01-01 09:00:00.000000000 +0900
***************
*** 1,932 ****
- /***************************************************************************
-  *   v4l2grab Version 0.1                                                  *
-  *   Copyright (C) 2009 by Tobias Müller                                   *
-  *   Tobias_Mueller@twam.info                                              *
-  *                                                                         *
-  *   based on V4L2 Specification, Appendix B: Video Capture Example        *
-  *   (http://v4l2spec.bytesex.org/spec/capture-example.html)               *
-  *                                                                         *
-  *   This program is free software; you can redistribute it and/or modify  *
-  *   it under the terms of the GNU General Public License as published by  *
-  *   the Free Software Foundation; either version 2 of the License, or     *
-  *   (at your option) any later version.                                   *
-  *                                                                         *
-  *   This program is distributed in the hope that it will be useful,       *
-  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
-  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
-  *   GNU General Public License for more details.                          *
-  *                                                                         *
-  *   You should have received a copy of the GNU General Public License     *
-  *   along with this program; if not, write to the                         *
-  *   Free Software Foundation, Inc.,                                       *
-  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
-  ***************************************************************************/
- //#define IO_READ
- #define IO_MMAP
- //#define IO_USERPTR
- 
- #if !defined(IO_READ) && !defined(IO_MMAP) && !defined(IO_USERPTR)
- #error You have to include one of IO_READ, IO_MMAP oder IO_USERPTR!
- #endif
- 
- #include <stdio.h>
- #include <stdlib.h>
- #include <string.h>
- #include <assert.h>
- #include <getopt.h>
- #include <fcntl.h>
- #include <unistd.h>
- #include <errno.h>
- #include <malloc.h>
- #include <sys/stat.h>
- #include <sys/types.h>
- #include <sys/time.h>
- #include <sys/mman.h>
- #include <sys/ioctl.h>
- #include <asm/types.h>
- #include <linux/videodev2.h>
- #include <jpeglib.h>
- 
- #define CLEAR(x) memset (&(x), 0, sizeof (x))
- 
- 
- typedef enum {
- #ifdef IO_READ
-         IO_METHOD_READ,
- #endif
- #ifdef IO_MMAP
-         IO_METHOD_MMAP,
- #endif
- #ifdef IO_USERPTR
-         IO_METHOD_USERPTR,
- #endif
- } io_method;
- 
- struct buffer {
-         void *                  start;
-         size_t                  length;
- };
- 
- #ifdef IO_MMAP
- static io_method        io              = IO_METHOD_MMAP;
- #endif
- 
- static int              fd              = -1;
- struct buffer *         buffers         = NULL;
- static unsigned int     n_buffers       = 0;
- 
- // global settings
- static unsigned int width = 640;
- static unsigned int height = 480;
- static unsigned char jpegQuality = 70;
- static char* jpegFilename = NULL;
- int g_timeout = 5;
- static char* deviceName = "/dev/video0";
- 
- /**
-   Convert from YUV422 format to RGB888. Formulae are described on http://en.wikipedia.org/wiki/YUV
- 
-   \param width width of image
-   \param height height of image
-   \param src source
-   \param dst destination
- */
- static void YUV422toRGB888(int width, int height, unsigned char *src, unsigned char *dst)
- {
-   int line, column;
-   unsigned char *py, *pu, *pv;
-   unsigned char *tmp = dst;
- 
-   /* In this format each four bytes is two pixels. Each four bytes is two Y's, a Cb and a Cr. 
-      Each Y goes to one of the pixels, and the Cb and Cr belong to both pixels. */
-   py = src;
-   pu = src + 1;
-   pv = src + 3;
- 
-   #define CLIP(x) ( (x)>=0xFF ? 0xFF : ( (x) <= 0x00 ? 0x00 : (x) ) )
- 
-   for (line = 0; line < height; ++line) {
-     for (column = 0; column < width; ++column) {
-       *tmp++ = CLIP((double)*py + 1.402*((double)*pv-128.0));
-       *tmp++ = CLIP((double)*py - 0.344*((double)*pu-128.0) - 0.714*((double)*pv-128.0));      
-       *tmp++ = CLIP((double)*py + 1.772*((double)*pu-128.0));
- 
-       // increase py every time
-       py += 2;
-       // increase pu,pv every second time
-       if ((column & 1)==1) {
-         pu += 4;
-         pv += 4;
-       }
-     }
-   }
- }
- 
- /**
-   Print error message and terminate programm with EXIT_FAILURE return code.
-   \param s error message to print
- */
- static void errno_exit(const char* s)
- {
-   fprintf(stderr, "%s error %d, %s\n", s, errno, strerror (errno));
-   exit(EXIT_FAILURE);
- }
- 
- /**
-   Do ioctl and retry if error was EINTR ("A signal was caught during the ioctl() operation."). Parameters are the same as on ioctl.
- 
-   \param fd file descriptor
-   \param request request
-   \param argp argument
-   \returns result from ioctl
- */
- static int xioctl(int fd, int request, void* argp)
- {
-   int r;
- 
-   do r = ioctl(fd, request, argp);
-   while (-1 == r && EINTR == errno);
- 
-   return r;
- }
- 
- /**
-   Write image to jpeg file.
- 
-   \param img image to write
- */
- static void jpegWrite(unsigned char* img)
- {
-   struct jpeg_compress_struct cinfo;
-   struct jpeg_error_mgr jerr;
- 	
-   JSAMPROW row_pointer[1];
-   FILE *outfile = fopen( jpegFilename, "wb" );
- 
-   // try to open file for saving
-   if (!outfile) {
-     errno_exit("jpeg");
-   }
- 
-   // create jpeg data
-   cinfo.err = jpeg_std_error( &jerr );
-   jpeg_create_compress(&cinfo);
-   jpeg_stdio_dest(&cinfo, outfile);
- 
-   // set image parameters
-   cinfo.image_width = width;	
-   cinfo.image_height = height;
-   cinfo.input_components = 3;
-   cinfo.in_color_space = JCS_RGB;
- 
-   // set jpeg compression parameters to default
-   jpeg_set_defaults(&cinfo);
-   // and then adjust quality setting
-   jpeg_set_quality(&cinfo, jpegQuality, TRUE);
- 
-   // start compress 
-   jpeg_start_compress(&cinfo, TRUE);
- 
-   // feed data
-   while (cinfo.next_scanline < cinfo.image_height) {
-     row_pointer[0] = &img[cinfo.next_scanline * cinfo.image_width *  cinfo.input_components];
-     jpeg_write_scanlines(&cinfo, row_pointer, 1);
-   }
- 
-   // finish compression
-   jpeg_finish_compress(&cinfo);
- 
-   // destroy jpeg data
-   jpeg_destroy_compress(&cinfo);
- 
-   // close output file
-   fclose(outfile);
- }
- 
- /**
-   process image read
- */
- static void imageProcess(const void* p)
- {
-   unsigned char* src = (unsigned char*)p;
-   unsigned char* dst = malloc(width*height*3*sizeof(char));
- 
-   // convert from YUV422 to RGB888
-   YUV422toRGB888(width,height,src,dst);
- 
-   // write jpeg
-   jpegWrite(dst);
- }
- 
- /**
-   read single frame
- */
- 
- static int frameRead(void)
- {
-   struct v4l2_buffer buf;
- #ifdef IO_USERPTR
-   unsigned int i;
- #endif
- 
-   switch (io) {
- #ifdef IO_READ
-     case IO_METHOD_READ:
-       if (-1 == read (fd, buffers[0].start, buffers[0].length)) {
-         switch (errno) {
-           case EAGAIN:
-             return 0;
- 
-           case EIO:
-             // Could ignore EIO, see spec.
- 
-             // fall through
-           default:
-             errno_exit("read");
-         }
-       }
- 
-       imageProcess(buffers[0].start);
-       break;
- #endif
- 
- #ifdef IO_MMAP
-     case IO_METHOD_MMAP:
-       CLEAR (buf);
- 
-       buf.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
-       buf.memory = V4L2_MEMORY_MMAP;
- 
-       if (-1 == xioctl(fd, VIDIOC_DQBUF, &buf)) {
-         switch (errno) {
-           case EAGAIN:
-             return 0;
- 
-           case EIO:
-              // Could ignore EIO, see spec
- 
-              // fall through
-           default:
-             errno_exit("VIDIOC_DQBUF");
-         }
-       }
- 
-       assert (buf.index < n_buffers);
- 
-       imageProcess(buffers[buf.index].start);
- 
-       if (-1 == xioctl(fd, VIDIOC_QBUF, &buf))
-         errno_exit("VIDIOC_QBUF");
- 
-       break;
- #endif
- 
- #ifdef IO_USERPTR
-     case IO_METHOD_USERPTR:
-       CLEAR (buf);
- 
-       buf.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
-       buf.memory = V4L2_MEMORY_USERPTR;
- 
-       if (-1 == xioctl(fd, VIDIOC_DQBUF, &buf)) {
-         switch (errno) {
-           case EAGAIN:
-             return 0;
- 
-           case EIO:
-             // Could ignore EIO, see spec.
- 
-             // fall through
-           default:
-             errno_exit("VIDIOC_DQBUF");
-                         
-         }
-       }
- 
-       for (i = 0; i < n_buffers; ++i)
-         if (buf.m.userptr == (unsigned long) buffers[i].start && buf.length == buffers[i].length)
-           break;
- 
-       assert (i < n_buffers);
- 
-       imageProcess((void *) buf.m.userptr);
- 
-       if (-1 == xioctl(fd, VIDIOC_QBUF, &buf))
-         errno_exit("VIDIOC_QBUF");
-       break;
- #endif
- 
-     }
- 
-   return 1;
- }
- 
- /** 
-   mainloop: read frames and process them
- */
- static void mainLoop(void)
- {
-   unsigned int count;
- 
-   count = 1;
- 
-   while (count-- > 0) {
-     for (;;) {
-       fd_set fds;
-       struct timeval tv;
-       int r;
- 
-       FD_ZERO(&fds);
-       FD_SET(fd, &fds);
- 
-       /* Timeout. */
-       tv.tv_sec = g_timeout;
-       tv.tv_usec = 0;
- 
-       r = select(fd + 1, &fds, NULL, NULL, &tv);
- 
-       if (-1 == r) {
-         if (EINTR == errno)
-           continue;
- 
-         errno_exit("select");
-       }
- 
-       if (0 == r) {
-         fprintf (stderr, "select timeout\n");
-         exit(EXIT_FAILURE);
-       }
- 
-       if (frameRead())
-         break;
-         
-       /* EAGAIN - continue select loop. */
-     }
-   }
- }
- 
- /**
-   stop capturing
- */
- static void captureStop(void)
- {
-   enum v4l2_buf_type type;
- 
-   switch (io) {
- #ifdef IO_READ
-     case IO_METHOD_READ:
-       /* Nothing to do. */
-       break;
- #endif
- 
- #ifdef IO_MMAP
-     case IO_METHOD_MMAP:
- #endif
- #ifdef IO_USERPTR
-     case IO_METHOD_USERPTR:
- #endif
- #if defined(IO_MMAP) || defined(IO_USERPTR)
-       type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
- 
-       if (-1 == xioctl(fd, VIDIOC_STREAMOFF, &type))
-         errno_exit("VIDIOC_STREAMOFF");
- 
-       break;
- #endif 
-    }
- }
- 
- /**
-   start capturing
- */
- static void captureStart(void)
- {
-   unsigned int i;
-   enum v4l2_buf_type type;
- 
-   switch (io) {
- #ifdef IO_READ    
-     case IO_METHOD_READ:
-       /* Nothing to do. */
-       break;
- #endif
- 
- #ifdef IO_MMAP
-     case IO_METHOD_MMAP:
-       for (i = 0; i < n_buffers; ++i) {
-         struct v4l2_buffer buf;
- 
-         CLEAR (buf);
- 
-         buf.type        = V4L2_BUF_TYPE_VIDEO_CAPTURE;
-         buf.memory      = V4L2_MEMORY_MMAP;
-         buf.index       = i;
- 
-         if (-1 == xioctl(fd, VIDIOC_QBUF, &buf))
-           errno_exit("VIDIOC_QBUF");
-       }
-                 
-       type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
- 
-       if (-1 == xioctl(fd, VIDIOC_STREAMON, &type))
-         errno_exit("VIDIOC_STREAMON");
- 
-       break;
- #endif
- 
- #ifdef IO_USERPTR
-     case IO_METHOD_USERPTR:
-       for (i = 0; i < n_buffers; ++i) {
-         struct v4l2_buffer buf;
- 
-         CLEAR (buf);
- 
-         buf.type        = V4L2_BUF_TYPE_VIDEO_CAPTURE;
-         buf.memory      = V4L2_MEMORY_USERPTR;
-         buf.index       = i;
-         buf.m.userptr   = (unsigned long) buffers[i].start;
-         buf.length      = buffers[i].length;
- 
-         if (-1 == xioctl(fd, VIDIOC_QBUF, &buf))
-           errno_exit("VIDIOC_QBUF");
-       }
- 
-       type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
- 
-       if (-1 == xioctl(fd, VIDIOC_STREAMON, &type))
-          errno_exit("VIDIOC_STREAMON");
- 
-       break;
- #endif
-   }
- }
- 
- static void deviceUninit(void)
- {
-   unsigned int i;
- 
-   switch (io) {
- #ifdef IO_READ
-     case IO_METHOD_READ:
-       free(buffers[0].start);
-       break;
- #endif
- 
- #ifdef IO_MMAP
-     case IO_METHOD_MMAP:
-       for (i = 0; i < n_buffers; ++i)
-       if (-1 == munmap (buffers[i].start, buffers[i].length))
-         errno_exit("munmap");
-       break;
- #endif
- 
- #ifdef IO_USERPTR
-     case IO_METHOD_USERPTR:
-       for (i = 0; i < n_buffers; ++i)
-         free (buffers[i].start);
-       break;
- #endif
-   }
- 
-   free(buffers);
- }
- 
- #ifdef IO_READ
- static void readInit(unsigned int buffer_size)
- {
-   buffers = calloc(1, sizeof(*buffers));
- 
-   if (!buffers) {
-     fprintf (stderr, "Out of memory\n");
-     exit(EXIT_FAILURE);
-   }
- 
-   buffers[0].length = buffer_size;
-   buffers[0].start = malloc (buffer_size);
- 
-   if (!buffers[0].start) {
-     fprintf (stderr, "Out of memory\n");
-     exit(EXIT_FAILURE);
-   }
- }
- #endif
- 
- #ifdef IO_MMAP
- static void mmapInit(void)
- {
-   struct v4l2_requestbuffers req;
- 
-   CLEAR (req);
- 
-   req.count               = 4;
-   req.type                = V4L2_BUF_TYPE_VIDEO_CAPTURE;
-   req.memory              = V4L2_MEMORY_MMAP;
- 
-   if (-1 == xioctl(fd, VIDIOC_REQBUFS, &req)) {
-     if (EINVAL == errno) {
-       fprintf(stderr, "%s does not support memory mapping\n", deviceName);
-       exit(EXIT_FAILURE);
-     } else {
-       errno_exit("VIDIOC_REQBUFS");
-     }
-   }
- 
-   if (req.count < 2) {
-     fprintf(stderr, "Insufficient buffer memory on %s\n", deviceName);
-     exit(EXIT_FAILURE);
-   }
- 
-   buffers = calloc(req.count, sizeof(*buffers));
- 
-   if (!buffers) {
-     fprintf(stderr, "Out of memory\n");
-     exit(EXIT_FAILURE);
-   }
- 
-   for (n_buffers = 0; n_buffers < req.count; ++n_buffers) {
-     struct v4l2_buffer buf;
- 
-     CLEAR (buf);
- 
-     buf.type        = V4L2_BUF_TYPE_VIDEO_CAPTURE;
-     buf.memory      = V4L2_MEMORY_MMAP;
-     buf.index       = n_buffers;
- 
-     if (-1 == xioctl(fd, VIDIOC_QUERYBUF, &buf))
-       errno_exit("VIDIOC_QUERYBUF");
- 
-     buffers[n_buffers].length = buf.length;
-     buffers[n_buffers].start =
-     mmap (NULL /* start anywhere */, buf.length, PROT_READ | PROT_WRITE /* required */, MAP_SHARED /* recommended */, fd, buf.m.offset);
- 
-     if (MAP_FAILED == buffers[n_buffers].start)
-       errno_exit("mmap");
-   }
- }
- #endif
- 
- #ifdef IO_USERPTR
- static void userptrInit(unsigned int buffer_size)
- {
-   struct v4l2_requestbuffers req;
-   unsigned int page_size;
- 
-   page_size = getpagesize ();
-   buffer_size = (buffer_size + page_size - 1) & ~(page_size - 1);
- 
-   CLEAR(req);
- 
-   req.count               = 4;
-   req.type                = V4L2_BUF_TYPE_VIDEO_CAPTURE;
-   req.memory              = V4L2_MEMORY_USERPTR;
- 
-   if (-1 == xioctl(fd, VIDIOC_REQBUFS, &req)) {
-     if (EINVAL == errno) {
-       fprintf(stderr, "%s does not support user pointer i/o\n", deviceName);
-       exit(EXIT_FAILURE);
-     } else {
-       errno_exit("VIDIOC_REQBUFS");
-     }
-   }
- 
-   buffers = calloc(4, sizeof (*buffers));
- 
-   if (!buffers) {
-     fprintf(stderr, "Out of memory\n");
-     exit(EXIT_FAILURE);
-   }
- 
-   for (n_buffers = 0; n_buffers < 4; ++n_buffers) {
-     buffers[n_buffers].length = buffer_size;
-     buffers[n_buffers].start = memalign (/* boundary */ page_size, buffer_size);
- 
-     if (!buffers[n_buffers].start) {
-       fprintf(stderr, "Out of memory\n");
-       exit(EXIT_FAILURE);
-     }
-   }
- }
- #endif
- 
- /**
-   initialize device
- */
- static void deviceInit(void)
- {
-   struct v4l2_capability cap;
-   struct v4l2_cropcap cropcap;
-   struct v4l2_crop crop;
-   struct v4l2_format fmt;
-   unsigned int min;
- 
-   if (-1 == xioctl(fd, VIDIOC_QUERYCAP, &cap)) {
-     if (EINVAL == errno) {
-       fprintf(stderr, "%s is no V4L2 device\n",deviceName);
-       exit(EXIT_FAILURE);
-     } else {
-       errno_exit("VIDIOC_QUERYCAP");
-     }
-   }
- 
-   if (!(cap.capabilities & V4L2_CAP_VIDEO_CAPTURE)) {
-     fprintf(stderr, "%s is no video capture device\n",deviceName);
-     exit(EXIT_FAILURE);
-   }
- 
-   switch (io) {
- #ifdef IO_READ
-     case IO_METHOD_READ:
-       if (!(cap.capabilities & V4L2_CAP_READWRITE)) {
-         fprintf(stderr, "%s does not support read i/o\n",deviceName);
-         exit(EXIT_FAILURE);
-       }
-       break;
- #endif
- 
- #ifdef IO_MMAP
-     case IO_METHOD_MMAP:
- #endif
- #ifdef IO_USERPTR
-     case IO_METHOD_USERPTR:
- #endif
- #if defined(IO_MMAP) || defined(IO_USERPTR)
-       if (!(cap.capabilities & V4L2_CAP_STREAMING)) {
-         fprintf(stderr, "%s does not support streaming i/o\n",deviceName);
-         exit(EXIT_FAILURE);
-       }
-       break;
- #endif
-   }
- 
- 
-   /* Select video input, video standard and tune here. */
-   CLEAR(cropcap);
- 
-   cropcap.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
- 
-   if (0 == xioctl(fd, VIDIOC_CROPCAP, &cropcap)) {
-     crop.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
-     crop.c = cropcap.defrect; /* reset to default */
- 
-     if (-1 == xioctl(fd, VIDIOC_S_CROP, &crop)) {
-       switch (errno) {
-         case EINVAL:
-           /* Cropping not supported. */
-           break;
-         default:
-           /* Errors ignored. */
-           break;
-       }
-     }
-   } else {        
-     /* Errors ignored. */
-   }
- 
-   CLEAR (fmt);
- 
-   // v4l2_format
-   fmt.type                = V4L2_BUF_TYPE_VIDEO_CAPTURE;
-   fmt.fmt.pix.width       = width; 
-   fmt.fmt.pix.height      = height;
-   //aiyps
- #if 1
- 	fmt.fmt.pix.pixelformat = V4L2_PIX_FMT_YUYV;
- #else
- 	fmt.fmt.pix.pixelformat =   V4L2_PIX_FMT_UYVY;
- #endif
-   fmt.fmt.pix.field       = V4L2_FIELD_INTERLACED;
- 
-   if (-1 == xioctl(fd, VIDIOC_S_FMT, &fmt))
-     errno_exit("VIDIOC_S_FMT");
- 
-   /* Note VIDIOC_S_FMT may change width and height. */
-   if (width != fmt.fmt.pix.width) {
-     width = fmt.fmt.pix.width;
-     fprintf(stderr,"Image width set to %i by device %s.\n",width,deviceName);
-   }
-   if (height != fmt.fmt.pix.height) {
-     height = fmt.fmt.pix.height;
-     fprintf(stderr,"Image height set to %i by device %s.\n",height,deviceName);
-   }
- 
-   /* Buggy driver paranoia. */
-   min = fmt.fmt.pix.width * 2;
-   if (fmt.fmt.pix.bytesperline < min)
-     fmt.fmt.pix.bytesperline = min;
-   min = fmt.fmt.pix.bytesperline * fmt.fmt.pix.height;
-   if (fmt.fmt.pix.sizeimage < min)
-     fmt.fmt.pix.sizeimage = min;
- 
-   switch (io) {
- #ifdef IO_READ
-     case IO_METHOD_READ:
-       readInit(fmt.fmt.pix.sizeimage);
-       break;
- #endif
- 
- #ifdef IO_MMAP
-     case IO_METHOD_MMAP:
-       mmapInit();
-       break;
- #endif
- 
- #ifdef IO_USERPTR
-     case IO_METHOD_USERPTR:
-       userptrInit(fmt.fmt.pix.sizeimage);
-       break;
- #endif
-   }
- }
- 
- /**
-   close device
- */
- static void deviceClose(void)
- {
-   if (-1 == close (fd))
-     errno_exit("close");
- 
-   fd = -1;
- }
- 
- /**
-   open device
- */
- static void deviceOpen(void)
- {
-   struct stat st;
- 
-   // stat file
-   if (-1 == stat(deviceName, &st)) {
-     fprintf(stderr, "Cannot identify '%s': %d, %s\n", deviceName, errno, strerror (errno));
-     exit(EXIT_FAILURE);
-   }
- 
-   // check if its device
-   if (!S_ISCHR (st.st_mode)) {
-     fprintf(stderr, "%s is no device\n", deviceName);
-     exit(EXIT_FAILURE);
-   }
- 
-   // open device
- #if 1
-   // aiyps
-   fd = open(deviceName, O_RDWR /* required */ | O_NONBLOCK, 0);
- #else
-   fd = open(deviceName, O_RDWR /* required */, 0);
- #endif
-   // check if opening was successfull
-   if (-1 == fd) {
-     fprintf(stderr, "Cannot open '%s': %d, %s\n", deviceName, errno, strerror (errno));
-     exit(EXIT_FAILURE);
-   }
- }
- 
- /**
-   print usage information
- */
- static void usage(FILE* fp, int argc, char** argv)
- {
-   fprintf (fp,
-     "Usage: %s [options]\n\n"
-     "Options:\n"
-     "-d | --device name   Video device name [/dev/video0]\n"
-     "-h | --help          Print this message\n"
-     "-o | --output        JPEG output filename\n"
-     "-q | --quality       JPEG quality (0-100)\n"
-     "-m | --mmap          Use memory mapped buffers\n"
-     "-r | --read          Use read() calls\n"
-     "-u | --userptr       Use application allocated buffers\n"
-     "-W | --width         width\n"
-     "-H | --height        height\n"
-     "-t | --timeout       Timeout\n"
-     "",
-     argv[0]);
- }
- 
- static const char short_options [] = "d:ho:q:mruW:H:t:";
- 
- static const struct option
- long_options [] = {
-         { "device",     required_argument,      NULL,           'd' },
-         { "help",       no_argument,            NULL,           'h' },
-         { "output",     required_argument,      NULL,           'o' },
-         { "quality",    required_argument,      NULL,           'q' },
-         { "mmap",       no_argument,            NULL,           'm' },
-         { "read",       no_argument,            NULL,           'r' },
-         { "userptr",    no_argument,            NULL,           'u' },
-         { "width",      required_argument,      NULL,           'W' },
-         { "height",     required_argument,      NULL,           'H' },
-         { "timeout",     required_argument,      NULL,          't' },
-         { 0, 0, 0, 0 }
- };
- 
- int main(int argc, char **argv)
- {
- 
-   for (;;) {
-     int index, c = 0;
-                 
-     c = getopt_long(argc, argv, short_options, long_options, &index);
- 
-     if (-1 == c)
-       break;
- 
-     switch (c) {
-       case 0: /* getopt_long() flag */
-         break;
- 
-       case 'd':
-         deviceName = optarg;
-         break;
- 
-       case 'h':
-         // print help
-         usage (stdout, argc, argv);
-         exit(EXIT_SUCCESS);
- 
-       case 'o':
-         // set jpeg filename
-         jpegFilename = optarg;
-         break;
- 
-       case 'q':
-         // set jpeg filename
-         jpegQuality = atoi(optarg);
-         break;
- 
-       case 'm':
- #ifdef IO_MMAP
-         io = IO_METHOD_MMAP;
- #else
-         fprintf(stderr, "You didn't compile for mmap support.\n");
-         exit(EXIT_FAILURE);         
- #endif
-         break;
- 
-       case 'r':
- #ifdef IO_READ
-         io = IO_METHOD_READ;
- #else
-         fprintf(stderr, "You didn't compile for read support.\n");
-         exit(EXIT_FAILURE);         
- #endif
-         break;
- 
-       case 'u':
- #ifdef IO_USERPTR
-         io = IO_METHOD_USERPTR;
- #else
-         fprintf(stderr, "You didn't compile for userptr support.\n");
-         exit(EXIT_FAILURE);         
- #endif
-         break;
- 
-       case 'W':
-         // set width
-         width = atoi(optarg);
-         break;
- 
-       case 'H':
-         // set height
-         height = atoi(optarg);
-         break;
- 		
- 	case 't':
- 		g_timeout = atoi(optarg);
- 		break;
- 		
-       default:
-         usage(stderr, argc, argv);
-         exit(EXIT_FAILURE);
-     }
-   }
- 
-   // check for need parameters
-   if (!jpegFilename) {
-         fprintf(stderr, "You have to specify JPEG output filename!\n\n");
-         usage(stdout, argc, argv);
-         exit(EXIT_FAILURE); 
-   }
- 
-   // open and initialize device
-   deviceOpen();
-   deviceInit();
- 
-   // start capturing
-   captureStart();
- 
-   // process frames
-   mainLoop();
- 
-   // stop capturing
-   captureStop();
- 
-   // close device
-   deviceUninit();
-   deviceClose();
- 
-   exit(EXIT_SUCCESS);
- 
-   return 0;
- }
--- 0 ----
diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/common/uart_flasher/target/ckb-1808/device.c buildroot-2013.08.1-ckb-20141129-1/board/ckb/common/uart_flasher/target/ckb-1808/device.c
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/common/uart_flasher/target/ckb-1808/device.c	2013-12-20 10:02:20.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/common/uart_flasher/target/ckb-1808/device.c	2014-11-28 08:59:40.000000000 +0900
***************
*** 583,589 ****
  }
  
  
! void init_DEVICE()
  {
  	// Ensure the kick registers are unlocked 
  	// Note these lines have no effect on 2.0 and later silicon
--- 583,589 ----
  }
  
  
! int init_DEVICE()
  {
  	// Ensure the kick registers are unlocked 
  	// Note these lines have no effect on 2.0 and later silicon
***************
*** 606,611 ****
--- 606,612 ----
  	//-- NOR FLASH Set
  	FLASH_Init();
  	DEVICE_Init();
+ 	return 0;
  }
  
  void udelay(int dly)
diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/common/uart_flasher/target/ckb-1808/include/device.h buildroot-2013.08.1-ckb-20141129-1/board/ckb/common/uart_flasher/target/ckb-1808/include/device.h
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/common/uart_flasher/target/ckb-1808/include/device.h	2013-12-20 10:02:20.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/common/uart_flasher/target/ckb-1808/include/device.h	2014-11-28 08:59:30.000000000 +0900
***************
*** 874,880 ****
  extern void    DEVICE_kickLock(void);
  
  // System Initialization prototypes
! extern void  init_DEVICE(void);
  
  // Peripheral Initialization prototypes
  extern Uint32  DEVICE_UARTInit(Uint8 periphNum);
--- 874,880 ----
  extern void    DEVICE_kickLock(void);
  
  // System Initialization prototypes
! extern int  init_DEVICE(void);
  
  // Peripheral Initialization prototypes
  extern Uint32  DEVICE_UARTInit(Uint8 periphNum);
diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/common/uart_flasher/target/ckb-3352/device.c buildroot-2013.08.1-ckb-20141129-1/board/ckb/common/uart_flasher/target/ckb-3352/device.c
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/common/uart_flasher/target/ckb-3352/device.c	2013-12-20 10:02:20.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/common/uart_flasher/target/ckb-3352/device.c	2014-11-28 09:00:44.000000000 +0900
***************
*** 200,208 ****
--- 200,210 ----
  
  /* MAIN PLL Fdll = 1 GHZ, */
  #define MPUPLL_M_275	 275	/* 125 * n */
+ #define MPUPLL_M_300	 300	/* 125 * n */
  #define MPUPLL_M_500	 500	/* 125 * n */
  #define MPUPLL_M_600	 600	/* 125 * n */
  #define MPUPLL_M_720	 720	/* 125 * n */
+ #define MPUPLL_M_800	 800	/* 125 * n */
  
  #define MPUPLL_N		 23	/* (n -1 ) */
  #define MPUPLL_M2		 1
***************
*** 252,257 ****
--- 254,260 ----
  #define DEFDCDC3			0x10
  #define DEFSLEW				0x11
  #define DCDC_GO				0x80
+ #define V0950				0x02
  #define V1100				0x08
  #define V1200				0x0C
  #define V1275				0x0F
***************
*** 569,574 ****
--- 572,580 ----
  #define vrefp			(PAD_CTRL_BASE + 0x330)
  #define vrefn			(PAD_CTRL_BASE + 0x334)
  
+ /* TI81XX spefic control submodules */
+ #define DEVICE_ID_REG_OFFSET		0x600
+ #define DEVICE_ID_REG	(CTRL_BASE + DEVICE_ID_REG_OFFSET)
  
  /* I2C */
  #define I2C_BASE1		0x44E0B000
***************
*** 1258,1265 ****
  	int DDR3_EMIF_TIM3				= 0x501F830F;		// by calc_tool
  	int DDR3_EMIF_SDREF				= 0x0000093B;		// 303MHz * 7.8us
  	int DDR3_ZQ_CFG					= 0x50074BE4;
! 	//int DDR3_EMIF_SDCFG				= 0x61C04AB2;
! 
  	int reg_sdram_type;
  	int reg_ibank_pos;
  	int reg_ddr_term;
--- 1264,1270 ----
  	int DDR3_EMIF_TIM3				= 0x501F830F;		// by calc_tool
  	int DDR3_EMIF_SDREF				= 0x0000093B;		// 303MHz * 7.8us
  	int DDR3_ZQ_CFG					= 0x50074BE4;
! 	
  	int reg_sdram_type;
  	int reg_ibank_pos;
  	int reg_ddr_term;
***************
*** 1307,1313 ****
  	reg_ebank				= (0<<3);
  	reg_pagesize			= (2);			/* 10 1k */
  
- //	Outport(3, EMIF4_0_SDRAM_CONFIG,			DDR3_EMIF_SDCFG);
  	Outport(3, EMIF4_0_SDRAM_CONFIG,	reg_sdram_type		|
                                          reg_ibank_pos		|
                                          reg_ddr_term		|
--- 1312,1317 ----
***************
*** 1326,1334 ****
  }
  
  
! void pll_init()
  {
! 	mpu_pll_config(MPUPLL_M_500);
  	core_pll_config();
  	per_pll_config();
  	ddr_pll_config();
--- 1330,1341 ----
  }
  
  
! void pll_init(int revision)
  {
! 	if(revision >= AM335X_REV_ES2_0)
! 		mpu_pll_config(MPUPLL_M_600);
! 	else
! 		mpu_pll_config(MPUPLL_M_500);
  	core_pll_config();
  	per_pll_config();
  	ddr_pll_config();
***************
*** 1824,1861 ****
  int tps65217_reg_write(int prot_level, int dest_reg, int dest_val, int mask)
  {
  
! 		int read_val;
! 		int xor_reg;
  
! 		/* if we are affecting only a bit field, read dest_reg and apply the mask */
! 		if (mask != MASK_ALL_BITS) {
! 			if (i2c_read_byte(TPS65217_CHIP_PM, dest_reg, &read_val))
! 				return 1;
! 			read_val &= (~mask);
! 			read_val |= (dest_val & mask);
! 			dest_val = read_val;
! 		}
! 
! 		if (prot_level > 0) {
! 			xor_reg = dest_reg ^ PASSWORD_UNLOCK;
! 			if (i2c_write_byte(TPS65217_CHIP_PM, PASSWORD, xor_reg))
! 				return 1;
! 		}
  
! 		if (i2c_write_byte(TPS65217_CHIP_PM, dest_reg, dest_val))
  			return 1;
  
! 		if (prot_level == PROT_LEVEL_2) {
! 			if (i2c_write_byte(TPS65217_CHIP_PM, PASSWORD, xor_reg))
! 				return 1;
  
! 			if (i2c_write_byte(TPS65217_CHIP_PM, dest_reg, dest_val))
! 				return 1;
! 		}
  
! 		return 0;
  }
  
  void arm_275m()
  {
  	int mask1	= 0x3F;
--- 1831,1868 ----
  int tps65217_reg_write(int prot_level, int dest_reg, int dest_val, int mask)
  {
  
! 	int read_val;
! 	int xor_reg;
  
! 	/* if we are affecting only a bit field, read dest_reg and apply the mask */
! 	if (mask != MASK_ALL_BITS) {
! 		if (i2c_read_byte(TPS65217_CHIP_PM, dest_reg, &read_val))
! 			return 1;
! 		read_val &= (~mask);
! 		read_val |= (dest_val & mask);
! 		dest_val = read_val;
! 	}
  
! 	if (prot_level > 0) {
! 		xor_reg = dest_reg ^ PASSWORD_UNLOCK;
! 		if (i2c_write_byte(TPS65217_CHIP_PM, PASSWORD, xor_reg))
  			return 1;
+ 	}
  
! 	if (i2c_write_byte(TPS65217_CHIP_PM, dest_reg, dest_val))
! 		return 1;
  
! 	if (prot_level == PROT_LEVEL_2) {
! 		if (i2c_write_byte(TPS65217_CHIP_PM, PASSWORD, xor_reg))
! 			return 1;
  
! 		if (i2c_write_byte(TPS65217_CHIP_PM, dest_reg, dest_val))
! 			return 1;
! 	}
! 	return 0;
  }
  
+ // Rev ES1
  void arm_275m()
  {
  	int mask1	= 0x3F;
***************
*** 1868,1873 ****
--- 1875,1897 ----
  	mpu_pll_config(MPUPLL_M_275);
  
  }
+ 
+ // Rev >= ES2_0
+ void arm_300m()
+ {
+ 	int mask1	= 0x3F;
+ 	int mask2	= 0x80;;
+ 
+ 	i2c_init(100000,1);
+ 	//tps65217_reg_write(PROT_LEVEL_2,DEFDCDC2,V1100,mask1);
+ 	tps65217_reg_write(PROT_LEVEL_2,DEFDCDC2,V0950,mask1);
+ 	tps65217_reg_write(PROT_LEVEL_2,DEFSLEW,DCDC_GO,mask2);
+ 	udelay(1);
+ 	mpu_pll_config(MPUPLL_M_300);
+ 
+ }
+ 
+ // Rev ES1
  void arm_500m()
  {
  	int mask1	= 0x3F;
***************
*** 1881,1916 ****
  
  }
  
! void arm_600m()
  {
  	int mask1	= 0x3F;
  	int mask2	= 0x80;;
  
  	i2c_init(100000,1);
! 	tps65217_reg_write(PROT_LEVEL_2,DEFDCDC2,V1200,mask1);
  	tps65217_reg_write(PROT_LEVEL_2,DEFSLEW,DCDC_GO,mask2);
  	udelay(1);
  	mpu_pll_config(MPUPLL_M_600);
  
  }
  
! void arm_720m()
  {
  	int mask1	= 0x3F;
  	int mask2	= 0x80;;
  
  	i2c_init(100000,1);
! 	tps65217_reg_write(PROT_LEVEL_2,DEFDCDC2,V1275,mask1);
  	tps65217_reg_write(PROT_LEVEL_2,DEFSLEW,DCDC_GO,mask2);
  	udelay(1);
  	mpu_pll_config(MPUPLL_M_720);
  
  }
  
! void init_DEVICE()
  {
  	watchdog_init();
! 	pll_init();
  	
  	pin_config();
  	gpmc_config();
--- 1905,1986 ----
  
  }
  
! void arm_600m(int revision)
  {
  	int mask1	= 0x3F;
  	int mask2	= 0x80;;
  
  	i2c_init(100000,1);
! 	if(revision >= AM335X_REV_ES2_0)
! 		tps65217_reg_write(PROT_LEVEL_2,DEFDCDC2,V1100,mask1);
! 	else
! 		tps65217_reg_write(PROT_LEVEL_2,DEFDCDC2,V1200,mask1);
  	tps65217_reg_write(PROT_LEVEL_2,DEFSLEW,DCDC_GO,mask2);
  	udelay(1);
  	mpu_pll_config(MPUPLL_M_600);
  
  }
  
! void arm_720m(int revision)
  {
  	int mask1	= 0x3F;
  	int mask2	= 0x80;;
  
  	i2c_init(100000,1);
! 	if(revision >= AM335X_REV_ES2_0)
! 		tps65217_reg_write(PROT_LEVEL_2,DEFDCDC2,V1200,mask1);
! 	else
! 		tps65217_reg_write(PROT_LEVEL_2,DEFDCDC2,V1275,mask1);
  	tps65217_reg_write(PROT_LEVEL_2,DEFSLEW,DCDC_GO,mask2);
  	udelay(1);
  	mpu_pll_config(MPUPLL_M_720);
  
  }
+ // Rev >= ES2_0
+ void arm_800m()
+ {
+ 	int mask1	= 0x3F;
+ 	int mask2	= 0x80;;
+ 
+ 	i2c_init(100000,1);
+ 	tps65217_reg_write(PROT_LEVEL_2,DEFDCDC2,V1275,mask1);
+ 	tps65217_reg_write(PROT_LEVEL_2,DEFSLEW,DCDC_GO,mask2);
+ 	udelay(1);
+ 	mpu_pll_config(MPUPLL_M_800);
+ 
+ }
  
! unsigned long get_dev_id()
  {
+ 	return Inport(3, DEVICE_ID_REG);
+ }
+ 
+ int init_DEVICE()
+ {
+ 	int revision;
+ 	unsigned long idcode;
+ 	unsigned char rev;
+ 
  	watchdog_init();
! 	/* get the CPU revision */
! 	idcode = get_dev_id();
! 	rev = (idcode >> 28) & 0xff;
! 	switch(rev)
! 	{
! 	case 0:
! 		revision = AM335X_REV_ES1_0;
! 		break;
! 	case 1:
! 		revision = AM335X_REV_ES2_0;
! 		break;
! 	case 2:
! 		revision = AM335X_REV_ES2_1;
! 		break;
! 	default:
! 		revision = AM335X_REV_UNKNOWN;
! 		break;
! 	}
! 	pll_init(revision);
  	
  	pin_config();
  	gpmc_config();
***************
*** 1918,1925 ****
  	config_am335x_ddr3();
  	/* some problem with CS1 mode, use GPIO mode */
  	gpmc_cs1_ext_cn_config(1);			/* 1 -> GPIO mode, 0->CS1 mode */
! 	//arm_600m();
  	DEVICE_UARTInit(115200);
  }
  
  void set_nor_flash_bank(int bank)
--- 1988,1999 ----
  	config_am335x_ddr3();
  	/* some problem with CS1 mode, use GPIO mode */
  	gpmc_cs1_ext_cn_config(1);			/* 1 -> GPIO mode, 0->CS1 mode */
! 	if(revision >= AM335X_REV_ES2_0)
! 		arm_800m();
! 	else
! 		arm_720m(revision);
  	DEVICE_UARTInit(115200);
+ 	return revision;
  }
  
  void set_nor_flash_bank(int bank)
diff -crN buildroot-2013.08.1-ckb-20140807-1/board/ckb/common/uart_flasher/target/ckb-3352/include/device.h buildroot-2013.08.1-ckb-20141129-1/board/ckb/common/uart_flasher/target/ckb-3352/include/device.h
*** buildroot-2013.08.1-ckb-20140807-1/board/ckb/common/uart_flasher/target/ckb-3352/include/device.h	2013-12-20 10:02:20.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/board/ckb/common/uart_flasher/target/ckb-3352/include/device.h	2014-11-28 09:00:05.000000000 +0900
***************
*** 15,20 ****
--- 15,27 ----
  #endif
  
  #define TARGET_NAME	"CKB-3352 (COMPUTEX Kumikomi Board)"
+ // CPU Revision
+ enum {
+ 	AM335X_REV_ES1_0,
+ 	AM335X_REV_ES2_0,
+ 	AM335X_REV_ES2_1,
+ 	AM335X_REV_UNKNOWN
+ };
  
  // System Control Module register structure
  typedef struct _DEVICE_SYS_MODULE_REGS_
***************
*** 510,516 ****
  #define dlm ier
  #define LSR lsr
  
- 
  /* useful defaults for LCR */
  #define UART_LCR_8N1	0x03
  
--- 517,522 ----
***************
*** 518,524 ****
  #define UART_CLK_RUNNING_MASK	0x1
  #define UART_SMART_IDLE_EN	(0x1 << 0x3)
  
- 
  /*
   * These are the definitions for the FIFO Control Register
   */
--- 524,529 ----
***************
*** 606,612 ****
  * Global Function Declarations                             *
  ***********************************************************/
  // System Initialization prototypes
! extern void  init_DEVICE(void);
  
  /***********************************************************
  * End file                                                 *
--- 611,617 ----
  * Global Function Declarations                             *
  ***********************************************************/
  // System Initialization prototypes
! extern int init_DEVICE(void);
  
  /***********************************************************
  * End file                                                 *
diff -crN buildroot-2013.08.1-ckb-20140807-1/configs/ckb-1808_defconfig buildroot-2013.08.1-ckb-20141129-1/configs/ckb-1808_defconfig
*** buildroot-2013.08.1-ckb-20140807-1/configs/ckb-1808_defconfig	2014-07-02 10:51:13.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/configs/ckb-1808_defconfig	2014-11-27 16:38:16.000000000 +0900
***************
*** 288,294 ****
  BR2_TARGET_GENERIC_GETTY_TERM="vt100"
  BR2_TARGET_GENERIC_REMOUNT_ROOTFS_RW=y
  BR2_ROOTFS_OVERLAY="board/ckb/ckb-1808/fs"
! BR2_ROOTFS_POST_BUILD_SCRIPT="board/ckb/ckb-1808/custom_fs.sh"
  BR2_ROOTFS_POST_IMAGE_SCRIPT=""
  BR2_ROOTFS_POST_SCRIPT_ARGS=""
  
--- 288,294 ----
  BR2_TARGET_GENERIC_GETTY_TERM="vt100"
  BR2_TARGET_GENERIC_REMOUNT_ROOTFS_RW=y
  BR2_ROOTFS_OVERLAY="board/ckb/ckb-1808/fs"
! BR2_ROOTFS_POST_BUILD_SCRIPT="board/ckb/ckb-1808/before_packing_fs.sh"
  BR2_ROOTFS_POST_IMAGE_SCRIPT=""
  BR2_ROOTFS_POST_SCRIPT_ARGS=""
  
***************
*** 1296,1304 ****
  # BR2_TARGET_ROOTFS_TAR is not set
  # BR2_TARGET_ROOTFS_UBIFS is not set
  BR2_EXCLUDE_USR_DIR_FROM_ROOTFS=y
! BR2_CUSTOM_ROOT_DIR_NAME="target_without_usr"
! BR2_CUSTOM_USR_DIR_NAME="sdcard_usr_folder"
! BR2_EXCLUDE_USR_DIR_POST_BUILD_SCRIPT="board/ckb/ckb-1808/extern_fs.sh"
  
  #
  # Bootloaders
--- 1296,1305 ----
  # BR2_TARGET_ROOTFS_TAR is not set
  # BR2_TARGET_ROOTFS_UBIFS is not set
  BR2_EXCLUDE_USR_DIR_FROM_ROOTFS=y
! BR2_CUSTOM_ROOT_DIR_NAME="initrd"
! BR2_CUSTOM_USR_DIR_NAME="microSD"
! BR2_USR_DIR_OVERLAY_NAME=""
! BR2_EXCLUDE_USR_DIR_POST_BUILD_SCRIPT="board/ckb/ckb-1808/usr_to_rootfs.sh"
  
  #
  # Bootloaders
diff -crN buildroot-2013.08.1-ckb-20140807-1/configs/ckb-3352_defconfig buildroot-2013.08.1-ckb-20141129-1/configs/ckb-3352_defconfig
*** buildroot-2013.08.1-ckb-20140807-1/configs/ckb-3352_defconfig	2014-07-02 10:27:04.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/configs/ckb-3352_defconfig	2014-11-27 16:38:24.000000000 +0900
***************
*** 98,103 ****
--- 98,104 ----
  BR2_CKB_GPIO_SAMPLE=y
  BR2_SPIDEV_SAMPLE=y
  BR2_CKB_EXT_CN1_MEM_SAMPLE=y
+ BR2_CKB_WDT_SAMPLE=y
  
  #
  # Build options
***************
*** 288,294 ****
  BR2_TARGET_GENERIC_GETTY_TERM="vt100"
  BR2_TARGET_GENERIC_REMOUNT_ROOTFS_RW=y
  BR2_ROOTFS_OVERLAY="board/ckb/ckb-3352/fs"
! BR2_ROOTFS_POST_BUILD_SCRIPT="board/ckb/ckb-3352/custom_fs.sh"
  BR2_ROOTFS_POST_IMAGE_SCRIPT=""
  BR2_ROOTFS_POST_SCRIPT_ARGS=""
  
--- 289,295 ----
  BR2_TARGET_GENERIC_GETTY_TERM="vt100"
  BR2_TARGET_GENERIC_REMOUNT_ROOTFS_RW=y
  BR2_ROOTFS_OVERLAY="board/ckb/ckb-3352/fs"
! BR2_ROOTFS_POST_BUILD_SCRIPT="board/ckb/ckb-3352/before_packing_fs.sh"
  BR2_ROOTFS_POST_IMAGE_SCRIPT=""
  BR2_ROOTFS_POST_SCRIPT_ARGS=""
  
***************
*** 1302,1310 ****
  # BR2_TARGET_ROOTFS_TAR is not set
  # BR2_TARGET_ROOTFS_UBIFS is not set
  BR2_EXCLUDE_USR_DIR_FROM_ROOTFS=y
! BR2_CUSTOM_ROOT_DIR_NAME="target_without_usr"
! BR2_CUSTOM_USR_DIR_NAME="sdcard_usr_folder"
! BR2_EXCLUDE_USR_DIR_POST_BUILD_SCRIPT="board/ckb/ckb-3352/extern_fs.sh"
  
  #
  # Bootloaders
--- 1303,1312 ----
  # BR2_TARGET_ROOTFS_TAR is not set
  # BR2_TARGET_ROOTFS_UBIFS is not set
  BR2_EXCLUDE_USR_DIR_FROM_ROOTFS=y
! BR2_CUSTOM_ROOT_DIR_NAME="initrd"
! BR2_CUSTOM_USR_DIR_NAME="microSD"
! BR2_USR_DIR_OVERLAY_NAME=""
! BR2_EXCLUDE_USR_DIR_POST_BUILD_SCRIPT="board/ckb/ckb-3352/usr_to_rootfs.sh"
  
  #
  # Bootloaders
diff -crN buildroot-2013.08.1-ckb-20140807-1/configs/ckb-rz_defconfig buildroot-2013.08.1-ckb-20141129-1/configs/ckb-rz_defconfig
*** buildroot-2013.08.1-ckb-20140807-1/configs/ckb-rz_defconfig	2014-07-08 17:40:31.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/configs/ckb-rz_defconfig	2014-11-27 16:38:37.000000000 +0900
***************
*** 289,295 ****
  BR2_TARGET_GENERIC_GETTY_TERM="vt100"
  BR2_TARGET_GENERIC_REMOUNT_ROOTFS_RW=y
  BR2_ROOTFS_OVERLAY="board/ckb/ckb-rz/fs"
! BR2_ROOTFS_POST_BUILD_SCRIPT="board/ckb/ckb-rz/custom_fs.sh"
  BR2_ROOTFS_POST_IMAGE_SCRIPT=""
  BR2_ROOTFS_POST_SCRIPT_ARGS=""
  
--- 289,295 ----
  BR2_TARGET_GENERIC_GETTY_TERM="vt100"
  BR2_TARGET_GENERIC_REMOUNT_ROOTFS_RW=y
  BR2_ROOTFS_OVERLAY="board/ckb/ckb-rz/fs"
! BR2_ROOTFS_POST_BUILD_SCRIPT="board/ckb/ckb-rz/before_packing_fs.sh"
  BR2_ROOTFS_POST_IMAGE_SCRIPT=""
  BR2_ROOTFS_POST_SCRIPT_ARGS=""
  
***************
*** 1301,1309 ****
  # BR2_TARGET_ROOTFS_TAR is not set
  # BR2_TARGET_ROOTFS_UBIFS is not set
  BR2_EXCLUDE_USR_DIR_FROM_ROOTFS=y
! BR2_CUSTOM_ROOT_DIR_NAME="target_without_usr"
! BR2_CUSTOM_USR_DIR_NAME="sdcard_usr_folder"
! BR2_EXCLUDE_USR_DIR_POST_BUILD_SCRIPT="board/ckb/ckb-rz/extern_fs.sh"
  
  #
  # Bootloaders
--- 1301,1310 ----
  # BR2_TARGET_ROOTFS_TAR is not set
  # BR2_TARGET_ROOTFS_UBIFS is not set
  BR2_EXCLUDE_USR_DIR_FROM_ROOTFS=y
! BR2_CUSTOM_ROOT_DIR_NAME="initrd"
! BR2_CUSTOM_USR_DIR_NAME="microSD"
! BR2_USR_DIR_OVERLAY_NAME=""
! BR2_EXCLUDE_USR_DIR_POST_BUILD_SCRIPT="board/ckb/ckb-rz/usr_to_rootfs.sh"
  
  #
  # Bootloaders
diff -crN buildroot-2013.08.1-ckb-20140807-1/fs/Config.in buildroot-2013.08.1-ckb-20141129-1/fs/Config.in
*** buildroot-2013.08.1-ckb-20140807-1/fs/Config.in	2014-01-24 09:50:56.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/fs/Config.in	2014-11-27 16:38:49.000000000 +0900
***************
*** 22,28 ****
  
  config BR2_CUSTOM_ROOT_DIR_NAME
  	string "Create a rootfs under"
! 	default "target_without_usr"
  	depends on BR2_EXCLUDE_USR_DIR_FROM_ROOTFS
  	help
  	  The name of the folder under which the rootfs excluding the
--- 22,28 ----
  
  config BR2_CUSTOM_ROOT_DIR_NAME
  	string "Create a rootfs under"
! 	default "intrd"
  	depends on BR2_EXCLUDE_USR_DIR_FROM_ROOTFS
  	help
  	  The name of the folder under which the rootfs excluding the
***************
*** 31,42 ****
  
  config BR2_CUSTOM_USR_DIR_NAME
  	string "Move contents of /usr to"
! 	default "sdcard_usr_folder"
  	depends on BR2_EXCLUDE_USR_DIR_FROM_ROOTFS
  	help
  	  The name of the folder into which the contents of /usr will
  	  be moved. This directory will appear under the
! 	  "output\images\" folder.
  
  config BR2_EXCLUDE_USR_DIR_POST_BUILD_SCRIPT
  	string "Run this script after excluding contents of /usr"
--- 31,49 ----
  
  config BR2_CUSTOM_USR_DIR_NAME
  	string "Move contents of /usr to"
! 	default "microSD"
  	depends on BR2_EXCLUDE_USR_DIR_FROM_ROOTFS
  	help
  	  The name of the folder into which the contents of /usr will
  	  be moved. This directory will appear under the
! 	  "output\" folder.
! 
! config BR2_USR_DIR_OVERLAY_NAME
! 	string "/usr overlay directories"
! 	default ""
! 	depends on BR2_EXCLUDE_USR_DIR_FROM_ROOTFS
! 	help
! 	  Specify a list of directories that are copied over the /usr directory.
  
  config BR2_EXCLUDE_USR_DIR_POST_BUILD_SCRIPT
  	string "Run this script after excluding contents of /usr"
diff -crN buildroot-2013.08.1-ckb-20140807-1/fs/common.mk buildroot-2013.08.1-ckb-20141129-1/fs/common.mk
*** buildroot-2013.08.1-ckb-20140807-1/fs/common.mk	2014-04-03 09:36:11.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/fs/common.mk	2014-11-27 16:38:59.000000000 +0900
***************
*** 39,44 ****
--- 39,45 ----
  
  CUSTOM_USR_DIR_NAME:=$(call qstrip,$(BR2_CUSTOM_USR_DIR_NAME))
  CUSTOM_ROOT_DIR_NAME:=$(call qstrip,$(BR2_CUSTOM_ROOT_DIR_NAME))
+ USR_DIR_OVERLAY_NAME:=$(call qstrip,$(BR2_USR_DIR_OVERLAY_NAME))
  EXCLUDE_USR_DIR-clean=./exclude_usr_dir-clean
  
  check_exclude_usr_dir:
***************
*** 58,74 ****
  	cp -rd $(TARGET_DIR)/ $(BASE_DIR)/$(CUSTOM_ROOT_DIR_NAME)
  	touch $(BASE_DIR)/$(CUSTOM_ROOT_DIR_NAME)/THIS_IS_NOT_YOUR_ROOT_FILESYSTEM
  	rm -rf $(BASE_DIR)/$(CUSTOM_ROOT_DIR_NAME)/THIS_IS_NOT_YOUR_ROOT_FILESYSTEM
! 	touch $(BINARIES_DIR)/$(CUSTOM_USR_DIR_NAME)
! 	rm -rf $(BINARIES_DIR)/$(CUSTOM_USR_DIR_NAME)
! 	mkdir $(BINARIES_DIR)/$(CUSTOM_USR_DIR_NAME)
! 	@$(call MESSAGE,"Moving \"usr\" folder to $(BINARIES_DIR)/$(CUSTOM_USR_DIR_NAME)/")
! 	mv $(BASE_DIR)/$(CUSTOM_ROOT_DIR_NAME)/usr/* $(BINARIES_DIR)/$(CUSTOM_USR_DIR_NAME)
  	@if ! [ $(BR2_EXCLUDE_USR_DIR_POST_BUILD_SCRIPT)11 == ""11 ]; then \
  		$(call MESSAGE,"Executing custom script $(BR2_EXCLUDE_USR_DIR_POST_BUILD_SCRIPT)") ;\
  		chmod +x $(BR2_EXCLUDE_USR_DIR_POST_BUILD_SCRIPT) ;\
  		$(BR2_EXCLUDE_USR_DIR_POST_BUILD_SCRIPT) $(BASE_DIR)/$(CUSTOM_ROOT_DIR_NAME) $(BINARIES_DIR)/$(CUSTOM_USR_DIR_NAME) ;\
! 	fi ;\
! 	echo "chown -R 0:0 $(BASE_DIR)/$(CUSTOM_ROOT_DIR_NAME)" >> $(FAKEROOT_SCRIPT) ;\
  
  exclude_usr_dir-clean:
  	@if ! [ $(CUSTOM_ROOT_DIR_NAME)11 = 11 ]; then \
--- 59,79 ----
  	cp -rd $(TARGET_DIR)/ $(BASE_DIR)/$(CUSTOM_ROOT_DIR_NAME)
  	touch $(BASE_DIR)/$(CUSTOM_ROOT_DIR_NAME)/THIS_IS_NOT_YOUR_ROOT_FILESYSTEM
  	rm -rf $(BASE_DIR)/$(CUSTOM_ROOT_DIR_NAME)/THIS_IS_NOT_YOUR_ROOT_FILESYSTEM
! 	touch $(BASE_DIR)/$(CUSTOM_USR_DIR_NAME)
! 	rm -rf $(BASE_DIR)/$(CUSTOM_USR_DIR_NAME)
! 	mkdir -p $(BASE_DIR)/$(CUSTOM_USR_DIR_NAME)/usr/
! 	@$(call MESSAGE,"Moving contents of \"usr\" folder to $(BASE_DIR)/$(CUSTOM_USR_DIR_NAME)/usr/")
! 	mv $(BASE_DIR)/$(CUSTOM_ROOT_DIR_NAME)/usr/* $(BASE_DIR)/$(CUSTOM_USR_DIR_NAME)/usr/
! 	@if ! [ $(BR2_USR_DIR_OVERLAY_NAME)11 == ""11 ]; then \
! 		$(call MESSAGE,"Copying contents of $(BR2_USR_DIR_OVERLAY_NAME) to $(BASE_DIR)/$(CUSTOM_USR_DIR_NAME)/usr/") ;\
! 		cp -rd $(USR_DIR_OVERLAY_NAME)/* $(BASE_DIR)/$(CUSTOM_USR_DIR_NAME)/usr/ ;\
! 	fi ;
  	@if ! [ $(BR2_EXCLUDE_USR_DIR_POST_BUILD_SCRIPT)11 == ""11 ]; then \
  		$(call MESSAGE,"Executing custom script $(BR2_EXCLUDE_USR_DIR_POST_BUILD_SCRIPT)") ;\
  		chmod +x $(BR2_EXCLUDE_USR_DIR_POST_BUILD_SCRIPT) ;\
  		$(BR2_EXCLUDE_USR_DIR_POST_BUILD_SCRIPT) $(BASE_DIR)/$(CUSTOM_ROOT_DIR_NAME) $(BINARIES_DIR)/$(CUSTOM_USR_DIR_NAME) ;\
! 	fi ;
! 	echo "chown -R 0:0 $(BASE_DIR)/$(CUSTOM_ROOT_DIR_NAME)" >> $(FAKEROOT_SCRIPT) ;
  
  exclude_usr_dir-clean:
  	@if ! [ $(CUSTOM_ROOT_DIR_NAME)11 = 11 ]; then \
diff -crN buildroot-2013.08.1-ckb-20140807-1/linux/linux.mk buildroot-2013.08.1-ckb-20141129-1/linux/linux.mk
*** buildroot-2013.08.1-ckb-20140807-1/linux/linux.mk	2014-07-08 16:05:59.000000000 +0900
--- buildroot-2013.08.1-ckb-20141129-1/linux/linux.mk	2014-11-25 16:26:37.000000000 +0900
***************
*** 348,355 ****
  		$(SED) "/\\<CONFIG_CKB_LCD_02\\>/d" $(@D)/.config; \
  		echo "# CONFIG_CKB_LCD_02 is not set" >> $(@D)/.config; \
  		\
! 		$(SED) "/\\<CONFIG_CKB_EXTCN_SPIDEV_SPI1\\>/d" $(@D)/.config; \
! 		echo "# CONFIG_CKB_EXTCN_SPIDEV_SPI1 is not set" >> $(@D)/.config; \
  		\
  		$(SED) "/\\<CONFIG_CKB_3352_AUDIO\\>/d" $(@D)/.config; \
  		echo "# CONFIG_CKB_3352_AUDIO is not set" >> $(@D)/.config; \
--- 348,355 ----
  		$(SED) "/\\<CONFIG_CKB_LCD_02\\>/d" $(@D)/.config; \
  		echo "# CONFIG_CKB_LCD_02 is not set" >> $(@D)/.config; \
  		\
! 		$(SED) "/\\<CONFIG_CKB_EXTCN_6_31_36_38\\>/d" $(@D)/.config; \
! 		echo "# CONFIG_CKB_EXTCN_6_31_36_38 is not set" >> $(@D)/.config; \
  		\
  		$(SED) "/\\<CONFIG_CKB_3352_AUDIO\\>/d" $(@D)/.config; \
  		echo "# CONFIG_CKB_3352_AUDIO is not set" >> $(@D)/.config; \
