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Having inherited the concept of PALMiCE series, it
realizes comfortable operation by speedup, and ease-of-use
by compactification and provision for connection that
requires no power supply. Furthermore, it supports multiple
cores and SWD (Serial Wire Debug) and SWV (Serial Wire
Viewer) which are provided by ARM CoreSight™ technology. 
SWD support
Supports "SWD"
interface by 2 strings of signal lines. The number of pins
occupied in the CPU has been reduced than with the
traditional JTAG interface by 5 strings of signal lines, and
by compactification of the connector, it can save the space.
SWV support
Supports "SWV", the
debug information interface by 1 string of signal line from
the CPU. Besides being capable of variable and event
information referencing without break during execution, it
will allow further improvement in debugging efficiency
by capturing
real-time trace information.
Multi-core support
Recently, multi-core
CPUs, which are capable of concurrent execution of
processing in multiple cores, are on
products to make power-saving and speedup feasible, and the
provision for it is required. In PALMiCE3, the internal
resource has been made more powerful to give itself a
structure that allows multi-core support.
Flexible support for various interfaces
Supports both
interfaces, the traditional 20-pin /14-pin 2.54mm(0.1") JTAG
connectors and 10-pin/20-pin 1.27mm(0.05") SWD connectors.
Even more compact body design
Although performance has been improved, it has been
materialized to even lighter and smaller body than the
former product.
Inherited Vbus support that requires no power supply
Realized connection that requires no power supply with Vbus
support provision based on the concept inherited from
PALMiCE series. 
Various features that had not been possible only with JTAG
now made into reality with SWV
- Profiler feature
Samples execution addresses at certain time interval and
analyzes the frequency of module execution based on the
times of capture. The feature is useful for identifying the
frequently used functions and the functions which occupy
much of the time.
- Printf debugging feature
By embedding the dedicated function in the user program of
the target, it implements the functionality similar to
Printf of C library. Output destination will be Terminal
Window in CSIDE.
With this, the history of variable etc. of your choice can
be saved to file.
- Time measurement between access data
Measures the time between the specified data accesses.
- Status bar
In the status bar, the target voltage is always indicated by
sampling. In addition, it indicates the program counter
value of the running CPU. With these, state of the CPU
execution can be roughly grasped.
Multi-core debugging
Allows debugging of
the CPUs implemented with multiple ARM7/9/11 or Cortex
cores. In multi-core debugging, it also supports synchronous
execution/synchronous break, which are essential. Provisions
have been made even for SMP-Linux and TOPPERS/FMP.
Sleep mode support
*2
Allows debugging at the JTAG clock synchronized with
operating clock of CPU by using the(RTCK) signal for
synchronizing the JTAG clock even in the case of the system
in which CPU clock changes for example to Sleep mode.
Semi-hosting feature
*2
The debugger processes standard input/output of the user
program through JTAG. For example, when C library functions
such as printf() and scanf() are executed, they will be
output to Terminal Window of the debugger and keyboard input
will be forwarded to the user program.
This feature processes communication between the user
program and the debugger in real time without causing break
to CPU. Thus, it is perfect for debugging that pursues
realtimeliness.
Program monitoring feature for improving application
performance
*1
*3
By monitoring the state of program execution during the user
application execution to calculate CPU usage rate and
execution rate of the program, and on the basis of the
measured results, the system performance can be improved.
- CPU usage rate execution history display
By referring to CPU usage rate of the user application in
graph, remaining capacity at the time of program execution
can be checked. In the case of multi-core, CPU usage rate of
each core is shown in graph.
- PC watcher display
Presents the execution rate of the user application as a
graph. Measurement of the execution rate can be by function
or OS task/process unit, hence performance can be measured
for the intended purpose. In the case of multi-core, the
execution rate of each core is shown in graph.
Provided with integrated development environment "CSIDE"
Version 5 as standard
Provided with integrated development environment as
standard for seamless implementation of development phases
from creation of the program to debugging.
CPU break feature *1
Allows before-execution
break of the program and access break upon read/write of
data by break logic
incorporated in CPU.
NOR-type flash memory support
Supports debugging features such as software breakpoint
setting and normal memory rewriting, besides downloading to
NOR-type flash memory. Also, new devices can be added easily
by using definition file format.
(For some on-chip flash memories, support is provided
on optional basis.)
Low voltage support and voltage measurement feature *4
Automatically follows the target voltage between 1.0V - 5.5V
in operation. Also, the target (VTref signal) voltage value
can be indicated.
Easy update
By unique internet key issuing system, real-time support
for newly added CPU, update to the latest version, range of
optionally purchased software, etc. has been made feasible.
To assist debugging of the target program using OS, optional
debug library softwares have been prepared for each OS. Use
of the debug library will add features for OS state
indication, program operation check, etc.
µITRON support
By additionally purchasing optional RTOS Debug Library
besides debugger software, task tracing feature and status
display feature for real-time OS will be added.
(Specifications vary by µITRON.)
TOPPERS support
By additionally purchasing optional RTOS Debug Library
besides debugger software, task tracing feature and status
display feature for real-time OS will be added.
T-Kernel, T-Kernel/SE support
By additionally purchasing optional T-Kernel Debug Library
besides debugger software, task tracing feature and status
indication feature for T-Kernel will be added. Also, in the
case of T-Kernel/SE, debugging of multiple processes and
subtasks provided by process management feature is also
supported.
OSE support
By additionally purchasing optional OSE Debug Library
besides debugger software, task tracing feature and status
display feature for OSE will be added.
Operating environment
| Supported host: |
IBM PC/AT compatibles (DOS/V machines) |
| Host I/F: |
USB 2.0 |
| Supported OS: |
Windows 2000
SP4 onward/XP
SP1 onward/Vista |
Connection illustration
- JTAG model
| Supported CPUs |
Product
summary |
Technical
information |
ARM7TDMI,ARM7TDMI-S,ARM7TDMI(Rev.4),
ARM720T,ARM720T(Rev.4),
ARM920T,ARM946E-S,ARM966E-S,
ARM922T,ARM925T,ARM926EJ-S,
ARM1136J-S,ARM1136JF-S,
ARM1156T2-S,ARM1156T2F-S,
ARM1176JZ-S,ARM1176JZF-S, ARM11 MPCore, ARM
Cortex-A8,ARM Cortex-A9 MPCore, ARM Cortex-M3
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For details of specifications, check them in Product
summary and Technical information.
*1: Specifications vary by CPU.
*2: Supported CPUs are ARM7/9/11
cores.
*3: Supported CPUs are ARM11 and
Cortex-M3/A8/A9 cores.
*4: Applicable to hardware
revisions 0-A onward.
In the case of hardware revision 0-0, it supports 1.0V - 3.6V.
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