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PALMiCE2H ARM is a JTAG emulator that supports a range of ARM cores including ARM7/9/11. JTAG model, which allows faster processing of various tasks, and ETM model, which allows by-second tracing with ETM by large-capacity tracing memory incorporated besides faster processing, are available. In ETM model, it made backward execution and back step that are not possible in ordinary execution possible by analyzing the traced contents and thereby retrieving register and memory contents to allow pseudo replication of CPU execution (Trace-back feature). |
The use of innovative debugging approach which simulates program execution results based on the traced data allows effective development of more and more overwhelming and complicated programs.  What is traceback feature?
Feature that retrieves register and memory values by
simulating trace contents and thereby to materialize pseudo execution.
-Allows program execution and step execution
with the traced contents.
Allows to grasp the program operation at a glance based on a few second traced data captured into large-capacity tracing memory.
Deadly focused on practical use, and assures
comfortable usability for handling of large amount of data |
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Easy to target the point since the program operation can be
grasped at a glance. |
Allows to
mark between 2 points and show the execution time interval. |
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Allows saving of traced data into file for repeated analysis
of the once traced data by loading from the file. |
Allows to search just by entering function name to address
column. |
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 Improve the efficiency by interlocking with traceback feature By interlocking traceback feature with CPU Tracing Window, debugging can be performed efficiently.
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Provides multi-core-debugging-specific features such as synchronized execution, synchronized break, status display for watching the state of execution by core and also allows debugging of multiple cores that interlock in operation.
Supports multi-core debugging by 1 unit of PALMiCE2H
Not to mention identical core, debugging can be
performed even for another core.
Supports synchronized execution
and synchronized break
Allows synchronized execution
control if specified in the debugger
setting.
Core-sensitive software break
and hardware break
Software break set on the shared
memory allows to differentiate and
break the break target core.Also, hardware break settings can be specified for individual core since each of them uses its own break feature.
Shows execution state for each
core
Allows to grasp the state of
execution by each core at a glance
in the status bar of the debugger
and also allows prompt switching of
debuggers. Supports AMP(Asymmetric Multi Processor)
Allows independent debugging of each
core since CSIDE can be assigned for
each core.Also allows debugging on the same OS or even on different OS by using the debugging feature incorporated in supported OS.
Support for SMP(Symmetric Multi Processor)
-Under development-
In embedded Linux supporting SMP,
processes are automatically assigned
to each core and controlled, such
that debugging can be performed for
multiple cores just like for single
processor without recognizing it
while doing so. Supported CPUs
Medity series(NEC Electronics-made)MPCore(ARM-made core) -Under development-
Note: Supported specifications vary by CPU. For details, make your inquiry to our sales.
Realizes comfortable debugging operation by high-speed downloading at 1MByte/s or at higher rate and by further speed-up in communication.
High-speed downloading at 1MByte/S or higher rate
Allows downloading via JTAG to the target RAM at
1MByte/S or higher rate thanks to USB
2.0(high-speed) mode support and optimization of
JTAG communication. Also realizes faster processing
of all sorts of commands by speeding up the
communication.
Also supports high-speed JTAG clock *1
Supports JTAG clock up to 60MHz, and therefore, if
CPU allows the use of high-speed JTAG clock, the
performance can be optimized.
High-performance in all points
By unique internet key issuing system, real-time support for newly added CPU, update to the latest version, range of optionally purchased software, etc. has been made feasible.
Adding new CPU
When support is provided for new CPU, debugging of
the CPU can be started right upon acquisition of
debugger software and license file through Internet.
(Some support for adding CPUs are free, while others
are charged.)
Updating to the latest version
When the debugger software has been updated, the
latest version of debugger software can be acquired
through Internet by using CSIDE Update Wizard
(application).
Instant use of range of optional software
Optional software can be used right upon license
acquisition through Internet following the purchase
of the optional software.
CPU break feature *1
| Allows before-execution break of the program and access break of the cache-hit cycle by break logic incorporated in CPU. |
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Semi-hosting feature
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If the target system has not been implemented with input/output
devices such as display, keyboard, and disk, semi-hosting
feature allows the use of input/output devices on the host
instead. For example, when C library functions such as printf() and scanf() are executed, they will be output to Terminal Window of the debugger and keyboard input will be forwarded to the user program. This feature processes communication between the user program and the debugger in real time without causing break to CPU. |
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NOR-type flash memory support
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Supports debugging features such as software breakpoint setting
and normal memory rewriting, besides downloading to NOR-type
flash memory. Also, new devices can be added easily by using
definition file format. (For some on-chip flash memories, support is provided on optional basis.) |
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Provided with integrated development environment "CSIDE" as
standard
| Provided with integrated development environment as standard for seamless implementation of development phases from creation of the program to debugging. |
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Real-time OS support(Optional)
| By additionally purchasing optional RTOS
Debug Library besides debugger software, task tracing feature
and status display feature for real-time OS will be added. (Specifications vary by real-time OS.) |
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Embedded Linux support(Optional)
| Supports multi-process/thread
debugging besides seamless debugging of kernel,
device driver, to application at any phase. (Specifications vary by distribution .) |
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JTAG model, which allows faster processing of various tasks, and ETM model, which allows by-second tracing with ETM by large-capacity tracing memory incorporated besides faster processing, are available.
Main unit models
| ETM383 | JTAG201 | |
|---|---|---|
| Model |
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| Target I/F | 38-pinned MICTOR connector (ETM connector) | 20-pinned connector (JTAG connector) |
| Multi-core debugging | Yes | Yes |
| ETM feature | Yes | No |
| Traceback feature | Yes | No |
Operating environment
| Supported host | : IBM PC/AT compatibles (DOS/V machines) |
| Host I/F | : USB 2.0 |
| Supported OS | : Windows 2000/XP/Vista |
Connection illustration
-ETM model(When connecting with JTAG attached)
-ETM model(When connecting with JTAG detatched)
-JTAG model
ARM family
| Supported CPUs | Product summary | Technical information |
|---|---|---|
| ARM7TDMI,ARM7TDMI-S,ARM720T, ARM920T,ARM946E-S,ARM966E-S, ARM922T,ARM925T,ARM926EJ-S, ARM1136J-S,ARM1136JF-S, ARM1156T2-S,ARM1156T2F-S, ARM1176JZ-S,ARM1176JZF-S |
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JTAG/ETM Normal ETM Multiplexer ETM Demulti Single ARM11 ETM Demulti Single |
For details of specifications check them in
Product summary and Technical information.
*1:Specifications vary by CPU.
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